From fe18894930a025617114aa8ca0adbf94d5bffe89 Mon Sep 17 00:00:00 2001
From: Haibo Chen <haibo.chen@nxp.com>
Date: Mon, 25 Apr 2022 16:41:00 +0800
Subject: [PATCH 0001/1731] iio: mma8452: fix probe fail when device tree
 compatible is used.

Correct the logic for the probe. First check of_match_table, if
not meet, then check i2c_driver.id_table. If both not meet, then
return fail.

Fixes: a47ac019e7e8 ("iio: mma8452: Fix probe failing when an i2c_device_id is used")
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Link: https://lore.kernel.org/r/1650876060-17577-1-git-send-email-haibo.chen@nxp.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/accel/mma8452.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/iio/accel/mma8452.c b/drivers/iio/accel/mma8452.c
index 9c02c681c84c3..4156d216c640a 100644
--- a/drivers/iio/accel/mma8452.c
+++ b/drivers/iio/accel/mma8452.c
@@ -1556,11 +1556,13 @@ static int mma8452_probe(struct i2c_client *client,
 	mutex_init(&data->lock);
 
 	data->chip_info = device_get_match_data(&client->dev);
-	if (!data->chip_info && id) {
-		data->chip_info = &mma_chip_info_table[id->driver_data];
-	} else {
-		dev_err(&client->dev, "unknown device model\n");
-		return -ENODEV;
+	if (!data->chip_info) {
+		if (id) {
+			data->chip_info = &mma_chip_info_table[id->driver_data];
+		} else {
+			dev_err(&client->dev, "unknown device model\n");
+			return -ENODEV;
+		}
 	}
 
 	ret = iio_read_mount_matrix(&client->dev, &data->orientation);
-- 
GitLab


From a5c89f7c43c12c592a882a0ec2a15e9df0011e80 Mon Sep 17 00:00:00 2001
From: Matthew Brost <matthew.brost@intel.com>
Date: Wed, 4 May 2022 16:46:36 -0700
Subject: [PATCH 0002/1731] drm/i915/guc: Support programming the EU priority
 in the GuC descriptor

In GuC submission mode the EU priority must be updated by the GuC rather
than the driver as the GuC owns the programming of the context descriptor.

Given that the GuC code uses the GuC priorities, we can't use a generic
function using i915 priorities for both execlists and GuC submission.
The existing function has therefore been pushed to the execlists
back-end while a new one has been added for GuC.

v2: correctly use the GuC prio.

Cc: John Harrison <john.c.harrison@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220504234636.2119794-1-daniele.ceraolospurio@intel.com
---
 .../drm/i915/gt/intel_execlists_submission.c  | 12 +++++++++-
 drivers/gpu/drm/i915/gt/intel_lrc.h           | 10 ---------
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 22 +++++++++++++++++++
 3 files changed, 33 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 86f7a9ac1c394..2b0266cab66b9 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -661,6 +661,16 @@ static inline void execlists_schedule_out(struct i915_request *rq)
 	i915_request_put(rq);
 }
 
+static u32 map_i915_prio_to_lrc_desc_prio(int prio)
+{
+	if (prio > I915_PRIORITY_NORMAL)
+		return GEN12_CTX_PRIORITY_HIGH;
+	else if (prio < I915_PRIORITY_NORMAL)
+		return GEN12_CTX_PRIORITY_LOW;
+	else
+		return GEN12_CTX_PRIORITY_NORMAL;
+}
+
 static u64 execlists_update_context(struct i915_request *rq)
 {
 	struct intel_context *ce = rq->context;
@@ -669,7 +679,7 @@ static u64 execlists_update_context(struct i915_request *rq)
 
 	desc = ce->lrc.desc;
 	if (rq->engine->flags & I915_ENGINE_HAS_EU_PRIORITY)
-		desc |= lrc_desc_priority(rq_prio(rq));
+		desc |= map_i915_prio_to_lrc_desc_prio(rq_prio(rq));
 
 	/*
 	 * WaIdleLiteRestore:bdw,skl
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h b/drivers/gpu/drm/i915/gt/intel_lrc.h
index 31be734010db3..a390f0813c8b6 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -111,16 +111,6 @@ enum {
 #define XEHP_SW_COUNTER_SHIFT			58
 #define XEHP_SW_COUNTER_WIDTH			6
 
-static inline u32 lrc_desc_priority(int prio)
-{
-	if (prio > I915_PRIORITY_NORMAL)
-		return GEN12_CTX_PRIORITY_HIGH;
-	else if (prio < I915_PRIORITY_NORMAL)
-		return GEN12_CTX_PRIORITY_LOW;
-	else
-		return GEN12_CTX_PRIORITY_NORMAL;
-}
-
 static inline void lrc_runtime_start(struct intel_context *ce)
 {
 	struct intel_context_stats *stats = &ce->stats;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 75291e9846c50..8bf8b6d588d43 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2394,6 +2394,26 @@ static int guc_context_policy_init(struct intel_context *ce, bool loop)
 	return ret;
 }
 
+static u32 map_guc_prio_to_lrc_desc_prio(u8 prio)
+{
+	/*
+	 * this matches the mapping we do in map_i915_prio_to_guc_prio()
+	 * (e.g. prio < I915_PRIORITY_NORMAL maps to GUC_CLIENT_PRIORITY_NORMAL)
+	 */
+	switch (prio) {
+	default:
+		MISSING_CASE(prio);
+		fallthrough;
+	case GUC_CLIENT_PRIORITY_KMD_NORMAL:
+		return GEN12_CTX_PRIORITY_NORMAL;
+	case GUC_CLIENT_PRIORITY_NORMAL:
+		return GEN12_CTX_PRIORITY_LOW;
+	case GUC_CLIENT_PRIORITY_HIGH:
+	case GUC_CLIENT_PRIORITY_KMD_HIGH:
+		return GEN12_CTX_PRIORITY_HIGH;
+	}
+}
+
 static void prepare_context_registration_info(struct intel_context *ce,
 					      struct guc_ctxt_registration_info *info)
 {
@@ -2420,6 +2440,8 @@ static void prepare_context_registration_info(struct intel_context *ce,
 	 */
 	info->hwlrca_lo = lower_32_bits(ce->lrc.lrca);
 	info->hwlrca_hi = upper_32_bits(ce->lrc.lrca);
+	if (engine->flags & I915_ENGINE_HAS_EU_PRIORITY)
+		info->hwlrca_lo |= map_guc_prio_to_lrc_desc_prio(ce->guc_state.prio);
 	info->flags = CONTEXT_REGISTRATION_FLAG_KMD;
 
 	/*
-- 
GitLab


From 315241d2d9102a90f71bd6c9e7dd06a1c831a184 Mon Sep 17 00:00:00 2001
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Date: Wed, 4 May 2022 13:48:13 -0700
Subject: [PATCH 0003/1731] drm/i915/huc: drop intel_huc_is_authenticated

The function name is confusing, because it doesn't check the actual auth
status in HW but the SW status. Given that there is only one user (the
huc_auth function itself), just get rid of it and use the FW status
checker directly.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220504204816.2082588-2-daniele.ceraolospurio@intel.com
---
 drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
 drivers/gpu/drm/i915/gt/uc/intel_huc.h | 5 -----
 2 files changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 556829de9c172..7b759b99cf3c8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -96,7 +96,7 @@ int intel_huc_auth(struct intel_huc *huc)
 	struct intel_guc *guc = &gt->uc.guc;
 	int ret;
 
-	GEM_BUG_ON(intel_huc_is_authenticated(huc));
+	GEM_BUG_ON(intel_uc_fw_is_running(&huc->fw));
 
 	if (!intel_uc_fw_is_loaded(&huc->fw))
 		return -ENOEXEC;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index 73ec670800f2b..77d813840d76c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -50,11 +50,6 @@ static inline bool intel_huc_is_used(struct intel_huc *huc)
 	return intel_uc_fw_is_available(&huc->fw);
 }
 
-static inline bool intel_huc_is_authenticated(struct intel_huc *huc)
-{
-	return intel_uc_fw_is_running(&huc->fw);
-}
-
 void intel_huc_load_status(struct intel_huc *huc, struct drm_printer *p);
 
 #endif
-- 
GitLab


From a7b516bd981f11feb0c9f5ee3d149855d48cb2c8 Mon Sep 17 00:00:00 2001
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Date: Wed, 4 May 2022 13:48:14 -0700
Subject: [PATCH 0004/1731] drm/i915/huc: Add fetch support for gsc-loaded HuC
 binary

On newer platforms (starting DG2 G10 B-step and G11 A-step), ownership of
HuC loading has been moved from the GuC to the GSC. As part of the
change, the header format of the HuC binary has been updated and does not
match the GuC anymore. The GSC will perform all the required checks on
the binary size, so we only need to check that the version matches.

Note that since we still haven't added any gsc-loaded FWs, the
loaded_via_gsc variable will always be kept to its initialization value
of zero.

v2: Add a note about loaded_via_gsc being zero (Alan)

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220504204816.2082588-3-daniele.ceraolospurio@intel.com
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c     | 99 ++++++++++++--------
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h     |  2 +
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h |  9 ++
 3 files changed, 72 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index d078f884b5e32..9361532726d6c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -301,45 +301,31 @@ static void __force_fw_fetch_failures(struct intel_uc_fw *uc_fw, int e)
 	}
 }
 
-/**
- * intel_uc_fw_fetch - fetch uC firmware
- * @uc_fw: uC firmware
- *
- * Fetch uC firmware into GEM obj.
- *
- * Return: 0 on success, a negative errno code on failure.
- */
-int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
+static int check_gsc_manifest(const struct firmware *fw,
+			      struct intel_uc_fw *uc_fw)
 {
-	struct drm_i915_private *i915 = __uc_fw_to_gt(uc_fw)->i915;
-	struct device *dev = i915->drm.dev;
-	struct drm_i915_gem_object *obj;
-	const struct firmware *fw = NULL;
-	struct uc_css_header *css;
-	size_t size;
-	int err;
+	u32 *dw = (u32 *)fw->data;
+	u32 version = dw[HUC_GSC_VERSION_DW];
 
-	GEM_BUG_ON(!i915->wopcm.size);
-	GEM_BUG_ON(!intel_uc_fw_is_enabled(uc_fw));
-
-	err = i915_inject_probe_error(i915, -ENXIO);
-	if (err)
-		goto fail;
+	uc_fw->major_ver_found = FIELD_GET(HUC_GSC_MAJOR_VER_MASK, version);
+	uc_fw->minor_ver_found = FIELD_GET(HUC_GSC_MINOR_VER_MASK, version);
 
-	__force_fw_fetch_failures(uc_fw, -EINVAL);
-	__force_fw_fetch_failures(uc_fw, -ESTALE);
+	return 0;
+}
 
-	err = request_firmware(&fw, uc_fw->path, dev);
-	if (err)
-		goto fail;
+static int check_ccs_header(struct drm_i915_private *i915,
+			    const struct firmware *fw,
+			    struct intel_uc_fw *uc_fw)
+{
+	struct uc_css_header *css;
+	size_t size;
 
 	/* Check the size of the blob before examining buffer contents */
 	if (unlikely(fw->size < sizeof(struct uc_css_header))) {
 		drm_warn(&i915->drm, "%s firmware %s: invalid size: %zu < %zu\n",
 			 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path,
 			 fw->size, sizeof(struct uc_css_header));
-		err = -ENODATA;
-		goto fail;
+		return -ENODATA;
 	}
 
 	css = (struct uc_css_header *)fw->data;
@@ -352,8 +338,7 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
 			 "%s firmware %s: unexpected header size: %zu != %zu\n",
 			 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path,
 			 fw->size, sizeof(struct uc_css_header));
-		err = -EPROTO;
-		goto fail;
+		return -EPROTO;
 	}
 
 	/* uCode size must calculated from other sizes */
@@ -368,8 +353,7 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
 		drm_warn(&i915->drm, "%s firmware %s: invalid size: %zu < %zu\n",
 			 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path,
 			 fw->size, size);
-		err = -ENOEXEC;
-		goto fail;
+		return -ENOEXEC;
 	}
 
 	/* Sanity check whether this fw is not larger than whole WOPCM memory */
@@ -378,8 +362,7 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
 		drm_warn(&i915->drm, "%s firmware %s: invalid size: %zu > %zu\n",
 			 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path,
 			 size, (size_t)i915->wopcm.size);
-		err = -E2BIG;
-		goto fail;
+		return -E2BIG;
 	}
 
 	/* Get version numbers from the CSS header */
@@ -388,6 +371,49 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
 	uc_fw->minor_ver_found = FIELD_GET(CSS_SW_VERSION_UC_MINOR,
 					   css->sw_version);
 
+	if (uc_fw->type == INTEL_UC_FW_TYPE_GUC)
+		uc_fw->private_data_size = css->private_data_size;
+
+	return 0;
+}
+
+/**
+ * intel_uc_fw_fetch - fetch uC firmware
+ * @uc_fw: uC firmware
+ *
+ * Fetch uC firmware into GEM obj.
+ *
+ * Return: 0 on success, a negative errno code on failure.
+ */
+int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
+{
+	struct drm_i915_private *i915 = __uc_fw_to_gt(uc_fw)->i915;
+	struct device *dev = i915->drm.dev;
+	struct drm_i915_gem_object *obj;
+	const struct firmware *fw = NULL;
+	int err;
+
+	GEM_BUG_ON(!i915->wopcm.size);
+	GEM_BUG_ON(!intel_uc_fw_is_enabled(uc_fw));
+
+	err = i915_inject_probe_error(i915, -ENXIO);
+	if (err)
+		goto fail;
+
+	__force_fw_fetch_failures(uc_fw, -EINVAL);
+	__force_fw_fetch_failures(uc_fw, -ESTALE);
+
+	err = request_firmware(&fw, uc_fw->path, dev);
+	if (err)
+		goto fail;
+
+	if (uc_fw->loaded_via_gsc)
+		err = check_gsc_manifest(fw, uc_fw);
+	else
+		err = check_ccs_header(i915, fw, uc_fw);
+	if (err)
+		goto fail;
+
 	if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
 	    uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
 		drm_notice(&i915->drm, "%s firmware %s: unexpected version: %u.%u != %u.%u\n",
@@ -400,9 +426,6 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
 		}
 	}
 
-	if (uc_fw->type == INTEL_UC_FW_TYPE_GUC)
-		uc_fw->private_data_size = css->private_data_size;
-
 	if (HAS_LMEM(i915)) {
 		obj = i915_gem_object_create_lmem_from_data(i915, fw->data, fw->size);
 		if (!IS_ERR(obj))
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
index 3229018877d3d..4f169035f5041 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
@@ -102,6 +102,8 @@ struct intel_uc_fw {
 	u32 ucode_size;
 
 	u32 private_data_size;
+
+	bool loaded_via_gsc;
 };
 
 #ifdef CONFIG_DRM_I915_DEBUG_GUC
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
index e41ffc7a7fbcb..b05e0e35b734c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
@@ -39,6 +39,11 @@
  * 3. Length info of each component can be found in header, in dwords.
  * 4. Modulus and exponent key are not required by driver. They may not appear
  *    in fw. So driver will load a truncated firmware in this case.
+ *
+ * Starting from DG2, the HuC is loaded by the GSC instead of i915. The GSC
+ * firmware performs all the required integrity checks, we just need to check
+ * the version. Note that the header for GSC-managed blobs is different from the
+ * CSS used for dma-loaded firmwares.
  */
 
 struct uc_css_header {
@@ -78,4 +83,8 @@ struct uc_css_header {
 } __packed;
 static_assert(sizeof(struct uc_css_header) == 128);
 
+#define HUC_GSC_VERSION_DW		44
+#define   HUC_GSC_MAJOR_VER_MASK	(0xFF << 0)
+#define   HUC_GSC_MINOR_VER_MASK	(0xFF << 16)
+
 #endif /* _INTEL_UC_FW_ABI_H */
-- 
GitLab


From 6f67930af78f10ac7a1a9ba81ec606a9bd07749f Mon Sep 17 00:00:00 2001
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Date: Wed, 4 May 2022 13:48:15 -0700
Subject: [PATCH 0005/1731] drm/i915/huc: Prepare for GSC-loaded HuC

HuC loading via GSC is performed via a PXP command sent through the mei
modules, so we need both MEI_GSC and MEI_PXP to be available. Given that
the GSC will do both the transfer and the authentication, the legacy HuC
loading paths can be safely skipped.
Also note that the GSC-loaded HuC survives GT reset.

v2: move the huc_is_authenticated() function to this patch.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220504204816.2082588-4-daniele.ceraolospurio@intel.com
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h |  1 +
 drivers/gpu/drm/i915/gt/uc/intel_huc.c     | 95 ++++++++++++++++++----
 drivers/gpu/drm/i915/gt/uc/intel_huc.h     |  6 ++
 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c  |  5 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c      | 11 ++-
 5 files changed, 100 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
index 66027a42cda9e..2516705b9f365 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
@@ -96,6 +96,7 @@
 
 #define GUC_SHIM_CONTROL2		_MMIO(0xc068)
 #define   GUC_IS_PRIVILEGED		(1<<29)
+#define   GSC_LOADS_HUC			(1<<30)
 
 #define GUC_SEND_INTERRUPT		_MMIO(0xc4c8)
 #define   GUC_SEND_TRIGGER		  (1<<0)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 7b759b99cf3c8..c36e2bf9b0f29 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -6,6 +6,7 @@
 #include <linux/types.h>
 
 #include "gt/intel_gt.h"
+#include "intel_guc_reg.h"
 #include "intel_huc.h"
 #include "i915_drv.h"
 
@@ -17,11 +18,15 @@
  * capabilities by adding HuC specific commands to batch buffers.
  *
  * The kernel driver is only responsible for loading the HuC firmware and
- * triggering its security authentication, which is performed by the GuC. For
- * The GuC to correctly perform the authentication, the HuC binary must be
- * loaded before the GuC one. Loading the HuC is optional; however, not using
- * the HuC might negatively impact power usage and/or performance of media
- * workloads, depending on the use-cases.
+ * triggering its security authentication, which is performed by the GuC on
+ * older platforms and by the GSC on newer ones. For the GuC to correctly
+ * perform the authentication, the HuC binary must be loaded before the GuC one.
+ * Loading the HuC is optional; however, not using the HuC might negatively
+ * impact power usage and/or performance of media workloads, depending on the
+ * use-cases.
+ * HuC must be reloaded on events that cause the WOPCM to lose its contents
+ * (S3/S4, FLR); GuC-authenticated HuC must also be reloaded on GuC/GT reset,
+ * while GSC-managed HuC will survive that.
  *
  * See https://github.com/intel/media-driver for the latest details on HuC
  * functionality.
@@ -54,11 +59,51 @@ void intel_huc_init_early(struct intel_huc *huc)
 	}
 }
 
+#define HUC_LOAD_MODE_STRING(x) (x ? "GSC" : "legacy")
+static int check_huc_loading_mode(struct intel_huc *huc)
+{
+	struct intel_gt *gt = huc_to_gt(huc);
+	bool fw_needs_gsc = intel_huc_is_loaded_by_gsc(huc);
+	bool hw_uses_gsc = false;
+
+	/*
+	 * The fuse for HuC load via GSC is only valid on platforms that have
+	 * GuC deprivilege.
+	 */
+	if (HAS_GUC_DEPRIVILEGE(gt->i915))
+		hw_uses_gsc = intel_uncore_read(gt->uncore, GUC_SHIM_CONTROL2) &
+			      GSC_LOADS_HUC;
+
+	if (fw_needs_gsc != hw_uses_gsc) {
+		drm_err(&gt->i915->drm,
+			"mismatch between HuC FW (%s) and HW (%s) load modes\n",
+			HUC_LOAD_MODE_STRING(fw_needs_gsc),
+			HUC_LOAD_MODE_STRING(hw_uses_gsc));
+		return -ENOEXEC;
+	}
+
+	/* make sure we can access the GSC via the mei driver if we need it */
+	if (!(IS_ENABLED(CONFIG_INTEL_MEI_PXP) && IS_ENABLED(CONFIG_INTEL_MEI_GSC)) &&
+	    fw_needs_gsc) {
+		drm_info(&gt->i915->drm,
+			 "Can't load HuC due to missing MEI modules\n");
+		return -EIO;
+	}
+
+	drm_dbg(&gt->i915->drm, "GSC loads huc=%s\n", str_yes_no(fw_needs_gsc));
+
+	return 0;
+}
+
 int intel_huc_init(struct intel_huc *huc)
 {
 	struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
 	int err;
 
+	err = check_huc_loading_mode(huc);
+	if (err)
+		goto out;
+
 	err = intel_uc_fw_init(&huc->fw);
 	if (err)
 		goto out;
@@ -96,17 +141,20 @@ int intel_huc_auth(struct intel_huc *huc)
 	struct intel_guc *guc = &gt->uc.guc;
 	int ret;
 
-	GEM_BUG_ON(intel_uc_fw_is_running(&huc->fw));
-
 	if (!intel_uc_fw_is_loaded(&huc->fw))
 		return -ENOEXEC;
 
+	/* GSC will do the auth */
+	if (intel_huc_is_loaded_by_gsc(huc))
+		return -ENODEV;
+
 	ret = i915_inject_probe_error(gt->i915, -ENXIO);
 	if (ret)
 		goto fail;
 
-	ret = intel_guc_auth_huc(guc,
-				 intel_guc_ggtt_offset(guc, huc->fw.rsa_data));
+	GEM_BUG_ON(intel_uc_fw_is_running(&huc->fw));
+
+	ret = intel_guc_auth_huc(guc, intel_guc_ggtt_offset(guc, huc->fw.rsa_data));
 	if (ret) {
 		DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
 		goto fail;
@@ -133,6 +181,18 @@ fail:
 	return ret;
 }
 
+static bool huc_is_authenticated(struct intel_huc *huc)
+{
+	struct intel_gt *gt = huc_to_gt(huc);
+	intel_wakeref_t wakeref;
+	u32 status = 0;
+
+	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+		status = intel_uncore_read(gt->uncore, huc->status.reg);
+
+	return (status & huc->status.mask) == huc->status.value;
+}
+
 /**
  * intel_huc_check_status() - check HuC status
  * @huc: intel_huc structure
@@ -150,10 +210,6 @@ fail:
  */
 int intel_huc_check_status(struct intel_huc *huc)
 {
-	struct intel_gt *gt = huc_to_gt(huc);
-	intel_wakeref_t wakeref;
-	u32 status = 0;
-
 	switch (__intel_uc_fw_status(&huc->fw)) {
 	case INTEL_UC_FIRMWARE_NOT_SUPPORTED:
 		return -ENODEV;
@@ -167,10 +223,17 @@ int intel_huc_check_status(struct intel_huc *huc)
 		break;
 	}
 
-	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
-		status = intel_uncore_read(gt->uncore, huc->status.reg);
+	return huc_is_authenticated(huc);
+}
 
-	return (status & huc->status.mask) == huc->status.value;
+void intel_huc_update_auth_status(struct intel_huc *huc)
+{
+	if (!intel_uc_fw_is_loadable(&huc->fw))
+		return;
+
+	if (huc_is_authenticated(huc))
+		intel_uc_fw_change_status(&huc->fw,
+					  INTEL_UC_FIRMWARE_RUNNING);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index 77d813840d76c..d7e25b6e879eb 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -27,6 +27,7 @@ int intel_huc_init(struct intel_huc *huc);
 void intel_huc_fini(struct intel_huc *huc);
 int intel_huc_auth(struct intel_huc *huc);
 int intel_huc_check_status(struct intel_huc *huc);
+void intel_huc_update_auth_status(struct intel_huc *huc);
 
 static inline int intel_huc_sanitize(struct intel_huc *huc)
 {
@@ -50,6 +51,11 @@ static inline bool intel_huc_is_used(struct intel_huc *huc)
 	return intel_uc_fw_is_available(&huc->fw);
 }
 
+static inline bool intel_huc_is_loaded_by_gsc(const struct intel_huc *huc)
+{
+	return huc->fw.loaded_via_gsc;
+}
+
 void intel_huc_load_status(struct intel_huc *huc, struct drm_printer *p);
 
 #endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index e5ef509c70e89..9d6ab1e016395 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -8,7 +8,7 @@
 #include "i915_drv.h"
 
 /**
- * intel_huc_fw_upload() - load HuC uCode to device
+ * intel_huc_fw_upload() - load HuC uCode to device via DMA transfer
  * @huc: intel_huc structure
  *
  * Called from intel_uc_init_hw() during driver load, resume from sleep and
@@ -21,6 +21,9 @@
  */
 int intel_huc_fw_upload(struct intel_huc *huc)
 {
+	if (intel_huc_is_loaded_by_gsc(huc))
+		return -ENODEV;
+
 	/* HW doesn't look at destination address for HuC, so set it to 0 */
 	return intel_uc_fw_upload(&huc->fw, 0, HUC_UKERNEL);
 }
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 8c9ef690ac9d8..0dce94f896a8c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -509,7 +509,16 @@ static int __uc_init_hw(struct intel_uc *uc)
 	if (ret)
 		goto err_log_capture;
 
-	intel_huc_auth(huc);
+	/*
+	 * GSC-loaded HuC is authenticated by the GSC, so we don't need to
+	 * trigger the auth here. However, given that the HuC loaded this way
+	 * survive GT reset, we still need to update our SW bookkeeping to make
+	 * sure it reflects the correct HW status.
+	 */
+	if (intel_huc_is_loaded_by_gsc(huc))
+		intel_huc_update_auth_status(huc);
+	else
+		intel_huc_auth(huc);
 
 	if (intel_uc_uses_guc_submission(uc))
 		intel_guc_submission_enable(guc);
-- 
GitLab


From 56ca3117f77a23a8b24e73e458bc85c11e5dea31 Mon Sep 17 00:00:00 2001
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Date: Wed, 4 May 2022 13:48:16 -0700
Subject: [PATCH 0006/1731] drm/i915/huc: Don't fail the probe if HuC init
 fails

The previous patch introduced new failure cases in the HuC init flow
that can be hit by simply changing the config, so we want to avoid
failing the probe in those scenarios. HuC load failure is already
considered a non-fatal error and we have a way to report to userspace
if the HuC is not available via a dedicated getparam, so no changes
in expectation there.
The error message in the HuC init code has also been lowered to info to
avoid throwing error message for an expected behavior.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220504204816.2082588-5-daniele.ceraolospurio@intel.com
---
 drivers/gpu/drm/i915/gt/uc/intel_huc.c |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c  | 11 ++---------
 2 files changed, 3 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index c36e2bf9b0f29..3bb8838e325a4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -113,7 +113,7 @@ int intel_huc_init(struct intel_huc *huc)
 	return 0;
 
 out:
-	i915_probe_error(i915, "failed with %d\n", err);
+	drm_info(&i915->drm, "HuC init failed with %d\n", err);
 	return err;
 }
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 0dce94f896a8c..ecf149c5fdb02 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -323,17 +323,10 @@ static int __uc_init(struct intel_uc *uc)
 	if (ret)
 		return ret;
 
-	if (intel_uc_uses_huc(uc)) {
-		ret = intel_huc_init(huc);
-		if (ret)
-			goto out_guc;
-	}
+	if (intel_uc_uses_huc(uc))
+		intel_huc_init(huc);
 
 	return 0;
-
-out_guc:
-	intel_guc_fini(guc);
-	return ret;
 }
 
 static void __uc_fini(struct intel_uc *uc)
-- 
GitLab


From e6c2db2be986158afb9991d9fa8a38fe65a88516 Mon Sep 17 00:00:00 2001
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date: Thu, 5 May 2022 12:00:06 +0100
Subject: [PATCH 0007/1731] drm/i915: Don't use DRM_DEBUG_WARN_ON for
 unexpected l3bank/mslice config

DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
to exercise a certain code path, so in case of values coming from MMIO
reads we cannot be sure CI will have all the possible SKUs and parts.

Use drm_warn instead and move logging to init phase while at it.

v2:
 * GEM_WARN_ON in intel_gt_get_valid_steering.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505110007.943449-1-tvrtko.ursulin@linux.intel.com
---
 drivers/gpu/drm/i915/gt/intel_gt.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 53307ca0eed0c..034182f85501b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -153,11 +153,14 @@ int intel_gt_init_mmio(struct intel_gt *gt)
 	 * An mslice is unavailable only if both the meml3 for the slice is
 	 * disabled *and* all of the DSS in the slice (quadrant) are disabled.
 	 */
-	if (HAS_MSLICES(i915))
+	if (HAS_MSLICES(i915)) {
 		gt->info.mslice_mask =
 			slicemask(gt, GEN_DSS_PER_MSLICE) |
 			(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
 			 GEN12_MEML3_EN_MASK);
+		if (!gt->info.mslice_mask) /* should be impossible! */
+			drm_warn(&i915->drm, "mslice mask all zero!\n");
+	}
 
 	if (IS_DG2(i915)) {
 		gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
@@ -171,6 +174,8 @@ int intel_gt_init_mmio(struct intel_gt *gt)
 		gt->info.l3bank_mask =
 			~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
 			GEN10_L3BANK_MASK;
+		if (!gt->info.l3bank_mask) /* should be impossible! */
+			drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
 	} else if (HAS_MSLICES(i915)) {
 		MISSING_CASE(INTEL_INFO(i915)->platform);
 	}
@@ -882,24 +887,20 @@ static void intel_gt_get_valid_steering(struct intel_gt *gt,
 {
 	switch (type) {
 	case L3BANK:
-		GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be impossible! */
-
 		*sliceid = 0;		/* unused */
 		*subsliceid = __ffs(gt->info.l3bank_mask);
 		break;
 	case MSLICE:
-		GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
-
+		GEM_WARN_ON(!HAS_MSLICES(gt->i915));
 		*sliceid = __ffs(gt->info.mslice_mask);
 		*subsliceid = 0;	/* unused */
 		break;
 	case LNCF:
-		GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
-
 		/*
 		 * An LNCF is always present if its mslice is present, so we
 		 * can safely just steer to LNCF 0 in all cases.
 		 */
+		GEM_WARN_ON(!HAS_MSLICES(gt->i915));
 		*sliceid = __ffs(gt->info.mslice_mask) << 1;
 		*subsliceid = 0;	/* unused */
 		break;
-- 
GitLab


From 91875c22a31be0bdf91d7ec651bb6b083b35ac37 Mon Sep 17 00:00:00 2001
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date: Thu, 5 May 2022 12:00:07 +0100
Subject: [PATCH 0008/1731] drm/i915: Don't use DRM_DEBUG_WARN_ON for ring
 unexpectedly not idle

DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
to exercise a certain code path, so in case of values coming from MMIO
reads we cannot be sure CI will have all the possible SKUs and parts, or
that it will catch all possible error conditions. Use drm_warn instead.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505110007.943449-2-tvrtko.ursulin@linux.intel.com
---
 drivers/gpu/drm/i915/gt/intel_ring_submission.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 5423bfd301adf..f8f279a195c0c 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -117,7 +117,9 @@ static void flush_cs_tlb(struct intel_engine_cs *engine)
 		return;
 
 	/* ring should be idle before issuing a sync flush*/
-	GEM_DEBUG_WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
+	if ((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0)
+		drm_warn(&engine->i915->drm, "%s not idle before sync flush!\n",
+			 engine->name);
 
 	ENGINE_WRITE_FW(engine, RING_INSTPM,
 			_MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
-- 
GitLab


From 09708b6d82ef473de91c49d90f35e38b0db463f5 Mon Sep 17 00:00:00 2001
From: YueHaibing <yuehaibing@huawei.com>
Date: Fri, 6 May 2022 11:26:52 +0800
Subject: [PATCH 0009/1731] drm/i915/gt: Fix build error without CONFIG_PM
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c: In function ‘act_freq_mhz_show’:
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:276:20: error: implicit declaration of function ‘sysfs_gt_attribute_r_max_func’ [-Werror=implicit-function-declaration]
  276 |  u32 actual_freq = sysfs_gt_attribute_r_max_func(dev, attr,
      |                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Move sysfs_gt_attribute_* macros out of #ifdef block to fix this.

Fixes: 56a709cf7746 ("drm/i915/gt: Create per-tile RPS sysfs interfaces")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220506032652.1856-1-yuehaibing@huawei.com
---
 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 26cbfa6477d12..e92990d514b24 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -17,7 +17,6 @@
 #include "intel_rc6.h"
 #include "intel_rps.h"
 
-#ifdef CONFIG_PM
 enum intel_gt_sysfs_op {
 	INTEL_GT_SYSFS_MIN = 0,
 	INTEL_GT_SYSFS_MAX,
@@ -92,6 +91,7 @@ sysfs_gt_attribute_r_func(struct device *dev, struct device_attribute *attr,
 #define sysfs_gt_attribute_r_max_func(d, a, f) \
 		sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX)
 
+#ifdef CONFIG_PM
 static u32 get_residency(struct intel_gt *gt, i915_reg_t reg)
 {
 	intel_wakeref_t wakeref;
-- 
GitLab


From 222ff6db8a0dcb86f2bb65fc8656aec635a737a6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com>
Date: Thu, 5 May 2022 12:35:18 -0700
Subject: [PATCH 0010/1731] drm/i915: Drop has_gt_uc from device info
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

No need to have this parameter in intel_device_info struct
as all platforms with graphics version 9 or newer has graphics
microcontroller.

As a side effect of the of removal this flag, it will not be printed
in dmesg during driver load anymore and developers will have to rely
on to check the macro and compare with platform being used and IP
versions of it.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505193524.276400-1-jose.souza@intel.com
---
 drivers/gpu/drm/i915/i915_drv.h          | 2 +-
 drivers/gpu/drm/i915/i915_gpu_error.c    | 2 +-
 drivers/gpu/drm/i915/i915_pci.c          | 3 ---
 drivers/gpu/drm/i915/intel_device_info.h | 1 -
 4 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3ed9021c615d2..d71ed8d272c55 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1350,7 +1350,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
  */
 #define HAS_FLAT_CCS(dev_priv)   (INTEL_INFO(dev_priv)->has_flat_ccs)
 
-#define HAS_GT_UC(dev_priv)	(INTEL_INFO(dev_priv)->has_gt_uc)
+#define HAS_GT_UC(dev_priv)	(GRAPHICS_VER(dev_priv) >= 9)
 
 #define HAS_POOLED_EU(dev_priv)	(INTEL_INFO(dev_priv)->has_pooled_eu)
 
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 0512c66fa4f3f..5bd9cb8998527 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -2008,7 +2008,7 @@ __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 du
 			return ERR_PTR(-ENOMEM);
 		}
 
-		if (INTEL_INFO(i915)->has_gt_uc) {
+		if (HAS_GT_UC(i915)) {
 			error->gt->uc = gt_record_uc(error->gt, compress);
 			if (error->gt->uc) {
 				if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 987bdeb090a51..a5f09a2f7472f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -644,7 +644,6 @@ static const struct intel_device_info chv_info = {
 	GEN(9), \
 	GEN9_DEFAULT_PAGE_SIZES, \
 	.display.has_dmc = 1, \
-	.has_gt_uc = 1, \
 	.display.has_hdcp = 1, \
 	.display.has_ipc = 1, \
 	.display.has_psr = 1, \
@@ -705,7 +704,6 @@ static const struct intel_device_info skl_gt4_info = {
 	.has_rps = true, \
 	.display.has_dp_mst = 1, \
 	.has_logical_ring_contexts = 1, \
-	.has_gt_uc = 1, \
 	.dma_mask_size = 39, \
 	.ppgtt_type = INTEL_PPGTT_FULL, \
 	.ppgtt_size = 48, \
@@ -1008,7 +1006,6 @@ static const struct intel_device_info adl_p_info = {
 	.has_64bit_reloc = 1, \
 	.has_flat_ccs = 1, \
 	.has_global_mocs = 1, \
-	.has_gt_uc = 1, \
 	.has_llc = 1, \
 	.has_logical_ring_contexts = 1, \
 	.has_logical_ring_elsq = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index ec0b8095e7fa3..93396c49488c0 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -141,7 +141,6 @@ enum intel_ppgtt_type {
 	func(has_4tile); \
 	func(has_flat_ccs); \
 	func(has_global_mocs); \
-	func(has_gt_uc); \
 	func(has_heci_pxp); \
 	func(has_heci_gscfi); \
 	func(has_guc_deprivilege); \
-- 
GitLab


From 218076abbcd647de46635d21331a34b814f90906 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com>
Date: Thu, 5 May 2022 12:35:19 -0700
Subject: [PATCH 0011/1731] drm/i915: Drop has_rc6 from device info
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

No need to have this parameter in intel_device_info struct
as all platforms with graphics version 6 or newer have software
support for this feature.

As a side effect of the of removal this flag, it will not be printed
in dmesg during driver load anymore and developers will have to rely
on to check the macro and compare with platform being used and IP
versions of it.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505193524.276400-2-jose.souza@intel.com
---
 drivers/gpu/drm/i915/i915_drv.h          | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c          | 8 --------
 drivers/gpu/drm/i915/intel_device_info.h | 1 -
 3 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d71ed8d272c55..8f48c3d906455 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1302,7 +1302,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_PSR2_SEL_FETCH(dev_priv)	 (DISPLAY_VER(dev_priv) >= 12)
 #define HAS_TRANSCODER(dev_priv, trans)	 ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)
 
-#define HAS_RC6(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6)
+/* ilk does support rc6, but we do not implement [power] contexts */
+#define HAS_RC6(dev_priv)		 (GRAPHICS_VER(dev_priv) >= 6)
 #define HAS_RC6p(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6p)
 #define HAS_RC6pp(dev_priv)		 (false) /* HW was never validated */
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a5f09a2f7472f..1973d8e047f0f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -376,8 +376,6 @@ static const struct intel_device_info gm45_info = {
 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
 	.has_snoop = true, \
 	.has_coherent_ggtt = true, \
-	/* ilk does support rc6, but we do not implement [power] contexts */ \
-	.has_rc6 = 0, \
 	.dma_mask_size = 36, \
 	I9XX_PIPE_OFFSETS, \
 	I9XX_CURSOR_OFFSETS, \
@@ -407,7 +405,6 @@ static const struct intel_device_info ilk_m_info = {
 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 	.has_coherent_ggtt = true, \
 	.has_llc = 1, \
-	.has_rc6 = 1, \
 	.has_rc6p = 1, \
 	.has_rps = true, \
 	.dma_mask_size = 40, \
@@ -458,7 +455,6 @@ static const struct intel_device_info snb_m_gt2_info = {
 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 	.has_coherent_ggtt = true, \
 	.has_llc = 1, \
-	.has_rc6 = 1, \
 	.has_rc6p = 1, \
 	.has_reset_engine = true, \
 	.has_rps = true, \
@@ -518,7 +514,6 @@ static const struct intel_device_info vlv_info = {
 	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
 	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
 	.has_runtime_pm = 1,
-	.has_rc6 = 1,
 	.has_reset_engine = true,
 	.has_rps = true,
 	.display.has_gmch = 1,
@@ -617,7 +612,6 @@ static const struct intel_device_info chv_info = {
 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
 	.has_64bit_reloc = 1,
 	.has_runtime_pm = 1,
-	.has_rc6 = 1,
 	.has_rps = true,
 	.has_logical_ring_contexts = 1,
 	.display.has_gmch = 1,
@@ -700,7 +694,6 @@ static const struct intel_device_info skl_gt4_info = {
 	.display.has_psr_hw_tracking = 1, \
 	.has_runtime_pm = 1, \
 	.display.has_dmc = 1, \
-	.has_rc6 = 1, \
 	.has_rps = true, \
 	.display.has_dp_mst = 1, \
 	.has_logical_ring_contexts = 1, \
@@ -1010,7 +1003,6 @@ static const struct intel_device_info adl_p_info = {
 	.has_logical_ring_contexts = 1, \
 	.has_logical_ring_elsq = 1, \
 	.has_mslices = 1, \
-	.has_rc6 = 1, \
 	.has_reset_engine = 1, \
 	.has_rps = 1, \
 	.has_runtime_pm = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 93396c49488c0..68af6f89a3661 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -151,7 +151,6 @@ enum intel_ppgtt_type {
 	func(has_mslices); \
 	func(has_pooled_eu); \
 	func(has_pxp); \
-	func(has_rc6); \
 	func(has_rc6p); \
 	func(has_rps); \
 	func(has_runtime_pm); \
-- 
GitLab


From 922abe4d19bd21b38298f3902674774b92a49293 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com>
Date: Thu, 5 May 2022 12:35:20 -0700
Subject: [PATCH 0012/1731] drm/i915: Drop has_reset_engine from device info
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

No need to have this parameter in intel_device_info struct
as all platforms with graphics version 7 or newer can reset engines.

As a side effect of the of removal this flag, it will not be printed
in dmesg during driver load anymore and developers will have to rely
on to check the macro and compare with platform being used and IP
versions of it.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505193524.276400-3-jose.souza@intel.com
---
 drivers/gpu/drm/i915/gt/intel_reset.c    | 2 +-
 drivers/gpu/drm/i915/i915_pci.c          | 5 -----
 drivers/gpu/drm/i915/intel_device_info.h | 1 -
 3 files changed, 1 insertion(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 5422a3b84bd44..894f17f8b4cea 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -699,7 +699,7 @@ bool intel_has_reset_engine(const struct intel_gt *gt)
 	if (gt->i915->params.reset < 2)
 		return false;
 
-	return INTEL_INFO(gt->i915)->has_reset_engine;
+	return GRAPHICS_VER(gt->i915) >= 7;
 }
 
 int intel_reset_guc(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1973d8e047f0f..b86e67c694584 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -456,7 +456,6 @@ static const struct intel_device_info snb_m_gt2_info = {
 	.has_coherent_ggtt = true, \
 	.has_llc = 1, \
 	.has_rc6p = 1, \
-	.has_reset_engine = true, \
 	.has_rps = true, \
 	.dma_mask_size = 40, \
 	.ppgtt_type = INTEL_PPGTT_ALIASING, \
@@ -514,7 +513,6 @@ static const struct intel_device_info vlv_info = {
 	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
 	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
 	.has_runtime_pm = 1,
-	.has_reset_engine = true,
 	.has_rps = true,
 	.display.has_gmch = 1,
 	.display.has_hotplug = 1,
@@ -618,7 +616,6 @@ static const struct intel_device_info chv_info = {
 	.dma_mask_size = 39,
 	.ppgtt_type = INTEL_PPGTT_FULL,
 	.ppgtt_size = 32,
-	.has_reset_engine = 1,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
@@ -700,7 +697,6 @@ static const struct intel_device_info skl_gt4_info = {
 	.dma_mask_size = 39, \
 	.ppgtt_type = INTEL_PPGTT_FULL, \
 	.ppgtt_size = 48, \
-	.has_reset_engine = 1, \
 	.has_snoop = true, \
 	.has_coherent_ggtt = false, \
 	.display.has_ipc = 1, \
@@ -1003,7 +999,6 @@ static const struct intel_device_info adl_p_info = {
 	.has_logical_ring_contexts = 1, \
 	.has_logical_ring_elsq = 1, \
 	.has_mslices = 1, \
-	.has_reset_engine = 1, \
 	.has_rps = 1, \
 	.has_runtime_pm = 1, \
 	.ppgtt_size = 48, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 68af6f89a3661..53777e14fa850 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -137,7 +137,6 @@ enum intel_ppgtt_type {
 	func(has_64k_pages); \
 	func(needs_compact_pt); \
 	func(gpu_reset_clobbers_display); \
-	func(has_reset_engine); \
 	func(has_4tile); \
 	func(has_flat_ccs); \
 	func(has_global_mocs); \
-- 
GitLab


From b6411373d3954c8fe4617c27f90f773108b0ab03 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com>
Date: Thu, 5 May 2022 12:35:21 -0700
Subject: [PATCH 0013/1731] drm/i915: Drop has_logical_ring_elsq from device
 info
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

No need to have this parameter in intel_device_info struct
as all platforms with graphics version 11 or newer has this feature.

As a side effect of the of removal this flag, it will not be printed
in dmesg during driver load anymore and developers will have to rely
on to check the macro and compare with platform being used and IP
versions of it.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505193524.276400-4-jose.souza@intel.com
---
 drivers/gpu/drm/i915/i915_drv.h          | 3 +--
 drivers/gpu/drm/i915/i915_pci.c          | 4 +---
 drivers/gpu/drm/i915/intel_device_info.h | 1 -
 3 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8f48c3d906455..bc6d8ccd662ee 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1241,8 +1241,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
 		(INTEL_INFO(dev_priv)->has_logical_ring_contexts)
-#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
-		(INTEL_INFO(dev_priv)->has_logical_ring_elsq)
+#define HAS_LOGICAL_RING_ELSQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11)
 
 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b86e67c694584..f60f9babdf2a9 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -809,8 +809,7 @@ static const struct intel_device_info cml_gt2_info = {
 	.dbuf.size = 2048, \
 	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
 	.display.has_dsc = 1, \
-	.has_coherent_ggtt = false, \
-	.has_logical_ring_elsq = 1
+	.has_coherent_ggtt = false
 
 static const struct intel_device_info icl_info = {
 	GEN11_FEATURES,
@@ -997,7 +996,6 @@ static const struct intel_device_info adl_p_info = {
 	.has_global_mocs = 1, \
 	.has_llc = 1, \
 	.has_logical_ring_contexts = 1, \
-	.has_logical_ring_elsq = 1, \
 	.has_mslices = 1, \
 	.has_rps = 1, \
 	.has_runtime_pm = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 53777e14fa850..1308752219db6 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -146,7 +146,6 @@ enum intel_ppgtt_type {
 	func(has_l3_dpf); \
 	func(has_llc); \
 	func(has_logical_ring_contexts); \
-	func(has_logical_ring_elsq); \
 	func(has_mslices); \
 	func(has_pooled_eu); \
 	func(has_pxp); \
-- 
GitLab


From efd01cd3c27636bc4840057a03839e54abaf11dc Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com>
Date: Thu, 5 May 2022 12:35:22 -0700
Subject: [PATCH 0014/1731] drm/i915: Drop has_ddi from device info
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

No need to have this parameter in intel_device_info struct
as all platforms with display version 9 or newer, haswell or broadwell
supports it.

As a side effect of the of removal this flag, it will not be printed
in dmesg during driver load anymore and developers will have to rely
on to check the macro and compare with platform being used and IP
versions of it.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505193524.276400-5-jose.souza@intel.com
---
 drivers/gpu/drm/i915/i915_drv.h          | 4 +++-
 drivers/gpu/drm/i915/i915_pci.c          | 3 ---
 drivers/gpu/drm/i915/intel_device_info.h | 1 -
 3 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bc6d8ccd662ee..eddfbf5d3dee6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1293,7 +1293,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_DP20(dev_priv)	(IS_DG2(dev_priv))
 
 #define HAS_CDCLK_CRAWL(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
-#define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)
+#define HAS_DDI(dev_priv)		 (DISPLAY_VER(dev_priv) >= 9 || \
+					  IS_BROADWELL(dev_priv) || \
+					  IS_HASWELL(dev_priv))
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
 #define HAS_PSR_HW_TRACKING(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f60f9babdf2a9..44a4723ff7f70 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -535,7 +535,6 @@ static const struct intel_device_info vlv_info = {
 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
-	.display.has_ddi = 1, \
 	.display.has_fpga_dbg = 1, \
 	.display.has_dp_mst = 1, \
 	.has_rc6p = 0 /* RC6p removed-by HSW */, \
@@ -683,7 +682,6 @@ static const struct intel_device_info skl_gt4_info = {
 		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 		BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
 	.has_64bit_reloc = 1, \
-	.display.has_ddi = 1, \
 	.display.has_fpga_dbg = 1, \
 	.display.fbc_mask = BIT(INTEL_FBC_A), \
 	.display.has_hdcp = 1, \
@@ -932,7 +930,6 @@ static const struct intel_device_info adl_s_info = {
 	.dbuf.size = 4096,							\
 	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |		\
 		BIT(DBUF_S4),							\
-	.display.has_ddi = 1,							\
 	.display.has_dmc = 1,							\
 	.display.has_dp_mst = 1,						\
 	.display.has_dsb = 1,							\
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 1308752219db6..cc317a511fb54 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -162,7 +162,6 @@ enum intel_ppgtt_type {
 	func(cursor_needs_physical); \
 	func(has_cdclk_crawl); \
 	func(has_dmc); \
-	func(has_ddi); \
 	func(has_dp_mst); \
 	func(has_dsb); \
 	func(has_dsc); \
-- 
GitLab


From eb86f645ab9b90c47de7ebe229feae7ac999421b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com>
Date: Thu, 5 May 2022 12:35:23 -0700
Subject: [PATCH 0015/1731] drm/i915: Drop has_dp_mst from device info
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

No need to have this parameter in intel_device_info struct
as the requirement to support it is the DDI support.

As a side effect of the of removal this flag, it will not be printed
in dmesg during driver load anymore and developers will have to rely
on to check the macro and compare with platform being used and IP
versions of it.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505193524.276400-6-jose.souza@intel.com
---
 drivers/gpu/drm/i915/i915_drv.h          | 2 +-
 drivers/gpu/drm/i915/i915_pci.c          | 3 ---
 drivers/gpu/drm/i915/intel_device_info.h | 1 -
 3 files changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index eddfbf5d3dee6..cbe0b19af0a8a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1289,13 +1289,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
 
-#define HAS_DP_MST(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dp_mst)
 #define HAS_DP20(dev_priv)	(IS_DG2(dev_priv))
 
 #define HAS_CDCLK_CRAWL(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
 #define HAS_DDI(dev_priv)		 (DISPLAY_VER(dev_priv) >= 9 || \
 					  IS_BROADWELL(dev_priv) || \
 					  IS_HASWELL(dev_priv))
+#define HAS_DP_MST(dev_priv)		 (HAS_DDI(dev_priv))
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
 #define HAS_PSR_HW_TRACKING(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 44a4723ff7f70..ca6461ecb7deb 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -536,7 +536,6 @@ static const struct intel_device_info vlv_info = {
 	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
 	.display.has_fpga_dbg = 1, \
-	.display.has_dp_mst = 1, \
 	.has_rc6p = 0 /* RC6p removed-by HSW */, \
 	HSW_PIPE_OFFSETS, \
 	.has_runtime_pm = 1
@@ -690,7 +689,6 @@ static const struct intel_device_info skl_gt4_info = {
 	.has_runtime_pm = 1, \
 	.display.has_dmc = 1, \
 	.has_rps = true, \
-	.display.has_dp_mst = 1, \
 	.has_logical_ring_contexts = 1, \
 	.dma_mask_size = 39, \
 	.ppgtt_type = INTEL_PPGTT_FULL, \
@@ -931,7 +929,6 @@ static const struct intel_device_info adl_s_info = {
 	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |		\
 		BIT(DBUF_S4),							\
 	.display.has_dmc = 1,							\
-	.display.has_dp_mst = 1,						\
 	.display.has_dsb = 1,							\
 	.display.has_dsc = 1,							\
 	.display.fbc_mask = BIT(INTEL_FBC_A),					\
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index cc317a511fb54..ffea8bff4b76d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -162,7 +162,6 @@ enum intel_ppgtt_type {
 	func(cursor_needs_physical); \
 	func(has_cdclk_crawl); \
 	func(has_dmc); \
-	func(has_dp_mst); \
 	func(has_dsb); \
 	func(has_dsc); \
 	func(has_fpga_dbg); \
-- 
GitLab


From b15a7357a84f091fde8ce35bf2fd494150ad4bd0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com>
Date: Thu, 5 May 2022 12:35:24 -0700
Subject: [PATCH 0016/1731] drm/i915: Drop has_psr from device info
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

No need to have this parameter in intel_device_info struct
as all platforms with display version 9 or newer has this feature.

As a side effect of the of removal this flag, it will not be printed
in dmesg during driver load anymore and developers will have to rely
on to check the macro and compare with platform being used and IP
versions of it.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505193524.276400-7-jose.souza@intel.com
---
 drivers/gpu/drm/i915/i915_drv.h          | 2 +-
 drivers/gpu/drm/i915/i915_pci.c          | 3 ---
 drivers/gpu/drm/i915/intel_device_info.h | 1 -
 3 files changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cbe0b19af0a8a..9d5fab8d20516 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1297,7 +1297,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 					  IS_HASWELL(dev_priv))
 #define HAS_DP_MST(dev_priv)		 (HAS_DDI(dev_priv))
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
-#define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
+#define HAS_PSR(dev_priv)		 (DISPLAY_VER(dev_priv) >= 9)
 #define HAS_PSR_HW_TRACKING(dev_priv) \
 	(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
 #define HAS_PSR2_SEL_FETCH(dev_priv)	 (DISPLAY_VER(dev_priv) >= 12)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index ca6461ecb7deb..1f320245c3442 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -635,7 +635,6 @@ static const struct intel_device_info chv_info = {
 	.display.has_dmc = 1, \
 	.display.has_hdcp = 1, \
 	.display.has_ipc = 1, \
-	.display.has_psr = 1, \
 	.display.has_psr_hw_tracking = 1, \
 	.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
 	.dbuf.slice_mask = BIT(DBUF_S1)
@@ -684,7 +683,6 @@ static const struct intel_device_info skl_gt4_info = {
 	.display.has_fpga_dbg = 1, \
 	.display.fbc_mask = BIT(INTEL_FBC_A), \
 	.display.has_hdcp = 1, \
-	.display.has_psr = 1, \
 	.display.has_psr_hw_tracking = 1, \
 	.has_runtime_pm = 1, \
 	.display.has_dmc = 1, \
@@ -936,7 +934,6 @@ static const struct intel_device_info adl_s_info = {
 	.display.has_hdcp = 1,							\
 	.display.has_hotplug = 1,						\
 	.display.has_ipc = 1,							\
-	.display.has_psr = 1,							\
 	.display.ver = 13,							\
 	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),	\
 	.pipe_offsets = {							\
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index ffea8bff4b76d..8702d1ae8fc00 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -172,7 +172,6 @@ enum intel_ppgtt_type {
 	func(has_ipc); \
 	func(has_modular_fia); \
 	func(has_overlay); \
-	func(has_psr); \
 	func(has_psr_hw_tracking); \
 	func(overlay_needs_physical); \
 	func(supports_tv);
-- 
GitLab


From 048058399f19d43cf21de9f5d36cd8144337d004 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Fri, 6 May 2022 11:50:40 +0200
Subject: [PATCH 0017/1731] iio: adc: axp288: Override TS pin bias current for
 some models
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Since commit 9bcf15f75cac ("iio: adc: axp288: Fix TS-pin handling") we
preserve the bias current set by the firmware at boot. This fixes issues
we were seeing on various models.

Some models like the Nuvision Solo 10 Draw tablet actually need the
old hardcoded 80ųA bias current for battery temperature monitoring
to work properly.

Add a quirk entry for the Nuvision Solo 10 Draw to the DMI quirk table
to restore setting the bias current to 80ųA on this model.

Fixes: 9bcf15f75cac ("iio: adc: axp288: Fix TS-pin handling")
BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=215882
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20220506095040.21008-1-hdegoede@redhat.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/axp288_adc.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/iio/adc/axp288_adc.c b/drivers/iio/adc/axp288_adc.c
index a4b8be5b8f883..580361bd98492 100644
--- a/drivers/iio/adc/axp288_adc.c
+++ b/drivers/iio/adc/axp288_adc.c
@@ -196,6 +196,14 @@ static const struct dmi_system_id axp288_adc_ts_bias_override[] = {
 		},
 		.driver_data = (void *)(uintptr_t)AXP288_ADC_TS_BIAS_80UA,
 	},
+	{
+		/* Nuvision Solo 10 Draw */
+		.matches = {
+		  DMI_MATCH(DMI_SYS_VENDOR, "TMAX"),
+		  DMI_MATCH(DMI_PRODUCT_NAME, "TM101W610L"),
+		},
+		.driver_data = (void *)(uintptr_t)AXP288_ADC_TS_BIAS_80UA,
+	},
 	{}
 };
 
-- 
GitLab


From bb52d3691db8cf24cea049235223f3599778f264 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Sun, 1 May 2022 21:50:29 +0200
Subject: [PATCH 0018/1731] iio: magnetometer: yas530: Fix memchr_inv() misuse

The call to check if the calibration is all zeroes is doing
it wrong: memchr_inv() returns NULL if the the calibration
contains all zeroes, but the check is for != NULL.

Fix it up. It's probably not an urgent fix because the inner
check for BIT(7) in data[13] will save us. But fix it.

Fixes: de8860b1ed47 ("iio: magnetometer: Add driver for Yamaha YAS530")
Reported-by: Jakob Hauser <jahau@rocketmail.com>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20220501195029.151852-1-linus.walleij@linaro.org
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/magnetometer/yamaha-yas530.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/magnetometer/yamaha-yas530.c b/drivers/iio/magnetometer/yamaha-yas530.c
index 9ff7b0e56cf67..b2bc637150bfa 100644
--- a/drivers/iio/magnetometer/yamaha-yas530.c
+++ b/drivers/iio/magnetometer/yamaha-yas530.c
@@ -639,7 +639,7 @@ static int yas532_get_calibration_data(struct yas5xx *yas5xx)
 	dev_dbg(yas5xx->dev, "calibration data: %*ph\n", 14, data);
 
 	/* Sanity check, is this all zeroes? */
-	if (memchr_inv(data, 0x00, 13)) {
+	if (memchr_inv(data, 0x00, 13) == NULL) {
 		if (!(data[13] & BIT(7)))
 			dev_warn(yas5xx->dev, "calibration is blank!\n");
 	}
-- 
GitLab


From 1b93ff4d0679190e8812cd0d0b3aebfcba1ed883 Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Wed, 4 May 2022 21:37:14 +0300
Subject: [PATCH 0019/1731] drm/i915: remove unused GEM_DEBUG_DECL() and
 GEM_DEBUG_BUG_ON()

There are already too many choices here, take away the unused ones.

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220504183716.987793-1-jani.nikula@intel.com
---
 drivers/gpu/drm/i915/i915_gem.h | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index d0752e5553db4..b7b257f54d2e2 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -54,9 +54,7 @@ struct drm_i915_private;
 	} while(0)
 #define GEM_WARN_ON(expr) WARN_ON(expr)
 
-#define GEM_DEBUG_DECL(var) var
 #define GEM_DEBUG_EXEC(expr) expr
-#define GEM_DEBUG_BUG_ON(expr) GEM_BUG_ON(expr)
 #define GEM_DEBUG_WARN_ON(expr) GEM_WARN_ON(expr)
 
 #else
@@ -66,9 +64,7 @@ struct drm_i915_private;
 #define GEM_BUG_ON(expr) BUILD_BUG_ON_INVALID(expr)
 #define GEM_WARN_ON(expr) ({ unlikely(!!(expr)); })
 
-#define GEM_DEBUG_DECL(var)
 #define GEM_DEBUG_EXEC(expr) do { } while (0)
-#define GEM_DEBUG_BUG_ON(expr)
 #define GEM_DEBUG_WARN_ON(expr) ({ BUILD_BUG_ON_INVALID(expr); 0; })
 #endif
 
-- 
GitLab


From e9794c88cd6cf4be4a79188916a75539751f532c Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Wed, 4 May 2022 21:37:15 +0300
Subject: [PATCH 0020/1731] drm/i915: remove single-use GEM_DEBUG_EXEC()

Reduce the magic of what's going on in GEM_DEBUG_EXEC() by expanding it
inline and being explicit about it. It's as single use case anyway, so
the macro feels overkill.

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220504183716.987793-2-jani.nikula@intel.com
---
 drivers/gpu/drm/i915/gt/intel_ring.c | 3 ++-
 drivers/gpu/drm/i915/i915_gem.h      | 2 --
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c
index 40ffcb94e3797..15ec64d881c44 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring.c
@@ -299,7 +299,8 @@ u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords)
 	GEM_BUG_ON(ring->emit > ring->size - bytes);
 	GEM_BUG_ON(ring->space < bytes);
 	cs = ring->vaddr + ring->emit;
-	GEM_DEBUG_EXEC(memset32(cs, POISON_INUSE, bytes / sizeof(*cs)));
+	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+		memset32(cs, POISON_INUSE, bytes / sizeof(*cs));
 	ring->emit += bytes;
 	ring->space -= bytes;
 
diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index b7b257f54d2e2..a2be323a4be55 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -54,7 +54,6 @@ struct drm_i915_private;
 	} while(0)
 #define GEM_WARN_ON(expr) WARN_ON(expr)
 
-#define GEM_DEBUG_EXEC(expr) expr
 #define GEM_DEBUG_WARN_ON(expr) GEM_WARN_ON(expr)
 
 #else
@@ -64,7 +63,6 @@ struct drm_i915_private;
 #define GEM_BUG_ON(expr) BUILD_BUG_ON_INVALID(expr)
 #define GEM_WARN_ON(expr) ({ unlikely(!!(expr)); })
 
-#define GEM_DEBUG_EXEC(expr) do { } while (0)
 #define GEM_DEBUG_WARN_ON(expr) ({ BUILD_BUG_ON_INVALID(expr); 0; })
 #endif
 
-- 
GitLab


From 23dd74db02d75579d8d4eb0b88c7ad119e782269 Mon Sep 17 00:00:00 2001
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date: Fri, 29 Apr 2022 11:04:13 +0100
Subject: [PATCH 0021/1731] drm/i915: Enable THP on Icelake and beyond

We have a statement from HW designers that the GPU read regression when
using 2M pages was fixed from Icelake onwards, which was also confirmed
by bencharking Eero did last year:

"""
When IOMMU is disabled, enabling THP causes following perf changes on
TGL-H (GT1):

    10-15% SynMark Batch[0-3]
    5-10% MemBW GPU texture, SynMark ShMapVsm
    3-5% SynMark TerrainFly* + Geom* + Fill* + CSCloth + Batch4
    1-3% GpuTest Triangle, SynMark TexMem* + DeferredAA + Batch[5-7]
          + few others
    -7% MemBW GPU blend

In the above 3D benchmark names, * means all the variants of tests with
the same prefix. For example "SynMark TexMem*", means both TexMem128 &
TexMem512 tests in the synthetic (Intel internal) SynMark test suite.

In the (public, but proprietary) GfxBench & GLB(enchmark) test suites,
there are both onscreen and offscreen variants of each test. Unless
explicitly stated otherwise, numbers are for both variants.

All tests are run with FullHD monitor. All tests are fullscreen except
for GLB and GpuTest ones, which are run in 1/2 screen window (GpuTest
triangle is run both in fullscreen and 1/2 screen window).
"""

Since the only regression is MemBW GPU blend, against many more gains,
it sounds it is time to enable THP on Gen11+.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
References: https://gitlab.freedesktop.org/drm/intel/-/issues/430
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220429100414.647857-1-tvrtko.ursulin@linux.intel.com
---
 drivers/gpu/drm/i915/gem/i915_gemfs.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gemfs.c b/drivers/gpu/drm/i915/gem/i915_gemfs.c
index ee87874e59dcc..c5a6bbc842fc4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gemfs.c
+++ b/drivers/gpu/drm/i915/gem/i915_gemfs.c
@@ -28,12 +28,14 @@ int i915_gemfs_init(struct drm_i915_private *i915)
 	 *
 	 * One example, although it is probably better with a per-file
 	 * control, is selecting huge page allocations ("huge=within_size").
-	 * However, we only do so to offset the overhead of iommu lookups
-	 * due to bandwidth issues (slow reads) on Broadwell+.
+	 * However, we only do so on platforms which benefit from it, or to
+	 * offset the overhead of iommu lookups, where with latter it is a net
+	 * win even on platforms which would otherwise see some performance
+	 * regressions such a slow reads issue on Broadwell and Skylake.
 	 */
 
 	opts = NULL;
-	if (i915_vtd_active(i915)) {
+	if (GRAPHICS_VER(i915) >= 11 || i915_vtd_active(i915)) {
 		if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE)) {
 			opts = huge_opt;
 			drm_info(&i915->drm,
@@ -41,7 +43,10 @@ int i915_gemfs_init(struct drm_i915_private *i915)
 				 opts);
 		} else {
 			drm_notice(&i915->drm,
-				   "Transparent Hugepage support is recommended for optimal performance when IOMMU is enabled!\n");
+				   "Transparent Hugepage support is recommended for optimal performance%s\n",
+				   GRAPHICS_VER(i915) >= 11 ?
+				   " on this platform!" :
+				   " when IOMMU is enabled!");
 		}
 	}
 
-- 
GitLab


From b499914eb83765a27e3b43f216e9d1bdf4265418 Mon Sep 17 00:00:00 2001
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date: Fri, 29 Apr 2022 11:04:14 +0100
Subject: [PATCH 0022/1731] drm/i915: Only setup private tmpfs mount when
 needed and fix logging

If i915 does not want to use huge pages there is a) no point in setting up
the private mount and b) should former fail, it is misleading to log THP
support is disabled in the caller, which does not even know if callee
tried to enable it.

Fix both by restructuring the flow in i915_gemfs_init and at the same time
note the failure to set it up in all cases.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220429100414.647857-2-tvrtko.ursulin@linux.intel.com
---
 drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 11 +-----
 drivers/gpu/drm/i915/gem/i915_gemfs.c     | 45 ++++++++++-------------
 drivers/gpu/drm/i915/gem/i915_gemfs.h     |  3 +-
 3 files changed, 23 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index c2a3e388fcb4c..955844f191935 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -671,17 +671,10 @@ fail:
 
 static int init_shmem(struct intel_memory_region *mem)
 {
-	int err;
-
-	err = i915_gemfs_init(mem->i915);
-	if (err) {
-		DRM_NOTE("Unable to create a private tmpfs mount, hugepage support will be disabled(%d).\n",
-			 err);
-	}
-
+	i915_gemfs_init(mem->i915);
 	intel_memory_region_set_name(mem, "system");
 
-	return 0; /* Don't error, we can simply fallback to the kernel mnt */
+	return 0; /* We have fallback to the kernel mnt if gemfs init failed. */
 }
 
 static int release_shmem(struct intel_memory_region *mem)
diff --git a/drivers/gpu/drm/i915/gem/i915_gemfs.c b/drivers/gpu/drm/i915/gem/i915_gemfs.c
index c5a6bbc842fc4..46b9a17d6abc6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gemfs.c
+++ b/drivers/gpu/drm/i915/gem/i915_gemfs.c
@@ -11,16 +11,11 @@
 #include "i915_gemfs.h"
 #include "i915_utils.h"
 
-int i915_gemfs_init(struct drm_i915_private *i915)
+void i915_gemfs_init(struct drm_i915_private *i915)
 {
 	char huge_opt[] = "huge=within_size"; /* r/w */
 	struct file_system_type *type;
 	struct vfsmount *gemfs;
-	char *opts;
-
-	type = get_fs_type("tmpfs");
-	if (!type)
-		return -ENODEV;
 
 	/*
 	 * By creating our own shmemfs mountpoint, we can pass in
@@ -34,29 +29,29 @@ int i915_gemfs_init(struct drm_i915_private *i915)
 	 * regressions such a slow reads issue on Broadwell and Skylake.
 	 */
 
-	opts = NULL;
-	if (GRAPHICS_VER(i915) >= 11 || i915_vtd_active(i915)) {
-		if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE)) {
-			opts = huge_opt;
-			drm_info(&i915->drm,
-				 "Transparent Hugepage mode '%s'\n",
-				 opts);
-		} else {
-			drm_notice(&i915->drm,
-				   "Transparent Hugepage support is recommended for optimal performance%s\n",
-				   GRAPHICS_VER(i915) >= 11 ?
-				   " on this platform!" :
-				   " when IOMMU is enabled!");
-		}
-	}
+	if (GRAPHICS_VER(i915) < 11 && !i915_vtd_active(i915))
+		return;
+
+	if (!IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE))
+		goto err;
 
-	gemfs = vfs_kern_mount(type, SB_KERNMOUNT, type->name, opts);
+	type = get_fs_type("tmpfs");
+	if (!type)
+		goto err;
+
+	gemfs = vfs_kern_mount(type, SB_KERNMOUNT, type->name, huge_opt);
 	if (IS_ERR(gemfs))
-		return PTR_ERR(gemfs);
+		goto err;
 
 	i915->mm.gemfs = gemfs;
-
-	return 0;
+	drm_info(&i915->drm, "Using Transparent Hugepages\n");
+	return;
+
+err:
+	drm_notice(&i915->drm,
+		   "Transparent Hugepage support is recommended for optimal performance%s\n",
+		   GRAPHICS_VER(i915) >= 11 ? " on this platform!" :
+					      " when IOMMU is enabled!");
 }
 
 void i915_gemfs_fini(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/gem/i915_gemfs.h b/drivers/gpu/drm/i915/gem/i915_gemfs.h
index 2a1e59af3e4a1..5d835e44c4f6e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gemfs.h
+++ b/drivers/gpu/drm/i915/gem/i915_gemfs.h
@@ -9,8 +9,7 @@
 
 struct drm_i915_private;
 
-int i915_gemfs_init(struct drm_i915_private *i915);
-
+void i915_gemfs_init(struct drm_i915_private *i915);
 void i915_gemfs_fini(struct drm_i915_private *i915);
 
 #endif
-- 
GitLab


From 429e1fc1b2c257f35b6a1318eb3a1ffb80bc6640 Mon Sep 17 00:00:00 2001
From: Lucas De Marchi <lucas.demarchi@intel.com>
Date: Mon, 2 May 2022 23:15:56 -0700
Subject: [PATCH 0023/1731] drm/i915/gem: Make drop_pages() return bool

Commit e4e806253003 ("drm/i915: Change shrink ordering to use locking
around unbinding.") changed the return type to int without changing the
return values or their meaning to "0 is success". Move it back to
boolean.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220503061556.513175-1-lucas.demarchi@intel.com
---
 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index 6a6ff98a87462..1030053571a20 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -36,7 +36,7 @@ static bool can_release_pages(struct drm_i915_gem_object *obj)
 	return swap_available() || obj->mm.madv == I915_MADV_DONTNEED;
 }
 
-static int drop_pages(struct drm_i915_gem_object *obj,
+static bool drop_pages(struct drm_i915_gem_object *obj,
 		       unsigned long shrink, bool trylock_vm)
 {
 	unsigned long flags;
-- 
GitLab


From 9d67edba730c4663eb7d87771123c3fb86ba606d Mon Sep 17 00:00:00 2001
From: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
Date: Thu, 5 May 2022 14:38:03 -0700
Subject: [PATCH 0024/1731] drm/i915/pvc: Define MOCS table for PVC

v2 (MattR):
 - Clarify comment above RING_CMD_CCTL programming.
 - Remove bspec reference from field definition.  (Lucas)
 - Add WARN if we try to use a (presumably uninitialized) wb_index of 0.
   On most platforms 0 is an invalid MOCS entry and even on the ones
   where it isn't, it isn't the right setting for wb_index.  (Lucas)

Bspec: 45101, 72161
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
Signed-off-by: Fei Yang <fei.yang@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505213812.3979301-4-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/intel_gt_types.h    |  1 +
 drivers/gpu/drm/i915/gt/intel_mocs.c        | 24 ++++++++++++++++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 30 ++++++++++++++++-----
 drivers/gpu/drm/i915/i915_drv.h             |  2 ++
 drivers/gpu/drm/i915/i915_pci.c             |  3 ++-
 drivers/gpu/drm/i915/intel_device_info.h    |  1 +
 6 files changed, 53 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index b06611c1d4ada..097e10291f2d3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -221,6 +221,7 @@ struct intel_gt {
 
 	struct {
 		u8 uc_index;
+		u8 wb_index; /* Only used on HAS_L3_CCS_READ() platforms */
 	} mocs;
 
 	struct intel_pxp pxp;
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index c4c37585ae8cc..c6ebe27810764 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -23,6 +23,7 @@ struct drm_i915_mocs_table {
 	unsigned int n_entries;
 	const struct drm_i915_mocs_entry *table;
 	u8 uc_index;
+	u8 wb_index; /* Only used on HAS_L3_CCS_READ() platforms */
 	u8 unused_entries_index;
 };
 
@@ -47,6 +48,7 @@ struct drm_i915_mocs_table {
 
 /* Helper defines */
 #define GEN9_NUM_MOCS_ENTRIES	64  /* 63-64 are reserved, but configured. */
+#define PVC_NUM_MOCS_ENTRIES	3
 
 /* (e)LLC caching options */
 /*
@@ -394,6 +396,17 @@ static const struct drm_i915_mocs_entry dg2_mocs_table_g10_ax[] = {
 	MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
 };
 
+static const struct drm_i915_mocs_entry pvc_mocs_table[] = {
+	/* Error */
+	MOCS_ENTRY(0, 0, L3_3_WB),
+
+	/* UC */
+	MOCS_ENTRY(1, 0, L3_1_UC),
+
+	/* WB */
+	MOCS_ENTRY(2, 0, L3_3_WB),
+};
+
 enum {
 	HAS_GLOBAL_MOCS = BIT(0),
 	HAS_ENGINE_MOCS = BIT(1),
@@ -423,7 +436,14 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
 	memset(table, 0, sizeof(struct drm_i915_mocs_table));
 
 	table->unused_entries_index = I915_MOCS_PTE;
-	if (IS_DG2(i915)) {
+	if (IS_PONTEVECCHIO(i915)) {
+		table->size = ARRAY_SIZE(pvc_mocs_table);
+		table->table = pvc_mocs_table;
+		table->n_entries = PVC_NUM_MOCS_ENTRIES;
+		table->uc_index = 1;
+		table->wb_index = 2;
+		table->unused_entries_index = 2;
+	} else if (IS_DG2(i915)) {
 		if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
 			table->size = ARRAY_SIZE(dg2_mocs_table_g10_ax);
 			table->table = dg2_mocs_table_g10_ax;
@@ -622,6 +642,8 @@ void intel_set_mocs_index(struct intel_gt *gt)
 
 	get_mocs_settings(gt->i915, &table);
 	gt->mocs.uc_index = table.uc_index;
+	if (HAS_L3_CCS_READ(gt->i915))
+		gt->mocs.wb_index = table.wb_index;
 }
 
 void intel_mocs_init(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a05c4b99b3fbc..756807c4b405e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1994,19 +1994,37 @@ void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
 static void
 engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 {
-	u8 mocs;
+	u8 mocs_w, mocs_r;
 
 	/*
-	 * RING_CMD_CCTL are need to be programed to un-cached
-	 * for memory writes and reads outputted by Command
-	 * Streamers on Gen12 onward platforms.
+	 * RING_CMD_CCTL specifies the default MOCS entry that will be used
+	 * by the command streamer when executing commands that don't have
+	 * a way to explicitly specify a MOCS setting.  The default should
+	 * usually reference whichever MOCS entry corresponds to uncached
+	 * behavior, although use of a WB cached entry is recommended by the
+	 * spec in certain circumstances on specific platforms.
 	 */
 	if (GRAPHICS_VER(engine->i915) >= 12) {
-		mocs = engine->gt->mocs.uc_index;
+		mocs_r = engine->gt->mocs.uc_index;
+		mocs_w = engine->gt->mocs.uc_index;
+
+		if (HAS_L3_CCS_READ(engine->i915) &&
+		    engine->class == COMPUTE_CLASS) {
+			mocs_r = engine->gt->mocs.wb_index;
+
+			/*
+			 * Even on the few platforms where MOCS 0 is a
+			 * legitimate table entry, it's never the correct
+			 * setting to use here; we can assume the MOCS init
+			 * just forgot to initialize wb_index.
+			 */
+			drm_WARN_ON(&engine->i915->drm, mocs_r == 0);
+		}
+
 		wa_masked_field_set(wal,
 				    RING_CMD_CCTL(engine->mmio_base),
 				    CMD_CCTL_MOCS_MASK,
-				    CMD_CCTL_MOCS_OVERRIDE(mocs, mocs));
+				    CMD_CCTL_MOCS_OVERRIDE(mocs_w, mocs_r));
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9d5fab8d20516..9c0a8c86876a8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1366,6 +1366,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
 
+#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
+
 /* DPF == dynamic parity feature */
 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1f320245c3442..0e1d0493d3fe8 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1051,7 +1051,8 @@ static const struct intel_device_info ats_m_info = {
 
 #define XE_HPC_FEATURES \
 	XE_HP_FEATURES, \
-	.dma_mask_size = 52
+	.dma_mask_size = 52, \
+	.has_l3_ccs_read = 1
 
 __maybe_unused
 static const struct intel_device_info pvc_info = {
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 8702d1ae8fc00..55f40fa0ea49a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -143,6 +143,7 @@ enum intel_ppgtt_type {
 	func(has_heci_pxp); \
 	func(has_heci_gscfi); \
 	func(has_guc_deprivilege); \
+	func(has_l3_ccs_read); \
 	func(has_l3_dpf); \
 	func(has_llc); \
 	func(has_logical_ring_contexts); \
-- 
GitLab


From 4de23dca7ec8dfb191ea80fbfe3f008d4ed52346 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Thu, 5 May 2022 14:38:04 -0700
Subject: [PATCH 0025/1731] drm/i915/pvc: Read correct RP_STATE_CAP register

The SoC registers, including RP_STATE_CAP, have moved to a new location
in GTTMMADR on Ponte Vecchio.  We need to update the register offset
accordingly.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505213812.3979301-5-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/intel_rps.c | 4 +++-
 drivers/gpu/drm/i915/i915_reg.h     | 1 +
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 3476a11f294ce..3bd8415a0f1b5 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1075,7 +1075,9 @@ static u32 intel_rps_read_state_cap(struct intel_rps *rps)
 	struct drm_i915_private *i915 = rps_to_i915(rps);
 	struct intel_uncore *uncore = rps_to_uncore(rps);
 
-	if (IS_XEHPSDV(i915))
+	if (IS_PONTEVECCHIO(i915))
+		return intel_uncore_read(uncore, PVC_RP_STATE_CAP);
+	else if (IS_XEHPSDV(i915))
 		return intel_uncore_read(uncore, XEHPSDV_RP_STATE_CAP);
 	else if (IS_GEN9_LP(i915))
 		return intel_uncore_read(uncore, BXT_RP_STATE_CAP);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index efcfe32cd8eba..f1a48d4578aa2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1845,6 +1845,7 @@
 #define BXT_RP_STATE_CAP        _MMIO(0x138170)
 #define GEN9_RP_STATE_LIMITS	_MMIO(0x138148)
 #define XEHPSDV_RP_STATE_CAP	_MMIO(0x250014)
+#define PVC_RP_STATE_CAP	_MMIO(0x281014)
 
 #define GT0_PERF_LIMIT_REASONS		_MMIO(0x1381a8)
 #define   GT0_PERF_LIMIT_REASONS_MASK	0xde3
-- 
GitLab


From 6cd96877c7da6bc3a28ef0bcb3bc7470f4dd9aa6 Mon Sep 17 00:00:00 2001
From: John Harrison <John.C.Harrison@Intel.com>
Date: Thu, 5 May 2022 14:38:06 -0700
Subject: [PATCH 0026/1731] drm/i915/pvc: Reduce stack usage in reset selftest
 with extra blitter engine
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

PVC adds extra blitter engines (in the following patch). The reset
selftest has a local array on the stack which is sized by the number
of engines. The increase pushes the size of this array to the point
where it trips the 'stack too large' compile warning. This patch takes
the allocation of the stack and makes it dynamic instead.

v2 (MattR):
 - Minor cosmetic changes:  re-sort definition and allocate using
   kmalloc_array().  (Tvrtko)

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505213812.3979301-7-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 83ff4c2e57c50..6493265d5f642 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -976,6 +976,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
 {
 	struct i915_gpu_error *global = &gt->i915->gpu_error;
 	struct intel_engine_cs *engine, *other;
+	struct active_engine *threads;
 	enum intel_engine_id id, tmp;
 	struct hang h;
 	int err = 0;
@@ -996,8 +997,11 @@ static int __igt_reset_engines(struct intel_gt *gt,
 			h.ctx->sched.priority = 1024;
 	}
 
+	threads = kmalloc_array(I915_NUM_ENGINES, sizeof(*threads), GFP_KERNEL);
+	if (!threads)
+		return -ENOMEM;
+
 	for_each_engine(engine, gt, id) {
-		struct active_engine threads[I915_NUM_ENGINES] = {};
 		unsigned long device = i915_reset_count(global);
 		unsigned long count = 0, reported;
 		bool using_guc = intel_engine_uses_guc(engine);
@@ -1016,7 +1020,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
 			break;
 		}
 
-		memset(threads, 0, sizeof(threads));
+		memset(threads, 0, sizeof(*threads) * I915_NUM_ENGINES);
 		for_each_engine(other, gt, tmp) {
 			struct task_struct *tsk;
 
@@ -1236,6 +1240,7 @@ unwind:
 			break;
 		}
 	}
+	kfree(threads);
 
 	if (intel_gt_is_wedged(gt))
 		err = -EIO;
-- 
GitLab


From 93d9e0453e2bb599e0bcced1b914f9b4010180a1 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Thu, 5 May 2022 14:38:07 -0700
Subject: [PATCH 0027/1731] drm/i915/gvt: Use intel_engine_mask_t for ring mask

When i915 adds additional PVC blitter instances (in an upcoming patch),
the definition of VECS0 will change from bit(10) to bit(18), causing
GVT's R_ALL mask to overflow the u16 storage that's currently used.
Let's replace the u16 with an intel_engine_mask_t to ensure we avoid
this.

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505213812.3979301-8-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 2459213b6c87f..efad8552d6e6c 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -428,7 +428,7 @@ struct cmd_info {
 #define R_VECS	BIT(VECS0)
 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
 	/* rings that support this cmd: BLT/RCS/VCS/VECS */
-	u16 rings;
+	intel_engine_mask_t rings;
 
 	/* devices that support this cmd: SNB/IVB/HSW/... */
 	u16 devices;
-- 
GitLab


From 69f8afdb45e7775840693bce42da79d9c22c2e83 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Thu, 5 May 2022 14:38:08 -0700
Subject: [PATCH 0028/1731] drm/i915/pvc: Engine definitions for new copy
 engines
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This patch adds the basic definitions needed to support
new copy engines. Also updating the cmd_info to accommodate
new engines, as the engine id's of legacy engines have been
changed.

v2:
 - Add _BCS(n) definition, similar to other engines.  (Tvrtko)
 - Add I915_MAX_BCS definition, similar to other engnes.  (Prathap)
 - Move GVT change to avoid u16 overflow to its own patch.  (Tvrtko)

Original-author: CQ Tang
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505213812.3979301-9-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 56 ++++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_engine_types.h | 12 ++++-
 drivers/gpu/drm/i915/gt/intel_gt_regs.h      |  8 +++
 drivers/gpu/drm/i915/i915_reg.h              |  8 +++
 4 files changed, 83 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 14c6ddbbfde8b..4532c3ea9ace1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -71,6 +71,62 @@ static const struct engine_info intel_engines[] = {
 			{ .graphics_ver = 6, .base = BLT_RING_BASE }
 		},
 	},
+	[BCS1] = {
+		.class = COPY_ENGINE_CLASS,
+		.instance = 1,
+		.mmio_bases = {
+			{ .graphics_ver = 12, .base = XEHPC_BCS1_RING_BASE }
+		},
+	},
+	[BCS2] = {
+		.class = COPY_ENGINE_CLASS,
+		.instance = 2,
+		.mmio_bases = {
+			{ .graphics_ver = 12, .base = XEHPC_BCS2_RING_BASE }
+		},
+	},
+	[BCS3] = {
+		.class = COPY_ENGINE_CLASS,
+		.instance = 3,
+		.mmio_bases = {
+			{ .graphics_ver = 12, .base = XEHPC_BCS3_RING_BASE }
+		},
+	},
+	[BCS4] = {
+		.class = COPY_ENGINE_CLASS,
+		.instance = 4,
+		.mmio_bases = {
+			{ .graphics_ver = 12, .base = XEHPC_BCS4_RING_BASE }
+		},
+	},
+	[BCS5] = {
+		.class = COPY_ENGINE_CLASS,
+		.instance = 5,
+		.mmio_bases = {
+			{ .graphics_ver = 12, .base = XEHPC_BCS5_RING_BASE }
+		},
+	},
+	[BCS6] = {
+		.class = COPY_ENGINE_CLASS,
+		.instance = 6,
+		.mmio_bases = {
+			{ .graphics_ver = 12, .base = XEHPC_BCS6_RING_BASE }
+		},
+	},
+	[BCS7] = {
+		.class = COPY_ENGINE_CLASS,
+		.instance = 7,
+		.mmio_bases = {
+			{ .graphics_ver = 12, .base = XEHPC_BCS7_RING_BASE }
+		},
+	},
+	[BCS8] = {
+		.class = COPY_ENGINE_CLASS,
+		.instance = 8,
+		.mmio_bases = {
+			{ .graphics_ver = 12, .base = XEHPC_BCS8_RING_BASE }
+		},
+	},
 	[VCS0] = {
 		.class = VIDEO_DECODE_CLASS,
 		.instance = 0,
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 298f2cc7a879f..2286f96f5f877 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -35,7 +35,7 @@
 #define OTHER_CLASS		4
 #define COMPUTE_CLASS		5
 #define MAX_ENGINE_CLASS	5
-#define MAX_ENGINE_INSTANCE	7
+#define MAX_ENGINE_INSTANCE	8
 
 #define I915_MAX_SLICES	3
 #define I915_MAX_SUBSLICES 8
@@ -99,6 +99,7 @@ struct i915_ctx_workarounds {
 #define I915_MAX_SFC	(I915_MAX_VCS / 2)
 #define I915_MAX_CCS	4
 #define I915_MAX_RCS	1
+#define I915_MAX_BCS	9
 
 /*
  * Engine IDs definitions.
@@ -107,6 +108,15 @@ struct i915_ctx_workarounds {
 enum intel_engine_id {
 	RCS0 = 0,
 	BCS0,
+	BCS1,
+	BCS2,
+	BCS3,
+	BCS4,
+	BCS5,
+	BCS6,
+	BCS7,
+	BCS8,
+#define _BCS(n) (BCS0 + (n))
 	VCS0,
 	VCS1,
 	VCS2,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index a0a49c16babd3..aa2c0974b02ce 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1476,6 +1476,14 @@
 #define   GEN11_KCR				(19)
 #define   GEN11_GTPM				(16)
 #define   GEN11_BCS				(15)
+#define   XEHPC_BCS1				(14)
+#define   XEHPC_BCS2				(13)
+#define   XEHPC_BCS3				(12)
+#define   XEHPC_BCS4				(11)
+#define   XEHPC_BCS5				(10)
+#define   XEHPC_BCS6				(9)
+#define   XEHPC_BCS7				(8)
+#define   XEHPC_BCS8				(23)
 #define   GEN12_CCS3				(7)
 #define   GEN12_CCS2				(6)
 #define   GEN12_CCS1				(5)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f1a48d4578aa2..117f9d909e950 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -976,6 +976,14 @@
 #define GEN12_COMPUTE2_RING_BASE	0x1e000
 #define GEN12_COMPUTE3_RING_BASE	0x26000
 #define BLT_RING_BASE		0x22000
+#define XEHPC_BCS1_RING_BASE	0x3e0000
+#define XEHPC_BCS2_RING_BASE	0x3e2000
+#define XEHPC_BCS3_RING_BASE	0x3e4000
+#define XEHPC_BCS4_RING_BASE	0x3e6000
+#define XEHPC_BCS5_RING_BASE	0x3e8000
+#define XEHPC_BCS6_RING_BASE	0x3ea000
+#define XEHPC_BCS7_RING_BASE	0x3ec000
+#define XEHPC_BCS8_RING_BASE	0x3ee000
 #define DG1_GSC_HECI1_BASE	0x00258000
 #define DG1_GSC_HECI2_BASE	0x00259000
 #define DG2_GSC_HECI1_BASE	0x00373000
-- 
GitLab


From 500d7135c924024ed2e5e62b03dd9b3b6257fa10 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Thu, 5 May 2022 14:38:09 -0700
Subject: [PATCH 0029/1731] drm/i915/pvc: Interrupt support for new copy
 engines

Add the interrupt handler support for new copy engines.

Bspec: 54030
Original-author: CQ Tang
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505213812.3979301-10-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/intel_gt_irq.c  | 16 ++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_gt_regs.h |  4 ++++
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 88b4becfcb175..3a72d4fd0214e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -193,6 +193,14 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
 	/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
 	intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK,	~0);
 	intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK,	~0);
+	if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2))
+		intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~0);
+	if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4))
+		intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~0);
+	if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6))
+		intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~0);
+	if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8))
+		intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~0);
 	intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK,	~0);
 	intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK,	~0);
 	if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
@@ -248,6 +256,14 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
 	/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
 	intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
 	intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~smask);
+	if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2))
+		intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
+	if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4))
+		intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
+	if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6))
+		intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
+	if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8))
+		intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
 	intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~dmask);
 	intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~dmask);
 	if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index aa2c0974b02ce..fe09288a31457 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1529,6 +1529,10 @@
 #define GEN11_GUNIT_CSME_INTR_MASK		_MMIO(0x1900f4)
 #define GEN12_CCS0_CCS1_INTR_MASK		_MMIO(0x190100)
 #define GEN12_CCS2_CCS3_INTR_MASK		_MMIO(0x190104)
+#define XEHPC_BCS1_BCS2_INTR_MASK		_MMIO(0x190110)
+#define XEHPC_BCS3_BCS4_INTR_MASK		_MMIO(0x190114)
+#define XEHPC_BCS5_BCS6_INTR_MASK		_MMIO(0x190118)
+#define XEHPC_BCS7_BCS8_INTR_MASK		_MMIO(0x19011c)
 
 #define GEN12_SFC_DONE(n)			_MMIO(0x1cc000 + (n) * 0x1000)
 
-- 
GitLab


From 8caaf7ad659da9b757781d5f08ce0bf98801931e Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Thu, 5 May 2022 14:38:10 -0700
Subject: [PATCH 0030/1731] drm/i915/pvc: Reset support for new copy engines
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add the reset support for new copy engines in PVC.

Bspec: 52549
Original-author: CQ Tang
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505213812.3979301-11-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c |  8 +++++
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   | 44 +++++++++++++----------
 2 files changed, 34 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 4532c3ea9ace1..c6e93db134b1e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -390,6 +390,14 @@ static u32 get_reset_domain(u8 ver, enum intel_engine_id id)
 		static const u32 engine_reset_domains[] = {
 			[RCS0]  = GEN11_GRDOM_RENDER,
 			[BCS0]  = GEN11_GRDOM_BLT,
+			[BCS1]  = XEHPC_GRDOM_BLT1,
+			[BCS2]  = XEHPC_GRDOM_BLT2,
+			[BCS3]  = XEHPC_GRDOM_BLT3,
+			[BCS4]  = XEHPC_GRDOM_BLT4,
+			[BCS5]  = XEHPC_GRDOM_BLT5,
+			[BCS6]  = XEHPC_GRDOM_BLT6,
+			[BCS7]  = XEHPC_GRDOM_BLT7,
+			[BCS8]  = XEHPC_GRDOM_BLT8,
 			[VCS0]  = GEN11_GRDOM_MEDIA,
 			[VCS1]  = GEN11_GRDOM_MEDIA2,
 			[VCS2]  = GEN11_GRDOM_MEDIA3,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index fe09288a31457..98ede9c93f000 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -597,24 +597,32 @@
 /* GEN11 changed all bit defs except for FULL & RENDER */
 #define   GEN11_GRDOM_FULL			GEN6_GRDOM_FULL
 #define   GEN11_GRDOM_RENDER			GEN6_GRDOM_RENDER
-#define   GEN11_GRDOM_BLT			(1 << 2)
-#define   GEN11_GRDOM_GUC			(1 << 3)
-#define   GEN11_GRDOM_MEDIA			(1 << 5)
-#define   GEN11_GRDOM_MEDIA2			(1 << 6)
-#define   GEN11_GRDOM_MEDIA3			(1 << 7)
-#define   GEN11_GRDOM_MEDIA4			(1 << 8)
-#define   GEN11_GRDOM_MEDIA5			(1 << 9)
-#define   GEN11_GRDOM_MEDIA6			(1 << 10)
-#define   GEN11_GRDOM_MEDIA7			(1 << 11)
-#define   GEN11_GRDOM_MEDIA8			(1 << 12)
-#define   GEN11_GRDOM_VECS			(1 << 13)
-#define   GEN11_GRDOM_VECS2			(1 << 14)
-#define   GEN11_GRDOM_VECS3			(1 << 15)
-#define   GEN11_GRDOM_VECS4			(1 << 16)
-#define   GEN11_GRDOM_SFC0			(1 << 17)
-#define   GEN11_GRDOM_SFC1			(1 << 18)
-#define   GEN11_GRDOM_SFC2			(1 << 19)
-#define   GEN11_GRDOM_SFC3			(1 << 20)
+#define   XEHPC_GRDOM_BLT8			REG_BIT(31)
+#define   XEHPC_GRDOM_BLT7			REG_BIT(30)
+#define   XEHPC_GRDOM_BLT6			REG_BIT(29)
+#define   XEHPC_GRDOM_BLT5			REG_BIT(28)
+#define   XEHPC_GRDOM_BLT4			REG_BIT(27)
+#define   XEHPC_GRDOM_BLT3			REG_BIT(26)
+#define   XEHPC_GRDOM_BLT2			REG_BIT(25)
+#define   XEHPC_GRDOM_BLT1			REG_BIT(24)
+#define   GEN11_GRDOM_SFC3			REG_BIT(20)
+#define   GEN11_GRDOM_SFC2			REG_BIT(19)
+#define   GEN11_GRDOM_SFC1			REG_BIT(18)
+#define   GEN11_GRDOM_SFC0			REG_BIT(17)
+#define   GEN11_GRDOM_VECS4			REG_BIT(16)
+#define   GEN11_GRDOM_VECS3			REG_BIT(15)
+#define   GEN11_GRDOM_VECS2			REG_BIT(14)
+#define   GEN11_GRDOM_VECS			REG_BIT(13)
+#define   GEN11_GRDOM_MEDIA8			REG_BIT(12)
+#define   GEN11_GRDOM_MEDIA7			REG_BIT(11)
+#define   GEN11_GRDOM_MEDIA6			REG_BIT(10)
+#define   GEN11_GRDOM_MEDIA5			REG_BIT(9)
+#define   GEN11_GRDOM_MEDIA4			REG_BIT(8)
+#define   GEN11_GRDOM_MEDIA3			REG_BIT(7)
+#define   GEN11_GRDOM_MEDIA2			REG_BIT(6)
+#define   GEN11_GRDOM_MEDIA			REG_BIT(5)
+#define   GEN11_GRDOM_GUC			REG_BIT(3)
+#define   GEN11_GRDOM_BLT			REG_BIT(2)
 #define   GEN11_VCS_SFC_RESET_BIT(instance)	(GEN11_GRDOM_SFC0 << ((instance) >> 1))
 #define   GEN11_VECS_SFC_RESET_BIT(instance)	(GEN11_GRDOM_SFC0 << (instance))
 
-- 
GitLab


From 1a1a5a315ee805bec457fd214250c088efadb50b Mon Sep 17 00:00:00 2001
From: Lucas De Marchi <lucas.demarchi@intel.com>
Date: Thu, 5 May 2022 14:38:11 -0700
Subject: [PATCH 0031/1731] drm/i915/pvc: skip all copy engines from aux table
 invalidate
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

As we have more copy engines now, mask all of them from aux table
invalidate.

v2 (MattR):
 - Use I915_MAX_BCS to determine mask rather than hardcoding BCS8.
   (Prathap)

Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505213812.3979301-12-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 3e13960615bde..daa1a61972f47 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -272,7 +272,8 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
 		if (!HAS_FLAT_CCS(rq->engine->i915) &&
 		    (rq->engine->class == VIDEO_DECODE_CLASS ||
 		     rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) {
-			aux_inv = rq->engine->mask & ~BIT(BCS0);
+			aux_inv = rq->engine->mask &
+				~GENMASK(_BCS(I915_MAX_BCS - 1), BCS0);
 			if (aux_inv)
 				cmd += 4;
 		}
-- 
GitLab


From ad5f74f3420183052532a220edd9a37aba92724a Mon Sep 17 00:00:00 2001
From: Lucas De Marchi <lucas.demarchi@intel.com>
Date: Thu, 5 May 2022 14:38:12 -0700
Subject: [PATCH 0032/1731] drm/i915/pvc: read fuses for link copy engines
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The new Link Copy engines in PVC may be fused off according to the
mslice_mask. Each bit of the MEML3_EN_MASK we read from the
GEN10_MIRROR_FUSE3 register disables a pair of link copy engines.

v2 (Tvrtko):
 - Minor cosmetic changes: s/u8/unsigned long/, use instance local
   variable.  (Tvrtko)

Bspec: 44483
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505213812.3979301-13-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 29 +++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index c6e93db134b1e..1adbf34c36324 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -686,6 +686,34 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
 	}
 }
 
+static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
+{
+	struct drm_i915_private *i915 = gt->i915;
+	struct intel_gt_info *info = &gt->info;
+	unsigned long meml3_mask;
+	unsigned long quad;
+
+	meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
+	meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
+
+	/*
+	 * Link Copy engines may be fused off according to meml3_mask. Each
+	 * bit is a quad that houses 2 Link Copy and two Sub Copy engines.
+	 */
+	for_each_clear_bit(quad, &meml3_mask, GEN12_MAX_MSLICES) {
+		unsigned int instance = quad * 2 + 1;
+		intel_engine_mask_t mask = GENMASK(_BCS(instance + 1),
+						   _BCS(instance));
+
+		if (mask & info->engine_mask) {
+			drm_dbg(&i915->drm, "bcs%u fused off\n", instance);
+			drm_dbg(&i915->drm, "bcs%u fused off\n", instance + 1);
+
+			info->engine_mask &= ~mask;
+		}
+	}
+}
+
 /*
  * Determine which engines are fused off in our particular hardware.
  * Note that we have a catch-22 situation where we need to be able to access
@@ -768,6 +796,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
 	GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
 
 	engine_mask_apply_compute_fuses(gt);
+	engine_mask_apply_copy_fuses(gt);
 
 	return info->engine_mask;
 }
-- 
GitLab


From ef83e1198f9f7d7db0031c839bb1112cfee45b42 Mon Sep 17 00:00:00 2001
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
Date: Wed, 4 May 2022 13:22:12 -0700
Subject: [PATCH 0033/1731] drm/i915/dmc: Load DMC on DG2

Add Support for DC states on Dg2.

v2: Add dc9 as the max supported DC states and disable DC5.
v3: set max_dc to 0. (Imre)

Cc: Imre Deak <imre.deak@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>(v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220504202213.740200-2-anusha.srivatsa@intel.com
---
 drivers/gpu/drm/i915/display/intel_display_power.c |  4 +++-
 drivers/gpu/drm/i915/display/intel_dmc.c           | 10 +++++++++-
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 1d9bd5808849f..15b15f434fcfc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -907,7 +907,9 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 	if (!HAS_DISPLAY(dev_priv))
 		return 0;
 
-	if (IS_DG1(dev_priv))
+	if (IS_DG2(dev_priv))
+		max_dc = 0;
+	else if (IS_DG1(dev_priv))
 		max_dc = 3;
 	else if (DISPLAY_VER(dev_priv) >= 12)
 		max_dc = 4;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 257cf662f9f4b..2f01aca4d9810 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -52,6 +52,10 @@
 
 #define DISPLAY_VER12_DMC_MAX_FW_SIZE	ICL_DMC_MAX_FW_SIZE
 
+#define DG2_DMC_PATH			DMC_PATH(dg2, 2, 06)
+#define DG2_DMC_VERSION_REQUIRED	DMC_VERSION(2, 06)
+MODULE_FIRMWARE(DG2_DMC_PATH);
+
 #define ADLP_DMC_PATH			DMC_PATH(adlp, 2, 16)
 #define ADLP_DMC_VERSION_REQUIRED	DMC_VERSION(2, 16)
 MODULE_FIRMWARE(ADLP_DMC_PATH);
@@ -688,7 +692,11 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
 	 */
 	intel_dmc_runtime_pm_get(dev_priv);
 
-	if (IS_ALDERLAKE_P(dev_priv)) {
+	if (IS_DG2(dev_priv)) {
+		dmc->fw_path = DG2_DMC_PATH;
+		dmc->required_version = DG2_DMC_VERSION_REQUIRED;
+		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
+	} else if (IS_ALDERLAKE_P(dev_priv)) {
 		dmc->fw_path = ADLP_DMC_PATH;
 		dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
 		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
-- 
GitLab


From 7ecc3cc8a7b39f08eee9aea7b718187583342a70 Mon Sep 17 00:00:00 2001
From: Imre Deak <imre.deak@intel.com>
Date: Tue, 10 May 2022 14:49:57 +0300
Subject: [PATCH 0034/1731] drm/i915: Fix 'mixing different enum types'
 warnings in intel_display_power.c
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Fix the following sparse warnings:

drivers/gpu/drm/i915/display/intel_display_power.c:2431:34: warning: mixing different enum types:
drivers/gpu/drm/i915/display/intel_display_power.c:2431:34:    unsigned int enum intel_display_power_domain
drivers/gpu/drm/i915/display/intel_display_power.c:2431:34:    int enum port
drivers/gpu/drm/i915/display/intel_display_power.c:2442:37: warning: mixing different enum types:
drivers/gpu/drm/i915/display/intel_display_power.c:2442:37:    unsigned int enum intel_display_power_domain
drivers/gpu/drm/i915/display/intel_display_power.c:2442:37:    int enum port
drivers/gpu/drm/i915/display/intel_display_power.c:2468:43: warning: mixing different enum types:
drivers/gpu/drm/i915/display/intel_display_power.c:2468:43:    unsigned int enum intel_display_power_domain
drivers/gpu/drm/i915/display/intel_display_power.c:2468:43:    unsigned int enum aux_ch
drivers/gpu/drm/i915/display/intel_display_power.c:2479:35: warning: mixing different enum types:
drivers/gpu/drm/i915/display/intel_display_power.c:2479:35:    unsigned int enum intel_display_power_domain
drivers/gpu/drm/i915/display/intel_display_power.c:2479:35:    unsigned int enum aux_ch

Fixes: 979e1b32e0e2 ("drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform")
Reported-by: Jani Nikula <jani.nikula@intel.com>
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220510114957.406070-1-imre.deak@intel.com
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 15b15f434fcfc..5eb8d63fb89ed 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -2430,7 +2430,7 @@ intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port)
 	if (drm_WARN_ON(&i915->drm, !domains) || domains->ddi_io == POWER_DOMAIN_INVALID)
 		return POWER_DOMAIN_PORT_DDI_IO_A;
 
-	return domains->ddi_io + port - domains->port_start;
+	return domains->ddi_io + (int)(port - domains->port_start);
 }
 
 enum intel_display_power_domain
@@ -2441,7 +2441,7 @@ intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port po
 	if (drm_WARN_ON(&i915->drm, !domains) || domains->ddi_lanes == POWER_DOMAIN_INVALID)
 		return POWER_DOMAIN_PORT_DDI_LANES_A;
 
-	return domains->ddi_lanes + port - domains->port_start;
+	return domains->ddi_lanes + (int)(port - domains->port_start);
 }
 
 static const struct intel_ddi_port_domains *
@@ -2467,7 +2467,7 @@ intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch
 	if (drm_WARN_ON(&i915->drm, !domains) || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID)
 		return POWER_DOMAIN_AUX_A;
 
-	return domains->aux_legacy_usbc + aux_ch - domains->aux_ch_start;
+	return domains->aux_legacy_usbc + (int)(aux_ch - domains->aux_ch_start);
 }
 
 enum intel_display_power_domain
@@ -2478,5 +2478,5 @@ intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch au
 	if (drm_WARN_ON(&i915->drm, !domains) || domains->aux_tbt == POWER_DOMAIN_INVALID)
 		return POWER_DOMAIN_AUX_TBT1;
 
-	return domains->aux_tbt + aux_ch - domains->aux_ch_start;
+	return domains->aux_tbt + (int)(aux_ch - domains->aux_ch_start);
 }
-- 
GitLab


From 303760aa914b7f5ac9602dbb4b471a2ad52eeb3e Mon Sep 17 00:00:00 2001
From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Date: Mon, 25 Apr 2022 17:30:45 -0700
Subject: [PATCH 0035/1731] i915/guc/reset: Make __guc_reset_context aware of
 guilty engines

There are 2 ways an engine can get reset in i915 and the method of reset
affects how KMD labels a context as guilty/innocent.

(1) GuC initiated engine-reset: GuC resets a hung engine and notifies
KMD. The context that hung on the engine is marked guilty and all other
contexts are innocent. The innocent contexts are resubmitted.

(2) GT based reset: When an engine heartbeat fails to tick, KMD
initiates a gt/chip reset. All active contexts are marked as guilty and
discarded.

In order to correctly mark the contexts as guilty/innocent, pass a mask
of engines that were reset to __guc_reset_context.

Fixes: eb5e7da736f3 ("drm/i915/guc: Reset implementation for new GuC interface")
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220426003045.3929439-1-umesh.nerlige.ramappa@intel.com
---
 drivers/gpu/drm/i915/gt/intel_reset.c            |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc.h           |  2 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c    | 16 ++++++++--------
 drivers/gpu/drm/i915/gt/uc/intel_uc.c            |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.h            |  2 +-
 5 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 894f17f8b4cea..11bf33f1f772a 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -808,7 +808,7 @@ static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
 		__intel_engine_reset(engine, stalled_mask & engine->mask);
 	local_bh_enable();
 
-	intel_uc_reset(&gt->uc, true);
+	intel_uc_reset(&gt->uc, ALL_ENGINES);
 
 	intel_ggtt_restore_fences(gt->ggtt);
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 3f3373f681235..966e69a8b1c12 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -443,7 +443,7 @@ int intel_guc_global_policies_update(struct intel_guc *guc);
 void intel_guc_context_ban(struct intel_context *ce, struct i915_request *rq);
 
 void intel_guc_submission_reset_prepare(struct intel_guc *guc);
-void intel_guc_submission_reset(struct intel_guc *guc, bool stalled);
+void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t stalled);
 void intel_guc_submission_reset_finish(struct intel_guc *guc);
 void intel_guc_submission_cancel_requests(struct intel_guc *guc);
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 8bf8b6d588d43..5a1dfacf24ea8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1654,9 +1654,9 @@ __unwind_incomplete_requests(struct intel_context *ce)
 	spin_unlock_irqrestore(&sched_engine->lock, flags);
 }
 
-static void __guc_reset_context(struct intel_context *ce, bool stalled)
+static void __guc_reset_context(struct intel_context *ce, intel_engine_mask_t stalled)
 {
-	bool local_stalled;
+	bool guilty;
 	struct i915_request *rq;
 	unsigned long flags;
 	u32 head;
@@ -1684,7 +1684,7 @@ static void __guc_reset_context(struct intel_context *ce, bool stalled)
 		if (!intel_context_is_pinned(ce))
 			goto next_context;
 
-		local_stalled = false;
+		guilty = false;
 		rq = intel_context_find_active_request(ce);
 		if (!rq) {
 			head = ce->ring->tail;
@@ -1692,14 +1692,14 @@ static void __guc_reset_context(struct intel_context *ce, bool stalled)
 		}
 
 		if (i915_request_started(rq))
-			local_stalled = true;
+			guilty = stalled & ce->engine->mask;
 
 		GEM_BUG_ON(i915_active_is_idle(&ce->active));
 		head = intel_ring_wrap(ce->ring, rq->head);
 
-		__i915_request_reset(rq, local_stalled && stalled);
+		__i915_request_reset(rq, guilty);
 out_replay:
-		guc_reset_state(ce, head, local_stalled && stalled);
+		guc_reset_state(ce, head, guilty);
 next_context:
 		if (i != number_children)
 			ce = list_next_entry(ce, parallel.child_link);
@@ -1709,7 +1709,7 @@ next_context:
 	intel_context_put(parent);
 }
 
-void intel_guc_submission_reset(struct intel_guc *guc, bool stalled)
+void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t stalled)
 {
 	struct intel_context *ce;
 	unsigned long index;
@@ -4228,7 +4228,7 @@ static void guc_context_replay(struct intel_context *ce)
 {
 	struct i915_sched_engine *sched_engine = ce->engine->sched_engine;
 
-	__guc_reset_context(ce, true);
+	__guc_reset_context(ce, ce->engine->mask);
 	tasklet_hi_schedule(&sched_engine->tasklet);
 }
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index ecf149c5fdb02..3c3527cb00075 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -597,7 +597,7 @@ sanitize:
 	__uc_sanitize(uc);
 }
 
-void intel_uc_reset(struct intel_uc *uc, bool stalled)
+void intel_uc_reset(struct intel_uc *uc, intel_engine_mask_t stalled)
 {
 	struct intel_guc *guc = &uc->guc;
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
index 866b462821c00..a8f38c2c60e23 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
@@ -42,7 +42,7 @@ void intel_uc_driver_late_release(struct intel_uc *uc);
 void intel_uc_driver_remove(struct intel_uc *uc);
 void intel_uc_init_mmio(struct intel_uc *uc);
 void intel_uc_reset_prepare(struct intel_uc *uc);
-void intel_uc_reset(struct intel_uc *uc, bool stalled);
+void intel_uc_reset(struct intel_uc *uc, intel_engine_mask_t stalled);
 void intel_uc_reset_finish(struct intel_uc *uc);
 void intel_uc_cancel_requests(struct intel_uc *uc);
 void intel_uc_suspend(struct intel_uc *uc);
-- 
GitLab


From 21c47196aec3a93f913a7515e1e7b30e6c54d6c6 Mon Sep 17 00:00:00 2001
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
Date: Tue, 10 May 2022 17:08:47 -0700
Subject: [PATCH 0036/1731] drm/i915/dmc: Add MMIO range restrictions

Bspec has added some steps that check forDMC MMIO range before
programming them

v2: Fix for CI
v3: move register defines to .h (Anusha)
- Check MMIO restrictions per pipe
- Add MMIO restricton for v1 dmc header as well (Lucas)
v4: s/_PICK/_PICK_EVEN and use it only for Pipe DMC scenario.
- clean up sanity check logic.(Lucas)
- Add MMIO range for RKL as well.(Anusha)
v5: Use DISPLAY_VER instead of per platform check (Lucas)

BSpec: 49193

Cc: stable@vger.kernel.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220511000847.1068302-1-anusha.srivatsa@intel.com
---
 drivers/gpu/drm/i915/display/intel_dmc.c      | 44 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dmc_regs.h | 18 +++++++-
 2 files changed, 61 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 2f01aca4d9810..34d00f5aff257 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -378,6 +378,44 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc,
 	}
 }
 
+static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc,
+				       const u32 *mmioaddr, u32 mmio_count,
+				       int header_ver, u8 dmc_id)
+{
+	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+	u32 start_range, end_range;
+	int i;
+
+	if (dmc_id >= DMC_FW_MAX) {
+		drm_warn(&i915->drm, "Unsupported firmware id %u\n", dmc_id);
+		return false;
+	}
+
+	if (header_ver == 1) {
+		start_range = DMC_MMIO_START_RANGE;
+		end_range = DMC_MMIO_END_RANGE;
+	} else if (dmc_id == DMC_FW_MAIN) {
+		start_range = TGL_MAIN_MMIO_START;
+		end_range = TGL_MAIN_MMIO_END;
+	} else if (DISPLAY_VER(i915) >= 13) {
+		start_range = ADLP_PIPE_MMIO_START;
+		end_range = ADLP_PIPE_MMIO_END;
+	} else if (DISPLAY_VER(i915) >= 12) {
+		start_range = TGL_PIPE_MMIO_START(dmc_id);
+		end_range = TGL_PIPE_MMIO_END(dmc_id);
+	} else {
+		drm_warn(&i915->drm, "Unknown mmio range for sanity check");
+		return false;
+	}
+
+	for (i = 0; i < mmio_count; i++) {
+		if (mmioaddr[i] < start_range || mmioaddr[i] > end_range)
+			return false;
+	}
+
+	return true;
+}
+
 static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
 			       const struct intel_dmc_header_base *dmc_header,
 			       size_t rem_size, u8 dmc_id)
@@ -447,6 +485,12 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
 		return 0;
 	}
 
+	if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count,
+					dmc_header->header_ver, dmc_id)) {
+		drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n");
+		return 0;
+	}
+
 	for (i = 0; i < mmio_count; i++) {
 		dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
 		dmc_info->mmiodata[i] = mmiodata[i];
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index d65e698832eb5..67e14eb96a7aa 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -16,7 +16,23 @@
 #define DMC_LAST_WRITE		_MMIO(0x8F034)
 #define DMC_LAST_WRITE_VALUE	0xc003b400
 #define DMC_MMIO_START_RANGE	0x80000
-#define DMC_MMIO_END_RANGE	0x8FFFF
+#define DMC_MMIO_END_RANGE     0x8FFFF
+#define DMC_V1_MMIO_START_RANGE		0x80000
+#define TGL_MAIN_MMIO_START		0x8F000
+#define TGL_MAIN_MMIO_END		0x8FFFF
+#define _TGL_PIPEA_MMIO_START		0x92000
+#define _TGL_PIPEA_MMIO_END		0x93FFF
+#define _TGL_PIPEB_MMIO_START		0x96000
+#define _TGL_PIPEB_MMIO_END		0x97FFF
+#define ADLP_PIPE_MMIO_START		0x5F000
+#define ADLP_PIPE_MMIO_END		0x5FFFF
+
+#define TGL_PIPE_MMIO_START(dmc_id)	_PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_START,\
+					      _TGL_PIPEB_MMIO_START)
+
+#define TGL_PIPE_MMIO_END(dmc_id)	_PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_END,\
+					      _TGL_PIPEB_MMIO_END)
+
 #define SKL_DMC_DC3_DC5_COUNT	_MMIO(0x80030)
 #define SKL_DMC_DC5_DC6_COUNT	_MMIO(0x8002C)
 #define BXT_DMC_DC3_DC5_COUNT	_MMIO(0x80038)
-- 
GitLab


From 18fb42db05a0b93ab5dd5eab5315e50eaa3ca620 Mon Sep 17 00:00:00 2001
From: Nathan Chancellor <nathan@kernel.org>
Date: Fri, 13 May 2022 08:51:36 +0100
Subject: [PATCH 0037/1731] drm/i915: Fix CFI violation with show_dynamic_id()

When an attribute group is created with sysfs_create_group(), the
->sysfs_ops() callback is set to kobj_sysfs_ops, which sets the ->show()
callback to kobj_attr_show(). kobj_attr_show() uses container_of() to
get the ->show() callback from the attribute it was passed, meaning the
->show() callback needs to be the same type as the ->show() callback in
'struct kobj_attribute'.

However, show_dynamic_id() has the type of the ->show() callback in
'struct device_attribute', which causes a CFI violation when opening the
'id' sysfs node under drm/card0/metrics. This happens to work because
the layout of 'struct kobj_attribute' and 'struct device_attribute' are
the same, so the container_of() cast happens to allow the ->show()
callback to still work.

Change the type of show_dynamic_id() to match the ->show() callback in
'struct kobj_attributes' and update the type of sysfs_metric_id to
match, which resolves the CFI violation.

Fixes: f89823c21224 ("drm/i915/perf: Implement I915_PERF_ADD/REMOVE_CONFIG interface")
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Reviewed-by: Kees Cook <keescook@chromium.org>
Reviewed-by: Sami Tolvanen <samitolvanen@google.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220513075136.1027007-1-tvrtko.ursulin@linux.intel.com
---
 drivers/gpu/drm/i915/i915_perf.c       | 4 ++--
 drivers/gpu/drm/i915/i915_perf_types.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 0a9c3fcc09b1e..1577ab6754db1 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4050,8 +4050,8 @@ addr_err:
 	return ERR_PTR(err);
 }
 
-static ssize_t show_dynamic_id(struct device *dev,
-			       struct device_attribute *attr,
+static ssize_t show_dynamic_id(struct kobject *kobj,
+			       struct kobj_attribute *attr,
 			       char *buf)
 {
 	struct i915_oa_config *oa_config =
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h b/drivers/gpu/drm/i915/i915_perf_types.h
index 473a3c0544bb8..05cb9a335a971 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -55,7 +55,7 @@ struct i915_oa_config {
 
 	struct attribute_group sysfs_metric;
 	struct attribute *attrs[2];
-	struct device_attribute sysfs_metric_id;
+	struct kobj_attribute sysfs_metric_id;
 
 	struct kref ref;
 	struct rcu_head rcu;
-- 
GitLab


From 945ae909aa76f55ac8c9e95feb3683512d39134a Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Thu, 12 May 2022 19:16:38 +0300
Subject: [PATCH 0038/1731] drm/i915/audio: fix audio code enable/disable pipe
 logging
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Need to use pipe_name(pipe) instead of pipe directly.

Fixes: 1f31e35f2e88 ("drm/i915/audio: unify audio codec enable/disable debug logging")
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220512161638.272601-1-jani.nikula@intel.com
---
 drivers/gpu/drm/i915/display/intel_audio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 1c87bf66b0925..f0f0dfce27ce7 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -827,7 +827,7 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
 	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Enable audio codec on pipe %c, %u bytes ELD\n",
 		    connector->base.id, connector->name,
 		    encoder->base.base.id, encoder->base.name,
-		    pipe, drm_eld_size(connector->eld));
+		    pipe_name(pipe), drm_eld_size(connector->eld));
 
 	/* FIXME precompute the ELD in .compute_config() */
 	if (!connector->eld[0])
@@ -888,7 +888,7 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
 
 	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Disable audio codec on pipe %c\n",
 		    connector->base.id, connector->name,
-		    encoder->base.base.id, encoder->base.name, pipe);
+		    encoder->base.base.id, encoder->base.name, pipe_name(pipe));
 
 	if (dev_priv->audio.funcs)
 		dev_priv->audio.funcs->audio_codec_disable(encoder,
-- 
GitLab


From ca10b9d60f8c9556720bad8b1ec7d522e353a01d Mon Sep 17 00:00:00 2001
From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Date: Thu, 5 May 2022 22:41:42 -0700
Subject: [PATCH 0039/1731] drm/i915/guc/rc: Use i915_probe_error instead of
 drm_error

To avoid false positives in error injection cases.

Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220506054142.5025-1-vinay.belgaumkar@intel.com
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
index e00661fb08531..8f8dd05835c5a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
@@ -49,7 +49,6 @@ static int guc_action_control_gucrc(struct intel_guc *guc, bool enable)
 static int __guc_rc_control(struct intel_guc *guc, bool enable)
 {
 	struct intel_gt *gt = guc_to_gt(guc);
-	struct drm_device *drm = &guc_to_gt(guc)->i915->drm;
 	int ret;
 
 	if (!intel_uc_uses_guc_rc(&gt->uc))
@@ -60,8 +59,8 @@ static int __guc_rc_control(struct intel_guc *guc, bool enable)
 
 	ret = guc_action_control_gucrc(guc, enable);
 	if (ret) {
-		drm_err(drm, "Failed to %s GuC RC (%pe)\n",
-			str_enable_disable(enable), ERR_PTR(ret));
+		i915_probe_error(guc_to_gt(guc)->i915, "Failed to %s GuC RC (%pe)\n",
+				 str_enable_disable(enable), ERR_PTR(ret));
 		return ret;
 	}
 
-- 
GitLab


From f8ef475aa069cd72e9e7bdb2d60dc6a89e2bafad Mon Sep 17 00:00:00 2001
From: Lv Ruyi <lv.ruyi@zte.com.cn>
Date: Mon, 9 May 2022 07:24:05 +0000
Subject: [PATCH 0040/1731] iio: adc: xilinx-ams: fix return error variable

Return irq instead of ret which always equals to zero here.

Fixes: d5c70627a794 ("iio: adc: Add Xilinx AMS driver")
Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: Lv Ruyi <lv.ruyi@zte.com.cn>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/xilinx-ams.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/xilinx-ams.c b/drivers/iio/adc/xilinx-ams.c
index a55396c1f8b28..a7687706012d2 100644
--- a/drivers/iio/adc/xilinx-ams.c
+++ b/drivers/iio/adc/xilinx-ams.c
@@ -1409,7 +1409,7 @@ static int ams_probe(struct platform_device *pdev)
 
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0)
-		return ret;
+		return irq;
 
 	ret = devm_request_irq(&pdev->dev, irq, &ams_irq, 0, "ams-irq",
 			       indio_dev);
-- 
GitLab


From c3e57159dea473e9e138d32d08c48f3103294050 Mon Sep 17 00:00:00 2001
From: Anshuman Gupta <anshuman.gupta@intel.com>
Date: Wed, 11 May 2022 18:34:54 +0530
Subject: [PATCH 0041/1731] drm/i915: Use drm_dbg for rpm logging

RPM suspend/resume also supported on gfx platforms which doesn't have
kms support and even on platforms without any connected display panel.
There is no good reason to log rpm suspend/resume debug message with
drm_dbg_kms() therefore changing it to drm_dbg().

Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220511130455.22028-1-anshuman.gupta@intel.com
---
 drivers/gpu/drm/i915/i915_driver.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 6a7f11ee0b9ef..30a7f4381f4b5 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1547,7 +1547,7 @@ static int intel_runtime_suspend(struct device *kdev)
 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
 		return -ENODEV;
 
-	drm_dbg_kms(&dev_priv->drm, "Suspending device\n");
+	drm_dbg(&dev_priv->drm, "Suspending device\n");
 
 	disable_rpm_wakeref_asserts(rpm);
 
@@ -1623,7 +1623,7 @@ static int intel_runtime_suspend(struct device *kdev)
 	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
 		intel_hpd_poll_enable(dev_priv);
 
-	drm_dbg_kms(&dev_priv->drm, "Device suspended\n");
+	drm_dbg(&dev_priv->drm, "Device suspended\n");
 	return 0;
 }
 
@@ -1637,7 +1637,7 @@ static int intel_runtime_resume(struct device *kdev)
 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
 		return -ENODEV;
 
-	drm_dbg_kms(&dev_priv->drm, "Resuming device\n");
+	drm_dbg(&dev_priv->drm, "Resuming device\n");
 
 	drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
 	disable_rpm_wakeref_asserts(rpm);
@@ -1681,7 +1681,7 @@ static int intel_runtime_resume(struct device *kdev)
 		drm_err(&dev_priv->drm,
 			"Runtime resume failed, disabling it (%d)\n", ret);
 	else
-		drm_dbg_kms(&dev_priv->drm, "Device resumed\n");
+		drm_dbg(&dev_priv->drm, "Device resumed\n");
 
 	return ret;
 }
-- 
GitLab


From 057a6a1936e79c0bc9c86537fb9886ed39cd078a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jouni=20H=C3=B6gander?= <jouni.hogander@intel.com>
Date: Fri, 13 May 2022 17:28:10 +0300
Subject: [PATCH 0042/1731] drm/i915/psr: Use full update In case of area
 calculation fails
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Currently we have some corner cases where area calculation fails.  For
these sel fetch area calculation ends up having update area as y1 = 0,
y2 = 4. Instead of these values safer option is full update.

One of such for example is big fb with offset. We don't have usable
offset in psr2_sel_fetch_update. Currently it's open what is the
proper way to fix this corner case. Use full update for now.

v2: Commit message modified
v3: Print out debug info once when area calculation fails
v4: Use drm_info_once
v5: pipeA -> "pipe %c", pipe_name(crtc-pipe)

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220513142811.779331-2-jouni.hogander@intel.com
---
 drivers/gpu/drm/i915/display/intel_psr.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 06db407e2749f..fecdaaeac39e0 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1685,6 +1685,7 @@ static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *c
 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 				struct intel_crtc *crtc)
 {
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 };
 	struct intel_plane_state *new_plane_state, *old_plane_state;
@@ -1770,6 +1771,19 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 		clip_area_update(&pipe_clip, &damaged_area);
 	}
 
+	/*
+	 * TODO: For now we are just using full update in case
+	 * selective fetch area calculation fails. To optimize this we
+	 * should identify cases where this happens and fix the area
+	 * calculation for those.
+	 */
+	if (pipe_clip.y1 == -1) {
+		drm_info_once(&dev_priv->drm,
+			      "Selective fetch area calculation failed in pipe %c\n",
+			      pipe_name(crtc->pipe));
+		full_update = true;
+	}
+
 	if (full_update)
 		goto skip_sel_fetch_set_loop;
 
-- 
GitLab


From d6774b8c3c5813aa541c9148f641d3d8d4b296d2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jouni=20H=C3=B6gander?= <jouni.hogander@intel.com>
Date: Fri, 13 May 2022 17:28:11 +0300
Subject: [PATCH 0043/1731] drm/i915: Ensure damage clip area is within pipe
 area
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Current update area calculation is not handling situation where
e.g. cursor plane is fully or partially outside pipe area.

Fix this by checking damage area against pipe_src area using
drm_rect_intersect.

v2: Set x1 and x2 in damaged_area initialization
v3: Move drm_rect_intersect into clip_area_update
v4: draw_area -> pipe_src

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5440
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220513142811.779331-3-jouni.hogander@intel.com
---
 drivers/gpu/drm/i915/display/intel_psr.c | 23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index fecdaaeac39e0..36356893c7caf 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1618,8 +1618,12 @@ exit:
 }
 
 static void clip_area_update(struct drm_rect *overlap_damage_area,
-			     struct drm_rect *damage_area)
+			     struct drm_rect *damage_area,
+			     struct drm_rect *pipe_src)
 {
+	if (!drm_rect_intersect(damage_area, pipe_src))
+		return;
+
 	if (overlap_damage_area->y1 == -1) {
 		overlap_damage_area->y1 = damage_area->y1;
 		overlap_damage_area->y2 = damage_area->y2;
@@ -1709,7 +1713,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 	 */
 	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
 					     new_plane_state, i) {
-		struct drm_rect src, damaged_area = { .y1 = -1 };
+		struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1,
+						      .x2 = INT_MAX };
 		struct drm_atomic_helper_damage_iter iter;
 		struct drm_rect clip;
 
@@ -1736,20 +1741,23 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 			if (old_plane_state->uapi.visible) {
 				damaged_area.y1 = old_plane_state->uapi.dst.y1;
 				damaged_area.y2 = old_plane_state->uapi.dst.y2;
-				clip_area_update(&pipe_clip, &damaged_area);
+				clip_area_update(&pipe_clip, &damaged_area,
+						 &crtc_state->pipe_src);
 			}
 
 			if (new_plane_state->uapi.visible) {
 				damaged_area.y1 = new_plane_state->uapi.dst.y1;
 				damaged_area.y2 = new_plane_state->uapi.dst.y2;
-				clip_area_update(&pipe_clip, &damaged_area);
+				clip_area_update(&pipe_clip, &damaged_area,
+						 &crtc_state->pipe_src);
 			}
 			continue;
 		} else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) {
 			/* If alpha changed mark the whole plane area as damaged */
 			damaged_area.y1 = new_plane_state->uapi.dst.y1;
 			damaged_area.y2 = new_plane_state->uapi.dst.y2;
-			clip_area_update(&pipe_clip, &damaged_area);
+			clip_area_update(&pipe_clip, &damaged_area,
+					 &crtc_state->pipe_src);
 			continue;
 		}
 
@@ -1760,7 +1768,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 						   &new_plane_state->uapi);
 		drm_atomic_for_each_plane_damage(&iter, &clip) {
 			if (drm_rect_intersect(&clip, &src))
-				clip_area_update(&damaged_area, &clip);
+				clip_area_update(&damaged_area, &clip,
+						 &crtc_state->pipe_src);
 		}
 
 		if (damaged_area.y1 == -1)
@@ -1768,7 +1777,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 
 		damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1;
 		damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1;
-		clip_area_update(&pipe_clip, &damaged_area);
+		clip_area_update(&pipe_clip, &damaged_area, &crtc_state->pipe_src);
 	}
 
 	/*
-- 
GitLab


From d158367c31f0f87567d2e8a0955287dc005d40e5 Mon Sep 17 00:00:00 2001
From: Nirmoy Das <nirmoy.das@intel.com>
Date: Wed, 11 May 2022 17:37:44 +0200
Subject: [PATCH 0044/1731] drm/i915: return -EIO on lmem setup failure

Caller of setup_lmem() ignores -ENODEV but failing
to setup lmem on dGPU isn't ignorable error.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220511153746.14142-1-nirmoy.das@intel.com
---
 drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index f5111c0a00605..5a7c403d718af 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -108,7 +108,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
 		flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT) * SZ_64K;
 
 		if (GEM_WARN_ON(lmem_size < flat_ccs_base))
-			return ERR_PTR(-ENODEV);
+			return ERR_PTR(-EIO);
 
 		tile_stolen = lmem_size - flat_ccs_base;
 
@@ -131,7 +131,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
 	io_start = pci_resource_start(pdev, 2);
 	io_size = min(pci_resource_len(pdev, 2), lmem_size);
 	if (!io_size)
-		return ERR_PTR(-ENODEV);
+		return ERR_PTR(-EIO);
 
 	min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
 						I915_GTT_PAGE_SIZE_4K;
-- 
GitLab


From 8f6de23184452793e60945a26ac40db435d7798d Mon Sep 17 00:00:00 2001
From: Nirmoy Das <nirmoy.das@intel.com>
Date: Wed, 11 May 2022 17:37:45 +0200
Subject: [PATCH 0045/1731] drm/i915: determine lmem_size properly

Determine lmem_size using ADDR_RANGE register so that lmem_setup()
works on platform with small-bar as well.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220511153746.14142-2-nirmoy.das@intel.com
---
 drivers/gpu/drm/i915/gt/intel_region_lmem.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 5a7c403d718af..cd105ec104299 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -101,9 +101,13 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
 		return ERR_PTR(-ENODEV);
 
 	if (HAS_FLAT_CCS(i915)) {
+		resource_size_t lmem_range;
 		u64 tile_stolen, flat_ccs_base;
 
-		lmem_size = pci_resource_len(pdev, 2);
+		lmem_range = intel_gt_read_register(&i915->gt0, XEHPSDV_TILE0_ADDR_RANGE) & 0xFFFF;
+		lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT;
+		lmem_size *= SZ_1G;
+
 		flat_ccs_base = intel_gt_read_register(gt, XEHPSDV_FLAT_CCS_BASE_ADDR);
 		flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT) * SZ_64K;
 
-- 
GitLab


From 9e97c46f832d4669b4e52cde5ad0bd43423504eb Mon Sep 17 00:00:00 2001
From: Nirmoy Das <nirmoy.das@intel.com>
Date: Wed, 11 May 2022 17:37:46 +0200
Subject: [PATCH 0046/1731] drm/i915: gracefully error out on platform with
 small-bar

Currently we just fatally crash during module load if we encounter
small-BAR configuration on DG2. We have most of the support already, but
we lack the final uAPI bits to tie it all together.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
[mauld: reword the commit and error message slightly]
Link: https://patchwork.freedesktop.org/patch/msgid/20220511153746.14142-3-nirmoy.das@intel.com
---
 drivers/gpu/drm/i915/gt/intel_region_lmem.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index cd105ec104299..e9c12e0d6f59f 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -111,6 +111,12 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
 		flat_ccs_base = intel_gt_read_register(gt, XEHPSDV_FLAT_CCS_BASE_ADDR);
 		flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT) * SZ_64K;
 
+		/* FIXME: Remove this when we have small-bar enabled */
+		if (pci_resource_len(pdev, 2) < lmem_size) {
+			drm_err(&i915->drm, "System requires small-BAR support, which is currently unsupported on this kernel\n");
+			return ERR_PTR(-EINVAL);
+		}
+
 		if (GEM_WARN_ON(lmem_size < flat_ccs_base))
 			return ERR_PTR(-EIO);
 
-- 
GitLab


From e180a7b218487065efd9a3f05eac5de7de128e19 Mon Sep 17 00:00:00 2001
From: Alan Previn <alan.previn.teres.alexis@intel.com>
Date: Fri, 6 May 2022 21:58:47 -0700
Subject: [PATCH 0047/1731] drm/i915/guc: Remove unnecessary GuC err capture
 noise

GuC error capture blurts some debug messages about empty
register lists for certain register types on engines during
firmware initialization.

These are not errors or warnings, so get rid of them.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220507045847.862261-2-alan.previn.teres.alexis@intel.com
---
 .../gpu/drm/i915/gt/uc/intel_guc_capture.c    | 77 +------------------
 1 file changed, 2 insertions(+), 75 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index c4e25966d3e9f..97a32e610c303 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -420,72 +420,6 @@ guc_capture_get_device_reglist(struct intel_guc *guc)
 	return default_lists;
 }
 
-static const char *
-__stringify_owner(u32 owner)
-{
-	switch (owner) {
-	case GUC_CAPTURE_LIST_INDEX_PF:
-		return "PF";
-	case GUC_CAPTURE_LIST_INDEX_VF:
-		return "VF";
-	default:
-		return "unknown";
-	}
-
-	return "";
-}
-
-static const char *
-__stringify_type(u32 type)
-{
-	switch (type) {
-	case GUC_CAPTURE_LIST_TYPE_GLOBAL:
-		return "Global";
-	case GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS:
-		return "Class";
-	case GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE:
-		return "Instance";
-	default:
-		return "unknown";
-	}
-
-	return "";
-}
-
-static const char *
-__stringify_engclass(u32 class)
-{
-	switch (class) {
-	case GUC_RENDER_CLASS:
-		return "Render";
-	case GUC_VIDEO_CLASS:
-		return "Video";
-	case GUC_VIDEOENHANCE_CLASS:
-		return "VideoEnhance";
-	case GUC_BLITTER_CLASS:
-		return "Blitter";
-	case GUC_COMPUTE_CLASS:
-		return "Compute";
-	default:
-		return "unknown";
-	}
-
-	return "";
-}
-
-static void
-guc_capture_warn_with_list_info(struct drm_i915_private *i915, char *msg,
-				u32 owner, u32 type, u32 classid)
-{
-	if (type == GUC_CAPTURE_LIST_TYPE_GLOBAL)
-		drm_dbg(&i915->drm, "GuC-capture: %s for %s %s-Registers.\n", msg,
-			__stringify_owner(owner), __stringify_type(type));
-	else
-		drm_dbg(&i915->drm, "GuC-capture: %s for %s %s-Registers on %s-Engine\n", msg,
-			__stringify_owner(owner), __stringify_type(type),
-			__stringify_engclass(classid));
-}
-
 static int
 guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
 		      struct guc_mmio_reg *ptr, u16 num_entries)
@@ -501,11 +435,8 @@ guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
 		return -ENODEV;
 
 	match = guc_capture_get_one_list(reglists, owner, type, classid);
-	if (!match) {
-		guc_capture_warn_with_list_info(i915, "Missing register list init", owner, type,
-						classid);
+	if (!match)
 		return -ENODATA;
-	}
 
 	for (i = 0; i < num_entries && i < match->num_regs; ++i) {
 		ptr[i].offset = match->list[i].reg.reg;
@@ -556,7 +487,6 @@ int
 intel_guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
 			      size_t *size)
 {
-	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
 	struct intel_guc_state_capture *gc = guc->capture;
 	struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid];
 	int num_regs;
@@ -570,11 +500,8 @@ intel_guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 cl
 	}
 
 	num_regs = guc_cap_list_num_regs(gc, owner, type, classid);
-	if (!num_regs) {
-		guc_capture_warn_with_list_info(i915, "Missing register list size",
-						owner, type, classid);
+	if (!num_regs)
 		return -ENODATA;
-	}
 
 	*size = PAGE_ALIGN((sizeof(struct guc_debug_capture_list)) +
 			   (num_regs * sizeof(struct guc_mmio_reg)));
-- 
GitLab


From a50794f26f52c66cb793d5d392f5f19bc2962cdd Mon Sep 17 00:00:00 2001
From: Ramalingam C <ramalingam.c@intel.com>
Date: Mon, 2 May 2022 19:45:08 +0530
Subject: [PATCH 0048/1731] uapi/drm/i915: Document memory residency and
 Flat-CCS capability of obj

Capture the impact of memory region preference list of the objects, on
their memory residency and Flat-CCS capability.

v2:
  Fix the Flat-CCS capability of an obj with {lmem, smem} preference
  list [Thomas]
v3:
  Reworded the doc [Matt]
v4:
  Fixed Typos and spelling mistakes [Tvrtko, Joonas]

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
cc: Matthew Auld <matthew.auld@intel.com>
cc: Thomas Hellstrom <thomas.hellstrom@linux.intel.com>
cc: Daniel Vetter <daniel.vetter@ffwll.ch>
cc: Jon Bloomfield <jon.bloomfield@intel.com>
cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
cc: Kenneth Graunke <kenneth@whitecape.org>
cc: mesa-dev@lists.freedesktop.org
cc: Jordan Justen <jordan.l.justen@intel.com>
cc: Tony Ye <tony.ye@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220502141508.2327-1-ramalingam.c@intel.com
---
 include/uapi/drm/i915_drm.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index a2def7b270097..de49b68b4fc87 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -3443,6 +3443,22 @@ struct drm_i915_gem_create_ext {
  * At which point we get the object handle in &drm_i915_gem_create_ext.handle,
  * along with the final object size in &drm_i915_gem_create_ext.size, which
  * should account for any rounding up, if required.
+ *
+ * Note that userspace has no means of knowing the current backing region
+ * for objects where @num_regions is larger than one. The kernel will only
+ * ensure that the priority order of the @regions array is honoured, either
+ * when initially placing the object, or when moving memory around due to
+ * memory pressure
+ *
+ * On Flat-CCS capable HW, compression is supported for the objects residing
+ * in I915_MEMORY_CLASS_DEVICE. When such objects (compressed) have other
+ * memory class in @regions and migrated (by i915, due to memory
+ * constraints) to the non I915_MEMORY_CLASS_DEVICE region, then i915 needs to
+ * decompress the content. But i915 doesn't have the required information to
+ * decompress the userspace compressed objects.
+ *
+ * So i915 supports Flat-CCS, on the objects which can reside only on
+ * I915_MEMORY_CLASS_DEVICE regions.
  */
 struct drm_i915_gem_create_ext_memory_regions {
 	/** @base: Extension link. See struct i915_user_extension. */
-- 
GitLab


From 451374eef622fca6f00eeeda89aaccb45a30a149 Mon Sep 17 00:00:00 2001
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Date: Wed, 11 May 2022 13:52:19 +0200
Subject: [PATCH 0049/1731] drm/i915: Use i915_gem_object_ggtt_pin_ww for
 reloc_iomap
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When removing short term pins, I've changed the the batch buffer
pinning for relocation to use __i915_vma_pin, because
i915_gem_object_ggtt_pin_ww was destroying the old vma. This
caused regressions, because the functions are not identical.

Fix the regressions by calling i915_gem_object_ggtt_pin_ww() again
on ggtt-only platforms, but only if the batch can be pinned without
being moved.

Fixes: b5cfe6f7a6e1 ("drm/i915: Remove short-term pins from execbuf, v6.")
Cc: Matthew Auld <matthew.auld@intel.com>
Reported-by: Mateusz Jończyk <mat.jonczyk@o2.pl>
Tested-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Acked-by: Matthew Auld <matthew.auld@intel.com>
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5806
Link: https://patchwork.freedesktop.org/patch/msgid/20220511115219.46507-1-maarten.lankhorst@linux.intel.com
---
 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index b3383e047505b..c326bd2b444fc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1251,14 +1251,12 @@ static void *reloc_iomap(struct i915_vma *batch,
 		 * Only attempt to pin the batch buffer to ggtt if the current batch
 		 * is not inside ggtt, or the batch buffer is not misplaced.
 		 */
-		if (!i915_is_ggtt(batch->vm)) {
+		if (!i915_is_ggtt(batch->vm) ||
+		    !i915_vma_misplaced(batch, 0, 0, PIN_MAPPABLE)) {
 			vma = i915_gem_object_ggtt_pin_ww(obj, &eb->ww, NULL, 0, 0,
 							  PIN_MAPPABLE |
 							  PIN_NONBLOCK /* NOWARN */ |
 							  PIN_NOEVICT);
-		} else if (i915_vma_is_map_and_fenceable(batch)) {
-			__i915_vma_pin(batch);
-			vma = batch;
 		}
 
 		if (vma == ERR_PTR(-EDEADLK))
-- 
GitLab


From 1ade30812abfdd1c161a155fd54b0dd594c217ee Mon Sep 17 00:00:00 2001
From: Andi Shyti <andi.shyti@linux.intel.com>
Date: Tue, 10 May 2022 16:04:47 +0200
Subject: [PATCH 0050/1731] drm/i915/gt: Fix use of static in macro mismatch

The INTEL_GT_RPS_SYSFS_ATTR was creating to different structures
but. When called with the "static" keyword this is affecting only
the first structure, while the second is created as non static.

Move the static keyword inside the macros to affect both the
structures.

Reported-by: Jani Nikula <jani.nikula@linux.intel.com>
Fixes: 56a709cf77468 ("drm/i915/gt: Create per-tile RPS sysfs interfaces")
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220510140447.80200-1-andi.shyti@linux.intel.com
---
 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index e92990d514b24..f76b6cf8040ec 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -457,22 +457,23 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *dev,
 }
 
 #define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store) \
-	struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, _show, _store); \
-	struct device_attribute dev_attr_rps_##_name = __ATTR(rps_##_name, _mode, _show, _store)
+	static struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, _show, _store); \
+	static struct device_attribute dev_attr_rps_##_name = __ATTR(rps_##_name, _mode, _show, _store)
 
 #define INTEL_GT_RPS_SYSFS_ATTR_RO(_name)				\
 		INTEL_GT_RPS_SYSFS_ATTR(_name, 0444, _name##_show, NULL)
 #define INTEL_GT_RPS_SYSFS_ATTR_RW(_name)				\
 		INTEL_GT_RPS_SYSFS_ATTR(_name, 0644, _name##_show, _name##_store)
 
-static INTEL_GT_RPS_SYSFS_ATTR_RO(act_freq_mhz);
-static INTEL_GT_RPS_SYSFS_ATTR_RO(cur_freq_mhz);
-static INTEL_GT_RPS_SYSFS_ATTR_RW(boost_freq_mhz);
-static INTEL_GT_RPS_SYSFS_ATTR_RO(RP0_freq_mhz);
-static INTEL_GT_RPS_SYSFS_ATTR_RO(RP1_freq_mhz);
-static INTEL_GT_RPS_SYSFS_ATTR_RO(RPn_freq_mhz);
-static INTEL_GT_RPS_SYSFS_ATTR_RW(max_freq_mhz);
-static INTEL_GT_RPS_SYSFS_ATTR_RW(min_freq_mhz);
+/* The below macros generate static structures */
+INTEL_GT_RPS_SYSFS_ATTR_RO(act_freq_mhz);
+INTEL_GT_RPS_SYSFS_ATTR_RO(cur_freq_mhz);
+INTEL_GT_RPS_SYSFS_ATTR_RW(boost_freq_mhz);
+INTEL_GT_RPS_SYSFS_ATTR_RO(RP0_freq_mhz);
+INTEL_GT_RPS_SYSFS_ATTR_RO(RP1_freq_mhz);
+INTEL_GT_RPS_SYSFS_ATTR_RO(RPn_freq_mhz);
+INTEL_GT_RPS_SYSFS_ATTR_RW(max_freq_mhz);
+INTEL_GT_RPS_SYSFS_ATTR_RW(min_freq_mhz);
 
 static DEVICE_ATTR_RO(vlv_rpe_freq_mhz);
 
-- 
GitLab


From 230fb39ff7e07bd0324c87acf08dd2c9b0bbcea8 Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Wed, 18 May 2022 14:33:14 +0300
Subject: [PATCH 0051/1731] drm/i915/reg: fix undefined behavior due to shift
 overflowing the constant
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Use REG_GENMASK() and REG_FIELD_PREP() to avoid errors due to
-fsanitize=shift.

References: https://lore.kernel.org/r/20220405151517.29753-12-bp@alien8.de
Reported-by: Borislav Petkov <bp@suse.de>
Reported-by: Ruiqi GONG <gongruiqi1@huawei.com>
Cc: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220518113315.1305027-1-jani.nikula@intel.com
---
 drivers/gpu/drm/i915/i915_reg.h | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c997bd604c499..9ad5938105375 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7546,25 +7546,25 @@ enum skl_power_gate {
 #define _PORT_CLK_SEL_A			0x46100
 #define _PORT_CLK_SEL_B			0x46104
 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
-#define  PORT_CLK_SEL_LCPLL_2700	(0 << 29)
-#define  PORT_CLK_SEL_LCPLL_1350	(1 << 29)
-#define  PORT_CLK_SEL_LCPLL_810		(2 << 29)
-#define  PORT_CLK_SEL_SPLL		(3 << 29)
-#define  PORT_CLK_SEL_WRPLL(pll)	(((pll) + 4) << 29)
-#define  PORT_CLK_SEL_WRPLL1		(4 << 29)
-#define  PORT_CLK_SEL_WRPLL2		(5 << 29)
-#define  PORT_CLK_SEL_NONE		(7 << 29)
-#define  PORT_CLK_SEL_MASK		(7 << 29)
+#define  PORT_CLK_SEL_MASK		REG_GENMASK(31, 29)
+#define  PORT_CLK_SEL_LCPLL_2700	REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0)
+#define  PORT_CLK_SEL_LCPLL_1350	REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1)
+#define  PORT_CLK_SEL_LCPLL_810		REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2)
+#define  PORT_CLK_SEL_SPLL		REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3)
+#define  PORT_CLK_SEL_WRPLL(pll)	REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll))
+#define  PORT_CLK_SEL_WRPLL1		REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4)
+#define  PORT_CLK_SEL_WRPLL2		REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5)
+#define  PORT_CLK_SEL_NONE		REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7)
 
 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
 #define DDI_CLK_SEL(port)		PORT_CLK_SEL(port)
-#define  DDI_CLK_SEL_NONE		(0x0 << 28)
-#define  DDI_CLK_SEL_MG			(0x8 << 28)
-#define  DDI_CLK_SEL_TBT_162		(0xC << 28)
-#define  DDI_CLK_SEL_TBT_270		(0xD << 28)
-#define  DDI_CLK_SEL_TBT_540		(0xE << 28)
-#define  DDI_CLK_SEL_TBT_810		(0xF << 28)
-#define  DDI_CLK_SEL_MASK		(0xF << 28)
+#define  DDI_CLK_SEL_MASK		REG_GENMASK(31, 28)
+#define  DDI_CLK_SEL_NONE		REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0)
+#define  DDI_CLK_SEL_MG			REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8)
+#define  DDI_CLK_SEL_TBT_162		REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC)
+#define  DDI_CLK_SEL_TBT_270		REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD)
+#define  DDI_CLK_SEL_TBT_540		REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE)
+#define  DDI_CLK_SEL_TBT_810		REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF)
 
 /* Transcoder clock selection */
 #define _TRANS_CLK_SEL_A		0x46140
-- 
GitLab


From 962bd34bb457f6353f333ce234c3fd34cad1c00a Mon Sep 17 00:00:00 2001
From: Borislav Petkov <bp@suse.de>
Date: Wed, 18 May 2022 14:33:15 +0300
Subject: [PATCH 0052/1731] drm/i915/uc: Fix undefined behavior due to shift
 overflowing the constant
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Fix:

  In file included from <command-line>:0:0:
  drivers/gpu/drm/i915/gt/uc/intel_guc.c: In function ‘intel_guc_send_mmio’:
  ././include/linux/compiler_types.h:352:38: error: call to ‘__compiletime_assert_1047’ \
  declared with attribute error: FIELD_PREP: mask is not constant
    _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)

and other build errors due to shift overflowing values.

See https://lore.kernel.org/r/YkwQ6%2BtIH8GQpuct@zn.tnic for the gory
details as to why it triggers with older gccs only.

v2 by Jani:
- Drop the i915_reg.h changes

Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Ruiqi GONG <gongruiqi1@huawei.com>
Cc: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220518113315.1305027-2-jani.nikula@intel.com
---
 drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h           | 2 +-
 drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h | 2 +-
 drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h          | 2 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h                 | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index be9ac47fa9d07..4ef9990ed7f8b 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -50,7 +50,7 @@
 
 #define HOST2GUC_SELF_CFG_REQUEST_MSG_LEN		(GUC_HXG_REQUEST_MSG_MIN_LEN + 3u)
 #define HOST2GUC_SELF_CFG_REQUEST_MSG_0_MBZ		GUC_HXG_REQUEST_MSG_0_DATA0
-#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY		(0xffff << 16)
+#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY		(0xffffU << 16)
 #define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN		(0xffff << 0)
 #define HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32		GUC_HXG_REQUEST_MSG_n_DATAn
 #define HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64		GUC_HXG_REQUEST_MSG_n_DATAn
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
index c9086a600bce5..df83c1cc7c7a6 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
@@ -82,7 +82,7 @@ static_assert(sizeof(struct guc_ct_buffer_desc) == 64);
 #define GUC_CTB_HDR_LEN				1u
 #define GUC_CTB_MSG_MIN_LEN			GUC_CTB_HDR_LEN
 #define GUC_CTB_MSG_MAX_LEN			256u
-#define GUC_CTB_MSG_0_FENCE			(0xffff << 16)
+#define GUC_CTB_MSG_0_FENCE			(0xffffU << 16)
 #define GUC_CTB_MSG_0_FORMAT			(0xf << 12)
 #define   GUC_CTB_FORMAT_HXG			0u
 #define GUC_CTB_MSG_0_RESERVED			(0xf << 8)
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h
index 29ac823acd4c7..7d5ba4d97d708 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h
@@ -40,7 +40,7 @@
  */
 
 #define GUC_HXG_MSG_MIN_LEN			1u
-#define GUC_HXG_MSG_0_ORIGIN			(0x1 << 31)
+#define GUC_HXG_MSG_0_ORIGIN			(0x1U << 31)
 #define   GUC_HXG_ORIGIN_HOST			0u
 #define   GUC_HXG_ORIGIN_GUC			1u
 #define GUC_HXG_MSG_0_TYPE			(0x7 << 28)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
index 2516705b9f365..8dc063f087eb1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
@@ -28,7 +28,7 @@
 #define   GS_MIA_HALT_REQUESTED		  (0x02 << GS_MIA_SHIFT)
 #define   GS_MIA_ISR_ENTRY		  (0x04 << GS_MIA_SHIFT)
 #define   GS_AUTH_STATUS_SHIFT		30
-#define   GS_AUTH_STATUS_MASK		  (0x03 << GS_AUTH_STATUS_SHIFT)
+#define   GS_AUTH_STATUS_MASK		  (0x03U << GS_AUTH_STATUS_SHIFT)
 #define   GS_AUTH_STATUS_BAD		  (0x01 << GS_AUTH_STATUS_SHIFT)
 #define   GS_AUTH_STATUS_GOOD		  (0x02 << GS_AUTH_STATUS_SHIFT)
 
-- 
GitLab


From 411d44d754739a371999412606b28af1d72a210b Mon Sep 17 00:00:00 2001
From: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
Date: Tue, 17 May 2022 14:29:05 -0700
Subject: [PATCH 0053/1731] drm/i915/dg2: Add workaround 22014600077

Signed-off-by: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220517212905.24212-1-swathi.dhanavanthri@intel.com
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h     |  1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 ++++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 98ede9c93f000..7246eb870c7e3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1068,6 +1068,7 @@
 #define   GEN9_ENABLE_GPGPU_PREEMPTION		REG_BIT(2)
 
 #define GEN10_CACHE_MODE_SS			_MMIO(0xe420)
+#define   ENABLE_EU_COUNT_FOR_TDL_FLUSH		REG_BIT(10)
 #define   ENABLE_PREFETCH_INTO_IC		REG_BIT(3)
 #define   FLOAT_BLEND_OPTIMIZATION_ENABLE	REG_BIT(4)
 
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 756807c4b405e..73b59ea6fd3bc 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2178,6 +2178,16 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 		wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB);
 	}
 
+	if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_B0, STEP_FOREVER) ||
+	    IS_DG2_G10(i915)) {
+		/* Wa_22014600077:dg2 */
+		wa_add(wal, GEN10_CACHE_MODE_SS, 0,
+		       _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH),
+		       0 /* Wa_14012342262 :write-only reg, so skip
+			    verification */,
+		       true);
+	}
+
 	if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
 	    IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
 		/*
-- 
GitLab


From 7f73b371710edaee1f40d834096c07c62e51b184 Mon Sep 17 00:00:00 2001
From: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
Date: Tue, 17 May 2022 13:13:38 -0700
Subject: [PATCH 0054/1731] drm/i915/dg2: Extend Wa_22010954014 to DG2-G11 and
 DG2-G12

Signed-off-by: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220517201338.7291-1-swathi.dhanavanthri@intel.com
---
 drivers/gpu/drm/i915/intel_pm.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 594ab59e4991a..b3a5c3f5ce141 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7494,10 +7494,9 @@ static void xehpsdv_init_clock_gating(struct drm_i915_private *dev_priv)
 
 static void dg2_init_clock_gating(struct drm_i915_private *i915)
 {
-	/* Wa_22010954014:dg2_g10 */
-	if (IS_DG2_G10(i915))
-		intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0,
-				 SGSI_SIDECLK_DIS);
+	/* Wa_22010954014:dg2 */
+	intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0,
+			 SGSI_SIDECLK_DIS);
 
 	/*
 	 * Wa_14010733611:dg2_g10
-- 
GitLab


From 9602efab9f8652ef39dc2789edcd26c3d1d3f901 Mon Sep 17 00:00:00 2001
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date: Thu, 19 May 2022 10:07:56 +0100
Subject: [PATCH 0055/1731] Revert "drm/i915: Drop has_psr from device info"

This reverts commit b15a7357a84f091fde8ce35bf2fd494150ad4bd0.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220519090802.1294691-2-tvrtko.ursulin@linux.intel.com
---
 drivers/gpu/drm/i915/i915_drv.h          | 2 +-
 drivers/gpu/drm/i915/i915_pci.c          | 3 +++
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9c0a8c86876a8..52695e7f60d21 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1297,7 +1297,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 					  IS_HASWELL(dev_priv))
 #define HAS_DP_MST(dev_priv)		 (HAS_DDI(dev_priv))
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
-#define HAS_PSR(dev_priv)		 (DISPLAY_VER(dev_priv) >= 9)
+#define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
 #define HAS_PSR_HW_TRACKING(dev_priv) \
 	(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
 #define HAS_PSR2_SEL_FETCH(dev_priv)	 (DISPLAY_VER(dev_priv) >= 12)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 0e1d0493d3fe8..5ceca6d99f261 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -635,6 +635,7 @@ static const struct intel_device_info chv_info = {
 	.display.has_dmc = 1, \
 	.display.has_hdcp = 1, \
 	.display.has_ipc = 1, \
+	.display.has_psr = 1, \
 	.display.has_psr_hw_tracking = 1, \
 	.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
 	.dbuf.slice_mask = BIT(DBUF_S1)
@@ -683,6 +684,7 @@ static const struct intel_device_info skl_gt4_info = {
 	.display.has_fpga_dbg = 1, \
 	.display.fbc_mask = BIT(INTEL_FBC_A), \
 	.display.has_hdcp = 1, \
+	.display.has_psr = 1, \
 	.display.has_psr_hw_tracking = 1, \
 	.has_runtime_pm = 1, \
 	.display.has_dmc = 1, \
@@ -934,6 +936,7 @@ static const struct intel_device_info adl_s_info = {
 	.display.has_hdcp = 1,							\
 	.display.has_hotplug = 1,						\
 	.display.has_ipc = 1,							\
+	.display.has_psr = 1,							\
 	.display.ver = 13,							\
 	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),	\
 	.pipe_offsets = {							\
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 55f40fa0ea49a..9dbaa2861fa15 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -173,6 +173,7 @@ enum intel_ppgtt_type {
 	func(has_ipc); \
 	func(has_modular_fia); \
 	func(has_overlay); \
+	func(has_psr); \
 	func(has_psr_hw_tracking); \
 	func(overlay_needs_physical); \
 	func(supports_tv);
-- 
GitLab


From e91eec9128c2ad9eab9cf9d7c17f8034b6a86c4c Mon Sep 17 00:00:00 2001
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date: Thu, 19 May 2022 10:07:57 +0100
Subject: [PATCH 0056/1731] Revert "drm/i915: Drop has_dp_mst from device info"

This reverts commit eb86f645ab9b90c47de7ebe229feae7ac999421b.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220519090802.1294691-3-tvrtko.ursulin@linux.intel.com
---
 drivers/gpu/drm/i915/i915_drv.h          | 2 +-
 drivers/gpu/drm/i915/i915_pci.c          | 3 +++
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 52695e7f60d21..680b7ff8c5579 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1289,13 +1289,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
 
+#define HAS_DP_MST(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dp_mst)
 #define HAS_DP20(dev_priv)	(IS_DG2(dev_priv))
 
 #define HAS_CDCLK_CRAWL(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
 #define HAS_DDI(dev_priv)		 (DISPLAY_VER(dev_priv) >= 9 || \
 					  IS_BROADWELL(dev_priv) || \
 					  IS_HASWELL(dev_priv))
-#define HAS_DP_MST(dev_priv)		 (HAS_DDI(dev_priv))
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
 #define HAS_PSR_HW_TRACKING(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 5ceca6d99f261..5870f7daa72e0 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -536,6 +536,7 @@ static const struct intel_device_info vlv_info = {
 	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
 	.display.has_fpga_dbg = 1, \
+	.display.has_dp_mst = 1, \
 	.has_rc6p = 0 /* RC6p removed-by HSW */, \
 	HSW_PIPE_OFFSETS, \
 	.has_runtime_pm = 1
@@ -689,6 +690,7 @@ static const struct intel_device_info skl_gt4_info = {
 	.has_runtime_pm = 1, \
 	.display.has_dmc = 1, \
 	.has_rps = true, \
+	.display.has_dp_mst = 1, \
 	.has_logical_ring_contexts = 1, \
 	.dma_mask_size = 39, \
 	.ppgtt_type = INTEL_PPGTT_FULL, \
@@ -929,6 +931,7 @@ static const struct intel_device_info adl_s_info = {
 	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |		\
 		BIT(DBUF_S4),							\
 	.display.has_dmc = 1,							\
+	.display.has_dp_mst = 1,						\
 	.display.has_dsb = 1,							\
 	.display.has_dsc = 1,							\
 	.display.fbc_mask = BIT(INTEL_FBC_A),					\
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 9dbaa2861fa15..6194dcc18e4fa 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -163,6 +163,7 @@ enum intel_ppgtt_type {
 	func(cursor_needs_physical); \
 	func(has_cdclk_crawl); \
 	func(has_dmc); \
+	func(has_dp_mst); \
 	func(has_dsb); \
 	func(has_dsc); \
 	func(has_fpga_dbg); \
-- 
GitLab


From 9d8d5a39173244a1394cf84a93447be6f82b361d Mon Sep 17 00:00:00 2001
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date: Thu, 19 May 2022 10:07:58 +0100
Subject: [PATCH 0057/1731] Revert "drm/i915: Drop has_ddi from device info"

This reverts commit efd01cd3c27636bc4840057a03839e54abaf11dc.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220519090802.1294691-4-tvrtko.ursulin@linux.intel.com
---
 drivers/gpu/drm/i915/i915_drv.h          | 4 +---
 drivers/gpu/drm/i915/i915_pci.c          | 3 +++
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 680b7ff8c5579..906a76b7d827a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1293,9 +1293,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_DP20(dev_priv)	(IS_DG2(dev_priv))
 
 #define HAS_CDCLK_CRAWL(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
-#define HAS_DDI(dev_priv)		 (DISPLAY_VER(dev_priv) >= 9 || \
-					  IS_BROADWELL(dev_priv) || \
-					  IS_HASWELL(dev_priv))
+#define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
 #define HAS_PSR_HW_TRACKING(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 5870f7daa72e0..e245a8208c647 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -535,6 +535,7 @@ static const struct intel_device_info vlv_info = {
 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
+	.display.has_ddi = 1, \
 	.display.has_fpga_dbg = 1, \
 	.display.has_dp_mst = 1, \
 	.has_rc6p = 0 /* RC6p removed-by HSW */, \
@@ -682,6 +683,7 @@ static const struct intel_device_info skl_gt4_info = {
 		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 		BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
 	.has_64bit_reloc = 1, \
+	.display.has_ddi = 1, \
 	.display.has_fpga_dbg = 1, \
 	.display.fbc_mask = BIT(INTEL_FBC_A), \
 	.display.has_hdcp = 1, \
@@ -930,6 +932,7 @@ static const struct intel_device_info adl_s_info = {
 	.dbuf.size = 4096,							\
 	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |		\
 		BIT(DBUF_S4),							\
+	.display.has_ddi = 1,							\
 	.display.has_dmc = 1,							\
 	.display.has_dp_mst = 1,						\
 	.display.has_dsb = 1,							\
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6194dcc18e4fa..9e2600b861395 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -163,6 +163,7 @@ enum intel_ppgtt_type {
 	func(cursor_needs_physical); \
 	func(has_cdclk_crawl); \
 	func(has_dmc); \
+	func(has_ddi); \
 	func(has_dp_mst); \
 	func(has_dsb); \
 	func(has_dsc); \
-- 
GitLab


From 3d6c72b7fdd2429ca1d4d690618bf65050380b48 Mon Sep 17 00:00:00 2001
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date: Thu, 19 May 2022 10:07:59 +0100
Subject: [PATCH 0058/1731] Revert "drm/i915: Drop has_logical_ring_elsq from
 device info"

This reverts commit b6411373d3954c8fe4617c27f90f773108b0ab03.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220519090802.1294691-5-tvrtko.ursulin@linux.intel.com
---
 drivers/gpu/drm/i915/i915_drv.h          | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c          | 4 +++-
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 906a76b7d827a..95bf99f7f7a56 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1241,7 +1241,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
 		(INTEL_INFO(dev_priv)->has_logical_ring_contexts)
-#define HAS_LOGICAL_RING_ELSQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11)
+#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
+		(INTEL_INFO(dev_priv)->has_logical_ring_elsq)
 
 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e245a8208c647..d5e2df985119b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -809,7 +809,8 @@ static const struct intel_device_info cml_gt2_info = {
 	.dbuf.size = 2048, \
 	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
 	.display.has_dsc = 1, \
-	.has_coherent_ggtt = false
+	.has_coherent_ggtt = false, \
+	.has_logical_ring_elsq = 1
 
 static const struct intel_device_info icl_info = {
 	GEN11_FEATURES,
@@ -996,6 +997,7 @@ static const struct intel_device_info adl_p_info = {
 	.has_global_mocs = 1, \
 	.has_llc = 1, \
 	.has_logical_ring_contexts = 1, \
+	.has_logical_ring_elsq = 1, \
 	.has_mslices = 1, \
 	.has_rps = 1, \
 	.has_runtime_pm = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 9e2600b861395..ffcd88d13bbfe 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -147,6 +147,7 @@ enum intel_ppgtt_type {
 	func(has_l3_dpf); \
 	func(has_llc); \
 	func(has_logical_ring_contexts); \
+	func(has_logical_ring_elsq); \
 	func(has_mslices); \
 	func(has_pooled_eu); \
 	func(has_pxp); \
-- 
GitLab


From b409db082da6b76ad2b759a1a48d9402eee4b942 Mon Sep 17 00:00:00 2001
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date: Thu, 19 May 2022 10:08:00 +0100
Subject: [PATCH 0059/1731] Revert "drm/i915: Drop has_reset_engine from device
 info"

This reverts commit 922abe4d19bd21b38298f3902674774b92a49293.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220519090802.1294691-6-tvrtko.ursulin@linux.intel.com
---
 drivers/gpu/drm/i915/gt/intel_reset.c    | 2 +-
 drivers/gpu/drm/i915/i915_pci.c          | 5 +++++
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 11bf33f1f772a..a5338c3fde7a0 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -699,7 +699,7 @@ bool intel_has_reset_engine(const struct intel_gt *gt)
 	if (gt->i915->params.reset < 2)
 		return false;
 
-	return GRAPHICS_VER(gt->i915) >= 7;
+	return INTEL_INFO(gt->i915)->has_reset_engine;
 }
 
 int intel_reset_guc(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d5e2df985119b..3e514e34bd1d4 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -456,6 +456,7 @@ static const struct intel_device_info snb_m_gt2_info = {
 	.has_coherent_ggtt = true, \
 	.has_llc = 1, \
 	.has_rc6p = 1, \
+	.has_reset_engine = true, \
 	.has_rps = true, \
 	.dma_mask_size = 40, \
 	.ppgtt_type = INTEL_PPGTT_ALIASING, \
@@ -513,6 +514,7 @@ static const struct intel_device_info vlv_info = {
 	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
 	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
 	.has_runtime_pm = 1,
+	.has_reset_engine = true,
 	.has_rps = true,
 	.display.has_gmch = 1,
 	.display.has_hotplug = 1,
@@ -616,6 +618,7 @@ static const struct intel_device_info chv_info = {
 	.dma_mask_size = 39,
 	.ppgtt_type = INTEL_PPGTT_FULL,
 	.ppgtt_size = 32,
+	.has_reset_engine = 1,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
@@ -697,6 +700,7 @@ static const struct intel_device_info skl_gt4_info = {
 	.dma_mask_size = 39, \
 	.ppgtt_type = INTEL_PPGTT_FULL, \
 	.ppgtt_size = 48, \
+	.has_reset_engine = 1, \
 	.has_snoop = true, \
 	.has_coherent_ggtt = false, \
 	.display.has_ipc = 1, \
@@ -999,6 +1003,7 @@ static const struct intel_device_info adl_p_info = {
 	.has_logical_ring_contexts = 1, \
 	.has_logical_ring_elsq = 1, \
 	.has_mslices = 1, \
+	.has_reset_engine = 1, \
 	.has_rps = 1, \
 	.has_runtime_pm = 1, \
 	.ppgtt_size = 48, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index ffcd88d13bbfe..b22004814e887 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -137,6 +137,7 @@ enum intel_ppgtt_type {
 	func(has_64k_pages); \
 	func(needs_compact_pt); \
 	func(gpu_reset_clobbers_display); \
+	func(has_reset_engine); \
 	func(has_4tile); \
 	func(has_flat_ccs); \
 	func(has_global_mocs); \
-- 
GitLab


From fdbec9ff669d83bf863ca7e657af6a9e4c949565 Mon Sep 17 00:00:00 2001
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date: Thu, 19 May 2022 10:08:01 +0100
Subject: [PATCH 0060/1731] Revert "drm/i915: Drop has_rc6 from device info"

This reverts commit 218076abbcd647de46635d21331a34b814f90906.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220519090802.1294691-7-tvrtko.ursulin@linux.intel.com
---
 drivers/gpu/drm/i915/i915_drv.h          | 3 +--
 drivers/gpu/drm/i915/i915_pci.c          | 8 ++++++++
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 95bf99f7f7a56..63451e94fd63f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1302,8 +1302,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_PSR2_SEL_FETCH(dev_priv)	 (DISPLAY_VER(dev_priv) >= 12)
 #define HAS_TRANSCODER(dev_priv, trans)	 ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)
 
-/* ilk does support rc6, but we do not implement [power] contexts */
-#define HAS_RC6(dev_priv)		 (GRAPHICS_VER(dev_priv) >= 6)
+#define HAS_RC6(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6)
 #define HAS_RC6p(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6p)
 #define HAS_RC6pp(dev_priv)		 (false) /* HW was never validated */
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 3e514e34bd1d4..80803ab6e938a 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -376,6 +376,8 @@ static const struct intel_device_info gm45_info = {
 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
 	.has_snoop = true, \
 	.has_coherent_ggtt = true, \
+	/* ilk does support rc6, but we do not implement [power] contexts */ \
+	.has_rc6 = 0, \
 	.dma_mask_size = 36, \
 	I9XX_PIPE_OFFSETS, \
 	I9XX_CURSOR_OFFSETS, \
@@ -405,6 +407,7 @@ static const struct intel_device_info ilk_m_info = {
 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 	.has_coherent_ggtt = true, \
 	.has_llc = 1, \
+	.has_rc6 = 1, \
 	.has_rc6p = 1, \
 	.has_rps = true, \
 	.dma_mask_size = 40, \
@@ -455,6 +458,7 @@ static const struct intel_device_info snb_m_gt2_info = {
 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 	.has_coherent_ggtt = true, \
 	.has_llc = 1, \
+	.has_rc6 = 1, \
 	.has_rc6p = 1, \
 	.has_reset_engine = true, \
 	.has_rps = true, \
@@ -514,6 +518,7 @@ static const struct intel_device_info vlv_info = {
 	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
 	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
 	.has_runtime_pm = 1,
+	.has_rc6 = 1,
 	.has_reset_engine = true,
 	.has_rps = true,
 	.display.has_gmch = 1,
@@ -612,6 +617,7 @@ static const struct intel_device_info chv_info = {
 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
 	.has_64bit_reloc = 1,
 	.has_runtime_pm = 1,
+	.has_rc6 = 1,
 	.has_rps = true,
 	.has_logical_ring_contexts = 1,
 	.display.has_gmch = 1,
@@ -694,6 +700,7 @@ static const struct intel_device_info skl_gt4_info = {
 	.display.has_psr_hw_tracking = 1, \
 	.has_runtime_pm = 1, \
 	.display.has_dmc = 1, \
+	.has_rc6 = 1, \
 	.has_rps = true, \
 	.display.has_dp_mst = 1, \
 	.has_logical_ring_contexts = 1, \
@@ -1003,6 +1010,7 @@ static const struct intel_device_info adl_p_info = {
 	.has_logical_ring_contexts = 1, \
 	.has_logical_ring_elsq = 1, \
 	.has_mslices = 1, \
+	.has_rc6 = 1, \
 	.has_reset_engine = 1, \
 	.has_rps = 1, \
 	.has_runtime_pm = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index b22004814e887..20de6974406a8 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -152,6 +152,7 @@ enum intel_ppgtt_type {
 	func(has_mslices); \
 	func(has_pooled_eu); \
 	func(has_pxp); \
+	func(has_rc6); \
 	func(has_rc6p); \
 	func(has_rps); \
 	func(has_runtime_pm); \
-- 
GitLab


From 39921e5f00f5a98ff9cb3229937ca339e8d9c9c6 Mon Sep 17 00:00:00 2001
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date: Thu, 19 May 2022 10:08:02 +0100
Subject: [PATCH 0061/1731] Revert "drm/i915: Drop has_gt_uc from device info"

This reverts commit 222ff6db8a0dcb86f2bb65fc8656aec635a737a6.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220519090802.1294691-8-tvrtko.ursulin@linux.intel.com
---
 drivers/gpu/drm/i915/i915_drv.h          | 2 +-
 drivers/gpu/drm/i915/i915_gpu_error.c    | 2 +-
 drivers/gpu/drm/i915/i915_pci.c          | 3 +++
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 4 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 63451e94fd63f..72394a11baf91 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1350,7 +1350,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
  */
 #define HAS_FLAT_CCS(dev_priv)   (INTEL_INFO(dev_priv)->has_flat_ccs)
 
-#define HAS_GT_UC(dev_priv)	(GRAPHICS_VER(dev_priv) >= 9)
+#define HAS_GT_UC(dev_priv)	(INTEL_INFO(dev_priv)->has_gt_uc)
 
 #define HAS_POOLED_EU(dev_priv)	(INTEL_INFO(dev_priv)->has_pooled_eu)
 
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 5bd9cb8998527..0512c66fa4f3f 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -2008,7 +2008,7 @@ __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 du
 			return ERR_PTR(-ENOMEM);
 		}
 
-		if (HAS_GT_UC(i915)) {
+		if (INTEL_INFO(i915)->has_gt_uc) {
 			error->gt->uc = gt_record_uc(error->gt, compress);
 			if (error->gt->uc) {
 				if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 80803ab6e938a..664a218030bee 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -644,6 +644,7 @@ static const struct intel_device_info chv_info = {
 	GEN(9), \
 	GEN9_DEFAULT_PAGE_SIZES, \
 	.display.has_dmc = 1, \
+	.has_gt_uc = 1, \
 	.display.has_hdcp = 1, \
 	.display.has_ipc = 1, \
 	.display.has_psr = 1, \
@@ -704,6 +705,7 @@ static const struct intel_device_info skl_gt4_info = {
 	.has_rps = true, \
 	.display.has_dp_mst = 1, \
 	.has_logical_ring_contexts = 1, \
+	.has_gt_uc = 1, \
 	.dma_mask_size = 39, \
 	.ppgtt_type = INTEL_PPGTT_FULL, \
 	.ppgtt_size = 48, \
@@ -1006,6 +1008,7 @@ static const struct intel_device_info adl_p_info = {
 	.has_64bit_reloc = 1, \
 	.has_flat_ccs = 1, \
 	.has_global_mocs = 1, \
+	.has_gt_uc = 1, \
 	.has_llc = 1, \
 	.has_logical_ring_contexts = 1, \
 	.has_logical_ring_elsq = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 20de6974406a8..c4ea5c4abfc67 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -141,6 +141,7 @@ enum intel_ppgtt_type {
 	func(has_4tile); \
 	func(has_flat_ccs); \
 	func(has_global_mocs); \
+	func(has_gt_uc); \
 	func(has_heci_pxp); \
 	func(has_heci_gscfi); \
 	func(has_guc_deprivilege); \
-- 
GitLab


From 85a040bc9049dd168d5e79a1fa9d2da87e6e52dc Mon Sep 17 00:00:00 2001
From: Ashutosh Dixit <ashutosh.dixit@intel.com>
Date: Thu, 19 May 2022 09:57:30 +0100
Subject: [PATCH 0062/1731] drm/i915: Introduce has_media_ratio_mode

Media ratio mode (the ability for media IP to work at a different frequency
from the GT) is available for a subset of dGfx platforms supporting
GuC/SLPC. Introduce 'has_media_ratio_mode' flag in intel_device_info to
identify these platforms and set it for XEHPSDV and DG2/ATS-M.

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220519085732.1276255-1-tvrtko.ursulin@linux.intel.com
[tursulin: fixup merge conflict]
---
 drivers/gpu/drm/i915/i915_drv.h          | 2 ++
 drivers/gpu/drm/i915/i915_pci.c          | 2 ++
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 3 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d5ba3e1af6035..8802ba39087b0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1214,6 +1214,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define CCS_MASK(gt) \
 	ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
 
+#define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode)
+
 /*
  * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
  * All later gens can run the final buffer from the ppgtt
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c88e454a74bba..1e5c40f36798f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1032,6 +1032,7 @@ static const struct intel_device_info xehpsdv_info = {
 	.display = { },
 	.has_64k_pages = 1,
 	.needs_compact_pt = 1,
+	.has_media_ratio_mode = 1,
 	.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) |
 		BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
@@ -1051,6 +1052,7 @@ static const struct intel_device_info xehpsdv_info = {
 	.has_64k_pages = 1, \
 	.has_guc_deprivilege = 1, \
 	.needs_compact_pt = 1, \
+	.has_media_ratio_mode = 1, \
 	.platform_engine_mask = \
 		BIT(RCS0) | BIT(BCS0) | \
 		BIT(VECS0) | BIT(VECS1) | \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 4053efaa55da2..eb3a37808e1dd 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -151,6 +151,7 @@ enum intel_ppgtt_type {
 	func(has_llc); \
 	func(has_logical_ring_contexts); \
 	func(has_logical_ring_elsq); \
+	func(has_media_ratio_mode); \
 	func(has_mslices); \
 	func(has_pooled_eu); \
 	func(has_pxp); \
-- 
GitLab


From ee421bb4cb9535f44015634baad833dcc98c9062 Mon Sep 17 00:00:00 2001
From: Ashutosh Dixit <ashutosh.dixit@intel.com>
Date: Thu, 19 May 2022 09:57:31 +0100
Subject: [PATCH 0063/1731] drm/i915/pcode: Extend pcode functions for multiple
 gt's

Each gt contains an independent instance of pcode. Extend pcode functions
to interface with pcode on different gt's. To avoid creating dependency of
display functionality on intel_gt, pcode function interfaces are exposed in
terms of uncore rather than intel_gt. Callers have been converted to pass
in the appropritate (i915 or intel_gt) uncore to the pcode functions.

v2: Expose pcode functions in terms of uncore rather than gt (Jani/Rodrigo)
v3: Retain previous function names to eliminate needless #defines (Rodrigo)
v4: Move out i915_pcode_init() to a separate patch (Tvrtko)
    Remove duplicated drm_err/drm_dbg from intel_pcode_init() (Tvrtko)

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220519085732.1276255-2-tvrtko.ursulin@linux.intel.com
[tursulin: fixup merge conflict]
---
 drivers/gpu/drm/i915/display/hsw_ips.c        |  4 +-
 drivers/gpu/drm/i915/display/intel_bw.c       |  6 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    | 16 ++---
 .../drm/i915/display/intel_display_power.c    |  2 +-
 .../i915/display/intel_display_power_well.c   |  4 +-
 drivers/gpu/drm/i915/display/intel_hdcp.c     |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c |  4 +-
 drivers/gpu/drm/i915/gt/intel_llc.c           |  3 +-
 drivers/gpu/drm/i915/gt/intel_rc6.c           |  4 +-
 drivers/gpu/drm/i915/gt/intel_rps.c           |  5 +-
 drivers/gpu/drm/i915/gt/selftest_llc.c        |  2 +-
 drivers/gpu/drm/i915/gt/selftest_rps.c        |  2 +-
 drivers/gpu/drm/i915/i915_driver.c            |  4 +-
 drivers/gpu/drm/i915/intel_dram.c             |  2 +-
 drivers/gpu/drm/i915/intel_pcode.c            | 69 ++++++++-----------
 drivers/gpu/drm/i915/intel_pcode.h            | 14 ++--
 drivers/gpu/drm/i915/intel_pm.c               | 10 +--
 17 files changed, 71 insertions(+), 82 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index 38014e0cc9ad5..861dcd2eb890a 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -28,7 +28,7 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
 
 	if (IS_BROADWELL(i915)) {
 		drm_WARN_ON(&i915->drm,
-			    snb_pcode_write(i915, DISPLAY_IPS_CONTROL,
+			    snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL,
 					    IPS_ENABLE | IPS_PCODE_CONTROL));
 		/*
 		 * Quoting Art Runyan: "its not safe to expect any particular
@@ -62,7 +62,7 @@ bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
 
 	if (IS_BROADWELL(i915)) {
 		drm_WARN_ON(&i915->drm,
-			    snb_pcode_write(i915, DISPLAY_IPS_CONTROL, 0));
+			    snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL, 0));
 		/*
 		 * Wait for PCODE to finish disabling IPS. The BSpec specified
 		 * 42ms timeout value leads to occasional timeouts so use 100ms
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 37bd7b17f3d0b..79269d2c476b2 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -78,7 +78,7 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
 	u16 dclk;
 	int ret;
 
-	ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+	ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
 			     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
 			     &val, &val2);
 	if (ret)
@@ -104,7 +104,7 @@ static int adls_pcode_read_psf_gv_point_info(struct drm_i915_private *dev_priv,
 	int ret;
 	int i;
 
-	ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+	ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
 			     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
 	if (ret)
 		return ret;
@@ -123,7 +123,7 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
 	int ret;
 
 	/* bspec says to keep retrying for at least 1 ms */
-	ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+	ret = skl_pcode_request(&dev_priv->uncore, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
 				points_mask,
 				ICL_PCODE_REP_QGV_MASK | ADLS_PCODE_REP_PSF_MASK,
 				ICL_PCODE_REP_QGV_SAFE | ADLS_PCODE_REP_PSF_SAFE,
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index b2017d8161b40..6e80162632ddf 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -800,7 +800,7 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 		     "trying to change cdclk frequency with cdclk not enabled\n"))
 		return;
 
-	ret = snb_pcode_write(dev_priv, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
+	ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
 	if (ret) {
 		drm_err(&dev_priv->drm,
 			"failed to inform pcode about cdclk change\n");
@@ -828,7 +828,7 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 			 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
 		drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
 
-	snb_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
+	snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ,
 			cdclk_config->voltage_level);
 
 	intel_de_write(dev_priv, CDCLK_FREQ,
@@ -1086,7 +1086,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 	drm_WARN_ON_ONCE(&dev_priv->drm,
 			 IS_SKYLAKE(dev_priv) && vco == 8640000);
 
-	ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+	ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
 				SKL_CDCLK_PREPARE_FOR_CHANGE,
 				SKL_CDCLK_READY_FOR_CHANGE,
 				SKL_CDCLK_READY_FOR_CHANGE, 3);
@@ -1132,7 +1132,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 	intel_de_posting_read(dev_priv, CDCLK_CTL);
 
 	/* inform PCU of the change */
-	snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+	snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
 			cdclk_config->voltage_level);
 
 	intel_update_cdclk(dev_priv);
@@ -1702,7 +1702,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 
 	/* Inform power controller of upcoming frequency change. */
 	if (DISPLAY_VER(dev_priv) >= 11)
-		ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+		ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
 					SKL_CDCLK_PREPARE_FOR_CHANGE,
 					SKL_CDCLK_READY_FOR_CHANGE,
 					SKL_CDCLK_READY_FOR_CHANGE, 3);
@@ -1711,7 +1711,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 		 * BSpec requires us to wait up to 150usec, but that leads to
 		 * timeouts; the 2ms used here is based on experiment.
 		 */
-		ret = snb_pcode_write_timeout(dev_priv,
+		ret = snb_pcode_write_timeout(&dev_priv->uncore,
 					      HSW_PCODE_DE_WRITE_FREQ_REQ,
 					      0x80000000, 150, 2);
 	if (ret) {
@@ -1774,7 +1774,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 		intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
 
 	if (DISPLAY_VER(dev_priv) >= 11) {
-		ret = snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+		ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
 				      cdclk_config->voltage_level);
 	} else {
 		/*
@@ -1783,7 +1783,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 		 * FIXME: Waiting for the request completion could be delayed
 		 * until the next PCODE request based on BSpec.
 		 */
-		ret = snb_pcode_write_timeout(dev_priv,
+		ret = snb_pcode_write_timeout(&dev_priv->uncore,
 					      HSW_PCODE_DE_WRITE_FREQ_REQ,
 					      cdclk_config->voltage_level,
 					      150, 2);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 5eb8d63fb89ed..fb17439bd4f8a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1196,7 +1196,7 @@ static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
 {
 	if (IS_HASWELL(dev_priv)) {
-		if (snb_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
+		if (snb_pcode_write(&dev_priv->uncore, GEN6_PCODE_WRITE_D_COMP, val))
 			drm_dbg_kms(&dev_priv->drm,
 				    "Failed to write to D_COMP\n");
 	} else {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 5be18eb94042b..91cfd5890f468 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -474,7 +474,7 @@ static void icl_tc_cold_exit(struct drm_i915_private *i915)
 	int ret, tries = 0;
 
 	while (1) {
-		ret = snb_pcode_write_timeout(i915, ICL_PCODE_EXIT_TCCOLD, 0,
+		ret = snb_pcode_write_timeout(&i915->uncore, ICL_PCODE_EXIT_TCCOLD, 0,
 					      250, 1);
 		if (ret != -EAGAIN || ++tries == 3)
 			break;
@@ -1739,7 +1739,7 @@ tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
 		 * Spec states that we should timeout the request after 200us
 		 * but the function below will timeout after 500us
 		 */
-		ret = snb_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val, &high_val);
+		ret = snb_pcode_read(&i915->uncore, TGL_PCODE_TCCOLD, &low_val, &high_val);
 		if (ret == 0) {
 			if (block &&
 			    (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 4de4c174a987d..ed5dab8427d6e 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -298,7 +298,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
 	 * Mailbox interface.
 	 */
 	if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
-		ret = snb_pcode_write(dev_priv, SKL_PCODE_LOAD_HDCP_KEYS, 1);
+		ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_LOAD_HDCP_KEYS, 1);
 		if (ret) {
 			drm_err(&dev_priv->drm,
 				"Failed to initiate HDCP key load (%d)\n",
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 437e96bb3b931..b3fa6607da7ea 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -138,7 +138,7 @@ static int gen6_drpc(struct seq_file *m)
 	}
 
 	if (GRAPHICS_VER(i915) <= 7)
-		snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
+		snb_pcode_read(gt->uncore, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
 
 	seq_printf(m, "RC1e Enabled: %s\n",
 		   str_yes_no(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
@@ -559,7 +559,7 @@ static int llc_show(struct seq_file *m, void *data)
 	wakeref = intel_runtime_pm_get(gt->uncore->rpm);
 	for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
 		ia_freq = gpu_freq;
-		snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
+		snb_pcode_read(gt->uncore, GEN6_PCODE_READ_MIN_FREQ_TABLE,
 			       &ia_freq, NULL);
 		seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
 			   intel_gpu_freq(rps,
diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c b/drivers/gpu/drm/i915/gt/intel_llc.c
index 40e2e28ee6c75..14fe65812e426 100644
--- a/drivers/gpu/drm/i915/gt/intel_llc.c
+++ b/drivers/gpu/drm/i915/gt/intel_llc.c
@@ -124,7 +124,6 @@ static void calc_ia_freq(struct intel_llc *llc,
 
 static void gen6_update_ring_freq(struct intel_llc *llc)
 {
-	struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
 	struct ia_constants consts;
 	unsigned int gpu_freq;
 
@@ -142,7 +141,7 @@ static void gen6_update_ring_freq(struct intel_llc *llc)
 		unsigned int ia_freq, ring_freq;
 
 		calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
-		snb_pcode_write(i915, GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
+		snb_pcode_write(llc_to_gt(llc)->uncore, GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
 				ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
 				ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
 				gpu_freq);
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 63db136cbc272..cc8bff220abcf 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -271,7 +271,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
 	    GEN6_RC_CTL_HW_ENABLE;
 
 	rc6vids = 0;
-	ret = snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
+	ret = snb_pcode_read(rc6_to_gt(rc6)->uncore, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
 	if (GRAPHICS_VER(i915) == 6 && ret) {
 		drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");
 	} else if (GRAPHICS_VER(i915) == 6 &&
@@ -281,7 +281,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
 			GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
 		rc6vids &= 0xffff00;
 		rc6vids |= GEN6_ENCODE_RC6_VID(450);
-		ret = snb_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
+		ret = snb_pcode_write(rc6_to_gt(rc6)->uncore, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
 		if (ret)
 			drm_err(&i915->drm,
 				"Couldn't fix incorrect rc6 voltage\n");
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index a9c13b1a30181..ce61ceb071144 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1096,7 +1096,8 @@ static void gen6_rps_init(struct intel_rps *rps)
 	    IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) {
 		u32 ddcc_status = 0;
 
-		if (snb_pcode_read(i915, HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
+		if (snb_pcode_read(rps_to_gt(rps)->uncore,
+				   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
 				   &ddcc_status, NULL) == 0)
 			rps->efficient_freq =
 				clamp_t(u8,
@@ -1947,7 +1948,7 @@ void intel_rps_init(struct intel_rps *rps)
 	if (GRAPHICS_VER(i915) == 6 || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
 		u32 params = 0;
 
-		snb_pcode_read(i915, GEN6_READ_OC_PARAMS, &params, NULL);
+		snb_pcode_read(rps_to_gt(rps)->uncore, GEN6_READ_OC_PARAMS, &params, NULL);
 		if (params & BIT(31)) { /* OC supported */
 			drm_dbg(&i915->drm,
 				"Overclocking supported, max: %dMHz, overclock: %dMHz\n",
diff --git a/drivers/gpu/drm/i915/gt/selftest_llc.c b/drivers/gpu/drm/i915/gt/selftest_llc.c
index 2cd184ab32b17..cfd736d889390 100644
--- a/drivers/gpu/drm/i915/gt/selftest_llc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_llc.c
@@ -31,7 +31,7 @@ static int gen6_verify_ring_freq(struct intel_llc *llc)
 		calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
 
 		val = gpu_freq;
-		if (snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
+		if (snb_pcode_read(llc_to_gt(llc)->uncore, GEN6_PCODE_READ_MIN_FREQ_TABLE,
 				   &val, NULL)) {
 			pr_err("Failed to read freq table[%d], range [%d, %d]\n",
 			       gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq);
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 6a69ac0184ad8..cfb4708dd62e6 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -521,7 +521,7 @@ static void show_pcu_config(struct intel_rps *rps)
 	for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
 		int ia_freq = gpu_freq;
 
-		snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
+		snb_pcode_read(rps_to_gt(rps)->uncore, GEN6_PCODE_READ_MIN_FREQ_TABLE,
 			       &ia_freq, NULL);
 
 		pr_info("%5d  %5d  %5d\n",
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 30a7f4381f4b5..419e237f9ea40 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -634,7 +634,7 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 
 	intel_opregion_setup(dev_priv);
 
-	ret = intel_pcode_init(dev_priv);
+	ret = intel_pcode_init(&dev_priv->uncore);
 	if (ret)
 		goto err_msi;
 
@@ -1249,7 +1249,7 @@ static int i915_drm_resume(struct drm_device *dev)
 
 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
-	ret = intel_pcode_init(dev_priv);
+	ret = intel_pcode_init(&dev_priv->uncore);
 	if (ret)
 		return ret;
 
diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
index 2b9e7833da96c..4374471197709 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -393,7 +393,7 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv)
 	u32 val = 0;
 	int ret;
 
-	ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+	ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
 			     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
 	if (ret)
 		return ret;
diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c
index ac727546868ec..2be700932322e 100644
--- a/drivers/gpu/drm/i915/intel_pcode.c
+++ b/drivers/gpu/drm/i915/intel_pcode.c
@@ -52,14 +52,12 @@ static int gen7_check_mailbox_status(u32 mbox)
 	}
 }
 
-static int __snb_pcode_rw(struct drm_i915_private *i915, u32 mbox,
+static int __snb_pcode_rw(struct intel_uncore *uncore, u32 mbox,
 			  u32 *val, u32 *val1,
 			  int fast_timeout_us, int slow_timeout_ms,
 			  bool is_read)
 {
-	struct intel_uncore *uncore = &i915->uncore;
-
-	lockdep_assert_held(&i915->sb_lock);
+	lockdep_assert_held(&uncore->i915->sb_lock);
 
 	/*
 	 * GEN6_PCODE_* are outside of the forcewake domain, we can use
@@ -88,22 +86,22 @@ static int __snb_pcode_rw(struct drm_i915_private *i915, u32 mbox,
 	if (is_read && val1)
 		*val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
 
-	if (GRAPHICS_VER(i915) > 6)
+	if (GRAPHICS_VER(uncore->i915) > 6)
 		return gen7_check_mailbox_status(mbox);
 	else
 		return gen6_check_mailbox_status(mbox);
 }
 
-int snb_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1)
+int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1)
 {
 	int err;
 
-	mutex_lock(&i915->sb_lock);
-	err = __snb_pcode_rw(i915, mbox, val, val1, 500, 20, true);
-	mutex_unlock(&i915->sb_lock);
+	mutex_lock(&uncore->i915->sb_lock);
+	err = __snb_pcode_rw(uncore, mbox, val, val1, 500, 20, true);
+	mutex_unlock(&uncore->i915->sb_lock);
 
 	if (err) {
-		drm_dbg(&i915->drm,
+		drm_dbg(&uncore->i915->drm,
 			"warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
 			mbox, __builtin_return_address(0), err);
 	}
@@ -111,18 +109,18 @@ int snb_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1)
 	return err;
 }
 
-int snb_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
+int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
 			    int fast_timeout_us, int slow_timeout_ms)
 {
 	int err;
 
-	mutex_lock(&i915->sb_lock);
-	err = __snb_pcode_rw(i915, mbox, &val, NULL,
+	mutex_lock(&uncore->i915->sb_lock);
+	err = __snb_pcode_rw(uncore, mbox, &val, NULL,
 			     fast_timeout_us, slow_timeout_ms, false);
-	mutex_unlock(&i915->sb_lock);
+	mutex_unlock(&uncore->i915->sb_lock);
 
 	if (err) {
-		drm_dbg(&i915->drm,
+		drm_dbg(&uncore->i915->drm,
 			"warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
 			val, mbox, __builtin_return_address(0), err);
 	}
@@ -130,18 +128,18 @@ int snb_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
 	return err;
 }
 
-static bool skl_pcode_try_request(struct drm_i915_private *i915, u32 mbox,
+static bool skl_pcode_try_request(struct intel_uncore *uncore, u32 mbox,
 				  u32 request, u32 reply_mask, u32 reply,
 				  u32 *status)
 {
-	*status = __snb_pcode_rw(i915, mbox, &request, NULL, 500, 0, true);
+	*status = __snb_pcode_rw(uncore, mbox, &request, NULL, 500, 0, true);
 
 	return (*status == 0) && ((request & reply_mask) == reply);
 }
 
 /**
  * skl_pcode_request - send PCODE request until acknowledgment
- * @i915: device private
+ * @uncore: uncore
  * @mbox: PCODE mailbox ID the request is targeted for
  * @request: request ID
  * @reply_mask: mask used to check for request acknowledgment
@@ -158,16 +156,16 @@ static bool skl_pcode_try_request(struct drm_i915_private *i915, u32 mbox,
  * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
  * other error as reported by PCODE.
  */
-int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
+int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,
 		      u32 reply_mask, u32 reply, int timeout_base_ms)
 {
 	u32 status;
 	int ret;
 
-	mutex_lock(&i915->sb_lock);
+	mutex_lock(&uncore->i915->sb_lock);
 
 #define COND \
-	skl_pcode_try_request(i915, mbox, request, reply_mask, reply, &status)
+	skl_pcode_try_request(uncore, mbox, request, reply_mask, reply, &status)
 
 	/*
 	 * Prime the PCODE by doing a request first. Normally it guarantees
@@ -193,35 +191,26 @@ int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
 	 * requests, and for any quirks of the PCODE firmware that delays
 	 * the request completion.
 	 */
-	drm_dbg_kms(&i915->drm,
+	drm_dbg_kms(&uncore->i915->drm,
 		    "PCODE timeout, retrying with preemption disabled\n");
-	drm_WARN_ON_ONCE(&i915->drm, timeout_base_ms > 3);
+	drm_WARN_ON_ONCE(&uncore->i915->drm, timeout_base_ms > 3);
 	preempt_disable();
 	ret = wait_for_atomic(COND, 50);
 	preempt_enable();
 
 out:
-	mutex_unlock(&i915->sb_lock);
+	mutex_unlock(&uncore->i915->sb_lock);
 	return status ? status : ret;
 #undef COND
 }
 
-int intel_pcode_init(struct drm_i915_private *i915)
+int intel_pcode_init(struct intel_uncore *uncore)
 {
-	int ret = 0;
-
-	if (!IS_DGFX(i915))
-		return ret;
-
-	ret = skl_pcode_request(i915, DG1_PCODE_STATUS,
-				DG1_UNCORE_GET_INIT_STATUS,
-				DG1_UNCORE_INIT_STATUS_COMPLETE,
-				DG1_UNCORE_INIT_STATUS_COMPLETE, 180000);
-
-	drm_dbg(&i915->drm, "PCODE init status %d\n", ret);
-
-	if (ret)
-		drm_err(&i915->drm, "Pcode did not report uncore initialization completion!\n");
+	if (!IS_DGFX(uncore->i915))
+		return 0;
 
-	return ret;
+	return skl_pcode_request(uncore, DG1_PCODE_STATUS,
+				 DG1_UNCORE_GET_INIT_STATUS,
+				 DG1_UNCORE_INIT_STATUS_COMPLETE,
+				 DG1_UNCORE_INIT_STATUS_COMPLETE, 180000);
 }
diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h
index 0962a17fac48c..8f6241b114a56 100644
--- a/drivers/gpu/drm/i915/intel_pcode.h
+++ b/drivers/gpu/drm/i915/intel_pcode.h
@@ -8,17 +8,17 @@
 
 #include <linux/types.h>
 
-struct drm_i915_private;
+struct intel_uncore;
 
-int snb_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1);
-int snb_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
+int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1);
+int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
 			    int fast_timeout_us, int slow_timeout_ms);
-#define snb_pcode_write(i915, mbox, val)			\
-	snb_pcode_write_timeout(i915, mbox, val, 500, 0)
+#define snb_pcode_write(uncore, mbox, val) \
+	snb_pcode_write_timeout(uncore, mbox, val, 500, 0)
 
-int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
+int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,
 		      u32 reply_mask, u32 reply, int timeout_base_ms);
 
-int intel_pcode_init(struct drm_i915_private *i915);
+int intel_pcode_init(struct intel_uncore *uncore);
 
 #endif /* _INTEL_PCODE_H */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ee0047fdc95d6..aacb21cbc62ec 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2874,7 +2874,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
 
 		/* read the first set of memory latencies[0:3] */
 		val = 0; /* data0 to be programmed to 0 for first set */
-		ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
+		ret = snb_pcode_read(&dev_priv->uncore, GEN9_PCODE_READ_MEM_LATENCY,
 				     &val, NULL);
 
 		if (ret) {
@@ -2893,7 +2893,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
 
 		/* read the second set of memory latencies[4:7] */
 		val = 1; /* data0 to be programmed to 1 for second set */
-		ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
+		ret = snb_pcode_read(&dev_priv->uncore, GEN9_PCODE_READ_MEM_LATENCY,
 				     &val, NULL);
 		if (ret) {
 			drm_err(&dev_priv->drm,
@@ -3679,7 +3679,7 @@ intel_sagv_block_time(struct drm_i915_private *dev_priv)
 		u32 val = 0;
 		int ret;
 
-		ret = snb_pcode_read(dev_priv,
+		ret = snb_pcode_read(&dev_priv->uncore,
 				     GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
 				     &val, NULL);
 		if (ret) {
@@ -3748,7 +3748,7 @@ static void skl_sagv_enable(struct drm_i915_private *dev_priv)
 		return;
 
 	drm_dbg_kms(&dev_priv->drm, "Enabling SAGV\n");
-	ret = snb_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
+	ret = snb_pcode_write(&dev_priv->uncore, GEN9_PCODE_SAGV_CONTROL,
 			      GEN9_SAGV_ENABLE);
 
 	/* We don't need to wait for SAGV when enabling */
@@ -3781,7 +3781,7 @@ static void skl_sagv_disable(struct drm_i915_private *dev_priv)
 
 	drm_dbg_kms(&dev_priv->drm, "Disabling SAGV\n");
 	/* bspec says to keep retrying for at least 1 ms */
-	ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
+	ret = skl_pcode_request(&dev_priv->uncore, GEN9_PCODE_SAGV_CONTROL,
 				GEN9_SAGV_DISABLE,
 				GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
 				1);
-- 
GitLab


From 5f38c3fb55ce3814b4353320d7a205068a420e48 Mon Sep 17 00:00:00 2001
From: Dale B Stimson <dale.b.stimson@intel.com>
Date: Thu, 19 May 2022 09:57:32 +0100
Subject: [PATCH 0064/1731] drm/i915/pcode: Add a couple of pcode helpers

Some dGfx pcode commands take additional sub-commands and parameters. Add a
couple of helpers to help formatting these commands to improve code
readability.

v2: Fixed commit author (Rodrigo)
v3: Function rename and convert to new uncore interface for pcode functions
    Remove unnecessary #define's (Andi)
v4: Another function rename

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220519085732.1276255-3-tvrtko.ursulin@linux.intel.com
---
 drivers/gpu/drm/i915/i915_reg.h    |  3 +++
 drivers/gpu/drm/i915/intel_pcode.c | 32 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_pcode.h |  6 ++++++
 3 files changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9ad5938105375..5d2ab9f66294c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6674,6 +6674,9 @@
 
 #define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
 #define   GEN6_PCODE_READY			(1 << 31)
+#define   GEN6_PCODE_MB_PARAM2			REG_GENMASK(23, 16)
+#define   GEN6_PCODE_MB_PARAM1			REG_GENMASK(15, 8)
+#define   GEN6_PCODE_MB_COMMAND			REG_GENMASK(7, 0)
 #define   GEN6_PCODE_ERROR_MASK			0xFF
 #define     GEN6_PCODE_SUCCESS			0x0
 #define     GEN6_PCODE_ILLEGAL_CMD		0x1
diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c
index 2be700932322e..a234d9b4ed143 100644
--- a/drivers/gpu/drm/i915/intel_pcode.c
+++ b/drivers/gpu/drm/i915/intel_pcode.c
@@ -214,3 +214,35 @@ int intel_pcode_init(struct intel_uncore *uncore)
 				 DG1_UNCORE_INIT_STATUS_COMPLETE,
 				 DG1_UNCORE_INIT_STATUS_COMPLETE, 180000);
 }
+
+int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val)
+{
+	intel_wakeref_t wakeref;
+	u32 mbox;
+	int err;
+
+	mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd)
+		| REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1)
+		| REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2);
+
+	with_intel_runtime_pm(uncore->rpm, wakeref)
+		err = snb_pcode_read(uncore, mbox, val, NULL);
+
+	return err;
+}
+
+int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val)
+{
+	intel_wakeref_t wakeref;
+	u32 mbox;
+	int err;
+
+	mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd)
+		| REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1)
+		| REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2);
+
+	with_intel_runtime_pm(uncore->rpm, wakeref)
+		err = snb_pcode_write(uncore, mbox, val);
+
+	return err;
+}
diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h
index 8f6241b114a56..8d2198e294225 100644
--- a/drivers/gpu/drm/i915/intel_pcode.h
+++ b/drivers/gpu/drm/i915/intel_pcode.h
@@ -21,4 +21,10 @@ int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,
 
 int intel_pcode_init(struct intel_uncore *uncore);
 
+/*
+ * Helpers for dGfx PCODE mailbox command formatting
+ */
+int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val);
+int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val);
+
 #endif /* _INTEL_PCODE_H */
-- 
GitLab


From 4419470191386456e0b8ed4eb06a70b0021798a6 Mon Sep 17 00:00:00 2001
From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date: Thu, 19 May 2022 20:26:07 -0700
Subject: [PATCH 0065/1731] Documentation: Add documentation for Processor MMIO
 Stale Data

Add the admin guide for Processor MMIO stale data vulnerabilities.

Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
---
 Documentation/admin-guide/hw-vuln/index.rst   |   1 +
 .../hw-vuln/processor_mmio_stale_data.rst     | 246 ++++++++++++++++++
 2 files changed, 247 insertions(+)
 create mode 100644 Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst

diff --git a/Documentation/admin-guide/hw-vuln/index.rst b/Documentation/admin-guide/hw-vuln/index.rst
index 8cbc711cda935..4df436e7c4177 100644
--- a/Documentation/admin-guide/hw-vuln/index.rst
+++ b/Documentation/admin-guide/hw-vuln/index.rst
@@ -17,3 +17,4 @@ are configurable at compile, boot or run time.
    special-register-buffer-data-sampling.rst
    core-scheduling.rst
    l1d_flush.rst
+   processor_mmio_stale_data.rst
diff --git a/Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst b/Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst
new file mode 100644
index 0000000000000..9393c50b5afc9
--- /dev/null
+++ b/Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst
@@ -0,0 +1,246 @@
+=========================================
+Processor MMIO Stale Data Vulnerabilities
+=========================================
+
+Processor MMIO Stale Data Vulnerabilities are a class of memory-mapped I/O
+(MMIO) vulnerabilities that can expose data. The sequences of operations for
+exposing data range from simple to very complex. Because most of the
+vulnerabilities require the attacker to have access to MMIO, many environments
+are not affected. System environments using virtualization where MMIO access is
+provided to untrusted guests may need mitigation. These vulnerabilities are
+not transient execution attacks. However, these vulnerabilities may propagate
+stale data into core fill buffers where the data can subsequently be inferred
+by an unmitigated transient execution attack. Mitigation for these
+vulnerabilities includes a combination of microcode update and software
+changes, depending on the platform and usage model. Some of these mitigations
+are similar to those used to mitigate Microarchitectural Data Sampling (MDS) or
+those used to mitigate Special Register Buffer Data Sampling (SRBDS).
+
+Data Propagators
+================
+Propagators are operations that result in stale data being copied or moved from
+one microarchitectural buffer or register to another. Processor MMIO Stale Data
+Vulnerabilities are operations that may result in stale data being directly
+read into an architectural, software-visible state or sampled from a buffer or
+register.
+
+Fill Buffer Stale Data Propagator (FBSDP)
+-----------------------------------------
+Stale data may propagate from fill buffers (FB) into the non-coherent portion
+of the uncore on some non-coherent writes. Fill buffer propagation by itself
+does not make stale data architecturally visible. Stale data must be propagated
+to a location where it is subject to reading or sampling.
+
+Sideband Stale Data Propagator (SSDP)
+-------------------------------------
+The sideband stale data propagator (SSDP) is limited to the client (including
+Intel Xeon server E3) uncore implementation. The sideband response buffer is
+shared by all client cores. For non-coherent reads that go to sideband
+destinations, the uncore logic returns 64 bytes of data to the core, including
+both requested data and unrequested stale data, from a transaction buffer and
+the sideband response buffer. As a result, stale data from the sideband
+response and transaction buffers may now reside in a core fill buffer.
+
+Primary Stale Data Propagator (PSDP)
+------------------------------------
+The primary stale data propagator (PSDP) is limited to the client (including
+Intel Xeon server E3) uncore implementation. Similar to the sideband response
+buffer, the primary response buffer is shared by all client cores. For some
+processors, MMIO primary reads will return 64 bytes of data to the core fill
+buffer including both requested data and unrequested stale data. This is
+similar to the sideband stale data propagator.
+
+Vulnerabilities
+===============
+Device Register Partial Write (DRPW) (CVE-2022-21166)
+-----------------------------------------------------
+Some endpoint MMIO registers incorrectly handle writes that are smaller than
+the register size. Instead of aborting the write or only copying the correct
+subset of bytes (for example, 2 bytes for a 2-byte write), more bytes than
+specified by the write transaction may be written to the register. On
+processors affected by FBSDP, this may expose stale data from the fill buffers
+of the core that created the write transaction.
+
+Shared Buffers Data Sampling (SBDS) (CVE-2022-21125)
+----------------------------------------------------
+After propagators may have moved data around the uncore and copied stale data
+into client core fill buffers, processors affected by MFBDS can leak data from
+the fill buffer. It is limited to the client (including Intel Xeon server E3)
+uncore implementation.
+
+Shared Buffers Data Read (SBDR) (CVE-2022-21123)
+------------------------------------------------
+It is similar to Shared Buffer Data Sampling (SBDS) except that the data is
+directly read into the architectural software-visible state. It is limited to
+the client (including Intel Xeon server E3) uncore implementation.
+
+Affected Processors
+===================
+Not all the CPUs are affected by all the variants. For instance, most
+processors for the server market (excluding Intel Xeon E3 processors) are
+impacted by only Device Register Partial Write (DRPW).
+
+Below is the list of affected Intel processors [#f1]_:
+
+   ===================  ============  =========
+   Common name          Family_Model  Steppings
+   ===================  ============  =========
+   HASWELL_X            06_3FH        2,4
+   SKYLAKE_L            06_4EH        3
+   BROADWELL_X          06_4FH        All
+   SKYLAKE_X            06_55H        3,4,6,7,11
+   BROADWELL_D          06_56H        3,4,5
+   SKYLAKE              06_5EH        3
+   ICELAKE_X            06_6AH        4,5,6
+   ICELAKE_D            06_6CH        1
+   ICELAKE_L            06_7EH        5
+   ATOM_TREMONT_D       06_86H        All
+   LAKEFIELD            06_8AH        1
+   KABYLAKE_L           06_8EH        9 to 12
+   ATOM_TREMONT         06_96H        1
+   ATOM_TREMONT_L       06_9CH        0
+   KABYLAKE             06_9EH        9 to 13
+   COMETLAKE            06_A5H        2,3,5
+   COMETLAKE_L          06_A6H        0,1
+   ROCKETLAKE           06_A7H        1
+   ===================  ============  =========
+
+If a CPU is in the affected processor list, but not affected by a variant, it
+is indicated by new bits in MSR IA32_ARCH_CAPABILITIES. As described in a later
+section, mitigation largely remains the same for all the variants, i.e. to
+clear the CPU fill buffers via VERW instruction.
+
+New bits in MSRs
+================
+Newer processors and microcode update on existing affected processors added new
+bits to IA32_ARCH_CAPABILITIES MSR. These bits can be used to enumerate
+specific variants of Processor MMIO Stale Data vulnerabilities and mitigation
+capability.
+
+MSR IA32_ARCH_CAPABILITIES
+--------------------------
+Bit 13 - SBDR_SSDP_NO - When set, processor is not affected by either the
+	 Shared Buffers Data Read (SBDR) vulnerability or the sideband stale
+	 data propagator (SSDP).
+Bit 14 - FBSDP_NO - When set, processor is not affected by the Fill Buffer
+	 Stale Data Propagator (FBSDP).
+Bit 15 - PSDP_NO - When set, processor is not affected by Primary Stale Data
+	 Propagator (PSDP).
+Bit 17 - FB_CLEAR - When set, VERW instruction will overwrite CPU fill buffer
+	 values as part of MD_CLEAR operations. Processors that do not
+	 enumerate MDS_NO (meaning they are affected by MDS) but that do
+	 enumerate support for both L1D_FLUSH and MD_CLEAR implicitly enumerate
+	 FB_CLEAR as part of their MD_CLEAR support.
+Bit 18 - FB_CLEAR_CTRL - Processor supports read and write to MSR
+	 IA32_MCU_OPT_CTRL[FB_CLEAR_DIS]. On such processors, the FB_CLEAR_DIS
+	 bit can be set to cause the VERW instruction to not perform the
+	 FB_CLEAR action. Not all processors that support FB_CLEAR will support
+	 FB_CLEAR_CTRL.
+
+MSR IA32_MCU_OPT_CTRL
+---------------------
+Bit 3 - FB_CLEAR_DIS - When set, VERW instruction does not perform the FB_CLEAR
+action. This may be useful to reduce the performance impact of FB_CLEAR in
+cases where system software deems it warranted (for example, when performance
+is more critical, or the untrusted software has no MMIO access). Note that
+FB_CLEAR_DIS has no impact on enumeration (for example, it does not change
+FB_CLEAR or MD_CLEAR enumeration) and it may not be supported on all processors
+that enumerate FB_CLEAR.
+
+Mitigation
+==========
+Like MDS, all variants of Processor MMIO Stale Data vulnerabilities  have the
+same mitigation strategy to force the CPU to clear the affected buffers before
+an attacker can extract the secrets.
+
+This is achieved by using the otherwise unused and obsolete VERW instruction in
+combination with a microcode update. The microcode clears the affected CPU
+buffers when the VERW instruction is executed.
+
+Kernel reuses the MDS function to invoke the buffer clearing:
+
+	mds_clear_cpu_buffers()
+
+On MDS affected CPUs, the kernel already invokes CPU buffer clear on
+kernel/userspace, hypervisor/guest and C-state (idle) transitions. No
+additional mitigation is needed on such CPUs.
+
+For CPUs not affected by MDS or TAA, mitigation is needed only for the attacker
+with MMIO capability. Therefore, VERW is not required for kernel/userspace. For
+virtualization case, VERW is only needed at VMENTER for a guest with MMIO
+capability.
+
+Mitigation points
+-----------------
+Return to user space
+^^^^^^^^^^^^^^^^^^^^
+Same mitigation as MDS when affected by MDS/TAA, otherwise no mitigation
+needed.
+
+C-State transition
+^^^^^^^^^^^^^^^^^^
+Control register writes by CPU during C-state transition can propagate data
+from fill buffer to uncore buffers. Execute VERW before C-state transition to
+clear CPU fill buffers.
+
+Guest entry point
+^^^^^^^^^^^^^^^^^
+Same mitigation as MDS when processor is also affected by MDS/TAA, otherwise
+execute VERW at VMENTER only for MMIO capable guests. On CPUs not affected by
+MDS/TAA, guest without MMIO access cannot extract secrets using Processor MMIO
+Stale Data vulnerabilities, so there is no need to execute VERW for such guests.
+
+Mitigation control on the kernel command line
+---------------------------------------------
+The kernel command line allows to control the Processor MMIO Stale Data
+mitigations at boot time with the option "mmio_stale_data=". The valid
+arguments for this option are:
+
+  ==========  =================================================================
+  full        If the CPU is vulnerable, enable mitigation; CPU buffer clearing
+              on exit to userspace and when entering a VM. Idle transitions are
+              protected as well. It does not automatically disable SMT.
+  full,nosmt  Same as full, with SMT disabled on vulnerable CPUs. This is the
+              complete mitigation.
+  off         Disables mitigation completely.
+  ==========  =================================================================
+
+If the CPU is affected and mmio_stale_data=off is not supplied on the kernel
+command line, then the kernel selects the appropriate mitigation.
+
+Mitigation status information
+-----------------------------
+The Linux kernel provides a sysfs interface to enumerate the current
+vulnerability status of the system: whether the system is vulnerable, and
+which mitigations are active. The relevant sysfs file is:
+
+	/sys/devices/system/cpu/vulnerabilities/mmio_stale_data
+
+The possible values in this file are:
+
+  .. list-table::
+
+     * - 'Not affected'
+       - The processor is not vulnerable
+     * - 'Vulnerable'
+       - The processor is vulnerable, but no mitigation enabled
+     * - 'Vulnerable: Clear CPU buffers attempted, no microcode'
+       - The processor is vulnerable, but microcode is not updated. The
+         mitigation is enabled on a best effort basis.
+     * - 'Mitigation: Clear CPU buffers'
+       - The processor is vulnerable and the CPU buffer clearing mitigation is
+         enabled.
+
+If the processor is vulnerable then the following information is appended to
+the above information:
+
+  ========================  ===========================================
+  'SMT vulnerable'          SMT is enabled
+  'SMT disabled'            SMT is disabled
+  'SMT Host state unknown'  Kernel runs in a VM, Host SMT state unknown
+  ========================  ===========================================
+
+References
+----------
+.. [#f1] Affected Processors
+   https://www.intel.com/content/www/us/en/developer/topic-technology/software-security-guidance/processors-affected-consolidated-product-cpu-model.html
-- 
GitLab


From 51802186158c74a0304f51ab963e7c2b3a2b046f Mon Sep 17 00:00:00 2001
From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date: Thu, 19 May 2022 20:27:08 -0700
Subject: [PATCH 0066/1731] x86/speculation/mmio: Enumerate Processor MMIO
 Stale Data bug

Processor MMIO Stale Data is a class of vulnerabilities that may
expose data after an MMIO operation. For more details please refer to
Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst

Add the Processor MMIO Stale Data bug enumeration. A microcode update
adds new bits to the MSR IA32_ARCH_CAPABILITIES, define them.

Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
---
 arch/x86/include/asm/cpufeatures.h       |  1 +
 arch/x86/include/asm/msr-index.h         | 19 +++++++++++
 arch/x86/kernel/cpu/common.c             | 43 ++++++++++++++++++++++--
 tools/arch/x86/include/asm/cpufeatures.h |  1 +
 tools/arch/x86/include/asm/msr-index.h   | 19 +++++++++++
 5 files changed, 81 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 73e643ae94b6f..e17de69faa543 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -443,5 +443,6 @@
 #define X86_BUG_TAA			X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */
 #define X86_BUG_ITLB_MULTIHIT		X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */
 #define X86_BUG_SRBDS			X86_BUG(24) /* CPU may leak RNG bits if not mitigated */
+#define X86_BUG_MMIO_STALE_DATA		X86_BUG(25) /* CPU is affected by Processor MMIO Stale Data vulnerabilities */
 
 #endif /* _ASM_X86_CPUFEATURES_H */
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index ee15311b6be1d..12976405441b7 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -114,6 +114,25 @@
 						 * Not susceptible to
 						 * TSX Async Abort (TAA) vulnerabilities.
 						 */
+#define ARCH_CAP_SBDR_SSDP_NO		BIT(13)	/*
+						 * Not susceptible to SBDR and SSDP
+						 * variants of Processor MMIO stale data
+						 * vulnerabilities.
+						 */
+#define ARCH_CAP_FBSDP_NO		BIT(14)	/*
+						 * Not susceptible to FBSDP variant of
+						 * Processor MMIO stale data
+						 * vulnerabilities.
+						 */
+#define ARCH_CAP_PSDP_NO		BIT(15)	/*
+						 * Not susceptible to PSDP variant of
+						 * Processor MMIO stale data
+						 * vulnerabilities.
+						 */
+#define ARCH_CAP_FB_CLEAR		BIT(17)	/*
+						 * VERW clears CPU fill buffer
+						 * even on MDS_NO CPUs.
+						 */
 
 #define MSR_IA32_FLUSH_CMD		0x0000010b
 #define L1D_FLUSH			BIT(0)	/*
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index e342ae4db3c4d..f7757409e1338 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1237,18 +1237,39 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
 					    X86_FEATURE_ANY, issues)
 
 #define SRBDS		BIT(0)
+/* CPU is affected by X86_BUG_MMIO_STALE_DATA */
+#define MMIO		BIT(1)
 
 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
 	VULNBL_INTEL_STEPPINGS(IVYBRIDGE,	X86_STEPPING_ANY,		SRBDS),
 	VULNBL_INTEL_STEPPINGS(HASWELL,		X86_STEPPING_ANY,		SRBDS),
 	VULNBL_INTEL_STEPPINGS(HASWELL_L,	X86_STEPPING_ANY,		SRBDS),
 	VULNBL_INTEL_STEPPINGS(HASWELL_G,	X86_STEPPING_ANY,		SRBDS),
+	VULNBL_INTEL_STEPPINGS(HASWELL_X,	BIT(2) | BIT(4),		MMIO),
+	VULNBL_INTEL_STEPPINGS(BROADWELL_D,	X86_STEPPINGS(0x3, 0x5),	MMIO),
 	VULNBL_INTEL_STEPPINGS(BROADWELL_G,	X86_STEPPING_ANY,		SRBDS),
+	VULNBL_INTEL_STEPPINGS(BROADWELL_X,	X86_STEPPING_ANY,		MMIO),
 	VULNBL_INTEL_STEPPINGS(BROADWELL,	X86_STEPPING_ANY,		SRBDS),
+	VULNBL_INTEL_STEPPINGS(SKYLAKE_L,	X86_STEPPINGS(0x3, 0x3),	SRBDS | MMIO),
 	VULNBL_INTEL_STEPPINGS(SKYLAKE_L,	X86_STEPPING_ANY,		SRBDS),
+	VULNBL_INTEL_STEPPINGS(SKYLAKE_X,	BIT(3) | BIT(4) | BIT(6) |
+						BIT(7) | BIT(0xB),              MMIO),
+	VULNBL_INTEL_STEPPINGS(SKYLAKE,		X86_STEPPINGS(0x3, 0x3),	SRBDS | MMIO),
 	VULNBL_INTEL_STEPPINGS(SKYLAKE,		X86_STEPPING_ANY,		SRBDS),
-	VULNBL_INTEL_STEPPINGS(KABYLAKE_L,	X86_STEPPINGS(0x0, 0xC),	SRBDS),
-	VULNBL_INTEL_STEPPINGS(KABYLAKE,	X86_STEPPINGS(0x0, 0xD),	SRBDS),
+	VULNBL_INTEL_STEPPINGS(KABYLAKE_L,	X86_STEPPINGS(0x9, 0xC),	SRBDS | MMIO),
+	VULNBL_INTEL_STEPPINGS(KABYLAKE_L,	X86_STEPPINGS(0x0, 0x8),	SRBDS),
+	VULNBL_INTEL_STEPPINGS(KABYLAKE,	X86_STEPPINGS(0x9, 0xD),	SRBDS | MMIO),
+	VULNBL_INTEL_STEPPINGS(KABYLAKE,	X86_STEPPINGS(0x0, 0x8),	SRBDS),
+	VULNBL_INTEL_STEPPINGS(ICELAKE_L,	X86_STEPPINGS(0x5, 0x5),	MMIO),
+	VULNBL_INTEL_STEPPINGS(ICELAKE_D,	X86_STEPPINGS(0x1, 0x1),	MMIO),
+	VULNBL_INTEL_STEPPINGS(ICELAKE_X,	X86_STEPPINGS(0x4, 0x6),	MMIO),
+	VULNBL_INTEL_STEPPINGS(COMETLAKE,	BIT(2) | BIT(3) | BIT(5),	MMIO),
+	VULNBL_INTEL_STEPPINGS(COMETLAKE_L,	X86_STEPPINGS(0x0, 0x1),	MMIO),
+	VULNBL_INTEL_STEPPINGS(LAKEFIELD,	X86_STEPPINGS(0x1, 0x1),	MMIO),
+	VULNBL_INTEL_STEPPINGS(ROCKETLAKE,	X86_STEPPINGS(0x1, 0x1),	MMIO),
+	VULNBL_INTEL_STEPPINGS(ATOM_TREMONT,	X86_STEPPINGS(0x1, 0x1),	MMIO),
+	VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_D,	X86_STEPPING_ANY,		MMIO),
+	VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L,	X86_STEPPINGS(0x0, 0x0),	MMIO),
 	{}
 };
 
@@ -1269,6 +1290,13 @@ u64 x86_read_arch_cap_msr(void)
 	return ia32_cap;
 }
 
+static bool arch_cap_mmio_immune(u64 ia32_cap)
+{
+	return (ia32_cap & ARCH_CAP_FBSDP_NO &&
+		ia32_cap & ARCH_CAP_PSDP_NO &&
+		ia32_cap & ARCH_CAP_SBDR_SSDP_NO);
+}
+
 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
 {
 	u64 ia32_cap = x86_read_arch_cap_msr();
@@ -1328,6 +1356,17 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
 	    cpu_matches(cpu_vuln_blacklist, SRBDS))
 		    setup_force_cpu_bug(X86_BUG_SRBDS);
 
+	/*
+	 * Processor MMIO Stale Data bug enumeration
+	 *
+	 * Affected CPU list is generally enough to enumerate the vulnerability,
+	 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may
+	 * not want the guest to enumerate the bug.
+	 */
+	if (cpu_matches(cpu_vuln_blacklist, MMIO) &&
+	    !arch_cap_mmio_immune(ia32_cap))
+		setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA);
+
 	if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))
 		return;
 
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index 73e643ae94b6f..e17de69faa543 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -443,5 +443,6 @@
 #define X86_BUG_TAA			X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */
 #define X86_BUG_ITLB_MULTIHIT		X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */
 #define X86_BUG_SRBDS			X86_BUG(24) /* CPU may leak RNG bits if not mitigated */
+#define X86_BUG_MMIO_STALE_DATA		X86_BUG(25) /* CPU is affected by Processor MMIO Stale Data vulnerabilities */
 
 #endif /* _ASM_X86_CPUFEATURES_H */
diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
index ee15311b6be1d..12976405441b7 100644
--- a/tools/arch/x86/include/asm/msr-index.h
+++ b/tools/arch/x86/include/asm/msr-index.h
@@ -114,6 +114,25 @@
 						 * Not susceptible to
 						 * TSX Async Abort (TAA) vulnerabilities.
 						 */
+#define ARCH_CAP_SBDR_SSDP_NO		BIT(13)	/*
+						 * Not susceptible to SBDR and SSDP
+						 * variants of Processor MMIO stale data
+						 * vulnerabilities.
+						 */
+#define ARCH_CAP_FBSDP_NO		BIT(14)	/*
+						 * Not susceptible to FBSDP variant of
+						 * Processor MMIO stale data
+						 * vulnerabilities.
+						 */
+#define ARCH_CAP_PSDP_NO		BIT(15)	/*
+						 * Not susceptible to PSDP variant of
+						 * Processor MMIO stale data
+						 * vulnerabilities.
+						 */
+#define ARCH_CAP_FB_CLEAR		BIT(17)	/*
+						 * VERW clears CPU fill buffer
+						 * even on MDS_NO CPUs.
+						 */
 
 #define MSR_IA32_FLUSH_CMD		0x0000010b
 #define L1D_FLUSH			BIT(0)	/*
-- 
GitLab


From f52ea6c26953fed339aa4eae717ee5c2133c7ff2 Mon Sep 17 00:00:00 2001
From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date: Thu, 19 May 2022 20:28:10 -0700
Subject: [PATCH 0067/1731] x86/speculation: Add a common function for MD_CLEAR
 mitigation update

Processor MMIO Stale Data mitigation uses similar mitigation as MDS and
TAA. In preparation for adding its mitigation, add a common function to
update all mitigations that depend on MD_CLEAR.

  [ bp: Add a newline in md_clear_update_mitigation() to separate
    statements better. ]

Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
---
 arch/x86/kernel/cpu/bugs.c | 59 +++++++++++++++++++++-----------------
 1 file changed, 33 insertions(+), 26 deletions(-)

diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 6296e1ebed1db..e05d207e7ec98 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -41,7 +41,7 @@ static void __init spectre_v2_select_mitigation(void);
 static void __init ssb_select_mitigation(void);
 static void __init l1tf_select_mitigation(void);
 static void __init mds_select_mitigation(void);
-static void __init mds_print_mitigation(void);
+static void __init md_clear_update_mitigation(void);
 static void __init taa_select_mitigation(void);
 static void __init srbds_select_mitigation(void);
 static void __init l1d_flush_select_mitigation(void);
@@ -123,10 +123,10 @@ void __init check_bugs(void)
 	l1d_flush_select_mitigation();
 
 	/*
-	 * As MDS and TAA mitigations are inter-related, print MDS
-	 * mitigation until after TAA mitigation selection is done.
+	 * As MDS and TAA mitigations are inter-related, update and print their
+	 * mitigation after TAA mitigation selection is done.
 	 */
-	mds_print_mitigation();
+	md_clear_update_mitigation();
 
 	arch_smt_update();
 
@@ -267,14 +267,6 @@ static void __init mds_select_mitigation(void)
 	}
 }
 
-static void __init mds_print_mitigation(void)
-{
-	if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off())
-		return;
-
-	pr_info("%s\n", mds_strings[mds_mitigation]);
-}
-
 static int __init mds_cmdline(char *str)
 {
 	if (!boot_cpu_has_bug(X86_BUG_MDS))
@@ -329,7 +321,7 @@ static void __init taa_select_mitigation(void)
 	/* TSX previously disabled by tsx=off */
 	if (!boot_cpu_has(X86_FEATURE_RTM)) {
 		taa_mitigation = TAA_MITIGATION_TSX_DISABLED;
-		goto out;
+		return;
 	}
 
 	if (cpu_mitigations_off()) {
@@ -343,7 +335,7 @@ static void __init taa_select_mitigation(void)
 	 */
 	if (taa_mitigation == TAA_MITIGATION_OFF &&
 	    mds_mitigation == MDS_MITIGATION_OFF)
-		goto out;
+		return;
 
 	if (boot_cpu_has(X86_FEATURE_MD_CLEAR))
 		taa_mitigation = TAA_MITIGATION_VERW;
@@ -375,18 +367,6 @@ static void __init taa_select_mitigation(void)
 
 	if (taa_nosmt || cpu_mitigations_auto_nosmt())
 		cpu_smt_disable(false);
-
-	/*
-	 * Update MDS mitigation, if necessary, as the mds_user_clear is
-	 * now enabled for TAA mitigation.
-	 */
-	if (mds_mitigation == MDS_MITIGATION_OFF &&
-	    boot_cpu_has_bug(X86_BUG_MDS)) {
-		mds_mitigation = MDS_MITIGATION_FULL;
-		mds_select_mitigation();
-	}
-out:
-	pr_info("%s\n", taa_strings[taa_mitigation]);
 }
 
 static int __init tsx_async_abort_parse_cmdline(char *str)
@@ -410,6 +390,33 @@ static int __init tsx_async_abort_parse_cmdline(char *str)
 }
 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
 
+#undef pr_fmt
+#define pr_fmt(fmt)     "" fmt
+
+static void __init md_clear_update_mitigation(void)
+{
+	if (cpu_mitigations_off())
+		return;
+
+	if (!static_key_enabled(&mds_user_clear))
+		goto out;
+
+	/*
+	 * mds_user_clear is now enabled. Update MDS mitigation, if
+	 * necessary.
+	 */
+	if (mds_mitigation == MDS_MITIGATION_OFF &&
+	    boot_cpu_has_bug(X86_BUG_MDS)) {
+		mds_mitigation = MDS_MITIGATION_FULL;
+		mds_select_mitigation();
+	}
+out:
+	if (boot_cpu_has_bug(X86_BUG_MDS))
+		pr_info("MDS: %s\n", mds_strings[mds_mitigation]);
+	if (boot_cpu_has_bug(X86_BUG_TAA))
+		pr_info("TAA: %s\n", taa_strings[taa_mitigation]);
+}
+
 #undef pr_fmt
 #define pr_fmt(fmt)	"SRBDS: " fmt
 
-- 
GitLab


From 8cb861e9e3c9a55099ad3d08e1a3b653d29c33ca Mon Sep 17 00:00:00 2001
From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date: Thu, 19 May 2022 20:29:11 -0700
Subject: [PATCH 0068/1731] x86/speculation/mmio: Add mitigation for Processor
 MMIO Stale Data

Processor MMIO Stale Data is a class of vulnerabilities that may
expose data after an MMIO operation. For details please refer to
Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst.

These vulnerabilities are broadly categorized as:

Device Register Partial Write (DRPW):
  Some endpoint MMIO registers incorrectly handle writes that are
  smaller than the register size. Instead of aborting the write or only
  copying the correct subset of bytes (for example, 2 bytes for a 2-byte
  write), more bytes than specified by the write transaction may be
  written to the register. On some processors, this may expose stale
  data from the fill buffers of the core that created the write
  transaction.

Shared Buffers Data Sampling (SBDS):
  After propagators may have moved data around the uncore and copied
  stale data into client core fill buffers, processors affected by MFBDS
  can leak data from the fill buffer.

Shared Buffers Data Read (SBDR):
  It is similar to Shared Buffer Data Sampling (SBDS) except that the
  data is directly read into the architectural software-visible state.

An attacker can use these vulnerabilities to extract data from CPU fill
buffers using MDS and TAA methods. Mitigate it by clearing the CPU fill
buffers using the VERW instruction before returning to a user or a
guest.

On CPUs not affected by MDS and TAA, user application cannot sample data
from CPU fill buffers using MDS or TAA. A guest with MMIO access can
still use DRPW or SBDR to extract data architecturally. Mitigate it with
VERW instruction to clear fill buffers before VMENTER for MMIO capable
guests.

Add a kernel parameter mmio_stale_data={off|full|full,nosmt} to control
the mitigation.

Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
---
 .../admin-guide/kernel-parameters.txt         |  36 ++++++
 arch/x86/include/asm/nospec-branch.h          |   2 +
 arch/x86/kernel/cpu/bugs.c                    | 111 +++++++++++++++++-
 arch/x86/kvm/vmx/vmx.c                        |   3 +
 4 files changed, 148 insertions(+), 4 deletions(-)

diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 3f1cc5e317ed4..c4893782055b4 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -3105,6 +3105,7 @@
 					       kvm.nx_huge_pages=off [X86]
 					       no_entry_flush [PPC]
 					       no_uaccess_flush [PPC]
+					       mmio_stale_data=off [X86]
 
 				Exceptions:
 					       This does not have any effect on
@@ -3126,6 +3127,7 @@
 				Equivalent to: l1tf=flush,nosmt [X86]
 					       mds=full,nosmt [X86]
 					       tsx_async_abort=full,nosmt [X86]
+					       mmio_stale_data=full,nosmt [X86]
 
 	mminit_loglevel=
 			[KNL] When CONFIG_DEBUG_MEMORY_INIT is set, this
@@ -3135,6 +3137,40 @@
 			log everything. Information is printed at KERN_DEBUG
 			so loglevel=8 may also need to be specified.
 
+	mmio_stale_data=
+			[X86,INTEL] Control mitigation for the Processor
+			MMIO Stale Data vulnerabilities.
+
+			Processor MMIO Stale Data is a class of
+			vulnerabilities that may expose data after an MMIO
+			operation. Exposed data could originate or end in
+			the same CPU buffers as affected by MDS and TAA.
+			Therefore, similar to MDS and TAA, the mitigation
+			is to clear the affected CPU buffers.
+
+			This parameter controls the mitigation. The
+			options are:
+
+			full       - Enable mitigation on vulnerable CPUs
+
+			full,nosmt - Enable mitigation and disable SMT on
+				     vulnerable CPUs.
+
+			off        - Unconditionally disable mitigation
+
+			On MDS or TAA affected machines,
+			mmio_stale_data=off can be prevented by an active
+			MDS or TAA mitigation as these vulnerabilities are
+			mitigated with the same mechanism so in order to
+			disable this mitigation, you need to specify
+			mds=off and tsx_async_abort=off too.
+
+			Not specifying this option is equivalent to
+			mmio_stale_data=full.
+
+			For details see:
+			Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst
+
 	module.sig_enforce
 			[KNL] When CONFIG_MODULE_SIG is set, this means that
 			modules without (valid) signatures will fail to load.
diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h
index acbaeaf83b61a..da251a5645b0e 100644
--- a/arch/x86/include/asm/nospec-branch.h
+++ b/arch/x86/include/asm/nospec-branch.h
@@ -269,6 +269,8 @@ DECLARE_STATIC_KEY_FALSE(mds_idle_clear);
 
 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
 
+DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear);
+
 #include <asm/segment.h>
 
 /**
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index e05d207e7ec98..7b01ba9bc701b 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -43,6 +43,7 @@ static void __init l1tf_select_mitigation(void);
 static void __init mds_select_mitigation(void);
 static void __init md_clear_update_mitigation(void);
 static void __init taa_select_mitigation(void);
+static void __init mmio_select_mitigation(void);
 static void __init srbds_select_mitigation(void);
 static void __init l1d_flush_select_mitigation(void);
 
@@ -85,6 +86,10 @@ EXPORT_SYMBOL_GPL(mds_idle_clear);
  */
 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
 
+/* Controls CPU Fill buffer clear before KVM guest MMIO accesses */
+DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear);
+EXPORT_SYMBOL_GPL(mmio_stale_data_clear);
+
 void __init check_bugs(void)
 {
 	identify_boot_cpu();
@@ -119,12 +124,14 @@ void __init check_bugs(void)
 	l1tf_select_mitigation();
 	mds_select_mitigation();
 	taa_select_mitigation();
+	mmio_select_mitigation();
 	srbds_select_mitigation();
 	l1d_flush_select_mitigation();
 
 	/*
-	 * As MDS and TAA mitigations are inter-related, update and print their
-	 * mitigation after TAA mitigation selection is done.
+	 * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update
+	 * and print their mitigation after MDS, TAA and MMIO Stale Data
+	 * mitigation selection is done.
 	 */
 	md_clear_update_mitigation();
 
@@ -390,6 +397,90 @@ static int __init tsx_async_abort_parse_cmdline(char *str)
 }
 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
 
+#undef pr_fmt
+#define pr_fmt(fmt)	"MMIO Stale Data: " fmt
+
+enum mmio_mitigations {
+	MMIO_MITIGATION_OFF,
+	MMIO_MITIGATION_UCODE_NEEDED,
+	MMIO_MITIGATION_VERW,
+};
+
+/* Default mitigation for Processor MMIO Stale Data vulnerabilities */
+static enum mmio_mitigations mmio_mitigation __ro_after_init = MMIO_MITIGATION_VERW;
+static bool mmio_nosmt __ro_after_init = false;
+
+static const char * const mmio_strings[] = {
+	[MMIO_MITIGATION_OFF]		= "Vulnerable",
+	[MMIO_MITIGATION_UCODE_NEEDED]	= "Vulnerable: Clear CPU buffers attempted, no microcode",
+	[MMIO_MITIGATION_VERW]		= "Mitigation: Clear CPU buffers",
+};
+
+static void __init mmio_select_mitigation(void)
+{
+	u64 ia32_cap;
+
+	if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) ||
+	    cpu_mitigations_off()) {
+		mmio_mitigation = MMIO_MITIGATION_OFF;
+		return;
+	}
+
+	if (mmio_mitigation == MMIO_MITIGATION_OFF)
+		return;
+
+	ia32_cap = x86_read_arch_cap_msr();
+
+	/*
+	 * Enable CPU buffer clear mitigation for host and VMM, if also affected
+	 * by MDS or TAA. Otherwise, enable mitigation for VMM only.
+	 */
+	if (boot_cpu_has_bug(X86_BUG_MDS) || (boot_cpu_has_bug(X86_BUG_TAA) &&
+					      boot_cpu_has(X86_FEATURE_RTM)))
+		static_branch_enable(&mds_user_clear);
+	else
+		static_branch_enable(&mmio_stale_data_clear);
+
+	/*
+	 * Check if the system has the right microcode.
+	 *
+	 * CPU Fill buffer clear mitigation is enumerated by either an explicit
+	 * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS
+	 * affected systems.
+	 */
+	if ((ia32_cap & ARCH_CAP_FB_CLEAR) ||
+	    (boot_cpu_has(X86_FEATURE_MD_CLEAR) &&
+	     boot_cpu_has(X86_FEATURE_FLUSH_L1D) &&
+	     !(ia32_cap & ARCH_CAP_MDS_NO)))
+		mmio_mitigation = MMIO_MITIGATION_VERW;
+	else
+		mmio_mitigation = MMIO_MITIGATION_UCODE_NEEDED;
+
+	if (mmio_nosmt || cpu_mitigations_auto_nosmt())
+		cpu_smt_disable(false);
+}
+
+static int __init mmio_stale_data_parse_cmdline(char *str)
+{
+	if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
+		return 0;
+
+	if (!str)
+		return -EINVAL;
+
+	if (!strcmp(str, "off")) {
+		mmio_mitigation = MMIO_MITIGATION_OFF;
+	} else if (!strcmp(str, "full")) {
+		mmio_mitigation = MMIO_MITIGATION_VERW;
+	} else if (!strcmp(str, "full,nosmt")) {
+		mmio_mitigation = MMIO_MITIGATION_VERW;
+		mmio_nosmt = true;
+	}
+
+	return 0;
+}
+early_param("mmio_stale_data", mmio_stale_data_parse_cmdline);
+
 #undef pr_fmt
 #define pr_fmt(fmt)     "" fmt
 
@@ -402,19 +493,31 @@ static void __init md_clear_update_mitigation(void)
 		goto out;
 
 	/*
-	 * mds_user_clear is now enabled. Update MDS mitigation, if
-	 * necessary.
+	 * mds_user_clear is now enabled. Update MDS, TAA and MMIO Stale Data
+	 * mitigation, if necessary.
 	 */
 	if (mds_mitigation == MDS_MITIGATION_OFF &&
 	    boot_cpu_has_bug(X86_BUG_MDS)) {
 		mds_mitigation = MDS_MITIGATION_FULL;
 		mds_select_mitigation();
 	}
+	if (taa_mitigation == TAA_MITIGATION_OFF &&
+	    boot_cpu_has_bug(X86_BUG_TAA)) {
+		taa_mitigation = TAA_MITIGATION_VERW;
+		taa_select_mitigation();
+	}
+	if (mmio_mitigation == MMIO_MITIGATION_OFF &&
+	    boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) {
+		mmio_mitigation = MMIO_MITIGATION_VERW;
+		mmio_select_mitigation();
+	}
 out:
 	if (boot_cpu_has_bug(X86_BUG_MDS))
 		pr_info("MDS: %s\n", mds_strings[mds_mitigation]);
 	if (boot_cpu_has_bug(X86_BUG_TAA))
 		pr_info("TAA: %s\n", taa_strings[taa_mitigation]);
+	if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
+		pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]);
 }
 
 #undef pr_fmt
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 610355b9ccceb..4fa216acadce8 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -6773,6 +6773,9 @@ static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
 		vmx_l1d_flush(vcpu);
 	else if (static_branch_unlikely(&mds_user_clear))
 		mds_clear_cpu_buffers();
+	else if (static_branch_unlikely(&mmio_stale_data_clear) &&
+		 kvm_arch_has_assigned_device(vcpu->kvm))
+		mds_clear_cpu_buffers();
 
 	if (vcpu->arch.cr2 != native_read_cr2())
 		native_write_cr2(vcpu->arch.cr2);
-- 
GitLab


From e5925fb867290ee924fcf2fe3ca887b792714366 Mon Sep 17 00:00:00 2001
From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date: Thu, 19 May 2022 20:30:12 -0700
Subject: [PATCH 0069/1731] x86/bugs: Group MDS, TAA & Processor MMIO Stale
 Data mitigations

MDS, TAA and Processor MMIO Stale Data mitigations rely on clearing CPU
buffers. Moreover, status of these mitigations affects each other.
During boot, it is important to maintain the order in which these
mitigations are selected. This is especially true for
md_clear_update_mitigation() that needs to be called after MDS, TAA and
Processor MMIO Stale Data mitigation selection is done.

Introduce md_clear_select_mitigation(), and select all these mitigations
from there. This reflects relationships between these mitigations and
ensures proper ordering.

Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
---
 arch/x86/kernel/cpu/bugs.c | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 7b01ba9bc701b..d2cc7dbba5e29 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -42,6 +42,7 @@ static void __init ssb_select_mitigation(void);
 static void __init l1tf_select_mitigation(void);
 static void __init mds_select_mitigation(void);
 static void __init md_clear_update_mitigation(void);
+static void __init md_clear_select_mitigation(void);
 static void __init taa_select_mitigation(void);
 static void __init mmio_select_mitigation(void);
 static void __init srbds_select_mitigation(void);
@@ -122,19 +123,10 @@ void __init check_bugs(void)
 	spectre_v2_select_mitigation();
 	ssb_select_mitigation();
 	l1tf_select_mitigation();
-	mds_select_mitigation();
-	taa_select_mitigation();
-	mmio_select_mitigation();
+	md_clear_select_mitigation();
 	srbds_select_mitigation();
 	l1d_flush_select_mitigation();
 
-	/*
-	 * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update
-	 * and print their mitigation after MDS, TAA and MMIO Stale Data
-	 * mitigation selection is done.
-	 */
-	md_clear_update_mitigation();
-
 	arch_smt_update();
 
 #ifdef CONFIG_X86_32
@@ -520,6 +512,20 @@ out:
 		pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]);
 }
 
+static void __init md_clear_select_mitigation(void)
+{
+	mds_select_mitigation();
+	taa_select_mitigation();
+	mmio_select_mitigation();
+
+	/*
+	 * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update
+	 * and print their mitigation after MDS, TAA and MMIO Stale Data
+	 * mitigation selection is done.
+	 */
+	md_clear_update_mitigation();
+}
+
 #undef pr_fmt
 #define pr_fmt(fmt)	"SRBDS: " fmt
 
-- 
GitLab


From 99a83db5a605137424e1efe29dc0573d6a5b6316 Mon Sep 17 00:00:00 2001
From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date: Thu, 19 May 2022 20:31:12 -0700
Subject: [PATCH 0070/1731] x86/speculation/mmio: Enable CPU Fill buffer
 clearing on idle

When the CPU is affected by Processor MMIO Stale Data vulnerabilities,
Fill Buffer Stale Data Propagator (FBSDP) can propagate stale data out
of Fill buffer to uncore buffer when CPU goes idle. Stale data can then
be exploited with other variants using MMIO operations.

Mitigate it by clearing the Fill buffer before entering idle state.

Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Co-developed-by: Josh Poimboeuf <jpoimboe@redhat.com>
Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
---
 arch/x86/kernel/cpu/bugs.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index d2cc7dbba5e29..56d5dea5e1283 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -433,6 +433,14 @@ static void __init mmio_select_mitigation(void)
 	else
 		static_branch_enable(&mmio_stale_data_clear);
 
+	/*
+	 * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can
+	 * be propagated to uncore buffers, clearing the Fill buffers on idle
+	 * is required irrespective of SMT state.
+	 */
+	if (!(ia32_cap & ARCH_CAP_FBSDP_NO))
+		static_branch_enable(&mds_idle_clear);
+
 	/*
 	 * Check if the system has the right microcode.
 	 *
@@ -1225,6 +1233,8 @@ static void update_indir_branch_cond(void)
 /* Update the static key controlling the MDS CPU buffer clear in idle */
 static void update_mds_branch_idle(void)
 {
+	u64 ia32_cap = x86_read_arch_cap_msr();
+
 	/*
 	 * Enable the idle clearing if SMT is active on CPUs which are
 	 * affected only by MSBDS and not any other MDS variant.
@@ -1236,10 +1246,12 @@ static void update_mds_branch_idle(void)
 	if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
 		return;
 
-	if (sched_smt_active())
+	if (sched_smt_active()) {
 		static_branch_enable(&mds_idle_clear);
-	else
+	} else if (mmio_mitigation == MMIO_MITIGATION_OFF ||
+		   (ia32_cap & ARCH_CAP_FBSDP_NO)) {
 		static_branch_disable(&mds_idle_clear);
+	}
 }
 
 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
-- 
GitLab


From 8d50cdf8b8341770bc6367bce40c0c1bb0e1d5b3 Mon Sep 17 00:00:00 2001
From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date: Thu, 19 May 2022 20:32:13 -0700
Subject: [PATCH 0071/1731] x86/speculation/mmio: Add sysfs reporting for
 Processor MMIO Stale Data

Add the sysfs reporting file for Processor MMIO Stale Data
vulnerability. It exposes the vulnerability and mitigation state similar
to the existing files for the other hardware vulnerabilities.

Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
---
 .../ABI/testing/sysfs-devices-system-cpu      |  1 +
 arch/x86/kernel/cpu/bugs.c                    | 22 +++++++++++++++++++
 drivers/base/cpu.c                            |  8 +++++++
 include/linux/cpu.h                           |  3 +++
 4 files changed, 34 insertions(+)

diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu
index 2ad01cad7f1c8..bcc974d276dc4 100644
--- a/Documentation/ABI/testing/sysfs-devices-system-cpu
+++ b/Documentation/ABI/testing/sysfs-devices-system-cpu
@@ -526,6 +526,7 @@ What:		/sys/devices/system/cpu/vulnerabilities
 		/sys/devices/system/cpu/vulnerabilities/srbds
 		/sys/devices/system/cpu/vulnerabilities/tsx_async_abort
 		/sys/devices/system/cpu/vulnerabilities/itlb_multihit
+		/sys/devices/system/cpu/vulnerabilities/mmio_stale_data
 Date:		January 2018
 Contact:	Linux kernel mailing list <linux-kernel@vger.kernel.org>
 Description:	Information about CPU vulnerabilities
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 56d5dea5e1283..38853077ca587 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -1902,6 +1902,20 @@ static ssize_t tsx_async_abort_show_state(char *buf)
 		       sched_smt_active() ? "vulnerable" : "disabled");
 }
 
+static ssize_t mmio_stale_data_show_state(char *buf)
+{
+	if (mmio_mitigation == MMIO_MITIGATION_OFF)
+		return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]);
+
+	if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
+		return sysfs_emit(buf, "%s; SMT Host state unknown\n",
+				  mmio_strings[mmio_mitigation]);
+	}
+
+	return sysfs_emit(buf, "%s; SMT %s\n", mmio_strings[mmio_mitigation],
+			  sched_smt_active() ? "vulnerable" : "disabled");
+}
+
 static char *stibp_state(void)
 {
 	if (spectre_v2_in_eibrs_mode(spectre_v2_enabled))
@@ -2002,6 +2016,9 @@ static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr
 	case X86_BUG_SRBDS:
 		return srbds_show_state(buf);
 
+	case X86_BUG_MMIO_STALE_DATA:
+		return mmio_stale_data_show_state(buf);
+
 	default:
 		break;
 	}
@@ -2053,4 +2070,9 @@ ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *
 {
 	return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
 }
+
+ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA);
+}
 #endif
diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c
index 2ef23fce0860c..a97776ea9d990 100644
--- a/drivers/base/cpu.c
+++ b/drivers/base/cpu.c
@@ -564,6 +564,12 @@ ssize_t __weak cpu_show_srbds(struct device *dev,
 	return sysfs_emit(buf, "Not affected\n");
 }
 
+ssize_t __weak cpu_show_mmio_stale_data(struct device *dev,
+					struct device_attribute *attr, char *buf)
+{
+	return sysfs_emit(buf, "Not affected\n");
+}
+
 static DEVICE_ATTR(meltdown, 0444, cpu_show_meltdown, NULL);
 static DEVICE_ATTR(spectre_v1, 0444, cpu_show_spectre_v1, NULL);
 static DEVICE_ATTR(spectre_v2, 0444, cpu_show_spectre_v2, NULL);
@@ -573,6 +579,7 @@ static DEVICE_ATTR(mds, 0444, cpu_show_mds, NULL);
 static DEVICE_ATTR(tsx_async_abort, 0444, cpu_show_tsx_async_abort, NULL);
 static DEVICE_ATTR(itlb_multihit, 0444, cpu_show_itlb_multihit, NULL);
 static DEVICE_ATTR(srbds, 0444, cpu_show_srbds, NULL);
+static DEVICE_ATTR(mmio_stale_data, 0444, cpu_show_mmio_stale_data, NULL);
 
 static struct attribute *cpu_root_vulnerabilities_attrs[] = {
 	&dev_attr_meltdown.attr,
@@ -584,6 +591,7 @@ static struct attribute *cpu_root_vulnerabilities_attrs[] = {
 	&dev_attr_tsx_async_abort.attr,
 	&dev_attr_itlb_multihit.attr,
 	&dev_attr_srbds.attr,
+	&dev_attr_mmio_stale_data.attr,
 	NULL
 };
 
diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index 54dc2f9a2d56e..2c74773547444 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -65,6 +65,9 @@ extern ssize_t cpu_show_tsx_async_abort(struct device *dev,
 extern ssize_t cpu_show_itlb_multihit(struct device *dev,
 				      struct device_attribute *attr, char *buf);
 extern ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf);
+extern ssize_t cpu_show_mmio_stale_data(struct device *dev,
+					struct device_attribute *attr,
+					char *buf);
 
 extern __printf(4, 5)
 struct device *cpu_device_create(struct device *parent, void *drvdata,
-- 
GitLab


From 22cac9c677c95f3ac5c9244f8ca0afdc7c8afb19 Mon Sep 17 00:00:00 2001
From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date: Thu, 19 May 2022 20:33:13 -0700
Subject: [PATCH 0072/1731] x86/speculation/srbds: Update SRBDS mitigation
 selection

Currently, Linux disables SRBDS mitigation on CPUs not affected by
MDS and have the TSX feature disabled. On such CPUs, secrets cannot
be extracted from CPU fill buffers using MDS or TAA. Without SRBDS
mitigation, Processor MMIO Stale Data vulnerabilities can be used to
extract RDRAND, RDSEED, and EGETKEY data.

Do not disable SRBDS mitigation by default when CPU is also affected by
Processor MMIO Stale Data vulnerabilities.

Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
---
 arch/x86/kernel/cpu/bugs.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 38853077ca587..ef4749097f42d 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -595,11 +595,13 @@ static void __init srbds_select_mitigation(void)
 		return;
 
 	/*
-	 * Check to see if this is one of the MDS_NO systems supporting
-	 * TSX that are only exposed to SRBDS when TSX is enabled.
+	 * Check to see if this is one of the MDS_NO systems supporting TSX that
+	 * are only exposed to SRBDS when TSX is enabled or when CPU is affected
+	 * by Processor MMIO Stale Data vulnerability.
 	 */
 	ia32_cap = x86_read_arch_cap_msr();
-	if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM))
+	if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) &&
+	    !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
 		srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
 	else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
 		srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
-- 
GitLab


From a992b8a4682f119ae035a01b40d4d0665c4a2875 Mon Sep 17 00:00:00 2001
From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date: Thu, 19 May 2022 20:34:14 -0700
Subject: [PATCH 0073/1731] x86/speculation/mmio: Reuse SRBDS mitigation for
 SBDS

The Shared Buffers Data Sampling (SBDS) variant of Processor MMIO Stale
Data vulnerabilities may expose RDRAND, RDSEED and SGX EGETKEY data.
Mitigation for this is added by a microcode update.

As some of the implications of SBDS are similar to SRBDS, SRBDS mitigation
infrastructure can be leveraged by SBDS. Set X86_BUG_SRBDS and use SRBDS
mitigation.

Mitigation is enabled by default; use srbds=off to opt-out. Mitigation
status can be checked from below file:

  /sys/devices/system/cpu/vulnerabilities/srbds

Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
---
 arch/x86/kernel/cpu/common.c | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index f7757409e1338..af5d0c188f7b8 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1239,6 +1239,8 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
 #define SRBDS		BIT(0)
 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */
 #define MMIO		BIT(1)
+/* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */
+#define MMIO_SBDS	BIT(2)
 
 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
 	VULNBL_INTEL_STEPPINGS(IVYBRIDGE,	X86_STEPPING_ANY,		SRBDS),
@@ -1260,16 +1262,17 @@ static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
 	VULNBL_INTEL_STEPPINGS(KABYLAKE_L,	X86_STEPPINGS(0x0, 0x8),	SRBDS),
 	VULNBL_INTEL_STEPPINGS(KABYLAKE,	X86_STEPPINGS(0x9, 0xD),	SRBDS | MMIO),
 	VULNBL_INTEL_STEPPINGS(KABYLAKE,	X86_STEPPINGS(0x0, 0x8),	SRBDS),
-	VULNBL_INTEL_STEPPINGS(ICELAKE_L,	X86_STEPPINGS(0x5, 0x5),	MMIO),
+	VULNBL_INTEL_STEPPINGS(ICELAKE_L,	X86_STEPPINGS(0x5, 0x5),	MMIO | MMIO_SBDS),
 	VULNBL_INTEL_STEPPINGS(ICELAKE_D,	X86_STEPPINGS(0x1, 0x1),	MMIO),
 	VULNBL_INTEL_STEPPINGS(ICELAKE_X,	X86_STEPPINGS(0x4, 0x6),	MMIO),
-	VULNBL_INTEL_STEPPINGS(COMETLAKE,	BIT(2) | BIT(3) | BIT(5),	MMIO),
-	VULNBL_INTEL_STEPPINGS(COMETLAKE_L,	X86_STEPPINGS(0x0, 0x1),	MMIO),
-	VULNBL_INTEL_STEPPINGS(LAKEFIELD,	X86_STEPPINGS(0x1, 0x1),	MMIO),
+	VULNBL_INTEL_STEPPINGS(COMETLAKE,	BIT(2) | BIT(3) | BIT(5),	MMIO | MMIO_SBDS),
+	VULNBL_INTEL_STEPPINGS(COMETLAKE_L,	X86_STEPPINGS(0x1, 0x1),	MMIO | MMIO_SBDS),
+	VULNBL_INTEL_STEPPINGS(COMETLAKE_L,	X86_STEPPINGS(0x0, 0x0),	MMIO),
+	VULNBL_INTEL_STEPPINGS(LAKEFIELD,	X86_STEPPINGS(0x1, 0x1),	MMIO | MMIO_SBDS),
 	VULNBL_INTEL_STEPPINGS(ROCKETLAKE,	X86_STEPPINGS(0x1, 0x1),	MMIO),
-	VULNBL_INTEL_STEPPINGS(ATOM_TREMONT,	X86_STEPPINGS(0x1, 0x1),	MMIO),
+	VULNBL_INTEL_STEPPINGS(ATOM_TREMONT,	X86_STEPPINGS(0x1, 0x1),	MMIO | MMIO_SBDS),
 	VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_D,	X86_STEPPING_ANY,		MMIO),
-	VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L,	X86_STEPPINGS(0x0, 0x0),	MMIO),
+	VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L,	X86_STEPPINGS(0x0, 0x0),	MMIO | MMIO_SBDS),
 	{}
 };
 
@@ -1350,10 +1353,14 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
 	/*
 	 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
 	 * in the vulnerability blacklist.
+	 *
+	 * Some of the implications and mitigation of Shared Buffers Data
+	 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as
+	 * SRBDS.
 	 */
 	if ((cpu_has(c, X86_FEATURE_RDRAND) ||
 	     cpu_has(c, X86_FEATURE_RDSEED)) &&
-	    cpu_matches(cpu_vuln_blacklist, SRBDS))
+	    cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS))
 		    setup_force_cpu_bug(X86_BUG_SRBDS);
 
 	/*
-- 
GitLab


From 027bbb884be006b05d9c577d6401686053aa789e Mon Sep 17 00:00:00 2001
From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date: Thu, 19 May 2022 20:35:15 -0700
Subject: [PATCH 0074/1731] KVM: x86/speculation: Disable Fill buffer clear
 within guests

The enumeration of MD_CLEAR in CPUID(EAX=7,ECX=0).EDX{bit 10} is not an
accurate indicator on all CPUs of whether the VERW instruction will
overwrite fill buffers. FB_CLEAR enumeration in
IA32_ARCH_CAPABILITIES{bit 17} covers the case of CPUs that are not
vulnerable to MDS/TAA, indicating that microcode does overwrite fill
buffers.

Guests running in VMM environments may not be aware of all the
capabilities/vulnerabilities of the host CPU. Specifically, a guest may
apply MDS/TAA mitigations when a virtual CPU is enumerated as vulnerable
to MDS/TAA even when the physical CPU is not. On CPUs that enumerate
FB_CLEAR_CTRL the VMM may set FB_CLEAR_DIS to skip overwriting of fill
buffers by the VERW instruction. This is done by setting FB_CLEAR_DIS
during VMENTER and resetting on VMEXIT. For guests that enumerate
FB_CLEAR (explicitly asking for fill buffer clear capability) the VMM
will not use FB_CLEAR_DIS.

Irrespective of guest state, host overwrites CPU buffers before VMENTER
to protect itself from an MMIO capable guest, as part of mitigation for
MMIO Stale Data vulnerabilities.

Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
---
 arch/x86/include/asm/msr-index.h       |  6 +++
 arch/x86/kvm/vmx/vmx.c                 | 69 ++++++++++++++++++++++++++
 arch/x86/kvm/vmx/vmx.h                 |  2 +
 arch/x86/kvm/x86.c                     |  3 ++
 tools/arch/x86/include/asm/msr-index.h |  6 +++
 5 files changed, 86 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 12976405441b7..4425d6773183b 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -133,6 +133,11 @@
 						 * VERW clears CPU fill buffer
 						 * even on MDS_NO CPUs.
 						 */
+#define ARCH_CAP_FB_CLEAR_CTRL		BIT(18)	/*
+						 * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS]
+						 * bit available to control VERW
+						 * behavior.
+						 */
 
 #define MSR_IA32_FLUSH_CMD		0x0000010b
 #define L1D_FLUSH			BIT(0)	/*
@@ -150,6 +155,7 @@
 #define MSR_IA32_MCU_OPT_CTRL		0x00000123
 #define RNGDS_MITG_DIS			BIT(0)	/* SRBDS support */
 #define RTM_ALLOW			BIT(1)	/* TSX development mode */
+#define FB_CLEAR_DIS			BIT(3)	/* CPU Fill buffer clear disable */
 
 #define MSR_IA32_SYSENTER_CS		0x00000174
 #define MSR_IA32_SYSENTER_ESP		0x00000175
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 4fa216acadce8..6e8fb36bc49a6 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -229,6 +229,9 @@ static const struct {
 #define L1D_CACHE_ORDER 4
 static void *vmx_l1d_flush_pages;
 
+/* Control for disabling CPU Fill buffer clear */
+static bool __read_mostly vmx_fb_clear_ctrl_available;
+
 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 {
 	struct page *page;
@@ -360,6 +363,60 @@ static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 	return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 }
 
+static void vmx_setup_fb_clear_ctrl(void)
+{
+	u64 msr;
+
+	if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES) &&
+	    !boot_cpu_has_bug(X86_BUG_MDS) &&
+	    !boot_cpu_has_bug(X86_BUG_TAA)) {
+		rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
+		if (msr & ARCH_CAP_FB_CLEAR_CTRL)
+			vmx_fb_clear_ctrl_available = true;
+	}
+}
+
+static __always_inline void vmx_disable_fb_clear(struct vcpu_vmx *vmx)
+{
+	u64 msr;
+
+	if (!vmx->disable_fb_clear)
+		return;
+
+	rdmsrl(MSR_IA32_MCU_OPT_CTRL, msr);
+	msr |= FB_CLEAR_DIS;
+	wrmsrl(MSR_IA32_MCU_OPT_CTRL, msr);
+	/* Cache the MSR value to avoid reading it later */
+	vmx->msr_ia32_mcu_opt_ctrl = msr;
+}
+
+static __always_inline void vmx_enable_fb_clear(struct vcpu_vmx *vmx)
+{
+	if (!vmx->disable_fb_clear)
+		return;
+
+	vmx->msr_ia32_mcu_opt_ctrl &= ~FB_CLEAR_DIS;
+	wrmsrl(MSR_IA32_MCU_OPT_CTRL, vmx->msr_ia32_mcu_opt_ctrl);
+}
+
+static void vmx_update_fb_clear_dis(struct kvm_vcpu *vcpu, struct vcpu_vmx *vmx)
+{
+	vmx->disable_fb_clear = vmx_fb_clear_ctrl_available;
+
+	/*
+	 * If guest will not execute VERW, there is no need to set FB_CLEAR_DIS
+	 * at VMEntry. Skip the MSR read/write when a guest has no use case to
+	 * execute VERW.
+	 */
+	if ((vcpu->arch.arch_capabilities & ARCH_CAP_FB_CLEAR) ||
+	   ((vcpu->arch.arch_capabilities & ARCH_CAP_MDS_NO) &&
+	    (vcpu->arch.arch_capabilities & ARCH_CAP_TAA_NO) &&
+	    (vcpu->arch.arch_capabilities & ARCH_CAP_PSDP_NO) &&
+	    (vcpu->arch.arch_capabilities & ARCH_CAP_FBSDP_NO) &&
+	    (vcpu->arch.arch_capabilities & ARCH_CAP_SBDR_SSDP_NO)))
+		vmx->disable_fb_clear = false;
+}
+
 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 	.set = vmentry_l1d_flush_set,
 	.get = vmentry_l1d_flush_get,
@@ -2252,6 +2309,10 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 			ret = kvm_set_msr_common(vcpu, msr_info);
 	}
 
+	/* FB_CLEAR may have changed, also update the FB_CLEAR_DIS behavior */
+	if (msr_index == MSR_IA32_ARCH_CAPABILITIES)
+		vmx_update_fb_clear_dis(vcpu, vmx);
+
 	return ret;
 }
 
@@ -4553,6 +4614,8 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
 	kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
 
 	vpid_sync_context(vmx->vpid);
+
+	vmx_update_fb_clear_dis(vcpu, vmx);
 }
 
 static void vmx_enable_irq_window(struct kvm_vcpu *vcpu)
@@ -6777,6 +6840,8 @@ static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
 		 kvm_arch_has_assigned_device(vcpu->kvm))
 		mds_clear_cpu_buffers();
 
+	vmx_disable_fb_clear(vmx);
+
 	if (vcpu->arch.cr2 != native_read_cr2())
 		native_write_cr2(vcpu->arch.cr2);
 
@@ -6785,6 +6850,8 @@ static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
 
 	vcpu->arch.cr2 = native_read_cr2();
 
+	vmx_enable_fb_clear(vmx);
+
 	guest_state_exit_irqoff();
 }
 
@@ -8185,6 +8252,8 @@ static int __init vmx_init(void)
 		return r;
 	}
 
+	vmx_setup_fb_clear_ctrl();
+
 	for_each_possible_cpu(cpu) {
 		INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
 
diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h
index b98c7e96697a9..8d2342ede0c59 100644
--- a/arch/x86/kvm/vmx/vmx.h
+++ b/arch/x86/kvm/vmx/vmx.h
@@ -348,6 +348,8 @@ struct vcpu_vmx {
 	u64 msr_ia32_feature_control_valid_bits;
 	/* SGX Launch Control public key hash */
 	u64 msr_ia32_sgxlepubkeyhash[4];
+	u64 msr_ia32_mcu_opt_ctrl;
+	bool disable_fb_clear;
 
 	struct pt_desc pt_desc;
 	struct lbr_desc lbr_desc;
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 4790f0d7d40b8..44b72caf2e0bf 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1587,6 +1587,9 @@ static u64 kvm_get_arch_capabilities(void)
 		 */
 	}
 
+	/* Guests don't need to know "Fill buffer clear control" exists */
+	data &= ~ARCH_CAP_FB_CLEAR_CTRL;
+
 	return data;
 }
 
diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
index 12976405441b7..4425d6773183b 100644
--- a/tools/arch/x86/include/asm/msr-index.h
+++ b/tools/arch/x86/include/asm/msr-index.h
@@ -133,6 +133,11 @@
 						 * VERW clears CPU fill buffer
 						 * even on MDS_NO CPUs.
 						 */
+#define ARCH_CAP_FB_CLEAR_CTRL		BIT(18)	/*
+						 * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS]
+						 * bit available to control VERW
+						 * behavior.
+						 */
 
 #define MSR_IA32_FLUSH_CMD		0x0000010b
 #define L1D_FLUSH			BIT(0)	/*
@@ -150,6 +155,7 @@
 #define MSR_IA32_MCU_OPT_CTRL		0x00000123
 #define RNGDS_MITG_DIS			BIT(0)	/* SRBDS support */
 #define RTM_ALLOW			BIT(1)	/* TSX development mode */
+#define FB_CLEAR_DIS			BIT(3)	/* CPU Fill buffer clear disable */
 
 #define MSR_IA32_SYSENTER_CS		0x00000174
 #define MSR_IA32_SYSENTER_ESP		0x00000175
-- 
GitLab


From 08c59dde71b73a0ac94e3ed2d431345b01f20485 Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Fri, 20 May 2022 12:46:00 +0300
Subject: [PATCH 0075/1731] drm/i915/dsi: fix VBT send packet port selection
 for ICL+
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The VBT send packet port selection was never updated for ICL+ where the
2nd link is on port B instead of port C as in VLV+ DSI.

First, single link DSI needs to use the configured port instead of
relying on the VBT sequence block port. Remove the hard-coded port C
check here and make it generic. For reference, see commit f915084edc5a
("drm/i915: Changes related to the sequence port no for") for the
original VLV specific fix.

Second, the sequence block port number is either 0 or 1, where 1
indicates the 2nd link. Remove the hard-coded port C here for 2nd
link. (This could be a "find second set bit" on DSI ports, but just
check the two possible options.)

Third, sanity check the result with a warning to avoid a NULL pointer
dereference.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5984
Cc: stable@vger.kernel.org # v4.19+
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220520094600.2066945-1-jani.nikula@intel.com
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 33 +++++++++++++-------
 1 file changed, 22 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index f370e9c4350dc..dd24aef925f2e 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -125,9 +125,25 @@ struct i2c_adapter_lookup {
 #define  ICL_GPIO_DDPA_CTRLCLK_2	8
 #define  ICL_GPIO_DDPA_CTRLDATA_2	9
 
-static enum port intel_dsi_seq_port_to_port(u8 port)
+static enum port intel_dsi_seq_port_to_port(struct intel_dsi *intel_dsi,
+					    u8 seq_port)
 {
-	return port ? PORT_C : PORT_A;
+	/*
+	 * If single link DSI is being used on any port, the VBT sequence block
+	 * send packet apparently always has 0 for the port. Just use the port
+	 * we have configured, and ignore the sequence block port.
+	 */
+	if (hweight8(intel_dsi->ports) == 1)
+		return ffs(intel_dsi->ports) - 1;
+
+	if (seq_port) {
+		if (intel_dsi->ports & PORT_B)
+			return PORT_B;
+		else if (intel_dsi->ports & PORT_C)
+			return PORT_C;
+	}
+
+	return PORT_A;
 }
 
 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
@@ -149,15 +165,10 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
 
 	seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
 
-	/* For DSI single link on Port A & C, the seq_port value which is
-	 * parsed from Sequence Block#53 of VBT has been set to 0
-	 * Now, read/write of packets for the DSI single link on Port A and
-	 * Port C will based on the DVO port from VBT block 2.
-	 */
-	if (intel_dsi->ports == (1 << PORT_C))
-		port = PORT_C;
-	else
-		port = intel_dsi_seq_port_to_port(seq_port);
+	port = intel_dsi_seq_port_to_port(intel_dsi, seq_port);
+
+	if (drm_WARN_ON(&dev_priv->drm, !intel_dsi->dsi_hosts[port]))
+		goto out;
 
 	dsi_device = intel_dsi->dsi_hosts[port]->device;
 	if (!dsi_device) {
-- 
GitLab


From 39b1bc4b5bcccac781267bb826b035fbb99c8b9d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Thu, 19 May 2022 17:00:10 +0300
Subject: [PATCH 0076/1731] drm/i915: Rename block_size()/block_offset()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Give block_size()/block_offset() a "raw_" prefix since they
both operate on the "raw" (as in not duplicated) BDB block
contents.

What actually spurred this was a conflict between intel_bios.c
block_size() vs. block_size() from blkdev.h. That only
happened to me on a custom tree where we somehow manage to
include blkdev.h into intel_bios.c. But I think the rename
makes sense anyway to clarify the purpose of these functions.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220519140010.10600-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index f7f49a03a2e49..befd579f6006e 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -122,7 +122,7 @@ find_raw_section(const void *_bdb, enum bdb_block_id section_id)
  * Offset from the start of BDB to the start of the
  * block data (just past the block header).
  */
-static u32 block_offset(const void *bdb, enum bdb_block_id section_id)
+static u32 raw_block_offset(const void *bdb, enum bdb_block_id section_id)
 {
 	const void *block;
 
@@ -134,7 +134,7 @@ static u32 block_offset(const void *bdb, enum bdb_block_id section_id)
 }
 
 /* size of the block excluding the header */
-static u32 block_size(const void *bdb, enum bdb_block_id section_id)
+static u32 raw_block_size(const void *bdb, enum bdb_block_id section_id)
 {
 	const void *block;
 
@@ -231,7 +231,7 @@ static bool validate_lfp_data_ptrs(const void *bdb,
 	int data_block_size, lfp_data_size;
 	int i;
 
-	data_block_size = block_size(bdb, BDB_LVDS_LFP_DATA);
+	data_block_size = raw_block_size(bdb, BDB_LVDS_LFP_DATA);
 	if (data_block_size == 0)
 		return false;
 
@@ -308,7 +308,7 @@ static bool fixup_lfp_data_ptrs(const void *bdb, void *ptrs_block)
 	u32 offset;
 	int i;
 
-	offset = block_offset(bdb, BDB_LVDS_LFP_DATA);
+	offset = raw_block_offset(bdb, BDB_LVDS_LFP_DATA);
 
 	for (i = 0; i < 16; i++) {
 		if (ptrs->ptr[i].fp_timing.offset < offset ||
-- 
GitLab


From 991dcb89caeb1b9bf714b382e23d3f6d8016e744 Mon Sep 17 00:00:00 2001
From: Imre Deak <imre.deak@intel.com>
Date: Sat, 21 May 2022 16:08:08 +0300
Subject: [PATCH 0077/1731] drm/i915/d12+: Disable DMC firmware flip queue
 handlers

Based on a bspec update the DMC firmware's flip queue handling events
need to be disabled before enabling DC5/6. i915 doesn't use the flip
queue feature atm, so disable it already after loading the firmware.
This removes some overhead of the event handler which runs at a 1 kHz
frequency.

Bspec: 49193, 72486, 72487

v2:
- Fix the DMC pipe A register offsets for GEN12.
- Disable the events on DG2 only on pipe A..D .
v3: (Lucas)
- Add TODO: to clarify the disabling sequence on all D13+
- s/intel_dmc_has_fw_payload/has_dmc_id_fw/
- s/simple_flipq/flipq/
- s/_GEN12,_GEN13/TGL_,ADLP_/
- s/MAINDMC/DMC/
v4:
- Only disable flip queues on TGL/DG2, as on other platforms the
  corresponding event handlers don't exist.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> # v1
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220521130808.637449-1-imre.deak@intel.com
---
 drivers/gpu/drm/i915/display/intel_dmc.c      | 93 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dmc_regs.h | 41 ++++++++
 2 files changed, 133 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 34d00f5aff257..fa9ef591b8853 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -248,9 +248,14 @@ struct stepping_info {
 	char substepping;
 };
 
+static bool has_dmc_id_fw(struct drm_i915_private *i915, int dmc_id)
+{
+	return i915->dmc.dmc_info[dmc_id].payload;
+}
+
 bool intel_dmc_has_payload(struct drm_i915_private *i915)
 {
-	return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
+	return has_dmc_id_fw(i915, DMC_FW_MAIN);
 }
 
 static const struct stepping_info *
@@ -272,6 +277,85 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 	intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
 }
 
+static void
+disable_flip_queue_event(struct drm_i915_private *i915,
+			 i915_reg_t ctl_reg, i915_reg_t htp_reg)
+{
+	u32 event_ctl;
+	u32 event_htp;
+
+	event_ctl = intel_de_read(i915, ctl_reg);
+	event_htp = intel_de_read(i915, htp_reg);
+	if (event_ctl != (DMC_EVT_CTL_ENABLE |
+			  DMC_EVT_CTL_RECURRING |
+			  REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
+					 DMC_EVT_CTL_TYPE_EDGE_0_1) |
+			  REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
+					 DMC_EVT_CTL_EVENT_ID_CLK_MSEC)) ||
+	    !event_htp) {
+		drm_dbg_kms(&i915->drm,
+			    "Unexpected DMC event configuration (control %08x htp %08x)\n",
+			    event_ctl, event_htp);
+		return;
+	}
+
+	intel_de_write(i915, ctl_reg,
+		       REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
+				      DMC_EVT_CTL_TYPE_EDGE_0_1) |
+		       REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
+				      DMC_EVT_CTL_EVENT_ID_FALSE));
+	intel_de_write(i915, htp_reg, 0);
+}
+
+static bool
+get_flip_queue_event_regs(struct drm_i915_private *i915, int dmc_id,
+			  i915_reg_t *ctl_reg, i915_reg_t *htp_reg)
+{
+	switch (dmc_id) {
+	case DMC_FW_MAIN:
+		if (DISPLAY_VER(i915) == 12) {
+			*ctl_reg = DMC_EVT_CTL(i915, dmc_id, 3);
+			*htp_reg = DMC_EVT_HTP(i915, dmc_id, 3);
+
+			return true;
+		}
+		break;
+	case DMC_FW_PIPEA ... DMC_FW_PIPED:
+		if (IS_DG2(i915)) {
+			*ctl_reg = DMC_EVT_CTL(i915, dmc_id, 2);
+			*htp_reg = DMC_EVT_HTP(i915, dmc_id, 2);
+
+			return true;
+		}
+		break;
+	}
+
+	return false;
+}
+
+static void
+disable_all_flip_queue_events(struct drm_i915_private *i915)
+{
+	int dmc_id;
+
+	/* TODO: check if the following applies to all D13+ platforms. */
+	if (!IS_DG2(i915) && !IS_TIGERLAKE(i915))
+		return;
+
+	for (dmc_id = 0; dmc_id < DMC_FW_MAX; dmc_id++) {
+		i915_reg_t ctl_reg;
+		i915_reg_t htp_reg;
+
+		if (!has_dmc_id_fw(i915, dmc_id))
+			continue;
+
+		if (!get_flip_queue_event_regs(i915, dmc_id, &ctl_reg, &htp_reg))
+			continue;
+
+		disable_flip_queue_event(i915, ctl_reg, htp_reg);
+	}
+}
+
 /**
  * intel_dmc_load_program() - write the firmware from memory to register.
  * @dev_priv: i915 drm device.
@@ -312,6 +396,13 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
 	dev_priv->dmc.dc_state = 0;
 
 	gen9_set_dc_state_debugmask(dev_priv);
+
+	/*
+	 * Flip queue events need to be disabled before enabling DC5/6.
+	 * i915 doesn't use the flip queue feature, so disable it already
+	 * here.
+	 */
+	disable_all_flip_queue_events(dev_priv);
 }
 
 void assert_dmc_loaded(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index 67e14eb96a7aa..238620b559662 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -10,6 +10,47 @@
 
 #define DMC_PROGRAM(addr, i)	_MMIO((addr) + (i) * 4)
 #define DMC_SSP_BASE_ADDR_GEN9	0x00002FC0
+
+#define _ADLP_PIPEDMC_REG_MMIO_BASE_A	0x5f000
+#define _TGL_PIPEDMC_REG_MMIO_BASE_A	0x92000
+
+#define __PIPEDMC_REG_MMIO_BASE(i915, dmc_id) \
+	((DISPLAY_VER(i915) >= 13 ? _ADLP_PIPEDMC_REG_MMIO_BASE_A : \
+				    _TGL_PIPEDMC_REG_MMIO_BASE_A) + \
+	 0x400 * ((dmc_id) - 1))
+
+#define __DMC_REG_MMIO_BASE		0x8f000
+
+#define _DMC_REG_MMIO_BASE(i915, dmc_id) \
+	((dmc_id) == DMC_FW_MAIN ? __DMC_REG_MMIO_BASE : \
+				   __PIPEDMC_REG_MMIO_BASE(i915, dmc_id))
+
+#define _DMC_REG(i915, dmc_id, reg) \
+	((reg) - __DMC_REG_MMIO_BASE + _DMC_REG_MMIO_BASE(i915, dmc_id))
+
+#define _DMC_EVT_HTP_0			0x8f004
+
+#define DMC_EVT_HTP(i915, dmc_id, handler) \
+	_MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_HTP_0) + 4 * (handler))
+
+#define _DMC_EVT_CTL_0			0x8f034
+
+#define DMC_EVT_CTL(i915, dmc_id, handler) \
+	_MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_CTL_0) + 4 * (handler))
+
+#define DMC_EVT_CTL_ENABLE		REG_BIT(31)
+#define DMC_EVT_CTL_RECURRING		REG_BIT(30)
+#define DMC_EVT_CTL_TYPE_MASK		REG_GENMASK(17, 16)
+#define DMC_EVT_CTL_TYPE_LEVEL_0	0
+#define DMC_EVT_CTL_TYPE_LEVEL_1	1
+#define DMC_EVT_CTL_TYPE_EDGE_1_0	2
+#define DMC_EVT_CTL_TYPE_EDGE_0_1	3
+
+#define DMC_EVT_CTL_EVENT_ID_MASK	REG_GENMASK(15, 8)
+#define DMC_EVT_CTL_EVENT_ID_FALSE	0x01
+/* An event handler scheduled to run at a 1 kHz frequency. */
+#define DMC_EVT_CTL_EVENT_ID_CLK_MSEC	0xbf
+
 #define DMC_HTP_ADDR_SKL	0x00500034
 #define DMC_SSP_BASE		_MMIO(0x8F074)
 #define DMC_HTP_SKL		_MMIO(0x8F004)
-- 
GitLab


From d63ddca7c58132257fd01e3a4feca41b3bac3089 Mon Sep 17 00:00:00 2001
From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Date: Mon, 16 May 2022 10:20:15 +0200
Subject: [PATCH 0078/1731] drm/i915: Update tiled blits selftest
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Update the selftest to include Tile 4 mode and switch to Tile 4 on
platforms that supports Tile 4 but no Tile Y and vice versa.
Also switch to XY_FAST_COPY_BLT on platforms that supports it.

v4: update commit message to reflect the code changes properly.
v3: add a function to find X-tile availability for a platform.
v2: disable Tile X for iGPU in fastblit and
    fix checkpath --strict warnings.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5879
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Co-developed-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220516082015.32020-1-nirmoy.das@intel.com
---
 .../i915/gem/selftests/i915_gem_client_blt.c  | 250 ++++++++++++++----
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h  |  22 ++
 2 files changed, 227 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index ddd0772fd8286..3cfc621ef363d 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -6,6 +6,7 @@
 #include "i915_selftest.h"
 
 #include "gt/intel_context.h"
+#include "gt/intel_engine_regs.h"
 #include "gt/intel_engine_user.h"
 #include "gt/intel_gpu_commands.h"
 #include "gt/intel_gt.h"
@@ -18,10 +19,71 @@
 #include "huge_gem_object.h"
 #include "mock_context.h"
 
+#define OW_SIZE 16                      /* in bytes */
+#define F_SUBTILE_SIZE 64               /* in bytes */
+#define F_TILE_WIDTH 128                /* in bytes */
+#define F_TILE_HEIGHT 32                /* in pixels */
+#define F_SUBTILE_WIDTH  OW_SIZE        /* in bytes */
+#define F_SUBTILE_HEIGHT 4              /* in pixels */
+
+static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp)
+{
+	int tile_base;
+	int tile_x, tile_y;
+	int swizzle, subtile;
+	int pixel_size = bpp / 8;
+	int pos;
+
+	/*
+	 * Subtile remapping for F tile. Note that map[a]==b implies map[b]==a
+	 * so we can use the same table to tile and until.
+	 */
+	static const u8 f_subtile_map[] = {
+		 0,  1,  2,  3,  8,  9, 10, 11,
+		 4,  5,  6,  7, 12, 13, 14, 15,
+		16, 17, 18, 19, 24, 25, 26, 27,
+		20, 21, 22, 23, 28, 29, 30, 31,
+		32, 33, 34, 35, 40, 41, 42, 43,
+		36, 37, 38, 39, 44, 45, 46, 47,
+		48, 49, 50, 51, 56, 57, 58, 59,
+		52, 53, 54, 55, 60, 61, 62, 63
+	};
+
+	x *= pixel_size;
+	/*
+	 * Where does the 4k tile start (in bytes)?  This is the same for Y and
+	 * F so we can use the Y-tile algorithm to get to that point.
+	 */
+	tile_base =
+		y / F_TILE_HEIGHT * stride * F_TILE_HEIGHT +
+		x / F_TILE_WIDTH * 4096;
+
+	/* Find pixel within tile */
+	tile_x = x % F_TILE_WIDTH;
+	tile_y = y % F_TILE_HEIGHT;
+
+	/* And figure out the subtile within the 4k tile */
+	subtile = tile_y / F_SUBTILE_HEIGHT * 8 + tile_x / F_SUBTILE_WIDTH;
+
+	/* Swizzle the subtile number according to the bspec diagram */
+	swizzle = f_subtile_map[subtile];
+
+	/* Calculate new position */
+	pos = tile_base +
+		swizzle * F_SUBTILE_SIZE +
+		tile_y % F_SUBTILE_HEIGHT * OW_SIZE +
+		tile_x % F_SUBTILE_WIDTH;
+
+	GEM_BUG_ON(!IS_ALIGNED(pos, pixel_size));
+
+	return pos / pixel_size * 4;
+}
+
 enum client_tiling {
 	CLIENT_TILING_LINEAR,
 	CLIENT_TILING_X,
 	CLIENT_TILING_Y,
+	CLIENT_TILING_4,
 	CLIENT_NUM_TILING_TYPES
 };
 
@@ -45,6 +107,36 @@ struct tiled_blits {
 	u32 height;
 };
 
+static bool supports_x_tiling(const struct drm_i915_private *i915)
+{
+	int gen = GRAPHICS_VER(i915);
+
+	if (gen < 12)
+		return true;
+
+	if (!HAS_LMEM(i915) || IS_DG1(i915))
+		return false;
+
+	return true;
+}
+
+static bool fast_blit_ok(const struct blit_buffer *buf)
+{
+	int gen = GRAPHICS_VER(buf->vma->vm->i915);
+
+	if (gen < 9)
+		return false;
+
+	if (gen < 12)
+		return true;
+
+	/* filter out platforms with unsupported X-tile support in fastblit */
+	if (buf->tiling == CLIENT_TILING_X && !supports_x_tiling(buf->vma->vm->i915))
+		return false;
+
+	return true;
+}
+
 static int prepare_blit(const struct tiled_blits *t,
 			struct blit_buffer *dst,
 			struct blit_buffer *src,
@@ -59,51 +151,103 @@ static int prepare_blit(const struct tiled_blits *t,
 	if (IS_ERR(cs))
 		return PTR_ERR(cs);
 
-	*cs++ = MI_LOAD_REGISTER_IMM(1);
-	*cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
-	cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
-	if (src->tiling == CLIENT_TILING_Y)
-		cmd |= BCS_SRC_Y;
-	if (dst->tiling == CLIENT_TILING_Y)
-		cmd |= BCS_DST_Y;
-	*cs++ = cmd;
-
-	cmd = MI_FLUSH_DW;
-	if (ver >= 8)
-		cmd++;
-	*cs++ = cmd;
-	*cs++ = 0;
-	*cs++ = 0;
-	*cs++ = 0;
-
-	cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2);
-	if (ver >= 8)
-		cmd += 2;
-
-	src_pitch = t->width * 4;
-	if (src->tiling) {
-		cmd |= XY_SRC_COPY_BLT_SRC_TILED;
-		src_pitch /= 4;
-	}
+	if (fast_blit_ok(dst) && fast_blit_ok(src)) {
+		struct intel_gt *gt = t->ce->engine->gt;
+		u32 src_tiles = 0, dst_tiles = 0;
+		u32 src_4t = 0, dst_4t = 0;
+
+		/* Need to program BLIT_CCTL if it is not done previously
+		 * before using XY_FAST_COPY_BLT
+		 */
+		*cs++ = MI_LOAD_REGISTER_IMM(1);
+		*cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base));
+		*cs++ = (BLIT_CCTL_SRC_MOCS(gt->mocs.uc_index) |
+			 BLIT_CCTL_DST_MOCS(gt->mocs.uc_index));
+
+		src_pitch = t->width; /* in dwords */
+		if (src->tiling == CLIENT_TILING_4) {
+			src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
+			src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4;
+		} else if (src->tiling == CLIENT_TILING_Y) {
+			src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
+		} else if (src->tiling == CLIENT_TILING_X) {
+			src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X);
+		} else {
+			src_pitch *= 4; /* in bytes */
+		}
 
-	dst_pitch = t->width * 4;
-	if (dst->tiling) {
-		cmd |= XY_SRC_COPY_BLT_DST_TILED;
-		dst_pitch /= 4;
-	}
+		dst_pitch = t->width; /* in dwords */
+		if (dst->tiling == CLIENT_TILING_4) {
+			dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
+			dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4;
+		} else if (dst->tiling == CLIENT_TILING_Y) {
+			dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
+		} else if (dst->tiling == CLIENT_TILING_X) {
+			dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X);
+		} else {
+			dst_pitch *= 4; /* in bytes */
+		}
 
-	*cs++ = cmd;
-	*cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
-	*cs++ = 0;
-	*cs++ = t->height << 16 | t->width;
-	*cs++ = lower_32_bits(dst->vma->node.start);
-	if (use_64b_reloc)
+		*cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2) |
+			src_tiles | dst_tiles;
+		*cs++ = src_4t | dst_4t | BLT_DEPTH_32 | dst_pitch;
+		*cs++ = 0;
+		*cs++ = t->height << 16 | t->width;
+		*cs++ = lower_32_bits(dst->vma->node.start);
 		*cs++ = upper_32_bits(dst->vma->node.start);
-	*cs++ = 0;
-	*cs++ = src_pitch;
-	*cs++ = lower_32_bits(src->vma->node.start);
-	if (use_64b_reloc)
+		*cs++ = 0;
+		*cs++ = src_pitch;
+		*cs++ = lower_32_bits(src->vma->node.start);
 		*cs++ = upper_32_bits(src->vma->node.start);
+	} else {
+		if (ver >= 6) {
+			*cs++ = MI_LOAD_REGISTER_IMM(1);
+			*cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
+			cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
+			if (src->tiling == CLIENT_TILING_Y)
+				cmd |= BCS_SRC_Y;
+			if (dst->tiling == CLIENT_TILING_Y)
+				cmd |= BCS_DST_Y;
+			*cs++ = cmd;
+
+			cmd = MI_FLUSH_DW;
+			if (ver >= 8)
+				cmd++;
+			*cs++ = cmd;
+			*cs++ = 0;
+			*cs++ = 0;
+			*cs++ = 0;
+		}
+
+		cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2);
+		if (ver >= 8)
+			cmd += 2;
+
+		src_pitch = t->width * 4;
+		if (src->tiling) {
+			cmd |= XY_SRC_COPY_BLT_SRC_TILED;
+			src_pitch /= 4;
+		}
+
+		dst_pitch = t->width * 4;
+		if (dst->tiling) {
+			cmd |= XY_SRC_COPY_BLT_DST_TILED;
+			dst_pitch /= 4;
+		}
+
+		*cs++ = cmd;
+		*cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
+		*cs++ = 0;
+		*cs++ = t->height << 16 | t->width;
+		*cs++ = lower_32_bits(dst->vma->node.start);
+		if (use_64b_reloc)
+			*cs++ = upper_32_bits(dst->vma->node.start);
+		*cs++ = 0;
+		*cs++ = src_pitch;
+		*cs++ = lower_32_bits(src->vma->node.start);
+		if (use_64b_reloc)
+			*cs++ = upper_32_bits(src->vma->node.start);
+	}
 
 	*cs++ = MI_BATCH_BUFFER_END;
 
@@ -181,7 +325,13 @@ static int tiled_blits_create_buffers(struct tiled_blits *t,
 
 		t->buffers[i].vma = vma;
 		t->buffers[i].tiling =
-			i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng);
+			i915_prandom_u32_max_state(CLIENT_NUM_TILING_TYPES, prng);
+
+		/* Platforms support either TileY or Tile4, not both */
+		if (HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_Y)
+			t->buffers[i].tiling = CLIENT_TILING_4;
+		else if (!HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_4)
+			t->buffers[i].tiling = CLIENT_TILING_Y;
 	}
 
 	return 0;
@@ -206,7 +356,8 @@ static u64 swizzle_bit(unsigned int bit, u64 offset)
 static u64 tiled_offset(const struct intel_gt *gt,
 			u64 v,
 			unsigned int stride,
-			enum client_tiling tiling)
+			enum client_tiling tiling,
+			int x_pos, int y_pos)
 {
 	unsigned int swizzle;
 	u64 x, y;
@@ -216,7 +367,12 @@ static u64 tiled_offset(const struct intel_gt *gt,
 
 	y = div64_u64_rem(v, stride, &x);
 
-	if (tiling == CLIENT_TILING_X) {
+	if (tiling == CLIENT_TILING_4) {
+		v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32);
+
+		/* no swizzling for f-tiling */
+		swizzle = I915_BIT_6_SWIZZLE_NONE;
+	} else if (tiling == CLIENT_TILING_X) {
 		v = div64_u64_rem(y, 8, &y) * stride * 8;
 		v += y * 512;
 		v += div64_u64_rem(x, 512, &x) << 12;
@@ -259,6 +415,7 @@ static const char *repr_tiling(enum client_tiling tiling)
 	case CLIENT_TILING_LINEAR: return "linear";
 	case CLIENT_TILING_X: return "X";
 	case CLIENT_TILING_Y: return "Y";
+	case CLIENT_TILING_4: return "F";
 	default: return "unknown";
 	}
 }
@@ -284,7 +441,7 @@ static int verify_buffer(const struct tiled_blits *t,
 	} else {
 		u64 v = tiled_offset(buf->vma->vm->gt,
 				     p * 4, t->width * 4,
-				     buf->tiling);
+				     buf->tiling, x, y);
 
 		if (vaddr[v / sizeof(*vaddr)] != buf->start_val + p)
 			ret = -EINVAL;
@@ -504,6 +661,9 @@ static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng)
 	if (err)
 		return err;
 
+	/* Simulating GTT eviction of the same buffer / layout */
+	t->buffers[2].tiling = t->buffers[0].tiling;
+
 	/* Reposition so that we overlap the old addresses, and slightly off */
 	err = tiled_blit(t,
 			 &t->buffers[2], t->hole + t->align,
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 556bca3be8040..246ab8f7bf578 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -236,6 +236,28 @@
 #define   XY_FAST_COLOR_BLT_DW		16
 #define   XY_FAST_COLOR_BLT_MOCS_MASK	GENMASK(27, 21)
 #define   XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31
+
+#define   XY_FAST_COPY_BLT_D0_SRC_TILING_MASK     REG_GENMASK(21, 20)
+#define   XY_FAST_COPY_BLT_D0_DST_TILING_MASK     REG_GENMASK(14, 13)
+#define   XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(mode)  \
+	REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode)
+#define   XY_FAST_COPY_BLT_D0_DST_TILE_MODE(mode)  \
+	REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode)
+#define     LINEAR				0
+#define     TILE_X				0x1
+#define     XMAJOR				0x1
+#define     YMAJOR				0x2
+#define     TILE_64			0x3
+#define   XY_FAST_COPY_BLT_D1_SRC_TILE4	REG_BIT(31)
+#define   XY_FAST_COPY_BLT_D1_DST_TILE4	REG_BIT(30)
+#define BLIT_CCTL_SRC_MOCS_MASK  REG_GENMASK(6, 0)
+#define BLIT_CCTL_DST_MOCS_MASK  REG_GENMASK(14, 8)
+/* Note:  MOCS value = (index << 1) */
+#define BLIT_CCTL_SRC_MOCS(idx) \
+	REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (idx) << 1)
+#define BLIT_CCTL_DST_MOCS(idx) \
+	REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (idx) << 1)
+
 #define SRC_COPY_BLT_CMD		(2 << 29 | 0x43 << 22)
 #define GEN9_XY_FAST_COPY_BLT_CMD	(2 << 29 | 0x42 << 22)
 #define XY_SRC_COPY_BLT_CMD		(2 << 29 | 0x53 << 22)
-- 
GitLab


From 8ae664907916eba9a9d56296bed684c27318a872 Mon Sep 17 00:00:00 2001
From: Julia Lawall <Julia.Lawall@inria.fr>
Date: Sat, 21 May 2022 13:11:40 +0200
Subject: [PATCH 0079/1731] drm/i915: fix typos in comments

Spelling mistakes (triple letters) in comments.
Detected with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220521111145.81697-90-Julia.Lawall@inria.fr
---
 drivers/gpu/drm/i915/display/intel_color.c           | 2 +-
 drivers/gpu/drm/i915/display/intel_pps.c             | 2 +-
 drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c           | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 34128c9c635c3..a27ce874a9e86 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1638,7 +1638,7 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
 	/*
 	 * Enable 10bit gamma for D13
 	 * ToDo: Extend to Logarithmic Gamma once the new UAPI
-	 * is acccepted and implemented by a userspace consumer
+	 * is accepted and implemented by a userspace consumer
 	 */
 	else if (DISPLAY_VER(i915) >= 13)
 		gamma_mode |= GAMMA_MODE_MODE_10BIT;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 5a598dd060391..4bc0563dde92f 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -509,7 +509,7 @@ static void wait_panel_power_cycle(struct intel_dp *intel_dp)
 
 	drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
 
-	/* take the difference of currrent time and panel power off time
+	/* take the difference of current time and panel power off time
 	 * and then make panel wait for t11_t12 if needed. */
 	panel_power_on_time = ktime_get_boottime();
 	panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time);
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 1c602d4ae2974..1c3fc4e5c3ca6 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1352,7 +1352,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 			 * submission. If we don't cancel the timer now,
 			 * we will see that the timer has expired and
 			 * reschedule the tasklet; continually until the
-			 * next context switch or other preeemption event.
+			 * next context switch or other preemption event.
 			 *
 			 * Since we have decided to reschedule based on
 			 * consumption of this timeslice, if we submit the
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index a24dc64418721..2dfbb1af111e7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -555,7 +555,7 @@ int intel_guc_log_relay_open(struct intel_guc_log *log)
 	/*
 	 * We require SSE 4.1 for fast reads from the GuC log buffer and
 	 * it should be present on the chipsets supporting GuC based
-	 * submisssions.
+	 * submissions.
 	 */
 	if (!i915_has_memcpy_from_wc()) {
 		ret = -ENXIO;
-- 
GitLab


From d32e8ed918ba7384fda9055ebb31b89b3eadb517 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Tue, 10 May 2022 23:02:24 -0700
Subject: [PATCH 0080/1731] drm/i915/uncore: Reorganize and document shadow and
 forcewake tables

Let's reorganize some of the forcewake/shadow handling in intel_uncore.c
and consolidate the cargo-cult comments on each table into more general
comments that apply to all tables.

We'll probably move forcewake handling to its own dedicated file in the
near future and further enhance this with true kerneldoc.  But this is a
good intermediate step to help clarify the behavior a bit.

Cc: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220511060228.1179450-2-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/intel_uncore.c | 124 ++++++++++++++++++----------
 1 file changed, 79 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 83517a703eb6e..632327f62dfa5 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -938,36 +938,32 @@ find_fw_domain(struct intel_uncore *uncore, u32 offset)
 	return entry->domains;
 }
 
-#define GEN_FW_RANGE(s, e, d) \
-	{ .start = (s), .end = (e), .domains = (d) }
-
-/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
-static const struct intel_forcewake_range __vlv_fw_ranges[] = {
-	GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
-	GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
-	GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
-};
-
-#define __fwtable_reg_read_fw_domains(uncore, offset) \
-({ \
-	enum forcewake_domains __fwd = 0; \
-	if (NEEDS_FORCE_WAKE((offset))) \
-		__fwd = find_fw_domain(uncore, offset); \
-	__fwd; \
-})
+/*
+ * Shadowed register tables describe special register ranges that i915 is
+ * allowed to write to without acquiring forcewake.  If these registers' power
+ * wells are down, the hardware will save values written by i915 to a shadow
+ * copy and automatically transfer them into the real register the next time
+ * the power well is woken up.  Shadowing only applies to writes; forcewake
+ * must still be acquired when reading from registers in these ranges.
+ *
+ * The documentation for shadowed registers is somewhat spotty on older
+ * platforms.  However missing registers from these lists is non-fatal; it just
+ * means we'll wake up the hardware for some register accesses where we didn't
+ * really need to.
+ *
+ * The ranges listed in these tables must be sorted by offset.
+ *
+ * When adding new tables here, please also add them to
+ * intel_shadow_table_check() in selftests/intel_uncore.c so that they will be
+ * scanned for obvious mistakes or typos by the selftests.
+ */
 
-/* *Must* be sorted by offset! See intel_shadow_table_check(). */
 static const struct i915_range gen8_shadowed_regs[] = {
 	{ .start =  0x2030, .end =  0x2030 },
 	{ .start =  0xA008, .end =  0xA00C },
 	{ .start = 0x12030, .end = 0x12030 },
 	{ .start = 0x1a030, .end = 0x1a030 },
 	{ .start = 0x22030, .end = 0x22030 },
-	/* TODO: Other registers are not yet used */
 };
 
 static const struct i915_range gen11_shadowed_regs[] = {
@@ -1107,11 +1103,70 @@ gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
 	return FORCEWAKE_RENDER;
 }
 
+#define __fwtable_reg_read_fw_domains(uncore, offset) \
+({ \
+	enum forcewake_domains __fwd = 0; \
+	if (NEEDS_FORCE_WAKE((offset))) \
+		__fwd = find_fw_domain(uncore, offset); \
+	__fwd; \
+})
+
+#define __fwtable_reg_write_fw_domains(uncore, offset) \
+({ \
+	enum forcewake_domains __fwd = 0; \
+	const u32 __offset = (offset); \
+	if (NEEDS_FORCE_WAKE((__offset)) && !is_shadowed(uncore, __offset)) \
+		__fwd = find_fw_domain(uncore, __offset); \
+	__fwd; \
+})
+
+#define GEN_FW_RANGE(s, e, d) \
+	{ .start = (s), .end = (e), .domains = (d) }
+
+/*
+ * All platforms' forcewake tables below must be sorted by offset ranges.
+ * Furthermore, new forcewake tables added should be "watertight" and have
+ * no gaps between ranges.
+ *
+ * When there are multiple consecutive ranges listed in the bspec with
+ * the same forcewake domain, it is customary to combine them into a single
+ * row in the tables below to keep the tables small and lookups fast.
+ * Likewise, reserved/unused ranges may be combined with the preceding and/or
+ * following ranges since the driver will never be making MMIO accesses in
+ * those ranges.
+ *
+ * For example, if the bspec were to list:
+ *
+ *    ...
+ *    0x1000 - 0x1fff:  GT
+ *    0x2000 - 0x2cff:  GT
+ *    0x2d00 - 0x2fff:  unused/reserved
+ *    0x3000 - 0xffff:  GT
+ *    ...
+ *
+ * these could all be represented by a single line in the code:
+ *
+ *   GEN_FW_RANGE(0x1000, 0xffff, FORCEWAKE_GT)
+ *
+ * When adding new forcewake tables here, please also add them to
+ * intel_uncore_mock_selftests in selftests/intel_uncore.c so that they will be
+ * scanned for obvious mistakes or typos by the selftests.
+ */
+
 static const struct intel_forcewake_range __gen6_fw_ranges[] = {
 	GEN_FW_RANGE(0x0, 0x3ffff, FORCEWAKE_RENDER),
 };
 
-/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
+static const struct intel_forcewake_range __vlv_fw_ranges[] = {
+	GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
+	GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
+	GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
+};
+
 static const struct intel_forcewake_range __chv_fw_ranges[] = {
 	GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
 	GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
@@ -1131,16 +1186,6 @@ static const struct intel_forcewake_range __chv_fw_ranges[] = {
 	GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
 };
 
-#define __fwtable_reg_write_fw_domains(uncore, offset) \
-({ \
-	enum forcewake_domains __fwd = 0; \
-	const u32 __offset = (offset); \
-	if (NEEDS_FORCE_WAKE((__offset)) && !is_shadowed(uncore, __offset)) \
-		__fwd = find_fw_domain(uncore, __offset); \
-	__fwd; \
-})
-
-/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
 	GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
@@ -1176,7 +1221,6 @@ static const struct intel_forcewake_range __gen9_fw_ranges[] = {
 	GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
 };
 
-/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 static const struct intel_forcewake_range __gen11_fw_ranges[] = {
 	GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */
 	GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
@@ -1215,14 +1259,6 @@ static const struct intel_forcewake_range __gen11_fw_ranges[] = {
 	GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0)
 };
 
-/*
- * *Must* be sorted by offset ranges! See intel_fw_table_check().
- *
- * Note that the spec lists several reserved/unused ranges that don't
- * actually contain any registers.  In the table below we'll combine those
- * reserved ranges with either the preceding or following range to keep the
- * table small and lookups fast.
- */
 static const struct intel_forcewake_range __gen12_fw_ranges[] = {
 	GEN_FW_RANGE(0x0, 0x1fff, 0), /*
 		0x0   -  0xaff: reserved
@@ -1327,8 +1363,6 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
 /*
  * Graphics IP version 12.55 brings a slight change to the 0xd800 range,
  * switching it from the GT domain to the render domain.
- *
- * *Must* be sorted by offset ranges! See intel_fw_table_check().
  */
 #define XEHP_FWRANGES(FW_RANGE_D800)					\
 	GEN_FW_RANGE(0x0, 0x1fff, 0), /*					\
-- 
GitLab


From fb289464f695f9d913479b4ebae9e39b057f8531 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Tue, 10 May 2022 23:02:25 -0700
Subject: [PATCH 0081/1731] drm/i915/pvc: Add forcewake support

Add PVC's forcewake ranges.

v2:
 - Drop replicated comment completely; move general cleanup of the
   documentation to a separate patch.

Bspec: 67609
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220511060228.1179450-3-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/intel_uncore.c           | 142 +++++++++++++++++-
 drivers/gpu/drm/i915/selftests/intel_uncore.c |   2 +
 2 files changed, 143 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 632327f62dfa5..33304eb987e46 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1076,6 +1076,45 @@ static const struct i915_range dg2_shadowed_regs[] = {
 	{ .start = 0x1F8510, .end = 0x1F8550 },
 };
 
+static const struct i915_range pvc_shadowed_regs[] = {
+	{ .start =   0x2030, .end =   0x2030 },
+	{ .start =   0x2510, .end =   0x2550 },
+	{ .start =   0xA008, .end =   0xA00C },
+	{ .start =   0xA188, .end =   0xA188 },
+	{ .start =   0xA278, .end =   0xA278 },
+	{ .start =   0xA540, .end =   0xA56C },
+	{ .start =   0xC4C8, .end =   0xC4C8 },
+	{ .start =   0xC4E0, .end =   0xC4E0 },
+	{ .start =   0xC600, .end =   0xC600 },
+	{ .start =   0xC658, .end =   0xC658 },
+	{ .start =  0x22030, .end =  0x22030 },
+	{ .start =  0x22510, .end =  0x22550 },
+	{ .start = 0x1C0030, .end = 0x1C0030 },
+	{ .start = 0x1C0510, .end = 0x1C0550 },
+	{ .start = 0x1C4030, .end = 0x1C4030 },
+	{ .start = 0x1C4510, .end = 0x1C4550 },
+	{ .start = 0x1C8030, .end = 0x1C8030 },
+	{ .start = 0x1C8510, .end = 0x1C8550 },
+	{ .start = 0x1D0030, .end = 0x1D0030 },
+	{ .start = 0x1D0510, .end = 0x1D0550 },
+	{ .start = 0x1D4030, .end = 0x1D4030 },
+	{ .start = 0x1D4510, .end = 0x1D4550 },
+	{ .start = 0x1D8030, .end = 0x1D8030 },
+	{ .start = 0x1D8510, .end = 0x1D8550 },
+	{ .start = 0x1E0030, .end = 0x1E0030 },
+	{ .start = 0x1E0510, .end = 0x1E0550 },
+	{ .start = 0x1E4030, .end = 0x1E4030 },
+	{ .start = 0x1E4510, .end = 0x1E4550 },
+	{ .start = 0x1E8030, .end = 0x1E8030 },
+	{ .start = 0x1E8510, .end = 0x1E8550 },
+	{ .start = 0x1F0030, .end = 0x1F0030 },
+	{ .start = 0x1F0510, .end = 0x1F0550 },
+	{ .start = 0x1F4030, .end = 0x1F4030 },
+	{ .start = 0x1F4510, .end = 0x1F4550 },
+	{ .start = 0x1F8030, .end = 0x1F8030 },
+	{ .start = 0x1F8510, .end = 0x1F8550 },
+};
+
 static int mmio_range_cmp(u32 key, const struct i915_range *range)
 {
 	if (key < range->start)
@@ -1524,6 +1563,103 @@ static const struct intel_forcewake_range __dg2_fw_ranges[] = {
 	XEHP_FWRANGES(FORCEWAKE_RENDER)
 };
 
+static const struct intel_forcewake_range __pvc_fw_ranges[] = {
+	GEN_FW_RANGE(0x0, 0xaff, 0),
+	GEN_FW_RANGE(0xb00, 0xbff, FORCEWAKE_GT),
+	GEN_FW_RANGE(0xc00, 0xfff, 0),
+	GEN_FW_RANGE(0x1000, 0x1fff, FORCEWAKE_GT),
+	GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
+	GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0x4000, 0x813f, FORCEWAKE_GT), /*
+		0x4000 - 0x4aff: gt
+		0x4b00 - 0x4fff: reserved
+		0x5000 - 0x51ff: gt
+		0x5200 - 0x52ff: reserved
+		0x5300 - 0x53ff: gt
+		0x5400 - 0x7fff: reserved
+		0x8000 - 0x813f: gt */
+	GEN_FW_RANGE(0x8140, 0x817f, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0x8180, 0x81ff, 0),
+	GEN_FW_RANGE(0x8200, 0x94cf, FORCEWAKE_GT), /*
+		0x8200 - 0x82ff: gt
+		0x8300 - 0x84ff: reserved
+		0x8500 - 0x887f: gt
+		0x8880 - 0x8a7f: reserved
+		0x8a80 - 0x8aff: gt
+		0x8b00 - 0x8fff: reserved
+		0x9000 - 0x947f: gt
+		0x9480 - 0x94cf: reserved */
+	GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0x9560, 0x967f, 0), /*
+		0x9560 - 0x95ff: always on
+		0x9600 - 0x967f: reserved */
+	GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /*
+		0x9680 - 0x96ff: render
+		0x9700 - 0x97ff: reserved */
+	GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*
+		0x9800 - 0xb4ff: gt
+		0xb500 - 0xbfff: reserved
+		0xc000 - 0xcfff: gt */
+	GEN_FW_RANGE(0xd000, 0xd3ff, 0),
+	GEN_FW_RANGE(0xd400, 0xdbff, FORCEWAKE_GT),
+	GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*
+		0xdd00 - 0xddff: gt
+		0xde00 - 0xde7f: reserved */
+	GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*
+		0xde80 - 0xdeff: render
+		0xdf00 - 0xe1ff: reserved
+		0xe200 - 0xe7ff: render
+		0xe800 - 0xe8ff: reserved */
+	GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT), /*
+		 0xe900 -  0xe9ff: gt
+		 0xea00 -  0xebff: reserved
+		 0xec00 -  0xffff: gt
+		0x10000 - 0x11fff: reserved */
+	GEN_FW_RANGE(0x12000, 0x12fff, 0), /*
+		0x12000 - 0x127ff: always on
+		0x12800 - 0x12fff: reserved */
+	GEN_FW_RANGE(0x13000, 0x23fff, FORCEWAKE_GT), /*
+		0x13000 - 0x135ff: gt
+		0x13600 - 0x147ff: reserved
+		0x14800 - 0x153ff: gt
+		0x15400 - 0x19fff: reserved
+		0x1a000 - 0x1ffff: gt
+		0x20000 - 0x21fff: reserved
+		0x22000 - 0x23fff: gt */
+	GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
+		24000 - 0x2407f: always on
+		24080 - 0x2417f: reserved */
+	GEN_FW_RANGE(0x24180, 0x3ffff, FORCEWAKE_GT), /*
+		0x24180 - 0x241ff: gt
+		0x24200 - 0x251ff: reserved
+		0x25200 - 0x252ff: gt
+		0x25300 - 0x25fff: reserved
+		0x26000 - 0x27fff: gt
+		0x28000 - 0x2ffff: reserved
+		0x30000 - 0x3ffff: gt */
+	GEN_FW_RANGE(0x40000, 0x1bffff, 0),
+	GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
+		0x1c0000 - 0x1c2bff: VD0
+		0x1c2c00 - 0x1c2cff: reserved
+		0x1c2d00 - 0x1c2dff: VD0
+		0x1c2e00 - 0x1c3eff: reserved
+		0x1c3f00 - 0x1c3fff: VD0 */
+	GEN_FW_RANGE(0x1c4000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX1), /*
+		0x1c4000 - 0x1c6aff: VD1
+		0x1c6b00 - 0x1c7eff: reserved
+		0x1c7f00 - 0x1c7fff: VD1
+		0x1c8000 - 0x1cffff: reserved */
+	GEN_FW_RANGE(0x1d0000, 0x23ffff, FORCEWAKE_MEDIA_VDBOX2), /*
+		0x1d0000 - 0x1d2aff: VD2
+		0x1d2b00 - 0x1d3eff: reserved
+		0x1d3f00 - 0x1d3fff: VD2
+		0x1d4000 - 0x23ffff: reserved */
+	GEN_FW_RANGE(0x240000, 0x3dffff, 0),
+	GEN_FW_RANGE(0x3e0000, 0x3effff, FORCEWAKE_GT),
+};
+
 static void
 ilk_dummy_write(struct intel_uncore *uncore)
 {
@@ -2159,7 +2295,11 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
 
 	ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
 
-	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
+	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60)) {
+		ASSIGN_FW_DOMAINS_TABLE(uncore, __pvc_fw_ranges);
+		ASSIGN_SHADOW_TABLE(uncore, pvc_shadowed_regs);
+		ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
+	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
 		ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
 		ASSIGN_SHADOW_TABLE(uncore, dg2_shadowed_regs);
 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index cdd196783535a..fda9bb79c049d 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -69,6 +69,7 @@ static int intel_shadow_table_check(void)
 		{ gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) },
 		{ gen12_shadowed_regs, ARRAY_SIZE(gen12_shadowed_regs) },
 		{ dg2_shadowed_regs, ARRAY_SIZE(dg2_shadowed_regs) },
+		{ pvc_shadowed_regs, ARRAY_SIZE(pvc_shadowed_regs) },
 	};
 	const struct i915_range *range;
 	unsigned int i, j;
@@ -115,6 +116,7 @@ int intel_uncore_mock_selftests(void)
 		{ __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
 		{ __gen12_fw_ranges, ARRAY_SIZE(__gen12_fw_ranges), true },
 		{ __xehp_fw_ranges, ARRAY_SIZE(__xehp_fw_ranges), true },
+		{ __pvc_fw_ranges, ARRAY_SIZE(__pvc_fw_ranges), true },
 	};
 	int err, i;
 
-- 
GitLab


From 1eb31338994889ac34c4f841e5d54bf10111741b Mon Sep 17 00:00:00 2001
From: Stuart Summers <stuart.summers@intel.com>
Date: Tue, 10 May 2022 23:02:26 -0700
Subject: [PATCH 0082/1731] drm/i915/pvc: Remove additional 3D flags from
 PIPE_CONTROL

Although we already strip 3D-specific flags from PIPE_CONTROL
instructions when submitting to a compute engine, there are some
additional flags that need to be removed when the platform as a whole
lacks a 3D pipeline.  Add those restrictions here.

v2:
 - Replace LACKS_3D_PIPELINE checks with !HAS_3D_PIPELINE and add
   has_3d_pipeline to all platforms except PVC.  (Lucas)

Bspec: 47112
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220511060228.1179450-4-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c     | 18 ++++++++++++------
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 15 +++++++++++++--
 drivers/gpu/drm/i915/i915_drv.h              |  2 ++
 drivers/gpu/drm/i915/i915_pci.c              | 10 ++++++++++
 drivers/gpu/drm/i915/intel_device_info.h     |  1 +
 5 files changed, 38 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index daa1a61972f47..98645797962f5 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -197,8 +197,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 
 		flags |= PIPE_CONTROL_CS_STALL;
 
-		if (engine->class == COMPUTE_CLASS)
-			flags &= ~PIPE_CONTROL_3D_FLAGS;
+		if (!HAS_3D_PIPELINE(engine->i915))
+			flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
+		else if (engine->class == COMPUTE_CLASS)
+			flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
 
 		cs = intel_ring_begin(rq, 6);
 		if (IS_ERR(cs))
@@ -227,8 +229,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 
 		flags |= PIPE_CONTROL_CS_STALL;
 
-		if (engine->class == COMPUTE_CLASS)
-			flags &= ~PIPE_CONTROL_3D_FLAGS;
+		if (!HAS_3D_PIPELINE(engine->i915))
+			flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
+		else if (engine->class == COMPUTE_CLASS)
+			flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
 
 		if (!HAS_FLAT_CCS(rq->engine->i915))
 			count = 8 + 4;
@@ -717,8 +721,10 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
 		/* Wa_1409600907 */
 		flags |= PIPE_CONTROL_DEPTH_STALL;
 
-	if (rq->engine->class == COMPUTE_CLASS)
-		flags &= ~PIPE_CONTROL_3D_FLAGS;
+	if (!HAS_3D_PIPELINE(rq->engine->i915))
+		flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
+	else if (rq->engine->class == COMPUTE_CLASS)
+		flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
 
 	cs = gen12_emit_ggtt_write_rcs(cs,
 				       rq->fence.seqno,
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 246ab8f7bf578..d4e9702d3c8e7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -310,8 +310,11 @@
 #define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1<<0)
 #define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
 
-/* 3D-related flags can't be set on compute engine */
-#define PIPE_CONTROL_3D_FLAGS (\
+/*
+ * 3D-related flags that can't be set on _engines_ that lack access to the 3D
+ * pipeline (i.e., CCS engines).
+ */
+#define PIPE_CONTROL_3D_ENGINE_FLAGS (\
 		PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
 		PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
 		PIPE_CONTROL_TILE_CACHE_FLUSH | \
@@ -322,6 +325,14 @@
 		PIPE_CONTROL_VF_CACHE_INVALIDATE | \
 		PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
 
+/* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */
+#define PIPE_CONTROL_3D_ARCH_FLAGS ( \
+		PIPE_CONTROL_3D_ENGINE_FLAGS | \
+		PIPE_CONTROL_INDIRECT_STATE_DISABLE | \
+		PIPE_CONTROL_FLUSH_ENABLE | \
+		PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
+		PIPE_CONTROL_DC_FLUSH_ENABLE)
+
 #define MI_MATH(x)			MI_INSTR(0x1a, (x) - 1)
 #define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
 /* Opcodes for MI_MATH_INSTR */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c5fc402d9c50c..11ef106dba930 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1405,6 +1405,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915))
 
+#define HAS_3D_PIPELINE(i915)	(INTEL_INFO(i915)->has_3d_pipeline)
+
 /* i915_gem.c */
 void i915_gem_init_early(struct drm_i915_private *dev_priv);
 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b9f474d3bec4e..269d7c8f2f81d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -171,6 +171,7 @@
 	.display.overlay_needs_physical = 1, \
 	.display.has_gmch = 1, \
 	.gpu_reset_clobbers_display = true, \
+	.has_3d_pipeline = 1, \
 	.hws_needs_physical = 1, \
 	.unfenced_needs_alignment = 1, \
 	.platform_engine_mask = BIT(RCS0), \
@@ -190,6 +191,7 @@
 	.display.has_overlay = 1, \
 	.display.overlay_needs_physical = 1, \
 	.display.has_gmch = 1, \
+	.has_3d_pipeline = 1, \
 	.gpu_reset_clobbers_display = true, \
 	.hws_needs_physical = 1, \
 	.unfenced_needs_alignment = 1, \
@@ -232,6 +234,7 @@ static const struct intel_device_info i865g_info = {
 	.display.has_gmch = 1, \
 	.gpu_reset_clobbers_display = true, \
 	.platform_engine_mask = BIT(RCS0), \
+	.has_3d_pipeline = 1, \
 	.has_snoop = true, \
 	.has_coherent_ggtt = true, \
 	.dma_mask_size = 32, \
@@ -323,6 +326,7 @@ static const struct intel_device_info pnv_m_info = {
 	.display.has_gmch = 1, \
 	.gpu_reset_clobbers_display = true, \
 	.platform_engine_mask = BIT(RCS0), \
+	.has_3d_pipeline = 1, \
 	.has_snoop = true, \
 	.has_coherent_ggtt = true, \
 	.dma_mask_size = 36, \
@@ -374,6 +378,7 @@ static const struct intel_device_info gm45_info = {
 	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 	.display.has_hotplug = 1, \
 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
+	.has_3d_pipeline = 1, \
 	.has_snoop = true, \
 	.has_coherent_ggtt = true, \
 	/* ilk does support rc6, but we do not implement [power] contexts */ \
@@ -405,6 +410,7 @@ static const struct intel_device_info ilk_m_info = {
 	.display.has_hotplug = 1, \
 	.display.fbc_mask = BIT(INTEL_FBC_A), \
 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
+	.has_3d_pipeline = 1, \
 	.has_coherent_ggtt = true, \
 	.has_llc = 1, \
 	.has_rc6 = 1, \
@@ -456,6 +462,7 @@ static const struct intel_device_info snb_m_gt2_info = {
 	.display.has_hotplug = 1, \
 	.display.fbc_mask = BIT(INTEL_FBC_A), \
 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
+	.has_3d_pipeline = 1, \
 	.has_coherent_ggtt = true, \
 	.has_llc = 1, \
 	.has_rc6 = 1, \
@@ -692,6 +699,7 @@ static const struct intel_device_info skl_gt4_info = {
 	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 		BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
+	.has_3d_pipeline = 1, \
 	.has_64bit_reloc = 1, \
 	.display.has_ddi = 1, \
 	.display.has_fpga_dbg = 1, \
@@ -1005,6 +1013,7 @@ static const struct intel_device_info adl_p_info = {
 	.graphics.rel = 50, \
 	XE_HP_PAGE_SIZES, \
 	.dma_mask_size = 46, \
+	.has_3d_pipeline = 1, \
 	.has_64bit_reloc = 1, \
 	.has_flat_ccs = 1, \
 	.has_global_mocs = 1, \
@@ -1080,6 +1089,7 @@ static const struct intel_device_info ats_m_info = {
 #define XE_HPC_FEATURES \
 	XE_HP_FEATURES, \
 	.dma_mask_size = 52, \
+	.has_3d_pipeline = 0, \
 	.has_l3_ccs_read = 1
 
 __maybe_unused
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index a134914237dd0..4e1c80966ab56 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -143,6 +143,7 @@ enum intel_ppgtt_type {
 	func(needs_compact_pt); \
 	func(gpu_reset_clobbers_display); \
 	func(has_reset_engine); \
+	func(has_3d_pipeline); \
 	func(has_4tile); \
 	func(has_flat_ccs); \
 	func(has_global_mocs); \
-- 
GitLab


From e41388d508a50ddb2be5c2676f1992353ca2f155 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Tue, 10 May 2022 23:02:27 -0700
Subject: [PATCH 0083/1731] drm/i915/pvc: Add new BCS engines to GuC engine
 list

Initialize ADS system info to reflect the availability of new BCS
engines

Original-author: CQ Tang
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220511060228.1179450-5-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h            | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 3eabf4cf8eec3..bb197610fd5b0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -457,7 +457,7 @@ static void fill_engine_enable_masks(struct intel_gt *gt,
 {
 	info_map_write(info_map, engine_enabled_masks[GUC_RENDER_CLASS], RCS_MASK(gt));
 	info_map_write(info_map, engine_enabled_masks[GUC_COMPUTE_CLASS], CCS_MASK(gt));
-	info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], 1);
+	info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], BCS_MASK(gt));
 	info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS], VDBOX_MASK(gt));
 	info_map_write(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS], VEBOX_MASK(gt));
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 11ef106dba930..74b3caccd8390 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1223,6 +1223,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 })
 #define RCS_MASK(gt) \
 	ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
+#define BCS_MASK(gt) \
+	ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
 #define VDBOX_MASK(gt) \
 	ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
 #define VEBOX_MASK(gt) \
-- 
GitLab


From a4f263f46961b1229b10ca3a98f0be618a9d47ac Mon Sep 17 00:00:00 2001
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Date: Tue, 10 May 2022 23:02:28 -0700
Subject: [PATCH 0084/1731] drm/i915/guc: XEHPSDV and PVC do not use HuC

Disable HuC loading since it is not used on these platforms.

Cc: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220511060228.1179450-6-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 3c3527cb00075..f2e7c82985efd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -45,6 +45,10 @@ static void uc_expand_default_options(struct intel_uc *uc)
 
 	/* Default: enable HuC authentication and GuC submission */
 	i915->params.enable_guc = ENABLE_GUC_LOAD_HUC | ENABLE_GUC_SUBMISSION;
+
+	/* XEHPSDV and PVC do not use HuC */
+	if (IS_XEHPSDV(i915) || IS_PONTEVECCHIO(i915))
+		i915->params.enable_guc &= ~ENABLE_GUC_LOAD_HUC;
 }
 
 /* Reset GuC providing us with fresh state for both GuC and HuC.
-- 
GitLab


From 837c72b23a57e15dd363d5f3f3f268c49c128740 Mon Sep 17 00:00:00 2001
From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Date: Mon, 23 May 2022 13:21:16 +0530
Subject: [PATCH 0085/1731] drm/i915/hwconfig: Report no hwconfig support on
 ADL-N

ADL-N being a subplatform of ADL-P, it lacks support for hwconfig
table. Explicit check added to skip ADL-N.

Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220523075116.207677-1-balasubramani.vivekanandan@intel.com
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
index 79c66b6b51a3f..5aaa3948de741 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
@@ -94,7 +94,7 @@ static int guc_hwconfig_fill_buffer(struct intel_guc *guc, struct intel_hwconfig
 
 static bool has_table(struct drm_i915_private *i915)
 {
-	if (IS_ALDERLAKE_P(i915))
+	if (IS_ALDERLAKE_P(i915) && !IS_ADLP_N(i915))
 		return true;
 	if (IS_DG2(i915))
 		return true;
-- 
GitLab


From edd34368c4c3b45b1386b15f78b2229420f8c6d4 Mon Sep 17 00:00:00 2001
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
Date: Wed, 25 May 2022 13:34:01 +0530
Subject: [PATCH 0086/1731] drm/i915/dg2: Support 4k@30 on HDMI

This patch adds a fix to support 297MHz of dot clock by calculating
the pll values using synopsis algorithm.
This will help to support 4k@30 mode for HDMI monitors on DG2.

v2: As per the algorithm, set MPLLB VCO range control bits to 3,
in register SNPS_PHY_MPLLB_DIV for 297Mhz. (Matt)

v3: Fix typo. (Ankit)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220525080401.1253511-1-ankit.k.nautiyal@intel.com
---
 drivers/gpu/drm/i915/display/intel_snps_phy.c | 32 +++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 0dd4775e8195e..cc1270978b67e 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -517,6 +517,37 @@ static const struct intel_mpllb_state dg2_hdmi_148_5 = {
 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
 };
 
+/* values in the below table are calculted using the algo */
+static const struct intel_mpllb_state dg2_hdmi_297 = {
+	.clock = 297000,
+	.ref_control =
+		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+	.mpllb_cp =
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+	.mpllb_div =
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
+	.mpllb_div2 =
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+	.mpllb_fracn1 =
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+	.mpllb_fracn2 =
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
+	.mpllb_sscen =
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
 static const struct intel_mpllb_state dg2_hdmi_594 = {
 	.clock = 594000,
 	.ref_control =
@@ -551,6 +582,7 @@ static const struct intel_mpllb_state * const dg2_hdmi_tables[] = {
 	&dg2_hdmi_27_0,
 	&dg2_hdmi_74_25,
 	&dg2_hdmi_148_5,
+	&dg2_hdmi_297,
 	&dg2_hdmi_594,
 	NULL,
 };
-- 
GitLab


From 16e214d4aef2d600ef94e845530a28ce795b8fcc Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Tue, 24 May 2022 16:59:06 -0700
Subject: [PATCH 0087/1731] drm/i915/hwconfig: Future-proof platform checks

PVC also has a hwconfig table.  Actually the current expectation is that
all future platforms will have hwconfig, so let's just change the
condition to an IP version check so that we don't need to keep updating
this for each new platform that shows up.

Cc: John Harrison <john.c.harrison@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220524235906.529771-1-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
index 5aaa3948de741..4781fccc2687d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
@@ -96,7 +96,7 @@ static bool has_table(struct drm_i915_private *i915)
 {
 	if (IS_ALDERLAKE_P(i915) && !IS_ADLP_N(i915))
 		return true;
-	if (IS_DG2(i915))
+	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
 		return true;
 
 	return false;
-- 
GitLab


From 3304033a1e69cd81a2044b4422f0d7e593afb4e6 Mon Sep 17 00:00:00 2001
From: Alan Previn <alan.previn.teres.alexis@intel.com>
Date: Thu, 10 Mar 2022 16:43:11 -0800
Subject: [PATCH 0088/1731] drm/i915/reset: Fix error_state_read ptr + offset
 use

Fix our pointer offset usage in error_state_read
when there is no i915_gpu_coredump but buf offset
is non-zero.

This fixes a kernel page fault can happen when
multiple tests are running concurrently in a loop
and one is producing engine resets and consuming
the i915 error_state dump while the other is
forcing full GT resets. (takes a while to trigger).

The dmesg call trace:

[ 5590.803000] BUG: unable to handle page fault for address:
               ffffffffa0b0e000
[ 5590.803009] #PF: supervisor read access in kernel mode
[ 5590.803013] #PF: error_code(0x0000) - not-present page
[ 5590.803016] PGD 5814067 P4D 5814067 PUD 5815063 PMD 109de4067
               PTE 0
[ 5590.803022] Oops: 0000 [#1] PREEMPT SMP NOPTI
[ 5590.803026] CPU: 5 PID: 13656 Comm: i915_hangman Tainted: G U
                    5.17.0-rc5-ups69-guc-err-capt-rev6+ #136
[ 5590.803033] Hardware name: Intel Corporation Alder Lake Client
                    Platform/AlderLake-M LP4x RVP, BIOS ADLPFWI1.R00.
                    3031.A02.2201171222	01/17/2022
[ 5590.803039] RIP: 0010:memcpy_erms+0x6/0x10
[ 5590.803045] Code: fe ff ff cc eb 1e 0f 1f 00 48 89 f8 48 89 d1
                     48 c1 e9 03 83 e2 07 f3 48 a5 89 d1 f3 a4 c3
                     66 0f 1f 44 00 00 48 89 f8 48 89 d1 <f3> a4
                     c3 0f 1f 80 00 00 00 00 48 89 f8 48 83 fa 20
                     72 7e 40 38 fe
[ 5590.803054] RSP: 0018:ffffc90003a8fdf0 EFLAGS: 00010282
[ 5590.803057] RAX: ffff888107ee9000 RBX: ffff888108cb1a00
               RCX: 0000000000000f8f
[ 5590.803061] RDX: 0000000000001000 RSI: ffffffffa0b0e000
               RDI: ffff888107ee9071
[ 5590.803065] RBP: 0000000000000000 R08: 0000000000000001
               R09: 0000000000000001
[ 5590.803069] R10: 0000000000000001 R11: 0000000000000002
               R12: 0000000000000019
[ 5590.803073] R13: 0000000000174fff R14: 0000000000001000
               R15: ffff888107ee9000
[ 5590.803077] FS: 00007f62a99bee80(0000) GS:ffff88849f880000(0000)
               knlGS:0000000000000000
[ 5590.803082] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 5590.803085] CR2: ffffffffa0b0e000 CR3: 000000010a1a8004
               CR4: 0000000000770ee0
[ 5590.803089] PKRU: 55555554
[ 5590.803091] Call Trace:
[ 5590.803093] <TASK>
[ 5590.803096] error_state_read+0xa1/0xd0 [i915]
[ 5590.803175] kernfs_fop_read_iter+0xb2/0x1b0
[ 5590.803180] new_sync_read+0x116/0x1a0
[ 5590.803185] vfs_read+0x114/0x1b0
[ 5590.803189] ksys_read+0x63/0xe0
[ 5590.803193] do_syscall_64+0x38/0xc0
[ 5590.803197] entry_SYSCALL_64_after_hwframe+0x44/0xae
[ 5590.803201] RIP: 0033:0x7f62aaea5912
[ 5590.803204] Code: c0 e9 b2 fe ff ff 50 48 8d 3d 5a b9 0c 00 e8 05
                     19 02 00 0f 1f 44 00 00 f3 0f 1e fa 64 8b 04 25
                     18 00 00 00 85 c0 75 10 0f 05 <48> 3d 00 f0 ff
                     ff 77 56 c3 0f 1f 44 00 00 48 83 ec 28 48 89 54 24
[ 5590.803213] RSP: 002b:00007fff5b659ae8 EFLAGS: 00000246
               ORIG_RAX: 0000000000000000
[ 5590.803218] RAX: ffffffffffffffda RBX: 0000000000100000
               RCX: 00007f62aaea5912
[ 5590.803221] RDX: 000000000008b000 RSI: 00007f62a8c4000f
               RDI: 0000000000000006
[ 5590.803225] RBP: 00007f62a8bcb00f R08: 0000000000200010
               R09: 0000000000101000
[ 5590.803229] R10: 0000000000000001 R11: 0000000000000246
               R12: 0000000000000006
[ 5590.803233] R13: 0000000000075000 R14: 00007f62a8acb010
               R15: 0000000000200000
[ 5590.803238] </TASK>
[ 5590.803240] Modules linked in: i915 ttm drm_buddy drm_dp_helper
                        drm_kms_helper syscopyarea sysfillrect sysimgblt
                        fb_sys_fops prime_numbers nfnetlink br_netfilter
                        overlay mei_pxp mei_hdcp x86_pkg_temp_thermal
                        coretemp kvm_intel snd_hda_codec_hdmi snd_hda_intel
                        snd_intel_dspcfg snd_hda_codec snd_hwdep
                        snd_hda_core snd_pcm mei_me mei fuse ip_tables
                        x_tables crct10dif_pclmul e1000e crc32_pclmul ptp
                        i2c_i801 ghash_clmulni_intel i2c_smbus pps_core
                        [last unloa ded: ttm]
[ 5590.803277] CR2: ffffffffa0b0e000
[ 5590.803280] ---[ end trace 0000000000000000 ]---

Fixes: 0e39037b3165 ("drm/i915: Cache the error string")
Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220311004311.514198-2-alan.previn.teres.alexis@intel.com
---
 drivers/gpu/drm/i915/i915_sysfs.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 8521daba212a7..a4e3b6dbb231d 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -166,7 +166,14 @@ static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
 	struct device *kdev = kobj_to_dev(kobj);
 	struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
 	struct i915_gpu_coredump *gpu;
-	ssize_t ret;
+	ssize_t ret = 0;
+
+	/*
+	 * FIXME: Concurrent clients triggering resets and reading + clearing
+	 * dumps can cause inconsistent sysfs reads when a user calls in with a
+	 * non-zero offset to complete a prior partial read but the
+	 * gpu_coredump has been cleared or replaced.
+	 */
 
 	gpu = i915_first_error_state(i915);
 	if (IS_ERR(gpu)) {
@@ -178,8 +185,10 @@ static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
 		const char *str = "No error state collected\n";
 		size_t len = strlen(str);
 
-		ret = min_t(size_t, count, len - off);
-		memcpy(buf, str + off, ret);
+		if (off < len) {
+			ret = min_t(size_t, count, len - off);
+			memcpy(buf, str + off, ret);
+		}
 	}
 
 	return ret;
-- 
GitLab


From 26be7cd8aacdd3f0429834e78e3166286779f083 Mon Sep 17 00:00:00 2001
From: Ashutosh Dixit <ashutosh.dixit@intel.com>
Date: Wed, 25 May 2022 06:19:17 -0700
Subject: [PATCH 0089/1731] drm/i915/gt: Add media freq factor to per-gt sysfs

Expose new sysfs to program and retrieve media freq factor. Factor values
of 0 (dynamic), 0.5 and 1.0 are supported via a u8.8 fixed point
representation (corresponding to integer values of 0, 128 and 256
respectively).

Media freq factor is converted to media_ratio_mode for GuC. It is
programmed into GuC using H2G SLPC interface. It is retrieved from GuC
through a register read. A cached media_ratio_mode is maintained to
preserve set values across GuC resets.

This patch adds the following sysfs files to gt/gtN sysfs:
* media_freq_factor
* media_freq_factor.scale

v2: Minor wording change in drm_warn (Tvrtko)

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/7ad7578335d8af9cba047b4bcf33d1887453d2e1.1653484574.git.ashutosh.dixit@intel.com
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h       |   1 +
 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c   | 130 ++++++++++++++++++
 .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h |   6 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c   |  20 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h   |   1 +
 .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h |   3 +
 6 files changed, 161 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 7246eb870c7e3..b4642dcc192fc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -740,6 +740,7 @@
 #define   GEN6_AGGRESSIVE_TURBO			(0 << 15)
 #define   GEN9_SW_REQ_UNSLICE_RATIO_SHIFT	23
 #define   GEN9_IGNORE_SLICE_RATIO		(0 << 0)
+#define   GEN12_MEDIA_FREQ_RATIO		REG_BIT(13)
 
 #define GEN6_RC_VIDEO_FREQ			_MMIO(0xa00c)
 #define   GEN6_RC_CTL_RC6pp_ENABLE		(1 << 16)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index f76b6cf8040ec..081a17f5ca33f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -558,6 +558,128 @@ static const struct attribute *freq_attrs[] = {
 	NULL
 };
 
+/*
+ * Scaling for multipliers (aka frequency factors).
+ * The format of the value in the register is u8.8.
+ *
+ * The presentation to userspace is inspired by the perf event framework.
+ * See:
+ *   Documentation/ABI/testing/sysfs-bus-event_source-devices-events
+ * for description of:
+ *   /sys/bus/event_source/devices/<pmu>/events/<event>.scale
+ *
+ * Summary: Expose two sysfs files for each multiplier.
+ *
+ * 1. File <attr> contains a raw hardware value.
+ * 2. File <attr>.scale contains the multiplicative scale factor to be
+ *    used by userspace to compute the actual value.
+ *
+ * So userspace knows that to get the frequency_factor it multiplies the
+ * provided value by the specified scale factor and vice-versa.
+ *
+ * That way there is no precision loss in the kernel interface and API
+ * is future proof should one day the hardware register change to u16.u16,
+ * on some platform. (Or any other fixed point representation.)
+ *
+ * Example:
+ * File <attr> contains the value 2.5, represented as u8.8 0x0280, which
+ * is comprised of:
+ * - an integer part of 2
+ * - a fractional part of 0x80 (representing 0x80 / 2^8 == 0x80 / 256).
+ * File <attr>.scale contains a string representation of floating point
+ * value 0.00390625 (which is (1 / 256)).
+ * Userspace computes the actual value:
+ *   0x0280 * 0.00390625 -> 2.5
+ * or converts an actual value to the value to be written into <attr>:
+ *   2.5 / 0.00390625 -> 0x0280
+ */
+
+#define U8_8_VAL_MASK           0xffff
+#define U8_8_SCALE_TO_VALUE     "0.00390625"
+
+static ssize_t freq_factor_scale_show(struct device *dev,
+				      struct device_attribute *attr,
+				      char *buff)
+{
+	return sysfs_emit(buff, "%s\n", U8_8_SCALE_TO_VALUE);
+}
+
+static u32 media_ratio_mode_to_factor(u32 mode)
+{
+	/* 0 -> 0, 1 -> 256, 2 -> 128 */
+	return !mode ? mode : 256 / mode;
+}
+
+static ssize_t media_freq_factor_show(struct device *dev,
+				      struct device_attribute *attr,
+				      char *buff)
+{
+	struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+	struct intel_guc_slpc *slpc = &gt->uc.guc.slpc;
+	intel_wakeref_t wakeref;
+	u32 mode;
+
+	/*
+	 * Retrieve media_ratio_mode from GEN6_RPNSWREQ bit 13 set by
+	 * GuC. GEN6_RPNSWREQ:13 value 0 represents 1:2 and 1 represents 1:1
+	 */
+	if (IS_XEHPSDV(gt->i915) &&
+	    slpc->media_ratio_mode == SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL) {
+		/*
+		 * For XEHPSDV dynamic mode GEN6_RPNSWREQ:13 does not contain
+		 * the media_ratio_mode, just return the cached media ratio
+		 */
+		mode = slpc->media_ratio_mode;
+	} else {
+		with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+			mode = intel_uncore_read(gt->uncore, GEN6_RPNSWREQ);
+		mode = REG_FIELD_GET(GEN12_MEDIA_FREQ_RATIO, mode) ?
+			SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE :
+			SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO;
+	}
+
+	return sysfs_emit(buff, "%u\n", media_ratio_mode_to_factor(mode));
+}
+
+static ssize_t media_freq_factor_store(struct device *dev,
+				       struct device_attribute *attr,
+				       const char *buff, size_t count)
+{
+	struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+	struct intel_guc_slpc *slpc = &gt->uc.guc.slpc;
+	u32 factor, mode;
+	int err;
+
+	err = kstrtou32(buff, 0, &factor);
+	if (err)
+		return err;
+
+	for (mode = SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL;
+	     mode <= SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO; mode++)
+		if (factor == media_ratio_mode_to_factor(mode))
+			break;
+
+	if (mode > SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO)
+		return -EINVAL;
+
+	err = intel_guc_slpc_set_media_ratio_mode(slpc, mode);
+	if (!err) {
+		slpc->media_ratio_mode = mode;
+		DRM_DEBUG("Set slpc->media_ratio_mode to %d", mode);
+	}
+	return err ?: count;
+}
+
+static DEVICE_ATTR_RW(media_freq_factor);
+static struct device_attribute dev_attr_media_freq_factor_scale =
+	__ATTR(media_freq_factor.scale, 0444, freq_factor_scale_show, NULL);
+
+static const struct attribute *media_perf_power_attrs[] = {
+	&dev_attr_media_freq_factor.attr,
+	&dev_attr_media_freq_factor_scale.attr,
+	NULL
+};
+
 static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj,
 				const struct attribute * const *attrs)
 {
@@ -599,4 +721,12 @@ void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct kobject *kobj)
 		drm_warn(&gt->i915->drm,
 			 "failed to create gt%u throttle sysfs files (%pe)",
 			 gt->info.id, ERR_PTR(ret));
+
+	if (HAS_MEDIA_RATIO_MODE(gt->i915) && intel_uc_uses_guc_slpc(&gt->uc)) {
+		ret = sysfs_create_files(kobj, media_perf_power_attrs);
+		if (ret)
+			drm_warn(&gt->i915->drm,
+				 "failed to create gt%u media_perf_power_attrs sysfs (%pe)\n",
+				 gt->info.id, ERR_PTR(ret));
+	}
 }
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
index 62cb4254a77af..4c840a2639dc5 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
@@ -122,6 +122,12 @@ enum slpc_param_id {
 	SLPC_MAX_PARAM = 32,
 };
 
+enum slpc_media_ratio_mode {
+	SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL = 0,
+	SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE = 1,
+	SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO = 2,
+};
+
 enum slpc_event_id {
 	SLPC_EVENT_RESET = 0,
 	SLPC_EVENT_SHUTDOWN = 1,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 1db833da42df3..2df31af70d638 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -260,6 +260,7 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
 	slpc->boost_freq = 0;
 	atomic_set(&slpc->num_waiters, 0);
 	slpc->num_boosts = 0;
+	slpc->media_ratio_mode = SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL;
 
 	mutex_init(&slpc->lock);
 	INIT_WORK(&slpc->boost_work, slpc_boost_work);
@@ -506,6 +507,22 @@ int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val)
 	return ret;
 }
 
+int intel_guc_slpc_set_media_ratio_mode(struct intel_guc_slpc *slpc, u32 val)
+{
+	struct drm_i915_private *i915 = slpc_to_i915(slpc);
+	intel_wakeref_t wakeref;
+	int ret = 0;
+
+	if (!HAS_MEDIA_RATIO_MODE(i915))
+		return -ENODEV;
+
+	with_intel_runtime_pm(&i915->runtime_pm, wakeref)
+		ret = slpc_set_param(slpc,
+				     SLPC_PARAM_MEDIA_FF_RATIO_MODE,
+				     val);
+	return ret;
+}
+
 void intel_guc_pm_intrmsk_enable(struct intel_gt *gt)
 {
 	u32 pm_intrmsk_mbz = 0;
@@ -654,6 +671,9 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
 		return ret;
 	}
 
+	/* Set cached media freq ratio mode */
+	intel_guc_slpc_set_media_ratio_mode(slpc, slpc->media_ratio_mode);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
index 0caa8fee3c040..82a98f78f96c3 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
@@ -38,6 +38,7 @@ int intel_guc_slpc_set_boost_freq(struct intel_guc_slpc *slpc, u32 val);
 int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val);
 int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val);
 int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, struct drm_printer *p);
+int intel_guc_slpc_set_media_ratio_mode(struct intel_guc_slpc *slpc, u32 val);
 void intel_guc_pm_intrmsk_enable(struct intel_gt *gt);
 void intel_guc_slpc_boost(struct intel_guc_slpc *slpc);
 void intel_guc_slpc_dec_waiters(struct intel_guc_slpc *slpc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
index bf5b9a563c09e..73d208123528f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
@@ -29,6 +29,9 @@ struct intel_guc_slpc {
 	u32 min_freq_softlimit;
 	u32 max_freq_softlimit;
 
+	/* cached media ratio mode */
+	u32 media_ratio_mode;
+
 	/* Protects set/reset of boost freq
 	 * and value of num_waiters
 	 */
-- 
GitLab


From 6a735552f44d7a29a9e629cdc3b5c3ac2b4021e6 Mon Sep 17 00:00:00 2001
From: Ashutosh Dixit <ashutosh.dixit@intel.com>
Date: Wed, 25 May 2022 06:19:18 -0700
Subject: [PATCH 0090/1731] drm/i915/pcode: Init pcode on different gt's

Extend pcode initialization to pcode on different gt's.

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/4de1e4fd71a2971549c5cfb185412f190f15e235.1653484574.git.ashutosh.dixit@intel.com
---
 drivers/gpu/drm/i915/i915_driver.c | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index b47746152d97f..d26dcca7e654a 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -520,6 +520,22 @@ mask_err:
 	return ret;
 }
 
+static int i915_pcode_init(struct drm_i915_private *i915)
+{
+	struct intel_gt *gt;
+	int id, ret;
+
+	for_each_gt(gt, i915, id) {
+		ret = intel_pcode_init(gt->uncore);
+		if (ret) {
+			drm_err(&gt->i915->drm, "gt%d: intel_pcode_init failed %d\n", id, ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
 /**
  * i915_driver_hw_probe - setup state requiring device access
  * @dev_priv: device private
@@ -629,7 +645,7 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 
 	intel_opregion_setup(dev_priv);
 
-	ret = intel_pcode_init(&dev_priv->uncore);
+	ret = i915_pcode_init(dev_priv);
 	if (ret)
 		goto err_msi;
 
@@ -1251,7 +1267,7 @@ static int i915_drm_resume(struct drm_device *dev)
 
 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
-	ret = intel_pcode_init(&dev_priv->uncore);
+	ret = i915_pcode_init(dev_priv);
 	if (ret)
 		return ret;
 
-- 
GitLab


From 9d15dd1bb3e7de4dd31a225977813dda2748253e Mon Sep 17 00:00:00 2001
From: Dale B Stimson <dale.b.stimson@intel.com>
Date: Wed, 25 May 2022 06:19:19 -0700
Subject: [PATCH 0091/1731] drm/i915/gt: Add media RP0/RPn to per-gt sysfs

Retrieve RP0 and RPn freq for media IP from PCODE and display in per-gt
sysfs. This patch adds the following files to gt/gtN sysfs:
* media_RP0_freq_mhz
* media_RPn_freq_mhz

v2: Fixed commit author (Rodrigo)
v3: Convert to new uncore interface for pcode functions
v4: Adapt to intel_pcode.* function rename
v5: #include "intel_pcode.h" in alphabetical order (Tvrtko)

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/45e34127a79e808f6582db8afb77f2f728a446e6.1653484574.git.ashutosh.dixit@intel.com
---
 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 47 +++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h             |  8 ++++
 2 files changed, 55 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 081a17f5ca33f..ae8a8f725f011 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -14,6 +14,7 @@
 #include "intel_gt_regs.h"
 #include "intel_gt_sysfs.h"
 #include "intel_gt_sysfs_pm.h"
+#include "intel_pcode.h"
 #include "intel_rc6.h"
 #include "intel_rps.h"
 
@@ -670,13 +671,59 @@ static ssize_t media_freq_factor_store(struct device *dev,
 	return err ?: count;
 }
 
+static ssize_t media_RP0_freq_mhz_show(struct device *dev,
+				       struct device_attribute *attr,
+				       char *buff)
+{
+	struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+	u32 val;
+	int err;
+
+	err = snb_pcode_read_p(gt->uncore, XEHPSDV_PCODE_FREQUENCY_CONFIG,
+			       PCODE_MBOX_FC_SC_READ_FUSED_P0,
+			       PCODE_MBOX_DOMAIN_MEDIAFF, &val);
+
+	if (err)
+		return err;
+
+	/* Fused media RP0 read from pcode is in units of 50 MHz */
+	val *= GT_FREQUENCY_MULTIPLIER;
+
+	return sysfs_emit(buff, "%u\n", val);
+}
+
+static ssize_t media_RPn_freq_mhz_show(struct device *dev,
+				       struct device_attribute *attr,
+				       char *buff)
+{
+	struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+	u32 val;
+	int err;
+
+	err = snb_pcode_read_p(gt->uncore, XEHPSDV_PCODE_FREQUENCY_CONFIG,
+			       PCODE_MBOX_FC_SC_READ_FUSED_PN,
+			       PCODE_MBOX_DOMAIN_MEDIAFF, &val);
+
+	if (err)
+		return err;
+
+	/* Fused media RPn read from pcode is in units of 50 MHz */
+	val *= GT_FREQUENCY_MULTIPLIER;
+
+	return sysfs_emit(buff, "%u\n", val);
+}
+
 static DEVICE_ATTR_RW(media_freq_factor);
 static struct device_attribute dev_attr_media_freq_factor_scale =
 	__ATTR(media_freq_factor.scale, 0444, freq_factor_scale_show, NULL);
+static DEVICE_ATTR_RO(media_RP0_freq_mhz);
+static DEVICE_ATTR_RO(media_RPn_freq_mhz);
 
 static const struct attribute *media_perf_power_attrs[] = {
 	&dev_attr_media_freq_factor.attr,
 	&dev_attr_media_freq_factor_scale.attr,
+	&dev_attr_media_RP0_freq_mhz.attr,
+	&dev_attr_media_RPn_freq_mhz.attr,
 	NULL
 };
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d1806dcee668b..213f02d58fc8e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6767,6 +6767,14 @@
 #define     DG1_UNCORE_GET_INIT_STATUS		0x0
 #define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
+#define   XEHPSDV_PCODE_FREQUENCY_CONFIG		0x6e	/* xehpsdv, pvc */
+/* XEHPSDV_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
+#define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
+#define     PCODE_MBOX_FC_SC_READ_FUSED_PN	0x1
+/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
+/*   XEHPSDV_PCODE_FREQUENCY_CONFIG param2 */
+#define     PCODE_MBOX_DOMAIN_NONE		0x0
+#define     PCODE_MBOX_DOMAIN_MEDIAFF		0x3
 #define GEN6_PCODE_DATA				_MMIO(0x138128)
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
-- 
GitLab


From 69d6bf5c3754ffc491896632438417d1cedc2c68 Mon Sep 17 00:00:00 2001
From: Ashutosh Dixit <ashutosh.dixit@intel.com>
Date: Wed, 25 May 2022 06:19:20 -0700
Subject: [PATCH 0092/1731] drm/i915/gt: Fix memory leaks in per-gt sysfs

All kmalloc'd kobjects need a kobject_put() to free memory. For example in
previous code, kobj_gt_release() never gets called. The requirement of
kobject_put() now results in a slightly different code organization.

v2: s/gtn/gt/ (Andi)

Fixes: b770bcfae9ad ("drm/i915/gt: create per-tile sysfs interface")
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Acked-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/a6f6686517c85fba61a0c45097f5bb4fe7e257fb.1653484574.git.ashutosh.dixit@intel.com
---
 drivers/gpu/drm/i915/gt/intel_gt.c       |  1 +
 drivers/gpu/drm/i915/gt/intel_gt_sysfs.c | 29 ++++++++++--------------
 drivers/gpu/drm/i915/gt/intel_gt_sysfs.h |  6 +----
 drivers/gpu/drm/i915/gt/intel_gt_types.h |  3 +++
 drivers/gpu/drm/i915/i915_sysfs.c        |  2 ++
 5 files changed, 19 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 034182f85501b..0a3931c011c62 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -790,6 +790,7 @@ void intel_gt_driver_unregister(struct intel_gt *gt)
 {
 	intel_wakeref_t wakeref;
 
+	intel_gt_sysfs_unregister(gt);
 	intel_rps_driver_unregister(&gt->rps);
 	intel_gsc_fini(&gt->gsc);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
index 8ec8bc660c8c2..9e4ebf53379bc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
@@ -24,7 +24,7 @@ bool is_object_gt(struct kobject *kobj)
 
 static struct intel_gt *kobj_to_gt(struct kobject *kobj)
 {
-	return container_of(kobj, struct kobj_gt, base)->gt;
+	return container_of(kobj, struct intel_gt, sysfs_gt);
 }
 
 struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
@@ -72,9 +72,9 @@ static struct attribute *id_attrs[] = {
 };
 ATTRIBUTE_GROUPS(id);
 
+/* A kobject needs a release() method even if it does nothing */
 static void kobj_gt_release(struct kobject *kobj)
 {
-	kfree(kobj);
 }
 
 static struct kobj_type kobj_gt_type = {
@@ -85,8 +85,6 @@ static struct kobj_type kobj_gt_type = {
 
 void intel_gt_sysfs_register(struct intel_gt *gt)
 {
-	struct kobj_gt *kg;
-
 	/*
 	 * We need to make things right with the
 	 * ABI compatibility. The files were originally
@@ -98,25 +96,22 @@ void intel_gt_sysfs_register(struct intel_gt *gt)
 	if (gt_is_root(gt))
 		intel_gt_sysfs_pm_init(gt, gt_get_parent_obj(gt));
 
-	kg = kzalloc(sizeof(*kg), GFP_KERNEL);
-	if (!kg)
+	/* init and xfer ownership to sysfs tree */
+	if (kobject_init_and_add(&gt->sysfs_gt, &kobj_gt_type,
+				 gt->i915->sysfs_gt, "gt%d", gt->info.id))
 		goto exit_fail;
 
-	kobject_init(&kg->base, &kobj_gt_type);
-	kg->gt = gt;
-
-	/* xfer ownership to sysfs tree */
-	if (kobject_add(&kg->base, gt->i915->sysfs_gt, "gt%d", gt->info.id))
-		goto exit_kobj_put;
-
-	intel_gt_sysfs_pm_init(gt, &kg->base);
+	intel_gt_sysfs_pm_init(gt, &gt->sysfs_gt);
 
 	return;
 
-exit_kobj_put:
-	kobject_put(&kg->base);
-
 exit_fail:
+	kobject_put(&gt->sysfs_gt);
 	drm_warn(&gt->i915->drm,
 		 "failed to initialize gt%d sysfs root\n", gt->info.id);
 }
+
+void intel_gt_sysfs_unregister(struct intel_gt *gt)
+{
+	kobject_put(&gt->sysfs_gt);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
index 9471b26752cfc..a99aa7e8b01a6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
@@ -13,11 +13,6 @@
 
 struct intel_gt;
 
-struct kobj_gt {
-	struct kobject base;
-	struct intel_gt *gt;
-};
-
 bool is_object_gt(struct kobject *kobj);
 
 struct drm_i915_private *kobj_to_i915(struct kobject *kobj);
@@ -28,6 +23,7 @@ intel_gt_create_kobj(struct intel_gt *gt,
 		     const char *name);
 
 void intel_gt_sysfs_register(struct intel_gt *gt);
+void intel_gt_sysfs_unregister(struct intel_gt *gt);
 struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
 					    const char *name);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 097e10291f2d3..993f003dad1dc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -225,6 +225,9 @@ struct intel_gt {
 	} mocs;
 
 	struct intel_pxp pxp;
+
+	/* gt/gtN sysfs */
+	struct kobject sysfs_gt;
 };
 
 enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index a4e3b6dbb231d..1e27502108313 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -268,4 +268,6 @@ void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
 
 	device_remove_bin_file(kdev,  &dpf_attrs_1);
 	device_remove_bin_file(kdev,  &dpf_attrs);
+
+	kobject_put(dev_priv->sysfs_gt);
 }
-- 
GitLab


From 420a07b841d03f6a436d8c06571c69aa5c783897 Mon Sep 17 00:00:00 2001
From: Nirmoy Das <nirmoy.das@intel.com>
Date: Wed, 25 May 2022 11:59:55 +0200
Subject: [PATCH 0093/1731] drm/i915: Individualize fences before adding to
 dma_resv obj

_i915_vma_move_to_active() can receive > 1 fences for
multiple batch buffers submission. Because dma_resv_add_fence()
can only accept one fence at a time, change _i915_vma_move_to_active()
to be aware of multiple fences so that it can add individual
fences to the dma resv object.

v6: fix multi-line comment.
v5: remove double fence reservation for batch VMAs.
v4: Reserve fences for composite_fence on multi-batch contexts and
    also reserve fence slots to composite_fence for each VMAs.
v3: dma_resv_reserve_fences is not cumulative so pass num_fences.
v2: make sure to reserve enough fence slots before adding.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5614
Fixes: 544460c33821 ("drm/i915: Multi-BB execbuf")
Cc: <stable@vger.kernel.org> # v5.16+
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220525095955.15371-1-nirmoy.das@intel.com
---
 .../gpu/drm/i915/gem/i915_gem_execbuffer.c    |  3 +-
 drivers/gpu/drm/i915/i915_vma.c               | 48 +++++++++++--------
 2 files changed, 30 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index c326bd2b444fc..30fe847c6664d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -999,7 +999,8 @@ static int eb_validate_vmas(struct i915_execbuffer *eb)
 			}
 		}
 
-		err = dma_resv_reserve_fences(vma->obj->base.resv, 1);
+		/* Reserve enough slots to accommodate composite fences */
+		err = dma_resv_reserve_fences(vma->obj->base.resv, eb->num_batches);
 		if (err)
 			return err;
 
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 4f6db539571aa..0bffb70b3c5f5 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -23,6 +23,7 @@
  */
 
 #include <linux/sched/mm.h>
+#include <linux/dma-fence-array.h>
 #include <drm/drm_gem.h>
 
 #include "display/intel_frontbuffer.h"
@@ -1823,6 +1824,21 @@ int _i915_vma_move_to_active(struct i915_vma *vma,
 	if (unlikely(err))
 		return err;
 
+	/*
+	 * Reserve fences slot early to prevent an allocation after preparing
+	 * the workload and associating fences with dma_resv.
+	 */
+	if (fence && !(flags & __EXEC_OBJECT_NO_RESERVE)) {
+		struct dma_fence *curr;
+		int idx;
+
+		dma_fence_array_for_each(curr, idx, fence)
+			;
+		err = dma_resv_reserve_fences(vma->obj->base.resv, idx);
+		if (unlikely(err))
+			return err;
+	}
+
 	if (flags & EXEC_OBJECT_WRITE) {
 		struct intel_frontbuffer *front;
 
@@ -1832,31 +1848,23 @@ int _i915_vma_move_to_active(struct i915_vma *vma,
 				i915_active_add_request(&front->write, rq);
 			intel_frontbuffer_put(front);
 		}
+	}
 
-		if (!(flags & __EXEC_OBJECT_NO_RESERVE)) {
-			err = dma_resv_reserve_fences(vma->obj->base.resv, 1);
-			if (unlikely(err))
-				return err;
-		}
+	if (fence) {
+		struct dma_fence *curr;
+		enum dma_resv_usage usage;
+		int idx;
 
-		if (fence) {
-			dma_resv_add_fence(vma->obj->base.resv, fence,
-					   DMA_RESV_USAGE_WRITE);
+		obj->read_domains = 0;
+		if (flags & EXEC_OBJECT_WRITE) {
+			usage = DMA_RESV_USAGE_WRITE;
 			obj->write_domain = I915_GEM_DOMAIN_RENDER;
-			obj->read_domains = 0;
-		}
-	} else {
-		if (!(flags & __EXEC_OBJECT_NO_RESERVE)) {
-			err = dma_resv_reserve_fences(vma->obj->base.resv, 1);
-			if (unlikely(err))
-				return err;
+		} else {
+			usage = DMA_RESV_USAGE_READ;
 		}
 
-		if (fence) {
-			dma_resv_add_fence(vma->obj->base.resv, fence,
-					   DMA_RESV_USAGE_READ);
-			obj->write_domain = 0;
-		}
+		dma_fence_array_for_each(curr, idx, fence)
+			dma_resv_add_fence(vma->obj->base.resv, curr, usage);
 	}
 
 	if (flags & EXEC_OBJECT_NEEDS_FENCE && vma->fence)
-- 
GitLab


From 4fde3f5d8805caba40cce2268c540d8a37403c6b Mon Sep 17 00:00:00 2001
From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Date: Thu, 26 May 2022 12:19:35 +0530
Subject: [PATCH 0094/1731] drm/i915/display/adl_p: Updates to HDMI combo PHY
 voltage swing table

New updates to HDMI combo PHY voltage swing tables. Actually with this
update (bspec updated on 08/17/2021), the values are reverted back to be
same as icelake for HDMI combo PHY.

Bspec: 49291
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220526064935.969225-1-balasubramani.vivekanandan@intel.com
---
 .../drm/i915/display/intel_ddi_buf_trans.c    | 22 +------------------
 1 file changed, 1 insertion(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 85f58dd3df722..5cae1d19bcbb6 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -878,26 +878,6 @@ static const struct intel_ddi_buf_trans adls_combo_phy_trans_edp_hbr3 = {
 	.num_entries = ARRAY_SIZE(_adls_combo_phy_trans_edp_hbr3),
 };
 
-static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_hdmi[] = {
-							/* NT mV Trans mV    db   */
-	{ .icl = { 0x6, 0x60, 0x3F, 0x00, 0x00 } },	/*  400    400      0.0 */
-	{ .icl = { 0x6, 0x68, 0x3F, 0x00, 0x00 } },	/*  500    500      0.0 */
-	{ .icl = { 0xA, 0x73, 0x3F, 0x00, 0x00 } },	/*  650    650      0.0 ALS */
-	{ .icl = { 0xA, 0x78, 0x3F, 0x00, 0x00 } },	/*  800    800      0.0 */
-	{ .icl = { 0xB, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1000   1000      0.0 Re-timer */
-	{ .icl = { 0xB, 0x7F, 0x3B, 0x00, 0x04 } },	/* Full    Red     -1.5 */
-	{ .icl = { 0xB, 0x7F, 0x39, 0x00, 0x06 } },	/* Full    Red     -1.8 */
-	{ .icl = { 0xB, 0x7F, 0x37, 0x00, 0x08 } },	/* Full    Red     -2.0 CRLS */
-	{ .icl = { 0xB, 0x7F, 0x35, 0x00, 0x0A } },	/* Full    Red     -2.5 */
-	{ .icl = { 0xB, 0x7F, 0x33, 0x00, 0x0C } },	/* Full    Red     -3.0 */
-};
-
-static const struct intel_ddi_buf_trans adlp_combo_phy_trans_hdmi = {
-	.entries = _adlp_combo_phy_trans_hdmi,
-	.num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_hdmi),
-	.hdmi_default_entry = ARRAY_SIZE(_adlp_combo_phy_trans_hdmi) - 1,
-};
-
 static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_dp_hbr[] = {
 							/* NT mV Trans mV db    */
 	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
@@ -1556,7 +1536,7 @@ adlp_get_combo_buf_trans(struct intel_encoder *encoder,
 			 int *n_entries)
 {
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
-		return intel_get_buf_trans(&adlp_combo_phy_trans_hdmi, n_entries);
+		return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 		return adlp_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
 	else
-- 
GitLab


From 51ab3b85000d214b75899875d5745935e06020e5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 10 May 2022 13:42:28 +0300
Subject: [PATCH 0095/1731] drm/i915: Pass intel_connector to
 intel_vrr_is_capable()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Pass intel_connector instead of drm_connector to
intel_vrr_is_capable(). Will result in less ugly casts.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-2-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_vrr.c | 14 +++++++-------
 drivers/gpu/drm/i915/display/intel_vrr.h |  4 ++--
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d55acc4a028a8..0deba9debe6da 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4523,7 +4523,7 @@ intel_dp_set_edid(struct intel_dp *intel_dp)
 	edid = intel_dp_get_edid(intel_dp);
 	connector->detect_edid = edid;
 
-	vrr_capable = intel_vrr_is_capable(&connector->base);
+	vrr_capable = intel_vrr_is_capable(connector);
 	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
 		    connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
 	drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 396f2f994fa07..081e52dd6c4e2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -9,17 +9,17 @@
 #include "intel_display_types.h"
 #include "intel_vrr.h"
 
-bool intel_vrr_is_capable(struct drm_connector *connector)
+bool intel_vrr_is_capable(struct intel_connector *connector)
 {
+	const struct drm_display_info *info = &connector->base.display_info;
+	struct drm_i915_private *i915 = to_i915(connector->base.dev);
 	struct intel_dp *intel_dp;
-	const struct drm_display_info *info = &connector->display_info;
-	struct drm_i915_private *i915 = to_i915(connector->dev);
 
-	if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
-	    connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
+	if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP &&
+	    connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 		return false;
 
-	intel_dp = intel_attached_dp(to_intel_connector(connector));
+	intel_dp = intel_attached_dp(connector);
 	/*
 	 * DP Sink is capable of VRR video timings if
 	 * Ignore MSA bit is set in DPCD.
@@ -97,7 +97,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 	const struct drm_display_info *info = &connector->base.display_info;
 	int vmin, vmax;
 
-	if (!intel_vrr_is_capable(&connector->base))
+	if (!intel_vrr_is_capable(connector))
 		return;
 
 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 1c2da572693d2..9fda1135b0dd5 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -8,15 +8,15 @@
 
 #include <linux/types.h>
 
-struct drm_connector;
 struct drm_connector_state;
 struct intel_atomic_state;
+struct intel_connector;
 struct intel_crtc;
 struct intel_crtc_state;
 struct intel_dp;
 struct intel_encoder;
 
-bool intel_vrr_is_capable(struct drm_connector *connector);
+bool intel_vrr_is_capable(struct intel_connector *connector);
 void intel_vrr_check_modeset(struct intel_atomic_state *state);
 void intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 			      struct drm_connector_state *conn_state);
-- 
GitLab


From 822e5ae701af2964c5808b6ade1d6f3b1eaec967 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 10 May 2022 13:42:29 +0300
Subject: [PATCH 0096/1731] drm/i915: Extract intel_edp_fixup_vbt_bpp()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

We have the same "override eDP VBT bpp with the current bpp" code
duplciated in two places. Extract it to a helper function.

TODO: Having this in .get_config() is pretty ugly. Should probably
try to move it somewhere else (setup_hw_state()/etc.)...

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-3-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/g4x_dp.c    | 22 ++-------------------
 drivers/gpu/drm/i915/display/intel_ddi.c | 22 ++-------------------
 drivers/gpu/drm/i915/display/intel_dp.c  | 25 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h  |  1 +
 4 files changed, 30 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 5a957acebfd62..82ad8fe7440c0 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -395,26 +395,8 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
 		intel_dotclock_calculate(pipe_config->port_clock,
 					 &pipe_config->dp_m_n);
 
-	if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
-	    pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
-		/*
-		 * This is a big fat ugly hack.
-		 *
-		 * Some machines in UEFI boot mode provide us a VBT that has 18
-		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
-		 * unknown we fail to light up. Yet the same BIOS boots up with
-		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
-		 * max, not what it tells us to use.
-		 *
-		 * Note: This will still be broken if the eDP panel is not lit
-		 * up by the BIOS, and thus we can't get the mode at module
-		 * load.
-		 */
-		drm_dbg_kms(&dev_priv->drm,
-			    "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
-			    pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
-		dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
-	}
+	if (intel_dp_is_edp(intel_dp))
+		intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d9f238edf547f..14547d6a63a6d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3433,26 +3433,8 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
 	pipe_config->has_audio =
 		intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
 
-	if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
-	    pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
-		/*
-		 * This is a big fat ugly hack.
-		 *
-		 * Some machines in UEFI boot mode provide us a VBT that has 18
-		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
-		 * unknown we fail to light up. Yet the same BIOS boots up with
-		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
-		 * max, not what it tells us to use.
-		 *
-		 * Note: This will still be broken if the eDP panel is not lit
-		 * up by the BIOS, and thus we can't get the mode at module
-		 * load.
-		 */
-		drm_dbg_kms(&dev_priv->drm,
-			    "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
-			    pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
-		dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
-	}
+	if (encoder->type == INTEL_OUTPUT_EDP)
+		intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp);
 
 	ddi_dotclock_get(pipe_config);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0deba9debe6da..688bf3ae92e7e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2709,6 +2709,31 @@ static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
 		    DRM_MODE_ARG(mode));
 }
 
+void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+	if (dev_priv->vbt.edp.bpp && pipe_bpp > dev_priv->vbt.edp.bpp) {
+		/*
+		 * This is a big fat ugly hack.
+		 *
+		 * Some machines in UEFI boot mode provide us a VBT that has 18
+		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
+		 * unknown we fail to light up. Yet the same BIOS boots up with
+		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
+		 * max, not what it tells us to use.
+		 *
+		 * Note: This will still be broken if the eDP panel is not lit
+		 * up by the BIOS, and thus we can't get the mode at module
+		 * load.
+		 */
+		drm_dbg_kms(&dev_priv->drm,
+			    "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
+			    pipe_bpp, dev_priv->vbt.edp.bpp);
+		dev_priv->vbt.edp.bpp = pipe_bpp;
+	}
+}
+
 static void intel_edp_mso_init(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index d457e17bdc57e..e794d910df564 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -63,6 +63,7 @@ enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
 			    const struct drm_connector_state *conn_state);
 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
+void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
-- 
GitLab


From 75bd0d5e4eadb9ce3e9b6fb71971b6e87c38799e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 10 May 2022 13:42:30 +0300
Subject: [PATCH 0097/1731] drm/i915/pps: Split pps_init_delays() into distinct
 parts
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Split each of the hw/vbt/spec PPS delay initialization into
separate functions to make the whole thing less cluttered.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_pps.c | 66 +++++++++++++++++-------
 1 file changed, 48 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 4bc0563dde92f..bc56f0fe8e6d5 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1159,53 +1159,83 @@ intel_pps_verify_state(struct intel_dp *intel_dp)
 	}
 }
 
-static void pps_init_delays(struct intel_dp *intel_dp)
+static void pps_init_delays_cur(struct intel_dp *intel_dp,
+				struct edp_power_seq *cur)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	struct edp_power_seq cur, vbt, spec,
-		*final = &intel_dp->pps.pps_delays;
 
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
-	/* already initialized? */
-	if (final->t11_t12 != 0)
-		return;
+	intel_pps_readout_hw_state(intel_dp, cur);
+
+	intel_pps_dump_state(intel_dp, "cur", cur);
+}
 
-	intel_pps_readout_hw_state(intel_dp, &cur);
+static void pps_init_delays_vbt(struct intel_dp *intel_dp,
+				struct edp_power_seq *vbt)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
-	intel_pps_dump_state(intel_dp, "cur", &cur);
+	*vbt = dev_priv->vbt.edp.pps;
 
-	vbt = dev_priv->vbt.edp.pps;
 	/* On Toshiba Satellite P50-C-18C system the VBT T12 delay
 	 * of 500ms appears to be too short. Ocassionally the panel
 	 * just fails to power back on. Increasing the delay to 800ms
 	 * seems sufficient to avoid this problem.
 	 */
 	if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
-		vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
+		vbt->t11_t12 = max_t(u16, vbt->t11_t12, 1300 * 10);
 		drm_dbg_kms(&dev_priv->drm,
 			    "Increasing T12 panel delay as per the quirk to %d\n",
-			    vbt.t11_t12);
+			    vbt->t11_t12);
 	}
+
 	/* T11_T12 delay is special and actually in units of 100ms, but zero
 	 * based in the hw (so we need to add 100 ms). But the sw vbt
 	 * table multiplies it with 1000 to make it in units of 100usec,
 	 * too. */
-	vbt.t11_t12 += 100 * 10;
+	vbt->t11_t12 += 100 * 10;
+
+	intel_pps_dump_state(intel_dp, "vbt", vbt);
+}
+
+static void pps_init_delays_spec(struct intel_dp *intel_dp,
+				 struct edp_power_seq *spec)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+	lockdep_assert_held(&dev_priv->pps_mutex);
 
 	/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
 	 * our hw here, which are all in 100usec. */
-	spec.t1_t3 = 210 * 10;
-	spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
-	spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
-	spec.t10 = 500 * 10;
+	spec->t1_t3 = 210 * 10;
+	spec->t8 = 50 * 10; /* no limit for t8, use t7 instead */
+	spec->t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
+	spec->t10 = 500 * 10;
 	/* This one is special and actually in units of 100ms, but zero
 	 * based in the hw (so we need to add 100 ms). But the sw vbt
 	 * table multiplies it with 1000 to make it in units of 100usec,
 	 * too. */
-	spec.t11_t12 = (510 + 100) * 10;
+	spec->t11_t12 = (510 + 100) * 10;
+
+	intel_pps_dump_state(intel_dp, "spec", spec);
+}
+
+static void pps_init_delays(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	struct edp_power_seq cur, vbt, spec,
+		*final = &intel_dp->pps.pps_delays;
+
+	lockdep_assert_held(&dev_priv->pps_mutex);
+
+	/* already initialized? */
+	if (final->t11_t12 != 0)
+		return;
 
-	intel_pps_dump_state(intel_dp, "vbt", &vbt);
+	pps_init_delays_cur(intel_dp, &cur);
+	pps_init_delays_vbt(intel_dp, &vbt);
+	pps_init_delays_spec(intel_dp, &spec);
 
 	/* Use the max of the register settings and vbt. If both are
 	 * unset, fall back to the spec limits. */
-- 
GitLab


From 60b02a09598f87972a15bb181b9a62b8a8ee682a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 10 May 2022 13:42:31 +0300
Subject: [PATCH 0098/1731] drm/i915/pps: Introduce pps_delays_valid()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add a small helper that determines if the PPS delays have been
initialized or not.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_pps.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index bc56f0fe8e6d5..2ef6502703c29 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1159,6 +1159,12 @@ intel_pps_verify_state(struct intel_dp *intel_dp)
 	}
 }
 
+static bool pps_delays_valid(struct edp_power_seq *delays)
+{
+	return delays->t1_t3 || delays->t8 || delays->t9 ||
+		delays->t10 || delays->t11_t12;
+}
+
 static void pps_init_delays_cur(struct intel_dp *intel_dp,
 				struct edp_power_seq *cur)
 {
@@ -1230,7 +1236,7 @@ static void pps_init_delays(struct intel_dp *intel_dp)
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
 	/* already initialized? */
-	if (final->t11_t12 != 0)
+	if (pps_delays_valid(final))
 		return;
 
 	pps_init_delays_cur(intel_dp, &cur);
-- 
GitLab


From 89fcdf4305996f869eb39eb8f14a989e9a289611 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 10 May 2022 13:42:32 +0300
Subject: [PATCH 0099/1731] drm/i915/pps: Don't apply quirks/etc. to the VBT
 PPS delays if they haven't been initialized
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Skip QUIRK_INCREASE_T12_DELAY and the t11_t12 adjustment of the
VBT PPS delays if we've not yet initialized them. Will be important
later when the PPS delay init can happen before VBT parsing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-6-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_pps.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 2ef6502703c29..80f8edb0d36d3 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1184,6 +1184,9 @@ static void pps_init_delays_vbt(struct intel_dp *intel_dp,
 
 	*vbt = dev_priv->vbt.edp.pps;
 
+	if (!pps_delays_valid(vbt))
+		return;
+
 	/* On Toshiba Satellite P50-C-18C system the VBT T12 delay
 	 * of 500ms appears to be too short. Ocassionally the panel
 	 * just fails to power back on. Increasing the delay to 800ms
-- 
GitLab


From 586294c3c1860ac991d3a241159c0edf974b68e4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 10 May 2022 13:42:33 +0300
Subject: [PATCH 0100/1731] drm/i915/pps: Stash away original BIOS programmed
 PPS delays
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

In order to do the panel VBT parsing after the EDID read
(needed to determine panel_type from PNPID) we need to stash
away the original BIOS programmed PPS delays so that we
can consult them again when we reinit the PPS delays after
the VBT parsing has been done.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-7-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h |  1 +
 drivers/gpu/drm/i915/display/intel_pps.c           | 13 ++++++++-----
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index cfd042117b109..2e9fe2b93d181 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1496,6 +1496,7 @@ struct intel_pps {
 	 */
 	bool pps_reset;
 	struct edp_power_seq pps_delays;
+	struct edp_power_seq bios_pps_delays;
 };
 
 struct intel_psr {
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 80f8edb0d36d3..f85dbd47eb609 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1165,16 +1165,19 @@ static bool pps_delays_valid(struct edp_power_seq *delays)
 		delays->t10 || delays->t11_t12;
 }
 
-static void pps_init_delays_cur(struct intel_dp *intel_dp,
-				struct edp_power_seq *cur)
+static void pps_init_delays_bios(struct intel_dp *intel_dp,
+				 struct edp_power_seq *bios)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
-	intel_pps_readout_hw_state(intel_dp, cur);
+	if (!pps_delays_valid(&intel_dp->pps.bios_pps_delays))
+		intel_pps_readout_hw_state(intel_dp, &intel_dp->pps.bios_pps_delays);
 
-	intel_pps_dump_state(intel_dp, "cur", cur);
+	*bios = intel_dp->pps.bios_pps_delays;
+
+	intel_pps_dump_state(intel_dp, "bios", bios);
 }
 
 static void pps_init_delays_vbt(struct intel_dp *intel_dp,
@@ -1242,7 +1245,7 @@ static void pps_init_delays(struct intel_dp *intel_dp)
 	if (pps_delays_valid(final))
 		return;
 
-	pps_init_delays_cur(intel_dp, &cur);
+	pps_init_delays_bios(intel_dp, &cur);
 	pps_init_delays_vbt(intel_dp, &vbt);
 	pps_init_delays_spec(intel_dp, &spec);
 
-- 
GitLab


From 8e75e8f573e1ff4a0c93c3be1554d2bfd5ae6029 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 10 May 2022 13:42:34 +0300
Subject: [PATCH 0101/1731] drm/i915/pps: Split PPS init+sanitize in two
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Split the PPS init to something we do at the start of the eDP
probe and a second part we do at the end.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-8-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c  |  2 ++
 drivers/gpu/drm/i915/display/intel_pps.c | 30 ++++++++++++++++++++----
 drivers/gpu/drm/i915/display/intel_pps.h |  1 +
 3 files changed, 28 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 688bf3ae92e7e..6580af399cc7f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5252,6 +5252,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 
 	intel_edp_add_properties(intel_dp);
 
+	intel_pps_init_late(intel_dp);
+
 	return true;
 
 out_vdd_off:
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index f85dbd47eb609..b8053897dc68e 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1051,7 +1051,7 @@ void vlv_pps_init(struct intel_encoder *encoder,
 	pps_init_registers(intel_dp, true);
 }
 
-static void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
+static void pps_vdd_init(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -1072,8 +1072,6 @@ static void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
 	drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);
 	intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
 							    intel_aux_power_domain(dig_port));
-
-	edp_panel_vdd_schedule_off(intel_dp);
 }
 
 bool intel_pps_have_panel_power_or_vdd(struct intel_dp *intel_dp)
@@ -1409,18 +1407,40 @@ void intel_pps_encoder_reset(struct intel_dp *intel_dp)
 
 		pps_init_delays(intel_dp);
 		pps_init_registers(intel_dp, false);
+		pps_vdd_init(intel_dp);
 
-		intel_pps_vdd_sanitize(intel_dp);
+		if (edp_have_panel_vdd(intel_dp))
+			edp_panel_vdd_schedule_off(intel_dp);
 	}
 }
 
 void intel_pps_init(struct intel_dp *intel_dp)
 {
+	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	intel_wakeref_t wakeref;
+
 	INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
 
 	pps_init_timestamps(intel_dp);
 
-	intel_pps_encoder_reset(intel_dp);
+	with_intel_pps_lock(intel_dp, wakeref) {
+		if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+			vlv_initial_power_sequencer_setup(intel_dp);
+
+		pps_init_delays(intel_dp);
+		pps_init_registers(intel_dp, false);
+		pps_vdd_init(intel_dp);
+	}
+}
+
+void intel_pps_init_late(struct intel_dp *intel_dp)
+{
+	intel_wakeref_t wakeref;
+
+	with_intel_pps_lock(intel_dp, wakeref) {
+		if (edp_have_panel_vdd(intel_dp))
+			edp_panel_vdd_schedule_off(intel_dp);
+	}
 }
 
 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
index e64144659d31f..a3a56f903f26d 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -41,6 +41,7 @@ bool intel_pps_have_panel_power_or_vdd(struct intel_dp *intel_dp);
 void intel_pps_wait_power_cycle(struct intel_dp *intel_dp);
 
 void intel_pps_init(struct intel_dp *intel_dp);
+void intel_pps_init_late(struct intel_dp *intel_dp);
 void intel_pps_encoder_reset(struct intel_dp *intel_dp);
 void intel_pps_reset_all(struct drm_i915_private *i915);
 
-- 
GitLab


From 67090801489d0a4c80c121494b749e1e97573447 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 10 May 2022 13:42:35 +0300
Subject: [PATCH 0102/1731] drm/i915/pps: Reinit PPS delays after VBT has been
 fully parsed
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

During the eDP probe we may not yet know the panel_type used
to index the VBT panel tables. So the initial eDP probe will have
to be done without that, and thus we won't yet have the PPS delays
from the VBT. Once the VBT has been fully parse we should reinit
the PPS delays to make sure it's fully accounted for.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-9-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_pps.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index b8053897dc68e..bcc70a329ecf9 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1438,6 +1438,11 @@ void intel_pps_init_late(struct intel_dp *intel_dp)
 	intel_wakeref_t wakeref;
 
 	with_intel_pps_lock(intel_dp, wakeref) {
+		/* Reinit delays after per-panel info has been parsed from VBT */
+		memset(&intel_dp->pps.pps_delays, 0, sizeof(intel_dp->pps.pps_delays));
+		pps_init_delays(intel_dp);
+		pps_init_registers(intel_dp, false);
+
 		if (edp_have_panel_vdd(intel_dp))
 			edp_panel_vdd_schedule_off(intel_dp);
 	}
-- 
GitLab


From 50759c13735dab06805eff0e8161d33216d6f5a3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 10 May 2022 13:42:36 +0300
Subject: [PATCH 0103/1731] drm/i915/pps: Keep VDD enabled during eDP probe
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Disable the delayed VDD off work during the eDP probe.
If we never turn off the VDD then we can't violate the
panel's power sequencing delays despite not having read
them out yet from the VBT.

This is mostly a belt+suspenders type of thing since the
the timeout we'd use for the delayed work should be long
enough that this won't normally happen. But I don't really
like relying on timeouts for correctless so might as well
make sure.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-10-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h |  1 +
 drivers/gpu/drm/i915/display/intel_pps.c           | 10 ++++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 2e9fe2b93d181..95d1cbfe37123 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1474,6 +1474,7 @@ struct intel_pps {
 	int backlight_off_delay;
 	struct delayed_work panel_vdd_work;
 	bool want_panel_vdd;
+	bool initializing;
 	unsigned long last_power_on;
 	unsigned long last_backlight_off;
 	ktime_t panel_power_off_time;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index bcc70a329ecf9..e6f701e411e0d 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -722,6 +722,13 @@ static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
 {
 	unsigned long delay;
 
+	/*
+	 * We may not yet know the real power sequencing delays,
+	 * so keep VDD enabled until we're done with init.
+	 */
+	if (intel_dp->pps.initializing)
+		return;
+
 	/*
 	 * Queue the timer to fire a long time from now (relative to the power
 	 * down delay) to keep the panel power up across a sequence of
@@ -1419,6 +1426,7 @@ void intel_pps_init(struct intel_dp *intel_dp)
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 	intel_wakeref_t wakeref;
 
+	intel_dp->pps.initializing = true;
 	INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
 
 	pps_init_timestamps(intel_dp);
@@ -1443,6 +1451,8 @@ void intel_pps_init_late(struct intel_dp *intel_dp)
 		pps_init_delays(intel_dp);
 		pps_init_registers(intel_dp, false);
 
+		intel_dp->pps.initializing = false;
+
 		if (edp_have_panel_vdd(intel_dp))
 			edp_panel_vdd_schedule_off(intel_dp);
 	}
-- 
GitLab


From c3fbcf60bc74b630967f291f47f0d9d0de6fcea7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 10 May 2022 13:42:37 +0300
Subject: [PATCH 0104/1731] drm/i915/bios: Split parse_driver_features() into
 two parts
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

We use the "driver features" block for two different kinds
of data: global data, and per panel data. Split the function
into two parts along that line so that we can start doing the
parsing in two different locations.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-11-ville.syrjala@linux.intel.com
---
 drivers/gpu/drm/i915/display/intel_bios.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index befd579f6006e..3de20d18eae86 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1180,6 +1180,16 @@ parse_driver_features(struct drm_i915_private *i915)
 		    driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS)
 			i915->vbt.int_lvds_support = 0;
 	}
+}
+
+static void
+parse_panel_driver_features(struct drm_i915_private *i915)
+{
+	const struct bdb_driver_features *driver;
+
+	driver = find_section(i915, BDB_DRIVER_FEATURES);
+	if (!driver)
+		return;
 
 	if (i915->vbt.version < 228) {
 		drm_dbg_kms(&i915->drm, "DRRS State Enabled:%d\n",
@@ -2957,6 +2967,7 @@ void intel_bios_init(struct drm_i915_private *i915)
 	parse_lfp_backlight(i915);
 	parse_sdvo_panel_data(i915);
 	parse_driver_features(i915);
+	parse_panel_driver_features(i915);
 	parse_power_conservation_features(i915);
 	parse_edp(i915);
 	parse_psr(i915);
-- 
GitLab


From c2fdb424d32204faf5be29d55f0086b611c94e38 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 10 May 2022 13:42:38 +0300
Subject: [PATCH 0105/1731] drm/i915/bios: Split VBT parsing to global vs.
 panel specific parts
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Parsing the panel specific data (anything that depends on panel_type)
from VBT is currently happening too early. Split the whole thing
into global vs. panel specific parts so that we can start doing
the panel specific parsing at a later time.

v2: Clarify that this is about panel_type (Jani)
    Split out the leak checks (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-12-ville.syrjala@linux.intel.com
---
 drivers/gpu/drm/i915/display/intel_bios.c    | 26 +++++++++++---------
 drivers/gpu/drm/i915/display/intel_bios.h    |  1 +
 drivers/gpu/drm/i915/display/intel_display.c |  1 +
 3 files changed, 17 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 3de20d18eae86..cc64119b52e69 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2961,18 +2961,7 @@ void intel_bios_init(struct drm_i915_private *i915)
 	/* Grab useful general definitions */
 	parse_general_features(i915);
 	parse_general_definitions(i915);
-	parse_panel_options(i915);
-	parse_generic_dtd(i915);
-	parse_lfp_data(i915);
-	parse_lfp_backlight(i915);
-	parse_sdvo_panel_data(i915);
 	parse_driver_features(i915);
-	parse_panel_driver_features(i915);
-	parse_power_conservation_features(i915);
-	parse_edp(i915);
-	parse_psr(i915);
-	parse_mipi_config(i915);
-	parse_mipi_sequence(i915);
 
 	/* Depends on child device list */
 	parse_compression_parameters(i915);
@@ -2991,6 +2980,21 @@ out:
 	kfree(oprom_vbt);
 }
 
+void intel_bios_init_panel(struct drm_i915_private *i915)
+{
+	parse_panel_options(i915);
+	parse_generic_dtd(i915);
+	parse_lfp_data(i915);
+	parse_lfp_backlight(i915);
+	parse_sdvo_panel_data(i915);
+	parse_panel_driver_features(i915);
+	parse_power_conservation_features(i915);
+	parse_edp(i915);
+	parse_psr(i915);
+	parse_mipi_config(i915);
+	parse_mipi_sequence(i915);
+}
+
 /**
  * intel_bios_driver_remove - Free any resources allocated by intel_bios_init()
  * @i915: i915 device instance
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index 4709c4d298059..c744d75fa435f 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -230,6 +230,7 @@ struct mipi_pps_data {
 } __packed;
 
 void intel_bios_init(struct drm_i915_private *dev_priv);
+void intel_bios_init_panel(struct drm_i915_private *dev_priv);
 void intel_bios_driver_remove(struct drm_i915_private *dev_priv);
 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9f105250f4749..7ad93afcc50c2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9580,6 +9580,7 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
 	}
 
 	intel_bios_init(i915);
+	intel_bios_init_panel(i915);
 
 	ret = intel_vga_register(i915);
 	if (ret)
-- 
GitLab


From 3cf050762534cc268a02793ec00240f81c6e2229 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 10 May 2022 13:42:39 +0300
Subject: [PATCH 0106/1731] drm/i915/bios: Split VBT data into per-panel vs.
 global parts
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Move the panel specific VBT parsing to happen during the
output probing stage. Needs to be done because the VBT
parsing will need to look at the EDID to determine
the correct panel_type on some machines.

We split the parsed VBT data (i915->vbt) along the same
boundary. For the moment we just hoist all the panel
specific stuff into connector->panel.vbt since that seems
like the most convenient place for eg. the backlight code.

Note that we simply drop the drrs type check from
intel_drrs_frontbuffer_update() since that operates on the whole
device rather than a specific connector/encoder. But the check
was just a micro optimization so removing it doesn't actually
mattter for correctness.

TODO: Lot's of cleanup to be done in the future. Eg. most of
the DSI stuff could probably be eliminated entirely and just
parsed on demand during DSI init.

v2: Note the intel_drrs_frontbuffer_update() change

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-13-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c        |  11 +-
 .../gpu/drm/i915/display/intel_backlight.c    |  23 +-
 drivers/gpu/drm/i915/display/intel_bios.c     | 371 ++++++++++--------
 drivers/gpu/drm/i915/display/intel_bios.h     |   5 +-
 .../drm/i915/display/intel_ddi_buf_trans.c    |   9 +-
 drivers/gpu/drm/i915/display/intel_display.c  |   1 -
 .../drm/i915/display/intel_display_types.h    |  69 ++++
 drivers/gpu/drm/i915/display/intel_dp.c       |  21 +-
 drivers/gpu/drm/i915/display/intel_dp.h       |   1 +
 .../drm/i915/display/intel_dp_aux_backlight.c |   6 +-
 drivers/gpu/drm/i915/display/intel_drrs.c     |   3 -
 drivers/gpu/drm/i915/display/intel_dsi.c      |   2 +-
 .../i915/display/intel_dsi_dcs_backlight.c    |   9 +-
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c  |  56 +--
 drivers/gpu/drm/i915/display/intel_lvds.c     |   6 +-
 drivers/gpu/drm/i915/display/intel_panel.c    |  13 +-
 drivers/gpu/drm/i915/display/intel_pps.c      |   6 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |  30 +-
 drivers/gpu/drm/i915/display/intel_sdvo.c     |   3 +
 drivers/gpu/drm/i915/display/vlv_dsi.c        |  14 +-
 drivers/gpu/drm/i915/i915_drv.h               |  63 ---
 21 files changed, 391 insertions(+), 331 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index d29211b9807c3..825727dc0a272 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1861,7 +1861,8 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
 {
 	struct drm_device *dev = intel_dsi->base.base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
+	struct intel_connector *connector = intel_dsi->attached_connector;
+	struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
 	u32 tlpx_ns;
 	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
 	u32 ths_prepare_ns, tclk_trail_ns;
@@ -2048,6 +2049,8 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 	/* attach connector to encoder */
 	intel_connector_attach_encoder(intel_connector, encoder);
 
+	intel_bios_init_panel(dev_priv, &intel_connector->panel);
+
 	mutex_lock(&dev->mode_config.mutex);
 	intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
 	mutex_unlock(&dev->mode_config.mutex);
@@ -2061,13 +2064,13 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 
 	intel_backlight_setup(intel_connector, INVALID_PIPE);
 
-	if (dev_priv->vbt.dsi.config->dual_link)
+	if (intel_connector->panel.vbt.dsi.config->dual_link)
 		intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
 	else
 		intel_dsi->ports = BIT(port);
 
-	intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
-	intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
+	intel_dsi->dcs_backlight_ports = intel_connector->panel.vbt.dsi.bl_ports;
+	intel_dsi->dcs_cabc_ports = intel_connector->panel.vbt.dsi.cabc_ports;
 
 	for_each_dsi_port(port, intel_dsi->ports) {
 		struct intel_dsi_host *host;
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index c8e1fc53a881f..68513206a66a0 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -1159,9 +1159,10 @@ static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
 	return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * mul);
 }
 
-static u16 get_vbt_pwm_freq(struct drm_i915_private *dev_priv)
+static u16 get_vbt_pwm_freq(struct intel_connector *connector)
 {
-	u16 pwm_freq_hz = dev_priv->vbt.backlight.pwm_freq_hz;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+	u16 pwm_freq_hz = connector->panel.vbt.backlight.pwm_freq_hz;
 
 	if (pwm_freq_hz) {
 		drm_dbg_kms(&dev_priv->drm,
@@ -1181,7 +1182,7 @@ static u32 get_backlight_max_vbt(struct intel_connector *connector)
 {
 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
-	u16 pwm_freq_hz = get_vbt_pwm_freq(dev_priv);
+	u16 pwm_freq_hz = get_vbt_pwm_freq(connector);
 	u32 pwm;
 
 	if (!panel->backlight.pwm_funcs->hz_to_pwm) {
@@ -1218,11 +1219,11 @@ static u32 get_backlight_min_vbt(struct intel_connector *connector)
 	 * against this by letting the minimum be at most (arbitrarily chosen)
 	 * 25% of the max.
 	 */
-	min = clamp_t(int, dev_priv->vbt.backlight.min_brightness, 0, 64);
-	if (min != dev_priv->vbt.backlight.min_brightness) {
+	min = clamp_t(int, connector->panel.vbt.backlight.min_brightness, 0, 64);
+	if (min != connector->panel.vbt.backlight.min_brightness) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "clamping VBT min backlight %d/255 to %d/255\n",
-			    dev_priv->vbt.backlight.min_brightness, min);
+			    connector->panel.vbt.backlight.min_brightness, min);
 	}
 
 	/* vbt value is a coefficient in range [0..255] */
@@ -1411,7 +1412,7 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
 	struct intel_panel *panel = &connector->panel;
 	u32 pwm_ctl, val;
 
-	panel->backlight.controller = dev_priv->vbt.backlight.controller;
+	panel->backlight.controller = connector->panel.vbt.backlight.controller;
 
 	pwm_ctl = intel_de_read(dev_priv,
 				BXT_BLC_PWM_CTL(panel->backlight.controller));
@@ -1484,7 +1485,7 @@ static int ext_pwm_setup_backlight(struct intel_connector *connector,
 	u32 level;
 
 	/* Get the right PWM chip for DSI backlight according to VBT */
-	if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) {
+	if (connector->panel.vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) {
 		panel->backlight.pwm = pwm_get(dev->dev, "pwm_pmic_backlight");
 		desc = "PMIC";
 	} else {
@@ -1513,11 +1514,11 @@ static int ext_pwm_setup_backlight(struct intel_connector *connector,
 
 		drm_dbg_kms(&dev_priv->drm, "PWM already enabled at freq %ld, VBT freq %d, level %d\n",
 			    NSEC_PER_SEC / (unsigned long)panel->backlight.pwm_state.period,
-			    get_vbt_pwm_freq(dev_priv), level);
+			    get_vbt_pwm_freq(connector), level);
 	} else {
 		/* Set period from VBT frequency, leave other settings at 0. */
 		panel->backlight.pwm_state.period =
-			NSEC_PER_SEC / get_vbt_pwm_freq(dev_priv);
+			NSEC_PER_SEC / get_vbt_pwm_freq(connector);
 	}
 
 	drm_info(&dev_priv->drm, "Using %s PWM for LCD backlight control\n",
@@ -1602,7 +1603,7 @@ int intel_backlight_setup(struct intel_connector *connector, enum pipe pipe)
 	struct intel_panel *panel = &connector->panel;
 	int ret;
 
-	if (!dev_priv->vbt.backlight.present) {
+	if (!connector->panel.vbt.backlight.present) {
 		if (dev_priv->quirks & QUIRK_BACKLIGHT_PRESENT) {
 			drm_dbg_kms(&dev_priv->drm,
 				    "no backlight present per VBT, but present per quirk\n");
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index cc64119b52e69..c9ed05e6e16bd 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -674,7 +674,8 @@ static int get_panel_type(struct drm_i915_private *i915)
 
 /* Parse general panel options */
 static void
-parse_panel_options(struct drm_i915_private *i915)
+parse_panel_options(struct drm_i915_private *i915,
+		    struct intel_panel *panel)
 {
 	const struct bdb_lvds_options *lvds_options;
 	int panel_type;
@@ -684,11 +685,11 @@ parse_panel_options(struct drm_i915_private *i915)
 	if (!lvds_options)
 		return;
 
-	i915->vbt.lvds_dither = lvds_options->pixel_dither;
+	panel->vbt.lvds_dither = lvds_options->pixel_dither;
 
 	panel_type = get_panel_type(i915);
 
-	i915->vbt.panel_type = panel_type;
+	panel->vbt.panel_type = panel_type;
 
 	drrs_mode = (lvds_options->dps_panel_type_bits
 				>> (panel_type * 2)) & MODE_MASK;
@@ -699,16 +700,16 @@ parse_panel_options(struct drm_i915_private *i915)
 	 */
 	switch (drrs_mode) {
 	case 0:
-		i915->vbt.drrs_type = DRRS_TYPE_STATIC;
+		panel->vbt.drrs_type = DRRS_TYPE_STATIC;
 		drm_dbg_kms(&i915->drm, "DRRS supported mode is static\n");
 		break;
 	case 2:
-		i915->vbt.drrs_type = DRRS_TYPE_SEAMLESS;
+		panel->vbt.drrs_type = DRRS_TYPE_SEAMLESS;
 		drm_dbg_kms(&i915->drm,
 			    "DRRS supported mode is seamless\n");
 		break;
 	default:
-		i915->vbt.drrs_type = DRRS_TYPE_NONE;
+		panel->vbt.drrs_type = DRRS_TYPE_NONE;
 		drm_dbg_kms(&i915->drm,
 			    "DRRS not supported (VBT input)\n");
 		break;
@@ -717,13 +718,14 @@ parse_panel_options(struct drm_i915_private *i915)
 
 static void
 parse_lfp_panel_dtd(struct drm_i915_private *i915,
+		    struct intel_panel *panel,
 		    const struct bdb_lvds_lfp_data *lvds_lfp_data,
 		    const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs)
 {
 	const struct lvds_dvo_timing *panel_dvo_timing;
 	const struct lvds_fp_timing *fp_timing;
 	struct drm_display_mode *panel_fixed_mode;
-	int panel_type = i915->vbt.panel_type;
+	int panel_type = panel->vbt.panel_type;
 
 	panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data,
 					       lvds_lfp_data_ptrs,
@@ -735,7 +737,7 @@ parse_lfp_panel_dtd(struct drm_i915_private *i915,
 
 	fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing);
 
-	i915->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
+	panel->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
 
 	drm_dbg_kms(&i915->drm,
 		    "Found panel mode in BIOS VBT legacy lfp table: " DRM_MODE_FMT "\n",
@@ -748,20 +750,21 @@ parse_lfp_panel_dtd(struct drm_i915_private *i915,
 	/* check the resolution, just to be sure */
 	if (fp_timing->x_res == panel_fixed_mode->hdisplay &&
 	    fp_timing->y_res == panel_fixed_mode->vdisplay) {
-		i915->vbt.bios_lvds_val = fp_timing->lvds_reg_val;
+		panel->vbt.bios_lvds_val = fp_timing->lvds_reg_val;
 		drm_dbg_kms(&i915->drm,
 			    "VBT initial LVDS value %x\n",
-			    i915->vbt.bios_lvds_val);
+			    panel->vbt.bios_lvds_val);
 	}
 }
 
 static void
-parse_lfp_data(struct drm_i915_private *i915)
+parse_lfp_data(struct drm_i915_private *i915,
+	       struct intel_panel *panel)
 {
 	const struct bdb_lvds_lfp_data *data;
 	const struct bdb_lvds_lfp_data_tail *tail;
 	const struct bdb_lvds_lfp_data_ptrs *ptrs;
-	int panel_type = i915->vbt.panel_type;
+	int panel_type = panel->vbt.panel_type;
 
 	ptrs = find_section(i915, BDB_LVDS_LFP_DATA_PTRS);
 	if (!ptrs)
@@ -771,24 +774,25 @@ parse_lfp_data(struct drm_i915_private *i915)
 	if (!data)
 		return;
 
-	if (!i915->vbt.lfp_lvds_vbt_mode)
-		parse_lfp_panel_dtd(i915, data, ptrs);
+	if (!panel->vbt.lfp_lvds_vbt_mode)
+		parse_lfp_panel_dtd(i915, panel, data, ptrs);
 
 	tail = get_lfp_data_tail(data, ptrs);
 	if (!tail)
 		return;
 
 	if (i915->vbt.version >= 188) {
-		i915->vbt.seamless_drrs_min_refresh_rate =
+		panel->vbt.seamless_drrs_min_refresh_rate =
 			tail->seamless_drrs_min_refresh_rate[panel_type];
 		drm_dbg_kms(&i915->drm,
 			    "Seamless DRRS min refresh rate: %d Hz\n",
-			    i915->vbt.seamless_drrs_min_refresh_rate);
+			    panel->vbt.seamless_drrs_min_refresh_rate);
 	}
 }
 
 static void
-parse_generic_dtd(struct drm_i915_private *i915)
+parse_generic_dtd(struct drm_i915_private *i915,
+		  struct intel_panel *panel)
 {
 	const struct bdb_generic_dtd *generic_dtd;
 	const struct generic_dtd_entry *dtd;
@@ -823,14 +827,14 @@ parse_generic_dtd(struct drm_i915_private *i915)
 
 	num_dtd = (get_blocksize(generic_dtd) -
 		   sizeof(struct bdb_generic_dtd)) / generic_dtd->gdtd_size;
-	if (i915->vbt.panel_type >= num_dtd) {
+	if (panel->vbt.panel_type >= num_dtd) {
 		drm_err(&i915->drm,
 			"Panel type %d not found in table of %d DTD's\n",
-			i915->vbt.panel_type, num_dtd);
+			panel->vbt.panel_type, num_dtd);
 		return;
 	}
 
-	dtd = &generic_dtd->dtd[i915->vbt.panel_type];
+	dtd = &generic_dtd->dtd[panel->vbt.panel_type];
 
 	panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
 	if (!panel_fixed_mode)
@@ -873,15 +877,16 @@ parse_generic_dtd(struct drm_i915_private *i915)
 		    "Found panel mode in BIOS VBT generic dtd table: " DRM_MODE_FMT "\n",
 		    DRM_MODE_ARG(panel_fixed_mode));
 
-	i915->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
+	panel->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
 }
 
 static void
-parse_lfp_backlight(struct drm_i915_private *i915)
+parse_lfp_backlight(struct drm_i915_private *i915,
+		    struct intel_panel *panel)
 {
 	const struct bdb_lfp_backlight_data *backlight_data;
 	const struct lfp_backlight_data_entry *entry;
-	int panel_type = i915->vbt.panel_type;
+	int panel_type = panel->vbt.panel_type;
 	u16 level;
 
 	backlight_data = find_section(i915, BDB_LVDS_BACKLIGHT);
@@ -897,15 +902,15 @@ parse_lfp_backlight(struct drm_i915_private *i915)
 
 	entry = &backlight_data->data[panel_type];
 
-	i915->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM;
-	if (!i915->vbt.backlight.present) {
+	panel->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM;
+	if (!panel->vbt.backlight.present) {
 		drm_dbg_kms(&i915->drm,
 			    "PWM backlight not present in VBT (type %u)\n",
 			    entry->type);
 		return;
 	}
 
-	i915->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
+	panel->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
 	if (i915->vbt.version >= 191) {
 		size_t exp_size;
 
@@ -920,13 +925,13 @@ parse_lfp_backlight(struct drm_i915_private *i915)
 			const struct lfp_backlight_control_method *method;
 
 			method = &backlight_data->backlight_control[panel_type];
-			i915->vbt.backlight.type = method->type;
-			i915->vbt.backlight.controller = method->controller;
+			panel->vbt.backlight.type = method->type;
+			panel->vbt.backlight.controller = method->controller;
 		}
 	}
 
-	i915->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
-	i915->vbt.backlight.active_low_pwm = entry->active_low_pwm;
+	panel->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
+	panel->vbt.backlight.active_low_pwm = entry->active_low_pwm;
 
 	if (i915->vbt.version >= 234) {
 		u16 min_level;
@@ -947,28 +952,29 @@ parse_lfp_backlight(struct drm_i915_private *i915)
 			drm_warn(&i915->drm, "Brightness min level > 255\n");
 			level = 255;
 		}
-		i915->vbt.backlight.min_brightness = min_level;
+		panel->vbt.backlight.min_brightness = min_level;
 
-		i915->vbt.backlight.brightness_precision_bits =
+		panel->vbt.backlight.brightness_precision_bits =
 			backlight_data->brightness_precision_bits[panel_type];
 	} else {
 		level = backlight_data->level[panel_type];
-		i915->vbt.backlight.min_brightness = entry->min_brightness;
+		panel->vbt.backlight.min_brightness = entry->min_brightness;
 	}
 
 	drm_dbg_kms(&i915->drm,
 		    "VBT backlight PWM modulation frequency %u Hz, "
 		    "active %s, min brightness %u, level %u, controller %u\n",
-		    i915->vbt.backlight.pwm_freq_hz,
-		    i915->vbt.backlight.active_low_pwm ? "low" : "high",
-		    i915->vbt.backlight.min_brightness,
+		    panel->vbt.backlight.pwm_freq_hz,
+		    panel->vbt.backlight.active_low_pwm ? "low" : "high",
+		    panel->vbt.backlight.min_brightness,
 		    level,
-		    i915->vbt.backlight.controller);
+		    panel->vbt.backlight.controller);
 }
 
 /* Try to find sdvo panel data */
 static void
-parse_sdvo_panel_data(struct drm_i915_private *i915)
+parse_sdvo_panel_data(struct drm_i915_private *i915,
+		      struct intel_panel *panel)
 {
 	const struct bdb_sdvo_panel_dtds *dtds;
 	struct drm_display_mode *panel_fixed_mode;
@@ -1001,7 +1007,7 @@ parse_sdvo_panel_data(struct drm_i915_private *i915)
 
 	fill_detail_timing_data(panel_fixed_mode, &dtds->dtds[index]);
 
-	i915->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode;
+	panel->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode;
 
 	drm_dbg_kms(&i915->drm,
 		    "Found SDVO panel mode in BIOS VBT tables: " DRM_MODE_FMT "\n",
@@ -1183,7 +1189,8 @@ parse_driver_features(struct drm_i915_private *i915)
 }
 
 static void
-parse_panel_driver_features(struct drm_i915_private *i915)
+parse_panel_driver_features(struct drm_i915_private *i915,
+			    struct intel_panel *panel)
 {
 	const struct bdb_driver_features *driver;
 
@@ -1201,17 +1208,18 @@ parse_panel_driver_features(struct drm_i915_private *i915)
 		 * driver->drrs_enabled=false
 		 */
 		if (!driver->drrs_enabled)
-			i915->vbt.drrs_type = DRRS_TYPE_NONE;
+			panel->vbt.drrs_type = DRRS_TYPE_NONE;
 
-		i915->vbt.psr.enable = driver->psr_enabled;
+		panel->vbt.psr.enable = driver->psr_enabled;
 	}
 }
 
 static void
-parse_power_conservation_features(struct drm_i915_private *i915)
+parse_power_conservation_features(struct drm_i915_private *i915,
+				  struct intel_panel *panel)
 {
 	const struct bdb_lfp_power *power;
-	u8 panel_type = i915->vbt.panel_type;
+	u8 panel_type = panel->vbt.panel_type;
 
 	if (i915->vbt.version < 228)
 		return;
@@ -1220,7 +1228,7 @@ parse_power_conservation_features(struct drm_i915_private *i915)
 	if (!power)
 		return;
 
-	i915->vbt.psr.enable = power->psr & BIT(panel_type);
+	panel->vbt.psr.enable = power->psr & BIT(panel_type);
 
 	/*
 	 * If DRRS is not supported, drrs_type has to be set to 0.
@@ -1229,19 +1237,20 @@ parse_power_conservation_features(struct drm_i915_private *i915)
 	 * power->drrs & BIT(panel_type)=false
 	 */
 	if (!(power->drrs & BIT(panel_type)))
-		i915->vbt.drrs_type = DRRS_TYPE_NONE;
+		panel->vbt.drrs_type = DRRS_TYPE_NONE;
 
 	if (i915->vbt.version >= 232)
-		i915->vbt.edp.hobl = power->hobl & BIT(panel_type);
+		panel->vbt.edp.hobl = power->hobl & BIT(panel_type);
 }
 
 static void
-parse_edp(struct drm_i915_private *i915)
+parse_edp(struct drm_i915_private *i915,
+	  struct intel_panel *panel)
 {
 	const struct bdb_edp *edp;
 	const struct edp_power_seq *edp_pps;
 	const struct edp_fast_link_params *edp_link_params;
-	int panel_type = i915->vbt.panel_type;
+	int panel_type = panel->vbt.panel_type;
 
 	edp = find_section(i915, BDB_EDP);
 	if (!edp)
@@ -1249,13 +1258,13 @@ parse_edp(struct drm_i915_private *i915)
 
 	switch ((edp->color_depth >> (panel_type * 2)) & 3) {
 	case EDP_18BPP:
-		i915->vbt.edp.bpp = 18;
+		panel->vbt.edp.bpp = 18;
 		break;
 	case EDP_24BPP:
-		i915->vbt.edp.bpp = 24;
+		panel->vbt.edp.bpp = 24;
 		break;
 	case EDP_30BPP:
-		i915->vbt.edp.bpp = 30;
+		panel->vbt.edp.bpp = 30;
 		break;
 	}
 
@@ -1263,14 +1272,14 @@ parse_edp(struct drm_i915_private *i915)
 	edp_pps = &edp->power_seqs[panel_type];
 	edp_link_params = &edp->fast_link_params[panel_type];
 
-	i915->vbt.edp.pps = *edp_pps;
+	panel->vbt.edp.pps = *edp_pps;
 
 	switch (edp_link_params->rate) {
 	case EDP_RATE_1_62:
-		i915->vbt.edp.rate = DP_LINK_BW_1_62;
+		panel->vbt.edp.rate = DP_LINK_BW_1_62;
 		break;
 	case EDP_RATE_2_7:
-		i915->vbt.edp.rate = DP_LINK_BW_2_7;
+		panel->vbt.edp.rate = DP_LINK_BW_2_7;
 		break;
 	default:
 		drm_dbg_kms(&i915->drm,
@@ -1281,13 +1290,13 @@ parse_edp(struct drm_i915_private *i915)
 
 	switch (edp_link_params->lanes) {
 	case EDP_LANE_1:
-		i915->vbt.edp.lanes = 1;
+		panel->vbt.edp.lanes = 1;
 		break;
 	case EDP_LANE_2:
-		i915->vbt.edp.lanes = 2;
+		panel->vbt.edp.lanes = 2;
 		break;
 	case EDP_LANE_4:
-		i915->vbt.edp.lanes = 4;
+		panel->vbt.edp.lanes = 4;
 		break;
 	default:
 		drm_dbg_kms(&i915->drm,
@@ -1298,16 +1307,16 @@ parse_edp(struct drm_i915_private *i915)
 
 	switch (edp_link_params->preemphasis) {
 	case EDP_PREEMPHASIS_NONE:
-		i915->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0;
+		panel->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0;
 		break;
 	case EDP_PREEMPHASIS_3_5dB:
-		i915->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1;
+		panel->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1;
 		break;
 	case EDP_PREEMPHASIS_6dB:
-		i915->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2;
+		panel->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2;
 		break;
 	case EDP_PREEMPHASIS_9_5dB:
-		i915->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3;
+		panel->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3;
 		break;
 	default:
 		drm_dbg_kms(&i915->drm,
@@ -1318,16 +1327,16 @@ parse_edp(struct drm_i915_private *i915)
 
 	switch (edp_link_params->vswing) {
 	case EDP_VSWING_0_4V:
-		i915->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
+		panel->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 		break;
 	case EDP_VSWING_0_6V:
-		i915->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
+		panel->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
 		break;
 	case EDP_VSWING_0_8V:
-		i915->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
+		panel->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
 		break;
 	case EDP_VSWING_1_2V:
-		i915->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
+		panel->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 		break;
 	default:
 		drm_dbg_kms(&i915->drm,
@@ -1341,24 +1350,25 @@ parse_edp(struct drm_i915_private *i915)
 
 		/* Don't read from VBT if module parameter has valid value*/
 		if (i915->params.edp_vswing) {
-			i915->vbt.edp.low_vswing =
+			panel->vbt.edp.low_vswing =
 				i915->params.edp_vswing == 1;
 		} else {
 			vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF;
-			i915->vbt.edp.low_vswing = vswing == 0;
+			panel->vbt.edp.low_vswing = vswing == 0;
 		}
 	}
 
-	i915->vbt.edp.drrs_msa_timing_delay =
+	panel->vbt.edp.drrs_msa_timing_delay =
 		(edp->sdrrs_msa_timing_delay >> (panel_type * 2)) & 3;
 }
 
 static void
-parse_psr(struct drm_i915_private *i915)
+parse_psr(struct drm_i915_private *i915,
+	  struct intel_panel *panel)
 {
 	const struct bdb_psr *psr;
 	const struct psr_table *psr_table;
-	int panel_type = i915->vbt.panel_type;
+	int panel_type = panel->vbt.panel_type;
 
 	psr = find_section(i915, BDB_PSR);
 	if (!psr) {
@@ -1368,11 +1378,11 @@ parse_psr(struct drm_i915_private *i915)
 
 	psr_table = &psr->psr_table[panel_type];
 
-	i915->vbt.psr.full_link = psr_table->full_link;
-	i915->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
+	panel->vbt.psr.full_link = psr_table->full_link;
+	panel->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
 
 	/* Allowed VBT values goes from 0 to 15 */
-	i915->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
+	panel->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
 		psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames;
 
 	/*
@@ -1383,13 +1393,13 @@ parse_psr(struct drm_i915_private *i915)
 	    (DISPLAY_VER(i915) >= 9 && !IS_BROXTON(i915))) {
 		switch (psr_table->tp1_wakeup_time) {
 		case 0:
-			i915->vbt.psr.tp1_wakeup_time_us = 500;
+			panel->vbt.psr.tp1_wakeup_time_us = 500;
 			break;
 		case 1:
-			i915->vbt.psr.tp1_wakeup_time_us = 100;
+			panel->vbt.psr.tp1_wakeup_time_us = 100;
 			break;
 		case 3:
-			i915->vbt.psr.tp1_wakeup_time_us = 0;
+			panel->vbt.psr.tp1_wakeup_time_us = 0;
 			break;
 		default:
 			drm_dbg_kms(&i915->drm,
@@ -1397,19 +1407,19 @@ parse_psr(struct drm_i915_private *i915)
 				    psr_table->tp1_wakeup_time);
 			fallthrough;
 		case 2:
-			i915->vbt.psr.tp1_wakeup_time_us = 2500;
+			panel->vbt.psr.tp1_wakeup_time_us = 2500;
 			break;
 		}
 
 		switch (psr_table->tp2_tp3_wakeup_time) {
 		case 0:
-			i915->vbt.psr.tp2_tp3_wakeup_time_us = 500;
+			panel->vbt.psr.tp2_tp3_wakeup_time_us = 500;
 			break;
 		case 1:
-			i915->vbt.psr.tp2_tp3_wakeup_time_us = 100;
+			panel->vbt.psr.tp2_tp3_wakeup_time_us = 100;
 			break;
 		case 3:
-			i915->vbt.psr.tp2_tp3_wakeup_time_us = 0;
+			panel->vbt.psr.tp2_tp3_wakeup_time_us = 0;
 			break;
 		default:
 			drm_dbg_kms(&i915->drm,
@@ -1417,12 +1427,12 @@ parse_psr(struct drm_i915_private *i915)
 				    psr_table->tp2_tp3_wakeup_time);
 			fallthrough;
 		case 2:
-			i915->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
+			panel->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
 		break;
 		}
 	} else {
-		i915->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
-		i915->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
+		panel->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
+		panel->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
 	}
 
 	if (i915->vbt.version >= 226) {
@@ -1444,62 +1454,64 @@ parse_psr(struct drm_i915_private *i915)
 			wakeup_time = 2500;
 			break;
 		}
-		i915->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time;
+		panel->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time;
 	} else {
 		/* Reusing PSR1 wakeup time for PSR2 in older VBTs */
-		i915->vbt.psr.psr2_tp2_tp3_wakeup_time_us = i915->vbt.psr.tp2_tp3_wakeup_time_us;
+		panel->vbt.psr.psr2_tp2_tp3_wakeup_time_us = panel->vbt.psr.tp2_tp3_wakeup_time_us;
 	}
 }
 
 static void parse_dsi_backlight_ports(struct drm_i915_private *i915,
-				      u16 version, enum port port)
+				      struct intel_panel *panel,
+				      enum port port)
 {
-	if (!i915->vbt.dsi.config->dual_link || version < 197) {
-		i915->vbt.dsi.bl_ports = BIT(port);
-		if (i915->vbt.dsi.config->cabc_supported)
-			i915->vbt.dsi.cabc_ports = BIT(port);
+	if (!panel->vbt.dsi.config->dual_link || i915->vbt.version < 197) {
+		panel->vbt.dsi.bl_ports = BIT(port);
+		if (panel->vbt.dsi.config->cabc_supported)
+			panel->vbt.dsi.cabc_ports = BIT(port);
 
 		return;
 	}
 
-	switch (i915->vbt.dsi.config->dl_dcs_backlight_ports) {
+	switch (panel->vbt.dsi.config->dl_dcs_backlight_ports) {
 	case DL_DCS_PORT_A:
-		i915->vbt.dsi.bl_ports = BIT(PORT_A);
+		panel->vbt.dsi.bl_ports = BIT(PORT_A);
 		break;
 	case DL_DCS_PORT_C:
-		i915->vbt.dsi.bl_ports = BIT(PORT_C);
+		panel->vbt.dsi.bl_ports = BIT(PORT_C);
 		break;
 	default:
 	case DL_DCS_PORT_A_AND_C:
-		i915->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C);
+		panel->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C);
 		break;
 	}
 
-	if (!i915->vbt.dsi.config->cabc_supported)
+	if (!panel->vbt.dsi.config->cabc_supported)
 		return;
 
-	switch (i915->vbt.dsi.config->dl_dcs_cabc_ports) {
+	switch (panel->vbt.dsi.config->dl_dcs_cabc_ports) {
 	case DL_DCS_PORT_A:
-		i915->vbt.dsi.cabc_ports = BIT(PORT_A);
+		panel->vbt.dsi.cabc_ports = BIT(PORT_A);
 		break;
 	case DL_DCS_PORT_C:
-		i915->vbt.dsi.cabc_ports = BIT(PORT_C);
+		panel->vbt.dsi.cabc_ports = BIT(PORT_C);
 		break;
 	default:
 	case DL_DCS_PORT_A_AND_C:
-		i915->vbt.dsi.cabc_ports =
+		panel->vbt.dsi.cabc_ports =
 					BIT(PORT_A) | BIT(PORT_C);
 		break;
 	}
 }
 
 static void
-parse_mipi_config(struct drm_i915_private *i915)
+parse_mipi_config(struct drm_i915_private *i915,
+		  struct intel_panel *panel)
 {
 	const struct bdb_mipi_config *start;
 	const struct mipi_config *config;
 	const struct mipi_pps_data *pps;
-	int panel_type = i915->vbt.panel_type;
+	int panel_type = panel->vbt.panel_type;
 	enum port port;
 
 	/* parse MIPI blocks only if LFP type is MIPI */
@@ -1507,7 +1519,7 @@ parse_mipi_config(struct drm_i915_private *i915)
 		return;
 
 	/* Initialize this to undefined indicating no generic MIPI support */
-	i915->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID;
+	panel->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID;
 
 	/* Block #40 is already parsed and panel_fixed_mode is
 	 * stored in i915->lfp_lvds_vbt_mode
@@ -1534,17 +1546,17 @@ parse_mipi_config(struct drm_i915_private *i915)
 	pps = &start->pps[panel_type];
 
 	/* store as of now full data. Trim when we realise all is not needed */
-	i915->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL);
-	if (!i915->vbt.dsi.config)
+	panel->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL);
+	if (!panel->vbt.dsi.config)
 		return;
 
-	i915->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL);
-	if (!i915->vbt.dsi.pps) {
-		kfree(i915->vbt.dsi.config);
+	panel->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL);
+	if (!panel->vbt.dsi.pps) {
+		kfree(panel->vbt.dsi.config);
 		return;
 	}
 
-	parse_dsi_backlight_ports(i915, i915->vbt.version, port);
+	parse_dsi_backlight_ports(i915, panel, port);
 
 	/* FIXME is the 90 vs. 270 correct? */
 	switch (config->rotation) {
@@ -1553,25 +1565,25 @@ parse_mipi_config(struct drm_i915_private *i915)
 		 * Most (all?) VBTs claim 0 degrees despite having
 		 * an upside down panel, thus we do not trust this.
 		 */
-		i915->vbt.dsi.orientation =
+		panel->vbt.dsi.orientation =
 			DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
 		break;
 	case ENABLE_ROTATION_90:
-		i915->vbt.dsi.orientation =
+		panel->vbt.dsi.orientation =
 			DRM_MODE_PANEL_ORIENTATION_RIGHT_UP;
 		break;
 	case ENABLE_ROTATION_180:
-		i915->vbt.dsi.orientation =
+		panel->vbt.dsi.orientation =
 			DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
 		break;
 	case ENABLE_ROTATION_270:
-		i915->vbt.dsi.orientation =
+		panel->vbt.dsi.orientation =
 			DRM_MODE_PANEL_ORIENTATION_LEFT_UP;
 		break;
 	}
 
 	/* We have mandatory mipi config blocks. Initialize as generic panel */
-	i915->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
+	panel->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
 }
 
 /* Find the sequence block and size for the given panel. */
@@ -1734,13 +1746,14 @@ static int goto_next_sequence_v3(const u8 *data, int index, int total)
  * Get len of pre-fixed deassert fragment from a v1 init OTP sequence,
  * skip all delay + gpio operands and stop at the first DSI packet op.
  */
-static int get_init_otp_deassert_fragment_len(struct drm_i915_private *i915)
+static int get_init_otp_deassert_fragment_len(struct drm_i915_private *i915,
+					      struct intel_panel *panel)
 {
-	const u8 *data = i915->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
+	const u8 *data = panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
 	int index, len;
 
 	if (drm_WARN_ON(&i915->drm,
-			!data || i915->vbt.dsi.seq_version != 1))
+			!data || panel->vbt.dsi.seq_version != 1))
 		return 0;
 
 	/* index = 1 to skip sequence byte */
@@ -1768,7 +1781,8 @@ static int get_init_otp_deassert_fragment_len(struct drm_i915_private *i915)
  * these devices we split the init OTP sequence into a deassert sequence and
  * the actual init OTP part.
  */
-static void fixup_mipi_sequences(struct drm_i915_private *i915)
+static void fixup_mipi_sequences(struct drm_i915_private *i915,
+				 struct intel_panel *panel)
 {
 	u8 *init_otp;
 	int len;
@@ -1778,18 +1792,18 @@ static void fixup_mipi_sequences(struct drm_i915_private *i915)
 		return;
 
 	/* Limit this to v1 vid-mode sequences */
-	if (i915->vbt.dsi.config->is_cmd_mode ||
-	    i915->vbt.dsi.seq_version != 1)
+	if (panel->vbt.dsi.config->is_cmd_mode ||
+	    panel->vbt.dsi.seq_version != 1)
 		return;
 
 	/* Only do this if there are otp and assert seqs and no deassert seq */
-	if (!i915->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] ||
-	    !i915->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] ||
-	    i915->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET])
+	if (!panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] ||
+	    !panel->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] ||
+	    panel->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET])
 		return;
 
 	/* The deassert-sequence ends at the first DSI packet */
-	len = get_init_otp_deassert_fragment_len(i915);
+	len = get_init_otp_deassert_fragment_len(i915, panel);
 	if (!len)
 		return;
 
@@ -1797,25 +1811,26 @@ static void fixup_mipi_sequences(struct drm_i915_private *i915)
 		    "Using init OTP fragment to deassert reset\n");
 
 	/* Copy the fragment, update seq byte and terminate it */
-	init_otp = (u8 *)i915->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
-	i915->vbt.dsi.deassert_seq = kmemdup(init_otp, len + 1, GFP_KERNEL);
-	if (!i915->vbt.dsi.deassert_seq)
+	init_otp = (u8 *)panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
+	panel->vbt.dsi.deassert_seq = kmemdup(init_otp, len + 1, GFP_KERNEL);
+	if (!panel->vbt.dsi.deassert_seq)
 		return;
-	i915->vbt.dsi.deassert_seq[0] = MIPI_SEQ_DEASSERT_RESET;
-	i915->vbt.dsi.deassert_seq[len] = MIPI_SEQ_ELEM_END;
+	panel->vbt.dsi.deassert_seq[0] = MIPI_SEQ_DEASSERT_RESET;
+	panel->vbt.dsi.deassert_seq[len] = MIPI_SEQ_ELEM_END;
 	/* Use the copy for deassert */
-	i915->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET] =
-		i915->vbt.dsi.deassert_seq;
+	panel->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET] =
+		panel->vbt.dsi.deassert_seq;
 	/* Replace the last byte of the fragment with init OTP seq byte */
 	init_otp[len - 1] = MIPI_SEQ_INIT_OTP;
 	/* And make MIPI_MIPI_SEQ_INIT_OTP point to it */
-	i915->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] = init_otp + len - 1;
+	panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] = init_otp + len - 1;
 }
 
 static void
-parse_mipi_sequence(struct drm_i915_private *i915)
+parse_mipi_sequence(struct drm_i915_private *i915,
+		    struct intel_panel *panel)
 {
-	int panel_type = i915->vbt.panel_type;
+	int panel_type = panel->vbt.panel_type;
 	const struct bdb_mipi_sequence *sequence;
 	const u8 *seq_data;
 	u32 seq_size;
@@ -1823,7 +1838,7 @@ parse_mipi_sequence(struct drm_i915_private *i915)
 	int index = 0;
 
 	/* Only our generic panel driver uses the sequence block. */
-	if (i915->vbt.dsi.panel_id != MIPI_DSI_GENERIC_PANEL_ID)
+	if (panel->vbt.dsi.panel_id != MIPI_DSI_GENERIC_PANEL_ID)
 		return;
 
 	sequence = find_section(i915, BDB_MIPI_SEQUENCE);
@@ -1869,7 +1884,7 @@ parse_mipi_sequence(struct drm_i915_private *i915)
 			drm_dbg_kms(&i915->drm,
 				    "Unsupported sequence %u\n", seq_id);
 
-		i915->vbt.dsi.sequence[seq_id] = data + index;
+		panel->vbt.dsi.sequence[seq_id] = data + index;
 
 		if (sequence->version >= 3)
 			index = goto_next_sequence_v3(data, index, seq_size);
@@ -1882,18 +1897,18 @@ parse_mipi_sequence(struct drm_i915_private *i915)
 		}
 	}
 
-	i915->vbt.dsi.data = data;
-	i915->vbt.dsi.size = seq_size;
-	i915->vbt.dsi.seq_version = sequence->version;
+	panel->vbt.dsi.data = data;
+	panel->vbt.dsi.size = seq_size;
+	panel->vbt.dsi.seq_version = sequence->version;
 
-	fixup_mipi_sequences(i915);
+	fixup_mipi_sequences(i915, panel);
 
 	drm_dbg(&i915->drm, "MIPI related VBT parsing complete\n");
 	return;
 
 err:
 	kfree(data);
-	memset(i915->vbt.dsi.sequence, 0, sizeof(i915->vbt.dsi.sequence));
+	memset(panel->vbt.dsi.sequence, 0, sizeof(panel->vbt.dsi.sequence));
 }
 
 static void
@@ -2647,15 +2662,6 @@ init_vbt_defaults(struct drm_i915_private *i915)
 {
 	i915->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC;
 
-	/* Default to having backlight */
-	i915->vbt.backlight.present = true;
-
-	/* LFP panel data */
-	i915->vbt.lvds_dither = 1;
-
-	/* SDVO panel data */
-	i915->vbt.sdvo_lvds_vbt_mode = NULL;
-
 	/* general features */
 	i915->vbt.int_tv_support = 1;
 	i915->vbt.int_crt_support = 1;
@@ -2675,6 +2681,17 @@ init_vbt_defaults(struct drm_i915_private *i915)
 		    i915->vbt.lvds_ssc_freq);
 }
 
+/* Common defaults which may be overridden by VBT. */
+static void
+init_vbt_panel_defaults(struct intel_panel *panel)
+{
+	/* Default to having backlight */
+	panel->vbt.backlight.present = true;
+
+	/* LFP panel data */
+	panel->vbt.lvds_dither = true;
+}
+
 /* Defaults to initialize only if there is no VBT. */
 static void
 init_vbt_missing_defaults(struct drm_i915_private *i915)
@@ -2980,19 +2997,22 @@ out:
 	kfree(oprom_vbt);
 }
 
-void intel_bios_init_panel(struct drm_i915_private *i915)
+void intel_bios_init_panel(struct drm_i915_private *i915,
+			   struct intel_panel *panel)
 {
-	parse_panel_options(i915);
-	parse_generic_dtd(i915);
-	parse_lfp_data(i915);
-	parse_lfp_backlight(i915);
-	parse_sdvo_panel_data(i915);
-	parse_panel_driver_features(i915);
-	parse_power_conservation_features(i915);
-	parse_edp(i915);
-	parse_psr(i915);
-	parse_mipi_config(i915);
-	parse_mipi_sequence(i915);
+	init_vbt_panel_defaults(panel);
+
+	parse_panel_options(i915, panel);
+	parse_generic_dtd(i915, panel);
+	parse_lfp_data(i915, panel);
+	parse_lfp_backlight(i915, panel);
+	parse_sdvo_panel_data(i915, panel);
+	parse_panel_driver_features(i915, panel);
+	parse_power_conservation_features(i915, panel);
+	parse_edp(i915, panel);
+	parse_psr(i915, panel);
+	parse_mipi_config(i915, panel);
+	parse_mipi_sequence(i915, panel);
 }
 
 /**
@@ -3014,19 +3034,22 @@ void intel_bios_driver_remove(struct drm_i915_private *i915)
 		list_del(&entry->node);
 		kfree(entry);
 	}
+}
 
-	kfree(i915->vbt.sdvo_lvds_vbt_mode);
-	i915->vbt.sdvo_lvds_vbt_mode = NULL;
-	kfree(i915->vbt.lfp_lvds_vbt_mode);
-	i915->vbt.lfp_lvds_vbt_mode = NULL;
-	kfree(i915->vbt.dsi.data);
-	i915->vbt.dsi.data = NULL;
-	kfree(i915->vbt.dsi.pps);
-	i915->vbt.dsi.pps = NULL;
-	kfree(i915->vbt.dsi.config);
-	i915->vbt.dsi.config = NULL;
-	kfree(i915->vbt.dsi.deassert_seq);
-	i915->vbt.dsi.deassert_seq = NULL;
+void intel_bios_fini_panel(struct intel_panel *panel)
+{
+	kfree(panel->vbt.sdvo_lvds_vbt_mode);
+	panel->vbt.sdvo_lvds_vbt_mode = NULL;
+	kfree(panel->vbt.lfp_lvds_vbt_mode);
+	panel->vbt.lfp_lvds_vbt_mode = NULL;
+	kfree(panel->vbt.dsi.data);
+	panel->vbt.dsi.data = NULL;
+	kfree(panel->vbt.dsi.pps);
+	panel->vbt.dsi.pps = NULL;
+	kfree(panel->vbt.dsi.config);
+	panel->vbt.dsi.config = NULL;
+	kfree(panel->vbt.dsi.deassert_seq);
+	panel->vbt.dsi.deassert_seq = NULL;
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index c744d75fa435f..86129f015718d 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -36,6 +36,7 @@ struct drm_i915_private;
 struct intel_bios_encoder_data;
 struct intel_crtc_state;
 struct intel_encoder;
+struct intel_panel;
 enum port;
 
 enum intel_backlight_type {
@@ -230,7 +231,9 @@ struct mipi_pps_data {
 } __packed;
 
 void intel_bios_init(struct drm_i915_private *dev_priv);
-void intel_bios_init_panel(struct drm_i915_private *dev_priv);
+void intel_bios_init_panel(struct drm_i915_private *dev_priv,
+			   struct intel_panel *panel);
+void intel_bios_fini_panel(struct intel_panel *panel);
 void intel_bios_driver_remove(struct drm_i915_private *dev_priv);
 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 5cae1d19bcbb6..247093e9efe5a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1042,17 +1042,18 @@ bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
 
 static bool use_edp_hobl(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	struct intel_connector *connector = intel_dp->attached_connector;
 
-	return i915->vbt.edp.hobl && !intel_dp->hobl_failed;
+	return connector->panel.vbt.edp.hobl && !intel_dp->hobl_failed;
 }
 
 static bool use_edp_low_vswing(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	struct intel_connector *connector = intel_dp->attached_connector;
 
-	return i915->vbt.edp.low_vswing;
+	return connector->panel.vbt.edp.low_vswing;
 }
 
 static const struct intel_ddi_buf_trans *
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7ad93afcc50c2..9f105250f4749 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9580,7 +9580,6 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
 	}
 
 	intel_bios_init(i915);
-	intel_bios_init_panel(i915);
 
 	ret = intel_vga_register(i915);
 	if (ret)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 95d1cbfe37123..1a2f51e01f701 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -279,6 +279,73 @@ struct intel_panel_bl_funcs {
 	u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
 };
 
+enum drrs_type {
+	DRRS_TYPE_NONE,
+	DRRS_TYPE_STATIC,
+	DRRS_TYPE_SEAMLESS,
+};
+
+struct intel_vbt_panel_data {
+	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
+	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
+
+	/* Feature bits */
+	unsigned int panel_type:4;
+	unsigned int lvds_dither:1;
+	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
+
+	u8 seamless_drrs_min_refresh_rate;
+	enum drrs_type drrs_type;
+
+	struct {
+		int rate;
+		int lanes;
+		int preemphasis;
+		int vswing;
+		int bpp;
+		struct edp_power_seq pps;
+		u8 drrs_msa_timing_delay;
+		bool low_vswing;
+		bool initialized;
+		bool hobl;
+	} edp;
+
+	struct {
+		bool enable;
+		bool full_link;
+		bool require_aux_wakeup;
+		int idle_frames;
+		int tp1_wakeup_time_us;
+		int tp2_tp3_wakeup_time_us;
+		int psr2_tp2_tp3_wakeup_time_us;
+	} psr;
+
+	struct {
+		u16 pwm_freq_hz;
+		u16 brightness_precision_bits;
+		bool present;
+		bool active_low_pwm;
+		u8 min_brightness;	/* min_brightness/255 of max */
+		u8 controller;		/* brightness controller number */
+		enum intel_backlight_type type;
+	} backlight;
+
+	/* MIPI DSI */
+	struct {
+		u16 panel_id;
+		struct mipi_config *config;
+		struct mipi_pps_data *pps;
+		u16 bl_ports;
+		u16 cabc_ports;
+		u8 seq_version;
+		u32 size;
+		u8 *data;
+		const u8 *sequence[MIPI_SEQ_MAX];
+		u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
+		enum drm_panel_orientation orientation;
+	} dsi;
+};
+
 struct intel_panel {
 	struct list_head fixed_modes;
 
@@ -318,6 +385,8 @@ struct intel_panel {
 		const struct intel_panel_bl_funcs *pwm_funcs;
 		void (*power)(struct intel_connector *, bool enable);
 	} backlight;
+
+	struct intel_vbt_panel_data vbt;
 };
 
 struct intel_digital_port;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6580af399cc7f..e6282465b57ae 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1219,11 +1219,12 @@ static int intel_dp_max_bpp(struct intel_dp *intel_dp,
 	if (intel_dp_is_edp(intel_dp)) {
 		/* Get bpp from vbt only for panels that dont have bpp in edid */
 		if (intel_connector->base.display_info.bpc == 0 &&
-		    dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
+		    intel_connector->panel.vbt.edp.bpp &&
+		    intel_connector->panel.vbt.edp.bpp < bpp) {
 			drm_dbg_kms(&dev_priv->drm,
 				    "clamping bpp for eDP panel to BIOS-provided %i\n",
-				    dev_priv->vbt.edp.bpp);
-			bpp = dev_priv->vbt.edp.bpp;
+				    intel_connector->panel.vbt.edp.bpp);
+			bpp = intel_connector->panel.vbt.edp.bpp;
 		}
 	}
 
@@ -1879,7 +1880,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
 	}
 
 	if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
-		pipe_config->msa_timing_delay = i915->vbt.edp.drrs_msa_timing_delay;
+		pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
 
 	pipe_config->has_drrs = true;
 
@@ -2712,8 +2713,10 @@ static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	struct intel_connector *connector = intel_dp->attached_connector;
 
-	if (dev_priv->vbt.edp.bpp && pipe_bpp > dev_priv->vbt.edp.bpp) {
+	if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
 		/*
 		 * This is a big fat ugly hack.
 		 *
@@ -2729,8 +2732,8 @@ void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
 		 */
 		drm_dbg_kms(&dev_priv->drm,
 			    "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
-			    pipe_bpp, dev_priv->vbt.edp.bpp);
-		dev_priv->vbt.edp.bpp = pipe_bpp;
+			    pipe_bpp, connector->panel.vbt.edp.bpp);
+		connector->panel.vbt.edp.bpp = pipe_bpp;
 	}
 }
 
@@ -5209,8 +5212,10 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 	}
 	intel_connector->edid = edid;
 
+	intel_bios_init_panel(dev_priv, &intel_connector->panel);
+
 	intel_panel_add_edid_fixed_modes(intel_connector,
-					 dev_priv->vbt.drrs_type != DRRS_TYPE_NONE);
+					 intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE);
 
 	/* MSO requires information from the EDID */
 	intel_edp_mso_init(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index e794d910df564..a54902c713a34 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -29,6 +29,7 @@ struct link_config_limits {
 	int min_bpp, max_bpp;
 };
 
+void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
 void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
 				       struct intel_crtc_state *pipe_config,
 				       struct link_config_limits *limits);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index fb6cf30ee6281..c92d5bb2326a3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -370,7 +370,7 @@ static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector,
 	int ret;
 
 	ret = drm_edp_backlight_init(&intel_dp->aux, &panel->backlight.edp.vesa.info,
-				     i915->vbt.backlight.pwm_freq_hz, intel_dp->edp_dpcd,
+				     panel->vbt.backlight.pwm_freq_hz, intel_dp->edp_dpcd,
 				     &current_level, &current_mode);
 	if (ret < 0)
 		return ret;
@@ -454,7 +454,7 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *connector)
 	case INTEL_DP_AUX_BACKLIGHT_OFF:
 		return -ENODEV;
 	case INTEL_DP_AUX_BACKLIGHT_AUTO:
-		switch (i915->vbt.backlight.type) {
+		switch (panel->vbt.backlight.type) {
 		case INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE:
 			try_vesa_interface = true;
 			break;
@@ -466,7 +466,7 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *connector)
 		}
 		break;
 	case INTEL_DP_AUX_BACKLIGHT_ON:
-		if (i915->vbt.backlight.type != INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE)
+		if (panel->vbt.backlight.type != INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE)
 			try_intel_interface = true;
 
 		try_vesa_interface = true;
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index 166caf293f7bc..7da4a9cbe4ba4 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -217,9 +217,6 @@ static void intel_drrs_frontbuffer_update(struct drm_i915_private *dev_priv,
 {
 	struct intel_crtc *crtc;
 
-	if (dev_priv->vbt.drrs_type != DRRS_TYPE_SEAMLESS)
-		return;
-
 	for_each_intel_crtc(&dev_priv->drm, crtc) {
 		unsigned int frontbuffer_bits;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c
index 389a8c24cdc1e..35e121cd226c5 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi.c
@@ -102,7 +102,7 @@ intel_dsi_get_panel_orientation(struct intel_connector *connector)
 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	enum drm_panel_orientation orientation;
 
-	orientation = dev_priv->vbt.dsi.orientation;
+	orientation = connector->panel.vbt.dsi.orientation;
 	if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
 		return orientation;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
index 7d234429e71ef..1bc7118c56a2a 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
@@ -160,12 +160,10 @@ static void dcs_enable_backlight(const struct intel_crtc_state *crtc_state,
 static int dcs_setup_backlight(struct intel_connector *connector,
 			       enum pipe unused)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_panel *panel = &connector->panel;
 
-	if (dev_priv->vbt.backlight.brightness_precision_bits > 8)
-		panel->backlight.max = (1 << dev_priv->vbt.backlight.brightness_precision_bits) - 1;
+	if (panel->vbt.backlight.brightness_precision_bits > 8)
+		panel->backlight.max = (1 << panel->vbt.backlight.brightness_precision_bits) - 1;
 	else
 		panel->backlight.max = PANEL_PWM_MAX_VALUE;
 
@@ -185,11 +183,10 @@ static const struct intel_panel_bl_funcs dcs_bl_funcs = {
 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector)
 {
 	struct drm_device *dev = intel_connector->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
 	struct intel_panel *panel = &intel_connector->panel;
 
-	if (dev_priv->vbt.backlight.type != INTEL_BACKLIGHT_DSI_DCS)
+	if (panel->vbt.backlight.type != INTEL_BACKLIGHT_DSI_DCS)
 		return -ENODEV;
 
 	if (drm_WARN_ON(dev, encoder->type != INTEL_OUTPUT_DSI))
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index dd24aef925f2e..75e8cc4337c93 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -240,9 +240,10 @@ static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
 	return data;
 }
 
-static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
+static void vlv_exec_gpio(struct intel_connector *connector,
 			  u8 gpio_source, u8 gpio_index, bool value)
 {
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct gpio_map *map;
 	u16 pconf0, padval;
 	u32 tmp;
@@ -256,7 +257,7 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
 
 	map = &vlv_gpio_table[gpio_index];
 
-	if (dev_priv->vbt.dsi.seq_version >= 3) {
+	if (connector->panel.vbt.dsi.seq_version >= 3) {
 		/* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
 		port = IOSF_PORT_GPIO_NC;
 	} else {
@@ -287,14 +288,15 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
 	vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
 }
 
-static void chv_exec_gpio(struct drm_i915_private *dev_priv,
+static void chv_exec_gpio(struct intel_connector *connector,
 			  u8 gpio_source, u8 gpio_index, bool value)
 {
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	u16 cfg0, cfg1;
 	u16 family_num;
 	u8 port;
 
-	if (dev_priv->vbt.dsi.seq_version >= 3) {
+	if (connector->panel.vbt.dsi.seq_version >= 3) {
 		if (gpio_index >= CHV_GPIO_IDX_START_SE) {
 			/* XXX: it's unclear whether 255->57 is part of SE. */
 			gpio_index -= CHV_GPIO_IDX_START_SE;
@@ -340,9 +342,10 @@ static void chv_exec_gpio(struct drm_i915_private *dev_priv,
 	vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
 }
 
-static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
+static void bxt_exec_gpio(struct intel_connector *connector,
 			  u8 gpio_source, u8 gpio_index, bool value)
 {
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	/* XXX: this table is a quick ugly hack. */
 	static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
 	struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
@@ -366,9 +369,11 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
 	gpiod_set_value(gpio_desc, value);
 }
 
-static void icl_exec_gpio(struct drm_i915_private *dev_priv,
+static void icl_exec_gpio(struct intel_connector *connector,
 			  u8 gpio_source, u8 gpio_index, bool value)
 {
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+
 	drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
 }
 
@@ -376,18 +381,19 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 {
 	struct drm_device *dev = intel_dsi->base.base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_connector *connector = intel_dsi->attached_connector;
 	u8 gpio_source, gpio_index = 0, gpio_number;
 	bool value;
 
 	drm_dbg_kms(&dev_priv->drm, "\n");
 
-	if (dev_priv->vbt.dsi.seq_version >= 3)
+	if (connector->panel.vbt.dsi.seq_version >= 3)
 		gpio_index = *data++;
 
 	gpio_number = *data++;
 
 	/* gpio source in sequence v2 only */
-	if (dev_priv->vbt.dsi.seq_version == 2)
+	if (connector->panel.vbt.dsi.seq_version == 2)
 		gpio_source = (*data >> 1) & 3;
 	else
 		gpio_source = 0;
@@ -396,13 +402,13 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 	value = *data++ & 1;
 
 	if (DISPLAY_VER(dev_priv) >= 11)
-		icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
+		icl_exec_gpio(connector, gpio_source, gpio_index, value);
 	else if (IS_VALLEYVIEW(dev_priv))
-		vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
+		vlv_exec_gpio(connector, gpio_source, gpio_number, value);
 	else if (IS_CHERRYVIEW(dev_priv))
-		chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
+		chv_exec_gpio(connector, gpio_source, gpio_number, value);
 	else
-		bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value);
+		bxt_exec_gpio(connector, gpio_source, gpio_index, value);
 
 	return data;
 }
@@ -585,14 +591,15 @@ static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,
 			       enum mipi_seq seq_id)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+	struct intel_connector *connector = intel_dsi->attached_connector;
 	const u8 *data;
 	fn_mipi_elem_exec mipi_elem_exec;
 
 	if (drm_WARN_ON(&dev_priv->drm,
-			seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence)))
+			seq_id >= ARRAY_SIZE(connector->panel.vbt.dsi.sequence)))
 		return;
 
-	data = dev_priv->vbt.dsi.sequence[seq_id];
+	data = connector->panel.vbt.dsi.sequence[seq_id];
 	if (!data)
 		return;
 
@@ -605,7 +612,7 @@ static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,
 	data++;
 
 	/* Skip Size of Sequence. */
-	if (dev_priv->vbt.dsi.seq_version >= 3)
+	if (connector->panel.vbt.dsi.seq_version >= 3)
 		data += 4;
 
 	while (1) {
@@ -621,7 +628,7 @@ static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,
 			mipi_elem_exec = NULL;
 
 		/* Size of Operation. */
-		if (dev_priv->vbt.dsi.seq_version >= 3)
+		if (connector->panel.vbt.dsi.seq_version >= 3)
 			operation_size = *data++;
 
 		if (mipi_elem_exec) {
@@ -669,10 +676,10 @@ void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
 
 void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
 {
-	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+	struct intel_connector *connector = intel_dsi->attached_connector;
 
 	/* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
-	if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
+	if (is_vid_mode(intel_dsi) && connector->panel.vbt.dsi.seq_version >= 3)
 		return;
 
 	msleep(msec);
@@ -734,9 +741,10 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 {
 	struct drm_device *dev = intel_dsi->base.base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
-	struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
-	struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
+	struct intel_connector *connector = intel_dsi->attached_connector;
+	struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
+	struct mipi_pps_data *pps = connector->panel.vbt.dsi.pps;
+	struct drm_display_mode *mode = connector->panel.vbt.lfp_lvds_vbt_mode;
 	u16 burst_mode_ratio;
 	enum port port;
 
@@ -872,7 +880,8 @@ void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on)
 {
 	struct drm_device *dev = intel_dsi->base.base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
+	struct intel_connector *connector = intel_dsi->attached_connector;
+	struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
 	enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
 	bool want_backlight_gpio = false;
 	bool want_panel_gpio = false;
@@ -927,7 +936,8 @@ void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi)
 {
 	struct drm_device *dev = intel_dsi->base.base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
+	struct intel_connector *connector = intel_dsi->attached_connector;
+	struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
 
 	if (intel_dsi->gpio_panel) {
 		gpiod_put(intel_dsi->gpio_panel);
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index e8478161f8b9b..9f250a70519aa 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -809,7 +809,7 @@ static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
 	else
 		val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK);
 	if (val == 0)
-		val = dev_priv->vbt.bios_lvds_val;
+		val = connector->panel.vbt.bios_lvds_val;
 
 	return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 }
@@ -967,9 +967,11 @@ void intel_lvds_init(struct drm_i915_private *dev_priv)
 	}
 	intel_connector->edid = edid;
 
+	intel_bios_init_panel(dev_priv, &intel_connector->panel);
+
 	/* Try EDID first */
 	intel_panel_add_edid_fixed_modes(intel_connector,
-					 dev_priv->vbt.drrs_type != DRRS_TYPE_NONE);
+					 intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE);
 
 	/* Failed to get EDID, what about VBT? */
 	if (!intel_panel_preferred_fixed_mode(intel_connector))
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index d1d1b59102d69..d055e41185582 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -75,9 +75,8 @@ const struct drm_display_mode *
 intel_panel_downclock_mode(struct intel_connector *connector,
 			   const struct drm_display_mode *adjusted_mode)
 {
-	struct drm_i915_private *i915 = to_i915(connector->base.dev);
 	const struct drm_display_mode *fixed_mode, *best_mode = NULL;
-	int min_vrefresh = i915->vbt.seamless_drrs_min_refresh_rate;
+	int min_vrefresh = connector->panel.vbt.seamless_drrs_min_refresh_rate;
 	int max_vrefresh = drm_mode_vrefresh(adjusted_mode);
 
 	/* pick the fixed_mode with the lowest refresh rate */
@@ -113,13 +112,11 @@ int intel_panel_get_modes(struct intel_connector *connector)
 
 enum drrs_type intel_panel_drrs_type(struct intel_connector *connector)
 {
-	struct drm_i915_private *i915 = to_i915(connector->base.dev);
-
 	if (list_empty(&connector->panel.fixed_modes) ||
 	    list_is_singular(&connector->panel.fixed_modes))
 		return DRRS_TYPE_NONE;
 
-	return i915->vbt.drrs_type;
+	return connector->panel.vbt.drrs_type;
 }
 
 int intel_panel_compute_config(struct intel_connector *connector,
@@ -260,7 +257,7 @@ void intel_panel_add_vbt_lfp_fixed_mode(struct intel_connector *connector)
 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
 	const struct drm_display_mode *mode;
 
-	mode = i915->vbt.lfp_lvds_vbt_mode;
+	mode = connector->panel.vbt.lfp_lvds_vbt_mode;
 	if (!mode)
 		return;
 
@@ -274,7 +271,7 @@ void intel_panel_add_vbt_sdvo_fixed_mode(struct intel_connector *connector)
 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
 	const struct drm_display_mode *mode;
 
-	mode = i915->vbt.sdvo_lvds_vbt_mode;
+	mode = connector->panel.vbt.sdvo_lvds_vbt_mode;
 	if (!mode)
 		return;
 
@@ -639,6 +636,8 @@ void intel_panel_fini(struct intel_connector *connector)
 
 	intel_backlight_destroy(panel);
 
+	intel_bios_fini_panel(panel);
+
 	list_for_each_entry_safe(fixed_mode, next, &panel->fixed_modes, head) {
 		list_del(&fixed_mode->head);
 		drm_mode_destroy(connector->base.dev, fixed_mode);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index e6f701e411e0d..1b21a341962f4 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -209,7 +209,8 @@ static int
 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	int backlight_controller = dev_priv->vbt.backlight.controller;
+	struct intel_connector *connector = intel_dp->attached_connector;
+	int backlight_controller = connector->panel.vbt.backlight.controller;
 
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
@@ -1189,8 +1190,9 @@ static void pps_init_delays_vbt(struct intel_dp *intel_dp,
 				struct edp_power_seq *vbt)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	struct intel_connector *connector = intel_dp->attached_connector;
 
-	*vbt = dev_priv->vbt.edp.pps;
+	*vbt = connector->panel.vbt.edp.pps;
 
 	if (!pps_delays_valid(vbt))
 		return;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 36356893c7caf..aedb3e0e69ecd 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -399,6 +399,7 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 
 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
 {
+	struct intel_connector *connector = intel_dp->attached_connector;
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u32 val = 0;
 
@@ -411,20 +412,20 @@ static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
 		goto check_tp3_sel;
 	}
 
-	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
+	if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0)
 		val |= EDP_PSR_TP1_TIME_0us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
+	else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100)
 		val |= EDP_PSR_TP1_TIME_100us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
+	else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500)
 		val |= EDP_PSR_TP1_TIME_500us;
 	else
 		val |= EDP_PSR_TP1_TIME_2500us;
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
+	if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0)
 		val |= EDP_PSR_TP2_TP3_TIME_0us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
+	else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100)
 		val |= EDP_PSR_TP2_TP3_TIME_100us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+	else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500)
 		val |= EDP_PSR_TP2_TP3_TIME_500us;
 	else
 		val |= EDP_PSR_TP2_TP3_TIME_2500us;
@@ -441,13 +442,14 @@ check_tp3_sel:
 
 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
 {
+	struct intel_connector *connector = intel_dp->attached_connector;
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	int idle_frames;
 
 	/* Let's use 6 as the minimum to cover all known cases including the
 	 * off-by-one issue that HW has in some cases.
 	 */
-	idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
+	idle_frames = max(6, connector->panel.vbt.psr.idle_frames);
 	idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
 
 	if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf))
@@ -483,18 +485,19 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
 
 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
 {
+	struct intel_connector *connector = intel_dp->attached_connector;
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u32 val = 0;
 
 	if (dev_priv->params.psr_safest_params)
 		return EDP_PSR2_TP2_TIME_2500us;
 
-	if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
-	    dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
+	if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
+	    connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
 		val |= EDP_PSR2_TP2_TIME_50us;
-	else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
+	else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
 		val |= EDP_PSR2_TP2_TIME_100us;
-	else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
+	else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
 		val |= EDP_PSR2_TP2_TIME_500us;
 	else
 		val |= EDP_PSR2_TP2_TIME_2500us;
@@ -2367,6 +2370,7 @@ unlock:
  */
 void intel_psr_init(struct intel_dp *intel_dp)
 {
+	struct intel_connector *connector = intel_dp->attached_connector;
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
@@ -2391,13 +2395,13 @@ void intel_psr_init(struct intel_dp *intel_dp)
 	intel_dp->psr.source_support = true;
 
 	if (dev_priv->params.enable_psr == -1)
-		if (!dev_priv->vbt.psr.enable)
+		if (!connector->panel.vbt.psr.enable)
 			dev_priv->params.enable_psr = 0;
 
 	/* Set link_standby x link_off defaults */
 	if (DISPLAY_VER(dev_priv) < 12)
 		/* For new platforms up to TGL let's respect VBT back again */
-		intel_dp->psr.link_standby = dev_priv->vbt.psr.full_link;
+		intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;
 
 	INIT_WORK(&intel_dp->psr.work, intel_psr_work);
 	INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index ab88d8b783e6a..7137d9e7aa187 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -2868,6 +2868,7 @@ static bool
 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
 {
 	struct drm_encoder *encoder = &intel_sdvo->base.base;
+	struct drm_i915_private *i915 = to_i915(encoder->dev);
 	struct drm_connector *connector;
 	struct intel_connector *intel_connector;
 	struct intel_sdvo_connector *intel_sdvo_connector;
@@ -2899,6 +2900,8 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
 	if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
 		goto err;
 
+	intel_bios_init_panel(i915, &intel_connector->panel);
+
 	/*
 	 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
 	 * SDVO->LVDS transcoders can't cope with the EDID mode.
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 1954f07f0d3ec..be8fd3c362df3 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -782,6 +782,7 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state,
 {
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	enum port port;
@@ -838,7 +839,7 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state,
 	 * the delay in that case. If there is no deassert-seq, then an
 	 * unconditional msleep is used to give the panel time to power-on.
 	 */
-	if (dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) {
+	if (connector->panel.vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) {
 		intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
 		intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
 	} else {
@@ -1690,7 +1691,8 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
 {
 	struct drm_device *dev = intel_dsi->base.base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
+	struct intel_connector *connector = intel_dsi->attached_connector;
+	struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
 	u32 tlpx_ns, extra_byte_count, tlpx_ui;
 	u32 ui_num, ui_den;
 	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
@@ -1924,13 +1926,15 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
 
 	intel_dsi->panel_power_off_time = ktime_get_boottime();
 
-	if (dev_priv->vbt.dsi.config->dual_link)
+	intel_bios_init_panel(dev_priv, &intel_connector->panel);
+
+	if (intel_connector->panel.vbt.dsi.config->dual_link)
 		intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
 	else
 		intel_dsi->ports = BIT(port);
 
-	intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
-	intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
+	intel_dsi->dcs_backlight_ports = intel_connector->panel.vbt.dsi.bl_ports;
+	intel_dsi->dcs_cabc_ports = intel_connector->panel.vbt.dsi.cabc_ports;
 
 	/* Create a DSI host (and a device) for each port. */
 	for_each_dsi_port(port, intel_dsi->ports) {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8802ba39087b0..c70c80f5799a2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -193,12 +193,6 @@ struct drm_i915_display_funcs {
 
 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
 
-enum drrs_type {
-	DRRS_TYPE_NONE,
-	DRRS_TYPE_STATIC,
-	DRRS_TYPE_SEAMLESS,
-};
-
 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
@@ -307,76 +301,19 @@ struct intel_vbt_data {
 	/* bdb version */
 	u16 version;
 
-	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
-	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
-
 	/* Feature bits */
 	unsigned int int_tv_support:1;
-	unsigned int lvds_dither:1;
 	unsigned int int_crt_support:1;
 	unsigned int lvds_use_ssc:1;
 	unsigned int int_lvds_support:1;
 	unsigned int display_clock_mode:1;
 	unsigned int fdi_rx_polarity_inverted:1;
-	unsigned int panel_type:4;
 	int lvds_ssc_freq;
-	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
 	enum drm_panel_orientation orientation;
 
 	bool override_afc_startup;
 	u8 override_afc_startup_val;
 
-	u8 seamless_drrs_min_refresh_rate;
-	enum drrs_type drrs_type;
-
-	struct {
-		int rate;
-		int lanes;
-		int preemphasis;
-		int vswing;
-		int bpp;
-		struct edp_power_seq pps;
-		u8 drrs_msa_timing_delay;
-		bool low_vswing;
-		bool initialized;
-		bool hobl;
-	} edp;
-
-	struct {
-		bool enable;
-		bool full_link;
-		bool require_aux_wakeup;
-		int idle_frames;
-		int tp1_wakeup_time_us;
-		int tp2_tp3_wakeup_time_us;
-		int psr2_tp2_tp3_wakeup_time_us;
-	} psr;
-
-	struct {
-		u16 pwm_freq_hz;
-		u16 brightness_precision_bits;
-		bool present;
-		bool active_low_pwm;
-		u8 min_brightness;	/* min_brightness/255 of max */
-		u8 controller;		/* brightness controller number */
-		enum intel_backlight_type type;
-	} backlight;
-
-	/* MIPI DSI */
-	struct {
-		u16 panel_id;
-		struct mipi_config *config;
-		struct mipi_pps_data *pps;
-		u16 bl_ports;
-		u16 cabc_ports;
-		u8 seq_version;
-		u32 size;
-		u8 *data;
-		const u8 *sequence[MIPI_SEQ_MAX];
-		u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
-		enum drm_panel_orientation orientation;
-	} dsi;
-
 	int crt_ddc_pin;
 
 	struct list_head display_devices;
-- 
GitLab


From c518a775a843413786d3db8b5cab084597730a5a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 10 May 2022 13:42:40 +0300
Subject: [PATCH 0107/1731] drm/i915/bios: Determine panel type via PNPID match
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Apparently when the VBT panel_type==0xff we should trawl through
the PNPID table and check for a match against the EDID. If a
match is found the index gives us the panel_type.

Tried to match the Windows behaviour here with first looking
for an exact match, and if one isn't found we fall back to
looking for a match w/o the mfg year/week.

v2: Rebase due to vlv_dsi changes
v3: Adjust to .get_panel_type() vfunc

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5545
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-14-ville.syrjala@linux.intel.com
---
 drivers/gpu/drm/i915/display/icl_dsi.c    |  2 +-
 drivers/gpu/drm/i915/display/intel_bios.c | 98 ++++++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_bios.h |  4 +-
 drivers/gpu/drm/i915/display/intel_dp.c   |  3 +-
 drivers/gpu/drm/i915/display/intel_lvds.c |  3 +-
 drivers/gpu/drm/i915/display/intel_sdvo.c |  2 +-
 drivers/gpu/drm/i915/display/vlv_dsi.c    |  2 +-
 7 files changed, 95 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 825727dc0a272..996bd3fdda6bd 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -2049,7 +2049,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 	/* attach connector to encoder */
 	intel_connector_attach_encoder(intel_connector, encoder);
 
-	intel_bios_init_panel(dev_priv, &intel_connector->panel);
+	intel_bios_init_panel(dev_priv, &intel_connector->panel, NULL);
 
 	mutex_lock(&dev->mode_config.mutex);
 	intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index c9ed05e6e16bd..d80d147154b44 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -584,6 +584,14 @@ get_lvds_fp_timing(const struct bdb_lvds_lfp_data *data,
 	return (const void *)data + ptrs->ptr[index].fp_timing.offset;
 }
 
+static const struct lvds_pnp_id *
+get_lvds_pnp_id(const struct bdb_lvds_lfp_data *data,
+		const struct bdb_lvds_lfp_data_ptrs *ptrs,
+		int index)
+{
+	return (const void *)data + ptrs->ptr[index].panel_pnp_id.offset;
+}
+
 static const struct bdb_lvds_lfp_data_tail *
 get_lfp_data_tail(const struct bdb_lvds_lfp_data *data,
 		  const struct bdb_lvds_lfp_data_ptrs *ptrs)
@@ -594,12 +602,14 @@ get_lfp_data_tail(const struct bdb_lvds_lfp_data *data,
 		return NULL;
 }
 
-static int opregion_get_panel_type(struct drm_i915_private *i915)
+static int opregion_get_panel_type(struct drm_i915_private *i915,
+				   const struct edid *edid)
 {
 	return intel_opregion_get_panel_type(i915);
 }
 
-static int vbt_get_panel_type(struct drm_i915_private *i915)
+static int vbt_get_panel_type(struct drm_i915_private *i915,
+			      const struct edid *edid)
 {
 	const struct bdb_lvds_options *lvds_options;
 
@@ -607,7 +617,8 @@ static int vbt_get_panel_type(struct drm_i915_private *i915)
 	if (!lvds_options)
 		return -1;
 
-	if (lvds_options->panel_type > 0xf) {
+	if (lvds_options->panel_type > 0xf &&
+	    lvds_options->panel_type != 0xff) {
 		drm_dbg_kms(&i915->drm, "Invalid VBT panel type 0x%x\n",
 			    lvds_options->panel_type);
 		return -1;
@@ -616,7 +627,54 @@ static int vbt_get_panel_type(struct drm_i915_private *i915)
 	return lvds_options->panel_type;
 }
 
-static int fallback_get_panel_type(struct drm_i915_private *i915)
+static int pnpid_get_panel_type(struct drm_i915_private *i915,
+				const struct edid *edid)
+{
+	const struct bdb_lvds_lfp_data *data;
+	const struct bdb_lvds_lfp_data_ptrs *ptrs;
+	const struct lvds_pnp_id *edid_id;
+	struct lvds_pnp_id edid_id_nodate;
+	int i, best = -1;
+
+	if (!edid)
+		return -1;
+
+	edid_id = (const void *)&edid->mfg_id[0];
+
+	edid_id_nodate = *edid_id;
+	edid_id_nodate.mfg_week = 0;
+	edid_id_nodate.mfg_year = 0;
+
+	ptrs = find_section(i915, BDB_LVDS_LFP_DATA_PTRS);
+	if (!ptrs)
+		return -1;
+
+	data = find_section(i915, BDB_LVDS_LFP_DATA);
+	if (!data)
+		return -1;
+
+	for (i = 0; i < 16; i++) {
+		const struct lvds_pnp_id *vbt_id =
+			get_lvds_pnp_id(data, ptrs, i);
+
+		/* full match? */
+		if (!memcmp(vbt_id, edid_id, sizeof(*vbt_id)))
+			return i;
+
+		/*
+		 * Accept a match w/o date if no full match is found,
+		 * and the VBT entry does not specify a date.
+		 */
+		if (best < 0 &&
+		    !memcmp(vbt_id, &edid_id_nodate, sizeof(*vbt_id)))
+			best = i;
+	}
+
+	return best;
+}
+
+static int fallback_get_panel_type(struct drm_i915_private *i915,
+				   const struct edid *edid)
 {
 	return 0;
 }
@@ -624,14 +682,17 @@ static int fallback_get_panel_type(struct drm_i915_private *i915)
 enum panel_type {
 	PANEL_TYPE_OPREGION,
 	PANEL_TYPE_VBT,
+	PANEL_TYPE_PNPID,
 	PANEL_TYPE_FALLBACK,
 };
 
-static int get_panel_type(struct drm_i915_private *i915)
+static int get_panel_type(struct drm_i915_private *i915,
+			  const struct edid *edid)
 {
 	struct {
 		const char *name;
-		int (*get_panel_type)(struct drm_i915_private *i915);
+		int (*get_panel_type)(struct drm_i915_private *i915,
+				      const struct edid *edid);
 		int panel_type;
 	} panel_types[] = {
 		[PANEL_TYPE_OPREGION] = {
@@ -642,6 +703,10 @@ static int get_panel_type(struct drm_i915_private *i915)
 			.name = "VBT",
 			.get_panel_type = vbt_get_panel_type,
 		},
+		[PANEL_TYPE_PNPID] = {
+			.name = "PNPID",
+			.get_panel_type = pnpid_get_panel_type,
+		},
 		[PANEL_TYPE_FALLBACK] = {
 			.name = "fallback",
 			.get_panel_type = fallback_get_panel_type,
@@ -650,9 +715,10 @@ static int get_panel_type(struct drm_i915_private *i915)
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(panel_types); i++) {
-		panel_types[i].panel_type = panel_types[i].get_panel_type(i915);
+		panel_types[i].panel_type = panel_types[i].get_panel_type(i915, edid);
 
-		drm_WARN_ON(&i915->drm, panel_types[i].panel_type > 0xf);
+		drm_WARN_ON(&i915->drm, panel_types[i].panel_type > 0xf &&
+			    panel_types[i].panel_type != 0xff);
 
 		if (panel_types[i].panel_type >= 0)
 			drm_dbg_kms(&i915->drm, "Panel type (%s): %d\n",
@@ -661,7 +727,11 @@ static int get_panel_type(struct drm_i915_private *i915)
 
 	if (panel_types[PANEL_TYPE_OPREGION].panel_type >= 0)
 		i = PANEL_TYPE_OPREGION;
-	else if (panel_types[PANEL_TYPE_VBT].panel_type >= 0)
+	else if (panel_types[PANEL_TYPE_VBT].panel_type == 0xff &&
+		 panel_types[PANEL_TYPE_PNPID].panel_type >= 0)
+		i = PANEL_TYPE_PNPID;
+	else if (panel_types[PANEL_TYPE_VBT].panel_type != 0xff &&
+		 panel_types[PANEL_TYPE_VBT].panel_type >= 0)
 		i = PANEL_TYPE_VBT;
 	else
 		i = PANEL_TYPE_FALLBACK;
@@ -675,7 +745,8 @@ static int get_panel_type(struct drm_i915_private *i915)
 /* Parse general panel options */
 static void
 parse_panel_options(struct drm_i915_private *i915,
-		    struct intel_panel *panel)
+		    struct intel_panel *panel,
+		    const struct edid *edid)
 {
 	const struct bdb_lvds_options *lvds_options;
 	int panel_type;
@@ -687,7 +758,7 @@ parse_panel_options(struct drm_i915_private *i915,
 
 	panel->vbt.lvds_dither = lvds_options->pixel_dither;
 
-	panel_type = get_panel_type(i915);
+	panel_type = get_panel_type(i915, edid);
 
 	panel->vbt.panel_type = panel_type;
 
@@ -2998,11 +3069,12 @@ out:
 }
 
 void intel_bios_init_panel(struct drm_i915_private *i915,
-			   struct intel_panel *panel)
+			   struct intel_panel *panel,
+			   const struct edid *edid)
 {
 	init_vbt_panel_defaults(panel);
 
-	parse_panel_options(i915, panel);
+	parse_panel_options(i915, panel, edid);
 	parse_generic_dtd(i915, panel);
 	parse_lfp_data(i915, panel);
 	parse_lfp_backlight(i915, panel);
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index 86129f015718d..b112200ae0a0b 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -33,6 +33,7 @@
 #include <linux/types.h>
 
 struct drm_i915_private;
+struct edid;
 struct intel_bios_encoder_data;
 struct intel_crtc_state;
 struct intel_encoder;
@@ -232,7 +233,8 @@ struct mipi_pps_data {
 
 void intel_bios_init(struct drm_i915_private *dev_priv);
 void intel_bios_init_panel(struct drm_i915_private *dev_priv,
-			   struct intel_panel *panel);
+			   struct intel_panel *panel,
+			   const struct edid *edid);
 void intel_bios_fini_panel(struct intel_panel *panel);
 void intel_bios_driver_remove(struct drm_i915_private *dev_priv);
 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e6282465b57ae..f74acc746d11a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5212,7 +5212,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 	}
 	intel_connector->edid = edid;
 
-	intel_bios_init_panel(dev_priv, &intel_connector->panel);
+	intel_bios_init_panel(dev_priv, &intel_connector->panel,
+			      IS_ERR(edid) ? NULL : edid);
 
 	intel_panel_add_edid_fixed_modes(intel_connector,
 					 intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE);
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 9f250a70519aa..595f03343939f 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -967,7 +967,8 @@ void intel_lvds_init(struct drm_i915_private *dev_priv)
 	}
 	intel_connector->edid = edid;
 
-	intel_bios_init_panel(dev_priv, &intel_connector->panel);
+	intel_bios_init_panel(dev_priv, &intel_connector->panel,
+			      IS_ERR(edid) ? NULL : edid);
 
 	/* Try EDID first */
 	intel_panel_add_edid_fixed_modes(intel_connector,
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 7137d9e7aa187..ba76783994ae0 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -2900,7 +2900,7 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
 	if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
 		goto err;
 
-	intel_bios_init_panel(i915, &intel_connector->panel);
+	intel_bios_init_panel(i915, &intel_connector->panel, NULL);
 
 	/*
 	 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index be8fd3c362df3..abda0888c8d41 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -1926,7 +1926,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
 
 	intel_dsi->panel_power_off_time = ktime_get_boottime();
 
-	intel_bios_init_panel(dev_priv, &intel_connector->panel);
+	intel_bios_init_panel(dev_priv, &intel_connector->panel, NULL);
 
 	if (intel_connector->panel.vbt.dsi.config->dual_link)
 		intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
-- 
GitLab


From 0aa93f54f4341a40b05ec2ac242109e78661d7aa Mon Sep 17 00:00:00 2001
From: Vivek Kasireddy <vivek.kasireddy@intel.com>
Date: Wed, 25 May 2022 17:19:39 -0700
Subject: [PATCH 0108/1731] drm/i915/tc: Don't default disconnected legacy
 Type-C ports to TBT mode (v2)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Commit 30e114ef4b16 ("drm/i915/tc: Check for DP-alt, legacy sinks before
taking PHY ownership") defaults any disconnected Type-C ports to TBT-alt
mode which presents a problem (which could most likely result in a system
hang) when userspace forces a modeset on a Type-C port that is wired for
legacy HDMI. The following warning is seen when Weston forces a modeset
on a disconnected legacy Type-C port (HDMI) on a TGL based Gigabyte system:
(https://www.gigabyte.com/Mini-PcBarebone/GB-BSi3-1115G4-rev-10#ov)

Missing case (clock == 173000)
WARNING: CPU: 1 PID: 438 at drivers/gpu/drm/i915/display/intel_ddi.c:245
icl_ddi_tc_enable_clock.cold+0x16a/0x1cf [i915]
CPU: 1 PID: 438 Comm: kworker/u8:3 Tainted: G     U  W   E
5.18.0-rc5-drm-tip+ #20
Hardware name: GIGABYTE GB-BSi3-1115G4/GB-BSi3-1115G4, BIOS F9
10/16/2021
Workqueue: i915_modeset intel_atomic_commit_work [i915]
RIP: 0010:icl_ddi_tc_enable_clock.cold+0x16a/0x1cf [i915]
Code: 74 6c 7f 10 81 fd d0 78 02 00 74 6d 81 fd b0 1e 04 00 74 70 48 63
d5 48 c7 c6 c0 7b ab c0 48 c7 c7 20 75 ab c0 e8 b8 b5 c1 f0 <0f> 0b 45
31 ed e9 fb fe ff ff 49 63 d5
 48 c7 c6 80 7b ab c0 48 c7
RSP: 0018:ffff8882522c78f0 EFLAGS: 00010282
RAX: 0000000000000000 RBX: 0000000000000003 RCX: 0000000000000000
RDX: 0000000000000027 RSI: 0000000000000004 RDI: ffffed104a458f10
RBP: 0000000000011558 R08: ffffffffb078de4e R09: ffff888269ca748b
R10: ffffed104d394e91 R11: 0000000000000000 R12: ffff888255a318f8
R13: 0000000000000002 R14: ffff888255a30000 R15: ffff88823ef00348
FS:  0000000000000000(0000) GS:ffff888269c80000(0000)
knlGS:0000000000000000
CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 00007fd7afa42000 CR3: 0000000255c02004 CR4: 00000000007706e0
PKRU: 55555554
Call Trace:
<TASK>
intel_ddi_pre_enable.cold+0x96/0x5bf [i915]
intel_encoders_pre_enable+0x10e/0x140 [i915]
hsw_crtc_enable+0x207/0x99d [i915]
? ilk_crtc_enable.cold+0x2a/0x2a [i915]
? prepare_to_wait_exclusive+0x120/0x120
intel_enable_crtc+0x9a/0xf0 [i915]
skl_commit_modeset_enables+0x466/0x820 [i915]
? intel_commit_modeset_enables+0xd0/0xd0 [i915]
? intel_mbus_dbox_update+0x1ed/0x250 [i915]
intel_atomic_commit_tail+0xf2d/0x3040 [i915]
_raw_spin_lock_irqsave+0x87/0xe0
_raw_read_unlock_irqrestore+0x40/0x40
__update_load_avg_cfs_rq+0x70/0x5c0
__i915_sw_fence_complete+0x85/0x3b0 [i915]
? intel_get_crtc_new_encoder+0x190/0x190 [i915]
? sysvec_irq_work+0x13/0x90
? asm_sysvec_irq_work+0x12/0x20
? _raw_spin_lock_irq+0x82/0xd0
? read_word_at_a_time+0xe/0x20
? process_one_work+0x393/0x690
process_one_work+0x393/0x690
worker_thread+0x2b7/0x620
? process_one_work+0x690/0x690
kthread+0x15a/0x190
? kthread_complete_and_exit+0x20/0x20
ret_from_fork+0x1f/0x30

Continuing with the modeset without setting the DDI clock results in
more warnings and eventually a system hang. This does not seem to
happen with disconnected legacy or DP-alt DP ports because the clock
rate defaults to 162000 (which is a valid TBT clock) during the link
training process. Therefore, to fix this issue, this patch avoids
setting disconnected Type-C legacy ports to TBT-alt mode which prevents
the selection of TBT PLL when a modeset is forced.

v2: (Imre)
- Retain the check for legacy hotplug live status to account for
incorrect VBTs.

Cc: Imre Deak <imre.deak@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220526001939.4031112-2-vivek.kasireddy@intel.com
---
 drivers/gpu/drm/i915/display/intel_tc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index b8b822ea37553..6773840f6cc70 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -494,7 +494,8 @@ static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
 	}
 
 	live_status_mask = tc_port_live_status_mask(dig_port);
-	if (!(live_status_mask & (BIT(TC_PORT_DP_ALT) | BIT(TC_PORT_LEGACY)))) {
+	if (!(live_status_mask & (BIT(TC_PORT_DP_ALT) | BIT(TC_PORT_LEGACY))) &&
+	    !dig_port->tc_legacy_port) {
 		drm_dbg_kms(&i915->drm, "Port %s: PHY ownership not required (live status %02x)\n",
 			    dig_port->tc_port_name, live_status_mask);
 		goto out_set_tbt_alt_mode;
-- 
GitLab


From 92a020747d6c9e2efe8168a4a444576581bba636 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 3 May 2022 21:22:17 +0300
Subject: [PATCH 0109/1731] drm/i915: Split shared dpll .get_dplls() into
 compute and get phases
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Split the DPLL state computation into a separate function
from the current .get_dplls() which currently serves a dual duty
by also reserving the shared DPLLs.

v2: s/false/-EINVAL/ (Jani)

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-2-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c     |  14 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 281 ++++++++++++++----
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   3 +
 3 files changed, 230 insertions(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 6eef0b8a91eb1..c19fb075ee6e0 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -933,7 +933,17 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
 static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
 				  struct intel_crtc *crtc)
 {
-	return 0;
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	struct intel_encoder *encoder =
+		intel_get_crtc_new_encoder(state, crtc_state);
+
+	if (DISPLAY_VER(dev_priv) < 11 &&
+	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
+		return 0;
+
+	return intel_compute_shared_dplls(state, crtc, encoder);
 }
 
 static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
@@ -1134,7 +1144,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
 	ilk_compute_dpll(crtc_state, &crtc_state->dpll,
 			 &crtc_state->dpll);
 
-	return 0;
+	return intel_compute_shared_dplls(state, crtc, NULL);
 }
 
 static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 22f55574a35c5..4c5c3439b745a 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -90,6 +90,9 @@ struct intel_shared_dpll_funcs {
 struct intel_dpll_mgr {
 	const struct dpll_info *dpll_info;
 
+	int (*compute_dplls)(struct intel_atomic_state *state,
+			     struct intel_crtc *crtc,
+			     struct intel_encoder *encoder);
 	int (*get_dplls)(struct intel_atomic_state *state,
 			 struct intel_crtc *crtc,
 			 struct intel_encoder *encoder);
@@ -514,6 +517,13 @@ static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
 	udelay(200);
 }
 
+static int ibx_compute_dpll(struct intel_atomic_state *state,
+			    struct intel_crtc *crtc,
+			    struct intel_encoder *encoder)
+{
+	return 0;
+}
+
 static int ibx_get_dpll(struct intel_atomic_state *state,
 			struct intel_crtc *crtc,
 			struct intel_encoder *encoder)
@@ -578,6 +588,7 @@ static const struct dpll_info pch_plls[] = {
 
 static const struct intel_dpll_mgr pch_pll_mgr = {
 	.dpll_info = pch_plls,
+	.compute_dplls = ibx_compute_dpll,
 	.get_dplls = ibx_get_dpll,
 	.put_dplls = intel_put_dpll,
 	.dump_hw_state = ibx_dump_hw_state,
@@ -894,33 +905,35 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
 	*r2_out = best.r2;
 }
 
-static struct intel_shared_dpll *
-hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
-		       struct intel_crtc *crtc)
+static int
+hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
+			   struct intel_crtc *crtc)
 {
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
-	struct intel_shared_dpll *pll;
-	u32 val;
 	unsigned int p, n2, r2;
 
 	hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p);
 
-	val = WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL |
-	      WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
-	      WRPLL_DIVIDER_POST(p);
-
-	crtc_state->dpll_hw_state.wrpll = val;
+	crtc_state->dpll_hw_state.wrpll =
+		WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL |
+		WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
+		WRPLL_DIVIDER_POST(p);
 
-	pll = intel_find_shared_dpll(state, crtc,
-				     &crtc_state->dpll_hw_state,
-				     BIT(DPLL_ID_WRPLL2) |
-				     BIT(DPLL_ID_WRPLL1));
+	return 0;
+}
 
-	if (!pll)
-		return NULL;
+static struct intel_shared_dpll *
+hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
+		       struct intel_crtc *crtc)
+{
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 
-	return pll;
+	return intel_find_shared_dpll(state, crtc,
+				      &crtc_state->dpll_hw_state,
+				      BIT(DPLL_ID_WRPLL2) |
+				      BIT(DPLL_ID_WRPLL1));
 }
 
 static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
@@ -963,6 +976,24 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
 	return (refclk * n / 10) / (p * r) * 2;
 }
 
+static int
+hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	int clock = crtc_state->port_clock;
+
+	switch (clock / 2) {
+	case 81000:
+	case 135000:
+	case 270000:
+		return 0;
+	default:
+		drm_dbg_kms(&dev_priv->drm, "Invalid clock for DP: %d\n",
+			    clock);
+		return -EINVAL;
+	}
+}
+
 static struct intel_shared_dpll *
 hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
 {
@@ -982,8 +1013,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
 		pll_id = DPLL_ID_LCPLL_2700;
 		break;
 	default:
-		drm_dbg_kms(&dev_priv->drm, "Invalid clock for DP: %d\n",
-			    clock);
+		MISSING_CASE(clock / 2);
 		return NULL;
 	}
 
@@ -1019,18 +1049,28 @@ static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
 	return link_clock * 2;
 }
 
-static struct intel_shared_dpll *
-hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
-		      struct intel_crtc *crtc)
+static int
+hsw_ddi_spll_compute_dpll(struct intel_atomic_state *state,
+			  struct intel_crtc *crtc)
 {
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 
 	if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000))
-		return NULL;
+		return -EINVAL;
+
+	crtc_state->dpll_hw_state.spll =
+		SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;
 
-	crtc_state->dpll_hw_state.spll = SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz |
-					 SPLL_REF_MUXED_SSC;
+	return 0;
+}
+
+static struct intel_shared_dpll *
+hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
+		      struct intel_crtc *crtc)
+{
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 
 	return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state,
 				      BIT(DPLL_ID_SPLL));
@@ -1060,6 +1100,23 @@ static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
 	return link_clock * 2;
 }
 
+static int hsw_compute_dpll(struct intel_atomic_state *state,
+			    struct intel_crtc *crtc,
+			    struct intel_encoder *encoder)
+{
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		return hsw_ddi_wrpll_compute_dpll(state, crtc);
+	else if (intel_crtc_has_dp_encoder(crtc_state))
+		return hsw_ddi_lcpll_compute_dpll(crtc_state);
+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
+		return hsw_ddi_spll_compute_dpll(state, crtc);
+	else
+		return -EINVAL;
+}
+
 static int hsw_get_dpll(struct intel_atomic_state *state,
 			struct intel_crtc *crtc,
 			struct intel_encoder *encoder)
@@ -1153,6 +1210,7 @@ static const struct dpll_info hsw_plls[] = {
 
 static const struct intel_dpll_mgr hsw_pll_mgr = {
 	.dpll_info = hsw_plls,
+	.compute_dplls = hsw_compute_dpll,
 	.get_dplls = hsw_get_dpll,
 	.put_dplls = intel_put_dpll,
 	.update_ref_clks = hsw_update_dpll_ref_clks,
@@ -1741,23 +1799,28 @@ static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
 	return link_clock * 2;
 }
 
-static int skl_get_dpll(struct intel_atomic_state *state,
-			struct intel_crtc *crtc,
-			struct intel_encoder *encoder)
+static int skl_compute_dpll(struct intel_atomic_state *state,
+			    struct intel_crtc *crtc,
+			    struct intel_encoder *encoder)
 {
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
-	struct intel_shared_dpll *pll;
-	int ret;
 
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
-		ret = skl_ddi_hdmi_pll_dividers(crtc_state);
+		return skl_ddi_hdmi_pll_dividers(crtc_state);
 	else if (intel_crtc_has_dp_encoder(crtc_state))
-		ret = skl_ddi_dp_set_dpll_hw_state(crtc_state);
+		return skl_ddi_dp_set_dpll_hw_state(crtc_state);
 	else
-		ret = -EINVAL;
-	if (ret)
-		return ret;
+		return -EINVAL;
+}
+
+static int skl_get_dpll(struct intel_atomic_state *state,
+			struct intel_crtc *crtc,
+			struct intel_encoder *encoder)
+{
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	struct intel_shared_dpll *pll;
 
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 		pll = intel_find_shared_dpll(state, crtc,
@@ -1834,6 +1897,7 @@ static const struct dpll_info skl_plls[] = {
 
 static const struct intel_dpll_mgr skl_pll_mgr = {
 	.dpll_info = skl_plls,
+	.compute_dplls = skl_compute_dpll,
 	.get_dplls = skl_get_dpll,
 	.put_dplls = intel_put_dpll,
 	.update_ref_clks = skl_update_dpll_ref_clks,
@@ -2225,6 +2289,21 @@ static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
 	return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock);
 }
 
+static int bxt_compute_dpll(struct intel_atomic_state *state,
+			    struct intel_crtc *crtc,
+			    struct intel_encoder *encoder)
+{
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		return bxt_ddi_hdmi_set_dpll_hw_state(crtc_state);
+	else if (intel_crtc_has_dp_encoder(crtc_state))
+		return bxt_ddi_dp_set_dpll_hw_state(crtc_state);
+	else
+		return -EINVAL;
+}
+
 static int bxt_get_dpll(struct intel_atomic_state *state,
 			struct intel_crtc *crtc,
 			struct intel_encoder *encoder)
@@ -2234,16 +2313,6 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_shared_dpll *pll;
 	enum intel_dpll_id id;
-	int ret;
-
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
-		ret = bxt_ddi_hdmi_set_dpll_hw_state(crtc_state);
-	else if (intel_crtc_has_dp_encoder(crtc_state))
-		ret = bxt_ddi_dp_set_dpll_hw_state(crtc_state);
-	else
-		ret = -EINVAL;
-	if (ret)
-		return ret;
 
 	/* 1:1 mapping between ports and PLLs */
 	id = (enum intel_dpll_id) encoder->port;
@@ -2302,6 +2371,7 @@ static const struct dpll_info bxt_plls[] = {
 
 static const struct intel_dpll_mgr bxt_pll_mgr = {
 	.dpll_info = bxt_plls,
+	.compute_dplls = bxt_compute_dpll,
 	.get_dplls = bxt_get_dpll,
 	.put_dplls = intel_put_dpll,
 	.update_ref_clks = bxt_update_dpll_ref_clks,
@@ -3119,19 +3189,16 @@ static u32 intel_get_hti_plls(struct drm_i915_private *i915)
 	return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->hti_state);
 }
 
-static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
-				  struct intel_crtc *crtc,
-				  struct intel_encoder *encoder)
+static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
+				      struct intel_crtc *crtc)
 {
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
-	struct skl_wrpll_params pll_params = { };
 	struct icl_port_dpll *port_dpll =
 		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum port port = encoder->port;
-	unsigned long dpll_mask;
-	int ret;
+	struct skl_wrpll_params pll_params = {};
+	bool ret;
 
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
@@ -3147,6 +3214,21 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
 
 	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
 
+	return 0;
+}
+
+static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
+				  struct intel_crtc *crtc,
+				  struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	struct icl_port_dpll *port_dpll =
+		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
+	enum port port = encoder->port;
+	unsigned long dpll_mask;
+
 	if (IS_ALDERLAKE_S(dev_priv)) {
 		dpll_mask =
 			BIT(DPLL_ID_DG1_DPLL3) |
@@ -3198,16 +3280,15 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
 	return 0;
 }
 
-static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
-				struct intel_crtc *crtc,
-				struct intel_encoder *encoder)
+static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
+				    struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
-	struct skl_wrpll_params pll_params = { };
-	struct icl_port_dpll *port_dpll;
-	enum intel_dpll_id dpll_id;
+	struct icl_port_dpll *port_dpll =
+		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
+	struct skl_wrpll_params pll_params = {};
 	int ret;
 
 	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
@@ -3220,6 +3301,30 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
 
 	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
 
+	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
+	ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
+	if (ret) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "Could not calculate MG PHY PLL state.\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
+				struct intel_crtc *crtc,
+				struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	struct icl_port_dpll *port_dpll =
+		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
+	enum intel_dpll_id dpll_id;
+	int ret;
+
+	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
 	port_dpll->pll = intel_find_shared_dpll(state, crtc,
 						&port_dpll->hw_state,
 						BIT(DPLL_ID_ICL_TBTPLL));
@@ -3232,13 +3337,6 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
 
 
 	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
-	ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
-	if (ret) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "Could not calculate MG PHY PLL state.\n");
-		goto err_unreference_tbt_pll;
-	}
-
 	dpll_id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
 							 encoder->port));
 	port_dpll->pll = intel_find_shared_dpll(state, crtc,
@@ -3263,6 +3361,23 @@ err_unreference_tbt_pll:
 	return ret;
 }
 
+static int icl_compute_dplls(struct intel_atomic_state *state,
+			     struct intel_crtc *crtc,
+			     struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+	if (intel_phy_is_combo(dev_priv, phy))
+		return icl_compute_combo_phy_dpll(state, crtc);
+	else if (intel_phy_is_tc(dev_priv, phy))
+		return icl_compute_tc_phy_dplls(state, crtc);
+
+	MISSING_CASE(phy);
+
+	return 0;
+}
+
 static int icl_get_dplls(struct intel_atomic_state *state,
 			 struct intel_crtc *crtc,
 			 struct intel_encoder *encoder)
@@ -3943,6 +4058,7 @@ static const struct dpll_info icl_plls[] = {
 
 static const struct intel_dpll_mgr icl_pll_mgr = {
 	.dpll_info = icl_plls,
+	.compute_dplls = icl_compute_dplls,
 	.get_dplls = icl_get_dplls,
 	.put_dplls = icl_put_dplls,
 	.update_active_dpll = icl_update_active_dpll,
@@ -3959,6 +4075,7 @@ static const struct dpll_info ehl_plls[] = {
 
 static const struct intel_dpll_mgr ehl_pll_mgr = {
 	.dpll_info = ehl_plls,
+	.compute_dplls = icl_compute_dplls,
 	.get_dplls = icl_get_dplls,
 	.put_dplls = icl_put_dplls,
 	.update_ref_clks = icl_update_dpll_ref_clks,
@@ -3987,6 +4104,7 @@ static const struct dpll_info tgl_plls[] = {
 
 static const struct intel_dpll_mgr tgl_pll_mgr = {
 	.dpll_info = tgl_plls,
+	.compute_dplls = icl_compute_dplls,
 	.get_dplls = icl_get_dplls,
 	.put_dplls = icl_put_dplls,
 	.update_active_dpll = icl_update_active_dpll,
@@ -4003,6 +4121,7 @@ static const struct dpll_info rkl_plls[] = {
 
 static const struct intel_dpll_mgr rkl_pll_mgr = {
 	.dpll_info = rkl_plls,
+	.compute_dplls = icl_compute_dplls,
 	.get_dplls = icl_get_dplls,
 	.put_dplls = icl_put_dplls,
 	.update_ref_clks = icl_update_dpll_ref_clks,
@@ -4019,6 +4138,7 @@ static const struct dpll_info dg1_plls[] = {
 
 static const struct intel_dpll_mgr dg1_pll_mgr = {
 	.dpll_info = dg1_plls,
+	.compute_dplls = icl_compute_dplls,
 	.get_dplls = icl_get_dplls,
 	.put_dplls = icl_put_dplls,
 	.update_ref_clks = icl_update_dpll_ref_clks,
@@ -4035,6 +4155,7 @@ static const struct dpll_info adls_plls[] = {
 
 static const struct intel_dpll_mgr adls_pll_mgr = {
 	.dpll_info = adls_plls,
+	.compute_dplls = icl_compute_dplls,
 	.get_dplls = icl_get_dplls,
 	.put_dplls = icl_put_dplls,
 	.update_ref_clks = icl_update_dpll_ref_clks,
@@ -4054,6 +4175,7 @@ static const struct dpll_info adlp_plls[] = {
 
 static const struct intel_dpll_mgr adlp_pll_mgr = {
 	.dpll_info = adlp_plls,
+	.compute_dplls = icl_compute_dplls,
 	.get_dplls = icl_get_dplls,
 	.put_dplls = icl_put_dplls,
 	.update_active_dpll = icl_update_active_dpll,
@@ -4118,6 +4240,33 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
 	BUG_ON(dev_priv->dpll.num_shared_dpll > I915_NUM_PLLS);
 }
 
+/**
+ * intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination
+ * @state: atomic state
+ * @crtc: CRTC to compute DPLLs for
+ * @encoder: encoder
+ *
+ * This function computes the DPLL state for the given CRTC and encoder.
+ *
+ * The new configuration in the atomic commit @state is made effective by
+ * calling intel_shared_dpll_swap_state().
+ *
+ * Returns:
+ * 0 on success, negative error code on falure.
+ */
+int intel_compute_shared_dplls(struct intel_atomic_state *state,
+			       struct intel_crtc *crtc,
+			       struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
+
+	if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
+		return -EINVAL;
+
+	return dpll_mgr->compute_dplls(state, crtc, encoder);
+}
+
 /**
  * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
  * @state: atomic state
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index f7c96a1f13c89..02412bf7625ca 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -336,6 +336,9 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
 			bool state);
 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
+int intel_compute_shared_dplls(struct intel_atomic_state *state,
+			       struct intel_crtc *crtc,
+			       struct intel_encoder *encoder);
 int intel_reserve_shared_dplls(struct intel_atomic_state *state,
 			       struct intel_crtc *crtc,
 			       struct intel_encoder *encoder);
-- 
GitLab


From 6cb07d20317c77494fa4de572887e3dcdbf98b6d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 3 May 2022 21:22:19 +0300
Subject: [PATCH 0110/1731] drm/i915: Clean up DPLL related debugs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The debugs in lower level DPLL code don't really provide any
useful extra information AFAICS. Better just streamline the
code and just put the necessary debugs (to identify at which
step the modeset failed) into the higher level code. In
addition we'll get the full state dump as well, which should
hopefully have enough information to figure out what went wrong.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-4-ville.syrjala@linux.intel.com
---
 drivers/gpu/drm/i915/display/intel_dpll.c     | 75 +++++++------------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 48 +++---------
 2 files changed, 35 insertions(+), 88 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index c19fb075ee6e0..5262f16b45acf 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -954,21 +954,12 @@ static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_encoder *encoder =
 		intel_get_crtc_new_encoder(state, crtc_state);
-	int ret;
 
 	if (DISPLAY_VER(dev_priv) < 11 &&
 	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
 		return 0;
 
-	ret = intel_reserve_shared_dplls(state, crtc, encoder);
-	if (ret) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "failed to find PLL for pipe %c\n",
-			    pipe_name(crtc->pipe));
-		return ret;
-	}
-
-	return 0;
+	return intel_reserve_shared_dplls(state, crtc, encoder);
 }
 
 static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
@@ -1135,11 +1126,8 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
 
 	if (!crtc_state->clock_set &&
 	    !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
-				refclk, NULL, &crtc_state->dpll)) {
-		drm_err(&dev_priv->drm,
-			"Couldn't find PLL settings for mode!\n");
+				refclk, NULL, &crtc_state->dpll))
 		return -EINVAL;
-	}
 
 	ilk_compute_dpll(crtc_state, &crtc_state->dpll,
 			 &crtc_state->dpll);
@@ -1150,24 +1138,14 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
 static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
 				    struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
-	int ret;
 
 	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
 	if (!crtc_state->has_pch_encoder)
 		return 0;
 
-	ret = intel_reserve_shared_dplls(state, crtc, NULL);
-	if (ret) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "failed to find PLL for pipe %c\n",
-			    pipe_name(crtc->pipe));
-		return ret;
-	}
-
-	return 0;
+	return intel_reserve_shared_dplls(state, crtc, NULL);
 }
 
 void vlv_compute_dpll(struct intel_crtc_state *crtc_state)
@@ -1208,7 +1186,6 @@ void chv_compute_dpll(struct intel_crtc_state *crtc_state)
 static int chv_crtc_compute_clock(struct intel_atomic_state *state,
 				  struct intel_crtc *crtc)
 {
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	const struct intel_limit *limit = &intel_limits_chv;
@@ -1216,10 +1193,8 @@ static int chv_crtc_compute_clock(struct intel_atomic_state *state,
 
 	if (!crtc_state->clock_set &&
 	    !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
-				refclk, NULL, &crtc_state->dpll)) {
-		drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
+				refclk, NULL, &crtc_state->dpll))
 		return -EINVAL;
-	}
 
 	chv_compute_dpll(crtc_state);
 
@@ -1229,7 +1204,6 @@ static int chv_crtc_compute_clock(struct intel_atomic_state *state,
 static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
 				  struct intel_crtc *crtc)
 {
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	const struct intel_limit *limit = &intel_limits_vlv;
@@ -1238,7 +1212,6 @@ static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
 	if (!crtc_state->clock_set &&
 	    !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
 				refclk, NULL, &crtc_state->dpll)) {
-		drm_err(&i915->drm,  "Couldn't find PLL settings for mode!\n");
 		return -EINVAL;
 	}
 
@@ -1280,11 +1253,8 @@ static int g4x_crtc_compute_clock(struct intel_atomic_state *state,
 
 	if (!crtc_state->clock_set &&
 	    !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
-				refclk, NULL, &crtc_state->dpll)) {
-		drm_err(&dev_priv->drm,
-			"Couldn't find PLL settings for mode!\n");
+				refclk, NULL, &crtc_state->dpll))
 		return -EINVAL;
-	}
 
 	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
 			  &crtc_state->dpll);
@@ -1316,11 +1286,8 @@ static int pnv_crtc_compute_clock(struct intel_atomic_state *state,
 
 	if (!crtc_state->clock_set &&
 	    !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
-				refclk, NULL, &crtc_state->dpll)) {
-		drm_err(&dev_priv->drm,
-			"Couldn't find PLL settings for mode!\n");
+				refclk, NULL, &crtc_state->dpll))
 		return -EINVAL;
-	}
 
 	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
 			  &crtc_state->dpll);
@@ -1352,11 +1319,8 @@ static int i9xx_crtc_compute_clock(struct intel_atomic_state *state,
 
 	if (!crtc_state->clock_set &&
 	    !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
-				 refclk, NULL, &crtc_state->dpll)) {
-		drm_err(&dev_priv->drm,
-			"Couldn't find PLL settings for mode!\n");
+				 refclk, NULL, &crtc_state->dpll))
 		return -EINVAL;
-	}
 
 	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
 			  &crtc_state->dpll);
@@ -1390,11 +1354,8 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
 
 	if (!crtc_state->clock_set &&
 	    !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
-				 refclk, NULL, &crtc_state->dpll)) {
-		drm_err(&dev_priv->drm,
-			"Couldn't find PLL settings for mode!\n");
+				 refclk, NULL, &crtc_state->dpll))
 		return -EINVAL;
-	}
 
 	i8xx_compute_dpll(crtc_state, &crtc_state->dpll,
 			  &crtc_state->dpll);
@@ -1446,6 +1407,7 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
 	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
+	int ret;
 
 	drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
 
@@ -1458,7 +1420,14 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
 	if (!crtc_state->hw.enable)
 		return 0;
 
-	return i915->dpll_funcs->crtc_compute_clock(state, crtc);
+	ret = i915->dpll_funcs->crtc_compute_clock(state, crtc);
+	if (ret) {
+		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n",
+			    crtc->base.base.id, crtc->base.name);
+		return ret;
+	}
+
+	return 0;
 }
 
 int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
@@ -1467,6 +1436,7 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
 	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
+	int ret;
 
 	drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
 
@@ -1479,7 +1449,14 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
 	if (!i915->dpll_funcs->crtc_get_shared_dpll)
 		return 0;
 
-	return i915->dpll_funcs->crtc_get_shared_dpll(state, crtc);
+	ret = i915->dpll_funcs->crtc_get_shared_dpll(state, crtc);
+	if (ret) {
+		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",
+			    crtc->base.base.id, crtc->base.name);
+		return ret;
+	}
+
+	return 0;
 }
 
 void
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 4c5c3439b745a..64708e874b135 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1603,10 +1603,8 @@ skip_remaining_dividers:
 			break;
 	}
 
-	if (!ctx.p) {
-		DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
+	if (!ctx.p)
 		return -EINVAL;
-	}
 
 	/*
 	 * gcc incorrectly analyses that these can be used without being
@@ -2145,19 +2143,14 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
 			  struct dpll *clk_div)
 {
 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	/* Calculate HDMI div */
 	/*
 	 * FIXME: tie the following calculation into
 	 * i9xx_crtc_compute_clock
 	 */
-	if (!bxt_find_best_dpll(crtc_state, clk_div)) {
-		drm_dbg(&i915->drm, "no PLL dividers found for clock %d pipe %c\n",
-			crtc_state->port_clock,
-			pipe_name(crtc->pipe));
+	if (!bxt_find_best_dpll(crtc_state, clk_div))
 		return -EINVAL;
-	}
 
 	drm_WARN_ON(&i915->drm, clk_div->m1 != 2);
 
@@ -2879,11 +2872,8 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
 
 	ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
 				       pll_state, is_dkl);
-	if (ret) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "Failed to find divisors for clock %d\n", clock);
+	if (ret)
 		return ret;
-	}
 
 	m1div = 2;
 	m2div_int = dco_khz / (refclk_khz * m1div);
@@ -2893,12 +2883,8 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
 			m2div_int = dco_khz / (refclk_khz * m1div);
 		}
 
-		if (m2div_int > 255) {
-			drm_dbg_kms(&dev_priv->drm,
-				    "Failed to find mdiv for clock %d\n",
-				    clock);
+		if (m2div_int > 255)
 			return -EINVAL;
-		}
 	}
 	m2div_rem = dco_khz % (refclk_khz * m1div);
 
@@ -3206,11 +3192,8 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
 	else
 		ret = icl_calc_dp_combo_pll(crtc_state, &pll_params);
 
-	if (ret) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "Could not calculate combo PHY PLL state.\n");
+	if (ret)
 		return ret;
-	}
 
 	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
 
@@ -3265,12 +3248,8 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
 	port_dpll->pll = intel_find_shared_dpll(state, crtc,
 						&port_dpll->hw_state,
 						dpll_mask);
-	if (!port_dpll->pll) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "No combo PHY PLL found for [ENCODER:%d:%s]\n",
-			    encoder->base.base.id, encoder->base.name);
+	if (!port_dpll->pll)
 		return -EINVAL;
-	}
 
 	intel_reference_shared_dpll(state, crtc,
 				    port_dpll->pll, &port_dpll->hw_state);
@@ -3293,21 +3272,15 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
 
 	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
 	ret = icl_calc_tbt_pll(crtc_state, &pll_params);
-	if (ret) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "Could not calculate TBT PLL state.\n");
+	if (ret)
 		return ret;
-	}
 
 	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
 
 	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
 	ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
-	if (ret) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "Could not calculate MG PHY PLL state.\n");
+	if (ret)
 		return ret;
-	}
 
 	return 0;
 }
@@ -3328,10 +3301,8 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
 	port_dpll->pll = intel_find_shared_dpll(state, crtc,
 						&port_dpll->hw_state,
 						BIT(DPLL_ID_ICL_TBTPLL));
-	if (!port_dpll->pll) {
-		drm_dbg_kms(&dev_priv->drm, "No TBT-ALT PLL found\n");
+	if (!port_dpll->pll)
 		return -EINVAL;
-	}
 	intel_reference_shared_dpll(state, crtc,
 				    port_dpll->pll, &port_dpll->hw_state);
 
@@ -3344,7 +3315,6 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
 						BIT(dpll_id));
 	if (!port_dpll->pll) {
 		ret = -EINVAL;
-		drm_dbg_kms(&dev_priv->drm, "No MG PHY PLL found\n");
 		goto err_unreference_tbt_pll;
 	}
 	intel_reference_shared_dpll(state, crtc,
-- 
GitLab


From 0e5397d8c9fe2a2e4fcc8d98cba4a12511a03267 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 3 May 2022 21:22:21 +0300
Subject: [PATCH 0111/1731] drm/i915: Extract PIPE_CONF_CHECK_TIMINGS()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Deduplicate the crtc_ timings comparisons.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-6-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 45 ++++++++------------
 1 file changed, 18 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9f105250f4749..87891dbda56a4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6077,6 +6077,21 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	} \
 } while (0)
 
+#define PIPE_CONF_CHECK_TIMINGS(name) do { \
+	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
+	PIPE_CONF_CHECK_I(name.crtc_htotal); \
+	PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
+	PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
+	PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
+	PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
+	PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
+	PIPE_CONF_CHECK_I(name.crtc_vtotal); \
+	PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
+	PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
+	PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
+	PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
+} while (0)
+
 /* This is required for BDW+ where there is only one set of registers for
  * switching between high and low RR.
  * This macro can be used whenever a comparison has to be made between one
@@ -6194,33 +6209,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_I(framestart_delay);
 	PIPE_CONF_CHECK_I(msa_timing_delay);
 
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start);
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end);
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start);
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end);
-
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start);
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end);
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start);
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end);
-
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
-
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
+	PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
+	PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
 
 	PIPE_CONF_CHECK_I(pixel_multiplier);
 
@@ -6396,6 +6386,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 #undef PIPE_CONF_CHECK_FLAGS
 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
 #undef PIPE_CONF_CHECK_COLOR_LUT
+#undef PIPE_CONF_CHECK_TIMINGS
 #undef PIPE_CONF_QUIRK
 
 	return ret;
-- 
GitLab


From 3951270abfd229e3e17c991942cd111b66454f97 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 3 May 2022 21:22:22 +0300
Subject: [PATCH 0112/1731] drm/i915: Extract PIPE_CONF_CHECK_RECT()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Deduplicate the drm_rect comparisons.

We also drop the redundant pch_pfit.enabled check since the
pch_pfit.dst rectanble will be zeroed anyway when the pfit
is not enabled.

v2: Document why we drop the enabled check (Jani)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-7-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 87891dbda56a4..ac3b9bcf83783 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6092,6 +6092,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
 } while (0)
 
+#define PIPE_CONF_CHECK_RECT(name) do { \
+	PIPE_CONF_CHECK_I(name.x1); \
+	PIPE_CONF_CHECK_I(name.x2); \
+	PIPE_CONF_CHECK_I(name.y1); \
+	PIPE_CONF_CHECK_I(name.y2); \
+} while (0)
+
 /* This is required for BDW+ where there is only one set of registers for
  * switching between high and low RR.
  * This macro can be used whenever a comparison has to be made between one
@@ -6254,18 +6261,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
 
 	if (!fastset) {
-		PIPE_CONF_CHECK_I(pipe_src.x1);
-		PIPE_CONF_CHECK_I(pipe_src.y1);
-		PIPE_CONF_CHECK_I(pipe_src.x2);
-		PIPE_CONF_CHECK_I(pipe_src.y2);
+		PIPE_CONF_CHECK_RECT(pipe_src);
 
 		PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
-		if (current_config->pch_pfit.enabled) {
-			PIPE_CONF_CHECK_I(pch_pfit.dst.x1);
-			PIPE_CONF_CHECK_I(pch_pfit.dst.y1);
-			PIPE_CONF_CHECK_I(pch_pfit.dst.x2);
-			PIPE_CONF_CHECK_I(pch_pfit.dst.y2);
-		}
+		PIPE_CONF_CHECK_RECT(pch_pfit.dst);
 
 		PIPE_CONF_CHECK_I(scaler_state.scaler_id);
 		PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
@@ -6387,6 +6386,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
 #undef PIPE_CONF_CHECK_COLOR_LUT
 #undef PIPE_CONF_CHECK_TIMINGS
+#undef PIPE_CONF_CHECK_RECT
 #undef PIPE_CONF_QUIRK
 
 	return ret;
-- 
GitLab


From 3d140a3d8816082f9732d6fccb81dc18823e03b3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 3 May 2022 21:22:23 +0300
Subject: [PATCH 0113/1731] drm/i915: Adjust intel_modeset_pipe_config() & co.
 calling convention
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Use the state+crtc calling convention for intel_modeset_pipe_config()
and othere related functions. Many of these need the full atomic state
anyway so passing it all the way through is just nicer than having to
worry about whether it can actually be extracted from eg. the crtc
state passed in.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-8-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 48 ++++++++++----------
 1 file changed, 25 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ac3b9bcf83783..7ba3229d86c1e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2811,9 +2811,11 @@ static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
 	return 0;
 }
 
-static int intel_crtc_compute_config(struct intel_crtc *crtc,
-				     struct intel_crtc_state *crtc_state)
+static int intel_crtc_compute_config(struct intel_atomic_state *state,
+				     struct intel_crtc *crtc)
 {
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 	int ret;
 
 	ret = intel_crtc_compute_pipe_src(crtc_state);
@@ -5056,11 +5058,12 @@ compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
 }
 
 static int
-compute_baseline_pipe_bpp(struct intel_crtc *crtc,
-			  struct intel_crtc_state *pipe_config)
+compute_baseline_pipe_bpp(struct intel_atomic_state *state,
+			  struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	struct drm_atomic_state *state = pipe_config->uapi.state;
+	struct intel_crtc_state *pipe_config =
+		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_connector *connector;
 	struct drm_connector_state *connector_state;
 	int bpp, i;
@@ -5076,7 +5079,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
 	pipe_config->pipe_bpp = bpp;
 
 	/* Clamp display bpp to connector max bpp */
-	for_each_new_connector_in_state(state, connector, connector_state, i) {
+	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
 		int ret;
 
 		if (connector_state->crtc != &crtc->base)
@@ -5636,18 +5639,18 @@ intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
 
 static int
 intel_modeset_pipe_config(struct intel_atomic_state *state,
-			  struct intel_crtc_state *pipe_config)
+			  struct intel_crtc *crtc)
 {
-	struct drm_crtc *crtc = pipe_config->uapi.crtc;
-	struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	struct intel_crtc_state *pipe_config =
+		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_connector *connector;
 	struct drm_connector_state *connector_state;
 	int pipe_src_w, pipe_src_h;
 	int base_bpp, ret, i;
 	bool retry = true;
 
-	pipe_config->cpu_transcoder =
-		(enum transcoder) to_intel_crtc(crtc)->pipe;
+	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
 
 	pipe_config->framestart_delay = 1;
 
@@ -5664,8 +5667,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 	      (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
 		pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
 
-	ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
-					pipe_config);
+	ret = compute_baseline_pipe_bpp(state, crtc);
 	if (ret)
 		return ret;
 
@@ -5688,10 +5690,10 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 		struct intel_encoder *encoder =
 			to_intel_encoder(connector_state->best_encoder);
 
-		if (connector_state->crtc != crtc)
+		if (connector_state->crtc != &crtc->base)
 			continue;
 
-		if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
+		if (!check_single_encoder_cloning(state, crtc, encoder)) {
 			drm_dbg_kms(&i915->drm,
 				    "rejecting invalid cloning configuration\n");
 			return -EINVAL;
@@ -5726,7 +5728,7 @@ encoder_retry:
 		struct intel_encoder *encoder =
 			to_intel_encoder(connector_state->best_encoder);
 
-		if (connector_state->crtc != crtc)
+		if (connector_state->crtc != &crtc->base)
 			continue;
 
 		ret = encoder->compute_config(encoder, pipe_config,
@@ -5745,7 +5747,7 @@ encoder_retry:
 		pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
 			* pipe_config->pixel_multiplier;
 
-	ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
+	ret = intel_crtc_compute_config(state, crtc);
 	if (ret == -EDEADLK)
 		return ret;
 	if (ret == -EAGAIN) {
@@ -5776,11 +5778,11 @@ encoder_retry:
 }
 
 static int
-intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state)
+intel_modeset_pipe_config_late(struct intel_atomic_state *state,
+			       struct intel_crtc *crtc)
 {
-	struct intel_atomic_state *state =
-		to_intel_atomic_state(crtc_state->uapi.state);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_connector_state *conn_state;
 	struct drm_connector *connector;
 	int i;
@@ -7724,7 +7726,7 @@ static int intel_atomic_check(struct drm_device *dev,
 		if (!new_crtc_state->hw.enable)
 			continue;
 
-		ret = intel_modeset_pipe_config(state, new_crtc_state);
+		ret = intel_modeset_pipe_config(state, crtc);
 		if (ret)
 			goto fail;
 
@@ -7738,7 +7740,7 @@ static int intel_atomic_check(struct drm_device *dev,
 		if (!intel_crtc_needs_modeset(new_crtc_state))
 			continue;
 
-		ret = intel_modeset_pipe_config_late(new_crtc_state);
+		ret = intel_modeset_pipe_config_late(state, crtc);
 		if (ret)
 			goto fail;
 
-- 
GitLab


From aa71f9870efea70b38b17c3d2af870530fcd02e3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 3 May 2022 21:22:24 +0300
Subject: [PATCH 0114/1731] drm/i915: s/pipe_config/crtc_state/
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Rename some of the 'pipe_config's to the more modern
'crtc_state'.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-9-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 62 ++++++++++----------
 1 file changed, 31 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7ba3229d86c1e..58d1a3cdfd260 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5017,10 +5017,10 @@ static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
 
 static int
 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
-		      struct intel_crtc_state *pipe_config)
+		      struct intel_crtc_state *crtc_state)
 {
 	struct drm_connector *connector = conn_state->connector;
-	struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
+	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 	const struct drm_display_info *info = &connector->display_info;
 	int bpp;
 
@@ -5042,16 +5042,16 @@ compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
 		return -EINVAL;
 	}
 
-	if (bpp < pipe_config->pipe_bpp) {
+	if (bpp < crtc_state->pipe_bpp) {
 		drm_dbg_kms(&i915->drm,
 			    "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
 			    "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
 			    connector->base.id, connector->name,
 			    bpp, 3 * info->bpc,
 			    3 * conn_state->max_requested_bpc,
-			    pipe_config->pipe_bpp);
+			    crtc_state->pipe_bpp);
 
-		pipe_config->pipe_bpp = bpp;
+		crtc_state->pipe_bpp = bpp;
 	}
 
 	return 0;
@@ -5062,7 +5062,7 @@ compute_baseline_pipe_bpp(struct intel_atomic_state *state,
 			  struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	struct intel_crtc_state *pipe_config =
+	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_connector *connector;
 	struct drm_connector_state *connector_state;
@@ -5076,7 +5076,7 @@ compute_baseline_pipe_bpp(struct intel_atomic_state *state,
 	else
 		bpp = 8*3;
 
-	pipe_config->pipe_bpp = bpp;
+	crtc_state->pipe_bpp = bpp;
 
 	/* Clamp display bpp to connector max bpp */
 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
@@ -5085,7 +5085,7 @@ compute_baseline_pipe_bpp(struct intel_atomic_state *state,
 		if (connector_state->crtc != &crtc->base)
 			continue;
 
-		ret = compute_sink_pipe_bpp(connector_state, pipe_config);
+		ret = compute_sink_pipe_bpp(connector_state, crtc_state);
 		if (ret)
 			return ret;
 	}
@@ -5642,7 +5642,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 			  struct intel_crtc *crtc)
 {
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-	struct intel_crtc_state *pipe_config =
+	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_connector *connector;
 	struct drm_connector_state *connector_state;
@@ -5650,28 +5650,28 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 	int base_bpp, ret, i;
 	bool retry = true;
 
-	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
+	crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
 
-	pipe_config->framestart_delay = 1;
+	crtc_state->framestart_delay = 1;
 
 	/*
 	 * Sanitize sync polarity flags based on requested ones. If neither
 	 * positive or negative polarity is requested, treat this as meaning
 	 * negative polarity.
 	 */
-	if (!(pipe_config->hw.adjusted_mode.flags &
+	if (!(crtc_state->hw.adjusted_mode.flags &
 	      (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
-		pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
+		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
 
-	if (!(pipe_config->hw.adjusted_mode.flags &
+	if (!(crtc_state->hw.adjusted_mode.flags &
 	      (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
-		pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
+		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
 
 	ret = compute_baseline_pipe_bpp(state, crtc);
 	if (ret)
 		return ret;
 
-	base_bpp = pipe_config->pipe_bpp;
+	base_bpp = crtc_state->pipe_bpp;
 
 	/*
 	 * Determine the real pipe dimensions. Note that stereo modes can
@@ -5681,9 +5681,9 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 	 * computation to clearly distinguish it from the adjusted mode, which
 	 * can be changed by the connectors in the below retry loop.
 	 */
-	drm_mode_get_hv_timing(&pipe_config->hw.mode,
+	drm_mode_get_hv_timing(&crtc_state->hw.mode,
 			       &pipe_src_w, &pipe_src_h);
-	drm_rect_init(&pipe_config->pipe_src, 0, 0,
+	drm_rect_init(&crtc_state->pipe_src, 0, 0,
 		      pipe_src_w, pipe_src_h);
 
 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
@@ -5704,20 +5704,20 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 		 * hooks so that the hooks can use this information safely.
 		 */
 		if (encoder->compute_output_type)
-			pipe_config->output_types |=
-				BIT(encoder->compute_output_type(encoder, pipe_config,
+			crtc_state->output_types |=
+				BIT(encoder->compute_output_type(encoder, crtc_state,
 								 connector_state));
 		else
-			pipe_config->output_types |= BIT(encoder->type);
+			crtc_state->output_types |= BIT(encoder->type);
 	}
 
 encoder_retry:
 	/* Ensure the port clock defaults are reset when retrying. */
-	pipe_config->port_clock = 0;
-	pipe_config->pixel_multiplier = 1;
+	crtc_state->port_clock = 0;
+	crtc_state->pixel_multiplier = 1;
 
 	/* Fill in default crtc timings, allow encoders to overwrite them. */
-	drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
+	drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,
 			      CRTC_STEREO_DOUBLE);
 
 	/* Pass our mode to the connectors and the CRTC to give them a chance to
@@ -5731,7 +5731,7 @@ encoder_retry:
 		if (connector_state->crtc != &crtc->base)
 			continue;
 
-		ret = encoder->compute_config(encoder, pipe_config,
+		ret = encoder->compute_config(encoder, crtc_state,
 					      connector_state);
 		if (ret == -EDEADLK)
 			return ret;
@@ -5743,9 +5743,9 @@ encoder_retry:
 
 	/* Set default port clock if not overwritten by the encoder. Needs to be
 	 * done afterwards in case the encoder adjusts the mode. */
-	if (!pipe_config->port_clock)
-		pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
-			* pipe_config->pixel_multiplier;
+	if (!crtc_state->port_clock)
+		crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
+			* crtc_state->pixel_multiplier;
 
 	ret = intel_crtc_compute_config(state, crtc);
 	if (ret == -EDEADLK)
@@ -5768,11 +5768,11 @@ encoder_retry:
 	 * only enable it on 6bpc panels and when its not a compliance
 	 * test requesting 6bpc video pattern.
 	 */
-	pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
-		!pipe_config->dither_force_disable;
+	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
+		!crtc_state->dither_force_disable;
 	drm_dbg_kms(&i915->drm,
 		    "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
-		    base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
+		    base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
 
 	return 0;
 }
-- 
GitLab


From 58ae532ee875783503428610ac0f5d80e73009a7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 3 May 2022 21:22:25 +0300
Subject: [PATCH 0115/1731] drm/i915: Improve modeset debugs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Use the "[CRTC:%d:%s]'/etc. format for some of the modeset debugs
so we know more about what has happened during the modeset state
computation.

Also tweak the connector bpp debug message a bit to make it less
confusing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-10-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++++++-------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 58d1a3cdfd260..d209e0bd663af 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5044,8 +5044,8 @@ compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
 
 	if (bpp < crtc_state->pipe_bpp) {
 		drm_dbg_kms(&i915->drm,
-			    "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
-			    "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
+			    "[CONNECTOR:%d:%s] Limiting display bpp to %d "
+			    "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
 			    connector->base.id, connector->name,
 			    bpp, 3 * info->bpc,
 			    3 * conn_state->max_requested_bpc,
@@ -5695,7 +5695,8 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 
 		if (!check_single_encoder_cloning(state, crtc, encoder)) {
 			drm_dbg_kms(&i915->drm,
-				    "rejecting invalid cloning configuration\n");
+				    "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
+				    encoder->base.base.id, encoder->base.name);
 			return -EINVAL;
 		}
 
@@ -5736,7 +5737,8 @@ encoder_retry:
 		if (ret == -EDEADLK)
 			return ret;
 		if (ret < 0) {
-			drm_dbg_kms(&i915->drm, "Encoder config failure: %d\n", ret);
+			drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n",
+				    encoder->base.base.id, encoder->base.name, ret);
 			return ret;
 		}
 	}
@@ -5752,15 +5754,18 @@ encoder_retry:
 		return ret;
 	if (ret == -EAGAIN) {
 		if (drm_WARN(&i915->drm, !retry,
-			     "loop in pipe configuration computation\n"))
+			     "[CRTC:%d:%s] loop in pipe configuration computation\n",
+			     crtc->base.base.id, crtc->base.name))
 			return -EINVAL;
 
-		drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");
+		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n",
+			    crtc->base.base.id, crtc->base.name);
 		retry = false;
 		goto encoder_retry;
 	}
 	if (ret < 0) {
-		drm_dbg_kms(&i915->drm, "CRTC config failure: %d\n", ret);
+		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
+			    crtc->base.base.id, crtc->base.name, ret);
 		return ret;
 	}
 
@@ -5771,7 +5776,8 @@ encoder_retry:
 	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
 		!crtc_state->dither_force_disable;
 	drm_dbg_kms(&i915->drm,
-		    "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
+		    "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
+		    crtc->base.base.id, crtc->base.name,
 		    base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
 
 	return 0;
-- 
GitLab


From f2206df8ec862073995f5d27f0f55f698843a9b8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 3 May 2022 21:22:36 +0300
Subject: [PATCH 0116/1731] drm/i915: Check hw.enable and hw.active in
 intel_pipe_config_compare()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Don't see a real reson not to check hw.active and hw.enable in
intel_pipe_config_compare(). We do have some checks for them
at a higher level, but I think better check them also in
intel_pipe_config_compare() in case something else doesn't
do a thorough enough job.

Also shuffle the mst_master_transcoder check next to the
cpu_transcoder check for a bit of consistency.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-21-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d209e0bd663af..6f2846c973b2e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6203,7 +6203,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 #define PIPE_CONF_QUIRK(quirk) \
 	((current_config->quirks | pipe_config->quirks) & (quirk))
 
+	PIPE_CONF_CHECK_I(hw.enable);
+	PIPE_CONF_CHECK_I(hw.active);
+
 	PIPE_CONF_CHECK_I(cpu_transcoder);
+	PIPE_CONF_CHECK_I(mst_master_transcoder);
 
 	PIPE_CONF_CHECK_BOOL(has_pch_encoder);
 	PIPE_CONF_CHECK_I(fdi_lanes);
@@ -6376,8 +6380,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_I(splitter.link_count);
 	PIPE_CONF_CHECK_I(splitter.pixel_overlap);
 
-	PIPE_CONF_CHECK_I(mst_master_transcoder);
-
 	PIPE_CONF_CHECK_BOOL(vrr.enable);
 	PIPE_CONF_CHECK_I(vrr.vmin);
 	PIPE_CONF_CHECK_I(vrr.vmax);
-- 
GitLab


From 4f543d664cec7e9b490bca55f57151afe6f5cf47 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 3 May 2022 21:22:39 +0300
Subject: [PATCH 0117/1731] drm/i915: Require an exact DP link freq match for
 the DG2 PLL
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

No idea why the DG2 PLL DP link frequency calculation is allowing
a non-exact match. That makes no sense so get rid of it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-24-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index cc1270978b67e..b48f42f1832a9 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -629,7 +629,7 @@ int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
 		return -EINVAL;
 
 	for (i = 0; tables[i]; i++) {
-		if (crtc_state->port_clock <= tables[i]->clock) {
+		if (crtc_state->port_clock == tables[i]->clock) {
 			crtc_state->mpllb_state = *tables[i];
 			return 0;
 		}
-- 
GitLab


From 8b449f1c44d1f921240da6a3e7fc4030966abbff Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Fri, 27 May 2022 09:33:47 -0700
Subject: [PATCH 0118/1731] drm/i915/pvc: Extract stepping information from PCI
 revid

For PVC, the base die and compute tile have separate stepping values
that we need to track; we'll use the existing graphics_step field to
represent the compute tile stepping and add a new 'basedie_step' field.

Unlike past platforms, steppings for these components are represented by
specific bitfields within the PCI revision ID, and we shouldn't make
assumptions about the non-CT, non-BD bits staying 0.  Let's update our
stepping code accordingly.

Bspec: 44484
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220527163348.1936146-2-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/i915_drv.h   | 13 ++++++
 drivers/gpu/drm/i915/intel_step.c | 70 ++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_step.h |  4 +-
 3 files changed, 85 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 74b3caccd8390..ec1b3484fdafa 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -943,6 +943,7 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
+#define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step)
 
 #define IS_DISPLAY_STEP(__i915, since, until) \
 	(drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
@@ -956,6 +957,10 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
 	(drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
 	 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))
 
+#define IS_BASEDIE_STEP(__i915, since, until) \
+	(drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \
+	 INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until))
+
 static __always_inline unsigned int
 __platform_mask_index(const struct intel_runtime_info *info,
 		      enum intel_platform p)
@@ -1208,6 +1213,14 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	(IS_DG2(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))
 
+#define IS_PVC_BD_STEP(__i915, since, until) \
+	(IS_PONTEVECCHIO(__i915) && \
+	 IS_BASEDIE_STEP(__i915, since, until))
+
+#define IS_PVC_CT_STEP(__i915, since, until) \
+	(IS_PONTEVECCHIO(__i915) && \
+	 IS_GRAPHICS_STEP(__i915, since, until))
+
 #define IS_LP(dev_priv)		(INTEL_INFO(dev_priv)->is_lp)
 #define IS_GEN9_LP(dev_priv)	(GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
 #define IS_GEN9_BC(dev_priv)	(GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 74e8e4680028a..42b3133d8387a 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -135,6 +135,8 @@ static const struct intel_step_info adlp_n_revids[] = {
 	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_D0 },
 };
 
+static void pvc_step_init(struct drm_i915_private *i915, int pci_revid);
+
 void intel_step_init(struct drm_i915_private *i915)
 {
 	const struct intel_step_info *revids = NULL;
@@ -142,7 +144,10 @@ void intel_step_init(struct drm_i915_private *i915)
 	int revid = INTEL_REVID(i915);
 	struct intel_step_info step = {};
 
-	if (IS_DG2_G10(i915)) {
+	if (IS_PONTEVECCHIO(i915)) {
+		pvc_step_init(i915, revid);
+		return;
+	} else if (IS_DG2_G10(i915)) {
 		revids = dg2_g10_revid_step_tbl;
 		size = ARRAY_SIZE(dg2_g10_revid_step_tbl);
 	} else if (IS_DG2_G11(i915)) {
@@ -235,6 +240,69 @@ void intel_step_init(struct drm_i915_private *i915)
 	RUNTIME_INFO(i915)->step = step;
 }
 
+#define PVC_BD_REVID	GENMASK(5, 3)
+#define PVC_CT_REVID	GENMASK(2, 0)
+
+static const int pvc_bd_subids[] = {
+	[0x0] = STEP_A0,
+	[0x3] = STEP_B0,
+	[0x4] = STEP_B1,
+	[0x5] = STEP_B3,
+};
+
+static const int pvc_ct_subids[] = {
+	[0x3] = STEP_A0,
+	[0x5] = STEP_B0,
+	[0x6] = STEP_B1,
+	[0x7] = STEP_C0,
+};
+
+static int
+pvc_step_lookup(struct drm_i915_private *i915, const char *type,
+		const int *table, int size, int subid)
+{
+	if (subid < size && table[subid] != STEP_NONE)
+		return table[subid];
+
+	drm_warn(&i915->drm, "Unknown %s id 0x%02x\n", type, subid);
+
+	/*
+	 * As on other platforms, try to use the next higher ID if we land on a
+	 * gap in the table.
+	 */
+	while (subid < size && table[subid] == STEP_NONE)
+		subid++;
+
+	if (subid < size) {
+		drm_dbg(&i915->drm, "Using steppings for %s id 0x%02x\n",
+			type, subid);
+		return table[subid];
+	}
+
+	drm_dbg(&i915->drm, "Using future steppings\n");
+	return STEP_FUTURE;
+}
+
+/*
+ * PVC needs special handling since we don't lookup the
+ * revid in a table, but rather specific bitfields within
+ * the revid for various components.
+ */
+static void pvc_step_init(struct drm_i915_private *i915, int pci_revid)
+{
+	int ct_subid, bd_subid;
+
+	bd_subid = FIELD_GET(PVC_BD_REVID, pci_revid);
+	ct_subid = FIELD_GET(PVC_CT_REVID, pci_revid);
+
+	RUNTIME_INFO(i915)->step.basedie_step =
+		pvc_step_lookup(i915, "Base Die", pvc_bd_subids,
+				ARRAY_SIZE(pvc_bd_subids), bd_subid);
+	RUNTIME_INFO(i915)->step.graphics_step =
+		pvc_step_lookup(i915, "Compute Tile", pvc_ct_subids,
+				ARRAY_SIZE(pvc_ct_subids), ct_subid);
+}
+
 #define STEP_NAME_CASE(name)	\
 	case STEP_##name:	\
 		return #name;
diff --git a/drivers/gpu/drm/i915/intel_step.h b/drivers/gpu/drm/i915/intel_step.h
index d71a99bd51793..a6b12bfa9744a 100644
--- a/drivers/gpu/drm/i915/intel_step.h
+++ b/drivers/gpu/drm/i915/intel_step.h
@@ -11,9 +11,10 @@
 struct drm_i915_private;
 
 struct intel_step_info {
-	u8 graphics_step;
+	u8 graphics_step;	/* Represents the compute tile on Xe_HPC */
 	u8 display_step;
 	u8 media_step;
+	u8 basedie_step;
 };
 
 #define STEP_ENUM_VAL(name)  STEP_##name,
@@ -25,6 +26,7 @@ struct intel_step_info {
 	func(B0)			\
 	func(B1)			\
 	func(B2)			\
+	func(B3)			\
 	func(C0)			\
 	func(C1)			\
 	func(D0)			\
-- 
GitLab


From ce581ae142e24deb27905840fb720fee9b38d7a4 Mon Sep 17 00:00:00 2001
From: Stuart Summers <stuart.summers@intel.com>
Date: Fri, 27 May 2022 09:33:48 -0700
Subject: [PATCH 0119/1731] drm/i915/pvc: Add initial PVC workarounds

Bspec: 64027
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220527163348.1936146-3-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/intel_engine_regs.h |  5 +-
 drivers/gpu/drm/i915/gt/intel_gt_regs.h     |  3 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 61 ++++++++++++++++++---
 drivers/gpu/drm/i915/intel_pm.c             | 16 +++++-
 4 files changed, 73 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
index 75a0c55c5aa5d..44de10cf7837f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -196,6 +196,7 @@
 #define RING_CTX_TIMESTAMP(base)		_MMIO((base) + 0x3a8) /* gen8+ */
 #define RING_PREDICATE_RESULT(base)		_MMIO((base) + 0x3b8)
 #define RING_FORCE_TO_NONPRIV(base, i)		_MMIO(((base) + 0x4D0) + (i) * 4)
+#define   RING_FORCE_TO_NONPRIV_DENY		REG_BIT(30)
 #define   RING_FORCE_TO_NONPRIV_ADDRESS_MASK	REG_GENMASK(25, 2)
 #define   RING_FORCE_TO_NONPRIV_ACCESS_RW	(0 << 28)    /* CFL+ & Gen11+ */
 #define   RING_FORCE_TO_NONPRIV_ACCESS_RD	(1 << 28)
@@ -208,7 +209,9 @@
 #define   RING_FORCE_TO_NONPRIV_RANGE_64	(3 << 0)
 #define   RING_FORCE_TO_NONPRIV_RANGE_MASK	(3 << 0)
 #define   RING_FORCE_TO_NONPRIV_MASK_VALID	\
-	(RING_FORCE_TO_NONPRIV_RANGE_MASK | RING_FORCE_TO_NONPRIV_ACCESS_MASK)
+	(RING_FORCE_TO_NONPRIV_RANGE_MASK | \
+	 RING_FORCE_TO_NONPRIV_ACCESS_MASK | \
+	 RING_FORCE_TO_NONPRIV_DENY)
 #define   RING_MAX_NONPRIV_SLOTS  12
 
 #define RING_EXECLIST_SQ_CONTENTS(base)		_MMIO((base) + 0x510)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index b4642dcc192fc..58e9b464d564c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1070,8 +1070,9 @@
 
 #define GEN10_CACHE_MODE_SS			_MMIO(0xe420)
 #define   ENABLE_EU_COUNT_FOR_TDL_FLUSH		REG_BIT(10)
-#define   ENABLE_PREFETCH_INTO_IC		REG_BIT(3)
+#define   DISABLE_ECC				REG_BIT(5)
 #define   FLOAT_BLEND_OPTIMIZATION_ENABLE	REG_BIT(4)
+#define   ENABLE_PREFETCH_INTO_IC		REG_BIT(3)
 
 #define EU_PERF_CNTL0				_MMIO(0xe458)
 #define EU_PERF_CNTL4				_MMIO(0xe45c)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 73b59ea6fd3bc..a604bc7c0701f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -776,7 +776,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 	if (engine->class != RENDER_CLASS)
 		goto done;
 
-	if (IS_DG2(i915))
+	if (IS_PONTEVECCHIO(i915))
+		; /* noop; none at this time */
+	else if (IS_DG2(i915))
 		dg2_ctx_workarounds_init(engine, wal);
 	else if (IS_XEHPSDV(i915))
 		; /* noop; none at this time */
@@ -1494,7 +1496,9 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
 {
 	struct drm_i915_private *i915 = gt->i915;
 
-	if (IS_DG2(i915))
+	if (IS_PONTEVECCHIO(i915))
+		; /* none yet */
+	else if (IS_DG2(i915))
 		dg2_gt_workarounds_init(gt, wal);
 	else if (IS_XEHPSDV(i915))
 		xehpsdv_gt_workarounds_init(gt, wal);
@@ -1924,6 +1928,32 @@ static void dg2_whitelist_build(struct intel_engine_cs *engine)
 	}
 }
 
+static void blacklist_trtt(struct intel_engine_cs *engine)
+{
+	struct i915_wa_list *w = &engine->whitelist;
+
+	/*
+	 * Prevent read/write access to [0x4400, 0x4600) which covers
+	 * the TRTT range across all engines. Note that normally userspace
+	 * cannot access the other engines' trtt control, but for simplicity
+	 * we cover the entire range on each engine.
+	 */
+	whitelist_reg_ext(w, _MMIO(0x4400),
+			  RING_FORCE_TO_NONPRIV_DENY |
+			  RING_FORCE_TO_NONPRIV_RANGE_64);
+	whitelist_reg_ext(w, _MMIO(0x4500),
+			  RING_FORCE_TO_NONPRIV_DENY |
+			  RING_FORCE_TO_NONPRIV_RANGE_64);
+}
+
+static void pvc_whitelist_build(struct intel_engine_cs *engine)
+{
+	allow_read_ctx_timestamp(engine);
+
+	/* Wa_16014440446:pvc */
+	blacklist_trtt(engine);
+}
+
 void intel_engine_init_whitelist(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *i915 = engine->i915;
@@ -1931,7 +1961,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
 
 	wa_init_start(w, "whitelist", engine->name);
 
-	if (IS_DG2(i915))
+	if (IS_PONTEVECCHIO(i915))
+		pvc_whitelist_build(engine);
+	else if (IS_DG2(i915))
 		dg2_whitelist_build(engine);
 	else if (IS_XEHPSDV(i915))
 		xehpsdv_whitelist_build(engine);
@@ -2041,9 +2073,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 	struct drm_i915_private *i915 = engine->i915;
 
 	if (IS_DG2(i915)) {
-		/* Wa_14015227452:dg2 */
-		wa_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
-
 		/* Wa_1509235366:dg2 */
 		wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS |
 			    GLOBAL_INVALIDATION_MODE);
@@ -2611,6 +2640,15 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 	}
 }
 
+static void
+ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
+{
+	if (IS_PVC_CT_STEP(engine->i915, STEP_A0, STEP_C0)) {
+		/* Wa_14014999345:pvc */
+		wa_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC);
+	}
+}
+
 /*
  * The workarounds in this function apply to shared registers in
  * the general render reset domain that aren't tied to a
@@ -2657,8 +2695,11 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 				GLOBAL_INVALIDATION_MODE);
 	}
 
-	if (IS_DG2(i915)) {
-		/* Wa_22014226127:dg2 */
+	if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) {
+		/* Wa_14015227452:dg2,pvc */
+		wa_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
+
+		/* Wa_22014226127:dg2,pvc */
 		wa_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
 	}
 }
@@ -2679,7 +2720,9 @@ engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal
 	if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE)
 		general_render_compute_wa_init(engine, wal);
 
-	if (engine->class == RENDER_CLASS)
+	if (engine->class == COMPUTE_CLASS)
+		ccs_engine_wa_init(engine, wal);
+	else if (engine->class == RENDER_CLASS)
 		rcs_engine_wa_init(engine, wal);
 	else
 		xcs_engine_wa_init(engine, wal);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 42db41c8e3b33..7a3f023d39e96 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7526,6 +7526,17 @@ static void dg2_init_clock_gating(struct drm_i915_private *i915)
 				 SGR_DIS | SGGI_DIS);
 }
 
+static void pvc_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+	/* Wa_14012385139:pvc */
+	if (IS_PVC_BD_STEP(dev_priv, STEP_A0, STEP_B0))
+		intel_uncore_rmw(&dev_priv->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS);
+
+	/* Wa_22010954014:pvc */
+	if (IS_PVC_BD_STEP(dev_priv, STEP_A0, STEP_B0))
+		intel_uncore_rmw(&dev_priv->uncore, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
+}
+
 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	if (!HAS_PCH_CNP(dev_priv))
@@ -7942,6 +7953,7 @@ static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs =
 	.init_clock_gating = platform##_init_clock_gating,		\
 }
 
+CG_FUNCS(pvc);
 CG_FUNCS(dg2);
 CG_FUNCS(xehpsdv);
 CG_FUNCS(adlp);
@@ -7980,7 +7992,9 @@ CG_FUNCS(nop);
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
-	if (IS_DG2(dev_priv))
+	if (IS_PONTEVECCHIO(dev_priv))
+		dev_priv->clock_gating_funcs = &pvc_clock_gating_funcs;
+	else if (IS_DG2(dev_priv))
 		dev_priv->clock_gating_funcs = &dg2_clock_gating_funcs;
 	else if (IS_XEHPSDV(dev_priv))
 		dev_priv->clock_gating_funcs = &xehpsdv_clock_gating_funcs;
-- 
GitLab


From 1dc6ff02c8bf77d71b9b5d11cbc9df77cfb28626 Mon Sep 17 00:00:00 2001
From: Josh Poimboeuf <jpoimboe@kernel.org>
Date: Mon, 23 May 2022 09:11:49 -0700
Subject: [PATCH 0120/1731] x86/speculation/mmio: Print SMT warning

Similar to MDS and TAA, print a warning if SMT is enabled for the MMIO
Stale Data vulnerability.

Signed-off-by: Josh Poimboeuf <jpoimboe@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
 arch/x86/kernel/cpu/bugs.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index ef4749097f42d..a8a9f64063315 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -1258,6 +1258,7 @@ static void update_mds_branch_idle(void)
 
 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
+#define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n"
 
 void cpu_bugs_smt_update(void)
 {
@@ -1302,6 +1303,16 @@ void cpu_bugs_smt_update(void)
 		break;
 	}
 
+	switch (mmio_mitigation) {
+	case MMIO_MITIGATION_VERW:
+	case MMIO_MITIGATION_UCODE_NEEDED:
+		if (sched_smt_active())
+			pr_warn_once(MMIO_MSG_SMT);
+		break;
+	case MMIO_MITIGATION_OFF:
+		break;
+	}
+
 	mutex_unlock(&spec_ctrl_mutex);
 }
 
-- 
GitLab


From 04514c14678e760e17e3cd44c553ade1bf3bef06 Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Tue, 31 May 2022 19:25:27 +0300
Subject: [PATCH 0121/1731] drm/i915/display: stop using BUG()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Avoid bringing the entire machine down even if there's a bug that
shouldn't happen, but won't corrupt the system either. Log them loudly
and limp on.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220531162527.1062319-1-jani.nikula@intel.com
---
 drivers/gpu/drm/i915/display/intel_ddi.c      | 11 ++++++-----
 drivers/gpu/drm/i915/display/intel_display.c  | 19 +++++++++++--------
 .../drm/i915/display/intel_display_types.h    | 15 +++++++++------
 3 files changed, 26 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 14547d6a63a6d..477edda29899f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -455,6 +455,9 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
 		temp |= TRANS_DDI_SELECT_PORT(port);
 
 	switch (crtc_state->pipe_bpp) {
+	default:
+		MISSING_CASE(crtc_state->pipe_bpp);
+		fallthrough;
 	case 18:
 		temp |= TRANS_DDI_BPC_6;
 		break;
@@ -467,8 +470,6 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
 	case 36:
 		temp |= TRANS_DDI_BPC_12;
 		break;
-	default:
-		BUG();
 	}
 
 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
@@ -478,6 +479,9 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
 
 	if (cpu_transcoder == TRANSCODER_EDP) {
 		switch (pipe) {
+		default:
+			MISSING_CASE(pipe);
+			fallthrough;
 		case PIPE_A:
 			/* On Haswell, can only use the always-on power well for
 			 * eDP when not using the panel fitter, and when not
@@ -494,9 +498,6 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
 		case PIPE_C:
 			temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 			break;
-		default:
-			BUG();
-			break;
 		}
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6f2846c973b2e..d7363640cf6ba 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -500,6 +500,9 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 	i915_reg_t dpll_reg;
 
 	switch (dig_port->base.port) {
+	default:
+		MISSING_CASE(dig_port->base.port);
+		fallthrough;
 	case PORT_B:
 		port_mask = DPLL_PORTB_READY_MASK;
 		dpll_reg = DPLL(0);
@@ -513,8 +516,6 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 		port_mask = DPLL_PORTD_READY_MASK;
 		dpll_reg = DPIO_PHY_STATUS;
 		break;
-	default:
-		BUG();
 	}
 
 	if (intel_de_wait_for_register(dev_priv, dpll_reg,
@@ -3159,6 +3160,10 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
 				    PIPECONF_DITHER_TYPE_SP;
 
 		switch (crtc_state->pipe_bpp) {
+		default:
+			/* Case prevented by intel_choose_pipe_bpp_dither. */
+			MISSING_CASE(crtc_state->pipe_bpp);
+			fallthrough;
 		case 18:
 			pipeconf |= PIPECONF_BPC_6;
 			break;
@@ -3168,9 +3173,6 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
 		case 30:
 			pipeconf |= PIPECONF_BPC_10;
 			break;
-		default:
-			/* Case prevented by intel_choose_pipe_bpp_dither. */
-			BUG();
 		}
 	}
 
@@ -3466,6 +3468,10 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
 	val = 0;
 
 	switch (crtc_state->pipe_bpp) {
+	default:
+		/* Case prevented by intel_choose_pipe_bpp_dither. */
+		MISSING_CASE(crtc_state->pipe_bpp);
+		fallthrough;
 	case 18:
 		val |= PIPECONF_BPC_6;
 		break;
@@ -3478,9 +3484,6 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
 	case 36:
 		val |= PIPECONF_BPC_12;
 		break;
-	default:
-		/* Case prevented by intel_choose_pipe_bpp_dither. */
-		BUG();
 	}
 
 	if (crtc_state->dither)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 1a2f51e01f701..9723ae448c0b9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1798,13 +1798,14 @@ static inline enum dpio_channel
 vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
 {
 	switch (dig_port->base.port) {
+	default:
+		MISSING_CASE(dig_port->base.port);
+		fallthrough;
 	case PORT_B:
 	case PORT_D:
 		return DPIO_CH0;
 	case PORT_C:
 		return DPIO_CH1;
-	default:
-		BUG();
 	}
 }
 
@@ -1812,13 +1813,14 @@ static inline enum dpio_phy
 vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
 {
 	switch (dig_port->base.port) {
+	default:
+		MISSING_CASE(dig_port->base.port);
+		fallthrough;
 	case PORT_B:
 	case PORT_C:
 		return DPIO_PHY0;
 	case PORT_D:
 		return DPIO_PHY1;
-	default:
-		BUG();
 	}
 }
 
@@ -1826,13 +1828,14 @@ static inline enum dpio_channel
 vlv_pipe_to_channel(enum pipe pipe)
 {
 	switch (pipe) {
+	default:
+		MISSING_CASE(pipe);
+		fallthrough;
 	case PIPE_A:
 	case PIPE_C:
 		return DPIO_CH0;
 	case PIPE_B:
 		return DPIO_CH1;
-	default:
-		BUG();
 	}
 }
 
-- 
GitLab


From fba99b1ab7bde41c1eb00431df37b9237be3681e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 31 May 2022 22:18:39 +0300
Subject: [PATCH 0122/1731] drm/i915: Parse VRR capability from VBT
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

VBT seems to have an extra flag for VRR vs. not. Let's consult
that for eDP panels.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220531191844.11313-2-ville.syrjala@linux.intel.com
---
 drivers/gpu/drm/i915/display/intel_bios.c     |  5 +++++
 .../drm/i915/display/intel_display_types.h    |  2 ++
 drivers/gpu/drm/i915/display/intel_vrr.c      | 22 ++++++++++++++-----
 3 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index d80d147154b44..31520d08e33e9 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1292,6 +1292,8 @@ parse_power_conservation_features(struct drm_i915_private *i915,
 	const struct bdb_lfp_power *power;
 	u8 panel_type = panel->vbt.panel_type;
 
+	panel->vbt.vrr = true; /* matches Windows behaviour */
+
 	if (i915->vbt.version < 228)
 		return;
 
@@ -1312,6 +1314,9 @@ parse_power_conservation_features(struct drm_i915_private *i915,
 
 	if (i915->vbt.version >= 232)
 		panel->vbt.edp.hobl = power->hobl & BIT(panel_type);
+
+	if (i915->vbt.version >= 233)
+		panel->vbt.vrr = power->vrr_feature_enabled & BIT(panel_type);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9723ae448c0b9..09a664c51a4a5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -294,6 +294,8 @@ struct intel_vbt_panel_data {
 	unsigned int lvds_dither:1;
 	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
 
+	bool vrr;
+
 	u8 seamless_drrs_min_refresh_rate;
 	enum drrs_type drrs_type;
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 081e52dd6c4e2..04250a0fec3c1 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -15,19 +15,29 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
 	struct intel_dp *intel_dp;
 
-	if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP &&
-	    connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort)
-		return false;
-
-	intel_dp = intel_attached_dp(connector);
 	/*
 	 * DP Sink is capable of VRR video timings if
 	 * Ignore MSA bit is set in DPCD.
 	 * EDID monitor range also should be atleast 10 for reasonable
 	 * Adaptive Sync or Variable Refresh Rate end user experience.
 	 */
+	switch (connector->base.connector_type) {
+	case DRM_MODE_CONNECTOR_eDP:
+		if (!connector->panel.vbt.vrr)
+			return false;
+		fallthrough;
+	case DRM_MODE_CONNECTOR_DisplayPort:
+		intel_dp = intel_attached_dp(connector);
+
+		if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd))
+			return false;
+
+		break;
+	default:
+		return false;
+	}
+
 	return HAS_VRR(i915) &&
-		drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) &&
 		info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
 }
 
-- 
GitLab


From 2db7d421cc5ca86bdcf57f2634f6eefdf349f998 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 31 May 2022 22:18:40 +0300
Subject: [PATCH 0123/1731] drm/i915: Print out rejected fixed modes
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

To help with debugging DRRS/VRR panel init let's dump out all
the fixed modes we rejected for whatever reason.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220531191844.11313-3-ville.syrjala@linux.intel.com
---
 drivers/gpu/drm/i915/display/intel_panel.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index d055e41185582..f55e4eafd74ea 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -217,6 +217,10 @@ static void intel_panel_destroy_probed_modes(struct intel_connector *connector)
 	struct drm_display_mode *mode, *next;
 
 	list_for_each_entry_safe(mode, next, &connector->base.probed_modes, head) {
+		drm_dbg_kms(&i915->drm,
+			    "[CONNECTOR:%d:%s] not using EDID mode: " DRM_MODE_FMT "\n",
+			    connector->base.base.id, connector->base.name,
+			    DRM_MODE_ARG(mode));
 		list_del(&mode->head);
 		drm_mode_destroy(&i915->drm, mode);
 	}
-- 
GitLab


From 6e939738da208bcc0e4dc794519e18cad85bca73 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 31 May 2022 22:18:41 +0300
Subject: [PATCH 0124/1731] drm/i915: Accept more fixed modes with VRR panels
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

It seem that when dealing with VRR capable eDP panels we need
to accept fixed modes with variable vblank length (which is what
VRR varies dynamically). Typically the preferred mode seems to be
a non-VRR more (lowish dotclock/refresh rate + short vblank).

We also have examples where it looks like even the hblank length
is a bit different between the preferred mode vs. VRR mode(s).
So let's just accept anything that has matching hdisp+vdisp+flags.

v2: Document that is_alt_drrs_mode() is a subset of is_alt_vrr_mode() (Jani)

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/125
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220531191844.11313-4-ville.syrjala@linux.intel.com
---
 drivers/gpu/drm/i915/display/intel_dp.c    |  3 +-
 drivers/gpu/drm/i915/display/intel_lvds.c  |  3 +-
 drivers/gpu/drm/i915/display/intel_panel.c | 49 ++++++++++++++++------
 drivers/gpu/drm/i915/display/intel_panel.h |  3 +-
 drivers/gpu/drm/i915/display/intel_sdvo.c  |  2 +-
 5 files changed, 44 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f74acc746d11a..a00c82ac46f48 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5216,7 +5216,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 			      IS_ERR(edid) ? NULL : edid);
 
 	intel_panel_add_edid_fixed_modes(intel_connector,
-					 intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE);
+					 intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE,
+					 intel_vrr_is_capable(intel_connector));
 
 	/* MSO requires information from the EDID */
 	intel_edp_mso_init(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 595f03343939f..e55802b454613 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -972,7 +972,8 @@ void intel_lvds_init(struct drm_i915_private *dev_priv)
 
 	/* Try EDID first */
 	intel_panel_add_edid_fixed_modes(intel_connector,
-					 intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE);
+					 intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE,
+					 false);
 
 	/* Failed to get EDID, what about VBT? */
 	if (!intel_panel_preferred_fixed_mode(intel_connector))
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index f55e4eafd74ea..237a40623dd7b 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -71,6 +71,27 @@ intel_panel_fixed_mode(struct intel_connector *connector,
 	return best_mode;
 }
 
+static bool is_alt_drrs_mode(const struct drm_display_mode *mode,
+			     const struct drm_display_mode *preferred_mode)
+{
+	return drm_mode_match(mode, preferred_mode,
+			      DRM_MODE_MATCH_TIMINGS |
+			      DRM_MODE_MATCH_FLAGS |
+			      DRM_MODE_MATCH_3D_FLAGS) &&
+		mode->clock != preferred_mode->clock;
+}
+
+static bool is_alt_vrr_mode(const struct drm_display_mode *mode,
+			    const struct drm_display_mode *preferred_mode)
+{
+	return drm_mode_match(mode, preferred_mode,
+			      DRM_MODE_MATCH_FLAGS |
+			      DRM_MODE_MATCH_3D_FLAGS) &&
+		mode->hdisplay == preferred_mode->hdisplay &&
+		mode->vdisplay == preferred_mode->vdisplay &&
+		mode->clock != preferred_mode->clock;
+}
+
 const struct drm_display_mode *
 intel_panel_downclock_mode(struct intel_connector *connector,
 			   const struct drm_display_mode *adjusted_mode)
@@ -83,7 +104,8 @@ intel_panel_downclock_mode(struct intel_connector *connector,
 	list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head) {
 		int vrefresh = drm_mode_vrefresh(fixed_mode);
 
-		if (vrefresh >= min_vrefresh && vrefresh < max_vrefresh) {
+		if (is_alt_drrs_mode(fixed_mode, adjusted_mode) &&
+		    vrefresh >= min_vrefresh && vrefresh < max_vrefresh) {
 			max_vrefresh = vrefresh;
 			best_mode = fixed_mode;
 		}
@@ -151,16 +173,18 @@ int intel_panel_compute_config(struct intel_connector *connector,
 }
 
 static bool is_alt_fixed_mode(const struct drm_display_mode *mode,
-			      const struct drm_display_mode *preferred_mode)
+			      const struct drm_display_mode *preferred_mode,
+			      bool has_vrr)
 {
-	return drm_mode_match(mode, preferred_mode,
-			      DRM_MODE_MATCH_TIMINGS |
-			      DRM_MODE_MATCH_FLAGS |
-			      DRM_MODE_MATCH_3D_FLAGS) &&
-		mode->clock != preferred_mode->clock;
+	/* is_alt_drrs_mode() is a subset of is_alt_vrr_mode() */
+	if (has_vrr)
+		return is_alt_vrr_mode(mode, preferred_mode);
+	else
+		return is_alt_drrs_mode(mode, preferred_mode);
 }
 
-static void intel_panel_add_edid_alt_fixed_modes(struct intel_connector *connector)
+static void intel_panel_add_edid_alt_fixed_modes(struct intel_connector *connector,
+						 bool has_vrr)
 {
 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	const struct drm_display_mode *preferred_mode =
@@ -168,7 +192,7 @@ static void intel_panel_add_edid_alt_fixed_modes(struct intel_connector *connect
 	struct drm_display_mode *mode, *next;
 
 	list_for_each_entry_safe(mode, next, &connector->base.probed_modes, head) {
-		if (!is_alt_fixed_mode(mode, preferred_mode))
+		if (!is_alt_fixed_mode(mode, preferred_mode, has_vrr))
 			continue;
 
 		drm_dbg_kms(&dev_priv->drm,
@@ -226,11 +250,12 @@ static void intel_panel_destroy_probed_modes(struct intel_connector *connector)
 	}
 }
 
-void intel_panel_add_edid_fixed_modes(struct intel_connector *connector, bool has_drrs)
+void intel_panel_add_edid_fixed_modes(struct intel_connector *connector,
+				      bool has_drrs, bool has_vrr)
 {
 	intel_panel_add_edid_preferred_mode(connector);
-	if (intel_panel_preferred_fixed_mode(connector) && has_drrs)
-		intel_panel_add_edid_alt_fixed_modes(connector);
+	if (intel_panel_preferred_fixed_mode(connector) && (has_drrs || has_vrr))
+		intel_panel_add_edid_alt_fixed_modes(connector, has_vrr);
 	intel_panel_destroy_probed_modes(connector);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_panel.h b/drivers/gpu/drm/i915/display/intel_panel.h
index 2e32bb728beb8..b087c0c3cc6db 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.h
+++ b/drivers/gpu/drm/i915/display/intel_panel.h
@@ -40,7 +40,8 @@ int intel_panel_fitting(struct intel_crtc_state *crtc_state,
 			const struct drm_connector_state *conn_state);
 int intel_panel_compute_config(struct intel_connector *connector,
 			       struct drm_display_mode *adjusted_mode);
-void intel_panel_add_edid_fixed_modes(struct intel_connector *connector, bool has_drrs);
+void intel_panel_add_edid_fixed_modes(struct intel_connector *connector,
+				      bool has_drrs, bool has_vrr);
 void intel_panel_add_vbt_lfp_fixed_mode(struct intel_connector *connector);
 void intel_panel_add_vbt_sdvo_fixed_mode(struct intel_connector *connector);
 void intel_panel_add_encoder_fixed_mode(struct intel_connector *connector,
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index ba76783994ae0..81f700517e894 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -2910,7 +2910,7 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
 
 	if (!intel_panel_preferred_fixed_mode(intel_connector)) {
 		intel_ddc_get_modes(connector, &intel_sdvo->ddc);
-		intel_panel_add_edid_fixed_modes(intel_connector, false);
+		intel_panel_add_edid_fixed_modes(intel_connector, false, false);
 	}
 
 	intel_panel_init(intel_connector);
-- 
GitLab


From a9b20eb6f7da7794f8ffbce0ab9c709cb1ed71aa Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 31 May 2022 22:18:42 +0300
Subject: [PATCH 0125/1731] drm/i915/bios: Fix aggressiveness typos
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Fix various typos around "aggressiveness". Note that
the VBT spec also sometimes missspells it as
"agressiveness" so I guess that's where some of the typos
came from.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220531191844.11313-5-ville.syrjala@linux.intel.com
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 4b98bab3b8907..39109f204c6d5 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -856,9 +856,9 @@ struct als_data_entry {
 	u16 lux;
 } __packed;
 
-struct agressiveness_profile_entry {
-	u8 dpst_agressiveness : 4;
-	u8 lace_agressiveness : 4;
+struct aggressiveness_profile_entry {
+	u8 dpst_aggressiveness : 4;
+	u8 lace_aggressiveness : 4;
 } __packed;
 
 struct bdb_lfp_power {
@@ -873,7 +873,7 @@ struct bdb_lfp_power {
 	u16 dmrrs;
 	u16 adb;
 	u16 lace_enabled_status;
-	struct agressiveness_profile_entry aggressivenes[16];
+	struct aggressiveness_profile_entry aggressiveness[16];
 	u16 hobl; /* 232+ */
 	u16 vrr_feature_enabled; /* 233+ */
 } __packed;
-- 
GitLab


From 700034566d6844b3a67f4b6c3a728d9c0c8d93af Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 31 May 2022 22:18:43 +0300
Subject: [PATCH 0126/1731] drm/i915/bios: Define more BDB contents
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add a bunch of new struff we're missing in various BDB blocks.

TODO: Bunch of these might actually need to be taken
into use...

v2: s/lfp_features/lfp_power/features/ (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220531191844.11313-6-ville.syrjala@linux.intel.com
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 50 ++++++++++++++++---
 1 file changed, 43 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 39109f204c6d5..14f1e1cc92c5f 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -564,7 +564,9 @@ struct bdb_driver_features {
 	u16 tbt_enabled:1;
 	u16 psr_enabled:1;
 	u16 ips_enabled:1;
-	u16 reserved3:4;
+	u16 reserved3:1;
+	u16 dmrrs_enabled:1;
+	u16 reserved4:2;
 	u16 pc_feature_valid:1;
 } __packed;
 
@@ -666,6 +668,16 @@ struct edp_full_link_params {
 	u8 vswing:4;
 } __packed;
 
+struct edp_apical_params {
+	u32 panel_oui;
+	u32 dpcd_base_address;
+	u32 dpcd_idridix_control_0;
+	u32 dpcd_option_select;
+	u32 dpcd_backlight;
+	u32 ambient_light;
+	u32 backlight_scale;
+} __packed;
+
 struct bdb_edp {
 	struct edp_power_seq power_seqs[16];
 	u32 color_depth;
@@ -681,6 +693,9 @@ struct bdb_edp {
 	struct edp_pwm_delays pwm_delays[16];			/* 186 */
 	u16 full_link_params_provided;				/* 199 */
 	struct edp_full_link_params full_link_params[16];	/* 199 */
+	u16 apical_enable;					/* 203 */
+	struct edp_apical_params apical_params[16];		/* 203 */
+	u16 edp_fast_link_training_rate[16];			/* 224 */
 } __packed;
 
 /*
@@ -717,6 +732,7 @@ struct bdb_lvds_options {
 
 	u16 lcdvcc_s0_enable;					/* 200 */
 	u32 rotation;						/* 228 */
+	u32 position;						/* 240 */
 } __packed;
 
 /*
@@ -843,13 +859,22 @@ struct bdb_lfp_backlight_data {
 	u8 level[16]; /* Obsolete from 234+ */
 	struct lfp_backlight_control_method backlight_control[16];
 	struct lfp_brightness_level brightness_level[16];		/* 234+ */
-	struct lfp_brightness_level brightness_min_level[16];	/* 234+ */
-	u8 brightness_precision_bits[16];						/* 236+ */
+	struct lfp_brightness_level brightness_min_level[16];		/* 234+ */
+	u8 brightness_precision_bits[16];				/* 236+ */
+	u16 hdr_dpcd_refresh_timeout[16];				/* 239+ */
 } __packed;
 
 /*
  * Block 44 - LFP Power Conservation Features Block
  */
+struct lfp_power_features {
+	u8 reserved1:1;
+	u8 power_conservation_pref:3;
+	u8 reserved2:1;
+	u8 lace_enabled_status:1;
+	u8 lace_support:1;
+	u8 als_enable:1;
+} __packed;
 
 struct als_data_entry {
 	u16 backlight_adjust;
@@ -861,10 +886,16 @@ struct aggressiveness_profile_entry {
 	u8 lace_aggressiveness : 4;
 } __packed;
 
+struct aggressiveness_profile2_entry {
+	u8 opst_aggressiveness : 4;
+	u8 elp_aggressiveness : 4;
+} __packed;
+
 struct bdb_lfp_power {
-	u8 lfp_feature_bits;
+	struct lfp_power_features features;
 	struct als_data_entry als[5];
-	u8 lace_aggressiveness_profile;
+	u8 lace_aggressiveness_profile:3;
+	u8 reserved1:5;
 	u16 dpst;
 	u16 psr;
 	u16 drrs;
@@ -876,6 +907,9 @@ struct bdb_lfp_power {
 	struct aggressiveness_profile_entry aggressiveness[16];
 	u16 hobl; /* 232+ */
 	u16 vrr_feature_enabled; /* 233+ */
+	u16 elp; /* 247+ */
+	u16 opst; /* 247+ */
+	struct aggressiveness_profile2_entry aggressiveness2[16]; /* 247+ */
 } __packed;
 
 /*
@@ -885,8 +919,10 @@ struct bdb_lfp_power {
 #define MAX_MIPI_CONFIGURATIONS	6
 
 struct bdb_mipi_config {
-	struct mipi_config config[MAX_MIPI_CONFIGURATIONS];
-	struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS];
+	struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; /* 175 */
+	struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; /* 177 */
+	struct edp_pwm_delays pwm_delays[MAX_MIPI_CONFIGURATIONS]; /* 186 */
+	u8 pmic_i2c_bus_number[MAX_MIPI_CONFIGURATIONS]; /* 190 */
 } __packed;
 
 /*
-- 
GitLab


From 5a18db2e92a3556ccacc92c031db6e6a7f2b34dc Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 31 May 2022 22:18:44 +0300
Subject: [PATCH 0127/1731] drm/i915: Treat DMRRS as static DRRS
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Some machines declare DRRS type = seamless, DRRS = no, DMRRS = yes.
I *think* DMRRS stands for "dynamcic media refresh rate", and
I suspect the way it's meant to work is that it lets the driver
switch refresh rates to match the frame rate for media playback.
Obviously for us all that kind of policy stuff is entirely up to
userspace, so the only thing we may do is make the extra refresh
rate(s) available.

So let's treat this case as just static DRRS for now. In the
future We might want to differentiate the "seamless w/ downclocking"
vs. "seamless w/o downclocking" cases so that we could do seamless
refresh rate changes for systems that only claim to support DMRRS.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/125
Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220531191844.11313-7-ville.syrjala@linux.intel.com
---
 drivers/gpu/drm/i915/display/intel_bios.c | 24 +++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 31520d08e33e9..0f95ca6521159 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1278,8 +1278,16 @@ parse_panel_driver_features(struct drm_i915_private *i915,
 		 * static DRRS is 0 and DRRS not supported is represented by
 		 * driver->drrs_enabled=false
 		 */
-		if (!driver->drrs_enabled)
-			panel->vbt.drrs_type = DRRS_TYPE_NONE;
+		if (!driver->drrs_enabled && panel->vbt.drrs_type != DRRS_TYPE_NONE) {
+			/*
+			 * FIXME Should DMRRS perhaps be treated as seamless
+			 * but without the automatic downclocking?
+			 */
+			if (driver->dmrrs_enabled)
+				panel->vbt.drrs_type = DRRS_TYPE_STATIC;
+			else
+				panel->vbt.drrs_type = DRRS_TYPE_NONE;
+		}
 
 		panel->vbt.psr.enable = driver->psr_enabled;
 	}
@@ -1309,8 +1317,16 @@ parse_power_conservation_features(struct drm_i915_private *i915,
 	 * static DRRS is 0 and DRRS not supported is represented by
 	 * power->drrs & BIT(panel_type)=false
 	 */
-	if (!(power->drrs & BIT(panel_type)))
-		panel->vbt.drrs_type = DRRS_TYPE_NONE;
+	if (!(power->drrs & BIT(panel_type)) && panel->vbt.drrs_type != DRRS_TYPE_NONE) {
+		/*
+		 * FIXME Should DMRRS perhaps be treated as seamless
+		 * but without the automatic downclocking?
+		 */
+		if (power->dmrrs & BIT(panel_type))
+			panel->vbt.drrs_type = DRRS_TYPE_STATIC;
+		else
+			panel->vbt.drrs_type = DRRS_TYPE_NONE;
+	}
 
 	if (i915->vbt.version >= 232)
 		panel->vbt.edp.hobl = power->hobl & BIT(panel_type);
-- 
GitLab


From 036d20726c30267724416e966c9f92db07de8081 Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Tue, 31 May 2022 13:08:56 -0700
Subject: [PATCH 0128/1731] drm/msm: Ensure mmap offset is initialized

If a GEM object is allocated, and then exported as a dma-buf fd which is
mmap'd before or without the GEM buffer being directly mmap'd, the
vma_node could be unitialized.  This leads to a situation where the CPU
mapping is not correctly torn down in drm_vma_node_unmap().

Fixes: e5516553999f ("drm: call drm_gem_object_funcs.mmap with fake offset")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220531200857.136547-1-robdclark@gmail.com
---
 drivers/gpu/drm/msm/msm_drv.c       |  2 +-
 drivers/gpu/drm/msm/msm_drv.h       |  1 +
 drivers/gpu/drm/msm/msm_gem_prime.c | 15 +++++++++++++++
 3 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 44485363f37a0..14ab9a627d8b0 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -964,7 +964,7 @@ static const struct drm_driver msm_driver = {
 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 	.gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
-	.gem_prime_mmap     = drm_gem_prime_mmap,
+	.gem_prime_mmap     = msm_gem_prime_mmap,
 #ifdef CONFIG_DEBUG_FS
 	.debugfs_init       = msm_debugfs_init,
 #endif
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index fdbaad53eb843..34f74d47b3c1f 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -246,6 +246,7 @@ unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_t
 void msm_gem_shrinker_init(struct drm_device *dev);
 void msm_gem_shrinker_cleanup(struct drm_device *dev);
 
+int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
 int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map);
 void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map);
diff --git a/drivers/gpu/drm/msm/msm_gem_prime.c b/drivers/gpu/drm/msm/msm_gem_prime.c
index 94ab705e9b8a4..dcc8a573bc762 100644
--- a/drivers/gpu/drm/msm/msm_gem_prime.c
+++ b/drivers/gpu/drm/msm/msm_gem_prime.c
@@ -11,6 +11,21 @@
 #include "msm_drv.h"
 #include "msm_gem.h"
 
+int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
+{
+	int ret;
+
+	/* Ensure the mmap offset is initialized.  We lazily initialize it,
+	 * so if it has not been first mmap'd directly as a GEM object, the
+	 * mmap offset will not be already initialized.
+	 */
+	ret = drm_gem_create_mmap_offset(obj);
+	if (ret)
+		return ret;
+
+	return drm_gem_prime_mmap(obj, vma);
+}
+
 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj)
 {
 	struct msm_gem_object *msm_obj = to_msm_bo(obj);
-- 
GitLab


From 935a3c66eb9b66426d4be9b54666c77dbe7c32eb Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Wed, 1 Jun 2022 08:07:20 -0700
Subject: [PATCH 0129/1731] drm/i915/xehp: Use separate sseu init function

Xe_HP has enough fundamental differences from previous platforms that it
makes sense to use a separate SSEU init function to keep things
straightforward and easy to understand.  We'll also add a has_xehp_dss
flag to the SSEU structure that will be used by other upcoming changes.

v2:
 - Add has_xehp_dss flag

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220601150725.521468-2-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/intel_sseu.c | 86 ++++++++++++++++------------
 drivers/gpu/drm/i915/gt/intel_sseu.h |  5 ++
 2 files changed, 54 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index fdd25691beda0..b5fd479a7b852 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -169,13 +169,43 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, u8 s_en,
 	sseu->eu_total = compute_eu_total(sseu);
 }
 
-static void gen12_sseu_info_init(struct intel_gt *gt)
+static void xehp_sseu_info_init(struct intel_gt *gt)
 {
 	struct sseu_dev_info *sseu = &gt->info.sseu;
 	struct intel_uncore *uncore = gt->uncore;
 	u32 g_dss_en, c_dss_en = 0;
 	u16 eu_en = 0;
 	u8 eu_en_fuse;
+	int eu;
+
+	/*
+	 * The concept of slice has been removed in Xe_HP.  To be compatible
+	 * with prior generations, assume a single slice across the entire
+	 * device. Then calculate out the DSS for each workload type within
+	 * that software slice.
+	 */
+	intel_sseu_set_info(sseu, 1, 32, 16);
+	sseu->has_xehp_dss = 1;
+
+	g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
+	c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
+
+	eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
+
+	for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
+		if (eu_en_fuse & BIT(eu))
+			eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
+
+	gen11_compute_sseu_info(sseu, 0x1, g_dss_en, c_dss_en, eu_en);
+}
+
+static void gen12_sseu_info_init(struct intel_gt *gt)
+{
+	struct sseu_dev_info *sseu = &gt->info.sseu;
+	struct intel_uncore *uncore = gt->uncore;
+	u32 g_dss_en;
+	u16 eu_en = 0;
+	u8 eu_en_fuse;
 	u8 s_en;
 	int eu;
 
@@ -183,43 +213,23 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
 	 * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS.
 	 * Instead of splitting these, provide userspace with an array
 	 * of DSS to more closely represent the hardware resource.
-	 *
-	 * In addition, the concept of slice has been removed in Xe_HP.
-	 * To be compatible with prior generations, assume a single slice
-	 * across the entire device. Then calculate out the DSS for each
-	 * workload type within that software slice.
 	 */
-	if (IS_DG2(gt->i915) || IS_XEHPSDV(gt->i915))
-		intel_sseu_set_info(sseu, 1, 32, 16);
-	else
-		intel_sseu_set_info(sseu, 1, 6, 16);
+	intel_sseu_set_info(sseu, 1, 6, 16);
 
-	/*
-	 * As mentioned above, Xe_HP does not have the concept of a slice.
-	 * Enable one for software backwards compatibility.
-	 */
-	if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
-		s_en = 0x1;
-	else
-		s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
-		       GEN11_GT_S_ENA_MASK;
+	s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
+		GEN11_GT_S_ENA_MASK;
 
 	g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
-	if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
-		c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
 
 	/* one bit per pair of EUs */
-	if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
-		eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
-	else
-		eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
-			       GEN11_EU_DIS_MASK);
+	eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
+		       GEN11_EU_DIS_MASK);
 
 	for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
 		if (eu_en_fuse & BIT(eu))
 			eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
 
-	gen11_compute_sseu_info(sseu, s_en, g_dss_en, c_dss_en, eu_en);
+	gen11_compute_sseu_info(sseu, s_en, g_dss_en, 0, eu_en);
 
 	/* TGL only supports slice-level power gating */
 	sseu->has_slice_pg = 1;
@@ -574,18 +584,20 @@ void intel_sseu_info_init(struct intel_gt *gt)
 {
 	struct drm_i915_private *i915 = gt->i915;
 
-	if (IS_HASWELL(i915))
-		hsw_sseu_info_init(gt);
-	else if (IS_CHERRYVIEW(i915))
-		cherryview_sseu_info_init(gt);
-	else if (IS_BROADWELL(i915))
-		bdw_sseu_info_init(gt);
-	else if (GRAPHICS_VER(i915) == 9)
-		gen9_sseu_info_init(gt);
-	else if (GRAPHICS_VER(i915) == 11)
-		gen11_sseu_info_init(gt);
+	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+		xehp_sseu_info_init(gt);
 	else if (GRAPHICS_VER(i915) >= 12)
 		gen12_sseu_info_init(gt);
+	else if (GRAPHICS_VER(i915) >= 11)
+		gen11_sseu_info_init(gt);
+	else if (GRAPHICS_VER(i915) >= 9)
+		gen9_sseu_info_init(gt);
+	else if (IS_BROADWELL(i915))
+		bdw_sseu_info_init(gt);
+	else if (IS_CHERRYVIEW(i915))
+		cherryview_sseu_info_init(gt);
+	else if (IS_HASWELL(i915))
+		hsw_sseu_info_init(gt);
 }
 
 u32 intel_sseu_make_rpcs(struct intel_gt *gt,
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 5c078df4729cb..4a041f9dc490f 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -66,6 +66,11 @@ struct sseu_dev_info {
 	u8 has_slice_pg:1;
 	u8 has_subslice_pg:1;
 	u8 has_eu_pg:1;
+	/*
+	 * For Xe_HP and beyond, the hardware no longer has traditional slices
+	 * so we just report the entire DSS pool under a fake "slice 0."
+	 */
+	u8 has_xehp_dss:1;
 
 	/* Topology fields */
 	u8 max_slices;
-- 
GitLab


From aa2bdc4843f5871e6c68fbec5e10c0dbaf10ff91 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Wed, 1 Jun 2022 08:07:21 -0700
Subject: [PATCH 0130/1731] drm/i915/xehp: Drop GETPARAM lookups of
 I915_PARAM_[SUB]SLICE_MASK

Slice/subslice/EU information should be obtained via the topology
queries provided by the I915_QUERY interface; let's turn off support for
the old GETPARAM lookups on Xe_HP and beyond where we can't return
meaningful values.

The slice mask lookup is meaningless since Xe_HP doesn't support
traditional slices (and we make no attempt to return the various new
units like gslices, cslices, mslices, etc.) here.

The subslice mask lookup is even more problematic; given the distinct
masks for geometry vs compute purposes, the combined mask returned here
is likely not what userspace would want to act upon anyway.  The value
is also limited to 32-bits by the nature of the GETPARAM ioctl which is
sufficient for the initial Xe_HP platforms, but is unable to convey the
larger masks that will be needed on other upcoming platforms.  Finally,
the value returned here becomes even less meaningful when used on
multi-tile platforms where each tile will have its own masks.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>  # mesa
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220601150725.521468-3-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/i915_getparam.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index c12a0adefda53..ac9767c56619c 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -148,11 +148,19 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
 		value = intel_engines_has_context_isolation(i915);
 		break;
 	case I915_PARAM_SLICE_MASK:
+		/* Not supported from Xe_HP onward; use topology queries */
+		if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+			return -EINVAL;
+
 		value = sseu->slice_mask;
 		if (!value)
 			return -ENODEV;
 		break;
 	case I915_PARAM_SUBSLICE_MASK:
+		/* Not supported from Xe_HP onward; use topology queries */
+		if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+			return -EINVAL;
+
 		/* Only copy bits from the first slice */
 		memcpy(&value, sseu->subslice_mask,
 		       min(sseu->ss_stride, (u8)sizeof(value)));
-- 
GitLab


From 4cfd16659641067f618cdd3589eda42eb2943399 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Wed, 1 Jun 2022 08:07:22 -0700
Subject: [PATCH 0131/1731] drm/i915/sseu: Simplify gen11+ SSEU handling

Although gen11 and gen12 architectures supported the concept of multiple
slices, in practice all the platforms that were actually designed only
had a single slice (i.e., note the parameters to 'intel_sseu_set_info'
that we pass for each platform).  We can simplify the code slightly by
dropping the multi-slice logic from gen11+ platforms.

v2:
 - Promote drm_dbg to drm_WARN_ON if the slice fuse register reports
   unexpected fusing.  (Tvrtko)

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220601150725.521468-4-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/intel_sseu.c | 76 +++++++++++++---------------
 1 file changed, 36 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index b5fd479a7b852..7e5222ad2f98e 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -119,52 +119,37 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu)
 	return total;
 }
 
-static u32 get_ss_stride_mask(struct sseu_dev_info *sseu, u8 s, u32 ss_en)
-{
-	u32 ss_mask;
-
-	ss_mask = ss_en >> (s * sseu->max_subslices);
-	ss_mask &= GENMASK(sseu->max_subslices - 1, 0);
-
-	return ss_mask;
-}
-
-static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, u8 s_en,
+static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
 				    u32 g_ss_en, u32 c_ss_en, u16 eu_en)
 {
-	int s, ss;
+	u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
+	int ss;
 
 	/* g_ss_en/c_ss_en represent entire subslice mask across all slices */
 	GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
 		   sizeof(g_ss_en) * BITS_PER_BYTE);
 
-	for (s = 0; s < sseu->max_slices; s++) {
-		if ((s_en & BIT(s)) == 0)
-			continue;
+	sseu->slice_mask |= BIT(0);
 
-		sseu->slice_mask |= BIT(s);
-
-		/*
-		 * XeHP introduces the concept of compute vs geometry DSS. To
-		 * reduce variation between GENs around subslice usage, store a
-		 * mask for both the geometry and compute enabled masks since
-		 * userspace will need to be able to query these masks
-		 * independently.  Also compute a total enabled subslice count
-		 * for the purposes of selecting subslices to use in a
-		 * particular GEM context.
-		 */
-		intel_sseu_set_subslices(sseu, s, sseu->compute_subslice_mask,
-					 get_ss_stride_mask(sseu, s, c_ss_en));
-		intel_sseu_set_subslices(sseu, s, sseu->geometry_subslice_mask,
-					 get_ss_stride_mask(sseu, s, g_ss_en));
-		intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
-					 get_ss_stride_mask(sseu, s,
-							    g_ss_en | c_ss_en));
+	/*
+	 * XeHP introduces the concept of compute vs geometry DSS. To reduce
+	 * variation between GENs around subslice usage, store a mask for both
+	 * the geometry and compute enabled masks since userspace will need to
+	 * be able to query these masks independently.  Also compute a total
+	 * enabled subslice count for the purposes of selecting subslices to
+	 * use in a particular GEM context.
+	 */
+	intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
+				 c_ss_en & valid_ss_mask);
+	intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
+				 g_ss_en & valid_ss_mask);
+	intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
+				 (g_ss_en | c_ss_en) & valid_ss_mask);
+
+	for (ss = 0; ss < sseu->max_subslices; ss++)
+		if (intel_sseu_has_subslice(sseu, 0, ss))
+			sseu_set_eus(sseu, 0, ss, eu_en);
 
-		for (ss = 0; ss < sseu->max_subslices; ss++)
-			if (intel_sseu_has_subslice(sseu, s, ss))
-				sseu_set_eus(sseu, s, ss, eu_en);
-	}
 	sseu->eu_per_subslice = hweight16(eu_en);
 	sseu->eu_total = compute_eu_total(sseu);
 }
@@ -196,7 +181,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
 		if (eu_en_fuse & BIT(eu))
 			eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
 
-	gen11_compute_sseu_info(sseu, 0x1, g_dss_en, c_dss_en, eu_en);
+	gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
 }
 
 static void gen12_sseu_info_init(struct intel_gt *gt)
@@ -216,8 +201,13 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
 	 */
 	intel_sseu_set_info(sseu, 1, 6, 16);
 
+	/*
+	 * Although gen12 architecture supported multiple slices, TGL, RKL,
+	 * DG1, and ADL only had a single slice.
+	 */
 	s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
 		GEN11_GT_S_ENA_MASK;
+	drm_WARN_ON(&gt->i915->drm, s_en != 0x1);
 
 	g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
 
@@ -229,7 +219,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
 		if (eu_en_fuse & BIT(eu))
 			eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
 
-	gen11_compute_sseu_info(sseu, s_en, g_dss_en, 0, eu_en);
+	gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
 
 	/* TGL only supports slice-level power gating */
 	sseu->has_slice_pg = 1;
@@ -248,14 +238,20 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
 	else
 		intel_sseu_set_info(sseu, 1, 8, 8);
 
+	/*
+	 * Although gen11 architecture supported multiple slices, ICL and
+	 * EHL/JSL only had a single slice in practice.
+	 */
 	s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
 		GEN11_GT_S_ENA_MASK;
+	drm_WARN_ON(&gt->i915->drm, s_en != 0x1);
+
 	ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE);
 
 	eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
 		  GEN11_EU_DIS_MASK);
 
-	gen11_compute_sseu_info(sseu, s_en, ss_en, 0, eu_en);
+	gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
 
 	/* ICL has no power gating restrictions. */
 	sseu->has_slice_pg = 1;
-- 
GitLab


From bc3c5e0809ae9faa039baf75547e8ee46ec124ef Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Wed, 1 Jun 2022 08:07:23 -0700
Subject: [PATCH 0132/1731] drm/i915/sseu: Don't try to store EU mask
 internally in UAPI format

Storing the EU mask internally in the same format the I915_QUERY
topology queries use makes the final copy_to_user() a bit simpler, but
makes the rest of the driver's SSEU more complicated and harder to
follow.  Let's switch to an internal representation that's more natural:
Xe_HP platforms will be a simple array of u16 masks, whereas pre-Xe_HP
platforms will be a two-dimensional array, indexed by [slice][subslice].
We'll convert to the uapi format only when the query uapi is called.

v2:
 - Drop has_common_ss_eumask.  We waste some space repeating identical
   EU masks for every single DSS, but the code is simpler without it.
   (Tvrtko)

v3:
 - Mask down EUs passed to sseu_set_eus at the callsite rather than
   inside the function.  (Tvrtko)
 - Eliminate sseu->eu_stride and calculate it when needed.  (Tvrtko)

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220601150725.521468-5-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/intel_sseu.c | 88 ++++++++++++++++++----------
 drivers/gpu/drm/i915/gt/intel_sseu.h | 10 +++-
 drivers/gpu/drm/i915/i915_query.c    | 13 ++--
 3 files changed, 73 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 7e5222ad2f98e..285cfd758bdce 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -19,8 +19,6 @@ void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
 
 	sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
 	GEM_BUG_ON(sseu->ss_stride > GEN_MAX_SUBSLICE_STRIDE);
-	sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
-	GEM_BUG_ON(sseu->eu_stride > GEN_MAX_EU_STRIDE);
 }
 
 unsigned int
@@ -78,47 +76,77 @@ intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
 	return hweight32(intel_sseu_get_subslices(sseu, slice));
 }
 
-static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
-		       int subslice)
-{
-	int slice_stride = sseu->max_subslices * sseu->eu_stride;
-
-	return slice * slice_stride + subslice * sseu->eu_stride;
-}
-
 static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
 			int subslice)
 {
-	int i, offset = sseu_eu_idx(sseu, slice, subslice);
-	u16 eu_mask = 0;
-
-	for (i = 0; i < sseu->eu_stride; i++)
-		eu_mask |=
-			((u16)sseu->eu_mask[offset + i]) << (i * BITS_PER_BYTE);
-
-	return eu_mask;
+	if (sseu->has_xehp_dss) {
+		WARN_ON(slice > 0);
+		return sseu->eu_mask.xehp[subslice];
+	} else {
+		return sseu->eu_mask.hsw[slice][subslice];
+	}
 }
 
 static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
 			 u16 eu_mask)
 {
-	int i, offset = sseu_eu_idx(sseu, slice, subslice);
-
-	for (i = 0; i < sseu->eu_stride; i++)
-		sseu->eu_mask[offset + i] =
-			(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
+	GEM_WARN_ON(eu_mask && __fls(eu_mask) >= sseu->max_eus_per_subslice);
+	if (sseu->has_xehp_dss) {
+		GEM_WARN_ON(slice > 0);
+		sseu->eu_mask.xehp[subslice] = eu_mask;
+	} else {
+		sseu->eu_mask.hsw[slice][subslice] = eu_mask;
+	}
 }
 
 static u16 compute_eu_total(const struct sseu_dev_info *sseu)
 {
-	u16 i, total = 0;
+	int s, ss, total = 0;
 
-	for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++)
-		total += hweight8(sseu->eu_mask[i]);
+	for (s = 0; s < sseu->max_slices; s++)
+		for (ss = 0; ss < sseu->max_subslices; ss++)
+			if (sseu->has_xehp_dss)
+				total += hweight16(sseu->eu_mask.xehp[ss]);
+			else
+				total += hweight16(sseu->eu_mask.hsw[s][ss]);
 
 	return total;
 }
 
+/**
+ * intel_sseu_copy_eumask_to_user - Copy EU mask into a userspace buffer
+ * @to: Pointer to userspace buffer to copy to
+ * @sseu: SSEU structure containing EU mask to copy
+ *
+ * Copies the EU mask to a userspace buffer in the format expected by
+ * the query ioctl's topology queries.
+ *
+ * Returns the result of the copy_to_user() operation.
+ */
+int intel_sseu_copy_eumask_to_user(void __user *to,
+				   const struct sseu_dev_info *sseu)
+{
+	u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE] = {};
+	int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
+	int len = sseu->max_slices * sseu->max_subslices * eu_stride;
+	int s, ss, i;
+
+	for (s = 0; s < sseu->max_slices; s++) {
+		for (ss = 0; ss < sseu->max_subslices; ss++) {
+			int uapi_offset =
+				s * sseu->max_subslices * eu_stride +
+				ss * eu_stride;
+			u16 mask = sseu_get_eus(sseu, s, ss);
+
+			for (i = 0; i < eu_stride; i++)
+				eu_mask[uapi_offset + i] =
+					(mask >> (BITS_PER_BYTE * i)) & 0xff;
+		}
+	}
+
+	return copy_to_user(to, eu_mask, len);
+}
+
 static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
 				    u32 g_ss_en, u32 c_ss_en, u16 eu_en)
 {
@@ -278,7 +306,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
 			  CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
 
 		subslice_mask |= BIT(0);
-		sseu_set_eus(sseu, 0, 0, ~disabled_mask);
+		sseu_set_eus(sseu, 0, 0, ~disabled_mask & 0xFF);
 	}
 
 	if (!(fuse & CHV_FGT_DISABLE_SS1)) {
@@ -289,7 +317,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
 			  CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
 
 		subslice_mask |= BIT(1);
-		sseu_set_eus(sseu, 0, 1, ~disabled_mask);
+		sseu_set_eus(sseu, 0, 1, ~disabled_mask & 0xFF);
 	}
 
 	intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask, subslice_mask);
@@ -362,7 +390,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
 
 			eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask;
 
-			sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
+			sseu_set_eus(sseu, s, ss, ~eu_disabled_mask & eu_mask);
 
 			eu_per_ss = sseu->max_eus_per_subslice -
 				hweight8(eu_disabled_mask);
@@ -475,7 +503,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
 			eu_disabled_mask =
 				eu_disable[s] >> (ss * sseu->max_eus_per_subslice);
 
-			sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
+			sseu_set_eus(sseu, s, ss, ~eu_disabled_mask & 0xFF);
 
 			n_disabled = hweight8(eu_disabled_mask);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 4a041f9dc490f..ffa375e68959c 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -57,7 +57,11 @@ struct sseu_dev_info {
 	u8 subslice_mask[GEN_SS_MASK_SIZE];
 	u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
 	u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
-	u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE];
+	union {
+		u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
+		u16 xehp[GEN_MAX_DSS];
+	} eu_mask;
+
 	u16 eu_total;
 	u8 eu_per_subslice;
 	u8 min_eu_in_pool;
@@ -78,7 +82,6 @@ struct sseu_dev_info {
 	u8 max_eus_per_subslice;
 
 	u8 ss_stride;
-	u8 eu_stride;
 };
 
 /*
@@ -150,4 +153,7 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
 
 u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
 
+int intel_sseu_copy_eumask_to_user(void __user *to,
+				   const struct sseu_dev_info *sseu);
+
 #endif /* __INTEL_SSEU_H__ */
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 7584cec53d5da..89c475d525b84 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -35,6 +35,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
 {
 	struct drm_i915_query_topology_info topo;
 	u32 slice_length, subslice_length, eu_length, total_length;
+	int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
 	int ret;
 
 	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
@@ -44,7 +45,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
 
 	slice_length = sizeof(sseu->slice_mask);
 	subslice_length = sseu->max_slices * sseu->ss_stride;
-	eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
+	eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
 	total_length = sizeof(topo) + slice_length + subslice_length +
 		       eu_length;
 
@@ -61,7 +62,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
 	topo.subslice_offset = slice_length;
 	topo.subslice_stride = sseu->ss_stride;
 	topo.eu_offset = slice_length + subslice_length;
-	topo.eu_stride = sseu->eu_stride;
+	topo.eu_stride = eu_stride;
 
 	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
 			 &topo, sizeof(topo)))
@@ -76,10 +77,10 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
 			 subslice_mask, subslice_length))
 		return -EFAULT;
 
-	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
-					 sizeof(topo) +
-					 slice_length + subslice_length),
-			 sseu->eu_mask, eu_length))
+	if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
+							   sizeof(topo) +
+							   slice_length + subslice_length),
+					   sseu))
 		return -EFAULT;
 
 	return total_length;
-- 
GitLab


From b87d39019651c9cae169396cf5ae525393084490 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Wed, 1 Jun 2022 08:07:24 -0700
Subject: [PATCH 0133/1731] drm/i915/sseu: Disassociate internal subslice mask
 representation from uapi

As with EU masks, it's easier to store subslice/DSS masks internally in
a format that's more natural for the driver to work with, and then only
covert into the u8[] uapi form when the query ioctl is invoked.  Since
the hardware design changed significantly with Xe_HP, we'll use a union
to choose between the old "hsw-style" subslice masks or the newer xehp
mask.  HSW-style masks will be stored in an array of u8's, indexed by
slice (there's never more than 6 subslices per slice on older
platforms).  For Xe_HP and beyond where slices no longer exist, we only
need a single bitmask.  However we already know that this mask is
eventually going to grow too large for a simple u64 to hold, so we'll
represent it in a manner that can be operated on by the utilities in
linux/bitmap.h.

v2:
 - Fix typo: BIT(s) -> BIT(ss) in gen9_sseu_device_status()

v3:
 - Eliminate sseu->ss_stride and just calculate the stride while
   specifically handling uapi.  (Tvrtko)
 - Use BITMAP_BITS() macro to refer to size of masks rather than
   passing I915_MAX_SS_FUSE_BITS directly.  (Tvrtko)
 - Report compute/geometry DSS masks separately when dumping Xe_HP SSEU
   info.  (Tvrtko)
 - Restore dropped range checks to intel_sseu_has_subslice().  (Tvrtko)

v4:
 - Make the bitmap size macro check the size of the .xehp field rather
   than the containing union.  (Tvrtko)
 - Don't add GEM_BUG_ON() intel_sseu_has_subslice()'s check for whether
   slice or subslice ID exceed sseu->max_[sub]slices; various loops
   in the driver are expected to exceed these, so we should just
   silently return 'false.'

v5:
 - Move XEHP_BITMAP_BITS() to the header so that we can also replace a
   usage of I915_MAX_SS_FUSE_BITS in one of the inline functions.
   (Bala)
 - Change the local variable in intel_slicemask_from_xehp_dssmask() from
   u16 to 'unsigned long' to make it a bit more future-proof.

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220601150725.521468-6-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c  |   5 +-
 drivers/gpu/drm/i915/gt/intel_engine_cs.c    |   4 +-
 drivers/gpu/drm/i915/gt/intel_gt.c           |  12 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c         | 261 +++++++++++--------
 drivers/gpu/drm/i915/gt/intel_sseu.h         |  79 ++++--
 drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c |  30 +--
 drivers/gpu/drm/i915/gt/intel_workarounds.c  |  24 +-
 drivers/gpu/drm/i915/i915_getparam.c         |   3 +-
 drivers/gpu/drm/i915/i915_query.c            |  13 +-
 9 files changed, 243 insertions(+), 188 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ab4c5ab28e4d9..a3bb73f5d53bf 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1875,6 +1875,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
 {
 	const struct sseu_dev_info *device = &gt->info.sseu;
 	struct drm_i915_private *i915 = gt->i915;
+	unsigned int dev_subslice_mask = intel_sseu_get_hsw_subslices(device, 0);
 
 	/* No zeros in any field. */
 	if (!user->slice_mask || !user->subslice_mask ||
@@ -1901,7 +1902,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
 	if (user->slice_mask & ~device->slice_mask)
 		return -EINVAL;
 
-	if (user->subslice_mask & ~device->subslice_mask[0])
+	if (user->subslice_mask & ~dev_subslice_mask)
 		return -EINVAL;
 
 	if (user->max_eus_per_subslice > device->max_eus_per_subslice)
@@ -1915,7 +1916,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
 	/* Part specific restrictions. */
 	if (GRAPHICS_VER(i915) == 11) {
 		unsigned int hw_s = hweight8(device->slice_mask);
-		unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
+		unsigned int hw_ss_per_s = hweight8(dev_subslice_mask);
 		unsigned int req_s = hweight8(context->slice_mask);
 		unsigned int req_ss = hweight8(context->subslice_mask);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 1adbf34c36324..f0acf8518a515 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -674,8 +674,8 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
 	if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
 		return;
 
-	ccs_mask = intel_slicemask_from_dssmask(intel_sseu_get_compute_subslices(&info->sseu),
-						ss_per_ccs);
+	ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
+						     ss_per_ccs);
 	/*
 	 * If all DSS in a quadrant are fused off, the corresponding CCS
 	 * engine is not available for use.
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 0a3931c011c62..ddfb98f704898 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -133,13 +133,6 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = {
 	{},
 };
 
-static u16 slicemask(struct intel_gt *gt, int count)
-{
-	u64 dss_mask = intel_sseu_get_subslices(&gt->info.sseu, 0);
-
-	return intel_slicemask_from_dssmask(dss_mask, count);
-}
-
 int intel_gt_init_mmio(struct intel_gt *gt)
 {
 	struct drm_i915_private *i915 = gt->i915;
@@ -155,9 +148,12 @@ int intel_gt_init_mmio(struct intel_gt *gt)
 	 */
 	if (HAS_MSLICES(i915)) {
 		gt->info.mslice_mask =
-			slicemask(gt, GEN_DSS_PER_MSLICE) |
+			intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
+							  GEN_DSS_PER_MSLICE);
+		gt->info.mslice_mask |=
 			(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
 			 GEN12_MEML3_EN_MASK);
+
 		if (!gt->info.mslice_mask) /* should be impossible! */
 			drm_warn(&i915->drm, "mslice mask all zero!\n");
 	}
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 285cfd758bdce..826d11f18817a 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -16,9 +16,6 @@ void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
 	sseu->max_slices = max_slices;
 	sseu->max_subslices = max_subslices;
 	sseu->max_eus_per_subslice = max_eus_per_subslice;
-
-	sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
-	GEM_BUG_ON(sseu->ss_stride > GEN_MAX_SUBSLICE_STRIDE);
 }
 
 unsigned int
@@ -26,54 +23,24 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
 {
 	unsigned int i, total = 0;
 
-	for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
-		total += hweight8(sseu->subslice_mask[i]);
-
-	return total;
-}
-
-static u32
-sseu_get_subslices(const struct sseu_dev_info *sseu,
-		   const u8 *subslice_mask, u8 slice)
-{
-	int i, offset = slice * sseu->ss_stride;
-	u32 mask = 0;
-
-	GEM_BUG_ON(slice >= sseu->max_slices);
-
-	for (i = 0; i < sseu->ss_stride; i++)
-		mask |= (u32)subslice_mask[offset + i] << i * BITS_PER_BYTE;
-
-	return mask;
-}
-
-u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
-{
-	return sseu_get_subslices(sseu, sseu->subslice_mask, slice);
-}
+	if (sseu->has_xehp_dss)
+		return bitmap_weight(sseu->subslice_mask.xehp,
+				     XEHP_BITMAP_BITS(sseu->subslice_mask));
 
-static u32 sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
-{
-	return sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
-}
+	for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++)
+		total += hweight8(sseu->subslice_mask.hsw[i]);
 
-u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu)
-{
-	return sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0);
-}
-
-void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
-			      u8 *subslice_mask, u32 ss_mask)
-{
-	int offset = slice * sseu->ss_stride;
-
-	memcpy(&subslice_mask[offset], &ss_mask, sseu->ss_stride);
+	return total;
 }
 
 unsigned int
-intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice)
 {
-	return hweight32(intel_sseu_get_subslices(sseu, slice));
+	WARN_ON(sseu->has_xehp_dss);
+	if (WARN_ON(slice >= sseu->max_slices))
+		return 0;
+
+	return sseu->subslice_mask.hsw[slice];
 }
 
 static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
@@ -147,32 +114,66 @@ int intel_sseu_copy_eumask_to_user(void __user *to,
 	return copy_to_user(to, eu_mask, len);
 }
 
+/**
+ * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer
+ * @to: Pointer to userspace buffer to copy to
+ * @sseu: SSEU structure containing subslice mask to copy
+ *
+ * Copies the subslice mask to a userspace buffer in the format expected by
+ * the query ioctl's topology queries.
+ *
+ * Returns the result of the copy_to_user() operation.
+ */
+int intel_sseu_copy_ssmask_to_user(void __user *to,
+				   const struct sseu_dev_info *sseu)
+{
+	u8 ss_mask[GEN_SS_MASK_SIZE] = {};
+	int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
+	int len = sseu->max_slices * ss_stride;
+	int s, ss, i;
+
+	for (s = 0; s < sseu->max_slices; s++) {
+		for (ss = 0; ss < sseu->max_subslices; ss++) {
+			i = s * ss_stride * BITS_PER_BYTE + ss;
+
+			if (!intel_sseu_has_subslice(sseu, s, ss))
+				continue;
+
+			ss_mask[i / BITS_PER_BYTE] |= BIT(i % BITS_PER_BYTE);
+		}
+	}
+
+	return copy_to_user(to, ss_mask, len);
+}
+
 static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
-				    u32 g_ss_en, u32 c_ss_en, u16 eu_en)
+				    u32 ss_en, u16 eu_en)
 {
 	u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
 	int ss;
 
-	/* g_ss_en/c_ss_en represent entire subslice mask across all slices */
-	GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
-		   sizeof(g_ss_en) * BITS_PER_BYTE);
+	sseu->slice_mask |= BIT(0);
+	sseu->subslice_mask.hsw[0] = ss_en & valid_ss_mask;
+
+	for (ss = 0; ss < sseu->max_subslices; ss++)
+		if (intel_sseu_has_subslice(sseu, 0, ss))
+			sseu_set_eus(sseu, 0, ss, eu_en);
+
+	sseu->eu_per_subslice = hweight16(eu_en);
+	sseu->eu_total = compute_eu_total(sseu);
+}
+
+static void xehp_compute_sseu_info(struct sseu_dev_info *sseu,
+				   u16 eu_en)
+{
+	int ss;
 
 	sseu->slice_mask |= BIT(0);
 
-	/*
-	 * XeHP introduces the concept of compute vs geometry DSS. To reduce
-	 * variation between GENs around subslice usage, store a mask for both
-	 * the geometry and compute enabled masks since userspace will need to
-	 * be able to query these masks independently.  Also compute a total
-	 * enabled subslice count for the purposes of selecting subslices to
-	 * use in a particular GEM context.
-	 */
-	intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
-				 c_ss_en & valid_ss_mask);
-	intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
-				 g_ss_en & valid_ss_mask);
-	intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
-				 (g_ss_en | c_ss_en) & valid_ss_mask);
+	bitmap_or(sseu->subslice_mask.xehp,
+		  sseu->compute_subslice_mask.xehp,
+		  sseu->geometry_subslice_mask.xehp,
+		  XEHP_BITMAP_BITS(sseu->subslice_mask));
 
 	for (ss = 0; ss < sseu->max_subslices; ss++)
 		if (intel_sseu_has_subslice(sseu, 0, ss))
@@ -182,11 +183,31 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
 	sseu->eu_total = compute_eu_total(sseu);
 }
 
+static void
+xehp_load_dss_mask(struct intel_uncore *uncore,
+		   intel_sseu_ss_mask_t *ssmask,
+		   int numregs,
+		   ...)
+{
+	va_list argp;
+	u32 fuse_val[I915_MAX_SS_FUSE_REGS] = {};
+	int i;
+
+	if (WARN_ON(numregs > I915_MAX_SS_FUSE_REGS))
+		numregs = I915_MAX_SS_FUSE_REGS;
+
+	va_start(argp, numregs);
+	for (i = 0; i < numregs; i++)
+		fuse_val[i] = intel_uncore_read(uncore, va_arg(argp, i915_reg_t));
+	va_end(argp);
+
+	bitmap_from_arr32(ssmask->xehp, fuse_val, numregs * 32);
+}
+
 static void xehp_sseu_info_init(struct intel_gt *gt)
 {
 	struct sseu_dev_info *sseu = &gt->info.sseu;
 	struct intel_uncore *uncore = gt->uncore;
-	u32 g_dss_en, c_dss_en = 0;
 	u16 eu_en = 0;
 	u8 eu_en_fuse;
 	int eu;
@@ -200,8 +221,10 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
 	intel_sseu_set_info(sseu, 1, 32, 16);
 	sseu->has_xehp_dss = 1;
 
-	g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
-	c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
+	xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
+			   GEN12_GT_GEOMETRY_DSS_ENABLE);
+	xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
+			   GEN12_GT_COMPUTE_DSS_ENABLE);
 
 	eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
 
@@ -209,7 +232,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
 		if (eu_en_fuse & BIT(eu))
 			eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
 
-	gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
+	xehp_compute_sseu_info(sseu, eu_en);
 }
 
 static void gen12_sseu_info_init(struct intel_gt *gt)
@@ -247,7 +270,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
 		if (eu_en_fuse & BIT(eu))
 			eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
 
-	gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
+	gen11_compute_sseu_info(sseu, g_dss_en, eu_en);
 
 	/* TGL only supports slice-level power gating */
 	sseu->has_slice_pg = 1;
@@ -279,7 +302,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
 	eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
 		  GEN11_EU_DIS_MASK);
 
-	gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
+	gen11_compute_sseu_info(sseu, ss_en, eu_en);
 
 	/* ICL has no power gating restrictions. */
 	sseu->has_slice_pg = 1;
@@ -291,7 +314,6 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
 {
 	struct sseu_dev_info *sseu = &gt->info.sseu;
 	u32 fuse;
-	u8 subslice_mask = 0;
 
 	fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);
 
@@ -305,7 +327,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
 			(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
 			  CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
 
-		subslice_mask |= BIT(0);
+		sseu->subslice_mask.hsw[0] |= BIT(0);
 		sseu_set_eus(sseu, 0, 0, ~disabled_mask & 0xFF);
 	}
 
@@ -316,12 +338,10 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
 			(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
 			  CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
 
-		subslice_mask |= BIT(1);
+		sseu->subslice_mask.hsw[0] |= BIT(1);
 		sseu_set_eus(sseu, 0, 1, ~disabled_mask & 0xFF);
 	}
 
-	intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask, subslice_mask);
-
 	sseu->eu_total = compute_eu_total(sseu);
 
 	/*
@@ -376,8 +396,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
 			/* skip disabled slice */
 			continue;
 
-		intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
-					 subslice_mask);
+		sseu->subslice_mask.hsw[s] = subslice_mask;
 
 		eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
 		for (ss = 0; ss < sseu->max_subslices; ss++) {
@@ -434,8 +453,8 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
 	sseu->has_eu_pg = sseu->eu_per_subslice > 2;
 
 	if (IS_GEN9_LP(i915)) {
-#define IS_SS_DISABLED(ss)	(!(sseu->subslice_mask[0] & BIT(ss)))
-		info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
+#define IS_SS_DISABLED(ss)	(!(sseu->subslice_mask.hsw[0] & BIT(ss)))
+		info->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;
 
 		sseu->min_eu_in_pool = 0;
 		if (info->has_pooled_eu) {
@@ -489,8 +508,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
 			/* skip disabled slice */
 			continue;
 
-		intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
-					 subslice_mask);
+		sseu->subslice_mask.hsw[s] = subslice_mask;
 
 		for (ss = 0; ss < sseu->max_subslices; ss++) {
 			u8 eu_disabled_mask;
@@ -587,8 +605,7 @@ static void hsw_sseu_info_init(struct intel_gt *gt)
 			    sseu->eu_per_subslice);
 
 	for (s = 0; s < sseu->max_slices; s++) {
-		intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
-					 subslice_mask);
+		sseu->subslice_mask.hsw[s] = subslice_mask;
 
 		for (ss = 0; ss < sseu->max_subslices; ss++) {
 			sseu_set_eus(sseu, s, ss,
@@ -677,7 +694,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
 	 */
 	if (GRAPHICS_VER(i915) == 11 &&
 	    slices == 1 &&
-	    subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
+	    subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) {
 		GEM_BUG_ON(subslices & 1);
 
 		subslice_pg = false;
@@ -743,14 +760,29 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
 {
 	int s;
 
-	drm_printf(p, "slice total: %u, mask=%04x\n",
-		   hweight8(sseu->slice_mask), sseu->slice_mask);
-	drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
-	for (s = 0; s < sseu->max_slices; s++) {
-		drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
-			   s, intel_sseu_subslices_per_slice(sseu, s),
-			   intel_sseu_get_subslices(sseu, s));
+	if (sseu->has_xehp_dss) {
+		drm_printf(p, "subslice total: %u\n",
+			   intel_sseu_subslice_total(sseu));
+		drm_printf(p, "geometry dss mask=%*pb\n",
+			   XEHP_BITMAP_BITS(sseu->geometry_subslice_mask),
+			   sseu->geometry_subslice_mask.xehp);
+		drm_printf(p, "compute dss mask=%*pb\n",
+			   XEHP_BITMAP_BITS(sseu->compute_subslice_mask),
+			   sseu->compute_subslice_mask.xehp);
+	} else {
+		drm_printf(p, "slice total: %u, mask=%04x\n",
+			   hweight8(sseu->slice_mask), sseu->slice_mask);
+		drm_printf(p, "subslice total: %u\n",
+			   intel_sseu_subslice_total(sseu));
+
+		for (s = 0; s < sseu->max_slices; s++) {
+			u8 ss_mask = sseu->subslice_mask.hsw[s];
+
+			drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
+				   s, hweight8(ss_mask), ss_mask);
+		}
 	}
+
 	drm_printf(p, "EU total: %u\n", sseu->eu_total);
 	drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
 	drm_printf(p, "has slice power gating: %s\n",
@@ -767,9 +799,10 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
 	int s, ss;
 
 	for (s = 0; s < sseu->max_slices; s++) {
+		u8 ss_mask = sseu->subslice_mask.hsw[s];
+
 		drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
-			   s, intel_sseu_subslices_per_slice(sseu, s),
-			   intel_sseu_get_subslices(sseu, s));
+			   s, hweight8(ss_mask), ss_mask);
 
 		for (ss = 0; ss < sseu->max_subslices; ss++) {
 			u16 enabled_eus = sseu_get_eus(sseu, s, ss);
@@ -783,16 +816,14 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
 static void sseu_print_xehp_topology(const struct sseu_dev_info *sseu,
 				     struct drm_printer *p)
 {
-	u32 g_dss_mask = sseu_get_geometry_subslices(sseu);
-	u32 c_dss_mask = intel_sseu_get_compute_subslices(sseu);
 	int dss;
 
 	for (dss = 0; dss < sseu->max_subslices; dss++) {
 		u16 enabled_eus = sseu_get_eus(sseu, 0, dss);
 
 		drm_printf(p, "DSS_%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss,
-			   str_yes_no(g_dss_mask & BIT(dss)),
-			   str_yes_no(c_dss_mask & BIT(dss)),
+			   str_yes_no(test_bit(dss, sseu->geometry_subslice_mask.xehp)),
+			   str_yes_no(test_bit(dss, sseu->compute_subslice_mask.xehp)),
 			   hweight16(enabled_eus), enabled_eus);
 	}
 }
@@ -810,20 +841,44 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
 	}
 }
 
-u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice)
+void intel_sseu_print_ss_info(const char *type,
+			      const struct sseu_dev_info *sseu,
+			      struct seq_file *m)
+{
+	int s;
+
+	if (sseu->has_xehp_dss) {
+		seq_printf(m, "  %s Geometry DSS: %u\n", type,
+			   bitmap_weight(sseu->geometry_subslice_mask.xehp,
+					 XEHP_BITMAP_BITS(sseu->geometry_subslice_mask)));
+		seq_printf(m, "  %s Compute DSS: %u\n", type,
+			   bitmap_weight(sseu->compute_subslice_mask.xehp,
+					 XEHP_BITMAP_BITS(sseu->compute_subslice_mask)));
+	} else {
+		for (s = 0; s < fls(sseu->slice_mask); s++)
+			seq_printf(m, "  %s Slice%i subslices: %u\n", type,
+				   s, hweight8(sseu->subslice_mask.hsw[s]));
+	}
+}
+
+u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask,
+				      int dss_per_slice)
 {
-	u16 slice_mask = 0;
+	intel_sseu_ss_mask_t per_slice_mask = {};
+	unsigned long slice_mask = 0;
 	int i;
 
-	WARN_ON(sizeof(dss_mask) * 8 / dss_per_slice > 8 * sizeof(slice_mask));
+	WARN_ON(DIV_ROUND_UP(XEHP_BITMAP_BITS(dss_mask), dss_per_slice) >
+		8 * sizeof(slice_mask));
 
-	for (i = 0; dss_mask; i++) {
-		if (dss_mask & GENMASK(dss_per_slice - 1, 0))
+	bitmap_fill(per_slice_mask.xehp, dss_per_slice);
+	for (i = 0; !bitmap_empty(dss_mask.xehp, XEHP_BITMAP_BITS(dss_mask)); i++) {
+		if (bitmap_intersects(dss_mask.xehp, per_slice_mask.xehp, dss_per_slice))
 			slice_mask |= BIT(i);
 
-		dss_mask >>= dss_per_slice;
+		bitmap_shift_right(dss_mask.xehp, dss_mask.xehp, dss_per_slice,
+				   XEHP_BITMAP_BITS(dss_mask));
 	}
 
 	return slice_mask;
 }
-
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index ffa375e68959c..f0e09b743faaa 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -25,12 +25,16 @@ struct drm_printer;
 /*
  * Maximum number of subslices that can exist within a HSW-style slice.  This
  * is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the
- * GEN_MAX_DSS value below).
+ * I915_MAX_SS_FUSE_BITS value below).
  */
 #define GEN_MAX_SS_PER_HSW_SLICE	6
 
-/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
-#define GEN_MAX_DSS			32
+/*
+ * Maximum number of 32-bit registers used by hardware to express the
+ * enabled/disabled subslices.
+ */
+#define I915_MAX_SS_FUSE_REGS	1
+#define I915_MAX_SS_FUSE_BITS	(I915_MAX_SS_FUSE_REGS * 32)
 
 /* Maximum number of EUs that can exist within a subslice or DSS. */
 #define GEN_MAX_EUS_PER_SS		16
@@ -38,7 +42,7 @@ struct drm_printer;
 #define SSEU_MAX(a, b)			((a) > (b) ? (a) : (b))
 
 /* The maximum number of bits needed to express each subslice/DSS independently */
-#define GEN_SS_MASK_SIZE		SSEU_MAX(GEN_MAX_DSS, \
+#define GEN_SS_MASK_SIZE		SSEU_MAX(I915_MAX_SS_FUSE_BITS, \
 						 GEN_MAX_HSW_SLICES * GEN_MAX_SS_PER_HSW_SLICE)
 
 #define GEN_SSEU_STRIDE(max_entries)	DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
@@ -49,17 +53,26 @@ struct drm_printer;
 #define GEN_DSS_PER_CSLICE	8
 #define GEN_DSS_PER_MSLICE	8
 
-#define GEN_MAX_GSLICES		(GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
-#define GEN_MAX_CSLICES		(GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
+#define GEN_MAX_GSLICES		(I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_GSLICE)
+#define GEN_MAX_CSLICES		(I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_CSLICE)
+
+typedef union {
+	u8 hsw[GEN_MAX_HSW_SLICES];
+
+	/* Bitmap compatible with linux/bitmap.h; may exceed size of u64 */
+	unsigned long xehp[BITS_TO_LONGS(I915_MAX_SS_FUSE_BITS)];
+} intel_sseu_ss_mask_t;
+
+#define XEHP_BITMAP_BITS(mask)	((int)BITS_PER_TYPE(typeof(mask.xehp)))
 
 struct sseu_dev_info {
 	u8 slice_mask;
-	u8 subslice_mask[GEN_SS_MASK_SIZE];
-	u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
-	u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
+	intel_sseu_ss_mask_t subslice_mask;
+	intel_sseu_ss_mask_t geometry_subslice_mask;
+	intel_sseu_ss_mask_t compute_subslice_mask;
 	union {
 		u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
-		u16 xehp[GEN_MAX_DSS];
+		u16 xehp[I915_MAX_SS_FUSE_BITS];
 	} eu_mask;
 
 	u16 eu_total;
@@ -80,8 +93,6 @@ struct sseu_dev_info {
 	u8 max_slices;
 	u8 max_subslices;
 	u8 max_eus_per_subslice;
-
-	u8 ss_stride;
 };
 
 /*
@@ -99,7 +110,7 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
 {
 	struct intel_sseu value = {
 		.slice_mask = sseu->slice_mask,
-		.subslice_mask = sseu->subslice_mask[0],
+		.subslice_mask = sseu->subslice_mask.hsw[0],
 		.min_eus_per_subslice = sseu->max_eus_per_subslice,
 		.max_eus_per_subslice = sseu->max_eus_per_subslice,
 	};
@@ -111,18 +122,28 @@ static inline bool
 intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
 			int subslice)
 {
-	u8 mask;
-	int ss_idx = subslice / BITS_PER_BYTE;
-
 	if (slice >= sseu->max_slices ||
 	    subslice >= sseu->max_subslices)
 		return false;
 
-	GEM_BUG_ON(ss_idx >= sseu->ss_stride);
-
-	mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
+	if (sseu->has_xehp_dss)
+		return test_bit(subslice, sseu->subslice_mask.xehp);
+	else
+		return sseu->subslice_mask.hsw[slice] & BIT(subslice);
+}
 
-	return mask & BIT(subslice % BITS_PER_BYTE);
+/*
+ * Used to obtain the index of the first DSS.  Can start searching from the
+ * beginning of a specific dss group (e.g., gslice, cslice, etc.) if
+ * groupsize and groupnum are non-zero.
+ */
+static inline unsigned int
+intel_sseu_find_first_xehp_dss(const struct sseu_dev_info *sseu, int groupsize,
+			       int groupnum)
+{
+	return find_next_bit(sseu->subslice_mask.xehp,
+			     XEHP_BITMAP_BITS(sseu->subslice_mask),
+			     groupnum * groupsize);
 }
 
 void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
@@ -132,14 +153,10 @@ unsigned int
 intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
 
 unsigned int
-intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
+intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice);
 
-u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
-
-u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
-
-void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
-			      u8 *subslice_mask, u32 ss_mask);
+intel_sseu_ss_mask_t
+intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
 
 void intel_sseu_info_init(struct intel_gt *gt);
 
@@ -151,9 +168,15 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
 			       const struct sseu_dev_info *sseu,
 			       struct drm_printer *p);
 
-u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
+u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask, int dss_per_slice);
 
 int intel_sseu_copy_eumask_to_user(void __user *to,
 				   const struct sseu_dev_info *sseu);
+int intel_sseu_copy_ssmask_to_user(void __user *to,
+				   const struct sseu_dev_info *sseu);
+
+void intel_sseu_print_ss_info(const char *type,
+			      const struct sseu_dev_info *sseu,
+			      struct seq_file *m);
 
 #endif /* __INTEL_SSEU_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
index 2d5d011e01db2..c2ee5e1826b5d 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
@@ -4,6 +4,7 @@
  * Copyright © 2020 Intel Corporation
  */
 
+#include <linux/bitmap.h>
 #include <linux/string_helpers.h>
 
 #include "i915_drv.h"
@@ -11,14 +12,6 @@
 #include "intel_gt_regs.h"
 #include "intel_sseu_debugfs.h"
 
-static void sseu_copy_subslices(const struct sseu_dev_info *sseu,
-				int slice, u8 *to_mask)
-{
-	int offset = slice * sseu->ss_stride;
-
-	memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
-}
-
 static void cherryview_sseu_device_status(struct intel_gt *gt,
 					  struct sseu_dev_info *sseu)
 {
@@ -41,7 +34,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt,
 			continue;
 
 		sseu->slice_mask = BIT(0);
-		sseu->subslice_mask[0] |= BIT(ss);
+		sseu->subslice_mask.hsw[0] |= BIT(ss);
 		eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
 			 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
 			 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
@@ -92,7 +85,7 @@ static void gen11_sseu_device_status(struct intel_gt *gt,
 			continue;
 
 		sseu->slice_mask |= BIT(s);
-		sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
+		sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
 
 		for (ss = 0; ss < info->sseu.max_subslices; ss++) {
 			unsigned int eu_cnt;
@@ -147,21 +140,17 @@ static void gen9_sseu_device_status(struct intel_gt *gt,
 		sseu->slice_mask |= BIT(s);
 
 		if (IS_GEN9_BC(gt->i915))
-			sseu_copy_subslices(&info->sseu, s,
-					    sseu->subslice_mask);
+			sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
 
 		for (ss = 0; ss < info->sseu.max_subslices; ss++) {
 			unsigned int eu_cnt;
-			u8 ss_idx = s * info->sseu.ss_stride +
-				    ss / BITS_PER_BYTE;
 
 			if (IS_GEN9_LP(gt->i915)) {
 				if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
 					/* skip disabled subslice */
 					continue;
 
-				sseu->subslice_mask[ss_idx] |=
-					BIT(ss % BITS_PER_BYTE);
+				sseu->subslice_mask.hsw[s] |= BIT(ss);
 			}
 
 			eu_cnt = eu_reg[2 * s + ss / 2] & eu_mask[ss % 2];
@@ -188,8 +177,7 @@ static void bdw_sseu_device_status(struct intel_gt *gt,
 	if (sseu->slice_mask) {
 		sseu->eu_per_subslice = info->sseu.eu_per_subslice;
 		for (s = 0; s < fls(sseu->slice_mask); s++)
-			sseu_copy_subslices(&info->sseu, s,
-					    sseu->subslice_mask);
+			sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
 		sseu->eu_total = sseu->eu_per_subslice *
 				 intel_sseu_subslice_total(sseu);
 
@@ -208,7 +196,6 @@ static void i915_print_sseu_info(struct seq_file *m,
 				 const struct sseu_dev_info *sseu)
 {
 	const char *type = is_available_info ? "Available" : "Enabled";
-	int s;
 
 	seq_printf(m, "  %s Slice Mask: %04x\n", type,
 		   sseu->slice_mask);
@@ -216,10 +203,7 @@ static void i915_print_sseu_info(struct seq_file *m,
 		   hweight8(sseu->slice_mask));
 	seq_printf(m, "  %s Subslice Total: %u\n", type,
 		   intel_sseu_subslice_total(sseu));
-	for (s = 0; s < fls(sseu->slice_mask); s++) {
-		seq_printf(m, "  %s Slice%i subslices: %u\n", type,
-			   s, intel_sseu_subslices_per_slice(sseu, s));
-	}
+	intel_sseu_print_ss_info(type, sseu, m);
 	seq_printf(m, "  %s EU Total: %u\n", type,
 		   sseu->eu_total);
 	seq_printf(m, "  %s EU Per Subslice: %u\n", type,
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a604bc7c0701f..6e875d4f5f651 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -950,8 +950,8 @@ gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
 	 * on s/ss combo, the read should be done with read_subslice_reg.
 	 */
 	slice = ffs(sseu->slice_mask) - 1;
-	GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
-	subslice = ffs(intel_sseu_get_subslices(sseu, slice));
+	GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
+	subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
 	GEM_BUG_ON(!subslice);
 	subslice--;
 
@@ -1089,11 +1089,10 @@ static void
 icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
 {
 	const struct sseu_dev_info *sseu = &gt->info.sseu;
-	unsigned int slice, subslice;
+	unsigned int subslice;
 
 	GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
 	GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
-	slice = 0;
 
 	/*
 	 * Although a platform may have subslices, we need to always steer
@@ -1104,7 +1103,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
 	 * one of the higher subslices, we run the risk of reading back 0's or
 	 * random garbage.
 	 */
-	subslice = __ffs(intel_sseu_get_subslices(sseu, slice));
+	subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0));
 
 	/*
 	 * If the subslice we picked above also steers us to a valid L3 bank,
@@ -1114,7 +1113,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
 	if (gt->info.l3bank_mask & BIT(subslice))
 		gt->steering_table[L3BANK] = NULL;
 
-	__add_mcr_wa(gt, wal, slice, subslice);
+	__add_mcr_wa(gt, wal, 0, subslice);
 }
 
 static void
@@ -1122,7 +1121,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
 {
 	const struct sseu_dev_info *sseu = &gt->info.sseu;
 	unsigned long slice, subslice = 0, slice_mask = 0;
-	u64 dss_mask = 0;
 	u32 lncf_mask = 0;
 	int i;
 
@@ -1153,8 +1151,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
 	 */
 
 	/* Find the potential gslice candidates */
-	dss_mask = intel_sseu_get_subslices(sseu, 0);
-	slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE);
+	slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,
+						       GEN_DSS_PER_GSLICE);
 
 	/*
 	 * Find the potential LNCF candidates.  Either LNCF within a valid
@@ -1179,9 +1177,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
 	}
 
 	slice = __ffs(slice_mask);
-	subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE));
+	subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice);
 	WARN_ON(subslice > GEN_DSS_PER_GSLICE);
-	WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0);
 
 	__add_mcr_wa(gt, wal, slice, subslice);
 
@@ -2062,9 +2059,8 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 
 static bool needs_wa_1308578152(struct intel_engine_cs *engine)
 {
-	u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0);
-
-	return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0;
+	return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
+		GEN_DSS_PER_GSLICE;
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index ac9767c56619c..6fd15b39570c1 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -162,8 +162,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
 			return -EINVAL;
 
 		/* Only copy bits from the first slice */
-		memcpy(&value, sseu->subslice_mask,
-		       min(sseu->ss_stride, (u8)sizeof(value)));
+		value = intel_sseu_get_hsw_subslices(sseu, 0);
 		if (!value)
 			return -ENODEV;
 		break;
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 89c475d525b84..0094f67c63f2b 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -31,10 +31,11 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
 
 static int fill_topology_info(const struct sseu_dev_info *sseu,
 			      struct drm_i915_query_item *query_item,
-			      const u8 *subslice_mask)
+			      intel_sseu_ss_mask_t subslice_mask)
 {
 	struct drm_i915_query_topology_info topo;
 	u32 slice_length, subslice_length, eu_length, total_length;
+	int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
 	int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
 	int ret;
 
@@ -44,7 +45,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
 		return -ENODEV;
 
 	slice_length = sizeof(sseu->slice_mask);
-	subslice_length = sseu->max_slices * sseu->ss_stride;
+	subslice_length = sseu->max_slices * ss_stride;
 	eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
 	total_length = sizeof(topo) + slice_length + subslice_length +
 		       eu_length;
@@ -60,7 +61,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
 	topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
 
 	topo.subslice_offset = slice_length;
-	topo.subslice_stride = sseu->ss_stride;
+	topo.subslice_stride = ss_stride;
 	topo.eu_offset = slice_length + subslice_length;
 	topo.eu_stride = eu_stride;
 
@@ -72,9 +73,9 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
 			 &sseu->slice_mask, slice_length))
 		return -EFAULT;
 
-	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
-					 sizeof(topo) + slice_length),
-			 subslice_mask, subslice_length))
+	if (intel_sseu_copy_ssmask_to_user(u64_to_user_ptr(query_item->data_ptr +
+							   sizeof(topo) + slice_length),
+					   sseu))
 		return -EFAULT;
 
 	if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
-- 
GitLab


From 5ac342ef84d7dccd1ba43f5fa2dc10a6feda91e2 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Wed, 1 Jun 2022 08:07:25 -0700
Subject: [PATCH 0134/1731] drm/i915/pvc: Add SSEU changes

PVC splits the mask of enabled DSS over two registers.  It also changes
the meaning of the EU fuse register such that each bit represents a
single EU rather than a pair of EUs.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220601150725.521468-7-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h  |  1 +
 drivers/gpu/drm/i915/gt/intel_sseu.c     | 31 ++++++++++++++++++------
 drivers/gpu/drm/i915/gt/intel_sseu.h     |  2 +-
 drivers/gpu/drm/i915/i915_drv.h          |  2 ++
 drivers/gpu/drm/i915/i915_pci.c          |  3 ++-
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 6 files changed, 31 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 58e9b464d564c..6aa1ceaa8d271 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -561,6 +561,7 @@
 #define   GEN11_GT_VEBOX_DISABLE_MASK		(0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
 
 #define GEN12_GT_COMPUTE_DSS_ENABLE		_MMIO(0x9144)
+#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT		_MMIO(0x9148)
 
 #define GEN6_UCGCTL1				_MMIO(0x9400)
 #define   GEN6_GAMUNIT_CLOCK_GATE_DISABLE	(1 << 22)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 826d11f18817a..7ef75f0d9c9e0 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -210,27 +210,44 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
 	struct intel_uncore *uncore = gt->uncore;
 	u16 eu_en = 0;
 	u8 eu_en_fuse;
+	int num_compute_regs, num_geometry_regs;
 	int eu;
 
+	if (IS_PONTEVECCHIO(gt->i915)) {
+		num_geometry_regs = 0;
+		num_compute_regs = 2;
+	} else {
+		num_geometry_regs = 1;
+		num_compute_regs = 1;
+	}
+
 	/*
 	 * The concept of slice has been removed in Xe_HP.  To be compatible
 	 * with prior generations, assume a single slice across the entire
 	 * device. Then calculate out the DSS for each workload type within
 	 * that software slice.
 	 */
-	intel_sseu_set_info(sseu, 1, 32, 16);
+	intel_sseu_set_info(sseu, 1,
+			    32 * max(num_geometry_regs, num_compute_regs),
+			    16);
 	sseu->has_xehp_dss = 1;
 
-	xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
+	xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask,
+			   num_geometry_regs,
 			   GEN12_GT_GEOMETRY_DSS_ENABLE);
-	xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
-			   GEN12_GT_COMPUTE_DSS_ENABLE);
+	xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask,
+			   num_compute_regs,
+			   GEN12_GT_COMPUTE_DSS_ENABLE,
+			   XEHPC_GT_COMPUTE_DSS_ENABLE_EXT);
 
 	eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
 
-	for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
-		if (eu_en_fuse & BIT(eu))
-			eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
+	if (HAS_ONE_EU_PER_FUSE_BIT(gt->i915))
+		eu_en = eu_en_fuse;
+	else
+		for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
+			if (eu_en_fuse & BIT(eu))
+				eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
 
 	xehp_compute_sseu_info(sseu, eu_en);
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index f0e09b743faaa..aa87d3832d60d 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -33,7 +33,7 @@ struct drm_printer;
  * Maximum number of 32-bit registers used by hardware to express the
  * enabled/disabled subslices.
  */
-#define I915_MAX_SS_FUSE_REGS	1
+#define I915_MAX_SS_FUSE_REGS	2
 #define I915_MAX_SS_FUSE_BITS	(I915_MAX_SS_FUSE_REGS * 32)
 
 /* Maximum number of EUs that can exist within a subslice or DSS. */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ec1b3484fdafa..fbea4d1ede7c8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1422,6 +1422,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_3D_PIPELINE(i915)	(INTEL_INFO(i915)->has_3d_pipeline)
 
+#define HAS_ONE_EU_PER_FUSE_BIT(i915)	(INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
+
 /* i915_gem.c */
 void i915_gem_init_early(struct drm_i915_private *dev_priv);
 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 269d7c8f2f81d..177aefa6511e6 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1090,7 +1090,8 @@ static const struct intel_device_info ats_m_info = {
 	XE_HP_FEATURES, \
 	.dma_mask_size = 52, \
 	.has_3d_pipeline = 0, \
-	.has_l3_ccs_read = 1
+	.has_l3_ccs_read = 1, \
+	.has_one_eu_per_fuse_bit = 1
 
 __maybe_unused
 static const struct intel_device_info pvc_info = {
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 4e1c80966ab56..346f17f2dce8c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -158,6 +158,7 @@ enum intel_ppgtt_type {
 	func(has_logical_ring_elsq); \
 	func(has_media_ratio_mode); \
 	func(has_mslices); \
+	func(has_one_eu_per_fuse_bit); \
 	func(has_pooled_eu); \
 	func(has_pxp); \
 	func(has_rc6); \
-- 
GitLab


From b729cfee705a56c6204647ac486107a1f814af36 Mon Sep 17 00:00:00 2001
From: Stuart Summers <stuart.summers@intel.com>
Date: Wed, 1 Jun 2022 14:06:46 -0700
Subject: [PATCH 0135/1731] drm/i915: Add extra registers to GPU error dump
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Our internal teams have identified a few additional engine registers
that are worth inspecting in error state dumps during development &
debug.  Let's capture and print them as part of our error dump.

For simplicity we'll just dump these registers on gen11 and beyond.
Most of these registers have existed since earlier platforms (e.g., gen6
or gen7) but were initially introduced only for a subset of the
platforms' engines; gen11 seems to be where they became available on all
engines.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220601210646.615946-1-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/intel_engine_regs.h |  5 +++++
 drivers/gpu/drm/i915/i915_gpu_error.c       | 19 +++++++++++++++++++
 drivers/gpu/drm/i915/i915_gpu_error.h       |  7 +++++++
 3 files changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
index 44de10cf7837f..889f0df3940b8 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -8,6 +8,7 @@
 
 #include "i915_reg_defs.h"
 
+#define RING_EXCC(base)				_MMIO((base) + 0x28)
 #define RING_TAIL(base)				_MMIO((base) + 0x30)
 #define   TAIL_ADDR				0x001FFFF8
 #define RING_HEAD(base)				_MMIO((base) + 0x34)
@@ -133,6 +134,8 @@
 		(REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \
 		 REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1))
 
+#define RING_CSCMDOP(base)			_MMIO((base) + 0x20c)
+
 /*
  * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
  * The lsb of each can be considered a separate enabling bit for encryption.
@@ -149,6 +152,7 @@
 		 REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
 
 #define RING_PREDICATE_RESULT(base)		_MMIO((base) + 0x3b8) /* gen12+ */
+
 #define MI_PREDICATE_RESULT_2(base)		_MMIO((base) + 0x3bc)
 #define   LOWER_SLICE_ENABLED			(1 << 0)
 #define   LOWER_SLICE_DISABLED			(0 << 0)
@@ -172,6 +176,7 @@
 #define	  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT	REG_BIT(2)
 #define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	REG_BIT(3)
 #define	  GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE	REG_BIT(8)
+#define RING_CTX_SR_CTL(base)			_MMIO((base) + 0x244)
 #define RING_SEMA_WAIT_POLL(base)		_MMIO((base) + 0x24c)
 #define GEN8_RING_PDP_UDW(base, n)		_MMIO((base) + 0x270 + (n) * 8 + 4)
 #define GEN8_RING_PDP_LDW(base, n)		_MMIO((base) + 0x270 + (n) * 8)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 0512c66fa4f3f..bff8a111424a2 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -581,6 +581,15 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
 		err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
 		err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
 	}
+	if (GRAPHICS_VER(m->i915) >= 11) {
+		err_printf(m, "  NOPID: 0x%08x\n", ee->nopid);
+		err_printf(m, "  EXCC: 0x%08x\n", ee->excc);
+		err_printf(m, "  CMD_CCTL: 0x%08x\n", ee->cmd_cctl);
+		err_printf(m, "  CSCMDOP: 0x%08x\n", ee->cscmdop);
+		err_printf(m, "  CTX_SR_CTL: 0x%08x\n", ee->ctx_sr_ctl);
+		err_printf(m, "  DMA_FADDR_HI: 0x%08x\n", ee->dma_faddr_hi);
+		err_printf(m, "  DMA_FADDR_LO: 0x%08x\n", ee->dma_faddr_lo);
+	}
 	if (HAS_PPGTT(m->i915)) {
 		err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
 
@@ -1224,6 +1233,16 @@ static void engine_record_registers(struct intel_engine_coredump *ee)
 		ee->ipehr = ENGINE_READ(engine, IPEHR);
 	}
 
+	if (GRAPHICS_VER(i915) >= 11) {
+		ee->cmd_cctl = ENGINE_READ(engine, RING_CMD_CCTL);
+		ee->cscmdop = ENGINE_READ(engine, RING_CSCMDOP);
+		ee->ctx_sr_ctl = ENGINE_READ(engine, RING_CTX_SR_CTL);
+		ee->dma_faddr_hi = ENGINE_READ(engine, RING_DMA_FADD_UDW);
+		ee->dma_faddr_lo = ENGINE_READ(engine, RING_DMA_FADD);
+		ee->nopid = ENGINE_READ(engine, RING_NOPID);
+		ee->excc = ENGINE_READ(engine, RING_EXCC);
+	}
+
 	intel_engine_get_instdone(engine, &ee->instdone);
 
 	ee->instpm = ENGINE_READ(engine, RING_INSTPM);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h
index a611abacd9c2c..55a143b92d10e 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -84,6 +84,13 @@ struct intel_engine_coredump {
 	u32 fault_reg;
 	u64 faddr;
 	u32 rc_psmi; /* sleep state */
+	u32 nopid;
+	u32 excc;
+	u32 cmd_cctl;
+	u32 cscmdop;
+	u32 ctx_sr_ctl;
+	u32 dma_faddr_hi;
+	u32 dma_faddr_lo;
 	struct intel_instdone instdone;
 
 	/* GuC matched capture-lists info */
-- 
GitLab


From e8971a790370e805281dd650ec936a9b66435220 Mon Sep 17 00:00:00 2001
From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Date: Thu, 2 Jun 2022 19:27:19 +0530
Subject: [PATCH 0136/1731] drm/i915/display/adlp: More updates to voltage
 swing table

Voltage swing table updated for eDP HBR3

Bspec: 49291
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220602135719.1093081-1-balasubramani.vivekanandan@intel.com
---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 247093e9efe5a..006a2e9790003 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -933,9 +933,9 @@ static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_dp_hbr2_edp_h
 	{ .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },	/* 350   900      8.2   */
 	{ .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
 	{ .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
-	{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
-	{ .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
-	{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
+	{ .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },	/* 500   900      5.1   */
+	{ .icl = { 0xC, 0x63, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
+	{ .icl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } },	/* 600   900      3.5   */
 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
 };
 
-- 
GitLab


From b43edc504ddd8902d1f697364049b0c0b89de6e2 Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Thu, 2 Jun 2022 12:45:42 +0300
Subject: [PATCH 0137/1731] drm/i915/regs: split out intel audio register
 definitions

Split out audio registers to a header of its own to reduce the size of
i915_reg.h.

TODO: Remove direct audio register access from intel_ddi.c. However,
unification of audio get config is cumbersome due to the audio enable
bit being in the DP or HDMI registers on older platforms.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220602094542.1386151-1-jani.nikula@intel.com
---
 drivers/gpu/drm/i915/display/intel_audio.c    |   1 +
 .../gpu/drm/i915/display/intel_audio_regs.h   | 160 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_ddi.c      |   1 +
 drivers/gpu/drm/i915/i915_reg.h               | 151 -----------------
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c   |   2 +
 5 files changed, 164 insertions(+), 151 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_audio_regs.h

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index f0f0dfce27ce7..6c9ee905f132b 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -30,6 +30,7 @@
 #include "i915_drv.h"
 #include "intel_atomic.h"
 #include "intel_audio.h"
+#include "intel_audio_regs.h"
 #include "intel_cdclk.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/display/intel_audio_regs.h b/drivers/gpu/drm/i915/display/intel_audio_regs.h
new file mode 100644
index 0000000000000..d1e5844e3484f
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_audio_regs.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_AUDIO_REGS_H__
+#define __INTEL_AUDIO_REGS_H__
+
+#include "i915_reg_defs.h"
+
+#define G4X_AUD_VID_DID			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
+#define   INTEL_AUDIO_DEVCL		0x808629FB
+#define   INTEL_AUDIO_DEVBLC		0x80862801
+#define   INTEL_AUDIO_DEVCTG		0x80862802
+
+#define G4X_AUD_CNTL_ST			_MMIO(0x620B4)
+#define   G4X_ELDV_DEVCL_DEVBLC		(1 << 13)
+#define   G4X_ELDV_DEVCTG		(1 << 14)
+#define   G4X_ELD_ADDR_MASK		(0xf << 5)
+#define   G4X_ELD_ACK			(1 << 4)
+#define G4X_HDMIW_HDMIEDID		_MMIO(0x6210C)
+
+#define _IBX_HDMIW_HDMIEDID_A		0xE2050
+#define _IBX_HDMIW_HDMIEDID_B		0xE2150
+#define IBX_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
+						  _IBX_HDMIW_HDMIEDID_B)
+#define _IBX_AUD_CNTL_ST_A		0xE20B4
+#define _IBX_AUD_CNTL_ST_B		0xE21B4
+#define IBX_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
+						  _IBX_AUD_CNTL_ST_B)
+#define   IBX_ELD_BUFFER_SIZE_MASK	(0x1f << 10)
+#define   IBX_ELD_ADDRESS_MASK		(0x1f << 5)
+#define   IBX_ELD_ACK			(1 << 4)
+#define IBX_AUD_CNTL_ST2		_MMIO(0xE20C0)
+#define   IBX_CP_READY(port)		((1 << 1) << (((port) - 1) * 4))
+#define   IBX_ELD_VALID(port)		((1 << 0) << (((port) - 1) * 4))
+
+#define _CPT_HDMIW_HDMIEDID_A		0xE5050
+#define _CPT_HDMIW_HDMIEDID_B		0xE5150
+#define CPT_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
+#define _CPT_AUD_CNTL_ST_A		0xE50B4
+#define _CPT_AUD_CNTL_ST_B		0xE51B4
+#define CPT_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
+#define CPT_AUD_CNTRL_ST2		_MMIO(0xE50C0)
+
+#define _VLV_HDMIW_HDMIEDID_A		(VLV_DISPLAY_BASE + 0x62050)
+#define _VLV_HDMIW_HDMIEDID_B		(VLV_DISPLAY_BASE + 0x62150)
+#define VLV_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
+#define _VLV_AUD_CNTL_ST_A		(VLV_DISPLAY_BASE + 0x620B4)
+#define _VLV_AUD_CNTL_ST_B		(VLV_DISPLAY_BASE + 0x621B4)
+#define VLV_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
+#define VLV_AUD_CNTL_ST2		_MMIO(VLV_DISPLAY_BASE + 0x620C0)
+
+#define _IBX_AUD_CONFIG_A		0xe2000
+#define _IBX_AUD_CONFIG_B		0xe2100
+#define IBX_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
+#define _CPT_AUD_CONFIG_A		0xe5000
+#define _CPT_AUD_CONFIG_B		0xe5100
+#define CPT_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
+#define _VLV_AUD_CONFIG_A		(VLV_DISPLAY_BASE + 0x62000)
+#define _VLV_AUD_CONFIG_B		(VLV_DISPLAY_BASE + 0x62100)
+#define VLV_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
+
+#define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)
+#define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)
+#define   AUD_CONFIG_UPPER_N_SHIFT		20
+#define   AUD_CONFIG_UPPER_N_MASK		(0xff << 20)
+#define   AUD_CONFIG_LOWER_N_SHIFT		4
+#define   AUD_CONFIG_LOWER_N_MASK		(0xfff << 4)
+#define   AUD_CONFIG_N_MASK			(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
+#define   AUD_CONFIG_N(n) \
+	(((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) |	\
+	 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
+#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT	16
+#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK	(0xf << 16)
+#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25175	(0 << 16)
+#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25200	(1 << 16)
+#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27000	(2 << 16)
+#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27027	(3 << 16)
+#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54000	(4 << 16)
+#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54054	(5 << 16)
+#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74176	(6 << 16)
+#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74250	(7 << 16)
+#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148352	(8 << 16)
+#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148500	(9 << 16)
+#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_296703	(10 << 16)
+#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_297000	(11 << 16)
+#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_593407	(12 << 16)
+#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_594000	(13 << 16)
+#define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)
+
+#define _HSW_AUD_CONFIG_A		0x65000
+#define _HSW_AUD_CONFIG_B		0x65100
+#define HSW_AUD_CFG(trans)		_MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
+
+#define _HSW_AUD_MISC_CTRL_A		0x65010
+#define _HSW_AUD_MISC_CTRL_B		0x65110
+#define HSW_AUD_MISC_CTRL(trans)	_MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
+
+#define _HSW_AUD_M_CTS_ENABLE_A		0x65028
+#define _HSW_AUD_M_CTS_ENABLE_B		0x65128
+#define HSW_AUD_M_CTS_ENABLE(trans)	_MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
+#define   AUD_M_CTS_M_VALUE_INDEX	(1 << 21)
+#define   AUD_M_CTS_M_PROG_ENABLE	(1 << 20)
+#define   AUD_CONFIG_M_MASK		0xfffff
+
+#define _HSW_AUD_DIP_ELD_CTRL_ST_A	0x650b4
+#define _HSW_AUD_DIP_ELD_CTRL_ST_B	0x651b4
+#define HSW_AUD_DIP_ELD_CTRL(trans)	_MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
+
+/* Audio Digital Converter */
+#define _HSW_AUD_DIG_CNVT_1		0x65080
+#define _HSW_AUD_DIG_CNVT_2		0x65180
+#define AUD_DIG_CNVT(trans)		_MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
+#define DIP_PORT_SEL_MASK		0x3
+
+#define _HSW_AUD_EDID_DATA_A		0x65050
+#define _HSW_AUD_EDID_DATA_B		0x65150
+#define HSW_AUD_EDID_DATA(trans)	_MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
+
+#define HSW_AUD_PIPE_CONV_CFG		_MMIO(0x6507c)
+#define HSW_AUD_PIN_ELD_CP_VLD		_MMIO(0x650c0)
+#define   AUDIO_INACTIVE(trans)		((1 << 3) << ((trans) * 4))
+#define   AUDIO_OUTPUT_ENABLE(trans)	((1 << 2) << ((trans) * 4))
+#define   AUDIO_CP_READY(trans)		((1 << 1) << ((trans) * 4))
+#define   AUDIO_ELD_VALID(trans)	((1 << 0) << ((trans) * 4))
+
+#define _AUD_TCA_DP_2DOT0_CTRL		0x650bc
+#define _AUD_TCB_DP_2DOT0_CTRL		0x651bc
+#define AUD_DP_2DOT0_CTRL(trans)	_MMIO_TRANS(trans, _AUD_TCA_DP_2DOT0_CTRL, _AUD_TCB_DP_2DOT0_CTRL)
+#define  AUD_ENABLE_SDP_SPLIT		REG_BIT(31)
+
+#define HSW_AUD_CHICKENBIT			_MMIO(0x65f10)
+#define   SKL_AUD_CODEC_WAKE_SIGNAL		(1 << 15)
+
+#define AUD_FREQ_CNTRL			_MMIO(0x65900)
+#define AUD_PIN_BUF_CTL		_MMIO(0x48414)
+#define   AUD_PIN_BUF_ENABLE		REG_BIT(31)
+
+#define AUD_TS_CDCLK_M			_MMIO(0x65ea0)
+#define   AUD_TS_CDCLK_M_EN		REG_BIT(31)
+#define AUD_TS_CDCLK_N			_MMIO(0x65ea4)
+
+/* Display Audio Config Reg */
+#define AUD_CONFIG_BE			_MMIO(0x65ef0)
+#define HBLANK_EARLY_ENABLE_ICL(pipe)		(0x1 << (20 - (pipe)))
+#define HBLANK_EARLY_ENABLE_TGL(pipe)		(0x1 << (24 + (pipe)))
+#define HBLANK_START_COUNT_MASK(pipe)		(0x7 << (3 + ((pipe) * 6)))
+#define HBLANK_START_COUNT(pipe, val)		(((val) & 0x7) << (3 + ((pipe)) * 6))
+#define NUMBER_SAMPLES_PER_LINE_MASK(pipe)	(0x3 << ((pipe) * 6))
+#define NUMBER_SAMPLES_PER_LINE(pipe, val)	(((val) & 0x3) << ((pipe) * 6))
+
+#define HBLANK_START_COUNT_8	0
+#define HBLANK_START_COUNT_16	1
+#define HBLANK_START_COUNT_32	2
+#define HBLANK_START_COUNT_64	3
+#define HBLANK_START_COUNT_96	4
+#define HBLANK_START_COUNT_128	5
+
+#endif /* __INTEL_AUDIO_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 477edda29899f..132bf5a17d157 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -32,6 +32,7 @@
 
 #include "i915_drv.h"
 #include "intel_audio.h"
+#include "intel_audio_regs.h"
 #include "intel_backlight.h"
 #include "intel_combo_phy.h"
 #include "intel_combo_phy_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d2ab9f66294c..cc608e264e23e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6762,163 +6762,12 @@
 		(((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
 #define   GEN7_L3CDERRST1_ENABLE	(1 << 7)
 
-/* Audio */
-#define G4X_AUD_VID_DID			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
-#define   INTEL_AUDIO_DEVCL		0x808629FB
-#define   INTEL_AUDIO_DEVBLC		0x80862801
-#define   INTEL_AUDIO_DEVCTG		0x80862802
-
-#define G4X_AUD_CNTL_ST			_MMIO(0x620B4)
-#define   G4X_ELDV_DEVCL_DEVBLC		(1 << 13)
-#define   G4X_ELDV_DEVCTG		(1 << 14)
-#define   G4X_ELD_ADDR_MASK		(0xf << 5)
-#define   G4X_ELD_ACK			(1 << 4)
-#define G4X_HDMIW_HDMIEDID		_MMIO(0x6210C)
-
-#define _IBX_HDMIW_HDMIEDID_A		0xE2050
-#define _IBX_HDMIW_HDMIEDID_B		0xE2150
-#define IBX_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
-						  _IBX_HDMIW_HDMIEDID_B)
-#define _IBX_AUD_CNTL_ST_A		0xE20B4
-#define _IBX_AUD_CNTL_ST_B		0xE21B4
-#define IBX_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
-						  _IBX_AUD_CNTL_ST_B)
-#define   IBX_ELD_BUFFER_SIZE_MASK	(0x1f << 10)
-#define   IBX_ELD_ADDRESS_MASK		(0x1f << 5)
-#define   IBX_ELD_ACK			(1 << 4)
-#define IBX_AUD_CNTL_ST2		_MMIO(0xE20C0)
-#define   IBX_CP_READY(port)		((1 << 1) << (((port) - 1) * 4))
-#define   IBX_ELD_VALID(port)		((1 << 0) << (((port) - 1) * 4))
-
-#define _CPT_HDMIW_HDMIEDID_A		0xE5050
-#define _CPT_HDMIW_HDMIEDID_B		0xE5150
-#define CPT_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
-#define _CPT_AUD_CNTL_ST_A		0xE50B4
-#define _CPT_AUD_CNTL_ST_B		0xE51B4
-#define CPT_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
-#define CPT_AUD_CNTRL_ST2		_MMIO(0xE50C0)
-
-#define _VLV_HDMIW_HDMIEDID_A		(VLV_DISPLAY_BASE + 0x62050)
-#define _VLV_HDMIW_HDMIEDID_B		(VLV_DISPLAY_BASE + 0x62150)
-#define VLV_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
-#define _VLV_AUD_CNTL_ST_A		(VLV_DISPLAY_BASE + 0x620B4)
-#define _VLV_AUD_CNTL_ST_B		(VLV_DISPLAY_BASE + 0x621B4)
-#define VLV_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
-#define VLV_AUD_CNTL_ST2		_MMIO(VLV_DISPLAY_BASE + 0x620C0)
-
 /* These are the 4 32-bit write offset registers for each stream
  * output buffer.  It determines the offset from the
  * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
  */
 #define GEN7_SO_WRITE_OFFSET(n)		_MMIO(0x5280 + (n) * 4)
 
-#define _IBX_AUD_CONFIG_A		0xe2000
-#define _IBX_AUD_CONFIG_B		0xe2100
-#define IBX_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
-#define _CPT_AUD_CONFIG_A		0xe5000
-#define _CPT_AUD_CONFIG_B		0xe5100
-#define CPT_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
-#define _VLV_AUD_CONFIG_A		(VLV_DISPLAY_BASE + 0x62000)
-#define _VLV_AUD_CONFIG_B		(VLV_DISPLAY_BASE + 0x62100)
-#define VLV_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
-
-#define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)
-#define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)
-#define   AUD_CONFIG_UPPER_N_SHIFT		20
-#define   AUD_CONFIG_UPPER_N_MASK		(0xff << 20)
-#define   AUD_CONFIG_LOWER_N_SHIFT		4
-#define   AUD_CONFIG_LOWER_N_MASK		(0xfff << 4)
-#define   AUD_CONFIG_N_MASK			(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
-#define   AUD_CONFIG_N(n) \
-	(((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) |	\
-	 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
-#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT	16
-#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK	(0xf << 16)
-#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25175	(0 << 16)
-#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25200	(1 << 16)
-#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27000	(2 << 16)
-#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27027	(3 << 16)
-#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54000	(4 << 16)
-#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54054	(5 << 16)
-#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74176	(6 << 16)
-#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74250	(7 << 16)
-#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148352	(8 << 16)
-#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148500	(9 << 16)
-#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_296703	(10 << 16)
-#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_297000	(11 << 16)
-#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_593407	(12 << 16)
-#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_594000	(13 << 16)
-#define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)
-
-/* HSW Audio */
-#define _HSW_AUD_CONFIG_A		0x65000
-#define _HSW_AUD_CONFIG_B		0x65100
-#define HSW_AUD_CFG(trans)		_MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
-
-#define _HSW_AUD_MISC_CTRL_A		0x65010
-#define _HSW_AUD_MISC_CTRL_B		0x65110
-#define HSW_AUD_MISC_CTRL(trans)	_MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
-
-#define _HSW_AUD_M_CTS_ENABLE_A		0x65028
-#define _HSW_AUD_M_CTS_ENABLE_B		0x65128
-#define HSW_AUD_M_CTS_ENABLE(trans)	_MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
-#define   AUD_M_CTS_M_VALUE_INDEX	(1 << 21)
-#define   AUD_M_CTS_M_PROG_ENABLE	(1 << 20)
-#define   AUD_CONFIG_M_MASK		0xfffff
-
-#define _HSW_AUD_DIP_ELD_CTRL_ST_A	0x650b4
-#define _HSW_AUD_DIP_ELD_CTRL_ST_B	0x651b4
-#define HSW_AUD_DIP_ELD_CTRL(trans)	_MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
-
-/* Audio Digital Converter */
-#define _HSW_AUD_DIG_CNVT_1		0x65080
-#define _HSW_AUD_DIG_CNVT_2		0x65180
-#define AUD_DIG_CNVT(trans)		_MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
-#define DIP_PORT_SEL_MASK		0x3
-
-#define _HSW_AUD_EDID_DATA_A		0x65050
-#define _HSW_AUD_EDID_DATA_B		0x65150
-#define HSW_AUD_EDID_DATA(trans)	_MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
-
-#define HSW_AUD_PIPE_CONV_CFG		_MMIO(0x6507c)
-#define HSW_AUD_PIN_ELD_CP_VLD		_MMIO(0x650c0)
-#define   AUDIO_INACTIVE(trans)		((1 << 3) << ((trans) * 4))
-#define   AUDIO_OUTPUT_ENABLE(trans)	((1 << 2) << ((trans) * 4))
-#define   AUDIO_CP_READY(trans)		((1 << 1) << ((trans) * 4))
-#define   AUDIO_ELD_VALID(trans)	((1 << 0) << ((trans) * 4))
-
-#define _AUD_TCA_DP_2DOT0_CTRL		0x650bc
-#define _AUD_TCB_DP_2DOT0_CTRL		0x651bc
-#define AUD_DP_2DOT0_CTRL(trans)	_MMIO_TRANS(trans, _AUD_TCA_DP_2DOT0_CTRL, _AUD_TCB_DP_2DOT0_CTRL)
-#define  AUD_ENABLE_SDP_SPLIT		REG_BIT(31)
-
-#define HSW_AUD_CHICKENBIT			_MMIO(0x65f10)
-#define   SKL_AUD_CODEC_WAKE_SIGNAL		(1 << 15)
-
-#define AUD_FREQ_CNTRL			_MMIO(0x65900)
-#define AUD_PIN_BUF_CTL		_MMIO(0x48414)
-#define   AUD_PIN_BUF_ENABLE		REG_BIT(31)
-
-#define AUD_TS_CDCLK_M			_MMIO(0x65ea0)
-#define   AUD_TS_CDCLK_M_EN		REG_BIT(31)
-#define AUD_TS_CDCLK_N			_MMIO(0x65ea4)
-
-/* Display Audio Config Reg */
-#define AUD_CONFIG_BE			_MMIO(0x65ef0)
-#define HBLANK_EARLY_ENABLE_ICL(pipe)		(0x1 << (20 - (pipe)))
-#define HBLANK_EARLY_ENABLE_TGL(pipe)		(0x1 << (24 + (pipe)))
-#define HBLANK_START_COUNT_MASK(pipe)		(0x7 << (3 + ((pipe) * 6)))
-#define HBLANK_START_COUNT(pipe, val)		(((val) & 0x7) << (3 + ((pipe)) * 6))
-#define NUMBER_SAMPLES_PER_LINE_MASK(pipe)	(0x3 << ((pipe) * 6))
-#define NUMBER_SAMPLES_PER_LINE(pipe, val)	(((val) & 0x3) << ((pipe) * 6))
-
-#define HBLANK_START_COUNT_8	0
-#define HBLANK_START_COUNT_16	1
-#define HBLANK_START_COUNT_32	2
-#define HBLANK_START_COUNT_64	3
-#define HBLANK_START_COUNT_96	4
-#define HBLANK_START_COUNT_128	5
-
 /*
  * HSW - ICL power wells
  *
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 72dac1718f3e7..157e166672d7b 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -3,10 +3,12 @@
  * Copyright © 2020 Intel Corporation
  */
 
+#include "display/intel_audio_regs.h"
 #include "display/intel_dmc_regs.h"
 #include "display/vlv_dsi_pll_regs.h"
 #include "gt/intel_gt_regs.h"
 #include "gvt/gvt.h"
+
 #include "i915_drv.h"
 #include "i915_pvinfo.h"
 #include "i915_reg.h"
-- 
GitLab


From f7dad0daf2c2368f72828b0729799f01bdcee33b Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Thu, 2 Jun 2022 16:30:19 -0700
Subject: [PATCH 0138/1731] drm/i915/pvc: GuC depriv applies to PVC
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

We missed this setting in the initial device info patch's definition of
XE_HPC_FEATURES.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220602233019.1659283-1-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 177aefa6511e6..b8244f72e4329 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1090,6 +1090,7 @@ static const struct intel_device_info ats_m_info = {
 	XE_HP_FEATURES, \
 	.dma_mask_size = 52, \
 	.has_3d_pipeline = 0, \
+	.has_guc_deprivilege = 1, \
 	.has_l3_ccs_read = 1, \
 	.has_one_eu_per_fuse_bit = 1
 
-- 
GitLab


From a820190204aef0739aa3a067d00273d117f9367c Mon Sep 17 00:00:00 2001
From: "Leung, Martin" <Martin.Leung@amd.com>
Date: Fri, 13 May 2022 17:40:42 -0400
Subject: [PATCH 0139/1731] drm/amdgpu/display: Prepare for new interfaces

why:
lut pipeline will be hooked up differently in some asics
need to add new interfaces

how:
add them

Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Martin <martin.leung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  2 +
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 17 +++++-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 52 +++++++++++--------
 drivers/gpu/drm/amd/display/dc/dc.h           |  1 +
 .../display/dc/dce110/dce110_hw_sequencer.c   | 23 ++++++--
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 13 +++--
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h |  2 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h  |  4 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h   |  5 ++
 .../amd/display/dc/inc/hw_sequencer_private.h |  2 +
 10 files changed, 83 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 70be67a566737..661a35473c4db 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1507,6 +1507,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 		DRM_INFO("Seamless boot condition check passed\n");
 	}
 
+	init_data.flags.enable_mipi_converter_optimization = true;
+
 	INIT_LIST_HEAD(&adev->dm.da_list);
 	/* Display Core create. */
 	adev->dm.dc = dc_create(&init_data);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index a789ea8af27f1..55a8f58ee2392 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -235,7 +235,8 @@ bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 
 	if (link->connector_signal == SIGNAL_TYPE_EDP) {
 		/*in case it is not on*/
-		link->dc->hwss.edp_power_control(link, true);
+		if (!link->dc->config.edp_no_power_sequencing)
+			link->dc->hwss.edp_power_control(link, true);
 		link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 	}
 
@@ -1016,6 +1017,7 @@ static bool detect_link_and_local_sink(struct dc_link *link,
 	bool same_edid = false;
 	enum dc_edid_status edid_status;
 	struct dc_context *dc_ctx = link->ctx;
+	struct dc *dc = dc_ctx->dc;
 	struct dc_sink *sink = NULL;
 	struct dc_sink *prev_sink = NULL;
 	struct dpcd_caps prev_dpcd_caps;
@@ -1095,6 +1097,16 @@ static bool detect_link_and_local_sink(struct dc_link *link,
 
 			detect_edp_sink_caps(link);
 			read_current_link_settings_on_detect(link);
+
+			/* Disable power sequence on MIPI panel + converter
+			 */
+			if (dc->config.enable_mipi_converter_optimization &&
+				dc_ctx->dce_version == DCN_VERSION_3_01 &&
+				link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 &&
+				memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580,
+					sizeof(link->dpcd_caps.branch_dev_name)) == 0)
+				dc->config.edp_no_power_sequencing = true;
+
 			sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 			sink_caps.signal = SIGNAL_TYPE_EDP;
 			break;
@@ -1993,7 +2005,8 @@ static enum dc_status enable_link_dp(struct dc_state *state,
 
 	if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
 		/*in case it is not on*/
-		link->dc->hwss.edp_power_control(link, true);
+		if (!link->dc->config.edp_no_power_sequencing)
+			link->dc->hwss.edp_power_control(link, true);
 		link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 03eedffbb5b21..bea77172bd14f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2074,7 +2074,8 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
 	uint32_t wait_time = 0;
 	union lane_align_status_updated dpcd_lane_status_updated = {0};
 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
-	enum link_training_result status = LINK_TRAINING_SUCCESS;
+	enum dc_status status = DC_OK;
+	enum link_training_result result = LINK_TRAINING_SUCCESS;
 	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
 
 	/* Transmit 128b/132b_TPS1 over Main-Link */
@@ -2099,22 +2100,24 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
 			lt_settings->pattern_for_eq, DPRX);
 
 	/* poll for channel EQ done */
-	while (status == LINK_TRAINING_SUCCESS) {
+	while (result == LINK_TRAINING_SUCCESS) {
 		dp_wait_for_training_aux_rd_interval(link, aux_rd_interval);
 		wait_time += aux_rd_interval;
-		dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
+		status = dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
 				&dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
 		dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
 			lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
 		dpcd_128b_132b_get_aux_rd_interval(link, &aux_rd_interval);
-		if (dp_is_ch_eq_done(lt_settings->link_settings.lane_count,
+		if (status != DC_OK) {
+			result = LINK_TRAINING_ABORT;
+		} else if (dp_is_ch_eq_done(lt_settings->link_settings.lane_count,
 				dpcd_lane_status)) {
 			/* pass */
 			break;
 		} else if (loop_count >= lt_settings->eq_loop_count_limit) {
-			status = DP_128b_132b_MAX_LOOP_COUNT_REACHED;
+			result = DP_128b_132b_MAX_LOOP_COUNT_REACHED;
 		} else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) {
-			status = DP_128b_132b_LT_FAILED;
+			result = DP_128b_132b_LT_FAILED;
 		} else {
 			dp_set_hw_lane_settings(link, link_res, lt_settings, DPRX);
 			dpcd_set_lane_settings(link, lt_settings, DPRX);
@@ -2123,24 +2126,26 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
 	}
 
 	/* poll for EQ interlane align done */
-	while (status == LINK_TRAINING_SUCCESS) {
-		if (dpcd_lane_status_updated.bits.EQ_INTERLANE_ALIGN_DONE_128b_132b) {
+	while (result == LINK_TRAINING_SUCCESS) {
+		if (status != DC_OK) {
+			result = LINK_TRAINING_ABORT;
+		} else if (dpcd_lane_status_updated.bits.EQ_INTERLANE_ALIGN_DONE_128b_132b) {
 			/* pass */
 			break;
 		} else if (wait_time >= lt_settings->eq_wait_time_limit) {
-			status = DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT;
+			result = DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT;
 		} else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) {
-			status = DP_128b_132b_LT_FAILED;
+			result = DP_128b_132b_LT_FAILED;
 		} else {
 			dp_wait_for_training_aux_rd_interval(link,
 					lt_settings->eq_pattern_time);
 			wait_time += lt_settings->eq_pattern_time;
-			dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
+			status = dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
 					&dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
 		}
 	}
 
-	return status;
+	return result;
 }
 
 static enum link_training_result dp_perform_128b_132b_cds_done_sequence(
@@ -2149,7 +2154,8 @@ static enum link_training_result dp_perform_128b_132b_cds_done_sequence(
 		struct link_training_settings *lt_settings)
 {
 	/* Assumption: assume hardware has transmitted eq pattern */
-	enum link_training_result status = LINK_TRAINING_SUCCESS;
+	enum dc_status status = DC_OK;
+	enum link_training_result result = LINK_TRAINING_SUCCESS;
 	union lane_align_status_updated dpcd_lane_status_updated = {0};
 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
 	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
@@ -2159,24 +2165,26 @@ static enum link_training_result dp_perform_128b_132b_cds_done_sequence(
 	dpcd_set_training_pattern(link, lt_settings->pattern_for_cds);
 
 	/* poll for CDS interlane align done and symbol lock */
-	while (status == LINK_TRAINING_SUCCESS) {
+	while (result  == LINK_TRAINING_SUCCESS) {
 		dp_wait_for_training_aux_rd_interval(link,
 				lt_settings->cds_pattern_time);
 		wait_time += lt_settings->cds_pattern_time;
-		dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
+		status = dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
 						&dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
-		if (dp_is_symbol_locked(lt_settings->link_settings.lane_count, dpcd_lane_status) &&
+		if (status != DC_OK) {
+			result = LINK_TRAINING_ABORT;
+		} else if (dp_is_symbol_locked(lt_settings->link_settings.lane_count, dpcd_lane_status) &&
 				dpcd_lane_status_updated.bits.CDS_INTERLANE_ALIGN_DONE_128b_132b) {
 			/* pass */
 			break;
 		} else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) {
-			status = DP_128b_132b_LT_FAILED;
+			result = DP_128b_132b_LT_FAILED;
 		} else if (wait_time >= lt_settings->cds_wait_time_limit) {
-			status = DP_128b_132b_CDS_DONE_TIMEOUT;
+			result = DP_128b_132b_CDS_DONE_TIMEOUT;
 		}
 	}
 
-	return status;
+	return result;
 }
 
 static enum link_training_result dp_perform_8b_10b_link_training(
@@ -7099,7 +7107,8 @@ void dp_enable_link_phy(
 	unsigned int i;
 
 	if (link->connector_signal == SIGNAL_TYPE_EDP) {
-		link->dc->hwss.edp_power_control(link, true);
+		if (!link->dc->config.edp_no_power_sequencing)
+			link->dc->hwss.edp_power_control(link, true);
 		link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 	}
 
@@ -7226,7 +7235,8 @@ void dp_disable_link_phy(struct dc_link *link, const struct link_resource *link_
 			link->dc->hwss.edp_backlight_control(link, false);
 		if (link_hwss->ext.disable_dp_link_output)
 			link_hwss->ext.disable_dp_link_output(link, link_res, signal);
-		link->dc->hwss.edp_power_control(link, false);
+		if (!link->dc->config.edp_no_power_sequencing)
+			link->dc->hwss.edp_power_control(link, false);
 	} else {
 		if (dmcu != NULL && dmcu->funcs->lock_phy)
 			dmcu->funcs->lock_phy(dmcu);
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 817028d3c4a0c..11b02a98cf0f9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -337,6 +337,7 @@ struct dc_config {
 	bool is_single_rank_dimm;
 	bool use_pipe_ctx_sync_logic;
 	bool ignore_dpref_ss;
+	bool enable_mipi_converter_optimization;
 };
 
 enum visual_confirm {
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 7eff7811769d1..a76523c95ab26 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1245,8 +1245,18 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
 			 * has changed or they enter protection state and hang.
 			 */
 			msleep(60);
-		} else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP)
-			edp_receiver_ready_T9(link);
+		} else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
+			if (!link->dc->config.edp_no_power_sequencing) {
+				/*
+				 * Sometimes, DP receiver chip power-controlled externally by an
+				 * Embedded Controller could be treated and used as eDP,
+				 * if it drives mobile display. In this case,
+				 * we shouldn't be doing power-sequencing, hence we can skip
+				 * waiting for T9-ready.
+				 */
+				edp_receiver_ready_T9(link);
+			}
+		}
 	}
 
 }
@@ -2181,15 +2191,18 @@ static void dce110_setup_audio_dto(
 			build_audio_output(context, pipe_ctx, &audio_output);
 
 			if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
-				/* disable audio DTBCLK DTO */
-				dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
-					dc->res_pool->dccg, 0);
+				struct dtbclk_dto_params dto_params = {0};
 
 				pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
 						pipe_ctx->stream_res.audio,
 						pipe_ctx->stream->signal,
 						&audio_output.crtc_info,
 						&audio_output.pll_info);
+
+				dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
+					dc->res_pool->dccg,
+					&dto_params);
+
 			} else
 				pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
 					pipe_ctx->stream_res.audio,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index bbc58d167c630..4519ecef2e7b7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -513,7 +513,7 @@ void dccg31_set_physymclk(
 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
 static void dccg31_set_dtbclk_dto(
 		struct dccg *dccg,
-		struct dtbclk_dto_params *params)
+		const struct dtbclk_dto_params *params)
 {
 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 	int req_dtbclk_khz = params->pixclk_khz;
@@ -579,18 +579,17 @@ static void dccg31_set_dtbclk_dto(
 
 void dccg31_set_audio_dtbclk_dto(
 		struct dccg *dccg,
-		uint32_t req_audio_dtbclk_khz)
+		const struct dtbclk_dto_params *params)
 {
 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 
-	if (dccg->ref_dtbclk_khz && req_audio_dtbclk_khz) {
+	if (params->ref_dtbclk_khz && params->req_audio_dtbclk_khz) {
 		uint32_t modulo, phase;
 
 		// phase / modulo = dtbclk / dtbclk ref
-		modulo = dccg->ref_dtbclk_khz * 1000;
-		phase = div_u64((((unsigned long long)modulo * req_audio_dtbclk_khz) + dccg->ref_dtbclk_khz - 1),
-			dccg->ref_dtbclk_khz);
-
+		modulo = params->ref_dtbclk_khz * 1000;
+		phase = div_u64((((unsigned long long)modulo * params->req_audio_dtbclk_khz) + params->ref_dtbclk_khz - 1),
+			params->ref_dtbclk_khz);
 
 		REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, modulo);
 		REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, phase);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
index 269cabbea72ab..f158c1ea214b3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
@@ -192,7 +192,7 @@ void dccg31_set_physymclk(
 
 void dccg31_set_audio_dtbclk_dto(
 		struct dccg *dccg,
-		uint32_t req_audio_dtbclk_khz);
+		const struct dtbclk_dto_params *params);
 
 void dccg31_set_hdmistreamclk(
 		struct dccg *dccg,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index c7021915bac88..c1023cc84f553 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -120,11 +120,11 @@ struct dccg_funcs {
 
 	void (*set_dtbclk_dto)(
 			struct dccg *dccg,
-			struct dtbclk_dto_params *dto_params);
+			const struct dtbclk_dto_params *params);
 
 	void (*set_audio_dtbclk_dto)(
 			struct dccg *dccg,
-			uint32_t req_audio_dtbclk_khz);
+			const struct dtbclk_dto_params *params);
 
 	void (*set_dispclk_change_mode)(
 			struct dccg *dccg,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
index f5fd2a0673230..5097037e39625 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -346,6 +346,11 @@ struct mpc_funcs {
 			int mpcc_id,
 			const struct mpc_grph_gamut_adjustment *adjust);
 
+	bool (*program_1dlut)(
+			struct mpc *mpc,
+			const struct pwl_params *params,
+			uint32_t rmu_idx);
+
 	bool (*program_shaper)(
 			struct mpc *mpc,
 			const struct pwl_params *params,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
index 8c2f190c47124..d2cb0e7945000 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
@@ -140,6 +140,8 @@ struct hwseq_private_funcs {
 			const struct dc_plane_state *plane_state);
 	bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx,
 			const struct dc_plane_state *plane_state);
+	bool (*set_mcm_luts)(struct pipe_ctx *pipe_ctx,
+			const struct dc_plane_state *plane_state);
 	void (*PLAT_58856_wa)(struct dc_state *context,
 			struct pipe_ctx *pipe_ctx);
 	void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);
-- 
GitLab


From b8b64595d6a1ccd5cdf56c528e921332d1366b22 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Tue, 24 May 2022 10:10:18 -0400
Subject: [PATCH 0140/1731] drm/amdgpu: simplify
 amdgpu_device_asic_has_dc_support()

Drop extra cases in the default case.

Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 26 ----------------------
 1 file changed, 26 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 625424f3082b6..ce2293e92db62 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3322,32 +3322,6 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
 		 * cause regressions.
 		 */
 		return amdgpu_dc > 0;
-	case CHIP_HAWAII:
-	case CHIP_CARRIZO:
-	case CHIP_STONEY:
-	case CHIP_POLARIS10:
-	case CHIP_POLARIS11:
-	case CHIP_POLARIS12:
-	case CHIP_VEGAM:
-	case CHIP_TONGA:
-	case CHIP_FIJI:
-	case CHIP_VEGA10:
-	case CHIP_VEGA12:
-	case CHIP_VEGA20:
-#if defined(CONFIG_DRM_AMD_DC_DCN)
-	case CHIP_RAVEN:
-	case CHIP_NAVI10:
-	case CHIP_NAVI14:
-	case CHIP_NAVI12:
-	case CHIP_RENOIR:
-	case CHIP_CYAN_SKILLFISH:
-	case CHIP_SIENNA_CICHLID:
-	case CHIP_NAVY_FLOUNDER:
-	case CHIP_DIMGREY_CAVEFISH:
-	case CHIP_BEIGE_GOBY:
-	case CHIP_VANGOGH:
-	case CHIP_YELLOW_CARP:
-#endif
 	default:
 		return amdgpu_dc != 0;
 #else
-- 
GitLab


From ab9d97d6f9f1bb5de83411581dc6cdf425a83a15 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Tue, 24 May 2022 10:17:43 -0400
Subject: [PATCH 0141/1731] drm/amdgpu: convert
 sienna_cichlid_get_default_config_table_settings() to IP version

Use IP version rather than asic type.

Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 78f3d9e722bb7..6b452e3f5ee38 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -4192,7 +4192,7 @@ static int sienna_cichlid_get_default_config_table_settings(struct smu_context *
 	table->gfx_activity_average_tau = 10;
 	table->mem_activity_average_tau = 10;
 	table->socket_power_average_tau = 100;
-	if (adev->asic_type != CHIP_SIENNA_CICHLID)
+	if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7))
 		table->apu_socket_power_average_tau = 100;
 
 	return 0;
-- 
GitLab


From f74e78ca90bd21b47746b90c439709007681f44c Mon Sep 17 00:00:00 2001
From: Mitchell Augustin <kernel@mitchellaugustin.com>
Date: Wed, 25 May 2022 14:09:14 -0500
Subject: [PATCH 0142/1731] amdgpu: amdgpu_device.c: Removed trailing
 whitespace

Removed trailing whitespace from end of line in amdgpu_device.c

Signed-off-by: Mitchell Augustin <kernel@mitchellaugustin.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index ce2293e92db62..e9155dc1c30c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3343,7 +3343,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
  */
 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
 {
-	if (amdgpu_sriov_vf(adev) || 
+	if (amdgpu_sriov_vf(adev) ||
 	    adev->enable_virtual_display ||
 	    (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
 		return false;
-- 
GitLab


From d5fe83d26dae59c5b52105075e8950dea8ce7c19 Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Tue, 10 May 2022 16:08:50 +0800
Subject: [PATCH 0143/1731] drm/amd/pm: correct the way for retrieving current
 uclk frequency

There is some problem with average frequency reading. Thus, we
switch to the target frequency reading instead.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 7432b3e76d3d7..52b20fad7d1f2 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -840,7 +840,7 @@ static int smu_v13_0_0_read_sensor(struct smu_context *smu,
 		break;
 	case AMDGPU_PP_SENSOR_GFX_MCLK:
 		ret = smu_v13_0_0_get_smu_metrics_data(smu,
-						       METRICS_AVERAGE_UCLK,
+						       METRICS_CURR_UCLK,
 						       (uint32_t *)data);
 		*(uint32_t *)data *= 100;
 		*size = 4;
-- 
GitLab


From 66f54992981444cb418f31018e190d15c92d3599 Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Mon, 16 May 2022 09:50:31 +0800
Subject: [PATCH 0144/1731] drm/amd/pm: update SMU 13.0.0 driver_if header

To fit the latest 78.39.0 PMFW.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h  | 6 ++++++
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h                | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
index c1f76236da261..6a817c7ce1109 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
@@ -1359,8 +1359,14 @@ typedef struct {
   uint16_t AverageDclk0Frequency  ;
   uint16_t AverageVclk1Frequency  ;
   uint16_t AverageDclk1Frequency  ;
+  uint16_t PCIeBusy;
+  uint16_t dGPU_W_MAX;
+  uint16_t padding;
+
+  uint32_t MetricsCounter;
 
   uint16_t AvgVoltage[SVI_PLANE_COUNT];
+  uint16_t AvgCurrent[SVI_PLANE_COUNT];
 
   uint16_t AverageGfxActivity    ;
   uint16_t AverageUclkActivity   ;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index afa1991e26f98..036fd2810ecca 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -30,7 +30,7 @@
 #define SMU13_DRIVER_IF_VERSION_ALDE 0x08
 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x04
 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04
-#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x28
+#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x29
 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x28
 
 #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500  //500ms
-- 
GitLab


From e309434ac56774c86e79a50980e8611ce7cc31a3 Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Wed, 18 May 2022 11:40:54 +0800
Subject: [PATCH 0145/1731] drm/amd/pm: enable fclk ds feature for SMU 13.0.0

The feature is ready with latest 78.39.0 PMFW.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 52b20fad7d1f2..5c74a72577c68 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -300,6 +300,8 @@ smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu,
 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT);
 
+	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT);
+
 	return 0;
 }
 
-- 
GitLab


From faf26f2b12e1e03956f7e628183e422d94713e4b Mon Sep 17 00:00:00 2001
From: pengfuyuan <pengfuyuan@kylinos.cn>
Date: Thu, 26 May 2022 17:29:09 +0800
Subject: [PATCH 0146/1731] drm/amd: Fix spelling typo in comments

Fix spelling typo in comments.

Reported-by: k2ci <kernel-bot@kylinos.cn>
Signed-off-by: pengfuyuan <pengfuyuan@kylinos.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h                       | 2 +-
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c         | 2 +-
 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c               | 4 ++--
 drivers/gpu/drm/amd/display/modules/vmid/vmid.c           | 2 +-
 drivers/gpu/drm/amd/include/mes_api_def.h                 | 2 +-
 drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/arcturus_ppsmc.h | 2 +-
 6 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 30ce6bb6fa77a..3ec7427c018c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -274,7 +274,7 @@ extern int amdgpu_vcnfw_log;
 #define CIK_CURSOR_WIDTH 128
 #define CIK_CURSOR_HEIGHT 128
 
-/* smasrt shift bias level limits */
+/* smart shift bias level limits */
 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 661a35473c4db..1c23a844b1612 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6679,7 +6679,7 @@ static void dm_disable_vblank(struct drm_crtc *crtc)
 	dm_set_vblank(crtc, false);
 }
 
-/* Implemented only the options currently availible for the driver */
+/* Implemented only the options currently available for the driver */
 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
 	.reset = dm_crtc_reset_state,
 	.destroy = amdgpu_dm_crtc_destroy,
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index fa39a06eed1d4..d52cbc0e9b679 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -619,7 +619,7 @@ static int get_max_dsc_slices(union dsc_enc_slice_caps slice_caps)
 }
 
 
-// Increment sice number in available sice numbers stops if possible, or just increment if not
+// Increment slice number in available slice numbers stops if possible, or just increment if not
 static int inc_num_slices(union dsc_enc_slice_caps slice_caps, int num_slices)
 {
 	// Get next bigger num slices available in common caps
@@ -650,7 +650,7 @@ static int inc_num_slices(union dsc_enc_slice_caps slice_caps, int num_slices)
 }
 
 
-// Decrement sice number in available sice numbers stops if possible, or just decrement if not. Stop at zero.
+// Decrement slice number in available slice numbers stops if possible, or just decrement if not. Stop at zero.
 static int dec_num_slices(union dsc_enc_slice_caps slice_caps, int num_slices)
 {
 	// Get next bigger num slices available in common caps
diff --git a/drivers/gpu/drm/amd/display/modules/vmid/vmid.c b/drivers/gpu/drm/amd/display/modules/vmid/vmid.c
index 61ee4be35d27d..2c40212d86da1 100644
--- a/drivers/gpu/drm/amd/display/modules/vmid/vmid.c
+++ b/drivers/gpu/drm/amd/display/modules/vmid/vmid.c
@@ -66,7 +66,7 @@ static void evict_vmids(struct core_vmid *core_vmid)
 	}
 }
 
-// Return value of -1 indicates vmid table unitialized or ptb dne in the table
+// Return value of -1 indicates vmid table uninitialized or ptb dne in the table
 static int get_existing_vmid_for_ptb(struct core_vmid *core_vmid, uint64_t ptb)
 {
 	int i;
diff --git a/drivers/gpu/drm/amd/include/mes_api_def.h b/drivers/gpu/drm/amd/include/mes_api_def.h
index b2a8503feec06..bf3d6ad263f9c 100644
--- a/drivers/gpu/drm/amd/include/mes_api_def.h
+++ b/drivers/gpu/drm/amd/include/mes_api_def.h
@@ -33,7 +33,7 @@
  */
 enum { API_FRAME_SIZE_IN_DWORDS = 64 };
 
-/* To avoid command in scheduler context to be overwritten whenenver mutilple
+/* To avoid command in scheduler context to be overwritten whenever multiple
  * interrupts come in, this creates another queue.
  */
 enum { API_NUMBER_OF_COMMAND_MAX = 32 };
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/arcturus_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/arcturus_ppsmc.h
index 45f5d29bc7057..15b313baa0ee0 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/arcturus_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/arcturus_ppsmc.h
@@ -120,7 +120,7 @@
 #define PPSMC_MSG_ReadSerialNumTop32		 0x40
 #define PPSMC_MSG_ReadSerialNumBottom32		 0x41
 
-/* paramater for MSG_LightSBR
+/* parameter for MSG_LightSBR
  * 1 -- Enable light secondary bus reset, only do nbio respond without further handling,
  *      leave driver to handle the real reset
  * 0 -- Disable LightSBR, default behavior, SMU will pass the reset to PSP
-- 
GitLab


From 2f6247dad2c56cfe2df3c6e00586ead5ee905b46 Mon Sep 17 00:00:00 2001
From: "Stanley.Yang" <Stanley.Yang@amd.com>
Date: Fri, 20 May 2022 18:22:21 +0800
Subject: [PATCH 0147/1731] drm/amdgpu/pm: support mca_ceumc_addr in ecctable

SMU add a new variable mca_ceumc_addr to record
umc correctable error address in EccInfo table,
driver side add EccInfo_V2_t to support this feature

Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h       |  1 +
 .../inc/pmfw_if/smu13_driver_if_aldebaran.h   | 16 +++++-
 .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c    | 53 ++++++++++++++-----
 3 files changed, 57 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
index b9a6fac2b8b20..28e603243b672 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
@@ -328,6 +328,7 @@ struct ecc_info_per_ch {
 	uint16_t ce_count_hi_chip;
 	uint64_t mca_umc_status;
 	uint64_t mca_umc_addr;
+	uint64_t mca_ceumc_addr;
 };
 
 struct umc_ecc_info {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h
index 0f67c56c2863a..6f92038470ecf 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h
@@ -519,7 +519,21 @@ typedef struct {
 } EccInfo_t;
 
 typedef struct {
-	EccInfo_t  EccInfo[ALDEBARAN_UMC_CHANNEL_NUM];
+	uint64_t mca_umc_status;
+	uint64_t mca_umc_addr;
+	uint64_t mca_ceumc_addr;
+
+	uint16_t ce_count_lo_chip;
+	uint16_t ce_count_hi_chip;
+
+	uint32_t eccPadding;
+} EccInfo_V2_t;
+
+typedef struct {
+	union {
+		EccInfo_t  EccInfo[ALDEBARAN_UMC_CHANNEL_NUM];
+		EccInfo_V2_t EccInfo_V2[ALDEBARAN_UMC_CHANNEL_NUM];
+	};
 } EccInfoTable_t;
 
 // These defines are used with the following messages:
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index fb130409309c0..bf124bc98b804 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -82,6 +82,12 @@
  */
 #define SUPPORT_ECCTABLE_SMU_VERSION 0x00442a00
 
+/*
+ * SMU support mca_ceumc_addr in ECCTABLE since version 68.55.0,
+ * use this to check mca_ceumc_addr record whether support
+ */
+#define SUPPORT_ECCTABLE_V2_SMU_VERSION 0x00443700
+
 /*
  * SMU support BAD CHENNEL info MSG since version 68.51.00,
  * use this to check ECCTALE feature whether support
@@ -1803,7 +1809,8 @@ static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu,
 	return sizeof(struct gpu_metrics_v1_3);
 }
 
-static int aldebaran_check_ecc_table_support(struct smu_context *smu)
+static int aldebaran_check_ecc_table_support(struct smu_context *smu,
+		int *ecctable_version)
 {
 	uint32_t if_version = 0xff, smu_version = 0xff;
 	int ret = 0;
@@ -1816,6 +1823,11 @@ static int aldebaran_check_ecc_table_support(struct smu_context *smu)
 
 	if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION)
 		ret = -EOPNOTSUPP;
+	else if (smu_version >= SUPPORT_ECCTABLE_SMU_VERSION &&
+			smu_version < SUPPORT_ECCTABLE_V2_SMU_VERSION)
+		*ecctable_version = 1;
+	else
+		*ecctable_version = 2;
 
 	return ret;
 }
@@ -1827,9 +1839,10 @@ static ssize_t aldebaran_get_ecc_info(struct smu_context *smu,
 	EccInfoTable_t *ecc_table = NULL;
 	struct ecc_info_per_ch *ecc_info_per_channel = NULL;
 	int i, ret = 0;
+	int table_version = 0;
 	struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
 
-	ret = aldebaran_check_ecc_table_support(smu);
+	ret = aldebaran_check_ecc_table_support(smu, &table_version);
 	if (ret)
 		return ret;
 
@@ -1845,16 +1858,32 @@ static ssize_t aldebaran_get_ecc_info(struct smu_context *smu,
 
 	ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
 
-	for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) {
-		ecc_info_per_channel = &(eccinfo->ecc[i]);
-		ecc_info_per_channel->ce_count_lo_chip =
-			ecc_table->EccInfo[i].ce_count_lo_chip;
-		ecc_info_per_channel->ce_count_hi_chip =
-			ecc_table->EccInfo[i].ce_count_hi_chip;
-		ecc_info_per_channel->mca_umc_status =
-			ecc_table->EccInfo[i].mca_umc_status;
-		ecc_info_per_channel->mca_umc_addr =
-			ecc_table->EccInfo[i].mca_umc_addr;
+	if (table_version == 1) {
+		for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) {
+			ecc_info_per_channel = &(eccinfo->ecc[i]);
+			ecc_info_per_channel->ce_count_lo_chip =
+				ecc_table->EccInfo[i].ce_count_lo_chip;
+			ecc_info_per_channel->ce_count_hi_chip =
+				ecc_table->EccInfo[i].ce_count_hi_chip;
+			ecc_info_per_channel->mca_umc_status =
+				ecc_table->EccInfo[i].mca_umc_status;
+			ecc_info_per_channel->mca_umc_addr =
+				ecc_table->EccInfo[i].mca_umc_addr;
+		}
+	} else if (table_version == 2) {
+		for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) {
+			ecc_info_per_channel = &(eccinfo->ecc[i]);
+			ecc_info_per_channel->ce_count_lo_chip =
+				ecc_table->EccInfo_V2[i].ce_count_lo_chip;
+			ecc_info_per_channel->ce_count_hi_chip =
+				ecc_table->EccInfo_V2[i].ce_count_hi_chip;
+			ecc_info_per_channel->mca_umc_status =
+				ecc_table->EccInfo_V2[i].mca_umc_status;
+			ecc_info_per_channel->mca_umc_addr =
+				ecc_table->EccInfo_V2[i].mca_umc_addr;
+			ecc_info_per_channel->mca_ceumc_addr =
+				ecc_table->EccInfo_V2[i].mca_ceumc_addr;
+		}
 	}
 
 	return ret;
-- 
GitLab


From b801d8ad1b516a951535241c9cf60cac8f9a5c2b Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Mon, 21 Feb 2022 15:34:41 -0500
Subject: [PATCH 0148/1731] drm/amd: Add atomfirmware.h definitions needed for
 DCN32/321

Add new structures for DCN 3.2.x.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/include/atomfirmware.h | 209 ++++++++++++++++++---
 1 file changed, 187 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index ae8f6d299ed92..ff855cb21d3f9 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -726,18 +726,20 @@ struct vram_usagebyfirmware_v2_1
   ***************************************************************************
 */
 
-enum atom_object_record_type_id 
-{
-  ATOM_I2C_RECORD_TYPE =1,
-  ATOM_HPD_INT_RECORD_TYPE =2,
-  ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9,
-  ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16,
-  ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17,
-  ATOM_ENCODER_CAP_RECORD_TYPE=20,
-  ATOM_BRACKET_LAYOUT_RECORD_TYPE=21,
-  ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22,
-  ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE=23,
-  ATOM_RECORD_END_TYPE  =0xFF,
+enum atom_object_record_type_id {
+	ATOM_I2C_RECORD_TYPE = 1,
+	ATOM_HPD_INT_RECORD_TYPE = 2,
+	ATOM_CONNECTOR_CAP_RECORD_TYPE = 3,
+	ATOM_CONNECTOR_SPEED_UPTO = 4,
+	ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE = 9,
+	ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE = 16,
+	ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE = 17,
+	ATOM_ENCODER_CAP_RECORD_TYPE = 20,
+	ATOM_BRACKET_LAYOUT_RECORD_TYPE = 21,
+	ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE = 22,
+	ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE = 23,
+	ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE = 25,
+	ATOM_RECORD_END_TYPE = 0xFF,
 };
 
 struct atom_common_record_header
@@ -760,6 +762,19 @@ struct atom_hpd_int_record
   uint8_t  plugin_pin_state;
 };
 
+struct atom_connector_caps_record {
+	struct atom_common_record_header
+		record_header; //record_type = ATOM_CONN_CAP_RECORD_TYPE
+	uint16_t connector_caps; //01b if internal display is checked; 10b if internal BL is checked; 0 of Not
+};
+
+struct atom_connector_speed_record {
+	struct atom_common_record_header
+		record_header; //record_type = ATOM_CONN_SPEED_UPTO
+	uint32_t connector_max_speed; // connector Max speed attribute, it sets 8100 in Mhz when DP connector @8.1Ghz.
+	uint16_t reserved;
+};
+
 // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap
 enum atom_encoder_caps_def
 {
@@ -885,6 +900,21 @@ struct  atom_bracket_layout_record
   uint8_t reserved;
   struct atom_connector_layout_info  conn_info[1];
 };
+struct atom_bracket_layout_record_v2 {
+	struct atom_common_record_header
+		record_header; //record_type =  ATOM_BRACKET_LAYOUT_RECORD_TYPE
+	uint8_t bracketlen; //Bracket Length in mm
+	uint8_t bracketwidth; //Bracket Width in mm
+	uint8_t conn_num; //Connector numbering
+	uint8_t mini_type; //Mini Type (0 = Normal; 1 = Mini)
+	uint8_t reserved1;
+	uint8_t reserved2;
+};
+
+enum atom_connector_layout_info_mini_type_def {
+	MINI_TYPE_NORMAL = 0,
+	MINI_TYPE_MINI = 1,
+};
 
 enum atom_display_device_tag_def{
   ATOM_DISPLAY_LCD1_SUPPORT            = 0x0002, //an embedded display is either an LVDS or eDP signal type of display
@@ -911,6 +941,19 @@ struct atom_display_object_path_v2
   uint8_t  reserved;
 };
 
+struct atom_display_object_path_v3 {
+	uint16_t display_objid; //Connector Object ID or Misc Object ID
+	uint16_t disp_recordoffset;
+	uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder
+	uint16_t reserved1; //only on USBC case, otherwise always = 0
+	uint16_t reserved2; //reserved and always = 0
+	uint16_t reserved3; //reserved and always = 0
+	//a supported device vector, each display path starts with this.the paths are enumerated in the way of priority,
+	//a path appears first
+	uint16_t device_tag;
+	uint16_t reserved4; //reserved and always = 0
+};
+
 struct display_object_info_table_v1_4
 {
   struct    atom_common_table_header  table_header;
@@ -920,6 +963,15 @@ struct display_object_info_table_v1_4
   struct    atom_display_object_path_v2 display_path[8];   //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path
 };
 
+struct display_object_info_table_v1_5 {
+	struct atom_common_table_header table_header;
+	uint16_t supporteddevices;
+	uint8_t number_of_path;
+	uint8_t reserved;
+	// the real number of this included in the structure is calculated by using the
+	// (whole structure size - the header size- number_of_path)/size of atom_display_object_path
+	struct atom_display_object_path_v3 display_path[8];
+};
 
 /* 
   ***************************************************************************
@@ -1080,17 +1132,73 @@ struct atom_dc_golden_table_v1
 	uint32_t reserved[23];
 };
 
-enum dce_info_caps_def
+enum dce_info_caps_def {
+	// only for VBIOS
+	DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED = 0x02,
+	// only for VBIOS
+	DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 = 0x04,
+	// only for VBIOS
+	DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING = 0x08,
+	// only for VBIOS
+	DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE = 0x20,
+	DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40,
+};
+
+struct atom_display_controller_info_v4_5
 {
-  // only for VBIOS
-  DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED  =0x02,      
-  // only for VBIOS
-  DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2      =0x04,
-  // only for VBIOS
-  DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING   =0x08,
-  // only for VBIOS
-  DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE	 =0x20,
-  DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40,
+  struct  atom_common_table_header  table_header;
+  uint32_t display_caps;
+  uint32_t bootup_dispclk_10khz;
+  uint16_t dce_refclk_10khz;
+  uint16_t i2c_engine_refclk_10khz;
+  uint16_t dvi_ss_percentage;       // in unit of 0.001%
+  uint16_t dvi_ss_rate_10hz;
+  uint16_t hdmi_ss_percentage;      // in unit of 0.001%
+  uint16_t hdmi_ss_rate_10hz;
+  uint16_t dp_ss_percentage;        // in unit of 0.001%
+  uint16_t dp_ss_rate_10hz;
+  uint8_t  dvi_ss_mode;             // enum of atom_spread_spectrum_mode
+  uint8_t  hdmi_ss_mode;            // enum of atom_spread_spectrum_mode
+  uint8_t  dp_ss_mode;              // enum of atom_spread_spectrum_mode
+  uint8_t  ss_reserved;
+  // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
+  uint8_t  dfp_hardcode_mode_num;
+  // DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
+  uint8_t  dfp_hardcode_refreshrate;
+  // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
+  uint8_t  vga_hardcode_mode_num;
+  // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
+  uint8_t  vga_hardcode_refreshrate;
+  uint16_t dpphy_refclk_10khz;
+  uint16_t hw_chip_id;
+  uint8_t  dcnip_min_ver;
+  uint8_t  dcnip_max_ver;
+  uint8_t  max_disp_pipe_num;
+  uint8_t  max_vbios_active_disp_pipe_num;
+  uint8_t  max_ppll_num;
+  uint8_t  max_disp_phy_num;
+  uint8_t  max_aux_pairs;
+  uint8_t  remotedisplayconfig;
+  uint32_t dispclk_pll_vco_freq;
+  uint32_t dp_ref_clk_freq;
+  // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us)
+  uint32_t max_mclk_chg_lat;
+  // Worst case memory self refresh exit time, units of 100ns of ns (0.1us)
+  uint32_t max_sr_exit_lat;
+  // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us)
+  uint32_t max_sr_enter_exit_lat;
+  uint16_t dc_golden_table_offset;  // point of struct of atom_dc_golden_table_vxx
+  uint16_t dc_golden_table_ver;
+  uint32_t aux_dphy_rx_control0_val;
+  uint32_t aux_dphy_tx_control_val;
+  uint32_t aux_dphy_rx_control1_val;
+  uint32_t dc_gpio_aux_ctrl_0_val;
+  uint32_t dc_gpio_aux_ctrl_1_val;
+  uint32_t dc_gpio_aux_ctrl_2_val;
+  uint32_t dc_gpio_aux_ctrl_3_val;
+  uint32_t dc_gpio_aux_ctrl_4_val;
+  uint32_t dc_gpio_aux_ctrl_5_val;
+  uint32_t reserved[26];
 };
 
 /* 
@@ -1806,6 +1914,63 @@ struct atom_smu_info_v3_3 {
   uint32_t reserved;
 };
 
+struct atom_smu_info_v3_5
+{
+  struct   atom_common_table_header  table_header;
+  uint8_t  smuip_min_ver;
+  uint8_t  smuip_max_ver;
+  uint8_t  waflclk_ss_mode;
+  uint8_t  gpuclk_ss_mode;
+  uint16_t sclk_ss_percentage;
+  uint16_t sclk_ss_rate_10hz;
+  uint16_t gpuclk_ss_percentage;    // in unit of 0.001%
+  uint16_t gpuclk_ss_rate_10hz;
+  uint32_t core_refclk_10khz;
+  uint32_t syspll0_1_vco_freq_10khz;
+  uint32_t syspll0_2_vco_freq_10khz;
+  uint8_t  pcc_gpio_bit;            // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
+  uint8_t  pcc_gpio_polarity;       // GPIO polarity for CTF
+  uint16_t smugoldenoffset;
+  uint32_t syspll0_0_vco_freq_10khz;
+  uint32_t bootup_smnclk_10khz;
+  uint32_t bootup_socclk_10khz;
+  uint32_t bootup_mp0clk_10khz;
+  uint32_t bootup_mp1clk_10khz;
+  uint32_t bootup_lclk_10khz;
+  uint32_t bootup_dcefclk_10khz;
+  uint32_t ctf_threshold_override_value;
+  uint32_t syspll3_0_vco_freq_10khz;
+  uint32_t syspll3_1_vco_freq_10khz;
+  uint32_t bootup_fclk_10khz;
+  uint32_t bootup_waflclk_10khz;
+  uint32_t smu_info_caps;
+  uint16_t waflclk_ss_percentage;    // in unit of 0.001%
+  uint16_t smuinitoffset;
+  uint32_t bootup_dprefclk_10khz;
+  uint32_t bootup_usbclk_10khz;
+  uint32_t smb_slave_address;
+  uint32_t cg_fdo_ctrl0_val;
+  uint32_t cg_fdo_ctrl1_val;
+  uint32_t cg_fdo_ctrl2_val;
+  uint32_t gdfll_as_wait_ctrl_val;
+  uint32_t gdfll_as_step_ctrl_val;
+  uint32_t bootup_dtbclk_10khz;
+  uint32_t fclk_syspll_refclk_10khz;
+  uint32_t smusvi_svc0_val;
+  uint32_t smusvi_svc1_val;
+  uint32_t smusvi_svd0_val;
+  uint32_t smusvi_svd1_val;
+  uint32_t smusvi_svt0_val;
+  uint32_t smusvi_svt1_val;
+  uint32_t cg_tach_ctrl_val;
+  uint32_t cg_pump_ctrl1_val;
+  uint32_t cg_pump_tach_ctrl_val;
+  uint32_t thm_ctf_delay_val;
+  uint32_t thm_thermal_int_ctrl_val;
+  uint32_t thm_tmon_config_val;
+  uint32_t reserved[16];
+};
+
 struct atom_smu_info_v3_6
 {
 	struct   atom_common_table_header  table_header;
-- 
GitLab


From 79b470e5ee83e979f8ff465efa8b7ced160bcae7 Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Mon, 21 Feb 2022 15:49:20 -0500
Subject: [PATCH 0149/1731] drm/amd/display: Add DCN32/321 version identifiers

Add DCN3.2 asic identifiers.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dmub/dmub_srv.h       | 2 ++
 drivers/gpu/drm/amd/display/include/dal_asic_id.h | 8 ++++++++
 drivers/gpu/drm/amd/display/include/dal_types.h   | 2 ++
 3 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index f5cb8932bd5cb..7dbc9fb554595 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -100,6 +100,8 @@ enum dmub_asic {
 	DMUB_ASIC_DCN31B,
 	DMUB_ASIC_DCN315,
 	DMUB_ASIC_DCN316,
+	DMUB_ASIC_DCN32,
+	DMUB_ASIC_DCN321,
 	DMUB_ASIC_MAX,
 };
 
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 310f8779db671..11391eead954e 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -247,6 +247,14 @@ enum {
 
 #define ASICREV_IS_GC_10_3_7(eChipRev) ((eChipRev >= GC_10_3_7_A0) && (eChipRev < GC_10_3_7_UNKNOWN))
 
+#define AMDGPU_FAMILY_GC_11_0_0 145
+#define GC_11_0_0_A0 0x1
+#define GC_11_0_2_A0 0x10
+#define GC_11_UNKNOWN 0xFF
+
+#define ASICREV_IS_GC_11_0_0(eChipRev) (eChipRev < GC_11_0_2_A0)
+#define ASICREV_IS_GC_11_0_2(eChipRev) (eChipRev >= GC_11_0_2_A0 && eChipRev < GC_11_UNKNOWN)
+
 /*
  * ASIC chip ID
  */
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
index bf9085fc5105b..775c640fc820b 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -59,6 +59,8 @@ enum dce_version {
 	DCN_VERSION_3_1,
 	DCN_VERSION_3_15,
 	DCN_VERSION_3_16,
+	DCN_VERSION_3_2,
+	DCN_VERSION_3_21,
 	DCN_VERSION_MAX
 };
 
-- 
GitLab


From 4f29f9cf092b2d331ba2081566be3272962b7f96 Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Thu, 14 Apr 2022 15:19:16 -0400
Subject: [PATCH 0150/1731] drm/amd: add register headers for DCN32/321

Add register headers for DCN 3.2.0 and 3.2.1.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../include/asic_reg/dcn/dcn_3_2_0_offset.h   |  14675 +
 .../include/asic_reg/dcn/dcn_3_2_0_sh_mask.h  | 222890 +++++++++++++++
 .../include/asic_reg/dcn/dcn_3_2_1_offset.h   |  14559 +
 .../include/asic_reg/dcn/dcn_3_2_1_sh_mask.h  |  56578 ++++
 4 files changed, 308702 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h

diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h
new file mode 100644
index 0000000000000..6f84ea5c006f9
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h
@@ -0,0 +1,14675 @@
+/*
+ * Copyright (C) 2022  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dcn_3_2_0_OFFSET_HEADER
+#define _dcn_3_2_0_OFFSET_HEADER
+
+
+
+// addressBlock: dcn_dc_dccg_dccg_dfs_dispdec
+// base address: 0x0
+#define regDENTIST_DISPCLK_CNTL                                                                         0x0064
+#define regDENTIST_DISPCLK_CNTL_BASE_IDX                                                                1
+
+
+// addressBlock: dcn_dc_dccg_dccg_dispdec
+// base address: 0x0
+#define regPHYPLLA_PIXCLK_RESYNC_CNTL                                                                   0x0040
+#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regPHYPLLB_PIXCLK_RESYNC_CNTL                                                                   0x0041
+#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regPHYPLLC_PIXCLK_RESYNC_CNTL                                                                   0x0042
+#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regPHYPLLD_PIXCLK_RESYNC_CNTL                                                                   0x0043
+#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regDP_DTO_DBUF_EN                                                                               0x0044
+#define regDP_DTO_DBUF_EN_BASE_IDX                                                                      1
+#define regDSCCLK3_DTO_PARAM                                                                            0x0045
+#define regDSCCLK3_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPREFCLK_CGTT_BLK_CTRL_REG                                                                   0x0048
+#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                          1
+#define regDCCG_GATE_DISABLE_CNTL4                                                                      0x0049
+#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX                                                             1
+#define regDPSTREAMCLK_CNTL                                                                             0x004a
+#define regDPSTREAMCLK_CNTL_BASE_IDX                                                                    1
+#define regREFCLK_CGTT_BLK_CTRL_REG                                                                     0x004b
+#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regPHYPLLE_PIXCLK_RESYNC_CNTL                                                                   0x004c
+#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regDCCG_GLOBAL_FGCG_REP_CNTL                                                                    0x0050
+#define regDCCG_GLOBAL_FGCG_REP_CNTL_BASE_IDX                                                           1
+#define regDCCG_DS_DTO_INCR                                                                             0x0053
+#define regDCCG_DS_DTO_INCR_BASE_IDX                                                                    1
+#define regDCCG_DS_DTO_MODULO                                                                           0x0054
+#define regDCCG_DS_DTO_MODULO_BASE_IDX                                                                  1
+#define regDCCG_DS_CNTL                                                                                 0x0055
+#define regDCCG_DS_CNTL_BASE_IDX                                                                        1
+#define regDCCG_DS_HW_CAL_INTERVAL                                                                      0x0056
+#define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX                                                             1
+#define regDPREFCLK_CNTL                                                                                0x0058
+#define regDPREFCLK_CNTL_BASE_IDX                                                                       1
+#define regDCE_VERSION                                                                                  0x005e
+#define regDCE_VERSION_BASE_IDX                                                                         1
+#define regDCCG_GTC_CNTL                                                                                0x0060
+#define regDCCG_GTC_CNTL_BASE_IDX                                                                       1
+#define regDCCG_GTC_DTO_INCR                                                                            0x0061
+#define regDCCG_GTC_DTO_INCR_BASE_IDX                                                                   1
+#define regDCCG_GTC_DTO_MODULO                                                                          0x0062
+#define regDCCG_GTC_DTO_MODULO_BASE_IDX                                                                 1
+#define regDCCG_GTC_CURRENT                                                                             0x0063
+#define regDCCG_GTC_CURRENT_BASE_IDX                                                                    1
+#define regSYMCLK32_SE_CNTL                                                                             0x0065
+#define regSYMCLK32_SE_CNTL_BASE_IDX                                                                    1
+#define regSYMCLK32_LE_CNTL                                                                             0x0066
+#define regSYMCLK32_LE_CNTL_BASE_IDX                                                                    1
+#define regDTBCLK_P_CNTL                                                                                0x0068
+#define regDTBCLK_P_CNTL_BASE_IDX                                                                       1
+#define regDCCG_GATE_DISABLE_CNTL5                                                                      0x0069
+#define regDCCG_GATE_DISABLE_CNTL5_BASE_IDX                                                             1
+#define regDSCCLK0_DTO_PARAM                                                                            0x006c
+#define regDSCCLK0_DTO_PARAM_BASE_IDX                                                                   1
+#define regDSCCLK1_DTO_PARAM                                                                            0x006d
+#define regDSCCLK1_DTO_PARAM_BASE_IDX                                                                   1
+#define regDSCCLK2_DTO_PARAM                                                                            0x006e
+#define regDSCCLK2_DTO_PARAM_BASE_IDX                                                                   1
+#define regOTG_PIXEL_RATE_DIV                                                                           0x006f
+#define regOTG_PIXEL_RATE_DIV_BASE_IDX                                                                  1
+#define regMILLISECOND_TIME_BASE_DIV                                                                    0x0070
+#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX                                                           1
+#define regDISPCLK_FREQ_CHANGE_CNTL                                                                     0x0071
+#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX                                                            1
+#define regDC_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0072
+#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1
+#define regDCCG_GATE_DISABLE_CNTL                                                                       0x0074
+#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX                                                              1
+#define regDISPCLK_CGTT_BLK_CTRL_REG                                                                    0x0075
+#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                           1
+#define regSOCCLK_CGTT_BLK_CTRL_REG                                                                     0x0076
+#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regDCCG_CAC_STATUS                                                                              0x0077
+#define regDCCG_CAC_STATUS_BASE_IDX                                                                     1
+#define regMICROSECOND_TIME_BASE_DIV                                                                    0x007b
+#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX                                                           1
+#define regDCCG_GATE_DISABLE_CNTL2                                                                      0x007c
+#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX                                                             1
+#define regSYMCLK_CGTT_BLK_CTRL_REG                                                                     0x007d
+#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regDCCG_DISP_CNTL_REG                                                                           0x007f
+#define regDCCG_DISP_CNTL_REG_BASE_IDX                                                                  1
+#define regOTG0_PIXEL_RATE_CNTL                                                                         0x0080
+#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO0_PHASE                                                                                0x0081
+#define regDP_DTO0_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO0_MODULO                                                                               0x0082
+#define regDP_DTO0_MODULO_BASE_IDX                                                                      1
+#define regOTG0_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0083
+#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regOTG1_PIXEL_RATE_CNTL                                                                         0x0084
+#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO1_PHASE                                                                                0x0085
+#define regDP_DTO1_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO1_MODULO                                                                               0x0086
+#define regDP_DTO1_MODULO_BASE_IDX                                                                      1
+#define regOTG1_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0087
+#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regOTG2_PIXEL_RATE_CNTL                                                                         0x0088
+#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO2_PHASE                                                                                0x0089
+#define regDP_DTO2_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO2_MODULO                                                                               0x008a
+#define regDP_DTO2_MODULO_BASE_IDX                                                                      1
+#define regOTG2_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008b
+#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regOTG3_PIXEL_RATE_CNTL                                                                         0x008c
+#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO3_PHASE                                                                                0x008d
+#define regDP_DTO3_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO3_MODULO                                                                               0x008e
+#define regDP_DTO3_MODULO_BASE_IDX                                                                      1
+#define regOTG3_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008f
+#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regDPPCLK_CGTT_BLK_CTRL_REG                                                                     0x0098
+#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regDPPCLK0_DTO_PARAM                                                                            0x0099
+#define regDPPCLK0_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPPCLK1_DTO_PARAM                                                                            0x009a
+#define regDPPCLK1_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPPCLK2_DTO_PARAM                                                                            0x009b
+#define regDPPCLK2_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPPCLK3_DTO_PARAM                                                                            0x009c
+#define regDPPCLK3_DTO_PARAM_BASE_IDX                                                                   1
+#define regDCCG_CAC_STATUS2                                                                             0x009f
+#define regDCCG_CAC_STATUS2_BASE_IDX                                                                    1
+#define regSYMCLKA_CLOCK_ENABLE                                                                         0x00a0
+#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKB_CLOCK_ENABLE                                                                         0x00a1
+#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKC_CLOCK_ENABLE                                                                         0x00a2
+#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKD_CLOCK_ENABLE                                                                         0x00a3
+#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKE_CLOCK_ENABLE                                                                         0x00a4
+#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regDCCG_SOFT_RESET                                                                              0x00a6
+#define regDCCG_SOFT_RESET_BASE_IDX                                                                     1
+#define regDSCCLK_DTO_CTRL                                                                              0x00a7
+#define regDSCCLK_DTO_CTRL_BASE_IDX                                                                     1
+#define regDCCG_AUDIO_DTO_SOURCE                                                                        0x00ab
+#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX                                                               1
+#define regDCCG_AUDIO_DTO0_PHASE                                                                        0x00ac
+#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX                                                               1
+#define regDCCG_AUDIO_DTO0_MODULE                                                                       0x00ad
+#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX                                                              1
+#define regDCCG_AUDIO_DTO1_PHASE                                                                        0x00ae
+#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX                                                               1
+#define regDCCG_AUDIO_DTO1_MODULE                                                                       0x00af
+#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX                                                              1
+#define regDCCG_VSYNC_OTG0_LATCH_VALUE                                                                  0x00b0
+#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG1_LATCH_VALUE                                                                  0x00b1
+#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG2_LATCH_VALUE                                                                  0x00b2
+#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG3_LATCH_VALUE                                                                  0x00b3
+#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG4_LATCH_VALUE                                                                  0x00b4
+#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG5_LATCH_VALUE                                                                  0x00b5
+#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX                                                         1
+#define regDPPCLK_DTO_CTRL                                                                              0x00b6
+#define regDPPCLK_DTO_CTRL_BASE_IDX                                                                     1
+#define regDCCG_VSYNC_CNT_CTRL                                                                          0x00b8
+#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX                                                                 1
+#define regDCCG_VSYNC_CNT_INT_CTRL                                                                      0x00b9
+#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX                                                             1
+#define regFORCE_SYMCLK_DISABLE                                                                         0x00ba
+#define regFORCE_SYMCLK_DISABLE_BASE_IDX                                                                1
+#define regDCCG_TEST_CLK_SEL                                                                            0x00be
+#define regDCCG_TEST_CLK_SEL_BASE_IDX                                                                   1
+#define regDTBCLK_DTO0_PHASE                                                                            0x0018
+#define regDTBCLK_DTO0_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO1_PHASE                                                                            0x0019
+#define regDTBCLK_DTO1_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO2_PHASE                                                                            0x001a
+#define regDTBCLK_DTO2_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO3_PHASE                                                                            0x001b
+#define regDTBCLK_DTO3_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO0_MODULO                                                                           0x001f
+#define regDTBCLK_DTO0_MODULO_BASE_IDX                                                                  2
+#define regDTBCLK_DTO1_MODULO                                                                           0x0020
+#define regDTBCLK_DTO1_MODULO_BASE_IDX                                                                  2
+#define regDTBCLK_DTO2_MODULO                                                                           0x0021
+#define regDTBCLK_DTO2_MODULO_BASE_IDX                                                                  2
+#define regDTBCLK_DTO3_MODULO                                                                           0x0022
+#define regDTBCLK_DTO3_MODULO_BASE_IDX                                                                  2
+#define regHDMICHARCLK0_CLOCK_CNTL                                                                      0x004a
+#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX                                                             2
+#define regPHYASYMCLK_CLOCK_CNTL                                                                        0x0052
+#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYBSYMCLK_CLOCK_CNTL                                                                        0x0053
+#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYCSYMCLK_CLOCK_CNTL                                                                        0x0054
+#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYDSYMCLK_CLOCK_CNTL                                                                        0x0055
+#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYESYMCLK_CLOCK_CNTL                                                                        0x0056
+#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regHDMISTREAMCLK_CNTL                                                                           0x0059
+#define regHDMISTREAMCLK_CNTL_BASE_IDX                                                                  2
+#define regDCCG_GATE_DISABLE_CNTL3                                                                      0x005a
+#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX                                                             2
+#define regHDMISTREAMCLK0_DTO_PARAM                                                                     0x005b
+#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX                                                            2
+#define regDCCG_AUDIO_DTBCLK_DTO_PHASE                                                                  0x0061
+#define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX                                                         2
+#define regDCCG_AUDIO_DTBCLK_DTO_MODULO                                                                 0x0062
+#define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX                                                        2
+#define regDTBCLK_DTO_DBUF_EN                                                                           0x0063
+#define regDTBCLK_DTO_DBUF_EN_BASE_IDX                                                                  2
+#define regDMCUBCLK_CNTL                                                                                0x0067
+#define regDMCUBCLK_CNTL_BASE_IDX                                                                       2
+
+
+// addressBlock: dcn_dc_dmu_rbbmif_dispdec
+// base address: 0x0
+#define regRBBMIF_TIMEOUT                                                                               0x017f
+#define regRBBMIF_TIMEOUT_BASE_IDX                                                                      2
+#define regRBBMIF_STATUS                                                                                0x0180
+#define regRBBMIF_STATUS_BASE_IDX                                                                       2
+#define regRBBMIF_STATUS_2                                                                              0x0181
+#define regRBBMIF_STATUS_2_BASE_IDX                                                                     2
+#define regRBBMIF_INT_STATUS                                                                            0x0182
+#define regRBBMIF_INT_STATUS_BASE_IDX                                                                   2
+#define regRBBMIF_TIMEOUT_DIS                                                                           0x0183
+#define regRBBMIF_TIMEOUT_DIS_BASE_IDX                                                                  2
+#define regRBBMIF_TIMEOUT_DIS_2                                                                         0x0184
+#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX                                                                2
+#define regRBBMIF_STATUS_FLAG                                                                           0x0185
+#define regRBBMIF_STATUS_FLAG_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dmu_ihc_dispdec
+// base address: 0x0
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE                                                         0x0126
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX                                                2
+#define regDC_GPU_TIMER_START_POSITION_VSTARTUP                                                         0x0127
+#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX                                                2
+#define regDC_GPU_TIMER_READ                                                                            0x0128
+#define regDC_GPU_TIMER_READ_BASE_IDX                                                                   2
+#define regDC_GPU_TIMER_READ_CNTL                                                                       0x0129
+#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2
+#define regDISP_INTERRUPT_STATUS                                                                        0x012a
+#define regDISP_INTERRUPT_STATUS_BASE_IDX                                                               2
+#define regDISP_INTERRUPT_STATUS_CONTINUE                                                               0x012b
+#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
+#define regDISP_INTERRUPT_STATUS_CONTINUE2                                                              0x012c
+#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE3                                                              0x012d
+#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE4                                                              0x012e
+#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE5                                                              0x012f
+#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE6                                                              0x0130
+#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE7                                                              0x0131
+#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE8                                                              0x0132
+#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE9                                                              0x0133
+#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE10                                                             0x0134
+#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE11                                                             0x0135
+#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE12                                                             0x0136
+#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE13                                                             0x0137
+#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE14                                                             0x0138
+#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE15                                                             0x0139
+#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE16                                                             0x013a
+#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE17                                                             0x013b
+#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE18                                                             0x013c
+#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE19                                                             0x013d
+#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE20                                                             0x013e
+#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE21                                                             0x013f
+#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE22                                                             0x0140
+#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX                                                    2
+#define regDC_GPU_TIMER_START_POSITION_VREADY                                                           0x0141
+#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX                                                  2
+#define regDC_GPU_TIMER_START_POSITION_FLIP                                                             0x0142
+#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX                                                    2
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK                                                 0x0143
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX                                        2
+#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY                                                        0x0144
+#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX                                               2
+#define regDISP_INTERRUPT_STATUS_CONTINUE23                                                             0x0145
+#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE24                                                             0x0146
+#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE25                                                             0x0147
+#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX                                                    2
+#define regDCCG_INTERRUPT_DEST                                                                          0x0148
+#define regDCCG_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regDMU_INTERRUPT_DEST                                                                           0x0149
+#define regDMU_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regDMU_INTERRUPT_DEST2                                                                          0x014a
+#define regDMU_INTERRUPT_DEST2_BASE_IDX                                                                 2
+#define regDCPG_INTERRUPT_DEST                                                                          0x014b
+#define regDCPG_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regDCPG_INTERRUPT_DEST2                                                                         0x014c
+#define regDCPG_INTERRUPT_DEST2_BASE_IDX                                                                2
+#define regMMHUBBUB_INTERRUPT_DEST                                                                      0x014d
+#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX                                                             2
+#define regWB_INTERRUPT_DEST                                                                            0x014e
+#define regWB_INTERRUPT_DEST_BASE_IDX                                                                   2
+#define regDCHUB_INTERRUPT_DEST                                                                         0x014f
+#define regDCHUB_INTERRUPT_DEST_BASE_IDX                                                                2
+#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST                                                             0x0150
+#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                    2
+#define regDCHUB_INTERRUPT_DEST2                                                                        0x0151
+#define regDCHUB_INTERRUPT_DEST2_BASE_IDX                                                               2
+#define regDPP_PERFCOUNTER_INTERRUPT_DEST                                                               0x0152
+#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                      2
+#define regMPC_INTERRUPT_DEST                                                                           0x0153
+#define regMPC_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regOPP_INTERRUPT_DEST                                                                           0x0154
+#define regOPP_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regOPTC_INTERRUPT_DEST                                                                          0x0155
+#define regOPTC_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG0_INTERRUPT_DEST                                                                          0x0156
+#define regOTG0_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG1_INTERRUPT_DEST                                                                          0x0157
+#define regOTG1_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG2_INTERRUPT_DEST                                                                          0x0158
+#define regOTG2_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG3_INTERRUPT_DEST                                                                          0x0159
+#define regOTG3_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG4_INTERRUPT_DEST                                                                          0x015a
+#define regOTG4_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG5_INTERRUPT_DEST                                                                          0x015b
+#define regOTG5_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regDIG_INTERRUPT_DEST                                                                           0x015c
+#define regDIG_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regI2C_DDC_HPD_INTERRUPT_DEST                                                                   0x015d
+#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX                                                          2
+#define regDIO_INTERRUPT_DEST                                                                           0x015f
+#define regDIO_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regDCIO_INTERRUPT_DEST                                                                          0x0160
+#define regDCIO_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regHPD_INTERRUPT_DEST                                                                           0x0161
+#define regHPD_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regAZ_INTERRUPT_DEST                                                                            0x0162
+#define regAZ_INTERRUPT_DEST_BASE_IDX                                                                   2
+#define regAUX_INTERRUPT_DEST                                                                           0x0163
+#define regAUX_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regDSC_INTERRUPT_DEST                                                                           0x0164
+#define regDSC_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regHPO_INTERRUPT_DEST                                                                           0x0165
+#define regHPO_INTERRUPT_DEST_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dmu_dmu_misc_dispdec
+// base address: 0x0
+#define regCC_DC_PIPE_DIS                                                                               0x00ca
+#define regCC_DC_PIPE_DIS_BASE_IDX                                                                      2
+#define regDMU_CLK_CNTL                                                                                 0x00cb
+#define regDMU_CLK_CNTL_BASE_IDX                                                                        2
+#define regDMCUB_SMU_INTERRUPT_CNTL                                                                     0x00cd
+#define regDMCUB_SMU_INTERRUPT_CNTL_BASE_IDX                                                            2
+#define regSMU_INTERRUPT_CONTROL                                                                        0x00ce
+#define regSMU_INTERRUPT_CONTROL_BASE_IDX                                                               2
+#define regDMU_MISC_ALLOW_DS_FORCE                                                                      0x00d6
+#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_dmu_dc_pg_dispdec
+// base address: 0x0
+#define regDOMAIN0_PG_CONFIG                                                                            0x0080
+#define regDOMAIN0_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN0_PG_STATUS                                                                            0x0081
+#define regDOMAIN0_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN1_PG_CONFIG                                                                            0x0082
+#define regDOMAIN1_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN1_PG_STATUS                                                                            0x0083
+#define regDOMAIN1_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN2_PG_CONFIG                                                                            0x0084
+#define regDOMAIN2_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN2_PG_STATUS                                                                            0x0085
+#define regDOMAIN2_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN3_PG_CONFIG                                                                            0x0086
+#define regDOMAIN3_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN3_PG_STATUS                                                                            0x0087
+#define regDOMAIN3_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN16_PG_CONFIG                                                                           0x0089
+#define regDOMAIN16_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN16_PG_STATUS                                                                           0x008a
+#define regDOMAIN16_PG_STATUS_BASE_IDX                                                                  2
+#define regDOMAIN17_PG_CONFIG                                                                           0x008b
+#define regDOMAIN17_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN17_PG_STATUS                                                                           0x008c
+#define regDOMAIN17_PG_STATUS_BASE_IDX                                                                  2
+#define regDOMAIN18_PG_CONFIG                                                                           0x008d
+#define regDOMAIN18_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN18_PG_STATUS                                                                           0x008e
+#define regDOMAIN18_PG_STATUS_BASE_IDX                                                                  2
+#define regDOMAIN19_PG_CONFIG                                                                           0x008f
+#define regDOMAIN19_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN19_PG_STATUS                                                                           0x0090
+#define regDOMAIN19_PG_STATUS_BASE_IDX                                                                  2
+#define regDCPG_INTERRUPT_STATUS                                                                        0x0091
+#define regDCPG_INTERRUPT_STATUS_BASE_IDX                                                               2
+#define regDCPG_INTERRUPT_STATUS_2                                                                      0x0092
+#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX                                                             2
+#define regDCPG_INTERRUPT_CONTROL_1                                                                     0x0093
+#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX                                                            2
+#define regDCPG_INTERRUPT_CONTROL_3                                                                     0x0094
+#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX                                                            2
+#define regDC_IP_REQUEST_CNTL                                                                           0x0095
+#define regDC_IP_REQUEST_CNTL_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dmu_dmcub_dispdec
+// base address: 0x0
+#define regDMCUB_REGION0_OFFSET                                                                         0x018e
+#define regDMCUB_REGION0_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION0_OFFSET_HIGH                                                                    0x018f
+#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION1_OFFSET                                                                         0x0190
+#define regDMCUB_REGION1_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION1_OFFSET_HIGH                                                                    0x0191
+#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION2_OFFSET                                                                         0x0192
+#define regDMCUB_REGION2_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION2_OFFSET_HIGH                                                                    0x0193
+#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION4_OFFSET                                                                         0x0196
+#define regDMCUB_REGION4_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION4_OFFSET_HIGH                                                                    0x0197
+#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION5_OFFSET                                                                         0x0198
+#define regDMCUB_REGION5_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION5_OFFSET_HIGH                                                                    0x0199
+#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION6_OFFSET                                                                         0x019a
+#define regDMCUB_REGION6_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION6_OFFSET_HIGH                                                                    0x019b
+#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION7_OFFSET                                                                         0x019c
+#define regDMCUB_REGION7_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION7_OFFSET_HIGH                                                                    0x019d
+#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION0_TOP_ADDRESS                                                                    0x019e
+#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION1_TOP_ADDRESS                                                                    0x019f
+#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION2_TOP_ADDRESS                                                                    0x01a0
+#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION4_TOP_ADDRESS                                                                    0x01a1
+#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION5_TOP_ADDRESS                                                                    0x01a2
+#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION6_TOP_ADDRESS                                                                    0x01a3
+#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION7_TOP_ADDRESS                                                                    0x01a4
+#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION3_CW0_BASE_ADDRESS                                                               0x01a5
+#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW1_BASE_ADDRESS                                                               0x01a6
+#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW2_BASE_ADDRESS                                                               0x01a7
+#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW3_BASE_ADDRESS                                                               0x01a8
+#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW4_BASE_ADDRESS                                                               0x01a9
+#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW5_BASE_ADDRESS                                                               0x01aa
+#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW6_BASE_ADDRESS                                                               0x01ab
+#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW7_BASE_ADDRESS                                                               0x01ac
+#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW0_TOP_ADDRESS                                                                0x01ad
+#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW1_TOP_ADDRESS                                                                0x01ae
+#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW2_TOP_ADDRESS                                                                0x01af
+#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW3_TOP_ADDRESS                                                                0x01b0
+#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW4_TOP_ADDRESS                                                                0x01b1
+#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW5_TOP_ADDRESS                                                                0x01b2
+#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW6_TOP_ADDRESS                                                                0x01b3
+#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW7_TOP_ADDRESS                                                                0x01b4
+#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW0_OFFSET                                                                     0x01b5
+#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW0_OFFSET_HIGH                                                                0x01b6
+#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW1_OFFSET                                                                     0x01b7
+#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW1_OFFSET_HIGH                                                                0x01b8
+#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW2_OFFSET                                                                     0x01b9
+#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW2_OFFSET_HIGH                                                                0x01ba
+#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW3_OFFSET                                                                     0x01bb
+#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW3_OFFSET_HIGH                                                                0x01bc
+#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW4_OFFSET                                                                     0x01bd
+#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW4_OFFSET_HIGH                                                                0x01be
+#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW5_OFFSET                                                                     0x01bf
+#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW5_OFFSET_HIGH                                                                0x01c0
+#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW6_OFFSET                                                                     0x01c1
+#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW6_OFFSET_HIGH                                                                0x01c2
+#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW7_OFFSET                                                                     0x01c3
+#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW7_OFFSET_HIGH                                                                0x01c4
+#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_INTERRUPT_ENABLE                                                                       0x01c5
+#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX                                                              2
+#define regDMCUB_INTERRUPT_ACK                                                                          0x01c6
+#define regDMCUB_INTERRUPT_ACK_BASE_IDX                                                                 2
+#define regDMCUB_INTERRUPT_STATUS                                                                       0x01c7
+#define regDMCUB_INTERRUPT_STATUS_BASE_IDX                                                              2
+#define regDMCUB_INTERRUPT_TYPE                                                                         0x01c8
+#define regDMCUB_INTERRUPT_TYPE_BASE_IDX                                                                2
+#define regDMCUB_EXT_INTERRUPT_STATUS                                                                   0x01c9
+#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX                                                          2
+#define regDMCUB_EXT_INTERRUPT_CTXID                                                                    0x01ca
+#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX                                                           2
+#define regDMCUB_EXT_INTERRUPT_ACK                                                                      0x01cb
+#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX                                                             2
+#define regDMCUB_INST_FETCH_FAULT_ADDR                                                                  0x01cc
+#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX                                                         2
+#define regDMCUB_DATA_WRITE_FAULT_ADDR                                                                  0x01cd
+#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX                                                         2
+#define regDMCUB_SEC_CNTL                                                                               0x01ce
+#define regDMCUB_SEC_CNTL_BASE_IDX                                                                      2
+#define regDMCUB_MEM_CNTL                                                                               0x01cf
+#define regDMCUB_MEM_CNTL_BASE_IDX                                                                      2
+#define regDMCUB_INBOX0_BASE_ADDRESS                                                                    0x01d0
+#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_INBOX0_SIZE                                                                            0x01d1
+#define regDMCUB_INBOX0_SIZE_BASE_IDX                                                                   2
+#define regDMCUB_INBOX0_WPTR                                                                            0x01d2
+#define regDMCUB_INBOX0_WPTR_BASE_IDX                                                                   2
+#define regDMCUB_INBOX0_RPTR                                                                            0x01d3
+#define regDMCUB_INBOX0_RPTR_BASE_IDX                                                                   2
+#define regDMCUB_INBOX1_BASE_ADDRESS                                                                    0x01d4
+#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_INBOX1_SIZE                                                                            0x01d5
+#define regDMCUB_INBOX1_SIZE_BASE_IDX                                                                   2
+#define regDMCUB_INBOX1_WPTR                                                                            0x01d6
+#define regDMCUB_INBOX1_WPTR_BASE_IDX                                                                   2
+#define regDMCUB_INBOX1_RPTR                                                                            0x01d7
+#define regDMCUB_INBOX1_RPTR_BASE_IDX                                                                   2
+#define regDMCUB_OUTBOX0_BASE_ADDRESS                                                                   0x01d8
+#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX                                                          2
+#define regDMCUB_OUTBOX0_SIZE                                                                           0x01d9
+#define regDMCUB_OUTBOX0_SIZE_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX0_WPTR                                                                           0x01da
+#define regDMCUB_OUTBOX0_WPTR_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX0_RPTR                                                                           0x01db
+#define regDMCUB_OUTBOX0_RPTR_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX1_BASE_ADDRESS                                                                   0x01dc
+#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX                                                          2
+#define regDMCUB_OUTBOX1_SIZE                                                                           0x01dd
+#define regDMCUB_OUTBOX1_SIZE_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX1_WPTR                                                                           0x01de
+#define regDMCUB_OUTBOX1_WPTR_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX1_RPTR                                                                           0x01df
+#define regDMCUB_OUTBOX1_RPTR_BASE_IDX                                                                  2
+#define regDMCUB_TIMER_TRIGGER0                                                                         0x01e0
+#define regDMCUB_TIMER_TRIGGER0_BASE_IDX                                                                2
+#define regDMCUB_TIMER_TRIGGER1                                                                         0x01e1
+#define regDMCUB_TIMER_TRIGGER1_BASE_IDX                                                                2
+#define regDMCUB_TIMER_WINDOW                                                                           0x01e2
+#define regDMCUB_TIMER_WINDOW_BASE_IDX                                                                  2
+#define regDMCUB_SCRATCH0                                                                               0x01e3
+#define regDMCUB_SCRATCH0_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH1                                                                               0x01e4
+#define regDMCUB_SCRATCH1_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH2                                                                               0x01e5
+#define regDMCUB_SCRATCH2_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH3                                                                               0x01e6
+#define regDMCUB_SCRATCH3_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH4                                                                               0x01e7
+#define regDMCUB_SCRATCH4_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH5                                                                               0x01e8
+#define regDMCUB_SCRATCH5_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH6                                                                               0x01e9
+#define regDMCUB_SCRATCH6_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH7                                                                               0x01ea
+#define regDMCUB_SCRATCH7_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH8                                                                               0x01eb
+#define regDMCUB_SCRATCH8_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH9                                                                               0x01ec
+#define regDMCUB_SCRATCH9_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH10                                                                              0x01ed
+#define regDMCUB_SCRATCH10_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH11                                                                              0x01ee
+#define regDMCUB_SCRATCH11_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH12                                                                              0x01ef
+#define regDMCUB_SCRATCH12_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH13                                                                              0x01f0
+#define regDMCUB_SCRATCH13_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH14                                                                              0x01f1
+#define regDMCUB_SCRATCH14_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH15                                                                              0x01f2
+#define regDMCUB_SCRATCH15_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH16                                                                              0x01f3
+#define regDMCUB_SCRATCH16_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH17                                                                              0x01f4
+#define regDMCUB_SCRATCH17_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH18                                                                              0x01f5
+#define regDMCUB_SCRATCH18_BASE_IDX                                                                     2
+#define regDMCUB_CNTL                                                                                   0x01f6
+#define regDMCUB_CNTL_BASE_IDX                                                                          2
+#define regDMCUB_GPINT_DATAIN0                                                                          0x01f7
+#define regDMCUB_GPINT_DATAIN0_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN1                                                                          0x01f8
+#define regDMCUB_GPINT_DATAIN1_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAOUT                                                                          0x01f9
+#define regDMCUB_GPINT_DATAOUT_BASE_IDX                                                                 2
+#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR                                                           0x01fa
+#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX                                                  2
+#define regDMCUB_LS_WAKE_INT_ENABLE                                                                     0x01fb
+#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX                                                            2
+#define regDMCUB_MEM_PWR_CNTL                                                                           0x01fc
+#define regDMCUB_MEM_PWR_CNTL_BASE_IDX                                                                  2
+#define regDMCUB_TIMER_CURRENT                                                                          0x01fd
+#define regDMCUB_TIMER_CURRENT_BASE_IDX                                                                 2
+#define regDMCUB_PROC_ID                                                                                0x01ff
+#define regDMCUB_PROC_ID_BASE_IDX                                                                       2
+#define regDMCUB_CNTL2                                                                                  0x0200
+#define regDMCUB_CNTL2_BASE_IDX                                                                         2
+#define regDMCUB_GPINT_DATAIN2                                                                          0x0215
+#define regDMCUB_GPINT_DATAIN2_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN3                                                                          0x0216
+#define regDMCUB_GPINT_DATAIN3_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN4                                                                          0x0217
+#define regDMCUB_GPINT_DATAIN4_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN5                                                                          0x0218
+#define regDMCUB_GPINT_DATAIN5_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN6                                                                          0x0219
+#define regDMCUB_GPINT_DATAIN6_BASE_IDX                                                                 2
+#define regDMCUB_REGION3_TMR_AXI_SPACE                                                                  0x021a
+#define regDMCUB_REGION3_TMR_AXI_SPACE_BASE_IDX                                                         2
+#define regDMCUB_SCRATCH19                                                                              0x022e
+#define regDMCUB_SCRATCH19_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH20                                                                              0x022f
+#define regDMCUB_SCRATCH20_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH21                                                                              0x0230
+#define regDMCUB_SCRATCH21_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH22                                                                              0x0231
+#define regDMCUB_SCRATCH22_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH23                                                                              0x0232
+#define regDMCUB_SCRATCH23_BASE_IDX                                                                     2
+
+
+// addressBlock: dcn_dc_wb0_dispdec_dwb_top_dispdec
+// base address: 0x0
+#define regDWB_ENABLE_CLK_CTRL                                                                          0x3228
+#define regDWB_ENABLE_CLK_CTRL_BASE_IDX                                                                 2
+#define regDWB_MEM_PWR_CTRL                                                                             0x3229
+#define regDWB_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define regFC_MODE_CTRL                                                                                 0x322a
+#define regFC_MODE_CTRL_BASE_IDX                                                                        2
+#define regFC_FLOW_CTRL                                                                                 0x322b
+#define regFC_FLOW_CTRL_BASE_IDX                                                                        2
+#define regFC_WINDOW_START                                                                              0x322c
+#define regFC_WINDOW_START_BASE_IDX                                                                     2
+#define regFC_WINDOW_SIZE                                                                               0x322d
+#define regFC_WINDOW_SIZE_BASE_IDX                                                                      2
+#define regFC_SOURCE_SIZE                                                                               0x322e
+#define regFC_SOURCE_SIZE_BASE_IDX                                                                      2
+#define regDWB_UPDATE_CTRL                                                                              0x322f
+#define regDWB_UPDATE_CTRL_BASE_IDX                                                                     2
+#define regDWB_CRC_CTRL                                                                                 0x3230
+#define regDWB_CRC_CTRL_BASE_IDX                                                                        2
+#define regDWB_CRC_MASK_R_G                                                                             0x3231
+#define regDWB_CRC_MASK_R_G_BASE_IDX                                                                    2
+#define regDWB_CRC_MASK_B_A                                                                             0x3232
+#define regDWB_CRC_MASK_B_A_BASE_IDX                                                                    2
+#define regDWB_CRC_VAL_R_G                                                                              0x3233
+#define regDWB_CRC_VAL_R_G_BASE_IDX                                                                     2
+#define regDWB_CRC_VAL_B_A                                                                              0x3234
+#define regDWB_CRC_VAL_B_A_BASE_IDX                                                                     2
+#define regDWB_OUT_CTRL                                                                                 0x3235
+#define regDWB_OUT_CTRL_BASE_IDX                                                                        2
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN                                                             0x3236
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX                                                    2
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT                                                                0x3237
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX                                                       2
+#define regDWB_HOST_READ_CONTROL                                                                        0x3238
+#define regDWB_HOST_READ_CONTROL_BASE_IDX                                                               2
+#define regDWB_OVERFLOW_STATUS                                                                          0x3239
+#define regDWB_OVERFLOW_STATUS_BASE_IDX                                                                 2
+#define regDWB_OVERFLOW_COUNTER                                                                         0x323a
+#define regDWB_OVERFLOW_COUNTER_BASE_IDX                                                                2
+#define regDWB_SOFT_RESET                                                                               0x323b
+#define regDWB_SOFT_RESET_BASE_IDX                                                                      2
+
+
+// addressBlock: dcn_dc_wb0_dispdec_dwbcp_dispdec
+// base address: 0x0
+#define regDWB_HDR_MULT_COEF                                                                            0x3294
+#define regDWB_HDR_MULT_COEF_BASE_IDX                                                                   2
+#define regDWB_GAMUT_REMAP_MODE                                                                         0x3295
+#define regDWB_GAMUT_REMAP_MODE_BASE_IDX                                                                2
+#define regDWB_GAMUT_REMAP_COEF_FORMAT                                                                  0x3296
+#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                                         2
+#define regDWB_GAMUT_REMAPA_C11_C12                                                                     0x3297
+#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C13_C14                                                                     0x3298
+#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C21_C22                                                                     0x3299
+#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C23_C24                                                                     0x329a
+#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C31_C32                                                                     0x329b
+#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C33_C34                                                                     0x329c
+#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C11_C12                                                                     0x329d
+#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C13_C14                                                                     0x329e
+#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C21_C22                                                                     0x329f
+#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C23_C24                                                                     0x32a0
+#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C31_C32                                                                     0x32a1
+#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C33_C34                                                                     0x32a2
+#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX                                                            2
+#define regDWB_OGAM_CONTROL                                                                             0x32a3
+#define regDWB_OGAM_CONTROL_BASE_IDX                                                                    2
+#define regDWB_OGAM_LUT_INDEX                                                                           0x32a4
+#define regDWB_OGAM_LUT_INDEX_BASE_IDX                                                                  2
+#define regDWB_OGAM_LUT_DATA                                                                            0x32a5
+#define regDWB_OGAM_LUT_DATA_BASE_IDX                                                                   2
+#define regDWB_OGAM_LUT_CONTROL                                                                         0x32a6
+#define regDWB_OGAM_LUT_CONTROL_BASE_IDX                                                                2
+#define regDWB_OGAM_RAMA_START_CNTL_B                                                                   0x32a7
+#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_START_CNTL_G                                                                   0x32a8
+#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_START_CNTL_R                                                                   0x32a9
+#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_B                                                              0x32aa
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B                                                             0x32ab
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_G                                                              0x32ac
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G                                                             0x32ad
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_R                                                              0x32ae
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R                                                             0x32af
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMA_END_CNTL1_B                                                                    0x32b0
+#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL2_B                                                                    0x32b1
+#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL1_G                                                                    0x32b2
+#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL2_G                                                                    0x32b3
+#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL1_R                                                                    0x32b4
+#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL2_R                                                                    0x32b5
+#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_OFFSET_B                                                                       0x32b6
+#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMA_OFFSET_G                                                                       0x32b7
+#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMA_OFFSET_R                                                                       0x32b8
+#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMA_REGION_0_1                                                                     0x32b9
+#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_2_3                                                                     0x32ba
+#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_4_5                                                                     0x32bb
+#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_6_7                                                                     0x32bc
+#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_8_9                                                                     0x32bd
+#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_10_11                                                                   0x32be
+#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_12_13                                                                   0x32bf
+#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_14_15                                                                   0x32c0
+#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_16_17                                                                   0x32c1
+#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_18_19                                                                   0x32c2
+#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_20_21                                                                   0x32c3
+#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_22_23                                                                   0x32c4
+#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_24_25                                                                   0x32c5
+#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_26_27                                                                   0x32c6
+#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_28_29                                                                   0x32c7
+#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_30_31                                                                   0x32c8
+#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_32_33                                                                   0x32c9
+#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_CNTL_B                                                                   0x32ca
+#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_CNTL_G                                                                   0x32cb
+#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_CNTL_R                                                                   0x32cc
+#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_B                                                              0x32cd
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B                                                             0x32ce
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_G                                                              0x32cf
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G                                                             0x32d0
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_R                                                              0x32d1
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R                                                             0x32d2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMB_END_CNTL1_B                                                                    0x32d3
+#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL2_B                                                                    0x32d4
+#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL1_G                                                                    0x32d5
+#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL2_G                                                                    0x32d6
+#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL1_R                                                                    0x32d7
+#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL2_R                                                                    0x32d8
+#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_OFFSET_B                                                                       0x32d9
+#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMB_OFFSET_G                                                                       0x32da
+#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMB_OFFSET_R                                                                       0x32db
+#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMB_REGION_0_1                                                                     0x32dc
+#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_2_3                                                                     0x32dd
+#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_4_5                                                                     0x32de
+#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_6_7                                                                     0x32df
+#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_8_9                                                                     0x32e0
+#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_10_11                                                                   0x32e1
+#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_12_13                                                                   0x32e2
+#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_14_15                                                                   0x32e3
+#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_16_17                                                                   0x32e4
+#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_18_19                                                                   0x32e5
+#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_20_21                                                                   0x32e6
+#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_22_23                                                                   0x32e7
+#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_24_25                                                                   0x32e8
+#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_26_27                                                                   0x32e9
+#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_28_29                                                                   0x32ea
+#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_30_31                                                                   0x32eb
+#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_32_33                                                                   0x32ec
+#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_mmhubbub_vga_dispdec
+// base address: 0x0
+#define regVGA_MEM_WRITE_PAGE_ADDR                                                                      0x0000
+#define regVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX                                                             0
+#define regVGA_MEM_READ_PAGE_ADDR                                                                       0x0001
+#define regVGA_MEM_READ_PAGE_ADDR_BASE_IDX                                                              0
+#define regVGA_RENDER_CONTROL                                                                           0x0000
+#define regVGA_RENDER_CONTROL_BASE_IDX                                                                  1
+#define regVGA_SEQUENCER_RESET_CONTROL                                                                  0x0001
+#define regVGA_SEQUENCER_RESET_CONTROL_BASE_IDX                                                         1
+#define regVGA_MODE_CONTROL                                                                             0x0002
+#define regVGA_MODE_CONTROL_BASE_IDX                                                                    1
+#define regVGA_SURFACE_PITCH_SELECT                                                                     0x0003
+#define regVGA_SURFACE_PITCH_SELECT_BASE_IDX                                                            1
+#define regVGA_MEMORY_BASE_ADDRESS                                                                      0x0004
+#define regVGA_MEMORY_BASE_ADDRESS_BASE_IDX                                                             1
+#define regVGA_DISPBUF1_SURFACE_ADDR                                                                    0x0006
+#define regVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX                                                           1
+#define regVGA_DISPBUF2_SURFACE_ADDR                                                                    0x0008
+#define regVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX                                                           1
+#define regVGA_MEMORY_BASE_ADDRESS_HIGH                                                                 0x0009
+#define regVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX                                                        1
+#define regVGA_HDP_CONTROL                                                                              0x000a
+#define regVGA_HDP_CONTROL_BASE_IDX                                                                     1
+#define regVGA_CACHE_CONTROL                                                                            0x000b
+#define regVGA_CACHE_CONTROL_BASE_IDX                                                                   1
+#define regD1VGA_CONTROL                                                                                0x000c
+#define regD1VGA_CONTROL_BASE_IDX                                                                       1
+#define regD2VGA_CONTROL                                                                                0x000e
+#define regD2VGA_CONTROL_BASE_IDX                                                                       1
+#define regVGA_STATUS                                                                                   0x0010
+#define regVGA_STATUS_BASE_IDX                                                                          1
+#define regVGA_INTERRUPT_CONTROL                                                                        0x0011
+#define regVGA_INTERRUPT_CONTROL_BASE_IDX                                                               1
+#define regVGA_STATUS_CLEAR                                                                             0x0012
+#define regVGA_STATUS_CLEAR_BASE_IDX                                                                    1
+#define regVGA_INTERRUPT_STATUS                                                                         0x0013
+#define regVGA_INTERRUPT_STATUS_BASE_IDX                                                                1
+#define regVGA_MAIN_CONTROL                                                                             0x0014
+#define regVGA_MAIN_CONTROL_BASE_IDX                                                                    1
+#define regVGA_TEST_CONTROL                                                                             0x0015
+#define regVGA_TEST_CONTROL_BASE_IDX                                                                    1
+#define regVGA_QOS_CTRL                                                                                 0x0018
+#define regVGA_QOS_CTRL_BASE_IDX                                                                        1
+#define regCRTC8_IDX                                                                                    0x002d
+#define regCRTC8_IDX_BASE_IDX                                                                           1
+#define regCRTC8_DATA                                                                                   0x002d
+#define regCRTC8_DATA_BASE_IDX                                                                          1
+#define regGENFC_WT                                                                                     0x002e
+#define regGENFC_WT_BASE_IDX                                                                            1
+#define regGENS1                                                                                        0x002e
+#define regGENS1_BASE_IDX                                                                               1
+#define regATTRDW                                                                                       0x0030
+#define regATTRDW_BASE_IDX                                                                              1
+#define regATTRX                                                                                        0x0030
+#define regATTRX_BASE_IDX                                                                               1
+#define regATTRDR                                                                                       0x0030
+#define regATTRDR_BASE_IDX                                                                              1
+#define regGENMO_WT                                                                                     0x0030
+#define regGENMO_WT_BASE_IDX                                                                            1
+#define regGENS0                                                                                        0x0030
+#define regGENS0_BASE_IDX                                                                               1
+#define regGENENB                                                                                       0x0030
+#define regGENENB_BASE_IDX                                                                              1
+#define regSEQ8_IDX                                                                                     0x0031
+#define regSEQ8_IDX_BASE_IDX                                                                            1
+#define regSEQ8_DATA                                                                                    0x0031
+#define regSEQ8_DATA_BASE_IDX                                                                           1
+#define regDAC_MASK                                                                                     0x0031
+#define regDAC_MASK_BASE_IDX                                                                            1
+#define regDAC_R_INDEX                                                                                  0x0031
+#define regDAC_R_INDEX_BASE_IDX                                                                         1
+#define regDAC_W_INDEX                                                                                  0x0032
+#define regDAC_W_INDEX_BASE_IDX                                                                         1
+#define regDAC_DATA                                                                                     0x0032
+#define regDAC_DATA_BASE_IDX                                                                            1
+#define regGENFC_RD                                                                                     0x0032
+#define regGENFC_RD_BASE_IDX                                                                            1
+#define regGENMO_RD                                                                                     0x0033
+#define regGENMO_RD_BASE_IDX                                                                            1
+#define regGRPH8_IDX                                                                                    0x0033
+#define regGRPH8_IDX_BASE_IDX                                                                           1
+#define regGRPH8_DATA                                                                                   0x0033
+#define regGRPH8_DATA_BASE_IDX                                                                          1
+#define regCRTC8_IDX_1                                                                                  0x0035
+#define regCRTC8_IDX_1_BASE_IDX                                                                         1
+#define regCRTC8_DATA_1                                                                                 0x0035
+#define regCRTC8_DATA_1_BASE_IDX                                                                        1
+#define regGENFC_WT_1                                                                                   0x0036
+#define regGENFC_WT_1_BASE_IDX                                                                          1
+#define regGENS1_1                                                                                      0x0036
+#define regGENS1_1_BASE_IDX                                                                             1
+#define regD3VGA_CONTROL                                                                                0x0038
+#define regD3VGA_CONTROL_BASE_IDX                                                                       1
+#define regD4VGA_CONTROL                                                                                0x0039
+#define regD4VGA_CONTROL_BASE_IDX                                                                       1
+#define regD5VGA_CONTROL                                                                                0x003a
+#define regD5VGA_CONTROL_BASE_IDX                                                                       1
+#define regD6VGA_CONTROL                                                                                0x003b
+#define regD6VGA_CONTROL_BASE_IDX                                                                       1
+#define regVGA_SOURCE_SELECT                                                                            0x003c
+#define regVGA_SOURCE_SELECT_BASE_IDX                                                                   1
+
+
+// addressBlock: dcn_dc_mmhubbub_vgaif_dispdec
+// base address: 0x0
+#define regMCIF_CONTROL                                                                                 0x034a
+#define regMCIF_CONTROL_BASE_IDX                                                                        2
+#define regMCIF_WRITE_COMBINE_CONTROL                                                                   0x034b
+#define regMCIF_WRITE_COMBINE_CONTROL_BASE_IDX                                                          2
+#define regMCIF_PHASE0_OUTSTANDING_COUNTER                                                              0x034e
+#define regMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+#define regMCIF_PHASE1_OUTSTANDING_COUNTER                                                              0x034f
+#define regMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+#define regMCIF_PHASE2_OUTSTANDING_COUNTER                                                              0x0350
+#define regMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_mmhubbub_mcif_wb0_dispdec
+// base address: 0x0
+#define regMCIF_WB_BUFMGR_SW_CONTROL                                                                    0x0272
+#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                           2
+#define regMCIF_WB_BUFMGR_STATUS                                                                        0x0274
+#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_PITCH                                                                            0x0275
+#define regMCIF_WB_BUF_PITCH_BASE_IDX                                                                   2
+#define regMCIF_WB_BUF_1_STATUS                                                                         0x0276
+#define regMCIF_WB_BUF_1_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_1_STATUS2                                                                        0x0277
+#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_2_STATUS                                                                         0x0278
+#define regMCIF_WB_BUF_2_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_2_STATUS2                                                                        0x0279
+#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_3_STATUS                                                                         0x027a
+#define regMCIF_WB_BUF_3_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_3_STATUS2                                                                        0x027b
+#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_4_STATUS                                                                         0x027c
+#define regMCIF_WB_BUF_4_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_4_STATUS2                                                                        0x027d
+#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_ARBITRATION_CONTROL                                                                  0x027e
+#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                         2
+#define regMCIF_WB_SCLK_CHANGE                                                                          0x027f
+#define regMCIF_WB_SCLK_CHANGE_BASE_IDX                                                                 2
+#define regMCIF_WB_TEST_DEBUG_INDEX                                                                     0x0280
+#define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX                                                            2
+#define regMCIF_WB_TEST_DEBUG_DATA                                                                      0x0281
+#define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX                                                             2
+#define regMCIF_WB_BUF_1_ADDR_Y                                                                         0x0282
+#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_1_ADDR_C                                                                         0x0284
+#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_2_ADDR_Y                                                                         0x0286
+#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_2_ADDR_C                                                                         0x0288
+#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_3_ADDR_Y                                                                         0x028a
+#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_3_ADDR_C                                                                         0x028c
+#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_4_ADDR_Y                                                                         0x028e
+#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_4_ADDR_C                                                                         0x0290
+#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUFMGR_VCE_CONTROL                                                                   0x0292
+#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                          2
+#define regMCIF_WB_NB_PSTATE_CONTROL                                                                    0x0293
+#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                           2
+#define regMCIF_WB_CLOCK_GATER_CONTROL                                                                  0x0294
+#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                         2
+#define regMCIF_WB_SELF_REFRESH_CONTROL                                                                 0x0296
+#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                                        2
+#define regMULTI_LEVEL_QOS_CTRL                                                                         0x0297
+#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX                                                                2
+#define regMCIF_WB_SECURITY_LEVEL                                                                       0x0298
+#define regMCIF_WB_SECURITY_LEVEL_BASE_IDX                                                              2
+#define regMCIF_WB_BUF_LUMA_SIZE                                                                        0x0299
+#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_CHROMA_SIZE                                                                      0x029a
+#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                             2
+#define regMCIF_WB_BUF_1_ADDR_Y_HIGH                                                                    0x029b
+#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_1_ADDR_C_HIGH                                                                    0x029c
+#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_2_ADDR_Y_HIGH                                                                    0x029d
+#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_2_ADDR_C_HIGH                                                                    0x029e
+#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_3_ADDR_Y_HIGH                                                                    0x029f
+#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_3_ADDR_C_HIGH                                                                    0x02a0
+#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_4_ADDR_Y_HIGH                                                                    0x02a1
+#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_4_ADDR_C_HIGH                                                                    0x02a2
+#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_1_RESOLUTION                                                                     0x02a3
+#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_BUF_2_RESOLUTION                                                                     0x02a4
+#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_BUF_3_RESOLUTION                                                                     0x02a5
+#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_BUF_4_RESOLUTION                                                                     0x02a6
+#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI                                                           0x02a7
+#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI_BASE_IDX                                                  2
+#define regMCIF_WB_VMID_CONTROL                                                                         0x02a8
+#define regMCIF_WB_VMID_CONTROL_BASE_IDX                                                                2
+#define regMCIF_WB_MIN_TTO                                                                              0x02a9
+#define regMCIF_WB_MIN_TTO_BASE_IDX                                                                     2
+
+
+// addressBlock: dcn_dc_mmhubbub_mmhubbub_dispdec
+// base address: 0x0
+#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                          0x02aa
+#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                                 2
+#define regMCIF_WB_WATERMARK                                                                            0x02ab
+#define regMCIF_WB_WATERMARK_BASE_IDX                                                                   2
+#define regMMHUBBUB_WARMUP_CONFIG                                                                       0x02ac
+#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX                                                              2
+#define regMMHUBBUB_WARMUP_CONTROL_STATUS                                                               0x02ad
+#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX                                                      2
+#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW                                                                0x02ae
+#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX                                                       2
+#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH                                                               0x02af
+#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX                                                      2
+#define regMMHUBBUB_WARMUP_ADDR_REGION                                                                  0x02b0
+#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX                                                         2
+#define regMMHUBBUB_MIN_TTO                                                                             0x02b1
+#define regMMHUBBUB_MIN_TTO_BASE_IDX                                                                    2
+#define regMMHUBBUB_CTRL                                                                                0x0333
+#define regMMHUBBUB_CTRL_BASE_IDX                                                                       2
+#define regWBIF_SMU_WM_CONTROL                                                                          0x0334
+#define regWBIF_SMU_WM_CONTROL_BASE_IDX                                                                 2
+#define regWBIF0_MISC_CTRL                                                                              0x0335
+#define regWBIF0_MISC_CTRL_BASE_IDX                                                                     2
+#define regWBIF0_PHASE0_OUTSTANDING_COUNTER                                                             0x0336
+#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                    2
+#define regWBIF0_PHASE1_OUTSTANDING_COUNTER                                                             0x0337
+#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                    2
+#define regVGA_SRC_SPLIT_CNTL                                                                           0x033e
+#define regVGA_SRC_SPLIT_CNTL_BASE_IDX                                                                  2
+#define regMMHUBBUB_MEM_PWR_STATUS                                                                      0x033f
+#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
+#define regMMHUBBUB_MEM_PWR_CNTL                                                                        0x0340
+#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX                                                               2
+#define regMMHUBBUB_CLOCK_CNTL                                                                          0x0341
+#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
+#define regMMHUBBUB_SOFT_RESET                                                                          0x0342
+#define regMMHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
+#define regDMU_IF_ERR_STATUS                                                                            0x0346
+#define regDMU_IF_ERR_STATUS_BASE_IDX                                                                   2
+#define regMMHUBBUB_CLIENT_UNIT_ID                                                                      0x0347
+#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX                                                             2
+#define regMMHUBBUB_WARMUP_VMID_CONTROL                                                                 0x0349
+#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX                                                        2
+
+
+// addressBlock: dcn_dc_hda_azf0controller_dispdec
+// base address: 0x0
+#define regAZALIA_CONTROLLER_CLOCK_GATING                                                               0x03c2
+#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX                                                      2
+#define regAZALIA_AUDIO_DTO                                                                             0x03c3
+#define regAZALIA_AUDIO_DTO_BASE_IDX                                                                    2
+#define regAZALIA_AUDIO_DTO_CONTROL                                                                     0x03c4
+#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX                                                            2
+#define regAZALIA_SOCCLK_CONTROL                                                                        0x03c5
+#define regAZALIA_SOCCLK_CONTROL_BASE_IDX                                                               2
+#define regAZALIA_UNDERFLOW_FILLER_SAMPLE                                                               0x03c6
+#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX                                                      2
+#define regAZALIA_DATA_DMA_CONTROL                                                                      0x03c7
+#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX                                                             2
+#define regAZALIA_BDL_DMA_CONTROL                                                                       0x03c8
+#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX                                                              2
+#define regAZALIA_RIRB_AND_DP_CONTROL                                                                   0x03c9
+#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2
+#define regAZALIA_CORB_DMA_CONTROL                                                                      0x03ca
+#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX                                                             2
+#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER                                                 0x03d1
+#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX                                        2
+#define regAZALIA_CYCLIC_BUFFER_SYNC                                                                    0x03d2
+#define regAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX                                                           2
+#define regAZALIA_GLOBAL_CAPABILITIES                                                                   0x03d3
+#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX                                                          2
+#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                                             0x03d4
+#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                    2
+#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                                         0x03d5
+#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2
+#define regAZALIA_INPUT_PAYLOAD_CAPABILITY                                                              0x03d6
+#define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                     2
+#define regAZALIA_INPUT_CRC0_CONTROL0                                                                   0x03d9
+#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_CONTROL1                                                                   0x03da
+#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_CONTROL2                                                                   0x03db
+#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_CONTROL3                                                                   0x03dc
+#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_RESULT                                                                     0x03dd
+#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX                                                            2
+#define regAZALIA_INPUT_CRC1_CONTROL0                                                                   0x03de
+#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_CONTROL1                                                                   0x03df
+#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_CONTROL2                                                                   0x03e0
+#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_CONTROL3                                                                   0x03e1
+#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_RESULT                                                                     0x03e2
+#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX                                                            2
+#define regAZALIA_CRC0_CONTROL0                                                                         0x03e3
+#define regAZALIA_CRC0_CONTROL0_BASE_IDX                                                                2
+#define regAZALIA_CRC0_CONTROL1                                                                         0x03e4
+#define regAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2
+#define regAZALIA_CRC0_CONTROL2                                                                         0x03e5
+#define regAZALIA_CRC0_CONTROL2_BASE_IDX                                                                2
+#define regAZALIA_CRC0_CONTROL3                                                                         0x03e6
+#define regAZALIA_CRC0_CONTROL3_BASE_IDX                                                                2
+#define regAZALIA_CRC0_RESULT                                                                           0x03e7
+#define regAZALIA_CRC0_RESULT_BASE_IDX                                                                  2
+#define regAZALIA_CRC1_CONTROL0                                                                         0x03e8
+#define regAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2
+#define regAZALIA_CRC1_CONTROL1                                                                         0x03e9
+#define regAZALIA_CRC1_CONTROL1_BASE_IDX                                                                2
+#define regAZALIA_CRC1_CONTROL2                                                                         0x03ea
+#define regAZALIA_CRC1_CONTROL2_BASE_IDX                                                                2
+#define regAZALIA_CRC1_CONTROL3                                                                         0x03eb
+#define regAZALIA_CRC1_CONTROL3_BASE_IDX                                                                2
+#define regAZALIA_CRC1_RESULT                                                                           0x03ec
+#define regAZALIA_CRC1_RESULT_BASE_IDX                                                                  2
+#define regAZALIA_MEM_PWR_CTRL                                                                          0x03ee
+#define regAZALIA_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regAZALIA_MEM_PWR_STATUS                                                                        0x03ef
+#define regAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2
+
+
+// addressBlock: dcn_dc_hda_azf0root_dispdec
+// base address: 0x0
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0406
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX                                 2
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0407
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX                                          2
+#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0408
+#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2
+#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                                          0x0409
+#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX                                                 2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x040a
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX                                       2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x040b
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX                             2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x040c
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX                                   2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x040d
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX                                     2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x040e
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX                                        2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                                       0x040f
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX                                              2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x0410
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX                              2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x0411
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX                          2
+#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                                            0x0412
+#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                   2
+#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                      0x0413
+#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                             2
+#define regAZALIA_F0_GTC_GROUP_OFFSET0                                                                  0x0415
+#define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET1                                                                  0x0416
+#define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET2                                                                  0x0417
+#define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET3                                                                  0x0418
+#define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET4                                                                  0x0419
+#define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET5                                                                  0x041a
+#define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET6                                                                  0x041b
+#define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX                                                         2
+#define regREG_DC_AUDIO_PORT_CONNECTIVITY                                                               0x041c
+#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                      2
+#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                         0x041d
+#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                                2
+
+
+// addressBlock: dcn_dc_hda_az_misc_dispdec
+// base address: 0x0
+#define regAZ_CLOCK_CNTL                                                                                0x0372
+#define regAZ_CLOCK_CNTL_BASE_IDX                                                                       2
+
+
+// addressBlock: dcn_dc_hda_azf0stream0_dispdec
+// base address: 0x0
+#define regAZF0STREAM0_AZALIA_STREAM_INDEX                                                              0x035e
+#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM0_AZALIA_STREAM_DATA                                                               0x035f
+#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azf0stream1_dispdec
+// base address: 0x8
+#define regAZF0STREAM1_AZALIA_STREAM_INDEX                                                              0x0360
+#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM1_AZALIA_STREAM_DATA                                                               0x0361
+#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azf0stream2_dispdec
+// base address: 0x10
+#define regAZF0STREAM2_AZALIA_STREAM_INDEX                                                              0x0362
+#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM2_AZALIA_STREAM_DATA                                                               0x0363
+#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azf0stream3_dispdec
+// base address: 0x18
+#define regAZF0STREAM3_AZALIA_STREAM_INDEX                                                              0x0364
+#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM3_AZALIA_STREAM_DATA                                                               0x0365
+#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azf0stream4_dispdec
+// base address: 0x20
+#define regAZF0STREAM4_AZALIA_STREAM_INDEX                                                              0x0366
+#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM4_AZALIA_STREAM_DATA                                                               0x0367
+#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azf0stream5_dispdec
+// base address: 0x28
+#define regAZF0STREAM5_AZALIA_STREAM_INDEX                                                              0x0368
+#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM5_AZALIA_STREAM_DATA                                                               0x0369
+#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azf0stream6_dispdec
+// base address: 0x30
+#define regAZF0STREAM6_AZALIA_STREAM_INDEX                                                              0x036a
+#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM6_AZALIA_STREAM_DATA                                                               0x036b
+#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azf0stream7_dispdec
+// base address: 0x38
+#define regAZF0STREAM7_AZALIA_STREAM_INDEX                                                              0x036c
+#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM7_AZALIA_STREAM_DATA                                                               0x036d
+#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azf0stream8_dispdec
+// base address: 0x320
+#define regAZF0STREAM8_AZALIA_STREAM_INDEX                                                              0x0426
+#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM8_AZALIA_STREAM_DATA                                                               0x0427
+#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azf0stream9_dispdec
+// base address: 0x328
+#define regAZF0STREAM9_AZALIA_STREAM_INDEX                                                              0x0428
+#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM9_AZALIA_STREAM_DATA                                                               0x0429
+#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azf0stream10_dispdec
+// base address: 0x330
+#define regAZF0STREAM10_AZALIA_STREAM_INDEX                                                             0x042a
+#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM10_AZALIA_STREAM_DATA                                                              0x042b
+#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_hda_azf0stream11_dispdec
+// base address: 0x338
+#define regAZF0STREAM11_AZALIA_STREAM_INDEX                                                             0x042c
+#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM11_AZALIA_STREAM_DATA                                                              0x042d
+#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_hda_azf0stream12_dispdec
+// base address: 0x340
+#define regAZF0STREAM12_AZALIA_STREAM_INDEX                                                             0x042e
+#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM12_AZALIA_STREAM_DATA                                                              0x042f
+#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_hda_azf0stream13_dispdec
+// base address: 0x348
+#define regAZF0STREAM13_AZALIA_STREAM_INDEX                                                             0x0430
+#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM13_AZALIA_STREAM_DATA                                                              0x0431
+#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_hda_azf0stream14_dispdec
+// base address: 0x350
+#define regAZF0STREAM14_AZALIA_STREAM_INDEX                                                             0x0432
+#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM14_AZALIA_STREAM_DATA                                                              0x0433
+#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_hda_azf0stream15_dispdec
+// base address: 0x358
+#define regAZF0STREAM15_AZALIA_STREAM_INDEX                                                             0x0434
+#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM15_AZALIA_STREAM_DATA                                                              0x0435
+#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint0_dispdec
+// base address: 0x0
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0386
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0387
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint1_dispdec
+// base address: 0x18
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x038c
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x038d
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint2_dispdec
+// base address: 0x30
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0392
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0393
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint3_dispdec
+// base address: 0x48
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0398
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0399
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint4_dispdec
+// base address: 0x60
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x039e
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x039f
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint5_dispdec
+// base address: 0x78
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03a4
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03a5
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint6_dispdec
+// base address: 0x90
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03aa
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03ab
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint7_dispdec
+// base address: 0xa8
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03b0
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03b1
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint0_dispdec
+// base address: 0x0
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043a
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043b
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint1_dispdec
+// base address: 0x10
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043e
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043f
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint2_dispdec
+// base address: 0x20
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0442
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0443
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint3_dispdec
+// base address: 0x30
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0446
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0447
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint4_dispdec
+// base address: 0x40
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044a
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044b
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint5_dispdec
+// base address: 0x50
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044e
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044f
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint6_dispdec
+// base address: 0x60
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0452
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0453
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint7_dispdec
+// base address: 0x70
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0456
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0457
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dcn_dc_dchubbubl_hubbub_dispdec
+// base address: 0x0
+#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND                                                                 0x04f9
+#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX                                                        2
+#define regDCHUBBUB_ARB_SAT_LEVEL                                                                       0x04fa
+#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX                                                              2
+#define regDCHUBBUB_ARB_QOS_FORCE                                                                       0x04fb
+#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX                                                              2
+#define regDCHUBBUB_ARB_DRAM_STATE_CNTL                                                                 0x04fc
+#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX                                                        2
+#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL                                                             0x04fd
+#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL_BASE_IDX                                                    2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A                                                        0x04fe
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A                                                      0x04ff
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A                                                     0x0500
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A                                                      0x0501
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A                                                       0x0502
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A                                                  0x0503
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A                                                  0x0504
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A                                                               0x0505
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A                                                              0x0506
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B                                                        0x0507
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B                                                      0x0508
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B                                                     0x0509
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B                                                      0x050a
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B                                                       0x050b
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B                                                  0x050c
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B                                                  0x050d
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B                                                               0x050e
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B                                                              0x050f
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C                                                        0x0510
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C                                                      0x0511
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C                                                     0x0512
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C                                                      0x0513
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C                                                       0x0514
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C                                                  0x0515
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C                                                  0x0516
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C                                                               0x0517
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C                                                              0x0518
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D                                                        0x0519
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D                                                      0x051a
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D                                                     0x051b
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D                                                      0x051c
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D                                                       0x051d
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D                                                  0x051e
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D                                                  0x051f
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D                                                               0x0520
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D                                                              0x0521
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL                                                           0x0522
+#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX                                                  2
+#define regDCHUBBUB_ARB_MALL_CNTL                                                                       0x0523
+#define regDCHUBBUB_ARB_MALL_CNTL_BASE_IDX                                                              2
+#define regDCHUBBUB_ARB_TIMEOUT_ENABLE                                                                  0x0524
+#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX                                                         2
+#define regDCHUBBUB_GLOBAL_TIMER_CNTL                                                                   0x0525
+#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX                                                          2
+#define regSURFACE_CHECK0_ADDRESS_LSB                                                                   0x0526
+#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK0_ADDRESS_MSB                                                                   0x0527
+#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK1_ADDRESS_LSB                                                                   0x0528
+#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK1_ADDRESS_MSB                                                                   0x0529
+#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK2_ADDRESS_LSB                                                                   0x052a
+#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK2_ADDRESS_MSB                                                                   0x052b
+#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK3_ADDRESS_LSB                                                                   0x052c
+#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK3_ADDRESS_MSB                                                                   0x052d
+#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX                                                          2
+#define regVTG0_CONTROL                                                                                 0x052e
+#define regVTG0_CONTROL_BASE_IDX                                                                        2
+#define regVTG1_CONTROL                                                                                 0x052f
+#define regVTG1_CONTROL_BASE_IDX                                                                        2
+#define regVTG2_CONTROL                                                                                 0x0530
+#define regVTG2_CONTROL_BASE_IDX                                                                        2
+#define regVTG3_CONTROL                                                                                 0x0531
+#define regVTG3_CONTROL_BASE_IDX                                                                        2
+#define regDCHUBBUB_SOFT_RESET                                                                          0x0532
+#define regDCHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
+#define regDCHUBBUB_CLOCK_CNTL                                                                          0x0533
+#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
+#define regDCFCLK_CNTL                                                                                  0x0534
+#define regDCFCLK_CNTL_BASE_IDX                                                                         2
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL                                                        0x0535
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX                                               2
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2                                                       0x0536
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX                                              2
+#define regDCHUBBUB_VLINE_SNAPSHOT                                                                      0x0537
+#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX                                                             2
+#define regDCHUBBUB_CTRL_STATUS                                                                         0x0538
+#define regDCHUBBUB_CTRL_STATUS_BASE_IDX                                                                2
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1                                                             0x053e
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX                                                    2
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2                                                             0x053f
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX                                                    2
+#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS                                                            0x0540
+#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX                                                   2
+#define regFMON_CTRL                                                                                    0x0541
+#define regFMON_CTRL_BASE_IDX                                                                           2
+
+
+// addressBlock: dcn_dc_dchubbubl_hubbub_sdpif_dispdec
+// base address: 0x0
+#define regDCHUBBUB_SDPIF_CFG0                                                                          0x046f
+#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX                                                                 2
+#define regDCHUBBUB_SDPIF_CFG1                                                                          0x0470
+#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX                                                                 2
+#define regDCHUBBUB_SDPIF_CFG2                                                                          0x0471
+#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX                                                                 2
+#define regVM_REQUEST_PHYSICAL                                                                          0x0472
+#define regVM_REQUEST_PHYSICAL_BASE_IDX                                                                 2
+#define regDCHUBBUB_FORCE_IO_STATUS_0                                                                   0x0473
+#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX                                                          2
+#define regDCHUBBUB_FORCE_IO_STATUS_1                                                                   0x0474
+#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX                                                          2
+#define regDCN_VM_FB_LOCATION_BASE                                                                      0x0475
+#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX                                                             2
+#define regDCN_VM_FB_LOCATION_TOP                                                                       0x0476
+#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX                                                              2
+#define regDCN_VM_FB_OFFSET                                                                             0x0477
+#define regDCN_VM_FB_OFFSET_BASE_IDX                                                                    2
+#define regDCN_VM_AGP_BOT                                                                               0x0478
+#define regDCN_VM_AGP_BOT_BASE_IDX                                                                      2
+#define regDCN_VM_AGP_TOP                                                                               0x0479
+#define regDCN_VM_AGP_TOP_BASE_IDX                                                                      2
+#define regDCN_VM_AGP_BASE                                                                              0x047a
+#define regDCN_VM_AGP_BASE_BASE_IDX                                                                     2
+#define regDCN_VM_LOCAL_HBM_ADDRESS_START                                                               0x047b
+#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                                      2
+#define regDCN_VM_LOCAL_HBM_ADDRESS_END                                                                 0x047c
+#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                                        2
+#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                           0x047d
+#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                                  2
+#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL                                                                  0x047e
+#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX                                                         2
+#define regDCHUBBUB_SDPIF_PIPE_NOALLOC                                                                  0x047f
+#define regDCHUBBUB_SDPIF_PIPE_NOALLOC_BASE_IDX                                                         2
+#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL                                                           0x0480
+#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX                                                  2
+#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL                                                          0x0481
+#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL_BASE_IDX                                                 2
+#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL                                                          0x0482
+#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL_BASE_IDX                                                 2
+#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL                                                            0x0483
+#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL_BASE_IDX                                                   2
+#define regSDPIF_REQUEST_RATE_LIMIT                                                                     0x0484
+#define regSDPIF_REQUEST_RATE_LIMIT_BASE_IDX                                                            2
+#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL                                                                  0x0485
+#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX                                                         2
+#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS                                                                0x0486
+#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX                                                       2
+
+
+// addressBlock: dcn_dc_dchubbubl_hubbub_ret_path_dispdec
+// base address: 0x0
+#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL                                                               0x04af
+#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX                                                      2
+#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS                                                             0x04b0
+#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX                                                    2
+#define regDCHUBBUB_CRC_CTRL                                                                            0x04b1
+#define regDCHUBBUB_CRC_CTRL_BASE_IDX                                                                   2
+#define regDCHUBBUB_CRC0_VAL_R_G                                                                        0x04b2
+#define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX                                                               2
+#define regDCHUBBUB_CRC0_VAL_B_A                                                                        0x04b3
+#define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX                                                               2
+#define regDCHUBBUB_CRC1_VAL_R_G                                                                        0x04b4
+#define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX                                                               2
+#define regDCHUBBUB_CRC1_VAL_B_A                                                                        0x04b5
+#define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX                                                               2
+#define regDCHUBBUB_DCC_STAT_CNTL                                                                       0x04b6
+#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX                                                              2
+#define regDCHUBBUB_DCC_STAT0                                                                           0x04b7
+#define regDCHUBBUB_DCC_STAT0_BASE_IDX                                                                  2
+#define regDCHUBBUB_DCC_STAT1                                                                           0x04b8
+#define regDCHUBBUB_DCC_STAT1_BASE_IDX                                                                  2
+#define regDCHUBBUB_DCC_STAT2                                                                           0x04b9
+#define regDCHUBBUB_DCC_STAT2_BASE_IDX                                                                  2
+#define regDCHUBBUB_COMPBUF_CTRL                                                                        0x04ba
+#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX                                                               2
+#define regDCHUBBUB_DET0_CTRL                                                                           0x04bb
+#define regDCHUBBUB_DET0_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_DET1_CTRL                                                                           0x04bc
+#define regDCHUBBUB_DET1_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_DET2_CTRL                                                                           0x04bd
+#define regDCHUBBUB_DET2_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_DET3_CTRL                                                                           0x04be
+#define regDCHUBBUB_DET3_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_MEM_PWR_MODE_CTRL                                                                   0x04c0
+#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX                                                          2
+#define regCOMPBUF_MEM_PWR_CTRL_1                                                                       0x04c1
+#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX                                                              2
+#define regCOMPBUF_MEM_PWR_CTRL_2                                                                       0x04c2
+#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX                                                              2
+#define regDCHUBBUB_MEM_PWR_STATUS                                                                      0x04c3
+#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
+#define regCOMPBUF_RESERVED_SPACE                                                                       0x04c4
+#define regCOMPBUF_RESERVED_SPACE_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dchubbubl_hubbub_vmrq_if_dispdec
+// base address: 0x0
+#define regDCN_VM_CONTEXT0_CNTL                                                                         0x0559
+#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                    0x055a
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                    0x055b
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                   0x055c
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                   0x055d
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                     0x055e
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                     0x055f
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT1_CNTL                                                                         0x0560
+#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0561
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0562
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                   0x0563
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                   0x0564
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                     0x0565
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                     0x0566
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT2_CNTL                                                                         0x0567
+#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0568
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0569
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                   0x056a
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                   0x056b
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                     0x056c
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                     0x056d
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT3_CNTL                                                                         0x056e
+#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                    0x056f
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0570
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                   0x0571
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                   0x0572
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                     0x0573
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                     0x0574
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT4_CNTL                                                                         0x0575
+#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0576
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0577
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                   0x0578
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                   0x0579
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                     0x057a
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                     0x057b
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT5_CNTL                                                                         0x057c
+#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                    0x057d
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                    0x057e
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                   0x057f
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                   0x0580
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                     0x0581
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                     0x0582
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT6_CNTL                                                                         0x0583
+#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0584
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0585
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                   0x0586
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                   0x0587
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                     0x0588
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                     0x0589
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT7_CNTL                                                                         0x058a
+#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                    0x058b
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                    0x058c
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                   0x058d
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                   0x058e
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                     0x058f
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                     0x0590
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT8_CNTL                                                                         0x0591
+#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0592
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0593
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                   0x0594
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                   0x0595
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                     0x0596
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                     0x0597
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT9_CNTL                                                                         0x0598
+#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0599
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                    0x059a
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                   0x059b
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                   0x059c
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                     0x059d
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                     0x059e
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT10_CNTL                                                                        0x059f
+#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a0
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a1
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                  0x05a2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                  0x05a3
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                    0x05a4
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                    0x05a5
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT11_CNTL                                                                        0x05a6
+#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a7
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a8
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                  0x05a9
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                  0x05aa
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                    0x05ab
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                    0x05ac
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT12_CNTL                                                                        0x05ad
+#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05ae
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05af
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                  0x05b0
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                  0x05b1
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                    0x05b2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                    0x05b3
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT13_CNTL                                                                        0x05b4
+#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05b5
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05b6
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                  0x05b7
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                  0x05b8
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                    0x05b9
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                    0x05ba
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT14_CNTL                                                                        0x05bb
+#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05bc
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05bd
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                  0x05be
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                  0x05bf
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                    0x05c0
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                    0x05c1
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT15_CNTL                                                                        0x05c2
+#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05c3
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05c4
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                  0x05c5
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                  0x05c6
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                    0x05c7
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                    0x05c8
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_DEFAULT_ADDR_MSB                                                                      0x05c9
+#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX                                                             2
+#define regDCN_VM_DEFAULT_ADDR_LSB                                                                      0x05ca
+#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX                                                             2
+#define regDCN_VM_FAULT_CNTL                                                                            0x05cb
+#define regDCN_VM_FAULT_CNTL_BASE_IDX                                                                   2
+#define regDCN_VM_FAULT_STATUS                                                                          0x05cc
+#define regDCN_VM_FAULT_STATUS_BASE_IDX                                                                 2
+#define regDCN_VM_FAULT_ADDR_MSB                                                                        0x05cd
+#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX                                                               2
+#define regDCN_VM_FAULT_ADDR_LSB                                                                        0x05ce
+#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX                                                               2
+
+
+// addressBlock: dcn_dc_dcbubp0_dispdec_hubp_dispdec
+// base address: 0x0
+#define regHUBP0_DCSURF_SURFACE_CONFIG                                                                  0x05e5
+#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP0_DCSURF_ADDR_CONFIG                                                                     0x05e6
+#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP0_DCSURF_TILING_CONFIG                                                                   0x05e7
+#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START                                                              0x05e9
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x05ea
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C                                                            0x05eb
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x05ec
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START                                                              0x05ed
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x05ee
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C                                                            0x05ef
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x05f0
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG                                                                 0x05f1
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x05f2
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP0_DCHUBP_CNTL                                                                            0x05f3
+#define regHUBP0_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP0_HUBP_CLK_CNTL                                                                          0x05f4
+#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP0_DCHUBP_VMPG_CONFIG                                                                     0x05f5
+#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP0_DCHUBP_MALL_CONFIG                                                                     0x05f6
+#define regHUBP0_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
+#define regHUBP0_DCHUBP_MALL_SUB_VP                                                                     0x05f7
+#define regHUBP0_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
+#define regHUBP0_HUBPREQ_DEBUG_DB                                                                       0x05f8
+#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP0_HUBPREQ_DEBUG                                                                          0x05f9
+#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x05fd
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x05fe
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+#define regHUBP0_HUBP_MALL_STATUS                                                                       0x05ff
+#define regHUBP0_HUBP_MALL_STATUS_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dcbubp0_dispdec_hubpreq_dispdec
+// base address: 0x0
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH                                                                0x0607
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C                                                              0x0608
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ0_VMID_SETTINGS_0                                                                     0x0609
+#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x060a
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x060b
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x060c
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x060d
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x060e
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x060f
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x0610
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x0611
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x0612
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x0613
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x0614
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x0615
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x0616
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x0617
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x0618
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x0619
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ0_DCSURF_SURFACE_CONTROL                                                              0x061a
+#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL                                                                 0x061b
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL2                                                                0x061c
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x061f
+#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE                                                                0x0620
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH                                                           0x0621
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C                                                              0x0622
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0623
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0624
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0625
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0626
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0627
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ0_DCN_EXPANSION_MODE                                                                  0x0628
+#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_TTU_QOS_WM                                                                      0x0629
+#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL                                                                 0x062a
+#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0                                                                 0x062b
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1                                                                 0x062c
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0                                                                 0x062d
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1                                                                 0x062e
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0                                                                  0x062f
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1                                                                  0x0630
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0                                                                  0x0631
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1                                                                  0x0632
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_DMDATA_VM_CNTL                                                                  0x0633
+#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0634
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0635
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL                                                               0x0642
+#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ0_BLANK_OFFSET_0                                                                      0x0643
+#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ0_BLANK_OFFSET_1                                                                      0x0644
+#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ0_DST_DIMENSIONS                                                                      0x0645
+#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ0_DST_AFTER_SCALER                                                                    0x0646
+#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ0_PREFETCH_SETTINGS                                                                   0x0647
+#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ0_PREFETCH_SETTINGS_C                                                                 0x0648
+#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_0                                                                 0x0649
+#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_1                                                                 0x064a
+#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_2                                                                 0x064b
+#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_3                                                                 0x064c
+#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_4                                                                 0x064d
+#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ0_FLIP_PARAMETERS_0                                                                   0x064e
+#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_1                                                                   0x064f
+#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_2                                                                   0x0650
+#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ0_NOM_PARAMETERS_0                                                                    0x0651
+#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_1                                                                    0x0652
+#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_2                                                                    0x0653
+#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_3                                                                    0x0654
+#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_4                                                                    0x0655
+#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_5                                                                    0x0656
+#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_6                                                                    0x0657
+#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_7                                                                    0x0658
+#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ0_PER_LINE_DELIVERY_PRE                                                               0x0659
+#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ0_PER_LINE_DELIVERY                                                                   0x065a
+#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ0_CURSOR_SETTINGS                                                                     0x065b
+#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ                                                                0x065c
+#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT                                                               0x065d
+#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL                                                                0x065e
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS                                                              0x065f
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ0_VBLANK_PARAMETERS_5                                                                 0x0662
+#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_6                                                                 0x0663
+#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ0_FLIP_PARAMETERS_3                                                                   0x0664
+#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_4                                                                   0x0665
+#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_5                                                                   0x0666
+#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_6                                                                   0x0667
+#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+#define regHUBPREQ0_UCLK_PSTATE_FORCE                                                                   0x0668
+#define regHUBPREQ0_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
+#define regHUBPREQ0_HUBPREQ_STATUS_REG0                                                                 0x0669
+#define regHUBPREQ0_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
+#define regHUBPREQ0_HUBPREQ_STATUS_REG1                                                                 0x066a
+#define regHUBPREQ0_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
+#define regHUBPREQ0_HUBPREQ_STATUS_REG2                                                                 0x066b
+#define regHUBPREQ0_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2
+
+
+// addressBlock: dcn_dc_dcbubp0_dispdec_hubpret_dispdec
+// base address: 0x0
+#define regHUBPRET0_HUBPRET_CONTROL                                                                     0x066c
+#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL                                                                0x066d
+#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS                                                              0x066e
+#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0                                                             0x066f
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1                                                             0x0670
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET0_HUBPRET_READ_LINE0                                                                  0x0671
+#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET0_HUBPRET_READ_LINE1                                                                  0x0672
+#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET0_HUBPRET_INTERRUPT                                                                   0x0673
+#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET0_HUBPRET_READ_LINE_VALUE                                                             0x0674
+#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET0_HUBPRET_READ_LINE_STATUS                                                            0x0675
+#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dcn_dc_dcbubp0_dispdec_cursor0_dispdec
+// base address: 0x0
+#define regCURSOR0_0_CURSOR_CONTROL                                                                     0x0678
+#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS                                                             0x0679
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x067a
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_0_CURSOR_SIZE                                                                        0x067b
+#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_0_CURSOR_POSITION                                                                    0x067c
+#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_0_CURSOR_HOT_SPOT                                                                    0x067d
+#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_0_CURSOR_STEREO_CONTROL                                                              0x067e
+#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_0_CURSOR_DST_OFFSET                                                                  0x067f
+#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL                                                                0x0680
+#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS                                                              0x0681
+#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_0_DMDATA_ADDRESS_HIGH                                                                0x0682
+#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_0_DMDATA_ADDRESS_LOW                                                                 0x0683
+#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_0_DMDATA_CNTL                                                                        0x0684
+#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_0_DMDATA_QOS_CNTL                                                                    0x0685
+#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_0_DMDATA_STATUS                                                                      0x0686
+#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_0_DMDATA_SW_CNTL                                                                     0x0687
+#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_0_DMDATA_SW_DATA                                                                     0x0688
+#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+
+// addressBlock: dcn_dc_dcbubp1_dispdec_hubp_dispdec
+// base address: 0x370
+#define regHUBP1_DCSURF_SURFACE_CONFIG                                                                  0x06c1
+#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP1_DCSURF_ADDR_CONFIG                                                                     0x06c2
+#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP1_DCSURF_TILING_CONFIG                                                                   0x06c3
+#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START                                                              0x06c5
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x06c6
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C                                                            0x06c7
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x06c8
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START                                                              0x06c9
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x06ca
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C                                                            0x06cb
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x06cc
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG                                                                 0x06cd
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x06ce
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP1_DCHUBP_CNTL                                                                            0x06cf
+#define regHUBP1_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP1_HUBP_CLK_CNTL                                                                          0x06d0
+#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP1_DCHUBP_VMPG_CONFIG                                                                     0x06d1
+#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP1_DCHUBP_MALL_CONFIG                                                                     0x06d2
+#define regHUBP1_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
+#define regHUBP1_DCHUBP_MALL_SUB_VP                                                                     0x06d3
+#define regHUBP1_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
+#define regHUBP1_HUBPREQ_DEBUG_DB                                                                       0x06d4
+#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP1_HUBPREQ_DEBUG                                                                          0x06d5
+#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x06d9
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x06da
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+#define regHUBP1_HUBP_MALL_STATUS                                                                       0x06db
+#define regHUBP1_HUBP_MALL_STATUS_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dcbubp1_dispdec_hubpreq_dispdec
+// base address: 0x370
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH                                                                0x06e3
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C                                                              0x06e4
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ1_VMID_SETTINGS_0                                                                     0x06e5
+#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x06e6
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x06e7
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x06e8
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x06e9
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x06ea
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x06eb
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x06ec
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x06ed
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x06ee
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x06ef
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x06f0
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x06f1
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x06f2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x06f3
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x06f4
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x06f5
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ1_DCSURF_SURFACE_CONTROL                                                              0x06f6
+#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL                                                                 0x06f7
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL2                                                                0x06f8
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x06fb
+#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE                                                                0x06fc
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH                                                           0x06fd
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C                                                              0x06fe
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x06ff
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0700
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0701
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0702
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0703
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ1_DCN_EXPANSION_MODE                                                                  0x0704
+#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_TTU_QOS_WM                                                                      0x0705
+#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL                                                                 0x0706
+#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0                                                                 0x0707
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1                                                                 0x0708
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0                                                                 0x0709
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1                                                                 0x070a
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0                                                                  0x070b
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1                                                                  0x070c
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0                                                                  0x070d
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1                                                                  0x070e
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_DMDATA_VM_CNTL                                                                  0x070f
+#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0710
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0711
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL                                                               0x071e
+#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ1_BLANK_OFFSET_0                                                                      0x071f
+#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ1_BLANK_OFFSET_1                                                                      0x0720
+#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ1_DST_DIMENSIONS                                                                      0x0721
+#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ1_DST_AFTER_SCALER                                                                    0x0722
+#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ1_PREFETCH_SETTINGS                                                                   0x0723
+#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ1_PREFETCH_SETTINGS_C                                                                 0x0724
+#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_0                                                                 0x0725
+#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_1                                                                 0x0726
+#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_2                                                                 0x0727
+#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_3                                                                 0x0728
+#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_4                                                                 0x0729
+#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ1_FLIP_PARAMETERS_0                                                                   0x072a
+#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_1                                                                   0x072b
+#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_2                                                                   0x072c
+#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ1_NOM_PARAMETERS_0                                                                    0x072d
+#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_1                                                                    0x072e
+#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_2                                                                    0x072f
+#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_3                                                                    0x0730
+#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_4                                                                    0x0731
+#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_5                                                                    0x0732
+#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_6                                                                    0x0733
+#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_7                                                                    0x0734
+#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ1_PER_LINE_DELIVERY_PRE                                                               0x0735
+#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ1_PER_LINE_DELIVERY                                                                   0x0736
+#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ1_CURSOR_SETTINGS                                                                     0x0737
+#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ                                                                0x0738
+#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT                                                               0x0739
+#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL                                                                0x073a
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS                                                              0x073b
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ1_VBLANK_PARAMETERS_5                                                                 0x073e
+#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_6                                                                 0x073f
+#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ1_FLIP_PARAMETERS_3                                                                   0x0740
+#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_4                                                                   0x0741
+#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_5                                                                   0x0742
+#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_6                                                                   0x0743
+#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+#define regHUBPREQ1_UCLK_PSTATE_FORCE                                                                   0x0744
+#define regHUBPREQ1_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
+#define regHUBPREQ1_HUBPREQ_STATUS_REG0                                                                 0x0745
+#define regHUBPREQ1_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
+#define regHUBPREQ1_HUBPREQ_STATUS_REG1                                                                 0x0746
+#define regHUBPREQ1_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
+#define regHUBPREQ1_HUBPREQ_STATUS_REG2                                                                 0x0747
+#define regHUBPREQ1_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2
+
+
+// addressBlock: dcn_dc_dcbubp1_dispdec_hubpret_dispdec
+// base address: 0x370
+#define regHUBPRET1_HUBPRET_CONTROL                                                                     0x0748
+#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL                                                                0x0749
+#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS                                                              0x074a
+#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0                                                             0x074b
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1                                                             0x074c
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET1_HUBPRET_READ_LINE0                                                                  0x074d
+#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET1_HUBPRET_READ_LINE1                                                                  0x074e
+#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET1_HUBPRET_INTERRUPT                                                                   0x074f
+#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET1_HUBPRET_READ_LINE_VALUE                                                             0x0750
+#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET1_HUBPRET_READ_LINE_STATUS                                                            0x0751
+#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dcn_dc_dcbubp1_dispdec_cursor0_dispdec
+// base address: 0x370
+#define regCURSOR0_1_CURSOR_CONTROL                                                                     0x0754
+#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS                                                             0x0755
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0756
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_1_CURSOR_SIZE                                                                        0x0757
+#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_1_CURSOR_POSITION                                                                    0x0758
+#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_1_CURSOR_HOT_SPOT                                                                    0x0759
+#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_1_CURSOR_STEREO_CONTROL                                                              0x075a
+#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_1_CURSOR_DST_OFFSET                                                                  0x075b
+#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL                                                                0x075c
+#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS                                                              0x075d
+#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_1_DMDATA_ADDRESS_HIGH                                                                0x075e
+#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_1_DMDATA_ADDRESS_LOW                                                                 0x075f
+#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_1_DMDATA_CNTL                                                                        0x0760
+#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_1_DMDATA_QOS_CNTL                                                                    0x0761
+#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_1_DMDATA_STATUS                                                                      0x0762
+#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_1_DMDATA_SW_CNTL                                                                     0x0763
+#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_1_DMDATA_SW_DATA                                                                     0x0764
+#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dcn_dc_dcbubp2_dispdec_hubp_dispdec
+// base address: 0x6e0
+#define regHUBP2_DCSURF_SURFACE_CONFIG                                                                  0x079d
+#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP2_DCSURF_ADDR_CONFIG                                                                     0x079e
+#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP2_DCSURF_TILING_CONFIG                                                                   0x079f
+#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START                                                              0x07a1
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x07a2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C                                                            0x07a3
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x07a4
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START                                                              0x07a5
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x07a6
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C                                                            0x07a7
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x07a8
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG                                                                 0x07a9
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x07aa
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP2_DCHUBP_CNTL                                                                            0x07ab
+#define regHUBP2_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP2_HUBP_CLK_CNTL                                                                          0x07ac
+#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP2_DCHUBP_VMPG_CONFIG                                                                     0x07ad
+#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP2_DCHUBP_MALL_CONFIG                                                                     0x07ae
+#define regHUBP2_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
+#define regHUBP2_DCHUBP_MALL_SUB_VP                                                                     0x07af
+#define regHUBP2_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
+#define regHUBP2_HUBPREQ_DEBUG_DB                                                                       0x07b0
+#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP2_HUBPREQ_DEBUG                                                                          0x07b1
+#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x07b5
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x07b6
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+#define regHUBP2_HUBP_MALL_STATUS                                                                       0x07b7
+#define regHUBP2_HUBP_MALL_STATUS_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dcbubp2_dispdec_hubpreq_dispdec
+// base address: 0x6e0
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH                                                                0x07bf
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C                                                              0x07c0
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ2_VMID_SETTINGS_0                                                                     0x07c1
+#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x07c2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x07c3
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x07c4
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x07c5
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x07c6
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x07c7
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x07c8
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x07c9
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x07ca
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x07cb
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x07cc
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x07cd
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x07ce
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x07cf
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x07d0
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x07d1
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ2_DCSURF_SURFACE_CONTROL                                                              0x07d2
+#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL                                                                 0x07d3
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL2                                                                0x07d4
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x07d7
+#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE                                                                0x07d8
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH                                                           0x07d9
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C                                                              0x07da
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x07db
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x07dc
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x07dd
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x07de
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x07df
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ2_DCN_EXPANSION_MODE                                                                  0x07e0
+#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_TTU_QOS_WM                                                                      0x07e1
+#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL                                                                 0x07e2
+#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0                                                                 0x07e3
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1                                                                 0x07e4
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0                                                                 0x07e5
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1                                                                 0x07e6
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0                                                                  0x07e7
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1                                                                  0x07e8
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0                                                                  0x07e9
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1                                                                  0x07ea
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_DMDATA_VM_CNTL                                                                  0x07eb
+#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x07ec
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x07ed
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL                                                               0x07fa
+#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ2_BLANK_OFFSET_0                                                                      0x07fb
+#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ2_BLANK_OFFSET_1                                                                      0x07fc
+#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ2_DST_DIMENSIONS                                                                      0x07fd
+#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ2_DST_AFTER_SCALER                                                                    0x07fe
+#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ2_PREFETCH_SETTINGS                                                                   0x07ff
+#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ2_PREFETCH_SETTINGS_C                                                                 0x0800
+#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_0                                                                 0x0801
+#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_1                                                                 0x0802
+#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_2                                                                 0x0803
+#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_3                                                                 0x0804
+#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_4                                                                 0x0805
+#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ2_FLIP_PARAMETERS_0                                                                   0x0806
+#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_1                                                                   0x0807
+#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_2                                                                   0x0808
+#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ2_NOM_PARAMETERS_0                                                                    0x0809
+#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_1                                                                    0x080a
+#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_2                                                                    0x080b
+#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_3                                                                    0x080c
+#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_4                                                                    0x080d
+#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_5                                                                    0x080e
+#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_6                                                                    0x080f
+#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_7                                                                    0x0810
+#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ2_PER_LINE_DELIVERY_PRE                                                               0x0811
+#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ2_PER_LINE_DELIVERY                                                                   0x0812
+#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ2_CURSOR_SETTINGS                                                                     0x0813
+#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ                                                                0x0814
+#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT                                                               0x0815
+#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL                                                                0x0816
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS                                                              0x0817
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ2_VBLANK_PARAMETERS_5                                                                 0x081a
+#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_6                                                                 0x081b
+#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ2_FLIP_PARAMETERS_3                                                                   0x081c
+#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_4                                                                   0x081d
+#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_5                                                                   0x081e
+#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_6                                                                   0x081f
+#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+#define regHUBPREQ2_UCLK_PSTATE_FORCE                                                                   0x0820
+#define regHUBPREQ2_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
+#define regHUBPREQ2_HUBPREQ_STATUS_REG0                                                                 0x0821
+#define regHUBPREQ2_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
+#define regHUBPREQ2_HUBPREQ_STATUS_REG1                                                                 0x0822
+#define regHUBPREQ2_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
+#define regHUBPREQ2_HUBPREQ_STATUS_REG2                                                                 0x0823
+#define regHUBPREQ2_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2
+
+
+// addressBlock: dcn_dc_dcbubp2_dispdec_hubpret_dispdec
+// base address: 0x6e0
+#define regHUBPRET2_HUBPRET_CONTROL                                                                     0x0824
+#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL                                                                0x0825
+#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS                                                              0x0826
+#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0                                                             0x0827
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1                                                             0x0828
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET2_HUBPRET_READ_LINE0                                                                  0x0829
+#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET2_HUBPRET_READ_LINE1                                                                  0x082a
+#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET2_HUBPRET_INTERRUPT                                                                   0x082b
+#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET2_HUBPRET_READ_LINE_VALUE                                                             0x082c
+#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET2_HUBPRET_READ_LINE_STATUS                                                            0x082d
+#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dcn_dc_dcbubp2_dispdec_cursor0_dispdec
+// base address: 0x6e0
+#define regCURSOR0_2_CURSOR_CONTROL                                                                     0x0830
+#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS                                                             0x0831
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0832
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_2_CURSOR_SIZE                                                                        0x0833
+#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_2_CURSOR_POSITION                                                                    0x0834
+#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_2_CURSOR_HOT_SPOT                                                                    0x0835
+#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_2_CURSOR_STEREO_CONTROL                                                              0x0836
+#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_2_CURSOR_DST_OFFSET                                                                  0x0837
+#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL                                                                0x0838
+#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS                                                              0x0839
+#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_2_DMDATA_ADDRESS_HIGH                                                                0x083a
+#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_2_DMDATA_ADDRESS_LOW                                                                 0x083b
+#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_2_DMDATA_CNTL                                                                        0x083c
+#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_2_DMDATA_QOS_CNTL                                                                    0x083d
+#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_2_DMDATA_STATUS                                                                      0x083e
+#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_2_DMDATA_SW_CNTL                                                                     0x083f
+#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_2_DMDATA_SW_DATA                                                                     0x0840
+#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dcn_dc_dcbubp3_dispdec_hubp_dispdec
+// base address: 0xa50
+#define regHUBP3_DCSURF_SURFACE_CONFIG                                                                  0x0879
+#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP3_DCSURF_ADDR_CONFIG                                                                     0x087a
+#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP3_DCSURF_TILING_CONFIG                                                                   0x087b
+#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START                                                              0x087d
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x087e
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C                                                            0x087f
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x0880
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START                                                              0x0881
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x0882
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C                                                            0x0883
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x0884
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG                                                                 0x0885
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x0886
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP3_DCHUBP_CNTL                                                                            0x0887
+#define regHUBP3_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP3_HUBP_CLK_CNTL                                                                          0x0888
+#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP3_DCHUBP_VMPG_CONFIG                                                                     0x0889
+#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP3_DCHUBP_MALL_CONFIG                                                                     0x088a
+#define regHUBP3_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
+#define regHUBP3_DCHUBP_MALL_SUB_VP                                                                     0x088b
+#define regHUBP3_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
+#define regHUBP3_HUBPREQ_DEBUG_DB                                                                       0x088c
+#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP3_HUBPREQ_DEBUG                                                                          0x088d
+#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x0891
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x0892
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+#define regHUBP3_HUBP_MALL_STATUS                                                                       0x0893
+#define regHUBP3_HUBP_MALL_STATUS_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dcbubp3_dispdec_hubpreq_dispdec
+// base address: 0xa50
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH                                                                0x089b
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C                                                              0x089c
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ3_VMID_SETTINGS_0                                                                     0x089d
+#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x089e
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x089f
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x08a0
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x08a1
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x08a2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x08a3
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x08a4
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x08a5
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x08a6
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x08a7
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x08a8
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x08a9
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x08aa
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x08ab
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x08ac
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x08ad
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ3_DCSURF_SURFACE_CONTROL                                                              0x08ae
+#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL                                                                 0x08af
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL2                                                                0x08b0
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x08b3
+#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE                                                                0x08b4
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH                                                           0x08b5
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C                                                              0x08b6
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x08b7
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x08b8
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x08b9
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x08ba
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x08bb
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ3_DCN_EXPANSION_MODE                                                                  0x08bc
+#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_TTU_QOS_WM                                                                      0x08bd
+#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL                                                                 0x08be
+#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0                                                                 0x08bf
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1                                                                 0x08c0
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0                                                                 0x08c1
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1                                                                 0x08c2
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0                                                                  0x08c3
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1                                                                  0x08c4
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0                                                                  0x08c5
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1                                                                  0x08c6
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_DMDATA_VM_CNTL                                                                  0x08c7
+#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x08c8
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x08c9
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL                                                               0x08d6
+#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ3_BLANK_OFFSET_0                                                                      0x08d7
+#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ3_BLANK_OFFSET_1                                                                      0x08d8
+#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ3_DST_DIMENSIONS                                                                      0x08d9
+#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ3_DST_AFTER_SCALER                                                                    0x08da
+#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ3_PREFETCH_SETTINGS                                                                   0x08db
+#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ3_PREFETCH_SETTINGS_C                                                                 0x08dc
+#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_0                                                                 0x08dd
+#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_1                                                                 0x08de
+#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_2                                                                 0x08df
+#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_3                                                                 0x08e0
+#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_4                                                                 0x08e1
+#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ3_FLIP_PARAMETERS_0                                                                   0x08e2
+#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_1                                                                   0x08e3
+#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_2                                                                   0x08e4
+#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ3_NOM_PARAMETERS_0                                                                    0x08e5
+#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_1                                                                    0x08e6
+#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_2                                                                    0x08e7
+#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_3                                                                    0x08e8
+#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_4                                                                    0x08e9
+#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_5                                                                    0x08ea
+#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_6                                                                    0x08eb
+#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_7                                                                    0x08ec
+#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ3_PER_LINE_DELIVERY_PRE                                                               0x08ed
+#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ3_PER_LINE_DELIVERY                                                                   0x08ee
+#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ3_CURSOR_SETTINGS                                                                     0x08ef
+#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ                                                                0x08f0
+#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT                                                               0x08f1
+#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL                                                                0x08f2
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS                                                              0x08f3
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ3_VBLANK_PARAMETERS_5                                                                 0x08f6
+#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_6                                                                 0x08f7
+#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ3_FLIP_PARAMETERS_3                                                                   0x08f8
+#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_4                                                                   0x08f9
+#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_5                                                                   0x08fa
+#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_6                                                                   0x08fb
+#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+#define regHUBPREQ3_UCLK_PSTATE_FORCE                                                                   0x08fc
+#define regHUBPREQ3_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
+#define regHUBPREQ3_HUBPREQ_STATUS_REG0                                                                 0x08fd
+#define regHUBPREQ3_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
+#define regHUBPREQ3_HUBPREQ_STATUS_REG1                                                                 0x08fe
+#define regHUBPREQ3_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
+#define regHUBPREQ3_HUBPREQ_STATUS_REG2                                                                 0x08ff
+#define regHUBPREQ3_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2
+
+
+// addressBlock: dcn_dc_dcbubp3_dispdec_hubpret_dispdec
+// base address: 0xa50
+#define regHUBPRET3_HUBPRET_CONTROL                                                                     0x0900
+#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL                                                                0x0901
+#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS                                                              0x0902
+#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0                                                             0x0903
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1                                                             0x0904
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET3_HUBPRET_READ_LINE0                                                                  0x0905
+#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET3_HUBPRET_READ_LINE1                                                                  0x0906
+#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET3_HUBPRET_INTERRUPT                                                                   0x0907
+#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET3_HUBPRET_READ_LINE_VALUE                                                             0x0908
+#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET3_HUBPRET_READ_LINE_STATUS                                                            0x0909
+#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dcn_dc_dcbubp3_dispdec_cursor0_dispdec
+// base address: 0xa50
+#define regCURSOR0_3_CURSOR_CONTROL                                                                     0x090c
+#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS                                                             0x090d
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x090e
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_3_CURSOR_SIZE                                                                        0x090f
+#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_3_CURSOR_POSITION                                                                    0x0910
+#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_3_CURSOR_HOT_SPOT                                                                    0x0911
+#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_3_CURSOR_STEREO_CONTROL                                                              0x0912
+#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_3_CURSOR_DST_OFFSET                                                                  0x0913
+#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL                                                                0x0914
+#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS                                                              0x0915
+#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_3_DMDATA_ADDRESS_HIGH                                                                0x0916
+#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_3_DMDATA_ADDRESS_LOW                                                                 0x0917
+#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_3_DMDATA_CNTL                                                                        0x0918
+#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_3_DMDATA_QOS_CNTL                                                                    0x0919
+#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_3_DMDATA_STATUS                                                                      0x091a
+#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_3_DMDATA_SW_CNTL                                                                     0x091b
+#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_3_DMDATA_SW_DATA                                                                     0x091c
+#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dcn_dc_dpp0_dispdec_cnvc_cfg_dispdec
+// base address: 0x0
+#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0ccf
+#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG0_FORMAT_CONTROL                                                                     0x0cd0
+#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_BIAS_R                                                                     0x0cd1
+#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_BIAS_G                                                                     0x0cd2
+#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_BIAS_B                                                                     0x0cd3
+#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_SCALE_R                                                                    0x0cd4
+#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG0_FCNV_FP_SCALE_G                                                                    0x0cd5
+#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG0_FCNV_FP_SCALE_B                                                                    0x0cd6
+#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG0_COLOR_KEYER_CONTROL                                                                0x0cd7
+#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG0_COLOR_KEYER_ALPHA                                                                  0x0cd8
+#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG0_COLOR_KEYER_RED                                                                    0x0cd9
+#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG0_COLOR_KEYER_GREEN                                                                  0x0cda
+#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG0_COLOR_KEYER_BLUE                                                                   0x0cdb
+#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG0_ALPHA_2BIT_LUT                                                                     0x0cdd
+#define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG0_PRE_DEALPHA                                                                        0x0cde
+#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG0_PRE_CSC_MODE                                                                       0x0cdf
+#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG0_PRE_CSC_C11_C12                                                                    0x0ce0
+#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C13_C14                                                                    0x0ce1
+#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C21_C22                                                                    0x0ce2
+#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C23_C24                                                                    0x0ce3
+#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C31_C32                                                                    0x0ce4
+#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C33_C34                                                                    0x0ce5
+#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_B_C11_C12                                                                  0x0ce6
+#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C13_C14                                                                  0x0ce7
+#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C21_C22                                                                  0x0ce8
+#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C23_C24                                                                  0x0ce9
+#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C31_C32                                                                  0x0cea
+#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C33_C34                                                                  0x0ceb
+#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG0_CNVC_COEF_FORMAT                                                                   0x0cec
+#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG0_PRE_DEGAM                                                                          0x0ced
+#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG0_PRE_REALPHA                                                                        0x0cee
+#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dcn_dc_dpp0_dispdec_cnvc_cur_dispdec
+// base address: 0x0
+#define regCNVC_CUR0_CURSOR0_CONTROL                                                                    0x0cf1
+#define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR0_CURSOR0_COLOR0                                                                     0x0cf2
+#define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR0_CURSOR0_COLOR1                                                                     0x0cf3
+#define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS                                                              0x0cf4
+#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_dpp0_dispdec_dscl_dispdec
+// base address: 0x0
+#define regDSCL0_SCL_COEF_RAM_TAP_SELECT                                                                0x0cf9
+#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL0_SCL_COEF_RAM_TAP_DATA                                                                  0x0cfa
+#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL0_SCL_MODE                                                                               0x0cfb
+#define regDSCL0_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL0_SCL_TAP_CONTROL                                                                        0x0cfc
+#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL0_DSCL_CONTROL                                                                           0x0cfd
+#define regDSCL0_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL0_DSCL_2TAP_CONTROL                                                                      0x0cfe
+#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0cff
+#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0d00
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL0_SCL_HORZ_FILTER_INIT                                                                   0x0d01
+#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0d02
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL0_SCL_HORZ_FILTER_INIT_C                                                                 0x0d03
+#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0d04
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL0_SCL_VERT_FILTER_INIT                                                                   0x0d05
+#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT                                                               0x0d06
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0d07
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL0_SCL_VERT_FILTER_INIT_C                                                                 0x0d08
+#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0d09
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL0_SCL_BLACK_COLOR                                                                        0x0d0a
+#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL0_DSCL_UPDATE                                                                            0x0d0b
+#define regDSCL0_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL0_DSCL_AUTOCAL                                                                           0x0d0c
+#define regDSCL0_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0d0d
+#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0d0e
+#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL0_OTG_H_BLANK                                                                            0x0d0f
+#define regDSCL0_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL0_OTG_V_BLANK                                                                            0x0d10
+#define regDSCL0_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL0_RECOUT_START                                                                           0x0d11
+#define regDSCL0_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL0_RECOUT_SIZE                                                                            0x0d12
+#define regDSCL0_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL0_MPC_SIZE                                                                               0x0d13
+#define regDSCL0_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL0_LB_DATA_FORMAT                                                                         0x0d14
+#define regDSCL0_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL0_LB_MEMORY_CTRL                                                                         0x0d15
+#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL0_LB_V_COUNTER                                                                           0x0d16
+#define regDSCL0_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL0_DSCL_MEM_PWR_CTRL                                                                      0x0d17
+#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL0_DSCL_MEM_PWR_STATUS                                                                    0x0d18
+#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL0_OBUF_CONTROL                                                                           0x0d19
+#define regDSCL0_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL0_OBUF_MEM_PWR_CTRL                                                                      0x0d1a
+#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_dpp0_dispdec_cm_dispdec
+// base address: 0x0
+#define regCM0_CM_CONTROL                                                                               0x0d20
+#define regCM0_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM0_CM_POST_CSC_CONTROL                                                                      0x0d21
+#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C11_C12                                                                      0x0d22
+#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C13_C14                                                                      0x0d23
+#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C21_C22                                                                      0x0d24
+#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C23_C24                                                                      0x0d25
+#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C31_C32                                                                      0x0d26
+#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C33_C34                                                                      0x0d27
+#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_B_C11_C12                                                                    0x0d28
+#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C13_C14                                                                    0x0d29
+#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C21_C22                                                                    0x0d2a
+#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C23_C24                                                                    0x0d2b
+#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C31_C32                                                                    0x0d2c
+#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C33_C34                                                                    0x0d2d
+#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM0_CM_GAMUT_REMAP_CONTROL                                                                   0x0d2e
+#define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C11_C12                                                                   0x0d2f
+#define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C13_C14                                                                   0x0d30
+#define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C21_C22                                                                   0x0d31
+#define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C23_C24                                                                   0x0d32
+#define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C31_C32                                                                   0x0d33
+#define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C33_C34                                                                   0x0d34
+#define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0d35
+#define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0d36
+#define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0d37
+#define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0d38
+#define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0d39
+#define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0d3a
+#define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM0_CM_BIAS_CR_R                                                                             0x0d3b
+#define regCM0_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM0_CM_BIAS_Y_G_CB_B                                                                         0x0d3c
+#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM0_CM_GAMCOR_CONTROL                                                                        0x0d3d
+#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM0_CM_GAMCOR_LUT_INDEX                                                                      0x0d3e
+#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM0_CM_GAMCOR_LUT_DATA                                                                       0x0d3f
+#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM0_CM_GAMCOR_LUT_CONTROL                                                                    0x0d40
+#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0d41
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0d42
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0d43
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0d44
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0d45
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0d46
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0d47
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0d48
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0d49
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0d4a
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0d4b
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0d4c
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0d4d
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0d4e
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0d4f
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0d50
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0d51
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0d52
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0d53
+#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0d54
+#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0d55
+#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0d56
+#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0d57
+#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0d58
+#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0d59
+#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0d5a
+#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0d5b
+#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0d5c
+#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0d5d
+#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0d5e
+#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0d5f
+#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0d60
+#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0d61
+#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0d62
+#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0d63
+#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0d64
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0d65
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0d66
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0d67
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0d68
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0d69
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0d6a
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0d6b
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0d6c
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0d6d
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0d6e
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0d6f
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0d70
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0d71
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0d72
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0d73
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0d74
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0d75
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0d76
+#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0d77
+#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0d78
+#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0d79
+#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0d7a
+#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0d7b
+#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0d7c
+#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0d7d
+#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0d7e
+#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0d7f
+#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0d80
+#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0d81
+#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0d82
+#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0d83
+#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0d84
+#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0d85
+#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0d86
+#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM0_CM_HDR_MULT_COEF                                                                         0x0d87
+#define regCM0_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM0_CM_MEM_PWR_CTRL                                                                          0x0d88
+#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM0_CM_MEM_PWR_STATUS                                                                        0x0d89
+#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM0_CM_DEALPHA                                                                               0x0d8b
+#define regCM0_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM0_CM_COEF_FORMAT                                                                           0x0d8c
+#define regCM0_CM_COEF_FORMAT_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dpp0_dispdec_dpp_top_dispdec
+// base address: 0x0
+#define regDPP_TOP0_DPP_CONTROL                                                                         0x0cc5
+#define regDPP_TOP0_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP0_DPP_SOFT_RESET                                                                      0x0cc6
+#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP0_DPP_CRC_VAL_R_G                                                                     0x0cc7
+#define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP0_DPP_CRC_VAL_B_A                                                                     0x0cc8
+#define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP0_DPP_CRC_CTRL                                                                        0x0cc9
+#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP0_HOST_READ_CONTROL                                                                   0x0cca
+#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_dpp1_dispdec_cnvc_cfg_dispdec
+// base address: 0x5ac
+#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0e3a
+#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG1_FORMAT_CONTROL                                                                     0x0e3b
+#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_BIAS_R                                                                     0x0e3c
+#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_BIAS_G                                                                     0x0e3d
+#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_BIAS_B                                                                     0x0e3e
+#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_SCALE_R                                                                    0x0e3f
+#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG1_FCNV_FP_SCALE_G                                                                    0x0e40
+#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG1_FCNV_FP_SCALE_B                                                                    0x0e41
+#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG1_COLOR_KEYER_CONTROL                                                                0x0e42
+#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG1_COLOR_KEYER_ALPHA                                                                  0x0e43
+#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG1_COLOR_KEYER_RED                                                                    0x0e44
+#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG1_COLOR_KEYER_GREEN                                                                  0x0e45
+#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG1_COLOR_KEYER_BLUE                                                                   0x0e46
+#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG1_ALPHA_2BIT_LUT                                                                     0x0e48
+#define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG1_PRE_DEALPHA                                                                        0x0e49
+#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG1_PRE_CSC_MODE                                                                       0x0e4a
+#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG1_PRE_CSC_C11_C12                                                                    0x0e4b
+#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C13_C14                                                                    0x0e4c
+#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C21_C22                                                                    0x0e4d
+#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C23_C24                                                                    0x0e4e
+#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C31_C32                                                                    0x0e4f
+#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C33_C34                                                                    0x0e50
+#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_B_C11_C12                                                                  0x0e51
+#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C13_C14                                                                  0x0e52
+#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C21_C22                                                                  0x0e53
+#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C23_C24                                                                  0x0e54
+#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C31_C32                                                                  0x0e55
+#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C33_C34                                                                  0x0e56
+#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG1_CNVC_COEF_FORMAT                                                                   0x0e57
+#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG1_PRE_DEGAM                                                                          0x0e58
+#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG1_PRE_REALPHA                                                                        0x0e59
+#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dcn_dc_dpp1_dispdec_cnvc_cur_dispdec
+// base address: 0x5ac
+#define regCNVC_CUR1_CURSOR0_CONTROL                                                                    0x0e5c
+#define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR1_CURSOR0_COLOR0                                                                     0x0e5d
+#define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR1_CURSOR0_COLOR1                                                                     0x0e5e
+#define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS                                                              0x0e5f
+#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_dpp1_dispdec_dscl_dispdec
+// base address: 0x5ac
+#define regDSCL1_SCL_COEF_RAM_TAP_SELECT                                                                0x0e64
+#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL1_SCL_COEF_RAM_TAP_DATA                                                                  0x0e65
+#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL1_SCL_MODE                                                                               0x0e66
+#define regDSCL1_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL1_SCL_TAP_CONTROL                                                                        0x0e67
+#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL1_DSCL_CONTROL                                                                           0x0e68
+#define regDSCL1_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL1_DSCL_2TAP_CONTROL                                                                      0x0e69
+#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0e6a
+#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0e6b
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL1_SCL_HORZ_FILTER_INIT                                                                   0x0e6c
+#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0e6d
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL1_SCL_HORZ_FILTER_INIT_C                                                                 0x0e6e
+#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0e6f
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL1_SCL_VERT_FILTER_INIT                                                                   0x0e70
+#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT                                                               0x0e71
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0e72
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL1_SCL_VERT_FILTER_INIT_C                                                                 0x0e73
+#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0e74
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL1_SCL_BLACK_COLOR                                                                        0x0e75
+#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL1_DSCL_UPDATE                                                                            0x0e76
+#define regDSCL1_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL1_DSCL_AUTOCAL                                                                           0x0e77
+#define regDSCL1_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0e78
+#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0e79
+#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL1_OTG_H_BLANK                                                                            0x0e7a
+#define regDSCL1_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL1_OTG_V_BLANK                                                                            0x0e7b
+#define regDSCL1_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL1_RECOUT_START                                                                           0x0e7c
+#define regDSCL1_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL1_RECOUT_SIZE                                                                            0x0e7d
+#define regDSCL1_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL1_MPC_SIZE                                                                               0x0e7e
+#define regDSCL1_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL1_LB_DATA_FORMAT                                                                         0x0e7f
+#define regDSCL1_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL1_LB_MEMORY_CTRL                                                                         0x0e80
+#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL1_LB_V_COUNTER                                                                           0x0e81
+#define regDSCL1_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL1_DSCL_MEM_PWR_CTRL                                                                      0x0e82
+#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL1_DSCL_MEM_PWR_STATUS                                                                    0x0e83
+#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL1_OBUF_CONTROL                                                                           0x0e84
+#define regDSCL1_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL1_OBUF_MEM_PWR_CTRL                                                                      0x0e85
+#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_dpp1_dispdec_cm_dispdec
+// base address: 0x5ac
+#define regCM1_CM_CONTROL                                                                               0x0e8b
+#define regCM1_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM1_CM_POST_CSC_CONTROL                                                                      0x0e8c
+#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C11_C12                                                                      0x0e8d
+#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C13_C14                                                                      0x0e8e
+#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C21_C22                                                                      0x0e8f
+#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C23_C24                                                                      0x0e90
+#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C31_C32                                                                      0x0e91
+#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C33_C34                                                                      0x0e92
+#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_B_C11_C12                                                                    0x0e93
+#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C13_C14                                                                    0x0e94
+#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C21_C22                                                                    0x0e95
+#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C23_C24                                                                    0x0e96
+#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C31_C32                                                                    0x0e97
+#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C33_C34                                                                    0x0e98
+#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM1_CM_GAMUT_REMAP_CONTROL                                                                   0x0e99
+#define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C11_C12                                                                   0x0e9a
+#define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C13_C14                                                                   0x0e9b
+#define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C21_C22                                                                   0x0e9c
+#define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C23_C24                                                                   0x0e9d
+#define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C31_C32                                                                   0x0e9e
+#define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C33_C34                                                                   0x0e9f
+#define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0ea0
+#define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0ea1
+#define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0ea2
+#define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0ea3
+#define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0ea4
+#define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0ea5
+#define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM1_CM_BIAS_CR_R                                                                             0x0ea6
+#define regCM1_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM1_CM_BIAS_Y_G_CB_B                                                                         0x0ea7
+#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM1_CM_GAMCOR_CONTROL                                                                        0x0ea8
+#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM1_CM_GAMCOR_LUT_INDEX                                                                      0x0ea9
+#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM1_CM_GAMCOR_LUT_DATA                                                                       0x0eaa
+#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM1_CM_GAMCOR_LUT_CONTROL                                                                    0x0eab
+#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0eac
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0ead
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0eae
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0eaf
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0eb0
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0eb1
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0eb2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0eb3
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0eb4
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0eb5
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0eb6
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0eb7
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0eb8
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0eb9
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0eba
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0ebb
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0ebc
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0ebd
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0ebe
+#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0ebf
+#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0ec0
+#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0ec1
+#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0ec2
+#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0ec3
+#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0ec4
+#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0ec5
+#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0ec6
+#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0ec7
+#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0ec8
+#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0ec9
+#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0eca
+#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0ecb
+#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0ecc
+#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0ecd
+#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0ece
+#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0ecf
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0ed0
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0ed1
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0ed2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0ed3
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0ed4
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0ed5
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0ed6
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0ed7
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0ed8
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0ed9
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0eda
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0edb
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0edc
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0edd
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0ede
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0edf
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0ee0
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0ee1
+#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0ee2
+#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0ee3
+#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0ee4
+#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0ee5
+#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0ee6
+#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0ee7
+#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0ee8
+#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0ee9
+#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0eea
+#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0eeb
+#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0eec
+#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0eed
+#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0eee
+#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0eef
+#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0ef0
+#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0ef1
+#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM1_CM_HDR_MULT_COEF                                                                         0x0ef2
+#define regCM1_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM1_CM_MEM_PWR_CTRL                                                                          0x0ef3
+#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM1_CM_MEM_PWR_STATUS                                                                        0x0ef4
+#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM1_CM_DEALPHA                                                                               0x0ef6
+#define regCM1_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM1_CM_COEF_FORMAT                                                                           0x0ef7
+#define regCM1_CM_COEF_FORMAT_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dpp1_dispdec_dpp_top_dispdec
+// base address: 0x5ac
+#define regDPP_TOP1_DPP_CONTROL                                                                         0x0e30
+#define regDPP_TOP1_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP1_DPP_SOFT_RESET                                                                      0x0e31
+#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP1_DPP_CRC_VAL_R_G                                                                     0x0e32
+#define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP1_DPP_CRC_VAL_B_A                                                                     0x0e33
+#define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP1_DPP_CRC_CTRL                                                                        0x0e34
+#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP1_HOST_READ_CONTROL                                                                   0x0e35
+#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_dpp2_dispdec_cnvc_cfg_dispdec
+// base address: 0xb58
+#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0fa5
+#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG2_FORMAT_CONTROL                                                                     0x0fa6
+#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_BIAS_R                                                                     0x0fa7
+#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_BIAS_G                                                                     0x0fa8
+#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_BIAS_B                                                                     0x0fa9
+#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_SCALE_R                                                                    0x0faa
+#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG2_FCNV_FP_SCALE_G                                                                    0x0fab
+#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG2_FCNV_FP_SCALE_B                                                                    0x0fac
+#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG2_COLOR_KEYER_CONTROL                                                                0x0fad
+#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG2_COLOR_KEYER_ALPHA                                                                  0x0fae
+#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG2_COLOR_KEYER_RED                                                                    0x0faf
+#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG2_COLOR_KEYER_GREEN                                                                  0x0fb0
+#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG2_COLOR_KEYER_BLUE                                                                   0x0fb1
+#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG2_ALPHA_2BIT_LUT                                                                     0x0fb3
+#define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG2_PRE_DEALPHA                                                                        0x0fb4
+#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG2_PRE_CSC_MODE                                                                       0x0fb5
+#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG2_PRE_CSC_C11_C12                                                                    0x0fb6
+#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C13_C14                                                                    0x0fb7
+#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C21_C22                                                                    0x0fb8
+#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C23_C24                                                                    0x0fb9
+#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C31_C32                                                                    0x0fba
+#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C33_C34                                                                    0x0fbb
+#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_B_C11_C12                                                                  0x0fbc
+#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C13_C14                                                                  0x0fbd
+#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C21_C22                                                                  0x0fbe
+#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C23_C24                                                                  0x0fbf
+#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C31_C32                                                                  0x0fc0
+#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C33_C34                                                                  0x0fc1
+#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG2_CNVC_COEF_FORMAT                                                                   0x0fc2
+#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG2_PRE_DEGAM                                                                          0x0fc3
+#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG2_PRE_REALPHA                                                                        0x0fc4
+#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dcn_dc_dpp2_dispdec_cnvc_cur_dispdec
+// base address: 0xb58
+#define regCNVC_CUR2_CURSOR0_CONTROL                                                                    0x0fc7
+#define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR2_CURSOR0_COLOR0                                                                     0x0fc8
+#define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR2_CURSOR0_COLOR1                                                                     0x0fc9
+#define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS                                                              0x0fca
+#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_dpp2_dispdec_dscl_dispdec
+// base address: 0xb58
+#define regDSCL2_SCL_COEF_RAM_TAP_SELECT                                                                0x0fcf
+#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL2_SCL_COEF_RAM_TAP_DATA                                                                  0x0fd0
+#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL2_SCL_MODE                                                                               0x0fd1
+#define regDSCL2_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL2_SCL_TAP_CONTROL                                                                        0x0fd2
+#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL2_DSCL_CONTROL                                                                           0x0fd3
+#define regDSCL2_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL2_DSCL_2TAP_CONTROL                                                                      0x0fd4
+#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0fd5
+#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0fd6
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL2_SCL_HORZ_FILTER_INIT                                                                   0x0fd7
+#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0fd8
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL2_SCL_HORZ_FILTER_INIT_C                                                                 0x0fd9
+#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0fda
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL2_SCL_VERT_FILTER_INIT                                                                   0x0fdb
+#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT                                                               0x0fdc
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0fdd
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL2_SCL_VERT_FILTER_INIT_C                                                                 0x0fde
+#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0fdf
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL2_SCL_BLACK_COLOR                                                                        0x0fe0
+#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL2_DSCL_UPDATE                                                                            0x0fe1
+#define regDSCL2_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL2_DSCL_AUTOCAL                                                                           0x0fe2
+#define regDSCL2_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0fe3
+#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0fe4
+#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL2_OTG_H_BLANK                                                                            0x0fe5
+#define regDSCL2_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL2_OTG_V_BLANK                                                                            0x0fe6
+#define regDSCL2_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL2_RECOUT_START                                                                           0x0fe7
+#define regDSCL2_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL2_RECOUT_SIZE                                                                            0x0fe8
+#define regDSCL2_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL2_MPC_SIZE                                                                               0x0fe9
+#define regDSCL2_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL2_LB_DATA_FORMAT                                                                         0x0fea
+#define regDSCL2_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL2_LB_MEMORY_CTRL                                                                         0x0feb
+#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL2_LB_V_COUNTER                                                                           0x0fec
+#define regDSCL2_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL2_DSCL_MEM_PWR_CTRL                                                                      0x0fed
+#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL2_DSCL_MEM_PWR_STATUS                                                                    0x0fee
+#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL2_OBUF_CONTROL                                                                           0x0fef
+#define regDSCL2_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL2_OBUF_MEM_PWR_CTRL                                                                      0x0ff0
+#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_dpp2_dispdec_cm_dispdec
+// base address: 0xb58
+#define regCM2_CM_CONTROL                                                                               0x0ff6
+#define regCM2_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM2_CM_POST_CSC_CONTROL                                                                      0x0ff7
+#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C11_C12                                                                      0x0ff8
+#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C13_C14                                                                      0x0ff9
+#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C21_C22                                                                      0x0ffa
+#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C23_C24                                                                      0x0ffb
+#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C31_C32                                                                      0x0ffc
+#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C33_C34                                                                      0x0ffd
+#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_B_C11_C12                                                                    0x0ffe
+#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C13_C14                                                                    0x0fff
+#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C21_C22                                                                    0x1000
+#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C23_C24                                                                    0x1001
+#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C31_C32                                                                    0x1002
+#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C33_C34                                                                    0x1003
+#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM2_CM_GAMUT_REMAP_CONTROL                                                                   0x1004
+#define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C11_C12                                                                   0x1005
+#define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C13_C14                                                                   0x1006
+#define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C21_C22                                                                   0x1007
+#define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C23_C24                                                                   0x1008
+#define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C31_C32                                                                   0x1009
+#define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C33_C34                                                                   0x100a
+#define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_B_C11_C12                                                                 0x100b
+#define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C13_C14                                                                 0x100c
+#define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C21_C22                                                                 0x100d
+#define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C23_C24                                                                 0x100e
+#define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C31_C32                                                                 0x100f
+#define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C33_C34                                                                 0x1010
+#define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM2_CM_BIAS_CR_R                                                                             0x1011
+#define regCM2_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM2_CM_BIAS_Y_G_CB_B                                                                         0x1012
+#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM2_CM_GAMCOR_CONTROL                                                                        0x1013
+#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM2_CM_GAMCOR_LUT_INDEX                                                                      0x1014
+#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM2_CM_GAMCOR_LUT_DATA                                                                       0x1015
+#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM2_CM_GAMCOR_LUT_CONTROL                                                                    0x1016
+#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1017
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1018
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1019
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x101a
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x101b
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x101c
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x101d
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x101e
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x101f
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x1020
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x1021
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x1022
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x1023
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x1024
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1025
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1026
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1027
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1028
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1029
+#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_2_3                                                                0x102a
+#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_4_5                                                                0x102b
+#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_6_7                                                                0x102c
+#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_8_9                                                                0x102d
+#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_10_11                                                              0x102e
+#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_12_13                                                              0x102f
+#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_14_15                                                              0x1030
+#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_16_17                                                              0x1031
+#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_18_19                                                              0x1032
+#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_20_21                                                              0x1033
+#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_22_23                                                              0x1034
+#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_24_25                                                              0x1035
+#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_26_27                                                              0x1036
+#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_28_29                                                              0x1037
+#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_30_31                                                              0x1038
+#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_32_33                                                              0x1039
+#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x103a
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x103b
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x103c
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x103d
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x103e
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x103f
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x1040
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x1041
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x1042
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x1043
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x1044
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x1045
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x1046
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x1047
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x1048
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x1049
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x104a
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x104b
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMB_REGION_0_1                                                                0x104c
+#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_2_3                                                                0x104d
+#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_4_5                                                                0x104e
+#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_6_7                                                                0x104f
+#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_8_9                                                                0x1050
+#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_10_11                                                              0x1051
+#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_12_13                                                              0x1052
+#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_14_15                                                              0x1053
+#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_16_17                                                              0x1054
+#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_18_19                                                              0x1055
+#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_20_21                                                              0x1056
+#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_22_23                                                              0x1057
+#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_24_25                                                              0x1058
+#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_26_27                                                              0x1059
+#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_28_29                                                              0x105a
+#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_30_31                                                              0x105b
+#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_32_33                                                              0x105c
+#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM2_CM_HDR_MULT_COEF                                                                         0x105d
+#define regCM2_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM2_CM_MEM_PWR_CTRL                                                                          0x105e
+#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM2_CM_MEM_PWR_STATUS                                                                        0x105f
+#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM2_CM_DEALPHA                                                                               0x1061
+#define regCM2_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM2_CM_COEF_FORMAT                                                                           0x1062
+#define regCM2_CM_COEF_FORMAT_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dpp2_dispdec_dpp_top_dispdec
+// base address: 0xb58
+#define regDPP_TOP2_DPP_CONTROL                                                                         0x0f9b
+#define regDPP_TOP2_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP2_DPP_SOFT_RESET                                                                      0x0f9c
+#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP2_DPP_CRC_VAL_R_G                                                                     0x0f9d
+#define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP2_DPP_CRC_VAL_B_A                                                                     0x0f9e
+#define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP2_DPP_CRC_CTRL                                                                        0x0f9f
+#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP2_HOST_READ_CONTROL                                                                   0x0fa0
+#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_dpp3_dispdec_cnvc_cfg_dispdec
+// base address: 0x1104
+#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT                                                          0x1110
+#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG3_FORMAT_CONTROL                                                                     0x1111
+#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_BIAS_R                                                                     0x1112
+#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_BIAS_G                                                                     0x1113
+#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_BIAS_B                                                                     0x1114
+#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_SCALE_R                                                                    0x1115
+#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG3_FCNV_FP_SCALE_G                                                                    0x1116
+#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG3_FCNV_FP_SCALE_B                                                                    0x1117
+#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG3_COLOR_KEYER_CONTROL                                                                0x1118
+#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG3_COLOR_KEYER_ALPHA                                                                  0x1119
+#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG3_COLOR_KEYER_RED                                                                    0x111a
+#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG3_COLOR_KEYER_GREEN                                                                  0x111b
+#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG3_COLOR_KEYER_BLUE                                                                   0x111c
+#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG3_ALPHA_2BIT_LUT                                                                     0x111e
+#define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG3_PRE_DEALPHA                                                                        0x111f
+#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG3_PRE_CSC_MODE                                                                       0x1120
+#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG3_PRE_CSC_C11_C12                                                                    0x1121
+#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C13_C14                                                                    0x1122
+#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C21_C22                                                                    0x1123
+#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C23_C24                                                                    0x1124
+#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C31_C32                                                                    0x1125
+#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C33_C34                                                                    0x1126
+#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_B_C11_C12                                                                  0x1127
+#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C13_C14                                                                  0x1128
+#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C21_C22                                                                  0x1129
+#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C23_C24                                                                  0x112a
+#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C31_C32                                                                  0x112b
+#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C33_C34                                                                  0x112c
+#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG3_CNVC_COEF_FORMAT                                                                   0x112d
+#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG3_PRE_DEGAM                                                                          0x112e
+#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG3_PRE_REALPHA                                                                        0x112f
+#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dcn_dc_dpp3_dispdec_cnvc_cur_dispdec
+// base address: 0x1104
+#define regCNVC_CUR3_CURSOR0_CONTROL                                                                    0x1132
+#define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR3_CURSOR0_COLOR0                                                                     0x1133
+#define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR3_CURSOR0_COLOR1                                                                     0x1134
+#define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS                                                              0x1135
+#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_dpp3_dispdec_dscl_dispdec
+// base address: 0x1104
+#define regDSCL3_SCL_COEF_RAM_TAP_SELECT                                                                0x113a
+#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL3_SCL_COEF_RAM_TAP_DATA                                                                  0x113b
+#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL3_SCL_MODE                                                                               0x113c
+#define regDSCL3_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL3_SCL_TAP_CONTROL                                                                        0x113d
+#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL3_DSCL_CONTROL                                                                           0x113e
+#define regDSCL3_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL3_DSCL_2TAP_CONTROL                                                                      0x113f
+#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL                                                           0x1140
+#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x1141
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL3_SCL_HORZ_FILTER_INIT                                                                   0x1142
+#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x1143
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL3_SCL_HORZ_FILTER_INIT_C                                                                 0x1144
+#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO                                                            0x1145
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL3_SCL_VERT_FILTER_INIT                                                                   0x1146
+#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT                                                               0x1147
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x1148
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL3_SCL_VERT_FILTER_INIT_C                                                                 0x1149
+#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C                                                             0x114a
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL3_SCL_BLACK_COLOR                                                                        0x114b
+#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL3_DSCL_UPDATE                                                                            0x114c
+#define regDSCL3_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL3_DSCL_AUTOCAL                                                                           0x114d
+#define regDSCL3_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x114e
+#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x114f
+#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL3_OTG_H_BLANK                                                                            0x1150
+#define regDSCL3_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL3_OTG_V_BLANK                                                                            0x1151
+#define regDSCL3_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL3_RECOUT_START                                                                           0x1152
+#define regDSCL3_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL3_RECOUT_SIZE                                                                            0x1153
+#define regDSCL3_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL3_MPC_SIZE                                                                               0x1154
+#define regDSCL3_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL3_LB_DATA_FORMAT                                                                         0x1155
+#define regDSCL3_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL3_LB_MEMORY_CTRL                                                                         0x1156
+#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL3_LB_V_COUNTER                                                                           0x1157
+#define regDSCL3_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL3_DSCL_MEM_PWR_CTRL                                                                      0x1158
+#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL3_DSCL_MEM_PWR_STATUS                                                                    0x1159
+#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL3_OBUF_CONTROL                                                                           0x115a
+#define regDSCL3_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL3_OBUF_MEM_PWR_CTRL                                                                      0x115b
+#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_dpp3_dispdec_cm_dispdec
+// base address: 0x1104
+#define regCM3_CM_CONTROL                                                                               0x1161
+#define regCM3_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM3_CM_POST_CSC_CONTROL                                                                      0x1162
+#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C11_C12                                                                      0x1163
+#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C13_C14                                                                      0x1164
+#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C21_C22                                                                      0x1165
+#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C23_C24                                                                      0x1166
+#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C31_C32                                                                      0x1167
+#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C33_C34                                                                      0x1168
+#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_B_C11_C12                                                                    0x1169
+#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C13_C14                                                                    0x116a
+#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C21_C22                                                                    0x116b
+#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C23_C24                                                                    0x116c
+#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C31_C32                                                                    0x116d
+#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C33_C34                                                                    0x116e
+#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM3_CM_GAMUT_REMAP_CONTROL                                                                   0x116f
+#define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C11_C12                                                                   0x1170
+#define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C13_C14                                                                   0x1171
+#define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C21_C22                                                                   0x1172
+#define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C23_C24                                                                   0x1173
+#define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C31_C32                                                                   0x1174
+#define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C33_C34                                                                   0x1175
+#define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_B_C11_C12                                                                 0x1176
+#define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C13_C14                                                                 0x1177
+#define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C21_C22                                                                 0x1178
+#define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C23_C24                                                                 0x1179
+#define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C31_C32                                                                 0x117a
+#define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C33_C34                                                                 0x117b
+#define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM3_CM_BIAS_CR_R                                                                             0x117c
+#define regCM3_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM3_CM_BIAS_Y_G_CB_B                                                                         0x117d
+#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM3_CM_GAMCOR_CONTROL                                                                        0x117e
+#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM3_CM_GAMCOR_LUT_INDEX                                                                      0x117f
+#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM3_CM_GAMCOR_LUT_DATA                                                                       0x1180
+#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM3_CM_GAMCOR_LUT_CONTROL                                                                    0x1181
+#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1182
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1183
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1184
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x1185
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x1186
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x1187
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x1188
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x1189
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x118a
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x118b
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x118c
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x118d
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x118e
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x118f
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1190
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1191
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1192
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1193
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1194
+#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_2_3                                                                0x1195
+#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_4_5                                                                0x1196
+#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_6_7                                                                0x1197
+#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_8_9                                                                0x1198
+#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_10_11                                                              0x1199
+#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_12_13                                                              0x119a
+#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_14_15                                                              0x119b
+#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_16_17                                                              0x119c
+#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_18_19                                                              0x119d
+#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_20_21                                                              0x119e
+#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_22_23                                                              0x119f
+#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_24_25                                                              0x11a0
+#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_26_27                                                              0x11a1
+#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_28_29                                                              0x11a2
+#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_30_31                                                              0x11a3
+#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_32_33                                                              0x11a4
+#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x11a5
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x11a6
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x11a7
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x11a8
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x11a9
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x11aa
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x11ab
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x11ac
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x11ad
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x11ae
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x11af
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x11b0
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x11b1
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x11b2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x11b3
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x11b4
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x11b5
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x11b6
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMB_REGION_0_1                                                                0x11b7
+#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_2_3                                                                0x11b8
+#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_4_5                                                                0x11b9
+#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_6_7                                                                0x11ba
+#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_8_9                                                                0x11bb
+#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_10_11                                                              0x11bc
+#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_12_13                                                              0x11bd
+#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_14_15                                                              0x11be
+#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_16_17                                                              0x11bf
+#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_18_19                                                              0x11c0
+#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_20_21                                                              0x11c1
+#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_22_23                                                              0x11c2
+#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_24_25                                                              0x11c3
+#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_26_27                                                              0x11c4
+#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_28_29                                                              0x11c5
+#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_30_31                                                              0x11c6
+#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_32_33                                                              0x11c7
+#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM3_CM_HDR_MULT_COEF                                                                         0x11c8
+#define regCM3_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM3_CM_MEM_PWR_CTRL                                                                          0x11c9
+#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM3_CM_MEM_PWR_STATUS                                                                        0x11ca
+#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM3_CM_DEALPHA                                                                               0x11cc
+#define regCM3_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM3_CM_COEF_FORMAT                                                                           0x11cd
+#define regCM3_CM_COEF_FORMAT_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dpp3_dispdec_dpp_top_dispdec
+// base address: 0x1104
+#define regDPP_TOP3_DPP_CONTROL                                                                         0x1106
+#define regDPP_TOP3_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP3_DPP_SOFT_RESET                                                                      0x1107
+#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP3_DPP_CRC_VAL_R_G                                                                     0x1108
+#define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP3_DPP_CRC_VAL_B_A                                                                     0x1109
+#define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP3_DPP_CRC_CTRL                                                                        0x110a
+#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP3_HOST_READ_CONTROL                                                                   0x110b
+#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_mpc_mpcc0_dispdec
+// base address: 0x0
+#define regMPCC0_MPCC_TOP_SEL                                                                           0x0000
+#define regMPCC0_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_BOT_SEL                                                                           0x0001
+#define regMPCC0_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_OPP_ID                                                                            0x0002
+#define regMPCC0_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC0_MPCC_CONTROL                                                                           0x0003
+#define regMPCC0_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_SM_CONTROL                                                                        0x0004
+#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC0_MPCC_UPDATE_LOCK_SEL                                                                   0x0005
+#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC0_MPCC_TOP_GAIN                                                                          0x0006
+#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC0_MPCC_BOT_GAIN_INSIDE                                                                   0x0007
+#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0008
+#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0009
+#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
+#define regMPCC0_MPCC_BG_R_CR                                                                           0x000a
+#define regMPCC0_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_BG_G_Y                                                                            0x000b
+#define regMPCC0_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC0_MPCC_BG_B_CB                                                                           0x000c
+#define regMPCC0_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_MEM_PWR_CTRL                                                                      0x000d
+#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC0_MPCC_STATUS                                                                            0x000e
+#define regMPCC0_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dcn_dc_mpc_mpcc1_dispdec
+// base address: 0x54
+#define regMPCC1_MPCC_TOP_SEL                                                                           0x0015
+#define regMPCC1_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_BOT_SEL                                                                           0x0016
+#define regMPCC1_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_OPP_ID                                                                            0x0017
+#define regMPCC1_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC1_MPCC_CONTROL                                                                           0x0018
+#define regMPCC1_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_SM_CONTROL                                                                        0x0019
+#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC1_MPCC_UPDATE_LOCK_SEL                                                                   0x001a
+#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC1_MPCC_TOP_GAIN                                                                          0x001b
+#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC1_MPCC_BOT_GAIN_INSIDE                                                                   0x001c
+#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE                                                                  0x001d
+#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x001e
+#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
+#define regMPCC1_MPCC_BG_R_CR                                                                           0x001f
+#define regMPCC1_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_BG_G_Y                                                                            0x0020
+#define regMPCC1_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC1_MPCC_BG_B_CB                                                                           0x0021
+#define regMPCC1_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_MEM_PWR_CTRL                                                                      0x0022
+#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC1_MPCC_STATUS                                                                            0x0023
+#define regMPCC1_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dcn_dc_mpc_mpcc2_dispdec
+// base address: 0xa8
+#define regMPCC2_MPCC_TOP_SEL                                                                           0x002a
+#define regMPCC2_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_BOT_SEL                                                                           0x002b
+#define regMPCC2_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_OPP_ID                                                                            0x002c
+#define regMPCC2_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC2_MPCC_CONTROL                                                                           0x002d
+#define regMPCC2_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_SM_CONTROL                                                                        0x002e
+#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC2_MPCC_UPDATE_LOCK_SEL                                                                   0x002f
+#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC2_MPCC_TOP_GAIN                                                                          0x0030
+#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC2_MPCC_BOT_GAIN_INSIDE                                                                   0x0031
+#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0032
+#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0033
+#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
+#define regMPCC2_MPCC_BG_R_CR                                                                           0x0034
+#define regMPCC2_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_BG_G_Y                                                                            0x0035
+#define regMPCC2_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC2_MPCC_BG_B_CB                                                                           0x0036
+#define regMPCC2_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_MEM_PWR_CTRL                                                                      0x0037
+#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC2_MPCC_STATUS                                                                            0x0038
+#define regMPCC2_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dcn_dc_mpc_mpcc3_dispdec
+// base address: 0xfc
+#define regMPCC3_MPCC_TOP_SEL                                                                           0x003f
+#define regMPCC3_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_BOT_SEL                                                                           0x0040
+#define regMPCC3_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_OPP_ID                                                                            0x0041
+#define regMPCC3_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC3_MPCC_CONTROL                                                                           0x0042
+#define regMPCC3_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_SM_CONTROL                                                                        0x0043
+#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC3_MPCC_UPDATE_LOCK_SEL                                                                   0x0044
+#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC3_MPCC_TOP_GAIN                                                                          0x0045
+#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC3_MPCC_BOT_GAIN_INSIDE                                                                   0x0046
+#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0047
+#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0048
+#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
+#define regMPCC3_MPCC_BG_R_CR                                                                           0x0049
+#define regMPCC3_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_BG_G_Y                                                                            0x004a
+#define regMPCC3_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC3_MPCC_BG_B_CB                                                                           0x004b
+#define regMPCC3_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_MEM_PWR_CTRL                                                                      0x004c
+#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC3_MPCC_STATUS                                                                            0x004d
+#define regMPCC3_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dcn_dc_mpc_mpc_cfg_dispdec
+// base address: 0x0
+#define regMPC_CLOCK_CONTROL                                                                            0x0398
+#define regMPC_CLOCK_CONTROL_BASE_IDX                                                                   3
+#define regMPC_SOFT_RESET                                                                               0x0399
+#define regMPC_SOFT_RESET_BASE_IDX                                                                      3
+#define regMPC_CRC_CTRL                                                                                 0x039a
+#define regMPC_CRC_CTRL_BASE_IDX                                                                        3
+#define regMPC_CRC_SEL_CONTROL                                                                          0x039b
+#define regMPC_CRC_SEL_CONTROL_BASE_IDX                                                                 3
+#define regMPC_CRC_RESULT_AR                                                                            0x039c
+#define regMPC_CRC_RESULT_AR_BASE_IDX                                                                   3
+#define regMPC_CRC_RESULT_GB                                                                            0x039d
+#define regMPC_CRC_RESULT_GB_BASE_IDX                                                                   3
+#define regMPC_CRC_RESULT_C                                                                             0x039e
+#define regMPC_CRC_RESULT_C_BASE_IDX                                                                    3
+#define regMPC_BYPASS_BG_AR                                                                             0x03a2
+#define regMPC_BYPASS_BG_AR_BASE_IDX                                                                    3
+#define regMPC_BYPASS_BG_GB                                                                             0x03a3
+#define regMPC_BYPASS_BG_GB_BASE_IDX                                                                    3
+#define regMPC_HOST_READ_CONTROL                                                                        0x03a4
+#define regMPC_HOST_READ_CONTROL_BASE_IDX                                                               3
+#define regMPC_DPP_PENDING_STATUS                                                                       0x03a5
+#define regMPC_DPP_PENDING_STATUS_BASE_IDX                                                              3
+#define regMPC_PENDING_STATUS_MISC                                                                      0x03a6
+#define regMPC_PENDING_STATUS_MISC_BASE_IDX                                                             3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET0                                                                0x03a7
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET0                                                                    0x03a8
+#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET0                                                                        0x03a9
+#define regADR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET0                                                                        0x03aa
+#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET0                                                                        0x03ab
+#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET1                                                                0x03ac
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET1                                                                    0x03ad
+#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET1                                                                        0x03ae
+#define regADR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET1                                                                        0x03af
+#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET1                                                                        0x03b0
+#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET2                                                                0x03b1
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET2                                                                    0x03b2
+#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET2                                                                        0x03b3
+#define regADR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET2                                                                        0x03b4
+#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET2                                                                        0x03b5
+#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET3                                                                0x03b6
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET3                                                                    0x03b7
+#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET3                                                                        0x03b8
+#define regADR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET3                                                                        0x03b9
+#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET3                                                                        0x03ba
+#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
+#define regMPC_DWB0_MUX                                                                                 0x03c6
+#define regMPC_DWB0_MUX_BASE_IDX                                                                        3
+
+
+// addressBlock: dcn_dc_mpc_mpcc_ogam0_dispdec
+// base address: 0x0
+#define regMPCC_OGAM0_MPCC_OGAM_CONTROL                                                                 0x00a8
+#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX                                                               0x00a9
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA                                                                0x00aa
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL                                                             0x00ab
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x00ac
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x00ad
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x00ae
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x00af
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x00b0
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x00b1
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x00b2
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x00b3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x00b4
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x00b5
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x00b6
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x00b7
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x00b8
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x00b9
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x00ba
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B                                                           0x00bb
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G                                                           0x00bc
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R                                                           0x00bd
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1                                                         0x00be
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3                                                         0x00bf
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5                                                         0x00c0
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7                                                         0x00c1
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9                                                         0x00c2
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11                                                       0x00c3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13                                                       0x00c4
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15                                                       0x00c5
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17                                                       0x00c6
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19                                                       0x00c7
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21                                                       0x00c8
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23                                                       0x00c9
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25                                                       0x00ca
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27                                                       0x00cb
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29                                                       0x00cc
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31                                                       0x00cd
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33                                                       0x00ce
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x00cf
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x00d0
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x00d1
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x00d2
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x00d3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x00d4
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x00d5
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x00d6
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x00d7
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x00d8
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x00d9
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x00da
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x00db
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x00dc
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x00dd
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B                                                           0x00de
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G                                                           0x00df
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R                                                           0x00e0
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1                                                         0x00e1
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3                                                         0x00e2
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5                                                         0x00e3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7                                                         0x00e4
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9                                                         0x00e5
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11                                                       0x00e6
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13                                                       0x00e7
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15                                                       0x00e8
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17                                                       0x00e9
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19                                                       0x00ea
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21                                                       0x00eb
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23                                                       0x00ec
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25                                                       0x00ed
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27                                                       0x00ee
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29                                                       0x00ef
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31                                                       0x00f0
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33                                                       0x00f1
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x00f2
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE                                                             0x00f3
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A                                                         0x00f4
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A                                                         0x00f5
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A                                                         0x00f6
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A                                                         0x00f7
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A                                                         0x00f8
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A                                                         0x00f9
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B                                                         0x00fa
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B                                                         0x00fb
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B                                                         0x00fc
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B                                                         0x00fd
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B                                                         0x00fe
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B                                                         0x00ff
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dcn_dc_mpc_mpcc_ogam1_dispdec
+// base address: 0x178
+#define regMPCC_OGAM1_MPCC_OGAM_CONTROL                                                                 0x0106
+#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX                                                               0x0107
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA                                                                0x0108
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL                                                             0x0109
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x010a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x010b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x010c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x010d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x010e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x010f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x0110
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x0111
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x0112
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x0113
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x0114
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x0115
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0116
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0117
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0118
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0119
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G                                                           0x011a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R                                                           0x011b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1                                                         0x011c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3                                                         0x011d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5                                                         0x011e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7                                                         0x011f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9                                                         0x0120
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11                                                       0x0121
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13                                                       0x0122
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15                                                       0x0123
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17                                                       0x0124
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19                                                       0x0125
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0126
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0127
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0128
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0129
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29                                                       0x012a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31                                                       0x012b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33                                                       0x012c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x012d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x012e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x012f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x0130
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x0131
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x0132
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x0133
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x0134
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x0135
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0136
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0137
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0138
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0139
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x013a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x013b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B                                                           0x013c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G                                                           0x013d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R                                                           0x013e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1                                                         0x013f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3                                                         0x0140
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5                                                         0x0141
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7                                                         0x0142
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9                                                         0x0143
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11                                                       0x0144
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13                                                       0x0145
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0146
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0147
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0148
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0149
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23                                                       0x014a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25                                                       0x014b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27                                                       0x014c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29                                                       0x014d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31                                                       0x014e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33                                                       0x014f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x0150
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE                                                             0x0151
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A                                                         0x0152
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A                                                         0x0153
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A                                                         0x0154
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A                                                         0x0155
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0156
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0157
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0158
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0159
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B                                                         0x015a
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B                                                         0x015b
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B                                                         0x015c
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B                                                         0x015d
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dcn_dc_mpc_mpcc_ogam2_dispdec
+// base address: 0x2f0
+#define regMPCC_OGAM2_MPCC_OGAM_CONTROL                                                                 0x0164
+#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX                                                               0x0165
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA                                                                0x0166
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL                                                             0x0167
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0168
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0169
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x016a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x016b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x016c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x016d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x016e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x016f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x0170
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x0171
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x0172
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x0173
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0174
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0175
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0176
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0177
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0178
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0179
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1                                                         0x017a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3                                                         0x017b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5                                                         0x017c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7                                                         0x017d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9                                                         0x017e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11                                                       0x017f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13                                                       0x0180
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15                                                       0x0181
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17                                                       0x0182
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19                                                       0x0183
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0184
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0185
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0186
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0187
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29                                                       0x0188
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31                                                       0x0189
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33                                                       0x018a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x018b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x018c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x018d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x018e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x018f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x0190
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x0191
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x0192
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x0193
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0194
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0195
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0196
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0197
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x0198
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x0199
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B                                                           0x019a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G                                                           0x019b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R                                                           0x019c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1                                                         0x019d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3                                                         0x019e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5                                                         0x019f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01a0
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01a1
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11                                                       0x01a2
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13                                                       0x01a3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15                                                       0x01a4
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17                                                       0x01a5
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19                                                       0x01a6
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21                                                       0x01a7
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23                                                       0x01a8
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25                                                       0x01a9
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27                                                       0x01aa
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29                                                       0x01ab
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31                                                       0x01ac
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33                                                       0x01ad
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x01ae
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE                                                             0x01af
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A                                                         0x01b0
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A                                                         0x01b1
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A                                                         0x01b2
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A                                                         0x01b3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A                                                         0x01b4
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A                                                         0x01b5
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B                                                         0x01b6
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B                                                         0x01b7
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B                                                         0x01b8
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B                                                         0x01b9
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B                                                         0x01ba
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B                                                         0x01bb
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dcn_dc_mpc_mpcc_ogam3_dispdec
+// base address: 0x468
+#define regMPCC_OGAM3_MPCC_OGAM_CONTROL                                                                 0x01c2
+#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX                                                               0x01c3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA                                                                0x01c4
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL                                                             0x01c5
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x01c6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x01c7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x01c8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x01c9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x01ca
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x01cb
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x01cc
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x01cd
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x01ce
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x01cf
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x01d0
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x01d1
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x01d2
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x01d3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x01d4
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B                                                           0x01d5
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G                                                           0x01d6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R                                                           0x01d7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1                                                         0x01d8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3                                                         0x01d9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5                                                         0x01da
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7                                                         0x01db
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9                                                         0x01dc
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11                                                       0x01dd
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13                                                       0x01de
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15                                                       0x01df
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17                                                       0x01e0
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19                                                       0x01e1
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21                                                       0x01e2
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23                                                       0x01e3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25                                                       0x01e4
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27                                                       0x01e5
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29                                                       0x01e6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31                                                       0x01e7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33                                                       0x01e8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x01e9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x01ea
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x01eb
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x01ec
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x01ed
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x01ee
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x01ef
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x01f0
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x01f1
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x01f2
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x01f3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x01f4
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x01f5
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x01f6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x01f7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B                                                           0x01f8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G                                                           0x01f9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R                                                           0x01fa
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1                                                         0x01fb
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3                                                         0x01fc
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5                                                         0x01fd
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01fe
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01ff
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11                                                       0x0200
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13                                                       0x0201
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0202
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0203
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0204
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0205
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23                                                       0x0206
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25                                                       0x0207
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0208
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0209
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31                                                       0x020a
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33                                                       0x020b
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x020c
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE                                                             0x020d
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A                                                         0x020e
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A                                                         0x020f
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A                                                         0x0210
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A                                                         0x0211
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0212
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0213
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0214
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0215
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B                                                         0x0216
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B                                                         0x0217
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B                                                         0x0218
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B                                                         0x0219
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dcn_dc_mpc_mpcc_mcm0_dispdec
+// base address: 0x0
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL                                                            0x0453
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0454
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0455
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0456
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R                                                            0x0457
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0458
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0459
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA                                                           0x045a
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x045b
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x045c
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x045d
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x045e
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x045f
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0460
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0461
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0462
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0463
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0464
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0465
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0466
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0467
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0468
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0469
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x046a
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x046b
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x046c
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x046d
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x046e
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x046f
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0470
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0471
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0472
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0473
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0474
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0475
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0476
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0477
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0478
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0479
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x047a
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x047b
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x047c
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x047d
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x047e
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x047f
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0480
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0481
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0482
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0483
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0484
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0485
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0486
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0487
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0488
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0489
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE                                                                0x048a
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX                                                               0x048b
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA                                                                0x048c
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x048d
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x048e
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x048f
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0490
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0491
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0492
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL                                                             0x0493
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0494
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0495
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0496
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0497
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0498
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0499
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x049a
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x049b
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x049c
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x049d
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x049e
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x049f
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x04a0
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x04a1
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x04a2
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x04a3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x04a4
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x04a5
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x04a6
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x04a7
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x04a8
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x04a9
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x04aa
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x04ab
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x04ac
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x04ad
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x04ae
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x04af
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x04b0
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x04b1
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x04b2
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x04b3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x04b4
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x04b5
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x04b6
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x04b7
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x04b8
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x04b9
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x04ba
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x04bb
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x04bc
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x04bd
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x04be
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x04bf
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x04c0
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x04c1
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x04c2
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x04c3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x04c4
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x04c5
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x04c6
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x04c7
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x04c8
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x04c9
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x04ca
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x04cb
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x04cc
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x04cd
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x04ce
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x04cf
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x04d0
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x04d1
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x04d2
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x04d3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x04d4
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x04d5
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x04d6
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x04d7
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x04d8
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x04d9
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x04da
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x04db
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x04dc
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL                                                              0x04dd
+#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3
+
+
+// addressBlock: dcn_dc_mpc_mpcc_mcm1_dispdec
+// base address: 0x240
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL                                                            0x04e3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R                                                           0x04e4
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G                                                           0x04e5
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B                                                           0x04e6
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R                                                            0x04e7
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x04e8
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x04e9
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA                                                           0x04ea
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x04eb
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x04ec
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x04ed
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x04ee
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x04ef
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x04f0
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x04f1
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x04f2
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x04f3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x04f4
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x04f5
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x04f6
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x04f7
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x04f8
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x04f9
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x04fa
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x04fb
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x04fc
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x04fd
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x04fe
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x04ff
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0500
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0501
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0502
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0503
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0504
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0505
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0506
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0507
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0508
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0509
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x050a
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x050b
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x050c
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x050d
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x050e
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x050f
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0510
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0511
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0512
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0513
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0514
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0515
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0516
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0517
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0518
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0519
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE                                                                0x051a
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX                                                               0x051b
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA                                                                0x051c
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x051d
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x051e
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x051f
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0520
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0521
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0522
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL                                                             0x0523
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0524
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0525
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0526
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0527
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0528
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0529
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x052a
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x052b
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x052c
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x052d
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x052e
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x052f
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x0530
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x0531
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x0532
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x0533
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x0534
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x0535
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x0536
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x0537
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x0538
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x0539
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x053a
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x053b
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x053c
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x053d
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x053e
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x053f
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x0540
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x0541
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x0542
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x0543
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x0544
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x0545
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x0546
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x0547
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x0548
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x0549
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x054a
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x054b
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x054c
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x054d
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x054e
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x054f
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x0550
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x0551
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x0552
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x0553
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x0554
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x0555
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x0556
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x0557
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x0558
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x0559
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x055a
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x055b
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x055c
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x055d
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x055e
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x055f
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x0560
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x0561
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x0562
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x0563
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x0564
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x0565
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x0566
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x0567
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x0568
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x0569
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x056a
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x056b
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x056c
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL                                                              0x056d
+#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3
+
+
+// addressBlock: dcn_dc_mpc_mpcc_mcm2_dispdec
+// base address: 0x480
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL                                                            0x0573
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0574
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0575
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0576
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R                                                            0x0577
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0578
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0579
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA                                                           0x057a
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x057b
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x057c
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x057d
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x057e
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x057f
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0580
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0581
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0582
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0583
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0584
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0585
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0586
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0587
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0588
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0589
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x058a
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x058b
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x058c
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x058d
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x058e
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x058f
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0590
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0591
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0592
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0593
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0594
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0595
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0596
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0597
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0598
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0599
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x059a
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x059b
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x059c
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x059d
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x059e
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x059f
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x05a0
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x05a1
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x05a2
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x05a3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x05a4
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x05a5
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x05a6
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x05a7
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x05a8
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x05a9
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE                                                                0x05aa
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX                                                               0x05ab
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA                                                                0x05ac
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x05ad
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x05ae
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x05af
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x05b0
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x05b1
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x05b2
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL                                                             0x05b3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x05b4
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA                                                            0x05b5
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x05b6
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x05b7
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x05b8
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x05b9
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x05ba
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x05bb
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x05bc
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x05bd
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x05be
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x05bf
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x05c0
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x05c1
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x05c2
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x05c3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x05c4
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x05c5
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x05c6
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x05c7
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x05c8
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x05c9
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x05ca
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x05cb
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x05cc
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x05cd
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x05ce
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x05cf
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x05d0
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x05d1
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x05d2
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x05d3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x05d4
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x05d5
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x05d6
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x05d7
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x05d8
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x05d9
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x05da
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x05db
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x05dc
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x05dd
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x05de
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x05df
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x05e0
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x05e1
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x05e2
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x05e3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x05e4
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x05e5
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x05e6
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x05e7
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x05e8
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x05e9
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x05ea
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x05eb
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x05ec
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x05ed
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x05ee
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x05ef
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x05f0
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x05f1
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x05f2
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x05f3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x05f4
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x05f5
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x05f6
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x05f7
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x05f8
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x05f9
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x05fa
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x05fb
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x05fc
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL                                                              0x05fd
+#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3
+
+
+// addressBlock: dcn_dc_mpc_mpcc_mcm3_dispdec
+// base address: 0x6c0
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL                                                            0x0603
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0604
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0605
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0606
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R                                                            0x0607
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0608
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0609
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA                                                           0x060a
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x060b
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x060c
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x060d
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x060e
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x060f
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0610
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0611
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0612
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0613
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0614
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0615
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0616
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0617
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0618
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0619
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x061a
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x061b
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x061c
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x061d
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x061e
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x061f
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0620
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0621
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0622
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0623
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0624
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0625
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0626
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0627
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0628
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0629
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x062a
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x062b
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x062c
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x062d
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x062e
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x062f
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0630
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0631
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0632
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0633
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0634
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0635
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0636
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0637
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0638
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0639
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE                                                                0x063a
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX                                                               0x063b
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA                                                                0x063c
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x063d
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x063e
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x063f
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0640
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0641
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0642
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL                                                             0x0643
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0644
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0645
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0646
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0647
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0648
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0649
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x064a
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x064b
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x064c
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x064d
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x064e
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x064f
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x0650
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x0651
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x0652
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x0653
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x0654
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x0655
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x0656
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x0657
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x0658
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x0659
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x065a
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x065b
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x065c
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x065d
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x065e
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x065f
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x0660
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x0661
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x0662
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x0663
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x0664
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x0665
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x0666
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x0667
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x0668
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x0669
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x066a
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x066b
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x066c
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x066d
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x066e
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x066f
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x0670
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x0671
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x0672
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x0673
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x0674
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x0675
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x0676
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x0677
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x0678
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x0679
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x067a
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x067b
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x067c
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x067d
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x067e
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x067f
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x0680
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x0681
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x0682
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x0683
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x0684
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x0685
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x0686
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x0687
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x0688
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x0689
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x068a
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x068b
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x068c
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL                                                              0x068d
+#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3
+
+
+// addressBlock: dcn_dc_mpc_mpc_ocsc_dispdec
+// base address: 0x0
+#define regMPC_OUT0_MUX                                                                                 0x03d8
+#define regMPC_OUT0_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT0_DENORM_CONTROL                                                                      0x03d9
+#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT0_DENORM_CLAMP_G_Y                                                                    0x03da
+#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT0_DENORM_CLAMP_B_CB                                                                   0x03db
+#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT1_MUX                                                                                 0x03dc
+#define regMPC_OUT1_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT1_DENORM_CONTROL                                                                      0x03dd
+#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT1_DENORM_CLAMP_G_Y                                                                    0x03de
+#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT1_DENORM_CLAMP_B_CB                                                                   0x03df
+#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT2_MUX                                                                                 0x03e0
+#define regMPC_OUT2_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT2_DENORM_CONTROL                                                                      0x03e1
+#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT2_DENORM_CLAMP_G_Y                                                                    0x03e2
+#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT2_DENORM_CLAMP_B_CB                                                                   0x03e3
+#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT3_MUX                                                                                 0x03e4
+#define regMPC_OUT3_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT3_DENORM_CONTROL                                                                      0x03e5
+#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT3_DENORM_CLAMP_G_Y                                                                    0x03e6
+#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT3_DENORM_CLAMP_B_CB                                                                   0x03e7
+#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT_CSC_COEF_FORMAT                                                                      0x03f0
+#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX                                                             3
+#define regMPC_OUT0_CSC_MODE                                                                            0x03f1
+#define regMPC_OUT0_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT0_CSC_C11_C12_A                                                                       0x03f2
+#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C13_C14_A                                                                       0x03f3
+#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C21_C22_A                                                                       0x03f4
+#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C23_C24_A                                                                       0x03f5
+#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C31_C32_A                                                                       0x03f6
+#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C33_C34_A                                                                       0x03f7
+#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C11_C12_B                                                                       0x03f8
+#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C13_C14_B                                                                       0x03f9
+#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C21_C22_B                                                                       0x03fa
+#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C23_C24_B                                                                       0x03fb
+#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C31_C32_B                                                                       0x03fc
+#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C33_C34_B                                                                       0x03fd
+#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_MODE                                                                            0x03fe
+#define regMPC_OUT1_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT1_CSC_C11_C12_A                                                                       0x03ff
+#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C13_C14_A                                                                       0x0400
+#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C21_C22_A                                                                       0x0401
+#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C23_C24_A                                                                       0x0402
+#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C31_C32_A                                                                       0x0403
+#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C33_C34_A                                                                       0x0404
+#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C11_C12_B                                                                       0x0405
+#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C13_C14_B                                                                       0x0406
+#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C21_C22_B                                                                       0x0407
+#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C23_C24_B                                                                       0x0408
+#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C31_C32_B                                                                       0x0409
+#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C33_C34_B                                                                       0x040a
+#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_MODE                                                                            0x040b
+#define regMPC_OUT2_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT2_CSC_C11_C12_A                                                                       0x040c
+#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C13_C14_A                                                                       0x040d
+#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C21_C22_A                                                                       0x040e
+#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C23_C24_A                                                                       0x040f
+#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C31_C32_A                                                                       0x0410
+#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C33_C34_A                                                                       0x0411
+#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C11_C12_B                                                                       0x0412
+#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C13_C14_B                                                                       0x0413
+#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C21_C22_B                                                                       0x0414
+#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C23_C24_B                                                                       0x0415
+#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C31_C32_B                                                                       0x0416
+#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C33_C34_B                                                                       0x0417
+#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_MODE                                                                            0x0418
+#define regMPC_OUT3_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT3_CSC_C11_C12_A                                                                       0x0419
+#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C13_C14_A                                                                       0x041a
+#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C21_C22_A                                                                       0x041b
+#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C23_C24_A                                                                       0x041c
+#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C31_C32_A                                                                       0x041d
+#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C33_C34_A                                                                       0x041e
+#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C11_C12_B                                                                       0x041f
+#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C13_C14_B                                                                       0x0420
+#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C21_C22_B                                                                       0x0421
+#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C23_C24_B                                                                       0x0422
+#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C31_C32_B                                                                       0x0423
+#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C33_C34_B                                                                       0x0424
+#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX                                                              3
+
+
+// addressBlock: dcn_dc_opp_abm0_dispdec
+// base address: 0x0
+#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0e7a
+#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM0_BL1_PWM_USER_LEVEL                                                                      0x0e7b
+#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM0_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0e7c
+#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0e7d
+#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0e7e
+#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0e7f
+#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM0_BL1_PWM_ABM_CNTL                                                                        0x0e80
+#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0e81
+#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM0_BL1_PWM_GRP2_REG_LOCK                                                                   0x0e82
+#define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM0_DC_ABM1_CNTL                                                                            0x0e83
+#define regABM0_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM0_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0e84
+#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0e85
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0e86
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0e87
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0e88
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0e89
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_THRES_12                                                                    0x0e8a
+#define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_ACE_THRES_34                                                                    0x0e8b
+#define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_ACE_CNTL_MISC                                                                   0x0e8c
+#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0e8e
+#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM0_DC_ABM1_HG_MISC_CTRL                                                                    0x0e8f
+#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0e90
+#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0e91
+#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0e92
+#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM0_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0e93
+#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0e94
+#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0e95
+#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0e96
+#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM0_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0e97
+#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0e98
+#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0e99
+#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0e9a
+#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0e9b
+#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0e9c
+#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0e9d
+#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM0_DC_ABM1_HG_RESULT_1                                                                     0x0e9e
+#define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_2                                                                     0x0e9f
+#define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_3                                                                     0x0ea0
+#define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_4                                                                     0x0ea1
+#define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_5                                                                     0x0ea2
+#define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_6                                                                     0x0ea3
+#define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_7                                                                     0x0ea4
+#define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_8                                                                     0x0ea5
+#define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_9                                                                     0x0ea6
+#define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_10                                                                    0x0ea7
+#define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_11                                                                    0x0ea8
+#define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_12                                                                    0x0ea9
+#define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_13                                                                    0x0eaa
+#define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_14                                                                    0x0eab
+#define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_15                                                                    0x0eac
+#define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_16                                                                    0x0ead
+#define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_17                                                                    0x0eae
+#define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_18                                                                    0x0eaf
+#define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_19                                                                    0x0eb0
+#define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_20                                                                    0x0eb1
+#define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_21                                                                    0x0eb2
+#define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_22                                                                    0x0eb3
+#define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_23                                                                    0x0eb4
+#define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_24                                                                    0x0eb5
+#define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_BL_MASTER_LOCK                                                                  0x0eb6
+#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dcn_dc_opp_abm1_dispdec
+// base address: 0x104
+#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0ebb
+#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM1_BL1_PWM_USER_LEVEL                                                                      0x0ebc
+#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM1_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0ebd
+#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0ebe
+#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0ebf
+#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0ec0
+#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM1_BL1_PWM_ABM_CNTL                                                                        0x0ec1
+#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0ec2
+#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM1_BL1_PWM_GRP2_REG_LOCK                                                                   0x0ec3
+#define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM1_DC_ABM1_CNTL                                                                            0x0ec4
+#define regABM1_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM1_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0ec5
+#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0ec6
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0ec7
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0ec8
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0ec9
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0eca
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_THRES_12                                                                    0x0ecb
+#define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_ACE_THRES_34                                                                    0x0ecc
+#define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_ACE_CNTL_MISC                                                                   0x0ecd
+#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0ecf
+#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM1_DC_ABM1_HG_MISC_CTRL                                                                    0x0ed0
+#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0ed1
+#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0ed2
+#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0ed3
+#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM1_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0ed4
+#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0ed5
+#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0ed6
+#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0ed7
+#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM1_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0ed8
+#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0ed9
+#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0eda
+#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0edb
+#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0edc
+#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0edd
+#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0ede
+#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM1_DC_ABM1_HG_RESULT_1                                                                     0x0edf
+#define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_2                                                                     0x0ee0
+#define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_3                                                                     0x0ee1
+#define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_4                                                                     0x0ee2
+#define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_5                                                                     0x0ee3
+#define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_6                                                                     0x0ee4
+#define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_7                                                                     0x0ee5
+#define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_8                                                                     0x0ee6
+#define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_9                                                                     0x0ee7
+#define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_10                                                                    0x0ee8
+#define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_11                                                                    0x0ee9
+#define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_12                                                                    0x0eea
+#define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_13                                                                    0x0eeb
+#define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_14                                                                    0x0eec
+#define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_15                                                                    0x0eed
+#define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_16                                                                    0x0eee
+#define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_17                                                                    0x0eef
+#define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_18                                                                    0x0ef0
+#define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_19                                                                    0x0ef1
+#define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_20                                                                    0x0ef2
+#define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_21                                                                    0x0ef3
+#define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_22                                                                    0x0ef4
+#define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_23                                                                    0x0ef5
+#define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_24                                                                    0x0ef6
+#define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_BL_MASTER_LOCK                                                                  0x0ef7
+#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dcn_dc_opp_abm2_dispdec
+// base address: 0x208
+#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0efc
+#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM2_BL1_PWM_USER_LEVEL                                                                      0x0efd
+#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM2_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0efe
+#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0eff
+#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f00
+#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f01
+#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM2_BL1_PWM_ABM_CNTL                                                                        0x0f02
+#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f03
+#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM2_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f04
+#define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM2_DC_ABM1_CNTL                                                                            0x0f05
+#define regABM2_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM2_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f06
+#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0f07
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0f08
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0f09
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0f0a
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0f0b
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_THRES_12                                                                    0x0f0c
+#define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_ACE_THRES_34                                                                    0x0f0d
+#define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f0e
+#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f10
+#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM2_DC_ABM1_HG_MISC_CTRL                                                                    0x0f11
+#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f12
+#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f13
+#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f14
+#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM2_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f15
+#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f16
+#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f17
+#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f18
+#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM2_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f19
+#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f1a
+#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f1b
+#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f1c
+#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f1d
+#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f1e
+#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f1f
+#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM2_DC_ABM1_HG_RESULT_1                                                                     0x0f20
+#define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_2                                                                     0x0f21
+#define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_3                                                                     0x0f22
+#define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_4                                                                     0x0f23
+#define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_5                                                                     0x0f24
+#define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_6                                                                     0x0f25
+#define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_7                                                                     0x0f26
+#define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_8                                                                     0x0f27
+#define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_9                                                                     0x0f28
+#define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_10                                                                    0x0f29
+#define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_11                                                                    0x0f2a
+#define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_12                                                                    0x0f2b
+#define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_13                                                                    0x0f2c
+#define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_14                                                                    0x0f2d
+#define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_15                                                                    0x0f2e
+#define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_16                                                                    0x0f2f
+#define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_17                                                                    0x0f30
+#define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_18                                                                    0x0f31
+#define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_19                                                                    0x0f32
+#define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_20                                                                    0x0f33
+#define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_21                                                                    0x0f34
+#define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_22                                                                    0x0f35
+#define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_23                                                                    0x0f36
+#define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_24                                                                    0x0f37
+#define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f38
+#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dcn_dc_opp_abm3_dispdec
+// base address: 0x30c
+#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0f3d
+#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM3_BL1_PWM_USER_LEVEL                                                                      0x0f3e
+#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM3_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0f3f
+#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0f40
+#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f41
+#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f42
+#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM3_BL1_PWM_ABM_CNTL                                                                        0x0f43
+#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f44
+#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM3_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f45
+#define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM3_DC_ABM1_CNTL                                                                            0x0f46
+#define regABM3_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM3_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f47
+#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0f48
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0f49
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0f4a
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0f4b
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0f4c
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_THRES_12                                                                    0x0f4d
+#define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_ACE_THRES_34                                                                    0x0f4e
+#define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f4f
+#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f51
+#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM3_DC_ABM1_HG_MISC_CTRL                                                                    0x0f52
+#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f53
+#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f54
+#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f55
+#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM3_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f56
+#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f57
+#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f58
+#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f59
+#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM3_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f5a
+#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f5b
+#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f5c
+#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f5d
+#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f5e
+#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f5f
+#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f60
+#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM3_DC_ABM1_HG_RESULT_1                                                                     0x0f61
+#define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_2                                                                     0x0f62
+#define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_3                                                                     0x0f63
+#define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_4                                                                     0x0f64
+#define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_5                                                                     0x0f65
+#define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_6                                                                     0x0f66
+#define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_7                                                                     0x0f67
+#define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_8                                                                     0x0f68
+#define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_9                                                                     0x0f69
+#define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_10                                                                    0x0f6a
+#define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_11                                                                    0x0f6b
+#define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_12                                                                    0x0f6c
+#define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_13                                                                    0x0f6d
+#define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_14                                                                    0x0f6e
+#define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_15                                                                    0x0f6f
+#define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_16                                                                    0x0f70
+#define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_17                                                                    0x0f71
+#define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_18                                                                    0x0f72
+#define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_19                                                                    0x0f73
+#define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_20                                                                    0x0f74
+#define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_21                                                                    0x0f75
+#define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_22                                                                    0x0f76
+#define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_23                                                                    0x0f77
+#define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_24                                                                    0x0f78
+#define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f79
+#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dcn_dc_opp_dpg0_dispdec
+// base address: 0x0
+#define regDPG0_DPG_CONTROL                                                                             0x1854
+#define regDPG0_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG0_DPG_RAMP_CONTROL                                                                        0x1855
+#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG0_DPG_DIMENSIONS                                                                          0x1856
+#define regDPG0_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG0_DPG_COLOUR_R_CR                                                                         0x1857
+#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG0_DPG_COLOUR_G_Y                                                                          0x1858
+#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG0_DPG_COLOUR_B_CB                                                                         0x1859
+#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG0_DPG_OFFSET_SEGMENT                                                                      0x185a
+#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG0_DPG_STATUS                                                                              0x185b
+#define regDPG0_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dcn_dc_opp_fmt0_dispdec
+// base address: 0x0
+#define regFMT0_FMT_CLAMP_COMPONENT_R                                                                   0x183c
+#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT0_FMT_CLAMP_COMPONENT_G                                                                   0x183d
+#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT0_FMT_CLAMP_COMPONENT_B                                                                   0x183e
+#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT0_FMT_DYNAMIC_EXP_CNTL                                                                    0x183f
+#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT0_FMT_CONTROL                                                                             0x1840
+#define regFMT0_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT0_FMT_BIT_DEPTH_CONTROL                                                                   0x1841
+#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT0_FMT_DITHER_RAND_R_SEED                                                                  0x1842
+#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT0_FMT_DITHER_RAND_G_SEED                                                                  0x1843
+#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT0_FMT_DITHER_RAND_B_SEED                                                                  0x1844
+#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT0_FMT_CLAMP_CNTL                                                                          0x1845
+#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1846
+#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT0_FMT_MAP420_MEMORY_CONTROL                                                               0x1847
+#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT0_FMT_422_CONTROL                                                                         0x1849
+#define regFMT0_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dcn_dc_opp_oppbuf0_dispdec
+// base address: 0x0
+#define regOPPBUF0_OPPBUF_CONTROL                                                                       0x1884
+#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0                                                               0x1885
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1                                                               0x1886
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF0_OPPBUF_CONTROL1                                                                      0x1889
+#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_opp_opp_pipe0_dispdec
+// base address: 0x0
+#define regOPP_PIPE0_OPP_PIPE_CONTROL                                                                   0x188c
+#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_opp_opp_pipe_crc0_dispdec
+// base address: 0x0
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL                                                           0x1891
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK                                                              0x1892
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0                                                           0x1893
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1                                                           0x1894
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2                                                           0x1895
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dcn_dc_opp_dpg1_dispdec
+// base address: 0x168
+#define regDPG1_DPG_CONTROL                                                                             0x18ae
+#define regDPG1_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG1_DPG_RAMP_CONTROL                                                                        0x18af
+#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG1_DPG_DIMENSIONS                                                                          0x18b0
+#define regDPG1_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG1_DPG_COLOUR_R_CR                                                                         0x18b1
+#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG1_DPG_COLOUR_G_Y                                                                          0x18b2
+#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG1_DPG_COLOUR_B_CB                                                                         0x18b3
+#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG1_DPG_OFFSET_SEGMENT                                                                      0x18b4
+#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG1_DPG_STATUS                                                                              0x18b5
+#define regDPG1_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dcn_dc_opp_fmt1_dispdec
+// base address: 0x168
+#define regFMT1_FMT_CLAMP_COMPONENT_R                                                                   0x1896
+#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT1_FMT_CLAMP_COMPONENT_G                                                                   0x1897
+#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT1_FMT_CLAMP_COMPONENT_B                                                                   0x1898
+#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT1_FMT_DYNAMIC_EXP_CNTL                                                                    0x1899
+#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT1_FMT_CONTROL                                                                             0x189a
+#define regFMT1_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT1_FMT_BIT_DEPTH_CONTROL                                                                   0x189b
+#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT1_FMT_DITHER_RAND_R_SEED                                                                  0x189c
+#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT1_FMT_DITHER_RAND_G_SEED                                                                  0x189d
+#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT1_FMT_DITHER_RAND_B_SEED                                                                  0x189e
+#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT1_FMT_CLAMP_CNTL                                                                          0x189f
+#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18a0
+#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT1_FMT_MAP420_MEMORY_CONTROL                                                               0x18a1
+#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT1_FMT_422_CONTROL                                                                         0x18a3
+#define regFMT1_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dcn_dc_opp_oppbuf1_dispdec
+// base address: 0x168
+#define regOPPBUF1_OPPBUF_CONTROL                                                                       0x18de
+#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0                                                               0x18df
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1                                                               0x18e0
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF1_OPPBUF_CONTROL1                                                                      0x18e3
+#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_opp_opp_pipe1_dispdec
+// base address: 0x168
+#define regOPP_PIPE1_OPP_PIPE_CONTROL                                                                   0x18e6
+#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_opp_opp_pipe_crc1_dispdec
+// base address: 0x168
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL                                                           0x18eb
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK                                                              0x18ec
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0                                                           0x18ed
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1                                                           0x18ee
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2                                                           0x18ef
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dcn_dc_opp_dpg2_dispdec
+// base address: 0x2d0
+#define regDPG2_DPG_CONTROL                                                                             0x1908
+#define regDPG2_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG2_DPG_RAMP_CONTROL                                                                        0x1909
+#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG2_DPG_DIMENSIONS                                                                          0x190a
+#define regDPG2_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG2_DPG_COLOUR_R_CR                                                                         0x190b
+#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG2_DPG_COLOUR_G_Y                                                                          0x190c
+#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG2_DPG_COLOUR_B_CB                                                                         0x190d
+#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG2_DPG_OFFSET_SEGMENT                                                                      0x190e
+#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG2_DPG_STATUS                                                                              0x190f
+#define regDPG2_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dcn_dc_opp_fmt2_dispdec
+// base address: 0x2d0
+#define regFMT2_FMT_CLAMP_COMPONENT_R                                                                   0x18f0
+#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT2_FMT_CLAMP_COMPONENT_G                                                                   0x18f1
+#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT2_FMT_CLAMP_COMPONENT_B                                                                   0x18f2
+#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT2_FMT_DYNAMIC_EXP_CNTL                                                                    0x18f3
+#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT2_FMT_CONTROL                                                                             0x18f4
+#define regFMT2_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT2_FMT_BIT_DEPTH_CONTROL                                                                   0x18f5
+#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT2_FMT_DITHER_RAND_R_SEED                                                                  0x18f6
+#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT2_FMT_DITHER_RAND_G_SEED                                                                  0x18f7
+#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT2_FMT_DITHER_RAND_B_SEED                                                                  0x18f8
+#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT2_FMT_CLAMP_CNTL                                                                          0x18f9
+#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18fa
+#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT2_FMT_MAP420_MEMORY_CONTROL                                                               0x18fb
+#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT2_FMT_422_CONTROL                                                                         0x18fd
+#define regFMT2_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dcn_dc_opp_oppbuf2_dispdec
+// base address: 0x2d0
+#define regOPPBUF2_OPPBUF_CONTROL                                                                       0x1938
+#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0                                                               0x1939
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1                                                               0x193a
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF2_OPPBUF_CONTROL1                                                                      0x193d
+#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_opp_opp_pipe2_dispdec
+// base address: 0x2d0
+#define regOPP_PIPE2_OPP_PIPE_CONTROL                                                                   0x1940
+#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_opp_opp_pipe_crc2_dispdec
+// base address: 0x2d0
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL                                                           0x1945
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK                                                              0x1946
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0                                                           0x1947
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1                                                           0x1948
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2                                                           0x1949
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dcn_dc_opp_dpg3_dispdec
+// base address: 0x438
+#define regDPG3_DPG_CONTROL                                                                             0x1962
+#define regDPG3_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG3_DPG_RAMP_CONTROL                                                                        0x1963
+#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG3_DPG_DIMENSIONS                                                                          0x1964
+#define regDPG3_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG3_DPG_COLOUR_R_CR                                                                         0x1965
+#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG3_DPG_COLOUR_G_Y                                                                          0x1966
+#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG3_DPG_COLOUR_B_CB                                                                         0x1967
+#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG3_DPG_OFFSET_SEGMENT                                                                      0x1968
+#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG3_DPG_STATUS                                                                              0x1969
+#define regDPG3_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dcn_dc_opp_fmt3_dispdec
+// base address: 0x438
+#define regFMT3_FMT_CLAMP_COMPONENT_R                                                                   0x194a
+#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT3_FMT_CLAMP_COMPONENT_G                                                                   0x194b
+#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT3_FMT_CLAMP_COMPONENT_B                                                                   0x194c
+#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT3_FMT_DYNAMIC_EXP_CNTL                                                                    0x194d
+#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT3_FMT_CONTROL                                                                             0x194e
+#define regFMT3_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT3_FMT_BIT_DEPTH_CONTROL                                                                   0x194f
+#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT3_FMT_DITHER_RAND_R_SEED                                                                  0x1950
+#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT3_FMT_DITHER_RAND_G_SEED                                                                  0x1951
+#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT3_FMT_DITHER_RAND_B_SEED                                                                  0x1952
+#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT3_FMT_CLAMP_CNTL                                                                          0x1953
+#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1954
+#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT3_FMT_MAP420_MEMORY_CONTROL                                                               0x1955
+#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT3_FMT_422_CONTROL                                                                         0x1957
+#define regFMT3_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dcn_dc_opp_oppbuf3_dispdec
+// base address: 0x438
+#define regOPPBUF3_OPPBUF_CONTROL                                                                       0x1992
+#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0                                                               0x1993
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1                                                               0x1994
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF3_OPPBUF_CONTROL1                                                                      0x1997
+#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_opp_opp_pipe3_dispdec
+// base address: 0x438
+#define regOPP_PIPE3_OPP_PIPE_CONTROL                                                                   0x199a
+#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_opp_opp_pipe_crc3_dispdec
+// base address: 0x438
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL                                                           0x199f
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK                                                              0x19a0
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0                                                           0x19a1
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1                                                           0x19a2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2                                                           0x19a3
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dcn_dc_opp_dscrm0_dispdec
+// base address: 0x0
+#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a64
+#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_opp_dscrm1_dispdec
+// base address: 0x4
+#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a65
+#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_opp_dscrm2_dispdec
+// base address: 0x8
+#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a66
+#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_opp_dscrm3_dispdec
+// base address: 0xc
+#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a67
+#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_opp_opp_top_dispdec
+// base address: 0x0
+#define regOPP_TOP_CLK_CONTROL                                                                          0x1a5e
+#define regOPP_TOP_CLK_CONTROL_BASE_IDX                                                                 2
+#define regOPP_ABM_CONTROL                                                                              0x1a60
+#define regOPP_ABM_CONTROL_BASE_IDX                                                                     2
+
+
+// addressBlock: dcn_dc_optc_odm0_dispdec
+// base address: 0x0
+#define regODM0_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aca
+#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM0_OPTC_DATA_SOURCE_SELECT                                                                 0x1acb
+#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM0_OPTC_DATA_FORMAT_CONTROL                                                                0x1acc
+#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM0_OPTC_BYTES_PER_PIXEL                                                                    0x1acd
+#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM0_OPTC_WIDTH_CONTROL                                                                      0x1ace
+#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM0_OPTC_INPUT_CLOCK_CONTROL                                                                0x1acf
+#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM0_OPTC_MEMORY_CONFIG                                                                      0x1ad0
+#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM0_OPTC_INPUT_SPARE_REGISTER                                                               0x1ad1
+#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_optc_odm1_dispdec
+// base address: 0x40
+#define regODM1_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1ada
+#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM1_OPTC_DATA_SOURCE_SELECT                                                                 0x1adb
+#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM1_OPTC_DATA_FORMAT_CONTROL                                                                0x1adc
+#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM1_OPTC_BYTES_PER_PIXEL                                                                    0x1add
+#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM1_OPTC_WIDTH_CONTROL                                                                      0x1ade
+#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM1_OPTC_INPUT_CLOCK_CONTROL                                                                0x1adf
+#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM1_OPTC_MEMORY_CONFIG                                                                      0x1ae0
+#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM1_OPTC_INPUT_SPARE_REGISTER                                                               0x1ae1
+#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_optc_odm2_dispdec
+// base address: 0x80
+#define regODM2_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aea
+#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM2_OPTC_DATA_SOURCE_SELECT                                                                 0x1aeb
+#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM2_OPTC_DATA_FORMAT_CONTROL                                                                0x1aec
+#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM2_OPTC_BYTES_PER_PIXEL                                                                    0x1aed
+#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM2_OPTC_WIDTH_CONTROL                                                                      0x1aee
+#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM2_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aef
+#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM2_OPTC_MEMORY_CONFIG                                                                      0x1af0
+#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM2_OPTC_INPUT_SPARE_REGISTER                                                               0x1af1
+#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_optc_odm3_dispdec
+// base address: 0xc0
+#define regODM3_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1afa
+#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM3_OPTC_DATA_SOURCE_SELECT                                                                 0x1afb
+#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM3_OPTC_DATA_FORMAT_CONTROL                                                                0x1afc
+#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM3_OPTC_BYTES_PER_PIXEL                                                                    0x1afd
+#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM3_OPTC_WIDTH_CONTROL                                                                      0x1afe
+#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM3_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aff
+#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM3_OPTC_MEMORY_CONFIG                                                                      0x1b00
+#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM3_OPTC_INPUT_SPARE_REGISTER                                                               0x1b01
+#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_optc_otg0_dispdec
+// base address: 0x0
+#define regOTG0_OTG_H_TOTAL                                                                             0x1b2a
+#define regOTG0_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG0_OTG_H_BLANK_START_END                                                                   0x1b2b
+#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG0_OTG_H_SYNC_A                                                                            0x1b2c
+#define regOTG0_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG0_OTG_H_SYNC_A_CNTL                                                                       0x1b2d
+#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG0_OTG_H_TIMING_CNTL                                                                       0x1b2e
+#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG0_OTG_V_TOTAL                                                                             0x1b2f
+#define regOTG0_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG0_OTG_V_TOTAL_MIN                                                                         0x1b30
+#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG0_OTG_V_TOTAL_MAX                                                                         0x1b31
+#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG0_OTG_V_TOTAL_MID                                                                         0x1b32
+#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG0_OTG_V_TOTAL_CONTROL                                                                     0x1b33
+#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG0_OTG_V_TOTAL_INT_STATUS                                                                  0x1b34
+#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG0_OTG_VSYNC_NOM_INT_STATUS                                                                0x1b35
+#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG0_OTG_V_BLANK_START_END                                                                   0x1b36
+#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG0_OTG_V_SYNC_A                                                                            0x1b37
+#define regOTG0_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG0_OTG_V_SYNC_A_CNTL                                                                       0x1b38
+#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG0_OTG_TRIGA_CNTL                                                                          0x1b39
+#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG0_OTG_TRIGA_MANUAL_TRIG                                                                   0x1b3a
+#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG0_OTG_TRIGB_CNTL                                                                          0x1b3b
+#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG0_OTG_TRIGB_MANUAL_TRIG                                                                   0x1b3c
+#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1b3d
+#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG0_OTG_FLOW_CONTROL                                                                        0x1b3e
+#define regOTG0_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1b3f
+#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG0_OTG_CONTROL                                                                             0x1b41
+#define regOTG0_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG0_OTG_INTERLACE_CONTROL                                                                   0x1b44
+#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG0_OTG_INTERLACE_STATUS                                                                    0x1b45
+#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG0_OTG_PIXEL_DATA_READBACK0                                                                0x1b47
+#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG0_OTG_PIXEL_DATA_READBACK1                                                                0x1b48
+#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG0_OTG_STATUS                                                                              0x1b49
+#define regOTG0_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG0_OTG_STATUS_POSITION                                                                     0x1b4a
+#define regOTG0_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG0_OTG_NOM_VERT_POSITION                                                                   0x1b4b
+#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG0_OTG_STATUS_FRAME_COUNT                                                                  0x1b4c
+#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG0_OTG_STATUS_VF_COUNT                                                                     0x1b4d
+#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG0_OTG_STATUS_HV_COUNT                                                                     0x1b4e
+#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG0_OTG_COUNT_CONTROL                                                                       0x1b4f
+#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG0_OTG_COUNT_RESET                                                                         0x1b50
+#define regOTG0_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1b51
+#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG0_OTG_VERT_SYNC_CONTROL                                                                   0x1b52
+#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG0_OTG_STEREO_STATUS                                                                       0x1b53
+#define regOTG0_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG0_OTG_STEREO_CONTROL                                                                      0x1b54
+#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG0_OTG_SNAPSHOT_STATUS                                                                     0x1b55
+#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG0_OTG_SNAPSHOT_CONTROL                                                                    0x1b56
+#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG0_OTG_SNAPSHOT_POSITION                                                                   0x1b57
+#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG0_OTG_SNAPSHOT_FRAME                                                                      0x1b58
+#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG0_OTG_INTERRUPT_CONTROL                                                                   0x1b59
+#define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG0_OTG_UPDATE_LOCK                                                                         0x1b5a
+#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1b5b
+#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG0_OTG_MASTER_EN                                                                           0x1b5c
+#define regOTG0_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1b62
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1b63
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1b64
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1b65
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1b66
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1b67
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG0_OTG_CRC_CNTL                                                                            0x1b68
+#define regOTG0_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1b69
+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1b6a
+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1b6b
+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1b6c
+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_DATA_RG                                                                        0x1b6d
+#define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC0_DATA_B                                                                         0x1b6e
+#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1b6f
+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1b70
+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1b71
+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1b72
+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_DATA_RG                                                                        0x1b73
+#define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC1_DATA_B                                                                         0x1b74
+#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC2_DATA_RG                                                                        0x1b75
+#define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC2_DATA_B                                                                         0x1b76
+#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC3_DATA_RG                                                                        0x1b77
+#define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC3_DATA_B                                                                         0x1b78
+#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1b79
+#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1b7a
+#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG0_OTG_STATIC_SCREEN_CONTROL                                                               0x1b81
+#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG0_OTG_3D_STRUCTURE_CONTROL                                                                0x1b82
+#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG0_OTG_GSL_VSYNC_GAP                                                                       0x1b83
+#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG0_OTG_MASTER_UPDATE_MODE                                                                  0x1b84
+#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG0_OTG_CLOCK_CONTROL                                                                       0x1b85
+#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG0_OTG_VSTARTUP_PARAM                                                                      0x1b86
+#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG0_OTG_VUPDATE_PARAM                                                                       0x1b87
+#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG0_OTG_VREADY_PARAM                                                                        0x1b88
+#define regOTG0_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG0_OTG_GLOBAL_SYNC_STATUS                                                                  0x1b89
+#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG0_OTG_MASTER_UPDATE_LOCK                                                                  0x1b8a
+#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG0_OTG_GSL_CONTROL                                                                         0x1b8b
+#define regOTG0_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG0_OTG_GSL_WINDOW_X                                                                        0x1b8c
+#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG0_OTG_GSL_WINDOW_Y                                                                        0x1b8d
+#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG0_OTG_VUPDATE_KEEPOUT                                                                     0x1b8e
+#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL0                                                                     0x1b8f
+#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL1                                                                     0x1b90
+#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL2                                                                     0x1b91
+#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL3                                                                     0x1b92
+#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL4                                                                     0x1b93
+#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG0_OTG_TRIG_MANUAL_CONTROL                                                                 0x1b94
+#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG0_OTG_MANUAL_FLOW_CONTROL                                                                 0x1b95
+#define regOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG0_OTG_DRR_TIMING_INT_STATUS                                                               0x1b96
+#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1b97
+#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG0_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1b98
+#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG0_OTG_DRR_TRIGGER_WINDOW                                                                  0x1b99
+#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG0_OTG_DRR_CONTROL                                                                         0x1b9a
+#define regOTG0_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG0_OTG_M_CONST_DTO0                                                                        0x1b9b
+#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG0_OTG_M_CONST_DTO1                                                                        0x1b9c
+#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG0_OTG_REQUEST_CONTROL                                                                     0x1b9d
+#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG0_OTG_DSC_START_POSITION                                                                  0x1b9e
+#define regOTG0_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG0_OTG_PIPE_UPDATE_STATUS                                                                  0x1b9f
+#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG0_OTG_SPARE_REGISTER                                                                      0x1ba1
+#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_optc_otg1_dispdec
+// base address: 0x200
+#define regOTG1_OTG_H_TOTAL                                                                             0x1baa
+#define regOTG1_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG1_OTG_H_BLANK_START_END                                                                   0x1bab
+#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG1_OTG_H_SYNC_A                                                                            0x1bac
+#define regOTG1_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG1_OTG_H_SYNC_A_CNTL                                                                       0x1bad
+#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG1_OTG_H_TIMING_CNTL                                                                       0x1bae
+#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG1_OTG_V_TOTAL                                                                             0x1baf
+#define regOTG1_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG1_OTG_V_TOTAL_MIN                                                                         0x1bb0
+#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG1_OTG_V_TOTAL_MAX                                                                         0x1bb1
+#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG1_OTG_V_TOTAL_MID                                                                         0x1bb2
+#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG1_OTG_V_TOTAL_CONTROL                                                                     0x1bb3
+#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG1_OTG_V_TOTAL_INT_STATUS                                                                  0x1bb4
+#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG1_OTG_VSYNC_NOM_INT_STATUS                                                                0x1bb5
+#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG1_OTG_V_BLANK_START_END                                                                   0x1bb6
+#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG1_OTG_V_SYNC_A                                                                            0x1bb7
+#define regOTG1_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG1_OTG_V_SYNC_A_CNTL                                                                       0x1bb8
+#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG1_OTG_TRIGA_CNTL                                                                          0x1bb9
+#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG1_OTG_TRIGA_MANUAL_TRIG                                                                   0x1bba
+#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG1_OTG_TRIGB_CNTL                                                                          0x1bbb
+#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG1_OTG_TRIGB_MANUAL_TRIG                                                                   0x1bbc
+#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1bbd
+#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG1_OTG_FLOW_CONTROL                                                                        0x1bbe
+#define regOTG1_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1bbf
+#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG1_OTG_CONTROL                                                                             0x1bc1
+#define regOTG1_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG1_OTG_INTERLACE_CONTROL                                                                   0x1bc4
+#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG1_OTG_INTERLACE_STATUS                                                                    0x1bc5
+#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG1_OTG_PIXEL_DATA_READBACK0                                                                0x1bc7
+#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG1_OTG_PIXEL_DATA_READBACK1                                                                0x1bc8
+#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG1_OTG_STATUS                                                                              0x1bc9
+#define regOTG1_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG1_OTG_STATUS_POSITION                                                                     0x1bca
+#define regOTG1_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG1_OTG_NOM_VERT_POSITION                                                                   0x1bcb
+#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG1_OTG_STATUS_FRAME_COUNT                                                                  0x1bcc
+#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG1_OTG_STATUS_VF_COUNT                                                                     0x1bcd
+#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG1_OTG_STATUS_HV_COUNT                                                                     0x1bce
+#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG1_OTG_COUNT_CONTROL                                                                       0x1bcf
+#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG1_OTG_COUNT_RESET                                                                         0x1bd0
+#define regOTG1_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1bd1
+#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG1_OTG_VERT_SYNC_CONTROL                                                                   0x1bd2
+#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG1_OTG_STEREO_STATUS                                                                       0x1bd3
+#define regOTG1_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG1_OTG_STEREO_CONTROL                                                                      0x1bd4
+#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG1_OTG_SNAPSHOT_STATUS                                                                     0x1bd5
+#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG1_OTG_SNAPSHOT_CONTROL                                                                    0x1bd6
+#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG1_OTG_SNAPSHOT_POSITION                                                                   0x1bd7
+#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG1_OTG_SNAPSHOT_FRAME                                                                      0x1bd8
+#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG1_OTG_INTERRUPT_CONTROL                                                                   0x1bd9
+#define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG1_OTG_UPDATE_LOCK                                                                         0x1bda
+#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1bdb
+#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG1_OTG_MASTER_EN                                                                           0x1bdc
+#define regOTG1_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1be2
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1be3
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1be4
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1be5
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1be6
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1be7
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG1_OTG_CRC_CNTL                                                                            0x1be8
+#define regOTG1_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1be9
+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1bea
+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1beb
+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1bec
+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_DATA_RG                                                                        0x1bed
+#define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC0_DATA_B                                                                         0x1bee
+#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1bef
+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1bf0
+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1bf1
+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1bf2
+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_DATA_RG                                                                        0x1bf3
+#define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC1_DATA_B                                                                         0x1bf4
+#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC2_DATA_RG                                                                        0x1bf5
+#define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC2_DATA_B                                                                         0x1bf6
+#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC3_DATA_RG                                                                        0x1bf7
+#define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC3_DATA_B                                                                         0x1bf8
+#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1bf9
+#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1bfa
+#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG1_OTG_STATIC_SCREEN_CONTROL                                                               0x1c01
+#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG1_OTG_3D_STRUCTURE_CONTROL                                                                0x1c02
+#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG1_OTG_GSL_VSYNC_GAP                                                                       0x1c03
+#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG1_OTG_MASTER_UPDATE_MODE                                                                  0x1c04
+#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG1_OTG_CLOCK_CONTROL                                                                       0x1c05
+#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG1_OTG_VSTARTUP_PARAM                                                                      0x1c06
+#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG1_OTG_VUPDATE_PARAM                                                                       0x1c07
+#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG1_OTG_VREADY_PARAM                                                                        0x1c08
+#define regOTG1_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG1_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c09
+#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG1_OTG_MASTER_UPDATE_LOCK                                                                  0x1c0a
+#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG1_OTG_GSL_CONTROL                                                                         0x1c0b
+#define regOTG1_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG1_OTG_GSL_WINDOW_X                                                                        0x1c0c
+#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG1_OTG_GSL_WINDOW_Y                                                                        0x1c0d
+#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG1_OTG_VUPDATE_KEEPOUT                                                                     0x1c0e
+#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL0                                                                     0x1c0f
+#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL1                                                                     0x1c10
+#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL2                                                                     0x1c11
+#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL3                                                                     0x1c12
+#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL4                                                                     0x1c13
+#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG1_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c14
+#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG1_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c15
+#define regOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG1_OTG_DRR_TIMING_INT_STATUS                                                               0x1c16
+#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c17
+#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG1_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c18
+#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG1_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c19
+#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG1_OTG_DRR_CONTROL                                                                         0x1c1a
+#define regOTG1_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG1_OTG_M_CONST_DTO0                                                                        0x1c1b
+#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG1_OTG_M_CONST_DTO1                                                                        0x1c1c
+#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG1_OTG_REQUEST_CONTROL                                                                     0x1c1d
+#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG1_OTG_DSC_START_POSITION                                                                  0x1c1e
+#define regOTG1_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG1_OTG_PIPE_UPDATE_STATUS                                                                  0x1c1f
+#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG1_OTG_SPARE_REGISTER                                                                      0x1c21
+#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_optc_otg2_dispdec
+// base address: 0x400
+#define regOTG2_OTG_H_TOTAL                                                                             0x1c2a
+#define regOTG2_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG2_OTG_H_BLANK_START_END                                                                   0x1c2b
+#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG2_OTG_H_SYNC_A                                                                            0x1c2c
+#define regOTG2_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG2_OTG_H_SYNC_A_CNTL                                                                       0x1c2d
+#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG2_OTG_H_TIMING_CNTL                                                                       0x1c2e
+#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG2_OTG_V_TOTAL                                                                             0x1c2f
+#define regOTG2_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG2_OTG_V_TOTAL_MIN                                                                         0x1c30
+#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG2_OTG_V_TOTAL_MAX                                                                         0x1c31
+#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG2_OTG_V_TOTAL_MID                                                                         0x1c32
+#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG2_OTG_V_TOTAL_CONTROL                                                                     0x1c33
+#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG2_OTG_V_TOTAL_INT_STATUS                                                                  0x1c34
+#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG2_OTG_VSYNC_NOM_INT_STATUS                                                                0x1c35
+#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG2_OTG_V_BLANK_START_END                                                                   0x1c36
+#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG2_OTG_V_SYNC_A                                                                            0x1c37
+#define regOTG2_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG2_OTG_V_SYNC_A_CNTL                                                                       0x1c38
+#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG2_OTG_TRIGA_CNTL                                                                          0x1c39
+#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG2_OTG_TRIGA_MANUAL_TRIG                                                                   0x1c3a
+#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG2_OTG_TRIGB_CNTL                                                                          0x1c3b
+#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG2_OTG_TRIGB_MANUAL_TRIG                                                                   0x1c3c
+#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1c3d
+#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG2_OTG_FLOW_CONTROL                                                                        0x1c3e
+#define regOTG2_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1c3f
+#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG2_OTG_CONTROL                                                                             0x1c41
+#define regOTG2_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG2_OTG_INTERLACE_CONTROL                                                                   0x1c44
+#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG2_OTG_INTERLACE_STATUS                                                                    0x1c45
+#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG2_OTG_PIXEL_DATA_READBACK0                                                                0x1c47
+#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG2_OTG_PIXEL_DATA_READBACK1                                                                0x1c48
+#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG2_OTG_STATUS                                                                              0x1c49
+#define regOTG2_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG2_OTG_STATUS_POSITION                                                                     0x1c4a
+#define regOTG2_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG2_OTG_NOM_VERT_POSITION                                                                   0x1c4b
+#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG2_OTG_STATUS_FRAME_COUNT                                                                  0x1c4c
+#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG2_OTG_STATUS_VF_COUNT                                                                     0x1c4d
+#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG2_OTG_STATUS_HV_COUNT                                                                     0x1c4e
+#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG2_OTG_COUNT_CONTROL                                                                       0x1c4f
+#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG2_OTG_COUNT_RESET                                                                         0x1c50
+#define regOTG2_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1c51
+#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG2_OTG_VERT_SYNC_CONTROL                                                                   0x1c52
+#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG2_OTG_STEREO_STATUS                                                                       0x1c53
+#define regOTG2_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG2_OTG_STEREO_CONTROL                                                                      0x1c54
+#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG2_OTG_SNAPSHOT_STATUS                                                                     0x1c55
+#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG2_OTG_SNAPSHOT_CONTROL                                                                    0x1c56
+#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG2_OTG_SNAPSHOT_POSITION                                                                   0x1c57
+#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG2_OTG_SNAPSHOT_FRAME                                                                      0x1c58
+#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG2_OTG_INTERRUPT_CONTROL                                                                   0x1c59
+#define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG2_OTG_UPDATE_LOCK                                                                         0x1c5a
+#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1c5b
+#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG2_OTG_MASTER_EN                                                                           0x1c5c
+#define regOTG2_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1c62
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1c63
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1c64
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1c65
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1c66
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1c67
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG2_OTG_CRC_CNTL                                                                            0x1c68
+#define regOTG2_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1c69
+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1c6a
+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1c6b
+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1c6c
+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_DATA_RG                                                                        0x1c6d
+#define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC0_DATA_B                                                                         0x1c6e
+#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1c6f
+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1c70
+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1c71
+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1c72
+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_DATA_RG                                                                        0x1c73
+#define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC1_DATA_B                                                                         0x1c74
+#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC2_DATA_RG                                                                        0x1c75
+#define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC2_DATA_B                                                                         0x1c76
+#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC3_DATA_RG                                                                        0x1c77
+#define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC3_DATA_B                                                                         0x1c78
+#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1c79
+#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1c7a
+#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG2_OTG_STATIC_SCREEN_CONTROL                                                               0x1c81
+#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG2_OTG_3D_STRUCTURE_CONTROL                                                                0x1c82
+#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG2_OTG_GSL_VSYNC_GAP                                                                       0x1c83
+#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG2_OTG_MASTER_UPDATE_MODE                                                                  0x1c84
+#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG2_OTG_CLOCK_CONTROL                                                                       0x1c85
+#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG2_OTG_VSTARTUP_PARAM                                                                      0x1c86
+#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG2_OTG_VUPDATE_PARAM                                                                       0x1c87
+#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG2_OTG_VREADY_PARAM                                                                        0x1c88
+#define regOTG2_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG2_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c89
+#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG2_OTG_MASTER_UPDATE_LOCK                                                                  0x1c8a
+#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG2_OTG_GSL_CONTROL                                                                         0x1c8b
+#define regOTG2_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG2_OTG_GSL_WINDOW_X                                                                        0x1c8c
+#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG2_OTG_GSL_WINDOW_Y                                                                        0x1c8d
+#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG2_OTG_VUPDATE_KEEPOUT                                                                     0x1c8e
+#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL0                                                                     0x1c8f
+#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL1                                                                     0x1c90
+#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL2                                                                     0x1c91
+#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL3                                                                     0x1c92
+#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL4                                                                     0x1c93
+#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG2_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c94
+#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG2_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c95
+#define regOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG2_OTG_DRR_TIMING_INT_STATUS                                                               0x1c96
+#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c97
+#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG2_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c98
+#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG2_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c99
+#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG2_OTG_DRR_CONTROL                                                                         0x1c9a
+#define regOTG2_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG2_OTG_M_CONST_DTO0                                                                        0x1c9b
+#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG2_OTG_M_CONST_DTO1                                                                        0x1c9c
+#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG2_OTG_REQUEST_CONTROL                                                                     0x1c9d
+#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG2_OTG_DSC_START_POSITION                                                                  0x1c9e
+#define regOTG2_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG2_OTG_PIPE_UPDATE_STATUS                                                                  0x1c9f
+#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG2_OTG_SPARE_REGISTER                                                                      0x1ca1
+#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_optc_otg3_dispdec
+// base address: 0x600
+#define regOTG3_OTG_H_TOTAL                                                                             0x1caa
+#define regOTG3_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG3_OTG_H_BLANK_START_END                                                                   0x1cab
+#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG3_OTG_H_SYNC_A                                                                            0x1cac
+#define regOTG3_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG3_OTG_H_SYNC_A_CNTL                                                                       0x1cad
+#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG3_OTG_H_TIMING_CNTL                                                                       0x1cae
+#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG3_OTG_V_TOTAL                                                                             0x1caf
+#define regOTG3_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG3_OTG_V_TOTAL_MIN                                                                         0x1cb0
+#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG3_OTG_V_TOTAL_MAX                                                                         0x1cb1
+#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG3_OTG_V_TOTAL_MID                                                                         0x1cb2
+#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG3_OTG_V_TOTAL_CONTROL                                                                     0x1cb3
+#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG3_OTG_V_TOTAL_INT_STATUS                                                                  0x1cb4
+#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG3_OTG_VSYNC_NOM_INT_STATUS                                                                0x1cb5
+#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG3_OTG_V_BLANK_START_END                                                                   0x1cb6
+#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG3_OTG_V_SYNC_A                                                                            0x1cb7
+#define regOTG3_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG3_OTG_V_SYNC_A_CNTL                                                                       0x1cb8
+#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG3_OTG_TRIGA_CNTL                                                                          0x1cb9
+#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG3_OTG_TRIGA_MANUAL_TRIG                                                                   0x1cba
+#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG3_OTG_TRIGB_CNTL                                                                          0x1cbb
+#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG3_OTG_TRIGB_MANUAL_TRIG                                                                   0x1cbc
+#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1cbd
+#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG3_OTG_FLOW_CONTROL                                                                        0x1cbe
+#define regOTG3_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1cbf
+#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG3_OTG_CONTROL                                                                             0x1cc1
+#define regOTG3_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG3_OTG_INTERLACE_CONTROL                                                                   0x1cc4
+#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG3_OTG_INTERLACE_STATUS                                                                    0x1cc5
+#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG3_OTG_PIXEL_DATA_READBACK0                                                                0x1cc7
+#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG3_OTG_PIXEL_DATA_READBACK1                                                                0x1cc8
+#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG3_OTG_STATUS                                                                              0x1cc9
+#define regOTG3_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG3_OTG_STATUS_POSITION                                                                     0x1cca
+#define regOTG3_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG3_OTG_NOM_VERT_POSITION                                                                   0x1ccb
+#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG3_OTG_STATUS_FRAME_COUNT                                                                  0x1ccc
+#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG3_OTG_STATUS_VF_COUNT                                                                     0x1ccd
+#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG3_OTG_STATUS_HV_COUNT                                                                     0x1cce
+#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG3_OTG_COUNT_CONTROL                                                                       0x1ccf
+#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG3_OTG_COUNT_RESET                                                                         0x1cd0
+#define regOTG3_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1cd1
+#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG3_OTG_VERT_SYNC_CONTROL                                                                   0x1cd2
+#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG3_OTG_STEREO_STATUS                                                                       0x1cd3
+#define regOTG3_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG3_OTG_STEREO_CONTROL                                                                      0x1cd4
+#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG3_OTG_SNAPSHOT_STATUS                                                                     0x1cd5
+#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG3_OTG_SNAPSHOT_CONTROL                                                                    0x1cd6
+#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG3_OTG_SNAPSHOT_POSITION                                                                   0x1cd7
+#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG3_OTG_SNAPSHOT_FRAME                                                                      0x1cd8
+#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG3_OTG_INTERRUPT_CONTROL                                                                   0x1cd9
+#define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG3_OTG_UPDATE_LOCK                                                                         0x1cda
+#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1cdb
+#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG3_OTG_MASTER_EN                                                                           0x1cdc
+#define regOTG3_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1ce2
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1ce3
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1ce4
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1ce5
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1ce6
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1ce7
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG3_OTG_CRC_CNTL                                                                            0x1ce8
+#define regOTG3_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1ce9
+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1cea
+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1ceb
+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1cec
+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_DATA_RG                                                                        0x1ced
+#define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC0_DATA_B                                                                         0x1cee
+#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1cef
+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1cf0
+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1cf1
+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1cf2
+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_DATA_RG                                                                        0x1cf3
+#define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC1_DATA_B                                                                         0x1cf4
+#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC2_DATA_RG                                                                        0x1cf5
+#define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC2_DATA_B                                                                         0x1cf6
+#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC3_DATA_RG                                                                        0x1cf7
+#define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC3_DATA_B                                                                         0x1cf8
+#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1cf9
+#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1cfa
+#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG3_OTG_STATIC_SCREEN_CONTROL                                                               0x1d01
+#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG3_OTG_3D_STRUCTURE_CONTROL                                                                0x1d02
+#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG3_OTG_GSL_VSYNC_GAP                                                                       0x1d03
+#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG3_OTG_MASTER_UPDATE_MODE                                                                  0x1d04
+#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG3_OTG_CLOCK_CONTROL                                                                       0x1d05
+#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG3_OTG_VSTARTUP_PARAM                                                                      0x1d06
+#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG3_OTG_VUPDATE_PARAM                                                                       0x1d07
+#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG3_OTG_VREADY_PARAM                                                                        0x1d08
+#define regOTG3_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG3_OTG_GLOBAL_SYNC_STATUS                                                                  0x1d09
+#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG3_OTG_MASTER_UPDATE_LOCK                                                                  0x1d0a
+#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG3_OTG_GSL_CONTROL                                                                         0x1d0b
+#define regOTG3_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG3_OTG_GSL_WINDOW_X                                                                        0x1d0c
+#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG3_OTG_GSL_WINDOW_Y                                                                        0x1d0d
+#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG3_OTG_VUPDATE_KEEPOUT                                                                     0x1d0e
+#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL0                                                                     0x1d0f
+#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL1                                                                     0x1d10
+#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL2                                                                     0x1d11
+#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL3                                                                     0x1d12
+#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL4                                                                     0x1d13
+#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG3_OTG_TRIG_MANUAL_CONTROL                                                                 0x1d14
+#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG3_OTG_MANUAL_FLOW_CONTROL                                                                 0x1d15
+#define regOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG3_OTG_DRR_TIMING_INT_STATUS                                                               0x1d16
+#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1d17
+#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG3_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1d18
+#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG3_OTG_DRR_TRIGGER_WINDOW                                                                  0x1d19
+#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG3_OTG_DRR_CONTROL                                                                         0x1d1a
+#define regOTG3_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG3_OTG_M_CONST_DTO0                                                                        0x1d1b
+#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG3_OTG_M_CONST_DTO1                                                                        0x1d1c
+#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG3_OTG_REQUEST_CONTROL                                                                     0x1d1d
+#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG3_OTG_DSC_START_POSITION                                                                  0x1d1e
+#define regOTG3_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG3_OTG_PIPE_UPDATE_STATUS                                                                  0x1d1f
+#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG3_OTG_SPARE_REGISTER                                                                      0x1d21
+#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_optc_optc_misc_dispdec
+// base address: 0x0
+#define regGSL_SOURCE_SELECT                                                                            0x1e2b
+#define regGSL_SOURCE_SELECT_BASE_IDX                                                                   2
+#define regOPTC_CLOCK_CONTROL                                                                           0x1e2c
+#define regOPTC_CLOCK_CONTROL_BASE_IDX                                                                  2
+#define regODM_MEM_PWR_CTRL                                                                             0x1e2d
+#define regODM_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define regODM_MEM_PWR_CTRL3                                                                            0x1e2f
+#define regODM_MEM_PWR_CTRL3_BASE_IDX                                                                   2
+#define regODM_MEM_PWR_STATUS                                                                           0x1e30
+#define regODM_MEM_PWR_STATUS_BASE_IDX                                                                  2
+#define regOPTC_MISC_SPARE_REGISTER                                                                     0x1e31
+#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX                                                            2
+
+
+// addressBlock: dcn_dc_dio_hpd0_dispdec
+// base address: 0x0
+#define regHPD0_DC_HPD_INT_STATUS                                                                       0x1f14
+#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD0_DC_HPD_INT_CONTROL                                                                      0x1f15
+#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD0_DC_HPD_CONTROL                                                                          0x1f16
+#define regHPD0_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD0_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f17
+#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f18
+#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dcn_dc_dio_hpd1_dispdec
+// base address: 0x20
+#define regHPD1_DC_HPD_INT_STATUS                                                                       0x1f1c
+#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD1_DC_HPD_INT_CONTROL                                                                      0x1f1d
+#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD1_DC_HPD_CONTROL                                                                          0x1f1e
+#define regHPD1_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD1_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f1f
+#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f20
+#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dcn_dc_dio_hpd2_dispdec
+// base address: 0x40
+#define regHPD2_DC_HPD_INT_STATUS                                                                       0x1f24
+#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD2_DC_HPD_INT_CONTROL                                                                      0x1f25
+#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD2_DC_HPD_CONTROL                                                                          0x1f26
+#define regHPD2_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD2_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f27
+#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f28
+#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dcn_dc_dio_hpd3_dispdec
+// base address: 0x60
+#define regHPD3_DC_HPD_INT_STATUS                                                                       0x1f2c
+#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD3_DC_HPD_INT_CONTROL                                                                      0x1f2d
+#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD3_DC_HPD_CONTROL                                                                          0x1f2e
+#define regHPD3_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD3_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f2f
+#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f30
+#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dcn_dc_dio_hpd4_dispdec
+// base address: 0x80
+#define regHPD4_DC_HPD_INT_STATUS                                                                       0x1f34
+#define regHPD4_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD4_DC_HPD_INT_CONTROL                                                                      0x1f35
+#define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD4_DC_HPD_CONTROL                                                                          0x1f36
+#define regHPD4_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD4_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f37
+#define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f38
+#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dcn_dc_dio_dp0_dispdec
+// base address: 0x0
+#define regDP0_DP_LINK_CNTL                                                                             0x2108
+#define regDP0_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_PIXEL_FORMAT                                                                          0x2109
+#define regDP0_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP0_DP_MSA_COLORIMETRY                                                                       0x210a
+#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP0_DP_CONFIG                                                                                0x210b
+#define regDP0_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP0_DP_VID_STREAM_CNTL                                                                       0x210c
+#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_STEER_FIFO                                                                            0x210d
+#define regDP0_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP0_DP_MSA_MISC                                                                              0x210e
+#define regDP0_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP0_DP_DPHY_INTERNAL_CTRL                                                                    0x210f
+#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP0_DP_VID_TIMING                                                                            0x2110
+#define regDP0_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP0_DP_VID_N                                                                                 0x2111
+#define regDP0_DP_VID_N_BASE_IDX                                                                        2
+#define regDP0_DP_VID_M                                                                                 0x2112
+#define regDP0_DP_VID_M_BASE_IDX                                                                        2
+#define regDP0_DP_LINK_FRAMING_CNTL                                                                     0x2113
+#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP0_DP_HBR2_EYE_PATTERN                                                                      0x2114
+#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP0_DP_VID_MSA_VBID                                                                          0x2115
+#define regDP0_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP0_DP_VID_INTERRUPT_CNTL                                                                    0x2116
+#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP0_DP_DPHY_CNTL                                                                             0x2117
+#define regDP0_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2118
+#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP0_DP_DPHY_SYM0                                                                             0x2119
+#define regDP0_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_SYM1                                                                             0x211a
+#define regDP0_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_SYM2                                                                             0x211b
+#define regDP0_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_8B10B_CNTL                                                                       0x211c
+#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_DPHY_PRBS_CNTL                                                                        0x211d
+#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP0_DP_DPHY_SCRAM_CNTL                                                                       0x211e
+#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_DPHY_CRC_EN                                                                           0x211f
+#define regDP0_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP0_DP_DPHY_CRC_CNTL                                                                         0x2120
+#define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP0_DP_DPHY_CRC_RESULT                                                                       0x2121
+#define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP0_DP_DPHY_CRC_MST_CNTL                                                                     0x2122
+#define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP0_DP_DPHY_CRC_MST_STATUS                                                                   0x2123
+#define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP0_DP_DPHY_FAST_TRAINING                                                                    0x2124
+#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP0_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2125
+#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP0_DP_SEC_CNTL                                                                              0x212b
+#define regDP0_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP0_DP_SEC_CNTL1                                                                             0x212c
+#define regDP0_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_FRAMING1                                                                          0x212d
+#define regDP0_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_FRAMING2                                                                          0x212e
+#define regDP0_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_FRAMING3                                                                          0x212f
+#define regDP0_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_FRAMING4                                                                          0x2130
+#define regDP0_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_AUD_N                                                                             0x2131
+#define regDP0_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_AUD_N_READBACK                                                                    0x2132
+#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP0_DP_SEC_AUD_M                                                                             0x2133
+#define regDP0_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_AUD_M_READBACK                                                                    0x2134
+#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP0_DP_SEC_TIMESTAMP                                                                         0x2135
+#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP0_DP_SEC_PACKET_CNTL                                                                       0x2136
+#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_MSE_RATE_CNTL                                                                         0x2137
+#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP0_DP_MSE_RATE_UPDATE                                                                       0x2139
+#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP0_DP_MSE_SAT0                                                                              0x213a
+#define regDP0_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP0_DP_MSE_SAT1                                                                              0x213b
+#define regDP0_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP0_DP_MSE_SAT2                                                                              0x213c
+#define regDP0_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP0_DP_MSE_SAT_UPDATE                                                                        0x213d
+#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP0_DP_MSE_LINK_TIMING                                                                       0x213e
+#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP0_DP_MSE_MISC_CNTL                                                                         0x213f
+#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2144
+#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2145
+#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP0_DP_MSE_SAT0_STATUS                                                                       0x2147
+#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP0_DP_MSE_SAT1_STATUS                                                                       0x2148
+#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP0_DP_MSE_SAT2_STATUS                                                                       0x2149
+#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP0_DP_DPIA_SPARE                                                                            0x214a
+#define regDP0_DP_DPIA_SPARE_BASE_IDX                                                                   2
+#define regDP0_DP_MSA_TIMING_PARAM1                                                                     0x214c
+#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP0_DP_MSA_TIMING_PARAM2                                                                     0x214d
+#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP0_DP_MSA_TIMING_PARAM3                                                                     0x214e
+#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP0_DP_MSA_TIMING_PARAM4                                                                     0x214f
+#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP0_DP_MSO_CNTL                                                                              0x2150
+#define regDP0_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP0_DP_MSO_CNTL1                                                                             0x2151
+#define regDP0_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP0_DP_DSC_CNTL                                                                              0x2152
+#define regDP0_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP0_DP_SEC_CNTL2                                                                             0x2153
+#define regDP0_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL3                                                                             0x2154
+#define regDP0_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL4                                                                             0x2155
+#define regDP0_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL5                                                                             0x2156
+#define regDP0_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL6                                                                             0x2157
+#define regDP0_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL7                                                                             0x2158
+#define regDP0_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP0_DP_DB_CNTL                                                                               0x2159
+#define regDP0_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP0_DP_MSA_VBID_MISC                                                                         0x215a
+#define regDP0_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP0_DP_SEC_METADATA_TRANSMISSION                                                             0x215b
+#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP0_DP_ALPM_CNTL                                                                             0x215d
+#define regDP0_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_GSP8_CNTL                                                                             0x215e
+#define regDP0_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_GSP9_CNTL                                                                             0x215f
+#define regDP0_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_GSP10_CNTL                                                                            0x2160
+#define regDP0_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP0_DP_GSP11_CNTL                                                                            0x2161
+#define regDP0_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP0_DP_GSP_EN_DB_STATUS                                                                      0x2162
+#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+#define regDP0_DP_AUXLESS_ALPM_CNTL1                                                                    0x2163
+#define regDP0_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
+#define regDP0_DP_AUXLESS_ALPM_CNTL2                                                                    0x2164
+#define regDP0_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
+#define regDP0_DP_AUXLESS_ALPM_CNTL3                                                                    0x2165
+#define regDP0_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
+#define regDP0_DP_AUXLESS_ALPM_CNTL4                                                                    0x2166
+#define regDP0_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
+#define regDP0_DP_AUXLESS_ALPM_CNTL5                                                                    0x2167
+#define regDP0_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
+
+
+// addressBlock: dcn_dc_dio_dig0_dispdec
+// base address: 0x0
+#define regDIG0_DIG_FE_CNTL                                                                             0x208b
+#define regDIG0_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG0_DIG_OUTPUT_CRC_CNTL                                                                     0x208c
+#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG0_DIG_OUTPUT_CRC_RESULT                                                                   0x208d
+#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG0_DIG_CLOCK_PATTERN                                                                       0x208e
+#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG0_DIG_TEST_PATTERN                                                                        0x208f
+#define regDIG0_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG0_DIG_RANDOM_PATTERN_SEED                                                                 0x2090
+#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG0_DIG_FIFO_CTRL0                                                                          0x2091
+#define regDIG0_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
+#define regDIG0_DIG_FIFO_CTRL1                                                                          0x2092
+#define regDIG0_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
+#define regDIG0_HDMI_METADATA_PACKET_CONTROL                                                            0x2093
+#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG0_HDMI_CONTROL                                                                            0x2094
+#define regDIG0_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG0_HDMI_STATUS                                                                             0x2095
+#define regDIG0_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG0_HDMI_AUDIO_PACKET_CONTROL                                                               0x2096
+#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG0_HDMI_ACR_PACKET_CONTROL                                                                 0x2097
+#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG0_HDMI_VBI_PACKET_CONTROL                                                                 0x2098
+#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG0_HDMI_INFOFRAME_CONTROL0                                                                 0x2099
+#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG0_HDMI_INFOFRAME_CONTROL1                                                                 0x209a
+#define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0                                                            0x209b
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6                                                            0x209c
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5                                                            0x209d
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG0_HDMI_GC                                                                                 0x209e
+#define regDIG0_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1                                                            0x209f
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2                                                            0x20a0
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3                                                            0x20a1
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4                                                            0x20a2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7                                                            0x20a3
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8                                                            0x20a4
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9                                                            0x20a5
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10                                                           0x20a6
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG0_HDMI_DB_CONTROL                                                                         0x20a7
+#define regDIG0_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG0_HDMI_ACR_32_0                                                                           0x20a8
+#define regDIG0_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_32_1                                                                           0x20a9
+#define regDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_44_0                                                                           0x20aa
+#define regDIG0_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_44_1                                                                           0x20ab
+#define regDIG0_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_48_0                                                                           0x20ac
+#define regDIG0_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_48_1                                                                           0x20ad
+#define regDIG0_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_STATUS_0                                                                       0x20ae
+#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG0_HDMI_ACR_STATUS_1                                                                       0x20af
+#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG0_AFMT_CNTL                                                                               0x20b0
+#define regDIG0_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG0_DIG_BE_CNTL                                                                             0x20b1
+#define regDIG0_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG0_DIG_BE_EN_CNTL                                                                          0x20b2
+#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG0_TMDS_CNTL                                                                               0x20d8
+#define regDIG0_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG0_TMDS_CONTROL_CHAR                                                                       0x20d9
+#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG0_TMDS_CONTROL0_FEEDBACK                                                                  0x20da
+#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG0_TMDS_STEREOSYNC_CTL_SEL                                                                 0x20db
+#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x20dc
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x20dd
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG0_TMDS_CTL_BITS                                                                           0x20df
+#define regDIG0_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG0_TMDS_DCBALANCER_CONTROL                                                                 0x20e0
+#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR                                                                0x20e1
+#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG0_TMDS_CTL0_1_GEN_CNTL                                                                    0x20e2
+#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG0_TMDS_CTL2_3_GEN_CNTL                                                                    0x20e3
+#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG0_DIG_VERSION                                                                             0x20e5
+#define regDIG0_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG0_FORCE_DIG_DISABLE                                                                       0x20e6
+#define regDIG0_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dio_dp1_dispdec
+// base address: 0x400
+#define regDP1_DP_LINK_CNTL                                                                             0x2208
+#define regDP1_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_PIXEL_FORMAT                                                                          0x2209
+#define regDP1_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP1_DP_MSA_COLORIMETRY                                                                       0x220a
+#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP1_DP_CONFIG                                                                                0x220b
+#define regDP1_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP1_DP_VID_STREAM_CNTL                                                                       0x220c
+#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_STEER_FIFO                                                                            0x220d
+#define regDP1_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP1_DP_MSA_MISC                                                                              0x220e
+#define regDP1_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP1_DP_DPHY_INTERNAL_CTRL                                                                    0x220f
+#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP1_DP_VID_TIMING                                                                            0x2210
+#define regDP1_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP1_DP_VID_N                                                                                 0x2211
+#define regDP1_DP_VID_N_BASE_IDX                                                                        2
+#define regDP1_DP_VID_M                                                                                 0x2212
+#define regDP1_DP_VID_M_BASE_IDX                                                                        2
+#define regDP1_DP_LINK_FRAMING_CNTL                                                                     0x2213
+#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP1_DP_HBR2_EYE_PATTERN                                                                      0x2214
+#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP1_DP_VID_MSA_VBID                                                                          0x2215
+#define regDP1_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP1_DP_VID_INTERRUPT_CNTL                                                                    0x2216
+#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP1_DP_DPHY_CNTL                                                                             0x2217
+#define regDP1_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2218
+#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP1_DP_DPHY_SYM0                                                                             0x2219
+#define regDP1_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_SYM1                                                                             0x221a
+#define regDP1_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_SYM2                                                                             0x221b
+#define regDP1_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_8B10B_CNTL                                                                       0x221c
+#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_DPHY_PRBS_CNTL                                                                        0x221d
+#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP1_DP_DPHY_SCRAM_CNTL                                                                       0x221e
+#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_DPHY_CRC_EN                                                                           0x221f
+#define regDP1_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP1_DP_DPHY_CRC_CNTL                                                                         0x2220
+#define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP1_DP_DPHY_CRC_RESULT                                                                       0x2221
+#define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP1_DP_DPHY_CRC_MST_CNTL                                                                     0x2222
+#define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP1_DP_DPHY_CRC_MST_STATUS                                                                   0x2223
+#define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP1_DP_DPHY_FAST_TRAINING                                                                    0x2224
+#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP1_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2225
+#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP1_DP_SEC_CNTL                                                                              0x222b
+#define regDP1_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP1_DP_SEC_CNTL1                                                                             0x222c
+#define regDP1_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_FRAMING1                                                                          0x222d
+#define regDP1_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_FRAMING2                                                                          0x222e
+#define regDP1_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_FRAMING3                                                                          0x222f
+#define regDP1_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_FRAMING4                                                                          0x2230
+#define regDP1_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_AUD_N                                                                             0x2231
+#define regDP1_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_AUD_N_READBACK                                                                    0x2232
+#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP1_DP_SEC_AUD_M                                                                             0x2233
+#define regDP1_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_AUD_M_READBACK                                                                    0x2234
+#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP1_DP_SEC_TIMESTAMP                                                                         0x2235
+#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP1_DP_SEC_PACKET_CNTL                                                                       0x2236
+#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_MSE_RATE_CNTL                                                                         0x2237
+#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP1_DP_MSE_RATE_UPDATE                                                                       0x2239
+#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP1_DP_MSE_SAT0                                                                              0x223a
+#define regDP1_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP1_DP_MSE_SAT1                                                                              0x223b
+#define regDP1_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP1_DP_MSE_SAT2                                                                              0x223c
+#define regDP1_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP1_DP_MSE_SAT_UPDATE                                                                        0x223d
+#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP1_DP_MSE_LINK_TIMING                                                                       0x223e
+#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP1_DP_MSE_MISC_CNTL                                                                         0x223f
+#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2244
+#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2245
+#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP1_DP_MSE_SAT0_STATUS                                                                       0x2247
+#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP1_DP_MSE_SAT1_STATUS                                                                       0x2248
+#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP1_DP_MSE_SAT2_STATUS                                                                       0x2249
+#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP1_DP_DPIA_SPARE                                                                            0x224a
+#define regDP1_DP_DPIA_SPARE_BASE_IDX                                                                   2
+#define regDP1_DP_MSA_TIMING_PARAM1                                                                     0x224c
+#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP1_DP_MSA_TIMING_PARAM2                                                                     0x224d
+#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP1_DP_MSA_TIMING_PARAM3                                                                     0x224e
+#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP1_DP_MSA_TIMING_PARAM4                                                                     0x224f
+#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP1_DP_MSO_CNTL                                                                              0x2250
+#define regDP1_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP1_DP_MSO_CNTL1                                                                             0x2251
+#define regDP1_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP1_DP_DSC_CNTL                                                                              0x2252
+#define regDP1_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP1_DP_SEC_CNTL2                                                                             0x2253
+#define regDP1_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL3                                                                             0x2254
+#define regDP1_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL4                                                                             0x2255
+#define regDP1_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL5                                                                             0x2256
+#define regDP1_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL6                                                                             0x2257
+#define regDP1_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL7                                                                             0x2258
+#define regDP1_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP1_DP_DB_CNTL                                                                               0x2259
+#define regDP1_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP1_DP_MSA_VBID_MISC                                                                         0x225a
+#define regDP1_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP1_DP_SEC_METADATA_TRANSMISSION                                                             0x225b
+#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP1_DP_ALPM_CNTL                                                                             0x225d
+#define regDP1_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_GSP8_CNTL                                                                             0x225e
+#define regDP1_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_GSP9_CNTL                                                                             0x225f
+#define regDP1_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_GSP10_CNTL                                                                            0x2260
+#define regDP1_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP1_DP_GSP11_CNTL                                                                            0x2261
+#define regDP1_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP1_DP_GSP_EN_DB_STATUS                                                                      0x2262
+#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+#define regDP1_DP_AUXLESS_ALPM_CNTL1                                                                    0x2263
+#define regDP1_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
+#define regDP1_DP_AUXLESS_ALPM_CNTL2                                                                    0x2264
+#define regDP1_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
+#define regDP1_DP_AUXLESS_ALPM_CNTL3                                                                    0x2265
+#define regDP1_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
+#define regDP1_DP_AUXLESS_ALPM_CNTL4                                                                    0x2266
+#define regDP1_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
+#define regDP1_DP_AUXLESS_ALPM_CNTL5                                                                    0x2267
+#define regDP1_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
+
+
+// addressBlock: dcn_dc_dio_dig1_dispdec
+// base address: 0x400
+#define regDIG1_DIG_FE_CNTL                                                                             0x218b
+#define regDIG1_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG1_DIG_OUTPUT_CRC_CNTL                                                                     0x218c
+#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG1_DIG_OUTPUT_CRC_RESULT                                                                   0x218d
+#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG1_DIG_CLOCK_PATTERN                                                                       0x218e
+#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG1_DIG_TEST_PATTERN                                                                        0x218f
+#define regDIG1_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG1_DIG_RANDOM_PATTERN_SEED                                                                 0x2190
+#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG1_DIG_FIFO_CTRL0                                                                          0x2191
+#define regDIG1_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
+#define regDIG1_DIG_FIFO_CTRL1                                                                          0x2192
+#define regDIG1_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
+#define regDIG1_HDMI_METADATA_PACKET_CONTROL                                                            0x2193
+#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG1_HDMI_CONTROL                                                                            0x2194
+#define regDIG1_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG1_HDMI_STATUS                                                                             0x2195
+#define regDIG1_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG1_HDMI_AUDIO_PACKET_CONTROL                                                               0x2196
+#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG1_HDMI_ACR_PACKET_CONTROL                                                                 0x2197
+#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG1_HDMI_VBI_PACKET_CONTROL                                                                 0x2198
+#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG1_HDMI_INFOFRAME_CONTROL0                                                                 0x2199
+#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG1_HDMI_INFOFRAME_CONTROL1                                                                 0x219a
+#define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0                                                            0x219b
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6                                                            0x219c
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5                                                            0x219d
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG1_HDMI_GC                                                                                 0x219e
+#define regDIG1_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1                                                            0x219f
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2                                                            0x21a0
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3                                                            0x21a1
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4                                                            0x21a2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7                                                            0x21a3
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8                                                            0x21a4
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9                                                            0x21a5
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10                                                           0x21a6
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG1_HDMI_DB_CONTROL                                                                         0x21a7
+#define regDIG1_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG1_HDMI_ACR_32_0                                                                           0x21a8
+#define regDIG1_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_32_1                                                                           0x21a9
+#define regDIG1_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_44_0                                                                           0x21aa
+#define regDIG1_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_44_1                                                                           0x21ab
+#define regDIG1_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_48_0                                                                           0x21ac
+#define regDIG1_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_48_1                                                                           0x21ad
+#define regDIG1_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_STATUS_0                                                                       0x21ae
+#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG1_HDMI_ACR_STATUS_1                                                                       0x21af
+#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG1_AFMT_CNTL                                                                               0x21b0
+#define regDIG1_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG1_DIG_BE_CNTL                                                                             0x21b1
+#define regDIG1_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG1_DIG_BE_EN_CNTL                                                                          0x21b2
+#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG1_TMDS_CNTL                                                                               0x21d8
+#define regDIG1_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG1_TMDS_CONTROL_CHAR                                                                       0x21d9
+#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG1_TMDS_CONTROL0_FEEDBACK                                                                  0x21da
+#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG1_TMDS_STEREOSYNC_CTL_SEL                                                                 0x21db
+#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x21dc
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x21dd
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG1_TMDS_CTL_BITS                                                                           0x21df
+#define regDIG1_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG1_TMDS_DCBALANCER_CONTROL                                                                 0x21e0
+#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR                                                                0x21e1
+#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG1_TMDS_CTL0_1_GEN_CNTL                                                                    0x21e2
+#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG1_TMDS_CTL2_3_GEN_CNTL                                                                    0x21e3
+#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG1_DIG_VERSION                                                                             0x21e5
+#define regDIG1_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG1_FORCE_DIG_DISABLE                                                                       0x21e6
+#define regDIG1_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dio_dp2_dispdec
+// base address: 0x800
+#define regDP2_DP_LINK_CNTL                                                                             0x2308
+#define regDP2_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_PIXEL_FORMAT                                                                          0x2309
+#define regDP2_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP2_DP_MSA_COLORIMETRY                                                                       0x230a
+#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP2_DP_CONFIG                                                                                0x230b
+#define regDP2_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP2_DP_VID_STREAM_CNTL                                                                       0x230c
+#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_STEER_FIFO                                                                            0x230d
+#define regDP2_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP2_DP_MSA_MISC                                                                              0x230e
+#define regDP2_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP2_DP_DPHY_INTERNAL_CTRL                                                                    0x230f
+#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP2_DP_VID_TIMING                                                                            0x2310
+#define regDP2_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP2_DP_VID_N                                                                                 0x2311
+#define regDP2_DP_VID_N_BASE_IDX                                                                        2
+#define regDP2_DP_VID_M                                                                                 0x2312
+#define regDP2_DP_VID_M_BASE_IDX                                                                        2
+#define regDP2_DP_LINK_FRAMING_CNTL                                                                     0x2313
+#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP2_DP_HBR2_EYE_PATTERN                                                                      0x2314
+#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP2_DP_VID_MSA_VBID                                                                          0x2315
+#define regDP2_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP2_DP_VID_INTERRUPT_CNTL                                                                    0x2316
+#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP2_DP_DPHY_CNTL                                                                             0x2317
+#define regDP2_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2318
+#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP2_DP_DPHY_SYM0                                                                             0x2319
+#define regDP2_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_SYM1                                                                             0x231a
+#define regDP2_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_SYM2                                                                             0x231b
+#define regDP2_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_8B10B_CNTL                                                                       0x231c
+#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_DPHY_PRBS_CNTL                                                                        0x231d
+#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP2_DP_DPHY_SCRAM_CNTL                                                                       0x231e
+#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_DPHY_CRC_EN                                                                           0x231f
+#define regDP2_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP2_DP_DPHY_CRC_CNTL                                                                         0x2320
+#define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP2_DP_DPHY_CRC_RESULT                                                                       0x2321
+#define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP2_DP_DPHY_CRC_MST_CNTL                                                                     0x2322
+#define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP2_DP_DPHY_CRC_MST_STATUS                                                                   0x2323
+#define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP2_DP_DPHY_FAST_TRAINING                                                                    0x2324
+#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP2_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2325
+#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP2_DP_SEC_CNTL                                                                              0x232b
+#define regDP2_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP2_DP_SEC_CNTL1                                                                             0x232c
+#define regDP2_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_FRAMING1                                                                          0x232d
+#define regDP2_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_FRAMING2                                                                          0x232e
+#define regDP2_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_FRAMING3                                                                          0x232f
+#define regDP2_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_FRAMING4                                                                          0x2330
+#define regDP2_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_AUD_N                                                                             0x2331
+#define regDP2_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_AUD_N_READBACK                                                                    0x2332
+#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP2_DP_SEC_AUD_M                                                                             0x2333
+#define regDP2_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_AUD_M_READBACK                                                                    0x2334
+#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP2_DP_SEC_TIMESTAMP                                                                         0x2335
+#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP2_DP_SEC_PACKET_CNTL                                                                       0x2336
+#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_MSE_RATE_CNTL                                                                         0x2337
+#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP2_DP_MSE_RATE_UPDATE                                                                       0x2339
+#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP2_DP_MSE_SAT0                                                                              0x233a
+#define regDP2_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP2_DP_MSE_SAT1                                                                              0x233b
+#define regDP2_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP2_DP_MSE_SAT2                                                                              0x233c
+#define regDP2_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP2_DP_MSE_SAT_UPDATE                                                                        0x233d
+#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP2_DP_MSE_LINK_TIMING                                                                       0x233e
+#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP2_DP_MSE_MISC_CNTL                                                                         0x233f
+#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2344
+#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2345
+#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP2_DP_MSE_SAT0_STATUS                                                                       0x2347
+#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP2_DP_MSE_SAT1_STATUS                                                                       0x2348
+#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP2_DP_MSE_SAT2_STATUS                                                                       0x2349
+#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP2_DP_DPIA_SPARE                                                                            0x234a
+#define regDP2_DP_DPIA_SPARE_BASE_IDX                                                                   2
+#define regDP2_DP_MSA_TIMING_PARAM1                                                                     0x234c
+#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP2_DP_MSA_TIMING_PARAM2                                                                     0x234d
+#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP2_DP_MSA_TIMING_PARAM3                                                                     0x234e
+#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP2_DP_MSA_TIMING_PARAM4                                                                     0x234f
+#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP2_DP_MSO_CNTL                                                                              0x2350
+#define regDP2_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP2_DP_MSO_CNTL1                                                                             0x2351
+#define regDP2_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP2_DP_DSC_CNTL                                                                              0x2352
+#define regDP2_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP2_DP_SEC_CNTL2                                                                             0x2353
+#define regDP2_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL3                                                                             0x2354
+#define regDP2_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL4                                                                             0x2355
+#define regDP2_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL5                                                                             0x2356
+#define regDP2_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL6                                                                             0x2357
+#define regDP2_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL7                                                                             0x2358
+#define regDP2_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP2_DP_DB_CNTL                                                                               0x2359
+#define regDP2_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP2_DP_MSA_VBID_MISC                                                                         0x235a
+#define regDP2_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP2_DP_SEC_METADATA_TRANSMISSION                                                             0x235b
+#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP2_DP_ALPM_CNTL                                                                             0x235d
+#define regDP2_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_GSP8_CNTL                                                                             0x235e
+#define regDP2_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_GSP9_CNTL                                                                             0x235f
+#define regDP2_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_GSP10_CNTL                                                                            0x2360
+#define regDP2_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP2_DP_GSP11_CNTL                                                                            0x2361
+#define regDP2_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP2_DP_GSP_EN_DB_STATUS                                                                      0x2362
+#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+#define regDP2_DP_AUXLESS_ALPM_CNTL1                                                                    0x2363
+#define regDP2_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
+#define regDP2_DP_AUXLESS_ALPM_CNTL2                                                                    0x2364
+#define regDP2_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
+#define regDP2_DP_AUXLESS_ALPM_CNTL3                                                                    0x2365
+#define regDP2_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
+#define regDP2_DP_AUXLESS_ALPM_CNTL4                                                                    0x2366
+#define regDP2_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
+#define regDP2_DP_AUXLESS_ALPM_CNTL5                                                                    0x2367
+#define regDP2_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
+
+
+// addressBlock: dcn_dc_dio_dig2_dispdec
+// base address: 0x800
+#define regDIG2_DIG_FE_CNTL                                                                             0x228b
+#define regDIG2_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG2_DIG_OUTPUT_CRC_CNTL                                                                     0x228c
+#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG2_DIG_OUTPUT_CRC_RESULT                                                                   0x228d
+#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG2_DIG_CLOCK_PATTERN                                                                       0x228e
+#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG2_DIG_TEST_PATTERN                                                                        0x228f
+#define regDIG2_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG2_DIG_RANDOM_PATTERN_SEED                                                                 0x2290
+#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG2_DIG_FIFO_CTRL0                                                                          0x2291
+#define regDIG2_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
+#define regDIG2_DIG_FIFO_CTRL1                                                                          0x2292
+#define regDIG2_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
+#define regDIG2_HDMI_METADATA_PACKET_CONTROL                                                            0x2293
+#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG2_HDMI_CONTROL                                                                            0x2294
+#define regDIG2_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG2_HDMI_STATUS                                                                             0x2295
+#define regDIG2_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG2_HDMI_AUDIO_PACKET_CONTROL                                                               0x2296
+#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG2_HDMI_ACR_PACKET_CONTROL                                                                 0x2297
+#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG2_HDMI_VBI_PACKET_CONTROL                                                                 0x2298
+#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG2_HDMI_INFOFRAME_CONTROL0                                                                 0x2299
+#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG2_HDMI_INFOFRAME_CONTROL1                                                                 0x229a
+#define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0                                                            0x229b
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6                                                            0x229c
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5                                                            0x229d
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG2_HDMI_GC                                                                                 0x229e
+#define regDIG2_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1                                                            0x229f
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2                                                            0x22a0
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3                                                            0x22a1
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4                                                            0x22a2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7                                                            0x22a3
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8                                                            0x22a4
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9                                                            0x22a5
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10                                                           0x22a6
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG2_HDMI_DB_CONTROL                                                                         0x22a7
+#define regDIG2_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG2_HDMI_ACR_32_0                                                                           0x22a8
+#define regDIG2_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_32_1                                                                           0x22a9
+#define regDIG2_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_44_0                                                                           0x22aa
+#define regDIG2_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_44_1                                                                           0x22ab
+#define regDIG2_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_48_0                                                                           0x22ac
+#define regDIG2_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_48_1                                                                           0x22ad
+#define regDIG2_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_STATUS_0                                                                       0x22ae
+#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG2_HDMI_ACR_STATUS_1                                                                       0x22af
+#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG2_AFMT_CNTL                                                                               0x22b0
+#define regDIG2_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG2_DIG_BE_CNTL                                                                             0x22b1
+#define regDIG2_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG2_DIG_BE_EN_CNTL                                                                          0x22b2
+#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG2_TMDS_CNTL                                                                               0x22d8
+#define regDIG2_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG2_TMDS_CONTROL_CHAR                                                                       0x22d9
+#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG2_TMDS_CONTROL0_FEEDBACK                                                                  0x22da
+#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG2_TMDS_STEREOSYNC_CTL_SEL                                                                 0x22db
+#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x22dc
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x22dd
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG2_TMDS_CTL_BITS                                                                           0x22df
+#define regDIG2_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG2_TMDS_DCBALANCER_CONTROL                                                                 0x22e0
+#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR                                                                0x22e1
+#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG2_TMDS_CTL0_1_GEN_CNTL                                                                    0x22e2
+#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG2_TMDS_CTL2_3_GEN_CNTL                                                                    0x22e3
+#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG2_DIG_VERSION                                                                             0x22e5
+#define regDIG2_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG2_FORCE_DIG_DISABLE                                                                       0x22e6
+#define regDIG2_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dio_dp3_dispdec
+// base address: 0xc00
+#define regDP3_DP_LINK_CNTL                                                                             0x2408
+#define regDP3_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_PIXEL_FORMAT                                                                          0x2409
+#define regDP3_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP3_DP_MSA_COLORIMETRY                                                                       0x240a
+#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP3_DP_CONFIG                                                                                0x240b
+#define regDP3_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP3_DP_VID_STREAM_CNTL                                                                       0x240c
+#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_STEER_FIFO                                                                            0x240d
+#define regDP3_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP3_DP_MSA_MISC                                                                              0x240e
+#define regDP3_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP3_DP_DPHY_INTERNAL_CTRL                                                                    0x240f
+#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP3_DP_VID_TIMING                                                                            0x2410
+#define regDP3_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP3_DP_VID_N                                                                                 0x2411
+#define regDP3_DP_VID_N_BASE_IDX                                                                        2
+#define regDP3_DP_VID_M                                                                                 0x2412
+#define regDP3_DP_VID_M_BASE_IDX                                                                        2
+#define regDP3_DP_LINK_FRAMING_CNTL                                                                     0x2413
+#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP3_DP_HBR2_EYE_PATTERN                                                                      0x2414
+#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP3_DP_VID_MSA_VBID                                                                          0x2415
+#define regDP3_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP3_DP_VID_INTERRUPT_CNTL                                                                    0x2416
+#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP3_DP_DPHY_CNTL                                                                             0x2417
+#define regDP3_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2418
+#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP3_DP_DPHY_SYM0                                                                             0x2419
+#define regDP3_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_SYM1                                                                             0x241a
+#define regDP3_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_SYM2                                                                             0x241b
+#define regDP3_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_8B10B_CNTL                                                                       0x241c
+#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_DPHY_PRBS_CNTL                                                                        0x241d
+#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP3_DP_DPHY_SCRAM_CNTL                                                                       0x241e
+#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_DPHY_CRC_EN                                                                           0x241f
+#define regDP3_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP3_DP_DPHY_CRC_CNTL                                                                         0x2420
+#define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP3_DP_DPHY_CRC_RESULT                                                                       0x2421
+#define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP3_DP_DPHY_CRC_MST_CNTL                                                                     0x2422
+#define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP3_DP_DPHY_CRC_MST_STATUS                                                                   0x2423
+#define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP3_DP_DPHY_FAST_TRAINING                                                                    0x2424
+#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP3_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2425
+#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP3_DP_SEC_CNTL                                                                              0x242b
+#define regDP3_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP3_DP_SEC_CNTL1                                                                             0x242c
+#define regDP3_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_FRAMING1                                                                          0x242d
+#define regDP3_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_FRAMING2                                                                          0x242e
+#define regDP3_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_FRAMING3                                                                          0x242f
+#define regDP3_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_FRAMING4                                                                          0x2430
+#define regDP3_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_AUD_N                                                                             0x2431
+#define regDP3_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_AUD_N_READBACK                                                                    0x2432
+#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP3_DP_SEC_AUD_M                                                                             0x2433
+#define regDP3_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_AUD_M_READBACK                                                                    0x2434
+#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP3_DP_SEC_TIMESTAMP                                                                         0x2435
+#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP3_DP_SEC_PACKET_CNTL                                                                       0x2436
+#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_MSE_RATE_CNTL                                                                         0x2437
+#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP3_DP_MSE_RATE_UPDATE                                                                       0x2439
+#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP3_DP_MSE_SAT0                                                                              0x243a
+#define regDP3_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP3_DP_MSE_SAT1                                                                              0x243b
+#define regDP3_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP3_DP_MSE_SAT2                                                                              0x243c
+#define regDP3_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP3_DP_MSE_SAT_UPDATE                                                                        0x243d
+#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP3_DP_MSE_LINK_TIMING                                                                       0x243e
+#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP3_DP_MSE_MISC_CNTL                                                                         0x243f
+#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2444
+#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2445
+#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP3_DP_MSE_SAT0_STATUS                                                                       0x2447
+#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP3_DP_MSE_SAT1_STATUS                                                                       0x2448
+#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP3_DP_MSE_SAT2_STATUS                                                                       0x2449
+#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP3_DP_DPIA_SPARE                                                                            0x244a
+#define regDP3_DP_DPIA_SPARE_BASE_IDX                                                                   2
+#define regDP3_DP_MSA_TIMING_PARAM1                                                                     0x244c
+#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP3_DP_MSA_TIMING_PARAM2                                                                     0x244d
+#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP3_DP_MSA_TIMING_PARAM3                                                                     0x244e
+#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP3_DP_MSA_TIMING_PARAM4                                                                     0x244f
+#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP3_DP_MSO_CNTL                                                                              0x2450
+#define regDP3_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP3_DP_MSO_CNTL1                                                                             0x2451
+#define regDP3_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP3_DP_DSC_CNTL                                                                              0x2452
+#define regDP3_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP3_DP_SEC_CNTL2                                                                             0x2453
+#define regDP3_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL3                                                                             0x2454
+#define regDP3_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL4                                                                             0x2455
+#define regDP3_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL5                                                                             0x2456
+#define regDP3_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL6                                                                             0x2457
+#define regDP3_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL7                                                                             0x2458
+#define regDP3_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP3_DP_DB_CNTL                                                                               0x2459
+#define regDP3_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP3_DP_MSA_VBID_MISC                                                                         0x245a
+#define regDP3_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP3_DP_SEC_METADATA_TRANSMISSION                                                             0x245b
+#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP3_DP_ALPM_CNTL                                                                             0x245d
+#define regDP3_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_GSP8_CNTL                                                                             0x245e
+#define regDP3_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_GSP9_CNTL                                                                             0x245f
+#define regDP3_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_GSP10_CNTL                                                                            0x2460
+#define regDP3_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP3_DP_GSP11_CNTL                                                                            0x2461
+#define regDP3_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP3_DP_GSP_EN_DB_STATUS                                                                      0x2462
+#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+#define regDP3_DP_AUXLESS_ALPM_CNTL1                                                                    0x2463
+#define regDP3_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
+#define regDP3_DP_AUXLESS_ALPM_CNTL2                                                                    0x2464
+#define regDP3_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
+#define regDP3_DP_AUXLESS_ALPM_CNTL3                                                                    0x2465
+#define regDP3_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
+#define regDP3_DP_AUXLESS_ALPM_CNTL4                                                                    0x2466
+#define regDP3_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
+#define regDP3_DP_AUXLESS_ALPM_CNTL5                                                                    0x2467
+#define regDP3_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
+
+
+// addressBlock: dcn_dc_dio_dig3_dispdec
+// base address: 0xc00
+#define regDIG3_DIG_FE_CNTL                                                                             0x238b
+#define regDIG3_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG3_DIG_OUTPUT_CRC_CNTL                                                                     0x238c
+#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG3_DIG_OUTPUT_CRC_RESULT                                                                   0x238d
+#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG3_DIG_CLOCK_PATTERN                                                                       0x238e
+#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG3_DIG_TEST_PATTERN                                                                        0x238f
+#define regDIG3_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG3_DIG_RANDOM_PATTERN_SEED                                                                 0x2390
+#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG3_DIG_FIFO_CTRL0                                                                          0x2391
+#define regDIG3_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
+#define regDIG3_DIG_FIFO_CTRL1                                                                          0x2392
+#define regDIG3_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
+#define regDIG3_HDMI_METADATA_PACKET_CONTROL                                                            0x2393
+#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG3_HDMI_CONTROL                                                                            0x2394
+#define regDIG3_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG3_HDMI_STATUS                                                                             0x2395
+#define regDIG3_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG3_HDMI_AUDIO_PACKET_CONTROL                                                               0x2396
+#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG3_HDMI_ACR_PACKET_CONTROL                                                                 0x2397
+#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG3_HDMI_VBI_PACKET_CONTROL                                                                 0x2398
+#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG3_HDMI_INFOFRAME_CONTROL0                                                                 0x2399
+#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG3_HDMI_INFOFRAME_CONTROL1                                                                 0x239a
+#define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0                                                            0x239b
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6                                                            0x239c
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5                                                            0x239d
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG3_HDMI_GC                                                                                 0x239e
+#define regDIG3_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1                                                            0x239f
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2                                                            0x23a0
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3                                                            0x23a1
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4                                                            0x23a2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7                                                            0x23a3
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8                                                            0x23a4
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9                                                            0x23a5
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10                                                           0x23a6
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG3_HDMI_DB_CONTROL                                                                         0x23a7
+#define regDIG3_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG3_HDMI_ACR_32_0                                                                           0x23a8
+#define regDIG3_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_32_1                                                                           0x23a9
+#define regDIG3_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_44_0                                                                           0x23aa
+#define regDIG3_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_44_1                                                                           0x23ab
+#define regDIG3_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_48_0                                                                           0x23ac
+#define regDIG3_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_48_1                                                                           0x23ad
+#define regDIG3_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_STATUS_0                                                                       0x23ae
+#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG3_HDMI_ACR_STATUS_1                                                                       0x23af
+#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG3_AFMT_CNTL                                                                               0x23b0
+#define regDIG3_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG3_DIG_BE_CNTL                                                                             0x23b1
+#define regDIG3_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG3_DIG_BE_EN_CNTL                                                                          0x23b2
+#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG3_TMDS_CNTL                                                                               0x23d8
+#define regDIG3_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG3_TMDS_CONTROL_CHAR                                                                       0x23d9
+#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG3_TMDS_CONTROL0_FEEDBACK                                                                  0x23da
+#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG3_TMDS_STEREOSYNC_CTL_SEL                                                                 0x23db
+#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x23dc
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x23dd
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG3_TMDS_CTL_BITS                                                                           0x23df
+#define regDIG3_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG3_TMDS_DCBALANCER_CONTROL                                                                 0x23e0
+#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR                                                                0x23e1
+#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG3_TMDS_CTL0_1_GEN_CNTL                                                                    0x23e2
+#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG3_TMDS_CTL2_3_GEN_CNTL                                                                    0x23e3
+#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG3_DIG_VERSION                                                                             0x23e5
+#define regDIG3_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG3_FORCE_DIG_DISABLE                                                                       0x23e6
+#define regDIG3_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dio_dp4_dispdec
+// base address: 0x1000
+#define regDP4_DP_LINK_CNTL                                                                             0x2508
+#define regDP4_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_PIXEL_FORMAT                                                                          0x2509
+#define regDP4_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP4_DP_MSA_COLORIMETRY                                                                       0x250a
+#define regDP4_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP4_DP_CONFIG                                                                                0x250b
+#define regDP4_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP4_DP_VID_STREAM_CNTL                                                                       0x250c
+#define regDP4_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_STEER_FIFO                                                                            0x250d
+#define regDP4_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP4_DP_MSA_MISC                                                                              0x250e
+#define regDP4_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP4_DP_DPHY_INTERNAL_CTRL                                                                    0x250f
+#define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP4_DP_VID_TIMING                                                                            0x2510
+#define regDP4_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP4_DP_VID_N                                                                                 0x2511
+#define regDP4_DP_VID_N_BASE_IDX                                                                        2
+#define regDP4_DP_VID_M                                                                                 0x2512
+#define regDP4_DP_VID_M_BASE_IDX                                                                        2
+#define regDP4_DP_LINK_FRAMING_CNTL                                                                     0x2513
+#define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP4_DP_HBR2_EYE_PATTERN                                                                      0x2514
+#define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP4_DP_VID_MSA_VBID                                                                          0x2515
+#define regDP4_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP4_DP_VID_INTERRUPT_CNTL                                                                    0x2516
+#define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP4_DP_DPHY_CNTL                                                                             0x2517
+#define regDP4_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2518
+#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP4_DP_DPHY_SYM0                                                                             0x2519
+#define regDP4_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_SYM1                                                                             0x251a
+#define regDP4_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_SYM2                                                                             0x251b
+#define regDP4_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_8B10B_CNTL                                                                       0x251c
+#define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_DPHY_PRBS_CNTL                                                                        0x251d
+#define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP4_DP_DPHY_SCRAM_CNTL                                                                       0x251e
+#define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_DPHY_CRC_EN                                                                           0x251f
+#define regDP4_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP4_DP_DPHY_CRC_CNTL                                                                         0x2520
+#define regDP4_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP4_DP_DPHY_CRC_RESULT                                                                       0x2521
+#define regDP4_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP4_DP_DPHY_CRC_MST_CNTL                                                                     0x2522
+#define regDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP4_DP_DPHY_CRC_MST_STATUS                                                                   0x2523
+#define regDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP4_DP_DPHY_FAST_TRAINING                                                                    0x2524
+#define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP4_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2525
+#define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP4_DP_SEC_CNTL                                                                              0x252b
+#define regDP4_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP4_DP_SEC_CNTL1                                                                             0x252c
+#define regDP4_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_FRAMING1                                                                          0x252d
+#define regDP4_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_FRAMING2                                                                          0x252e
+#define regDP4_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_FRAMING3                                                                          0x252f
+#define regDP4_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_FRAMING4                                                                          0x2530
+#define regDP4_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_AUD_N                                                                             0x2531
+#define regDP4_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_AUD_N_READBACK                                                                    0x2532
+#define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP4_DP_SEC_AUD_M                                                                             0x2533
+#define regDP4_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_AUD_M_READBACK                                                                    0x2534
+#define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP4_DP_SEC_TIMESTAMP                                                                         0x2535
+#define regDP4_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP4_DP_SEC_PACKET_CNTL                                                                       0x2536
+#define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_MSE_RATE_CNTL                                                                         0x2537
+#define regDP4_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP4_DP_MSE_RATE_UPDATE                                                                       0x2539
+#define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP4_DP_MSE_SAT0                                                                              0x253a
+#define regDP4_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP4_DP_MSE_SAT1                                                                              0x253b
+#define regDP4_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP4_DP_MSE_SAT2                                                                              0x253c
+#define regDP4_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP4_DP_MSE_SAT_UPDATE                                                                        0x253d
+#define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP4_DP_MSE_LINK_TIMING                                                                       0x253e
+#define regDP4_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP4_DP_MSE_MISC_CNTL                                                                         0x253f
+#define regDP4_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2544
+#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2545
+#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP4_DP_MSE_SAT0_STATUS                                                                       0x2547
+#define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP4_DP_MSE_SAT1_STATUS                                                                       0x2548
+#define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP4_DP_MSE_SAT2_STATUS                                                                       0x2549
+#define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP4_DP_DPIA_SPARE                                                                            0x254a
+#define regDP4_DP_DPIA_SPARE_BASE_IDX                                                                   2
+#define regDP4_DP_MSA_TIMING_PARAM1                                                                     0x254c
+#define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP4_DP_MSA_TIMING_PARAM2                                                                     0x254d
+#define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP4_DP_MSA_TIMING_PARAM3                                                                     0x254e
+#define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP4_DP_MSA_TIMING_PARAM4                                                                     0x254f
+#define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP4_DP_MSO_CNTL                                                                              0x2550
+#define regDP4_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP4_DP_MSO_CNTL1                                                                             0x2551
+#define regDP4_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP4_DP_DSC_CNTL                                                                              0x2552
+#define regDP4_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP4_DP_SEC_CNTL2                                                                             0x2553
+#define regDP4_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL3                                                                             0x2554
+#define regDP4_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL4                                                                             0x2555
+#define regDP4_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL5                                                                             0x2556
+#define regDP4_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL6                                                                             0x2557
+#define regDP4_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL7                                                                             0x2558
+#define regDP4_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP4_DP_DB_CNTL                                                                               0x2559
+#define regDP4_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP4_DP_MSA_VBID_MISC                                                                         0x255a
+#define regDP4_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP4_DP_SEC_METADATA_TRANSMISSION                                                             0x255b
+#define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP4_DP_ALPM_CNTL                                                                             0x255d
+#define regDP4_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_GSP8_CNTL                                                                             0x255e
+#define regDP4_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_GSP9_CNTL                                                                             0x255f
+#define regDP4_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_GSP10_CNTL                                                                            0x2560
+#define regDP4_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP4_DP_GSP11_CNTL                                                                            0x2561
+#define regDP4_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP4_DP_GSP_EN_DB_STATUS                                                                      0x2562
+#define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+#define regDP4_DP_AUXLESS_ALPM_CNTL1                                                                    0x2563
+#define regDP4_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
+#define regDP4_DP_AUXLESS_ALPM_CNTL2                                                                    0x2564
+#define regDP4_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
+#define regDP4_DP_AUXLESS_ALPM_CNTL3                                                                    0x2565
+#define regDP4_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
+#define regDP4_DP_AUXLESS_ALPM_CNTL4                                                                    0x2566
+#define regDP4_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
+#define regDP4_DP_AUXLESS_ALPM_CNTL5                                                                    0x2567
+#define regDP4_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
+
+
+// addressBlock: dcn_dc_dio_dig4_dispdec
+// base address: 0x1000
+#define regDIG4_DIG_FE_CNTL                                                                             0x248b
+#define regDIG4_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG4_DIG_OUTPUT_CRC_CNTL                                                                     0x248c
+#define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG4_DIG_OUTPUT_CRC_RESULT                                                                   0x248d
+#define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG4_DIG_CLOCK_PATTERN                                                                       0x248e
+#define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG4_DIG_TEST_PATTERN                                                                        0x248f
+#define regDIG4_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG4_DIG_RANDOM_PATTERN_SEED                                                                 0x2490
+#define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG4_DIG_FIFO_CTRL0                                                                          0x2491
+#define regDIG4_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
+#define regDIG4_DIG_FIFO_CTRL1                                                                          0x2492
+#define regDIG4_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
+#define regDIG4_HDMI_METADATA_PACKET_CONTROL                                                            0x2493
+#define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG4_HDMI_CONTROL                                                                            0x2494
+#define regDIG4_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG4_HDMI_STATUS                                                                             0x2495
+#define regDIG4_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG4_HDMI_AUDIO_PACKET_CONTROL                                                               0x2496
+#define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG4_HDMI_ACR_PACKET_CONTROL                                                                 0x2497
+#define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG4_HDMI_VBI_PACKET_CONTROL                                                                 0x2498
+#define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG4_HDMI_INFOFRAME_CONTROL0                                                                 0x2499
+#define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG4_HDMI_INFOFRAME_CONTROL1                                                                 0x249a
+#define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0                                                            0x249b
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6                                                            0x249c
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5                                                            0x249d
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG4_HDMI_GC                                                                                 0x249e
+#define regDIG4_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1                                                            0x249f
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2                                                            0x24a0
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3                                                            0x24a1
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4                                                            0x24a2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7                                                            0x24a3
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8                                                            0x24a4
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9                                                            0x24a5
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10                                                           0x24a6
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG4_HDMI_DB_CONTROL                                                                         0x24a7
+#define regDIG4_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG4_HDMI_ACR_32_0                                                                           0x24a8
+#define regDIG4_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_32_1                                                                           0x24a9
+#define regDIG4_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_44_0                                                                           0x24aa
+#define regDIG4_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_44_1                                                                           0x24ab
+#define regDIG4_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_48_0                                                                           0x24ac
+#define regDIG4_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_48_1                                                                           0x24ad
+#define regDIG4_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_STATUS_0                                                                       0x24ae
+#define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG4_HDMI_ACR_STATUS_1                                                                       0x24af
+#define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG4_AFMT_CNTL                                                                               0x24b0
+#define regDIG4_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG4_DIG_BE_CNTL                                                                             0x24b1
+#define regDIG4_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG4_DIG_BE_EN_CNTL                                                                          0x24b2
+#define regDIG4_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG4_TMDS_CNTL                                                                               0x24d8
+#define regDIG4_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG4_TMDS_CONTROL_CHAR                                                                       0x24d9
+#define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG4_TMDS_CONTROL0_FEEDBACK                                                                  0x24da
+#define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG4_TMDS_STEREOSYNC_CTL_SEL                                                                 0x24db
+#define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x24dc
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x24dd
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG4_TMDS_CTL_BITS                                                                           0x24df
+#define regDIG4_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG4_TMDS_DCBALANCER_CONTROL                                                                 0x24e0
+#define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR                                                                0x24e1
+#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG4_TMDS_CTL0_1_GEN_CNTL                                                                    0x24e2
+#define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG4_TMDS_CTL2_3_GEN_CNTL                                                                    0x24e3
+#define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG4_DIG_VERSION                                                                             0x24e5
+#define regDIG4_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG4_FORCE_DIG_DISABLE                                                                       0x24e6
+#define regDIG4_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dio_dig0_afmt_afmt_dispdec
+// base address: 0x154cc
+#define regAFMT0_AFMT_VBI_PACKET_CONTROL                                                                0x2074
+#define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2075
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT0_AFMT_AUDIO_INFO0                                                                       0x2076
+#define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT0_AFMT_AUDIO_INFO1                                                                       0x2077
+#define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT0_AFMT_60958_0                                                                           0x2078
+#define regAFMT0_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT0_AFMT_60958_1                                                                           0x2079
+#define regAFMT0_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT0_AFMT_AUDIO_CRC_CONTROL                                                                 0x207a
+#define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT0_AFMT_RAMP_CONTROL0                                                                     0x207b
+#define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT0_AFMT_RAMP_CONTROL1                                                                     0x207c
+#define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT0_AFMT_RAMP_CONTROL2                                                                     0x207d
+#define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT0_AFMT_RAMP_CONTROL3                                                                     0x207e
+#define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT0_AFMT_60958_2                                                                           0x207f
+#define regAFMT0_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT0_AFMT_AUDIO_CRC_RESULT                                                                  0x2080
+#define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT0_AFMT_STATUS                                                                            0x2081
+#define regAFMT0_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL                                                              0x2082
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT0_AFMT_INFOFRAME_CONTROL0                                                                0x2083
+#define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT0_AFMT_INTERRUPT_STATUS                                                                  0x2084
+#define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT0_AFMT_AUDIO_SRC_CONTROL                                                                 0x2085
+#define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT0_AFMT_MEM_PWR                                                                           0x2087
+#define regAFMT0_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dio_dig1_afmt_afmt_dispdec
+// base address: 0x158cc
+#define regAFMT1_AFMT_VBI_PACKET_CONTROL                                                                0x2174
+#define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2175
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT1_AFMT_AUDIO_INFO0                                                                       0x2176
+#define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT1_AFMT_AUDIO_INFO1                                                                       0x2177
+#define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT1_AFMT_60958_0                                                                           0x2178
+#define regAFMT1_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT1_AFMT_60958_1                                                                           0x2179
+#define regAFMT1_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT1_AFMT_AUDIO_CRC_CONTROL                                                                 0x217a
+#define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT1_AFMT_RAMP_CONTROL0                                                                     0x217b
+#define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT1_AFMT_RAMP_CONTROL1                                                                     0x217c
+#define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT1_AFMT_RAMP_CONTROL2                                                                     0x217d
+#define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT1_AFMT_RAMP_CONTROL3                                                                     0x217e
+#define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT1_AFMT_60958_2                                                                           0x217f
+#define regAFMT1_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT1_AFMT_AUDIO_CRC_RESULT                                                                  0x2180
+#define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT1_AFMT_STATUS                                                                            0x2181
+#define regAFMT1_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL                                                              0x2182
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT1_AFMT_INFOFRAME_CONTROL0                                                                0x2183
+#define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT1_AFMT_INTERRUPT_STATUS                                                                  0x2184
+#define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT1_AFMT_AUDIO_SRC_CONTROL                                                                 0x2185
+#define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT1_AFMT_MEM_PWR                                                                           0x2187
+#define regAFMT1_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dio_dig2_afmt_afmt_dispdec
+// base address: 0x15ccc
+#define regAFMT2_AFMT_VBI_PACKET_CONTROL                                                                0x2274
+#define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2275
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT2_AFMT_AUDIO_INFO0                                                                       0x2276
+#define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT2_AFMT_AUDIO_INFO1                                                                       0x2277
+#define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT2_AFMT_60958_0                                                                           0x2278
+#define regAFMT2_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT2_AFMT_60958_1                                                                           0x2279
+#define regAFMT2_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT2_AFMT_AUDIO_CRC_CONTROL                                                                 0x227a
+#define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT2_AFMT_RAMP_CONTROL0                                                                     0x227b
+#define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT2_AFMT_RAMP_CONTROL1                                                                     0x227c
+#define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT2_AFMT_RAMP_CONTROL2                                                                     0x227d
+#define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT2_AFMT_RAMP_CONTROL3                                                                     0x227e
+#define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT2_AFMT_60958_2                                                                           0x227f
+#define regAFMT2_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT2_AFMT_AUDIO_CRC_RESULT                                                                  0x2280
+#define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT2_AFMT_STATUS                                                                            0x2281
+#define regAFMT2_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL                                                              0x2282
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT2_AFMT_INFOFRAME_CONTROL0                                                                0x2283
+#define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT2_AFMT_INTERRUPT_STATUS                                                                  0x2284
+#define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT2_AFMT_AUDIO_SRC_CONTROL                                                                 0x2285
+#define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT2_AFMT_MEM_PWR                                                                           0x2287
+#define regAFMT2_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dio_dig3_afmt_afmt_dispdec
+// base address: 0x160cc
+#define regAFMT3_AFMT_VBI_PACKET_CONTROL                                                                0x2374
+#define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2375
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT3_AFMT_AUDIO_INFO0                                                                       0x2376
+#define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT3_AFMT_AUDIO_INFO1                                                                       0x2377
+#define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT3_AFMT_60958_0                                                                           0x2378
+#define regAFMT3_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT3_AFMT_60958_1                                                                           0x2379
+#define regAFMT3_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT3_AFMT_AUDIO_CRC_CONTROL                                                                 0x237a
+#define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT3_AFMT_RAMP_CONTROL0                                                                     0x237b
+#define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT3_AFMT_RAMP_CONTROL1                                                                     0x237c
+#define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT3_AFMT_RAMP_CONTROL2                                                                     0x237d
+#define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT3_AFMT_RAMP_CONTROL3                                                                     0x237e
+#define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT3_AFMT_60958_2                                                                           0x237f
+#define regAFMT3_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT3_AFMT_AUDIO_CRC_RESULT                                                                  0x2380
+#define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT3_AFMT_STATUS                                                                            0x2381
+#define regAFMT3_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL                                                              0x2382
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT3_AFMT_INFOFRAME_CONTROL0                                                                0x2383
+#define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT3_AFMT_INTERRUPT_STATUS                                                                  0x2384
+#define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT3_AFMT_AUDIO_SRC_CONTROL                                                                 0x2385
+#define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT3_AFMT_MEM_PWR                                                                           0x2387
+#define regAFMT3_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dio_dig4_afmt_afmt_dispdec
+// base address: 0x164cc
+#define regAFMT4_AFMT_VBI_PACKET_CONTROL                                                                0x2474
+#define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2475
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT4_AFMT_AUDIO_INFO0                                                                       0x2476
+#define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT4_AFMT_AUDIO_INFO1                                                                       0x2477
+#define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT4_AFMT_60958_0                                                                           0x2478
+#define regAFMT4_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT4_AFMT_60958_1                                                                           0x2479
+#define regAFMT4_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT4_AFMT_AUDIO_CRC_CONTROL                                                                 0x247a
+#define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT4_AFMT_RAMP_CONTROL0                                                                     0x247b
+#define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT4_AFMT_RAMP_CONTROL1                                                                     0x247c
+#define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT4_AFMT_RAMP_CONTROL2                                                                     0x247d
+#define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT4_AFMT_RAMP_CONTROL3                                                                     0x247e
+#define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT4_AFMT_60958_2                                                                           0x247f
+#define regAFMT4_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT4_AFMT_AUDIO_CRC_RESULT                                                                  0x2480
+#define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT4_AFMT_STATUS                                                                            0x2481
+#define regAFMT4_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL                                                              0x2482
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT4_AFMT_INFOFRAME_CONTROL0                                                                0x2483
+#define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT4_AFMT_INTERRUPT_STATUS                                                                  0x2484
+#define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT4_AFMT_AUDIO_SRC_CONTROL                                                                 0x2485
+#define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT4_AFMT_MEM_PWR                                                                           0x2487
+#define regAFMT4_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dio_dig0_dme_dme_dispdec
+// base address: 0x15524
+#define regDME0_DME_CONTROL                                                                             0x2089
+#define regDME0_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME0_DME_MEMORY_CONTROL                                                                      0x208a
+#define regDME0_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_dio_dig0_vpg_vpg_dispdec
+// base address: 0x154a0
+#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2068
+#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG0_VPG_GENERIC_PACKET_DATA                                                                 0x2069
+#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x206a
+#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x206b
+#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG0_VPG_GENERIC_STATUS                                                                      0x206c
+#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG0_VPG_MEM_PWR                                                                             0x206d
+#define regVPG0_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x206e
+#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG0_VPG_ISRC1_2_DATA                                                                        0x206f
+#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG0_VPG_MPEG_INFO0                                                                          0x2070
+#define regVPG0_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG0_VPG_MPEG_INFO1                                                                          0x2071
+#define regVPG0_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dcn_dc_dio_dig1_dme_dme_dispdec
+// base address: 0x15924
+#define regDME1_DME_CONTROL                                                                             0x2189
+#define regDME1_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME1_DME_MEMORY_CONTROL                                                                      0x218a
+#define regDME1_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_dio_dig1_vpg_vpg_dispdec
+// base address: 0x158a0
+#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2168
+#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG1_VPG_GENERIC_PACKET_DATA                                                                 0x2169
+#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x216a
+#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x216b
+#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG1_VPG_GENERIC_STATUS                                                                      0x216c
+#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG1_VPG_MEM_PWR                                                                             0x216d
+#define regVPG1_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x216e
+#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG1_VPG_ISRC1_2_DATA                                                                        0x216f
+#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG1_VPG_MPEG_INFO0                                                                          0x2170
+#define regVPG1_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG1_VPG_MPEG_INFO1                                                                          0x2171
+#define regVPG1_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dcn_dc_dio_dig2_dme_dme_dispdec
+// base address: 0x15d24
+#define regDME2_DME_CONTROL                                                                             0x2289
+#define regDME2_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME2_DME_MEMORY_CONTROL                                                                      0x228a
+#define regDME2_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_dio_dig2_vpg_vpg_dispdec
+// base address: 0x15ca0
+#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2268
+#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG2_VPG_GENERIC_PACKET_DATA                                                                 0x2269
+#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x226a
+#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x226b
+#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG2_VPG_GENERIC_STATUS                                                                      0x226c
+#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG2_VPG_MEM_PWR                                                                             0x226d
+#define regVPG2_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x226e
+#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG2_VPG_ISRC1_2_DATA                                                                        0x226f
+#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG2_VPG_MPEG_INFO0                                                                          0x2270
+#define regVPG2_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG2_VPG_MPEG_INFO1                                                                          0x2271
+#define regVPG2_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dcn_dc_dio_dig3_dme_dme_dispdec
+// base address: 0x16124
+#define regDME3_DME_CONTROL                                                                             0x2389
+#define regDME3_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME3_DME_MEMORY_CONTROL                                                                      0x238a
+#define regDME3_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_dio_dig3_vpg_vpg_dispdec
+// base address: 0x160a0
+#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2368
+#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG3_VPG_GENERIC_PACKET_DATA                                                                 0x2369
+#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x236a
+#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x236b
+#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG3_VPG_GENERIC_STATUS                                                                      0x236c
+#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG3_VPG_MEM_PWR                                                                             0x236d
+#define regVPG3_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x236e
+#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG3_VPG_ISRC1_2_DATA                                                                        0x236f
+#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG3_VPG_MPEG_INFO0                                                                          0x2370
+#define regVPG3_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG3_VPG_MPEG_INFO1                                                                          0x2371
+#define regVPG3_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dcn_dc_dio_dig4_dme_dme_dispdec
+// base address: 0x16524
+#define regDME4_DME_CONTROL                                                                             0x2489
+#define regDME4_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME4_DME_MEMORY_CONTROL                                                                      0x248a
+#define regDME4_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_dio_dig4_vpg_vpg_dispdec
+// base address: 0x164a0
+#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2468
+#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG4_VPG_GENERIC_PACKET_DATA                                                                 0x2469
+#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x246a
+#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x246b
+#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG4_VPG_GENERIC_STATUS                                                                      0x246c
+#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG4_VPG_MEM_PWR                                                                             0x246d
+#define regVPG4_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x246e
+#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG4_VPG_ISRC1_2_DATA                                                                        0x246f
+#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG4_VPG_MPEG_INFO0                                                                          0x2470
+#define regVPG4_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG4_VPG_MPEG_INFO1                                                                          0x2471
+#define regVPG4_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dcn_dc_dio_dp_aux0_dispdec
+// base address: 0x0
+#define regDP_AUX0_AUX_CONTROL                                                                          0x1f50
+#define regDP_AUX0_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX0_AUX_SW_CONTROL                                                                       0x1f51
+#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX0_AUX_ARB_CONTROL                                                                      0x1f52
+#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX0_AUX_INTERRUPT_CONTROL                                                                0x1f53
+#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX0_AUX_SW_STATUS                                                                        0x1f54
+#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX0_AUX_LS_STATUS                                                                        0x1f55
+#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX0_AUX_SW_DATA                                                                          0x1f56
+#define regDP_AUX0_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX0_AUX_LS_DATA                                                                          0x1f57
+#define regDP_AUX0_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                                              0x1f58
+#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX0_AUX_DPHY_TX_CONTROL                                                                  0x1f59
+#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL0                                                                 0x1f5a
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL1                                                                 0x1f5b
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX0_AUX_DPHY_TX_STATUS                                                                   0x1f5c
+#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX0_AUX_DPHY_RX_STATUS                                                                   0x1f5d
+#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROL                                                                 0x1f5e
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f5f
+#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f60
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX0_AUX_GTC_SYNC_STATUS                                                                  0x1f61
+#define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX0_AUX_PHY_WAKE_CNTL                                                                    0x1f66
+#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dcn_dc_dio_dp_aux1_dispdec
+// base address: 0x70
+#define regDP_AUX1_AUX_CONTROL                                                                          0x1f6c
+#define regDP_AUX1_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX1_AUX_SW_CONTROL                                                                       0x1f6d
+#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX1_AUX_ARB_CONTROL                                                                      0x1f6e
+#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX1_AUX_INTERRUPT_CONTROL                                                                0x1f6f
+#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX1_AUX_SW_STATUS                                                                        0x1f70
+#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX1_AUX_LS_STATUS                                                                        0x1f71
+#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX1_AUX_SW_DATA                                                                          0x1f72
+#define regDP_AUX1_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX1_AUX_LS_DATA                                                                          0x1f73
+#define regDP_AUX1_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                                              0x1f74
+#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX1_AUX_DPHY_TX_CONTROL                                                                  0x1f75
+#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL0                                                                 0x1f76
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL1                                                                 0x1f77
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX1_AUX_DPHY_TX_STATUS                                                                   0x1f78
+#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX1_AUX_DPHY_RX_STATUS                                                                   0x1f79
+#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROL                                                                 0x1f7a
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f7b
+#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f7c
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX1_AUX_GTC_SYNC_STATUS                                                                  0x1f7d
+#define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX1_AUX_PHY_WAKE_CNTL                                                                    0x1f82
+#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dcn_dc_dio_dp_aux2_dispdec
+// base address: 0xe0
+#define regDP_AUX2_AUX_CONTROL                                                                          0x1f88
+#define regDP_AUX2_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX2_AUX_SW_CONTROL                                                                       0x1f89
+#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX2_AUX_ARB_CONTROL                                                                      0x1f8a
+#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX2_AUX_INTERRUPT_CONTROL                                                                0x1f8b
+#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX2_AUX_SW_STATUS                                                                        0x1f8c
+#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX2_AUX_LS_STATUS                                                                        0x1f8d
+#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX2_AUX_SW_DATA                                                                          0x1f8e
+#define regDP_AUX2_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX2_AUX_LS_DATA                                                                          0x1f8f
+#define regDP_AUX2_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                                              0x1f90
+#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX2_AUX_DPHY_TX_CONTROL                                                                  0x1f91
+#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL0                                                                 0x1f92
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL1                                                                 0x1f93
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX2_AUX_DPHY_TX_STATUS                                                                   0x1f94
+#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX2_AUX_DPHY_RX_STATUS                                                                   0x1f95
+#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROL                                                                 0x1f96
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f97
+#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f98
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX2_AUX_GTC_SYNC_STATUS                                                                  0x1f99
+#define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX2_AUX_PHY_WAKE_CNTL                                                                    0x1f9e
+#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dcn_dc_dio_dp_aux3_dispdec
+// base address: 0x150
+#define regDP_AUX3_AUX_CONTROL                                                                          0x1fa4
+#define regDP_AUX3_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX3_AUX_SW_CONTROL                                                                       0x1fa5
+#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX3_AUX_ARB_CONTROL                                                                      0x1fa6
+#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX3_AUX_INTERRUPT_CONTROL                                                                0x1fa7
+#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX3_AUX_SW_STATUS                                                                        0x1fa8
+#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX3_AUX_LS_STATUS                                                                        0x1fa9
+#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX3_AUX_SW_DATA                                                                          0x1faa
+#define regDP_AUX3_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX3_AUX_LS_DATA                                                                          0x1fab
+#define regDP_AUX3_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                                              0x1fac
+#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX3_AUX_DPHY_TX_CONTROL                                                                  0x1fad
+#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL0                                                                 0x1fae
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL1                                                                 0x1faf
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX3_AUX_DPHY_TX_STATUS                                                                   0x1fb0
+#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX3_AUX_DPHY_RX_STATUS                                                                   0x1fb1
+#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROL                                                                 0x1fb2
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fb3
+#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fb4
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX3_AUX_GTC_SYNC_STATUS                                                                  0x1fb5
+#define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX3_AUX_PHY_WAKE_CNTL                                                                    0x1fba
+#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dcn_dc_dio_dp_aux4_dispdec
+// base address: 0x1c0
+#define regDP_AUX4_AUX_CONTROL                                                                          0x1fc0
+#define regDP_AUX4_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX4_AUX_SW_CONTROL                                                                       0x1fc1
+#define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX4_AUX_ARB_CONTROL                                                                      0x1fc2
+#define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX4_AUX_INTERRUPT_CONTROL                                                                0x1fc3
+#define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX4_AUX_SW_STATUS                                                                        0x1fc4
+#define regDP_AUX4_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX4_AUX_LS_STATUS                                                                        0x1fc5
+#define regDP_AUX4_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX4_AUX_SW_DATA                                                                          0x1fc6
+#define regDP_AUX4_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX4_AUX_LS_DATA                                                                          0x1fc7
+#define regDP_AUX4_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL                                                              0x1fc8
+#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX4_AUX_DPHY_TX_CONTROL                                                                  0x1fc9
+#define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL0                                                                 0x1fca
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL1                                                                 0x1fcb
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX4_AUX_DPHY_TX_STATUS                                                                   0x1fcc
+#define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX4_AUX_DPHY_RX_STATUS                                                                   0x1fcd
+#define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROL                                                                 0x1fce
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fcf
+#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fd0
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX4_AUX_GTC_SYNC_STATUS                                                                  0x1fd1
+#define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX4_AUX_PHY_WAKE_CNTL                                                                    0x1fd6
+#define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dcn_dc_dio_dout_i2c_dispdec
+// base address: 0x0
+#define regDC_I2C_CONTROL                                                                               0x1e98
+#define regDC_I2C_CONTROL_BASE_IDX                                                                      2
+#define regDC_I2C_ARBITRATION                                                                           0x1e99
+#define regDC_I2C_ARBITRATION_BASE_IDX                                                                  2
+#define regDC_I2C_INTERRUPT_CONTROL                                                                     0x1e9a
+#define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX                                                            2
+#define regDC_I2C_SW_STATUS                                                                             0x1e9b
+#define regDC_I2C_SW_STATUS_BASE_IDX                                                                    2
+#define regDC_I2C_DDC1_HW_STATUS                                                                        0x1e9c
+#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC2_HW_STATUS                                                                        0x1e9d
+#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC3_HW_STATUS                                                                        0x1e9e
+#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC4_HW_STATUS                                                                        0x1e9f
+#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC5_HW_STATUS                                                                        0x1ea0
+#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC1_SPEED                                                                            0x1ea2
+#define regDC_I2C_DDC1_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC1_SETUP                                                                            0x1ea3
+#define regDC_I2C_DDC1_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC2_SPEED                                                                            0x1ea4
+#define regDC_I2C_DDC2_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC2_SETUP                                                                            0x1ea5
+#define regDC_I2C_DDC2_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC3_SPEED                                                                            0x1ea6
+#define regDC_I2C_DDC3_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC3_SETUP                                                                            0x1ea7
+#define regDC_I2C_DDC3_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC4_SPEED                                                                            0x1ea8
+#define regDC_I2C_DDC4_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC4_SETUP                                                                            0x1ea9
+#define regDC_I2C_DDC4_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC5_SPEED                                                                            0x1eaa
+#define regDC_I2C_DDC5_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC5_SETUP                                                                            0x1eab
+#define regDC_I2C_DDC5_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_TRANSACTION0                                                                          0x1eae
+#define regDC_I2C_TRANSACTION0_BASE_IDX                                                                 2
+#define regDC_I2C_TRANSACTION1                                                                          0x1eaf
+#define regDC_I2C_TRANSACTION1_BASE_IDX                                                                 2
+#define regDC_I2C_TRANSACTION2                                                                          0x1eb0
+#define regDC_I2C_TRANSACTION2_BASE_IDX                                                                 2
+#define regDC_I2C_TRANSACTION3                                                                          0x1eb1
+#define regDC_I2C_TRANSACTION3_BASE_IDX                                                                 2
+#define regDC_I2C_DATA                                                                                  0x1eb2
+#define regDC_I2C_DATA_BASE_IDX                                                                         2
+#define regDC_I2C_EDID_DETECT_CTRL                                                                      0x1eb6
+#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX                                                             2
+#define regDC_I2C_READ_REQUEST_INTERRUPT                                                                0x1eb7
+#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX                                                       2
+
+
+// addressBlock: dcn_dc_dio_dio_misc_dispdec
+// base address: 0x0
+#define regDIO_SCRATCH0                                                                                 0x1eca
+#define regDIO_SCRATCH0_BASE_IDX                                                                        2
+#define regDIO_SCRATCH1                                                                                 0x1ecb
+#define regDIO_SCRATCH1_BASE_IDX                                                                        2
+#define regDIO_SCRATCH2                                                                                 0x1ecc
+#define regDIO_SCRATCH2_BASE_IDX                                                                        2
+#define regDIO_SCRATCH3                                                                                 0x1ecd
+#define regDIO_SCRATCH3_BASE_IDX                                                                        2
+#define regDIO_SCRATCH4                                                                                 0x1ece
+#define regDIO_SCRATCH4_BASE_IDX                                                                        2
+#define regDIO_SCRATCH5                                                                                 0x1ecf
+#define regDIO_SCRATCH5_BASE_IDX                                                                        2
+#define regDIO_SCRATCH6                                                                                 0x1ed0
+#define regDIO_SCRATCH6_BASE_IDX                                                                        2
+#define regDIO_SCRATCH7                                                                                 0x1ed1
+#define regDIO_SCRATCH7_BASE_IDX                                                                        2
+#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS                                                          0x1ed3
+#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS_BASE_IDX                                                 2
+#define regDIO_MEM_PWR_STATUS                                                                           0x1edd
+#define regDIO_MEM_PWR_STATUS_BASE_IDX                                                                  2
+#define regDIO_MEM_PWR_CTRL                                                                             0x1ede
+#define regDIO_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define regDIO_MEM_PWR_CTRL2                                                                            0x1edf
+#define regDIO_MEM_PWR_CTRL2_BASE_IDX                                                                   2
+#define regDIO_CLK_CNTL                                                                                 0x1ee0
+#define regDIO_CLK_CNTL_BASE_IDX                                                                        2
+#define regDIO_POWER_MANAGEMENT_CNTL                                                                    0x1ee4
+#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX                                                           2
+#define regDIG_SOFT_RESET                                                                               0x1eee
+#define regDIG_SOFT_RESET_BASE_IDX                                                                      2
+#define regDIO_CLK_CNTL2                                                                                0x1ef2
+#define regDIO_CLK_CNTL2_BASE_IDX                                                                       2
+#define regDIO_CLK_CNTL3                                                                                0x1ef3
+#define regDIO_CLK_CNTL3_BASE_IDX                                                                       2
+#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL                                                              0x1eff
+#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX                                                     2
+#define regDIO_LINKA_CNTL                                                                               0x1f04
+#define regDIO_LINKA_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKB_CNTL                                                                               0x1f05
+#define regDIO_LINKB_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKC_CNTL                                                                               0x1f06
+#define regDIO_LINKC_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKD_CNTL                                                                               0x1f07
+#define regDIO_LINKD_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKE_CNTL                                                                               0x1f08
+#define regDIO_LINKE_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKF_CNTL                                                                               0x1f09
+#define regDIO_LINKF_CNTL_BASE_IDX                                                                      2
+
+
+// addressBlock: dcn_dc_dcio_dcio_dispdec
+// base address: 0x0
+#define regDC_GENERICA                                                                                  0x2868
+#define regDC_GENERICA_BASE_IDX                                                                         2
+#define regDC_GENERICB                                                                                  0x2869
+#define regDC_GENERICB_BASE_IDX                                                                         2
+#define regDCIO_CLOCK_CNTL                                                                              0x286a
+#define regDCIO_CLOCK_CNTL_BASE_IDX                                                                     2
+#define regDC_REF_CLK_CNTL                                                                              0x286b
+#define regDC_REF_CLK_CNTL_BASE_IDX                                                                     2
+#define regUNIPHYA_CHANNEL_XBAR_CNTL                                                                    0x286e
+#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYB_CHANNEL_XBAR_CNTL                                                                    0x2870
+#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYC_CHANNEL_XBAR_CNTL                                                                    0x2872
+#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYD_CHANNEL_XBAR_CNTL                                                                    0x2874
+#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYE_CHANNEL_XBAR_CNTL                                                                    0x2876
+#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regDCIO_WRCMD_DELAY                                                                             0x287e
+#define regDCIO_WRCMD_DELAY_BASE_IDX                                                                    2
+#define regDC_PINSTRAPS                                                                                 0x2880
+#define regDC_PINSTRAPS_BASE_IDX                                                                        2
+#define regDCIO_SPARE                                                                                   0x2882
+#define regDCIO_SPARE_BASE_IDX                                                                          2
+#define regINTERCEPT_STATE                                                                              0x2884
+#define regINTERCEPT_STATE_BASE_IDX                                                                     2
+#define regDCIO_PATTERN_GEN_PAT                                                                         0x2886
+#define regDCIO_PATTERN_GEN_PAT_BASE_IDX                                                                2
+#define regDCIO_PATTERN_GEN_EN                                                                          0x2887
+#define regDCIO_PATTERN_GEN_EN_BASE_IDX                                                                 2
+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL                                                             0x288b
+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX                                                    2
+#define regDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c
+#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2
+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL                                                                   0x288d
+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX                                                          2
+#define regDCIO_SOFT_RESET                                                                              0x289e
+#define regDCIO_SOFT_RESET_BASE_IDX                                                                     2
+
+
+// addressBlock: dcn_dc_dcio_dcio_chip_dispdec
+// base address: 0x0
+#define regDC_GPIO_GENERIC_MASK                                                                         0x28c8
+#define regDC_GPIO_GENERIC_MASK_BASE_IDX                                                                2
+#define regDC_GPIO_GENERIC_A                                                                            0x28c9
+#define regDC_GPIO_GENERIC_A_BASE_IDX                                                                   2
+#define regDC_GPIO_GENERIC_EN                                                                           0x28ca
+#define regDC_GPIO_GENERIC_EN_BASE_IDX                                                                  2
+#define regDC_GPIO_GENERIC_Y                                                                            0x28cb
+#define regDC_GPIO_GENERIC_Y_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC1_MASK                                                                            0x28d0
+#define regDC_GPIO_DDC1_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC1_A                                                                               0x28d1
+#define regDC_GPIO_DDC1_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC1_EN                                                                              0x28d2
+#define regDC_GPIO_DDC1_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC1_Y                                                                               0x28d3
+#define regDC_GPIO_DDC1_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC2_MASK                                                                            0x28d4
+#define regDC_GPIO_DDC2_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC2_A                                                                               0x28d5
+#define regDC_GPIO_DDC2_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC2_EN                                                                              0x28d6
+#define regDC_GPIO_DDC2_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC2_Y                                                                               0x28d7
+#define regDC_GPIO_DDC2_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC3_MASK                                                                            0x28d8
+#define regDC_GPIO_DDC3_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC3_A                                                                               0x28d9
+#define regDC_GPIO_DDC3_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC3_EN                                                                              0x28da
+#define regDC_GPIO_DDC3_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC3_Y                                                                               0x28db
+#define regDC_GPIO_DDC3_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC4_MASK                                                                            0x28dc
+#define regDC_GPIO_DDC4_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC4_A                                                                               0x28dd
+#define regDC_GPIO_DDC4_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC4_EN                                                                              0x28de
+#define regDC_GPIO_DDC4_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC4_Y                                                                               0x28df
+#define regDC_GPIO_DDC4_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC5_MASK                                                                            0x28e0
+#define regDC_GPIO_DDC5_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC5_A                                                                               0x28e1
+#define regDC_GPIO_DDC5_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC5_EN                                                                              0x28e2
+#define regDC_GPIO_DDC5_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC5_Y                                                                               0x28e3
+#define regDC_GPIO_DDC5_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDCVGA_MASK                                                                          0x28e8
+#define regDC_GPIO_DDCVGA_MASK_BASE_IDX                                                                 2
+#define regDC_GPIO_DDCVGA_A                                                                             0x28e9
+#define regDC_GPIO_DDCVGA_A_BASE_IDX                                                                    2
+#define regDC_GPIO_DDCVGA_EN                                                                            0x28ea
+#define regDC_GPIO_DDCVGA_EN_BASE_IDX                                                                   2
+#define regDC_GPIO_DDCVGA_Y                                                                             0x28eb
+#define regDC_GPIO_DDCVGA_Y_BASE_IDX                                                                    2
+#define regDC_GPIO_GENLK_MASK                                                                           0x28f0
+#define regDC_GPIO_GENLK_MASK_BASE_IDX                                                                  2
+#define regDC_GPIO_GENLK_A                                                                              0x28f1
+#define regDC_GPIO_GENLK_A_BASE_IDX                                                                     2
+#define regDC_GPIO_GENLK_EN                                                                             0x28f2
+#define regDC_GPIO_GENLK_EN_BASE_IDX                                                                    2
+#define regDC_GPIO_GENLK_Y                                                                              0x28f3
+#define regDC_GPIO_GENLK_Y_BASE_IDX                                                                     2
+#define regDC_GPIO_HPD_MASK                                                                             0x28f4
+#define regDC_GPIO_HPD_MASK_BASE_IDX                                                                    2
+#define regDC_GPIO_HPD_A                                                                                0x28f5
+#define regDC_GPIO_HPD_A_BASE_IDX                                                                       2
+#define regDC_GPIO_HPD_EN                                                                               0x28f6
+#define regDC_GPIO_HPD_EN_BASE_IDX                                                                      2
+#define regDC_GPIO_HPD_Y                                                                                0x28f7
+#define regDC_GPIO_HPD_Y_BASE_IDX                                                                       2
+#define regDC_GPIO_DRIVE_STRENGTH_S0                                                                    0x28f8
+#define regDC_GPIO_DRIVE_STRENGTH_S0_BASE_IDX                                                           2
+#define regDC_GPIO_DRIVE_STRENGTH_S1                                                                    0x28f9
+#define regDC_GPIO_DRIVE_STRENGTH_S1_BASE_IDX                                                           2
+#define regDC_GPIO_PWRSEQ0_EN                                                                           0x28fa
+#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX                                                                  2
+#define regDC_GPIO_PAD_STRENGTH_1                                                                       0x28fc
+#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX                                                              2
+#define regDC_GPIO_PAD_STRENGTH_2                                                                       0x28fd
+#define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX                                                              2
+#define regPHY_AUX_CNTL                                                                                 0x28ff
+#define regPHY_AUX_CNTL_BASE_IDX                                                                        2
+#define regDC_GPIO_DRIVE_TXIMPSEL                                                                       0x2900
+#define regDC_GPIO_DRIVE_TXIMPSEL_BASE_IDX                                                              2
+#define regDC_GPIO_TX12_EN                                                                              0x2915
+#define regDC_GPIO_TX12_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_AUX_CTRL_0                                                                           0x2916
+#define regDC_GPIO_AUX_CTRL_0_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_1                                                                           0x2917
+#define regDC_GPIO_AUX_CTRL_1_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_2                                                                           0x2918
+#define regDC_GPIO_AUX_CTRL_2_BASE_IDX                                                                  2
+#define regDC_GPIO_RXEN                                                                                 0x2919
+#define regDC_GPIO_RXEN_BASE_IDX                                                                        2
+#define regDC_GPIO_PULLUPEN                                                                             0x291a
+#define regDC_GPIO_PULLUPEN_BASE_IDX                                                                    2
+#define regDC_GPIO_AUX_CTRL_3                                                                           0x291b
+#define regDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_4                                                                           0x291c
+#define regDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_5                                                                           0x291d
+#define regDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2
+#define regAUXI2C_PAD_ALL_PWR_OK                                                                        0x291e
+#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2
+
+
+// addressBlock: dcn_dc_dcio_dcio_uniphy0_dispdec
+// base address: 0x0
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2928
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2929
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x292a
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x292b
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x292c
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x292d
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x292e
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x292f
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2930
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2931
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2932
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2933
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2934
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2935
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2936
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2937
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2938
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2939
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x293a
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x293b
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x293c
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x293d
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x293e
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x293f
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2940
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2941
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2942
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2943
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2944
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2945
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2946
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2947
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2948
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2949
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x294a
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x294b
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x294c
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x294d
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x294e
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x294f
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2950
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2951
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2952
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2953
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2954
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2955
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2956
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2957
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2958
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2959
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x295a
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x295b
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x295c
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x295d
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x295e
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x295f
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2960
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2961
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dcn_dc_dcio_dcio_uniphy1_dispdec
+// base address: 0x360
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2a00
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2a01
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2a02
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2a03
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2a04
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2a05
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2a06
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2a07
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2a08
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2a09
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2a0a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2a0b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2a0c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2a0d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2a0e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2a0f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2a10
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2a11
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2a12
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2a13
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2a14
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2a15
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2a16
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2a17
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2a18
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2a19
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2a1a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2a1b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2a1c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2a1d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2a1e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2a1f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2a20
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2a21
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2a22
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2a23
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2a24
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2a25
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2a26
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2a27
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2a28
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2a29
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2a2a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2a2b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2a2c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2a2d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2a2e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2a2f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2a30
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2a31
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2a32
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2a33
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2a34
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2a35
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2a36
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2a37
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2a38
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2a39
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dcn_dc_dcio_dcio_uniphy2_dispdec
+// base address: 0x6c0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2ad8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2ad9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2ada
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2adb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2adc
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2add
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2ade
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2adf
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2ae0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2ae1
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2ae2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2ae3
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2ae4
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2ae5
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2ae6
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2ae7
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2ae8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2ae9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2aea
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2aeb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2aec
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2aed
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2aee
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2aef
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2af0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2af1
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2af2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2af3
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2af4
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2af5
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2af6
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2af7
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2af8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2af9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2afa
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2afb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2afc
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2afd
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2afe
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2aff
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2b00
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2b01
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2b02
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2b03
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2b04
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2b05
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2b06
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2b07
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2b08
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2b09
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2b0a
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2b0b
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2b0c
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2b0d
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2b0e
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2b0f
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2b10
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2b11
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dcn_dc_dcio_dcio_uniphy3_dispdec
+// base address: 0xa20
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2bb0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2bb1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2bb2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2bb3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2bb4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2bb5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2bb6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2bb7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2bb8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2bb9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2bba
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2bbb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2bbc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2bbd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2bbe
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2bbf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2bc0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2bc1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2bc2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2bc3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2bc4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2bc5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2bc6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2bc7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2bc8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2bc9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2bca
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2bcb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2bcc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2bcd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2bce
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2bcf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2bd0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2bd1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2bd2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2bd3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2bd4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2bd5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2bd6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2bd7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2bd8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2bd9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2bda
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2bdb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2bdc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2bdd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2bde
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2bdf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2be0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2be1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2be2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2be3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2be4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2be5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2be6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2be7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2be8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2be9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dcn_dc_dcio_dcio_uniphy4_dispdec
+// base address: 0xd80
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2c88
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2c89
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2c8a
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2c8b
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2c8c
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2c8d
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2c8e
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2c8f
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2c90
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2c91
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2c92
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2c93
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2c94
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2c95
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2c96
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2c97
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2c98
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2c99
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2c9a
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2c9b
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2c9c
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2c9d
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2c9e
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2c9f
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2ca0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2ca1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2ca2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2ca3
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2ca4
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2ca5
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2ca6
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2ca7
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2ca8
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2ca9
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2caa
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2cab
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2cac
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2cad
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2cae
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2caf
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2cb0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2cb1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2cb2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2cb3
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2cb4
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2cb5
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2cb6
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2cb7
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2cb8
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2cb9
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2cba
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2cbb
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2cbc
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2cbd
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2cbe
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2cbf
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2cc0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2cc1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dcn_dc_pwrseq0_dispdec_pwrseq_dispdec
+// base address: 0x0
+#define regDC_GPIO_PWRSEQ_EN                                                                            0x2f10
+#define regDC_GPIO_PWRSEQ_EN_BASE_IDX                                                                   2
+#define regDC_GPIO_PWRSEQ_CTRL                                                                          0x2f11
+#define regDC_GPIO_PWRSEQ_CTRL_BASE_IDX                                                                 2
+#define regDC_GPIO_PWRSEQ_MASK                                                                          0x2f12
+#define regDC_GPIO_PWRSEQ_MASK_BASE_IDX                                                                 2
+#define regDC_GPIO_PWRSEQ_A_Y                                                                           0x2f13
+#define regDC_GPIO_PWRSEQ_A_Y_BASE_IDX                                                                  2
+#define regPANEL_PWRSEQ_CNTL                                                                            0x2f14
+#define regPANEL_PWRSEQ_CNTL_BASE_IDX                                                                   2
+#define regPANEL_PWRSEQ_STATE                                                                           0x2f15
+#define regPANEL_PWRSEQ_STATE_BASE_IDX                                                                  2
+#define regPANEL_PWRSEQ_DELAY1                                                                          0x2f16
+#define regPANEL_PWRSEQ_DELAY1_BASE_IDX                                                                 2
+#define regPANEL_PWRSEQ_DELAY2                                                                          0x2f17
+#define regPANEL_PWRSEQ_DELAY2_BASE_IDX                                                                 2
+#define regPANEL_PWRSEQ_REF_DIV1                                                                        0x2f18
+#define regPANEL_PWRSEQ_REF_DIV1_BASE_IDX                                                               2
+#define regBL_PWM_CNTL                                                                                  0x2f19
+#define regBL_PWM_CNTL_BASE_IDX                                                                         2
+#define regBL_PWM_CNTL2                                                                                 0x2f1a
+#define regBL_PWM_CNTL2_BASE_IDX                                                                        2
+#define regBL_PWM_PERIOD_CNTL                                                                           0x2f1b
+#define regBL_PWM_PERIOD_CNTL_BASE_IDX                                                                  2
+#define regBL_PWM_GRP1_REG_LOCK                                                                         0x2f1c
+#define regBL_PWM_GRP1_REG_LOCK_BASE_IDX                                                                2
+#define regPANEL_PWRSEQ_REF_DIV2                                                                        0x2f1d
+#define regPANEL_PWRSEQ_REF_DIV2_BASE_IDX                                                               2
+#define regPWRSEQ_SPARE                                                                                 0x2f21
+#define regPWRSEQ_SPARE_BASE_IDX                                                                        2
+
+
+// addressBlock: dcn_dc_dsc0_dispdec_dscc_dispdec
+// base address: 0x0
+#define regDSCC0_DSCC_CONFIG0                                                                           0x300a
+#define regDSCC0_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC0_DSCC_CONFIG1                                                                           0x300b
+#define regDSCC0_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC0_DSCC_STATUS                                                                            0x300c
+#define regDSCC0_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x300d
+#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC0_DSCC_PPS_CONFIG0                                                                       0x300e
+#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG1                                                                       0x300f
+#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG2                                                                       0x3010
+#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG3                                                                       0x3011
+#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG4                                                                       0x3012
+#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG5                                                                       0x3013
+#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG6                                                                       0x3014
+#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG7                                                                       0x3015
+#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG8                                                                       0x3016
+#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG9                                                                       0x3017
+#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG10                                                                      0x3018
+#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG11                                                                      0x3019
+#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG12                                                                      0x301a
+#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG13                                                                      0x301b
+#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG14                                                                      0x301c
+#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG15                                                                      0x301d
+#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG16                                                                      0x301e
+#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG17                                                                      0x301f
+#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG18                                                                      0x3020
+#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG19                                                                      0x3021
+#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG20                                                                      0x3022
+#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG21                                                                      0x3023
+#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG22                                                                      0x3024
+#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC0_DSCC_MEM_POWER_CONTROL                                                                 0x3025
+#define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3026
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3027
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3028
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3029
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x302a
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x302b
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_MAX_ABS_ERROR0                                                                    0x302c
+#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC0_DSCC_MAX_ABS_ERROR1                                                                    0x302d
+#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x302e
+#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x302f
+#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3030
+#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3031
+#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3032
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3033
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3034
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+
+
+// addressBlock: dcn_dc_dsc0_dispdec_dsccif_dispdec
+// base address: 0x0
+#define regDSCCIF0_DSCCIF_CONFIG0                                                                       0x3005
+#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF0_DSCCIF_CONFIG1                                                                       0x3006
+#define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dsc0_dispdec_dsc_top_dispdec
+// base address: 0x0
+#define regDSC_TOP0_DSC_TOP_CONTROL                                                                     0x3000
+#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP0_DSC_DEBUG_CONTROL                                                                   0x3001
+#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_dsc1_dispdec_dscc_dispdec
+// base address: 0x170
+#define regDSCC1_DSCC_CONFIG0                                                                           0x3066
+#define regDSCC1_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC1_DSCC_CONFIG1                                                                           0x3067
+#define regDSCC1_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC1_DSCC_STATUS                                                                            0x3068
+#define regDSCC1_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3069
+#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC1_DSCC_PPS_CONFIG0                                                                       0x306a
+#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG1                                                                       0x306b
+#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG2                                                                       0x306c
+#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG3                                                                       0x306d
+#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG4                                                                       0x306e
+#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG5                                                                       0x306f
+#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG6                                                                       0x3070
+#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG7                                                                       0x3071
+#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG8                                                                       0x3072
+#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG9                                                                       0x3073
+#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG10                                                                      0x3074
+#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG11                                                                      0x3075
+#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG12                                                                      0x3076
+#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG13                                                                      0x3077
+#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG14                                                                      0x3078
+#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG15                                                                      0x3079
+#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG16                                                                      0x307a
+#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG17                                                                      0x307b
+#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG18                                                                      0x307c
+#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG19                                                                      0x307d
+#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG20                                                                      0x307e
+#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG21                                                                      0x307f
+#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG22                                                                      0x3080
+#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC1_DSCC_MEM_POWER_CONTROL                                                                 0x3081
+#define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3082
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3083
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3084
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3085
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x3086
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x3087
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_MAX_ABS_ERROR0                                                                    0x3088
+#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC1_DSCC_MAX_ABS_ERROR1                                                                    0x3089
+#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x308a
+#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x308b
+#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x308c
+#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x308d
+#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x308e
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x308f
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3090
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+
+
+// addressBlock: dcn_dc_dsc1_dispdec_dsccif_dispdec
+// base address: 0x170
+#define regDSCCIF1_DSCCIF_CONFIG0                                                                       0x3061
+#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF1_DSCCIF_CONFIG1                                                                       0x3062
+#define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dsc1_dispdec_dsc_top_dispdec
+// base address: 0x170
+#define regDSC_TOP1_DSC_TOP_CONTROL                                                                     0x305c
+#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP1_DSC_DEBUG_CONTROL                                                                   0x305d
+#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_dsc2_dispdec_dscc_dispdec
+// base address: 0x2e0
+#define regDSCC2_DSCC_CONFIG0                                                                           0x30c2
+#define regDSCC2_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC2_DSCC_CONFIG1                                                                           0x30c3
+#define regDSCC2_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC2_DSCC_STATUS                                                                            0x30c4
+#define regDSCC2_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x30c5
+#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC2_DSCC_PPS_CONFIG0                                                                       0x30c6
+#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG1                                                                       0x30c7
+#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG2                                                                       0x30c8
+#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG3                                                                       0x30c9
+#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG4                                                                       0x30ca
+#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG5                                                                       0x30cb
+#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG6                                                                       0x30cc
+#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG7                                                                       0x30cd
+#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG8                                                                       0x30ce
+#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG9                                                                       0x30cf
+#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG10                                                                      0x30d0
+#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG11                                                                      0x30d1
+#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG12                                                                      0x30d2
+#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG13                                                                      0x30d3
+#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG14                                                                      0x30d4
+#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG15                                                                      0x30d5
+#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG16                                                                      0x30d6
+#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG17                                                                      0x30d7
+#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG18                                                                      0x30d8
+#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG19                                                                      0x30d9
+#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG20                                                                      0x30da
+#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG21                                                                      0x30db
+#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG22                                                                      0x30dc
+#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC2_DSCC_MEM_POWER_CONTROL                                                                 0x30dd
+#define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x30de
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x30df
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x30e0
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x30e1
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x30e2
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x30e3
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_MAX_ABS_ERROR0                                                                    0x30e4
+#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC2_DSCC_MAX_ABS_ERROR1                                                                    0x30e5
+#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x30e6
+#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x30e7
+#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x30e8
+#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x30e9
+#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x30ea
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x30eb
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x30ec
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x30ed
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+
+
+// addressBlock: dcn_dc_dsc2_dispdec_dsccif_dispdec
+// base address: 0x2e0
+#define regDSCCIF2_DSCCIF_CONFIG0                                                                       0x30bd
+#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF2_DSCCIF_CONFIG1                                                                       0x30be
+#define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dsc2_dispdec_dsc_top_dispdec
+// base address: 0x2e0
+#define regDSC_TOP2_DSC_TOP_CONTROL                                                                     0x30b8
+#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP2_DSC_DEBUG_CONTROL                                                                   0x30b9
+#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_dsc3_dispdec_dscc_dispdec
+// base address: 0x450
+#define regDSCC3_DSCC_CONFIG0                                                                           0x311e
+#define regDSCC3_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC3_DSCC_CONFIG1                                                                           0x311f
+#define regDSCC3_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC3_DSCC_STATUS                                                                            0x3120
+#define regDSCC3_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3121
+#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC3_DSCC_PPS_CONFIG0                                                                       0x3122
+#define regDSCC3_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG1                                                                       0x3123
+#define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG2                                                                       0x3124
+#define regDSCC3_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG3                                                                       0x3125
+#define regDSCC3_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG4                                                                       0x3126
+#define regDSCC3_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG5                                                                       0x3127
+#define regDSCC3_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG6                                                                       0x3128
+#define regDSCC3_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG7                                                                       0x3129
+#define regDSCC3_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG8                                                                       0x312a
+#define regDSCC3_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG9                                                                       0x312b
+#define regDSCC3_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG10                                                                      0x312c
+#define regDSCC3_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG11                                                                      0x312d
+#define regDSCC3_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG12                                                                      0x312e
+#define regDSCC3_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG13                                                                      0x312f
+#define regDSCC3_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG14                                                                      0x3130
+#define regDSCC3_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG15                                                                      0x3131
+#define regDSCC3_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG16                                                                      0x3132
+#define regDSCC3_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG17                                                                      0x3133
+#define regDSCC3_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG18                                                                      0x3134
+#define regDSCC3_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG19                                                                      0x3135
+#define regDSCC3_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG20                                                                      0x3136
+#define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG21                                                                      0x3137
+#define regDSCC3_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG22                                                                      0x3138
+#define regDSCC3_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC3_DSCC_MEM_POWER_CONTROL                                                                 0x3139
+#define regDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x313a
+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x313b
+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x313c
+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x313d
+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x313e
+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x313f
+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC3_DSCC_MAX_ABS_ERROR0                                                                    0x3140
+#define regDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC3_DSCC_MAX_ABS_ERROR1                                                                    0x3141
+#define regDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x3142
+#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x3143
+#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3144
+#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3145
+#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3146
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3147
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3148
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3149
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+
+
+// addressBlock: dcn_dc_dsc3_dispdec_dsccif_dispdec
+// base address: 0x450
+#define regDSCCIF3_DSCCIF_CONFIG0                                                                       0x3119
+#define regDSCCIF3_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF3_DSCCIF_CONFIG1                                                                       0x311a
+#define regDSCCIF3_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dsc3_dispdec_dsc_top_dispdec
+// base address: 0x450
+#define regDSC_TOP3_DSC_TOP_CONTROL                                                                     0x3114
+#define regDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP3_DSC_DEBUG_CONTROL                                                                   0x3115
+#define regDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_hpo_hpo_top_dispdec
+// base address: 0x2790c
+#define regHPO_TOP_CLOCK_CONTROL                                                                        0x0e43
+#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX                                                               3
+#define regHPO_TOP_HW_CONTROL                                                                           0x0e4a
+#define regHPO_TOP_HW_CONTROL_BASE_IDX                                                                  3
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_mapper_dispdec
+// base address: 0x27958
+#define regDP_STREAM_MAPPER_CONTROL0                                                                    0x0e56
+#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX                                                           3
+#define regDP_STREAM_MAPPER_CONTROL1                                                                    0x0e57
+#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX                                                           3
+#define regDP_STREAM_MAPPER_CONTROL2                                                                    0x0e58
+#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX                                                           3
+#define regDP_STREAM_MAPPER_CONTROL3                                                                    0x0e59
+#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX                                                           3
+
+
+// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec
+// base address: 0x2646c
+#define regAFMT5_AFMT_VBI_PACKET_CONTROL                                                                0x091c
+#define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       3
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2                                                             0x091d
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    3
+#define regAFMT5_AFMT_AUDIO_INFO0                                                                       0x091e
+#define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX                                                              3
+#define regAFMT5_AFMT_AUDIO_INFO1                                                                       0x091f
+#define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX                                                              3
+#define regAFMT5_AFMT_60958_0                                                                           0x0920
+#define regAFMT5_AFMT_60958_0_BASE_IDX                                                                  3
+#define regAFMT5_AFMT_60958_1                                                                           0x0921
+#define regAFMT5_AFMT_60958_1_BASE_IDX                                                                  3
+#define regAFMT5_AFMT_AUDIO_CRC_CONTROL                                                                 0x0922
+#define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        3
+#define regAFMT5_AFMT_RAMP_CONTROL0                                                                     0x0923
+#define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX                                                            3
+#define regAFMT5_AFMT_RAMP_CONTROL1                                                                     0x0924
+#define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX                                                            3
+#define regAFMT5_AFMT_RAMP_CONTROL2                                                                     0x0925
+#define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX                                                            3
+#define regAFMT5_AFMT_RAMP_CONTROL3                                                                     0x0926
+#define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX                                                            3
+#define regAFMT5_AFMT_60958_2                                                                           0x0927
+#define regAFMT5_AFMT_60958_2_BASE_IDX                                                                  3
+#define regAFMT5_AFMT_AUDIO_CRC_RESULT                                                                  0x0928
+#define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         3
+#define regAFMT5_AFMT_STATUS                                                                            0x0929
+#define regAFMT5_AFMT_STATUS_BASE_IDX                                                                   3
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL                                                              0x092a
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     3
+#define regAFMT5_AFMT_INFOFRAME_CONTROL0                                                                0x092b
+#define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       3
+#define regAFMT5_AFMT_INTERRUPT_STATUS                                                                  0x092c
+#define regAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         3
+#define regAFMT5_AFMT_AUDIO_SRC_CONTROL                                                                 0x092d
+#define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        3
+#define regAFMT5_AFMT_MEM_PWR                                                                           0x092f
+#define regAFMT5_AFMT_MEM_PWR_BASE_IDX                                                                  3
+
+
+// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec
+// base address: 0x264f0
+#define regDME5_DME_CONTROL                                                                             0x093c
+#define regDME5_DME_CONTROL_BASE_IDX                                                                    3
+#define regDME5_DME_MEMORY_CONTROL                                                                      0x093d
+#define regDME5_DME_MEMORY_CONTROL_BASE_IDX                                                             3
+
+
+// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec
+// base address: 0x264c4
+#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x0931
+#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 3
+#define regVPG5_VPG_GENERIC_PACKET_DATA                                                                 0x0932
+#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        3
+#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x0933
+#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      3
+#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x0934
+#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  3
+#define regVPG5_VPG_GENERIC_STATUS                                                                      0x0935
+#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX                                                             3
+#define regVPG5_VPG_MEM_PWR                                                                             0x0936
+#define regVPG5_VPG_MEM_PWR_BASE_IDX                                                                    3
+#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x0937
+#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        3
+#define regVPG5_VPG_ISRC1_2_DATA                                                                        0x0938
+#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX                                                               3
+#define regVPG5_VPG_MPEG_INFO0                                                                          0x0939
+#define regVPG5_VPG_MPEG_INFO0_BASE_IDX                                                                 3
+#define regVPG5_VPG_MPEG_INFO1                                                                          0x093a
+#define regVPG5_VPG_MPEG_INFO1_BASE_IDX                                                                 3
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc0_dispdec
+// base address: 0x1ab8c
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x3623
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x3624
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x3625
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x3626
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x3627
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE                                                           0x3628
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc0_apg_apg_dispdec
+// base address: 0x1abc0
+#define regAPG0_APG_CONTROL                                                                             0x3630
+#define regAPG0_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG0_APG_CONTROL2                                                                            0x3631
+#define regAPG0_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG0_APG_DBG_GEN_CONTROL                                                                     0x3632
+#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG0_APG_PACKET_CONTROL                                                                      0x3633
+#define regAPG0_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG0_APG_AUDIO_CRC_CONTROL                                                                   0x363a
+#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG0_APG_AUDIO_CRC_CONTROL2                                                                  0x363b
+#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG0_APG_AUDIO_CRC_RESULT                                                                    0x363c
+#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG0_APG_STATUS                                                                              0x3641
+#define regAPG0_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG0_APG_STATUS2                                                                             0x3642
+#define regAPG0_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG0_APG_MEM_PWR                                                                             0x3644
+#define regAPG0_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG0_APG_SPARE                                                                               0x3646
+#define regAPG0_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc0_dme_dme_dispdec
+// base address: 0x1ac38
+#define regDME6_DME_CONTROL                                                                             0x364e
+#define regDME6_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME6_DME_MEMORY_CONTROL                                                                      0x364f
+#define regDME6_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec
+// base address: 0x1ac44
+#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x3651
+#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG6_VPG_GENERIC_PACKET_DATA                                                                 0x3652
+#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x3653
+#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x3654
+#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG6_VPG_GENERIC_STATUS                                                                      0x3655
+#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG6_VPG_MEM_PWR                                                                             0x3656
+#define regVPG6_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x3657
+#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG6_VPG_ISRC1_2_DATA                                                                        0x3658
+#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG6_VPG_MPEG_INFO0                                                                          0x3659
+#define regVPG6_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG6_VPG_MPEG_INFO1                                                                          0x365a
+#define regVPG6_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dcn_dc_hpo_dp_sym32_enc0_dispdec
+// base address: 0x1ac74
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL                                                           0x365d
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x365e
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x365f
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3660
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3661
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0                                                          0x3662
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1                                                          0x3663
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2                                                          0x3664
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3                                                          0x3665
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4                                                          0x3666
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5                                                          0x3667
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6                                                          0x3668
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7                                                          0x3669
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8                                                          0x366a
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x366b
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x366c
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x366d
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x366e
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x366f
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3670
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3671
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x3672
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x3673
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x3674
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x3675
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x3676
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x3677
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x3678
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x3679
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x367a
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL                                                       0x367b
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x367c
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x367d
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x367e
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x3683
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3684
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3685
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x3686
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x3687
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3688
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3689
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x368a
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x368b
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE                                                             0x368c
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc1_dispdec
+// base address: 0x1aedc
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x36f7
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x36f8
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x36f9
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x36fa
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x36fb
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE                                                           0x36fc
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc1_apg_apg_dispdec
+// base address: 0x1af10
+#define regAPG1_APG_CONTROL                                                                             0x3704
+#define regAPG1_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG1_APG_CONTROL2                                                                            0x3705
+#define regAPG1_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG1_APG_DBG_GEN_CONTROL                                                                     0x3706
+#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG1_APG_PACKET_CONTROL                                                                      0x3707
+#define regAPG1_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG1_APG_AUDIO_CRC_CONTROL                                                                   0x370e
+#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG1_APG_AUDIO_CRC_CONTROL2                                                                  0x370f
+#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG1_APG_AUDIO_CRC_RESULT                                                                    0x3710
+#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG1_APG_STATUS                                                                              0x3715
+#define regAPG1_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG1_APG_STATUS2                                                                             0x3716
+#define regAPG1_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG1_APG_MEM_PWR                                                                             0x3718
+#define regAPG1_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG1_APG_SPARE                                                                               0x371a
+#define regAPG1_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc1_dme_dme_dispdec
+// base address: 0x1af88
+#define regDME7_DME_CONTROL                                                                             0x3722
+#define regDME7_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME7_DME_MEMORY_CONTROL                                                                      0x3723
+#define regDME7_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec
+// base address: 0x1af94
+#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x3725
+#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG7_VPG_GENERIC_PACKET_DATA                                                                 0x3726
+#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x3727
+#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x3728
+#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG7_VPG_GENERIC_STATUS                                                                      0x3729
+#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG7_VPG_MEM_PWR                                                                             0x372a
+#define regVPG7_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x372b
+#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG7_VPG_ISRC1_2_DATA                                                                        0x372c
+#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG7_VPG_MPEG_INFO0                                                                          0x372d
+#define regVPG7_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG7_VPG_MPEG_INFO1                                                                          0x372e
+#define regVPG7_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dcn_dc_hpo_dp_sym32_enc1_dispdec
+// base address: 0x1afc4
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL                                                           0x3731
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x3732
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x3733
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3734
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3735
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0                                                          0x3736
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1                                                          0x3737
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2                                                          0x3738
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3                                                          0x3739
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4                                                          0x373a
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5                                                          0x373b
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6                                                          0x373c
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7                                                          0x373d
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8                                                          0x373e
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x373f
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x3740
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x3741
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x3742
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x3743
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3744
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3745
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x3746
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x3747
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x3748
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x3749
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x374a
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x374b
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x374c
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x374d
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x374e
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL                                                       0x374f
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x3750
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x3751
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x3752
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x3757
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3758
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3759
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x375a
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x375b
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x375c
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x375d
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x375e
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x375f
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE                                                             0x3760
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc2_dispdec
+// base address: 0x1b22c
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x37cb
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x37cc
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x37cd
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x37ce
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x37cf
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE                                                           0x37d0
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc2_apg_apg_dispdec
+// base address: 0x1b260
+#define regAPG2_APG_CONTROL                                                                             0x37d8
+#define regAPG2_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG2_APG_CONTROL2                                                                            0x37d9
+#define regAPG2_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG2_APG_DBG_GEN_CONTROL                                                                     0x37da
+#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG2_APG_PACKET_CONTROL                                                                      0x37db
+#define regAPG2_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG2_APG_AUDIO_CRC_CONTROL                                                                   0x37e2
+#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG2_APG_AUDIO_CRC_CONTROL2                                                                  0x37e3
+#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG2_APG_AUDIO_CRC_RESULT                                                                    0x37e4
+#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG2_APG_STATUS                                                                              0x37e9
+#define regAPG2_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG2_APG_STATUS2                                                                             0x37ea
+#define regAPG2_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG2_APG_MEM_PWR                                                                             0x37ec
+#define regAPG2_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG2_APG_SPARE                                                                               0x37ee
+#define regAPG2_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc2_dme_dme_dispdec
+// base address: 0x1b2d8
+#define regDME8_DME_CONTROL                                                                             0x37f6
+#define regDME8_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME8_DME_MEMORY_CONTROL                                                                      0x37f7
+#define regDME8_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec
+// base address: 0x1b2e4
+#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x37f9
+#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG8_VPG_GENERIC_PACKET_DATA                                                                 0x37fa
+#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x37fb
+#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x37fc
+#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG8_VPG_GENERIC_STATUS                                                                      0x37fd
+#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG8_VPG_MEM_PWR                                                                             0x37fe
+#define regVPG8_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x37ff
+#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG8_VPG_ISRC1_2_DATA                                                                        0x3800
+#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG8_VPG_MPEG_INFO0                                                                          0x3801
+#define regVPG8_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG8_VPG_MPEG_INFO1                                                                          0x3802
+#define regVPG8_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dcn_dc_hpo_dp_sym32_enc2_dispdec
+// base address: 0x1b314
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL                                                           0x3805
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x3806
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x3807
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3808
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3809
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0                                                          0x380a
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1                                                          0x380b
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2                                                          0x380c
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3                                                          0x380d
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4                                                          0x380e
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5                                                          0x380f
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6                                                          0x3810
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7                                                          0x3811
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8                                                          0x3812
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x3813
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x3814
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x3815
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x3816
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x3817
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3818
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3819
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x381a
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x381b
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x381c
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x381d
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x381e
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x381f
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x3820
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x3821
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x3822
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL                                                       0x3823
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x3824
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x3825
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x3826
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x382b
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x382c
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x382d
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x382e
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x382f
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3830
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3831
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x3832
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3833
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE                                                             0x3834
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc3_dispdec
+// base address: 0x1b57c
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x389f
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x38a0
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x38a1
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x38a2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x38a3
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE                                                           0x38a4
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc3_apg_apg_dispdec
+// base address: 0x1b5b0
+#define regAPG3_APG_CONTROL                                                                             0x38ac
+#define regAPG3_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG3_APG_CONTROL2                                                                            0x38ad
+#define regAPG3_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG3_APG_DBG_GEN_CONTROL                                                                     0x38ae
+#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG3_APG_PACKET_CONTROL                                                                      0x38af
+#define regAPG3_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG3_APG_AUDIO_CRC_CONTROL                                                                   0x38b6
+#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG3_APG_AUDIO_CRC_CONTROL2                                                                  0x38b7
+#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG3_APG_AUDIO_CRC_RESULT                                                                    0x38b8
+#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG3_APG_STATUS                                                                              0x38bd
+#define regAPG3_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG3_APG_STATUS2                                                                             0x38be
+#define regAPG3_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG3_APG_MEM_PWR                                                                             0x38c0
+#define regAPG3_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG3_APG_SPARE                                                                               0x38c2
+#define regAPG3_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc3_dme_dme_dispdec
+// base address: 0x1b628
+#define regDME9_DME_CONTROL                                                                             0x38ca
+#define regDME9_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME9_DME_MEMORY_CONTROL                                                                      0x38cb
+#define regDME9_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec
+// base address: 0x1b634
+#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x38cd
+#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG9_VPG_GENERIC_PACKET_DATA                                                                 0x38ce
+#define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x38cf
+#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x38d0
+#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG9_VPG_GENERIC_STATUS                                                                      0x38d1
+#define regVPG9_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG9_VPG_MEM_PWR                                                                             0x38d2
+#define regVPG9_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x38d3
+#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG9_VPG_ISRC1_2_DATA                                                                        0x38d4
+#define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG9_VPG_MPEG_INFO0                                                                          0x38d5
+#define regVPG9_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG9_VPG_MPEG_INFO1                                                                          0x38d6
+#define regVPG9_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dcn_dc_hpo_dp_sym32_enc3_dispdec
+// base address: 0x1b664
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL                                                           0x38d9
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x38da
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x38db
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x38dc
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x38dd
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0                                                          0x38de
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1                                                          0x38df
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2                                                          0x38e0
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3                                                          0x38e1
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4                                                          0x38e2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5                                                          0x38e3
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6                                                          0x38e4
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7                                                          0x38e5
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8                                                          0x38e6
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x38e7
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x38e8
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x38e9
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x38ea
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x38eb
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x38ec
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x38ed
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x38ee
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x38ef
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x38f0
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x38f1
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x38f2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x38f3
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x38f4
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x38f5
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x38f6
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL                                                       0x38f7
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x38f8
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x38f9
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x38fa
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x38ff
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3900
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3901
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x3902
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x3903
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3904
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3905
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x3906
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3907
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE                                                             0x3908
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dcn_dc_hpo_dp_link_enc0_dispdec
+// base address: 0x1ad5c
+#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL                                                       0x3697
+#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2
+#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE                                                               0x3698
+#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hpo_dp_dphy_sym320_dispdec
+// base address: 0x1ae00
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL                                                         0x36c0
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS                                                          0x36c1
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE                                                      0x36c4
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x36c5
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x36c6
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x36c7
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x36c8
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0                                                         0x36cb
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1                                                         0x36cc
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2                                                         0x36cd
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3                                                         0x36ce
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x36d1
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x36d2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x36d3
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x36d4
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG                                                       0x36d7
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x36d8
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x36d9
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x36da
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x36db
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x36dc
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x36dd
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x36de
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x36df
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x36e0
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x36e1
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x36e2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x36e3
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x36e4
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x36e5
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x36e6
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x36e7
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS                                                    0x36e8
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE                                                 0x36ea
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX                                        2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0                                                     0x36eb
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1                                                     0x36ec
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS                                                      0x36ed
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT                                                       0x36ee
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX                                              2
+
+
+// addressBlock: dcn_dc_hpo_dp_link_enc1_dispdec
+// base address: 0x1b0ac
+#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL                                                       0x376b
+#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2
+#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE                                                               0x376c
+#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hpo_dp_dphy_sym321_dispdec
+// base address: 0x1b150
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL                                                         0x3794
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS                                                          0x3795
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE                                                      0x3798
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x3799
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x379a
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x379b
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x379c
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0                                                         0x379f
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1                                                         0x37a0
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2                                                         0x37a1
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3                                                         0x37a2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x37a5
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x37a6
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x37a7
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x37a8
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG                                                       0x37ab
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x37ac
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x37ad
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x37ae
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x37af
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x37b0
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x37b1
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x37b2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x37b3
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x37b4
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x37b5
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x37b6
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x37b7
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x37b8
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x37b9
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x37ba
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x37bb
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS                                                    0x37bc
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE                                                 0x37be
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX                                        2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0                                                     0x37bf
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1                                                     0x37c0
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS                                                      0x37c1
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT                                                       0x37c2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX                                              2
+
+
+// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe0_dispdec
+// base address: 0x0
+#define regRDPCSPIPE0_RDPCSPIPE_PHY_CNTL6                                                               0x293b
+#define regRDPCSPIPE0_RDPCSPIPE_PHY_CNTL6_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe1_dispdec
+// base address: 0x360
+#define regRDPCSPIPE1_RDPCSPIPE_PHY_CNTL6                                                               0x2a13
+#define regRDPCSPIPE1_RDPCSPIPE_PHY_CNTL6_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe2_dispdec
+// base address: 0x6c0
+#define regRDPCSPIPE2_RDPCSPIPE_PHY_CNTL6                                                               0x2aeb
+#define regRDPCSPIPE2_RDPCSPIPE_PHY_CNTL6_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe3_dispdec
+// base address: 0xa20
+#define regRDPCSPIPE3_RDPCSPIPE_PHY_CNTL6                                                               0x2bc3
+#define regRDPCSPIPE3_RDPCSPIPE_PHY_CNTL6_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe4_dispdec
+// base address: 0xd80
+#define regRDPCSPIPE4_RDPCSPIPE_PHY_CNTL6                                                               0x2c9b
+#define regRDPCSPIPE4_RDPCSPIPE_PHY_CNTL6_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azcontroller_azdec
+// base address: 0x0
+#define regCORB_WRITE_POINTER                                                                           0x0000
+#define regCORB_WRITE_POINTER_BASE_IDX                                                                  0
+#define regCORB_READ_POINTER                                                                            0x0000
+#define regCORB_READ_POINTER_BASE_IDX                                                                   0
+#define regCORB_CONTROL                                                                                 0x0001
+#define regCORB_CONTROL_BASE_IDX                                                                        0
+#define regCORB_STATUS                                                                                  0x0001
+#define regCORB_STATUS_BASE_IDX                                                                         0
+#define regCORB_SIZE                                                                                    0x0001
+#define regCORB_SIZE_BASE_IDX                                                                           0
+#define regRIRB_LOWER_BASE_ADDRESS                                                                      0x0002
+#define regRIRB_LOWER_BASE_ADDRESS_BASE_IDX                                                             0
+#define regRIRB_UPPER_BASE_ADDRESS                                                                      0x0003
+#define regRIRB_UPPER_BASE_ADDRESS_BASE_IDX                                                             0
+#define regRIRB_WRITE_POINTER                                                                           0x0004
+#define regRIRB_WRITE_POINTER_BASE_IDX                                                                  0
+#define regRESPONSE_INTERRUPT_COUNT                                                                     0x0004
+#define regRESPONSE_INTERRUPT_COUNT_BASE_IDX                                                            0
+#define regRIRB_CONTROL                                                                                 0x0005
+#define regRIRB_CONTROL_BASE_IDX                                                                        0
+#define regRIRB_STATUS                                                                                  0x0005
+#define regRIRB_STATUS_BASE_IDX                                                                         0
+#define regRIRB_SIZE                                                                                    0x0005
+#define regRIRB_SIZE_BASE_IDX                                                                           0
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE                                                           0x0006
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX                                                  0
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                                      0x0006
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                             0
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                                     0x0006
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                            0
+#define regIMMEDIATE_RESPONSE_INPUT_INTERFACE                                                           0x0007
+#define regIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX                                                  0
+#define regIMMEDIATE_COMMAND_STATUS                                                                     0x0008
+#define regIMMEDIATE_COMMAND_STATUS_BASE_IDX                                                            0
+#define regDMA_POSITION_LOWER_BASE_ADDRESS                                                              0x000a
+#define regDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX                                                     0
+#define regDMA_POSITION_UPPER_BASE_ADDRESS                                                              0x000b
+#define regDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX                                                     0
+#define regWALL_CLOCK_COUNTER_ALIAS                                                                     0x074c
+#define regWALL_CLOCK_COUNTER_ALIAS_BASE_IDX                                                            1
+
+
+// addressBlock: dcn_dc_hda_azendpoint_azdec
+// base address: 0x0
+#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                           0x0006
+#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                  0
+#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                          0x0006
+#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                 0
+
+
+// addressBlock: dcn_dc_hda_azinputendpoint_azdec
+// base address: 0x0
+#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                                            0x0006
+#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX                                   0
+#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                                           0x0006
+#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX                                  0
+
+
+// addressBlock: dcn_dc_hda_azroot_azdec
+// base address: 0x0
+#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                               0x0006
+#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                      0
+#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                              0x0006
+#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                     0
+
+
+// addressBlock: dcn_dc_hda_azstream0_azdec
+// base address: 0x0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x000e
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x000f
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0010
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0011
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x0012
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x0012
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x0014
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x0015
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0761
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dcn_dc_hda_azstream1_azdec
+// base address: 0x20
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x0016
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x0017
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0018
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0019
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x001a
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x001a
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x001c
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x001d
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0769
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dcn_dc_hda_azstream2_azdec
+// base address: 0x40
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x001e
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x001f
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0020
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0021
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x0022
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x0022
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x0024
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x0025
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0771
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dcn_dc_hda_azstream3_azdec
+// base address: 0x60
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x0026
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x0027
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0028
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0029
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x002a
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x002a
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x002c
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x002d
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0779
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dcn_dc_hda_azstream4_azdec
+// base address: 0x80
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x002e
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x002f
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0030
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0031
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x0032
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x0032
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x0034
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x0035
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0781
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dcn_dc_hda_azstream5_azdec
+// base address: 0xa0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x0036
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x0037
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0038
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0039
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x003a
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x003a
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x003c
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x003d
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0789
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dcn_dc_hda_azstream6_azdec
+// base address: 0xc0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x003e
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x003f
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0040
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0041
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x0042
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x0042
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x0044
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x0045
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0791
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dcn_dc_hda_azstream7_azdec
+// base address: 0xe0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x0046
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x0047
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0048
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0049
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x004a
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x004a
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x004c
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x004d
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0799
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: vga_vgaseqind
+// base address: 0x0
+#define ixSEQ00                                                                                        0x0000
+#define ixSEQ01                                                                                        0x0001
+#define ixSEQ02                                                                                        0x0002
+#define ixSEQ03                                                                                        0x0003
+#define ixSEQ04                                                                                        0x0004
+
+
+// addressBlock: vga_vgacrtind
+// base address: 0x0
+#define ixCRT00                                                                                        0x0000
+#define ixCRT01                                                                                        0x0001
+#define ixCRT02                                                                                        0x0002
+#define ixCRT03                                                                                        0x0003
+#define ixCRT04                                                                                        0x0004
+#define ixCRT05                                                                                        0x0005
+#define ixCRT06                                                                                        0x0006
+#define ixCRT07                                                                                        0x0007
+#define ixCRT08                                                                                        0x0008
+#define ixCRT09                                                                                        0x0009
+#define ixCRT0A                                                                                        0x000a
+#define ixCRT0B                                                                                        0x000b
+#define ixCRT0C                                                                                        0x000c
+#define ixCRT0D                                                                                        0x000d
+#define ixCRT0E                                                                                        0x000e
+#define ixCRT0F                                                                                        0x000f
+#define ixCRT10                                                                                        0x0010
+#define ixCRT11                                                                                        0x0011
+#define ixCRT12                                                                                        0x0012
+#define ixCRT13                                                                                        0x0013
+#define ixCRT14                                                                                        0x0014
+#define ixCRT15                                                                                        0x0015
+#define ixCRT16                                                                                        0x0016
+#define ixCRT17                                                                                        0x0017
+#define ixCRT18                                                                                        0x0018
+#define ixCRT1E                                                                                        0x001e
+#define ixCRT1F                                                                                        0x001f
+#define ixCRT22                                                                                        0x0022
+
+
+// addressBlock: vga_vgagrphind
+// base address: 0x0
+#define ixGRA00                                                                                        0x0000
+#define ixGRA01                                                                                        0x0001
+#define ixGRA02                                                                                        0x0002
+#define ixGRA03                                                                                        0x0003
+#define ixGRA04                                                                                        0x0004
+#define ixGRA05                                                                                        0x0005
+#define ixGRA06                                                                                        0x0006
+#define ixGRA07                                                                                        0x0007
+#define ixGRA08                                                                                        0x0008
+
+
+// addressBlock: vga_vgaattrind
+// base address: 0x0
+#define ixATTR00                                                                                       0x0000
+#define ixATTR01                                                                                       0x0001
+#define ixATTR02                                                                                       0x0002
+#define ixATTR03                                                                                       0x0003
+#define ixATTR04                                                                                       0x0004
+#define ixATTR05                                                                                       0x0005
+#define ixATTR06                                                                                       0x0006
+#define ixATTR07                                                                                       0x0007
+#define ixATTR08                                                                                       0x0008
+#define ixATTR09                                                                                       0x0009
+#define ixATTR0A                                                                                       0x000a
+#define ixATTR0B                                                                                       0x000b
+#define ixATTR0C                                                                                       0x000c
+#define ixATTR0D                                                                                       0x000d
+#define ixATTR0E                                                                                       0x000e
+#define ixATTR0F                                                                                       0x000f
+#define ixATTR10                                                                                       0x0010
+#define ixATTR11                                                                                       0x0011
+#define ixATTR12                                                                                       0x0012
+#define ixATTR13                                                                                       0x0013
+#define ixATTR14                                                                                       0x0014
+
+
+// addressBlock: azendpoint_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                                           0x2200
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                          0x2706
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                                          0x270d
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                                        0x270e
+#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                                                     0x2724
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                                        0x273e
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                                                  0x2770
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                              0x2771
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x2f09
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                                     0x2f0a
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                                           0x2f0b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY                                   0x3702
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                                                   0x3707
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                                             0x3708
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                               0x3709
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                                   0x371c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                                 0x371d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                                 0x371e
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                                 0x371f
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION                                      0x3770
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                                               0x3771
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                                                    0x3772
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                                                 0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                                            0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                                            0x3777
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                                            0x3778
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                                            0x3779
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                                            0x377a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                                          0x377b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                                            0x3780
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                                             0x3781
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                                             0x3785
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                                             0x3786
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                                             0x3787
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                                             0x3788
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                                0x3789
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                                    0x378a
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                                    0x378b
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                                    0x378c
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                                    0x378d
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                                    0x378e
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                                    0x378f
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                                    0x3790
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                                    0x3791
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                                    0x3792
+#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                                         0x3793
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                                            0x3797
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                            0x3798
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                                             0x3799
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                              0x379a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                                                      0x379b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                                                   0x379c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                                  0x379d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                                 0x379e
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                      0x3f09
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                                                   0x3f0c
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                                         0x3f0e
+
+
+// addressBlock: azendpoint_descriptorind
+// base address: 0x0
+#define ixAUDIO_DESCRIPTOR0                                                                            0x0001
+#define ixAUDIO_DESCRIPTOR1                                                                            0x0002
+#define ixAUDIO_DESCRIPTOR2                                                                            0x0003
+#define ixAUDIO_DESCRIPTOR3                                                                            0x0004
+#define ixAUDIO_DESCRIPTOR4                                                                            0x0005
+#define ixAUDIO_DESCRIPTOR5                                                                            0x0006
+#define ixAUDIO_DESCRIPTOR6                                                                            0x0007
+#define ixAUDIO_DESCRIPTOR7                                                                            0x0008
+#define ixAUDIO_DESCRIPTOR8                                                                            0x0009
+#define ixAUDIO_DESCRIPTOR9                                                                            0x000a
+#define ixAUDIO_DESCRIPTOR10                                                                           0x000b
+#define ixAUDIO_DESCRIPTOR11                                                                           0x000c
+#define ixAUDIO_DESCRIPTOR12                                                                           0x000d
+#define ixAUDIO_DESCRIPTOR13                                                                           0x000e
+
+
+// addressBlock: azendpoint_sinkinfoind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                                                  0x0000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                                       0x0001
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                                             0x0002
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                                          0x0003
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                                          0x0004
+#define ixSINK_DESCRIPTION0                                                                            0x0005
+#define ixSINK_DESCRIPTION1                                                                            0x0006
+#define ixSINK_DESCRIPTION2                                                                            0x0007
+#define ixSINK_DESCRIPTION3                                                                            0x0008
+#define ixSINK_DESCRIPTION4                                                                            0x0009
+#define ixSINK_DESCRIPTION5                                                                            0x000a
+#define ixSINK_DESCRIPTION6                                                                            0x000b
+#define ixSINK_DESCRIPTION7                                                                            0x000c
+#define ixSINK_DESCRIPTION8                                                                            0x000d
+#define ixSINK_DESCRIPTION9                                                                            0x000e
+#define ixSINK_DESCRIPTION10                                                                           0x000f
+#define ixSINK_DESCRIPTION11                                                                           0x0010
+#define ixSINK_DESCRIPTION12                                                                           0x0011
+#define ixSINK_DESCRIPTION13                                                                           0x0012
+#define ixSINK_DESCRIPTION14                                                                           0x0013
+#define ixSINK_DESCRIPTION15                                                                           0x0014
+#define ixSINK_DESCRIPTION16                                                                           0x0015
+#define ixSINK_DESCRIPTION17                                                                           0x0016
+
+
+// addressBlock: azf0controller_azinputcrc0resultind
+// base address: 0x0
+#define ixAZALIA_INPUT_CRC0_CHANNEL0                                                                   0x0000
+#define ixAZALIA_INPUT_CRC0_CHANNEL1                                                                   0x0001
+#define ixAZALIA_INPUT_CRC0_CHANNEL2                                                                   0x0002
+#define ixAZALIA_INPUT_CRC0_CHANNEL3                                                                   0x0003
+#define ixAZALIA_INPUT_CRC0_CHANNEL4                                                                   0x0004
+#define ixAZALIA_INPUT_CRC0_CHANNEL5                                                                   0x0005
+#define ixAZALIA_INPUT_CRC0_CHANNEL6                                                                   0x0006
+#define ixAZALIA_INPUT_CRC0_CHANNEL7                                                                   0x0007
+
+
+// addressBlock: azf0controller_azinputcrc1resultind
+// base address: 0x0
+#define ixAZALIA_INPUT_CRC1_CHANNEL0                                                                   0x0000
+#define ixAZALIA_INPUT_CRC1_CHANNEL1                                                                   0x0001
+#define ixAZALIA_INPUT_CRC1_CHANNEL2                                                                   0x0002
+#define ixAZALIA_INPUT_CRC1_CHANNEL3                                                                   0x0003
+#define ixAZALIA_INPUT_CRC1_CHANNEL4                                                                   0x0004
+#define ixAZALIA_INPUT_CRC1_CHANNEL5                                                                   0x0005
+#define ixAZALIA_INPUT_CRC1_CHANNEL6                                                                   0x0006
+#define ixAZALIA_INPUT_CRC1_CHANNEL7                                                                   0x0007
+
+
+// addressBlock: azf0controller_azcrc0resultind
+// base address: 0x0
+#define ixAZALIA_CRC0_CHANNEL0                                                                         0x0000
+#define ixAZALIA_CRC0_CHANNEL1                                                                         0x0001
+#define ixAZALIA_CRC0_CHANNEL2                                                                         0x0002
+#define ixAZALIA_CRC0_CHANNEL3                                                                         0x0003
+#define ixAZALIA_CRC0_CHANNEL4                                                                         0x0004
+#define ixAZALIA_CRC0_CHANNEL5                                                                         0x0005
+#define ixAZALIA_CRC0_CHANNEL6                                                                         0x0006
+#define ixAZALIA_CRC0_CHANNEL7                                                                         0x0007
+
+
+// addressBlock: azf0controller_azcrc1resultind
+// base address: 0x0
+#define ixAZALIA_CRC1_CHANNEL0                                                                         0x0000
+#define ixAZALIA_CRC1_CHANNEL1                                                                         0x0001
+#define ixAZALIA_CRC1_CHANNEL2                                                                         0x0002
+#define ixAZALIA_CRC1_CHANNEL3                                                                         0x0003
+#define ixAZALIA_CRC1_CHANNEL4                                                                         0x0004
+#define ixAZALIA_CRC1_CHANNEL5                                                                         0x0005
+#define ixAZALIA_CRC1_CHANNEL6                                                                         0x0006
+#define ixAZALIA_CRC1_CHANNEL7                                                                         0x0007
+
+
+// addressBlock: azinputendpoint_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                                     0x6200
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                    0x6706
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                                    0x670d
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                          0x6f09
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                               0x6f0a
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                                     0x6f0b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                                             0x7707
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                                       0x7708
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                                         0x7709
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                             0x771c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                           0x771d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                           0x771e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                           0x771f
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                                         0x7771
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                                       0x7777
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                                       0x7778
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                                       0x7779
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                                       0x777a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                                        0x777c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                                       0x7785
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                                       0x7786
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                                       0x7787
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                                       0x7788
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                      0x7798
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                                       0x7799
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                        0x779a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                                       0x779b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                                                  0x779c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                                           0x779d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                                           0x779e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x7f09
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                                             0x7f0c
+
+
+// addressBlock: azroot_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0f00
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0f02
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                                        0x0f04
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x1705
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x1720
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2                                     0x1721
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3                                     0x1722
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4                                     0x1723
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x1770
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                                       0x17ff
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT                                    0x1f04
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x1f05
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x1f0a
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x1f0b
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x1f0f
+
+
+// addressBlock: azf0stream0_streamind
+// base address: 0x0
+#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream1_streamind
+// base address: 0x0
+#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream2_streamind
+// base address: 0x0
+#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream3_streamind
+// base address: 0x0
+#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream4_streamind
+// base address: 0x0
+#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream5_streamind
+// base address: 0x0
+#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream6_streamind
+// base address: 0x0
+#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream7_streamind
+// base address: 0x0
+#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream8_streamind
+// base address: 0x0
+#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream9_streamind
+// base address: 0x0
+#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream10_streamind
+// base address: 0x0
+#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream11_streamind
+// base address: 0x0
+#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream12_streamind
+// base address: 0x0
+#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream13_streamind
+// base address: 0x0
+#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream14_streamind
+// base address: 0x0
+#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream15_streamind
+// base address: 0x0
+#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0endpoint0_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint1_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint2_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint3_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint4_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint5_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint6_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint7_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0inputendpoint0_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint1_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint2_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint3_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint4_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint5_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint6_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint7_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: c20_phy_cr0_rdpcspipecrind
+// base address: 0x0
+#define ixC20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x10cc
+#define ixC20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x12cc
+#define ixC20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x14cc
+#define ixC20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x16cc
+#define ixC20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2021
+#define ixC20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x20c0
+#define ixC20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2221
+#define ixC20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x22c0
+#define ixC20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2421
+#define ixC20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x24c0
+#define ixC20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2621
+#define ixC20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x26c0
+#define ixC20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x50cc
+#define ixC20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x6021
+#define ixC20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x60c0
+
+
+// addressBlock: c20_phy_cr1_rdpcspipecrind
+// base address: 0x0
+#define ixC20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x10cc
+#define ixC20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x12cc
+#define ixC20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x14cc
+#define ixC20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x16cc
+#define ixC20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2021
+#define ixC20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x20c0
+#define ixC20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2221
+#define ixC20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x22c0
+#define ixC20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2421
+#define ixC20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x24c0
+#define ixC20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2621
+#define ixC20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x26c0
+#define ixC20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x50cc
+#define ixC20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x6021
+#define ixC20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x60c0
+
+
+// addressBlock: c20_phy_cr2_rdpcspipecrind
+// base address: 0x0
+#define ixC20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x10cc
+#define ixC20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x12cc
+#define ixC20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x14cc
+#define ixC20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x16cc
+#define ixC20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2021
+#define ixC20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x20c0
+#define ixC20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2221
+#define ixC20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x22c0
+#define ixC20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2421
+#define ixC20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x24c0
+#define ixC20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2621
+#define ixC20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x26c0
+#define ixC20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x50cc
+#define ixC20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x6021
+#define ixC20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x60c0
+
+
+// addressBlock: c20_phy_cr3_rdpcspipecrind
+// base address: 0x0
+#define ixC20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x10cc
+#define ixC20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x12cc
+#define ixC20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x14cc
+#define ixC20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x16cc
+#define ixC20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2021
+#define ixC20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x20c0
+#define ixC20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2221
+#define ixC20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x22c0
+#define ixC20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2421
+#define ixC20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x24c0
+#define ixC20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2621
+#define ixC20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x26c0
+#define ixC20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x50cc
+#define ixC20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x6021
+#define ixC20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x60c0
+
+
+// addressBlock: c20_phy_cr4_rdpcspipecrind
+// base address: 0x0
+#define ixC20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x10cc
+#define ixC20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x12cc
+#define ixC20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x14cc
+#define ixC20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x16cc
+#define ixC20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2021
+#define ixC20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x20c0
+#define ixC20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2221
+#define ixC20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x22c0
+#define ixC20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2421
+#define ixC20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x24c0
+#define ixC20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2621
+#define ixC20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x26c0
+#define ixC20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x50cc
+#define ixC20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x6021
+#define ixC20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x60c0
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h
new file mode 100644
index 0000000000000..d42f91560bb95
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h
@@ -0,0 +1,222890 @@
+
+/*
+ * Copyright (C) 2022  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dcn_3_2_0_SH_MASK_HEADER
+#define _dcn_3_2_0_SH_MASK_HEADER
+
+
+// addressBlock: dcn_dc_dccg_dccg_dfs_dispdec
+//DENTIST_DISPCLK_CNTL
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT                                                 0x0
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT                                                 0x8
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT                                                 0xf
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT                                                   0x11
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT                                                  0x12
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT                                                 0x13
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT                                                  0x14
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT                                                    0x15
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT                                                   0x16
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT                                                  0x18
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK                                                   0x0000007FL
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK                                                   0x00007F00L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK                                                   0x00018000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK                                                     0x00020000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK                                                    0x00040000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK                                                   0x00080000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK                                                    0x00100000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK                                                      0x00200000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK                                                     0x00400000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK                                                    0x7F000000L
+
+
+// addressBlock: dcn_dc_dccg_dccg_dispdec
+//PHYPLLA_PIXCLK_RESYNC_CNTL
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK                                                0x00000100L
+//PHYPLLB_PIXCLK_RESYNC_CNTL
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK                                                0x00000100L
+//PHYPLLC_PIXCLK_RESYNC_CNTL
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK                                                0x00000100L
+//PHYPLLD_PIXCLK_RESYNC_CNTL
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK                                                0x00000100L
+//DP_DTO_DBUF_EN
+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT                                                                0x0
+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT                                                                0x1
+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT                                                                0x2
+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT                                                                0x3
+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT                                                                0x4
+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT                                                                0x5
+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT                                                                0x6
+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT                                                                0x7
+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK                                                                  0x00000001L
+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK                                                                  0x00000002L
+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK                                                                  0x00000004L
+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK                                                                  0x00000008L
+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK                                                                  0x00000010L
+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK                                                                  0x00000020L
+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK                                                                  0x00000040L
+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK                                                                  0x00000080L
+//DSCCLK3_DTO_PARAM
+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPREFCLK_CGTT_BLK_CTRL_REG
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT                                             0x0
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT                                            0x4
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK                                               0x0000000FL
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK                                              0x00000FF0L
+//DCCG_GATE_DISABLE_CNTL4
+#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x0
+#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x1
+#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x2
+#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x3
+#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x4
+#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE__SHIFT                                        0x11
+#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000001L
+#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000002L
+#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000004L
+#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000008L
+#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000010L
+#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE_MASK                                          0x00020000L
+//DPSTREAMCLK_CNTL
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL__SHIFT                                                         0x0
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN__SHIFT                                                              0x3
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL__SHIFT                                                         0x4
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_EN__SHIFT                                                              0x7
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_SRC_SEL__SHIFT                                                         0x8
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_EN__SHIFT                                                              0xb
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_SRC_SEL__SHIFT                                                         0xc
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_EN__SHIFT                                                              0xf
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL_MASK                                                           0x00000007L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN_MASK                                                                0x00000008L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL_MASK                                                           0x00000070L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_EN_MASK                                                                0x00000080L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_SRC_SEL_MASK                                                           0x00000700L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_EN_MASK                                                                0x00000800L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_SRC_SEL_MASK                                                           0x00007000L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_EN_MASK                                                                0x00008000L
+//REFCLK_CGTT_BLK_CTRL_REG
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//PHYPLLE_PIXCLK_RESYNC_CNTL
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK                                                0x00000100L
+//DCCG_GLOBAL_FGCG_REP_CNTL
+#define DCCG_GLOBAL_FGCG_REP_CNTL__DCCG_GLOBAL_FGCG_REP_DIS__SHIFT                                            0x0
+#define DCCG_GLOBAL_FGCG_REP_CNTL__DCCG_GLOBAL_FGCG_REP_DIS_MASK                                              0x00000001L
+//DCCG_DS_DTO_INCR
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT                                                             0x0
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK                                                               0xFFFFFFFFL
+//DCCG_DS_DTO_MODULO
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT                                                         0x0
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK                                                           0xFFFFFFFFL
+//DCCG_DS_CNTL
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT                                                                   0x0
+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT                                                                  0x4
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT                                                            0x8
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT                                                           0x9
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT                                                          0x10
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT                                                        0x18
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT                                                           0x19
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK                                                                     0x00000001L
+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK                                                                    0x00000030L
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK                                                              0x00000100L
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK                                                             0x00000200L
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK                                                            0x00030000L
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK                                                          0x01000000L
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK                                                             0x02000000L
+//DCCG_DS_HW_CAL_INTERVAL
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT                                               0x0
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK                                                 0xFFFFFFFFL
+//DPREFCLK_CNTL
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT                                                                0x0
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK                                                                  0x00000007L
+//DCE_VERSION
+#define DCE_VERSION__MAJOR_VERSION__SHIFT                                                                     0x0
+#define DCE_VERSION__MINOR_VERSION__SHIFT                                                                     0x8
+#define DCE_VERSION__MAJOR_VERSION_MASK                                                                       0x000000FFL
+#define DCE_VERSION__MINOR_VERSION_MASK                                                                       0x0000FF00L
+//DCCG_GTC_CNTL
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT                                                                 0x0
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK                                                                   0x00000001L
+//DCCG_GTC_DTO_INCR
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT                                                           0x0
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK                                                             0xFFFFFFFFL
+//DCCG_GTC_DTO_MODULO
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT                                                       0x0
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK                                                         0xFFFFFFFFL
+//DCCG_GTC_CURRENT
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT                                                             0x0
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK                                                               0xFFFFFFFFL
+//SYMCLK32_SE_CNTL
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL__SHIFT                                                         0x0
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN__SHIFT                                                              0x3
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL__SHIFT                                                         0x4
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN__SHIFT                                                              0x7
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL__SHIFT                                                         0x8
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN__SHIFT                                                              0xb
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL__SHIFT                                                         0xc
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN__SHIFT                                                              0xf
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL_MASK                                                           0x00000007L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN_MASK                                                                0x00000008L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL_MASK                                                           0x00000070L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN_MASK                                                                0x00000080L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL_MASK                                                           0x00000700L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN_MASK                                                                0x00000800L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL_MASK                                                           0x00007000L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN_MASK                                                                0x00008000L
+//SYMCLK32_LE_CNTL
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL__SHIFT                                                         0x0
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN__SHIFT                                                              0x3
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL__SHIFT                                                         0x4
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN__SHIFT                                                              0x7
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL_MASK                                                           0x00000007L
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN_MASK                                                                0x00000008L
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL_MASK                                                           0x00000070L
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN_MASK                                                                0x00000080L
+//DTBCLK_P_CNTL
+#define DTBCLK_P_CNTL__DTBCLK_P0_SRC_SEL__SHIFT                                                               0x0
+#define DTBCLK_P_CNTL__DTBCLK_P0_EN__SHIFT                                                                    0x2
+#define DTBCLK_P_CNTL__DTBCLK_P1_SRC_SEL__SHIFT                                                               0x3
+#define DTBCLK_P_CNTL__DTBCLK_P1_EN__SHIFT                                                                    0x5
+#define DTBCLK_P_CNTL__DTBCLK_P2_SRC_SEL__SHIFT                                                               0x6
+#define DTBCLK_P_CNTL__DTBCLK_P2_EN__SHIFT                                                                    0x8
+#define DTBCLK_P_CNTL__DTBCLK_P3_SRC_SEL__SHIFT                                                               0x9
+#define DTBCLK_P_CNTL__DTBCLK_P3_EN__SHIFT                                                                    0xb
+#define DTBCLK_P_CNTL__DTBCLK_P0_SRC_SEL_MASK                                                                 0x00000003L
+#define DTBCLK_P_CNTL__DTBCLK_P0_EN_MASK                                                                      0x00000004L
+#define DTBCLK_P_CNTL__DTBCLK_P1_SRC_SEL_MASK                                                                 0x00000018L
+#define DTBCLK_P_CNTL__DTBCLK_P1_EN_MASK                                                                      0x00000020L
+#define DTBCLK_P_CNTL__DTBCLK_P2_SRC_SEL_MASK                                                                 0x000000C0L
+#define DTBCLK_P_CNTL__DTBCLK_P2_EN_MASK                                                                      0x00000100L
+#define DTBCLK_P_CNTL__DTBCLK_P3_SRC_SEL_MASK                                                                 0x00000600L
+#define DTBCLK_P_CNTL__DTBCLK_P3_EN_MASK                                                                      0x00000800L
+//DCCG_GATE_DISABLE_CNTL5
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P0_GATE_DISABLE__SHIFT                                                0x0
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P1_GATE_DISABLE__SHIFT                                                0x1
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P2_GATE_DISABLE__SHIFT                                                0x2
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P3_GATE_DISABLE__SHIFT                                                0x3
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_ROOT_GATE_DISABLE__SHIFT                                        0x6
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_GATE_DISABLE__SHIFT                                             0x7
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_ROOT_GATE_DISABLE__SHIFT                                        0x8
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_GATE_DISABLE__SHIFT                                             0x9
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_ROOT_GATE_DISABLE__SHIFT                                        0xa
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_GATE_DISABLE__SHIFT                                             0xb
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_ROOT_GATE_DISABLE__SHIFT                                        0xc
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_GATE_DISABLE__SHIFT                                             0xd
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P0_GATE_DISABLE_MASK                                                  0x00000001L
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P1_GATE_DISABLE_MASK                                                  0x00000002L
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P2_GATE_DISABLE_MASK                                                  0x00000004L
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P3_GATE_DISABLE_MASK                                                  0x00000008L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_ROOT_GATE_DISABLE_MASK                                          0x00000040L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_GATE_DISABLE_MASK                                               0x00000080L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_ROOT_GATE_DISABLE_MASK                                          0x00000100L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_GATE_DISABLE_MASK                                               0x00000200L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_ROOT_GATE_DISABLE_MASK                                          0x00000400L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_GATE_DISABLE_MASK                                               0x00000800L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_ROOT_GATE_DISABLE_MASK                                          0x00001000L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_GATE_DISABLE_MASK                                               0x00002000L
+//DSCCLK0_DTO_PARAM
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK                                                            0x00FF0000L
+//DSCCLK1_DTO_PARAM
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK                                                            0x00FF0000L
+//DSCCLK2_DTO_PARAM
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO_MASK                                                            0x00FF0000L
+//OTG_PIXEL_RATE_DIV
+#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK1__SHIFT                                                      0x0
+#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK2__SHIFT                                                      0x1
+#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK1__SHIFT                                                      0x3
+#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK2__SHIFT                                                      0x4
+#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK1__SHIFT                                                      0x6
+#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK2__SHIFT                                                      0x7
+#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK1__SHIFT                                                      0x9
+#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK2__SHIFT                                                      0xa
+#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK1_MASK                                                        0x00000001L
+#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK2_MASK                                                        0x00000006L
+#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK1_MASK                                                        0x00000008L
+#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK2_MASK                                                        0x00000030L
+#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK1_MASK                                                        0x00000040L
+#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK2_MASK                                                        0x00000180L
+#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK1_MASK                                                        0x00000200L
+#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK2_MASK                                                        0x00000C00L
+//MILLISECOND_TIME_BASE_DIV
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT                                           0x0
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK                                             0x0001FFFFL
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L
+//DISPCLK_FREQ_CHANGE_CNTL
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT                                                   0x0
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT                                                    0x10
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT                                               0x14
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT                                            0x19
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT                                               0x1c
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT                                               0x1d
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT                                              0x1e
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT                                         0x1f
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK                                                     0x00003FFFL
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK                                                      0x000F0000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK                                                 0x00100000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK                                              0x0E000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK                                                 0x10000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK                                                 0x20000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK                                                0x40000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK                                           0x80000000L
+//DC_MEM_GLOBAL_PWR_REQ_CNTL
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT                                          0x0
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK                                            0x00000001L
+//DCCG_GATE_DISABLE_CNTL
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT                                              0x0
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT                                            0x1
+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT                                                    0x2
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT                                                  0x3
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT                                                   0x4
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT                                                   0x6
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT                                           0x8
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT                                                    0x9
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT                                             0xa
+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT                                                    0xb
+#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE__SHIFT                                                  0xc
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT                                                   0x11
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT                                                   0x12
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT                                                   0x13
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT                                              0x16
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT                                                    0x1a
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT                                              0x1b
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT                                                    0x1c
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT                                                   0x1d
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT                                                    0x1e
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK                                                0x00000001L
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK                                              0x00000002L
+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK                                                      0x00000004L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK                                                    0x00000008L
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK                                                     0x00000010L
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK                                                     0x00000040L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK                                             0x00000100L
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK                                                      0x00000200L
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK                                               0x00000400L
+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK                                                      0x00000800L
+#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE_MASK                                                    0x00001000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK                                                     0x00020000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK                                                     0x00040000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK                                                     0x00080000L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK                                                0x00400000L
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK                                                      0x04000000L
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK                                                0x08000000L
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK                                                      0x10000000L
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK                                                     0x20000000L
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK                                                      0x40000000L
+//DISPCLK_CGTT_BLK_CTRL_REG
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT                                               0x0
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT                                              0x4
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK                                                 0x0000000FL
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK                                                0x00000FF0L
+//SOCCLK_CGTT_BLK_CTRL_REG
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DCCG_CAC_STATUS
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT                                                             0x0
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK                                                               0xFFFFFFFFL
+//MICROSECOND_TIME_BASE_DIV
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT                                           0x0
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT                                                        0x8
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT                                                        0x10
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT                                           0x11
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK                                             0x0000007FL
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK                                                          0x00007F00L
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK                                                          0x00010000L
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK                                             0x00020000L
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L
+//DCCG_GATE_DISABLE_CNTL2
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT                                               0x0
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT                                               0x1
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT                                               0x2
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT                                               0x3
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT                                               0x4
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT                                               0x5
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT                                               0x6
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE__SHIFT                                             0x8
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE__SHIFT                                             0x9
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE__SHIFT                                             0xa
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE__SHIFT                                             0xb
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE__SHIFT                                             0xc
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE__SHIFT                                             0xd
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT                                                  0x10
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT                                                  0x11
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT                                                  0x12
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT                                                  0x13
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT                                                  0x14
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT                                                  0x15
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT                                                  0x16
+#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE__SHIFT                                               0x18
+#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE__SHIFT                                               0x19
+#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE__SHIFT                                               0x1a
+#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE__SHIFT                                               0x1b
+#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE__SHIFT                                               0x1c
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK                                                 0x00000001L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK                                                 0x00000002L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK                                                 0x00000004L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK                                                 0x00000008L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK                                                 0x00000010L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK                                                 0x00000020L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK                                                 0x00000040L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE_MASK                                               0x00000100L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE_MASK                                               0x00000200L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE_MASK                                               0x00000400L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE_MASK                                               0x00000800L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE_MASK                                               0x00001000L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE_MASK                                               0x00002000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK                                                    0x00010000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK                                                    0x00020000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK                                                    0x00040000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK                                                    0x00080000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK                                                    0x00100000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK                                                    0x00200000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK                                                    0x00400000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE_MASK                                                 0x01000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE_MASK                                                 0x02000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE_MASK                                                 0x04000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE_MASK                                                 0x08000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE_MASK                                                 0x10000000L
+//SYMCLK_CGTT_BLK_CTRL_REG
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DCCG_DISP_CNTL_REG
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT                                                      0x8
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK                                                        0x00000100L
+//OTG0_PIXEL_RATE_CNTL
+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_ENABLE__SHIFT                                                       0x3
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT                                                           0x4
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT                                                       0x5
+#define OTG0_PIXEL_RATE_CNTL__DTBCLKDTO0_ENABLE_STATUS__SHIFT                                                 0x6
+#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS__SHIFT                                                     0x7
+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL__SHIFT                                                        0xc
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_ENABLE_MASK                                                         0x00000008L
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK                                                             0x00000010L
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG0_PIXEL_RATE_CNTL__DTBCLKDTO0_ENABLE_STATUS_MASK                                                   0x00000040L
+#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS_MASK                                                       0x00000080L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL_MASK                                                          0x00003000L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+//DP_DTO0_PHASE
+#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT                                                                   0x0
+#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO0_MODULO
+#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT                                                                 0x0
+#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG0_PHYPLL_PIXEL_RATE_CNTL
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//OTG1_PIXEL_RATE_CNTL
+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_ENABLE__SHIFT                                                       0x3
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT                                                           0x4
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT                                                       0x5
+#define OTG1_PIXEL_RATE_CNTL__DTBCLKDTO1_ENABLE_STATUS__SHIFT                                                 0x6
+#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS__SHIFT                                                     0x7
+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL__SHIFT                                                        0xc
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_ENABLE_MASK                                                         0x00000008L
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK                                                             0x00000010L
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG1_PIXEL_RATE_CNTL__DTBCLKDTO1_ENABLE_STATUS_MASK                                                   0x00000040L
+#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS_MASK                                                       0x00000080L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL_MASK                                                          0x00003000L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+//DP_DTO1_PHASE
+#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT                                                                   0x0
+#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO1_MODULO
+#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT                                                                 0x0
+#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG1_PHYPLL_PIXEL_RATE_CNTL
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//OTG2_PIXEL_RATE_CNTL
+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_ENABLE__SHIFT                                                       0x3
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT                                                           0x4
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT                                                       0x5
+#define OTG2_PIXEL_RATE_CNTL__DTBCLKDTO2_ENABLE_STATUS__SHIFT                                                 0x6
+#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS__SHIFT                                                     0x7
+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL__SHIFT                                                        0xc
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_ENABLE_MASK                                                         0x00000008L
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK                                                             0x00000010L
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG2_PIXEL_RATE_CNTL__DTBCLKDTO2_ENABLE_STATUS_MASK                                                   0x00000040L
+#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS_MASK                                                       0x00000080L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL_MASK                                                          0x00003000L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+//DP_DTO2_PHASE
+#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT                                                                   0x0
+#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO2_MODULO
+#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT                                                                 0x0
+#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG2_PHYPLL_PIXEL_RATE_CNTL
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//OTG3_PIXEL_RATE_CNTL
+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_ENABLE__SHIFT                                                       0x3
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT                                                           0x4
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT                                                       0x5
+#define OTG3_PIXEL_RATE_CNTL__DTBCLKDTO3_ENABLE_STATUS__SHIFT                                                 0x6
+#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS__SHIFT                                                     0x7
+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL__SHIFT                                                        0xc
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_ENABLE_MASK                                                         0x00000008L
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK                                                             0x00000010L
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG3_PIXEL_RATE_CNTL__DTBCLKDTO3_ENABLE_STATUS_MASK                                                   0x00000040L
+#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS_MASK                                                       0x00000080L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL_MASK                                                          0x00003000L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+//DP_DTO3_PHASE
+#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT                                                                   0x0
+#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO3_MODULO
+#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT                                                                 0x0
+#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG3_PHYPLL_PIXEL_RATE_CNTL
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//DPPCLK_CGTT_BLK_CTRL_REG
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DPPCLK0_DTO_PARAM
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPPCLK1_DTO_PARAM
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPPCLK2_DTO_PARAM
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPPCLK3_DTO_PARAM
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO_MASK                                                            0x00FF0000L
+//DCCG_CAC_STATUS2
+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT                                                           0x0
+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK                                                             0x0007FFFFL
+//SYMCLKA_CLOCK_ENABLE
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKB_CLOCK_ENABLE
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKC_CLOCK_ENABLE
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKD_CLOCK_ENABLE
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKE_CLOCK_ENABLE
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK                                                       0x00000700L
+//DCCG_SOFT_RESET
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT                                                             0x0
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT                                                                0x2
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT                                                                0x3
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT                                                     0x4
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT                                                           0x8
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT                                                             0xc
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT                                                             0xd
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xe
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xf
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x10
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x11
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x12
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x13
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x14
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x15
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK                                                               0x00000001L
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK                                                                  0x00000004L
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK                                                                  0x00000008L
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK                                                       0x00000010L
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK                                                             0x00000100L
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK                                                               0x00001000L
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK                                                               0x00002000L
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00004000L
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00008000L
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00010000L
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00020000L
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00040000L
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00080000L
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00100000L
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00200000L
+//DSCCLK_DTO_CTRL
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE__SHIFT                                                            0x0
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE__SHIFT                                                            0x1
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE__SHIFT                                                            0x2
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE__SHIFT                                                            0x3
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE__SHIFT                                                            0x4
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE__SHIFT                                                            0x5
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT                                                             0x8
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT                                                             0x9
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT                                                             0xa
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT                                                             0xb
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT                                                             0xc
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT                                                             0xd
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE_MASK                                                              0x00000001L
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE_MASK                                                              0x00000002L
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE_MASK                                                              0x00000004L
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE_MASK                                                              0x00000008L
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE_MASK                                                              0x00000010L
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE_MASK                                                              0x00000020L
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK                                                               0x00000100L
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK                                                               0x00000200L
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK                                                               0x00000400L
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK                                                               0x00000800L
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK                                                               0x00001000L
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK                                                               0x00002000L
+//DCCG_AUDIO_DTO_SOURCE
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT                                              0x0
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT                                                      0x4
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT                                          0x14
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT                                          0x18
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT                                          0x1c
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO__SHIFT                                    0x1d
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK                                                0x00000007L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK                                                        0x00000070L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK                                            0x00100000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK                                            0x01000000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK                                            0x10000000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO_MASK                                      0x20000000L
+//DCCG_AUDIO_DTO0_PHASE
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT                                                   0x0
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK                                                     0xFFFFFFFFL
+//DCCG_AUDIO_DTO0_MODULE
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT                                                 0x0
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK                                                   0xFFFFFFFFL
+//DCCG_AUDIO_DTO1_PHASE
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT                                                   0x0
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK                                                     0xFFFFFFFFL
+//DCCG_AUDIO_DTO1_MODULE
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT                                                 0x0
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK                                                   0xFFFFFFFFL
+//DCCG_VSYNC_OTG0_LATCH_VALUE
+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG1_LATCH_VALUE
+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG2_LATCH_VALUE
+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG3_LATCH_VALUE
+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG4_LATCH_VALUE
+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG5_LATCH_VALUE
+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DPPCLK_DTO_CTRL
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE__SHIFT                                                            0x0
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT                                                             0x1
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE__SHIFT                                                            0x4
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT                                                             0x5
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE__SHIFT                                                            0x8
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT                                                             0x9
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE__SHIFT                                                            0xc
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT                                                             0xd
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE__SHIFT                                                            0x10
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT                                                             0x11
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE__SHIFT                                                            0x14
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT                                                             0x15
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE_MASK                                                              0x00000001L
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK                                                               0x00000002L
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE_MASK                                                              0x00000010L
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK                                                               0x00000020L
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE_MASK                                                              0x00000100L
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK                                                               0x00000200L
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE_MASK                                                              0x00001000L
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK                                                               0x00002000L
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE_MASK                                                              0x00010000L
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK                                                               0x00020000L
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE_MASK                                                              0x00100000L
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK                                                               0x00200000L
+//DCCG_VSYNC_CNT_CTRL
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT                                                     0x0
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT                                                   0x2
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT                                                  0x3
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT                                               0x4
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT                                                  0x8
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT                                                  0x10
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT                                                  0x11
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT                                                  0x12
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT                                                  0x13
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT                                                  0x14
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT                                                  0x15
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT                                            0x18
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT                                            0x19
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT                                            0x1a
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT                                            0x1b
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT                                            0x1c
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT                                            0x1d
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK                                                       0x00000001L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK                                                     0x00000004L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK                                                    0x00000008L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK                                                 0x000000F0L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK                                                    0x00000F00L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK                                                    0x00010000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK                                                    0x00020000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK                                                    0x00040000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK                                                    0x00080000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK                                                    0x00100000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK                                                    0x00200000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK                                              0x01000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK                                              0x02000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK                                              0x04000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK                                              0x08000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK                                              0x10000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK                                              0x20000000L
+//DCCG_VSYNC_CNT_INT_CTRL
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT                                   0x0
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT                             0x0
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT                                   0x1
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT                             0x1
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT                                   0x2
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT                             0x2
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT                                   0x3
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT                             0x3
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT                                   0x4
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT                             0x4
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT                                   0x5
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT                             0x5
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT                                        0x8
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT                                        0x9
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT                                        0xa
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT                                        0xb
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT                                        0xc
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT                                        0xd
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK                                     0x00000001L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK                               0x00000001L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK                                     0x00000002L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK                               0x00000002L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK                                     0x00000004L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK                               0x00000004L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK                                     0x00000008L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK                               0x00000008L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK                                     0x00000010L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK                               0x00000010L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK                                     0x00000020L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK                               0x00000020L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK                                          0x00000100L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK                                          0x00000200L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK                                          0x00000400L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK                                          0x00000800L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK                                          0x00001000L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK                                          0x00002000L
+//FORCE_SYMCLK_DISABLE
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE__SHIFT                                                    0x0
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE__SHIFT                                                    0x1
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE__SHIFT                                                    0x2
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE__SHIFT                                                    0x3
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE__SHIFT                                                    0x4
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE__SHIFT                                                    0x5
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE__SHIFT                                                    0x6
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE_MASK                                                      0x00000001L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE_MASK                                                      0x00000002L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE_MASK                                                      0x00000004L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE_MASK                                                      0x00000008L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE_MASK                                                      0x00000010L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE_MASK                                                      0x00000020L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE_MASK                                                      0x00000040L
+//DCCG_TEST_CLK_SEL
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT                                                  0x0
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT                                                  0xc
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL__SHIFT                                              0xe
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT                                                  0x10
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT                                                  0x1c
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK                                                    0x000001FFL
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK                                                    0x00001000L
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL_MASK                                                0x0000C000L
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK                                                    0x01FF0000L
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK                                                    0x10000000L
+//DTBCLK_DTO0_PHASE
+#define DTBCLK_DTO0_PHASE__DTBCLK_DTO0_PHASE__SHIFT                                                           0x0
+#define DTBCLK_DTO0_PHASE__DTBCLK_DTO0_PHASE_MASK                                                             0xFFFFFFFFL
+//DTBCLK_DTO1_PHASE
+#define DTBCLK_DTO1_PHASE__DTBCLK_DTO1_PHASE__SHIFT                                                           0x0
+#define DTBCLK_DTO1_PHASE__DTBCLK_DTO1_PHASE_MASK                                                             0xFFFFFFFFL
+//DTBCLK_DTO2_PHASE
+#define DTBCLK_DTO2_PHASE__DTBCLK_DTO2_PHASE__SHIFT                                                           0x0
+#define DTBCLK_DTO2_PHASE__DTBCLK_DTO2_PHASE_MASK                                                             0xFFFFFFFFL
+//DTBCLK_DTO3_PHASE
+#define DTBCLK_DTO3_PHASE__DTBCLK_DTO3_PHASE__SHIFT                                                           0x0
+#define DTBCLK_DTO3_PHASE__DTBCLK_DTO3_PHASE_MASK                                                             0xFFFFFFFFL
+//DTBCLK_DTO0_MODULO
+#define DTBCLK_DTO0_MODULO__DTBCLK_DTO0_MODULO__SHIFT                                                         0x0
+#define DTBCLK_DTO0_MODULO__DTBCLK_DTO0_MODULO_MASK                                                           0xFFFFFFFFL
+//DTBCLK_DTO1_MODULO
+#define DTBCLK_DTO1_MODULO__DTBCLK_DTO1_MODULO__SHIFT                                                         0x0
+#define DTBCLK_DTO1_MODULO__DTBCLK_DTO1_MODULO_MASK                                                           0xFFFFFFFFL
+//DTBCLK_DTO2_MODULO
+#define DTBCLK_DTO2_MODULO__DTBCLK_DTO2_MODULO__SHIFT                                                         0x0
+#define DTBCLK_DTO2_MODULO__DTBCLK_DTO2_MODULO_MASK                                                           0xFFFFFFFFL
+//DTBCLK_DTO3_MODULO
+#define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO__SHIFT                                                         0x0
+#define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO_MASK                                                           0xFFFFFFFFL
+//HDMICHARCLK0_CLOCK_CNTL
+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN__SHIFT                                                       0x0
+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL__SHIFT                                                  0x4
+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN_MASK                                                         0x00000001L
+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL_MASK                                                    0x00000070L
+//PHYASYMCLK_CLOCK_CNTL
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//PHYBSYMCLK_CLOCK_CNTL
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//PHYCSYMCLK_CLOCK_CNTL
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//PHYDSYMCLK_CLOCK_CNTL
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//PHYESYMCLK_CLOCK_CNTL
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//HDMISTREAMCLK_CNTL
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL__SHIFT                                                     0x0
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN__SHIFT                                                          0x3
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_DTO_FORCE_DIS__SHIFT                                               0x4
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL_MASK                                                       0x00000007L
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN_MASK                                                            0x00000008L
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_DTO_FORCE_DIS_MASK                                                 0x00000010L
+//DCCG_GATE_DISABLE_CNTL3
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE__SHIFT                                           0x0
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE__SHIFT                                           0x1
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE__SHIFT                                           0x2
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE__SHIFT                                           0x3
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE__SHIFT                                           0x4
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE__SHIFT                                           0x5
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE__SHIFT                                        0x8
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE__SHIFT                                             0x9
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE__SHIFT                                        0xa
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE__SHIFT                                             0xb
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE__SHIFT                                        0xc
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE__SHIFT                                             0xd
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE__SHIFT                                        0xe
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE__SHIFT                                             0xf
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE__SHIFT                                        0x14
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE__SHIFT                                             0x15
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE__SHIFT                                        0x16
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE__SHIFT                                             0x17
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE_MASK                                             0x00000001L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE_MASK                                             0x00000002L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE_MASK                                             0x00000004L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE_MASK                                             0x00000008L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE_MASK                                             0x00000010L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE_MASK                                             0x00000020L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE_MASK                                          0x00000100L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE_MASK                                               0x00000200L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE_MASK                                          0x00000400L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE_MASK                                               0x00000800L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE_MASK                                          0x00001000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE_MASK                                               0x00002000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE_MASK                                          0x00004000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE_MASK                                               0x00008000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE_MASK                                          0x00100000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE_MASK                                               0x00200000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE_MASK                                          0x00400000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE_MASK                                               0x00800000L
+//HDMISTREAMCLK0_DTO_PARAM
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE__SHIFT                                             0x0
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO__SHIFT                                            0x8
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN__SHIFT                                                0x10
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE_MASK                                               0x000000FFL
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO_MASK                                              0x0000FF00L
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN_MASK                                                  0x00010000L
+//DCCG_AUDIO_DTBCLK_DTO_PHASE
+#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE__SHIFT                                       0x0
+#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE_MASK                                         0xFFFFFFFFL
+//DCCG_AUDIO_DTBCLK_DTO_MODULO
+#define DCCG_AUDIO_DTBCLK_DTO_MODULO__DCCG_AUDIO_DTBCLK_DTO_MODULO__SHIFT                                     0x0
+#define DCCG_AUDIO_DTBCLK_DTO_MODULO__DCCG_AUDIO_DTBCLK_DTO_MODULO_MASK                                       0xFFFFFFFFL
+//DTBCLK_DTO_DBUF_EN
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO0_DBUF_EN__SHIFT                                                        0x0
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO1_DBUF_EN__SHIFT                                                        0x1
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO2_DBUF_EN__SHIFT                                                        0x2
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO3_DBUF_EN__SHIFT                                                        0x3
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO0_DBUF_EN_MASK                                                          0x00000001L
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO1_DBUF_EN_MASK                                                          0x00000002L
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO2_DBUF_EN_MASK                                                          0x00000004L
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO3_DBUF_EN_MASK                                                          0x00000008L
+//DMCUBCLK_CNTL
+#define DMCUBCLK_CNTL__DMCUBCLK_SRC_SEL__SHIFT                                                                0x0
+#define DMCUBCLK_CNTL__DMCUBCLK_SRC_SEL_MASK                                                                  0x00000003L
+
+
+
+
+// addressBlock: dcn_dc_dmu_rbbmif_dispdec
+//RBBMIF_TIMEOUT
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT                                                           0x0
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT                                                     0x14
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK                                                             0x000FFFFFL
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK                                                       0xFFF00000L
+//RBBMIF_STATUS
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT                                                      0x0
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK                                                        0xFFFFFFFFL
+//RBBMIF_STATUS_2
+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2__SHIFT                                                  0x0
+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2_MASK                                                    0x0000007FL
+//RBBMIF_INT_STATUS
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR__SHIFT                                                         0x2
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT                                                           0x1c
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT                                                  0x1d
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT                                                          0x1e
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT                                                         0x1f
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR_MASK                                                           0x0003FFFCL
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK                                                             0x10000000L
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK                                                    0x20000000L
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK                                                            0x40000000L
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK                                                           0x80000000L
+//RBBMIF_TIMEOUT_DIS
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT                                                        0x0
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT                                                        0x1
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT                                                        0x2
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT                                                        0x3
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT                                                        0x4
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT                                                        0x5
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT                                                        0x6
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT                                                        0x7
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT                                                        0x8
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT                                                        0x9
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT                                                       0xa
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT                                                       0xb
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT                                                       0xc
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT                                                       0xd
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT                                                       0xe
+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT                                                       0xf
+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT                                                       0x10
+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT                                                       0x11
+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT                                                       0x12
+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT                                                       0x13
+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT                                                       0x14
+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT                                                       0x15
+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT                                                       0x16
+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT                                                       0x17
+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT                                                       0x18
+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT                                                       0x19
+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT                                                       0x1a
+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT                                                       0x1b
+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT                                                       0x1c
+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT                                                       0x1d
+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS__SHIFT                                                       0x1e
+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS__SHIFT                                                       0x1f
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK                                                          0x00000001L
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK                                                          0x00000002L
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK                                                          0x00000004L
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK                                                          0x00000008L
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK                                                          0x00000010L
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK                                                          0x00000020L
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK                                                          0x00000040L
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK                                                          0x00000080L
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK                                                          0x00000100L
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK                                                          0x00000200L
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK                                                         0x00000400L
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK                                                         0x00000800L
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK                                                         0x00001000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK                                                         0x00002000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK                                                         0x00004000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK                                                         0x00008000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK                                                         0x00010000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK                                                         0x00020000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK                                                         0x00040000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK                                                         0x00080000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK                                                         0x00100000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK                                                         0x00200000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK                                                         0x00400000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK                                                         0x00800000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK                                                         0x01000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK                                                         0x02000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK                                                         0x04000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK                                                         0x08000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK                                                         0x10000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK                                                         0x20000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS_MASK                                                         0x40000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS_MASK                                                         0x80000000L
+//RBBMIF_TIMEOUT_DIS_2
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS__SHIFT                                                     0x0
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS__SHIFT                                                     0x1
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS__SHIFT                                                     0x2
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS__SHIFT                                                     0x3
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS__SHIFT                                                     0x4
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS__SHIFT                                                     0x5
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS__SHIFT                                                     0x6
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS_MASK                                                       0x00000001L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS_MASK                                                       0x00000002L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS_MASK                                                       0x00000004L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS_MASK                                                       0x00000008L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS_MASK                                                       0x00000010L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS_MASK                                                       0x00000020L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS_MASK                                                       0x00000040L
+//RBBMIF_STATUS_FLAG
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT                                                               0x0
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT                                                        0x4
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT                                                          0x5
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT                                                           0x6
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT                                                 0x8
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT                                                 0x9
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT                                                 0x10
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK                                                                 0x00000003L
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK                                                          0x00000010L
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK                                                            0x00000020L
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK                                                             0x00000040L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK                                                   0x00000100L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK                                                   0x00000E00L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK                                                   0xFFFF0000L
+
+
+//DC_GPU_TIMER_START_POSITION_V_UPDATE
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT                  0x0
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT                  0x4
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT                  0x8
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT                  0xc
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT                  0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT                  0x14
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK                    0x00000007L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK                    0x00000070L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK                    0x00000700L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK                    0x00007000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK                    0x00070000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK                    0x00700000L
+//DC_GPU_TIMER_START_POSITION_VSTARTUP
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT                  0x0
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT                  0x4
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT                  0x8
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT                  0xc
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT                  0x10
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT                  0x14
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK                    0x00000007L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK                    0x00000070L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK                    0x00000700L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK                    0x00007000L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK                    0x00070000L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK                    0x00700000L
+//DC_GPU_TIMER_READ
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT                                                           0x0
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK                                                             0xFFFFFFFFL
+//DC_GPU_TIMER_READ_CNTL
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT                                               0x0
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT                               0x8
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT                               0xb
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT                               0xe
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT                               0x11
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT                               0x14
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT                               0x17
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK                                                 0x0000007FL
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK                                 0x00000700L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK                                 0x00003800L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK                                 0x0001C000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK                                 0x000E0000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK                                 0x00700000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK                                 0x03800000L
+//DISP_INTERRUPT_STATUS
+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT                                          0x1
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT                                             0x4
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                                0x5
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                                      0x6
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT                                                0x7
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT                                                0x8
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                            0x9
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                              0xa
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                                0xf
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                                    0x10
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT                                                       0x11
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT                                                    0x12
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT                                                  0x13
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT                                                  0x14
+#define DISP_INTERRUPT_STATUS__DIO_ALPM_INTERRUPT__SHIFT                                                      0x15
+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT                                            0x17
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT                                                0x18
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT                                          0x1f
+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK                                            0x00000002L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK                                               0x00000010L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                                  0x00000020L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                                        0x00000040L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK                                                  0x00000080L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK                                                  0x00000100L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK                                              0x00000200L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                                0x00000400L
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                                  0x00008000L
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                                      0x00010000L
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK                                                         0x00020000L
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK                                                      0x00040000L
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK                                                    0x00080000L
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK                                                    0x00100000L
+#define DISP_INTERRUPT_STATUS__DIO_ALPM_INTERRUPT_MASK                                                        0x00200000L
+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK                                              0x00800000L
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK                                                  0x01000000L
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK                                            0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE
+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT                                 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT                                    0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                       0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                             0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT                                       0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT                                       0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                   0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                     0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                       0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                           0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT                                              0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT                                           0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT                                         0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT                                         0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT                                   0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT                                   0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT                                0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK                                   0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK                                      0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                         0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                               0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK                                         0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK                                         0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK                                     0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                       0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                         0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                             0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK                                                0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK                                             0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK                                           0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK                                           0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK                                     0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK                                     0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK                                  0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE2
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE3
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK                                  0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE5
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK                                    0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK                                    0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK                                    0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE6
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT                                      0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT                                      0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT                                      0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT                                      0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT                                      0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK                                        0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK                                        0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK                                        0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK                                        0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK                                        0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE7
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE8
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE9
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT                              0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK                                  0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK                                  0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK                                0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE10
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT                                0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT                                0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT                                0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT                                0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT                                0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK                                  0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK                                  0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK                                  0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK                                  0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK                                  0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE_MASK                                     0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE_MASK                                     0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE_MASK                                     0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE_MASK                                     0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE_MASK                                     0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE11
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT                                        0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT                                        0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT                                        0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT                                        0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT                                        0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT                                        0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT__SHIFT                                    0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK                                          0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK                                          0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK                                          0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK                                          0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK                                          0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK                                          0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT_MASK                                      0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE12
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE13
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT                                0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT__SHIFT                                 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT__SHIFT                     0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT                          0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT                          0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT                          0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT                          0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT                          0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT                          0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT                          0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK                                  0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT_MASK                                   0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_MASK                       0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK                            0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK                            0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK                            0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK                            0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK                            0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK                            0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK                            0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE14
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE15
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE16
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT                                   0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT                                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT                                   0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT                                   0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT                                    0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT                                   0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT                                   0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT                                    0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT                                   0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT                                   0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT                                    0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT                                   0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT                                   0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT                                    0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT                                   0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK                                     0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK                                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK                                     0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK                                     0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK                                      0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK                                     0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK                                     0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK                                      0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK                                     0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK                                     0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK                                      0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK                                     0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK                                     0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK                                      0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK                                     0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT_MASK                                    0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT_MASK                                    0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT_MASK                                    0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT_MASK                                    0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE17
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT                                     0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT                                     0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT                                     0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT                                     0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT                                     0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT                                     0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT                                     0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT                                     0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK                                       0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK                                       0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK                                       0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK                                       0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK                                       0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK                                       0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK                                       0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK                                       0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE18
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT                            0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT                            0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT                            0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT                            0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT                            0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT                            0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT                            0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT                            0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT                        0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT                        0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT                        0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT                        0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT                        0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT                        0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK                              0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK                              0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK                              0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK                              0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK                              0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK                              0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK                              0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK                              0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK                          0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK                          0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK                          0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK                          0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK                          0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK                          0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE19
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT                           0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT                           0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT                           0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT                           0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT                           0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT                           0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT                           0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT                           0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT                          0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT                          0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT                          0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT                          0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT                          0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT                          0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK                             0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK                             0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK                             0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK                             0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK                             0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK                             0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK                             0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK                             0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK                            0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK                            0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK                            0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK                            0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK                            0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK                            0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE20
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT                                    0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT                                    0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT                                    0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT                                    0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT                                    0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK                                      0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK                                      0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK                                      0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK                                      0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK                                      0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE21
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT                          0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT                          0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT                          0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT                          0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT                          0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT                          0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT                        0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT                           0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT                           0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT                           0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT                           0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT                           0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT                           0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT                            0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK                            0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK                            0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK                            0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK                            0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK                            0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK                            0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK                          0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK                             0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK                             0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK                             0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK                             0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK                             0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK                             0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK                              0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE22
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK                               0x80000000L
+//DC_GPU_TIMER_START_POSITION_VREADY
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT                      0x0
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT                      0x4
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT                      0x8
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT                      0xc
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT                      0x10
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT                      0x14
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK                        0x00000007L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK                        0x00000070L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK                        0x00000700L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK                        0x00007000L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK                        0x00070000L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK                        0x00700000L
+//DC_GPU_TIMER_START_POSITION_FLIP
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT                          0x0
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT                          0x4
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT                          0x8
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT                          0xc
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT                          0x10
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT                          0x14
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT                          0x18
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT                          0x1c
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK                            0x00000007L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK                            0x00000070L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK                            0x00000700L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK                            0x00007000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK                            0x00070000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK                            0x00700000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK                            0x07000000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK                            0x70000000L
+//DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT  0x0
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT  0x4
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT  0x8
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT  0xc
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT  0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT  0x14
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK    0x00000007L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK    0x00000070L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK    0x00000700L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK    0x00007000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK    0x00070000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK    0x00700000L
+//DC_GPU_TIMER_START_POSITION_FLIP_AWAY
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT                0x0
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT                0x4
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT                0x8
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT                0xc
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT                0x10
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT                0x14
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT                0x18
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT                0x1c
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK                  0x00000007L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK                  0x00000070L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK                  0x00000700L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK                  0x00007000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK                  0x00070000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK                  0x00700000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK                  0x07000000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK                  0x70000000L
+//DISP_INTERRUPT_STATUS_CONTINUE23
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT                         0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT                         0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT                         0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT                         0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT                         0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT                         0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT                       0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT                       0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT                       0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT                       0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT                       0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT                       0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK                           0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK                           0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK                           0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK                           0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK                           0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK                           0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK                         0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK                         0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK                         0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK                         0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK                         0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK                         0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE24
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT                          0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT                           0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                    0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                     0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                     0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                      0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                   0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                    0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                    0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                     0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT                              0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT                              0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN2_INTERRUPT__SHIFT                              0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN3_INTERRUPT__SHIFT                              0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN4_INTERRUPT__SHIFT                              0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN5_INTERRUPT__SHIFT                              0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN6_INTERRUPT__SHIFT                              0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT                              0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT                      0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK                            0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK                             0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                      0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                       0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                       0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                        0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                     0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                      0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                      0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                       0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK                                0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK                                0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN2_INTERRUPT_MASK                                0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN3_INTERRUPT_MASK                                0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN4_INTERRUPT_MASK                                0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN5_INTERRUPT_MASK                                0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN6_INTERRUPT_MASK                                0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK                                0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK                        0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE25
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DPIA_INTERRUPT__SHIFT                                               0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_WHITELIST_INVALID_ACCESS_INTERRUPT__SHIFT                     0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE25__MMHUBBUB_WARMUP_INTERRUPT__SHIFT                                    0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DPIA_INTERRUPT_MASK                                                 0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_WHITELIST_INVALID_ACCESS_INTERRUPT_MASK                       0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__MMHUBBUB_WARMUP_INTERRUPT_MASK                                      0x40000000L
+//DCCG_INTERRUPT_DEST
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT                                        0x0
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT                                        0x1
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT                                        0x2
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT                                        0x3
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT                                        0x4
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT                                        0x5
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK                                          0x00000001L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK                                          0x00000002L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK                                          0x00000004L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK                                          0x00000008L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK                                          0x00000010L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK                                          0x00000020L
+//DMU_INTERRUPT_DEST
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT                                                  0x0
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT                                                  0x1
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT                                                  0x2
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT                                                  0x3
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT                                                  0x4
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT3_INT_DEST__SHIFT                                                  0x5
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT4_INT_DEST__SHIFT                                                  0x6
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT5_INT_DEST__SHIFT                                                  0x7
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT6_INT_DEST__SHIFT                                                  0x8
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT_IH_INT_DEST__SHIFT                                                0x9
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT                                            0xa
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT                                             0xb
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT                                            0xc
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT                                             0xd
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT                                           0xe
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT                                            0xf
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT                                           0x10
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT                                            0x11
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT                                 0x1a
+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                          0x1b
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK                                                    0x00000001L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK                                                    0x00000002L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK                                                    0x00000004L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK                                                    0x00000008L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK                                                    0x00000010L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT3_INT_DEST_MASK                                                    0x00000020L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT4_INT_DEST_MASK                                                    0x00000040L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT5_INT_DEST_MASK                                                    0x00000080L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT6_INT_DEST_MASK                                                    0x00000100L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT_IH_INT_DEST_MASK                                                  0x00000200L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK                                              0x00000400L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK                                               0x00000800L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK                                              0x00001000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK                                               0x00002000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK                                             0x00004000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK                                              0x00008000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK                                             0x00010000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK                                              0x00020000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK                                   0x04000000L
+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                            0x08000000L
+//DMU_INTERRUPT_DEST2
+#define DMU_INTERRUPT_DEST2__DPIA_IHC_INTERRUPT_DEST__SHIFT                                                   0xc
+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_WHITELIST_INVALID_ACCESS_INTERRUPT_DEST__SHIFT                         0xd
+#define DMU_INTERRUPT_DEST2__DPIA_IHC_INTERRUPT_DEST_MASK                                                     0x00001000L
+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_WHITELIST_INVALID_ACCESS_INTERRUPT_DEST_MASK                           0x00002000L
+//DCPG_INTERRUPT_DEST
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x0
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x1
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x2
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x3
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x4
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x5
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x6
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x7
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x10
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x11
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x12
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x13
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x14
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x15
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x16
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x17
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000001L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000002L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000004L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000008L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000010L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000020L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000040L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000080L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00010000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00020000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00040000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00080000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00100000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00200000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00400000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00800000L
+//DCPG_INTERRUPT_DEST2
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT                                0x0
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT                                0x1
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT                                0x2
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT                                0x3
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT                                0x4
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT                                0x5
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x6
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x7
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x8
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x9
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xa
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xb
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000001L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000002L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000004L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000008L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000010L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000020L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000040L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000080L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000100L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000200L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000400L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000800L
+//MMHUBBUB_INTERRUPT_DEST
+#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST__SHIFT                                        0x0
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x1
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x2
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x3
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x4
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST__SHIFT                                       0x5
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST__SHIFT                                    0x8
+#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST_MASK                                          0x00000001L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000002L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000004L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000008L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000010L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST_MASK                                         0x00000020L
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST_MASK                                      0x00000100L
+//WB_INTERRUPT_DEST
+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x1
+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x9
+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0xb
+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000002L
+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000200L
+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000800L
+//DCHUB_INTERRUPT_DEST
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x0
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x2
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x3
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x4
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x5
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x6
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x7
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x8
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x9
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xa
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xb
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0xc
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0xd
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xe
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xf
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x10
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x11
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x12
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x13
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x14
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x15
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x16
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x17
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x18
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x19
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1a
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1b
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x1c
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1d
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1e
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1f
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000001L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000002L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000004L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000008L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000010L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000020L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000040L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000080L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000100L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000200L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000400L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000800L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00001000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00002000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00004000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00008000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00010000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00020000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00040000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00080000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00100000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00200000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00400000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00800000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x01000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x02000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x04000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x08000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x10000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x20000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x40000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x80000000L
+//DCHUB_PERFCOUNTER_INTERRUPT_DEST
+//DCHUB_INTERRUPT_DEST2
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x0
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x1
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x2
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x3
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x4
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x5
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x6
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x7
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x8
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x9
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xa
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xb
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xc
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xd
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xe
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xf
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT                                      0x18
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                       0x19
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST__SHIFT                           0x1a
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000001L
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000002L
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000004L
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000008L
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000010L
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000020L
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000040L
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000080L
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000100L
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000200L
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000400L
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000800L
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00001000L
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00002000L
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00004000L
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00008000L
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK                                        0x01000000L
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                         0x02000000L
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST_MASK                             0x04000000L
+//DPP_PERFCOUNTER_INTERRUPT_DEST
+//MPC_INTERRUPT_DEST
+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST__SHIFT                                                 0x0
+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST__SHIFT                                                 0x1
+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST__SHIFT                                                 0x2
+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST__SHIFT                                                 0x3
+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST__SHIFT                                                 0x4
+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST__SHIFT                                                 0x5
+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST__SHIFT                                                 0x6
+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST__SHIFT                                                 0x7
+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST_MASK                                                   0x00000001L
+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST_MASK                                                   0x00000002L
+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST_MASK                                                   0x00000004L
+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST_MASK                                                   0x00000008L
+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST_MASK                                                   0x00000010L
+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST_MASK                                                   0x00000020L
+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST_MASK                                                   0x00000040L
+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST_MASK                                                   0x00000080L
+//OPP_INTERRUPT_DEST
+//OPTC_INTERRUPT_DEST
+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x18
+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x19
+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1a
+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1b
+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1c
+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1d
+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x01000000L
+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x02000000L
+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x04000000L
+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x08000000L
+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x10000000L
+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x20000000L
+//OTG0_INTERRUPT_DEST
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG1_INTERRUPT_DEST
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG2_INTERRUPT_DEST
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG3_INTERRUPT_DEST
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG4_INTERRUPT_DEST
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG5_INTERRUPT_DEST
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//DIG_INTERRUPT_DEST
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x0
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x1
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x2
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x3
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x4
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x5
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x6
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x7
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x8
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x9
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xa
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xb
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xc
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xd
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xe
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xf
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000001L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000002L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000004L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000008L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000010L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000020L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000040L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000080L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000100L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000200L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000400L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000800L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00001000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00002000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00004000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00008000L
+//I2C_DDC_HPD_INTERRUPT_DEST
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT                                0x0
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT                           0x1
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT                           0x2
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT                           0x3
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT                           0x4
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT                           0x5
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT                           0x6
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT                         0x7
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x10
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x11
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x12
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x13
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x14
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x15
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT                          0x16
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK                                  0x00000001L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK                             0x00000002L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK                             0x00000004L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK                             0x00000008L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK                             0x00000010L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK                             0x00000020L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK                             0x00000040L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK                           0x00000080L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00010000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00020000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00040000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00080000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00100000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00200000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK                            0x00400000L
+//DIO_INTERRUPT_DEST
+#define DIO_INTERRUPT_DEST__DIO_ALPM_INTERRUPT_DEST__SHIFT                                                    0x4
+#define DIO_INTERRUPT_DEST__DIO_ALPM_INTERRUPT_DEST_MASK                                                      0x00000010L
+//DCIO_INTERRUPT_DEST
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x0
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x1
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x2
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x3
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x4
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x5
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x6
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x10
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000001L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000002L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000004L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000008L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000010L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000020L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000040L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00010000L
+//HPD_INTERRUPT_DEST
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT                                               0x0
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT                                               0x1
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT                                               0x2
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT                                               0x3
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT                                               0x4
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT                                               0x5
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT                                            0x8
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT                                            0x9
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT                                            0xa
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT                                            0xb
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT                                            0xc
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT                                            0xd
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK                                                 0x00000001L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK                                                 0x00000002L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK                                                 0x00000004L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK                                                 0x00000008L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK                                                 0x00000010L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK                                                 0x00000020L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK                                              0x00000100L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK                                              0x00000200L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK                                              0x00000400L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK                                              0x00000800L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK                                              0x00001000L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK                                              0x00002000L
+//AZ_INTERRUPT_DEST
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x0
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x1
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x2
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x3
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x4
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x5
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x6
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x7
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x8
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x9
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xa
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xb
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xc
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xd
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xe
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xf
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x10
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x11
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x12
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x13
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x14
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x15
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x16
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x17
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000001L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000002L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000004L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000008L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000010L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000020L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000040L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000080L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000100L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000200L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000400L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000800L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK                                       0x00001000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK                                       0x00002000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK                                       0x00004000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK                                       0x00008000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK                                      0x00010000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK                                      0x00020000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK                                      0x00040000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK                                      0x00080000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK                                      0x00100000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK                                      0x00200000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK                                      0x00400000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK                                      0x00800000L
+//AUX_INTERRUPT_DEST
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x0
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x1
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x2
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x3
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x4
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x5
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x6
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x7
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x8
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x9
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT                                       0xa
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT                                       0xb
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x10
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x11
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x12
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x13
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x14
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x15
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x16
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x17
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x18
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x19
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x1a
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x1b
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000001L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000002L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000004L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000008L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000010L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000020L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000040L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000080L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000100L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000200L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000400L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000800L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00010000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00020000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00040000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00080000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00100000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00200000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00400000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00800000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x01000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x02000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x04000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x08000000L
+//DSC_INTERRUPT_DEST
+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x0
+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x1
+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x4
+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x5
+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x8
+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x9
+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0xc
+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0xd
+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x10
+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x11
+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x14
+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x15
+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000001L
+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000002L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000010L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000020L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000100L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000200L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00001000L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00002000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00010000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00020000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00100000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00200000L
+//HPO_INTERRUPT_DEST
+
+
+//CC_DC_PIPE_DIS
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT                                                                    0x0
+#define CC_DC_PIPE_DIS__DC_FULL_DIS__SHIFT                                                                    0xc
+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE__SHIFT                                                                0x10
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK                                                                      0x000000FFL
+#define CC_DC_PIPE_DIS__DC_FULL_DIS_MASK                                                                      0x00001000L
+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE_MASK                                                                  0x00010000L
+//DMU_CLK_CNTL
+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT                                                                 0x0
+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT                                                           0x4
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT                                                        0x6
+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT                                                               0x8
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT                                                        0xa
+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK                                                                   0x0000000FL
+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK                                                             0x00000010L
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK                                                          0x00000040L
+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK                                                                 0x00000100L
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK                                                          0x00000400L
+//DMCUB_SMU_INTERRUPT_CNTL
+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_INT__SHIFT                                                    0x0
+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG__SHIFT                                                        0x10
+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_INT_MASK                                                      0x00000001L
+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_MASK                                                          0xFFFF0000L
+//SMU_INTERRUPT_CONTROL
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT                                                       0x0
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT                                                       0x4
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT                                                        0x10
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK                                                         0x00000001L
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK                                                         0x00000010L
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK                                                          0xFFFF0000L
+//DMU_MISC_ALLOW_DS_FORCE
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT                                            0x0
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT                                         0x4
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK                                              0x00000001L
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK                                           0x00000010L
+
+
+//DOMAIN0_PG_CONFIG
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L
+//DOMAIN0_PG_STATUS
+#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c
+#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e
+#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L
+#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L
+//DOMAIN1_PG_CONFIG
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L
+//DOMAIN1_PG_STATUS
+#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c
+#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e
+#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L
+#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L
+//DOMAIN2_PG_CONFIG
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L
+//DOMAIN2_PG_STATUS
+#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c
+#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e
+#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L
+#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L
+//DOMAIN3_PG_CONFIG
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L
+//DOMAIN3_PG_STATUS
+#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c
+#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e
+#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L
+#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L
+//DOMAIN16_PG_CONFIG
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN16_PG_STATUS
+#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DOMAIN17_PG_CONFIG
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN17_PG_STATUS
+#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DOMAIN18_PG_CONFIG
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN18_PG_STATUS
+#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DOMAIN19_PG_CONFIG
+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN19_PG_STATUS
+#define DOMAIN19_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN19_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DCPG_INTERRUPT_STATUS
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT                                           0x0
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x1
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT                                           0x2
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x3
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT                                           0x4
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x5
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT                                           0x6
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x7
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK                                             0x00000001L
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000002L
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK                                             0x00000004L
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000008L
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK                                             0x00000010L
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000020L
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK                                             0x00000040L
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000080L
+//DCPG_INTERRUPT_STATUS_2
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT                                        0x0
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x1
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT                                        0x2
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x3
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT                                        0x4
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x5
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT                                        0x6
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x7
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED_MASK                                          0x00000001L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000002L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED_MASK                                          0x00000004L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000008L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED_MASK                                          0x00000010L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000020L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED_MASK                                          0x00000040L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000080L
+//DCPG_INTERRUPT_CONTROL_1
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT                                            0x0
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT                                           0x1
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT                                          0x2
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT                                         0x3
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT                                            0x4
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT                                           0x5
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT                                          0x6
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT                                         0x7
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT                                            0x8
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT                                           0x9
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT                                          0xa
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT                                         0xb
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT                                            0xc
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT                                           0xd
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT                                          0xe
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT                                         0xf
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK                                              0x00000001L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK                                             0x00000002L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK                                            0x00000004L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK                                           0x00000008L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK                                              0x00000010L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK                                             0x00000020L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK                                            0x00000040L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK                                           0x00000080L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK                                              0x00000100L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK                                             0x00000200L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK                                            0x00000400L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK                                           0x00000800L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK                                              0x00001000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK                                             0x00002000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK                                            0x00004000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK                                           0x00008000L
+//DCPG_INTERRUPT_CONTROL_3
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK__SHIFT                                           0x0
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR__SHIFT                                          0x1
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK__SHIFT                                         0x2
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT                                        0x3
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK__SHIFT                                           0x4
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR__SHIFT                                          0x5
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK__SHIFT                                         0x6
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT                                        0x7
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK__SHIFT                                           0x8
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR__SHIFT                                          0x9
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK__SHIFT                                         0xa
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT                                        0xb
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK__SHIFT                                           0xc
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR__SHIFT                                          0xd
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK__SHIFT                                         0xe
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT                                        0xf
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK_MASK                                             0x00000001L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR_MASK                                            0x00000002L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK_MASK                                           0x00000004L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR_MASK                                          0x00000008L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK_MASK                                             0x00000010L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR_MASK                                            0x00000020L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK_MASK                                           0x00000040L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR_MASK                                          0x00000080L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK_MASK                                             0x00000100L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR_MASK                                            0x00000200L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK_MASK                                           0x00000400L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR_MASK                                          0x00000800L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK_MASK                                             0x00001000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR_MASK                                            0x00002000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK_MASK                                           0x00004000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR_MASK                                          0x00008000L
+//DC_IP_REQUEST_CNTL
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT                                                              0x0
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK                                                                0x00000001L
+
+
+// addressBlock: dcn_dc_dmu_dmcub_dispdec
+//DMCUB_REGION0_OFFSET
+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION0_OFFSET_HIGH
+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION1_OFFSET
+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION1_OFFSET_HIGH
+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION2_OFFSET
+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION2_OFFSET_HIGH
+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION4_OFFSET
+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION4_OFFSET_HIGH
+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION5_OFFSET
+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION5_OFFSET_HIGH
+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION6_OFFSET
+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION6_OFFSET_HIGH
+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION7_OFFSET
+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION7_OFFSET_HIGH
+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION0_TOP_ADDRESS
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION1_TOP_ADDRESS
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION2_TOP_ADDRESS
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION4_TOP_ADDRESS
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION5_TOP_ADDRESS
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION6_TOP_ADDRESS
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION7_TOP_ADDRESS
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION3_CW0_BASE_ADDRESS
+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW1_BASE_ADDRESS
+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW2_BASE_ADDRESS
+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW3_BASE_ADDRESS
+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW4_BASE_ADDRESS
+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW5_BASE_ADDRESS
+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW6_BASE_ADDRESS
+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW7_BASE_ADDRESS
+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW0_TOP_ADDRESS
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW1_TOP_ADDRESS
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW2_TOP_ADDRESS
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW3_TOP_ADDRESS
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW4_TOP_ADDRESS
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW5_TOP_ADDRESS
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW6_TOP_ADDRESS
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW7_TOP_ADDRESS
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW0_OFFSET
+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW0_OFFSET_HIGH
+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW1_OFFSET
+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW1_OFFSET_HIGH
+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW2_OFFSET
+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW2_OFFSET_HIGH
+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW3_OFFSET
+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW3_OFFSET_HIGH
+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW4_OFFSET
+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW4_OFFSET_HIGH
+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW5_OFFSET
+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW5_OFFSET_HIGH
+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW6_OFFSET
+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW6_OFFSET_HIGH
+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW7_OFFSET
+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW7_OFFSET_HIGH
+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_INTERRUPT_ENABLE
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT                                                    0x0
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT                                                    0x1
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT                                              0x2
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT                                               0x3
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT                                              0x4
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT                                               0x5
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT                                             0x6
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT                                              0x7
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT                                             0x8
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT                                              0x9
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT                                                    0xa
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT                                                    0xb
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT                                                    0xc
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT3_INT_EN__SHIFT                                                    0xd
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT4_INT_EN__SHIFT                                                    0xe
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT5_INT_EN__SHIFT                                                    0xf
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT6_INT_EN__SHIFT                                                    0x10
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN__SHIFT                                                  0x11
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT                                   0x12
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK                                                      0x00000001L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK                                                      0x00000002L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK                                                0x00000004L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK                                                 0x00000008L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK                                                0x00000010L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK                                                 0x00000020L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK                                               0x00000040L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK                                                0x00000080L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK                                               0x00000100L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK                                                0x00000200L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK                                                      0x00000400L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK                                                      0x00000800L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK                                                      0x00001000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT3_INT_EN_MASK                                                      0x00002000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT4_INT_EN_MASK                                                      0x00004000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT5_INT_EN_MASK                                                      0x00008000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT6_INT_EN_MASK                                                      0x00010000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN_MASK                                                    0x00020000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK                                     0x00040000L
+//DMCUB_INTERRUPT_ACK
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT                                                      0x0
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT                                                      0x1
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT                                                0x2
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT                                                 0x3
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT                                                0x4
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT                                                 0x5
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT                                               0x6
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT                                                0x7
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT                                               0x8
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT                                                0x9
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT                                                      0xa
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT                                                      0xb
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT                                                      0xc
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT3_INT_ACK__SHIFT                                                      0xd
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT4_INT_ACK__SHIFT                                                      0xe
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT5_INT_ACK__SHIFT                                                      0xf
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT6_INT_ACK__SHIFT                                                      0x10
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK__SHIFT                                                    0x11
+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT                                         0x12
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK                                                        0x00000001L
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK                                                        0x00000002L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK                                                  0x00000004L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK                                                   0x00000008L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK                                                  0x00000010L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK                                                   0x00000020L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK                                                 0x00000040L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK                                                  0x00000080L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK                                                 0x00000100L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK                                                  0x00000200L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK                                                        0x00000400L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK                                                        0x00000800L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK                                                        0x00001000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT3_INT_ACK_MASK                                                        0x00002000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT4_INT_ACK_MASK                                                        0x00004000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT5_INT_ACK_MASK                                                        0x00008000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT6_INT_ACK_MASK                                                        0x00010000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK_MASK                                                      0x00020000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK                                           0x00040000L
+//DMCUB_INTERRUPT_STATUS
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT                                                  0x0
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT                                                  0x1
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT                                            0x2
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT                                             0x3
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT                                            0x4
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT                                             0x5
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT                                           0x6
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT                                            0x7
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT                                           0x8
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT                                            0x9
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT                                                  0xa
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT                                                  0xb
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT                                                  0xc
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT3_INT_STAT__SHIFT                                                  0xd
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT4_INT_STAT__SHIFT                                                  0xe
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT5_INT_STAT__SHIFT                                                  0xf
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT6_INT_STAT__SHIFT                                                  0x10
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT_IH_INT_STAT__SHIFT                                                0x11
+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT                                          0x12
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT                                                 0x13
+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT                                                 0x14
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK                                                    0x00000001L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK                                                    0x00000002L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK                                              0x00000004L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK                                               0x00000008L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK                                              0x00000010L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK                                               0x00000020L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK                                             0x00000040L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK                                              0x00000080L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK                                             0x00000100L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK                                              0x00000200L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK                                                    0x00000400L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK                                                    0x00000800L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK                                                    0x00001000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT3_INT_STAT_MASK                                                    0x00002000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT4_INT_STAT_MASK                                                    0x00004000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT5_INT_STAT_MASK                                                    0x00008000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT6_INT_STAT_MASK                                                    0x00010000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT_IH_INT_STAT_MASK                                                  0x00020000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK                                            0x00040000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK                                                   0x00080000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK                                                   0x00100000L
+//DMCUB_INTERRUPT_TYPE
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT                                                    0x0
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT                                                    0x1
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT                                              0x2
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT                                               0x3
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT                                              0x4
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT                                               0x5
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT                                             0x6
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT                                              0x7
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT                                             0x8
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT                                              0x9
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT                                                    0xa
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT                                                    0xb
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT                                                    0xc
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT3_INT_TYPE__SHIFT                                                    0xd
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT4_INT_TYPE__SHIFT                                                    0xe
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT5_INT_TYPE__SHIFT                                                    0xf
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT6_INT_TYPE__SHIFT                                                    0x10
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT_IH_INT_TYPE__SHIFT                                                  0x11
+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT                                   0x12
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK                                                      0x00000001L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK                                                      0x00000002L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK                                                0x00000004L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK                                                 0x00000008L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK                                                0x00000010L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK                                                 0x00000020L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK                                               0x00000040L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK                                                0x00000080L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK                                               0x00000100L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK                                                0x00000200L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK                                                      0x00000400L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK                                                      0x00000800L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK                                                      0x00001000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT3_INT_TYPE_MASK                                                      0x00002000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT4_INT_TYPE_MASK                                                      0x00004000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT5_INT_TYPE_MASK                                                      0x00008000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT6_INT_TYPE_MASK                                                      0x00010000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT_IH_INT_TYPE_MASK                                                    0x00020000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK                                     0x00040000L
+//DMCUB_EXT_INTERRUPT_STATUS
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT                                          0x0
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT                                             0x8
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK                                            0x000000FFL
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK                                               0x0000FF00L
+//DMCUB_EXT_INTERRUPT_CTXID
+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT                                           0x0
+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK                                             0x0FFFFFFFL
+//DMCUB_EXT_INTERRUPT_ACK
+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT                                               0x0
+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK                                                 0x00000001L
+//DMCUB_INST_FETCH_FAULT_ADDR
+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT                                       0x0
+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK                                         0xFFFFFFFFL
+//DMCUB_DATA_WRITE_FAULT_ADDR
+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT                                       0x0
+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK                                         0xFFFFFFFFL
+//DMCUB_SEC_CNTL
+#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL__SHIFT                                                              0x0
+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT                                                              0x8
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT                                                                0x10
+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT                                                   0x11
+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT                                                        0x14
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT                                                         0x15
+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT                                                   0x18
+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT                                                   0x19
+#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL_MASK                                                                0x00000007L
+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK                                                                0x00003F00L
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK                                                                  0x00010000L
+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK                                                     0x00020000L
+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK                                                          0x00100000L
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK                                                           0x00200000L
+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK                                                     0x01000000L
+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK                                                     0x02000000L
+//DMCUB_MEM_CNTL
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT                                                            0x0
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT                                                             0x4
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK                                                              0x0000000FL
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK                                                               0x000000F0L
+//DMCUB_INBOX0_BASE_ADDRESS
+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT                                           0x0
+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK                                             0xFFFFFFFFL
+//DMCUB_INBOX0_SIZE
+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT                                                           0x0
+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX0_WPTR
+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX0_RPTR
+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX1_BASE_ADDRESS
+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT                                           0x0
+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK                                             0xFFFFFFFFL
+//DMCUB_INBOX1_SIZE
+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT                                                           0x0
+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX1_WPTR
+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX1_RPTR
+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_OUTBOX0_BASE_ADDRESS
+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT                                         0x0
+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK                                           0xFFFFFFFFL
+//DMCUB_OUTBOX0_SIZE
+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT                                                         0x0
+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX0_WPTR
+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX0_RPTR
+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_BASE_ADDRESS
+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT                                         0x0
+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_SIZE
+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT                                                         0x0
+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_WPTR
+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_RPTR
+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_TIMER_TRIGGER0
+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT                                                     0x0
+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK                                                       0xFFFFFFFFL
+//DMCUB_TIMER_TRIGGER1
+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT                                                     0x0
+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK                                                       0xFFFFFFFFL
+//DMCUB_TIMER_WINDOW
+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT                                                         0x0
+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK                                                           0x00000007L
+//DMCUB_SCRATCH0
+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH1
+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH2
+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH3
+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH4
+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH5
+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH6
+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH7
+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH8
+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH9
+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH10
+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT                                                               0x0
+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH11
+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT                                                               0x0
+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH12
+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT                                                               0x0
+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH13
+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT                                                               0x0
+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH14
+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT                                                               0x0
+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH15
+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT                                                               0x0
+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH16
+#define DMCUB_SCRATCH16__DMCUB_SCRATCH16__SHIFT                                                               0x0
+#define DMCUB_SCRATCH16__DMCUB_SCRATCH16_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH17
+#define DMCUB_SCRATCH17__DMCUB_SCRATCH17__SHIFT                                                               0x0
+#define DMCUB_SCRATCH17__DMCUB_SCRATCH17_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH18
+#define DMCUB_SCRATCH18__DMCUB_SCRATCH18__SHIFT                                                               0x0
+#define DMCUB_SCRATCH18__DMCUB_SCRATCH18_MASK                                                                 0xFFFFFFFFL
+//DMCUB_CNTL
+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT                                                                0x0
+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT                                                          0x8
+#define DMCUB_CNTL__DMCUB_ENABLE__SHIFT                                                                       0x10
+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT                                                      0x12
+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT                                                                 0x13
+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT                                                            0x14
+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK                                                                  0x000000FFL
+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK                                                            0x00000100L
+#define DMCUB_CNTL__DMCUB_ENABLE_MASK                                                                         0x00010000L
+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK                                                        0x00040000L
+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK                                                                   0x00080000L
+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK                                                              0x00100000L
+//DMCUB_GPINT_DATAIN0
+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAIN1
+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAOUT
+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK                                                         0xFFFFFFFFL
+//DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR
+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT                         0x0
+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK                           0xFFFFFFFFL
+//DMCUB_LS_WAKE_INT_ENABLE
+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT                                             0x0
+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK                                               0xFFFFFFFFL
+//DMCUB_MEM_PWR_CNTL
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT                                                        0x1
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT                                                          0x3
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT                                                        0x4
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK                                                          0x00000006L
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK                                                            0x00000008L
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK                                                          0x00000030L
+//DMCUB_TIMER_CURRENT
+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT                                                       0x0
+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK                                                         0xFFFFFFFFL
+//DMCUB_PROC_ID
+#define DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT                                                                   0x0
+#define DMCUB_PROC_ID__DMCUB_PROC_ID_MASK                                                                     0x0000FFFFL
+//DMCUB_CNTL2
+#define DMCUB_CNTL2__DMCUB_SOFT_RESET__SHIFT                                                                  0x0
+#define DMCUB_CNTL2__DMCUB_SOFT_RESET_MASK                                                                    0x00000001L
+//DMCUB_GPINT_DATAIN2
+#define DMCUB_GPINT_DATAIN2__DMCUB_GPINT_DATAIN2__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN2__DMCUB_GPINT_DATAIN2_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAIN3
+#define DMCUB_GPINT_DATAIN3__DMCUB_GPINT_DATAIN3__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN3__DMCUB_GPINT_DATAIN3_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAIN4
+#define DMCUB_GPINT_DATAIN4__DMCUB_GPINT_DATAIN4__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN4__DMCUB_GPINT_DATAIN4_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAIN5
+#define DMCUB_GPINT_DATAIN5__DMCUB_GPINT_DATAIN5__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN5__DMCUB_GPINT_DATAIN5_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAIN6
+#define DMCUB_GPINT_DATAIN6__DMCUB_GPINT_DATAIN6__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN6__DMCUB_GPINT_DATAIN6_MASK                                                         0xFFFFFFFFL
+//DMCUB_REGION3_TMR_AXI_SPACE
+#define DMCUB_REGION3_TMR_AXI_SPACE__DMCUB_REGION3_TMR_AXI_SPACE__SHIFT                                       0x0
+#define DMCUB_REGION3_TMR_AXI_SPACE__DMCUB_REGION3_TMR_AXI_SPACE_MASK                                         0x07L
+//DMCUB_SCRATCH19
+#define DMCUB_SCRATCH19__DMCUB_SCRATCH19__SHIFT                                                               0x0
+#define DMCUB_SCRATCH19__DMCUB_SCRATCH19_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH20
+#define DMCUB_SCRATCH20__DMCUB_SCRATCH20__SHIFT                                                               0x0
+#define DMCUB_SCRATCH20__DMCUB_SCRATCH20_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH21
+#define DMCUB_SCRATCH21__DMCUB_SCRATCH21__SHIFT                                                               0x0
+#define DMCUB_SCRATCH21__DMCUB_SCRATCH21_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH22
+#define DMCUB_SCRATCH22__DMCUB_SCRATCH22__SHIFT                                                               0x0
+#define DMCUB_SCRATCH22__DMCUB_SCRATCH22_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH23
+#define DMCUB_SCRATCH23__DMCUB_SCRATCH23__SHIFT                                                               0x0
+#define DMCUB_SCRATCH23__DMCUB_SCRATCH23_MASK                                                                 0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_wb0_dispdec_dwb_top_dispdec
+//DWB_ENABLE_CLK_CTRL
+#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE__SHIFT                                                                0x0
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS__SHIFT                                                    0x4
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS__SHIFT                                                    0x8
+#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL__SHIFT                                                          0xc
+#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE_MASK                                                                  0x00000001L
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS_MASK                                                      0x00000010L
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS_MASK                                                      0x00000100L
+#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL_MASK                                                            0x00003000L
+//DWB_MEM_PWR_CTRL
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE__SHIFT                                                   0xc
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE__SHIFT                                                   0x14
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE_MASK                                                     0x00003000L
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE_MASK                                                     0x00300000L
+//FC_MODE_CTRL
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN__SHIFT                                                              0x0
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE__SHIFT                                                            0x4
+#define FC_MODE_CTRL__FC_WINDOW_CROP_EN__SHIFT                                                                0x8
+#define FC_MODE_CTRL__FC_EYE_SELECTION__SHIFT                                                                 0xc
+#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY__SHIFT                                                           0x10
+#define FC_MODE_CTRL__FC_NEW_CONTENT__SHIFT                                                                   0x14
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT__SHIFT                                                      0x1f
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_MASK                                                                0x00000001L
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE_MASK                                                              0x00000030L
+#define FC_MODE_CTRL__FC_WINDOW_CROP_EN_MASK                                                                  0x00000100L
+#define FC_MODE_CTRL__FC_EYE_SELECTION_MASK                                                                   0x00003000L
+#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY_MASK                                                             0x00010000L
+#define FC_MODE_CTRL__FC_NEW_CONTENT_MASK                                                                     0x00100000L
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT_MASK                                                        0x80000000L
+//FC_FLOW_CTRL
+#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT__SHIFT                                                       0x0
+#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT_MASK                                                         0x00000FFFL
+//FC_WINDOW_START
+#define FC_WINDOW_START__FC_WINDOW_START_X__SHIFT                                                             0x0
+#define FC_WINDOW_START__FC_WINDOW_START_Y__SHIFT                                                             0x10
+#define FC_WINDOW_START__FC_WINDOW_START_X_MASK                                                               0x00001FFFL
+#define FC_WINDOW_START__FC_WINDOW_START_Y_MASK                                                               0x1FFF0000L
+//FC_WINDOW_SIZE
+#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH__SHIFT                                                                0x0
+#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT__SHIFT                                                               0x10
+#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH_MASK                                                                  0x00000FFFL
+#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT_MASK                                                                 0x0FFF0000L
+//FC_SOURCE_SIZE
+#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH__SHIFT                                                                0x0
+#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT__SHIFT                                                               0x10
+#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH_MASK                                                                  0x00007FFFL
+#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT_MASK                                                                 0x7FFF0000L
+//DWB_UPDATE_CTRL
+#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK__SHIFT                                                               0x0
+#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING__SHIFT                                                            0x4
+#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK_MASK                                                                 0x00000001L
+#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING_MASK                                                              0x00000010L
+//DWB_CRC_CTRL
+#define DWB_CRC_CTRL__DWB_CRC_EN__SHIFT                                                                       0x0
+#define DWB_CRC_CTRL__DWB_CRC_CONT_EN__SHIFT                                                                  0x4
+#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL__SHIFT                                                                  0x8
+#define DWB_CRC_CTRL__DWB_CRC_EN_MASK                                                                         0x00000001L
+#define DWB_CRC_CTRL__DWB_CRC_CONT_EN_MASK                                                                    0x00000010L
+#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL_MASK                                                                    0x00000300L
+//DWB_CRC_MASK_R_G
+#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK__SHIFT                                                             0x0
+#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK__SHIFT                                                           0x10
+#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK_MASK                                                               0x0000FFFFL
+#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK_MASK                                                             0xFFFF0000L
+//DWB_CRC_MASK_B_A
+#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK__SHIFT                                                            0x0
+#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK__SHIFT                                                               0x10
+#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK_MASK                                                              0x0000FFFFL
+#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK_MASK                                                                 0xFFFF0000L
+//DWB_CRC_VAL_R_G
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED__SHIFT                                                               0x0
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN__SHIFT                                                             0x10
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED_MASK                                                                 0x0000FFFFL
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN_MASK                                                               0xFFFF0000L
+//DWB_CRC_VAL_B_A
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE__SHIFT                                                              0x0
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A__SHIFT                                                                 0x10
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE_MASK                                                                0x0000FFFFL
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A_MASK                                                                   0xFFFF0000L
+//DWB_OUT_CTRL
+#define DWB_OUT_CTRL__OUT_FORMAT__SHIFT                                                                       0x0
+#define DWB_OUT_CTRL__OUT_DENORM__SHIFT                                                                       0x4
+#define DWB_OUT_CTRL__OUT_MAX__SHIFT                                                                          0x8
+#define DWB_OUT_CTRL__OUT_MIN__SHIFT                                                                          0x14
+#define DWB_OUT_CTRL__OUT_FORMAT_MASK                                                                         0x00000003L
+#define DWB_OUT_CTRL__OUT_DENORM_MASK                                                                         0x00000030L
+#define DWB_OUT_CTRL__OUT_MAX_MASK                                                                            0x0003FF00L
+#define DWB_OUT_CTRL__OUT_MIN_MASK                                                                            0x3FF00000L
+//DWB_MMHUBBUB_BACKPRESSURE_CNT_EN
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__SHIFT                             0x0
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN_MASK                               0x00000001L
+//DWB_MMHUBBUB_BACKPRESSURE_CNT
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE__SHIFT                                   0x0
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE_MASK                                     0x0000FFFFL
+//DWB_HOST_READ_CONTROL
+#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL__SHIFT                                              0x0
+#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL_MASK                                                0x000000FFL
+//DWB_OVERFLOW_STATUS
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG__SHIFT                                                    0x0
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK__SHIFT                                                     0x8
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK__SHIFT                                                    0xc
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS__SHIFT                                              0x10
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE__SHIFT                                                0x14
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG_MASK                                                      0x00000001L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK_MASK                                                       0x00000100L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK_MASK                                                      0x00001000L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS_MASK                                                0x00010000L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE_MASK                                                  0x00100000L
+//DWB_OVERFLOW_COUNTER
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE__SHIFT                                                   0x0
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT__SHIFT                                              0x4
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT__SHIFT                                              0x10
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE_MASK                                                     0x00000003L
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT_MASK                                                0x0000FFF0L
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT_MASK                                                0x0FFF0000L
+//DWB_SOFT_RESET
+#define DWB_SOFT_RESET__DWB_SOFT_RESET__SHIFT                                                                 0x0
+#define DWB_SOFT_RESET__DWB_SOFT_RESET_MASK                                                                   0x00000001L
+
+
+// addressBlock: dcn_dc_wb0_dispdec_dwbcp_dispdec
+//DWB_HDR_MULT_COEF
+#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF__SHIFT                                                           0x0
+#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF_MASK                                                             0x0007FFFFL
+//DWB_GAMUT_REMAP_MODE
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE__SHIFT                                                     0x0
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT__SHIFT                                             0x18
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_MASK                                                       0x00000003L
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT_MASK                                               0x03000000L
+//DWB_GAMUT_REMAP_COEF_FORMAT
+#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT__SHIFT                                       0x0
+#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT_MASK                                         0x00000001L
+//DWB_GAMUT_REMAPA_C11_C12
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C13_C14
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C21_C22
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C23_C24
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C31_C32
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C33_C34
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C11_C12
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C13_C14
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C21_C22
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C23_C24
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C31_C32
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C33_C34
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34_MASK                                                   0xFFFF0000L
+//DWB_OGAM_CONTROL
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE__SHIFT                                                                0x0
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT__SHIFT                                                              0x4
+#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE__SHIFT                                                         0x8
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT__SHIFT                                                        0x18
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT__SHIFT                                                      0x1c
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_MASK                                                                  0x00000003L
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_MASK                                                                0x00000010L
+#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE_MASK                                                           0x00000100L
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT_MASK                                                          0x03000000L
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT_MASK                                                        0x10000000L
+//DWB_OGAM_LUT_INDEX
+#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX__SHIFT                                                         0x0
+#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX_MASK                                                           0x000001FFL
+//DWB_OGAM_LUT_DATA
+#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA__SHIFT                                                           0x0
+#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA_MASK                                                             0x0003FFFFL
+//DWB_OGAM_LUT_CONTROL
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                                            0x0
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL__SHIFT                                              0x4
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG__SHIFT                                                    0x8
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL__SHIFT                                                    0xc
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE__SHIFT                                                 0x10
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK_MASK                                              0x00000007L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL_MASK                                                0x00000030L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG_MASK                                                      0x00000100L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL_MASK                                                      0x00001000L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE_MASK                                                   0x00010000L
+//DWB_OGAM_RAMA_START_CNTL_B
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B__SHIFT                                   0x0
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                           0x14
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                             0x07F00000L
+//DWB_OGAM_RAMA_START_CNTL_G
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G__SHIFT                                   0x0
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                           0x14
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                             0x07F00000L
+//DWB_OGAM_RAMA_START_CNTL_R
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R__SHIFT                                   0x0
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                           0x14
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                             0x07F00000L
+//DWB_OGAM_RAMA_START_BASE_CNTL_B
+#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                         0x0
+#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMA_START_SLOPE_CNTL_B
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                       0x0
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMA_START_BASE_CNTL_G
+#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                         0x0
+#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMA_START_SLOPE_CNTL_G
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                       0x0
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMA_START_BASE_CNTL_R
+#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                         0x0
+#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMA_START_SLOPE_CNTL_R
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                       0x0
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL1_B
+#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL2_B
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B__SHIFT                                      0x0
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                                0x10
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMA_END_CNTL1_G
+#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL2_G
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G__SHIFT                                      0x0
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                                0x10
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMA_END_CNTL1_R
+#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL2_R
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R__SHIFT                                      0x0
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                                0x10
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMA_OFFSET_B
+#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B__SHIFT                                                 0x0
+#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMA_OFFSET_G
+#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G__SHIFT                                                 0x0
+#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMA_OFFSET_R
+#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R__SHIFT                                                 0x0
+#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMA_REGION_0_1
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_2_3
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_4_5
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_6_7
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_8_9
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_10_11
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_12_13
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_14_15
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_16_17
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_18_19
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_20_21
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_22_23
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_24_25
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_26_27
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_28_29
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_30_31
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_32_33
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_START_CNTL_B
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B__SHIFT                                   0x0
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                           0x14
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                             0x07F00000L
+//DWB_OGAM_RAMB_START_CNTL_G
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G__SHIFT                                   0x0
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                           0x14
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                             0x07F00000L
+//DWB_OGAM_RAMB_START_CNTL_R
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R__SHIFT                                   0x0
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                           0x14
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                             0x07F00000L
+//DWB_OGAM_RAMB_START_BASE_CNTL_B
+#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                         0x0
+#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMB_START_SLOPE_CNTL_B
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                       0x0
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMB_START_BASE_CNTL_G
+#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                         0x0
+#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMB_START_SLOPE_CNTL_G
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                       0x0
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMB_START_BASE_CNTL_R
+#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                         0x0
+#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMB_START_SLOPE_CNTL_R
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                       0x0
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL1_B
+#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL2_B
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B__SHIFT                                      0x0
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                                0x10
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMB_END_CNTL1_G
+#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL2_G
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G__SHIFT                                      0x0
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                                0x10
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMB_END_CNTL1_R
+#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL2_R
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R__SHIFT                                      0x0
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                                0x10
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMB_OFFSET_B
+#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B__SHIFT                                                 0x0
+#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMB_OFFSET_G
+#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G__SHIFT                                                 0x0
+#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMB_OFFSET_R
+#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R__SHIFT                                                 0x0
+#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMB_REGION_0_1
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_2_3
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_4_5
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_6_7
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_8_9
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_10_11
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_12_13
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_14_15
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_16_17
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_18_19
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_20_21
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_22_23
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_24_25
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_26_27
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_28_29
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_30_31
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_32_33
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                              0x70000000L
+
+
+//VGA_MEM_WRITE_PAGE_ADDR
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT                                              0x0
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT                                              0x10
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK                                                0x000003FFL
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK                                                0x03FF0000L
+//VGA_MEM_READ_PAGE_ADDR
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT                                                0x0
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT                                                0x10
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK                                                  0x000003FFL
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK                                                  0x03FF0000L
+//VGA_RENDER_CONTROL
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT                                                             0x0
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT                                                             0x5
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT                                                    0x7
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT                                                 0x8
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT                                                           0x10
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT                                                              0x18
+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT                                           0x19
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK                                                               0x0000001FL
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK                                                               0x00000060L
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK                                                      0x00000080L
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK                                                   0x00000100L
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK                                                             0x00030000L
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK                                                                0x01000000L
+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK                                             0x02000000L
+//VGA_SEQUENCER_RESET_CONTROL
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x0
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x1
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x2
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x3
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x4
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x5
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0x8
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0x9
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xa
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xb
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xc
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xd
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT                                      0x10
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT                             0x11
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT                                0x12
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000001L
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000002L
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000004L
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000008L
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000010L
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000020L
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000100L
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000200L
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000400L
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000800L
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00001000L
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00002000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK                                        0x00010000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK                               0x00020000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK                                  0x00FC0000L
+//VGA_MODE_CONTROL
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT                                                               0x0
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT                                                  0x4
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT                                                     0x8
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT                                                      0x10
+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT                                                    0x18
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK                                                                 0x00000001L
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK                                                    0x00000030L
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK                                                       0x00000100L
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK                                                        0x00010000L
+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK                                                      0x01000000L
+//VGA_SURFACE_PITCH_SELECT
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT                                             0x0
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT                                            0x8
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK                                               0x00000003L
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK                                              0x00000300L
+//VGA_MEMORY_BASE_ADDRESS
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT                                               0x0
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK                                                 0xFFFFFFFFL
+//VGA_DISPBUF1_SURFACE_ADDR
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT                                           0x0
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK                                             0x01FFFFFFL
+//VGA_DISPBUF2_SURFACE_ADDR
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT                                           0x0
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK                                             0x01FFFFFFL
+//VGA_MEMORY_BASE_ADDRESS_HIGH
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT                                     0x0
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK                                       0x0000FFFFL
+//VGA_HDP_CONTROL
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT                                                        0x0
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT                                                            0x4
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT                                                         0x8
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT                                                                0x10
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT                                                        0x18
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK                                                          0x00000001L
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK                                                              0x00000010L
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK                                                           0x00000100L
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK                                                                  0x00010000L
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK                                                          0x01000000L
+//VGA_CACHE_CONTROL
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT                                                 0x0
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT                                                      0x8
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT                                                  0x10
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT                                                          0x14
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT                                                        0x18
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK                                                   0x00000001L
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK                                                        0x00000100L
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK                                                    0x00010000L
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK                                                            0x00100000L
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK                                                          0x3F000000L
+//D1VGA_CONTROL
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT                                                                    0x18
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D1VGA_CONTROL__D1VGA_ROTATE_MASK                                                                      0x03000000L
+//D2VGA_CONTROL
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT                                                                    0x18
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D2VGA_CONTROL__D2VGA_ROTATE_MASK                                                                      0x03000000L
+//VGA_STATUS
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT                                                              0x0
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT                                                              0x1
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT                                                          0x2
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT                                                       0x3
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK                                                                0x00000001L
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK                                                                0x00000002L
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK                                                            0x00000004L
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK                                                         0x00000008L
+//VGA_INTERRUPT_CONTROL
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT                                                 0x0
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT                                                 0x8
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT                                             0x10
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT                                          0x18
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK                                                   0x00000001L
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK                                                   0x00000100L
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK                                               0x00010000L
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK                                            0x01000000L
+//VGA_STATUS_CLEAR
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT                                                     0x0
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT                                                     0x8
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT                                                 0x10
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT                                              0x18
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK                                                       0x00000001L
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK                                                       0x00000100L
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK                                                   0x00010000L
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK                                                0x01000000L
+//VGA_INTERRUPT_STATUS
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT                                                0x0
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT                                                0x1
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT                                            0x2
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT                                         0x3
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK                                                  0x00000001L
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK                                                  0x00000002L
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK                                              0x00000004L
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK                                           0x00000008L
+//VGA_MAIN_CONTROL
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT                                                             0x0
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT                                                     0x3
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT                                        0x5
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT                                       0x8
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT                                                0xc
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT                                        0x10
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT                                          0x18
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT                                             0x1a
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT                                                       0x1d
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT                                0x1f
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK                                                               0x00000003L
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK                                                       0x00000018L
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK                                          0x000000E0L
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK                                         0x00000300L
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK                                                  0x0000F000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK                                          0x00030000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK                                            0x03000000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK                                               0x04000000L
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK                                                         0x20000000L
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK                                  0x80000000L
+//VGA_TEST_CONTROL
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT                                                              0x0
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT                                                        0x8
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT                                                         0x10
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT                                               0x18
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK                                                                0x00000001L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK                                                          0x00000100L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK                                                           0x00010000L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK                                                 0x01000000L
+//VGA_QOS_CTRL
+#define VGA_QOS_CTRL__VGA_READ_QOS__SHIFT                                                                     0x0
+#define VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT                                                                    0x4
+#define VGA_QOS_CTRL__VGA_READ_QOS_MASK                                                                       0x0000000FL
+#define VGA_QOS_CTRL__VGA_WRITE_QOS_MASK                                                                      0x000000F0L
+//CRTC8_IDX
+#define CRTC8_IDX__VCRTC_IDX__SHIFT                                                                           0x0
+#define CRTC8_IDX__VCRTC_IDX_MASK                                                                             0x3FL
+//CRTC8_DATA
+#define CRTC8_DATA__VCRTC_DATA__SHIFT                                                                         0x0
+#define CRTC8_DATA__VCRTC_DATA_MASK                                                                           0xFFL
+//GENFC_WT
+#define GENFC_WT__VSYNC_SEL_W__SHIFT                                                                          0x3
+#define GENFC_WT__VSYNC_SEL_W_MASK                                                                            0x08L
+//GENS1
+#define GENS1__NO_DISPLAY__SHIFT                                                                              0x0
+#define GENS1__VGA_VSTATUS__SHIFT                                                                             0x3
+#define GENS1__PIXEL_READ_BACK__SHIFT                                                                         0x4
+#define GENS1__NO_DISPLAY_MASK                                                                                0x01L
+#define GENS1__VGA_VSTATUS_MASK                                                                               0x08L
+#define GENS1__PIXEL_READ_BACK_MASK                                                                           0x30L
+//ATTRDW
+#define ATTRDW__ATTR_DATA__SHIFT                                                                              0x0
+#define ATTRDW__ATTR_DATA_MASK                                                                                0xFFL
+//ATTRX
+#define ATTRX__ATTR_IDX__SHIFT                                                                                0x0
+#define ATTRX__ATTR_PAL_RW_ENB__SHIFT                                                                         0x5
+#define ATTRX__ATTR_IDX_MASK                                                                                  0x1FL
+#define ATTRX__ATTR_PAL_RW_ENB_MASK                                                                           0x20L
+//ATTRDR
+#define ATTRDR__ATTR_DATA__SHIFT                                                                              0x0
+#define ATTRDR__ATTR_DATA_MASK                                                                                0xFFL
+//GENMO_WT
+#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT                                                                 0x0
+#define GENMO_WT__VGA_RAM_EN__SHIFT                                                                           0x1
+#define GENMO_WT__VGA_CKSEL__SHIFT                                                                            0x2
+#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT                                                                    0x5
+#define GENMO_WT__VGA_HSYNC_POL__SHIFT                                                                        0x6
+#define GENMO_WT__VGA_VSYNC_POL__SHIFT                                                                        0x7
+#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK                                                                   0x01L
+#define GENMO_WT__VGA_RAM_EN_MASK                                                                             0x02L
+#define GENMO_WT__VGA_CKSEL_MASK                                                                              0x0CL
+#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK                                                                      0x20L
+#define GENMO_WT__VGA_HSYNC_POL_MASK                                                                          0x40L
+#define GENMO_WT__VGA_VSYNC_POL_MASK                                                                          0x80L
+//GENS0
+#define GENS0__SENSE_SWITCH__SHIFT                                                                            0x4
+#define GENS0__CRT_INTR__SHIFT                                                                                0x7
+#define GENS0__SENSE_SWITCH_MASK                                                                              0x10L
+#define GENS0__CRT_INTR_MASK                                                                                  0x80L
+//GENENB
+#define GENENB__BLK_IO_BASE__SHIFT                                                                            0x0
+#define GENENB__BLK_IO_BASE_MASK                                                                              0xFFL
+//SEQ8_IDX
+#define SEQ8_IDX__SEQ_IDX__SHIFT                                                                              0x0
+#define SEQ8_IDX__SEQ_IDX_MASK                                                                                0x07L
+//SEQ8_DATA
+#define SEQ8_DATA__SEQ_DATA__SHIFT                                                                            0x0
+#define SEQ8_DATA__SEQ_DATA_MASK                                                                              0xFFL
+//DAC_MASK
+#define DAC_MASK__DAC_MASK__SHIFT                                                                             0x0
+#define DAC_MASK__DAC_MASK_MASK                                                                               0xFFL
+//DAC_R_INDEX
+#define DAC_R_INDEX__DAC_R_INDEX__SHIFT                                                                       0x0
+#define DAC_R_INDEX__DAC_R_INDEX_MASK                                                                         0xFFL
+//DAC_W_INDEX
+#define DAC_W_INDEX__DAC_W_INDEX__SHIFT                                                                       0x0
+#define DAC_W_INDEX__DAC_W_INDEX_MASK                                                                         0xFFL
+//DAC_DATA
+#define DAC_DATA__DAC_DATA__SHIFT                                                                             0x0
+#define DAC_DATA__DAC_DATA_MASK                                                                               0x3FL
+//GENFC_RD
+#define GENFC_RD__VSYNC_SEL_R__SHIFT                                                                          0x3
+#define GENFC_RD__VSYNC_SEL_R_MASK                                                                            0x08L
+//GENMO_RD
+#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT                                                                 0x0
+#define GENMO_RD__VGA_RAM_EN__SHIFT                                                                           0x1
+#define GENMO_RD__VGA_CKSEL__SHIFT                                                                            0x2
+#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT                                                                    0x5
+#define GENMO_RD__VGA_HSYNC_POL__SHIFT                                                                        0x6
+#define GENMO_RD__VGA_VSYNC_POL__SHIFT                                                                        0x7
+#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK                                                                   0x01L
+#define GENMO_RD__VGA_RAM_EN_MASK                                                                             0x02L
+#define GENMO_RD__VGA_CKSEL_MASK                                                                              0x0CL
+#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK                                                                      0x20L
+#define GENMO_RD__VGA_HSYNC_POL_MASK                                                                          0x40L
+#define GENMO_RD__VGA_VSYNC_POL_MASK                                                                          0x80L
+//GRPH8_IDX
+#define GRPH8_IDX__GRPH_IDX__SHIFT                                                                            0x0
+#define GRPH8_IDX__GRPH_IDX_MASK                                                                              0x0FL
+//GRPH8_DATA
+#define GRPH8_DATA__GRPH_DATA__SHIFT                                                                          0x0
+#define GRPH8_DATA__GRPH_DATA_MASK                                                                            0xFFL
+//CRTC8_IDX_1
+#define CRTC8_IDX_1__VCRTC_IDX__SHIFT                                                                         0x0
+#define CRTC8_IDX_1__VCRTC_IDX_MASK                                                                           0x3FL
+//CRTC8_DATA_1
+#define CRTC8_DATA_1__VCRTC_DATA__SHIFT                                                                       0x0
+#define CRTC8_DATA_1__VCRTC_DATA_MASK                                                                         0xFFL
+//GENFC_WT_1
+#define GENFC_WT_1__VSYNC_SEL_W__SHIFT                                                                        0x3
+#define GENFC_WT_1__VSYNC_SEL_W_MASK                                                                          0x08L
+//GENS1_1
+#define GENS1_1__NO_DISPLAY__SHIFT                                                                            0x0
+#define GENS1_1__VGA_VSTATUS__SHIFT                                                                           0x3
+#define GENS1_1__PIXEL_READ_BACK__SHIFT                                                                       0x4
+#define GENS1_1__NO_DISPLAY_MASK                                                                              0x01L
+#define GENS1_1__VGA_VSTATUS_MASK                                                                             0x08L
+#define GENS1_1__PIXEL_READ_BACK_MASK                                                                         0x30L
+//D3VGA_CONTROL
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT                                                                    0x18
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D3VGA_CONTROL__D3VGA_ROTATE_MASK                                                                      0x03000000L
+//D4VGA_CONTROL
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT                                                                    0x18
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D4VGA_CONTROL__D4VGA_ROTATE_MASK                                                                      0x03000000L
+//D5VGA_CONTROL
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT                                                                    0x18
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D5VGA_CONTROL__D5VGA_ROTATE_MASK                                                                      0x03000000L
+//D6VGA_CONTROL
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT                                                                    0x18
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D6VGA_CONTROL__D6VGA_ROTATE_MASK                                                                      0x03000000L
+//VGA_SOURCE_SELECT
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT                                                            0x0
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT                                                            0x8
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK                                                              0x00000007L
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK                                                              0x00000700L
+
+
+// addressBlock: dcn_dc_mmhubbub_vgaif_dispdec
+//MCIF_CONTROL
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT                                                   0x1e
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT                                              0x1f
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK                                                     0x40000000L
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK                                                0x80000000L
+//MCIF_WRITE_COMBINE_CONTROL
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT                                         0x0
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK                                           0x000003FFL
+//MCIF_PHASE0_OUTSTANDING_COUNTER
+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER__SHIFT                               0x0
+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
+//MCIF_PHASE1_OUTSTANDING_COUNTER
+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER__SHIFT                               0x0
+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
+//MCIF_PHASE2_OUTSTANDING_COUNTER
+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER__SHIFT                               0x0
+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
+
+
+// addressBlock: dcn_dc_mmhubbub_mcif_wb0_dispdec
+//MCIF_WB_BUFMGR_SW_CONTROL
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT                                               0x0
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT                                            0x4
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT                                           0x5
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT                                      0x6
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT                                    0x7
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT                                              0x8
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT                                           0x18
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK                                                 0x00000001L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK                                              0x00000010L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK                                             0x00000020L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK                                        0x00000040L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK                                      0x00000080L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK                                                0x00000F00L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK                                             0x01000000L
+//MCIF_WB_BUFMGR_STATUS
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT                                           0x0
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT                                            0x1
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT                                    0x2
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT                                                  0x4
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT                                             0x7
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT                                                   0x8
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT                                               0xc
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT                                                 0x1c
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK                                             0x00000001L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK                                              0x00000002L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK                                      0x00000004L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK                                                    0x00000070L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK                                               0x00000080L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK                                                     0x00000F00L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK                                                 0x01FFF000L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK                                                   0x70000000L
+//MCIF_WB_BUF_PITCH
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT                                                      0x8
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT                                                    0x18
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK                                                        0x0000FF00L
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK                                                      0xFF000000L
+//MCIF_WB_BUF_1_STATUS
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_1_STATUS2
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_BUF_2_STATUS
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_2_STATUS2
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_BUF_3_STATUS
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_3_STATUS2
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_BUF_4_STATUS
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_4_STATUS2
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_ARBITRATION_CONTROL
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT                                  0x0
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT                                            0x14
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK                                    0x00000003L
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK                                              0xFFF00000L
+//MCIF_WB_SCLK_CHANGE
+#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT                                                    0x0
+#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK                                                      0x00000001L
+//MCIF_WB_TEST_DEBUG_INDEX
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT                                             0x0
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT                                          0x8
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK                                               0x000000FFL
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK                                            0x00000100L
+//MCIF_WB_TEST_DEBUG_DATA
+#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT                                               0x0
+#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK                                                 0xFFFFFFFFL
+//MCIF_WB_BUF_1_ADDR_Y
+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_1_ADDR_C
+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_2_ADDR_Y
+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_2_ADDR_C
+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_3_ADDR_Y
+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_3_ADDR_C
+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_4_ADDR_Y
+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_4_ADDR_C
+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUFMGR_VCE_CONTROL
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT                                     0x0
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT                                          0x4
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT                                         0x5
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT                                    0x6
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT                                            0x8
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT                                          0x10
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK                                       0x00000001L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK                                            0x00000010L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK                                           0x00000020L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK                                      0x00000040L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK                                              0x00000F00L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK                                            0x1FFF0000L
+//MCIF_WB_NB_PSTATE_CONTROL
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT                                           0x1
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK                                             0x00000002L
+//MCIF_WB_CLOCK_GATER_CONTROL
+#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT                                  0x0
+#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK                                    0x00000001L
+//MCIF_WB_SELF_REFRESH_CONTROL
+#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT                                            0x1
+#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK                                              0x00000002L
+//MULTI_LEVEL_QOS_CTRL
+#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT                                                0x0
+#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK                                                  0x003FFFFFL
+//MCIF_WB_SECURITY_LEVEL
+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL__SHIFT                                                 0x0
+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SPACE__SHIFT                                                          0x4
+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL_MASK                                                   0x00000007L
+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SPACE_MASK                                                            0x00000070L
+//MCIF_WB_BUF_LUMA_SIZE
+#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT                                                   0x0
+#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK                                                     0x000FFFFFL
+//MCIF_WB_BUF_CHROMA_SIZE
+#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT                                               0x0
+#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK                                                 0x000FFFFFL
+//MCIF_WB_BUF_1_ADDR_Y_HIGH
+#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_1_ADDR_C_HIGH
+#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_2_ADDR_Y_HIGH
+#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_2_ADDR_C_HIGH
+#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_3_ADDR_Y_HIGH
+#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_3_ADDR_C_HIGH
+#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_4_ADDR_Y_HIGH
+#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_4_ADDR_C_HIGH
+#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_1_RESOLUTION
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_BUF_2_RESOLUTION
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_BUF_3_RESOLUTION
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_BUF_4_RESOLUTION
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_PSTATE_CHANGE_DURATION_VBI
+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_UCLK_PSTATE_CHANGE_DURATION_VBI__SHIFT                    0x0
+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_FCLK_PSTATE_CHANGE_DURATION_VBI__SHIFT                    0x10
+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_UCLK_PSTATE_CHANGE_DURATION_VBI_MASK                      0x0000FFFFL
+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_FCLK_PSTATE_CHANGE_DURATION_VBI_MASK                      0xFFFF0000L
+//MCIF_WB_VMID_CONTROL
+#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID__SHIFT                                                           0x0
+#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID_MASK                                                             0x0000000FL
+//MCIF_WB_MIN_TTO
+#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO__SHIFT                                                               0x0
+#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO_MASK                                                                 0x0007FFFFL
+
+
+//MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT                        0x0
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT                           0x18
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_TYPE__SHIFT                           0x1f
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK                          0x001FFFFFL
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK                             0x07000000L
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_TYPE_MASK                             0x80000000L
+//MCIF_WB_WATERMARK
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT                                                       0x0
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK__SHIFT                                                  0x18
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK                                                         0x001FFFFFL
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK_MASK                                                    0x07000000L
+//MMHUBBUB_WARMUP_CONFIG
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS__SHIFT                                                    0x10
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID__SHIFT                                                   0x14
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS_MASK                                                      0x000F0000L
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID_MASK                                                     0x00F00000L
+//MMHUBBUB_WARMUP_CONTROL_STATUS
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN__SHIFT                                             0x0
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN__SHIFT                                      0x4
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS__SHIFT                                  0x5
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK__SHIFT                                     0x6
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR__SHIFT                                       0x8
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN_MASK                                               0x00000001L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN_MASK                                        0x00000010L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS_MASK                                    0x00000020L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK_MASK                                       0x00000040L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR_MASK                                         0x03FFFF00L
+//MMHUBBUB_WARMUP_BASE_ADDR_LOW
+#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW__SHIFT                                   0x0
+#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW_MASK                                     0xFFFFFFFFL
+//MMHUBBUB_WARMUP_BASE_ADDR_HIGH
+#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH__SHIFT                                 0x0
+#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH_MASK                                   0x000007FFL
+//MMHUBBUB_WARMUP_ADDR_REGION
+#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION__SHIFT                                       0x0
+#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION_MASK                                         0x07FFFFFFL
+//MMHUBBUB_MIN_TTO
+#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO__SHIFT                                                             0x0
+#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO_MASK                                                               0x0007FFFFL
+//MMHUBBUB_CTRL
+#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE__SHIFT                                                            0x0
+#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE_MASK                                                              0x00000003L
+//WBIF_SMU_WM_CONTROL
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL__SHIFT                                                        0x14
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ__SHIFT                                                        0x16
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL_MASK                                                          0x00300000L
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ_MASK                                                          0x00400000L
+//WBIF0_MISC_CTRL
+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT                                             0x0
+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT                                                     0x10
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT                                                   0x18
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT                                                0x19
+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK                                               0x000003FFL
+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK                                                       0x00010000L
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK                                                     0x01000000L
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK                                                  0x02000000L
+//WBIF0_PHASE0_OUTSTANDING_COUNTER
+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT                          0x0
+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL
+//WBIF0_PHASE1_OUTSTANDING_COUNTER
+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT                          0x0
+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL
+//VGA_SRC_SPLIT_CNTL
+#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL__SHIFT                                                              0x0
+#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL_MASK                                                                0x00000003L
+//MMHUBBUB_MEM_PWR_STATUS
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT                                         0x0
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT                                         0x2
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT                                       0x4
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT                                       0x6
+#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT                                                     0x1f
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK                                           0x00000003L
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK                                           0x0000000CL
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK                                         0x00000030L
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK                                         0x000000C0L
+#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK                                                       0x80000000L
+//MMHUBBUB_MEM_PWR_CNTL
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT                                                       0x0
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT                                                         0x1
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT                                                 0x2
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT                                                   0x4
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT                                              0x5
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT                                               0x7
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT                                             0x8
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK                                                         0x00000001L
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK                                                           0x00000002L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK                                                   0x0000000CL
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK                                                     0x00000010L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK                                                0x00000060L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK                                                 0x00000080L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK                                               0x00000100L
+//MMHUBBUB_CLOCK_CNTL
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT                                               0x5
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS__SHIFT                                                  0x6
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS__SHIFT                                                   0x7
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT                                                    0x8
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT                                                  0x9
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT                                                   0xa
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_FGCG_REP_DIS__SHIFT                                                     0x11
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK                                                 0x00000020L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS_MASK                                                    0x00000040L
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS_MASK                                                     0x00000080L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK                                                      0x00000100L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK                                                    0x00000200L
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK                                                     0x00000400L
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_FGCG_REP_DIS_MASK                                                       0x00020000L
+//MMHUBBUB_SOFT_RESET
+#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET__SHIFT                                                            0x0
+#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET__SHIFT                                                          0x1
+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT                                                          0x2
+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET__SHIFT                                                          0x8
+#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET_MASK                                                              0x00000001L
+#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET_MASK                                                            0x00000002L
+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK                                                            0x00000004L
+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET_MASK                                                            0x00000100L
+//DMU_IF_ERR_STATUS
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT                                                      0x0
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT                                                  0x4
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK                                                        0x00000001L
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK                                                    0x00000010L
+//MMHUBBUB_CLIENT_UNIT_ID
+#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID__SHIFT                                                           0x0
+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID__SHIFT                                                         0x8
+#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID_MASK                                                             0x0000003FL
+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID_MASK                                                           0x00003F00L
+//MMHUBBUB_WARMUP_VMID_CONTROL
+#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID__SHIFT                                           0x0
+#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID_MASK                                             0x0000000FL
+
+
+// addressBlock: dcn_dc_hda_azf0controller_dispdec
+//AZALIA_CONTROLLER_CLOCK_GATING
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT                                            0x0
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT                                                 0x4
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK                                              0x00000001L
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK                                                   0x00000010L
+//AZALIA_AUDIO_DTO
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT                                                       0x0
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT                                                      0x10
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK                                                         0x0000FFFFL
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK                                                        0xFFFF0000L
+//AZALIA_AUDIO_DTO_CONTROL
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT                                               0x8
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK                                                 0x00000300L
+//AZALIA_SOCCLK_CONTROL
+#define AZALIA_SOCCLK_CONTROL__DRM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT                                           0x0
+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT                                  0x1
+#define AZALIA_SOCCLK_CONTROL__DRM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK                                             0x00000001L
+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK                                    0x00000002L
+//AZALIA_UNDERFLOW_FILLER_SAMPLE
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT                                 0x0
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK                                   0xFFFFFFFFL
+//AZALIA_DATA_DMA_CONTROL
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT                                                    0x0
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT                                              0x2
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT                                                  0x4
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT                                            0x6
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT                                          0x10
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT                                              0x11
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK                                                      0x00000003L
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK                                                0x0000000CL
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK                                                    0x00000030L
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK                                              0x000000C0L
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK                                            0x00010000L
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK                                                0x00020000L
+//AZALIA_BDL_DMA_CONTROL
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT                                                      0x0
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT                                                0x2
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT                                                    0x4
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT                                              0x6
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK                                                        0x00000003L
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK                                                  0x0000000CL
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK                                                      0x00000030L
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK                                                0x000000C0L
+//AZALIA_RIRB_AND_DP_CONTROL
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT                                                     0x0
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT                                                   0x4
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT                                             0x5
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK                                                       0x00000001L
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK                                                     0x00000010L
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK                                               0x000001E0L
+//AZALIA_CORB_DMA_CONTROL
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT                                                    0x0
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT                                                  0x4
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK                                                      0x00000001L
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK                                                    0x00000010L
+//AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT            0x0
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK              0xFFFFFFFFL
+//AZALIA_CYCLIC_BUFFER_SYNC
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT                                           0x0
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK                                             0x00000001L
+//AZALIA_GLOBAL_CAPABILITIES
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT                               0x1
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK                                 0x00000006L
+//AZALIA_OUTPUT_PAYLOAD_CAPABILITY
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT                                    0x0
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT                                                   0x10
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK                                      0x0000FFFFL
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK                                                     0xFFFF0000L
+//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT                                     0x0
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT                                    0x8
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT                               0x10
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK                                       0x000000FFL
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK                                      0x00000100L
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK                                 0x00FF0000L
+//AZALIA_INPUT_PAYLOAD_CAPABILITY
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT                                      0x0
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT                                                     0x10
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK                                        0x0000FFFFL
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK                                                       0xFFFF0000L
+//AZALIA_INPUT_CRC0_CONTROL0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L
+//AZALIA_INPUT_CRC0_CONTROL1
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CONTROL2
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL
+//AZALIA_INPUT_CRC0_CONTROL3
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L
+//AZALIA_INPUT_CRC0_RESULT
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CONTROL0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L
+//AZALIA_INPUT_CRC1_CONTROL1
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CONTROL2
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL
+//AZALIA_INPUT_CRC1_CONTROL3
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L
+//AZALIA_INPUT_CRC1_RESULT
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL
+//AZALIA_CRC0_CONTROL0
+#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT                                                                   0x0
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc
+#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK                                                                     0x00000001L
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L
+//AZALIA_CRC0_CONTROL1
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL
+//AZALIA_CRC0_CONTROL2
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL
+//AZALIA_CRC0_CONTROL3
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L
+//AZALIA_CRC0_RESULT
+#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT                                                                 0x0
+#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL
+//AZALIA_CRC1_CONTROL0
+#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT                                                                   0x0
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc
+#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK                                                                     0x00000001L
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L
+//AZALIA_CRC1_CONTROL1
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL
+//AZALIA_CRC1_CONTROL2
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL
+//AZALIA_CRC1_CONTROL3
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L
+//AZALIA_CRC1_RESULT
+#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT                                                                 0x0
+#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL
+//AZALIA_MEM_PWR_CTRL
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT                                                          0x0
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT                                                            0x2
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT                                            0x3
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT                                              0x5
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT                                            0x6
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT                                              0x8
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT                                            0x9
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT                                              0xb
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT                                            0xc
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT                                              0xe
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT                                            0xf
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT                                              0x11
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT                                            0x12
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT                                              0x14
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT                                                       0x1c
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK                                                            0x00000003L
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK                                                              0x00000004L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK                                              0x00000018L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK                                                0x00000020L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK                                              0x000000C0L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK                                                0x00000100L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK                                              0x00000600L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK                                                0x00000800L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK                                              0x00003000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK                                                0x00004000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK                                              0x00018000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK                                                0x00020000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK                                              0x000C0000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK                                                0x00100000L
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK                                                         0x30000000L
+//AZALIA_MEM_PWR_STATUS
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT                                                        0x0
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT                                          0x2
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT                                          0x4
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT                                          0x6
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT                                          0x8
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT                                          0xa
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT                                          0xc
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK                                                          0x00000003L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK                                            0x0000000CL
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK                                            0x00000030L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK                                            0x000000C0L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK                                            0x00000300L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK                                            0x00000C00L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK                                            0x00003000L
+
+
+// addressBlock: dcn_dc_hda_azf0root_dispdec
+//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL
+//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL
+//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT                                       0x0
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT                                0x4
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK                                         0x00000007L
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK                                  0x00000070L
+//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT                        0x0
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK                          0x0000003FL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL
+//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT                                           0x0
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                           0x4
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK                                             0x00000007L
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                             0x00000010L
+//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT                               0x0
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT               0x4
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK                                 0x00000007L
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                 0x00000010L
+//AZALIA_F0_GTC_GROUP_OFFSET0
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET1
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET2
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET3
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET4
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET5
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET6
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK                                                   0xFFFFFFFFL
+//REG_DC_AUDIO_PORT_CONNECTIVITY
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT                                          0x0
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                          0x4
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK                                            0x00000007L
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                            0x00000010L
+//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT                              0x0
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT              0x4
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK                                0x00000007L
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                0x00000010L
+
+
+// addressBlock: dcn_dc_hda_az_misc_dispdec
+//AZ_CLOCK_CNTL
+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT                                                       0x0
+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT                                                              0x8
+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT                                                         0x10
+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT                                                              0x18
+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK                                                         0x00000001L
+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK                                                                0x00000100L
+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK                                                           0x00010000L
+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK                                                                0x1F000000L
+
+
+// addressBlock: dcn_dc_hda_azf0stream0_dispdec
+//AZF0STREAM0_AZALIA_STREAM_INDEX
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM0_AZALIA_STREAM_DATA
+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream1_dispdec
+//AZF0STREAM1_AZALIA_STREAM_INDEX
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM1_AZALIA_STREAM_DATA
+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream2_dispdec
+//AZF0STREAM2_AZALIA_STREAM_INDEX
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM2_AZALIA_STREAM_DATA
+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream3_dispdec
+//AZF0STREAM3_AZALIA_STREAM_INDEX
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM3_AZALIA_STREAM_DATA
+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream4_dispdec
+//AZF0STREAM4_AZALIA_STREAM_INDEX
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM4_AZALIA_STREAM_DATA
+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream5_dispdec
+//AZF0STREAM5_AZALIA_STREAM_INDEX
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM5_AZALIA_STREAM_DATA
+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream6_dispdec
+//AZF0STREAM6_AZALIA_STREAM_INDEX
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM6_AZALIA_STREAM_DATA
+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream7_dispdec
+//AZF0STREAM7_AZALIA_STREAM_INDEX
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM7_AZALIA_STREAM_DATA
+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream8_dispdec
+//AZF0STREAM8_AZALIA_STREAM_INDEX
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM8_AZALIA_STREAM_DATA
+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream9_dispdec
+//AZF0STREAM9_AZALIA_STREAM_INDEX
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM9_AZALIA_STREAM_DATA
+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream10_dispdec
+//AZF0STREAM10_AZALIA_STREAM_INDEX
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM10_AZALIA_STREAM_DATA
+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream11_dispdec
+//AZF0STREAM11_AZALIA_STREAM_INDEX
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM11_AZALIA_STREAM_DATA
+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream12_dispdec
+//AZF0STREAM12_AZALIA_STREAM_INDEX
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM12_AZALIA_STREAM_DATA
+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream13_dispdec
+//AZF0STREAM13_AZALIA_STREAM_INDEX
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM13_AZALIA_STREAM_DATA
+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream14_dispdec
+//AZF0STREAM14_AZALIA_STREAM_INDEX
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM14_AZALIA_STREAM_DATA
+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream15_dispdec
+//AZF0STREAM15_AZALIA_STREAM_INDEX
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM15_AZALIA_STREAM_DATA
+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint0_dispdec
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint1_dispdec
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint2_dispdec
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint3_dispdec
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint4_dispdec
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint5_dispdec
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint6_dispdec
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint7_dispdec
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint0_dispdec
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint1_dispdec
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint2_dispdec
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint3_dispdec
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint4_dispdec
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint5_dispdec
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint6_dispdec
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint7_dispdec
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dchubbubl_hubbub_dispdec
+//DCHUBBUB_ARB_DF_REQ_OUTSTAND
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT                                    0x0
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT                                    0xa
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK                                      0x000003FFL
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK                                      0x000FFC00L
+//DCHUBBUB_ARB_SAT_LEVEL
+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT                                                 0x0
+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK                                                   0xFFFFFFFFL
+//DCHUBBUB_ARB_QOS_FORCE
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT                                           0x0
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT                                          0x8
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_DURING_PSTATE_CHANGE_REQUEST__SHIFT         0x9
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK                                             0x0000000FL
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK                                            0x00000100L
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_DURING_PSTATE_CHANGE_REQUEST_MASK           0x00000200L
+//DCHUBBUB_ARB_DRAM_STATE_CNTL
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT                      0x0
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT                     0x1
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_CSTATE_DURING_PSTATE_CHANGE_REQUEST__SHIFT  0x2
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT                     0x4
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT                    0x5
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__ENABLE_QOS_FORCE_PSTATE__SHIFT                                          0x7
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE__SHIFT                                 0xc
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK                        0x00000001L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK                       0x00000002L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_CSTATE_DURING_PSTATE_CHANGE_REQUEST_MASK  0x00000004L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK                       0x00000010L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK                      0x00000020L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__ENABLE_QOS_FORCE_PSTATE_MASK                                            0x00000080L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE_MASK                                   0x00001000L
+//DCHUBBUB_ARB_USR_RETRAINING_CNTL
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__USR_RETRAINING_REQUEST__SHIFT                                       0x0
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__ALLOW_USR_RETRAINING__SHIFT                                         0x1
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE__SHIFT                0x8
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE__SHIFT               0x9
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST__SHIFT  0xa
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE__SHIFT  0xb
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__USR_RETRAINING_REQUEST_MASK                                         0x00000001L
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__ALLOW_USR_RETRAINING_MASK                                           0x00000002L
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE_MASK                  0x00000100L
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE_MASK                 0x00000200L
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST_MASK  0x00000400L
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE_MASK  0x00000800L
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK                     0x00003FFFL
+//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__SHIFT               0x0
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_MASK                 0x00003FFFL
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK                 0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK                   0x0000FFFFL
+//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__SHIFT       0x0
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__SHIFT       0x0
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_A
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK                     0x00003FFFL
+//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__SHIFT               0x0
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_MASK                 0x00003FFFL
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK                 0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK                   0x0000FFFFL
+//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__SHIFT       0x0
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__SHIFT       0x0
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_B
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK                     0x00003FFFL
+//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__SHIFT               0x0
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_MASK                 0x00003FFFL
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK                 0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK                   0x0000FFFFL
+//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__SHIFT       0x0
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__SHIFT       0x0
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_C
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK                     0x00003FFFL
+//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__SHIFT               0x0
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_MASK                 0x00003FFFL
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK                 0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK                   0x0000FFFFL
+//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__SHIFT       0x0
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__SHIFT       0x0
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_D
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT                       0x0
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT       0x4
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT        0x5
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT                      0x8
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__PSTATE_CHANGE_TYPE__SHIFT                                         0x18
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK                         0x00000003L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK         0x00000010L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK          0x00000020L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK                        0x00000100L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__PSTATE_CHANGE_TYPE_MASK                                           0x01000000L
+//DCHUBBUB_ARB_MALL_CNTL
+#define DCHUBBUB_ARB_MALL_CNTL__GLOBAL_USE_MALL_FOR_SS__SHIFT                                                 0x0
+#define DCHUBBUB_ARB_MALL_CNTL__MALL_IN_USE__SHIFT                                                            0x4
+#define DCHUBBUB_ARB_MALL_CNTL__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5
+#define DCHUBBUB_ARB_MALL_CNTL__GLOBAL_USE_MALL_FOR_SS_MASK                                                   0x00000001L
+#define DCHUBBUB_ARB_MALL_CNTL__MALL_IN_USE_MASK                                                              0x00000010L
+#define DCHUBBUB_ARB_MALL_CNTL__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L
+//DCHUBBUB_ARB_TIMEOUT_ENABLE
+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT                                       0x0
+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK                                         0x00000001L
+//DCHUBBUB_GLOBAL_TIMER_CNTL
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT                                       0x0
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT                                       0xc
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT                                         0x10
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK                                         0x0000000FL
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK                                         0x00001000L
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK                                           0xFFFF0000L
+//SURFACE_CHECK0_ADDRESS_LSB
+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK0_ADDRESS_MSB
+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK                                               0x80000000L
+//SURFACE_CHECK1_ADDRESS_LSB
+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK1_ADDRESS_MSB
+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK                                               0x80000000L
+//SURFACE_CHECK2_ADDRESS_LSB
+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK2_ADDRESS_MSB
+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK                                               0x80000000L
+//SURFACE_CHECK3_ADDRESS_LSB
+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK3_ADDRESS_MSB
+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK                                               0x80000000L
+//VTG0_CONTROL
+#define VTG0_CONTROL__VTG0_FP2__SHIFT                                                                         0x0
+#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG0_CONTROL__VTG0_ENABLE__SHIFT                                                                      0x1f
+#define VTG0_CONTROL__VTG0_FP2_MASK                                                                           0x00007FFFL
+#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG0_CONTROL__VTG0_ENABLE_MASK                                                                        0x80000000L
+//VTG1_CONTROL
+#define VTG1_CONTROL__VTG1_FP2__SHIFT                                                                         0x0
+#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG1_CONTROL__VTG1_ENABLE__SHIFT                                                                      0x1f
+#define VTG1_CONTROL__VTG1_FP2_MASK                                                                           0x00007FFFL
+#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG1_CONTROL__VTG1_ENABLE_MASK                                                                        0x80000000L
+//VTG2_CONTROL
+#define VTG2_CONTROL__VTG2_FP2__SHIFT                                                                         0x0
+#define VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG2_CONTROL__VTG2_ENABLE__SHIFT                                                                      0x1f
+#define VTG2_CONTROL__VTG2_FP2_MASK                                                                           0x00007FFFL
+#define VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG2_CONTROL__VTG2_ENABLE_MASK                                                                        0x80000000L
+//VTG3_CONTROL
+#define VTG3_CONTROL__VTG3_FP2__SHIFT                                                                         0x0
+#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG3_CONTROL__VTG3_ENABLE__SHIFT                                                                      0x1f
+#define VTG3_CONTROL__VTG3_FP2_MASK                                                                           0x00007FFFL
+#define VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG3_CONTROL__VTG3_ENABLE_MASK                                                                        0x80000000L
+//DCHUBBUB_SOFT_RESET
+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT                                                0x0
+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT                                                   0x1
+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT                                                        0x4
+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK                                                  0x00000001L
+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK                                                     0x00000002L
+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK                                                          0x00000010L
+//DCHUBBUB_CLOCK_CNTL
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0
+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                               0x5
+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                                0x6
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_FGCG_REP_DIS__SHIFT                                                     0x7
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL
+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK                                                 0x00000020L
+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK                                                  0x00000040L
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_FGCG_REP_DIS_MASK                                                       0x00000080L
+//DCFCLK_CNTL
+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT                                                              0x0
+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT                                                             0x4
+#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT                                                                   0x1f
+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK                                                                0x0000000FL
+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK                                                               0x00000FF0L
+#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK                                                                     0x80000000L
+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT                                 0x0
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN__SHIFT            0x1
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL__SHIFT                         0x2
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT                                    0x3
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT                                0x7
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT                                  0xa
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT                                          0xb
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK                                   0x00000001L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN_MASK              0x00000002L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL_MASK                           0x00000004L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK                                      0x00000078L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK                                  0x00000380L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK                                    0x00000400L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK                                            0x007FF800L
+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT                          0x0
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT                     0x1
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT                         0x4
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT                                     0xc
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT                                     0x13
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT                               0x1f
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK                            0x00000001L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK                       0x0000000EL
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK                           0x00000FF0L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK                                       0x00007000L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK                                       0x7FF80000L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK                                 0x80000000L
+//DCHUBBUB_VLINE_SNAPSHOT
+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT                                               0x0
+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK                                                 0x00000001L
+//DCHUBBUB_CTRL_STATUS
+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN__SHIFT                                                  0x0
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS__SHIFT                                                      0x2
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR__SHIFT                                                       0x3
+#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE__SHIFT                                               0x1f
+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN_MASK                                                    0x00000001L
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS_MASK                                                        0x00000004L
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR_MASK                                                         0x00000008L
+#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE_MASK                                                 0x80000000L
+//DCHUBBUB_TIMEOUT_DETECTION_CTRL1
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT                                0x0
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT                         0x6
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK                                  0x0000003FL
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK                           0xFFFFFFC0L
+//DCHUBBUB_TIMEOUT_DETECTION_CTRL2
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT                      0x0
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT                                0x1b
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT                                 0x1c
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK                        0x07FFFFFFL
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK                                  0x08000000L
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK                                   0x10000000L
+//DCHUBBUB_TIMEOUT_INTERRUPT_STATUS
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT                                 0x0
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT                                 0x1
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT                                  0x2
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT                                   0x3
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK                                   0x00000001L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK                                   0x00000002L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK                                    0x00000004L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK                                     0x000000F8L
+//FMON_CTRL
+#define FMON_CTRL__FMON_START__SHIFT                                                                          0x0
+#define FMON_CTRL__FMON_MODE__SHIFT                                                                           0x1
+#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT                                                                  0x4
+#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT                                                                  0x5
+#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT                                                               0x6
+#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT                                                                  0x7
+#define FMON_CTRL__FMON_STATE__SHIFT                                                                          0x9
+#define FMON_CTRL__FMON_URG_FILTER__SHIFT                                                                     0xc
+#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT                                                                  0xd
+#define FMON_CTRL__FMON_FILTER_UID_1__SHIFT                                                                   0x11
+#define FMON_CTRL__FMON_FILTER_UID_2__SHIFT                                                                   0x16
+#define FMON_CTRL__FMON_SOF_SEL__SHIFT                                                                        0x1b
+#define FMON_CTRL__FMON_START_MASK                                                                            0x00000001L
+#define FMON_CTRL__FMON_MODE_MASK                                                                             0x00000006L
+#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK                                                                    0x00000010L
+#define FMON_CTRL__FMON_STATUS_IGNORE_MASK                                                                    0x00000020L
+#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK                                                                 0x00000040L
+#define FMON_CTRL__FMON_FILTER_UID_EN_MASK                                                                    0x00000180L
+#define FMON_CTRL__FMON_STATE_MASK                                                                            0x00000600L
+#define FMON_CTRL__FMON_URG_FILTER_MASK                                                                       0x00001000L
+#define FMON_CTRL__FMON_URG_THRESHOLD_MASK                                                                    0x0001E000L
+#define FMON_CTRL__FMON_FILTER_UID_1_MASK                                                                     0x003E0000L
+#define FMON_CTRL__FMON_FILTER_UID_2_MASK                                                                     0x07C00000L
+#define FMON_CTRL__FMON_SOF_SEL_MASK                                                                          0x38000000L
+
+
+// addressBlock: dcn_dc_dchubbubl_hubbub_sdpif_dispdec
+//DCHUBBUB_SDPIF_CFG0
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT                                                  0x0
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT                                                         0x1
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT                                                0x3
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT                                                     0x6
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT                                                    0xa
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT                                               0xb
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT                                              0xc
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT                                                 0xd
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT                                                       0xe
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT                                                        0xf
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT                                             0x19
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK                                                    0x00000001L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK                                                           0x00000006L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK                                                  0x00000038L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK                                                       0x000003C0L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK                                                      0x00000400L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK                                                 0x00000800L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK                                                0x00001000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK                                                   0x00002000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK                                                         0x00004000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK                                                          0x00008000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK                                               0x7E000000L
+//DCHUBBUB_SDPIF_CFG1
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT                                                 0x0
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT                                                    0x1
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT                                              0x2
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT                                                         0x8
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_MAX_NUM_OUTSTANDING__SHIFT                                                 0x9
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK                                                   0x00000001L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK                                                      0x00000002L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK                                                0x00000004L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK                                                           0x00000100L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_MAX_NUM_OUTSTANDING_MASK                                                   0x00000200L
+//DCHUBBUB_SDPIF_CFG2
+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT__SHIFT                                                         0x0
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL__SHIFT                                                      0x8
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK__SHIFT                                                     0x10
+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT_MASK                                                           0x00000001L
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL_MASK                                                        0x00000700L
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK_MASK                                                       0x01FF0000L
+//VM_REQUEST_PHYSICAL
+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT                                                      0x0
+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT                                                      0x3
+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK                                                        0x00000001L
+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK                                                        0x00000008L
+//DCHUBBUB_FORCE_IO_STATUS_0
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT                                              0x0
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT                                       0x1
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT                                        0x2
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT                                      0x3
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT                                 0x7
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT                                      0xa
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK                                                0x00000001L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK                                         0x00000002L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK                                          0x00000004L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK                                        0x00000078L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK                                   0x00000380L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK                                        0xFFFFFC00L
+//DCHUBBUB_FORCE_IO_STATUS_1
+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT                                      0x0
+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK                                        0x001FFFFFL
+//DCN_VM_FB_LOCATION_BASE
+#define DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                               0x0
+#define DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                                 0x00FFFFFFL
+//DCN_VM_FB_LOCATION_TOP
+#define DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                                 0x0
+#define DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                                   0x00FFFFFFL
+//DCN_VM_FB_OFFSET
+#define DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                                    0x0
+#define DCN_VM_FB_OFFSET__FB_OFFSET_MASK                                                                      0x00FFFFFFL
+//DCN_VM_AGP_BOT
+#define DCN_VM_AGP_BOT__AGP_BOT__SHIFT                                                                        0x0
+#define DCN_VM_AGP_BOT__AGP_BOT_MASK                                                                          0x00FFFFFFL
+//DCN_VM_AGP_TOP
+#define DCN_VM_AGP_TOP__AGP_TOP__SHIFT                                                                        0x0
+#define DCN_VM_AGP_TOP__AGP_TOP_MASK                                                                          0x00FFFFFFL
+//DCN_VM_AGP_BASE
+#define DCN_VM_AGP_BASE__AGP_BASE__SHIFT                                                                      0x0
+#define DCN_VM_AGP_BASE__AGP_BASE_MASK                                                                        0x00FFFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_START
+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT                                                  0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK                                                    0x000FFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_END
+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT                                                      0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK                                                        0x000FFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                                       0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                                         0x00000001L
+//DCHUBBUB_SDPIF_PIPE_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL__SHIFT                                               0x0
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL__SHIFT                                               0x3
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL__SHIFT                                               0x6
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL__SHIFT                                               0x9
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL_MASK                                                 0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL_MASK                                                 0x00000038L
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL_MASK                                                 0x000001C0L
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL_MASK                                                 0x00000E00L
+//DCHUBBUB_SDPIF_PIPE_NOALLOC
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE0_NOALLOC__SHIFT                                               0x0
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE1_NOALLOC__SHIFT                                               0x1
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE2_NOALLOC__SHIFT                                               0x2
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE3_NOALLOC__SHIFT                                               0x3
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE0_NOALLOC_MASK                                                 0x00000001L
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE1_NOALLOC_MASK                                                 0x00000002L
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE2_NOALLOC_MASK                                                 0x00000004L
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE3_NOALLOC_MASK                                                 0x00000008L
+//DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL__SHIFT                                 0x0
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL__SHIFT                                 0x3
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL__SHIFT                                 0x6
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL__SHIFT                                 0x9
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL_MASK                                   0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL_MASK                                   0x00000038L
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL_MASK                                   0x000001C0L
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL_MASK                                   0x00000E00L
+//DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL__SHIFT                               0x0
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL__SHIFT                               0x3
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE2_DCCMETA_SEC_LVL__SHIFT                               0x6
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE3_DCCMETA_SEC_LVL__SHIFT                               0x9
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL_MASK                                 0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL_MASK                                 0x00000038L
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE2_DCCMETA_SEC_LVL_MASK                                 0x000001C0L
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE3_DCCMETA_SEC_LVL_MASK                                 0x00000E00L
+//DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL__SHIFT                               0x0
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL__SHIFT                               0x3
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE2_CURSOR0_SEC_LVL__SHIFT                               0x6
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE3_CURSOR0_SEC_LVL__SHIFT                               0x9
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL_MASK                                 0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL_MASK                                 0x00000038L
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE2_CURSOR0_SEC_LVL_MASK                                 0x000001C0L
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE3_CURSOR0_SEC_LVL_MASK                                 0x00000E00L
+//DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL__SHIFT                                   0x0
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL__SHIFT                                   0x3
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE2_GPUVM_SEC_LVL__SHIFT                                   0x6
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE3_GPUVM_SEC_LVL__SHIFT                                   0x9
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL_MASK                                     0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL_MASK                                     0x00000038L
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE2_GPUVM_SEC_LVL_MASK                                     0x000001C0L
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE3_GPUVM_SEC_LVL_MASK                                     0x00000E00L
+//SDPIF_REQUEST_RATE_LIMIT
+#define SDPIF_REQUEST_RATE_LIMIT__SDPIF_REQUEST_RATE_LIMIT__SHIFT                                             0x0
+#define SDPIF_REQUEST_RATE_LIMIT__SDPIF_REQUEST_RATE_LIMIT_MASK                                               0x00000FFFL
+//DCHUBBUB_SDPIF_MEM_PWR_CTRL
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT                                      0x0
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT                                        0x2
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK                                        0x00000003L
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK                                          0x00000004L
+//DCHUBBUB_SDPIF_MEM_PWR_STATUS
+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT                                    0x0
+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK                                      0x00000003L
+
+
+// addressBlock: dcn_dc_dchubbubl_hubbub_ret_path_dispdec
+//DCHUBBUB_RET_PATH_MEM_PWR_CTRL
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT                                0x0
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT                                  0x2
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK                                  0x00000003L
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK                                    0x00000004L
+//DCHUBBUB_RET_PATH_MEM_PWR_STATUS
+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT                              0x0
+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK                                0x00000003L
+//DCHUBBUB_CRC_CTRL
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT                                                             0x0
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT                                                        0x1
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT                                              0x2
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT                                              0x3
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT                                                       0x4
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT                                                       0x6
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT                                                       0x8
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT                                                       0xc
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT                                                   0x14
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK                                                               0x00000001L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK                                                          0x00000002L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK                                                0x00000004L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK                                                0x00000008L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK                                                         0x00000030L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK                                                         0x000000C0L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK                                                         0x00000F00L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK                                                         0x00001000L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK                                                     0x00100000L
+//DCHUBBUB_CRC0_VAL_R_G
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR__SHIFT                                                      0x0
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y__SHIFT                                                       0x10
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y_MASK                                                         0xFFFF0000L
+//DCHUBBUB_CRC0_VAL_B_A
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB__SHIFT                                                      0x0
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA__SHIFT                                                     0x10
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA_MASK                                                       0xFFFF0000L
+//DCHUBBUB_CRC1_VAL_R_G
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR__SHIFT                                                      0x0
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y__SHIFT                                                       0x10
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y_MASK                                                         0xFFFF0000L
+//DCHUBBUB_CRC1_VAL_B_A
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB__SHIFT                                                      0x0
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA__SHIFT                                                     0x10
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA_MASK                                                       0xFFFF0000L
+//DCHUBBUB_DCC_STAT_CNTL
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE__SHIFT                                                 0x0
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN__SHIFT                                                   0x1
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE__SHIFT                                                 0x2
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL__SHIFT                                             0x4
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT__SHIFT                                            0x10
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE_MASK                                                   0x00000001L
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN_MASK                                                     0x00000002L
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE_MASK                                                   0x00000004L
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL_MASK                                               0x000000F0L
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT_MASK                                              0xFFFF0000L
+//DCHUBBUB_DCC_STAT0
+#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ__SHIFT                                                0x0
+#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ_MASK                                                  0xFFFFFFFFL
+//DCHUBBUB_DCC_STAT1
+#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ__SHIFT                                                   0x0
+#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ_MASK                                                     0xFFFFFFFFL
+//DCHUBBUB_DCC_STAT2
+#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ__SHIFT                                                  0x0
+#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ_MASK                                                    0xFFFFFFFFL
+//DCHUBBUB_COMPBUF_CTRL
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE__SHIFT                                                            0x0
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT__SHIFT                                                    0x8
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE__SHIFT                                     0x10
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS__SHIFT                                     0x12
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR__SHIFT                                      0x13
+#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR__SHIFT                                                            0x1f
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_MASK                                                              0x0000001FL
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT_MASK                                                      0x00001F00L
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE_MASK                                       0x00010000L
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS_MASK                                       0x00040000L
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR_MASK                                        0x00080000L
+#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR_MASK                                                              0x80000000L
+//DCHUBBUB_DET0_CTRL
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE__SHIFT                                                                  0x0
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT__SHIFT                                                          0x8
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_MASK                                                                    0x0000001FL
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT_MASK                                                            0x00001F00L
+//DCHUBBUB_DET1_CTRL
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE__SHIFT                                                                  0x0
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT__SHIFT                                                          0x8
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_MASK                                                                    0x0000001FL
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT_MASK                                                            0x00001F00L
+//DCHUBBUB_DET2_CTRL
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE__SHIFT                                                                  0x0
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT__SHIFT                                                          0x8
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_MASK                                                                    0x0000001FL
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT_MASK                                                            0x00001F00L
+//DCHUBBUB_DET3_CTRL
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE__SHIFT                                                                  0x0
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT__SHIFT                                                          0x8
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_MASK                                                                    0x0000001FL
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT_MASK                                                            0x00001F00L
+//DCHUBBUB_MEM_PWR_MODE_CTRL
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE__SHIFT                                        0x0
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE__SHIFT                                        0x2
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE__SHIFT                                          0x4
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE__SHIFT                                             0x6
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE__SHIFT                                             0x8
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE__SHIFT                                           0xa
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE__SHIFT                                                  0x10
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE__SHIFT                                              0x12
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                                0x14
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS__SHIFT                                                0x18
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS__SHIFT                                               0x19
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS__SHIFT                                               0x1a
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE_MASK                                          0x00000003L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE_MASK                                          0x0000000CL
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE_MASK                                            0x00000030L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE_MASK                                               0x000000C0L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE_MASK                                             0x00000C00L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE_MASK                                                    0x00030000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE_MASK                                                0x000C0000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE_MASK                                                  0x00300000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS_MASK                                                  0x01000000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS_MASK                                                 0x02000000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS_MASK                                                 0x04000000L
+//COMPBUF_MEM_PWR_CTRL_1
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY__SHIFT                                            0x0
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY__SHIFT                                           0x8
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY__SHIFT                                              0x10
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY__SHIFT                                             0x18
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY_MASK                                              0x000000FFL
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY_MASK                                             0x0000FF00L
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY_MASK                                                0x00FF0000L
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY_MASK                                               0xFF000000L
+//COMPBUF_MEM_PWR_CTRL_2
+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY__SHIFT                                       0x0
+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY_MASK                                         0x000000FFL
+//DCHUBBUB_MEM_PWR_STATUS
+#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE__SHIFT                                                 0x0
+#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE__SHIFT                                                0x2
+#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE__SHIFT                                             0x4
+#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE__SHIFT                                                0x6
+#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE__SHIFT                                                    0x8
+#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE__SHIFT                                                    0xa
+#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE__SHIFT                                                    0xc
+#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE__SHIFT                                                    0xe
+#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE_MASK                                                   0x00000003L
+#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE_MASK                                                  0x0000000CL
+#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE_MASK                                               0x00000030L
+#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE_MASK                                                  0x000000C0L
+#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE_MASK                                                      0x00000300L
+#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE_MASK                                                      0x00000C00L
+#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE_MASK                                                      0x00003000L
+#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE_MASK                                                      0x0000C000L
+//COMPBUF_RESERVED_SPACE
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B__SHIFT                                             0x0
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS__SHIFT                                              0x10
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B_MASK                                               0x00000FFFL
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS_MASK                                                0x0FFF0000L
+
+
+// addressBlock: dcn_dc_dchubbubl_hubbub_vmrq_if_dispdec
+//DCN_VM_CONTEXT0_CNTL
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT1_CNTL
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT2_CNTL
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT3_CNTL
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT4_CNTL
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT5_CNTL
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT6_CNTL
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT7_CNTL
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT8_CNTL
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT9_CNTL
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT10_CNTL
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT11_CNTL
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT12_CNTL
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT13_CNTL
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT14_CNTL
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT15_CNTL
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_DEFAULT_ADDR_MSB
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB__SHIFT                                               0x0
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA__SHIFT                                                    0x1c
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP__SHIFT                                                  0x1d
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB_MASK                                                 0x0000000FL
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA_MASK                                                      0x10000000L
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP_MASK                                                    0x20000000L
+//DCN_VM_DEFAULT_ADDR_LSB
+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB__SHIFT                                               0x0
+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB_MASK                                                 0xFFFFFFFFL
+//DCN_VM_FAULT_CNTL
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT                                                   0x0
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT                                                    0x1
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT                                               0x2
+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT                                                  0x8
+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT                                                    0x9
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK                                                     0x00000001L
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK                                                      0x00000002L
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK                                                 0x00000004L
+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK                                                    0x00000100L
+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK                                                      0x00000200L
+//DCN_VM_FAULT_STATUS
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT                                                       0x0
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT                                                         0x10
+#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID__SHIFT                                                 0x14
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT                                                  0x18
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT                                                         0x1a
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT                                             0x1f
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK                                                         0x0000FFFFL
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK                                                           0x000F0000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID_MASK                                                   0x00F00000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK                                                    0x03000000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK                                                           0x3C000000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK                                               0x80000000L
+//DCN_VM_FAULT_ADDR_MSB
+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT                                                   0x0
+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK                                                     0x0000000FL
+//DCN_VM_FAULT_ADDR_LSB
+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT                                                   0x0
+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK                                                     0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dcbubp0_dispdec_hubp_dispdec
+//HUBP0_DCSURF_SURFACE_CONFIG
+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP0_DCSURF_ADDR_CONFIG
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP0_DCSURF_TILING_CONFIG
+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP0_DCSURF_PRI_VIEWPORT_START
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_START
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP0_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP0_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP0_DCHUBP_CNTL
+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2
+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa
+#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L
+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L
+#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP0_HUBP_CLK_CNTL
+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP0_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP0_DCHUBP_VMPG_CONFIG
+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP0_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1
+#define HUBP0_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2
+#define HUBP0_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7
+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+#define HUBP0_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L
+#define HUBP0_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL
+#define HUBP0_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L
+//HUBP0_DCHUBP_MALL_CONFIG
+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0
+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2
+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L
+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L
+//HUBP0_DCHUBP_MALL_SUB_VP
+#define HUBP0_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT                                               0x0
+#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT                                                 0x1
+#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT                                                 0xf
+#define HUBP0_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK                                                 0x00000001L
+#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK                                                   0x00007FFEL
+#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK                                                   0x1FFF8000L
+//HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+//HUBP0_HUBP_MALL_STATUS
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3
+#define HUBP0_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4
+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5
+#define HUBP0_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6
+#define HUBP0_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7
+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8
+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9
+#define HUBP0_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa
+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb
+#define HUBP0_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc
+#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT                                                     0xd
+#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe
+#define HUBP0_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf
+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10
+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11
+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12
+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L
+#define HUBP0_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L
+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L
+#define HUBP0_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L
+#define HUBP0_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L
+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L
+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L
+#define HUBP0_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L
+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L
+#define HUBP0_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L
+#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK                                                       0x00002000L
+#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L
+#define HUBP0_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L
+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L
+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L
+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L
+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L
+
+
+// addressBlock: dcn_dc_dcbubp0_dispdec_hubpreq_dispdec
+//HUBPREQ0_DCSURF_SURFACE_PITCH
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ0_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ0_VMID_SETTINGS_0
+#define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ0_DCSURF_SURFACE_CONTROL
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ0_DCSURF_FLIP_CONTROL
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ0_DCSURF_FLIP_CONTROL2
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ0_DCSURF_SURFACE_INUSE
+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ0_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ0_DCN_EXPANSION_MODE
+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ0_DCN_TTU_QOS_WM
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ0_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ0_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ0_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ0_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ0_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ0_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ0_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ0_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ0_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ0_DCN_DMDATA_VM_CNTL
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L
+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ0_BLANK_OFFSET_0
+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ0_BLANK_OFFSET_1
+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ0_DST_DIMENSIONS
+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ0_DST_AFTER_SCALER
+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ0_PREFETCH_SETTINGS
+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ0_PREFETCH_SETTINGS_C
+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_0
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ0_VBLANK_PARAMETERS_1
+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_2
+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_3
+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_4
+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_0
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ0_FLIP_PARAMETERS_1
+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_2
+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_0
+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_1
+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_2
+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_3
+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_4
+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_5
+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_6
+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_7
+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ0_PER_LINE_DELIVERY_PRE
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ0_PER_LINE_DELIVERY
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ0_CURSOR_SETTINGS
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ0_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ0_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ0_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ0_VBLANK_PARAMETERS_5
+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_6
+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_3
+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_4
+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_5
+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_6
+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+//HUBPREQ0_UCLK_PSTATE_FORCE
+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0
+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1
+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2
+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3
+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L
+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L
+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L
+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L
+//HUBPREQ0_HUBPREQ_STATUS_REG0
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT                                         0x0
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT                                         0x8
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK                                           0x0000001FL
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK                                           0x00001F00L
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L
+//HUBPREQ0_HUBPREQ_STATUS_REG1
+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0
+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10
+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x00003FFFL
+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0x3FFF0000L
+//HUBPREQ0_HUBPREQ_STATUS_REG2
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L
+
+
+// addressBlock: dcn_dc_dcbubp0_dispdec_hubpret_dispdec
+//HUBPRET0_HUBPRET_CONTROL
+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4
+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L
+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET0_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET0_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET0_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
+//HUBPRET0_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET0_HUBPRET_READ_LINE0
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET0_HUBPRET_READ_LINE1
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET0_HUBPRET_INTERRUPT
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET0_HUBPRET_READ_LINE_VALUE
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET0_HUBPRET_READ_LINE_STATUS
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dcn_dc_dcbubp0_dispdec_cursor0_dispdec
+//CURSOR0_0_CURSOR_CONTROL
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+//CURSOR0_0_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_0_CURSOR_SIZE
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_0_CURSOR_POSITION
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_0_CURSOR_HOT_SPOT
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_0_CURSOR_STEREO_CONTROL
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_0_CURSOR_DST_OFFSET
+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_0_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_0_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_0_DMDATA_ADDRESS_HIGH
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_0_DMDATA_ADDRESS_LOW
+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_0_DMDATA_CNTL
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_0_DMDATA_QOS_CNTL
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_0_DMDATA_STATUS
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_0_DMDATA_SW_CNTL
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_0_DMDATA_SW_DATA
+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dcbubp1_dispdec_hubp_dispdec
+//HUBP1_DCSURF_SURFACE_CONFIG
+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP1_DCSURF_ADDR_CONFIG
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP1_DCSURF_TILING_CONFIG
+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP1_DCSURF_PRI_VIEWPORT_START
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_START
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP1_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP1_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP1_DCHUBP_CNTL
+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2
+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa
+#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L
+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L
+#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP1_HUBP_CLK_CNTL
+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP1_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP1_DCHUBP_VMPG_CONFIG
+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP1_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1
+#define HUBP1_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2
+#define HUBP1_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7
+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+#define HUBP1_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L
+#define HUBP1_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL
+#define HUBP1_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L
+//HUBP1_DCHUBP_MALL_CONFIG
+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0
+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2
+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L
+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L
+//HUBP1_DCHUBP_MALL_SUB_VP
+#define HUBP1_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT                                               0x0
+#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT                                                 0x1
+#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT                                                 0xf
+#define HUBP1_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK                                                 0x00000001L
+#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK                                                   0x00007FFEL
+#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK                                                   0x1FFF8000L
+//HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+//HUBP1_HUBP_MALL_STATUS
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3
+#define HUBP1_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4
+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5
+#define HUBP1_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6
+#define HUBP1_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7
+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8
+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9
+#define HUBP1_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa
+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb
+#define HUBP1_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc
+#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT                                                     0xd
+#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe
+#define HUBP1_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf
+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10
+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11
+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12
+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L
+#define HUBP1_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L
+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L
+#define HUBP1_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L
+#define HUBP1_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L
+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L
+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L
+#define HUBP1_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L
+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L
+#define HUBP1_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L
+#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK                                                       0x00002000L
+#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L
+#define HUBP1_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L
+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L
+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L
+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L
+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L
+
+
+// addressBlock: dcn_dc_dcbubp1_dispdec_hubpreq_dispdec
+//HUBPREQ1_DCSURF_SURFACE_PITCH
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ1_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ1_VMID_SETTINGS_0
+#define HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ1_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ1_DCSURF_SURFACE_CONTROL
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ1_DCSURF_FLIP_CONTROL
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ1_DCSURF_FLIP_CONTROL2
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ1_DCSURF_SURFACE_INUSE
+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ1_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ1_DCN_EXPANSION_MODE
+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ1_DCN_TTU_QOS_WM
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ1_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ1_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ1_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ1_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ1_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ1_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ1_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ1_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ1_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ1_DCN_DMDATA_VM_CNTL
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L
+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ1_BLANK_OFFSET_0
+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ1_BLANK_OFFSET_1
+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ1_DST_DIMENSIONS
+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ1_DST_AFTER_SCALER
+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ1_PREFETCH_SETTINGS
+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ1_PREFETCH_SETTINGS_C
+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_0
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ1_VBLANK_PARAMETERS_1
+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_2
+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_3
+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_4
+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_0
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ1_FLIP_PARAMETERS_1
+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_2
+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_0
+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_1
+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_2
+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_3
+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_4
+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_5
+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_6
+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_7
+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ1_PER_LINE_DELIVERY_PRE
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ1_PER_LINE_DELIVERY
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ1_CURSOR_SETTINGS
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ1_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ1_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ1_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ1_VBLANK_PARAMETERS_5
+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_6
+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_3
+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_4
+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_5
+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_6
+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+//HUBPREQ1_UCLK_PSTATE_FORCE
+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0
+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1
+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2
+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3
+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L
+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L
+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L
+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L
+//HUBPREQ1_HUBPREQ_STATUS_REG0
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT                                         0x0
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT                                         0x8
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK                                           0x0000001FL
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK                                           0x00001F00L
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L
+//HUBPREQ1_HUBPREQ_STATUS_REG1
+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0
+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10
+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x00003FFFL
+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0x3FFF0000L
+//HUBPREQ1_HUBPREQ_STATUS_REG2
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L
+
+
+// addressBlock: dcn_dc_dcbubp1_dispdec_hubpret_dispdec
+//HUBPRET1_HUBPRET_CONTROL
+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4
+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L
+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET1_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET1_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET1_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
+//HUBPRET1_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET1_HUBPRET_READ_LINE0
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET1_HUBPRET_READ_LINE1
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET1_HUBPRET_INTERRUPT
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET1_HUBPRET_READ_LINE_VALUE
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET1_HUBPRET_READ_LINE_STATUS
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dcn_dc_dcbubp1_dispdec_cursor0_dispdec
+//CURSOR0_1_CURSOR_CONTROL
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+//CURSOR0_1_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_1_CURSOR_SIZE
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_1_CURSOR_POSITION
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_1_CURSOR_HOT_SPOT
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_1_CURSOR_STEREO_CONTROL
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_1_CURSOR_DST_OFFSET
+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_1_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_1_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_1_DMDATA_ADDRESS_HIGH
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_1_DMDATA_ADDRESS_LOW
+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_1_DMDATA_CNTL
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_1_DMDATA_QOS_CNTL
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_1_DMDATA_STATUS
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_1_DMDATA_SW_CNTL
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_1_DMDATA_SW_DATA
+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dcbubp2_dispdec_hubp_dispdec
+//HUBP2_DCSURF_SURFACE_CONFIG
+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP2_DCSURF_ADDR_CONFIG
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP2_DCSURF_TILING_CONFIG
+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP2_DCSURF_PRI_VIEWPORT_START
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP2_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_START
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP2_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP2_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP2_DCHUBP_CNTL
+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2
+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa
+#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L
+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L
+#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP2_HUBP_CLK_CNTL
+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP2_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP2_DCHUBP_VMPG_CONFIG
+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP2_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1
+#define HUBP2_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2
+#define HUBP2_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7
+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+#define HUBP2_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L
+#define HUBP2_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL
+#define HUBP2_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L
+//HUBP2_DCHUBP_MALL_CONFIG
+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0
+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2
+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L
+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L
+//HUBP2_DCHUBP_MALL_SUB_VP
+#define HUBP2_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT                                               0x0
+#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT                                                 0x1
+#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT                                                 0xf
+#define HUBP2_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK                                                 0x00000001L
+#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK                                                   0x00007FFEL
+#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK                                                   0x1FFF8000L
+//HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+//HUBP2_HUBP_MALL_STATUS
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3
+#define HUBP2_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4
+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5
+#define HUBP2_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6
+#define HUBP2_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7
+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8
+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9
+#define HUBP2_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa
+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb
+#define HUBP2_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc
+#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT                                                     0xd
+#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe
+#define HUBP2_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf
+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10
+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11
+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12
+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L
+#define HUBP2_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L
+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L
+#define HUBP2_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L
+#define HUBP2_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L
+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L
+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L
+#define HUBP2_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L
+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L
+#define HUBP2_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L
+#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK                                                       0x00002000L
+#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L
+#define HUBP2_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L
+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L
+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L
+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L
+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L
+
+
+// addressBlock: dcn_dc_dcbubp2_dispdec_hubpreq_dispdec
+//HUBPREQ2_DCSURF_SURFACE_PITCH
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ2_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ2_VMID_SETTINGS_0
+#define HUBPREQ2_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ2_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ2_DCSURF_SURFACE_CONTROL
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ2_DCSURF_FLIP_CONTROL
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ2_DCSURF_FLIP_CONTROL2
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ2_DCSURF_SURFACE_INUSE
+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ2_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ2_DCN_EXPANSION_MODE
+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ2_DCN_TTU_QOS_WM
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ2_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ2_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ2_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ2_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ2_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ2_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ2_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ2_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ2_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ2_DCN_DMDATA_VM_CNTL
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L
+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ2_BLANK_OFFSET_0
+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ2_BLANK_OFFSET_1
+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ2_DST_DIMENSIONS
+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ2_DST_AFTER_SCALER
+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ2_PREFETCH_SETTINGS
+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ2_PREFETCH_SETTINGS_C
+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_0
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ2_VBLANK_PARAMETERS_1
+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_2
+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_3
+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_4
+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_0
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ2_FLIP_PARAMETERS_1
+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_2
+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_0
+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_1
+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_2
+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_3
+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_4
+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_5
+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_6
+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_7
+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ2_PER_LINE_DELIVERY_PRE
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ2_PER_LINE_DELIVERY
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ2_CURSOR_SETTINGS
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ2_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ2_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ2_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ2_VBLANK_PARAMETERS_5
+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_6
+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_3
+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_4
+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_5
+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_6
+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+//HUBPREQ2_UCLK_PSTATE_FORCE
+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0
+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1
+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2
+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3
+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L
+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L
+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L
+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L
+//HUBPREQ2_HUBPREQ_STATUS_REG0
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT                                         0x0
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT                                         0x8
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK                                           0x0000001FL
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK                                           0x00001F00L
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L
+//HUBPREQ2_HUBPREQ_STATUS_REG1
+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0
+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10
+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x00003FFFL
+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0x3FFF0000L
+//HUBPREQ2_HUBPREQ_STATUS_REG2
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L
+
+
+// addressBlock: dcn_dc_dcbubp2_dispdec_hubpret_dispdec
+//HUBPRET2_HUBPRET_CONTROL
+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4
+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L
+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET2_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET2_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET2_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
+//HUBPRET2_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET2_HUBPRET_READ_LINE0
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET2_HUBPRET_READ_LINE1
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET2_HUBPRET_INTERRUPT
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET2_HUBPRET_READ_LINE_VALUE
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET2_HUBPRET_READ_LINE_STATUS
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dcn_dc_dcbubp2_dispdec_cursor0_dispdec
+//CURSOR0_2_CURSOR_CONTROL
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+//CURSOR0_2_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_2_CURSOR_SIZE
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_2_CURSOR_POSITION
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_2_CURSOR_HOT_SPOT
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_2_CURSOR_STEREO_CONTROL
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_2_CURSOR_DST_OFFSET
+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_2_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_2_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_2_DMDATA_ADDRESS_HIGH
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_2_DMDATA_ADDRESS_LOW
+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_2_DMDATA_CNTL
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_2_DMDATA_QOS_CNTL
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_2_DMDATA_STATUS
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_2_DMDATA_SW_CNTL
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_2_DMDATA_SW_DATA
+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dcbubp3_dispdec_hubp_dispdec
+//HUBP3_DCSURF_SURFACE_CONFIG
+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP3_DCSURF_ADDR_CONFIG
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP3_DCSURF_TILING_CONFIG
+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP3_DCSURF_PRI_VIEWPORT_START
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP3_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_START
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP3_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP3_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP3_DCHUBP_CNTL
+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2
+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa
+#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L
+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L
+#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP3_HUBP_CLK_CNTL
+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP3_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP3_DCHUBP_VMPG_CONFIG
+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP3_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1
+#define HUBP3_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2
+#define HUBP3_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7
+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+#define HUBP3_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L
+#define HUBP3_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL
+#define HUBP3_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L
+//HUBP3_DCHUBP_MALL_CONFIG
+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0
+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2
+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L
+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L
+//HUBP3_DCHUBP_MALL_SUB_VP
+#define HUBP3_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT                                               0x0
+#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT                                                 0x1
+#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT                                                 0xf
+#define HUBP3_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK                                                 0x00000001L
+#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK                                                   0x00007FFEL
+#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK                                                   0x1FFF8000L
+//HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+//HUBP3_HUBP_MALL_STATUS
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3
+#define HUBP3_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4
+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5
+#define HUBP3_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6
+#define HUBP3_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7
+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8
+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9
+#define HUBP3_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa
+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb
+#define HUBP3_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc
+#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT                                                     0xd
+#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe
+#define HUBP3_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf
+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10
+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11
+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12
+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L
+#define HUBP3_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L
+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L
+#define HUBP3_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L
+#define HUBP3_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L
+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L
+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L
+#define HUBP3_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L
+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L
+#define HUBP3_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L
+#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK                                                       0x00002000L
+#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L
+#define HUBP3_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L
+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L
+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L
+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L
+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L
+
+
+// addressBlock: dcn_dc_dcbubp3_dispdec_hubpreq_dispdec
+//HUBPREQ3_DCSURF_SURFACE_PITCH
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ3_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ3_VMID_SETTINGS_0
+#define HUBPREQ3_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ3_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ3_DCSURF_SURFACE_CONTROL
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ3_DCSURF_FLIP_CONTROL
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ3_DCSURF_FLIP_CONTROL2
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ3_DCSURF_SURFACE_INUSE
+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ3_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ3_DCN_EXPANSION_MODE
+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ3_DCN_TTU_QOS_WM
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ3_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ3_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ3_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ3_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ3_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ3_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ3_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ3_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ3_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ3_DCN_DMDATA_VM_CNTL
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L
+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ3_BLANK_OFFSET_0
+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ3_BLANK_OFFSET_1
+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ3_DST_DIMENSIONS
+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ3_DST_AFTER_SCALER
+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ3_PREFETCH_SETTINGS
+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ3_PREFETCH_SETTINGS_C
+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_0
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ3_VBLANK_PARAMETERS_1
+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_2
+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_3
+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_4
+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_0
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ3_FLIP_PARAMETERS_1
+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_2
+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_0
+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_1
+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_2
+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_3
+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_4
+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_5
+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_6
+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_7
+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ3_PER_LINE_DELIVERY_PRE
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ3_PER_LINE_DELIVERY
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ3_CURSOR_SETTINGS
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ3_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ3_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ3_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ3_VBLANK_PARAMETERS_5
+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_6
+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_3
+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_4
+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_5
+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_6
+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+//HUBPREQ3_UCLK_PSTATE_FORCE
+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0
+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1
+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2
+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3
+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L
+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L
+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L
+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L
+//HUBPREQ3_HUBPREQ_STATUS_REG0
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT                                         0x0
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT                                         0x8
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK                                           0x0000001FL
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK                                           0x00001F00L
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L
+//HUBPREQ3_HUBPREQ_STATUS_REG1
+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0
+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10
+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x00003FFFL
+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0x3FFF0000L
+//HUBPREQ3_HUBPREQ_STATUS_REG2
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L
+
+
+// addressBlock: dcn_dc_dcbubp3_dispdec_hubpret_dispdec
+//HUBPRET3_HUBPRET_CONTROL
+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4
+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L
+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET3_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET3_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET3_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
+//HUBPRET3_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET3_HUBPRET_READ_LINE0
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET3_HUBPRET_READ_LINE1
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET3_HUBPRET_INTERRUPT
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET3_HUBPRET_READ_LINE_VALUE
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET3_HUBPRET_READ_LINE_STATUS
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dcn_dc_dcbubp3_dispdec_cursor0_dispdec
+//CURSOR0_3_CURSOR_CONTROL
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+//CURSOR0_3_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_3_CURSOR_SIZE
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_3_CURSOR_POSITION
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_3_CURSOR_HOT_SPOT
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_3_CURSOR_STEREO_CONTROL
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_3_CURSOR_DST_OFFSET
+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_3_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_3_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_3_DMDATA_ADDRESS_HIGH
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_3_DMDATA_ADDRESS_LOW
+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_3_DMDATA_CNTL
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_3_DMDATA_QOS_CNTL
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_3_DMDATA_STATUS
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_3_DMDATA_SW_CNTL
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_3_DMDATA_SW_DATA
+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dpp0_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG0_FORMAT_CONTROL
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG0_FCNV_FP_BIAS_R
+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_BIAS_G
+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_BIAS_B
+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_R
+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_G
+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_B
+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG0_COLOR_KEYER_CONTROL
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG0_COLOR_KEYER_ALPHA
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_RED
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_GREEN
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_BLUE
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG0_ALPHA_2BIT_LUT
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG0_PRE_DEALPHA
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG0_PRE_CSC_MODE
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG0_PRE_CSC_C11_C12
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C13_C14
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C21_C22
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C23_C24
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C31_C32
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C33_C34
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C11_C12
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C13_C14
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C21_C22
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C23_C24
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C31_C32
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C33_C34
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_CNVC_COEF_FORMAT
+#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG0_PRE_DEGAM
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG0_PRE_REALPHA
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dcn_dc_dpp0_dispdec_cnvc_cur_dispdec
+//CNVC_CUR0_CURSOR0_CONTROL
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR0_CURSOR0_COLOR0
+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR0_CURSOR0_COLOR1
+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR0_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dpp0_dispdec_dscl_dispdec
+//DSCL0_SCL_COEF_RAM_TAP_SELECT
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00030000L
+//DSCL0_SCL_COEF_RAM_TAP_DATA
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL0_SCL_MODE
+#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL0_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL0_SCL_TAP_CONTROL
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL0_DSCL_CONTROL
+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL0_DSCL_2TAP_CONTROL
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL0_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL0_SCL_HORZ_FILTER_INIT
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL0_SCL_HORZ_FILTER_INIT_C
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL0_SCL_VERT_FILTER_INIT
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL0_SCL_VERT_FILTER_INIT_BOT
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL0_SCL_VERT_FILTER_INIT_C
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL0_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL0_SCL_BLACK_COLOR
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL0_DSCL_UPDATE
+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL0_DSCL_AUTOCAL
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL0_OTG_H_BLANK
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL0_OTG_V_BLANK
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL0_RECOUT_START
+#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL0_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL0_RECOUT_SIZE
+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL0_MPC_SIZE
+#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL0_LB_DATA_FORMAT
+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL0_LB_MEMORY_CTRL
+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL0_LB_V_COUNTER
+#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL0_DSCL_MEM_PWR_CTRL
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL0_DSCL_MEM_PWR_STATUS
+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL0_OBUF_CONTROL
+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL0_OBUF_MEM_PWR_CTRL
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dcn_dc_dpp0_dispdec_cm_dispdec
+//CM0_CM_CONTROL
+#define CM0_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM0_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM0_CM_POST_CSC_CONTROL
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM0_CM_POST_CSC_C11_C12
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C13_C14
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C21_C22
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C23_C24
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C31_C32
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C33_C34
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_B_C11_C12
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C13_C14
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C21_C22
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C23_C24
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C31_C32
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C33_C34
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_CONTROL
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM0_CM_GAMUT_REMAP_C11_C12
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C13_C14
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C21_C22
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C23_C24
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C31_C32
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C33_C34
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C11_C12
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C13_C14
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C21_C22
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C23_C24
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C31_C32
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C33_C34
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM0_CM_BIAS_CR_R
+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM0_CM_BIAS_Y_G_CB_B
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM0_CM_GAMCOR_CONTROL
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM0_CM_GAMCOR_LUT_INDEX
+#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM0_CM_GAMCOR_LUT_DATA
+#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM0_CM_GAMCOR_LUT_CONTROL
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT                                              0x5
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK                                                0x00000020L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM0_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMA_OFFSET_B
+#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMA_OFFSET_G
+#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMA_OFFSET_R
+#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMA_REGION_0_1
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_2_3
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_4_5
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_6_7
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_8_9
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_10_11
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_12_13
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_14_15
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_16_17
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_18_19
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_20_21
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_22_23
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_24_25
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_26_27
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_28_29
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_30_31
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_32_33
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMB_OFFSET_B
+#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMB_OFFSET_G
+#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMB_OFFSET_R
+#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMB_REGION_0_1
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_2_3
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_4_5
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_6_7
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_8_9
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_10_11
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_12_13
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_14_15
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_16_17
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_18_19
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_20_21
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_22_23
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_24_25
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_26_27
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_28_29
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_30_31
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_32_33
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_HDR_MULT_COEF
+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM0_CM_MEM_PWR_CTRL
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+//CM0_CM_MEM_PWR_STATUS
+#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+//CM0_CM_DEALPHA
+#define CM0_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM0_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM0_CM_COEF_FORMAT
+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+
+
+// addressBlock: dcn_dc_dpp0_dispdec_dpp_top_dispdec
+//DPP_TOP0_DPP_CONTROL
+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP0_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP0_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP0_DPP_SOFT_RESET
+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP0_DPP_CRC_VAL_R_G
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP0_DPP_CRC_VAL_B_A
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP0_DPP_CRC_CTRL
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP0_HOST_READ_CONTROL
+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dcn_dc_dpp1_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG1_FORMAT_CONTROL
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG1_FCNV_FP_BIAS_R
+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_BIAS_G
+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_BIAS_B
+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_R
+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_G
+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_B
+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG1_COLOR_KEYER_CONTROL
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG1_COLOR_KEYER_ALPHA
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_RED
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_GREEN
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_BLUE
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG1_ALPHA_2BIT_LUT
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG1_PRE_DEALPHA
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG1_PRE_CSC_MODE
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG1_PRE_CSC_C11_C12
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C13_C14
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C21_C22
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C23_C24
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C31_C32
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C33_C34
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C11_C12
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C13_C14
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C21_C22
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C23_C24
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C31_C32
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C33_C34
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_CNVC_COEF_FORMAT
+#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG1_PRE_DEGAM
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG1_PRE_REALPHA
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dcn_dc_dpp1_dispdec_cnvc_cur_dispdec
+//CNVC_CUR1_CURSOR0_CONTROL
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR1_CURSOR0_COLOR0
+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR1_CURSOR0_COLOR1
+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR1_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dpp1_dispdec_dscl_dispdec
+//DSCL1_SCL_COEF_RAM_TAP_SELECT
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00030000L
+//DSCL1_SCL_COEF_RAM_TAP_DATA
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL1_SCL_MODE
+#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL1_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL1_SCL_TAP_CONTROL
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL1_DSCL_CONTROL
+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL1_DSCL_2TAP_CONTROL
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL1_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL1_SCL_HORZ_FILTER_INIT
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL1_SCL_HORZ_FILTER_INIT_C
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL1_SCL_VERT_FILTER_INIT
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL1_SCL_VERT_FILTER_INIT_BOT
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL1_SCL_VERT_FILTER_INIT_C
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL1_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL1_SCL_BLACK_COLOR
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL1_DSCL_UPDATE
+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL1_DSCL_AUTOCAL
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL1_OTG_H_BLANK
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL1_OTG_V_BLANK
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL1_RECOUT_START
+#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL1_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL1_RECOUT_SIZE
+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL1_MPC_SIZE
+#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL1_LB_DATA_FORMAT
+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL1_LB_MEMORY_CTRL
+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL1_LB_V_COUNTER
+#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL1_DSCL_MEM_PWR_CTRL
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL1_DSCL_MEM_PWR_STATUS
+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL1_OBUF_CONTROL
+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL1_OBUF_MEM_PWR_CTRL
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dcn_dc_dpp1_dispdec_cm_dispdec
+//CM1_CM_CONTROL
+#define CM1_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM1_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM1_CM_POST_CSC_CONTROL
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM1_CM_POST_CSC_C11_C12
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C13_C14
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C21_C22
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C23_C24
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C31_C32
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C33_C34
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_B_C11_C12
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C13_C14
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C21_C22
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C23_C24
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C31_C32
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C33_C34
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_CONTROL
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM1_CM_GAMUT_REMAP_C11_C12
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C13_C14
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C21_C22
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C23_C24
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C31_C32
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C33_C34
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C11_C12
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C13_C14
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C21_C22
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C23_C24
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C31_C32
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C33_C34
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM1_CM_BIAS_CR_R
+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM1_CM_BIAS_Y_G_CB_B
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM1_CM_GAMCOR_CONTROL
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM1_CM_GAMCOR_LUT_INDEX
+#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM1_CM_GAMCOR_LUT_DATA
+#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM1_CM_GAMCOR_LUT_CONTROL
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT                                              0x5
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK                                                0x00000020L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM1_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMA_OFFSET_B
+#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMA_OFFSET_G
+#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMA_OFFSET_R
+#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMA_REGION_0_1
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_2_3
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_4_5
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_6_7
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_8_9
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_10_11
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_12_13
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_14_15
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_16_17
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_18_19
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_20_21
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_22_23
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_24_25
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_26_27
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_28_29
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_30_31
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_32_33
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMB_OFFSET_B
+#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMB_OFFSET_G
+#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMB_OFFSET_R
+#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMB_REGION_0_1
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_2_3
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_4_5
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_6_7
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_8_9
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_10_11
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_12_13
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_14_15
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_16_17
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_18_19
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_20_21
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_22_23
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_24_25
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_26_27
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_28_29
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_30_31
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_32_33
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_HDR_MULT_COEF
+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM1_CM_MEM_PWR_CTRL
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+//CM1_CM_MEM_PWR_STATUS
+#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+//CM1_CM_DEALPHA
+#define CM1_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM1_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM1_CM_COEF_FORMAT
+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+
+
+// addressBlock: dcn_dc_dpp1_dispdec_dpp_top_dispdec
+//DPP_TOP1_DPP_CONTROL
+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP1_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP1_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP1_DPP_SOFT_RESET
+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP1_DPP_CRC_VAL_R_G
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP1_DPP_CRC_VAL_B_A
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP1_DPP_CRC_CTRL
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP1_HOST_READ_CONTROL
+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dcn_dc_dpp2_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG2_FORMAT_CONTROL
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG2_FCNV_FP_BIAS_R
+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_BIAS_G
+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_BIAS_B
+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_SCALE_R
+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_SCALE_G
+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_SCALE_B
+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG2_COLOR_KEYER_CONTROL
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG2_COLOR_KEYER_ALPHA
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG2_COLOR_KEYER_RED
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG2_COLOR_KEYER_GREEN
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG2_COLOR_KEYER_BLUE
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG2_ALPHA_2BIT_LUT
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG2_PRE_DEALPHA
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG2_PRE_CSC_MODE
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG2_PRE_CSC_C11_C12
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C13_C14
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C21_C22
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C23_C24
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C31_C32
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C33_C34
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C11_C12
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C13_C14
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C21_C22
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C23_C24
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C31_C32
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C33_C34
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_CNVC_COEF_FORMAT
+#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG2_PRE_DEGAM
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG2_PRE_REALPHA
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dcn_dc_dpp2_dispdec_cnvc_cur_dispdec
+//CNVC_CUR2_CURSOR0_CONTROL
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR2_CURSOR0_COLOR0
+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR2_CURSOR0_COLOR1
+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR2_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dpp2_dispdec_dscl_dispdec
+//DSCL2_SCL_COEF_RAM_TAP_SELECT
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00030000L
+//DSCL2_SCL_COEF_RAM_TAP_DATA
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL2_SCL_MODE
+#define DSCL2_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL2_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL2_SCL_TAP_CONTROL
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL2_DSCL_CONTROL
+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL2_DSCL_2TAP_CONTROL
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL2_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL2_SCL_HORZ_FILTER_INIT
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL2_SCL_HORZ_FILTER_INIT_C
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL2_SCL_VERT_FILTER_INIT
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL2_SCL_VERT_FILTER_INIT_BOT
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL2_SCL_VERT_FILTER_INIT_C
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL2_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL2_SCL_BLACK_COLOR
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL2_DSCL_UPDATE
+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL2_DSCL_AUTOCAL
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL2_OTG_H_BLANK
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL2_OTG_V_BLANK
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL2_RECOUT_START
+#define DSCL2_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL2_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL2_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL2_RECOUT_SIZE
+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL2_MPC_SIZE
+#define DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL2_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL2_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL2_LB_DATA_FORMAT
+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL2_LB_MEMORY_CTRL
+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL2_LB_V_COUNTER
+#define DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL2_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL2_DSCL_MEM_PWR_CTRL
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL2_DSCL_MEM_PWR_STATUS
+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL2_OBUF_CONTROL
+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL2_OBUF_MEM_PWR_CTRL
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dcn_dc_dpp2_dispdec_cm_dispdec
+//CM2_CM_CONTROL
+#define CM2_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM2_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM2_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM2_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM2_CM_POST_CSC_CONTROL
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM2_CM_POST_CSC_C11_C12
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C13_C14
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C21_C22
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C23_C24
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C31_C32
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C33_C34
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_B_C11_C12
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C13_C14
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C21_C22
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C23_C24
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C31_C32
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C33_C34
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_CONTROL
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM2_CM_GAMUT_REMAP_C11_C12
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C13_C14
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C21_C22
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C23_C24
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C31_C32
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C33_C34
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C11_C12
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C13_C14
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C21_C22
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C23_C24
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C31_C32
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C33_C34
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM2_CM_BIAS_CR_R
+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM2_CM_BIAS_Y_G_CB_B
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM2_CM_GAMCOR_CONTROL
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM2_CM_GAMCOR_LUT_INDEX
+#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM2_CM_GAMCOR_LUT_DATA
+#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM2_CM_GAMCOR_LUT_CONTROL
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT                                              0x5
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK                                                0x00000020L
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM2_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMA_OFFSET_B
+#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMA_OFFSET_G
+#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMA_OFFSET_R
+#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMA_REGION_0_1
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_2_3
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_4_5
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_6_7
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_8_9
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_10_11
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_12_13
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_14_15
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_16_17
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_18_19
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_20_21
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_22_23
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_24_25
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_26_27
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_28_29
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_30_31
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_32_33
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMB_OFFSET_B
+#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMB_OFFSET_G
+#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMB_OFFSET_R
+#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMB_REGION_0_1
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_2_3
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_4_5
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_6_7
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_8_9
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_10_11
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_12_13
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_14_15
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_16_17
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_18_19
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_20_21
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_22_23
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_24_25
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_26_27
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_28_29
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_30_31
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_32_33
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_HDR_MULT_COEF
+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM2_CM_MEM_PWR_CTRL
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+//CM2_CM_MEM_PWR_STATUS
+#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+//CM2_CM_DEALPHA
+#define CM2_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM2_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM2_CM_COEF_FORMAT
+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+
+
+// addressBlock: dcn_dc_dpp2_dispdec_dpp_top_dispdec
+//DPP_TOP2_DPP_CONTROL
+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP2_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP2_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP2_DPP_SOFT_RESET
+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP2_DPP_CRC_VAL_R_G
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP2_DPP_CRC_VAL_B_A
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP2_DPP_CRC_CTRL
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP2_HOST_READ_CONTROL
+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dcn_dc_dpp3_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG3_FORMAT_CONTROL
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG3_FCNV_FP_BIAS_R
+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_BIAS_G
+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_BIAS_B
+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_SCALE_R
+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_SCALE_G
+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_SCALE_B
+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG3_COLOR_KEYER_CONTROL
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG3_COLOR_KEYER_ALPHA
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG3_COLOR_KEYER_RED
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG3_COLOR_KEYER_GREEN
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG3_COLOR_KEYER_BLUE
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG3_ALPHA_2BIT_LUT
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG3_PRE_DEALPHA
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG3_PRE_CSC_MODE
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG3_PRE_CSC_C11_C12
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C13_C14
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C21_C22
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C23_C24
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C31_C32
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C33_C34
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C11_C12
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C13_C14
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C21_C22
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C23_C24
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C31_C32
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C33_C34
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_CNVC_COEF_FORMAT
+#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG3_PRE_DEGAM
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG3_PRE_REALPHA
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dcn_dc_dpp3_dispdec_cnvc_cur_dispdec
+//CNVC_CUR3_CURSOR0_CONTROL
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR3_CURSOR0_COLOR0
+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR3_CURSOR0_COLOR1
+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR3_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dpp3_dispdec_dscl_dispdec
+//DSCL3_SCL_COEF_RAM_TAP_SELECT
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00030000L
+//DSCL3_SCL_COEF_RAM_TAP_DATA
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL3_SCL_MODE
+#define DSCL3_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL3_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL3_SCL_TAP_CONTROL
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL3_DSCL_CONTROL
+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL3_DSCL_2TAP_CONTROL
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL3_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL3_SCL_HORZ_FILTER_INIT
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL3_SCL_HORZ_FILTER_INIT_C
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL3_SCL_VERT_FILTER_INIT
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL3_SCL_VERT_FILTER_INIT_BOT
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL3_SCL_VERT_FILTER_INIT_C
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL3_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL3_SCL_BLACK_COLOR
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL3_DSCL_UPDATE
+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL3_DSCL_AUTOCAL
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL3_OTG_H_BLANK
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL3_OTG_V_BLANK
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL3_RECOUT_START
+#define DSCL3_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL3_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL3_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL3_RECOUT_SIZE
+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL3_MPC_SIZE
+#define DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL3_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL3_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL3_LB_DATA_FORMAT
+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL3_LB_MEMORY_CTRL
+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL3_LB_V_COUNTER
+#define DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL3_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL3_DSCL_MEM_PWR_CTRL
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL3_DSCL_MEM_PWR_STATUS
+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL3_OBUF_CONTROL
+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL3_OBUF_MEM_PWR_CTRL
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dcn_dc_dpp3_dispdec_cm_dispdec
+//CM3_CM_CONTROL
+#define CM3_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM3_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM3_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM3_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM3_CM_POST_CSC_CONTROL
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM3_CM_POST_CSC_C11_C12
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C13_C14
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C21_C22
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C23_C24
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C31_C32
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C33_C34
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_B_C11_C12
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C13_C14
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C21_C22
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C23_C24
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C31_C32
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C33_C34
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_CONTROL
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM3_CM_GAMUT_REMAP_C11_C12
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C13_C14
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C21_C22
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C23_C24
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C31_C32
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C33_C34
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C11_C12
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C13_C14
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C21_C22
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C23_C24
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C31_C32
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C33_C34
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM3_CM_BIAS_CR_R
+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM3_CM_BIAS_Y_G_CB_B
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM3_CM_GAMCOR_CONTROL
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM3_CM_GAMCOR_LUT_INDEX
+#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM3_CM_GAMCOR_LUT_DATA
+#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM3_CM_GAMCOR_LUT_CONTROL
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT                                              0x5
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK                                                0x00000020L
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM3_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMA_OFFSET_B
+#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMA_OFFSET_G
+#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMA_OFFSET_R
+#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMA_REGION_0_1
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_2_3
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_4_5
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_6_7
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_8_9
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_10_11
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_12_13
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_14_15
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_16_17
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_18_19
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_20_21
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_22_23
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_24_25
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_26_27
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_28_29
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_30_31
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_32_33
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMB_OFFSET_B
+#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMB_OFFSET_G
+#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMB_OFFSET_R
+#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMB_REGION_0_1
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_2_3
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_4_5
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_6_7
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_8_9
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_10_11
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_12_13
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_14_15
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_16_17
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_18_19
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_20_21
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_22_23
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_24_25
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_26_27
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_28_29
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_30_31
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_32_33
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_HDR_MULT_COEF
+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM3_CM_MEM_PWR_CTRL
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+//CM3_CM_MEM_PWR_STATUS
+#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+//CM3_CM_DEALPHA
+#define CM3_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM3_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM3_CM_COEF_FORMAT
+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+
+
+// addressBlock: dcn_dc_dpp3_dispdec_dpp_top_dispdec
+//DPP_TOP3_DPP_CONTROL
+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP3_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP3_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP3_DPP_SOFT_RESET
+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP3_DPP_CRC_VAL_R_G
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP3_DPP_CRC_VAL_B_A
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP3_DPP_CRC_CTRL
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP3_HOST_READ_CONTROL
+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dcn_dc_mpc_mpcc0_dispdec
+//MPCC0_MPCC_TOP_SEL
+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC0_MPCC_BOT_SEL
+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC0_MPCC_OPP_ID
+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC0_MPCC_CONTROL
+#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC0_MPCC_SM_CONTROL
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC0_MPCC_UPDATE_LOCK_SEL
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC0_MPCC_TOP_GAIN
+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC0_MPCC_BOT_GAIN_INSIDE
+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC0_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL
+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0
+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4
+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L
+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L
+//MPCC0_MPCC_BG_R_CR
+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC0_MPCC_BG_G_Y
+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC0_MPCC_BG_B_CB
+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC0_MPCC_MEM_PWR_CTRL
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC0_MPCC_STATUS
+#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC0_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC0_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dcn_dc_mpc_mpcc1_dispdec
+//MPCC1_MPCC_TOP_SEL
+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC1_MPCC_BOT_SEL
+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC1_MPCC_OPP_ID
+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC1_MPCC_CONTROL
+#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC1_MPCC_SM_CONTROL
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC1_MPCC_UPDATE_LOCK_SEL
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC1_MPCC_TOP_GAIN
+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC1_MPCC_BOT_GAIN_INSIDE
+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC1_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL
+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0
+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4
+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L
+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L
+//MPCC1_MPCC_BG_R_CR
+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC1_MPCC_BG_G_Y
+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC1_MPCC_BG_B_CB
+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC1_MPCC_MEM_PWR_CTRL
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC1_MPCC_STATUS
+#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC1_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC1_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dcn_dc_mpc_mpcc2_dispdec
+//MPCC2_MPCC_TOP_SEL
+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC2_MPCC_BOT_SEL
+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC2_MPCC_OPP_ID
+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC2_MPCC_CONTROL
+#define MPCC2_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC2_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC2_MPCC_SM_CONTROL
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC2_MPCC_UPDATE_LOCK_SEL
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC2_MPCC_TOP_GAIN
+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC2_MPCC_BOT_GAIN_INSIDE
+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC2_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL
+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0
+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4
+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L
+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L
+//MPCC2_MPCC_BG_R_CR
+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC2_MPCC_BG_G_Y
+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC2_MPCC_BG_B_CB
+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC2_MPCC_MEM_PWR_CTRL
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC2_MPCC_STATUS
+#define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC2_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC2_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC2_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC2_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC2_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dcn_dc_mpc_mpcc3_dispdec
+//MPCC3_MPCC_TOP_SEL
+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC3_MPCC_BOT_SEL
+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC3_MPCC_OPP_ID
+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC3_MPCC_CONTROL
+#define MPCC3_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC3_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC3_MPCC_SM_CONTROL
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC3_MPCC_UPDATE_LOCK_SEL
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC3_MPCC_TOP_GAIN
+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC3_MPCC_BOT_GAIN_INSIDE
+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC3_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL
+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0
+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4
+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L
+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L
+//MPCC3_MPCC_BG_R_CR
+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC3_MPCC_BG_G_Y
+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC3_MPCC_BG_B_CB
+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC3_MPCC_MEM_PWR_CTRL
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC3_MPCC_STATUS
+#define MPCC3_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC3_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC3_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC3_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC3_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC3_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dcn_dc_mpc_mpc_cfg_dispdec
+//MPC_CLOCK_CONTROL
+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                      0x1
+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT                                                            0x4
+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                        0x00000002L
+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK                                                              0x00000030L
+//MPC_SOFT_RESET
+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT                                                               0x0
+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT                                                               0x1
+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET__SHIFT                                                               0x2
+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET__SHIFT                                                               0x3
+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT                                                            0xa
+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT                                                            0xb
+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET__SHIFT                                                            0xc
+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET__SHIFT                                                            0xd
+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT                                                            0x14
+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT                                                            0x15
+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET__SHIFT                                                            0x16
+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET__SHIFT                                                            0x17
+#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT                                                                 0x1f
+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK                                                                 0x00000001L
+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK                                                                 0x00000002L
+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET_MASK                                                                 0x00000004L
+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET_MASK                                                                 0x00000008L
+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK                                                              0x00000400L
+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK                                                              0x00000800L
+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET_MASK                                                              0x00001000L
+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET_MASK                                                              0x00002000L
+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK                                                              0x00100000L
+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK                                                              0x00200000L
+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET_MASK                                                              0x00400000L
+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET_MASK                                                              0x00800000L
+#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK                                                                   0x80000000L
+//MPC_CRC_CTRL
+#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT                                                                       0x0
+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT                                                                  0x4
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT                                                              0x8
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT                                                                0xa
+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT                                                           0xc
+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT                                                                  0x18
+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT                                                         0x1c
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED__SHIFT                                                           0x1e
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT                                                              0x1f
+#define MPC_CRC_CTRL__MPC_CRC_EN_MASK                                                                         0x00000001L
+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK                                                                    0x00000010L
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK                                                                0x00000300L
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK                                                                  0x00000400L
+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK                                                             0x00003000L
+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK                                                                    0x03000000L
+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK                                                           0x10000000L
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED_MASK                                                             0x40000000L
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK                                                                0x80000000L
+//MPC_CRC_SEL_CONTROL
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT                                                           0x0
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT                                                           0x4
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL__SHIFT                                                           0x8
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT                                                              0x10
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK                                                             0x0000000FL
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK                                                             0x000000F0L
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL_MASK                                                             0x00000300L
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK                                                                0xFFFF0000L
+//MPC_CRC_RESULT_AR
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A__SHIFT                                                            0x0
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R__SHIFT                                                            0x10
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A_MASK                                                              0x0000FFFFL
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R_MASK                                                              0xFFFF0000L
+//MPC_CRC_RESULT_GB
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G__SHIFT                                                            0x0
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B__SHIFT                                                            0x10
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G_MASK                                                              0x0000FFFFL
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B_MASK                                                              0xFFFF0000L
+//MPC_CRC_RESULT_C
+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C__SHIFT                                                             0x0
+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C_MASK                                                               0x0000FFFFL
+//MPC_BYPASS_BG_AR
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT                                                          0x0
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT                                                           0x10
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK                                                            0x0000FFFFL
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK                                                             0xFFFF0000L
+//MPC_BYPASS_BG_GB
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT                                                            0x0
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT                                                           0x10
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK                                                              0x0000FFFFL
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK                                                             0xFFFF0000L
+//MPC_HOST_READ_CONTROL
+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                                  0x0
+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                                    0x000000FFL
+//MPC_DPP_PENDING_STATUS
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING__SHIFT                                         0x0
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING__SHIFT                                          0x1
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING__SHIFT                                          0x2
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING__SHIFT                                         0x4
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING__SHIFT                                          0x5
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING__SHIFT                                          0x6
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING__SHIFT                                         0x8
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING__SHIFT                                          0x9
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING__SHIFT                                          0xa
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING__SHIFT                                         0xc
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING__SHIFT                                          0xd
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING__SHIFT                                          0xe
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING_MASK                                           0x00000001L
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING_MASK                                            0x00000002L
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING_MASK                                            0x00000004L
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING_MASK                                           0x00000010L
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING_MASK                                            0x00000020L
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING_MASK                                            0x00000040L
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING_MASK                                           0x00000100L
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING_MASK                                            0x00000200L
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING_MASK                                            0x00000400L
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING_MASK                                           0x00001000L
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING_MASK                                            0x00002000L
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING_MASK                                            0x00004000L
+//MPC_PENDING_STATUS_MISC
+#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING__SHIFT                                        0x0
+#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING__SHIFT                                        0x1
+#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING__SHIFT                                        0x2
+#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING__SHIFT                                        0x3
+#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING__SHIFT                                           0x8
+#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING__SHIFT                                           0x9
+#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING__SHIFT                                           0xa
+#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING__SHIFT                                           0xb
+#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING__SHIFT                                         0x10
+#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING_MASK                                          0x00000001L
+#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING_MASK                                          0x00000002L
+#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING_MASK                                          0x00000004L
+#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING_MASK                                          0x00000008L
+#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING_MASK                                             0x00000100L
+#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING_MASK                                             0x00000200L
+#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING_MASK                                             0x00000400L
+#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING_MASK                                             0x00000800L
+#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING_MASK                                           0x00010000L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET0
+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET0
+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET0
+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET0
+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET1
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET1
+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET1
+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET1
+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET1
+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET2
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET2
+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET2
+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET2
+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET2
+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET3
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET3
+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET3
+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET3
+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET3
+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//MPC_DWB0_MUX
+#define MPC_DWB0_MUX__MPC_DWB0_MUX__SHIFT                                                                     0x0
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS__SHIFT                                                              0x4
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_MASK                                                                       0x0000000FL
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS_MASK                                                                0x000000F0L
+
+
+// addressBlock: dcn_dc_mpc_mpcc_ogam0_dispdec
+//MPCC_OGAM0_MPCC_OGAM_CONTROL
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM0_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM0_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dcn_dc_mpc_mpcc_ogam1_dispdec
+//MPCC_OGAM1_MPCC_OGAM_CONTROL
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM1_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM1_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dcn_dc_mpc_mpcc_ogam2_dispdec
+//MPCC_OGAM2_MPCC_OGAM_CONTROL
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM2_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM2_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dcn_dc_mpc_mpcc_ogam3_dispdec
+//MPCC_OGAM3_MPCC_OGAM_CONTROL
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM3_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM3_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dcn_dc_mpc_mpcc_mcm0_dispdec
+//MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2
+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL
+//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL
+//MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL
+//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL
+//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_3DLUT_MODE
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L
+//MPCC_MCM0_MPCC_MCM_3DLUT_INDEX
+#define MPCC_MCM0_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL
+//MPCC_MCM0_MPCC_MCM_3DLUT_DATA
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL
+//MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L
+//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL
+//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L
+//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT                              0x5
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK                                0x00000020L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L
+
+
+// addressBlock: dcn_dc_mpc_mpcc_mcm1_dispdec
+//MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2
+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL
+//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL
+//MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL
+//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL
+//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_3DLUT_MODE
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L
+//MPCC_MCM1_MPCC_MCM_3DLUT_INDEX
+#define MPCC_MCM1_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL
+//MPCC_MCM1_MPCC_MCM_3DLUT_DATA
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL
+//MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L
+//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL
+//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L
+//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT                              0x5
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK                                0x00000020L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L
+
+
+// addressBlock: dcn_dc_mpc_mpcc_mcm2_dispdec
+//MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2
+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL
+//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL
+//MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL
+//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL
+//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_3DLUT_MODE
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L
+//MPCC_MCM2_MPCC_MCM_3DLUT_INDEX
+#define MPCC_MCM2_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL
+//MPCC_MCM2_MPCC_MCM_3DLUT_DATA
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL
+//MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L
+//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL
+//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L
+//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT                              0x5
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK                                0x00000020L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L
+
+
+// addressBlock: dcn_dc_mpc_mpcc_mcm3_dispdec
+//MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2
+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL
+//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL
+//MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL
+//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL
+//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_3DLUT_MODE
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L
+//MPCC_MCM3_MPCC_MCM_3DLUT_INDEX
+#define MPCC_MCM3_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL
+//MPCC_MCM3_MPCC_MCM_3DLUT_DATA
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL
+//MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L
+//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL
+//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L
+//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT                              0x5
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK                                0x00000020L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L
+
+
+// addressBlock: dcn_dc_mpc_mpc_ocsc_dispdec
+//MPC_OUT0_MUX
+#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT0_DENORM_CONTROL
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT0_DENORM_CLAMP_G_Y
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT0_DENORM_CLAMP_B_CB
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT1_MUX
+#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT1_DENORM_CONTROL
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT1_DENORM_CLAMP_G_Y
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT1_DENORM_CLAMP_B_CB
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT2_MUX
+#define MPC_OUT2_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT2_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT2_DENORM_CONTROL
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT2_DENORM_CLAMP_G_Y
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT2_DENORM_CLAMP_B_CB
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT3_MUX
+#define MPC_OUT3_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT3_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT3_DENORM_CONTROL
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT3_DENORM_CLAMP_G_Y
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT3_DENORM_CLAMP_B_CB
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT_CSC_COEF_FORMAT
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT__SHIFT                                                 0x0
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT__SHIFT                                                 0x1
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT__SHIFT                                                 0x2
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT__SHIFT                                                 0x3
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT_MASK                                                   0x00000001L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT_MASK                                                   0x00000002L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT_MASK                                                   0x00000004L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT_MASK                                                   0x00000008L
+//MPC_OUT0_CSC_MODE
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT0_CSC_C11_C12_A
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C13_C14_A
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C21_C22_A
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C23_C24_A
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C31_C32_A
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C33_C34_A
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C11_C12_B
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C13_C14_B
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C21_C22_B
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C23_C24_B
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C31_C32_B
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C33_C34_B
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_MODE
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT1_CSC_C11_C12_A
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C13_C14_A
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C21_C22_A
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C23_C24_A
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C31_C32_A
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C33_C34_A
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C11_C12_B
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C13_C14_B
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C21_C22_B
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C23_C24_B
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C31_C32_B
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C33_C34_B
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_MODE
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT2_CSC_C11_C12_A
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C13_C14_A
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C21_C22_A
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C23_C24_A
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C31_C32_A
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C33_C34_A
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C11_C12_B
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C13_C14_B
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C21_C22_B
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C23_C24_B
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C31_C32_B
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C33_C34_B
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_MODE
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT3_CSC_C11_C12_A
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C13_C14_A
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C21_C22_A
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C23_C24_A
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C31_C32_A
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C33_C34_A
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C11_C12_B
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C13_C14_B
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C21_C22_B
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C23_C24_B
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C31_C32_B
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C33_C34_B
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+
+
+// addressBlock: dcn_dc_opp_abm0_dispdec
+//ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM0_BL1_PWM_USER_LEVEL
+#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM0_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM0_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM0_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM0_BL1_PWM_ABM_CNTL
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM0_BL1_PWM_GRP2_REG_LOCK
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM0_DC_ABM1_CNTL
+#define ABM0_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM0_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM0_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_THRES_12
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM0_DC_ABM1_ACE_THRES_34
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM0_DC_ABM1_ACE_CNTL_MISC
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM0_DC_ABM1_HG_MISC_CTRL
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM0_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM0_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM0_DC_ABM1_LS_PIXEL_COUNT
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM0_DC_ABM1_HG_SAMPLE_RATE
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM0_DC_ABM1_LS_SAMPLE_RATE
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_1
+#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_2
+#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_3
+#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_4
+#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_5
+#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_6
+#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_7
+#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_8
+#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_9
+#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_10
+#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_11
+#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_12
+#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_13
+#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_14
+#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_15
+#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_16
+#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_17
+#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_18
+#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_19
+#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_20
+#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_21
+#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_22
+#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_23
+#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_24
+#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_BL_MASTER_LOCK
+#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dcn_dc_opp_abm1_dispdec
+//ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM1_BL1_PWM_USER_LEVEL
+#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM1_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM1_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM1_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM1_BL1_PWM_ABM_CNTL
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM1_BL1_PWM_GRP2_REG_LOCK
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM1_DC_ABM1_CNTL
+#define ABM1_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM1_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM1_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_THRES_12
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM1_DC_ABM1_ACE_THRES_34
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM1_DC_ABM1_ACE_CNTL_MISC
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM1_DC_ABM1_HG_MISC_CTRL
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM1_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM1_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM1_DC_ABM1_LS_PIXEL_COUNT
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM1_DC_ABM1_HG_SAMPLE_RATE
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM1_DC_ABM1_LS_SAMPLE_RATE
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_1
+#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_2
+#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_3
+#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_4
+#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_5
+#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_6
+#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_7
+#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_8
+#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_9
+#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_10
+#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_11
+#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_12
+#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_13
+#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_14
+#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_15
+#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_16
+#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_17
+#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_18
+#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_19
+#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_20
+#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_21
+#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_22
+#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_23
+#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_24
+#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_BL_MASTER_LOCK
+#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dcn_dc_opp_abm2_dispdec
+//ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM2_BL1_PWM_USER_LEVEL
+#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM2_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM2_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM2_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM2_BL1_PWM_ABM_CNTL
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM2_BL1_PWM_GRP2_REG_LOCK
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM2_DC_ABM1_CNTL
+#define ABM2_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM2_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM2_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_THRES_12
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM2_DC_ABM1_ACE_THRES_34
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM2_DC_ABM1_ACE_CNTL_MISC
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM2_DC_ABM1_HG_MISC_CTRL
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM2_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM2_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM2_DC_ABM1_LS_PIXEL_COUNT
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM2_DC_ABM1_HG_SAMPLE_RATE
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM2_DC_ABM1_LS_SAMPLE_RATE
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_1
+#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_2
+#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_3
+#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_4
+#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_5
+#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_6
+#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_7
+#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_8
+#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_9
+#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_10
+#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_11
+#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_12
+#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_13
+#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_14
+#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_15
+#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_16
+#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_17
+#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_18
+#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_19
+#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_20
+#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_21
+#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_22
+#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_23
+#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_24
+#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_BL_MASTER_LOCK
+#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dcn_dc_opp_abm3_dispdec
+//ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM3_BL1_PWM_USER_LEVEL
+#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM3_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM3_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM3_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM3_BL1_PWM_ABM_CNTL
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM3_BL1_PWM_GRP2_REG_LOCK
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM3_DC_ABM1_CNTL
+#define ABM3_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM3_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM3_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_THRES_12
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM3_DC_ABM1_ACE_THRES_34
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM3_DC_ABM1_ACE_CNTL_MISC
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM3_DC_ABM1_HG_MISC_CTRL
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM3_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM3_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM3_DC_ABM1_LS_PIXEL_COUNT
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM3_DC_ABM1_HG_SAMPLE_RATE
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM3_DC_ABM1_LS_SAMPLE_RATE
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_1
+#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_2
+#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_3
+#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_4
+#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_5
+#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_6
+#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_7
+#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_8
+#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_9
+#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_10
+#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_11
+#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_12
+#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_13
+#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_14
+#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_15
+#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_16
+#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_17
+#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_18
+#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_19
+#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_20
+#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_21
+#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_22
+#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_23
+#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_24
+#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_BL_MASTER_LOCK
+#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dcn_dc_opp_dpg0_dispdec
+//DPG0_DPG_CONTROL
+#define DPG0_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG0_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG0_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG0_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG0_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG0_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG0_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG0_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG0_DPG_RAMP_CONTROL
+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG0_DPG_DIMENSIONS
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG0_DPG_COLOUR_R_CR
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG0_DPG_COLOUR_G_Y
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG0_DPG_COLOUR_B_CB
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG0_DPG_OFFSET_SEGMENT
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG0_DPG_STATUS
+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dcn_dc_opp_fmt0_dispdec
+//FMT0_FMT_CLAMP_COMPONENT_R
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT0_FMT_CLAMP_COMPONENT_G
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT0_FMT_CLAMP_COMPONENT_B
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT0_FMT_DYNAMIC_EXP_CNTL
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT0_FMT_CONTROL
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT0_FMT_BIT_DEPTH_CONTROL
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT0_FMT_DITHER_RAND_R_SEED
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT0_FMT_DITHER_RAND_G_SEED
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT0_FMT_DITHER_RAND_B_SEED
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT0_FMT_CLAMP_CNTL
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT0_FMT_MAP420_MEMORY_CONTROL
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT0_FMT_422_CONTROL
+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dcn_dc_opp_oppbuf0_dispdec
+//OPPBUF0_OPPBUF_CONTROL
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF0_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF0_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF0_OPPBUF_CONTROL1
+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dcn_dc_opp_opp_pipe0_dispdec
+//OPP_PIPE0_OPP_PIPE_CONTROL
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dcn_dc_opp_opp_pipe_crc0_dispdec
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dcn_dc_opp_dpg1_dispdec
+//DPG1_DPG_CONTROL
+#define DPG1_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG1_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG1_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG1_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG1_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG1_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG1_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG1_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG1_DPG_RAMP_CONTROL
+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG1_DPG_DIMENSIONS
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG1_DPG_COLOUR_R_CR
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG1_DPG_COLOUR_G_Y
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG1_DPG_COLOUR_B_CB
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG1_DPG_OFFSET_SEGMENT
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG1_DPG_STATUS
+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dcn_dc_opp_fmt1_dispdec
+//FMT1_FMT_CLAMP_COMPONENT_R
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT1_FMT_CLAMP_COMPONENT_G
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT1_FMT_CLAMP_COMPONENT_B
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT1_FMT_DYNAMIC_EXP_CNTL
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT1_FMT_CONTROL
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT1_FMT_BIT_DEPTH_CONTROL
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT1_FMT_DITHER_RAND_R_SEED
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT1_FMT_DITHER_RAND_G_SEED
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT1_FMT_DITHER_RAND_B_SEED
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT1_FMT_CLAMP_CNTL
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT1_FMT_MAP420_MEMORY_CONTROL
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT1_FMT_422_CONTROL
+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dcn_dc_opp_oppbuf1_dispdec
+//OPPBUF1_OPPBUF_CONTROL
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF1_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF1_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF1_OPPBUF_CONTROL1
+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dcn_dc_opp_opp_pipe1_dispdec
+//OPP_PIPE1_OPP_PIPE_CONTROL
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dcn_dc_opp_opp_pipe_crc1_dispdec
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dcn_dc_opp_dpg2_dispdec
+//DPG2_DPG_CONTROL
+#define DPG2_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG2_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG2_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG2_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG2_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG2_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG2_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG2_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG2_DPG_RAMP_CONTROL
+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG2_DPG_DIMENSIONS
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG2_DPG_COLOUR_R_CR
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG2_DPG_COLOUR_G_Y
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG2_DPG_COLOUR_B_CB
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG2_DPG_OFFSET_SEGMENT
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG2_DPG_STATUS
+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dcn_dc_opp_fmt2_dispdec
+//FMT2_FMT_CLAMP_COMPONENT_R
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT2_FMT_CLAMP_COMPONENT_G
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT2_FMT_CLAMP_COMPONENT_B
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT2_FMT_DYNAMIC_EXP_CNTL
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT2_FMT_CONTROL
+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT2_FMT_BIT_DEPTH_CONTROL
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT2_FMT_DITHER_RAND_R_SEED
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT2_FMT_DITHER_RAND_G_SEED
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT2_FMT_DITHER_RAND_B_SEED
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT2_FMT_CLAMP_CNTL
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT2_FMT_MAP420_MEMORY_CONTROL
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT2_FMT_422_CONTROL
+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dcn_dc_opp_oppbuf2_dispdec
+//OPPBUF2_OPPBUF_CONTROL
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF2_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF2_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF2_OPPBUF_CONTROL1
+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dcn_dc_opp_opp_pipe2_dispdec
+//OPP_PIPE2_OPP_PIPE_CONTROL
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dcn_dc_opp_opp_pipe_crc2_dispdec
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dcn_dc_opp_dpg3_dispdec
+//DPG3_DPG_CONTROL
+#define DPG3_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG3_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG3_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG3_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG3_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG3_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG3_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG3_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG3_DPG_RAMP_CONTROL
+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG3_DPG_DIMENSIONS
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG3_DPG_COLOUR_R_CR
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG3_DPG_COLOUR_G_Y
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG3_DPG_COLOUR_B_CB
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG3_DPG_OFFSET_SEGMENT
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG3_DPG_STATUS
+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dcn_dc_opp_fmt3_dispdec
+//FMT3_FMT_CLAMP_COMPONENT_R
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT3_FMT_CLAMP_COMPONENT_G
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT3_FMT_CLAMP_COMPONENT_B
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT3_FMT_DYNAMIC_EXP_CNTL
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT3_FMT_CONTROL
+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT3_FMT_BIT_DEPTH_CONTROL
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT3_FMT_DITHER_RAND_R_SEED
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT3_FMT_DITHER_RAND_G_SEED
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT3_FMT_DITHER_RAND_B_SEED
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT3_FMT_CLAMP_CNTL
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT3_FMT_MAP420_MEMORY_CONTROL
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT3_FMT_422_CONTROL
+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dcn_dc_opp_oppbuf3_dispdec
+//OPPBUF3_OPPBUF_CONTROL
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF3_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF3_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF3_OPPBUF_CONTROL1
+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dcn_dc_opp_opp_pipe3_dispdec
+//OPP_PIPE3_OPP_PIPE_CONTROL
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dcn_dc_opp_opp_pipe_crc3_dispdec
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dcn_dc_opp_dscrm0_dispdec
+//DSCRM0_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dcn_dc_opp_dscrm1_dispdec
+//DSCRM1_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dcn_dc_opp_dscrm2_dispdec
+//DSCRM2_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dcn_dc_opp_dscrm3_dispdec
+//DSCRM3_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dcn_dc_opp_opp_top_dispdec
+//OPP_TOP_CLK_CONTROL
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT                                                0x4
+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT                                                          0x8
+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT                                                         0xc
+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT                                                         0xd
+#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON__SHIFT                                                         0xe
+#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON__SHIFT                                                         0xf
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK                                                  0x00000010L
+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK                                                            0x00000F00L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK                                                           0x00001000L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK                                                           0x00002000L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON_MASK                                                           0x00004000L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON_MASK                                                           0x00008000L
+//OPP_ABM_CONTROL
+#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL__SHIFT                                                             0x0
+#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL_MASK                                                               0x00000007L
+
+
+// addressBlock: dcn_dc_optc_odm0_dispdec
+//ODM0_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM0_OPTC_DATA_SOURCE_SELECT
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L
+//ODM0_OPTC_DATA_FORMAT_CONTROL
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM0_OPTC_BYTES_PER_PIXEL
+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM0_OPTC_WIDTH_CONTROL
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM0_OPTC_INPUT_CLOCK_CONTROL
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM0_OPTC_MEMORY_CONFIG
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L
+//ODM0_OPTC_INPUT_SPARE_REGISTER
+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_optc_odm1_dispdec
+//ODM1_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM1_OPTC_DATA_SOURCE_SELECT
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L
+//ODM1_OPTC_DATA_FORMAT_CONTROL
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM1_OPTC_BYTES_PER_PIXEL
+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM1_OPTC_WIDTH_CONTROL
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM1_OPTC_INPUT_CLOCK_CONTROL
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM1_OPTC_MEMORY_CONFIG
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L
+//ODM1_OPTC_INPUT_SPARE_REGISTER
+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_optc_odm2_dispdec
+//ODM2_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM2_OPTC_DATA_SOURCE_SELECT
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L
+//ODM2_OPTC_DATA_FORMAT_CONTROL
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM2_OPTC_BYTES_PER_PIXEL
+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM2_OPTC_WIDTH_CONTROL
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM2_OPTC_INPUT_CLOCK_CONTROL
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM2_OPTC_MEMORY_CONFIG
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L
+//ODM2_OPTC_INPUT_SPARE_REGISTER
+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_optc_odm3_dispdec
+//ODM3_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM3_OPTC_DATA_SOURCE_SELECT
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L
+//ODM3_OPTC_DATA_FORMAT_CONTROL
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM3_OPTC_BYTES_PER_PIXEL
+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM3_OPTC_WIDTH_CONTROL
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM3_OPTC_INPUT_CLOCK_CONTROL
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM3_OPTC_MEMORY_CONFIG
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L
+//ODM3_OPTC_INPUT_SPARE_REGISTER
+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_optc_otg0_dispdec
+//OTG0_OTG_H_TOTAL
+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG0_OTG_H_BLANK_START_END
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG0_OTG_H_SYNC_A
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG0_OTG_H_SYNC_A_CNTL
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG0_OTG_H_TIMING_CNTL
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L
+//OTG0_OTG_V_TOTAL
+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG0_OTG_V_TOTAL_MIN
+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG0_OTG_V_TOTAL_MAX
+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG0_OTG_V_TOTAL_MID
+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG0_OTG_V_TOTAL_CONTROL
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG0_OTG_V_TOTAL_INT_STATUS
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG0_OTG_VSYNC_NOM_INT_STATUS
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG0_OTG_V_BLANK_START_END
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG0_OTG_V_SYNC_A
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG0_OTG_V_SYNC_A_CNTL
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG0_OTG_TRIGA_CNTL
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG0_OTG_TRIGA_MANUAL_TRIG
+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG0_OTG_TRIGB_CNTL
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG0_OTG_TRIGB_MANUAL_TRIG
+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG0_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG0_OTG_FLOW_CONTROL
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG0_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG0_OTG_CONTROL
+#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG0_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG0_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L
+//OTG0_OTG_INTERLACE_CONTROL
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG0_OTG_INTERLACE_STATUS
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG0_OTG_PIXEL_DATA_READBACK0
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG0_OTG_PIXEL_DATA_READBACK1
+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG0_OTG_STATUS
+#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG0_OTG_STATUS_POSITION
+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG0_OTG_NOM_VERT_POSITION
+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG0_OTG_STATUS_FRAME_COUNT
+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG0_OTG_STATUS_VF_COUNT
+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG0_OTG_STATUS_HV_COUNT
+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG0_OTG_COUNT_CONTROL
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG0_OTG_COUNT_RESET
+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG0_OTG_VERT_SYNC_CONTROL
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG0_OTG_STEREO_STATUS
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG0_OTG_STEREO_CONTROL
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG0_OTG_SNAPSHOT_STATUS
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG0_OTG_SNAPSHOT_CONTROL
+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG0_OTG_SNAPSHOT_POSITION
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG0_OTG_SNAPSHOT_FRAME
+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG0_OTG_INTERRUPT_CONTROL
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG0_OTG_UPDATE_LOCK
+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG0_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG0_OTG_MASTER_EN
+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG0_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L
+//OTG0_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG0_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG0_OTG_CRC_CNTL
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG0_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_DATA_RG
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC0_DATA_B
+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_DATA_RG
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC1_DATA_B
+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC2_DATA_RG
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC2_DATA_B
+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC3_DATA_RG
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC3_DATA_B
+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG0_OTG_STATIC_SCREEN_CONTROL
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG0_OTG_3D_STRUCTURE_CONTROL
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG0_OTG_GSL_VSYNC_GAP
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG0_OTG_MASTER_UPDATE_MODE
+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG0_OTG_CLOCK_CONTROL
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG0_OTG_VSTARTUP_PARAM
+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG0_OTG_VUPDATE_PARAM
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG0_OTG_VREADY_PARAM
+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG0_OTG_GLOBAL_SYNC_STATUS
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG0_OTG_MASTER_UPDATE_LOCK
+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG0_OTG_GSL_CONTROL
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG0_OTG_GSL_WINDOW_X
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG0_OTG_GSL_WINDOW_Y
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG0_OTG_VUPDATE_KEEPOUT
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL0
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL1
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL2
+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL3
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG0_OTG_GLOBAL_CONTROL4
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG0_OTG_TRIG_MANUAL_CONTROL
+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG0_OTG_MANUAL_FLOW_CONTROL
+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG0_OTG_DRR_TIMING_INT_STATUS
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG0_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG0_OTG_DRR_V_TOTAL_CHANGE
+#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG0_OTG_DRR_TRIGGER_WINDOW
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG0_OTG_DRR_CONTROL
+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG0_OTG_M_CONST_DTO0
+#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG0_OTG_M_CONST_DTO1
+#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG0_OTG_REQUEST_CONTROL
+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG0_OTG_DSC_START_POSITION
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG0_OTG_PIPE_UPDATE_STATUS
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG0_OTG_SPARE_REGISTER
+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_optc_otg1_dispdec
+//OTG1_OTG_H_TOTAL
+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG1_OTG_H_BLANK_START_END
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG1_OTG_H_SYNC_A
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG1_OTG_H_SYNC_A_CNTL
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG1_OTG_H_TIMING_CNTL
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L
+//OTG1_OTG_V_TOTAL
+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG1_OTG_V_TOTAL_MIN
+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG1_OTG_V_TOTAL_MAX
+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG1_OTG_V_TOTAL_MID
+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG1_OTG_V_TOTAL_CONTROL
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG1_OTG_V_TOTAL_INT_STATUS
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG1_OTG_VSYNC_NOM_INT_STATUS
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG1_OTG_V_BLANK_START_END
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG1_OTG_V_SYNC_A
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG1_OTG_V_SYNC_A_CNTL
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG1_OTG_TRIGA_CNTL
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG1_OTG_TRIGA_MANUAL_TRIG
+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG1_OTG_TRIGB_CNTL
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG1_OTG_TRIGB_MANUAL_TRIG
+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG1_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG1_OTG_FLOW_CONTROL
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG1_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG1_OTG_CONTROL
+#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG1_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG1_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L
+//OTG1_OTG_INTERLACE_CONTROL
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG1_OTG_INTERLACE_STATUS
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG1_OTG_PIXEL_DATA_READBACK0
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG1_OTG_PIXEL_DATA_READBACK1
+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG1_OTG_STATUS
+#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG1_OTG_STATUS_POSITION
+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG1_OTG_NOM_VERT_POSITION
+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG1_OTG_STATUS_FRAME_COUNT
+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG1_OTG_STATUS_VF_COUNT
+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG1_OTG_STATUS_HV_COUNT
+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG1_OTG_COUNT_CONTROL
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG1_OTG_COUNT_RESET
+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG1_OTG_VERT_SYNC_CONTROL
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG1_OTG_STEREO_STATUS
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG1_OTG_STEREO_CONTROL
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG1_OTG_SNAPSHOT_STATUS
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG1_OTG_SNAPSHOT_CONTROL
+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG1_OTG_SNAPSHOT_POSITION
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG1_OTG_SNAPSHOT_FRAME
+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG1_OTG_INTERRUPT_CONTROL
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG1_OTG_UPDATE_LOCK
+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG1_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG1_OTG_MASTER_EN
+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG1_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L
+//OTG1_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG1_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG1_OTG_CRC_CNTL
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG1_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_DATA_RG
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC0_DATA_B
+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_DATA_RG
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC1_DATA_B
+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC2_DATA_RG
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC2_DATA_B
+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC3_DATA_RG
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC3_DATA_B
+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG1_OTG_STATIC_SCREEN_CONTROL
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG1_OTG_3D_STRUCTURE_CONTROL
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG1_OTG_GSL_VSYNC_GAP
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG1_OTG_MASTER_UPDATE_MODE
+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG1_OTG_CLOCK_CONTROL
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG1_OTG_VSTARTUP_PARAM
+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG1_OTG_VUPDATE_PARAM
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG1_OTG_VREADY_PARAM
+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG1_OTG_GLOBAL_SYNC_STATUS
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG1_OTG_MASTER_UPDATE_LOCK
+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG1_OTG_GSL_CONTROL
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG1_OTG_GSL_WINDOW_X
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG1_OTG_GSL_WINDOW_Y
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG1_OTG_VUPDATE_KEEPOUT
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL0
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL1
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL2
+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL3
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG1_OTG_GLOBAL_CONTROL4
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG1_OTG_TRIG_MANUAL_CONTROL
+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG1_OTG_MANUAL_FLOW_CONTROL
+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG1_OTG_DRR_TIMING_INT_STATUS
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG1_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG1_OTG_DRR_V_TOTAL_CHANGE
+#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG1_OTG_DRR_TRIGGER_WINDOW
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG1_OTG_DRR_CONTROL
+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG1_OTG_M_CONST_DTO0
+#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG1_OTG_M_CONST_DTO1
+#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG1_OTG_REQUEST_CONTROL
+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG1_OTG_DSC_START_POSITION
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG1_OTG_PIPE_UPDATE_STATUS
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG1_OTG_SPARE_REGISTER
+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_optc_otg2_dispdec
+//OTG2_OTG_H_TOTAL
+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG2_OTG_H_BLANK_START_END
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG2_OTG_H_SYNC_A
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG2_OTG_H_SYNC_A_CNTL
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG2_OTG_H_TIMING_CNTL
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L
+//OTG2_OTG_V_TOTAL
+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG2_OTG_V_TOTAL_MIN
+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG2_OTG_V_TOTAL_MAX
+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG2_OTG_V_TOTAL_MID
+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG2_OTG_V_TOTAL_CONTROL
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG2_OTG_V_TOTAL_INT_STATUS
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG2_OTG_VSYNC_NOM_INT_STATUS
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG2_OTG_V_BLANK_START_END
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG2_OTG_V_SYNC_A
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG2_OTG_V_SYNC_A_CNTL
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG2_OTG_TRIGA_CNTL
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG2_OTG_TRIGA_MANUAL_TRIG
+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG2_OTG_TRIGB_CNTL
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG2_OTG_TRIGB_MANUAL_TRIG
+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG2_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG2_OTG_FLOW_CONTROL
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG2_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG2_OTG_CONTROL
+#define OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG2_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG2_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L
+//OTG2_OTG_INTERLACE_CONTROL
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG2_OTG_INTERLACE_STATUS
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG2_OTG_PIXEL_DATA_READBACK0
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG2_OTG_PIXEL_DATA_READBACK1
+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG2_OTG_STATUS
+#define OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG2_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG2_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG2_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG2_OTG_STATUS_POSITION
+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG2_OTG_NOM_VERT_POSITION
+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG2_OTG_STATUS_FRAME_COUNT
+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG2_OTG_STATUS_VF_COUNT
+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG2_OTG_STATUS_HV_COUNT
+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG2_OTG_COUNT_CONTROL
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG2_OTG_COUNT_RESET
+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG2_OTG_VERT_SYNC_CONTROL
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG2_OTG_STEREO_STATUS
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG2_OTG_STEREO_CONTROL
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG2_OTG_SNAPSHOT_STATUS
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG2_OTG_SNAPSHOT_CONTROL
+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG2_OTG_SNAPSHOT_POSITION
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG2_OTG_SNAPSHOT_FRAME
+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG2_OTG_INTERRUPT_CONTROL
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG2_OTG_UPDATE_LOCK
+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG2_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG2_OTG_MASTER_EN
+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG2_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L
+//OTG2_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG2_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG2_OTG_CRC_CNTL
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG2_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_DATA_RG
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC0_DATA_B
+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_DATA_RG
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC1_DATA_B
+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC2_DATA_RG
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC2_DATA_B
+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC3_DATA_RG
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC3_DATA_B
+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG2_OTG_STATIC_SCREEN_CONTROL
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG2_OTG_3D_STRUCTURE_CONTROL
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG2_OTG_GSL_VSYNC_GAP
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG2_OTG_MASTER_UPDATE_MODE
+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG2_OTG_CLOCK_CONTROL
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG2_OTG_VSTARTUP_PARAM
+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG2_OTG_VUPDATE_PARAM
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG2_OTG_VREADY_PARAM
+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG2_OTG_GLOBAL_SYNC_STATUS
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG2_OTG_MASTER_UPDATE_LOCK
+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG2_OTG_GSL_CONTROL
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG2_OTG_GSL_WINDOW_X
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG2_OTG_GSL_WINDOW_Y
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG2_OTG_VUPDATE_KEEPOUT
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL0
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL1
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL2
+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL3
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG2_OTG_GLOBAL_CONTROL4
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG2_OTG_TRIG_MANUAL_CONTROL
+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG2_OTG_MANUAL_FLOW_CONTROL
+#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG2_OTG_DRR_TIMING_INT_STATUS
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG2_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG2_OTG_DRR_V_TOTAL_CHANGE
+#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG2_OTG_DRR_TRIGGER_WINDOW
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG2_OTG_DRR_CONTROL
+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG2_OTG_M_CONST_DTO0
+#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG2_OTG_M_CONST_DTO1
+#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG2_OTG_REQUEST_CONTROL
+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG2_OTG_DSC_START_POSITION
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG2_OTG_PIPE_UPDATE_STATUS
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG2_OTG_SPARE_REGISTER
+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_optc_otg3_dispdec
+//OTG3_OTG_H_TOTAL
+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG3_OTG_H_BLANK_START_END
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG3_OTG_H_SYNC_A
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG3_OTG_H_SYNC_A_CNTL
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG3_OTG_H_TIMING_CNTL
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L
+//OTG3_OTG_V_TOTAL
+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG3_OTG_V_TOTAL_MIN
+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG3_OTG_V_TOTAL_MAX
+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG3_OTG_V_TOTAL_MID
+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG3_OTG_V_TOTAL_CONTROL
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG3_OTG_V_TOTAL_INT_STATUS
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG3_OTG_VSYNC_NOM_INT_STATUS
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG3_OTG_V_BLANK_START_END
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG3_OTG_V_SYNC_A
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG3_OTG_V_SYNC_A_CNTL
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG3_OTG_TRIGA_CNTL
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG3_OTG_TRIGA_MANUAL_TRIG
+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG3_OTG_TRIGB_CNTL
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG3_OTG_TRIGB_MANUAL_TRIG
+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG3_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG3_OTG_FLOW_CONTROL
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG3_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG3_OTG_CONTROL
+#define OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG3_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L
+//OTG3_OTG_INTERLACE_CONTROL
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG3_OTG_INTERLACE_STATUS
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG3_OTG_PIXEL_DATA_READBACK0
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG3_OTG_PIXEL_DATA_READBACK1
+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG3_OTG_STATUS
+#define OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG3_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG3_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG3_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG3_OTG_STATUS_POSITION
+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG3_OTG_NOM_VERT_POSITION
+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG3_OTG_STATUS_FRAME_COUNT
+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG3_OTG_STATUS_VF_COUNT
+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG3_OTG_STATUS_HV_COUNT
+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG3_OTG_COUNT_CONTROL
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG3_OTG_COUNT_RESET
+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG3_OTG_VERT_SYNC_CONTROL
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG3_OTG_STEREO_STATUS
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG3_OTG_STEREO_CONTROL
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG3_OTG_SNAPSHOT_STATUS
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG3_OTG_SNAPSHOT_CONTROL
+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG3_OTG_SNAPSHOT_POSITION
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG3_OTG_SNAPSHOT_FRAME
+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG3_OTG_INTERRUPT_CONTROL
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG3_OTG_UPDATE_LOCK
+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG3_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG3_OTG_MASTER_EN
+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG3_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L
+//OTG3_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG3_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG3_OTG_CRC_CNTL
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG3_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_DATA_RG
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC0_DATA_B
+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_DATA_RG
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC1_DATA_B
+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC2_DATA_RG
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC2_DATA_B
+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC3_DATA_RG
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC3_DATA_B
+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG3_OTG_STATIC_SCREEN_CONTROL
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG3_OTG_3D_STRUCTURE_CONTROL
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG3_OTG_GSL_VSYNC_GAP
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG3_OTG_MASTER_UPDATE_MODE
+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG3_OTG_CLOCK_CONTROL
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG3_OTG_VSTARTUP_PARAM
+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG3_OTG_VUPDATE_PARAM
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG3_OTG_VREADY_PARAM
+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG3_OTG_GLOBAL_SYNC_STATUS
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG3_OTG_MASTER_UPDATE_LOCK
+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG3_OTG_GSL_CONTROL
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG3_OTG_GSL_WINDOW_X
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG3_OTG_GSL_WINDOW_Y
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG3_OTG_VUPDATE_KEEPOUT
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL0
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL1
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL2
+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL3
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG3_OTG_GLOBAL_CONTROL4
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG3_OTG_TRIG_MANUAL_CONTROL
+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG3_OTG_MANUAL_FLOW_CONTROL
+#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG3_OTG_DRR_TIMING_INT_STATUS
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG3_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG3_OTG_DRR_V_TOTAL_CHANGE
+#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG3_OTG_DRR_TRIGGER_WINDOW
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG3_OTG_DRR_CONTROL
+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG3_OTG_M_CONST_DTO0
+#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG3_OTG_M_CONST_DTO1
+#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG3_OTG_REQUEST_CONTROL
+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG3_OTG_DSC_START_POSITION
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG3_OTG_PIPE_UPDATE_STATUS
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG3_OTG_SPARE_REGISTER
+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_optc_optc_misc_dispdec
+//GSL_SOURCE_SELECT
+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT                                                       0x0
+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT                                                       0x4
+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT                                                       0x8
+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT                                                         0x10
+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK                                                         0x00000007L
+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK                                                         0x00000070L
+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK                                                         0x00000700L
+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK                                                           0x00070000L
+//OPTC_CLOCK_CONTROL
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT                                                    0x1
+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT                                                          0x8
+#define OPTC_CLOCK_CONTROL__OPTC_FGCG_REP_DIS__SHIFT                                                          0xf
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK                                                      0x00000002L
+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK                                                            0x00000F00L
+#define OPTC_CLOCK_CONTROL__OPTC_FGCG_REP_DIS_MASK                                                            0x00008000L
+//ODM_MEM_PWR_CTRL
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT                                                           0x0
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT                                                             0x2
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT                                                           0x4
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT                                                             0x6
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT                                                           0x8
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT                                                             0xa
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT                                                           0xc
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT                                                             0xe
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE__SHIFT                                                           0x10
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS__SHIFT                                                             0x12
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE__SHIFT                                                           0x14
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS__SHIFT                                                             0x16
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE__SHIFT                                                           0x18
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS__SHIFT                                                             0x1a
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE__SHIFT                                                           0x1c
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS__SHIFT                                                             0x1e
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK                                                             0x00000003L
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK                                                               0x00000004L
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK                                                             0x00000030L
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK                                                               0x00000040L
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK                                                             0x00000300L
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK                                                               0x00000400L
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK                                                             0x00003000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK                                                               0x00004000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE_MASK                                                             0x00030000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS_MASK                                                               0x00040000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE_MASK                                                             0x00300000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS_MASK                                                               0x00400000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE_MASK                                                             0x03000000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS_MASK                                                               0x04000000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE_MASK                                                             0x30000000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS_MASK                                                               0x40000000L
+//ODM_MEM_PWR_CTRL3
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT                                                 0x0
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT                                                     0x2
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK                                                   0x00000003L
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK                                                       0x0000000CL
+//ODM_MEM_PWR_STATUS
+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT                                                         0x0
+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT                                                         0x2
+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT                                                         0x4
+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT                                                         0x6
+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE__SHIFT                                                         0x8
+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE__SHIFT                                                         0xa
+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE__SHIFT                                                         0xc
+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE__SHIFT                                                         0xe
+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK                                                           0x00000003L
+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK                                                           0x0000000CL
+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK                                                           0x00000030L
+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK                                                           0x000000C0L
+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE_MASK                                                           0x00000300L
+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE_MASK                                                           0x00000C00L
+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE_MASK                                                           0x00003000L
+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE_MASK                                                           0x0000C000L
+//OPTC_MISC_SPARE_REGISTER
+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT                                                  0x0
+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK                                                    0x000000FFL
+
+
+// addressBlock: dcn_dc_dio_hpd0_dispdec
+//HPD0_DC_HPD_INT_STATUS
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD0_DC_HPD_INT_CONTROL
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD0_DC_HPD_CONTROL
+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD0_DC_HPD_FAST_TRAIN_CNTL
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD0_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dcn_dc_dio_hpd1_dispdec
+//HPD1_DC_HPD_INT_STATUS
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD1_DC_HPD_INT_CONTROL
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD1_DC_HPD_CONTROL
+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD1_DC_HPD_FAST_TRAIN_CNTL
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD1_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dcn_dc_dio_hpd2_dispdec
+//HPD2_DC_HPD_INT_STATUS
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD2_DC_HPD_INT_CONTROL
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD2_DC_HPD_CONTROL
+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD2_DC_HPD_FAST_TRAIN_CNTL
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD2_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dcn_dc_dio_hpd3_dispdec
+//HPD3_DC_HPD_INT_STATUS
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD3_DC_HPD_INT_CONTROL
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD3_DC_HPD_CONTROL
+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD3_DC_HPD_FAST_TRAIN_CNTL
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD3_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dcn_dc_dio_hpd4_dispdec
+//HPD4_DC_HPD_INT_STATUS
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD4_DC_HPD_INT_CONTROL
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD4_DC_HPD_CONTROL
+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD4_DC_HPD_FAST_TRAIN_CNTL
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD4_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dcn_dc_dio_dp0_dispdec
+//DP0_DP_LINK_CNTL
+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP0_DP_PIXEL_FORMAT
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L
+//DP0_DP_MSA_COLORIMETRY
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP0_DP_CONFIG
+#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP0_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP0_DP_VID_STREAM_CNTL
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP0_DP_STEER_FIFO
+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP0_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18
+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+#define DP0_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L
+//DP0_DP_MSA_MISC
+#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP0_DP_DPHY_INTERNAL_CTRL
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP0_DP_VID_TIMING
+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP0_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP0_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP0_DP_VID_N
+#define DP0_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP0_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP0_DP_VID_M
+#define DP0_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP0_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP0_DP_LINK_FRAMING_CNTL
+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP0_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP0_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP0_DP_HBR2_EYE_PATTERN
+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP0_DP_VID_MSA_VBID
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP0_DP_VID_INTERRUPT_CNTL
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP0_DP_DPHY_CNTL
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP0_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP0_DP_DPHY_SYM0
+#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP0_DP_DPHY_SYM1
+#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP0_DP_DPHY_SYM2
+#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP0_DP_DPHY_8B10B_CNTL
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP0_DP_DPHY_PRBS_CNTL
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP0_DP_DPHY_SCRAM_CNTL
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP0_DP_DPHY_CRC_EN
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP0_DP_DPHY_CRC_CNTL
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP0_DP_DPHY_CRC_RESULT
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP0_DP_DPHY_CRC_MST_CNTL
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP0_DP_DPHY_CRC_MST_STATUS
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP0_DP_DPHY_FAST_TRAINING
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP0_DP_DPHY_FAST_TRAINING_STATUS
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP0_DP_SEC_CNTL
+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP0_DP_SEC_CNTL1
+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_FRAMING1
+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP0_DP_SEC_FRAMING2
+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP0_DP_SEC_FRAMING3
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP0_DP_SEC_FRAMING4
+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP0_DP_SEC_AUD_N
+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP0_DP_SEC_AUD_N_READBACK
+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP0_DP_SEC_AUD_M
+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP0_DP_SEC_AUD_M_READBACK
+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP0_DP_SEC_TIMESTAMP
+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP0_DP_SEC_PACKET_CNTL
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP0_DP_MSE_RATE_CNTL
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP0_DP_MSE_RATE_UPDATE
+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP0_DP_MSE_SAT0
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP0_DP_MSE_SAT1
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP0_DP_MSE_SAT2
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP0_DP_MSE_SAT_UPDATE
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP0_DP_MSE_LINK_TIMING
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP0_DP_MSE_MISC_CNTL
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP0_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP0_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP0_DP_MSE_SAT0_STATUS
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP0_DP_MSE_SAT1_STATUS
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP0_DP_MSE_SAT2_STATUS
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP0_DP_DPIA_SPARE
+#define DP0_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0
+#define DP0_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L
+//DP0_DP_MSA_TIMING_PARAM1
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP0_DP_MSA_TIMING_PARAM2
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP0_DP_MSA_TIMING_PARAM3
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP0_DP_MSA_TIMING_PARAM4
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP0_DP_MSO_CNTL
+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP0_DP_MSO_CNTL1
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP0_DP_DSC_CNTL
+#define DP0_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP0_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L
+//DP0_DP_SEC_CNTL2
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP0_DP_SEC_CNTL3
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_CNTL4
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_CNTL5
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_CNTL6
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP0_DP_SEC_CNTL7
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP0_DP_DB_CNTL
+#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP0_DP_MSA_VBID_MISC
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP0_DP_SEC_METADATA_TRANSMISSION
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP0_DP_ALPM_CNTL
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP0_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP0_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP0_DP_GSP8_CNTL
+#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_GSP9_CNTL
+#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_GSP10_CNTL
+#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP0_DP_GSP11_CNTL
+#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP0_DP_GSP_EN_DB_STATUS
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+//DP0_DP_AUXLESS_ALPM_CNTL1
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L
+//DP0_DP_AUXLESS_ALPM_CNTL2
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT                                       0x8
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0xf
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT                                              0x10
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x16
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x17
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT                                              0x18
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK                                         0x00003F00L
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00008000L
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK                                                0x000F0000L
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00400000L
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00800000L
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK                                                0xFF000000L
+//DP0_DP_AUXLESS_ALPM_CNTL3
+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0
+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10
+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL
+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L
+//DP0_DP_AUXLESS_ALPM_CNTL4
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x0
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x8
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x9
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0xa
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0xb
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x0000007FL
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000100L
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000200L
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000400L
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000800L
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L
+//DP0_DP_AUXLESS_ALPM_CNTL5
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dio_dig0_dispdec
+//DIG0_DIG_FE_CNTL
+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG0_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf
+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14
+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG0_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L
+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L
+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG0_DIG_OUTPUT_CRC_CNTL
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG0_DIG_OUTPUT_CRC_RESULT
+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG0_DIG_CLOCK_PATTERN
+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG0_DIG_TEST_PATTERN
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG0_DIG_RANDOM_PATTERN_SEED
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG0_DIG_FIFO_CTRL0
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L
+//DIG0_DIG_FIFO_CTRL1
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L
+//DIG0_HDMI_METADATA_PACKET_CONTROL
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG0_HDMI_CONTROL
+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG0_HDMI_STATUS
+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG0_HDMI_AUDIO_PACKET_CONTROL
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG0_HDMI_ACR_PACKET_CONTROL
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG0_HDMI_VBI_PACKET_CONTROL
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L
+//DIG0_HDMI_INFOFRAME_CONTROL0
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG0_HDMI_INFOFRAME_CONTROL1
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG0_HDMI_GC
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG0_HDMI_DB_CONTROL
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG0_HDMI_ACR_32_0
+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG0_HDMI_ACR_32_1
+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG0_HDMI_ACR_44_0
+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG0_HDMI_ACR_44_1
+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG0_HDMI_ACR_48_0
+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG0_HDMI_ACR_48_1
+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG0_HDMI_ACR_STATUS_0
+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG0_HDMI_ACR_STATUS_1
+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG0_AFMT_CNTL
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG0_DIG_BE_CNTL
+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG0_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG0_DIG_BE_EN_CNTL
+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG0_TMDS_CNTL
+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG0_TMDS_CONTROL_CHAR
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG0_TMDS_CONTROL0_FEEDBACK
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG0_TMDS_STEREOSYNC_CTL_SEL
+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG0_TMDS_CTL_BITS
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG0_TMDS_DCBALANCER_CONTROL
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG0_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG0_TMDS_CTL0_1_GEN_CNTL
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG0_TMDS_CTL2_3_GEN_CNTL
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG0_DIG_VERSION
+#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG0_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG0_FORCE_DIG_DISABLE
+#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dcn_dc_dio_dp1_dispdec
+//DP1_DP_LINK_CNTL
+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP1_DP_PIXEL_FORMAT
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L
+//DP1_DP_MSA_COLORIMETRY
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP1_DP_CONFIG
+#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP1_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP1_DP_VID_STREAM_CNTL
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP1_DP_STEER_FIFO
+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP1_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18
+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+#define DP1_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L
+//DP1_DP_MSA_MISC
+#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP1_DP_DPHY_INTERNAL_CTRL
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP1_DP_VID_TIMING
+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP1_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP1_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP1_DP_VID_N
+#define DP1_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP1_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP1_DP_VID_M
+#define DP1_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP1_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP1_DP_LINK_FRAMING_CNTL
+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP1_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP1_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP1_DP_HBR2_EYE_PATTERN
+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP1_DP_VID_MSA_VBID
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP1_DP_VID_INTERRUPT_CNTL
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP1_DP_DPHY_CNTL
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP1_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP1_DP_DPHY_SYM0
+#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP1_DP_DPHY_SYM1
+#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP1_DP_DPHY_SYM2
+#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP1_DP_DPHY_8B10B_CNTL
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP1_DP_DPHY_PRBS_CNTL
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP1_DP_DPHY_SCRAM_CNTL
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP1_DP_DPHY_CRC_EN
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP1_DP_DPHY_CRC_CNTL
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP1_DP_DPHY_CRC_RESULT
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP1_DP_DPHY_CRC_MST_CNTL
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP1_DP_DPHY_CRC_MST_STATUS
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP1_DP_DPHY_FAST_TRAINING
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP1_DP_DPHY_FAST_TRAINING_STATUS
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP1_DP_SEC_CNTL
+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP1_DP_SEC_CNTL1
+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_FRAMING1
+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP1_DP_SEC_FRAMING2
+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP1_DP_SEC_FRAMING3
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP1_DP_SEC_FRAMING4
+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP1_DP_SEC_AUD_N
+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP1_DP_SEC_AUD_N_READBACK
+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP1_DP_SEC_AUD_M
+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP1_DP_SEC_AUD_M_READBACK
+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP1_DP_SEC_TIMESTAMP
+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP1_DP_SEC_PACKET_CNTL
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP1_DP_MSE_RATE_CNTL
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP1_DP_MSE_RATE_UPDATE
+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP1_DP_MSE_SAT0
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP1_DP_MSE_SAT1
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP1_DP_MSE_SAT2
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP1_DP_MSE_SAT_UPDATE
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP1_DP_MSE_LINK_TIMING
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP1_DP_MSE_MISC_CNTL
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP1_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP1_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP1_DP_MSE_SAT0_STATUS
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP1_DP_MSE_SAT1_STATUS
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP1_DP_MSE_SAT2_STATUS
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP1_DP_DPIA_SPARE
+#define DP1_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0
+#define DP1_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L
+//DP1_DP_MSA_TIMING_PARAM1
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP1_DP_MSA_TIMING_PARAM2
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP1_DP_MSA_TIMING_PARAM3
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP1_DP_MSA_TIMING_PARAM4
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP1_DP_MSO_CNTL
+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP1_DP_MSO_CNTL1
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP1_DP_DSC_CNTL
+#define DP1_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP1_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L
+//DP1_DP_SEC_CNTL2
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP1_DP_SEC_CNTL3
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_CNTL4
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_CNTL5
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_CNTL6
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP1_DP_SEC_CNTL7
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP1_DP_DB_CNTL
+#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP1_DP_MSA_VBID_MISC
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP1_DP_SEC_METADATA_TRANSMISSION
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP1_DP_ALPM_CNTL
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP1_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP1_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP1_DP_GSP8_CNTL
+#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_GSP9_CNTL
+#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_GSP10_CNTL
+#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP1_DP_GSP11_CNTL
+#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP1_DP_GSP_EN_DB_STATUS
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+//DP1_DP_AUXLESS_ALPM_CNTL1
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L
+//DP1_DP_AUXLESS_ALPM_CNTL2
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT                                       0x8
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0xf
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT                                              0x10
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x16
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x17
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT                                              0x18
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK                                         0x00003F00L
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00008000L
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK                                                0x000F0000L
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00400000L
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00800000L
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK                                                0xFF000000L
+//DP1_DP_AUXLESS_ALPM_CNTL3
+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0
+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10
+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL
+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L
+//DP1_DP_AUXLESS_ALPM_CNTL4
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x0
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x8
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x9
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0xa
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0xb
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x0000007FL
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000100L
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000200L
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000400L
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000800L
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L
+//DP1_DP_AUXLESS_ALPM_CNTL5
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dio_dig1_dispdec
+//DIG1_DIG_FE_CNTL
+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG1_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf
+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14
+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG1_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L
+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L
+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG1_DIG_OUTPUT_CRC_CNTL
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG1_DIG_OUTPUT_CRC_RESULT
+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG1_DIG_CLOCK_PATTERN
+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG1_DIG_TEST_PATTERN
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG1_DIG_RANDOM_PATTERN_SEED
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG1_DIG_FIFO_CTRL0
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L
+//DIG1_DIG_FIFO_CTRL1
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L
+//DIG1_HDMI_METADATA_PACKET_CONTROL
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG1_HDMI_CONTROL
+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG1_HDMI_STATUS
+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG1_HDMI_AUDIO_PACKET_CONTROL
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG1_HDMI_ACR_PACKET_CONTROL
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG1_HDMI_VBI_PACKET_CONTROL
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L
+//DIG1_HDMI_INFOFRAME_CONTROL0
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG1_HDMI_INFOFRAME_CONTROL1
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG1_HDMI_GC
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG1_HDMI_DB_CONTROL
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG1_HDMI_ACR_32_0
+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG1_HDMI_ACR_32_1
+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG1_HDMI_ACR_44_0
+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG1_HDMI_ACR_44_1
+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG1_HDMI_ACR_48_0
+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG1_HDMI_ACR_48_1
+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG1_HDMI_ACR_STATUS_0
+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG1_HDMI_ACR_STATUS_1
+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG1_AFMT_CNTL
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG1_DIG_BE_CNTL
+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG1_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG1_DIG_BE_EN_CNTL
+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG1_TMDS_CNTL
+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG1_TMDS_CONTROL_CHAR
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG1_TMDS_CONTROL0_FEEDBACK
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG1_TMDS_STEREOSYNC_CTL_SEL
+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG1_TMDS_CTL_BITS
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG1_TMDS_DCBALANCER_CONTROL
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG1_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG1_TMDS_CTL0_1_GEN_CNTL
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG1_TMDS_CTL2_3_GEN_CNTL
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG1_DIG_VERSION
+#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG1_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG1_FORCE_DIG_DISABLE
+#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dcn_dc_dio_dp2_dispdec
+//DP2_DP_LINK_CNTL
+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP2_DP_PIXEL_FORMAT
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L
+//DP2_DP_MSA_COLORIMETRY
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP2_DP_CONFIG
+#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP2_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP2_DP_VID_STREAM_CNTL
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP2_DP_STEER_FIFO
+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP2_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18
+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+#define DP2_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L
+//DP2_DP_MSA_MISC
+#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP2_DP_DPHY_INTERNAL_CTRL
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP2_DP_VID_TIMING
+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP2_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP2_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP2_DP_VID_N
+#define DP2_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP2_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP2_DP_VID_M
+#define DP2_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP2_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP2_DP_LINK_FRAMING_CNTL
+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP2_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP2_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP2_DP_HBR2_EYE_PATTERN
+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP2_DP_VID_MSA_VBID
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP2_DP_VID_INTERRUPT_CNTL
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP2_DP_DPHY_CNTL
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP2_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP2_DP_DPHY_SYM0
+#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP2_DP_DPHY_SYM1
+#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP2_DP_DPHY_SYM2
+#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP2_DP_DPHY_8B10B_CNTL
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP2_DP_DPHY_PRBS_CNTL
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP2_DP_DPHY_SCRAM_CNTL
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP2_DP_DPHY_CRC_EN
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP2_DP_DPHY_CRC_CNTL
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP2_DP_DPHY_CRC_RESULT
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP2_DP_DPHY_CRC_MST_CNTL
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP2_DP_DPHY_CRC_MST_STATUS
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP2_DP_DPHY_FAST_TRAINING
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP2_DP_DPHY_FAST_TRAINING_STATUS
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP2_DP_SEC_CNTL
+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP2_DP_SEC_CNTL1
+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_FRAMING1
+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP2_DP_SEC_FRAMING2
+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP2_DP_SEC_FRAMING3
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP2_DP_SEC_FRAMING4
+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP2_DP_SEC_AUD_N
+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP2_DP_SEC_AUD_N_READBACK
+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP2_DP_SEC_AUD_M
+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP2_DP_SEC_AUD_M_READBACK
+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP2_DP_SEC_TIMESTAMP
+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP2_DP_SEC_PACKET_CNTL
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP2_DP_MSE_RATE_CNTL
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP2_DP_MSE_RATE_UPDATE
+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP2_DP_MSE_SAT0
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP2_DP_MSE_SAT1
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP2_DP_MSE_SAT2
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP2_DP_MSE_SAT_UPDATE
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP2_DP_MSE_LINK_TIMING
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP2_DP_MSE_MISC_CNTL
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP2_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP2_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP2_DP_MSE_SAT0_STATUS
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP2_DP_MSE_SAT1_STATUS
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP2_DP_MSE_SAT2_STATUS
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP2_DP_DPIA_SPARE
+#define DP2_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0
+#define DP2_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L
+//DP2_DP_MSA_TIMING_PARAM1
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP2_DP_MSA_TIMING_PARAM2
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP2_DP_MSA_TIMING_PARAM3
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP2_DP_MSA_TIMING_PARAM4
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP2_DP_MSO_CNTL
+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP2_DP_MSO_CNTL1
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP2_DP_DSC_CNTL
+#define DP2_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP2_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L
+//DP2_DP_SEC_CNTL2
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP2_DP_SEC_CNTL3
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_CNTL4
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_CNTL5
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_CNTL6
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP2_DP_SEC_CNTL7
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP2_DP_DB_CNTL
+#define DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP2_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP2_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP2_DP_MSA_VBID_MISC
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP2_DP_SEC_METADATA_TRANSMISSION
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP2_DP_ALPM_CNTL
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP2_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP2_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP2_DP_GSP8_CNTL
+#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_GSP9_CNTL
+#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_GSP10_CNTL
+#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP2_DP_GSP11_CNTL
+#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP2_DP_GSP_EN_DB_STATUS
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+//DP2_DP_AUXLESS_ALPM_CNTL1
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L
+//DP2_DP_AUXLESS_ALPM_CNTL2
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT                                       0x8
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0xf
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT                                              0x10
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x16
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x17
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT                                              0x18
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK                                         0x00003F00L
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00008000L
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK                                                0x000F0000L
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00400000L
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00800000L
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK                                                0xFF000000L
+//DP2_DP_AUXLESS_ALPM_CNTL3
+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0
+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10
+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL
+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L
+//DP2_DP_AUXLESS_ALPM_CNTL4
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x0
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x8
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x9
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0xa
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0xb
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x0000007FL
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000100L
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000200L
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000400L
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000800L
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L
+//DP2_DP_AUXLESS_ALPM_CNTL5
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dio_dig2_dispdec
+//DIG2_DIG_FE_CNTL
+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG2_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf
+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14
+#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG2_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L
+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L
+#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG2_DIG_OUTPUT_CRC_CNTL
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG2_DIG_OUTPUT_CRC_RESULT
+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG2_DIG_CLOCK_PATTERN
+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG2_DIG_TEST_PATTERN
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG2_DIG_RANDOM_PATTERN_SEED
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG2_DIG_FIFO_CTRL0
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L
+//DIG2_DIG_FIFO_CTRL1
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L
+//DIG2_HDMI_METADATA_PACKET_CONTROL
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG2_HDMI_CONTROL
+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG2_HDMI_STATUS
+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG2_HDMI_AUDIO_PACKET_CONTROL
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG2_HDMI_ACR_PACKET_CONTROL
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG2_HDMI_VBI_PACKET_CONTROL
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L
+//DIG2_HDMI_INFOFRAME_CONTROL0
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG2_HDMI_INFOFRAME_CONTROL1
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG2_HDMI_GC
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG2_HDMI_DB_CONTROL
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG2_HDMI_ACR_32_0
+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG2_HDMI_ACR_32_1
+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG2_HDMI_ACR_44_0
+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG2_HDMI_ACR_44_1
+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG2_HDMI_ACR_48_0
+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG2_HDMI_ACR_48_1
+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG2_HDMI_ACR_STATUS_0
+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG2_HDMI_ACR_STATUS_1
+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG2_AFMT_CNTL
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG2_DIG_BE_CNTL
+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG2_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG2_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG2_DIG_BE_EN_CNTL
+#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG2_TMDS_CNTL
+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG2_TMDS_CONTROL_CHAR
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG2_TMDS_CONTROL0_FEEDBACK
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG2_TMDS_STEREOSYNC_CTL_SEL
+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG2_TMDS_CTL_BITS
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG2_TMDS_DCBALANCER_CONTROL
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG2_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG2_TMDS_CTL0_1_GEN_CNTL
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG2_TMDS_CTL2_3_GEN_CNTL
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG2_DIG_VERSION
+#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG2_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG2_FORCE_DIG_DISABLE
+#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dcn_dc_dio_dp3_dispdec
+//DP3_DP_LINK_CNTL
+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP3_DP_PIXEL_FORMAT
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L
+//DP3_DP_MSA_COLORIMETRY
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP3_DP_CONFIG
+#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP3_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP3_DP_VID_STREAM_CNTL
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP3_DP_STEER_FIFO
+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP3_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18
+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+#define DP3_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L
+//DP3_DP_MSA_MISC
+#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP3_DP_DPHY_INTERNAL_CTRL
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP3_DP_VID_TIMING
+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP3_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP3_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP3_DP_VID_N
+#define DP3_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP3_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP3_DP_VID_M
+#define DP3_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP3_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP3_DP_LINK_FRAMING_CNTL
+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP3_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP3_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP3_DP_HBR2_EYE_PATTERN
+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP3_DP_VID_MSA_VBID
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP3_DP_VID_INTERRUPT_CNTL
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP3_DP_DPHY_CNTL
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP3_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP3_DP_DPHY_SYM0
+#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP3_DP_DPHY_SYM1
+#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP3_DP_DPHY_SYM2
+#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP3_DP_DPHY_8B10B_CNTL
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP3_DP_DPHY_PRBS_CNTL
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP3_DP_DPHY_SCRAM_CNTL
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP3_DP_DPHY_CRC_EN
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP3_DP_DPHY_CRC_CNTL
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP3_DP_DPHY_CRC_RESULT
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP3_DP_DPHY_CRC_MST_CNTL
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP3_DP_DPHY_CRC_MST_STATUS
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP3_DP_DPHY_FAST_TRAINING
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP3_DP_DPHY_FAST_TRAINING_STATUS
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP3_DP_SEC_CNTL
+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP3_DP_SEC_CNTL1
+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_FRAMING1
+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP3_DP_SEC_FRAMING2
+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP3_DP_SEC_FRAMING3
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP3_DP_SEC_FRAMING4
+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP3_DP_SEC_AUD_N
+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP3_DP_SEC_AUD_N_READBACK
+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP3_DP_SEC_AUD_M
+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP3_DP_SEC_AUD_M_READBACK
+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP3_DP_SEC_TIMESTAMP
+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP3_DP_SEC_PACKET_CNTL
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP3_DP_MSE_RATE_CNTL
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP3_DP_MSE_RATE_UPDATE
+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP3_DP_MSE_SAT0
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP3_DP_MSE_SAT1
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP3_DP_MSE_SAT2
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP3_DP_MSE_SAT_UPDATE
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP3_DP_MSE_LINK_TIMING
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP3_DP_MSE_MISC_CNTL
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP3_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP3_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP3_DP_MSE_SAT0_STATUS
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP3_DP_MSE_SAT1_STATUS
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP3_DP_MSE_SAT2_STATUS
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP3_DP_DPIA_SPARE
+#define DP3_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0
+#define DP3_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L
+//DP3_DP_MSA_TIMING_PARAM1
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP3_DP_MSA_TIMING_PARAM2
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP3_DP_MSA_TIMING_PARAM3
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP3_DP_MSA_TIMING_PARAM4
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP3_DP_MSO_CNTL
+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP3_DP_MSO_CNTL1
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP3_DP_DSC_CNTL
+#define DP3_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP3_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L
+//DP3_DP_SEC_CNTL2
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP3_DP_SEC_CNTL3
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_CNTL4
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_CNTL5
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_CNTL6
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP3_DP_SEC_CNTL7
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP3_DP_DB_CNTL
+#define DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP3_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP3_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP3_DP_MSA_VBID_MISC
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP3_DP_SEC_METADATA_TRANSMISSION
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP3_DP_ALPM_CNTL
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP3_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP3_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP3_DP_GSP8_CNTL
+#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_GSP9_CNTL
+#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_GSP10_CNTL
+#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP3_DP_GSP11_CNTL
+#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP3_DP_GSP_EN_DB_STATUS
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+//DP3_DP_AUXLESS_ALPM_CNTL1
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L
+//DP3_DP_AUXLESS_ALPM_CNTL2
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT                                       0x8
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0xf
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT                                              0x10
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x16
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x17
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT                                              0x18
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK                                         0x00003F00L
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00008000L
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK                                                0x000F0000L
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00400000L
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00800000L
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK                                                0xFF000000L
+//DP3_DP_AUXLESS_ALPM_CNTL3
+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0
+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10
+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL
+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L
+//DP3_DP_AUXLESS_ALPM_CNTL4
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x0
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x8
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x9
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0xa
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0xb
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x0000007FL
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000100L
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000200L
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000400L
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000800L
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L
+//DP3_DP_AUXLESS_ALPM_CNTL5
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dio_dig3_dispdec
+//DIG3_DIG_FE_CNTL
+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG3_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf
+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14
+#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG3_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L
+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L
+#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG3_DIG_OUTPUT_CRC_CNTL
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG3_DIG_OUTPUT_CRC_RESULT
+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG3_DIG_CLOCK_PATTERN
+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG3_DIG_TEST_PATTERN
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG3_DIG_RANDOM_PATTERN_SEED
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG3_DIG_FIFO_CTRL0
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L
+//DIG3_DIG_FIFO_CTRL1
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L
+//DIG3_HDMI_METADATA_PACKET_CONTROL
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG3_HDMI_CONTROL
+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG3_HDMI_STATUS
+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG3_HDMI_AUDIO_PACKET_CONTROL
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG3_HDMI_ACR_PACKET_CONTROL
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG3_HDMI_VBI_PACKET_CONTROL
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L
+//DIG3_HDMI_INFOFRAME_CONTROL0
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG3_HDMI_INFOFRAME_CONTROL1
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG3_HDMI_GC
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG3_HDMI_DB_CONTROL
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG3_HDMI_ACR_32_0
+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG3_HDMI_ACR_32_1
+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG3_HDMI_ACR_44_0
+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG3_HDMI_ACR_44_1
+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG3_HDMI_ACR_48_0
+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG3_HDMI_ACR_48_1
+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG3_HDMI_ACR_STATUS_0
+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG3_HDMI_ACR_STATUS_1
+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG3_AFMT_CNTL
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG3_DIG_BE_CNTL
+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG3_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG3_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG3_DIG_BE_EN_CNTL
+#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG3_TMDS_CNTL
+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG3_TMDS_CONTROL_CHAR
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG3_TMDS_CONTROL0_FEEDBACK
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG3_TMDS_STEREOSYNC_CTL_SEL
+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG3_TMDS_CTL_BITS
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG3_TMDS_DCBALANCER_CONTROL
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG3_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG3_TMDS_CTL0_1_GEN_CNTL
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG3_TMDS_CTL2_3_GEN_CNTL
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG3_DIG_VERSION
+#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG3_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG3_FORCE_DIG_DISABLE
+#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dcn_dc_dio_dp4_dispdec
+//DP4_DP_LINK_CNTL
+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP4_DP_PIXEL_FORMAT
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L
+//DP4_DP_MSA_COLORIMETRY
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP4_DP_CONFIG
+#define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP4_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP4_DP_VID_STREAM_CNTL
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP4_DP_STEER_FIFO
+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP4_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18
+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+#define DP4_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L
+//DP4_DP_MSA_MISC
+#define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP4_DP_DPHY_INTERNAL_CTRL
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP4_DP_VID_TIMING
+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP4_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP4_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP4_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP4_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP4_DP_VID_N
+#define DP4_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP4_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP4_DP_VID_M
+#define DP4_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP4_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP4_DP_LINK_FRAMING_CNTL
+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP4_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP4_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP4_DP_HBR2_EYE_PATTERN
+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP4_DP_VID_MSA_VBID
+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP4_DP_VID_INTERRUPT_CNTL
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP4_DP_DPHY_CNTL
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP4_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP4_DP_DPHY_SYM0
+#define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP4_DP_DPHY_SYM1
+#define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP4_DP_DPHY_SYM2
+#define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP4_DP_DPHY_8B10B_CNTL
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP4_DP_DPHY_PRBS_CNTL
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP4_DP_DPHY_SCRAM_CNTL
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP4_DP_DPHY_CRC_EN
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP4_DP_DPHY_CRC_CNTL
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP4_DP_DPHY_CRC_RESULT
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP4_DP_DPHY_CRC_MST_CNTL
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP4_DP_DPHY_CRC_MST_STATUS
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP4_DP_DPHY_FAST_TRAINING
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP4_DP_DPHY_FAST_TRAINING_STATUS
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP4_DP_SEC_CNTL
+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP4_DP_SEC_CNTL1
+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_SEC_FRAMING1
+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP4_DP_SEC_FRAMING2
+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP4_DP_SEC_FRAMING3
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP4_DP_SEC_FRAMING4
+#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP4_DP_SEC_AUD_N
+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP4_DP_SEC_AUD_N_READBACK
+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP4_DP_SEC_AUD_M
+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP4_DP_SEC_AUD_M_READBACK
+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP4_DP_SEC_TIMESTAMP
+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP4_DP_SEC_PACKET_CNTL
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP4_DP_MSE_RATE_CNTL
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP4_DP_MSE_RATE_UPDATE
+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP4_DP_MSE_SAT0
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP4_DP_MSE_SAT1
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP4_DP_MSE_SAT2
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP4_DP_MSE_SAT_UPDATE
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP4_DP_MSE_LINK_TIMING
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP4_DP_MSE_MISC_CNTL
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP4_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP4_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP4_DP_MSE_SAT0_STATUS
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP4_DP_MSE_SAT1_STATUS
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP4_DP_MSE_SAT2_STATUS
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP4_DP_DPIA_SPARE
+#define DP4_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0
+#define DP4_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L
+//DP4_DP_MSA_TIMING_PARAM1
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP4_DP_MSA_TIMING_PARAM2
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP4_DP_MSA_TIMING_PARAM3
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP4_DP_MSA_TIMING_PARAM4
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP4_DP_MSO_CNTL
+#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP4_DP_MSO_CNTL1
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP4_DP_DSC_CNTL
+#define DP4_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP4_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L
+//DP4_DP_SEC_CNTL2
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP4_DP_SEC_CNTL3
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_SEC_CNTL4
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_SEC_CNTL5
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_SEC_CNTL6
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP4_DP_SEC_CNTL7
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP4_DP_DB_CNTL
+#define DP4_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP4_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP4_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP4_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP4_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP4_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP4_DP_MSA_VBID_MISC
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP4_DP_SEC_METADATA_TRANSMISSION
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP4_DP_ALPM_CNTL
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP4_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP4_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP4_DP_GSP8_CNTL
+#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_GSP9_CNTL
+#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_GSP10_CNTL
+#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP4_DP_GSP11_CNTL
+#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP4_DP_GSP_EN_DB_STATUS
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+//DP4_DP_AUXLESS_ALPM_CNTL1
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L
+//DP4_DP_AUXLESS_ALPM_CNTL2
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT                                       0x8
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0xf
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT                                              0x10
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x16
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x17
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT                                              0x18
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK                                         0x00003F00L
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00008000L
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK                                                0x000F0000L
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00400000L
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00800000L
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK                                                0xFF000000L
+//DP4_DP_AUXLESS_ALPM_CNTL3
+#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0
+#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10
+#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL
+#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L
+//DP4_DP_AUXLESS_ALPM_CNTL4
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x0
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x8
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x9
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0xa
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0xb
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x0000007FL
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000100L
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000200L
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000400L
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000800L
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L
+//DP4_DP_AUXLESS_ALPM_CNTL5
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dio_dig4_dispdec
+//DIG4_DIG_FE_CNTL
+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG4_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf
+#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14
+#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG4_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L
+#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L
+#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG4_DIG_OUTPUT_CRC_CNTL
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG4_DIG_OUTPUT_CRC_RESULT
+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG4_DIG_CLOCK_PATTERN
+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG4_DIG_TEST_PATTERN
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG4_DIG_RANDOM_PATTERN_SEED
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG4_DIG_FIFO_CTRL0
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L
+//DIG4_DIG_FIFO_CTRL1
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L
+//DIG4_HDMI_METADATA_PACKET_CONTROL
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG4_HDMI_CONTROL
+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG4_HDMI_STATUS
+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG4_HDMI_AUDIO_PACKET_CONTROL
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG4_HDMI_ACR_PACKET_CONTROL
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG4_HDMI_VBI_PACKET_CONTROL
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L
+//DIG4_HDMI_INFOFRAME_CONTROL0
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG4_HDMI_INFOFRAME_CONTROL1
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG4_HDMI_GC
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG4_HDMI_DB_CONTROL
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG4_HDMI_ACR_32_0
+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG4_HDMI_ACR_32_1
+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG4_HDMI_ACR_44_0
+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG4_HDMI_ACR_44_1
+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG4_HDMI_ACR_48_0
+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG4_HDMI_ACR_48_1
+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG4_HDMI_ACR_STATUS_0
+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG4_HDMI_ACR_STATUS_1
+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG4_AFMT_CNTL
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG4_DIG_BE_CNTL
+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG4_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG4_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG4_DIG_BE_EN_CNTL
+#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG4_TMDS_CNTL
+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG4_TMDS_CONTROL_CHAR
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG4_TMDS_CONTROL0_FEEDBACK
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG4_TMDS_STEREOSYNC_CTL_SEL
+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG4_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG4_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG4_TMDS_CTL_BITS
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG4_TMDS_DCBALANCER_CONTROL
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG4_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG4_TMDS_CTL0_1_GEN_CNTL
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG4_TMDS_CTL2_3_GEN_CNTL
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG4_DIG_VERSION
+#define DIG4_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG4_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG4_FORCE_DIG_DISABLE
+#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dcn_dc_dio_dig0_afmt_afmt_dispdec
+//AFMT0_AFMT_VBI_PACKET_CONTROL
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT0_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT0_AFMT_AUDIO_INFO0
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT0_AFMT_AUDIO_INFO1
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT0_AFMT_60958_0
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT0_AFMT_60958_1
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT0_AFMT_AUDIO_CRC_CONTROL
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT0_AFMT_RAMP_CONTROL0
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT0_AFMT_RAMP_CONTROL1
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT0_AFMT_RAMP_CONTROL2
+#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT0_AFMT_RAMP_CONTROL3
+#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT0_AFMT_60958_2
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT0_AFMT_AUDIO_CRC_RESULT
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT0_AFMT_STATUS
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT0_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L
+//AFMT0_AFMT_INFOFRAME_CONTROL0
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT0_AFMT_INTERRUPT_STATUS
+//AFMT0_AFMT_AUDIO_SRC_CONTROL
+#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT0_AFMT_MEM_PWR
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dcn_dc_dio_dig1_afmt_afmt_dispdec
+//AFMT1_AFMT_VBI_PACKET_CONTROL
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT1_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT1_AFMT_AUDIO_INFO0
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT1_AFMT_AUDIO_INFO1
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT1_AFMT_60958_0
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT1_AFMT_60958_1
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT1_AFMT_AUDIO_CRC_CONTROL
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT1_AFMT_RAMP_CONTROL0
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT1_AFMT_RAMP_CONTROL1
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT1_AFMT_RAMP_CONTROL2
+#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT1_AFMT_RAMP_CONTROL3
+#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT1_AFMT_60958_2
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT1_AFMT_AUDIO_CRC_RESULT
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT1_AFMT_STATUS
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT1_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L
+//AFMT1_AFMT_INFOFRAME_CONTROL0
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT1_AFMT_INTERRUPT_STATUS
+//AFMT1_AFMT_AUDIO_SRC_CONTROL
+#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT1_AFMT_MEM_PWR
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dcn_dc_dio_dig2_afmt_afmt_dispdec
+//AFMT2_AFMT_VBI_PACKET_CONTROL
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT2_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT2_AFMT_AUDIO_INFO0
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT2_AFMT_AUDIO_INFO1
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT2_AFMT_60958_0
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT2_AFMT_60958_1
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT2_AFMT_AUDIO_CRC_CONTROL
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT2_AFMT_RAMP_CONTROL0
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT2_AFMT_RAMP_CONTROL1
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT2_AFMT_RAMP_CONTROL2
+#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT2_AFMT_RAMP_CONTROL3
+#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT2_AFMT_60958_2
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT2_AFMT_AUDIO_CRC_RESULT
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT2_AFMT_STATUS
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT2_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L
+//AFMT2_AFMT_INFOFRAME_CONTROL0
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT2_AFMT_INTERRUPT_STATUS
+//AFMT2_AFMT_AUDIO_SRC_CONTROL
+#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT2_AFMT_MEM_PWR
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dcn_dc_dio_dig3_afmt_afmt_dispdec
+//AFMT3_AFMT_VBI_PACKET_CONTROL
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT3_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT3_AFMT_AUDIO_INFO0
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT3_AFMT_AUDIO_INFO1
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT3_AFMT_60958_0
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT3_AFMT_60958_1
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT3_AFMT_AUDIO_CRC_CONTROL
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT3_AFMT_RAMP_CONTROL0
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT3_AFMT_RAMP_CONTROL1
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT3_AFMT_RAMP_CONTROL2
+#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT3_AFMT_RAMP_CONTROL3
+#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT3_AFMT_60958_2
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT3_AFMT_AUDIO_CRC_RESULT
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT3_AFMT_STATUS
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT3_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L
+//AFMT3_AFMT_INFOFRAME_CONTROL0
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT3_AFMT_INTERRUPT_STATUS
+//AFMT3_AFMT_AUDIO_SRC_CONTROL
+#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT3_AFMT_MEM_PWR
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dcn_dc_dio_dig4_afmt_afmt_dispdec
+//AFMT4_AFMT_VBI_PACKET_CONTROL
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT4_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT4_AFMT_AUDIO_INFO0
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT4_AFMT_AUDIO_INFO1
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT4_AFMT_60958_0
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT4_AFMT_60958_1
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT4_AFMT_AUDIO_CRC_CONTROL
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT4_AFMT_RAMP_CONTROL0
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT4_AFMT_RAMP_CONTROL1
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT4_AFMT_RAMP_CONTROL2
+#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT4_AFMT_RAMP_CONTROL3
+#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT4_AFMT_60958_2
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT4_AFMT_AUDIO_CRC_RESULT
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT4_AFMT_STATUS
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT4_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L
+//AFMT4_AFMT_INFOFRAME_CONTROL0
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT4_AFMT_INTERRUPT_STATUS
+//AFMT4_AFMT_AUDIO_SRC_CONTROL
+#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT4_AFMT_MEM_PWR
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dcn_dc_dio_dig0_dme_dme_dispdec
+//DME0_DME_CONTROL
+#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME0_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME0_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME0_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME0_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME0_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME0_DME_MEMORY_CONTROL
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dcn_dc_dio_dig0_vpg_vpg_dispdec
+//VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG0_VPG_GENERIC_PACKET_DATA
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG0_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG0_VPG_GENERIC_STATUS
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG0_VPG_MEM_PWR
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG0_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG0_VPG_ISRC1_2_DATA
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG0_VPG_MPEG_INFO0
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG0_VPG_MPEG_INFO1
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dcn_dc_dio_dig1_dme_dme_dispdec
+//DME1_DME_CONTROL
+#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME1_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME1_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME1_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME1_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME1_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME1_DME_MEMORY_CONTROL
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dcn_dc_dio_dig1_vpg_vpg_dispdec
+//VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG1_VPG_GENERIC_PACKET_DATA
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG1_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG1_VPG_GENERIC_STATUS
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG1_VPG_MEM_PWR
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG1_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG1_VPG_ISRC1_2_DATA
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG1_VPG_MPEG_INFO0
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG1_VPG_MPEG_INFO1
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dcn_dc_dio_dig2_dme_dme_dispdec
+//DME2_DME_CONTROL
+#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME2_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME2_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME2_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME2_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME2_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME2_DME_MEMORY_CONTROL
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dcn_dc_dio_dig2_vpg_vpg_dispdec
+//VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG2_VPG_GENERIC_PACKET_DATA
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG2_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG2_VPG_GENERIC_STATUS
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG2_VPG_MEM_PWR
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG2_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG2_VPG_ISRC1_2_DATA
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG2_VPG_MPEG_INFO0
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG2_VPG_MPEG_INFO1
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dcn_dc_dio_dig3_dme_dme_dispdec
+//DME3_DME_CONTROL
+#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME3_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME3_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME3_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME3_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME3_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME3_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME3_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME3_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME3_DME_MEMORY_CONTROL
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dcn_dc_dio_dig3_vpg_vpg_dispdec
+//VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG3_VPG_GENERIC_PACKET_DATA
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG3_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG3_VPG_GENERIC_STATUS
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG3_VPG_MEM_PWR
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG3_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG3_VPG_ISRC1_2_DATA
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG3_VPG_MPEG_INFO0
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG3_VPG_MPEG_INFO1
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dcn_dc_dio_dig4_dme_dme_dispdec
+//DME4_DME_CONTROL
+#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME4_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME4_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME4_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME4_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME4_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME4_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME4_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME4_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME4_DME_MEMORY_CONTROL
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dcn_dc_dio_dig4_vpg_vpg_dispdec
+//VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG4_VPG_GENERIC_PACKET_DATA
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG4_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG4_VPG_GENERIC_STATUS
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG4_VPG_MEM_PWR
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG4_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG4_VPG_ISRC1_2_DATA
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG4_VPG_MPEG_INFO0
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG4_VPG_MPEG_INFO1
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dcn_dc_dio_dp_aux0_dispdec
+//DP_AUX0_AUX_CONTROL
+#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX0_AUX_SW_CONTROL
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX0_AUX_ARB_CONTROL
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX0_AUX_INTERRUPT_CONTROL
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX0_AUX_SW_STATUS
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX0_AUX_LS_STATUS
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX0_AUX_SW_DATA
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX0_AUX_LS_DATA
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX0_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX0_AUX_DPHY_TX_CONTROL
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX0_AUX_DPHY_RX_CONTROL0
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX0_AUX_DPHY_RX_CONTROL1
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX0_AUX_DPHY_TX_STATUS
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX0_AUX_DPHY_RX_STATUS
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX0_AUX_GTC_SYNC_CONTROL
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX0_AUX_GTC_SYNC_STATUS
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX0_AUX_PHY_WAKE_CNTL
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dcn_dc_dio_dp_aux1_dispdec
+//DP_AUX1_AUX_CONTROL
+#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX1_AUX_SW_CONTROL
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX1_AUX_ARB_CONTROL
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX1_AUX_INTERRUPT_CONTROL
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX1_AUX_SW_STATUS
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX1_AUX_LS_STATUS
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX1_AUX_SW_DATA
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX1_AUX_LS_DATA
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX1_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX1_AUX_DPHY_TX_CONTROL
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX1_AUX_DPHY_RX_CONTROL0
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX1_AUX_DPHY_RX_CONTROL1
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX1_AUX_DPHY_TX_STATUS
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX1_AUX_DPHY_RX_STATUS
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX1_AUX_GTC_SYNC_CONTROL
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX1_AUX_GTC_SYNC_STATUS
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX1_AUX_PHY_WAKE_CNTL
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dcn_dc_dio_dp_aux2_dispdec
+//DP_AUX2_AUX_CONTROL
+#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX2_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX2_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX2_AUX_SW_CONTROL
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX2_AUX_ARB_CONTROL
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX2_AUX_INTERRUPT_CONTROL
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX2_AUX_SW_STATUS
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX2_AUX_LS_STATUS
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX2_AUX_SW_DATA
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX2_AUX_LS_DATA
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX2_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX2_AUX_DPHY_TX_CONTROL
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX2_AUX_DPHY_RX_CONTROL0
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX2_AUX_DPHY_RX_CONTROL1
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX2_AUX_DPHY_TX_STATUS
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX2_AUX_DPHY_RX_STATUS
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX2_AUX_GTC_SYNC_CONTROL
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX2_AUX_GTC_SYNC_STATUS
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX2_AUX_PHY_WAKE_CNTL
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dcn_dc_dio_dp_aux3_dispdec
+//DP_AUX3_AUX_CONTROL
+#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX3_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX3_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX3_AUX_SW_CONTROL
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX3_AUX_ARB_CONTROL
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX3_AUX_INTERRUPT_CONTROL
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX3_AUX_SW_STATUS
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX3_AUX_LS_STATUS
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX3_AUX_SW_DATA
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX3_AUX_LS_DATA
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX3_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX3_AUX_DPHY_TX_CONTROL
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX3_AUX_DPHY_RX_CONTROL0
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX3_AUX_DPHY_RX_CONTROL1
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX3_AUX_DPHY_TX_STATUS
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX3_AUX_DPHY_RX_STATUS
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX3_AUX_GTC_SYNC_CONTROL
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX3_AUX_GTC_SYNC_STATUS
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX3_AUX_PHY_WAKE_CNTL
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dcn_dc_dio_dp_aux4_dispdec
+//DP_AUX4_AUX_CONTROL
+#define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX4_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX4_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX4_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX4_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX4_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX4_AUX_SW_CONTROL
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX4_AUX_ARB_CONTROL
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX4_AUX_INTERRUPT_CONTROL
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX4_AUX_SW_STATUS
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX4_AUX_LS_STATUS
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX4_AUX_SW_DATA
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX4_AUX_LS_DATA
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX4_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX4_AUX_DPHY_TX_CONTROL
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX4_AUX_DPHY_RX_CONTROL0
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX4_AUX_DPHY_RX_CONTROL1
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX4_AUX_DPHY_TX_STATUS
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX4_AUX_DPHY_RX_STATUS
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX4_AUX_GTC_SYNC_CONTROL
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX4_AUX_GTC_SYNC_STATUS
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX4_AUX_PHY_WAKE_CNTL
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dcn_dc_dio_dout_i2c_dispdec
+//DC_I2C_CONTROL
+#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT                                                                      0x0
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT                                                              0x1
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT                                                              0x2
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT                                                         0x3
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT                                                              0x8
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT                                                       0x14
+#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT                                                             0x1f
+#define DC_I2C_CONTROL__DC_I2C_GO_MASK                                                                        0x00000001L
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK                                                                0x00000002L
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK                                                                0x00000004L
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK                                                           0x00000008L
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK                                                                0x00000700L
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK                                                         0x00300000L
+#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK                                                               0x80000000L
+//DC_I2C_ARBITRATION
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT                                                         0x0
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT                                                  0x2
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT                                                     0x4
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT                                                       0x8
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT                                                       0xc
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT                                                  0x14
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT                                               0x15
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT                                                0x18
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT                                             0x19
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK                                                           0x00000003L
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK                                                    0x0000000CL
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK                                                       0x00000010L
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK                                                         0x00000100L
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK                                                         0x00001000L
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK                                                    0x00100000L
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK                                                 0x00200000L
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK                                                  0x01000000L
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK                                               0x02000000L
+//DC_I2C_INTERRUPT_CONTROL
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT                                                   0x0
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT                                                   0x1
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT                                                  0x2
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT                                              0x4
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT                                              0x5
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT                                             0x6
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT                                              0x8
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT                                              0x9
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT                                             0xa
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT                                              0xc
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT                                              0xd
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT                                             0xe
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT                                              0x10
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT                                              0x11
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT                                             0x12
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT                                              0x14
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT                                              0x15
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT                                             0x16
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT                                              0x18
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT                                              0x19
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT                                             0x1a
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT                                            0x1b
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT                                            0x1c
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT                                           0x1d
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK                                                     0x00000001L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK                                                     0x00000002L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK                                                    0x00000004L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK                                                0x00000010L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK                                                0x00000020L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK                                               0x00000040L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK                                                0x00000100L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK                                                0x00000200L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK                                               0x00000400L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK                                                0x00001000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK                                                0x00002000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK                                               0x00004000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK                                                0x00010000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK                                                0x00020000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK                                               0x00040000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK                                                0x00100000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK                                                0x00200000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK                                               0x00400000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK                                                0x01000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK                                                0x02000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK                                               0x04000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK                                              0x08000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK                                              0x10000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK                                             0x20000000L
+//DC_I2C_SW_STATUS
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT                                                             0x0
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT                                                               0x2
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT                                                            0x4
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT                                                            0x5
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT                                                        0x6
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT                                                    0x7
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT                                                    0x8
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT                                                              0xc
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT                                                              0xd
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT                                                              0xe
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT                                                              0xf
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT                                                                0x12
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK                                                               0x00000003L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK                                                                 0x00000004L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK                                                              0x00000010L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK                                                              0x00000020L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK                                                          0x00000040L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK                                                      0x00000080L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK                                                      0x00000100L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK                                                                0x00001000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK                                                                0x00002000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK                                                                0x00004000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK                                                                0x00008000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK                                                                  0x00040000L
+//DC_I2C_DDC1_HW_STATUS
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC2_HW_STATUS
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC3_HW_STATUS
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC4_HW_STATUS
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC5_HW_STATUS
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC1_SPEED
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC1_SETUP
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC2_SPEED
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC2_SETUP
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC3_SPEED
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC3_SETUP
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC4_SPEED
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC4_SETUP
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC5_SPEED
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC5_SETUP
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_TRANSACTION0
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK                                                               0x03FF0000L
+//DC_I2C_TRANSACTION1
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK                                                               0x03FF0000L
+//DC_I2C_TRANSACTION2
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK                                                               0x03FF0000L
+//DC_I2C_TRANSACTION3
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK                                                               0x03FF0000L
+//DC_I2C_DATA
+#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT                                                                    0x0
+#define DC_I2C_DATA__DC_I2C_DATA__SHIFT                                                                       0x8
+#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT                                                                      0x10
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT                                                                0x1f
+#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK                                                                      0x00000001L
+#define DC_I2C_DATA__DC_I2C_DATA_MASK                                                                         0x0000FF00L
+#define DC_I2C_DATA__DC_I2C_INDEX_MASK                                                                        0x03FF0000L
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK                                                                  0x80000000L
+//DC_I2C_EDID_DETECT_CTRL
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT                                          0x0
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT                              0x14
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT                                         0x1c
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK                                            0x0000FFFFL
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK                                0x00F00000L
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK                                           0x10000000L
+//DC_I2C_READ_REQUEST_INTERRUPT
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT                               0x0
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT                                    0x1
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT                                    0x2
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT                                   0x3
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT                               0x4
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT                                    0x5
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT                                    0x6
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT                                   0x7
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT                               0x8
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT                                    0x9
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT                                    0xa
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT                                   0xb
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT                               0xc
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT                                    0xd
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT                                    0xe
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT                                   0xf
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT                               0x10
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT                                    0x11
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT                                    0x12
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT                                   0x13
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT                               0x14
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT                                    0x15
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT                                    0x16
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT                                   0x17
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT                             0x18
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT                                  0x19
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT                                  0x1a
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT                                 0x1b
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT                              0x1e
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT                                0x1f
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK                                 0x00000001L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK                                      0x00000002L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK                                      0x00000004L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK                                     0x00000008L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK                                 0x00000010L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK                                      0x00000020L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK                                      0x00000040L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK                                     0x00000080L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK                                 0x00000100L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK                                      0x00000200L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK                                      0x00000400L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK                                     0x00000800L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK                                 0x00001000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK                                      0x00002000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK                                      0x00004000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK                                     0x00008000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK                                 0x00010000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK                                      0x00020000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK                                      0x00040000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK                                     0x00080000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK                                 0x00100000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK                                      0x00200000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK                                      0x00400000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK                                     0x00800000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK                               0x01000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK                                    0x02000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK                                    0x04000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK                                   0x08000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK                                0x40000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK                                  0x80000000L
+
+
+// addressBlock: dcn_dc_dio_dio_misc_dispdec
+//DIO_SCRATCH0
+#define DIO_SCRATCH0__DIO_SCRATCH0__SHIFT                                                                     0x0
+#define DIO_SCRATCH0__DIO_SCRATCH0_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH1
+#define DIO_SCRATCH1__DIO_SCRATCH1__SHIFT                                                                     0x0
+#define DIO_SCRATCH1__DIO_SCRATCH1_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH2
+#define DIO_SCRATCH2__DIO_SCRATCH2__SHIFT                                                                     0x0
+#define DIO_SCRATCH2__DIO_SCRATCH2_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH3
+#define DIO_SCRATCH3__DIO_SCRATCH3__SHIFT                                                                     0x0
+#define DIO_SCRATCH3__DIO_SCRATCH3_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH4
+#define DIO_SCRATCH4__DIO_SCRATCH4__SHIFT                                                                     0x0
+#define DIO_SCRATCH4__DIO_SCRATCH4_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH5
+#define DIO_SCRATCH5__DIO_SCRATCH5__SHIFT                                                                     0x0
+#define DIO_SCRATCH5__DIO_SCRATCH5_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH6
+#define DIO_SCRATCH6__DIO_SCRATCH6__SHIFT                                                                     0x0
+#define DIO_SCRATCH6__DIO_SCRATCH6_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH7
+#define DIO_SCRATCH7__DIO_SCRATCH7__SHIFT                                                                     0x0
+#define DIO_SCRATCH7__DIO_SCRATCH7_MASK                                                                       0xFFFFFFFFL
+//DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGA_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x0
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGB_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x1
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGC_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x2
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGD_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x3
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGE_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x4
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGF_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x5
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGG_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x6
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGA_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000001L
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGB_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000002L
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGC_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000004L
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGD_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000008L
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGE_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000010L
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGF_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000020L
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGG_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000040L
+//DIO_MEM_PWR_STATUS
+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT                                                          0x0
+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT                                                          0x3
+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT                                                          0x4
+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT                                                          0x5
+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT                                                          0x6
+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT                                                          0x7
+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT                                                          0x8
+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT                                                          0x9
+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK                                                            0x00000001L
+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK                                                            0x00000008L
+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK                                                            0x00000010L
+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK                                                            0x00000020L
+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK                                                            0x00000040L
+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK                                                            0x00000080L
+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK                                                            0x00000100L
+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK                                                            0x00000200L
+//DIO_MEM_PWR_CTRL
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT                                                        0x0
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT                                                          0x1
+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT                                                          0x4
+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT                                                          0x5
+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT                                                          0x6
+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT                                                          0x7
+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT                                                          0x8
+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT                                                          0x9
+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT                                                          0xa
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK                                                          0x00000001L
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK                                                            0x00000002L
+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK                                                            0x00000010L
+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK                                                            0x00000020L
+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK                                                            0x00000040L
+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK                                                            0x00000080L
+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK                                                            0x00000100L
+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK                                                            0x00000200L
+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK                                                            0x00000400L
+//DIO_MEM_PWR_CTRL2
+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE__SHIFT                                                       0x18
+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE__SHIFT                                                       0x19
+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1a
+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1b
+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1c
+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1d
+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1e
+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE_MASK                                                         0x01000000L
+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE_MASK                                                         0x02000000L
+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE_MASK                                                         0x04000000L
+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE_MASK                                                         0x08000000L
+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE_MASK                                                         0x10000000L
+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE_MASK                                                         0x20000000L
+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE_MASK                                                         0x40000000L
+//DIO_CLK_CNTL
+#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS__SHIFT                                                           0x5
+#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS__SHIFT                                                            0xa
+#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT                                                          0x18
+#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT                                                          0x19
+#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT                                                          0x1a
+#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT                                                          0x1b
+#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT                                                          0x1c
+#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT                                                          0x1d
+#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT                                                          0x1e
+#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS_MASK                                                             0x00000020L
+#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS_MASK                                                              0x00000400L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK                                                            0x01000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK                                                            0x02000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK                                                            0x04000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK                                                            0x08000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK                                                            0x10000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK                                                            0x20000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK                                                            0x40000000L
+//DIO_POWER_MANAGEMENT_CNTL
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT                                                     0x0
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT                                                     0x8
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK                                                       0x00000001L
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK                                                       0x00000100L
+//DIG_SOFT_RESET
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT                                                             0x0
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT                                                             0x1
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT                                                             0x4
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT                                                             0x5
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT                                                             0x8
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT                                                             0x9
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT                                                             0xc
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT                                                             0xd
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT                                                             0x10
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT                                                             0x11
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT                                                             0x14
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT                                                             0x15
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT                                                             0x18
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT                                                             0x19
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK                                                               0x00000001L
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK                                                               0x00000002L
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK                                                               0x00000010L
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK                                                               0x00000020L
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK                                                               0x00000100L
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK                                                               0x00000200L
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK                                                               0x00001000L
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK                                                               0x00002000L
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK                                                               0x00010000L
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK                                                               0x00020000L
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK                                                               0x00100000L
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK                                                               0x00200000L
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK                                                               0x01000000L
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK                                                               0x02000000L
+//DIO_CLK_CNTL2
+#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL__SHIFT                                                                0x0
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS__SHIFT                                                         0x7
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS__SHIFT                                                         0x8
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS__SHIFT                                                         0x9
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS__SHIFT                                                         0xa
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS__SHIFT                                                         0xb
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS__SHIFT                                                         0xc
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS__SHIFT                                                         0xd
+#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x11
+#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x12
+#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x13
+#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x14
+#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x15
+#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x16
+#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x17
+#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS__SHIFT                                                           0x18
+#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS__SHIFT                                                           0x19
+#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS__SHIFT                                                           0x1a
+#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS__SHIFT                                                           0x1b
+#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS__SHIFT                                                           0x1c
+#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS__SHIFT                                                           0x1d
+#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS__SHIFT                                                           0x1e
+#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL_MASK                                                                  0x0000007FL
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS_MASK                                                           0x00000080L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS_MASK                                                           0x00000100L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS_MASK                                                           0x00000200L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS_MASK                                                           0x00000400L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS_MASK                                                           0x00000800L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS_MASK                                                           0x00001000L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS_MASK                                                           0x00002000L
+#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK                                                        0x00020000L
+#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK                                                        0x00040000L
+#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK                                                        0x00080000L
+#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK                                                        0x00100000L
+#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK                                                        0x00200000L
+#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK                                                        0x00400000L
+#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK                                                        0x00800000L
+#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS_MASK                                                             0x01000000L
+#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS_MASK                                                             0x02000000L
+#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS_MASK                                                             0x04000000L
+#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS_MASK                                                             0x08000000L
+#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS_MASK                                                             0x10000000L
+#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS_MASK                                                             0x20000000L
+#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS_MASK                                                             0x40000000L
+//DIO_CLK_CNTL3
+#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x0
+#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x1
+#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x2
+#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x3
+#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x4
+#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x5
+#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x6
+#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT                                                         0xa
+#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT                                                         0xb
+#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT                                                         0xc
+#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT                                                         0xd
+#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT                                                         0xe
+#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT                                                         0xf
+#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT                                                         0x10
+#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000001L
+#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000002L
+#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000004L
+#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000008L
+#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000010L
+#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000020L
+#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000040L
+#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK                                                           0x00000400L
+#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK                                                           0x00000800L
+#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK                                                           0x00001000L
+#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK                                                           0x00002000L
+#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK                                                           0x00004000L
+#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK                                                           0x00008000L
+#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK                                                           0x00010000L
+//DIO_HDMI_RXSTATUS_TIMER_CONTROL
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT                                0x0
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT                                  0x4
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT                                0x8
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT                                  0xc
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT                              0x10
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK                                  0x00000001L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK                                    0x00000010L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK                                  0x00000100L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK                                    0x00001000L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK                                0x0FFF0000L
+//DIO_LINKA_CNTL
+#define DIO_LINKA_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKA_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKA_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKA_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKA_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKA_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKB_CNTL
+#define DIO_LINKB_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKB_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKB_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKB_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKB_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKB_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKC_CNTL
+#define DIO_LINKC_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKC_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKC_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKC_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKC_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKC_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKD_CNTL
+#define DIO_LINKD_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKD_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKD_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKD_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKD_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKD_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKE_CNTL
+#define DIO_LINKE_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKE_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKE_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKE_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKE_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKE_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKF_CNTL
+#define DIO_LINKF_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKF_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKF_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKF_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKF_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKF_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+
+
+// addressBlock: dcn_dc_dcio_dcio_dispdec
+//DC_GENERICA
+#define DC_GENERICA__GENERICA_EN__SHIFT                                                                       0x0
+#define DC_GENERICA__GENERICA_SEL__SHIFT                                                                      0x7
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
+#define DC_GENERICA__GENERICA_EN_MASK                                                                         0x00000001L
+#define DC_GENERICA__GENERICA_SEL_MASK                                                                        0x00000F80L
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
+//DC_GENERICB
+#define DC_GENERICB__GENERICB_EN__SHIFT                                                                       0x0
+#define DC_GENERICB__GENERICB_SEL__SHIFT                                                                      0x8
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
+#define DC_GENERICB__GENERICB_EN_MASK                                                                         0x00000001L
+#define DC_GENERICB__GENERICB_SEL_MASK                                                                        0x00000F00L
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
+//DCIO_CLOCK_CNTL
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT                                                             0x0
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT                                                       0x5
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK                                                               0x0000001FL
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK                                                         0x00000020L
+//DC_REF_CLK_CNTL
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT                                                             0x0
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT                                                          0x8
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK                                                               0x00000003L
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK                                                            0x00000300L
+//UNIPHYA_CHANNEL_XBAR_CNTL
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYB_CHANNEL_XBAR_CNTL
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYC_CHANNEL_XBAR_CNTL
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYD_CHANNEL_XBAR_CNTL
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYE_CHANNEL_XBAR_CNTL
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//DCIO_WRCMD_DELAY
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT                                                                 0x18
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK                                                                   0xFF000000L
+//DC_PINSTRAPS
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT                                                         0xd
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT                                                               0xe
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT                                                            0x10
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT                                                        0x11
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK                                                           0x00002000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK                                                                 0x0000C000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK                                                              0x00010000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK                                                          0x000E0000L
+//DCIO_SPARE
+#define DCIO_SPARE__DCIO_SPARE__SHIFT                                                                         0x0
+#define DCIO_SPARE__DCIO_SPARE_MASK                                                                           0xFFFFFFFFL
+//INTERCEPT_STATE
+#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE__SHIFT                                                      0x0
+#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE__SHIFT                                                      0x1
+#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE__SHIFT                                                        0x4
+#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE__SHIFT                                                        0x5
+#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE__SHIFT                                                        0x6
+#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE__SHIFT                                                        0x7
+#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE__SHIFT                                                        0x8
+#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE__SHIFT                                                        0x9
+#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE__SHIFT                                                        0xa
+#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE_MASK                                                        0x00000001L
+#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE_MASK                                                        0x00000002L
+#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE_MASK                                                          0x00000010L
+#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE_MASK                                                          0x00000020L
+#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE_MASK                                                          0x00000040L
+#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE_MASK                                                          0x00000080L
+#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE_MASK                                                          0x00000100L
+#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE_MASK                                                          0x00000200L
+#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE_MASK                                                          0x00000400L
+//DCIO_PATTERN_GEN_PAT
+#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT__SHIFT                                                     0x0
+#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT_MASK                                                       0xFFFFFFFFL
+//DCIO_PATTERN_GEN_EN
+#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN__SHIFT                                                       0x0
+#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN_MASK                                                         0x00000001L
+//DCIO_BL_PWM_FRAME_START_DISP_SEL
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x0
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x4
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000007L
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000070L
+//DCIO_GSL_GENLK_PAD_CNTL
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT                                     0x4
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT                                               0x8
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT                                   0x14
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT                                             0x18
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK                                       0x00000030L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK                                                 0x00000300L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK                                     0x00300000L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK                                               0x03000000L
+//DCIO_GSL_SWAPLOCK_PAD_CNTL
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT                                 0x4
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT                                           0x8
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT                                 0x14
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT                                           0x18
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK                                   0x00000030L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK                                             0x00000300L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK                                   0x00300000L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK                                             0x03000000L
+//DCIO_SOFT_RESET
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT                                                            0x0
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT                                                            0x1
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT                                                            0x2
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT                                                            0x3
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT                                                            0x4
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT                                                            0x5
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT                                                            0x6
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT                                                             0x8
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT                                                             0x9
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT                                                             0xa
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT                                                             0xb
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT                                                             0xc
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT                                                             0xd
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT                                                             0xe
+#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET__SHIFT                                                            0x10
+#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET__SHIFT                                                            0x11
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK                                                              0x00000001L
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK                                                              0x00000002L
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK                                                              0x00000004L
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK                                                              0x00000008L
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK                                                              0x00000010L
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK                                                              0x00000020L
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK                                                              0x00000040L
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK                                                               0x00000100L
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK                                                               0x00000200L
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK                                                               0x00000400L
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK                                                               0x00000800L
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK                                                               0x00001000L
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK                                                               0x00002000L
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK                                                               0x00004000L
+#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET_MASK                                                              0x00010000L
+#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET_MASK                                                              0x00020000L
+
+
+// addressBlock: dcn_dc_dcio_dcio_chip_dispdec
+//DC_GPIO_GENERIC_MASK
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT                                                    0x0
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT                                                  0x1
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT                                                    0x2
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT                                                    0x4
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT                                                  0x5
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT                                                    0x6
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT                                                    0x8
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT                                                  0x9
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT                                                    0xa
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT                                                    0xc
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT                                                  0xd
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT                                                    0xe
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT                                                    0x10
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT                                                  0x11
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT                                                    0x12
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT                                                    0x14
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT                                                  0x15
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT                                                    0x16
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT                                                    0x18
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT                                                  0x19
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT                                                    0x1a
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN__SHIFT                                             0x1c
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK                                                      0x00000001L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK                                                    0x00000002L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK                                                      0x0000000CL
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK                                                      0x00000010L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK                                                    0x00000020L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK                                                      0x000000C0L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK                                                      0x00000100L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK                                                    0x00000200L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK                                                      0x00000C00L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK                                                      0x00001000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK                                                    0x00002000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK                                                      0x0000C000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK                                                      0x00010000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK                                                    0x00020000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK                                                      0x000C0000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK                                                      0x00100000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK                                                    0x00200000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK                                                      0x00C00000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK                                                      0x01000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK                                                    0x02000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK                                                      0x0C000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN_MASK                                               0xF0000000L
+//DC_GPIO_GENERIC_A
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT                                                          0x0
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT                                                          0x8
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT                                                          0x10
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT                                                          0x14
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT                                                          0x15
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT                                                          0x16
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT                                                          0x17
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK                                                            0x00000001L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK                                                            0x00000100L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK                                                            0x00010000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK                                                            0x00100000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK                                                            0x00200000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK                                                            0x00400000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK                                                            0x00800000L
+//DC_GPIO_GENERIC_EN
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT                                                        0x0
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT                                                        0x8
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT                                                        0x10
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT                                                        0x14
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT                                                        0x15
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT                                                        0x16
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT                                                        0x17
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK                                                          0x00000001L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK                                                          0x00000100L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK                                                          0x00010000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK                                                          0x00100000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK                                                          0x00200000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK                                                          0x00400000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK                                                          0x00800000L
+//DC_GPIO_GENERIC_Y
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT                                                          0x0
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT                                                          0x8
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT                                                          0x10
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT                                                          0x14
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT                                                          0x15
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT                                                          0x16
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT                                                          0x17
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK                                                            0x00000001L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK                                                            0x00000100L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK                                                            0x00010000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK                                                            0x00100000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK                                                            0x00200000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK                                                            0x00400000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK                                                            0x00800000L
+//DC_GPIO_DDC1_MASK
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC1_A
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC1_EN
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC1_Y
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC2_MASK
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC2_A
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC2_EN
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC2_Y
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC3_MASK
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC3_A
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC3_EN
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC3_Y
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC4_MASK
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC4_A
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC4_EN
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC4_Y
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC5_MASK
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC5_A
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC5_EN
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC5_Y
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDCVGA_MASK
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT                                                    0x0
+#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY__SHIFT                                              0x4
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT                                                    0x6
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT                                                   0x8
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT                                                  0xc
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT                                                   0xe
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT                                                           0x10
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT                                                                0x14
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT                                                     0x16
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT                                                     0x18
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT                                                    0x1c
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK                                                      0x00000001L
+#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY_MASK                                                0x00000010L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK                                                      0x00000040L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK                                                     0x00000100L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK                                                    0x00001000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK                                                     0x00004000L
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK                                                             0x00010000L
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK                                                                  0x00100000L
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK                                                       0x00400000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK                                                       0x0F000000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK                                                      0xF0000000L
+//DC_GPIO_DDCVGA_A
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT                                                          0x0
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT                                                         0x8
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK                                                            0x00000001L
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK                                                           0x00000100L
+//DC_GPIO_DDCVGA_EN
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT                                                        0x0
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT                                                       0x8
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK                                                          0x00000001L
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK                                                         0x00000100L
+//DC_GPIO_DDCVGA_Y
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT                                                          0x0
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT                                                         0x8
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK                                                            0x00000001L
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK                                                           0x00000100L
+//DC_GPIO_GENLK_MASK
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT                                                     0x0
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT                                                   0x1
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT                                                    0x3
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT                                                     0x4
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT                                                   0x8
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT                                                 0x9
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT                                                  0xb
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT                                                   0xc
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT                                                    0x10
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT                                                  0x11
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT                                                   0x13
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT                                                    0x14
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT                                                    0x18
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT                                                  0x19
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT                                                   0x1b
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT                                                    0x1c
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK                                                       0x00000001L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK                                                     0x00000002L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK                                                      0x00000008L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK                                                       0x00000030L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK                                                     0x00000100L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK                                                   0x00000200L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK                                                    0x00000800L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK                                                     0x00003000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK                                                      0x00010000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK                                                    0x00020000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK                                                     0x00080000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK                                                      0x00300000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK                                                      0x01000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK                                                    0x02000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK                                                     0x08000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK                                                      0x30000000L
+//DC_GPIO_GENLK_A
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT                                                           0x0
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT                                                         0x8
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT                                                          0x10
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT                                                          0x18
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK                                                             0x00000001L
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK                                                           0x00000100L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK                                                            0x00010000L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK                                                            0x01000000L
+//DC_GPIO_GENLK_EN
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT                                                         0x0
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT                                                       0x8
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT                                                        0x10
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT                                                        0x18
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK                                                           0x00000001L
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK                                                         0x00000100L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK                                                          0x00010000L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK                                                          0x01000000L
+//DC_GPIO_GENLK_Y
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT                                                           0x0
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT                                                         0x8
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT                                                          0x10
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT                                                          0x18
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK                                                             0x00000001L
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK                                                           0x00000100L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK                                                            0x00010000L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK                                                            0x01000000L
+//DC_GPIO_HPD_MASK
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT                                                            0x0
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT                                                          0x4
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT                                                            0x6
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT                                                            0x8
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT                                                          0x9
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT                                                            0xa
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT                                                            0x10
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT                                                          0x11
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT                                                            0x12
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT                                                            0x14
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT                                                          0x15
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT                                                            0x16
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT                                                            0x18
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT                                                          0x19
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT                                                            0x1a
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT                                                            0x1c
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT                                                          0x1d
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT                                                            0x1e
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK                                                              0x00000001L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK                                                            0x00000010L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK                                                              0x000000C0L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK                                                              0x00000100L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK                                                            0x00000200L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK                                                              0x00000C00L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK                                                              0x00010000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK                                                            0x00020000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK                                                              0x000C0000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK                                                              0x00100000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK                                                            0x00200000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK                                                              0x00C00000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK                                                              0x01000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK                                                            0x02000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK                                                              0x0C000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK                                                              0x10000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK                                                            0x20000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK                                                              0xC0000000L
+//DC_GPIO_HPD_A
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT                                                                  0x0
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT                                                                  0x8
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT                                                                  0x10
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT                                                                  0x18
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT                                                                  0x1a
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT                                                                  0x1c
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK                                                                    0x00000001L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK                                                                    0x00000100L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK                                                                    0x00010000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK                                                                    0x01000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK                                                                    0x04000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK                                                                    0x10000000L
+//DC_GPIO_HPD_EN
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT                                                                0x0
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT                                                                 0x1
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT                                                                 0x2
+#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT                                                                   0x5
+#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT                                                                      0x6
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT                                                                0x8
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT                                                                 0x9
+#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT                                                                   0xa
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT                                                                0x10
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT                                                                 0x11
+#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT                                                                   0x12
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT                                                                0x14
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT                                                                 0x15
+#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT                                                                   0x16
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT                                                                0x18
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT                                                                 0x19
+#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT                                                                   0x1a
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT                                                                0x1c
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT                                                                 0x1d
+#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT                                                                   0x1e
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK                                                                  0x00000001L
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK                                                                   0x00000002L
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK                                                                   0x00000004L
+#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK                                                                     0x00000020L
+#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK                                                                        0x00000040L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK                                                                  0x00000100L
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK                                                                   0x00000200L
+#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK                                                                     0x00000400L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK                                                                  0x00010000L
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK                                                                   0x00020000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK                                                                     0x00040000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK                                                                  0x00100000L
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK                                                                   0x00200000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK                                                                     0x00400000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK                                                                  0x01000000L
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK                                                                   0x02000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK                                                                     0x04000000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK                                                                  0x10000000L
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK                                                                   0x20000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK                                                                     0x40000000L
+//DC_GPIO_HPD_Y
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT                                                                  0x0
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT                                                                  0x8
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT                                                                  0x10
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT                                                                  0x18
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT                                                                  0x1a
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT                                                                  0x1c
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK                                                                    0x00000001L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK                                                                    0x00000100L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK                                                                    0x00010000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK                                                                    0x01000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK                                                                    0x04000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK                                                                    0x10000000L
+//DC_GPIO_DRIVE_STRENGTH_S0
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICA_S0__SHIFT                                                 0x0
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICB_S0__SHIFT                                                 0x1
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICC_S0__SHIFT                                                 0x2
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICD_S0__SHIFT                                                 0x3
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICE_S0__SHIFT                                                 0x4
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICF_S0__SHIFT                                                 0x5
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICG_S0__SHIFT                                                 0x6
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_CLK_S0__SHIFT                                                0x8
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_VSYNC_S0__SHIFT                                              0x9
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_A_S0__SHIFT                                               0xa
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_B_S0__SHIFT                                               0xb
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICA_S0_MASK                                                   0x00000001L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICB_S0_MASK                                                   0x00000002L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICC_S0_MASK                                                   0x00000004L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICD_S0_MASK                                                   0x00000008L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICE_S0_MASK                                                   0x00000010L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICF_S0_MASK                                                   0x00000020L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICG_S0_MASK                                                   0x00000040L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_CLK_S0_MASK                                                  0x00000100L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_VSYNC_S0_MASK                                                0x00000200L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_A_S0_MASK                                                 0x00000400L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_B_S0_MASK                                                 0x00000800L
+//DC_GPIO_DRIVE_STRENGTH_S1
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICA_S1__SHIFT                                                 0x0
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICB_S1__SHIFT                                                 0x1
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICC_S1__SHIFT                                                 0x2
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICD_S1__SHIFT                                                 0x3
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICE_S1__SHIFT                                                 0x4
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICF_S1__SHIFT                                                 0x5
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICG_S1__SHIFT                                                 0x6
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_CLK_S1__SHIFT                                                0x8
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_VSYNC_S1__SHIFT                                              0x9
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_A_S1__SHIFT                                               0xa
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_B_S1__SHIFT                                               0xb
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICA_S1_MASK                                                   0x00000001L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICB_S1_MASK                                                   0x00000002L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICC_S1_MASK                                                   0x00000004L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICD_S1_MASK                                                   0x00000008L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICE_S1_MASK                                                   0x00000010L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICF_S1_MASK                                                   0x00000020L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICG_S1_MASK                                                   0x00000040L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_CLK_S1_MASK                                                  0x00000100L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_VSYNC_S1_MASK                                                0x00000200L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_A_S1_MASK                                                 0x00000400L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_B_S1_MASK                                                 0x00000800L
+//DC_GPIO_PWRSEQ0_EN
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT                                               0x14
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT                                              0x15
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT                                                  0x19
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT                                                 0x1a
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                0x1d
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK                                                 0x00100000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK                                                0x00E00000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK                                                    0x02000000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK                                                   0x1C000000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                  0x20000000L
+//DC_GPIO_PAD_STRENGTH_1
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT                                                      0x0
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT                                                      0x4
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT                                                     0x10
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT                                                     0x14
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT                                                       0x18
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT                                                       0x1c
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK                                                        0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK                                                        0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK                                                       0x000F0000L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK                                                       0x00F00000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK                                                         0x0F000000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK                                                         0xF0000000L
+//DC_GPIO_PAD_STRENGTH_2
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT                                                            0x0
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT                                                            0x4
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT                                                  0x8
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT                                                     0xc
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT                                                         0x1e
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK                                                              0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK                                                              0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK                                                    0x00000700L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK                                                       0x00007000L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK                                                           0xC0000000L
+//PHY_AUX_CNTL
+#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT                                                                     0x9
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT                                                                   0xa
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT                                                                   0xc
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT                                                                   0xe
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT                                                                   0x10
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT                                                                   0x12
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT                                                                   0x14
+#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK                                                                       0x00000200L
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK                                                                     0x00000C00L
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK                                                                     0x00003000L
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK                                                                     0x0000C000L
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK                                                                     0x00030000L
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK                                                                     0x000C0000L
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK                                                                     0x00300000L
+//DC_GPIO_DRIVE_TXIMPSEL
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICA_TXIMPSEL__SHIFT                                              0x0
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICB_TXIMPSEL__SHIFT                                              0x1
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICC_TXIMPSEL__SHIFT                                              0x2
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICD_TXIMPSEL__SHIFT                                              0x3
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICE_TXIMPSEL__SHIFT                                              0x4
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICF_TXIMPSEL__SHIFT                                              0x5
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICG_TXIMPSEL__SHIFT                                              0x6
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_CLK_TXIMPSEL__SHIFT                                             0x8
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_VSYNC_TXIMPSEL__SHIFT                                           0x9
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_A_TXIMPSEL__SHIFT                                            0xa
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_B_TXIMPSEL__SHIFT                                            0xb
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD1_TXIMPSEL__SHIFT                                                  0xc
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD2_TXIMPSEL__SHIFT                                                  0xd
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD3_TXIMPSEL__SHIFT                                                  0xe
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD4_TXIMPSEL__SHIFT                                                  0xf
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD5_TXIMPSEL__SHIFT                                                  0x10
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD6_TXIMPSEL__SHIFT                                                  0x11
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICA_TXIMPSEL_MASK                                                0x00000001L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICB_TXIMPSEL_MASK                                                0x00000002L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICC_TXIMPSEL_MASK                                                0x00000004L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICD_TXIMPSEL_MASK                                                0x00000008L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICE_TXIMPSEL_MASK                                                0x00000010L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICF_TXIMPSEL_MASK                                                0x00000020L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICG_TXIMPSEL_MASK                                                0x00000040L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_CLK_TXIMPSEL_MASK                                               0x00000100L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_VSYNC_TXIMPSEL_MASK                                             0x00000200L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_A_TXIMPSEL_MASK                                              0x00000400L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_B_TXIMPSEL_MASK                                              0x00000800L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD1_TXIMPSEL_MASK                                                    0x00001000L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD2_TXIMPSEL_MASK                                                    0x00002000L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD3_TXIMPSEL_MASK                                                    0x00004000L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD4_TXIMPSEL_MASK                                                    0x00008000L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD5_TXIMPSEL_MASK                                                    0x00010000L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD6_TXIMPSEL_MASK                                                    0x00020000L
+//DC_GPIO_TX12_EN
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT                                                      0x3
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT                                                      0x4
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT                                                      0x5
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT                                                      0x6
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT                                                      0x7
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT                                                      0x8
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT                                                      0x9
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK                                                        0x00000008L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK                                                        0x00000010L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK                                                        0x00000020L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK                                                        0x00000040L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK                                                        0x00000080L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK                                                        0x00000100L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK                                                        0x00000200L
+//DC_GPIO_AUX_CTRL_0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT                                                   0x0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT                                                   0x2
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT                                                   0x4
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT                                                   0x6
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT                                                   0x8
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT                                                   0xa
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT                                                 0xc
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT                                                     0x10
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT                                                     0x11
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT                                                     0x12
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT                                                     0x13
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT                                                     0x14
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT                                                     0x15
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT                                                   0x16
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT                                                    0x18
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT                                                    0x19
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT                                                    0x1a
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT                                                    0x1b
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT                                                    0x1c
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT                                                    0x1d
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT                                                  0x1e
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK                                                     0x00000003L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK                                                     0x0000000CL
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK                                                     0x00000030L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK                                                     0x000000C0L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK                                                     0x00000300L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK                                                     0x00000C00L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK                                                   0x00003000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK                                                       0x00010000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK                                                       0x00020000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK                                                       0x00040000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK                                                       0x00080000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK                                                       0x00100000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK                                                       0x00200000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK                                                     0x00C00000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK                                                      0x01000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK                                                      0x02000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK                                                      0x04000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK                                                      0x08000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK                                                      0x10000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK                                                      0x20000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK                                                    0xC0000000L
+//DC_GPIO_AUX_CTRL_1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT                                                       0x0
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT                                                       0x1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT                                                       0x2
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT                                                       0x3
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT                                                       0x4
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT                                                       0x5
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT                                                       0x6
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT                                                       0x7
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT                                                      0x8
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT                                                      0xa
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT                                                      0xb
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT                                                       0xd
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT                                                       0xe
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT                                                      0x10
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT                                                       0x12
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT                                                       0x14
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT                                                       0x19
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT                                                       0x1a
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT                                                       0x1b
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT                                                       0x1c
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT                                                       0x1d
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT                                                     0x1e
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK                                                         0x00000001L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK                                                         0x00000002L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK                                                         0x00000004L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK                                                         0x00000008L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK                                                         0x00000010L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK                                                         0x00000020L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK                                                         0x00000040L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK                                                         0x00000080L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK                                                        0x00000100L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK                                                        0x00000400L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK                                                        0x00001800L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK                                                         0x00002000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK                                                         0x0000C000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK                                                        0x00030000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK                                                         0x000C0000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK                                                         0x00300000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK                                                         0x02000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK                                                         0x04000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK                                                         0x08000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK                                                         0x10000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK                                                         0x20000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK                                                       0xC0000000L
+//DC_GPIO_AUX_CTRL_2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT                                                  0x0
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT                                                  0x2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT                                                  0x4
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT                                                    0x8
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT                                                    0x9
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT                                                    0xa
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT                                                   0xc
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT                                                   0xd
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT                                                   0xe
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT                                                       0x10
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT                                                       0x11
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT                                                       0x12
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT                                                       0x13
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT                                                      0x14
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT                                                        0x18
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT                                                        0x19
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT                                                        0x1a
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT                                                      0x1b
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT                                                      0x1c
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT                                                      0x1d
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT                                                      0x1e
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK                                                    0x00000003L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK                                                    0x0000000CL
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK                                                    0x00000030L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK                                                      0x00000100L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK                                                      0x00000200L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK                                                      0x00000400L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK                                                     0x00001000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK                                                     0x00002000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK                                                     0x00004000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK                                                         0x00010000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK                                                         0x00020000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK                                                         0x00040000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK                                                         0x00080000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK                                                        0x00100000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK                                                          0x01000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK                                                          0x02000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK                                                          0x04000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK                                                        0x08000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK                                                        0x10000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK                                                        0x20000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK                                                        0x40000000L
+//DC_GPIO_RXEN
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT                                                            0x0
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT                                                            0x1
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT                                                            0x2
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT                                                            0x3
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT                                                            0x4
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT                                                            0x5
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT                                                            0x6
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT                                                              0x8
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT                                                              0x9
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT                                                           0xa
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT                                                         0xb
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT                                                          0xc
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT                                                          0xd
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT                                                                0xe
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT                                                                0xf
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT                                                                0x10
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT                                                                0x11
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT                                                                0x12
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT                                                                0x13
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK                                                              0x00000001L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK                                                              0x00000002L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK                                                              0x00000004L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK                                                              0x00000008L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK                                                              0x00000010L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK                                                              0x00000020L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK                                                              0x00000040L
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK                                                                0x00000100L
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK                                                                0x00000200L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK                                                             0x00000400L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK                                                           0x00000800L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK                                                            0x00001000L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK                                                            0x00002000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK                                                                  0x00004000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK                                                                  0x00008000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK                                                                  0x00010000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK                                                                  0x00020000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK                                                                  0x00040000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK                                                                  0x00080000L
+//DC_GPIO_PULLUPEN
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT                                                       0x0
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT                                                       0x1
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT                                                       0x2
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT                                                       0x3
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT                                                       0x4
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT                                                       0x5
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT                                                       0x6
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT                                                         0x8
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT                                                         0x9
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT                                                           0xe
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT                                                           0xf
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT                                                           0x10
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT                                                           0x11
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT                                                           0x12
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT                                                           0x13
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK                                                         0x00000001L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK                                                         0x00000002L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK                                                         0x00000004L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK                                                         0x00000008L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK                                                         0x00000010L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK                                                         0x00000020L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK                                                         0x00000040L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK                                                           0x00000100L
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK                                                           0x00000200L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK                                                             0x00004000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK                                                             0x00008000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK                                                             0x00010000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK                                                             0x00020000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK                                                             0x00040000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK                                                             0x00080000L
+//DC_GPIO_AUX_CTRL_3
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT                                                             0x0
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT                                                             0x1
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT                                                             0x2
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT                                                             0x3
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT                                                             0x4
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT                                                             0x5
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT                                                            0x8
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT                                                            0x9
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT                                                            0xa
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT                                                            0xb
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT                                                            0xc
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT                                                            0xd
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT                                                              0x10
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT                                                              0x12
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT                                                              0x14
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT                                                              0x16
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT                                                              0x18
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT                                                              0x1a
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK                                                               0x00000001L
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK                                                               0x00000002L
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK                                                               0x00000004L
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK                                                               0x00000008L
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK                                                               0x00000010L
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK                                                               0x00000020L
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK                                                              0x00000100L
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK                                                              0x00000200L
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK                                                              0x00000400L
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK                                                              0x00000800L
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK                                                              0x00001000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK                                                              0x00002000L
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK                                                                0x00030000L
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK                                                                0x000C0000L
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK                                                                0x00300000L
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK                                                                0x00C00000L
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK                                                                0x03000000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK                                                                0x0C000000L
+//DC_GPIO_AUX_CTRL_4
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT                                                              0x0
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT                                                              0x4
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT                                                              0x8
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT                                                              0xc
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT                                                              0x10
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT                                                              0x14
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK                                                                0x0000000FL
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK                                                                0x000000F0L
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK                                                                0x00000F00L
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK                                                                0x0000F000L
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK                                                                0x000F0000L
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK                                                                0x00F00000L
+//DC_GPIO_AUX_CTRL_5
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT                                                              0x0
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT                                                              0x2
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT                                                              0x4
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT                                                              0x6
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT                                                              0x8
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT                                                              0xa
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT                                                           0xc
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT                                                           0xd
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT                                                           0xe
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT                                                           0xf
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT                                                           0x10
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT                                                           0x11
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT                                                        0x12
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT                                                        0x13
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT                                                        0x14
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT                                                        0x15
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT                                                        0x16
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT                                                        0x17
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT                                                          0x18
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT                                                          0x19
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT                                                          0x1a
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT                                                          0x1b
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT                                                          0x1c
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT                                                          0x1d
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK                                                                0x00000003L
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK                                                                0x0000000CL
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK                                                                0x00000030L
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK                                                                0x000000C0L
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK                                                                0x00000300L
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK                                                                0x00000C00L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK                                                             0x00001000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK                                                             0x00002000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK                                                             0x00004000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK                                                             0x00008000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK                                                             0x00010000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK                                                             0x00020000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK                                                          0x00040000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK                                                          0x00080000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK                                                          0x00100000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK                                                          0x00200000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK                                                          0x00400000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK                                                          0x00800000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK                                                            0x01000000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK                                                            0x02000000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK                                                            0x04000000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK                                                            0x08000000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK                                                            0x10000000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK                                                            0x20000000L
+//AUXI2C_PAD_ALL_PWR_OK
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT                                                  0x0
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT                                                  0x1
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT                                                  0x2
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT                                                  0x3
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT                                                  0x4
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT                                                  0x5
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK                                                    0x00000001L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK                                                    0x00000002L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK                                                    0x00000004L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK                                                    0x00000008L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK                                                    0x00000010L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK                                                    0x00000020L
+
+
+// addressBlock: dcn_dc_dcio_dcio_uniphy0_dispdec
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dcio_dcio_uniphy1_dispdec
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dcio_dcio_uniphy2_dispdec
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dcio_dcio_uniphy3_dispdec
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dcio_dcio_uniphy4_dispdec
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_pwrseq0_dispdec_pwrseq_dispdec
+//DC_GPIO_PWRSEQ_EN
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT                                                          0x0
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT                                                            0x8
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT                                                             0x10
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK                                                            0x00000001L
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK                                                              0x00000100L
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK                                                               0x00010000L
+//DC_GPIO_PWRSEQ_CTRL
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TXIMPSEL__SHIFT                                                  0x0
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TXIMPSEL__SHIFT                                                    0x1
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TXIMPSEL__SHIFT                                                     0x2
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT                                                      0x3
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT                                                        0x4
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT                                                         0x5
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT                                                     0x6
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT                                                       0x7
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT                                                        0x8
+#define DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_S0__SHIFT                                                        0x10
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_S1__SHIFT                                                        0x14
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_S1__SHIFT                                                          0x15
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_S1__SHIFT                                                           0x16
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TXIMPSEL_MASK                                                    0x00000001L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TXIMPSEL_MASK                                                      0x00000002L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TXIMPSEL_MASK                                                       0x00000004L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK                                                        0x00000008L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK                                                          0x00000010L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK                                                           0x00000020L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK                                                       0x00000040L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK                                                         0x00000080L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK                                                          0x00000100L
+#define DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_S0_MASK                                                          0x00010000L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_S1_MASK                                                          0x00100000L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_S1_MASK                                                            0x00200000L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_S1_MASK                                                             0x00400000L
+//DC_GPIO_PWRSEQ_MASK
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT                                                      0x0
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT                                                    0x4
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT                                                      0x6
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                        0x8
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                                      0xc
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                        0xe
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT                                                         0x10
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                                       0x14
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT                                                         0x16
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK                                                        0x00000001L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK                                                      0x00000010L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK                                                        0x000000C0L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK                                                          0x00000100L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                        0x00001000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK                                                          0x0000C000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK                                                           0x00010000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                         0x00100000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK                                                           0x00C00000L
+//DC_GPIO_PWRSEQ_A_Y
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT                                                          0x0
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT                                                          0x1
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT                                                            0x8
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT                                                            0x9
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT                                                             0x10
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT                                                             0x11
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK                                                            0x00000001L
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK                                                            0x00000002L
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK                                                              0x00000100L
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK                                                              0x00000200L
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK                                                               0x00010000L
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK                                                               0x00020000L
+//PANEL_PWRSEQ_CNTL
+#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT                                                             0x0
+#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT                                                   0x4
+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT                                                                0x8
+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT                                                           0x9
+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT                                                            0xa
+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT                                                                 0x10
+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT                                                            0x11
+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT                                                             0x12
+#define PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT                                                                  0x18
+#define PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT                                                             0x19
+#define PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT                                                              0x1a
+#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK                                                               0x00000001L
+#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK                                                     0x00000010L
+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK                                                                  0x00000100L
+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK                                                             0x00000200L
+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK                                                              0x00000400L
+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK                                                                   0x00010000L
+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK                                                              0x00020000L
+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK                                                               0x00040000L
+#define PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK                                                                    0x01000000L
+#define PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK                                                               0x02000000L
+#define PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK                                                                0x04000000L
+//PANEL_PWRSEQ_STATE
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT                                                0x0
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT                                                         0x1
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT                                                        0x2
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT                                                          0x3
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT                                                          0x4
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT                                                         0x8
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK                                                  0x00000001L
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK                                                           0x00000002L
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK                                                          0x00000004L
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK                                                            0x00000008L
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK                                                            0x00000010L
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK                                                           0x00000F00L
+//PANEL_PWRSEQ_DELAY1
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT                                                        0x0
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT                                                        0x8
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT                                                        0x10
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT                                                        0x18
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK                                                          0x000000FFL
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK                                                          0x0000FF00L
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK                                                          0x00FF0000L
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK                                                          0xFF000000L
+//PANEL_PWRSEQ_DELAY2
+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT                                                    0x0
+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT                                                        0x8
+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT                                                        0x10
+#define PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT                                                 0x18
+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK                                                      0x000000FFL
+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK                                                          0x0000FF00L
+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK                                                          0x00FF0000L
+#define PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK                                                   0x01000000L
+//PANEL_PWRSEQ_REF_DIV1
+#define PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT                                                    0x0
+#define PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT                                                          0x10
+#define PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK                                                      0x00000FFFL
+#define PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK                                                            0xFFFF0000L
+//BL_PWM_CNTL
+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                            0x0
+#define BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT                                                                 0x13
+#define BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT                                                      0x14
+#define BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                                    0x15
+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                              0x1e
+#define BL_PWM_CNTL__BL_PWM_EN__SHIFT                                                                         0x1f
+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                              0x0000FFFFL
+#define BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK                                                                   0x00080000L
+#define BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK                                                        0x00100000L
+#define BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                      0x00200000L
+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                                0x40000000L
+#define BL_PWM_CNTL__BL_PWM_EN_MASK                                                                           0x80000000L
+//BL_PWM_CNTL2
+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                                      0x0
+#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT                                                   0x1c
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                                    0x1e
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT                                                  0x1f
+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                        0x0000FFFFL
+#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK                                                     0x30000000L
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                                      0x40000000L
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK                                                    0x80000000L
+//BL_PWM_PERIOD_CNTL
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                              0x0
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                                       0x10
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                                0x0000FFFFL
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                         0x000F0000L
+//BL_PWM_GRP1_REG_LOCK
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                                     0x0
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                           0x8
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                        0x10
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                                     0x18
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                        0x1f
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                                       0x00000001L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                             0x00000100L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                          0x00010000L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                                       0x01000000L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                          0x80000000L
+//PANEL_PWRSEQ_REF_DIV2
+#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT                                                            0x0
+#define PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT                                               0x8
+#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT                                        0x10
+#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK                                                              0x0000007FL
+#define PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK                                                 0x00007F00L
+#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK                                          0x00010000L
+//PWRSEQ_SPARE
+#define PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT                                                                     0x0
+#define PWRSEQ_SPARE__PWRSEQ_SPARE_MASK                                                                       0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dsc0_dispdec_dscc_dispdec
+//DSCC0_DSCC_CONFIG0
+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC0_DSCC_CONFIG1
+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
+//DSCC0_DSCC_STATUS
+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC0_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                    0xc
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT             0x1c
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                      0x00001000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK               0x10000000L
+//DSCC0_DSCC_PPS_CONFIG0
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC0_DSCC_PPS_CONFIG1
+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG2
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG3
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG4
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG5
+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG6
+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC0_DSCC_PPS_CONFIG7
+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG8
+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG9
+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG10
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG11
+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC0_DSCC_PPS_CONFIG12
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG13
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG14
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG15
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG16
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG17
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG18
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG19
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG20
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG21
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG22
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC0_DSCC_MEM_POWER_CONTROL
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_MAX_ABS_ERROR0
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC0_DSCC_MAX_ABS_ERROR1
+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+
+
+// addressBlock: dcn_dc_dsc0_dispdec_dsccif_dispdec
+//DSCCIF0_DSCCIF_CONFIG0
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF0_DSCCIF_CONFIG1
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dsc0_dispdec_dsc_top_dispdec
+//DSC_TOP0_DSC_TOP_CONTROL
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+//DSC_TOP0_DSC_DEBUG_CONTROL
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
+
+
+// addressBlock: dcn_dc_dsc1_dispdec_dscc_dispdec
+//DSCC1_DSCC_CONFIG0
+#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC1_DSCC_CONFIG1
+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
+//DSCC1_DSCC_STATUS
+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC1_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                    0xc
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT             0x1c
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                      0x00001000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK               0x10000000L
+//DSCC1_DSCC_PPS_CONFIG0
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC1_DSCC_PPS_CONFIG1
+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG2
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG3
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG4
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG5
+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG6
+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC1_DSCC_PPS_CONFIG7
+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG8
+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG9
+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG10
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG11
+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC1_DSCC_PPS_CONFIG12
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG13
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG14
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG15
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG16
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG17
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG18
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG19
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG20
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG21
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG22
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC1_DSCC_MEM_POWER_CONTROL
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_MAX_ABS_ERROR0
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC1_DSCC_MAX_ABS_ERROR1
+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+
+
+// addressBlock: dcn_dc_dsc1_dispdec_dsccif_dispdec
+//DSCCIF1_DSCCIF_CONFIG0
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF1_DSCCIF_CONFIG1
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dsc1_dispdec_dsc_top_dispdec
+//DSC_TOP1_DSC_TOP_CONTROL
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+
+
+// addressBlock: dcn_dc_dsc2_dispdec_dscc_dispdec
+//DSCC2_DSCC_CONFIG0
+#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC2_DSCC_CONFIG1
+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
+//DSCC2_DSCC_STATUS
+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC2_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                    0xc
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT             0x1c
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                      0x00001000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK               0x10000000L
+//DSCC2_DSCC_PPS_CONFIG0
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC2_DSCC_PPS_CONFIG1
+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG2
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG3
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG4
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG5
+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG6
+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC2_DSCC_PPS_CONFIG7
+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG8
+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG9
+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG10
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG11
+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC2_DSCC_PPS_CONFIG12
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC2_DSCC_PPS_CONFIG13
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC2_DSCC_PPS_CONFIG14
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC2_DSCC_PPS_CONFIG15
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG16
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG17
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG18
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG19
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG20
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG21
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG22
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC2_DSCC_MEM_POWER_CONTROL
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_MAX_ABS_ERROR0
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC2_DSCC_MAX_ABS_ERROR1
+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+
+
+// addressBlock: dcn_dc_dsc2_dispdec_dsccif_dispdec
+//DSCCIF2_DSCCIF_CONFIG0
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF2_DSCCIF_CONFIG1
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dsc2_dispdec_dsc_top_dispdec
+//DSC_TOP2_DSC_TOP_CONTROL
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+
+
+// addressBlock: dcn_dc_dsc3_dispdec_dscc_dispdec
+//DSCC3_DSCC_CONFIG0
+#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC3_DSCC_CONFIG1
+#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
+#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
+//DSCC3_DSCC_STATUS
+#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC3_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                    0xc
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT             0x1c
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                      0x00001000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK               0x10000000L
+//DSCC3_DSCC_PPS_CONFIG0
+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC3_DSCC_PPS_CONFIG1
+#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG2
+#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG3
+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG4
+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG5
+#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG6
+#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC3_DSCC_PPS_CONFIG7
+#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG8
+#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG9
+#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG10
+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG11
+#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC3_DSCC_PPS_CONFIG12
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC3_DSCC_PPS_CONFIG13
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC3_DSCC_PPS_CONFIG14
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC3_DSCC_PPS_CONFIG15
+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG16
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG17
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG18
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG19
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG20
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG21
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG22
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC3_DSCC_MEM_POWER_CONTROL
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC3_DSCC_MAX_ABS_ERROR0
+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC3_DSCC_MAX_ABS_ERROR1
+#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+
+
+// addressBlock: dcn_dc_dsc3_dispdec_dsccif_dispdec
+//DSCCIF3_DSCCIF_CONFIG0
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF3_DSCCIF_CONFIG1
+#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dsc3_dispdec_dsc_top_dispdec
+//DSC_TOP3_DSC_TOP_CONTROL
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+
+
+// addressBlock: dcn_dc_hpo_hpo_top_dispdec
+//HPO_TOP_CLOCK_CONTROL
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT                                                  0x0
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS__SHIFT                                                    0x1
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS__SHIFT                                                     0x5
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS__SHIFT                                            0x8
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS__SHIFT                                            0x9
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS__SHIFT                                              0xc
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS__SHIFT                                              0xd
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS__SHIFT                                              0x10
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS__SHIFT                                              0x11
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS__SHIFT                                              0x12
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS__SHIFT                                              0x13
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS__SHIFT                                              0x14
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS__SHIFT                                              0x15
+#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL__SHIFT                                                        0x18
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS_MASK                                                    0x00000001L
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS_MASK                                                      0x00000002L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS_MASK                                                       0x00000020L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS_MASK                                              0x00000100L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS_MASK                                              0x00000200L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS_MASK                                                0x00001000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS_MASK                                                0x00002000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS_MASK                                                0x00010000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS_MASK                                                0x00020000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS_MASK                                                0x00040000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS_MASK                                                0x00080000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS_MASK                                                0x00100000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS_MASK                                                0x00200000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL_MASK                                                          0xFF000000L
+//HPO_TOP_HW_CONTROL
+#define HPO_TOP_HW_CONTROL__HPO_IO_EN__SHIFT                                                                  0x0
+#define HPO_TOP_HW_CONTROL__HPO_IO_EN_MASK                                                                    0x00000001L
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_mapper_dispdec
+//DP_STREAM_MAPPER_CONTROL0
+#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET__SHIFT                                               0x0
+#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L
+//DP_STREAM_MAPPER_CONTROL1
+#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET__SHIFT                                               0x0
+#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L
+//DP_STREAM_MAPPER_CONTROL2
+#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET__SHIFT                                               0x0
+#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L
+//DP_STREAM_MAPPER_CONTROL3
+#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET__SHIFT                                               0x0
+#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L
+
+
+// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec
+//AFMT5_AFMT_VBI_PACKET_CONTROL
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT5_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT5_AFMT_AUDIO_INFO0
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT5_AFMT_AUDIO_INFO1
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT5_AFMT_60958_0
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT5_AFMT_60958_1
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT5_AFMT_AUDIO_CRC_CONTROL
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT5_AFMT_RAMP_CONTROL0
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT5_AFMT_RAMP_CONTROL1
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT5_AFMT_RAMP_CONTROL2
+#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT5_AFMT_RAMP_CONTROL3
+#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT5_AFMT_60958_2
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT5_AFMT_AUDIO_CRC_RESULT
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT5_AFMT_STATUS
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT5_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L
+//AFMT5_AFMT_INFOFRAME_CONTROL0
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT5_AFMT_INTERRUPT_STATUS
+//AFMT5_AFMT_AUDIO_SRC_CONTROL
+#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT5_AFMT_MEM_PWR
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec
+//DME5_DME_CONTROL
+#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME5_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME5_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME5_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME5_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME5_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME5_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME5_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME5_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME5_DME_MEMORY_CONTROL
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec
+//VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG5_VPG_GENERIC_PACKET_DATA
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG5_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG5_VPG_GENERIC_STATUS
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG5_VPG_MEM_PWR
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG5_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG5_VPG_ISRC1_2_DATA
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG5_VPG_MPEG_INFO0
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG5_VPG_MPEG_INFO1
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc0_dispdec
+//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L
+//DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL
+#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L
+//DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL
+#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L
+//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L
+//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L
+//DP_STREAM_ENC0_DP_STREAM_ENC_SPARE
+#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc0_apg_apg_dispdec
+//APG0_APG_CONTROL
+#define APG0_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1
+#define APG0_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2
+#define APG0_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L
+#define APG0_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L
+//APG0_APG_CONTROL2
+#define APG0_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0
+#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8
+#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18
+#define APG0_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L
+#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L
+#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L
+//APG0_APG_DBG_GEN_CONTROL
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L
+//APG0_APG_PACKET_CONTROL
+#define APG0_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT                                                       0x0
+#define APG0_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1
+#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2
+#define APG0_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK                                                         0x00000001L
+#define APG0_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L
+#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L
+//APG0_APG_AUDIO_CRC_CONTROL
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L
+//APG0_APG_AUDIO_CRC_CONTROL2
+#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0
+#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL
+//APG0_APG_AUDIO_CRC_RESULT
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L
+//APG0_APG_STATUS
+#define APG0_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4
+#define APG0_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19
+#define APG0_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L
+#define APG0_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L
+//APG0_APG_STATUS2
+#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0
+#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L
+//APG0_APG_MEM_PWR
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8
+#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L
+#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L
+//APG0_APG_SPARE
+#define APG0_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0
+#define APG0_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc0_dme_dme_dispdec
+//DME6_DME_CONTROL
+#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME6_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME6_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME6_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME6_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME6_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME6_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME6_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME6_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME6_DME_MEMORY_CONTROL
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec
+//VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG6_VPG_GENERIC_PACKET_DATA
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG6_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG6_VPG_GENERIC_STATUS
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG6_VPG_MEM_PWR
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG6_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG6_VPG_ISRC1_2_DATA
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG6_VPG_MPEG_INFO0
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG6_VPG_MPEG_INFO1
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dcn_dc_hpo_dp_sym32_enc0_dispdec
+//DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L
+//DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SPARE
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc1_dispdec
+//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L
+//DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL
+#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L
+//DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL
+#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L
+//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L
+//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L
+//DP_STREAM_ENC1_DP_STREAM_ENC_SPARE
+#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc1_apg_apg_dispdec
+//APG1_APG_CONTROL
+#define APG1_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1
+#define APG1_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2
+#define APG1_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L
+#define APG1_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L
+//APG1_APG_CONTROL2
+#define APG1_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0
+#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8
+#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18
+#define APG1_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L
+#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L
+#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L
+//APG1_APG_DBG_GEN_CONTROL
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L
+//APG1_APG_PACKET_CONTROL
+#define APG1_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT                                                       0x0
+#define APG1_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1
+#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2
+#define APG1_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK                                                         0x00000001L
+#define APG1_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L
+#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L
+//APG1_APG_AUDIO_CRC_CONTROL
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L
+//APG1_APG_AUDIO_CRC_CONTROL2
+#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0
+#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL
+//APG1_APG_AUDIO_CRC_RESULT
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L
+//APG1_APG_STATUS
+#define APG1_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4
+#define APG1_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19
+#define APG1_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L
+#define APG1_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L
+//APG1_APG_STATUS2
+#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0
+#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L
+//APG1_APG_MEM_PWR
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8
+#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L
+#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L
+//APG1_APG_SPARE
+#define APG1_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0
+#define APG1_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc1_dme_dme_dispdec
+//DME7_DME_CONTROL
+#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME7_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME7_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME7_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME7_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME7_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME7_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME7_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME7_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME7_DME_MEMORY_CONTROL
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec
+//VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG7_VPG_GENERIC_PACKET_DATA
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG7_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG7_VPG_GENERIC_STATUS
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG7_VPG_MEM_PWR
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG7_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG7_VPG_ISRC1_2_DATA
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG7_VPG_MPEG_INFO0
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG7_VPG_MPEG_INFO1
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dcn_dc_hpo_dp_sym32_enc1_dispdec
+//DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L
+//DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SPARE
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc2_dispdec
+//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L
+//DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL
+#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L
+//DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL
+#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L
+//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L
+//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L
+//DP_STREAM_ENC2_DP_STREAM_ENC_SPARE
+#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc2_apg_apg_dispdec
+//APG2_APG_CONTROL
+#define APG2_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1
+#define APG2_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2
+#define APG2_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L
+#define APG2_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L
+//APG2_APG_CONTROL2
+#define APG2_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0
+#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8
+#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18
+#define APG2_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L
+#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L
+#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L
+//APG2_APG_DBG_GEN_CONTROL
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L
+//APG2_APG_PACKET_CONTROL
+#define APG2_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT                                                       0x0
+#define APG2_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1
+#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2
+#define APG2_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK                                                         0x00000001L
+#define APG2_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L
+#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L
+//APG2_APG_AUDIO_CRC_CONTROL
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L
+//APG2_APG_AUDIO_CRC_CONTROL2
+#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0
+#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL
+//APG2_APG_AUDIO_CRC_RESULT
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L
+//APG2_APG_STATUS
+#define APG2_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4
+#define APG2_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19
+#define APG2_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L
+#define APG2_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L
+//APG2_APG_STATUS2
+#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0
+#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L
+//APG2_APG_MEM_PWR
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8
+#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L
+#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L
+//APG2_APG_SPARE
+#define APG2_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0
+#define APG2_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc2_dme_dme_dispdec
+//DME8_DME_CONTROL
+#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME8_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME8_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME8_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME8_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME8_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME8_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME8_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME8_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME8_DME_MEMORY_CONTROL
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec
+//VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG8_VPG_GENERIC_PACKET_DATA
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG8_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG8_VPG_GENERIC_STATUS
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG8_VPG_MEM_PWR
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG8_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG8_VPG_ISRC1_2_DATA
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG8_VPG_MPEG_INFO0
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG8_VPG_MPEG_INFO1
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dcn_dc_hpo_dp_sym32_enc2_dispdec
+//DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L
+//DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SPARE
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc3_dispdec
+//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L
+//DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL
+#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L
+//DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL
+#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L
+//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L
+//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L
+//DP_STREAM_ENC3_DP_STREAM_ENC_SPARE
+#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc3_apg_apg_dispdec
+//APG3_APG_CONTROL
+#define APG3_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1
+#define APG3_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2
+#define APG3_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L
+#define APG3_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L
+//APG3_APG_CONTROL2
+#define APG3_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0
+#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8
+#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18
+#define APG3_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L
+#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L
+#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L
+//APG3_APG_DBG_GEN_CONTROL
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L
+//APG3_APG_PACKET_CONTROL
+#define APG3_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT                                                       0x0
+#define APG3_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1
+#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2
+#define APG3_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK                                                         0x00000001L
+#define APG3_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L
+#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L
+//APG3_APG_AUDIO_CRC_CONTROL
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L
+//APG3_APG_AUDIO_CRC_CONTROL2
+#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0
+#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL
+//APG3_APG_AUDIO_CRC_RESULT
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L
+//APG3_APG_STATUS
+#define APG3_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4
+#define APG3_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19
+#define APG3_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L
+#define APG3_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L
+//APG3_APG_STATUS2
+#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0
+#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L
+//APG3_APG_MEM_PWR
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8
+#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L
+#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L
+//APG3_APG_SPARE
+#define APG3_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0
+#define APG3_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc3_dme_dme_dispdec
+//DME9_DME_CONTROL
+#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME9_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME9_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME9_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME9_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME9_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME9_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME9_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME9_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME9_DME_MEMORY_CONTROL
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec
+//VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG9_VPG_GENERIC_PACKET_DATA
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG9_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG9_VPG_GENERIC_STATUS
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG9_VPG_MEM_PWR
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG9_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG9_VPG_ISRC1_2_DATA
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG9_VPG_MPEG_INFO0
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG9_VPG_MPEG_INFO1
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dcn_dc_hpo_dp_sym32_enc3_dispdec
+//DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L
+//DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SPARE
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_link_enc0_dispdec
+//DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT                                   0x0
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT                          0x4
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK                                     0x00000001L
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK                            0x00000010L
+//DP_LINK_ENC0_DP_LINK_ENC_SPARE
+#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT                                              0x0
+#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK                                                0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_dphy_sym320_dispdec
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT                                              0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT                                               0x1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT                                          0x2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE__SHIFT                                                     0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT                                                0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK                                                0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK                                                 0x00000002L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK                                            0x00000004L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE_MASK                                                       0x00000030L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK                                                  0x00000300L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS__SHIFT                                                    0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT                                              0x1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT                                              0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT                                       0xc
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT                                        0x10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS_MASK                                                      0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK                                                0x00000002L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK                                                0x00000030L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK                                         0x00001000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK                                          0x00030000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT                                            0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK                                              0x00000003L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT                                           0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT                                             0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT                                           0xc
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT                                             0x10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT                                           0x14
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT                                             0x18
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT                                           0x1c
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK                                               0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK                                             0x00000070L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK                                               0x00000700L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK                                             0x00007000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK                                               0x00070000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK                                             0x00700000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK                                               0x07000000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK                                             0x70000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT                                    0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK                                      0x000000FFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT                                            0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK                                              0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT                              0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT                                          0x1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT                               0x2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT                                        0x3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT                            0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT                               0x5
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT                             0x6
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT                                    0x7
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT                                        0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK                                0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK                                            0x00000002L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK                                 0x00000004L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK                                          0x00000008L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK                              0x00000010L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK                                 0x00000020L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK                               0x00000040L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK                                      0x00000080L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK                                          0x00000100L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE__SHIFT                               0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE__SHIFT                                 0x2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL__SHIFT                               0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE__SHIFT                               0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE__SHIFT                                 0xa
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL__SHIFT                               0xc
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE__SHIFT                               0x10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE__SHIFT                                 0x12
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL__SHIFT                               0x14
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE__SHIFT                               0x18
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE__SHIFT                                 0x1a
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL__SHIFT                               0x1c
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE_MASK                                 0x00000003L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE_MASK                                   0x00000004L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL_MASK                                 0x000000F0L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE_MASK                                 0x00000300L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE_MASK                                   0x00000400L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL_MASK                                 0x0000F000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE_MASK                                 0x00030000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE_MASK                                   0x00040000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL_MASK                                 0x00F00000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE_MASK                                 0x03000000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE_MASK                                   0x04000000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL_MASK                                 0xF0000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE__SHIFT                                           0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET__SHIFT                                            0x1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE__SHIFT                                      0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE__SHIFT                                       0x6
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE__SHIFT                                 0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF__SHIFT                                      0x10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT__SHIFT                                      0x11
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS__SHIFT                                  0x14
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT__SHIFT                                        0x15
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE_MASK                                             0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET_MASK                                              0x00000002L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE_MASK                                        0x00000030L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE_MASK                                         0x000000C0L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE_MASK                                   0x00003F00L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF_MASK                                        0x00010000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT_MASK                                        0x000E0000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS_MASK                                    0x00100000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT_MASK                                          0x00600000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS__SHIFT                                      0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS_MASK                                        0xFFFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE__SHIFT                                              0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE__SHIFT                                             0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE_MASK                                                0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE_MASK                                               0x00FFFF00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT_MASK                                         0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_link_enc1_dispdec
+//DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT                                   0x0
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT                          0x4
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK                                     0x00000001L
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK                            0x00000010L
+//DP_LINK_ENC1_DP_LINK_ENC_SPARE
+#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT                                              0x0
+#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK                                                0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_dphy_sym321_dispdec
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT                                              0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT                                               0x1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT                                          0x2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE__SHIFT                                                     0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT                                                0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK                                                0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK                                                 0x00000002L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK                                            0x00000004L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE_MASK                                                       0x00000030L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK                                                  0x00000300L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS__SHIFT                                                    0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT                                              0x1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT                                              0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT                                       0xc
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT                                        0x10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS_MASK                                                      0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK                                                0x00000002L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK                                                0x00000030L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK                                         0x00001000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK                                          0x00030000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT                                            0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK                                              0x00000003L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT                                           0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT                                             0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT                                           0xc
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT                                             0x10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT                                           0x14
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT                                             0x18
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT                                           0x1c
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK                                               0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK                                             0x00000070L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK                                               0x00000700L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK                                             0x00007000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK                                               0x00070000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK                                             0x00700000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK                                               0x07000000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK                                             0x70000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT                                    0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK                                      0x000000FFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT                                            0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK                                              0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT                              0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT                                          0x1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT                               0x2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT                                        0x3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT                            0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT                               0x5
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT                             0x6
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT                                    0x7
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT                                        0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK                                0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK                                            0x00000002L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK                                 0x00000004L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK                                          0x00000008L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK                              0x00000010L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK                                 0x00000020L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK                               0x00000040L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK                                      0x00000080L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK                                          0x00000100L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE__SHIFT                               0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE__SHIFT                                 0x2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL__SHIFT                               0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE__SHIFT                               0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE__SHIFT                                 0xa
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL__SHIFT                               0xc
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE__SHIFT                               0x10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE__SHIFT                                 0x12
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL__SHIFT                               0x14
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE__SHIFT                               0x18
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE__SHIFT                                 0x1a
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL__SHIFT                               0x1c
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE_MASK                                 0x00000003L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE_MASK                                   0x00000004L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL_MASK                                 0x000000F0L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE_MASK                                 0x00000300L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE_MASK                                   0x00000400L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL_MASK                                 0x0000F000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE_MASK                                 0x00030000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE_MASK                                   0x00040000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL_MASK                                 0x00F00000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE_MASK                                 0x03000000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE_MASK                                   0x04000000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL_MASK                                 0xF0000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE__SHIFT                                           0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET__SHIFT                                            0x1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE__SHIFT                                      0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE__SHIFT                                       0x6
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE__SHIFT                                 0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF__SHIFT                                      0x10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT__SHIFT                                      0x11
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS__SHIFT                                  0x14
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT__SHIFT                                        0x15
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE_MASK                                             0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET_MASK                                              0x00000002L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE_MASK                                        0x00000030L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE_MASK                                         0x000000C0L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE_MASK                                   0x00003F00L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF_MASK                                        0x00010000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT_MASK                                        0x000E0000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS_MASK                                    0x00100000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT_MASK                                          0x00600000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS__SHIFT                                      0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS_MASK                                        0xFFFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE__SHIFT                                              0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE__SHIFT                                             0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE_MASK                                                0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE_MASK                                               0x00FFFF00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT_MASK                                         0xFFFFFFFFL
+
+
+// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe0_dispdec
+//RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6
+#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                            0x10
+#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                        0x11
+#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                    0x12
+#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                              0x00010000L
+#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                          0x00020000L
+#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                      0x00040000L
+
+
+// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe1_dispdec
+//RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6
+#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                            0x10
+#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                        0x11
+#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                    0x12
+#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                              0x00010000L
+#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                          0x00020000L
+#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                      0x00040000L
+
+
+// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe2_dispdec
+//RDPCSPIPE2_RDPCSPIPE_PHY_CNTL6
+#define RDPCSPIPE2_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                            0x10
+#define RDPCSPIPE2_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                        0x11
+#define RDPCSPIPE2_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                    0x12
+#define RDPCSPIPE2_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                              0x00010000L
+#define RDPCSPIPE2_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                          0x00020000L
+#define RDPCSPIPE2_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                      0x00040000L
+
+
+// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe3_dispdec
+//RDPCSPIPE3_RDPCSPIPE_PHY_CNTL6
+#define RDPCSPIPE3_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                            0x10
+#define RDPCSPIPE3_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                        0x11
+#define RDPCSPIPE3_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                    0x12
+#define RDPCSPIPE3_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                              0x00010000L
+#define RDPCSPIPE3_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                          0x00020000L
+#define RDPCSPIPE3_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                      0x00040000L
+
+
+// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe4_dispdec
+//RDPCSPIPE4_RDPCSPIPE_PHY_CNTL6
+#define RDPCSPIPE4_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                            0x10
+#define RDPCSPIPE4_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                        0x11
+#define RDPCSPIPE4_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                    0x12
+#define RDPCSPIPE4_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                              0x00010000L
+#define RDPCSPIPE4_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                          0x00020000L
+#define RDPCSPIPE4_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                      0x00040000L
+
+
+// addressBlock: dcn_dc_hda_azcontroller_azdec
+//CORB_WRITE_POINTER
+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT                                                         0x0
+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK                                                           0x00FFL
+//CORB_READ_POINTER
+#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT                                                           0x0
+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT                                                     0xf
+#define CORB_READ_POINTER__CORB_READ_POINTER_MASK                                                             0x00FFL
+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK                                                       0x8000L
+//CORB_CONTROL
+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT                                               0x0
+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT                                                           0x1
+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK                                                 0x01L
+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK                                                             0x02L
+//CORB_STATUS
+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT                                                      0x0
+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK                                                        0x01L
+//CORB_SIZE
+#define CORB_SIZE__CORB_SIZE__SHIFT                                                                           0x0
+#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT                                                                0x4
+#define CORB_SIZE__CORB_SIZE_MASK                                                                             0x0003L
+#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK                                                                  0x00F0L
+//RIRB_LOWER_BASE_ADDRESS
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                                    0x0
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT                                               0x7
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                                      0x0000007FL
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK                                                 0xFFFFFF80L
+//RIRB_UPPER_BASE_ADDRESS
+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT                                               0x0
+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK                                                 0xFFFFFFFFL
+//RIRB_WRITE_POINTER
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT                                                         0x0
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT                                                   0xf
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK                                                           0x00FFL
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK                                                     0x8000L
+//RESPONSE_INTERRUPT_COUNT
+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT                                           0x0
+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK                                             0x00FFL
+//RIRB_CONTROL
+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT                                                       0x0
+#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT                                                                  0x1
+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT                                               0x2
+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK                                                         0x01L
+#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK                                                                    0x02L
+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK                                                 0x04L
+//RIRB_STATUS
+#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT                                                                0x0
+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT                                                 0x2
+#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK                                                                  0x01L
+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK                                                   0x04L
+//RIRB_SIZE
+#define RIRB_SIZE__RIRB_SIZE__SHIFT                                                                           0x0
+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT                                                                0x4
+#define RIRB_SIZE__RIRB_SIZE_MASK                                                                             0x0003L
+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK                                                                  0x00F0L
+//IMMEDIATE_COMMAND_OUTPUT_INTERFACE
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT                   0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT                      0x1c
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK                     0x0FFFFFFFL
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK                        0xF0000000L
+//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                               0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                                 0xFFFFFFFFL
+//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                              0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                                0x0000FFFFL
+//IMMEDIATE_RESPONSE_INPUT_INTERFACE
+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT                                    0x0
+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK                                      0xFFFFFFFFL
+//IMMEDIATE_COMMAND_STATUS
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT                                               0x0
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT                                               0x1
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK                                                 0x00000001L
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK                                                 0x00000002L
+//DMA_POSITION_LOWER_BASE_ADDRESS
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT                                    0x0
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                    0x1
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT                               0x7
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK                                      0x00000001L
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                      0x0000007EL
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK                                 0xFFFFFF80L
+//DMA_POSITION_UPPER_BASE_ADDRESS
+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT                               0x0
+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK                                 0xFFFFFFFFL
+//WALL_CLOCK_COUNTER_ALIAS
+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT                                             0x0
+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK                                               0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azendpoint_azdec
+//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                    0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                      0xFFFFFFFFL
+//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                   0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                     0x0001FFFFL
+
+
+// addressBlock: dcn_dc_hda_azinputendpoint_azdec
+//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                     0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                       0xFFFFFFFFL
+//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                    0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                      0x0001FFFFL
+
+
+// addressBlock: dcn_dc_hda_azroot_azdec
+//AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                        0x0
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                          0xFFFFFFFFL
+//AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                       0x0
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                         0x0001FFFFL
+
+
+// addressBlock: dcn_dc_hda_azstream0_azdec
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azstream1_azdec
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azstream2_azdec
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azstream3_azdec
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azstream4_azdec
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azstream5_azdec
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azstream6_azdec
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azstream7_azdec
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: vga_vgaseqind
+//SEQ00
+#define SEQ00__SEQ_RST0B__SHIFT                                                                               0x0
+#define SEQ00__SEQ_RST1B__SHIFT                                                                               0x1
+#define SEQ00__SEQ_RST0B_MASK                                                                                 0x01L
+#define SEQ00__SEQ_RST1B_MASK                                                                                 0x02L
+//SEQ01
+#define SEQ01__SEQ_DOT8__SHIFT                                                                                0x0
+#define SEQ01__SEQ_SHIFT2__SHIFT                                                                              0x2
+#define SEQ01__SEQ_PCLKBY2__SHIFT                                                                             0x3
+#define SEQ01__SEQ_SHIFT4__SHIFT                                                                              0x4
+#define SEQ01__SEQ_MAXBW__SHIFT                                                                               0x5
+#define SEQ01__SEQ_DOT8_MASK                                                                                  0x01L
+#define SEQ01__SEQ_SHIFT2_MASK                                                                                0x04L
+#define SEQ01__SEQ_PCLKBY2_MASK                                                                               0x08L
+#define SEQ01__SEQ_SHIFT4_MASK                                                                                0x10L
+#define SEQ01__SEQ_MAXBW_MASK                                                                                 0x20L
+//SEQ02
+#define SEQ02__SEQ_MAP0_EN__SHIFT                                                                             0x0
+#define SEQ02__SEQ_MAP1_EN__SHIFT                                                                             0x1
+#define SEQ02__SEQ_MAP2_EN__SHIFT                                                                             0x2
+#define SEQ02__SEQ_MAP3_EN__SHIFT                                                                             0x3
+#define SEQ02__SEQ_MAP0_EN_MASK                                                                               0x01L
+#define SEQ02__SEQ_MAP1_EN_MASK                                                                               0x02L
+#define SEQ02__SEQ_MAP2_EN_MASK                                                                               0x04L
+#define SEQ02__SEQ_MAP3_EN_MASK                                                                               0x08L
+//SEQ03
+#define SEQ03__SEQ_FONT_B1__SHIFT                                                                             0x0
+#define SEQ03__SEQ_FONT_B2__SHIFT                                                                             0x1
+#define SEQ03__SEQ_FONT_A1__SHIFT                                                                             0x2
+#define SEQ03__SEQ_FONT_A2__SHIFT                                                                             0x3
+#define SEQ03__SEQ_FONT_B0__SHIFT                                                                             0x4
+#define SEQ03__SEQ_FONT_A0__SHIFT                                                                             0x5
+#define SEQ03__SEQ_FONT_B1_MASK                                                                               0x01L
+#define SEQ03__SEQ_FONT_B2_MASK                                                                               0x02L
+#define SEQ03__SEQ_FONT_A1_MASK                                                                               0x04L
+#define SEQ03__SEQ_FONT_A2_MASK                                                                               0x08L
+#define SEQ03__SEQ_FONT_B0_MASK                                                                               0x10L
+#define SEQ03__SEQ_FONT_A0_MASK                                                                               0x20L
+//SEQ04
+#define SEQ04__SEQ_256K__SHIFT                                                                                0x1
+#define SEQ04__SEQ_ODDEVEN__SHIFT                                                                             0x2
+#define SEQ04__SEQ_CHAIN__SHIFT                                                                               0x3
+#define SEQ04__SEQ_256K_MASK                                                                                  0x02L
+#define SEQ04__SEQ_ODDEVEN_MASK                                                                               0x04L
+#define SEQ04__SEQ_CHAIN_MASK                                                                                 0x08L
+
+
+// addressBlock: vga_vgacrtind
+//CRT00
+#define CRT00__H_TOTAL__SHIFT                                                                                 0x0
+#define CRT00__H_TOTAL_MASK                                                                                   0xFFL
+//CRT01
+#define CRT01__H_DISP_END__SHIFT                                                                              0x0
+#define CRT01__H_DISP_END_MASK                                                                                0xFFL
+//CRT02
+#define CRT02__H_BLANK_START__SHIFT                                                                           0x0
+#define CRT02__H_BLANK_START_MASK                                                                             0xFFL
+//CRT03
+#define CRT03__H_BLANK_END__SHIFT                                                                             0x0
+#define CRT03__H_DE_SKEW__SHIFT                                                                               0x5
+#define CRT03__CR10CR11_R_DIS_B__SHIFT                                                                        0x7
+#define CRT03__H_BLANK_END_MASK                                                                               0x1FL
+#define CRT03__H_DE_SKEW_MASK                                                                                 0x60L
+#define CRT03__CR10CR11_R_DIS_B_MASK                                                                          0x80L
+//CRT04
+#define CRT04__H_SYNC_START__SHIFT                                                                            0x0
+#define CRT04__H_SYNC_START_MASK                                                                              0xFFL
+//CRT05
+#define CRT05__H_SYNC_END__SHIFT                                                                              0x0
+#define CRT05__H_SYNC_SKEW__SHIFT                                                                             0x5
+#define CRT05__H_BLANK_END_B5__SHIFT                                                                          0x7
+#define CRT05__H_SYNC_END_MASK                                                                                0x1FL
+#define CRT05__H_SYNC_SKEW_MASK                                                                               0x60L
+#define CRT05__H_BLANK_END_B5_MASK                                                                            0x80L
+//CRT06
+#define CRT06__V_TOTAL__SHIFT                                                                                 0x0
+#define CRT06__V_TOTAL_MASK                                                                                   0xFFL
+//CRT07
+#define CRT07__V_TOTAL_B8__SHIFT                                                                              0x0
+#define CRT07__V_DISP_END_B8__SHIFT                                                                           0x1
+#define CRT07__V_SYNC_START_B8__SHIFT                                                                         0x2
+#define CRT07__V_BLANK_START_B8__SHIFT                                                                        0x3
+#define CRT07__LINE_CMP_B8__SHIFT                                                                             0x4
+#define CRT07__V_TOTAL_B9__SHIFT                                                                              0x5
+#define CRT07__V_DISP_END_B9__SHIFT                                                                           0x6
+#define CRT07__V_SYNC_START_B9__SHIFT                                                                         0x7
+#define CRT07__V_TOTAL_B8_MASK                                                                                0x01L
+#define CRT07__V_DISP_END_B8_MASK                                                                             0x02L
+#define CRT07__V_SYNC_START_B8_MASK                                                                           0x04L
+#define CRT07__V_BLANK_START_B8_MASK                                                                          0x08L
+#define CRT07__LINE_CMP_B8_MASK                                                                               0x10L
+#define CRT07__V_TOTAL_B9_MASK                                                                                0x20L
+#define CRT07__V_DISP_END_B9_MASK                                                                             0x40L
+#define CRT07__V_SYNC_START_B9_MASK                                                                           0x80L
+//CRT08
+#define CRT08__ROW_SCAN_START__SHIFT                                                                          0x0
+#define CRT08__BYTE_PAN__SHIFT                                                                                0x5
+#define CRT08__ROW_SCAN_START_MASK                                                                            0x1FL
+#define CRT08__BYTE_PAN_MASK                                                                                  0x60L
+//CRT09
+#define CRT09__MAX_ROW_SCAN__SHIFT                                                                            0x0
+#define CRT09__V_BLANK_START_B9__SHIFT                                                                        0x5
+#define CRT09__LINE_CMP_B9__SHIFT                                                                             0x6
+#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT                                                                      0x7
+#define CRT09__MAX_ROW_SCAN_MASK                                                                              0x1FL
+#define CRT09__V_BLANK_START_B9_MASK                                                                          0x20L
+#define CRT09__LINE_CMP_B9_MASK                                                                               0x40L
+#define CRT09__DOUBLE_CHAR_HEIGHT_MASK                                                                        0x80L
+//CRT0A
+#define CRT0A__CURSOR_START__SHIFT                                                                            0x0
+#define CRT0A__CURSOR_DISABLE__SHIFT                                                                          0x5
+#define CRT0A__CURSOR_START_MASK                                                                              0x1FL
+#define CRT0A__CURSOR_DISABLE_MASK                                                                            0x20L
+//CRT0B
+#define CRT0B__CURSOR_END__SHIFT                                                                              0x0
+#define CRT0B__CURSOR_SKEW__SHIFT                                                                             0x5
+#define CRT0B__CURSOR_END_MASK                                                                                0x1FL
+#define CRT0B__CURSOR_SKEW_MASK                                                                               0x60L
+//CRT0C
+#define CRT0C__DISP_START__SHIFT                                                                              0x0
+#define CRT0C__DISP_START_MASK                                                                                0xFFL
+//CRT0D
+#define CRT0D__DISP_START__SHIFT                                                                              0x0
+#define CRT0D__DISP_START_MASK                                                                                0xFFL
+//CRT0E
+#define CRT0E__CURSOR_LOC_HI__SHIFT                                                                           0x0
+#define CRT0E__CURSOR_LOC_HI_MASK                                                                             0xFFL
+//CRT0F
+#define CRT0F__CURSOR_LOC_LO__SHIFT                                                                           0x0
+#define CRT0F__CURSOR_LOC_LO_MASK                                                                             0xFFL
+//CRT10
+#define CRT10__V_SYNC_START__SHIFT                                                                            0x0
+#define CRT10__V_SYNC_START_MASK                                                                              0xFFL
+//CRT11
+#define CRT11__V_SYNC_END__SHIFT                                                                              0x0
+#define CRT11__V_INTR_CLR__SHIFT                                                                              0x4
+#define CRT11__V_INTR_EN__SHIFT                                                                               0x5
+#define CRT11__SEL5_REFRESH_CYC__SHIFT                                                                        0x6
+#define CRT11__C0T7_WR_ONLY__SHIFT                                                                            0x7
+#define CRT11__V_SYNC_END_MASK                                                                                0x0FL
+#define CRT11__V_INTR_CLR_MASK                                                                                0x10L
+#define CRT11__V_INTR_EN_MASK                                                                                 0x20L
+#define CRT11__SEL5_REFRESH_CYC_MASK                                                                          0x40L
+#define CRT11__C0T7_WR_ONLY_MASK                                                                              0x80L
+//CRT12
+#define CRT12__V_DISP_END__SHIFT                                                                              0x0
+#define CRT12__V_DISP_END_MASK                                                                                0xFFL
+//CRT13
+#define CRT13__DISP_PITCH__SHIFT                                                                              0x0
+#define CRT13__DISP_PITCH_MASK                                                                                0xFFL
+//CRT14
+#define CRT14__UNDRLN_LOC__SHIFT                                                                              0x0
+#define CRT14__ADDR_CNT_BY4__SHIFT                                                                            0x5
+#define CRT14__DOUBLE_WORD__SHIFT                                                                             0x6
+#define CRT14__UNDRLN_LOC_MASK                                                                                0x1FL
+#define CRT14__ADDR_CNT_BY4_MASK                                                                              0x20L
+#define CRT14__DOUBLE_WORD_MASK                                                                               0x40L
+//CRT15
+#define CRT15__V_BLANK_START__SHIFT                                                                           0x0
+#define CRT15__V_BLANK_START_MASK                                                                             0xFFL
+//CRT16
+#define CRT16__V_BLANK_END__SHIFT                                                                             0x0
+#define CRT16__V_BLANK_END_MASK                                                                               0xFFL
+//CRT17
+#define CRT17__RA0_AS_A13B__SHIFT                                                                             0x0
+#define CRT17__RA1_AS_A14B__SHIFT                                                                             0x1
+#define CRT17__VCOUNT_BY2__SHIFT                                                                              0x2
+#define CRT17__ADDR_CNT_BY2__SHIFT                                                                            0x3
+#define CRT17__WRAP_A15TOA0__SHIFT                                                                            0x5
+#define CRT17__BYTE_MODE__SHIFT                                                                               0x6
+#define CRT17__CRTC_SYNC_EN__SHIFT                                                                            0x7
+#define CRT17__RA0_AS_A13B_MASK                                                                               0x01L
+#define CRT17__RA1_AS_A14B_MASK                                                                               0x02L
+#define CRT17__VCOUNT_BY2_MASK                                                                                0x04L
+#define CRT17__ADDR_CNT_BY2_MASK                                                                              0x08L
+#define CRT17__WRAP_A15TOA0_MASK                                                                              0x20L
+#define CRT17__BYTE_MODE_MASK                                                                                 0x40L
+#define CRT17__CRTC_SYNC_EN_MASK                                                                              0x80L
+//CRT18
+#define CRT18__LINE_CMP__SHIFT                                                                                0x0
+#define CRT18__LINE_CMP_MASK                                                                                  0xFFL
+//CRT1E
+#define CRT1E__GRPH_DEC_RD1__SHIFT                                                                            0x1
+#define CRT1E__GRPH_DEC_RD1_MASK                                                                              0x02L
+//CRT1F
+#define CRT1F__GRPH_DEC_RD0__SHIFT                                                                            0x0
+#define CRT1F__GRPH_DEC_RD0_MASK                                                                              0xFFL
+//CRT22
+#define CRT22__GRPH_LATCH_DATA__SHIFT                                                                         0x0
+#define CRT22__GRPH_LATCH_DATA_MASK                                                                           0xFFL
+
+
+// addressBlock: vga_vgagrphind
+//GRA00
+#define GRA00__GRPH_SET_RESET0__SHIFT                                                                         0x0
+#define GRA00__GRPH_SET_RESET1__SHIFT                                                                         0x1
+#define GRA00__GRPH_SET_RESET2__SHIFT                                                                         0x2
+#define GRA00__GRPH_SET_RESET3__SHIFT                                                                         0x3
+#define GRA00__GRPH_SET_RESET0_MASK                                                                           0x01L
+#define GRA00__GRPH_SET_RESET1_MASK                                                                           0x02L
+#define GRA00__GRPH_SET_RESET2_MASK                                                                           0x04L
+#define GRA00__GRPH_SET_RESET3_MASK                                                                           0x08L
+//GRA01
+#define GRA01__GRPH_SET_RESET_ENA0__SHIFT                                                                     0x0
+#define GRA01__GRPH_SET_RESET_ENA1__SHIFT                                                                     0x1
+#define GRA01__GRPH_SET_RESET_ENA2__SHIFT                                                                     0x2
+#define GRA01__GRPH_SET_RESET_ENA3__SHIFT                                                                     0x3
+#define GRA01__GRPH_SET_RESET_ENA0_MASK                                                                       0x01L
+#define GRA01__GRPH_SET_RESET_ENA1_MASK                                                                       0x02L
+#define GRA01__GRPH_SET_RESET_ENA2_MASK                                                                       0x04L
+#define GRA01__GRPH_SET_RESET_ENA3_MASK                                                                       0x08L
+//GRA02
+#define GRA02__GRPH_CCOMP__SHIFT                                                                              0x0
+#define GRA02__GRPH_CCOMP_MASK                                                                                0x0FL
+//GRA03
+#define GRA03__GRPH_ROTATE__SHIFT                                                                             0x0
+#define GRA03__GRPH_FN_SEL__SHIFT                                                                             0x3
+#define GRA03__GRPH_ROTATE_MASK                                                                               0x07L
+#define GRA03__GRPH_FN_SEL_MASK                                                                               0x18L
+//GRA04
+#define GRA04__GRPH_RMAP__SHIFT                                                                               0x0
+#define GRA04__GRPH_RMAP_MASK                                                                                 0x03L
+//GRA05
+#define GRA05__GRPH_WRITE_MODE__SHIFT                                                                         0x0
+#define GRA05__GRPH_READ1__SHIFT                                                                              0x3
+#define GRA05__CGA_ODDEVEN__SHIFT                                                                             0x4
+#define GRA05__GRPH_OES__SHIFT                                                                                0x5
+#define GRA05__GRPH_PACK__SHIFT                                                                               0x6
+#define GRA05__GRPH_WRITE_MODE_MASK                                                                           0x03L
+#define GRA05__GRPH_READ1_MASK                                                                                0x08L
+#define GRA05__CGA_ODDEVEN_MASK                                                                               0x10L
+#define GRA05__GRPH_OES_MASK                                                                                  0x20L
+#define GRA05__GRPH_PACK_MASK                                                                                 0x40L
+//GRA06
+#define GRA06__GRPH_GRAPHICS__SHIFT                                                                           0x0
+#define GRA06__GRPH_ODDEVEN__SHIFT                                                                            0x1
+#define GRA06__GRPH_ADRSEL__SHIFT                                                                             0x2
+#define GRA06__GRPH_GRAPHICS_MASK                                                                             0x01L
+#define GRA06__GRPH_ODDEVEN_MASK                                                                              0x02L
+#define GRA06__GRPH_ADRSEL_MASK                                                                               0x0CL
+//GRA07
+#define GRA07__GRPH_XCARE0__SHIFT                                                                             0x0
+#define GRA07__GRPH_XCARE1__SHIFT                                                                             0x1
+#define GRA07__GRPH_XCARE2__SHIFT                                                                             0x2
+#define GRA07__GRPH_XCARE3__SHIFT                                                                             0x3
+#define GRA07__GRPH_XCARE0_MASK                                                                               0x01L
+#define GRA07__GRPH_XCARE1_MASK                                                                               0x02L
+#define GRA07__GRPH_XCARE2_MASK                                                                               0x04L
+#define GRA07__GRPH_XCARE3_MASK                                                                               0x08L
+//GRA08
+#define GRA08__GRPH_BMSK__SHIFT                                                                               0x0
+#define GRA08__GRPH_BMSK_MASK                                                                                 0xFFL
+
+
+// addressBlock: vga_vgaattrind
+//ATTR00
+#define ATTR00__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR00__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR01
+#define ATTR01__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR01__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR02
+#define ATTR02__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR02__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR03
+#define ATTR03__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR03__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR04
+#define ATTR04__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR04__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR05
+#define ATTR05__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR05__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR06
+#define ATTR06__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR06__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR07
+#define ATTR07__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR07__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR08
+#define ATTR08__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR08__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR09
+#define ATTR09__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR09__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0A
+#define ATTR0A__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0A__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0B
+#define ATTR0B__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0B__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0C
+#define ATTR0C__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0C__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0D
+#define ATTR0D__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0D__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0E
+#define ATTR0E__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0E__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0F
+#define ATTR0F__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0F__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR10
+#define ATTR10__ATTR_GRPH_MODE__SHIFT                                                                         0x0
+#define ATTR10__ATTR_MONO_EN__SHIFT                                                                           0x1
+#define ATTR10__ATTR_LGRPH_EN__SHIFT                                                                          0x2
+#define ATTR10__ATTR_BLINK_EN__SHIFT                                                                          0x3
+#define ATTR10__ATTR_PANTOPONLY__SHIFT                                                                        0x5
+#define ATTR10__ATTR_PCLKBY2__SHIFT                                                                           0x6
+#define ATTR10__ATTR_CSEL_EN__SHIFT                                                                           0x7
+#define ATTR10__ATTR_GRPH_MODE_MASK                                                                           0x01L
+#define ATTR10__ATTR_MONO_EN_MASK                                                                             0x02L
+#define ATTR10__ATTR_LGRPH_EN_MASK                                                                            0x04L
+#define ATTR10__ATTR_BLINK_EN_MASK                                                                            0x08L
+#define ATTR10__ATTR_PANTOPONLY_MASK                                                                          0x20L
+#define ATTR10__ATTR_PCLKBY2_MASK                                                                             0x40L
+#define ATTR10__ATTR_CSEL_EN_MASK                                                                             0x80L
+//ATTR11
+#define ATTR11__ATTR_OVSC__SHIFT                                                                              0x0
+#define ATTR11__ATTR_OVSC_MASK                                                                                0xFFL
+//ATTR12
+#define ATTR12__ATTR_MAP_EN__SHIFT                                                                            0x0
+#define ATTR12__ATTR_VSMUX__SHIFT                                                                             0x4
+#define ATTR12__ATTR_MAP_EN_MASK                                                                              0x0FL
+#define ATTR12__ATTR_VSMUX_MASK                                                                               0x30L
+//ATTR13
+#define ATTR13__ATTR_PPAN__SHIFT                                                                              0x0
+#define ATTR13__ATTR_PPAN_MASK                                                                                0x0FL
+//ATTR14
+#define ATTR14__ATTR_CSEL1__SHIFT                                                                             0x0
+#define ATTR14__ATTR_CSEL2__SHIFT                                                                             0x2
+#define ATTR14__ATTR_CSEL1_MASK                                                                               0x03L
+#define ATTR14__ATTR_CSEL2_MASK                                                                               0x0CL
+
+
+// addressBlock: azendpoint_f2codecind
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                         0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                            0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                        0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                       0xb
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                           0xe
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                                0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT                              0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                           0x0000000FL
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                              0x00000070L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                          0x00000700L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                         0x00003800L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                             0x00004000L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                                  0x00008000L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK                                0x00008000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                                0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                                 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                                  0x0000000FL
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                                   0x000000F0L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                         0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                      0x2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                       0x3
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                      0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                                 0x5
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                       0x6
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                         0x7
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                        0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                                 0x17
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                       0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                           0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                        0x00000004L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                         0x00000008L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                        0x00000010L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                                   0x00000020L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                         0x00000040L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                           0x00000080L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                          0x00007F00L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                                   0x00800000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT                                      0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK                                        0x0000007FL
+//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                                       0x0
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                                    0x14
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                                         0x00000003L
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                                      0x00700000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT                               0x7
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK                                 0x00000080L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                                         0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                                           0x000000FFL
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT            0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT              0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT             0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK              0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK                0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK               0x00000070L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT                 0x4
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK                   0x00000010L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT              0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT               0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                0x00000FFFL
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                 0x001F0000L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                             0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                               0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT              0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK                0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                                         0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                                           0x00000040L
+//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                          0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                       0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                            0x0000003FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                         0x00000080L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                                0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                                0x1f
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                                  0x7FFFFFFFL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                                  0x80000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                           0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT                0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                               0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                              0xc
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT                    0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT                     0x14
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                           0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT                  0x1e
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                             0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK                  0x000000F0L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                                 0x00000F00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                                0x0000F000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                      0x000F0000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                       0x00F00000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                             0x3F000000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK                    0xC0000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                            0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                               0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                              0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT                  0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK                    0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT                0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                           0x0000003FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK                  0x000000C0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT                       0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT                         0x9
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT                 0xa
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK                      0x0000007FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK                         0x00000100L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK                           0x00000200L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK                   0x0000FC00L
+//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                               0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT                                  0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT                                         0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT                                    0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK                                    0x00000003L
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK                                           0x00000078L
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK                                      0x00000080L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT                                      0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT                            0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT                                0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT                     0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK                                       0x00000007L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK                                        0x00000078L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK                              0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK                                  0x00FF0000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK                       0xFF000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT                                  0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK                                    0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT                                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT                                             0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK                                               0x000000FFL
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK                                               0x0000FF00L
+//AZALIA_F2_CODEC_PIN_CONTROL_HBR
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                                   0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                                    0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                                     0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                      0x00000010L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK                               0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT                                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK                                      0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                               0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                                 0x00000001L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                                   0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT                          0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                                     0x00000003L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK                            0x0000003CL
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT                         0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT                0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT                            0x3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT                   0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK                           0x00000003L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK                  0x00000004L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                              0x00000078L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK                     0x00000080L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT                     0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT            0x6
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK                       0x0000003FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK              0x00000040L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT            0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT   0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK              0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK     0x00000010L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT               0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT                     0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                                 0x5
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT                           0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK                 0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK                       0x00000010L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                                   0x00000060L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK                             0x00000080L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK                         0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK                         0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK                         0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK                         0x000000F0L
+//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                                         0x0
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                                           0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                               0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                                 0x00000001L
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                          0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT                    0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                            0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                      0x0000FF00L
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                                           0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                           0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                             0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                                           0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                                             0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT                       0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                               0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT                             0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                                       0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK                         0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                                 0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                               0x00FF0000L
+//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT   0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK     0x00000003L
+//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK                       0x00000010L
+//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT            0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT               0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT              0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT          0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                                0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT                     0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT       0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                       0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                               0x9
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                         0xa
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                               0xb
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT       0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                                  0x14
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK              0x00000001L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK                 0x00000002L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK                0x00000004L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK            0x00000008L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                                  0x00000020L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                       0x00000040L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK         0x00000080L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                         0x00000100L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                                 0x00000200L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                           0x00000400L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                                 0x00000800L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK         0x000F0000L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                                    0x00F00000L
+//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                            0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                                   0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                          0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                            0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                                     0x4
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                      0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                                  0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                               0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                       0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                       0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                                 0x18
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                              0x00000001L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                                     0x00000002L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                            0x00000004L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                              0x00000008L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                       0x00000010L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                        0x00000020L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                                    0x00000040L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                                 0x00000080L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                         0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                         0x00010000L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                                   0x01000000L
+//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT                   0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azendpoint_descriptorind
+//AUDIO_DESCRIPTOR0
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR1
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR2
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR3
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR4
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR5
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR6
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR7
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR8
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR9
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR10
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+//AUDIO_DESCRIPTOR11
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+//AUDIO_DESCRIPTOR12
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+//AUDIO_DESCRIPTOR13
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+
+
+// addressBlock: azendpoint_sinkinfoind
+//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT                                   0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK                                     0x0000FFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT                                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK                                               0x0000FFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK                           0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT                                                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK                                                      0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT                                                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK                                                      0xFFFFFFFFL
+//SINK_DESCRIPTION0
+#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION0__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION1
+#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION1__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION2
+#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION2__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION3
+#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION3__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION4
+#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION4__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION5
+#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION5__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION6
+#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION6__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION7
+#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION7__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION8
+#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION8__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION9
+#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION9__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION10
+#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION10__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION11
+#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION11__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION12
+#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION12__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION13
+#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION13__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION14
+#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION14__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION15
+#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION15__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION16
+#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION16__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION17
+#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION17__DESCRIPTION_MASK                                                                  0x000000FFL
+
+
+// addressBlock: azf0controller_azinputcrc0resultind
+//AZALIA_INPUT_CRC0_CHANNEL0
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL1
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL2
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL3
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL4
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL5
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL6
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL7
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azinputcrc1resultind
+//AZALIA_INPUT_CRC1_CHANNEL0
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL1
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL2
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL3
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL4
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL5
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL6
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL7
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azcrc0resultind
+//AZALIA_CRC0_CHANNEL0
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL1
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL2
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL3
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL4
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL5
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL6
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL7
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azcrc1resultind
+//AZALIA_CRC1_CHANNEL0
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL1
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL2
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL3
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL4
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL5
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL6
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL7
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: azinputendpoint_f2codecind
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                      0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                  0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                 0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                     0xe
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                          0xf
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                     0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                        0x00000070L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                    0x00000700L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                   0x00003800L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                       0x00004000L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                            0x00008000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                          0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                           0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                            0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                             0x000000F0L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                               0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                   0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                 0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                           0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                 0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                   0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                  0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                           0x17
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                     0x00000002L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                  0x00000004L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                   0x00000008L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                  0x00000010L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                             0x00000020L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                   0x00000040L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                     0x00000080L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                    0x00007F00L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                             0x00800000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT   0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT           0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                    0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT         0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT           0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                   0x9
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT             0xa
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                   0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                      0x14
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK     0x00000002L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK    0x00000004L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK             0x00000010L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                      0x00000020L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK           0x00000040L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK             0x00000100L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                     0x00000200L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK               0x00000400L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                     0x00000800L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                        0x00F00000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT        0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT         0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK          0x00000FFFL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK           0x001F0000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                       0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                         0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                                    0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                                      0x00000020L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                    0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                 0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                      0x0000003FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                   0x00000080L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                          0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                          0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                            0x7FFFFFFFL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                            0x80000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                     0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT          0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                         0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                        0xc
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT              0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT               0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                     0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT            0x1e
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                       0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK            0x000000F0L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                           0x00000F00L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                          0x0000F000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                 0x00F00000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                       0x3F000000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK              0xC0000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                       0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                      0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                         0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                        0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT            0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT             0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK              0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK               0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT          0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                     0x0000003FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK            0x000000C0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                       0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                         0x000000FFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                             0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                              0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                               0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                0x00000010L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                    0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT              0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                      0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                0x0000FF00L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                                     0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                     0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                       0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT                         0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT                         0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK                           0x00000006L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK                 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK   0x00000020L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT                                0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT                                  0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                                   0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                                       0x00000007L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK                                  0x0000FF00L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                                    0x00FF0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                                     0x80000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT                           0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK                             0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT                           0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK                             0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L
+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                      0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                             0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                    0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                      0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                            0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                         0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                           0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                        0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                               0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                      0x00000004L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                        0x00000008L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                  0x00000020L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                              0x00000040L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                           0x00000080L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                   0x0000FF00L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                   0x00010000L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                                             0x01000000L
+
+
+// addressBlock: azroot_f2codecind
+//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL
+//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT                   0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK                     0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT                   0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK                     0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT                   0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK                     0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L
+
+
+// addressBlock: azf0stream0_streamind
+//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream1_streamind
+//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream2_streamind
+//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream3_streamind
+//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream4_streamind
+//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream5_streamind
+//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream6_streamind
+//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream7_streamind
+//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream8_streamind
+//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream9_streamind
+//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream10_streamind
+//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream11_streamind
+//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream12_streamind
+//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream13_streamind
+//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream14_streamind
+//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream15_streamind
+//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0endpoint0_endpointind
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint1_endpointind
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint2_endpointind
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint3_endpointind
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint4_endpointind
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint5_endpointind
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint6_endpointind
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint7_endpointind
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0inputendpoint0_inputendpointind
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint1_inputendpointind
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint2_inputendpointind
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint3_inputendpointind
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint4_inputendpointind
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint5_inputendpointind
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint6_inputendpointind
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint7_inputendpointind
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: c20_phy_cr0_rdpcspipecrind
+//C20_PHY_CR0_SUP_DIG_IDCODE_LO
+#define C20_PHY_CR0_SUP_DIG_IDCODE_LO__VAL__SHIFT                                                             0x0
+#define C20_PHY_CR0_SUP_DIG_IDCODE_LO__VAL_MASK                                                               0xFFFFL
+//C20_PHY_CR0_SUP_DIG_IDCODE_HI
+#define C20_PHY_CR0_SUP_DIG_IDCODE_HI__VAL__SHIFT                                                             0x0
+#define C20_PHY_CR0_SUP_DIG_IDCODE_HI__VAL_MASK                                                               0xFFFFL
+//C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN__SHIFT                                          0x2
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN__SHIFT                                  0x3
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD__SHIFT                                              0x4
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE__SHIFT                                            0x6
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN__SHIFT                                                    0xa
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN__SHIFT                                            0xb
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD__SHIFT                                  0xc
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN__SHIFT                               0xd
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14__SHIFT                                           0xe
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_MASK                                                 0x0001L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_MASK                                            0x0004L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN_MASK                                    0x0008L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_MASK                                                0x0010L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_MASK                                              0x01C0L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_MASK                                                      0x0400L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN_MASK                                              0x0800L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_MASK                                    0x1000L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN_MASK                                 0x2000L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14_MASK                                             0xC000L
+//C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL__SHIFT                                          0x0
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL__SHIFT                                           0x3
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN__SHIFT                                   0x5
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN__SHIFT                                            0x6
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL__SHIFT                                       0x8
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                               0x9
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10__SHIFT                                           0xa
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_MASK                                            0x0003L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_MASK                                             0x0018L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN_MASK                                     0x0020L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_MASK                                              0x0040L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_MASK                                         0x0100L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10_MASK                                             0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x0200L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x0200L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                                     0x0
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN__SHIFT                             0x2
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                               0x3
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN__SHIFT                                       0x6
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE__SHIFT                                              0x7
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9__SHIFT                                                0x9
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                                       0x0003L
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN_MASK                               0x0004L
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_MASK                                                 0x0038L
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN_MASK                                         0x0040L
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_MASK                                                0x0080L
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9_MASK                                                  0xFE00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xd
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN__SHIFT                                             0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL_MASK                                           0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV_MASK                                           0x001CL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL_MASK                                 0x0060L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                   0x0E00L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                    0x1000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK                                        0x2000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS_MASK                                        0x4000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN_MASK                                               0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN__SHIFT                                          0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL__SHIFT                                          0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD_MASK                                          0x3000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN_MASK                                            0x4000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL_MASK                                            0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_OVRD_IN
+#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW_MASK                                           0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN
+#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH_MASK                                         0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN__SHIFT                                          0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x3
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0xd
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN_MASK                                            0x0004L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD_MASK                                     0x0008L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK                               0x03E0L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK                                0x0400L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK                      0x1000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK                                  0x2000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN_MASK                          0x4000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_3
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_4
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_5
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_6
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN__SHIFT                                             0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT                                            0xd
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL_MASK                                           0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV_MASK                                           0x001CL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL_MASK                                 0x0060L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                   0x0700L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN_MASK                                               0x1000L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK                                              0xE000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT__SHIFT                                          0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_MASK                                         0x007FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_MASK                                            0x7F00L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN_MASK                                    0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP__SHIFT                                         0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN__SHIFT                                 0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_MASK                                        0x007FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_MASK                                           0x7F00L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN_MASK                                   0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I__SHIFT                                             0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN__SHIFT                                     0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x3
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_MASK                                               0x0003L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN_MASK                                       0x0004L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_MASK                                          0x0018L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN__SHIFT                                          0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x3
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0xd
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN_MASK                                            0x0004L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD_MASK                                     0x0008L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK                               0x03E0L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK                                0x0400L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK                      0x1000L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK                                  0x2000L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN_MASK                          0x4000L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_3
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_5
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_6
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ__SHIFT                                                   0x0
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN__SHIFT                                               0x1
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN__SHIFT                                                  0x2
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN__SHIFT                                                  0x3
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN__SHIFT                                                 0x4
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7__SHIFT                                               0x7
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ_MASK                                                     0x0001L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN_MASK                                                 0x0002L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN_MASK                                                    0x0004L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN_MASK                                                    0x0008L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN_MASK                                                   0x0010L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7_MASK                                                 0xFF80L
+//C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET__SHIFT                                            0x0
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET__SHIFT                                              0xa
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN__SHIFT                                      0xf
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_MASK                                              0x01FFL
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_MASK                                                0x7C00L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN_MASK                                        0x8000L
+//C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET__SHIFT                                            0x0
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10__SHIFT                                              0xa
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_MASK                                              0x01FFL
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10_MASK                                                0xFC00L
+//C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT                                                  0x2
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT                                                  0x4
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x6
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x7
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x9
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD__SHIFT                                           0xa
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0xb
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD__SHIFT                                            0xc
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0xd
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14__SHIFT                                               0xe
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x0001L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK                                                    0x0004L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK                                                    0x0010L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x0040L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x0080L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x0100L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x0200L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_MASK                                             0x0400L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x0800L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_MASK                                              0x1000L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x2000L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14_MASK                                                 0xC000L
+//C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN
+#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x6
+#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN__SHIFT                                         0x9
+#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
+#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x001FL
+#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x01C0L
+#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN_MASK                                           0x0200L
+#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK                                                  0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV__SHIFT                                        0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xb
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14__SHIFT                                            0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV_MASK                                           0x000EL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV_MASK                                          0x0030L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0380L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK                                        0x0400L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS_MASK                                        0x0800L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD_MASK                                          0x3000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14_MASK                                              0xC000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_ASIC_IN
+#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW_MASK                                           0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN
+#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH_MASK                                         0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x3
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD_MASK                                     0x0004L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK                               0x00F8L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK                                0x0100L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK                                  0x0200L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_3
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_4
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_5
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_6
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV__SHIFT                                        0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x6
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9__SHIFT                                             0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV_MASK                                           0x000EL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV_MASK                                          0x0030L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x01C0L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9_MASK                                               0xFE00L
+//C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT__SHIFT                                          0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS_MASK                                         0x007FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_MASK                                            0x3F80L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP__SHIFT                                         0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS_MASK                                        0x007FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_MASK                                           0x3F80L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I__SHIFT                                             0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I_MASK                                               0x0003L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO_MASK                                          0x000CL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x3
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD_MASK                                     0x0004L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK                               0x00F8L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK                                0x0100L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK                                  0x0200L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_3
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_5
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_6
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                            0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                      0xb
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14__SHIFT                                      0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                              0x0600L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                        0x3800L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14_MASK                                        0xC000L
+//C20_PHY_CR0_SUP_DIG_ASIC_IN_0
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__PHY_RESET__SHIFT                                                       0x0
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_CLK_EN__SHIFT                                                      0x1
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN__SHIFT                                                 0x2
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_USE_PAD__SHIFT                                                     0x3
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__TEST_BURNIN__SHIFT                                                     0x4
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN__SHIFT                                                  0x5
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RTUNE_REQ__SHIFT                                                       0x6
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RES_REQ_IN__SHIFT                                                      0x7
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RES_ACK_IN__SHIFT                                                      0x8
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__BG_EN__SHIFT                                                           0x9
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                              0xa
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_RANGE__SHIFT                                                       0xb
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE__SHIFT                                                 0xe
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RESERVED_15_15__SHIFT                                                  0xf
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__PHY_RESET_MASK                                                         0x0001L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_CLK_EN_MASK                                                        0x0002L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN_MASK                                                   0x0004L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_USE_PAD_MASK                                                       0x0008L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__TEST_BURNIN_MASK                                                       0x0010L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN_MASK                                                    0x0020L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RTUNE_REQ_MASK                                                         0x0040L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RES_REQ_IN_MASK                                                        0x0080L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RES_ACK_IN_MASK                                                        0x0100L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__BG_EN_MASK                                                             0x0200L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL_MASK                                                0x0400L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_RANGE_MASK                                                         0x3800L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE_MASK                                                   0x4000L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RESERVED_15_15_MASK                                                    0x8000L
+//C20_PHY_CR0_SUP_DIG_ASIC_IN_1
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__SUP_MISC__SHIFT                                                        0x0
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN__SHIFT                                                0x8
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN__SHIFT                                              0x9
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL__SHIFT                                                 0xa
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL__SHIFT                                                  0xc
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__RESERVED_15_14__SHIFT                                                  0xe
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__SUP_MISC_MASK                                                          0x00FFL
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN_MASK                                                  0x0100L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN_MASK                                                0x0200L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL_MASK                                                   0x0C00L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL_MASK                                                    0x3000L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__RESERVED_15_14_MASK                                                    0xC000L
+//C20_PHY_CR0_SUP_DIG_ASIC_OUT_0
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT__SHIFT                                              0x0
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__MPLLA_STATE__SHIFT                                                    0x1
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__MPLLB_STATE__SHIFT                                                    0x2
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RTUNE_ACK__SHIFT                                                      0x3
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT__SHIFT                                                    0x4
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT__SHIFT                                                    0x5
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__DTB_OUT__SHIFT                                                        0x6
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RESERVED_15_8__SHIFT                                                  0x8
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT_MASK                                                0x0001L
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__MPLLA_STATE_MASK                                                      0x0002L
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__MPLLB_STATE_MASK                                                      0x0004L
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RTUNE_ACK_MASK                                                        0x0008L
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT_MASK                                                      0x0010L
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT_MASK                                                      0x0020L
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__DTB_OUT_MASK                                                          0x00C0L
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RESERVED_15_8_MASK                                                    0xFF00L
+//C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN
+#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x5
+#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN__SHIFT                                                 0x8
+#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET__SHIFT                                                0x9
+#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14__SHIFT                                                0xe
+#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x001FL
+#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x00E0L
+#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN_MASK                                                   0x0100L
+#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET_MASK                                                  0x3E00L
+#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14_MASK                                                  0xC000L
+//C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN__SHIFT                                            0x8
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9__SHIFT                                               0x9
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN_MASK                                              0x0100L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9_MASK                                                 0xFE00L
+//C20_PHY_CR0_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN
+#define C20_PHY_CR0_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET__SHIFT                                 0x0
+#define C20_PHY_CR0_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET_MASK                                   0x01FFL
+#define C20_PHY_CR0_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN
+#define C20_PHY_CR0_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET__SHIFT                                 0x0
+#define C20_PHY_CR0_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET_MASK                                   0x01FFL
+#define C20_PHY_CR0_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL__SHIFT                                0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL__SHIFT                                  0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL__SHIFT                             0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10__SHIFT                                          0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL_MASK                                  0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL_MASK                                    0x0004L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL_MASK                               0x01F0L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10_MASK                                            0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY__SHIFT                                           0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE__SHIFT                                      0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7__SHIFT                                           0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE_MASK                                           0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY_MASK                                             0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE_MASK                                        0x007CL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7_MASK                                             0xFF80L
+//C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED__SHIFT                                                     0x1
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL__SHIFT                                                0x6
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7__SHIFT                                                0x7
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x0001L
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED_MASK                                                       0x0002L
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x0004L
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x0038L
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL_MASK                                                  0x0040L
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7_MASK                                                  0xFF80L
+//C20_PHY_CR0_SUP_DIG_RTUNE_STAT
+#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__RTUNE_STATE__SHIFT                                                    0xa
+#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE__SHIFT                                                 0xd
+#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__RESERVED_15_15__SHIFT                                                 0xf
+#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x03FFL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__RTUNE_STATE_MASK                                                      0x1C00L
+#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE_MASK                                                   0x6000L
+#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__RESERVED_15_15_MASK                                                   0x8000L
+//C20_PHY_CR0_SUP_DIG_RTUNE_RX_SET_VAL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
+#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x003FL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0xFFC0L
+//C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x03FFL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x03FFL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR0_SUP_DIG_RTUNE_RX_STAT
+#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x003FL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_STAT
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x03FFL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0xFC00L
+//C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_STAT
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x03FFL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0xFC00L
+//C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG__SHIFT                                                  0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10__SHIFT                                       0xa
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG_MASK                                                    0x03FFL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10_MASK                                         0xFC00L
+//C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_1
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN__SHIFT                                                 0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10__SHIFT                                       0xa
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN_MASK                                                   0x03FFL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10_MASK                                         0xFC00L
+//C20_PHY_CR0_SUP_DIG_RTUNE_FAST_FLAGS
+#define C20_PHY_CR0_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE__SHIFT                                               0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR0_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE_MASK                                                 0x0001L
+#define C20_PHY_CR0_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER__SHIFT                                  0xa
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11__SHIFT                                    0xb
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x01FFL
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x0200L
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER_MASK                                    0x0400L
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11_MASK                                      0xF800L
+//C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x01FFL
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x00FFL
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x001FL
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x0020L
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE__SHIFT                                     0x1
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE__SHIFT                                     0x2
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE__SHIFT                                      0x4
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6__SHIFT                                     0x6
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE_MASK                                        0x0001L
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE_MASK                                       0x0002L
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE_MASK                                       0x000CL
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE_MASK                                        0x0030L
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6_MASK                                       0xFFC0L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL__SHIFT                                0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL__SHIFT                                 0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN__SHIFT                               0x6
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE__SHIFT                             0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE__SHIFT                                0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT_MASK                                      0x000FL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL_MASK                                  0x0010L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL_MASK                                   0x0020L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE_MASK                               0x7F80L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE_MASK                                  0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE__SHIFT                               0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14__SHIFT                              0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK                                      0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK                              0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK                               0x0008L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK                                0x0010L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE_MASK                                 0x3C00L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14_MASK                                0xC000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                                      0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                                       0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                                      0x6
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xd
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP__SHIFT                             0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                                        0x0010L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                                         0x0020L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                                        0x0040L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0080L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0100L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0200L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x1000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x2000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x4000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP_MASK                               0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME__SHIFT               0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME__SHIFT                 0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME_MASK                 0x03FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME_MASK                   0x3C00L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK                         0xC000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME__SHIFT           0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME__SHIFT                         0xb
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME_MASK             0x07FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME_MASK                           0xF800L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME__SHIFT                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME__SHIFT                  0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME__SHIFT               0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME_MASK                          0x001FL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME_MASK                    0x03E0L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME_MASK                 0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME__SHIFT                  0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME__SHIFT                0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME_MASK                    0x007FL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME_MASK                  0x0F80L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT                     0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL__SHIFT                       0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12__SHIFT                           0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK                       0x00FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL_MASK                         0x0F00L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12_MASK                             0xF000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT             0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP__SHIFT          0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG__SHIFT         0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK               0x00FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP_MASK            0x0300L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG_MASK           0x0C00L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0__SHIFT                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0__SHIFT                      0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0_MASK                        0x00FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0_MASK                        0xFF00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1__SHIFT                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1__SHIFT                      0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1_MASK                        0x00FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1_MASK                        0xFF00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2__SHIFT                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2__SHIFT                      0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2_MASK                        0x00FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2_MASK                        0xFF00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3__SHIFT                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3__SHIFT                      0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3_MASK                        0x00FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3_MASK                        0xFF00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME__SHIFT         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME__SHIFT                   0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME_MASK           0x03FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME_MASK                     0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME__SHIFT     0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11__SHIFT                       0xb
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME_MASK       0x07FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11_MASK                         0xF800L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME__SHIFT              0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10__SHIFT                       0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME_MASK                0x03FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10_MASK                         0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME__SHIFT             0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10__SHIFT                       0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME_MASK               0x03FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10_MASK                         0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7__SHIFT                        0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME_MASK                 0x007FL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7_MASK                          0xFF80L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN__SHIFT                 0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2__SHIFT                               0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN_MASK                   0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2_MASK                                 0xFFFCL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_FRAC_OUT
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_SSC_RAMP
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK                                          0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK                                           0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN__SHIFT                            0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE__SHIFT                                   0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL_MASK                             0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN_MASK                              0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE_MASK                                     0x007CL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK                                      0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK                              0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK                               0x0008L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK                                0x0010L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC__SHIFT                                 0xd
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC__SHIFT                                 0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0010L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0020L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0100L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x0200L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x0400L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x0800L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x1000L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC_MASK                                   0x2000L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC_MASK                                   0x4000L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME__SHIFT                          0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME_MASK                              0x00FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME_MASK                            0x3F00L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK                         0xC000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME__SHIFT                       0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME__SHIFT                          0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME_MASK                         0x00FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME_MASK                            0xFF00L
+//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME__SHIFT                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME__SHIFT                         0x6
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME_MASK                        0x003FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME_MASK                           0x0FC0L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME__SHIFT                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME__SHIFT                           0x6
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME_MASK                          0x003FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME_MASK                             0x0FC0L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS__SHIFT                0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS_MASK                  0x001FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7__SHIFT                        0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME_MASK                 0x007FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7_MASK                          0xFF80L
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_FRAC_OUT
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_SSC_RAMP
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK                                          0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK                                           0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT__SHIFT                                      0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK__SHIFT                                             0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC__SHIFT                                              0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT__SHIFT                                          0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL__SHIFT                                         0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10__SHIFT                                             0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT_MASK                                           0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT_MASK                                        0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK_MASK                                               0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC_MASK                                                0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT_MASK                                            0x01F0L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL_MASK                                           0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10_MASK                                               0xFC00L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN__SHIFT                                                 0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START__SHIFT                                    0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN__SHIFT                                            0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL__SHIFT                                      0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START__SHIFT                                   0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL__SHIFT                                         0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN__SHIFT                                                 0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST__SHIFT                                           0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE__SHIFT                                               0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST__SHIFT                                             0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN_MASK                                                   0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START_MASK                                      0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN_MASK                                              0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL_MASK                                        0x0030L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START_MASK                                     0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL_MASK                                           0x0380L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN_MASK                                                   0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST_MASK                                             0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE_MASK                                                 0x3000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST_MASK                                               0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP__SHIFT                              0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL__SHIFT                                       0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST__SHIFT                                       0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT__SHIFT                                 0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN__SHIFT                                 0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN__SHIFT                                   0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN__SHIFT                               0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN__SHIFT                               0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN__SHIFT                                0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN__SHIFT                            0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12__SHIFT                                      0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP_MASK                                0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL_MASK                                         0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST_MASK                                         0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT_MASK                                   0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN_MASK                                   0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN_MASK                                     0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN_MASK                              0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12_MASK                                        0xF000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL__SHIFT                                       0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST__SHIFT                                       0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT__SHIFT                                 0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN__SHIFT                               0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN__SHIFT                               0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN__SHIFT                               0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN__SHIFT                                0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN__SHIFT                           0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE__SHIFT                                 0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY__SHIFT                                   0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14__SHIFT                                      0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_MASK                                         0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST_MASK                                         0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT_MASK                                   0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN_MASK                             0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE_MASK                                   0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY_MASK                                     0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14_MASK                                        0xC000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN__SHIFT                                                  0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START__SHIFT                                          0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN__SHIFT                                  0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START__SHIFT                                          0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN__SHIFT                                  0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER__SHIFT                                0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP__SHIFT                                0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                          0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_MASK                                                    0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_MASK                                            0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN_MASK                                    0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_MASK                                            0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN_MASK                                    0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER_MASK                                  0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP_MASK                                  0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                            0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                      0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                              0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                   0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                           0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE__SHIFT                                  0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_MASK                                        0x000CL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_MASK                                     0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                             0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE_MASK                                       0x0180L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE_MASK                                    0x7E00L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL__SHIFT                                   0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL__SHIFT                                0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL_MASK                                      0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL_MASK                                     0x0006L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL_MASK                                  0x0018L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP__SHIFT                            0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                    0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN__SHIFT                            0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                         0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                         0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT__SHIFT                               0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                        0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_MASK                              0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                      0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN_MASK                              0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                           0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                           0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_MASK                                 0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN__SHIFT                                 0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN__SHIFT                              0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN__SHIFT                      0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN__SHIFT                            0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN__SHIFT                    0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN__SHIFT                            0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN__SHIFT                                  0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN__SHIFT                          0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN__SHIFT                              0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_MASK                                   0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN_MASK                           0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN_MASK                           0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_MASK                                0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN_MASK                        0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_MASK                              0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN_MASK                      0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_MASK                              0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN_MASK                           0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_MASK                                    0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN_MASK                            0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_MASK                                0x4000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN__SHIFT                                0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN_MASK                        0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK                                  0xFFF0L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC__SHIFT                              0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT__SHIFT                               0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC_MASK                                0x003FL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT_MASK                                 0xFFC0L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                         0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                         0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT__SHIFT                                   0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE__SHIFT                                   0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                     0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                        0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                           0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                           0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_MASK                                     0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_MASK                                     0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                       0x4000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN__SHIFT                                 0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN__SHIFT                                0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                        0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN__SHIFT                         0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN__SHIFT                             0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_MASK                                   0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN_MASK                           0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN_MASK                           0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                          0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN_MASK                           0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_MASK                               0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN__SHIFT                                0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN_MASK                        0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK                                  0xFFF0L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC__SHIFT                              0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT__SHIFT                               0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC_MASK                                0x003FL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT_MASK                                 0xFFC0L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                            0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                      0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                          0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                         0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                       0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                              0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                        0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                            0x000CL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                           0x3FF0L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                         0x4000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC__SHIFT                                          0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_MASK                                            0x00FFL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE__SHIFT                            0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN__SHIFT                    0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE__SHIFT                              0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN__SHIFT                      0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_MASK                              0x00FFL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN_MASK                      0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_MASK                                0x1E00L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN_MASK                        0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG__SHIFT                                   0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1__SHIFT                                        0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT__SHIFT                                  0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START__SHIFT                             0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG__SHIFT                              0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST__SHIFT                                  0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT__SHIFT                            0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG__SHIFT                                   0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2__SHIFT                           0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7__SHIFT                                0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST__SHIFT                           0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT__SHIFT                                 0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX__SHIFT                             0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_MASK                                     0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1_MASK                                          0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT_MASK                                    0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START_MASK                               0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG_MASK                                0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST_MASK                                    0x0060L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT_MASK                              0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG_MASK                                     0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2_MASK                             0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7_MASK                                  0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST_MASK                             0x1800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT_MASK                                   0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX_MASK                               0xC000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX__SHIFT                             0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0__SHIFT                         0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6__SHIFT                                        0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0__SHIFT                              0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS__SHIFT                                   0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST_MASK                                      0x0003L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX_MASK                               0x000CL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0_MASK                           0x0030L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6_MASK                                          0x00C0L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0_MASK                                0x7F00L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS_MASK                                     0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF__SHIFT                                 0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP__SHIFT                                 0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB__SHIFT                                      0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP__SHIFT                                 0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE__SHIFT                                 0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5__SHIFT                                        0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON__SHIFT                                 0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN__SHIFT                            0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN__SHIFT                           0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF_MASK                                   0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP_MASK                                   0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB_MASK                                        0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP_MASK                                   0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE_MASK                                   0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5_MASK                                          0x0060L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON_MASK                                   0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN_MASK                              0x0F00L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN_MASK                             0xF000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE__SHIFT                          0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE__SHIFT                                    0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM__SHIFT                                0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR__SHIFT                                0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF__SHIFT                                        0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9__SHIFT                                       0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE_MASK                            0x0003L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE_MASK                                      0x000CL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM_MASK                                  0x0030L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR_MASK                                  0x00C0L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF_MASK                                          0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9_MASK                                         0x7E00L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF__SHIFT                                    0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR__SHIFT                           0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL__SHIFT                                0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0_MASK                                      0x007FL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF_MASK                                      0x0180L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR_MASK                             0x7E00L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL_MASK                                  0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS__SHIFT                          0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC__SHIFT                            0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS__SHIFT                               0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4__SHIFT                                      0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG__SHIFT                                0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL__SHIFT                             0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE__SHIFT                             0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG__SHIFT                              0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL__SHIFT                                0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG__SHIFT                                 0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG__SHIFT                           0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET__SHIFT                              0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG__SHIFT                               0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0_MASK                                        0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS_MASK                            0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC_MASK                              0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS_MASK                                 0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4_MASK                                        0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG_MASK                                  0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL_MASK                               0x00C0L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE_MASK                               0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG_MASK                                0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL_MASK                                  0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG_MASK                                   0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG_MASK                             0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET_MASK                                0x4000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG_MASK                                 0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV__SHIFT                                 0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_MASK                                   0xFFFFL
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16__SHIFT                           0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT__SHIFT                              0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22__SHIFT                           0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16_MASK                             0x003FL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT_MASK                                0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22_MASK                             0x3F80L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN__SHIFT                      0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN__SHIFT                           0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW__SHIFT                              0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW__SHIFT                                   0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN__SHIFT                       0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG__SHIFT                            0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90__SHIFT                            0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN_MASK                        0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN_MASK                             0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW_MASK                                0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW_MASK                                     0x0FF8L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN_MASK                         0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG_MASK                              0x6000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90_MASK                              0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0__SHIFT                                     0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0_MASK                                       0xFFFFL
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0__SHIFT                                     0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0_MASK                                       0xFFFFL
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0__SHIFT                                  0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0_MASK                                    0x00FFL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT__SHIFT                       0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT__SHIFT                       0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV__SHIFT                           0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN__SHIFT                                  0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK__SHIFT                          0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6__SHIFT                                      0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS__SHIFT                          0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS__SHIFT                               0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT__SHIFT                          0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG__SHIFT                           0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR__SHIFT                          0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO__SHIFT                              0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV__SHIFT                             0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90__SHIFT                            0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT_MASK                         0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT_MASK                         0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV_MASK                             0x000CL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN_MASK                                    0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK_MASK                            0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6_MASK                                        0x00C0L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS_MASK                            0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS_MASK                                 0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT_MASK                            0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG_MASK                             0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR_MASK                            0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO_MASK                                0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV_MASK                               0x4000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90_MASK                              0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE__SHIFT                             0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG__SHIFT                              0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL__SHIFT                                0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG__SHIFT                                 0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN__SHIFT                          0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG__SHIFT                           0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET__SHIFT                              0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG__SHIFT                               0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP__SHIFT                            0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13__SHIFT                                    0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT__SHIFT                              0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE_MASK                               0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG_MASK                                0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL_MASK                                  0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG_MASK                                   0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN_MASK                            0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG_MASK                             0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET_MASK                                0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG_MASK                                 0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP_MASK                              0x1F00L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13_MASK                                      0x6000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT_MASK                                0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER__SHIFT                 0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ__SHIFT                       0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE__SHIFT                  0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED__SHIFT                       0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV__SHIFT                         0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H__SHIFT                         0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP__SHIFT                        0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP__SHIFT                    0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP__SHIFT                      0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP__SHIFT                       0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE__SHIFT                          0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER_MASK                   0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ_MASK                         0x0006L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE_MASK                    0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED_MASK                         0x00F0L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV_MASK                           0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H_MASK                           0x0600L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP_MASK                          0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP_MASK                      0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP_MASK                        0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP_MASK                         0x4000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE_MASK                            0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN__SHIFT                 0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN__SHIFT                         0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK__SHIFT                            0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5__SHIFT                                      0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8__SHIFT                                     0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START__SHIFT                     0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE__SHIFT                        0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST__SHIFT                             0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN_MASK                   0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN_MASK                           0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_MASK                              0x001CL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5_MASK                                        0x00E0L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8_MASK                                       0x0F00L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START_MASK                       0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE_MASK                          0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST_MASK                               0xC000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT__SHIFT                             0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW__SHIFT                         0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF__SHIFT                    0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS__SHIFT                               0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH__SHIFT                       0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN__SHIFT                           0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP__SHIFT                             0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO__SHIFT                            0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR__SHIFT                        0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING__SHIFT                           0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR__SHIFT                          0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF__SHIFT                    0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK__SHIFT                    0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG__SHIFT                        0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT_MASK                               0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW_MASK                           0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF_MASK                      0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS_MASK                                 0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH_MASK                         0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN_MASK                             0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP_MASK                               0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO_MASK                              0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR_MASK                          0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING_MASK                             0x0600L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR_MASK                            0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF_MASK                      0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK_MASK                      0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG_MASK                          0xC000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT__SHIFT                       0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING__SHIFT                        0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR__SHIFT                        0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2__SHIFT                    0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP__SHIFT                      0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED__SHIFT                       0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2__SHIFT                     0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X__SHIFT                               0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD__SHIFT                                 0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N__SHIFT                             0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC__SHIFT                           0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER__SHIFT                            0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT_MASK                         0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING_MASK                          0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR_MASK                          0x000CL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2_MASK                      0x0030L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP_MASK                        0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_MASK                         0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2_MASK                       0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X_MASK                                 0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD_MASK                                   0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N_MASK                               0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC_MASK                             0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER_MASK                              0xE000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF__SHIFT                          0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF__SHIFT                         0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL__SHIFT                          0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0__SHIFT                        0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH__SHIFT                         0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2__SHIFT                          0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES__SHIFT                             0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF_MASK                            0x0007L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF_MASK                           0x0038L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL_MASK                            0x00C0L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0_MASK                          0x0300L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH_MASK                           0x0C00L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2_MASK                            0x3000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES_MASK                               0xC000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG__SHIFT                            0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC__SHIFT                             0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL__SHIFT                         0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP__SHIFT                        0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK__SHIFT                          0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN__SHIFT                    0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST__SHIFT                              0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0_MASK                                        0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG_MASK                              0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC_MASK                               0x000CL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL_MASK                           0x0030L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP_MASK                          0x00C0L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK_MASK                            0x0F00L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN_MASK                      0x3000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST_MASK                                0xC000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                 0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                   0xFFFFL
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                 0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                   0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_CMN_CTL
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_CMN_CLK_GATE_CTL
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN__SHIFT                                                 0x2
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x5
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN__SHIFT                                                 0x6
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE__SHIFT                                              0x8
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x9
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ__SHIFT                                                    0xa
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0xb
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE__SHIFT                                           0xc
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_MASK                                                   0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_MASK                                                   0x0040L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_MASK                                                0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0200L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_MASK                                                      0x0400L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x0800L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE_MASK                                             0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0xE000L
+//C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME__SHIFT                                         0x6
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10__SHIFT                                             0xa
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME_MASK                                                0x003FL
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME_MASK                                           0x03C0L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10_MASK                                               0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_CTRL
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4__SHIFT                                             0x4
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE_MASK                                              0x000FL
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4_MASK                                               0xFFF0L
+//C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ADDR
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ADDR__ADDR__SHIFT                                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ADDR__ADDR_MASK                                                        0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_DATA
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_DATA__DATA__SHIFT                                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_DATA__DATA_MASK                                                        0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_FLAGS
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ACCUM
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ACCUM__VAL__SHIFT                                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ACCUM__VAL_MASK                                                        0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLL_IN
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN__SHIFT                                                   0x3
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__RESERVED_15_4__SHIFT                                                  0x4
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE_MASK                                           0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN_MASK                                                     0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__RESERVED_15_4_MASK                                                    0xFFF0L
+//C20_PHY_CR0_RAWCMN_DIG_FW_PWRUP_DONE
+#define C20_PHY_CR0_RAWCMN_DIG_FW_PWRUP_DONE__DONE__SHIFT                                                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR0_RAWCMN_DIG_FW_PWRUP_DONE__DONE_MASK                                                       0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_STATIC_CONFIG_STATUS
+#define C20_PHY_CR0_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE_MASK                                            0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS
+#define C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE__SHIFT                                          0x1
+#define C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE_MASK                                            0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE_MASK                                            0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2__SHIFT                                             0x2
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE_MASK                                               0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2_MASK                                               0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x2
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0x3
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0x4
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0x5
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x7
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x9
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0xa
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0xc
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL_MASK                       0x0003L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN_MASK                        0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK                       0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN_MASK                        0x0010L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK                        0x0020L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL_MASK                       0x0180L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN_MASK                        0x0200L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK                       0x0400L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK                        0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE__SHIFT                               0x1
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN_MASK                               0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE_MASK                                 0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE__SHIFT                               0x1
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN_MASK                               0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE_MASK                                 0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_CONFIG_MASTER_VERSION
+#define C20_PHY_CR0_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION_MASK                                     0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL
+#define C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN__SHIFT                              0x8
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN_MASK                                0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN__SHIFT                              0x8
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN_MASK                                0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11__SHIFT                                          0xb
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC_MASK                                                  0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL_MASK                                             0x0700L
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11_MASK                                            0xF800L
+//C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET__SHIFT                                        0x5
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14__SHIFT                                          0xe
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL_MASK                                              0x001FL
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET_MASK                                          0x3FE0L
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14_MASK                                            0xC000L
+//C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET__SHIFT                                        0x5
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14__SHIFT                                          0xe
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET_MASK                                            0x001FL
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET_MASK                                          0x3FE0L
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14_MASK                                            0xC000L
+//C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_3
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID__SHIFT                                               0x0
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10__SHIFT                                          0xa
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID_MASK                                                 0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10_MASK                                            0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN__SHIFT                                         0xf
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER_MASK                                              0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN_MASK                                              0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN_MASK                                           0x8000L
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV__SHIFT                                            0x8
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0xb
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD__SHIFT                                          0xe
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV_MASK                                              0x0700L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV_MASK                                            0x1800L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD_MASK                                            0xC000L
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_2
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_3
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH__SHIFT                                               0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH_MASK                                                 0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_4
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB_MASK                                            0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_5
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK                                       0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV__SHIFT                                     0xa
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL__SHIFT                                            0xd
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xe
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB_MASK                                            0x000FL
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK                                       0x01F0L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD_MASK                                           0x0200L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV_MASK                                       0x1C00L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL_MASK                                              0x2000L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN_MASK                                                 0x4000L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_7
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN_MASK                                                0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_8
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT_MASK                                               0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_9
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM_MASK                                                0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV__SHIFT                                            0xd
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER_MASK                                              0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN_MASK                                              0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV_MASK                                              0xE000L
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE__SHIFT                                          0xa
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV_MASK                                            0x0300L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE_MASK                                            0x7C00L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP__SHIFT                                               0x7
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO__SHIFT                                              0xe
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT_MASK                                                  0x007FL
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP_MASK                                                 0x3F80L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO_MASK                                                0xC000L
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS__SHIFT                                            0x7
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I__SHIFT                                                   0xe
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS_MASK                                               0x007FL
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS_MASK                                              0x3F80L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I_MASK                                                     0xC000L
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_4
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB_MASK                                            0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_5
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK                                       0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV__SHIFT                                     0xa
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xd
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB_MASK                                            0x000FL
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK                                       0x01F0L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD_MASK                                           0x0200L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV_MASK                                       0x1C00L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN_MASK                                                 0x2000L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_7
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN_MASK                                                0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_8
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT_MASK                                               0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_9
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM_MASK                                                0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV_MASK                                               0x0007L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV_MASK                                     0x0018L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN__SHIFT                                        0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN_MASK                                          0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3_MASK                                       0xFFF8L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0__SHIFT                           0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0_MASK                                  0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0_MASK                             0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1__SHIFT                           0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1_MASK                                  0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1_MASK                             0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2__SHIFT                           0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2_MASK                                  0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2_MASK                             0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3__SHIFT                           0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3_MASK                                  0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3_MASK                             0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL__SHIFT                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL_MASK                                0x0003L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_DONE
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0__SHIFT                           0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0_MASK                                  0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0_MASK                             0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1__SHIFT                           0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1_MASK                                  0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1_MASK                             0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2__SHIFT                           0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2_MASK                                  0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2_MASK                             0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3__SHIFT                           0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3_MASK                                  0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3_MASK                             0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL__SHIFT                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL_MASK                                0x0003L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_DONE
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12__SHIFT                                          0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE_MASK                                                0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12_MASK                                            0xF000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12__SHIFT                                          0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE_MASK                                                0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12_MASK                                            0xF000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_IN_RECAL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_IN_RECAL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                       0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6__SHIFT                                           0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                         0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                       0x0010L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6_MASK                                             0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO__SHIFT                                       0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                              0x4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                               0x5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                          0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO_MASK                                         0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                                0x0010L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                            0x8
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12__SHIFT                                         0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                      0x0010L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                              0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12_MASK                                           0xF000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN__SHIFT                                            0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN__SHIFT                                                0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                        0x4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK__SHIFT                                                0x5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN_MASK                                              0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN_MASK                                                  0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL_MASK                                          0x0010L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK_MASK                                                  0x0020L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6_MASK                                               0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                               0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                              0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                               0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL__SHIFT                                  0x4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN__SHIFT                                   0x5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL__SHIFT                                   0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL_MASK                                0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL_MASK                                0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN_MASK                                 0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL_MASK                                    0x0010L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN_MASK                                     0x0020L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL_MASK                                     0x0040L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK__SHIFT                                          0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4__SHIFT                                            0x4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK_MASK                                            0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK_MASK                                            0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4_MASK                                              0xFFF0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL_MASK                    0x0003L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL_MASK                    0x0003L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                                0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT__SHIFT                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE__SHIFT                              0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT_MASK                                0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE_MASK                                0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                        0x003FL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                    0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0_MASK                                  0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                        0x003FL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                    0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1_MASK                                  0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                        0x003FL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                    0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2_MASK                                  0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                        0x003FL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                    0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3_MASK                                  0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                        0x003FL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                    0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4_MASK                                  0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                        0x003FL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                    0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5_MASK                                  0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                        0x003FL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                    0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6_MASK                                  0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_7
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                        0x003FL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                    0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7_MASK                                  0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL__SHIFT                             0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL__SHIFT                             0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN__SHIFT                              0x4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL__SHIFT                         0x5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL_MASK                               0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL_MASK                               0x000CL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN_MASK                                0x0010L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL_MASK                           0x0060L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS_MASK                                         0x0018L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5_MASK                                                0xFFE0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OUT
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_0__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_0__VAL_MASK                                                     0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_1__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_1__VAL_MASK                                                     0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_AON_RAW_VERSION
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RAW_VERSION__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RAW_VERSION__VAL_MASK                                                      0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_EOF_ADDR
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_BOC_ADDR
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL__SHIFT                                     0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN__SHIFT                                      0x7
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10__SHIFT                                           0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL_MASK                                    0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL_MASK                                       0x0010L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL_MASK                                       0x0040L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN_MASK                                        0x0080L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10_MASK                                             0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL_MASK                                            0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN__SHIFT                                            0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN__SHIFT                                            0x4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE__SHIFT                                        0x5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE__SHIFT                                        0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL__SHIFT                                            0x9
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT__SHIFT                                         0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT__SHIFT                                         0xb
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF__SHIFT                                         0xd
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW__SHIFT                                          0xe
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN_MASK                                              0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN_MASK                                              0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN_MASK                                              0x0010L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE_MASK                                          0x0020L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE_MASK                                          0x0040L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ_MASK                                           0x0080L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ_MASK                                           0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL_MASK                                              0x0200L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT_MASK                                           0x0400L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT_MASK                                           0x0800L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL_MASK                                          0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF_MASK                                           0x2000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW_MASK                                            0x4000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL__SHIFT                            0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL_MASK                              0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_METADATA_LOCATION
+#define C20_PHY_CR0_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION_MASK                                  0x7FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST__SHIFT                         0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN__SHIFT                 0xf
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_MASK                           0x7FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN_MASK                   0x8000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR0_LANE0_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_LANE0_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR0_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR0_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR0_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL
+#define C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR0_LANE0_DIG_RX_LBERT_ERR
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR0_LANE1_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_LANE1_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR0_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR0_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR0_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL
+#define C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR0_LANE1_DIG_RX_LBERT_ERR
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR0_LANE2_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_LANE2_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR0_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR0_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR0_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL
+#define C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR0_LANE2_DIG_RX_LBERT_ERR
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR0_LANE3_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_LANE3_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR0_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR0_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR0_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL
+#define C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR0_LANE3_DIG_RX_LBERT_ERR
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_SUP
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_SUP
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_SUP
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_SUP
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_IN_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_IN_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_IN_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_IN_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR0_LANEX_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_LANEX_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR0_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR0_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR0_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL
+#define C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR0_LANEX_DIG_RX_LBERT_ERR
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_SUP
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_IN_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+
+
+// addressBlock: c20_phy_lane0_pipe0_rdpcspipemsgbusind
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK           0x02L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK                  0x04L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK                 0x08L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK             0x10L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK                           0xE0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK                      0x7FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK                   0x80L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK   0xFFL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK                               0x02L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK                            0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK                                  0x02L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK                                 0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK                         0x02L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK                           0x04L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK                                  0xF8L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK              0x02L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK                             0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                         0x40L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK                                  0x80L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK                            0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                    0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK                                  0x40L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK             0x80L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK                                 0x07L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK                                  0x08L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK                                  0xF0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                     0x40L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK                              0x80L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK                        0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK                       0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK                              0x40L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK         0x80L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK                             0x07L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK                              0x08L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK                              0xF0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK                  0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK                              0xFEL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK             0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK   0x1EL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK             0x20L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK                      0x40L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK                     0x80L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK                           0x03L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK                            0xFCL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK                         0x03L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK                             0xFCL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK                 0xFFL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK                            0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK                                0x02L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK                                0x04L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK                                     0xF8L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK                             0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK                                 0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK                               0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK                        0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK                             0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK                      0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK                      0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x03L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x0CL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x30L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK                       0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK  0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK  0x02L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK    0x04L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK    0x08L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK     0x10L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK                       0xE0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK    0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK    0x02L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK      0x04L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK      0x08L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK       0x10L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK                        0xE0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK          0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK          0x02L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK          0x04L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK          0x08L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK                    0x10L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK                            0xE0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK                      0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK                     0x02L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK                           0xFCL
+
+
+// addressBlock: c20_phy_lane1_pipe0_rdpcspipemsgbusind
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK           0x02L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK                  0x04L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK                 0x08L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK             0x10L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK                           0xE0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK                      0x7FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK                   0x80L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK   0xFFL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK                               0x02L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK                            0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK                                  0x02L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK                                 0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK                         0x02L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK                           0x04L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK                                  0xF8L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK              0x02L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK                             0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                         0x40L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK                                  0x80L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK                            0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                    0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK                                  0x40L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK             0x80L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK                                 0x07L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK                                  0x08L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK                                  0xF0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                     0x40L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK                              0x80L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK                        0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK                       0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK                              0x40L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK         0x80L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK                             0x07L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK                              0x08L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK                              0xF0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK                  0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK                              0xFEL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK             0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK   0x1EL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK             0x20L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK                      0x40L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK                     0x80L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK                           0x03L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK                            0xFCL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK                         0x03L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK                             0xFCL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK                 0xFFL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK                            0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK                                0x02L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK                                0x04L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK                                     0xF8L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK                             0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK                                 0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK                               0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK                        0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK                             0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK                      0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK                      0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x03L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x0CL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x30L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK                       0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK  0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK  0x02L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK    0x04L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK    0x08L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK     0x10L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK                       0xE0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK    0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK    0x02L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK      0x04L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK      0x08L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK       0x10L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK                        0xE0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK          0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK          0x02L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK          0x04L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK          0x08L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK                    0x10L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK                            0xE0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK                      0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK                     0x02L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK                           0xFCL
+
+
+// addressBlock: c20_phy_cr1_rdpcspipecrind
+//C20_PHY_CR1_SUP_DIG_IDCODE_LO
+#define C20_PHY_CR1_SUP_DIG_IDCODE_LO__VAL__SHIFT                                                             0x0
+#define C20_PHY_CR1_SUP_DIG_IDCODE_LO__VAL_MASK                                                               0xFFFFL
+//C20_PHY_CR1_SUP_DIG_IDCODE_HI
+#define C20_PHY_CR1_SUP_DIG_IDCODE_HI__VAL__SHIFT                                                             0x0
+#define C20_PHY_CR1_SUP_DIG_IDCODE_HI__VAL_MASK                                                               0xFFFFL
+//C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN__SHIFT                                          0x2
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN__SHIFT                                  0x3
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD__SHIFT                                              0x4
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE__SHIFT                                            0x6
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN__SHIFT                                                    0xa
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN__SHIFT                                            0xb
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD__SHIFT                                  0xc
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN__SHIFT                               0xd
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14__SHIFT                                           0xe
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_MASK                                                 0x0001L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_MASK                                            0x0004L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN_MASK                                    0x0008L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_MASK                                                0x0010L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_MASK                                              0x01C0L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_MASK                                                      0x0400L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN_MASK                                              0x0800L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_MASK                                    0x1000L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN_MASK                                 0x2000L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14_MASK                                             0xC000L
+//C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL__SHIFT                                          0x0
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL__SHIFT                                           0x3
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN__SHIFT                                   0x5
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN__SHIFT                                            0x6
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL__SHIFT                                       0x8
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                               0x9
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10__SHIFT                                           0xa
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_MASK                                            0x0003L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_MASK                                             0x0018L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN_MASK                                     0x0020L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_MASK                                              0x0040L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_MASK                                         0x0100L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10_MASK                                             0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x0200L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x0200L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                                     0x0
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN__SHIFT                             0x2
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                               0x3
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN__SHIFT                                       0x6
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE__SHIFT                                              0x7
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9__SHIFT                                                0x9
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                                       0x0003L
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN_MASK                               0x0004L
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_MASK                                                 0x0038L
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN_MASK                                         0x0040L
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_MASK                                                0x0080L
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9_MASK                                                  0xFE00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xd
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN__SHIFT                                             0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL_MASK                                           0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV_MASK                                           0x001CL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL_MASK                                 0x0060L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                   0x0E00L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                    0x1000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK                                        0x2000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS_MASK                                        0x4000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN_MASK                                               0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN__SHIFT                                          0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL__SHIFT                                          0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD_MASK                                          0x3000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN_MASK                                            0x4000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL_MASK                                            0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_OVRD_IN
+#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW_MASK                                           0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN
+#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH_MASK                                         0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN__SHIFT                                          0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x3
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0xd
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN_MASK                                            0x0004L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD_MASK                                     0x0008L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK                               0x03E0L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK                                0x0400L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK                      0x1000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK                                  0x2000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN_MASK                          0x4000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_3
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_4
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_5
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_6
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN__SHIFT                                             0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT                                            0xd
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL_MASK                                           0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV_MASK                                           0x001CL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL_MASK                                 0x0060L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                   0x0700L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN_MASK                                               0x1000L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK                                              0xE000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT__SHIFT                                          0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_MASK                                         0x007FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_MASK                                            0x7F00L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN_MASK                                    0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP__SHIFT                                         0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN__SHIFT                                 0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_MASK                                        0x007FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_MASK                                           0x7F00L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN_MASK                                   0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I__SHIFT                                             0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN__SHIFT                                     0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x3
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_MASK                                               0x0003L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN_MASK                                       0x0004L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_MASK                                          0x0018L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN__SHIFT                                          0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x3
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0xd
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN_MASK                                            0x0004L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD_MASK                                     0x0008L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK                               0x03E0L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK                                0x0400L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK                      0x1000L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK                                  0x2000L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN_MASK                          0x4000L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_3
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_5
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_6
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ__SHIFT                                                   0x0
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN__SHIFT                                               0x1
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN__SHIFT                                                  0x2
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN__SHIFT                                                  0x3
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN__SHIFT                                                 0x4
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7__SHIFT                                               0x7
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ_MASK                                                     0x0001L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN_MASK                                                 0x0002L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN_MASK                                                    0x0004L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN_MASK                                                    0x0008L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN_MASK                                                   0x0010L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7_MASK                                                 0xFF80L
+//C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET__SHIFT                                            0x0
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET__SHIFT                                              0xa
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN__SHIFT                                      0xf
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_MASK                                              0x01FFL
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_MASK                                                0x7C00L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN_MASK                                        0x8000L
+//C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET__SHIFT                                            0x0
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10__SHIFT                                              0xa
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_MASK                                              0x01FFL
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10_MASK                                                0xFC00L
+//C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT                                                  0x2
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT                                                  0x4
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x6
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x7
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x9
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD__SHIFT                                           0xa
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0xb
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD__SHIFT                                            0xc
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0xd
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14__SHIFT                                               0xe
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x0001L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK                                                    0x0004L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK                                                    0x0010L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x0040L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x0080L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x0100L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x0200L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_MASK                                             0x0400L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x0800L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_MASK                                              0x1000L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x2000L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14_MASK                                                 0xC000L
+//C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN
+#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x6
+#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN__SHIFT                                         0x9
+#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
+#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x001FL
+#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x01C0L
+#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN_MASK                                           0x0200L
+#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK                                                  0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV__SHIFT                                        0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xb
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14__SHIFT                                            0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV_MASK                                           0x000EL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV_MASK                                          0x0030L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0380L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK                                        0x0400L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS_MASK                                        0x0800L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD_MASK                                          0x3000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14_MASK                                              0xC000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_ASIC_IN
+#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW_MASK                                           0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN
+#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH_MASK                                         0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x3
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD_MASK                                     0x0004L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK                               0x00F8L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK                                0x0100L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK                                  0x0200L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_3
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_4
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_5
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_6
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV__SHIFT                                        0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x6
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9__SHIFT                                             0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV_MASK                                           0x000EL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV_MASK                                          0x0030L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x01C0L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9_MASK                                               0xFE00L
+//C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT__SHIFT                                          0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS_MASK                                         0x007FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_MASK                                            0x3F80L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP__SHIFT                                         0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS_MASK                                        0x007FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_MASK                                           0x3F80L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I__SHIFT                                             0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I_MASK                                               0x0003L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO_MASK                                          0x000CL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x3
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD_MASK                                     0x0004L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK                               0x00F8L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK                                0x0100L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK                                  0x0200L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_3
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_5
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_6
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                            0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                      0xb
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14__SHIFT                                      0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                              0x0600L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                        0x3800L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14_MASK                                        0xC000L
+//C20_PHY_CR1_SUP_DIG_ASIC_IN_0
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__PHY_RESET__SHIFT                                                       0x0
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_CLK_EN__SHIFT                                                      0x1
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN__SHIFT                                                 0x2
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_USE_PAD__SHIFT                                                     0x3
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__TEST_BURNIN__SHIFT                                                     0x4
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN__SHIFT                                                  0x5
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RTUNE_REQ__SHIFT                                                       0x6
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RES_REQ_IN__SHIFT                                                      0x7
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RES_ACK_IN__SHIFT                                                      0x8
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__BG_EN__SHIFT                                                           0x9
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                              0xa
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_RANGE__SHIFT                                                       0xb
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE__SHIFT                                                 0xe
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RESERVED_15_15__SHIFT                                                  0xf
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__PHY_RESET_MASK                                                         0x0001L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_CLK_EN_MASK                                                        0x0002L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN_MASK                                                   0x0004L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_USE_PAD_MASK                                                       0x0008L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__TEST_BURNIN_MASK                                                       0x0010L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN_MASK                                                    0x0020L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RTUNE_REQ_MASK                                                         0x0040L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RES_REQ_IN_MASK                                                        0x0080L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RES_ACK_IN_MASK                                                        0x0100L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__BG_EN_MASK                                                             0x0200L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL_MASK                                                0x0400L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_RANGE_MASK                                                         0x3800L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE_MASK                                                   0x4000L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RESERVED_15_15_MASK                                                    0x8000L
+//C20_PHY_CR1_SUP_DIG_ASIC_IN_1
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__SUP_MISC__SHIFT                                                        0x0
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN__SHIFT                                                0x8
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN__SHIFT                                              0x9
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL__SHIFT                                                 0xa
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL__SHIFT                                                  0xc
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__RESERVED_15_14__SHIFT                                                  0xe
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__SUP_MISC_MASK                                                          0x00FFL
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN_MASK                                                  0x0100L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN_MASK                                                0x0200L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL_MASK                                                   0x0C00L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL_MASK                                                    0x3000L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__RESERVED_15_14_MASK                                                    0xC000L
+//C20_PHY_CR1_SUP_DIG_ASIC_OUT_0
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT__SHIFT                                              0x0
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__MPLLA_STATE__SHIFT                                                    0x1
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__MPLLB_STATE__SHIFT                                                    0x2
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RTUNE_ACK__SHIFT                                                      0x3
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT__SHIFT                                                    0x4
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT__SHIFT                                                    0x5
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__DTB_OUT__SHIFT                                                        0x6
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RESERVED_15_8__SHIFT                                                  0x8
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT_MASK                                                0x0001L
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__MPLLA_STATE_MASK                                                      0x0002L
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__MPLLB_STATE_MASK                                                      0x0004L
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RTUNE_ACK_MASK                                                        0x0008L
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT_MASK                                                      0x0010L
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT_MASK                                                      0x0020L
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__DTB_OUT_MASK                                                          0x00C0L
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RESERVED_15_8_MASK                                                    0xFF00L
+//C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN
+#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x5
+#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN__SHIFT                                                 0x8
+#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET__SHIFT                                                0x9
+#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14__SHIFT                                                0xe
+#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x001FL
+#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x00E0L
+#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN_MASK                                                   0x0100L
+#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET_MASK                                                  0x3E00L
+#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14_MASK                                                  0xC000L
+//C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN__SHIFT                                            0x8
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9__SHIFT                                               0x9
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN_MASK                                              0x0100L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9_MASK                                                 0xFE00L
+//C20_PHY_CR1_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN
+#define C20_PHY_CR1_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET__SHIFT                                 0x0
+#define C20_PHY_CR1_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET_MASK                                   0x01FFL
+#define C20_PHY_CR1_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN
+#define C20_PHY_CR1_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET__SHIFT                                 0x0
+#define C20_PHY_CR1_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET_MASK                                   0x01FFL
+#define C20_PHY_CR1_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL__SHIFT                                0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL__SHIFT                                  0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL__SHIFT                             0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10__SHIFT                                          0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL_MASK                                  0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL_MASK                                    0x0004L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL_MASK                               0x01F0L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10_MASK                                            0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY__SHIFT                                           0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE__SHIFT                                      0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7__SHIFT                                           0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE_MASK                                           0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY_MASK                                             0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE_MASK                                        0x007CL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7_MASK                                             0xFF80L
+//C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED__SHIFT                                                     0x1
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL__SHIFT                                                0x6
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7__SHIFT                                                0x7
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x0001L
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED_MASK                                                       0x0002L
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x0004L
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x0038L
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL_MASK                                                  0x0040L
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7_MASK                                                  0xFF80L
+//C20_PHY_CR1_SUP_DIG_RTUNE_STAT
+#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__RTUNE_STATE__SHIFT                                                    0xa
+#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE__SHIFT                                                 0xd
+#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__RESERVED_15_15__SHIFT                                                 0xf
+#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x03FFL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__RTUNE_STATE_MASK                                                      0x1C00L
+#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE_MASK                                                   0x6000L
+#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__RESERVED_15_15_MASK                                                   0x8000L
+//C20_PHY_CR1_SUP_DIG_RTUNE_RX_SET_VAL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
+#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x003FL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0xFFC0L
+//C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x03FFL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x03FFL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR1_SUP_DIG_RTUNE_RX_STAT
+#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x003FL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_STAT
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x03FFL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0xFC00L
+//C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_STAT
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x03FFL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0xFC00L
+//C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG__SHIFT                                                  0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10__SHIFT                                       0xa
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG_MASK                                                    0x03FFL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10_MASK                                         0xFC00L
+//C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_1
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN__SHIFT                                                 0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10__SHIFT                                       0xa
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN_MASK                                                   0x03FFL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10_MASK                                         0xFC00L
+//C20_PHY_CR1_SUP_DIG_RTUNE_FAST_FLAGS
+#define C20_PHY_CR1_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE__SHIFT                                               0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR1_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE_MASK                                                 0x0001L
+#define C20_PHY_CR1_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER__SHIFT                                  0xa
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11__SHIFT                                    0xb
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x01FFL
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x0200L
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER_MASK                                    0x0400L
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11_MASK                                      0xF800L
+//C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x01FFL
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x00FFL
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x001FL
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x0020L
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE__SHIFT                                     0x1
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE__SHIFT                                     0x2
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE__SHIFT                                      0x4
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6__SHIFT                                     0x6
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE_MASK                                        0x0001L
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE_MASK                                       0x0002L
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE_MASK                                       0x000CL
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE_MASK                                        0x0030L
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6_MASK                                       0xFFC0L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL__SHIFT                                0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL__SHIFT                                 0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN__SHIFT                               0x6
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE__SHIFT                             0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE__SHIFT                                0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT_MASK                                      0x000FL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL_MASK                                  0x0010L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL_MASK                                   0x0020L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE_MASK                               0x7F80L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE_MASK                                  0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE__SHIFT                               0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14__SHIFT                              0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK                                      0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK                              0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK                               0x0008L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK                                0x0010L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE_MASK                                 0x3C00L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14_MASK                                0xC000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                                      0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                                       0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                                      0x6
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xd
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP__SHIFT                             0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                                        0x0010L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                                         0x0020L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                                        0x0040L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0080L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0100L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0200L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x1000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x2000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x4000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP_MASK                               0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME__SHIFT               0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME__SHIFT                 0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME_MASK                 0x03FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME_MASK                   0x3C00L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK                         0xC000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME__SHIFT           0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME__SHIFT                         0xb
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME_MASK             0x07FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME_MASK                           0xF800L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME__SHIFT                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME__SHIFT                  0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME__SHIFT               0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME_MASK                          0x001FL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME_MASK                    0x03E0L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME_MASK                 0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME__SHIFT                  0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME__SHIFT                0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME_MASK                    0x007FL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME_MASK                  0x0F80L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT                     0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL__SHIFT                       0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12__SHIFT                           0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK                       0x00FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL_MASK                         0x0F00L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12_MASK                             0xF000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT             0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP__SHIFT          0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG__SHIFT         0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK               0x00FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP_MASK            0x0300L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG_MASK           0x0C00L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0__SHIFT                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0__SHIFT                      0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0_MASK                        0x00FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0_MASK                        0xFF00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1__SHIFT                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1__SHIFT                      0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1_MASK                        0x00FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1_MASK                        0xFF00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2__SHIFT                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2__SHIFT                      0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2_MASK                        0x00FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2_MASK                        0xFF00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3__SHIFT                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3__SHIFT                      0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3_MASK                        0x00FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3_MASK                        0xFF00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME__SHIFT         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME__SHIFT                   0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME_MASK           0x03FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME_MASK                     0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME__SHIFT     0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11__SHIFT                       0xb
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME_MASK       0x07FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11_MASK                         0xF800L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME__SHIFT              0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10__SHIFT                       0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME_MASK                0x03FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10_MASK                         0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME__SHIFT             0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10__SHIFT                       0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME_MASK               0x03FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10_MASK                         0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7__SHIFT                        0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME_MASK                 0x007FL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7_MASK                          0xFF80L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN__SHIFT                 0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2__SHIFT                               0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN_MASK                   0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2_MASK                                 0xFFFCL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_FRAC_OUT
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_SSC_RAMP
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK                                          0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK                                           0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN__SHIFT                            0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE__SHIFT                                   0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL_MASK                             0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN_MASK                              0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE_MASK                                     0x007CL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK                                      0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK                              0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK                               0x0008L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK                                0x0010L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC__SHIFT                                 0xd
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC__SHIFT                                 0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0010L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0020L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0100L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x0200L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x0400L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x0800L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x1000L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC_MASK                                   0x2000L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC_MASK                                   0x4000L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME__SHIFT                          0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME_MASK                              0x00FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME_MASK                            0x3F00L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK                         0xC000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME__SHIFT                       0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME__SHIFT                          0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME_MASK                         0x00FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME_MASK                            0xFF00L
+//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME__SHIFT                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME__SHIFT                         0x6
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME_MASK                        0x003FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME_MASK                           0x0FC0L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME__SHIFT                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME__SHIFT                           0x6
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME_MASK                          0x003FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME_MASK                             0x0FC0L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS__SHIFT                0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS_MASK                  0x001FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7__SHIFT                        0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME_MASK                 0x007FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7_MASK                          0xFF80L
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_FRAC_OUT
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_SSC_RAMP
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK                                          0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK                                           0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT__SHIFT                                      0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK__SHIFT                                             0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC__SHIFT                                              0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT__SHIFT                                          0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL__SHIFT                                         0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10__SHIFT                                             0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT_MASK                                           0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT_MASK                                        0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK_MASK                                               0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC_MASK                                                0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT_MASK                                            0x01F0L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL_MASK                                           0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10_MASK                                               0xFC00L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN__SHIFT                                                 0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START__SHIFT                                    0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN__SHIFT                                            0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL__SHIFT                                      0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START__SHIFT                                   0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL__SHIFT                                         0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN__SHIFT                                                 0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST__SHIFT                                           0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE__SHIFT                                               0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST__SHIFT                                             0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN_MASK                                                   0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START_MASK                                      0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN_MASK                                              0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL_MASK                                        0x0030L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START_MASK                                     0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL_MASK                                           0x0380L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN_MASK                                                   0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST_MASK                                             0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE_MASK                                                 0x3000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST_MASK                                               0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP__SHIFT                              0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL__SHIFT                                       0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST__SHIFT                                       0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT__SHIFT                                 0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN__SHIFT                                 0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN__SHIFT                                   0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN__SHIFT                               0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN__SHIFT                               0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN__SHIFT                                0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN__SHIFT                            0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12__SHIFT                                      0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP_MASK                                0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL_MASK                                         0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST_MASK                                         0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT_MASK                                   0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN_MASK                                   0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN_MASK                                     0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN_MASK                              0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12_MASK                                        0xF000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL__SHIFT                                       0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST__SHIFT                                       0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT__SHIFT                                 0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN__SHIFT                               0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN__SHIFT                               0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN__SHIFT                               0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN__SHIFT                                0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN__SHIFT                           0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE__SHIFT                                 0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY__SHIFT                                   0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14__SHIFT                                      0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_MASK                                         0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST_MASK                                         0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT_MASK                                   0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN_MASK                             0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE_MASK                                   0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY_MASK                                     0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14_MASK                                        0xC000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN__SHIFT                                                  0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START__SHIFT                                          0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN__SHIFT                                  0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START__SHIFT                                          0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN__SHIFT                                  0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER__SHIFT                                0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP__SHIFT                                0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                          0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_MASK                                                    0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_MASK                                            0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN_MASK                                    0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_MASK                                            0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN_MASK                                    0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER_MASK                                  0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP_MASK                                  0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                            0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                      0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                              0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                   0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                           0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE__SHIFT                                  0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_MASK                                        0x000CL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_MASK                                     0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                             0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE_MASK                                       0x0180L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE_MASK                                    0x7E00L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL__SHIFT                                   0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL__SHIFT                                0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL_MASK                                      0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL_MASK                                     0x0006L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL_MASK                                  0x0018L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP__SHIFT                            0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                    0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN__SHIFT                            0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                         0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                         0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT__SHIFT                               0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                        0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_MASK                              0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                      0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN_MASK                              0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                           0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                           0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_MASK                                 0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN__SHIFT                                 0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN__SHIFT                              0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN__SHIFT                      0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN__SHIFT                            0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN__SHIFT                    0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN__SHIFT                            0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN__SHIFT                                  0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN__SHIFT                          0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN__SHIFT                              0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_MASK                                   0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN_MASK                           0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN_MASK                           0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_MASK                                0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN_MASK                        0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_MASK                              0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN_MASK                      0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_MASK                              0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN_MASK                           0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_MASK                                    0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN_MASK                            0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_MASK                                0x4000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN__SHIFT                                0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN_MASK                        0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK                                  0xFFF0L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC__SHIFT                              0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT__SHIFT                               0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC_MASK                                0x003FL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT_MASK                                 0xFFC0L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                         0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                         0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT__SHIFT                                   0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE__SHIFT                                   0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                     0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                        0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                           0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                           0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_MASK                                     0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_MASK                                     0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                       0x4000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN__SHIFT                                 0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN__SHIFT                                0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                        0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN__SHIFT                         0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN__SHIFT                             0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_MASK                                   0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN_MASK                           0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN_MASK                           0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                          0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN_MASK                           0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_MASK                               0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN__SHIFT                                0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN_MASK                        0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK                                  0xFFF0L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC__SHIFT                              0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT__SHIFT                               0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC_MASK                                0x003FL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT_MASK                                 0xFFC0L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                            0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                      0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                          0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                         0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                       0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                              0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                        0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                            0x000CL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                           0x3FF0L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                         0x4000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC__SHIFT                                          0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_MASK                                            0x00FFL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE__SHIFT                            0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN__SHIFT                    0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE__SHIFT                              0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN__SHIFT                      0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_MASK                              0x00FFL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN_MASK                      0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_MASK                                0x1E00L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN_MASK                        0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG__SHIFT                                   0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1__SHIFT                                        0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT__SHIFT                                  0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START__SHIFT                             0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG__SHIFT                              0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST__SHIFT                                  0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT__SHIFT                            0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG__SHIFT                                   0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2__SHIFT                           0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7__SHIFT                                0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST__SHIFT                           0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT__SHIFT                                 0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX__SHIFT                             0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_MASK                                     0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1_MASK                                          0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT_MASK                                    0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START_MASK                               0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG_MASK                                0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST_MASK                                    0x0060L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT_MASK                              0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG_MASK                                     0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2_MASK                             0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7_MASK                                  0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST_MASK                             0x1800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT_MASK                                   0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX_MASK                               0xC000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX__SHIFT                             0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0__SHIFT                         0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6__SHIFT                                        0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0__SHIFT                              0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS__SHIFT                                   0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST_MASK                                      0x0003L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX_MASK                               0x000CL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0_MASK                           0x0030L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6_MASK                                          0x00C0L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0_MASK                                0x7F00L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS_MASK                                     0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF__SHIFT                                 0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP__SHIFT                                 0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB__SHIFT                                      0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP__SHIFT                                 0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE__SHIFT                                 0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5__SHIFT                                        0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON__SHIFT                                 0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN__SHIFT                            0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN__SHIFT                           0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF_MASK                                   0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP_MASK                                   0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB_MASK                                        0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP_MASK                                   0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE_MASK                                   0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5_MASK                                          0x0060L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON_MASK                                   0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN_MASK                              0x0F00L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN_MASK                             0xF000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE__SHIFT                          0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE__SHIFT                                    0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM__SHIFT                                0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR__SHIFT                                0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF__SHIFT                                        0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9__SHIFT                                       0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE_MASK                            0x0003L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE_MASK                                      0x000CL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM_MASK                                  0x0030L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR_MASK                                  0x00C0L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF_MASK                                          0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9_MASK                                         0x7E00L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF__SHIFT                                    0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR__SHIFT                           0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL__SHIFT                                0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0_MASK                                      0x007FL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF_MASK                                      0x0180L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR_MASK                             0x7E00L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL_MASK                                  0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS__SHIFT                          0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC__SHIFT                            0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS__SHIFT                               0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4__SHIFT                                      0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG__SHIFT                                0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL__SHIFT                             0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE__SHIFT                             0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG__SHIFT                              0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL__SHIFT                                0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG__SHIFT                                 0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG__SHIFT                           0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET__SHIFT                              0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG__SHIFT                               0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0_MASK                                        0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS_MASK                            0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC_MASK                              0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS_MASK                                 0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4_MASK                                        0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG_MASK                                  0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL_MASK                               0x00C0L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE_MASK                               0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG_MASK                                0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL_MASK                                  0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG_MASK                                   0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG_MASK                             0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET_MASK                                0x4000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG_MASK                                 0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV__SHIFT                                 0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_MASK                                   0xFFFFL
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16__SHIFT                           0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT__SHIFT                              0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22__SHIFT                           0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16_MASK                             0x003FL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT_MASK                                0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22_MASK                             0x3F80L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN__SHIFT                      0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN__SHIFT                           0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW__SHIFT                              0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW__SHIFT                                   0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN__SHIFT                       0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG__SHIFT                            0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90__SHIFT                            0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN_MASK                        0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN_MASK                             0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW_MASK                                0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW_MASK                                     0x0FF8L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN_MASK                         0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG_MASK                              0x6000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90_MASK                              0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0__SHIFT                                     0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0_MASK                                       0xFFFFL
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0__SHIFT                                     0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0_MASK                                       0xFFFFL
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0__SHIFT                                  0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0_MASK                                    0x00FFL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT__SHIFT                       0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT__SHIFT                       0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV__SHIFT                           0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN__SHIFT                                  0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK__SHIFT                          0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6__SHIFT                                      0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS__SHIFT                          0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS__SHIFT                               0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT__SHIFT                          0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG__SHIFT                           0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR__SHIFT                          0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO__SHIFT                              0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV__SHIFT                             0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90__SHIFT                            0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT_MASK                         0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT_MASK                         0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV_MASK                             0x000CL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN_MASK                                    0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK_MASK                            0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6_MASK                                        0x00C0L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS_MASK                            0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS_MASK                                 0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT_MASK                            0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG_MASK                             0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR_MASK                            0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO_MASK                                0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV_MASK                               0x4000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90_MASK                              0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE__SHIFT                             0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG__SHIFT                              0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL__SHIFT                                0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG__SHIFT                                 0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN__SHIFT                          0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG__SHIFT                           0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET__SHIFT                              0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG__SHIFT                               0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP__SHIFT                            0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13__SHIFT                                    0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT__SHIFT                              0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE_MASK                               0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG_MASK                                0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL_MASK                                  0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG_MASK                                   0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN_MASK                            0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG_MASK                             0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET_MASK                                0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG_MASK                                 0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP_MASK                              0x1F00L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13_MASK                                      0x6000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT_MASK                                0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER__SHIFT                 0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ__SHIFT                       0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE__SHIFT                  0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED__SHIFT                       0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV__SHIFT                         0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H__SHIFT                         0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP__SHIFT                        0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP__SHIFT                    0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP__SHIFT                      0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP__SHIFT                       0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE__SHIFT                          0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER_MASK                   0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ_MASK                         0x0006L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE_MASK                    0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED_MASK                         0x00F0L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV_MASK                           0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H_MASK                           0x0600L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP_MASK                          0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP_MASK                      0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP_MASK                        0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP_MASK                         0x4000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE_MASK                            0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN__SHIFT                 0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN__SHIFT                         0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK__SHIFT                            0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5__SHIFT                                      0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8__SHIFT                                     0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START__SHIFT                     0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE__SHIFT                        0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST__SHIFT                             0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN_MASK                   0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN_MASK                           0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_MASK                              0x001CL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5_MASK                                        0x00E0L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8_MASK                                       0x0F00L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START_MASK                       0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE_MASK                          0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST_MASK                               0xC000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT__SHIFT                             0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW__SHIFT                         0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF__SHIFT                    0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS__SHIFT                               0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH__SHIFT                       0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN__SHIFT                           0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP__SHIFT                             0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO__SHIFT                            0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR__SHIFT                        0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING__SHIFT                           0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR__SHIFT                          0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF__SHIFT                    0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK__SHIFT                    0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG__SHIFT                        0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT_MASK                               0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW_MASK                           0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF_MASK                      0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS_MASK                                 0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH_MASK                         0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN_MASK                             0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP_MASK                               0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO_MASK                              0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR_MASK                          0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING_MASK                             0x0600L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR_MASK                            0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF_MASK                      0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK_MASK                      0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG_MASK                          0xC000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT__SHIFT                       0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING__SHIFT                        0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR__SHIFT                        0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2__SHIFT                    0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP__SHIFT                      0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED__SHIFT                       0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2__SHIFT                     0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X__SHIFT                               0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD__SHIFT                                 0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N__SHIFT                             0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC__SHIFT                           0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER__SHIFT                            0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT_MASK                         0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING_MASK                          0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR_MASK                          0x000CL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2_MASK                      0x0030L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP_MASK                        0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_MASK                         0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2_MASK                       0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X_MASK                                 0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD_MASK                                   0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N_MASK                               0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC_MASK                             0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER_MASK                              0xE000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF__SHIFT                          0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF__SHIFT                         0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL__SHIFT                          0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0__SHIFT                        0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH__SHIFT                         0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2__SHIFT                          0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES__SHIFT                             0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF_MASK                            0x0007L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF_MASK                           0x0038L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL_MASK                            0x00C0L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0_MASK                          0x0300L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH_MASK                           0x0C00L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2_MASK                            0x3000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES_MASK                               0xC000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG__SHIFT                            0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC__SHIFT                             0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL__SHIFT                         0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP__SHIFT                        0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK__SHIFT                          0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN__SHIFT                    0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST__SHIFT                              0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0_MASK                                        0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG_MASK                              0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC_MASK                               0x000CL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL_MASK                           0x0030L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP_MASK                          0x00C0L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK_MASK                            0x0F00L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN_MASK                      0x3000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST_MASK                                0xC000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                 0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                   0xFFFFL
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                 0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                   0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_CMN_CTL
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_CMN_CLK_GATE_CTL
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN__SHIFT                                                 0x2
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x5
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN__SHIFT                                                 0x6
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE__SHIFT                                              0x8
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x9
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ__SHIFT                                                    0xa
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0xb
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE__SHIFT                                           0xc
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_MASK                                                   0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_MASK                                                   0x0040L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_MASK                                                0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0200L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_MASK                                                      0x0400L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x0800L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE_MASK                                             0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0xE000L
+//C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME__SHIFT                                         0x6
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10__SHIFT                                             0xa
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME_MASK                                                0x003FL
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME_MASK                                           0x03C0L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10_MASK                                               0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_CTRL
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4__SHIFT                                             0x4
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE_MASK                                              0x000FL
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4_MASK                                               0xFFF0L
+//C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ADDR
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ADDR__ADDR__SHIFT                                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ADDR__ADDR_MASK                                                        0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_DATA
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_DATA__DATA__SHIFT                                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_DATA__DATA_MASK                                                        0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_FLAGS
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ACCUM
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ACCUM__VAL__SHIFT                                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ACCUM__VAL_MASK                                                        0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLL_IN
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN__SHIFT                                                   0x3
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__RESERVED_15_4__SHIFT                                                  0x4
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE_MASK                                           0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN_MASK                                                     0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__RESERVED_15_4_MASK                                                    0xFFF0L
+//C20_PHY_CR1_RAWCMN_DIG_FW_PWRUP_DONE
+#define C20_PHY_CR1_RAWCMN_DIG_FW_PWRUP_DONE__DONE__SHIFT                                                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR1_RAWCMN_DIG_FW_PWRUP_DONE__DONE_MASK                                                       0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_STATIC_CONFIG_STATUS
+#define C20_PHY_CR1_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE_MASK                                            0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS
+#define C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE__SHIFT                                          0x1
+#define C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE_MASK                                            0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE_MASK                                            0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2__SHIFT                                             0x2
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE_MASK                                               0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2_MASK                                               0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x2
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0x3
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0x4
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0x5
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x7
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x9
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0xa
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0xc
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL_MASK                       0x0003L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN_MASK                        0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK                       0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN_MASK                        0x0010L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK                        0x0020L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL_MASK                       0x0180L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN_MASK                        0x0200L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK                       0x0400L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK                        0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE__SHIFT                               0x1
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN_MASK                               0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE_MASK                                 0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE__SHIFT                               0x1
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN_MASK                               0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE_MASK                                 0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_CONFIG_MASTER_VERSION
+#define C20_PHY_CR1_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION_MASK                                     0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL
+#define C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN__SHIFT                              0x8
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN_MASK                                0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN__SHIFT                              0x8
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN_MASK                                0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11__SHIFT                                          0xb
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC_MASK                                                  0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL_MASK                                             0x0700L
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11_MASK                                            0xF800L
+//C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET__SHIFT                                        0x5
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14__SHIFT                                          0xe
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL_MASK                                              0x001FL
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET_MASK                                          0x3FE0L
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14_MASK                                            0xC000L
+//C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET__SHIFT                                        0x5
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14__SHIFT                                          0xe
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET_MASK                                            0x001FL
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET_MASK                                          0x3FE0L
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14_MASK                                            0xC000L
+//C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_3
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID__SHIFT                                               0x0
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10__SHIFT                                          0xa
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID_MASK                                                 0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10_MASK                                            0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN__SHIFT                                         0xf
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER_MASK                                              0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN_MASK                                              0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN_MASK                                           0x8000L
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV__SHIFT                                            0x8
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0xb
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD__SHIFT                                          0xe
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV_MASK                                              0x0700L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV_MASK                                            0x1800L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD_MASK                                            0xC000L
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_2
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_3
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH__SHIFT                                               0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH_MASK                                                 0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_4
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB_MASK                                            0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_5
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK                                       0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV__SHIFT                                     0xa
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL__SHIFT                                            0xd
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xe
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB_MASK                                            0x000FL
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK                                       0x01F0L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD_MASK                                           0x0200L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV_MASK                                       0x1C00L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL_MASK                                              0x2000L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN_MASK                                                 0x4000L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_7
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN_MASK                                                0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_8
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT_MASK                                               0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_9
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM_MASK                                                0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV__SHIFT                                            0xd
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER_MASK                                              0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN_MASK                                              0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV_MASK                                              0xE000L
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE__SHIFT                                          0xa
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV_MASK                                            0x0300L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE_MASK                                            0x7C00L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP__SHIFT                                               0x7
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO__SHIFT                                              0xe
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT_MASK                                                  0x007FL
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP_MASK                                                 0x3F80L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO_MASK                                                0xC000L
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS__SHIFT                                            0x7
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I__SHIFT                                                   0xe
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS_MASK                                               0x007FL
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS_MASK                                              0x3F80L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I_MASK                                                     0xC000L
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_4
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB_MASK                                            0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_5
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK                                       0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV__SHIFT                                     0xa
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xd
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB_MASK                                            0x000FL
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK                                       0x01F0L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD_MASK                                           0x0200L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV_MASK                                       0x1C00L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN_MASK                                                 0x2000L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_7
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN_MASK                                                0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_8
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT_MASK                                               0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_9
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM_MASK                                                0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV_MASK                                               0x0007L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV_MASK                                     0x0018L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN__SHIFT                                        0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN_MASK                                          0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3_MASK                                       0xFFF8L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0__SHIFT                           0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0_MASK                                  0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0_MASK                             0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1__SHIFT                           0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1_MASK                                  0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1_MASK                             0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2__SHIFT                           0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2_MASK                                  0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2_MASK                             0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3__SHIFT                           0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3_MASK                                  0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3_MASK                             0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL__SHIFT                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL_MASK                                0x0003L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_DONE
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0__SHIFT                           0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0_MASK                                  0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0_MASK                             0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1__SHIFT                           0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1_MASK                                  0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1_MASK                             0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2__SHIFT                           0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2_MASK                                  0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2_MASK                             0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3__SHIFT                           0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3_MASK                                  0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3_MASK                             0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL__SHIFT                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL_MASK                                0x0003L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_DONE
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12__SHIFT                                          0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE_MASK                                                0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12_MASK                                            0xF000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12__SHIFT                                          0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE_MASK                                                0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12_MASK                                            0xF000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_IN_RECAL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_IN_RECAL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                       0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6__SHIFT                                           0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                         0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                       0x0010L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6_MASK                                             0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO__SHIFT                                       0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                              0x4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                               0x5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                          0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO_MASK                                         0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                                0x0010L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                            0x8
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12__SHIFT                                         0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                      0x0010L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                              0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12_MASK                                           0xF000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN__SHIFT                                            0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN__SHIFT                                                0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                        0x4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK__SHIFT                                                0x5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN_MASK                                              0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN_MASK                                                  0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL_MASK                                          0x0010L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK_MASK                                                  0x0020L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6_MASK                                               0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                               0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                              0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                               0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL__SHIFT                                  0x4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN__SHIFT                                   0x5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL__SHIFT                                   0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL_MASK                                0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL_MASK                                0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN_MASK                                 0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL_MASK                                    0x0010L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN_MASK                                     0x0020L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL_MASK                                     0x0040L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK__SHIFT                                          0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4__SHIFT                                            0x4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK_MASK                                            0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK_MASK                                            0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4_MASK                                              0xFFF0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL_MASK                    0x0003L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL_MASK                    0x0003L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                                0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT__SHIFT                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE__SHIFT                              0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT_MASK                                0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE_MASK                                0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                        0x003FL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                    0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0_MASK                                  0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                        0x003FL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                    0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1_MASK                                  0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                        0x003FL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                    0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2_MASK                                  0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                        0x003FL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                    0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3_MASK                                  0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                        0x003FL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                    0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4_MASK                                  0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                        0x003FL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                    0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5_MASK                                  0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                        0x003FL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                    0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6_MASK                                  0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_7
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                        0x003FL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                    0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7_MASK                                  0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL__SHIFT                             0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL__SHIFT                             0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN__SHIFT                              0x4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL__SHIFT                         0x5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL_MASK                               0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL_MASK                               0x000CL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN_MASK                                0x0010L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL_MASK                           0x0060L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS_MASK                                         0x0018L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5_MASK                                                0xFFE0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OUT
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_0__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_0__VAL_MASK                                                     0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_1__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_1__VAL_MASK                                                     0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_AON_RAW_VERSION
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RAW_VERSION__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RAW_VERSION__VAL_MASK                                                      0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_EOF_ADDR
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_BOC_ADDR
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL__SHIFT                                     0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN__SHIFT                                      0x7
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10__SHIFT                                           0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL_MASK                                    0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL_MASK                                       0x0010L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL_MASK                                       0x0040L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN_MASK                                        0x0080L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10_MASK                                             0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL_MASK                                            0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN__SHIFT                                            0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN__SHIFT                                            0x4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE__SHIFT                                        0x5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE__SHIFT                                        0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL__SHIFT                                            0x9
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT__SHIFT                                         0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT__SHIFT                                         0xb
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF__SHIFT                                         0xd
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW__SHIFT                                          0xe
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN_MASK                                              0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN_MASK                                              0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN_MASK                                              0x0010L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE_MASK                                          0x0020L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE_MASK                                          0x0040L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ_MASK                                           0x0080L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ_MASK                                           0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL_MASK                                              0x0200L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT_MASK                                           0x0400L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT_MASK                                           0x0800L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL_MASK                                          0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF_MASK                                           0x2000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW_MASK                                            0x4000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL__SHIFT                            0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL_MASK                              0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_METADATA_LOCATION
+#define C20_PHY_CR1_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION_MASK                                  0x7FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST__SHIFT                         0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN__SHIFT                 0xf
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_MASK                           0x7FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN_MASK                   0x8000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR1_LANE0_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_LANE0_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR1_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR1_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR1_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL
+#define C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR1_LANE0_DIG_RX_LBERT_ERR
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR1_LANE1_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_LANE1_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR1_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR1_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR1_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL
+#define C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR1_LANE1_DIG_RX_LBERT_ERR
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR1_LANE2_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_LANE2_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR1_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR1_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR1_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL
+#define C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR1_LANE2_DIG_RX_LBERT_ERR
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR1_LANE3_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_LANE3_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR1_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR1_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR1_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL
+#define C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR1_LANE3_DIG_RX_LBERT_ERR
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_SUP
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_SUP
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_SUP
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_SUP
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_IN_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_IN_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_IN_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_IN_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR1_LANEX_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_LANEX_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR1_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR1_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR1_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL
+#define C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR1_LANEX_DIG_RX_LBERT_ERR
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_SUP
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_IN_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+
+
+// addressBlock: c20_phy_lane0_pipe1_rdpcspipemsgbusind
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK           0x02L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK                  0x04L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK                 0x08L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK             0x10L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK                           0xE0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK                      0x7FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK                   0x80L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK   0xFFL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK                               0x02L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK                            0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK                                  0x02L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK                                 0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK                         0x02L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK                           0x04L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK                                  0xF8L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK              0x02L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK                             0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                         0x40L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK                                  0x80L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK                            0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                    0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK                                  0x40L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK             0x80L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK                                 0x07L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK                                  0x08L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK                                  0xF0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                     0x40L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK                              0x80L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK                        0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK                       0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK                              0x40L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK         0x80L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK                             0x07L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK                              0x08L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK                              0xF0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK                  0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK                              0xFEL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK             0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK   0x1EL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK             0x20L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK                      0x40L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK                     0x80L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK                           0x03L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK                            0xFCL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK                         0x03L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK                             0xFCL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK                 0xFFL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK                            0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK                                0x02L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK                                0x04L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK                                     0xF8L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK                             0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK                                 0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK                               0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK                        0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK                             0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK                      0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK                      0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x03L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x0CL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x30L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK                       0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK  0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK  0x02L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK    0x04L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK    0x08L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK     0x10L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK                       0xE0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK    0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK    0x02L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK      0x04L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK      0x08L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK       0x10L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK                        0xE0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK          0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK          0x02L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK          0x04L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK          0x08L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK                    0x10L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK                            0xE0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK                      0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK                     0x02L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK                           0xFCL
+
+
+// addressBlock: c20_phy_lane1_pipe1_rdpcspipemsgbusind
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK           0x02L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK                  0x04L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK                 0x08L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK             0x10L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK                           0xE0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK                      0x7FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK                   0x80L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK   0xFFL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK                               0x02L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK                            0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK                                  0x02L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK                                 0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK                         0x02L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK                           0x04L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK                                  0xF8L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK              0x02L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK                             0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                         0x40L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK                                  0x80L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK                            0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                    0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK                                  0x40L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK             0x80L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK                                 0x07L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK                                  0x08L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK                                  0xF0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                     0x40L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK                              0x80L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK                        0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK                       0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK                              0x40L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK         0x80L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK                             0x07L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK                              0x08L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK                              0xF0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK                  0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK                              0xFEL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK             0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK   0x1EL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK             0x20L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK                      0x40L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK                     0x80L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK                           0x03L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK                            0xFCL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK                         0x03L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK                             0xFCL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK                 0xFFL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK                            0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK                                0x02L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK                                0x04L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK                                     0xF8L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK                             0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK                                 0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK                               0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK                        0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK                             0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK                      0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK                      0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x03L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x0CL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x30L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK                       0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK  0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK  0x02L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK    0x04L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK    0x08L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK     0x10L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK                       0xE0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK    0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK    0x02L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK      0x04L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK      0x08L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK       0x10L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK                        0xE0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK          0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK          0x02L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK          0x04L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK          0x08L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK                    0x10L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK                            0xE0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK                      0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK                     0x02L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK                           0xFCL
+
+
+// addressBlock: c20_phy_cr2_rdpcspipecrind
+//C20_PHY_CR2_SUP_DIG_IDCODE_LO
+#define C20_PHY_CR2_SUP_DIG_IDCODE_LO__VAL__SHIFT                                                             0x0
+#define C20_PHY_CR2_SUP_DIG_IDCODE_LO__VAL_MASK                                                               0xFFFFL
+//C20_PHY_CR2_SUP_DIG_IDCODE_HI
+#define C20_PHY_CR2_SUP_DIG_IDCODE_HI__VAL__SHIFT                                                             0x0
+#define C20_PHY_CR2_SUP_DIG_IDCODE_HI__VAL_MASK                                                               0xFFFFL
+//C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN__SHIFT                                          0x2
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN__SHIFT                                  0x3
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD__SHIFT                                              0x4
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE__SHIFT                                            0x6
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN__SHIFT                                                    0xa
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN__SHIFT                                            0xb
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD__SHIFT                                  0xc
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN__SHIFT                               0xd
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14__SHIFT                                           0xe
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_MASK                                                 0x0001L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_MASK                                            0x0004L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN_MASK                                    0x0008L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_MASK                                                0x0010L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_MASK                                              0x01C0L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_MASK                                                      0x0400L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN_MASK                                              0x0800L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_MASK                                    0x1000L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN_MASK                                 0x2000L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14_MASK                                             0xC000L
+//C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL__SHIFT                                          0x0
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL__SHIFT                                           0x3
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN__SHIFT                                   0x5
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN__SHIFT                                            0x6
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL__SHIFT                                       0x8
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                               0x9
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10__SHIFT                                           0xa
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_MASK                                            0x0003L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_MASK                                             0x0018L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN_MASK                                     0x0020L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_MASK                                              0x0040L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_MASK                                         0x0100L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10_MASK                                             0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x0200L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x0200L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                                     0x0
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN__SHIFT                             0x2
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                               0x3
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN__SHIFT                                       0x6
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE__SHIFT                                              0x7
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9__SHIFT                                                0x9
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                                       0x0003L
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN_MASK                               0x0004L
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_MASK                                                 0x0038L
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN_MASK                                         0x0040L
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_MASK                                                0x0080L
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9_MASK                                                  0xFE00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xd
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN__SHIFT                                             0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL_MASK                                           0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV_MASK                                           0x001CL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL_MASK                                 0x0060L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                   0x0E00L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                    0x1000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK                                        0x2000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS_MASK                                        0x4000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN_MASK                                               0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN__SHIFT                                          0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL__SHIFT                                          0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD_MASK                                          0x3000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN_MASK                                            0x4000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL_MASK                                            0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_BW_LOW_OVRD_IN
+#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW_MASK                                           0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN
+#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH_MASK                                         0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN__SHIFT                                          0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x3
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0xd
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN_MASK                                            0x0004L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD_MASK                                     0x0008L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK                               0x03E0L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK                                0x0400L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK                      0x1000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK                                  0x2000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN_MASK                          0x4000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_3
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_4
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_5
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_6
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN__SHIFT                                             0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT                                            0xd
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL_MASK                                           0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV_MASK                                           0x001CL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL_MASK                                 0x0060L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                   0x0700L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN_MASK                                               0x1000L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK                                              0xE000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT__SHIFT                                          0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_MASK                                         0x007FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_MASK                                            0x7F00L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN_MASK                                    0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP__SHIFT                                         0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN__SHIFT                                 0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_MASK                                        0x007FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_MASK                                           0x7F00L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN_MASK                                   0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I__SHIFT                                             0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN__SHIFT                                     0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x3
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_MASK                                               0x0003L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN_MASK                                       0x0004L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_MASK                                          0x0018L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN__SHIFT                                          0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x3
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0xd
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN_MASK                                            0x0004L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD_MASK                                     0x0008L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK                               0x03E0L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK                                0x0400L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK                      0x1000L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK                                  0x2000L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN_MASK                          0x4000L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_3
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_5
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_6
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ__SHIFT                                                   0x0
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN__SHIFT                                               0x1
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN__SHIFT                                                  0x2
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN__SHIFT                                                  0x3
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN__SHIFT                                                 0x4
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7__SHIFT                                               0x7
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ_MASK                                                     0x0001L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN_MASK                                                 0x0002L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN_MASK                                                    0x0004L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN_MASK                                                    0x0008L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN_MASK                                                   0x0010L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7_MASK                                                 0xFF80L
+//C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET__SHIFT                                            0x0
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET__SHIFT                                              0xa
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN__SHIFT                                      0xf
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_MASK                                              0x01FFL
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_MASK                                                0x7C00L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN_MASK                                        0x8000L
+//C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_2
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET__SHIFT                                            0x0
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10__SHIFT                                              0xa
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_MASK                                              0x01FFL
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10_MASK                                                0xFC00L
+//C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT                                                  0x2
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT                                                  0x4
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x6
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x7
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x9
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD__SHIFT                                           0xa
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0xb
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD__SHIFT                                            0xc
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0xd
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14__SHIFT                                               0xe
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x0001L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK                                                    0x0004L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK                                                    0x0010L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x0040L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x0080L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x0100L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x0200L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_MASK                                             0x0400L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x0800L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_MASK                                              0x1000L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x2000L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14_MASK                                                 0xC000L
+//C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN
+#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x6
+#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN__SHIFT                                         0x9
+#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
+#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x001FL
+#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x01C0L
+#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN_MASK                                           0x0200L
+#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK                                                  0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV__SHIFT                                        0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xb
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14__SHIFT                                            0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV_MASK                                           0x000EL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV_MASK                                          0x0030L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0380L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK                                        0x0400L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS_MASK                                        0x0800L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD_MASK                                          0x3000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14_MASK                                              0xC000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_BW_LOW_ASIC_IN
+#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW_MASK                                           0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN
+#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH_MASK                                         0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x3
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD_MASK                                     0x0004L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK                               0x00F8L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK                                0x0100L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK                                  0x0200L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_3
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_4
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_5
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_6
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV__SHIFT                                        0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x6
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9__SHIFT                                             0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV_MASK                                           0x000EL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV_MASK                                          0x0030L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x01C0L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9_MASK                                               0xFE00L
+//C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT__SHIFT                                          0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS_MASK                                         0x007FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_MASK                                            0x3F80L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP__SHIFT                                         0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS_MASK                                        0x007FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_MASK                                           0x3F80L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I__SHIFT                                             0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I_MASK                                               0x0003L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO_MASK                                          0x000CL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x3
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD_MASK                                     0x0004L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK                               0x00F8L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK                                0x0100L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK                                  0x0200L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_3
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_5
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_6
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                            0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                      0xb
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14__SHIFT                                      0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                              0x0600L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                        0x3800L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14_MASK                                        0xC000L
+//C20_PHY_CR2_SUP_DIG_ASIC_IN_0
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__PHY_RESET__SHIFT                                                       0x0
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_CLK_EN__SHIFT                                                      0x1
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN__SHIFT                                                 0x2
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_USE_PAD__SHIFT                                                     0x3
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__TEST_BURNIN__SHIFT                                                     0x4
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN__SHIFT                                                  0x5
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RTUNE_REQ__SHIFT                                                       0x6
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RES_REQ_IN__SHIFT                                                      0x7
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RES_ACK_IN__SHIFT                                                      0x8
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__BG_EN__SHIFT                                                           0x9
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                              0xa
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_RANGE__SHIFT                                                       0xb
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE__SHIFT                                                 0xe
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RESERVED_15_15__SHIFT                                                  0xf
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__PHY_RESET_MASK                                                         0x0001L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_CLK_EN_MASK                                                        0x0002L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN_MASK                                                   0x0004L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_USE_PAD_MASK                                                       0x0008L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__TEST_BURNIN_MASK                                                       0x0010L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN_MASK                                                    0x0020L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RTUNE_REQ_MASK                                                         0x0040L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RES_REQ_IN_MASK                                                        0x0080L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RES_ACK_IN_MASK                                                        0x0100L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__BG_EN_MASK                                                             0x0200L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL_MASK                                                0x0400L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_RANGE_MASK                                                         0x3800L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE_MASK                                                   0x4000L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RESERVED_15_15_MASK                                                    0x8000L
+//C20_PHY_CR2_SUP_DIG_ASIC_IN_1
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__SUP_MISC__SHIFT                                                        0x0
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN__SHIFT                                                0x8
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN__SHIFT                                              0x9
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL__SHIFT                                                 0xa
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL__SHIFT                                                  0xc
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__RESERVED_15_14__SHIFT                                                  0xe
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__SUP_MISC_MASK                                                          0x00FFL
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN_MASK                                                  0x0100L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN_MASK                                                0x0200L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL_MASK                                                   0x0C00L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL_MASK                                                    0x3000L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__RESERVED_15_14_MASK                                                    0xC000L
+//C20_PHY_CR2_SUP_DIG_ASIC_OUT_0
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT__SHIFT                                              0x0
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__MPLLA_STATE__SHIFT                                                    0x1
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__MPLLB_STATE__SHIFT                                                    0x2
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RTUNE_ACK__SHIFT                                                      0x3
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT__SHIFT                                                    0x4
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT__SHIFT                                                    0x5
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__DTB_OUT__SHIFT                                                        0x6
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RESERVED_15_8__SHIFT                                                  0x8
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT_MASK                                                0x0001L
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__MPLLA_STATE_MASK                                                      0x0002L
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__MPLLB_STATE_MASK                                                      0x0004L
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RTUNE_ACK_MASK                                                        0x0008L
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT_MASK                                                      0x0010L
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT_MASK                                                      0x0020L
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__DTB_OUT_MASK                                                          0x00C0L
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RESERVED_15_8_MASK                                                    0xFF00L
+//C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN
+#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x5
+#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN__SHIFT                                                 0x8
+#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET__SHIFT                                                0x9
+#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14__SHIFT                                                0xe
+#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x001FL
+#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x00E0L
+#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN_MASK                                                   0x0100L
+#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET_MASK                                                  0x3E00L
+#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14_MASK                                                  0xC000L
+//C20_PHY_CR2_SUP_DIG_SUP_OVRD_MISC
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN__SHIFT                                            0x8
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9__SHIFT                                               0x9
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN_MASK                                              0x0100L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9_MASK                                                 0xFE00L
+//C20_PHY_CR2_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN
+#define C20_PHY_CR2_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET__SHIFT                                 0x0
+#define C20_PHY_CR2_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET_MASK                                   0x01FFL
+#define C20_PHY_CR2_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN
+#define C20_PHY_CR2_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET__SHIFT                                 0x0
+#define C20_PHY_CR2_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET_MASK                                   0x01FFL
+#define C20_PHY_CR2_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL__SHIFT                                0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL__SHIFT                                  0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL__SHIFT                             0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10__SHIFT                                          0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL_MASK                                  0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL_MASK                                    0x0004L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL_MASK                               0x01F0L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10_MASK                                            0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY__SHIFT                                           0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE__SHIFT                                      0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7__SHIFT                                           0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE_MASK                                           0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY_MASK                                             0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE_MASK                                        0x007CL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7_MASK                                             0xFF80L
+//C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__RESERVED__SHIFT                                                     0x1
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL__SHIFT                                                0x6
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7__SHIFT                                                0x7
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x0001L
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__RESERVED_MASK                                                       0x0002L
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x0004L
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x0038L
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL_MASK                                                  0x0040L
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7_MASK                                                  0xFF80L
+//C20_PHY_CR2_SUP_DIG_RTUNE_STAT
+#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__RTUNE_STATE__SHIFT                                                    0xa
+#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE__SHIFT                                                 0xd
+#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__RESERVED_15_15__SHIFT                                                 0xf
+#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x03FFL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__RTUNE_STATE_MASK                                                      0x1C00L
+#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE_MASK                                                   0x6000L
+#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__RESERVED_15_15_MASK                                                   0x8000L
+//C20_PHY_CR2_SUP_DIG_RTUNE_RX_SET_VAL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
+#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x003FL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0xFFC0L
+//C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x03FFL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x03FFL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR2_SUP_DIG_RTUNE_RX_STAT
+#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x003FL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_STAT
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x03FFL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0xFC00L
+//C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_STAT
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x03FFL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0xFC00L
+//C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG__SHIFT                                                  0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10__SHIFT                                       0xa
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG_MASK                                                    0x03FFL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10_MASK                                         0xFC00L
+//C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_1
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN__SHIFT                                                 0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10__SHIFT                                       0xa
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN_MASK                                                   0x03FFL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10_MASK                                         0xFC00L
+//C20_PHY_CR2_SUP_DIG_RTUNE_FAST_FLAGS
+#define C20_PHY_CR2_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE__SHIFT                                               0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR2_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE_MASK                                                 0x0001L
+#define C20_PHY_CR2_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER__SHIFT                                  0xa
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11__SHIFT                                    0xb
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x01FFL
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x0200L
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER_MASK                                    0x0400L
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11_MASK                                      0xF800L
+//C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x01FFL
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x00FFL
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x001FL
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x0020L
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE__SHIFT                                     0x1
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE__SHIFT                                     0x2
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE__SHIFT                                      0x4
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6__SHIFT                                     0x6
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE_MASK                                        0x0001L
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE_MASK                                       0x0002L
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE_MASK                                       0x000CL
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE_MASK                                        0x0030L
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6_MASK                                       0xFFC0L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL__SHIFT                                0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL__SHIFT                                 0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN__SHIFT                               0x6
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE__SHIFT                             0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE__SHIFT                                0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT_MASK                                      0x000FL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL_MASK                                  0x0010L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL_MASK                                   0x0020L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE_MASK                               0x7F80L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE_MASK                                  0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE__SHIFT                               0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14__SHIFT                              0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK                                      0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK                              0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK                               0x0008L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK                                0x0010L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE_MASK                                 0x3C00L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14_MASK                                0xC000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                                      0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                                       0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                                      0x6
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xd
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP__SHIFT                             0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                                        0x0010L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                                         0x0020L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                                        0x0040L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0080L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0100L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0200L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x1000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x2000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x4000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP_MASK                               0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME__SHIFT               0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME__SHIFT                 0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME_MASK                 0x03FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME_MASK                   0x3C00L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK                         0xC000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME__SHIFT           0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME__SHIFT                         0xb
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME_MASK             0x07FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME_MASK                           0xF800L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME__SHIFT                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME__SHIFT                  0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME__SHIFT               0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME_MASK                          0x001FL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME_MASK                    0x03E0L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME_MASK                 0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME__SHIFT                  0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME__SHIFT                0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME_MASK                    0x007FL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME_MASK                  0x0F80L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT                     0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL__SHIFT                       0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12__SHIFT                           0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK                       0x00FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL_MASK                         0x0F00L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12_MASK                             0xF000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT             0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP__SHIFT          0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG__SHIFT         0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK               0x00FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP_MASK            0x0300L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG_MASK           0x0C00L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0__SHIFT                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0__SHIFT                      0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0_MASK                        0x00FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0_MASK                        0xFF00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1__SHIFT                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1__SHIFT                      0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1_MASK                        0x00FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1_MASK                        0xFF00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2__SHIFT                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2__SHIFT                      0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2_MASK                        0x00FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2_MASK                        0xFF00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3__SHIFT                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3__SHIFT                      0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3_MASK                        0x00FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3_MASK                        0xFF00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME__SHIFT         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME__SHIFT                   0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME_MASK           0x03FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME_MASK                     0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME__SHIFT     0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11__SHIFT                       0xb
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME_MASK       0x07FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11_MASK                         0xF800L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME__SHIFT              0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10__SHIFT                       0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME_MASK                0x03FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10_MASK                         0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME__SHIFT             0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10__SHIFT                       0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME_MASK               0x03FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10_MASK                         0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7__SHIFT                        0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME_MASK                 0x007FL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7_MASK                          0xFF80L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN__SHIFT                 0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2__SHIFT                               0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN_MASK                   0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2_MASK                                 0xFFFCL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_FRAC_OUT
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_SSC_RAMP
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_CONFIG
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK                                          0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK                                           0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN__SHIFT                            0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE__SHIFT                                   0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL_MASK                             0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN_MASK                              0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE_MASK                                     0x007CL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK                                      0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK                              0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK                               0x0008L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK                                0x0010L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC__SHIFT                                 0xd
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC__SHIFT                                 0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0010L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0020L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0100L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x0200L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x0400L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x0800L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x1000L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC_MASK                                   0x2000L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC_MASK                                   0x4000L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME__SHIFT                          0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME_MASK                              0x00FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME_MASK                            0x3F00L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK                         0xC000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME__SHIFT                       0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME__SHIFT                          0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME_MASK                         0x00FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME_MASK                            0xFF00L
+//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME__SHIFT                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME__SHIFT                         0x6
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME_MASK                        0x003FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME_MASK                           0x0FC0L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME__SHIFT                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME__SHIFT                           0x6
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME_MASK                          0x003FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME_MASK                             0x0FC0L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS__SHIFT                0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS_MASK                  0x001FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7__SHIFT                        0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME_MASK                 0x007FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7_MASK                          0xFF80L
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_FRAC_OUT
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_SSC_RAMP
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_CONFIG
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK                                          0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK                                           0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT__SHIFT                                      0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK__SHIFT                                             0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC__SHIFT                                              0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT__SHIFT                                          0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL__SHIFT                                         0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10__SHIFT                                             0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT_MASK                                           0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT_MASK                                        0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK_MASK                                               0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC_MASK                                                0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT_MASK                                            0x01F0L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL_MASK                                           0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10_MASK                                               0xFC00L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN__SHIFT                                                 0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START__SHIFT                                    0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN__SHIFT                                            0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL__SHIFT                                      0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START__SHIFT                                   0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL__SHIFT                                         0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN__SHIFT                                                 0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST__SHIFT                                           0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE__SHIFT                                               0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST__SHIFT                                             0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN_MASK                                                   0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START_MASK                                      0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN_MASK                                              0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL_MASK                                        0x0030L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START_MASK                                     0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL_MASK                                           0x0380L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN_MASK                                                   0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST_MASK                                             0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE_MASK                                                 0x3000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST_MASK                                               0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP__SHIFT                              0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL__SHIFT                                       0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST__SHIFT                                       0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT__SHIFT                                 0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN__SHIFT                                 0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN__SHIFT                                   0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN__SHIFT                               0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN__SHIFT                               0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN__SHIFT                                0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN__SHIFT                            0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12__SHIFT                                      0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP_MASK                                0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL_MASK                                         0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST_MASK                                         0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT_MASK                                   0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN_MASK                                   0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN_MASK                                     0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN_MASK                              0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12_MASK                                        0xF000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL__SHIFT                                       0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST__SHIFT                                       0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT__SHIFT                                 0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN__SHIFT                               0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN__SHIFT                               0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN__SHIFT                               0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN__SHIFT                                0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN__SHIFT                           0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE__SHIFT                                 0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY__SHIFT                                   0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14__SHIFT                                      0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_MASK                                         0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST_MASK                                         0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT_MASK                                   0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN_MASK                             0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE_MASK                                   0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY_MASK                                     0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14_MASK                                        0xC000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN__SHIFT                                                  0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START__SHIFT                                          0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN__SHIFT                                  0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START__SHIFT                                          0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN__SHIFT                                  0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER__SHIFT                                0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP__SHIFT                                0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                          0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_MASK                                                    0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_MASK                                            0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN_MASK                                    0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_MASK                                            0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN_MASK                                    0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER_MASK                                  0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP_MASK                                  0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                            0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                      0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                              0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                   0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                           0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE__SHIFT                                  0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_MASK                                        0x000CL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_MASK                                     0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                             0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE_MASK                                       0x0180L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE_MASK                                    0x7E00L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL__SHIFT                                   0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL__SHIFT                                0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL_MASK                                      0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL_MASK                                     0x0006L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL_MASK                                  0x0018L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP__SHIFT                            0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                    0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN__SHIFT                            0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                         0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                         0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT__SHIFT                               0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                        0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_MASK                              0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                      0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN_MASK                              0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                           0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                           0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_MASK                                 0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN__SHIFT                                 0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN__SHIFT                              0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN__SHIFT                      0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN__SHIFT                            0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN__SHIFT                    0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN__SHIFT                            0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN__SHIFT                                  0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN__SHIFT                          0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN__SHIFT                              0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_MASK                                   0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN_MASK                           0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN_MASK                           0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_MASK                                0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN_MASK                        0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_MASK                              0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN_MASK                      0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_MASK                              0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN_MASK                           0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_MASK                                    0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN_MASK                            0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_MASK                                0x4000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN__SHIFT                                0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN_MASK                        0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK                                  0xFFF0L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC__SHIFT                              0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT__SHIFT                               0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC_MASK                                0x003FL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT_MASK                                 0xFFC0L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                         0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                         0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT__SHIFT                                   0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE__SHIFT                                   0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                     0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                        0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                           0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                           0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_MASK                                     0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_MASK                                     0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                       0x4000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN__SHIFT                                 0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN__SHIFT                                0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                        0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN__SHIFT                         0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN__SHIFT                             0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_MASK                                   0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN_MASK                           0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN_MASK                           0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                          0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN_MASK                           0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_MASK                               0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN__SHIFT                                0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN_MASK                        0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK                                  0xFFF0L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC__SHIFT                              0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT__SHIFT                               0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC_MASK                                0x003FL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT_MASK                                 0xFFC0L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                            0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                      0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                          0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                         0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                       0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                              0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                        0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                            0x000CL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                           0x3FF0L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                         0x4000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_OVRD_OUT
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC__SHIFT                                          0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_MASK                                            0x00FFL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE__SHIFT                            0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN__SHIFT                    0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE__SHIFT                              0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN__SHIFT                      0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_MASK                              0x00FFL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN_MASK                      0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_MASK                                0x1E00L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN_MASK                        0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG__SHIFT                                   0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1__SHIFT                                        0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT__SHIFT                                  0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START__SHIFT                             0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG__SHIFT                              0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST__SHIFT                                  0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT__SHIFT                            0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG__SHIFT                                   0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2__SHIFT                           0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7__SHIFT                                0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST__SHIFT                           0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT__SHIFT                                 0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX__SHIFT                             0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_MASK                                     0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1_MASK                                          0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT_MASK                                    0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START_MASK                               0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG_MASK                                0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST_MASK                                    0x0060L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT_MASK                              0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG_MASK                                     0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2_MASK                             0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7_MASK                                  0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST_MASK                             0x1800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT_MASK                                   0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX_MASK                               0xC000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX__SHIFT                             0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0__SHIFT                         0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6__SHIFT                                        0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0__SHIFT                              0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS__SHIFT                                   0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST_MASK                                      0x0003L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX_MASK                               0x000CL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0_MASK                           0x0030L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6_MASK                                          0x00C0L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0_MASK                                0x7F00L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS_MASK                                     0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF__SHIFT                                 0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP__SHIFT                                 0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB__SHIFT                                      0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP__SHIFT                                 0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE__SHIFT                                 0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5__SHIFT                                        0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON__SHIFT                                 0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN__SHIFT                            0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN__SHIFT                           0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF_MASK                                   0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP_MASK                                   0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB_MASK                                        0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP_MASK                                   0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE_MASK                                   0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5_MASK                                          0x0060L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON_MASK                                   0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN_MASK                              0x0F00L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN_MASK                             0xF000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE__SHIFT                          0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE__SHIFT                                    0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM__SHIFT                                0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR__SHIFT                                0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF__SHIFT                                        0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9__SHIFT                                       0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE_MASK                            0x0003L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE_MASK                                      0x000CL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM_MASK                                  0x0030L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR_MASK                                  0x00C0L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF_MASK                                          0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9_MASK                                         0x7E00L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF__SHIFT                                    0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR__SHIFT                           0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL__SHIFT                                0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0_MASK                                      0x007FL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF_MASK                                      0x0180L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR_MASK                             0x7E00L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL_MASK                                  0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS__SHIFT                          0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC__SHIFT                            0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS__SHIFT                               0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4__SHIFT                                      0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG__SHIFT                                0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL__SHIFT                             0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE__SHIFT                             0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG__SHIFT                              0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL__SHIFT                                0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG__SHIFT                                 0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG__SHIFT                           0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET__SHIFT                              0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG__SHIFT                               0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0_MASK                                        0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS_MASK                            0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC_MASK                              0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS_MASK                                 0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4_MASK                                        0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG_MASK                                  0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL_MASK                               0x00C0L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE_MASK                               0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG_MASK                                0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL_MASK                                  0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG_MASK                                   0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG_MASK                             0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET_MASK                                0x4000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG_MASK                                 0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV__SHIFT                                 0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_MASK                                   0xFFFFL
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16__SHIFT                           0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT__SHIFT                              0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22__SHIFT                           0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16_MASK                             0x003FL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT_MASK                                0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22_MASK                             0x3F80L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN__SHIFT                      0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN__SHIFT                           0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW__SHIFT                              0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW__SHIFT                                   0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN__SHIFT                       0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG__SHIFT                            0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90__SHIFT                            0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN_MASK                        0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN_MASK                             0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW_MASK                                0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW_MASK                                     0x0FF8L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN_MASK                         0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG_MASK                              0x6000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90_MASK                              0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0__SHIFT                                     0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0_MASK                                       0xFFFFL
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0__SHIFT                                     0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0_MASK                                       0xFFFFL
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0__SHIFT                                  0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0_MASK                                    0x00FFL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT__SHIFT                       0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT__SHIFT                       0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV__SHIFT                           0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN__SHIFT                                  0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK__SHIFT                          0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6__SHIFT                                      0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS__SHIFT                          0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS__SHIFT                               0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT__SHIFT                          0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG__SHIFT                           0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR__SHIFT                          0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO__SHIFT                              0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV__SHIFT                             0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90__SHIFT                            0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT_MASK                         0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT_MASK                         0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV_MASK                             0x000CL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN_MASK                                    0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK_MASK                            0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6_MASK                                        0x00C0L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS_MASK                            0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS_MASK                                 0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT_MASK                            0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG_MASK                             0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR_MASK                            0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO_MASK                                0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV_MASK                               0x4000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90_MASK                              0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE__SHIFT                             0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG__SHIFT                              0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL__SHIFT                                0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG__SHIFT                                 0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN__SHIFT                          0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG__SHIFT                           0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET__SHIFT                              0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG__SHIFT                               0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP__SHIFT                            0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13__SHIFT                                    0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT__SHIFT                              0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE_MASK                               0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG_MASK                                0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL_MASK                                  0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG_MASK                                   0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN_MASK                            0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG_MASK                             0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET_MASK                                0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG_MASK                                 0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP_MASK                              0x1F00L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13_MASK                                      0x6000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT_MASK                                0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER__SHIFT                 0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ__SHIFT                       0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE__SHIFT                  0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED__SHIFT                       0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV__SHIFT                         0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H__SHIFT                         0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP__SHIFT                        0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP__SHIFT                    0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP__SHIFT                      0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP__SHIFT                       0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE__SHIFT                          0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER_MASK                   0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ_MASK                         0x0006L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE_MASK                    0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED_MASK                         0x00F0L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV_MASK                           0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H_MASK                           0x0600L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP_MASK                          0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP_MASK                      0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP_MASK                        0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP_MASK                         0x4000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE_MASK                            0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN__SHIFT                 0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN__SHIFT                         0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK__SHIFT                            0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5__SHIFT                                      0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8__SHIFT                                     0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START__SHIFT                     0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE__SHIFT                        0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST__SHIFT                             0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN_MASK                   0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN_MASK                           0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_MASK                              0x001CL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5_MASK                                        0x00E0L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8_MASK                                       0x0F00L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START_MASK                       0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE_MASK                          0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST_MASK                               0xC000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT__SHIFT                             0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW__SHIFT                         0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF__SHIFT                    0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS__SHIFT                               0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH__SHIFT                       0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN__SHIFT                           0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP__SHIFT                             0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO__SHIFT                            0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR__SHIFT                        0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING__SHIFT                           0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR__SHIFT                          0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF__SHIFT                    0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK__SHIFT                    0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG__SHIFT                        0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT_MASK                               0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW_MASK                           0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF_MASK                      0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS_MASK                                 0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH_MASK                         0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN_MASK                             0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP_MASK                               0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO_MASK                              0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR_MASK                          0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING_MASK                             0x0600L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR_MASK                            0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF_MASK                      0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK_MASK                      0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG_MASK                          0xC000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT__SHIFT                       0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING__SHIFT                        0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR__SHIFT                        0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2__SHIFT                    0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP__SHIFT                      0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED__SHIFT                       0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2__SHIFT                     0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X__SHIFT                               0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD__SHIFT                                 0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N__SHIFT                             0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC__SHIFT                           0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER__SHIFT                            0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT_MASK                         0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING_MASK                          0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR_MASK                          0x000CL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2_MASK                      0x0030L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP_MASK                        0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_MASK                         0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2_MASK                       0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X_MASK                                 0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD_MASK                                   0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N_MASK                               0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC_MASK                             0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER_MASK                              0xE000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF__SHIFT                          0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF__SHIFT                         0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL__SHIFT                          0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0__SHIFT                        0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH__SHIFT                         0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2__SHIFT                          0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES__SHIFT                             0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF_MASK                            0x0007L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF_MASK                           0x0038L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL_MASK                            0x00C0L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0_MASK                          0x0300L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH_MASK                           0x0C00L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2_MASK                            0x3000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES_MASK                               0xC000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG__SHIFT                            0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC__SHIFT                             0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL__SHIFT                         0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP__SHIFT                        0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK__SHIFT                          0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN__SHIFT                    0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST__SHIFT                              0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0_MASK                                        0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG_MASK                              0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC_MASK                               0x000CL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL_MASK                           0x0030L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP_MASK                          0x00C0L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK_MASK                            0x0F00L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN_MASK                      0x3000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST_MASK                                0xC000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                 0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                   0xFFFFL
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                 0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                   0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_CMN_CTL
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_CMN_CLK_GATE_CTL
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN__SHIFT                                                 0x2
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x5
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN__SHIFT                                                 0x6
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE__SHIFT                                              0x8
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x9
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ__SHIFT                                                    0xa
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0xb
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE__SHIFT                                           0xc
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_MASK                                                   0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_MASK                                                   0x0040L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_MASK                                                0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0200L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_MASK                                                      0x0400L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x0800L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE_MASK                                             0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0xE000L
+//C20_PHY_CR2_RAWCMN_DIG_MPLL_CONFIG
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME__SHIFT                                         0x6
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10__SHIFT                                             0xa
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME_MASK                                                0x003FL
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME_MASK                                           0x03C0L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10_MASK                                               0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_CTRL
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4__SHIFT                                             0x4
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE_MASK                                              0x000FL
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4_MASK                                               0xFFF0L
+//C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_ADDR
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_ADDR__ADDR__SHIFT                                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_ADDR__ADDR_MASK                                                        0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_DATA
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_DATA__DATA__SHIFT                                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_DATA__DATA_MASK                                                        0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_FLAGS
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_ACCUM
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_ACCUM__VAL__SHIFT                                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_ACCUM__VAL_MASK                                                        0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLL_IN
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN__SHIFT                                                   0x3
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__RESERVED_15_4__SHIFT                                                  0x4
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE_MASK                                           0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN_MASK                                                     0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__RESERVED_15_4_MASK                                                    0xFFF0L
+//C20_PHY_CR2_RAWCMN_DIG_FW_PWRUP_DONE
+#define C20_PHY_CR2_RAWCMN_DIG_FW_PWRUP_DONE__DONE__SHIFT                                                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR2_RAWCMN_DIG_FW_PWRUP_DONE__DONE_MASK                                                       0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_STATIC_CONFIG_STATUS
+#define C20_PHY_CR2_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE_MASK                                            0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_FW_CONFIG_STATUS
+#define C20_PHY_CR2_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE__SHIFT                                          0x1
+#define C20_PHY_CR2_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE_MASK                                            0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE_MASK                                            0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_CMN_STATUS_1
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2__SHIFT                                             0x2
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE_MASK                                               0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2_MASK                                               0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x2
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0x3
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0x4
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0x5
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x7
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x9
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0xa
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0xc
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL_MASK                       0x0003L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN_MASK                        0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK                       0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN_MASK                        0x0010L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK                        0x0020L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL_MASK                       0x0180L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN_MASK                        0x0200L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK                       0x0400L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK                        0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_FRAC_UPDATE
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE__SHIFT                               0x1
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN_MASK                               0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE_MASK                                 0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_FRAC_UPDATE
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE__SHIFT                               0x1
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN_MASK                               0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE_MASK                                 0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_CONFIG_MASTER_VERSION
+#define C20_PHY_CR2_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION_MASK                                     0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_0
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_1
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_2
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_3
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR2_RAWCMN_DIG_CREG_ACCESS_CTL
+#define C20_PHY_CR2_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN__SHIFT                              0x8
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN_MASK                                0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN__SHIFT                              0x8
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN_MASK                                0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_0
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11__SHIFT                                          0xb
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC_MASK                                                  0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL_MASK                                             0x0700L
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11_MASK                                            0xF800L
+//C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_1
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET__SHIFT                                        0x5
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14__SHIFT                                          0xe
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL_MASK                                              0x001FL
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET_MASK                                          0x3FE0L
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14_MASK                                            0xC000L
+//C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_2
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET__SHIFT                                        0x5
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14__SHIFT                                          0xe
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET_MASK                                            0x001FL
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET_MASK                                          0x3FE0L
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14_MASK                                            0xC000L
+//C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_3
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID__SHIFT                                               0x0
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10__SHIFT                                          0xa
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID_MASK                                                 0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10_MASK                                            0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN__SHIFT                                         0xf
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER_MASK                                              0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN_MASK                                              0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN_MASK                                           0x8000L
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV__SHIFT                                            0x8
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0xb
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD__SHIFT                                          0xe
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV_MASK                                              0x0700L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV_MASK                                            0x1800L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD_MASK                                            0xC000L
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_2
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_3
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH__SHIFT                                               0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH_MASK                                                 0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_4
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB_MASK                                            0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_5
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK                                       0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV__SHIFT                                     0xa
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL__SHIFT                                            0xd
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xe
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB_MASK                                            0x000FL
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK                                       0x01F0L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD_MASK                                           0x0200L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV_MASK                                       0x1C00L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL_MASK                                              0x2000L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN_MASK                                                 0x4000L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_7
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN_MASK                                                0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_8
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT_MASK                                               0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_9
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM_MASK                                                0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV__SHIFT                                            0xd
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER_MASK                                              0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN_MASK                                              0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV_MASK                                              0xE000L
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE__SHIFT                                          0xa
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV_MASK                                            0x0300L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE_MASK                                            0x7C00L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_2
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP__SHIFT                                               0x7
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO__SHIFT                                              0xe
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT_MASK                                                  0x007FL
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP_MASK                                                 0x3F80L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO_MASK                                                0xC000L
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_3
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS__SHIFT                                            0x7
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I__SHIFT                                                   0xe
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS_MASK                                               0x007FL
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS_MASK                                              0x3F80L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I_MASK                                                     0xC000L
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_4
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB_MASK                                            0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_5
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK                                       0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV__SHIFT                                     0xa
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xd
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB_MASK                                            0x000FL
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK                                       0x01F0L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD_MASK                                           0x0200L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV_MASK                                       0x1C00L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN_MASK                                                 0x2000L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_7
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN_MASK                                                0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_8
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT_MASK                                               0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_9
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM_MASK                                                0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_10
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV_MASK                                               0x0007L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV_MASK                                     0x0018L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN__SHIFT                                        0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN_MASK                                          0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3_MASK                                       0xFFF8L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0__SHIFT                           0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0_MASK                                  0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0_MASK                             0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1__SHIFT                           0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1_MASK                                  0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1_MASK                             0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2__SHIFT                           0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2_MASK                                  0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2_MASK                             0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3__SHIFT                           0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3_MASK                                  0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3_MASK                             0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL__SHIFT                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL_MASK                                0x0003L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_DONE
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0__SHIFT                           0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0_MASK                                  0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0_MASK                             0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1__SHIFT                           0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1_MASK                                  0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1_MASK                             0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2__SHIFT                           0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2_MASK                                  0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2_MASK                             0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3__SHIFT                           0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3_MASK                                  0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3_MASK                             0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL__SHIFT                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL_MASK                                0x0003L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_DONE
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12__SHIFT                                          0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE_MASK                                                0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12_MASK                                            0xF000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12__SHIFT                                          0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE_MASK                                                0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12_MASK                                            0xF000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_IN_RECAL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_IN_RECAL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                       0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6__SHIFT                                           0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                         0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                       0x0010L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6_MASK                                             0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO__SHIFT                                       0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                              0x4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                               0x5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                          0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO_MASK                                         0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                                0x0010L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                            0x8
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12__SHIFT                                         0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                      0x0010L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                              0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12_MASK                                           0xF000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN__SHIFT                                            0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN__SHIFT                                                0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                        0x4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK__SHIFT                                                0x5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN_MASK                                              0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN_MASK                                                  0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL_MASK                                          0x0010L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK_MASK                                                  0x0020L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6_MASK                                               0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                               0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                              0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                               0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL__SHIFT                                  0x4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN__SHIFT                                   0x5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL__SHIFT                                   0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL_MASK                                0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL_MASK                                0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN_MASK                                 0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL_MASK                                    0x0010L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN_MASK                                     0x0020L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL_MASK                                     0x0040L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK__SHIFT                                          0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4__SHIFT                                            0x4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK_MASK                                            0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK_MASK                                            0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4_MASK                                              0xFFF0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL_MASK                    0x0003L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL_MASK                    0x0003L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                                0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT__SHIFT                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE__SHIFT                              0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT_MASK                                0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE_MASK                                0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                        0x003FL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                    0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0_MASK                                  0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                        0x003FL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                    0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1_MASK                                  0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                        0x003FL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                    0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2_MASK                                  0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                        0x003FL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                    0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3_MASK                                  0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                        0x003FL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                    0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4_MASK                                  0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                        0x003FL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                    0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5_MASK                                  0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                        0x003FL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                    0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6_MASK                                  0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_7
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                        0x003FL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                    0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7_MASK                                  0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL__SHIFT                             0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL__SHIFT                             0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN__SHIFT                              0x4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL__SHIFT                         0x5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL_MASK                               0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL_MASK                               0x000CL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN_MASK                                0x0010L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL_MASK                           0x0060L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS_MASK                                         0x0018L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5_MASK                                                0xFFE0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OUT
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_AON_FW_VERSION_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_FW_VERSION_0__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_FW_VERSION_0__VAL_MASK                                                     0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_AON_FW_VERSION_1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_FW_VERSION_1__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_FW_VERSION_1__VAL_MASK                                                     0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_AON_RAW_VERSION
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RAW_VERSION__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RAW_VERSION__VAL_MASK                                                      0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_EOF_ADDR
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_BOC_ADDR
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL__SHIFT                                     0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN__SHIFT                                      0x7
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10__SHIFT                                           0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL_MASK                                    0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL_MASK                                       0x0010L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL_MASK                                       0x0040L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN_MASK                                        0x0080L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10_MASK                                             0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL_MASK                                            0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN__SHIFT                                            0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN__SHIFT                                            0x4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE__SHIFT                                        0x5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE__SHIFT                                        0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL__SHIFT                                            0x9
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT__SHIFT                                         0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT__SHIFT                                         0xb
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF__SHIFT                                         0xd
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW__SHIFT                                          0xe
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN_MASK                                              0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN_MASK                                              0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN_MASK                                              0x0010L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE_MASK                                          0x0020L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE_MASK                                          0x0040L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ_MASK                                           0x0080L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ_MASK                                           0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL_MASK                                              0x0200L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT_MASK                                           0x0400L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT_MASK                                           0x0800L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL_MASK                                          0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF_MASK                                           0x2000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW_MASK                                            0x4000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL__SHIFT                            0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL_MASK                              0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_METADATA_LOCATION
+#define C20_PHY_CR2_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION_MASK                                  0x7FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST__SHIFT                         0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN__SHIFT                 0xf
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_MASK                           0x7FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN_MASK                   0x8000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR2_LANE0_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_LANE0_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR2_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR2_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR2_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR2_LANE0_DIG_TX_FIFO_CTL
+#define C20_PHY_CR2_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR2_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR2_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR2_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR2_LANE0_DIG_RX_LBERT_ERR
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_CDR_STAT
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR2_LANE1_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_LANE1_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR2_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR2_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR2_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR2_LANE1_DIG_TX_FIFO_CTL
+#define C20_PHY_CR2_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR2_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR2_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR2_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR2_LANE1_DIG_RX_LBERT_ERR
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_CDR_STAT
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR2_LANE2_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_LANE2_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR2_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR2_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR2_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR2_LANE2_DIG_TX_FIFO_CTL
+#define C20_PHY_CR2_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR2_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR2_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR2_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR2_LANE2_DIG_RX_LBERT_ERR
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_CDR_STAT
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR2_LANE3_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_LANE3_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR2_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR2_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR2_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR2_LANE3_DIG_TX_FIFO_CTL
+#define C20_PHY_CR2_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR2_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR2_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR2_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR2_LANE3_DIG_RX_LBERT_ERR
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_CDR_STAT
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_CR_LOCK
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_SUP
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_CR_LOCK
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_SUP
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_CR_LOCK
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_SUP
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_CR_LOCK
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_SUP
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_IN_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_OUT_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_IN_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_OUT_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_IN_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_OUT_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_IN_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_OUT_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR2_LANEX_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_LANEX_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR2_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR2_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR2_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR2_LANEX_DIG_TX_FIFO_CTL
+#define C20_PHY_CR2_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR2_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR2_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR2_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR2_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR2_LANEX_DIG_RX_LBERT_ERR
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_CDR_STAT
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_CR_LOCK
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_SUP
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_IN_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_OUT_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+
+
+// addressBlock: c20_phy_lane0_pipe2_rdpcspipemsgbusind
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK           0x02L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK                  0x04L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK                 0x08L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK             0x10L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK                           0xE0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK                      0x7FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK                   0x80L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK   0xFFL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK                               0x02L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK                            0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK                                  0x02L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK                                 0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK                         0x02L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK                           0x04L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK                                  0xF8L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK              0x02L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK                             0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                         0x40L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK                                  0x80L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK                            0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                    0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK                                  0x40L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK             0x80L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK                                 0x07L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK                                  0x08L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK                                  0xF0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                     0x40L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK                              0x80L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK                        0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK                       0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK                              0x40L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK         0x80L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK                             0x07L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK                              0x08L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK                              0xF0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK                  0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK                              0xFEL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK             0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK   0x1EL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK             0x20L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK                      0x40L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK                     0x80L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK                           0x03L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK                            0xFCL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK                         0x03L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK                             0xFCL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK                 0xFFL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK                            0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK                                0x02L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK                                0x04L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK                                     0xF8L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK                             0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK                                 0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK                               0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK                        0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK                             0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK                      0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK                      0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x03L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x0CL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x30L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK                       0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK  0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK  0x02L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK    0x04L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK    0x08L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK     0x10L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK                       0xE0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK    0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK    0x02L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK      0x04L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK      0x08L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK       0x10L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK                        0xE0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK          0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK          0x02L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK          0x04L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK          0x08L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK                    0x10L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK                            0xE0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK                      0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK                     0x02L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK                           0xFCL
+
+
+// addressBlock: c20_phy_lane1_pipe2_rdpcspipemsgbusind
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK           0x02L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK                  0x04L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK                 0x08L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK             0x10L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK                           0xE0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK                      0x7FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK                   0x80L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK   0xFFL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK                               0x02L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK                            0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK                                  0x02L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK                                 0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK                         0x02L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK                           0x04L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK                                  0xF8L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK              0x02L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK                             0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                         0x40L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK                                  0x80L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK                            0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                    0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK                                  0x40L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK             0x80L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK                                 0x07L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK                                  0x08L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK                                  0xF0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                     0x40L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK                              0x80L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK                        0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK                       0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK                              0x40L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK         0x80L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK                             0x07L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK                              0x08L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK                              0xF0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK                  0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK                              0xFEL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK             0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK   0x1EL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK             0x20L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK                      0x40L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK                     0x80L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK                           0x03L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK                            0xFCL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK                         0x03L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK                             0xFCL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK                 0xFFL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK                            0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK                                0x02L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK                                0x04L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK                                     0xF8L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK                             0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK                                 0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK                               0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK                        0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK                             0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK                      0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK                      0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x03L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x0CL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x30L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK                       0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK  0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK  0x02L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK    0x04L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK    0x08L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK     0x10L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK                       0xE0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK    0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK    0x02L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK      0x04L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK      0x08L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK       0x10L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK                        0xE0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK          0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK          0x02L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK          0x04L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK          0x08L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK                    0x10L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK                            0xE0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK                      0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK                     0x02L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK                           0xFCL
+
+
+// addressBlock: c20_phy_cr3_rdpcspipecrind
+//C20_PHY_CR3_SUP_DIG_IDCODE_LO
+#define C20_PHY_CR3_SUP_DIG_IDCODE_LO__VAL__SHIFT                                                             0x0
+#define C20_PHY_CR3_SUP_DIG_IDCODE_LO__VAL_MASK                                                               0xFFFFL
+//C20_PHY_CR3_SUP_DIG_IDCODE_HI
+#define C20_PHY_CR3_SUP_DIG_IDCODE_HI__VAL__SHIFT                                                             0x0
+#define C20_PHY_CR3_SUP_DIG_IDCODE_HI__VAL_MASK                                                               0xFFFFL
+//C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN__SHIFT                                          0x2
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN__SHIFT                                  0x3
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD__SHIFT                                              0x4
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE__SHIFT                                            0x6
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN__SHIFT                                                    0xa
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN__SHIFT                                            0xb
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD__SHIFT                                  0xc
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN__SHIFT                               0xd
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14__SHIFT                                           0xe
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_MASK                                                 0x0001L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_MASK                                            0x0004L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN_MASK                                    0x0008L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_MASK                                                0x0010L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_MASK                                              0x01C0L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_MASK                                                      0x0400L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN_MASK                                              0x0800L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_MASK                                    0x1000L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN_MASK                                 0x2000L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14_MASK                                             0xC000L
+//C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL__SHIFT                                          0x0
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL__SHIFT                                           0x3
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN__SHIFT                                   0x5
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN__SHIFT                                            0x6
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL__SHIFT                                       0x8
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                               0x9
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10__SHIFT                                           0xa
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_MASK                                            0x0003L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_MASK                                             0x0018L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN_MASK                                     0x0020L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_MASK                                              0x0040L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_MASK                                         0x0100L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10_MASK                                             0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x0200L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x0200L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                                     0x0
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN__SHIFT                             0x2
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                               0x3
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN__SHIFT                                       0x6
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE__SHIFT                                              0x7
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9__SHIFT                                                0x9
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                                       0x0003L
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN_MASK                               0x0004L
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_MASK                                                 0x0038L
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN_MASK                                         0x0040L
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_MASK                                                0x0080L
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9_MASK                                                  0xFE00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xd
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN__SHIFT                                             0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL_MASK                                           0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV_MASK                                           0x001CL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL_MASK                                 0x0060L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                   0x0E00L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                    0x1000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK                                        0x2000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS_MASK                                        0x4000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN_MASK                                               0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN__SHIFT                                          0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL__SHIFT                                          0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD_MASK                                          0x3000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN_MASK                                            0x4000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL_MASK                                            0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_BW_LOW_OVRD_IN
+#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW_MASK                                           0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN
+#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH_MASK                                         0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN__SHIFT                                          0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x3
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0xd
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN_MASK                                            0x0004L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD_MASK                                     0x0008L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK                               0x03E0L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK                                0x0400L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK                      0x1000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK                                  0x2000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN_MASK                          0x4000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_3
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_4
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_5
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_6
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN__SHIFT                                             0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT                                            0xd
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL_MASK                                           0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV_MASK                                           0x001CL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL_MASK                                 0x0060L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                   0x0700L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN_MASK                                               0x1000L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK                                              0xE000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT__SHIFT                                          0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_MASK                                         0x007FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_MASK                                            0x7F00L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN_MASK                                    0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP__SHIFT                                         0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN__SHIFT                                 0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_MASK                                        0x007FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_MASK                                           0x7F00L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN_MASK                                   0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I__SHIFT                                             0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN__SHIFT                                     0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x3
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_MASK                                               0x0003L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN_MASK                                       0x0004L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_MASK                                          0x0018L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN__SHIFT                                          0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x3
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0xd
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN_MASK                                            0x0004L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD_MASK                                     0x0008L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK                               0x03E0L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK                                0x0400L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK                      0x1000L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK                                  0x2000L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN_MASK                          0x4000L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_3
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_5
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_6
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ__SHIFT                                                   0x0
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN__SHIFT                                               0x1
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN__SHIFT                                                  0x2
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN__SHIFT                                                  0x3
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN__SHIFT                                                 0x4
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7__SHIFT                                               0x7
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ_MASK                                                     0x0001L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN_MASK                                                 0x0002L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN_MASK                                                    0x0004L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN_MASK                                                    0x0008L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN_MASK                                                   0x0010L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7_MASK                                                 0xFF80L
+//C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET__SHIFT                                            0x0
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET__SHIFT                                              0xa
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN__SHIFT                                      0xf
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_MASK                                              0x01FFL
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_MASK                                                0x7C00L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN_MASK                                        0x8000L
+//C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_2
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET__SHIFT                                            0x0
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10__SHIFT                                              0xa
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_MASK                                              0x01FFL
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10_MASK                                                0xFC00L
+//C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT                                                  0x2
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT                                                  0x4
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x6
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x7
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x9
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD__SHIFT                                           0xa
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0xb
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD__SHIFT                                            0xc
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0xd
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14__SHIFT                                               0xe
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x0001L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK                                                    0x0004L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK                                                    0x0010L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x0040L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x0080L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x0100L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x0200L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_MASK                                             0x0400L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x0800L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_MASK                                              0x1000L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x2000L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14_MASK                                                 0xC000L
+//C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN
+#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x6
+#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN__SHIFT                                         0x9
+#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
+#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x001FL
+#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x01C0L
+#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN_MASK                                           0x0200L
+#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK                                                  0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV__SHIFT                                        0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xb
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14__SHIFT                                            0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV_MASK                                           0x000EL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV_MASK                                          0x0030L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0380L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK                                        0x0400L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS_MASK                                        0x0800L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD_MASK                                          0x3000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14_MASK                                              0xC000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_BW_LOW_ASIC_IN
+#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW_MASK                                           0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN
+#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH_MASK                                         0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x3
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD_MASK                                     0x0004L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK                               0x00F8L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK                                0x0100L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK                                  0x0200L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_3
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_4
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_5
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_6
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV__SHIFT                                        0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x6
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9__SHIFT                                             0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV_MASK                                           0x000EL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV_MASK                                          0x0030L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x01C0L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9_MASK                                               0xFE00L
+//C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT__SHIFT                                          0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS_MASK                                         0x007FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_MASK                                            0x3F80L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP__SHIFT                                         0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS_MASK                                        0x007FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_MASK                                           0x3F80L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I__SHIFT                                             0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I_MASK                                               0x0003L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO_MASK                                          0x000CL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x3
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD_MASK                                     0x0004L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK                               0x00F8L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK                                0x0100L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK                                  0x0200L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_3
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_5
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_6
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                            0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                      0xb
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14__SHIFT                                      0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                              0x0600L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                        0x3800L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14_MASK                                        0xC000L
+//C20_PHY_CR3_SUP_DIG_ASIC_IN_0
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__PHY_RESET__SHIFT                                                       0x0
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_CLK_EN__SHIFT                                                      0x1
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN__SHIFT                                                 0x2
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_USE_PAD__SHIFT                                                     0x3
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__TEST_BURNIN__SHIFT                                                     0x4
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN__SHIFT                                                  0x5
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RTUNE_REQ__SHIFT                                                       0x6
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RES_REQ_IN__SHIFT                                                      0x7
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RES_ACK_IN__SHIFT                                                      0x8
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__BG_EN__SHIFT                                                           0x9
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                              0xa
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_RANGE__SHIFT                                                       0xb
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE__SHIFT                                                 0xe
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RESERVED_15_15__SHIFT                                                  0xf
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__PHY_RESET_MASK                                                         0x0001L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_CLK_EN_MASK                                                        0x0002L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN_MASK                                                   0x0004L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_USE_PAD_MASK                                                       0x0008L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__TEST_BURNIN_MASK                                                       0x0010L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN_MASK                                                    0x0020L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RTUNE_REQ_MASK                                                         0x0040L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RES_REQ_IN_MASK                                                        0x0080L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RES_ACK_IN_MASK                                                        0x0100L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__BG_EN_MASK                                                             0x0200L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL_MASK                                                0x0400L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_RANGE_MASK                                                         0x3800L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE_MASK                                                   0x4000L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RESERVED_15_15_MASK                                                    0x8000L
+//C20_PHY_CR3_SUP_DIG_ASIC_IN_1
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__SUP_MISC__SHIFT                                                        0x0
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN__SHIFT                                                0x8
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN__SHIFT                                              0x9
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL__SHIFT                                                 0xa
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL__SHIFT                                                  0xc
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__RESERVED_15_14__SHIFT                                                  0xe
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__SUP_MISC_MASK                                                          0x00FFL
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN_MASK                                                  0x0100L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN_MASK                                                0x0200L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL_MASK                                                   0x0C00L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL_MASK                                                    0x3000L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__RESERVED_15_14_MASK                                                    0xC000L
+//C20_PHY_CR3_SUP_DIG_ASIC_OUT_0
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT__SHIFT                                              0x0
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__MPLLA_STATE__SHIFT                                                    0x1
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__MPLLB_STATE__SHIFT                                                    0x2
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RTUNE_ACK__SHIFT                                                      0x3
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT__SHIFT                                                    0x4
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT__SHIFT                                                    0x5
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__DTB_OUT__SHIFT                                                        0x6
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RESERVED_15_8__SHIFT                                                  0x8
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT_MASK                                                0x0001L
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__MPLLA_STATE_MASK                                                      0x0002L
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__MPLLB_STATE_MASK                                                      0x0004L
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RTUNE_ACK_MASK                                                        0x0008L
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT_MASK                                                      0x0010L
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT_MASK                                                      0x0020L
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__DTB_OUT_MASK                                                          0x00C0L
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RESERVED_15_8_MASK                                                    0xFF00L
+//C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN
+#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x5
+#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN__SHIFT                                                 0x8
+#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET__SHIFT                                                0x9
+#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14__SHIFT                                                0xe
+#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x001FL
+#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x00E0L
+#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN_MASK                                                   0x0100L
+#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET_MASK                                                  0x3E00L
+#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14_MASK                                                  0xC000L
+//C20_PHY_CR3_SUP_DIG_SUP_OVRD_MISC
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN__SHIFT                                            0x8
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9__SHIFT                                               0x9
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN_MASK                                              0x0100L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9_MASK                                                 0xFE00L
+//C20_PHY_CR3_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN
+#define C20_PHY_CR3_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET__SHIFT                                 0x0
+#define C20_PHY_CR3_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET_MASK                                   0x01FFL
+#define C20_PHY_CR3_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN
+#define C20_PHY_CR3_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET__SHIFT                                 0x0
+#define C20_PHY_CR3_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET_MASK                                   0x01FFL
+#define C20_PHY_CR3_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL__SHIFT                                0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL__SHIFT                                  0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL__SHIFT                             0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10__SHIFT                                          0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL_MASK                                  0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL_MASK                                    0x0004L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL_MASK                               0x01F0L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10_MASK                                            0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY__SHIFT                                           0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE__SHIFT                                      0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7__SHIFT                                           0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE_MASK                                           0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY_MASK                                             0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE_MASK                                        0x007CL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7_MASK                                             0xFF80L
+//C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__RESERVED__SHIFT                                                     0x1
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL__SHIFT                                                0x6
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7__SHIFT                                                0x7
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x0001L
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__RESERVED_MASK                                                       0x0002L
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x0004L
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x0038L
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL_MASK                                                  0x0040L
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7_MASK                                                  0xFF80L
+//C20_PHY_CR3_SUP_DIG_RTUNE_STAT
+#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__RTUNE_STATE__SHIFT                                                    0xa
+#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE__SHIFT                                                 0xd
+#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__RESERVED_15_15__SHIFT                                                 0xf
+#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x03FFL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__RTUNE_STATE_MASK                                                      0x1C00L
+#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE_MASK                                                   0x6000L
+#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__RESERVED_15_15_MASK                                                   0x8000L
+//C20_PHY_CR3_SUP_DIG_RTUNE_RX_SET_VAL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
+#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x003FL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0xFFC0L
+//C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x03FFL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x03FFL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR3_SUP_DIG_RTUNE_RX_STAT
+#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x003FL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_STAT
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x03FFL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0xFC00L
+//C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_STAT
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x03FFL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0xFC00L
+//C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG__SHIFT                                                  0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10__SHIFT                                       0xa
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG_MASK                                                    0x03FFL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10_MASK                                         0xFC00L
+//C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_1
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN__SHIFT                                                 0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10__SHIFT                                       0xa
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN_MASK                                                   0x03FFL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10_MASK                                         0xFC00L
+//C20_PHY_CR3_SUP_DIG_RTUNE_FAST_FLAGS
+#define C20_PHY_CR3_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE__SHIFT                                               0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR3_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE_MASK                                                 0x0001L
+#define C20_PHY_CR3_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER__SHIFT                                  0xa
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11__SHIFT                                    0xb
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x01FFL
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x0200L
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER_MASK                                    0x0400L
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11_MASK                                      0xF800L
+//C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x01FFL
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x00FFL
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x001FL
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x0020L
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE__SHIFT                                     0x1
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE__SHIFT                                     0x2
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE__SHIFT                                      0x4
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6__SHIFT                                     0x6
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE_MASK                                        0x0001L
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE_MASK                                       0x0002L
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE_MASK                                       0x000CL
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE_MASK                                        0x0030L
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6_MASK                                       0xFFC0L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL__SHIFT                                0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL__SHIFT                                 0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN__SHIFT                               0x6
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE__SHIFT                             0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE__SHIFT                                0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT_MASK                                      0x000FL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL_MASK                                  0x0010L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL_MASK                                   0x0020L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE_MASK                               0x7F80L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE_MASK                                  0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE__SHIFT                               0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14__SHIFT                              0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK                                      0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK                              0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK                               0x0008L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK                                0x0010L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE_MASK                                 0x3C00L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14_MASK                                0xC000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                                      0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                                       0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                                      0x6
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xd
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP__SHIFT                             0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                                        0x0010L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                                         0x0020L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                                        0x0040L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0080L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0100L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0200L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x1000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x2000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x4000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP_MASK                               0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME__SHIFT               0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME__SHIFT                 0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME_MASK                 0x03FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME_MASK                   0x3C00L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK                         0xC000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME__SHIFT           0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME__SHIFT                         0xb
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME_MASK             0x07FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME_MASK                           0xF800L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME__SHIFT                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME__SHIFT                  0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME__SHIFT               0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME_MASK                          0x001FL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME_MASK                    0x03E0L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME_MASK                 0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME__SHIFT                  0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME__SHIFT                0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME_MASK                    0x007FL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME_MASK                  0x0F80L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT                     0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL__SHIFT                       0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12__SHIFT                           0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK                       0x00FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL_MASK                         0x0F00L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12_MASK                             0xF000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT             0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP__SHIFT          0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG__SHIFT         0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK               0x00FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP_MASK            0x0300L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG_MASK           0x0C00L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0__SHIFT                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0__SHIFT                      0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0_MASK                        0x00FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0_MASK                        0xFF00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1__SHIFT                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1__SHIFT                      0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1_MASK                        0x00FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1_MASK                        0xFF00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2__SHIFT                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2__SHIFT                      0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2_MASK                        0x00FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2_MASK                        0xFF00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3__SHIFT                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3__SHIFT                      0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3_MASK                        0x00FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3_MASK                        0xFF00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME__SHIFT         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME__SHIFT                   0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME_MASK           0x03FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME_MASK                     0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME__SHIFT     0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11__SHIFT                       0xb
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME_MASK       0x07FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11_MASK                         0xF800L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME__SHIFT              0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10__SHIFT                       0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME_MASK                0x03FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10_MASK                         0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME__SHIFT             0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10__SHIFT                       0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME_MASK               0x03FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10_MASK                         0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7__SHIFT                        0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME_MASK                 0x007FL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7_MASK                          0xFF80L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN__SHIFT                 0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2__SHIFT                               0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN_MASK                   0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2_MASK                                 0xFFFCL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_FRAC_OUT
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_SSC_RAMP
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_CONFIG
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK                                          0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK                                           0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN__SHIFT                            0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE__SHIFT                                   0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL_MASK                             0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN_MASK                              0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE_MASK                                     0x007CL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK                                      0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK                              0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK                               0x0008L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK                                0x0010L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC__SHIFT                                 0xd
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC__SHIFT                                 0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0010L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0020L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0100L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x0200L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x0400L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x0800L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x1000L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC_MASK                                   0x2000L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC_MASK                                   0x4000L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME__SHIFT                          0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME_MASK                              0x00FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME_MASK                            0x3F00L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK                         0xC000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME__SHIFT                       0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME__SHIFT                          0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME_MASK                         0x00FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME_MASK                            0xFF00L
+//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME__SHIFT                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME__SHIFT                         0x6
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME_MASK                        0x003FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME_MASK                           0x0FC0L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME__SHIFT                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME__SHIFT                           0x6
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME_MASK                          0x003FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME_MASK                             0x0FC0L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS__SHIFT                0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS_MASK                  0x001FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7__SHIFT                        0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME_MASK                 0x007FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7_MASK                          0xFF80L
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_FRAC_OUT
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_SSC_RAMP
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_CONFIG
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK                                          0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK                                           0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT__SHIFT                                      0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK__SHIFT                                             0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC__SHIFT                                              0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT__SHIFT                                          0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL__SHIFT                                         0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10__SHIFT                                             0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT_MASK                                           0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT_MASK                                        0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK_MASK                                               0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC_MASK                                                0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT_MASK                                            0x01F0L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL_MASK                                           0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10_MASK                                               0xFC00L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN__SHIFT                                                 0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START__SHIFT                                    0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN__SHIFT                                            0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL__SHIFT                                      0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START__SHIFT                                   0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL__SHIFT                                         0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN__SHIFT                                                 0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST__SHIFT                                           0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE__SHIFT                                               0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST__SHIFT                                             0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN_MASK                                                   0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START_MASK                                      0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN_MASK                                              0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL_MASK                                        0x0030L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START_MASK                                     0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL_MASK                                           0x0380L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN_MASK                                                   0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST_MASK                                             0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE_MASK                                                 0x3000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST_MASK                                               0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP__SHIFT                              0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL__SHIFT                                       0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST__SHIFT                                       0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT__SHIFT                                 0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN__SHIFT                                 0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN__SHIFT                                   0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN__SHIFT                               0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN__SHIFT                               0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN__SHIFT                                0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN__SHIFT                            0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12__SHIFT                                      0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP_MASK                                0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL_MASK                                         0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST_MASK                                         0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT_MASK                                   0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN_MASK                                   0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN_MASK                                     0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN_MASK                              0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12_MASK                                        0xF000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL__SHIFT                                       0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST__SHIFT                                       0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT__SHIFT                                 0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN__SHIFT                               0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN__SHIFT                               0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN__SHIFT                               0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN__SHIFT                                0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN__SHIFT                           0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE__SHIFT                                 0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY__SHIFT                                   0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14__SHIFT                                      0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_MASK                                         0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST_MASK                                         0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT_MASK                                   0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN_MASK                             0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE_MASK                                   0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY_MASK                                     0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14_MASK                                        0xC000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN__SHIFT                                                  0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START__SHIFT                                          0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN__SHIFT                                  0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START__SHIFT                                          0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN__SHIFT                                  0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER__SHIFT                                0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP__SHIFT                                0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                          0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_MASK                                                    0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_MASK                                            0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN_MASK                                    0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_MASK                                            0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN_MASK                                    0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER_MASK                                  0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP_MASK                                  0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                            0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                      0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                              0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                   0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                           0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE__SHIFT                                  0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_MASK                                        0x000CL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_MASK                                     0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                             0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE_MASK                                       0x0180L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE_MASK                                    0x7E00L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL__SHIFT                                   0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL__SHIFT                                0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL_MASK                                      0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL_MASK                                     0x0006L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL_MASK                                  0x0018L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP__SHIFT                            0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                    0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN__SHIFT                            0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                         0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                         0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT__SHIFT                               0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                        0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_MASK                              0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                      0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN_MASK                              0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                           0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                           0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_MASK                                 0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN__SHIFT                                 0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN__SHIFT                              0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN__SHIFT                      0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN__SHIFT                            0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN__SHIFT                    0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN__SHIFT                            0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN__SHIFT                                  0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN__SHIFT                          0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN__SHIFT                              0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_MASK                                   0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN_MASK                           0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN_MASK                           0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_MASK                                0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN_MASK                        0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_MASK                              0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN_MASK                      0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_MASK                              0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN_MASK                           0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_MASK                                    0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN_MASK                            0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_MASK                                0x4000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN__SHIFT                                0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN_MASK                        0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK                                  0xFFF0L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC__SHIFT                              0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT__SHIFT                               0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC_MASK                                0x003FL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT_MASK                                 0xFFC0L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                         0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                         0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT__SHIFT                                   0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE__SHIFT                                   0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                     0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                        0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                           0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                           0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_MASK                                     0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_MASK                                     0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                       0x4000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN__SHIFT                                 0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN__SHIFT                                0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                        0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN__SHIFT                         0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN__SHIFT                             0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_MASK                                   0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN_MASK                           0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN_MASK                           0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                          0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN_MASK                           0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_MASK                               0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN__SHIFT                                0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN_MASK                        0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK                                  0xFFF0L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC__SHIFT                              0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT__SHIFT                               0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC_MASK                                0x003FL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT_MASK                                 0xFFC0L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                            0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                      0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                          0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                         0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                       0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                              0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                        0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                            0x000CL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                           0x3FF0L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                         0x4000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_OVRD_OUT
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC__SHIFT                                          0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_MASK                                            0x00FFL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE__SHIFT                            0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN__SHIFT                    0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE__SHIFT                              0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN__SHIFT                      0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_MASK                              0x00FFL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN_MASK                      0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_MASK                                0x1E00L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN_MASK                        0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG__SHIFT                                   0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1__SHIFT                                        0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT__SHIFT                                  0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START__SHIFT                             0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG__SHIFT                              0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST__SHIFT                                  0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT__SHIFT                            0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG__SHIFT                                   0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2__SHIFT                           0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7__SHIFT                                0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST__SHIFT                           0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT__SHIFT                                 0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX__SHIFT                             0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_MASK                                     0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1_MASK                                          0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT_MASK                                    0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START_MASK                               0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG_MASK                                0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST_MASK                                    0x0060L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT_MASK                              0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG_MASK                                     0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2_MASK                             0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7_MASK                                  0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST_MASK                             0x1800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT_MASK                                   0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX_MASK                               0xC000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX__SHIFT                             0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0__SHIFT                         0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6__SHIFT                                        0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0__SHIFT                              0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS__SHIFT                                   0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST_MASK                                      0x0003L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX_MASK                               0x000CL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0_MASK                           0x0030L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6_MASK                                          0x00C0L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0_MASK                                0x7F00L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS_MASK                                     0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF__SHIFT                                 0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP__SHIFT                                 0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB__SHIFT                                      0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP__SHIFT                                 0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE__SHIFT                                 0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5__SHIFT                                        0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON__SHIFT                                 0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN__SHIFT                            0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN__SHIFT                           0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF_MASK                                   0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP_MASK                                   0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB_MASK                                        0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP_MASK                                   0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE_MASK                                   0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5_MASK                                          0x0060L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON_MASK                                   0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN_MASK                              0x0F00L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN_MASK                             0xF000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE__SHIFT                          0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE__SHIFT                                    0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM__SHIFT                                0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR__SHIFT                                0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF__SHIFT                                        0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9__SHIFT                                       0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE_MASK                            0x0003L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE_MASK                                      0x000CL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM_MASK                                  0x0030L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR_MASK                                  0x00C0L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF_MASK                                          0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9_MASK                                         0x7E00L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF__SHIFT                                    0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR__SHIFT                           0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL__SHIFT                                0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0_MASK                                      0x007FL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF_MASK                                      0x0180L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR_MASK                             0x7E00L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL_MASK                                  0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS__SHIFT                          0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC__SHIFT                            0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS__SHIFT                               0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4__SHIFT                                      0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG__SHIFT                                0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL__SHIFT                             0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE__SHIFT                             0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG__SHIFT                              0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL__SHIFT                                0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG__SHIFT                                 0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG__SHIFT                           0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET__SHIFT                              0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG__SHIFT                               0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0_MASK                                        0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS_MASK                            0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC_MASK                              0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS_MASK                                 0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4_MASK                                        0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG_MASK                                  0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL_MASK                               0x00C0L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE_MASK                               0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG_MASK                                0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL_MASK                                  0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG_MASK                                   0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG_MASK                             0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET_MASK                                0x4000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG_MASK                                 0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV__SHIFT                                 0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_MASK                                   0xFFFFL
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16__SHIFT                           0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT__SHIFT                              0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22__SHIFT                           0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16_MASK                             0x003FL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT_MASK                                0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22_MASK                             0x3F80L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN__SHIFT                      0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN__SHIFT                           0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW__SHIFT                              0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW__SHIFT                                   0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN__SHIFT                       0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG__SHIFT                            0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90__SHIFT                            0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN_MASK                        0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN_MASK                             0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW_MASK                                0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW_MASK                                     0x0FF8L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN_MASK                         0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG_MASK                              0x6000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90_MASK                              0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0__SHIFT                                     0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0_MASK                                       0xFFFFL
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0__SHIFT                                     0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0_MASK                                       0xFFFFL
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0__SHIFT                                  0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0_MASK                                    0x00FFL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT__SHIFT                       0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT__SHIFT                       0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV__SHIFT                           0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN__SHIFT                                  0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK__SHIFT                          0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6__SHIFT                                      0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS__SHIFT                          0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS__SHIFT                               0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT__SHIFT                          0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG__SHIFT                           0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR__SHIFT                          0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO__SHIFT                              0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV__SHIFT                             0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90__SHIFT                            0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT_MASK                         0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT_MASK                         0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV_MASK                             0x000CL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN_MASK                                    0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK_MASK                            0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6_MASK                                        0x00C0L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS_MASK                            0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS_MASK                                 0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT_MASK                            0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG_MASK                             0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR_MASK                            0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO_MASK                                0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV_MASK                               0x4000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90_MASK                              0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE__SHIFT                             0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG__SHIFT                              0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL__SHIFT                                0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG__SHIFT                                 0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN__SHIFT                          0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG__SHIFT                           0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET__SHIFT                              0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG__SHIFT                               0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP__SHIFT                            0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13__SHIFT                                    0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT__SHIFT                              0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE_MASK                               0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG_MASK                                0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL_MASK                                  0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG_MASK                                   0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN_MASK                            0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG_MASK                             0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET_MASK                                0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG_MASK                                 0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP_MASK                              0x1F00L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13_MASK                                      0x6000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT_MASK                                0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER__SHIFT                 0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ__SHIFT                       0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE__SHIFT                  0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED__SHIFT                       0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV__SHIFT                         0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H__SHIFT                         0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP__SHIFT                        0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP__SHIFT                    0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP__SHIFT                      0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP__SHIFT                       0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE__SHIFT                          0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER_MASK                   0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ_MASK                         0x0006L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE_MASK                    0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED_MASK                         0x00F0L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV_MASK                           0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H_MASK                           0x0600L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP_MASK                          0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP_MASK                      0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP_MASK                        0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP_MASK                         0x4000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE_MASK                            0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN__SHIFT                 0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN__SHIFT                         0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK__SHIFT                            0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5__SHIFT                                      0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8__SHIFT                                     0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START__SHIFT                     0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE__SHIFT                        0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST__SHIFT                             0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN_MASK                   0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN_MASK                           0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_MASK                              0x001CL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5_MASK                                        0x00E0L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8_MASK                                       0x0F00L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START_MASK                       0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE_MASK                          0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST_MASK                               0xC000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT__SHIFT                             0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW__SHIFT                         0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF__SHIFT                    0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS__SHIFT                               0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH__SHIFT                       0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN__SHIFT                           0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP__SHIFT                             0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO__SHIFT                            0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR__SHIFT                        0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING__SHIFT                           0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR__SHIFT                          0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF__SHIFT                    0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK__SHIFT                    0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG__SHIFT                        0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT_MASK                               0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW_MASK                           0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF_MASK                      0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS_MASK                                 0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH_MASK                         0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN_MASK                             0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP_MASK                               0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO_MASK                              0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR_MASK                          0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING_MASK                             0x0600L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR_MASK                            0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF_MASK                      0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK_MASK                      0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG_MASK                          0xC000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT__SHIFT                       0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING__SHIFT                        0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR__SHIFT                        0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2__SHIFT                    0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP__SHIFT                      0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED__SHIFT                       0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2__SHIFT                     0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X__SHIFT                               0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD__SHIFT                                 0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N__SHIFT                             0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC__SHIFT                           0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER__SHIFT                            0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT_MASK                         0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING_MASK                          0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR_MASK                          0x000CL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2_MASK                      0x0030L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP_MASK                        0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_MASK                         0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2_MASK                       0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X_MASK                                 0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD_MASK                                   0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N_MASK                               0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC_MASK                             0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER_MASK                              0xE000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF__SHIFT                          0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF__SHIFT                         0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL__SHIFT                          0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0__SHIFT                        0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH__SHIFT                         0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2__SHIFT                          0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES__SHIFT                             0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF_MASK                            0x0007L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF_MASK                           0x0038L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL_MASK                            0x00C0L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0_MASK                          0x0300L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH_MASK                           0x0C00L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2_MASK                            0x3000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES_MASK                               0xC000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG__SHIFT                            0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC__SHIFT                             0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL__SHIFT                         0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP__SHIFT                        0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK__SHIFT                          0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN__SHIFT                    0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST__SHIFT                              0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0_MASK                                        0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG_MASK                              0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC_MASK                               0x000CL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL_MASK                           0x0030L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP_MASK                          0x00C0L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK_MASK                            0x0F00L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN_MASK                      0x3000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST_MASK                                0xC000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                 0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                   0xFFFFL
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                 0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                   0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_CMN_CTL
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_CMN_CLK_GATE_CTL
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN__SHIFT                                                 0x2
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x5
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN__SHIFT                                                 0x6
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE__SHIFT                                              0x8
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x9
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ__SHIFT                                                    0xa
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0xb
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE__SHIFT                                           0xc
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_MASK                                                   0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_MASK                                                   0x0040L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_MASK                                                0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0200L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_MASK                                                      0x0400L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x0800L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE_MASK                                             0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0xE000L
+//C20_PHY_CR3_RAWCMN_DIG_MPLL_CONFIG
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME__SHIFT                                         0x6
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10__SHIFT                                             0xa
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME_MASK                                                0x003FL
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME_MASK                                           0x03C0L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10_MASK                                               0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_CTRL
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4__SHIFT                                             0x4
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE_MASK                                              0x000FL
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4_MASK                                               0xFFF0L
+//C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_ADDR
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_ADDR__ADDR__SHIFT                                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_ADDR__ADDR_MASK                                                        0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_DATA
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_DATA__DATA__SHIFT                                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_DATA__DATA_MASK                                                        0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_FLAGS
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_ACCUM
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_ACCUM__VAL__SHIFT                                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_ACCUM__VAL_MASK                                                        0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLL_IN
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN__SHIFT                                                   0x3
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__RESERVED_15_4__SHIFT                                                  0x4
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE_MASK                                           0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN_MASK                                                     0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__RESERVED_15_4_MASK                                                    0xFFF0L
+//C20_PHY_CR3_RAWCMN_DIG_FW_PWRUP_DONE
+#define C20_PHY_CR3_RAWCMN_DIG_FW_PWRUP_DONE__DONE__SHIFT                                                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR3_RAWCMN_DIG_FW_PWRUP_DONE__DONE_MASK                                                       0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_STATIC_CONFIG_STATUS
+#define C20_PHY_CR3_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE_MASK                                            0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_FW_CONFIG_STATUS
+#define C20_PHY_CR3_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE__SHIFT                                          0x1
+#define C20_PHY_CR3_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE_MASK                                            0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE_MASK                                            0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_CMN_STATUS_1
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2__SHIFT                                             0x2
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE_MASK                                               0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2_MASK                                               0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x2
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0x3
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0x4
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0x5
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x7
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x9
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0xa
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0xc
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL_MASK                       0x0003L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN_MASK                        0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK                       0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN_MASK                        0x0010L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK                        0x0020L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL_MASK                       0x0180L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN_MASK                        0x0200L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK                       0x0400L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK                        0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_FRAC_UPDATE
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE__SHIFT                               0x1
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN_MASK                               0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE_MASK                                 0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_FRAC_UPDATE
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE__SHIFT                               0x1
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN_MASK                               0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE_MASK                                 0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_CONFIG_MASTER_VERSION
+#define C20_PHY_CR3_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION_MASK                                     0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_0
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_1
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_2
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_3
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR3_RAWCMN_DIG_CREG_ACCESS_CTL
+#define C20_PHY_CR3_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN__SHIFT                              0x8
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN_MASK                                0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN__SHIFT                              0x8
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN_MASK                                0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_0
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11__SHIFT                                          0xb
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC_MASK                                                  0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL_MASK                                             0x0700L
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11_MASK                                            0xF800L
+//C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_1
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET__SHIFT                                        0x5
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14__SHIFT                                          0xe
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL_MASK                                              0x001FL
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET_MASK                                          0x3FE0L
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14_MASK                                            0xC000L
+//C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_2
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET__SHIFT                                        0x5
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14__SHIFT                                          0xe
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET_MASK                                            0x001FL
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET_MASK                                          0x3FE0L
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14_MASK                                            0xC000L
+//C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_3
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID__SHIFT                                               0x0
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10__SHIFT                                          0xa
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID_MASK                                                 0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10_MASK                                            0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN__SHIFT                                         0xf
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER_MASK                                              0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN_MASK                                              0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN_MASK                                           0x8000L
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV__SHIFT                                            0x8
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0xb
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD__SHIFT                                          0xe
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV_MASK                                              0x0700L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV_MASK                                            0x1800L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD_MASK                                            0xC000L
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_2
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_3
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH__SHIFT                                               0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH_MASK                                                 0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_4
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB_MASK                                            0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_5
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK                                       0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV__SHIFT                                     0xa
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL__SHIFT                                            0xd
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xe
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB_MASK                                            0x000FL
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK                                       0x01F0L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD_MASK                                           0x0200L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV_MASK                                       0x1C00L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL_MASK                                              0x2000L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN_MASK                                                 0x4000L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_7
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN_MASK                                                0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_8
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT_MASK                                               0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_9
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM_MASK                                                0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV__SHIFT                                            0xd
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER_MASK                                              0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN_MASK                                              0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV_MASK                                              0xE000L
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE__SHIFT                                          0xa
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV_MASK                                            0x0300L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE_MASK                                            0x7C00L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_2
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP__SHIFT                                               0x7
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO__SHIFT                                              0xe
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT_MASK                                                  0x007FL
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP_MASK                                                 0x3F80L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO_MASK                                                0xC000L
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_3
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS__SHIFT                                            0x7
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I__SHIFT                                                   0xe
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS_MASK                                               0x007FL
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS_MASK                                              0x3F80L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I_MASK                                                     0xC000L
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_4
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB_MASK                                            0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_5
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK                                       0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV__SHIFT                                     0xa
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xd
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB_MASK                                            0x000FL
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK                                       0x01F0L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD_MASK                                           0x0200L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV_MASK                                       0x1C00L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN_MASK                                                 0x2000L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_7
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN_MASK                                                0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_8
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT_MASK                                               0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_9
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM_MASK                                                0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_10
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV_MASK                                               0x0007L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV_MASK                                     0x0018L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN__SHIFT                                        0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN_MASK                                          0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3_MASK                                       0xFFF8L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0__SHIFT                           0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0_MASK                                  0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0_MASK                             0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1__SHIFT                           0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1_MASK                                  0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1_MASK                             0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2__SHIFT                           0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2_MASK                                  0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2_MASK                             0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3__SHIFT                           0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3_MASK                                  0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3_MASK                             0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL__SHIFT                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL_MASK                                0x0003L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_DONE
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0__SHIFT                           0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0_MASK                                  0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0_MASK                             0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1__SHIFT                           0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1_MASK                                  0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1_MASK                             0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2__SHIFT                           0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2_MASK                                  0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2_MASK                             0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3__SHIFT                           0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3_MASK                                  0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3_MASK                             0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL__SHIFT                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL_MASK                                0x0003L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_DONE
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12__SHIFT                                          0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE_MASK                                                0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12_MASK                                            0xF000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12__SHIFT                                          0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE_MASK                                                0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12_MASK                                            0xF000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_IN_RECAL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_IN_RECAL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                       0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6__SHIFT                                           0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                         0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                       0x0010L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6_MASK                                             0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO__SHIFT                                       0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                              0x4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                               0x5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                          0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO_MASK                                         0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                                0x0010L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                            0x8
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12__SHIFT                                         0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                      0x0010L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                              0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12_MASK                                           0xF000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN__SHIFT                                            0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN__SHIFT                                                0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                        0x4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK__SHIFT                                                0x5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN_MASK                                              0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN_MASK                                                  0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL_MASK                                          0x0010L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK_MASK                                                  0x0020L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6_MASK                                               0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                               0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                              0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                               0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL__SHIFT                                  0x4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN__SHIFT                                   0x5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL__SHIFT                                   0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL_MASK                                0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL_MASK                                0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN_MASK                                 0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL_MASK                                    0x0010L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN_MASK                                     0x0020L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL_MASK                                     0x0040L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK__SHIFT                                          0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4__SHIFT                                            0x4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK_MASK                                            0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK_MASK                                            0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4_MASK                                              0xFFF0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL_MASK                    0x0003L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL_MASK                    0x0003L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                                0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT__SHIFT                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE__SHIFT                              0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT_MASK                                0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE_MASK                                0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                        0x003FL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                    0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0_MASK                                  0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                        0x003FL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                    0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1_MASK                                  0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                        0x003FL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                    0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2_MASK                                  0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                        0x003FL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                    0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3_MASK                                  0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                        0x003FL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                    0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4_MASK                                  0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                        0x003FL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                    0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5_MASK                                  0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                        0x003FL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                    0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6_MASK                                  0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_7
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                        0x003FL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                    0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7_MASK                                  0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL__SHIFT                             0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL__SHIFT                             0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN__SHIFT                              0x4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL__SHIFT                         0x5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL_MASK                               0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL_MASK                               0x000CL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN_MASK                                0x0010L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL_MASK                           0x0060L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS_MASK                                         0x0018L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5_MASK                                                0xFFE0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OUT
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_AON_FW_VERSION_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_FW_VERSION_0__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_FW_VERSION_0__VAL_MASK                                                     0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_AON_FW_VERSION_1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_FW_VERSION_1__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_FW_VERSION_1__VAL_MASK                                                     0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_AON_RAW_VERSION
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RAW_VERSION__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RAW_VERSION__VAL_MASK                                                      0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_EOF_ADDR
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_BOC_ADDR
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL__SHIFT                                     0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN__SHIFT                                      0x7
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10__SHIFT                                           0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL_MASK                                    0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL_MASK                                       0x0010L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL_MASK                                       0x0040L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN_MASK                                        0x0080L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10_MASK                                             0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL_MASK                                            0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN__SHIFT                                            0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN__SHIFT                                            0x4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE__SHIFT                                        0x5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE__SHIFT                                        0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL__SHIFT                                            0x9
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT__SHIFT                                         0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT__SHIFT                                         0xb
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF__SHIFT                                         0xd
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW__SHIFT                                          0xe
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN_MASK                                              0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN_MASK                                              0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN_MASK                                              0x0010L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE_MASK                                          0x0020L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE_MASK                                          0x0040L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ_MASK                                           0x0080L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ_MASK                                           0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL_MASK                                              0x0200L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT_MASK                                           0x0400L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT_MASK                                           0x0800L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL_MASK                                          0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF_MASK                                           0x2000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW_MASK                                            0x4000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL__SHIFT                            0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL_MASK                              0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_METADATA_LOCATION
+#define C20_PHY_CR3_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION_MASK                                  0x7FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST__SHIFT                         0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN__SHIFT                 0xf
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_MASK                           0x7FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN_MASK                   0x8000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR3_LANE0_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_LANE0_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR3_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR3_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR3_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR3_LANE0_DIG_TX_FIFO_CTL
+#define C20_PHY_CR3_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR3_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR3_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR3_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR3_LANE0_DIG_RX_LBERT_ERR
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_CDR_STAT
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR3_LANE1_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_LANE1_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR3_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR3_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR3_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR3_LANE1_DIG_TX_FIFO_CTL
+#define C20_PHY_CR3_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR3_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR3_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR3_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR3_LANE1_DIG_RX_LBERT_ERR
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_CDR_STAT
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR3_LANE2_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_LANE2_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR3_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR3_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR3_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR3_LANE2_DIG_TX_FIFO_CTL
+#define C20_PHY_CR3_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR3_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR3_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR3_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR3_LANE2_DIG_RX_LBERT_ERR
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_CDR_STAT
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR3_LANE3_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_LANE3_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR3_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR3_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR3_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR3_LANE3_DIG_TX_FIFO_CTL
+#define C20_PHY_CR3_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR3_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR3_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR3_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR3_LANE3_DIG_RX_LBERT_ERR
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_CDR_STAT
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_CR_LOCK
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_SUP
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_CR_LOCK
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_SUP
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_CR_LOCK
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_SUP
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_CR_LOCK
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_SUP
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_IN_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_OUT_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_IN_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_OUT_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_IN_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_OUT_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_IN_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_OUT_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR3_LANEX_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_LANEX_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR3_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR3_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR3_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR3_LANEX_DIG_TX_FIFO_CTL
+#define C20_PHY_CR3_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR3_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR3_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR3_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR3_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR3_LANEX_DIG_RX_LBERT_ERR
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_CDR_STAT
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_CR_LOCK
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_SUP
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_IN_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_OUT_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+
+
+// addressBlock: c20_phy_lane0_pipe3_rdpcspipemsgbusind
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK           0x02L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK                  0x04L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK                 0x08L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK             0x10L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK                           0xE0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK                      0x7FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK                   0x80L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK   0xFFL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK                               0x02L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK                            0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK                                  0x02L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK                                 0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK                         0x02L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK                           0x04L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK                                  0xF8L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK              0x02L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK                             0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                         0x40L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK                                  0x80L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK                            0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                    0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK                                  0x40L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK             0x80L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK                                 0x07L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK                                  0x08L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK                                  0xF0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                     0x40L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK                              0x80L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK                        0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK                       0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK                              0x40L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK         0x80L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK                             0x07L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK                              0x08L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK                              0xF0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK                  0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK                              0xFEL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK             0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK   0x1EL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK             0x20L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK                      0x40L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK                     0x80L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK                           0x03L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK                            0xFCL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK                         0x03L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK                             0xFCL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK                 0xFFL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK                            0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK                                0x02L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK                                0x04L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK                                     0xF8L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK                             0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK                                 0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK                               0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK                        0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK                             0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK                      0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK                      0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x03L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x0CL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x30L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK                       0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK  0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK  0x02L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK    0x04L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK    0x08L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK     0x10L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK                       0xE0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK    0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK    0x02L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK      0x04L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK      0x08L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK       0x10L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK                        0xE0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK          0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK          0x02L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK          0x04L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK          0x08L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK                    0x10L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK                            0xE0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK                      0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK                     0x02L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK                           0xFCL
+
+
+// addressBlock: c20_phy_lane1_pipe3_rdpcspipemsgbusind
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK           0x02L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK                  0x04L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK                 0x08L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK             0x10L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK                           0xE0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK                      0x7FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK                   0x80L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK   0xFFL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK                               0x02L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK                            0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK                                  0x02L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK                                 0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK                         0x02L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK                           0x04L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK                                  0xF8L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK              0x02L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK                             0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                         0x40L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK                                  0x80L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK                            0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                    0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK                                  0x40L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK             0x80L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK                                 0x07L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK                                  0x08L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK                                  0xF0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                     0x40L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK                              0x80L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK                        0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK                       0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK                              0x40L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK         0x80L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK                             0x07L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK                              0x08L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK                              0xF0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK                  0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK                              0xFEL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK             0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK   0x1EL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK             0x20L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK                      0x40L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK                     0x80L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK                           0x03L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK                            0xFCL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK                         0x03L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK                             0xFCL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK                 0xFFL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK                            0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK                                0x02L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK                                0x04L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK                                     0xF8L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK                             0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK                                 0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK                               0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK                        0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK                             0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK                      0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK                      0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x03L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x0CL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x30L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK                       0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK  0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK  0x02L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK    0x04L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK    0x08L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK     0x10L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK                       0xE0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK    0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK    0x02L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK      0x04L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK      0x08L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK       0x10L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK                        0xE0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK          0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK          0x02L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK          0x04L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK          0x08L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK                    0x10L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK                            0xE0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK                      0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK                     0x02L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK                           0xFCL
+
+
+// addressBlock: c20_phy_cr4_rdpcspipecrind
+//C20_PHY_CR4_SUP_DIG_IDCODE_LO
+#define C20_PHY_CR4_SUP_DIG_IDCODE_LO__VAL__SHIFT                                                             0x0
+#define C20_PHY_CR4_SUP_DIG_IDCODE_LO__VAL_MASK                                                               0xFFFFL
+//C20_PHY_CR4_SUP_DIG_IDCODE_HI
+#define C20_PHY_CR4_SUP_DIG_IDCODE_HI__VAL__SHIFT                                                             0x0
+#define C20_PHY_CR4_SUP_DIG_IDCODE_HI__VAL_MASK                                                               0xFFFFL
+//C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN__SHIFT                                          0x2
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN__SHIFT                                  0x3
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD__SHIFT                                              0x4
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE__SHIFT                                            0x6
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN__SHIFT                                                    0xa
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN__SHIFT                                            0xb
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD__SHIFT                                  0xc
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN__SHIFT                               0xd
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14__SHIFT                                           0xe
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_MASK                                                 0x0001L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_MASK                                            0x0004L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN_MASK                                    0x0008L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_MASK                                                0x0010L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_MASK                                              0x01C0L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_MASK                                                      0x0400L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN_MASK                                              0x0800L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_MASK                                    0x1000L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN_MASK                                 0x2000L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14_MASK                                             0xC000L
+//C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL__SHIFT                                          0x0
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL__SHIFT                                           0x3
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN__SHIFT                                   0x5
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN__SHIFT                                            0x6
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL__SHIFT                                       0x8
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                               0x9
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10__SHIFT                                           0xa
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_MASK                                            0x0003L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_MASK                                             0x0018L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN_MASK                                     0x0020L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_MASK                                              0x0040L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_MASK                                         0x0100L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10_MASK                                             0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x0200L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x0200L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                                     0x0
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN__SHIFT                             0x2
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                               0x3
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN__SHIFT                                       0x6
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE__SHIFT                                              0x7
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9__SHIFT                                                0x9
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                                       0x0003L
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN_MASK                               0x0004L
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_MASK                                                 0x0038L
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN_MASK                                         0x0040L
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_MASK                                                0x0080L
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9_MASK                                                  0xFE00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xd
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN__SHIFT                                             0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL_MASK                                           0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV_MASK                                           0x001CL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL_MASK                                 0x0060L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                   0x0E00L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                    0x1000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK                                        0x2000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS_MASK                                        0x4000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN_MASK                                               0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN__SHIFT                                          0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL__SHIFT                                          0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD_MASK                                          0x3000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN_MASK                                            0x4000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL_MASK                                            0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_BW_LOW_OVRD_IN
+#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW_MASK                                           0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN
+#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH_MASK                                         0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN__SHIFT                                          0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x3
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0xd
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN_MASK                                            0x0004L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD_MASK                                     0x0008L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK                               0x03E0L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK                                0x0400L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK                      0x1000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK                                  0x2000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN_MASK                          0x4000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_3
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_4
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_5
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_6
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN__SHIFT                                             0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT                                            0xd
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL_MASK                                           0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV_MASK                                           0x001CL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL_MASK                                 0x0060L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                   0x0700L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN_MASK                                               0x1000L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK                                              0xE000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT__SHIFT                                          0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_MASK                                         0x007FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_MASK                                            0x7F00L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN_MASK                                    0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP__SHIFT                                         0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN__SHIFT                                 0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_MASK                                        0x007FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_MASK                                           0x7F00L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN_MASK                                   0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I__SHIFT                                             0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN__SHIFT                                     0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x3
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_MASK                                               0x0003L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN_MASK                                       0x0004L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_MASK                                          0x0018L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN__SHIFT                                          0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x3
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0xd
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN_MASK                                            0x0004L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD_MASK                                     0x0008L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK                               0x03E0L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK                                0x0400L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK                      0x1000L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK                                  0x2000L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN_MASK                          0x4000L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_3
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_5
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_6
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ__SHIFT                                                   0x0
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN__SHIFT                                               0x1
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN__SHIFT                                                  0x2
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN__SHIFT                                                  0x3
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN__SHIFT                                                 0x4
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7__SHIFT                                               0x7
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ_MASK                                                     0x0001L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN_MASK                                                 0x0002L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN_MASK                                                    0x0004L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN_MASK                                                    0x0008L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN_MASK                                                   0x0010L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7_MASK                                                 0xFF80L
+//C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET__SHIFT                                            0x0
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET__SHIFT                                              0xa
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN__SHIFT                                      0xf
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_MASK                                              0x01FFL
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_MASK                                                0x7C00L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN_MASK                                        0x8000L
+//C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_2
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET__SHIFT                                            0x0
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10__SHIFT                                              0xa
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_MASK                                              0x01FFL
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10_MASK                                                0xFC00L
+//C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT                                                  0x2
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT                                                  0x4
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x6
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x7
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x9
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD__SHIFT                                           0xa
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0xb
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD__SHIFT                                            0xc
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0xd
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14__SHIFT                                               0xe
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x0001L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK                                                    0x0004L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK                                                    0x0010L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x0040L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x0080L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x0100L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x0200L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_MASK                                             0x0400L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x0800L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_MASK                                              0x1000L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x2000L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14_MASK                                                 0xC000L
+//C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN
+#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x6
+#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN__SHIFT                                         0x9
+#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
+#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x001FL
+#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x01C0L
+#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN_MASK                                           0x0200L
+#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK                                                  0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV__SHIFT                                        0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xb
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14__SHIFT                                            0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV_MASK                                           0x000EL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV_MASK                                          0x0030L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0380L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK                                        0x0400L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS_MASK                                        0x0800L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD_MASK                                          0x3000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14_MASK                                              0xC000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_BW_LOW_ASIC_IN
+#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW_MASK                                           0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN
+#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH_MASK                                         0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x3
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD_MASK                                     0x0004L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK                               0x00F8L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK                                0x0100L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK                                  0x0200L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_3
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_4
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_5
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_6
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV__SHIFT                                        0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x6
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9__SHIFT                                             0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV_MASK                                           0x000EL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV_MASK                                          0x0030L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x01C0L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9_MASK                                               0xFE00L
+//C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT__SHIFT                                          0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS_MASK                                         0x007FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_MASK                                            0x3F80L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP__SHIFT                                         0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS_MASK                                        0x007FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_MASK                                           0x3F80L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I__SHIFT                                             0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I_MASK                                               0x0003L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO_MASK                                          0x000CL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x3
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD_MASK                                     0x0004L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK                               0x00F8L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK                                0x0100L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK                                  0x0200L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_3
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_5
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_6
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                            0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                      0xb
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14__SHIFT                                      0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                              0x0600L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                        0x3800L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14_MASK                                        0xC000L
+//C20_PHY_CR4_SUP_DIG_ASIC_IN_0
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__PHY_RESET__SHIFT                                                       0x0
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_CLK_EN__SHIFT                                                      0x1
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN__SHIFT                                                 0x2
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_USE_PAD__SHIFT                                                     0x3
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__TEST_BURNIN__SHIFT                                                     0x4
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN__SHIFT                                                  0x5
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RTUNE_REQ__SHIFT                                                       0x6
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RES_REQ_IN__SHIFT                                                      0x7
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RES_ACK_IN__SHIFT                                                      0x8
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__BG_EN__SHIFT                                                           0x9
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                              0xa
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_RANGE__SHIFT                                                       0xb
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE__SHIFT                                                 0xe
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RESERVED_15_15__SHIFT                                                  0xf
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__PHY_RESET_MASK                                                         0x0001L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_CLK_EN_MASK                                                        0x0002L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN_MASK                                                   0x0004L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_USE_PAD_MASK                                                       0x0008L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__TEST_BURNIN_MASK                                                       0x0010L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN_MASK                                                    0x0020L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RTUNE_REQ_MASK                                                         0x0040L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RES_REQ_IN_MASK                                                        0x0080L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RES_ACK_IN_MASK                                                        0x0100L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__BG_EN_MASK                                                             0x0200L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL_MASK                                                0x0400L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_RANGE_MASK                                                         0x3800L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE_MASK                                                   0x4000L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RESERVED_15_15_MASK                                                    0x8000L
+//C20_PHY_CR4_SUP_DIG_ASIC_IN_1
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__SUP_MISC__SHIFT                                                        0x0
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN__SHIFT                                                0x8
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN__SHIFT                                              0x9
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL__SHIFT                                                 0xa
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL__SHIFT                                                  0xc
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__RESERVED_15_14__SHIFT                                                  0xe
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__SUP_MISC_MASK                                                          0x00FFL
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN_MASK                                                  0x0100L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN_MASK                                                0x0200L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL_MASK                                                   0x0C00L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL_MASK                                                    0x3000L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__RESERVED_15_14_MASK                                                    0xC000L
+//C20_PHY_CR4_SUP_DIG_ASIC_OUT_0
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT__SHIFT                                              0x0
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__MPLLA_STATE__SHIFT                                                    0x1
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__MPLLB_STATE__SHIFT                                                    0x2
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RTUNE_ACK__SHIFT                                                      0x3
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT__SHIFT                                                    0x4
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT__SHIFT                                                    0x5
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__DTB_OUT__SHIFT                                                        0x6
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RESERVED_15_8__SHIFT                                                  0x8
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT_MASK                                                0x0001L
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__MPLLA_STATE_MASK                                                      0x0002L
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__MPLLB_STATE_MASK                                                      0x0004L
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RTUNE_ACK_MASK                                                        0x0008L
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT_MASK                                                      0x0010L
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT_MASK                                                      0x0020L
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__DTB_OUT_MASK                                                          0x00C0L
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RESERVED_15_8_MASK                                                    0xFF00L
+//C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN
+#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x5
+#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN__SHIFT                                                 0x8
+#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET__SHIFT                                                0x9
+#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14__SHIFT                                                0xe
+#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x001FL
+#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x00E0L
+#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN_MASK                                                   0x0100L
+#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET_MASK                                                  0x3E00L
+#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14_MASK                                                  0xC000L
+//C20_PHY_CR4_SUP_DIG_SUP_OVRD_MISC
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN__SHIFT                                            0x8
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9__SHIFT                                               0x9
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN_MASK                                              0x0100L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9_MASK                                                 0xFE00L
+//C20_PHY_CR4_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN
+#define C20_PHY_CR4_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET__SHIFT                                 0x0
+#define C20_PHY_CR4_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET_MASK                                   0x01FFL
+#define C20_PHY_CR4_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN
+#define C20_PHY_CR4_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET__SHIFT                                 0x0
+#define C20_PHY_CR4_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET_MASK                                   0x01FFL
+#define C20_PHY_CR4_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL__SHIFT                                0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL__SHIFT                                  0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL__SHIFT                             0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10__SHIFT                                          0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL_MASK                                  0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL_MASK                                    0x0004L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL_MASK                               0x01F0L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10_MASK                                            0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY__SHIFT                                           0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE__SHIFT                                      0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7__SHIFT                                           0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE_MASK                                           0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY_MASK                                             0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE_MASK                                        0x007CL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7_MASK                                             0xFF80L
+//C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__RESERVED__SHIFT                                                     0x1
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL__SHIFT                                                0x6
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7__SHIFT                                                0x7
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x0001L
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__RESERVED_MASK                                                       0x0002L
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x0004L
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x0038L
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL_MASK                                                  0x0040L
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7_MASK                                                  0xFF80L
+//C20_PHY_CR4_SUP_DIG_RTUNE_STAT
+#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__RTUNE_STATE__SHIFT                                                    0xa
+#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE__SHIFT                                                 0xd
+#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__RESERVED_15_15__SHIFT                                                 0xf
+#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x03FFL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__RTUNE_STATE_MASK                                                      0x1C00L
+#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE_MASK                                                   0x6000L
+#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__RESERVED_15_15_MASK                                                   0x8000L
+//C20_PHY_CR4_SUP_DIG_RTUNE_RX_SET_VAL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
+#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x003FL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0xFFC0L
+//C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x03FFL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x03FFL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR4_SUP_DIG_RTUNE_RX_STAT
+#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x003FL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_STAT
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x03FFL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0xFC00L
+//C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_STAT
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x03FFL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0xFC00L
+//C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG__SHIFT                                                  0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10__SHIFT                                       0xa
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG_MASK                                                    0x03FFL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10_MASK                                         0xFC00L
+//C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_1
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN__SHIFT                                                 0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10__SHIFT                                       0xa
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN_MASK                                                   0x03FFL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10_MASK                                         0xFC00L
+//C20_PHY_CR4_SUP_DIG_RTUNE_FAST_FLAGS
+#define C20_PHY_CR4_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE__SHIFT                                               0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR4_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE_MASK                                                 0x0001L
+#define C20_PHY_CR4_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER__SHIFT                                  0xa
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11__SHIFT                                    0xb
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x01FFL
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x0200L
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER_MASK                                    0x0400L
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11_MASK                                      0xF800L
+//C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x01FFL
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x00FFL
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x001FL
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x0020L
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE__SHIFT                                     0x1
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE__SHIFT                                     0x2
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE__SHIFT                                      0x4
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6__SHIFT                                     0x6
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE_MASK                                        0x0001L
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE_MASK                                       0x0002L
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE_MASK                                       0x000CL
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE_MASK                                        0x0030L
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6_MASK                                       0xFFC0L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL__SHIFT                                0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL__SHIFT                                 0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN__SHIFT                               0x6
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE__SHIFT                             0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE__SHIFT                                0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT_MASK                                      0x000FL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL_MASK                                  0x0010L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL_MASK                                   0x0020L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE_MASK                               0x7F80L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE_MASK                                  0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE__SHIFT                               0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14__SHIFT                              0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK                                      0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK                              0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK                               0x0008L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK                                0x0010L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE_MASK                                 0x3C00L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14_MASK                                0xC000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                                      0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                                       0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                                      0x6
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xd
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP__SHIFT                             0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                                        0x0010L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                                         0x0020L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                                        0x0040L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0080L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0100L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0200L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x1000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x2000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x4000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP_MASK                               0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME__SHIFT               0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME__SHIFT                 0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME_MASK                 0x03FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME_MASK                   0x3C00L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK                         0xC000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME__SHIFT           0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME__SHIFT                         0xb
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME_MASK             0x07FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME_MASK                           0xF800L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME__SHIFT                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME__SHIFT                  0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME__SHIFT               0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME_MASK                          0x001FL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME_MASK                    0x03E0L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME_MASK                 0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME__SHIFT                  0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME__SHIFT                0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME_MASK                    0x007FL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME_MASK                  0x0F80L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT                     0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL__SHIFT                       0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12__SHIFT                           0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK                       0x00FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL_MASK                         0x0F00L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12_MASK                             0xF000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT             0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP__SHIFT          0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG__SHIFT         0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK               0x00FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP_MASK            0x0300L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG_MASK           0x0C00L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0__SHIFT                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0__SHIFT                      0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0_MASK                        0x00FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0_MASK                        0xFF00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1__SHIFT                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1__SHIFT                      0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1_MASK                        0x00FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1_MASK                        0xFF00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2__SHIFT                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2__SHIFT                      0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2_MASK                        0x00FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2_MASK                        0xFF00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3__SHIFT                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3__SHIFT                      0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3_MASK                        0x00FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3_MASK                        0xFF00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME__SHIFT         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME__SHIFT                   0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME_MASK           0x03FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME_MASK                     0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME__SHIFT     0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11__SHIFT                       0xb
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME_MASK       0x07FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11_MASK                         0xF800L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME__SHIFT              0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10__SHIFT                       0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME_MASK                0x03FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10_MASK                         0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME__SHIFT             0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10__SHIFT                       0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME_MASK               0x03FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10_MASK                         0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7__SHIFT                        0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME_MASK                 0x007FL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7_MASK                          0xFF80L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN__SHIFT                 0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2__SHIFT                               0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN_MASK                   0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2_MASK                                 0xFFFCL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_FRAC_OUT
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_SSC_RAMP
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_CONFIG
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK                                          0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK                                           0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN__SHIFT                            0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE__SHIFT                                   0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL_MASK                             0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN_MASK                              0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE_MASK                                     0x007CL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK                                      0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK                              0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK                               0x0008L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK                                0x0010L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC__SHIFT                                 0xd
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC__SHIFT                                 0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0010L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0020L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0100L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x0200L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x0400L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x0800L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x1000L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC_MASK                                   0x2000L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC_MASK                                   0x4000L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME__SHIFT                          0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME_MASK                              0x00FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME_MASK                            0x3F00L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK                         0xC000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME__SHIFT                       0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME__SHIFT                          0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME_MASK                         0x00FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME_MASK                            0xFF00L
+//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME__SHIFT                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME__SHIFT                         0x6
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME_MASK                        0x003FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME_MASK                           0x0FC0L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME__SHIFT                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME__SHIFT                           0x6
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME_MASK                          0x003FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME_MASK                             0x0FC0L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS__SHIFT                0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS_MASK                  0x001FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7__SHIFT                        0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME_MASK                 0x007FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7_MASK                          0xFF80L
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_FRAC_OUT
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_SSC_RAMP
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_CONFIG
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK                                          0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK                                           0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT__SHIFT                                      0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK__SHIFT                                             0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC__SHIFT                                              0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT__SHIFT                                          0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL__SHIFT                                         0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10__SHIFT                                             0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT_MASK                                           0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT_MASK                                        0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK_MASK                                               0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC_MASK                                                0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT_MASK                                            0x01F0L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL_MASK                                           0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10_MASK                                               0xFC00L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN__SHIFT                                                 0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START__SHIFT                                    0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN__SHIFT                                            0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL__SHIFT                                      0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START__SHIFT                                   0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL__SHIFT                                         0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN__SHIFT                                                 0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST__SHIFT                                           0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE__SHIFT                                               0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST__SHIFT                                             0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN_MASK                                                   0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START_MASK                                      0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN_MASK                                              0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL_MASK                                        0x0030L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START_MASK                                     0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL_MASK                                           0x0380L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN_MASK                                                   0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST_MASK                                             0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE_MASK                                                 0x3000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST_MASK                                               0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP__SHIFT                              0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL__SHIFT                                       0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST__SHIFT                                       0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT__SHIFT                                 0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN__SHIFT                                 0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN__SHIFT                                   0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN__SHIFT                               0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN__SHIFT                               0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN__SHIFT                                0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN__SHIFT                            0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12__SHIFT                                      0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP_MASK                                0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL_MASK                                         0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST_MASK                                         0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT_MASK                                   0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN_MASK                                   0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN_MASK                                     0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN_MASK                              0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12_MASK                                        0xF000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL__SHIFT                                       0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST__SHIFT                                       0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT__SHIFT                                 0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN__SHIFT                               0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN__SHIFT                               0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN__SHIFT                               0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN__SHIFT                                0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN__SHIFT                           0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE__SHIFT                                 0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY__SHIFT                                   0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14__SHIFT                                      0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_MASK                                         0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST_MASK                                         0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT_MASK                                   0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN_MASK                             0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE_MASK                                   0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY_MASK                                     0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14_MASK                                        0xC000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN__SHIFT                                                  0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START__SHIFT                                          0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN__SHIFT                                  0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START__SHIFT                                          0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN__SHIFT                                  0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER__SHIFT                                0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP__SHIFT                                0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                          0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_MASK                                                    0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_MASK                                            0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN_MASK                                    0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_MASK                                            0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN_MASK                                    0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER_MASK                                  0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP_MASK                                  0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                            0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                      0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                              0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                   0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                           0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE__SHIFT                                  0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_MASK                                        0x000CL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_MASK                                     0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                             0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE_MASK                                       0x0180L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE_MASK                                    0x7E00L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL__SHIFT                                   0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL__SHIFT                                0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL_MASK                                      0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL_MASK                                     0x0006L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL_MASK                                  0x0018L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP__SHIFT                            0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                    0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN__SHIFT                            0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                         0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                         0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT__SHIFT                               0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                        0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_MASK                              0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                      0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN_MASK                              0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                           0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                           0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_MASK                                 0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN__SHIFT                                 0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN__SHIFT                              0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN__SHIFT                      0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN__SHIFT                            0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN__SHIFT                    0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN__SHIFT                            0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN__SHIFT                                  0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN__SHIFT                          0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN__SHIFT                              0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_MASK                                   0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN_MASK                           0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN_MASK                           0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_MASK                                0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN_MASK                        0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_MASK                              0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN_MASK                      0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_MASK                              0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN_MASK                           0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_MASK                                    0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN_MASK                            0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_MASK                                0x4000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN__SHIFT                                0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN_MASK                        0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK                                  0xFFF0L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC__SHIFT                              0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT__SHIFT                               0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC_MASK                                0x003FL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT_MASK                                 0xFFC0L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                         0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                         0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT__SHIFT                                   0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE__SHIFT                                   0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                     0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                        0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                           0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                           0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_MASK                                     0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_MASK                                     0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                       0x4000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN__SHIFT                                 0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN__SHIFT                                0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                        0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN__SHIFT                         0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN__SHIFT                             0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_MASK                                   0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN_MASK                           0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN_MASK                           0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                          0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN_MASK                           0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_MASK                               0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN__SHIFT                                0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN_MASK                        0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK                                  0xFFF0L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC__SHIFT                              0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT__SHIFT                               0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC_MASK                                0x003FL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT_MASK                                 0xFFC0L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                            0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                      0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                          0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                         0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                       0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                              0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                        0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                            0x000CL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                           0x3FF0L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                         0x4000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_OVRD_OUT
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC__SHIFT                                          0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_MASK                                            0x00FFL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE__SHIFT                            0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN__SHIFT                    0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE__SHIFT                              0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN__SHIFT                      0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_MASK                              0x00FFL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN_MASK                      0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_MASK                                0x1E00L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN_MASK                        0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG__SHIFT                                   0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1__SHIFT                                        0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT__SHIFT                                  0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START__SHIFT                             0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG__SHIFT                              0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST__SHIFT                                  0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT__SHIFT                            0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG__SHIFT                                   0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2__SHIFT                           0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7__SHIFT                                0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST__SHIFT                           0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT__SHIFT                                 0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX__SHIFT                             0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_MASK                                     0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1_MASK                                          0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT_MASK                                    0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START_MASK                               0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG_MASK                                0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST_MASK                                    0x0060L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT_MASK                              0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG_MASK                                     0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2_MASK                             0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7_MASK                                  0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST_MASK                             0x1800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT_MASK                                   0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX_MASK                               0xC000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX__SHIFT                             0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0__SHIFT                         0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6__SHIFT                                        0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0__SHIFT                              0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS__SHIFT                                   0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST_MASK                                      0x0003L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX_MASK                               0x000CL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0_MASK                           0x0030L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6_MASK                                          0x00C0L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0_MASK                                0x7F00L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS_MASK                                     0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF__SHIFT                                 0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP__SHIFT                                 0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB__SHIFT                                      0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP__SHIFT                                 0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE__SHIFT                                 0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5__SHIFT                                        0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON__SHIFT                                 0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN__SHIFT                            0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN__SHIFT                           0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF_MASK                                   0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP_MASK                                   0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB_MASK                                        0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP_MASK                                   0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE_MASK                                   0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5_MASK                                          0x0060L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON_MASK                                   0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN_MASK                              0x0F00L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN_MASK                             0xF000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE__SHIFT                          0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE__SHIFT                                    0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM__SHIFT                                0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR__SHIFT                                0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF__SHIFT                                        0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9__SHIFT                                       0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE_MASK                            0x0003L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE_MASK                                      0x000CL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM_MASK                                  0x0030L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR_MASK                                  0x00C0L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF_MASK                                          0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9_MASK                                         0x7E00L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF__SHIFT                                    0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR__SHIFT                           0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL__SHIFT                                0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0_MASK                                      0x007FL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF_MASK                                      0x0180L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR_MASK                             0x7E00L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL_MASK                                  0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS__SHIFT                          0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC__SHIFT                            0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS__SHIFT                               0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4__SHIFT                                      0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG__SHIFT                                0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL__SHIFT                             0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE__SHIFT                             0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG__SHIFT                              0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL__SHIFT                                0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG__SHIFT                                 0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG__SHIFT                           0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET__SHIFT                              0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG__SHIFT                               0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0_MASK                                        0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS_MASK                            0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC_MASK                              0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS_MASK                                 0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4_MASK                                        0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG_MASK                                  0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL_MASK                               0x00C0L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE_MASK                               0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG_MASK                                0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL_MASK                                  0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG_MASK                                   0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG_MASK                             0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET_MASK                                0x4000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG_MASK                                 0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV__SHIFT                                 0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_MASK                                   0xFFFFL
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16__SHIFT                           0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT__SHIFT                              0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22__SHIFT                           0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16_MASK                             0x003FL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT_MASK                                0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22_MASK                             0x3F80L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN__SHIFT                      0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN__SHIFT                           0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW__SHIFT                              0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW__SHIFT                                   0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN__SHIFT                       0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG__SHIFT                            0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90__SHIFT                            0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN_MASK                        0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN_MASK                             0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW_MASK                                0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW_MASK                                     0x0FF8L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN_MASK                         0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG_MASK                              0x6000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90_MASK                              0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0__SHIFT                                     0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0_MASK                                       0xFFFFL
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0__SHIFT                                     0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0_MASK                                       0xFFFFL
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0__SHIFT                                  0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0_MASK                                    0x00FFL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT__SHIFT                       0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT__SHIFT                       0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV__SHIFT                           0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN__SHIFT                                  0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK__SHIFT                          0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6__SHIFT                                      0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS__SHIFT                          0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS__SHIFT                               0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT__SHIFT                          0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG__SHIFT                           0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR__SHIFT                          0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO__SHIFT                              0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV__SHIFT                             0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90__SHIFT                            0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT_MASK                         0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT_MASK                         0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV_MASK                             0x000CL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN_MASK                                    0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK_MASK                            0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6_MASK                                        0x00C0L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS_MASK                            0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS_MASK                                 0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT_MASK                            0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG_MASK                             0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR_MASK                            0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO_MASK                                0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV_MASK                               0x4000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90_MASK                              0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE__SHIFT                             0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG__SHIFT                              0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL__SHIFT                                0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG__SHIFT                                 0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN__SHIFT                          0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG__SHIFT                           0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET__SHIFT                              0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG__SHIFT                               0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP__SHIFT                            0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13__SHIFT                                    0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT__SHIFT                              0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE_MASK                               0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG_MASK                                0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL_MASK                                  0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG_MASK                                   0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN_MASK                            0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG_MASK                             0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET_MASK                                0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG_MASK                                 0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP_MASK                              0x1F00L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13_MASK                                      0x6000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT_MASK                                0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER__SHIFT                 0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ__SHIFT                       0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE__SHIFT                  0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED__SHIFT                       0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV__SHIFT                         0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H__SHIFT                         0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP__SHIFT                        0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP__SHIFT                    0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP__SHIFT                      0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP__SHIFT                       0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE__SHIFT                          0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER_MASK                   0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ_MASK                         0x0006L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE_MASK                    0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED_MASK                         0x00F0L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV_MASK                           0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H_MASK                           0x0600L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP_MASK                          0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP_MASK                      0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP_MASK                        0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP_MASK                         0x4000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE_MASK                            0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN__SHIFT                 0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN__SHIFT                         0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK__SHIFT                            0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5__SHIFT                                      0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8__SHIFT                                     0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START__SHIFT                     0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE__SHIFT                        0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST__SHIFT                             0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN_MASK                   0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN_MASK                           0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_MASK                              0x001CL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5_MASK                                        0x00E0L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8_MASK                                       0x0F00L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START_MASK                       0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE_MASK                          0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST_MASK                               0xC000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT__SHIFT                             0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW__SHIFT                         0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF__SHIFT                    0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS__SHIFT                               0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH__SHIFT                       0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN__SHIFT                           0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP__SHIFT                             0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO__SHIFT                            0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR__SHIFT                        0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING__SHIFT                           0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR__SHIFT                          0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF__SHIFT                    0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK__SHIFT                    0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG__SHIFT                        0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT_MASK                               0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW_MASK                           0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF_MASK                      0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS_MASK                                 0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH_MASK                         0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN_MASK                             0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP_MASK                               0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO_MASK                              0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR_MASK                          0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING_MASK                             0x0600L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR_MASK                            0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF_MASK                      0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK_MASK                      0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG_MASK                          0xC000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT__SHIFT                       0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING__SHIFT                        0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR__SHIFT                        0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2__SHIFT                    0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP__SHIFT                      0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED__SHIFT                       0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2__SHIFT                     0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X__SHIFT                               0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD__SHIFT                                 0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N__SHIFT                             0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC__SHIFT                           0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER__SHIFT                            0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT_MASK                         0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING_MASK                          0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR_MASK                          0x000CL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2_MASK                      0x0030L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP_MASK                        0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_MASK                         0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2_MASK                       0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X_MASK                                 0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD_MASK                                   0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N_MASK                               0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC_MASK                             0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER_MASK                              0xE000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF__SHIFT                          0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF__SHIFT                         0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL__SHIFT                          0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0__SHIFT                        0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH__SHIFT                         0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2__SHIFT                          0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES__SHIFT                             0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF_MASK                            0x0007L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF_MASK                           0x0038L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL_MASK                            0x00C0L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0_MASK                          0x0300L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH_MASK                           0x0C00L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2_MASK                            0x3000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES_MASK                               0xC000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG__SHIFT                            0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC__SHIFT                             0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL__SHIFT                         0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP__SHIFT                        0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK__SHIFT                          0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN__SHIFT                    0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST__SHIFT                              0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0_MASK                                        0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG_MASK                              0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC_MASK                               0x000CL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL_MASK                           0x0030L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP_MASK                          0x00C0L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK_MASK                            0x0F00L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN_MASK                      0x3000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST_MASK                                0xC000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                 0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                   0xFFFFL
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                 0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                   0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_CMN_CTL
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_CMN_CLK_GATE_CTL
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN__SHIFT                                                 0x2
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x5
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN__SHIFT                                                 0x6
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE__SHIFT                                              0x8
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x9
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ__SHIFT                                                    0xa
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0xb
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE__SHIFT                                           0xc
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_MASK                                                   0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_MASK                                                   0x0040L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_MASK                                                0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0200L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_MASK                                                      0x0400L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x0800L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE_MASK                                             0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0xE000L
+//C20_PHY_CR4_RAWCMN_DIG_MPLL_CONFIG
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME__SHIFT                                         0x6
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10__SHIFT                                             0xa
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME_MASK                                                0x003FL
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME_MASK                                           0x03C0L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10_MASK                                               0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_CTRL
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4__SHIFT                                             0x4
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE_MASK                                              0x000FL
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4_MASK                                               0xFFF0L
+//C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_ADDR
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_ADDR__ADDR__SHIFT                                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_ADDR__ADDR_MASK                                                        0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_DATA
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_DATA__DATA__SHIFT                                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_DATA__DATA_MASK                                                        0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_FLAGS
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_ACCUM
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_ACCUM__VAL__SHIFT                                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_ACCUM__VAL_MASK                                                        0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLL_IN
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN__SHIFT                                                   0x3
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__RESERVED_15_4__SHIFT                                                  0x4
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE_MASK                                           0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN_MASK                                                     0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__RESERVED_15_4_MASK                                                    0xFFF0L
+//C20_PHY_CR4_RAWCMN_DIG_FW_PWRUP_DONE
+#define C20_PHY_CR4_RAWCMN_DIG_FW_PWRUP_DONE__DONE__SHIFT                                                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR4_RAWCMN_DIG_FW_PWRUP_DONE__DONE_MASK                                                       0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_STATIC_CONFIG_STATUS
+#define C20_PHY_CR4_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE_MASK                                            0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_FW_CONFIG_STATUS
+#define C20_PHY_CR4_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE__SHIFT                                          0x1
+#define C20_PHY_CR4_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE_MASK                                            0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE_MASK                                            0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_CMN_STATUS_1
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2__SHIFT                                             0x2
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE_MASK                                               0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2_MASK                                               0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x2
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0x3
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0x4
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0x5
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x7
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x9
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0xa
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0xc
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL_MASK                       0x0003L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN_MASK                        0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK                       0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN_MASK                        0x0010L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK                        0x0020L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL_MASK                       0x0180L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN_MASK                        0x0200L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK                       0x0400L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK                        0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_FRAC_UPDATE
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE__SHIFT                               0x1
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN_MASK                               0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE_MASK                                 0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_FRAC_UPDATE
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE__SHIFT                               0x1
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN_MASK                               0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE_MASK                                 0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_CONFIG_MASTER_VERSION
+#define C20_PHY_CR4_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION_MASK                                     0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_0
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_1
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_2
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_3
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR4_RAWCMN_DIG_CREG_ACCESS_CTL
+#define C20_PHY_CR4_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN__SHIFT                              0x8
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN_MASK                                0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN__SHIFT                              0x8
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN_MASK                                0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_0
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11__SHIFT                                          0xb
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC_MASK                                                  0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL_MASK                                             0x0700L
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11_MASK                                            0xF800L
+//C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_1
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET__SHIFT                                        0x5
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14__SHIFT                                          0xe
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL_MASK                                              0x001FL
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET_MASK                                          0x3FE0L
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14_MASK                                            0xC000L
+//C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_2
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET__SHIFT                                        0x5
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14__SHIFT                                          0xe
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET_MASK                                            0x001FL
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET_MASK                                          0x3FE0L
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14_MASK                                            0xC000L
+//C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_3
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID__SHIFT                                               0x0
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10__SHIFT                                          0xa
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID_MASK                                                 0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10_MASK                                            0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN__SHIFT                                         0xf
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER_MASK                                              0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN_MASK                                              0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN_MASK                                           0x8000L
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV__SHIFT                                            0x8
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0xb
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD__SHIFT                                          0xe
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV_MASK                                              0x0700L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV_MASK                                            0x1800L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD_MASK                                            0xC000L
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_2
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_3
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH__SHIFT                                               0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH_MASK                                                 0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_4
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB_MASK                                            0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_5
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK                                       0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV__SHIFT                                     0xa
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL__SHIFT                                            0xd
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xe
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB_MASK                                            0x000FL
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK                                       0x01F0L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD_MASK                                           0x0200L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV_MASK                                       0x1C00L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL_MASK                                              0x2000L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN_MASK                                                 0x4000L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_7
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN_MASK                                                0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_8
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT_MASK                                               0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_9
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM_MASK                                                0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV__SHIFT                                            0xd
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER_MASK                                              0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN_MASK                                              0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV_MASK                                              0xE000L
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE__SHIFT                                          0xa
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV_MASK                                            0x0300L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE_MASK                                            0x7C00L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_2
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP__SHIFT                                               0x7
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO__SHIFT                                              0xe
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT_MASK                                                  0x007FL
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP_MASK                                                 0x3F80L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO_MASK                                                0xC000L
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_3
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS__SHIFT                                            0x7
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I__SHIFT                                                   0xe
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS_MASK                                               0x007FL
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS_MASK                                              0x3F80L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I_MASK                                                     0xC000L
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_4
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB_MASK                                            0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_5
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK                                       0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV__SHIFT                                     0xa
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xd
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB_MASK                                            0x000FL
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK                                       0x01F0L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD_MASK                                           0x0200L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV_MASK                                       0x1C00L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN_MASK                                                 0x2000L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_7
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN_MASK                                                0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_8
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT_MASK                                               0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_9
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM_MASK                                                0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_10
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV_MASK                                               0x0007L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV_MASK                                     0x0018L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN__SHIFT                                        0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN_MASK                                          0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3_MASK                                       0xFFF8L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0__SHIFT                           0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0_MASK                                  0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0_MASK                             0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1__SHIFT                           0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1_MASK                                  0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1_MASK                             0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2__SHIFT                           0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2_MASK                                  0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2_MASK                             0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3__SHIFT                           0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3_MASK                                  0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3_MASK                             0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL__SHIFT                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL_MASK                                0x0003L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_DONE
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0__SHIFT                           0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0_MASK                                  0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0_MASK                             0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1__SHIFT                           0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1_MASK                                  0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1_MASK                             0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2__SHIFT                           0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2_MASK                                  0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2_MASK                             0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3__SHIFT                           0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3_MASK                                  0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3_MASK                             0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL__SHIFT                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL_MASK                                0x0003L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_DONE
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12__SHIFT                                          0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE_MASK                                                0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12_MASK                                            0xF000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12__SHIFT                                          0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE_MASK                                                0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12_MASK                                            0xF000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_IN_RECAL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_IN_RECAL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                       0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6__SHIFT                                           0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                         0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                       0x0010L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6_MASK                                             0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO__SHIFT                                       0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                              0x4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                               0x5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                          0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO_MASK                                         0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                                0x0010L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                            0x8
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12__SHIFT                                         0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                      0x0010L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                              0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12_MASK                                           0xF000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN__SHIFT                                            0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN__SHIFT                                                0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                        0x4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK__SHIFT                                                0x5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN_MASK                                              0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN_MASK                                                  0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL_MASK                                          0x0010L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK_MASK                                                  0x0020L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6_MASK                                               0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                               0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                              0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                               0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL__SHIFT                                  0x4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN__SHIFT                                   0x5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL__SHIFT                                   0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL_MASK                                0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL_MASK                                0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN_MASK                                 0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL_MASK                                    0x0010L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN_MASK                                     0x0020L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL_MASK                                     0x0040L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK__SHIFT                                          0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4__SHIFT                                            0x4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK_MASK                                            0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK_MASK                                            0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4_MASK                                              0xFFF0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL_MASK                    0x0003L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL_MASK                    0x0003L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                                0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT__SHIFT                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE__SHIFT                              0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT_MASK                                0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE_MASK                                0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                        0x003FL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                    0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0_MASK                                  0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                        0x003FL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                    0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1_MASK                                  0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                        0x003FL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                    0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2_MASK                                  0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                        0x003FL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                    0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3_MASK                                  0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                        0x003FL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                    0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4_MASK                                  0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                        0x003FL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                    0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5_MASK                                  0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                        0x003FL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                    0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6_MASK                                  0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_7
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                        0x003FL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                    0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7_MASK                                  0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL__SHIFT                             0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL__SHIFT                             0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN__SHIFT                              0x4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL__SHIFT                         0x5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL_MASK                               0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL_MASK                               0x000CL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN_MASK                                0x0010L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL_MASK                           0x0060L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS_MASK                                         0x0018L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5_MASK                                                0xFFE0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OUT
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_AON_FW_VERSION_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_FW_VERSION_0__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_FW_VERSION_0__VAL_MASK                                                     0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_AON_FW_VERSION_1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_FW_VERSION_1__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_FW_VERSION_1__VAL_MASK                                                     0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_AON_RAW_VERSION
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RAW_VERSION__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RAW_VERSION__VAL_MASK                                                      0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_EOF_ADDR
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_BOC_ADDR
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL__SHIFT                                     0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN__SHIFT                                      0x7
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10__SHIFT                                           0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL_MASK                                    0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL_MASK                                       0x0010L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL_MASK                                       0x0040L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN_MASK                                        0x0080L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10_MASK                                             0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL_MASK                                            0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN__SHIFT                                            0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN__SHIFT                                            0x4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE__SHIFT                                        0x5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE__SHIFT                                        0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL__SHIFT                                            0x9
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT__SHIFT                                         0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT__SHIFT                                         0xb
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF__SHIFT                                         0xd
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW__SHIFT                                          0xe
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN_MASK                                              0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN_MASK                                              0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN_MASK                                              0x0010L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE_MASK                                          0x0020L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE_MASK                                          0x0040L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ_MASK                                           0x0080L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ_MASK                                           0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL_MASK                                              0x0200L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT_MASK                                           0x0400L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT_MASK                                           0x0800L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL_MASK                                          0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF_MASK                                           0x2000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW_MASK                                            0x4000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL__SHIFT                            0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL_MASK                              0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_METADATA_LOCATION
+#define C20_PHY_CR4_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION_MASK                                  0x7FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST__SHIFT                         0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN__SHIFT                 0xf
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_MASK                           0x7FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN_MASK                   0x8000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR4_LANE0_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_LANE0_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR4_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR4_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR4_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR4_LANE0_DIG_TX_FIFO_CTL
+#define C20_PHY_CR4_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR4_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR4_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR4_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR4_LANE0_DIG_RX_LBERT_ERR
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_CDR_STAT
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR4_LANE1_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_LANE1_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR4_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR4_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR4_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR4_LANE1_DIG_TX_FIFO_CTL
+#define C20_PHY_CR4_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR4_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR4_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR4_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR4_LANE1_DIG_RX_LBERT_ERR
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_CDR_STAT
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR4_LANE2_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_LANE2_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR4_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR4_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR4_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR4_LANE2_DIG_TX_FIFO_CTL
+#define C20_PHY_CR4_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR4_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR4_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR4_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR4_LANE2_DIG_RX_LBERT_ERR
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_CDR_STAT
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR4_LANE3_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_LANE3_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR4_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR4_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR4_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR4_LANE3_DIG_TX_FIFO_CTL
+#define C20_PHY_CR4_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR4_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR4_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR4_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR4_LANE3_DIG_RX_LBERT_ERR
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_CDR_STAT
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_CR_LOCK
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_SUP
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_CR_LOCK
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_SUP
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_CR_LOCK
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_SUP
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_CR_LOCK
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_SUP
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_IN_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_OUT_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_IN_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_OUT_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_IN_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_OUT_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_IN_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_OUT_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR4_LANEX_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_LANEX_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR4_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR4_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR4_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR4_LANEX_DIG_TX_FIFO_CTL
+#define C20_PHY_CR4_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR4_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR4_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR4_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR4_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR4_LANEX_DIG_RX_LBERT_ERR
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_CDR_STAT
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_CR_LOCK
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_SUP
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_IN_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_OUT_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+
+
+// addressBlock: c20_phy_lane0_pipe4_rdpcspipemsgbusind
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK           0x02L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK                  0x04L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK                 0x08L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK             0x10L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK                           0xE0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK                      0x7FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK                   0x80L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK   0xFFL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK                               0x02L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK                            0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK                                  0x02L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK                                 0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK                         0x02L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK                           0x04L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK                                  0xF8L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK              0x02L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK                             0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                         0x40L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK                                  0x80L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK                            0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                    0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK                                  0x40L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK             0x80L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK                                 0x07L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK                                  0x08L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK                                  0xF0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                     0x40L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK                              0x80L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK                        0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK                       0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK                              0x40L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK         0x80L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK                             0x07L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK                              0x08L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK                              0xF0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK                  0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK                              0xFEL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK             0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK   0x1EL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK             0x20L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK                      0x40L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK                     0x80L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK                           0x03L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK                            0xFCL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK                         0x03L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK                             0xFCL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK                 0xFFL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK                            0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK                                0x02L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK                                0x04L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK                                     0xF8L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK                             0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK                                 0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK                               0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK                        0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK                             0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK                      0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK                      0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x03L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x0CL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x30L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK                       0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK  0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK  0x02L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK    0x04L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK    0x08L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK     0x10L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK                       0xE0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK    0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK    0x02L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK      0x04L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK      0x08L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK       0x10L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK                        0xE0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK          0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK          0x02L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK          0x04L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK          0x08L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK                    0x10L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK                            0xE0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK                      0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK                     0x02L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK                           0xFCL
+
+
+// addressBlock: c20_phy_lane1_pipe4_rdpcspipemsgbusind
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK           0x02L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK                  0x04L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK                 0x08L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK             0x10L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK                           0xE0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK                      0x7FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK                   0x80L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK   0xFFL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK                               0x02L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK                            0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK                                  0x02L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK                                 0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK                         0x02L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK                           0x04L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK                                  0xF8L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK              0x02L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK                             0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                         0x40L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK                                  0x80L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK                            0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                    0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK                                  0x40L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK             0x80L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK                                 0x07L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK                                  0x08L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK                                  0xF0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                     0x40L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK                              0x80L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK                        0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK                       0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK                              0x40L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK         0x80L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK                             0x07L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK                              0x08L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK                              0xF0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK                  0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK                              0xFEL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK             0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK   0x1EL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK             0x20L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK                      0x40L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK                     0x80L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK                           0x03L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK                            0xFCL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK                         0x03L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK                             0xFCL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK                 0xFFL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK                            0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK                                0x02L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK                                0x04L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK                                     0xF8L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK                             0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK                                 0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK                               0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK                        0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK                             0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK                      0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK                      0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x03L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x0CL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x30L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK                       0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK  0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK  0x02L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK    0x04L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK    0x08L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK     0x10L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK                       0xE0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK    0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK    0x02L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK      0x04L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK      0x08L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK       0x10L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK                        0xE0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK          0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK          0x02L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK          0x04L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK          0x08L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK                    0x10L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK                            0xE0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK                      0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK                     0x02L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK                           0xFCL
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h
new file mode 100644
index 0000000000000..e40a924c02cef
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h
@@ -0,0 +1,14559 @@
+/*
+ * Copyright (C) 2022  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dcn_3_2_1_OFFSET_HEADER
+#define _dcn_3_2_1_OFFSET_HEADER
+
+
+
+// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
+// base address: 0x0
+#define regDENTIST_DISPCLK_CNTL                                                                         0x0064
+#define regDENTIST_DISPCLK_CNTL_BASE_IDX                                                                1
+
+
+// addressBlock: dce_dc_dccg_dccg_dispdec
+// base address: 0x0
+#define regPHYPLLA_PIXCLK_RESYNC_CNTL                                                                   0x0040
+#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regPHYPLLB_PIXCLK_RESYNC_CNTL                                                                   0x0041
+#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regPHYPLLC_PIXCLK_RESYNC_CNTL                                                                   0x0042
+#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regPHYPLLD_PIXCLK_RESYNC_CNTL                                                                   0x0043
+#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regDP_DTO_DBUF_EN                                                                               0x0044
+#define regDP_DTO_DBUF_EN_BASE_IDX                                                                      1
+#define regDSCCLK3_DTO_PARAM                                                                            0x0045
+#define regDSCCLK3_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPREFCLK_CGTT_BLK_CTRL_REG                                                                   0x0048
+#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                          1
+#define regDCCG_GATE_DISABLE_CNTL4                                                                      0x0049
+#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX                                                             1
+#define regDPSTREAMCLK_CNTL                                                                             0x004a
+#define regDPSTREAMCLK_CNTL_BASE_IDX                                                                    1
+#define regREFCLK_CGTT_BLK_CTRL_REG                                                                     0x004b
+#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regPHYPLLE_PIXCLK_RESYNC_CNTL                                                                   0x004c
+#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regDCCG_GLOBAL_FGCG_REP_CNTL                                                                    0x0050
+#define regDCCG_GLOBAL_FGCG_REP_CNTL_BASE_IDX                                                           1
+#define regDCCG_DS_DTO_INCR                                                                             0x0053
+#define regDCCG_DS_DTO_INCR_BASE_IDX                                                                    1
+#define regDCCG_DS_DTO_MODULO                                                                           0x0054
+#define regDCCG_DS_DTO_MODULO_BASE_IDX                                                                  1
+#define regDCCG_DS_CNTL                                                                                 0x0055
+#define regDCCG_DS_CNTL_BASE_IDX                                                                        1
+#define regDCCG_DS_HW_CAL_INTERVAL                                                                      0x0056
+#define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX                                                             1
+#define regDPREFCLK_CNTL                                                                                0x0058
+#define regDPREFCLK_CNTL_BASE_IDX                                                                       1
+#define regDCE_VERSION                                                                                  0x005e
+#define regDCE_VERSION_BASE_IDX                                                                         1
+#define regDCCG_GTC_CNTL                                                                                0x0060
+#define regDCCG_GTC_CNTL_BASE_IDX                                                                       1
+#define regDCCG_GTC_DTO_INCR                                                                            0x0061
+#define regDCCG_GTC_DTO_INCR_BASE_IDX                                                                   1
+#define regDCCG_GTC_DTO_MODULO                                                                          0x0062
+#define regDCCG_GTC_DTO_MODULO_BASE_IDX                                                                 1
+#define regDCCG_GTC_CURRENT                                                                             0x0063
+#define regDCCG_GTC_CURRENT_BASE_IDX                                                                    1
+#define regSYMCLK32_SE_CNTL                                                                             0x0065
+#define regSYMCLK32_SE_CNTL_BASE_IDX                                                                    1
+#define regSYMCLK32_LE_CNTL                                                                             0x0066
+#define regSYMCLK32_LE_CNTL_BASE_IDX                                                                    1
+#define regDTBCLK_P_CNTL                                                                                0x0068
+#define regDTBCLK_P_CNTL_BASE_IDX                                                                       1
+#define regDCCG_GATE_DISABLE_CNTL5                                                                      0x0069
+#define regDCCG_GATE_DISABLE_CNTL5_BASE_IDX                                                             1
+#define regDSCCLK0_DTO_PARAM                                                                            0x006c
+#define regDSCCLK0_DTO_PARAM_BASE_IDX                                                                   1
+#define regDSCCLK1_DTO_PARAM                                                                            0x006d
+#define regDSCCLK1_DTO_PARAM_BASE_IDX                                                                   1
+#define regDSCCLK2_DTO_PARAM                                                                            0x006e
+#define regDSCCLK2_DTO_PARAM_BASE_IDX                                                                   1
+#define regOTG_PIXEL_RATE_DIV                                                                           0x006f
+#define regOTG_PIXEL_RATE_DIV_BASE_IDX                                                                  1
+#define regMILLISECOND_TIME_BASE_DIV                                                                    0x0070
+#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX                                                           1
+#define regDISPCLK_FREQ_CHANGE_CNTL                                                                     0x0071
+#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX                                                            1
+#define regDC_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0072
+#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1
+#define regDCCG_GATE_DISABLE_CNTL                                                                       0x0074
+#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX                                                              1
+#define regDISPCLK_CGTT_BLK_CTRL_REG                                                                    0x0075
+#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                           1
+#define regSOCCLK_CGTT_BLK_CTRL_REG                                                                     0x0076
+#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regDCCG_CAC_STATUS                                                                              0x0077
+#define regDCCG_CAC_STATUS_BASE_IDX                                                                     1
+#define regMICROSECOND_TIME_BASE_DIV                                                                    0x007b
+#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX                                                           1
+#define regDCCG_GATE_DISABLE_CNTL2                                                                      0x007c
+#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX                                                             1
+#define regSYMCLK_CGTT_BLK_CTRL_REG                                                                     0x007d
+#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regDCCG_DISP_CNTL_REG                                                                           0x007f
+#define regDCCG_DISP_CNTL_REG_BASE_IDX                                                                  1
+#define regOTG0_PIXEL_RATE_CNTL                                                                         0x0080
+#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO0_PHASE                                                                                0x0081
+#define regDP_DTO0_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO0_MODULO                                                                               0x0082
+#define regDP_DTO0_MODULO_BASE_IDX                                                                      1
+#define regOTG0_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0083
+#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regOTG1_PIXEL_RATE_CNTL                                                                         0x0084
+#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO1_PHASE                                                                                0x0085
+#define regDP_DTO1_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO1_MODULO                                                                               0x0086
+#define regDP_DTO1_MODULO_BASE_IDX                                                                      1
+#define regOTG1_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0087
+#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regOTG2_PIXEL_RATE_CNTL                                                                         0x0088
+#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO2_PHASE                                                                                0x0089
+#define regDP_DTO2_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO2_MODULO                                                                               0x008a
+#define regDP_DTO2_MODULO_BASE_IDX                                                                      1
+#define regOTG2_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008b
+#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regOTG3_PIXEL_RATE_CNTL                                                                         0x008c
+#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO3_PHASE                                                                                0x008d
+#define regDP_DTO3_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO3_MODULO                                                                               0x008e
+#define regDP_DTO3_MODULO_BASE_IDX                                                                      1
+#define regOTG3_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008f
+#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regDPPCLK_CGTT_BLK_CTRL_REG                                                                     0x0098
+#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regDPPCLK0_DTO_PARAM                                                                            0x0099
+#define regDPPCLK0_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPPCLK1_DTO_PARAM                                                                            0x009a
+#define regDPPCLK1_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPPCLK2_DTO_PARAM                                                                            0x009b
+#define regDPPCLK2_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPPCLK3_DTO_PARAM                                                                            0x009c
+#define regDPPCLK3_DTO_PARAM_BASE_IDX                                                                   1
+#define regDCCG_CAC_STATUS2                                                                             0x009f
+#define regDCCG_CAC_STATUS2_BASE_IDX                                                                    1
+#define regSYMCLKA_CLOCK_ENABLE                                                                         0x00a0
+#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKB_CLOCK_ENABLE                                                                         0x00a1
+#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKC_CLOCK_ENABLE                                                                         0x00a2
+#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKD_CLOCK_ENABLE                                                                         0x00a3
+#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKE_CLOCK_ENABLE                                                                         0x00a4
+#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regDCCG_SOFT_RESET                                                                              0x00a6
+#define regDCCG_SOFT_RESET_BASE_IDX                                                                     1
+#define regDSCCLK_DTO_CTRL                                                                              0x00a7
+#define regDSCCLK_DTO_CTRL_BASE_IDX                                                                     1
+#define regDCCG_AUDIO_DTO_SOURCE                                                                        0x00ab
+#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX                                                               1
+#define regDCCG_AUDIO_DTO0_PHASE                                                                        0x00ac
+#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX                                                               1
+#define regDCCG_AUDIO_DTO0_MODULE                                                                       0x00ad
+#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX                                                              1
+#define regDCCG_AUDIO_DTO1_PHASE                                                                        0x00ae
+#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX                                                               1
+#define regDCCG_AUDIO_DTO1_MODULE                                                                       0x00af
+#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX                                                              1
+#define regDCCG_VSYNC_OTG0_LATCH_VALUE                                                                  0x00b0
+#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG1_LATCH_VALUE                                                                  0x00b1
+#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG2_LATCH_VALUE                                                                  0x00b2
+#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG3_LATCH_VALUE                                                                  0x00b3
+#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG4_LATCH_VALUE                                                                  0x00b4
+#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG5_LATCH_VALUE                                                                  0x00b5
+#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX                                                         1
+#define regDPPCLK_DTO_CTRL                                                                              0x00b6
+#define regDPPCLK_DTO_CTRL_BASE_IDX                                                                     1
+#define regDCCG_VSYNC_CNT_CTRL                                                                          0x00b8
+#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX                                                                 1
+#define regDCCG_VSYNC_CNT_INT_CTRL                                                                      0x00b9
+#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX                                                             1
+#define regFORCE_SYMCLK_DISABLE                                                                         0x00ba
+#define regFORCE_SYMCLK_DISABLE_BASE_IDX                                                                1
+#define regDCCG_TEST_CLK_SEL                                                                            0x00be
+#define regDCCG_TEST_CLK_SEL_BASE_IDX                                                                   1
+#define regDTBCLK_DTO0_PHASE                                                                            0x0018
+#define regDTBCLK_DTO0_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO1_PHASE                                                                            0x0019
+#define regDTBCLK_DTO1_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO2_PHASE                                                                            0x001a
+#define regDTBCLK_DTO2_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO3_PHASE                                                                            0x001b
+#define regDTBCLK_DTO3_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO0_MODULO                                                                           0x001f
+#define regDTBCLK_DTO0_MODULO_BASE_IDX                                                                  2
+#define regDTBCLK_DTO1_MODULO                                                                           0x0020
+#define regDTBCLK_DTO1_MODULO_BASE_IDX                                                                  2
+#define regDTBCLK_DTO2_MODULO                                                                           0x0021
+#define regDTBCLK_DTO2_MODULO_BASE_IDX                                                                  2
+#define regDTBCLK_DTO3_MODULO                                                                           0x0022
+#define regDTBCLK_DTO3_MODULO_BASE_IDX                                                                  2
+#define regHDMICHARCLK0_CLOCK_CNTL                                                                      0x004a
+#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX                                                             2
+#define regPHYASYMCLK_CLOCK_CNTL                                                                        0x0052
+#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYBSYMCLK_CLOCK_CNTL                                                                        0x0053
+#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYCSYMCLK_CLOCK_CNTL                                                                        0x0054
+#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYDSYMCLK_CLOCK_CNTL                                                                        0x0055
+#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYESYMCLK_CLOCK_CNTL                                                                        0x0056
+#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regHDMISTREAMCLK_CNTL                                                                           0x0059
+#define regHDMISTREAMCLK_CNTL_BASE_IDX                                                                  2
+#define regDCCG_GATE_DISABLE_CNTL3                                                                      0x005a
+#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX                                                             2
+#define regHDMISTREAMCLK0_DTO_PARAM                                                                     0x005b
+#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX                                                            2
+#define regDCCG_AUDIO_DTBCLK_DTO_PHASE                                                                  0x0061
+#define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX                                                         2
+#define regDCCG_AUDIO_DTBCLK_DTO_MODULO                                                                 0x0062
+#define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX                                                        2
+#define regDTBCLK_DTO_DBUF_EN                                                                           0x0063
+#define regDTBCLK_DTO_DBUF_EN_BASE_IDX                                                                  2
+#define regDMCUBCLK_CNTL                                                                                0x0067
+#define regDMCUBCLK_CNTL_BASE_IDX                                                                       2
+
+
+// addressBlock: dce_dc_dmu_rbbmif_dispdec
+// base address: 0x0
+#define regRBBMIF_TIMEOUT                                                                               0x017f
+#define regRBBMIF_TIMEOUT_BASE_IDX                                                                      2
+#define regRBBMIF_STATUS                                                                                0x0180
+#define regRBBMIF_STATUS_BASE_IDX                                                                       2
+#define regRBBMIF_STATUS_2                                                                              0x0181
+#define regRBBMIF_STATUS_2_BASE_IDX                                                                     2
+#define regRBBMIF_INT_STATUS                                                                            0x0182
+#define regRBBMIF_INT_STATUS_BASE_IDX                                                                   2
+#define regRBBMIF_TIMEOUT_DIS                                                                           0x0183
+#define regRBBMIF_TIMEOUT_DIS_BASE_IDX                                                                  2
+#define regRBBMIF_TIMEOUT_DIS_2                                                                         0x0184
+#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX                                                                2
+#define regRBBMIF_STATUS_FLAG                                                                           0x0185
+#define regRBBMIF_STATUS_FLAG_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dmu_ihc_dispdec
+// base address: 0x0
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE                                                         0x0126
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX                                                2
+#define regDC_GPU_TIMER_START_POSITION_VSTARTUP                                                         0x0127
+#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX                                                2
+#define regDC_GPU_TIMER_READ                                                                            0x0128
+#define regDC_GPU_TIMER_READ_BASE_IDX                                                                   2
+#define regDC_GPU_TIMER_READ_CNTL                                                                       0x0129
+#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2
+#define regDISP_INTERRUPT_STATUS                                                                        0x012a
+#define regDISP_INTERRUPT_STATUS_BASE_IDX                                                               2
+#define regDISP_INTERRUPT_STATUS_CONTINUE                                                               0x012b
+#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
+#define regDISP_INTERRUPT_STATUS_CONTINUE2                                                              0x012c
+#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE3                                                              0x012d
+#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE4                                                              0x012e
+#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE5                                                              0x012f
+#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE6                                                              0x0130
+#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE7                                                              0x0131
+#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE8                                                              0x0132
+#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE9                                                              0x0133
+#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE10                                                             0x0134
+#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE11                                                             0x0135
+#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE12                                                             0x0136
+#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE13                                                             0x0137
+#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE14                                                             0x0138
+#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE15                                                             0x0139
+#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE16                                                             0x013a
+#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE17                                                             0x013b
+#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE18                                                             0x013c
+#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE19                                                             0x013d
+#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE20                                                             0x013e
+#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE21                                                             0x013f
+#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE22                                                             0x0140
+#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX                                                    2
+#define regDC_GPU_TIMER_START_POSITION_VREADY                                                           0x0141
+#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX                                                  2
+#define regDC_GPU_TIMER_START_POSITION_FLIP                                                             0x0142
+#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX                                                    2
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK                                                 0x0143
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX                                        2
+#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY                                                        0x0144
+#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX                                               2
+#define regDISP_INTERRUPT_STATUS_CONTINUE23                                                             0x0145
+#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE24                                                             0x0146
+#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE25                                                             0x0147
+#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX                                                    2
+#define regDCCG_INTERRUPT_DEST                                                                          0x0148
+#define regDCCG_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regDMU_INTERRUPT_DEST                                                                           0x0149
+#define regDMU_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regDMU_INTERRUPT_DEST2                                                                          0x014a
+#define regDMU_INTERRUPT_DEST2_BASE_IDX                                                                 2
+#define regDCPG_INTERRUPT_DEST                                                                          0x014b
+#define regDCPG_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regDCPG_INTERRUPT_DEST2                                                                         0x014c
+#define regDCPG_INTERRUPT_DEST2_BASE_IDX                                                                2
+#define regMMHUBBUB_INTERRUPT_DEST                                                                      0x014d
+#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX                                                             2
+#define regWB_INTERRUPT_DEST                                                                            0x014e
+#define regWB_INTERRUPT_DEST_BASE_IDX                                                                   2
+#define regDCHUB_INTERRUPT_DEST                                                                         0x014f
+#define regDCHUB_INTERRUPT_DEST_BASE_IDX                                                                2
+#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST                                                             0x0150
+#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                    2
+#define regDCHUB_INTERRUPT_DEST2                                                                        0x0151
+#define regDCHUB_INTERRUPT_DEST2_BASE_IDX                                                               2
+#define regDPP_PERFCOUNTER_INTERRUPT_DEST                                                               0x0152
+#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                      2
+#define regMPC_INTERRUPT_DEST                                                                           0x0153
+#define regMPC_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regOPP_INTERRUPT_DEST                                                                           0x0154
+#define regOPP_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regOPTC_INTERRUPT_DEST                                                                          0x0155
+#define regOPTC_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG0_INTERRUPT_DEST                                                                          0x0156
+#define regOTG0_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG1_INTERRUPT_DEST                                                                          0x0157
+#define regOTG1_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG2_INTERRUPT_DEST                                                                          0x0158
+#define regOTG2_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG3_INTERRUPT_DEST                                                                          0x0159
+#define regOTG3_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG4_INTERRUPT_DEST                                                                          0x015a
+#define regOTG4_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG5_INTERRUPT_DEST                                                                          0x015b
+#define regOTG5_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regDIG_INTERRUPT_DEST                                                                           0x015c
+#define regDIG_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regI2C_DDC_HPD_INTERRUPT_DEST                                                                   0x015d
+#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX                                                          2
+#define regDIO_INTERRUPT_DEST                                                                           0x015f
+#define regDIO_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regDCIO_INTERRUPT_DEST                                                                          0x0160
+#define regDCIO_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regHPD_INTERRUPT_DEST                                                                           0x0161
+#define regHPD_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regAZ_INTERRUPT_DEST                                                                            0x0162
+#define regAZ_INTERRUPT_DEST_BASE_IDX                                                                   2
+#define regAUX_INTERRUPT_DEST                                                                           0x0163
+#define regAUX_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regDSC_INTERRUPT_DEST                                                                           0x0164
+#define regDSC_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regHPO_INTERRUPT_DEST                                                                           0x0165
+#define regHPO_INTERRUPT_DEST_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dmu_dmu_misc_dispdec
+// base address: 0x0
+#define regCC_DC_PIPE_DIS                                                                               0x00ca
+#define regCC_DC_PIPE_DIS_BASE_IDX                                                                      2
+#define regDMU_CLK_CNTL                                                                                 0x00cb
+#define regDMU_CLK_CNTL_BASE_IDX                                                                        2
+#define regDMCUB_SMU_INTERRUPT_CNTL                                                                     0x00cd
+#define regDMCUB_SMU_INTERRUPT_CNTL_BASE_IDX                                                            2
+#define regSMU_INTERRUPT_CONTROL                                                                        0x00ce
+#define regSMU_INTERRUPT_CONTROL_BASE_IDX                                                               2
+#define regDMU_MISC_ALLOW_DS_FORCE                                                                      0x00d6
+#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dmu_dc_pg_dispdec
+// base address: 0x0
+#define regDOMAIN0_PG_CONFIG                                                                            0x0080
+#define regDOMAIN0_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN0_PG_STATUS                                                                            0x0081
+#define regDOMAIN0_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN1_PG_CONFIG                                                                            0x0082
+#define regDOMAIN1_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN1_PG_STATUS                                                                            0x0083
+#define regDOMAIN1_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN2_PG_CONFIG                                                                            0x0084
+#define regDOMAIN2_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN2_PG_STATUS                                                                            0x0085
+#define regDOMAIN2_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN3_PG_CONFIG                                                                            0x0086
+#define regDOMAIN3_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN3_PG_STATUS                                                                            0x0087
+#define regDOMAIN3_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN16_PG_CONFIG                                                                           0x0089
+#define regDOMAIN16_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN16_PG_STATUS                                                                           0x008a
+#define regDOMAIN16_PG_STATUS_BASE_IDX                                                                  2
+#define regDOMAIN17_PG_CONFIG                                                                           0x008b
+#define regDOMAIN17_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN17_PG_STATUS                                                                           0x008c
+#define regDOMAIN17_PG_STATUS_BASE_IDX                                                                  2
+#define regDOMAIN18_PG_CONFIG                                                                           0x008d
+#define regDOMAIN18_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN18_PG_STATUS                                                                           0x008e
+#define regDOMAIN18_PG_STATUS_BASE_IDX                                                                  2
+#define regDOMAIN19_PG_CONFIG                                                                           0x008f
+#define regDOMAIN19_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN19_PG_STATUS                                                                           0x0090
+#define regDOMAIN19_PG_STATUS_BASE_IDX                                                                  2
+#define regDCPG_INTERRUPT_STATUS                                                                        0x0091
+#define regDCPG_INTERRUPT_STATUS_BASE_IDX                                                               2
+#define regDCPG_INTERRUPT_STATUS_2                                                                      0x0092
+#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX                                                             2
+#define regDCPG_INTERRUPT_CONTROL_1                                                                     0x0093
+#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX                                                            2
+#define regDCPG_INTERRUPT_CONTROL_3                                                                     0x0094
+#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX                                                            2
+#define regDC_IP_REQUEST_CNTL                                                                           0x0095
+#define regDC_IP_REQUEST_CNTL_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dmu_dmcub_dispdec
+// base address: 0x0
+#define regDMCUB_REGION0_OFFSET                                                                         0x018e
+#define regDMCUB_REGION0_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION0_OFFSET_HIGH                                                                    0x018f
+#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION1_OFFSET                                                                         0x0190
+#define regDMCUB_REGION1_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION1_OFFSET_HIGH                                                                    0x0191
+#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION2_OFFSET                                                                         0x0192
+#define regDMCUB_REGION2_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION2_OFFSET_HIGH                                                                    0x0193
+#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION4_OFFSET                                                                         0x0196
+#define regDMCUB_REGION4_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION4_OFFSET_HIGH                                                                    0x0197
+#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION5_OFFSET                                                                         0x0198
+#define regDMCUB_REGION5_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION5_OFFSET_HIGH                                                                    0x0199
+#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION6_OFFSET                                                                         0x019a
+#define regDMCUB_REGION6_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION6_OFFSET_HIGH                                                                    0x019b
+#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION7_OFFSET                                                                         0x019c
+#define regDMCUB_REGION7_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION7_OFFSET_HIGH                                                                    0x019d
+#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION0_TOP_ADDRESS                                                                    0x019e
+#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION1_TOP_ADDRESS                                                                    0x019f
+#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION2_TOP_ADDRESS                                                                    0x01a0
+#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION4_TOP_ADDRESS                                                                    0x01a1
+#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION5_TOP_ADDRESS                                                                    0x01a2
+#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION6_TOP_ADDRESS                                                                    0x01a3
+#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION7_TOP_ADDRESS                                                                    0x01a4
+#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION3_CW0_BASE_ADDRESS                                                               0x01a5
+#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW1_BASE_ADDRESS                                                               0x01a6
+#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW2_BASE_ADDRESS                                                               0x01a7
+#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW3_BASE_ADDRESS                                                               0x01a8
+#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW4_BASE_ADDRESS                                                               0x01a9
+#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW5_BASE_ADDRESS                                                               0x01aa
+#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW6_BASE_ADDRESS                                                               0x01ab
+#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW7_BASE_ADDRESS                                                               0x01ac
+#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW0_TOP_ADDRESS                                                                0x01ad
+#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW1_TOP_ADDRESS                                                                0x01ae
+#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW2_TOP_ADDRESS                                                                0x01af
+#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW3_TOP_ADDRESS                                                                0x01b0
+#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW4_TOP_ADDRESS                                                                0x01b1
+#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW5_TOP_ADDRESS                                                                0x01b2
+#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW6_TOP_ADDRESS                                                                0x01b3
+#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW7_TOP_ADDRESS                                                                0x01b4
+#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW0_OFFSET                                                                     0x01b5
+#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW0_OFFSET_HIGH                                                                0x01b6
+#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW1_OFFSET                                                                     0x01b7
+#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW1_OFFSET_HIGH                                                                0x01b8
+#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW2_OFFSET                                                                     0x01b9
+#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW2_OFFSET_HIGH                                                                0x01ba
+#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW3_OFFSET                                                                     0x01bb
+#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW3_OFFSET_HIGH                                                                0x01bc
+#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW4_OFFSET                                                                     0x01bd
+#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW4_OFFSET_HIGH                                                                0x01be
+#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW5_OFFSET                                                                     0x01bf
+#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW5_OFFSET_HIGH                                                                0x01c0
+#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW6_OFFSET                                                                     0x01c1
+#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW6_OFFSET_HIGH                                                                0x01c2
+#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW7_OFFSET                                                                     0x01c3
+#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW7_OFFSET_HIGH                                                                0x01c4
+#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_INTERRUPT_ENABLE                                                                       0x01c5
+#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX                                                              2
+#define regDMCUB_INTERRUPT_ACK                                                                          0x01c6
+#define regDMCUB_INTERRUPT_ACK_BASE_IDX                                                                 2
+#define regDMCUB_INTERRUPT_STATUS                                                                       0x01c7
+#define regDMCUB_INTERRUPT_STATUS_BASE_IDX                                                              2
+#define regDMCUB_INTERRUPT_TYPE                                                                         0x01c8
+#define regDMCUB_INTERRUPT_TYPE_BASE_IDX                                                                2
+#define regDMCUB_EXT_INTERRUPT_STATUS                                                                   0x01c9
+#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX                                                          2
+#define regDMCUB_EXT_INTERRUPT_CTXID                                                                    0x01ca
+#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX                                                           2
+#define regDMCUB_EXT_INTERRUPT_ACK                                                                      0x01cb
+#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX                                                             2
+#define regDMCUB_INST_FETCH_FAULT_ADDR                                                                  0x01cc
+#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX                                                         2
+#define regDMCUB_DATA_WRITE_FAULT_ADDR                                                                  0x01cd
+#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX                                                         2
+#define regDMCUB_SEC_CNTL                                                                               0x01ce
+#define regDMCUB_SEC_CNTL_BASE_IDX                                                                      2
+#define regDMCUB_MEM_CNTL                                                                               0x01cf
+#define regDMCUB_MEM_CNTL_BASE_IDX                                                                      2
+#define regDMCUB_INBOX0_BASE_ADDRESS                                                                    0x01d0
+#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_INBOX0_SIZE                                                                            0x01d1
+#define regDMCUB_INBOX0_SIZE_BASE_IDX                                                                   2
+#define regDMCUB_INBOX0_WPTR                                                                            0x01d2
+#define regDMCUB_INBOX0_WPTR_BASE_IDX                                                                   2
+#define regDMCUB_INBOX0_RPTR                                                                            0x01d3
+#define regDMCUB_INBOX0_RPTR_BASE_IDX                                                                   2
+#define regDMCUB_INBOX1_BASE_ADDRESS                                                                    0x01d4
+#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_INBOX1_SIZE                                                                            0x01d5
+#define regDMCUB_INBOX1_SIZE_BASE_IDX                                                                   2
+#define regDMCUB_INBOX1_WPTR                                                                            0x01d6
+#define regDMCUB_INBOX1_WPTR_BASE_IDX                                                                   2
+#define regDMCUB_INBOX1_RPTR                                                                            0x01d7
+#define regDMCUB_INBOX1_RPTR_BASE_IDX                                                                   2
+#define regDMCUB_OUTBOX0_BASE_ADDRESS                                                                   0x01d8
+#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX                                                          2
+#define regDMCUB_OUTBOX0_SIZE                                                                           0x01d9
+#define regDMCUB_OUTBOX0_SIZE_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX0_WPTR                                                                           0x01da
+#define regDMCUB_OUTBOX0_WPTR_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX0_RPTR                                                                           0x01db
+#define regDMCUB_OUTBOX0_RPTR_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX1_BASE_ADDRESS                                                                   0x01dc
+#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX                                                          2
+#define regDMCUB_OUTBOX1_SIZE                                                                           0x01dd
+#define regDMCUB_OUTBOX1_SIZE_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX1_WPTR                                                                           0x01de
+#define regDMCUB_OUTBOX1_WPTR_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX1_RPTR                                                                           0x01df
+#define regDMCUB_OUTBOX1_RPTR_BASE_IDX                                                                  2
+#define regDMCUB_TIMER_TRIGGER0                                                                         0x01e0
+#define regDMCUB_TIMER_TRIGGER0_BASE_IDX                                                                2
+#define regDMCUB_TIMER_TRIGGER1                                                                         0x01e1
+#define regDMCUB_TIMER_TRIGGER1_BASE_IDX                                                                2
+#define regDMCUB_TIMER_WINDOW                                                                           0x01e2
+#define regDMCUB_TIMER_WINDOW_BASE_IDX                                                                  2
+#define regDMCUB_SCRATCH0                                                                               0x01e3
+#define regDMCUB_SCRATCH0_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH1                                                                               0x01e4
+#define regDMCUB_SCRATCH1_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH2                                                                               0x01e5
+#define regDMCUB_SCRATCH2_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH3                                                                               0x01e6
+#define regDMCUB_SCRATCH3_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH4                                                                               0x01e7
+#define regDMCUB_SCRATCH4_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH5                                                                               0x01e8
+#define regDMCUB_SCRATCH5_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH6                                                                               0x01e9
+#define regDMCUB_SCRATCH6_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH7                                                                               0x01ea
+#define regDMCUB_SCRATCH7_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH8                                                                               0x01eb
+#define regDMCUB_SCRATCH8_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH9                                                                               0x01ec
+#define regDMCUB_SCRATCH9_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH10                                                                              0x01ed
+#define regDMCUB_SCRATCH10_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH11                                                                              0x01ee
+#define regDMCUB_SCRATCH11_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH12                                                                              0x01ef
+#define regDMCUB_SCRATCH12_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH13                                                                              0x01f0
+#define regDMCUB_SCRATCH13_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH14                                                                              0x01f1
+#define regDMCUB_SCRATCH14_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH15                                                                              0x01f2
+#define regDMCUB_SCRATCH15_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH16                                                                              0x01f3
+#define regDMCUB_SCRATCH16_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH17                                                                              0x01f4
+#define regDMCUB_SCRATCH17_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH18                                                                              0x01f5
+#define regDMCUB_SCRATCH18_BASE_IDX                                                                     2
+#define regDMCUB_CNTL                                                                                   0x01f6
+#define regDMCUB_CNTL_BASE_IDX                                                                          2
+#define regDMCUB_GPINT_DATAIN0                                                                          0x01f7
+#define regDMCUB_GPINT_DATAIN0_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN1                                                                          0x01f8
+#define regDMCUB_GPINT_DATAIN1_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAOUT                                                                          0x01f9
+#define regDMCUB_GPINT_DATAOUT_BASE_IDX                                                                 2
+#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR                                                           0x01fa
+#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX                                                  2
+#define regDMCUB_LS_WAKE_INT_ENABLE                                                                     0x01fb
+#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX                                                            2
+#define regDMCUB_MEM_PWR_CNTL                                                                           0x01fc
+#define regDMCUB_MEM_PWR_CNTL_BASE_IDX                                                                  2
+#define regDMCUB_TIMER_CURRENT                                                                          0x01fd
+#define regDMCUB_TIMER_CURRENT_BASE_IDX                                                                 2
+#define regDMCUB_PROC_ID                                                                                0x01ff
+#define regDMCUB_PROC_ID_BASE_IDX                                                                       2
+#define regDMCUB_CNTL2                                                                                  0x0200
+#define regDMCUB_CNTL2_BASE_IDX                                                                         2
+#define regDMCUB_GPINT_DATAIN2                                                                          0x0215
+#define regDMCUB_GPINT_DATAIN2_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN3                                                                          0x0216
+#define regDMCUB_GPINT_DATAIN3_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN4                                                                          0x0217
+#define regDMCUB_GPINT_DATAIN4_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN5                                                                          0x0218
+#define regDMCUB_GPINT_DATAIN5_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN6                                                                          0x0219
+#define regDMCUB_GPINT_DATAIN6_BASE_IDX                                                                 2
+#define regDMCUB_REGION3_TMR_AXI_SPACE                                                                  0x021a
+#define regDMCUB_REGION3_TMR_AXI_SPACE_BASE_IDX                                                         2
+#define regDMCUB_SCRATCH19                                                                              0x022e
+#define regDMCUB_SCRATCH19_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH20                                                                              0x022f
+#define regDMCUB_SCRATCH20_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH21                                                                              0x0230
+#define regDMCUB_SCRATCH21_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH22                                                                              0x0231
+#define regDMCUB_SCRATCH22_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH23                                                                              0x0232
+#define regDMCUB_SCRATCH23_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec
+// base address: 0x0
+#define regDWB_ENABLE_CLK_CTRL                                                                          0x3228
+#define regDWB_ENABLE_CLK_CTRL_BASE_IDX                                                                 2
+#define regDWB_MEM_PWR_CTRL                                                                             0x3229
+#define regDWB_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define regFC_MODE_CTRL                                                                                 0x322a
+#define regFC_MODE_CTRL_BASE_IDX                                                                        2
+#define regFC_FLOW_CTRL                                                                                 0x322b
+#define regFC_FLOW_CTRL_BASE_IDX                                                                        2
+#define regFC_WINDOW_START                                                                              0x322c
+#define regFC_WINDOW_START_BASE_IDX                                                                     2
+#define regFC_WINDOW_SIZE                                                                               0x322d
+#define regFC_WINDOW_SIZE_BASE_IDX                                                                      2
+#define regFC_SOURCE_SIZE                                                                               0x322e
+#define regFC_SOURCE_SIZE_BASE_IDX                                                                      2
+#define regDWB_UPDATE_CTRL                                                                              0x322f
+#define regDWB_UPDATE_CTRL_BASE_IDX                                                                     2
+#define regDWB_CRC_CTRL                                                                                 0x3230
+#define regDWB_CRC_CTRL_BASE_IDX                                                                        2
+#define regDWB_CRC_MASK_R_G                                                                             0x3231
+#define regDWB_CRC_MASK_R_G_BASE_IDX                                                                    2
+#define regDWB_CRC_MASK_B_A                                                                             0x3232
+#define regDWB_CRC_MASK_B_A_BASE_IDX                                                                    2
+#define regDWB_CRC_VAL_R_G                                                                              0x3233
+#define regDWB_CRC_VAL_R_G_BASE_IDX                                                                     2
+#define regDWB_CRC_VAL_B_A                                                                              0x3234
+#define regDWB_CRC_VAL_B_A_BASE_IDX                                                                     2
+#define regDWB_OUT_CTRL                                                                                 0x3235
+#define regDWB_OUT_CTRL_BASE_IDX                                                                        2
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN                                                             0x3236
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX                                                    2
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT                                                                0x3237
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX                                                       2
+#define regDWB_HOST_READ_CONTROL                                                                        0x3238
+#define regDWB_HOST_READ_CONTROL_BASE_IDX                                                               2
+#define regDWB_OVERFLOW_STATUS                                                                          0x3239
+#define regDWB_OVERFLOW_STATUS_BASE_IDX                                                                 2
+#define regDWB_OVERFLOW_COUNTER                                                                         0x323a
+#define regDWB_OVERFLOW_COUNTER_BASE_IDX                                                                2
+#define regDWB_SOFT_RESET                                                                               0x323b
+#define regDWB_SOFT_RESET_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec
+// base address: 0x0
+#define regDWB_HDR_MULT_COEF                                                                            0x3294
+#define regDWB_HDR_MULT_COEF_BASE_IDX                                                                   2
+#define regDWB_GAMUT_REMAP_MODE                                                                         0x3295
+#define regDWB_GAMUT_REMAP_MODE_BASE_IDX                                                                2
+#define regDWB_GAMUT_REMAP_COEF_FORMAT                                                                  0x3296
+#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                                         2
+#define regDWB_GAMUT_REMAPA_C11_C12                                                                     0x3297
+#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C13_C14                                                                     0x3298
+#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C21_C22                                                                     0x3299
+#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C23_C24                                                                     0x329a
+#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C31_C32                                                                     0x329b
+#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C33_C34                                                                     0x329c
+#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C11_C12                                                                     0x329d
+#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C13_C14                                                                     0x329e
+#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C21_C22                                                                     0x329f
+#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C23_C24                                                                     0x32a0
+#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C31_C32                                                                     0x32a1
+#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C33_C34                                                                     0x32a2
+#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX                                                            2
+#define regDWB_OGAM_CONTROL                                                                             0x32a3
+#define regDWB_OGAM_CONTROL_BASE_IDX                                                                    2
+#define regDWB_OGAM_LUT_INDEX                                                                           0x32a4
+#define regDWB_OGAM_LUT_INDEX_BASE_IDX                                                                  2
+#define regDWB_OGAM_LUT_DATA                                                                            0x32a5
+#define regDWB_OGAM_LUT_DATA_BASE_IDX                                                                   2
+#define regDWB_OGAM_LUT_CONTROL                                                                         0x32a6
+#define regDWB_OGAM_LUT_CONTROL_BASE_IDX                                                                2
+#define regDWB_OGAM_RAMA_START_CNTL_B                                                                   0x32a7
+#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_START_CNTL_G                                                                   0x32a8
+#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_START_CNTL_R                                                                   0x32a9
+#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_B                                                              0x32aa
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B                                                             0x32ab
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_G                                                              0x32ac
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G                                                             0x32ad
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_R                                                              0x32ae
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R                                                             0x32af
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMA_END_CNTL1_B                                                                    0x32b0
+#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL2_B                                                                    0x32b1
+#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL1_G                                                                    0x32b2
+#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL2_G                                                                    0x32b3
+#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL1_R                                                                    0x32b4
+#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL2_R                                                                    0x32b5
+#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_OFFSET_B                                                                       0x32b6
+#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMA_OFFSET_G                                                                       0x32b7
+#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMA_OFFSET_R                                                                       0x32b8
+#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMA_REGION_0_1                                                                     0x32b9
+#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_2_3                                                                     0x32ba
+#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_4_5                                                                     0x32bb
+#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_6_7                                                                     0x32bc
+#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_8_9                                                                     0x32bd
+#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_10_11                                                                   0x32be
+#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_12_13                                                                   0x32bf
+#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_14_15                                                                   0x32c0
+#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_16_17                                                                   0x32c1
+#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_18_19                                                                   0x32c2
+#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_20_21                                                                   0x32c3
+#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_22_23                                                                   0x32c4
+#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_24_25                                                                   0x32c5
+#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_26_27                                                                   0x32c6
+#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_28_29                                                                   0x32c7
+#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_30_31                                                                   0x32c8
+#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_32_33                                                                   0x32c9
+#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_CNTL_B                                                                   0x32ca
+#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_CNTL_G                                                                   0x32cb
+#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_CNTL_R                                                                   0x32cc
+#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_B                                                              0x32cd
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B                                                             0x32ce
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_G                                                              0x32cf
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G                                                             0x32d0
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_R                                                              0x32d1
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R                                                             0x32d2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMB_END_CNTL1_B                                                                    0x32d3
+#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL2_B                                                                    0x32d4
+#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL1_G                                                                    0x32d5
+#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL2_G                                                                    0x32d6
+#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL1_R                                                                    0x32d7
+#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL2_R                                                                    0x32d8
+#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_OFFSET_B                                                                       0x32d9
+#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMB_OFFSET_G                                                                       0x32da
+#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMB_OFFSET_R                                                                       0x32db
+#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMB_REGION_0_1                                                                     0x32dc
+#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_2_3                                                                     0x32dd
+#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_4_5                                                                     0x32de
+#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_6_7                                                                     0x32df
+#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_8_9                                                                     0x32e0
+#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_10_11                                                                   0x32e1
+#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_12_13                                                                   0x32e2
+#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_14_15                                                                   0x32e3
+#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_16_17                                                                   0x32e4
+#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_18_19                                                                   0x32e5
+#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_20_21                                                                   0x32e6
+#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_22_23                                                                   0x32e7
+#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_24_25                                                                   0x32e8
+#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_26_27                                                                   0x32e9
+#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_28_29                                                                   0x32ea
+#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_30_31                                                                   0x32eb
+#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_32_33                                                                   0x32ec
+#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec
+// base address: 0x0
+#define regVGA_MEM_WRITE_PAGE_ADDR                                                                      0x0000
+#define regVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX                                                             0
+#define regVGA_MEM_READ_PAGE_ADDR                                                                       0x0001
+#define regVGA_MEM_READ_PAGE_ADDR_BASE_IDX                                                              0
+#define regVGA_RENDER_CONTROL                                                                           0x0000
+#define regVGA_RENDER_CONTROL_BASE_IDX                                                                  1
+#define regVGA_SEQUENCER_RESET_CONTROL                                                                  0x0001
+#define regVGA_SEQUENCER_RESET_CONTROL_BASE_IDX                                                         1
+#define regVGA_MODE_CONTROL                                                                             0x0002
+#define regVGA_MODE_CONTROL_BASE_IDX                                                                    1
+#define regVGA_SURFACE_PITCH_SELECT                                                                     0x0003
+#define regVGA_SURFACE_PITCH_SELECT_BASE_IDX                                                            1
+#define regVGA_MEMORY_BASE_ADDRESS                                                                      0x0004
+#define regVGA_MEMORY_BASE_ADDRESS_BASE_IDX                                                             1
+#define regVGA_DISPBUF1_SURFACE_ADDR                                                                    0x0006
+#define regVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX                                                           1
+#define regVGA_DISPBUF2_SURFACE_ADDR                                                                    0x0008
+#define regVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX                                                           1
+#define regVGA_MEMORY_BASE_ADDRESS_HIGH                                                                 0x0009
+#define regVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX                                                        1
+#define regVGA_HDP_CONTROL                                                                              0x000a
+#define regVGA_HDP_CONTROL_BASE_IDX                                                                     1
+#define regVGA_CACHE_CONTROL                                                                            0x000b
+#define regVGA_CACHE_CONTROL_BASE_IDX                                                                   1
+#define regD1VGA_CONTROL                                                                                0x000c
+#define regD1VGA_CONTROL_BASE_IDX                                                                       1
+#define regD2VGA_CONTROL                                                                                0x000e
+#define regD2VGA_CONTROL_BASE_IDX                                                                       1
+#define regVGA_STATUS                                                                                   0x0010
+#define regVGA_STATUS_BASE_IDX                                                                          1
+#define regVGA_INTERRUPT_CONTROL                                                                        0x0011
+#define regVGA_INTERRUPT_CONTROL_BASE_IDX                                                               1
+#define regVGA_STATUS_CLEAR                                                                             0x0012
+#define regVGA_STATUS_CLEAR_BASE_IDX                                                                    1
+#define regVGA_INTERRUPT_STATUS                                                                         0x0013
+#define regVGA_INTERRUPT_STATUS_BASE_IDX                                                                1
+#define regVGA_MAIN_CONTROL                                                                             0x0014
+#define regVGA_MAIN_CONTROL_BASE_IDX                                                                    1
+#define regVGA_TEST_CONTROL                                                                             0x0015
+#define regVGA_TEST_CONTROL_BASE_IDX                                                                    1
+#define regVGA_QOS_CTRL                                                                                 0x0018
+#define regVGA_QOS_CTRL_BASE_IDX                                                                        1
+#define regCRTC8_IDX                                                                                    0x002d
+#define regCRTC8_IDX_BASE_IDX                                                                           1
+#define regCRTC8_DATA                                                                                   0x002d
+#define regCRTC8_DATA_BASE_IDX                                                                          1
+#define regGENFC_WT                                                                                     0x002e
+#define regGENFC_WT_BASE_IDX                                                                            1
+#define regGENS1                                                                                        0x002e
+#define regGENS1_BASE_IDX                                                                               1
+#define regATTRDW                                                                                       0x0030
+#define regATTRDW_BASE_IDX                                                                              1
+#define regATTRX                                                                                        0x0030
+#define regATTRX_BASE_IDX                                                                               1
+#define regATTRDR                                                                                       0x0030
+#define regATTRDR_BASE_IDX                                                                              1
+#define regGENMO_WT                                                                                     0x0030
+#define regGENMO_WT_BASE_IDX                                                                            1
+#define regGENS0                                                                                        0x0030
+#define regGENS0_BASE_IDX                                                                               1
+#define regGENENB                                                                                       0x0030
+#define regGENENB_BASE_IDX                                                                              1
+#define regSEQ8_IDX                                                                                     0x0031
+#define regSEQ8_IDX_BASE_IDX                                                                            1
+#define regSEQ8_DATA                                                                                    0x0031
+#define regSEQ8_DATA_BASE_IDX                                                                           1
+#define regDAC_MASK                                                                                     0x0031
+#define regDAC_MASK_BASE_IDX                                                                            1
+#define regDAC_R_INDEX                                                                                  0x0031
+#define regDAC_R_INDEX_BASE_IDX                                                                         1
+#define regDAC_W_INDEX                                                                                  0x0032
+#define regDAC_W_INDEX_BASE_IDX                                                                         1
+#define regDAC_DATA                                                                                     0x0032
+#define regDAC_DATA_BASE_IDX                                                                            1
+#define regGENFC_RD                                                                                     0x0032
+#define regGENFC_RD_BASE_IDX                                                                            1
+#define regGENMO_RD                                                                                     0x0033
+#define regGENMO_RD_BASE_IDX                                                                            1
+#define regGRPH8_IDX                                                                                    0x0033
+#define regGRPH8_IDX_BASE_IDX                                                                           1
+#define regGRPH8_DATA                                                                                   0x0033
+#define regGRPH8_DATA_BASE_IDX                                                                          1
+#define regCRTC8_IDX_1                                                                                  0x0035
+#define regCRTC8_IDX_1_BASE_IDX                                                                         1
+#define regCRTC8_DATA_1                                                                                 0x0035
+#define regCRTC8_DATA_1_BASE_IDX                                                                        1
+#define regGENFC_WT_1                                                                                   0x0036
+#define regGENFC_WT_1_BASE_IDX                                                                          1
+#define regGENS1_1                                                                                      0x0036
+#define regGENS1_1_BASE_IDX                                                                             1
+#define regD3VGA_CONTROL                                                                                0x0038
+#define regD3VGA_CONTROL_BASE_IDX                                                                       1
+#define regD4VGA_CONTROL                                                                                0x0039
+#define regD4VGA_CONTROL_BASE_IDX                                                                       1
+#define regD5VGA_CONTROL                                                                                0x003a
+#define regD5VGA_CONTROL_BASE_IDX                                                                       1
+#define regD6VGA_CONTROL                                                                                0x003b
+#define regD6VGA_CONTROL_BASE_IDX                                                                       1
+#define regVGA_SOURCE_SELECT                                                                            0x003c
+#define regVGA_SOURCE_SELECT_BASE_IDX                                                                   1
+
+
+// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
+// base address: 0x0
+#define regMCIF_CONTROL                                                                                 0x034a
+#define regMCIF_CONTROL_BASE_IDX                                                                        2
+#define regMCIF_WRITE_COMBINE_CONTROL                                                                   0x034b
+#define regMCIF_WRITE_COMBINE_CONTROL_BASE_IDX                                                          2
+#define regMCIF_PHASE0_OUTSTANDING_COUNTER                                                              0x034e
+#define regMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+#define regMCIF_PHASE1_OUTSTANDING_COUNTER                                                              0x034f
+#define regMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+#define regMCIF_PHASE2_OUTSTANDING_COUNTER                                                              0x0350
+#define regMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
+// base address: 0x0
+#define regMCIF_WB_BUFMGR_SW_CONTROL                                                                    0x0272
+#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                           2
+#define regMCIF_WB_BUFMGR_STATUS                                                                        0x0274
+#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_PITCH                                                                            0x0275
+#define regMCIF_WB_BUF_PITCH_BASE_IDX                                                                   2
+#define regMCIF_WB_BUF_1_STATUS                                                                         0x0276
+#define regMCIF_WB_BUF_1_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_1_STATUS2                                                                        0x0277
+#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_2_STATUS                                                                         0x0278
+#define regMCIF_WB_BUF_2_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_2_STATUS2                                                                        0x0279
+#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_3_STATUS                                                                         0x027a
+#define regMCIF_WB_BUF_3_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_3_STATUS2                                                                        0x027b
+#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_4_STATUS                                                                         0x027c
+#define regMCIF_WB_BUF_4_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_4_STATUS2                                                                        0x027d
+#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_ARBITRATION_CONTROL                                                                  0x027e
+#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                         2
+#define regMCIF_WB_SCLK_CHANGE                                                                          0x027f
+#define regMCIF_WB_SCLK_CHANGE_BASE_IDX                                                                 2
+#define regMCIF_WB_TEST_DEBUG_INDEX                                                                     0x0280
+#define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX                                                            2
+#define regMCIF_WB_TEST_DEBUG_DATA                                                                      0x0281
+#define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX                                                             2
+#define regMCIF_WB_BUF_1_ADDR_Y                                                                         0x0282
+#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_1_ADDR_C                                                                         0x0284
+#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_2_ADDR_Y                                                                         0x0286
+#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_2_ADDR_C                                                                         0x0288
+#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_3_ADDR_Y                                                                         0x028a
+#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_3_ADDR_C                                                                         0x028c
+#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_4_ADDR_Y                                                                         0x028e
+#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_4_ADDR_C                                                                         0x0290
+#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUFMGR_VCE_CONTROL                                                                   0x0292
+#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                          2
+#define regMCIF_WB_NB_PSTATE_CONTROL                                                                    0x0293
+#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                           2
+#define regMCIF_WB_CLOCK_GATER_CONTROL                                                                  0x0294
+#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                         2
+#define regMCIF_WB_SELF_REFRESH_CONTROL                                                                 0x0296
+#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                                        2
+#define regMULTI_LEVEL_QOS_CTRL                                                                         0x0297
+#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX                                                                2
+#define regMCIF_WB_SECURITY_LEVEL                                                                       0x0298
+#define regMCIF_WB_SECURITY_LEVEL_BASE_IDX                                                              2
+#define regMCIF_WB_BUF_LUMA_SIZE                                                                        0x0299
+#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_CHROMA_SIZE                                                                      0x029a
+#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                             2
+#define regMCIF_WB_BUF_1_ADDR_Y_HIGH                                                                    0x029b
+#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_1_ADDR_C_HIGH                                                                    0x029c
+#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_2_ADDR_Y_HIGH                                                                    0x029d
+#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_2_ADDR_C_HIGH                                                                    0x029e
+#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_3_ADDR_Y_HIGH                                                                    0x029f
+#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_3_ADDR_C_HIGH                                                                    0x02a0
+#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_4_ADDR_Y_HIGH                                                                    0x02a1
+#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_4_ADDR_C_HIGH                                                                    0x02a2
+#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_1_RESOLUTION                                                                     0x02a3
+#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_BUF_2_RESOLUTION                                                                     0x02a4
+#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_BUF_3_RESOLUTION                                                                     0x02a5
+#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_BUF_4_RESOLUTION                                                                     0x02a6
+#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI                                                           0x02a7
+#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI_BASE_IDX                                                  2
+#define regMCIF_WB_VMID_CONTROL                                                                         0x02a8
+#define regMCIF_WB_VMID_CONTROL_BASE_IDX                                                                2
+#define regMCIF_WB_MIN_TTO                                                                              0x02a9
+#define regMCIF_WB_MIN_TTO_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
+// base address: 0x0
+#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                          0x02aa
+#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                                 2
+#define regMCIF_WB_WATERMARK                                                                            0x02ab
+#define regMCIF_WB_WATERMARK_BASE_IDX                                                                   2
+#define regMMHUBBUB_WARMUP_CONFIG                                                                       0x02ac
+#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX                                                              2
+#define regMMHUBBUB_WARMUP_CONTROL_STATUS                                                               0x02ad
+#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX                                                      2
+#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW                                                                0x02ae
+#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX                                                       2
+#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH                                                               0x02af
+#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX                                                      2
+#define regMMHUBBUB_WARMUP_ADDR_REGION                                                                  0x02b0
+#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX                                                         2
+#define regMMHUBBUB_MIN_TTO                                                                             0x02b1
+#define regMMHUBBUB_MIN_TTO_BASE_IDX                                                                    2
+#define regMMHUBBUB_CTRL                                                                                0x0333
+#define regMMHUBBUB_CTRL_BASE_IDX                                                                       2
+#define regWBIF_SMU_WM_CONTROL                                                                          0x0334
+#define regWBIF_SMU_WM_CONTROL_BASE_IDX                                                                 2
+#define regWBIF0_MISC_CTRL                                                                              0x0335
+#define regWBIF0_MISC_CTRL_BASE_IDX                                                                     2
+#define regWBIF0_PHASE0_OUTSTANDING_COUNTER                                                             0x0336
+#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                    2
+#define regWBIF0_PHASE1_OUTSTANDING_COUNTER                                                             0x0337
+#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                    2
+#define regVGA_SRC_SPLIT_CNTL                                                                           0x033e
+#define regVGA_SRC_SPLIT_CNTL_BASE_IDX                                                                  2
+#define regMMHUBBUB_MEM_PWR_STATUS                                                                      0x033f
+#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
+#define regMMHUBBUB_MEM_PWR_CNTL                                                                        0x0340
+#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX                                                               2
+#define regMMHUBBUB_CLOCK_CNTL                                                                          0x0341
+#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
+#define regMMHUBBUB_SOFT_RESET                                                                          0x0342
+#define regMMHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
+#define regDMU_IF_ERR_STATUS                                                                            0x0346
+#define regDMU_IF_ERR_STATUS_BASE_IDX                                                                   2
+#define regMMHUBBUB_CLIENT_UNIT_ID                                                                      0x0347
+#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX                                                             2
+#define regMMHUBBUB_WARMUP_VMID_CONTROL                                                                 0x0349
+#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_hda_azf0controller_dispdec
+// base address: 0x0
+#define regAZALIA_CONTROLLER_CLOCK_GATING                                                               0x03c2
+#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX                                                      2
+#define regAZALIA_AUDIO_DTO                                                                             0x03c3
+#define regAZALIA_AUDIO_DTO_BASE_IDX                                                                    2
+#define regAZALIA_AUDIO_DTO_CONTROL                                                                     0x03c4
+#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX                                                            2
+#define regAZALIA_SOCCLK_CONTROL                                                                        0x03c5
+#define regAZALIA_SOCCLK_CONTROL_BASE_IDX                                                               2
+#define regAZALIA_UNDERFLOW_FILLER_SAMPLE                                                               0x03c6
+#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX                                                      2
+#define regAZALIA_DATA_DMA_CONTROL                                                                      0x03c7
+#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX                                                             2
+#define regAZALIA_BDL_DMA_CONTROL                                                                       0x03c8
+#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX                                                              2
+#define regAZALIA_RIRB_AND_DP_CONTROL                                                                   0x03c9
+#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2
+#define regAZALIA_CORB_DMA_CONTROL                                                                      0x03ca
+#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX                                                             2
+#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER                                                 0x03d1
+#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX                                        2
+#define regAZALIA_CYCLIC_BUFFER_SYNC                                                                    0x03d2
+#define regAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX                                                           2
+#define regAZALIA_GLOBAL_CAPABILITIES                                                                   0x03d3
+#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX                                                          2
+#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                                             0x03d4
+#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                    2
+#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                                         0x03d5
+#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2
+#define regAZALIA_INPUT_PAYLOAD_CAPABILITY                                                              0x03d6
+#define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                     2
+#define regAZALIA_INPUT_CRC0_CONTROL0                                                                   0x03d9
+#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_CONTROL1                                                                   0x03da
+#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_CONTROL2                                                                   0x03db
+#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_CONTROL3                                                                   0x03dc
+#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_RESULT                                                                     0x03dd
+#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX                                                            2
+#define regAZALIA_INPUT_CRC1_CONTROL0                                                                   0x03de
+#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_CONTROL1                                                                   0x03df
+#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_CONTROL2                                                                   0x03e0
+#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_CONTROL3                                                                   0x03e1
+#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_RESULT                                                                     0x03e2
+#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX                                                            2
+#define regAZALIA_CRC0_CONTROL0                                                                         0x03e3
+#define regAZALIA_CRC0_CONTROL0_BASE_IDX                                                                2
+#define regAZALIA_CRC0_CONTROL1                                                                         0x03e4
+#define regAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2
+#define regAZALIA_CRC0_CONTROL2                                                                         0x03e5
+#define regAZALIA_CRC0_CONTROL2_BASE_IDX                                                                2
+#define regAZALIA_CRC0_CONTROL3                                                                         0x03e6
+#define regAZALIA_CRC0_CONTROL3_BASE_IDX                                                                2
+#define regAZALIA_CRC0_RESULT                                                                           0x03e7
+#define regAZALIA_CRC0_RESULT_BASE_IDX                                                                  2
+#define regAZALIA_CRC1_CONTROL0                                                                         0x03e8
+#define regAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2
+#define regAZALIA_CRC1_CONTROL1                                                                         0x03e9
+#define regAZALIA_CRC1_CONTROL1_BASE_IDX                                                                2
+#define regAZALIA_CRC1_CONTROL2                                                                         0x03ea
+#define regAZALIA_CRC1_CONTROL2_BASE_IDX                                                                2
+#define regAZALIA_CRC1_CONTROL3                                                                         0x03eb
+#define regAZALIA_CRC1_CONTROL3_BASE_IDX                                                                2
+#define regAZALIA_CRC1_RESULT                                                                           0x03ec
+#define regAZALIA_CRC1_RESULT_BASE_IDX                                                                  2
+#define regAZALIA_MEM_PWR_CTRL                                                                          0x03ee
+#define regAZALIA_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regAZALIA_MEM_PWR_STATUS                                                                        0x03ef
+#define regAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_hda_azf0root_dispdec
+// base address: 0x0
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0406
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX                                 2
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0407
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX                                          2
+#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0408
+#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2
+#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                                          0x0409
+#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX                                                 2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x040a
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX                                       2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x040b
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX                             2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x040c
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX                                   2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x040d
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX                                     2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x040e
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX                                        2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                                       0x040f
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX                                              2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x0410
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX                              2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x0411
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX                          2
+#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                                            0x0412
+#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                   2
+#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                      0x0413
+#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                             2
+#define regAZALIA_F0_GTC_GROUP_OFFSET0                                                                  0x0415
+#define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET1                                                                  0x0416
+#define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET2                                                                  0x0417
+#define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET3                                                                  0x0418
+#define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET4                                                                  0x0419
+#define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET5                                                                  0x041a
+#define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET6                                                                  0x041b
+#define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX                                                         2
+#define regREG_DC_AUDIO_PORT_CONNECTIVITY                                                               0x041c
+#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                      2
+#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                         0x041d
+#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                                2
+
+
+// addressBlock: dce_dc_hda_az_misc_dispdec
+// base address: 0x0
+#define regAZ_CLOCK_CNTL                                                                                0x0372
+#define regAZ_CLOCK_CNTL_BASE_IDX                                                                       2
+
+
+// addressBlock: dce_dc_hda_azf0stream0_dispdec
+// base address: 0x0
+#define regAZF0STREAM0_AZALIA_STREAM_INDEX                                                              0x035e
+#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM0_AZALIA_STREAM_DATA                                                               0x035f
+#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream1_dispdec
+// base address: 0x8
+#define regAZF0STREAM1_AZALIA_STREAM_INDEX                                                              0x0360
+#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM1_AZALIA_STREAM_DATA                                                               0x0361
+#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream2_dispdec
+// base address: 0x10
+#define regAZF0STREAM2_AZALIA_STREAM_INDEX                                                              0x0362
+#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM2_AZALIA_STREAM_DATA                                                               0x0363
+#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream3_dispdec
+// base address: 0x18
+#define regAZF0STREAM3_AZALIA_STREAM_INDEX                                                              0x0364
+#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM3_AZALIA_STREAM_DATA                                                               0x0365
+#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream4_dispdec
+// base address: 0x20
+#define regAZF0STREAM4_AZALIA_STREAM_INDEX                                                              0x0366
+#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM4_AZALIA_STREAM_DATA                                                               0x0367
+#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream5_dispdec
+// base address: 0x28
+#define regAZF0STREAM5_AZALIA_STREAM_INDEX                                                              0x0368
+#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM5_AZALIA_STREAM_DATA                                                               0x0369
+#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream6_dispdec
+// base address: 0x30
+#define regAZF0STREAM6_AZALIA_STREAM_INDEX                                                              0x036a
+#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM6_AZALIA_STREAM_DATA                                                               0x036b
+#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream7_dispdec
+// base address: 0x38
+#define regAZF0STREAM7_AZALIA_STREAM_INDEX                                                              0x036c
+#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM7_AZALIA_STREAM_DATA                                                               0x036d
+#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream8_dispdec
+// base address: 0x320
+#define regAZF0STREAM8_AZALIA_STREAM_INDEX                                                              0x0426
+#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM8_AZALIA_STREAM_DATA                                                               0x0427
+#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream9_dispdec
+// base address: 0x328
+#define regAZF0STREAM9_AZALIA_STREAM_INDEX                                                              0x0428
+#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM9_AZALIA_STREAM_DATA                                                               0x0429
+#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream10_dispdec
+// base address: 0x330
+#define regAZF0STREAM10_AZALIA_STREAM_INDEX                                                             0x042a
+#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM10_AZALIA_STREAM_DATA                                                              0x042b
+#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream11_dispdec
+// base address: 0x338
+#define regAZF0STREAM11_AZALIA_STREAM_INDEX                                                             0x042c
+#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM11_AZALIA_STREAM_DATA                                                              0x042d
+#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream12_dispdec
+// base address: 0x340
+#define regAZF0STREAM12_AZALIA_STREAM_INDEX                                                             0x042e
+#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM12_AZALIA_STREAM_DATA                                                              0x042f
+#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream13_dispdec
+// base address: 0x348
+#define regAZF0STREAM13_AZALIA_STREAM_INDEX                                                             0x0430
+#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM13_AZALIA_STREAM_DATA                                                              0x0431
+#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream14_dispdec
+// base address: 0x350
+#define regAZF0STREAM14_AZALIA_STREAM_INDEX                                                             0x0432
+#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM14_AZALIA_STREAM_DATA                                                              0x0433
+#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream15_dispdec
+// base address: 0x358
+#define regAZF0STREAM15_AZALIA_STREAM_INDEX                                                             0x0434
+#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM15_AZALIA_STREAM_DATA                                                              0x0435
+#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
+// base address: 0x0
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0386
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0387
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
+// base address: 0x18
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x038c
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x038d
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
+// base address: 0x30
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0392
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0393
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
+// base address: 0x48
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0398
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0399
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
+// base address: 0x60
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x039e
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x039f
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
+// base address: 0x78
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03a4
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03a5
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
+// base address: 0x90
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03aa
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03ab
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
+// base address: 0xa8
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03b0
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03b1
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
+// base address: 0x0
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043a
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043b
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
+// base address: 0x10
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043e
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043f
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
+// base address: 0x20
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0442
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0443
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
+// base address: 0x30
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0446
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0447
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
+// base address: 0x40
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044a
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044b
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
+// base address: 0x50
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044e
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044f
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
+// base address: 0x60
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0452
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0453
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
+// base address: 0x70
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0456
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0457
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_dispdec
+// base address: 0x0
+#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND                                                                 0x04f9
+#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX                                                        2
+#define regDCHUBBUB_ARB_SAT_LEVEL                                                                       0x04fa
+#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX                                                              2
+#define regDCHUBBUB_ARB_QOS_FORCE                                                                       0x04fb
+#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX                                                              2
+#define regDCHUBBUB_ARB_DRAM_STATE_CNTL                                                                 0x04fc
+#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX                                                        2
+#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL                                                             0x04fd
+#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL_BASE_IDX                                                    2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A                                                        0x04fe
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A                                                      0x04ff
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A                                                     0x0500
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A                                                      0x0501
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A                                                       0x0502
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A                                                  0x0503
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A                                                  0x0504
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A                                                               0x0505
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A                                                              0x0506
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B                                                        0x0507
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B                                                      0x0508
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B                                                     0x0509
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B                                                      0x050a
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B                                                       0x050b
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B                                                  0x050c
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B                                                  0x050d
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B                                                               0x050e
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B                                                              0x050f
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C                                                        0x0510
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C                                                      0x0511
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C                                                     0x0512
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C                                                      0x0513
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C                                                       0x0514
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C                                                  0x0515
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C                                                  0x0516
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C                                                               0x0517
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C                                                              0x0518
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D                                                        0x0519
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D                                                      0x051a
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D                                                     0x051b
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D                                                      0x051c
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D                                                       0x051d
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D                                                  0x051e
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D                                                  0x051f
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D                                                               0x0520
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D                                                              0x0521
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL                                                           0x0522
+#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX                                                  2
+#define regDCHUBBUB_ARB_MALL_CNTL                                                                       0x0523
+#define regDCHUBBUB_ARB_MALL_CNTL_BASE_IDX                                                              2
+#define regDCHUBBUB_ARB_TIMEOUT_ENABLE                                                                  0x0524
+#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX                                                         2
+#define regDCHUBBUB_GLOBAL_TIMER_CNTL                                                                   0x0525
+#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX                                                          2
+#define regSURFACE_CHECK0_ADDRESS_LSB                                                                   0x0526
+#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK0_ADDRESS_MSB                                                                   0x0527
+#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK1_ADDRESS_LSB                                                                   0x0528
+#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK1_ADDRESS_MSB                                                                   0x0529
+#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK2_ADDRESS_LSB                                                                   0x052a
+#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK2_ADDRESS_MSB                                                                   0x052b
+#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK3_ADDRESS_LSB                                                                   0x052c
+#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK3_ADDRESS_MSB                                                                   0x052d
+#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX                                                          2
+#define regVTG0_CONTROL                                                                                 0x052e
+#define regVTG0_CONTROL_BASE_IDX                                                                        2
+#define regVTG1_CONTROL                                                                                 0x052f
+#define regVTG1_CONTROL_BASE_IDX                                                                        2
+#define regVTG2_CONTROL                                                                                 0x0530
+#define regVTG2_CONTROL_BASE_IDX                                                                        2
+#define regVTG3_CONTROL                                                                                 0x0531
+#define regVTG3_CONTROL_BASE_IDX                                                                        2
+#define regDCHUBBUB_SOFT_RESET                                                                          0x0532
+#define regDCHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
+#define regDCHUBBUB_CLOCK_CNTL                                                                          0x0533
+#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
+#define regDCFCLK_CNTL                                                                                  0x0534
+#define regDCFCLK_CNTL_BASE_IDX                                                                         2
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL                                                        0x0535
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX                                               2
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2                                                       0x0536
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX                                              2
+#define regDCHUBBUB_VLINE_SNAPSHOT                                                                      0x0537
+#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX                                                             2
+#define regDCHUBBUB_CTRL_STATUS                                                                         0x0538
+#define regDCHUBBUB_CTRL_STATUS_BASE_IDX                                                                2
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1                                                             0x053e
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX                                                    2
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2                                                             0x053f
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX                                                    2
+#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS                                                            0x0540
+#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX                                                   2
+#define regFMON_CTRL                                                                                    0x0541
+#define regFMON_CTRL_BASE_IDX                                                                           2
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec
+// base address: 0x0
+#define regDCHUBBUB_SDPIF_CFG0                                                                          0x046f
+#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX                                                                 2
+#define regDCHUBBUB_SDPIF_CFG1                                                                          0x0470
+#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX                                                                 2
+#define regDCHUBBUB_SDPIF_CFG2                                                                          0x0471
+#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX                                                                 2
+#define regVM_REQUEST_PHYSICAL                                                                          0x0472
+#define regVM_REQUEST_PHYSICAL_BASE_IDX                                                                 2
+#define regDCHUBBUB_FORCE_IO_STATUS_0                                                                   0x0473
+#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX                                                          2
+#define regDCHUBBUB_FORCE_IO_STATUS_1                                                                   0x0474
+#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX                                                          2
+#define regDCN_VM_FB_LOCATION_BASE                                                                      0x0475
+#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX                                                             2
+#define regDCN_VM_FB_LOCATION_TOP                                                                       0x0476
+#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX                                                              2
+#define regDCN_VM_FB_OFFSET                                                                             0x0477
+#define regDCN_VM_FB_OFFSET_BASE_IDX                                                                    2
+#define regDCN_VM_AGP_BOT                                                                               0x0478
+#define regDCN_VM_AGP_BOT_BASE_IDX                                                                      2
+#define regDCN_VM_AGP_TOP                                                                               0x0479
+#define regDCN_VM_AGP_TOP_BASE_IDX                                                                      2
+#define regDCN_VM_AGP_BASE                                                                              0x047a
+#define regDCN_VM_AGP_BASE_BASE_IDX                                                                     2
+#define regDCN_VM_LOCAL_HBM_ADDRESS_START                                                               0x047b
+#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                                      2
+#define regDCN_VM_LOCAL_HBM_ADDRESS_END                                                                 0x047c
+#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                                        2
+#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                           0x047d
+#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                                  2
+#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL                                                                  0x047e
+#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX                                                         2
+#define regDCHUBBUB_SDPIF_PIPE_NOALLOC                                                                  0x047f
+#define regDCHUBBUB_SDPIF_PIPE_NOALLOC_BASE_IDX                                                         2
+#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL                                                           0x0480
+#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX                                                  2
+#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL                                                          0x0481
+#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL_BASE_IDX                                                 2
+#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL                                                          0x0482
+#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL_BASE_IDX                                                 2
+#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL                                                            0x0483
+#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL_BASE_IDX                                                   2
+#define regSDPIF_REQUEST_RATE_LIMIT                                                                     0x0484
+#define regSDPIF_REQUEST_RATE_LIMIT_BASE_IDX                                                            2
+#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL                                                                  0x0485
+#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX                                                         2
+#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS                                                                0x0486
+#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX                                                       2
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec
+// base address: 0x0
+#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL                                                               0x04af
+#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX                                                      2
+#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS                                                             0x04b0
+#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX                                                    2
+#define regDCHUBBUB_CRC_CTRL                                                                            0x04b1
+#define regDCHUBBUB_CRC_CTRL_BASE_IDX                                                                   2
+#define regDCHUBBUB_CRC0_VAL_R_G                                                                        0x04b2
+#define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX                                                               2
+#define regDCHUBBUB_CRC0_VAL_B_A                                                                        0x04b3
+#define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX                                                               2
+#define regDCHUBBUB_CRC1_VAL_R_G                                                                        0x04b4
+#define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX                                                               2
+#define regDCHUBBUB_CRC1_VAL_B_A                                                                        0x04b5
+#define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX                                                               2
+#define regDCHUBBUB_DCC_STAT_CNTL                                                                       0x04b6
+#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX                                                              2
+#define regDCHUBBUB_DCC_STAT0                                                                           0x04b7
+#define regDCHUBBUB_DCC_STAT0_BASE_IDX                                                                  2
+#define regDCHUBBUB_DCC_STAT1                                                                           0x04b8
+#define regDCHUBBUB_DCC_STAT1_BASE_IDX                                                                  2
+#define regDCHUBBUB_DCC_STAT2                                                                           0x04b9
+#define regDCHUBBUB_DCC_STAT2_BASE_IDX                                                                  2
+#define regDCHUBBUB_COMPBUF_CTRL                                                                        0x04ba
+#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX                                                               2
+#define regDCHUBBUB_DET0_CTRL                                                                           0x04bb
+#define regDCHUBBUB_DET0_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_DET1_CTRL                                                                           0x04bc
+#define regDCHUBBUB_DET1_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_DET2_CTRL                                                                           0x04bd
+#define regDCHUBBUB_DET2_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_DET3_CTRL                                                                           0x04be
+#define regDCHUBBUB_DET3_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_MEM_PWR_MODE_CTRL                                                                   0x04c0
+#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX                                                          2
+#define regCOMPBUF_MEM_PWR_CTRL_1                                                                       0x04c1
+#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX                                                              2
+#define regCOMPBUF_MEM_PWR_CTRL_2                                                                       0x04c2
+#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX                                                              2
+#define regDCHUBBUB_MEM_PWR_STATUS                                                                      0x04c3
+#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
+#define regCOMPBUF_RESERVED_SPACE                                                                       0x04c4
+#define regCOMPBUF_RESERVED_SPACE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec
+// base address: 0x0
+#define regDCN_VM_CONTEXT0_CNTL                                                                         0x0559
+#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                    0x055a
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                    0x055b
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                   0x055c
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                   0x055d
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                     0x055e
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                     0x055f
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT1_CNTL                                                                         0x0560
+#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0561
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0562
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                   0x0563
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                   0x0564
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                     0x0565
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                     0x0566
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT2_CNTL                                                                         0x0567
+#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0568
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0569
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                   0x056a
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                   0x056b
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                     0x056c
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                     0x056d
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT3_CNTL                                                                         0x056e
+#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                    0x056f
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0570
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                   0x0571
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                   0x0572
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                     0x0573
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                     0x0574
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT4_CNTL                                                                         0x0575
+#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0576
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0577
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                   0x0578
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                   0x0579
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                     0x057a
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                     0x057b
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT5_CNTL                                                                         0x057c
+#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                    0x057d
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                    0x057e
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                   0x057f
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                   0x0580
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                     0x0581
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                     0x0582
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT6_CNTL                                                                         0x0583
+#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0584
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0585
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                   0x0586
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                   0x0587
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                     0x0588
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                     0x0589
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT7_CNTL                                                                         0x058a
+#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                    0x058b
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                    0x058c
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                   0x058d
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                   0x058e
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                     0x058f
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                     0x0590
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT8_CNTL                                                                         0x0591
+#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0592
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0593
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                   0x0594
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                   0x0595
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                     0x0596
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                     0x0597
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT9_CNTL                                                                         0x0598
+#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0599
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                    0x059a
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                   0x059b
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                   0x059c
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                     0x059d
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                     0x059e
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT10_CNTL                                                                        0x059f
+#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a0
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a1
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                  0x05a2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                  0x05a3
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                    0x05a4
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                    0x05a5
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT11_CNTL                                                                        0x05a6
+#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a7
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a8
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                  0x05a9
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                  0x05aa
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                    0x05ab
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                    0x05ac
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT12_CNTL                                                                        0x05ad
+#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05ae
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05af
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                  0x05b0
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                  0x05b1
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                    0x05b2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                    0x05b3
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT13_CNTL                                                                        0x05b4
+#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05b5
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05b6
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                  0x05b7
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                  0x05b8
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                    0x05b9
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                    0x05ba
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT14_CNTL                                                                        0x05bb
+#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05bc
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05bd
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                  0x05be
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                  0x05bf
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                    0x05c0
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                    0x05c1
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT15_CNTL                                                                        0x05c2
+#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05c3
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05c4
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                  0x05c5
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                  0x05c6
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                    0x05c7
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                    0x05c8
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_DEFAULT_ADDR_MSB                                                                      0x05c9
+#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX                                                             2
+#define regDCN_VM_DEFAULT_ADDR_LSB                                                                      0x05ca
+#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX                                                             2
+#define regDCN_VM_FAULT_CNTL                                                                            0x05cb
+#define regDCN_VM_FAULT_CNTL_BASE_IDX                                                                   2
+#define regDCN_VM_FAULT_STATUS                                                                          0x05cc
+#define regDCN_VM_FAULT_STATUS_BASE_IDX                                                                 2
+#define regDCN_VM_FAULT_ADDR_MSB                                                                        0x05cd
+#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX                                                               2
+#define regDCN_VM_FAULT_ADDR_LSB                                                                        0x05ce
+#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
+// base address: 0x0
+#define regHUBP0_DCSURF_SURFACE_CONFIG                                                                  0x05e5
+#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP0_DCSURF_ADDR_CONFIG                                                                     0x05e6
+#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP0_DCSURF_TILING_CONFIG                                                                   0x05e7
+#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START                                                              0x05e9
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x05ea
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C                                                            0x05eb
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x05ec
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START                                                              0x05ed
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x05ee
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C                                                            0x05ef
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x05f0
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG                                                                 0x05f1
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x05f2
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP0_DCHUBP_CNTL                                                                            0x05f3
+#define regHUBP0_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP0_HUBP_CLK_CNTL                                                                          0x05f4
+#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP0_DCHUBP_VMPG_CONFIG                                                                     0x05f5
+#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP0_DCHUBP_MALL_CONFIG                                                                     0x05f6
+#define regHUBP0_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
+#define regHUBP0_DCHUBP_MALL_SUB_VP                                                                     0x05f7
+#define regHUBP0_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
+#define regHUBP0_HUBPREQ_DEBUG_DB                                                                       0x05f8
+#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP0_HUBPREQ_DEBUG                                                                          0x05f9
+#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x05fd
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x05fe
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+#define regHUBP0_HUBP_MALL_STATUS                                                                       0x05ff
+#define regHUBP0_HUBP_MALL_STATUS_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
+// base address: 0x0
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH                                                                0x0607
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C                                                              0x0608
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ0_VMID_SETTINGS_0                                                                     0x0609
+#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x060a
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x060b
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x060c
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x060d
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x060e
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x060f
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x0610
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x0611
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x0612
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x0613
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x0614
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x0615
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x0616
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x0617
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x0618
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x0619
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ0_DCSURF_SURFACE_CONTROL                                                              0x061a
+#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL                                                                 0x061b
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL2                                                                0x061c
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x061f
+#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE                                                                0x0620
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH                                                           0x0621
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C                                                              0x0622
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0623
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0624
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0625
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0626
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0627
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ0_DCN_EXPANSION_MODE                                                                  0x0628
+#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_TTU_QOS_WM                                                                      0x0629
+#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL                                                                 0x062a
+#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0                                                                 0x062b
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1                                                                 0x062c
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0                                                                 0x062d
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1                                                                 0x062e
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0                                                                  0x062f
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1                                                                  0x0630
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0                                                                  0x0631
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1                                                                  0x0632
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_DMDATA_VM_CNTL                                                                  0x0633
+#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0634
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0635
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL                                                               0x0642
+#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ0_BLANK_OFFSET_0                                                                      0x0643
+#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ0_BLANK_OFFSET_1                                                                      0x0644
+#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ0_DST_DIMENSIONS                                                                      0x0645
+#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ0_DST_AFTER_SCALER                                                                    0x0646
+#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ0_PREFETCH_SETTINGS                                                                   0x0647
+#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ0_PREFETCH_SETTINGS_C                                                                 0x0648
+#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_0                                                                 0x0649
+#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_1                                                                 0x064a
+#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_2                                                                 0x064b
+#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_3                                                                 0x064c
+#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_4                                                                 0x064d
+#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ0_FLIP_PARAMETERS_0                                                                   0x064e
+#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_1                                                                   0x064f
+#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_2                                                                   0x0650
+#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ0_NOM_PARAMETERS_0                                                                    0x0651
+#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_1                                                                    0x0652
+#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_2                                                                    0x0653
+#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_3                                                                    0x0654
+#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_4                                                                    0x0655
+#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_5                                                                    0x0656
+#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_6                                                                    0x0657
+#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_7                                                                    0x0658
+#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ0_PER_LINE_DELIVERY_PRE                                                               0x0659
+#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ0_PER_LINE_DELIVERY                                                                   0x065a
+#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ0_CURSOR_SETTINGS                                                                     0x065b
+#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ                                                                0x065c
+#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT                                                               0x065d
+#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL                                                                0x065e
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS                                                              0x065f
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ0_VBLANK_PARAMETERS_5                                                                 0x0662
+#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_6                                                                 0x0663
+#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ0_FLIP_PARAMETERS_3                                                                   0x0664
+#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_4                                                                   0x0665
+#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_5                                                                   0x0666
+#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_6                                                                   0x0667
+#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+#define regHUBPREQ0_UCLK_PSTATE_FORCE                                                                   0x0668
+#define regHUBPREQ0_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
+#define regHUBPREQ0_HUBPREQ_STATUS_REG0                                                                 0x0669
+#define regHUBPREQ0_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
+#define regHUBPREQ0_HUBPREQ_STATUS_REG1                                                                 0x066a
+#define regHUBPREQ0_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
+#define regHUBPREQ0_HUBPREQ_STATUS_REG2                                                                 0x066b
+#define regHUBPREQ0_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
+// base address: 0x0
+#define regHUBPRET0_HUBPRET_CONTROL                                                                     0x066c
+#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL                                                                0x066d
+#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS                                                              0x066e
+#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0                                                             0x066f
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1                                                             0x0670
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET0_HUBPRET_READ_LINE0                                                                  0x0671
+#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET0_HUBPRET_READ_LINE1                                                                  0x0672
+#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET0_HUBPRET_INTERRUPT                                                                   0x0673
+#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET0_HUBPRET_READ_LINE_VALUE                                                             0x0674
+#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET0_HUBPRET_READ_LINE_STATUS                                                            0x0675
+#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
+// base address: 0x0
+#define regCURSOR0_0_CURSOR_CONTROL                                                                     0x0678
+#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS                                                             0x0679
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x067a
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_0_CURSOR_SIZE                                                                        0x067b
+#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_0_CURSOR_POSITION                                                                    0x067c
+#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_0_CURSOR_HOT_SPOT                                                                    0x067d
+#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_0_CURSOR_STEREO_CONTROL                                                              0x067e
+#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_0_CURSOR_DST_OFFSET                                                                  0x067f
+#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL                                                                0x0680
+#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS                                                              0x0681
+#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_0_DMDATA_ADDRESS_HIGH                                                                0x0682
+#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_0_DMDATA_ADDRESS_LOW                                                                 0x0683
+#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_0_DMDATA_CNTL                                                                        0x0684
+#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_0_DMDATA_QOS_CNTL                                                                    0x0685
+#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_0_DMDATA_STATUS                                                                      0x0686
+#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_0_DMDATA_SW_CNTL                                                                     0x0687
+#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_0_DMDATA_SW_DATA                                                                     0x0688
+#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
+// base address: 0x370
+#define regHUBP1_DCSURF_SURFACE_CONFIG                                                                  0x06c1
+#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP1_DCSURF_ADDR_CONFIG                                                                     0x06c2
+#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP1_DCSURF_TILING_CONFIG                                                                   0x06c3
+#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START                                                              0x06c5
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x06c6
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C                                                            0x06c7
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x06c8
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START                                                              0x06c9
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x06ca
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C                                                            0x06cb
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x06cc
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG                                                                 0x06cd
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x06ce
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP1_DCHUBP_CNTL                                                                            0x06cf
+#define regHUBP1_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP1_HUBP_CLK_CNTL                                                                          0x06d0
+#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP1_DCHUBP_VMPG_CONFIG                                                                     0x06d1
+#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP1_DCHUBP_MALL_CONFIG                                                                     0x06d2
+#define regHUBP1_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
+#define regHUBP1_DCHUBP_MALL_SUB_VP                                                                     0x06d3
+#define regHUBP1_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
+#define regHUBP1_HUBPREQ_DEBUG_DB                                                                       0x06d4
+#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP1_HUBPREQ_DEBUG                                                                          0x06d5
+#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x06d9
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x06da
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+#define regHUBP1_HUBP_MALL_STATUS                                                                       0x06db
+#define regHUBP1_HUBP_MALL_STATUS_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
+// base address: 0x370
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH                                                                0x06e3
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C                                                              0x06e4
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ1_VMID_SETTINGS_0                                                                     0x06e5
+#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x06e6
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x06e7
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x06e8
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x06e9
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x06ea
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x06eb
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x06ec
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x06ed
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x06ee
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x06ef
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x06f0
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x06f1
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x06f2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x06f3
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x06f4
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x06f5
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ1_DCSURF_SURFACE_CONTROL                                                              0x06f6
+#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL                                                                 0x06f7
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL2                                                                0x06f8
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x06fb
+#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE                                                                0x06fc
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH                                                           0x06fd
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C                                                              0x06fe
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x06ff
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0700
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0701
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0702
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0703
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ1_DCN_EXPANSION_MODE                                                                  0x0704
+#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_TTU_QOS_WM                                                                      0x0705
+#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL                                                                 0x0706
+#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0                                                                 0x0707
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1                                                                 0x0708
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0                                                                 0x0709
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1                                                                 0x070a
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0                                                                  0x070b
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1                                                                  0x070c
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0                                                                  0x070d
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1                                                                  0x070e
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_DMDATA_VM_CNTL                                                                  0x070f
+#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0710
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0711
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL                                                               0x071e
+#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ1_BLANK_OFFSET_0                                                                      0x071f
+#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ1_BLANK_OFFSET_1                                                                      0x0720
+#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ1_DST_DIMENSIONS                                                                      0x0721
+#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ1_DST_AFTER_SCALER                                                                    0x0722
+#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ1_PREFETCH_SETTINGS                                                                   0x0723
+#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ1_PREFETCH_SETTINGS_C                                                                 0x0724
+#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_0                                                                 0x0725
+#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_1                                                                 0x0726
+#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_2                                                                 0x0727
+#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_3                                                                 0x0728
+#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_4                                                                 0x0729
+#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ1_FLIP_PARAMETERS_0                                                                   0x072a
+#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_1                                                                   0x072b
+#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_2                                                                   0x072c
+#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ1_NOM_PARAMETERS_0                                                                    0x072d
+#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_1                                                                    0x072e
+#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_2                                                                    0x072f
+#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_3                                                                    0x0730
+#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_4                                                                    0x0731
+#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_5                                                                    0x0732
+#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_6                                                                    0x0733
+#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_7                                                                    0x0734
+#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ1_PER_LINE_DELIVERY_PRE                                                               0x0735
+#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ1_PER_LINE_DELIVERY                                                                   0x0736
+#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ1_CURSOR_SETTINGS                                                                     0x0737
+#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ                                                                0x0738
+#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT                                                               0x0739
+#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL                                                                0x073a
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS                                                              0x073b
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ1_VBLANK_PARAMETERS_5                                                                 0x073e
+#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_6                                                                 0x073f
+#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ1_FLIP_PARAMETERS_3                                                                   0x0740
+#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_4                                                                   0x0741
+#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_5                                                                   0x0742
+#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_6                                                                   0x0743
+#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+#define regHUBPREQ1_UCLK_PSTATE_FORCE                                                                   0x0744
+#define regHUBPREQ1_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
+#define regHUBPREQ1_HUBPREQ_STATUS_REG0                                                                 0x0745
+#define regHUBPREQ1_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
+#define regHUBPREQ1_HUBPREQ_STATUS_REG1                                                                 0x0746
+#define regHUBPREQ1_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
+#define regHUBPREQ1_HUBPREQ_STATUS_REG2                                                                 0x0747
+#define regHUBPREQ1_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
+// base address: 0x370
+#define regHUBPRET1_HUBPRET_CONTROL                                                                     0x0748
+#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL                                                                0x0749
+#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS                                                              0x074a
+#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0                                                             0x074b
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1                                                             0x074c
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET1_HUBPRET_READ_LINE0                                                                  0x074d
+#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET1_HUBPRET_READ_LINE1                                                                  0x074e
+#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET1_HUBPRET_INTERRUPT                                                                   0x074f
+#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET1_HUBPRET_READ_LINE_VALUE                                                             0x0750
+#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET1_HUBPRET_READ_LINE_STATUS                                                            0x0751
+#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
+// base address: 0x370
+#define regCURSOR0_1_CURSOR_CONTROL                                                                     0x0754
+#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS                                                             0x0755
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0756
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_1_CURSOR_SIZE                                                                        0x0757
+#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_1_CURSOR_POSITION                                                                    0x0758
+#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_1_CURSOR_HOT_SPOT                                                                    0x0759
+#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_1_CURSOR_STEREO_CONTROL                                                              0x075a
+#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_1_CURSOR_DST_OFFSET                                                                  0x075b
+#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL                                                                0x075c
+#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS                                                              0x075d
+#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_1_DMDATA_ADDRESS_HIGH                                                                0x075e
+#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_1_DMDATA_ADDRESS_LOW                                                                 0x075f
+#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_1_DMDATA_CNTL                                                                        0x0760
+#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_1_DMDATA_QOS_CNTL                                                                    0x0761
+#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_1_DMDATA_STATUS                                                                      0x0762
+#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_1_DMDATA_SW_CNTL                                                                     0x0763
+#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_1_DMDATA_SW_DATA                                                                     0x0764
+#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
+// base address: 0x6e0
+#define regHUBP2_DCSURF_SURFACE_CONFIG                                                                  0x079d
+#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP2_DCSURF_ADDR_CONFIG                                                                     0x079e
+#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP2_DCSURF_TILING_CONFIG                                                                   0x079f
+#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START                                                              0x07a1
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x07a2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C                                                            0x07a3
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x07a4
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START                                                              0x07a5
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x07a6
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C                                                            0x07a7
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x07a8
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG                                                                 0x07a9
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x07aa
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP2_DCHUBP_CNTL                                                                            0x07ab
+#define regHUBP2_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP2_HUBP_CLK_CNTL                                                                          0x07ac
+#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP2_DCHUBP_VMPG_CONFIG                                                                     0x07ad
+#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP2_DCHUBP_MALL_CONFIG                                                                     0x07ae
+#define regHUBP2_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
+#define regHUBP2_DCHUBP_MALL_SUB_VP                                                                     0x07af
+#define regHUBP2_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
+#define regHUBP2_HUBPREQ_DEBUG_DB                                                                       0x07b0
+#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP2_HUBPREQ_DEBUG                                                                          0x07b1
+#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x07b5
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x07b6
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+#define regHUBP2_HUBP_MALL_STATUS                                                                       0x07b7
+#define regHUBP2_HUBP_MALL_STATUS_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
+// base address: 0x6e0
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH                                                                0x07bf
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C                                                              0x07c0
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ2_VMID_SETTINGS_0                                                                     0x07c1
+#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x07c2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x07c3
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x07c4
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x07c5
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x07c6
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x07c7
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x07c8
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x07c9
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x07ca
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x07cb
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x07cc
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x07cd
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x07ce
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x07cf
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x07d0
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x07d1
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ2_DCSURF_SURFACE_CONTROL                                                              0x07d2
+#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL                                                                 0x07d3
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL2                                                                0x07d4
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x07d7
+#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE                                                                0x07d8
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH                                                           0x07d9
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C                                                              0x07da
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x07db
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x07dc
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x07dd
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x07de
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x07df
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ2_DCN_EXPANSION_MODE                                                                  0x07e0
+#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_TTU_QOS_WM                                                                      0x07e1
+#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL                                                                 0x07e2
+#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0                                                                 0x07e3
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1                                                                 0x07e4
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0                                                                 0x07e5
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1                                                                 0x07e6
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0                                                                  0x07e7
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1                                                                  0x07e8
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0                                                                  0x07e9
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1                                                                  0x07ea
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_DMDATA_VM_CNTL                                                                  0x07eb
+#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x07ec
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x07ed
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL                                                               0x07fa
+#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ2_BLANK_OFFSET_0                                                                      0x07fb
+#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ2_BLANK_OFFSET_1                                                                      0x07fc
+#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ2_DST_DIMENSIONS                                                                      0x07fd
+#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ2_DST_AFTER_SCALER                                                                    0x07fe
+#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ2_PREFETCH_SETTINGS                                                                   0x07ff
+#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ2_PREFETCH_SETTINGS_C                                                                 0x0800
+#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_0                                                                 0x0801
+#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_1                                                                 0x0802
+#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_2                                                                 0x0803
+#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_3                                                                 0x0804
+#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_4                                                                 0x0805
+#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ2_FLIP_PARAMETERS_0                                                                   0x0806
+#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_1                                                                   0x0807
+#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_2                                                                   0x0808
+#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ2_NOM_PARAMETERS_0                                                                    0x0809
+#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_1                                                                    0x080a
+#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_2                                                                    0x080b
+#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_3                                                                    0x080c
+#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_4                                                                    0x080d
+#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_5                                                                    0x080e
+#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_6                                                                    0x080f
+#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_7                                                                    0x0810
+#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ2_PER_LINE_DELIVERY_PRE                                                               0x0811
+#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ2_PER_LINE_DELIVERY                                                                   0x0812
+#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ2_CURSOR_SETTINGS                                                                     0x0813
+#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ                                                                0x0814
+#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT                                                               0x0815
+#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL                                                                0x0816
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS                                                              0x0817
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ2_VBLANK_PARAMETERS_5                                                                 0x081a
+#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_6                                                                 0x081b
+#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ2_FLIP_PARAMETERS_3                                                                   0x081c
+#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_4                                                                   0x081d
+#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_5                                                                   0x081e
+#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_6                                                                   0x081f
+#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+#define regHUBPREQ2_UCLK_PSTATE_FORCE                                                                   0x0820
+#define regHUBPREQ2_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
+#define regHUBPREQ2_HUBPREQ_STATUS_REG0                                                                 0x0821
+#define regHUBPREQ2_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
+#define regHUBPREQ2_HUBPREQ_STATUS_REG1                                                                 0x0822
+#define regHUBPREQ2_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
+#define regHUBPREQ2_HUBPREQ_STATUS_REG2                                                                 0x0823
+#define regHUBPREQ2_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
+// base address: 0x6e0
+#define regHUBPRET2_HUBPRET_CONTROL                                                                     0x0824
+#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL                                                                0x0825
+#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS                                                              0x0826
+#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0                                                             0x0827
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1                                                             0x0828
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET2_HUBPRET_READ_LINE0                                                                  0x0829
+#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET2_HUBPRET_READ_LINE1                                                                  0x082a
+#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET2_HUBPRET_INTERRUPT                                                                   0x082b
+#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET2_HUBPRET_READ_LINE_VALUE                                                             0x082c
+#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET2_HUBPRET_READ_LINE_STATUS                                                            0x082d
+#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
+// base address: 0x6e0
+#define regCURSOR0_2_CURSOR_CONTROL                                                                     0x0830
+#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS                                                             0x0831
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0832
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_2_CURSOR_SIZE                                                                        0x0833
+#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_2_CURSOR_POSITION                                                                    0x0834
+#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_2_CURSOR_HOT_SPOT                                                                    0x0835
+#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_2_CURSOR_STEREO_CONTROL                                                              0x0836
+#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_2_CURSOR_DST_OFFSET                                                                  0x0837
+#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL                                                                0x0838
+#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS                                                              0x0839
+#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_2_DMDATA_ADDRESS_HIGH                                                                0x083a
+#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_2_DMDATA_ADDRESS_LOW                                                                 0x083b
+#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_2_DMDATA_CNTL                                                                        0x083c
+#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_2_DMDATA_QOS_CNTL                                                                    0x083d
+#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_2_DMDATA_STATUS                                                                      0x083e
+#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_2_DMDATA_SW_CNTL                                                                     0x083f
+#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_2_DMDATA_SW_DATA                                                                     0x0840
+#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
+// base address: 0xa50
+#define regHUBP3_DCSURF_SURFACE_CONFIG                                                                  0x0879
+#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP3_DCSURF_ADDR_CONFIG                                                                     0x087a
+#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP3_DCSURF_TILING_CONFIG                                                                   0x087b
+#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START                                                              0x087d
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x087e
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C                                                            0x087f
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x0880
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START                                                              0x0881
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x0882
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C                                                            0x0883
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x0884
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG                                                                 0x0885
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x0886
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP3_DCHUBP_CNTL                                                                            0x0887
+#define regHUBP3_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP3_HUBP_CLK_CNTL                                                                          0x0888
+#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP3_DCHUBP_VMPG_CONFIG                                                                     0x0889
+#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP3_DCHUBP_MALL_CONFIG                                                                     0x088a
+#define regHUBP3_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
+#define regHUBP3_DCHUBP_MALL_SUB_VP                                                                     0x088b
+#define regHUBP3_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
+#define regHUBP3_HUBPREQ_DEBUG_DB                                                                       0x088c
+#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP3_HUBPREQ_DEBUG                                                                          0x088d
+#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x0891
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x0892
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+#define regHUBP3_HUBP_MALL_STATUS                                                                       0x0893
+#define regHUBP3_HUBP_MALL_STATUS_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
+// base address: 0xa50
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH                                                                0x089b
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C                                                              0x089c
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ3_VMID_SETTINGS_0                                                                     0x089d
+#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x089e
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x089f
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x08a0
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x08a1
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x08a2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x08a3
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x08a4
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x08a5
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x08a6
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x08a7
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x08a8
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x08a9
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x08aa
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x08ab
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x08ac
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x08ad
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ3_DCSURF_SURFACE_CONTROL                                                              0x08ae
+#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL                                                                 0x08af
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL2                                                                0x08b0
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x08b3
+#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE                                                                0x08b4
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH                                                           0x08b5
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C                                                              0x08b6
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x08b7
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x08b8
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x08b9
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x08ba
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x08bb
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ3_DCN_EXPANSION_MODE                                                                  0x08bc
+#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_TTU_QOS_WM                                                                      0x08bd
+#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL                                                                 0x08be
+#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0                                                                 0x08bf
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1                                                                 0x08c0
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0                                                                 0x08c1
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1                                                                 0x08c2
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0                                                                  0x08c3
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1                                                                  0x08c4
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0                                                                  0x08c5
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1                                                                  0x08c6
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_DMDATA_VM_CNTL                                                                  0x08c7
+#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x08c8
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x08c9
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL                                                               0x08d6
+#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ3_BLANK_OFFSET_0                                                                      0x08d7
+#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ3_BLANK_OFFSET_1                                                                      0x08d8
+#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ3_DST_DIMENSIONS                                                                      0x08d9
+#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ3_DST_AFTER_SCALER                                                                    0x08da
+#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ3_PREFETCH_SETTINGS                                                                   0x08db
+#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ3_PREFETCH_SETTINGS_C                                                                 0x08dc
+#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_0                                                                 0x08dd
+#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_1                                                                 0x08de
+#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_2                                                                 0x08df
+#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_3                                                                 0x08e0
+#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_4                                                                 0x08e1
+#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ3_FLIP_PARAMETERS_0                                                                   0x08e2
+#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_1                                                                   0x08e3
+#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_2                                                                   0x08e4
+#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ3_NOM_PARAMETERS_0                                                                    0x08e5
+#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_1                                                                    0x08e6
+#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_2                                                                    0x08e7
+#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_3                                                                    0x08e8
+#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_4                                                                    0x08e9
+#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_5                                                                    0x08ea
+#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_6                                                                    0x08eb
+#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_7                                                                    0x08ec
+#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ3_PER_LINE_DELIVERY_PRE                                                               0x08ed
+#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ3_PER_LINE_DELIVERY                                                                   0x08ee
+#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ3_CURSOR_SETTINGS                                                                     0x08ef
+#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ                                                                0x08f0
+#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT                                                               0x08f1
+#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL                                                                0x08f2
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS                                                              0x08f3
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ3_VBLANK_PARAMETERS_5                                                                 0x08f6
+#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_6                                                                 0x08f7
+#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ3_FLIP_PARAMETERS_3                                                                   0x08f8
+#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_4                                                                   0x08f9
+#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_5                                                                   0x08fa
+#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_6                                                                   0x08fb
+#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+#define regHUBPREQ3_UCLK_PSTATE_FORCE                                                                   0x08fc
+#define regHUBPREQ3_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
+#define regHUBPREQ3_HUBPREQ_STATUS_REG0                                                                 0x08fd
+#define regHUBPREQ3_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
+#define regHUBPREQ3_HUBPREQ_STATUS_REG1                                                                 0x08fe
+#define regHUBPREQ3_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
+#define regHUBPREQ3_HUBPREQ_STATUS_REG2                                                                 0x08ff
+#define regHUBPREQ3_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
+// base address: 0xa50
+#define regHUBPRET3_HUBPRET_CONTROL                                                                     0x0900
+#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL                                                                0x0901
+#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS                                                              0x0902
+#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0                                                             0x0903
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1                                                             0x0904
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET3_HUBPRET_READ_LINE0                                                                  0x0905
+#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET3_HUBPRET_READ_LINE1                                                                  0x0906
+#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET3_HUBPRET_INTERRUPT                                                                   0x0907
+#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET3_HUBPRET_READ_LINE_VALUE                                                             0x0908
+#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET3_HUBPRET_READ_LINE_STATUS                                                            0x0909
+#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
+// base address: 0xa50
+#define regCURSOR0_3_CURSOR_CONTROL                                                                     0x090c
+#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS                                                             0x090d
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x090e
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_3_CURSOR_SIZE                                                                        0x090f
+#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_3_CURSOR_POSITION                                                                    0x0910
+#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_3_CURSOR_HOT_SPOT                                                                    0x0911
+#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_3_CURSOR_STEREO_CONTROL                                                              0x0912
+#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_3_CURSOR_DST_OFFSET                                                                  0x0913
+#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL                                                                0x0914
+#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS                                                              0x0915
+#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_3_DMDATA_ADDRESS_HIGH                                                                0x0916
+#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_3_DMDATA_ADDRESS_LOW                                                                 0x0917
+#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_3_DMDATA_CNTL                                                                        0x0918
+#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_3_DMDATA_QOS_CNTL                                                                    0x0919
+#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_3_DMDATA_STATUS                                                                      0x091a
+#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_3_DMDATA_SW_CNTL                                                                     0x091b
+#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_3_DMDATA_SW_DATA                                                                     0x091c
+#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
+// base address: 0x0
+#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0ccf
+#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG0_FORMAT_CONTROL                                                                     0x0cd0
+#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_BIAS_R                                                                     0x0cd1
+#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_BIAS_G                                                                     0x0cd2
+#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_BIAS_B                                                                     0x0cd3
+#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_SCALE_R                                                                    0x0cd4
+#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG0_FCNV_FP_SCALE_G                                                                    0x0cd5
+#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG0_FCNV_FP_SCALE_B                                                                    0x0cd6
+#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG0_COLOR_KEYER_CONTROL                                                                0x0cd7
+#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG0_COLOR_KEYER_ALPHA                                                                  0x0cd8
+#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG0_COLOR_KEYER_RED                                                                    0x0cd9
+#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG0_COLOR_KEYER_GREEN                                                                  0x0cda
+#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG0_COLOR_KEYER_BLUE                                                                   0x0cdb
+#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG0_ALPHA_2BIT_LUT                                                                     0x0cdd
+#define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG0_PRE_DEALPHA                                                                        0x0cde
+#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG0_PRE_CSC_MODE                                                                       0x0cdf
+#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG0_PRE_CSC_C11_C12                                                                    0x0ce0
+#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C13_C14                                                                    0x0ce1
+#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C21_C22                                                                    0x0ce2
+#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C23_C24                                                                    0x0ce3
+#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C31_C32                                                                    0x0ce4
+#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C33_C34                                                                    0x0ce5
+#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_B_C11_C12                                                                  0x0ce6
+#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C13_C14                                                                  0x0ce7
+#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C21_C22                                                                  0x0ce8
+#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C23_C24                                                                  0x0ce9
+#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C31_C32                                                                  0x0cea
+#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C33_C34                                                                  0x0ceb
+#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG0_CNVC_COEF_FORMAT                                                                   0x0cec
+#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG0_PRE_DEGAM                                                                          0x0ced
+#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG0_PRE_REALPHA                                                                        0x0cee
+#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
+// base address: 0x0
+#define regCNVC_CUR0_CURSOR0_CONTROL                                                                    0x0cf1
+#define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR0_CURSOR0_COLOR0                                                                     0x0cf2
+#define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR0_CURSOR0_COLOR1                                                                     0x0cf3
+#define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS                                                              0x0cf4
+#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
+// base address: 0x0
+#define regDSCL0_SCL_COEF_RAM_TAP_SELECT                                                                0x0cf9
+#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL0_SCL_COEF_RAM_TAP_DATA                                                                  0x0cfa
+#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL0_SCL_MODE                                                                               0x0cfb
+#define regDSCL0_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL0_SCL_TAP_CONTROL                                                                        0x0cfc
+#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL0_DSCL_CONTROL                                                                           0x0cfd
+#define regDSCL0_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL0_DSCL_2TAP_CONTROL                                                                      0x0cfe
+#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0cff
+#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0d00
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL0_SCL_HORZ_FILTER_INIT                                                                   0x0d01
+#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0d02
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL0_SCL_HORZ_FILTER_INIT_C                                                                 0x0d03
+#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0d04
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL0_SCL_VERT_FILTER_INIT                                                                   0x0d05
+#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT                                                               0x0d06
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0d07
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL0_SCL_VERT_FILTER_INIT_C                                                                 0x0d08
+#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0d09
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL0_SCL_BLACK_COLOR                                                                        0x0d0a
+#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL0_DSCL_UPDATE                                                                            0x0d0b
+#define regDSCL0_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL0_DSCL_AUTOCAL                                                                           0x0d0c
+#define regDSCL0_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0d0d
+#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0d0e
+#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL0_OTG_H_BLANK                                                                            0x0d0f
+#define regDSCL0_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL0_OTG_V_BLANK                                                                            0x0d10
+#define regDSCL0_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL0_RECOUT_START                                                                           0x0d11
+#define regDSCL0_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL0_RECOUT_SIZE                                                                            0x0d12
+#define regDSCL0_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL0_MPC_SIZE                                                                               0x0d13
+#define regDSCL0_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL0_LB_DATA_FORMAT                                                                         0x0d14
+#define regDSCL0_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL0_LB_MEMORY_CTRL                                                                         0x0d15
+#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL0_LB_V_COUNTER                                                                           0x0d16
+#define regDSCL0_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL0_DSCL_MEM_PWR_CTRL                                                                      0x0d17
+#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL0_DSCL_MEM_PWR_STATUS                                                                    0x0d18
+#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL0_OBUF_CONTROL                                                                           0x0d19
+#define regDSCL0_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL0_OBUF_MEM_PWR_CTRL                                                                      0x0d1a
+#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
+// base address: 0x0
+#define regCM0_CM_CONTROL                                                                               0x0d20
+#define regCM0_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM0_CM_POST_CSC_CONTROL                                                                      0x0d21
+#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C11_C12                                                                      0x0d22
+#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C13_C14                                                                      0x0d23
+#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C21_C22                                                                      0x0d24
+#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C23_C24                                                                      0x0d25
+#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C31_C32                                                                      0x0d26
+#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C33_C34                                                                      0x0d27
+#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_B_C11_C12                                                                    0x0d28
+#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C13_C14                                                                    0x0d29
+#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C21_C22                                                                    0x0d2a
+#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C23_C24                                                                    0x0d2b
+#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C31_C32                                                                    0x0d2c
+#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C33_C34                                                                    0x0d2d
+#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM0_CM_GAMUT_REMAP_CONTROL                                                                   0x0d2e
+#define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C11_C12                                                                   0x0d2f
+#define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C13_C14                                                                   0x0d30
+#define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C21_C22                                                                   0x0d31
+#define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C23_C24                                                                   0x0d32
+#define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C31_C32                                                                   0x0d33
+#define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C33_C34                                                                   0x0d34
+#define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0d35
+#define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0d36
+#define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0d37
+#define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0d38
+#define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0d39
+#define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0d3a
+#define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM0_CM_BIAS_CR_R                                                                             0x0d3b
+#define regCM0_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM0_CM_BIAS_Y_G_CB_B                                                                         0x0d3c
+#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM0_CM_GAMCOR_CONTROL                                                                        0x0d3d
+#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM0_CM_GAMCOR_LUT_INDEX                                                                      0x0d3e
+#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM0_CM_GAMCOR_LUT_DATA                                                                       0x0d3f
+#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM0_CM_GAMCOR_LUT_CONTROL                                                                    0x0d40
+#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0d41
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0d42
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0d43
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0d44
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0d45
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0d46
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0d47
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0d48
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0d49
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0d4a
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0d4b
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0d4c
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0d4d
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0d4e
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0d4f
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0d50
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0d51
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0d52
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0d53
+#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0d54
+#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0d55
+#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0d56
+#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0d57
+#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0d58
+#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0d59
+#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0d5a
+#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0d5b
+#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0d5c
+#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0d5d
+#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0d5e
+#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0d5f
+#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0d60
+#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0d61
+#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0d62
+#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0d63
+#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0d64
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0d65
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0d66
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0d67
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0d68
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0d69
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0d6a
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0d6b
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0d6c
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0d6d
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0d6e
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0d6f
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0d70
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0d71
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0d72
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0d73
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0d74
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0d75
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0d76
+#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0d77
+#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0d78
+#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0d79
+#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0d7a
+#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0d7b
+#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0d7c
+#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0d7d
+#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0d7e
+#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0d7f
+#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0d80
+#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0d81
+#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0d82
+#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0d83
+#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0d84
+#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0d85
+#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0d86
+#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM0_CM_HDR_MULT_COEF                                                                         0x0d87
+#define regCM0_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM0_CM_MEM_PWR_CTRL                                                                          0x0d88
+#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM0_CM_MEM_PWR_STATUS                                                                        0x0d89
+#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM0_CM_DEALPHA                                                                               0x0d8b
+#define regCM0_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM0_CM_COEF_FORMAT                                                                           0x0d8c
+#define regCM0_CM_COEF_FORMAT_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
+// base address: 0x0
+#define regDPP_TOP0_DPP_CONTROL                                                                         0x0cc5
+#define regDPP_TOP0_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP0_DPP_SOFT_RESET                                                                      0x0cc6
+#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP0_DPP_CRC_VAL_R_G                                                                     0x0cc7
+#define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP0_DPP_CRC_VAL_B_A                                                                     0x0cc8
+#define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP0_DPP_CRC_CTRL                                                                        0x0cc9
+#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP0_HOST_READ_CONTROL                                                                   0x0cca
+#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
+// base address: 0x5ac
+#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0e3a
+#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG1_FORMAT_CONTROL                                                                     0x0e3b
+#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_BIAS_R                                                                     0x0e3c
+#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_BIAS_G                                                                     0x0e3d
+#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_BIAS_B                                                                     0x0e3e
+#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_SCALE_R                                                                    0x0e3f
+#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG1_FCNV_FP_SCALE_G                                                                    0x0e40
+#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG1_FCNV_FP_SCALE_B                                                                    0x0e41
+#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG1_COLOR_KEYER_CONTROL                                                                0x0e42
+#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG1_COLOR_KEYER_ALPHA                                                                  0x0e43
+#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG1_COLOR_KEYER_RED                                                                    0x0e44
+#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG1_COLOR_KEYER_GREEN                                                                  0x0e45
+#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG1_COLOR_KEYER_BLUE                                                                   0x0e46
+#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG1_ALPHA_2BIT_LUT                                                                     0x0e48
+#define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG1_PRE_DEALPHA                                                                        0x0e49
+#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG1_PRE_CSC_MODE                                                                       0x0e4a
+#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG1_PRE_CSC_C11_C12                                                                    0x0e4b
+#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C13_C14                                                                    0x0e4c
+#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C21_C22                                                                    0x0e4d
+#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C23_C24                                                                    0x0e4e
+#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C31_C32                                                                    0x0e4f
+#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C33_C34                                                                    0x0e50
+#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_B_C11_C12                                                                  0x0e51
+#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C13_C14                                                                  0x0e52
+#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C21_C22                                                                  0x0e53
+#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C23_C24                                                                  0x0e54
+#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C31_C32                                                                  0x0e55
+#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C33_C34                                                                  0x0e56
+#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG1_CNVC_COEF_FORMAT                                                                   0x0e57
+#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG1_PRE_DEGAM                                                                          0x0e58
+#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG1_PRE_REALPHA                                                                        0x0e59
+#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
+// base address: 0x5ac
+#define regCNVC_CUR1_CURSOR0_CONTROL                                                                    0x0e5c
+#define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR1_CURSOR0_COLOR0                                                                     0x0e5d
+#define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR1_CURSOR0_COLOR1                                                                     0x0e5e
+#define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS                                                              0x0e5f
+#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
+// base address: 0x5ac
+#define regDSCL1_SCL_COEF_RAM_TAP_SELECT                                                                0x0e64
+#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL1_SCL_COEF_RAM_TAP_DATA                                                                  0x0e65
+#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL1_SCL_MODE                                                                               0x0e66
+#define regDSCL1_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL1_SCL_TAP_CONTROL                                                                        0x0e67
+#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL1_DSCL_CONTROL                                                                           0x0e68
+#define regDSCL1_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL1_DSCL_2TAP_CONTROL                                                                      0x0e69
+#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0e6a
+#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0e6b
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL1_SCL_HORZ_FILTER_INIT                                                                   0x0e6c
+#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0e6d
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL1_SCL_HORZ_FILTER_INIT_C                                                                 0x0e6e
+#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0e6f
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL1_SCL_VERT_FILTER_INIT                                                                   0x0e70
+#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT                                                               0x0e71
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0e72
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL1_SCL_VERT_FILTER_INIT_C                                                                 0x0e73
+#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0e74
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL1_SCL_BLACK_COLOR                                                                        0x0e75
+#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL1_DSCL_UPDATE                                                                            0x0e76
+#define regDSCL1_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL1_DSCL_AUTOCAL                                                                           0x0e77
+#define regDSCL1_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0e78
+#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0e79
+#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL1_OTG_H_BLANK                                                                            0x0e7a
+#define regDSCL1_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL1_OTG_V_BLANK                                                                            0x0e7b
+#define regDSCL1_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL1_RECOUT_START                                                                           0x0e7c
+#define regDSCL1_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL1_RECOUT_SIZE                                                                            0x0e7d
+#define regDSCL1_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL1_MPC_SIZE                                                                               0x0e7e
+#define regDSCL1_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL1_LB_DATA_FORMAT                                                                         0x0e7f
+#define regDSCL1_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL1_LB_MEMORY_CTRL                                                                         0x0e80
+#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL1_LB_V_COUNTER                                                                           0x0e81
+#define regDSCL1_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL1_DSCL_MEM_PWR_CTRL                                                                      0x0e82
+#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL1_DSCL_MEM_PWR_STATUS                                                                    0x0e83
+#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL1_OBUF_CONTROL                                                                           0x0e84
+#define regDSCL1_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL1_OBUF_MEM_PWR_CTRL                                                                      0x0e85
+#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
+// base address: 0x5ac
+#define regCM1_CM_CONTROL                                                                               0x0e8b
+#define regCM1_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM1_CM_POST_CSC_CONTROL                                                                      0x0e8c
+#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C11_C12                                                                      0x0e8d
+#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C13_C14                                                                      0x0e8e
+#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C21_C22                                                                      0x0e8f
+#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C23_C24                                                                      0x0e90
+#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C31_C32                                                                      0x0e91
+#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C33_C34                                                                      0x0e92
+#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_B_C11_C12                                                                    0x0e93
+#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C13_C14                                                                    0x0e94
+#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C21_C22                                                                    0x0e95
+#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C23_C24                                                                    0x0e96
+#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C31_C32                                                                    0x0e97
+#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C33_C34                                                                    0x0e98
+#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM1_CM_GAMUT_REMAP_CONTROL                                                                   0x0e99
+#define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C11_C12                                                                   0x0e9a
+#define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C13_C14                                                                   0x0e9b
+#define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C21_C22                                                                   0x0e9c
+#define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C23_C24                                                                   0x0e9d
+#define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C31_C32                                                                   0x0e9e
+#define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C33_C34                                                                   0x0e9f
+#define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0ea0
+#define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0ea1
+#define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0ea2
+#define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0ea3
+#define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0ea4
+#define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0ea5
+#define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM1_CM_BIAS_CR_R                                                                             0x0ea6
+#define regCM1_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM1_CM_BIAS_Y_G_CB_B                                                                         0x0ea7
+#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM1_CM_GAMCOR_CONTROL                                                                        0x0ea8
+#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM1_CM_GAMCOR_LUT_INDEX                                                                      0x0ea9
+#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM1_CM_GAMCOR_LUT_DATA                                                                       0x0eaa
+#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM1_CM_GAMCOR_LUT_CONTROL                                                                    0x0eab
+#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0eac
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0ead
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0eae
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0eaf
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0eb0
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0eb1
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0eb2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0eb3
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0eb4
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0eb5
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0eb6
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0eb7
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0eb8
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0eb9
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0eba
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0ebb
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0ebc
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0ebd
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0ebe
+#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0ebf
+#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0ec0
+#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0ec1
+#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0ec2
+#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0ec3
+#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0ec4
+#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0ec5
+#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0ec6
+#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0ec7
+#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0ec8
+#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0ec9
+#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0eca
+#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0ecb
+#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0ecc
+#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0ecd
+#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0ece
+#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0ecf
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0ed0
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0ed1
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0ed2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0ed3
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0ed4
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0ed5
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0ed6
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0ed7
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0ed8
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0ed9
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0eda
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0edb
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0edc
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0edd
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0ede
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0edf
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0ee0
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0ee1
+#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0ee2
+#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0ee3
+#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0ee4
+#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0ee5
+#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0ee6
+#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0ee7
+#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0ee8
+#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0ee9
+#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0eea
+#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0eeb
+#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0eec
+#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0eed
+#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0eee
+#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0eef
+#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0ef0
+#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0ef1
+#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM1_CM_HDR_MULT_COEF                                                                         0x0ef2
+#define regCM1_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM1_CM_MEM_PWR_CTRL                                                                          0x0ef3
+#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM1_CM_MEM_PWR_STATUS                                                                        0x0ef4
+#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM1_CM_DEALPHA                                                                               0x0ef6
+#define regCM1_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM1_CM_COEF_FORMAT                                                                           0x0ef7
+#define regCM1_CM_COEF_FORMAT_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
+// base address: 0x5ac
+#define regDPP_TOP1_DPP_CONTROL                                                                         0x0e30
+#define regDPP_TOP1_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP1_DPP_SOFT_RESET                                                                      0x0e31
+#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP1_DPP_CRC_VAL_R_G                                                                     0x0e32
+#define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP1_DPP_CRC_VAL_B_A                                                                     0x0e33
+#define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP1_DPP_CRC_CTRL                                                                        0x0e34
+#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP1_HOST_READ_CONTROL                                                                   0x0e35
+#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
+// base address: 0xb58
+#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0fa5
+#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG2_FORMAT_CONTROL                                                                     0x0fa6
+#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_BIAS_R                                                                     0x0fa7
+#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_BIAS_G                                                                     0x0fa8
+#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_BIAS_B                                                                     0x0fa9
+#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_SCALE_R                                                                    0x0faa
+#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG2_FCNV_FP_SCALE_G                                                                    0x0fab
+#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG2_FCNV_FP_SCALE_B                                                                    0x0fac
+#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG2_COLOR_KEYER_CONTROL                                                                0x0fad
+#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG2_COLOR_KEYER_ALPHA                                                                  0x0fae
+#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG2_COLOR_KEYER_RED                                                                    0x0faf
+#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG2_COLOR_KEYER_GREEN                                                                  0x0fb0
+#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG2_COLOR_KEYER_BLUE                                                                   0x0fb1
+#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG2_ALPHA_2BIT_LUT                                                                     0x0fb3
+#define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG2_PRE_DEALPHA                                                                        0x0fb4
+#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG2_PRE_CSC_MODE                                                                       0x0fb5
+#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG2_PRE_CSC_C11_C12                                                                    0x0fb6
+#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C13_C14                                                                    0x0fb7
+#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C21_C22                                                                    0x0fb8
+#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C23_C24                                                                    0x0fb9
+#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C31_C32                                                                    0x0fba
+#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C33_C34                                                                    0x0fbb
+#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_B_C11_C12                                                                  0x0fbc
+#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C13_C14                                                                  0x0fbd
+#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C21_C22                                                                  0x0fbe
+#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C23_C24                                                                  0x0fbf
+#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C31_C32                                                                  0x0fc0
+#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C33_C34                                                                  0x0fc1
+#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG2_CNVC_COEF_FORMAT                                                                   0x0fc2
+#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG2_PRE_DEGAM                                                                          0x0fc3
+#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG2_PRE_REALPHA                                                                        0x0fc4
+#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
+// base address: 0xb58
+#define regCNVC_CUR2_CURSOR0_CONTROL                                                                    0x0fc7
+#define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR2_CURSOR0_COLOR0                                                                     0x0fc8
+#define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR2_CURSOR0_COLOR1                                                                     0x0fc9
+#define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS                                                              0x0fca
+#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
+// base address: 0xb58
+#define regDSCL2_SCL_COEF_RAM_TAP_SELECT                                                                0x0fcf
+#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL2_SCL_COEF_RAM_TAP_DATA                                                                  0x0fd0
+#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL2_SCL_MODE                                                                               0x0fd1
+#define regDSCL2_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL2_SCL_TAP_CONTROL                                                                        0x0fd2
+#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL2_DSCL_CONTROL                                                                           0x0fd3
+#define regDSCL2_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL2_DSCL_2TAP_CONTROL                                                                      0x0fd4
+#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0fd5
+#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0fd6
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL2_SCL_HORZ_FILTER_INIT                                                                   0x0fd7
+#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0fd8
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL2_SCL_HORZ_FILTER_INIT_C                                                                 0x0fd9
+#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0fda
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL2_SCL_VERT_FILTER_INIT                                                                   0x0fdb
+#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT                                                               0x0fdc
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0fdd
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL2_SCL_VERT_FILTER_INIT_C                                                                 0x0fde
+#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0fdf
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL2_SCL_BLACK_COLOR                                                                        0x0fe0
+#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL2_DSCL_UPDATE                                                                            0x0fe1
+#define regDSCL2_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL2_DSCL_AUTOCAL                                                                           0x0fe2
+#define regDSCL2_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0fe3
+#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0fe4
+#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL2_OTG_H_BLANK                                                                            0x0fe5
+#define regDSCL2_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL2_OTG_V_BLANK                                                                            0x0fe6
+#define regDSCL2_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL2_RECOUT_START                                                                           0x0fe7
+#define regDSCL2_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL2_RECOUT_SIZE                                                                            0x0fe8
+#define regDSCL2_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL2_MPC_SIZE                                                                               0x0fe9
+#define regDSCL2_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL2_LB_DATA_FORMAT                                                                         0x0fea
+#define regDSCL2_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL2_LB_MEMORY_CTRL                                                                         0x0feb
+#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL2_LB_V_COUNTER                                                                           0x0fec
+#define regDSCL2_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL2_DSCL_MEM_PWR_CTRL                                                                      0x0fed
+#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL2_DSCL_MEM_PWR_STATUS                                                                    0x0fee
+#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL2_OBUF_CONTROL                                                                           0x0fef
+#define regDSCL2_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL2_OBUF_MEM_PWR_CTRL                                                                      0x0ff0
+#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
+// base address: 0xb58
+#define regCM2_CM_CONTROL                                                                               0x0ff6
+#define regCM2_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM2_CM_POST_CSC_CONTROL                                                                      0x0ff7
+#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C11_C12                                                                      0x0ff8
+#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C13_C14                                                                      0x0ff9
+#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C21_C22                                                                      0x0ffa
+#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C23_C24                                                                      0x0ffb
+#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C31_C32                                                                      0x0ffc
+#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C33_C34                                                                      0x0ffd
+#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_B_C11_C12                                                                    0x0ffe
+#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C13_C14                                                                    0x0fff
+#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C21_C22                                                                    0x1000
+#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C23_C24                                                                    0x1001
+#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C31_C32                                                                    0x1002
+#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C33_C34                                                                    0x1003
+#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM2_CM_GAMUT_REMAP_CONTROL                                                                   0x1004
+#define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C11_C12                                                                   0x1005
+#define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C13_C14                                                                   0x1006
+#define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C21_C22                                                                   0x1007
+#define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C23_C24                                                                   0x1008
+#define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C31_C32                                                                   0x1009
+#define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C33_C34                                                                   0x100a
+#define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_B_C11_C12                                                                 0x100b
+#define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C13_C14                                                                 0x100c
+#define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C21_C22                                                                 0x100d
+#define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C23_C24                                                                 0x100e
+#define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C31_C32                                                                 0x100f
+#define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C33_C34                                                                 0x1010
+#define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM2_CM_BIAS_CR_R                                                                             0x1011
+#define regCM2_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM2_CM_BIAS_Y_G_CB_B                                                                         0x1012
+#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM2_CM_GAMCOR_CONTROL                                                                        0x1013
+#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM2_CM_GAMCOR_LUT_INDEX                                                                      0x1014
+#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM2_CM_GAMCOR_LUT_DATA                                                                       0x1015
+#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM2_CM_GAMCOR_LUT_CONTROL                                                                    0x1016
+#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1017
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1018
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1019
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x101a
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x101b
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x101c
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x101d
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x101e
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x101f
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x1020
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x1021
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x1022
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x1023
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x1024
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1025
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1026
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1027
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1028
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1029
+#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_2_3                                                                0x102a
+#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_4_5                                                                0x102b
+#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_6_7                                                                0x102c
+#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_8_9                                                                0x102d
+#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_10_11                                                              0x102e
+#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_12_13                                                              0x102f
+#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_14_15                                                              0x1030
+#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_16_17                                                              0x1031
+#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_18_19                                                              0x1032
+#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_20_21                                                              0x1033
+#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_22_23                                                              0x1034
+#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_24_25                                                              0x1035
+#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_26_27                                                              0x1036
+#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_28_29                                                              0x1037
+#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_30_31                                                              0x1038
+#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_32_33                                                              0x1039
+#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x103a
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x103b
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x103c
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x103d
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x103e
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x103f
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x1040
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x1041
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x1042
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x1043
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x1044
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x1045
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x1046
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x1047
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x1048
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x1049
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x104a
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x104b
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMB_REGION_0_1                                                                0x104c
+#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_2_3                                                                0x104d
+#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_4_5                                                                0x104e
+#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_6_7                                                                0x104f
+#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_8_9                                                                0x1050
+#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_10_11                                                              0x1051
+#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_12_13                                                              0x1052
+#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_14_15                                                              0x1053
+#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_16_17                                                              0x1054
+#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_18_19                                                              0x1055
+#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_20_21                                                              0x1056
+#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_22_23                                                              0x1057
+#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_24_25                                                              0x1058
+#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_26_27                                                              0x1059
+#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_28_29                                                              0x105a
+#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_30_31                                                              0x105b
+#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_32_33                                                              0x105c
+#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM2_CM_HDR_MULT_COEF                                                                         0x105d
+#define regCM2_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM2_CM_MEM_PWR_CTRL                                                                          0x105e
+#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM2_CM_MEM_PWR_STATUS                                                                        0x105f
+#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM2_CM_DEALPHA                                                                               0x1061
+#define regCM2_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM2_CM_COEF_FORMAT                                                                           0x1062
+#define regCM2_CM_COEF_FORMAT_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
+// base address: 0xb58
+#define regDPP_TOP2_DPP_CONTROL                                                                         0x0f9b
+#define regDPP_TOP2_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP2_DPP_SOFT_RESET                                                                      0x0f9c
+#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP2_DPP_CRC_VAL_R_G                                                                     0x0f9d
+#define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP2_DPP_CRC_VAL_B_A                                                                     0x0f9e
+#define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP2_DPP_CRC_CTRL                                                                        0x0f9f
+#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP2_HOST_READ_CONTROL                                                                   0x0fa0
+#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
+// base address: 0x1104
+#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT                                                          0x1110
+#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG3_FORMAT_CONTROL                                                                     0x1111
+#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_BIAS_R                                                                     0x1112
+#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_BIAS_G                                                                     0x1113
+#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_BIAS_B                                                                     0x1114
+#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_SCALE_R                                                                    0x1115
+#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG3_FCNV_FP_SCALE_G                                                                    0x1116
+#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG3_FCNV_FP_SCALE_B                                                                    0x1117
+#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG3_COLOR_KEYER_CONTROL                                                                0x1118
+#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG3_COLOR_KEYER_ALPHA                                                                  0x1119
+#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG3_COLOR_KEYER_RED                                                                    0x111a
+#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG3_COLOR_KEYER_GREEN                                                                  0x111b
+#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG3_COLOR_KEYER_BLUE                                                                   0x111c
+#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG3_ALPHA_2BIT_LUT                                                                     0x111e
+#define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG3_PRE_DEALPHA                                                                        0x111f
+#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG3_PRE_CSC_MODE                                                                       0x1120
+#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG3_PRE_CSC_C11_C12                                                                    0x1121
+#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C13_C14                                                                    0x1122
+#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C21_C22                                                                    0x1123
+#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C23_C24                                                                    0x1124
+#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C31_C32                                                                    0x1125
+#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C33_C34                                                                    0x1126
+#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_B_C11_C12                                                                  0x1127
+#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C13_C14                                                                  0x1128
+#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C21_C22                                                                  0x1129
+#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C23_C24                                                                  0x112a
+#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C31_C32                                                                  0x112b
+#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C33_C34                                                                  0x112c
+#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG3_CNVC_COEF_FORMAT                                                                   0x112d
+#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG3_PRE_DEGAM                                                                          0x112e
+#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG3_PRE_REALPHA                                                                        0x112f
+#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
+// base address: 0x1104
+#define regCNVC_CUR3_CURSOR0_CONTROL                                                                    0x1132
+#define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR3_CURSOR0_COLOR0                                                                     0x1133
+#define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR3_CURSOR0_COLOR1                                                                     0x1134
+#define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS                                                              0x1135
+#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
+// base address: 0x1104
+#define regDSCL3_SCL_COEF_RAM_TAP_SELECT                                                                0x113a
+#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL3_SCL_COEF_RAM_TAP_DATA                                                                  0x113b
+#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL3_SCL_MODE                                                                               0x113c
+#define regDSCL3_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL3_SCL_TAP_CONTROL                                                                        0x113d
+#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL3_DSCL_CONTROL                                                                           0x113e
+#define regDSCL3_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL3_DSCL_2TAP_CONTROL                                                                      0x113f
+#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL                                                           0x1140
+#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x1141
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL3_SCL_HORZ_FILTER_INIT                                                                   0x1142
+#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x1143
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL3_SCL_HORZ_FILTER_INIT_C                                                                 0x1144
+#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO                                                            0x1145
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL3_SCL_VERT_FILTER_INIT                                                                   0x1146
+#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT                                                               0x1147
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x1148
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL3_SCL_VERT_FILTER_INIT_C                                                                 0x1149
+#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C                                                             0x114a
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL3_SCL_BLACK_COLOR                                                                        0x114b
+#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL3_DSCL_UPDATE                                                                            0x114c
+#define regDSCL3_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL3_DSCL_AUTOCAL                                                                           0x114d
+#define regDSCL3_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x114e
+#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x114f
+#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL3_OTG_H_BLANK                                                                            0x1150
+#define regDSCL3_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL3_OTG_V_BLANK                                                                            0x1151
+#define regDSCL3_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL3_RECOUT_START                                                                           0x1152
+#define regDSCL3_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL3_RECOUT_SIZE                                                                            0x1153
+#define regDSCL3_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL3_MPC_SIZE                                                                               0x1154
+#define regDSCL3_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL3_LB_DATA_FORMAT                                                                         0x1155
+#define regDSCL3_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL3_LB_MEMORY_CTRL                                                                         0x1156
+#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL3_LB_V_COUNTER                                                                           0x1157
+#define regDSCL3_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL3_DSCL_MEM_PWR_CTRL                                                                      0x1158
+#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL3_DSCL_MEM_PWR_STATUS                                                                    0x1159
+#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL3_OBUF_CONTROL                                                                           0x115a
+#define regDSCL3_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL3_OBUF_MEM_PWR_CTRL                                                                      0x115b
+#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
+// base address: 0x1104
+#define regCM3_CM_CONTROL                                                                               0x1161
+#define regCM3_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM3_CM_POST_CSC_CONTROL                                                                      0x1162
+#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C11_C12                                                                      0x1163
+#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C13_C14                                                                      0x1164
+#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C21_C22                                                                      0x1165
+#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C23_C24                                                                      0x1166
+#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C31_C32                                                                      0x1167
+#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C33_C34                                                                      0x1168
+#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_B_C11_C12                                                                    0x1169
+#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C13_C14                                                                    0x116a
+#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C21_C22                                                                    0x116b
+#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C23_C24                                                                    0x116c
+#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C31_C32                                                                    0x116d
+#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C33_C34                                                                    0x116e
+#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM3_CM_GAMUT_REMAP_CONTROL                                                                   0x116f
+#define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C11_C12                                                                   0x1170
+#define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C13_C14                                                                   0x1171
+#define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C21_C22                                                                   0x1172
+#define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C23_C24                                                                   0x1173
+#define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C31_C32                                                                   0x1174
+#define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C33_C34                                                                   0x1175
+#define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_B_C11_C12                                                                 0x1176
+#define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C13_C14                                                                 0x1177
+#define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C21_C22                                                                 0x1178
+#define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C23_C24                                                                 0x1179
+#define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C31_C32                                                                 0x117a
+#define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C33_C34                                                                 0x117b
+#define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM3_CM_BIAS_CR_R                                                                             0x117c
+#define regCM3_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM3_CM_BIAS_Y_G_CB_B                                                                         0x117d
+#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM3_CM_GAMCOR_CONTROL                                                                        0x117e
+#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM3_CM_GAMCOR_LUT_INDEX                                                                      0x117f
+#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM3_CM_GAMCOR_LUT_DATA                                                                       0x1180
+#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM3_CM_GAMCOR_LUT_CONTROL                                                                    0x1181
+#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1182
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1183
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1184
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x1185
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x1186
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x1187
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x1188
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x1189
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x118a
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x118b
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x118c
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x118d
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x118e
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x118f
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1190
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1191
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1192
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1193
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1194
+#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_2_3                                                                0x1195
+#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_4_5                                                                0x1196
+#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_6_7                                                                0x1197
+#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_8_9                                                                0x1198
+#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_10_11                                                              0x1199
+#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_12_13                                                              0x119a
+#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_14_15                                                              0x119b
+#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_16_17                                                              0x119c
+#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_18_19                                                              0x119d
+#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_20_21                                                              0x119e
+#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_22_23                                                              0x119f
+#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_24_25                                                              0x11a0
+#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_26_27                                                              0x11a1
+#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_28_29                                                              0x11a2
+#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_30_31                                                              0x11a3
+#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_32_33                                                              0x11a4
+#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x11a5
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x11a6
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x11a7
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x11a8
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x11a9
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x11aa
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x11ab
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x11ac
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x11ad
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x11ae
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x11af
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x11b0
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x11b1
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x11b2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x11b3
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x11b4
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x11b5
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x11b6
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMB_REGION_0_1                                                                0x11b7
+#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_2_3                                                                0x11b8
+#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_4_5                                                                0x11b9
+#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_6_7                                                                0x11ba
+#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_8_9                                                                0x11bb
+#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_10_11                                                              0x11bc
+#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_12_13                                                              0x11bd
+#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_14_15                                                              0x11be
+#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_16_17                                                              0x11bf
+#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_18_19                                                              0x11c0
+#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_20_21                                                              0x11c1
+#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_22_23                                                              0x11c2
+#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_24_25                                                              0x11c3
+#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_26_27                                                              0x11c4
+#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_28_29                                                              0x11c5
+#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_30_31                                                              0x11c6
+#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_32_33                                                              0x11c7
+#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM3_CM_HDR_MULT_COEF                                                                         0x11c8
+#define regCM3_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM3_CM_MEM_PWR_CTRL                                                                          0x11c9
+#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM3_CM_MEM_PWR_STATUS                                                                        0x11ca
+#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM3_CM_DEALPHA                                                                               0x11cc
+#define regCM3_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM3_CM_COEF_FORMAT                                                                           0x11cd
+#define regCM3_CM_COEF_FORMAT_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
+// base address: 0x1104
+#define regDPP_TOP3_DPP_CONTROL                                                                         0x1106
+#define regDPP_TOP3_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP3_DPP_SOFT_RESET                                                                      0x1107
+#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP3_DPP_CRC_VAL_R_G                                                                     0x1108
+#define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP3_DPP_CRC_VAL_B_A                                                                     0x1109
+#define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP3_DPP_CRC_CTRL                                                                        0x110a
+#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP3_HOST_READ_CONTROL                                                                   0x110b
+#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_mpc_mpcc0_dispdec
+// base address: 0x0
+#define regMPCC0_MPCC_TOP_SEL                                                                           0x0000
+#define regMPCC0_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_BOT_SEL                                                                           0x0001
+#define regMPCC0_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_OPP_ID                                                                            0x0002
+#define regMPCC0_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC0_MPCC_CONTROL                                                                           0x0003
+#define regMPCC0_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_SM_CONTROL                                                                        0x0004
+#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC0_MPCC_UPDATE_LOCK_SEL                                                                   0x0005
+#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC0_MPCC_TOP_GAIN                                                                          0x0006
+#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC0_MPCC_BOT_GAIN_INSIDE                                                                   0x0007
+#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0008
+#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0009
+#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
+#define regMPCC0_MPCC_BG_R_CR                                                                           0x000a
+#define regMPCC0_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_BG_G_Y                                                                            0x000b
+#define regMPCC0_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC0_MPCC_BG_B_CB                                                                           0x000c
+#define regMPCC0_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_MEM_PWR_CTRL                                                                      0x000d
+#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC0_MPCC_STATUS                                                                            0x000e
+#define regMPCC0_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpcc1_dispdec
+// base address: 0x54
+#define regMPCC1_MPCC_TOP_SEL                                                                           0x0015
+#define regMPCC1_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_BOT_SEL                                                                           0x0016
+#define regMPCC1_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_OPP_ID                                                                            0x0017
+#define regMPCC1_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC1_MPCC_CONTROL                                                                           0x0018
+#define regMPCC1_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_SM_CONTROL                                                                        0x0019
+#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC1_MPCC_UPDATE_LOCK_SEL                                                                   0x001a
+#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC1_MPCC_TOP_GAIN                                                                          0x001b
+#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC1_MPCC_BOT_GAIN_INSIDE                                                                   0x001c
+#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE                                                                  0x001d
+#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x001e
+#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
+#define regMPCC1_MPCC_BG_R_CR                                                                           0x001f
+#define regMPCC1_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_BG_G_Y                                                                            0x0020
+#define regMPCC1_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC1_MPCC_BG_B_CB                                                                           0x0021
+#define regMPCC1_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_MEM_PWR_CTRL                                                                      0x0022
+#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC1_MPCC_STATUS                                                                            0x0023
+#define regMPCC1_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpcc2_dispdec
+// base address: 0xa8
+#define regMPCC2_MPCC_TOP_SEL                                                                           0x002a
+#define regMPCC2_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_BOT_SEL                                                                           0x002b
+#define regMPCC2_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_OPP_ID                                                                            0x002c
+#define regMPCC2_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC2_MPCC_CONTROL                                                                           0x002d
+#define regMPCC2_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_SM_CONTROL                                                                        0x002e
+#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC2_MPCC_UPDATE_LOCK_SEL                                                                   0x002f
+#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC2_MPCC_TOP_GAIN                                                                          0x0030
+#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC2_MPCC_BOT_GAIN_INSIDE                                                                   0x0031
+#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0032
+#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0033
+#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
+#define regMPCC2_MPCC_BG_R_CR                                                                           0x0034
+#define regMPCC2_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_BG_G_Y                                                                            0x0035
+#define regMPCC2_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC2_MPCC_BG_B_CB                                                                           0x0036
+#define regMPCC2_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_MEM_PWR_CTRL                                                                      0x0037
+#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC2_MPCC_STATUS                                                                            0x0038
+#define regMPCC2_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpcc3_dispdec
+// base address: 0xfc
+#define regMPCC3_MPCC_TOP_SEL                                                                           0x003f
+#define regMPCC3_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_BOT_SEL                                                                           0x0040
+#define regMPCC3_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_OPP_ID                                                                            0x0041
+#define regMPCC3_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC3_MPCC_CONTROL                                                                           0x0042
+#define regMPCC3_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_SM_CONTROL                                                                        0x0043
+#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC3_MPCC_UPDATE_LOCK_SEL                                                                   0x0044
+#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC3_MPCC_TOP_GAIN                                                                          0x0045
+#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC3_MPCC_BOT_GAIN_INSIDE                                                                   0x0046
+#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0047
+#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0048
+#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
+#define regMPCC3_MPCC_BG_R_CR                                                                           0x0049
+#define regMPCC3_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_BG_G_Y                                                                            0x004a
+#define regMPCC3_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC3_MPCC_BG_B_CB                                                                           0x004b
+#define regMPCC3_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_MEM_PWR_CTRL                                                                      0x004c
+#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC3_MPCC_STATUS                                                                            0x004d
+#define regMPCC3_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
+// base address: 0x0
+#define regMPC_CLOCK_CONTROL                                                                            0x0398
+#define regMPC_CLOCK_CONTROL_BASE_IDX                                                                   3
+#define regMPC_SOFT_RESET                                                                               0x0399
+#define regMPC_SOFT_RESET_BASE_IDX                                                                      3
+#define regMPC_CRC_CTRL                                                                                 0x039a
+#define regMPC_CRC_CTRL_BASE_IDX                                                                        3
+#define regMPC_CRC_SEL_CONTROL                                                                          0x039b
+#define regMPC_CRC_SEL_CONTROL_BASE_IDX                                                                 3
+#define regMPC_CRC_RESULT_AR                                                                            0x039c
+#define regMPC_CRC_RESULT_AR_BASE_IDX                                                                   3
+#define regMPC_CRC_RESULT_GB                                                                            0x039d
+#define regMPC_CRC_RESULT_GB_BASE_IDX                                                                   3
+#define regMPC_CRC_RESULT_C                                                                             0x039e
+#define regMPC_CRC_RESULT_C_BASE_IDX                                                                    3
+#define regMPC_BYPASS_BG_AR                                                                             0x03a2
+#define regMPC_BYPASS_BG_AR_BASE_IDX                                                                    3
+#define regMPC_BYPASS_BG_GB                                                                             0x03a3
+#define regMPC_BYPASS_BG_GB_BASE_IDX                                                                    3
+#define regMPC_HOST_READ_CONTROL                                                                        0x03a4
+#define regMPC_HOST_READ_CONTROL_BASE_IDX                                                               3
+#define regMPC_DPP_PENDING_STATUS                                                                       0x03a5
+#define regMPC_DPP_PENDING_STATUS_BASE_IDX                                                              3
+#define regMPC_PENDING_STATUS_MISC                                                                      0x03a6
+#define regMPC_PENDING_STATUS_MISC_BASE_IDX                                                             3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET0                                                                0x03a7
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET0                                                                    0x03a8
+#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET0                                                                        0x03a9
+#define regADR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET0                                                                        0x03aa
+#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET0                                                                        0x03ab
+#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET1                                                                0x03ac
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET1                                                                    0x03ad
+#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET1                                                                        0x03ae
+#define regADR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET1                                                                        0x03af
+#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET1                                                                        0x03b0
+#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET2                                                                0x03b1
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET2                                                                    0x03b2
+#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET2                                                                        0x03b3
+#define regADR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET2                                                                        0x03b4
+#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET2                                                                        0x03b5
+#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET3                                                                0x03b6
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET3                                                                    0x03b7
+#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET3                                                                        0x03b8
+#define regADR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET3                                                                        0x03b9
+#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET3                                                                        0x03ba
+#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
+#define regMPC_DWB0_MUX                                                                                 0x03c6
+#define regMPC_DWB0_MUX_BASE_IDX                                                                        3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
+// base address: 0x0
+#define regMPCC_OGAM0_MPCC_OGAM_CONTROL                                                                 0x00a8
+#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX                                                               0x00a9
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA                                                                0x00aa
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL                                                             0x00ab
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x00ac
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x00ad
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x00ae
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x00af
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x00b0
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x00b1
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x00b2
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x00b3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x00b4
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x00b5
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x00b6
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x00b7
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x00b8
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x00b9
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x00ba
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B                                                           0x00bb
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G                                                           0x00bc
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R                                                           0x00bd
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1                                                         0x00be
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3                                                         0x00bf
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5                                                         0x00c0
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7                                                         0x00c1
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9                                                         0x00c2
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11                                                       0x00c3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13                                                       0x00c4
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15                                                       0x00c5
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17                                                       0x00c6
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19                                                       0x00c7
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21                                                       0x00c8
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23                                                       0x00c9
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25                                                       0x00ca
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27                                                       0x00cb
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29                                                       0x00cc
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31                                                       0x00cd
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33                                                       0x00ce
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x00cf
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x00d0
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x00d1
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x00d2
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x00d3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x00d4
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x00d5
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x00d6
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x00d7
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x00d8
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x00d9
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x00da
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x00db
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x00dc
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x00dd
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B                                                           0x00de
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G                                                           0x00df
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R                                                           0x00e0
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1                                                         0x00e1
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3                                                         0x00e2
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5                                                         0x00e3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7                                                         0x00e4
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9                                                         0x00e5
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11                                                       0x00e6
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13                                                       0x00e7
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15                                                       0x00e8
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17                                                       0x00e9
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19                                                       0x00ea
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21                                                       0x00eb
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23                                                       0x00ec
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25                                                       0x00ed
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27                                                       0x00ee
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29                                                       0x00ef
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31                                                       0x00f0
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33                                                       0x00f1
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x00f2
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE                                                             0x00f3
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A                                                         0x00f4
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A                                                         0x00f5
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A                                                         0x00f6
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A                                                         0x00f7
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A                                                         0x00f8
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A                                                         0x00f9
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B                                                         0x00fa
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B                                                         0x00fb
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B                                                         0x00fc
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B                                                         0x00fd
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B                                                         0x00fe
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B                                                         0x00ff
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
+// base address: 0x178
+#define regMPCC_OGAM1_MPCC_OGAM_CONTROL                                                                 0x0106
+#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX                                                               0x0107
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA                                                                0x0108
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL                                                             0x0109
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x010a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x010b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x010c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x010d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x010e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x010f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x0110
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x0111
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x0112
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x0113
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x0114
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x0115
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0116
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0117
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0118
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0119
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G                                                           0x011a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R                                                           0x011b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1                                                         0x011c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3                                                         0x011d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5                                                         0x011e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7                                                         0x011f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9                                                         0x0120
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11                                                       0x0121
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13                                                       0x0122
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15                                                       0x0123
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17                                                       0x0124
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19                                                       0x0125
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0126
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0127
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0128
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0129
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29                                                       0x012a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31                                                       0x012b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33                                                       0x012c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x012d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x012e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x012f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x0130
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x0131
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x0132
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x0133
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x0134
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x0135
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0136
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0137
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0138
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0139
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x013a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x013b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B                                                           0x013c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G                                                           0x013d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R                                                           0x013e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1                                                         0x013f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3                                                         0x0140
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5                                                         0x0141
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7                                                         0x0142
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9                                                         0x0143
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11                                                       0x0144
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13                                                       0x0145
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0146
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0147
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0148
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0149
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23                                                       0x014a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25                                                       0x014b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27                                                       0x014c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29                                                       0x014d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31                                                       0x014e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33                                                       0x014f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x0150
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE                                                             0x0151
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A                                                         0x0152
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A                                                         0x0153
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A                                                         0x0154
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A                                                         0x0155
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0156
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0157
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0158
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0159
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B                                                         0x015a
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B                                                         0x015b
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B                                                         0x015c
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B                                                         0x015d
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
+// base address: 0x2f0
+#define regMPCC_OGAM2_MPCC_OGAM_CONTROL                                                                 0x0164
+#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX                                                               0x0165
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA                                                                0x0166
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL                                                             0x0167
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0168
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0169
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x016a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x016b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x016c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x016d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x016e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x016f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x0170
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x0171
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x0172
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x0173
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0174
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0175
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0176
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0177
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0178
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0179
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1                                                         0x017a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3                                                         0x017b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5                                                         0x017c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7                                                         0x017d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9                                                         0x017e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11                                                       0x017f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13                                                       0x0180
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15                                                       0x0181
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17                                                       0x0182
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19                                                       0x0183
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0184
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0185
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0186
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0187
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29                                                       0x0188
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31                                                       0x0189
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33                                                       0x018a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x018b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x018c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x018d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x018e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x018f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x0190
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x0191
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x0192
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x0193
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0194
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0195
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0196
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0197
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x0198
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x0199
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B                                                           0x019a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G                                                           0x019b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R                                                           0x019c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1                                                         0x019d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3                                                         0x019e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5                                                         0x019f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01a0
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01a1
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11                                                       0x01a2
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13                                                       0x01a3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15                                                       0x01a4
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17                                                       0x01a5
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19                                                       0x01a6
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21                                                       0x01a7
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23                                                       0x01a8
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25                                                       0x01a9
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27                                                       0x01aa
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29                                                       0x01ab
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31                                                       0x01ac
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33                                                       0x01ad
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x01ae
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE                                                             0x01af
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A                                                         0x01b0
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A                                                         0x01b1
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A                                                         0x01b2
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A                                                         0x01b3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A                                                         0x01b4
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A                                                         0x01b5
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B                                                         0x01b6
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B                                                         0x01b7
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B                                                         0x01b8
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B                                                         0x01b9
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B                                                         0x01ba
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B                                                         0x01bb
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
+// base address: 0x468
+#define regMPCC_OGAM3_MPCC_OGAM_CONTROL                                                                 0x01c2
+#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX                                                               0x01c3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA                                                                0x01c4
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL                                                             0x01c5
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x01c6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x01c7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x01c8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x01c9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x01ca
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x01cb
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x01cc
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x01cd
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x01ce
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x01cf
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x01d0
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x01d1
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x01d2
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x01d3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x01d4
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B                                                           0x01d5
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G                                                           0x01d6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R                                                           0x01d7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1                                                         0x01d8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3                                                         0x01d9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5                                                         0x01da
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7                                                         0x01db
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9                                                         0x01dc
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11                                                       0x01dd
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13                                                       0x01de
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15                                                       0x01df
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17                                                       0x01e0
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19                                                       0x01e1
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21                                                       0x01e2
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23                                                       0x01e3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25                                                       0x01e4
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27                                                       0x01e5
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29                                                       0x01e6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31                                                       0x01e7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33                                                       0x01e8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x01e9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x01ea
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x01eb
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x01ec
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x01ed
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x01ee
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x01ef
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x01f0
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x01f1
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x01f2
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x01f3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x01f4
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x01f5
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x01f6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x01f7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B                                                           0x01f8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G                                                           0x01f9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R                                                           0x01fa
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1                                                         0x01fb
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3                                                         0x01fc
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5                                                         0x01fd
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01fe
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01ff
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11                                                       0x0200
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13                                                       0x0201
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0202
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0203
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0204
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0205
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23                                                       0x0206
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25                                                       0x0207
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0208
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0209
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31                                                       0x020a
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33                                                       0x020b
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x020c
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE                                                             0x020d
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A                                                         0x020e
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A                                                         0x020f
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A                                                         0x0210
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A                                                         0x0211
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0212
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0213
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0214
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0215
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B                                                         0x0216
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B                                                         0x0217
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B                                                         0x0218
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B                                                         0x0219
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpcc_mcm0_dispdec
+// base address: 0x0
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL                                                            0x0453
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0454
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0455
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0456
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R                                                            0x0457
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0458
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0459
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA                                                           0x045a
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x045b
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x045c
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x045d
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x045e
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x045f
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0460
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0461
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0462
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0463
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0464
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0465
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0466
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0467
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0468
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0469
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x046a
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x046b
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x046c
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x046d
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x046e
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x046f
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0470
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0471
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0472
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0473
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0474
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0475
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0476
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0477
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0478
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0479
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x047a
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x047b
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x047c
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x047d
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x047e
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x047f
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0480
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0481
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0482
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0483
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0484
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0485
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0486
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0487
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0488
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0489
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE                                                                0x048a
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX                                                               0x048b
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA                                                                0x048c
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x048d
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x048e
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x048f
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0490
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0491
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0492
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL                                                             0x0493
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0494
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0495
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0496
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0497
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0498
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0499
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x049a
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x049b
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x049c
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x049d
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x049e
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x049f
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x04a0
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x04a1
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x04a2
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x04a3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x04a4
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x04a5
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x04a6
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x04a7
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x04a8
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x04a9
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x04aa
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x04ab
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x04ac
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x04ad
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x04ae
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x04af
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x04b0
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x04b1
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x04b2
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x04b3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x04b4
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x04b5
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x04b6
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x04b7
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x04b8
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x04b9
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x04ba
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x04bb
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x04bc
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x04bd
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x04be
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x04bf
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x04c0
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x04c1
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x04c2
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x04c3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x04c4
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x04c5
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x04c6
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x04c7
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x04c8
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x04c9
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x04ca
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x04cb
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x04cc
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x04cd
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x04ce
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x04cf
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x04d0
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x04d1
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x04d2
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x04d3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x04d4
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x04d5
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x04d6
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x04d7
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x04d8
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x04d9
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x04da
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x04db
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x04dc
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL                                                              0x04dd
+#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3
+
+
+// addressBlock: dce_dc_mpc_mpcc_mcm1_dispdec
+// base address: 0x240
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL                                                            0x04e3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R                                                           0x04e4
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G                                                           0x04e5
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B                                                           0x04e6
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R                                                            0x04e7
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x04e8
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x04e9
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA                                                           0x04ea
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x04eb
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x04ec
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x04ed
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x04ee
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x04ef
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x04f0
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x04f1
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x04f2
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x04f3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x04f4
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x04f5
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x04f6
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x04f7
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x04f8
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x04f9
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x04fa
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x04fb
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x04fc
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x04fd
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x04fe
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x04ff
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0500
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0501
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0502
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0503
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0504
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0505
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0506
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0507
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0508
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0509
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x050a
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x050b
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x050c
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x050d
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x050e
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x050f
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0510
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0511
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0512
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0513
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0514
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0515
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0516
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0517
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0518
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0519
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE                                                                0x051a
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX                                                               0x051b
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA                                                                0x051c
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x051d
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x051e
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x051f
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0520
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0521
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0522
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL                                                             0x0523
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0524
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0525
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0526
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0527
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0528
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0529
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x052a
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x052b
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x052c
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x052d
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x052e
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x052f
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x0530
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x0531
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x0532
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x0533
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x0534
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x0535
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x0536
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x0537
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x0538
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x0539
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x053a
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x053b
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x053c
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x053d
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x053e
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x053f
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x0540
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x0541
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x0542
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x0543
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x0544
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x0545
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x0546
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x0547
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x0548
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x0549
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x054a
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x054b
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x054c
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x054d
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x054e
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x054f
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x0550
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x0551
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x0552
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x0553
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x0554
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x0555
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x0556
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x0557
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x0558
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x0559
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x055a
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x055b
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x055c
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x055d
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x055e
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x055f
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x0560
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x0561
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x0562
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x0563
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x0564
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x0565
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x0566
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x0567
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x0568
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x0569
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x056a
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x056b
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x056c
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL                                                              0x056d
+#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3
+
+
+// addressBlock: dce_dc_mpc_mpcc_mcm2_dispdec
+// base address: 0x480
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL                                                            0x0573
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0574
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0575
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0576
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R                                                            0x0577
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0578
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0579
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA                                                           0x057a
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x057b
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x057c
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x057d
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x057e
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x057f
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0580
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0581
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0582
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0583
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0584
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0585
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0586
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0587
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0588
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0589
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x058a
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x058b
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x058c
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x058d
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x058e
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x058f
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0590
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0591
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0592
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0593
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0594
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0595
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0596
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0597
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0598
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0599
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x059a
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x059b
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x059c
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x059d
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x059e
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x059f
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x05a0
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x05a1
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x05a2
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x05a3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x05a4
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x05a5
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x05a6
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x05a7
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x05a8
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x05a9
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE                                                                0x05aa
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX                                                               0x05ab
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA                                                                0x05ac
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x05ad
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x05ae
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x05af
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x05b0
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x05b1
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x05b2
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL                                                             0x05b3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x05b4
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA                                                            0x05b5
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x05b6
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x05b7
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x05b8
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x05b9
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x05ba
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x05bb
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x05bc
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x05bd
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x05be
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x05bf
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x05c0
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x05c1
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x05c2
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x05c3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x05c4
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x05c5
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x05c6
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x05c7
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x05c8
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x05c9
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x05ca
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x05cb
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x05cc
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x05cd
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x05ce
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x05cf
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x05d0
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x05d1
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x05d2
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x05d3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x05d4
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x05d5
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x05d6
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x05d7
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x05d8
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x05d9
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x05da
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x05db
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x05dc
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x05dd
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x05de
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x05df
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x05e0
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x05e1
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x05e2
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x05e3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x05e4
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x05e5
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x05e6
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x05e7
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x05e8
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x05e9
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x05ea
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x05eb
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x05ec
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x05ed
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x05ee
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x05ef
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x05f0
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x05f1
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x05f2
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x05f3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x05f4
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x05f5
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x05f6
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x05f7
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x05f8
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x05f9
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x05fa
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x05fb
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x05fc
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL                                                              0x05fd
+#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3
+
+
+// addressBlock: dce_dc_mpc_mpcc_mcm3_dispdec
+// base address: 0x6c0
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL                                                            0x0603
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0604
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0605
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0606
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R                                                            0x0607
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0608
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0609
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA                                                           0x060a
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x060b
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x060c
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x060d
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x060e
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x060f
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0610
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0611
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0612
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0613
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0614
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0615
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0616
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0617
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0618
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0619
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x061a
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x061b
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x061c
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x061d
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x061e
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x061f
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0620
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0621
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0622
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0623
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0624
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0625
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0626
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0627
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0628
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0629
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x062a
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x062b
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x062c
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x062d
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x062e
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x062f
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0630
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0631
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0632
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0633
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0634
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0635
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0636
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0637
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0638
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0639
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE                                                                0x063a
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX                                                               0x063b
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA                                                                0x063c
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x063d
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x063e
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x063f
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0640
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0641
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0642
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL                                                             0x0643
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0644
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0645
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0646
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0647
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0648
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0649
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x064a
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x064b
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x064c
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x064d
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x064e
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x064f
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x0650
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x0651
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x0652
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x0653
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x0654
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x0655
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x0656
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x0657
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x0658
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x0659
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x065a
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x065b
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x065c
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x065d
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x065e
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x065f
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x0660
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x0661
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x0662
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x0663
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x0664
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x0665
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x0666
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x0667
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x0668
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x0669
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x066a
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x066b
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x066c
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x066d
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x066e
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x066f
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x0670
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x0671
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x0672
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x0673
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x0674
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x0675
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x0676
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x0677
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x0678
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x0679
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x067a
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x067b
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x067c
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x067d
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x067e
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x067f
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x0680
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x0681
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x0682
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x0683
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x0684
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x0685
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x0686
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x0687
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x0688
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x0689
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x068a
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x068b
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x068c
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL                                                              0x068d
+#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3
+
+
+// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
+// base address: 0x0
+#define regMPC_OUT0_MUX                                                                                 0x03d8
+#define regMPC_OUT0_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT0_DENORM_CONTROL                                                                      0x03d9
+#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT0_DENORM_CLAMP_G_Y                                                                    0x03da
+#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT0_DENORM_CLAMP_B_CB                                                                   0x03db
+#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT1_MUX                                                                                 0x03dc
+#define regMPC_OUT1_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT1_DENORM_CONTROL                                                                      0x03dd
+#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT1_DENORM_CLAMP_G_Y                                                                    0x03de
+#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT1_DENORM_CLAMP_B_CB                                                                   0x03df
+#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT2_MUX                                                                                 0x03e0
+#define regMPC_OUT2_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT2_DENORM_CONTROL                                                                      0x03e1
+#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT2_DENORM_CLAMP_G_Y                                                                    0x03e2
+#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT2_DENORM_CLAMP_B_CB                                                                   0x03e3
+#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT3_MUX                                                                                 0x03e4
+#define regMPC_OUT3_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT3_DENORM_CONTROL                                                                      0x03e5
+#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT3_DENORM_CLAMP_G_Y                                                                    0x03e6
+#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT3_DENORM_CLAMP_B_CB                                                                   0x03e7
+#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT_CSC_COEF_FORMAT                                                                      0x03f0
+#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX                                                             3
+#define regMPC_OUT0_CSC_MODE                                                                            0x03f1
+#define regMPC_OUT0_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT0_CSC_C11_C12_A                                                                       0x03f2
+#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C13_C14_A                                                                       0x03f3
+#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C21_C22_A                                                                       0x03f4
+#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C23_C24_A                                                                       0x03f5
+#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C31_C32_A                                                                       0x03f6
+#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C33_C34_A                                                                       0x03f7
+#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C11_C12_B                                                                       0x03f8
+#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C13_C14_B                                                                       0x03f9
+#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C21_C22_B                                                                       0x03fa
+#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C23_C24_B                                                                       0x03fb
+#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C31_C32_B                                                                       0x03fc
+#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C33_C34_B                                                                       0x03fd
+#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_MODE                                                                            0x03fe
+#define regMPC_OUT1_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT1_CSC_C11_C12_A                                                                       0x03ff
+#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C13_C14_A                                                                       0x0400
+#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C21_C22_A                                                                       0x0401
+#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C23_C24_A                                                                       0x0402
+#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C31_C32_A                                                                       0x0403
+#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C33_C34_A                                                                       0x0404
+#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C11_C12_B                                                                       0x0405
+#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C13_C14_B                                                                       0x0406
+#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C21_C22_B                                                                       0x0407
+#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C23_C24_B                                                                       0x0408
+#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C31_C32_B                                                                       0x0409
+#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C33_C34_B                                                                       0x040a
+#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_MODE                                                                            0x040b
+#define regMPC_OUT2_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT2_CSC_C11_C12_A                                                                       0x040c
+#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C13_C14_A                                                                       0x040d
+#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C21_C22_A                                                                       0x040e
+#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C23_C24_A                                                                       0x040f
+#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C31_C32_A                                                                       0x0410
+#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C33_C34_A                                                                       0x0411
+#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C11_C12_B                                                                       0x0412
+#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C13_C14_B                                                                       0x0413
+#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C21_C22_B                                                                       0x0414
+#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C23_C24_B                                                                       0x0415
+#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C31_C32_B                                                                       0x0416
+#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C33_C34_B                                                                       0x0417
+#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_MODE                                                                            0x0418
+#define regMPC_OUT3_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT3_CSC_C11_C12_A                                                                       0x0419
+#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C13_C14_A                                                                       0x041a
+#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C21_C22_A                                                                       0x041b
+#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C23_C24_A                                                                       0x041c
+#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C31_C32_A                                                                       0x041d
+#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C33_C34_A                                                                       0x041e
+#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C11_C12_B                                                                       0x041f
+#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C13_C14_B                                                                       0x0420
+#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C21_C22_B                                                                       0x0421
+#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C23_C24_B                                                                       0x0422
+#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C31_C32_B                                                                       0x0423
+#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C33_C34_B                                                                       0x0424
+#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX                                                              3
+
+
+// addressBlock: dce_dc_opp_abm0_dispdec
+// base address: 0x0
+#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0e7a
+#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM0_BL1_PWM_USER_LEVEL                                                                      0x0e7b
+#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM0_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0e7c
+#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0e7d
+#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0e7e
+#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0e7f
+#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM0_BL1_PWM_ABM_CNTL                                                                        0x0e80
+#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0e81
+#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM0_BL1_PWM_GRP2_REG_LOCK                                                                   0x0e82
+#define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM0_DC_ABM1_CNTL                                                                            0x0e83
+#define regABM0_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM0_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0e84
+#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0e85
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0e86
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0e87
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0e88
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0e89
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_THRES_12                                                                    0x0e8a
+#define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_ACE_THRES_34                                                                    0x0e8b
+#define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_ACE_CNTL_MISC                                                                   0x0e8c
+#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0e8e
+#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM0_DC_ABM1_HG_MISC_CTRL                                                                    0x0e8f
+#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0e90
+#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0e91
+#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0e92
+#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM0_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0e93
+#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0e94
+#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0e95
+#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0e96
+#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM0_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0e97
+#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0e98
+#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0e99
+#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0e9a
+#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0e9b
+#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0e9c
+#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0e9d
+#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM0_DC_ABM1_HG_RESULT_1                                                                     0x0e9e
+#define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_2                                                                     0x0e9f
+#define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_3                                                                     0x0ea0
+#define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_4                                                                     0x0ea1
+#define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_5                                                                     0x0ea2
+#define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_6                                                                     0x0ea3
+#define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_7                                                                     0x0ea4
+#define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_8                                                                     0x0ea5
+#define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_9                                                                     0x0ea6
+#define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_10                                                                    0x0ea7
+#define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_11                                                                    0x0ea8
+#define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_12                                                                    0x0ea9
+#define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_13                                                                    0x0eaa
+#define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_14                                                                    0x0eab
+#define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_15                                                                    0x0eac
+#define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_16                                                                    0x0ead
+#define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_17                                                                    0x0eae
+#define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_18                                                                    0x0eaf
+#define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_19                                                                    0x0eb0
+#define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_20                                                                    0x0eb1
+#define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_21                                                                    0x0eb2
+#define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_22                                                                    0x0eb3
+#define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_23                                                                    0x0eb4
+#define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_24                                                                    0x0eb5
+#define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_BL_MASTER_LOCK                                                                  0x0eb6
+#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_abm1_dispdec
+// base address: 0x104
+#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0ebb
+#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM1_BL1_PWM_USER_LEVEL                                                                      0x0ebc
+#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM1_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0ebd
+#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0ebe
+#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0ebf
+#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0ec0
+#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM1_BL1_PWM_ABM_CNTL                                                                        0x0ec1
+#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0ec2
+#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM1_BL1_PWM_GRP2_REG_LOCK                                                                   0x0ec3
+#define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM1_DC_ABM1_CNTL                                                                            0x0ec4
+#define regABM1_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM1_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0ec5
+#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0ec6
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0ec7
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0ec8
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0ec9
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0eca
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_THRES_12                                                                    0x0ecb
+#define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_ACE_THRES_34                                                                    0x0ecc
+#define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_ACE_CNTL_MISC                                                                   0x0ecd
+#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0ecf
+#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM1_DC_ABM1_HG_MISC_CTRL                                                                    0x0ed0
+#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0ed1
+#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0ed2
+#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0ed3
+#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM1_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0ed4
+#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0ed5
+#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0ed6
+#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0ed7
+#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM1_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0ed8
+#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0ed9
+#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0eda
+#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0edb
+#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0edc
+#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0edd
+#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0ede
+#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM1_DC_ABM1_HG_RESULT_1                                                                     0x0edf
+#define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_2                                                                     0x0ee0
+#define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_3                                                                     0x0ee1
+#define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_4                                                                     0x0ee2
+#define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_5                                                                     0x0ee3
+#define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_6                                                                     0x0ee4
+#define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_7                                                                     0x0ee5
+#define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_8                                                                     0x0ee6
+#define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_9                                                                     0x0ee7
+#define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_10                                                                    0x0ee8
+#define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_11                                                                    0x0ee9
+#define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_12                                                                    0x0eea
+#define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_13                                                                    0x0eeb
+#define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_14                                                                    0x0eec
+#define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_15                                                                    0x0eed
+#define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_16                                                                    0x0eee
+#define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_17                                                                    0x0eef
+#define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_18                                                                    0x0ef0
+#define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_19                                                                    0x0ef1
+#define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_20                                                                    0x0ef2
+#define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_21                                                                    0x0ef3
+#define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_22                                                                    0x0ef4
+#define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_23                                                                    0x0ef5
+#define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_24                                                                    0x0ef6
+#define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_BL_MASTER_LOCK                                                                  0x0ef7
+#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_abm2_dispdec
+// base address: 0x208
+#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0efc
+#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM2_BL1_PWM_USER_LEVEL                                                                      0x0efd
+#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM2_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0efe
+#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0eff
+#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f00
+#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f01
+#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM2_BL1_PWM_ABM_CNTL                                                                        0x0f02
+#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f03
+#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM2_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f04
+#define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM2_DC_ABM1_CNTL                                                                            0x0f05
+#define regABM2_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM2_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f06
+#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0f07
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0f08
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0f09
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0f0a
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0f0b
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_THRES_12                                                                    0x0f0c
+#define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_ACE_THRES_34                                                                    0x0f0d
+#define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f0e
+#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f10
+#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM2_DC_ABM1_HG_MISC_CTRL                                                                    0x0f11
+#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f12
+#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f13
+#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f14
+#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM2_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f15
+#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f16
+#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f17
+#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f18
+#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM2_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f19
+#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f1a
+#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f1b
+#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f1c
+#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f1d
+#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f1e
+#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f1f
+#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM2_DC_ABM1_HG_RESULT_1                                                                     0x0f20
+#define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_2                                                                     0x0f21
+#define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_3                                                                     0x0f22
+#define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_4                                                                     0x0f23
+#define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_5                                                                     0x0f24
+#define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_6                                                                     0x0f25
+#define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_7                                                                     0x0f26
+#define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_8                                                                     0x0f27
+#define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_9                                                                     0x0f28
+#define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_10                                                                    0x0f29
+#define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_11                                                                    0x0f2a
+#define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_12                                                                    0x0f2b
+#define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_13                                                                    0x0f2c
+#define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_14                                                                    0x0f2d
+#define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_15                                                                    0x0f2e
+#define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_16                                                                    0x0f2f
+#define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_17                                                                    0x0f30
+#define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_18                                                                    0x0f31
+#define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_19                                                                    0x0f32
+#define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_20                                                                    0x0f33
+#define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_21                                                                    0x0f34
+#define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_22                                                                    0x0f35
+#define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_23                                                                    0x0f36
+#define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_24                                                                    0x0f37
+#define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f38
+#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_abm3_dispdec
+// base address: 0x30c
+#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0f3d
+#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM3_BL1_PWM_USER_LEVEL                                                                      0x0f3e
+#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM3_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0f3f
+#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0f40
+#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f41
+#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f42
+#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM3_BL1_PWM_ABM_CNTL                                                                        0x0f43
+#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f44
+#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM3_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f45
+#define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM3_DC_ABM1_CNTL                                                                            0x0f46
+#define regABM3_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM3_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f47
+#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0f48
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0f49
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0f4a
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0f4b
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0f4c
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_THRES_12                                                                    0x0f4d
+#define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_ACE_THRES_34                                                                    0x0f4e
+#define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f4f
+#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f51
+#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM3_DC_ABM1_HG_MISC_CTRL                                                                    0x0f52
+#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f53
+#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f54
+#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f55
+#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM3_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f56
+#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f57
+#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f58
+#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f59
+#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM3_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f5a
+#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f5b
+#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f5c
+#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f5d
+#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f5e
+#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f5f
+#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f60
+#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM3_DC_ABM1_HG_RESULT_1                                                                     0x0f61
+#define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_2                                                                     0x0f62
+#define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_3                                                                     0x0f63
+#define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_4                                                                     0x0f64
+#define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_5                                                                     0x0f65
+#define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_6                                                                     0x0f66
+#define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_7                                                                     0x0f67
+#define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_8                                                                     0x0f68
+#define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_9                                                                     0x0f69
+#define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_10                                                                    0x0f6a
+#define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_11                                                                    0x0f6b
+#define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_12                                                                    0x0f6c
+#define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_13                                                                    0x0f6d
+#define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_14                                                                    0x0f6e
+#define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_15                                                                    0x0f6f
+#define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_16                                                                    0x0f70
+#define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_17                                                                    0x0f71
+#define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_18                                                                    0x0f72
+#define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_19                                                                    0x0f73
+#define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_20                                                                    0x0f74
+#define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_21                                                                    0x0f75
+#define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_22                                                                    0x0f76
+#define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_23                                                                    0x0f77
+#define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_24                                                                    0x0f78
+#define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f79
+#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_dpg0_dispdec
+// base address: 0x0
+#define regDPG0_DPG_CONTROL                                                                             0x1854
+#define regDPG0_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG0_DPG_RAMP_CONTROL                                                                        0x1855
+#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG0_DPG_DIMENSIONS                                                                          0x1856
+#define regDPG0_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG0_DPG_COLOUR_R_CR                                                                         0x1857
+#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG0_DPG_COLOUR_G_Y                                                                          0x1858
+#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG0_DPG_COLOUR_B_CB                                                                         0x1859
+#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG0_DPG_OFFSET_SEGMENT                                                                      0x185a
+#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG0_DPG_STATUS                                                                              0x185b
+#define regDPG0_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_fmt0_dispdec
+// base address: 0x0
+#define regFMT0_FMT_CLAMP_COMPONENT_R                                                                   0x183c
+#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT0_FMT_CLAMP_COMPONENT_G                                                                   0x183d
+#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT0_FMT_CLAMP_COMPONENT_B                                                                   0x183e
+#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT0_FMT_DYNAMIC_EXP_CNTL                                                                    0x183f
+#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT0_FMT_CONTROL                                                                             0x1840
+#define regFMT0_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT0_FMT_BIT_DEPTH_CONTROL                                                                   0x1841
+#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT0_FMT_DITHER_RAND_R_SEED                                                                  0x1842
+#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT0_FMT_DITHER_RAND_G_SEED                                                                  0x1843
+#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT0_FMT_DITHER_RAND_B_SEED                                                                  0x1844
+#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT0_FMT_CLAMP_CNTL                                                                          0x1845
+#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1846
+#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT0_FMT_MAP420_MEMORY_CONTROL                                                               0x1847
+#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT0_FMT_422_CONTROL                                                                         0x1849
+#define regFMT0_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_oppbuf0_dispdec
+// base address: 0x0
+#define regOPPBUF0_OPPBUF_CONTROL                                                                       0x1884
+#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0                                                               0x1885
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1                                                               0x1886
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF0_OPPBUF_CONTROL1                                                                      0x1889
+#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe0_dispdec
+// base address: 0x0
+#define regOPP_PIPE0_OPP_PIPE_CONTROL                                                                   0x188c
+#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
+// base address: 0x0
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL                                                           0x1891
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK                                                              0x1892
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0                                                           0x1893
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1                                                           0x1894
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2                                                           0x1895
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_dpg1_dispdec
+// base address: 0x168
+#define regDPG1_DPG_CONTROL                                                                             0x18ae
+#define regDPG1_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG1_DPG_RAMP_CONTROL                                                                        0x18af
+#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG1_DPG_DIMENSIONS                                                                          0x18b0
+#define regDPG1_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG1_DPG_COLOUR_R_CR                                                                         0x18b1
+#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG1_DPG_COLOUR_G_Y                                                                          0x18b2
+#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG1_DPG_COLOUR_B_CB                                                                         0x18b3
+#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG1_DPG_OFFSET_SEGMENT                                                                      0x18b4
+#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG1_DPG_STATUS                                                                              0x18b5
+#define regDPG1_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_fmt1_dispdec
+// base address: 0x168
+#define regFMT1_FMT_CLAMP_COMPONENT_R                                                                   0x1896
+#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT1_FMT_CLAMP_COMPONENT_G                                                                   0x1897
+#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT1_FMT_CLAMP_COMPONENT_B                                                                   0x1898
+#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT1_FMT_DYNAMIC_EXP_CNTL                                                                    0x1899
+#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT1_FMT_CONTROL                                                                             0x189a
+#define regFMT1_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT1_FMT_BIT_DEPTH_CONTROL                                                                   0x189b
+#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT1_FMT_DITHER_RAND_R_SEED                                                                  0x189c
+#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT1_FMT_DITHER_RAND_G_SEED                                                                  0x189d
+#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT1_FMT_DITHER_RAND_B_SEED                                                                  0x189e
+#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT1_FMT_CLAMP_CNTL                                                                          0x189f
+#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18a0
+#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT1_FMT_MAP420_MEMORY_CONTROL                                                               0x18a1
+#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT1_FMT_422_CONTROL                                                                         0x18a3
+#define regFMT1_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_oppbuf1_dispdec
+// base address: 0x168
+#define regOPPBUF1_OPPBUF_CONTROL                                                                       0x18de
+#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0                                                               0x18df
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1                                                               0x18e0
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF1_OPPBUF_CONTROL1                                                                      0x18e3
+#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe1_dispdec
+// base address: 0x168
+#define regOPP_PIPE1_OPP_PIPE_CONTROL                                                                   0x18e6
+#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
+// base address: 0x168
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL                                                           0x18eb
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK                                                              0x18ec
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0                                                           0x18ed
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1                                                           0x18ee
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2                                                           0x18ef
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_dpg2_dispdec
+// base address: 0x2d0
+#define regDPG2_DPG_CONTROL                                                                             0x1908
+#define regDPG2_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG2_DPG_RAMP_CONTROL                                                                        0x1909
+#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG2_DPG_DIMENSIONS                                                                          0x190a
+#define regDPG2_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG2_DPG_COLOUR_R_CR                                                                         0x190b
+#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG2_DPG_COLOUR_G_Y                                                                          0x190c
+#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG2_DPG_COLOUR_B_CB                                                                         0x190d
+#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG2_DPG_OFFSET_SEGMENT                                                                      0x190e
+#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG2_DPG_STATUS                                                                              0x190f
+#define regDPG2_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_fmt2_dispdec
+// base address: 0x2d0
+#define regFMT2_FMT_CLAMP_COMPONENT_R                                                                   0x18f0
+#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT2_FMT_CLAMP_COMPONENT_G                                                                   0x18f1
+#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT2_FMT_CLAMP_COMPONENT_B                                                                   0x18f2
+#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT2_FMT_DYNAMIC_EXP_CNTL                                                                    0x18f3
+#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT2_FMT_CONTROL                                                                             0x18f4
+#define regFMT2_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT2_FMT_BIT_DEPTH_CONTROL                                                                   0x18f5
+#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT2_FMT_DITHER_RAND_R_SEED                                                                  0x18f6
+#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT2_FMT_DITHER_RAND_G_SEED                                                                  0x18f7
+#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT2_FMT_DITHER_RAND_B_SEED                                                                  0x18f8
+#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT2_FMT_CLAMP_CNTL                                                                          0x18f9
+#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18fa
+#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT2_FMT_MAP420_MEMORY_CONTROL                                                               0x18fb
+#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT2_FMT_422_CONTROL                                                                         0x18fd
+#define regFMT2_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_oppbuf2_dispdec
+// base address: 0x2d0
+#define regOPPBUF2_OPPBUF_CONTROL                                                                       0x1938
+#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0                                                               0x1939
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1                                                               0x193a
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF2_OPPBUF_CONTROL1                                                                      0x193d
+#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe2_dispdec
+// base address: 0x2d0
+#define regOPP_PIPE2_OPP_PIPE_CONTROL                                                                   0x1940
+#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
+// base address: 0x2d0
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL                                                           0x1945
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK                                                              0x1946
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0                                                           0x1947
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1                                                           0x1948
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2                                                           0x1949
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_dpg3_dispdec
+// base address: 0x438
+#define regDPG3_DPG_CONTROL                                                                             0x1962
+#define regDPG3_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG3_DPG_RAMP_CONTROL                                                                        0x1963
+#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG3_DPG_DIMENSIONS                                                                          0x1964
+#define regDPG3_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG3_DPG_COLOUR_R_CR                                                                         0x1965
+#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG3_DPG_COLOUR_G_Y                                                                          0x1966
+#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG3_DPG_COLOUR_B_CB                                                                         0x1967
+#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG3_DPG_OFFSET_SEGMENT                                                                      0x1968
+#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG3_DPG_STATUS                                                                              0x1969
+#define regDPG3_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_fmt3_dispdec
+// base address: 0x438
+#define regFMT3_FMT_CLAMP_COMPONENT_R                                                                   0x194a
+#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT3_FMT_CLAMP_COMPONENT_G                                                                   0x194b
+#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT3_FMT_CLAMP_COMPONENT_B                                                                   0x194c
+#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT3_FMT_DYNAMIC_EXP_CNTL                                                                    0x194d
+#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT3_FMT_CONTROL                                                                             0x194e
+#define regFMT3_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT3_FMT_BIT_DEPTH_CONTROL                                                                   0x194f
+#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT3_FMT_DITHER_RAND_R_SEED                                                                  0x1950
+#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT3_FMT_DITHER_RAND_G_SEED                                                                  0x1951
+#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT3_FMT_DITHER_RAND_B_SEED                                                                  0x1952
+#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT3_FMT_CLAMP_CNTL                                                                          0x1953
+#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1954
+#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT3_FMT_MAP420_MEMORY_CONTROL                                                               0x1955
+#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT3_FMT_422_CONTROL                                                                         0x1957
+#define regFMT3_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_oppbuf3_dispdec
+// base address: 0x438
+#define regOPPBUF3_OPPBUF_CONTROL                                                                       0x1992
+#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0                                                               0x1993
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1                                                               0x1994
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF3_OPPBUF_CONTROL1                                                                      0x1997
+#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe3_dispdec
+// base address: 0x438
+#define regOPP_PIPE3_OPP_PIPE_CONTROL                                                                   0x199a
+#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
+// base address: 0x438
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL                                                           0x199f
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK                                                              0x19a0
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0                                                           0x19a1
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1                                                           0x19a2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2                                                           0x19a3
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_dscrm0_dispdec
+// base address: 0x0
+#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a64
+#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_opp_dscrm1_dispdec
+// base address: 0x4
+#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a65
+#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_opp_dscrm2_dispdec
+// base address: 0x8
+#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a66
+#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_opp_dscrm3_dispdec
+// base address: 0xc
+#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a67
+#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_opp_opp_top_dispdec
+// base address: 0x0
+#define regOPP_TOP_CLK_CONTROL                                                                          0x1a5e
+#define regOPP_TOP_CLK_CONTROL_BASE_IDX                                                                 2
+#define regOPP_ABM_CONTROL                                                                              0x1a60
+#define regOPP_ABM_CONTROL_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_optc_odm0_dispdec
+// base address: 0x0
+#define regODM0_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aca
+#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM0_OPTC_DATA_SOURCE_SELECT                                                                 0x1acb
+#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM0_OPTC_DATA_FORMAT_CONTROL                                                                0x1acc
+#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM0_OPTC_BYTES_PER_PIXEL                                                                    0x1acd
+#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM0_OPTC_WIDTH_CONTROL                                                                      0x1ace
+#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM0_OPTC_INPUT_CLOCK_CONTROL                                                                0x1acf
+#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM0_OPTC_MEMORY_CONFIG                                                                      0x1ad0
+#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM0_OPTC_INPUT_SPARE_REGISTER                                                               0x1ad1
+#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_odm1_dispdec
+// base address: 0x40
+#define regODM1_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1ada
+#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM1_OPTC_DATA_SOURCE_SELECT                                                                 0x1adb
+#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM1_OPTC_DATA_FORMAT_CONTROL                                                                0x1adc
+#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM1_OPTC_BYTES_PER_PIXEL                                                                    0x1add
+#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM1_OPTC_WIDTH_CONTROL                                                                      0x1ade
+#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM1_OPTC_INPUT_CLOCK_CONTROL                                                                0x1adf
+#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM1_OPTC_MEMORY_CONFIG                                                                      0x1ae0
+#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM1_OPTC_INPUT_SPARE_REGISTER                                                               0x1ae1
+#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_odm2_dispdec
+// base address: 0x80
+#define regODM2_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aea
+#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM2_OPTC_DATA_SOURCE_SELECT                                                                 0x1aeb
+#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM2_OPTC_DATA_FORMAT_CONTROL                                                                0x1aec
+#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM2_OPTC_BYTES_PER_PIXEL                                                                    0x1aed
+#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM2_OPTC_WIDTH_CONTROL                                                                      0x1aee
+#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM2_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aef
+#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM2_OPTC_MEMORY_CONFIG                                                                      0x1af0
+#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM2_OPTC_INPUT_SPARE_REGISTER                                                               0x1af1
+#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_odm3_dispdec
+// base address: 0xc0
+#define regODM3_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1afa
+#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM3_OPTC_DATA_SOURCE_SELECT                                                                 0x1afb
+#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM3_OPTC_DATA_FORMAT_CONTROL                                                                0x1afc
+#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM3_OPTC_BYTES_PER_PIXEL                                                                    0x1afd
+#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM3_OPTC_WIDTH_CONTROL                                                                      0x1afe
+#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM3_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aff
+#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM3_OPTC_MEMORY_CONFIG                                                                      0x1b00
+#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM3_OPTC_INPUT_SPARE_REGISTER                                                               0x1b01
+#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_otg0_dispdec
+// base address: 0x0
+#define regOTG0_OTG_H_TOTAL                                                                             0x1b2a
+#define regOTG0_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG0_OTG_H_BLANK_START_END                                                                   0x1b2b
+#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG0_OTG_H_SYNC_A                                                                            0x1b2c
+#define regOTG0_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG0_OTG_H_SYNC_A_CNTL                                                                       0x1b2d
+#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG0_OTG_H_TIMING_CNTL                                                                       0x1b2e
+#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG0_OTG_V_TOTAL                                                                             0x1b2f
+#define regOTG0_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG0_OTG_V_TOTAL_MIN                                                                         0x1b30
+#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG0_OTG_V_TOTAL_MAX                                                                         0x1b31
+#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG0_OTG_V_TOTAL_MID                                                                         0x1b32
+#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG0_OTG_V_TOTAL_CONTROL                                                                     0x1b33
+#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG0_OTG_V_TOTAL_INT_STATUS                                                                  0x1b34
+#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG0_OTG_VSYNC_NOM_INT_STATUS                                                                0x1b35
+#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG0_OTG_V_BLANK_START_END                                                                   0x1b36
+#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG0_OTG_V_SYNC_A                                                                            0x1b37
+#define regOTG0_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG0_OTG_V_SYNC_A_CNTL                                                                       0x1b38
+#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG0_OTG_TRIGA_CNTL                                                                          0x1b39
+#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG0_OTG_TRIGA_MANUAL_TRIG                                                                   0x1b3a
+#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG0_OTG_TRIGB_CNTL                                                                          0x1b3b
+#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG0_OTG_TRIGB_MANUAL_TRIG                                                                   0x1b3c
+#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1b3d
+#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG0_OTG_FLOW_CONTROL                                                                        0x1b3e
+#define regOTG0_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1b3f
+#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG0_OTG_CONTROL                                                                             0x1b41
+#define regOTG0_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG0_OTG_INTERLACE_CONTROL                                                                   0x1b44
+#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG0_OTG_INTERLACE_STATUS                                                                    0x1b45
+#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG0_OTG_PIXEL_DATA_READBACK0                                                                0x1b47
+#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG0_OTG_PIXEL_DATA_READBACK1                                                                0x1b48
+#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG0_OTG_STATUS                                                                              0x1b49
+#define regOTG0_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG0_OTG_STATUS_POSITION                                                                     0x1b4a
+#define regOTG0_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG0_OTG_NOM_VERT_POSITION                                                                   0x1b4b
+#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG0_OTG_STATUS_FRAME_COUNT                                                                  0x1b4c
+#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG0_OTG_STATUS_VF_COUNT                                                                     0x1b4d
+#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG0_OTG_STATUS_HV_COUNT                                                                     0x1b4e
+#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG0_OTG_COUNT_CONTROL                                                                       0x1b4f
+#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG0_OTG_COUNT_RESET                                                                         0x1b50
+#define regOTG0_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1b51
+#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG0_OTG_VERT_SYNC_CONTROL                                                                   0x1b52
+#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG0_OTG_STEREO_STATUS                                                                       0x1b53
+#define regOTG0_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG0_OTG_STEREO_CONTROL                                                                      0x1b54
+#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG0_OTG_SNAPSHOT_STATUS                                                                     0x1b55
+#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG0_OTG_SNAPSHOT_CONTROL                                                                    0x1b56
+#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG0_OTG_SNAPSHOT_POSITION                                                                   0x1b57
+#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG0_OTG_SNAPSHOT_FRAME                                                                      0x1b58
+#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG0_OTG_INTERRUPT_CONTROL                                                                   0x1b59
+#define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG0_OTG_UPDATE_LOCK                                                                         0x1b5a
+#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1b5b
+#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG0_OTG_MASTER_EN                                                                           0x1b5c
+#define regOTG0_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1b62
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1b63
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1b64
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1b65
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1b66
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1b67
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG0_OTG_CRC_CNTL                                                                            0x1b68
+#define regOTG0_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1b69
+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1b6a
+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1b6b
+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1b6c
+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_DATA_RG                                                                        0x1b6d
+#define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC0_DATA_B                                                                         0x1b6e
+#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1b6f
+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1b70
+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1b71
+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1b72
+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_DATA_RG                                                                        0x1b73
+#define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC1_DATA_B                                                                         0x1b74
+#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC2_DATA_RG                                                                        0x1b75
+#define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC2_DATA_B                                                                         0x1b76
+#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC3_DATA_RG                                                                        0x1b77
+#define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC3_DATA_B                                                                         0x1b78
+#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1b79
+#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1b7a
+#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG0_OTG_STATIC_SCREEN_CONTROL                                                               0x1b81
+#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG0_OTG_3D_STRUCTURE_CONTROL                                                                0x1b82
+#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG0_OTG_GSL_VSYNC_GAP                                                                       0x1b83
+#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG0_OTG_MASTER_UPDATE_MODE                                                                  0x1b84
+#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG0_OTG_CLOCK_CONTROL                                                                       0x1b85
+#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG0_OTG_VSTARTUP_PARAM                                                                      0x1b86
+#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG0_OTG_VUPDATE_PARAM                                                                       0x1b87
+#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG0_OTG_VREADY_PARAM                                                                        0x1b88
+#define regOTG0_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG0_OTG_GLOBAL_SYNC_STATUS                                                                  0x1b89
+#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG0_OTG_MASTER_UPDATE_LOCK                                                                  0x1b8a
+#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG0_OTG_GSL_CONTROL                                                                         0x1b8b
+#define regOTG0_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG0_OTG_GSL_WINDOW_X                                                                        0x1b8c
+#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG0_OTG_GSL_WINDOW_Y                                                                        0x1b8d
+#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG0_OTG_VUPDATE_KEEPOUT                                                                     0x1b8e
+#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL0                                                                     0x1b8f
+#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL1                                                                     0x1b90
+#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL2                                                                     0x1b91
+#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL3                                                                     0x1b92
+#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL4                                                                     0x1b93
+#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG0_OTG_TRIG_MANUAL_CONTROL                                                                 0x1b94
+#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG0_OTG_MANUAL_FLOW_CONTROL                                                                 0x1b95
+#define regOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG0_OTG_DRR_TIMING_INT_STATUS                                                               0x1b96
+#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1b97
+#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG0_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1b98
+#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG0_OTG_DRR_TRIGGER_WINDOW                                                                  0x1b99
+#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG0_OTG_DRR_CONTROL                                                                         0x1b9a
+#define regOTG0_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG0_OTG_M_CONST_DTO0                                                                        0x1b9b
+#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG0_OTG_M_CONST_DTO1                                                                        0x1b9c
+#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG0_OTG_REQUEST_CONTROL                                                                     0x1b9d
+#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG0_OTG_DSC_START_POSITION                                                                  0x1b9e
+#define regOTG0_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG0_OTG_PIPE_UPDATE_STATUS                                                                  0x1b9f
+#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG0_OTG_SPARE_REGISTER                                                                      0x1ba1
+#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_otg1_dispdec
+// base address: 0x200
+#define regOTG1_OTG_H_TOTAL                                                                             0x1baa
+#define regOTG1_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG1_OTG_H_BLANK_START_END                                                                   0x1bab
+#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG1_OTG_H_SYNC_A                                                                            0x1bac
+#define regOTG1_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG1_OTG_H_SYNC_A_CNTL                                                                       0x1bad
+#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG1_OTG_H_TIMING_CNTL                                                                       0x1bae
+#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG1_OTG_V_TOTAL                                                                             0x1baf
+#define regOTG1_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG1_OTG_V_TOTAL_MIN                                                                         0x1bb0
+#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG1_OTG_V_TOTAL_MAX                                                                         0x1bb1
+#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG1_OTG_V_TOTAL_MID                                                                         0x1bb2
+#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG1_OTG_V_TOTAL_CONTROL                                                                     0x1bb3
+#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG1_OTG_V_TOTAL_INT_STATUS                                                                  0x1bb4
+#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG1_OTG_VSYNC_NOM_INT_STATUS                                                                0x1bb5
+#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG1_OTG_V_BLANK_START_END                                                                   0x1bb6
+#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG1_OTG_V_SYNC_A                                                                            0x1bb7
+#define regOTG1_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG1_OTG_V_SYNC_A_CNTL                                                                       0x1bb8
+#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG1_OTG_TRIGA_CNTL                                                                          0x1bb9
+#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG1_OTG_TRIGA_MANUAL_TRIG                                                                   0x1bba
+#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG1_OTG_TRIGB_CNTL                                                                          0x1bbb
+#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG1_OTG_TRIGB_MANUAL_TRIG                                                                   0x1bbc
+#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1bbd
+#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG1_OTG_FLOW_CONTROL                                                                        0x1bbe
+#define regOTG1_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1bbf
+#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG1_OTG_CONTROL                                                                             0x1bc1
+#define regOTG1_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG1_OTG_INTERLACE_CONTROL                                                                   0x1bc4
+#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG1_OTG_INTERLACE_STATUS                                                                    0x1bc5
+#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG1_OTG_PIXEL_DATA_READBACK0                                                                0x1bc7
+#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG1_OTG_PIXEL_DATA_READBACK1                                                                0x1bc8
+#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG1_OTG_STATUS                                                                              0x1bc9
+#define regOTG1_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG1_OTG_STATUS_POSITION                                                                     0x1bca
+#define regOTG1_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG1_OTG_NOM_VERT_POSITION                                                                   0x1bcb
+#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG1_OTG_STATUS_FRAME_COUNT                                                                  0x1bcc
+#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG1_OTG_STATUS_VF_COUNT                                                                     0x1bcd
+#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG1_OTG_STATUS_HV_COUNT                                                                     0x1bce
+#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG1_OTG_COUNT_CONTROL                                                                       0x1bcf
+#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG1_OTG_COUNT_RESET                                                                         0x1bd0
+#define regOTG1_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1bd1
+#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG1_OTG_VERT_SYNC_CONTROL                                                                   0x1bd2
+#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG1_OTG_STEREO_STATUS                                                                       0x1bd3
+#define regOTG1_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG1_OTG_STEREO_CONTROL                                                                      0x1bd4
+#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG1_OTG_SNAPSHOT_STATUS                                                                     0x1bd5
+#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG1_OTG_SNAPSHOT_CONTROL                                                                    0x1bd6
+#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG1_OTG_SNAPSHOT_POSITION                                                                   0x1bd7
+#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG1_OTG_SNAPSHOT_FRAME                                                                      0x1bd8
+#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG1_OTG_INTERRUPT_CONTROL                                                                   0x1bd9
+#define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG1_OTG_UPDATE_LOCK                                                                         0x1bda
+#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1bdb
+#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG1_OTG_MASTER_EN                                                                           0x1bdc
+#define regOTG1_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1be2
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1be3
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1be4
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1be5
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1be6
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1be7
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG1_OTG_CRC_CNTL                                                                            0x1be8
+#define regOTG1_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1be9
+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1bea
+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1beb
+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1bec
+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_DATA_RG                                                                        0x1bed
+#define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC0_DATA_B                                                                         0x1bee
+#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1bef
+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1bf0
+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1bf1
+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1bf2
+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_DATA_RG                                                                        0x1bf3
+#define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC1_DATA_B                                                                         0x1bf4
+#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC2_DATA_RG                                                                        0x1bf5
+#define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC2_DATA_B                                                                         0x1bf6
+#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC3_DATA_RG                                                                        0x1bf7
+#define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC3_DATA_B                                                                         0x1bf8
+#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1bf9
+#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1bfa
+#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG1_OTG_STATIC_SCREEN_CONTROL                                                               0x1c01
+#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG1_OTG_3D_STRUCTURE_CONTROL                                                                0x1c02
+#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG1_OTG_GSL_VSYNC_GAP                                                                       0x1c03
+#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG1_OTG_MASTER_UPDATE_MODE                                                                  0x1c04
+#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG1_OTG_CLOCK_CONTROL                                                                       0x1c05
+#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG1_OTG_VSTARTUP_PARAM                                                                      0x1c06
+#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG1_OTG_VUPDATE_PARAM                                                                       0x1c07
+#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG1_OTG_VREADY_PARAM                                                                        0x1c08
+#define regOTG1_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG1_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c09
+#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG1_OTG_MASTER_UPDATE_LOCK                                                                  0x1c0a
+#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG1_OTG_GSL_CONTROL                                                                         0x1c0b
+#define regOTG1_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG1_OTG_GSL_WINDOW_X                                                                        0x1c0c
+#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG1_OTG_GSL_WINDOW_Y                                                                        0x1c0d
+#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG1_OTG_VUPDATE_KEEPOUT                                                                     0x1c0e
+#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL0                                                                     0x1c0f
+#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL1                                                                     0x1c10
+#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL2                                                                     0x1c11
+#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL3                                                                     0x1c12
+#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL4                                                                     0x1c13
+#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG1_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c14
+#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG1_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c15
+#define regOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG1_OTG_DRR_TIMING_INT_STATUS                                                               0x1c16
+#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c17
+#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG1_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c18
+#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG1_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c19
+#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG1_OTG_DRR_CONTROL                                                                         0x1c1a
+#define regOTG1_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG1_OTG_M_CONST_DTO0                                                                        0x1c1b
+#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG1_OTG_M_CONST_DTO1                                                                        0x1c1c
+#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG1_OTG_REQUEST_CONTROL                                                                     0x1c1d
+#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG1_OTG_DSC_START_POSITION                                                                  0x1c1e
+#define regOTG1_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG1_OTG_PIPE_UPDATE_STATUS                                                                  0x1c1f
+#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG1_OTG_SPARE_REGISTER                                                                      0x1c21
+#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_otg2_dispdec
+// base address: 0x400
+#define regOTG2_OTG_H_TOTAL                                                                             0x1c2a
+#define regOTG2_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG2_OTG_H_BLANK_START_END                                                                   0x1c2b
+#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG2_OTG_H_SYNC_A                                                                            0x1c2c
+#define regOTG2_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG2_OTG_H_SYNC_A_CNTL                                                                       0x1c2d
+#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG2_OTG_H_TIMING_CNTL                                                                       0x1c2e
+#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG2_OTG_V_TOTAL                                                                             0x1c2f
+#define regOTG2_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG2_OTG_V_TOTAL_MIN                                                                         0x1c30
+#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG2_OTG_V_TOTAL_MAX                                                                         0x1c31
+#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG2_OTG_V_TOTAL_MID                                                                         0x1c32
+#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG2_OTG_V_TOTAL_CONTROL                                                                     0x1c33
+#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG2_OTG_V_TOTAL_INT_STATUS                                                                  0x1c34
+#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG2_OTG_VSYNC_NOM_INT_STATUS                                                                0x1c35
+#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG2_OTG_V_BLANK_START_END                                                                   0x1c36
+#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG2_OTG_V_SYNC_A                                                                            0x1c37
+#define regOTG2_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG2_OTG_V_SYNC_A_CNTL                                                                       0x1c38
+#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG2_OTG_TRIGA_CNTL                                                                          0x1c39
+#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG2_OTG_TRIGA_MANUAL_TRIG                                                                   0x1c3a
+#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG2_OTG_TRIGB_CNTL                                                                          0x1c3b
+#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG2_OTG_TRIGB_MANUAL_TRIG                                                                   0x1c3c
+#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1c3d
+#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG2_OTG_FLOW_CONTROL                                                                        0x1c3e
+#define regOTG2_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1c3f
+#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG2_OTG_CONTROL                                                                             0x1c41
+#define regOTG2_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG2_OTG_INTERLACE_CONTROL                                                                   0x1c44
+#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG2_OTG_INTERLACE_STATUS                                                                    0x1c45
+#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG2_OTG_PIXEL_DATA_READBACK0                                                                0x1c47
+#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG2_OTG_PIXEL_DATA_READBACK1                                                                0x1c48
+#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG2_OTG_STATUS                                                                              0x1c49
+#define regOTG2_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG2_OTG_STATUS_POSITION                                                                     0x1c4a
+#define regOTG2_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG2_OTG_NOM_VERT_POSITION                                                                   0x1c4b
+#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG2_OTG_STATUS_FRAME_COUNT                                                                  0x1c4c
+#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG2_OTG_STATUS_VF_COUNT                                                                     0x1c4d
+#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG2_OTG_STATUS_HV_COUNT                                                                     0x1c4e
+#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG2_OTG_COUNT_CONTROL                                                                       0x1c4f
+#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG2_OTG_COUNT_RESET                                                                         0x1c50
+#define regOTG2_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1c51
+#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG2_OTG_VERT_SYNC_CONTROL                                                                   0x1c52
+#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG2_OTG_STEREO_STATUS                                                                       0x1c53
+#define regOTG2_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG2_OTG_STEREO_CONTROL                                                                      0x1c54
+#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG2_OTG_SNAPSHOT_STATUS                                                                     0x1c55
+#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG2_OTG_SNAPSHOT_CONTROL                                                                    0x1c56
+#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG2_OTG_SNAPSHOT_POSITION                                                                   0x1c57
+#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG2_OTG_SNAPSHOT_FRAME                                                                      0x1c58
+#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG2_OTG_INTERRUPT_CONTROL                                                                   0x1c59
+#define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG2_OTG_UPDATE_LOCK                                                                         0x1c5a
+#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1c5b
+#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG2_OTG_MASTER_EN                                                                           0x1c5c
+#define regOTG2_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1c62
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1c63
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1c64
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1c65
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1c66
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1c67
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG2_OTG_CRC_CNTL                                                                            0x1c68
+#define regOTG2_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1c69
+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1c6a
+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1c6b
+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1c6c
+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_DATA_RG                                                                        0x1c6d
+#define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC0_DATA_B                                                                         0x1c6e
+#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1c6f
+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1c70
+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1c71
+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1c72
+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_DATA_RG                                                                        0x1c73
+#define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC1_DATA_B                                                                         0x1c74
+#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC2_DATA_RG                                                                        0x1c75
+#define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC2_DATA_B                                                                         0x1c76
+#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC3_DATA_RG                                                                        0x1c77
+#define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC3_DATA_B                                                                         0x1c78
+#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1c79
+#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1c7a
+#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG2_OTG_STATIC_SCREEN_CONTROL                                                               0x1c81
+#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG2_OTG_3D_STRUCTURE_CONTROL                                                                0x1c82
+#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG2_OTG_GSL_VSYNC_GAP                                                                       0x1c83
+#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG2_OTG_MASTER_UPDATE_MODE                                                                  0x1c84
+#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG2_OTG_CLOCK_CONTROL                                                                       0x1c85
+#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG2_OTG_VSTARTUP_PARAM                                                                      0x1c86
+#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG2_OTG_VUPDATE_PARAM                                                                       0x1c87
+#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG2_OTG_VREADY_PARAM                                                                        0x1c88
+#define regOTG2_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG2_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c89
+#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG2_OTG_MASTER_UPDATE_LOCK                                                                  0x1c8a
+#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG2_OTG_GSL_CONTROL                                                                         0x1c8b
+#define regOTG2_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG2_OTG_GSL_WINDOW_X                                                                        0x1c8c
+#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG2_OTG_GSL_WINDOW_Y                                                                        0x1c8d
+#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG2_OTG_VUPDATE_KEEPOUT                                                                     0x1c8e
+#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL0                                                                     0x1c8f
+#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL1                                                                     0x1c90
+#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL2                                                                     0x1c91
+#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL3                                                                     0x1c92
+#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL4                                                                     0x1c93
+#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG2_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c94
+#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG2_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c95
+#define regOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG2_OTG_DRR_TIMING_INT_STATUS                                                               0x1c96
+#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c97
+#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG2_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c98
+#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG2_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c99
+#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG2_OTG_DRR_CONTROL                                                                         0x1c9a
+#define regOTG2_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG2_OTG_M_CONST_DTO0                                                                        0x1c9b
+#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG2_OTG_M_CONST_DTO1                                                                        0x1c9c
+#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG2_OTG_REQUEST_CONTROL                                                                     0x1c9d
+#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG2_OTG_DSC_START_POSITION                                                                  0x1c9e
+#define regOTG2_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG2_OTG_PIPE_UPDATE_STATUS                                                                  0x1c9f
+#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG2_OTG_SPARE_REGISTER                                                                      0x1ca1
+#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_otg3_dispdec
+// base address: 0x600
+#define regOTG3_OTG_H_TOTAL                                                                             0x1caa
+#define regOTG3_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG3_OTG_H_BLANK_START_END                                                                   0x1cab
+#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG3_OTG_H_SYNC_A                                                                            0x1cac
+#define regOTG3_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG3_OTG_H_SYNC_A_CNTL                                                                       0x1cad
+#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG3_OTG_H_TIMING_CNTL                                                                       0x1cae
+#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG3_OTG_V_TOTAL                                                                             0x1caf
+#define regOTG3_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG3_OTG_V_TOTAL_MIN                                                                         0x1cb0
+#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG3_OTG_V_TOTAL_MAX                                                                         0x1cb1
+#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG3_OTG_V_TOTAL_MID                                                                         0x1cb2
+#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG3_OTG_V_TOTAL_CONTROL                                                                     0x1cb3
+#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG3_OTG_V_TOTAL_INT_STATUS                                                                  0x1cb4
+#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG3_OTG_VSYNC_NOM_INT_STATUS                                                                0x1cb5
+#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG3_OTG_V_BLANK_START_END                                                                   0x1cb6
+#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG3_OTG_V_SYNC_A                                                                            0x1cb7
+#define regOTG3_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG3_OTG_V_SYNC_A_CNTL                                                                       0x1cb8
+#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG3_OTG_TRIGA_CNTL                                                                          0x1cb9
+#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG3_OTG_TRIGA_MANUAL_TRIG                                                                   0x1cba
+#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG3_OTG_TRIGB_CNTL                                                                          0x1cbb
+#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG3_OTG_TRIGB_MANUAL_TRIG                                                                   0x1cbc
+#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1cbd
+#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG3_OTG_FLOW_CONTROL                                                                        0x1cbe
+#define regOTG3_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1cbf
+#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG3_OTG_CONTROL                                                                             0x1cc1
+#define regOTG3_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG3_OTG_INTERLACE_CONTROL                                                                   0x1cc4
+#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG3_OTG_INTERLACE_STATUS                                                                    0x1cc5
+#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG3_OTG_PIXEL_DATA_READBACK0                                                                0x1cc7
+#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG3_OTG_PIXEL_DATA_READBACK1                                                                0x1cc8
+#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG3_OTG_STATUS                                                                              0x1cc9
+#define regOTG3_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG3_OTG_STATUS_POSITION                                                                     0x1cca
+#define regOTG3_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG3_OTG_NOM_VERT_POSITION                                                                   0x1ccb
+#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG3_OTG_STATUS_FRAME_COUNT                                                                  0x1ccc
+#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG3_OTG_STATUS_VF_COUNT                                                                     0x1ccd
+#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG3_OTG_STATUS_HV_COUNT                                                                     0x1cce
+#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG3_OTG_COUNT_CONTROL                                                                       0x1ccf
+#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG3_OTG_COUNT_RESET                                                                         0x1cd0
+#define regOTG3_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1cd1
+#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG3_OTG_VERT_SYNC_CONTROL                                                                   0x1cd2
+#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG3_OTG_STEREO_STATUS                                                                       0x1cd3
+#define regOTG3_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG3_OTG_STEREO_CONTROL                                                                      0x1cd4
+#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG3_OTG_SNAPSHOT_STATUS                                                                     0x1cd5
+#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG3_OTG_SNAPSHOT_CONTROL                                                                    0x1cd6
+#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG3_OTG_SNAPSHOT_POSITION                                                                   0x1cd7
+#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG3_OTG_SNAPSHOT_FRAME                                                                      0x1cd8
+#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG3_OTG_INTERRUPT_CONTROL                                                                   0x1cd9
+#define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG3_OTG_UPDATE_LOCK                                                                         0x1cda
+#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1cdb
+#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG3_OTG_MASTER_EN                                                                           0x1cdc
+#define regOTG3_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1ce2
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1ce3
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1ce4
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1ce5
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1ce6
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1ce7
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG3_OTG_CRC_CNTL                                                                            0x1ce8
+#define regOTG3_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1ce9
+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1cea
+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1ceb
+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1cec
+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_DATA_RG                                                                        0x1ced
+#define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC0_DATA_B                                                                         0x1cee
+#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1cef
+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1cf0
+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1cf1
+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1cf2
+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_DATA_RG                                                                        0x1cf3
+#define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC1_DATA_B                                                                         0x1cf4
+#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC2_DATA_RG                                                                        0x1cf5
+#define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC2_DATA_B                                                                         0x1cf6
+#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC3_DATA_RG                                                                        0x1cf7
+#define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC3_DATA_B                                                                         0x1cf8
+#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1cf9
+#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1cfa
+#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG3_OTG_STATIC_SCREEN_CONTROL                                                               0x1d01
+#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG3_OTG_3D_STRUCTURE_CONTROL                                                                0x1d02
+#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG3_OTG_GSL_VSYNC_GAP                                                                       0x1d03
+#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG3_OTG_MASTER_UPDATE_MODE                                                                  0x1d04
+#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG3_OTG_CLOCK_CONTROL                                                                       0x1d05
+#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG3_OTG_VSTARTUP_PARAM                                                                      0x1d06
+#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG3_OTG_VUPDATE_PARAM                                                                       0x1d07
+#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG3_OTG_VREADY_PARAM                                                                        0x1d08
+#define regOTG3_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG3_OTG_GLOBAL_SYNC_STATUS                                                                  0x1d09
+#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG3_OTG_MASTER_UPDATE_LOCK                                                                  0x1d0a
+#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG3_OTG_GSL_CONTROL                                                                         0x1d0b
+#define regOTG3_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG3_OTG_GSL_WINDOW_X                                                                        0x1d0c
+#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG3_OTG_GSL_WINDOW_Y                                                                        0x1d0d
+#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG3_OTG_VUPDATE_KEEPOUT                                                                     0x1d0e
+#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL0                                                                     0x1d0f
+#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL1                                                                     0x1d10
+#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL2                                                                     0x1d11
+#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL3                                                                     0x1d12
+#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL4                                                                     0x1d13
+#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG3_OTG_TRIG_MANUAL_CONTROL                                                                 0x1d14
+#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG3_OTG_MANUAL_FLOW_CONTROL                                                                 0x1d15
+#define regOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG3_OTG_DRR_TIMING_INT_STATUS                                                               0x1d16
+#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1d17
+#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG3_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1d18
+#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG3_OTG_DRR_TRIGGER_WINDOW                                                                  0x1d19
+#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG3_OTG_DRR_CONTROL                                                                         0x1d1a
+#define regOTG3_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG3_OTG_M_CONST_DTO0                                                                        0x1d1b
+#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG3_OTG_M_CONST_DTO1                                                                        0x1d1c
+#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG3_OTG_REQUEST_CONTROL                                                                     0x1d1d
+#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG3_OTG_DSC_START_POSITION                                                                  0x1d1e
+#define regOTG3_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG3_OTG_PIPE_UPDATE_STATUS                                                                  0x1d1f
+#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG3_OTG_SPARE_REGISTER                                                                      0x1d21
+#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_optc_misc_dispdec
+// base address: 0x0
+#define regGSL_SOURCE_SELECT                                                                            0x1e2b
+#define regGSL_SOURCE_SELECT_BASE_IDX                                                                   2
+#define regOPTC_CLOCK_CONTROL                                                                           0x1e2c
+#define regOPTC_CLOCK_CONTROL_BASE_IDX                                                                  2
+#define regODM_MEM_PWR_CTRL                                                                             0x1e2d
+#define regODM_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define regODM_MEM_PWR_CTRL3                                                                            0x1e2f
+#define regODM_MEM_PWR_CTRL3_BASE_IDX                                                                   2
+#define regODM_MEM_PWR_STATUS                                                                           0x1e30
+#define regODM_MEM_PWR_STATUS_BASE_IDX                                                                  2
+#define regOPTC_MISC_SPARE_REGISTER                                                                     0x1e31
+#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dio_hpd0_dispdec
+// base address: 0x0
+#define regHPD0_DC_HPD_INT_STATUS                                                                       0x1f14
+#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD0_DC_HPD_INT_CONTROL                                                                      0x1f15
+#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD0_DC_HPD_CONTROL                                                                          0x1f16
+#define regHPD0_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD0_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f17
+#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f18
+#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_hpd1_dispdec
+// base address: 0x20
+#define regHPD1_DC_HPD_INT_STATUS                                                                       0x1f1c
+#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD1_DC_HPD_INT_CONTROL                                                                      0x1f1d
+#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD1_DC_HPD_CONTROL                                                                          0x1f1e
+#define regHPD1_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD1_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f1f
+#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f20
+#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_hpd2_dispdec
+// base address: 0x40
+#define regHPD2_DC_HPD_INT_STATUS                                                                       0x1f24
+#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD2_DC_HPD_INT_CONTROL                                                                      0x1f25
+#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD2_DC_HPD_CONTROL                                                                          0x1f26
+#define regHPD2_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD2_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f27
+#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f28
+#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_hpd3_dispdec
+// base address: 0x60
+#define regHPD3_DC_HPD_INT_STATUS                                                                       0x1f2c
+#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD3_DC_HPD_INT_CONTROL                                                                      0x1f2d
+#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD3_DC_HPD_CONTROL                                                                          0x1f2e
+#define regHPD3_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD3_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f2f
+#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f30
+#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_hpd4_dispdec
+// base address: 0x80
+#define regHPD4_DC_HPD_INT_STATUS                                                                       0x1f34
+#define regHPD4_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD4_DC_HPD_INT_CONTROL                                                                      0x1f35
+#define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD4_DC_HPD_CONTROL                                                                          0x1f36
+#define regHPD4_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD4_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f37
+#define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f38
+#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_dp0_dispdec
+// base address: 0x0
+#define regDP0_DP_LINK_CNTL                                                                             0x2108
+#define regDP0_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_PIXEL_FORMAT                                                                          0x2109
+#define regDP0_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP0_DP_MSA_COLORIMETRY                                                                       0x210a
+#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP0_DP_CONFIG                                                                                0x210b
+#define regDP0_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP0_DP_VID_STREAM_CNTL                                                                       0x210c
+#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_STEER_FIFO                                                                            0x210d
+#define regDP0_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP0_DP_MSA_MISC                                                                              0x210e
+#define regDP0_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP0_DP_DPHY_INTERNAL_CTRL                                                                    0x210f
+#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP0_DP_VID_TIMING                                                                            0x2110
+#define regDP0_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP0_DP_VID_N                                                                                 0x2111
+#define regDP0_DP_VID_N_BASE_IDX                                                                        2
+#define regDP0_DP_VID_M                                                                                 0x2112
+#define regDP0_DP_VID_M_BASE_IDX                                                                        2
+#define regDP0_DP_LINK_FRAMING_CNTL                                                                     0x2113
+#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP0_DP_HBR2_EYE_PATTERN                                                                      0x2114
+#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP0_DP_VID_MSA_VBID                                                                          0x2115
+#define regDP0_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP0_DP_VID_INTERRUPT_CNTL                                                                    0x2116
+#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP0_DP_DPHY_CNTL                                                                             0x2117
+#define regDP0_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2118
+#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP0_DP_DPHY_SYM0                                                                             0x2119
+#define regDP0_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_SYM1                                                                             0x211a
+#define regDP0_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_SYM2                                                                             0x211b
+#define regDP0_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_8B10B_CNTL                                                                       0x211c
+#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_DPHY_PRBS_CNTL                                                                        0x211d
+#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP0_DP_DPHY_SCRAM_CNTL                                                                       0x211e
+#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_DPHY_CRC_EN                                                                           0x211f
+#define regDP0_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP0_DP_DPHY_CRC_CNTL                                                                         0x2120
+#define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP0_DP_DPHY_CRC_RESULT                                                                       0x2121
+#define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP0_DP_DPHY_CRC_MST_CNTL                                                                     0x2122
+#define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP0_DP_DPHY_CRC_MST_STATUS                                                                   0x2123
+#define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP0_DP_DPHY_FAST_TRAINING                                                                    0x2124
+#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP0_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2125
+#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP0_DP_SEC_CNTL                                                                              0x212b
+#define regDP0_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP0_DP_SEC_CNTL1                                                                             0x212c
+#define regDP0_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_FRAMING1                                                                          0x212d
+#define regDP0_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_FRAMING2                                                                          0x212e
+#define regDP0_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_FRAMING3                                                                          0x212f
+#define regDP0_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_FRAMING4                                                                          0x2130
+#define regDP0_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_AUD_N                                                                             0x2131
+#define regDP0_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_AUD_N_READBACK                                                                    0x2132
+#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP0_DP_SEC_AUD_M                                                                             0x2133
+#define regDP0_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_AUD_M_READBACK                                                                    0x2134
+#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP0_DP_SEC_TIMESTAMP                                                                         0x2135
+#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP0_DP_SEC_PACKET_CNTL                                                                       0x2136
+#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_MSE_RATE_CNTL                                                                         0x2137
+#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP0_DP_MSE_RATE_UPDATE                                                                       0x2139
+#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP0_DP_MSE_SAT0                                                                              0x213a
+#define regDP0_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP0_DP_MSE_SAT1                                                                              0x213b
+#define regDP0_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP0_DP_MSE_SAT2                                                                              0x213c
+#define regDP0_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP0_DP_MSE_SAT_UPDATE                                                                        0x213d
+#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP0_DP_MSE_LINK_TIMING                                                                       0x213e
+#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP0_DP_MSE_MISC_CNTL                                                                         0x213f
+#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2144
+#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2145
+#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP0_DP_MSE_SAT0_STATUS                                                                       0x2147
+#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP0_DP_MSE_SAT1_STATUS                                                                       0x2148
+#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP0_DP_MSE_SAT2_STATUS                                                                       0x2149
+#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP0_DP_DPIA_SPARE                                                                            0x214a
+#define regDP0_DP_DPIA_SPARE_BASE_IDX                                                                   2
+#define regDP0_DP_MSA_TIMING_PARAM1                                                                     0x214c
+#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP0_DP_MSA_TIMING_PARAM2                                                                     0x214d
+#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP0_DP_MSA_TIMING_PARAM3                                                                     0x214e
+#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP0_DP_MSA_TIMING_PARAM4                                                                     0x214f
+#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP0_DP_MSO_CNTL                                                                              0x2150
+#define regDP0_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP0_DP_MSO_CNTL1                                                                             0x2151
+#define regDP0_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP0_DP_DSC_CNTL                                                                              0x2152
+#define regDP0_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP0_DP_SEC_CNTL2                                                                             0x2153
+#define regDP0_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL3                                                                             0x2154
+#define regDP0_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL4                                                                             0x2155
+#define regDP0_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL5                                                                             0x2156
+#define regDP0_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL6                                                                             0x2157
+#define regDP0_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL7                                                                             0x2158
+#define regDP0_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP0_DP_DB_CNTL                                                                               0x2159
+#define regDP0_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP0_DP_MSA_VBID_MISC                                                                         0x215a
+#define regDP0_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP0_DP_SEC_METADATA_TRANSMISSION                                                             0x215b
+#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP0_DP_ALPM_CNTL                                                                             0x215d
+#define regDP0_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_GSP8_CNTL                                                                             0x215e
+#define regDP0_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_GSP9_CNTL                                                                             0x215f
+#define regDP0_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_GSP10_CNTL                                                                            0x2160
+#define regDP0_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP0_DP_GSP11_CNTL                                                                            0x2161
+#define regDP0_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP0_DP_GSP_EN_DB_STATUS                                                                      0x2162
+#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+#define regDP0_DP_AUXLESS_ALPM_CNTL1                                                                    0x2163
+#define regDP0_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
+#define regDP0_DP_AUXLESS_ALPM_CNTL2                                                                    0x2164
+#define regDP0_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
+#define regDP0_DP_AUXLESS_ALPM_CNTL3                                                                    0x2165
+#define regDP0_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
+#define regDP0_DP_AUXLESS_ALPM_CNTL4                                                                    0x2166
+#define regDP0_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
+#define regDP0_DP_AUXLESS_ALPM_CNTL5                                                                    0x2167
+#define regDP0_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dig0_dispdec
+// base address: 0x0
+#define regDIG0_DIG_FE_CNTL                                                                             0x208b
+#define regDIG0_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG0_DIG_OUTPUT_CRC_CNTL                                                                     0x208c
+#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG0_DIG_OUTPUT_CRC_RESULT                                                                   0x208d
+#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG0_DIG_CLOCK_PATTERN                                                                       0x208e
+#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG0_DIG_TEST_PATTERN                                                                        0x208f
+#define regDIG0_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG0_DIG_RANDOM_PATTERN_SEED                                                                 0x2090
+#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG0_DIG_FIFO_CTRL0                                                                          0x2091
+#define regDIG0_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
+#define regDIG0_DIG_FIFO_CTRL1                                                                          0x2092
+#define regDIG0_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
+#define regDIG0_HDMI_METADATA_PACKET_CONTROL                                                            0x2093
+#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG0_HDMI_CONTROL                                                                            0x2094
+#define regDIG0_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG0_HDMI_STATUS                                                                             0x2095
+#define regDIG0_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG0_HDMI_AUDIO_PACKET_CONTROL                                                               0x2096
+#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG0_HDMI_ACR_PACKET_CONTROL                                                                 0x2097
+#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG0_HDMI_VBI_PACKET_CONTROL                                                                 0x2098
+#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG0_HDMI_INFOFRAME_CONTROL0                                                                 0x2099
+#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG0_HDMI_INFOFRAME_CONTROL1                                                                 0x209a
+#define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0                                                            0x209b
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6                                                            0x209c
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5                                                            0x209d
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG0_HDMI_GC                                                                                 0x209e
+#define regDIG0_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1                                                            0x209f
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2                                                            0x20a0
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3                                                            0x20a1
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4                                                            0x20a2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7                                                            0x20a3
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8                                                            0x20a4
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9                                                            0x20a5
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10                                                           0x20a6
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG0_HDMI_DB_CONTROL                                                                         0x20a7
+#define regDIG0_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG0_HDMI_ACR_32_0                                                                           0x20a8
+#define regDIG0_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_32_1                                                                           0x20a9
+#define regDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_44_0                                                                           0x20aa
+#define regDIG0_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_44_1                                                                           0x20ab
+#define regDIG0_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_48_0                                                                           0x20ac
+#define regDIG0_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_48_1                                                                           0x20ad
+#define regDIG0_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_STATUS_0                                                                       0x20ae
+#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG0_HDMI_ACR_STATUS_1                                                                       0x20af
+#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG0_AFMT_CNTL                                                                               0x20b0
+#define regDIG0_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG0_DIG_BE_CNTL                                                                             0x20b1
+#define regDIG0_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG0_DIG_BE_EN_CNTL                                                                          0x20b2
+#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG0_TMDS_CNTL                                                                               0x20d8
+#define regDIG0_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG0_TMDS_CONTROL_CHAR                                                                       0x20d9
+#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG0_TMDS_CONTROL0_FEEDBACK                                                                  0x20da
+#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG0_TMDS_STEREOSYNC_CTL_SEL                                                                 0x20db
+#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x20dc
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x20dd
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG0_TMDS_CTL_BITS                                                                           0x20df
+#define regDIG0_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG0_TMDS_DCBALANCER_CONTROL                                                                 0x20e0
+#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR                                                                0x20e1
+#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG0_TMDS_CTL0_1_GEN_CNTL                                                                    0x20e2
+#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG0_TMDS_CTL2_3_GEN_CNTL                                                                    0x20e3
+#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG0_DIG_VERSION                                                                             0x20e5
+#define regDIG0_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG0_FORCE_DIG_DISABLE                                                                       0x20e6
+#define regDIG0_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dp1_dispdec
+// base address: 0x400
+#define regDP1_DP_LINK_CNTL                                                                             0x2208
+#define regDP1_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_PIXEL_FORMAT                                                                          0x2209
+#define regDP1_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP1_DP_MSA_COLORIMETRY                                                                       0x220a
+#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP1_DP_CONFIG                                                                                0x220b
+#define regDP1_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP1_DP_VID_STREAM_CNTL                                                                       0x220c
+#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_STEER_FIFO                                                                            0x220d
+#define regDP1_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP1_DP_MSA_MISC                                                                              0x220e
+#define regDP1_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP1_DP_DPHY_INTERNAL_CTRL                                                                    0x220f
+#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP1_DP_VID_TIMING                                                                            0x2210
+#define regDP1_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP1_DP_VID_N                                                                                 0x2211
+#define regDP1_DP_VID_N_BASE_IDX                                                                        2
+#define regDP1_DP_VID_M                                                                                 0x2212
+#define regDP1_DP_VID_M_BASE_IDX                                                                        2
+#define regDP1_DP_LINK_FRAMING_CNTL                                                                     0x2213
+#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP1_DP_HBR2_EYE_PATTERN                                                                      0x2214
+#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP1_DP_VID_MSA_VBID                                                                          0x2215
+#define regDP1_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP1_DP_VID_INTERRUPT_CNTL                                                                    0x2216
+#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP1_DP_DPHY_CNTL                                                                             0x2217
+#define regDP1_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2218
+#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP1_DP_DPHY_SYM0                                                                             0x2219
+#define regDP1_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_SYM1                                                                             0x221a
+#define regDP1_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_SYM2                                                                             0x221b
+#define regDP1_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_8B10B_CNTL                                                                       0x221c
+#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_DPHY_PRBS_CNTL                                                                        0x221d
+#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP1_DP_DPHY_SCRAM_CNTL                                                                       0x221e
+#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_DPHY_CRC_EN                                                                           0x221f
+#define regDP1_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP1_DP_DPHY_CRC_CNTL                                                                         0x2220
+#define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP1_DP_DPHY_CRC_RESULT                                                                       0x2221
+#define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP1_DP_DPHY_CRC_MST_CNTL                                                                     0x2222
+#define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP1_DP_DPHY_CRC_MST_STATUS                                                                   0x2223
+#define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP1_DP_DPHY_FAST_TRAINING                                                                    0x2224
+#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP1_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2225
+#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP1_DP_SEC_CNTL                                                                              0x222b
+#define regDP1_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP1_DP_SEC_CNTL1                                                                             0x222c
+#define regDP1_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_FRAMING1                                                                          0x222d
+#define regDP1_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_FRAMING2                                                                          0x222e
+#define regDP1_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_FRAMING3                                                                          0x222f
+#define regDP1_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_FRAMING4                                                                          0x2230
+#define regDP1_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_AUD_N                                                                             0x2231
+#define regDP1_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_AUD_N_READBACK                                                                    0x2232
+#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP1_DP_SEC_AUD_M                                                                             0x2233
+#define regDP1_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_AUD_M_READBACK                                                                    0x2234
+#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP1_DP_SEC_TIMESTAMP                                                                         0x2235
+#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP1_DP_SEC_PACKET_CNTL                                                                       0x2236
+#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_MSE_RATE_CNTL                                                                         0x2237
+#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP1_DP_MSE_RATE_UPDATE                                                                       0x2239
+#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP1_DP_MSE_SAT0                                                                              0x223a
+#define regDP1_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP1_DP_MSE_SAT1                                                                              0x223b
+#define regDP1_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP1_DP_MSE_SAT2                                                                              0x223c
+#define regDP1_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP1_DP_MSE_SAT_UPDATE                                                                        0x223d
+#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP1_DP_MSE_LINK_TIMING                                                                       0x223e
+#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP1_DP_MSE_MISC_CNTL                                                                         0x223f
+#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2244
+#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2245
+#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP1_DP_MSE_SAT0_STATUS                                                                       0x2247
+#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP1_DP_MSE_SAT1_STATUS                                                                       0x2248
+#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP1_DP_MSE_SAT2_STATUS                                                                       0x2249
+#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP1_DP_DPIA_SPARE                                                                            0x224a
+#define regDP1_DP_DPIA_SPARE_BASE_IDX                                                                   2
+#define regDP1_DP_MSA_TIMING_PARAM1                                                                     0x224c
+#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP1_DP_MSA_TIMING_PARAM2                                                                     0x224d
+#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP1_DP_MSA_TIMING_PARAM3                                                                     0x224e
+#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP1_DP_MSA_TIMING_PARAM4                                                                     0x224f
+#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP1_DP_MSO_CNTL                                                                              0x2250
+#define regDP1_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP1_DP_MSO_CNTL1                                                                             0x2251
+#define regDP1_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP1_DP_DSC_CNTL                                                                              0x2252
+#define regDP1_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP1_DP_SEC_CNTL2                                                                             0x2253
+#define regDP1_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL3                                                                             0x2254
+#define regDP1_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL4                                                                             0x2255
+#define regDP1_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL5                                                                             0x2256
+#define regDP1_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL6                                                                             0x2257
+#define regDP1_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL7                                                                             0x2258
+#define regDP1_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP1_DP_DB_CNTL                                                                               0x2259
+#define regDP1_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP1_DP_MSA_VBID_MISC                                                                         0x225a
+#define regDP1_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP1_DP_SEC_METADATA_TRANSMISSION                                                             0x225b
+#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP1_DP_ALPM_CNTL                                                                             0x225d
+#define regDP1_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_GSP8_CNTL                                                                             0x225e
+#define regDP1_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_GSP9_CNTL                                                                             0x225f
+#define regDP1_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_GSP10_CNTL                                                                            0x2260
+#define regDP1_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP1_DP_GSP11_CNTL                                                                            0x2261
+#define regDP1_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP1_DP_GSP_EN_DB_STATUS                                                                      0x2262
+#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+#define regDP1_DP_AUXLESS_ALPM_CNTL1                                                                    0x2263
+#define regDP1_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
+#define regDP1_DP_AUXLESS_ALPM_CNTL2                                                                    0x2264
+#define regDP1_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
+#define regDP1_DP_AUXLESS_ALPM_CNTL3                                                                    0x2265
+#define regDP1_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
+#define regDP1_DP_AUXLESS_ALPM_CNTL4                                                                    0x2266
+#define regDP1_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
+#define regDP1_DP_AUXLESS_ALPM_CNTL5                                                                    0x2267
+#define regDP1_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dig1_dispdec
+// base address: 0x400
+#define regDIG1_DIG_FE_CNTL                                                                             0x218b
+#define regDIG1_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG1_DIG_OUTPUT_CRC_CNTL                                                                     0x218c
+#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG1_DIG_OUTPUT_CRC_RESULT                                                                   0x218d
+#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG1_DIG_CLOCK_PATTERN                                                                       0x218e
+#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG1_DIG_TEST_PATTERN                                                                        0x218f
+#define regDIG1_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG1_DIG_RANDOM_PATTERN_SEED                                                                 0x2190
+#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG1_DIG_FIFO_CTRL0                                                                          0x2191
+#define regDIG1_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
+#define regDIG1_DIG_FIFO_CTRL1                                                                          0x2192
+#define regDIG1_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
+#define regDIG1_HDMI_METADATA_PACKET_CONTROL                                                            0x2193
+#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG1_HDMI_CONTROL                                                                            0x2194
+#define regDIG1_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG1_HDMI_STATUS                                                                             0x2195
+#define regDIG1_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG1_HDMI_AUDIO_PACKET_CONTROL                                                               0x2196
+#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG1_HDMI_ACR_PACKET_CONTROL                                                                 0x2197
+#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG1_HDMI_VBI_PACKET_CONTROL                                                                 0x2198
+#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG1_HDMI_INFOFRAME_CONTROL0                                                                 0x2199
+#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG1_HDMI_INFOFRAME_CONTROL1                                                                 0x219a
+#define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0                                                            0x219b
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6                                                            0x219c
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5                                                            0x219d
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG1_HDMI_GC                                                                                 0x219e
+#define regDIG1_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1                                                            0x219f
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2                                                            0x21a0
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3                                                            0x21a1
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4                                                            0x21a2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7                                                            0x21a3
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8                                                            0x21a4
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9                                                            0x21a5
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10                                                           0x21a6
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG1_HDMI_DB_CONTROL                                                                         0x21a7
+#define regDIG1_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG1_HDMI_ACR_32_0                                                                           0x21a8
+#define regDIG1_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_32_1                                                                           0x21a9
+#define regDIG1_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_44_0                                                                           0x21aa
+#define regDIG1_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_44_1                                                                           0x21ab
+#define regDIG1_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_48_0                                                                           0x21ac
+#define regDIG1_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_48_1                                                                           0x21ad
+#define regDIG1_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_STATUS_0                                                                       0x21ae
+#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG1_HDMI_ACR_STATUS_1                                                                       0x21af
+#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG1_AFMT_CNTL                                                                               0x21b0
+#define regDIG1_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG1_DIG_BE_CNTL                                                                             0x21b1
+#define regDIG1_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG1_DIG_BE_EN_CNTL                                                                          0x21b2
+#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG1_TMDS_CNTL                                                                               0x21d8
+#define regDIG1_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG1_TMDS_CONTROL_CHAR                                                                       0x21d9
+#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG1_TMDS_CONTROL0_FEEDBACK                                                                  0x21da
+#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG1_TMDS_STEREOSYNC_CTL_SEL                                                                 0x21db
+#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x21dc
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x21dd
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG1_TMDS_CTL_BITS                                                                           0x21df
+#define regDIG1_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG1_TMDS_DCBALANCER_CONTROL                                                                 0x21e0
+#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR                                                                0x21e1
+#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG1_TMDS_CTL0_1_GEN_CNTL                                                                    0x21e2
+#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG1_TMDS_CTL2_3_GEN_CNTL                                                                    0x21e3
+#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG1_DIG_VERSION                                                                             0x21e5
+#define regDIG1_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG1_FORCE_DIG_DISABLE                                                                       0x21e6
+#define regDIG1_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dp2_dispdec
+// base address: 0x800
+#define regDP2_DP_LINK_CNTL                                                                             0x2308
+#define regDP2_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_PIXEL_FORMAT                                                                          0x2309
+#define regDP2_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP2_DP_MSA_COLORIMETRY                                                                       0x230a
+#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP2_DP_CONFIG                                                                                0x230b
+#define regDP2_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP2_DP_VID_STREAM_CNTL                                                                       0x230c
+#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_STEER_FIFO                                                                            0x230d
+#define regDP2_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP2_DP_MSA_MISC                                                                              0x230e
+#define regDP2_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP2_DP_DPHY_INTERNAL_CTRL                                                                    0x230f
+#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP2_DP_VID_TIMING                                                                            0x2310
+#define regDP2_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP2_DP_VID_N                                                                                 0x2311
+#define regDP2_DP_VID_N_BASE_IDX                                                                        2
+#define regDP2_DP_VID_M                                                                                 0x2312
+#define regDP2_DP_VID_M_BASE_IDX                                                                        2
+#define regDP2_DP_LINK_FRAMING_CNTL                                                                     0x2313
+#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP2_DP_HBR2_EYE_PATTERN                                                                      0x2314
+#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP2_DP_VID_MSA_VBID                                                                          0x2315
+#define regDP2_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP2_DP_VID_INTERRUPT_CNTL                                                                    0x2316
+#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP2_DP_DPHY_CNTL                                                                             0x2317
+#define regDP2_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2318
+#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP2_DP_DPHY_SYM0                                                                             0x2319
+#define regDP2_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_SYM1                                                                             0x231a
+#define regDP2_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_SYM2                                                                             0x231b
+#define regDP2_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_8B10B_CNTL                                                                       0x231c
+#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_DPHY_PRBS_CNTL                                                                        0x231d
+#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP2_DP_DPHY_SCRAM_CNTL                                                                       0x231e
+#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_DPHY_CRC_EN                                                                           0x231f
+#define regDP2_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP2_DP_DPHY_CRC_CNTL                                                                         0x2320
+#define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP2_DP_DPHY_CRC_RESULT                                                                       0x2321
+#define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP2_DP_DPHY_CRC_MST_CNTL                                                                     0x2322
+#define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP2_DP_DPHY_CRC_MST_STATUS                                                                   0x2323
+#define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP2_DP_DPHY_FAST_TRAINING                                                                    0x2324
+#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP2_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2325
+#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP2_DP_SEC_CNTL                                                                              0x232b
+#define regDP2_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP2_DP_SEC_CNTL1                                                                             0x232c
+#define regDP2_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_FRAMING1                                                                          0x232d
+#define regDP2_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_FRAMING2                                                                          0x232e
+#define regDP2_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_FRAMING3                                                                          0x232f
+#define regDP2_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_FRAMING4                                                                          0x2330
+#define regDP2_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_AUD_N                                                                             0x2331
+#define regDP2_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_AUD_N_READBACK                                                                    0x2332
+#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP2_DP_SEC_AUD_M                                                                             0x2333
+#define regDP2_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_AUD_M_READBACK                                                                    0x2334
+#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP2_DP_SEC_TIMESTAMP                                                                         0x2335
+#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP2_DP_SEC_PACKET_CNTL                                                                       0x2336
+#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_MSE_RATE_CNTL                                                                         0x2337
+#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP2_DP_MSE_RATE_UPDATE                                                                       0x2339
+#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP2_DP_MSE_SAT0                                                                              0x233a
+#define regDP2_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP2_DP_MSE_SAT1                                                                              0x233b
+#define regDP2_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP2_DP_MSE_SAT2                                                                              0x233c
+#define regDP2_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP2_DP_MSE_SAT_UPDATE                                                                        0x233d
+#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP2_DP_MSE_LINK_TIMING                                                                       0x233e
+#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP2_DP_MSE_MISC_CNTL                                                                         0x233f
+#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2344
+#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2345
+#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP2_DP_MSE_SAT0_STATUS                                                                       0x2347
+#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP2_DP_MSE_SAT1_STATUS                                                                       0x2348
+#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP2_DP_MSE_SAT2_STATUS                                                                       0x2349
+#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP2_DP_DPIA_SPARE                                                                            0x234a
+#define regDP2_DP_DPIA_SPARE_BASE_IDX                                                                   2
+#define regDP2_DP_MSA_TIMING_PARAM1                                                                     0x234c
+#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP2_DP_MSA_TIMING_PARAM2                                                                     0x234d
+#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP2_DP_MSA_TIMING_PARAM3                                                                     0x234e
+#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP2_DP_MSA_TIMING_PARAM4                                                                     0x234f
+#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP2_DP_MSO_CNTL                                                                              0x2350
+#define regDP2_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP2_DP_MSO_CNTL1                                                                             0x2351
+#define regDP2_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP2_DP_DSC_CNTL                                                                              0x2352
+#define regDP2_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP2_DP_SEC_CNTL2                                                                             0x2353
+#define regDP2_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL3                                                                             0x2354
+#define regDP2_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL4                                                                             0x2355
+#define regDP2_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL5                                                                             0x2356
+#define regDP2_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL6                                                                             0x2357
+#define regDP2_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL7                                                                             0x2358
+#define regDP2_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP2_DP_DB_CNTL                                                                               0x2359
+#define regDP2_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP2_DP_MSA_VBID_MISC                                                                         0x235a
+#define regDP2_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP2_DP_SEC_METADATA_TRANSMISSION                                                             0x235b
+#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP2_DP_ALPM_CNTL                                                                             0x235d
+#define regDP2_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_GSP8_CNTL                                                                             0x235e
+#define regDP2_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_GSP9_CNTL                                                                             0x235f
+#define regDP2_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_GSP10_CNTL                                                                            0x2360
+#define regDP2_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP2_DP_GSP11_CNTL                                                                            0x2361
+#define regDP2_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP2_DP_GSP_EN_DB_STATUS                                                                      0x2362
+#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+#define regDP2_DP_AUXLESS_ALPM_CNTL1                                                                    0x2363
+#define regDP2_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
+#define regDP2_DP_AUXLESS_ALPM_CNTL2                                                                    0x2364
+#define regDP2_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
+#define regDP2_DP_AUXLESS_ALPM_CNTL3                                                                    0x2365
+#define regDP2_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
+#define regDP2_DP_AUXLESS_ALPM_CNTL4                                                                    0x2366
+#define regDP2_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
+#define regDP2_DP_AUXLESS_ALPM_CNTL5                                                                    0x2367
+#define regDP2_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dig2_dispdec
+// base address: 0x800
+#define regDIG2_DIG_FE_CNTL                                                                             0x228b
+#define regDIG2_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG2_DIG_OUTPUT_CRC_CNTL                                                                     0x228c
+#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG2_DIG_OUTPUT_CRC_RESULT                                                                   0x228d
+#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG2_DIG_CLOCK_PATTERN                                                                       0x228e
+#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG2_DIG_TEST_PATTERN                                                                        0x228f
+#define regDIG2_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG2_DIG_RANDOM_PATTERN_SEED                                                                 0x2290
+#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG2_DIG_FIFO_CTRL0                                                                          0x2291
+#define regDIG2_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
+#define regDIG2_DIG_FIFO_CTRL1                                                                          0x2292
+#define regDIG2_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
+#define regDIG2_HDMI_METADATA_PACKET_CONTROL                                                            0x2293
+#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG2_HDMI_CONTROL                                                                            0x2294
+#define regDIG2_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG2_HDMI_STATUS                                                                             0x2295
+#define regDIG2_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG2_HDMI_AUDIO_PACKET_CONTROL                                                               0x2296
+#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG2_HDMI_ACR_PACKET_CONTROL                                                                 0x2297
+#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG2_HDMI_VBI_PACKET_CONTROL                                                                 0x2298
+#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG2_HDMI_INFOFRAME_CONTROL0                                                                 0x2299
+#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG2_HDMI_INFOFRAME_CONTROL1                                                                 0x229a
+#define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0                                                            0x229b
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6                                                            0x229c
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5                                                            0x229d
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG2_HDMI_GC                                                                                 0x229e
+#define regDIG2_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1                                                            0x229f
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2                                                            0x22a0
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3                                                            0x22a1
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4                                                            0x22a2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7                                                            0x22a3
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8                                                            0x22a4
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9                                                            0x22a5
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10                                                           0x22a6
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG2_HDMI_DB_CONTROL                                                                         0x22a7
+#define regDIG2_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG2_HDMI_ACR_32_0                                                                           0x22a8
+#define regDIG2_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_32_1                                                                           0x22a9
+#define regDIG2_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_44_0                                                                           0x22aa
+#define regDIG2_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_44_1                                                                           0x22ab
+#define regDIG2_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_48_0                                                                           0x22ac
+#define regDIG2_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_48_1                                                                           0x22ad
+#define regDIG2_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_STATUS_0                                                                       0x22ae
+#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG2_HDMI_ACR_STATUS_1                                                                       0x22af
+#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG2_AFMT_CNTL                                                                               0x22b0
+#define regDIG2_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG2_DIG_BE_CNTL                                                                             0x22b1
+#define regDIG2_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG2_DIG_BE_EN_CNTL                                                                          0x22b2
+#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG2_TMDS_CNTL                                                                               0x22d8
+#define regDIG2_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG2_TMDS_CONTROL_CHAR                                                                       0x22d9
+#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG2_TMDS_CONTROL0_FEEDBACK                                                                  0x22da
+#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG2_TMDS_STEREOSYNC_CTL_SEL                                                                 0x22db
+#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x22dc
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x22dd
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG2_TMDS_CTL_BITS                                                                           0x22df
+#define regDIG2_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG2_TMDS_DCBALANCER_CONTROL                                                                 0x22e0
+#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR                                                                0x22e1
+#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG2_TMDS_CTL0_1_GEN_CNTL                                                                    0x22e2
+#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG2_TMDS_CTL2_3_GEN_CNTL                                                                    0x22e3
+#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG2_DIG_VERSION                                                                             0x22e5
+#define regDIG2_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG2_FORCE_DIG_DISABLE                                                                       0x22e6
+#define regDIG2_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dp3_dispdec
+// base address: 0xc00
+#define regDP3_DP_LINK_CNTL                                                                             0x2408
+#define regDP3_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_PIXEL_FORMAT                                                                          0x2409
+#define regDP3_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP3_DP_MSA_COLORIMETRY                                                                       0x240a
+#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP3_DP_CONFIG                                                                                0x240b
+#define regDP3_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP3_DP_VID_STREAM_CNTL                                                                       0x240c
+#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_STEER_FIFO                                                                            0x240d
+#define regDP3_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP3_DP_MSA_MISC                                                                              0x240e
+#define regDP3_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP3_DP_DPHY_INTERNAL_CTRL                                                                    0x240f
+#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP3_DP_VID_TIMING                                                                            0x2410
+#define regDP3_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP3_DP_VID_N                                                                                 0x2411
+#define regDP3_DP_VID_N_BASE_IDX                                                                        2
+#define regDP3_DP_VID_M                                                                                 0x2412
+#define regDP3_DP_VID_M_BASE_IDX                                                                        2
+#define regDP3_DP_LINK_FRAMING_CNTL                                                                     0x2413
+#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP3_DP_HBR2_EYE_PATTERN                                                                      0x2414
+#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP3_DP_VID_MSA_VBID                                                                          0x2415
+#define regDP3_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP3_DP_VID_INTERRUPT_CNTL                                                                    0x2416
+#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP3_DP_DPHY_CNTL                                                                             0x2417
+#define regDP3_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2418
+#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP3_DP_DPHY_SYM0                                                                             0x2419
+#define regDP3_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_SYM1                                                                             0x241a
+#define regDP3_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_SYM2                                                                             0x241b
+#define regDP3_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_8B10B_CNTL                                                                       0x241c
+#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_DPHY_PRBS_CNTL                                                                        0x241d
+#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP3_DP_DPHY_SCRAM_CNTL                                                                       0x241e
+#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_DPHY_CRC_EN                                                                           0x241f
+#define regDP3_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP3_DP_DPHY_CRC_CNTL                                                                         0x2420
+#define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP3_DP_DPHY_CRC_RESULT                                                                       0x2421
+#define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP3_DP_DPHY_CRC_MST_CNTL                                                                     0x2422
+#define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP3_DP_DPHY_CRC_MST_STATUS                                                                   0x2423
+#define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP3_DP_DPHY_FAST_TRAINING                                                                    0x2424
+#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP3_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2425
+#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP3_DP_SEC_CNTL                                                                              0x242b
+#define regDP3_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP3_DP_SEC_CNTL1                                                                             0x242c
+#define regDP3_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_FRAMING1                                                                          0x242d
+#define regDP3_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_FRAMING2                                                                          0x242e
+#define regDP3_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_FRAMING3                                                                          0x242f
+#define regDP3_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_FRAMING4                                                                          0x2430
+#define regDP3_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_AUD_N                                                                             0x2431
+#define regDP3_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_AUD_N_READBACK                                                                    0x2432
+#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP3_DP_SEC_AUD_M                                                                             0x2433
+#define regDP3_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_AUD_M_READBACK                                                                    0x2434
+#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP3_DP_SEC_TIMESTAMP                                                                         0x2435
+#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP3_DP_SEC_PACKET_CNTL                                                                       0x2436
+#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_MSE_RATE_CNTL                                                                         0x2437
+#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP3_DP_MSE_RATE_UPDATE                                                                       0x2439
+#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP3_DP_MSE_SAT0                                                                              0x243a
+#define regDP3_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP3_DP_MSE_SAT1                                                                              0x243b
+#define regDP3_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP3_DP_MSE_SAT2                                                                              0x243c
+#define regDP3_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP3_DP_MSE_SAT_UPDATE                                                                        0x243d
+#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP3_DP_MSE_LINK_TIMING                                                                       0x243e
+#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP3_DP_MSE_MISC_CNTL                                                                         0x243f
+#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2444
+#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2445
+#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP3_DP_MSE_SAT0_STATUS                                                                       0x2447
+#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP3_DP_MSE_SAT1_STATUS                                                                       0x2448
+#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP3_DP_MSE_SAT2_STATUS                                                                       0x2449
+#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP3_DP_DPIA_SPARE                                                                            0x244a
+#define regDP3_DP_DPIA_SPARE_BASE_IDX                                                                   2
+#define regDP3_DP_MSA_TIMING_PARAM1                                                                     0x244c
+#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP3_DP_MSA_TIMING_PARAM2                                                                     0x244d
+#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP3_DP_MSA_TIMING_PARAM3                                                                     0x244e
+#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP3_DP_MSA_TIMING_PARAM4                                                                     0x244f
+#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP3_DP_MSO_CNTL                                                                              0x2450
+#define regDP3_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP3_DP_MSO_CNTL1                                                                             0x2451
+#define regDP3_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP3_DP_DSC_CNTL                                                                              0x2452
+#define regDP3_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP3_DP_SEC_CNTL2                                                                             0x2453
+#define regDP3_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL3                                                                             0x2454
+#define regDP3_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL4                                                                             0x2455
+#define regDP3_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL5                                                                             0x2456
+#define regDP3_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL6                                                                             0x2457
+#define regDP3_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL7                                                                             0x2458
+#define regDP3_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP3_DP_DB_CNTL                                                                               0x2459
+#define regDP3_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP3_DP_MSA_VBID_MISC                                                                         0x245a
+#define regDP3_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP3_DP_SEC_METADATA_TRANSMISSION                                                             0x245b
+#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP3_DP_ALPM_CNTL                                                                             0x245d
+#define regDP3_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_GSP8_CNTL                                                                             0x245e
+#define regDP3_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_GSP9_CNTL                                                                             0x245f
+#define regDP3_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_GSP10_CNTL                                                                            0x2460
+#define regDP3_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP3_DP_GSP11_CNTL                                                                            0x2461
+#define regDP3_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP3_DP_GSP_EN_DB_STATUS                                                                      0x2462
+#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+#define regDP3_DP_AUXLESS_ALPM_CNTL1                                                                    0x2463
+#define regDP3_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
+#define regDP3_DP_AUXLESS_ALPM_CNTL2                                                                    0x2464
+#define regDP3_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
+#define regDP3_DP_AUXLESS_ALPM_CNTL3                                                                    0x2465
+#define regDP3_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
+#define regDP3_DP_AUXLESS_ALPM_CNTL4                                                                    0x2466
+#define regDP3_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
+#define regDP3_DP_AUXLESS_ALPM_CNTL5                                                                    0x2467
+#define regDP3_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dig3_dispdec
+// base address: 0xc00
+#define regDIG3_DIG_FE_CNTL                                                                             0x238b
+#define regDIG3_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG3_DIG_OUTPUT_CRC_CNTL                                                                     0x238c
+#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG3_DIG_OUTPUT_CRC_RESULT                                                                   0x238d
+#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG3_DIG_CLOCK_PATTERN                                                                       0x238e
+#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG3_DIG_TEST_PATTERN                                                                        0x238f
+#define regDIG3_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG3_DIG_RANDOM_PATTERN_SEED                                                                 0x2390
+#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG3_DIG_FIFO_CTRL0                                                                          0x2391
+#define regDIG3_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
+#define regDIG3_DIG_FIFO_CTRL1                                                                          0x2392
+#define regDIG3_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
+#define regDIG3_HDMI_METADATA_PACKET_CONTROL                                                            0x2393
+#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG3_HDMI_CONTROL                                                                            0x2394
+#define regDIG3_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG3_HDMI_STATUS                                                                             0x2395
+#define regDIG3_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG3_HDMI_AUDIO_PACKET_CONTROL                                                               0x2396
+#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG3_HDMI_ACR_PACKET_CONTROL                                                                 0x2397
+#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG3_HDMI_VBI_PACKET_CONTROL                                                                 0x2398
+#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG3_HDMI_INFOFRAME_CONTROL0                                                                 0x2399
+#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG3_HDMI_INFOFRAME_CONTROL1                                                                 0x239a
+#define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0                                                            0x239b
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6                                                            0x239c
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5                                                            0x239d
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG3_HDMI_GC                                                                                 0x239e
+#define regDIG3_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1                                                            0x239f
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2                                                            0x23a0
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3                                                            0x23a1
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4                                                            0x23a2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7                                                            0x23a3
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8                                                            0x23a4
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9                                                            0x23a5
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10                                                           0x23a6
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG3_HDMI_DB_CONTROL                                                                         0x23a7
+#define regDIG3_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG3_HDMI_ACR_32_0                                                                           0x23a8
+#define regDIG3_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_32_1                                                                           0x23a9
+#define regDIG3_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_44_0                                                                           0x23aa
+#define regDIG3_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_44_1                                                                           0x23ab
+#define regDIG3_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_48_0                                                                           0x23ac
+#define regDIG3_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_48_1                                                                           0x23ad
+#define regDIG3_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_STATUS_0                                                                       0x23ae
+#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG3_HDMI_ACR_STATUS_1                                                                       0x23af
+#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG3_AFMT_CNTL                                                                               0x23b0
+#define regDIG3_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG3_DIG_BE_CNTL                                                                             0x23b1
+#define regDIG3_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG3_DIG_BE_EN_CNTL                                                                          0x23b2
+#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG3_TMDS_CNTL                                                                               0x23d8
+#define regDIG3_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG3_TMDS_CONTROL_CHAR                                                                       0x23d9
+#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG3_TMDS_CONTROL0_FEEDBACK                                                                  0x23da
+#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG3_TMDS_STEREOSYNC_CTL_SEL                                                                 0x23db
+#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x23dc
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x23dd
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG3_TMDS_CTL_BITS                                                                           0x23df
+#define regDIG3_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG3_TMDS_DCBALANCER_CONTROL                                                                 0x23e0
+#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR                                                                0x23e1
+#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG3_TMDS_CTL0_1_GEN_CNTL                                                                    0x23e2
+#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG3_TMDS_CTL2_3_GEN_CNTL                                                                    0x23e3
+#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG3_DIG_VERSION                                                                             0x23e5
+#define regDIG3_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG3_FORCE_DIG_DISABLE                                                                       0x23e6
+#define regDIG3_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dp4_dispdec
+// base address: 0x1000
+#define regDP4_DP_LINK_CNTL                                                                             0x2508
+#define regDP4_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_PIXEL_FORMAT                                                                          0x2509
+#define regDP4_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP4_DP_MSA_COLORIMETRY                                                                       0x250a
+#define regDP4_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP4_DP_CONFIG                                                                                0x250b
+#define regDP4_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP4_DP_VID_STREAM_CNTL                                                                       0x250c
+#define regDP4_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_STEER_FIFO                                                                            0x250d
+#define regDP4_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP4_DP_MSA_MISC                                                                              0x250e
+#define regDP4_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP4_DP_DPHY_INTERNAL_CTRL                                                                    0x250f
+#define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP4_DP_VID_TIMING                                                                            0x2510
+#define regDP4_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP4_DP_VID_N                                                                                 0x2511
+#define regDP4_DP_VID_N_BASE_IDX                                                                        2
+#define regDP4_DP_VID_M                                                                                 0x2512
+#define regDP4_DP_VID_M_BASE_IDX                                                                        2
+#define regDP4_DP_LINK_FRAMING_CNTL                                                                     0x2513
+#define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP4_DP_HBR2_EYE_PATTERN                                                                      0x2514
+#define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP4_DP_VID_MSA_VBID                                                                          0x2515
+#define regDP4_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP4_DP_VID_INTERRUPT_CNTL                                                                    0x2516
+#define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP4_DP_DPHY_CNTL                                                                             0x2517
+#define regDP4_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2518
+#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP4_DP_DPHY_SYM0                                                                             0x2519
+#define regDP4_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_SYM1                                                                             0x251a
+#define regDP4_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_SYM2                                                                             0x251b
+#define regDP4_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_8B10B_CNTL                                                                       0x251c
+#define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_DPHY_PRBS_CNTL                                                                        0x251d
+#define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP4_DP_DPHY_SCRAM_CNTL                                                                       0x251e
+#define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_DPHY_CRC_EN                                                                           0x251f
+#define regDP4_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP4_DP_DPHY_CRC_CNTL                                                                         0x2520
+#define regDP4_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP4_DP_DPHY_CRC_RESULT                                                                       0x2521
+#define regDP4_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP4_DP_DPHY_CRC_MST_CNTL                                                                     0x2522
+#define regDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP4_DP_DPHY_CRC_MST_STATUS                                                                   0x2523
+#define regDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP4_DP_DPHY_FAST_TRAINING                                                                    0x2524
+#define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP4_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2525
+#define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP4_DP_SEC_CNTL                                                                              0x252b
+#define regDP4_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP4_DP_SEC_CNTL1                                                                             0x252c
+#define regDP4_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_FRAMING1                                                                          0x252d
+#define regDP4_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_FRAMING2                                                                          0x252e
+#define regDP4_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_FRAMING3                                                                          0x252f
+#define regDP4_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_FRAMING4                                                                          0x2530
+#define regDP4_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_AUD_N                                                                             0x2531
+#define regDP4_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_AUD_N_READBACK                                                                    0x2532
+#define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP4_DP_SEC_AUD_M                                                                             0x2533
+#define regDP4_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_AUD_M_READBACK                                                                    0x2534
+#define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP4_DP_SEC_TIMESTAMP                                                                         0x2535
+#define regDP4_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP4_DP_SEC_PACKET_CNTL                                                                       0x2536
+#define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_MSE_RATE_CNTL                                                                         0x2537
+#define regDP4_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP4_DP_MSE_RATE_UPDATE                                                                       0x2539
+#define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP4_DP_MSE_SAT0                                                                              0x253a
+#define regDP4_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP4_DP_MSE_SAT1                                                                              0x253b
+#define regDP4_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP4_DP_MSE_SAT2                                                                              0x253c
+#define regDP4_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP4_DP_MSE_SAT_UPDATE                                                                        0x253d
+#define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP4_DP_MSE_LINK_TIMING                                                                       0x253e
+#define regDP4_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP4_DP_MSE_MISC_CNTL                                                                         0x253f
+#define regDP4_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2544
+#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2545
+#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP4_DP_MSE_SAT0_STATUS                                                                       0x2547
+#define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP4_DP_MSE_SAT1_STATUS                                                                       0x2548
+#define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP4_DP_MSE_SAT2_STATUS                                                                       0x2549
+#define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP4_DP_DPIA_SPARE                                                                            0x254a
+#define regDP4_DP_DPIA_SPARE_BASE_IDX                                                                   2
+#define regDP4_DP_MSA_TIMING_PARAM1                                                                     0x254c
+#define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP4_DP_MSA_TIMING_PARAM2                                                                     0x254d
+#define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP4_DP_MSA_TIMING_PARAM3                                                                     0x254e
+#define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP4_DP_MSA_TIMING_PARAM4                                                                     0x254f
+#define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP4_DP_MSO_CNTL                                                                              0x2550
+#define regDP4_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP4_DP_MSO_CNTL1                                                                             0x2551
+#define regDP4_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP4_DP_DSC_CNTL                                                                              0x2552
+#define regDP4_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP4_DP_SEC_CNTL2                                                                             0x2553
+#define regDP4_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL3                                                                             0x2554
+#define regDP4_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL4                                                                             0x2555
+#define regDP4_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL5                                                                             0x2556
+#define regDP4_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL6                                                                             0x2557
+#define regDP4_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL7                                                                             0x2558
+#define regDP4_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP4_DP_DB_CNTL                                                                               0x2559
+#define regDP4_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP4_DP_MSA_VBID_MISC                                                                         0x255a
+#define regDP4_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP4_DP_SEC_METADATA_TRANSMISSION                                                             0x255b
+#define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP4_DP_ALPM_CNTL                                                                             0x255d
+#define regDP4_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_GSP8_CNTL                                                                             0x255e
+#define regDP4_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_GSP9_CNTL                                                                             0x255f
+#define regDP4_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_GSP10_CNTL                                                                            0x2560
+#define regDP4_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP4_DP_GSP11_CNTL                                                                            0x2561
+#define regDP4_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP4_DP_GSP_EN_DB_STATUS                                                                      0x2562
+#define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+#define regDP4_DP_AUXLESS_ALPM_CNTL1                                                                    0x2563
+#define regDP4_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
+#define regDP4_DP_AUXLESS_ALPM_CNTL2                                                                    0x2564
+#define regDP4_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
+#define regDP4_DP_AUXLESS_ALPM_CNTL3                                                                    0x2565
+#define regDP4_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
+#define regDP4_DP_AUXLESS_ALPM_CNTL4                                                                    0x2566
+#define regDP4_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
+#define regDP4_DP_AUXLESS_ALPM_CNTL5                                                                    0x2567
+#define regDP4_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dig4_dispdec
+// base address: 0x1000
+#define regDIG4_DIG_FE_CNTL                                                                             0x248b
+#define regDIG4_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG4_DIG_OUTPUT_CRC_CNTL                                                                     0x248c
+#define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG4_DIG_OUTPUT_CRC_RESULT                                                                   0x248d
+#define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG4_DIG_CLOCK_PATTERN                                                                       0x248e
+#define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG4_DIG_TEST_PATTERN                                                                        0x248f
+#define regDIG4_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG4_DIG_RANDOM_PATTERN_SEED                                                                 0x2490
+#define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG4_DIG_FIFO_CTRL0                                                                          0x2491
+#define regDIG4_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
+#define regDIG4_DIG_FIFO_CTRL1                                                                          0x2492
+#define regDIG4_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
+#define regDIG4_HDMI_METADATA_PACKET_CONTROL                                                            0x2493
+#define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG4_HDMI_CONTROL                                                                            0x2494
+#define regDIG4_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG4_HDMI_STATUS                                                                             0x2495
+#define regDIG4_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG4_HDMI_AUDIO_PACKET_CONTROL                                                               0x2496
+#define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG4_HDMI_ACR_PACKET_CONTROL                                                                 0x2497
+#define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG4_HDMI_VBI_PACKET_CONTROL                                                                 0x2498
+#define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG4_HDMI_INFOFRAME_CONTROL0                                                                 0x2499
+#define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG4_HDMI_INFOFRAME_CONTROL1                                                                 0x249a
+#define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0                                                            0x249b
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6                                                            0x249c
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5                                                            0x249d
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG4_HDMI_GC                                                                                 0x249e
+#define regDIG4_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1                                                            0x249f
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2                                                            0x24a0
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3                                                            0x24a1
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4                                                            0x24a2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7                                                            0x24a3
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8                                                            0x24a4
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9                                                            0x24a5
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10                                                           0x24a6
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG4_HDMI_DB_CONTROL                                                                         0x24a7
+#define regDIG4_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG4_HDMI_ACR_32_0                                                                           0x24a8
+#define regDIG4_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_32_1                                                                           0x24a9
+#define regDIG4_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_44_0                                                                           0x24aa
+#define regDIG4_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_44_1                                                                           0x24ab
+#define regDIG4_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_48_0                                                                           0x24ac
+#define regDIG4_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_48_1                                                                           0x24ad
+#define regDIG4_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_STATUS_0                                                                       0x24ae
+#define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG4_HDMI_ACR_STATUS_1                                                                       0x24af
+#define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG4_AFMT_CNTL                                                                               0x24b0
+#define regDIG4_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG4_DIG_BE_CNTL                                                                             0x24b1
+#define regDIG4_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG4_DIG_BE_EN_CNTL                                                                          0x24b2
+#define regDIG4_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG4_TMDS_CNTL                                                                               0x24d8
+#define regDIG4_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG4_TMDS_CONTROL_CHAR                                                                       0x24d9
+#define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG4_TMDS_CONTROL0_FEEDBACK                                                                  0x24da
+#define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG4_TMDS_STEREOSYNC_CTL_SEL                                                                 0x24db
+#define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x24dc
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x24dd
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG4_TMDS_CTL_BITS                                                                           0x24df
+#define regDIG4_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG4_TMDS_DCBALANCER_CONTROL                                                                 0x24e0
+#define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR                                                                0x24e1
+#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG4_TMDS_CTL0_1_GEN_CNTL                                                                    0x24e2
+#define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG4_TMDS_CTL2_3_GEN_CNTL                                                                    0x24e3
+#define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG4_DIG_VERSION                                                                             0x24e5
+#define regDIG4_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG4_FORCE_DIG_DISABLE                                                                       0x24e6
+#define regDIG4_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec
+// base address: 0x154cc
+#define regAFMT0_AFMT_VBI_PACKET_CONTROL                                                                0x2074
+#define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2075
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT0_AFMT_AUDIO_INFO0                                                                       0x2076
+#define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT0_AFMT_AUDIO_INFO1                                                                       0x2077
+#define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT0_AFMT_60958_0                                                                           0x2078
+#define regAFMT0_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT0_AFMT_60958_1                                                                           0x2079
+#define regAFMT0_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT0_AFMT_AUDIO_CRC_CONTROL                                                                 0x207a
+#define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT0_AFMT_RAMP_CONTROL0                                                                     0x207b
+#define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT0_AFMT_RAMP_CONTROL1                                                                     0x207c
+#define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT0_AFMT_RAMP_CONTROL2                                                                     0x207d
+#define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT0_AFMT_RAMP_CONTROL3                                                                     0x207e
+#define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT0_AFMT_60958_2                                                                           0x207f
+#define regAFMT0_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT0_AFMT_AUDIO_CRC_RESULT                                                                  0x2080
+#define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT0_AFMT_STATUS                                                                            0x2081
+#define regAFMT0_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL                                                              0x2082
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT0_AFMT_INFOFRAME_CONTROL0                                                                0x2083
+#define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT0_AFMT_INTERRUPT_STATUS                                                                  0x2084
+#define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT0_AFMT_AUDIO_SRC_CONTROL                                                                 0x2085
+#define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT0_AFMT_MEM_PWR                                                                           0x2087
+#define regAFMT0_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec
+// base address: 0x158cc
+#define regAFMT1_AFMT_VBI_PACKET_CONTROL                                                                0x2174
+#define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2175
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT1_AFMT_AUDIO_INFO0                                                                       0x2176
+#define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT1_AFMT_AUDIO_INFO1                                                                       0x2177
+#define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT1_AFMT_60958_0                                                                           0x2178
+#define regAFMT1_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT1_AFMT_60958_1                                                                           0x2179
+#define regAFMT1_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT1_AFMT_AUDIO_CRC_CONTROL                                                                 0x217a
+#define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT1_AFMT_RAMP_CONTROL0                                                                     0x217b
+#define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT1_AFMT_RAMP_CONTROL1                                                                     0x217c
+#define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT1_AFMT_RAMP_CONTROL2                                                                     0x217d
+#define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT1_AFMT_RAMP_CONTROL3                                                                     0x217e
+#define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT1_AFMT_60958_2                                                                           0x217f
+#define regAFMT1_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT1_AFMT_AUDIO_CRC_RESULT                                                                  0x2180
+#define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT1_AFMT_STATUS                                                                            0x2181
+#define regAFMT1_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL                                                              0x2182
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT1_AFMT_INFOFRAME_CONTROL0                                                                0x2183
+#define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT1_AFMT_INTERRUPT_STATUS                                                                  0x2184
+#define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT1_AFMT_AUDIO_SRC_CONTROL                                                                 0x2185
+#define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT1_AFMT_MEM_PWR                                                                           0x2187
+#define regAFMT1_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec
+// base address: 0x15ccc
+#define regAFMT2_AFMT_VBI_PACKET_CONTROL                                                                0x2274
+#define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2275
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT2_AFMT_AUDIO_INFO0                                                                       0x2276
+#define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT2_AFMT_AUDIO_INFO1                                                                       0x2277
+#define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT2_AFMT_60958_0                                                                           0x2278
+#define regAFMT2_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT2_AFMT_60958_1                                                                           0x2279
+#define regAFMT2_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT2_AFMT_AUDIO_CRC_CONTROL                                                                 0x227a
+#define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT2_AFMT_RAMP_CONTROL0                                                                     0x227b
+#define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT2_AFMT_RAMP_CONTROL1                                                                     0x227c
+#define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT2_AFMT_RAMP_CONTROL2                                                                     0x227d
+#define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT2_AFMT_RAMP_CONTROL3                                                                     0x227e
+#define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT2_AFMT_60958_2                                                                           0x227f
+#define regAFMT2_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT2_AFMT_AUDIO_CRC_RESULT                                                                  0x2280
+#define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT2_AFMT_STATUS                                                                            0x2281
+#define regAFMT2_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL                                                              0x2282
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT2_AFMT_INFOFRAME_CONTROL0                                                                0x2283
+#define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT2_AFMT_INTERRUPT_STATUS                                                                  0x2284
+#define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT2_AFMT_AUDIO_SRC_CONTROL                                                                 0x2285
+#define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT2_AFMT_MEM_PWR                                                                           0x2287
+#define regAFMT2_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec
+// base address: 0x160cc
+#define regAFMT3_AFMT_VBI_PACKET_CONTROL                                                                0x2374
+#define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2375
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT3_AFMT_AUDIO_INFO0                                                                       0x2376
+#define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT3_AFMT_AUDIO_INFO1                                                                       0x2377
+#define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT3_AFMT_60958_0                                                                           0x2378
+#define regAFMT3_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT3_AFMT_60958_1                                                                           0x2379
+#define regAFMT3_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT3_AFMT_AUDIO_CRC_CONTROL                                                                 0x237a
+#define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT3_AFMT_RAMP_CONTROL0                                                                     0x237b
+#define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT3_AFMT_RAMP_CONTROL1                                                                     0x237c
+#define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT3_AFMT_RAMP_CONTROL2                                                                     0x237d
+#define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT3_AFMT_RAMP_CONTROL3                                                                     0x237e
+#define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT3_AFMT_60958_2                                                                           0x237f
+#define regAFMT3_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT3_AFMT_AUDIO_CRC_RESULT                                                                  0x2380
+#define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT3_AFMT_STATUS                                                                            0x2381
+#define regAFMT3_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL                                                              0x2382
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT3_AFMT_INFOFRAME_CONTROL0                                                                0x2383
+#define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT3_AFMT_INTERRUPT_STATUS                                                                  0x2384
+#define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT3_AFMT_AUDIO_SRC_CONTROL                                                                 0x2385
+#define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT3_AFMT_MEM_PWR                                                                           0x2387
+#define regAFMT3_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec
+// base address: 0x164cc
+#define regAFMT4_AFMT_VBI_PACKET_CONTROL                                                                0x2474
+#define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2475
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT4_AFMT_AUDIO_INFO0                                                                       0x2476
+#define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT4_AFMT_AUDIO_INFO1                                                                       0x2477
+#define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT4_AFMT_60958_0                                                                           0x2478
+#define regAFMT4_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT4_AFMT_60958_1                                                                           0x2479
+#define regAFMT4_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT4_AFMT_AUDIO_CRC_CONTROL                                                                 0x247a
+#define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT4_AFMT_RAMP_CONTROL0                                                                     0x247b
+#define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT4_AFMT_RAMP_CONTROL1                                                                     0x247c
+#define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT4_AFMT_RAMP_CONTROL2                                                                     0x247d
+#define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT4_AFMT_RAMP_CONTROL3                                                                     0x247e
+#define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT4_AFMT_60958_2                                                                           0x247f
+#define regAFMT4_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT4_AFMT_AUDIO_CRC_RESULT                                                                  0x2480
+#define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT4_AFMT_STATUS                                                                            0x2481
+#define regAFMT4_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL                                                              0x2482
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT4_AFMT_INFOFRAME_CONTROL0                                                                0x2483
+#define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT4_AFMT_INTERRUPT_STATUS                                                                  0x2484
+#define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT4_AFMT_AUDIO_SRC_CONTROL                                                                 0x2485
+#define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT4_AFMT_MEM_PWR                                                                           0x2487
+#define regAFMT4_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec
+// base address: 0x15524
+#define regDME0_DME_CONTROL                                                                             0x2089
+#define regDME0_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME0_DME_MEMORY_CONTROL                                                                      0x208a
+#define regDME0_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec
+// base address: 0x154a0
+#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2068
+#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG0_VPG_GENERIC_PACKET_DATA                                                                 0x2069
+#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x206a
+#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x206b
+#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG0_VPG_GENERIC_STATUS                                                                      0x206c
+#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG0_VPG_MEM_PWR                                                                             0x206d
+#define regVPG0_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x206e
+#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG0_VPG_ISRC1_2_DATA                                                                        0x206f
+#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG0_VPG_MPEG_INFO0                                                                          0x2070
+#define regVPG0_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG0_VPG_MPEG_INFO1                                                                          0x2071
+#define regVPG0_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec
+// base address: 0x15924
+#define regDME1_DME_CONTROL                                                                             0x2189
+#define regDME1_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME1_DME_MEMORY_CONTROL                                                                      0x218a
+#define regDME1_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec
+// base address: 0x158a0
+#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2168
+#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG1_VPG_GENERIC_PACKET_DATA                                                                 0x2169
+#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x216a
+#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x216b
+#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG1_VPG_GENERIC_STATUS                                                                      0x216c
+#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG1_VPG_MEM_PWR                                                                             0x216d
+#define regVPG1_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x216e
+#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG1_VPG_ISRC1_2_DATA                                                                        0x216f
+#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG1_VPG_MPEG_INFO0                                                                          0x2170
+#define regVPG1_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG1_VPG_MPEG_INFO1                                                                          0x2171
+#define regVPG1_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec
+// base address: 0x15d24
+#define regDME2_DME_CONTROL                                                                             0x2289
+#define regDME2_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME2_DME_MEMORY_CONTROL                                                                      0x228a
+#define regDME2_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec
+// base address: 0x15ca0
+#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2268
+#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG2_VPG_GENERIC_PACKET_DATA                                                                 0x2269
+#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x226a
+#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x226b
+#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG2_VPG_GENERIC_STATUS                                                                      0x226c
+#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG2_VPG_MEM_PWR                                                                             0x226d
+#define regVPG2_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x226e
+#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG2_VPG_ISRC1_2_DATA                                                                        0x226f
+#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG2_VPG_MPEG_INFO0                                                                          0x2270
+#define regVPG2_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG2_VPG_MPEG_INFO1                                                                          0x2271
+#define regVPG2_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec
+// base address: 0x16124
+#define regDME3_DME_CONTROL                                                                             0x2389
+#define regDME3_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME3_DME_MEMORY_CONTROL                                                                      0x238a
+#define regDME3_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec
+// base address: 0x160a0
+#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2368
+#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG3_VPG_GENERIC_PACKET_DATA                                                                 0x2369
+#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x236a
+#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x236b
+#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG3_VPG_GENERIC_STATUS                                                                      0x236c
+#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG3_VPG_MEM_PWR                                                                             0x236d
+#define regVPG3_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x236e
+#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG3_VPG_ISRC1_2_DATA                                                                        0x236f
+#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG3_VPG_MPEG_INFO0                                                                          0x2370
+#define regVPG3_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG3_VPG_MPEG_INFO1                                                                          0x2371
+#define regVPG3_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec
+// base address: 0x16524
+#define regDME4_DME_CONTROL                                                                             0x2489
+#define regDME4_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME4_DME_MEMORY_CONTROL                                                                      0x248a
+#define regDME4_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec
+// base address: 0x164a0
+#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2468
+#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG4_VPG_GENERIC_PACKET_DATA                                                                 0x2469
+#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x246a
+#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x246b
+#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG4_VPG_GENERIC_STATUS                                                                      0x246c
+#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG4_VPG_MEM_PWR                                                                             0x246d
+#define regVPG4_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x246e
+#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG4_VPG_ISRC1_2_DATA                                                                        0x246f
+#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG4_VPG_MPEG_INFO0                                                                          0x2470
+#define regVPG4_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG4_VPG_MPEG_INFO1                                                                          0x2471
+#define regVPG4_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dp_aux0_dispdec
+// base address: 0x0
+#define regDP_AUX0_AUX_CONTROL                                                                          0x1f50
+#define regDP_AUX0_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX0_AUX_SW_CONTROL                                                                       0x1f51
+#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX0_AUX_ARB_CONTROL                                                                      0x1f52
+#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX0_AUX_INTERRUPT_CONTROL                                                                0x1f53
+#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX0_AUX_SW_STATUS                                                                        0x1f54
+#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX0_AUX_LS_STATUS                                                                        0x1f55
+#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX0_AUX_SW_DATA                                                                          0x1f56
+#define regDP_AUX0_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX0_AUX_LS_DATA                                                                          0x1f57
+#define regDP_AUX0_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                                              0x1f58
+#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX0_AUX_DPHY_TX_CONTROL                                                                  0x1f59
+#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL0                                                                 0x1f5a
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL1                                                                 0x1f5b
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX0_AUX_DPHY_TX_STATUS                                                                   0x1f5c
+#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX0_AUX_DPHY_RX_STATUS                                                                   0x1f5d
+#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROL                                                                 0x1f5e
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f5f
+#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f60
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX0_AUX_GTC_SYNC_STATUS                                                                  0x1f61
+#define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX0_AUX_PHY_WAKE_CNTL                                                                    0x1f66
+#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dp_aux1_dispdec
+// base address: 0x70
+#define regDP_AUX1_AUX_CONTROL                                                                          0x1f6c
+#define regDP_AUX1_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX1_AUX_SW_CONTROL                                                                       0x1f6d
+#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX1_AUX_ARB_CONTROL                                                                      0x1f6e
+#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX1_AUX_INTERRUPT_CONTROL                                                                0x1f6f
+#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX1_AUX_SW_STATUS                                                                        0x1f70
+#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX1_AUX_LS_STATUS                                                                        0x1f71
+#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX1_AUX_SW_DATA                                                                          0x1f72
+#define regDP_AUX1_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX1_AUX_LS_DATA                                                                          0x1f73
+#define regDP_AUX1_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                                              0x1f74
+#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX1_AUX_DPHY_TX_CONTROL                                                                  0x1f75
+#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL0                                                                 0x1f76
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL1                                                                 0x1f77
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX1_AUX_DPHY_TX_STATUS                                                                   0x1f78
+#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX1_AUX_DPHY_RX_STATUS                                                                   0x1f79
+#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROL                                                                 0x1f7a
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f7b
+#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f7c
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX1_AUX_GTC_SYNC_STATUS                                                                  0x1f7d
+#define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX1_AUX_PHY_WAKE_CNTL                                                                    0x1f82
+#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dp_aux2_dispdec
+// base address: 0xe0
+#define regDP_AUX2_AUX_CONTROL                                                                          0x1f88
+#define regDP_AUX2_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX2_AUX_SW_CONTROL                                                                       0x1f89
+#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX2_AUX_ARB_CONTROL                                                                      0x1f8a
+#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX2_AUX_INTERRUPT_CONTROL                                                                0x1f8b
+#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX2_AUX_SW_STATUS                                                                        0x1f8c
+#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX2_AUX_LS_STATUS                                                                        0x1f8d
+#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX2_AUX_SW_DATA                                                                          0x1f8e
+#define regDP_AUX2_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX2_AUX_LS_DATA                                                                          0x1f8f
+#define regDP_AUX2_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                                              0x1f90
+#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX2_AUX_DPHY_TX_CONTROL                                                                  0x1f91
+#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL0                                                                 0x1f92
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL1                                                                 0x1f93
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX2_AUX_DPHY_TX_STATUS                                                                   0x1f94
+#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX2_AUX_DPHY_RX_STATUS                                                                   0x1f95
+#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROL                                                                 0x1f96
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f97
+#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f98
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX2_AUX_GTC_SYNC_STATUS                                                                  0x1f99
+#define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX2_AUX_PHY_WAKE_CNTL                                                                    0x1f9e
+#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dp_aux3_dispdec
+// base address: 0x150
+#define regDP_AUX3_AUX_CONTROL                                                                          0x1fa4
+#define regDP_AUX3_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX3_AUX_SW_CONTROL                                                                       0x1fa5
+#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX3_AUX_ARB_CONTROL                                                                      0x1fa6
+#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX3_AUX_INTERRUPT_CONTROL                                                                0x1fa7
+#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX3_AUX_SW_STATUS                                                                        0x1fa8
+#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX3_AUX_LS_STATUS                                                                        0x1fa9
+#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX3_AUX_SW_DATA                                                                          0x1faa
+#define regDP_AUX3_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX3_AUX_LS_DATA                                                                          0x1fab
+#define regDP_AUX3_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                                              0x1fac
+#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX3_AUX_DPHY_TX_CONTROL                                                                  0x1fad
+#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL0                                                                 0x1fae
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL1                                                                 0x1faf
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX3_AUX_DPHY_TX_STATUS                                                                   0x1fb0
+#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX3_AUX_DPHY_RX_STATUS                                                                   0x1fb1
+#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROL                                                                 0x1fb2
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fb3
+#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fb4
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX3_AUX_GTC_SYNC_STATUS                                                                  0x1fb5
+#define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX3_AUX_PHY_WAKE_CNTL                                                                    0x1fba
+#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dp_aux4_dispdec
+// base address: 0x1c0
+#define regDP_AUX4_AUX_CONTROL                                                                          0x1fc0
+#define regDP_AUX4_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX4_AUX_SW_CONTROL                                                                       0x1fc1
+#define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX4_AUX_ARB_CONTROL                                                                      0x1fc2
+#define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX4_AUX_INTERRUPT_CONTROL                                                                0x1fc3
+#define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX4_AUX_SW_STATUS                                                                        0x1fc4
+#define regDP_AUX4_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX4_AUX_LS_STATUS                                                                        0x1fc5
+#define regDP_AUX4_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX4_AUX_SW_DATA                                                                          0x1fc6
+#define regDP_AUX4_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX4_AUX_LS_DATA                                                                          0x1fc7
+#define regDP_AUX4_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL                                                              0x1fc8
+#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX4_AUX_DPHY_TX_CONTROL                                                                  0x1fc9
+#define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL0                                                                 0x1fca
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL1                                                                 0x1fcb
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX4_AUX_DPHY_TX_STATUS                                                                   0x1fcc
+#define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX4_AUX_DPHY_RX_STATUS                                                                   0x1fcd
+#define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROL                                                                 0x1fce
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fcf
+#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fd0
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX4_AUX_GTC_SYNC_STATUS                                                                  0x1fd1
+#define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX4_AUX_PHY_WAKE_CNTL                                                                    0x1fd6
+#define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dout_i2c_dispdec
+// base address: 0x0
+#define regDC_I2C_CONTROL                                                                               0x1e98
+#define regDC_I2C_CONTROL_BASE_IDX                                                                      2
+#define regDC_I2C_ARBITRATION                                                                           0x1e99
+#define regDC_I2C_ARBITRATION_BASE_IDX                                                                  2
+#define regDC_I2C_INTERRUPT_CONTROL                                                                     0x1e9a
+#define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX                                                            2
+#define regDC_I2C_SW_STATUS                                                                             0x1e9b
+#define regDC_I2C_SW_STATUS_BASE_IDX                                                                    2
+#define regDC_I2C_DDC1_HW_STATUS                                                                        0x1e9c
+#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC2_HW_STATUS                                                                        0x1e9d
+#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC3_HW_STATUS                                                                        0x1e9e
+#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC4_HW_STATUS                                                                        0x1e9f
+#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC5_HW_STATUS                                                                        0x1ea0
+#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC1_SPEED                                                                            0x1ea2
+#define regDC_I2C_DDC1_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC1_SETUP                                                                            0x1ea3
+#define regDC_I2C_DDC1_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC2_SPEED                                                                            0x1ea4
+#define regDC_I2C_DDC2_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC2_SETUP                                                                            0x1ea5
+#define regDC_I2C_DDC2_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC3_SPEED                                                                            0x1ea6
+#define regDC_I2C_DDC3_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC3_SETUP                                                                            0x1ea7
+#define regDC_I2C_DDC3_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC4_SPEED                                                                            0x1ea8
+#define regDC_I2C_DDC4_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC4_SETUP                                                                            0x1ea9
+#define regDC_I2C_DDC4_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC5_SPEED                                                                            0x1eaa
+#define regDC_I2C_DDC5_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC5_SETUP                                                                            0x1eab
+#define regDC_I2C_DDC5_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_TRANSACTION0                                                                          0x1eae
+#define regDC_I2C_TRANSACTION0_BASE_IDX                                                                 2
+#define regDC_I2C_TRANSACTION1                                                                          0x1eaf
+#define regDC_I2C_TRANSACTION1_BASE_IDX                                                                 2
+#define regDC_I2C_TRANSACTION2                                                                          0x1eb0
+#define regDC_I2C_TRANSACTION2_BASE_IDX                                                                 2
+#define regDC_I2C_TRANSACTION3                                                                          0x1eb1
+#define regDC_I2C_TRANSACTION3_BASE_IDX                                                                 2
+#define regDC_I2C_DATA                                                                                  0x1eb2
+#define regDC_I2C_DATA_BASE_IDX                                                                         2
+#define regDC_I2C_EDID_DETECT_CTRL                                                                      0x1eb6
+#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX                                                             2
+#define regDC_I2C_READ_REQUEST_INTERRUPT                                                                0x1eb7
+#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX                                                       2
+
+
+// addressBlock: dce_dc_dio_dio_misc_dispdec
+// base address: 0x0
+#define regDIO_SCRATCH0                                                                                 0x1eca
+#define regDIO_SCRATCH0_BASE_IDX                                                                        2
+#define regDIO_SCRATCH1                                                                                 0x1ecb
+#define regDIO_SCRATCH1_BASE_IDX                                                                        2
+#define regDIO_SCRATCH2                                                                                 0x1ecc
+#define regDIO_SCRATCH2_BASE_IDX                                                                        2
+#define regDIO_SCRATCH3                                                                                 0x1ecd
+#define regDIO_SCRATCH3_BASE_IDX                                                                        2
+#define regDIO_SCRATCH4                                                                                 0x1ece
+#define regDIO_SCRATCH4_BASE_IDX                                                                        2
+#define regDIO_SCRATCH5                                                                                 0x1ecf
+#define regDIO_SCRATCH5_BASE_IDX                                                                        2
+#define regDIO_SCRATCH6                                                                                 0x1ed0
+#define regDIO_SCRATCH6_BASE_IDX                                                                        2
+#define regDIO_SCRATCH7                                                                                 0x1ed1
+#define regDIO_SCRATCH7_BASE_IDX                                                                        2
+#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS                                                          0x1ed3
+#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS_BASE_IDX                                                 2
+#define regDIO_MEM_PWR_STATUS                                                                           0x1edd
+#define regDIO_MEM_PWR_STATUS_BASE_IDX                                                                  2
+#define regDIO_MEM_PWR_CTRL                                                                             0x1ede
+#define regDIO_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define regDIO_MEM_PWR_CTRL2                                                                            0x1edf
+#define regDIO_MEM_PWR_CTRL2_BASE_IDX                                                                   2
+#define regDIO_CLK_CNTL                                                                                 0x1ee0
+#define regDIO_CLK_CNTL_BASE_IDX                                                                        2
+#define regDIO_POWER_MANAGEMENT_CNTL                                                                    0x1ee4
+#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX                                                           2
+#define regDIG_SOFT_RESET                                                                               0x1eee
+#define regDIG_SOFT_RESET_BASE_IDX                                                                      2
+#define regDIO_CLK_CNTL2                                                                                0x1ef2
+#define regDIO_CLK_CNTL2_BASE_IDX                                                                       2
+#define regDIO_CLK_CNTL3                                                                                0x1ef3
+#define regDIO_CLK_CNTL3_BASE_IDX                                                                       2
+#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL                                                              0x1eff
+#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX                                                     2
+#define regDIO_LINKA_CNTL                                                                               0x1f04
+#define regDIO_LINKA_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKB_CNTL                                                                               0x1f05
+#define regDIO_LINKB_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKC_CNTL                                                                               0x1f06
+#define regDIO_LINKC_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKD_CNTL                                                                               0x1f07
+#define regDIO_LINKD_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKE_CNTL                                                                               0x1f08
+#define regDIO_LINKE_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKF_CNTL                                                                               0x1f09
+#define regDIO_LINKF_CNTL_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_dcio_dcio_dispdec
+// base address: 0x0
+#define regDC_GENERICA                                                                                  0x2868
+#define regDC_GENERICA_BASE_IDX                                                                         2
+#define regDC_GENERICB                                                                                  0x2869
+#define regDC_GENERICB_BASE_IDX                                                                         2
+#define regDCIO_CLOCK_CNTL                                                                              0x286a
+#define regDCIO_CLOCK_CNTL_BASE_IDX                                                                     2
+#define regDC_REF_CLK_CNTL                                                                              0x286b
+#define regDC_REF_CLK_CNTL_BASE_IDX                                                                     2
+#define regUNIPHYA_LINK_CNTL                                                                            0x286d
+#define regUNIPHYA_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYA_CHANNEL_XBAR_CNTL                                                                    0x286e
+#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYB_LINK_CNTL                                                                            0x286f
+#define regUNIPHYB_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYB_CHANNEL_XBAR_CNTL                                                                    0x2870
+#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYC_LINK_CNTL                                                                            0x2871
+#define regUNIPHYC_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYC_CHANNEL_XBAR_CNTL                                                                    0x2872
+#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYD_LINK_CNTL                                                                            0x2873
+#define regUNIPHYD_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYD_CHANNEL_XBAR_CNTL                                                                    0x2874
+#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYE_LINK_CNTL                                                                            0x2875
+#define regUNIPHYE_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYE_CHANNEL_XBAR_CNTL                                                                    0x2876
+#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regDCIO_WRCMD_DELAY                                                                             0x287e
+#define regDCIO_WRCMD_DELAY_BASE_IDX                                                                    2
+#define regDC_PINSTRAPS                                                                                 0x2880
+#define regDC_PINSTRAPS_BASE_IDX                                                                        2
+#define regDCIO_SPARE                                                                                   0x2882
+#define regDCIO_SPARE_BASE_IDX                                                                          2
+#define regINTERCEPT_STATE                                                                              0x2884
+#define regINTERCEPT_STATE_BASE_IDX                                                                     2
+#define regDCIO_PATTERN_GEN_PAT                                                                         0x2886
+#define regDCIO_PATTERN_GEN_PAT_BASE_IDX                                                                2
+#define regDCIO_PATTERN_GEN_EN                                                                          0x2887
+#define regDCIO_PATTERN_GEN_EN_BASE_IDX                                                                 2
+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL                                                             0x288b
+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX                                                    2
+#define regDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c
+#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2
+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL                                                                   0x288d
+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX                                                          2
+#define regDCIO_SOFT_RESET                                                                              0x289e
+#define regDCIO_SOFT_RESET_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_dcio_dcio_chip_dispdec
+// base address: 0x0
+#define regDC_GPIO_GENERIC_MASK                                                                         0x28c8
+#define regDC_GPIO_GENERIC_MASK_BASE_IDX                                                                2
+#define regDC_GPIO_GENERIC_A                                                                            0x28c9
+#define regDC_GPIO_GENERIC_A_BASE_IDX                                                                   2
+#define regDC_GPIO_GENERIC_EN                                                                           0x28ca
+#define regDC_GPIO_GENERIC_EN_BASE_IDX                                                                  2
+#define regDC_GPIO_GENERIC_Y                                                                            0x28cb
+#define regDC_GPIO_GENERIC_Y_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC1_MASK                                                                            0x28d0
+#define regDC_GPIO_DDC1_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC1_A                                                                               0x28d1
+#define regDC_GPIO_DDC1_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC1_EN                                                                              0x28d2
+#define regDC_GPIO_DDC1_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC1_Y                                                                               0x28d3
+#define regDC_GPIO_DDC1_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC2_MASK                                                                            0x28d4
+#define regDC_GPIO_DDC2_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC2_A                                                                               0x28d5
+#define regDC_GPIO_DDC2_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC2_EN                                                                              0x28d6
+#define regDC_GPIO_DDC2_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC2_Y                                                                               0x28d7
+#define regDC_GPIO_DDC2_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC3_MASK                                                                            0x28d8
+#define regDC_GPIO_DDC3_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC3_A                                                                               0x28d9
+#define regDC_GPIO_DDC3_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC3_EN                                                                              0x28da
+#define regDC_GPIO_DDC3_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC3_Y                                                                               0x28db
+#define regDC_GPIO_DDC3_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC4_MASK                                                                            0x28dc
+#define regDC_GPIO_DDC4_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC4_A                                                                               0x28dd
+#define regDC_GPIO_DDC4_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC4_EN                                                                              0x28de
+#define regDC_GPIO_DDC4_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC4_Y                                                                               0x28df
+#define regDC_GPIO_DDC4_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC5_MASK                                                                            0x28e0
+#define regDC_GPIO_DDC5_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC5_A                                                                               0x28e1
+#define regDC_GPIO_DDC5_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC5_EN                                                                              0x28e2
+#define regDC_GPIO_DDC5_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC5_Y                                                                               0x28e3
+#define regDC_GPIO_DDC5_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDCVGA_MASK                                                                          0x28e8
+#define regDC_GPIO_DDCVGA_MASK_BASE_IDX                                                                 2
+#define regDC_GPIO_DDCVGA_A                                                                             0x28e9
+#define regDC_GPIO_DDCVGA_A_BASE_IDX                                                                    2
+#define regDC_GPIO_DDCVGA_EN                                                                            0x28ea
+#define regDC_GPIO_DDCVGA_EN_BASE_IDX                                                                   2
+#define regDC_GPIO_DDCVGA_Y                                                                             0x28eb
+#define regDC_GPIO_DDCVGA_Y_BASE_IDX                                                                    2
+#define regDC_GPIO_GENLK_MASK                                                                           0x28f0
+#define regDC_GPIO_GENLK_MASK_BASE_IDX                                                                  2
+#define regDC_GPIO_GENLK_A                                                                              0x28f1
+#define regDC_GPIO_GENLK_A_BASE_IDX                                                                     2
+#define regDC_GPIO_GENLK_EN                                                                             0x28f2
+#define regDC_GPIO_GENLK_EN_BASE_IDX                                                                    2
+#define regDC_GPIO_GENLK_Y                                                                              0x28f3
+#define regDC_GPIO_GENLK_Y_BASE_IDX                                                                     2
+#define regDC_GPIO_HPD_MASK                                                                             0x28f4
+#define regDC_GPIO_HPD_MASK_BASE_IDX                                                                    2
+#define regDC_GPIO_HPD_A                                                                                0x28f5
+#define regDC_GPIO_HPD_A_BASE_IDX                                                                       2
+#define regDC_GPIO_HPD_EN                                                                               0x28f6
+#define regDC_GPIO_HPD_EN_BASE_IDX                                                                      2
+#define regDC_GPIO_HPD_Y                                                                                0x28f7
+#define regDC_GPIO_HPD_Y_BASE_IDX                                                                       2
+#define regDC_GPIO_DRIVE_STRENGTH_S0                                                                    0x28f8
+#define regDC_GPIO_DRIVE_STRENGTH_S0_BASE_IDX                                                           2
+#define regDC_GPIO_DRIVE_STRENGTH_S1                                                                    0x28f9
+#define regDC_GPIO_DRIVE_STRENGTH_S1_BASE_IDX                                                           2
+#define regDC_GPIO_PWRSEQ0_EN                                                                           0x28fa
+#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX                                                                  2
+#define regDC_GPIO_PAD_STRENGTH_1                                                                       0x28fc
+#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX                                                              2
+#define regDC_GPIO_PAD_STRENGTH_2                                                                       0x28fd
+#define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX                                                              2
+#define regPHY_AUX_CNTL                                                                                 0x28ff
+#define regPHY_AUX_CNTL_BASE_IDX                                                                        2
+#define regDC_GPIO_DRIVE_TXIMPSEL                                                                       0x2900
+#define regDC_GPIO_DRIVE_TXIMPSEL_BASE_IDX                                                              2
+#define regDC_GPIO_TX12_EN                                                                              0x2915
+#define regDC_GPIO_TX12_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_AUX_CTRL_0                                                                           0x2916
+#define regDC_GPIO_AUX_CTRL_0_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_1                                                                           0x2917
+#define regDC_GPIO_AUX_CTRL_1_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_2                                                                           0x2918
+#define regDC_GPIO_AUX_CTRL_2_BASE_IDX                                                                  2
+#define regDC_GPIO_RXEN                                                                                 0x2919
+#define regDC_GPIO_RXEN_BASE_IDX                                                                        2
+#define regDC_GPIO_PULLUPEN                                                                             0x291a
+#define regDC_GPIO_PULLUPEN_BASE_IDX                                                                    2
+#define regDC_GPIO_AUX_CTRL_3                                                                           0x291b
+#define regDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_4                                                                           0x291c
+#define regDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_5                                                                           0x291d
+#define regDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2
+#define regAUXI2C_PAD_ALL_PWR_OK                                                                        0x291e
+#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec
+// base address: 0x0
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2928
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2929
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x292a
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x292b
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x292c
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x292d
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x292e
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x292f
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2930
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2931
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2932
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2933
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2934
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2935
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2936
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2937
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2938
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2939
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x293a
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x293b
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x293c
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x293d
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x293e
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x293f
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2940
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2941
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2942
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2943
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2944
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2945
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2946
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2947
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2948
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2949
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x294a
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x294b
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x294c
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x294d
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x294e
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x294f
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2950
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2951
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2952
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2953
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2954
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2955
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2956
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2957
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2958
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2959
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x295a
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x295b
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x295c
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x295d
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x295e
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x295f
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2960
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2961
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec
+// base address: 0x360
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2a00
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2a01
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2a02
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2a03
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2a04
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2a05
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2a06
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2a07
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2a08
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2a09
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2a0a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2a0b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2a0c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2a0d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2a0e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2a0f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2a10
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2a11
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2a12
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2a13
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2a14
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2a15
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2a16
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2a17
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2a18
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2a19
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2a1a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2a1b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2a1c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2a1d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2a1e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2a1f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2a20
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2a21
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2a22
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2a23
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2a24
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2a25
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2a26
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2a27
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2a28
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2a29
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2a2a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2a2b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2a2c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2a2d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2a2e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2a2f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2a30
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2a31
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2a32
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2a33
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2a34
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2a35
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2a36
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2a37
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2a38
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2a39
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec
+// base address: 0x6c0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2ad8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2ad9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2ada
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2adb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2adc
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2add
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2ade
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2adf
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2ae0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2ae1
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2ae2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2ae3
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2ae4
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2ae5
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2ae6
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2ae7
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2ae8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2ae9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2aea
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2aeb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2aec
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2aed
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2aee
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2aef
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2af0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2af1
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2af2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2af3
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2af4
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2af5
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2af6
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2af7
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2af8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2af9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2afa
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2afb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2afc
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2afd
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2afe
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2aff
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2b00
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2b01
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2b02
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2b03
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2b04
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2b05
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2b06
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2b07
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2b08
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2b09
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2b0a
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2b0b
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2b0c
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2b0d
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2b0e
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2b0f
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2b10
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2b11
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec
+// base address: 0xa20
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2bb0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2bb1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2bb2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2bb3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2bb4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2bb5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2bb6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2bb7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2bb8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2bb9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2bba
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2bbb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2bbc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2bbd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2bbe
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2bbf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2bc0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2bc1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2bc2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2bc3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2bc4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2bc5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2bc6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2bc7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2bc8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2bc9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2bca
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2bcb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2bcc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2bcd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2bce
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2bcf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2bd0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2bd1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2bd2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2bd3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2bd4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2bd5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2bd6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2bd7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2bd8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2bd9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2bda
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2bdb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2bdc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2bdd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2bde
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2bdf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2be0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2be1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2be2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2be3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2be4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2be5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2be6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2be7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2be8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2be9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec
+// base address: 0xd80
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2c88
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2c89
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2c8a
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2c8b
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2c8c
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2c8d
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2c8e
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2c8f
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2c90
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2c91
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2c92
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2c93
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2c94
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2c95
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2c96
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2c97
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2c98
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2c99
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2c9a
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2c9b
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2c9c
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2c9d
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2c9e
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2c9f
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2ca0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2ca1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2ca2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2ca3
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2ca4
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2ca5
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2ca6
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2ca7
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2ca8
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2ca9
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2caa
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2cab
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2cac
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2cad
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2cae
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2caf
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2cb0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2cb1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2cb2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2cb3
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2cb4
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2cb5
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2cb6
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2cb7
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2cb8
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2cb9
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2cba
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2cbb
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2cbc
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2cbd
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2cbe
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2cbf
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2cc0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2cc1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec
+// base address: 0x0
+#define regDC_GPIO_PWRSEQ_EN                                                                            0x2f10
+#define regDC_GPIO_PWRSEQ_EN_BASE_IDX                                                                   2
+#define regDC_GPIO_PWRSEQ_CTRL                                                                          0x2f11
+#define regDC_GPIO_PWRSEQ_CTRL_BASE_IDX                                                                 2
+#define regDC_GPIO_PWRSEQ_MASK                                                                          0x2f12
+#define regDC_GPIO_PWRSEQ_MASK_BASE_IDX                                                                 2
+#define regDC_GPIO_PWRSEQ_A_Y                                                                           0x2f13
+#define regDC_GPIO_PWRSEQ_A_Y_BASE_IDX                                                                  2
+#define regPANEL_PWRSEQ_CNTL                                                                            0x2f14
+#define regPANEL_PWRSEQ_CNTL_BASE_IDX                                                                   2
+#define regPANEL_PWRSEQ_STATE                                                                           0x2f15
+#define regPANEL_PWRSEQ_STATE_BASE_IDX                                                                  2
+#define regPANEL_PWRSEQ_DELAY1                                                                          0x2f16
+#define regPANEL_PWRSEQ_DELAY1_BASE_IDX                                                                 2
+#define regPANEL_PWRSEQ_DELAY2                                                                          0x2f17
+#define regPANEL_PWRSEQ_DELAY2_BASE_IDX                                                                 2
+#define regPANEL_PWRSEQ_REF_DIV1                                                                        0x2f18
+#define regPANEL_PWRSEQ_REF_DIV1_BASE_IDX                                                               2
+#define regBL_PWM_CNTL                                                                                  0x2f19
+#define regBL_PWM_CNTL_BASE_IDX                                                                         2
+#define regBL_PWM_CNTL2                                                                                 0x2f1a
+#define regBL_PWM_CNTL2_BASE_IDX                                                                        2
+#define regBL_PWM_PERIOD_CNTL                                                                           0x2f1b
+#define regBL_PWM_PERIOD_CNTL_BASE_IDX                                                                  2
+#define regBL_PWM_GRP1_REG_LOCK                                                                         0x2f1c
+#define regBL_PWM_GRP1_REG_LOCK_BASE_IDX                                                                2
+#define regPANEL_PWRSEQ_REF_DIV2                                                                        0x2f1d
+#define regPANEL_PWRSEQ_REF_DIV2_BASE_IDX                                                               2
+#define regPWRSEQ_SPARE                                                                                 0x2f21
+#define regPWRSEQ_SPARE_BASE_IDX                                                                        2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
+// base address: 0x0
+#define regDSCC0_DSCC_CONFIG0                                                                           0x300a
+#define regDSCC0_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC0_DSCC_CONFIG1                                                                           0x300b
+#define regDSCC0_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC0_DSCC_STATUS                                                                            0x300c
+#define regDSCC0_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x300d
+#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC0_DSCC_PPS_CONFIG0                                                                       0x300e
+#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG1                                                                       0x300f
+#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG2                                                                       0x3010
+#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG3                                                                       0x3011
+#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG4                                                                       0x3012
+#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG5                                                                       0x3013
+#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG6                                                                       0x3014
+#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG7                                                                       0x3015
+#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG8                                                                       0x3016
+#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG9                                                                       0x3017
+#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG10                                                                      0x3018
+#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG11                                                                      0x3019
+#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG12                                                                      0x301a
+#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG13                                                                      0x301b
+#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG14                                                                      0x301c
+#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG15                                                                      0x301d
+#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG16                                                                      0x301e
+#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG17                                                                      0x301f
+#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG18                                                                      0x3020
+#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG19                                                                      0x3021
+#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG20                                                                      0x3022
+#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG21                                                                      0x3023
+#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG22                                                                      0x3024
+#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC0_DSCC_MEM_POWER_CONTROL                                                                 0x3025
+#define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3026
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3027
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3028
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3029
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x302a
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x302b
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_MAX_ABS_ERROR0                                                                    0x302c
+#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC0_DSCC_MAX_ABS_ERROR1                                                                    0x302d
+#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x302e
+#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x302f
+#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3030
+#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3031
+#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3032
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3033
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3034
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
+// base address: 0x0
+#define regDSCCIF0_DSCCIF_CONFIG0                                                                       0x3005
+#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF0_DSCCIF_CONFIG1                                                                       0x3006
+#define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
+// base address: 0x0
+#define regDSC_TOP0_DSC_TOP_CONTROL                                                                     0x3000
+#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP0_DSC_DEBUG_CONTROL                                                                   0x3001
+#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
+// base address: 0x170
+#define regDSCC1_DSCC_CONFIG0                                                                           0x3066
+#define regDSCC1_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC1_DSCC_CONFIG1                                                                           0x3067
+#define regDSCC1_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC1_DSCC_STATUS                                                                            0x3068
+#define regDSCC1_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3069
+#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC1_DSCC_PPS_CONFIG0                                                                       0x306a
+#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG1                                                                       0x306b
+#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG2                                                                       0x306c
+#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG3                                                                       0x306d
+#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG4                                                                       0x306e
+#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG5                                                                       0x306f
+#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG6                                                                       0x3070
+#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG7                                                                       0x3071
+#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG8                                                                       0x3072
+#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG9                                                                       0x3073
+#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG10                                                                      0x3074
+#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG11                                                                      0x3075
+#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG12                                                                      0x3076
+#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG13                                                                      0x3077
+#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG14                                                                      0x3078
+#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG15                                                                      0x3079
+#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG16                                                                      0x307a
+#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG17                                                                      0x307b
+#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG18                                                                      0x307c
+#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG19                                                                      0x307d
+#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG20                                                                      0x307e
+#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG21                                                                      0x307f
+#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG22                                                                      0x3080
+#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC1_DSCC_MEM_POWER_CONTROL                                                                 0x3081
+#define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3082
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3083
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3084
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3085
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x3086
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x3087
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_MAX_ABS_ERROR0                                                                    0x3088
+#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC1_DSCC_MAX_ABS_ERROR1                                                                    0x3089
+#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x308a
+#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x308b
+#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x308c
+#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x308d
+#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x308e
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x308f
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3090
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
+// base address: 0x170
+#define regDSCCIF1_DSCCIF_CONFIG0                                                                       0x3061
+#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF1_DSCCIF_CONFIG1                                                                       0x3062
+#define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
+// base address: 0x170
+#define regDSC_TOP1_DSC_TOP_CONTROL                                                                     0x305c
+#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP1_DSC_DEBUG_CONTROL                                                                   0x305d
+#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
+// base address: 0x2e0
+#define regDSCC2_DSCC_CONFIG0                                                                           0x30c2
+#define regDSCC2_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC2_DSCC_CONFIG1                                                                           0x30c3
+#define regDSCC2_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC2_DSCC_STATUS                                                                            0x30c4
+#define regDSCC2_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x30c5
+#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC2_DSCC_PPS_CONFIG0                                                                       0x30c6
+#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG1                                                                       0x30c7
+#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG2                                                                       0x30c8
+#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG3                                                                       0x30c9
+#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG4                                                                       0x30ca
+#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG5                                                                       0x30cb
+#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG6                                                                       0x30cc
+#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG7                                                                       0x30cd
+#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG8                                                                       0x30ce
+#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG9                                                                       0x30cf
+#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG10                                                                      0x30d0
+#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG11                                                                      0x30d1
+#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG12                                                                      0x30d2
+#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG13                                                                      0x30d3
+#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG14                                                                      0x30d4
+#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG15                                                                      0x30d5
+#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG16                                                                      0x30d6
+#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG17                                                                      0x30d7
+#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG18                                                                      0x30d8
+#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG19                                                                      0x30d9
+#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG20                                                                      0x30da
+#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG21                                                                      0x30db
+#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG22                                                                      0x30dc
+#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC2_DSCC_MEM_POWER_CONTROL                                                                 0x30dd
+#define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x30de
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x30df
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x30e0
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x30e1
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x30e2
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x30e3
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_MAX_ABS_ERROR0                                                                    0x30e4
+#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC2_DSCC_MAX_ABS_ERROR1                                                                    0x30e5
+#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x30e6
+#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x30e7
+#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x30e8
+#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x30e9
+#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x30ea
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x30eb
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x30ec
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x30ed
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
+// base address: 0x2e0
+#define regDSCCIF2_DSCCIF_CONFIG0                                                                       0x30bd
+#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF2_DSCCIF_CONFIG1                                                                       0x30be
+#define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
+// base address: 0x2e0
+#define regDSC_TOP2_DSC_TOP_CONTROL                                                                     0x30b8
+#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP2_DSC_DEBUG_CONTROL                                                                   0x30b9
+#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec
+// base address: 0x450
+#define regDSCC3_DSCC_CONFIG0                                                                           0x311e
+#define regDSCC3_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC3_DSCC_CONFIG1                                                                           0x311f
+#define regDSCC3_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC3_DSCC_STATUS                                                                            0x3120
+#define regDSCC3_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3121
+#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC3_DSCC_PPS_CONFIG0                                                                       0x3122
+#define regDSCC3_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG1                                                                       0x3123
+#define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG2                                                                       0x3124
+#define regDSCC3_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG3                                                                       0x3125
+#define regDSCC3_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG4                                                                       0x3126
+#define regDSCC3_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG5                                                                       0x3127
+#define regDSCC3_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG6                                                                       0x3128
+#define regDSCC3_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG7                                                                       0x3129
+#define regDSCC3_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG8                                                                       0x312a
+#define regDSCC3_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG9                                                                       0x312b
+#define regDSCC3_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG10                                                                      0x312c
+#define regDSCC3_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG11                                                                      0x312d
+#define regDSCC3_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG12                                                                      0x312e
+#define regDSCC3_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG13                                                                      0x312f
+#define regDSCC3_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG14                                                                      0x3130
+#define regDSCC3_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG15                                                                      0x3131
+#define regDSCC3_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG16                                                                      0x3132
+#define regDSCC3_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG17                                                                      0x3133
+#define regDSCC3_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG18                                                                      0x3134
+#define regDSCC3_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG19                                                                      0x3135
+#define regDSCC3_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG20                                                                      0x3136
+#define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG21                                                                      0x3137
+#define regDSCC3_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG22                                                                      0x3138
+#define regDSCC3_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC3_DSCC_MEM_POWER_CONTROL                                                                 0x3139
+#define regDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x313a
+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x313b
+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x313c
+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x313d
+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x313e
+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x313f
+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC3_DSCC_MAX_ABS_ERROR0                                                                    0x3140
+#define regDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC3_DSCC_MAX_ABS_ERROR1                                                                    0x3141
+#define regDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x3142
+#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x3143
+#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3144
+#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3145
+#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3146
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3147
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3148
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3149
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+
+
+// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec
+// base address: 0x450
+#define regDSCCIF3_DSCCIF_CONFIG0                                                                       0x3119
+#define regDSCCIF3_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF3_DSCCIF_CONFIG1                                                                       0x311a
+#define regDSCCIF3_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec
+// base address: 0x450
+#define regDSC_TOP3_DSC_TOP_CONTROL                                                                     0x3114
+#define regDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP3_DSC_DEBUG_CONTROL                                                                   0x3115
+#define regDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_hpo_hpo_top_dispdec
+// base address: 0x2790c
+#define regHPO_TOP_CLOCK_CONTROL                                                                        0x0e43
+#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX                                                               3
+#define regHPO_TOP_HW_CONTROL                                                                           0x0e4a
+#define regHPO_TOP_HW_CONTROL_BASE_IDX                                                                  3
+
+
+// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec
+// base address: 0x27958
+#define regDP_STREAM_MAPPER_CONTROL0                                                                    0x0e56
+#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX                                                           3
+#define regDP_STREAM_MAPPER_CONTROL1                                                                    0x0e57
+#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX                                                           3
+#define regDP_STREAM_MAPPER_CONTROL2                                                                    0x0e58
+#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX                                                           3
+#define regDP_STREAM_MAPPER_CONTROL3                                                                    0x0e59
+#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX                                                           3
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec
+// base address: 0x2646c
+#define regAFMT5_AFMT_VBI_PACKET_CONTROL                                                                0x091c
+#define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       3
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2                                                             0x091d
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    3
+#define regAFMT5_AFMT_AUDIO_INFO0                                                                       0x091e
+#define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX                                                              3
+#define regAFMT5_AFMT_AUDIO_INFO1                                                                       0x091f
+#define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX                                                              3
+#define regAFMT5_AFMT_60958_0                                                                           0x0920
+#define regAFMT5_AFMT_60958_0_BASE_IDX                                                                  3
+#define regAFMT5_AFMT_60958_1                                                                           0x0921
+#define regAFMT5_AFMT_60958_1_BASE_IDX                                                                  3
+#define regAFMT5_AFMT_AUDIO_CRC_CONTROL                                                                 0x0922
+#define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        3
+#define regAFMT5_AFMT_RAMP_CONTROL0                                                                     0x0923
+#define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX                                                            3
+#define regAFMT5_AFMT_RAMP_CONTROL1                                                                     0x0924
+#define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX                                                            3
+#define regAFMT5_AFMT_RAMP_CONTROL2                                                                     0x0925
+#define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX                                                            3
+#define regAFMT5_AFMT_RAMP_CONTROL3                                                                     0x0926
+#define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX                                                            3
+#define regAFMT5_AFMT_60958_2                                                                           0x0927
+#define regAFMT5_AFMT_60958_2_BASE_IDX                                                                  3
+#define regAFMT5_AFMT_AUDIO_CRC_RESULT                                                                  0x0928
+#define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         3
+#define regAFMT5_AFMT_STATUS                                                                            0x0929
+#define regAFMT5_AFMT_STATUS_BASE_IDX                                                                   3
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL                                                              0x092a
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     3
+#define regAFMT5_AFMT_INFOFRAME_CONTROL0                                                                0x092b
+#define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       3
+#define regAFMT5_AFMT_INTERRUPT_STATUS                                                                  0x092c
+#define regAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         3
+#define regAFMT5_AFMT_AUDIO_SRC_CONTROL                                                                 0x092d
+#define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        3
+#define regAFMT5_AFMT_MEM_PWR                                                                           0x092f
+#define regAFMT5_AFMT_MEM_PWR_BASE_IDX                                                                  3
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec
+// base address: 0x264f0
+#define regDME5_DME_CONTROL                                                                             0x093c
+#define regDME5_DME_CONTROL_BASE_IDX                                                                    3
+#define regDME5_DME_MEMORY_CONTROL                                                                      0x093d
+#define regDME5_DME_MEMORY_CONTROL_BASE_IDX                                                             3
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec
+// base address: 0x264c4
+#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x0931
+#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 3
+#define regVPG5_VPG_GENERIC_PACKET_DATA                                                                 0x0932
+#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        3
+#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x0933
+#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      3
+#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x0934
+#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  3
+#define regVPG5_VPG_GENERIC_STATUS                                                                      0x0935
+#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX                                                             3
+#define regVPG5_VPG_MEM_PWR                                                                             0x0936
+#define regVPG5_VPG_MEM_PWR_BASE_IDX                                                                    3
+#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x0937
+#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        3
+#define regVPG5_VPG_ISRC1_2_DATA                                                                        0x0938
+#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX                                                               3
+#define regVPG5_VPG_MPEG_INFO0                                                                          0x0939
+#define regVPG5_VPG_MPEG_INFO0_BASE_IDX                                                                 3
+#define regVPG5_VPG_MPEG_INFO1                                                                          0x093a
+#define regVPG5_VPG_MPEG_INFO1_BASE_IDX                                                                 3
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec
+// base address: 0x1ab8c
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x3623
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x3624
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x3625
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x3626
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x3627
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE                                                           0x3628
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec
+// base address: 0x1abc0
+#define regAPG0_APG_CONTROL                                                                             0x3630
+#define regAPG0_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG0_APG_CONTROL2                                                                            0x3631
+#define regAPG0_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG0_APG_DBG_GEN_CONTROL                                                                     0x3632
+#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG0_APG_PACKET_CONTROL                                                                      0x3633
+#define regAPG0_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG0_APG_AUDIO_CRC_CONTROL                                                                   0x363a
+#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG0_APG_AUDIO_CRC_CONTROL2                                                                  0x363b
+#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG0_APG_AUDIO_CRC_RESULT                                                                    0x363c
+#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG0_APG_STATUS                                                                              0x3641
+#define regAPG0_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG0_APG_STATUS2                                                                             0x3642
+#define regAPG0_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG0_APG_MEM_PWR                                                                             0x3644
+#define regAPG0_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG0_APG_SPARE                                                                               0x3646
+#define regAPG0_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec
+// base address: 0x1ac38
+#define regDME6_DME_CONTROL                                                                             0x364e
+#define regDME6_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME6_DME_MEMORY_CONTROL                                                                      0x364f
+#define regDME6_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec
+// base address: 0x1ac44
+#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x3651
+#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG6_VPG_GENERIC_PACKET_DATA                                                                 0x3652
+#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x3653
+#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x3654
+#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG6_VPG_GENERIC_STATUS                                                                      0x3655
+#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG6_VPG_MEM_PWR                                                                             0x3656
+#define regVPG6_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x3657
+#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG6_VPG_ISRC1_2_DATA                                                                        0x3658
+#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG6_VPG_MPEG_INFO0                                                                          0x3659
+#define regVPG6_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG6_VPG_MPEG_INFO1                                                                          0x365a
+#define regVPG6_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec
+// base address: 0x1ac74
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL                                                           0x365d
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x365e
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x365f
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3660
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3661
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0                                                          0x3662
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1                                                          0x3663
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2                                                          0x3664
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3                                                          0x3665
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4                                                          0x3666
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5                                                          0x3667
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6                                                          0x3668
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7                                                          0x3669
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8                                                          0x366a
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x366b
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x366c
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x366d
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x366e
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x366f
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3670
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3671
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x3672
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x3673
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x3674
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x3675
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x3676
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x3677
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x3678
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x3679
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x367a
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL                                                       0x367b
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x367c
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x367d
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x367e
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x3683
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3684
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3685
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x3686
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x3687
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3688
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3689
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x368a
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x368b
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE                                                             0x368c
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec
+// base address: 0x1aedc
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x36f7
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x36f8
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x36f9
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x36fa
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x36fb
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE                                                           0x36fc
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec
+// base address: 0x1af10
+#define regAPG1_APG_CONTROL                                                                             0x3704
+#define regAPG1_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG1_APG_CONTROL2                                                                            0x3705
+#define regAPG1_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG1_APG_DBG_GEN_CONTROL                                                                     0x3706
+#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG1_APG_PACKET_CONTROL                                                                      0x3707
+#define regAPG1_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG1_APG_AUDIO_CRC_CONTROL                                                                   0x370e
+#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG1_APG_AUDIO_CRC_CONTROL2                                                                  0x370f
+#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG1_APG_AUDIO_CRC_RESULT                                                                    0x3710
+#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG1_APG_STATUS                                                                              0x3715
+#define regAPG1_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG1_APG_STATUS2                                                                             0x3716
+#define regAPG1_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG1_APG_MEM_PWR                                                                             0x3718
+#define regAPG1_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG1_APG_SPARE                                                                               0x371a
+#define regAPG1_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec
+// base address: 0x1af88
+#define regDME7_DME_CONTROL                                                                             0x3722
+#define regDME7_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME7_DME_MEMORY_CONTROL                                                                      0x3723
+#define regDME7_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec
+// base address: 0x1af94
+#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x3725
+#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG7_VPG_GENERIC_PACKET_DATA                                                                 0x3726
+#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x3727
+#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x3728
+#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG7_VPG_GENERIC_STATUS                                                                      0x3729
+#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG7_VPG_MEM_PWR                                                                             0x372a
+#define regVPG7_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x372b
+#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG7_VPG_ISRC1_2_DATA                                                                        0x372c
+#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG7_VPG_MPEG_INFO0                                                                          0x372d
+#define regVPG7_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG7_VPG_MPEG_INFO1                                                                          0x372e
+#define regVPG7_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec
+// base address: 0x1afc4
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL                                                           0x3731
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x3732
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x3733
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3734
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3735
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0                                                          0x3736
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1                                                          0x3737
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2                                                          0x3738
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3                                                          0x3739
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4                                                          0x373a
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5                                                          0x373b
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6                                                          0x373c
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7                                                          0x373d
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8                                                          0x373e
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x373f
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x3740
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x3741
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x3742
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x3743
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3744
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3745
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x3746
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x3747
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x3748
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x3749
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x374a
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x374b
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x374c
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x374d
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x374e
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL                                                       0x374f
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x3750
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x3751
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x3752
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x3757
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3758
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3759
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x375a
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x375b
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x375c
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x375d
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x375e
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x375f
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE                                                             0x3760
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec
+// base address: 0x1b22c
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x37cb
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x37cc
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x37cd
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x37ce
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x37cf
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE                                                           0x37d0
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec
+// base address: 0x1b260
+#define regAPG2_APG_CONTROL                                                                             0x37d8
+#define regAPG2_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG2_APG_CONTROL2                                                                            0x37d9
+#define regAPG2_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG2_APG_DBG_GEN_CONTROL                                                                     0x37da
+#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG2_APG_PACKET_CONTROL                                                                      0x37db
+#define regAPG2_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG2_APG_AUDIO_CRC_CONTROL                                                                   0x37e2
+#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG2_APG_AUDIO_CRC_CONTROL2                                                                  0x37e3
+#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG2_APG_AUDIO_CRC_RESULT                                                                    0x37e4
+#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG2_APG_STATUS                                                                              0x37e9
+#define regAPG2_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG2_APG_STATUS2                                                                             0x37ea
+#define regAPG2_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG2_APG_MEM_PWR                                                                             0x37ec
+#define regAPG2_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG2_APG_SPARE                                                                               0x37ee
+#define regAPG2_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec
+// base address: 0x1b2d8
+#define regDME8_DME_CONTROL                                                                             0x37f6
+#define regDME8_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME8_DME_MEMORY_CONTROL                                                                      0x37f7
+#define regDME8_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec
+// base address: 0x1b2e4
+#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x37f9
+#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG8_VPG_GENERIC_PACKET_DATA                                                                 0x37fa
+#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x37fb
+#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x37fc
+#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG8_VPG_GENERIC_STATUS                                                                      0x37fd
+#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG8_VPG_MEM_PWR                                                                             0x37fe
+#define regVPG8_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x37ff
+#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG8_VPG_ISRC1_2_DATA                                                                        0x3800
+#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG8_VPG_MPEG_INFO0                                                                          0x3801
+#define regVPG8_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG8_VPG_MPEG_INFO1                                                                          0x3802
+#define regVPG8_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec
+// base address: 0x1b314
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL                                                           0x3805
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x3806
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x3807
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3808
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3809
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0                                                          0x380a
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1                                                          0x380b
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2                                                          0x380c
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3                                                          0x380d
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4                                                          0x380e
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5                                                          0x380f
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6                                                          0x3810
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7                                                          0x3811
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8                                                          0x3812
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x3813
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x3814
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x3815
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x3816
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x3817
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3818
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3819
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x381a
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x381b
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x381c
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x381d
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x381e
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x381f
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x3820
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x3821
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x3822
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL                                                       0x3823
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x3824
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x3825
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x3826
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x382b
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x382c
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x382d
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x382e
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x382f
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3830
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3831
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x3832
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3833
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE                                                             0x3834
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec
+// base address: 0x1b57c
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x389f
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x38a0
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x38a1
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x38a2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x38a3
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE                                                           0x38a4
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec
+// base address: 0x1b5b0
+#define regAPG3_APG_CONTROL                                                                             0x38ac
+#define regAPG3_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG3_APG_CONTROL2                                                                            0x38ad
+#define regAPG3_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG3_APG_DBG_GEN_CONTROL                                                                     0x38ae
+#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG3_APG_PACKET_CONTROL                                                                      0x38af
+#define regAPG3_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG3_APG_AUDIO_CRC_CONTROL                                                                   0x38b6
+#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG3_APG_AUDIO_CRC_CONTROL2                                                                  0x38b7
+#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG3_APG_AUDIO_CRC_RESULT                                                                    0x38b8
+#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG3_APG_STATUS                                                                              0x38bd
+#define regAPG3_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG3_APG_STATUS2                                                                             0x38be
+#define regAPG3_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG3_APG_MEM_PWR                                                                             0x38c0
+#define regAPG3_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG3_APG_SPARE                                                                               0x38c2
+#define regAPG3_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec
+// base address: 0x1b628
+#define regDME9_DME_CONTROL                                                                             0x38ca
+#define regDME9_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME9_DME_MEMORY_CONTROL                                                                      0x38cb
+#define regDME9_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec
+// base address: 0x1b634
+#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x38cd
+#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG9_VPG_GENERIC_PACKET_DATA                                                                 0x38ce
+#define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x38cf
+#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x38d0
+#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG9_VPG_GENERIC_STATUS                                                                      0x38d1
+#define regVPG9_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG9_VPG_MEM_PWR                                                                             0x38d2
+#define regVPG9_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x38d3
+#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG9_VPG_ISRC1_2_DATA                                                                        0x38d4
+#define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG9_VPG_MPEG_INFO0                                                                          0x38d5
+#define regVPG9_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG9_VPG_MPEG_INFO1                                                                          0x38d6
+#define regVPG9_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec
+// base address: 0x1b664
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL                                                           0x38d9
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x38da
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x38db
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x38dc
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x38dd
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0                                                          0x38de
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1                                                          0x38df
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2                                                          0x38e0
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3                                                          0x38e1
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4                                                          0x38e2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5                                                          0x38e3
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6                                                          0x38e4
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7                                                          0x38e5
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8                                                          0x38e6
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x38e7
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x38e8
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x38e9
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x38ea
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x38eb
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x38ec
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x38ed
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x38ee
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x38ef
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x38f0
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x38f1
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x38f2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x38f3
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x38f4
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x38f5
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x38f6
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL                                                       0x38f7
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x38f8
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x38f9
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x38fa
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x38ff
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3900
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3901
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x3902
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x3903
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3904
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3905
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x3906
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3907
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE                                                             0x3908
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec
+// base address: 0x1ad5c
+#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL                                                       0x3697
+#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2
+#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE                                                               0x3698
+#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec
+// base address: 0x1ae00
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL                                                         0x36c0
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS                                                          0x36c1
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE                                                      0x36c4
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x36c5
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x36c6
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x36c7
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x36c8
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0                                                         0x36cb
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1                                                         0x36cc
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2                                                         0x36cd
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3                                                         0x36ce
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x36d1
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x36d2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x36d3
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x36d4
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG                                                       0x36d7
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x36d8
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x36d9
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x36da
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x36db
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x36dc
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x36dd
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x36de
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x36df
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x36e0
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x36e1
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x36e2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x36e3
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x36e4
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x36e5
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x36e6
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x36e7
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS                                                    0x36e8
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE                                                 0x36ea
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX                                        2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0                                                     0x36eb
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1                                                     0x36ec
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS                                                      0x36ed
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT                                                       0x36ee
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX                                              2
+
+
+// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec
+// base address: 0x1b0ac
+#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL                                                       0x376b
+#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2
+#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE                                                               0x376c
+#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec
+// base address: 0x1b150
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL                                                         0x3794
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS                                                          0x3795
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE                                                      0x3798
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x3799
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x379a
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x379b
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x379c
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0                                                         0x379f
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1                                                         0x37a0
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2                                                         0x37a1
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3                                                         0x37a2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x37a5
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x37a6
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x37a7
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x37a8
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG                                                       0x37ab
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x37ac
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x37ad
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x37ae
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x37af
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x37b0
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x37b1
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x37b2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x37b3
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x37b4
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x37b5
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x37b6
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x37b7
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x37b8
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x37b9
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x37ba
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x37bb
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS                                                    0x37bc
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE                                                 0x37be
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX                                        2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0                                                     0x37bf
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1                                                     0x37c0
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS                                                      0x37c1
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT                                                       0x37c2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX                                              2
+
+
+// addressBlock: dce_dc_hda_azcontroller_azdec
+// base address: 0x0
+#define regCORB_WRITE_POINTER                                                                           0x0000
+#define regCORB_WRITE_POINTER_BASE_IDX                                                                  0
+#define regCORB_READ_POINTER                                                                            0x0000
+#define regCORB_READ_POINTER_BASE_IDX                                                                   0
+#define regCORB_CONTROL                                                                                 0x0001
+#define regCORB_CONTROL_BASE_IDX                                                                        0
+#define regCORB_STATUS                                                                                  0x0001
+#define regCORB_STATUS_BASE_IDX                                                                         0
+#define regCORB_SIZE                                                                                    0x0001
+#define regCORB_SIZE_BASE_IDX                                                                           0
+#define regRIRB_LOWER_BASE_ADDRESS                                                                      0x0002
+#define regRIRB_LOWER_BASE_ADDRESS_BASE_IDX                                                             0
+#define regRIRB_UPPER_BASE_ADDRESS                                                                      0x0003
+#define regRIRB_UPPER_BASE_ADDRESS_BASE_IDX                                                             0
+#define regRIRB_WRITE_POINTER                                                                           0x0004
+#define regRIRB_WRITE_POINTER_BASE_IDX                                                                  0
+#define regRESPONSE_INTERRUPT_COUNT                                                                     0x0004
+#define regRESPONSE_INTERRUPT_COUNT_BASE_IDX                                                            0
+#define regRIRB_CONTROL                                                                                 0x0005
+#define regRIRB_CONTROL_BASE_IDX                                                                        0
+#define regRIRB_STATUS                                                                                  0x0005
+#define regRIRB_STATUS_BASE_IDX                                                                         0
+#define regRIRB_SIZE                                                                                    0x0005
+#define regRIRB_SIZE_BASE_IDX                                                                           0
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE                                                           0x0006
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX                                                  0
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                                      0x0006
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                             0
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                                     0x0006
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                            0
+#define regIMMEDIATE_RESPONSE_INPUT_INTERFACE                                                           0x0007
+#define regIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX                                                  0
+#define regIMMEDIATE_COMMAND_STATUS                                                                     0x0008
+#define regIMMEDIATE_COMMAND_STATUS_BASE_IDX                                                            0
+#define regDMA_POSITION_LOWER_BASE_ADDRESS                                                              0x000a
+#define regDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX                                                     0
+#define regDMA_POSITION_UPPER_BASE_ADDRESS                                                              0x000b
+#define regDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX                                                     0
+#define regWALL_CLOCK_COUNTER_ALIAS                                                                     0x074c
+#define regWALL_CLOCK_COUNTER_ALIAS_BASE_IDX                                                            1
+
+
+// addressBlock: dce_dc_hda_azendpoint_azdec
+// base address: 0x0
+#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                           0x0006
+#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                  0
+#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                          0x0006
+#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                 0
+
+
+// addressBlock: dce_dc_hda_azinputendpoint_azdec
+// base address: 0x0
+#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                                            0x0006
+#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX                                   0
+#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                                           0x0006
+#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX                                  0
+
+
+// addressBlock: dce_dc_hda_azroot_azdec
+// base address: 0x0
+#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                               0x0006
+#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                      0
+#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                              0x0006
+#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                     0
+
+
+// addressBlock: dce_dc_hda_azstream0_azdec
+// base address: 0x0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x000e
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x000f
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0010
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0011
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x0012
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x0012
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x0014
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x0015
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0761
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dce_dc_hda_azstream1_azdec
+// base address: 0x20
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x0016
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x0017
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0018
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0019
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x001a
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x001a
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x001c
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x001d
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0769
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dce_dc_hda_azstream2_azdec
+// base address: 0x40
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x001e
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x001f
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0020
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0021
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x0022
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x0022
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x0024
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x0025
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0771
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dce_dc_hda_azstream3_azdec
+// base address: 0x60
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x0026
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x0027
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0028
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0029
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x002a
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x002a
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x002c
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x002d
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0779
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dce_dc_hda_azstream4_azdec
+// base address: 0x80
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x002e
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x002f
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0030
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0031
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x0032
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x0032
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x0034
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x0035
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0781
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dce_dc_hda_azstream5_azdec
+// base address: 0xa0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x0036
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x0037
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0038
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0039
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x003a
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x003a
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x003c
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x003d
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0789
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dce_dc_hda_azstream6_azdec
+// base address: 0xc0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x003e
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x003f
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0040
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0041
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x0042
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x0042
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x0044
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x0045
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0791
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dce_dc_hda_azstream7_azdec
+// base address: 0xe0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x0046
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x0047
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0048
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0049
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x004a
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x004a
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x004c
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x004d
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0799
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: vga_vgaseqind
+// base address: 0x0
+#define ixSEQ00                                                                                        0x0000
+#define ixSEQ01                                                                                        0x0001
+#define ixSEQ02                                                                                        0x0002
+#define ixSEQ03                                                                                        0x0003
+#define ixSEQ04                                                                                        0x0004
+
+
+// addressBlock: vga_vgacrtind
+// base address: 0x0
+#define ixCRT00                                                                                        0x0000
+#define ixCRT01                                                                                        0x0001
+#define ixCRT02                                                                                        0x0002
+#define ixCRT03                                                                                        0x0003
+#define ixCRT04                                                                                        0x0004
+#define ixCRT05                                                                                        0x0005
+#define ixCRT06                                                                                        0x0006
+#define ixCRT07                                                                                        0x0007
+#define ixCRT08                                                                                        0x0008
+#define ixCRT09                                                                                        0x0009
+#define ixCRT0A                                                                                        0x000a
+#define ixCRT0B                                                                                        0x000b
+#define ixCRT0C                                                                                        0x000c
+#define ixCRT0D                                                                                        0x000d
+#define ixCRT0E                                                                                        0x000e
+#define ixCRT0F                                                                                        0x000f
+#define ixCRT10                                                                                        0x0010
+#define ixCRT11                                                                                        0x0011
+#define ixCRT12                                                                                        0x0012
+#define ixCRT13                                                                                        0x0013
+#define ixCRT14                                                                                        0x0014
+#define ixCRT15                                                                                        0x0015
+#define ixCRT16                                                                                        0x0016
+#define ixCRT17                                                                                        0x0017
+#define ixCRT18                                                                                        0x0018
+#define ixCRT1E                                                                                        0x001e
+#define ixCRT1F                                                                                        0x001f
+#define ixCRT22                                                                                        0x0022
+
+
+// addressBlock: vga_vgagrphind
+// base address: 0x0
+#define ixGRA00                                                                                        0x0000
+#define ixGRA01                                                                                        0x0001
+#define ixGRA02                                                                                        0x0002
+#define ixGRA03                                                                                        0x0003
+#define ixGRA04                                                                                        0x0004
+#define ixGRA05                                                                                        0x0005
+#define ixGRA06                                                                                        0x0006
+#define ixGRA07                                                                                        0x0007
+#define ixGRA08                                                                                        0x0008
+
+
+// addressBlock: vga_vgaattrind
+// base address: 0x0
+#define ixATTR00                                                                                       0x0000
+#define ixATTR01                                                                                       0x0001
+#define ixATTR02                                                                                       0x0002
+#define ixATTR03                                                                                       0x0003
+#define ixATTR04                                                                                       0x0004
+#define ixATTR05                                                                                       0x0005
+#define ixATTR06                                                                                       0x0006
+#define ixATTR07                                                                                       0x0007
+#define ixATTR08                                                                                       0x0008
+#define ixATTR09                                                                                       0x0009
+#define ixATTR0A                                                                                       0x000a
+#define ixATTR0B                                                                                       0x000b
+#define ixATTR0C                                                                                       0x000c
+#define ixATTR0D                                                                                       0x000d
+#define ixATTR0E                                                                                       0x000e
+#define ixATTR0F                                                                                       0x000f
+#define ixATTR10                                                                                       0x0010
+#define ixATTR11                                                                                       0x0011
+#define ixATTR12                                                                                       0x0012
+#define ixATTR13                                                                                       0x0013
+#define ixATTR14                                                                                       0x0014
+
+
+// addressBlock: azendpoint_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                                           0x2200
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                          0x2706
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                                          0x270d
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                                        0x270e
+#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                                                     0x2724
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                                        0x273e
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                                                  0x2770
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                              0x2771
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x2f09
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                                     0x2f0a
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                                           0x2f0b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY                                   0x3702
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                                                   0x3707
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                                             0x3708
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                               0x3709
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                                   0x371c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                                 0x371d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                                 0x371e
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                                 0x371f
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION                                      0x3770
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                                               0x3771
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                                                    0x3772
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                                                 0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                                            0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                                            0x3777
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                                            0x3778
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                                            0x3779
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                                            0x377a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                                          0x377b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                                            0x3780
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                                             0x3781
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                                             0x3785
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                                             0x3786
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                                             0x3787
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                                             0x3788
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                                0x3789
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                                    0x378a
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                                    0x378b
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                                    0x378c
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                                    0x378d
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                                    0x378e
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                                    0x378f
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                                    0x3790
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                                    0x3791
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                                    0x3792
+#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                                         0x3793
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                                            0x3797
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                            0x3798
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                                             0x3799
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                              0x379a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                                                      0x379b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                                                   0x379c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                                  0x379d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                                 0x379e
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                      0x3f09
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                                                   0x3f0c
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                                         0x3f0e
+
+
+// addressBlock: azendpoint_descriptorind
+// base address: 0x0
+#define ixAUDIO_DESCRIPTOR0                                                                            0x0001
+#define ixAUDIO_DESCRIPTOR1                                                                            0x0002
+#define ixAUDIO_DESCRIPTOR2                                                                            0x0003
+#define ixAUDIO_DESCRIPTOR3                                                                            0x0004
+#define ixAUDIO_DESCRIPTOR4                                                                            0x0005
+#define ixAUDIO_DESCRIPTOR5                                                                            0x0006
+#define ixAUDIO_DESCRIPTOR6                                                                            0x0007
+#define ixAUDIO_DESCRIPTOR7                                                                            0x0008
+#define ixAUDIO_DESCRIPTOR8                                                                            0x0009
+#define ixAUDIO_DESCRIPTOR9                                                                            0x000a
+#define ixAUDIO_DESCRIPTOR10                                                                           0x000b
+#define ixAUDIO_DESCRIPTOR11                                                                           0x000c
+#define ixAUDIO_DESCRIPTOR12                                                                           0x000d
+#define ixAUDIO_DESCRIPTOR13                                                                           0x000e
+
+
+// addressBlock: azendpoint_sinkinfoind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                                                  0x0000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                                       0x0001
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                                             0x0002
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                                          0x0003
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                                          0x0004
+#define ixSINK_DESCRIPTION0                                                                            0x0005
+#define ixSINK_DESCRIPTION1                                                                            0x0006
+#define ixSINK_DESCRIPTION2                                                                            0x0007
+#define ixSINK_DESCRIPTION3                                                                            0x0008
+#define ixSINK_DESCRIPTION4                                                                            0x0009
+#define ixSINK_DESCRIPTION5                                                                            0x000a
+#define ixSINK_DESCRIPTION6                                                                            0x000b
+#define ixSINK_DESCRIPTION7                                                                            0x000c
+#define ixSINK_DESCRIPTION8                                                                            0x000d
+#define ixSINK_DESCRIPTION9                                                                            0x000e
+#define ixSINK_DESCRIPTION10                                                                           0x000f
+#define ixSINK_DESCRIPTION11                                                                           0x0010
+#define ixSINK_DESCRIPTION12                                                                           0x0011
+#define ixSINK_DESCRIPTION13                                                                           0x0012
+#define ixSINK_DESCRIPTION14                                                                           0x0013
+#define ixSINK_DESCRIPTION15                                                                           0x0014
+#define ixSINK_DESCRIPTION16                                                                           0x0015
+#define ixSINK_DESCRIPTION17                                                                           0x0016
+
+
+// addressBlock: azf0controller_azinputcrc0resultind
+// base address: 0x0
+#define ixAZALIA_INPUT_CRC0_CHANNEL0                                                                   0x0000
+#define ixAZALIA_INPUT_CRC0_CHANNEL1                                                                   0x0001
+#define ixAZALIA_INPUT_CRC0_CHANNEL2                                                                   0x0002
+#define ixAZALIA_INPUT_CRC0_CHANNEL3                                                                   0x0003
+#define ixAZALIA_INPUT_CRC0_CHANNEL4                                                                   0x0004
+#define ixAZALIA_INPUT_CRC0_CHANNEL5                                                                   0x0005
+#define ixAZALIA_INPUT_CRC0_CHANNEL6                                                                   0x0006
+#define ixAZALIA_INPUT_CRC0_CHANNEL7                                                                   0x0007
+
+
+// addressBlock: azf0controller_azinputcrc1resultind
+// base address: 0x0
+#define ixAZALIA_INPUT_CRC1_CHANNEL0                                                                   0x0000
+#define ixAZALIA_INPUT_CRC1_CHANNEL1                                                                   0x0001
+#define ixAZALIA_INPUT_CRC1_CHANNEL2                                                                   0x0002
+#define ixAZALIA_INPUT_CRC1_CHANNEL3                                                                   0x0003
+#define ixAZALIA_INPUT_CRC1_CHANNEL4                                                                   0x0004
+#define ixAZALIA_INPUT_CRC1_CHANNEL5                                                                   0x0005
+#define ixAZALIA_INPUT_CRC1_CHANNEL6                                                                   0x0006
+#define ixAZALIA_INPUT_CRC1_CHANNEL7                                                                   0x0007
+
+
+// addressBlock: azf0controller_azcrc0resultind
+// base address: 0x0
+#define ixAZALIA_CRC0_CHANNEL0                                                                         0x0000
+#define ixAZALIA_CRC0_CHANNEL1                                                                         0x0001
+#define ixAZALIA_CRC0_CHANNEL2                                                                         0x0002
+#define ixAZALIA_CRC0_CHANNEL3                                                                         0x0003
+#define ixAZALIA_CRC0_CHANNEL4                                                                         0x0004
+#define ixAZALIA_CRC0_CHANNEL5                                                                         0x0005
+#define ixAZALIA_CRC0_CHANNEL6                                                                         0x0006
+#define ixAZALIA_CRC0_CHANNEL7                                                                         0x0007
+
+
+// addressBlock: azf0controller_azcrc1resultind
+// base address: 0x0
+#define ixAZALIA_CRC1_CHANNEL0                                                                         0x0000
+#define ixAZALIA_CRC1_CHANNEL1                                                                         0x0001
+#define ixAZALIA_CRC1_CHANNEL2                                                                         0x0002
+#define ixAZALIA_CRC1_CHANNEL3                                                                         0x0003
+#define ixAZALIA_CRC1_CHANNEL4                                                                         0x0004
+#define ixAZALIA_CRC1_CHANNEL5                                                                         0x0005
+#define ixAZALIA_CRC1_CHANNEL6                                                                         0x0006
+#define ixAZALIA_CRC1_CHANNEL7                                                                         0x0007
+
+
+// addressBlock: azinputendpoint_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                                     0x6200
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                    0x6706
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                                    0x670d
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                          0x6f09
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                               0x6f0a
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                                     0x6f0b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                                             0x7707
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                                       0x7708
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                                         0x7709
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                             0x771c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                           0x771d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                           0x771e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                           0x771f
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                                         0x7771
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                                       0x7777
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                                       0x7778
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                                       0x7779
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                                       0x777a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                                        0x777c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                                       0x7785
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                                       0x7786
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                                       0x7787
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                                       0x7788
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                      0x7798
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                                       0x7799
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                        0x779a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                                       0x779b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                                                  0x779c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                                           0x779d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                                           0x779e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x7f09
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                                             0x7f0c
+
+
+// addressBlock: azroot_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0f00
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0f02
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                                        0x0f04
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x1705
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x1720
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2                                     0x1721
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3                                     0x1722
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4                                     0x1723
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x1770
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                                       0x17ff
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT                                    0x1f04
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x1f05
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x1f0a
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x1f0b
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x1f0f
+
+
+// addressBlock: azf0stream0_streamind
+// base address: 0x0
+#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream1_streamind
+// base address: 0x0
+#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream2_streamind
+// base address: 0x0
+#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream3_streamind
+// base address: 0x0
+#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream4_streamind
+// base address: 0x0
+#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream5_streamind
+// base address: 0x0
+#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream6_streamind
+// base address: 0x0
+#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream7_streamind
+// base address: 0x0
+#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream8_streamind
+// base address: 0x0
+#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream9_streamind
+// base address: 0x0
+#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream10_streamind
+// base address: 0x0
+#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream11_streamind
+// base address: 0x0
+#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream12_streamind
+// base address: 0x0
+#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream13_streamind
+// base address: 0x0
+#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream14_streamind
+// base address: 0x0
+#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream15_streamind
+// base address: 0x0
+#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0endpoint0_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint1_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint2_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint3_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint4_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint5_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint6_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint7_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0inputendpoint0_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint1_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint2_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint3_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint4_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint5_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint6_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint7_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h
new file mode 100644
index 0000000000000..23faa628cd59e
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h
@@ -0,0 +1,56578 @@
+/*
+ * Copyright (C) 2022  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dcn_3_2_1_SH_MASK_HEADER
+#define _dcn_3_2_1_SH_MASK_HEADER
+
+
+// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
+//DENTIST_DISPCLK_CNTL
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT                                                 0x0
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT                                                 0x8
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT                                                 0xf
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT                                                   0x11
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT                                                  0x12
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT                                                 0x13
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT                                                  0x14
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT                                                    0x15
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT                                                   0x16
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT                                                  0x18
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK                                                   0x0000007FL
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK                                                   0x00007F00L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK                                                   0x00018000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK                                                     0x00020000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK                                                    0x00040000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK                                                   0x00080000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK                                                    0x00100000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK                                                      0x00200000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK                                                     0x00400000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK                                                    0x7F000000L
+
+
+// addressBlock: dce_dc_dccg_dccg_dispdec
+//PHYPLLA_PIXCLK_RESYNC_CNTL
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK                                                0x00000100L
+//PHYPLLB_PIXCLK_RESYNC_CNTL
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK                                                0x00000100L
+//PHYPLLC_PIXCLK_RESYNC_CNTL
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK                                                0x00000100L
+//PHYPLLD_PIXCLK_RESYNC_CNTL
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK                                                0x00000100L
+//DP_DTO_DBUF_EN
+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT                                                                0x0
+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT                                                                0x1
+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT                                                                0x2
+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT                                                                0x3
+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT                                                                0x4
+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT                                                                0x5
+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT                                                                0x6
+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT                                                                0x7
+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK                                                                  0x00000001L
+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK                                                                  0x00000002L
+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK                                                                  0x00000004L
+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK                                                                  0x00000008L
+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK                                                                  0x00000010L
+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK                                                                  0x00000020L
+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK                                                                  0x00000040L
+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK                                                                  0x00000080L
+//DSCCLK3_DTO_PARAM
+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPREFCLK_CGTT_BLK_CTRL_REG
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT                                             0x0
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT                                            0x4
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK                                               0x0000000FL
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK                                              0x00000FF0L
+//DCCG_GATE_DISABLE_CNTL4
+#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x0
+#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x1
+#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x2
+#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x3
+#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x4
+#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE__SHIFT                                        0x11
+#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000001L
+#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000002L
+#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000004L
+#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000008L
+#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000010L
+#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE_MASK                                          0x00020000L
+//DPSTREAMCLK_CNTL
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL__SHIFT                                                         0x0
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN__SHIFT                                                              0x3
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL__SHIFT                                                         0x4
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_EN__SHIFT                                                              0x7
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_SRC_SEL__SHIFT                                                         0x8
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_EN__SHIFT                                                              0xb
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_SRC_SEL__SHIFT                                                         0xc
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_EN__SHIFT                                                              0xf
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL_MASK                                                           0x00000007L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN_MASK                                                                0x00000008L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL_MASK                                                           0x00000070L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_EN_MASK                                                                0x00000080L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_SRC_SEL_MASK                                                           0x00000700L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_EN_MASK                                                                0x00000800L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_SRC_SEL_MASK                                                           0x00007000L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_EN_MASK                                                                0x00008000L
+//REFCLK_CGTT_BLK_CTRL_REG
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//PHYPLLE_PIXCLK_RESYNC_CNTL
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK                                                0x00000100L
+//DCCG_GLOBAL_FGCG_REP_CNTL
+#define DCCG_GLOBAL_FGCG_REP_CNTL__DCCG_GLOBAL_FGCG_REP_DIS__SHIFT                                            0x0
+#define DCCG_GLOBAL_FGCG_REP_CNTL__DCCG_GLOBAL_FGCG_REP_DIS_MASK                                              0x00000001L
+//DCCG_DS_DTO_INCR
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT                                                             0x0
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK                                                               0xFFFFFFFFL
+//DCCG_DS_DTO_MODULO
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT                                                         0x0
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK                                                           0xFFFFFFFFL
+//DCCG_DS_CNTL
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT                                                                   0x0
+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT                                                                  0x4
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT                                                            0x8
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT                                                           0x9
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT                                                          0x10
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT                                                        0x18
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT                                                           0x19
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK                                                                     0x00000001L
+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK                                                                    0x00000030L
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK                                                              0x00000100L
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK                                                             0x00000200L
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK                                                            0x00030000L
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK                                                          0x01000000L
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK                                                             0x02000000L
+//DCCG_DS_HW_CAL_INTERVAL
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT                                               0x0
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK                                                 0xFFFFFFFFL
+//DPREFCLK_CNTL
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT                                                                0x0
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK                                                                  0x00000007L
+//DCE_VERSION
+#define DCE_VERSION__MAJOR_VERSION__SHIFT                                                                     0x0
+#define DCE_VERSION__MINOR_VERSION__SHIFT                                                                     0x8
+#define DCE_VERSION__MAJOR_VERSION_MASK                                                                       0x000000FFL
+#define DCE_VERSION__MINOR_VERSION_MASK                                                                       0x0000FF00L
+//DCCG_GTC_CNTL
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT                                                                 0x0
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK                                                                   0x00000001L
+//DCCG_GTC_DTO_INCR
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT                                                           0x0
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK                                                             0xFFFFFFFFL
+//DCCG_GTC_DTO_MODULO
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT                                                       0x0
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK                                                         0xFFFFFFFFL
+//DCCG_GTC_CURRENT
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT                                                             0x0
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK                                                               0xFFFFFFFFL
+//SYMCLK32_SE_CNTL
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL__SHIFT                                                         0x0
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN__SHIFT                                                              0x3
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL__SHIFT                                                         0x4
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN__SHIFT                                                              0x7
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL__SHIFT                                                         0x8
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN__SHIFT                                                              0xb
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL__SHIFT                                                         0xc
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN__SHIFT                                                              0xf
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL_MASK                                                           0x00000007L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN_MASK                                                                0x00000008L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL_MASK                                                           0x00000070L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN_MASK                                                                0x00000080L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL_MASK                                                           0x00000700L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN_MASK                                                                0x00000800L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL_MASK                                                           0x00007000L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN_MASK                                                                0x00008000L
+//SYMCLK32_LE_CNTL
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL__SHIFT                                                         0x0
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN__SHIFT                                                              0x3
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL__SHIFT                                                         0x4
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN__SHIFT                                                              0x7
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL_MASK                                                           0x00000007L
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN_MASK                                                                0x00000008L
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL_MASK                                                           0x00000070L
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN_MASK                                                                0x00000080L
+//DTBCLK_P_CNTL
+#define DTBCLK_P_CNTL__DTBCLK_P0_SRC_SEL__SHIFT                                                               0x0
+#define DTBCLK_P_CNTL__DTBCLK_P0_EN__SHIFT                                                                    0x2
+#define DTBCLK_P_CNTL__DTBCLK_P1_SRC_SEL__SHIFT                                                               0x3
+#define DTBCLK_P_CNTL__DTBCLK_P1_EN__SHIFT                                                                    0x5
+#define DTBCLK_P_CNTL__DTBCLK_P2_SRC_SEL__SHIFT                                                               0x6
+#define DTBCLK_P_CNTL__DTBCLK_P2_EN__SHIFT                                                                    0x8
+#define DTBCLK_P_CNTL__DTBCLK_P3_SRC_SEL__SHIFT                                                               0x9
+#define DTBCLK_P_CNTL__DTBCLK_P3_EN__SHIFT                                                                    0xb
+#define DTBCLK_P_CNTL__DTBCLK_P0_SRC_SEL_MASK                                                                 0x00000003L
+#define DTBCLK_P_CNTL__DTBCLK_P0_EN_MASK                                                                      0x00000004L
+#define DTBCLK_P_CNTL__DTBCLK_P1_SRC_SEL_MASK                                                                 0x00000018L
+#define DTBCLK_P_CNTL__DTBCLK_P1_EN_MASK                                                                      0x00000020L
+#define DTBCLK_P_CNTL__DTBCLK_P2_SRC_SEL_MASK                                                                 0x000000C0L
+#define DTBCLK_P_CNTL__DTBCLK_P2_EN_MASK                                                                      0x00000100L
+#define DTBCLK_P_CNTL__DTBCLK_P3_SRC_SEL_MASK                                                                 0x00000600L
+#define DTBCLK_P_CNTL__DTBCLK_P3_EN_MASK                                                                      0x00000800L
+//DCCG_GATE_DISABLE_CNTL5
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P0_GATE_DISABLE__SHIFT                                                0x0
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P1_GATE_DISABLE__SHIFT                                                0x1
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P2_GATE_DISABLE__SHIFT                                                0x2
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P3_GATE_DISABLE__SHIFT                                                0x3
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_ROOT_GATE_DISABLE__SHIFT                                        0x6
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_GATE_DISABLE__SHIFT                                             0x7
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_ROOT_GATE_DISABLE__SHIFT                                        0x8
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_GATE_DISABLE__SHIFT                                             0x9
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_ROOT_GATE_DISABLE__SHIFT                                        0xa
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_GATE_DISABLE__SHIFT                                             0xb
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_ROOT_GATE_DISABLE__SHIFT                                        0xc
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_GATE_DISABLE__SHIFT                                             0xd
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P0_GATE_DISABLE_MASK                                                  0x00000001L
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P1_GATE_DISABLE_MASK                                                  0x00000002L
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P2_GATE_DISABLE_MASK                                                  0x00000004L
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P3_GATE_DISABLE_MASK                                                  0x00000008L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_ROOT_GATE_DISABLE_MASK                                          0x00000040L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_GATE_DISABLE_MASK                                               0x00000080L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_ROOT_GATE_DISABLE_MASK                                          0x00000100L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_GATE_DISABLE_MASK                                               0x00000200L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_ROOT_GATE_DISABLE_MASK                                          0x00000400L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_GATE_DISABLE_MASK                                               0x00000800L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_ROOT_GATE_DISABLE_MASK                                          0x00001000L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_GATE_DISABLE_MASK                                               0x00002000L
+//DSCCLK0_DTO_PARAM
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK                                                            0x00FF0000L
+//DSCCLK1_DTO_PARAM
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK                                                            0x00FF0000L
+//DSCCLK2_DTO_PARAM
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO_MASK                                                            0x00FF0000L
+//OTG_PIXEL_RATE_DIV
+#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK1__SHIFT                                                      0x0
+#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK2__SHIFT                                                      0x1
+#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK1__SHIFT                                                      0x3
+#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK2__SHIFT                                                      0x4
+#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK1__SHIFT                                                      0x6
+#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK2__SHIFT                                                      0x7
+#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK1__SHIFT                                                      0x9
+#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK2__SHIFT                                                      0xa
+#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK1_MASK                                                        0x00000001L
+#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK2_MASK                                                        0x00000006L
+#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK1_MASK                                                        0x00000008L
+#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK2_MASK                                                        0x00000030L
+#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK1_MASK                                                        0x00000040L
+#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK2_MASK                                                        0x00000180L
+#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK1_MASK                                                        0x00000200L
+#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK2_MASK                                                        0x00000C00L
+//MILLISECOND_TIME_BASE_DIV
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT                                           0x0
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK                                             0x0001FFFFL
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L
+//DISPCLK_FREQ_CHANGE_CNTL
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT                                                   0x0
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT                                                    0x10
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT                                               0x14
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT                                            0x19
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT                                               0x1c
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT                                               0x1d
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT                                              0x1e
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT                                         0x1f
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK                                                     0x00003FFFL
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK                                                      0x000F0000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK                                                 0x00100000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK                                              0x0E000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK                                                 0x10000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK                                                 0x20000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK                                                0x40000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK                                           0x80000000L
+//DC_MEM_GLOBAL_PWR_REQ_CNTL
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT                                          0x0
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK                                            0x00000001L
+//DCCG_GATE_DISABLE_CNTL
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT                                              0x0
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT                                            0x1
+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT                                                    0x2
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT                                                  0x3
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT                                                   0x4
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT                                                   0x6
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT                                           0x8
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT                                                    0x9
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT                                             0xa
+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT                                                    0xb
+#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE__SHIFT                                                  0xc
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT                                                   0x11
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT                                                   0x12
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT                                                   0x13
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT                                              0x16
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT                                                    0x1a
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT                                              0x1b
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT                                                    0x1c
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT                                                   0x1d
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT                                                    0x1e
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK                                                0x00000001L
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK                                              0x00000002L
+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK                                                      0x00000004L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK                                                    0x00000008L
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK                                                     0x00000010L
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK                                                     0x00000040L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK                                             0x00000100L
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK                                                      0x00000200L
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK                                               0x00000400L
+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK                                                      0x00000800L
+#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE_MASK                                                    0x00001000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK                                                     0x00020000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK                                                     0x00040000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK                                                     0x00080000L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK                                                0x00400000L
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK                                                      0x04000000L
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK                                                0x08000000L
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK                                                      0x10000000L
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK                                                     0x20000000L
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK                                                      0x40000000L
+//DISPCLK_CGTT_BLK_CTRL_REG
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT                                               0x0
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT                                              0x4
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK                                                 0x0000000FL
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK                                                0x00000FF0L
+//SOCCLK_CGTT_BLK_CTRL_REG
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DCCG_CAC_STATUS
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT                                                             0x0
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK                                                               0xFFFFFFFFL
+//MICROSECOND_TIME_BASE_DIV
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT                                           0x0
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT                                                        0x8
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT                                                        0x10
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT                                           0x11
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK                                             0x0000007FL
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK                                                          0x00007F00L
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK                                                          0x00010000L
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK                                             0x00020000L
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L
+//DCCG_GATE_DISABLE_CNTL2
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT                                               0x0
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT                                               0x1
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT                                               0x2
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT                                               0x3
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT                                               0x4
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT                                               0x5
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT                                               0x6
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE__SHIFT                                             0x8
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE__SHIFT                                             0x9
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE__SHIFT                                             0xa
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE__SHIFT                                             0xb
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE__SHIFT                                             0xc
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE__SHIFT                                             0xd
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT                                                  0x10
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT                                                  0x11
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT                                                  0x12
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT                                                  0x13
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT                                                  0x14
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT                                                  0x15
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT                                                  0x16
+#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE__SHIFT                                               0x18
+#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE__SHIFT                                               0x19
+#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE__SHIFT                                               0x1a
+#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE__SHIFT                                               0x1b
+#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE__SHIFT                                               0x1c
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK                                                 0x00000001L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK                                                 0x00000002L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK                                                 0x00000004L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK                                                 0x00000008L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK                                                 0x00000010L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK                                                 0x00000020L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK                                                 0x00000040L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE_MASK                                               0x00000100L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE_MASK                                               0x00000200L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE_MASK                                               0x00000400L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE_MASK                                               0x00000800L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE_MASK                                               0x00001000L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE_MASK                                               0x00002000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK                                                    0x00010000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK                                                    0x00020000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK                                                    0x00040000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK                                                    0x00080000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK                                                    0x00100000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK                                                    0x00200000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK                                                    0x00400000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE_MASK                                                 0x01000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE_MASK                                                 0x02000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE_MASK                                                 0x04000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE_MASK                                                 0x08000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE_MASK                                                 0x10000000L
+//SYMCLK_CGTT_BLK_CTRL_REG
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DCCG_DISP_CNTL_REG
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT                                                      0x8
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK                                                        0x00000100L
+//OTG0_PIXEL_RATE_CNTL
+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_ENABLE__SHIFT                                                       0x3
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT                                                           0x4
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT                                                       0x5
+#define OTG0_PIXEL_RATE_CNTL__DTBCLKDTO0_ENABLE_STATUS__SHIFT                                                 0x6
+#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS__SHIFT                                                     0x7
+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL__SHIFT                                                        0xc
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_ENABLE_MASK                                                         0x00000008L
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK                                                             0x00000010L
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG0_PIXEL_RATE_CNTL__DTBCLKDTO0_ENABLE_STATUS_MASK                                                   0x00000040L
+#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS_MASK                                                       0x00000080L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL_MASK                                                          0x00003000L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+//DP_DTO0_PHASE
+#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT                                                                   0x0
+#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO0_MODULO
+#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT                                                                 0x0
+#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG0_PHYPLL_PIXEL_RATE_CNTL
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//OTG1_PIXEL_RATE_CNTL
+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_ENABLE__SHIFT                                                       0x3
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT                                                           0x4
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT                                                       0x5
+#define OTG1_PIXEL_RATE_CNTL__DTBCLKDTO1_ENABLE_STATUS__SHIFT                                                 0x6
+#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS__SHIFT                                                     0x7
+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL__SHIFT                                                        0xc
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_ENABLE_MASK                                                         0x00000008L
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK                                                             0x00000010L
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG1_PIXEL_RATE_CNTL__DTBCLKDTO1_ENABLE_STATUS_MASK                                                   0x00000040L
+#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS_MASK                                                       0x00000080L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL_MASK                                                          0x00003000L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+//DP_DTO1_PHASE
+#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT                                                                   0x0
+#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO1_MODULO
+#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT                                                                 0x0
+#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG1_PHYPLL_PIXEL_RATE_CNTL
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//OTG2_PIXEL_RATE_CNTL
+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_ENABLE__SHIFT                                                       0x3
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT                                                           0x4
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT                                                       0x5
+#define OTG2_PIXEL_RATE_CNTL__DTBCLKDTO2_ENABLE_STATUS__SHIFT                                                 0x6
+#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS__SHIFT                                                     0x7
+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL__SHIFT                                                        0xc
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_ENABLE_MASK                                                         0x00000008L
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK                                                             0x00000010L
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG2_PIXEL_RATE_CNTL__DTBCLKDTO2_ENABLE_STATUS_MASK                                                   0x00000040L
+#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS_MASK                                                       0x00000080L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL_MASK                                                          0x00003000L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+//DP_DTO2_PHASE
+#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT                                                                   0x0
+#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO2_MODULO
+#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT                                                                 0x0
+#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG2_PHYPLL_PIXEL_RATE_CNTL
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//OTG3_PIXEL_RATE_CNTL
+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_ENABLE__SHIFT                                                       0x3
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT                                                           0x4
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT                                                       0x5
+#define OTG3_PIXEL_RATE_CNTL__DTBCLKDTO3_ENABLE_STATUS__SHIFT                                                 0x6
+#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS__SHIFT                                                     0x7
+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL__SHIFT                                                        0xc
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_ENABLE_MASK                                                         0x00000008L
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK                                                             0x00000010L
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG3_PIXEL_RATE_CNTL__DTBCLKDTO3_ENABLE_STATUS_MASK                                                   0x00000040L
+#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS_MASK                                                       0x00000080L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL_MASK                                                          0x00003000L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+//DP_DTO3_PHASE
+#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT                                                                   0x0
+#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO3_MODULO
+#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT                                                                 0x0
+#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG3_PHYPLL_PIXEL_RATE_CNTL
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//DPPCLK_CGTT_BLK_CTRL_REG
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DPPCLK0_DTO_PARAM
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPPCLK1_DTO_PARAM
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPPCLK2_DTO_PARAM
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPPCLK3_DTO_PARAM
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO_MASK                                                            0x00FF0000L
+//DCCG_CAC_STATUS2
+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT                                                           0x0
+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK                                                             0x0007FFFFL
+//SYMCLKA_CLOCK_ENABLE
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKB_CLOCK_ENABLE
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKC_CLOCK_ENABLE
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKD_CLOCK_ENABLE
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKE_CLOCK_ENABLE
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK                                                       0x00000700L
+//DCCG_SOFT_RESET
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT                                                             0x0
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT                                                                0x2
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT                                                                0x3
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT                                                     0x4
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT                                                           0x8
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT                                                             0xc
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT                                                             0xd
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xe
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xf
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x10
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x11
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x12
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x13
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x14
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x15
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK                                                               0x00000001L
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK                                                                  0x00000004L
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK                                                                  0x00000008L
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK                                                       0x00000010L
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK                                                             0x00000100L
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK                                                               0x00001000L
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK                                                               0x00002000L
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00004000L
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00008000L
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00010000L
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00020000L
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00040000L
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00080000L
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00100000L
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00200000L
+//DSCCLK_DTO_CTRL
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE__SHIFT                                                            0x0
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE__SHIFT                                                            0x1
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE__SHIFT                                                            0x2
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE__SHIFT                                                            0x3
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE__SHIFT                                                            0x4
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE__SHIFT                                                            0x5
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT                                                             0x8
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT                                                             0x9
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT                                                             0xa
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT                                                             0xb
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT                                                             0xc
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT                                                             0xd
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE_MASK                                                              0x00000001L
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE_MASK                                                              0x00000002L
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE_MASK                                                              0x00000004L
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE_MASK                                                              0x00000008L
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE_MASK                                                              0x00000010L
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE_MASK                                                              0x00000020L
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK                                                               0x00000100L
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK                                                               0x00000200L
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK                                                               0x00000400L
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK                                                               0x00000800L
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK                                                               0x00001000L
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK                                                               0x00002000L
+//DCCG_AUDIO_DTO_SOURCE
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT                                              0x0
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT                                                      0x4
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT                                          0x14
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT                                          0x18
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT                                          0x1c
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO__SHIFT                                    0x1d
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK                                                0x00000007L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK                                                        0x00000070L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK                                            0x00100000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK                                            0x01000000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK                                            0x10000000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO_MASK                                      0x20000000L
+//DCCG_AUDIO_DTO0_PHASE
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT                                                   0x0
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK                                                     0xFFFFFFFFL
+//DCCG_AUDIO_DTO0_MODULE
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT                                                 0x0
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK                                                   0xFFFFFFFFL
+//DCCG_AUDIO_DTO1_PHASE
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT                                                   0x0
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK                                                     0xFFFFFFFFL
+//DCCG_AUDIO_DTO1_MODULE
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT                                                 0x0
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK                                                   0xFFFFFFFFL
+//DCCG_VSYNC_OTG0_LATCH_VALUE
+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG1_LATCH_VALUE
+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG2_LATCH_VALUE
+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG3_LATCH_VALUE
+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG4_LATCH_VALUE
+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG5_LATCH_VALUE
+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DPPCLK_DTO_CTRL
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE__SHIFT                                                            0x0
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT                                                             0x1
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE__SHIFT                                                            0x4
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT                                                             0x5
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE__SHIFT                                                            0x8
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT                                                             0x9
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE__SHIFT                                                            0xc
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT                                                             0xd
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE__SHIFT                                                            0x10
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT                                                             0x11
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE__SHIFT                                                            0x14
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT                                                             0x15
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE_MASK                                                              0x00000001L
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK                                                               0x00000002L
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE_MASK                                                              0x00000010L
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK                                                               0x00000020L
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE_MASK                                                              0x00000100L
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK                                                               0x00000200L
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE_MASK                                                              0x00001000L
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK                                                               0x00002000L
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE_MASK                                                              0x00010000L
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK                                                               0x00020000L
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE_MASK                                                              0x00100000L
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK                                                               0x00200000L
+//DCCG_VSYNC_CNT_CTRL
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT                                                     0x0
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT                                                   0x2
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT                                                  0x3
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT                                               0x4
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT                                                  0x8
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT                                                  0x10
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT                                                  0x11
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT                                                  0x12
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT                                                  0x13
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT                                                  0x14
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT                                                  0x15
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT                                            0x18
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT                                            0x19
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT                                            0x1a
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT                                            0x1b
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT                                            0x1c
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT                                            0x1d
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK                                                       0x00000001L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK                                                     0x00000004L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK                                                    0x00000008L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK                                                 0x000000F0L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK                                                    0x00000F00L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK                                                    0x00010000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK                                                    0x00020000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK                                                    0x00040000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK                                                    0x00080000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK                                                    0x00100000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK                                                    0x00200000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK                                              0x01000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK                                              0x02000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK                                              0x04000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK                                              0x08000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK                                              0x10000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK                                              0x20000000L
+//DCCG_VSYNC_CNT_INT_CTRL
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT                                   0x0
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT                             0x0
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT                                   0x1
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT                             0x1
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT                                   0x2
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT                             0x2
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT                                   0x3
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT                             0x3
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT                                   0x4
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT                             0x4
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT                                   0x5
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT                             0x5
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT                                        0x8
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT                                        0x9
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT                                        0xa
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT                                        0xb
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT                                        0xc
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT                                        0xd
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK                                     0x00000001L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK                               0x00000001L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK                                     0x00000002L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK                               0x00000002L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK                                     0x00000004L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK                               0x00000004L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK                                     0x00000008L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK                               0x00000008L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK                                     0x00000010L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK                               0x00000010L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK                                     0x00000020L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK                               0x00000020L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK                                          0x00000100L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK                                          0x00000200L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK                                          0x00000400L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK                                          0x00000800L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK                                          0x00001000L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK                                          0x00002000L
+//FORCE_SYMCLK_DISABLE
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE__SHIFT                                                    0x0
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE__SHIFT                                                    0x1
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE__SHIFT                                                    0x2
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE__SHIFT                                                    0x3
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE__SHIFT                                                    0x4
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE__SHIFT                                                    0x5
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE__SHIFT                                                    0x6
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE_MASK                                                      0x00000001L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE_MASK                                                      0x00000002L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE_MASK                                                      0x00000004L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE_MASK                                                      0x00000008L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE_MASK                                                      0x00000010L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE_MASK                                                      0x00000020L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE_MASK                                                      0x00000040L
+//DCCG_TEST_CLK_SEL
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT                                                  0x0
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT                                                  0xc
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL__SHIFT                                              0xe
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT                                                  0x10
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT                                                  0x1c
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK                                                    0x000001FFL
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK                                                    0x00001000L
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL_MASK                                                0x0000C000L
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK                                                    0x01FF0000L
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK                                                    0x10000000L
+//DTBCLK_DTO0_PHASE
+#define DTBCLK_DTO0_PHASE__DTBCLK_DTO0_PHASE__SHIFT                                                           0x0
+#define DTBCLK_DTO0_PHASE__DTBCLK_DTO0_PHASE_MASK                                                             0xFFFFFFFFL
+//DTBCLK_DTO1_PHASE
+#define DTBCLK_DTO1_PHASE__DTBCLK_DTO1_PHASE__SHIFT                                                           0x0
+#define DTBCLK_DTO1_PHASE__DTBCLK_DTO1_PHASE_MASK                                                             0xFFFFFFFFL
+//DTBCLK_DTO2_PHASE
+#define DTBCLK_DTO2_PHASE__DTBCLK_DTO2_PHASE__SHIFT                                                           0x0
+#define DTBCLK_DTO2_PHASE__DTBCLK_DTO2_PHASE_MASK                                                             0xFFFFFFFFL
+//DTBCLK_DTO3_PHASE
+#define DTBCLK_DTO3_PHASE__DTBCLK_DTO3_PHASE__SHIFT                                                           0x0
+#define DTBCLK_DTO3_PHASE__DTBCLK_DTO3_PHASE_MASK                                                             0xFFFFFFFFL
+//DTBCLK_DTO0_MODULO
+#define DTBCLK_DTO0_MODULO__DTBCLK_DTO0_MODULO__SHIFT                                                         0x0
+#define DTBCLK_DTO0_MODULO__DTBCLK_DTO0_MODULO_MASK                                                           0xFFFFFFFFL
+//DTBCLK_DTO1_MODULO
+#define DTBCLK_DTO1_MODULO__DTBCLK_DTO1_MODULO__SHIFT                                                         0x0
+#define DTBCLK_DTO1_MODULO__DTBCLK_DTO1_MODULO_MASK                                                           0xFFFFFFFFL
+//DTBCLK_DTO2_MODULO
+#define DTBCLK_DTO2_MODULO__DTBCLK_DTO2_MODULO__SHIFT                                                         0x0
+#define DTBCLK_DTO2_MODULO__DTBCLK_DTO2_MODULO_MASK                                                           0xFFFFFFFFL
+//DTBCLK_DTO3_MODULO
+#define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO__SHIFT                                                         0x0
+#define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO_MASK                                                           0xFFFFFFFFL
+//HDMICHARCLK0_CLOCK_CNTL
+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN__SHIFT                                                       0x0
+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL__SHIFT                                                  0x4
+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN_MASK                                                         0x00000001L
+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL_MASK                                                    0x00000070L
+//PHYASYMCLK_CLOCK_CNTL
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//PHYBSYMCLK_CLOCK_CNTL
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//PHYCSYMCLK_CLOCK_CNTL
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//PHYDSYMCLK_CLOCK_CNTL
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//PHYESYMCLK_CLOCK_CNTL
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//HDMISTREAMCLK_CNTL
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL__SHIFT                                                     0x0
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN__SHIFT                                                          0x3
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_DTO_FORCE_DIS__SHIFT                                               0x4
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL_MASK                                                       0x00000007L
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN_MASK                                                            0x00000008L
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_DTO_FORCE_DIS_MASK                                                 0x00000010L
+//DCCG_GATE_DISABLE_CNTL3
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE__SHIFT                                           0x0
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE__SHIFT                                           0x1
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE__SHIFT                                           0x2
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE__SHIFT                                           0x3
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE__SHIFT                                           0x4
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE__SHIFT                                           0x5
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE__SHIFT                                        0x8
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE__SHIFT                                             0x9
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE__SHIFT                                        0xa
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE__SHIFT                                             0xb
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE__SHIFT                                        0xc
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE__SHIFT                                             0xd
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE__SHIFT                                        0xe
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE__SHIFT                                             0xf
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE__SHIFT                                        0x14
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE__SHIFT                                             0x15
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE__SHIFT                                        0x16
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE__SHIFT                                             0x17
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE_MASK                                             0x00000001L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE_MASK                                             0x00000002L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE_MASK                                             0x00000004L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE_MASK                                             0x00000008L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE_MASK                                             0x00000010L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE_MASK                                             0x00000020L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE_MASK                                          0x00000100L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE_MASK                                               0x00000200L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE_MASK                                          0x00000400L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE_MASK                                               0x00000800L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE_MASK                                          0x00001000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE_MASK                                               0x00002000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE_MASK                                          0x00004000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE_MASK                                               0x00008000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE_MASK                                          0x00100000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE_MASK                                               0x00200000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE_MASK                                          0x00400000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE_MASK                                               0x00800000L
+//HDMISTREAMCLK0_DTO_PARAM
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE__SHIFT                                             0x0
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO__SHIFT                                            0x8
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN__SHIFT                                                0x10
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE_MASK                                               0x000000FFL
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO_MASK                                              0x0000FF00L
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN_MASK                                                  0x00010000L
+//DCCG_AUDIO_DTBCLK_DTO_PHASE
+#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE__SHIFT                                       0x0
+#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE_MASK                                         0xFFFFFFFFL
+//DCCG_AUDIO_DTBCLK_DTO_MODULO
+#define DCCG_AUDIO_DTBCLK_DTO_MODULO__DCCG_AUDIO_DTBCLK_DTO_MODULO__SHIFT                                     0x0
+#define DCCG_AUDIO_DTBCLK_DTO_MODULO__DCCG_AUDIO_DTBCLK_DTO_MODULO_MASK                                       0xFFFFFFFFL
+//DTBCLK_DTO_DBUF_EN
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO0_DBUF_EN__SHIFT                                                        0x0
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO1_DBUF_EN__SHIFT                                                        0x1
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO2_DBUF_EN__SHIFT                                                        0x2
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO3_DBUF_EN__SHIFT                                                        0x3
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO0_DBUF_EN_MASK                                                          0x00000001L
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO1_DBUF_EN_MASK                                                          0x00000002L
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO2_DBUF_EN_MASK                                                          0x00000004L
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO3_DBUF_EN_MASK                                                          0x00000008L
+//DMCUBCLK_CNTL
+#define DMCUBCLK_CNTL__DMCUBCLK_SRC_SEL__SHIFT                                                                0x0
+#define DMCUBCLK_CNTL__DMCUBCLK_SRC_SEL_MASK                                                                  0x00000003L
+
+
+// addressBlock: dce_dc_dmu_rbbmif_dispdec
+//RBBMIF_TIMEOUT
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT                                                           0x0
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT                                                     0x14
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK                                                             0x000FFFFFL
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK                                                       0xFFF00000L
+//RBBMIF_STATUS
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT                                                      0x0
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK                                                        0xFFFFFFFFL
+//RBBMIF_STATUS_2
+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2__SHIFT                                                  0x0
+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2_MASK                                                    0x0000007FL
+//RBBMIF_INT_STATUS
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR__SHIFT                                                         0x2
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT                                                           0x1c
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT                                                  0x1d
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT                                                          0x1e
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT                                                         0x1f
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR_MASK                                                           0x0003FFFCL
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK                                                             0x10000000L
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK                                                    0x20000000L
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK                                                            0x40000000L
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK                                                           0x80000000L
+//RBBMIF_TIMEOUT_DIS
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT                                                        0x0
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT                                                        0x1
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT                                                        0x2
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT                                                        0x3
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT                                                        0x4
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT                                                        0x5
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT                                                        0x6
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT                                                        0x7
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT                                                        0x8
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT                                                        0x9
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT                                                       0xa
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT                                                       0xb
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT                                                       0xc
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT                                                       0xd
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT                                                       0xe
+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT                                                       0xf
+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT                                                       0x10
+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT                                                       0x11
+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT                                                       0x12
+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT                                                       0x13
+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT                                                       0x14
+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT                                                       0x15
+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT                                                       0x16
+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT                                                       0x17
+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT                                                       0x18
+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT                                                       0x19
+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT                                                       0x1a
+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT                                                       0x1b
+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT                                                       0x1c
+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT                                                       0x1d
+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS__SHIFT                                                       0x1e
+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS__SHIFT                                                       0x1f
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK                                                          0x00000001L
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK                                                          0x00000002L
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK                                                          0x00000004L
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK                                                          0x00000008L
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK                                                          0x00000010L
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK                                                          0x00000020L
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK                                                          0x00000040L
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK                                                          0x00000080L
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK                                                          0x00000100L
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK                                                          0x00000200L
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK                                                         0x00000400L
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK                                                         0x00000800L
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK                                                         0x00001000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK                                                         0x00002000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK                                                         0x00004000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK                                                         0x00008000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK                                                         0x00010000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK                                                         0x00020000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK                                                         0x00040000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK                                                         0x00080000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK                                                         0x00100000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK                                                         0x00200000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK                                                         0x00400000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK                                                         0x00800000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK                                                         0x01000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK                                                         0x02000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK                                                         0x04000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK                                                         0x08000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK                                                         0x10000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK                                                         0x20000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS_MASK                                                         0x40000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS_MASK                                                         0x80000000L
+//RBBMIF_TIMEOUT_DIS_2
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS__SHIFT                                                     0x0
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS__SHIFT                                                     0x1
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS__SHIFT                                                     0x2
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS__SHIFT                                                     0x3
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS__SHIFT                                                     0x4
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS__SHIFT                                                     0x5
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS__SHIFT                                                     0x6
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS_MASK                                                       0x00000001L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS_MASK                                                       0x00000002L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS_MASK                                                       0x00000004L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS_MASK                                                       0x00000008L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS_MASK                                                       0x00000010L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS_MASK                                                       0x00000020L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS_MASK                                                       0x00000040L
+//RBBMIF_STATUS_FLAG
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT                                                               0x0
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT                                                        0x4
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT                                                          0x5
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT                                                           0x6
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT                                                 0x8
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT                                                 0x9
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT                                                 0x10
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK                                                                 0x00000003L
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK                                                          0x00000010L
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK                                                            0x00000020L
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK                                                             0x00000040L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK                                                   0x00000100L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK                                                   0x00000E00L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK                                                   0xFFFF0000L
+
+
+// addressBlock: dce_dc_dmu_ihc_dispdec
+//DC_GPU_TIMER_START_POSITION_V_UPDATE
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT                  0x0
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT                  0x4
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT                  0x8
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT                  0xc
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT                  0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT                  0x14
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK                    0x00000007L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK                    0x00000070L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK                    0x00000700L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK                    0x00007000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK                    0x00070000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK                    0x00700000L
+//DC_GPU_TIMER_START_POSITION_VSTARTUP
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT                  0x0
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT                  0x4
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT                  0x8
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT                  0xc
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT                  0x10
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT                  0x14
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK                    0x00000007L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK                    0x00000070L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK                    0x00000700L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK                    0x00007000L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK                    0x00070000L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK                    0x00700000L
+//DC_GPU_TIMER_READ
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT                                                           0x0
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK                                                             0xFFFFFFFFL
+//DC_GPU_TIMER_READ_CNTL
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT                                               0x0
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT                               0x8
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT                               0xb
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT                               0xe
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT                               0x11
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT                               0x14
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT                               0x17
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK                                                 0x0000007FL
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK                                 0x00000700L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK                                 0x00003800L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK                                 0x0001C000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK                                 0x000E0000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK                                 0x00700000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK                                 0x03800000L
+//DISP_INTERRUPT_STATUS
+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT                                          0x1
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT                                             0x4
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                                0x5
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                                      0x6
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT                                                0x7
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT                                                0x8
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                            0x9
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                              0xa
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                                0xf
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                                    0x10
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT                                                       0x11
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT                                                    0x12
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT                                                  0x13
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT                                                  0x14
+#define DISP_INTERRUPT_STATUS__DIO_ALPM_INTERRUPT__SHIFT                                                      0x15
+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT                                            0x17
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT                                                0x18
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT                                          0x1f
+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK                                            0x00000002L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK                                               0x00000010L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                                  0x00000020L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                                        0x00000040L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK                                                  0x00000080L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK                                                  0x00000100L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK                                              0x00000200L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                                0x00000400L
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                                  0x00008000L
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                                      0x00010000L
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK                                                         0x00020000L
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK                                                      0x00040000L
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK                                                    0x00080000L
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK                                                    0x00100000L
+#define DISP_INTERRUPT_STATUS__DIO_ALPM_INTERRUPT_MASK                                                        0x00200000L
+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK                                              0x00800000L
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK                                                  0x01000000L
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK                                            0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE
+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT                                 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT                                    0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                       0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                             0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT                                       0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT                                       0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                   0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                     0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                       0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                           0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT                                              0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT                                           0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT                                         0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT                                         0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT                                   0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT                                   0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT                                0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK                                   0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK                                      0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                         0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                               0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK                                         0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK                                         0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK                                     0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                       0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                         0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                             0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK                                                0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK                                             0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK                                           0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK                                           0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK                                     0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK                                     0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK                                  0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE2
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE3
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK                                  0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE5
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK                                    0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK                                    0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK                                    0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE6
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT                                      0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT                                      0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT                                      0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT                                      0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT                                      0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK                                        0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK                                        0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK                                        0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK                                        0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK                                        0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE7
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE8
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE9
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT                              0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK                                  0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK                                  0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK                                0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE10
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT                                0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT                                0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT                                0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT                                0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT                                0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK                                  0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK                                  0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK                                  0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK                                  0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK                                  0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE_MASK                                     0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE_MASK                                     0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE_MASK                                     0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE_MASK                                     0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE_MASK                                     0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE11
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT                                        0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT                                        0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT                                        0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT                                        0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT                                        0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT                                        0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT__SHIFT                                    0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK                                          0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK                                          0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK                                          0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK                                          0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK                                          0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK                                          0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT_MASK                                      0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE12
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE13
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT                                0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT__SHIFT                                 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT__SHIFT                     0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT                          0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT                          0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT                          0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT                          0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT                          0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT                          0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT                          0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK                                  0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT_MASK                                   0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_MASK                       0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK                            0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK                            0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK                            0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK                            0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK                            0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK                            0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK                            0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE14
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE15
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE16
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT                                   0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT                                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT                                   0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT                                   0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT                                    0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT                                   0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT                                   0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT                                    0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT                                   0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT                                   0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT                                    0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT                                   0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT                                   0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT                                    0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT                                   0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK                                     0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK                                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK                                     0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK                                     0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK                                      0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK                                     0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK                                     0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK                                      0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK                                     0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK                                     0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK                                      0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK                                     0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK                                     0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK                                      0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK                                     0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT_MASK                                    0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT_MASK                                    0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT_MASK                                    0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT_MASK                                    0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE17
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT                                     0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT                                     0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT                                     0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT                                     0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT                                     0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT                                     0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT                                     0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT                                     0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK                                       0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK                                       0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK                                       0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK                                       0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK                                       0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK                                       0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK                                       0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK                                       0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE18
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT                            0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT                            0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT                            0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT                            0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT                            0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT                            0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT                            0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT                            0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT                        0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT                        0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT                        0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT                        0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT                        0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT                        0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK                              0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK                              0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK                              0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK                              0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK                              0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK                              0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK                              0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK                              0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK                          0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK                          0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK                          0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK                          0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK                          0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK                          0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE19
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT                           0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT                           0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT                           0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT                           0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT                           0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT                           0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT                           0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT                           0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT                          0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT                          0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT                          0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT                          0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT                          0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT                          0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK                             0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK                             0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK                             0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK                             0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK                             0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK                             0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK                             0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK                             0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK                            0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK                            0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK                            0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK                            0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK                            0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK                            0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE20
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT                                    0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT                                    0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT                                    0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT                                    0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT                                    0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK                                      0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK                                      0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK                                      0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK                                      0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK                                      0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE21
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT                          0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT                          0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT                          0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT                          0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT                          0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT                          0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT                        0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT                           0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT                           0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT                           0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT                           0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT                           0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT                           0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT                            0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK                            0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK                            0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK                            0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK                            0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK                            0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK                            0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK                          0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK                             0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK                             0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK                             0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK                             0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK                             0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK                             0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK                              0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE22
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK                               0x80000000L
+//DC_GPU_TIMER_START_POSITION_VREADY
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT                      0x0
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT                      0x4
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT                      0x8
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT                      0xc
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT                      0x10
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT                      0x14
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK                        0x00000007L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK                        0x00000070L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK                        0x00000700L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK                        0x00007000L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK                        0x00070000L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK                        0x00700000L
+//DC_GPU_TIMER_START_POSITION_FLIP
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT                          0x0
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT                          0x4
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT                          0x8
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT                          0xc
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT                          0x10
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT                          0x14
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT                          0x18
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT                          0x1c
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK                            0x00000007L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK                            0x00000070L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK                            0x00000700L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK                            0x00007000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK                            0x00070000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK                            0x00700000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK                            0x07000000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK                            0x70000000L
+//DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT  0x0
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT  0x4
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT  0x8
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT  0xc
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT  0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT  0x14
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK    0x00000007L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK    0x00000070L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK    0x00000700L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK    0x00007000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK    0x00070000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK    0x00700000L
+//DC_GPU_TIMER_START_POSITION_FLIP_AWAY
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT                0x0
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT                0x4
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT                0x8
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT                0xc
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT                0x10
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT                0x14
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT                0x18
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT                0x1c
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK                  0x00000007L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK                  0x00000070L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK                  0x00000700L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK                  0x00007000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK                  0x00070000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK                  0x00700000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK                  0x07000000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK                  0x70000000L
+//DISP_INTERRUPT_STATUS_CONTINUE23
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT                         0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT                         0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT                         0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT                         0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT                         0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT                         0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT                       0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT                       0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT                       0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT                       0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT                       0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT                       0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK                           0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK                           0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK                           0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK                           0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK                           0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK                           0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK                         0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK                         0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK                         0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK                         0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK                         0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK                         0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE24
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT                          0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT                           0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                    0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                     0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                     0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                      0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                   0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                    0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                    0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                     0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT                              0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT                              0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN2_INTERRUPT__SHIFT                              0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN3_INTERRUPT__SHIFT                              0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN4_INTERRUPT__SHIFT                              0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN5_INTERRUPT__SHIFT                              0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN6_INTERRUPT__SHIFT                              0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT                              0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT                      0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK                            0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK                             0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                      0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                       0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                       0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                        0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                     0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                      0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                      0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                       0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK                                0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK                                0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN2_INTERRUPT_MASK                                0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN3_INTERRUPT_MASK                                0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN4_INTERRUPT_MASK                                0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN5_INTERRUPT_MASK                                0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN6_INTERRUPT_MASK                                0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK                                0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK                        0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE25
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DPIA_INTERRUPT__SHIFT                                               0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_WHITELIST_INVALID_ACCESS_INTERRUPT__SHIFT                     0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE25__MMHUBBUB_WARMUP_INTERRUPT__SHIFT                                    0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DPIA_INTERRUPT_MASK                                                 0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_WHITELIST_INVALID_ACCESS_INTERRUPT_MASK                       0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__MMHUBBUB_WARMUP_INTERRUPT_MASK                                      0x40000000L
+//DCCG_INTERRUPT_DEST
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT                                        0x0
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT                                        0x1
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT                                        0x2
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT                                        0x3
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT                                        0x4
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT                                        0x5
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK                                          0x00000001L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK                                          0x00000002L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK                                          0x00000004L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK                                          0x00000008L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK                                          0x00000010L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK                                          0x00000020L
+//DMU_INTERRUPT_DEST
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT                                                  0x0
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT                                                  0x1
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT                                                  0x2
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT                                                  0x3
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT                                                  0x4
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT3_INT_DEST__SHIFT                                                  0x5
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT4_INT_DEST__SHIFT                                                  0x6
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT5_INT_DEST__SHIFT                                                  0x7
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT6_INT_DEST__SHIFT                                                  0x8
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT_IH_INT_DEST__SHIFT                                                0x9
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT                                            0xa
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT                                             0xb
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT                                            0xc
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT                                             0xd
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT                                           0xe
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT                                            0xf
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT                                           0x10
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT                                            0x11
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT                                 0x1a
+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                          0x1b
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK                                                    0x00000001L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK                                                    0x00000002L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK                                                    0x00000004L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK                                                    0x00000008L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK                                                    0x00000010L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT3_INT_DEST_MASK                                                    0x00000020L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT4_INT_DEST_MASK                                                    0x00000040L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT5_INT_DEST_MASK                                                    0x00000080L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT6_INT_DEST_MASK                                                    0x00000100L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT_IH_INT_DEST_MASK                                                  0x00000200L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK                                              0x00000400L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK                                               0x00000800L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK                                              0x00001000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK                                               0x00002000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK                                             0x00004000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK                                              0x00008000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK                                             0x00010000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK                                              0x00020000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK                                   0x04000000L
+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                            0x08000000L
+//DMU_INTERRUPT_DEST2
+#define DMU_INTERRUPT_DEST2__DPIA_IHC_INTERRUPT_DEST__SHIFT                                                   0xc
+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_WHITELIST_INVALID_ACCESS_INTERRUPT_DEST__SHIFT                         0xd
+#define DMU_INTERRUPT_DEST2__DPIA_IHC_INTERRUPT_DEST_MASK                                                     0x00001000L
+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_WHITELIST_INVALID_ACCESS_INTERRUPT_DEST_MASK                           0x00002000L
+//DCPG_INTERRUPT_DEST
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x0
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x1
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x2
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x3
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x4
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x5
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x6
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x7
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x10
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x11
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x12
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x13
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x14
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x15
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x16
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x17
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000001L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000002L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000004L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000008L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000010L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000020L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000040L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000080L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00010000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00020000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00040000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00080000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00100000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00200000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00400000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00800000L
+//DCPG_INTERRUPT_DEST2
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT                                0x0
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT                                0x1
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT                                0x2
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT                                0x3
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT                                0x4
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT                                0x5
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x6
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x7
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x8
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x9
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xa
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xb
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000001L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000002L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000004L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000008L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000010L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000020L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000040L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000080L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000100L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000200L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000400L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000800L
+//MMHUBBUB_INTERRUPT_DEST
+#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST__SHIFT                                        0x0
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x1
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x2
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x3
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x4
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST__SHIFT                                       0x5
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST__SHIFT                                    0x8
+#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST_MASK                                          0x00000001L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000002L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000004L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000008L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000010L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST_MASK                                         0x00000020L
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST_MASK                                      0x00000100L
+//WB_INTERRUPT_DEST
+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x1
+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x9
+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0xb
+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000002L
+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000200L
+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000800L
+//DCHUB_INTERRUPT_DEST
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x0
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x2
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x3
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x4
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x5
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x6
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x7
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x8
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x9
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xa
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xb
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0xc
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0xd
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xe
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xf
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x10
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x11
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x12
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x13
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x14
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x15
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x16
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x17
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x18
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x19
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1a
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1b
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x1c
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1d
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1e
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1f
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000001L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000002L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000004L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000008L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000010L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000020L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000040L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000080L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000100L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000200L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000400L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000800L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00001000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00002000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00004000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00008000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00010000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00020000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00040000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00080000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00100000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00200000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00400000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00800000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x01000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x02000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x04000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x08000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x10000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x20000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x40000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x80000000L
+//DCHUB_PERFCOUNTER_INTERRUPT_DEST
+//DCHUB_INTERRUPT_DEST2
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x0
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x1
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x2
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x3
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x4
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x5
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x6
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x7
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x8
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x9
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xa
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xb
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xc
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xd
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xe
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xf
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT                                      0x18
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                       0x19
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST__SHIFT                           0x1a
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000001L
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000002L
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000004L
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000008L
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000010L
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000020L
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000040L
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000080L
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000100L
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000200L
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000400L
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000800L
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00001000L
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00002000L
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00004000L
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00008000L
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK                                        0x01000000L
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                         0x02000000L
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST_MASK                             0x04000000L
+//DPP_PERFCOUNTER_INTERRUPT_DEST
+//MPC_INTERRUPT_DEST
+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST__SHIFT                                                 0x0
+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST__SHIFT                                                 0x1
+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST__SHIFT                                                 0x2
+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST__SHIFT                                                 0x3
+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST__SHIFT                                                 0x4
+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST__SHIFT                                                 0x5
+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST__SHIFT                                                 0x6
+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST__SHIFT                                                 0x7
+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST_MASK                                                   0x00000001L
+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST_MASK                                                   0x00000002L
+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST_MASK                                                   0x00000004L
+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST_MASK                                                   0x00000008L
+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST_MASK                                                   0x00000010L
+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST_MASK                                                   0x00000020L
+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST_MASK                                                   0x00000040L
+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST_MASK                                                   0x00000080L
+//OPP_INTERRUPT_DEST
+//OPTC_INTERRUPT_DEST
+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x18
+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x19
+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1a
+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1b
+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1c
+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1d
+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x01000000L
+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x02000000L
+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x04000000L
+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x08000000L
+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x10000000L
+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x20000000L
+//OTG0_INTERRUPT_DEST
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG1_INTERRUPT_DEST
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG2_INTERRUPT_DEST
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG3_INTERRUPT_DEST
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG4_INTERRUPT_DEST
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG5_INTERRUPT_DEST
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//DIG_INTERRUPT_DEST
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x0
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x1
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x2
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x3
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x4
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x5
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x6
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x7
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x8
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x9
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xa
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xb
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xc
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xd
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xe
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xf
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000001L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000002L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000004L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000008L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000010L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000020L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000040L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000080L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000100L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000200L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000400L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000800L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00001000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00002000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00004000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00008000L
+//I2C_DDC_HPD_INTERRUPT_DEST
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT                                0x0
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT                           0x1
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT                           0x2
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT                           0x3
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT                           0x4
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT                           0x5
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT                           0x6
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT                         0x7
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x10
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x11
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x12
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x13
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x14
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x15
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT                          0x16
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK                                  0x00000001L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK                             0x00000002L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK                             0x00000004L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK                             0x00000008L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK                             0x00000010L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK                             0x00000020L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK                             0x00000040L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK                           0x00000080L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00010000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00020000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00040000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00080000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00100000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00200000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK                            0x00400000L
+//DIO_INTERRUPT_DEST
+#define DIO_INTERRUPT_DEST__DIO_ALPM_INTERRUPT_DEST__SHIFT                                                    0x4
+#define DIO_INTERRUPT_DEST__DIO_ALPM_INTERRUPT_DEST_MASK                                                      0x00000010L
+//DCIO_INTERRUPT_DEST
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x0
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x1
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x2
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x3
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x4
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x5
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x6
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x10
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000001L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000002L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000004L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000008L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000010L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000020L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000040L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00010000L
+//HPD_INTERRUPT_DEST
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT                                               0x0
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT                                               0x1
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT                                               0x2
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT                                               0x3
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT                                               0x4
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT                                               0x5
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT                                            0x8
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT                                            0x9
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT                                            0xa
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT                                            0xb
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT                                            0xc
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT                                            0xd
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK                                                 0x00000001L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK                                                 0x00000002L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK                                                 0x00000004L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK                                                 0x00000008L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK                                                 0x00000010L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK                                                 0x00000020L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK                                              0x00000100L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK                                              0x00000200L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK                                              0x00000400L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK                                              0x00000800L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK                                              0x00001000L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK                                              0x00002000L
+//AZ_INTERRUPT_DEST
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x0
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x1
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x2
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x3
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x4
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x5
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x6
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x7
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x8
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x9
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xa
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xb
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xc
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xd
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xe
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xf
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x10
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x11
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x12
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x13
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x14
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x15
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x16
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x17
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000001L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000002L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000004L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000008L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000010L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000020L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000040L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000080L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000100L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000200L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000400L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000800L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK                                       0x00001000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK                                       0x00002000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK                                       0x00004000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK                                       0x00008000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK                                      0x00010000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK                                      0x00020000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK                                      0x00040000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK                                      0x00080000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK                                      0x00100000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK                                      0x00200000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK                                      0x00400000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK                                      0x00800000L
+//AUX_INTERRUPT_DEST
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x0
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x1
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x2
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x3
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x4
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x5
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x6
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x7
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x8
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x9
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT                                       0xa
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT                                       0xb
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x10
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x11
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x12
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x13
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x14
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x15
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x16
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x17
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x18
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x19
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x1a
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x1b
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000001L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000002L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000004L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000008L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000010L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000020L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000040L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000080L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000100L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000200L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000400L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000800L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00010000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00020000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00040000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00080000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00100000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00200000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00400000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00800000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x01000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x02000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x04000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x08000000L
+//DSC_INTERRUPT_DEST
+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x0
+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x1
+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x4
+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x5
+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x8
+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x9
+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0xc
+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0xd
+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x10
+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x11
+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x14
+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x15
+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000001L
+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000002L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000010L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000020L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000100L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000200L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00001000L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00002000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00010000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00020000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00100000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00200000L
+//HPO_INTERRUPT_DEST
+
+
+// addressBlock: dce_dc_dmu_dmu_misc_dispdec
+//CC_DC_PIPE_DIS
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT                                                                    0x0
+#define CC_DC_PIPE_DIS__DC_FULL_DIS__SHIFT                                                                    0xc
+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE__SHIFT                                                                0x10
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK                                                                      0x000000FFL
+#define CC_DC_PIPE_DIS__DC_FULL_DIS_MASK                                                                      0x00001000L
+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE_MASK                                                                  0x00010000L
+//DMU_CLK_CNTL
+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT                                                                 0x0
+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT                                                           0x4
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT                                                        0x6
+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT                                                               0x8
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT                                                        0xa
+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK                                                                   0x0000000FL
+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK                                                             0x00000010L
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK                                                          0x00000040L
+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK                                                                 0x00000100L
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK                                                          0x00000400L
+//DMCUB_SMU_INTERRUPT_CNTL
+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_INT__SHIFT                                                    0x0
+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG__SHIFT                                                        0x10
+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_INT_MASK                                                      0x00000001L
+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_MASK                                                          0xFFFF0000L
+//SMU_INTERRUPT_CONTROL
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT                                                       0x0
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT                                                       0x4
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT                                                        0x10
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK                                                         0x00000001L
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK                                                         0x00000010L
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK                                                          0xFFFF0000L
+//DMU_MISC_ALLOW_DS_FORCE
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT                                            0x0
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT                                         0x4
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK                                              0x00000001L
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK                                           0x00000010L
+
+
+// addressBlock: dce_dc_dmu_dc_pg_dispdec
+//DOMAIN0_PG_CONFIG
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L
+//DOMAIN0_PG_STATUS
+#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c
+#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e
+#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L
+#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L
+//DOMAIN1_PG_CONFIG
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L
+//DOMAIN1_PG_STATUS
+#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c
+#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e
+#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L
+#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L
+//DOMAIN2_PG_CONFIG
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L
+//DOMAIN2_PG_STATUS
+#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c
+#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e
+#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L
+#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L
+//DOMAIN3_PG_CONFIG
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L
+//DOMAIN3_PG_STATUS
+#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c
+#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e
+#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L
+#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L
+//DOMAIN16_PG_CONFIG
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN16_PG_STATUS
+#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DOMAIN17_PG_CONFIG
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN17_PG_STATUS
+#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DOMAIN18_PG_CONFIG
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN18_PG_STATUS
+#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DOMAIN19_PG_CONFIG
+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN19_PG_STATUS
+#define DOMAIN19_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN19_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DCPG_INTERRUPT_STATUS
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT                                           0x0
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x1
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT                                           0x2
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x3
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT                                           0x4
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x5
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT                                           0x6
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x7
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK                                             0x00000001L
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000002L
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK                                             0x00000004L
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000008L
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK                                             0x00000010L
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000020L
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK                                             0x00000040L
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000080L
+//DCPG_INTERRUPT_STATUS_2
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT                                        0x0
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x1
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT                                        0x2
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x3
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT                                        0x4
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x5
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT                                        0x6
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x7
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED_MASK                                          0x00000001L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000002L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED_MASK                                          0x00000004L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000008L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED_MASK                                          0x00000010L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000020L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED_MASK                                          0x00000040L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000080L
+//DCPG_INTERRUPT_CONTROL_1
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT                                            0x0
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT                                           0x1
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT                                          0x2
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT                                         0x3
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT                                            0x4
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT                                           0x5
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT                                          0x6
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT                                         0x7
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT                                            0x8
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT                                           0x9
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT                                          0xa
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT                                         0xb
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT                                            0xc
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT                                           0xd
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT                                          0xe
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT                                         0xf
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK                                              0x00000001L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK                                             0x00000002L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK                                            0x00000004L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK                                           0x00000008L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK                                              0x00000010L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK                                             0x00000020L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK                                            0x00000040L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK                                           0x00000080L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK                                              0x00000100L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK                                             0x00000200L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK                                            0x00000400L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK                                           0x00000800L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK                                              0x00001000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK                                             0x00002000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK                                            0x00004000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK                                           0x00008000L
+//DCPG_INTERRUPT_CONTROL_3
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK__SHIFT                                           0x0
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR__SHIFT                                          0x1
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK__SHIFT                                         0x2
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT                                        0x3
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK__SHIFT                                           0x4
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR__SHIFT                                          0x5
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK__SHIFT                                         0x6
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT                                        0x7
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK__SHIFT                                           0x8
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR__SHIFT                                          0x9
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK__SHIFT                                         0xa
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT                                        0xb
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK__SHIFT                                           0xc
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR__SHIFT                                          0xd
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK__SHIFT                                         0xe
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT                                        0xf
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK_MASK                                             0x00000001L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR_MASK                                            0x00000002L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK_MASK                                           0x00000004L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR_MASK                                          0x00000008L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK_MASK                                             0x00000010L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR_MASK                                            0x00000020L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK_MASK                                           0x00000040L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR_MASK                                          0x00000080L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK_MASK                                             0x00000100L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR_MASK                                            0x00000200L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK_MASK                                           0x00000400L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR_MASK                                          0x00000800L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK_MASK                                             0x00001000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR_MASK                                            0x00002000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK_MASK                                           0x00004000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR_MASK                                          0x00008000L
+//DC_IP_REQUEST_CNTL
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT                                                              0x0
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK                                                                0x00000001L
+
+
+// addressBlock: dce_dc_dmu_dmcub_dispdec
+//DMCUB_REGION0_OFFSET
+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION0_OFFSET_HIGH
+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION1_OFFSET
+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION1_OFFSET_HIGH
+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION2_OFFSET
+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION2_OFFSET_HIGH
+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION4_OFFSET
+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION4_OFFSET_HIGH
+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION5_OFFSET
+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION5_OFFSET_HIGH
+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION6_OFFSET
+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION6_OFFSET_HIGH
+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION7_OFFSET
+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION7_OFFSET_HIGH
+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION0_TOP_ADDRESS
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION1_TOP_ADDRESS
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION2_TOP_ADDRESS
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION4_TOP_ADDRESS
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION5_TOP_ADDRESS
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION6_TOP_ADDRESS
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION7_TOP_ADDRESS
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION3_CW0_BASE_ADDRESS
+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW1_BASE_ADDRESS
+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW2_BASE_ADDRESS
+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW3_BASE_ADDRESS
+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW4_BASE_ADDRESS
+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW5_BASE_ADDRESS
+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW6_BASE_ADDRESS
+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW7_BASE_ADDRESS
+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW0_TOP_ADDRESS
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW1_TOP_ADDRESS
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW2_TOP_ADDRESS
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW3_TOP_ADDRESS
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW4_TOP_ADDRESS
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW5_TOP_ADDRESS
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW6_TOP_ADDRESS
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW7_TOP_ADDRESS
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW0_OFFSET
+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW0_OFFSET_HIGH
+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW1_OFFSET
+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW1_OFFSET_HIGH
+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW2_OFFSET
+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW2_OFFSET_HIGH
+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW3_OFFSET
+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW3_OFFSET_HIGH
+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW4_OFFSET
+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW4_OFFSET_HIGH
+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW5_OFFSET
+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW5_OFFSET_HIGH
+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW6_OFFSET
+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW6_OFFSET_HIGH
+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW7_OFFSET
+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW7_OFFSET_HIGH
+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_INTERRUPT_ENABLE
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT                                                    0x0
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT                                                    0x1
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT                                              0x2
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT                                               0x3
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT                                              0x4
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT                                               0x5
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT                                             0x6
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT                                              0x7
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT                                             0x8
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT                                              0x9
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT                                                    0xa
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT                                                    0xb
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT                                                    0xc
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT3_INT_EN__SHIFT                                                    0xd
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT4_INT_EN__SHIFT                                                    0xe
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT5_INT_EN__SHIFT                                                    0xf
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT6_INT_EN__SHIFT                                                    0x10
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN__SHIFT                                                  0x11
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT                                   0x12
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK                                                      0x00000001L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK                                                      0x00000002L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK                                                0x00000004L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK                                                 0x00000008L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK                                                0x00000010L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK                                                 0x00000020L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK                                               0x00000040L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK                                                0x00000080L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK                                               0x00000100L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK                                                0x00000200L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK                                                      0x00000400L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK                                                      0x00000800L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK                                                      0x00001000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT3_INT_EN_MASK                                                      0x00002000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT4_INT_EN_MASK                                                      0x00004000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT5_INT_EN_MASK                                                      0x00008000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT6_INT_EN_MASK                                                      0x00010000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN_MASK                                                    0x00020000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK                                     0x00040000L
+//DMCUB_INTERRUPT_ACK
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT                                                      0x0
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT                                                      0x1
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT                                                0x2
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT                                                 0x3
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT                                                0x4
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT                                                 0x5
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT                                               0x6
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT                                                0x7
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT                                               0x8
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT                                                0x9
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT                                                      0xa
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT                                                      0xb
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT                                                      0xc
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT3_INT_ACK__SHIFT                                                      0xd
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT4_INT_ACK__SHIFT                                                      0xe
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT5_INT_ACK__SHIFT                                                      0xf
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT6_INT_ACK__SHIFT                                                      0x10
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK__SHIFT                                                    0x11
+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT                                         0x12
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK                                                        0x00000001L
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK                                                        0x00000002L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK                                                  0x00000004L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK                                                   0x00000008L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK                                                  0x00000010L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK                                                   0x00000020L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK                                                 0x00000040L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK                                                  0x00000080L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK                                                 0x00000100L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK                                                  0x00000200L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK                                                        0x00000400L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK                                                        0x00000800L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK                                                        0x00001000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT3_INT_ACK_MASK                                                        0x00002000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT4_INT_ACK_MASK                                                        0x00004000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT5_INT_ACK_MASK                                                        0x00008000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT6_INT_ACK_MASK                                                        0x00010000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK_MASK                                                      0x00020000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK                                           0x00040000L
+//DMCUB_INTERRUPT_STATUS
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT                                                  0x0
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT                                                  0x1
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT                                            0x2
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT                                             0x3
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT                                            0x4
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT                                             0x5
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT                                           0x6
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT                                            0x7
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT                                           0x8
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT                                            0x9
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT                                                  0xa
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT                                                  0xb
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT                                                  0xc
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT3_INT_STAT__SHIFT                                                  0xd
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT4_INT_STAT__SHIFT                                                  0xe
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT5_INT_STAT__SHIFT                                                  0xf
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT6_INT_STAT__SHIFT                                                  0x10
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT_IH_INT_STAT__SHIFT                                                0x11
+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT                                          0x12
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT                                                 0x13
+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT                                                 0x14
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK                                                    0x00000001L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK                                                    0x00000002L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK                                              0x00000004L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK                                               0x00000008L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK                                              0x00000010L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK                                               0x00000020L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK                                             0x00000040L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK                                              0x00000080L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK                                             0x00000100L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK                                              0x00000200L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK                                                    0x00000400L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK                                                    0x00000800L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK                                                    0x00001000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT3_INT_STAT_MASK                                                    0x00002000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT4_INT_STAT_MASK                                                    0x00004000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT5_INT_STAT_MASK                                                    0x00008000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT6_INT_STAT_MASK                                                    0x00010000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT_IH_INT_STAT_MASK                                                  0x00020000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK                                            0x00040000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK                                                   0x00080000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK                                                   0x00100000L
+//DMCUB_INTERRUPT_TYPE
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT                                                    0x0
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT                                                    0x1
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT                                              0x2
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT                                               0x3
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT                                              0x4
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT                                               0x5
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT                                             0x6
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT                                              0x7
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT                                             0x8
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT                                              0x9
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT                                                    0xa
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT                                                    0xb
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT                                                    0xc
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT3_INT_TYPE__SHIFT                                                    0xd
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT4_INT_TYPE__SHIFT                                                    0xe
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT5_INT_TYPE__SHIFT                                                    0xf
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT6_INT_TYPE__SHIFT                                                    0x10
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT_IH_INT_TYPE__SHIFT                                                  0x11
+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT                                   0x12
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK                                                      0x00000001L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK                                                      0x00000002L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK                                                0x00000004L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK                                                 0x00000008L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK                                                0x00000010L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK                                                 0x00000020L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK                                               0x00000040L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK                                                0x00000080L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK                                               0x00000100L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK                                                0x00000200L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK                                                      0x00000400L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK                                                      0x00000800L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK                                                      0x00001000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT3_INT_TYPE_MASK                                                      0x00002000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT4_INT_TYPE_MASK                                                      0x00004000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT5_INT_TYPE_MASK                                                      0x00008000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT6_INT_TYPE_MASK                                                      0x00010000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT_IH_INT_TYPE_MASK                                                    0x00020000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK                                     0x00040000L
+//DMCUB_EXT_INTERRUPT_STATUS
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT                                          0x0
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT                                             0x8
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK                                            0x000000FFL
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK                                               0x0000FF00L
+//DMCUB_EXT_INTERRUPT_CTXID
+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT                                           0x0
+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK                                             0x0FFFFFFFL
+//DMCUB_EXT_INTERRUPT_ACK
+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT                                               0x0
+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK                                                 0x00000001L
+//DMCUB_INST_FETCH_FAULT_ADDR
+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT                                       0x0
+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK                                         0xFFFFFFFFL
+//DMCUB_DATA_WRITE_FAULT_ADDR
+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT                                       0x0
+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK                                         0xFFFFFFFFL
+//DMCUB_SEC_CNTL
+#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL__SHIFT                                                              0x0
+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT                                                              0x8
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT                                                                0x10
+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT                                                   0x11
+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT                                                        0x14
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT                                                         0x15
+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT                                                   0x18
+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT                                                   0x19
+#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL_MASK                                                                0x00000007L
+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK                                                                0x00003F00L
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK                                                                  0x00010000L
+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK                                                     0x00020000L
+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK                                                          0x00100000L
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK                                                           0x00200000L
+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK                                                     0x01000000L
+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK                                                     0x02000000L
+//DMCUB_MEM_CNTL
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT                                                            0x0
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT                                                             0x4
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK                                                              0x0000000FL
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK                                                               0x000000F0L
+//DMCUB_INBOX0_BASE_ADDRESS
+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT                                           0x0
+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK                                             0xFFFFFFFFL
+//DMCUB_INBOX0_SIZE
+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT                                                           0x0
+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX0_WPTR
+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX0_RPTR
+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX1_BASE_ADDRESS
+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT                                           0x0
+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK                                             0xFFFFFFFFL
+//DMCUB_INBOX1_SIZE
+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT                                                           0x0
+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX1_WPTR
+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX1_RPTR
+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_OUTBOX0_BASE_ADDRESS
+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT                                         0x0
+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK                                           0xFFFFFFFFL
+//DMCUB_OUTBOX0_SIZE
+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT                                                         0x0
+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX0_WPTR
+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX0_RPTR
+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_BASE_ADDRESS
+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT                                         0x0
+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_SIZE
+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT                                                         0x0
+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_WPTR
+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_RPTR
+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_TIMER_TRIGGER0
+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT                                                     0x0
+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK                                                       0xFFFFFFFFL
+//DMCUB_TIMER_TRIGGER1
+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT                                                     0x0
+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK                                                       0xFFFFFFFFL
+//DMCUB_TIMER_WINDOW
+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT                                                         0x0
+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK                                                           0x00000007L
+//DMCUB_SCRATCH0
+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH1
+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH2
+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH3
+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH4
+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH5
+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH6
+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH7
+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH8
+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH9
+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH10
+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT                                                               0x0
+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH11
+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT                                                               0x0
+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH12
+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT                                                               0x0
+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH13
+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT                                                               0x0
+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH14
+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT                                                               0x0
+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH15
+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT                                                               0x0
+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH16
+#define DMCUB_SCRATCH16__DMCUB_SCRATCH16__SHIFT                                                               0x0
+#define DMCUB_SCRATCH16__DMCUB_SCRATCH16_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH17
+#define DMCUB_SCRATCH17__DMCUB_SCRATCH17__SHIFT                                                               0x0
+#define DMCUB_SCRATCH17__DMCUB_SCRATCH17_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH18
+#define DMCUB_SCRATCH18__DMCUB_SCRATCH18__SHIFT                                                               0x0
+#define DMCUB_SCRATCH18__DMCUB_SCRATCH18_MASK                                                                 0xFFFFFFFFL
+//DMCUB_CNTL
+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT                                                                0x0
+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT                                                          0x8
+#define DMCUB_CNTL__DMCUB_ENABLE__SHIFT                                                                       0x10
+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT                                                      0x12
+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT                                                                 0x13
+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT                                                            0x14
+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK                                                                  0x000000FFL
+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK                                                            0x00000100L
+#define DMCUB_CNTL__DMCUB_ENABLE_MASK                                                                         0x00010000L
+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK                                                        0x00040000L
+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK                                                                   0x00080000L
+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK                                                              0x00100000L
+//DMCUB_GPINT_DATAIN0
+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAIN1
+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAOUT
+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK                                                         0xFFFFFFFFL
+//DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR
+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT                         0x0
+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK                           0xFFFFFFFFL
+//DMCUB_LS_WAKE_INT_ENABLE
+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT                                             0x0
+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK                                               0xFFFFFFFFL
+//DMCUB_MEM_PWR_CNTL
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT                                                        0x1
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT                                                          0x3
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT                                                        0x4
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK                                                          0x00000006L
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK                                                            0x00000008L
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK                                                          0x00000030L
+//DMCUB_TIMER_CURRENT
+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT                                                       0x0
+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK                                                         0xFFFFFFFFL
+//DMCUB_PROC_ID
+#define DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT                                                                   0x0
+#define DMCUB_PROC_ID__DMCUB_PROC_ID_MASK                                                                     0x0000FFFFL
+//DMCUB_CNTL2
+#define DMCUB_CNTL2__DMCUB_SOFT_RESET__SHIFT                                                                  0x0
+#define DMCUB_CNTL2__DMCUB_SOFT_RESET_MASK                                                                    0x00000001L
+//DMCUB_GPINT_DATAIN2
+#define DMCUB_GPINT_DATAIN2__DMCUB_GPINT_DATAIN2__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN2__DMCUB_GPINT_DATAIN2_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAIN3
+#define DMCUB_GPINT_DATAIN3__DMCUB_GPINT_DATAIN3__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN3__DMCUB_GPINT_DATAIN3_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAIN4
+#define DMCUB_GPINT_DATAIN4__DMCUB_GPINT_DATAIN4__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN4__DMCUB_GPINT_DATAIN4_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAIN5
+#define DMCUB_GPINT_DATAIN5__DMCUB_GPINT_DATAIN5__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN5__DMCUB_GPINT_DATAIN5_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAIN6
+#define DMCUB_GPINT_DATAIN6__DMCUB_GPINT_DATAIN6__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN6__DMCUB_GPINT_DATAIN6_MASK                                                         0xFFFFFFFFL
+//DMCUB_REGION3_TMR_AXI_SPACE
+#define DMCUB_REGION3_TMR_AXI_SPACE__DMCUB_REGION3_TMR_AXI_SPACE__SHIFT                                       0x0
+#define DMCUB_REGION3_TMR_AXI_SPACE__DMCUB_REGION3_TMR_AXI_SPACE_MASK                                         0x07L
+//DMCUB_SCRATCH19
+#define DMCUB_SCRATCH19__DMCUB_SCRATCH19__SHIFT                                                               0x0
+#define DMCUB_SCRATCH19__DMCUB_SCRATCH19_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH20
+#define DMCUB_SCRATCH20__DMCUB_SCRATCH20__SHIFT                                                               0x0
+#define DMCUB_SCRATCH20__DMCUB_SCRATCH20_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH21
+#define DMCUB_SCRATCH21__DMCUB_SCRATCH21__SHIFT                                                               0x0
+#define DMCUB_SCRATCH21__DMCUB_SCRATCH21_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH22
+#define DMCUB_SCRATCH22__DMCUB_SCRATCH22__SHIFT                                                               0x0
+#define DMCUB_SCRATCH22__DMCUB_SCRATCH22_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH23
+#define DMCUB_SCRATCH23__DMCUB_SCRATCH23__SHIFT                                                               0x0
+#define DMCUB_SCRATCH23__DMCUB_SCRATCH23_MASK                                                                 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec
+//DWB_ENABLE_CLK_CTRL
+#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE__SHIFT                                                                0x0
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS__SHIFT                                                    0x4
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS__SHIFT                                                    0x8
+#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL__SHIFT                                                          0xc
+#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE_MASK                                                                  0x00000001L
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS_MASK                                                      0x00000010L
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS_MASK                                                      0x00000100L
+#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL_MASK                                                            0x00003000L
+//DWB_MEM_PWR_CTRL
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE__SHIFT                                                   0xc
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE__SHIFT                                                   0x14
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE_MASK                                                     0x00003000L
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE_MASK                                                     0x00300000L
+//FC_MODE_CTRL
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN__SHIFT                                                              0x0
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE__SHIFT                                                            0x4
+#define FC_MODE_CTRL__FC_WINDOW_CROP_EN__SHIFT                                                                0x8
+#define FC_MODE_CTRL__FC_EYE_SELECTION__SHIFT                                                                 0xc
+#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY__SHIFT                                                           0x10
+#define FC_MODE_CTRL__FC_NEW_CONTENT__SHIFT                                                                   0x14
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT__SHIFT                                                      0x1f
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_MASK                                                                0x00000001L
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE_MASK                                                              0x00000030L
+#define FC_MODE_CTRL__FC_WINDOW_CROP_EN_MASK                                                                  0x00000100L
+#define FC_MODE_CTRL__FC_EYE_SELECTION_MASK                                                                   0x00003000L
+#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY_MASK                                                             0x00010000L
+#define FC_MODE_CTRL__FC_NEW_CONTENT_MASK                                                                     0x00100000L
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT_MASK                                                        0x80000000L
+//FC_FLOW_CTRL
+#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT__SHIFT                                                       0x0
+#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT_MASK                                                         0x00000FFFL
+//FC_WINDOW_START
+#define FC_WINDOW_START__FC_WINDOW_START_X__SHIFT                                                             0x0
+#define FC_WINDOW_START__FC_WINDOW_START_Y__SHIFT                                                             0x10
+#define FC_WINDOW_START__FC_WINDOW_START_X_MASK                                                               0x00001FFFL
+#define FC_WINDOW_START__FC_WINDOW_START_Y_MASK                                                               0x1FFF0000L
+//FC_WINDOW_SIZE
+#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH__SHIFT                                                                0x0
+#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT__SHIFT                                                               0x10
+#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH_MASK                                                                  0x00000FFFL
+#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT_MASK                                                                 0x0FFF0000L
+//FC_SOURCE_SIZE
+#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH__SHIFT                                                                0x0
+#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT__SHIFT                                                               0x10
+#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH_MASK                                                                  0x00007FFFL
+#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT_MASK                                                                 0x7FFF0000L
+//DWB_UPDATE_CTRL
+#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK__SHIFT                                                               0x0
+#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING__SHIFT                                                            0x4
+#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK_MASK                                                                 0x00000001L
+#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING_MASK                                                              0x00000010L
+//DWB_CRC_CTRL
+#define DWB_CRC_CTRL__DWB_CRC_EN__SHIFT                                                                       0x0
+#define DWB_CRC_CTRL__DWB_CRC_CONT_EN__SHIFT                                                                  0x4
+#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL__SHIFT                                                                  0x8
+#define DWB_CRC_CTRL__DWB_CRC_EN_MASK                                                                         0x00000001L
+#define DWB_CRC_CTRL__DWB_CRC_CONT_EN_MASK                                                                    0x00000010L
+#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL_MASK                                                                    0x00000300L
+//DWB_CRC_MASK_R_G
+#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK__SHIFT                                                             0x0
+#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK__SHIFT                                                           0x10
+#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK_MASK                                                               0x0000FFFFL
+#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK_MASK                                                             0xFFFF0000L
+//DWB_CRC_MASK_B_A
+#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK__SHIFT                                                            0x0
+#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK__SHIFT                                                               0x10
+#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK_MASK                                                              0x0000FFFFL
+#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK_MASK                                                                 0xFFFF0000L
+//DWB_CRC_VAL_R_G
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED__SHIFT                                                               0x0
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN__SHIFT                                                             0x10
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED_MASK                                                                 0x0000FFFFL
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN_MASK                                                               0xFFFF0000L
+//DWB_CRC_VAL_B_A
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE__SHIFT                                                              0x0
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A__SHIFT                                                                 0x10
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE_MASK                                                                0x0000FFFFL
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A_MASK                                                                   0xFFFF0000L
+//DWB_OUT_CTRL
+#define DWB_OUT_CTRL__OUT_FORMAT__SHIFT                                                                       0x0
+#define DWB_OUT_CTRL__OUT_DENORM__SHIFT                                                                       0x4
+#define DWB_OUT_CTRL__OUT_MAX__SHIFT                                                                          0x8
+#define DWB_OUT_CTRL__OUT_MIN__SHIFT                                                                          0x14
+#define DWB_OUT_CTRL__OUT_FORMAT_MASK                                                                         0x00000003L
+#define DWB_OUT_CTRL__OUT_DENORM_MASK                                                                         0x00000030L
+#define DWB_OUT_CTRL__OUT_MAX_MASK                                                                            0x0003FF00L
+#define DWB_OUT_CTRL__OUT_MIN_MASK                                                                            0x3FF00000L
+//DWB_MMHUBBUB_BACKPRESSURE_CNT_EN
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__SHIFT                             0x0
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN_MASK                               0x00000001L
+//DWB_MMHUBBUB_BACKPRESSURE_CNT
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE__SHIFT                                   0x0
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE_MASK                                     0x0000FFFFL
+//DWB_HOST_READ_CONTROL
+#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL__SHIFT                                              0x0
+#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL_MASK                                                0x000000FFL
+//DWB_OVERFLOW_STATUS
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG__SHIFT                                                    0x0
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK__SHIFT                                                     0x8
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK__SHIFT                                                    0xc
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS__SHIFT                                              0x10
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE__SHIFT                                                0x14
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG_MASK                                                      0x00000001L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK_MASK                                                       0x00000100L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK_MASK                                                      0x00001000L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS_MASK                                                0x00010000L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE_MASK                                                  0x00100000L
+//DWB_OVERFLOW_COUNTER
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE__SHIFT                                                   0x0
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT__SHIFT                                              0x4
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT__SHIFT                                              0x10
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE_MASK                                                     0x00000003L
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT_MASK                                                0x0000FFF0L
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT_MASK                                                0x0FFF0000L
+//DWB_SOFT_RESET
+#define DWB_SOFT_RESET__DWB_SOFT_RESET__SHIFT                                                                 0x0
+#define DWB_SOFT_RESET__DWB_SOFT_RESET_MASK                                                                   0x00000001L
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec
+//DWB_HDR_MULT_COEF
+#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF__SHIFT                                                           0x0
+#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF_MASK                                                             0x0007FFFFL
+//DWB_GAMUT_REMAP_MODE
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE__SHIFT                                                     0x0
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT__SHIFT                                             0x18
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_MASK                                                       0x00000003L
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT_MASK                                               0x03000000L
+//DWB_GAMUT_REMAP_COEF_FORMAT
+#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT__SHIFT                                       0x0
+#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT_MASK                                         0x00000001L
+//DWB_GAMUT_REMAPA_C11_C12
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C13_C14
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C21_C22
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C23_C24
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C31_C32
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C33_C34
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C11_C12
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C13_C14
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C21_C22
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C23_C24
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C31_C32
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C33_C34
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34_MASK                                                   0xFFFF0000L
+//DWB_OGAM_CONTROL
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE__SHIFT                                                                0x0
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT__SHIFT                                                              0x4
+#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE__SHIFT                                                         0x8
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT__SHIFT                                                        0x18
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT__SHIFT                                                      0x1c
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_MASK                                                                  0x00000003L
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_MASK                                                                0x00000010L
+#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE_MASK                                                           0x00000100L
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT_MASK                                                          0x03000000L
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT_MASK                                                        0x10000000L
+//DWB_OGAM_LUT_INDEX
+#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX__SHIFT                                                         0x0
+#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX_MASK                                                           0x000001FFL
+//DWB_OGAM_LUT_DATA
+#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA__SHIFT                                                           0x0
+#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA_MASK                                                             0x0003FFFFL
+//DWB_OGAM_LUT_CONTROL
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                                            0x0
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL__SHIFT                                              0x4
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG__SHIFT                                                    0x8
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL__SHIFT                                                    0xc
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE__SHIFT                                                 0x10
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK_MASK                                              0x00000007L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL_MASK                                                0x00000030L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG_MASK                                                      0x00000100L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL_MASK                                                      0x00001000L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE_MASK                                                   0x00010000L
+//DWB_OGAM_RAMA_START_CNTL_B
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B__SHIFT                                   0x0
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                           0x14
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                             0x07F00000L
+//DWB_OGAM_RAMA_START_CNTL_G
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G__SHIFT                                   0x0
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                           0x14
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                             0x07F00000L
+//DWB_OGAM_RAMA_START_CNTL_R
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R__SHIFT                                   0x0
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                           0x14
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                             0x07F00000L
+//DWB_OGAM_RAMA_START_BASE_CNTL_B
+#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                         0x0
+#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMA_START_SLOPE_CNTL_B
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                       0x0
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMA_START_BASE_CNTL_G
+#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                         0x0
+#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMA_START_SLOPE_CNTL_G
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                       0x0
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMA_START_BASE_CNTL_R
+#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                         0x0
+#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMA_START_SLOPE_CNTL_R
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                       0x0
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL1_B
+#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL2_B
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B__SHIFT                                      0x0
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                                0x10
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMA_END_CNTL1_G
+#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL2_G
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G__SHIFT                                      0x0
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                                0x10
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMA_END_CNTL1_R
+#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL2_R
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R__SHIFT                                      0x0
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                                0x10
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMA_OFFSET_B
+#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B__SHIFT                                                 0x0
+#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMA_OFFSET_G
+#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G__SHIFT                                                 0x0
+#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMA_OFFSET_R
+#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R__SHIFT                                                 0x0
+#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMA_REGION_0_1
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_2_3
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_4_5
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_6_7
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_8_9
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_10_11
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_12_13
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_14_15
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_16_17
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_18_19
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_20_21
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_22_23
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_24_25
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_26_27
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_28_29
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_30_31
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_32_33
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_START_CNTL_B
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B__SHIFT                                   0x0
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                           0x14
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                             0x07F00000L
+//DWB_OGAM_RAMB_START_CNTL_G
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G__SHIFT                                   0x0
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                           0x14
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                             0x07F00000L
+//DWB_OGAM_RAMB_START_CNTL_R
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R__SHIFT                                   0x0
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                           0x14
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                             0x07F00000L
+//DWB_OGAM_RAMB_START_BASE_CNTL_B
+#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                         0x0
+#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMB_START_SLOPE_CNTL_B
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                       0x0
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMB_START_BASE_CNTL_G
+#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                         0x0
+#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMB_START_SLOPE_CNTL_G
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                       0x0
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMB_START_BASE_CNTL_R
+#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                         0x0
+#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMB_START_SLOPE_CNTL_R
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                       0x0
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL1_B
+#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL2_B
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B__SHIFT                                      0x0
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                                0x10
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMB_END_CNTL1_G
+#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL2_G
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G__SHIFT                                      0x0
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                                0x10
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMB_END_CNTL1_R
+#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL2_R
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R__SHIFT                                      0x0
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                                0x10
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMB_OFFSET_B
+#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B__SHIFT                                                 0x0
+#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMB_OFFSET_G
+#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G__SHIFT                                                 0x0
+#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMB_OFFSET_R
+#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R__SHIFT                                                 0x0
+#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMB_REGION_0_1
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_2_3
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_4_5
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_6_7
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_8_9
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_10_11
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_12_13
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_14_15
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_16_17
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_18_19
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_20_21
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_22_23
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_24_25
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_26_27
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_28_29
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_30_31
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_32_33
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                              0x70000000L
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec
+//VGA_MEM_WRITE_PAGE_ADDR
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT                                              0x0
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT                                              0x10
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK                                                0x000003FFL
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK                                                0x03FF0000L
+//VGA_MEM_READ_PAGE_ADDR
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT                                                0x0
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT                                                0x10
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK                                                  0x000003FFL
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK                                                  0x03FF0000L
+//VGA_RENDER_CONTROL
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT                                                             0x0
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT                                                             0x5
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT                                                    0x7
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT                                                 0x8
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT                                                           0x10
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT                                                              0x18
+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT                                           0x19
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK                                                               0x0000001FL
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK                                                               0x00000060L
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK                                                      0x00000080L
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK                                                   0x00000100L
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK                                                             0x00030000L
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK                                                                0x01000000L
+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK                                             0x02000000L
+//VGA_SEQUENCER_RESET_CONTROL
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x0
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x1
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x2
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x3
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x4
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x5
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0x8
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0x9
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xa
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xb
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xc
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xd
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT                                      0x10
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT                             0x11
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT                                0x12
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000001L
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000002L
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000004L
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000008L
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000010L
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000020L
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000100L
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000200L
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000400L
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000800L
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00001000L
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00002000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK                                        0x00010000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK                               0x00020000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK                                  0x00FC0000L
+//VGA_MODE_CONTROL
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT                                                               0x0
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT                                                  0x4
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT                                                     0x8
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT                                                      0x10
+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT                                                    0x18
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK                                                                 0x00000001L
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK                                                    0x00000030L
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK                                                       0x00000100L
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK                                                        0x00010000L
+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK                                                      0x01000000L
+//VGA_SURFACE_PITCH_SELECT
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT                                             0x0
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT                                            0x8
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK                                               0x00000003L
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK                                              0x00000300L
+//VGA_MEMORY_BASE_ADDRESS
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT                                               0x0
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK                                                 0xFFFFFFFFL
+//VGA_DISPBUF1_SURFACE_ADDR
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT                                           0x0
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK                                             0x01FFFFFFL
+//VGA_DISPBUF2_SURFACE_ADDR
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT                                           0x0
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK                                             0x01FFFFFFL
+//VGA_MEMORY_BASE_ADDRESS_HIGH
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT                                     0x0
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK                                       0x0000FFFFL
+//VGA_HDP_CONTROL
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT                                                        0x0
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT                                                            0x4
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT                                                         0x8
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT                                                                0x10
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT                                                        0x18
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK                                                          0x00000001L
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK                                                              0x00000010L
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK                                                           0x00000100L
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK                                                                  0x00010000L
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK                                                          0x01000000L
+//VGA_CACHE_CONTROL
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT                                                 0x0
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT                                                      0x8
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT                                                  0x10
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT                                                          0x14
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT                                                        0x18
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK                                                   0x00000001L
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK                                                        0x00000100L
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK                                                    0x00010000L
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK                                                            0x00100000L
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK                                                          0x3F000000L
+//D1VGA_CONTROL
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT                                                                    0x18
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D1VGA_CONTROL__D1VGA_ROTATE_MASK                                                                      0x03000000L
+//D2VGA_CONTROL
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT                                                                    0x18
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D2VGA_CONTROL__D2VGA_ROTATE_MASK                                                                      0x03000000L
+//VGA_STATUS
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT                                                              0x0
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT                                                              0x1
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT                                                          0x2
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT                                                       0x3
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK                                                                0x00000001L
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK                                                                0x00000002L
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK                                                            0x00000004L
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK                                                         0x00000008L
+//VGA_INTERRUPT_CONTROL
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT                                                 0x0
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT                                                 0x8
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT                                             0x10
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT                                          0x18
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK                                                   0x00000001L
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK                                                   0x00000100L
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK                                               0x00010000L
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK                                            0x01000000L
+//VGA_STATUS_CLEAR
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT                                                     0x0
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT                                                     0x8
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT                                                 0x10
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT                                              0x18
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK                                                       0x00000001L
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK                                                       0x00000100L
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK                                                   0x00010000L
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK                                                0x01000000L
+//VGA_INTERRUPT_STATUS
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT                                                0x0
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT                                                0x1
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT                                            0x2
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT                                         0x3
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK                                                  0x00000001L
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK                                                  0x00000002L
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK                                              0x00000004L
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK                                           0x00000008L
+//VGA_MAIN_CONTROL
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT                                                             0x0
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT                                                     0x3
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT                                        0x5
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT                                       0x8
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT                                                0xc
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT                                        0x10
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT                                          0x18
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT                                             0x1a
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT                                                       0x1d
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT                                0x1f
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK                                                               0x00000003L
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK                                                       0x00000018L
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK                                          0x000000E0L
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK                                         0x00000300L
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK                                                  0x0000F000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK                                          0x00030000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK                                            0x03000000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK                                               0x04000000L
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK                                                         0x20000000L
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK                                  0x80000000L
+//VGA_TEST_CONTROL
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT                                                              0x0
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT                                                        0x8
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT                                                         0x10
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT                                               0x18
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK                                                                0x00000001L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK                                                          0x00000100L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK                                                           0x00010000L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK                                                 0x01000000L
+//VGA_QOS_CTRL
+#define VGA_QOS_CTRL__VGA_READ_QOS__SHIFT                                                                     0x0
+#define VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT                                                                    0x4
+#define VGA_QOS_CTRL__VGA_READ_QOS_MASK                                                                       0x0000000FL
+#define VGA_QOS_CTRL__VGA_WRITE_QOS_MASK                                                                      0x000000F0L
+//CRTC8_IDX
+#define CRTC8_IDX__VCRTC_IDX__SHIFT                                                                           0x0
+#define CRTC8_IDX__VCRTC_IDX_MASK                                                                             0x3FL
+//CRTC8_DATA
+#define CRTC8_DATA__VCRTC_DATA__SHIFT                                                                         0x0
+#define CRTC8_DATA__VCRTC_DATA_MASK                                                                           0xFFL
+//GENFC_WT
+#define GENFC_WT__VSYNC_SEL_W__SHIFT                                                                          0x3
+#define GENFC_WT__VSYNC_SEL_W_MASK                                                                            0x08L
+//GENS1
+#define GENS1__NO_DISPLAY__SHIFT                                                                              0x0
+#define GENS1__VGA_VSTATUS__SHIFT                                                                             0x3
+#define GENS1__PIXEL_READ_BACK__SHIFT                                                                         0x4
+#define GENS1__NO_DISPLAY_MASK                                                                                0x01L
+#define GENS1__VGA_VSTATUS_MASK                                                                               0x08L
+#define GENS1__PIXEL_READ_BACK_MASK                                                                           0x30L
+//ATTRDW
+#define ATTRDW__ATTR_DATA__SHIFT                                                                              0x0
+#define ATTRDW__ATTR_DATA_MASK                                                                                0xFFL
+//ATTRX
+#define ATTRX__ATTR_IDX__SHIFT                                                                                0x0
+#define ATTRX__ATTR_PAL_RW_ENB__SHIFT                                                                         0x5
+#define ATTRX__ATTR_IDX_MASK                                                                                  0x1FL
+#define ATTRX__ATTR_PAL_RW_ENB_MASK                                                                           0x20L
+//ATTRDR
+#define ATTRDR__ATTR_DATA__SHIFT                                                                              0x0
+#define ATTRDR__ATTR_DATA_MASK                                                                                0xFFL
+//GENMO_WT
+#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT                                                                 0x0
+#define GENMO_WT__VGA_RAM_EN__SHIFT                                                                           0x1
+#define GENMO_WT__VGA_CKSEL__SHIFT                                                                            0x2
+#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT                                                                    0x5
+#define GENMO_WT__VGA_HSYNC_POL__SHIFT                                                                        0x6
+#define GENMO_WT__VGA_VSYNC_POL__SHIFT                                                                        0x7
+#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK                                                                   0x01L
+#define GENMO_WT__VGA_RAM_EN_MASK                                                                             0x02L
+#define GENMO_WT__VGA_CKSEL_MASK                                                                              0x0CL
+#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK                                                                      0x20L
+#define GENMO_WT__VGA_HSYNC_POL_MASK                                                                          0x40L
+#define GENMO_WT__VGA_VSYNC_POL_MASK                                                                          0x80L
+//GENS0
+#define GENS0__SENSE_SWITCH__SHIFT                                                                            0x4
+#define GENS0__CRT_INTR__SHIFT                                                                                0x7
+#define GENS0__SENSE_SWITCH_MASK                                                                              0x10L
+#define GENS0__CRT_INTR_MASK                                                                                  0x80L
+//GENENB
+#define GENENB__BLK_IO_BASE__SHIFT                                                                            0x0
+#define GENENB__BLK_IO_BASE_MASK                                                                              0xFFL
+//SEQ8_IDX
+#define SEQ8_IDX__SEQ_IDX__SHIFT                                                                              0x0
+#define SEQ8_IDX__SEQ_IDX_MASK                                                                                0x07L
+//SEQ8_DATA
+#define SEQ8_DATA__SEQ_DATA__SHIFT                                                                            0x0
+#define SEQ8_DATA__SEQ_DATA_MASK                                                                              0xFFL
+//DAC_MASK
+#define DAC_MASK__DAC_MASK__SHIFT                                                                             0x0
+#define DAC_MASK__DAC_MASK_MASK                                                                               0xFFL
+//DAC_R_INDEX
+#define DAC_R_INDEX__DAC_R_INDEX__SHIFT                                                                       0x0
+#define DAC_R_INDEX__DAC_R_INDEX_MASK                                                                         0xFFL
+//DAC_W_INDEX
+#define DAC_W_INDEX__DAC_W_INDEX__SHIFT                                                                       0x0
+#define DAC_W_INDEX__DAC_W_INDEX_MASK                                                                         0xFFL
+//DAC_DATA
+#define DAC_DATA__DAC_DATA__SHIFT                                                                             0x0
+#define DAC_DATA__DAC_DATA_MASK                                                                               0x3FL
+//GENFC_RD
+#define GENFC_RD__VSYNC_SEL_R__SHIFT                                                                          0x3
+#define GENFC_RD__VSYNC_SEL_R_MASK                                                                            0x08L
+//GENMO_RD
+#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT                                                                 0x0
+#define GENMO_RD__VGA_RAM_EN__SHIFT                                                                           0x1
+#define GENMO_RD__VGA_CKSEL__SHIFT                                                                            0x2
+#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT                                                                    0x5
+#define GENMO_RD__VGA_HSYNC_POL__SHIFT                                                                        0x6
+#define GENMO_RD__VGA_VSYNC_POL__SHIFT                                                                        0x7
+#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK                                                                   0x01L
+#define GENMO_RD__VGA_RAM_EN_MASK                                                                             0x02L
+#define GENMO_RD__VGA_CKSEL_MASK                                                                              0x0CL
+#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK                                                                      0x20L
+#define GENMO_RD__VGA_HSYNC_POL_MASK                                                                          0x40L
+#define GENMO_RD__VGA_VSYNC_POL_MASK                                                                          0x80L
+//GRPH8_IDX
+#define GRPH8_IDX__GRPH_IDX__SHIFT                                                                            0x0
+#define GRPH8_IDX__GRPH_IDX_MASK                                                                              0x0FL
+//GRPH8_DATA
+#define GRPH8_DATA__GRPH_DATA__SHIFT                                                                          0x0
+#define GRPH8_DATA__GRPH_DATA_MASK                                                                            0xFFL
+//CRTC8_IDX_1
+#define CRTC8_IDX_1__VCRTC_IDX__SHIFT                                                                         0x0
+#define CRTC8_IDX_1__VCRTC_IDX_MASK                                                                           0x3FL
+//CRTC8_DATA_1
+#define CRTC8_DATA_1__VCRTC_DATA__SHIFT                                                                       0x0
+#define CRTC8_DATA_1__VCRTC_DATA_MASK                                                                         0xFFL
+//GENFC_WT_1
+#define GENFC_WT_1__VSYNC_SEL_W__SHIFT                                                                        0x3
+#define GENFC_WT_1__VSYNC_SEL_W_MASK                                                                          0x08L
+//GENS1_1
+#define GENS1_1__NO_DISPLAY__SHIFT                                                                            0x0
+#define GENS1_1__VGA_VSTATUS__SHIFT                                                                           0x3
+#define GENS1_1__PIXEL_READ_BACK__SHIFT                                                                       0x4
+#define GENS1_1__NO_DISPLAY_MASK                                                                              0x01L
+#define GENS1_1__VGA_VSTATUS_MASK                                                                             0x08L
+#define GENS1_1__PIXEL_READ_BACK_MASK                                                                         0x30L
+//D3VGA_CONTROL
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT                                                                    0x18
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D3VGA_CONTROL__D3VGA_ROTATE_MASK                                                                      0x03000000L
+//D4VGA_CONTROL
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT                                                                    0x18
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D4VGA_CONTROL__D4VGA_ROTATE_MASK                                                                      0x03000000L
+//D5VGA_CONTROL
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT                                                                    0x18
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D5VGA_CONTROL__D5VGA_ROTATE_MASK                                                                      0x03000000L
+//D6VGA_CONTROL
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT                                                                    0x18
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D6VGA_CONTROL__D6VGA_ROTATE_MASK                                                                      0x03000000L
+//VGA_SOURCE_SELECT
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT                                                            0x0
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT                                                            0x8
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK                                                              0x00000007L
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK                                                              0x00000700L
+
+
+// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
+//MCIF_CONTROL
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT                                                   0x1e
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT                                              0x1f
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK                                                     0x40000000L
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK                                                0x80000000L
+//MCIF_WRITE_COMBINE_CONTROL
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT                                         0x0
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK                                           0x000003FFL
+//MCIF_PHASE0_OUTSTANDING_COUNTER
+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER__SHIFT                               0x0
+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
+//MCIF_PHASE1_OUTSTANDING_COUNTER
+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER__SHIFT                               0x0
+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
+//MCIF_PHASE2_OUTSTANDING_COUNTER
+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER__SHIFT                               0x0
+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
+
+
+// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
+//MCIF_WB_BUFMGR_SW_CONTROL
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT                                               0x0
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT                                            0x4
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT                                           0x5
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT                                      0x6
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT                                    0x7
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT                                              0x8
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT                                           0x18
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK                                                 0x00000001L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK                                              0x00000010L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK                                             0x00000020L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK                                        0x00000040L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK                                      0x00000080L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK                                                0x00000F00L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK                                             0x01000000L
+//MCIF_WB_BUFMGR_STATUS
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT                                           0x0
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT                                            0x1
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT                                    0x2
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT                                                  0x4
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT                                             0x7
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT                                                   0x8
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT                                               0xc
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT                                                 0x1c
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK                                             0x00000001L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK                                              0x00000002L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK                                      0x00000004L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK                                                    0x00000070L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK                                               0x00000080L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK                                                     0x00000F00L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK                                                 0x01FFF000L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK                                                   0x70000000L
+//MCIF_WB_BUF_PITCH
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT                                                      0x8
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT                                                    0x18
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK                                                        0x0000FF00L
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK                                                      0xFF000000L
+//MCIF_WB_BUF_1_STATUS
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_1_STATUS2
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_BUF_2_STATUS
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_2_STATUS2
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_BUF_3_STATUS
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_3_STATUS2
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_BUF_4_STATUS
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_4_STATUS2
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_ARBITRATION_CONTROL
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT                                  0x0
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT                                            0x14
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK                                    0x00000003L
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK                                              0xFFF00000L
+//MCIF_WB_SCLK_CHANGE
+#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT                                                    0x0
+#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK                                                      0x00000001L
+//MCIF_WB_TEST_DEBUG_INDEX
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT                                             0x0
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT                                          0x8
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK                                               0x000000FFL
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK                                            0x00000100L
+//MCIF_WB_TEST_DEBUG_DATA
+#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT                                               0x0
+#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK                                                 0xFFFFFFFFL
+//MCIF_WB_BUF_1_ADDR_Y
+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_1_ADDR_C
+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_2_ADDR_Y
+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_2_ADDR_C
+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_3_ADDR_Y
+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_3_ADDR_C
+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_4_ADDR_Y
+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_4_ADDR_C
+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUFMGR_VCE_CONTROL
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT                                     0x0
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT                                          0x4
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT                                         0x5
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT                                    0x6
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT                                            0x8
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT                                          0x10
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK                                       0x00000001L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK                                            0x00000010L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK                                           0x00000020L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK                                      0x00000040L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK                                              0x00000F00L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK                                            0x1FFF0000L
+//MCIF_WB_NB_PSTATE_CONTROL
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT                                           0x1
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK                                             0x00000002L
+//MCIF_WB_CLOCK_GATER_CONTROL
+#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT                                  0x0
+#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK                                    0x00000001L
+//MCIF_WB_SELF_REFRESH_CONTROL
+#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT                                            0x1
+#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK                                              0x00000002L
+//MULTI_LEVEL_QOS_CTRL
+#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT                                                0x0
+#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK                                                  0x003FFFFFL
+//MCIF_WB_SECURITY_LEVEL
+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL__SHIFT                                                 0x0
+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SPACE__SHIFT                                                          0x4
+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL_MASK                                                   0x00000007L
+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SPACE_MASK                                                            0x00000070L
+//MCIF_WB_BUF_LUMA_SIZE
+#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT                                                   0x0
+#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK                                                     0x000FFFFFL
+//MCIF_WB_BUF_CHROMA_SIZE
+#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT                                               0x0
+#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK                                                 0x000FFFFFL
+//MCIF_WB_BUF_1_ADDR_Y_HIGH
+#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_1_ADDR_C_HIGH
+#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_2_ADDR_Y_HIGH
+#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_2_ADDR_C_HIGH
+#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_3_ADDR_Y_HIGH
+#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_3_ADDR_C_HIGH
+#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_4_ADDR_Y_HIGH
+#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_4_ADDR_C_HIGH
+#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_1_RESOLUTION
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_BUF_2_RESOLUTION
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_BUF_3_RESOLUTION
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_BUF_4_RESOLUTION
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_PSTATE_CHANGE_DURATION_VBI
+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_UCLK_PSTATE_CHANGE_DURATION_VBI__SHIFT                    0x0
+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_FCLK_PSTATE_CHANGE_DURATION_VBI__SHIFT                    0x10
+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_UCLK_PSTATE_CHANGE_DURATION_VBI_MASK                      0x0000FFFFL
+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_FCLK_PSTATE_CHANGE_DURATION_VBI_MASK                      0xFFFF0000L
+//MCIF_WB_VMID_CONTROL
+#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID__SHIFT                                                           0x0
+#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID_MASK                                                             0x0000000FL
+//MCIF_WB_MIN_TTO
+#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO__SHIFT                                                               0x0
+#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO_MASK                                                                 0x0007FFFFL
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
+//MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT                        0x0
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT                           0x18
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_TYPE__SHIFT                           0x1f
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK                          0x001FFFFFL
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK                             0x07000000L
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_TYPE_MASK                             0x80000000L
+//MCIF_WB_WATERMARK
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT                                                       0x0
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK__SHIFT                                                  0x18
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK                                                         0x001FFFFFL
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK_MASK                                                    0x07000000L
+//MMHUBBUB_WARMUP_CONFIG
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS__SHIFT                                                    0x10
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID__SHIFT                                                   0x14
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS_MASK                                                      0x000F0000L
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID_MASK                                                     0x00F00000L
+//MMHUBBUB_WARMUP_CONTROL_STATUS
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN__SHIFT                                             0x0
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN__SHIFT                                      0x4
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS__SHIFT                                  0x5
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK__SHIFT                                     0x6
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR__SHIFT                                       0x8
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN_MASK                                               0x00000001L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN_MASK                                        0x00000010L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS_MASK                                    0x00000020L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK_MASK                                       0x00000040L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR_MASK                                         0x03FFFF00L
+//MMHUBBUB_WARMUP_BASE_ADDR_LOW
+#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW__SHIFT                                   0x0
+#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW_MASK                                     0xFFFFFFFFL
+//MMHUBBUB_WARMUP_BASE_ADDR_HIGH
+#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH__SHIFT                                 0x0
+#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH_MASK                                   0x000007FFL
+//MMHUBBUB_WARMUP_ADDR_REGION
+#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION__SHIFT                                       0x0
+#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION_MASK                                         0x07FFFFFFL
+//MMHUBBUB_MIN_TTO
+#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO__SHIFT                                                             0x0
+#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO_MASK                                                               0x0007FFFFL
+//MMHUBBUB_CTRL
+#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE__SHIFT                                                            0x0
+#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE_MASK                                                              0x00000003L
+//WBIF_SMU_WM_CONTROL
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL__SHIFT                                                        0x14
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ__SHIFT                                                        0x16
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL_MASK                                                          0x00300000L
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ_MASK                                                          0x00400000L
+//WBIF0_MISC_CTRL
+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT                                             0x0
+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT                                                     0x10
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT                                                   0x18
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT                                                0x19
+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK                                               0x000003FFL
+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK                                                       0x00010000L
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK                                                     0x01000000L
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK                                                  0x02000000L
+//WBIF0_PHASE0_OUTSTANDING_COUNTER
+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT                          0x0
+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL
+//WBIF0_PHASE1_OUTSTANDING_COUNTER
+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT                          0x0
+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL
+//VGA_SRC_SPLIT_CNTL
+#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL__SHIFT                                                              0x0
+#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL_MASK                                                                0x00000003L
+//MMHUBBUB_MEM_PWR_STATUS
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT                                         0x0
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT                                         0x2
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT                                       0x4
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT                                       0x6
+#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT                                                     0x1f
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK                                           0x00000003L
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK                                           0x0000000CL
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK                                         0x00000030L
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK                                         0x000000C0L
+#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK                                                       0x80000000L
+//MMHUBBUB_MEM_PWR_CNTL
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT                                                       0x0
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT                                                         0x1
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT                                                 0x2
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT                                                   0x4
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT                                              0x5
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT                                               0x7
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT                                             0x8
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK                                                         0x00000001L
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK                                                           0x00000002L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK                                                   0x0000000CL
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK                                                     0x00000010L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK                                                0x00000060L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK                                                 0x00000080L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK                                               0x00000100L
+//MMHUBBUB_CLOCK_CNTL
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT                                               0x5
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS__SHIFT                                                  0x6
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS__SHIFT                                                   0x7
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT                                                    0x8
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT                                                  0x9
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT                                                   0xa
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_FGCG_REP_DIS__SHIFT                                                     0x11
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK                                                 0x00000020L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS_MASK                                                    0x00000040L
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS_MASK                                                     0x00000080L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK                                                      0x00000100L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK                                                    0x00000200L
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK                                                     0x00000400L
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_FGCG_REP_DIS_MASK                                                       0x00020000L
+//MMHUBBUB_SOFT_RESET
+#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET__SHIFT                                                            0x0
+#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET__SHIFT                                                          0x1
+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT                                                          0x2
+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET__SHIFT                                                          0x8
+#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET_MASK                                                              0x00000001L
+#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET_MASK                                                            0x00000002L
+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK                                                            0x00000004L
+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET_MASK                                                            0x00000100L
+//DMU_IF_ERR_STATUS
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT                                                      0x0
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT                                                  0x4
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK                                                        0x00000001L
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK                                                    0x00000010L
+//MMHUBBUB_CLIENT_UNIT_ID
+#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID__SHIFT                                                           0x0
+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID__SHIFT                                                         0x8
+#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID_MASK                                                             0x0000003FL
+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID_MASK                                                           0x00003F00L
+//MMHUBBUB_WARMUP_VMID_CONTROL
+#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID__SHIFT                                           0x0
+#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID_MASK                                             0x0000000FL
+
+
+// addressBlock: dce_dc_hda_azf0controller_dispdec
+//AZALIA_CONTROLLER_CLOCK_GATING
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT                                            0x0
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT                                                 0x4
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK                                              0x00000001L
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK                                                   0x00000010L
+//AZALIA_AUDIO_DTO
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT                                                       0x0
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT                                                      0x10
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK                                                         0x0000FFFFL
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK                                                        0xFFFF0000L
+//AZALIA_AUDIO_DTO_CONTROL
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT                                               0x8
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK                                                 0x00000300L
+//AZALIA_SOCCLK_CONTROL
+#define AZALIA_SOCCLK_CONTROL__DRM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT                                           0x0
+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT                                  0x1
+#define AZALIA_SOCCLK_CONTROL__DRM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK                                             0x00000001L
+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK                                    0x00000002L
+//AZALIA_UNDERFLOW_FILLER_SAMPLE
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT                                 0x0
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK                                   0xFFFFFFFFL
+//AZALIA_DATA_DMA_CONTROL
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT                                                    0x0
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT                                              0x2
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT                                                  0x4
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT                                            0x6
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT                                          0x10
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT                                              0x11
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK                                                      0x00000003L
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK                                                0x0000000CL
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK                                                    0x00000030L
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK                                              0x000000C0L
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK                                            0x00010000L
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK                                                0x00020000L
+//AZALIA_BDL_DMA_CONTROL
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT                                                      0x0
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT                                                0x2
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT                                                    0x4
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT                                              0x6
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK                                                        0x00000003L
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK                                                  0x0000000CL
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK                                                      0x00000030L
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK                                                0x000000C0L
+//AZALIA_RIRB_AND_DP_CONTROL
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT                                                     0x0
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT                                                   0x4
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT                                             0x5
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK                                                       0x00000001L
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK                                                     0x00000010L
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK                                               0x000001E0L
+//AZALIA_CORB_DMA_CONTROL
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT                                                    0x0
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT                                                  0x4
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK                                                      0x00000001L
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK                                                    0x00000010L
+//AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT            0x0
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK              0xFFFFFFFFL
+//AZALIA_CYCLIC_BUFFER_SYNC
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT                                           0x0
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK                                             0x00000001L
+//AZALIA_GLOBAL_CAPABILITIES
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT                               0x1
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK                                 0x00000006L
+//AZALIA_OUTPUT_PAYLOAD_CAPABILITY
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT                                    0x0
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT                                                   0x10
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK                                      0x0000FFFFL
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK                                                     0xFFFF0000L
+//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT                                     0x0
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT                                    0x8
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT                               0x10
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK                                       0x000000FFL
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK                                      0x00000100L
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK                                 0x00FF0000L
+//AZALIA_INPUT_PAYLOAD_CAPABILITY
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT                                      0x0
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT                                                     0x10
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK                                        0x0000FFFFL
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK                                                       0xFFFF0000L
+//AZALIA_INPUT_CRC0_CONTROL0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L
+//AZALIA_INPUT_CRC0_CONTROL1
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CONTROL2
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL
+//AZALIA_INPUT_CRC0_CONTROL3
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L
+//AZALIA_INPUT_CRC0_RESULT
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CONTROL0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L
+//AZALIA_INPUT_CRC1_CONTROL1
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CONTROL2
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL
+//AZALIA_INPUT_CRC1_CONTROL3
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L
+//AZALIA_INPUT_CRC1_RESULT
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL
+//AZALIA_CRC0_CONTROL0
+#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT                                                                   0x0
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc
+#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK                                                                     0x00000001L
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L
+//AZALIA_CRC0_CONTROL1
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL
+//AZALIA_CRC0_CONTROL2
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL
+//AZALIA_CRC0_CONTROL3
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L
+//AZALIA_CRC0_RESULT
+#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT                                                                 0x0
+#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL
+//AZALIA_CRC1_CONTROL0
+#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT                                                                   0x0
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc
+#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK                                                                     0x00000001L
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L
+//AZALIA_CRC1_CONTROL1
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL
+//AZALIA_CRC1_CONTROL2
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL
+//AZALIA_CRC1_CONTROL3
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L
+//AZALIA_CRC1_RESULT
+#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT                                                                 0x0
+#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL
+//AZALIA_MEM_PWR_CTRL
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT                                                          0x0
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT                                                            0x2
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT                                            0x3
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT                                              0x5
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT                                            0x6
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT                                              0x8
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT                                            0x9
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT                                              0xb
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT                                            0xc
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT                                              0xe
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT                                            0xf
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT                                              0x11
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT                                            0x12
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT                                              0x14
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT                                                       0x1c
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK                                                            0x00000003L
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK                                                              0x00000004L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK                                              0x00000018L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK                                                0x00000020L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK                                              0x000000C0L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK                                                0x00000100L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK                                              0x00000600L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK                                                0x00000800L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK                                              0x00003000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK                                                0x00004000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK                                              0x00018000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK                                                0x00020000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK                                              0x000C0000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK                                                0x00100000L
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK                                                         0x30000000L
+//AZALIA_MEM_PWR_STATUS
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT                                                        0x0
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT                                          0x2
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT                                          0x4
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT                                          0x6
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT                                          0x8
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT                                          0xa
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT                                          0xc
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK                                                          0x00000003L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK                                            0x0000000CL
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK                                            0x00000030L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK                                            0x000000C0L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK                                            0x00000300L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK                                            0x00000C00L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK                                            0x00003000L
+
+
+// addressBlock: dce_dc_hda_azf0root_dispdec
+//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL
+//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL
+//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT                                       0x0
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT                                0x4
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK                                         0x00000007L
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK                                  0x00000070L
+//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT                        0x0
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK                          0x0000003FL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL
+//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT                                           0x0
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                           0x4
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK                                             0x00000007L
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                             0x00000010L
+//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT                               0x0
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT               0x4
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK                                 0x00000007L
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                 0x00000010L
+//AZALIA_F0_GTC_GROUP_OFFSET0
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET1
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET2
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET3
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET4
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET5
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET6
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK                                                   0xFFFFFFFFL
+//REG_DC_AUDIO_PORT_CONNECTIVITY
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT                                          0x0
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                          0x4
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK                                            0x00000007L
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                            0x00000010L
+//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT                              0x0
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT              0x4
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK                                0x00000007L
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                0x00000010L
+
+
+// addressBlock: dce_dc_hda_az_misc_dispdec
+//AZ_CLOCK_CNTL
+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT                                                       0x0
+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT                                                              0x8
+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT                                                         0x10
+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT                                                              0x18
+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK                                                         0x00000001L
+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK                                                                0x00000100L
+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK                                                           0x00010000L
+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK                                                                0x1F000000L
+
+
+// addressBlock: dce_dc_hda_azf0stream0_dispdec
+//AZF0STREAM0_AZALIA_STREAM_INDEX
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM0_AZALIA_STREAM_DATA
+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream1_dispdec
+//AZF0STREAM1_AZALIA_STREAM_INDEX
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM1_AZALIA_STREAM_DATA
+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream2_dispdec
+//AZF0STREAM2_AZALIA_STREAM_INDEX
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM2_AZALIA_STREAM_DATA
+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream3_dispdec
+//AZF0STREAM3_AZALIA_STREAM_INDEX
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM3_AZALIA_STREAM_DATA
+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream4_dispdec
+//AZF0STREAM4_AZALIA_STREAM_INDEX
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM4_AZALIA_STREAM_DATA
+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream5_dispdec
+//AZF0STREAM5_AZALIA_STREAM_INDEX
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM5_AZALIA_STREAM_DATA
+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream6_dispdec
+//AZF0STREAM6_AZALIA_STREAM_INDEX
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM6_AZALIA_STREAM_DATA
+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream7_dispdec
+//AZF0STREAM7_AZALIA_STREAM_INDEX
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM7_AZALIA_STREAM_DATA
+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream8_dispdec
+//AZF0STREAM8_AZALIA_STREAM_INDEX
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM8_AZALIA_STREAM_DATA
+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream9_dispdec
+//AZF0STREAM9_AZALIA_STREAM_INDEX
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM9_AZALIA_STREAM_DATA
+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream10_dispdec
+//AZF0STREAM10_AZALIA_STREAM_INDEX
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM10_AZALIA_STREAM_DATA
+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream11_dispdec
+//AZF0STREAM11_AZALIA_STREAM_INDEX
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM11_AZALIA_STREAM_DATA
+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream12_dispdec
+//AZF0STREAM12_AZALIA_STREAM_INDEX
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM12_AZALIA_STREAM_DATA
+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream13_dispdec
+//AZF0STREAM13_AZALIA_STREAM_INDEX
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM13_AZALIA_STREAM_DATA
+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream14_dispdec
+//AZF0STREAM14_AZALIA_STREAM_INDEX
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM14_AZALIA_STREAM_DATA
+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream15_dispdec
+//AZF0STREAM15_AZALIA_STREAM_INDEX
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM15_AZALIA_STREAM_DATA
+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_dispdec
+//DCHUBBUB_ARB_DF_REQ_OUTSTAND
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT                                    0x0
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT                                    0xa
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK                                      0x000003FFL
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK                                      0x000FFC00L
+//DCHUBBUB_ARB_SAT_LEVEL
+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT                                                 0x0
+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK                                                   0xFFFFFFFFL
+//DCHUBBUB_ARB_QOS_FORCE
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT                                           0x0
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT                                          0x8
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_DURING_PSTATE_CHANGE_REQUEST__SHIFT         0x9
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK                                             0x0000000FL
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK                                            0x00000100L
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_DURING_PSTATE_CHANGE_REQUEST_MASK           0x00000200L
+//DCHUBBUB_ARB_DRAM_STATE_CNTL
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT                      0x0
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT                     0x1
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_CSTATE_DURING_PSTATE_CHANGE_REQUEST__SHIFT  0x2
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT                     0x4
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT                    0x5
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__ENABLE_QOS_FORCE_PSTATE__SHIFT                                          0x7
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE__SHIFT                                 0xc
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK                        0x00000001L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK                       0x00000002L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_CSTATE_DURING_PSTATE_CHANGE_REQUEST_MASK  0x00000004L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK                       0x00000010L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK                      0x00000020L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__ENABLE_QOS_FORCE_PSTATE_MASK                                            0x00000080L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE_MASK                                   0x00001000L
+//DCHUBBUB_ARB_USR_RETRAINING_CNTL
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__USR_RETRAINING_REQUEST__SHIFT                                       0x0
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__ALLOW_USR_RETRAINING__SHIFT                                         0x1
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE__SHIFT                0x8
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE__SHIFT               0x9
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST__SHIFT  0xa
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE__SHIFT  0xb
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__USR_RETRAINING_REQUEST_MASK                                         0x00000001L
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__ALLOW_USR_RETRAINING_MASK                                           0x00000002L
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE_MASK                  0x00000100L
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE_MASK                 0x00000200L
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST_MASK  0x00000400L
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE_MASK  0x00000800L
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK                     0x00003FFFL
+//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__SHIFT               0x0
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_MASK                 0x00003FFFL
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK                 0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK                   0x0000FFFFL
+//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__SHIFT       0x0
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__SHIFT       0x0
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_A
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK                     0x00003FFFL
+//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__SHIFT               0x0
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_MASK                 0x00003FFFL
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK                 0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK                   0x0000FFFFL
+//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__SHIFT       0x0
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__SHIFT       0x0
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_B
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK                     0x00003FFFL
+//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__SHIFT               0x0
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_MASK                 0x00003FFFL
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK                 0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK                   0x0000FFFFL
+//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__SHIFT       0x0
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__SHIFT       0x0
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_C
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK                     0x00003FFFL
+//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__SHIFT               0x0
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_MASK                 0x00003FFFL
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK                 0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK                   0x0000FFFFL
+//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__SHIFT       0x0
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__SHIFT       0x0
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_D
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT                       0x0
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT       0x4
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT        0x5
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT                      0x8
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__PSTATE_CHANGE_TYPE__SHIFT                                         0x18
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK                         0x00000003L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK         0x00000010L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK          0x00000020L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK                        0x00000100L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__PSTATE_CHANGE_TYPE_MASK                                           0x01000000L
+//DCHUBBUB_ARB_MALL_CNTL
+#define DCHUBBUB_ARB_MALL_CNTL__GLOBAL_USE_MALL_FOR_SS__SHIFT                                                 0x0
+#define DCHUBBUB_ARB_MALL_CNTL__MALL_IN_USE__SHIFT                                                            0x4
+#define DCHUBBUB_ARB_MALL_CNTL__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5
+#define DCHUBBUB_ARB_MALL_CNTL__GLOBAL_USE_MALL_FOR_SS_MASK                                                   0x00000001L
+#define DCHUBBUB_ARB_MALL_CNTL__MALL_IN_USE_MASK                                                              0x00000010L
+#define DCHUBBUB_ARB_MALL_CNTL__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L
+//DCHUBBUB_ARB_TIMEOUT_ENABLE
+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT                                       0x0
+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK                                         0x00000001L
+//DCHUBBUB_GLOBAL_TIMER_CNTL
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT                                       0x0
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT                                       0xc
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT                                         0x10
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK                                         0x0000000FL
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK                                         0x00001000L
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK                                           0xFFFF0000L
+//SURFACE_CHECK0_ADDRESS_LSB
+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK0_ADDRESS_MSB
+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK                                               0x80000000L
+//SURFACE_CHECK1_ADDRESS_LSB
+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK1_ADDRESS_MSB
+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK                                               0x80000000L
+//SURFACE_CHECK2_ADDRESS_LSB
+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK2_ADDRESS_MSB
+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK                                               0x80000000L
+//SURFACE_CHECK3_ADDRESS_LSB
+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK3_ADDRESS_MSB
+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK                                               0x80000000L
+//VTG0_CONTROL
+#define VTG0_CONTROL__VTG0_FP2__SHIFT                                                                         0x0
+#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG0_CONTROL__VTG0_ENABLE__SHIFT                                                                      0x1f
+#define VTG0_CONTROL__VTG0_FP2_MASK                                                                           0x00007FFFL
+#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG0_CONTROL__VTG0_ENABLE_MASK                                                                        0x80000000L
+//VTG1_CONTROL
+#define VTG1_CONTROL__VTG1_FP2__SHIFT                                                                         0x0
+#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG1_CONTROL__VTG1_ENABLE__SHIFT                                                                      0x1f
+#define VTG1_CONTROL__VTG1_FP2_MASK                                                                           0x00007FFFL
+#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG1_CONTROL__VTG1_ENABLE_MASK                                                                        0x80000000L
+//VTG2_CONTROL
+#define VTG2_CONTROL__VTG2_FP2__SHIFT                                                                         0x0
+#define VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG2_CONTROL__VTG2_ENABLE__SHIFT                                                                      0x1f
+#define VTG2_CONTROL__VTG2_FP2_MASK                                                                           0x00007FFFL
+#define VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG2_CONTROL__VTG2_ENABLE_MASK                                                                        0x80000000L
+//VTG3_CONTROL
+#define VTG3_CONTROL__VTG3_FP2__SHIFT                                                                         0x0
+#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG3_CONTROL__VTG3_ENABLE__SHIFT                                                                      0x1f
+#define VTG3_CONTROL__VTG3_FP2_MASK                                                                           0x00007FFFL
+#define VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG3_CONTROL__VTG3_ENABLE_MASK                                                                        0x80000000L
+//DCHUBBUB_SOFT_RESET
+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT                                                0x0
+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT                                                   0x1
+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT                                                        0x4
+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK                                                  0x00000001L
+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK                                                     0x00000002L
+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK                                                          0x00000010L
+//DCHUBBUB_CLOCK_CNTL
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0
+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                               0x5
+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                                0x6
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_FGCG_REP_DIS__SHIFT                                                     0x7
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL
+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK                                                 0x00000020L
+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK                                                  0x00000040L
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_FGCG_REP_DIS_MASK                                                       0x00000080L
+//DCFCLK_CNTL
+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT                                                              0x0
+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT                                                             0x4
+#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT                                                                   0x1f
+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK                                                                0x0000000FL
+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK                                                               0x00000FF0L
+#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK                                                                     0x80000000L
+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT                                 0x0
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN__SHIFT            0x1
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL__SHIFT                         0x2
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT                                    0x3
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT                                0x7
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT                                  0xa
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT                                          0xb
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK                                   0x00000001L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN_MASK              0x00000002L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL_MASK                           0x00000004L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK                                      0x00000078L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK                                  0x00000380L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK                                    0x00000400L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK                                            0x007FF800L
+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT                          0x0
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT                     0x1
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT                         0x4
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT                                     0xc
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT                                     0x13
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT                               0x1f
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK                            0x00000001L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK                       0x0000000EL
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK                           0x00000FF0L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK                                       0x00007000L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK                                       0x7FF80000L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK                                 0x80000000L
+//DCHUBBUB_VLINE_SNAPSHOT
+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT                                               0x0
+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK                                                 0x00000001L
+//DCHUBBUB_CTRL_STATUS
+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN__SHIFT                                                  0x0
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS__SHIFT                                                      0x2
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR__SHIFT                                                       0x3
+#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE__SHIFT                                               0x1f
+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN_MASK                                                    0x00000001L
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS_MASK                                                        0x00000004L
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR_MASK                                                         0x00000008L
+#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE_MASK                                                 0x80000000L
+//DCHUBBUB_TIMEOUT_DETECTION_CTRL1
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT                                0x0
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT                         0x6
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK                                  0x0000003FL
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK                           0xFFFFFFC0L
+//DCHUBBUB_TIMEOUT_DETECTION_CTRL2
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT                      0x0
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT                                0x1b
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT                                 0x1c
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK                        0x07FFFFFFL
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK                                  0x08000000L
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK                                   0x10000000L
+//DCHUBBUB_TIMEOUT_INTERRUPT_STATUS
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT                                 0x0
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT                                 0x1
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT                                  0x2
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT                                   0x3
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK                                   0x00000001L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK                                   0x00000002L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK                                    0x00000004L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK                                     0x000000F8L
+//FMON_CTRL
+#define FMON_CTRL__FMON_START__SHIFT                                                                          0x0
+#define FMON_CTRL__FMON_MODE__SHIFT                                                                           0x1
+#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT                                                                  0x4
+#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT                                                                  0x5
+#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT                                                               0x6
+#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT                                                                  0x7
+#define FMON_CTRL__FMON_STATE__SHIFT                                                                          0x9
+#define FMON_CTRL__FMON_URG_FILTER__SHIFT                                                                     0xc
+#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT                                                                  0xd
+#define FMON_CTRL__FMON_FILTER_UID_1__SHIFT                                                                   0x11
+#define FMON_CTRL__FMON_FILTER_UID_2__SHIFT                                                                   0x16
+#define FMON_CTRL__FMON_SOF_SEL__SHIFT                                                                        0x1b
+#define FMON_CTRL__FMON_START_MASK                                                                            0x00000001L
+#define FMON_CTRL__FMON_MODE_MASK                                                                             0x00000006L
+#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK                                                                    0x00000010L
+#define FMON_CTRL__FMON_STATUS_IGNORE_MASK                                                                    0x00000020L
+#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK                                                                 0x00000040L
+#define FMON_CTRL__FMON_FILTER_UID_EN_MASK                                                                    0x00000180L
+#define FMON_CTRL__FMON_STATE_MASK                                                                            0x00000600L
+#define FMON_CTRL__FMON_URG_FILTER_MASK                                                                       0x00001000L
+#define FMON_CTRL__FMON_URG_THRESHOLD_MASK                                                                    0x0001E000L
+#define FMON_CTRL__FMON_FILTER_UID_1_MASK                                                                     0x003E0000L
+#define FMON_CTRL__FMON_FILTER_UID_2_MASK                                                                     0x07C00000L
+#define FMON_CTRL__FMON_SOF_SEL_MASK                                                                          0x38000000L
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec
+//DCHUBBUB_SDPIF_CFG0
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT                                                  0x0
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT                                                         0x1
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT                                                0x3
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT                                                     0x6
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT                                                    0xa
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT                                               0xb
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT                                              0xc
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT                                                 0xd
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT                                                       0xe
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT                                                        0xf
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT                                             0x19
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK                                                    0x00000001L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK                                                           0x00000006L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK                                                  0x00000038L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK                                                       0x000003C0L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK                                                      0x00000400L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK                                                 0x00000800L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK                                                0x00001000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK                                                   0x00002000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK                                                         0x00004000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK                                                          0x00008000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK                                               0x7E000000L
+//DCHUBBUB_SDPIF_CFG1
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT                                                 0x0
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT                                                    0x1
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT                                              0x2
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT                                                         0x8
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_MAX_NUM_OUTSTANDING__SHIFT                                                 0x9
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK                                                   0x00000001L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK                                                      0x00000002L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK                                                0x00000004L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK                                                           0x00000100L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_MAX_NUM_OUTSTANDING_MASK                                                   0x00000200L
+//DCHUBBUB_SDPIF_CFG2
+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT__SHIFT                                                         0x0
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL__SHIFT                                                      0x8
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK__SHIFT                                                     0x10
+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT_MASK                                                           0x00000001L
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL_MASK                                                        0x00000700L
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK_MASK                                                       0x01FF0000L
+//VM_REQUEST_PHYSICAL
+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT                                                      0x0
+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT                                                      0x3
+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK                                                        0x00000001L
+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK                                                        0x00000008L
+//DCHUBBUB_FORCE_IO_STATUS_0
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT                                              0x0
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT                                       0x1
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT                                        0x2
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT                                      0x3
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT                                 0x7
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT                                      0xa
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK                                                0x00000001L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK                                         0x00000002L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK                                          0x00000004L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK                                        0x00000078L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK                                   0x00000380L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK                                        0xFFFFFC00L
+//DCHUBBUB_FORCE_IO_STATUS_1
+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT                                      0x0
+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK                                        0x001FFFFFL
+//DCN_VM_FB_LOCATION_BASE
+#define DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                               0x0
+#define DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                                 0x00FFFFFFL
+//DCN_VM_FB_LOCATION_TOP
+#define DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                                 0x0
+#define DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                                   0x00FFFFFFL
+//DCN_VM_FB_OFFSET
+#define DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                                    0x0
+#define DCN_VM_FB_OFFSET__FB_OFFSET_MASK                                                                      0x00FFFFFFL
+//DCN_VM_AGP_BOT
+#define DCN_VM_AGP_BOT__AGP_BOT__SHIFT                                                                        0x0
+#define DCN_VM_AGP_BOT__AGP_BOT_MASK                                                                          0x00FFFFFFL
+//DCN_VM_AGP_TOP
+#define DCN_VM_AGP_TOP__AGP_TOP__SHIFT                                                                        0x0
+#define DCN_VM_AGP_TOP__AGP_TOP_MASK                                                                          0x00FFFFFFL
+//DCN_VM_AGP_BASE
+#define DCN_VM_AGP_BASE__AGP_BASE__SHIFT                                                                      0x0
+#define DCN_VM_AGP_BASE__AGP_BASE_MASK                                                                        0x00FFFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_START
+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT                                                  0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK                                                    0x000FFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_END
+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT                                                      0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK                                                        0x000FFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                                       0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                                         0x00000001L
+//DCHUBBUB_SDPIF_PIPE_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL__SHIFT                                               0x0
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL__SHIFT                                               0x3
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL__SHIFT                                               0x6
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL__SHIFT                                               0x9
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL_MASK                                                 0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL_MASK                                                 0x00000038L
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL_MASK                                                 0x000001C0L
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL_MASK                                                 0x00000E00L
+//DCHUBBUB_SDPIF_PIPE_NOALLOC
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE0_NOALLOC__SHIFT                                               0x0
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE1_NOALLOC__SHIFT                                               0x1
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE2_NOALLOC__SHIFT                                               0x2
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE3_NOALLOC__SHIFT                                               0x3
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE0_NOALLOC_MASK                                                 0x00000001L
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE1_NOALLOC_MASK                                                 0x00000002L
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE2_NOALLOC_MASK                                                 0x00000004L
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE3_NOALLOC_MASK                                                 0x00000008L
+//DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL__SHIFT                                 0x0
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL__SHIFT                                 0x3
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL__SHIFT                                 0x6
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL__SHIFT                                 0x9
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL_MASK                                   0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL_MASK                                   0x00000038L
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL_MASK                                   0x000001C0L
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL_MASK                                   0x00000E00L
+//DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL__SHIFT                               0x0
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL__SHIFT                               0x3
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE2_DCCMETA_SEC_LVL__SHIFT                               0x6
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE3_DCCMETA_SEC_LVL__SHIFT                               0x9
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL_MASK                                 0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL_MASK                                 0x00000038L
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE2_DCCMETA_SEC_LVL_MASK                                 0x000001C0L
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE3_DCCMETA_SEC_LVL_MASK                                 0x00000E00L
+//DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL__SHIFT                               0x0
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL__SHIFT                               0x3
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE2_CURSOR0_SEC_LVL__SHIFT                               0x6
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE3_CURSOR0_SEC_LVL__SHIFT                               0x9
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL_MASK                                 0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL_MASK                                 0x00000038L
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE2_CURSOR0_SEC_LVL_MASK                                 0x000001C0L
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE3_CURSOR0_SEC_LVL_MASK                                 0x00000E00L
+//DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL__SHIFT                                   0x0
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL__SHIFT                                   0x3
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE2_GPUVM_SEC_LVL__SHIFT                                   0x6
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE3_GPUVM_SEC_LVL__SHIFT                                   0x9
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL_MASK                                     0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL_MASK                                     0x00000038L
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE2_GPUVM_SEC_LVL_MASK                                     0x000001C0L
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE3_GPUVM_SEC_LVL_MASK                                     0x00000E00L
+//SDPIF_REQUEST_RATE_LIMIT
+#define SDPIF_REQUEST_RATE_LIMIT__SDPIF_REQUEST_RATE_LIMIT__SHIFT                                             0x0
+#define SDPIF_REQUEST_RATE_LIMIT__SDPIF_REQUEST_RATE_LIMIT_MASK                                               0x00000FFFL
+//DCHUBBUB_SDPIF_MEM_PWR_CTRL
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT                                      0x0
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT                                        0x2
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK                                        0x00000003L
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK                                          0x00000004L
+//DCHUBBUB_SDPIF_MEM_PWR_STATUS
+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT                                    0x0
+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK                                      0x00000003L
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec
+//DCHUBBUB_RET_PATH_MEM_PWR_CTRL
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT                                0x0
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT                                  0x2
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK                                  0x00000003L
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK                                    0x00000004L
+//DCHUBBUB_RET_PATH_MEM_PWR_STATUS
+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT                              0x0
+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK                                0x00000003L
+//DCHUBBUB_CRC_CTRL
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT                                                             0x0
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT                                                        0x1
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT                                              0x2
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT                                              0x3
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT                                                       0x4
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT                                                       0x6
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT                                                       0x8
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT                                                       0xc
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT                                                   0x14
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK                                                               0x00000001L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK                                                          0x00000002L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK                                                0x00000004L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK                                                0x00000008L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK                                                         0x00000030L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK                                                         0x000000C0L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK                                                         0x00000F00L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK                                                         0x00001000L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK                                                     0x00100000L
+//DCHUBBUB_CRC0_VAL_R_G
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR__SHIFT                                                      0x0
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y__SHIFT                                                       0x10
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y_MASK                                                         0xFFFF0000L
+//DCHUBBUB_CRC0_VAL_B_A
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB__SHIFT                                                      0x0
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA__SHIFT                                                     0x10
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA_MASK                                                       0xFFFF0000L
+//DCHUBBUB_CRC1_VAL_R_G
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR__SHIFT                                                      0x0
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y__SHIFT                                                       0x10
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y_MASK                                                         0xFFFF0000L
+//DCHUBBUB_CRC1_VAL_B_A
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB__SHIFT                                                      0x0
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA__SHIFT                                                     0x10
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA_MASK                                                       0xFFFF0000L
+//DCHUBBUB_DCC_STAT_CNTL
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE__SHIFT                                                 0x0
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN__SHIFT                                                   0x1
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE__SHIFT                                                 0x2
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL__SHIFT                                             0x4
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT__SHIFT                                            0x10
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE_MASK                                                   0x00000001L
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN_MASK                                                     0x00000002L
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE_MASK                                                   0x00000004L
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL_MASK                                               0x000000F0L
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT_MASK                                              0xFFFF0000L
+//DCHUBBUB_DCC_STAT0
+#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ__SHIFT                                                0x0
+#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ_MASK                                                  0xFFFFFFFFL
+//DCHUBBUB_DCC_STAT1
+#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ__SHIFT                                                   0x0
+#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ_MASK                                                     0xFFFFFFFFL
+//DCHUBBUB_DCC_STAT2
+#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ__SHIFT                                                  0x0
+#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ_MASK                                                    0xFFFFFFFFL
+//DCHUBBUB_COMPBUF_CTRL
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE__SHIFT                                                            0x0
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT__SHIFT                                                    0x8
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE__SHIFT                                     0x10
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS__SHIFT                                     0x12
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR__SHIFT                                      0x13
+#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR__SHIFT                                                            0x1f
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_MASK                                                              0x0000001FL
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT_MASK                                                      0x00001F00L
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE_MASK                                       0x00010000L
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS_MASK                                       0x00040000L
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR_MASK                                        0x00080000L
+#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR_MASK                                                              0x80000000L
+//DCHUBBUB_DET0_CTRL
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE__SHIFT                                                                  0x0
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT__SHIFT                                                          0x8
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_MASK                                                                    0x0000001FL
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT_MASK                                                            0x00001F00L
+//DCHUBBUB_DET1_CTRL
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE__SHIFT                                                                  0x0
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT__SHIFT                                                          0x8
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_MASK                                                                    0x0000001FL
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT_MASK                                                            0x00001F00L
+//DCHUBBUB_DET2_CTRL
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE__SHIFT                                                                  0x0
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT__SHIFT                                                          0x8
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_MASK                                                                    0x0000001FL
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT_MASK                                                            0x00001F00L
+//DCHUBBUB_DET3_CTRL
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE__SHIFT                                                                  0x0
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT__SHIFT                                                          0x8
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_MASK                                                                    0x0000001FL
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT_MASK                                                            0x00001F00L
+//DCHUBBUB_MEM_PWR_MODE_CTRL
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE__SHIFT                                        0x0
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE__SHIFT                                        0x2
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE__SHIFT                                          0x4
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE__SHIFT                                             0x6
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE__SHIFT                                             0x8
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE__SHIFT                                           0xa
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE__SHIFT                                                  0x10
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE__SHIFT                                              0x12
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                                0x14
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS__SHIFT                                                0x18
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS__SHIFT                                               0x19
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS__SHIFT                                               0x1a
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE_MASK                                          0x00000003L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE_MASK                                          0x0000000CL
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE_MASK                                            0x00000030L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE_MASK                                               0x000000C0L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE_MASK                                             0x00000C00L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE_MASK                                                    0x00030000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE_MASK                                                0x000C0000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE_MASK                                                  0x00300000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS_MASK                                                  0x01000000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS_MASK                                                 0x02000000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS_MASK                                                 0x04000000L
+//COMPBUF_MEM_PWR_CTRL_1
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY__SHIFT                                            0x0
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY__SHIFT                                           0x8
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY__SHIFT                                              0x10
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY__SHIFT                                             0x18
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY_MASK                                              0x000000FFL
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY_MASK                                             0x0000FF00L
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY_MASK                                                0x00FF0000L
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY_MASK                                               0xFF000000L
+//COMPBUF_MEM_PWR_CTRL_2
+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY__SHIFT                                       0x0
+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY_MASK                                         0x000000FFL
+//DCHUBBUB_MEM_PWR_STATUS
+#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE__SHIFT                                                 0x0
+#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE__SHIFT                                                0x2
+#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE__SHIFT                                             0x4
+#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE__SHIFT                                                0x6
+#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE__SHIFT                                                    0x8
+#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE__SHIFT                                                    0xa
+#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE__SHIFT                                                    0xc
+#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE__SHIFT                                                    0xe
+#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE_MASK                                                   0x00000003L
+#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE_MASK                                                  0x0000000CL
+#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE_MASK                                               0x00000030L
+#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE_MASK                                                  0x000000C0L
+#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE_MASK                                                      0x00000300L
+#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE_MASK                                                      0x00000C00L
+#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE_MASK                                                      0x00003000L
+#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE_MASK                                                      0x0000C000L
+//COMPBUF_RESERVED_SPACE
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B__SHIFT                                             0x0
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS__SHIFT                                              0x10
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B_MASK                                               0x00000FFFL
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS_MASK                                                0x0FFF0000L
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec
+//DCN_VM_CONTEXT0_CNTL
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT1_CNTL
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT2_CNTL
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT3_CNTL
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT4_CNTL
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT5_CNTL
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT6_CNTL
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT7_CNTL
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT8_CNTL
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT9_CNTL
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT10_CNTL
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT11_CNTL
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT12_CNTL
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT13_CNTL
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT14_CNTL
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT15_CNTL
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_DEFAULT_ADDR_MSB
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB__SHIFT                                               0x0
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA__SHIFT                                                    0x1c
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP__SHIFT                                                  0x1d
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB_MASK                                                 0x0000000FL
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA_MASK                                                      0x10000000L
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP_MASK                                                    0x20000000L
+//DCN_VM_DEFAULT_ADDR_LSB
+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB__SHIFT                                               0x0
+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB_MASK                                                 0xFFFFFFFFL
+//DCN_VM_FAULT_CNTL
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT                                                   0x0
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT                                                    0x1
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT                                               0x2
+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT                                                  0x8
+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT                                                    0x9
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK                                                     0x00000001L
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK                                                      0x00000002L
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK                                                 0x00000004L
+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK                                                    0x00000100L
+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK                                                      0x00000200L
+//DCN_VM_FAULT_STATUS
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT                                                       0x0
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT                                                         0x10
+#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID__SHIFT                                                 0x14
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT                                                  0x18
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT                                                         0x1a
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT                                             0x1f
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK                                                         0x0000FFFFL
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK                                                           0x000F0000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID_MASK                                                   0x00F00000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK                                                    0x03000000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK                                                           0x3C000000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK                                               0x80000000L
+//DCN_VM_FAULT_ADDR_MSB
+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT                                                   0x0
+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK                                                     0x0000000FL
+//DCN_VM_FAULT_ADDR_LSB
+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT                                                   0x0
+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK                                                     0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
+//HUBP0_DCSURF_SURFACE_CONFIG
+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP0_DCSURF_ADDR_CONFIG
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP0_DCSURF_TILING_CONFIG
+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP0_DCSURF_PRI_VIEWPORT_START
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_START
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP0_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP0_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP0_DCHUBP_CNTL
+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2
+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa
+#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L
+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L
+#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP0_HUBP_CLK_CNTL
+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP0_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP0_DCHUBP_VMPG_CONFIG
+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP0_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1
+#define HUBP0_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2
+#define HUBP0_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7
+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+#define HUBP0_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L
+#define HUBP0_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL
+#define HUBP0_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L
+//HUBP0_DCHUBP_MALL_CONFIG
+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0
+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2
+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L
+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L
+//HUBP0_DCHUBP_MALL_SUB_VP
+#define HUBP0_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT                                               0x0
+#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT                                                 0x1
+#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT                                                 0xf
+#define HUBP0_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK                                                 0x00000001L
+#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK                                                   0x00007FFEL
+#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK                                                   0x1FFF8000L
+//HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+//HUBP0_HUBP_MALL_STATUS
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3
+#define HUBP0_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4
+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5
+#define HUBP0_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6
+#define HUBP0_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7
+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8
+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9
+#define HUBP0_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa
+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb
+#define HUBP0_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc
+#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT                                                     0xd
+#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe
+#define HUBP0_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf
+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10
+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11
+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12
+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L
+#define HUBP0_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L
+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L
+#define HUBP0_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L
+#define HUBP0_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L
+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L
+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L
+#define HUBP0_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L
+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L
+#define HUBP0_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L
+#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK                                                       0x00002000L
+#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L
+#define HUBP0_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L
+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L
+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L
+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L
+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
+//HUBPREQ0_DCSURF_SURFACE_PITCH
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ0_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ0_VMID_SETTINGS_0
+#define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ0_DCSURF_SURFACE_CONTROL
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ0_DCSURF_FLIP_CONTROL
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ0_DCSURF_FLIP_CONTROL2
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ0_DCSURF_SURFACE_INUSE
+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ0_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ0_DCN_EXPANSION_MODE
+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ0_DCN_TTU_QOS_WM
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ0_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ0_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ0_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ0_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ0_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ0_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ0_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ0_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ0_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ0_DCN_DMDATA_VM_CNTL
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L
+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ0_BLANK_OFFSET_0
+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ0_BLANK_OFFSET_1
+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ0_DST_DIMENSIONS
+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ0_DST_AFTER_SCALER
+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ0_PREFETCH_SETTINGS
+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ0_PREFETCH_SETTINGS_C
+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_0
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ0_VBLANK_PARAMETERS_1
+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_2
+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_3
+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_4
+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_0
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ0_FLIP_PARAMETERS_1
+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_2
+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_0
+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_1
+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_2
+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_3
+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_4
+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_5
+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_6
+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_7
+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ0_PER_LINE_DELIVERY_PRE
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ0_PER_LINE_DELIVERY
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ0_CURSOR_SETTINGS
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ0_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ0_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ0_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ0_VBLANK_PARAMETERS_5
+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_6
+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_3
+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_4
+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_5
+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_6
+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+//HUBPREQ0_UCLK_PSTATE_FORCE
+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0
+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1
+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2
+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3
+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L
+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L
+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L
+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L
+//HUBPREQ0_HUBPREQ_STATUS_REG0
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT                                         0x0
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT                                         0x8
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK                                           0x0000001FL
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK                                           0x00001F00L
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L
+//HUBPREQ0_HUBPREQ_STATUS_REG1
+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0
+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10
+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x00003FFFL
+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0x3FFF0000L
+//HUBPREQ0_HUBPREQ_STATUS_REG2
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
+//HUBPRET0_HUBPRET_CONTROL
+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4
+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L
+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET0_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET0_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET0_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
+//HUBPRET0_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET0_HUBPRET_READ_LINE0
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET0_HUBPRET_READ_LINE1
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET0_HUBPRET_INTERRUPT
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET0_HUBPRET_READ_LINE_VALUE
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET0_HUBPRET_READ_LINE_STATUS
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
+//CURSOR0_0_CURSOR_CONTROL
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+//CURSOR0_0_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_0_CURSOR_SIZE
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_0_CURSOR_POSITION
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_0_CURSOR_HOT_SPOT
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_0_CURSOR_STEREO_CONTROL
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_0_CURSOR_DST_OFFSET
+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_0_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_0_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_0_DMDATA_ADDRESS_HIGH
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_0_DMDATA_ADDRESS_LOW
+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_0_DMDATA_CNTL
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_0_DMDATA_QOS_CNTL
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_0_DMDATA_STATUS
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_0_DMDATA_SW_CNTL
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_0_DMDATA_SW_DATA
+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
+//HUBP1_DCSURF_SURFACE_CONFIG
+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP1_DCSURF_ADDR_CONFIG
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP1_DCSURF_TILING_CONFIG
+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP1_DCSURF_PRI_VIEWPORT_START
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_START
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP1_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP1_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP1_DCHUBP_CNTL
+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2
+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa
+#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L
+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L
+#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP1_HUBP_CLK_CNTL
+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP1_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP1_DCHUBP_VMPG_CONFIG
+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP1_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1
+#define HUBP1_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2
+#define HUBP1_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7
+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+#define HUBP1_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L
+#define HUBP1_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL
+#define HUBP1_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L
+//HUBP1_DCHUBP_MALL_CONFIG
+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0
+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2
+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L
+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L
+//HUBP1_DCHUBP_MALL_SUB_VP
+#define HUBP1_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT                                               0x0
+#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT                                                 0x1
+#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT                                                 0xf
+#define HUBP1_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK                                                 0x00000001L
+#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK                                                   0x00007FFEL
+#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK                                                   0x1FFF8000L
+//HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+//HUBP1_HUBP_MALL_STATUS
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3
+#define HUBP1_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4
+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5
+#define HUBP1_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6
+#define HUBP1_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7
+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8
+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9
+#define HUBP1_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa
+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb
+#define HUBP1_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc
+#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT                                                     0xd
+#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe
+#define HUBP1_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf
+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10
+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11
+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12
+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L
+#define HUBP1_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L
+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L
+#define HUBP1_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L
+#define HUBP1_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L
+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L
+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L
+#define HUBP1_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L
+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L
+#define HUBP1_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L
+#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK                                                       0x00002000L
+#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L
+#define HUBP1_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L
+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L
+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L
+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L
+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
+//HUBPREQ1_DCSURF_SURFACE_PITCH
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ1_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ1_VMID_SETTINGS_0
+#define HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ1_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ1_DCSURF_SURFACE_CONTROL
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ1_DCSURF_FLIP_CONTROL
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ1_DCSURF_FLIP_CONTROL2
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ1_DCSURF_SURFACE_INUSE
+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ1_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ1_DCN_EXPANSION_MODE
+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ1_DCN_TTU_QOS_WM
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ1_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ1_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ1_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ1_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ1_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ1_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ1_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ1_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ1_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ1_DCN_DMDATA_VM_CNTL
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L
+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ1_BLANK_OFFSET_0
+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ1_BLANK_OFFSET_1
+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ1_DST_DIMENSIONS
+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ1_DST_AFTER_SCALER
+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ1_PREFETCH_SETTINGS
+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ1_PREFETCH_SETTINGS_C
+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_0
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ1_VBLANK_PARAMETERS_1
+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_2
+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_3
+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_4
+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_0
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ1_FLIP_PARAMETERS_1
+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_2
+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_0
+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_1
+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_2
+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_3
+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_4
+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_5
+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_6
+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_7
+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ1_PER_LINE_DELIVERY_PRE
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ1_PER_LINE_DELIVERY
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ1_CURSOR_SETTINGS
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ1_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ1_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ1_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ1_VBLANK_PARAMETERS_5
+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_6
+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_3
+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_4
+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_5
+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_6
+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+//HUBPREQ1_UCLK_PSTATE_FORCE
+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0
+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1
+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2
+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3
+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L
+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L
+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L
+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L
+//HUBPREQ1_HUBPREQ_STATUS_REG0
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT                                         0x0
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT                                         0x8
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK                                           0x0000001FL
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK                                           0x00001F00L
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L
+//HUBPREQ1_HUBPREQ_STATUS_REG1
+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0
+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10
+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x00003FFFL
+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0x3FFF0000L
+//HUBPREQ1_HUBPREQ_STATUS_REG2
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
+//HUBPRET1_HUBPRET_CONTROL
+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4
+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L
+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET1_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET1_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET1_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
+//HUBPRET1_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET1_HUBPRET_READ_LINE0
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET1_HUBPRET_READ_LINE1
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET1_HUBPRET_INTERRUPT
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET1_HUBPRET_READ_LINE_VALUE
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET1_HUBPRET_READ_LINE_STATUS
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
+//CURSOR0_1_CURSOR_CONTROL
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+//CURSOR0_1_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_1_CURSOR_SIZE
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_1_CURSOR_POSITION
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_1_CURSOR_HOT_SPOT
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_1_CURSOR_STEREO_CONTROL
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_1_CURSOR_DST_OFFSET
+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_1_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_1_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_1_DMDATA_ADDRESS_HIGH
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_1_DMDATA_ADDRESS_LOW
+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_1_DMDATA_CNTL
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_1_DMDATA_QOS_CNTL
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_1_DMDATA_STATUS
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_1_DMDATA_SW_CNTL
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_1_DMDATA_SW_DATA
+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
+//HUBP2_DCSURF_SURFACE_CONFIG
+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP2_DCSURF_ADDR_CONFIG
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP2_DCSURF_TILING_CONFIG
+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP2_DCSURF_PRI_VIEWPORT_START
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP2_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_START
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP2_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP2_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP2_DCHUBP_CNTL
+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2
+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa
+#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L
+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L
+#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP2_HUBP_CLK_CNTL
+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP2_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP2_DCHUBP_VMPG_CONFIG
+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP2_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1
+#define HUBP2_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2
+#define HUBP2_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7
+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+#define HUBP2_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L
+#define HUBP2_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL
+#define HUBP2_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L
+//HUBP2_DCHUBP_MALL_CONFIG
+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0
+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2
+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L
+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L
+//HUBP2_DCHUBP_MALL_SUB_VP
+#define HUBP2_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT                                               0x0
+#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT                                                 0x1
+#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT                                                 0xf
+#define HUBP2_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK                                                 0x00000001L
+#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK                                                   0x00007FFEL
+#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK                                                   0x1FFF8000L
+//HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+//HUBP2_HUBP_MALL_STATUS
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3
+#define HUBP2_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4
+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5
+#define HUBP2_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6
+#define HUBP2_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7
+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8
+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9
+#define HUBP2_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa
+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb
+#define HUBP2_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc
+#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT                                                     0xd
+#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe
+#define HUBP2_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf
+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10
+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11
+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12
+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L
+#define HUBP2_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L
+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L
+#define HUBP2_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L
+#define HUBP2_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L
+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L
+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L
+#define HUBP2_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L
+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L
+#define HUBP2_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L
+#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK                                                       0x00002000L
+#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L
+#define HUBP2_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L
+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L
+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L
+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L
+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
+//HUBPREQ2_DCSURF_SURFACE_PITCH
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ2_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ2_VMID_SETTINGS_0
+#define HUBPREQ2_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ2_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ2_DCSURF_SURFACE_CONTROL
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ2_DCSURF_FLIP_CONTROL
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ2_DCSURF_FLIP_CONTROL2
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ2_DCSURF_SURFACE_INUSE
+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ2_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ2_DCN_EXPANSION_MODE
+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ2_DCN_TTU_QOS_WM
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ2_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ2_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ2_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ2_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ2_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ2_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ2_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ2_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ2_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ2_DCN_DMDATA_VM_CNTL
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L
+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ2_BLANK_OFFSET_0
+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ2_BLANK_OFFSET_1
+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ2_DST_DIMENSIONS
+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ2_DST_AFTER_SCALER
+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ2_PREFETCH_SETTINGS
+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ2_PREFETCH_SETTINGS_C
+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_0
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ2_VBLANK_PARAMETERS_1
+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_2
+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_3
+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_4
+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_0
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ2_FLIP_PARAMETERS_1
+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_2
+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_0
+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_1
+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_2
+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_3
+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_4
+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_5
+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_6
+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_7
+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ2_PER_LINE_DELIVERY_PRE
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ2_PER_LINE_DELIVERY
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ2_CURSOR_SETTINGS
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ2_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ2_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ2_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ2_VBLANK_PARAMETERS_5
+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_6
+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_3
+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_4
+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_5
+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_6
+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+//HUBPREQ2_UCLK_PSTATE_FORCE
+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0
+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1
+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2
+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3
+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L
+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L
+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L
+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L
+//HUBPREQ2_HUBPREQ_STATUS_REG0
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT                                         0x0
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT                                         0x8
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK                                           0x0000001FL
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK                                           0x00001F00L
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L
+//HUBPREQ2_HUBPREQ_STATUS_REG1
+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0
+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10
+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x00003FFFL
+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0x3FFF0000L
+//HUBPREQ2_HUBPREQ_STATUS_REG2
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
+//HUBPRET2_HUBPRET_CONTROL
+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4
+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L
+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET2_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET2_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET2_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
+//HUBPRET2_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET2_HUBPRET_READ_LINE0
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET2_HUBPRET_READ_LINE1
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET2_HUBPRET_INTERRUPT
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET2_HUBPRET_READ_LINE_VALUE
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET2_HUBPRET_READ_LINE_STATUS
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
+//CURSOR0_2_CURSOR_CONTROL
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+//CURSOR0_2_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_2_CURSOR_SIZE
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_2_CURSOR_POSITION
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_2_CURSOR_HOT_SPOT
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_2_CURSOR_STEREO_CONTROL
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_2_CURSOR_DST_OFFSET
+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_2_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_2_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_2_DMDATA_ADDRESS_HIGH
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_2_DMDATA_ADDRESS_LOW
+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_2_DMDATA_CNTL
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_2_DMDATA_QOS_CNTL
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_2_DMDATA_STATUS
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_2_DMDATA_SW_CNTL
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_2_DMDATA_SW_DATA
+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
+//HUBP3_DCSURF_SURFACE_CONFIG
+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP3_DCSURF_ADDR_CONFIG
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP3_DCSURF_TILING_CONFIG
+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP3_DCSURF_PRI_VIEWPORT_START
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP3_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_START
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP3_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP3_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP3_DCHUBP_CNTL
+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2
+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa
+#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L
+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L
+#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP3_HUBP_CLK_CNTL
+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP3_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP3_DCHUBP_VMPG_CONFIG
+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP3_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1
+#define HUBP3_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2
+#define HUBP3_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7
+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+#define HUBP3_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L
+#define HUBP3_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL
+#define HUBP3_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L
+//HUBP3_DCHUBP_MALL_CONFIG
+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0
+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2
+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L
+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L
+//HUBP3_DCHUBP_MALL_SUB_VP
+#define HUBP3_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT                                               0x0
+#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT                                                 0x1
+#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT                                                 0xf
+#define HUBP3_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK                                                 0x00000001L
+#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK                                                   0x00007FFEL
+#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK                                                   0x1FFF8000L
+//HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+//HUBP3_HUBP_MALL_STATUS
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3
+#define HUBP3_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4
+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5
+#define HUBP3_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6
+#define HUBP3_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7
+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8
+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9
+#define HUBP3_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa
+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb
+#define HUBP3_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc
+#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT                                                     0xd
+#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe
+#define HUBP3_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf
+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10
+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11
+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12
+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L
+#define HUBP3_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L
+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L
+#define HUBP3_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L
+#define HUBP3_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L
+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L
+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L
+#define HUBP3_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L
+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L
+#define HUBP3_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L
+#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK                                                       0x00002000L
+#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L
+#define HUBP3_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L
+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L
+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L
+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L
+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
+//HUBPREQ3_DCSURF_SURFACE_PITCH
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ3_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ3_VMID_SETTINGS_0
+#define HUBPREQ3_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ3_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ3_DCSURF_SURFACE_CONTROL
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ3_DCSURF_FLIP_CONTROL
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ3_DCSURF_FLIP_CONTROL2
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ3_DCSURF_SURFACE_INUSE
+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ3_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ3_DCN_EXPANSION_MODE
+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ3_DCN_TTU_QOS_WM
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ3_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ3_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ3_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ3_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ3_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ3_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ3_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ3_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ3_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ3_DCN_DMDATA_VM_CNTL
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L
+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ3_BLANK_OFFSET_0
+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ3_BLANK_OFFSET_1
+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ3_DST_DIMENSIONS
+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ3_DST_AFTER_SCALER
+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ3_PREFETCH_SETTINGS
+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ3_PREFETCH_SETTINGS_C
+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_0
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ3_VBLANK_PARAMETERS_1
+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_2
+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_3
+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_4
+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_0
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ3_FLIP_PARAMETERS_1
+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_2
+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_0
+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_1
+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_2
+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_3
+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_4
+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_5
+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_6
+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_7
+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ3_PER_LINE_DELIVERY_PRE
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ3_PER_LINE_DELIVERY
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ3_CURSOR_SETTINGS
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ3_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ3_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ3_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ3_VBLANK_PARAMETERS_5
+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_6
+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_3
+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_4
+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_5
+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_6
+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+//HUBPREQ3_UCLK_PSTATE_FORCE
+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0
+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1
+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2
+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3
+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L
+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L
+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L
+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L
+//HUBPREQ3_HUBPREQ_STATUS_REG0
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT                                         0x0
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT                                         0x8
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK                                           0x0000001FL
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK                                           0x00001F00L
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L
+//HUBPREQ3_HUBPREQ_STATUS_REG1
+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0
+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10
+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x00003FFFL
+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0x3FFF0000L
+//HUBPREQ3_HUBPREQ_STATUS_REG2
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
+//HUBPRET3_HUBPRET_CONTROL
+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4
+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L
+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET3_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET3_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET3_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
+//HUBPRET3_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET3_HUBPRET_READ_LINE0
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET3_HUBPRET_READ_LINE1
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET3_HUBPRET_INTERRUPT
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET3_HUBPRET_READ_LINE_VALUE
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET3_HUBPRET_READ_LINE_STATUS
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
+//CURSOR0_3_CURSOR_CONTROL
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+//CURSOR0_3_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_3_CURSOR_SIZE
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_3_CURSOR_POSITION
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_3_CURSOR_HOT_SPOT
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_3_CURSOR_STEREO_CONTROL
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_3_CURSOR_DST_OFFSET
+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_3_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_3_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_3_DMDATA_ADDRESS_HIGH
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_3_DMDATA_ADDRESS_LOW
+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_3_DMDATA_CNTL
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_3_DMDATA_QOS_CNTL
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_3_DMDATA_STATUS
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_3_DMDATA_SW_CNTL
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_3_DMDATA_SW_DATA
+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG0_FORMAT_CONTROL
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG0_FCNV_FP_BIAS_R
+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_BIAS_G
+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_BIAS_B
+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_R
+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_G
+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_B
+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG0_COLOR_KEYER_CONTROL
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG0_COLOR_KEYER_ALPHA
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_RED
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_GREEN
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_BLUE
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG0_ALPHA_2BIT_LUT
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG0_PRE_DEALPHA
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG0_PRE_CSC_MODE
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG0_PRE_CSC_C11_C12
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C13_C14
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C21_C22
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C23_C24
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C31_C32
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C33_C34
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C11_C12
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C13_C14
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C21_C22
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C23_C24
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C31_C32
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C33_C34
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_CNVC_COEF_FORMAT
+#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG0_PRE_DEGAM
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG0_PRE_REALPHA
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
+//CNVC_CUR0_CURSOR0_CONTROL
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR0_CURSOR0_COLOR0
+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR0_CURSOR0_COLOR1
+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR0_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
+//DSCL0_SCL_COEF_RAM_TAP_SELECT
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00030000L
+//DSCL0_SCL_COEF_RAM_TAP_DATA
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL0_SCL_MODE
+#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL0_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL0_SCL_TAP_CONTROL
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL0_DSCL_CONTROL
+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL0_DSCL_2TAP_CONTROL
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL0_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL0_SCL_HORZ_FILTER_INIT
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL0_SCL_HORZ_FILTER_INIT_C
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL0_SCL_VERT_FILTER_INIT
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL0_SCL_VERT_FILTER_INIT_BOT
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL0_SCL_VERT_FILTER_INIT_C
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL0_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL0_SCL_BLACK_COLOR
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL0_DSCL_UPDATE
+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL0_DSCL_AUTOCAL
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL0_OTG_H_BLANK
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL0_OTG_V_BLANK
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL0_RECOUT_START
+#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL0_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL0_RECOUT_SIZE
+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL0_MPC_SIZE
+#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL0_LB_DATA_FORMAT
+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL0_LB_MEMORY_CTRL
+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL0_LB_V_COUNTER
+#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL0_DSCL_MEM_PWR_CTRL
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL0_DSCL_MEM_PWR_STATUS
+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL0_OBUF_CONTROL
+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL0_OBUF_MEM_PWR_CTRL
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
+//CM0_CM_CONTROL
+#define CM0_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM0_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM0_CM_POST_CSC_CONTROL
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM0_CM_POST_CSC_C11_C12
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C13_C14
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C21_C22
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C23_C24
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C31_C32
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C33_C34
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_B_C11_C12
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C13_C14
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C21_C22
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C23_C24
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C31_C32
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C33_C34
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_CONTROL
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM0_CM_GAMUT_REMAP_C11_C12
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C13_C14
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C21_C22
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C23_C24
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C31_C32
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C33_C34
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C11_C12
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C13_C14
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C21_C22
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C23_C24
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C31_C32
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C33_C34
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM0_CM_BIAS_CR_R
+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM0_CM_BIAS_Y_G_CB_B
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM0_CM_GAMCOR_CONTROL
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM0_CM_GAMCOR_LUT_INDEX
+#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM0_CM_GAMCOR_LUT_DATA
+#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM0_CM_GAMCOR_LUT_CONTROL
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT                                              0x5
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK                                                0x00000020L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM0_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMA_OFFSET_B
+#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMA_OFFSET_G
+#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMA_OFFSET_R
+#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMA_REGION_0_1
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_2_3
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_4_5
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_6_7
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_8_9
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_10_11
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_12_13
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_14_15
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_16_17
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_18_19
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_20_21
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_22_23
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_24_25
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_26_27
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_28_29
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_30_31
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_32_33
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMB_OFFSET_B
+#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMB_OFFSET_G
+#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMB_OFFSET_R
+#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMB_REGION_0_1
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_2_3
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_4_5
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_6_7
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_8_9
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_10_11
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_12_13
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_14_15
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_16_17
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_18_19
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_20_21
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_22_23
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_24_25
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_26_27
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_28_29
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_30_31
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_32_33
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_HDR_MULT_COEF
+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM0_CM_MEM_PWR_CTRL
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+//CM0_CM_MEM_PWR_STATUS
+#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+//CM0_CM_DEALPHA
+#define CM0_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM0_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM0_CM_COEF_FORMAT
+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
+//DPP_TOP0_DPP_CONTROL
+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP0_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP0_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP0_DPP_SOFT_RESET
+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP0_DPP_CRC_VAL_R_G
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP0_DPP_CRC_VAL_B_A
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP0_DPP_CRC_CTRL
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP0_HOST_READ_CONTROL
+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG1_FORMAT_CONTROL
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG1_FCNV_FP_BIAS_R
+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_BIAS_G
+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_BIAS_B
+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_R
+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_G
+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_B
+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG1_COLOR_KEYER_CONTROL
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG1_COLOR_KEYER_ALPHA
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_RED
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_GREEN
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_BLUE
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG1_ALPHA_2BIT_LUT
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG1_PRE_DEALPHA
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG1_PRE_CSC_MODE
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG1_PRE_CSC_C11_C12
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C13_C14
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C21_C22
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C23_C24
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C31_C32
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C33_C34
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C11_C12
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C13_C14
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C21_C22
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C23_C24
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C31_C32
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C33_C34
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_CNVC_COEF_FORMAT
+#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG1_PRE_DEGAM
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG1_PRE_REALPHA
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
+//CNVC_CUR1_CURSOR0_CONTROL
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR1_CURSOR0_COLOR0
+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR1_CURSOR0_COLOR1
+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR1_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
+//DSCL1_SCL_COEF_RAM_TAP_SELECT
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00030000L
+//DSCL1_SCL_COEF_RAM_TAP_DATA
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL1_SCL_MODE
+#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL1_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL1_SCL_TAP_CONTROL
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL1_DSCL_CONTROL
+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL1_DSCL_2TAP_CONTROL
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL1_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL1_SCL_HORZ_FILTER_INIT
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL1_SCL_HORZ_FILTER_INIT_C
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL1_SCL_VERT_FILTER_INIT
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL1_SCL_VERT_FILTER_INIT_BOT
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL1_SCL_VERT_FILTER_INIT_C
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL1_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL1_SCL_BLACK_COLOR
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL1_DSCL_UPDATE
+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL1_DSCL_AUTOCAL
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL1_OTG_H_BLANK
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL1_OTG_V_BLANK
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL1_RECOUT_START
+#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL1_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL1_RECOUT_SIZE
+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL1_MPC_SIZE
+#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL1_LB_DATA_FORMAT
+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL1_LB_MEMORY_CTRL
+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL1_LB_V_COUNTER
+#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL1_DSCL_MEM_PWR_CTRL
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL1_DSCL_MEM_PWR_STATUS
+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL1_OBUF_CONTROL
+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL1_OBUF_MEM_PWR_CTRL
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
+//CM1_CM_CONTROL
+#define CM1_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM1_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM1_CM_POST_CSC_CONTROL
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM1_CM_POST_CSC_C11_C12
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C13_C14
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C21_C22
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C23_C24
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C31_C32
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C33_C34
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_B_C11_C12
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C13_C14
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C21_C22
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C23_C24
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C31_C32
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C33_C34
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_CONTROL
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM1_CM_GAMUT_REMAP_C11_C12
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C13_C14
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C21_C22
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C23_C24
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C31_C32
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C33_C34
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C11_C12
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C13_C14
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C21_C22
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C23_C24
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C31_C32
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C33_C34
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM1_CM_BIAS_CR_R
+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM1_CM_BIAS_Y_G_CB_B
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM1_CM_GAMCOR_CONTROL
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM1_CM_GAMCOR_LUT_INDEX
+#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM1_CM_GAMCOR_LUT_DATA
+#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM1_CM_GAMCOR_LUT_CONTROL
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT                                              0x5
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK                                                0x00000020L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM1_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMA_OFFSET_B
+#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMA_OFFSET_G
+#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMA_OFFSET_R
+#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMA_REGION_0_1
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_2_3
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_4_5
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_6_7
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_8_9
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_10_11
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_12_13
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_14_15
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_16_17
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_18_19
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_20_21
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_22_23
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_24_25
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_26_27
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_28_29
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_30_31
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_32_33
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMB_OFFSET_B
+#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMB_OFFSET_G
+#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMB_OFFSET_R
+#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMB_REGION_0_1
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_2_3
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_4_5
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_6_7
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_8_9
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_10_11
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_12_13
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_14_15
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_16_17
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_18_19
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_20_21
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_22_23
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_24_25
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_26_27
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_28_29
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_30_31
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_32_33
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_HDR_MULT_COEF
+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM1_CM_MEM_PWR_CTRL
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+//CM1_CM_MEM_PWR_STATUS
+#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+//CM1_CM_DEALPHA
+#define CM1_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM1_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM1_CM_COEF_FORMAT
+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
+//DPP_TOP1_DPP_CONTROL
+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP1_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP1_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP1_DPP_SOFT_RESET
+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP1_DPP_CRC_VAL_R_G
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP1_DPP_CRC_VAL_B_A
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP1_DPP_CRC_CTRL
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP1_HOST_READ_CONTROL
+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG2_FORMAT_CONTROL
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG2_FCNV_FP_BIAS_R
+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_BIAS_G
+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_BIAS_B
+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_SCALE_R
+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_SCALE_G
+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_SCALE_B
+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG2_COLOR_KEYER_CONTROL
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG2_COLOR_KEYER_ALPHA
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG2_COLOR_KEYER_RED
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG2_COLOR_KEYER_GREEN
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG2_COLOR_KEYER_BLUE
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG2_ALPHA_2BIT_LUT
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG2_PRE_DEALPHA
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG2_PRE_CSC_MODE
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG2_PRE_CSC_C11_C12
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C13_C14
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C21_C22
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C23_C24
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C31_C32
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C33_C34
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C11_C12
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C13_C14
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C21_C22
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C23_C24
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C31_C32
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C33_C34
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_CNVC_COEF_FORMAT
+#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG2_PRE_DEGAM
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG2_PRE_REALPHA
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
+//CNVC_CUR2_CURSOR0_CONTROL
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR2_CURSOR0_COLOR0
+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR2_CURSOR0_COLOR1
+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR2_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
+//DSCL2_SCL_COEF_RAM_TAP_SELECT
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00030000L
+//DSCL2_SCL_COEF_RAM_TAP_DATA
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL2_SCL_MODE
+#define DSCL2_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL2_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL2_SCL_TAP_CONTROL
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL2_DSCL_CONTROL
+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL2_DSCL_2TAP_CONTROL
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL2_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL2_SCL_HORZ_FILTER_INIT
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL2_SCL_HORZ_FILTER_INIT_C
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL2_SCL_VERT_FILTER_INIT
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL2_SCL_VERT_FILTER_INIT_BOT
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL2_SCL_VERT_FILTER_INIT_C
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL2_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL2_SCL_BLACK_COLOR
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL2_DSCL_UPDATE
+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL2_DSCL_AUTOCAL
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL2_OTG_H_BLANK
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL2_OTG_V_BLANK
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL2_RECOUT_START
+#define DSCL2_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL2_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL2_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL2_RECOUT_SIZE
+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL2_MPC_SIZE
+#define DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL2_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL2_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL2_LB_DATA_FORMAT
+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL2_LB_MEMORY_CTRL
+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL2_LB_V_COUNTER
+#define DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL2_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL2_DSCL_MEM_PWR_CTRL
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL2_DSCL_MEM_PWR_STATUS
+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL2_OBUF_CONTROL
+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL2_OBUF_MEM_PWR_CTRL
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
+//CM2_CM_CONTROL
+#define CM2_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM2_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM2_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM2_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM2_CM_POST_CSC_CONTROL
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM2_CM_POST_CSC_C11_C12
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C13_C14
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C21_C22
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C23_C24
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C31_C32
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C33_C34
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_B_C11_C12
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C13_C14
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C21_C22
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C23_C24
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C31_C32
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C33_C34
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_CONTROL
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM2_CM_GAMUT_REMAP_C11_C12
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C13_C14
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C21_C22
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C23_C24
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C31_C32
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C33_C34
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C11_C12
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C13_C14
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C21_C22
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C23_C24
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C31_C32
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C33_C34
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM2_CM_BIAS_CR_R
+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM2_CM_BIAS_Y_G_CB_B
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM2_CM_GAMCOR_CONTROL
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM2_CM_GAMCOR_LUT_INDEX
+#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM2_CM_GAMCOR_LUT_DATA
+#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM2_CM_GAMCOR_LUT_CONTROL
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT                                              0x5
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK                                                0x00000020L
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM2_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMA_OFFSET_B
+#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMA_OFFSET_G
+#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMA_OFFSET_R
+#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMA_REGION_0_1
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_2_3
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_4_5
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_6_7
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_8_9
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_10_11
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_12_13
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_14_15
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_16_17
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_18_19
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_20_21
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_22_23
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_24_25
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_26_27
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_28_29
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_30_31
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_32_33
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMB_OFFSET_B
+#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMB_OFFSET_G
+#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMB_OFFSET_R
+#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMB_REGION_0_1
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_2_3
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_4_5
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_6_7
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_8_9
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_10_11
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_12_13
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_14_15
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_16_17
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_18_19
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_20_21
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_22_23
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_24_25
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_26_27
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_28_29
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_30_31
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_32_33
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_HDR_MULT_COEF
+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM2_CM_MEM_PWR_CTRL
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+//CM2_CM_MEM_PWR_STATUS
+#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+//CM2_CM_DEALPHA
+#define CM2_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM2_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM2_CM_COEF_FORMAT
+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
+//DPP_TOP2_DPP_CONTROL
+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP2_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP2_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP2_DPP_SOFT_RESET
+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP2_DPP_CRC_VAL_R_G
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP2_DPP_CRC_VAL_B_A
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP2_DPP_CRC_CTRL
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP2_HOST_READ_CONTROL
+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG3_FORMAT_CONTROL
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG3_FCNV_FP_BIAS_R
+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_BIAS_G
+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_BIAS_B
+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_SCALE_R
+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_SCALE_G
+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_SCALE_B
+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG3_COLOR_KEYER_CONTROL
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG3_COLOR_KEYER_ALPHA
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG3_COLOR_KEYER_RED
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG3_COLOR_KEYER_GREEN
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG3_COLOR_KEYER_BLUE
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG3_ALPHA_2BIT_LUT
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG3_PRE_DEALPHA
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG3_PRE_CSC_MODE
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG3_PRE_CSC_C11_C12
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C13_C14
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C21_C22
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C23_C24
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C31_C32
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C33_C34
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C11_C12
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C13_C14
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C21_C22
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C23_C24
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C31_C32
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C33_C34
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_CNVC_COEF_FORMAT
+#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG3_PRE_DEGAM
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG3_PRE_REALPHA
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
+//CNVC_CUR3_CURSOR0_CONTROL
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR3_CURSOR0_COLOR0
+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR3_CURSOR0_COLOR1
+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR3_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
+//DSCL3_SCL_COEF_RAM_TAP_SELECT
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00030000L
+//DSCL3_SCL_COEF_RAM_TAP_DATA
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL3_SCL_MODE
+#define DSCL3_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL3_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL3_SCL_TAP_CONTROL
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL3_DSCL_CONTROL
+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL3_DSCL_2TAP_CONTROL
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL3_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL3_SCL_HORZ_FILTER_INIT
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL3_SCL_HORZ_FILTER_INIT_C
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL3_SCL_VERT_FILTER_INIT
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL3_SCL_VERT_FILTER_INIT_BOT
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL3_SCL_VERT_FILTER_INIT_C
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL3_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL3_SCL_BLACK_COLOR
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL3_DSCL_UPDATE
+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL3_DSCL_AUTOCAL
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL3_OTG_H_BLANK
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL3_OTG_V_BLANK
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL3_RECOUT_START
+#define DSCL3_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL3_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL3_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL3_RECOUT_SIZE
+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL3_MPC_SIZE
+#define DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL3_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL3_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL3_LB_DATA_FORMAT
+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL3_LB_MEMORY_CTRL
+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL3_LB_V_COUNTER
+#define DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL3_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL3_DSCL_MEM_PWR_CTRL
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL3_DSCL_MEM_PWR_STATUS
+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL3_OBUF_CONTROL
+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL3_OBUF_MEM_PWR_CTRL
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
+//CM3_CM_CONTROL
+#define CM3_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM3_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM3_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM3_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM3_CM_POST_CSC_CONTROL
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM3_CM_POST_CSC_C11_C12
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C13_C14
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C21_C22
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C23_C24
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C31_C32
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C33_C34
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_B_C11_C12
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C13_C14
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C21_C22
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C23_C24
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C31_C32
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C33_C34
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_CONTROL
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM3_CM_GAMUT_REMAP_C11_C12
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C13_C14
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C21_C22
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C23_C24
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C31_C32
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C33_C34
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C11_C12
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C13_C14
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C21_C22
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C23_C24
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C31_C32
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C33_C34
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM3_CM_BIAS_CR_R
+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM3_CM_BIAS_Y_G_CB_B
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM3_CM_GAMCOR_CONTROL
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM3_CM_GAMCOR_LUT_INDEX
+#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM3_CM_GAMCOR_LUT_DATA
+#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM3_CM_GAMCOR_LUT_CONTROL
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT                                              0x5
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK                                                0x00000020L
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM3_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMA_OFFSET_B
+#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMA_OFFSET_G
+#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMA_OFFSET_R
+#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMA_REGION_0_1
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_2_3
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_4_5
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_6_7
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_8_9
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_10_11
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_12_13
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_14_15
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_16_17
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_18_19
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_20_21
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_22_23
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_24_25
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_26_27
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_28_29
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_30_31
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_32_33
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMB_OFFSET_B
+#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMB_OFFSET_G
+#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMB_OFFSET_R
+#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMB_REGION_0_1
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_2_3
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_4_5
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_6_7
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_8_9
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_10_11
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_12_13
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_14_15
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_16_17
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_18_19
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_20_21
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_22_23
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_24_25
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_26_27
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_28_29
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_30_31
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_32_33
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_HDR_MULT_COEF
+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM3_CM_MEM_PWR_CTRL
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+//CM3_CM_MEM_PWR_STATUS
+#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+//CM3_CM_DEALPHA
+#define CM3_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM3_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM3_CM_COEF_FORMAT
+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
+//DPP_TOP3_DPP_CONTROL
+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP3_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP3_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP3_DPP_SOFT_RESET
+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP3_DPP_CRC_VAL_R_G
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP3_DPP_CRC_VAL_B_A
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP3_DPP_CRC_CTRL
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP3_HOST_READ_CONTROL
+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dce_dc_mpc_mpcc0_dispdec
+//MPCC0_MPCC_TOP_SEL
+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC0_MPCC_BOT_SEL
+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC0_MPCC_OPP_ID
+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC0_MPCC_CONTROL
+#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC0_MPCC_SM_CONTROL
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC0_MPCC_UPDATE_LOCK_SEL
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC0_MPCC_TOP_GAIN
+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC0_MPCC_BOT_GAIN_INSIDE
+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC0_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL
+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0
+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4
+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L
+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L
+//MPCC0_MPCC_BG_R_CR
+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC0_MPCC_BG_G_Y
+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC0_MPCC_BG_B_CB
+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC0_MPCC_MEM_PWR_CTRL
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC0_MPCC_STATUS
+#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC0_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC0_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dce_dc_mpc_mpcc1_dispdec
+//MPCC1_MPCC_TOP_SEL
+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC1_MPCC_BOT_SEL
+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC1_MPCC_OPP_ID
+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC1_MPCC_CONTROL
+#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC1_MPCC_SM_CONTROL
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC1_MPCC_UPDATE_LOCK_SEL
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC1_MPCC_TOP_GAIN
+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC1_MPCC_BOT_GAIN_INSIDE
+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC1_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL
+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0
+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4
+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L
+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L
+//MPCC1_MPCC_BG_R_CR
+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC1_MPCC_BG_G_Y
+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC1_MPCC_BG_B_CB
+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC1_MPCC_MEM_PWR_CTRL
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC1_MPCC_STATUS
+#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC1_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC1_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dce_dc_mpc_mpcc2_dispdec
+//MPCC2_MPCC_TOP_SEL
+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC2_MPCC_BOT_SEL
+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC2_MPCC_OPP_ID
+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC2_MPCC_CONTROL
+#define MPCC2_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC2_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC2_MPCC_SM_CONTROL
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC2_MPCC_UPDATE_LOCK_SEL
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC2_MPCC_TOP_GAIN
+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC2_MPCC_BOT_GAIN_INSIDE
+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC2_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL
+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0
+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4
+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L
+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L
+//MPCC2_MPCC_BG_R_CR
+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC2_MPCC_BG_G_Y
+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC2_MPCC_BG_B_CB
+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC2_MPCC_MEM_PWR_CTRL
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC2_MPCC_STATUS
+#define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC2_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC2_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC2_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC2_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC2_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dce_dc_mpc_mpcc3_dispdec
+//MPCC3_MPCC_TOP_SEL
+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC3_MPCC_BOT_SEL
+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC3_MPCC_OPP_ID
+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC3_MPCC_CONTROL
+#define MPCC3_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC3_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC3_MPCC_SM_CONTROL
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC3_MPCC_UPDATE_LOCK_SEL
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC3_MPCC_TOP_GAIN
+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC3_MPCC_BOT_GAIN_INSIDE
+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC3_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL
+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0
+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4
+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L
+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L
+//MPCC3_MPCC_BG_R_CR
+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC3_MPCC_BG_G_Y
+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC3_MPCC_BG_B_CB
+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC3_MPCC_MEM_PWR_CTRL
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC3_MPCC_STATUS
+#define MPCC3_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC3_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC3_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC3_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC3_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC3_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
+//MPC_CLOCK_CONTROL
+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                      0x1
+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT                                                            0x4
+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                        0x00000002L
+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK                                                              0x00000030L
+//MPC_SOFT_RESET
+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT                                                               0x0
+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT                                                               0x1
+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET__SHIFT                                                               0x2
+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET__SHIFT                                                               0x3
+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT                                                            0xa
+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT                                                            0xb
+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET__SHIFT                                                            0xc
+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET__SHIFT                                                            0xd
+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT                                                            0x14
+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT                                                            0x15
+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET__SHIFT                                                            0x16
+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET__SHIFT                                                            0x17
+#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT                                                                 0x1f
+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK                                                                 0x00000001L
+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK                                                                 0x00000002L
+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET_MASK                                                                 0x00000004L
+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET_MASK                                                                 0x00000008L
+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK                                                              0x00000400L
+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK                                                              0x00000800L
+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET_MASK                                                              0x00001000L
+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET_MASK                                                              0x00002000L
+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK                                                              0x00100000L
+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK                                                              0x00200000L
+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET_MASK                                                              0x00400000L
+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET_MASK                                                              0x00800000L
+#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK                                                                   0x80000000L
+//MPC_CRC_CTRL
+#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT                                                                       0x0
+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT                                                                  0x4
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT                                                              0x8
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT                                                                0xa
+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT                                                           0xc
+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT                                                                  0x18
+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT                                                         0x1c
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED__SHIFT                                                           0x1e
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT                                                              0x1f
+#define MPC_CRC_CTRL__MPC_CRC_EN_MASK                                                                         0x00000001L
+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK                                                                    0x00000010L
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK                                                                0x00000300L
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK                                                                  0x00000400L
+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK                                                             0x00003000L
+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK                                                                    0x03000000L
+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK                                                           0x10000000L
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED_MASK                                                             0x40000000L
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK                                                                0x80000000L
+//MPC_CRC_SEL_CONTROL
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT                                                           0x0
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT                                                           0x4
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL__SHIFT                                                           0x8
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT                                                              0x10
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK                                                             0x0000000FL
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK                                                             0x000000F0L
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL_MASK                                                             0x00000300L
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK                                                                0xFFFF0000L
+//MPC_CRC_RESULT_AR
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A__SHIFT                                                            0x0
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R__SHIFT                                                            0x10
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A_MASK                                                              0x0000FFFFL
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R_MASK                                                              0xFFFF0000L
+//MPC_CRC_RESULT_GB
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G__SHIFT                                                            0x0
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B__SHIFT                                                            0x10
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G_MASK                                                              0x0000FFFFL
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B_MASK                                                              0xFFFF0000L
+//MPC_CRC_RESULT_C
+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C__SHIFT                                                             0x0
+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C_MASK                                                               0x0000FFFFL
+//MPC_BYPASS_BG_AR
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT                                                          0x0
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT                                                           0x10
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK                                                            0x0000FFFFL
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK                                                             0xFFFF0000L
+//MPC_BYPASS_BG_GB
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT                                                            0x0
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT                                                           0x10
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK                                                              0x0000FFFFL
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK                                                             0xFFFF0000L
+//MPC_HOST_READ_CONTROL
+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                                  0x0
+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                                    0x000000FFL
+//MPC_DPP_PENDING_STATUS
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING__SHIFT                                         0x0
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING__SHIFT                                          0x1
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING__SHIFT                                          0x2
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING__SHIFT                                         0x4
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING__SHIFT                                          0x5
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING__SHIFT                                          0x6
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING__SHIFT                                         0x8
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING__SHIFT                                          0x9
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING__SHIFT                                          0xa
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING__SHIFT                                         0xc
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING__SHIFT                                          0xd
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING__SHIFT                                          0xe
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING_MASK                                           0x00000001L
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING_MASK                                            0x00000002L
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING_MASK                                            0x00000004L
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING_MASK                                           0x00000010L
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING_MASK                                            0x00000020L
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING_MASK                                            0x00000040L
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING_MASK                                           0x00000100L
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING_MASK                                            0x00000200L
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING_MASK                                            0x00000400L
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING_MASK                                           0x00001000L
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING_MASK                                            0x00002000L
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING_MASK                                            0x00004000L
+//MPC_PENDING_STATUS_MISC
+#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING__SHIFT                                        0x0
+#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING__SHIFT                                        0x1
+#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING__SHIFT                                        0x2
+#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING__SHIFT                                        0x3
+#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING__SHIFT                                           0x8
+#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING__SHIFT                                           0x9
+#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING__SHIFT                                           0xa
+#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING__SHIFT                                           0xb
+#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING__SHIFT                                         0x10
+#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING_MASK                                          0x00000001L
+#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING_MASK                                          0x00000002L
+#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING_MASK                                          0x00000004L
+#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING_MASK                                          0x00000008L
+#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING_MASK                                             0x00000100L
+#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING_MASK                                             0x00000200L
+#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING_MASK                                             0x00000400L
+#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING_MASK                                             0x00000800L
+#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING_MASK                                           0x00010000L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET0
+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET0
+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET0
+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET0
+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET1
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET1
+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET1
+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET1
+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET1
+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET2
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET2
+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET2
+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET2
+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET2
+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET3
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET3
+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET3
+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET3
+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET3
+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//MPC_DWB0_MUX
+#define MPC_DWB0_MUX__MPC_DWB0_MUX__SHIFT                                                                     0x0
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS__SHIFT                                                              0x4
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_MASK                                                                       0x0000000FL
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS_MASK                                                                0x000000F0L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
+//MPCC_OGAM0_MPCC_OGAM_CONTROL
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM0_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM0_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
+//MPCC_OGAM1_MPCC_OGAM_CONTROL
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM1_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM1_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
+//MPCC_OGAM2_MPCC_OGAM_CONTROL
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM2_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM2_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
+//MPCC_OGAM3_MPCC_OGAM_CONTROL
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM3_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM3_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_mcm0_dispdec
+//MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2
+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL
+//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL
+//MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL
+//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL
+//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_3DLUT_MODE
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L
+//MPCC_MCM0_MPCC_MCM_3DLUT_INDEX
+#define MPCC_MCM0_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL
+//MPCC_MCM0_MPCC_MCM_3DLUT_DATA
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL
+//MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L
+//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL
+//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L
+//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT                              0x5
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK                                0x00000020L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_mcm1_dispdec
+//MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2
+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL
+//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL
+//MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL
+//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL
+//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_3DLUT_MODE
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L
+//MPCC_MCM1_MPCC_MCM_3DLUT_INDEX
+#define MPCC_MCM1_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL
+//MPCC_MCM1_MPCC_MCM_3DLUT_DATA
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL
+//MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L
+//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL
+//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L
+//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT                              0x5
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK                                0x00000020L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_mcm2_dispdec
+//MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2
+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL
+//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL
+//MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL
+//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL
+//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_3DLUT_MODE
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L
+//MPCC_MCM2_MPCC_MCM_3DLUT_INDEX
+#define MPCC_MCM2_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL
+//MPCC_MCM2_MPCC_MCM_3DLUT_DATA
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL
+//MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L
+//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL
+//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L
+//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT                              0x5
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK                                0x00000020L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_mcm3_dispdec
+//MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2
+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL
+//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL
+//MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL
+//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL
+//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_3DLUT_MODE
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L
+//MPCC_MCM3_MPCC_MCM_3DLUT_INDEX
+#define MPCC_MCM3_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL
+//MPCC_MCM3_MPCC_MCM_3DLUT_DATA
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL
+//MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L
+//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL
+//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L
+//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT                              0x5
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK                                0x00000020L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L
+
+
+// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
+//MPC_OUT0_MUX
+#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT0_DENORM_CONTROL
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT0_DENORM_CLAMP_G_Y
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT0_DENORM_CLAMP_B_CB
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT1_MUX
+#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT1_DENORM_CONTROL
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT1_DENORM_CLAMP_G_Y
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT1_DENORM_CLAMP_B_CB
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT2_MUX
+#define MPC_OUT2_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT2_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT2_DENORM_CONTROL
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT2_DENORM_CLAMP_G_Y
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT2_DENORM_CLAMP_B_CB
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT3_MUX
+#define MPC_OUT3_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT3_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT3_DENORM_CONTROL
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT3_DENORM_CLAMP_G_Y
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT3_DENORM_CLAMP_B_CB
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT_CSC_COEF_FORMAT
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT__SHIFT                                                 0x0
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT__SHIFT                                                 0x1
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT__SHIFT                                                 0x2
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT__SHIFT                                                 0x3
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT_MASK                                                   0x00000001L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT_MASK                                                   0x00000002L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT_MASK                                                   0x00000004L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT_MASK                                                   0x00000008L
+//MPC_OUT0_CSC_MODE
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT0_CSC_C11_C12_A
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C13_C14_A
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C21_C22_A
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C23_C24_A
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C31_C32_A
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C33_C34_A
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C11_C12_B
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C13_C14_B
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C21_C22_B
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C23_C24_B
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C31_C32_B
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C33_C34_B
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_MODE
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT1_CSC_C11_C12_A
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C13_C14_A
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C21_C22_A
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C23_C24_A
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C31_C32_A
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C33_C34_A
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C11_C12_B
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C13_C14_B
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C21_C22_B
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C23_C24_B
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C31_C32_B
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C33_C34_B
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_MODE
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT2_CSC_C11_C12_A
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C13_C14_A
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C21_C22_A
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C23_C24_A
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C31_C32_A
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C33_C34_A
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C11_C12_B
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C13_C14_B
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C21_C22_B
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C23_C24_B
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C31_C32_B
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C33_C34_B
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_MODE
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT3_CSC_C11_C12_A
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C13_C14_A
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C21_C22_A
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C23_C24_A
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C31_C32_A
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C33_C34_A
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C11_C12_B
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C13_C14_B
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C21_C22_B
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C23_C24_B
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C31_C32_B
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C33_C34_B
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+
+
+// addressBlock: dce_dc_opp_abm0_dispdec
+//ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM0_BL1_PWM_USER_LEVEL
+#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM0_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM0_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM0_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM0_BL1_PWM_ABM_CNTL
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM0_BL1_PWM_GRP2_REG_LOCK
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM0_DC_ABM1_CNTL
+#define ABM0_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM0_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM0_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_THRES_12
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM0_DC_ABM1_ACE_THRES_34
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM0_DC_ABM1_ACE_CNTL_MISC
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM0_DC_ABM1_HG_MISC_CTRL
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM0_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM0_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM0_DC_ABM1_LS_PIXEL_COUNT
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM0_DC_ABM1_HG_SAMPLE_RATE
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM0_DC_ABM1_LS_SAMPLE_RATE
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_1
+#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_2
+#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_3
+#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_4
+#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_5
+#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_6
+#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_7
+#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_8
+#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_9
+#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_10
+#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_11
+#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_12
+#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_13
+#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_14
+#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_15
+#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_16
+#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_17
+#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_18
+#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_19
+#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_20
+#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_21
+#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_22
+#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_23
+#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_24
+#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_BL_MASTER_LOCK
+#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dce_dc_opp_abm1_dispdec
+//ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM1_BL1_PWM_USER_LEVEL
+#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM1_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM1_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM1_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM1_BL1_PWM_ABM_CNTL
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM1_BL1_PWM_GRP2_REG_LOCK
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM1_DC_ABM1_CNTL
+#define ABM1_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM1_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM1_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_THRES_12
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM1_DC_ABM1_ACE_THRES_34
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM1_DC_ABM1_ACE_CNTL_MISC
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM1_DC_ABM1_HG_MISC_CTRL
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM1_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM1_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM1_DC_ABM1_LS_PIXEL_COUNT
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM1_DC_ABM1_HG_SAMPLE_RATE
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM1_DC_ABM1_LS_SAMPLE_RATE
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_1
+#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_2
+#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_3
+#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_4
+#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_5
+#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_6
+#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_7
+#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_8
+#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_9
+#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_10
+#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_11
+#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_12
+#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_13
+#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_14
+#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_15
+#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_16
+#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_17
+#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_18
+#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_19
+#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_20
+#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_21
+#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_22
+#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_23
+#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_24
+#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_BL_MASTER_LOCK
+#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dce_dc_opp_abm2_dispdec
+//ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM2_BL1_PWM_USER_LEVEL
+#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM2_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM2_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM2_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM2_BL1_PWM_ABM_CNTL
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM2_BL1_PWM_GRP2_REG_LOCK
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM2_DC_ABM1_CNTL
+#define ABM2_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM2_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM2_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_THRES_12
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM2_DC_ABM1_ACE_THRES_34
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM2_DC_ABM1_ACE_CNTL_MISC
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM2_DC_ABM1_HG_MISC_CTRL
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM2_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM2_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM2_DC_ABM1_LS_PIXEL_COUNT
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM2_DC_ABM1_HG_SAMPLE_RATE
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM2_DC_ABM1_LS_SAMPLE_RATE
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_1
+#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_2
+#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_3
+#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_4
+#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_5
+#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_6
+#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_7
+#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_8
+#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_9
+#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_10
+#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_11
+#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_12
+#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_13
+#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_14
+#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_15
+#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_16
+#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_17
+#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_18
+#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_19
+#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_20
+#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_21
+#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_22
+#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_23
+#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_24
+#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_BL_MASTER_LOCK
+#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dce_dc_opp_abm3_dispdec
+//ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM3_BL1_PWM_USER_LEVEL
+#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM3_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM3_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM3_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM3_BL1_PWM_ABM_CNTL
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM3_BL1_PWM_GRP2_REG_LOCK
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM3_DC_ABM1_CNTL
+#define ABM3_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM3_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM3_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_THRES_12
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM3_DC_ABM1_ACE_THRES_34
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM3_DC_ABM1_ACE_CNTL_MISC
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM3_DC_ABM1_HG_MISC_CTRL
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM3_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM3_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM3_DC_ABM1_LS_PIXEL_COUNT
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM3_DC_ABM1_HG_SAMPLE_RATE
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM3_DC_ABM1_LS_SAMPLE_RATE
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_1
+#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_2
+#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_3
+#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_4
+#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_5
+#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_6
+#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_7
+#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_8
+#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_9
+#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_10
+#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_11
+#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_12
+#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_13
+#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_14
+#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_15
+#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_16
+#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_17
+#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_18
+#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_19
+#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_20
+#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_21
+#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_22
+#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_23
+#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_24
+#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_BL_MASTER_LOCK
+#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dce_dc_opp_dpg0_dispdec
+//DPG0_DPG_CONTROL
+#define DPG0_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG0_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG0_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG0_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG0_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG0_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG0_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG0_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG0_DPG_RAMP_CONTROL
+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG0_DPG_DIMENSIONS
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG0_DPG_COLOUR_R_CR
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG0_DPG_COLOUR_G_Y
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG0_DPG_COLOUR_B_CB
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG0_DPG_OFFSET_SEGMENT
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG0_DPG_STATUS
+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dce_dc_opp_fmt0_dispdec
+//FMT0_FMT_CLAMP_COMPONENT_R
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT0_FMT_CLAMP_COMPONENT_G
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT0_FMT_CLAMP_COMPONENT_B
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT0_FMT_DYNAMIC_EXP_CNTL
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT0_FMT_CONTROL
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT0_FMT_BIT_DEPTH_CONTROL
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT0_FMT_DITHER_RAND_R_SEED
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT0_FMT_DITHER_RAND_G_SEED
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT0_FMT_DITHER_RAND_B_SEED
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT0_FMT_CLAMP_CNTL
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT0_FMT_MAP420_MEMORY_CONTROL
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT0_FMT_422_CONTROL
+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf0_dispdec
+//OPPBUF0_OPPBUF_CONTROL
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF0_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF0_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF0_OPPBUF_CONTROL1
+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe0_dispdec
+//OPP_PIPE0_OPP_PIPE_CONTROL
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_dpg1_dispdec
+//DPG1_DPG_CONTROL
+#define DPG1_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG1_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG1_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG1_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG1_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG1_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG1_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG1_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG1_DPG_RAMP_CONTROL
+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG1_DPG_DIMENSIONS
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG1_DPG_COLOUR_R_CR
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG1_DPG_COLOUR_G_Y
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG1_DPG_COLOUR_B_CB
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG1_DPG_OFFSET_SEGMENT
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG1_DPG_STATUS
+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dce_dc_opp_fmt1_dispdec
+//FMT1_FMT_CLAMP_COMPONENT_R
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT1_FMT_CLAMP_COMPONENT_G
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT1_FMT_CLAMP_COMPONENT_B
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT1_FMT_DYNAMIC_EXP_CNTL
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT1_FMT_CONTROL
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT1_FMT_BIT_DEPTH_CONTROL
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT1_FMT_DITHER_RAND_R_SEED
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT1_FMT_DITHER_RAND_G_SEED
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT1_FMT_DITHER_RAND_B_SEED
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT1_FMT_CLAMP_CNTL
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT1_FMT_MAP420_MEMORY_CONTROL
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT1_FMT_422_CONTROL
+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf1_dispdec
+//OPPBUF1_OPPBUF_CONTROL
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF1_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF1_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF1_OPPBUF_CONTROL1
+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe1_dispdec
+//OPP_PIPE1_OPP_PIPE_CONTROL
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_dpg2_dispdec
+//DPG2_DPG_CONTROL
+#define DPG2_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG2_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG2_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG2_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG2_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG2_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG2_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG2_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG2_DPG_RAMP_CONTROL
+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG2_DPG_DIMENSIONS
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG2_DPG_COLOUR_R_CR
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG2_DPG_COLOUR_G_Y
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG2_DPG_COLOUR_B_CB
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG2_DPG_OFFSET_SEGMENT
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG2_DPG_STATUS
+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dce_dc_opp_fmt2_dispdec
+//FMT2_FMT_CLAMP_COMPONENT_R
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT2_FMT_CLAMP_COMPONENT_G
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT2_FMT_CLAMP_COMPONENT_B
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT2_FMT_DYNAMIC_EXP_CNTL
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT2_FMT_CONTROL
+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT2_FMT_BIT_DEPTH_CONTROL
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT2_FMT_DITHER_RAND_R_SEED
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT2_FMT_DITHER_RAND_G_SEED
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT2_FMT_DITHER_RAND_B_SEED
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT2_FMT_CLAMP_CNTL
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT2_FMT_MAP420_MEMORY_CONTROL
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT2_FMT_422_CONTROL
+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf2_dispdec
+//OPPBUF2_OPPBUF_CONTROL
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF2_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF2_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF2_OPPBUF_CONTROL1
+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe2_dispdec
+//OPP_PIPE2_OPP_PIPE_CONTROL
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_dpg3_dispdec
+//DPG3_DPG_CONTROL
+#define DPG3_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG3_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG3_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG3_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG3_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG3_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG3_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG3_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG3_DPG_RAMP_CONTROL
+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG3_DPG_DIMENSIONS
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG3_DPG_COLOUR_R_CR
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG3_DPG_COLOUR_G_Y
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG3_DPG_COLOUR_B_CB
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG3_DPG_OFFSET_SEGMENT
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG3_DPG_STATUS
+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dce_dc_opp_fmt3_dispdec
+//FMT3_FMT_CLAMP_COMPONENT_R
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT3_FMT_CLAMP_COMPONENT_G
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT3_FMT_CLAMP_COMPONENT_B
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT3_FMT_DYNAMIC_EXP_CNTL
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT3_FMT_CONTROL
+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT3_FMT_BIT_DEPTH_CONTROL
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT3_FMT_DITHER_RAND_R_SEED
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT3_FMT_DITHER_RAND_G_SEED
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT3_FMT_DITHER_RAND_B_SEED
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT3_FMT_CLAMP_CNTL
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT3_FMT_MAP420_MEMORY_CONTROL
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT3_FMT_422_CONTROL
+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf3_dispdec
+//OPPBUF3_OPPBUF_CONTROL
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF3_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF3_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF3_OPPBUF_CONTROL1
+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe3_dispdec
+//OPP_PIPE3_OPP_PIPE_CONTROL
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_dscrm0_dispdec
+//DSCRM0_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dce_dc_opp_dscrm1_dispdec
+//DSCRM1_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dce_dc_opp_dscrm2_dispdec
+//DSCRM2_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dce_dc_opp_dscrm3_dispdec
+//DSCRM3_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dce_dc_opp_opp_top_dispdec
+//OPP_TOP_CLK_CONTROL
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT                                                0x4
+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT                                                          0x8
+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT                                                         0xc
+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT                                                         0xd
+#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON__SHIFT                                                         0xe
+#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON__SHIFT                                                         0xf
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK                                                  0x00000010L
+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK                                                            0x00000F00L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK                                                           0x00001000L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK                                                           0x00002000L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON_MASK                                                           0x00004000L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON_MASK                                                           0x00008000L
+//OPP_ABM_CONTROL
+#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL__SHIFT                                                             0x0
+#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL_MASK                                                               0x00000007L
+
+
+// addressBlock: dce_dc_optc_odm0_dispdec
+//ODM0_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM0_OPTC_DATA_SOURCE_SELECT
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L
+//ODM0_OPTC_DATA_FORMAT_CONTROL
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM0_OPTC_BYTES_PER_PIXEL
+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM0_OPTC_WIDTH_CONTROL
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM0_OPTC_INPUT_CLOCK_CONTROL
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM0_OPTC_MEMORY_CONFIG
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L
+//ODM0_OPTC_INPUT_SPARE_REGISTER
+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm1_dispdec
+//ODM1_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM1_OPTC_DATA_SOURCE_SELECT
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L
+//ODM1_OPTC_DATA_FORMAT_CONTROL
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM1_OPTC_BYTES_PER_PIXEL
+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM1_OPTC_WIDTH_CONTROL
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM1_OPTC_INPUT_CLOCK_CONTROL
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM1_OPTC_MEMORY_CONFIG
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L
+//ODM1_OPTC_INPUT_SPARE_REGISTER
+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm2_dispdec
+//ODM2_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM2_OPTC_DATA_SOURCE_SELECT
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L
+//ODM2_OPTC_DATA_FORMAT_CONTROL
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM2_OPTC_BYTES_PER_PIXEL
+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM2_OPTC_WIDTH_CONTROL
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM2_OPTC_INPUT_CLOCK_CONTROL
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM2_OPTC_MEMORY_CONFIG
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L
+//ODM2_OPTC_INPUT_SPARE_REGISTER
+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm3_dispdec
+//ODM3_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM3_OPTC_DATA_SOURCE_SELECT
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L
+//ODM3_OPTC_DATA_FORMAT_CONTROL
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM3_OPTC_BYTES_PER_PIXEL
+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM3_OPTC_WIDTH_CONTROL
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM3_OPTC_INPUT_CLOCK_CONTROL
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM3_OPTC_MEMORY_CONFIG
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L
+//ODM3_OPTC_INPUT_SPARE_REGISTER
+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg0_dispdec
+//OTG0_OTG_H_TOTAL
+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG0_OTG_H_BLANK_START_END
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG0_OTG_H_SYNC_A
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG0_OTG_H_SYNC_A_CNTL
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG0_OTG_H_TIMING_CNTL
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L
+//OTG0_OTG_V_TOTAL
+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG0_OTG_V_TOTAL_MIN
+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG0_OTG_V_TOTAL_MAX
+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG0_OTG_V_TOTAL_MID
+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG0_OTG_V_TOTAL_CONTROL
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG0_OTG_V_TOTAL_INT_STATUS
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG0_OTG_VSYNC_NOM_INT_STATUS
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG0_OTG_V_BLANK_START_END
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG0_OTG_V_SYNC_A
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG0_OTG_V_SYNC_A_CNTL
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG0_OTG_TRIGA_CNTL
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG0_OTG_TRIGA_MANUAL_TRIG
+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG0_OTG_TRIGB_CNTL
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG0_OTG_TRIGB_MANUAL_TRIG
+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG0_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG0_OTG_FLOW_CONTROL
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG0_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG0_OTG_CONTROL
+#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG0_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG0_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L
+//OTG0_OTG_INTERLACE_CONTROL
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG0_OTG_INTERLACE_STATUS
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG0_OTG_PIXEL_DATA_READBACK0
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG0_OTG_PIXEL_DATA_READBACK1
+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG0_OTG_STATUS
+#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG0_OTG_STATUS_POSITION
+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG0_OTG_NOM_VERT_POSITION
+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG0_OTG_STATUS_FRAME_COUNT
+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG0_OTG_STATUS_VF_COUNT
+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG0_OTG_STATUS_HV_COUNT
+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG0_OTG_COUNT_CONTROL
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG0_OTG_COUNT_RESET
+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG0_OTG_VERT_SYNC_CONTROL
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG0_OTG_STEREO_STATUS
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG0_OTG_STEREO_CONTROL
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG0_OTG_SNAPSHOT_STATUS
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG0_OTG_SNAPSHOT_CONTROL
+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG0_OTG_SNAPSHOT_POSITION
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG0_OTG_SNAPSHOT_FRAME
+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG0_OTG_INTERRUPT_CONTROL
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG0_OTG_UPDATE_LOCK
+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG0_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG0_OTG_MASTER_EN
+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG0_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L
+//OTG0_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG0_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG0_OTG_CRC_CNTL
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG0_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_DATA_RG
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC0_DATA_B
+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_DATA_RG
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC1_DATA_B
+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC2_DATA_RG
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC2_DATA_B
+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC3_DATA_RG
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC3_DATA_B
+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG0_OTG_STATIC_SCREEN_CONTROL
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG0_OTG_3D_STRUCTURE_CONTROL
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG0_OTG_GSL_VSYNC_GAP
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG0_OTG_MASTER_UPDATE_MODE
+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG0_OTG_CLOCK_CONTROL
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG0_OTG_VSTARTUP_PARAM
+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG0_OTG_VUPDATE_PARAM
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG0_OTG_VREADY_PARAM
+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG0_OTG_GLOBAL_SYNC_STATUS
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG0_OTG_MASTER_UPDATE_LOCK
+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG0_OTG_GSL_CONTROL
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG0_OTG_GSL_WINDOW_X
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG0_OTG_GSL_WINDOW_Y
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG0_OTG_VUPDATE_KEEPOUT
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL0
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL1
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL2
+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL3
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG0_OTG_GLOBAL_CONTROL4
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG0_OTG_TRIG_MANUAL_CONTROL
+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG0_OTG_MANUAL_FLOW_CONTROL
+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG0_OTG_DRR_TIMING_INT_STATUS
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG0_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG0_OTG_DRR_V_TOTAL_CHANGE
+#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG0_OTG_DRR_TRIGGER_WINDOW
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG0_OTG_DRR_CONTROL
+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG0_OTG_M_CONST_DTO0
+#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG0_OTG_M_CONST_DTO1
+#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG0_OTG_REQUEST_CONTROL
+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG0_OTG_DSC_START_POSITION
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG0_OTG_PIPE_UPDATE_STATUS
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG0_OTG_SPARE_REGISTER
+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg1_dispdec
+//OTG1_OTG_H_TOTAL
+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG1_OTG_H_BLANK_START_END
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG1_OTG_H_SYNC_A
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG1_OTG_H_SYNC_A_CNTL
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG1_OTG_H_TIMING_CNTL
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L
+//OTG1_OTG_V_TOTAL
+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG1_OTG_V_TOTAL_MIN
+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG1_OTG_V_TOTAL_MAX
+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG1_OTG_V_TOTAL_MID
+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG1_OTG_V_TOTAL_CONTROL
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG1_OTG_V_TOTAL_INT_STATUS
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG1_OTG_VSYNC_NOM_INT_STATUS
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG1_OTG_V_BLANK_START_END
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG1_OTG_V_SYNC_A
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG1_OTG_V_SYNC_A_CNTL
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG1_OTG_TRIGA_CNTL
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG1_OTG_TRIGA_MANUAL_TRIG
+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG1_OTG_TRIGB_CNTL
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG1_OTG_TRIGB_MANUAL_TRIG
+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG1_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG1_OTG_FLOW_CONTROL
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG1_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG1_OTG_CONTROL
+#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG1_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG1_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L
+//OTG1_OTG_INTERLACE_CONTROL
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG1_OTG_INTERLACE_STATUS
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG1_OTG_PIXEL_DATA_READBACK0
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG1_OTG_PIXEL_DATA_READBACK1
+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG1_OTG_STATUS
+#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG1_OTG_STATUS_POSITION
+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG1_OTG_NOM_VERT_POSITION
+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG1_OTG_STATUS_FRAME_COUNT
+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG1_OTG_STATUS_VF_COUNT
+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG1_OTG_STATUS_HV_COUNT
+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG1_OTG_COUNT_CONTROL
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG1_OTG_COUNT_RESET
+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG1_OTG_VERT_SYNC_CONTROL
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG1_OTG_STEREO_STATUS
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG1_OTG_STEREO_CONTROL
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG1_OTG_SNAPSHOT_STATUS
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG1_OTG_SNAPSHOT_CONTROL
+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG1_OTG_SNAPSHOT_POSITION
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG1_OTG_SNAPSHOT_FRAME
+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG1_OTG_INTERRUPT_CONTROL
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG1_OTG_UPDATE_LOCK
+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG1_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG1_OTG_MASTER_EN
+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG1_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L
+//OTG1_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG1_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG1_OTG_CRC_CNTL
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG1_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_DATA_RG
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC0_DATA_B
+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_DATA_RG
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC1_DATA_B
+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC2_DATA_RG
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC2_DATA_B
+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC3_DATA_RG
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC3_DATA_B
+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG1_OTG_STATIC_SCREEN_CONTROL
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG1_OTG_3D_STRUCTURE_CONTROL
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG1_OTG_GSL_VSYNC_GAP
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG1_OTG_MASTER_UPDATE_MODE
+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG1_OTG_CLOCK_CONTROL
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG1_OTG_VSTARTUP_PARAM
+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG1_OTG_VUPDATE_PARAM
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG1_OTG_VREADY_PARAM
+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG1_OTG_GLOBAL_SYNC_STATUS
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG1_OTG_MASTER_UPDATE_LOCK
+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG1_OTG_GSL_CONTROL
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG1_OTG_GSL_WINDOW_X
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG1_OTG_GSL_WINDOW_Y
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG1_OTG_VUPDATE_KEEPOUT
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL0
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL1
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL2
+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL3
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG1_OTG_GLOBAL_CONTROL4
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG1_OTG_TRIG_MANUAL_CONTROL
+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG1_OTG_MANUAL_FLOW_CONTROL
+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG1_OTG_DRR_TIMING_INT_STATUS
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG1_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG1_OTG_DRR_V_TOTAL_CHANGE
+#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG1_OTG_DRR_TRIGGER_WINDOW
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG1_OTG_DRR_CONTROL
+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG1_OTG_M_CONST_DTO0
+#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG1_OTG_M_CONST_DTO1
+#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG1_OTG_REQUEST_CONTROL
+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG1_OTG_DSC_START_POSITION
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG1_OTG_PIPE_UPDATE_STATUS
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG1_OTG_SPARE_REGISTER
+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg2_dispdec
+//OTG2_OTG_H_TOTAL
+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG2_OTG_H_BLANK_START_END
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG2_OTG_H_SYNC_A
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG2_OTG_H_SYNC_A_CNTL
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG2_OTG_H_TIMING_CNTL
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L
+//OTG2_OTG_V_TOTAL
+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG2_OTG_V_TOTAL_MIN
+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG2_OTG_V_TOTAL_MAX
+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG2_OTG_V_TOTAL_MID
+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG2_OTG_V_TOTAL_CONTROL
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG2_OTG_V_TOTAL_INT_STATUS
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG2_OTG_VSYNC_NOM_INT_STATUS
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG2_OTG_V_BLANK_START_END
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG2_OTG_V_SYNC_A
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG2_OTG_V_SYNC_A_CNTL
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG2_OTG_TRIGA_CNTL
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG2_OTG_TRIGA_MANUAL_TRIG
+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG2_OTG_TRIGB_CNTL
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG2_OTG_TRIGB_MANUAL_TRIG
+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG2_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG2_OTG_FLOW_CONTROL
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG2_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG2_OTG_CONTROL
+#define OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG2_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG2_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L
+//OTG2_OTG_INTERLACE_CONTROL
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG2_OTG_INTERLACE_STATUS
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG2_OTG_PIXEL_DATA_READBACK0
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG2_OTG_PIXEL_DATA_READBACK1
+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG2_OTG_STATUS
+#define OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG2_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG2_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG2_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG2_OTG_STATUS_POSITION
+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG2_OTG_NOM_VERT_POSITION
+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG2_OTG_STATUS_FRAME_COUNT
+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG2_OTG_STATUS_VF_COUNT
+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG2_OTG_STATUS_HV_COUNT
+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG2_OTG_COUNT_CONTROL
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG2_OTG_COUNT_RESET
+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG2_OTG_VERT_SYNC_CONTROL
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG2_OTG_STEREO_STATUS
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG2_OTG_STEREO_CONTROL
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG2_OTG_SNAPSHOT_STATUS
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG2_OTG_SNAPSHOT_CONTROL
+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG2_OTG_SNAPSHOT_POSITION
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG2_OTG_SNAPSHOT_FRAME
+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG2_OTG_INTERRUPT_CONTROL
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG2_OTG_UPDATE_LOCK
+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG2_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG2_OTG_MASTER_EN
+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG2_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L
+//OTG2_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG2_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG2_OTG_CRC_CNTL
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG2_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_DATA_RG
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC0_DATA_B
+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_DATA_RG
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC1_DATA_B
+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC2_DATA_RG
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC2_DATA_B
+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC3_DATA_RG
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC3_DATA_B
+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG2_OTG_STATIC_SCREEN_CONTROL
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG2_OTG_3D_STRUCTURE_CONTROL
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG2_OTG_GSL_VSYNC_GAP
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG2_OTG_MASTER_UPDATE_MODE
+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG2_OTG_CLOCK_CONTROL
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG2_OTG_VSTARTUP_PARAM
+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG2_OTG_VUPDATE_PARAM
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG2_OTG_VREADY_PARAM
+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG2_OTG_GLOBAL_SYNC_STATUS
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG2_OTG_MASTER_UPDATE_LOCK
+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG2_OTG_GSL_CONTROL
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG2_OTG_GSL_WINDOW_X
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG2_OTG_GSL_WINDOW_Y
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG2_OTG_VUPDATE_KEEPOUT
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL0
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL1
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL2
+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL3
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG2_OTG_GLOBAL_CONTROL4
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG2_OTG_TRIG_MANUAL_CONTROL
+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG2_OTG_MANUAL_FLOW_CONTROL
+#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG2_OTG_DRR_TIMING_INT_STATUS
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG2_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG2_OTG_DRR_V_TOTAL_CHANGE
+#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG2_OTG_DRR_TRIGGER_WINDOW
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG2_OTG_DRR_CONTROL
+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG2_OTG_M_CONST_DTO0
+#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG2_OTG_M_CONST_DTO1
+#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG2_OTG_REQUEST_CONTROL
+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG2_OTG_DSC_START_POSITION
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG2_OTG_PIPE_UPDATE_STATUS
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG2_OTG_SPARE_REGISTER
+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg3_dispdec
+//OTG3_OTG_H_TOTAL
+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG3_OTG_H_BLANK_START_END
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG3_OTG_H_SYNC_A
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG3_OTG_H_SYNC_A_CNTL
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG3_OTG_H_TIMING_CNTL
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L
+//OTG3_OTG_V_TOTAL
+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG3_OTG_V_TOTAL_MIN
+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG3_OTG_V_TOTAL_MAX
+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG3_OTG_V_TOTAL_MID
+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG3_OTG_V_TOTAL_CONTROL
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG3_OTG_V_TOTAL_INT_STATUS
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG3_OTG_VSYNC_NOM_INT_STATUS
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG3_OTG_V_BLANK_START_END
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG3_OTG_V_SYNC_A
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG3_OTG_V_SYNC_A_CNTL
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG3_OTG_TRIGA_CNTL
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG3_OTG_TRIGA_MANUAL_TRIG
+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG3_OTG_TRIGB_CNTL
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG3_OTG_TRIGB_MANUAL_TRIG
+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG3_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG3_OTG_FLOW_CONTROL
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG3_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG3_OTG_CONTROL
+#define OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG3_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L
+//OTG3_OTG_INTERLACE_CONTROL
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG3_OTG_INTERLACE_STATUS
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG3_OTG_PIXEL_DATA_READBACK0
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG3_OTG_PIXEL_DATA_READBACK1
+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG3_OTG_STATUS
+#define OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG3_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG3_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG3_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG3_OTG_STATUS_POSITION
+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG3_OTG_NOM_VERT_POSITION
+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG3_OTG_STATUS_FRAME_COUNT
+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG3_OTG_STATUS_VF_COUNT
+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG3_OTG_STATUS_HV_COUNT
+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG3_OTG_COUNT_CONTROL
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG3_OTG_COUNT_RESET
+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG3_OTG_VERT_SYNC_CONTROL
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG3_OTG_STEREO_STATUS
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG3_OTG_STEREO_CONTROL
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG3_OTG_SNAPSHOT_STATUS
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG3_OTG_SNAPSHOT_CONTROL
+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG3_OTG_SNAPSHOT_POSITION
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG3_OTG_SNAPSHOT_FRAME
+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG3_OTG_INTERRUPT_CONTROL
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG3_OTG_UPDATE_LOCK
+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG3_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG3_OTG_MASTER_EN
+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG3_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L
+//OTG3_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG3_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG3_OTG_CRC_CNTL
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG3_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_DATA_RG
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC0_DATA_B
+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_DATA_RG
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC1_DATA_B
+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC2_DATA_RG
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC2_DATA_B
+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC3_DATA_RG
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC3_DATA_B
+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG3_OTG_STATIC_SCREEN_CONTROL
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG3_OTG_3D_STRUCTURE_CONTROL
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG3_OTG_GSL_VSYNC_GAP
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG3_OTG_MASTER_UPDATE_MODE
+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG3_OTG_CLOCK_CONTROL
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG3_OTG_VSTARTUP_PARAM
+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG3_OTG_VUPDATE_PARAM
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG3_OTG_VREADY_PARAM
+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG3_OTG_GLOBAL_SYNC_STATUS
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG3_OTG_MASTER_UPDATE_LOCK
+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG3_OTG_GSL_CONTROL
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG3_OTG_GSL_WINDOW_X
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG3_OTG_GSL_WINDOW_Y
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG3_OTG_VUPDATE_KEEPOUT
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL0
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL1
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL2
+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL3
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG3_OTG_GLOBAL_CONTROL4
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG3_OTG_TRIG_MANUAL_CONTROL
+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG3_OTG_MANUAL_FLOW_CONTROL
+#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG3_OTG_DRR_TIMING_INT_STATUS
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG3_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG3_OTG_DRR_V_TOTAL_CHANGE
+#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG3_OTG_DRR_TRIGGER_WINDOW
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG3_OTG_DRR_CONTROL
+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG3_OTG_M_CONST_DTO0
+#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG3_OTG_M_CONST_DTO1
+#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG3_OTG_REQUEST_CONTROL
+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG3_OTG_DSC_START_POSITION
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG3_OTG_PIPE_UPDATE_STATUS
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG3_OTG_SPARE_REGISTER
+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_optc_misc_dispdec
+//GSL_SOURCE_SELECT
+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT                                                       0x0
+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT                                                       0x4
+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT                                                       0x8
+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT                                                         0x10
+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK                                                         0x00000007L
+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK                                                         0x00000070L
+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK                                                         0x00000700L
+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK                                                           0x00070000L
+//OPTC_CLOCK_CONTROL
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT                                                    0x1
+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT                                                          0x8
+#define OPTC_CLOCK_CONTROL__OPTC_FGCG_REP_DIS__SHIFT                                                          0xf
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK                                                      0x00000002L
+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK                                                            0x00000F00L
+#define OPTC_CLOCK_CONTROL__OPTC_FGCG_REP_DIS_MASK                                                            0x00008000L
+//ODM_MEM_PWR_CTRL
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT                                                           0x0
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT                                                             0x2
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT                                                           0x4
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT                                                             0x6
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT                                                           0x8
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT                                                             0xa
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT                                                           0xc
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT                                                             0xe
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE__SHIFT                                                           0x10
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS__SHIFT                                                             0x12
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE__SHIFT                                                           0x14
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS__SHIFT                                                             0x16
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE__SHIFT                                                           0x18
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS__SHIFT                                                             0x1a
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE__SHIFT                                                           0x1c
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS__SHIFT                                                             0x1e
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK                                                             0x00000003L
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK                                                               0x00000004L
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK                                                             0x00000030L
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK                                                               0x00000040L
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK                                                             0x00000300L
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK                                                               0x00000400L
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK                                                             0x00003000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK                                                               0x00004000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE_MASK                                                             0x00030000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS_MASK                                                               0x00040000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE_MASK                                                             0x00300000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS_MASK                                                               0x00400000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE_MASK                                                             0x03000000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS_MASK                                                               0x04000000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE_MASK                                                             0x30000000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS_MASK                                                               0x40000000L
+//ODM_MEM_PWR_CTRL3
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT                                                 0x0
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT                                                     0x2
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK                                                   0x00000003L
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK                                                       0x0000000CL
+//ODM_MEM_PWR_STATUS
+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT                                                         0x0
+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT                                                         0x2
+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT                                                         0x4
+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT                                                         0x6
+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE__SHIFT                                                         0x8
+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE__SHIFT                                                         0xa
+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE__SHIFT                                                         0xc
+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE__SHIFT                                                         0xe
+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK                                                           0x00000003L
+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK                                                           0x0000000CL
+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK                                                           0x00000030L
+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK                                                           0x000000C0L
+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE_MASK                                                           0x00000300L
+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE_MASK                                                           0x00000C00L
+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE_MASK                                                           0x00003000L
+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE_MASK                                                           0x0000C000L
+//OPTC_MISC_SPARE_REGISTER
+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT                                                  0x0
+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK                                                    0x000000FFL
+
+
+// addressBlock: dce_dc_dio_hpd0_dispdec
+//HPD0_DC_HPD_INT_STATUS
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD0_DC_HPD_INT_CONTROL
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD0_DC_HPD_CONTROL
+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD0_DC_HPD_FAST_TRAIN_CNTL
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD0_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_hpd1_dispdec
+//HPD1_DC_HPD_INT_STATUS
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD1_DC_HPD_INT_CONTROL
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD1_DC_HPD_CONTROL
+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD1_DC_HPD_FAST_TRAIN_CNTL
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD1_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_hpd2_dispdec
+//HPD2_DC_HPD_INT_STATUS
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD2_DC_HPD_INT_CONTROL
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD2_DC_HPD_CONTROL
+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD2_DC_HPD_FAST_TRAIN_CNTL
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD2_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_hpd3_dispdec
+//HPD3_DC_HPD_INT_STATUS
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD3_DC_HPD_INT_CONTROL
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD3_DC_HPD_CONTROL
+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD3_DC_HPD_FAST_TRAIN_CNTL
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD3_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_hpd4_dispdec
+//HPD4_DC_HPD_INT_STATUS
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD4_DC_HPD_INT_CONTROL
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD4_DC_HPD_CONTROL
+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD4_DC_HPD_FAST_TRAIN_CNTL
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD4_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_dp0_dispdec
+//DP0_DP_LINK_CNTL
+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP0_DP_PIXEL_FORMAT
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L
+//DP0_DP_MSA_COLORIMETRY
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP0_DP_CONFIG
+#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP0_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP0_DP_VID_STREAM_CNTL
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP0_DP_STEER_FIFO
+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP0_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18
+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+#define DP0_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L
+//DP0_DP_MSA_MISC
+#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP0_DP_DPHY_INTERNAL_CTRL
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP0_DP_VID_TIMING
+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP0_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP0_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP0_DP_VID_N
+#define DP0_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP0_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP0_DP_VID_M
+#define DP0_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP0_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP0_DP_LINK_FRAMING_CNTL
+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP0_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP0_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP0_DP_HBR2_EYE_PATTERN
+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP0_DP_VID_MSA_VBID
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP0_DP_VID_INTERRUPT_CNTL
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP0_DP_DPHY_CNTL
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP0_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP0_DP_DPHY_SYM0
+#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP0_DP_DPHY_SYM1
+#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP0_DP_DPHY_SYM2
+#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP0_DP_DPHY_8B10B_CNTL
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP0_DP_DPHY_PRBS_CNTL
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP0_DP_DPHY_SCRAM_CNTL
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP0_DP_DPHY_CRC_EN
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP0_DP_DPHY_CRC_CNTL
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP0_DP_DPHY_CRC_RESULT
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP0_DP_DPHY_CRC_MST_CNTL
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP0_DP_DPHY_CRC_MST_STATUS
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP0_DP_DPHY_FAST_TRAINING
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP0_DP_DPHY_FAST_TRAINING_STATUS
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP0_DP_SEC_CNTL
+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP0_DP_SEC_CNTL1
+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_FRAMING1
+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP0_DP_SEC_FRAMING2
+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP0_DP_SEC_FRAMING3
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP0_DP_SEC_FRAMING4
+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP0_DP_SEC_AUD_N
+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP0_DP_SEC_AUD_N_READBACK
+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP0_DP_SEC_AUD_M
+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP0_DP_SEC_AUD_M_READBACK
+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP0_DP_SEC_TIMESTAMP
+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP0_DP_SEC_PACKET_CNTL
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP0_DP_MSE_RATE_CNTL
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP0_DP_MSE_RATE_UPDATE
+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP0_DP_MSE_SAT0
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP0_DP_MSE_SAT1
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP0_DP_MSE_SAT2
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP0_DP_MSE_SAT_UPDATE
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP0_DP_MSE_LINK_TIMING
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP0_DP_MSE_MISC_CNTL
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP0_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP0_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP0_DP_MSE_SAT0_STATUS
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP0_DP_MSE_SAT1_STATUS
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP0_DP_MSE_SAT2_STATUS
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP0_DP_DPIA_SPARE
+#define DP0_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0
+#define DP0_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L
+//DP0_DP_MSA_TIMING_PARAM1
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP0_DP_MSA_TIMING_PARAM2
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP0_DP_MSA_TIMING_PARAM3
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP0_DP_MSA_TIMING_PARAM4
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP0_DP_MSO_CNTL
+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP0_DP_MSO_CNTL1
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP0_DP_DSC_CNTL
+#define DP0_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP0_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L
+//DP0_DP_SEC_CNTL2
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP0_DP_SEC_CNTL3
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_CNTL4
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_CNTL5
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_CNTL6
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP0_DP_SEC_CNTL7
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP0_DP_DB_CNTL
+#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP0_DP_MSA_VBID_MISC
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP0_DP_SEC_METADATA_TRANSMISSION
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP0_DP_ALPM_CNTL
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP0_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP0_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP0_DP_GSP8_CNTL
+#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_GSP9_CNTL
+#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_GSP10_CNTL
+#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP0_DP_GSP11_CNTL
+#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP0_DP_GSP_EN_DB_STATUS
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+//DP0_DP_AUXLESS_ALPM_CNTL1
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L
+//DP0_DP_AUXLESS_ALPM_CNTL2
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT                                       0x8
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0xf
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT                                              0x10
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x16
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x17
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT                                              0x18
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK                                         0x00003F00L
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00008000L
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK                                                0x000F0000L
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00400000L
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00800000L
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK                                                0xFF000000L
+//DP0_DP_AUXLESS_ALPM_CNTL3
+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0
+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10
+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL
+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L
+//DP0_DP_AUXLESS_ALPM_CNTL4
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x0
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x8
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x9
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0xa
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0xb
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x0000007FL
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000100L
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000200L
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000400L
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000800L
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L
+//DP0_DP_AUXLESS_ALPM_CNTL5
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_dio_dig0_dispdec
+//DIG0_DIG_FE_CNTL
+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG0_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf
+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14
+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG0_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L
+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L
+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG0_DIG_OUTPUT_CRC_CNTL
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG0_DIG_OUTPUT_CRC_RESULT
+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG0_DIG_CLOCK_PATTERN
+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG0_DIG_TEST_PATTERN
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG0_DIG_RANDOM_PATTERN_SEED
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG0_DIG_FIFO_CTRL0
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L
+//DIG0_DIG_FIFO_CTRL1
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L
+//DIG0_HDMI_METADATA_PACKET_CONTROL
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG0_HDMI_CONTROL
+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG0_HDMI_STATUS
+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG0_HDMI_AUDIO_PACKET_CONTROL
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG0_HDMI_ACR_PACKET_CONTROL
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG0_HDMI_VBI_PACKET_CONTROL
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L
+//DIG0_HDMI_INFOFRAME_CONTROL0
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG0_HDMI_INFOFRAME_CONTROL1
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG0_HDMI_GC
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG0_HDMI_DB_CONTROL
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG0_HDMI_ACR_32_0
+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG0_HDMI_ACR_32_1
+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG0_HDMI_ACR_44_0
+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG0_HDMI_ACR_44_1
+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG0_HDMI_ACR_48_0
+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG0_HDMI_ACR_48_1
+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG0_HDMI_ACR_STATUS_0
+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG0_HDMI_ACR_STATUS_1
+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG0_AFMT_CNTL
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG0_DIG_BE_CNTL
+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG0_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG0_DIG_BE_EN_CNTL
+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG0_TMDS_CNTL
+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG0_TMDS_CONTROL_CHAR
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG0_TMDS_CONTROL0_FEEDBACK
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG0_TMDS_STEREOSYNC_CTL_SEL
+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG0_TMDS_CTL_BITS
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG0_TMDS_DCBALANCER_CONTROL
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG0_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG0_TMDS_CTL0_1_GEN_CNTL
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG0_TMDS_CTL2_3_GEN_CNTL
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG0_DIG_VERSION
+#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG0_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG0_FORCE_DIG_DISABLE
+#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp1_dispdec
+//DP1_DP_LINK_CNTL
+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP1_DP_PIXEL_FORMAT
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L
+//DP1_DP_MSA_COLORIMETRY
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP1_DP_CONFIG
+#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP1_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP1_DP_VID_STREAM_CNTL
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP1_DP_STEER_FIFO
+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP1_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18
+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+#define DP1_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L
+//DP1_DP_MSA_MISC
+#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP1_DP_DPHY_INTERNAL_CTRL
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP1_DP_VID_TIMING
+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP1_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP1_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP1_DP_VID_N
+#define DP1_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP1_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP1_DP_VID_M
+#define DP1_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP1_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP1_DP_LINK_FRAMING_CNTL
+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP1_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP1_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP1_DP_HBR2_EYE_PATTERN
+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP1_DP_VID_MSA_VBID
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP1_DP_VID_INTERRUPT_CNTL
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP1_DP_DPHY_CNTL
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP1_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP1_DP_DPHY_SYM0
+#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP1_DP_DPHY_SYM1
+#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP1_DP_DPHY_SYM2
+#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP1_DP_DPHY_8B10B_CNTL
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP1_DP_DPHY_PRBS_CNTL
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP1_DP_DPHY_SCRAM_CNTL
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP1_DP_DPHY_CRC_EN
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP1_DP_DPHY_CRC_CNTL
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP1_DP_DPHY_CRC_RESULT
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP1_DP_DPHY_CRC_MST_CNTL
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP1_DP_DPHY_CRC_MST_STATUS
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP1_DP_DPHY_FAST_TRAINING
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP1_DP_DPHY_FAST_TRAINING_STATUS
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP1_DP_SEC_CNTL
+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP1_DP_SEC_CNTL1
+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_FRAMING1
+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP1_DP_SEC_FRAMING2
+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP1_DP_SEC_FRAMING3
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP1_DP_SEC_FRAMING4
+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP1_DP_SEC_AUD_N
+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP1_DP_SEC_AUD_N_READBACK
+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP1_DP_SEC_AUD_M
+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP1_DP_SEC_AUD_M_READBACK
+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP1_DP_SEC_TIMESTAMP
+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP1_DP_SEC_PACKET_CNTL
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP1_DP_MSE_RATE_CNTL
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP1_DP_MSE_RATE_UPDATE
+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP1_DP_MSE_SAT0
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP1_DP_MSE_SAT1
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP1_DP_MSE_SAT2
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP1_DP_MSE_SAT_UPDATE
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP1_DP_MSE_LINK_TIMING
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP1_DP_MSE_MISC_CNTL
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP1_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP1_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP1_DP_MSE_SAT0_STATUS
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP1_DP_MSE_SAT1_STATUS
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP1_DP_MSE_SAT2_STATUS
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP1_DP_DPIA_SPARE
+#define DP1_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0
+#define DP1_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L
+//DP1_DP_MSA_TIMING_PARAM1
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP1_DP_MSA_TIMING_PARAM2
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP1_DP_MSA_TIMING_PARAM3
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP1_DP_MSA_TIMING_PARAM4
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP1_DP_MSO_CNTL
+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP1_DP_MSO_CNTL1
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP1_DP_DSC_CNTL
+#define DP1_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP1_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L
+//DP1_DP_SEC_CNTL2
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP1_DP_SEC_CNTL3
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_CNTL4
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_CNTL5
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_CNTL6
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP1_DP_SEC_CNTL7
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP1_DP_DB_CNTL
+#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP1_DP_MSA_VBID_MISC
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP1_DP_SEC_METADATA_TRANSMISSION
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP1_DP_ALPM_CNTL
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP1_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP1_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP1_DP_GSP8_CNTL
+#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_GSP9_CNTL
+#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_GSP10_CNTL
+#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP1_DP_GSP11_CNTL
+#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP1_DP_GSP_EN_DB_STATUS
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+//DP1_DP_AUXLESS_ALPM_CNTL1
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L
+//DP1_DP_AUXLESS_ALPM_CNTL2
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT                                       0x8
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0xf
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT                                              0x10
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x16
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x17
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT                                              0x18
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK                                         0x00003F00L
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00008000L
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK                                                0x000F0000L
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00400000L
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00800000L
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK                                                0xFF000000L
+//DP1_DP_AUXLESS_ALPM_CNTL3
+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0
+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10
+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL
+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L
+//DP1_DP_AUXLESS_ALPM_CNTL4
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x0
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x8
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x9
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0xa
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0xb
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x0000007FL
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000100L
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000200L
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000400L
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000800L
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L
+//DP1_DP_AUXLESS_ALPM_CNTL5
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_dio_dig1_dispdec
+//DIG1_DIG_FE_CNTL
+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG1_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf
+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14
+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG1_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L
+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L
+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG1_DIG_OUTPUT_CRC_CNTL
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG1_DIG_OUTPUT_CRC_RESULT
+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG1_DIG_CLOCK_PATTERN
+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG1_DIG_TEST_PATTERN
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG1_DIG_RANDOM_PATTERN_SEED
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG1_DIG_FIFO_CTRL0
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L
+//DIG1_DIG_FIFO_CTRL1
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L
+//DIG1_HDMI_METADATA_PACKET_CONTROL
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG1_HDMI_CONTROL
+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG1_HDMI_STATUS
+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG1_HDMI_AUDIO_PACKET_CONTROL
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG1_HDMI_ACR_PACKET_CONTROL
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG1_HDMI_VBI_PACKET_CONTROL
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L
+//DIG1_HDMI_INFOFRAME_CONTROL0
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG1_HDMI_INFOFRAME_CONTROL1
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG1_HDMI_GC
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG1_HDMI_DB_CONTROL
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG1_HDMI_ACR_32_0
+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG1_HDMI_ACR_32_1
+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG1_HDMI_ACR_44_0
+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG1_HDMI_ACR_44_1
+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG1_HDMI_ACR_48_0
+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG1_HDMI_ACR_48_1
+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG1_HDMI_ACR_STATUS_0
+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG1_HDMI_ACR_STATUS_1
+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG1_AFMT_CNTL
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG1_DIG_BE_CNTL
+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG1_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG1_DIG_BE_EN_CNTL
+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG1_TMDS_CNTL
+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG1_TMDS_CONTROL_CHAR
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG1_TMDS_CONTROL0_FEEDBACK
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG1_TMDS_STEREOSYNC_CTL_SEL
+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG1_TMDS_CTL_BITS
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG1_TMDS_DCBALANCER_CONTROL
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG1_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG1_TMDS_CTL0_1_GEN_CNTL
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG1_TMDS_CTL2_3_GEN_CNTL
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG1_DIG_VERSION
+#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG1_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG1_FORCE_DIG_DISABLE
+#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp2_dispdec
+//DP2_DP_LINK_CNTL
+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP2_DP_PIXEL_FORMAT
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L
+//DP2_DP_MSA_COLORIMETRY
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP2_DP_CONFIG
+#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP2_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP2_DP_VID_STREAM_CNTL
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP2_DP_STEER_FIFO
+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP2_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18
+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+#define DP2_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L
+//DP2_DP_MSA_MISC
+#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP2_DP_DPHY_INTERNAL_CTRL
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP2_DP_VID_TIMING
+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP2_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP2_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP2_DP_VID_N
+#define DP2_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP2_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP2_DP_VID_M
+#define DP2_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP2_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP2_DP_LINK_FRAMING_CNTL
+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP2_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP2_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP2_DP_HBR2_EYE_PATTERN
+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP2_DP_VID_MSA_VBID
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP2_DP_VID_INTERRUPT_CNTL
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP2_DP_DPHY_CNTL
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP2_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP2_DP_DPHY_SYM0
+#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP2_DP_DPHY_SYM1
+#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP2_DP_DPHY_SYM2
+#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP2_DP_DPHY_8B10B_CNTL
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP2_DP_DPHY_PRBS_CNTL
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP2_DP_DPHY_SCRAM_CNTL
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP2_DP_DPHY_CRC_EN
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP2_DP_DPHY_CRC_CNTL
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP2_DP_DPHY_CRC_RESULT
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP2_DP_DPHY_CRC_MST_CNTL
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP2_DP_DPHY_CRC_MST_STATUS
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP2_DP_DPHY_FAST_TRAINING
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP2_DP_DPHY_FAST_TRAINING_STATUS
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP2_DP_SEC_CNTL
+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP2_DP_SEC_CNTL1
+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_FRAMING1
+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP2_DP_SEC_FRAMING2
+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP2_DP_SEC_FRAMING3
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP2_DP_SEC_FRAMING4
+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP2_DP_SEC_AUD_N
+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP2_DP_SEC_AUD_N_READBACK
+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP2_DP_SEC_AUD_M
+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP2_DP_SEC_AUD_M_READBACK
+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP2_DP_SEC_TIMESTAMP
+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP2_DP_SEC_PACKET_CNTL
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP2_DP_MSE_RATE_CNTL
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP2_DP_MSE_RATE_UPDATE
+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP2_DP_MSE_SAT0
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP2_DP_MSE_SAT1
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP2_DP_MSE_SAT2
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP2_DP_MSE_SAT_UPDATE
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP2_DP_MSE_LINK_TIMING
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP2_DP_MSE_MISC_CNTL
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP2_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP2_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP2_DP_MSE_SAT0_STATUS
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP2_DP_MSE_SAT1_STATUS
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP2_DP_MSE_SAT2_STATUS
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP2_DP_DPIA_SPARE
+#define DP2_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0
+#define DP2_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L
+//DP2_DP_MSA_TIMING_PARAM1
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP2_DP_MSA_TIMING_PARAM2
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP2_DP_MSA_TIMING_PARAM3
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP2_DP_MSA_TIMING_PARAM4
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP2_DP_MSO_CNTL
+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP2_DP_MSO_CNTL1
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP2_DP_DSC_CNTL
+#define DP2_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP2_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L
+//DP2_DP_SEC_CNTL2
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP2_DP_SEC_CNTL3
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_CNTL4
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_CNTL5
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_CNTL6
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP2_DP_SEC_CNTL7
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP2_DP_DB_CNTL
+#define DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP2_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP2_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP2_DP_MSA_VBID_MISC
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP2_DP_SEC_METADATA_TRANSMISSION
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP2_DP_ALPM_CNTL
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP2_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP2_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP2_DP_GSP8_CNTL
+#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_GSP9_CNTL
+#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_GSP10_CNTL
+#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP2_DP_GSP11_CNTL
+#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP2_DP_GSP_EN_DB_STATUS
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+//DP2_DP_AUXLESS_ALPM_CNTL1
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L
+//DP2_DP_AUXLESS_ALPM_CNTL2
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT                                       0x8
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0xf
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT                                              0x10
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x16
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x17
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT                                              0x18
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK                                         0x00003F00L
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00008000L
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK                                                0x000F0000L
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00400000L
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00800000L
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK                                                0xFF000000L
+//DP2_DP_AUXLESS_ALPM_CNTL3
+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0
+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10
+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL
+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L
+//DP2_DP_AUXLESS_ALPM_CNTL4
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x0
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x8
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x9
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0xa
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0xb
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x0000007FL
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000100L
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000200L
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000400L
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000800L
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L
+//DP2_DP_AUXLESS_ALPM_CNTL5
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_dio_dig2_dispdec
+//DIG2_DIG_FE_CNTL
+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG2_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf
+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14
+#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG2_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L
+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L
+#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG2_DIG_OUTPUT_CRC_CNTL
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG2_DIG_OUTPUT_CRC_RESULT
+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG2_DIG_CLOCK_PATTERN
+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG2_DIG_TEST_PATTERN
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG2_DIG_RANDOM_PATTERN_SEED
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG2_DIG_FIFO_CTRL0
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L
+//DIG2_DIG_FIFO_CTRL1
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L
+//DIG2_HDMI_METADATA_PACKET_CONTROL
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG2_HDMI_CONTROL
+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG2_HDMI_STATUS
+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG2_HDMI_AUDIO_PACKET_CONTROL
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG2_HDMI_ACR_PACKET_CONTROL
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG2_HDMI_VBI_PACKET_CONTROL
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L
+//DIG2_HDMI_INFOFRAME_CONTROL0
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG2_HDMI_INFOFRAME_CONTROL1
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG2_HDMI_GC
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG2_HDMI_DB_CONTROL
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG2_HDMI_ACR_32_0
+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG2_HDMI_ACR_32_1
+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG2_HDMI_ACR_44_0
+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG2_HDMI_ACR_44_1
+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG2_HDMI_ACR_48_0
+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG2_HDMI_ACR_48_1
+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG2_HDMI_ACR_STATUS_0
+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG2_HDMI_ACR_STATUS_1
+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG2_AFMT_CNTL
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG2_DIG_BE_CNTL
+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG2_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG2_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG2_DIG_BE_EN_CNTL
+#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG2_TMDS_CNTL
+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG2_TMDS_CONTROL_CHAR
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG2_TMDS_CONTROL0_FEEDBACK
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG2_TMDS_STEREOSYNC_CTL_SEL
+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG2_TMDS_CTL_BITS
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG2_TMDS_DCBALANCER_CONTROL
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG2_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG2_TMDS_CTL0_1_GEN_CNTL
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG2_TMDS_CTL2_3_GEN_CNTL
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG2_DIG_VERSION
+#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG2_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG2_FORCE_DIG_DISABLE
+#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp3_dispdec
+//DP3_DP_LINK_CNTL
+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP3_DP_PIXEL_FORMAT
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L
+//DP3_DP_MSA_COLORIMETRY
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP3_DP_CONFIG
+#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP3_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP3_DP_VID_STREAM_CNTL
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP3_DP_STEER_FIFO
+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP3_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18
+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+#define DP3_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L
+//DP3_DP_MSA_MISC
+#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP3_DP_DPHY_INTERNAL_CTRL
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP3_DP_VID_TIMING
+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP3_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP3_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP3_DP_VID_N
+#define DP3_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP3_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP3_DP_VID_M
+#define DP3_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP3_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP3_DP_LINK_FRAMING_CNTL
+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP3_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP3_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP3_DP_HBR2_EYE_PATTERN
+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP3_DP_VID_MSA_VBID
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP3_DP_VID_INTERRUPT_CNTL
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP3_DP_DPHY_CNTL
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP3_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP3_DP_DPHY_SYM0
+#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP3_DP_DPHY_SYM1
+#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP3_DP_DPHY_SYM2
+#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP3_DP_DPHY_8B10B_CNTL
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP3_DP_DPHY_PRBS_CNTL
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP3_DP_DPHY_SCRAM_CNTL
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP3_DP_DPHY_CRC_EN
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP3_DP_DPHY_CRC_CNTL
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP3_DP_DPHY_CRC_RESULT
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP3_DP_DPHY_CRC_MST_CNTL
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP3_DP_DPHY_CRC_MST_STATUS
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP3_DP_DPHY_FAST_TRAINING
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP3_DP_DPHY_FAST_TRAINING_STATUS
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP3_DP_SEC_CNTL
+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP3_DP_SEC_CNTL1
+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_FRAMING1
+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP3_DP_SEC_FRAMING2
+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP3_DP_SEC_FRAMING3
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP3_DP_SEC_FRAMING4
+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP3_DP_SEC_AUD_N
+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP3_DP_SEC_AUD_N_READBACK
+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP3_DP_SEC_AUD_M
+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP3_DP_SEC_AUD_M_READBACK
+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP3_DP_SEC_TIMESTAMP
+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP3_DP_SEC_PACKET_CNTL
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP3_DP_MSE_RATE_CNTL
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP3_DP_MSE_RATE_UPDATE
+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP3_DP_MSE_SAT0
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP3_DP_MSE_SAT1
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP3_DP_MSE_SAT2
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP3_DP_MSE_SAT_UPDATE
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP3_DP_MSE_LINK_TIMING
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP3_DP_MSE_MISC_CNTL
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP3_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP3_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP3_DP_MSE_SAT0_STATUS
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP3_DP_MSE_SAT1_STATUS
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP3_DP_MSE_SAT2_STATUS
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP3_DP_DPIA_SPARE
+#define DP3_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0
+#define DP3_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L
+//DP3_DP_MSA_TIMING_PARAM1
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP3_DP_MSA_TIMING_PARAM2
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP3_DP_MSA_TIMING_PARAM3
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP3_DP_MSA_TIMING_PARAM4
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP3_DP_MSO_CNTL
+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP3_DP_MSO_CNTL1
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP3_DP_DSC_CNTL
+#define DP3_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP3_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L
+//DP3_DP_SEC_CNTL2
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP3_DP_SEC_CNTL3
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_CNTL4
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_CNTL5
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_CNTL6
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP3_DP_SEC_CNTL7
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP3_DP_DB_CNTL
+#define DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP3_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP3_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP3_DP_MSA_VBID_MISC
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP3_DP_SEC_METADATA_TRANSMISSION
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP3_DP_ALPM_CNTL
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP3_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP3_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP3_DP_GSP8_CNTL
+#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_GSP9_CNTL
+#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_GSP10_CNTL
+#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP3_DP_GSP11_CNTL
+#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP3_DP_GSP_EN_DB_STATUS
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+//DP3_DP_AUXLESS_ALPM_CNTL1
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L
+//DP3_DP_AUXLESS_ALPM_CNTL2
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT                                       0x8
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0xf
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT                                              0x10
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x16
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x17
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT                                              0x18
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK                                         0x00003F00L
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00008000L
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK                                                0x000F0000L
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00400000L
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00800000L
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK                                                0xFF000000L
+//DP3_DP_AUXLESS_ALPM_CNTL3
+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0
+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10
+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL
+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L
+//DP3_DP_AUXLESS_ALPM_CNTL4
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x0
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x8
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x9
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0xa
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0xb
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x0000007FL
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000100L
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000200L
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000400L
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000800L
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L
+//DP3_DP_AUXLESS_ALPM_CNTL5
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_dio_dig3_dispdec
+//DIG3_DIG_FE_CNTL
+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG3_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf
+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14
+#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG3_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L
+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L
+#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG3_DIG_OUTPUT_CRC_CNTL
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG3_DIG_OUTPUT_CRC_RESULT
+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG3_DIG_CLOCK_PATTERN
+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG3_DIG_TEST_PATTERN
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG3_DIG_RANDOM_PATTERN_SEED
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG3_DIG_FIFO_CTRL0
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L
+//DIG3_DIG_FIFO_CTRL1
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L
+//DIG3_HDMI_METADATA_PACKET_CONTROL
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG3_HDMI_CONTROL
+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG3_HDMI_STATUS
+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG3_HDMI_AUDIO_PACKET_CONTROL
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG3_HDMI_ACR_PACKET_CONTROL
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG3_HDMI_VBI_PACKET_CONTROL
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L
+//DIG3_HDMI_INFOFRAME_CONTROL0
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG3_HDMI_INFOFRAME_CONTROL1
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG3_HDMI_GC
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG3_HDMI_DB_CONTROL
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG3_HDMI_ACR_32_0
+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG3_HDMI_ACR_32_1
+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG3_HDMI_ACR_44_0
+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG3_HDMI_ACR_44_1
+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG3_HDMI_ACR_48_0
+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG3_HDMI_ACR_48_1
+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG3_HDMI_ACR_STATUS_0
+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG3_HDMI_ACR_STATUS_1
+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG3_AFMT_CNTL
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG3_DIG_BE_CNTL
+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG3_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG3_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG3_DIG_BE_EN_CNTL
+#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG3_TMDS_CNTL
+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG3_TMDS_CONTROL_CHAR
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG3_TMDS_CONTROL0_FEEDBACK
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG3_TMDS_STEREOSYNC_CTL_SEL
+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG3_TMDS_CTL_BITS
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG3_TMDS_DCBALANCER_CONTROL
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG3_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG3_TMDS_CTL0_1_GEN_CNTL
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG3_TMDS_CTL2_3_GEN_CNTL
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG3_DIG_VERSION
+#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG3_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG3_FORCE_DIG_DISABLE
+#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp4_dispdec
+//DP4_DP_LINK_CNTL
+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP4_DP_PIXEL_FORMAT
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L
+//DP4_DP_MSA_COLORIMETRY
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP4_DP_CONFIG
+#define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP4_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP4_DP_VID_STREAM_CNTL
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP4_DP_STEER_FIFO
+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP4_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18
+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+#define DP4_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L
+//DP4_DP_MSA_MISC
+#define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP4_DP_DPHY_INTERNAL_CTRL
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP4_DP_VID_TIMING
+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP4_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP4_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP4_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP4_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP4_DP_VID_N
+#define DP4_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP4_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP4_DP_VID_M
+#define DP4_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP4_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP4_DP_LINK_FRAMING_CNTL
+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP4_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP4_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP4_DP_HBR2_EYE_PATTERN
+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP4_DP_VID_MSA_VBID
+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP4_DP_VID_INTERRUPT_CNTL
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP4_DP_DPHY_CNTL
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP4_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP4_DP_DPHY_SYM0
+#define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP4_DP_DPHY_SYM1
+#define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP4_DP_DPHY_SYM2
+#define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP4_DP_DPHY_8B10B_CNTL
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP4_DP_DPHY_PRBS_CNTL
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP4_DP_DPHY_SCRAM_CNTL
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP4_DP_DPHY_CRC_EN
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP4_DP_DPHY_CRC_CNTL
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP4_DP_DPHY_CRC_RESULT
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP4_DP_DPHY_CRC_MST_CNTL
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP4_DP_DPHY_CRC_MST_STATUS
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP4_DP_DPHY_FAST_TRAINING
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP4_DP_DPHY_FAST_TRAINING_STATUS
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP4_DP_SEC_CNTL
+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP4_DP_SEC_CNTL1
+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_SEC_FRAMING1
+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP4_DP_SEC_FRAMING2
+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP4_DP_SEC_FRAMING3
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP4_DP_SEC_FRAMING4
+#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP4_DP_SEC_AUD_N
+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP4_DP_SEC_AUD_N_READBACK
+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP4_DP_SEC_AUD_M
+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP4_DP_SEC_AUD_M_READBACK
+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP4_DP_SEC_TIMESTAMP
+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP4_DP_SEC_PACKET_CNTL
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP4_DP_MSE_RATE_CNTL
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP4_DP_MSE_RATE_UPDATE
+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP4_DP_MSE_SAT0
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP4_DP_MSE_SAT1
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP4_DP_MSE_SAT2
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP4_DP_MSE_SAT_UPDATE
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP4_DP_MSE_LINK_TIMING
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP4_DP_MSE_MISC_CNTL
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP4_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP4_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP4_DP_MSE_SAT0_STATUS
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP4_DP_MSE_SAT1_STATUS
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP4_DP_MSE_SAT2_STATUS
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP4_DP_DPIA_SPARE
+#define DP4_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0
+#define DP4_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L
+//DP4_DP_MSA_TIMING_PARAM1
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP4_DP_MSA_TIMING_PARAM2
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP4_DP_MSA_TIMING_PARAM3
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP4_DP_MSA_TIMING_PARAM4
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP4_DP_MSO_CNTL
+#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP4_DP_MSO_CNTL1
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP4_DP_DSC_CNTL
+#define DP4_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP4_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L
+//DP4_DP_SEC_CNTL2
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP4_DP_SEC_CNTL3
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_SEC_CNTL4
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_SEC_CNTL5
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_SEC_CNTL6
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP4_DP_SEC_CNTL7
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP4_DP_DB_CNTL
+#define DP4_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP4_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP4_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP4_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP4_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP4_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP4_DP_MSA_VBID_MISC
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP4_DP_SEC_METADATA_TRANSMISSION
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP4_DP_ALPM_CNTL
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP4_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP4_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP4_DP_GSP8_CNTL
+#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_GSP9_CNTL
+#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_GSP10_CNTL
+#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP4_DP_GSP11_CNTL
+#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP4_DP_GSP_EN_DB_STATUS
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+//DP4_DP_AUXLESS_ALPM_CNTL1
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L
+//DP4_DP_AUXLESS_ALPM_CNTL2
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT                                       0x8
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0xf
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT                                              0x10
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x16
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x17
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT                                              0x18
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK                                         0x00003F00L
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00008000L
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK                                                0x000F0000L
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00400000L
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00800000L
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK                                                0xFF000000L
+//DP4_DP_AUXLESS_ALPM_CNTL3
+#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0
+#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10
+#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL
+#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L
+//DP4_DP_AUXLESS_ALPM_CNTL4
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x0
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x8
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x9
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0xa
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0xb
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x0000007FL
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000100L
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000200L
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000400L
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000800L
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L
+//DP4_DP_AUXLESS_ALPM_CNTL5
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_dio_dig4_dispdec
+//DIG4_DIG_FE_CNTL
+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG4_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf
+#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14
+#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG4_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L
+#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L
+#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG4_DIG_OUTPUT_CRC_CNTL
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG4_DIG_OUTPUT_CRC_RESULT
+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG4_DIG_CLOCK_PATTERN
+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG4_DIG_TEST_PATTERN
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG4_DIG_RANDOM_PATTERN_SEED
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG4_DIG_FIFO_CTRL0
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L
+//DIG4_DIG_FIFO_CTRL1
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L
+//DIG4_HDMI_METADATA_PACKET_CONTROL
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG4_HDMI_CONTROL
+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG4_HDMI_STATUS
+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG4_HDMI_AUDIO_PACKET_CONTROL
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG4_HDMI_ACR_PACKET_CONTROL
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG4_HDMI_VBI_PACKET_CONTROL
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L
+//DIG4_HDMI_INFOFRAME_CONTROL0
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG4_HDMI_INFOFRAME_CONTROL1
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG4_HDMI_GC
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG4_HDMI_DB_CONTROL
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG4_HDMI_ACR_32_0
+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG4_HDMI_ACR_32_1
+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG4_HDMI_ACR_44_0
+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG4_HDMI_ACR_44_1
+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG4_HDMI_ACR_48_0
+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG4_HDMI_ACR_48_1
+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG4_HDMI_ACR_STATUS_0
+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG4_HDMI_ACR_STATUS_1
+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG4_AFMT_CNTL
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG4_DIG_BE_CNTL
+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG4_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG4_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG4_DIG_BE_EN_CNTL
+#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG4_TMDS_CNTL
+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG4_TMDS_CONTROL_CHAR
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG4_TMDS_CONTROL0_FEEDBACK
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG4_TMDS_STEREOSYNC_CTL_SEL
+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG4_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG4_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG4_TMDS_CTL_BITS
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG4_TMDS_DCBALANCER_CONTROL
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG4_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG4_TMDS_CTL0_1_GEN_CNTL
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG4_TMDS_CTL2_3_GEN_CNTL
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG4_DIG_VERSION
+#define DIG4_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG4_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG4_FORCE_DIG_DISABLE
+#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec
+//AFMT0_AFMT_VBI_PACKET_CONTROL
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT0_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT0_AFMT_AUDIO_INFO0
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT0_AFMT_AUDIO_INFO1
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT0_AFMT_60958_0
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT0_AFMT_60958_1
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT0_AFMT_AUDIO_CRC_CONTROL
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT0_AFMT_RAMP_CONTROL0
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT0_AFMT_RAMP_CONTROL1
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT0_AFMT_RAMP_CONTROL2
+#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT0_AFMT_RAMP_CONTROL3
+#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT0_AFMT_60958_2
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT0_AFMT_AUDIO_CRC_RESULT
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT0_AFMT_STATUS
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT0_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L
+//AFMT0_AFMT_INFOFRAME_CONTROL0
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT0_AFMT_INTERRUPT_STATUS
+//AFMT0_AFMT_AUDIO_SRC_CONTROL
+#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT0_AFMT_MEM_PWR
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec
+//AFMT1_AFMT_VBI_PACKET_CONTROL
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT1_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT1_AFMT_AUDIO_INFO0
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT1_AFMT_AUDIO_INFO1
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT1_AFMT_60958_0
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT1_AFMT_60958_1
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT1_AFMT_AUDIO_CRC_CONTROL
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT1_AFMT_RAMP_CONTROL0
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT1_AFMT_RAMP_CONTROL1
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT1_AFMT_RAMP_CONTROL2
+#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT1_AFMT_RAMP_CONTROL3
+#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT1_AFMT_60958_2
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT1_AFMT_AUDIO_CRC_RESULT
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT1_AFMT_STATUS
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT1_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L
+//AFMT1_AFMT_INFOFRAME_CONTROL0
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT1_AFMT_INTERRUPT_STATUS
+//AFMT1_AFMT_AUDIO_SRC_CONTROL
+#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT1_AFMT_MEM_PWR
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec
+//AFMT2_AFMT_VBI_PACKET_CONTROL
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT2_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT2_AFMT_AUDIO_INFO0
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT2_AFMT_AUDIO_INFO1
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT2_AFMT_60958_0
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT2_AFMT_60958_1
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT2_AFMT_AUDIO_CRC_CONTROL
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT2_AFMT_RAMP_CONTROL0
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT2_AFMT_RAMP_CONTROL1
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT2_AFMT_RAMP_CONTROL2
+#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT2_AFMT_RAMP_CONTROL3
+#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT2_AFMT_60958_2
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT2_AFMT_AUDIO_CRC_RESULT
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT2_AFMT_STATUS
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT2_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L
+//AFMT2_AFMT_INFOFRAME_CONTROL0
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT2_AFMT_INTERRUPT_STATUS
+//AFMT2_AFMT_AUDIO_SRC_CONTROL
+#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT2_AFMT_MEM_PWR
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec
+//AFMT3_AFMT_VBI_PACKET_CONTROL
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT3_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT3_AFMT_AUDIO_INFO0
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT3_AFMT_AUDIO_INFO1
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT3_AFMT_60958_0
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT3_AFMT_60958_1
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT3_AFMT_AUDIO_CRC_CONTROL
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT3_AFMT_RAMP_CONTROL0
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT3_AFMT_RAMP_CONTROL1
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT3_AFMT_RAMP_CONTROL2
+#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT3_AFMT_RAMP_CONTROL3
+#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT3_AFMT_60958_2
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT3_AFMT_AUDIO_CRC_RESULT
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT3_AFMT_STATUS
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT3_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L
+//AFMT3_AFMT_INFOFRAME_CONTROL0
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT3_AFMT_INTERRUPT_STATUS
+//AFMT3_AFMT_AUDIO_SRC_CONTROL
+#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT3_AFMT_MEM_PWR
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec
+//AFMT4_AFMT_VBI_PACKET_CONTROL
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT4_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT4_AFMT_AUDIO_INFO0
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT4_AFMT_AUDIO_INFO1
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT4_AFMT_60958_0
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT4_AFMT_60958_1
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT4_AFMT_AUDIO_CRC_CONTROL
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT4_AFMT_RAMP_CONTROL0
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT4_AFMT_RAMP_CONTROL1
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT4_AFMT_RAMP_CONTROL2
+#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT4_AFMT_RAMP_CONTROL3
+#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT4_AFMT_60958_2
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT4_AFMT_AUDIO_CRC_RESULT
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT4_AFMT_STATUS
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT4_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L
+//AFMT4_AFMT_INFOFRAME_CONTROL0
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT4_AFMT_INTERRUPT_STATUS
+//AFMT4_AFMT_AUDIO_SRC_CONTROL
+#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT4_AFMT_MEM_PWR
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec
+//DME0_DME_CONTROL
+#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME0_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME0_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME0_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME0_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME0_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME0_DME_MEMORY_CONTROL
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec
+//VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG0_VPG_GENERIC_PACKET_DATA
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG0_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG0_VPG_GENERIC_STATUS
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG0_VPG_MEM_PWR
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG0_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG0_VPG_ISRC1_2_DATA
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG0_VPG_MPEG_INFO0
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG0_VPG_MPEG_INFO1
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec
+//DME1_DME_CONTROL
+#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME1_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME1_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME1_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME1_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME1_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME1_DME_MEMORY_CONTROL
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec
+//VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG1_VPG_GENERIC_PACKET_DATA
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG1_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG1_VPG_GENERIC_STATUS
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG1_VPG_MEM_PWR
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG1_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG1_VPG_ISRC1_2_DATA
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG1_VPG_MPEG_INFO0
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG1_VPG_MPEG_INFO1
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec
+//DME2_DME_CONTROL
+#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME2_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME2_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME2_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME2_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME2_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME2_DME_MEMORY_CONTROL
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec
+//VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG2_VPG_GENERIC_PACKET_DATA
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG2_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG2_VPG_GENERIC_STATUS
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG2_VPG_MEM_PWR
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG2_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG2_VPG_ISRC1_2_DATA
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG2_VPG_MPEG_INFO0
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG2_VPG_MPEG_INFO1
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec
+//DME3_DME_CONTROL
+#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME3_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME3_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME3_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME3_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME3_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME3_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME3_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME3_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME3_DME_MEMORY_CONTROL
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec
+//VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG3_VPG_GENERIC_PACKET_DATA
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG3_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG3_VPG_GENERIC_STATUS
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG3_VPG_MEM_PWR
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG3_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG3_VPG_ISRC1_2_DATA
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG3_VPG_MPEG_INFO0
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG3_VPG_MPEG_INFO1
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec
+//DME4_DME_CONTROL
+#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME4_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME4_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME4_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME4_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME4_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME4_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME4_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME4_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME4_DME_MEMORY_CONTROL
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec
+//VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG4_VPG_GENERIC_PACKET_DATA
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG4_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG4_VPG_GENERIC_STATUS
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG4_VPG_MEM_PWR
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG4_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG4_VPG_ISRC1_2_DATA
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG4_VPG_MPEG_INFO0
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG4_VPG_MPEG_INFO1
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_dio_dp_aux0_dispdec
+//DP_AUX0_AUX_CONTROL
+#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX0_AUX_SW_CONTROL
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX0_AUX_ARB_CONTROL
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX0_AUX_INTERRUPT_CONTROL
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX0_AUX_SW_STATUS
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX0_AUX_LS_STATUS
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX0_AUX_SW_DATA
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX0_AUX_LS_DATA
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX0_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX0_AUX_DPHY_TX_CONTROL
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX0_AUX_DPHY_RX_CONTROL0
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX0_AUX_DPHY_RX_CONTROL1
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX0_AUX_DPHY_TX_STATUS
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX0_AUX_DPHY_RX_STATUS
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX0_AUX_GTC_SYNC_CONTROL
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX0_AUX_GTC_SYNC_STATUS
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX0_AUX_PHY_WAKE_CNTL
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dce_dc_dio_dp_aux1_dispdec
+//DP_AUX1_AUX_CONTROL
+#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX1_AUX_SW_CONTROL
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX1_AUX_ARB_CONTROL
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX1_AUX_INTERRUPT_CONTROL
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX1_AUX_SW_STATUS
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX1_AUX_LS_STATUS
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX1_AUX_SW_DATA
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX1_AUX_LS_DATA
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX1_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX1_AUX_DPHY_TX_CONTROL
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX1_AUX_DPHY_RX_CONTROL0
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX1_AUX_DPHY_RX_CONTROL1
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX1_AUX_DPHY_TX_STATUS
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX1_AUX_DPHY_RX_STATUS
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX1_AUX_GTC_SYNC_CONTROL
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX1_AUX_GTC_SYNC_STATUS
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX1_AUX_PHY_WAKE_CNTL
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dce_dc_dio_dp_aux2_dispdec
+//DP_AUX2_AUX_CONTROL
+#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX2_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX2_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX2_AUX_SW_CONTROL
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX2_AUX_ARB_CONTROL
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX2_AUX_INTERRUPT_CONTROL
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX2_AUX_SW_STATUS
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX2_AUX_LS_STATUS
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX2_AUX_SW_DATA
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX2_AUX_LS_DATA
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX2_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX2_AUX_DPHY_TX_CONTROL
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX2_AUX_DPHY_RX_CONTROL0
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX2_AUX_DPHY_RX_CONTROL1
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX2_AUX_DPHY_TX_STATUS
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX2_AUX_DPHY_RX_STATUS
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX2_AUX_GTC_SYNC_CONTROL
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX2_AUX_GTC_SYNC_STATUS
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX2_AUX_PHY_WAKE_CNTL
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dce_dc_dio_dp_aux3_dispdec
+//DP_AUX3_AUX_CONTROL
+#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX3_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX3_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX3_AUX_SW_CONTROL
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX3_AUX_ARB_CONTROL
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX3_AUX_INTERRUPT_CONTROL
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX3_AUX_SW_STATUS
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX3_AUX_LS_STATUS
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX3_AUX_SW_DATA
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX3_AUX_LS_DATA
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX3_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX3_AUX_DPHY_TX_CONTROL
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX3_AUX_DPHY_RX_CONTROL0
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX3_AUX_DPHY_RX_CONTROL1
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX3_AUX_DPHY_TX_STATUS
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX3_AUX_DPHY_RX_STATUS
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX3_AUX_GTC_SYNC_CONTROL
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX3_AUX_GTC_SYNC_STATUS
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX3_AUX_PHY_WAKE_CNTL
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dce_dc_dio_dp_aux4_dispdec
+//DP_AUX4_AUX_CONTROL
+#define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX4_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX4_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX4_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX4_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX4_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX4_AUX_SW_CONTROL
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX4_AUX_ARB_CONTROL
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX4_AUX_INTERRUPT_CONTROL
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX4_AUX_SW_STATUS
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX4_AUX_LS_STATUS
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX4_AUX_SW_DATA
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX4_AUX_LS_DATA
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX4_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX4_AUX_DPHY_TX_CONTROL
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX4_AUX_DPHY_RX_CONTROL0
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX4_AUX_DPHY_RX_CONTROL1
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX4_AUX_DPHY_TX_STATUS
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX4_AUX_DPHY_RX_STATUS
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX4_AUX_GTC_SYNC_CONTROL
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX4_AUX_GTC_SYNC_STATUS
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX4_AUX_PHY_WAKE_CNTL
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dce_dc_dio_dout_i2c_dispdec
+//DC_I2C_CONTROL
+#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT                                                                      0x0
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT                                                              0x1
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT                                                              0x2
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT                                                         0x3
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT                                                              0x8
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT                                                       0x14
+#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT                                                             0x1f
+#define DC_I2C_CONTROL__DC_I2C_GO_MASK                                                                        0x00000001L
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK                                                                0x00000002L
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK                                                                0x00000004L
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK                                                           0x00000008L
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK                                                                0x00000700L
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK                                                         0x00300000L
+#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK                                                               0x80000000L
+//DC_I2C_ARBITRATION
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT                                                         0x0
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT                                                  0x2
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT                                                     0x4
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT                                                       0x8
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT                                                       0xc
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT                                                  0x14
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT                                               0x15
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT                                                0x18
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT                                             0x19
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK                                                           0x00000003L
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK                                                    0x0000000CL
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK                                                       0x00000010L
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK                                                         0x00000100L
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK                                                         0x00001000L
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK                                                    0x00100000L
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK                                                 0x00200000L
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK                                                  0x01000000L
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK                                               0x02000000L
+//DC_I2C_INTERRUPT_CONTROL
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT                                                   0x0
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT                                                   0x1
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT                                                  0x2
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT                                              0x4
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT                                              0x5
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT                                             0x6
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT                                              0x8
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT                                              0x9
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT                                             0xa
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT                                              0xc
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT                                              0xd
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT                                             0xe
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT                                              0x10
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT                                              0x11
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT                                             0x12
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT                                              0x14
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT                                              0x15
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT                                             0x16
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT                                              0x18
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT                                              0x19
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT                                             0x1a
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT                                            0x1b
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT                                            0x1c
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT                                           0x1d
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK                                                     0x00000001L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK                                                     0x00000002L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK                                                    0x00000004L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK                                                0x00000010L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK                                                0x00000020L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK                                               0x00000040L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK                                                0x00000100L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK                                                0x00000200L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK                                               0x00000400L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK                                                0x00001000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK                                                0x00002000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK                                               0x00004000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK                                                0x00010000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK                                                0x00020000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK                                               0x00040000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK                                                0x00100000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK                                                0x00200000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK                                               0x00400000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK                                                0x01000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK                                                0x02000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK                                               0x04000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK                                              0x08000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK                                              0x10000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK                                             0x20000000L
+//DC_I2C_SW_STATUS
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT                                                             0x0
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT                                                               0x2
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT                                                            0x4
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT                                                            0x5
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT                                                        0x6
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT                                                    0x7
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT                                                    0x8
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT                                                              0xc
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT                                                              0xd
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT                                                              0xe
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT                                                              0xf
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT                                                                0x12
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK                                                               0x00000003L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK                                                                 0x00000004L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK                                                              0x00000010L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK                                                              0x00000020L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK                                                          0x00000040L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK                                                      0x00000080L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK                                                      0x00000100L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK                                                                0x00001000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK                                                                0x00002000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK                                                                0x00004000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK                                                                0x00008000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK                                                                  0x00040000L
+//DC_I2C_DDC1_HW_STATUS
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC2_HW_STATUS
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC3_HW_STATUS
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC4_HW_STATUS
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC5_HW_STATUS
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC1_SPEED
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC1_SETUP
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC2_SPEED
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC2_SETUP
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC3_SPEED
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC3_SETUP
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC4_SPEED
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC4_SETUP
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC5_SPEED
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC5_SETUP
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_TRANSACTION0
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK                                                               0x03FF0000L
+//DC_I2C_TRANSACTION1
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK                                                               0x03FF0000L
+//DC_I2C_TRANSACTION2
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK                                                               0x03FF0000L
+//DC_I2C_TRANSACTION3
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK                                                               0x03FF0000L
+//DC_I2C_DATA
+#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT                                                                    0x0
+#define DC_I2C_DATA__DC_I2C_DATA__SHIFT                                                                       0x8
+#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT                                                                      0x10
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT                                                                0x1f
+#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK                                                                      0x00000001L
+#define DC_I2C_DATA__DC_I2C_DATA_MASK                                                                         0x0000FF00L
+#define DC_I2C_DATA__DC_I2C_INDEX_MASK                                                                        0x03FF0000L
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK                                                                  0x80000000L
+//DC_I2C_EDID_DETECT_CTRL
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT                                          0x0
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT                              0x14
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT                                         0x1c
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK                                            0x0000FFFFL
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK                                0x00F00000L
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK                                           0x10000000L
+//DC_I2C_READ_REQUEST_INTERRUPT
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT                               0x0
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT                                    0x1
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT                                    0x2
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT                                   0x3
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT                               0x4
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT                                    0x5
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT                                    0x6
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT                                   0x7
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT                               0x8
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT                                    0x9
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT                                    0xa
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT                                   0xb
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT                               0xc
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT                                    0xd
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT                                    0xe
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT                                   0xf
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT                               0x10
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT                                    0x11
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT                                    0x12
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT                                   0x13
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT                               0x14
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT                                    0x15
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT                                    0x16
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT                                   0x17
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT                             0x18
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT                                  0x19
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT                                  0x1a
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT                                 0x1b
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT                              0x1e
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT                                0x1f
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK                                 0x00000001L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK                                      0x00000002L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK                                      0x00000004L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK                                     0x00000008L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK                                 0x00000010L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK                                      0x00000020L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK                                      0x00000040L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK                                     0x00000080L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK                                 0x00000100L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK                                      0x00000200L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK                                      0x00000400L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK                                     0x00000800L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK                                 0x00001000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK                                      0x00002000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK                                      0x00004000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK                                     0x00008000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK                                 0x00010000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK                                      0x00020000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK                                      0x00040000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK                                     0x00080000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK                                 0x00100000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK                                      0x00200000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK                                      0x00400000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK                                     0x00800000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK                               0x01000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK                                    0x02000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK                                    0x04000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK                                   0x08000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK                                0x40000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK                                  0x80000000L
+
+
+// addressBlock: dce_dc_dio_dio_misc_dispdec
+//DIO_SCRATCH0
+#define DIO_SCRATCH0__DIO_SCRATCH0__SHIFT                                                                     0x0
+#define DIO_SCRATCH0__DIO_SCRATCH0_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH1
+#define DIO_SCRATCH1__DIO_SCRATCH1__SHIFT                                                                     0x0
+#define DIO_SCRATCH1__DIO_SCRATCH1_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH2
+#define DIO_SCRATCH2__DIO_SCRATCH2__SHIFT                                                                     0x0
+#define DIO_SCRATCH2__DIO_SCRATCH2_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH3
+#define DIO_SCRATCH3__DIO_SCRATCH3__SHIFT                                                                     0x0
+#define DIO_SCRATCH3__DIO_SCRATCH3_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH4
+#define DIO_SCRATCH4__DIO_SCRATCH4__SHIFT                                                                     0x0
+#define DIO_SCRATCH4__DIO_SCRATCH4_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH5
+#define DIO_SCRATCH5__DIO_SCRATCH5__SHIFT                                                                     0x0
+#define DIO_SCRATCH5__DIO_SCRATCH5_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH6
+#define DIO_SCRATCH6__DIO_SCRATCH6__SHIFT                                                                     0x0
+#define DIO_SCRATCH6__DIO_SCRATCH6_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH7
+#define DIO_SCRATCH7__DIO_SCRATCH7__SHIFT                                                                     0x0
+#define DIO_SCRATCH7__DIO_SCRATCH7_MASK                                                                       0xFFFFFFFFL
+//DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGA_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x0
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGB_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x1
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGC_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x2
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGD_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x3
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGE_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x4
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGF_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x5
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGG_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x6
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGA_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000001L
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGB_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000002L
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGC_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000004L
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGD_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000008L
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGE_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000010L
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGF_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000020L
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGG_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000040L
+//DIO_MEM_PWR_STATUS
+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT                                                          0x0
+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT                                                          0x3
+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT                                                          0x4
+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT                                                          0x5
+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT                                                          0x6
+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT                                                          0x7
+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT                                                          0x8
+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT                                                          0x9
+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK                                                            0x00000001L
+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK                                                            0x00000008L
+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK                                                            0x00000010L
+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK                                                            0x00000020L
+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK                                                            0x00000040L
+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK                                                            0x00000080L
+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK                                                            0x00000100L
+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK                                                            0x00000200L
+//DIO_MEM_PWR_CTRL
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT                                                        0x0
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT                                                          0x1
+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT                                                          0x4
+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT                                                          0x5
+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT                                                          0x6
+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT                                                          0x7
+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT                                                          0x8
+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT                                                          0x9
+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT                                                          0xa
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK                                                          0x00000001L
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK                                                            0x00000002L
+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK                                                            0x00000010L
+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK                                                            0x00000020L
+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK                                                            0x00000040L
+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK                                                            0x00000080L
+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK                                                            0x00000100L
+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK                                                            0x00000200L
+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK                                                            0x00000400L
+//DIO_MEM_PWR_CTRL2
+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE__SHIFT                                                       0x18
+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE__SHIFT                                                       0x19
+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1a
+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1b
+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1c
+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1d
+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1e
+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE_MASK                                                         0x01000000L
+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE_MASK                                                         0x02000000L
+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE_MASK                                                         0x04000000L
+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE_MASK                                                         0x08000000L
+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE_MASK                                                         0x10000000L
+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE_MASK                                                         0x20000000L
+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE_MASK                                                         0x40000000L
+//DIO_CLK_CNTL
+#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS__SHIFT                                                           0x5
+#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS__SHIFT                                                            0xa
+#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT                                                          0x18
+#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT                                                          0x19
+#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT                                                          0x1a
+#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT                                                          0x1b
+#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT                                                          0x1c
+#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT                                                          0x1d
+#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT                                                          0x1e
+#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS_MASK                                                             0x00000020L
+#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS_MASK                                                              0x00000400L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK                                                            0x01000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK                                                            0x02000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK                                                            0x04000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK                                                            0x08000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK                                                            0x10000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK                                                            0x20000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK                                                            0x40000000L
+//DIO_POWER_MANAGEMENT_CNTL
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT                                                     0x0
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT                                                     0x8
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK                                                       0x00000001L
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK                                                       0x00000100L
+//DIG_SOFT_RESET
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT                                                             0x0
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT                                                             0x1
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT                                                             0x4
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT                                                             0x5
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT                                                             0x8
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT                                                             0x9
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT                                                             0xc
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT                                                             0xd
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT                                                             0x10
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT                                                             0x11
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT                                                             0x14
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT                                                             0x15
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT                                                             0x18
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT                                                             0x19
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK                                                               0x00000001L
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK                                                               0x00000002L
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK                                                               0x00000010L
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK                                                               0x00000020L
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK                                                               0x00000100L
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK                                                               0x00000200L
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK                                                               0x00001000L
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK                                                               0x00002000L
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK                                                               0x00010000L
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK                                                               0x00020000L
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK                                                               0x00100000L
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK                                                               0x00200000L
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK                                                               0x01000000L
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK                                                               0x02000000L
+//DIO_CLK_CNTL2
+#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL__SHIFT                                                                0x0
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS__SHIFT                                                         0x7
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS__SHIFT                                                         0x8
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS__SHIFT                                                         0x9
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS__SHIFT                                                         0xa
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS__SHIFT                                                         0xb
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS__SHIFT                                                         0xc
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS__SHIFT                                                         0xd
+#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x11
+#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x12
+#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x13
+#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x14
+#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x15
+#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x16
+#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x17
+#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS__SHIFT                                                           0x18
+#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS__SHIFT                                                           0x19
+#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS__SHIFT                                                           0x1a
+#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS__SHIFT                                                           0x1b
+#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS__SHIFT                                                           0x1c
+#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS__SHIFT                                                           0x1d
+#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS__SHIFT                                                           0x1e
+#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL_MASK                                                                  0x0000007FL
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS_MASK                                                           0x00000080L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS_MASK                                                           0x00000100L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS_MASK                                                           0x00000200L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS_MASK                                                           0x00000400L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS_MASK                                                           0x00000800L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS_MASK                                                           0x00001000L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS_MASK                                                           0x00002000L
+#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK                                                        0x00020000L
+#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK                                                        0x00040000L
+#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK                                                        0x00080000L
+#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK                                                        0x00100000L
+#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK                                                        0x00200000L
+#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK                                                        0x00400000L
+#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK                                                        0x00800000L
+#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS_MASK                                                             0x01000000L
+#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS_MASK                                                             0x02000000L
+#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS_MASK                                                             0x04000000L
+#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS_MASK                                                             0x08000000L
+#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS_MASK                                                             0x10000000L
+#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS_MASK                                                             0x20000000L
+#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS_MASK                                                             0x40000000L
+//DIO_CLK_CNTL3
+#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x0
+#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x1
+#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x2
+#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x3
+#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x4
+#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x5
+#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x6
+#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT                                                         0xa
+#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT                                                         0xb
+#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT                                                         0xc
+#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT                                                         0xd
+#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT                                                         0xe
+#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT                                                         0xf
+#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT                                                         0x10
+#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000001L
+#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000002L
+#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000004L
+#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000008L
+#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000010L
+#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000020L
+#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000040L
+#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK                                                           0x00000400L
+#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK                                                           0x00000800L
+#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK                                                           0x00001000L
+#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK                                                           0x00002000L
+#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK                                                           0x00004000L
+#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK                                                           0x00008000L
+#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK                                                           0x00010000L
+//DIO_HDMI_RXSTATUS_TIMER_CONTROL
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT                                0x0
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT                                  0x4
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT                                0x8
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT                                  0xc
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT                              0x10
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK                                  0x00000001L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK                                    0x00000010L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK                                  0x00000100L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK                                    0x00001000L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK                                0x0FFF0000L
+//DIO_LINKA_CNTL
+#define DIO_LINKA_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKA_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKA_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKA_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKA_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKA_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKB_CNTL
+#define DIO_LINKB_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKB_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKB_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKB_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKB_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKB_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKC_CNTL
+#define DIO_LINKC_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKC_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKC_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKC_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKC_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKC_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKD_CNTL
+#define DIO_LINKD_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKD_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKD_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKD_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKD_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKD_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKE_CNTL
+#define DIO_LINKE_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKE_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKE_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKE_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKE_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKE_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKF_CNTL
+#define DIO_LINKF_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKF_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKF_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKF_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKF_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKF_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+
+
+// addressBlock: dce_dc_dcio_dcio_dispdec
+//DC_GENERICA
+#define DC_GENERICA__GENERICA_EN__SHIFT                                                                       0x0
+#define DC_GENERICA__GENERICA_SEL__SHIFT                                                                      0x7
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
+#define DC_GENERICA__GENERICA_EN_MASK                                                                         0x00000001L
+#define DC_GENERICA__GENERICA_SEL_MASK                                                                        0x00000F80L
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
+//DC_GENERICB
+#define DC_GENERICB__GENERICB_EN__SHIFT                                                                       0x0
+#define DC_GENERICB__GENERICB_SEL__SHIFT                                                                      0x8
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
+#define DC_GENERICB__GENERICB_EN_MASK                                                                         0x00000001L
+#define DC_GENERICB__GENERICB_SEL_MASK                                                                        0x00000F00L
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
+//DCIO_CLOCK_CNTL
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT                                                             0x0
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT                                                       0x5
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK                                                               0x0000001FL
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK                                                         0x00000020L
+//DC_REF_CLK_CNTL
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT                                                             0x0
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT                                                          0x8
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK                                                               0x00000003L
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK                                                            0x00000300L
+//UNIPHYA_LINK_CNTL
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+//UNIPHYA_CHANNEL_XBAR_CNTL
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYB_LINK_CNTL
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+//UNIPHYB_CHANNEL_XBAR_CNTL
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYC_LINK_CNTL
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+//UNIPHYC_CHANNEL_XBAR_CNTL
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYD_LINK_CNTL
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+//UNIPHYD_CHANNEL_XBAR_CNTL
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYE_LINK_CNTL
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+//UNIPHYE_CHANNEL_XBAR_CNTL
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//DCIO_WRCMD_DELAY
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT                                                                 0x18
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK                                                                   0xFF000000L
+//DC_PINSTRAPS
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT                                                         0xd
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT                                                               0xe
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT                                                            0x10
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT                                                        0x11
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK                                                           0x00002000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK                                                                 0x0000C000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK                                                              0x00010000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK                                                          0x000E0000L
+//DCIO_SPARE
+#define DCIO_SPARE__DCIO_SPARE__SHIFT                                                                         0x0
+#define DCIO_SPARE__DCIO_SPARE_MASK                                                                           0xFFFFFFFFL
+//INTERCEPT_STATE
+#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE__SHIFT                                                      0x0
+#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE__SHIFT                                                      0x1
+#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE__SHIFT                                                        0x4
+#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE__SHIFT                                                        0x5
+#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE__SHIFT                                                        0x6
+#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE__SHIFT                                                        0x7
+#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE__SHIFT                                                        0x8
+#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE__SHIFT                                                        0x9
+#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE__SHIFT                                                        0xa
+#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE_MASK                                                        0x00000001L
+#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE_MASK                                                        0x00000002L
+#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE_MASK                                                          0x00000010L
+#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE_MASK                                                          0x00000020L
+#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE_MASK                                                          0x00000040L
+#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE_MASK                                                          0x00000080L
+#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE_MASK                                                          0x00000100L
+#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE_MASK                                                          0x00000200L
+#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE_MASK                                                          0x00000400L
+//DCIO_PATTERN_GEN_PAT
+#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT__SHIFT                                                     0x0
+#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT_MASK                                                       0xFFFFFFFFL
+//DCIO_PATTERN_GEN_EN
+#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN__SHIFT                                                       0x0
+#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN_MASK                                                         0x00000001L
+//DCIO_BL_PWM_FRAME_START_DISP_SEL
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x0
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x4
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000007L
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000070L
+//DCIO_GSL_GENLK_PAD_CNTL
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT                                     0x4
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT                                               0x8
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT                                   0x14
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT                                             0x18
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK                                       0x00000030L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK                                                 0x00000300L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK                                     0x00300000L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK                                               0x03000000L
+//DCIO_GSL_SWAPLOCK_PAD_CNTL
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT                                 0x4
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT                                           0x8
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT                                 0x14
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT                                           0x18
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK                                   0x00000030L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK                                             0x00000300L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK                                   0x00300000L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK                                             0x03000000L
+//DCIO_SOFT_RESET
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT                                                            0x0
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT                                                            0x1
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT                                                            0x2
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT                                                            0x3
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT                                                            0x4
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT                                                            0x5
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT                                                            0x6
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT                                                             0x8
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT                                                             0x9
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT                                                             0xa
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT                                                             0xb
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT                                                             0xc
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT                                                             0xd
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT                                                             0xe
+#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET__SHIFT                                                            0x10
+#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET__SHIFT                                                            0x11
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK                                                              0x00000001L
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK                                                              0x00000002L
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK                                                              0x00000004L
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK                                                              0x00000008L
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK                                                              0x00000010L
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK                                                              0x00000020L
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK                                                              0x00000040L
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK                                                               0x00000100L
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK                                                               0x00000200L
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK                                                               0x00000400L
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK                                                               0x00000800L
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK                                                               0x00001000L
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK                                                               0x00002000L
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK                                                               0x00004000L
+#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET_MASK                                                              0x00010000L
+#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET_MASK                                                              0x00020000L
+
+
+// addressBlock: dce_dc_dcio_dcio_chip_dispdec
+//DC_GPIO_GENERIC_MASK
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT                                                    0x0
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT                                                  0x1
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT                                                    0x2
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT                                                    0x4
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT                                                  0x5
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT                                                    0x6
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT                                                    0x8
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT                                                  0x9
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT                                                    0xa
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT                                                    0xc
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT                                                  0xd
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT                                                    0xe
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT                                                    0x10
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT                                                  0x11
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT                                                    0x12
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT                                                    0x14
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT                                                  0x15
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT                                                    0x16
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT                                                    0x18
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT                                                  0x19
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT                                                    0x1a
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN__SHIFT                                             0x1c
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK                                                      0x00000001L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK                                                    0x00000002L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK                                                      0x0000000CL
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK                                                      0x00000010L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK                                                    0x00000020L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK                                                      0x000000C0L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK                                                      0x00000100L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK                                                    0x00000200L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK                                                      0x00000C00L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK                                                      0x00001000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK                                                    0x00002000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK                                                      0x0000C000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK                                                      0x00010000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK                                                    0x00020000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK                                                      0x000C0000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK                                                      0x00100000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK                                                    0x00200000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK                                                      0x00C00000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK                                                      0x01000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK                                                    0x02000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK                                                      0x0C000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN_MASK                                               0xF0000000L
+//DC_GPIO_GENERIC_A
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT                                                          0x0
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT                                                          0x8
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT                                                          0x10
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT                                                          0x14
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT                                                          0x15
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT                                                          0x16
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT                                                          0x17
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK                                                            0x00000001L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK                                                            0x00000100L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK                                                            0x00010000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK                                                            0x00100000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK                                                            0x00200000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK                                                            0x00400000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK                                                            0x00800000L
+//DC_GPIO_GENERIC_EN
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT                                                        0x0
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT                                                        0x8
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT                                                        0x10
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT                                                        0x14
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT                                                        0x15
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT                                                        0x16
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT                                                        0x17
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK                                                          0x00000001L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK                                                          0x00000100L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK                                                          0x00010000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK                                                          0x00100000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK                                                          0x00200000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK                                                          0x00400000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK                                                          0x00800000L
+//DC_GPIO_GENERIC_Y
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT                                                          0x0
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT                                                          0x8
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT                                                          0x10
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT                                                          0x14
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT                                                          0x15
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT                                                          0x16
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT                                                          0x17
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK                                                            0x00000001L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK                                                            0x00000100L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK                                                            0x00010000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK                                                            0x00100000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK                                                            0x00200000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK                                                            0x00400000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK                                                            0x00800000L
+//DC_GPIO_DDC1_MASK
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC1_A
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC1_EN
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC1_Y
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC2_MASK
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC2_A
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC2_EN
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC2_Y
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC3_MASK
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC3_A
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC3_EN
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC3_Y
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC4_MASK
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC4_A
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC4_EN
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC4_Y
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC5_MASK
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC5_A
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC5_EN
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC5_Y
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDCVGA_MASK
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT                                                    0x0
+#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY__SHIFT                                              0x4
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT                                                    0x6
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT                                                   0x8
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT                                                  0xc
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT                                                   0xe
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT                                                           0x10
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT                                                                0x14
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT                                                     0x16
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT                                                     0x18
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT                                                    0x1c
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK                                                      0x00000001L
+#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY_MASK                                                0x00000010L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK                                                      0x00000040L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK                                                     0x00000100L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK                                                    0x00001000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK                                                     0x00004000L
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK                                                             0x00010000L
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK                                                                  0x00100000L
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK                                                       0x00400000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK                                                       0x0F000000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK                                                      0xF0000000L
+//DC_GPIO_DDCVGA_A
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT                                                          0x0
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT                                                         0x8
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK                                                            0x00000001L
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK                                                           0x00000100L
+//DC_GPIO_DDCVGA_EN
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT                                                        0x0
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT                                                       0x8
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK                                                          0x00000001L
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK                                                         0x00000100L
+//DC_GPIO_DDCVGA_Y
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT                                                          0x0
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT                                                         0x8
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK                                                            0x00000001L
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK                                                           0x00000100L
+//DC_GPIO_GENLK_MASK
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT                                                     0x0
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT                                                   0x1
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT                                                    0x3
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT                                                     0x4
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT                                                   0x8
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT                                                 0x9
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT                                                  0xb
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT                                                   0xc
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT                                                    0x10
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT                                                  0x11
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT                                                   0x13
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT                                                    0x14
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT                                                    0x18
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT                                                  0x19
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT                                                   0x1b
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT                                                    0x1c
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK                                                       0x00000001L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK                                                     0x00000002L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK                                                      0x00000008L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK                                                       0x00000030L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK                                                     0x00000100L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK                                                   0x00000200L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK                                                    0x00000800L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK                                                     0x00003000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK                                                      0x00010000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK                                                    0x00020000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK                                                     0x00080000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK                                                      0x00300000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK                                                      0x01000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK                                                    0x02000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK                                                     0x08000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK                                                      0x30000000L
+//DC_GPIO_GENLK_A
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT                                                           0x0
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT                                                         0x8
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT                                                          0x10
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT                                                          0x18
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK                                                             0x00000001L
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK                                                           0x00000100L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK                                                            0x00010000L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK                                                            0x01000000L
+//DC_GPIO_GENLK_EN
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT                                                         0x0
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT                                                       0x8
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT                                                        0x10
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT                                                        0x18
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK                                                           0x00000001L
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK                                                         0x00000100L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK                                                          0x00010000L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK                                                          0x01000000L
+//DC_GPIO_GENLK_Y
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT                                                           0x0
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT                                                         0x8
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT                                                          0x10
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT                                                          0x18
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK                                                             0x00000001L
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK                                                           0x00000100L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK                                                            0x00010000L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK                                                            0x01000000L
+//DC_GPIO_HPD_MASK
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT                                                            0x0
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT                                                          0x4
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT                                                            0x6
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT                                                            0x8
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT                                                          0x9
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT                                                            0xa
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT                                                            0x10
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT                                                          0x11
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT                                                            0x12
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT                                                            0x14
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT                                                          0x15
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT                                                            0x16
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT                                                            0x18
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT                                                          0x19
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT                                                            0x1a
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT                                                            0x1c
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT                                                          0x1d
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT                                                            0x1e
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK                                                              0x00000001L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK                                                            0x00000010L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK                                                              0x000000C0L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK                                                              0x00000100L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK                                                            0x00000200L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK                                                              0x00000C00L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK                                                              0x00010000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK                                                            0x00020000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK                                                              0x000C0000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK                                                              0x00100000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK                                                            0x00200000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK                                                              0x00C00000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK                                                              0x01000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK                                                            0x02000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK                                                              0x0C000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK                                                              0x10000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK                                                            0x20000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK                                                              0xC0000000L
+//DC_GPIO_HPD_A
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT                                                                  0x0
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT                                                                  0x8
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT                                                                  0x10
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT                                                                  0x18
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT                                                                  0x1a
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT                                                                  0x1c
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK                                                                    0x00000001L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK                                                                    0x00000100L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK                                                                    0x00010000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK                                                                    0x01000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK                                                                    0x04000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK                                                                    0x10000000L
+//DC_GPIO_HPD_EN
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT                                                                0x0
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT                                                                 0x1
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT                                                                 0x2
+#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT                                                                   0x5
+#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT                                                                      0x6
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT                                                                0x8
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT                                                                 0x9
+#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT                                                                   0xa
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT                                                                0x10
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT                                                                 0x11
+#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT                                                                   0x12
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT                                                                0x14
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT                                                                 0x15
+#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT                                                                   0x16
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT                                                                0x18
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT                                                                 0x19
+#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT                                                                   0x1a
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT                                                                0x1c
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT                                                                 0x1d
+#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT                                                                   0x1e
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK                                                                  0x00000001L
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK                                                                   0x00000002L
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK                                                                   0x00000004L
+#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK                                                                     0x00000020L
+#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK                                                                        0x00000040L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK                                                                  0x00000100L
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK                                                                   0x00000200L
+#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK                                                                     0x00000400L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK                                                                  0x00010000L
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK                                                                   0x00020000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK                                                                     0x00040000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK                                                                  0x00100000L
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK                                                                   0x00200000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK                                                                     0x00400000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK                                                                  0x01000000L
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK                                                                   0x02000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK                                                                     0x04000000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK                                                                  0x10000000L
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK                                                                   0x20000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK                                                                     0x40000000L
+//DC_GPIO_HPD_Y
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT                                                                  0x0
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT                                                                  0x8
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT                                                                  0x10
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT                                                                  0x18
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT                                                                  0x1a
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT                                                                  0x1c
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK                                                                    0x00000001L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK                                                                    0x00000100L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK                                                                    0x00010000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK                                                                    0x01000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK                                                                    0x04000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK                                                                    0x10000000L
+//DC_GPIO_DRIVE_STRENGTH_S0
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICA_S0__SHIFT                                                 0x0
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICB_S0__SHIFT                                                 0x1
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICC_S0__SHIFT                                                 0x2
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICD_S0__SHIFT                                                 0x3
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICE_S0__SHIFT                                                 0x4
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICF_S0__SHIFT                                                 0x5
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICG_S0__SHIFT                                                 0x6
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_CLK_S0__SHIFT                                                0x8
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_VSYNC_S0__SHIFT                                              0x9
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_A_S0__SHIFT                                               0xa
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_B_S0__SHIFT                                               0xb
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICA_S0_MASK                                                   0x00000001L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICB_S0_MASK                                                   0x00000002L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICC_S0_MASK                                                   0x00000004L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICD_S0_MASK                                                   0x00000008L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICE_S0_MASK                                                   0x00000010L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICF_S0_MASK                                                   0x00000020L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICG_S0_MASK                                                   0x00000040L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_CLK_S0_MASK                                                  0x00000100L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_VSYNC_S0_MASK                                                0x00000200L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_A_S0_MASK                                                 0x00000400L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_B_S0_MASK                                                 0x00000800L
+//DC_GPIO_DRIVE_STRENGTH_S1
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICA_S1__SHIFT                                                 0x0
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICB_S1__SHIFT                                                 0x1
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICC_S1__SHIFT                                                 0x2
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICD_S1__SHIFT                                                 0x3
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICE_S1__SHIFT                                                 0x4
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICF_S1__SHIFT                                                 0x5
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICG_S1__SHIFT                                                 0x6
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_CLK_S1__SHIFT                                                0x8
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_VSYNC_S1__SHIFT                                              0x9
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_A_S1__SHIFT                                               0xa
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_B_S1__SHIFT                                               0xb
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICA_S1_MASK                                                   0x00000001L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICB_S1_MASK                                                   0x00000002L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICC_S1_MASK                                                   0x00000004L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICD_S1_MASK                                                   0x00000008L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICE_S1_MASK                                                   0x00000010L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICF_S1_MASK                                                   0x00000020L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICG_S1_MASK                                                   0x00000040L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_CLK_S1_MASK                                                  0x00000100L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_VSYNC_S1_MASK                                                0x00000200L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_A_S1_MASK                                                 0x00000400L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_B_S1_MASK                                                 0x00000800L
+//DC_GPIO_PWRSEQ0_EN
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT                                               0x14
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT                                              0x15
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT                                                  0x19
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT                                                 0x1a
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                0x1d
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK                                                 0x00100000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK                                                0x00E00000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK                                                    0x02000000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK                                                   0x1C000000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                  0x20000000L
+//DC_GPIO_PAD_STRENGTH_1
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT                                                      0x0
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT                                                      0x4
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT                                                     0x10
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT                                                     0x14
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT                                                       0x18
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT                                                       0x1c
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK                                                        0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK                                                        0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK                                                       0x000F0000L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK                                                       0x00F00000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK                                                         0x0F000000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK                                                         0xF0000000L
+//DC_GPIO_PAD_STRENGTH_2
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT                                                            0x0
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT                                                            0x4
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT                                                  0x8
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT                                                     0xc
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT                                                         0x1e
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK                                                              0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK                                                              0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK                                                    0x00000700L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK                                                       0x00007000L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK                                                           0xC0000000L
+//PHY_AUX_CNTL
+#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT                                                                     0x9
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT                                                                   0xa
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT                                                                   0xc
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT                                                                   0xe
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT                                                                   0x10
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT                                                                   0x12
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT                                                                   0x14
+#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK                                                                       0x00000200L
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK                                                                     0x00000C00L
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK                                                                     0x00003000L
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK                                                                     0x0000C000L
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK                                                                     0x00030000L
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK                                                                     0x000C0000L
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK                                                                     0x00300000L
+//DC_GPIO_DRIVE_TXIMPSEL
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICA_TXIMPSEL__SHIFT                                              0x0
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICB_TXIMPSEL__SHIFT                                              0x1
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICC_TXIMPSEL__SHIFT                                              0x2
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICD_TXIMPSEL__SHIFT                                              0x3
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICE_TXIMPSEL__SHIFT                                              0x4
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICF_TXIMPSEL__SHIFT                                              0x5
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICG_TXIMPSEL__SHIFT                                              0x6
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_CLK_TXIMPSEL__SHIFT                                             0x8
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_VSYNC_TXIMPSEL__SHIFT                                           0x9
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_A_TXIMPSEL__SHIFT                                            0xa
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_B_TXIMPSEL__SHIFT                                            0xb
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD1_TXIMPSEL__SHIFT                                                  0xc
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD2_TXIMPSEL__SHIFT                                                  0xd
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD3_TXIMPSEL__SHIFT                                                  0xe
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD4_TXIMPSEL__SHIFT                                                  0xf
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD5_TXIMPSEL__SHIFT                                                  0x10
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD6_TXIMPSEL__SHIFT                                                  0x11
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICA_TXIMPSEL_MASK                                                0x00000001L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICB_TXIMPSEL_MASK                                                0x00000002L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICC_TXIMPSEL_MASK                                                0x00000004L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICD_TXIMPSEL_MASK                                                0x00000008L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICE_TXIMPSEL_MASK                                                0x00000010L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICF_TXIMPSEL_MASK                                                0x00000020L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICG_TXIMPSEL_MASK                                                0x00000040L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_CLK_TXIMPSEL_MASK                                               0x00000100L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_VSYNC_TXIMPSEL_MASK                                             0x00000200L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_A_TXIMPSEL_MASK                                              0x00000400L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_B_TXIMPSEL_MASK                                              0x00000800L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD1_TXIMPSEL_MASK                                                    0x00001000L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD2_TXIMPSEL_MASK                                                    0x00002000L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD3_TXIMPSEL_MASK                                                    0x00004000L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD4_TXIMPSEL_MASK                                                    0x00008000L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD5_TXIMPSEL_MASK                                                    0x00010000L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD6_TXIMPSEL_MASK                                                    0x00020000L
+//DC_GPIO_TX12_EN
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT                                                      0x3
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT                                                      0x4
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT                                                      0x5
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT                                                      0x6
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT                                                      0x7
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT                                                      0x8
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT                                                      0x9
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK                                                        0x00000008L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK                                                        0x00000010L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK                                                        0x00000020L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK                                                        0x00000040L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK                                                        0x00000080L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK                                                        0x00000100L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK                                                        0x00000200L
+//DC_GPIO_AUX_CTRL_0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT                                                   0x0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT                                                   0x2
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT                                                   0x4
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT                                                   0x6
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT                                                   0x8
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT                                                   0xa
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT                                                 0xc
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT                                                     0x10
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT                                                     0x11
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT                                                     0x12
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT                                                     0x13
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT                                                     0x14
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT                                                     0x15
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT                                                   0x16
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT                                                    0x18
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT                                                    0x19
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT                                                    0x1a
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT                                                    0x1b
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT                                                    0x1c
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT                                                    0x1d
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT                                                  0x1e
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK                                                     0x00000003L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK                                                     0x0000000CL
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK                                                     0x00000030L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK                                                     0x000000C0L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK                                                     0x00000300L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK                                                     0x00000C00L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK                                                   0x00003000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK                                                       0x00010000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK                                                       0x00020000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK                                                       0x00040000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK                                                       0x00080000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK                                                       0x00100000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK                                                       0x00200000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK                                                     0x00C00000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK                                                      0x01000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK                                                      0x02000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK                                                      0x04000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK                                                      0x08000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK                                                      0x10000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK                                                      0x20000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK                                                    0xC0000000L
+//DC_GPIO_AUX_CTRL_1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT                                                       0x0
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT                                                       0x1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT                                                       0x2
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT                                                       0x3
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT                                                       0x4
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT                                                       0x5
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT                                                       0x6
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT                                                       0x7
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT                                                      0x8
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT                                                      0xa
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT                                                      0xb
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT                                                       0xd
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT                                                       0xe
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT                                                      0x10
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT                                                       0x12
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT                                                       0x14
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT                                                       0x19
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT                                                       0x1a
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT                                                       0x1b
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT                                                       0x1c
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT                                                       0x1d
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT                                                     0x1e
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK                                                         0x00000001L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK                                                         0x00000002L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK                                                         0x00000004L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK                                                         0x00000008L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK                                                         0x00000010L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK                                                         0x00000020L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK                                                         0x00000040L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK                                                         0x00000080L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK                                                        0x00000100L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK                                                        0x00000400L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK                                                        0x00001800L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK                                                         0x00002000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK                                                         0x0000C000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK                                                        0x00030000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK                                                         0x000C0000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK                                                         0x00300000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK                                                         0x02000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK                                                         0x04000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK                                                         0x08000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK                                                         0x10000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK                                                         0x20000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK                                                       0xC0000000L
+//DC_GPIO_AUX_CTRL_2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT                                                  0x0
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT                                                  0x2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT                                                  0x4
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT                                                    0x8
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT                                                    0x9
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT                                                    0xa
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT                                                   0xc
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT                                                   0xd
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT                                                   0xe
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT                                                       0x10
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT                                                       0x11
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT                                                       0x12
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT                                                       0x13
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT                                                      0x14
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT                                                        0x18
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT                                                        0x19
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT                                                        0x1a
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT                                                      0x1b
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT                                                      0x1c
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT                                                      0x1d
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT                                                      0x1e
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK                                                    0x00000003L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK                                                    0x0000000CL
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK                                                    0x00000030L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK                                                      0x00000100L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK                                                      0x00000200L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK                                                      0x00000400L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK                                                     0x00001000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK                                                     0x00002000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK                                                     0x00004000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK                                                         0x00010000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK                                                         0x00020000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK                                                         0x00040000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK                                                         0x00080000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK                                                        0x00100000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK                                                          0x01000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK                                                          0x02000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK                                                          0x04000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK                                                        0x08000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK                                                        0x10000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK                                                        0x20000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK                                                        0x40000000L
+//DC_GPIO_RXEN
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT                                                            0x0
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT                                                            0x1
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT                                                            0x2
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT                                                            0x3
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT                                                            0x4
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT                                                            0x5
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT                                                            0x6
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT                                                              0x8
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT                                                              0x9
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT                                                           0xa
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT                                                         0xb
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT                                                          0xc
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT                                                          0xd
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT                                                                0xe
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT                                                                0xf
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT                                                                0x10
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT                                                                0x11
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT                                                                0x12
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT                                                                0x13
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK                                                              0x00000001L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK                                                              0x00000002L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK                                                              0x00000004L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK                                                              0x00000008L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK                                                              0x00000010L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK                                                              0x00000020L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK                                                              0x00000040L
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK                                                                0x00000100L
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK                                                                0x00000200L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK                                                             0x00000400L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK                                                           0x00000800L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK                                                            0x00001000L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK                                                            0x00002000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK                                                                  0x00004000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK                                                                  0x00008000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK                                                                  0x00010000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK                                                                  0x00020000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK                                                                  0x00040000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK                                                                  0x00080000L
+//DC_GPIO_PULLUPEN
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT                                                       0x0
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT                                                       0x1
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT                                                       0x2
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT                                                       0x3
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT                                                       0x4
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT                                                       0x5
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT                                                       0x6
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT                                                         0x8
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT                                                         0x9
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT                                                           0xe
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT                                                           0xf
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT                                                           0x10
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT                                                           0x11
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT                                                           0x12
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT                                                           0x13
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK                                                         0x00000001L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK                                                         0x00000002L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK                                                         0x00000004L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK                                                         0x00000008L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK                                                         0x00000010L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK                                                         0x00000020L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK                                                         0x00000040L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK                                                           0x00000100L
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK                                                           0x00000200L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK                                                             0x00004000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK                                                             0x00008000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK                                                             0x00010000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK                                                             0x00020000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK                                                             0x00040000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK                                                             0x00080000L
+//DC_GPIO_AUX_CTRL_3
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT                                                             0x0
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT                                                             0x1
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT                                                             0x2
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT                                                             0x3
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT                                                             0x4
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT                                                             0x5
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT                                                            0x8
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT                                                            0x9
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT                                                            0xa
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT                                                            0xb
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT                                                            0xc
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT                                                            0xd
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT                                                              0x10
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT                                                              0x12
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT                                                              0x14
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT                                                              0x16
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT                                                              0x18
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT                                                              0x1a
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK                                                               0x00000001L
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK                                                               0x00000002L
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK                                                               0x00000004L
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK                                                               0x00000008L
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK                                                               0x00000010L
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK                                                               0x00000020L
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK                                                              0x00000100L
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK                                                              0x00000200L
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK                                                              0x00000400L
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK                                                              0x00000800L
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK                                                              0x00001000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK                                                              0x00002000L
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK                                                                0x00030000L
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK                                                                0x000C0000L
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK                                                                0x00300000L
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK                                                                0x00C00000L
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK                                                                0x03000000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK                                                                0x0C000000L
+//DC_GPIO_AUX_CTRL_4
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT                                                              0x0
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT                                                              0x4
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT                                                              0x8
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT                                                              0xc
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT                                                              0x10
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT                                                              0x14
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK                                                                0x0000000FL
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK                                                                0x000000F0L
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK                                                                0x00000F00L
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK                                                                0x0000F000L
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK                                                                0x000F0000L
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK                                                                0x00F00000L
+//DC_GPIO_AUX_CTRL_5
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT                                                              0x0
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT                                                              0x2
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT                                                              0x4
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT                                                              0x6
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT                                                              0x8
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT                                                              0xa
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT                                                           0xc
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT                                                           0xd
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT                                                           0xe
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT                                                           0xf
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT                                                           0x10
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT                                                           0x11
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT                                                        0x12
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT                                                        0x13
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT                                                        0x14
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT                                                        0x15
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT                                                        0x16
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT                                                        0x17
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT                                                          0x18
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT                                                          0x19
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT                                                          0x1a
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT                                                          0x1b
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT                                                          0x1c
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT                                                          0x1d
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK                                                                0x00000003L
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK                                                                0x0000000CL
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK                                                                0x00000030L
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK                                                                0x000000C0L
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK                                                                0x00000300L
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK                                                                0x00000C00L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK                                                             0x00001000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK                                                             0x00002000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK                                                             0x00004000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK                                                             0x00008000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK                                                             0x00010000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK                                                             0x00020000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK                                                          0x00040000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK                                                          0x00080000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK                                                          0x00100000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK                                                          0x00200000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK                                                          0x00400000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK                                                          0x00800000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK                                                            0x01000000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK                                                            0x02000000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK                                                            0x04000000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK                                                            0x08000000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK                                                            0x10000000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK                                                            0x20000000L
+//AUXI2C_PAD_ALL_PWR_OK
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT                                                  0x0
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT                                                  0x1
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT                                                  0x2
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT                                                  0x3
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT                                                  0x4
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT                                                  0x5
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK                                                    0x00000001L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK                                                    0x00000002L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK                                                    0x00000004L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK                                                    0x00000008L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK                                                    0x00000010L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK                                                    0x00000020L
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec
+//DC_GPIO_PWRSEQ_EN
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT                                                          0x0
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT                                                            0x8
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT                                                             0x10
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK                                                            0x00000001L
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK                                                              0x00000100L
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK                                                               0x00010000L
+//DC_GPIO_PWRSEQ_CTRL
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TXIMPSEL__SHIFT                                                  0x0
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TXIMPSEL__SHIFT                                                    0x1
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TXIMPSEL__SHIFT                                                     0x2
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT                                                      0x3
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT                                                        0x4
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT                                                         0x5
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT                                                     0x6
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT                                                       0x7
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT                                                        0x8
+#define DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_S0__SHIFT                                                        0x10
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_S1__SHIFT                                                        0x14
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_S1__SHIFT                                                          0x15
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_S1__SHIFT                                                           0x16
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TXIMPSEL_MASK                                                    0x00000001L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TXIMPSEL_MASK                                                      0x00000002L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TXIMPSEL_MASK                                                       0x00000004L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK                                                        0x00000008L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK                                                          0x00000010L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK                                                           0x00000020L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK                                                       0x00000040L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK                                                         0x00000080L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK                                                          0x00000100L
+#define DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_S0_MASK                                                          0x00010000L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_S1_MASK                                                          0x00100000L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_S1_MASK                                                            0x00200000L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_S1_MASK                                                             0x00400000L
+//DC_GPIO_PWRSEQ_MASK
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT                                                      0x0
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT                                                    0x4
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT                                                      0x6
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                        0x8
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                                      0xc
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                        0xe
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT                                                         0x10
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                                       0x14
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT                                                         0x16
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK                                                        0x00000001L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK                                                      0x00000010L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK                                                        0x000000C0L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK                                                          0x00000100L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                        0x00001000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK                                                          0x0000C000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK                                                           0x00010000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                         0x00100000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK                                                           0x00C00000L
+//DC_GPIO_PWRSEQ_A_Y
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT                                                          0x0
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT                                                          0x1
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT                                                            0x8
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT                                                            0x9
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT                                                             0x10
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT                                                             0x11
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK                                                            0x00000001L
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK                                                            0x00000002L
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK                                                              0x00000100L
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK                                                              0x00000200L
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK                                                               0x00010000L
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK                                                               0x00020000L
+//PANEL_PWRSEQ_CNTL
+#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT                                                             0x0
+#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT                                                   0x4
+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT                                                                0x8
+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT                                                           0x9
+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT                                                            0xa
+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT                                                                 0x10
+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT                                                            0x11
+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT                                                             0x12
+#define PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT                                                                  0x18
+#define PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT                                                             0x19
+#define PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT                                                              0x1a
+#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK                                                               0x00000001L
+#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK                                                     0x00000010L
+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK                                                                  0x00000100L
+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK                                                             0x00000200L
+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK                                                              0x00000400L
+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK                                                                   0x00010000L
+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK                                                              0x00020000L
+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK                                                               0x00040000L
+#define PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK                                                                    0x01000000L
+#define PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK                                                               0x02000000L
+#define PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK                                                                0x04000000L
+//PANEL_PWRSEQ_STATE
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT                                                0x0
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT                                                         0x1
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT                                                        0x2
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT                                                          0x3
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT                                                          0x4
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT                                                         0x8
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK                                                  0x00000001L
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK                                                           0x00000002L
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK                                                          0x00000004L
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK                                                            0x00000008L
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK                                                            0x00000010L
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK                                                           0x00000F00L
+//PANEL_PWRSEQ_DELAY1
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT                                                        0x0
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT                                                        0x8
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT                                                        0x10
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT                                                        0x18
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK                                                          0x000000FFL
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK                                                          0x0000FF00L
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK                                                          0x00FF0000L
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK                                                          0xFF000000L
+//PANEL_PWRSEQ_DELAY2
+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT                                                    0x0
+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT                                                        0x8
+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT                                                        0x10
+#define PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT                                                 0x18
+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK                                                      0x000000FFL
+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK                                                          0x0000FF00L
+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK                                                          0x00FF0000L
+#define PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK                                                   0x01000000L
+//PANEL_PWRSEQ_REF_DIV1
+#define PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT                                                    0x0
+#define PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT                                                          0x10
+#define PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK                                                      0x00000FFFL
+#define PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK                                                            0xFFFF0000L
+//BL_PWM_CNTL
+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                            0x0
+#define BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT                                                                 0x13
+#define BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT                                                      0x14
+#define BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                                    0x15
+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                              0x1e
+#define BL_PWM_CNTL__BL_PWM_EN__SHIFT                                                                         0x1f
+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                              0x0000FFFFL
+#define BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK                                                                   0x00080000L
+#define BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK                                                        0x00100000L
+#define BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                      0x00200000L
+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                                0x40000000L
+#define BL_PWM_CNTL__BL_PWM_EN_MASK                                                                           0x80000000L
+//BL_PWM_CNTL2
+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                                      0x0
+#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT                                                   0x1c
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                                    0x1e
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT                                                  0x1f
+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                        0x0000FFFFL
+#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK                                                     0x30000000L
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                                      0x40000000L
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK                                                    0x80000000L
+//BL_PWM_PERIOD_CNTL
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                              0x0
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                                       0x10
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                                0x0000FFFFL
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                         0x000F0000L
+//BL_PWM_GRP1_REG_LOCK
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                                     0x0
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                           0x8
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                        0x10
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                                     0x18
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                        0x1f
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                                       0x00000001L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                             0x00000100L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                          0x00010000L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                                       0x01000000L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                          0x80000000L
+//PANEL_PWRSEQ_REF_DIV2
+#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT                                                            0x0
+#define PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT                                               0x8
+#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT                                        0x10
+#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK                                                              0x0000007FL
+#define PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK                                                 0x00007F00L
+#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK                                          0x00010000L
+//PWRSEQ_SPARE
+#define PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT                                                                     0x0
+#define PWRSEQ_SPARE__PWRSEQ_SPARE_MASK                                                                       0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
+//DSCC0_DSCC_CONFIG0
+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC0_DSCC_CONFIG1
+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
+//DSCC0_DSCC_STATUS
+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC0_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                    0xc
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT             0x1c
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                      0x00001000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK               0x10000000L
+//DSCC0_DSCC_PPS_CONFIG0
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC0_DSCC_PPS_CONFIG1
+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG2
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG3
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG4
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG5
+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG6
+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC0_DSCC_PPS_CONFIG7
+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG8
+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG9
+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG10
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG11
+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC0_DSCC_PPS_CONFIG12
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG13
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG14
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG15
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG16
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG17
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG18
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG19
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG20
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG21
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG22
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC0_DSCC_MEM_POWER_CONTROL
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_MAX_ABS_ERROR0
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC0_DSCC_MAX_ABS_ERROR1
+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
+//DSCCIF0_DSCCIF_CONFIG0
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF0_DSCCIF_CONFIG1
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
+//DSC_TOP0_DSC_TOP_CONTROL
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+//DSC_TOP0_DSC_DEBUG_CONTROL
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
+//DSCC1_DSCC_CONFIG0
+#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC1_DSCC_CONFIG1
+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
+//DSCC1_DSCC_STATUS
+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC1_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                    0xc
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT             0x1c
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                      0x00001000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK               0x10000000L
+//DSCC1_DSCC_PPS_CONFIG0
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC1_DSCC_PPS_CONFIG1
+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG2
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG3
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG4
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG5
+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG6
+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC1_DSCC_PPS_CONFIG7
+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG8
+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG9
+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG10
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG11
+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC1_DSCC_PPS_CONFIG12
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG13
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG14
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG15
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG16
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG17
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG18
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG19
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG20
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG21
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG22
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC1_DSCC_MEM_POWER_CONTROL
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_MAX_ABS_ERROR0
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC1_DSCC_MAX_ABS_ERROR1
+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
+//DSCCIF1_DSCCIF_CONFIG0
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF1_DSCCIF_CONFIG1
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
+//DSC_TOP1_DSC_TOP_CONTROL
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
+//DSCC2_DSCC_CONFIG0
+#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC2_DSCC_CONFIG1
+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
+//DSCC2_DSCC_STATUS
+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC2_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                    0xc
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT             0x1c
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                      0x00001000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK               0x10000000L
+//DSCC2_DSCC_PPS_CONFIG0
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC2_DSCC_PPS_CONFIG1
+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG2
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG3
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG4
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG5
+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG6
+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC2_DSCC_PPS_CONFIG7
+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG8
+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG9
+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG10
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG11
+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC2_DSCC_PPS_CONFIG12
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC2_DSCC_PPS_CONFIG13
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC2_DSCC_PPS_CONFIG14
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC2_DSCC_PPS_CONFIG15
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG16
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG17
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG18
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG19
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG20
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG21
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG22
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC2_DSCC_MEM_POWER_CONTROL
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_MAX_ABS_ERROR0
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC2_DSCC_MAX_ABS_ERROR1
+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
+//DSCCIF2_DSCCIF_CONFIG0
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF2_DSCCIF_CONFIG1
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
+//DSC_TOP2_DSC_TOP_CONTROL
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+
+
+// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec
+//DSCC3_DSCC_CONFIG0
+#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC3_DSCC_CONFIG1
+#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
+#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
+//DSCC3_DSCC_STATUS
+#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC3_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                    0xc
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT             0x1c
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                      0x00001000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK               0x10000000L
+//DSCC3_DSCC_PPS_CONFIG0
+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC3_DSCC_PPS_CONFIG1
+#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG2
+#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG3
+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG4
+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG5
+#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG6
+#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC3_DSCC_PPS_CONFIG7
+#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG8
+#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG9
+#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG10
+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG11
+#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC3_DSCC_PPS_CONFIG12
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC3_DSCC_PPS_CONFIG13
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC3_DSCC_PPS_CONFIG14
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC3_DSCC_PPS_CONFIG15
+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG16
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG17
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG18
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG19
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG20
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG21
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG22
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC3_DSCC_MEM_POWER_CONTROL
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC3_DSCC_MAX_ABS_ERROR0
+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC3_DSCC_MAX_ABS_ERROR1
+#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+
+
+// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec
+//DSCCIF3_DSCCIF_CONFIG0
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF3_DSCCIF_CONFIG1
+#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec
+//DSC_TOP3_DSC_TOP_CONTROL
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+
+
+// addressBlock: dce_dc_hpo_hpo_top_dispdec
+//HPO_TOP_CLOCK_CONTROL
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT                                                  0x0
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS__SHIFT                                                    0x1
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS__SHIFT                                                     0x5
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS__SHIFT                                            0x8
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS__SHIFT                                            0x9
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS__SHIFT                                              0xc
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS__SHIFT                                              0xd
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS__SHIFT                                              0x10
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS__SHIFT                                              0x11
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS__SHIFT                                              0x12
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS__SHIFT                                              0x13
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS__SHIFT                                              0x14
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS__SHIFT                                              0x15
+#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL__SHIFT                                                        0x18
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS_MASK                                                    0x00000001L
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS_MASK                                                      0x00000002L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS_MASK                                                       0x00000020L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS_MASK                                              0x00000100L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS_MASK                                              0x00000200L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS_MASK                                                0x00001000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS_MASK                                                0x00002000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS_MASK                                                0x00010000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS_MASK                                                0x00020000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS_MASK                                                0x00040000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS_MASK                                                0x00080000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS_MASK                                                0x00100000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS_MASK                                                0x00200000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL_MASK                                                          0xFF000000L
+//HPO_TOP_HW_CONTROL
+#define HPO_TOP_HW_CONTROL__HPO_IO_EN__SHIFT                                                                  0x0
+#define HPO_TOP_HW_CONTROL__HPO_IO_EN_MASK                                                                    0x00000001L
+
+
+// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec
+//DP_STREAM_MAPPER_CONTROL0
+#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET__SHIFT                                               0x0
+#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L
+//DP_STREAM_MAPPER_CONTROL1
+#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET__SHIFT                                               0x0
+#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L
+//DP_STREAM_MAPPER_CONTROL2
+#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET__SHIFT                                               0x0
+#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L
+//DP_STREAM_MAPPER_CONTROL3
+#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET__SHIFT                                               0x0
+#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec
+//AFMT5_AFMT_VBI_PACKET_CONTROL
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT5_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT5_AFMT_AUDIO_INFO0
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT5_AFMT_AUDIO_INFO1
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT5_AFMT_60958_0
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT5_AFMT_60958_1
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT5_AFMT_AUDIO_CRC_CONTROL
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT5_AFMT_RAMP_CONTROL0
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT5_AFMT_RAMP_CONTROL1
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT5_AFMT_RAMP_CONTROL2
+#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT5_AFMT_RAMP_CONTROL3
+#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT5_AFMT_60958_2
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT5_AFMT_AUDIO_CRC_RESULT
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT5_AFMT_STATUS
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT5_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L
+//AFMT5_AFMT_INFOFRAME_CONTROL0
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT5_AFMT_INTERRUPT_STATUS
+//AFMT5_AFMT_AUDIO_SRC_CONTROL
+#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT5_AFMT_MEM_PWR
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec
+//DME5_DME_CONTROL
+#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME5_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME5_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME5_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME5_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME5_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME5_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME5_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME5_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME5_DME_MEMORY_CONTROL
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec
+//VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG5_VPG_GENERIC_PACKET_DATA
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG5_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG5_VPG_GENERIC_STATUS
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG5_VPG_MEM_PWR
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG5_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG5_VPG_ISRC1_2_DATA
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG5_VPG_MPEG_INFO0
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG5_VPG_MPEG_INFO1
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec
+//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L
+//DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL
+#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L
+//DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL
+#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L
+//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L
+//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L
+//DP_STREAM_ENC0_DP_STREAM_ENC_SPARE
+#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec
+//APG0_APG_CONTROL
+#define APG0_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1
+#define APG0_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2
+#define APG0_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L
+#define APG0_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L
+//APG0_APG_CONTROL2
+#define APG0_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0
+#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8
+#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18
+#define APG0_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L
+#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L
+#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L
+//APG0_APG_DBG_GEN_CONTROL
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L
+//APG0_APG_PACKET_CONTROL
+#define APG0_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT                                                       0x0
+#define APG0_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1
+#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2
+#define APG0_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK                                                         0x00000001L
+#define APG0_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L
+#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L
+//APG0_APG_AUDIO_CRC_CONTROL
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L
+//APG0_APG_AUDIO_CRC_CONTROL2
+#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0
+#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL
+//APG0_APG_AUDIO_CRC_RESULT
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L
+//APG0_APG_STATUS
+#define APG0_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4
+#define APG0_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19
+#define APG0_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L
+#define APG0_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L
+//APG0_APG_STATUS2
+#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0
+#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L
+//APG0_APG_MEM_PWR
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8
+#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L
+#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L
+//APG0_APG_SPARE
+#define APG0_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0
+#define APG0_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec
+//DME6_DME_CONTROL
+#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME6_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME6_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME6_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME6_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME6_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME6_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME6_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME6_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME6_DME_MEMORY_CONTROL
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec
+//VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG6_VPG_GENERIC_PACKET_DATA
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG6_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG6_VPG_GENERIC_STATUS
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG6_VPG_MEM_PWR
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG6_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG6_VPG_ISRC1_2_DATA
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG6_VPG_MPEG_INFO0
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG6_VPG_MPEG_INFO1
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec
+//DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L
+//DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SPARE
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec
+//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L
+//DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL
+#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L
+//DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL
+#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L
+//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L
+//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L
+//DP_STREAM_ENC1_DP_STREAM_ENC_SPARE
+#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec
+//APG1_APG_CONTROL
+#define APG1_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1
+#define APG1_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2
+#define APG1_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L
+#define APG1_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L
+//APG1_APG_CONTROL2
+#define APG1_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0
+#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8
+#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18
+#define APG1_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L
+#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L
+#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L
+//APG1_APG_DBG_GEN_CONTROL
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L
+//APG1_APG_PACKET_CONTROL
+#define APG1_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT                                                       0x0
+#define APG1_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1
+#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2
+#define APG1_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK                                                         0x00000001L
+#define APG1_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L
+#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L
+//APG1_APG_AUDIO_CRC_CONTROL
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L
+//APG1_APG_AUDIO_CRC_CONTROL2
+#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0
+#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL
+//APG1_APG_AUDIO_CRC_RESULT
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L
+//APG1_APG_STATUS
+#define APG1_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4
+#define APG1_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19
+#define APG1_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L
+#define APG1_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L
+//APG1_APG_STATUS2
+#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0
+#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L
+//APG1_APG_MEM_PWR
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8
+#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L
+#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L
+//APG1_APG_SPARE
+#define APG1_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0
+#define APG1_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec
+//DME7_DME_CONTROL
+#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME7_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME7_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME7_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME7_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME7_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME7_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME7_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME7_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME7_DME_MEMORY_CONTROL
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec
+//VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG7_VPG_GENERIC_PACKET_DATA
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG7_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG7_VPG_GENERIC_STATUS
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG7_VPG_MEM_PWR
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG7_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG7_VPG_ISRC1_2_DATA
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG7_VPG_MPEG_INFO0
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG7_VPG_MPEG_INFO1
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec
+//DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L
+//DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SPARE
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec
+//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L
+//DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL
+#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L
+//DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL
+#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L
+//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L
+//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L
+//DP_STREAM_ENC2_DP_STREAM_ENC_SPARE
+#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec
+//APG2_APG_CONTROL
+#define APG2_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1
+#define APG2_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2
+#define APG2_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L
+#define APG2_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L
+//APG2_APG_CONTROL2
+#define APG2_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0
+#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8
+#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18
+#define APG2_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L
+#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L
+#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L
+//APG2_APG_DBG_GEN_CONTROL
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L
+//APG2_APG_PACKET_CONTROL
+#define APG2_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT                                                       0x0
+#define APG2_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1
+#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2
+#define APG2_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK                                                         0x00000001L
+#define APG2_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L
+#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L
+//APG2_APG_AUDIO_CRC_CONTROL
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L
+//APG2_APG_AUDIO_CRC_CONTROL2
+#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0
+#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL
+//APG2_APG_AUDIO_CRC_RESULT
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L
+//APG2_APG_STATUS
+#define APG2_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4
+#define APG2_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19
+#define APG2_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L
+#define APG2_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L
+//APG2_APG_STATUS2
+#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0
+#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L
+//APG2_APG_MEM_PWR
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8
+#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L
+#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L
+//APG2_APG_SPARE
+#define APG2_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0
+#define APG2_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec
+//DME8_DME_CONTROL
+#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME8_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME8_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME8_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME8_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME8_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME8_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME8_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME8_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME8_DME_MEMORY_CONTROL
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec
+//VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG8_VPG_GENERIC_PACKET_DATA
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG8_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG8_VPG_GENERIC_STATUS
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG8_VPG_MEM_PWR
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG8_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG8_VPG_ISRC1_2_DATA
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG8_VPG_MPEG_INFO0
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG8_VPG_MPEG_INFO1
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec
+//DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L
+//DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SPARE
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec
+//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L
+//DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL
+#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L
+//DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL
+#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L
+//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L
+//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L
+//DP_STREAM_ENC3_DP_STREAM_ENC_SPARE
+#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec
+//APG3_APG_CONTROL
+#define APG3_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1
+#define APG3_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2
+#define APG3_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L
+#define APG3_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L
+//APG3_APG_CONTROL2
+#define APG3_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0
+#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8
+#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18
+#define APG3_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L
+#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L
+#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L
+//APG3_APG_DBG_GEN_CONTROL
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L
+//APG3_APG_PACKET_CONTROL
+#define APG3_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT                                                       0x0
+#define APG3_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1
+#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2
+#define APG3_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK                                                         0x00000001L
+#define APG3_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L
+#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L
+//APG3_APG_AUDIO_CRC_CONTROL
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L
+//APG3_APG_AUDIO_CRC_CONTROL2
+#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0
+#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL
+//APG3_APG_AUDIO_CRC_RESULT
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L
+//APG3_APG_STATUS
+#define APG3_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4
+#define APG3_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19
+#define APG3_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L
+#define APG3_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L
+//APG3_APG_STATUS2
+#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0
+#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L
+//APG3_APG_MEM_PWR
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8
+#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L
+#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L
+//APG3_APG_SPARE
+#define APG3_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0
+#define APG3_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec
+//DME9_DME_CONTROL
+#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME9_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME9_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME9_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME9_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME9_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME9_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME9_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME9_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME9_DME_MEMORY_CONTROL
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec
+//VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG9_VPG_GENERIC_PACKET_DATA
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG9_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG9_VPG_GENERIC_STATUS
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG9_VPG_MEM_PWR
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG9_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG9_VPG_ISRC1_2_DATA
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG9_VPG_MPEG_INFO0
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG9_VPG_MPEG_INFO1
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec
+//DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L
+//DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SPARE
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec
+//DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT                                   0x0
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT                          0x4
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK                                     0x00000001L
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK                            0x00000010L
+//DP_LINK_ENC0_DP_LINK_ENC_SPARE
+#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT                                              0x0
+#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK                                                0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT                                              0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT                                               0x1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT                                          0x2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE__SHIFT                                                     0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT                                                0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK                                                0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK                                                 0x00000002L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK                                            0x00000004L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE_MASK                                                       0x00000030L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK                                                  0x00000300L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS__SHIFT                                                    0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT                                              0x1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT                                              0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT                                       0xc
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT                                        0x10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS_MASK                                                      0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK                                                0x00000002L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK                                                0x00000030L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK                                         0x00001000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK                                          0x00030000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT                                            0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK                                              0x00000003L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT                                           0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT                                             0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT                                           0xc
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT                                             0x10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT                                           0x14
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT                                             0x18
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT                                           0x1c
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK                                               0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK                                             0x00000070L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK                                               0x00000700L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK                                             0x00007000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK                                               0x00070000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK                                             0x00700000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK                                               0x07000000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK                                             0x70000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT                                    0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK                                      0x000000FFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT                                            0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK                                              0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT                              0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT                                          0x1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT                               0x2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT                                        0x3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT                            0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT                               0x5
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT                             0x6
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT                                    0x7
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT                                        0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK                                0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK                                            0x00000002L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK                                 0x00000004L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK                                          0x00000008L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK                              0x00000010L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK                                 0x00000020L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK                               0x00000040L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK                                      0x00000080L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK                                          0x00000100L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE__SHIFT                               0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE__SHIFT                                 0x2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL__SHIFT                               0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE__SHIFT                               0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE__SHIFT                                 0xa
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL__SHIFT                               0xc
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE__SHIFT                               0x10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE__SHIFT                                 0x12
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL__SHIFT                               0x14
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE__SHIFT                               0x18
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE__SHIFT                                 0x1a
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL__SHIFT                               0x1c
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE_MASK                                 0x00000003L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE_MASK                                   0x00000004L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL_MASK                                 0x000000F0L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE_MASK                                 0x00000300L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE_MASK                                   0x00000400L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL_MASK                                 0x0000F000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE_MASK                                 0x00030000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE_MASK                                   0x00040000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL_MASK                                 0x00F00000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE_MASK                                 0x03000000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE_MASK                                   0x04000000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL_MASK                                 0xF0000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE__SHIFT                                           0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET__SHIFT                                            0x1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE__SHIFT                                      0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE__SHIFT                                       0x6
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE__SHIFT                                 0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF__SHIFT                                      0x10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT__SHIFT                                      0x11
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS__SHIFT                                  0x14
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT__SHIFT                                        0x15
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE_MASK                                             0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET_MASK                                              0x00000002L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE_MASK                                        0x00000030L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE_MASK                                         0x000000C0L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE_MASK                                   0x00003F00L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF_MASK                                        0x00010000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT_MASK                                        0x000E0000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS_MASK                                    0x00100000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT_MASK                                          0x00600000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS__SHIFT                                      0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS_MASK                                        0xFFFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE__SHIFT                                              0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE__SHIFT                                             0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE_MASK                                                0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE_MASK                                               0x00FFFF00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT_MASK                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec
+//DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT                                   0x0
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT                          0x4
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK                                     0x00000001L
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK                            0x00000010L
+//DP_LINK_ENC1_DP_LINK_ENC_SPARE
+#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT                                              0x0
+#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK                                                0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT                                              0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT                                               0x1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT                                          0x2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE__SHIFT                                                     0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT                                                0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK                                                0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK                                                 0x00000002L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK                                            0x00000004L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE_MASK                                                       0x00000030L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK                                                  0x00000300L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS__SHIFT                                                    0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT                                              0x1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT                                              0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT                                       0xc
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT                                        0x10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS_MASK                                                      0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK                                                0x00000002L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK                                                0x00000030L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK                                         0x00001000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK                                          0x00030000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT                                            0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK                                              0x00000003L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT                                           0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT                                             0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT                                           0xc
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT                                             0x10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT                                           0x14
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT                                             0x18
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT                                           0x1c
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK                                               0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK                                             0x00000070L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK                                               0x00000700L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK                                             0x00007000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK                                               0x00070000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK                                             0x00700000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK                                               0x07000000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK                                             0x70000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT                                    0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK                                      0x000000FFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT                                            0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK                                              0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT                              0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT                                          0x1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT                               0x2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT                                        0x3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT                            0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT                               0x5
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT                             0x6
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT                                    0x7
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT                                        0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK                                0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK                                            0x00000002L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK                                 0x00000004L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK                                          0x00000008L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK                              0x00000010L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK                                 0x00000020L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK                               0x00000040L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK                                      0x00000080L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK                                          0x00000100L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE__SHIFT                               0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE__SHIFT                                 0x2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL__SHIFT                               0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE__SHIFT                               0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE__SHIFT                                 0xa
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL__SHIFT                               0xc
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE__SHIFT                               0x10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE__SHIFT                                 0x12
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL__SHIFT                               0x14
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE__SHIFT                               0x18
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE__SHIFT                                 0x1a
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL__SHIFT                               0x1c
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE_MASK                                 0x00000003L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE_MASK                                   0x00000004L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL_MASK                                 0x000000F0L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE_MASK                                 0x00000300L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE_MASK                                   0x00000400L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL_MASK                                 0x0000F000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE_MASK                                 0x00030000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE_MASK                                   0x00040000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL_MASK                                 0x00F00000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE_MASK                                 0x03000000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE_MASK                                   0x04000000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL_MASK                                 0xF0000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE__SHIFT                                           0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET__SHIFT                                            0x1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE__SHIFT                                      0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE__SHIFT                                       0x6
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE__SHIFT                                 0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF__SHIFT                                      0x10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT__SHIFT                                      0x11
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS__SHIFT                                  0x14
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT__SHIFT                                        0x15
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE_MASK                                             0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET_MASK                                              0x00000002L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE_MASK                                        0x00000030L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE_MASK                                         0x000000C0L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE_MASK                                   0x00003F00L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF_MASK                                        0x00010000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT_MASK                                        0x000E0000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS_MASK                                    0x00100000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT_MASK                                          0x00600000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS__SHIFT                                      0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS_MASK                                        0xFFFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE__SHIFT                                              0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE__SHIFT                                             0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE_MASK                                                0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE_MASK                                               0x00FFFF00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT_MASK                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azcontroller_azdec
+//CORB_WRITE_POINTER
+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT                                                         0x0
+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK                                                           0x00FFL
+//CORB_READ_POINTER
+#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT                                                           0x0
+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT                                                     0xf
+#define CORB_READ_POINTER__CORB_READ_POINTER_MASK                                                             0x00FFL
+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK                                                       0x8000L
+//CORB_CONTROL
+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT                                               0x0
+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT                                                           0x1
+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK                                                 0x01L
+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK                                                             0x02L
+//CORB_STATUS
+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT                                                      0x0
+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK                                                        0x01L
+//CORB_SIZE
+#define CORB_SIZE__CORB_SIZE__SHIFT                                                                           0x0
+#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT                                                                0x4
+#define CORB_SIZE__CORB_SIZE_MASK                                                                             0x0003L
+#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK                                                                  0x00F0L
+//RIRB_LOWER_BASE_ADDRESS
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                                    0x0
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT                                               0x7
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                                      0x0000007FL
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK                                                 0xFFFFFF80L
+//RIRB_UPPER_BASE_ADDRESS
+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT                                               0x0
+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK                                                 0xFFFFFFFFL
+//RIRB_WRITE_POINTER
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT                                                         0x0
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT                                                   0xf
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK                                                           0x00FFL
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK                                                     0x8000L
+//RESPONSE_INTERRUPT_COUNT
+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT                                           0x0
+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK                                             0x00FFL
+//RIRB_CONTROL
+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT                                                       0x0
+#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT                                                                  0x1
+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT                                               0x2
+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK                                                         0x01L
+#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK                                                                    0x02L
+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK                                                 0x04L
+//RIRB_STATUS
+#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT                                                                0x0
+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT                                                 0x2
+#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK                                                                  0x01L
+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK                                                   0x04L
+//RIRB_SIZE
+#define RIRB_SIZE__RIRB_SIZE__SHIFT                                                                           0x0
+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT                                                                0x4
+#define RIRB_SIZE__RIRB_SIZE_MASK                                                                             0x0003L
+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK                                                                  0x00F0L
+//IMMEDIATE_COMMAND_OUTPUT_INTERFACE
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT                   0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT                      0x1c
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK                     0x0FFFFFFFL
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK                        0xF0000000L
+//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                               0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                                 0xFFFFFFFFL
+//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                              0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                                0x0000FFFFL
+//IMMEDIATE_RESPONSE_INPUT_INTERFACE
+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT                                    0x0
+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK                                      0xFFFFFFFFL
+//IMMEDIATE_COMMAND_STATUS
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT                                               0x0
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT                                               0x1
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK                                                 0x00000001L
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK                                                 0x00000002L
+//DMA_POSITION_LOWER_BASE_ADDRESS
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT                                    0x0
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                    0x1
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT                               0x7
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK                                      0x00000001L
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                      0x0000007EL
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK                                 0xFFFFFF80L
+//DMA_POSITION_UPPER_BASE_ADDRESS
+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT                               0x0
+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK                                 0xFFFFFFFFL
+//WALL_CLOCK_COUNTER_ALIAS
+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT                                             0x0
+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK                                               0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azendpoint_azdec
+//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                    0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                      0xFFFFFFFFL
+//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                   0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                     0x0001FFFFL
+
+
+// addressBlock: dce_dc_hda_azinputendpoint_azdec
+//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                     0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                       0xFFFFFFFFL
+//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                    0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                      0x0001FFFFL
+
+
+// addressBlock: dce_dc_hda_azroot_azdec
+//AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                        0x0
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                          0xFFFFFFFFL
+//AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                       0x0
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                         0x0001FFFFL
+
+
+// addressBlock: dce_dc_hda_azstream0_azdec
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azstream1_azdec
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azstream2_azdec
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azstream3_azdec
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azstream4_azdec
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azstream5_azdec
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azstream6_azdec
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azstream7_azdec
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: vga_vgaseqind
+//SEQ00
+#define SEQ00__SEQ_RST0B__SHIFT                                                                               0x0
+#define SEQ00__SEQ_RST1B__SHIFT                                                                               0x1
+#define SEQ00__SEQ_RST0B_MASK                                                                                 0x01L
+#define SEQ00__SEQ_RST1B_MASK                                                                                 0x02L
+//SEQ01
+#define SEQ01__SEQ_DOT8__SHIFT                                                                                0x0
+#define SEQ01__SEQ_SHIFT2__SHIFT                                                                              0x2
+#define SEQ01__SEQ_PCLKBY2__SHIFT                                                                             0x3
+#define SEQ01__SEQ_SHIFT4__SHIFT                                                                              0x4
+#define SEQ01__SEQ_MAXBW__SHIFT                                                                               0x5
+#define SEQ01__SEQ_DOT8_MASK                                                                                  0x01L
+#define SEQ01__SEQ_SHIFT2_MASK                                                                                0x04L
+#define SEQ01__SEQ_PCLKBY2_MASK                                                                               0x08L
+#define SEQ01__SEQ_SHIFT4_MASK                                                                                0x10L
+#define SEQ01__SEQ_MAXBW_MASK                                                                                 0x20L
+//SEQ02
+#define SEQ02__SEQ_MAP0_EN__SHIFT                                                                             0x0
+#define SEQ02__SEQ_MAP1_EN__SHIFT                                                                             0x1
+#define SEQ02__SEQ_MAP2_EN__SHIFT                                                                             0x2
+#define SEQ02__SEQ_MAP3_EN__SHIFT                                                                             0x3
+#define SEQ02__SEQ_MAP0_EN_MASK                                                                               0x01L
+#define SEQ02__SEQ_MAP1_EN_MASK                                                                               0x02L
+#define SEQ02__SEQ_MAP2_EN_MASK                                                                               0x04L
+#define SEQ02__SEQ_MAP3_EN_MASK                                                                               0x08L
+//SEQ03
+#define SEQ03__SEQ_FONT_B1__SHIFT                                                                             0x0
+#define SEQ03__SEQ_FONT_B2__SHIFT                                                                             0x1
+#define SEQ03__SEQ_FONT_A1__SHIFT                                                                             0x2
+#define SEQ03__SEQ_FONT_A2__SHIFT                                                                             0x3
+#define SEQ03__SEQ_FONT_B0__SHIFT                                                                             0x4
+#define SEQ03__SEQ_FONT_A0__SHIFT                                                                             0x5
+#define SEQ03__SEQ_FONT_B1_MASK                                                                               0x01L
+#define SEQ03__SEQ_FONT_B2_MASK                                                                               0x02L
+#define SEQ03__SEQ_FONT_A1_MASK                                                                               0x04L
+#define SEQ03__SEQ_FONT_A2_MASK                                                                               0x08L
+#define SEQ03__SEQ_FONT_B0_MASK                                                                               0x10L
+#define SEQ03__SEQ_FONT_A0_MASK                                                                               0x20L
+//SEQ04
+#define SEQ04__SEQ_256K__SHIFT                                                                                0x1
+#define SEQ04__SEQ_ODDEVEN__SHIFT                                                                             0x2
+#define SEQ04__SEQ_CHAIN__SHIFT                                                                               0x3
+#define SEQ04__SEQ_256K_MASK                                                                                  0x02L
+#define SEQ04__SEQ_ODDEVEN_MASK                                                                               0x04L
+#define SEQ04__SEQ_CHAIN_MASK                                                                                 0x08L
+
+
+// addressBlock: vga_vgacrtind
+//CRT00
+#define CRT00__H_TOTAL__SHIFT                                                                                 0x0
+#define CRT00__H_TOTAL_MASK                                                                                   0xFFL
+//CRT01
+#define CRT01__H_DISP_END__SHIFT                                                                              0x0
+#define CRT01__H_DISP_END_MASK                                                                                0xFFL
+//CRT02
+#define CRT02__H_BLANK_START__SHIFT                                                                           0x0
+#define CRT02__H_BLANK_START_MASK                                                                             0xFFL
+//CRT03
+#define CRT03__H_BLANK_END__SHIFT                                                                             0x0
+#define CRT03__H_DE_SKEW__SHIFT                                                                               0x5
+#define CRT03__CR10CR11_R_DIS_B__SHIFT                                                                        0x7
+#define CRT03__H_BLANK_END_MASK                                                                               0x1FL
+#define CRT03__H_DE_SKEW_MASK                                                                                 0x60L
+#define CRT03__CR10CR11_R_DIS_B_MASK                                                                          0x80L
+//CRT04
+#define CRT04__H_SYNC_START__SHIFT                                                                            0x0
+#define CRT04__H_SYNC_START_MASK                                                                              0xFFL
+//CRT05
+#define CRT05__H_SYNC_END__SHIFT                                                                              0x0
+#define CRT05__H_SYNC_SKEW__SHIFT                                                                             0x5
+#define CRT05__H_BLANK_END_B5__SHIFT                                                                          0x7
+#define CRT05__H_SYNC_END_MASK                                                                                0x1FL
+#define CRT05__H_SYNC_SKEW_MASK                                                                               0x60L
+#define CRT05__H_BLANK_END_B5_MASK                                                                            0x80L
+//CRT06
+#define CRT06__V_TOTAL__SHIFT                                                                                 0x0
+#define CRT06__V_TOTAL_MASK                                                                                   0xFFL
+//CRT07
+#define CRT07__V_TOTAL_B8__SHIFT                                                                              0x0
+#define CRT07__V_DISP_END_B8__SHIFT                                                                           0x1
+#define CRT07__V_SYNC_START_B8__SHIFT                                                                         0x2
+#define CRT07__V_BLANK_START_B8__SHIFT                                                                        0x3
+#define CRT07__LINE_CMP_B8__SHIFT                                                                             0x4
+#define CRT07__V_TOTAL_B9__SHIFT                                                                              0x5
+#define CRT07__V_DISP_END_B9__SHIFT                                                                           0x6
+#define CRT07__V_SYNC_START_B9__SHIFT                                                                         0x7
+#define CRT07__V_TOTAL_B8_MASK                                                                                0x01L
+#define CRT07__V_DISP_END_B8_MASK                                                                             0x02L
+#define CRT07__V_SYNC_START_B8_MASK                                                                           0x04L
+#define CRT07__V_BLANK_START_B8_MASK                                                                          0x08L
+#define CRT07__LINE_CMP_B8_MASK                                                                               0x10L
+#define CRT07__V_TOTAL_B9_MASK                                                                                0x20L
+#define CRT07__V_DISP_END_B9_MASK                                                                             0x40L
+#define CRT07__V_SYNC_START_B9_MASK                                                                           0x80L
+//CRT08
+#define CRT08__ROW_SCAN_START__SHIFT                                                                          0x0
+#define CRT08__BYTE_PAN__SHIFT                                                                                0x5
+#define CRT08__ROW_SCAN_START_MASK                                                                            0x1FL
+#define CRT08__BYTE_PAN_MASK                                                                                  0x60L
+//CRT09
+#define CRT09__MAX_ROW_SCAN__SHIFT                                                                            0x0
+#define CRT09__V_BLANK_START_B9__SHIFT                                                                        0x5
+#define CRT09__LINE_CMP_B9__SHIFT                                                                             0x6
+#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT                                                                      0x7
+#define CRT09__MAX_ROW_SCAN_MASK                                                                              0x1FL
+#define CRT09__V_BLANK_START_B9_MASK                                                                          0x20L
+#define CRT09__LINE_CMP_B9_MASK                                                                               0x40L
+#define CRT09__DOUBLE_CHAR_HEIGHT_MASK                                                                        0x80L
+//CRT0A
+#define CRT0A__CURSOR_START__SHIFT                                                                            0x0
+#define CRT0A__CURSOR_DISABLE__SHIFT                                                                          0x5
+#define CRT0A__CURSOR_START_MASK                                                                              0x1FL
+#define CRT0A__CURSOR_DISABLE_MASK                                                                            0x20L
+//CRT0B
+#define CRT0B__CURSOR_END__SHIFT                                                                              0x0
+#define CRT0B__CURSOR_SKEW__SHIFT                                                                             0x5
+#define CRT0B__CURSOR_END_MASK                                                                                0x1FL
+#define CRT0B__CURSOR_SKEW_MASK                                                                               0x60L
+//CRT0C
+#define CRT0C__DISP_START__SHIFT                                                                              0x0
+#define CRT0C__DISP_START_MASK                                                                                0xFFL
+//CRT0D
+#define CRT0D__DISP_START__SHIFT                                                                              0x0
+#define CRT0D__DISP_START_MASK                                                                                0xFFL
+//CRT0E
+#define CRT0E__CURSOR_LOC_HI__SHIFT                                                                           0x0
+#define CRT0E__CURSOR_LOC_HI_MASK                                                                             0xFFL
+//CRT0F
+#define CRT0F__CURSOR_LOC_LO__SHIFT                                                                           0x0
+#define CRT0F__CURSOR_LOC_LO_MASK                                                                             0xFFL
+//CRT10
+#define CRT10__V_SYNC_START__SHIFT                                                                            0x0
+#define CRT10__V_SYNC_START_MASK                                                                              0xFFL
+//CRT11
+#define CRT11__V_SYNC_END__SHIFT                                                                              0x0
+#define CRT11__V_INTR_CLR__SHIFT                                                                              0x4
+#define CRT11__V_INTR_EN__SHIFT                                                                               0x5
+#define CRT11__SEL5_REFRESH_CYC__SHIFT                                                                        0x6
+#define CRT11__C0T7_WR_ONLY__SHIFT                                                                            0x7
+#define CRT11__V_SYNC_END_MASK                                                                                0x0FL
+#define CRT11__V_INTR_CLR_MASK                                                                                0x10L
+#define CRT11__V_INTR_EN_MASK                                                                                 0x20L
+#define CRT11__SEL5_REFRESH_CYC_MASK                                                                          0x40L
+#define CRT11__C0T7_WR_ONLY_MASK                                                                              0x80L
+//CRT12
+#define CRT12__V_DISP_END__SHIFT                                                                              0x0
+#define CRT12__V_DISP_END_MASK                                                                                0xFFL
+//CRT13
+#define CRT13__DISP_PITCH__SHIFT                                                                              0x0
+#define CRT13__DISP_PITCH_MASK                                                                                0xFFL
+//CRT14
+#define CRT14__UNDRLN_LOC__SHIFT                                                                              0x0
+#define CRT14__ADDR_CNT_BY4__SHIFT                                                                            0x5
+#define CRT14__DOUBLE_WORD__SHIFT                                                                             0x6
+#define CRT14__UNDRLN_LOC_MASK                                                                                0x1FL
+#define CRT14__ADDR_CNT_BY4_MASK                                                                              0x20L
+#define CRT14__DOUBLE_WORD_MASK                                                                               0x40L
+//CRT15
+#define CRT15__V_BLANK_START__SHIFT                                                                           0x0
+#define CRT15__V_BLANK_START_MASK                                                                             0xFFL
+//CRT16
+#define CRT16__V_BLANK_END__SHIFT                                                                             0x0
+#define CRT16__V_BLANK_END_MASK                                                                               0xFFL
+//CRT17
+#define CRT17__RA0_AS_A13B__SHIFT                                                                             0x0
+#define CRT17__RA1_AS_A14B__SHIFT                                                                             0x1
+#define CRT17__VCOUNT_BY2__SHIFT                                                                              0x2
+#define CRT17__ADDR_CNT_BY2__SHIFT                                                                            0x3
+#define CRT17__WRAP_A15TOA0__SHIFT                                                                            0x5
+#define CRT17__BYTE_MODE__SHIFT                                                                               0x6
+#define CRT17__CRTC_SYNC_EN__SHIFT                                                                            0x7
+#define CRT17__RA0_AS_A13B_MASK                                                                               0x01L
+#define CRT17__RA1_AS_A14B_MASK                                                                               0x02L
+#define CRT17__VCOUNT_BY2_MASK                                                                                0x04L
+#define CRT17__ADDR_CNT_BY2_MASK                                                                              0x08L
+#define CRT17__WRAP_A15TOA0_MASK                                                                              0x20L
+#define CRT17__BYTE_MODE_MASK                                                                                 0x40L
+#define CRT17__CRTC_SYNC_EN_MASK                                                                              0x80L
+//CRT18
+#define CRT18__LINE_CMP__SHIFT                                                                                0x0
+#define CRT18__LINE_CMP_MASK                                                                                  0xFFL
+//CRT1E
+#define CRT1E__GRPH_DEC_RD1__SHIFT                                                                            0x1
+#define CRT1E__GRPH_DEC_RD1_MASK                                                                              0x02L
+//CRT1F
+#define CRT1F__GRPH_DEC_RD0__SHIFT                                                                            0x0
+#define CRT1F__GRPH_DEC_RD0_MASK                                                                              0xFFL
+//CRT22
+#define CRT22__GRPH_LATCH_DATA__SHIFT                                                                         0x0
+#define CRT22__GRPH_LATCH_DATA_MASK                                                                           0xFFL
+
+
+// addressBlock: vga_vgagrphind
+//GRA00
+#define GRA00__GRPH_SET_RESET0__SHIFT                                                                         0x0
+#define GRA00__GRPH_SET_RESET1__SHIFT                                                                         0x1
+#define GRA00__GRPH_SET_RESET2__SHIFT                                                                         0x2
+#define GRA00__GRPH_SET_RESET3__SHIFT                                                                         0x3
+#define GRA00__GRPH_SET_RESET0_MASK                                                                           0x01L
+#define GRA00__GRPH_SET_RESET1_MASK                                                                           0x02L
+#define GRA00__GRPH_SET_RESET2_MASK                                                                           0x04L
+#define GRA00__GRPH_SET_RESET3_MASK                                                                           0x08L
+//GRA01
+#define GRA01__GRPH_SET_RESET_ENA0__SHIFT                                                                     0x0
+#define GRA01__GRPH_SET_RESET_ENA1__SHIFT                                                                     0x1
+#define GRA01__GRPH_SET_RESET_ENA2__SHIFT                                                                     0x2
+#define GRA01__GRPH_SET_RESET_ENA3__SHIFT                                                                     0x3
+#define GRA01__GRPH_SET_RESET_ENA0_MASK                                                                       0x01L
+#define GRA01__GRPH_SET_RESET_ENA1_MASK                                                                       0x02L
+#define GRA01__GRPH_SET_RESET_ENA2_MASK                                                                       0x04L
+#define GRA01__GRPH_SET_RESET_ENA3_MASK                                                                       0x08L
+//GRA02
+#define GRA02__GRPH_CCOMP__SHIFT                                                                              0x0
+#define GRA02__GRPH_CCOMP_MASK                                                                                0x0FL
+//GRA03
+#define GRA03__GRPH_ROTATE__SHIFT                                                                             0x0
+#define GRA03__GRPH_FN_SEL__SHIFT                                                                             0x3
+#define GRA03__GRPH_ROTATE_MASK                                                                               0x07L
+#define GRA03__GRPH_FN_SEL_MASK                                                                               0x18L
+//GRA04
+#define GRA04__GRPH_RMAP__SHIFT                                                                               0x0
+#define GRA04__GRPH_RMAP_MASK                                                                                 0x03L
+//GRA05
+#define GRA05__GRPH_WRITE_MODE__SHIFT                                                                         0x0
+#define GRA05__GRPH_READ1__SHIFT                                                                              0x3
+#define GRA05__CGA_ODDEVEN__SHIFT                                                                             0x4
+#define GRA05__GRPH_OES__SHIFT                                                                                0x5
+#define GRA05__GRPH_PACK__SHIFT                                                                               0x6
+#define GRA05__GRPH_WRITE_MODE_MASK                                                                           0x03L
+#define GRA05__GRPH_READ1_MASK                                                                                0x08L
+#define GRA05__CGA_ODDEVEN_MASK                                                                               0x10L
+#define GRA05__GRPH_OES_MASK                                                                                  0x20L
+#define GRA05__GRPH_PACK_MASK                                                                                 0x40L
+//GRA06
+#define GRA06__GRPH_GRAPHICS__SHIFT                                                                           0x0
+#define GRA06__GRPH_ODDEVEN__SHIFT                                                                            0x1
+#define GRA06__GRPH_ADRSEL__SHIFT                                                                             0x2
+#define GRA06__GRPH_GRAPHICS_MASK                                                                             0x01L
+#define GRA06__GRPH_ODDEVEN_MASK                                                                              0x02L
+#define GRA06__GRPH_ADRSEL_MASK                                                                               0x0CL
+//GRA07
+#define GRA07__GRPH_XCARE0__SHIFT                                                                             0x0
+#define GRA07__GRPH_XCARE1__SHIFT                                                                             0x1
+#define GRA07__GRPH_XCARE2__SHIFT                                                                             0x2
+#define GRA07__GRPH_XCARE3__SHIFT                                                                             0x3
+#define GRA07__GRPH_XCARE0_MASK                                                                               0x01L
+#define GRA07__GRPH_XCARE1_MASK                                                                               0x02L
+#define GRA07__GRPH_XCARE2_MASK                                                                               0x04L
+#define GRA07__GRPH_XCARE3_MASK                                                                               0x08L
+//GRA08
+#define GRA08__GRPH_BMSK__SHIFT                                                                               0x0
+#define GRA08__GRPH_BMSK_MASK                                                                                 0xFFL
+
+
+// addressBlock: vga_vgaattrind
+//ATTR00
+#define ATTR00__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR00__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR01
+#define ATTR01__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR01__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR02
+#define ATTR02__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR02__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR03
+#define ATTR03__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR03__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR04
+#define ATTR04__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR04__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR05
+#define ATTR05__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR05__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR06
+#define ATTR06__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR06__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR07
+#define ATTR07__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR07__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR08
+#define ATTR08__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR08__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR09
+#define ATTR09__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR09__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0A
+#define ATTR0A__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0A__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0B
+#define ATTR0B__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0B__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0C
+#define ATTR0C__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0C__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0D
+#define ATTR0D__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0D__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0E
+#define ATTR0E__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0E__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0F
+#define ATTR0F__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0F__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR10
+#define ATTR10__ATTR_GRPH_MODE__SHIFT                                                                         0x0
+#define ATTR10__ATTR_MONO_EN__SHIFT                                                                           0x1
+#define ATTR10__ATTR_LGRPH_EN__SHIFT                                                                          0x2
+#define ATTR10__ATTR_BLINK_EN__SHIFT                                                                          0x3
+#define ATTR10__ATTR_PANTOPONLY__SHIFT                                                                        0x5
+#define ATTR10__ATTR_PCLKBY2__SHIFT                                                                           0x6
+#define ATTR10__ATTR_CSEL_EN__SHIFT                                                                           0x7
+#define ATTR10__ATTR_GRPH_MODE_MASK                                                                           0x01L
+#define ATTR10__ATTR_MONO_EN_MASK                                                                             0x02L
+#define ATTR10__ATTR_LGRPH_EN_MASK                                                                            0x04L
+#define ATTR10__ATTR_BLINK_EN_MASK                                                                            0x08L
+#define ATTR10__ATTR_PANTOPONLY_MASK                                                                          0x20L
+#define ATTR10__ATTR_PCLKBY2_MASK                                                                             0x40L
+#define ATTR10__ATTR_CSEL_EN_MASK                                                                             0x80L
+//ATTR11
+#define ATTR11__ATTR_OVSC__SHIFT                                                                              0x0
+#define ATTR11__ATTR_OVSC_MASK                                                                                0xFFL
+//ATTR12
+#define ATTR12__ATTR_MAP_EN__SHIFT                                                                            0x0
+#define ATTR12__ATTR_VSMUX__SHIFT                                                                             0x4
+#define ATTR12__ATTR_MAP_EN_MASK                                                                              0x0FL
+#define ATTR12__ATTR_VSMUX_MASK                                                                               0x30L
+//ATTR13
+#define ATTR13__ATTR_PPAN__SHIFT                                                                              0x0
+#define ATTR13__ATTR_PPAN_MASK                                                                                0x0FL
+//ATTR14
+#define ATTR14__ATTR_CSEL1__SHIFT                                                                             0x0
+#define ATTR14__ATTR_CSEL2__SHIFT                                                                             0x2
+#define ATTR14__ATTR_CSEL1_MASK                                                                               0x03L
+#define ATTR14__ATTR_CSEL2_MASK                                                                               0x0CL
+
+
+// addressBlock: azendpoint_f2codecind
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                         0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                            0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                        0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                       0xb
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                           0xe
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                                0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT                              0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                           0x0000000FL
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                              0x00000070L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                          0x00000700L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                         0x00003800L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                             0x00004000L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                                  0x00008000L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK                                0x00008000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                                0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                                 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                                  0x0000000FL
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                                   0x000000F0L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                         0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                      0x2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                       0x3
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                      0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                                 0x5
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                       0x6
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                         0x7
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                        0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                                 0x17
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                       0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                           0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                        0x00000004L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                         0x00000008L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                        0x00000010L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                                   0x00000020L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                         0x00000040L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                           0x00000080L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                          0x00007F00L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                                   0x00800000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT                                      0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK                                        0x0000007FL
+//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                                       0x0
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                                    0x14
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                                         0x00000003L
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                                      0x00700000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT                               0x7
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK                                 0x00000080L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                                         0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                                           0x000000FFL
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT            0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT              0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT             0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK              0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK                0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK               0x00000070L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT                 0x4
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK                   0x00000010L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT              0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT               0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                0x00000FFFL
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                 0x001F0000L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                             0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                               0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT              0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK                0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                                         0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                                           0x00000040L
+//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                          0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                       0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                            0x0000003FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                         0x00000080L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                                0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                                0x1f
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                                  0x7FFFFFFFL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                                  0x80000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                           0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT                0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                               0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                              0xc
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT                    0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT                     0x14
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                           0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT                  0x1e
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                             0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK                  0x000000F0L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                                 0x00000F00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                                0x0000F000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                      0x000F0000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                       0x00F00000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                             0x3F000000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK                    0xC0000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                            0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                               0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                              0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT                  0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK                    0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT                0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                           0x0000003FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK                  0x000000C0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT                       0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT                         0x9
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT                 0xa
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK                      0x0000007FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK                         0x00000100L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK                           0x00000200L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK                   0x0000FC00L
+//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                               0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT                                  0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT                                         0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT                                    0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK                                    0x00000003L
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK                                           0x00000078L
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK                                      0x00000080L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT                                      0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT                            0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT                                0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT                     0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK                                       0x00000007L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK                                        0x00000078L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK                              0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK                                  0x00FF0000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK                       0xFF000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT                                  0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK                                    0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT                                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT                                             0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK                                               0x000000FFL
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK                                               0x0000FF00L
+//AZALIA_F2_CODEC_PIN_CONTROL_HBR
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                                   0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                                    0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                                     0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                      0x00000010L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK                               0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT                                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK                                      0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                               0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                                 0x00000001L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                                   0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT                          0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                                     0x00000003L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK                            0x0000003CL
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT                         0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT                0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT                            0x3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT                   0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK                           0x00000003L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK                  0x00000004L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                              0x00000078L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK                     0x00000080L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT                     0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT            0x6
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK                       0x0000003FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK              0x00000040L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT            0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT   0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK              0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK     0x00000010L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT               0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT                     0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                                 0x5
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT                           0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK                 0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK                       0x00000010L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                                   0x00000060L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK                             0x00000080L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK                         0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK                         0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK                         0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK                         0x000000F0L
+//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                                         0x0
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                                           0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                               0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                                 0x00000001L
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                          0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT                    0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                            0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                      0x0000FF00L
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                                           0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                           0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                             0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                                           0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                                             0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT                       0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                               0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT                             0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                                       0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK                         0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                                 0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                               0x00FF0000L
+//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT   0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK     0x00000003L
+//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK                       0x00000010L
+//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT            0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT               0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT              0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT          0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                                0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT                     0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT       0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                       0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                               0x9
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                         0xa
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                               0xb
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT       0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                                  0x14
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK              0x00000001L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK                 0x00000002L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK                0x00000004L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK            0x00000008L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                                  0x00000020L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                       0x00000040L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK         0x00000080L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                         0x00000100L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                                 0x00000200L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                           0x00000400L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                                 0x00000800L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK         0x000F0000L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                                    0x00F00000L
+//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                            0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                                   0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                          0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                            0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                                     0x4
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                      0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                                  0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                               0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                       0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                       0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                                 0x18
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                              0x00000001L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                                     0x00000002L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                            0x00000004L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                              0x00000008L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                       0x00000010L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                        0x00000020L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                                    0x00000040L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                                 0x00000080L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                         0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                         0x00010000L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                                   0x01000000L
+//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT                   0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azendpoint_descriptorind
+//AUDIO_DESCRIPTOR0
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR1
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR2
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR3
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR4
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR5
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR6
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR7
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR8
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR9
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR10
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+//AUDIO_DESCRIPTOR11
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+//AUDIO_DESCRIPTOR12
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+//AUDIO_DESCRIPTOR13
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+
+
+// addressBlock: azendpoint_sinkinfoind
+//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT                                   0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK                                     0x0000FFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT                                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK                                               0x0000FFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK                           0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT                                                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK                                                      0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT                                                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK                                                      0xFFFFFFFFL
+//SINK_DESCRIPTION0
+#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION0__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION1
+#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION1__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION2
+#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION2__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION3
+#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION3__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION4
+#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION4__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION5
+#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION5__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION6
+#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION6__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION7
+#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION7__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION8
+#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION8__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION9
+#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION9__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION10
+#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION10__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION11
+#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION11__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION12
+#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION12__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION13
+#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION13__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION14
+#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION14__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION15
+#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION15__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION16
+#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION16__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION17
+#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION17__DESCRIPTION_MASK                                                                  0x000000FFL
+
+
+// addressBlock: azf0controller_azinputcrc0resultind
+//AZALIA_INPUT_CRC0_CHANNEL0
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL1
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL2
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL3
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL4
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL5
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL6
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL7
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azinputcrc1resultind
+//AZALIA_INPUT_CRC1_CHANNEL0
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL1
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL2
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL3
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL4
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL5
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL6
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL7
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azcrc0resultind
+//AZALIA_CRC0_CHANNEL0
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL1
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL2
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL3
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL4
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL5
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL6
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL7
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azcrc1resultind
+//AZALIA_CRC1_CHANNEL0
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL1
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL2
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL3
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL4
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL5
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL6
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL7
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: azinputendpoint_f2codecind
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                      0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                  0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                 0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                     0xe
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                          0xf
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                     0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                        0x00000070L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                    0x00000700L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                   0x00003800L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                       0x00004000L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                            0x00008000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                          0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                           0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                            0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                             0x000000F0L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                               0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                   0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                 0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                           0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                 0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                   0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                  0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                           0x17
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                     0x00000002L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                  0x00000004L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                   0x00000008L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                  0x00000010L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                             0x00000020L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                   0x00000040L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                     0x00000080L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                    0x00007F00L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                             0x00800000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT   0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT           0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                    0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT         0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT           0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                   0x9
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT             0xa
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                   0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                      0x14
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK     0x00000002L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK    0x00000004L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK             0x00000010L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                      0x00000020L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK           0x00000040L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK             0x00000100L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                     0x00000200L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK               0x00000400L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                     0x00000800L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                        0x00F00000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT        0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT         0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK          0x00000FFFL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK           0x001F0000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                       0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                         0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                                    0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                                      0x00000020L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                    0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                 0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                      0x0000003FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                   0x00000080L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                          0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                          0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                            0x7FFFFFFFL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                            0x80000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                     0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT          0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                         0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                        0xc
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT              0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT               0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                     0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT            0x1e
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                       0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK            0x000000F0L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                           0x00000F00L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                          0x0000F000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                 0x00F00000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                       0x3F000000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK              0xC0000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                       0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                      0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                         0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                        0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT            0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT             0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK              0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK               0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT          0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                     0x0000003FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK            0x000000C0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                       0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                         0x000000FFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                             0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                              0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                               0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                0x00000010L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                    0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT              0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                      0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                0x0000FF00L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                                     0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                     0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                       0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT                         0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT                         0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK                           0x00000006L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK                 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK   0x00000020L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT                                0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT                                  0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                                   0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                                       0x00000007L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK                                  0x0000FF00L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                                    0x00FF0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                                     0x80000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT                           0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK                             0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT                           0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK                             0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L
+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                      0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                             0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                    0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                      0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                            0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                         0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                           0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                        0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                               0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                      0x00000004L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                        0x00000008L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                  0x00000020L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                              0x00000040L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                           0x00000080L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                   0x0000FF00L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                   0x00010000L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                                             0x01000000L
+
+
+// addressBlock: azroot_f2codecind
+//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL
+//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT                   0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK                     0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT                   0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK                     0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT                   0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK                     0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L
+
+
+// addressBlock: azf0stream0_streamind
+//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream1_streamind
+//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream2_streamind
+//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream3_streamind
+//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream4_streamind
+//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream5_streamind
+//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream6_streamind
+//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream7_streamind
+//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream8_streamind
+//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream9_streamind
+//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream10_streamind
+//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream11_streamind
+//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream12_streamind
+//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream13_streamind
+//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream14_streamind
+//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream15_streamind
+//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0endpoint0_endpointind
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint1_endpointind
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint2_endpointind
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint3_endpointind
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint4_endpointind
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint5_endpointind
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint6_endpointind
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint7_endpointind
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0inputendpoint0_inputendpointind
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint1_inputendpointind
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint2_inputendpointind
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint3_inputendpointind
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint4_inputendpointind
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint5_inputendpointind
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint6_inputendpointind
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint7_inputendpointind
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+#endif
-- 
GitLab


From ac2e555e0a7fe571d46f7dcb1529b4bee00095d6 Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Mon, 21 Feb 2022 16:03:58 -0500
Subject: [PATCH 0151/1731] drm/amd/display: Add DMCUB source files and changes
 for DCN32/321

DMCUB is the display engine microcontroller which aids in modesetting
and other display related features.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c  |  31 ++
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h  |   2 +
 drivers/gpu/drm/amd/display/dmub/dmub_srv.h   |   6 +
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |  26 +-
 drivers/gpu/drm/amd/display/dmub/src/Makefile |   1 +
 .../gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 488 ++++++++++++++++++
 .../gpu/drm/amd/display/dmub/src/dmub_dcn32.h | 256 +++++++++
 .../gpu/drm/amd/display/dmub/src/dmub_srv.c   |  51 +-
 8 files changed, 859 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
 create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 541376fabbef1..11597bca966ab 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -250,6 +250,37 @@ void dc_dmub_trace_event_control(struct dc *dc, bool enable)
 	dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable);
 }
 
+void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub)
+{
+	union dmub_rb_cmd cmd = { 0 };
+	enum dmub_status status;
+
+	if (!dmub) {
+		return;
+	}
+
+	memset(&cmd, 0, sizeof(cmd));
+
+	/* Prepare fw command */
+	cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS;
+	cmd.query_feature_caps.header.sub_type = 0;
+	cmd.query_feature_caps.header.ret_status = 1;
+	cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data);
+
+	/* Send command to fw */
+	status = dmub_srv_cmd_with_reply_data(dmub, &cmd);
+
+	ASSERT(status == DMUB_STATUS_OK);
+
+	/* If command was processed, copy feature caps to dmub srv */
+	if (status == DMUB_STATUS_OK &&
+	    cmd.query_feature_caps.header.ret_status == 0) {
+		memcpy(&dmub->feature_caps,
+		       &cmd.query_feature_caps.query_feature_caps_data,
+		       sizeof(struct dmub_feature_caps));
+	}
+}
+
 bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data)
 {
 	if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
index 7e4e2ec5915d2..50e44b53f14c2 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
@@ -68,6 +68,8 @@ bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_bu
 
 void dc_dmub_trace_event_control(struct dc *dc, bool enable);
 
+void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub);
+
 void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv);
 void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv);
 void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_data_register data);
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 7dbc9fb554595..04049dc5d9dfb 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -246,6 +246,7 @@ struct dmub_srv_hw_params {
 	bool dpia_supported;
 	bool disable_dpia;
 	bool usb4_cm_version;
+	bool fw_in_system_memory;
 };
 
 /**
@@ -310,6 +311,9 @@ struct dmub_srv_hw_funcs {
 			      const struct dmub_window *cw0,
 			      const struct dmub_window *cw1);
 
+	void (*backdoor_load_zfb_mode)(struct dmub_srv *dmub,
+			      const struct dmub_window *cw0,
+			      const struct dmub_window *cw1);
 	void (*setup_windows)(struct dmub_srv *dmub,
 			      const struct dmub_window *cw2,
 			      const struct dmub_window *cw3,
@@ -365,6 +369,7 @@ struct dmub_srv_hw_funcs {
 
 	uint32_t (*get_gpint_dataout)(struct dmub_srv *dmub);
 
+	void (*configure_dmub_in_system_memory)(struct dmub_srv *dmub);
 	void (*clear_inbox0_ack_register)(struct dmub_srv *dmub);
 	uint32_t (*read_inbox0_ack_register)(struct dmub_srv *dmub);
 	void (*send_inbox0_cmd)(struct dmub_srv *dmub, union dmub_inbox0_data_register data);
@@ -412,6 +417,7 @@ struct dmub_srv {
 	/* private: internal use only */
 	const struct dmub_srv_common_regs *regs;
 	const struct dmub_srv_dcn31_regs *regs_dcn31;
+	const struct dmub_srv_dcn32_regs *regs_dcn32;
 
 	struct dmub_srv_base_funcs funcs;
 	struct dmub_srv_hw_funcs hw_funcs;
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 385c28238beb1..8fc1846f07087 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -641,7 +641,10 @@ enum dmub_cmd_type {
 	 * Command type used for all panel control commands.
 	 */
 	DMUB_CMD__PANEL_CNTL = 74,
-
+	/**
+	 * Command type used for <TODO:description>
+	 */
+	DMUB_CMD__CAB_FOR_SS = 75,
 	/**
 	 * Command type used for interfacing with DPIA.
 	 */
@@ -878,6 +881,23 @@ struct dmub_rb_cmd_mall {
 	uint8_t reserved2; /**< Reserved bits */
 };
 
+/**
+ * enum dmub_cmd_cab_type - TODO:
+ */
+enum dmub_cmd_cab_type {
+	DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0,
+	DMUB_CMD__CAB_NO_DCN_REQ = 1,
+	DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2,
+};
+
+/**
+ * struct dmub_rb_cmd_cab_for_ss - TODO:
+ */
+struct dmub_rb_cmd_cab_for_ss {
+	struct dmub_cmd_header header;
+	uint8_t cab_alloc_ways; /* total number of ways */
+	uint8_t debug_bits;     /* debug bits */
+};
 /**
  * enum dmub_cmd_idle_opt_type - Idle optimization command type.
  */
@@ -2693,6 +2713,10 @@ union dmub_rb_cmd {
 	 * Definition of a DMUB_CMD__MALL command.
 	 */
 	struct dmub_rb_cmd_mall mall;
+	/**
+	 * Definition of a DMUB_CMD__CAB command.
+	 */
+	struct dmub_rb_cmd_cab_for_ss cab;
 	/**
 	 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.
 	 */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/Makefile b/drivers/gpu/drm/amd/display/dmub/src/Makefile
index 856c7f48de7a9..0589ad4778eea 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/Makefile
+++ b/drivers/gpu/drm/amd/display/dmub/src/Makefile
@@ -23,6 +23,7 @@
 DMUB = dmub_srv.o dmub_srv_stat.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o
 DMUB += dmub_dcn30.o dmub_dcn301.o dmub_dcn302.o dmub_dcn303.o
 DMUB += dmub_dcn31.o dmub_dcn315.o dmub_dcn316.o
+DMUB += dmub_dcn32.o
 
 AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB))
 
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
new file mode 100644
index 0000000000000..0a498082ccc6b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
@@ -0,0 +1,488 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "../dmub_srv.h"
+#include "dmub_reg.h"
+#include "dmub_dcn32.h"
+
+#include "dcn/dcn_3_2_0_offset.h"
+#include "dcn/dcn_3_2_0_sh_mask.h"
+
+#define DCN_BASE__INST0_SEG2                       0x000034C0
+
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
+#define CTX dmub
+#define REGS dmub->regs_dcn32
+#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
+
+const struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs = {
+#define DMUB_SR(reg) REG_OFFSET_EXP(reg),
+		{ DMUB_DCN32_REGS() },
+#undef DMUB_SR
+
+#define DMUB_SF(reg, field) FD_MASK(reg, field),
+		{ DMUB_DCN32_FIELDS() },
+#undef DMUB_SF
+
+#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
+		{ DMUB_DCN32_FIELDS() },
+#undef DMUB_SF
+};
+
+static void dmub_dcn32_get_fb_base_offset(struct dmub_srv *dmub,
+		uint64_t *fb_base,
+		uint64_t *fb_offset)
+{
+	uint32_t tmp;
+
+	if (dmub->fb_base || dmub->fb_offset) {
+		*fb_base = dmub->fb_base;
+		*fb_offset = dmub->fb_offset;
+		return;
+	}
+
+	REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
+	*fb_base = (uint64_t)tmp << 24;
+
+	REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
+	*fb_offset = (uint64_t)tmp << 24;
+}
+
+static inline void dmub_dcn32_translate_addr(const union dmub_addr *addr_in,
+		uint64_t fb_base,
+		uint64_t fb_offset,
+		union dmub_addr *addr_out)
+{
+	addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
+}
+
+void dmub_dcn32_reset(struct dmub_srv *dmub)
+{
+	union dmub_gpint_data_register cmd;
+	const uint32_t timeout = 30;
+	uint32_t in_reset, scratch, i;
+
+	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
+
+	if (in_reset == 0) {
+		cmd.bits.status = 1;
+		cmd.bits.command_code = DMUB_GPINT__STOP_FW;
+		cmd.bits.param = 0;
+
+		dmub->hw_funcs.set_gpint(dmub, cmd);
+
+		/**
+		 * Timeout covers both the ACK and the wait
+		 * for remaining work to finish.
+		 *
+		 * This is mostly bound by the PHY disable sequence.
+		 * Each register check will be greater than 1us, so
+		 * don't bother using udelay.
+		 */
+
+		for (i = 0; i < timeout; ++i) {
+			if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
+				break;
+		}
+
+		for (i = 0; i < timeout; ++i) {
+			scratch = dmub->hw_funcs.get_gpint_response(dmub);
+			if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
+				break;
+		}
+
+		/* Clear the GPINT command manually so we don't reset again. */
+		cmd.all = 0;
+		dmub->hw_funcs.set_gpint(dmub, cmd);
+
+		/* Force reset in case we timed out, DMCUB is likely hung. */
+	}
+
+	REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);
+	REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
+	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
+	REG_WRITE(DMCUB_INBOX1_RPTR, 0);
+	REG_WRITE(DMCUB_INBOX1_WPTR, 0);
+	REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
+	REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
+	REG_WRITE(DMCUB_SCRATCH0, 0);
+}
+
+void dmub_dcn32_reset_release(struct dmub_srv *dmub)
+{
+	REG_WRITE(DMCUB_GPINT_DATAIN1, 0);
+	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
+	REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
+	REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
+	REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);
+}
+
+void dmub_dcn32_backdoor_load(struct dmub_srv *dmub,
+		const struct dmub_window *cw0,
+		const struct dmub_window *cw1)
+{
+	union dmub_addr offset;
+	uint64_t fb_base, fb_offset;
+
+	dmub_dcn32_get_fb_base_offset(dmub, &fb_base, &fb_offset);
+
+	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
+
+	dmub_dcn32_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
+
+	REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
+	REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
+			DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
+			DMCUB_REGION3_CW0_ENABLE, 1);
+
+	dmub_dcn32_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
+
+	REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
+	REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
+			DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
+			DMCUB_REGION3_CW1_ENABLE, 1);
+
+	REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
+			0x20);
+}
+
+void dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub,
+		      const struct dmub_window *cw0,
+		      const struct dmub_window *cw1)
+{
+	union dmub_addr offset;
+
+	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
+
+	offset = cw0->offset;
+
+	REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
+	REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
+			DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
+			DMCUB_REGION3_CW0_ENABLE, 1);
+
+	offset = cw1->offset;
+
+	REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
+	REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
+			DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
+			DMCUB_REGION3_CW1_ENABLE, 1);
+
+	REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
+			0x20);
+}
+
+void dmub_dcn32_setup_windows(struct dmub_srv *dmub,
+		const struct dmub_window *cw2,
+		const struct dmub_window *cw3,
+		const struct dmub_window *cw4,
+		const struct dmub_window *cw5,
+		const struct dmub_window *cw6)
+{
+	union dmub_addr offset;
+
+	offset = cw3->offset;
+
+	REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
+	REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
+			DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
+			DMCUB_REGION3_CW3_ENABLE, 1);
+
+	offset = cw4->offset;
+
+	REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
+	REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
+			DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
+			DMCUB_REGION3_CW4_ENABLE, 1);
+
+	offset = cw5->offset;
+
+	REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
+	REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
+			DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
+			DMCUB_REGION3_CW5_ENABLE, 1);
+
+	REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
+	REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
+			DMCUB_REGION5_TOP_ADDRESS,
+			cw5->region.top - cw5->region.base - 1,
+			DMCUB_REGION5_ENABLE, 1);
+
+	offset = cw6->offset;
+
+	REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
+	REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
+			DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
+			DMCUB_REGION3_CW6_ENABLE, 1);
+}
+
+void dmub_dcn32_setup_mailbox(struct dmub_srv *dmub,
+		const struct dmub_region *inbox1)
+{
+	REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
+	REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
+}
+
+uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub)
+{
+	return REG_READ(DMCUB_INBOX1_RPTR);
+}
+
+void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
+{
+	REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
+}
+
+void dmub_dcn32_setup_out_mailbox(struct dmub_srv *dmub,
+		const struct dmub_region *outbox1)
+{
+	REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
+	REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
+}
+
+uint32_t dmub_dcn32_get_outbox1_wptr(struct dmub_srv *dmub)
+{
+	/**
+	 * outbox1 wptr register is accessed without locks (dal & dc)
+	 * and to be called only by dmub_srv_stat_get_notification()
+	 */
+	return REG_READ(DMCUB_OUTBOX1_WPTR);
+}
+
+void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
+{
+	/**
+	 * outbox1 rptr register is accessed without locks (dal & dc)
+	 * and to be called only by dmub_srv_stat_get_notification()
+	 */
+	REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
+}
+
+bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub)
+{
+	uint32_t is_hw_init;
+
+	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
+
+	return is_hw_init != 0;
+}
+
+bool dmub_dcn32_is_supported(struct dmub_srv *dmub)
+{
+	uint32_t supported = 0;
+
+	REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
+
+	return supported;
+}
+
+void dmub_dcn32_set_gpint(struct dmub_srv *dmub,
+		union dmub_gpint_data_register reg)
+{
+	REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
+}
+
+bool dmub_dcn32_is_gpint_acked(struct dmub_srv *dmub,
+		union dmub_gpint_data_register reg)
+{
+	union dmub_gpint_data_register test;
+
+	reg.bits.status = 0;
+	test.all = REG_READ(DMCUB_GPINT_DATAIN1);
+
+	return test.all == reg.all;
+}
+
+uint32_t dmub_dcn32_get_gpint_response(struct dmub_srv *dmub)
+{
+	return REG_READ(DMCUB_SCRATCH7);
+}
+
+uint32_t dmub_dcn32_get_gpint_dataout(struct dmub_srv *dmub)
+{
+	uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);
+
+	REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);
+
+	REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
+	REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);
+	REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);
+
+	REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);
+
+	return dataout;
+}
+
+union dmub_fw_boot_status dmub_dcn32_get_fw_boot_status(struct dmub_srv *dmub)
+{
+	union dmub_fw_boot_status status;
+
+	status.all = REG_READ(DMCUB_SCRATCH0);
+	return status;
+}
+
+void dmub_dcn32_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
+{
+	union dmub_fw_boot_options boot_options = {0};
+
+	boot_options.bits.z10_disable = params->disable_z10;
+
+	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
+}
+
+void dmub_dcn32_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
+{
+	union dmub_fw_boot_options boot_options;
+	boot_options.all = REG_READ(DMCUB_SCRATCH14);
+	boot_options.bits.skip_phy_init_panel_sequence = skip;
+	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
+}
+
+void dmub_dcn32_setup_outbox0(struct dmub_srv *dmub,
+		const struct dmub_region *outbox0)
+{
+	REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
+
+	REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
+}
+
+uint32_t dmub_dcn32_get_outbox0_wptr(struct dmub_srv *dmub)
+{
+	return REG_READ(DMCUB_OUTBOX0_WPTR);
+}
+
+void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
+{
+	REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
+}
+
+uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub)
+{
+	return REG_READ(DMCUB_TIMER_CURRENT);
+}
+
+void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
+{
+	uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;
+	uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
+
+	if (!dmub || !diag_data)
+		return;
+
+	memset(diag_data, 0, sizeof(*diag_data));
+
+	diag_data->dmcub_version = dmub->fw_version;
+
+	diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0);
+	diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1);
+	diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2);
+	diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3);
+	diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4);
+	diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5);
+	diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6);
+	diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7);
+	diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8);
+	diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9);
+	diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10);
+	diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11);
+	diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12);
+	diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13);
+	diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14);
+	diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15);
+
+	diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
+	diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
+	diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
+
+	diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
+	diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
+	diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
+
+	diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
+	diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
+	diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
+
+	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
+	diag_data->is_dmcub_enabled = is_dmub_enabled;
+
+	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
+	diag_data->is_dmcub_soft_reset = is_soft_reset;
+
+	REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
+	diag_data->is_dmcub_secure_reset = is_sec_reset;
+
+	REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
+	diag_data->is_traceport_en  = is_traceport_enabled;
+
+	REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
+	diag_data->is_cw0_enabled = is_cw0_enabled;
+
+	REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
+	diag_data->is_cw6_enabled = is_cw6_enabled;
+}
+void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub)
+{
+	/* DMCUB_REGION3_TMR_AXI_SPACE values:
+	 * 0b011 (0x3) - FB physical address
+	 * 0b100 (0x4) - GPU virtual address
+	 *
+	 * Default value is 0x3 (FB Physical address for TMR). When programming
+	 * DMUB to be in system memory, change to 0x4. The system memory allocated
+	 * is accessible by both GPU and CPU, so we use GPU virtual address.
+	 */
+	REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4);
+}
+
+void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)
+{
+	REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all);
+}
+
+void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub)
+{
+	REG_WRITE(DMCUB_SCRATCH17, 0);
+}
+
+uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub)
+{
+	return REG_READ(DMCUB_SCRATCH17);
+}
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h
new file mode 100644
index 0000000000000..7d1a6eb4d6657
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h
@@ -0,0 +1,256 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DMUB_DCN32_H_
+#define _DMUB_DCN32_H_
+
+#include "dmub_dcn31.h"
+
+struct dmub_srv;
+
+/* DCN32 register definitions. */
+
+#define DMUB_DCN32_REGS() \
+	DMUB_SR(DMCUB_CNTL) \
+	DMUB_SR(DMCUB_CNTL2) \
+	DMUB_SR(DMCUB_SEC_CNTL) \
+	DMUB_SR(DMCUB_INBOX0_SIZE) \
+	DMUB_SR(DMCUB_INBOX0_RPTR) \
+	DMUB_SR(DMCUB_INBOX0_WPTR) \
+	DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_INBOX1_SIZE) \
+	DMUB_SR(DMCUB_INBOX1_RPTR) \
+	DMUB_SR(DMCUB_INBOX1_WPTR) \
+	DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_OUTBOX0_SIZE) \
+	DMUB_SR(DMCUB_OUTBOX0_RPTR) \
+	DMUB_SR(DMCUB_OUTBOX0_WPTR) \
+	DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_OUTBOX1_SIZE) \
+	DMUB_SR(DMCUB_OUTBOX1_RPTR) \
+	DMUB_SR(DMCUB_OUTBOX1_WPTR) \
+	DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION4_OFFSET) \
+	DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION5_OFFSET) \
+	DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_SCRATCH0) \
+	DMUB_SR(DMCUB_SCRATCH1) \
+	DMUB_SR(DMCUB_SCRATCH2) \
+	DMUB_SR(DMCUB_SCRATCH3) \
+	DMUB_SR(DMCUB_SCRATCH4) \
+	DMUB_SR(DMCUB_SCRATCH5) \
+	DMUB_SR(DMCUB_SCRATCH6) \
+	DMUB_SR(DMCUB_SCRATCH7) \
+	DMUB_SR(DMCUB_SCRATCH8) \
+	DMUB_SR(DMCUB_SCRATCH9) \
+	DMUB_SR(DMCUB_SCRATCH10) \
+	DMUB_SR(DMCUB_SCRATCH11) \
+	DMUB_SR(DMCUB_SCRATCH12) \
+	DMUB_SR(DMCUB_SCRATCH13) \
+	DMUB_SR(DMCUB_SCRATCH14) \
+	DMUB_SR(DMCUB_SCRATCH15) \
+	DMUB_SR(DMCUB_SCRATCH16) \
+	DMUB_SR(DMCUB_SCRATCH17) \
+	DMUB_SR(DMCUB_GPINT_DATAIN1) \
+	DMUB_SR(DMCUB_GPINT_DATAOUT) \
+	DMUB_SR(CC_DC_PIPE_DIS) \
+	DMUB_SR(MMHUBBUB_SOFT_RESET) \
+	DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
+	DMUB_SR(DCN_VM_FB_OFFSET) \
+	DMUB_SR(DMCUB_TIMER_CURRENT) \
+	DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \
+	DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \
+	DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR) \
+	DMUB_SR(DMCUB_REGION3_TMR_AXI_SPACE) \
+	DMUB_SR(DMCUB_INTERRUPT_ENABLE) \
+	DMUB_SR(DMCUB_INTERRUPT_ACK)
+
+#define DMUB_DCN32_FIELDS() \
+	DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
+	DMUB_SF(DMCUB_CNTL, DMCUB_TRACEPORT_EN) \
+	DMUB_SF(DMCUB_CNTL2, DMCUB_SOFT_RESET) \
+	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \
+	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \
+	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS) \
+	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \
+	DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \
+	DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \
+	DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \
+	DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \
+	DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \
+	DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) \
+	DMUB_SF(DMCUB_INBOX0_WPTR, DMCUB_INBOX0_WPTR) \
+	DMUB_SF(DMCUB_REGION3_TMR_AXI_SPACE, DMCUB_REGION3_TMR_AXI_SPACE) \
+	DMUB_SF(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN) \
+	DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK)
+
+struct dmub_srv_dcn32_reg_offset {
+#define DMUB_SR(reg) uint32_t reg;
+	DMUB_DCN32_REGS()
+	DMCUB_INTERNAL_REGS()
+#undef DMUB_SR
+};
+
+struct dmub_srv_dcn32_reg_shift {
+#define DMUB_SF(reg, field) uint8_t reg##__##field;
+	DMUB_DCN32_FIELDS()
+#undef DMUB_SF
+};
+
+struct dmub_srv_dcn32_reg_mask {
+#define DMUB_SF(reg, field) uint32_t reg##__##field;
+	DMUB_DCN32_FIELDS()
+#undef DMUB_SF
+};
+
+struct dmub_srv_dcn32_regs {
+	const struct dmub_srv_dcn32_reg_offset offset;
+	const struct dmub_srv_dcn32_reg_mask mask;
+	const struct dmub_srv_dcn32_reg_shift shift;
+};
+
+extern const struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs;
+
+void dmub_dcn32_reset(struct dmub_srv *dmub);
+
+void dmub_dcn32_reset_release(struct dmub_srv *dmub);
+
+void dmub_dcn32_backdoor_load(struct dmub_srv *dmub,
+			      const struct dmub_window *cw0,
+			      const struct dmub_window *cw1);
+
+void dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub,
+		      const struct dmub_window *cw0,
+		      const struct dmub_window *cw1);
+
+void dmub_dcn32_setup_windows(struct dmub_srv *dmub,
+			      const struct dmub_window *cw2,
+			      const struct dmub_window *cw3,
+			      const struct dmub_window *cw4,
+			      const struct dmub_window *cw5,
+			      const struct dmub_window *cw6);
+
+void dmub_dcn32_setup_mailbox(struct dmub_srv *dmub,
+			      const struct dmub_region *inbox1);
+
+uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub);
+
+void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
+
+void dmub_dcn32_setup_out_mailbox(struct dmub_srv *dmub,
+			      const struct dmub_region *outbox1);
+
+uint32_t dmub_dcn32_get_outbox1_wptr(struct dmub_srv *dmub);
+
+void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
+
+bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub);
+
+bool dmub_dcn32_is_supported(struct dmub_srv *dmub);
+
+void dmub_dcn32_set_gpint(struct dmub_srv *dmub,
+			  union dmub_gpint_data_register reg);
+
+bool dmub_dcn32_is_gpint_acked(struct dmub_srv *dmub,
+			       union dmub_gpint_data_register reg);
+
+uint32_t dmub_dcn32_get_gpint_response(struct dmub_srv *dmub);
+
+uint32_t dmub_dcn32_get_gpint_dataout(struct dmub_srv *dmub);
+
+void dmub_dcn32_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);
+
+void dmub_dcn32_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);
+
+union dmub_fw_boot_status dmub_dcn32_get_fw_boot_status(struct dmub_srv *dmub);
+
+void dmub_dcn32_setup_outbox0(struct dmub_srv *dmub,
+			      const struct dmub_region *outbox0);
+
+uint32_t dmub_dcn32_get_outbox0_wptr(struct dmub_srv *dmub);
+
+void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
+
+uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub);
+
+void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data);
+
+void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub);
+void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);
+void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub);
+uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub);
+
+#endif /* _DMUB_DCN32_H_ */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 66db5e538c7f0..4c6a624f04a72 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -34,6 +34,7 @@
 #include "dmub_dcn31.h"
 #include "dmub_dcn315.h"
 #include "dmub_dcn316.h"
+#include "dmub_dcn32.h"
 #include "os_types.h"
 /*
  * Note: the DMUB service is standalone. No additional headers should be
@@ -260,6 +261,43 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
 
 		break;
 
+	case DMUB_ASIC_DCN32:
+	case DMUB_ASIC_DCN321:
+		dmub->regs_dcn32 = &dmub_srv_dcn32_regs;
+		funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory;
+		funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd;
+		funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register;
+		funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register;
+		funcs->reset = dmub_dcn32_reset;
+		funcs->reset_release = dmub_dcn32_reset_release;
+		funcs->backdoor_load = dmub_dcn32_backdoor_load;
+		funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode;
+		funcs->setup_windows = dmub_dcn32_setup_windows;
+		funcs->setup_mailbox = dmub_dcn32_setup_mailbox;
+		funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr;
+		funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr;
+		funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox;
+		funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr;
+		funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr;
+		funcs->is_supported = dmub_dcn32_is_supported;
+		funcs->is_hw_init = dmub_dcn32_is_hw_init;
+		funcs->set_gpint = dmub_dcn32_set_gpint;
+		funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked;
+		funcs->get_gpint_response = dmub_dcn32_get_gpint_response;
+		funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout;
+		funcs->get_fw_status = dmub_dcn32_get_fw_boot_status;
+		funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options;
+		funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence;
+
+		/* outbox0 call stacks */
+		funcs->setup_outbox0 = dmub_dcn32_setup_outbox0;
+		funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr;
+		funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr;
+		funcs->get_current_time = dmub_dcn32_get_current_time;
+		funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data;
+
+		break;
+
 	default:
 		return false;
 	}
@@ -501,6 +539,9 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
 	cw1.region.base = DMUB_CW1_BASE;
 	cw1.region.top = cw1.region.base + stack_fb->size - 1;
 
+	if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory)
+		dmub->hw_funcs.configure_dmub_in_system_memory(dmub);
+
 	if (params->load_inst_const && dmub->hw_funcs.backdoor_load) {
 		/**
 		 * Read back all the instruction memory so we don't hang the
@@ -508,7 +549,11 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
 		 * flushed yet. This only occurs in backdoor loading.
 		 */
 		dmub_flush_buffer_mem(inst_fb);
-		dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
+
+		if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode)
+			dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1);
+		else
+			dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
 	}
 
 	cw2.offset.quad_part = data_fb->gpu_addr;
@@ -583,6 +628,10 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
 	if (dmub->hw_funcs.enable_dmub_boot_options)
 		dmub->hw_funcs.enable_dmub_boot_options(dmub, params);
 
+	if (dmub->hw_funcs.skip_dmub_panel_power_sequence)
+		dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub,
+			params->skip_panel_power_sequence);
+
 	if (dmub->hw_funcs.reset_release)
 		dmub->hw_funcs.reset_release(dmub);
 
-- 
GitLab


From 0efd4374f6b41650863947a7528d45e8ad0f7ae0 Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Mon, 21 Feb 2022 16:41:46 -0500
Subject: [PATCH 0152/1731] drm/amd/display: add dcn32 IRQ changes

Add DCN3.2.x interrupt support.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/irq/Makefile   |  10 +-
 .../display/dc/irq/dcn32/irq_service_dcn32.c  | 369 ++++++++++++++++++
 .../display/dc/irq/dcn32/irq_service_dcn32.h  |  35 ++
 3 files changed, 413 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.h

diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile
index 5f49048dde47d..41da81c85fdc9 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
@@ -135,7 +135,6 @@ IRQ_DCN31 = irq_service_dcn31.o
 AMD_DAL_IRQ_DCN31= $(addprefix $(AMDDALPATH)/dc/irq/dcn31/,$(IRQ_DCN31))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN31)
-
 ###############################################################################
 # DCN 315
 ###############################################################################
@@ -144,3 +143,12 @@ IRQ_DCN315 = irq_service_dcn315.o
 AMD_DAL_IRQ_DCN315= $(addprefix $(AMDDALPATH)/dc/irq/dcn315/,$(IRQ_DCN315))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN315)
+
+###############################################################################
+# DCN 32
+###############################################################################
+IRQ_DCN32 = irq_service_dcn32.o
+
+AMD_DAL_IRQ_DCN32= $(addprefix $(AMDDALPATH)/dc/irq/dcn32/,$(IRQ_DCN32))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN32)
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
new file mode 100644
index 0000000000000..3f9d6531c5633
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
@@ -0,0 +1,369 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "include/logger_interface.h"
+#include "../dce110/irq_service_dce110.h"
+
+#include "dcn/dcn_3_2_0_offset.h"
+#include "dcn/dcn_3_2_0_sh_mask.h"
+
+#include "irq_service_dcn32.h"
+
+#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
+
+#define DCN_BASE__INST0_SEG2                       0x000034C0
+
+enum dc_irq_source to_dal_irq_source_dcn32(
+		struct irq_service *irq_service,
+		uint32_t src_id,
+		uint32_t ext_id)
+{
+	switch (src_id) {
+	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK1;
+	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK2;
+	case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK3;
+	case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK4;
+	case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK5;
+	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK6;
+	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP1;
+	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP2;
+	case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP3;
+	case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP4;
+	case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP5;
+	case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP6;
+	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE1;
+	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE2;
+	case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE3;
+	case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE4;
+	case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE5;
+	case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE6;
+
+	case DCN_1_0__SRCID__DC_HPD1_INT:
+		/* generic src_id for all HPD and HPDRX interrupts */
+		switch (ext_id) {
+		case DCN_1_0__CTXID__DC_HPD1_INT:
+			return DC_IRQ_SOURCE_HPD1;
+		case DCN_1_0__CTXID__DC_HPD2_INT:
+			return DC_IRQ_SOURCE_HPD2;
+		case DCN_1_0__CTXID__DC_HPD3_INT:
+			return DC_IRQ_SOURCE_HPD3;
+		case DCN_1_0__CTXID__DC_HPD4_INT:
+			return DC_IRQ_SOURCE_HPD4;
+		case DCN_1_0__CTXID__DC_HPD5_INT:
+			return DC_IRQ_SOURCE_HPD5;
+		case DCN_1_0__CTXID__DC_HPD6_INT:
+			return DC_IRQ_SOURCE_HPD6;
+		case DCN_1_0__CTXID__DC_HPD1_RX_INT:
+			return DC_IRQ_SOURCE_HPD1RX;
+		case DCN_1_0__CTXID__DC_HPD2_RX_INT:
+			return DC_IRQ_SOURCE_HPD2RX;
+		case DCN_1_0__CTXID__DC_HPD3_RX_INT:
+			return DC_IRQ_SOURCE_HPD3RX;
+		case DCN_1_0__CTXID__DC_HPD4_RX_INT:
+			return DC_IRQ_SOURCE_HPD4RX;
+		case DCN_1_0__CTXID__DC_HPD5_RX_INT:
+			return DC_IRQ_SOURCE_HPD5RX;
+		case DCN_1_0__CTXID__DC_HPD6_RX_INT:
+			return DC_IRQ_SOURCE_HPD6RX;
+		default:
+			return DC_IRQ_SOURCE_INVALID;
+		}
+		break;
+
+	default:
+		return DC_IRQ_SOURCE_INVALID;
+	}
+}
+
+static bool hpd_ack(
+	struct irq_service *irq_service,
+	const struct irq_source_info *info)
+{
+	uint32_t addr = info->status_reg;
+	uint32_t value = dm_read_reg(irq_service->ctx, addr);
+	uint32_t current_status =
+		get_reg_field_value(
+			value,
+			HPD0_DC_HPD_INT_STATUS,
+			DC_HPD_SENSE_DELAYED);
+
+	dal_irq_service_ack_generic(irq_service, info);
+
+	value = dm_read_reg(irq_service->ctx, info->enable_reg);
+
+	set_reg_field_value(
+		value,
+		current_status ? 0 : 1,
+		HPD0_DC_HPD_INT_CONTROL,
+		DC_HPD_INT_POLARITY);
+
+	dm_write_reg(irq_service->ctx, info->enable_reg, value);
+
+	return true;
+}
+
+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
+	.set = NULL,
+	.ack = hpd_ack
+};
+
+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+#undef BASE_INNER
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+/* compile time expand base address. */
+#define BASE(seg) \
+	BASE_INNER(seg)
+
+#define SRI(reg_name, block, id)\
+	BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+			reg ## block ## id ## _ ## reg_name
+
+#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
+	.enable_reg = SRI(reg1, block, reg_num),\
+	.enable_mask = \
+		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
+	.enable_value = {\
+		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
+		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
+	},\
+	.ack_reg = SRI(reg2, block, reg_num),\
+	.ack_mask = \
+		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
+	.ack_value = \
+		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
+
+#define hpd_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
+		IRQ_REG_ENTRY(HPD, reg_num,\
+			DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
+			DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
+		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
+		.funcs = &hpd_irq_info_funcs\
+	}
+
+#define hpd_rx_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
+		IRQ_REG_ENTRY(HPD, reg_num,\
+			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
+			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
+		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
+		.funcs = &hpd_rx_irq_info_funcs\
+	}
+#define pflip_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
+		IRQ_REG_ENTRY(HUBPREQ, reg_num,\
+			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
+			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
+		.funcs = &pflip_irq_info_funcs\
+	}
+
+/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
+ * of DCE's DC_IRQ_SOURCE_VUPDATEx.
+ */
+#define vupdate_no_lock_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
+		IRQ_REG_ENTRY(OTG, reg_num,\
+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
+		.funcs = &vupdate_no_lock_irq_info_funcs\
+	}
+
+#define vblank_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
+		IRQ_REG_ENTRY(OTG, reg_num,\
+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
+		.funcs = &vblank_irq_info_funcs\
+}
+
+#define dummy_irq_entry() \
+	{\
+		.funcs = &dummy_irq_info_funcs\
+	}
+
+#define i2c_int_entry(reg_num) \
+	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
+
+#define dp_sink_int_entry(reg_num) \
+	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
+
+#define gpio_pad_int_entry(reg_num) \
+	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
+
+#define dc_underflow_int_entry(reg_num) \
+	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
+
+static const struct irq_source_info_funcs dummy_irq_info_funcs = {
+	.set = dal_irq_service_dummy_set,
+	.ack = dal_irq_service_dummy_ack
+};
+
+static const struct irq_source_info
+irq_source_info_dcn32[DAL_IRQ_SOURCES_NUMBER] = {
+	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
+	hpd_int_entry(0),
+	hpd_int_entry(1),
+	hpd_int_entry(2),
+	hpd_int_entry(3),
+	hpd_int_entry(4),
+	hpd_rx_int_entry(0),
+	hpd_rx_int_entry(1),
+	hpd_rx_int_entry(2),
+	hpd_rx_int_entry(3),
+	hpd_rx_int_entry(4),
+	i2c_int_entry(1),
+	i2c_int_entry(2),
+	i2c_int_entry(3),
+	i2c_int_entry(4),
+	i2c_int_entry(5),
+	i2c_int_entry(6),
+	dp_sink_int_entry(1),
+	dp_sink_int_entry(2),
+	dp_sink_int_entry(3),
+	dp_sink_int_entry(4),
+	dp_sink_int_entry(5),
+	dp_sink_int_entry(6),
+	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
+	pflip_int_entry(0),
+	pflip_int_entry(1),
+	pflip_int_entry(2),
+	pflip_int_entry(3),
+	[DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
+	[DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
+	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
+	gpio_pad_int_entry(0),
+	gpio_pad_int_entry(1),
+	gpio_pad_int_entry(2),
+	gpio_pad_int_entry(3),
+	gpio_pad_int_entry(4),
+	gpio_pad_int_entry(5),
+	gpio_pad_int_entry(6),
+	gpio_pad_int_entry(7),
+	gpio_pad_int_entry(8),
+	gpio_pad_int_entry(9),
+	gpio_pad_int_entry(10),
+	gpio_pad_int_entry(11),
+	gpio_pad_int_entry(12),
+	gpio_pad_int_entry(13),
+	gpio_pad_int_entry(14),
+	gpio_pad_int_entry(15),
+	gpio_pad_int_entry(16),
+	gpio_pad_int_entry(17),
+	gpio_pad_int_entry(18),
+	gpio_pad_int_entry(19),
+	gpio_pad_int_entry(20),
+	gpio_pad_int_entry(21),
+	gpio_pad_int_entry(22),
+	gpio_pad_int_entry(23),
+	gpio_pad_int_entry(24),
+	gpio_pad_int_entry(25),
+	gpio_pad_int_entry(26),
+	gpio_pad_int_entry(27),
+	gpio_pad_int_entry(28),
+	gpio_pad_int_entry(29),
+	gpio_pad_int_entry(30),
+	dc_underflow_int_entry(1),
+	dc_underflow_int_entry(2),
+	dc_underflow_int_entry(3),
+	dc_underflow_int_entry(4),
+	dc_underflow_int_entry(5),
+	dc_underflow_int_entry(6),
+	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
+	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
+	vupdate_no_lock_int_entry(0),
+	vupdate_no_lock_int_entry(1),
+	vupdate_no_lock_int_entry(2),
+	vupdate_no_lock_int_entry(3),
+	vblank_int_entry(0),
+	vblank_int_entry(1),
+	vblank_int_entry(2),
+	vblank_int_entry(3),
+};
+
+static const struct irq_service_funcs irq_service_funcs_dcn32 = {
+		.to_dal_irq_source = to_dal_irq_source_dcn32
+};
+
+static void dcn32_irq_construct(
+	struct irq_service *irq_service,
+	struct irq_service_init_data *init_data)
+{
+	dal_irq_service_construct(irq_service, init_data);
+
+	irq_service->info = irq_source_info_dcn32;
+	irq_service->funcs = &irq_service_funcs_dcn32;
+}
+
+struct irq_service *dal_irq_service_dcn32_create(
+	struct irq_service_init_data *init_data)
+{
+	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
+						  GFP_KERNEL);
+
+	if (!irq_service)
+		return NULL;
+
+	dcn32_irq_construct(irq_service, init_data);
+	return irq_service;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.h b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.h
new file mode 100644
index 0000000000000..a0d9c9e4e17f1
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#ifndef __DAL_IRQ_SERVICE_DCN32_H__
+#define __DAL_IRQ_SERVICE_DCN32_H__
+
+#include "../irq_service.h"
+
+struct irq_service *dal_irq_service_dcn32_create(
+	struct irq_service_init_data *init_data);
+
+#endif /* __DAL_IRQ_SERVICE_DCN32_H__ */
-- 
GitLab


From 58efeea32d5e32fa340c7ee3f52d5f986b240e39 Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Mon, 21 Feb 2022 16:55:55 -0500
Subject: [PATCH 0153/1731] drm/amd/display: add GPIO changes for DCN32/321

Add support for the GPIO changes for DCN3.2.x.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/gpio/Makefile  |   8 +-
 .../display/dc/gpio/dcn32/hw_factory_dcn32.c  | 255 +++++++++++++
 .../hw_factory_dcn32.h}                       |  13 +-
 .../dc/gpio/dcn32/hw_translate_dcn32.c        | 349 ++++++++++++++++++
 .../hw_translate_dcn32.h}                     |  11 +-
 .../dc/gpio/diagnostics/hw_factory_diag.c     |  62 ----
 .../dc/gpio/diagnostics/hw_translate_diag.c   |  41 --
 .../gpu/drm/amd/display/dc/gpio/hw_factory.c  |  16 +-
 .../drm/amd/display/dc/gpio/hw_translate.c    |  13 +-
 9 files changed, 628 insertions(+), 140 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
 rename drivers/gpu/drm/amd/display/dc/gpio/{diagnostics/hw_factory_diag.h => dcn32/hw_factory_dcn32.h} (81%)
 create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
 rename drivers/gpu/drm/amd/display/dc/gpio/{diagnostics/hw_translate_diag.h => dcn32/hw_translate_dcn32.h} (82%)
 delete mode 100644 drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c
 delete mode 100644 drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.c

diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
index 0f4a22be8c40f..bc47481a158ea 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
@@ -115,10 +115,10 @@ AMD_DAL_GPIO_DCN315 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn315/,$(GPIO_DCN315))
 AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN315)
 
 ###############################################################################
-# Diagnostics on FPGA
+# DCN 3.2
 ###############################################################################
-GPIO_DIAG_FPGA = hw_translate_diag.o hw_factory_diag.o
+GPIO_DCN32 = hw_translate_dcn32.o hw_factory_dcn32.o
 
-AMD_DAL_GPIO_DIAG_FPGA = $(addprefix $(AMDDALPATH)/dc/gpio/diagnostics/,$(GPIO_DIAG_FPGA))
+AMD_DAL_GPIO_DCN32 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn32/,$(GPIO_DCN32))
 
-AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DIAG_FPGA)
+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN32)
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
new file mode 100644
index 0000000000000..d635b73af46fe
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
@@ -0,0 +1,255 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#include "dm_services.h"
+#include "include/gpio_types.h"
+#include "../hw_factory.h"
+
+
+#include "../hw_gpio.h"
+#include "../hw_ddc.h"
+#include "../hw_hpd.h"
+#include "../hw_generic.h"
+
+#include "hw_factory_dcn32.h"
+
+#include "dcn/dcn_3_2_0_offset.h"
+#include "dcn/dcn_3_2_0_sh_mask.h"
+
+#include "reg_helper.h"
+#include "../hpd_regs.h"
+
+#define DCN_BASE__INST0_SEG2                       0x000034C0
+
+/* begin *********************
+ * macros to expend register list macro defined in HW object header file */
+
+/* DCN */
+#define block HPD
+#define reg_num 0
+
+#undef BASE_INNER
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+#define BASE(seg) BASE_INNER(seg)
+
+
+
+#define REG(reg_name)\
+		BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
+
+#define SF_HPD(reg_name, field_name, post_fix)\
+	.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
+
+#define REGI(reg_name, block, id)\
+	BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+				reg ## block ## id ## _ ## reg_name
+
+#define SF(reg_name, field_name, post_fix)\
+	.field_name = reg_name ## __ ## field_name ## post_fix
+
+/* macros to expend register list macro defined in HW object header file
+ * end *********************/
+
+
+
+#define hpd_regs(id) \
+{\
+	HPD_REG_LIST(id)\
+}
+
+static const struct hpd_registers hpd_regs[] = {
+	hpd_regs(0),
+	hpd_regs(1),
+	hpd_regs(2),
+	hpd_regs(3),
+	hpd_regs(4),
+};
+
+static const struct hpd_sh_mask hpd_shift = {
+		HPD_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct hpd_sh_mask hpd_mask = {
+		HPD_MASK_SH_LIST(_MASK)
+};
+
+#include "../ddc_regs.h"
+
+ /* set field name */
+#define SF_DDC(reg_name, field_name, post_fix)\
+	.field_name = reg_name ## __ ## field_name ## post_fix
+
+static const struct ddc_registers ddc_data_regs_dcn[] = {
+	ddc_data_regs_dcn2(1),
+	ddc_data_regs_dcn2(2),
+	ddc_data_regs_dcn2(3),
+	ddc_data_regs_dcn2(4),
+	ddc_data_regs_dcn2(5),
+	{
+			DDC_GPIO_VGA_REG_LIST(DATA),
+			.ddc_setup = 0,
+			.phy_aux_cntl = 0,
+			.dc_gpio_aux_ctrl_5 = 0
+	}
+};
+
+static const struct ddc_registers ddc_clk_regs_dcn[] = {
+	ddc_clk_regs_dcn2(1),
+	ddc_clk_regs_dcn2(2),
+	ddc_clk_regs_dcn2(3),
+	ddc_clk_regs_dcn2(4),
+	ddc_clk_regs_dcn2(5),
+	{
+			DDC_GPIO_VGA_REG_LIST(CLK),
+			.ddc_setup = 0,
+			.phy_aux_cntl = 0,
+			.dc_gpio_aux_ctrl_5 = 0
+	}
+};
+
+static const struct ddc_sh_mask ddc_shift[] = {
+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 1),
+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 2),
+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)
+};
+
+static const struct ddc_sh_mask ddc_mask[] = {
+	DDC_MASK_SH_LIST_DCN2(_MASK, 1),
+	DDC_MASK_SH_LIST_DCN2(_MASK, 2),
+	DDC_MASK_SH_LIST_DCN2(_MASK, 3),
+	DDC_MASK_SH_LIST_DCN2(_MASK, 4),
+	DDC_MASK_SH_LIST_DCN2(_MASK, 5),
+	DDC_MASK_SH_LIST_DCN2(_MASK, 6)
+};
+
+#include "../generic_regs.h"
+
+/* set field name */
+#define SF_GENERIC(reg_name, field_name, post_fix)\
+	.field_name = reg_name ## __ ## field_name ## post_fix
+
+#define generic_regs(id) \
+{\
+	GENERIC_REG_LIST(id)\
+}
+
+static const struct generic_registers generic_regs[] = {
+	generic_regs(A),
+	generic_regs(B),
+};
+
+static const struct generic_sh_mask generic_shift[] = {
+	GENERIC_MASK_SH_LIST(__SHIFT, A),
+	GENERIC_MASK_SH_LIST(__SHIFT, B),
+};
+
+static const struct generic_sh_mask generic_mask[] = {
+	GENERIC_MASK_SH_LIST(_MASK, A),
+	GENERIC_MASK_SH_LIST(_MASK, B),
+};
+
+static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
+{
+	struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
+
+	generic->regs = &generic_regs[en];
+	generic->shifts = &generic_shift[en];
+	generic->masks = &generic_mask[en];
+	generic->base.regs = &generic_regs[en].gpio;
+}
+
+static void define_ddc_registers(
+		struct hw_gpio_pin *pin,
+		uint32_t en)
+{
+	struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
+
+	switch (pin->id) {
+	case GPIO_ID_DDC_DATA:
+		ddc->regs = &ddc_data_regs_dcn[en];
+		ddc->base.regs = &ddc_data_regs_dcn[en].gpio;
+		break;
+	case GPIO_ID_DDC_CLOCK:
+		ddc->regs = &ddc_clk_regs_dcn[en];
+		ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;
+		break;
+	default:
+		ASSERT_CRITICAL(false);
+		return;
+	}
+
+	ddc->shifts = &ddc_shift[en];
+	ddc->masks = &ddc_mask[en];
+
+}
+
+static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
+{
+	struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
+
+	hpd->regs = &hpd_regs[en];
+	hpd->shifts = &hpd_shift;
+	hpd->masks = &hpd_mask;
+	hpd->base.regs = &hpd_regs[en].gpio;
+}
+
+
+/* fucntion table */
+static const struct hw_factory_funcs funcs = {
+	.init_ddc_data = dal_hw_ddc_init,
+	.init_generic = dal_hw_generic_init,
+	.init_hpd = dal_hw_hpd_init,
+	.get_ddc_pin = dal_hw_ddc_get_pin,
+	.get_hpd_pin = dal_hw_hpd_get_pin,
+	.get_generic_pin = dal_hw_generic_get_pin,
+	.define_hpd_registers = define_hpd_registers,
+	.define_ddc_registers = define_ddc_registers,
+	.define_generic_registers = define_generic_registers
+};
+/*
+ * dal_hw_factory_dcn32_init
+ *
+ * @brief
+ * Initialize HW factory function pointers and pin info
+ *
+ * @param
+ * struct hw_factory *factory - [out] struct of function pointers
+ */
+void dal_hw_factory_dcn32_init(struct hw_factory *factory)
+{
+	factory->number_of_pins[GPIO_ID_DDC_DATA] = 6;
+	factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 6;
+	factory->number_of_pins[GPIO_ID_GENERIC] = 4;
+	factory->number_of_pins[GPIO_ID_HPD] = 5;
+	factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28;
+	factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
+	factory->number_of_pins[GPIO_ID_SYNC] = 0;
+	factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/
+
+	factory->funcs = &funcs;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.h
similarity index 81%
rename from drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.h
rename to drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.h
index bf68eb1d9a1d2..71138d0e192be 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.h
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013-16 Advanced Micro Devices, Inc.
+ * Copyright 2022 Advanced Micro Devices, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -22,13 +22,10 @@
  * Authors: AMD
  *
  */
-
-#ifndef __DAL_HW_FACTORY_DIAG_FPGA_H__
-#define __DAL_HW_FACTORY_DIAG_FPGA_H__
-
-struct hw_factory;
+#ifndef __DAL_HW_FACTORY_DCN32_H__
+#define __DAL_HW_FACTORY_DCN32_H__
 
 /* Initialize HW factory function pointers and pin info */
-void dal_hw_factory_diag_fpga_init(struct hw_factory *factory);
+void dal_hw_factory_dcn32_init(struct hw_factory *factory);
 
-#endif /* __DAL_HW_FACTORY_DIAG_FPGA_H__ */
+#endif /* __DAL_HW_FACTORY_DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
new file mode 100644
index 0000000000000..8493b9981f9e8
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
@@ -0,0 +1,349 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+/*
+ * Pre-requisites: headers required by header of this unit
+ */
+#include "hw_translate_dcn32.h"
+
+#include "dm_services.h"
+#include "include/gpio_types.h"
+#include "../hw_translate.h"
+
+#include "dcn/dcn_3_2_0_offset.h"
+#include "dcn/dcn_3_2_0_sh_mask.h"
+
+#define DCN_BASE__INST0_SEG2                       0x000034C0
+
+/* begin *********************
+ * macros to expend register list macro defined in HW object header file */
+
+/* DCN */
+#define block HPD
+#define reg_num 0
+
+#undef BASE_INNER
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+#define BASE(seg) BASE_INNER(seg)
+
+#undef REG
+#define REG(reg_name)\
+		BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
+#define SF_HPD(reg_name, field_name, post_fix)\
+	.field_name = reg_name ## __ ## field_name ## post_fix
+
+
+/* macros to expend register list macro defined in HW object header file
+ * end *********************/
+
+
+static bool offset_to_id(
+	uint32_t offset,
+	uint32_t mask,
+	enum gpio_id *id,
+	uint32_t *en)
+{
+	switch (offset) {
+	/* GENERIC */
+	case REG(DC_GPIO_GENERIC_A):
+		*id = GPIO_ID_GENERIC;
+		switch (mask) {
+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
+			*en = GPIO_GENERIC_A;
+			return true;
+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
+			*en = GPIO_GENERIC_B;
+			return true;
+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
+			*en = GPIO_GENERIC_C;
+			return true;
+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
+			*en = GPIO_GENERIC_D;
+			return true;
+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
+			*en = GPIO_GENERIC_E;
+			return true;
+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
+			*en = GPIO_GENERIC_F;
+			return true;
+		default:
+			ASSERT_CRITICAL(false);
+			return false;
+		}
+	break;
+	/* HPD */
+	case REG(DC_GPIO_HPD_A):
+		*id = GPIO_ID_HPD;
+		switch (mask) {
+		case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
+			*en = GPIO_HPD_1;
+			return true;
+		case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
+			*en = GPIO_HPD_2;
+			return true;
+		case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
+			*en = GPIO_HPD_3;
+			return true;
+		case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
+			*en = GPIO_HPD_4;
+			return true;
+		case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
+			*en = GPIO_HPD_5;
+			return true;
+		default:
+			ASSERT_CRITICAL(false);
+			return false;
+		}
+	break;
+	/* REG(DC_GPIO_GENLK_MASK */
+	case REG(DC_GPIO_GENLK_A):
+		*id = GPIO_ID_GSL;
+		switch (mask) {
+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
+			*en = GPIO_GSL_GENLOCK_CLOCK;
+			return true;
+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
+			*en = GPIO_GSL_GENLOCK_VSYNC;
+			return true;
+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
+			*en = GPIO_GSL_SWAPLOCK_A;
+			return true;
+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
+			*en = GPIO_GSL_SWAPLOCK_B;
+			return true;
+		default:
+			ASSERT_CRITICAL(false);
+			return false;
+		}
+	break;
+	/* DDC */
+	/* we don't care about the GPIO_ID for DDC
+	 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
+	 * directly in the create method */
+	case REG(DC_GPIO_DDC1_A):
+		*en = GPIO_DDC_LINE_DDC1;
+		return true;
+	case REG(DC_GPIO_DDC2_A):
+		*en = GPIO_DDC_LINE_DDC2;
+		return true;
+	case REG(DC_GPIO_DDC3_A):
+		*en = GPIO_DDC_LINE_DDC3;
+		return true;
+	case REG(DC_GPIO_DDC4_A):
+		*en = GPIO_DDC_LINE_DDC4;
+		return true;
+	case REG(DC_GPIO_DDC5_A):
+		*en = GPIO_DDC_LINE_DDC5;
+		return true;
+	case REG(DC_GPIO_DDCVGA_A):
+		*en = GPIO_DDC_LINE_DDC_VGA;
+		return true;
+	default:
+		ASSERT_CRITICAL(false);
+		return false;
+	}
+}
+
+static bool id_to_offset(
+	enum gpio_id id,
+	uint32_t en,
+	struct gpio_pin_info *info)
+{
+	bool result = true;
+
+	switch (id) {
+	case GPIO_ID_DDC_DATA:
+		info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK;
+		switch (en) {
+		case GPIO_DDC_LINE_DDC1:
+			info->offset = REG(DC_GPIO_DDC1_A);
+		break;
+		case GPIO_DDC_LINE_DDC2:
+			info->offset = REG(DC_GPIO_DDC2_A);
+		break;
+		case GPIO_DDC_LINE_DDC3:
+			info->offset = REG(DC_GPIO_DDC3_A);
+		break;
+		case GPIO_DDC_LINE_DDC4:
+			info->offset = REG(DC_GPIO_DDC4_A);
+		break;
+		case GPIO_DDC_LINE_DDC5:
+			info->offset = REG(DC_GPIO_DDC5_A);
+		break;
+		case GPIO_DDC_LINE_DDC_VGA:
+			info->offset = REG(DC_GPIO_DDCVGA_A);
+		break;
+		case GPIO_DDC_LINE_I2C_PAD:
+		default:
+			ASSERT_CRITICAL(false);
+			result = false;
+		}
+	break;
+	case GPIO_ID_DDC_CLOCK:
+		info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK;
+		switch (en) {
+		case GPIO_DDC_LINE_DDC1:
+			info->offset = REG(DC_GPIO_DDC1_A);
+		break;
+		case GPIO_DDC_LINE_DDC2:
+			info->offset = REG(DC_GPIO_DDC2_A);
+		break;
+		case GPIO_DDC_LINE_DDC3:
+			info->offset = REG(DC_GPIO_DDC3_A);
+		break;
+		case GPIO_DDC_LINE_DDC4:
+			info->offset = REG(DC_GPIO_DDC4_A);
+		break;
+		case GPIO_DDC_LINE_DDC5:
+			info->offset = REG(DC_GPIO_DDC5_A);
+		break;
+		case GPIO_DDC_LINE_DDC_VGA:
+			info->offset = REG(DC_GPIO_DDCVGA_A);
+		break;
+		case GPIO_DDC_LINE_I2C_PAD:
+		default:
+			ASSERT_CRITICAL(false);
+			result = false;
+		}
+	break;
+	case GPIO_ID_GENERIC:
+		info->offset = REG(DC_GPIO_GENERIC_A);
+		switch (en) {
+		case GPIO_GENERIC_A:
+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
+		break;
+		case GPIO_GENERIC_B:
+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
+		break;
+		case GPIO_GENERIC_C:
+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
+		break;
+		case GPIO_GENERIC_D:
+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
+		break;
+		case GPIO_GENERIC_E:
+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
+		break;
+		case GPIO_GENERIC_F:
+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
+		break;
+		default:
+			ASSERT_CRITICAL(false);
+			result = false;
+		}
+	break;
+	case GPIO_ID_HPD:
+		info->offset = REG(DC_GPIO_HPD_A);
+		switch (en) {
+		case GPIO_HPD_1:
+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
+		break;
+		case GPIO_HPD_2:
+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
+		break;
+		case GPIO_HPD_3:
+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
+		break;
+		case GPIO_HPD_4:
+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
+		break;
+		case GPIO_HPD_5:
+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
+		break;
+		default:
+			ASSERT_CRITICAL(false);
+			result = false;
+		}
+	break;
+	case GPIO_ID_GSL:
+		switch (en) {
+		case GPIO_GSL_GENLOCK_CLOCK:
+				/*not implmented*/
+			ASSERT_CRITICAL(false);
+			result = false;
+		break;
+		case GPIO_GSL_GENLOCK_VSYNC:
+			/*not implmented*/
+			ASSERT_CRITICAL(false);
+			result = false;
+		break;
+		case GPIO_GSL_SWAPLOCK_A:
+			/*not implmented*/
+			ASSERT_CRITICAL(false);
+			result = false;
+		break;
+		case GPIO_GSL_SWAPLOCK_B:
+			/*not implmented*/
+			ASSERT_CRITICAL(false);
+			result = false;
+
+		break;
+		default:
+			ASSERT_CRITICAL(false);
+			result = false;
+		}
+	break;
+	case GPIO_ID_SYNC:
+	case GPIO_ID_VIP_PAD:
+	default:
+		ASSERT_CRITICAL(false);
+		result = false;
+	}
+
+	if (result) {
+		info->offset_y = info->offset + 2;
+		info->offset_en = info->offset + 1;
+		info->offset_mask = info->offset - 1;
+
+		info->mask_y = info->mask;
+		info->mask_en = info->mask;
+		info->mask_mask = info->mask;
+	}
+
+	return result;
+}
+
+/* function table */
+static const struct hw_translate_funcs funcs = {
+	.offset_to_id = offset_to_id,
+	.id_to_offset = id_to_offset,
+};
+
+/*
+ * dal_hw_translate_dcn32_init
+ *
+ * @brief
+ * Initialize Hw translate function pointers.
+ *
+ * @param
+ * struct hw_translate *tr - [out] struct of function pointers
+ *
+ */
+void dal_hw_translate_dcn32_init(struct hw_translate *tr)
+{
+	tr->funcs = &funcs;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.h
similarity index 82%
rename from drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.h
rename to drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.h
index 4f053241fe962..af64e104d84c4 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.h
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013-16 Advanced Micro Devices, Inc.
+ * Copyright 2022 Advanced Micro Devices, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -22,13 +22,12 @@
  * Authors: AMD
  *
  */
-
-#ifndef __DAL_HW_TRANSLATE_DIAG_FPGA_H__
-#define __DAL_HW_TRANSLATE_DIAG_FPGA_H__
+#ifndef __DAL_HW_TRANSLATE_DCN32_H__
+#define __DAL_HW_TRANSLATE_DCN32_H__
 
 struct hw_translate;
 
 /* Initialize Hw translate function pointers */
-void dal_hw_translate_diag_fpga_init(struct hw_translate *tr);
+void dal_hw_translate_dcn32_init(struct hw_translate *tr);
 
-#endif /* __DAL_HW_TRANSLATE_DIAG_FPGA_H__ */
+#endif /* __DAL_HW_TRANSLATE_DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c b/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c
deleted file mode 100644
index c6e28f6bf1a27..0000000000000
--- a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright 2013-16 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-
-#include "dm_services.h"
-#include "hw_factory_diag.h"
-#include "include/gpio_types.h"
-#include "../hw_factory.h"
-
-/*
- * Header of this unit
- */
-
-#include "../hw_gpio.h"
-#include "../hw_ddc.h"
-#include "../hw_hpd.h"
-#include "../hw_generic.h"
-
-/* function table */
-static const struct hw_factory_funcs funcs = {
-	.init_ddc_data = NULL,
-	.init_generic = NULL,
-	.init_hpd = NULL,
-};
-
-void dal_hw_factory_diag_fpga_init(struct hw_factory *factory)
-{
-	factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
-	factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
-	factory->number_of_pins[GPIO_ID_GENERIC] = 7;
-	factory->number_of_pins[GPIO_ID_HPD] = 6;
-	factory->number_of_pins[GPIO_ID_GPIO_PAD] = 31;
-	factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
-	factory->number_of_pins[GPIO_ID_SYNC] = 2;
-	factory->number_of_pins[GPIO_ID_GSL] = 4;
-	factory->funcs = &funcs;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.c b/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.c
deleted file mode 100644
index e5138a5a8eb5a..0000000000000
--- a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2013-16 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "hw_translate_diag.h"
-#include "include/gpio_types.h"
-
-#include "../hw_translate.h"
-
-/* function table */
-static const struct hw_translate_funcs funcs = {
-	.offset_to_id = NULL,
-	.id_to_offset = NULL,
-};
-
-void dal_hw_translate_diag_fpga_init(struct hw_translate *tr)
-{
-	tr->funcs = &funcs;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
index ef4f696120978..9756640411b90 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
@@ -53,23 +53,13 @@
 #include "dcn21/hw_factory_dcn21.h"
 #include "dcn30/hw_factory_dcn30.h"
 #include "dcn315/hw_factory_dcn315.h"
-
-#include "diagnostics/hw_factory_diag.h"
-
-/*
- * This unit
- */
+#include "dcn32/hw_factory_dcn32.h"
 
 bool dal_hw_factory_init(
 	struct hw_factory *factory,
 	enum dce_version dce_version,
 	enum dce_environment dce_environment)
 {
-	if (IS_FPGA_MAXIMUS_DC(dce_environment)) {
-		dal_hw_factory_diag_fpga_init(factory);
-		return true;
-	}
-
 	switch (dce_version) {
 #if defined(CONFIG_DRM_AMD_DC_SI)
 	case DCE_VERSION_6_0:
@@ -118,6 +108,10 @@ bool dal_hw_factory_init(
 	case DCN_VERSION_3_15:
 		dal_hw_factory_dcn315_init(factory);
 		return true;
+	case DCN_VERSION_3_2:
+	case DCN_VERSION_3_21:
+		dal_hw_factory_dcn32_init(factory);
+		return true;
 	default:
 		ASSERT_CRITICAL(false);
 		return false;
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
index 1db4f1414d7eb..82aad7bc03005 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
@@ -51,8 +51,7 @@
 #include "dcn21/hw_translate_dcn21.h"
 #include "dcn30/hw_translate_dcn30.h"
 #include "dcn315/hw_translate_dcn315.h"
-
-#include "diagnostics/hw_translate_diag.h"
+#include "dcn32/hw_translate_dcn32.h"
 
 /*
  * This unit
@@ -63,11 +62,6 @@ bool dal_hw_translate_init(
 	enum dce_version dce_version,
 	enum dce_environment dce_environment)
 {
-	if (IS_FPGA_MAXIMUS_DC(dce_environment)) {
-		dal_hw_translate_diag_fpga_init(translate);
-		return true;
-	}
-
 	switch (dce_version) {
 #if defined(CONFIG_DRM_AMD_DC_SI)
 	case DCE_VERSION_6_0:
@@ -113,7 +107,10 @@ bool dal_hw_translate_init(
 	case DCN_VERSION_3_15:
 		dal_hw_translate_dcn315_init(translate);
 		return true;
-
+	case DCN_VERSION_3_2:
+	case DCN_VERSION_3_21:
+		dal_hw_translate_dcn32_init(translate);
+		return true;
 	default:
 		BREAK_TO_DEBUGGER();
 		return false;
-- 
GitLab


From dda4fb85e433f761eedaed0005a2bc20d705d504 Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Mon, 21 Feb 2022 16:58:49 -0500
Subject: [PATCH 0154/1731] drm/amd/display: DML changes for DCN32/321

DML is required for display configuration modelling for things like
bandwidth management and validation.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dml/Makefile   |    7 +
 .../dc/dml/dcn30/display_mode_vba_30.c        |    8 +-
 .../dc/dml/dcn31/display_mode_vba_31.c        |    2 +-
 .../dc/dml/dcn32/display_mode_vba_32.c        | 3835 ++++++++++
 .../dc/dml/dcn32/display_mode_vba_32.h        |   57 +
 .../dc/dml/dcn32/display_mode_vba_util_32.c   | 6254 +++++++++++++++++
 .../dc/dml/dcn32/display_mode_vba_util_32.h   | 1175 ++++
 .../dc/dml/dcn32/display_rq_dlg_calc_32.c     |  616 ++
 .../dc/dml/dcn32/display_rq_dlg_calc_32.h     |   70 +
 .../amd/display/dc/dml/display_mode_enums.h   |   88 +-
 .../drm/amd/display/dc/dml/display_mode_lib.c |   12 +
 .../drm/amd/display/dc/dml/display_mode_lib.h |   15 +
 .../amd/display/dc/dml/display_mode_structs.h |  132 +
 .../drm/amd/display/dc/dml/display_mode_vba.c |  171 +
 .../drm/amd/display/dc/dml/display_mode_vba.h |  242 +-
 .../gpu/drm/amd/display/dc/dml/dml_wrapper.c  |   71 +-
 16 files changed, 12710 insertions(+), 45 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.h

diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
index a64b88ca01a91..c48688cdd7f7d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
@@ -72,6 +72,9 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_ccflags) $(frame_warn_flag)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/dcn30_fpu.o := $(dml_ccflags)
+CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_32.o := $(dml_ccflags) $(frame_warn_flag)
+CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_rq_dlg_calc_32.o := $(dml_ccflags)
+CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_util_32.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/dcn31_fpu.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn301/dcn301_fpu.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn302/dcn302_fpu.o := $(dml_ccflags)
@@ -93,6 +96,9 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_rcflags)
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_32.o := $(dml_rcflags)
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_rq_dlg_calc_32.o := $(dml_rcflags)
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_util_32.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn301/dcn301_fpu.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dsc/rc_calc_fpu.o  := $(dml_rcflags)
@@ -116,6 +122,7 @@ DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o
 DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o
 DML += dcn30/dcn30_fpu.o dcn30/display_mode_vba_30.o dcn30/display_rq_dlg_calc_30.o
 DML += dcn31/display_mode_vba_31.o dcn31/display_rq_dlg_calc_31.o
+DML += dcn32/display_mode_vba_32.o dcn32/display_rq_dlg_calc_32.o dcn32/display_mode_vba_util_32.o
 DML += dcn31/dcn31_fpu.o
 DML += dcn301/dcn301_fpu.o
 DML += dcn302/dcn302_fpu.o
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index f47d82da115c9..fb4aa4c800bf7 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -438,8 +438,8 @@ static void UseMinimumDCFCLK(
 		int dpte_group_bytes[],
 		double PrefetchLinesY[][2][DC__NUM_DPP__MAX],
 		double PrefetchLinesC[][2][DC__NUM_DPP__MAX],
-		int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
-		int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
 		int BytePerPixelY[],
 		int BytePerPixelC[],
 		int HTotal[],
@@ -6696,8 +6696,8 @@ static void UseMinimumDCFCLK(
 		int dpte_group_bytes[],
 		double PrefetchLinesY[][2][DC__NUM_DPP__MAX],
 		double PrefetchLinesC[][2][DC__NUM_DPP__MAX],
-		int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
-		int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
 		int BytePerPixelY[],
 		int BytePerPixelC[],
 		int HTotal[],
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index e4b9fd31223c9..448fbbcdf88ab 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -2996,7 +2996,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 				v->ImmediateFlipSupported)) ? true : false;
 #ifdef __DML_VBA_DEBUG__
 		dml_print("DML::%s: PrefetchModeSupported %d\n", __func__, v->PrefetchModeSupported);
-		dml_print("DML::%s: ImmediateFlipRequirement %d\n", __func__, v->ImmediateFlipRequirement == dm_immediate_flip_required);
+		dml_print("DML::%s: ImmediateFlipRequirement[0] %d\n", __func__, v->ImmediateFlipRequirement[0] == dm_immediate_flip_required);
 		dml_print("DML::%s: ImmediateFlipSupported %d\n", __func__, v->ImmediateFlipSupported);
 		dml_print("DML::%s: ImmediateFlipSupport %d\n", __func__, v->ImmediateFlipSupport);
 		dml_print("DML::%s: HostVMEnable %d\n", __func__, v->HostVMEnable);
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
new file mode 100644
index 0000000000000..b77a1ae792d12
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -0,0 +1,3835 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dc.h"
+#include "dc_link.h"
+#include "../display_mode_lib.h"
+#include "display_mode_vba_32.h"
+#include "../dml_inline_defs.h"
+#include "display_mode_vba_util_32.h"
+
+static const unsigned int NumberOfStates = DC__VOLTAGE_STATES;
+
+void dml32_recalculate(struct display_mode_lib *mode_lib);
+static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
+		struct display_mode_lib *mode_lib);
+void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);
+
+void dml32_recalculate(struct display_mode_lib *mode_lib)
+{
+	ModeSupportAndSystemConfiguration(mode_lib);
+
+	dml32_CalculateMaxDETAndMinCompressedBufferSize(mode_lib->vba.ConfigReturnBufferSizeInKByte,
+			mode_lib->vba.ROBBufferSizeInKByte,
+			DC__NUM_DPP,
+			false, //mode_lib->vba.override_setting.nomDETInKByteOverrideEnable,
+			0, //mode_lib->vba.override_setting.nomDETInKByteOverrideValue,
+
+			/* Output */
+			&mode_lib->vba.MaxTotalDETInKByte, &mode_lib->vba.nomDETInKByte,
+			&mode_lib->vba.MinCompressedBufferSizeInKByte);
+
+	PixelClockAdjustmentForProgressiveToInterlaceUnit(mode_lib);
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: Calling DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation\n", __func__);
+#endif
+	DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(mode_lib);
+}
+
+static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
+		struct display_mode_lib *mode_lib)
+{
+	struct vba_vars_st *v = &mode_lib->vba;
+	unsigned int j, k;
+	bool ImmediateFlipRequirementFinal;
+	int iteration;
+	double MaxTotalRDBandwidth;
+	unsigned int NextPrefetchMode;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: --- START ---\n", __func__);
+	dml_print("DML::%s: mode_lib->vba.PrefetchMode = %d\n", __func__, mode_lib->vba.PrefetchMode);
+	dml_print("DML::%s: mode_lib->vba.ImmediateFlipSupport = %d\n", __func__, mode_lib->vba.ImmediateFlipSupport);
+	dml_print("DML::%s: mode_lib->vba.VoltageLevel = %d\n", __func__, mode_lib->vba.VoltageLevel);
+#endif
+
+	v->WritebackDISPCLK = 0.0;
+	v->GlobalDPPCLK = 0.0;
+
+	// DISPCLK and DPPCLK Calculation
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		if (mode_lib->vba.WritebackEnable[k]) {
+			v->WritebackDISPCLK = dml_max(v->WritebackDISPCLK,
+					dml32_CalculateWriteBackDISPCLK(
+							mode_lib->vba.WritebackPixelFormat[k],
+							mode_lib->vba.PixelClock[k], mode_lib->vba.WritebackHRatio[k],
+							mode_lib->vba.WritebackVRatio[k],
+							mode_lib->vba.WritebackHTaps[k],
+							mode_lib->vba.WritebackVTaps[k],
+							mode_lib->vba.WritebackSourceWidth[k],
+							mode_lib->vba.WritebackDestinationWidth[k],
+							mode_lib->vba.HTotal[k], mode_lib->vba.WritebackLineBufferSize,
+							mode_lib->vba.DISPCLKDPPCLKVCOSpeed));
+		}
+	}
+
+	v->DISPCLK_calculated = v->WritebackDISPCLK;
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		if (mode_lib->vba.BlendingAndTiming[k] == k) {
+			v->DISPCLK_calculated = dml_max(v->DISPCLK_calculated,
+					dml32_CalculateRequiredDispclk(
+							mode_lib->vba.ODMCombineEnabled[k],
+							mode_lib->vba.PixelClock[k],
+							mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading,
+							mode_lib->vba.DISPCLKRampingMargin,
+							mode_lib->vba.DISPCLKDPPCLKVCOSpeed,
+							mode_lib->vba.MaxDppclk[v->soc.num_states - 1]));
+		}
+	}
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(mode_lib->vba.HRatio[k],
+				mode_lib->vba.HRatioChroma[k],
+				mode_lib->vba.VRatio[k],
+				mode_lib->vba.VRatioChroma[k],
+				mode_lib->vba.MaxDCHUBToPSCLThroughput,
+				mode_lib->vba.MaxPSCLToLBThroughput,
+				mode_lib->vba.PixelClock[k],
+				mode_lib->vba.SourcePixelFormat[k],
+				mode_lib->vba.htaps[k],
+				mode_lib->vba.HTAPsChroma[k],
+				mode_lib->vba.vtaps[k],
+				mode_lib->vba.VTAPsChroma[k],
+
+				/* Output */
+				&v->PSCL_THROUGHPUT_LUMA[k], &v->PSCL_THROUGHPUT_CHROMA[k],
+				&v->DPPCLKUsingSingleDPP[k]);
+	}
+
+	dml32_CalculateDPPCLK(mode_lib->vba.NumberOfActiveSurfaces, mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading,
+			mode_lib->vba.DISPCLKDPPCLKVCOSpeed, v->DPPCLKUsingSingleDPP, mode_lib->vba.DPPPerPlane,
+			/* Output */
+			&v->GlobalDPPCLK, v->DPPCLK);
+
+	for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
+		v->DPPCLK_calculated[k] = v->DPPCLK[k];
+	}
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		dml32_CalculateBytePerPixelAndBlockSizes(
+				mode_lib->vba.SourcePixelFormat[k],
+				mode_lib->vba.SurfaceTiling[k],
+
+				/* Output */
+				&v->BytePerPixelY[k],
+				&v->BytePerPixelC[k],
+				&v->BytePerPixelDETY[k],
+				&v->BytePerPixelDETC[k],
+				&v->BlockHeight256BytesY[k],
+				&v->BlockHeight256BytesC[k],
+				&v->BlockWidth256BytesY[k],
+				&v->BlockWidth256BytesC[k],
+				&v->BlockHeightY[k],
+				&v->BlockHeightC[k],
+				&v->BlockWidthY[k],
+				&v->BlockWidthC[k]);
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: %d\n", __func__, __LINE__);
+#endif
+	dml32_CalculateSwathWidth(
+			false,  // ForceSingleDPP
+			mode_lib->vba.NumberOfActiveSurfaces,
+			mode_lib->vba.SourcePixelFormat,
+			mode_lib->vba.SourceRotation,
+			mode_lib->vba.ViewportStationary,
+			mode_lib->vba.ViewportWidth,
+			mode_lib->vba.ViewportHeight,
+			mode_lib->vba.ViewportXStartY,
+			mode_lib->vba.ViewportYStartY,
+			mode_lib->vba.ViewportXStartC,
+			mode_lib->vba.ViewportYStartC,
+			mode_lib->vba.SurfaceWidthY,
+			mode_lib->vba.SurfaceWidthC,
+			mode_lib->vba.SurfaceHeightY,
+			mode_lib->vba.SurfaceHeightC,
+			mode_lib->vba.ODMCombineEnabled,
+			v->BytePerPixelY,
+			v->BytePerPixelC,
+			v->BlockHeight256BytesY,
+			v->BlockHeight256BytesC,
+			v->BlockWidth256BytesY,
+			v->BlockWidth256BytesC,
+			mode_lib->vba.BlendingAndTiming,
+			mode_lib->vba.HActive,
+			mode_lib->vba.HRatio,
+			mode_lib->vba.DPPPerPlane,
+
+			/* Output */
+			v->SwathWidthSingleDPPY, v->SwathWidthSingleDPPC, v->SwathWidthY, v->SwathWidthC,
+			v->dummy_vars
+				.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+				.dummy_integer_array[0], // Integer             MaximumSwathHeightY[]
+			v->dummy_vars
+				.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+				.dummy_integer_array[1], // Integer             MaximumSwathHeightC[]
+			v->swath_width_luma_ub, v->swath_width_chroma_ub);
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		v->ReadBandwidthSurfaceLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k]
+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
+		v->ReadBandwidthSurfaceChroma[k] = v->SwathWidthSingleDPPC[k] * v->BytePerPixelC[k]
+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
+				* mode_lib->vba.VRatioChroma[k];
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: ReadBandwidthSurfaceLuma[%i] = %fBps\n",
+				__func__, k, v->ReadBandwidthSurfaceLuma[k]);
+		dml_print("DML::%s: ReadBandwidthSurfaceChroma[%i] = %fBps\n",
+				__func__, k, v->ReadBandwidthSurfaceChroma[k]);
+#endif
+	}
+
+	{
+		// VBA_DELTA
+		// Calculate DET size, swath height
+		dml32_CalculateSwathAndDETConfiguration(
+				mode_lib->vba.DETSizeOverride,
+				mode_lib->vba.UsesMALLForPStateChange,
+				mode_lib->vba.ConfigReturnBufferSizeInKByte,
+				mode_lib->vba.MaxTotalDETInKByte,
+				mode_lib->vba.MinCompressedBufferSizeInKByte,
+				false, /* ForceSingleDPP */
+				mode_lib->vba.NumberOfActiveSurfaces,
+				mode_lib->vba.nomDETInKByte,
+				mode_lib->vba.UseUnboundedRequesting,
+				mode_lib->vba.CompressedBufferSegmentSizeInkByteFinal,
+				v->dummy_vars
+					.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+					.dummy_output_encoder_array, /* output_encoder_class Output[] */
+				v->ReadBandwidthSurfaceLuma,
+				v->ReadBandwidthSurfaceChroma,
+				v->dummy_vars
+					.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+					.dummy_single_array[0], /* Single MaximumSwathWidthLuma[] */
+				v->dummy_vars
+					.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+					.dummy_single_array[1], /* Single MaximumSwathWidthChroma[] */
+				mode_lib->vba.SourceRotation,
+				mode_lib->vba.ViewportStationary,
+				mode_lib->vba.SourcePixelFormat,
+				mode_lib->vba.SurfaceTiling,
+				mode_lib->vba.ViewportWidth,
+				mode_lib->vba.ViewportHeight,
+				mode_lib->vba.ViewportXStartY,
+				mode_lib->vba.ViewportYStartY,
+				mode_lib->vba.ViewportXStartC,
+				mode_lib->vba.ViewportYStartC,
+				mode_lib->vba.SurfaceWidthY,
+				mode_lib->vba.SurfaceWidthC,
+				mode_lib->vba.SurfaceHeightY,
+				mode_lib->vba.SurfaceHeightC,
+				v->BlockHeight256BytesY,
+				v->BlockHeight256BytesC,
+				v->BlockWidth256BytesY,
+				v->BlockWidth256BytesC,
+				mode_lib->vba.ODMCombineEnabled,
+				mode_lib->vba.BlendingAndTiming,
+				v->BytePerPixelY,
+				v->BytePerPixelC,
+				v->BytePerPixelDETY,
+				v->BytePerPixelDETC,
+				mode_lib->vba.HActive,
+				mode_lib->vba.HRatio,
+				mode_lib->vba.HRatioChroma,
+				mode_lib->vba.DPPPerPlane,
+
+				/* Output */
+				v->dummy_vars
+					.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+					.dummy_long_array[0], /* Long swath_width_luma_ub[] */
+				v->dummy_vars
+					.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+					.dummy_long_array[1], /* Long swath_width_chroma_ub[] */
+				v->dummy_vars
+					.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+					.dummy_double_array[0], /* Long SwathWidth[] */
+				v->dummy_vars
+					.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+					.dummy_double_array[1], /* Long SwathWidthChroma[] */
+				mode_lib->vba.SwathHeightY,
+				mode_lib->vba.SwathHeightC,
+				mode_lib->vba.DETBufferSizeInKByte,
+				mode_lib->vba.DETBufferSizeY,
+				mode_lib->vba.DETBufferSizeC,
+				&v->UnboundedRequestEnabled,
+				&v->CompressedBufferSizeInkByte,
+				v->dummy_vars
+					.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+					.dummy_boolean_array, /* bool ViewportSizeSupportPerSurface[] */
+				&v->dummy_vars
+					 .DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+					 .dummy_boolean); /* bool *ViewportSizeSupport */
+	}
+
+	// DCFCLK Deep Sleep
+	dml32_CalculateDCFCLKDeepSleep(
+			mode_lib->vba.NumberOfActiveSurfaces,
+			v->BytePerPixelY,
+			v->BytePerPixelC,
+			mode_lib->vba.VRatio,
+			mode_lib->vba.VRatioChroma,
+			v->SwathWidthY,
+			v->SwathWidthC,
+			mode_lib->vba.DPPPerPlane,
+			mode_lib->vba.HRatio,
+			mode_lib->vba.HRatioChroma,
+			mode_lib->vba.PixelClock,
+			v->PSCL_THROUGHPUT_LUMA,
+			v->PSCL_THROUGHPUT_CHROMA,
+			mode_lib->vba.DPPCLK,
+			v->ReadBandwidthSurfaceLuma,
+			v->ReadBandwidthSurfaceChroma,
+			mode_lib->vba.ReturnBusWidth,
+
+			/* Output */
+			&v->DCFCLKDeepSleep);
+
+	// DSCCLK
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
+			v->DSCCLK_calculated[k] = 0.0;
+		} else {
+			if (mode_lib->vba.OutputFormat[k] == dm_420)
+				mode_lib->vba.DSCFormatFactor = 2;
+			else if (mode_lib->vba.OutputFormat[k] == dm_444)
+				mode_lib->vba.DSCFormatFactor = 1;
+			else if (mode_lib->vba.OutputFormat[k] == dm_n422)
+				mode_lib->vba.DSCFormatFactor = 2;
+			else
+				mode_lib->vba.DSCFormatFactor = 1;
+			if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
+				v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 12
+						/ mode_lib->vba.DSCFormatFactor
+						/ (1 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100);
+			else if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
+				v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 6
+						/ mode_lib->vba.DSCFormatFactor
+						/ (1 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100);
+			else
+				v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 3
+						/ mode_lib->vba.DSCFormatFactor
+						/ (1 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100);
+		}
+	}
+
+	// DSC Delay
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		v->DSCDelay[k] = dml32_DSCDelayRequirement(mode_lib->vba.DSCEnabled[k],
+				mode_lib->vba.ODMCombineEnabled[k], mode_lib->vba.DSCInputBitPerComponent[k],
+				mode_lib->vba.OutputBpp[k], mode_lib->vba.HActive[k], mode_lib->vba.HTotal[k],
+				mode_lib->vba.NumberOfDSCSlices[k], mode_lib->vba.OutputFormat[k],
+				mode_lib->vba.Output[k], mode_lib->vba.PixelClock[k],
+				mode_lib->vba.PixelClockBackEnd[k]);
+	}
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
+		for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; ++j) // NumberOfSurfaces
+			if (j != k && mode_lib->vba.BlendingAndTiming[k] == j && mode_lib->vba.DSCEnabled[j])
+				v->DSCDelay[k] = v->DSCDelay[j];
+
+	//Immediate Flip
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		v->ImmediateFlipSupportedSurface[k] = mode_lib->vba.ImmediateFlipSupport
+				&& (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required);
+	}
+
+	// Prefetch
+	dml32_CalculateSurfaceSizeInMall(
+				mode_lib->vba.NumberOfActiveSurfaces,
+				mode_lib->vba.MALLAllocatedForDCNFinal,
+				mode_lib->vba.UseMALLForStaticScreen,
+				mode_lib->vba.DCCEnable,
+				mode_lib->vba.ViewportStationary,
+				mode_lib->vba.ViewportXStartY,
+				mode_lib->vba.ViewportYStartY,
+				mode_lib->vba.ViewportXStartC,
+				mode_lib->vba.ViewportYStartC,
+				mode_lib->vba.ViewportWidth,
+				mode_lib->vba.ViewportHeight,
+				v->BytePerPixelY,
+				mode_lib->vba.ViewportWidthChroma,
+				mode_lib->vba.ViewportHeightChroma,
+				v->BytePerPixelC,
+				mode_lib->vba.SurfaceWidthY,
+				mode_lib->vba.SurfaceWidthC,
+				mode_lib->vba.SurfaceHeightY,
+				mode_lib->vba.SurfaceHeightC,
+				v->BlockWidth256BytesY,
+				v->BlockWidth256BytesC,
+				v->BlockHeight256BytesY,
+				v->BlockHeight256BytesC,
+				v->BlockWidthY,
+				v->BlockWidthC,
+				v->BlockHeightY,
+				v->BlockHeightC,
+
+				/* Output */
+				v->SurfaceSizeInMALL,
+				&v->dummy_vars.
+				DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+				.dummy_boolean2); /* Boolean *ExceededMALLSize */
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].PixelClock = mode_lib->vba.PixelClock[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DPPPerSurface = mode_lib->vba.DPPPerPlane[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SourceRotation = mode_lib->vba.SourceRotation[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportHeight = mode_lib->vba.ViewportHeight[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportHeightChroma = mode_lib->vba.ViewportHeightChroma[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidth256BytesY = v->BlockWidth256BytesY[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeight256BytesY = v->BlockHeight256BytesY[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidth256BytesC = v->BlockWidth256BytesC[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeight256BytesC = v->BlockHeight256BytesC[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidthY = v->BlockWidthY[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeightY = v->BlockHeightY[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidthC = v->BlockWidthC[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeightC = v->BlockHeightC[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].InterlaceEnable = mode_lib->vba.Interlace[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].HTotal = mode_lib->vba.HTotal[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DCCEnable = mode_lib->vba.DCCEnable[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SurfaceTiling = mode_lib->vba.SurfaceTiling[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BytePerPixelY = v->BytePerPixelY[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BytePerPixelC = v->BytePerPixelC[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ProgressiveToInterlaceUnitInOPP = mode_lib->vba.ProgressiveToInterlaceUnitInOPP;
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VRatio = mode_lib->vba.VRatio[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VRatioChroma = mode_lib->vba.VRatioChroma[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VTaps = mode_lib->vba.vtaps[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VTapsChroma = mode_lib->vba.VTAPsChroma[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].PitchY = mode_lib->vba.PitchY[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DCCMetaPitchY = mode_lib->vba.DCCMetaPitchY[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].PitchC = mode_lib->vba.PitchC[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DCCMetaPitchC = mode_lib->vba.DCCMetaPitchC[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportStationary = mode_lib->vba.ViewportStationary[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportXStart = mode_lib->vba.ViewportXStartY[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportYStart = mode_lib->vba.ViewportYStartY[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportXStartC = mode_lib->vba.ViewportXStartC[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportYStartC = mode_lib->vba.ViewportYStartC[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].FORCE_ONE_ROW_FOR_FRAME = mode_lib->vba.ForceOneRowForFrame[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SwathHeightY = mode_lib->vba.SwathHeightY[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SwathHeightC = mode_lib->vba.SwathHeightC[k];
+	}
+
+	{
+
+		dml32_CalculateVMRowAndSwath(
+				mode_lib->vba.NumberOfActiveSurfaces,
+				v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters,
+				v->SurfaceSizeInMALL,
+				mode_lib->vba.PTEBufferSizeInRequestsLuma,
+				mode_lib->vba.PTEBufferSizeInRequestsChroma,
+				mode_lib->vba.DCCMetaBufferSizeBytes,
+				mode_lib->vba.UseMALLForStaticScreen,
+				mode_lib->vba.UsesMALLForPStateChange,
+				mode_lib->vba.MALLAllocatedForDCNFinal,
+				v->SwathWidthY,
+				v->SwathWidthC,
+				mode_lib->vba.GPUVMEnable,
+				mode_lib->vba.HostVMEnable,
+				mode_lib->vba.HostVMMaxNonCachedPageTableLevels,
+				mode_lib->vba.GPUVMMaxPageTableLevels,
+				mode_lib->vba.GPUVMMinPageSizeKBytes,
+				mode_lib->vba.HostVMMinPageSize,
+
+				/* Output */
+				v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_boolean_array2[0],  // Boolean PTEBufferSizeNotExceeded[]
+				v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_boolean_array2[1],  // Boolean DCCMetaBufferSizeNotExceeded[]
+				v->dpte_row_width_luma_ub,
+				v->dpte_row_width_chroma_ub,
+				v->dpte_row_height,
+				v->dpte_row_height_chroma,
+				v->dpte_row_height_linear,
+				v->dpte_row_height_linear_chroma,
+				v->meta_req_width,
+				v->meta_req_width_chroma,
+				v->meta_req_height,
+				v->meta_req_height_chroma,
+				v->meta_row_width,
+				v->meta_row_width_chroma,
+				v->meta_row_height,
+				v->meta_row_height_chroma,
+				v->vm_group_bytes,
+				v->dpte_group_bytes,
+				v->PixelPTEReqWidthY,
+				v->PixelPTEReqHeightY,
+				v->PTERequestSizeY,
+				v->PixelPTEReqWidthC,
+				v->PixelPTEReqHeightC,
+				v->PTERequestSizeC,
+				v->dpde0_bytes_per_frame_ub_l,
+				v->meta_pte_bytes_per_frame_ub_l,
+				v->dpde0_bytes_per_frame_ub_c,
+				v->meta_pte_bytes_per_frame_ub_c,
+				v->PrefetchSourceLinesY,
+				v->PrefetchSourceLinesC,
+				v->VInitPreFillY, v->VInitPreFillC,
+				v->MaxNumSwathY,
+				v->MaxNumSwathC,
+				v->meta_row_bw,
+				v->dpte_row_bw,
+				v->PixelPTEBytesPerRow,
+				v->PDEAndMetaPTEBytesFrame,
+				v->MetaRowByte,
+				v->Use_One_Row_For_Frame,
+				v->Use_One_Row_For_Frame_Flip,
+				v->UsesMALLForStaticScreen,
+				v->PTE_BUFFER_MODE,
+				v->BIGK_FRAGMENT_SIZE);
+	}
+
+
+	v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.ReorderBytes = mode_lib->vba.NumberOfChannels
+			* dml_max3(mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly,
+					mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData,
+					mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly);
+
+	v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.VMDataOnlyReturnBW = dml32_get_return_bw_mbps_vm_only(
+			&mode_lib->vba.soc,
+			mode_lib->vba.VoltageLevel,
+			mode_lib->vba.DCFCLK,
+			mode_lib->vba.FabricClock,
+			mode_lib->vba.DRAMSpeed);
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: mode_lib->vba.ReturnBusWidth = %f\n", __func__, mode_lib->vba.ReturnBusWidth);
+	dml_print("DML::%s: mode_lib->vba.DCFCLK = %f\n", __func__, mode_lib->vba.DCFCLK);
+	dml_print("DML::%s: mode_lib->vba.FabricClock = %f\n", __func__, mode_lib->vba.FabricClock);
+	dml_print("DML::%s: mode_lib->vba.FabricDatapathToDCNDataReturn = %f\n", __func__,
+			mode_lib->vba.FabricDatapathToDCNDataReturn);
+	dml_print("DML::%s: mode_lib->vba.PercentOfIdealSDPPortBWReceivedAfterUrgLatency = %f\n",
+			__func__, mode_lib->vba.PercentOfIdealSDPPortBWReceivedAfterUrgLatency);
+	dml_print("DML::%s: mode_lib->vba.DRAMSpeed = %f\n", __func__, mode_lib->vba.DRAMSpeed);
+	dml_print("DML::%s: mode_lib->vba.NumberOfChannels = %f\n", __func__, mode_lib->vba.NumberOfChannels);
+	dml_print("DML::%s: mode_lib->vba.DRAMChannelWidth = %f\n", __func__, mode_lib->vba.DRAMChannelWidth);
+	dml_print("DML::%s: mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly = %f\n",
+			__func__, mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly);
+	dml_print("DML::%s: VMDataOnlyReturnBW = %f\n", __func__, VMDataOnlyReturnBW);
+	dml_print("DML::%s: ReturnBW = %f\n", __func__, mode_lib->vba.ReturnBW);
+#endif
+
+	v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor = 1.0;
+
+	if (mode_lib->vba.GPUVMEnable && mode_lib->vba.HostVMEnable)
+		v->dummy_vars
+			.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+			.HostVMInefficiencyFactor =
+			mode_lib->vba.ReturnBW / v->dummy_vars
+				.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+				.VMDataOnlyReturnBW;
+
+	mode_lib->vba.TotalDCCActiveDPP = 0;
+	mode_lib->vba.TotalActiveDPP = 0;
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP + mode_lib->vba.DPPPerPlane[k];
+		if (mode_lib->vba.DCCEnable[k])
+			mode_lib->vba.TotalDCCActiveDPP = mode_lib->vba.TotalDCCActiveDPP
+					+ mode_lib->vba.DPPPerPlane[k];
+	}
+
+	v->UrgentExtraLatency = dml32_CalculateExtraLatency(
+			mode_lib->vba.RoundTripPingLatencyCycles,
+			v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.ReorderBytes,
+			mode_lib->vba.DCFCLK,
+			mode_lib->vba.TotalActiveDPP,
+			mode_lib->vba.PixelChunkSizeInKByte,
+			mode_lib->vba.TotalDCCActiveDPP,
+			mode_lib->vba.MetaChunkSize,
+			mode_lib->vba.ReturnBW,
+			mode_lib->vba.GPUVMEnable,
+			mode_lib->vba.HostVMEnable,
+			mode_lib->vba.NumberOfActiveSurfaces,
+			mode_lib->vba.DPPPerPlane,
+			v->dpte_group_bytes,
+			v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor,
+			mode_lib->vba.HostVMMinPageSize,
+			mode_lib->vba.HostVMMaxNonCachedPageTableLevels);
+
+	mode_lib->vba.TCalc = 24.0 / v->DCFCLKDeepSleep;
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		if (mode_lib->vba.BlendingAndTiming[k] == k) {
+			if (mode_lib->vba.WritebackEnable[k] == true) {
+				v->WritebackDelay[mode_lib->vba.VoltageLevel][k] = mode_lib->vba.WritebackLatency
+						+ dml32_CalculateWriteBackDelay(
+								mode_lib->vba.WritebackPixelFormat[k],
+								mode_lib->vba.WritebackHRatio[k],
+								mode_lib->vba.WritebackVRatio[k],
+								mode_lib->vba.WritebackVTaps[k],
+								mode_lib->vba.WritebackDestinationWidth[k],
+								mode_lib->vba.WritebackDestinationHeight[k],
+								mode_lib->vba.WritebackSourceHeight[k],
+								mode_lib->vba.HTotal[k]) / mode_lib->vba.DISPCLK;
+			} else
+				v->WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0;
+			for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; ++j) {
+				if (mode_lib->vba.BlendingAndTiming[j] == k &&
+					mode_lib->vba.WritebackEnable[j] == true) {
+					v->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
+						dml_max(v->WritebackDelay[mode_lib->vba.VoltageLevel][k],
+						mode_lib->vba.WritebackLatency +
+						dml32_CalculateWriteBackDelay(
+								mode_lib->vba.WritebackPixelFormat[j],
+								mode_lib->vba.WritebackHRatio[j],
+								mode_lib->vba.WritebackVRatio[j],
+								mode_lib->vba.WritebackVTaps[j],
+								mode_lib->vba.WritebackDestinationWidth[j],
+								mode_lib->vba.WritebackDestinationHeight[j],
+								mode_lib->vba.WritebackSourceHeight[j],
+								mode_lib->vba.HTotal[k]) / mode_lib->vba.DISPCLK);
+				}
+			}
+		}
+	}
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
+		for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; ++j)
+			if (mode_lib->vba.BlendingAndTiming[k] == j)
+				v->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
+						v->WritebackDelay[mode_lib->vba.VoltageLevel][j];
+
+	v->UrgentLatency = dml32_CalculateUrgentLatency(mode_lib->vba.UrgentLatencyPixelDataOnly,
+			mode_lib->vba.UrgentLatencyPixelMixedWithVMData,
+			mode_lib->vba.UrgentLatencyVMDataOnly,
+			mode_lib->vba.DoUrgentLatencyAdjustment,
+			mode_lib->vba.UrgentLatencyAdjustmentFabricClockComponent,
+			mode_lib->vba.UrgentLatencyAdjustmentFabricClockReference,
+			mode_lib->vba.FabricClock);
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		dml32_CalculateUrgentBurstFactor(mode_lib->vba.UsesMALLForPStateChange[k],
+				v->swath_width_luma_ub[k],
+				v->swath_width_chroma_ub[k],
+				mode_lib->vba.SwathHeightY[k],
+				mode_lib->vba.SwathHeightC[k],
+				mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
+				v->UrgentLatency,
+				mode_lib->vba.CursorBufferSize,
+				mode_lib->vba.CursorWidth[k][0],
+				mode_lib->vba.CursorBPP[k][0],
+				mode_lib->vba.VRatio[k],
+				mode_lib->vba.VRatioChroma[k],
+				v->BytePerPixelDETY[k],
+				v->BytePerPixelDETC[k],
+				mode_lib->vba.DETBufferSizeY[k],
+				mode_lib->vba.DETBufferSizeC[k],
+
+				/* output */
+				&v->UrgBurstFactorCursor[k],
+				&v->UrgBurstFactorLuma[k],
+				&v->UrgBurstFactorChroma[k],
+				&v->NoUrgentLatencyHiding[k]);
+
+		v->cursor_bw[k] = mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0] * mode_lib->vba.CursorBPP[k][0] / 8 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
+	}
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		v->MaxVStartupLines[k] = ((mode_lib->vba.Interlace[k] &&
+				!mode_lib->vba.ProgressiveToInterlaceUnitInOPP) ?
+				dml_floor((mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]) / 2.0, 1.0) :
+				mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]) - dml_max(1.0,
+				dml_ceil((double) v->WritebackDelay[mode_lib->vba.VoltageLevel][k]
+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1));
+
+	// Clamp to max OTG vstartup register limit
+	if (v->MaxVStartupLines[k] > 1023)
+		v->MaxVStartupLines[k] = 1023;
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
+		dml_print("DML::%s: k=%d VoltageLevel = %d\n", __func__, k, mode_lib->vba.VoltageLevel);
+		dml_print("DML::%s: k=%d WritebackDelay = %f\n", __func__,
+				k, v->WritebackDelay[mode_lib->vba.VoltageLevel][k]);
+#endif
+	}
+
+	v->MaximumMaxVStartupLines = 0;
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
+		v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]);
+
+	ImmediateFlipRequirementFinal = false;
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		ImmediateFlipRequirementFinal = ImmediateFlipRequirementFinal
+				|| (mode_lib->vba.ImmediateFlipRequirement[k] == dm_immediate_flip_required);
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: ImmediateFlipRequirementFinal = %d\n", __func__, ImmediateFlipRequirementFinal);
+#endif
+	// ModeProgramming will not repeat the schedule calculation using different prefetch mode,
+	//it is just calcualated once with given prefetch mode
+	dml32_CalculateMinAndMaxPrefetchMode(
+			mode_lib->vba.AllowForPStateChangeOrStutterInVBlankFinal,
+			&mode_lib->vba.MinPrefetchMode,
+			&mode_lib->vba.MaxPrefetchMode);
+
+	v->VStartupLines = __DML_VBA_MIN_VSTARTUP__;
+
+	iteration = 0;
+	MaxTotalRDBandwidth = 0;
+	NextPrefetchMode = mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb];
+
+	do {
+		double MaxTotalRDBandwidthNoUrgentBurst = 0.0;
+		bool DestinationLineTimesForPrefetchLessThan2 = false;
+		bool VRatioPrefetchMoreThanMax = false;
+		double dummy_unit_vector[DC__NUM_DPP__MAX];
+
+		MaxTotalRDBandwidth = 0;
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: Start loop: VStartup = %d\n", __func__, mode_lib->vba.VStartupLines);
+#endif
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			/* NOTE PerfetchMode variable is invalid in DAL as per the input received.
+			 * Hence the direction is to use PrefetchModePerState.
+			 */
+			double TWait = dml32_CalculateTWait(
+					mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
+					mode_lib->vba.UsesMALLForPStateChange[k],
+					mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+					mode_lib->vba.DRRDisplay[k],
+					mode_lib->vba.DRAMClockChangeLatency,
+					mode_lib->vba.FCLKChangeLatency, v->UrgentLatency,
+					mode_lib->vba.SREnterPlusExitTime);
+
+			DmlPipe myPipe;
+
+			myPipe.Dppclk = mode_lib->vba.DPPCLK[k];
+			myPipe.Dispclk = mode_lib->vba.DISPCLK;
+			myPipe.PixelClock = mode_lib->vba.PixelClock[k];
+			myPipe.DCFClkDeepSleep = v->DCFCLKDeepSleep;
+			myPipe.DPPPerSurface = mode_lib->vba.DPPPerPlane[k];
+			myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k];
+			myPipe.SourceRotation = mode_lib->vba.SourceRotation[k];
+			myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k];
+			myPipe.BlockHeight256BytesY = v->BlockHeight256BytesY[k];
+			myPipe.BlockWidth256BytesC = v->BlockWidth256BytesC[k];
+			myPipe.BlockHeight256BytesC = v->BlockHeight256BytesC[k];
+			myPipe.InterlaceEnable = mode_lib->vba.Interlace[k];
+			myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k];
+			myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k];
+			myPipe.HTotal = mode_lib->vba.HTotal[k];
+			myPipe.HActive = mode_lib->vba.HActive[k];
+			myPipe.DCCEnable = mode_lib->vba.DCCEnable[k];
+			myPipe.ODMMode = mode_lib->vba.ODMCombineEnabled[k];
+			myPipe.SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k];
+			myPipe.BytePerPixelY = v->BytePerPixelY[k];
+			myPipe.BytePerPixelC = v->BytePerPixelC[k];
+			myPipe.ProgressiveToInterlaceUnitInOPP = mode_lib->vba.ProgressiveToInterlaceUnitInOPP;
+			v->ErrorResult[k] = dml32_CalculatePrefetchSchedule(v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor,
+					&myPipe, v->DSCDelay[k],
+					mode_lib->vba.DPPCLKDelaySubtotal + mode_lib->vba.DPPCLKDelayCNVCFormater,
+					mode_lib->vba.DPPCLKDelaySCL,
+					mode_lib->vba.DPPCLKDelaySCLLBOnly,
+					mode_lib->vba.DPPCLKDelayCNVCCursor,
+					mode_lib->vba.DISPCLKDelaySubtotal,
+					(unsigned int) (v->SwathWidthY[k] / mode_lib->vba.HRatio[k]),
+					mode_lib->vba.OutputFormat[k],
+					mode_lib->vba.MaxInterDCNTileRepeaters,
+					dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
+					v->MaxVStartupLines[k],
+					mode_lib->vba.GPUVMMaxPageTableLevels,
+					mode_lib->vba.GPUVMEnable,
+					mode_lib->vba.HostVMEnable,
+					mode_lib->vba.HostVMMaxNonCachedPageTableLevels,
+					mode_lib->vba.HostVMMinPageSize,
+					mode_lib->vba.DynamicMetadataEnable[k],
+					mode_lib->vba.DynamicMetadataVMEnabled,
+					mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
+					mode_lib->vba.DynamicMetadataTransmittedBytes[k],
+					v->UrgentLatency,
+					v->UrgentExtraLatency,
+					mode_lib->vba.TCalc,
+					v->PDEAndMetaPTEBytesFrame[k],
+					v->MetaRowByte[k],
+					v->PixelPTEBytesPerRow[k],
+					v->PrefetchSourceLinesY[k],
+					v->SwathWidthY[k],
+					v->VInitPreFillY[k],
+					v->MaxNumSwathY[k],
+					v->PrefetchSourceLinesC[k],
+					v->SwathWidthC[k],
+					v->VInitPreFillC[k],
+					v->MaxNumSwathC[k],
+					v->swath_width_luma_ub[k],
+					v->swath_width_chroma_ub[k],
+					mode_lib->vba.SwathHeightY[k],
+					mode_lib->vba.SwathHeightC[k],
+					TWait,
+					/* Output */
+					&v->DSTXAfterScaler[k],
+					&v->DSTYAfterScaler[k],
+					&v->DestinationLinesForPrefetch[k],
+					&v->PrefetchBandwidth[k],
+					&v->DestinationLinesToRequestVMInVBlank[k],
+					&v->DestinationLinesToRequestRowInVBlank[k],
+					&v->VRatioPrefetchY[k],
+					&v->VRatioPrefetchC[k],
+					&v->RequiredPrefetchPixDataBWLuma[k],
+					&v->RequiredPrefetchPixDataBWChroma[k],
+					&v->NotEnoughTimeForDynamicMetadata[k],
+					&v->Tno_bw[k], &v->prefetch_vmrow_bw[k],
+					&v->Tdmdl_vm[k],
+					&v->Tdmdl[k],
+					&v->TSetup[k],
+					&v->VUpdateOffsetPix[k],
+					&v->VUpdateWidthPix[k],
+					&v->VReadyOffsetPix[k]);
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%0d Prefetch calculation errResult=%0d\n",
+					__func__, k, mode_lib->vba.ErrorResult[k]);
+#endif
+			v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]);
+		}
+
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			dml32_CalculateUrgentBurstFactor(mode_lib->vba.UsesMALLForPStateChange[k],
+					v->swath_width_luma_ub[k],
+					v->swath_width_chroma_ub[k],
+					mode_lib->vba.SwathHeightY[k],
+					mode_lib->vba.SwathHeightC[k],
+					mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
+					v->UrgentLatency,
+					mode_lib->vba.CursorBufferSize,
+					mode_lib->vba.CursorWidth[k][0],
+					mode_lib->vba.CursorBPP[k][0],
+					v->VRatioPrefetchY[k],
+					v->VRatioPrefetchC[k],
+					v->BytePerPixelDETY[k],
+					v->BytePerPixelDETC[k],
+					mode_lib->vba.DETBufferSizeY[k],
+					mode_lib->vba.DETBufferSizeC[k],
+					/* Output */
+					&v->UrgBurstFactorCursorPre[k],
+					&v->UrgBurstFactorLumaPre[k],
+					&v->UrgBurstFactorChromaPre[k],
+					&v->NoUrgentLatencyHidingPre[k]);
+
+			v->cursor_bw_pre[k] = mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0] * mode_lib->vba.CursorBPP[k][0] /
+					8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * v->VRatioPrefetchY[k];
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%0d DPPPerSurface=%d\n", __func__, k, mode_lib->vba.DPPPerPlane[k]);
+			dml_print("DML::%s: k=%0d UrgBurstFactorLuma=%f\n", __func__, k, v->UrgBurstFactorLuma[k]);
+			dml_print("DML::%s: k=%0d UrgBurstFactorChroma=%f\n", __func__, k, v->UrgBurstFactorChroma[k]);
+			dml_print("DML::%s: k=%0d UrgBurstFactorLumaPre=%f\n", __func__, k,
+					v->UrgBurstFactorLumaPre[k]);
+			dml_print("DML::%s: k=%0d UrgBurstFactorChromaPre=%f\n", __func__, k,
+					v->UrgBurstFactorChromaPre[k]);
+
+			dml_print("DML::%s: k=%0d VRatioPrefetchY=%f\n", __func__, k, v->VRatioPrefetchY[k]);
+			dml_print("DML::%s: k=%0d VRatioY=%f\n", __func__, k, mode_lib->vba.VRatio[k]);
+
+			dml_print("DML::%s: k=%0d prefetch_vmrow_bw=%f\n", __func__, k, v->prefetch_vmrow_bw[k]);
+			dml_print("DML::%s: k=%0d ReadBandwidthSurfaceLuma=%f\n", __func__, k,
+					v->ReadBandwidthSurfaceLuma[k]);
+			dml_print("DML::%s: k=%0d ReadBandwidthSurfaceChroma=%f\n", __func__, k,
+					v->ReadBandwidthSurfaceChroma[k]);
+			dml_print("DML::%s: k=%0d cursor_bw=%f\n", __func__, k, v->cursor_bw[k]);
+			dml_print("DML::%s: k=%0d meta_row_bw=%f\n", __func__, k, v->meta_row_bw[k]);
+			dml_print("DML::%s: k=%0d dpte_row_bw=%f\n", __func__, k, v->dpte_row_bw[k]);
+			dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWLuma=%f\n", __func__, k,
+					v->RequiredPrefetchPixDataBWLuma[k]);
+			dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWChroma=%f\n", __func__, k,
+					v->RequiredPrefetchPixDataBWChroma[k]);
+			dml_print("DML::%s: k=%0d cursor_bw_pre=%f\n", __func__, k, v->cursor_bw_pre[k]);
+			dml_print("DML::%s: k=%0d MaxTotalRDBandwidthNoUrgentBurst=%f\n", __func__, k,
+					MaxTotalRDBandwidthNoUrgentBurst);
+#endif
+			if (v->DestinationLinesForPrefetch[k] < 2)
+				DestinationLineTimesForPrefetchLessThan2 = true;
+
+			if (v->VRatioPrefetchY[k] > __DML_MAX_VRATIO_PRE__
+					|| v->VRatioPrefetchC[k] > __DML_MAX_VRATIO_PRE__)
+				VRatioPrefetchMoreThanMax = true;
+
+			//bool DestinationLinesToRequestVMInVBlankEqualOrMoreThan32 = false;
+			//bool DestinationLinesToRequestRowInVBlankEqualOrMoreThan16 = false;
+			//if (v->DestinationLinesToRequestVMInVBlank[k] >= 32) {
+			//    DestinationLinesToRequestVMInVBlankEqualOrMoreThan32 = true;
+			//}
+
+			//if (v->DestinationLinesToRequestRowInVBlank[k] >= 16) {
+			//    DestinationLinesToRequestRowInVBlankEqualOrMoreThan16 = true;
+			//}
+		}
+
+		v->FractionOfUrgentBandwidth = MaxTotalRDBandwidthNoUrgentBurst / mode_lib->vba.ReturnBW;
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: MaxTotalRDBandwidthNoUrgentBurst=%f\n",
+				__func__, MaxTotalRDBandwidthNoUrgentBurst);
+		dml_print("DML::%s: ReturnBW=%f\n", __func__, mode_lib->vba.ReturnBW);
+		dml_print("DML::%s: FractionOfUrgentBandwidth=%f\n",
+				__func__, mode_lib->vba.FractionOfUrgentBandwidth);
+#endif
+
+		{
+			double dummy_single[1];
+
+			dml32_CalculatePrefetchBandwithSupport(
+					mode_lib->vba.NumberOfActiveSurfaces,
+					mode_lib->vba.ReturnBW,
+					v->NoUrgentLatencyHidingPre,
+					v->ReadBandwidthSurfaceLuma,
+					v->ReadBandwidthSurfaceChroma,
+					v->RequiredPrefetchPixDataBWLuma,
+					v->RequiredPrefetchPixDataBWChroma,
+					v->cursor_bw,
+					v->meta_row_bw,
+					v->dpte_row_bw,
+					v->cursor_bw_pre,
+					v->prefetch_vmrow_bw,
+					mode_lib->vba.DPPPerPlane,
+					v->UrgBurstFactorLuma,
+					v->UrgBurstFactorChroma,
+					v->UrgBurstFactorCursor,
+					v->UrgBurstFactorLumaPre,
+					v->UrgBurstFactorChromaPre,
+					v->UrgBurstFactorCursorPre,
+
+					/* output */
+					&MaxTotalRDBandwidth,
+					&dummy_single[0],
+					&v->PrefetchModeSupported);
+		}
+
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
+			dummy_unit_vector[k] = 1.0;
+
+		{
+			double  dummy_single[1];
+			bool dummy_boolean[1];
+			dml32_CalculatePrefetchBandwithSupport(mode_lib->vba.NumberOfActiveSurfaces,
+					mode_lib->vba.ReturnBW,
+					v->NoUrgentLatencyHidingPre,
+					v->ReadBandwidthSurfaceLuma,
+					v->ReadBandwidthSurfaceChroma,
+					v->RequiredPrefetchPixDataBWLuma,
+					v->RequiredPrefetchPixDataBWChroma,
+					v->cursor_bw,
+					v->meta_row_bw,
+					v->dpte_row_bw,
+					v->cursor_bw_pre,
+					v->prefetch_vmrow_bw,
+					mode_lib->vba.DPPPerPlane,
+					dummy_unit_vector,
+					dummy_unit_vector,
+					dummy_unit_vector,
+					dummy_unit_vector,
+					dummy_unit_vector,
+					dummy_unit_vector,
+
+					/* output */
+					&dummy_single[0],
+					&v->FractionOfUrgentBandwidth,
+					&dummy_boolean[0]);
+		}
+
+		if (VRatioPrefetchMoreThanMax != false || DestinationLineTimesForPrefetchLessThan2 != false) {
+			v->PrefetchModeSupported = false;
+		}
+
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			if (v->ErrorResult[k] == true || v->NotEnoughTimeForDynamicMetadata[k]) {
+				v->PrefetchModeSupported = false;
+			}
+		}
+
+		if (v->PrefetchModeSupported == true && mode_lib->vba.ImmediateFlipSupport == true) {
+			mode_lib->vba.BandwidthAvailableForImmediateFlip = dml32_CalculateBandwidthAvailableForImmediateFlip(
+					mode_lib->vba.NumberOfActiveSurfaces,
+					mode_lib->vba.ReturnBW,
+					v->ReadBandwidthSurfaceLuma,
+					v->ReadBandwidthSurfaceChroma,
+					v->RequiredPrefetchPixDataBWLuma,
+					v->RequiredPrefetchPixDataBWChroma,
+					v->cursor_bw,
+					v->cursor_bw_pre,
+					mode_lib->vba.DPPPerPlane,
+					v->UrgBurstFactorLuma,
+					v->UrgBurstFactorChroma,
+					v->UrgBurstFactorCursor,
+					v->UrgBurstFactorLumaPre,
+					v->UrgBurstFactorChromaPre,
+					v->UrgBurstFactorCursorPre);
+
+			mode_lib->vba.TotImmediateFlipBytes = 0;
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				if (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required) {
+					mode_lib->vba.TotImmediateFlipBytes = mode_lib->vba.TotImmediateFlipBytes
+							+ mode_lib->vba.DPPPerPlane[k]
+									* (v->PDEAndMetaPTEBytesFrame[k]
+											+ v->MetaRowByte[k]);
+					if (v->use_one_row_for_frame_flip[k]) {
+						mode_lib->vba.TotImmediateFlipBytes =
+								mode_lib->vba.TotImmediateFlipBytes
+										+ 2 * v->PixelPTEBytesPerRow[k];
+					} else {
+						mode_lib->vba.TotImmediateFlipBytes =
+								mode_lib->vba.TotImmediateFlipBytes
+										+ v->PixelPTEBytesPerRow[k];
+					}
+				}
+			}
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				dml32_CalculateFlipSchedule(v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor,
+						v->UrgentExtraLatency,
+						v->UrgentLatency,
+						mode_lib->vba.GPUVMMaxPageTableLevels,
+						mode_lib->vba.HostVMEnable,
+						mode_lib->vba.HostVMMaxNonCachedPageTableLevels,
+						mode_lib->vba.GPUVMEnable,
+						mode_lib->vba.HostVMMinPageSize,
+						v->PDEAndMetaPTEBytesFrame[k],
+						v->MetaRowByte[k],
+						v->PixelPTEBytesPerRow[k],
+						mode_lib->vba.BandwidthAvailableForImmediateFlip,
+						mode_lib->vba.TotImmediateFlipBytes,
+						mode_lib->vba.SourcePixelFormat[k],
+						mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
+						mode_lib->vba.VRatio[k],
+						mode_lib->vba.VRatioChroma[k],
+						v->Tno_bw[k],
+						mode_lib->vba.DCCEnable[k],
+						v->dpte_row_height[k],
+						v->meta_row_height[k],
+						v->dpte_row_height_chroma[k],
+						v->meta_row_height_chroma[k],
+						v->Use_One_Row_For_Frame_Flip[k],
+
+						/* Output */
+						&v->DestinationLinesToRequestVMInImmediateFlip[k],
+						&v->DestinationLinesToRequestRowInImmediateFlip[k],
+						&v->final_flip_bw[k],
+						&v->ImmediateFlipSupportedForPipe[k]);
+			}
+
+			{
+				double  dummy_single[2];
+				bool dummy_boolean[1];
+				dml32_CalculateImmediateFlipBandwithSupport(mode_lib->vba.NumberOfActiveSurfaces,
+						mode_lib->vba.ReturnBW,
+						mode_lib->vba.ImmediateFlipRequirement,
+						v->final_flip_bw,
+						v->ReadBandwidthSurfaceLuma,
+						v->ReadBandwidthSurfaceChroma,
+						v->RequiredPrefetchPixDataBWLuma,
+						v->RequiredPrefetchPixDataBWChroma,
+						v->cursor_bw,
+						v->meta_row_bw,
+						v->dpte_row_bw,
+						v->cursor_bw_pre,
+						v->prefetch_vmrow_bw,
+						mode_lib->vba.DPPPerPlane,
+						v->UrgBurstFactorLuma,
+						v->UrgBurstFactorChroma,
+						v->UrgBurstFactorCursor,
+						v->UrgBurstFactorLumaPre,
+						v->UrgBurstFactorChromaPre,
+						v->UrgBurstFactorCursorPre,
+
+						/* output */
+						&v->total_dcn_read_bw_with_flip,    // Single  *TotalBandwidth
+						&dummy_single[0],                        // Single  *FractionOfUrgentBandwidth
+						&v->ImmediateFlipSupported);        // Boolean *ImmediateFlipBandwidthSupport
+
+				dml32_CalculateImmediateFlipBandwithSupport(mode_lib->vba.NumberOfActiveSurfaces,
+						mode_lib->vba.ReturnBW,
+						mode_lib->vba.ImmediateFlipRequirement,
+						v->final_flip_bw,
+						v->ReadBandwidthSurfaceLuma,
+						v->ReadBandwidthSurfaceChroma,
+						v->RequiredPrefetchPixDataBWLuma,
+						v->RequiredPrefetchPixDataBWChroma,
+						v->cursor_bw,
+						v->meta_row_bw,
+						v->dpte_row_bw,
+						v->cursor_bw_pre,
+						v->prefetch_vmrow_bw,
+						mode_lib->vba.DPPPerPlane,
+						dummy_unit_vector,
+						dummy_unit_vector,
+						dummy_unit_vector,
+						dummy_unit_vector,
+						dummy_unit_vector,
+						dummy_unit_vector,
+
+						/* output */
+						&dummy_single[1],                                // Single  *TotalBandwidth
+						&v->FractionOfUrgentBandwidthImmediateFlip, // Single  *FractionOfUrgentBandwidth
+						&dummy_boolean[0]);                              // Boolean *ImmediateFlipBandwidthSupport
+			}
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				if (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required && v->ImmediateFlipSupportedForPipe[k] == false) {
+					v->ImmediateFlipSupported = false;
+#ifdef __DML_VBA_DEBUG__
+					dml_print("DML::%s: Pipe %0d not supporing iflip\n", __func__, k);
+#endif
+				}
+			}
+		} else {
+			v->ImmediateFlipSupported = false;
+		}
+
+		/* consider flip support is okay if the flip bw is ok or (when user does't require a iflip and there is no host vm) */
+		v->PrefetchAndImmediateFlipSupported = (v->PrefetchModeSupported == true &&
+				((!mode_lib->vba.ImmediateFlipSupport && !mode_lib->vba.HostVMEnable && !ImmediateFlipRequirementFinal) ||
+						v->ImmediateFlipSupported)) ? true : false;
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: PrefetchModeSupported = %d\n", __func__, locals->PrefetchModeSupported);
+		for (uint k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
+			dml_print("DML::%s: ImmediateFlipRequirement[%d] = %d\n", __func__, k,  mode_lib->vba.ImmediateFlipRequirement[k] == dm_immediate_flip_required);
+		dml_print("DML::%s: ImmediateFlipSupported = %d\n", __func__, locals->ImmediateFlipSupported);
+		dml_print("DML::%s: ImmediateFlipSupport = %d\n", __func__, mode_lib->vba.ImmediateFlipSupport);
+		dml_print("DML::%s: HostVMEnable = %d\n", __func__, mode_lib->vba.HostVMEnable);
+		dml_print("DML::%s: PrefetchAndImmediateFlipSupported = %d\n", __func__, locals->PrefetchAndImmediateFlipSupported);
+		dml_print("DML::%s: Done loop: Vstartup=%d, Max Vstartup=%d\n", __func__, locals->VStartupLines, locals->MaximumMaxVStartupLines);
+#endif
+
+		v->VStartupLines = v->VStartupLines + 1;
+
+		if (v->VStartupLines > v->MaximumMaxVStartupLines) {
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: Vstartup exceeds max vstartup, exiting loop\n", __func__);
+#endif
+			break; // VBA_DELTA: Implementation divergence! Gabe is *still* iterating across prefetch modes which we don't care to do
+		}
+		iteration++;
+		if (iteration > 2500) {
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: too many errors, exit now\n", __func__);
+			assert(0);
+#endif
+		}
+	} while (!(v->PrefetchAndImmediateFlipSupported || NextPrefetchMode > mode_lib->vba.MaxPrefetchMode));
+
+
+	if (v->VStartupLines <= v->MaximumMaxVStartupLines) {
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: Good, Prefetch and flip scheduling found solution at VStartupLines=%d\n", __func__, locals->VStartupLines-1);
+#endif
+	}
+
+
+	//Watermarks and NB P-State/DRAM Clock Change Support
+	{
+		SOCParametersList mmSOCParameters;
+		enum clock_change_support dummy_dramchange_support;
+		enum dm_fclock_change_support dummy_fclkchange_support;
+		bool dummy_USRRetrainingSupport;
+
+		mmSOCParameters.UrgentLatency = v->UrgentLatency;
+		mmSOCParameters.ExtraLatency = v->UrgentExtraLatency;
+		mmSOCParameters.WritebackLatency = mode_lib->vba.WritebackLatency;
+		mmSOCParameters.DRAMClockChangeLatency = mode_lib->vba.DRAMClockChangeLatency;
+		mmSOCParameters.FCLKChangeLatency = mode_lib->vba.FCLKChangeLatency;
+		mmSOCParameters.SRExitTime = mode_lib->vba.SRExitTime;
+		mmSOCParameters.SREnterPlusExitTime = mode_lib->vba.SREnterPlusExitTime;
+		mmSOCParameters.SRExitZ8Time = mode_lib->vba.SRExitZ8Time;
+		mmSOCParameters.SREnterPlusExitZ8Time = mode_lib->vba.SREnterPlusExitZ8Time;
+		mmSOCParameters.USRRetrainingLatency = mode_lib->vba.USRRetrainingLatency;
+		mmSOCParameters.SMNLatency = mode_lib->vba.SMNLatency;
+
+		dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
+			mode_lib->vba.USRRetrainingRequiredFinal,
+			mode_lib->vba.UsesMALLForPStateChange,
+			mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
+			mode_lib->vba.NumberOfActiveSurfaces,
+			mode_lib->vba.MaxLineBufferLines,
+			mode_lib->vba.LineBufferSizeFinal,
+			mode_lib->vba.WritebackInterfaceBufferSize,
+			mode_lib->vba.DCFCLK,
+			mode_lib->vba.ReturnBW,
+			mode_lib->vba.SynchronizeTimingsFinal,
+			mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+			mode_lib->vba.DRRDisplay,
+			v->dpte_group_bytes,
+			v->meta_row_height,
+			v->meta_row_height_chroma,
+			mmSOCParameters,
+			mode_lib->vba.WritebackChunkSize,
+			mode_lib->vba.SOCCLK,
+			v->DCFCLKDeepSleep,
+			mode_lib->vba.DETBufferSizeY,
+			mode_lib->vba.DETBufferSizeC,
+			mode_lib->vba.SwathHeightY,
+			mode_lib->vba.SwathHeightC,
+			mode_lib->vba.LBBitPerPixel,
+			v->SwathWidthY,
+			v->SwathWidthC,
+			mode_lib->vba.HRatio,
+			mode_lib->vba.HRatioChroma,
+			mode_lib->vba.vtaps,
+			mode_lib->vba.VTAPsChroma,
+			mode_lib->vba.VRatio,
+			mode_lib->vba.VRatioChroma,
+			mode_lib->vba.HTotal,
+			mode_lib->vba.VTotal,
+			mode_lib->vba.VActive,
+			mode_lib->vba.PixelClock,
+			mode_lib->vba.BlendingAndTiming,
+			mode_lib->vba.DPPPerPlane,
+			v->BytePerPixelDETY,
+			v->BytePerPixelDETC,
+			v->DSTXAfterScaler,
+			v->DSTYAfterScaler,
+			mode_lib->vba.WritebackEnable,
+			mode_lib->vba.WritebackPixelFormat,
+			mode_lib->vba.WritebackDestinationWidth,
+			mode_lib->vba.WritebackDestinationHeight,
+			mode_lib->vba.WritebackSourceHeight,
+			v->UnboundedRequestEnabled,
+			v->CompressedBufferSizeInkByte,
+
+			/* Output */
+			&v->Watermark,
+			&dummy_dramchange_support,
+			v->MaxActiveDRAMClockChangeLatencySupported,
+			v->SubViewportLinesNeededInMALL,
+			&dummy_fclkchange_support,
+			&v->MinActiveFCLKChangeLatencySupported,
+			&dummy_USRRetrainingSupport,
+			mode_lib->vba.ActiveDRAMClockChangeLatencyMargin);
+
+		/* DCN32 has a new struct Watermarks (typedef) which is used to store
+		 * calculated WM values. Copy over values from struct to vba varaibles
+		 * to ensure that the DCN32 getters return the correct value.
+		 */
+		v->UrgentWatermark = v->Watermark.UrgentWatermark;
+		v->WritebackUrgentWatermark = v->Watermark.WritebackUrgentWatermark;
+		v->DRAMClockChangeWatermark = v->Watermark.DRAMClockChangeWatermark;
+		v->WritebackDRAMClockChangeWatermark = v->Watermark.WritebackDRAMClockChangeWatermark;
+		v->StutterExitWatermark = v->Watermark.StutterExitWatermark;
+		v->StutterEnterPlusExitWatermark = v->Watermark.StutterEnterPlusExitWatermark;
+		v->Z8StutterExitWatermark = v->Watermark.Z8StutterExitWatermark;
+		v->Z8StutterEnterPlusExitWatermark = v->Watermark.Z8StutterEnterPlusExitWatermark;
+
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			if (mode_lib->vba.WritebackEnable[k] == true) {
+				v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(0,
+						v->VStartup[k] * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]
+								- v->Watermark.WritebackDRAMClockChangeWatermark);
+				v->WritebackAllowFCLKChangeEndPosition[k] = dml_max(0,
+						v->VStartup[k] * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]
+								- v->Watermark.WritebackFCLKChangeWatermark);
+			} else {
+				v->WritebackAllowDRAMClockChangeEndPosition[k] = 0;
+				v->WritebackAllowFCLKChangeEndPosition[k] = 0;
+			}
+		}
+	}
+
+	//Display Pipeline Delivery Time in Prefetch, Groups
+	dml32_CalculatePixelDeliveryTimes(
+			mode_lib->vba.NumberOfActiveSurfaces,
+			mode_lib->vba.VRatio,
+			mode_lib->vba.VRatioChroma,
+			v->VRatioPrefetchY,
+			v->VRatioPrefetchC,
+			v->swath_width_luma_ub,
+			v->swath_width_chroma_ub,
+			mode_lib->vba.DPPPerPlane,
+			mode_lib->vba.HRatio,
+			mode_lib->vba.HRatioChroma,
+			mode_lib->vba.PixelClock,
+			v->PSCL_THROUGHPUT_LUMA,
+			v->PSCL_THROUGHPUT_CHROMA,
+			mode_lib->vba.DPPCLK,
+			v->BytePerPixelC,
+			mode_lib->vba.SourceRotation,
+			mode_lib->vba.NumberOfCursors,
+			mode_lib->vba.CursorWidth,
+			mode_lib->vba.CursorBPP,
+			v->BlockWidth256BytesY,
+			v->BlockHeight256BytesY,
+			v->BlockWidth256BytesC,
+			v->BlockHeight256BytesC,
+
+			/* Output */
+			v->DisplayPipeLineDeliveryTimeLuma,
+			v->DisplayPipeLineDeliveryTimeChroma,
+			v->DisplayPipeLineDeliveryTimeLumaPrefetch,
+			v->DisplayPipeLineDeliveryTimeChromaPrefetch,
+			v->DisplayPipeRequestDeliveryTimeLuma,
+			v->DisplayPipeRequestDeliveryTimeChroma,
+			v->DisplayPipeRequestDeliveryTimeLumaPrefetch,
+			v->DisplayPipeRequestDeliveryTimeChromaPrefetch,
+			v->CursorRequestDeliveryTime,
+			v->CursorRequestDeliveryTimePrefetch);
+
+	dml32_CalculateMetaAndPTETimes(v->Use_One_Row_For_Frame,
+			mode_lib->vba.NumberOfActiveSurfaces,
+			mode_lib->vba.GPUVMEnable,
+			mode_lib->vba.MetaChunkSize,
+			mode_lib->vba.MinMetaChunkSizeBytes,
+			mode_lib->vba.HTotal,
+			mode_lib->vba.VRatio,
+			mode_lib->vba.VRatioChroma,
+			v->DestinationLinesToRequestRowInVBlank,
+			v->DestinationLinesToRequestRowInImmediateFlip,
+			mode_lib->vba.DCCEnable,
+			mode_lib->vba.PixelClock,
+			v->BytePerPixelY,
+			v->BytePerPixelC,
+			mode_lib->vba.SourceRotation,
+			v->dpte_row_height,
+			v->dpte_row_height_chroma,
+			v->meta_row_width,
+			v->meta_row_width_chroma,
+			v->meta_row_height,
+			v->meta_row_height_chroma,
+			v->meta_req_width,
+			v->meta_req_width_chroma,
+			v->meta_req_height,
+			v->meta_req_height_chroma,
+			v->dpte_group_bytes,
+			v->PTERequestSizeY,
+			v->PTERequestSizeC,
+			v->PixelPTEReqWidthY,
+			v->PixelPTEReqHeightY,
+			v->PixelPTEReqWidthC,
+			v->PixelPTEReqHeightC,
+			v->dpte_row_width_luma_ub,
+			v->dpte_row_width_chroma_ub,
+
+			/* Output */
+			v->DST_Y_PER_PTE_ROW_NOM_L,
+			v->DST_Y_PER_PTE_ROW_NOM_C,
+			v->DST_Y_PER_META_ROW_NOM_L,
+			v->DST_Y_PER_META_ROW_NOM_C,
+			v->TimePerMetaChunkNominal,
+			v->TimePerChromaMetaChunkNominal,
+			v->TimePerMetaChunkVBlank,
+			v->TimePerChromaMetaChunkVBlank,
+			v->TimePerMetaChunkFlip,
+			v->TimePerChromaMetaChunkFlip,
+			v->time_per_pte_group_nom_luma,
+			v->time_per_pte_group_vblank_luma,
+			v->time_per_pte_group_flip_luma,
+			v->time_per_pte_group_nom_chroma,
+			v->time_per_pte_group_vblank_chroma,
+			v->time_per_pte_group_flip_chroma);
+
+	dml32_CalculateVMGroupAndRequestTimes(
+			mode_lib->vba.NumberOfActiveSurfaces,
+			mode_lib->vba.GPUVMEnable,
+			mode_lib->vba.GPUVMMaxPageTableLevels,
+			mode_lib->vba.HTotal,
+			v->BytePerPixelC,
+			v->DestinationLinesToRequestVMInVBlank,
+			v->DestinationLinesToRequestVMInImmediateFlip,
+			mode_lib->vba.DCCEnable,
+			mode_lib->vba.PixelClock,
+			v->dpte_row_width_luma_ub,
+			v->dpte_row_width_chroma_ub,
+			v->vm_group_bytes,
+			v->dpde0_bytes_per_frame_ub_l,
+			v->dpde0_bytes_per_frame_ub_c,
+			v->meta_pte_bytes_per_frame_ub_l,
+			v->meta_pte_bytes_per_frame_ub_c,
+
+			/* Output */
+			v->TimePerVMGroupVBlank,
+			v->TimePerVMGroupFlip,
+			v->TimePerVMRequestVBlank,
+			v->TimePerVMRequestFlip);
+
+	// Min TTUVBlank
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		if (mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) {
+			v->MinTTUVBlank[k] = dml_max4(v->Watermark.DRAMClockChangeWatermark,
+					v->Watermark.FCLKChangeWatermark, v->Watermark.StutterEnterPlusExitWatermark,
+					v->Watermark.UrgentWatermark);
+		} else if (mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb]
+				== 1) {
+			v->MinTTUVBlank[k] = dml_max3(v->Watermark.FCLKChangeWatermark,
+					v->Watermark.StutterEnterPlusExitWatermark, v->Watermark.UrgentWatermark);
+		} else if (mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb]
+				== 2) {
+			v->MinTTUVBlank[k] = dml_max(v->Watermark.StutterEnterPlusExitWatermark,
+					v->Watermark.UrgentWatermark);
+		} else {
+			v->MinTTUVBlank[k] = v->Watermark.UrgentWatermark;
+		}
+		if (!mode_lib->vba.DynamicMetadataEnable[k])
+			v->MinTTUVBlank[k] = mode_lib->vba.TCalc + v->MinTTUVBlank[k];
+	}
+
+	// DCC Configuration
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: Calculate DCC configuration for surface k=%d\n", __func__, k);
+#endif
+		dml32_CalculateDCCConfiguration(
+				mode_lib->vba.DCCEnable[k],
+				mode_lib->vba.DCCProgrammingAssumesScanDirectionUnknownFinal,
+				mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceWidthY[k],
+				mode_lib->vba.SurfaceWidthC[k],
+				mode_lib->vba.SurfaceHeightY[k],
+				mode_lib->vba.SurfaceHeightC[k],
+				mode_lib->vba.nomDETInKByte,
+				v->BlockHeight256BytesY[k],
+				v->BlockHeight256BytesC[k],
+				mode_lib->vba.SurfaceTiling[k],
+				v->BytePerPixelY[k],
+				v->BytePerPixelC[k],
+				v->BytePerPixelDETY[k],
+				v->BytePerPixelDETC[k],
+				mode_lib->vba.SourceScan[k],
+				/* Output */
+				&v->DCCYMaxUncompressedBlock[k],
+				&v->DCCCMaxUncompressedBlock[k],
+				&v->DCCYMaxCompressedBlock[k],
+				&v->DCCCMaxCompressedBlock[k],
+				&v->DCCYIndependentBlock[k],
+				&v->DCCCIndependentBlock[k]);
+	}
+
+	// VStartup Adjustment
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		bool isInterlaceTiming;
+		double Tvstartup_margin = (v->MaxVStartupLines[k] - v->VStartup[k]) * mode_lib->vba.HTotal[k]
+				/ mode_lib->vba.PixelClock[k];
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, MinTTUVBlank = %f (before vstartup margin)\n", __func__, k,
+				v->MinTTUVBlank[k]);
+#endif
+
+		v->MinTTUVBlank[k] = v->MinTTUVBlank[k] + Tvstartup_margin;
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, Tvstartup_margin = %f\n", __func__, k, Tvstartup_margin);
+		dml_print("DML::%s: k=%d, MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
+		dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
+		dml_print("DML::%s: k=%d, MinTTUVBlank = %f\n", __func__, k, v->MinTTUVBlank[k]);
+#endif
+
+		v->Tdmdl[k] = v->Tdmdl[k] + Tvstartup_margin;
+		if (mode_lib->vba.DynamicMetadataEnable[k] && mode_lib->vba.DynamicMetadataVMEnabled)
+			v->Tdmdl_vm[k] = v->Tdmdl_vm[k] + Tvstartup_margin;
+
+		isInterlaceTiming = (mode_lib->vba.Interlace[k] &&
+				!mode_lib->vba.ProgressiveToInterlaceUnitInOPP);
+
+		v->MIN_DST_Y_NEXT_START[k] = ((isInterlaceTiming ? dml_floor((mode_lib->vba.VTotal[k] -
+						mode_lib->vba.VFrontPorch[k]) / 2.0, 1.0) :
+						mode_lib->vba.VTotal[k]) - mode_lib->vba.VFrontPorch[k])
+						+ dml_max(1.0,
+						dml_ceil(v->WritebackDelay[mode_lib->vba.VoltageLevel][k]
+						/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0))
+						+ dml_floor(4.0 * v->TSetup[k] / (mode_lib->vba.HTotal[k]
+						/ mode_lib->vba.PixelClock[k]), 1.0) / 4.0;
+
+		v->VStartup[k] = (isInterlaceTiming ? (2 * v->MaxVStartupLines[k]) : v->MaxVStartupLines[k]);
+
+		if (((v->VUpdateOffsetPix[k] + v->VUpdateWidthPix[k] + v->VReadyOffsetPix[k])
+			/ mode_lib->vba.HTotal[k]) <= (isInterlaceTiming ? dml_floor((mode_lib->vba.VTotal[k]
+			- mode_lib->vba.VActive[k] - mode_lib->vba.VFrontPorch[k] - v->VStartup[k]) / 2.0, 1.0) :
+			(int) (mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
+		       - mode_lib->vba.VFrontPorch[k] - v->VStartup[k]))) {
+			v->VREADY_AT_OR_AFTER_VSYNC[k] = true;
+		} else {
+			v->VREADY_AT_OR_AFTER_VSYNC[k] = false;
+		}
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, VStartup = %d (max)\n", __func__, k, v->VStartup[k]);
+		dml_print("DML::%s: k=%d, VUpdateOffsetPix = %d\n", __func__, k, v->VUpdateOffsetPix[k]);
+		dml_print("DML::%s: k=%d, VUpdateWidthPix = %d\n", __func__, k, v->VUpdateWidthPix[k]);
+		dml_print("DML::%s: k=%d, VReadyOffsetPix = %d\n", __func__, k, v->VReadyOffsetPix[k]);
+		dml_print("DML::%s: k=%d, HTotal = %d\n", __func__, k, mode_lib->vba.HTotal[k]);
+		dml_print("DML::%s: k=%d, VTotal = %d\n", __func__, k, mode_lib->vba.VTotal[k]);
+		dml_print("DML::%s: k=%d, VActive = %d\n", __func__, k, mode_lib->vba.VActive[k]);
+		dml_print("DML::%s: k=%d, VFrontPorch = %d\n", __func__, k, mode_lib->vba.VFrontPorch[k]);
+		dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
+		dml_print("DML::%s: k=%d, TSetup = %f\n", __func__, k, v->TSetup[k]);
+		dml_print("DML::%s: k=%d, MIN_DST_Y_NEXT_START = %f\n", __func__, k, v->MIN_DST_Y_NEXT_START[k]);
+		dml_print("DML::%s: k=%d, VREADY_AT_OR_AFTER_VSYNC = %d\n", __func__, k,
+				v->VREADY_AT_OR_AFTER_VSYNC[k]);
+#endif
+	}
+
+	{
+		//Maximum Bandwidth Used
+		double TotalWRBandwidth = 0;
+		double WRBandwidth = 0;
+
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			if (mode_lib->vba.WritebackEnable[k] == true
+					&& mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
+				WRBandwidth = mode_lib->vba.WritebackDestinationWidth[k]
+						* mode_lib->vba.WritebackDestinationHeight[k]
+						/ (mode_lib->vba.HTotal[k] * mode_lib->vba.WritebackSourceHeight[k]
+								/ mode_lib->vba.PixelClock[k]) * 4;
+			} else if (mode_lib->vba.WritebackEnable[k] == true) {
+				WRBandwidth = mode_lib->vba.WritebackDestinationWidth[k]
+						* mode_lib->vba.WritebackDestinationHeight[k]
+						/ (mode_lib->vba.HTotal[k] * mode_lib->vba.WritebackSourceHeight[k]
+								/ mode_lib->vba.PixelClock[k]) * 8;
+			}
+			TotalWRBandwidth = TotalWRBandwidth + WRBandwidth;
+		}
+
+		v->TotalDataReadBandwidth = 0;
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			v->TotalDataReadBandwidth = v->TotalDataReadBandwidth + v->ReadBandwidthSurfaceLuma[k]
+					+ v->ReadBandwidthSurfaceChroma[k];
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%d, TotalDataReadBandwidth = %f\n",
+					__func__, k, v->TotalDataReadBandwidth);
+			dml_print("DML::%s: k=%d, ReadBandwidthSurfaceLuma = %f\n",
+					__func__, k, v->ReadBandwidthSurfaceLuma[k]);
+			dml_print("DML::%s: k=%d, ReadBandwidthSurfaceChroma = %f\n",
+					__func__, k, v->ReadBandwidthSurfaceChroma[k]);
+#endif
+		}
+	}
+
+	// Stutter Efficiency
+	dml32_CalculateStutterEfficiency(v->CompressedBufferSizeInkByte,
+			mode_lib->vba.UsesMALLForPStateChange,
+			v->UnboundedRequestEnabled,
+			mode_lib->vba.MetaFIFOSizeInKEntries,
+			mode_lib->vba.ZeroSizeBufferEntries,
+			mode_lib->vba.PixelChunkSizeInKByte,
+			mode_lib->vba.NumberOfActiveSurfaces,
+			mode_lib->vba.ROBBufferSizeInKByte,
+			v->TotalDataReadBandwidth,
+			mode_lib->vba.DCFCLK,
+			mode_lib->vba.ReturnBW,
+			mode_lib->vba.CompbufReservedSpace64B,
+			mode_lib->vba.CompbufReservedSpaceZs,
+			mode_lib->vba.SRExitTime,
+			mode_lib->vba.SRExitZ8Time,
+			mode_lib->vba.SynchronizeTimingsFinal,
+			mode_lib->vba.BlendingAndTiming,
+			v->Watermark.StutterEnterPlusExitWatermark,
+			v->Watermark.Z8StutterEnterPlusExitWatermark,
+			mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
+			mode_lib->vba.Interlace,
+			v->MinTTUVBlank, mode_lib->vba.DPPPerPlane,
+			mode_lib->vba.DETBufferSizeY,
+			v->BytePerPixelY,
+			v->BytePerPixelDETY,
+			v->SwathWidthY,
+			mode_lib->vba.SwathHeightY,
+			mode_lib->vba.SwathHeightC,
+			mode_lib->vba.DCCRateLuma,
+			mode_lib->vba.DCCRateChroma,
+			mode_lib->vba.DCCFractionOfZeroSizeRequestsLuma,
+			mode_lib->vba.DCCFractionOfZeroSizeRequestsChroma,
+			mode_lib->vba.HTotal, mode_lib->vba.VTotal,
+			mode_lib->vba.PixelClock,
+			mode_lib->vba.VRatio,
+			mode_lib->vba.SourceRotation,
+			v->BlockHeight256BytesY,
+			v->BlockWidth256BytesY,
+			v->BlockHeight256BytesC,
+			v->BlockWidth256BytesC,
+			v->DCCYMaxUncompressedBlock,
+			v->DCCCMaxUncompressedBlock,
+			mode_lib->vba.VActive,
+			mode_lib->vba.DCCEnable,
+			mode_lib->vba.WritebackEnable,
+			v->ReadBandwidthSurfaceLuma,
+			v->ReadBandwidthSurfaceChroma,
+			v->meta_row_bw,
+			v->dpte_row_bw,
+			/* Output */
+			&v->StutterEfficiencyNotIncludingVBlank,
+			&v->StutterEfficiency,
+			&v->NumberOfStutterBurstsPerFrame,
+			&v->Z8StutterEfficiencyNotIncludingVBlank,
+			&v->Z8StutterEfficiency,
+			&v->Z8NumberOfStutterBurstsPerFrame,
+			&v->StutterPeriod,
+			&v->DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE);
+
+#ifdef __DML_VBA_ALLOW_DELTA__
+	{
+		double dummy_single[2];
+		unsigned int dummy_integer[1];
+		bool dummy_boolean[1];
+
+		// Calculate z8 stutter eff assuming 0 reserved space
+		dml32_CalculateStutterEfficiency(v->CompressedBufferSizeInkByte,
+				mode_lib->vba.UsesMALLForPStateChange,
+				v->UnboundedRequestEnabled,
+				mode_lib->vba.MetaFIFOSizeInKEntries,
+				mode_lib->vba.ZeroSizeBufferEntries,
+				mode_lib->vba.PixelChunkSizeInKByte,
+				mode_lib->vba.NumberOfActiveSurfaces,
+				mode_lib->vba.ROBBufferSizeInKByte,
+				v->TotalDataReadBandwidth,
+				mode_lib->vba.DCFCLK,
+				mode_lib->vba.ReturnBW,
+				0, //mode_lib->vba.CompbufReservedSpace64B,
+				0, //mode_lib->vba.CompbufReservedSpaceZs,
+				mode_lib->vba.SRExitTime,
+				mode_lib->vba.SRExitZ8Time,
+				mode_lib->vba.SynchronizeTimingsFinal,
+				mode_lib->vba.BlendingAndTiming,
+				v->Watermark.StutterEnterPlusExitWatermark,
+				v->Watermark.Z8StutterEnterPlusExitWatermark,
+				mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
+				mode_lib->vba.Interlace,
+				v->MinTTUVBlank,
+				mode_lib->vba.DPPPerPlane,
+				mode_lib->vba.DETBufferSizeY,
+				v->BytePerPixelY, v->BytePerPixelDETY,
+				v->SwathWidthY, mode_lib->vba.SwathHeightY,
+				mode_lib->vba.SwathHeightC,
+				mode_lib->vba.DCCRateLuma,
+				mode_lib->vba.DCCRateChroma,
+				mode_lib->vba.DCCFractionOfZeroSizeRequestsLuma,
+				mode_lib->vba.DCCFractionOfZeroSizeRequestsChroma,
+				mode_lib->vba.HTotal,
+				mode_lib->vba.VTotal,
+				mode_lib->vba.PixelClock,
+				mode_lib->vba.VRatio,
+				mode_lib->vba.SourceRotation,
+				v->BlockHeight256BytesY,
+				v->BlockWidth256BytesY,
+				v->BlockHeight256BytesC,
+				v->BlockWidth256BytesC,
+				v->DCCYMaxUncompressedBlock,
+				v->DCCCMaxUncompressedBlock,
+				mode_lib->vba.VActive,
+				mode_lib->vba.DCCEnable,
+				mode_lib->vba.WritebackEnable,
+				v->ReadBandwidthSurfaceLuma,
+				v->ReadBandwidthSurfaceChroma,
+				v->meta_row_bw, v->dpte_row_bw,
+
+				/* Output */
+				&dummy_single[0],
+				&dummy_single[1],
+				&dummy_integer[0],
+				&v->Z8StutterEfficiencyNotIncludingVBlankBestCase,
+				&v->Z8StutterEfficiencyBestCase,
+				&v->Z8NumberOfStutterBurstsPerFrameBestCase,
+				&v->StutterPeriodBestCase,
+				&dummy_boolean[0]);
+	}
+#else
+	v->Z8StutterEfficiencyNotIncludingVBlankBestCase = v->Z8StutterEfficiencyNotIncludingVBlank;
+	v->Z8StutterEfficiencyBestCase = v->Z8StutterEfficiency;
+	v->Z8NumberOfStutterBurstsPerFrameBestCase = v->Z8NumberOfStutterBurstsPerFrame;
+	v->StutterPeriodBestCase = v->StutterPeriod;
+#endif
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: --- END ---\n", __func__);
+#endif
+}
+
+void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
+{
+	bool dummy_boolean[2];
+	unsigned int dummy_integer[1];
+	bool MPCCombineMethodAsNeededForPStateChangeAndVoltage;
+	bool MPCCombineMethodAsPossible;
+	enum odm_combine_mode dummy_odm_mode[DC__NUM_DPP__MAX];
+	unsigned int TotalNumberOfActiveOTG;
+	unsigned int TotalNumberOfActiveHDMIFRL;
+	unsigned int TotalNumberOfActiveDP2p0;
+	unsigned int TotalNumberOfActiveDP2p0Outputs;
+	unsigned int TotalDSCUnitsRequired;
+	unsigned int m;
+	unsigned int ReorderingBytes;
+	bool FullFrameMALLPStateMethod;
+	bool SubViewportMALLPStateMethod;
+	bool PhantomPipeMALLPStateMethod;
+	double MaxTotalVActiveRDBandwidth;
+	double DSTYAfterScaler[DC__NUM_DPP__MAX];
+	double DSTXAfterScaler[DC__NUM_DPP__MAX];
+	unsigned int MaximumMPCCombine;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: called\n", __func__);
+#endif
+	struct vba_vars_st *v = &mode_lib->vba;
+
+	int i, j;
+	unsigned int k;
+
+	/*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/
+
+	/*Scale Ratio, taps Support Check*/
+
+	mode_lib->vba.ScaleRatioAndTapsSupport = true;
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (mode_lib->vba.ScalerEnabled[k] == false
+				&& ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe_alpha)
+						|| mode_lib->vba.HRatio[k] != 1.0 || mode_lib->vba.htaps[k] != 1.0
+						|| mode_lib->vba.VRatio[k] != 1.0 || mode_lib->vba.vtaps[k] != 1.0)) {
+			mode_lib->vba.ScaleRatioAndTapsSupport = false;
+		} else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0 || mode_lib->vba.htaps[k] < 1.0
+				|| mode_lib->vba.htaps[k] > 8.0
+				|| (mode_lib->vba.htaps[k] > 1.0 && (mode_lib->vba.htaps[k] % 2) == 1)
+				|| mode_lib->vba.HRatio[k] > mode_lib->vba.MaxHSCLRatio
+				|| mode_lib->vba.VRatio[k] > mode_lib->vba.MaxVSCLRatio
+				|| mode_lib->vba.HRatio[k] > mode_lib->vba.htaps[k]
+				|| mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k]
+				|| (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe
+						&& (mode_lib->vba.VTAPsChroma[k] < 1
+								|| mode_lib->vba.VTAPsChroma[k] > 8
+								|| mode_lib->vba.HTAPsChroma[k] < 1
+								|| mode_lib->vba.HTAPsChroma[k] > 8
+								|| (mode_lib->vba.HTAPsChroma[k] > 1
+										&& mode_lib->vba.HTAPsChroma[k] % 2
+												== 1)
+								|| mode_lib->vba.HRatioChroma[k]
+										> mode_lib->vba.MaxHSCLRatio
+								|| mode_lib->vba.VRatioChroma[k]
+										> mode_lib->vba.MaxVSCLRatio
+								|| mode_lib->vba.HRatioChroma[k]
+										> mode_lib->vba.HTAPsChroma[k]
+								|| mode_lib->vba.VRatioChroma[k]
+										> mode_lib->vba.VTAPsChroma[k]))) {
+			mode_lib->vba.ScaleRatioAndTapsSupport = false;
+		}
+	}
+
+	/*Source Format, Pixel Format and Scan Support Check*/
+	mode_lib->vba.SourceFormatPixelAndScanSupport = true;
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
+			&& (!(!IsVertical(mode_lib->vba.SourceScan[k])) || mode_lib->vba.DCCEnable[k] == true)) {
+			mode_lib->vba.SourceFormatPixelAndScanSupport = false;
+		}
+	}
+
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		dml32_CalculateBytePerPixelAndBlockSizes(
+				mode_lib->vba.SourcePixelFormat[k],
+				mode_lib->vba.SurfaceTiling[k],
+
+				/* Output */
+				&mode_lib->vba.BytePerPixelY[k],
+				&mode_lib->vba.BytePerPixelC[k],
+				&mode_lib->vba.BytePerPixelInDETY[k],
+				&mode_lib->vba.BytePerPixelInDETC[k],
+				&mode_lib->vba.Read256BlockHeightY[k],
+				&mode_lib->vba.Read256BlockHeightC[k],
+				&mode_lib->vba.Read256BlockWidthY[k],
+				&mode_lib->vba.Read256BlockWidthC[k],
+				&mode_lib->vba.MicroTileHeightY[k],
+				&mode_lib->vba.MicroTileHeightC[k],
+				&mode_lib->vba.MicroTileWidthY[k],
+				&mode_lib->vba.MicroTileWidthC[k]);
+	}
+
+	/*Bandwidth Support Check*/
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (!IsVertical(mode_lib->vba.SourceRotation[k])) {
+			v->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k];
+			v->SwathWidthCSingleDPP[k] = mode_lib->vba.ViewportWidthChroma[k];
+		} else {
+			v->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k];
+			v->SwathWidthCSingleDPP[k] = mode_lib->vba.ViewportHeightChroma[k];
+		}
+	}
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		v->ReadBandwidthLuma[k] = v->SwathWidthYSingleDPP[k] * dml_ceil(v->BytePerPixelInDETY[k], 1.0)
+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
+		v->ReadBandwidthChroma[k] = v->SwathWidthYSingleDPP[k] / 2 * dml_ceil(v->BytePerPixelInDETC[k], 2.0)
+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]
+				/ 2.0;
+	}
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (mode_lib->vba.WritebackEnable[k] == true && mode_lib->vba.WritebackPixelFormat[k] == dm_444_64) {
+			v->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
+					* mode_lib->vba.WritebackDestinationHeight[k]
+					/ (mode_lib->vba.WritebackSourceHeight[k] * mode_lib->vba.HTotal[k]
+							/ mode_lib->vba.PixelClock[k]) * 8.0;
+		} else if (mode_lib->vba.WritebackEnable[k] == true) {
+			v->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
+					* mode_lib->vba.WritebackDestinationHeight[k]
+					/ (mode_lib->vba.WritebackSourceHeight[k] * mode_lib->vba.HTotal[k]
+							/ mode_lib->vba.PixelClock[k]) * 4.0;
+		} else {
+			v->WriteBandwidth[k] = 0.0;
+		}
+	}
+
+	/*Writeback Latency support check*/
+
+	mode_lib->vba.WritebackLatencySupport = true;
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (mode_lib->vba.WritebackEnable[k] == true
+				&& (v->WriteBandwidth[k]
+						> mode_lib->vba.WritebackInterfaceBufferSize * 1024
+								/ mode_lib->vba.WritebackLatency)) {
+			mode_lib->vba.WritebackLatencySupport = false;
+		}
+	}
+
+	/*Writeback Mode Support Check*/
+	mode_lib->vba.EnoughWritebackUnits = true;
+	mode_lib->vba.TotalNumberOfActiveWriteback = 0;
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (mode_lib->vba.WritebackEnable[k] == true)
+			mode_lib->vba.TotalNumberOfActiveWriteback = mode_lib->vba.TotalNumberOfActiveWriteback + 1;
+	}
+
+	if (mode_lib->vba.TotalNumberOfActiveWriteback > mode_lib->vba.MaxNumWriteback)
+		mode_lib->vba.EnoughWritebackUnits = false;
+
+	/*Writeback Scale Ratio and Taps Support Check*/
+	mode_lib->vba.WritebackScaleRatioAndTapsSupport = true;
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (mode_lib->vba.WritebackEnable[k] == true) {
+			if (mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackMaxHSCLRatio
+					|| mode_lib->vba.WritebackVRatio[k] > mode_lib->vba.WritebackMaxVSCLRatio
+					|| mode_lib->vba.WritebackHRatio[k] < mode_lib->vba.WritebackMinHSCLRatio
+					|| mode_lib->vba.WritebackVRatio[k] < mode_lib->vba.WritebackMinVSCLRatio
+					|| mode_lib->vba.WritebackHTaps[k] > mode_lib->vba.WritebackMaxHSCLTaps
+					|| mode_lib->vba.WritebackVTaps[k] > mode_lib->vba.WritebackMaxVSCLTaps
+					|| mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackHTaps[k]
+					|| mode_lib->vba.WritebackVRatio[k] > mode_lib->vba.WritebackVTaps[k]
+					|| (mode_lib->vba.WritebackHTaps[k] > 2.0
+							&& ((mode_lib->vba.WritebackHTaps[k] % 2) == 1))) {
+				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
+			}
+			if (2.0 * mode_lib->vba.WritebackDestinationWidth[k] * (mode_lib->vba.WritebackVTaps[k] - 1)
+					* 57 > mode_lib->vba.WritebackLineBufferSize) {
+				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
+			}
+		}
+	}
+
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(mode_lib->vba.HRatio[k], mode_lib->vba.HRatioChroma[k],
+				mode_lib->vba.VRatio[k], mode_lib->vba.VRatioChroma[k],
+				mode_lib->vba.MaxDCHUBToPSCLThroughput, mode_lib->vba.MaxPSCLToLBThroughput,
+				mode_lib->vba.PixelClock[k], mode_lib->vba.SourcePixelFormat[k],
+				mode_lib->vba.htaps[k], mode_lib->vba.HTAPsChroma[k], mode_lib->vba.vtaps[k],
+				mode_lib->vba.VTAPsChroma[k],
+				/* Output */
+				&mode_lib->vba.PSCL_FACTOR[k], &mode_lib->vba.PSCL_FACTOR_CHROMA[k],
+				&mode_lib->vba.MinDPPCLKUsingSingleDPP[k]);
+	}
+
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+
+		if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 8192;
+		} else if (!IsVertical(mode_lib->vba.SourceRotation[k]) && v->BytePerPixelC[k] > 0
+				&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe_alpha) {
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 7680;
+		} else if (IsVertical(mode_lib->vba.SourceRotation[k]) && v->BytePerPixelC[k] > 0
+				&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe_alpha) {
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 4320;
+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_rgbe_alpha) {
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 3840;
+		} else if (IsVertical(mode_lib->vba.SourceRotation[k]) && v->BytePerPixelY[k] == 8 &&
+				mode_lib->vba.DCCEnable[k] == true) {
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 3072;
+		} else {
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 6144;
+		}
+
+		if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8 || mode_lib->vba.SourcePixelFormat[k] == dm_420_10
+				|| mode_lib->vba.SourcePixelFormat[k] == dm_420_12) {
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportChroma = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma / 2.0;
+		} else {
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportChroma = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma;
+		}
+		v->MaximumSwathWidthInLineBufferLuma = mode_lib->vba.LineBufferSizeFinal
+				* dml_max(mode_lib->vba.HRatio[k], 1.0) / mode_lib->vba.LBBitPerPixel[k]
+				/ (mode_lib->vba.vtaps[k] + dml_max(dml_ceil(mode_lib->vba.VRatio[k], 1.0) - 2, 0.0));
+		if (v->BytePerPixelC[k] == 0.0) {
+			v->MaximumSwathWidthInLineBufferChroma = 0;
+		} else {
+			v->MaximumSwathWidthInLineBufferChroma = mode_lib->vba.LineBufferSizeFinal
+					* dml_max(mode_lib->vba.HRatioChroma[k], 1.0) / mode_lib->vba.LBBitPerPixel[k]
+					/ (mode_lib->vba.VTAPsChroma[k]
+							+ dml_max(dml_ceil(mode_lib->vba.VRatioChroma[k], 1.0) - 2,
+									0.0));
+		}
+		v->MaximumSwathWidthLuma[k] = dml_min(v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma,
+				v->MaximumSwathWidthInLineBufferLuma);
+		v->MaximumSwathWidthChroma[k] = dml_min(v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportChroma,
+				v->MaximumSwathWidthInLineBufferChroma);
+	}
+
+	/*Number Of DSC Slices*/
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		if (mode_lib->vba.BlendingAndTiming[k] == k) {
+			if (mode_lib->vba.PixelClockBackEnd[k] > 4800) {
+				mode_lib->vba.NumberOfDSCSlices[k] = dml_ceil(mode_lib->vba.PixelClockBackEnd[k] / 600,
+						4);
+			} else if (mode_lib->vba.PixelClockBackEnd[k] > 2400) {
+				mode_lib->vba.NumberOfDSCSlices[k] = 8;
+			} else if (mode_lib->vba.PixelClockBackEnd[k] > 1200) {
+				mode_lib->vba.NumberOfDSCSlices[k] = 4;
+			} else if (mode_lib->vba.PixelClockBackEnd[k] > 340) {
+				mode_lib->vba.NumberOfDSCSlices[k] = 2;
+			} else {
+				mode_lib->vba.NumberOfDSCSlices[k] = 1;
+			}
+		} else {
+			mode_lib->vba.NumberOfDSCSlices[k] = 0;
+		}
+	}
+
+	dml32_CalculateSwathAndDETConfiguration(
+			mode_lib->vba.DETSizeOverride,
+			mode_lib->vba.UsesMALLForPStateChange,
+			mode_lib->vba.ConfigReturnBufferSizeInKByte,
+			mode_lib->vba.MaxTotalDETInKByte,
+			mode_lib->vba.MinCompressedBufferSizeInKByte,
+			1, /* ForceSingleDPP */
+			mode_lib->vba.NumberOfActiveSurfaces,
+			mode_lib->vba.nomDETInKByte,
+			mode_lib->vba.UseUnboundedRequesting,
+			mode_lib->vba.CompressedBufferSegmentSizeInkByteFinal,
+			mode_lib->vba.Output,
+			mode_lib->vba.ReadBandwidthLuma,
+			mode_lib->vba.ReadBandwidthChroma,
+			mode_lib->vba.MaximumSwathWidthLuma,
+			mode_lib->vba.MaximumSwathWidthChroma,
+			mode_lib->vba.SourceRotation,
+			mode_lib->vba.ViewportStationary,
+			mode_lib->vba.SourcePixelFormat,
+			mode_lib->vba.SurfaceTiling,
+			mode_lib->vba.ViewportWidth,
+			mode_lib->vba.ViewportHeight,
+			mode_lib->vba.ViewportXStartY,
+			mode_lib->vba.ViewportYStartY,
+			mode_lib->vba.ViewportXStartC,
+			mode_lib->vba.ViewportYStartC,
+			mode_lib->vba.SurfaceWidthY,
+			mode_lib->vba.SurfaceWidthC,
+			mode_lib->vba.SurfaceHeightY,
+			mode_lib->vba.SurfaceHeightC,
+			mode_lib->vba.Read256BlockHeightY,
+			mode_lib->vba.Read256BlockHeightC,
+			mode_lib->vba.Read256BlockWidthY,
+			mode_lib->vba.Read256BlockWidthC,
+			dummy_odm_mode,
+			mode_lib->vba.BlendingAndTiming,
+			mode_lib->vba.BytePerPixelY,
+			mode_lib->vba.BytePerPixelC,
+			mode_lib->vba.BytePerPixelInDETY,
+			mode_lib->vba.BytePerPixelInDETC,
+			mode_lib->vba.HActive,
+			mode_lib->vba.HRatio,
+			mode_lib->vba.HRatioChroma,
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[0], /*  Integer DPPPerSurface[] */
+
+			/* Output */
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[1], /* Long            swath_width_luma_ub[] */
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[2], /* Long            swath_width_chroma_ub[]  */
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_double_array[0], /* Long            SwathWidth[]  */
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_double_array[1], /* Long            SwathWidthChroma[]  */
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[3], /* Integer         SwathHeightY[]  */
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[4], /* Integer         SwathHeightC[]  */
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[5], /* Long            DETBufferSizeInKByte[]  */
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[6], /* Long            DETBufferSizeY[]  */
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[7], /* Long            DETBufferSizeC[]  */
+			&dummy_boolean[0], /* bool           *UnboundedRequestEnabled  */
+			&dummy_integer[0], /* Long           *CompressedBufferSizeInkByte  */
+			mode_lib->vba.SingleDPPViewportSizeSupportPerSurface,/* bool ViewportSizeSupportPerSurface[] */
+			&dummy_boolean[1]); /* bool           *ViewportSizeSupport */
+
+	MPCCombineMethodAsNeededForPStateChangeAndVoltage = false;
+	MPCCombineMethodAsPossible = false;
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		if (mode_lib->vba.MPCCombineUse[k] == dm_mpc_reduce_voltage_and_clocks)
+			MPCCombineMethodAsNeededForPStateChangeAndVoltage = true;
+		if (mode_lib->vba.MPCCombineUse[k] == dm_mpc_always_when_possible)
+			MPCCombineMethodAsPossible = true;
+	}
+	mode_lib->vba.MPCCombineMethodIncompatible = MPCCombineMethodAsNeededForPStateChangeAndVoltage
+			&& MPCCombineMethodAsPossible;
+
+	for (i = 0; i < v->soc.num_states; i++) {
+		for (j = 0; j < 2; j++) {
+			bool NoChroma;
+			mode_lib->vba.TotalNumberOfActiveDPP[i][j] = 0;
+			mode_lib->vba.TotalAvailablePipesSupport[i][j] = true;
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+
+				bool TotalAvailablePipesSupportNoDSC;
+				unsigned int NumberOfDPPNoDSC;
+				enum odm_combine_mode ODMModeNoDSC = dm_odm_combine_mode_disabled;
+				double RequiredDISPCLKPerSurfaceNoDSC;
+				bool TotalAvailablePipesSupportDSC;
+				unsigned int NumberOfDPPDSC;
+				enum odm_combine_mode ODMModeDSC = dm_odm_combine_mode_disabled;
+				double RequiredDISPCLKPerSurfaceDSC;
+
+				dml32_CalculateODMMode(
+						mode_lib->vba.MaximumPixelsPerLinePerDSCUnit,
+						mode_lib->vba.HActive[k],
+						mode_lib->vba.Output[k],
+						mode_lib->vba.ODMUse[k],
+						mode_lib->vba.MaxDispclk[i],
+						mode_lib->vba.MaxDispclk[v->soc.num_states - 1],
+						false,
+						mode_lib->vba.TotalNumberOfActiveDPP[i][j],
+						mode_lib->vba.MaxNumDPP,
+						mode_lib->vba.PixelClock[k],
+						mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading,
+						mode_lib->vba.DISPCLKRampingMargin,
+						mode_lib->vba.DISPCLKDPPCLKVCOSpeed,
+
+						/* Output */
+						&TotalAvailablePipesSupportNoDSC,
+						&NumberOfDPPNoDSC,
+						&ODMModeNoDSC,
+						&RequiredDISPCLKPerSurfaceNoDSC);
+
+				dml32_CalculateODMMode(
+						mode_lib->vba.MaximumPixelsPerLinePerDSCUnit,
+						mode_lib->vba.HActive[k],
+						mode_lib->vba.Output[k],
+						mode_lib->vba.ODMUse[k],
+						mode_lib->vba.MaxDispclk[i],
+						mode_lib->vba.MaxDispclk[v->soc.num_states - 1],
+						true,
+						mode_lib->vba.TotalNumberOfActiveDPP[i][j],
+						mode_lib->vba.MaxNumDPP,
+						mode_lib->vba.PixelClock[k],
+						mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading,
+						mode_lib->vba.DISPCLKRampingMargin,
+						mode_lib->vba.DISPCLKDPPCLKVCOSpeed,
+
+						/* Output */
+						&TotalAvailablePipesSupportDSC,
+						&NumberOfDPPDSC,
+						&ODMModeDSC,
+						&RequiredDISPCLKPerSurfaceDSC);
+
+				dml32_CalculateOutputLink(
+						mode_lib->vba.PHYCLKPerState[i],
+						mode_lib->vba.PHYCLKD18PerState[i],
+						mode_lib->vba.PHYCLKD32PerState[i],
+						mode_lib->vba.Downspreading,
+						(mode_lib->vba.BlendingAndTiming[k] == k),
+						mode_lib->vba.Output[k],
+						mode_lib->vba.OutputFormat[k],
+						mode_lib->vba.HTotal[k],
+						mode_lib->vba.HActive[k],
+						mode_lib->vba.PixelClockBackEnd[k],
+						mode_lib->vba.ForcedOutputLinkBPP[k],
+						mode_lib->vba.DSCInputBitPerComponent[k],
+						mode_lib->vba.NumberOfDSCSlices[k],
+						mode_lib->vba.AudioSampleRate[k],
+						mode_lib->vba.AudioSampleLayout[k],
+						ODMModeNoDSC,
+						ODMModeDSC,
+						mode_lib->vba.DSCEnable[k],
+						mode_lib->vba.OutputLinkDPLanes[k],
+						mode_lib->vba.OutputLinkDPRate[k],
+
+						/* Output */
+						&mode_lib->vba.RequiresDSC[i][k],
+						&mode_lib->vba.RequiresFEC[i][k],
+						&mode_lib->vba.OutputBppPerState[i][k],
+						&mode_lib->vba.OutputTypePerState[i][k],
+						&mode_lib->vba.OutputRatePerState[i][k],
+						&mode_lib->vba.RequiredSlots[i][k]);
+
+				if (mode_lib->vba.RequiresDSC[i][k] == false) {
+					mode_lib->vba.ODMCombineEnablePerState[i][k] = ODMModeNoDSC;
+					mode_lib->vba.RequiredDISPCLKPerSurface[i][j][k] =
+							RequiredDISPCLKPerSurfaceNoDSC;
+					if (!TotalAvailablePipesSupportNoDSC)
+						mode_lib->vba.TotalAvailablePipesSupport[i][j] = false;
+					mode_lib->vba.TotalNumberOfActiveDPP[i][j] =
+							mode_lib->vba.TotalNumberOfActiveDPP[i][j] + NumberOfDPPNoDSC;
+				} else {
+					mode_lib->vba.ODMCombineEnablePerState[i][k] = ODMModeDSC;
+					mode_lib->vba.RequiredDISPCLKPerSurface[i][j][k] =
+							RequiredDISPCLKPerSurfaceDSC;
+					if (!TotalAvailablePipesSupportDSC)
+						mode_lib->vba.TotalAvailablePipesSupport[i][j] = false;
+					mode_lib->vba.TotalNumberOfActiveDPP[i][j] =
+							mode_lib->vba.TotalNumberOfActiveDPP[i][j] + NumberOfDPPDSC;
+				}
+			}
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
+					mode_lib->vba.MPCCombine[i][j][k] = false;
+					mode_lib->vba.NoOfDPP[i][j][k] = 4;
+				} else if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
+					mode_lib->vba.MPCCombine[i][j][k] = false;
+					mode_lib->vba.NoOfDPP[i][j][k] = 2;
+				} else if (mode_lib->vba.MPCCombineUse[k] == dm_mpc_never) {
+					mode_lib->vba.MPCCombine[i][j][k] = false;
+					mode_lib->vba.NoOfDPP[i][j][k] = 1;
+				} else if (dml32_RoundToDFSGranularity(
+						mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
+								* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
+												/ 100), 1,
+						mode_lib->vba.DISPCLKDPPCLKVCOSpeed) <= mode_lib->vba.MaxDppclk[i] &&
+				mode_lib->vba.SingleDPPViewportSizeSupportPerSurface[k] == true) {
+					mode_lib->vba.MPCCombine[i][j][k] = false;
+					mode_lib->vba.NoOfDPP[i][j][k] = 1;
+				} else if (mode_lib->vba.TotalNumberOfActiveDPP[i][j] < mode_lib->vba.MaxNumDPP) {
+					mode_lib->vba.MPCCombine[i][j][k] = true;
+					mode_lib->vba.NoOfDPP[i][j][k] = 2;
+					mode_lib->vba.TotalNumberOfActiveDPP[i][j] =
+							mode_lib->vba.TotalNumberOfActiveDPP[i][j] + 1;
+				} else {
+					mode_lib->vba.MPCCombine[i][j][k] = false;
+					mode_lib->vba.NoOfDPP[i][j][k] = 1;
+					mode_lib->vba.TotalAvailablePipesSupport[i][j] = false;
+				}
+			}
+
+			mode_lib->vba.TotalNumberOfSingleDPPSurfaces[i][j] = 0;
+			NoChroma = true;
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				if (mode_lib->vba.NoOfDPP[i][j][k] == 1)
+					mode_lib->vba.TotalNumberOfSingleDPPSurfaces[i][j] =
+							mode_lib->vba.TotalNumberOfSingleDPPSurfaces[i][j] + 1;
+				if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
+						|| mode_lib->vba.SourcePixelFormat[k] == dm_420_10
+						|| mode_lib->vba.SourcePixelFormat[k] == dm_420_12
+						|| mode_lib->vba.SourcePixelFormat[k] == dm_rgbe_alpha) {
+					NoChroma = false;
+				}
+			}
+
+			if (j == 1 && !dml32_UnboundedRequest(mode_lib->vba.UseUnboundedRequesting,
+							mode_lib->vba.TotalNumberOfActiveDPP[i][j], NoChroma,
+							mode_lib->vba.Output[0])) {
+				while (!(mode_lib->vba.TotalNumberOfActiveDPP[i][j] >= mode_lib->vba.MaxNumDPP
+						|| mode_lib->vba.TotalNumberOfSingleDPPSurfaces[i][j] == 0)) {
+					double BWOfNonCombinedSurfaceOfMaximumBandwidth = 0;
+					unsigned int NumberOfNonCombinedSurfaceOfMaximumBandwidth = 0;
+
+					for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+						if (mode_lib->vba.MPCCombineUse[k]
+							!= dm_mpc_never &&
+							mode_lib->vba.MPCCombineUse[k] != dm_mpc_reduce_voltage &&
+							mode_lib->vba.ReadBandwidthLuma[k] +
+							mode_lib->vba.ReadBandwidthChroma[k] >
+							BWOfNonCombinedSurfaceOfMaximumBandwidth &&
+							(mode_lib->vba.ODMCombineEnablePerState[i][k] !=
+							dm_odm_combine_mode_2to1 &&
+							mode_lib->vba.ODMCombineEnablePerState[i][k] !=
+							dm_odm_combine_mode_4to1) &&
+								mode_lib->vba.MPCCombine[i][j][k] == false) {
+							BWOfNonCombinedSurfaceOfMaximumBandwidth =
+								mode_lib->vba.ReadBandwidthLuma[k]
+								+ mode_lib->vba.ReadBandwidthChroma[k];
+							NumberOfNonCombinedSurfaceOfMaximumBandwidth = k;
+						}
+					}
+					mode_lib->vba.MPCCombine[i][j][NumberOfNonCombinedSurfaceOfMaximumBandwidth] =
+							true;
+					mode_lib->vba.NoOfDPP[i][j][NumberOfNonCombinedSurfaceOfMaximumBandwidth] = 2;
+					mode_lib->vba.TotalNumberOfActiveDPP[i][j] =
+							mode_lib->vba.TotalNumberOfActiveDPP[i][j] + 1;
+					mode_lib->vba.TotalNumberOfSingleDPPSurfaces[i][j] =
+							mode_lib->vba.TotalNumberOfSingleDPPSurfaces[i][j] - 1;
+				}
+			}
+
+			//DISPCLK/DPPCLK
+			mode_lib->vba.WritebackRequiredDISPCLK = 0;
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				if (mode_lib->vba.WritebackEnable[k]) {
+					mode_lib->vba.WritebackRequiredDISPCLK = dml_max(
+							mode_lib->vba.WritebackRequiredDISPCLK,
+							dml32_CalculateWriteBackDISPCLK(
+									mode_lib->vba.WritebackPixelFormat[k],
+									mode_lib->vba.PixelClock[k],
+									mode_lib->vba.WritebackHRatio[k],
+									mode_lib->vba.WritebackVRatio[k],
+									mode_lib->vba.WritebackHTaps[k],
+									mode_lib->vba.WritebackVTaps[k],
+									mode_lib->vba.WritebackSourceWidth[k],
+									mode_lib->vba.WritebackDestinationWidth[k],
+									mode_lib->vba.HTotal[k],
+									mode_lib->vba.WritebackLineBufferSize,
+									mode_lib->vba.DISPCLKDPPCLKVCOSpeed));
+				}
+			}
+
+			mode_lib->vba.RequiredDISPCLK[i][j] = mode_lib->vba.WritebackRequiredDISPCLK;
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				mode_lib->vba.RequiredDISPCLK[i][j] = dml_max(mode_lib->vba.RequiredDISPCLK[i][j],
+						mode_lib->vba.RequiredDISPCLKPerSurface[i][j][k]);
+			}
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
+				mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k];
+
+			dml32_CalculateDPPCLK(mode_lib->vba.NumberOfActiveSurfaces,
+					mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading,
+					mode_lib->vba.DISPCLKDPPCLKVCOSpeed, mode_lib->vba.MinDPPCLKUsingSingleDPP,
+					mode_lib->vba.NoOfDPPThisState,
+					/* Output */
+					&mode_lib->vba.GlobalDPPCLK, mode_lib->vba.RequiredDPPCLKThisState);
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
+				mode_lib->vba.RequiredDPPCLK[i][j][k] = mode_lib->vba.RequiredDPPCLKThisState[k];
+
+			mode_lib->vba.DISPCLK_DPPCLK_Support[i][j] = !((mode_lib->vba.RequiredDISPCLK[i][j]
+					> mode_lib->vba.MaxDispclk[i])
+					|| (mode_lib->vba.GlobalDPPCLK > mode_lib->vba.MaxDppclk[i]));
+
+			if (mode_lib->vba.TotalNumberOfActiveDPP[i][j] > mode_lib->vba.MaxNumDPP)
+				mode_lib->vba.TotalAvailablePipesSupport[i][j] = false;
+		} // j
+	} // i (VOLTAGE_STATE)
+
+	/* Total Available OTG, HDMIFRL, DP Support Check */
+	TotalNumberOfActiveOTG = 0;
+	TotalNumberOfActiveHDMIFRL = 0;
+	TotalNumberOfActiveDP2p0 = 0;
+	TotalNumberOfActiveDP2p0Outputs = 0;
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		if (mode_lib->vba.BlendingAndTiming[k] == k) {
+			TotalNumberOfActiveOTG = TotalNumberOfActiveOTG + 1;
+			if (mode_lib->vba.Output[k] == dm_dp2p0) {
+				TotalNumberOfActiveDP2p0 = TotalNumberOfActiveDP2p0 + 1;
+				if (mode_lib->vba.OutputMultistreamId[k]
+						== k || mode_lib->vba.OutputMultistreamEn[k] == false) {
+					TotalNumberOfActiveDP2p0Outputs = TotalNumberOfActiveDP2p0Outputs + 1;
+				}
+			}
+		}
+	}
+
+	mode_lib->vba.NumberOfOTGSupport = (TotalNumberOfActiveOTG <= mode_lib->vba.MaxNumOTG);
+	mode_lib->vba.NumberOfHDMIFRLSupport = (TotalNumberOfActiveHDMIFRL <= mode_lib->vba.MaxNumHDMIFRLOutputs);
+	mode_lib->vba.NumberOfDP2p0Support = (TotalNumberOfActiveDP2p0 <= mode_lib->vba.MaxNumDP2p0Streams
+			&& TotalNumberOfActiveDP2p0Outputs <= mode_lib->vba.MaxNumDP2p0Outputs);
+
+	/* Display IO and DSC Support Check */
+	mode_lib->vba.NonsupportedDSCInputBPC = false;
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (!(mode_lib->vba.DSCInputBitPerComponent[k] == 12.0
+				|| mode_lib->vba.DSCInputBitPerComponent[k] == 10.0
+				|| mode_lib->vba.DSCInputBitPerComponent[k] == 8.0
+				|| mode_lib->vba.DSCInputBitPerComponent[k] >
+				mode_lib->vba.MaximumDSCBitsPerComponent)) {
+			mode_lib->vba.NonsupportedDSCInputBPC = true;
+		}
+	}
+
+	for (i = 0; i < v->soc.num_states; ++i) {
+		unsigned int TotalSlots;
+
+		mode_lib->vba.ExceededMultistreamSlots[i] = false;
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == k) {
+				TotalSlots = mode_lib->vba.RequiredSlots[i][k];
+				for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; ++j) {
+					if (mode_lib->vba.OutputMultistreamId[j] == k)
+						TotalSlots = TotalSlots + mode_lib->vba.RequiredSlots[i][j];
+				}
+				if (mode_lib->vba.Output[k] == dm_dp && TotalSlots > 63)
+					mode_lib->vba.ExceededMultistreamSlots[i] = true;
+				if (mode_lib->vba.Output[k] == dm_dp2p0 && TotalSlots > 64)
+					mode_lib->vba.ExceededMultistreamSlots[i] = true;
+			}
+		}
+		mode_lib->vba.LinkCapacitySupport[i] = true;
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			if (mode_lib->vba.BlendingAndTiming[k] == k
+					&& (mode_lib->vba.Output[k] == dm_dp || mode_lib->vba.Output[k] == dm_dp2p0
+							|| mode_lib->vba.Output[k] == dm_edp
+							|| mode_lib->vba.Output[k] == dm_hdmi)
+					&& mode_lib->vba.OutputBppPerState[i][k] == 0) {
+				mode_lib->vba.LinkCapacitySupport[i] = false;
+			}
+		}
+	}
+
+	mode_lib->vba.P2IWith420 = false;
+	mode_lib->vba.DSCOnlyIfNecessaryWithBPP = false;
+	mode_lib->vba.DSC422NativeNotSupported = false;
+	mode_lib->vba.LinkRateDoesNotMatchDPVersion = false;
+	mode_lib->vba.LinkRateForMultistreamNotIndicated = false;
+	mode_lib->vba.BPPForMultistreamNotIndicated = false;
+	mode_lib->vba.MultistreamWithHDMIOreDP = false;
+	mode_lib->vba.MSOOrODMSplitWithNonDPLink = false;
+	mode_lib->vba.NotEnoughLanesForMSO = false;
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		if (mode_lib->vba.BlendingAndTiming[k] == k
+				&& (mode_lib->vba.Output[k] == dm_dp || mode_lib->vba.Output[k] == dm_dp2p0
+						|| mode_lib->vba.Output[k] == dm_edp
+						|| mode_lib->vba.Output[k] == dm_hdmi)) {
+			if (mode_lib->vba.OutputFormat[k]
+					== dm_420 && mode_lib->vba.Interlace[k] == 1 &&
+					mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true)
+				mode_lib->vba.P2IWith420 = true;
+
+			if (mode_lib->vba.DSCEnable[k] && mode_lib->vba.ForcedOutputLinkBPP[k] != 0)
+				mode_lib->vba.DSCOnlyIfNecessaryWithBPP = true;
+			if ((mode_lib->vba.DSCEnable[k] || mode_lib->vba.DSCEnable[k])
+					&& mode_lib->vba.OutputFormat[k] == dm_n422
+					&& !mode_lib->vba.DSC422NativeSupport)
+				mode_lib->vba.DSC422NativeNotSupported = true;
+
+			if (((mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_hbr
+					|| mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_hbr2
+					|| mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_hbr3)
+					&& mode_lib->vba.Output[k] != dm_dp && mode_lib->vba.Output[k] != dm_edp)
+					|| ((mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_uhbr10
+							|| mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_uhbr13p5
+							|| mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_uhbr20)
+							&& mode_lib->vba.Output[k] != dm_dp2p0))
+				mode_lib->vba.LinkRateDoesNotMatchDPVersion = true;
+
+			if (mode_lib->vba.OutputMultistreamEn[k] == true) {
+				if (mode_lib->vba.OutputMultistreamId[k] == k
+					&& mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_na)
+					mode_lib->vba.LinkRateForMultistreamNotIndicated = true;
+				if (mode_lib->vba.OutputMultistreamId[k] == k && mode_lib->vba.ForcedOutputLinkBPP[k] == 0)
+					mode_lib->vba.BPPForMultistreamNotIndicated = true;
+				for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; ++j) {
+					if (mode_lib->vba.OutputMultistreamId[k] == j && mode_lib->vba.OutputMultistreamEn[k]
+						&& mode_lib->vba.ForcedOutputLinkBPP[k] == 0)
+						mode_lib->vba.BPPForMultistreamNotIndicated = true;
+				}
+			}
+
+			if ((mode_lib->vba.Output[k] == dm_edp || mode_lib->vba.Output[k] == dm_hdmi)) {
+				if (mode_lib->vba.OutputMultistreamId[k] == k && mode_lib->vba.OutputMultistreamEn[k])
+					mode_lib->vba.MultistreamWithHDMIOreDP = true;
+
+				for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; ++j) {
+					if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == j)
+						mode_lib->vba.MultistreamWithHDMIOreDP = true;
+				}
+			}
+
+			if (mode_lib->vba.Output[k] != dm_dp
+					&& (mode_lib->vba.ODMUse[k] == dm_odm_split_policy_1to2
+							|| mode_lib->vba.ODMUse[k] == dm_odm_mso_policy_1to2
+							|| mode_lib->vba.ODMUse[k] == dm_odm_mso_policy_1to4))
+				mode_lib->vba.MSOOrODMSplitWithNonDPLink = true;
+
+			if ((mode_lib->vba.ODMUse[k] == dm_odm_mso_policy_1to2
+					&& mode_lib->vba.OutputLinkDPLanes[k] < 2)
+					|| (mode_lib->vba.ODMUse[k] == dm_odm_mso_policy_1to4
+							&& mode_lib->vba.OutputLinkDPLanes[k] < 4))
+				mode_lib->vba.NotEnoughLanesForMSO = true;
+		}
+	}
+
+	for (i = 0; i < v->soc.num_states; ++i) {
+		mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] = false;
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			if (mode_lib->vba.BlendingAndTiming[k] == k
+					&& dml32_RequiredDTBCLK(mode_lib->vba.RequiresDSC[i][k],
+							mode_lib->vba.PixelClockBackEnd[k],
+							mode_lib->vba.OutputFormat[k],
+							mode_lib->vba.OutputBppPerState[i][k],
+							mode_lib->vba.NumberOfDSCSlices[k], mode_lib->vba.HTotal[k],
+							mode_lib->vba.HActive[k], mode_lib->vba.AudioSampleRate[k],
+							mode_lib->vba.AudioSampleLayout[k])
+							> mode_lib->vba.DTBCLKPerState[i]) {
+				mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] = true;
+			}
+		}
+	}
+
+	for (i = 0; i < v->soc.num_states; ++i) {
+		mode_lib->vba.ODMCombine2To1SupportCheckOK[i] = true;
+		mode_lib->vba.ODMCombine4To1SupportCheckOK[i] = true;
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			if (mode_lib->vba.BlendingAndTiming[k] == k
+					&& mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1
+					&& mode_lib->vba.Output[k] == dm_hdmi) {
+				mode_lib->vba.ODMCombine2To1SupportCheckOK[i] = false;
+			}
+			if (mode_lib->vba.BlendingAndTiming[k] == k
+					&& mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
+					&& (mode_lib->vba.Output[k] == dm_dp || mode_lib->vba.Output[k] == dm_edp
+							|| mode_lib->vba.Output[k] == dm_hdmi)) {
+				mode_lib->vba.ODMCombine4To1SupportCheckOK[i] = false;
+			}
+		}
+	}
+
+	for (i = 0; i < v->soc.num_states; i++) {
+		mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = false;
+		for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+			if (mode_lib->vba.BlendingAndTiming[k] == k) {
+				if (mode_lib->vba.Output[k] == dm_dp || mode_lib->vba.Output[k] == dm_dp2p0
+						|| mode_lib->vba.Output[k] == dm_edp) {
+					if (mode_lib->vba.OutputFormat[k] == dm_420) {
+						mode_lib->vba.DSCFormatFactor = 2;
+					} else if (mode_lib->vba.OutputFormat[k] == dm_444) {
+						mode_lib->vba.DSCFormatFactor = 1;
+					} else if (mode_lib->vba.OutputFormat[k] == dm_n422) {
+						mode_lib->vba.DSCFormatFactor = 2;
+					} else {
+						mode_lib->vba.DSCFormatFactor = 1;
+					}
+					if (mode_lib->vba.RequiresDSC[i][k] == true) {
+						if (mode_lib->vba.ODMCombineEnablePerState[i][k]
+								== dm_odm_combine_mode_4to1) {
+							if (mode_lib->vba.PixelClockBackEnd[k] / 12.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i])
+								mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = true;
+						} else if (mode_lib->vba.ODMCombineEnablePerState[i][k]
+								== dm_odm_combine_mode_2to1) {
+							if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i])
+								mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = true;
+						} else {
+							if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i])
+								mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = true;
+						}
+					}
+				}
+			}
+		}
+	}
+
+	/* Check DSC Unit and Slices Support */
+	TotalDSCUnitsRequired = 0;
+
+	for (i = 0; i < v->soc.num_states; ++i) {
+		mode_lib->vba.NotEnoughDSCUnits[i] = false;
+		mode_lib->vba.NotEnoughDSCSlices[i] = false;
+		TotalDSCUnitsRequired = 0;
+		mode_lib->vba.PixelsPerLinePerDSCUnitSupport[i] = true;
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			if (mode_lib->vba.RequiresDSC[i][k] == true) {
+				if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
+					if (mode_lib->vba.HActive[k]
+							> 4 * mode_lib->vba.MaximumPixelsPerLinePerDSCUnit)
+						mode_lib->vba.PixelsPerLinePerDSCUnitSupport[i] = false;
+					TotalDSCUnitsRequired = TotalDSCUnitsRequired + 4;
+					if (mode_lib->vba.NumberOfDSCSlices[k] > 16)
+						mode_lib->vba.NotEnoughDSCSlices[i] = true;
+				} else if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
+					if (mode_lib->vba.HActive[k]
+							> 2 * mode_lib->vba.MaximumPixelsPerLinePerDSCUnit)
+						mode_lib->vba.PixelsPerLinePerDSCUnitSupport[i] = false;
+					TotalDSCUnitsRequired = TotalDSCUnitsRequired + 2;
+					if (mode_lib->vba.NumberOfDSCSlices[k] > 8)
+						mode_lib->vba.NotEnoughDSCSlices[i] = true;
+				} else {
+					if (mode_lib->vba.HActive[k] > mode_lib->vba.MaximumPixelsPerLinePerDSCUnit)
+						mode_lib->vba.PixelsPerLinePerDSCUnitSupport[i] = false;
+					TotalDSCUnitsRequired = TotalDSCUnitsRequired + 1;
+					if (mode_lib->vba.NumberOfDSCSlices[k] > 4)
+						mode_lib->vba.NotEnoughDSCSlices[i] = true;
+				}
+			}
+		}
+		if (TotalDSCUnitsRequired > mode_lib->vba.NumberOfDSC)
+			mode_lib->vba.NotEnoughDSCUnits[i] = true;
+	}
+
+	/*DSC Delay per state*/
+	for (i = 0; i < v->soc.num_states; ++i) {
+		unsigned int m;
+
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			mode_lib->vba.DSCDelayPerState[i][k] = dml32_DSCDelayRequirement(
+					mode_lib->vba.RequiresDSC[i][k], mode_lib->vba.ODMCombineEnablePerState[i][k],
+					mode_lib->vba.DSCInputBitPerComponent[k],
+					mode_lib->vba.OutputBppPerState[i][k], mode_lib->vba.HActive[k],
+					mode_lib->vba.HTotal[k], mode_lib->vba.NumberOfDSCSlices[k],
+					mode_lib->vba.OutputFormat[k], mode_lib->vba.Output[k],
+					mode_lib->vba.PixelClock[k], mode_lib->vba.PixelClockBackEnd[k]);
+		}
+
+		m = 0;
+
+		for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+			for (m = 0; m <= mode_lib->vba.NumberOfActiveSurfaces - 1; m++) {
+				for (j = 0; j <= mode_lib->vba.NumberOfActiveSurfaces - 1; j++) {
+					if (mode_lib->vba.BlendingAndTiming[k] == m &&
+							mode_lib->vba.RequiresDSC[i][m] == true) {
+						mode_lib->vba.DSCDelayPerState[i][k] =
+							mode_lib->vba.DSCDelayPerState[i][m];
+					}
+				}
+			}
+		}
+	}
+
+	//Calculate Swath, DET Configuration, DCFCLKDeepSleep
+	//
+	for (i = 0; i < (int) v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			bool dummy_boolean_array[1][DC__NUM_DPP__MAX];
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				mode_lib->vba.RequiredDPPCLKThisState[k] = mode_lib->vba.RequiredDPPCLK[i][j][k];
+				mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k];
+				mode_lib->vba.ODMCombineEnableThisState[k] =
+						mode_lib->vba.ODMCombineEnablePerState[i][k];
+			}
+
+			dml32_CalculateSwathAndDETConfiguration(
+					mode_lib->vba.DETSizeOverride,
+					mode_lib->vba.UsesMALLForPStateChange,
+					mode_lib->vba.ConfigReturnBufferSizeInKByte,
+					mode_lib->vba.MaxTotalDETInKByte,
+					mode_lib->vba.MinCompressedBufferSizeInKByte,
+					false, /* ForceSingleDPP */
+					mode_lib->vba.NumberOfActiveSurfaces,
+					mode_lib->vba.nomDETInKByte,
+					mode_lib->vba.UseUnboundedRequesting,
+					mode_lib->vba.CompressedBufferSegmentSizeInkByteFinal,
+					mode_lib->vba.Output,
+					mode_lib->vba.ReadBandwidthLuma,
+					mode_lib->vba.ReadBandwidthChroma,
+					mode_lib->vba.MaximumSwathWidthLuma,
+					mode_lib->vba.MaximumSwathWidthChroma,
+					mode_lib->vba.SourceRotation,
+					mode_lib->vba.ViewportStationary,
+					mode_lib->vba.SourcePixelFormat,
+					mode_lib->vba.SurfaceTiling,
+					mode_lib->vba.ViewportWidth,
+					mode_lib->vba.ViewportHeight,
+					mode_lib->vba.ViewportXStartY,
+					mode_lib->vba.ViewportYStartY,
+					mode_lib->vba.ViewportXStartC,
+					mode_lib->vba.ViewportYStartC,
+					mode_lib->vba.SurfaceWidthY,
+					mode_lib->vba.SurfaceWidthC,
+					mode_lib->vba.SurfaceHeightY,
+					mode_lib->vba.SurfaceHeightC,
+					mode_lib->vba.Read256BlockHeightY,
+					mode_lib->vba.Read256BlockHeightC,
+					mode_lib->vba.Read256BlockWidthY,
+					mode_lib->vba.Read256BlockWidthC,
+					mode_lib->vba.ODMCombineEnableThisState,
+					mode_lib->vba.BlendingAndTiming,
+					mode_lib->vba.BytePerPixelY,
+					mode_lib->vba.BytePerPixelC,
+					mode_lib->vba.BytePerPixelInDETY,
+					mode_lib->vba.BytePerPixelInDETC,
+					mode_lib->vba.HActive,
+					mode_lib->vba.HRatio,
+					mode_lib->vba.HRatioChroma,
+					mode_lib->vba.NoOfDPPThisState,
+					/* Output */
+					mode_lib->vba.swath_width_luma_ub_this_state,
+					mode_lib->vba.swath_width_chroma_ub_this_state,
+					mode_lib->vba.SwathWidthYThisState,
+					mode_lib->vba.SwathWidthCThisState,
+					mode_lib->vba.SwathHeightYThisState,
+					mode_lib->vba.SwathHeightCThisState,
+					mode_lib->vba.DETBufferSizeInKByteThisState,
+					mode_lib->vba.DETBufferSizeYThisState,
+					mode_lib->vba.DETBufferSizeCThisState,
+					&mode_lib->vba.UnboundedRequestEnabledThisState,
+					&mode_lib->vba.CompressedBufferSizeInkByteThisState,
+					dummy_boolean_array[0],
+					&mode_lib->vba.ViewportSizeSupport[i][j]);
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				mode_lib->vba.swath_width_luma_ub_all_states[i][j][k] =
+						mode_lib->vba.swath_width_luma_ub_this_state[k];
+				mode_lib->vba.swath_width_chroma_ub_all_states[i][j][k] =
+						mode_lib->vba.swath_width_chroma_ub_this_state[k];
+				mode_lib->vba.SwathWidthYAllStates[i][j][k] = mode_lib->vba.SwathWidthYThisState[k];
+				mode_lib->vba.SwathWidthCAllStates[i][j][k] = mode_lib->vba.SwathWidthCThisState[k];
+				mode_lib->vba.SwathHeightYAllStates[i][j][k] = mode_lib->vba.SwathHeightYThisState[k];
+				mode_lib->vba.SwathHeightCAllStates[i][j][k] = mode_lib->vba.SwathHeightCThisState[k];
+				mode_lib->vba.UnboundedRequestEnabledAllStates[i][j] =
+						mode_lib->vba.UnboundedRequestEnabledThisState;
+				mode_lib->vba.CompressedBufferSizeInkByteAllStates[i][j] =
+						mode_lib->vba.CompressedBufferSizeInkByteThisState;
+				mode_lib->vba.DETBufferSizeInKByteAllStates[i][j][k] =
+						mode_lib->vba.DETBufferSizeInKByteThisState[k];
+				mode_lib->vba.DETBufferSizeYAllStates[i][j][k] =
+						mode_lib->vba.DETBufferSizeYThisState[k];
+				mode_lib->vba.DETBufferSizeCAllStates[i][j][k] =
+						mode_lib->vba.DETBufferSizeCThisState[k];
+			}
+		}
+	}
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		mode_lib->vba.cursor_bw[k] = mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0]
+				* mode_lib->vba.CursorBPP[k][0] / 8.0
+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
+	}
+
+	dml32_CalculateSurfaceSizeInMall(
+			mode_lib->vba.NumberOfActiveSurfaces,
+			mode_lib->vba.MALLAllocatedForDCNFinal,
+			mode_lib->vba.UseMALLForStaticScreen,
+			mode_lib->vba.DCCEnable,
+			mode_lib->vba.ViewportStationary,
+			mode_lib->vba.ViewportXStartY,
+			mode_lib->vba.ViewportYStartY,
+			mode_lib->vba.ViewportXStartC,
+			mode_lib->vba.ViewportYStartC,
+			mode_lib->vba.ViewportWidth,
+			mode_lib->vba.ViewportHeight,
+			mode_lib->vba.BytePerPixelY,
+			mode_lib->vba.ViewportWidthChroma,
+			mode_lib->vba.ViewportHeightChroma,
+			mode_lib->vba.BytePerPixelC,
+			mode_lib->vba.SurfaceWidthY,
+			mode_lib->vba.SurfaceWidthC,
+			mode_lib->vba.SurfaceHeightY,
+			mode_lib->vba.SurfaceHeightC,
+			mode_lib->vba.Read256BlockWidthY,
+			mode_lib->vba.Read256BlockWidthC,
+			mode_lib->vba.Read256BlockHeightY,
+			mode_lib->vba.Read256BlockHeightC,
+			mode_lib->vba.MicroTileWidthY,
+			mode_lib->vba.MicroTileWidthC,
+			mode_lib->vba.MicroTileHeightY,
+			mode_lib->vba.MicroTileHeightC,
+
+			/* Output */
+			mode_lib->vba.SurfaceSizeInMALL,
+			&mode_lib->vba.ExceededMALLSize);
+
+	for (i = 0; i < v->soc.num_states; i++) {
+		for (j = 0; j < 2; j++) {
+			for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+				mode_lib->vba.swath_width_luma_ub_this_state[k] =
+						mode_lib->vba.swath_width_luma_ub_all_states[i][j][k];
+				mode_lib->vba.swath_width_chroma_ub_this_state[k] =
+						mode_lib->vba.swath_width_chroma_ub_all_states[i][j][k];
+				mode_lib->vba.SwathWidthYThisState[k] = mode_lib->vba.SwathWidthYAllStates[i][j][k];
+				mode_lib->vba.SwathWidthCThisState[k] = mode_lib->vba.SwathWidthCAllStates[i][j][k];
+				mode_lib->vba.SwathHeightYThisState[k] = mode_lib->vba.SwathHeightYAllStates[i][j][k];
+				mode_lib->vba.SwathHeightCThisState[k] = mode_lib->vba.SwathHeightCAllStates[i][j][k];
+				mode_lib->vba.DETBufferSizeInKByteThisState[k] =
+						mode_lib->vba.DETBufferSizeInKByteAllStates[i][j][k];
+				mode_lib->vba.DETBufferSizeYThisState[k] =
+						mode_lib->vba.DETBufferSizeYAllStates[i][j][k];
+				mode_lib->vba.DETBufferSizeCThisState[k] =
+						mode_lib->vba.DETBufferSizeCAllStates[i][j][k];
+				mode_lib->vba.RequiredDPPCLKThisState[k] = mode_lib->vba.RequiredDPPCLK[i][j][k];
+				mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k];
+			}
+
+			mode_lib->vba.TotalNumberOfDCCActiveDPP[i][j] = 0;
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				if (mode_lib->vba.DCCEnable[k] == true) {
+					mode_lib->vba.TotalNumberOfDCCActiveDPP[i][j] =
+							mode_lib->vba.TotalNumberOfDCCActiveDPP[i][j]
+									+ mode_lib->vba.NoOfDPP[i][j][k];
+				}
+			}
+
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].PixelClock = mode_lib->vba.PixelClock[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DPPPerSurface = mode_lib->vba.NoOfDPP[i][j][k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SourceRotation = mode_lib->vba.SourceRotation[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportHeight = mode_lib->vba.ViewportHeight[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportHeightChroma = mode_lib->vba.ViewportHeightChroma[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidth256BytesY = mode_lib->vba.Read256BlockWidthY[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeight256BytesY = mode_lib->vba.Read256BlockHeightY[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidth256BytesC = mode_lib->vba.Read256BlockWidthC[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeight256BytesC = mode_lib->vba.Read256BlockHeightC[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthY = mode_lib->vba.MicroTileWidthY[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightY = mode_lib->vba.MicroTileHeightY[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthC = mode_lib->vba.MicroTileWidthC[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightC = mode_lib->vba.MicroTileHeightC[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].InterlaceEnable = mode_lib->vba.Interlace[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].HTotal = mode_lib->vba.HTotal[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DCCEnable = mode_lib->vba.DCCEnable[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SurfaceTiling = mode_lib->vba.SurfaceTiling[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BytePerPixelY = mode_lib->vba.BytePerPixelY[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BytePerPixelC = mode_lib->vba.BytePerPixelC[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ProgressiveToInterlaceUnitInOPP =
+				mode_lib->vba.ProgressiveToInterlaceUnitInOPP;
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VRatio = mode_lib->vba.VRatio[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VRatioChroma = mode_lib->vba.VRatioChroma[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VTaps = mode_lib->vba.vtaps[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VTapsChroma = mode_lib->vba.VTAPsChroma[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].PitchY = mode_lib->vba.PitchY[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DCCMetaPitchY = mode_lib->vba.DCCMetaPitchY[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].PitchC = mode_lib->vba.PitchC[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DCCMetaPitchC = mode_lib->vba.DCCMetaPitchC[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportStationary = mode_lib->vba.ViewportStationary[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportXStart = mode_lib->vba.ViewportXStartY[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportYStart = mode_lib->vba.ViewportYStartY[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportXStartC = mode_lib->vba.ViewportXStartC[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportYStartC = mode_lib->vba.ViewportYStartC[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].FORCE_ONE_ROW_FOR_FRAME = mode_lib->vba.ForceOneRowForFrame[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SwathHeightY = mode_lib->vba.SwathHeightYThisState[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SwathHeightC = mode_lib->vba.SwathHeightCThisState[k];
+			}
+
+			{
+				bool dummy_boolean_array[2][DC__NUM_DPP__MAX];
+				unsigned int dummy_integer_array[22][DC__NUM_DPP__MAX];
+
+				dml32_CalculateVMRowAndSwath(
+						mode_lib->vba.NumberOfActiveSurfaces,
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters,
+						mode_lib->vba.SurfaceSizeInMALL,
+						mode_lib->vba.PTEBufferSizeInRequestsLuma,
+						mode_lib->vba.PTEBufferSizeInRequestsChroma,
+						mode_lib->vba.DCCMetaBufferSizeBytes,
+						mode_lib->vba.UseMALLForStaticScreen,
+						mode_lib->vba.UsesMALLForPStateChange,
+						mode_lib->vba.MALLAllocatedForDCNFinal,
+						mode_lib->vba.SwathWidthYThisState,
+						mode_lib->vba.SwathWidthCThisState,
+						mode_lib->vba.GPUVMEnable,
+						mode_lib->vba.HostVMEnable,
+						mode_lib->vba.HostVMMaxNonCachedPageTableLevels,
+						mode_lib->vba.GPUVMMaxPageTableLevels,
+						mode_lib->vba.GPUVMMinPageSizeKBytes,
+						mode_lib->vba.HostVMMinPageSize,
+
+						/* Output */
+						mode_lib->vba.PTEBufferSizeNotExceededPerState,
+						mode_lib->vba.DCCMetaBufferSizeNotExceededPerState,
+						dummy_integer_array[0],
+						dummy_integer_array[1],
+						mode_lib->vba.dpte_row_height,
+						mode_lib->vba.dpte_row_height_chroma,
+						dummy_integer_array[2],
+						dummy_integer_array[3],
+						dummy_integer_array[4],
+						dummy_integer_array[5],
+						dummy_integer_array[6],
+						dummy_integer_array[7],
+						dummy_integer_array[8],
+						dummy_integer_array[9],
+						mode_lib->vba.meta_row_height,
+						mode_lib->vba.meta_row_height_chroma,
+						dummy_integer_array[10],
+						mode_lib->vba.dpte_group_bytes,
+						dummy_integer_array[11],
+						dummy_integer_array[12],
+						dummy_integer_array[13],
+						dummy_integer_array[14],
+						dummy_integer_array[15],
+						dummy_integer_array[16],
+						dummy_integer_array[17],
+						dummy_integer_array[18],
+						dummy_integer_array[19],
+						dummy_integer_array[20],
+						mode_lib->vba.PrefetchLinesYThisState,
+						mode_lib->vba.PrefetchLinesCThisState,
+						mode_lib->vba.PrefillY,
+						mode_lib->vba.PrefillC,
+						mode_lib->vba.MaxNumSwY,
+						mode_lib->vba.MaxNumSwC,
+						mode_lib->vba.meta_row_bandwidth_this_state,
+						mode_lib->vba.dpte_row_bandwidth_this_state,
+						mode_lib->vba.DPTEBytesPerRowThisState,
+						mode_lib->vba.PDEAndMetaPTEBytesPerFrameThisState,
+						mode_lib->vba.MetaRowBytesThisState,
+						mode_lib->vba.use_one_row_for_frame_this_state,
+						mode_lib->vba.use_one_row_for_frame_flip_this_state,
+						dummy_boolean_array[0], // Boolean UsesMALLForStaticScreen[]
+						dummy_boolean_array[1], // Boolean PTE_BUFFER_MODE[]
+						dummy_integer_array[21]); // Long BIGK_FRAGMENT_SIZE[]
+			}
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				mode_lib->vba.PrefetchLinesY[i][j][k] = mode_lib->vba.PrefetchLinesYThisState[k];
+				mode_lib->vba.PrefetchLinesC[i][j][k] = mode_lib->vba.PrefetchLinesCThisState[k];
+				mode_lib->vba.meta_row_bandwidth[i][j][k] =
+						mode_lib->vba.meta_row_bandwidth_this_state[k];
+				mode_lib->vba.dpte_row_bandwidth[i][j][k] =
+						mode_lib->vba.dpte_row_bandwidth_this_state[k];
+				mode_lib->vba.DPTEBytesPerRow[i][j][k] = mode_lib->vba.DPTEBytesPerRowThisState[k];
+				mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k] =
+						mode_lib->vba.PDEAndMetaPTEBytesPerFrameThisState[k];
+				mode_lib->vba.MetaRowBytes[i][j][k] = mode_lib->vba.MetaRowBytesThisState[k];
+				mode_lib->vba.use_one_row_for_frame[i][j][k] =
+						mode_lib->vba.use_one_row_for_frame_this_state[k];
+				mode_lib->vba.use_one_row_for_frame_flip[i][j][k] =
+						mode_lib->vba.use_one_row_for_frame_flip_this_state[k];
+			}
+
+			mode_lib->vba.PTEBufferSizeNotExceeded[i][j] = true;
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				if (mode_lib->vba.PTEBufferSizeNotExceededPerState[k] == false)
+					mode_lib->vba.PTEBufferSizeNotExceeded[i][j] = false;
+			}
+
+			mode_lib->vba.DCCMetaBufferSizeNotExceeded[i][j] = true;
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				if (mode_lib->vba.DCCMetaBufferSizeNotExceededPerState[k] == false)
+					mode_lib->vba.DCCMetaBufferSizeNotExceeded[i][j] = false;
+			}
+
+			mode_lib->vba.UrgLatency[i] = dml32_CalculateUrgentLatency(
+					mode_lib->vba.UrgentLatencyPixelDataOnly,
+					mode_lib->vba.UrgentLatencyPixelMixedWithVMData,
+					mode_lib->vba.UrgentLatencyVMDataOnly, mode_lib->vba.DoUrgentLatencyAdjustment,
+					mode_lib->vba.UrgentLatencyAdjustmentFabricClockComponent,
+					mode_lib->vba.UrgentLatencyAdjustmentFabricClockReference,
+					mode_lib->vba.FabricClockPerState[i]);
+
+			//bool   NotUrgentLatencyHiding[DC__NUM_DPP__MAX];
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				dml32_CalculateUrgentBurstFactor(
+						mode_lib->vba.UsesMALLForPStateChange[k],
+						mode_lib->vba.swath_width_luma_ub_this_state[k],
+						mode_lib->vba.swath_width_chroma_ub_this_state[k],
+						mode_lib->vba.SwathHeightYThisState[k],
+						mode_lib->vba.SwathHeightCThisState[k],
+						(double) mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
+						mode_lib->vba.UrgLatency[i],
+						mode_lib->vba.CursorBufferSize,
+						mode_lib->vba.CursorWidth[k][0],
+						mode_lib->vba.CursorBPP[k][0],
+						mode_lib->vba.VRatio[k],
+						mode_lib->vba.VRatioChroma[k],
+						mode_lib->vba.BytePerPixelInDETY[k],
+						mode_lib->vba.BytePerPixelInDETC[k],
+						mode_lib->vba.DETBufferSizeYThisState[k],
+						mode_lib->vba.DETBufferSizeCThisState[k],
+						/* Output */
+						&mode_lib->vba.UrgentBurstFactorCursor[k],
+						&mode_lib->vba.UrgentBurstFactorLuma[k],
+						&mode_lib->vba.UrgentBurstFactorChroma[k],
+						&mode_lib->vba.NoUrgentLatencyHiding[k]);
+			}
+
+			dml32_CalculateDCFCLKDeepSleep(
+					mode_lib->vba.NumberOfActiveSurfaces,
+					mode_lib->vba.BytePerPixelY,
+					mode_lib->vba.BytePerPixelC,
+					mode_lib->vba.VRatio,
+					mode_lib->vba.VRatioChroma,
+					mode_lib->vba.SwathWidthYThisState,
+					mode_lib->vba.SwathWidthCThisState,
+					mode_lib->vba.NoOfDPPThisState,
+					mode_lib->vba.HRatio,
+					mode_lib->vba.HRatioChroma,
+					mode_lib->vba.PixelClock,
+					mode_lib->vba.PSCL_FACTOR,
+					mode_lib->vba.PSCL_FACTOR_CHROMA,
+					mode_lib->vba.RequiredDPPCLKThisState,
+					mode_lib->vba.ReadBandwidthLuma,
+					mode_lib->vba.ReadBandwidthChroma,
+					mode_lib->vba.ReturnBusWidth,
+
+					/* Output */
+					&mode_lib->vba.ProjectedDCFCLKDeepSleep[i][j]);
+		}
+	}
+
+	m = 0;
+
+	//Calculate Return BW
+	for (i = 0; i < (int) v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+				if (mode_lib->vba.BlendingAndTiming[k] == k) {
+					if (mode_lib->vba.WritebackEnable[k] == true) {
+						mode_lib->vba.WritebackDelayTime[k] =
+							mode_lib->vba.WritebackLatency
+						+ dml32_CalculateWriteBackDelay(
+							mode_lib->vba.WritebackPixelFormat[k],
+							mode_lib->vba.WritebackHRatio[k],
+							mode_lib->vba.WritebackVRatio[k],
+							mode_lib->vba.WritebackVTaps[k],
+							mode_lib->vba.WritebackDestinationWidth[k],
+							mode_lib->vba.WritebackDestinationHeight[k],
+							mode_lib->vba.WritebackSourceHeight[k],
+							mode_lib->vba.HTotal[k])
+							/ mode_lib->vba.RequiredDISPCLK[i][j];
+					} else {
+						mode_lib->vba.WritebackDelayTime[k] = 0.0;
+					}
+					for (m = 0; m <= mode_lib->vba.NumberOfActiveSurfaces - 1; m++) {
+						if (mode_lib->vba.BlendingAndTiming[m]
+								== k && mode_lib->vba.WritebackEnable[m] == true) {
+							mode_lib->vba.WritebackDelayTime[k] =
+								dml_max(mode_lib->vba.WritebackDelayTime[k],
+									mode_lib->vba.WritebackLatency
+								+ dml32_CalculateWriteBackDelay(
+									mode_lib->vba.WritebackPixelFormat[m],
+									mode_lib->vba.WritebackHRatio[m],
+									mode_lib->vba.WritebackVRatio[m],
+									mode_lib->vba.WritebackVTaps[m],
+									mode_lib->vba.WritebackDestinationWidth[m],
+									mode_lib->vba.WritebackDestinationHeight[m],
+									mode_lib->vba.WritebackSourceHeight[m],
+									mode_lib->vba.HTotal[m]) /
+									mode_lib->vba.RequiredDISPCLK[i][j]);
+						}
+					}
+				}
+			}
+			for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+				for (m = 0; m <= mode_lib->vba.NumberOfActiveSurfaces - 1; m++) {
+					if (mode_lib->vba.BlendingAndTiming[k] == m) {
+						mode_lib->vba.WritebackDelayTime[k] =
+								mode_lib->vba.WritebackDelayTime[m];
+					}
+				}
+			}
+			mode_lib->vba.MaxMaxVStartup[i][j] = 0;
+			for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+				mode_lib->vba.MaximumVStartup[i][j][k] = ((mode_lib->vba.Interlace[k] &&
+								!mode_lib->vba.ProgressiveToInterlaceUnitInOPP) ?
+								dml_floor((mode_lib->vba.VTotal[k] -
+									mode_lib->vba.VActive[k]) / 2.0, 1.0) :
+								mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k])
+								- dml_max(1.0, dml_ceil(1.0 *
+									mode_lib->vba.WritebackDelayTime[k] /
+									(mode_lib->vba.HTotal[k] /
+									mode_lib->vba.PixelClock[k]), 1.0));
+
+				// Clamp to max OTG vstartup register limit
+				if (mode_lib->vba.MaximumVStartup[i][j][k] > 1023)
+					mode_lib->vba.MaximumVStartup[i][j][k] = 1023;
+
+				mode_lib->vba.MaxMaxVStartup[i][j] = dml_max(mode_lib->vba.MaxMaxVStartup[i][j],
+						mode_lib->vba.MaximumVStartup[i][j][k]);
+			}
+		}
+	}
+
+	ReorderingBytes = mode_lib->vba.NumberOfChannels
+			* dml_max3(mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly,
+					mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData,
+					mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly);
+
+	dml32_CalculateMinAndMaxPrefetchMode(mode_lib->vba.AllowForPStateChangeOrStutterInVBlankFinal,
+			&mode_lib->vba.MinPrefetchMode,
+			&mode_lib->vba.MaxPrefetchMode);
+
+	for (i = 0; i < (int) v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j)
+			mode_lib->vba.DCFCLKState[i][j] = mode_lib->vba.DCFCLKPerState[i];
+	}
+
+	/* Immediate Flip and MALL parameters */
+	mode_lib->vba.ImmediateFlipRequiredFinal = false;
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		mode_lib->vba.ImmediateFlipRequiredFinal = mode_lib->vba.ImmediateFlipRequiredFinal
+				|| (mode_lib->vba.ImmediateFlipRequirement[k] == dm_immediate_flip_required);
+	}
+
+	mode_lib->vba.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified = false;
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		mode_lib->vba.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified =
+				mode_lib->vba.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified
+						|| ((mode_lib->vba.ImmediateFlipRequirement[k]
+								!= dm_immediate_flip_required)
+								&& (mode_lib->vba.ImmediateFlipRequirement[k]
+										!= dm_immediate_flip_not_required));
+	}
+	mode_lib->vba.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified =
+			mode_lib->vba.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified
+					&& mode_lib->vba.ImmediateFlipRequiredFinal;
+
+	mode_lib->vba.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = false;
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		mode_lib->vba.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe =
+			mode_lib->vba.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe ||
+			((mode_lib->vba.HostVMEnable == true || mode_lib->vba.ImmediateFlipRequirement[k] !=
+					dm_immediate_flip_not_required) &&
+			(mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame ||
+			mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe));
+	}
+
+	mode_lib->vba.InvalidCombinationOfMALLUseForPStateAndStaticScreen = false;
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		mode_lib->vba.InvalidCombinationOfMALLUseForPStateAndStaticScreen =
+			mode_lib->vba.InvalidCombinationOfMALLUseForPStateAndStaticScreen
+			|| ((mode_lib->vba.UseMALLForStaticScreen[k] == dm_use_mall_static_screen_enable
+			|| mode_lib->vba.UseMALLForStaticScreen[k] == dm_use_mall_static_screen_optimize)
+			&& (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe))
+			|| ((mode_lib->vba.UseMALLForStaticScreen[k] == dm_use_mall_static_screen_disable
+			|| mode_lib->vba.UseMALLForStaticScreen[k] == dm_use_mall_static_screen_optimize)
+			&& (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame));
+	}
+
+	FullFrameMALLPStateMethod = false;
+	SubViewportMALLPStateMethod = false;
+	PhantomPipeMALLPStateMethod = false;
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		if (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame)
+			FullFrameMALLPStateMethod = true;
+		if (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport)
+			SubViewportMALLPStateMethod = true;
+		if (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe)
+			PhantomPipeMALLPStateMethod = true;
+	}
+	mode_lib->vba.InvalidCombinationOfMALLUseForPState = (SubViewportMALLPStateMethod
+			!= PhantomPipeMALLPStateMethod) || (SubViewportMALLPStateMethod && FullFrameMALLPStateMethod);
+
+	if (mode_lib->vba.UseMinimumRequiredDCFCLK == true) {
+		dml32_UseMinimumDCFCLK(
+				mode_lib->vba.UsesMALLForPStateChange,
+				mode_lib->vba.DRRDisplay,
+				mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+				mode_lib->vba.MaxInterDCNTileRepeaters,
+				mode_lib->vba.MaxPrefetchMode,
+				mode_lib->vba.DRAMClockChangeLatency,
+				mode_lib->vba.FCLKChangeLatency,
+				mode_lib->vba.SREnterPlusExitTime,
+				mode_lib->vba.ReturnBusWidth,
+				mode_lib->vba.RoundTripPingLatencyCycles,
+				ReorderingBytes,
+				mode_lib->vba.PixelChunkSizeInKByte,
+				mode_lib->vba.MetaChunkSize,
+				mode_lib->vba.GPUVMEnable,
+				mode_lib->vba.GPUVMMaxPageTableLevels,
+				mode_lib->vba.HostVMEnable,
+				mode_lib->vba.NumberOfActiveSurfaces,
+				mode_lib->vba.HostVMMinPageSize,
+				mode_lib->vba.HostVMMaxNonCachedPageTableLevels,
+				mode_lib->vba.DynamicMetadataVMEnabled,
+				mode_lib->vba.ImmediateFlipRequiredFinal,
+				mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
+				mode_lib->vba.MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation,
+				mode_lib->vba.PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency,
+				mode_lib->vba.VTotal,
+				mode_lib->vba.VActive,
+				mode_lib->vba.DynamicMetadataTransmittedBytes,
+				mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired,
+				mode_lib->vba.Interlace,
+				mode_lib->vba.RequiredDPPCLK,
+				mode_lib->vba.RequiredDISPCLK,
+				mode_lib->vba.UrgLatency,
+				mode_lib->vba.NoOfDPP,
+				mode_lib->vba.ProjectedDCFCLKDeepSleep,
+				mode_lib->vba.MaximumVStartup,
+				mode_lib->vba.TotalNumberOfActiveDPP,
+				mode_lib->vba.TotalNumberOfDCCActiveDPP,
+				mode_lib->vba.dpte_group_bytes,
+				mode_lib->vba.PrefetchLinesY,
+				mode_lib->vba.PrefetchLinesC,
+				mode_lib->vba.swath_width_luma_ub_all_states,
+				mode_lib->vba.swath_width_chroma_ub_all_states,
+				mode_lib->vba.BytePerPixelY,
+				mode_lib->vba.BytePerPixelC,
+				mode_lib->vba.HTotal,
+				mode_lib->vba.PixelClock,
+				mode_lib->vba.PDEAndMetaPTEBytesPerFrame,
+				mode_lib->vba.DPTEBytesPerRow,
+				mode_lib->vba.MetaRowBytes,
+				mode_lib->vba.DynamicMetadataEnable,
+				mode_lib->vba.ReadBandwidthLuma,
+				mode_lib->vba.ReadBandwidthChroma,
+				mode_lib->vba.DCFCLKPerState,
+
+				/* Output */
+				mode_lib->vba.DCFCLKState);
+	} // UseMinimumRequiredDCFCLK == true
+
+	for (i = 0; i < (int) v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			mode_lib->vba.ReturnBWPerState[i][j] = dml32_get_return_bw_mbps(&mode_lib->vba.soc, i,
+					mode_lib->vba.HostVMEnable, mode_lib->vba.DCFCLKState[i][j],
+					mode_lib->vba.FabricClockPerState[i], mode_lib->vba.DRAMSpeedPerState[i]);
+		}
+	}
+
+	//Re-ordering Buffer Support Check
+	for (i = 0; i < (int) v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			if ((mode_lib->vba.ROBBufferSizeInKByte - mode_lib->vba.PixelChunkSizeInKByte) * 1024
+					/ mode_lib->vba.ReturnBWPerState[i][j]
+					> (mode_lib->vba.RoundTripPingLatencyCycles + 32)
+							/ mode_lib->vba.DCFCLKState[i][j]
+							+ ReorderingBytes / mode_lib->vba.ReturnBWPerState[i][j]) {
+				mode_lib->vba.ROBSupport[i][j] = true;
+			} else {
+				mode_lib->vba.ROBSupport[i][j] = false;
+			}
+		}
+	}
+
+	//Vertical Active BW support check
+	MaxTotalVActiveRDBandwidth = 0;
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + mode_lib->vba.ReadBandwidthLuma[k]
+				+ mode_lib->vba.ReadBandwidthChroma[k];
+	}
+
+	for (i = 0; i < (int) v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			mode_lib->vba.MaxTotalVerticalActiveAvailableBandwidth[i][j] =
+				dml_min3(mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLKState[i][j]
+					* mode_lib->vba.MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation / 100,
+					mode_lib->vba.FabricClockPerState[i]
+					* mode_lib->vba.FabricDatapathToDCNDataReturn
+					* mode_lib->vba.MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation / 100,
+					mode_lib->vba.DRAMSpeedPerState[i]
+					* mode_lib->vba.NumberOfChannels
+					* mode_lib->vba.DRAMChannelWidth
+					* (i < 2 ? mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE : mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation) / 100);
+
+			if (MaxTotalVActiveRDBandwidth
+					<= mode_lib->vba.MaxTotalVerticalActiveAvailableBandwidth[i][j]) {
+				mode_lib->vba.TotalVerticalActiveBandwidthSupport[i][j] = true;
+			} else {
+				mode_lib->vba.TotalVerticalActiveBandwidthSupport[i][j] = false;
+			}
+		}
+	}
+
+	/* Prefetch Check */
+
+	for (i = 0; i < (int) v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			double VMDataOnlyReturnBWPerState;
+			double HostVMInefficiencyFactor;
+			unsigned int NextPrefetchModeState;
+
+			mode_lib->vba.TimeCalc = 24 / mode_lib->vba.ProjectedDCFCLKDeepSleep[i][j];
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k];
+				mode_lib->vba.swath_width_luma_ub_this_state[k] =
+						mode_lib->vba.swath_width_luma_ub_all_states[i][j][k];
+				mode_lib->vba.swath_width_chroma_ub_this_state[k] =
+						mode_lib->vba.swath_width_chroma_ub_all_states[i][j][k];
+				mode_lib->vba.SwathWidthYThisState[k] = mode_lib->vba.SwathWidthYAllStates[i][j][k];
+				mode_lib->vba.SwathWidthCThisState[k] = mode_lib->vba.SwathWidthCAllStates[i][j][k];
+				mode_lib->vba.SwathHeightYThisState[k] = mode_lib->vba.SwathHeightYAllStates[i][j][k];
+				mode_lib->vba.SwathHeightCThisState[k] = mode_lib->vba.SwathHeightCAllStates[i][j][k];
+				mode_lib->vba.UnboundedRequestEnabledThisState =
+						mode_lib->vba.UnboundedRequestEnabledAllStates[i][j];
+				mode_lib->vba.CompressedBufferSizeInkByteThisState =
+						mode_lib->vba.CompressedBufferSizeInkByteAllStates[i][j];
+				mode_lib->vba.DETBufferSizeInKByteThisState[k] =
+						mode_lib->vba.DETBufferSizeInKByteAllStates[i][j][k];
+				mode_lib->vba.DETBufferSizeYThisState[k] =
+						mode_lib->vba.DETBufferSizeYAllStates[i][j][k];
+				mode_lib->vba.DETBufferSizeCThisState[k] =
+						mode_lib->vba.DETBufferSizeCAllStates[i][j][k];
+			}
+
+			mode_lib->vba.VActiveBandwithSupport[i][j] = dml32_CalculateVActiveBandwithSupport(
+					mode_lib->vba.NumberOfActiveSurfaces,
+					mode_lib->vba.ReturnBWPerState[i][j],
+					mode_lib->vba.NoUrgentLatencyHiding,
+					mode_lib->vba.ReadBandwidthLuma,
+					mode_lib->vba.ReadBandwidthChroma,
+					mode_lib->vba.cursor_bw,
+					mode_lib->vba.meta_row_bandwidth_this_state,
+					mode_lib->vba.dpte_row_bandwidth_this_state,
+					mode_lib->vba.NoOfDPPThisState,
+					mode_lib->vba.UrgentBurstFactorLuma,
+					mode_lib->vba.UrgentBurstFactorChroma,
+					mode_lib->vba.UrgentBurstFactorCursor);
+
+			VMDataOnlyReturnBWPerState = dml32_get_return_bw_mbps_vm_only(&mode_lib->vba.soc, i,
+					mode_lib->vba.DCFCLKState[i][j], mode_lib->vba.FabricClockPerState[i],
+					mode_lib->vba.DRAMSpeedPerState[i]);
+			HostVMInefficiencyFactor = 1;
+
+			if (mode_lib->vba.GPUVMEnable && mode_lib->vba.HostVMEnable)
+				HostVMInefficiencyFactor = mode_lib->vba.ReturnBWPerState[i][j]
+						/ VMDataOnlyReturnBWPerState;
+
+			mode_lib->vba.ExtraLatency = dml32_CalculateExtraLatency(
+					mode_lib->vba.RoundTripPingLatencyCycles, ReorderingBytes,
+					mode_lib->vba.DCFCLKState[i][j], mode_lib->vba.TotalNumberOfActiveDPP[i][j],
+					mode_lib->vba.PixelChunkSizeInKByte,
+					mode_lib->vba.TotalNumberOfDCCActiveDPP[i][j], mode_lib->vba.MetaChunkSize,
+					mode_lib->vba.ReturnBWPerState[i][j], mode_lib->vba.GPUVMEnable,
+					mode_lib->vba.HostVMEnable, mode_lib->vba.NumberOfActiveSurfaces,
+					mode_lib->vba.NoOfDPPThisState, mode_lib->vba.dpte_group_bytes,
+					HostVMInefficiencyFactor, mode_lib->vba.HostVMMinPageSize,
+					mode_lib->vba.HostVMMaxNonCachedPageTableLevels);
+
+			NextPrefetchModeState = mode_lib->vba.MinPrefetchMode;
+
+			mode_lib->vba.NextMaxVStartup = mode_lib->vba.MaxMaxVStartup[i][j];
+
+			do {
+				mode_lib->vba.PrefetchModePerState[i][j] = NextPrefetchModeState;
+				mode_lib->vba.MaxVStartup = mode_lib->vba.NextMaxVStartup;
+
+				for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+					DmlPipe myPipe;
+					unsigned int dummy_integer;
+
+					mode_lib->vba.TWait = dml32_CalculateTWait(
+							mode_lib->vba.PrefetchModePerState[i][j],
+							mode_lib->vba.UsesMALLForPStateChange[k],
+							mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+							mode_lib->vba.DRRDisplay[k],
+							mode_lib->vba.DRAMClockChangeLatency,
+							mode_lib->vba.FCLKChangeLatency, mode_lib->vba.UrgLatency[i],
+							mode_lib->vba.SREnterPlusExitTime);
+
+					myPipe.Dppclk = mode_lib->vba.RequiredDPPCLK[i][j][k];
+					myPipe.Dispclk = mode_lib->vba.RequiredDISPCLK[i][j];
+					myPipe.PixelClock = mode_lib->vba.PixelClock[k];
+					myPipe.DCFClkDeepSleep = mode_lib->vba.ProjectedDCFCLKDeepSleep[i][j];
+					myPipe.DPPPerSurface = mode_lib->vba.NoOfDPP[i][j][k];
+					myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k];
+					myPipe.SourceRotation = mode_lib->vba.SourceRotation[k];
+					myPipe.BlockWidth256BytesY = mode_lib->vba.Read256BlockWidthY[k];
+					myPipe.BlockHeight256BytesY = mode_lib->vba.Read256BlockHeightY[k];
+					myPipe.BlockWidth256BytesC = mode_lib->vba.Read256BlockWidthC[k];
+					myPipe.BlockHeight256BytesC = mode_lib->vba.Read256BlockHeightC[k];
+					myPipe.InterlaceEnable = mode_lib->vba.Interlace[k];
+					myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k];
+					myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k];
+					myPipe.HTotal = mode_lib->vba.HTotal[k];
+					myPipe.HActive = mode_lib->vba.HActive[k];
+					myPipe.DCCEnable = mode_lib->vba.DCCEnable[k];
+					myPipe.ODMMode = mode_lib->vba.ODMCombineEnablePerState[i][k];
+					myPipe.SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k];
+					myPipe.BytePerPixelY = mode_lib->vba.BytePerPixelY[k];
+					myPipe.BytePerPixelC = mode_lib->vba.BytePerPixelC[k];
+					myPipe.ProgressiveToInterlaceUnitInOPP =
+							mode_lib->vba.ProgressiveToInterlaceUnitInOPP;
+
+					mode_lib->vba.NoTimeForPrefetch[i][j][k] =
+						dml32_CalculatePrefetchSchedule(
+							HostVMInefficiencyFactor,
+							&myPipe,
+							mode_lib->vba.DSCDelayPerState[i][k],
+							mode_lib->vba.DPPCLKDelaySubtotal +
+								mode_lib->vba.DPPCLKDelayCNVCFormater,
+							mode_lib->vba.DPPCLKDelaySCL,
+							mode_lib->vba.DPPCLKDelaySCLLBOnly,
+							mode_lib->vba.DPPCLKDelayCNVCCursor,
+							mode_lib->vba.DISPCLKDelaySubtotal,
+							mode_lib->vba.SwathWidthYThisState[k] /
+								mode_lib->vba.HRatio[k],
+							mode_lib->vba.OutputFormat[k],
+							mode_lib->vba.MaxInterDCNTileRepeaters,
+							dml_min(mode_lib->vba.MaxVStartup,
+									mode_lib->vba.MaximumVStartup[i][j][k]),
+							mode_lib->vba.MaximumVStartup[i][j][k],
+							mode_lib->vba.GPUVMMaxPageTableLevels,
+							mode_lib->vba.GPUVMEnable, mode_lib->vba.HostVMEnable,
+							mode_lib->vba.HostVMMaxNonCachedPageTableLevels,
+							mode_lib->vba.HostVMMinPageSize,
+							mode_lib->vba.DynamicMetadataEnable[k],
+							mode_lib->vba.DynamicMetadataVMEnabled,
+							mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
+							mode_lib->vba.DynamicMetadataTransmittedBytes[k],
+							mode_lib->vba.UrgLatency[i],
+							mode_lib->vba.ExtraLatency,
+							mode_lib->vba.TimeCalc,
+							mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k],
+							mode_lib->vba.MetaRowBytes[i][j][k],
+							mode_lib->vba.DPTEBytesPerRow[i][j][k],
+							mode_lib->vba.PrefetchLinesY[i][j][k],
+							mode_lib->vba.SwathWidthYThisState[k],
+							mode_lib->vba.PrefillY[k],
+							mode_lib->vba.MaxNumSwY[k],
+							mode_lib->vba.PrefetchLinesC[i][j][k],
+							mode_lib->vba.SwathWidthCThisState[k],
+							mode_lib->vba.PrefillC[k],
+							mode_lib->vba.MaxNumSwC[k],
+							mode_lib->vba.swath_width_luma_ub_this_state[k],
+							mode_lib->vba.swath_width_chroma_ub_this_state[k],
+							mode_lib->vba.SwathHeightYThisState[k],
+							mode_lib->vba.SwathHeightCThisState[k], mode_lib->vba.TWait,
+
+							/* Output */
+							&DSTXAfterScaler[k],
+							&DSTYAfterScaler[k],
+							&mode_lib->vba.LineTimesForPrefetch[k],
+							&mode_lib->vba.PrefetchBW[k],
+							&mode_lib->vba.LinesForMetaPTE[k],
+							&mode_lib->vba.LinesForMetaAndDPTERow[k],
+							&mode_lib->vba.VRatioPreY[i][j][k],
+							&mode_lib->vba.VRatioPreC[i][j][k],
+							&mode_lib->vba.RequiredPrefetchPixelDataBWLuma[0][0][k],
+							&mode_lib->vba.RequiredPrefetchPixelDataBWChroma[0][0][k],
+							&mode_lib->vba.NoTimeForDynamicMetadata[i][j][k],
+							&mode_lib->vba.Tno_bw[k],
+							&mode_lib->vba.prefetch_vmrow_bw[k],
+							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[0],         // double *Tdmdl_vm
+							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[1],         // double *Tdmdl
+							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[2],         // double *TSetup
+							&dummy_integer,         							    // unsigned int   *VUpdateOffsetPix
+							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[3],         // unsigned int   *VUpdateWidthPix
+							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[4]);        // unsigned int   *VReadyOffsetPix
+				}
+
+				for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+					dml32_CalculateUrgentBurstFactor(
+							mode_lib->vba.UsesMALLForPStateChange[k],
+							mode_lib->vba.swath_width_luma_ub_this_state[k],
+							mode_lib->vba.swath_width_chroma_ub_this_state[k],
+							mode_lib->vba.SwathHeightYThisState[k],
+							mode_lib->vba.SwathHeightCThisState[k],
+							mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
+							mode_lib->vba.UrgLatency[i], mode_lib->vba.CursorBufferSize,
+							mode_lib->vba.CursorWidth[k][0], mode_lib->vba.CursorBPP[k][0],
+							mode_lib->vba.VRatioPreY[i][j][k],
+							mode_lib->vba.VRatioPreC[i][j][k],
+							mode_lib->vba.BytePerPixelInDETY[k],
+							mode_lib->vba.BytePerPixelInDETC[k],
+							mode_lib->vba.DETBufferSizeYThisState[k],
+							mode_lib->vba.DETBufferSizeCThisState[k],
+							/* Output */
+							&mode_lib->vba.UrgentBurstFactorCursorPre[k],
+							&mode_lib->vba.UrgentBurstFactorLumaPre[k],
+							&mode_lib->vba.UrgentBurstFactorChroma[k],
+							&mode_lib->vba.NotUrgentLatencyHidingPre[k]);
+				}
+
+				{
+					double dummy_single[2];
+					dml32_CalculatePrefetchBandwithSupport(
+							mode_lib->vba.NumberOfActiveSurfaces,
+							mode_lib->vba.ReturnBWPerState[i][j],
+							mode_lib->vba.NotUrgentLatencyHidingPre,
+							mode_lib->vba.ReadBandwidthLuma,
+							mode_lib->vba.ReadBandwidthChroma,
+							mode_lib->vba.RequiredPrefetchPixelDataBWLuma[0][0],
+							mode_lib->vba.RequiredPrefetchPixelDataBWChroma[0][0],
+							mode_lib->vba.cursor_bw,
+							mode_lib->vba.meta_row_bandwidth_this_state,
+							mode_lib->vba.dpte_row_bandwidth_this_state,
+							mode_lib->vba.cursor_bw_pre,
+							mode_lib->vba.prefetch_vmrow_bw,
+							mode_lib->vba.NoOfDPPThisState,
+							mode_lib->vba.UrgentBurstFactorLuma,
+							mode_lib->vba.UrgentBurstFactorChroma,
+							mode_lib->vba.UrgentBurstFactorCursor,
+							mode_lib->vba.UrgentBurstFactorLumaPre,
+							mode_lib->vba.UrgentBurstFactorChromaPre,
+							mode_lib->vba.UrgentBurstFactorCursorPre,
+
+							/* output */
+							&dummy_single[0],   // Single  *PrefetchBandwidth
+							&dummy_single[1],   // Single  *FractionOfUrgentBandwidth
+							&mode_lib->vba.PrefetchSupported[i][j]);
+				}
+
+				for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+					if (mode_lib->vba.LineTimesForPrefetch[k]
+							< 2.0 || mode_lib->vba.LinesForMetaPTE[k] >= 32.0
+							|| mode_lib->vba.LinesForMetaAndDPTERow[k] >= 16.0
+							|| mode_lib->vba.NoTimeForPrefetch[i][j][k] == true) {
+						mode_lib->vba.PrefetchSupported[i][j] = false;
+					}
+				}
+
+				mode_lib->vba.DynamicMetadataSupported[i][j] = true;
+				for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+					if (mode_lib->vba.NoTimeForDynamicMetadata[i][j][k] == true)
+						mode_lib->vba.DynamicMetadataSupported[i][j] = false;
+				}
+
+				mode_lib->vba.VRatioInPrefetchSupported[i][j] = true;
+				for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+					if (mode_lib->vba.VRatioPreY[i][j][k] > __DML_MAX_VRATIO_PRE__
+							|| mode_lib->vba.VRatioPreC[i][j][k] > __DML_MAX_VRATIO_PRE__
+							|| mode_lib->vba.NoTimeForPrefetch[i][j][k] == true) {
+						mode_lib->vba.VRatioInPrefetchSupported[i][j] = false;
+					}
+				}
+				mode_lib->vba.AnyLinesForVMOrRowTooLarge = false;
+				for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+					if (mode_lib->vba.LinesForMetaAndDPTERow[k] >= 16
+							|| mode_lib->vba.LinesForMetaPTE[k] >= 32) {
+						mode_lib->vba.AnyLinesForVMOrRowTooLarge = true;
+					}
+				}
+
+				if (mode_lib->vba.PrefetchSupported[i][j] == true
+						&& mode_lib->vba.VRatioInPrefetchSupported[i][j] == true) {
+					mode_lib->vba.BandwidthAvailableForImmediateFlip =
+							dml32_CalculateBandwidthAvailableForImmediateFlip(
+							mode_lib->vba.NumberOfActiveSurfaces,
+							mode_lib->vba.ReturnBWPerState[i][j],
+							mode_lib->vba.ReadBandwidthLuma,
+							mode_lib->vba.ReadBandwidthChroma,
+							mode_lib->vba.RequiredPrefetchPixelDataBWLuma[0][0],
+							mode_lib->vba.RequiredPrefetchPixelDataBWChroma[0][0],
+							mode_lib->vba.cursor_bw,
+							mode_lib->vba.cursor_bw_pre,
+							mode_lib->vba.NoOfDPPThisState,
+							mode_lib->vba.UrgentBurstFactorLuma,
+							mode_lib->vba.UrgentBurstFactorChroma,
+							mode_lib->vba.UrgentBurstFactorCursor,
+							mode_lib->vba.UrgentBurstFactorLumaPre,
+							mode_lib->vba.UrgentBurstFactorChromaPre,
+							mode_lib->vba.UrgentBurstFactorCursorPre);
+
+					mode_lib->vba.TotImmediateFlipBytes = 0.0;
+					for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+						if (!(mode_lib->vba.ImmediateFlipRequirement[k] ==
+								dm_immediate_flip_not_required)) {
+							mode_lib->vba.TotImmediateFlipBytes =
+									mode_lib->vba.TotImmediateFlipBytes
+								+ mode_lib->vba.NoOfDPP[i][j][k]
+								* mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k]
+								+ mode_lib->vba.MetaRowBytes[i][j][k];
+							if (mode_lib->vba.use_one_row_for_frame_flip[i][j][k]) {
+								mode_lib->vba.TotImmediateFlipBytes =
+									mode_lib->vba.TotImmediateFlipBytes + 2
+								* mode_lib->vba.DPTEBytesPerRow[i][j][k];
+							} else {
+								mode_lib->vba.TotImmediateFlipBytes =
+									mode_lib->vba.TotImmediateFlipBytes
+								+ mode_lib->vba.DPTEBytesPerRow[i][j][k];
+							}
+						}
+					}
+
+					for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+						dml32_CalculateFlipSchedule(HostVMInefficiencyFactor,
+							mode_lib->vba.ExtraLatency,
+							mode_lib->vba.UrgLatency[i],
+							mode_lib->vba.GPUVMMaxPageTableLevels,
+							mode_lib->vba.HostVMEnable,
+							mode_lib->vba.HostVMMaxNonCachedPageTableLevels,
+							mode_lib->vba.GPUVMEnable,
+							mode_lib->vba.HostVMMinPageSize,
+							mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k],
+							mode_lib->vba.MetaRowBytes[i][j][k],
+							mode_lib->vba.DPTEBytesPerRow[i][j][k],
+							mode_lib->vba.BandwidthAvailableForImmediateFlip,
+							mode_lib->vba.TotImmediateFlipBytes,
+							mode_lib->vba.SourcePixelFormat[k],
+							(mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]),
+							mode_lib->vba.VRatio[k],
+							mode_lib->vba.VRatioChroma[k],
+							mode_lib->vba.Tno_bw[k],
+								mode_lib->vba.DCCEnable[k],
+							mode_lib->vba.dpte_row_height[k],
+							mode_lib->vba.meta_row_height[k],
+							mode_lib->vba.dpte_row_height_chroma[k],
+							mode_lib->vba.meta_row_height_chroma[k],
+							mode_lib->vba.use_one_row_for_frame_flip[i][j][k], // 24
+
+							/* Output */
+							&mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k],
+							&mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k],
+							&mode_lib->vba.final_flip_bw[k],
+							&mode_lib->vba.ImmediateFlipSupportedForPipe[k]);
+					}
+
+					{
+						double dummy_single[2];
+						dml32_CalculateImmediateFlipBandwithSupport(mode_lib->vba.NumberOfActiveSurfaces,
+								mode_lib->vba.ReturnBWPerState[i][j],
+								mode_lib->vba.ImmediateFlipRequirement,
+								mode_lib->vba.final_flip_bw,
+								mode_lib->vba.ReadBandwidthLuma,
+								mode_lib->vba.ReadBandwidthChroma,
+								mode_lib->vba.RequiredPrefetchPixelDataBWLuma[0][0],
+								mode_lib->vba.RequiredPrefetchPixelDataBWChroma[0][0],
+								mode_lib->vba.cursor_bw,
+								mode_lib->vba.meta_row_bandwidth_this_state,
+								mode_lib->vba.dpte_row_bandwidth_this_state,
+								mode_lib->vba.cursor_bw_pre,
+								mode_lib->vba.prefetch_vmrow_bw,
+								mode_lib->vba.DPPPerPlane,
+								mode_lib->vba.UrgentBurstFactorLuma,
+								mode_lib->vba.UrgentBurstFactorChroma,
+								mode_lib->vba.UrgentBurstFactorCursor,
+								mode_lib->vba.UrgentBurstFactorLumaPre,
+								mode_lib->vba.UrgentBurstFactorChromaPre,
+								mode_lib->vba.UrgentBurstFactorCursorPre,
+
+								/* output */
+								&dummy_single[0], //  Single  *TotalBandwidth
+								&dummy_single[1], //  Single  *FractionOfUrgentBandwidth
+								&mode_lib->vba.ImmediateFlipSupportedForState[i][j]); // Boolean *ImmediateFlipBandwidthSupport
+					}
+
+					for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+						if (!(mode_lib->vba.ImmediateFlipRequirement[k]
+								== dm_immediate_flip_not_required)
+								&& (mode_lib->vba.ImmediateFlipSupportedForPipe[k]
+										== false))
+							mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false;
+					}
+				} else { // if prefetch not support, assume iflip not supported
+					mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false;
+				}
+
+				if (mode_lib->vba.MaxVStartup <= __DML_VBA_MIN_VSTARTUP__
+						|| mode_lib->vba.AnyLinesForVMOrRowTooLarge == false) {
+					mode_lib->vba.NextMaxVStartup = mode_lib->vba.MaxMaxVStartup[i][j];
+					NextPrefetchModeState = NextPrefetchModeState + 1;
+				} else {
+					mode_lib->vba.NextMaxVStartup = mode_lib->vba.NextMaxVStartup - 1;
+				}
+			} while (!((mode_lib->vba.PrefetchSupported[i][j] == true
+					&& mode_lib->vba.DynamicMetadataSupported[i][j] == true
+					&& mode_lib->vba.VRatioInPrefetchSupported[i][j] == true &&
+					// consider flip support is okay if when there is no hostvm and the
+					// user does't require a iflip OR the flip bw is ok
+					// If there is hostvm, DCN needs to support iflip for invalidation
+					((mode_lib->vba.HostVMEnable == false
+							&& !mode_lib->vba.ImmediateFlipRequiredFinal)
+							|| mode_lib->vba.ImmediateFlipSupportedForState[i][j] == true))
+					|| (mode_lib->vba.NextMaxVStartup == mode_lib->vba.MaxMaxVStartup[i][j]
+							&& NextPrefetchModeState > mode_lib->vba.MaxPrefetchMode)));
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				mode_lib->vba.use_one_row_for_frame_this_state[k] =
+						mode_lib->vba.use_one_row_for_frame[i][j][k];
+			}
+
+
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.UrgentLatency = mode_lib->vba.UrgLatency[i];
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.ExtraLatency = mode_lib->vba.ExtraLatency;
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.WritebackLatency = mode_lib->vba.WritebackLatency;
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.DRAMClockChangeLatency = mode_lib->vba.DRAMClockChangeLatency;
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.FCLKChangeLatency = mode_lib->vba.FCLKChangeLatency;
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SRExitTime = mode_lib->vba.SRExitTime;
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SREnterPlusExitTime = mode_lib->vba.SREnterPlusExitTime;
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SRExitZ8Time = mode_lib->vba.SRExitZ8Time;
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SREnterPlusExitZ8Time = mode_lib->vba.SREnterPlusExitZ8Time;
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.USRRetrainingLatency = mode_lib->vba.USRRetrainingLatency;
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SMNLatency = mode_lib->vba.SMNLatency;
+
+			{
+				unsigned int dummy_integer[4];
+				dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
+						mode_lib->vba.USRRetrainingRequiredFinal,
+						mode_lib->vba.UsesMALLForPStateChange,
+						mode_lib->vba.PrefetchModePerState[i][j],
+						mode_lib->vba.NumberOfActiveSurfaces,
+						mode_lib->vba.MaxLineBufferLines,
+						mode_lib->vba.LineBufferSizeFinal,
+						mode_lib->vba.WritebackInterfaceBufferSize,
+						mode_lib->vba.DCFCLKState[i][j],
+						mode_lib->vba.ReturnBWPerState[i][j],
+						mode_lib->vba.SynchronizeTimingsFinal,
+						mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+						mode_lib->vba.DRRDisplay,
+						mode_lib->vba.dpte_group_bytes,
+						mode_lib->vba.meta_row_height,
+						mode_lib->vba.meta_row_height_chroma,
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters,
+						mode_lib->vba.WritebackChunkSize,
+						mode_lib->vba.SOCCLKPerState[i],
+						mode_lib->vba.ProjectedDCFCLKDeepSleep[i][j],
+						mode_lib->vba.DETBufferSizeYThisState,
+						mode_lib->vba.DETBufferSizeCThisState,
+						mode_lib->vba.SwathHeightYThisState,
+						mode_lib->vba.SwathHeightCThisState,
+						mode_lib->vba.LBBitPerPixel,
+						mode_lib->vba.SwathWidthYThisState, // 24
+						mode_lib->vba.SwathWidthCThisState,
+						mode_lib->vba.HRatio,
+						mode_lib->vba.HRatioChroma,
+						mode_lib->vba.vtaps,
+						mode_lib->vba.VTAPsChroma,
+						mode_lib->vba.VRatio,
+						mode_lib->vba.VRatioChroma,
+						mode_lib->vba.HTotal,
+						mode_lib->vba.VTotal,
+						mode_lib->vba.VActive,
+						mode_lib->vba.PixelClock,
+						mode_lib->vba.BlendingAndTiming,
+						mode_lib->vba.NoOfDPPThisState,
+						mode_lib->vba.BytePerPixelInDETY,
+						mode_lib->vba.BytePerPixelInDETC,
+						DSTXAfterScaler,
+						DSTYAfterScaler,
+						mode_lib->vba.WritebackEnable,
+						mode_lib->vba.WritebackPixelFormat,
+						mode_lib->vba.WritebackDestinationWidth,
+						mode_lib->vba.WritebackDestinationHeight,
+						mode_lib->vba.WritebackSourceHeight,
+						mode_lib->vba.UnboundedRequestEnabledThisState,
+						mode_lib->vba.CompressedBufferSizeInkByteThisState,
+
+						/* Output */
+						&mode_lib->vba.Watermark, // Store the values in vba
+						&mode_lib->vba.DRAMClockChangeSupport[i][j],
+						&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single2[0], // double *MaxActiveDRAMClockChangeLatencySupported
+						&dummy_integer[0], // Long SubViewportLinesNeededInMALL[]
+						&mode_lib->vba.FCLKChangeSupport[i][j],
+						&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single2[1], // double *MinActiveFCLKChangeLatencySupported
+						&mode_lib->vba.USRRetrainingSupport[i][j],
+						mode_lib->vba.ActiveDRAMClockChangeLatencyMargin);
+			}
+		}
+	} // End of Prefetch Check
+
+	/*Cursor Support Check*/
+	mode_lib->vba.CursorSupport = true;
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (mode_lib->vba.CursorWidth[k][0] > 0.0) {
+			if (mode_lib->vba.CursorBPP[k][0] == 64 && mode_lib->vba.Cursor64BppSupport == false)
+				mode_lib->vba.CursorSupport = false;
+		}
+	}
+
+	/*Valid Pitch Check*/
+	mode_lib->vba.PitchSupport = true;
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		mode_lib->vba.AlignedYPitch[k] = dml_ceil(
+				dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.SurfaceWidthY[k]),
+				mode_lib->vba.MacroTileWidthY[k]);
+		if (mode_lib->vba.DCCEnable[k] == true) {
+			mode_lib->vba.AlignedDCCMetaPitchY[k] = dml_ceil(
+					dml_max(mode_lib->vba.DCCMetaPitchY[k], mode_lib->vba.SurfaceWidthY[k]),
+					64.0 * mode_lib->vba.Read256BlockWidthY[k]);
+		} else {
+			mode_lib->vba.AlignedDCCMetaPitchY[k] = mode_lib->vba.DCCMetaPitchY[k];
+		}
+		if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64 && mode_lib->vba.SourcePixelFormat[k] != dm_444_32
+				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
+				&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
+				&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe
+				&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) {
+			mode_lib->vba.AlignedCPitch[k] = dml_ceil(
+					dml_max(mode_lib->vba.PitchC[k], mode_lib->vba.SurfaceWidthC[k]),
+					mode_lib->vba.MacroTileWidthC[k]);
+			if (mode_lib->vba.DCCEnable[k] == true) {
+				mode_lib->vba.AlignedDCCMetaPitchC[k] = dml_ceil(
+						dml_max(mode_lib->vba.DCCMetaPitchC[k],
+								mode_lib->vba.SurfaceWidthC[k]),
+						64.0 * mode_lib->vba.Read256BlockWidthC[k]);
+			} else {
+				mode_lib->vba.AlignedDCCMetaPitchC[k] = mode_lib->vba.DCCMetaPitchC[k];
+			}
+		} else {
+			mode_lib->vba.AlignedCPitch[k] = mode_lib->vba.PitchC[k];
+			mode_lib->vba.AlignedDCCMetaPitchC[k] = mode_lib->vba.DCCMetaPitchC[k];
+		}
+		if (mode_lib->vba.AlignedYPitch[k] > mode_lib->vba.PitchY[k]
+				|| mode_lib->vba.AlignedCPitch[k] > mode_lib->vba.PitchC[k]
+				|| mode_lib->vba.AlignedDCCMetaPitchY[k] > mode_lib->vba.DCCMetaPitchY[k]
+				|| mode_lib->vba.AlignedDCCMetaPitchC[k] > mode_lib->vba.DCCMetaPitchC[k]) {
+			mode_lib->vba.PitchSupport = false;
+		}
+	}
+
+	mode_lib->vba.ViewportExceedsSurface = false;
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (mode_lib->vba.ViewportWidth[k] > mode_lib->vba.SurfaceWidthY[k]
+				|| mode_lib->vba.ViewportHeight[k] > mode_lib->vba.SurfaceHeightY[k]) {
+			mode_lib->vba.ViewportExceedsSurface = true;
+			if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
+					&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
+					&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
+					&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
+					&& mode_lib->vba.SourcePixelFormat[k] != dm_444_8
+					&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe) {
+				if (mode_lib->vba.ViewportWidthChroma[k] > mode_lib->vba.SurfaceWidthC[k]
+						|| mode_lib->vba.ViewportHeightChroma[k]
+								> mode_lib->vba.SurfaceHeightC[k]) {
+					mode_lib->vba.ViewportExceedsSurface = true;
+				}
+			}
+		}
+	}
+
+	/*Mode Support, Voltage State and SOC Configuration*/
+	for (i = v->soc.num_states - 1; i >= 0; i--) {
+		for (j = 0; j < 2; j++) {
+			if (mode_lib->vba.ScaleRatioAndTapsSupport == true
+				&& mode_lib->vba.SourceFormatPixelAndScanSupport == true
+				&& mode_lib->vba.ViewportSizeSupport[i][j] == true
+				&& !mode_lib->vba.LinkRateDoesNotMatchDPVersion
+				&& !mode_lib->vba.LinkRateForMultistreamNotIndicated
+				&& !mode_lib->vba.BPPForMultistreamNotIndicated
+				&& !mode_lib->vba.MultistreamWithHDMIOreDP
+				&& !mode_lib->vba.ExceededMultistreamSlots[i]
+				&& !mode_lib->vba.MSOOrODMSplitWithNonDPLink
+				&& !mode_lib->vba.NotEnoughLanesForMSO
+				&& mode_lib->vba.LinkCapacitySupport[i] == true && !mode_lib->vba.P2IWith420
+				&& !mode_lib->vba.DSCOnlyIfNecessaryWithBPP
+				&& !mode_lib->vba.DSC422NativeNotSupported
+				&& !mode_lib->vba.MPCCombineMethodIncompatible
+				&& mode_lib->vba.ODMCombine2To1SupportCheckOK[i] == true
+				&& mode_lib->vba.ODMCombine4To1SupportCheckOK[i] == true
+				&& mode_lib->vba.NotEnoughDSCUnits[i] == false
+				&& !mode_lib->vba.NotEnoughDSCSlices[i]
+				&& !mode_lib->vba.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe
+				&& !mode_lib->vba.InvalidCombinationOfMALLUseForPStateAndStaticScreen
+				&& mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] == false
+				&& mode_lib->vba.PixelsPerLinePerDSCUnitSupport[i]
+				&& mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] == false
+				&& !mode_lib->vba.InvalidCombinationOfMALLUseForPState
+				&& !mode_lib->vba.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified
+				&& mode_lib->vba.ROBSupport[i][j] == true
+				&& mode_lib->vba.DISPCLK_DPPCLK_Support[i][j] == true
+				&& mode_lib->vba.TotalAvailablePipesSupport[i][j] == true
+				&& mode_lib->vba.NumberOfOTGSupport == true
+				&& mode_lib->vba.NumberOfHDMIFRLSupport == true
+				&& mode_lib->vba.EnoughWritebackUnits == true
+				&& mode_lib->vba.WritebackLatencySupport == true
+				&& mode_lib->vba.WritebackScaleRatioAndTapsSupport == true
+				&& mode_lib->vba.CursorSupport == true && mode_lib->vba.PitchSupport == true
+				&& mode_lib->vba.ViewportExceedsSurface == false
+				&& mode_lib->vba.PrefetchSupported[i][j] == true
+				&& mode_lib->vba.VActiveBandwithSupport[i][j] == true
+				&& mode_lib->vba.DynamicMetadataSupported[i][j] == true
+				&& mode_lib->vba.TotalVerticalActiveBandwidthSupport[i][j] == true
+				&& mode_lib->vba.VRatioInPrefetchSupported[i][j] == true
+				&& mode_lib->vba.PTEBufferSizeNotExceeded[i][j] == true
+				&& mode_lib->vba.DCCMetaBufferSizeNotExceeded[i][j] == true
+				&& mode_lib->vba.NonsupportedDSCInputBPC == false
+				&& !mode_lib->vba.ExceededMALLSize
+				&& ((mode_lib->vba.HostVMEnable == false
+				&& !mode_lib->vba.ImmediateFlipRequiredFinal)
+				|| mode_lib->vba.ImmediateFlipSupportedForState[i][j])
+				&& (!mode_lib->vba.DRAMClockChangeRequirementFinal
+				|| i == v->soc.num_states - 1
+				|| mode_lib->vba.DRAMClockChangeSupport[i][j] != dm_dram_clock_change_unsupported)
+				&& (!mode_lib->vba.FCLKChangeRequirementFinal || i == v->soc.num_states - 1
+				|| mode_lib->vba.FCLKChangeSupport[i][j] != dm_fclock_change_unsupported)
+				&& (!mode_lib->vba.USRRetrainingRequiredFinal
+				|| &mode_lib->vba.USRRetrainingSupport[i][j])) {
+				mode_lib->vba.ModeSupport[i][j] = true;
+			} else {
+				mode_lib->vba.ModeSupport[i][j] = false;
+			}
+		}
+	}
+
+	MaximumMPCCombine = 0;
+
+	for (i = v->soc.num_states; i >= 0; i--) {
+		if (i == v->soc.num_states || mode_lib->vba.ModeSupport[i][0] == true ||
+				mode_lib->vba.ModeSupport[i][1] == true) {
+			mode_lib->vba.VoltageLevel = i;
+			mode_lib->vba.ModeIsSupported = mode_lib->vba.ModeSupport[i][0] == true
+					|| mode_lib->vba.ModeSupport[i][1] == true;
+
+			if ((mode_lib->vba.ModeSupport[i][0] == false && mode_lib->vba.ModeSupport[i][1] == true)
+				|| MPCCombineMethodAsPossible
+				|| (MPCCombineMethodAsNeededForPStateChangeAndVoltage
+				&& mode_lib->vba.DRAMClockChangeRequirementFinal
+				&& (((mode_lib->vba.DRAMClockChangeSupport[i][1] == dm_dram_clock_change_vactive
+				|| mode_lib->vba.DRAMClockChangeSupport[i][1] ==
+						dm_dram_clock_change_vactive_w_mall_full_frame
+				|| mode_lib->vba.DRAMClockChangeSupport[i][1] ==
+						dm_dram_clock_change_vactive_w_mall_sub_vp)
+				&& !(mode_lib->vba.DRAMClockChangeSupport[i][0] == dm_dram_clock_change_vactive
+				|| mode_lib->vba.DRAMClockChangeSupport[i][0] ==
+						dm_dram_clock_change_vactive_w_mall_full_frame
+				|| mode_lib->vba.DRAMClockChangeSupport[i][0] ==
+						dm_dram_clock_change_vactive_w_mall_sub_vp))
+				|| ((mode_lib->vba.DRAMClockChangeSupport[i][1] == dm_dram_clock_change_vblank
+				|| mode_lib->vba.DRAMClockChangeSupport[i][1] ==
+						dm_dram_clock_change_vblank_w_mall_full_frame
+				|| mode_lib->vba.DRAMClockChangeSupport[i][1] ==
+						dm_dram_clock_change_vblank_w_mall_sub_vp)
+				&& mode_lib->vba.DRAMClockChangeSupport[i][0] == dm_dram_clock_change_unsupported)))
+				|| (MPCCombineMethodAsNeededForPStateChangeAndVoltage &&
+				mode_lib->vba.FCLKChangeRequirementFinal
+				&& ((mode_lib->vba.FCLKChangeSupport[i][1] == dm_fclock_change_vactive
+				&& mode_lib->vba.FCLKChangeSupport[i][0] != dm_fclock_change_vactive)
+				|| (mode_lib->vba.FCLKChangeSupport[i][1] == dm_fclock_change_vblank
+				&& mode_lib->vba.FCLKChangeSupport[i][0] == dm_fclock_change_unsupported)))) {
+				MaximumMPCCombine = 1;
+			} else {
+				MaximumMPCCombine = 0;
+			}
+		}
+	}
+
+	mode_lib->vba.ImmediateFlipSupport =
+			mode_lib->vba.ImmediateFlipSupportedForState[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
+	mode_lib->vba.UnboundedRequestEnabled =
+			mode_lib->vba.UnboundedRequestEnabledAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
+	mode_lib->vba.CompressedBufferSizeInkByte =
+			mode_lib->vba.CompressedBufferSizeInkByteAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine]; // Not used, informational
+
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		mode_lib->vba.MPCCombineEnable[k] =
+				mode_lib->vba.MPCCombine[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
+		mode_lib->vba.DPPPerPlane[k] = mode_lib->vba.NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
+		mode_lib->vba.SwathHeightY[k] =
+				mode_lib->vba.SwathHeightYAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
+		mode_lib->vba.SwathHeightC[k] =
+				mode_lib->vba.SwathHeightCAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
+		mode_lib->vba.DETBufferSizeInKByte[k] =
+			mode_lib->vba.DETBufferSizeInKByteAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
+		mode_lib->vba.DETBufferSizeY[k] =
+				mode_lib->vba.DETBufferSizeYAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
+		mode_lib->vba.DETBufferSizeC[k] =
+				mode_lib->vba.DETBufferSizeCAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
+		mode_lib->vba.OutputType[k] = mode_lib->vba.OutputTypePerState[mode_lib->vba.VoltageLevel][k];
+		mode_lib->vba.OutputRate[k] = mode_lib->vba.OutputRatePerState[mode_lib->vba.VoltageLevel][k];
+	}
+
+	mode_lib->vba.DCFCLK = mode_lib->vba.DCFCLKState[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
+	mode_lib->vba.DRAMSpeed = mode_lib->vba.DRAMSpeedPerState[mode_lib->vba.VoltageLevel];
+	mode_lib->vba.FabricClock = mode_lib->vba.FabricClockPerState[mode_lib->vba.VoltageLevel];
+	mode_lib->vba.SOCCLK = mode_lib->vba.SOCCLKPerState[mode_lib->vba.VoltageLevel];
+	mode_lib->vba.ReturnBW = mode_lib->vba.ReturnBWPerState[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
+	mode_lib->vba.DISPCLK = mode_lib->vba.RequiredDISPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
+	mode_lib->vba.maxMpcComb = MaximumMPCCombine;
+
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (mode_lib->vba.BlendingAndTiming[k] == k) {
+			mode_lib->vba.ODMCombineEnabled[k] =
+					mode_lib->vba.ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k];
+		} else {
+			mode_lib->vba.ODMCombineEnabled[k] = dm_odm_combine_mode_disabled;
+		}
+
+		mode_lib->vba.DSCEnabled[k] = mode_lib->vba.RequiresDSC[mode_lib->vba.VoltageLevel][k];
+		mode_lib->vba.FECEnable[k] = mode_lib->vba.RequiresFEC[mode_lib->vba.VoltageLevel][k];
+		mode_lib->vba.OutputBpp[k] = mode_lib->vba.OutputBppPerState[mode_lib->vba.VoltageLevel][k];
+	}
+
+	mode_lib->vba.UrgentWatermark = mode_lib->vba.Watermark.UrgentWatermark;
+	mode_lib->vba.StutterEnterPlusExitWatermark = mode_lib->vba.Watermark.StutterEnterPlusExitWatermark;
+	mode_lib->vba.StutterExitWatermark = mode_lib->vba.Watermark.StutterExitWatermark;
+	mode_lib->vba.WritebackDRAMClockChangeWatermark = mode_lib->vba.Watermark.WritebackDRAMClockChangeWatermark;
+	mode_lib->vba.DRAMClockChangeWatermark = mode_lib->vba.Watermark.DRAMClockChangeWatermark;
+	mode_lib->vba.UrgentLatency = mode_lib->vba.UrgLatency[mode_lib->vba.VoltageLevel];
+	mode_lib->vba.DCFCLKDeepSleep = mode_lib->vba.ProjectedDCFCLKDeepSleep[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
+
+	/* VBA has Error type to Error Msg output here, but not necessary for DML-C */
+} // ModeSupportAndSystemConfigurationFull
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h
new file mode 100644
index 0000000000000..c62e0991358b3
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DML32_DISPLAY_MODE_VBA_H__
+#define __DML32_DISPLAY_MODE_VBA_H__
+
+#include "../display_mode_enums.h"
+
+// To enable a lot of debug msg
+//#define __DML_VBA_DEBUG__
+// For DML-C changes that hasn't been propagated to VBA yet
+//#define __DML_VBA_ALLOW_DELTA__
+
+// Move these to ip parameters/constant
+// At which vstartup the DML start to try if the mode can be supported
+#define __DML_VBA_MIN_VSTARTUP__    9
+
+// Delay in DCFCLK from ARB to DET (1st num is ARB to SDPIF, 2nd number is SDPIF to DET)
+#define __DML_ARB_TO_RET_DELAY__    7 + 95
+
+// fudge factor for min dcfclk calclation
+#define __DML_MIN_DCFCLK_FACTOR__   1.15
+
+// Prefetch schedule max vratio
+#define __DML_MAX_VRATIO_PRE__ 4.0
+
+#define BPP_INVALID 0
+#define BPP_BLENDED_PIPE 0xffffffff
+
+struct display_mode_lib;
+
+void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);
+void dml32_recalculate(struct display_mode_lib *mode_lib);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
new file mode 100644
index 0000000000000..6509a84eeb640
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -0,0 +1,6254 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#include "display_mode_vba_util_32.h"
+#include "../dml_inline_defs.h"
+#include "display_mode_vba_32.h"
+#include "../display_mode_lib.h"
+
+unsigned int dml32_dscceComputeDelay(
+		unsigned int bpc,
+		double BPP,
+		unsigned int sliceWidth,
+		unsigned int numSlices,
+		enum output_format_class pixelFormat,
+		enum output_encoder_class Output)
+{
+	// valid bpc         = source bits per component in the set of {8, 10, 12}
+	// valid bpp         = increments of 1/16 of a bit
+	//                    min = 6/7/8 in N420/N422/444, respectively
+	//                    max = such that compression is 1:1
+	//valid sliceWidth  = number of pixels per slice line,
+	//	must be less than or equal to 5184/numSlices (or 4096/numSlices in 420 mode)
+	//valid numSlices   = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4}
+	//valid pixelFormat = pixel/color format in the set of {:N444_RGB, :S422, :N422, :N420}
+
+	// fixed value
+	unsigned int rcModelSize = 8192;
+
+	// N422/N420 operate at 2 pixels per clock
+	unsigned int pixelsPerClock, lstall, D, initalXmitDelay, w, s, ix, wx, p, l0, a, ax, L,
+	Delay, pixels;
+
+	if (pixelFormat == dm_420)
+		pixelsPerClock = 2;
+	else if (pixelFormat == dm_n422)
+		pixelsPerClock = 2;
+	// #all other modes operate at 1 pixel per clock
+	else
+		pixelsPerClock = 1;
+
+	//initial transmit delay as per PPS
+	initalXmitDelay = dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock);
+
+	//compute ssm delay
+	if (bpc == 8)
+		D = 81;
+	else if (bpc == 10)
+		D = 89;
+	else
+		D = 113;
+
+	//divide by pixel per cycle to compute slice width as seen by DSC
+	w = sliceWidth / pixelsPerClock;
+
+	//422 mode has an additional cycle of delay
+	if (pixelFormat == dm_420 || pixelFormat == dm_444 || pixelFormat == dm_n422)
+		s = 0;
+	else
+		s = 1;
+
+	//main calculation for the dscce
+	ix = initalXmitDelay + 45;
+	wx = (w + 2) / 3;
+	p = 3 * wx - w;
+	l0 = ix / w;
+	a = ix + p * l0;
+	ax = (a + 2) / 3 + D + 6 + 1;
+	L = (ax + wx - 1) / wx;
+	if ((ix % w) == 0 && p != 0)
+		lstall = 1;
+	else
+		lstall = 0;
+	Delay = L * wx * (numSlices - 1) + ax + s + lstall + 22;
+
+	//dsc processes 3 pixel containers per cycle and a container can contain 1 or 2 pixels
+	pixels = Delay * 3 * pixelsPerClock;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: bpc: %d\n", __func__, bpc);
+	dml_print("DML::%s: BPP: %f\n", __func__, BPP);
+	dml_print("DML::%s: sliceWidth: %d\n", __func__, sliceWidth);
+	dml_print("DML::%s: numSlices: %d\n", __func__, numSlices);
+	dml_print("DML::%s: pixelFormat: %d\n", __func__, pixelFormat);
+	dml_print("DML::%s: Output: %d\n", __func__, Output);
+	dml_print("DML::%s: pixels: %d\n", __func__, pixels);
+#endif
+
+	return pixels;
+}
+
+unsigned int dml32_dscComputeDelay(enum output_format_class pixelFormat, enum output_encoder_class Output)
+{
+	unsigned int Delay = 0;
+
+	if (pixelFormat == dm_420) {
+		//   sfr
+		Delay = Delay + 2;
+		//   dsccif
+		Delay = Delay + 0;
+		//   dscc - input deserializer
+		Delay = Delay + 3;
+		//   dscc gets pixels every other cycle
+		Delay = Delay + 2;
+		//   dscc - input cdc fifo
+		Delay = Delay + 12;
+		//   dscc gets pixels every other cycle
+		Delay = Delay + 13;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   dscc - output cdc fifo
+		Delay = Delay + 7;
+		//   dscc gets pixels every other cycle
+		Delay = Delay + 3;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   dscc - output serializer
+		Delay = Delay + 1;
+		//   sft
+		Delay = Delay + 1;
+	} else if (pixelFormat == dm_n422 || (pixelFormat != dm_444)) {
+		//   sfr
+		Delay = Delay + 2;
+		//   dsccif
+		Delay = Delay + 1;
+		//   dscc - input deserializer
+		Delay = Delay + 5;
+		//  dscc - input cdc fifo
+		Delay = Delay + 25;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   dscc - output cdc fifo
+		Delay = Delay + 10;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   dscc - output serializer
+		Delay = Delay + 1;
+		//   sft
+		Delay = Delay + 1;
+	} else {
+		//   sfr
+		Delay = Delay + 2;
+		//   dsccif
+		Delay = Delay + 0;
+		//   dscc - input deserializer
+		Delay = Delay + 3;
+		//   dscc - input cdc fifo
+		Delay = Delay + 12;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   dscc - output cdc fifo
+		Delay = Delay + 7;
+		//   dscc - output serializer
+		Delay = Delay + 1;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   sft
+		Delay = Delay + 1;
+	}
+
+	return Delay;
+}
+
+
+bool IsVertical(enum dm_rotation_angle Scan)
+{
+	bool is_vert = false;
+
+	if (Scan == dm_rotation_90 || Scan == dm_rotation_90m || Scan == dm_rotation_270 || Scan == dm_rotation_270m)
+		is_vert = true;
+	else
+		is_vert = false;
+	return is_vert;
+}
+
+void dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(
+		double HRatio,
+		double HRatioChroma,
+		double VRatio,
+		double VRatioChroma,
+		double MaxDCHUBToPSCLThroughput,
+		double MaxPSCLToLBThroughput,
+		double PixelClock,
+		enum source_format_class SourcePixelFormat,
+		unsigned int HTaps,
+		unsigned int HTapsChroma,
+		unsigned int VTaps,
+		unsigned int VTapsChroma,
+
+		/* output */
+		double *PSCL_THROUGHPUT,
+		double *PSCL_THROUGHPUT_CHROMA,
+		double *DPPCLKUsingSingleDPP)
+{
+	double DPPCLKUsingSingleDPPLuma;
+	double DPPCLKUsingSingleDPPChroma;
+
+	if (HRatio > 1) {
+		*PSCL_THROUGHPUT = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput * HRatio /
+				dml_ceil((double) HTaps / 6.0, 1.0));
+	} else {
+		*PSCL_THROUGHPUT = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput);
+	}
+
+	DPPCLKUsingSingleDPPLuma = PixelClock * dml_max3(VTaps / 6 * dml_min(1, HRatio), HRatio * VRatio /
+			*PSCL_THROUGHPUT, 1);
+
+	if ((HTaps > 6 || VTaps > 6) && DPPCLKUsingSingleDPPLuma < 2 * PixelClock)
+		DPPCLKUsingSingleDPPLuma = 2 * PixelClock;
+
+	if ((SourcePixelFormat != dm_420_8 && SourcePixelFormat != dm_420_10 && SourcePixelFormat != dm_420_12 &&
+			SourcePixelFormat != dm_rgbe_alpha)) {
+		*PSCL_THROUGHPUT_CHROMA = 0;
+		*DPPCLKUsingSingleDPP = DPPCLKUsingSingleDPPLuma;
+	} else {
+		if (HRatioChroma > 1) {
+			*PSCL_THROUGHPUT_CHROMA = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput *
+					HRatioChroma / dml_ceil((double) HTapsChroma / 6.0, 1.0));
+		} else {
+			*PSCL_THROUGHPUT_CHROMA = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput);
+		}
+		DPPCLKUsingSingleDPPChroma = PixelClock * dml_max3(VTapsChroma / 6 * dml_min(1, HRatioChroma),
+				HRatioChroma * VRatioChroma / *PSCL_THROUGHPUT_CHROMA, 1);
+		if ((HTapsChroma > 6 || VTapsChroma > 6) && DPPCLKUsingSingleDPPChroma < 2 * PixelClock)
+			DPPCLKUsingSingleDPPChroma = 2 * PixelClock;
+		*DPPCLKUsingSingleDPP = dml_max(DPPCLKUsingSingleDPPLuma, DPPCLKUsingSingleDPPChroma);
+	}
+}
+
+void dml32_CalculateBytePerPixelAndBlockSizes(
+		enum source_format_class SourcePixelFormat,
+		enum dm_swizzle_mode SurfaceTiling,
+
+		/* Output */
+		unsigned int *BytePerPixelY,
+		unsigned int *BytePerPixelC,
+		double  *BytePerPixelDETY,
+		double  *BytePerPixelDETC,
+		unsigned int *BlockHeight256BytesY,
+		unsigned int *BlockHeight256BytesC,
+		unsigned int *BlockWidth256BytesY,
+		unsigned int *BlockWidth256BytesC,
+		unsigned int *MacroTileHeightY,
+		unsigned int *MacroTileHeightC,
+		unsigned int *MacroTileWidthY,
+		unsigned int *MacroTileWidthC)
+{
+	if (SourcePixelFormat == dm_444_64) {
+		*BytePerPixelDETY = 8;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 8;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_444_32 || SourcePixelFormat == dm_rgbe) {
+		*BytePerPixelDETY = 4;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 4;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_444_16 || SourcePixelFormat == dm_444_16) {
+		*BytePerPixelDETY = 2;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 2;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_444_8) {
+		*BytePerPixelDETY = 1;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 1;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_rgbe_alpha) {
+		*BytePerPixelDETY = 4;
+		*BytePerPixelDETC = 1;
+		*BytePerPixelY = 4;
+		*BytePerPixelC = 1;
+	} else if (SourcePixelFormat == dm_420_8) {
+		*BytePerPixelDETY = 1;
+		*BytePerPixelDETC = 2;
+		*BytePerPixelY = 1;
+		*BytePerPixelC = 2;
+	} else if (SourcePixelFormat == dm_420_12) {
+		*BytePerPixelDETY = 2;
+		*BytePerPixelDETC = 4;
+		*BytePerPixelY = 2;
+		*BytePerPixelC = 4;
+	} else {
+		*BytePerPixelDETY = 4.0 / 3;
+		*BytePerPixelDETC = 8.0 / 3;
+		*BytePerPixelY = 2;
+		*BytePerPixelC = 4;
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: SourcePixelFormat = %d\n", __func__, SourcePixelFormat);
+	dml_print("DML::%s: BytePerPixelDETY = %f\n", __func__, *BytePerPixelDETY);
+	dml_print("DML::%s: BytePerPixelDETC = %f\n", __func__, *BytePerPixelDETC);
+	dml_print("DML::%s: BytePerPixelY    = %d\n", __func__, *BytePerPixelY);
+	dml_print("DML::%s: BytePerPixelC    = %d\n", __func__, *BytePerPixelC);
+#endif
+	if ((SourcePixelFormat == dm_444_64 || SourcePixelFormat == dm_444_32
+			|| SourcePixelFormat == dm_444_16
+			|| SourcePixelFormat == dm_444_8
+			|| SourcePixelFormat == dm_mono_16
+			|| SourcePixelFormat == dm_mono_8
+			|| SourcePixelFormat == dm_rgbe)) {
+		if (SurfaceTiling == dm_sw_linear)
+			*BlockHeight256BytesY = 1;
+		else if (SourcePixelFormat == dm_444_64)
+			*BlockHeight256BytesY = 4;
+		else if (SourcePixelFormat == dm_444_8)
+			*BlockHeight256BytesY = 16;
+		else
+			*BlockHeight256BytesY = 8;
+
+		*BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY;
+		*BlockHeight256BytesC = 0;
+		*BlockWidth256BytesC = 0;
+	} else {
+		if (SurfaceTiling == dm_sw_linear) {
+			*BlockHeight256BytesY = 1;
+			*BlockHeight256BytesC = 1;
+		} else if (SourcePixelFormat == dm_rgbe_alpha) {
+			*BlockHeight256BytesY = 8;
+			*BlockHeight256BytesC = 16;
+		} else if (SourcePixelFormat == dm_420_8) {
+			*BlockHeight256BytesY = 16;
+			*BlockHeight256BytesC = 8;
+		} else {
+			*BlockHeight256BytesY = 8;
+			*BlockHeight256BytesC = 8;
+		}
+		*BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY;
+		*BlockWidth256BytesC = 256U / *BytePerPixelC / *BlockHeight256BytesC;
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: BlockWidth256BytesY  = %d\n", __func__, *BlockWidth256BytesY);
+	dml_print("DML::%s: BlockHeight256BytesY = %d\n", __func__, *BlockHeight256BytesY);
+	dml_print("DML::%s: BlockWidth256BytesC  = %d\n", __func__, *BlockWidth256BytesC);
+	dml_print("DML::%s: BlockHeight256BytesC = %d\n", __func__, *BlockHeight256BytesC);
+#endif
+
+	if (SurfaceTiling == dm_sw_linear) {
+		*MacroTileHeightY = *BlockHeight256BytesY;
+		*MacroTileWidthY = 256 / *BytePerPixelY / *MacroTileHeightY;
+		*MacroTileHeightC = *BlockHeight256BytesC;
+		if (*MacroTileHeightC == 0)
+			*MacroTileWidthC = 0;
+		else
+			*MacroTileWidthC = 256 / *BytePerPixelC / *MacroTileHeightC;
+	} else if (SurfaceTiling == dm_sw_64kb_d || SurfaceTiling == dm_sw_64kb_d_t ||
+			SurfaceTiling == dm_sw_64kb_d_x || SurfaceTiling == dm_sw_64kb_r_x) {
+		*MacroTileHeightY = 16 * *BlockHeight256BytesY;
+		*MacroTileWidthY = 65536 / *BytePerPixelY / *MacroTileHeightY;
+		*MacroTileHeightC = 16 * *BlockHeight256BytesC;
+		if (*MacroTileHeightC == 0)
+			*MacroTileWidthC = 0;
+		else
+			*MacroTileWidthC = 65536 / *BytePerPixelC / *MacroTileHeightC;
+	} else {
+		*MacroTileHeightY = 32 * *BlockHeight256BytesY;
+		*MacroTileWidthY = 65536 * 4 / *BytePerPixelY / *MacroTileHeightY;
+		*MacroTileHeightC = 32 * *BlockHeight256BytesC;
+		if (*MacroTileHeightC == 0)
+			*MacroTileWidthC = 0;
+		else
+			*MacroTileWidthC = 65536 * 4 / *BytePerPixelC / *MacroTileHeightC;
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: MacroTileWidthY  = %d\n", __func__, *MacroTileWidthY);
+	dml_print("DML::%s: MacroTileHeightY = %d\n", __func__, *MacroTileHeightY);
+	dml_print("DML::%s: MacroTileWidthC  = %d\n", __func__, *MacroTileWidthC);
+	dml_print("DML::%s: MacroTileHeightC = %d\n", __func__, *MacroTileHeightC);
+#endif
+} // CalculateBytePerPixelAndBlockSizes
+
+void dml32_CalculatedoublePipeDPPCLKAndSCLThroughput(
+		double HRatio,
+		double HRatioChroma,
+		double VRatio,
+		double VRatioChroma,
+		double MaxDCHUBToPSCLThroughput,
+		double MaxPSCLToLBThroughput,
+		double PixelClock,
+		enum source_format_class SourcePixelFormat,
+		unsigned int HTaps,
+		unsigned int HTapsChroma,
+		unsigned int VTaps,
+		unsigned int VTapsChroma,
+
+		/* output */
+		double *PSCL_THROUGHPUT,
+		double *PSCL_THROUGHPUT_CHROMA,
+		double *DPPCLKUsingdoubleDPP)
+{
+	double DPPCLKUsingdoubleDPPLuma;
+	double DPPCLKUsingdoubleDPPChroma;
+
+	if (HRatio > 1) {
+		*PSCL_THROUGHPUT = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput * HRatio /
+				dml_ceil((double) HTaps / 6.0, 1.0));
+	} else {
+		*PSCL_THROUGHPUT = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput);
+	}
+
+	DPPCLKUsingdoubleDPPLuma = PixelClock * dml_max3(VTaps / 6 * dml_min(1, HRatio), HRatio * VRatio /
+			*PSCL_THROUGHPUT, 1);
+
+	if ((HTaps > 6 || VTaps > 6) && DPPCLKUsingdoubleDPPLuma < 2 * PixelClock)
+		DPPCLKUsingdoubleDPPLuma = 2 * PixelClock;
+
+	if ((SourcePixelFormat != dm_420_8 && SourcePixelFormat != dm_420_10 && SourcePixelFormat != dm_420_12 &&
+			SourcePixelFormat != dm_rgbe_alpha)) {
+		*PSCL_THROUGHPUT_CHROMA = 0;
+		*DPPCLKUsingdoubleDPP = DPPCLKUsingdoubleDPPLuma;
+	} else {
+		if (HRatioChroma > 1) {
+			*PSCL_THROUGHPUT_CHROMA = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput *
+					HRatioChroma / dml_ceil((double) HTapsChroma / 6.0, 1.0));
+		} else {
+			*PSCL_THROUGHPUT_CHROMA = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput);
+		}
+		DPPCLKUsingdoubleDPPChroma = PixelClock * dml_max3(VTapsChroma / 6 * dml_min(1, HRatioChroma),
+				HRatioChroma * VRatioChroma / *PSCL_THROUGHPUT_CHROMA, 1);
+		if ((HTapsChroma > 6 || VTapsChroma > 6) && DPPCLKUsingdoubleDPPChroma < 2 * PixelClock)
+			DPPCLKUsingdoubleDPPChroma = 2 * PixelClock;
+		*DPPCLKUsingdoubleDPP = dml_max(DPPCLKUsingdoubleDPPLuma, DPPCLKUsingdoubleDPPChroma);
+	}
+}
+
+void dml32_CalculateSwathAndDETConfiguration(
+		unsigned int DETSizeOverride[],
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		unsigned int ConfigReturnBufferSizeInKByte,
+		unsigned int MaxTotalDETInKByte,
+		unsigned int MinCompressedBufferSizeInKByte,
+		double ForceSingleDPP,
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int nomDETInKByte,
+		enum unbounded_requesting_policy UseUnboundedRequestingFinal,
+		unsigned int CompressedBufferSegmentSizeInkByteFinal,
+		enum output_encoder_class Output[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double MaximumSwathWidthLuma[],
+		double MaximumSwathWidthChroma[],
+		enum dm_rotation_angle SourceRotation[],
+		bool ViewportStationary[],
+		enum source_format_class SourcePixelFormat[],
+		enum dm_swizzle_mode SurfaceTiling[],
+		unsigned int ViewportWidth[],
+		unsigned int ViewportHeight[],
+		unsigned int ViewportXStart[],
+		unsigned int ViewportYStart[],
+		unsigned int ViewportXStartC[],
+		unsigned int ViewportYStartC[],
+		unsigned int SurfaceWidthY[],
+		unsigned int SurfaceWidthC[],
+		unsigned int SurfaceHeightY[],
+		unsigned int SurfaceHeightC[],
+		unsigned int Read256BytesBlockHeightY[],
+		unsigned int Read256BytesBlockHeightC[],
+		unsigned int Read256BytesBlockWidthY[],
+		unsigned int Read256BytesBlockWidthC[],
+		enum odm_combine_mode ODMMode[],
+		unsigned int BlendingAndTiming[],
+		unsigned int BytePerPixY[],
+		unsigned int BytePerPixC[],
+		double BytePerPixDETY[],
+		double BytePerPixDETC[],
+		unsigned int HActive[],
+		double HRatio[],
+		double HRatioChroma[],
+		unsigned int DPPPerSurface[],
+
+		/* Output */
+		unsigned int swath_width_luma_ub[],
+		unsigned int swath_width_chroma_ub[],
+		double SwathWidth[],
+		double SwathWidthChroma[],
+		unsigned int SwathHeightY[],
+		unsigned int SwathHeightC[],
+		unsigned int DETBufferSizeInKByte[],
+		unsigned int DETBufferSizeY[],
+		unsigned int DETBufferSizeC[],
+		bool *UnboundedRequestEnabled,
+		unsigned int *CompressedBufferSizeInkByte,
+		bool ViewportSizeSupportPerSurface[],
+		bool *ViewportSizeSupport)
+{
+	unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX];
+	unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX];
+	unsigned int RoundedUpMaxSwathSizeBytesY[DC__NUM_DPP__MAX];
+	unsigned int RoundedUpMaxSwathSizeBytesC[DC__NUM_DPP__MAX];
+	unsigned int RoundedUpSwathSizeBytesY;
+	unsigned int RoundedUpSwathSizeBytesC;
+	double SwathWidthdoubleDPP[DC__NUM_DPP__MAX];
+	double SwathWidthdoubleDPPChroma[DC__NUM_DPP__MAX];
+	unsigned int k;
+	unsigned int TotalActiveDPP = 0;
+	bool NoChromaSurfaces = true;
+	unsigned int DETBufferSizeInKByteForSwathCalculation;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: ForceSingleDPP = %d\n", __func__, ForceSingleDPP);
+#endif
+	dml32_CalculateSwathWidth(ForceSingleDPP,
+			NumberOfActiveSurfaces,
+			SourcePixelFormat,
+			SourceRotation,
+			ViewportStationary,
+			ViewportWidth,
+			ViewportHeight,
+			ViewportXStart,
+			ViewportYStart,
+			ViewportXStartC,
+			ViewportYStartC,
+			SurfaceWidthY,
+			SurfaceWidthC,
+			SurfaceHeightY,
+			SurfaceHeightC,
+			ODMMode,
+			BytePerPixY,
+			BytePerPixC,
+			Read256BytesBlockHeightY,
+			Read256BytesBlockHeightC,
+			Read256BytesBlockWidthY,
+			Read256BytesBlockWidthC,
+			BlendingAndTiming,
+			HActive,
+			HRatio,
+			DPPPerSurface,
+
+			/* Output */
+			SwathWidthdoubleDPP,
+			SwathWidthdoubleDPPChroma,
+			SwathWidth,
+			SwathWidthChroma,
+			MaximumSwathHeightY,
+			MaximumSwathHeightC,
+			swath_width_luma_ub,
+			swath_width_chroma_ub);
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		RoundedUpMaxSwathSizeBytesY[k] = swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k];
+		RoundedUpMaxSwathSizeBytesC[k] = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k];
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%0d DPPPerSurface = %d\n", __func__, k, DPPPerSurface[k]);
+		dml_print("DML::%s: k=%0d swath_width_luma_ub = %d\n", __func__, k, swath_width_luma_ub[k]);
+		dml_print("DML::%s: k=%0d BytePerPixDETY = %f\n", __func__, k, BytePerPixDETY[k]);
+		dml_print("DML::%s: k=%0d MaximumSwathHeightY = %d\n", __func__, k, MaximumSwathHeightY[k]);
+		dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesY = %d\n", __func__, k,
+				RoundedUpMaxSwathSizeBytesY[k]);
+		dml_print("DML::%s: k=%0d swath_width_chroma_ub = %d\n", __func__, k, swath_width_chroma_ub[k]);
+		dml_print("DML::%s: k=%0d BytePerPixDETC = %f\n", __func__, k, BytePerPixDETC[k]);
+		dml_print("DML::%s: k=%0d MaximumSwathHeightC = %d\n", __func__, k, MaximumSwathHeightC[k]);
+		dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesC = %d\n", __func__, k,
+				RoundedUpMaxSwathSizeBytesC[k]);
+#endif
+
+		if (SourcePixelFormat[k] == dm_420_10) {
+			RoundedUpMaxSwathSizeBytesY[k] = dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesY[k], 256);
+			RoundedUpMaxSwathSizeBytesC[k] = dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesC[k], 256);
+		}
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		TotalActiveDPP = TotalActiveDPP + (ForceSingleDPP ? 1 : DPPPerSurface[k]);
+		if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 ||
+				SourcePixelFormat[k] == dm_420_12 || SourcePixelFormat[k] == dm_rgbe_alpha) {
+			NoChromaSurfaces = false;
+		}
+	}
+
+	*UnboundedRequestEnabled = dml32_UnboundedRequest(UseUnboundedRequestingFinal, TotalActiveDPP,
+			NoChromaSurfaces, Output[0]);
+
+	dml32_CalculateDETBufferSize(DETSizeOverride,
+			UseMALLForPStateChange,
+			ForceSingleDPP,
+			NumberOfActiveSurfaces,
+			*UnboundedRequestEnabled,
+			nomDETInKByte,
+			MaxTotalDETInKByte,
+			ConfigReturnBufferSizeInKByte,
+			MinCompressedBufferSizeInKByte,
+			CompressedBufferSegmentSizeInkByteFinal,
+			SourcePixelFormat,
+			ReadBandwidthLuma,
+			ReadBandwidthChroma,
+			RoundedUpMaxSwathSizeBytesY,
+			RoundedUpMaxSwathSizeBytesC,
+			DPPPerSurface,
+
+			/* Output */
+			DETBufferSizeInKByte,    // per hubp pipe
+			CompressedBufferSizeInkByte);
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: TotalActiveDPP = %d\n", __func__, TotalActiveDPP);
+	dml_print("DML::%s: nomDETInKByte = %d\n", __func__, nomDETInKByte);
+	dml_print("DML::%s: ConfigReturnBufferSizeInKByte = %d\n", __func__, ConfigReturnBufferSizeInKByte);
+	dml_print("DML::%s: UseUnboundedRequestingFinal = %d\n", __func__, UseUnboundedRequestingFinal);
+	dml_print("DML::%s: UnboundedRequestEnabled = %d\n", __func__, *UnboundedRequestEnabled);
+	dml_print("DML::%s: CompressedBufferSizeInkByte = %d\n", __func__, *CompressedBufferSizeInkByte);
+#endif
+
+	*ViewportSizeSupport = true;
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+
+		DETBufferSizeInKByteForSwathCalculation = (UseMALLForPStateChange[k] ==
+				dm_use_mall_pstate_change_phantom_pipe ? 1024 : DETBufferSizeInKByte[k]);
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%0d DETBufferSizeInKByteForSwathCalculation = %d\n", __func__, k,
+				DETBufferSizeInKByteForSwathCalculation);
+#endif
+
+		if (RoundedUpMaxSwathSizeBytesY[k] + RoundedUpMaxSwathSizeBytesC[k] <=
+				DETBufferSizeInKByteForSwathCalculation * 1024 / 2) {
+			SwathHeightY[k] = MaximumSwathHeightY[k];
+			SwathHeightC[k] = MaximumSwathHeightC[k];
+			RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY[k];
+			RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC[k];
+		} else if (RoundedUpMaxSwathSizeBytesY[k] >= 1.5 * RoundedUpMaxSwathSizeBytesC[k] &&
+				RoundedUpMaxSwathSizeBytesY[k] / 2 + RoundedUpMaxSwathSizeBytesC[k] <=
+				DETBufferSizeInKByteForSwathCalculation * 1024 / 2) {
+			SwathHeightY[k] = MaximumSwathHeightY[k] / 2;
+			SwathHeightC[k] = MaximumSwathHeightC[k];
+			RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY[k] / 2;
+			RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC[k];
+		} else if (RoundedUpMaxSwathSizeBytesY[k] < 1.5 * RoundedUpMaxSwathSizeBytesC[k] &&
+				RoundedUpMaxSwathSizeBytesY[k] + RoundedUpMaxSwathSizeBytesC[k] / 2 <=
+				DETBufferSizeInKByteForSwathCalculation * 1024 / 2) {
+			SwathHeightY[k] = MaximumSwathHeightY[k];
+			SwathHeightC[k] = MaximumSwathHeightC[k] / 2;
+			RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY[k];
+			RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC[k] / 2;
+		} else {
+			SwathHeightY[k] = MaximumSwathHeightY[k] / 2;
+			SwathHeightC[k] = MaximumSwathHeightC[k] / 2;
+			RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY[k] / 2;
+			RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC[k] / 2;
+		}
+
+		if ((RoundedUpMaxSwathSizeBytesY[k] / 2 + RoundedUpMaxSwathSizeBytesC[k] / 2 >
+				DETBufferSizeInKByteForSwathCalculation * 1024 / 2)
+				|| SwathWidth[k] > MaximumSwathWidthLuma[k] || (SwathHeightC[k] > 0 &&
+						SwathWidthChroma[k] > MaximumSwathWidthChroma[k])) {
+			*ViewportSizeSupport = false;
+			ViewportSizeSupportPerSurface[k] = false;
+		} else {
+			ViewportSizeSupportPerSurface[k] = true;
+		}
+
+		if (SwathHeightC[k] == 0) {
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%0d All DET for plane0\n", __func__, k);
+#endif
+			DETBufferSizeY[k] = DETBufferSizeInKByte[k] * 1024;
+			DETBufferSizeC[k] = 0;
+		} else if (RoundedUpSwathSizeBytesY <= 1.5 * RoundedUpSwathSizeBytesC) {
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%0d Half DET for plane0, half for plane1\n", __func__, k);
+#endif
+			DETBufferSizeY[k] = DETBufferSizeInKByte[k] * 1024 / 2;
+			DETBufferSizeC[k] = DETBufferSizeInKByte[k] * 1024 / 2;
+		} else {
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%0d 2/3 DET for plane0, 1/3 for plane1\n", __func__, k);
+#endif
+			DETBufferSizeY[k] = dml_floor(DETBufferSizeInKByte[k] * 1024 * 2 / 3, 1024);
+			DETBufferSizeC[k] = DETBufferSizeInKByte[k] * 1024 - DETBufferSizeY[k];
+		}
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%0d SwathHeightY = %d\n", __func__, k, SwathHeightY[k]);
+		dml_print("DML::%s: k=%0d SwathHeightC = %d\n", __func__, k, SwathHeightC[k]);
+		dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesY = %d\n", __func__,
+				k, RoundedUpMaxSwathSizeBytesY[k]);
+		dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesC = %d\n", __func__,
+				k, RoundedUpMaxSwathSizeBytesC[k]);
+		dml_print("DML::%s: k=%0d RoundedUpSwathSizeBytesY = %d\n", __func__, k, RoundedUpSwathSizeBytesY);
+		dml_print("DML::%s: k=%0d RoundedUpSwathSizeBytesC = %d\n", __func__, k, RoundedUpSwathSizeBytesC);
+		dml_print("DML::%s: k=%0d DETBufferSizeInKByte = %d\n", __func__, k, DETBufferSizeInKByte[k]);
+		dml_print("DML::%s: k=%0d DETBufferSizeY = %d\n", __func__, k, DETBufferSizeY[k]);
+		dml_print("DML::%s: k=%0d DETBufferSizeC = %d\n", __func__, k, DETBufferSizeC[k]);
+		dml_print("DML::%s: k=%0d ViewportSizeSupportPerSurface = %d\n", __func__, k,
+				ViewportSizeSupportPerSurface[k]);
+#endif
+
+	}
+} // CalculateSwathAndDETConfiguration
+
+void dml32_CalculateSwathWidth(
+		bool				ForceSingleDPP,
+		unsigned int			NumberOfActiveSurfaces,
+		enum source_format_class	SourcePixelFormat[],
+		enum dm_rotation_angle		SourceRotation[],
+		bool				ViewportStationary[],
+		unsigned int			ViewportWidth[],
+		unsigned int			ViewportHeight[],
+		unsigned int			ViewportXStart[],
+		unsigned int			ViewportYStart[],
+		unsigned int			ViewportXStartC[],
+		unsigned int			ViewportYStartC[],
+		unsigned int			SurfaceWidthY[],
+		unsigned int			SurfaceWidthC[],
+		unsigned int			SurfaceHeightY[],
+		unsigned int			SurfaceHeightC[],
+		enum odm_combine_mode		ODMMode[],
+		unsigned int			BytePerPixY[],
+		unsigned int			BytePerPixC[],
+		unsigned int			Read256BytesBlockHeightY[],
+		unsigned int			Read256BytesBlockHeightC[],
+		unsigned int			Read256BytesBlockWidthY[],
+		unsigned int			Read256BytesBlockWidthC[],
+		unsigned int			BlendingAndTiming[],
+		unsigned int			HActive[],
+		double				HRatio[],
+		unsigned int			DPPPerSurface[],
+
+		/* Output */
+		double				SwathWidthdoubleDPPY[],
+		double				SwathWidthdoubleDPPC[],
+		double				SwathWidthY[], // per-pipe
+		double				SwathWidthC[], // per-pipe
+		unsigned int			MaximumSwathHeightY[],
+		unsigned int			MaximumSwathHeightC[],
+		unsigned int			swath_width_luma_ub[], // per-pipe
+		unsigned int			swath_width_chroma_ub[]) // per-pipe
+{
+	unsigned int k, j;
+	enum odm_combine_mode MainSurfaceODMMode;
+
+    unsigned int surface_width_ub_l;
+    unsigned int surface_height_ub_l;
+    unsigned int surface_width_ub_c;
+    unsigned int surface_height_ub_c;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: ForceSingleDPP = %d\n", __func__, ForceSingleDPP);
+	dml_print("DML::%s: NumberOfActiveSurfaces = %d\n", __func__, NumberOfActiveSurfaces);
+#endif
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (!IsVertical(SourceRotation[k]))
+			SwathWidthdoubleDPPY[k] = ViewportWidth[k];
+		else
+			SwathWidthdoubleDPPY[k] = ViewportHeight[k];
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d ViewportWidth=%d\n", __func__, k, ViewportWidth[k]);
+		dml_print("DML::%s: k=%d ViewportHeight=%d\n", __func__, k, ViewportHeight[k]);
+#endif
+
+		MainSurfaceODMMode = ODMMode[k];
+		for (j = 0; j < NumberOfActiveSurfaces; ++j) {
+			if (BlendingAndTiming[k] == j)
+				MainSurfaceODMMode = ODMMode[j];
+		}
+
+		if (ForceSingleDPP) {
+			SwathWidthY[k] = SwathWidthdoubleDPPY[k];
+		} else {
+			if (MainSurfaceODMMode == dm_odm_combine_mode_4to1) {
+				SwathWidthY[k] = dml_min(SwathWidthdoubleDPPY[k],
+						dml_round(HActive[k] / 4.0 * HRatio[k]));
+			} else if (MainSurfaceODMMode == dm_odm_combine_mode_2to1) {
+				SwathWidthY[k] = dml_min(SwathWidthdoubleDPPY[k],
+						dml_round(HActive[k] / 2.0 * HRatio[k]));
+			} else if (DPPPerSurface[k] == 2) {
+				SwathWidthY[k] = SwathWidthdoubleDPPY[k] / 2;
+			} else {
+				SwathWidthY[k] = SwathWidthdoubleDPPY[k];
+			}
+		}
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d HActive=%d\n", __func__, k, HActive[k]);
+		dml_print("DML::%s: k=%d HRatio=%f\n", __func__, k, HRatio[k]);
+		dml_print("DML::%s: k=%d MainSurfaceODMMode=%d\n", __func__, k, MainSurfaceODMMode);
+		dml_print("DML::%s: k=%d SwathWidthdoubleDPPY=%d\n", __func__, k, SwathWidthdoubleDPPY[k]);
+		dml_print("DML::%s: k=%d SwathWidthY=%d\n", __func__, k, SwathWidthY[k]);
+#endif
+
+		if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 ||
+				SourcePixelFormat[k] == dm_420_12) {
+			SwathWidthC[k] = SwathWidthY[k] / 2;
+			SwathWidthdoubleDPPC[k] = SwathWidthdoubleDPPY[k] / 2;
+		} else {
+			SwathWidthC[k] = SwathWidthY[k];
+			SwathWidthdoubleDPPC[k] = SwathWidthdoubleDPPY[k];
+		}
+
+		if (ForceSingleDPP == true) {
+			SwathWidthY[k] = SwathWidthdoubleDPPY[k];
+			SwathWidthC[k] = SwathWidthdoubleDPPC[k];
+		}
+
+		surface_width_ub_l  = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]);
+		surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]);
+		surface_width_ub_c  = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]);
+		surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]);
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d surface_width_ub_l=%0d\n", __func__, k, surface_width_ub_l);
+		dml_print("DML::%s: k=%d surface_height_ub_l=%0d\n", __func__, k, surface_height_ub_l);
+		dml_print("DML::%s: k=%d surface_width_ub_c=%0d\n", __func__, k, surface_width_ub_c);
+		dml_print("DML::%s: k=%d surface_height_ub_c=%0d\n", __func__, k, surface_height_ub_c);
+		dml_print("DML::%s: k=%d Read256BytesBlockWidthY=%0d\n", __func__, k, Read256BytesBlockWidthY[k]);
+		dml_print("DML::%s: k=%d Read256BytesBlockHeightY=%0d\n", __func__, k, Read256BytesBlockHeightY[k]);
+		dml_print("DML::%s: k=%d Read256BytesBlockWidthC=%0d\n", __func__, k, Read256BytesBlockWidthC[k]);
+		dml_print("DML::%s: k=%d Read256BytesBlockHeightC=%0d\n", __func__, k, Read256BytesBlockHeightC[k]);
+		dml_print("DML::%s: k=%d ViewportStationary=%0d\n", __func__, k, ViewportStationary[k]);
+		dml_print("DML::%s: k=%d DPPPerSurface=%0d\n", __func__, k, DPPPerSurface[k]);
+#endif
+
+		if (!IsVertical(SourceRotation[k])) {
+			MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k];
+			MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k];
+			if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
+				swath_width_luma_ub[k] = dml_min(surface_width_ub_l,
+						dml_floor(ViewportXStart[k] +
+								SwathWidthY[k] +
+								Read256BytesBlockWidthY[k] - 1,
+								Read256BytesBlockWidthY[k]) -
+								dml_floor(ViewportXStart[k],
+								Read256BytesBlockWidthY[k]));
+			} else {
+				swath_width_luma_ub[k] = dml_min(surface_width_ub_l,
+						dml_ceil(SwathWidthY[k] - 1,
+								Read256BytesBlockWidthY[k]) +
+								Read256BytesBlockWidthY[k]);
+			}
+			if (BytePerPixC[k] > 0) {
+				if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
+					swath_width_chroma_ub[k] = dml_min(surface_width_ub_c,
+							dml_floor(ViewportXStartC[k] + SwathWidthC[k] +
+									Read256BytesBlockWidthC[k] - 1,
+									Read256BytesBlockWidthC[k]) -
+									dml_floor(ViewportXStartC[k],
+									Read256BytesBlockWidthC[k]));
+				} else {
+					swath_width_chroma_ub[k] = dml_min(surface_width_ub_c,
+							dml_ceil(SwathWidthC[k] - 1,
+								Read256BytesBlockWidthC[k]) +
+								Read256BytesBlockWidthC[k]);
+				}
+			} else {
+				swath_width_chroma_ub[k] = 0;
+			}
+		} else {
+			MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k];
+			MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k];
+
+			if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
+				swath_width_luma_ub[k] = dml_min(surface_height_ub_l, dml_floor(ViewportYStart[k] +
+						SwathWidthY[k] + Read256BytesBlockHeightY[k] - 1,
+						Read256BytesBlockHeightY[k]) -
+						dml_floor(ViewportYStart[k], Read256BytesBlockHeightY[k]));
+			} else {
+				swath_width_luma_ub[k] = dml_min(surface_height_ub_l, dml_ceil(SwathWidthY[k] - 1,
+						Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]);
+			}
+			if (BytePerPixC[k] > 0) {
+				if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
+					swath_width_chroma_ub[k] = dml_min(surface_height_ub_c,
+							dml_floor(ViewportYStartC[k] + SwathWidthC[k] +
+									Read256BytesBlockHeightC[k] - 1,
+									Read256BytesBlockHeightC[k]) -
+									dml_floor(ViewportYStartC[k],
+											Read256BytesBlockHeightC[k]));
+				} else {
+					swath_width_chroma_ub[k] = dml_min(surface_height_ub_c,
+							dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) +
+							Read256BytesBlockHeightC[k]);
+				}
+			} else {
+				swath_width_chroma_ub[k] = 0;
+			}
+		}
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d swath_width_luma_ub=%0d\n", __func__, k, swath_width_luma_ub[k]);
+		dml_print("DML::%s: k=%d swath_width_chroma_ub=%0d\n", __func__, k, swath_width_chroma_ub[k]);
+		dml_print("DML::%s: k=%d MaximumSwathHeightY=%0d\n", __func__, k, MaximumSwathHeightY[k]);
+		dml_print("DML::%s: k=%d MaximumSwathHeightC=%0d\n", __func__, k, MaximumSwathHeightC[k]);
+#endif
+
+	}
+} // CalculateSwathWidth
+
+bool dml32_UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal,
+		unsigned int TotalNumberOfActiveDPP,
+		bool NoChroma,
+		enum output_encoder_class Output)
+{
+	bool ret_val = false;
+
+	ret_val = (UseUnboundedRequestingFinal != dm_unbounded_requesting_disable &&
+			TotalNumberOfActiveDPP == 1 && NoChroma);
+	if (UseUnboundedRequestingFinal == dm_unbounded_requesting_edp_only && Output != dm_edp)
+		ret_val = false;
+	return ret_val;
+}
+
+void dml32_CalculateDETBufferSize(
+		unsigned int DETSizeOverride[],
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		bool ForceSingleDPP,
+		unsigned int NumberOfActiveSurfaces,
+		bool UnboundedRequestEnabled,
+		unsigned int nomDETInKByte,
+		unsigned int MaxTotalDETInKByte,
+		unsigned int ConfigReturnBufferSizeInKByte,
+		unsigned int MinCompressedBufferSizeInKByte,
+		unsigned int CompressedBufferSegmentSizeInkByteFinal,
+		enum source_format_class SourcePixelFormat[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		unsigned int RoundedUpMaxSwathSizeBytesY[],
+		unsigned int RoundedUpMaxSwathSizeBytesC[],
+		unsigned int DPPPerSurface[],
+		/* Output */
+		unsigned int DETBufferSizeInKByte[],
+		unsigned int *CompressedBufferSizeInkByte)
+{
+	unsigned int DETBufferSizePoolInKByte;
+	unsigned int NextDETBufferPieceInKByte;
+	bool DETPieceAssignedToThisSurfaceAlready[DC__NUM_DPP__MAX];
+	bool NextPotentialSurfaceToAssignDETPieceFound;
+	unsigned int NextSurfaceToAssignDETPiece;
+	double TotalBandwidth;
+	double BandwidthOfSurfacesNotAssignedDETPiece;
+	unsigned int max_minDET;
+	unsigned int minDET;
+	unsigned int minDET_pipe;
+	unsigned int j, k;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: ForceSingleDPP = %d\n", __func__, ForceSingleDPP);
+	dml_print("DML::%s: nomDETInKByte = %d\n", __func__, nomDETInKByte);
+	dml_print("DML::%s: NumberOfActiveSurfaces = %d\n", __func__, NumberOfActiveSurfaces);
+	dml_print("DML::%s: UnboundedRequestEnabled = %d\n", __func__, UnboundedRequestEnabled);
+	dml_print("DML::%s: MaxTotalDETInKByte = %d\n", __func__, MaxTotalDETInKByte);
+	dml_print("DML::%s: ConfigReturnBufferSizeInKByte = %d\n", __func__, ConfigReturnBufferSizeInKByte);
+	dml_print("DML::%s: MinCompressedBufferSizeInKByte = %d\n", __func__, MinCompressedBufferSizeInKByte);
+	dml_print("DML::%s: CompressedBufferSegmentSizeInkByteFinal = %d\n", __func__,
+			CompressedBufferSegmentSizeInkByteFinal);
+#endif
+
+	// Note: Will use default det size if that fits 2 swaths
+	if (UnboundedRequestEnabled) {
+		if (DETSizeOverride[0] > 0) {
+			DETBufferSizeInKByte[0] = DETSizeOverride[0];
+		} else {
+			DETBufferSizeInKByte[0] = dml_max(nomDETInKByte, dml_ceil(2.0 *
+					((double) RoundedUpMaxSwathSizeBytesY[0] +
+							(double) RoundedUpMaxSwathSizeBytesC[0]) / 1024.0, 64.0));
+		}
+		*CompressedBufferSizeInkByte = ConfigReturnBufferSizeInKByte - DETBufferSizeInKByte[0];
+	} else {
+		DETBufferSizePoolInKByte = MaxTotalDETInKByte;
+		for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+			DETBufferSizeInKByte[k] = nomDETInKByte;
+			if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 ||
+					SourcePixelFormat[k] == dm_420_12) {
+				max_minDET = nomDETInKByte - 64;
+			} else {
+				max_minDET = nomDETInKByte;
+			}
+			minDET = 128;
+			minDET_pipe = 0;
+
+			// add DET resource until can hold 2 full swaths
+			while (minDET <= max_minDET && minDET_pipe == 0) {
+				if (2.0 * ((double) RoundedUpMaxSwathSizeBytesY[k] +
+						(double) RoundedUpMaxSwathSizeBytesC[k]) / 1024.0 <= minDET)
+					minDET_pipe = minDET;
+				minDET = minDET + 64;
+			}
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%0d minDET        = %d\n", __func__, k, minDET);
+			dml_print("DML::%s: k=%0d max_minDET    = %d\n", __func__, k, max_minDET);
+			dml_print("DML::%s: k=%0d minDET_pipe   = %d\n", __func__, k, minDET_pipe);
+			dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesY = %d\n", __func__, k,
+					RoundedUpMaxSwathSizeBytesY[k]);
+			dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesC = %d\n", __func__, k,
+					RoundedUpMaxSwathSizeBytesC[k]);
+#endif
+
+			if (minDET_pipe == 0) {
+				minDET_pipe = dml_max(128, dml_ceil(((double)RoundedUpMaxSwathSizeBytesY[k] +
+						(double)RoundedUpMaxSwathSizeBytesC[k]) / 1024.0, 64));
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: k=%0d minDET_pipe = %d (assume each plane take half DET)\n",
+						__func__, k, minDET_pipe);
+#endif
+			}
+
+			if (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) {
+				DETBufferSizeInKByte[k] = 0;
+			} else if (DETSizeOverride[k] > 0) {
+				DETBufferSizeInKByte[k] = DETSizeOverride[k];
+				DETBufferSizePoolInKByte = DETBufferSizePoolInKByte -
+						(ForceSingleDPP ? 1 : DPPPerSurface[k]) * DETSizeOverride[k];
+			} else if ((ForceSingleDPP ? 1 : DPPPerSurface[k]) * minDET_pipe <= DETBufferSizePoolInKByte) {
+				DETBufferSizeInKByte[k] = minDET_pipe;
+				DETBufferSizePoolInKByte = DETBufferSizePoolInKByte -
+						(ForceSingleDPP ? 1 : DPPPerSurface[k]) * minDET_pipe;
+			}
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%d DPPPerSurface = %d\n", __func__, k, DPPPerSurface[k]);
+			dml_print("DML::%s: k=%d DETSizeOverride = %d\n", __func__, k, DETSizeOverride[k]);
+			dml_print("DML::%s: k=%d DETBufferSizeInKByte = %d\n", __func__, k, DETBufferSizeInKByte[k]);
+			dml_print("DML::%s: DETBufferSizePoolInKByte = %d\n", __func__, DETBufferSizePoolInKByte);
+#endif
+		}
+
+		TotalBandwidth = 0;
+		for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+			if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe)
+				TotalBandwidth = TotalBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
+		}
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: --- Before bandwidth adjustment ---\n", __func__);
+		for (uint k = 0; k < NumberOfActiveSurfaces; ++k)
+			dml_print("DML::%s: k=%d DETBufferSizeInKByte   = %d\n", __func__, k, DETBufferSizeInKByte[k]);
+		dml_print("DML::%s: --- DET allocation with bandwidth ---\n", __func__);
+		dml_print("DML::%s: TotalBandwidth = %f\n", __func__, TotalBandwidth);
+#endif
+		BandwidthOfSurfacesNotAssignedDETPiece = TotalBandwidth;
+		for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+
+			if (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) {
+				DETPieceAssignedToThisSurfaceAlready[k] = true;
+			} else if (DETSizeOverride[k] > 0 || (((double) (ForceSingleDPP ? 1 : DPPPerSurface[k]) *
+					(double) DETBufferSizeInKByte[k] / (double) MaxTotalDETInKByte) >=
+					((ReadBandwidthLuma[k] + ReadBandwidthChroma[k]) / TotalBandwidth))) {
+				DETPieceAssignedToThisSurfaceAlready[k] = true;
+				BandwidthOfSurfacesNotAssignedDETPiece = BandwidthOfSurfacesNotAssignedDETPiece -
+						ReadBandwidthLuma[k] - ReadBandwidthChroma[k];
+			} else {
+				DETPieceAssignedToThisSurfaceAlready[k] = false;
+			}
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%d DETPieceAssignedToThisSurfaceAlready = %d\n", __func__, k,
+					DETPieceAssignedToThisSurfaceAlready[k]);
+			dml_print("DML::%s: k=%d BandwidthOfSurfacesNotAssignedDETPiece = %f\n", __func__, k,
+					BandwidthOfSurfacesNotAssignedDETPiece);
+#endif
+		}
+
+		for (j = 0; j < NumberOfActiveSurfaces; ++j) {
+			NextPotentialSurfaceToAssignDETPieceFound = false;
+			NextSurfaceToAssignDETPiece = 0;
+
+			for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: j=%d k=%d, ReadBandwidthLuma[k] = %f\n", __func__, j, k,
+						ReadBandwidthLuma[k]);
+				dml_print("DML::%s: j=%d k=%d, ReadBandwidthChroma[k] = %f\n", __func__, j, k,
+						ReadBandwidthChroma[k]);
+				dml_print("DML::%s: j=%d k=%d, ReadBandwidthLuma[Next] = %f\n", __func__, j, k,
+						ReadBandwidthLuma[NextSurfaceToAssignDETPiece]);
+				dml_print("DML::%s: j=%d k=%d, ReadBandwidthChroma[Next] = %f\n", __func__, j, k,
+						ReadBandwidthChroma[NextSurfaceToAssignDETPiece]);
+				dml_print("DML::%s: j=%d k=%d, NextSurfaceToAssignDETPiece = %d\n", __func__, j, k,
+						NextSurfaceToAssignDETPiece);
+#endif
+				if (!DETPieceAssignedToThisSurfaceAlready[k] &&
+						(!NextPotentialSurfaceToAssignDETPieceFound ||
+						ReadBandwidthLuma[k] + ReadBandwidthChroma[k] <
+						ReadBandwidthLuma[NextSurfaceToAssignDETPiece] +
+						ReadBandwidthChroma[NextSurfaceToAssignDETPiece])) {
+					NextSurfaceToAssignDETPiece = k;
+					NextPotentialSurfaceToAssignDETPieceFound = true;
+				}
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: j=%d k=%d, DETPieceAssignedToThisSurfaceAlready = %d\n",
+						__func__, j, k, DETPieceAssignedToThisSurfaceAlready[k]);
+				dml_print("DML::%s: j=%d k=%d, NextPotentialSurfaceToAssignDETPieceFound = %d\n",
+						__func__, j, k, NextPotentialSurfaceToAssignDETPieceFound);
+#endif
+			}
+
+			if (NextPotentialSurfaceToAssignDETPieceFound) {
+				// Note: To show the banker's rounding behavior in VBA and also the fact
+				// that the DET buffer size varies due to precision issue
+				//
+				//double tmp1 =  ((double) DETBufferSizePoolInKByte *
+				// (ReadBandwidthLuma[NextSurfaceToAssignDETPiece] +
+				// ReadBandwidthChroma[NextSurfaceToAssignDETPiece]) /
+				// BandwidthOfSurfacesNotAssignedDETPiece /
+				// ((ForceSingleDPP ? 1 : DPPPerSurface[NextSurfaceToAssignDETPiece]) * 64.0));
+				//double tmp2 =  dml_round((double) DETBufferSizePoolInKByte *
+				// (ReadBandwidthLuma[NextSurfaceToAssignDETPiece] +
+				// ReadBandwidthChroma[NextSurfaceToAssignDETPiece]) /
+				 //BandwidthOfSurfacesNotAssignedDETPiece /
+				// ((ForceSingleDPP ? 1 : DPPPerSurface[NextSurfaceToAssignDETPiece]) * 64.0));
+				//
+				//dml_print("DML::%s: j=%d, tmp1 = %f\n", __func__, j, tmp1);
+				//dml_print("DML::%s: j=%d, tmp2 = %f\n", __func__, j, tmp2);
+
+				NextDETBufferPieceInKByte = dml_min(
+					dml_round((double) DETBufferSizePoolInKByte *
+						(ReadBandwidthLuma[NextSurfaceToAssignDETPiece] +
+						ReadBandwidthChroma[NextSurfaceToAssignDETPiece]) /
+						BandwidthOfSurfacesNotAssignedDETPiece /
+						((ForceSingleDPP ? 1 :
+								DPPPerSurface[NextSurfaceToAssignDETPiece]) * 64.0)) *
+						(ForceSingleDPP ? 1 :
+								DPPPerSurface[NextSurfaceToAssignDETPiece]) * 64.0,
+						dml_floor((double) DETBufferSizePoolInKByte,
+						(ForceSingleDPP ? 1 :
+								DPPPerSurface[NextSurfaceToAssignDETPiece]) * 64.0));
+
+				// Above calculation can assign the entire DET buffer allocation to a single pipe.
+				// We should limit the per-pipe DET size to the nominal / max per pipe.
+				if (NextDETBufferPieceInKByte > nomDETInKByte * (ForceSingleDPP ? 1 : DPPPerSurface[k])) {
+					if (DETBufferSizeInKByte[NextSurfaceToAssignDETPiece] <
+							nomDETInKByte * (ForceSingleDPP ? 1 : DPPPerSurface[k])) {
+						NextDETBufferPieceInKByte = nomDETInKByte * (ForceSingleDPP ? 1 : DPPPerSurface[k]) -
+								DETBufferSizeInKByte[NextSurfaceToAssignDETPiece];
+					} else {
+						// Case where DETBufferSizeInKByte[NextSurfaceToAssignDETPiece]
+						// already has the max per-pipe value
+						NextDETBufferPieceInKByte = 0;
+					}
+				}
+
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: j=%0d, DETBufferSizePoolInKByte = %d\n", __func__, j,
+					DETBufferSizePoolInKByte);
+				dml_print("DML::%s: j=%0d, NextSurfaceToAssignDETPiece = %d\n", __func__, j,
+					NextSurfaceToAssignDETPiece);
+				dml_print("DML::%s: j=%0d, ReadBandwidthLuma[%0d] = %f\n", __func__, j,
+					NextSurfaceToAssignDETPiece, ReadBandwidthLuma[NextSurfaceToAssignDETPiece]);
+				dml_print("DML::%s: j=%0d, ReadBandwidthChroma[%0d] = %f\n", __func__, j,
+					NextSurfaceToAssignDETPiece, ReadBandwidthChroma[NextSurfaceToAssignDETPiece]);
+				dml_print("DML::%s: j=%0d, BandwidthOfSurfacesNotAssignedDETPiece = %f\n",
+					__func__, j, BandwidthOfSurfacesNotAssignedDETPiece);
+				dml_print("DML::%s: j=%0d, NextDETBufferPieceInKByte = %d\n", __func__, j,
+					NextDETBufferPieceInKByte);
+				dml_print("DML::%s: j=%0d, DETBufferSizeInKByte[%0d] increases from %0d ",
+					__func__, j, NextSurfaceToAssignDETPiece,
+					DETBufferSizeInKByte[NextSurfaceToAssignDETPiece]);
+#endif
+
+				DETBufferSizeInKByte[NextSurfaceToAssignDETPiece] =
+						DETBufferSizeInKByte[NextSurfaceToAssignDETPiece]
+						+ NextDETBufferPieceInKByte
+						/ (ForceSingleDPP ? 1 : DPPPerSurface[NextSurfaceToAssignDETPiece]);
+#ifdef __DML_VBA_DEBUG__
+				dml_print("to %0d\n", DETBufferSizeInKByte[NextSurfaceToAssignDETPiece]);
+#endif
+
+				DETBufferSizePoolInKByte = DETBufferSizePoolInKByte - NextDETBufferPieceInKByte;
+				DETPieceAssignedToThisSurfaceAlready[NextSurfaceToAssignDETPiece] = true;
+				BandwidthOfSurfacesNotAssignedDETPiece = BandwidthOfSurfacesNotAssignedDETPiece -
+						(ReadBandwidthLuma[NextSurfaceToAssignDETPiece] +
+								ReadBandwidthChroma[NextSurfaceToAssignDETPiece]);
+			}
+		}
+		*CompressedBufferSizeInkByte = MinCompressedBufferSizeInKByte;
+	}
+	*CompressedBufferSizeInkByte = *CompressedBufferSizeInkByte * CompressedBufferSegmentSizeInkByteFinal / 64;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: --- After bandwidth adjustment ---\n", __func__);
+	dml_print("DML::%s: CompressedBufferSizeInkByte = %d\n", __func__, *CompressedBufferSizeInkByte);
+	for (uint k = 0; k < NumberOfActiveSurfaces; ++k) {
+		dml_print("DML::%s: k=%d DETBufferSizeInKByte = %d (TotalReadBandWidth=%f)\n",
+				__func__, k, DETBufferSizeInKByte[k], ReadBandwidthLuma[k] + ReadBandwidthChroma[k]);
+	}
+#endif
+} // CalculateDETBufferSize
+
+void dml32_CalculateODMMode(
+		unsigned int MaximumPixelsPerLinePerDSCUnit,
+		unsigned int HActive,
+		enum output_encoder_class Output,
+		enum odm_combine_policy ODMUse,
+		double StateDispclk,
+		double MaxDispclk,
+		bool DSCEnable,
+		unsigned int TotalNumberOfActiveDPP,
+		unsigned int MaxNumDPP,
+		double PixelClock,
+		double DISPCLKDPPCLKDSCCLKDownSpreading,
+		double DISPCLKRampingMargin,
+		double DISPCLKDPPCLKVCOSpeed,
+
+		/* Output */
+		bool *TotalAvailablePipesSupport,
+		unsigned int *NumberOfDPP,
+		enum odm_combine_mode *ODMMode,
+		double *RequiredDISPCLKPerSurface)
+{
+
+	double SurfaceRequiredDISPCLKWithoutODMCombine;
+	double SurfaceRequiredDISPCLKWithODMCombineTwoToOne;
+	double SurfaceRequiredDISPCLKWithODMCombineFourToOne;
+
+	SurfaceRequiredDISPCLKWithoutODMCombine = dml32_CalculateRequiredDispclk(dm_odm_combine_mode_disabled,
+			PixelClock, DISPCLKDPPCLKDSCCLKDownSpreading, DISPCLKRampingMargin, DISPCLKDPPCLKVCOSpeed,
+			MaxDispclk);
+	SurfaceRequiredDISPCLKWithODMCombineTwoToOne = dml32_CalculateRequiredDispclk(dm_odm_combine_mode_2to1,
+			PixelClock, DISPCLKDPPCLKDSCCLKDownSpreading, DISPCLKRampingMargin, DISPCLKDPPCLKVCOSpeed,
+			MaxDispclk);
+	SurfaceRequiredDISPCLKWithODMCombineFourToOne = dml32_CalculateRequiredDispclk(dm_odm_combine_mode_4to1,
+			PixelClock, DISPCLKDPPCLKDSCCLKDownSpreading, DISPCLKRampingMargin, DISPCLKDPPCLKVCOSpeed,
+			MaxDispclk);
+	*TotalAvailablePipesSupport = true;
+	*ODMMode = dm_odm_combine_mode_disabled; // initialize as disable
+
+	if (ODMUse == dm_odm_combine_policy_none)
+		*ODMMode = dm_odm_combine_mode_disabled;
+
+	*RequiredDISPCLKPerSurface = SurfaceRequiredDISPCLKWithoutODMCombine;
+	*NumberOfDPP = 0;
+
+	// FIXME check ODMUse == "" condition does it mean bypass or Gabriel means something like don't care??
+	// (ODMUse == "" || ODMUse == "CombineAsNeeded")
+
+	if (!(Output == dm_hdmi || Output == dm_dp || Output == dm_edp) && (ODMUse == dm_odm_combine_policy_4to1 ||
+			((SurfaceRequiredDISPCLKWithODMCombineTwoToOne > StateDispclk ||
+					(DSCEnable && (HActive > 2 * MaximumPixelsPerLinePerDSCUnit)))))) {
+		if (TotalNumberOfActiveDPP + 4 <= MaxNumDPP) {
+			*ODMMode = dm_odm_combine_mode_4to1;
+			*RequiredDISPCLKPerSurface = SurfaceRequiredDISPCLKWithODMCombineFourToOne;
+			*NumberOfDPP = 4;
+		} else {
+			*TotalAvailablePipesSupport = false;
+		}
+	} else if (Output != dm_hdmi && (ODMUse == dm_odm_combine_policy_2to1 ||
+			(((SurfaceRequiredDISPCLKWithoutODMCombine > StateDispclk &&
+					SurfaceRequiredDISPCLKWithODMCombineTwoToOne <= StateDispclk) ||
+					(DSCEnable && (HActive > MaximumPixelsPerLinePerDSCUnit)))))) {
+		if (TotalNumberOfActiveDPP + 2 <= MaxNumDPP) {
+			*ODMMode = dm_odm_combine_mode_2to1;
+			*RequiredDISPCLKPerSurface = SurfaceRequiredDISPCLKWithODMCombineTwoToOne;
+			*NumberOfDPP = 2;
+		} else {
+			*TotalAvailablePipesSupport = false;
+		}
+	} else {
+		if (TotalNumberOfActiveDPP + 1 <= MaxNumDPP)
+			*NumberOfDPP = 1;
+		else
+			*TotalAvailablePipesSupport = false;
+	}
+}
+
+double dml32_CalculateRequiredDispclk(
+		enum odm_combine_mode ODMMode,
+		double PixelClock,
+		double DISPCLKDPPCLKDSCCLKDownSpreading,
+		double DISPCLKRampingMargin,
+		double DISPCLKDPPCLKVCOSpeed,
+		double MaxDispclk)
+{
+	double RequiredDispclk = 0.;
+	double PixelClockAfterODM;
+	double DISPCLKWithRampingRoundedToDFSGranularity;
+	double DISPCLKWithoutRampingRoundedToDFSGranularity;
+	double MaxDispclkRoundedDownToDFSGranularity;
+
+	if (ODMMode == dm_odm_combine_mode_4to1)
+		PixelClockAfterODM = PixelClock / 4;
+	else if (ODMMode == dm_odm_combine_mode_2to1)
+		PixelClockAfterODM = PixelClock / 2;
+	else
+		PixelClockAfterODM = PixelClock;
+
+
+	DISPCLKWithRampingRoundedToDFSGranularity = dml32_RoundToDFSGranularity(
+			PixelClockAfterODM * (1 + DISPCLKDPPCLKDSCCLKDownSpreading / 100)
+					* (1 + DISPCLKRampingMargin / 100), 1, DISPCLKDPPCLKVCOSpeed);
+
+	DISPCLKWithoutRampingRoundedToDFSGranularity = dml32_RoundToDFSGranularity(
+			PixelClockAfterODM * (1 + DISPCLKDPPCLKDSCCLKDownSpreading / 100), 1, DISPCLKDPPCLKVCOSpeed);
+
+	MaxDispclkRoundedDownToDFSGranularity = dml32_RoundToDFSGranularity(MaxDispclk, 0, DISPCLKDPPCLKVCOSpeed);
+
+	if (DISPCLKWithoutRampingRoundedToDFSGranularity > MaxDispclkRoundedDownToDFSGranularity)
+		RequiredDispclk = DISPCLKWithoutRampingRoundedToDFSGranularity;
+	else if (DISPCLKWithRampingRoundedToDFSGranularity > MaxDispclkRoundedDownToDFSGranularity)
+		RequiredDispclk = MaxDispclkRoundedDownToDFSGranularity;
+	else
+		RequiredDispclk = DISPCLKWithRampingRoundedToDFSGranularity;
+
+	return RequiredDispclk;
+}
+
+double dml32_RoundToDFSGranularity(double Clock, bool round_up, double VCOSpeed)
+{
+	if (Clock <= 0.0)
+		return 0.0;
+
+	if (round_up)
+		return VCOSpeed * 4.0 / dml_floor(VCOSpeed * 4.0 / Clock, 1.0);
+	else
+		return VCOSpeed * 4.0 / dml_ceil(VCOSpeed * 4.0 / Clock, 1.0);
+}
+
+void dml32_CalculateOutputLink(
+		double PHYCLKPerState,
+		double PHYCLKD18PerState,
+		double PHYCLKD32PerState,
+		double Downspreading,
+		bool IsMainSurfaceUsingTheIndicatedTiming,
+		enum output_encoder_class Output,
+		enum output_format_class OutputFormat,
+		unsigned int HTotal,
+		unsigned int HActive,
+		double PixelClockBackEnd,
+		double ForcedOutputLinkBPP,
+		unsigned int DSCInputBitPerComponent,
+		unsigned int NumberOfDSCSlices,
+		double AudioSampleRate,
+		unsigned int AudioSampleLayout,
+		enum odm_combine_mode ODMModeNoDSC,
+		enum odm_combine_mode ODMModeDSC,
+		bool DSCEnable,
+		unsigned int OutputLinkDPLanes,
+		enum dm_output_link_dp_rate OutputLinkDPRate,
+
+		/* Output */
+		bool *RequiresDSC,
+		double *RequiresFEC,
+		double  *OutBpp,
+		enum dm_output_type *OutputType,
+		enum dm_output_rate *OutputRate,
+		unsigned int *RequiredSlots)
+{
+	bool LinkDSCEnable;
+	unsigned int dummy;
+	*RequiresDSC = false;
+	*RequiresFEC = false;
+	*OutBpp = 0;
+	*OutputType = dm_output_type_unknown;
+	*OutputRate = dm_output_rate_unknown;
+
+	if (IsMainSurfaceUsingTheIndicatedTiming) {
+		if (Output == dm_hdmi) {
+			*RequiresDSC = false;
+			*RequiresFEC = false;
+			*OutBpp = dml32_TruncToValidBPP(dml_min(600, PHYCLKPerState) * 10, 3, HTotal, HActive,
+					PixelClockBackEnd, ForcedOutputLinkBPP, false, Output, OutputFormat,
+					DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout,
+					ODMModeNoDSC, ODMModeDSC, &dummy);
+			//OutputTypeAndRate = "HDMI";
+			*OutputType = dm_output_type_hdmi;
+
+		} else if (Output == dm_dp || Output == dm_dp2p0 || Output == dm_edp) {
+			if (DSCEnable == true) {
+				*RequiresDSC = true;
+				LinkDSCEnable = true;
+				if (Output == dm_dp || Output == dm_dp2p0)
+					*RequiresFEC = true;
+				else
+					*RequiresFEC = false;
+			} else {
+				*RequiresDSC = false;
+				LinkDSCEnable = false;
+				if (Output == dm_dp2p0)
+					*RequiresFEC = true;
+				else
+					*RequiresFEC = false;
+			}
+			if (Output == dm_dp2p0) {
+				*OutBpp = 0;
+				if ((OutputLinkDPRate == dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_uhbr10) &&
+						PHYCLKD32PerState >= 10000 / 32) {
+					*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 10000,
+							OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+							ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat,
+							DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate,
+							AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+					if (*OutBpp == 0 && PHYCLKD32PerState < 13500 / 32 && DSCEnable == true &&
+							ForcedOutputLinkBPP == 0) {
+						*RequiresDSC = true;
+						LinkDSCEnable = true;
+						*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 10000,
+								OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+								ForcedOutputLinkBPP, LinkDSCEnable, Output,
+								OutputFormat, DSCInputBitPerComponent,
+								NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout,
+								ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+					}
+					//OutputTypeAndRate = Output & " UHBR10";
+					*OutputType = dm_output_type_dp2p0;
+					*OutputRate = dm_output_rate_dp_rate_uhbr10;
+				}
+				if ((OutputLinkDPRate == dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_uhbr13p5) &&
+						*OutBpp == 0 && PHYCLKD32PerState >= 13500 / 32) {
+					*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 13500,
+							OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+							ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat,
+							DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate,
+							AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+
+					if (*OutBpp == 0 && PHYCLKD32PerState < 20000 / 32 && DSCEnable == true &&
+							ForcedOutputLinkBPP == 0) {
+						*RequiresDSC = true;
+						LinkDSCEnable = true;
+						*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 13500,
+								OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+								ForcedOutputLinkBPP, LinkDSCEnable, Output,
+								OutputFormat, DSCInputBitPerComponent,
+								NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout,
+								ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+					}
+					//OutputTypeAndRate = Output & " UHBR13p5";
+					*OutputType = dm_output_type_dp2p0;
+					*OutputRate = dm_output_rate_dp_rate_uhbr13p5;
+				}
+				if ((OutputLinkDPRate == dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_uhbr20) &&
+						*OutBpp == 0 && PHYCLKD32PerState >= 20000 / 32) {
+					*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 20000,
+							OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+							ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat,
+							DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate,
+							AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+					if (*OutBpp == 0 && DSCEnable == true && ForcedOutputLinkBPP == 0) {
+						*RequiresDSC = true;
+						LinkDSCEnable = true;
+						*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 20000,
+								OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+								ForcedOutputLinkBPP, LinkDSCEnable, Output,
+								OutputFormat, DSCInputBitPerComponent,
+								NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout,
+								ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+					}
+					//OutputTypeAndRate = Output & " UHBR20";
+					*OutputType = dm_output_type_dp2p0;
+					*OutputRate = dm_output_rate_dp_rate_uhbr20;
+				}
+			} else {
+				*OutBpp = 0;
+				if ((OutputLinkDPRate == dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_hbr) &&
+						PHYCLKPerState >= 270) {
+					*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 2700,
+							OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+							ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat,
+							DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate,
+							AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+					if (*OutBpp == 0 && PHYCLKPerState < 540 && DSCEnable == true &&
+							ForcedOutputLinkBPP == 0) {
+						*RequiresDSC = true;
+						LinkDSCEnable = true;
+						if (Output == dm_dp)
+							*RequiresFEC = true;
+						*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 2700,
+								OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+								ForcedOutputLinkBPP, LinkDSCEnable, Output,
+								OutputFormat, DSCInputBitPerComponent,
+								NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout,
+								ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+					}
+					//OutputTypeAndRate = Output & " HBR";
+					*OutputType = (Output == dm_dp) ? dm_output_type_dp : dm_output_type_edp;
+					*OutputRate = dm_output_rate_dp_rate_hbr;
+				}
+				if ((OutputLinkDPRate == dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_hbr2) &&
+						*OutBpp == 0 && PHYCLKPerState >= 540) {
+					*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 5400,
+							OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+							ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat,
+							DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate,
+							AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+
+					if (*OutBpp == 0 && PHYCLKPerState < 810 && DSCEnable == true &&
+							ForcedOutputLinkBPP == 0) {
+						*RequiresDSC = true;
+						LinkDSCEnable = true;
+						if (Output == dm_dp)
+							*RequiresFEC = true;
+
+						*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 5400,
+								OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+								ForcedOutputLinkBPP, LinkDSCEnable, Output,
+								OutputFormat, DSCInputBitPerComponent,
+								NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout,
+								ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+					}
+					//OutputTypeAndRate = Output & " HBR2";
+					*OutputType = (Output == dm_dp) ? dm_output_type_dp : dm_output_type_edp;
+					*OutputRate = dm_output_rate_dp_rate_hbr2;
+				}
+				if ((OutputLinkDPRate == dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_hbr3) && *OutBpp == 0 && PHYCLKPerState >= 810) {
+					*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 8100,
+							OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+							ForcedOutputLinkBPP, LinkDSCEnable, Output,
+							OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices,
+							AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC,
+							RequiredSlots);
+
+					if (*OutBpp == 0 && DSCEnable == true && ForcedOutputLinkBPP == 0) {
+						*RequiresDSC = true;
+						LinkDSCEnable = true;
+						if (Output == dm_dp)
+							*RequiresFEC = true;
+
+						*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 8100,
+								OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+								ForcedOutputLinkBPP, LinkDSCEnable, Output,
+								OutputFormat, DSCInputBitPerComponent,
+								NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout,
+								ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+					}
+					//OutputTypeAndRate = Output & " HBR3";
+					*OutputType = (Output == dm_dp) ? dm_output_type_dp : dm_output_type_edp;
+					*OutputRate = dm_output_rate_dp_rate_hbr3;
+				}
+			}
+		}
+	}
+}
+
+void dml32_CalculateDPPCLK(
+		unsigned int NumberOfActiveSurfaces,
+		double DISPCLKDPPCLKDSCCLKDownSpreading,
+		double DISPCLKDPPCLKVCOSpeed,
+		double DPPCLKUsingSingleDPP[],
+		unsigned int DPPPerSurface[],
+
+		/* output */
+		double *GlobalDPPCLK,
+		double Dppclk[])
+{
+	unsigned int k;
+	*GlobalDPPCLK = 0;
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		Dppclk[k] = DPPCLKUsingSingleDPP[k] / DPPPerSurface[k] * (1 + DISPCLKDPPCLKDSCCLKDownSpreading / 100);
+		*GlobalDPPCLK = dml_max(*GlobalDPPCLK, Dppclk[k]);
+	}
+	*GlobalDPPCLK = dml32_RoundToDFSGranularity(*GlobalDPPCLK, 1, DISPCLKDPPCLKVCOSpeed);
+	for (k = 0; k < NumberOfActiveSurfaces; ++k)
+		Dppclk[k] = *GlobalDPPCLK / 255 * dml_ceil(Dppclk[k] * 255.0 / *GlobalDPPCLK, 1.0);
+}
+
+double dml32_TruncToValidBPP(
+		double LinkBitRate,
+		unsigned int Lanes,
+		unsigned int HTotal,
+		unsigned int HActive,
+		double PixelClock,
+		double DesiredBPP,
+		bool DSCEnable,
+		enum output_encoder_class Output,
+		enum output_format_class Format,
+		unsigned int DSCInputBitPerComponent,
+		unsigned int DSCSlices,
+		unsigned int AudioRate,
+		unsigned int AudioLayout,
+		enum odm_combine_mode ODMModeNoDSC,
+		enum odm_combine_mode ODMModeDSC,
+		/* Output */
+		unsigned int *RequiredSlots)
+{
+	double    MaxLinkBPP;
+	unsigned int   MinDSCBPP;
+	double    MaxDSCBPP;
+	unsigned int   NonDSCBPP0;
+	unsigned int   NonDSCBPP1;
+	unsigned int   NonDSCBPP2;
+	unsigned int   NonDSCBPP3;
+
+	if (Format == dm_420) {
+		NonDSCBPP0 = 12;
+		NonDSCBPP1 = 15;
+		NonDSCBPP2 = 18;
+		MinDSCBPP = 6;
+		MaxDSCBPP = 1.5 * DSCInputBitPerComponent - 1 / 16;
+	} else if (Format == dm_444) {
+		NonDSCBPP0 = 18;
+		NonDSCBPP1 = 24;
+		NonDSCBPP2 = 30;
+		NonDSCBPP3 = 36;
+		MinDSCBPP = 8;
+		MaxDSCBPP = 3 * DSCInputBitPerComponent - 1.0 / 16;
+	} else {
+		if (Output == dm_hdmi) {
+			NonDSCBPP0 = 24;
+			NonDSCBPP1 = 24;
+			NonDSCBPP2 = 24;
+		} else {
+			NonDSCBPP0 = 16;
+			NonDSCBPP1 = 20;
+			NonDSCBPP2 = 24;
+		}
+		if (Format == dm_n422) {
+			MinDSCBPP = 7;
+			MaxDSCBPP = 2 * DSCInputBitPerComponent - 1.0 / 16.0;
+		} else {
+			MinDSCBPP = 8;
+			MaxDSCBPP = 3 * DSCInputBitPerComponent - 1.0 / 16.0;
+		}
+	}
+	if (Output == dm_dp2p0) {
+		MaxLinkBPP = LinkBitRate * Lanes / PixelClock * 128 / 132 * 383 / 384 * 65536 / 65540;
+	} else if (DSCEnable && Output == dm_dp) {
+		MaxLinkBPP = LinkBitRate / 10 * 8 * Lanes / PixelClock * (1 - 2.4 / 100);
+	} else {
+		MaxLinkBPP = LinkBitRate / 10 * 8 * Lanes / PixelClock;
+	}
+
+	if (DSCEnable) {
+		if (ODMModeDSC == dm_odm_combine_mode_4to1)
+			MaxLinkBPP = dml_min(MaxLinkBPP, 16);
+		else if (ODMModeDSC == dm_odm_combine_mode_2to1)
+			MaxLinkBPP = dml_min(MaxLinkBPP, 32);
+		else if (ODMModeDSC == dm_odm_split_mode_1to2)
+			MaxLinkBPP = 2 * MaxLinkBPP;
+	} else {
+		if (ODMModeNoDSC == dm_odm_combine_mode_4to1)
+			MaxLinkBPP = dml_min(MaxLinkBPP, 16);
+		else if (ODMModeNoDSC == dm_odm_combine_mode_2to1)
+			MaxLinkBPP = dml_min(MaxLinkBPP, 32);
+		else if (ODMModeNoDSC == dm_odm_split_mode_1to2)
+			MaxLinkBPP = 2 * MaxLinkBPP;
+	}
+
+	if (DesiredBPP == 0) {
+		if (DSCEnable) {
+			if (MaxLinkBPP < MinDSCBPP)
+				return BPP_INVALID;
+			else if (MaxLinkBPP >= MaxDSCBPP)
+				return MaxDSCBPP;
+			else
+				return dml_floor(16.0 * MaxLinkBPP, 1.0) / 16.0;
+		} else {
+			if (MaxLinkBPP >= NonDSCBPP3)
+				return NonDSCBPP3;
+			else if (MaxLinkBPP >= NonDSCBPP2)
+				return NonDSCBPP2;
+			else if (MaxLinkBPP >= NonDSCBPP1)
+				return NonDSCBPP1;
+			else if (MaxLinkBPP >= NonDSCBPP0)
+				return 16.0;
+			else
+				return BPP_INVALID;
+		}
+	} else {
+		if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 ||
+				DesiredBPP == NonDSCBPP0 || DesiredBPP == NonDSCBPP3)) ||
+				(DSCEnable && DesiredBPP >= MinDSCBPP && DesiredBPP <= MaxDSCBPP)))
+			return BPP_INVALID;
+		else
+			return DesiredBPP;
+	}
+
+	*RequiredSlots = dml_ceil(DesiredBPP / MaxLinkBPP * 64, 1);
+
+	return BPP_INVALID;
+} // TruncToValidBPP
+
+double dml32_RequiredDTBCLK(
+		bool              DSCEnable,
+		double               PixelClock,
+		enum output_format_class  OutputFormat,
+		double               OutputBpp,
+		unsigned int              DSCSlices,
+		unsigned int                 HTotal,
+		unsigned int                 HActive,
+		unsigned int              AudioRate,
+		unsigned int              AudioLayout)
+{
+	double PixelWordRate = PixelClock /  (OutputFormat == dm_444 ? 1 : 2);
+	double HCActive = dml_ceil(DSCSlices * dml_ceil(OutputBpp *
+			dml_ceil(HActive / DSCSlices, 1) / 8.0, 1) / 3.0, 1);
+	double HCBlank = 64 + 32 *
+			dml_ceil(AudioRate *  (AudioLayout == 1 ? 1 : 0.25) * HTotal / (PixelClock * 1000), 1);
+	double AverageTribyteRate = PixelWordRate * (HCActive + HCBlank) / HTotal;
+	double HActiveTribyteRate = PixelWordRate * HCActive / HActive;
+
+	if (DSCEnable != true)
+		return dml_max(PixelClock / 4.0 * OutputBpp / 24.0, 25.0);
+
+	return dml_max4(PixelWordRate / 4.0, AverageTribyteRate / 4.0, HActiveTribyteRate / 4.0, 25.0) * 1.002;
+}
+
+unsigned int dml32_DSCDelayRequirement(bool DSCEnabled,
+		enum odm_combine_mode ODMMode,
+		unsigned int DSCInputBitPerComponent,
+		double OutputBpp,
+		unsigned int HActive,
+		unsigned int HTotal,
+		unsigned int NumberOfDSCSlices,
+		enum output_format_class  OutputFormat,
+		enum output_encoder_class Output,
+		double PixelClock,
+		double PixelClockBackEnd)
+{
+	unsigned int DSCDelayRequirement_val;
+
+	if (DSCEnabled == true && OutputBpp != 0) {
+		if (ODMMode == dm_odm_combine_mode_4to1) {
+			DSCDelayRequirement_val = 4 * (dml32_dscceComputeDelay(DSCInputBitPerComponent, OutputBpp,
+					dml_ceil(HActive / NumberOfDSCSlices, 1), NumberOfDSCSlices / 4,
+					OutputFormat, Output) + dml32_dscComputeDelay(OutputFormat, Output));
+		} else if (ODMMode == dm_odm_combine_mode_2to1) {
+			DSCDelayRequirement_val = 2 * (dml32_dscceComputeDelay(DSCInputBitPerComponent, OutputBpp,
+					dml_ceil(HActive / NumberOfDSCSlices, 1), NumberOfDSCSlices / 2,
+					OutputFormat, Output) + dml32_dscComputeDelay(OutputFormat, Output));
+		} else {
+			DSCDelayRequirement_val = dml32_dscceComputeDelay(DSCInputBitPerComponent, OutputBpp,
+					dml_ceil(HActive / NumberOfDSCSlices, 1), NumberOfDSCSlices,
+					OutputFormat, Output) + dml32_dscComputeDelay(OutputFormat, Output);
+		}
+
+		DSCDelayRequirement_val = DSCDelayRequirement_val + (HTotal - HActive) *
+				dml_ceil(DSCDelayRequirement_val / HActive, 1);
+
+		DSCDelayRequirement_val = DSCDelayRequirement_val * PixelClock / PixelClockBackEnd;
+
+	} else {
+		DSCDelayRequirement_val = 0;
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DSCEnabled              = %d\n", __func__, DSCEnabled);
+	dml_print("DML::%s: OutputBpp               = %f\n", __func__, OutputBpp);
+	dml_print("DML::%s: HActive                 = %d\n", __func__, HActive);
+	dml_print("DML::%s: OutputFormat            = %d\n", __func__, OutputFormat);
+	dml_print("DML::%s: DSCInputBitPerComponent = %d\n", __func__, DSCInputBitPerComponent);
+	dml_print("DML::%s: NumberOfDSCSlices       = %d\n", __func__, NumberOfDSCSlices);
+	dml_print("DML::%s: DSCDelayRequirement_val = %d\n", __func__, DSCDelayRequirement_val);
+#endif
+
+	return DSCDelayRequirement_val;
+}
+
+void dml32_CalculateSurfaceSizeInMall(
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int MALLAllocatedForDCN,
+		enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[],
+		bool DCCEnable[],
+		bool ViewportStationary[],
+		unsigned int ViewportXStartY[],
+		unsigned int ViewportYStartY[],
+		unsigned int ViewportXStartC[],
+		unsigned int ViewportYStartC[],
+		unsigned int ViewportWidthY[],
+		unsigned int ViewportHeightY[],
+		unsigned int BytesPerPixelY[],
+		unsigned int ViewportWidthC[],
+		unsigned int ViewportHeightC[],
+		unsigned int BytesPerPixelC[],
+		unsigned int SurfaceWidthY[],
+		unsigned int SurfaceWidthC[],
+		unsigned int SurfaceHeightY[],
+		unsigned int SurfaceHeightC[],
+		unsigned int Read256BytesBlockWidthY[],
+		unsigned int Read256BytesBlockWidthC[],
+		unsigned int Read256BytesBlockHeightY[],
+		unsigned int Read256BytesBlockHeightC[],
+		unsigned int ReadBlockWidthY[],
+		unsigned int ReadBlockWidthC[],
+		unsigned int ReadBlockHeightY[],
+		unsigned int ReadBlockHeightC[],
+
+		/* Output */
+		unsigned int    SurfaceSizeInMALL[],
+		bool *ExceededMALLSize)
+{
+	unsigned int TotalSurfaceSizeInMALL  = 0;
+	unsigned int k;
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (ViewportStationary[k]) {
+			SurfaceSizeInMALL[k] = dml_min(dml_ceil(SurfaceWidthY[k], ReadBlockWidthY[k]),
+					dml_floor(ViewportXStartY[k] + ViewportWidthY[k] + ReadBlockWidthY[k] - 1,
+						ReadBlockWidthY[k]) - dml_floor(ViewportXStartY[k],
+						ReadBlockWidthY[k])) * dml_min(dml_ceil(SurfaceHeightY[k],
+						ReadBlockHeightY[k]), dml_floor(ViewportYStartY[k] +
+						ViewportHeightY[k] + ReadBlockHeightY[k] - 1, ReadBlockHeightY[k]) -
+						dml_floor(ViewportYStartY[k], ReadBlockHeightY[k])) * BytesPerPixelY[k];
+
+			if (ReadBlockWidthC[k] > 0) {
+				SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
+						dml_min(dml_ceil(SurfaceWidthC[k], ReadBlockWidthC[k]),
+							dml_floor(ViewportXStartC[k] + ViewportWidthC[k] +
+							ReadBlockWidthC[k] - 1, ReadBlockWidthC[k]) -
+							dml_floor(ViewportXStartC[k], ReadBlockWidthC[k])) *
+							dml_min(dml_ceil(SurfaceHeightC[k], ReadBlockHeightC[k]),
+							dml_floor(ViewportYStartC[k] + ViewportHeightC[k] +
+							ReadBlockHeightC[k] - 1, ReadBlockHeightC[k]) -
+							dml_floor(ViewportYStartC[k], ReadBlockHeightC[k])) *
+							BytesPerPixelC[k];
+			}
+			if (DCCEnable[k] == true) {
+				SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
+						dml_min(dml_ceil(SurfaceWidthY[k], 8 * Read256BytesBlockWidthY[k]),
+							dml_floor(ViewportXStartY[k] + ViewportWidthY[k] + 8 *
+							Read256BytesBlockWidthY[k] - 1, 8 * Read256BytesBlockWidthY[k])
+							- dml_floor(ViewportXStartY[k], 8 * Read256BytesBlockWidthY[k]))
+							* dml_min(dml_ceil(SurfaceHeightY[k], 8 *
+							Read256BytesBlockHeightY[k]), dml_floor(ViewportYStartY[k] +
+							ViewportHeightY[k] + 8 * Read256BytesBlockHeightY[k] - 1, 8 *
+							Read256BytesBlockHeightY[k]) - dml_floor(ViewportYStartY[k], 8
+							* Read256BytesBlockHeightY[k])) * BytesPerPixelY[k] / 256;
+				if (Read256BytesBlockWidthC[k] > 0) {
+					SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
+							dml_min(dml_ceil(SurfaceWidthC[k], 8 *
+								Read256BytesBlockWidthC[k]),
+								dml_floor(ViewportXStartC[k] + ViewportWidthC[k] + 8
+								* Read256BytesBlockWidthC[k] - 1, 8 *
+								Read256BytesBlockWidthC[k]) -
+								dml_floor(ViewportXStartC[k], 8 *
+								Read256BytesBlockWidthC[k])) *
+								dml_min(dml_ceil(SurfaceHeightC[k], 8 *
+								Read256BytesBlockHeightC[k]),
+								dml_floor(ViewportYStartC[k] + ViewportHeightC[k] +
+								8 * Read256BytesBlockHeightC[k] - 1, 8 *
+								Read256BytesBlockHeightC[k]) -
+								dml_floor(ViewportYStartC[k], 8 *
+								Read256BytesBlockHeightC[k])) *
+								BytesPerPixelC[k] / 256;
+				}
+			}
+		} else {
+			SurfaceSizeInMALL[k] = dml_ceil(dml_min(SurfaceWidthY[k], ViewportWidthY[k] +
+					ReadBlockWidthY[k] - 1), ReadBlockWidthY[k]) *
+					dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] +
+							ReadBlockHeightY[k] - 1), ReadBlockHeightY[k]) *
+							BytesPerPixelY[k];
+			if (ReadBlockWidthC[k] > 0) {
+				SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
+						dml_ceil(dml_min(SurfaceWidthC[k], ViewportWidthC[k] +
+								ReadBlockWidthC[k] - 1), ReadBlockWidthC[k]) *
+						dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] +
+								ReadBlockHeightC[k] - 1), ReadBlockHeightC[k]) *
+								BytesPerPixelC[k];
+			}
+			if (DCCEnable[k] == true) {
+				SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
+						dml_ceil(dml_min(SurfaceWidthY[k], ViewportWidthY[k] + 8 *
+								Read256BytesBlockWidthY[k] - 1), 8 *
+								Read256BytesBlockWidthY[k]) *
+						dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] + 8 *
+								Read256BytesBlockHeightY[k] - 1), 8 *
+								Read256BytesBlockHeightY[k]) * BytesPerPixelY[k] / 256;
+
+				if (Read256BytesBlockWidthC[k] > 0) {
+					SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
+							dml_ceil(dml_min(SurfaceWidthC[k], ViewportWidthC[k] + 8 *
+									Read256BytesBlockWidthC[k] - 1), 8 *
+									Read256BytesBlockWidthC[k]) *
+							dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] + 8 *
+									Read256BytesBlockHeightC[k] - 1), 8 *
+									Read256BytesBlockHeightC[k]) *
+									BytesPerPixelC[k] / 256;
+				}
+			}
+		}
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (UseMALLForStaticScreen[k] == dm_use_mall_static_screen_enable)
+			TotalSurfaceSizeInMALL = TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k];
+	}
+	*ExceededMALLSize =  (TotalSurfaceSizeInMALL <= MALLAllocatedForDCN * 1024 * 1024 ? false : true);
+} // CalculateSurfaceSizeInMall
+
+void dml32_CalculateVMRowAndSwath(
+		unsigned int NumberOfActiveSurfaces,
+		DmlPipe myPipe[],
+		unsigned int SurfaceSizeInMALL[],
+		unsigned int PTEBufferSizeInRequestsLuma,
+		unsigned int PTEBufferSizeInRequestsChroma,
+		unsigned int DCCMetaBufferSizeBytes,
+		enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[],
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		unsigned int MALLAllocatedForDCN,
+		double SwathWidthY[],
+		double SwathWidthC[],
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		unsigned int GPUVMMaxPageTableLevels,
+		unsigned int GPUVMMinPageSizeKBytes[],
+		unsigned int HostVMMinPageSize,
+
+		/* Output */
+		bool PTEBufferSizeNotExceeded[],
+		bool DCCMetaBufferSizeNotExceeded[],
+		unsigned int dpte_row_width_luma_ub[],
+		unsigned int dpte_row_width_chroma_ub[],
+		unsigned int dpte_row_height_luma[],
+		unsigned int dpte_row_height_chroma[],
+		unsigned int dpte_row_height_linear_luma[],     // VBA_DELTA
+		unsigned int dpte_row_height_linear_chroma[],   // VBA_DELTA
+		unsigned int meta_req_width[],
+		unsigned int meta_req_width_chroma[],
+		unsigned int meta_req_height[],
+		unsigned int meta_req_height_chroma[],
+		unsigned int meta_row_width[],
+		unsigned int meta_row_width_chroma[],
+		unsigned int meta_row_height[],
+		unsigned int meta_row_height_chroma[],
+		unsigned int vm_group_bytes[],
+		unsigned int dpte_group_bytes[],
+		unsigned int PixelPTEReqWidthY[],
+		unsigned int PixelPTEReqHeightY[],
+		unsigned int PTERequestSizeY[],
+		unsigned int PixelPTEReqWidthC[],
+		unsigned int PixelPTEReqHeightC[],
+		unsigned int PTERequestSizeC[],
+		unsigned int dpde0_bytes_per_frame_ub_l[],
+		unsigned int meta_pte_bytes_per_frame_ub_l[],
+		unsigned int dpde0_bytes_per_frame_ub_c[],
+		unsigned int meta_pte_bytes_per_frame_ub_c[],
+		double PrefetchSourceLinesY[],
+		double PrefetchSourceLinesC[],
+		double VInitPreFillY[],
+		double VInitPreFillC[],
+		unsigned int MaxNumSwathY[],
+		unsigned int MaxNumSwathC[],
+		double meta_row_bw[],
+		double dpte_row_bw[],
+		double PixelPTEBytesPerRow[],
+		double PDEAndMetaPTEBytesFrame[],
+		double MetaRowByte[],
+		bool use_one_row_for_frame[],
+		bool use_one_row_for_frame_flip[],
+		bool UsesMALLForStaticScreen[],
+		bool PTE_BUFFER_MODE[],
+		unsigned int BIGK_FRAGMENT_SIZE[])
+{
+	unsigned int k;
+	unsigned int PTEBufferSizeInRequestsForLuma[DC__NUM_DPP__MAX];
+	unsigned int PTEBufferSizeInRequestsForChroma[DC__NUM_DPP__MAX];
+	unsigned int PDEAndMetaPTEBytesFrameY;
+	unsigned int PDEAndMetaPTEBytesFrameC;
+	unsigned int MetaRowByteY[DC__NUM_DPP__MAX];
+	unsigned int MetaRowByteC[DC__NUM_DPP__MAX];
+	unsigned int PixelPTEBytesPerRowY[DC__NUM_DPP__MAX];
+	unsigned int PixelPTEBytesPerRowC[DC__NUM_DPP__MAX];
+	unsigned int PixelPTEBytesPerRowY_one_row_per_frame[DC__NUM_DPP__MAX];
+	unsigned int PixelPTEBytesPerRowC_one_row_per_frame[DC__NUM_DPP__MAX];
+	unsigned int dpte_row_width_luma_ub_one_row_per_frame[DC__NUM_DPP__MAX];
+	unsigned int dpte_row_height_luma_one_row_per_frame[DC__NUM_DPP__MAX];
+	unsigned int dpte_row_width_chroma_ub_one_row_per_frame[DC__NUM_DPP__MAX];
+	unsigned int dpte_row_height_chroma_one_row_per_frame[DC__NUM_DPP__MAX];
+	bool one_row_per_frame_fits_in_buffer[DC__NUM_DPP__MAX];
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (HostVMEnable == true) {
+			vm_group_bytes[k] = 512;
+			dpte_group_bytes[k] = 512;
+		} else if (GPUVMEnable == true) {
+			vm_group_bytes[k] = 2048;
+			if (GPUVMMinPageSizeKBytes[k] >= 64 && IsVertical(myPipe[k].SourceRotation))
+				dpte_group_bytes[k] = 512;
+			else
+				dpte_group_bytes[k] = 2048;
+		} else {
+			vm_group_bytes[k] = 0;
+			dpte_group_bytes[k] = 0;
+		}
+
+		if (myPipe[k].SourcePixelFormat == dm_420_8 || myPipe[k].SourcePixelFormat == dm_420_10 ||
+				myPipe[k].SourcePixelFormat == dm_420_12 ||
+				myPipe[k].SourcePixelFormat == dm_rgbe_alpha) {
+			if ((myPipe[k].SourcePixelFormat == dm_420_10 || myPipe[k].SourcePixelFormat == dm_420_12) &&
+					!IsVertical(myPipe[k].SourceRotation)) {
+				PTEBufferSizeInRequestsForLuma[k] =
+						(PTEBufferSizeInRequestsLuma + PTEBufferSizeInRequestsChroma) / 2;
+				PTEBufferSizeInRequestsForChroma[k] = PTEBufferSizeInRequestsForLuma[k];
+			} else {
+				PTEBufferSizeInRequestsForLuma[k] = PTEBufferSizeInRequestsLuma;
+				PTEBufferSizeInRequestsForChroma[k] = PTEBufferSizeInRequestsChroma;
+			}
+
+			PDEAndMetaPTEBytesFrameC = dml32_CalculateVMAndRowBytes(
+					myPipe[k].ViewportStationary,
+					myPipe[k].DCCEnable,
+					myPipe[k].DPPPerSurface,
+					myPipe[k].BlockHeight256BytesC,
+					myPipe[k].BlockWidth256BytesC,
+					myPipe[k].SourcePixelFormat,
+					myPipe[k].SurfaceTiling,
+					myPipe[k].BytePerPixelC,
+					myPipe[k].SourceRotation,
+					SwathWidthC[k],
+					myPipe[k].ViewportHeightChroma,
+					myPipe[k].ViewportXStartC,
+					myPipe[k].ViewportYStartC,
+					GPUVMEnable,
+					HostVMEnable,
+					HostVMMaxNonCachedPageTableLevels,
+					GPUVMMaxPageTableLevels,
+					GPUVMMinPageSizeKBytes[k],
+					HostVMMinPageSize,
+					PTEBufferSizeInRequestsForChroma[k],
+					myPipe[k].PitchC,
+					myPipe[k].DCCMetaPitchC,
+					myPipe[k].BlockWidthC,
+					myPipe[k].BlockHeightC,
+
+					/* Output */
+					&MetaRowByteC[k],
+					&PixelPTEBytesPerRowC[k],
+					&dpte_row_width_chroma_ub[k],
+					&dpte_row_height_chroma[k],
+					&dpte_row_height_linear_chroma[k],
+					&PixelPTEBytesPerRowC_one_row_per_frame[k],
+					&dpte_row_width_chroma_ub_one_row_per_frame[k],
+					&dpte_row_height_chroma_one_row_per_frame[k],
+					&meta_req_width_chroma[k],
+					&meta_req_height_chroma[k],
+					&meta_row_width_chroma[k],
+					&meta_row_height_chroma[k],
+					&PixelPTEReqWidthC[k],
+					&PixelPTEReqHeightC[k],
+					&PTERequestSizeC[k],
+					&dpde0_bytes_per_frame_ub_c[k],
+					&meta_pte_bytes_per_frame_ub_c[k]);
+
+			PrefetchSourceLinesC[k] = dml32_CalculatePrefetchSourceLines(
+					myPipe[k].VRatioChroma,
+					myPipe[k].VTapsChroma,
+					myPipe[k].InterlaceEnable,
+					myPipe[k].ProgressiveToInterlaceUnitInOPP,
+					myPipe[k].SwathHeightC,
+					myPipe[k].SourceRotation,
+					myPipe[k].ViewportStationary,
+					SwathWidthC[k],
+					myPipe[k].ViewportHeightChroma,
+					myPipe[k].ViewportXStartC,
+					myPipe[k].ViewportYStartC,
+
+					/* Output */
+					&VInitPreFillC[k],
+					&MaxNumSwathC[k]);
+		} else {
+			PTEBufferSizeInRequestsForLuma[k] = PTEBufferSizeInRequestsLuma + PTEBufferSizeInRequestsChroma;
+			PTEBufferSizeInRequestsForChroma[k] = 0;
+			PixelPTEBytesPerRowC[k] = 0;
+			PDEAndMetaPTEBytesFrameC = 0;
+			MetaRowByteC[k] = 0;
+			MaxNumSwathC[k] = 0;
+			PrefetchSourceLinesC[k] = 0;
+			dpte_row_height_chroma_one_row_per_frame[k] = 0;
+			dpte_row_width_chroma_ub_one_row_per_frame[k] = 0;
+			PixelPTEBytesPerRowC_one_row_per_frame[k] = 0;
+		}
+
+		PDEAndMetaPTEBytesFrameY = dml32_CalculateVMAndRowBytes(
+				myPipe[k].ViewportStationary,
+				myPipe[k].DCCEnable,
+				myPipe[k].DPPPerSurface,
+				myPipe[k].BlockHeight256BytesY,
+				myPipe[k].BlockWidth256BytesY,
+				myPipe[k].SourcePixelFormat,
+				myPipe[k].SurfaceTiling,
+				myPipe[k].BytePerPixelY,
+				myPipe[k].SourceRotation,
+				SwathWidthY[k],
+				myPipe[k].ViewportHeight,
+				myPipe[k].ViewportXStart,
+				myPipe[k].ViewportYStart,
+				GPUVMEnable,
+				HostVMEnable,
+				HostVMMaxNonCachedPageTableLevels,
+				GPUVMMaxPageTableLevels,
+				GPUVMMinPageSizeKBytes[k],
+				HostVMMinPageSize,
+				PTEBufferSizeInRequestsForLuma[k],
+				myPipe[k].PitchY,
+				myPipe[k].DCCMetaPitchY,
+				myPipe[k].BlockWidthY,
+				myPipe[k].BlockHeightY,
+
+				/* Output */
+				&MetaRowByteY[k],
+				&PixelPTEBytesPerRowY[k],
+				&dpte_row_width_luma_ub[k],
+				&dpte_row_height_luma[k],
+				&dpte_row_height_linear_luma[k],
+				&PixelPTEBytesPerRowY_one_row_per_frame[k],
+				&dpte_row_width_luma_ub_one_row_per_frame[k],
+				&dpte_row_height_luma_one_row_per_frame[k],
+				&meta_req_width[k],
+				&meta_req_height[k],
+				&meta_row_width[k],
+				&meta_row_height[k],
+				&PixelPTEReqWidthY[k],
+				&PixelPTEReqHeightY[k],
+				&PTERequestSizeY[k],
+				&dpde0_bytes_per_frame_ub_l[k],
+				&meta_pte_bytes_per_frame_ub_l[k]);
+
+		PrefetchSourceLinesY[k] = dml32_CalculatePrefetchSourceLines(
+				myPipe[k].VRatio,
+				myPipe[k].VTaps,
+				myPipe[k].InterlaceEnable,
+				myPipe[k].ProgressiveToInterlaceUnitInOPP,
+				myPipe[k].SwathHeightY,
+				myPipe[k].SourceRotation,
+				myPipe[k].ViewportStationary,
+				SwathWidthY[k],
+				myPipe[k].ViewportHeight,
+				myPipe[k].ViewportXStart,
+				myPipe[k].ViewportYStart,
+
+				/* Output */
+				&VInitPreFillY[k],
+				&MaxNumSwathY[k]);
+
+		PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY + PDEAndMetaPTEBytesFrameC;
+		MetaRowByte[k] = MetaRowByteY[k] + MetaRowByteC[k];
+
+		if (PixelPTEBytesPerRowY[k] <= 64 * PTEBufferSizeInRequestsForLuma[k] &&
+				PixelPTEBytesPerRowC[k] <= 64 * PTEBufferSizeInRequestsForChroma[k]) {
+			PTEBufferSizeNotExceeded[k] = true;
+		} else {
+			PTEBufferSizeNotExceeded[k] = false;
+		}
+
+		one_row_per_frame_fits_in_buffer[k] = (PixelPTEBytesPerRowY_one_row_per_frame[k] <= 64 * 2 *
+			PTEBufferSizeInRequestsForLuma[k] &&
+			PixelPTEBytesPerRowC_one_row_per_frame[k] <= 64 * 2 * PTEBufferSizeInRequestsForChroma[k]);
+	}
+
+	dml32_CalculateMALLUseForStaticScreen(
+			NumberOfActiveSurfaces,
+			MALLAllocatedForDCN,
+			UseMALLForStaticScreen,   // mode
+			SurfaceSizeInMALL,
+			one_row_per_frame_fits_in_buffer,
+			/* Output */
+			UsesMALLForStaticScreen); // boolen
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		PTE_BUFFER_MODE[k] = myPipe[k].FORCE_ONE_ROW_FOR_FRAME || UsesMALLForStaticScreen[k] ||
+				(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport) ||
+				(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) ||
+				(GPUVMMinPageSizeKBytes[k] > 64);
+		BIGK_FRAGMENT_SIZE[k] = dml_log2(GPUVMMinPageSizeKBytes[k] * 1024) - 12;
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, SurfaceSizeInMALL = %d\n",  __func__, k, SurfaceSizeInMALL[k]);
+		dml_print("DML::%s: k=%d, UsesMALLForStaticScreen = %d\n",  __func__, k, UsesMALLForStaticScreen[k]);
+#endif
+		use_one_row_for_frame[k] = myPipe[k].FORCE_ONE_ROW_FOR_FRAME || UsesMALLForStaticScreen[k] ||
+				(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport) ||
+				(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) ||
+				(GPUVMMinPageSizeKBytes[k] > 64 && IsVertical(myPipe[k].SourceRotation));
+
+		use_one_row_for_frame_flip[k] = use_one_row_for_frame[k] &&
+				!(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame);
+
+		if (use_one_row_for_frame[k]) {
+			dpte_row_height_luma[k] = dpte_row_height_luma_one_row_per_frame[k];
+			dpte_row_width_luma_ub[k] = dpte_row_width_luma_ub_one_row_per_frame[k];
+			PixelPTEBytesPerRowY[k] = PixelPTEBytesPerRowY_one_row_per_frame[k];
+			dpte_row_height_chroma[k] = dpte_row_height_chroma_one_row_per_frame[k];
+			dpte_row_width_chroma_ub[k] = dpte_row_width_chroma_ub_one_row_per_frame[k];
+			PixelPTEBytesPerRowC[k] = PixelPTEBytesPerRowC_one_row_per_frame[k];
+			PTEBufferSizeNotExceeded[k] = one_row_per_frame_fits_in_buffer[k];
+		}
+
+		if (MetaRowByte[k] <= DCCMetaBufferSizeBytes)
+			DCCMetaBufferSizeNotExceeded[k] = true;
+		else
+			DCCMetaBufferSizeNotExceeded[k] = false;
+
+		PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY[k] + PixelPTEBytesPerRowC[k];
+		if (use_one_row_for_frame[k])
+			PixelPTEBytesPerRow[k] = PixelPTEBytesPerRow[k] / 2;
+
+		dml32_CalculateRowBandwidth(
+				GPUVMEnable,
+				myPipe[k].SourcePixelFormat,
+				myPipe[k].VRatio,
+				myPipe[k].VRatioChroma,
+				myPipe[k].DCCEnable,
+				myPipe[k].HTotal / myPipe[k].PixelClock,
+				MetaRowByteY[k], MetaRowByteC[k],
+				meta_row_height[k],
+				meta_row_height_chroma[k],
+				PixelPTEBytesPerRowY[k],
+				PixelPTEBytesPerRowC[k],
+				dpte_row_height_luma[k],
+				dpte_row_height_chroma[k],
+
+				/* Output */
+				&meta_row_bw[k],
+				&dpte_row_bw[k]);
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, use_one_row_for_frame        = %d\n",  __func__, k, use_one_row_for_frame[k]);
+		dml_print("DML::%s: k=%d, use_one_row_for_frame_flip   = %d\n",
+				__func__, k, use_one_row_for_frame_flip[k]);
+		dml_print("DML::%s: k=%d, UseMALLForPStateChange       = %d\n",
+				__func__, k, UseMALLForPStateChange[k]);
+		dml_print("DML::%s: k=%d, dpte_row_height_luma         = %d\n",  __func__, k, dpte_row_height_luma[k]);
+		dml_print("DML::%s: k=%d, dpte_row_width_luma_ub       = %d\n",
+				__func__, k, dpte_row_width_luma_ub[k]);
+		dml_print("DML::%s: k=%d, PixelPTEBytesPerRowY         = %d\n",  __func__, k, PixelPTEBytesPerRowY[k]);
+		dml_print("DML::%s: k=%d, dpte_row_height_chroma       = %d\n",
+				__func__, k, dpte_row_height_chroma[k]);
+		dml_print("DML::%s: k=%d, dpte_row_width_chroma_ub     = %d\n",
+				__func__, k, dpte_row_width_chroma_ub[k]);
+		dml_print("DML::%s: k=%d, PixelPTEBytesPerRowC         = %d\n",  __func__, k, PixelPTEBytesPerRowC[k]);
+		dml_print("DML::%s: k=%d, PixelPTEBytesPerRow          = %d\n",  __func__, k, PixelPTEBytesPerRow[k]);
+		dml_print("DML::%s: k=%d, PTEBufferSizeNotExceeded     = %d\n",
+				__func__, k, PTEBufferSizeNotExceeded[k]);
+		dml_print("DML::%s: k=%d, PTE_BUFFER_MODE              = %d\n", __func__, k, PTE_BUFFER_MODE[k]);
+		dml_print("DML::%s: k=%d, BIGK_FRAGMENT_SIZE           = %d\n", __func__, k, BIGK_FRAGMENT_SIZE[k]);
+#endif
+	}
+} // CalculateVMRowAndSwath
+
+unsigned int dml32_CalculateVMAndRowBytes(
+		bool ViewportStationary,
+		bool DCCEnable,
+		unsigned int NumberOfDPPs,
+		unsigned int BlockHeight256Bytes,
+		unsigned int BlockWidth256Bytes,
+		enum source_format_class SourcePixelFormat,
+		unsigned int SurfaceTiling,
+		unsigned int BytePerPixel,
+		enum dm_rotation_angle SourceRotation,
+		double SwathWidth,
+		unsigned int ViewportHeight,
+		unsigned int    ViewportXStart,
+		unsigned int    ViewportYStart,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		unsigned int GPUVMMaxPageTableLevels,
+		unsigned int GPUVMMinPageSizeKBytes,
+		unsigned int HostVMMinPageSize,
+		unsigned int PTEBufferSizeInRequests,
+		unsigned int Pitch,
+		unsigned int DCCMetaPitch,
+		unsigned int MacroTileWidth,
+		unsigned int MacroTileHeight,
+
+		/* Output */
+		unsigned int *MetaRowByte,
+		unsigned int *PixelPTEBytesPerRow,
+		unsigned int    *dpte_row_width_ub,
+		unsigned int *dpte_row_height,
+		unsigned int *dpte_row_height_linear,
+		unsigned int    *PixelPTEBytesPerRow_one_row_per_frame,
+		unsigned int    *dpte_row_width_ub_one_row_per_frame,
+		unsigned int    *dpte_row_height_one_row_per_frame,
+		unsigned int *MetaRequestWidth,
+		unsigned int *MetaRequestHeight,
+		unsigned int *meta_row_width,
+		unsigned int *meta_row_height,
+		unsigned int *PixelPTEReqWidth,
+		unsigned int *PixelPTEReqHeight,
+		unsigned int *PTERequestSize,
+		unsigned int    *DPDE0BytesFrame,
+		unsigned int    *MetaPTEBytesFrame)
+{
+	unsigned int MPDEBytesFrame;
+	unsigned int DCCMetaSurfaceBytes;
+	unsigned int ExtraDPDEBytesFrame;
+	unsigned int PDEAndMetaPTEBytesFrame;
+	unsigned int HostVMDynamicLevels = 0;
+	unsigned int    MacroTileSizeBytes;
+	unsigned int    vp_height_meta_ub;
+	unsigned int    vp_height_dpte_ub;
+	unsigned int PixelPTEReqWidth_linear = 0; // VBA_DELTA. VBA doesn't calculate this
+
+	if (GPUVMEnable == true && HostVMEnable == true) {
+		if (HostVMMinPageSize < 2048)
+			HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels;
+		else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576)
+			HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1);
+		else
+			HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2);
+	}
+
+	*MetaRequestHeight = 8 * BlockHeight256Bytes;
+	*MetaRequestWidth = 8 * BlockWidth256Bytes;
+	if (SurfaceTiling == dm_sw_linear) {
+		*meta_row_height = 32;
+		*meta_row_width = dml_floor(ViewportXStart + SwathWidth + *MetaRequestWidth - 1, *MetaRequestWidth)
+				- dml_floor(ViewportXStart, *MetaRequestWidth);
+	} else if (!IsVertical(SourceRotation)) {
+		*meta_row_height = *MetaRequestHeight;
+		if (ViewportStationary && NumberOfDPPs == 1) {
+			*meta_row_width = dml_floor(ViewportXStart + SwathWidth + *MetaRequestWidth - 1,
+					*MetaRequestWidth) - dml_floor(ViewportXStart, *MetaRequestWidth);
+		} else {
+			*meta_row_width = dml_ceil(SwathWidth - 1, *MetaRequestWidth) + *MetaRequestWidth;
+		}
+		*MetaRowByte = *meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0;
+	} else {
+		*meta_row_height = *MetaRequestWidth;
+		if (ViewportStationary && NumberOfDPPs == 1) {
+			*meta_row_width = dml_floor(ViewportYStart + ViewportHeight + *MetaRequestHeight - 1,
+					*MetaRequestHeight) - dml_floor(ViewportYStart, *MetaRequestHeight);
+		} else {
+			*meta_row_width = dml_ceil(SwathWidth - 1, *MetaRequestHeight) + *MetaRequestHeight;
+		}
+		*MetaRowByte = *meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0;
+	}
+
+	if (ViewportStationary && (NumberOfDPPs == 1 || !IsVertical(SourceRotation))) {
+		vp_height_meta_ub = dml_floor(ViewportYStart + ViewportHeight + 64 * BlockHeight256Bytes - 1,
+				64 * BlockHeight256Bytes) - dml_floor(ViewportYStart, 64 * BlockHeight256Bytes);
+	} else if (!IsVertical(SourceRotation)) {
+		vp_height_meta_ub = dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes;
+	} else {
+		vp_height_meta_ub = dml_ceil(SwathWidth - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes;
+	}
+
+	DCCMetaSurfaceBytes = DCCMetaPitch * vp_height_meta_ub * BytePerPixel / 256.0;
+
+	if (GPUVMEnable == true) {
+		*MetaPTEBytesFrame = (dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) /
+				(8 * 4.0 * 1024), 1) + 1) * 64;
+		MPDEBytesFrame = 128 * (GPUVMMaxPageTableLevels - 1);
+	} else {
+		*MetaPTEBytesFrame = 0;
+		MPDEBytesFrame = 0;
+	}
+
+	if (DCCEnable != true) {
+		*MetaPTEBytesFrame = 0;
+		MPDEBytesFrame = 0;
+		*MetaRowByte = 0;
+	}
+
+	MacroTileSizeBytes = MacroTileWidth * BytePerPixel * MacroTileHeight;
+
+	if (GPUVMEnable == true && GPUVMMaxPageTableLevels > 1) {
+		if (ViewportStationary && (NumberOfDPPs == 1 || !IsVertical(SourceRotation))) {
+			vp_height_dpte_ub = dml_floor(ViewportYStart + ViewportHeight +
+					MacroTileHeight - 1, MacroTileHeight) -
+					dml_floor(ViewportYStart, MacroTileHeight);
+		} else if (!IsVertical(SourceRotation)) {
+			vp_height_dpte_ub = dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight;
+		} else {
+			vp_height_dpte_ub = dml_ceil(SwathWidth - 1, MacroTileHeight) + MacroTileHeight;
+		}
+		*DPDE0BytesFrame = 64 * (dml_ceil((Pitch * vp_height_dpte_ub * BytePerPixel - MacroTileSizeBytes) /
+				(8 * 2097152), 1) + 1);
+		ExtraDPDEBytesFrame = 128 * (GPUVMMaxPageTableLevels - 2);
+	} else {
+		*DPDE0BytesFrame = 0;
+		ExtraDPDEBytesFrame = 0;
+		vp_height_dpte_ub = 0;
+	}
+
+	PDEAndMetaPTEBytesFrame = *MetaPTEBytesFrame + MPDEBytesFrame + *DPDE0BytesFrame + ExtraDPDEBytesFrame;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DCCEnable = %d\n", __func__, DCCEnable);
+	dml_print("DML::%s: GPUVMEnable = %d\n", __func__, GPUVMEnable);
+	dml_print("DML::%s: SwModeLinear = %d\n", __func__, SurfaceTiling == dm_sw_linear);
+	dml_print("DML::%s: BytePerPixel = %d\n", __func__, BytePerPixel);
+	dml_print("DML::%s: GPUVMMaxPageTableLevels = %d\n", __func__, GPUVMMaxPageTableLevels);
+	dml_print("DML::%s: BlockHeight256Bytes = %d\n", __func__, BlockHeight256Bytes);
+	dml_print("DML::%s: BlockWidth256Bytes = %d\n", __func__, BlockWidth256Bytes);
+	dml_print("DML::%s: MacroTileHeight = %d\n", __func__, MacroTileHeight);
+	dml_print("DML::%s: MacroTileWidth = %d\n", __func__, MacroTileWidth);
+	dml_print("DML::%s: MetaPTEBytesFrame = %d\n", __func__, *MetaPTEBytesFrame);
+	dml_print("DML::%s: MPDEBytesFrame = %d\n", __func__, MPDEBytesFrame);
+	dml_print("DML::%s: DPDE0BytesFrame = %d\n", __func__, *DPDE0BytesFrame);
+	dml_print("DML::%s: ExtraDPDEBytesFrame= %d\n", __func__, ExtraDPDEBytesFrame);
+	dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d\n", __func__, PDEAndMetaPTEBytesFrame);
+	dml_print("DML::%s: ViewportHeight = %d\n", __func__, ViewportHeight);
+	dml_print("DML::%s: SwathWidth = %d\n", __func__, SwathWidth);
+	dml_print("DML::%s: vp_height_dpte_ub = %d\n", __func__, vp_height_dpte_ub);
+#endif
+
+	if (HostVMEnable == true)
+		PDEAndMetaPTEBytesFrame = PDEAndMetaPTEBytesFrame * (1 + 8 * HostVMDynamicLevels);
+
+	if (SurfaceTiling == dm_sw_linear) {
+		*PixelPTEReqHeight = 1;
+		*PixelPTEReqWidth = GPUVMMinPageSizeKBytes * 1024 * 8 / BytePerPixel;
+		PixelPTEReqWidth_linear = GPUVMMinPageSizeKBytes * 1024 * 8 / BytePerPixel;
+		*PTERequestSize = 64;
+	} else if (GPUVMMinPageSizeKBytes == 4) {
+		*PixelPTEReqHeight = 16 * BlockHeight256Bytes;
+		*PixelPTEReqWidth = 16 * BlockWidth256Bytes;
+		*PTERequestSize = 128;
+	} else {
+		*PixelPTEReqHeight = MacroTileHeight;
+		*PixelPTEReqWidth = 8 *  1024 * GPUVMMinPageSizeKBytes / (MacroTileHeight * BytePerPixel);
+		*PTERequestSize = 64;
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: GPUVMMinPageSizeKBytes = %d\n", __func__, GPUVMMinPageSizeKBytes);
+	dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d (after HostVM factor)\n", __func__, PDEAndMetaPTEBytesFrame);
+	dml_print("DML::%s: PixelPTEReqHeight = %d\n", __func__, *PixelPTEReqHeight);
+	dml_print("DML::%s: PixelPTEReqWidth = %d\n", __func__, *PixelPTEReqWidth);
+	dml_print("DML::%s: PixelPTEReqWidth_linear = %d\n", __func__, PixelPTEReqWidth_linear);
+	dml_print("DML::%s: PTERequestSize = %d\n", __func__, *PTERequestSize);
+	dml_print("DML::%s: Pitch = %d\n", __func__, Pitch);
+#endif
+
+	*dpte_row_height_one_row_per_frame = vp_height_dpte_ub;
+	*dpte_row_width_ub_one_row_per_frame = (dml_ceil(((double)Pitch * (double)*dpte_row_height_one_row_per_frame /
+			(double) *PixelPTEReqHeight - 1) / (double) *PixelPTEReqWidth, 1) + 1) *
+					(double) *PixelPTEReqWidth;
+	*PixelPTEBytesPerRow_one_row_per_frame = *dpte_row_width_ub_one_row_per_frame / *PixelPTEReqWidth *
+			*PTERequestSize;
+
+	if (SurfaceTiling == dm_sw_linear) {
+		*dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests *
+				*PixelPTEReqWidth / Pitch), 1));
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: dpte_row_height = %d (1)\n", __func__,
+				PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch);
+		dml_print("DML::%s: dpte_row_height = %f (2)\n", __func__,
+				dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch));
+		dml_print("DML::%s: dpte_row_height = %f (3)\n", __func__,
+				dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1));
+		dml_print("DML::%s: dpte_row_height = %d (4)\n", __func__,
+				1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests *
+						*PixelPTEReqWidth / Pitch), 1));
+		dml_print("DML::%s: dpte_row_height = %d\n", __func__, *dpte_row_height);
+#endif
+		*dpte_row_width_ub = dml_ceil(((double) Pitch * (double) *dpte_row_height - 1),
+				(double) *PixelPTEReqWidth) + *PixelPTEReqWidth;
+		*PixelPTEBytesPerRow = *dpte_row_width_ub / (double)*PixelPTEReqWidth * (double)*PTERequestSize;
+
+		// VBA_DELTA, VBA doesn't have programming value for pte row height linear.
+		*dpte_row_height_linear = 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests *
+				PixelPTEReqWidth_linear / Pitch), 1);
+		if (*dpte_row_height_linear > 128)
+			*dpte_row_height_linear = 128;
+
+	} else if (!IsVertical(SourceRotation)) {
+		*dpte_row_height = *PixelPTEReqHeight;
+
+		if (GPUVMMinPageSizeKBytes > 64) {
+			*dpte_row_width_ub = (dml_ceil((Pitch * *dpte_row_height / *PixelPTEReqHeight - 1) /
+					*PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth;
+		} else if (ViewportStationary && (NumberOfDPPs == 1)) {
+			*dpte_row_width_ub = dml_floor(ViewportXStart + SwathWidth +
+					*PixelPTEReqWidth - 1, *PixelPTEReqWidth) -
+					dml_floor(ViewportXStart, *PixelPTEReqWidth);
+		} else {
+			*dpte_row_width_ub = (dml_ceil((SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) *
+					*PixelPTEReqWidth;
+		}
+
+		*PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize;
+	} else {
+		*dpte_row_height = dml_min(*PixelPTEReqWidth, MacroTileWidth);
+
+		if (ViewportStationary && (NumberOfDPPs == 1)) {
+			*dpte_row_width_ub = dml_floor(ViewportYStart + ViewportHeight + *PixelPTEReqHeight - 1,
+					*PixelPTEReqHeight) - dml_floor(ViewportYStart, *PixelPTEReqHeight);
+		} else {
+			*dpte_row_width_ub = (dml_ceil((SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1)
+					* *PixelPTEReqHeight;
+		}
+
+		*PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqHeight * *PTERequestSize;
+	}
+
+	if (GPUVMEnable != true)
+		*PixelPTEBytesPerRow = 0;
+	if (HostVMEnable == true)
+		*PixelPTEBytesPerRow = *PixelPTEBytesPerRow * (1 + 8 * HostVMDynamicLevels);
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: GPUVMMinPageSizeKBytes = %d\n", __func__, GPUVMMinPageSizeKBytes);
+	dml_print("DML::%s: dpte_row_height = %d\n", __func__, *dpte_row_height);
+	dml_print("DML::%s: dpte_row_height_linear = %d\n", __func__, *dpte_row_height_linear);
+	dml_print("DML::%s: dpte_row_width_ub = %d\n", __func__, *dpte_row_width_ub);
+	dml_print("DML::%s: PixelPTEBytesPerRow = %d\n", __func__, *PixelPTEBytesPerRow);
+	dml_print("DML::%s: PTEBufferSizeInRequests = %d\n", __func__, PTEBufferSizeInRequests);
+	dml_print("DML::%s: dpte_row_height_one_row_per_frame = %d\n", __func__, *dpte_row_height_one_row_per_frame);
+	dml_print("DML::%s: dpte_row_width_ub_one_row_per_frame = %d\n",
+			__func__, *dpte_row_width_ub_one_row_per_frame);
+	dml_print("DML::%s: PixelPTEBytesPerRow_one_row_per_frame = %d\n",
+			__func__, *PixelPTEBytesPerRow_one_row_per_frame);
+	dml_print("DML: vm_bytes = meta_pte_bytes_per_frame (per_pipe) = MetaPTEBytesFrame = : %i\n",
+			*MetaPTEBytesFrame);
+#endif
+
+	return PDEAndMetaPTEBytesFrame;
+} // CalculateVMAndRowBytes
+
+double dml32_CalculatePrefetchSourceLines(
+		double VRatio,
+		unsigned int VTaps,
+		bool Interlace,
+		bool ProgressiveToInterlaceUnitInOPP,
+		unsigned int SwathHeight,
+		enum dm_rotation_angle SourceRotation,
+		bool ViewportStationary,
+		double SwathWidth,
+		unsigned int ViewportHeight,
+		unsigned int ViewportXStart,
+		unsigned int ViewportYStart,
+
+		/* Output */
+		double *VInitPreFill,
+		unsigned int *MaxNumSwath)
+{
+
+	unsigned int vp_start_rot;
+	unsigned int sw0_tmp;
+	unsigned int MaxPartialSwath;
+	double numLines;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: VRatio = %f\n", __func__, VRatio);
+	dml_print("DML::%s: VTaps = %d\n", __func__, VTaps);
+	dml_print("DML::%s: ViewportXStart = %d\n", __func__, ViewportXStart);
+	dml_print("DML::%s: ViewportYStart = %d\n", __func__, ViewportYStart);
+	dml_print("DML::%s: ViewportStationary = %d\n", __func__, ViewportStationary);
+	dml_print("DML::%s: SwathHeight = %d\n", __func__, SwathHeight);
+#endif
+	if (ProgressiveToInterlaceUnitInOPP)
+		*VInitPreFill = dml_floor((VRatio + (double) VTaps + 1) / 2.0, 1);
+	else
+		*VInitPreFill = dml_floor((VRatio + (double) VTaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1);
+
+	if (ViewportStationary) {
+		if (SourceRotation == dm_rotation_180 || SourceRotation == dm_rotation_180m) {
+			vp_start_rot = SwathHeight -
+					(((unsigned int) (ViewportYStart + ViewportHeight - 1) % SwathHeight) + 1);
+		} else if (SourceRotation == dm_rotation_270 || SourceRotation == dm_rotation_90m) {
+			vp_start_rot = ViewportXStart;
+		} else if (SourceRotation == dm_rotation_90 || SourceRotation == dm_rotation_270m) {
+			vp_start_rot = SwathHeight -
+					(((unsigned int)(ViewportYStart + SwathWidth - 1) % SwathHeight) + 1);
+		} else {
+			vp_start_rot = ViewportYStart;
+		}
+		sw0_tmp = SwathHeight - (vp_start_rot % SwathHeight);
+		if (sw0_tmp < *VInitPreFill)
+			*MaxNumSwath = dml_ceil((*VInitPreFill - sw0_tmp) / SwathHeight, 1) + 1;
+		else
+			*MaxNumSwath = 1;
+		MaxPartialSwath = dml_max(1, (unsigned int) (vp_start_rot + *VInitPreFill - 1) % SwathHeight);
+	} else {
+		*MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1;
+		if (*VInitPreFill > 1)
+			MaxPartialSwath = dml_max(1, (unsigned int) (*VInitPreFill - 2) % SwathHeight);
+		else
+			MaxPartialSwath = dml_max(1, (unsigned int) (*VInitPreFill + SwathHeight - 2) % SwathHeight);
+	}
+	numLines = *MaxNumSwath * SwathHeight + MaxPartialSwath;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: vp_start_rot = %d\n", __func__, vp_start_rot);
+	dml_print("DML::%s: VInitPreFill = %d\n", __func__, *VInitPreFill);
+	dml_print("DML::%s: MaxPartialSwath = %d\n", __func__, MaxPartialSwath);
+	dml_print("DML::%s: MaxNumSwath = %d\n", __func__, *MaxNumSwath);
+	dml_print("DML::%s: Prefetch source lines = %3.2f\n", __func__, numLines);
+#endif
+	return numLines;
+
+} // CalculatePrefetchSourceLines
+
+void dml32_CalculateMALLUseForStaticScreen(
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int MALLAllocatedForDCNFinal,
+		enum dm_use_mall_for_static_screen_mode *UseMALLForStaticScreen,
+		unsigned int SurfaceSizeInMALL[],
+		bool one_row_per_frame_fits_in_buffer[],
+
+		/* output */
+		bool UsesMALLForStaticScreen[])
+{
+	unsigned int k;
+	unsigned int SurfaceToAddToMALL;
+	bool CanAddAnotherSurfaceToMALL;
+	unsigned int TotalSurfaceSizeInMALL;
+
+	TotalSurfaceSizeInMALL = 0;
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		UsesMALLForStaticScreen[k] = (UseMALLForStaticScreen[k] == dm_use_mall_static_screen_enable);
+		if (UsesMALLForStaticScreen[k])
+			TotalSurfaceSizeInMALL = TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k];
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, UsesMALLForStaticScreen = %d\n",  __func__, k, UsesMALLForStaticScreen[k]);
+		dml_print("DML::%s: k=%d, TotalSurfaceSizeInMALL = %d\n",  __func__, k, TotalSurfaceSizeInMALL);
+#endif
+	}
+
+	SurfaceToAddToMALL = 0;
+	CanAddAnotherSurfaceToMALL = true;
+	while (CanAddAnotherSurfaceToMALL) {
+		CanAddAnotherSurfaceToMALL = false;
+		for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+			if (TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k] <= MALLAllocatedForDCNFinal * 1024 * 1024 &&
+					!UsesMALLForStaticScreen[k] &&
+					UseMALLForStaticScreen[k] != dm_use_mall_static_screen_disable &&
+					one_row_per_frame_fits_in_buffer[k] &&
+					(!CanAddAnotherSurfaceToMALL ||
+					SurfaceSizeInMALL[k] < SurfaceSizeInMALL[SurfaceToAddToMALL])) {
+				CanAddAnotherSurfaceToMALL = true;
+				SurfaceToAddToMALL = k;
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: k=%d, UseMALLForStaticScreen = %d (dis, en, optimize)\n",
+						__func__, k, UseMALLForStaticScreen[k]);
+#endif
+			}
+		}
+		if (CanAddAnotherSurfaceToMALL) {
+			UsesMALLForStaticScreen[SurfaceToAddToMALL] = true;
+			TotalSurfaceSizeInMALL = TotalSurfaceSizeInMALL + SurfaceSizeInMALL[SurfaceToAddToMALL];
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: SurfaceToAddToMALL       = %d\n",  __func__, SurfaceToAddToMALL);
+			dml_print("DML::%s: TotalSurfaceSizeInMALL   = %d\n",  __func__, TotalSurfaceSizeInMALL);
+#endif
+
+		}
+	}
+}
+
+void dml32_CalculateRowBandwidth(
+		bool GPUVMEnable,
+		enum source_format_class SourcePixelFormat,
+		double VRatio,
+		double VRatioChroma,
+		bool DCCEnable,
+		double LineTime,
+		unsigned int MetaRowByteLuma,
+		unsigned int MetaRowByteChroma,
+		unsigned int meta_row_height_luma,
+		unsigned int meta_row_height_chroma,
+		unsigned int PixelPTEBytesPerRowLuma,
+		unsigned int PixelPTEBytesPerRowChroma,
+		unsigned int dpte_row_height_luma,
+		unsigned int dpte_row_height_chroma,
+		/* Output */
+		double *meta_row_bw,
+		double *dpte_row_bw)
+{
+	if (DCCEnable != true) {
+		*meta_row_bw = 0;
+	} else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_420_12 ||
+			SourcePixelFormat == dm_rgbe_alpha) {
+		*meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime) + VRatioChroma *
+				MetaRowByteChroma / (meta_row_height_chroma * LineTime);
+	} else {
+		*meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime);
+	}
+
+	if (GPUVMEnable != true) {
+		*dpte_row_bw = 0;
+	} else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_420_12 ||
+			SourcePixelFormat == dm_rgbe_alpha) {
+		*dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime) +
+				VRatioChroma * PixelPTEBytesPerRowChroma / (dpte_row_height_chroma * LineTime);
+	} else {
+		*dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime);
+	}
+}
+
+double dml32_CalculateUrgentLatency(
+		double UrgentLatencyPixelDataOnly,
+		double UrgentLatencyPixelMixedWithVMData,
+		double UrgentLatencyVMDataOnly,
+		bool   DoUrgentLatencyAdjustment,
+		double UrgentLatencyAdjustmentFabricClockComponent,
+		double UrgentLatencyAdjustmentFabricClockReference,
+		double FabricClock)
+{
+	double   ret;
+
+	ret = dml_max3(UrgentLatencyPixelDataOnly, UrgentLatencyPixelMixedWithVMData, UrgentLatencyVMDataOnly);
+	if (DoUrgentLatencyAdjustment == true) {
+		ret = ret + UrgentLatencyAdjustmentFabricClockComponent *
+				(UrgentLatencyAdjustmentFabricClockReference / FabricClock - 1);
+	}
+	return ret;
+}
+
+void dml32_CalculateUrgentBurstFactor(
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange,
+		unsigned int    swath_width_luma_ub,
+		unsigned int    swath_width_chroma_ub,
+		unsigned int SwathHeightY,
+		unsigned int SwathHeightC,
+		double  LineTime,
+		double  UrgentLatency,
+		double  CursorBufferSize,
+		unsigned int CursorWidth,
+		unsigned int CursorBPP,
+		double  VRatio,
+		double  VRatioC,
+		double  BytePerPixelInDETY,
+		double  BytePerPixelInDETC,
+		unsigned int    DETBufferSizeY,
+		unsigned int    DETBufferSizeC,
+		/* Output */
+		double *UrgentBurstFactorCursor,
+		double *UrgentBurstFactorLuma,
+		double *UrgentBurstFactorChroma,
+		bool   *NotEnoughUrgentLatencyHiding)
+{
+	double       LinesInDETLuma;
+	double       LinesInDETChroma;
+	unsigned int LinesInCursorBuffer;
+	double       CursorBufferSizeInTime;
+	double       DETBufferSizeInTimeLuma;
+	double       DETBufferSizeInTimeChroma;
+
+	*NotEnoughUrgentLatencyHiding = 0;
+
+	if (CursorWidth > 0) {
+		LinesInCursorBuffer = 1 << (unsigned int) dml_floor(dml_log2(CursorBufferSize * 1024.0 /
+				(CursorWidth * CursorBPP / 8.0)), 1.0);
+		if (VRatio > 0) {
+			CursorBufferSizeInTime = LinesInCursorBuffer * LineTime / VRatio;
+			if (CursorBufferSizeInTime - UrgentLatency <= 0) {
+				*NotEnoughUrgentLatencyHiding = 1;
+				*UrgentBurstFactorCursor = 0;
+			} else {
+				*UrgentBurstFactorCursor = CursorBufferSizeInTime /
+						(CursorBufferSizeInTime - UrgentLatency);
+			}
+		} else {
+			*UrgentBurstFactorCursor = 1;
+		}
+	}
+
+	LinesInDETLuma = (UseMALLForPStateChange == dm_use_mall_pstate_change_phantom_pipe ? 1024*1024 :
+			DETBufferSizeY) / BytePerPixelInDETY / swath_width_luma_ub;
+
+	if (VRatio > 0) {
+		DETBufferSizeInTimeLuma = dml_floor(LinesInDETLuma, SwathHeightY) * LineTime / VRatio;
+		if (DETBufferSizeInTimeLuma - UrgentLatency <= 0) {
+			*NotEnoughUrgentLatencyHiding = 1;
+			*UrgentBurstFactorLuma = 0;
+		} else {
+			*UrgentBurstFactorLuma = DETBufferSizeInTimeLuma / (DETBufferSizeInTimeLuma - UrgentLatency);
+		}
+	} else {
+		*UrgentBurstFactorLuma = 1;
+	}
+
+	if (BytePerPixelInDETC > 0) {
+		LinesInDETChroma = (UseMALLForPStateChange == dm_use_mall_pstate_change_phantom_pipe ?
+					1024 * 1024 : DETBufferSizeC) / BytePerPixelInDETC
+					/ swath_width_chroma_ub;
+
+		if (VRatio > 0) {
+			DETBufferSizeInTimeChroma = dml_floor(LinesInDETChroma, SwathHeightC) * LineTime / VRatio;
+			if (DETBufferSizeInTimeChroma - UrgentLatency <= 0) {
+				*NotEnoughUrgentLatencyHiding = 1;
+				*UrgentBurstFactorChroma = 0;
+			} else {
+				*UrgentBurstFactorChroma = DETBufferSizeInTimeChroma
+						/ (DETBufferSizeInTimeChroma - UrgentLatency);
+			}
+		} else {
+			*UrgentBurstFactorChroma = 1;
+		}
+	}
+} // CalculateUrgentBurstFactor
+
+void dml32_CalculateDCFCLKDeepSleep(
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int BytePerPixelY[],
+		unsigned int BytePerPixelC[],
+		double VRatio[],
+		double VRatioChroma[],
+		double SwathWidthY[],
+		double SwathWidthC[],
+		unsigned int DPPPerSurface[],
+		double HRatio[],
+		double HRatioChroma[],
+		double PixelClock[],
+		double PSCL_THROUGHPUT[],
+		double PSCL_THROUGHPUT_CHROMA[],
+		double Dppclk[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		unsigned int ReturnBusWidth,
+
+		/* Output */
+		double *DCFClkDeepSleep)
+{
+	unsigned int k;
+	double   DisplayPipeLineDeliveryTimeLuma;
+	double   DisplayPipeLineDeliveryTimeChroma;
+	double   DCFClkDeepSleepPerSurface[DC__NUM_DPP__MAX];
+	double ReadBandwidth = 0.0;
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+
+		if (VRatio[k] <= 1) {
+			DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerSurface[k] / HRatio[k]
+					/ PixelClock[k];
+		} else {
+			DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
+		}
+		if (BytePerPixelC[k] == 0) {
+			DisplayPipeLineDeliveryTimeChroma = 0;
+		} else {
+			if (VRatioChroma[k] <= 1) {
+				DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] *
+						DPPPerSurface[k] / HRatioChroma[k] / PixelClock[k];
+			} else {
+				DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] / PSCL_THROUGHPUT_CHROMA[k]
+						/ Dppclk[k];
+			}
+		}
+
+		if (BytePerPixelC[k] > 0) {
+			DCFClkDeepSleepPerSurface[k] = dml_max(__DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] *
+					BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma,
+					__DML_MIN_DCFCLK_FACTOR__ * SwathWidthC[k] * BytePerPixelC[k] /
+					32.0 / DisplayPipeLineDeliveryTimeChroma);
+		} else {
+			DCFClkDeepSleepPerSurface[k] = __DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] /
+					64.0 / DisplayPipeLineDeliveryTimeLuma;
+		}
+		DCFClkDeepSleepPerSurface[k] = dml_max(DCFClkDeepSleepPerSurface[k], PixelClock[k] / 16);
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, PixelClock = %f\n", __func__, k, PixelClock[k]);
+		dml_print("DML::%s: k=%d, DCFClkDeepSleepPerSurface = %f\n", __func__, k, DCFClkDeepSleepPerSurface[k]);
+#endif
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k)
+		ReadBandwidth = ReadBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
+
+	*DCFClkDeepSleep = dml_max(8.0, __DML_MIN_DCFCLK_FACTOR__ * ReadBandwidth / (double) ReturnBusWidth);
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: __DML_MIN_DCFCLK_FACTOR__ = %f\n", __func__, __DML_MIN_DCFCLK_FACTOR__);
+	dml_print("DML::%s: ReadBandwidth = %f\n", __func__, ReadBandwidth);
+	dml_print("DML::%s: ReturnBusWidth = %d\n", __func__, ReturnBusWidth);
+	dml_print("DML::%s: DCFClkDeepSleep = %f\n", __func__, *DCFClkDeepSleep);
+#endif
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k)
+		*DCFClkDeepSleep = dml_max(*DCFClkDeepSleep, DCFClkDeepSleepPerSurface[k]);
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DCFClkDeepSleep = %f (final)\n", __func__, *DCFClkDeepSleep);
+#endif
+} // CalculateDCFCLKDeepSleep
+
+double dml32_CalculateWriteBackDelay(
+		enum source_format_class WritebackPixelFormat,
+		double WritebackHRatio,
+		double WritebackVRatio,
+		unsigned int WritebackVTaps,
+		unsigned int         WritebackDestinationWidth,
+		unsigned int         WritebackDestinationHeight,
+		unsigned int         WritebackSourceHeight,
+		unsigned int HTotal)
+{
+	double CalculateWriteBackDelay;
+	double Line_length;
+	double Output_lines_last_notclamped;
+	double WritebackVInit;
+
+	WritebackVInit = (WritebackVRatio + WritebackVTaps + 1) / 2;
+	Line_length = dml_max((double) WritebackDestinationWidth,
+			dml_ceil((double)WritebackDestinationWidth / 6.0, 1.0) * WritebackVTaps);
+	Output_lines_last_notclamped = WritebackDestinationHeight - 1 -
+			dml_ceil(((double)WritebackSourceHeight -
+					(double) WritebackVInit) / (double)WritebackVRatio, 1.0);
+	if (Output_lines_last_notclamped < 0) {
+		CalculateWriteBackDelay = 0;
+	} else {
+		CalculateWriteBackDelay = Output_lines_last_notclamped * Line_length +
+				(HTotal - WritebackDestinationWidth) + 80;
+	}
+	return CalculateWriteBackDelay;
+}
+
+void dml32_UseMinimumDCFCLK(
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		bool DRRDisplay[],
+		bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+		unsigned int MaxInterDCNTileRepeaters,
+		unsigned int MaxPrefetchMode,
+		double DRAMClockChangeLatencyFinal,
+		double FCLKChangeLatency,
+		double SREnterPlusExitTime,
+		unsigned int ReturnBusWidth,
+		unsigned int RoundTripPingLatencyCycles,
+		unsigned int ReorderingBytes,
+		unsigned int PixelChunkSizeInKByte,
+		unsigned int MetaChunkSize,
+		bool GPUVMEnable,
+		unsigned int GPUVMMaxPageTableLevels,
+		bool HostVMEnable,
+		unsigned int NumberOfActiveSurfaces,
+		double HostVMMinPageSize,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		bool DynamicMetadataVMEnabled,
+		bool ImmediateFlipRequirement,
+		bool ProgressiveToInterlaceUnitInOPP,
+		double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation,
+		double PercentOfIdealSDPPortBWReceivedAfterUrgLatency,
+		unsigned int VTotal[],
+		unsigned int VActive[],
+		unsigned int DynamicMetadataTransmittedBytes[],
+		unsigned int DynamicMetadataLinesBeforeActiveRequired[],
+		bool Interlace[],
+		double RequiredDPPCLKPerSurface[][2][DC__NUM_DPP__MAX],
+		double RequiredDISPCLK[][2],
+		double UrgLatency[],
+		unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX],
+		double ProjectedDCFClkDeepSleep[][2],
+		double MaximumVStartup[][2][DC__NUM_DPP__MAX],
+		unsigned int TotalNumberOfActiveDPP[][2],
+		unsigned int TotalNumberOfDCCActiveDPP[][2],
+		unsigned int dpte_group_bytes[],
+		double PrefetchLinesY[][2][DC__NUM_DPP__MAX],
+		double PrefetchLinesC[][2][DC__NUM_DPP__MAX],
+		unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		unsigned int BytePerPixelY[],
+		unsigned int BytePerPixelC[],
+		unsigned int HTotal[],
+		double PixelClock[],
+		double PDEAndMetaPTEBytesPerFrame[][2][DC__NUM_DPP__MAX],
+		double DPTEBytesPerRow[][2][DC__NUM_DPP__MAX],
+		double MetaRowBytes[][2][DC__NUM_DPP__MAX],
+		bool DynamicMetadataEnable[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double DCFCLKPerState[],
+		/* Output */
+		double DCFCLKState[][2])
+{
+	unsigned int i, j, k;
+	unsigned int     dummy1;
+	double dummy2, dummy3;
+	double   NormalEfficiency;
+	double   TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];
+
+	NormalEfficiency = PercentOfIdealSDPPortBWReceivedAfterUrgLatency / 100.0;
+	for  (i = 0; i < DC__VOLTAGE_STATES; ++i) {
+		for  (j = 0; j <= 1; ++j) {
+			double PixelDCFCLKCyclesRequiredInPrefetch[DC__NUM_DPP__MAX];
+			double PrefetchPixelLinesTime[DC__NUM_DPP__MAX];
+			double DCFCLKRequiredForPeakBandwidthPerSurface[DC__NUM_DPP__MAX];
+			double DynamicMetadataVMExtraLatency[DC__NUM_DPP__MAX];
+			double MinimumTWait = 0.0;
+			double DPTEBandwidth;
+			double DCFCLKRequiredForAverageBandwidth;
+			unsigned int ExtraLatencyBytes;
+			double ExtraLatencyCycles;
+			double DCFCLKRequiredForPeakBandwidth;
+			unsigned int NoOfDPPState[DC__NUM_DPP__MAX];
+			double MinimumTvmPlus2Tr0;
+
+			TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0;
+			for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+				TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = TotalMaxPrefetchFlipDPTERowBandwidth[i][j]
+						+ NoOfDPP[i][j][k] * DPTEBytesPerRow[i][j][k]
+								/ (15.75 * HTotal[k] / PixelClock[k]);
+			}
+
+			for (k = 0; k <= NumberOfActiveSurfaces - 1; ++k)
+				NoOfDPPState[k] = NoOfDPP[i][j][k];
+
+			DPTEBandwidth = TotalMaxPrefetchFlipDPTERowBandwidth[i][j];
+			DCFCLKRequiredForAverageBandwidth = dml_max(ProjectedDCFClkDeepSleep[i][j], DPTEBandwidth / NormalEfficiency / ReturnBusWidth);
+
+			ExtraLatencyBytes = dml32_CalculateExtraLatencyBytes(ReorderingBytes,
+					TotalNumberOfActiveDPP[i][j], PixelChunkSizeInKByte,
+					TotalNumberOfDCCActiveDPP[i][j], MetaChunkSize, GPUVMEnable, HostVMEnable,
+					NumberOfActiveSurfaces, NoOfDPPState, dpte_group_bytes, 1, HostVMMinPageSize,
+					HostVMMaxNonCachedPageTableLevels);
+			ExtraLatencyCycles = RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__
+					+ ExtraLatencyBytes / NormalEfficiency / ReturnBusWidth;
+			for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+				double DCFCLKCyclesRequiredInPrefetch;
+				double PrefetchTime;
+
+				PixelDCFCLKCyclesRequiredInPrefetch[k] = (PrefetchLinesY[i][j][k]
+						* swath_width_luma_ub_all_states[i][j][k] * BytePerPixelY[k]
+						+ PrefetchLinesC[i][j][k] * swath_width_chroma_ub_all_states[i][j][k]
+								* BytePerPixelC[k]) / NormalEfficiency
+						/ ReturnBusWidth;
+				DCFCLKCyclesRequiredInPrefetch = 2 * ExtraLatencyCycles / NoOfDPPState[k]
+						+ PDEAndMetaPTEBytesPerFrame[i][j][k] / NormalEfficiency
+								/ NormalEfficiency / ReturnBusWidth
+								* (GPUVMMaxPageTableLevels > 2 ? 1 : 0)
+						+ 2 * DPTEBytesPerRow[i][j][k] / NormalEfficiency / NormalEfficiency
+								/ ReturnBusWidth
+						+ 2 * MetaRowBytes[i][j][k] / NormalEfficiency / ReturnBusWidth
+						+ PixelDCFCLKCyclesRequiredInPrefetch[k];
+				PrefetchPixelLinesTime[k] = dml_max(PrefetchLinesY[i][j][k], PrefetchLinesC[i][j][k])
+						* HTotal[k] / PixelClock[k];
+				DynamicMetadataVMExtraLatency[k] = (GPUVMEnable == true &&
+						DynamicMetadataEnable[k] == true && DynamicMetadataVMEnabled == true) ?
+						UrgLatency[i] * GPUVMMaxPageTableLevels *
+						(HostVMEnable == true ? HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0;
+
+				MinimumTWait = dml32_CalculateTWait(MaxPrefetchMode,
+						UseMALLForPStateChange[k],
+						SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+						DRRDisplay[k],
+						DRAMClockChangeLatencyFinal,
+						FCLKChangeLatency,
+						UrgLatency[i],
+						SREnterPlusExitTime);
+
+				PrefetchTime = (MaximumVStartup[i][j][k] - 1) * HTotal[k] / PixelClock[k] -
+						MinimumTWait - UrgLatency[i] *
+						((GPUVMMaxPageTableLevels <= 2 ? GPUVMMaxPageTableLevels :
+						GPUVMMaxPageTableLevels - 2) *  (HostVMEnable == true ?
+						HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1) -
+						DynamicMetadataVMExtraLatency[k];
+
+				if (PrefetchTime > 0) {
+					double ExpectedVRatioPrefetch;
+
+					ExpectedVRatioPrefetch = PrefetchPixelLinesTime[k] / (PrefetchTime *
+							PixelDCFCLKCyclesRequiredInPrefetch[k] /
+							DCFCLKCyclesRequiredInPrefetch);
+					DCFCLKRequiredForPeakBandwidthPerSurface[k] = NoOfDPPState[k] *
+							PixelDCFCLKCyclesRequiredInPrefetch[k] /
+							PrefetchPixelLinesTime[k] *
+							dml_max(1.0, ExpectedVRatioPrefetch) *
+							dml_max(1.0, ExpectedVRatioPrefetch / 4);
+					if (HostVMEnable == true || ImmediateFlipRequirement == true) {
+						DCFCLKRequiredForPeakBandwidthPerSurface[k] =
+								DCFCLKRequiredForPeakBandwidthPerSurface[k] +
+								NoOfDPPState[k] * DPTEBandwidth / NormalEfficiency /
+								NormalEfficiency / ReturnBusWidth;
+					}
+				} else {
+					DCFCLKRequiredForPeakBandwidthPerSurface[k] = DCFCLKPerState[i];
+				}
+				if (DynamicMetadataEnable[k] == true) {
+					double TSetupPipe;
+					double TdmbfPipe;
+					double TdmsksPipe;
+					double TdmecPipe;
+					double AllowedTimeForUrgentExtraLatency;
+
+					dml32_CalculateVUpdateAndDynamicMetadataParameters(
+							MaxInterDCNTileRepeaters,
+							RequiredDPPCLKPerSurface[i][j][k],
+							RequiredDISPCLK[i][j],
+							ProjectedDCFClkDeepSleep[i][j],
+							PixelClock[k],
+							HTotal[k],
+							VTotal[k] - VActive[k],
+							DynamicMetadataTransmittedBytes[k],
+							DynamicMetadataLinesBeforeActiveRequired[k],
+							Interlace[k],
+							ProgressiveToInterlaceUnitInOPP,
+
+							/* output */
+							&TSetupPipe,
+							&TdmbfPipe,
+							&TdmecPipe,
+							&TdmsksPipe,
+							&dummy1,
+							&dummy2,
+							&dummy3);
+					AllowedTimeForUrgentExtraLatency = MaximumVStartup[i][j][k] * HTotal[k] /
+							PixelClock[k] - MinimumTWait - TSetupPipe - TdmbfPipe -
+							TdmecPipe - TdmsksPipe - DynamicMetadataVMExtraLatency[k];
+					if (AllowedTimeForUrgentExtraLatency > 0)
+						DCFCLKRequiredForPeakBandwidthPerSurface[k] =
+								dml_max(DCFCLKRequiredForPeakBandwidthPerSurface[k],
+								ExtraLatencyCycles / AllowedTimeForUrgentExtraLatency);
+					else
+						DCFCLKRequiredForPeakBandwidthPerSurface[k] = DCFCLKPerState[i];
+				}
+			}
+			DCFCLKRequiredForPeakBandwidth = 0;
+			for (k = 0; k <= NumberOfActiveSurfaces - 1; ++k) {
+				DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth +
+						DCFCLKRequiredForPeakBandwidthPerSurface[k];
+			}
+			MinimumTvmPlus2Tr0 = UrgLatency[i] * (GPUVMEnable == true ?
+					(HostVMEnable == true ? (GPUVMMaxPageTableLevels + 2) *
+					(HostVMMaxNonCachedPageTableLevels + 1) - 1 : GPUVMMaxPageTableLevels + 1) : 0);
+			for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+				double MaximumTvmPlus2Tr0PlusTsw;
+
+				MaximumTvmPlus2Tr0PlusTsw = (MaximumVStartup[i][j][k] - 2) * HTotal[k] /
+						PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k];
+				if (MaximumTvmPlus2Tr0PlusTsw <= MinimumTvmPlus2Tr0 + PrefetchPixelLinesTime[k] / 4) {
+					DCFCLKRequiredForPeakBandwidth = DCFCLKPerState[i];
+				} else {
+					DCFCLKRequiredForPeakBandwidth = dml_max3(DCFCLKRequiredForPeakBandwidth,
+							2 * ExtraLatencyCycles / (MaximumTvmPlus2Tr0PlusTsw -
+								MinimumTvmPlus2Tr0 -
+								PrefetchPixelLinesTime[k] / 4),
+							(2 * ExtraLatencyCycles +
+								PixelDCFCLKCyclesRequiredInPrefetch[k]) /
+								(MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0));
+				}
+			}
+			DCFCLKState[i][j] = dml_min(DCFCLKPerState[i], 1.05 *
+					dml_max(DCFCLKRequiredForAverageBandwidth, DCFCLKRequiredForPeakBandwidth));
+		}
+	}
+}
+
+unsigned int dml32_CalculateExtraLatencyBytes(unsigned int ReorderingBytes,
+		unsigned int TotalNumberOfActiveDPP,
+		unsigned int PixelChunkSizeInKByte,
+		unsigned int TotalNumberOfDCCActiveDPP,
+		unsigned int MetaChunkSize,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int NumberOfDPP[],
+		unsigned int dpte_group_bytes[],
+		double HostVMInefficiencyFactor,
+		double HostVMMinPageSize,
+		unsigned int HostVMMaxNonCachedPageTableLevels)
+{
+	unsigned int k;
+	double   ret;
+	unsigned int  HostVMDynamicLevels;
+
+	if (GPUVMEnable == true && HostVMEnable == true) {
+		if (HostVMMinPageSize < 2048)
+			HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels;
+		else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576)
+			HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1);
+		else
+			HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2);
+	} else {
+		HostVMDynamicLevels = 0;
+	}
+
+	ret = ReorderingBytes + (TotalNumberOfActiveDPP * PixelChunkSizeInKByte +
+			TotalNumberOfDCCActiveDPP * MetaChunkSize) * 1024.0;
+
+	if (GPUVMEnable == true) {
+		for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+			ret = ret + NumberOfDPP[k] * dpte_group_bytes[k] *
+					(1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactor;
+		}
+	}
+	return ret;
+}
+
+void dml32_CalculateVUpdateAndDynamicMetadataParameters(
+		unsigned int MaxInterDCNTileRepeaters,
+		double Dppclk,
+		double Dispclk,
+		double DCFClkDeepSleep,
+		double PixelClock,
+		unsigned int HTotal,
+		unsigned int VBlank,
+		unsigned int DynamicMetadataTransmittedBytes,
+		unsigned int DynamicMetadataLinesBeforeActiveRequired,
+		unsigned int InterlaceEnable,
+		bool ProgressiveToInterlaceUnitInOPP,
+
+		/* output */
+		double *TSetup,
+		double *Tdmbf,
+		double *Tdmec,
+		double *Tdmsks,
+		unsigned int *VUpdateOffsetPix,
+		double *VUpdateWidthPix,
+		double *VReadyOffsetPix)
+{
+	double TotalRepeaterDelayTime;
+
+	TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2 / Dppclk + 3 / Dispclk);
+	*VUpdateWidthPix  =
+			dml_ceil((14.0 / DCFClkDeepSleep + 12.0 / Dppclk + TotalRepeaterDelayTime) * PixelClock, 1.0);
+	*VReadyOffsetPix  = dml_ceil(dml_max(150.0 / Dppclk,
+			TotalRepeaterDelayTime + 20.0 / DCFClkDeepSleep + 10.0 / Dppclk) * PixelClock, 1.0);
+	*VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1.0);
+	*TSetup = (*VUpdateOffsetPix + *VUpdateWidthPix + *VReadyOffsetPix) / PixelClock;
+	*Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / Dispclk;
+	*Tdmec = HTotal / PixelClock;
+
+	if (DynamicMetadataLinesBeforeActiveRequired == 0)
+		*Tdmsks = VBlank * HTotal / PixelClock / 2.0;
+	else
+		*Tdmsks = DynamicMetadataLinesBeforeActiveRequired * HTotal / PixelClock;
+
+	if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false)
+		*Tdmsks = *Tdmsks / 2;
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: VUpdateWidthPix = %d\n", __func__, *VUpdateWidthPix);
+	dml_print("DML::%s: VReadyOffsetPix = %d\n", __func__, *VReadyOffsetPix);
+	dml_print("DML::%s: VUpdateOffsetPix = %d\n", __func__, *VUpdateOffsetPix);
+
+	dml_print("DML::%s: DynamicMetadataLinesBeforeActiveRequired = %d\n",
+			__func__, DynamicMetadataLinesBeforeActiveRequired);
+	dml_print("DML::%s: VBlank = %d\n", __func__, VBlank);
+	dml_print("DML::%s: HTotal = %d\n", __func__, HTotal);
+	dml_print("DML::%s: PixelClock = %f\n", __func__, PixelClock);
+	dml_print("DML::%s: Tdmsks = %f\n", __func__, *Tdmsks);
+#endif
+}
+
+double dml32_CalculateTWait(
+		unsigned int PrefetchMode,
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange,
+		bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+		bool DRRDisplay,
+		double DRAMClockChangeLatency,
+		double FCLKChangeLatency,
+		double UrgentLatency,
+		double SREnterPlusExitTime)
+{
+	double TWait = 0.0;
+
+	if (PrefetchMode == 0 &&
+			!(UseMALLForPStateChange == dm_use_mall_pstate_change_full_frame) &&
+			!(UseMALLForPStateChange == dm_use_mall_pstate_change_sub_viewport) &&
+			!(UseMALLForPStateChange == dm_use_mall_pstate_change_phantom_pipe) &&
+			!(SynchronizeDRRDisplaysForUCLKPStateChangeFinal && DRRDisplay)) {
+		TWait = dml_max3(DRAMClockChangeLatency + UrgentLatency, SREnterPlusExitTime, UrgentLatency);
+	} else if (PrefetchMode <= 1 && !(UseMALLForPStateChange == dm_use_mall_pstate_change_phantom_pipe)) {
+		TWait = dml_max3(FCLKChangeLatency + UrgentLatency, SREnterPlusExitTime, UrgentLatency);
+	} else if (PrefetchMode <= 2 && !(UseMALLForPStateChange == dm_use_mall_pstate_change_phantom_pipe)) {
+		TWait = dml_max(SREnterPlusExitTime, UrgentLatency);
+	} else {
+		TWait = UrgentLatency;
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: PrefetchMode = %d\n", __func__, PrefetchMode);
+	dml_print("DML::%s: TWait = %f\n", __func__, TWait);
+#endif
+	return TWait;
+} // CalculateTWait
+
+// Function: get_return_bw_mbps
+// Megabyte per second
+double dml32_get_return_bw_mbps(const soc_bounding_box_st *soc,
+		const int VoltageLevel,
+		const bool HostVMEnable,
+		const double DCFCLK,
+		const double FabricClock,
+		const double DRAMSpeed)
+{
+	double ReturnBW = 0.;
+	double IdealSDPPortBandwidth    = soc->return_bus_width_bytes /*mode_lib->vba.ReturnBusWidth*/ * DCFCLK;
+	double IdealFabricBandwidth     = FabricClock * soc->fabric_datapath_to_dcn_data_return_bytes;
+	double IdealDRAMBandwidth       = DRAMSpeed * soc->num_chans * soc->dram_channel_width_bytes;
+	double PixelDataOnlyReturnBW    = dml_min3(IdealSDPPortBandwidth * soc->pct_ideal_sdp_bw_after_urgent / 100,
+			IdealFabricBandwidth * soc->pct_ideal_fabric_bw_after_urgent / 100,
+			IdealDRAMBandwidth * (VoltageLevel < 2 ? soc->pct_ideal_dram_bw_after_urgent_strobe  :
+					soc->pct_ideal_dram_sdp_bw_after_urgent_pixel_only) / 100);
+	double PixelMixedWithVMDataReturnBW = dml_min3(IdealSDPPortBandwidth * soc->pct_ideal_sdp_bw_after_urgent / 100,
+			IdealFabricBandwidth * soc->pct_ideal_fabric_bw_after_urgent / 100,
+			IdealDRAMBandwidth * (VoltageLevel < 2 ? soc->pct_ideal_dram_bw_after_urgent_strobe :
+					soc->pct_ideal_dram_sdp_bw_after_urgent_pixel_only) / 100);
+
+	if (HostVMEnable != true)
+		ReturnBW = PixelDataOnlyReturnBW;
+	else
+		ReturnBW = PixelMixedWithVMDataReturnBW;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: VoltageLevel = %d\n", __func__, VoltageLevel);
+	dml_print("DML::%s: HostVMEnable = %d\n", __func__, HostVMEnable);
+	dml_print("DML::%s: DCFCLK       = %f\n", __func__, DCFCLK);
+	dml_print("DML::%s: FabricClock  = %f\n", __func__, FabricClock);
+	dml_print("DML::%s: DRAMSpeed    = %f\n", __func__, DRAMSpeed);
+	dml_print("DML::%s: IdealSDPPortBandwidth        = %f\n", __func__, IdealSDPPortBandwidth);
+	dml_print("DML::%s: IdealFabricBandwidth         = %f\n", __func__, IdealFabricBandwidth);
+	dml_print("DML::%s: IdealDRAMBandwidth           = %f\n", __func__, IdealDRAMBandwidth);
+	dml_print("DML::%s: PixelDataOnlyReturnBW        = %f\n", __func__, PixelDataOnlyReturnBW);
+	dml_print("DML::%s: PixelMixedWithVMDataReturnBW = %f\n", __func__, PixelMixedWithVMDataReturnBW);
+	dml_print("DML::%s: ReturnBW                     = %f MBps\n", __func__, ReturnBW);
+#endif
+	return ReturnBW;
+}
+
+// Function: get_return_bw_mbps_vm_only
+// Megabyte per second
+double dml32_get_return_bw_mbps_vm_only(const soc_bounding_box_st *soc,
+		const int VoltageLevel,
+		const double DCFCLK,
+		const double FabricClock,
+		const double DRAMSpeed)
+{
+	double VMDataOnlyReturnBW = dml_min3(
+			soc->return_bus_width_bytes * DCFCLK * soc->pct_ideal_sdp_bw_after_urgent / 100.0,
+			FabricClock * soc->fabric_datapath_to_dcn_data_return_bytes
+					* soc->pct_ideal_sdp_bw_after_urgent / 100.0,
+			DRAMSpeed * soc->num_chans * soc->dram_channel_width_bytes
+					* (VoltageLevel < 2 ?
+							soc->pct_ideal_dram_bw_after_urgent_strobe :
+							soc->pct_ideal_dram_sdp_bw_after_urgent_vm_only) / 100.0);
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: VoltageLevel = %d\n", __func__, VoltageLevel);
+	dml_print("DML::%s: DCFCLK       = %f\n", __func__, DCFCLK);
+	dml_print("DML::%s: FabricClock  = %f\n", __func__, FabricClock);
+	dml_print("DML::%s: DRAMSpeed    = %f\n", __func__, DRAMSpeed);
+	dml_print("DML::%s: VMDataOnlyReturnBW = %f\n", __func__, VMDataOnlyReturnBW);
+#endif
+	return VMDataOnlyReturnBW;
+}
+
+double dml32_CalculateExtraLatency(
+		unsigned int RoundTripPingLatencyCycles,
+		unsigned int ReorderingBytes,
+		double DCFCLK,
+		unsigned int TotalNumberOfActiveDPP,
+		unsigned int PixelChunkSizeInKByte,
+		unsigned int TotalNumberOfDCCActiveDPP,
+		unsigned int MetaChunkSize,
+		double ReturnBW,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int NumberOfDPP[],
+		unsigned int dpte_group_bytes[],
+		double HostVMInefficiencyFactor,
+		double HostVMMinPageSize,
+		unsigned int HostVMMaxNonCachedPageTableLevels)
+{
+	double ExtraLatencyBytes;
+	double ExtraLatency;
+
+	ExtraLatencyBytes = dml32_CalculateExtraLatencyBytes(
+			ReorderingBytes,
+			TotalNumberOfActiveDPP,
+			PixelChunkSizeInKByte,
+			TotalNumberOfDCCActiveDPP,
+			MetaChunkSize,
+			GPUVMEnable,
+			HostVMEnable,
+			NumberOfActiveSurfaces,
+			NumberOfDPP,
+			dpte_group_bytes,
+			HostVMInefficiencyFactor,
+			HostVMMinPageSize,
+			HostVMMaxNonCachedPageTableLevels);
+
+	ExtraLatency = (RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__) / DCFCLK + ExtraLatencyBytes / ReturnBW;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: RoundTripPingLatencyCycles=%d\n", __func__, RoundTripPingLatencyCycles);
+	dml_print("DML::%s: DCFCLK=%f\n", __func__, DCFCLK);
+	dml_print("DML::%s: ExtraLatencyBytes=%f\n", __func__, ExtraLatencyBytes);
+	dml_print("DML::%s: ReturnBW=%f\n", __func__, ReturnBW);
+	dml_print("DML::%s: ExtraLatency=%f\n", __func__, ExtraLatency);
+#endif
+
+	return ExtraLatency;
+} // CalculateExtraLatency
+
+bool dml32_CalculatePrefetchSchedule(
+		double HostVMInefficiencyFactor,
+		DmlPipe *myPipe,
+		unsigned int DSCDelay,
+		double DPPCLKDelaySubtotalPlusCNVCFormater,
+		double DPPCLKDelaySCL,
+		double DPPCLKDelaySCLLBOnly,
+		double DPPCLKDelayCNVCCursor,
+		double DISPCLKDelaySubtotal,
+		unsigned int DPP_RECOUT_WIDTH,
+		enum output_format_class OutputFormat,
+		unsigned int MaxInterDCNTileRepeaters,
+		unsigned int VStartup,
+		unsigned int MaxVStartup,
+		unsigned int GPUVMPageTableLevels,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		double HostVMMinPageSize,
+		bool DynamicMetadataEnable,
+		bool DynamicMetadataVMEnabled,
+		int DynamicMetadataLinesBeforeActiveRequired,
+		unsigned int DynamicMetadataTransmittedBytes,
+		double UrgentLatency,
+		double UrgentExtraLatency,
+		double TCalc,
+		unsigned int PDEAndMetaPTEBytesFrame,
+		unsigned int MetaRowByte,
+		unsigned int PixelPTEBytesPerRow,
+		double PrefetchSourceLinesY,
+		unsigned int SwathWidthY,
+		unsigned int VInitPreFillY,
+		unsigned int MaxNumSwathY,
+		double PrefetchSourceLinesC,
+		unsigned int SwathWidthC,
+		unsigned int VInitPreFillC,
+		unsigned int MaxNumSwathC,
+		unsigned int swath_width_luma_ub,
+		unsigned int swath_width_chroma_ub,
+		unsigned int SwathHeightY,
+		unsigned int SwathHeightC,
+		double TWait,
+		/* Output */
+		double   *DSTXAfterScaler,
+		double   *DSTYAfterScaler,
+		double *DestinationLinesForPrefetch,
+		double *PrefetchBandwidth,
+		double *DestinationLinesToRequestVMInVBlank,
+		double *DestinationLinesToRequestRowInVBlank,
+		double *VRatioPrefetchY,
+		double *VRatioPrefetchC,
+		double *RequiredPrefetchPixDataBWLuma,
+		double *RequiredPrefetchPixDataBWChroma,
+		bool   *NotEnoughTimeForDynamicMetadata,
+		double *Tno_bw,
+		double *prefetch_vmrow_bw,
+		double *Tdmdl_vm,
+		double *Tdmdl,
+		double *TSetup,
+		unsigned int   *VUpdateOffsetPix,
+		double   *VUpdateWidthPix,
+		double   *VReadyOffsetPix)
+{
+	bool MyError = false;
+	unsigned int DPPCycles, DISPCLKCycles;
+	double DSTTotalPixelsAfterScaler;
+	double LineTime;
+	double dst_y_prefetch_equ;
+	double prefetch_bw_oto;
+	double Tvm_oto;
+	double Tr0_oto;
+	double Tvm_oto_lines;
+	double Tr0_oto_lines;
+	double dst_y_prefetch_oto;
+	double TimeForFetchingMetaPTE = 0;
+	double TimeForFetchingRowInVBlank = 0;
+	double LinesToRequestPrefetchPixelData = 0;
+	unsigned int HostVMDynamicLevelsTrips;
+	double  trip_to_mem;
+	double  Tvm_trips;
+	double  Tr0_trips;
+	double  Tvm_trips_rounded;
+	double  Tr0_trips_rounded;
+	double  Lsw_oto;
+	double  Tpre_rounded;
+	double  prefetch_bw_equ;
+	double  Tvm_equ;
+	double  Tr0_equ;
+	double  Tdmbf;
+	double  Tdmec;
+	double  Tdmsks;
+	double  prefetch_sw_bytes;
+	double  bytes_pp;
+	double  dep_bytes;
+	unsigned int max_vratio_pre = __DML_MAX_VRATIO_PRE__;
+	double  min_Lsw;
+	double  Tsw_est1 = 0;
+	double  Tsw_est3 = 0;
+
+	if (GPUVMEnable == true && HostVMEnable == true)
+		HostVMDynamicLevelsTrips = HostVMMaxNonCachedPageTableLevels;
+	else
+		HostVMDynamicLevelsTrips = 0;
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: GPUVMEnable = %d\n", __func__, GPUVMEnable);
+	dml_print("DML::%s: GPUVMPageTableLevels = %d\n", __func__, GPUVMPageTableLevels);
+	dml_print("DML::%s: DCCEnable = %d\n", __func__, myPipe->DCCEnable);
+	dml_print("DML::%s: HostVMEnable=%d HostVMInefficiencyFactor=%f\n",
+			__func__, HostVMEnable, HostVMInefficiencyFactor);
+#endif
+	dml32_CalculateVUpdateAndDynamicMetadataParameters(
+			MaxInterDCNTileRepeaters,
+			myPipe->Dppclk,
+			myPipe->Dispclk,
+			myPipe->DCFClkDeepSleep,
+			myPipe->PixelClock,
+			myPipe->HTotal,
+			myPipe->VBlank,
+			DynamicMetadataTransmittedBytes,
+			DynamicMetadataLinesBeforeActiveRequired,
+			myPipe->InterlaceEnable,
+			myPipe->ProgressiveToInterlaceUnitInOPP,
+			TSetup,
+
+			/* output */
+			&Tdmbf,
+			&Tdmec,
+			&Tdmsks,
+			VUpdateOffsetPix,
+			VUpdateWidthPix,
+			VReadyOffsetPix);
+
+	LineTime = myPipe->HTotal / myPipe->PixelClock;
+	trip_to_mem = UrgentLatency;
+	Tvm_trips = UrgentExtraLatency + trip_to_mem * (GPUVMPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1);
+
+	if (DynamicMetadataVMEnabled == true)
+		*Tdmdl = TWait + Tvm_trips + trip_to_mem;
+	else
+		*Tdmdl = TWait + UrgentExtraLatency;
+
+#ifdef __DML_VBA_ALLOW_DELTA__
+	if (DynamicMetadataEnable == false)
+		*Tdmdl = 0.0;
+#endif
+
+	if (DynamicMetadataEnable == true) {
+		if (VStartup * LineTime < *TSetup + *Tdmdl + Tdmbf + Tdmec + Tdmsks) {
+			*NotEnoughTimeForDynamicMetadata = true;
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: Not Enough Time for Dynamic Meta!\n", __func__);
+			dml_print("DML::%s: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n",
+					__func__, Tdmbf);
+			dml_print("DML::%s: Tdmec: %fus - time dio takes to transfer dmd\n", __func__, Tdmec);
+			dml_print("DML::%s: Tdmsks: %fus - time before active dmd must complete transmission at dio\n",
+					__func__, Tdmsks);
+			dml_print("DML::%s: Tdmdl: %fus - time for fabric to become ready and fetch dmd\n",
+					__func__, *Tdmdl);
+#endif
+		} else {
+			*NotEnoughTimeForDynamicMetadata = false;
+		}
+	} else {
+		*NotEnoughTimeForDynamicMetadata = false;
+	}
+
+	*Tdmdl_vm =  (DynamicMetadataEnable == true && DynamicMetadataVMEnabled == true &&
+			GPUVMEnable == true ? TWait + Tvm_trips : 0);
+
+	if (myPipe->ScalerEnabled)
+		DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCL;
+	else
+		DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCLLBOnly;
+
+	DPPCycles = DPPCycles + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor;
+
+	DISPCLKCycles = DISPCLKDelaySubtotal;
+
+	if (myPipe->Dppclk == 0.0 || myPipe->Dispclk == 0.0)
+		return true;
+
+	*DSTXAfterScaler = DPPCycles * myPipe->PixelClock / myPipe->Dppclk + DISPCLKCycles *
+			myPipe->PixelClock / myPipe->Dispclk + DSCDelay;
+
+	*DSTXAfterScaler = *DSTXAfterScaler + (myPipe->ODMMode != dm_odm_combine_mode_disabled ? 18 : 0)
+			+ (myPipe->DPPPerSurface - 1) * DPP_RECOUT_WIDTH
+			+ ((myPipe->ODMMode == dm_odm_split_mode_1to2 || myPipe->ODMMode == dm_odm_mode_mso_1to2) ?
+					myPipe->HActive / 2 : 0)
+			+ ((myPipe->ODMMode == dm_odm_mode_mso_1to4) ? myPipe->HActive * 3 / 4 : 0);
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DPPCycles: %d\n", __func__, DPPCycles);
+	dml_print("DML::%s: PixelClock: %f\n", __func__, myPipe->PixelClock);
+	dml_print("DML::%s: Dppclk: %f\n", __func__, myPipe->Dppclk);
+	dml_print("DML::%s: DISPCLKCycles: %d\n", __func__, DISPCLKCycles);
+	dml_print("DML::%s: DISPCLK: %f\n", __func__,  myPipe->Dispclk);
+	dml_print("DML::%s: DSCDelay: %d\n", __func__,  DSCDelay);
+	dml_print("DML::%s: ODMMode: %d\n", __func__,  myPipe->ODMMode);
+	dml_print("DML::%s: DPP_RECOUT_WIDTH: %d\n", __func__, DPP_RECOUT_WIDTH);
+	dml_print("DML::%s: DSTXAfterScaler: %d\n", __func__,  *DSTXAfterScaler);
+#endif
+
+	if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && myPipe->ProgressiveToInterlaceUnitInOPP))
+		*DSTYAfterScaler = 1;
+	else
+		*DSTYAfterScaler = 0;
+
+	DSTTotalPixelsAfterScaler = *DSTYAfterScaler * myPipe->HTotal + *DSTXAfterScaler;
+	*DSTYAfterScaler = dml_floor(DSTTotalPixelsAfterScaler / myPipe->HTotal, 1);
+	*DSTXAfterScaler = DSTTotalPixelsAfterScaler - ((double) (*DSTYAfterScaler * myPipe->HTotal));
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DSTXAfterScaler: %d (final)\n", __func__,  *DSTXAfterScaler);
+	dml_print("DML::%s: DSTYAfterScaler: %d (final)\n", __func__, *DSTYAfterScaler);
+#endif
+
+	MyError = false;
+
+	Tr0_trips = trip_to_mem * (HostVMDynamicLevelsTrips + 1);
+
+	if (GPUVMEnable == true) {
+		Tvm_trips_rounded = dml_ceil(4.0 * Tvm_trips / LineTime, 1.0) / 4.0 * LineTime;
+		Tr0_trips_rounded = dml_ceil(4.0 * Tr0_trips / LineTime, 1.0) / 4.0 * LineTime;
+		if (GPUVMPageTableLevels >= 3) {
+			*Tno_bw = UrgentExtraLatency + trip_to_mem *
+					(double) ((GPUVMPageTableLevels - 2) * (HostVMDynamicLevelsTrips + 1) - 1);
+		} else if (GPUVMPageTableLevels == 1 && myPipe->DCCEnable != true) {
+			Tr0_trips_rounded = dml_ceil(4.0 * UrgentExtraLatency / LineTime, 1.0) /
+					4.0 * LineTime; // VBA_ERROR
+			*Tno_bw = UrgentExtraLatency;
+		} else {
+			*Tno_bw = 0;
+		}
+	} else if (myPipe->DCCEnable == true) {
+		Tvm_trips_rounded = LineTime / 4.0;
+		Tr0_trips_rounded = dml_ceil(4.0 * Tr0_trips / LineTime, 1.0) / 4.0 * LineTime;
+		*Tno_bw = 0;
+	} else {
+		Tvm_trips_rounded = LineTime / 4.0;
+		Tr0_trips_rounded = LineTime / 2.0;
+		*Tno_bw = 0;
+	}
+	Tvm_trips_rounded = dml_max(Tvm_trips_rounded, LineTime / 4.0);
+	Tr0_trips_rounded = dml_max(Tr0_trips_rounded, LineTime / 4.0);
+
+	if (myPipe->SourcePixelFormat == dm_420_8 || myPipe->SourcePixelFormat == dm_420_10
+			|| myPipe->SourcePixelFormat == dm_420_12) {
+		bytes_pp = myPipe->BytePerPixelY + myPipe->BytePerPixelC / 4;
+	} else {
+		bytes_pp = myPipe->BytePerPixelY + myPipe->BytePerPixelC;
+	}
+
+	prefetch_sw_bytes = PrefetchSourceLinesY * swath_width_luma_ub * myPipe->BytePerPixelY
+			+ PrefetchSourceLinesC * swath_width_chroma_ub * myPipe->BytePerPixelC;
+	prefetch_bw_oto = dml_max(bytes_pp * myPipe->PixelClock / myPipe->DPPPerSurface,
+			prefetch_sw_bytes / (dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime));
+
+	min_Lsw = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) / max_vratio_pre;
+	min_Lsw = dml_max(min_Lsw, 1.0);
+	Lsw_oto = dml_ceil(4.0 * dml_max(prefetch_sw_bytes / prefetch_bw_oto / LineTime, min_Lsw), 1.0) / 4.0;
+
+	if (GPUVMEnable == true) {
+		Tvm_oto = dml_max3(
+				Tvm_trips,
+				*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto,
+				LineTime / 4.0);
+	} else
+		Tvm_oto = LineTime / 4.0;
+
+	if ((GPUVMEnable == true || myPipe->DCCEnable == true)) {
+		Tr0_oto = dml_max4(
+				Tr0_trips,
+				(MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_oto,
+				(LineTime - Tvm_oto)/2.0,
+				LineTime / 4.0);
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: Tr0_oto max0 = %f\n", __func__,
+				(MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_oto);
+		dml_print("DML::%s: Tr0_oto max1 = %f\n", __func__, Tr0_trips);
+		dml_print("DML::%s: Tr0_oto max2 = %f\n", __func__, LineTime - Tvm_oto);
+		dml_print("DML::%s: Tr0_oto max3 = %f\n", __func__, LineTime / 4);
+#endif
+	} else
+		Tr0_oto = (LineTime - Tvm_oto) / 2.0;
+
+	Tvm_oto_lines = dml_ceil(4.0 * Tvm_oto / LineTime, 1) / 4.0;
+	Tr0_oto_lines = dml_ceil(4.0 * Tr0_oto / LineTime, 1) / 4.0;
+	dst_y_prefetch_oto = Tvm_oto_lines + 2 * Tr0_oto_lines + Lsw_oto;
+
+	dst_y_prefetch_equ = VStartup - (*TSetup + dml_max(TWait + TCalc, *Tdmdl)) / LineTime -
+			(*DSTYAfterScaler + (double) *DSTXAfterScaler / (double) myPipe->HTotal);
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: HTotal = %d\n", __func__, myPipe->HTotal);
+	dml_print("DML::%s: min_Lsw = %f\n", __func__, min_Lsw);
+	dml_print("DML::%s: *Tno_bw = %f\n", __func__, *Tno_bw);
+	dml_print("DML::%s: UrgentExtraLatency = %f\n", __func__, UrgentExtraLatency);
+	dml_print("DML::%s: trip_to_mem = %f\n", __func__, trip_to_mem);
+	dml_print("DML::%s: BytePerPixelY = %d\n", __func__, myPipe->BytePerPixelY);
+	dml_print("DML::%s: PrefetchSourceLinesY = %f\n", __func__, PrefetchSourceLinesY);
+	dml_print("DML::%s: swath_width_luma_ub = %d\n", __func__, swath_width_luma_ub);
+	dml_print("DML::%s: BytePerPixelC = %d\n", __func__, myPipe->BytePerPixelC);
+	dml_print("DML::%s: PrefetchSourceLinesC = %f\n", __func__, PrefetchSourceLinesC);
+	dml_print("DML::%s: swath_width_chroma_ub = %d\n", __func__, swath_width_chroma_ub);
+	dml_print("DML::%s: prefetch_sw_bytes = %f\n", __func__, prefetch_sw_bytes);
+	dml_print("DML::%s: bytes_pp = %f\n", __func__, bytes_pp);
+	dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d\n", __func__, PDEAndMetaPTEBytesFrame);
+	dml_print("DML::%s: MetaRowByte = %d\n", __func__, MetaRowByte);
+	dml_print("DML::%s: PixelPTEBytesPerRow = %d\n", __func__, PixelPTEBytesPerRow);
+	dml_print("DML::%s: HostVMInefficiencyFactor = %f\n", __func__, HostVMInefficiencyFactor);
+	dml_print("DML::%s: Tvm_trips = %f\n", __func__, Tvm_trips);
+	dml_print("DML::%s: Tr0_trips = %f\n", __func__, Tr0_trips);
+	dml_print("DML::%s: prefetch_bw_oto = %f\n", __func__, prefetch_bw_oto);
+	dml_print("DML::%s: Tr0_oto = %f\n", __func__, Tr0_oto);
+	dml_print("DML::%s: Tvm_oto = %f\n", __func__, Tvm_oto);
+	dml_print("DML::%s: Tvm_oto_lines = %f\n", __func__, Tvm_oto_lines);
+	dml_print("DML::%s: Tr0_oto_lines = %f\n", __func__, Tr0_oto_lines);
+	dml_print("DML::%s: Lsw_oto = %f\n", __func__, Lsw_oto);
+	dml_print("DML::%s: dst_y_prefetch_oto = %f\n", __func__, dst_y_prefetch_oto);
+	dml_print("DML::%s: dst_y_prefetch_equ = %f\n", __func__, dst_y_prefetch_equ);
+#endif
+
+	dst_y_prefetch_equ = dml_floor(4.0 * (dst_y_prefetch_equ + 0.125), 1) / 4.0;
+	Tpre_rounded = dst_y_prefetch_equ * LineTime;
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: dst_y_prefetch_equ: %f (after round)\n", __func__, dst_y_prefetch_equ);
+	dml_print("DML::%s: LineTime: %f\n", __func__, LineTime);
+	dml_print("DML::%s: VStartup: %d\n", __func__, VStartup);
+	dml_print("DML::%s: Tvstartup: %fus - time between vstartup and first pixel of active\n",
+			__func__, VStartup * LineTime);
+	dml_print("DML::%s: TSetup: %fus - time from vstartup to vready\n", __func__, *TSetup);
+	dml_print("DML::%s: TCalc: %fus - time for calculations in dchub starting at vready\n", __func__, TCalc);
+	dml_print("DML::%s: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n", __func__, Tdmbf);
+	dml_print("DML::%s: Tdmec: %fus - time dio takes to transfer dmd\n", __func__, Tdmec);
+	dml_print("DML::%s: Tdmdl_vm: %fus - time for vm stages of dmd\n", __func__, *Tdmdl_vm);
+	dml_print("DML::%s: Tdmdl: %fus - time for fabric to become ready and fetch dmd\n", __func__, *Tdmdl);
+	dml_print("DML::%s: DSTYAfterScaler: %d lines - number of lines of pipeline and buffer delay after scaler\n",
+			__func__, *DSTYAfterScaler);
+#endif
+	dep_bytes = dml_max(PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor,
+			MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor);
+
+	if (prefetch_sw_bytes < dep_bytes)
+		prefetch_sw_bytes = 2 * dep_bytes;
+
+	*PrefetchBandwidth = 0;
+	*DestinationLinesToRequestVMInVBlank = 0;
+	*DestinationLinesToRequestRowInVBlank = 0;
+	*VRatioPrefetchY = 0;
+	*VRatioPrefetchC = 0;
+	*RequiredPrefetchPixDataBWLuma = 0;
+	if (dst_y_prefetch_equ > 1) {
+		double PrefetchBandwidth1;
+		double PrefetchBandwidth2;
+		double PrefetchBandwidth3;
+		double PrefetchBandwidth4;
+
+		if (Tpre_rounded - *Tno_bw > 0) {
+			PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte
+					+ 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor
+					+ prefetch_sw_bytes) / (Tpre_rounded - *Tno_bw);
+			Tsw_est1 = prefetch_sw_bytes / PrefetchBandwidth1;
+		} else
+			PrefetchBandwidth1 = 0;
+
+		if (VStartup == MaxVStartup && (Tsw_est1 / LineTime < min_Lsw)
+				&& Tpre_rounded - min_Lsw * LineTime - 0.75 * LineTime - *Tno_bw > 0) {
+			PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte
+					+ 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor)
+					/ (Tpre_rounded - min_Lsw * LineTime - 0.75 * LineTime - *Tno_bw);
+		}
+
+		if (Tpre_rounded - *Tno_bw - 2 * Tr0_trips_rounded > 0)
+			PrefetchBandwidth2 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + prefetch_sw_bytes) /
+			(Tpre_rounded - *Tno_bw - 2 * Tr0_trips_rounded);
+		else
+			PrefetchBandwidth2 = 0;
+
+		if (Tpre_rounded - Tvm_trips_rounded > 0) {
+			PrefetchBandwidth3 = (2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor
+					+ prefetch_sw_bytes) / (Tpre_rounded - Tvm_trips_rounded);
+			Tsw_est3 = prefetch_sw_bytes / PrefetchBandwidth3;
+		} else
+			PrefetchBandwidth3 = 0;
+
+
+		if (VStartup == MaxVStartup &&
+				(Tsw_est3 / LineTime < min_Lsw) && Tpre_rounded - min_Lsw * LineTime - 0.75 *
+				LineTime - Tvm_trips_rounded > 0) {
+			PrefetchBandwidth3 = (2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor)
+					/ (Tpre_rounded - min_Lsw * LineTime - 0.75 * LineTime - Tvm_trips_rounded);
+		}
+
+		if (Tpre_rounded - Tvm_trips_rounded - 2 * Tr0_trips_rounded > 0) {
+			PrefetchBandwidth4 = prefetch_sw_bytes /
+					(Tpre_rounded - Tvm_trips_rounded - 2 * Tr0_trips_rounded);
+		} else {
+			PrefetchBandwidth4 = 0;
+		}
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: Tpre_rounded: %f\n", __func__, Tpre_rounded);
+		dml_print("DML::%s: Tno_bw: %f\n", __func__, *Tno_bw);
+		dml_print("DML::%s: Tvm_trips_rounded: %f\n", __func__, Tvm_trips_rounded);
+		dml_print("DML::%s: Tsw_est1: %f\n", __func__, Tsw_est1);
+		dml_print("DML::%s: Tsw_est3: %f\n", __func__, Tsw_est3);
+		dml_print("DML::%s: PrefetchBandwidth1: %f\n", __func__, PrefetchBandwidth1);
+		dml_print("DML::%s: PrefetchBandwidth2: %f\n", __func__, PrefetchBandwidth2);
+		dml_print("DML::%s: PrefetchBandwidth3: %f\n", __func__, PrefetchBandwidth3);
+		dml_print("DML::%s: PrefetchBandwidth4: %f\n", __func__, PrefetchBandwidth4);
+#endif
+		{
+			bool Case1OK;
+			bool Case2OK;
+			bool Case3OK;
+
+			if (PrefetchBandwidth1 > 0) {
+				if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth1
+						>= Tvm_trips_rounded
+						&& (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor)
+								/ PrefetchBandwidth1 >= Tr0_trips_rounded) {
+					Case1OK = true;
+				} else {
+					Case1OK = false;
+				}
+			} else {
+				Case1OK = false;
+			}
+
+			if (PrefetchBandwidth2 > 0) {
+				if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth2
+						>= Tvm_trips_rounded
+						&& (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor)
+						/ PrefetchBandwidth2 < Tr0_trips_rounded) {
+					Case2OK = true;
+				} else {
+					Case2OK = false;
+				}
+			} else {
+				Case2OK = false;
+			}
+
+			if (PrefetchBandwidth3 > 0) {
+				if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth3 <
+						Tvm_trips_rounded && (MetaRowByte + PixelPTEBytesPerRow *
+								HostVMInefficiencyFactor) / PrefetchBandwidth3 >=
+								Tr0_trips_rounded) {
+					Case3OK = true;
+				} else {
+					Case3OK = false;
+				}
+			} else {
+				Case3OK = false;
+			}
+
+			if (Case1OK)
+				prefetch_bw_equ = PrefetchBandwidth1;
+			else if (Case2OK)
+				prefetch_bw_equ = PrefetchBandwidth2;
+			else if (Case3OK)
+				prefetch_bw_equ = PrefetchBandwidth3;
+			else
+				prefetch_bw_equ = PrefetchBandwidth4;
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: Case1OK: %d\n", __func__, Case1OK);
+			dml_print("DML::%s: Case2OK: %d\n", __func__, Case2OK);
+			dml_print("DML::%s: Case3OK: %d\n", __func__, Case3OK);
+			dml_print("DML::%s: prefetch_bw_equ: %f\n", __func__, prefetch_bw_equ);
+#endif
+
+			if (prefetch_bw_equ > 0) {
+				if (GPUVMEnable == true) {
+					Tvm_equ = dml_max3(*Tno_bw + PDEAndMetaPTEBytesFrame *
+							HostVMInefficiencyFactor / prefetch_bw_equ,
+							Tvm_trips, LineTime / 4);
+				} else {
+					Tvm_equ = LineTime / 4;
+				}
+
+				if ((GPUVMEnable == true || myPipe->DCCEnable == true)) {
+					Tr0_equ = dml_max4((MetaRowByte + PixelPTEBytesPerRow *
+							HostVMInefficiencyFactor) / prefetch_bw_equ, Tr0_trips,
+							(LineTime - Tvm_equ) / 2, LineTime / 4);
+				} else {
+					Tr0_equ = (LineTime - Tvm_equ) / 2;
+				}
+			} else {
+				Tvm_equ = 0;
+				Tr0_equ = 0;
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML: prefetch_bw_equ equals 0! %s:%d\n", __FILE__, __LINE__);
+#endif
+			}
+		}
+
+		if (dst_y_prefetch_oto < dst_y_prefetch_equ) {
+			*DestinationLinesForPrefetch = dst_y_prefetch_oto;
+			TimeForFetchingMetaPTE = Tvm_oto;
+			TimeForFetchingRowInVBlank = Tr0_oto;
+			*PrefetchBandwidth = prefetch_bw_oto;
+		} else {
+			*DestinationLinesForPrefetch = dst_y_prefetch_equ;
+			TimeForFetchingMetaPTE = Tvm_equ;
+			TimeForFetchingRowInVBlank = Tr0_equ;
+			*PrefetchBandwidth = prefetch_bw_equ;
+		}
+
+		*DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.0;
+
+		*DestinationLinesToRequestRowInVBlank =
+				dml_ceil(4.0 * TimeForFetchingRowInVBlank / LineTime, 1.0) / 4.0;
+
+		LinesToRequestPrefetchPixelData = *DestinationLinesForPrefetch -
+				*DestinationLinesToRequestVMInVBlank - 2 * *DestinationLinesToRequestRowInVBlank;
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: DestinationLinesForPrefetch = %f\n", __func__, *DestinationLinesForPrefetch);
+		dml_print("DML::%s: DestinationLinesToRequestVMInVBlank = %f\n",
+				__func__, *DestinationLinesToRequestVMInVBlank);
+		dml_print("DML::%s: TimeForFetchingRowInVBlank = %f\n", __func__, TimeForFetchingRowInVBlank);
+		dml_print("DML::%s: LineTime = %f\n", __func__, LineTime);
+		dml_print("DML::%s: DestinationLinesToRequestRowInVBlank = %f\n",
+				__func__, *DestinationLinesToRequestRowInVBlank);
+		dml_print("DML::%s: PrefetchSourceLinesY = %f\n", __func__, PrefetchSourceLinesY);
+		dml_print("DML::%s: LinesToRequestPrefetchPixelData = %f\n", __func__, LinesToRequestPrefetchPixelData);
+#endif
+
+		if (LinesToRequestPrefetchPixelData >= 1 && prefetch_bw_equ > 0) {
+			*VRatioPrefetchY = (double) PrefetchSourceLinesY / LinesToRequestPrefetchPixelData;
+			*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: VRatioPrefetchY = %f\n", __func__, *VRatioPrefetchY);
+			dml_print("DML::%s: SwathHeightY = %d\n", __func__, SwathHeightY);
+			dml_print("DML::%s: VInitPreFillY = %d\n", __func__, VInitPreFillY);
+#endif
+			if ((SwathHeightY > 4) && (VInitPreFillY > 3)) {
+				if (LinesToRequestPrefetchPixelData > (VInitPreFillY - 3.0) / 2.0) {
+					*VRatioPrefetchY =
+							dml_max((double) PrefetchSourceLinesY /
+									LinesToRequestPrefetchPixelData,
+									(double) MaxNumSwathY * SwathHeightY /
+									(LinesToRequestPrefetchPixelData -
+									(VInitPreFillY - 3.0) / 2.0));
+					*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
+				} else {
+					MyError = true;
+					*VRatioPrefetchY = 0;
+				}
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: VRatioPrefetchY = %f\n", __func__, *VRatioPrefetchY);
+				dml_print("DML::%s: PrefetchSourceLinesY = %f\n", __func__, PrefetchSourceLinesY);
+				dml_print("DML::%s: MaxNumSwathY = %d\n", __func__, MaxNumSwathY);
+#endif
+			}
+
+			*VRatioPrefetchC = (double) PrefetchSourceLinesC / LinesToRequestPrefetchPixelData;
+			*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: VRatioPrefetchC = %f\n", __func__, *VRatioPrefetchC);
+			dml_print("DML::%s: SwathHeightC = %d\n", __func__, SwathHeightC);
+			dml_print("DML::%s: VInitPreFillC = %d\n", __func__, VInitPreFillC);
+#endif
+			if ((SwathHeightC > 4)) {
+				if (LinesToRequestPrefetchPixelData > (VInitPreFillC - 3.0) / 2.0) {
+					*VRatioPrefetchC =
+						dml_max(*VRatioPrefetchC,
+							(double) MaxNumSwathC * SwathHeightC /
+							(LinesToRequestPrefetchPixelData -
+							(VInitPreFillC - 3.0) / 2.0));
+					*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
+				} else {
+					MyError = true;
+					*VRatioPrefetchC = 0;
+				}
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: VRatioPrefetchC = %f\n", __func__, *VRatioPrefetchC);
+				dml_print("DML::%s: PrefetchSourceLinesC = %f\n", __func__, PrefetchSourceLinesC);
+				dml_print("DML::%s: MaxNumSwathC = %d\n", __func__, MaxNumSwathC);
+#endif
+			}
+
+			*RequiredPrefetchPixDataBWLuma = (double) PrefetchSourceLinesY
+					/ LinesToRequestPrefetchPixelData * myPipe->BytePerPixelY * swath_width_luma_ub
+					/ LineTime;
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: BytePerPixelY = %d\n", __func__, myPipe->BytePerPixelY);
+			dml_print("DML::%s: swath_width_luma_ub = %d\n", __func__, swath_width_luma_ub);
+			dml_print("DML::%s: LineTime = %f\n", __func__, LineTime);
+			dml_print("DML::%s: RequiredPrefetchPixDataBWLuma = %f\n",
+					__func__, *RequiredPrefetchPixDataBWLuma);
+#endif
+			*RequiredPrefetchPixDataBWChroma = (double) PrefetchSourceLinesC /
+					LinesToRequestPrefetchPixelData
+					* myPipe->BytePerPixelC
+					* swath_width_chroma_ub / LineTime;
+		} else {
+			MyError = true;
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML:%s: MyErr set. LinesToRequestPrefetchPixelData: %f, should be > 0\n",
+					__func__, LinesToRequestPrefetchPixelData);
+#endif
+			*VRatioPrefetchY = 0;
+			*VRatioPrefetchC = 0;
+			*RequiredPrefetchPixDataBWLuma = 0;
+			*RequiredPrefetchPixDataBWChroma = 0;
+		}
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML: Tpre: %fus - sum of time to request meta pte, 2 x data pte + meta data, swaths\n",
+			(double)LinesToRequestPrefetchPixelData * LineTime +
+			2.0*TimeForFetchingRowInVBlank + TimeForFetchingMetaPTE);
+		dml_print("DML:  Tvm: %fus - time to fetch page tables for meta surface\n", TimeForFetchingMetaPTE);
+		dml_print("DML: To: %fus - time for propagation from scaler to optc\n",
+			(*DSTYAfterScaler + ((double) (*DSTXAfterScaler) / (double) myPipe->HTotal)) * LineTime);
+		dml_print("DML: Tvstartup - TSetup - Tcalc - Twait - Tpre - To > 0\n");
+		dml_print("DML: Tslack(pre): %fus - time left over in schedule\n", VStartup * LineTime -
+			TimeForFetchingMetaPTE - 2*TimeForFetchingRowInVBlank - (*DSTYAfterScaler +
+			((double) (*DSTXAfterScaler) / (double) myPipe->HTotal)) * LineTime - TWait - TCalc - *TSetup);
+		dml_print("DML: row_bytes = dpte_row_bytes (per_pipe) = PixelPTEBytesPerRow = : %d\n",
+				PixelPTEBytesPerRow);
+#endif
+	} else {
+		MyError = true;
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: MyErr set, dst_y_prefetch_equ = %f (should be > 1)\n",
+				__func__, dst_y_prefetch_equ);
+#endif
+	}
+
+	{
+		double prefetch_vm_bw;
+		double prefetch_row_bw;
+
+		if (PDEAndMetaPTEBytesFrame == 0) {
+			prefetch_vm_bw = 0;
+		} else if (*DestinationLinesToRequestVMInVBlank > 0) {
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d\n", __func__, PDEAndMetaPTEBytesFrame);
+			dml_print("DML::%s: HostVMInefficiencyFactor = %f\n", __func__, HostVMInefficiencyFactor);
+			dml_print("DML::%s: DestinationLinesToRequestVMInVBlank = %f\n",
+					__func__, *DestinationLinesToRequestVMInVBlank);
+			dml_print("DML::%s: LineTime = %f\n", __func__, LineTime);
+#endif
+			prefetch_vm_bw = PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor /
+					(*DestinationLinesToRequestVMInVBlank * LineTime);
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: prefetch_vm_bw = %f\n", __func__, prefetch_vm_bw);
+#endif
+		} else {
+			prefetch_vm_bw = 0;
+			MyError = true;
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: MyErr set. DestinationLinesToRequestVMInVBlank=%f (should be > 0)\n",
+					__func__, *DestinationLinesToRequestVMInVBlank);
+#endif
+		}
+
+		if (MetaRowByte + PixelPTEBytesPerRow == 0) {
+			prefetch_row_bw = 0;
+		} else if (*DestinationLinesToRequestRowInVBlank > 0) {
+			prefetch_row_bw = (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) /
+					(*DestinationLinesToRequestRowInVBlank * LineTime);
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: MetaRowByte = %d\n", __func__, MetaRowByte);
+			dml_print("DML::%s: PixelPTEBytesPerRow = %d\n", __func__, PixelPTEBytesPerRow);
+			dml_print("DML::%s: DestinationLinesToRequestRowInVBlank = %f\n",
+					__func__, *DestinationLinesToRequestRowInVBlank);
+			dml_print("DML::%s: prefetch_row_bw = %f\n", __func__, prefetch_row_bw);
+#endif
+		} else {
+			prefetch_row_bw = 0;
+			MyError = true;
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: MyErr set. DestinationLinesToRequestRowInVBlank=%f (should be > 0)\n",
+					__func__, *DestinationLinesToRequestRowInVBlank);
+#endif
+		}
+
+		*prefetch_vmrow_bw = dml_max(prefetch_vm_bw, prefetch_row_bw);
+	}
+
+	if (MyError) {
+		*PrefetchBandwidth = 0;
+		TimeForFetchingMetaPTE = 0;
+		TimeForFetchingRowInVBlank = 0;
+		*DestinationLinesToRequestVMInVBlank = 0;
+		*DestinationLinesToRequestRowInVBlank = 0;
+		*DestinationLinesForPrefetch = 0;
+		LinesToRequestPrefetchPixelData = 0;
+		*VRatioPrefetchY = 0;
+		*VRatioPrefetchC = 0;
+		*RequiredPrefetchPixDataBWLuma = 0;
+		*RequiredPrefetchPixDataBWChroma = 0;
+	}
+
+	return MyError;
+} // CalculatePrefetchSchedule
+
+void dml32_CalculateFlipSchedule(
+		double HostVMInefficiencyFactor,
+		double UrgentExtraLatency,
+		double UrgentLatency,
+		unsigned int GPUVMMaxPageTableLevels,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		bool GPUVMEnable,
+		double HostVMMinPageSize,
+		double PDEAndMetaPTEBytesPerFrame,
+		double MetaRowBytes,
+		double DPTEBytesPerRow,
+		double BandwidthAvailableForImmediateFlip,
+		unsigned int TotImmediateFlipBytes,
+		enum source_format_class SourcePixelFormat,
+		double LineTime,
+		double VRatio,
+		double VRatioChroma,
+		double Tno_bw,
+		bool DCCEnable,
+		unsigned int dpte_row_height,
+		unsigned int meta_row_height,
+		unsigned int dpte_row_height_chroma,
+		unsigned int meta_row_height_chroma,
+		bool    use_one_row_for_frame_flip,
+
+		/* Output */
+		double *DestinationLinesToRequestVMInImmediateFlip,
+		double *DestinationLinesToRequestRowInImmediateFlip,
+		double *final_flip_bw,
+		bool *ImmediateFlipSupportedForPipe)
+{
+	double min_row_time = 0.0;
+	unsigned int HostVMDynamicLevelsTrips;
+	double TimeForFetchingMetaPTEImmediateFlip;
+	double TimeForFetchingRowInVBlankImmediateFlip;
+	double ImmediateFlipBW;
+
+	if (GPUVMEnable == true && HostVMEnable == true)
+		HostVMDynamicLevelsTrips = HostVMMaxNonCachedPageTableLevels;
+	else
+		HostVMDynamicLevelsTrips = 0;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: TotImmediateFlipBytes = %d\n", __func__, TotImmediateFlipBytes);
+	dml_print("DML::%s: BandwidthAvailableForImmediateFlip = %f\n", __func__, BandwidthAvailableForImmediateFlip);
+#endif
+
+	if (TotImmediateFlipBytes > 0) {
+		if (use_one_row_for_frame_flip) {
+			ImmediateFlipBW = (PDEAndMetaPTEBytesPerFrame + MetaRowBytes + 2 * DPTEBytesPerRow) *
+					BandwidthAvailableForImmediateFlip / TotImmediateFlipBytes;
+		} else {
+			ImmediateFlipBW = (PDEAndMetaPTEBytesPerFrame + MetaRowBytes + DPTEBytesPerRow) *
+					BandwidthAvailableForImmediateFlip / TotImmediateFlipBytes;
+		}
+		if (GPUVMEnable == true) {
+			TimeForFetchingMetaPTEImmediateFlip = dml_max3(Tno_bw + PDEAndMetaPTEBytesPerFrame *
+					HostVMInefficiencyFactor / ImmediateFlipBW,
+					UrgentExtraLatency + UrgentLatency *
+					(GPUVMMaxPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1),
+					LineTime / 4.0);
+		} else {
+			TimeForFetchingMetaPTEImmediateFlip = 0;
+		}
+		if ((GPUVMEnable == true || DCCEnable == true)) {
+			TimeForFetchingRowInVBlankImmediateFlip = dml_max3(
+					(MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / ImmediateFlipBW,
+					UrgentLatency * (HostVMDynamicLevelsTrips + 1), LineTime / 4.0);
+		} else {
+			TimeForFetchingRowInVBlankImmediateFlip = 0;
+		}
+
+		*DestinationLinesToRequestVMInImmediateFlip =
+				dml_ceil(4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime), 1.0) / 4.0;
+		*DestinationLinesToRequestRowInImmediateFlip =
+				dml_ceil(4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime), 1.0) / 4.0;
+
+		if (GPUVMEnable == true) {
+			*final_flip_bw = dml_max(PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor /
+					(*DestinationLinesToRequestVMInImmediateFlip * LineTime),
+					(MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) /
+					(*DestinationLinesToRequestRowInImmediateFlip * LineTime));
+		} else if ((GPUVMEnable == true || DCCEnable == true)) {
+			*final_flip_bw = (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) /
+					(*DestinationLinesToRequestRowInImmediateFlip * LineTime);
+		} else {
+			*final_flip_bw = 0;
+		}
+	} else {
+		TimeForFetchingMetaPTEImmediateFlip = 0;
+		TimeForFetchingRowInVBlankImmediateFlip = 0;
+		*DestinationLinesToRequestVMInImmediateFlip = 0;
+		*DestinationLinesToRequestRowInImmediateFlip = 0;
+		*final_flip_bw = 0;
+	}
+
+	if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_rgbe_alpha) {
+		if (GPUVMEnable == true && DCCEnable != true) {
+			min_row_time = dml_min(dpte_row_height *
+					LineTime / VRatio, dpte_row_height_chroma * LineTime / VRatioChroma);
+		} else if (GPUVMEnable != true && DCCEnable == true) {
+			min_row_time = dml_min(meta_row_height *
+					LineTime / VRatio, meta_row_height_chroma * LineTime / VRatioChroma);
+		} else {
+			min_row_time = dml_min4(dpte_row_height * LineTime / VRatio, meta_row_height *
+					LineTime / VRatio, dpte_row_height_chroma * LineTime /
+					VRatioChroma, meta_row_height_chroma * LineTime / VRatioChroma);
+		}
+	} else {
+		if (GPUVMEnable == true && DCCEnable != true) {
+			min_row_time = dpte_row_height * LineTime / VRatio;
+		} else if (GPUVMEnable != true && DCCEnable == true) {
+			min_row_time = meta_row_height * LineTime / VRatio;
+		} else {
+			min_row_time =
+				dml_min(dpte_row_height * LineTime / VRatio, meta_row_height * LineTime / VRatio);
+		}
+	}
+
+	if (*DestinationLinesToRequestVMInImmediateFlip >= 32 || *DestinationLinesToRequestRowInImmediateFlip >= 16
+			|| TimeForFetchingMetaPTEImmediateFlip + 2 * TimeForFetchingRowInVBlankImmediateFlip
+					> min_row_time) {
+		*ImmediateFlipSupportedForPipe = false;
+	} else {
+		*ImmediateFlipSupportedForPipe = true;
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: GPUVMEnable = %d\n", __func__, GPUVMEnable);
+	dml_print("DML::%s: DCCEnable = %d\n", __func__, DCCEnable);
+	dml_print("DML::%s: DestinationLinesToRequestVMInImmediateFlip = %f\n",
+			__func__, *DestinationLinesToRequestVMInImmediateFlip);
+	dml_print("DML::%s: DestinationLinesToRequestRowInImmediateFlip = %f\n",
+			__func__, *DestinationLinesToRequestRowInImmediateFlip);
+	dml_print("DML::%s: TimeForFetchingMetaPTEImmediateFlip = %f\n", __func__, TimeForFetchingMetaPTEImmediateFlip);
+	dml_print("DML::%s: TimeForFetchingRowInVBlankImmediateFlip = %f\n",
+			__func__, TimeForFetchingRowInVBlankImmediateFlip);
+	dml_print("DML::%s: min_row_time = %f\n", __func__, min_row_time);
+	dml_print("DML::%s: ImmediateFlipSupportedForPipe = %d\n", __func__, *ImmediateFlipSupportedForPipe);
+#endif
+} // CalculateFlipSchedule
+
+void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
+		bool USRRetrainingRequiredFinal,
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		unsigned int PrefetchMode,
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int MaxLineBufferLines,
+		unsigned int LineBufferSize,
+		unsigned int WritebackInterfaceBufferSize,
+		double DCFCLK,
+		double ReturnBW,
+		bool SynchronizeTimingsFinal,
+		bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+		bool DRRDisplay[],
+		unsigned int dpte_group_bytes[],
+		unsigned int meta_row_height[],
+		unsigned int meta_row_height_chroma[],
+		SOCParametersList mmSOCParameters,
+		unsigned int WritebackChunkSize,
+		double SOCCLK,
+		double DCFClkDeepSleep,
+		unsigned int DETBufferSizeY[],
+		unsigned int DETBufferSizeC[],
+		unsigned int SwathHeightY[],
+		unsigned int SwathHeightC[],
+		unsigned int LBBitPerPixel[],
+		double SwathWidthY[],
+		double SwathWidthC[],
+		double HRatio[],
+		double HRatioChroma[],
+		unsigned int VTaps[],
+		unsigned int VTapsChroma[],
+		double VRatio[],
+		double VRatioChroma[],
+		unsigned int HTotal[],
+		unsigned int VTotal[],
+		unsigned int VActive[],
+		double PixelClock[],
+		unsigned int BlendingAndTiming[],
+		unsigned int DPPPerSurface[],
+		double BytePerPixelDETY[],
+		double BytePerPixelDETC[],
+		double DSTXAfterScaler[],
+		double DSTYAfterScaler[],
+		bool WritebackEnable[],
+		enum source_format_class WritebackPixelFormat[],
+		double WritebackDestinationWidth[],
+		double WritebackDestinationHeight[],
+		double WritebackSourceHeight[],
+		bool UnboundedRequestEnabled,
+		unsigned int CompressedBufferSizeInkByte,
+
+		/* Output */
+		Watermarks *Watermark,
+		enum clock_change_support *DRAMClockChangeSupport,
+		double MaxActiveDRAMClockChangeLatencySupported[],
+		unsigned int SubViewportLinesNeededInMALL[],
+		enum dm_fclock_change_support *FCLKChangeSupport,
+		double *MinActiveFCLKChangeLatencySupported,
+		bool *USRRetrainingSupport,
+		double ActiveDRAMClockChangeLatencyMargin[])
+{
+	unsigned int i, j, k;
+	unsigned int SurfaceWithMinActiveFCLKChangeMargin = 0;
+	unsigned int DRAMClockChangeSupportNumber = 0;
+	unsigned int LastSurfaceWithoutMargin;
+	unsigned int DRAMClockChangeMethod = 0;
+	bool FoundFirstSurfaceWithMinActiveFCLKChangeMargin = false;
+	double MinActiveFCLKChangeMargin = 0.;
+	double SecondMinActiveFCLKChangeMarginOneDisplayInVBLank = 0.;
+	double ActiveClockChangeLatencyHidingY;
+	double ActiveClockChangeLatencyHidingC;
+	double ActiveClockChangeLatencyHiding;
+    double EffectiveDETBufferSizeY;
+	double     ActiveFCLKChangeLatencyMargin[DC__NUM_DPP__MAX];
+	double     USRRetrainingLatencyMargin[DC__NUM_DPP__MAX];
+	double TotalPixelBW = 0.0;
+	bool    SynchronizedSurfaces[DC__NUM_DPP__MAX][DC__NUM_DPP__MAX];
+	double     EffectiveLBLatencyHidingY;
+	double     EffectiveLBLatencyHidingC;
+	double     LinesInDETY[DC__NUM_DPP__MAX];
+	double     LinesInDETC[DC__NUM_DPP__MAX];
+	unsigned int    LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX];
+	unsigned int    LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX];
+	double     FullDETBufferingTimeY;
+	double     FullDETBufferingTimeC;
+	double     WritebackDRAMClockChangeLatencyMargin;
+	double     WritebackFCLKChangeLatencyMargin;
+	double     WritebackLatencyHiding;
+	bool    SameTimingForFCLKChange;
+
+	unsigned int    TotalActiveWriteback = 0;
+	unsigned int LBLatencyHidingSourceLinesY[DC__NUM_DPP__MAX];
+	unsigned int LBLatencyHidingSourceLinesC[DC__NUM_DPP__MAX];
+
+	Watermark->UrgentWatermark = mmSOCParameters.UrgentLatency + mmSOCParameters.ExtraLatency;
+	Watermark->USRRetrainingWatermark = mmSOCParameters.UrgentLatency + mmSOCParameters.ExtraLatency
+			+ mmSOCParameters.USRRetrainingLatency + mmSOCParameters.SMNLatency;
+	Watermark->DRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency + Watermark->UrgentWatermark;
+	Watermark->FCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency + Watermark->UrgentWatermark;
+	Watermark->StutterExitWatermark = mmSOCParameters.SRExitTime + mmSOCParameters.ExtraLatency
+			+ 10 / DCFClkDeepSleep;
+	Watermark->StutterEnterPlusExitWatermark = mmSOCParameters.SREnterPlusExitTime + mmSOCParameters.ExtraLatency
+			+ 10 / DCFClkDeepSleep;
+	Watermark->Z8StutterExitWatermark = mmSOCParameters.SRExitZ8Time + mmSOCParameters.ExtraLatency
+			+ 10 / DCFClkDeepSleep;
+	Watermark->Z8StutterEnterPlusExitWatermark = mmSOCParameters.SREnterPlusExitZ8Time
+			+ mmSOCParameters.ExtraLatency + 10 / DCFClkDeepSleep;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: UrgentLatency = %f\n", __func__, mmSOCParameters.UrgentLatency);
+	dml_print("DML::%s: ExtraLatency = %f\n", __func__, mmSOCParameters.ExtraLatency);
+	dml_print("DML::%s: DRAMClockChangeLatency = %f\n", __func__, mmSOCParameters.DRAMClockChangeLatency);
+	dml_print("DML::%s: UrgentWatermark = %f\n", __func__, Watermark->UrgentWatermark);
+	dml_print("DML::%s: USRRetrainingWatermark = %f\n", __func__, Watermark->USRRetrainingWatermark);
+	dml_print("DML::%s: DRAMClockChangeWatermark = %f\n", __func__, Watermark->DRAMClockChangeWatermark);
+	dml_print("DML::%s: FCLKChangeWatermark = %f\n", __func__, Watermark->FCLKChangeWatermark);
+	dml_print("DML::%s: StutterExitWatermark = %f\n", __func__, Watermark->StutterExitWatermark);
+	dml_print("DML::%s: StutterEnterPlusExitWatermark = %f\n", __func__, Watermark->StutterEnterPlusExitWatermark);
+	dml_print("DML::%s: Z8StutterExitWatermark = %f\n", __func__, Watermark->Z8StutterExitWatermark);
+	dml_print("DML::%s: Z8StutterEnterPlusExitWatermark = %f\n",
+			__func__, Watermark->Z8StutterEnterPlusExitWatermark);
+#endif
+
+
+	TotalActiveWriteback = 0;
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (WritebackEnable[k] == true)
+			TotalActiveWriteback = TotalActiveWriteback + 1;
+	}
+
+	if (TotalActiveWriteback <= 1) {
+		Watermark->WritebackUrgentWatermark = mmSOCParameters.WritebackLatency;
+	} else {
+		Watermark->WritebackUrgentWatermark = mmSOCParameters.WritebackLatency
+				+ WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
+	}
+	if (USRRetrainingRequiredFinal)
+		Watermark->WritebackUrgentWatermark = Watermark->WritebackUrgentWatermark
+				+ mmSOCParameters.USRRetrainingLatency;
+
+	if (TotalActiveWriteback <= 1) {
+		Watermark->WritebackDRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency
+				+ mmSOCParameters.WritebackLatency;
+		Watermark->WritebackFCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency
+				+ mmSOCParameters.WritebackLatency;
+	} else {
+		Watermark->WritebackDRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency
+				+ mmSOCParameters.WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
+		Watermark->WritebackFCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency
+				+ mmSOCParameters.WritebackLatency + WritebackChunkSize * 1024 / 32 / SOCCLK;
+	}
+
+	if (USRRetrainingRequiredFinal)
+		Watermark->WritebackDRAMClockChangeWatermark = Watermark->WritebackDRAMClockChangeWatermark
+				+ mmSOCParameters.USRRetrainingLatency;
+
+	if (USRRetrainingRequiredFinal)
+		Watermark->WritebackFCLKChangeWatermark = Watermark->WritebackFCLKChangeWatermark
+				+ mmSOCParameters.USRRetrainingLatency;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: WritebackDRAMClockChangeWatermark = %f\n",
+			__func__, Watermark->WritebackDRAMClockChangeWatermark);
+	dml_print("DML::%s: WritebackFCLKChangeWatermark = %f\n", __func__, Watermark->WritebackFCLKChangeWatermark);
+	dml_print("DML::%s: WritebackUrgentWatermark = %f\n", __func__, Watermark->WritebackUrgentWatermark);
+	dml_print("DML::%s: USRRetrainingRequiredFinal = %d\n", __func__, USRRetrainingRequiredFinal);
+	dml_print("DML::%s: USRRetrainingLatency = %f\n", __func__, mmSOCParameters.USRRetrainingLatency);
+#endif
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		TotalPixelBW = TotalPixelBW + DPPPerSurface[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k] +
+				SwathWidthC[k] * BytePerPixelDETC[k] * VRatioChroma[k]) / (HTotal[k] / PixelClock[k]);
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+
+		LBLatencyHidingSourceLinesY[k] = dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1)) - (VTaps[k] - 1);
+		LBLatencyHidingSourceLinesC[k] = dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(HRatioChroma[k], 1.0)), 1)) - (VTapsChroma[k] - 1);
+
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, MaxLineBufferLines = %d\n", __func__, k, MaxLineBufferLines);
+		dml_print("DML::%s: k=%d, LineBufferSize     = %d\n", __func__, k, LineBufferSize);
+		dml_print("DML::%s: k=%d, LBBitPerPixel      = %d\n", __func__, k, LBBitPerPixel[k]);
+		dml_print("DML::%s: k=%d, HRatio             = %f\n", __func__, k, HRatio[k]);
+		dml_print("DML::%s: k=%d, VTaps              = %d\n", __func__, k, VTaps[k]);
+#endif
+
+		EffectiveLBLatencyHidingY = LBLatencyHidingSourceLinesY[k] / VRatio[k] * (HTotal[k] / PixelClock[k]);
+		EffectiveLBLatencyHidingC = LBLatencyHidingSourceLinesC[k] / VRatioChroma[k] * (HTotal[k] / PixelClock[k]);
+		EffectiveDETBufferSizeY = DETBufferSizeY[k];
+
+		if (UnboundedRequestEnabled) {
+			EffectiveDETBufferSizeY = EffectiveDETBufferSizeY
+					+ CompressedBufferSizeInkByte * 1024
+							* (SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k])
+							/ (HTotal[k] / PixelClock[k]) / TotalPixelBW;
+		}
+
+		LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k];
+		LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
+		FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k]) / VRatio[k];
+
+		ActiveClockChangeLatencyHidingY = EffectiveLBLatencyHidingY + FullDETBufferingTimeY
+				- (DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k] / PixelClock[k];
+
+		if (NumberOfActiveSurfaces > 1) {
+			ActiveClockChangeLatencyHidingY = ActiveClockChangeLatencyHidingY
+					- (1 - 1 / NumberOfActiveSurfaces) * SwathHeightY[k] * HTotal[k]
+							/ PixelClock[k] / VRatio[k];
+		}
+
+		if (BytePerPixelDETC[k] > 0) {
+			LinesInDETC[k] = DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k];
+			LinesInDETCRoundedDownToSwath[k] = dml_floor(LinesInDETC[k], SwathHeightC[k]);
+			FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k])
+					/ VRatioChroma[k];
+			ActiveClockChangeLatencyHidingC = EffectiveLBLatencyHidingC + FullDETBufferingTimeC
+					- (DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k]
+							/ PixelClock[k];
+			if (NumberOfActiveSurfaces > 1) {
+				ActiveClockChangeLatencyHidingC = ActiveClockChangeLatencyHidingC
+						- (1 - 1 / NumberOfActiveSurfaces) * SwathHeightC[k] * HTotal[k]
+								/ PixelClock[k] / VRatioChroma[k];
+			}
+			ActiveClockChangeLatencyHiding = dml_min(ActiveClockChangeLatencyHidingY,
+					ActiveClockChangeLatencyHidingC);
+		} else {
+			ActiveClockChangeLatencyHiding = ActiveClockChangeLatencyHidingY;
+		}
+
+		ActiveDRAMClockChangeLatencyMargin[k] = ActiveClockChangeLatencyHiding - Watermark->UrgentWatermark
+				- Watermark->DRAMClockChangeWatermark;
+		ActiveFCLKChangeLatencyMargin[k] = ActiveClockChangeLatencyHiding - Watermark->UrgentWatermark
+				- Watermark->FCLKChangeWatermark;
+		USRRetrainingLatencyMargin[k] = ActiveClockChangeLatencyHiding - Watermark->USRRetrainingWatermark;
+
+		if (WritebackEnable[k]) {
+			WritebackLatencyHiding = WritebackInterfaceBufferSize * 1024
+					/ (WritebackDestinationWidth[k] * WritebackDestinationHeight[k]
+							/ (WritebackSourceHeight[k] * HTotal[k] / PixelClock[k]) * 4);
+			if (WritebackPixelFormat[k] == dm_444_64)
+				WritebackLatencyHiding = WritebackLatencyHiding / 2;
+
+			WritebackDRAMClockChangeLatencyMargin = WritebackLatencyHiding
+					- Watermark->WritebackDRAMClockChangeWatermark;
+
+			WritebackFCLKChangeLatencyMargin = WritebackLatencyHiding
+					- Watermark->WritebackFCLKChangeWatermark;
+
+			ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMargin[k],
+					WritebackFCLKChangeLatencyMargin);
+			ActiveFCLKChangeLatencyMargin[k] = dml_min(ActiveFCLKChangeLatencyMargin[k],
+					WritebackDRAMClockChangeLatencyMargin);
+		}
+		MaxActiveDRAMClockChangeLatencySupported[k] =
+				(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) ?
+						0 :
+						(ActiveDRAMClockChangeLatencyMargin[k]
+								+ mmSOCParameters.DRAMClockChangeLatency);
+	}
+
+	for (i = 0; i < NumberOfActiveSurfaces; ++i) {
+		for (j = 0; j < NumberOfActiveSurfaces; ++j) {
+			if (i == j ||
+					(BlendingAndTiming[i] == i && BlendingAndTiming[j] == i) ||
+					(BlendingAndTiming[j] == j && BlendingAndTiming[i] == j) ||
+					(BlendingAndTiming[i] == BlendingAndTiming[j] && BlendingAndTiming[i] != i) ||
+					(SynchronizeTimingsFinal && PixelClock[i] == PixelClock[j] &&
+					HTotal[i] == HTotal[j] && VTotal[i] == VTotal[j] &&
+					VActive[i] == VActive[j]) || (SynchronizeDRRDisplaysForUCLKPStateChangeFinal &&
+					(DRRDisplay[i] || DRRDisplay[j]))) {
+				SynchronizedSurfaces[i][j] = true;
+			} else {
+				SynchronizedSurfaces[i][j] = false;
+			}
+		}
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if ((UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) &&
+				(!FoundFirstSurfaceWithMinActiveFCLKChangeMargin ||
+				ActiveFCLKChangeLatencyMargin[k] < MinActiveFCLKChangeMargin)) {
+			FoundFirstSurfaceWithMinActiveFCLKChangeMargin = true;
+			MinActiveFCLKChangeMargin = ActiveFCLKChangeLatencyMargin[k];
+			SurfaceWithMinActiveFCLKChangeMargin = k;
+		}
+	}
+
+	*MinActiveFCLKChangeLatencySupported = MinActiveFCLKChangeMargin + mmSOCParameters.FCLKChangeLatency;
+
+	SameTimingForFCLKChange = true;
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (!SynchronizedSurfaces[k][SurfaceWithMinActiveFCLKChangeMargin]) {
+			if ((UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) &&
+					(SameTimingForFCLKChange ||
+					ActiveFCLKChangeLatencyMargin[k] <
+					SecondMinActiveFCLKChangeMarginOneDisplayInVBLank)) {
+				SecondMinActiveFCLKChangeMarginOneDisplayInVBLank = ActiveFCLKChangeLatencyMargin[k];
+			}
+			SameTimingForFCLKChange = false;
+		}
+	}
+
+	if (MinActiveFCLKChangeMargin > 0) {
+		*FCLKChangeSupport = dm_fclock_change_vactive;
+	} else if ((SameTimingForFCLKChange || SecondMinActiveFCLKChangeMarginOneDisplayInVBLank > 0) &&
+			(PrefetchMode <= 1)) {
+		*FCLKChangeSupport = dm_fclock_change_vblank;
+	} else {
+		*FCLKChangeSupport = dm_fclock_change_unsupported;
+	}
+
+	*USRRetrainingSupport = true;
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if ((UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) &&
+				(USRRetrainingLatencyMargin[k] < 0)) {
+			*USRRetrainingSupport = false;
+		}
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_full_frame &&
+				UseMALLForPStateChange[k] != dm_use_mall_pstate_change_sub_viewport &&
+				UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe &&
+				ActiveDRAMClockChangeLatencyMargin[k] < 0) {
+			if (PrefetchMode > 0) {
+				DRAMClockChangeSupportNumber = 2;
+			} else if (DRAMClockChangeSupportNumber == 0) {
+				DRAMClockChangeSupportNumber = 1;
+				LastSurfaceWithoutMargin = k;
+			} else if (DRAMClockChangeSupportNumber == 1 &&
+					!SynchronizedSurfaces[LastSurfaceWithoutMargin][k]) {
+				DRAMClockChangeSupportNumber = 2;
+			}
+		}
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame)
+			DRAMClockChangeMethod = 1;
+		else if (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport)
+			DRAMClockChangeMethod = 2;
+	}
+
+	if (DRAMClockChangeMethod == 0) {
+		if (DRAMClockChangeSupportNumber == 0)
+			*DRAMClockChangeSupport = dm_dram_clock_change_vactive;
+		else if (DRAMClockChangeSupportNumber == 1)
+			*DRAMClockChangeSupport = dm_dram_clock_change_vblank;
+		else
+			*DRAMClockChangeSupport = dm_dram_clock_change_unsupported;
+	} else if (DRAMClockChangeMethod == 1) {
+		if (DRAMClockChangeSupportNumber == 0)
+			*DRAMClockChangeSupport = dm_dram_clock_change_vactive_w_mall_full_frame;
+		else if (DRAMClockChangeSupportNumber == 1)
+			*DRAMClockChangeSupport = dm_dram_clock_change_vblank_w_mall_full_frame;
+		else
+			*DRAMClockChangeSupport = dm_dram_clock_change_unsupported;
+	} else {
+		if (DRAMClockChangeSupportNumber == 0)
+			*DRAMClockChangeSupport = dm_dram_clock_change_vactive_w_mall_sub_vp;
+		else if (DRAMClockChangeSupportNumber == 1)
+			*DRAMClockChangeSupport = dm_dram_clock_change_vblank_w_mall_sub_vp;
+		else
+			*DRAMClockChangeSupport = dm_dram_clock_change_unsupported;
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		unsigned int dst_y_pstate;
+		unsigned int src_y_pstate_l;
+		unsigned int src_y_pstate_c;
+		unsigned int src_y_ahead_l, src_y_ahead_c, sub_vp_lines_l, sub_vp_lines_c;
+
+		dst_y_pstate = dml_ceil((mmSOCParameters.DRAMClockChangeLatency + mmSOCParameters.UrgentLatency) / (HTotal[k] / PixelClock[k]), 1);
+		src_y_pstate_l = dml_ceil(dst_y_pstate * VRatio[k], SwathHeightY[k]);
+		src_y_ahead_l = dml_floor(DETBufferSizeY[k] / BytePerPixelDETY[k] / SwathWidthY[k], SwathHeightY[k]) + LBLatencyHidingSourceLinesY[k];
+		sub_vp_lines_l = src_y_pstate_l + src_y_ahead_l + meta_row_height[k];
+
+#ifdef __DML_VBA_DEBUG__
+dml_print("DML::%s: k=%d, DETBufferSizeY               = %d\n", __func__, k, DETBufferSizeY[k]);
+dml_print("DML::%s: k=%d, BytePerPixelDETY             = %f\n", __func__, k, BytePerPixelDETY[k]);
+dml_print("DML::%s: k=%d, SwathWidthY                  = %d\n", __func__, k, SwathWidthY[k]);
+dml_print("DML::%s: k=%d, SwathHeightY                 = %d\n", __func__, k, SwathHeightY[k]);
+dml_print("DML::%s: k=%d, LBLatencyHidingSourceLinesY  = %d\n", __func__, k, LBLatencyHidingSourceLinesY[k]);
+dml_print("DML::%s: k=%d, dst_y_pstate      = %d\n", __func__, k, dst_y_pstate);
+dml_print("DML::%s: k=%d, src_y_pstate_l    = %d\n", __func__, k, src_y_pstate_l);
+dml_print("DML::%s: k=%d, src_y_ahead_l     = %d\n", __func__, k, src_y_ahead_l);
+dml_print("DML::%s: k=%d, meta_row_height   = %d\n", __func__, k, meta_row_height[k]);
+dml_print("DML::%s: k=%d, sub_vp_lines_l    = %d\n", __func__, k, sub_vp_lines_l);
+#endif
+		SubViewportLinesNeededInMALL[k] = sub_vp_lines_l;
+
+		if (BytePerPixelDETC[k] > 0) {
+			src_y_pstate_c = dml_ceil(dst_y_pstate * VRatioChroma[k], SwathHeightC[k]);
+			src_y_ahead_c = dml_floor(DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k], SwathHeightC[k]) + LBLatencyHidingSourceLinesC[k];
+			sub_vp_lines_c = src_y_pstate_c + src_y_ahead_c + meta_row_height_chroma[k];
+			SubViewportLinesNeededInMALL[k] = dml_max(sub_vp_lines_l, sub_vp_lines_c);
+
+#ifdef __DML_VBA_DEBUG__
+dml_print("DML::%s: k=%d, src_y_pstate_c            = %d\n", __func__, k, src_y_pstate_c);
+dml_print("DML::%s: k=%d, src_y_ahead_c             = %d\n", __func__, k, src_y_ahead_c);
+dml_print("DML::%s: k=%d, meta_row_height_chroma    = %d\n", __func__, k, meta_row_height_chroma[k]);
+dml_print("DML::%s: k=%d, sub_vp_lines_c            = %d\n", __func__, k, sub_vp_lines_c);
+#endif
+		}
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DRAMClockChangeSupport = %d\n", __func__, *DRAMClockChangeSupport);
+	dml_print("DML::%s: FCLKChangeSupport = %d\n", __func__, *FCLKChangeSupport);
+	dml_print("DML::%s: MinActiveFCLKChangeLatencySupported = %f\n",
+			__func__, *MinActiveFCLKChangeLatencySupported);
+	dml_print("DML::%s: USRRetrainingSupport = %d\n", __func__, *USRRetrainingSupport);
+#endif
+} // CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport
+
+double dml32_CalculateWriteBackDISPCLK(
+		enum source_format_class WritebackPixelFormat,
+		double PixelClock,
+		double WritebackHRatio,
+		double WritebackVRatio,
+		unsigned int WritebackHTaps,
+		unsigned int WritebackVTaps,
+		unsigned int   WritebackSourceWidth,
+		unsigned int   WritebackDestinationWidth,
+		unsigned int HTotal,
+		unsigned int WritebackLineBufferSize,
+		double DISPCLKDPPCLKVCOSpeed)
+{
+	double DISPCLK_H, DISPCLK_V, DISPCLK_HB;
+
+	DISPCLK_H = PixelClock * dml_ceil(WritebackHTaps / 8.0, 1) / WritebackHRatio;
+	DISPCLK_V = PixelClock * (WritebackVTaps * dml_ceil(WritebackDestinationWidth / 6.0, 1) + 8.0) / HTotal;
+	DISPCLK_HB = PixelClock * WritebackVTaps * (WritebackDestinationWidth *
+			WritebackVTaps - WritebackLineBufferSize / 57.0) / 6.0 / WritebackSourceWidth;
+	return dml32_RoundToDFSGranularity(dml_max3(DISPCLK_H, DISPCLK_V, DISPCLK_HB), 1, DISPCLKDPPCLKVCOSpeed);
+}
+
+void dml32_CalculateMinAndMaxPrefetchMode(
+		enum dm_prefetch_modes   AllowForPStateChangeOrStutterInVBlankFinal,
+		unsigned int             *MinPrefetchMode,
+		unsigned int             *MaxPrefetchMode)
+{
+	if (AllowForPStateChangeOrStutterInVBlankFinal == dm_prefetch_support_none) {
+		*MinPrefetchMode = 3;
+		*MaxPrefetchMode = 3;
+	} else if (AllowForPStateChangeOrStutterInVBlankFinal == dm_prefetch_support_stutter) {
+		*MinPrefetchMode = 2;
+		*MaxPrefetchMode = 2;
+	} else if (AllowForPStateChangeOrStutterInVBlankFinal == dm_prefetch_support_fclk_and_stutter) {
+		*MinPrefetchMode = 1;
+		*MaxPrefetchMode = 1;
+	} else if (AllowForPStateChangeOrStutterInVBlankFinal == dm_prefetch_support_uclk_fclk_and_stutter) {
+		*MinPrefetchMode = 0;
+		*MaxPrefetchMode = 0;
+	} else if (AllowForPStateChangeOrStutterInVBlankFinal ==
+			dm_prefetch_support_uclk_fclk_and_stutter_if_possible) {
+		*MinPrefetchMode = 0;
+		*MaxPrefetchMode = 3;
+	} else {
+		*MinPrefetchMode = 0;
+		*MaxPrefetchMode = 3;
+	}
+} // CalculateMinAndMaxPrefetchMode
+
+void dml32_CalculatePixelDeliveryTimes(
+		unsigned int             NumberOfActiveSurfaces,
+		double              VRatio[],
+		double              VRatioChroma[],
+		double              VRatioPrefetchY[],
+		double              VRatioPrefetchC[],
+		unsigned int             swath_width_luma_ub[],
+		unsigned int             swath_width_chroma_ub[],
+		unsigned int             DPPPerSurface[],
+		double              HRatio[],
+		double              HRatioChroma[],
+		double              PixelClock[],
+		double              PSCL_THROUGHPUT[],
+		double              PSCL_THROUGHPUT_CHROMA[],
+		double              Dppclk[],
+		unsigned int             BytePerPixelC[],
+		enum dm_rotation_angle   SourceRotation[],
+		unsigned int             NumberOfCursors[],
+		unsigned int             CursorWidth[][DC__NUM_CURSOR__MAX],
+		unsigned int             CursorBPP[][DC__NUM_CURSOR__MAX],
+		unsigned int             BlockWidth256BytesY[],
+		unsigned int             BlockHeight256BytesY[],
+		unsigned int             BlockWidth256BytesC[],
+		unsigned int             BlockHeight256BytesC[],
+
+		/* Output */
+		double              DisplayPipeLineDeliveryTimeLuma[],
+		double              DisplayPipeLineDeliveryTimeChroma[],
+		double              DisplayPipeLineDeliveryTimeLumaPrefetch[],
+		double              DisplayPipeLineDeliveryTimeChromaPrefetch[],
+		double              DisplayPipeRequestDeliveryTimeLuma[],
+		double              DisplayPipeRequestDeliveryTimeChroma[],
+		double              DisplayPipeRequestDeliveryTimeLumaPrefetch[],
+		double              DisplayPipeRequestDeliveryTimeChromaPrefetch[],
+		double              CursorRequestDeliveryTime[],
+		double              CursorRequestDeliveryTimePrefetch[])
+{
+	double   req_per_swath_ub;
+	unsigned int k;
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d : HRatio = %f\n", __func__, k, HRatio[k]);
+		dml_print("DML::%s: k=%d : VRatio = %f\n", __func__, k, VRatio[k]);
+		dml_print("DML::%s: k=%d : HRatioChroma = %f\n", __func__, k, HRatioChroma[k]);
+		dml_print("DML::%s: k=%d : VRatioChroma = %f\n", __func__, k, VRatioChroma[k]);
+		dml_print("DML::%s: k=%d : swath_width_luma_ub = %d\n", __func__, k, swath_width_luma_ub[k]);
+		dml_print("DML::%s: k=%d : swath_width_chroma_ub = %d\n", __func__, k, swath_width_chroma_ub[k]);
+		dml_print("DML::%s: k=%d : PSCL_THROUGHPUT = %f\n", __func__, k, PSCL_THROUGHPUT[k]);
+		dml_print("DML::%s: k=%d : PSCL_THROUGHPUT_CHROMA = %f\n", __func__, k, PSCL_THROUGHPUT_CHROMA[k]);
+		dml_print("DML::%s: k=%d : DPPPerSurface = %d\n", __func__, k, DPPPerSurface[k]);
+		dml_print("DML::%s: k=%d : PixelClock = %f\n", __func__, k, PixelClock[k]);
+		dml_print("DML::%s: k=%d : Dppclk = %f\n", __func__, k, Dppclk[k]);
+#endif
+
+		if (VRatio[k] <= 1) {
+			DisplayPipeLineDeliveryTimeLuma[k] =
+					swath_width_luma_ub[k] * DPPPerSurface[k] / HRatio[k] / PixelClock[k];
+		} else {
+			DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
+		}
+
+		if (BytePerPixelC[k] == 0) {
+			DisplayPipeLineDeliveryTimeChroma[k] = 0;
+		} else {
+			if (VRatioChroma[k] <= 1) {
+				DisplayPipeLineDeliveryTimeChroma[k] =
+					swath_width_chroma_ub[k] * DPPPerSurface[k] / HRatioChroma[k] / PixelClock[k];
+			} else {
+				DisplayPipeLineDeliveryTimeChroma[k] =
+					swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];
+			}
+		}
+
+		if (VRatioPrefetchY[k] <= 1) {
+			DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
+					swath_width_luma_ub[k] * DPPPerSurface[k] / HRatio[k] / PixelClock[k];
+		} else {
+			DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
+					swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
+		}
+
+		if (BytePerPixelC[k] == 0) {
+			DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
+		} else {
+			if (VRatioPrefetchC[k] <= 1) {
+				DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] *
+						DPPPerSurface[k] / HRatioChroma[k] / PixelClock[k];
+			} else {
+				DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
+						swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];
+			}
+		}
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeLuma = %f\n",
+				__func__, k, DisplayPipeLineDeliveryTimeLuma[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeLumaPrefetch = %f\n",
+				__func__, k, DisplayPipeLineDeliveryTimeLumaPrefetch[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeChroma = %f\n",
+				__func__, k, DisplayPipeLineDeliveryTimeChroma[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeChromaPrefetch = %f\n",
+				__func__, k, DisplayPipeLineDeliveryTimeChromaPrefetch[k]);
+#endif
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (!IsVertical(SourceRotation[k]))
+			req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k];
+		else
+			req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k];
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d : req_per_swath_ub = %f (Luma)\n", __func__, k, req_per_swath_ub);
+#endif
+
+		DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k] / req_per_swath_ub;
+		DisplayPipeRequestDeliveryTimeLumaPrefetch[k] =
+				DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub;
+		if (BytePerPixelC[k] == 0) {
+			DisplayPipeRequestDeliveryTimeChroma[k] = 0;
+			DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0;
+		} else {
+			if (!IsVertical(SourceRotation[k]))
+				req_per_swath_ub = swath_width_chroma_ub[k] / BlockWidth256BytesC[k];
+			else
+				req_per_swath_ub = swath_width_chroma_ub[k] / BlockHeight256BytesC[k];
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%d : req_per_swath_ub = %f (Chroma)\n", __func__, k, req_per_swath_ub);
+#endif
+			DisplayPipeRequestDeliveryTimeChroma[k] =
+					DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub;
+			DisplayPipeRequestDeliveryTimeChromaPrefetch[k] =
+					DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub;
+		}
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeLuma = %f\n",
+				__func__, k, DisplayPipeRequestDeliveryTimeLuma[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeLumaPrefetch = %f\n",
+				__func__, k, DisplayPipeRequestDeliveryTimeLumaPrefetch[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeChroma = %f\n",
+				__func__, k, DisplayPipeRequestDeliveryTimeChroma[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeChromaPrefetch = %f\n",
+				__func__, k, DisplayPipeRequestDeliveryTimeChromaPrefetch[k]);
+#endif
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		unsigned int cursor_req_per_width;
+
+		cursor_req_per_width = dml_ceil((double) CursorWidth[k][0] * (double) CursorBPP[k][0] /
+				256.0 / 8.0, 1.0);
+		if (NumberOfCursors[k] > 0) {
+			if (VRatio[k] <= 1) {
+				CursorRequestDeliveryTime[k] = (double) CursorWidth[k][0] /
+						HRatio[k] / PixelClock[k] / cursor_req_per_width;
+			} else {
+				CursorRequestDeliveryTime[k] = (double) CursorWidth[k][0] /
+						PSCL_THROUGHPUT[k] / Dppclk[k] / cursor_req_per_width;
+			}
+			if (VRatioPrefetchY[k] <= 1) {
+				CursorRequestDeliveryTimePrefetch[k] = (double) CursorWidth[k][0] /
+						HRatio[k] / PixelClock[k] / cursor_req_per_width;
+			} else {
+				CursorRequestDeliveryTimePrefetch[k] = (double) CursorWidth[k][0] /
+						PSCL_THROUGHPUT[k] / Dppclk[k] / cursor_req_per_width;
+			}
+		} else {
+			CursorRequestDeliveryTime[k] = 0;
+			CursorRequestDeliveryTimePrefetch[k] = 0;
+		}
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d : NumberOfCursors = %d\n",
+				__func__, k, NumberOfCursors[k]);
+		dml_print("DML::%s: k=%d : CursorRequestDeliveryTime = %f\n",
+				__func__, k, CursorRequestDeliveryTime[k]);
+		dml_print("DML::%s: k=%d : CursorRequestDeliveryTimePrefetch = %f\n",
+				__func__, k, CursorRequestDeliveryTimePrefetch[k]);
+#endif
+	}
+} // CalculatePixelDeliveryTimes
+
+void dml32_CalculateMetaAndPTETimes(
+		bool use_one_row_for_frame[],
+		unsigned int NumberOfActiveSurfaces,
+		bool GPUVMEnable,
+		unsigned int MetaChunkSize,
+		unsigned int MinMetaChunkSizeBytes,
+		unsigned int    HTotal[],
+		double  VRatio[],
+		double  VRatioChroma[],
+		double  DestinationLinesToRequestRowInVBlank[],
+		double  DestinationLinesToRequestRowInImmediateFlip[],
+		bool DCCEnable[],
+		double  PixelClock[],
+		unsigned int BytePerPixelY[],
+		unsigned int BytePerPixelC[],
+		enum dm_rotation_angle SourceRotation[],
+		unsigned int dpte_row_height[],
+		unsigned int dpte_row_height_chroma[],
+		unsigned int meta_row_width[],
+		unsigned int meta_row_width_chroma[],
+		unsigned int meta_row_height[],
+		unsigned int meta_row_height_chroma[],
+		unsigned int meta_req_width[],
+		unsigned int meta_req_width_chroma[],
+		unsigned int meta_req_height[],
+		unsigned int meta_req_height_chroma[],
+		unsigned int dpte_group_bytes[],
+		unsigned int    PTERequestSizeY[],
+		unsigned int    PTERequestSizeC[],
+		unsigned int    PixelPTEReqWidthY[],
+		unsigned int    PixelPTEReqHeightY[],
+		unsigned int    PixelPTEReqWidthC[],
+		unsigned int    PixelPTEReqHeightC[],
+		unsigned int    dpte_row_width_luma_ub[],
+		unsigned int    dpte_row_width_chroma_ub[],
+
+		/* Output */
+		double DST_Y_PER_PTE_ROW_NOM_L[],
+		double DST_Y_PER_PTE_ROW_NOM_C[],
+		double DST_Y_PER_META_ROW_NOM_L[],
+		double DST_Y_PER_META_ROW_NOM_C[],
+		double TimePerMetaChunkNominal[],
+		double TimePerChromaMetaChunkNominal[],
+		double TimePerMetaChunkVBlank[],
+		double TimePerChromaMetaChunkVBlank[],
+		double TimePerMetaChunkFlip[],
+		double TimePerChromaMetaChunkFlip[],
+		double time_per_pte_group_nom_luma[],
+		double time_per_pte_group_vblank_luma[],
+		double time_per_pte_group_flip_luma[],
+		double time_per_pte_group_nom_chroma[],
+		double time_per_pte_group_vblank_chroma[],
+		double time_per_pte_group_flip_chroma[])
+{
+	unsigned int   meta_chunk_width;
+	unsigned int   min_meta_chunk_width;
+	unsigned int   meta_chunk_per_row_int;
+	unsigned int   meta_row_remainder;
+	unsigned int   meta_chunk_threshold;
+	unsigned int   meta_chunks_per_row_ub;
+	unsigned int   meta_chunk_width_chroma;
+	unsigned int   min_meta_chunk_width_chroma;
+	unsigned int   meta_chunk_per_row_int_chroma;
+	unsigned int   meta_row_remainder_chroma;
+	unsigned int   meta_chunk_threshold_chroma;
+	unsigned int   meta_chunks_per_row_ub_chroma;
+	unsigned int   dpte_group_width_luma;
+	unsigned int   dpte_groups_per_row_luma_ub;
+	unsigned int   dpte_group_width_chroma;
+	unsigned int   dpte_groups_per_row_chroma_ub;
+	unsigned int k;
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k];
+		if (BytePerPixelC[k] == 0)
+			DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
+		else
+			DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / VRatioChroma[k];
+		DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k];
+		if (BytePerPixelC[k] == 0)
+			DST_Y_PER_META_ROW_NOM_C[k] = 0;
+		else
+			DST_Y_PER_META_ROW_NOM_C[k] = meta_row_height_chroma[k] / VRatioChroma[k];
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (DCCEnable[k] == true) {
+			meta_chunk_width = MetaChunkSize * 1024 * 256 / BytePerPixelY[k] / meta_row_height[k];
+			min_meta_chunk_width = MinMetaChunkSizeBytes * 256 / BytePerPixelY[k] / meta_row_height[k];
+			meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width;
+			meta_row_remainder = meta_row_width[k] % meta_chunk_width;
+			if (!IsVertical(SourceRotation[k]))
+				meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
+			else
+				meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k];
+
+			if (meta_row_remainder <= meta_chunk_threshold)
+				meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
+			else
+				meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
+
+			TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] *
+					HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
+			TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] *
+					HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
+			TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] *
+					HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
+			if (BytePerPixelC[k] == 0) {
+				TimePerChromaMetaChunkNominal[k] = 0;
+				TimePerChromaMetaChunkVBlank[k] = 0;
+				TimePerChromaMetaChunkFlip[k] = 0;
+			} else {
+				meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] /
+						meta_row_height_chroma[k];
+				min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] /
+						meta_row_height_chroma[k];
+				meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] /
+						meta_chunk_width_chroma;
+				meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma;
+				if (!IsVertical(SourceRotation[k])) {
+					meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma -
+							meta_req_width_chroma[k];
+				} else {
+					meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma -
+							meta_req_height_chroma[k];
+				}
+				if (meta_row_remainder_chroma <= meta_chunk_threshold_chroma)
+					meta_chunks_per_row_ub_chroma = meta_chunk_per_row_int_chroma + 1;
+				else
+					meta_chunks_per_row_ub_chroma = meta_chunk_per_row_int_chroma + 2;
+
+				TimePerChromaMetaChunkNominal[k] = meta_row_height_chroma[k] / VRatioChroma[k] *
+						HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
+				TimePerChromaMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] *
+						HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
+				TimePerChromaMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] *
+						HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
+			}
+		} else {
+			TimePerMetaChunkNominal[k] = 0;
+			TimePerMetaChunkVBlank[k] = 0;
+			TimePerMetaChunkFlip[k] = 0;
+			TimePerChromaMetaChunkNominal[k] = 0;
+			TimePerChromaMetaChunkVBlank[k] = 0;
+			TimePerChromaMetaChunkFlip[k] = 0;
+		}
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (GPUVMEnable == true) {
+			if (!IsVertical(SourceRotation[k])) {
+				dpte_group_width_luma = (double) dpte_group_bytes[k] /
+						(double) PTERequestSizeY[k] * PixelPTEReqWidthY[k];
+			} else {
+				dpte_group_width_luma = (double) dpte_group_bytes[k] /
+						(double) PTERequestSizeY[k] * PixelPTEReqHeightY[k];
+			}
+
+			if (use_one_row_for_frame[k]) {
+				dpte_groups_per_row_luma_ub = dml_ceil((double) dpte_row_width_luma_ub[k] /
+						(double) dpte_group_width_luma / 2.0, 1.0);
+			} else {
+				dpte_groups_per_row_luma_ub = dml_ceil((double) dpte_row_width_luma_ub[k] /
+						(double) dpte_group_width_luma, 1.0);
+			}
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%0d, use_one_row_for_frame        = %d\n",
+					__func__, k, use_one_row_for_frame[k]);
+			dml_print("DML::%s: k=%0d, dpte_group_bytes             = %d\n",
+					__func__, k, dpte_group_bytes[k]);
+			dml_print("DML::%s: k=%0d, PTERequestSizeY              = %d\n",
+					__func__, k, PTERequestSizeY[k]);
+			dml_print("DML::%s: k=%0d, PixelPTEReqWidthY            = %d\n",
+					__func__, k, PixelPTEReqWidthY[k]);
+			dml_print("DML::%s: k=%0d, PixelPTEReqHeightY           = %d\n",
+					__func__, k, PixelPTEReqHeightY[k]);
+			dml_print("DML::%s: k=%0d, dpte_row_width_luma_ub       = %d\n",
+					__func__, k, dpte_row_width_luma_ub[k]);
+			dml_print("DML::%s: k=%0d, dpte_group_width_luma        = %d\n",
+					__func__, k, dpte_group_width_luma);
+			dml_print("DML::%s: k=%0d, dpte_groups_per_row_luma_ub  = %d\n",
+					__func__, k, dpte_groups_per_row_luma_ub);
+#endif
+
+			time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] *
+					HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
+			time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] *
+					HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
+			time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] *
+					HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
+			if (BytePerPixelC[k] == 0) {
+				time_per_pte_group_nom_chroma[k] = 0;
+				time_per_pte_group_vblank_chroma[k] = 0;
+				time_per_pte_group_flip_chroma[k] = 0;
+			} else {
+				if (!IsVertical(SourceRotation[k])) {
+					dpte_group_width_chroma = (double) dpte_group_bytes[k] /
+							(double) PTERequestSizeC[k] * PixelPTEReqWidthC[k];
+				} else {
+					dpte_group_width_chroma = (double) dpte_group_bytes[k] /
+							(double) PTERequestSizeC[k] * PixelPTEReqHeightC[k];
+				}
+
+				if (use_one_row_for_frame[k]) {
+					dpte_groups_per_row_chroma_ub = dml_ceil((double) dpte_row_width_chroma_ub[k] /
+							(double) dpte_group_width_chroma / 2.0, 1.0);
+				} else {
+					dpte_groups_per_row_chroma_ub = dml_ceil((double) dpte_row_width_chroma_ub[k] /
+							(double) dpte_group_width_chroma, 1.0);
+				}
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: k=%0d, dpte_row_width_chroma_ub        = %d\n",
+						__func__, k, dpte_row_width_chroma_ub[k]);
+				dml_print("DML::%s: k=%0d, dpte_group_width_chroma        = %d\n",
+						__func__, k, dpte_group_width_chroma);
+				dml_print("DML::%s: k=%0d, dpte_groups_per_row_chroma_ub  = %d\n",
+						__func__, k, dpte_groups_per_row_chroma_ub);
+#endif
+				time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] *
+						HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
+				time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] *
+						HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
+				time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] *
+						HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
+			}
+		} else {
+			time_per_pte_group_nom_luma[k] = 0;
+			time_per_pte_group_vblank_luma[k] = 0;
+			time_per_pte_group_flip_luma[k] = 0;
+			time_per_pte_group_nom_chroma[k] = 0;
+			time_per_pte_group_vblank_chroma[k] = 0;
+			time_per_pte_group_flip_chroma[k] = 0;
+		}
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%0d, DestinationLinesToRequestRowInVBlank         = %f\n",
+				__func__, k, DestinationLinesToRequestRowInVBlank[k]);
+		dml_print("DML::%s: k=%0d, DestinationLinesToRequestRowInImmediateFlip  = %f\n",
+				__func__, k, DestinationLinesToRequestRowInImmediateFlip[k]);
+		dml_print("DML::%s: k=%0d, DST_Y_PER_PTE_ROW_NOM_L                      = %f\n",
+				__func__, k, DST_Y_PER_PTE_ROW_NOM_L[k]);
+		dml_print("DML::%s: k=%0d, DST_Y_PER_PTE_ROW_NOM_C                      = %f\n",
+				__func__, k, DST_Y_PER_PTE_ROW_NOM_C[k]);
+		dml_print("DML::%s: k=%0d, DST_Y_PER_META_ROW_NOM_L                     = %f\n",
+				__func__, k, DST_Y_PER_META_ROW_NOM_L[k]);
+		dml_print("DML::%s: k=%0d, DST_Y_PER_META_ROW_NOM_C                     = %f\n",
+				__func__, k, DST_Y_PER_META_ROW_NOM_C[k]);
+		dml_print("DML::%s: k=%0d, TimePerMetaChunkNominal          = %f\n",
+				__func__, k, TimePerMetaChunkNominal[k]);
+		dml_print("DML::%s: k=%0d, TimePerMetaChunkVBlank           = %f\n",
+				__func__, k, TimePerMetaChunkVBlank[k]);
+		dml_print("DML::%s: k=%0d, TimePerMetaChunkFlip             = %f\n",
+				__func__, k, TimePerMetaChunkFlip[k]);
+		dml_print("DML::%s: k=%0d, TimePerChromaMetaChunkNominal    = %f\n",
+				__func__, k, TimePerChromaMetaChunkNominal[k]);
+		dml_print("DML::%s: k=%0d, TimePerChromaMetaChunkVBlank     = %f\n",
+				__func__, k, TimePerChromaMetaChunkVBlank[k]);
+		dml_print("DML::%s: k=%0d, TimePerChromaMetaChunkFlip       = %f\n",
+				__func__, k, TimePerChromaMetaChunkFlip[k]);
+		dml_print("DML::%s: k=%0d, time_per_pte_group_nom_luma      = %f\n",
+				__func__, k, time_per_pte_group_nom_luma[k]);
+		dml_print("DML::%s: k=%0d, time_per_pte_group_vblank_luma   = %f\n",
+				__func__, k, time_per_pte_group_vblank_luma[k]);
+		dml_print("DML::%s: k=%0d, time_per_pte_group_flip_luma     = %f\n",
+				__func__, k, time_per_pte_group_flip_luma[k]);
+		dml_print("DML::%s: k=%0d, time_per_pte_group_nom_chroma    = %f\n",
+				__func__, k, time_per_pte_group_nom_chroma[k]);
+		dml_print("DML::%s: k=%0d, time_per_pte_group_vblank_chroma = %f\n",
+				__func__, k, time_per_pte_group_vblank_chroma[k]);
+		dml_print("DML::%s: k=%0d, time_per_pte_group_flip_chroma   = %f\n",
+				__func__, k, time_per_pte_group_flip_chroma[k]);
+#endif
+	}
+} // CalculateMetaAndPTETimes
+
+void dml32_CalculateVMGroupAndRequestTimes(
+		unsigned int     NumberOfActiveSurfaces,
+		bool     GPUVMEnable,
+		unsigned int     GPUVMMaxPageTableLevels,
+		unsigned int     HTotal[],
+		unsigned int     BytePerPixelC[],
+		double      DestinationLinesToRequestVMInVBlank[],
+		double      DestinationLinesToRequestVMInImmediateFlip[],
+		bool     DCCEnable[],
+		double      PixelClock[],
+		unsigned int        dpte_row_width_luma_ub[],
+		unsigned int        dpte_row_width_chroma_ub[],
+		unsigned int     vm_group_bytes[],
+		unsigned int     dpde0_bytes_per_frame_ub_l[],
+		unsigned int     dpde0_bytes_per_frame_ub_c[],
+		unsigned int        meta_pte_bytes_per_frame_ub_l[],
+		unsigned int        meta_pte_bytes_per_frame_ub_c[],
+
+		/* Output */
+		double      TimePerVMGroupVBlank[],
+		double      TimePerVMGroupFlip[],
+		double      TimePerVMRequestVBlank[],
+		double      TimePerVMRequestFlip[])
+{
+	unsigned int k;
+	unsigned int   num_group_per_lower_vm_stage;
+	unsigned int   num_req_per_lower_vm_stage;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: NumberOfActiveSurfaces = %d\n", __func__, NumberOfActiveSurfaces);
+	dml_print("DML::%s: GPUVMEnable = %d\n", __func__, GPUVMEnable);
+#endif
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%0d, DCCEnable = %d\n", __func__, k, DCCEnable[k]);
+		dml_print("DML::%s: k=%0d, vm_group_bytes = %d\n", __func__, k, vm_group_bytes[k]);
+		dml_print("DML::%s: k=%0d, dpde0_bytes_per_frame_ub_l = %d\n",
+				__func__, k, dpde0_bytes_per_frame_ub_l[k]);
+		dml_print("DML::%s: k=%0d, dpde0_bytes_per_frame_ub_c = %d\n",
+				__func__, k, dpde0_bytes_per_frame_ub_c[k]);
+		dml_print("DML::%s: k=%0d, meta_pte_bytes_per_frame_ub_l = %d\n",
+				__func__, k, meta_pte_bytes_per_frame_ub_l[k]);
+		dml_print("DML::%s: k=%0d, meta_pte_bytes_per_frame_ub_c = %d\n",
+				__func__, k, meta_pte_bytes_per_frame_ub_c[k]);
+#endif
+
+		if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
+			if (DCCEnable[k] == false) {
+				if (BytePerPixelC[k] > 0) {
+					num_group_per_lower_vm_stage = dml_ceil(
+							(double) (dpde0_bytes_per_frame_ub_l[k]) /
+							(double) (vm_group_bytes[k]), 1.0) +
+							dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) /
+							(double) (vm_group_bytes[k]), 1.0);
+				} else {
+					num_group_per_lower_vm_stage = dml_ceil(
+							(double) (dpde0_bytes_per_frame_ub_l[k]) /
+							(double) (vm_group_bytes[k]), 1.0);
+				}
+			} else {
+				if (GPUVMMaxPageTableLevels == 1) {
+					if (BytePerPixelC[k] > 0) {
+						num_group_per_lower_vm_stage = dml_ceil(
+							(double) (meta_pte_bytes_per_frame_ub_l[k]) /
+							(double) (vm_group_bytes[k]), 1.0) +
+							dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) /
+							(double) (vm_group_bytes[k]), 1.0);
+					} else {
+						num_group_per_lower_vm_stage = dml_ceil(
+								(double) (meta_pte_bytes_per_frame_ub_l[k]) /
+								(double) (vm_group_bytes[k]), 1.0);
+					}
+				} else {
+					if (BytePerPixelC[k] > 0) {
+						num_group_per_lower_vm_stage = 2 + dml_ceil(
+							(double) (dpde0_bytes_per_frame_ub_l[k]) /
+							(double) (vm_group_bytes[k]), 1) +
+							dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) /
+							(double) (vm_group_bytes[k]), 1) +
+							dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) /
+							(double) (vm_group_bytes[k]), 1) +
+							dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) /
+							(double) (vm_group_bytes[k]), 1);
+					} else {
+						num_group_per_lower_vm_stage = 1 + dml_ceil(
+							(double) (dpde0_bytes_per_frame_ub_l[k]) /
+							(double) (vm_group_bytes[k]), 1) + dml_ceil(
+							(double) (meta_pte_bytes_per_frame_ub_l[k]) /
+							(double) (vm_group_bytes[k]), 1);
+					}
+				}
+			}
+
+			if (DCCEnable[k] == false) {
+				if (BytePerPixelC[k] > 0) {
+					num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 +
+							dpde0_bytes_per_frame_ub_c[k] / 64;
+				} else {
+					num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64;
+				}
+			} else {
+				if (GPUVMMaxPageTableLevels == 1) {
+					if (BytePerPixelC[k] > 0) {
+						num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64 +
+								meta_pte_bytes_per_frame_ub_c[k] / 64;
+					} else {
+						num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64;
+					}
+				} else {
+					if (BytePerPixelC[k] > 0) {
+						num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] /
+								64 + dpde0_bytes_per_frame_ub_c[k] / 64 +
+								meta_pte_bytes_per_frame_ub_l[k] / 64 +
+								meta_pte_bytes_per_frame_ub_c[k] / 64;
+					} else {
+						num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] /
+								64 + meta_pte_bytes_per_frame_ub_l[k] / 64;
+					}
+				}
+			}
+
+			TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] *
+					HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
+			TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] *
+					HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
+			TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k] *
+					HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
+			TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] *
+					HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
+
+			if (GPUVMMaxPageTableLevels > 2) {
+				TimePerVMGroupVBlank[k]    = TimePerVMGroupVBlank[k] / 2;
+				TimePerVMGroupFlip[k]      = TimePerVMGroupFlip[k] / 2;
+				TimePerVMRequestVBlank[k]  = TimePerVMRequestVBlank[k] / 2;
+				TimePerVMRequestFlip[k]    = TimePerVMRequestFlip[k] / 2;
+			}
+
+		} else {
+			TimePerVMGroupVBlank[k] = 0;
+			TimePerVMGroupFlip[k] = 0;
+			TimePerVMRequestVBlank[k] = 0;
+			TimePerVMRequestFlip[k] = 0;
+		}
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%0d, TimePerVMGroupVBlank = %f\n", __func__, k, TimePerVMGroupVBlank[k]);
+		dml_print("DML::%s: k=%0d, TimePerVMGroupFlip = %f\n", __func__, k, TimePerVMGroupFlip[k]);
+		dml_print("DML::%s: k=%0d, TimePerVMRequestVBlank = %f\n", __func__, k, TimePerVMRequestVBlank[k]);
+		dml_print("DML::%s: k=%0d, TimePerVMRequestFlip = %f\n", __func__, k, TimePerVMRequestFlip[k]);
+#endif
+	}
+} // CalculateVMGroupAndRequestTimes
+
+void dml32_CalculateDCCConfiguration(
+		bool             DCCEnabled,
+		bool             DCCProgrammingAssumesScanDirectionUnknown,
+		enum source_format_class SourcePixelFormat,
+		unsigned int             SurfaceWidthLuma,
+		unsigned int             SurfaceWidthChroma,
+		unsigned int             SurfaceHeightLuma,
+		unsigned int             SurfaceHeightChroma,
+		unsigned int                nomDETInKByte,
+		unsigned int             RequestHeight256ByteLuma,
+		unsigned int             RequestHeight256ByteChroma,
+		enum dm_swizzle_mode     TilingFormat,
+		unsigned int             BytePerPixelY,
+		unsigned int             BytePerPixelC,
+		double              BytePerPixelDETY,
+		double              BytePerPixelDETC,
+		enum dm_rotation_angle   SourceRotation,
+		/* Output */
+		unsigned int        *MaxUncompressedBlockLuma,
+		unsigned int        *MaxUncompressedBlockChroma,
+		unsigned int        *MaxCompressedBlockLuma,
+		unsigned int        *MaxCompressedBlockChroma,
+		unsigned int        *IndependentBlockLuma,
+		unsigned int        *IndependentBlockChroma)
+{
+
+	enum RequestType   RequestLuma;
+	enum RequestType   RequestChroma;
+
+	unsigned int   segment_order_horz_contiguous_luma;
+	unsigned int   segment_order_horz_contiguous_chroma;
+	unsigned int   segment_order_vert_contiguous_luma;
+	unsigned int   segment_order_vert_contiguous_chroma;
+	unsigned int req128_horz_wc_l;
+	unsigned int req128_horz_wc_c;
+	unsigned int req128_vert_wc_l;
+	unsigned int req128_vert_wc_c;
+	unsigned int MAS_vp_horz_limit;
+	unsigned int MAS_vp_vert_limit;
+	unsigned int max_vp_horz_width;
+	unsigned int max_vp_vert_height;
+	unsigned int eff_surf_width_l;
+	unsigned int eff_surf_width_c;
+	unsigned int eff_surf_height_l;
+	unsigned int eff_surf_height_c;
+	unsigned int full_swath_bytes_horz_wc_l;
+	unsigned int full_swath_bytes_horz_wc_c;
+	unsigned int full_swath_bytes_vert_wc_l;
+	unsigned int full_swath_bytes_vert_wc_c;
+	unsigned int DETBufferSizeForDCC = nomDETInKByte * 1024;
+
+	unsigned int   yuv420;
+	unsigned int   horz_div_l;
+	unsigned int   horz_div_c;
+	unsigned int   vert_div_l;
+	unsigned int   vert_div_c;
+
+	unsigned int     swath_buf_size;
+	double   detile_buf_vp_horz_limit;
+	double   detile_buf_vp_vert_limit;
+
+	typedef enum {
+		REQ_256Bytes,
+		REQ_128BytesNonContiguous,
+		REQ_128BytesContiguous,
+		REQ_NA
+	} RequestType;
+
+	yuv420 = ((SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 ||
+			SourcePixelFormat == dm_420_12) ? 1 : 0);
+	horz_div_l = 1;
+	horz_div_c = 1;
+	vert_div_l = 1;
+	vert_div_c = 1;
+
+	if (BytePerPixelY == 1)
+		vert_div_l = 0;
+	if (BytePerPixelC == 1)
+		vert_div_c = 0;
+
+	if (BytePerPixelC == 0) {
+		swath_buf_size = DETBufferSizeForDCC / 2 - 2 * 256;
+		detile_buf_vp_horz_limit = (double) swath_buf_size / ((double) RequestHeight256ByteLuma *
+				BytePerPixelY / (1 + horz_div_l));
+		detile_buf_vp_vert_limit = (double) swath_buf_size / (256.0 / RequestHeight256ByteLuma /
+				(1 + vert_div_l));
+	} else {
+		swath_buf_size = DETBufferSizeForDCC / 2 - 2 * 2 * 256;
+		detile_buf_vp_horz_limit = (double) swath_buf_size / ((double) RequestHeight256ByteLuma *
+				BytePerPixelY / (1 + horz_div_l) + (double) RequestHeight256ByteChroma *
+				BytePerPixelC / (1 + horz_div_c) / (1 + yuv420));
+		detile_buf_vp_vert_limit = (double) swath_buf_size / (256.0 / RequestHeight256ByteLuma /
+				(1 + vert_div_l) + 256.0 / RequestHeight256ByteChroma /
+				(1 + vert_div_c) / (1 + yuv420));
+	}
+
+	if (SourcePixelFormat == dm_420_10) {
+		detile_buf_vp_horz_limit = 1.5 * detile_buf_vp_horz_limit;
+		detile_buf_vp_vert_limit = 1.5 * detile_buf_vp_vert_limit;
+	}
+
+	detile_buf_vp_horz_limit = dml_floor(detile_buf_vp_horz_limit - 1, 16);
+	detile_buf_vp_vert_limit = dml_floor(detile_buf_vp_vert_limit - 1, 16);
+
+	MAS_vp_horz_limit = SourcePixelFormat == dm_rgbe_alpha ? 3840 : 6144;
+	MAS_vp_vert_limit = SourcePixelFormat == dm_rgbe_alpha ? 3840 : (BytePerPixelY == 8 ? 3072 : 6144);
+	max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit);
+	max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit);
+	eff_surf_width_l =  (SurfaceWidthLuma > max_vp_horz_width ? max_vp_horz_width : SurfaceWidthLuma);
+	eff_surf_width_c =  eff_surf_width_l / (1 + yuv420);
+	eff_surf_height_l =  (SurfaceHeightLuma > max_vp_vert_height ? max_vp_vert_height : SurfaceHeightLuma);
+	eff_surf_height_c =  eff_surf_height_l / (1 + yuv420);
+
+	full_swath_bytes_horz_wc_l = eff_surf_width_l * RequestHeight256ByteLuma * BytePerPixelY;
+	full_swath_bytes_vert_wc_l = eff_surf_height_l * 256 / RequestHeight256ByteLuma;
+	if (BytePerPixelC > 0) {
+		full_swath_bytes_horz_wc_c = eff_surf_width_c * RequestHeight256ByteChroma * BytePerPixelC;
+		full_swath_bytes_vert_wc_c = eff_surf_height_c * 256 / RequestHeight256ByteChroma;
+	} else {
+		full_swath_bytes_horz_wc_c = 0;
+		full_swath_bytes_vert_wc_c = 0;
+	}
+
+	if (SourcePixelFormat == dm_420_10) {
+		full_swath_bytes_horz_wc_l = dml_ceil((double) full_swath_bytes_horz_wc_l * 2.0 / 3.0, 256.0);
+		full_swath_bytes_horz_wc_c = dml_ceil((double) full_swath_bytes_horz_wc_c * 2.0 / 3.0, 256.0);
+		full_swath_bytes_vert_wc_l = dml_ceil((double) full_swath_bytes_vert_wc_l * 2.0 / 3.0, 256.0);
+		full_swath_bytes_vert_wc_c = dml_ceil((double) full_swath_bytes_vert_wc_c * 2.0 / 3.0, 256.0);
+	}
+
+	if (2 * full_swath_bytes_horz_wc_l + 2 * full_swath_bytes_horz_wc_c <= DETBufferSizeForDCC) {
+		req128_horz_wc_l = 0;
+		req128_horz_wc_c = 0;
+	} else if (full_swath_bytes_horz_wc_l < 1.5 * full_swath_bytes_horz_wc_c && 2 * full_swath_bytes_horz_wc_l +
+			full_swath_bytes_horz_wc_c <= DETBufferSizeForDCC) {
+		req128_horz_wc_l = 0;
+		req128_horz_wc_c = 1;
+	} else if (full_swath_bytes_horz_wc_l >= 1.5 * full_swath_bytes_horz_wc_c && full_swath_bytes_horz_wc_l + 2 *
+			full_swath_bytes_horz_wc_c <= DETBufferSizeForDCC) {
+		req128_horz_wc_l = 1;
+		req128_horz_wc_c = 0;
+	} else {
+		req128_horz_wc_l = 1;
+		req128_horz_wc_c = 1;
+	}
+
+	if (2 * full_swath_bytes_vert_wc_l + 2 * full_swath_bytes_vert_wc_c <= DETBufferSizeForDCC) {
+		req128_vert_wc_l = 0;
+		req128_vert_wc_c = 0;
+	} else if (full_swath_bytes_vert_wc_l < 1.5 * full_swath_bytes_vert_wc_c && 2 *
+			full_swath_bytes_vert_wc_l + full_swath_bytes_vert_wc_c <= DETBufferSizeForDCC) {
+		req128_vert_wc_l = 0;
+		req128_vert_wc_c = 1;
+	} else if (full_swath_bytes_vert_wc_l >= 1.5 * full_swath_bytes_vert_wc_c &&
+			full_swath_bytes_vert_wc_l + 2 * full_swath_bytes_vert_wc_c <= DETBufferSizeForDCC) {
+		req128_vert_wc_l = 1;
+		req128_vert_wc_c = 0;
+	} else {
+		req128_vert_wc_l = 1;
+		req128_vert_wc_c = 1;
+	}
+
+	if (BytePerPixelY == 2) {
+		segment_order_horz_contiguous_luma = 0;
+		segment_order_vert_contiguous_luma = 1;
+	} else {
+		segment_order_horz_contiguous_luma = 1;
+		segment_order_vert_contiguous_luma = 0;
+	}
+
+	if (BytePerPixelC == 2) {
+		segment_order_horz_contiguous_chroma = 0;
+		segment_order_vert_contiguous_chroma = 1;
+	} else {
+		segment_order_horz_contiguous_chroma = 1;
+		segment_order_vert_contiguous_chroma = 0;
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DCCEnabled = %d\n", __func__, DCCEnabled);
+	dml_print("DML::%s: nomDETInKByte = %d\n", __func__, nomDETInKByte);
+	dml_print("DML::%s: DETBufferSizeForDCC = %d\n", __func__, DETBufferSizeForDCC);
+	dml_print("DML::%s: req128_horz_wc_l = %d\n", __func__, req128_horz_wc_l);
+	dml_print("DML::%s: req128_horz_wc_c = %d\n", __func__, req128_horz_wc_c);
+	dml_print("DML::%s: full_swath_bytes_horz_wc_l = %d\n", __func__, full_swath_bytes_horz_wc_l);
+	dml_print("DML::%s: full_swath_bytes_vert_wc_c = %d\n", __func__, full_swath_bytes_vert_wc_c);
+	dml_print("DML::%s: segment_order_horz_contiguous_luma = %d\n", __func__, segment_order_horz_contiguous_luma);
+	dml_print("DML::%s: segment_order_horz_contiguous_chroma = %d\n",
+			__func__, segment_order_horz_contiguous_chroma);
+#endif
+
+	if (DCCProgrammingAssumesScanDirectionUnknown == true) {
+		if (req128_horz_wc_l == 0 && req128_vert_wc_l == 0)
+			RequestLuma = REQ_256Bytes;
+		else if ((req128_horz_wc_l == 1 && segment_order_horz_contiguous_luma == 0) ||
+				(req128_vert_wc_l == 1 && segment_order_vert_contiguous_luma == 0))
+			RequestLuma = REQ_128BytesNonContiguous;
+		else
+			RequestLuma = REQ_128BytesContiguous;
+
+		if (req128_horz_wc_c == 0 && req128_vert_wc_c == 0)
+			RequestChroma = REQ_256Bytes;
+		else if ((req128_horz_wc_c == 1 && segment_order_horz_contiguous_chroma == 0) ||
+				(req128_vert_wc_c == 1 && segment_order_vert_contiguous_chroma == 0))
+			RequestChroma = REQ_128BytesNonContiguous;
+		else
+			RequestChroma = REQ_128BytesContiguous;
+
+	} else if (!IsVertical(SourceRotation)) {
+		if (req128_horz_wc_l == 0)
+			RequestLuma = REQ_256Bytes;
+		else if (segment_order_horz_contiguous_luma == 0)
+			RequestLuma = REQ_128BytesNonContiguous;
+		else
+			RequestLuma = REQ_128BytesContiguous;
+
+		if (req128_horz_wc_c == 0)
+			RequestChroma = REQ_256Bytes;
+		else if (segment_order_horz_contiguous_chroma == 0)
+			RequestChroma = REQ_128BytesNonContiguous;
+		else
+			RequestChroma = REQ_128BytesContiguous;
+
+	} else {
+		if (req128_vert_wc_l == 0)
+			RequestLuma = REQ_256Bytes;
+		else if (segment_order_vert_contiguous_luma == 0)
+			RequestLuma = REQ_128BytesNonContiguous;
+		else
+			RequestLuma = REQ_128BytesContiguous;
+
+		if (req128_vert_wc_c == 0)
+			RequestChroma = REQ_256Bytes;
+		else if (segment_order_vert_contiguous_chroma == 0)
+			RequestChroma = REQ_128BytesNonContiguous;
+		else
+			RequestChroma = REQ_128BytesContiguous;
+	}
+
+	if (RequestLuma == (enum RequestType) REQ_256Bytes) {
+		*MaxUncompressedBlockLuma = 256;
+		*MaxCompressedBlockLuma = 256;
+		*IndependentBlockLuma = 0;
+	} else if (RequestLuma == (enum RequestType) REQ_128BytesContiguous) {
+		*MaxUncompressedBlockLuma = 256;
+		*MaxCompressedBlockLuma = 128;
+		*IndependentBlockLuma = 128;
+	} else {
+		*MaxUncompressedBlockLuma = 256;
+		*MaxCompressedBlockLuma = 64;
+		*IndependentBlockLuma = 64;
+	}
+
+	if (RequestChroma == (enum RequestType) REQ_256Bytes) {
+		*MaxUncompressedBlockChroma = 256;
+		*MaxCompressedBlockChroma = 256;
+		*IndependentBlockChroma = 0;
+	} else if (RequestChroma == (enum RequestType) REQ_128BytesContiguous) {
+		*MaxUncompressedBlockChroma = 256;
+		*MaxCompressedBlockChroma = 128;
+		*IndependentBlockChroma = 128;
+	} else {
+		*MaxUncompressedBlockChroma = 256;
+		*MaxCompressedBlockChroma = 64;
+		*IndependentBlockChroma = 64;
+	}
+
+	if (DCCEnabled != true || BytePerPixelC == 0) {
+		*MaxUncompressedBlockChroma = 0;
+		*MaxCompressedBlockChroma = 0;
+		*IndependentBlockChroma = 0;
+	}
+
+	if (DCCEnabled != true) {
+		*MaxUncompressedBlockLuma = 0;
+		*MaxCompressedBlockLuma = 0;
+		*IndependentBlockLuma = 0;
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: MaxUncompressedBlockLuma = %d\n", __func__, *MaxUncompressedBlockLuma);
+	dml_print("DML::%s: MaxCompressedBlockLuma = %d\n", __func__, *MaxCompressedBlockLuma);
+	dml_print("DML::%s: IndependentBlockLuma = %d\n", __func__, *IndependentBlockLuma);
+	dml_print("DML::%s: MaxUncompressedBlockChroma = %d\n", __func__, *MaxUncompressedBlockChroma);
+	dml_print("DML::%s: MaxCompressedBlockChroma = %d\n", __func__, *MaxCompressedBlockChroma);
+	dml_print("DML::%s: IndependentBlockChroma = %d\n", __func__, *IndependentBlockChroma);
+#endif
+
+} // CalculateDCCConfiguration
+
+void dml32_CalculateStutterEfficiency(
+		unsigned int      CompressedBufferSizeInkByte,
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		bool   UnboundedRequestEnabled,
+		unsigned int      MetaFIFOSizeInKEntries,
+		unsigned int      ZeroSizeBufferEntries,
+		unsigned int      PixelChunkSizeInKByte,
+		unsigned int   NumberOfActiveSurfaces,
+		unsigned int      ROBBufferSizeInKByte,
+		double    TotalDataReadBandwidth,
+		double    DCFCLK,
+		double    ReturnBW,
+		unsigned int      CompbufReservedSpace64B,
+		unsigned int      CompbufReservedSpaceZs,
+		double    SRExitTime,
+		double    SRExitZ8Time,
+		bool   SynchronizeTimingsFinal,
+		unsigned int   BlendingAndTiming[],
+		double    StutterEnterPlusExitWatermark,
+		double    Z8StutterEnterPlusExitWatermark,
+		bool   ProgressiveToInterlaceUnitInOPP,
+		bool   Interlace[],
+		double    MinTTUVBlank[],
+		unsigned int   DPPPerSurface[],
+		unsigned int      DETBufferSizeY[],
+		unsigned int   BytePerPixelY[],
+		double    BytePerPixelDETY[],
+		double      SwathWidthY[],
+		unsigned int   SwathHeightY[],
+		unsigned int   SwathHeightC[],
+		double    NetDCCRateLuma[],
+		double    NetDCCRateChroma[],
+		double    DCCFractionOfZeroSizeRequestsLuma[],
+		double    DCCFractionOfZeroSizeRequestsChroma[],
+		unsigned int      HTotal[],
+		unsigned int      VTotal[],
+		double    PixelClock[],
+		double    VRatio[],
+		enum dm_rotation_angle SourceRotation[],
+		unsigned int   BlockHeight256BytesY[],
+		unsigned int   BlockWidth256BytesY[],
+		unsigned int   BlockHeight256BytesC[],
+		unsigned int   BlockWidth256BytesC[],
+		unsigned int   DCCYMaxUncompressedBlock[],
+		unsigned int   DCCCMaxUncompressedBlock[],
+		unsigned int      VActive[],
+		bool   DCCEnable[],
+		bool   WritebackEnable[],
+		double    ReadBandwidthSurfaceLuma[],
+		double    ReadBandwidthSurfaceChroma[],
+		double    meta_row_bw[],
+		double    dpte_row_bw[],
+
+		/* Output */
+		double   *StutterEfficiencyNotIncludingVBlank,
+		double   *StutterEfficiency,
+		unsigned int     *NumberOfStutterBurstsPerFrame,
+		double   *Z8StutterEfficiencyNotIncludingVBlank,
+		double   *Z8StutterEfficiency,
+		unsigned int     *Z8NumberOfStutterBurstsPerFrame,
+		double   *StutterPeriod,
+		bool  *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE)
+{
+
+	bool FoundCriticalSurface = false;
+	unsigned int SwathSizeCriticalSurface = 0;
+	unsigned int LastChunkOfSwathSize;
+	unsigned int MissingPartOfLastSwathOfDETSize;
+	double LastZ8StutterPeriod = 0.0;
+	double LastStutterPeriod = 0.0;
+	unsigned int TotalNumberOfActiveOTG = 0;
+	double doublePixelClock;
+	unsigned int doubleHTotal;
+	unsigned int doubleVTotal;
+	bool SameTiming = true;
+	double DETBufferingTimeY;
+	double SwathWidthYCriticalSurface = 0.0;
+	double SwathHeightYCriticalSurface = 0.0;
+	double VActiveTimeCriticalSurface = 0.0;
+	double FrameTimeCriticalSurface = 0.0;
+	unsigned int BytePerPixelYCriticalSurface = 0;
+	double LinesToFinishSwathTransferStutterCriticalSurface = 0.0;
+	unsigned int DETBufferSizeYCriticalSurface = 0;
+	double MinTTUVBlankCriticalSurface = 0.0;
+	unsigned int BlockWidth256BytesYCriticalSurface = 0;
+	bool doublePlaneCriticalSurface = 0;
+	bool doublePipeCriticalSurface = 0;
+	double TotalCompressedReadBandwidth;
+	double TotalRowReadBandwidth;
+	double AverageDCCCompressionRate;
+	double EffectiveCompressedBufferSize;
+	double PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer;
+	double StutterBurstTime;
+	unsigned int TotalActiveWriteback;
+	double LinesInDETY;
+	double LinesInDETYRoundedDownToSwath;
+	double MaximumEffectiveCompressionLuma;
+	double MaximumEffectiveCompressionChroma;
+	double TotalZeroSizeRequestReadBandwidth;
+	double TotalZeroSizeCompressedReadBandwidth;
+	double AverageDCCZeroSizeFraction;
+	double AverageZeroSizeCompressionRate;
+	unsigned int k;
+
+	TotalZeroSizeRequestReadBandwidth = 0;
+	TotalZeroSizeCompressedReadBandwidth = 0;
+	TotalRowReadBandwidth = 0;
+	TotalCompressedReadBandwidth = 0;
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) {
+			if (DCCEnable[k] == true) {
+				if ((IsVertical(SourceRotation[k]) && BlockWidth256BytesY[k] > SwathHeightY[k])
+						|| (!IsVertical(SourceRotation[k])
+								&& BlockHeight256BytesY[k] > SwathHeightY[k])
+						|| DCCYMaxUncompressedBlock[k] < 256) {
+					MaximumEffectiveCompressionLuma = 2;
+				} else {
+					MaximumEffectiveCompressionLuma = 4;
+				}
+				TotalCompressedReadBandwidth = TotalCompressedReadBandwidth
+						+ ReadBandwidthSurfaceLuma[k]
+								/ dml_min(NetDCCRateLuma[k],
+										MaximumEffectiveCompressionLuma);
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: k=%0d, ReadBandwidthSurfaceLuma = %f\n",
+						__func__, k, ReadBandwidthSurfaceLuma[k]);
+				dml_print("DML::%s: k=%0d, NetDCCRateLuma = %f\n",
+						__func__, k, NetDCCRateLuma[k]);
+				dml_print("DML::%s: k=%0d, MaximumEffectiveCompressionLuma = %f\n",
+						__func__, k, MaximumEffectiveCompressionLuma);
+#endif
+				TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth
+						+ ReadBandwidthSurfaceLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k];
+				TotalZeroSizeCompressedReadBandwidth = TotalZeroSizeCompressedReadBandwidth
+						+ ReadBandwidthSurfaceLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k]
+								/ MaximumEffectiveCompressionLuma;
+
+				if (ReadBandwidthSurfaceChroma[k] > 0) {
+					if ((IsVertical(SourceRotation[k]) && BlockWidth256BytesC[k] > SwathHeightC[k])
+							|| (!IsVertical(SourceRotation[k])
+									&& BlockHeight256BytesC[k] > SwathHeightC[k])
+							|| DCCCMaxUncompressedBlock[k] < 256) {
+						MaximumEffectiveCompressionChroma = 2;
+					} else {
+						MaximumEffectiveCompressionChroma = 4;
+					}
+					TotalCompressedReadBandwidth =
+							TotalCompressedReadBandwidth
+							+ ReadBandwidthSurfaceChroma[k]
+							/ dml_min(NetDCCRateChroma[k],
+							MaximumEffectiveCompressionChroma);
+#ifdef __DML_VBA_DEBUG__
+					dml_print("DML::%s: k=%0d, ReadBandwidthSurfaceChroma = %f\n",
+							__func__, k, ReadBandwidthSurfaceChroma[k]);
+					dml_print("DML::%s: k=%0d, NetDCCRateChroma = %f\n",
+							__func__, k, NetDCCRateChroma[k]);
+					dml_print("DML::%s: k=%0d, MaximumEffectiveCompressionChroma = %f\n",
+							__func__, k, MaximumEffectiveCompressionChroma);
+#endif
+					TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth
+							+ ReadBandwidthSurfaceChroma[k]
+									* DCCFractionOfZeroSizeRequestsChroma[k];
+					TotalZeroSizeCompressedReadBandwidth = TotalZeroSizeCompressedReadBandwidth
+							+ ReadBandwidthSurfaceChroma[k]
+									* DCCFractionOfZeroSizeRequestsChroma[k]
+									/ MaximumEffectiveCompressionChroma;
+				}
+			} else {
+				TotalCompressedReadBandwidth = TotalCompressedReadBandwidth
+						+ ReadBandwidthSurfaceLuma[k] + ReadBandwidthSurfaceChroma[k];
+			}
+			TotalRowReadBandwidth = TotalRowReadBandwidth
+					+ DPPPerSurface[k] * (meta_row_bw[k] + dpte_row_bw[k]);
+		}
+	}
+
+	AverageDCCCompressionRate = TotalDataReadBandwidth / TotalCompressedReadBandwidth;
+	AverageDCCZeroSizeFraction = TotalZeroSizeRequestReadBandwidth / TotalDataReadBandwidth;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: UnboundedRequestEnabled = %d\n", __func__, UnboundedRequestEnabled);
+	dml_print("DML::%s: TotalCompressedReadBandwidth = %f\n", __func__, TotalCompressedReadBandwidth);
+	dml_print("DML::%s: TotalZeroSizeRequestReadBandwidth = %f\n", __func__, TotalZeroSizeRequestReadBandwidth);
+	dml_print("DML::%s: TotalZeroSizeCompressedReadBandwidth = %f\n",
+			__func__, TotalZeroSizeCompressedReadBandwidth);
+	dml_print("DML::%s: MaximumEffectiveCompressionLuma = %f\n", __func__, MaximumEffectiveCompressionLuma);
+	dml_print("DML::%s: MaximumEffectiveCompressionChroma = %f\n", __func__, MaximumEffectiveCompressionChroma);
+	dml_print("DML::%s: AverageDCCCompressionRate = %f\n", __func__, AverageDCCCompressionRate);
+	dml_print("DML::%s: AverageDCCZeroSizeFraction = %f\n", __func__, AverageDCCZeroSizeFraction);
+	dml_print("DML::%s: CompbufReservedSpace64B = %d\n", __func__, CompbufReservedSpace64B);
+	dml_print("DML::%s: CompbufReservedSpaceZs = %d\n", __func__, CompbufReservedSpaceZs);
+	dml_print("DML::%s: CompressedBufferSizeInkByte = %d\n", __func__, CompressedBufferSizeInkByte);
+#endif
+	if (AverageDCCZeroSizeFraction == 1) {
+		AverageZeroSizeCompressionRate = TotalZeroSizeRequestReadBandwidth
+				/ TotalZeroSizeCompressedReadBandwidth;
+		EffectiveCompressedBufferSize = (double) MetaFIFOSizeInKEntries * 1024 * 64
+				* AverageZeroSizeCompressionRate
+				+ ((double) ZeroSizeBufferEntries - CompbufReservedSpaceZs) * 64
+						* AverageZeroSizeCompressionRate;
+	} else if (AverageDCCZeroSizeFraction > 0) {
+		AverageZeroSizeCompressionRate = TotalZeroSizeRequestReadBandwidth
+				/ TotalZeroSizeCompressedReadBandwidth;
+		EffectiveCompressedBufferSize = dml_min(
+				(double) CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate,
+				(double) MetaFIFOSizeInKEntries * 1024 * 64
+					/ (AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate
+					+ 1 / AverageDCCCompressionRate))
+					+ dml_min(((double) ROBBufferSizeInKByte * 1024 - CompbufReservedSpace64B * 64)
+					* AverageDCCCompressionRate,
+					((double) ZeroSizeBufferEntries - CompbufReservedSpaceZs) * 64
+					/ (AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate));
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: min 1 = %f\n", __func__,
+				CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate);
+		dml_print("DML::%s: min 2 = %f\n", __func__, MetaFIFOSizeInKEntries * 1024 * 64 /
+				(AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate + 1 /
+						AverageDCCCompressionRate));
+		dml_print("DML::%s: min 3 = %f\n", __func__, (ROBBufferSizeInKByte * 1024 -
+				CompbufReservedSpace64B * 64) * AverageDCCCompressionRate);
+		dml_print("DML::%s: min 4 = %f\n", __func__, (ZeroSizeBufferEntries - CompbufReservedSpaceZs) * 64 /
+				(AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate));
+#endif
+	} else {
+		EffectiveCompressedBufferSize = dml_min(
+				(double) CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate,
+				(double) MetaFIFOSizeInKEntries * 1024 * 64 * AverageDCCCompressionRate)
+				+ ((double) ROBBufferSizeInKByte * 1024 - CompbufReservedSpace64B * 64)
+						* AverageDCCCompressionRate;
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: min 1 = %f\n", __func__,
+				CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate);
+		dml_print("DML::%s: min 2 = %f\n", __func__,
+				MetaFIFOSizeInKEntries * 1024 * 64 * AverageDCCCompressionRate);
+#endif
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: MetaFIFOSizeInKEntries = %d\n", __func__, MetaFIFOSizeInKEntries);
+	dml_print("DML::%s: AverageZeroSizeCompressionRate = %f\n", __func__, AverageZeroSizeCompressionRate);
+	dml_print("DML::%s: EffectiveCompressedBufferSize = %f\n", __func__, EffectiveCompressedBufferSize);
+#endif
+
+	*StutterPeriod = 0;
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) {
+			LinesInDETY = ((double) DETBufferSizeY[k]
+					+ (UnboundedRequestEnabled == true ? EffectiveCompressedBufferSize : 0)
+							* ReadBandwidthSurfaceLuma[k] / TotalDataReadBandwidth)
+					/ BytePerPixelDETY[k] / SwathWidthY[k];
+			LinesInDETYRoundedDownToSwath = dml_floor(LinesInDETY, SwathHeightY[k]);
+			DETBufferingTimeY = LinesInDETYRoundedDownToSwath * ((double) HTotal[k] / PixelClock[k])
+					/ VRatio[k];
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%0d, DETBufferSizeY = %d\n", __func__, k, DETBufferSizeY[k]);
+			dml_print("DML::%s: k=%0d, BytePerPixelDETY = %f\n", __func__, k, BytePerPixelDETY[k]);
+			dml_print("DML::%s: k=%0d, SwathWidthY = %d\n", __func__, k, SwathWidthY[k]);
+			dml_print("DML::%s: k=%0d, ReadBandwidthSurfaceLuma = %f\n",
+					__func__, k, ReadBandwidthSurfaceLuma[k]);
+			dml_print("DML::%s: k=%0d, TotalDataReadBandwidth = %f\n", __func__, k, TotalDataReadBandwidth);
+			dml_print("DML::%s: k=%0d, LinesInDETY = %f\n", __func__, k, LinesInDETY);
+			dml_print("DML::%s: k=%0d, LinesInDETYRoundedDownToSwath = %f\n",
+					__func__, k, LinesInDETYRoundedDownToSwath);
+			dml_print("DML::%s: k=%0d, HTotal = %d\n", __func__, k, HTotal[k]);
+			dml_print("DML::%s: k=%0d, PixelClock = %f\n", __func__, k, PixelClock[k]);
+			dml_print("DML::%s: k=%0d, VRatio = %f\n", __func__, k, VRatio[k]);
+			dml_print("DML::%s: k=%0d, DETBufferingTimeY = %f\n", __func__, k, DETBufferingTimeY);
+			dml_print("DML::%s: k=%0d, PixelClock = %f\n", __func__, k, PixelClock[k]);
+#endif
+
+			if (!FoundCriticalSurface || DETBufferingTimeY < *StutterPeriod) {
+				bool isInterlaceTiming = Interlace[k] && !ProgressiveToInterlaceUnitInOPP;
+
+				FoundCriticalSurface = true;
+				*StutterPeriod = DETBufferingTimeY;
+				FrameTimeCriticalSurface = (
+						isInterlaceTiming ?
+								dml_floor((double) VTotal[k] / 2.0, 1.0) : VTotal[k])
+						* (double) HTotal[k] / PixelClock[k];
+				VActiveTimeCriticalSurface = (
+						isInterlaceTiming ?
+								dml_floor((double) VActive[k] / 2.0, 1.0) : VActive[k])
+						* (double) HTotal[k] / PixelClock[k];
+				BytePerPixelYCriticalSurface = BytePerPixelY[k];
+				SwathWidthYCriticalSurface = SwathWidthY[k];
+				SwathHeightYCriticalSurface = SwathHeightY[k];
+				BlockWidth256BytesYCriticalSurface = BlockWidth256BytesY[k];
+				LinesToFinishSwathTransferStutterCriticalSurface = SwathHeightY[k]
+						- (LinesInDETY - LinesInDETYRoundedDownToSwath);
+				DETBufferSizeYCriticalSurface = DETBufferSizeY[k];
+				MinTTUVBlankCriticalSurface = MinTTUVBlank[k];
+				doublePlaneCriticalSurface = (ReadBandwidthSurfaceChroma[k] == 0);
+				doublePipeCriticalSurface = (DPPPerSurface[k] == 1);
+
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: k=%0d, FoundCriticalSurface                = %d\n",
+						__func__, k, FoundCriticalSurface);
+				dml_print("DML::%s: k=%0d, StutterPeriod                       = %f\n",
+						__func__, k, *StutterPeriod);
+				dml_print("DML::%s: k=%0d, MinTTUVBlankCriticalSurface         = %f\n",
+						__func__, k, MinTTUVBlankCriticalSurface);
+				dml_print("DML::%s: k=%0d, FrameTimeCriticalSurface            = %f\n",
+						__func__, k, FrameTimeCriticalSurface);
+				dml_print("DML::%s: k=%0d, VActiveTimeCriticalSurface          = %f\n",
+						__func__, k, VActiveTimeCriticalSurface);
+				dml_print("DML::%s: k=%0d, BytePerPixelYCriticalSurface        = %d\n",
+						__func__, k, BytePerPixelYCriticalSurface);
+				dml_print("DML::%s: k=%0d, SwathWidthYCriticalSurface          = %f\n",
+						__func__, k, SwathWidthYCriticalSurface);
+				dml_print("DML::%s: k=%0d, SwathHeightYCriticalSurface         = %f\n",
+						__func__, k, SwathHeightYCriticalSurface);
+				dml_print("DML::%s: k=%0d, BlockWidth256BytesYCriticalSurface  = %d\n",
+						__func__, k, BlockWidth256BytesYCriticalSurface);
+				dml_print("DML::%s: k=%0d, doublePlaneCriticalSurface          = %d\n",
+						__func__, k, doublePlaneCriticalSurface);
+				dml_print("DML::%s: k=%0d, doublePipeCriticalSurface           = %d\n",
+						__func__, k, doublePipeCriticalSurface);
+				dml_print("DML::%s: k=%0d, LinesToFinishSwathTransferStutterCriticalSurface = %f\n",
+						__func__, k, LinesToFinishSwathTransferStutterCriticalSurface);
+#endif
+			}
+		}
+	}
+
+	PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer = dml_min(*StutterPeriod * TotalDataReadBandwidth,
+			EffectiveCompressedBufferSize);
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: ROBBufferSizeInKByte = %d\n", __func__, ROBBufferSizeInKByte);
+	dml_print("DML::%s: AverageDCCCompressionRate = %f\n", __func__, AverageDCCCompressionRate);
+	dml_print("DML::%s: StutterPeriod * TotalDataReadBandwidth = %f\n",
+			__func__, *StutterPeriod * TotalDataReadBandwidth);
+	dml_print("DML::%s: EffectiveCompressedBufferSize = %f\n", __func__, EffectiveCompressedBufferSize);
+	dml_print("DML::%s: PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer = %f\n", __func__,
+			PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer);
+	dml_print("DML::%s: ReturnBW = %f\n", __func__, ReturnBW);
+	dml_print("DML::%s: TotalDataReadBandwidth = %f\n", __func__, TotalDataReadBandwidth);
+	dml_print("DML::%s: TotalRowReadBandwidth = %f\n", __func__, TotalRowReadBandwidth);
+	dml_print("DML::%s: DCFCLK = %f\n", __func__, DCFCLK);
+#endif
+
+	StutterBurstTime = PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer / AverageDCCCompressionRate
+			/ ReturnBW
+			+ (*StutterPeriod * TotalDataReadBandwidth
+					- PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer) / (DCFCLK * 64)
+			+ *StutterPeriod * TotalRowReadBandwidth / ReturnBW;
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: Part 1 = %f\n", __func__, PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer /
+			AverageDCCCompressionRate / ReturnBW);
+	dml_print("DML::%s: StutterPeriod * TotalDataReadBandwidth = %f\n",
+			__func__, (*StutterPeriod * TotalDataReadBandwidth));
+	dml_print("DML::%s: Part 2 = %f\n", __func__, (*StutterPeriod * TotalDataReadBandwidth -
+			PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer) / (DCFCLK * 64));
+	dml_print("DML::%s: Part 3 = %f\n", __func__, *StutterPeriod * TotalRowReadBandwidth / ReturnBW);
+	dml_print("DML::%s: StutterBurstTime = %f\n", __func__, StutterBurstTime);
+#endif
+	StutterBurstTime = dml_max(StutterBurstTime,
+			LinesToFinishSwathTransferStutterCriticalSurface * BytePerPixelYCriticalSurface
+					* SwathWidthYCriticalSurface / ReturnBW);
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: Time to finish residue swath=%f\n",
+			__func__,
+			LinesToFinishSwathTransferStutterCriticalSurface *
+			BytePerPixelYCriticalSurface * SwathWidthYCriticalSurface / ReturnBW);
+#endif
+
+	TotalActiveWriteback = 0;
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (WritebackEnable[k])
+			TotalActiveWriteback = TotalActiveWriteback + 1;
+	}
+
+	if (TotalActiveWriteback == 0) {
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: SRExitTime = %f\n", __func__, SRExitTime);
+		dml_print("DML::%s: SRExitZ8Time = %f\n", __func__, SRExitZ8Time);
+		dml_print("DML::%s: StutterBurstTime = %f (final)\n", __func__, StutterBurstTime);
+		dml_print("DML::%s: StutterPeriod = %f\n", __func__, *StutterPeriod);
+#endif
+		*StutterEfficiencyNotIncludingVBlank = dml_max(0.,
+				1 - (SRExitTime + StutterBurstTime) / *StutterPeriod) * 100;
+		*Z8StutterEfficiencyNotIncludingVBlank = dml_max(0.,
+				1 - (SRExitZ8Time + StutterBurstTime) / *StutterPeriod) * 100;
+		*NumberOfStutterBurstsPerFrame = (
+				*StutterEfficiencyNotIncludingVBlank > 0 ?
+						dml_ceil(VActiveTimeCriticalSurface / *StutterPeriod, 1) : 0);
+		*Z8NumberOfStutterBurstsPerFrame = (
+				*Z8StutterEfficiencyNotIncludingVBlank > 0 ?
+						dml_ceil(VActiveTimeCriticalSurface / *StutterPeriod, 1) : 0);
+	} else {
+		*StutterEfficiencyNotIncludingVBlank = 0.;
+		*Z8StutterEfficiencyNotIncludingVBlank = 0.;
+		*NumberOfStutterBurstsPerFrame = 0;
+		*Z8NumberOfStutterBurstsPerFrame = 0;
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: VActiveTimeCriticalSurface = %f\n", __func__, VActiveTimeCriticalSurface);
+	dml_print("DML::%s: StutterEfficiencyNotIncludingVBlank = %f\n",
+			__func__, *StutterEfficiencyNotIncludingVBlank);
+	dml_print("DML::%s: Z8StutterEfficiencyNotIncludingVBlank = %f\n",
+			__func__, *Z8StutterEfficiencyNotIncludingVBlank);
+	dml_print("DML::%s: NumberOfStutterBurstsPerFrame = %d\n", __func__, *NumberOfStutterBurstsPerFrame);
+	dml_print("DML::%s: Z8NumberOfStutterBurstsPerFrame = %d\n", __func__, *Z8NumberOfStutterBurstsPerFrame);
+#endif
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) {
+			if (BlendingAndTiming[k] == k) {
+				if (TotalNumberOfActiveOTG == 0) {
+					doublePixelClock = PixelClock[k];
+					doubleHTotal = HTotal[k];
+					doubleVTotal = VTotal[k];
+				} else if (doublePixelClock != PixelClock[k] || doubleHTotal != HTotal[k]
+						|| doubleVTotal != VTotal[k]) {
+					SameTiming = false;
+				}
+				TotalNumberOfActiveOTG = TotalNumberOfActiveOTG + 1;
+			}
+		}
+	}
+
+	if (*StutterEfficiencyNotIncludingVBlank > 0) {
+		LastStutterPeriod = VActiveTimeCriticalSurface - (*NumberOfStutterBurstsPerFrame - 1) * *StutterPeriod;
+
+		if ((SynchronizeTimingsFinal || TotalNumberOfActiveOTG == 1) && SameTiming
+				&& LastStutterPeriod + MinTTUVBlankCriticalSurface > StutterEnterPlusExitWatermark) {
+			*StutterEfficiency = (1 - (*NumberOfStutterBurstsPerFrame * SRExitTime
+						+ StutterBurstTime * VActiveTimeCriticalSurface
+						/ *StutterPeriod) / FrameTimeCriticalSurface) * 100;
+		} else {
+			*StutterEfficiency = *StutterEfficiencyNotIncludingVBlank;
+		}
+	} else {
+		*StutterEfficiency = 0;
+	}
+
+	if (*Z8StutterEfficiencyNotIncludingVBlank > 0) {
+		LastZ8StutterPeriod = VActiveTimeCriticalSurface
+				- (*NumberOfStutterBurstsPerFrame - 1) * *StutterPeriod;
+		if ((SynchronizeTimingsFinal || TotalNumberOfActiveOTG == 1) && SameTiming && LastZ8StutterPeriod +
+				MinTTUVBlankCriticalSurface > Z8StutterEnterPlusExitWatermark) {
+			*Z8StutterEfficiency = (1 - (*NumberOfStutterBurstsPerFrame * SRExitZ8Time + StutterBurstTime
+				* VActiveTimeCriticalSurface / *StutterPeriod) / FrameTimeCriticalSurface) * 100;
+		} else {
+			*Z8StutterEfficiency = *Z8StutterEfficiencyNotIncludingVBlank;
+		}
+	} else {
+		*Z8StutterEfficiency = 0.;
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: LastZ8StutterPeriod = %f\n", __func__, LastZ8StutterPeriod);
+	dml_print("DML::%s: Z8StutterEnterPlusExitWatermark = %f\n", __func__, Z8StutterEnterPlusExitWatermark);
+	dml_print("DML::%s: StutterBurstTime = %f\n", __func__, StutterBurstTime);
+	dml_print("DML::%s: StutterPeriod = %f\n", __func__, *StutterPeriod);
+	dml_print("DML::%s: StutterEfficiency = %f\n", __func__, *StutterEfficiency);
+	dml_print("DML::%s: Z8StutterEfficiency = %f\n", __func__, *Z8StutterEfficiency);
+	dml_print("DML::%s: StutterEfficiencyNotIncludingVBlank = %f\n",
+			__func__, *StutterEfficiencyNotIncludingVBlank);
+	dml_print("DML::%s: Z8NumberOfStutterBurstsPerFrame = %d\n", __func__, *Z8NumberOfStutterBurstsPerFrame);
+#endif
+
+	SwathSizeCriticalSurface = BytePerPixelYCriticalSurface * SwathHeightYCriticalSurface
+			* dml_ceil(SwathWidthYCriticalSurface, BlockWidth256BytesYCriticalSurface);
+	LastChunkOfSwathSize = SwathSizeCriticalSurface % (PixelChunkSizeInKByte * 1024);
+	MissingPartOfLastSwathOfDETSize = dml_ceil(DETBufferSizeYCriticalSurface, SwathSizeCriticalSurface)
+			- DETBufferSizeYCriticalSurface;
+
+	*DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE = !(!UnboundedRequestEnabled && (NumberOfActiveSurfaces == 1)
+			&& doublePlaneCriticalSurface && doublePipeCriticalSurface && (LastChunkOfSwathSize > 0)
+			&& (LastChunkOfSwathSize <= 4096) && (MissingPartOfLastSwathOfDETSize > 0)
+			&& (MissingPartOfLastSwathOfDETSize <= LastChunkOfSwathSize));
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: SwathSizeCriticalSurface = %d\n", __func__, SwathSizeCriticalSurface);
+	dml_print("DML::%s: LastChunkOfSwathSize = %d\n", __func__, LastChunkOfSwathSize);
+	dml_print("DML::%s: MissingPartOfLastSwathOfDETSize = %d\n", __func__, MissingPartOfLastSwathOfDETSize);
+	dml_print("DML::%s: DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE = %d\n", __func__, *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE);
+#endif
+} // CalculateStutterEfficiency
+
+void dml32_CalculateMaxDETAndMinCompressedBufferSize(
+		unsigned int    ConfigReturnBufferSizeInKByte,
+		unsigned int    ROBBufferSizeInKByte,
+		unsigned int MaxNumDPP,
+		bool nomDETInKByteOverrideEnable, // VBA_DELTA, allow DV to override default DET size
+		unsigned int nomDETInKByteOverrideValue,  // VBA_DELTA
+
+		/* Output */
+		unsigned int *MaxTotalDETInKByte,
+		unsigned int *nomDETInKByte,
+		unsigned int *MinCompressedBufferSizeInKByte)
+{
+	bool     det_buff_size_override_en  = nomDETInKByteOverrideEnable;
+	unsigned int        det_buff_size_override_val = nomDETInKByteOverrideValue;
+
+	*MaxTotalDETInKByte = dml_ceil(((double)ConfigReturnBufferSizeInKByte +
+			(double) ROBBufferSizeInKByte) * 4.0 / 5.0, 64);
+	*nomDETInKByte = dml_floor((double) *MaxTotalDETInKByte / (double) MaxNumDPP, 64);
+	*MinCompressedBufferSizeInKByte = ConfigReturnBufferSizeInKByte - *MaxTotalDETInKByte;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: ConfigReturnBufferSizeInKByte = %0d\n", __func__, ConfigReturnBufferSizeInKByte);
+	dml_print("DML::%s: ROBBufferSizeInKByte = %0d\n", __func__, ROBBufferSizeInKByte);
+	dml_print("DML::%s: MaxNumDPP = %0d\n", __func__, MaxNumDPP);
+	dml_print("DML::%s: MaxTotalDETInKByte = %0d\n", __func__, *MaxTotalDETInKByte);
+	dml_print("DML::%s: nomDETInKByte = %0d\n", __func__, *nomDETInKByte);
+	dml_print("DML::%s: MinCompressedBufferSizeInKByte = %0d\n", __func__, *MinCompressedBufferSizeInKByte);
+#endif
+
+	if (det_buff_size_override_en) {
+		*nomDETInKByte = det_buff_size_override_val;
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: nomDETInKByte = %0d (override)\n", __func__, *nomDETInKByte);
+#endif
+	}
+} // CalculateMaxDETAndMinCompressedBufferSize
+
+bool dml32_CalculateVActiveBandwithSupport(unsigned int NumberOfActiveSurfaces,
+		double ReturnBW,
+		bool NotUrgentLatencyHiding[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double cursor_bw[],
+		double meta_row_bandwidth[],
+		double dpte_row_bandwidth[],
+		unsigned int NumberOfDPP[],
+		double UrgentBurstFactorLuma[],
+		double UrgentBurstFactorChroma[],
+		double UrgentBurstFactorCursor[])
+{
+	unsigned int k;
+	bool NotEnoughUrgentLatencyHiding = false;
+	bool CalculateVActiveBandwithSupport_val = false;
+	double VActiveBandwith = 0;
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (NotUrgentLatencyHiding[k]) {
+			NotEnoughUrgentLatencyHiding = true;
+		}
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		VActiveBandwith = VActiveBandwith + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k] + NumberOfDPP[k] * meta_row_bandwidth[k] + NumberOfDPP[k] * dpte_row_bandwidth[k];
+	}
+
+	CalculateVActiveBandwithSupport_val = (VActiveBandwith <= ReturnBW) && !NotEnoughUrgentLatencyHiding;
+
+#ifdef __DML_VBA_DEBUG__
+dml_print("DML::%s: NotEnoughUrgentLatencyHiding        = %d\n", __func__, NotEnoughUrgentLatencyHiding);
+dml_print("DML::%s: VActiveBandwith                     = %f\n", __func__, VActiveBandwith);
+dml_print("DML::%s: ReturnBW                            = %f\n", __func__, ReturnBW);
+dml_print("DML::%s: CalculateVActiveBandwithSupport_val = %d\n", __func__, CalculateVActiveBandwithSupport_val);
+#endif
+	return CalculateVActiveBandwithSupport_val;
+}
+
+void dml32_CalculatePrefetchBandwithSupport(unsigned int NumberOfActiveSurfaces,
+		double ReturnBW,
+		bool NotUrgentLatencyHiding[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double PrefetchBandwidthLuma[],
+		double PrefetchBandwidthChroma[],
+		double cursor_bw[],
+		double meta_row_bandwidth[],
+		double dpte_row_bandwidth[],
+		double cursor_bw_pre[],
+		double prefetch_vmrow_bw[],
+		unsigned int NumberOfDPP[],
+		double UrgentBurstFactorLuma[],
+		double UrgentBurstFactorChroma[],
+		double UrgentBurstFactorCursor[],
+		double UrgentBurstFactorLumaPre[],
+		double UrgentBurstFactorChromaPre[],
+		double UrgentBurstFactorCursorPre[],
+
+		/* output */
+		double  *PrefetchBandwidth,
+		double  *FractionOfUrgentBandwidth,
+		bool *PrefetchBandwidthSupport)
+{
+	unsigned int k;
+	bool NotEnoughUrgentLatencyHiding = false;
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (NotUrgentLatencyHiding[k]) {
+			NotEnoughUrgentLatencyHiding = true;
+		}
+	}
+
+	*PrefetchBandwidth = 0;
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		*PrefetchBandwidth = *PrefetchBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
+				ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k] + NumberOfDPP[k] * (meta_row_bandwidth[k] + dpte_row_bandwidth[k]),
+				NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
+	}
+
+	*PrefetchBandwidthSupport = (*PrefetchBandwidth <= ReturnBW) && !NotEnoughUrgentLatencyHiding;
+	*FractionOfUrgentBandwidth = *PrefetchBandwidth / ReturnBW;
+}
+
+double dml32_CalculateBandwidthAvailableForImmediateFlip(unsigned int NumberOfActiveSurfaces,
+		double ReturnBW,
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double PrefetchBandwidthLuma[],
+		double PrefetchBandwidthChroma[],
+		double cursor_bw[],
+		double cursor_bw_pre[],
+		unsigned int NumberOfDPP[],
+		double UrgentBurstFactorLuma[],
+		double UrgentBurstFactorChroma[],
+		double UrgentBurstFactorCursor[],
+		double UrgentBurstFactorLumaPre[],
+		double UrgentBurstFactorChromaPre[],
+		double UrgentBurstFactorCursorPre[])
+{
+	unsigned int k;
+	double CalculateBandwidthAvailableForImmediateFlip_val = ReturnBW;
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		CalculateBandwidthAvailableForImmediateFlip_val = CalculateBandwidthAvailableForImmediateFlip_val - dml_max(ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
+				NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
+	}
+
+	return CalculateBandwidthAvailableForImmediateFlip_val;
+}
+
+void dml32_CalculateImmediateFlipBandwithSupport(unsigned int NumberOfActiveSurfaces,
+		double ReturnBW,
+		enum immediate_flip_requirement ImmediateFlipRequirement[],
+		double final_flip_bw[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double PrefetchBandwidthLuma[],
+		double PrefetchBandwidthChroma[],
+		double cursor_bw[],
+		double meta_row_bandwidth[],
+		double dpte_row_bandwidth[],
+		double cursor_bw_pre[],
+		double prefetch_vmrow_bw[],
+		unsigned int NumberOfDPP[],
+		double UrgentBurstFactorLuma[],
+		double UrgentBurstFactorChroma[],
+		double UrgentBurstFactorCursor[],
+		double UrgentBurstFactorLumaPre[],
+		double UrgentBurstFactorChromaPre[],
+		double UrgentBurstFactorCursorPre[],
+
+		/* output */
+		double  *TotalBandwidth,
+		double  *FractionOfUrgentBandwidth,
+		bool *ImmediateFlipBandwidthSupport)
+{
+	unsigned int k;
+	*TotalBandwidth = 0;
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (ImmediateFlipRequirement[k] != dm_immediate_flip_not_required) {
+			*TotalBandwidth = *TotalBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
+					NumberOfDPP[k] * final_flip_bw[k] + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
+					NumberOfDPP[k] * (final_flip_bw[k] + PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
+		} else {
+			*TotalBandwidth = *TotalBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
+					NumberOfDPP[k] * (meta_row_bandwidth[k] + dpte_row_bandwidth[k]) + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
+					NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
+		}
+	}
+	*ImmediateFlipBandwidthSupport = (*TotalBandwidth <= ReturnBW);
+	*FractionOfUrgentBandwidth = *TotalBandwidth / ReturnBW;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
new file mode 100644
index 0000000000000..72461b934ee06
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
@@ -0,0 +1,1175 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DML_DCN32_DISPLAY_MODE_VBA_UTIL_32_H__
+#define __DML_DCN32_DISPLAY_MODE_VBA_UTIL_32_H__
+
+#include "../display_mode_enums.h"
+#include "os_types.h"
+#include "../dc_features.h"
+#include "../display_mode_structs.h"
+
+unsigned int dml32_dscceComputeDelay(
+		unsigned int bpc,
+		double BPP,
+		unsigned int sliceWidth,
+		unsigned int numSlices,
+		enum output_format_class pixelFormat,
+		enum output_encoder_class Output);
+
+unsigned int dml32_dscComputeDelay(enum output_format_class pixelFormat, enum output_encoder_class Output);
+
+bool IsVertical(enum dm_rotation_angle Scan);
+
+void dml32_CalculateBytePerPixelAndBlockSizes(
+		enum source_format_class SourcePixelFormat,
+		enum dm_swizzle_mode SurfaceTiling,
+
+		/*Output*/
+		unsigned int *BytePerPixelY,
+		unsigned int *BytePerPixelC,
+		double           *BytePerPixelDETY,
+		double           *BytePerPixelDETC,
+		unsigned int *BlockHeight256BytesY,
+		unsigned int *BlockHeight256BytesC,
+		unsigned int *BlockWidth256BytesY,
+		unsigned int *BlockWidth256BytesC,
+		unsigned int *MacroTileHeightY,
+		unsigned int *MacroTileHeightC,
+		unsigned int *MacroTileWidthY,
+		unsigned int *MacroTileWidthC);
+
+void dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(
+		double HRatio,
+		double HRatioChroma,
+		double VRatio,
+		double VRatioChroma,
+		double MaxDCHUBToPSCLThroughput,
+		double MaxPSCLToLBThroughput,
+		double PixelClock,
+		enum source_format_class SourcePixelFormat,
+		unsigned int HTaps,
+		unsigned int HTapsChroma,
+		unsigned int VTaps,
+		unsigned int VTapsChroma,
+
+		/* output */
+		double *PSCL_THROUGHPUT,
+		double *PSCL_THROUGHPUT_CHROMA,
+		double *DPPCLKUsingSingleDPP);
+
+void dml32_CalculateSwathAndDETConfiguration(
+		unsigned int DETSizeOverride[],
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		unsigned int ConfigReturnBufferSizeInKByte,
+		unsigned int MaxTotalDETInKByte,
+		unsigned int MinCompressedBufferSizeInKByte,
+		double ForceSingleDPP,
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int nomDETInKByte,
+		enum unbounded_requesting_policy UseUnboundedRequestingFinal,
+		unsigned int CompressedBufferSegmentSizeInkByteFinal,
+		enum output_encoder_class Output[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double MaximumSwathWidthLuma[],
+		double MaximumSwathWidthChroma[],
+		enum dm_rotation_angle SourceRotation[],
+		bool ViewportStationary[],
+		enum source_format_class SourcePixelFormat[],
+		enum dm_swizzle_mode SurfaceTiling[],
+		unsigned int ViewportWidth[],
+		unsigned int ViewportHeight[],
+		unsigned int ViewportXStart[],
+		unsigned int ViewportYStart[],
+		unsigned int ViewportXStartC[],
+		unsigned int ViewportYStartC[],
+		unsigned int SurfaceWidthY[],
+		unsigned int SurfaceWidthC[],
+		unsigned int SurfaceHeightY[],
+		unsigned int SurfaceHeightC[],
+		unsigned int Read256BytesBlockHeightY[],
+		unsigned int Read256BytesBlockHeightC[],
+		unsigned int Read256BytesBlockWidthY[],
+		unsigned int Read256BytesBlockWidthC[],
+		enum odm_combine_mode ODMMode[],
+		unsigned int BlendingAndTiming[],
+		unsigned int BytePerPixY[],
+		unsigned int BytePerPixC[],
+		double BytePerPixDETY[],
+		double BytePerPixDETC[],
+		unsigned int HActive[],
+		double HRatio[],
+		double HRatioChroma[],
+		unsigned int DPPPerSurface[],
+
+		/* Output */
+		unsigned int swath_width_luma_ub[],
+		unsigned int swath_width_chroma_ub[],
+		double SwathWidth[],
+		double SwathWidthChroma[],
+		unsigned int SwathHeightY[],
+		unsigned int SwathHeightC[],
+		unsigned int DETBufferSizeInKByte[],
+		unsigned int DETBufferSizeY[],
+		unsigned int DETBufferSizeC[],
+		bool *UnboundedRequestEnabled,
+		unsigned int *CompressedBufferSizeInkByte,
+		bool ViewportSizeSupportPerSurface[],
+		bool *ViewportSizeSupport);
+
+void dml32_CalculateSwathWidth(
+		bool ForceSingleDPP,
+		unsigned int NumberOfActiveSurfaces,
+		enum source_format_class SourcePixelFormat[],
+		enum dm_rotation_angle SourceScan[],
+		bool ViewportStationary[],
+		unsigned int ViewportWidth[],
+		unsigned int ViewportHeight[],
+		unsigned int ViewportXStart[],
+		unsigned int ViewportYStart[],
+		unsigned int ViewportXStartC[],
+		unsigned int ViewportYStartC[],
+		unsigned int SurfaceWidthY[],
+		unsigned int SurfaceWidthC[],
+		unsigned int SurfaceHeightY[],
+		unsigned int SurfaceHeightC[],
+		enum odm_combine_mode ODMMode[],
+		unsigned int BytePerPixY[],
+		unsigned int BytePerPixC[],
+		unsigned int Read256BytesBlockHeightY[],
+		unsigned int Read256BytesBlockHeightC[],
+		unsigned int Read256BytesBlockWidthY[],
+		unsigned int Read256BytesBlockWidthC[],
+		unsigned int BlendingAndTiming[],
+		unsigned int HActive[],
+		double HRatio[],
+		unsigned int DPPPerSurface[],
+
+		/* Output */
+		double SwathWidthdoubleDPPY[],
+		double SwathWidthdoubleDPPC[],
+		double SwathWidthY[], // per-pipe
+		double SwathWidthC[], // per-pipe
+		unsigned int MaximumSwathHeightY[],
+		unsigned int MaximumSwathHeightC[],
+		unsigned int swath_width_luma_ub[], // per-pipe
+		unsigned int swath_width_chroma_ub[]);
+
+bool dml32_UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal,
+		unsigned int TotalNumberOfActiveDPP,
+		bool NoChroma,
+		enum output_encoder_class Output);
+
+void dml32_CalculateDETBufferSize(
+		unsigned int DETSizeOverride[],
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		bool ForceSingleDPP,
+		unsigned int NumberOfActiveSurfaces,
+		bool UnboundedRequestEnabled,
+		unsigned int nomDETInKByte,
+		unsigned int MaxTotalDETInKByte,
+		unsigned int ConfigReturnBufferSizeInKByte,
+		unsigned int MinCompressedBufferSizeInKByte,
+		unsigned int CompressedBufferSegmentSizeInkByteFinal,
+		enum source_format_class SourcePixelFormat[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		unsigned int RoundedUpMaxSwathSizeBytesY[],
+		unsigned int RoundedUpMaxSwathSizeBytesC[],
+		unsigned int DPPPerSurface[],
+		/* Output */
+		unsigned int DETBufferSizeInKByte[],
+		unsigned int *CompressedBufferSizeInkByte);
+
+void dml32_CalculateODMMode(
+		unsigned int MaximumPixelsPerLinePerDSCUnit,
+		unsigned int HActive,
+		enum output_encoder_class Output,
+		enum odm_combine_policy ODMUse,
+		double StateDispclk,
+		double MaxDispclk,
+		bool DSCEnable,
+		unsigned int TotalNumberOfActiveDPP,
+		unsigned int MaxNumDPP,
+		double PixelClock,
+		double DISPCLKDPPCLKDSCCLKDownSpreading,
+		double DISPCLKRampingMargin,
+		double DISPCLKDPPCLKVCOSpeed,
+
+		/* Output */
+		bool *TotalAvailablePipesSupport,
+		unsigned int *NumberOfDPP,
+		enum odm_combine_mode *ODMMode,
+		double *RequiredDISPCLKPerSurface);
+
+double dml32_CalculateRequiredDispclk(
+		enum odm_combine_mode ODMMode,
+		double PixelClock,
+		double DISPCLKDPPCLKDSCCLKDownSpreading,
+		double DISPCLKRampingMargin,
+		double DISPCLKDPPCLKVCOSpeed,
+		double MaxDispclk);
+
+double dml32_RoundToDFSGranularity(double Clock, bool round_up, double VCOSpeed);
+
+void dml32_CalculateOutputLink(
+		double PHYCLKPerState,
+		double PHYCLKD18PerState,
+		double PHYCLKD32PerState,
+		double Downspreading,
+		bool IsMainSurfaceUsingTheIndicatedTiming,
+		enum output_encoder_class Output,
+		enum output_format_class OutputFormat,
+		unsigned int HTotal,
+		unsigned int HActive,
+		double PixelClockBackEnd,
+		double ForcedOutputLinkBPP,
+		unsigned int DSCInputBitPerComponent,
+		unsigned int NumberOfDSCSlices,
+		double AudioSampleRate,
+		unsigned int AudioSampleLayout,
+		enum odm_combine_mode ODMModeNoDSC,
+		enum odm_combine_mode ODMModeDSC,
+		bool DSCEnable,
+		unsigned int OutputLinkDPLanes,
+		enum dm_output_link_dp_rate OutputLinkDPRate,
+
+		/* Output */
+		bool *RequiresDSC,
+		double *RequiresFEC,
+		double  *OutBpp,
+		enum dm_output_type *OutputType,
+		enum dm_output_rate *OutputRate,
+		unsigned int *RequiredSlots);
+
+void dml32_CalculateDPPCLK(
+		unsigned int NumberOfActiveSurfaces,
+		double DISPCLKDPPCLKDSCCLKDownSpreading,
+		double DISPCLKDPPCLKVCOSpeed,
+		double DPPCLKUsingSingleDPP[],
+		unsigned int DPPPerSurface[],
+
+		/* output */
+		double *GlobalDPPCLK,
+		double Dppclk[]);
+
+double dml32_TruncToValidBPP(
+		double LinkBitRate,
+		unsigned int Lanes,
+		unsigned int HTotal,
+		unsigned int HActive,
+		double PixelClock,
+		double DesiredBPP,
+		bool DSCEnable,
+		enum output_encoder_class Output,
+		enum output_format_class Format,
+		unsigned int DSCInputBitPerComponent,
+		unsigned int DSCSlices,
+		unsigned int AudioRate,
+		unsigned int AudioLayout,
+		enum odm_combine_mode ODMModeNoDSC,
+		enum odm_combine_mode ODMModeDSC,
+		/* Output */
+		unsigned int *RequiredSlots);
+
+double dml32_RequiredDTBCLK(
+		bool              DSCEnable,
+		double               PixelClock,
+		enum output_format_class  OutputFormat,
+		double               OutputBpp,
+		unsigned int              DSCSlices,
+		unsigned int                 HTotal,
+		unsigned int                 HActive,
+		unsigned int              AudioRate,
+		unsigned int              AudioLayout);
+
+unsigned int dml32_DSCDelayRequirement(bool DSCEnabled,
+		enum odm_combine_mode ODMMode,
+		unsigned int DSCInputBitPerComponent,
+		double OutputBpp,
+		unsigned int HActive,
+		unsigned int HTotal,
+		unsigned int NumberOfDSCSlices,
+		enum output_format_class  OutputFormat,
+		enum output_encoder_class Output,
+		double PixelClock,
+		double PixelClockBackEnd);
+
+void dml32_CalculateSurfaceSizeInMall(
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int MALLAllocatedForDCN,
+		enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[],
+		bool DCCEnable[],
+		bool ViewportStationary[],
+		unsigned int ViewportXStartY[],
+		unsigned int ViewportYStartY[],
+		unsigned int ViewportXStartC[],
+		unsigned int ViewportYStartC[],
+		unsigned int ViewportWidthY[],
+		unsigned int ViewportHeightY[],
+		unsigned int BytesPerPixelY[],
+		unsigned int ViewportWidthC[],
+		unsigned int ViewportHeightC[],
+		unsigned int BytesPerPixelC[],
+		unsigned int SurfaceWidthY[],
+		unsigned int SurfaceWidthC[],
+		unsigned int SurfaceHeightY[],
+		unsigned int SurfaceHeightC[],
+		unsigned int Read256BytesBlockWidthY[],
+		unsigned int Read256BytesBlockWidthC[],
+		unsigned int Read256BytesBlockHeightY[],
+		unsigned int Read256BytesBlockHeightC[],
+		unsigned int ReadBlockWidthY[],
+		unsigned int ReadBlockWidthC[],
+		unsigned int ReadBlockHeightY[],
+		unsigned int ReadBlockHeightC[],
+
+		/* Output */
+		unsigned int    SurfaceSizeInMALL[],
+		bool *ExceededMALLSize);
+
+void dml32_CalculateVMRowAndSwath(
+		unsigned int NumberOfActiveSurfaces,
+		DmlPipe myPipe[],
+		unsigned int SurfaceSizeInMALL[],
+		unsigned int PTEBufferSizeInRequestsLuma,
+		unsigned int PTEBufferSizeInRequestsChroma,
+		unsigned int DCCMetaBufferSizeBytes,
+		enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[],
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		unsigned int MALLAllocatedForDCN,
+		double SwathWidthY[],
+		double SwathWidthC[],
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		unsigned int GPUVMMaxPageTableLevels,
+		unsigned int GPUVMMinPageSizeKBytes[],
+		unsigned int HostVMMinPageSize,
+
+		/* Output */
+		bool PTEBufferSizeNotExceeded[],
+		bool DCCMetaBufferSizeNotExceeded[],
+		unsigned int dpte_row_width_luma_ub[],
+		unsigned int dpte_row_width_chroma_ub[],
+		unsigned int dpte_row_height_luma[],
+		unsigned int dpte_row_height_chroma[],
+		unsigned int dpte_row_height_linear_luma[],     // VBA_DELTA
+		unsigned int dpte_row_height_linear_chroma[],   // VBA_DELTA
+		unsigned int meta_req_width[],
+		unsigned int meta_req_width_chroma[],
+		unsigned int meta_req_height[],
+		unsigned int meta_req_height_chroma[],
+		unsigned int meta_row_width[],
+		unsigned int meta_row_width_chroma[],
+		unsigned int meta_row_height[],
+		unsigned int meta_row_height_chroma[],
+		unsigned int vm_group_bytes[],
+		unsigned int dpte_group_bytes[],
+		unsigned int PixelPTEReqWidthY[],
+		unsigned int PixelPTEReqHeightY[],
+		unsigned int PTERequestSizeY[],
+		unsigned int PixelPTEReqWidthC[],
+		unsigned int PixelPTEReqHeightC[],
+		unsigned int PTERequestSizeC[],
+		unsigned int dpde0_bytes_per_frame_ub_l[],
+		unsigned int meta_pte_bytes_per_frame_ub_l[],
+		unsigned int dpde0_bytes_per_frame_ub_c[],
+		unsigned int meta_pte_bytes_per_frame_ub_c[],
+		double PrefetchSourceLinesY[],
+		double PrefetchSourceLinesC[],
+		double VInitPreFillY[],
+		double VInitPreFillC[],
+		unsigned int MaxNumSwathY[],
+		unsigned int MaxNumSwathC[],
+		double meta_row_bw[],
+		double dpte_row_bw[],
+		double PixelPTEBytesPerRow[],
+		double PDEAndMetaPTEBytesFrame[],
+		double MetaRowByte[],
+		bool use_one_row_for_frame[],
+		bool use_one_row_for_frame_flip[],
+		bool UsesMALLForStaticScreen[],
+		bool PTE_BUFFER_MODE[],
+		unsigned int BIGK_FRAGMENT_SIZE[]);
+
+unsigned int dml32_CalculateVMAndRowBytes(
+		bool ViewportStationary,
+		bool DCCEnable,
+		unsigned int NumberOfDPPs,
+		unsigned int BlockHeight256Bytes,
+		unsigned int BlockWidth256Bytes,
+		enum source_format_class SourcePixelFormat,
+		unsigned int SurfaceTiling,
+		unsigned int BytePerPixel,
+		enum dm_rotation_angle SourceScan,
+		double SwathWidth,
+		unsigned int ViewportHeight,
+		unsigned int    ViewportXStart,
+		unsigned int    ViewportYStart,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		unsigned int GPUVMMaxPageTableLevels,
+		unsigned int GPUVMMinPageSizeKBytes,
+		unsigned int HostVMMinPageSize,
+		unsigned int PTEBufferSizeInRequests,
+		unsigned int Pitch,
+		unsigned int DCCMetaPitch,
+		unsigned int MacroTileWidth,
+		unsigned int MacroTileHeight,
+
+		/* Output */
+		unsigned int *MetaRowByte,
+		unsigned int *PixelPTEBytesPerRow,
+		unsigned int    *dpte_row_width_ub,
+		unsigned int *dpte_row_height,
+		unsigned int *dpte_row_height_linear,
+		unsigned int    *PixelPTEBytesPerRow_one_row_per_frame,
+		unsigned int    *dpte_row_width_ub_one_row_per_frame,
+		unsigned int    *dpte_row_height_one_row_per_frame,
+		unsigned int *MetaRequestWidth,
+		unsigned int *MetaRequestHeight,
+		unsigned int *meta_row_width,
+		unsigned int *meta_row_height,
+		unsigned int *PixelPTEReqWidth,
+		unsigned int *PixelPTEReqHeight,
+		unsigned int *PTERequestSize,
+		unsigned int    *DPDE0BytesFrame,
+		unsigned int    *MetaPTEBytesFrame);
+
+double dml32_CalculatePrefetchSourceLines(
+		double VRatio,
+		unsigned int VTaps,
+		bool Interlace,
+		bool ProgressiveToInterlaceUnitInOPP,
+		unsigned int SwathHeight,
+		enum dm_rotation_angle SourceRotation,
+		bool ViewportStationary,
+		double SwathWidth,
+		unsigned int ViewportHeight,
+		unsigned int ViewportXStart,
+		unsigned int ViewportYStart,
+
+		/* Output */
+		double *VInitPreFill,
+		unsigned int *MaxNumSwath);
+
+void dml32_CalculateMALLUseForStaticScreen(
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int MALLAllocatedForDCNFinal,
+		enum dm_use_mall_for_static_screen_mode *UseMALLForStaticScreen,
+		unsigned int SurfaceSizeInMALL[],
+		bool one_row_per_frame_fits_in_buffer[],
+
+		/* output */
+		bool UsesMALLForStaticScreen[]);
+
+void dml32_CalculateRowBandwidth(
+		bool GPUVMEnable,
+		enum source_format_class SourcePixelFormat,
+		double VRatio,
+		double VRatioChroma,
+		bool DCCEnable,
+		double LineTime,
+		unsigned int MetaRowByteLuma,
+		unsigned int MetaRowByteChroma,
+		unsigned int meta_row_height_luma,
+		unsigned int meta_row_height_chroma,
+		unsigned int PixelPTEBytesPerRowLuma,
+		unsigned int PixelPTEBytesPerRowChroma,
+		unsigned int dpte_row_height_luma,
+		unsigned int dpte_row_height_chroma,
+		/* Output */
+		double *meta_row_bw,
+		double *dpte_row_bw);
+
+double dml32_CalculateUrgentLatency(
+		double UrgentLatencyPixelDataOnly,
+		double UrgentLatencyPixelMixedWithVMData,
+		double UrgentLatencyVMDataOnly,
+		bool   DoUrgentLatencyAdjustment,
+		double UrgentLatencyAdjustmentFabricClockComponent,
+		double UrgentLatencyAdjustmentFabricClockReference,
+		double FabricClock);
+
+void dml32_CalculateUrgentBurstFactor(
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange,
+		unsigned int    swath_width_luma_ub,
+		unsigned int    swath_width_chroma_ub,
+		unsigned int SwathHeightY,
+		unsigned int SwathHeightC,
+		double  LineTime,
+		double  UrgentLatency,
+		double  CursorBufferSize,
+		unsigned int CursorWidth,
+		unsigned int CursorBPP,
+		double  VRatio,
+		double  VRatioC,
+		double  BytePerPixelInDETY,
+		double  BytePerPixelInDETC,
+		unsigned int    DETBufferSizeY,
+		unsigned int    DETBufferSizeC,
+		/* Output */
+		double *UrgentBurstFactorCursor,
+		double *UrgentBurstFactorLuma,
+		double *UrgentBurstFactorChroma,
+		bool   *NotEnoughUrgentLatencyHiding);
+
+void dml32_CalculateDCFCLKDeepSleep(
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int BytePerPixelY[],
+		unsigned int BytePerPixelC[],
+		double VRatio[],
+		double VRatioChroma[],
+		double SwathWidthY[],
+		double SwathWidthC[],
+		unsigned int DPPPerSurface[],
+		double HRatio[],
+		double HRatioChroma[],
+		double PixelClock[],
+		double PSCL_THROUGHPUT[],
+		double PSCL_THROUGHPUT_CHROMA[],
+		double Dppclk[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		unsigned int ReturnBusWidth,
+
+		/* Output */
+		double *DCFClkDeepSleep);
+
+double dml32_CalculateWriteBackDelay(
+		enum source_format_class WritebackPixelFormat,
+		double WritebackHRatio,
+		double WritebackVRatio,
+		unsigned int WritebackVTaps,
+		unsigned int         WritebackDestinationWidth,
+		unsigned int         WritebackDestinationHeight,
+		unsigned int         WritebackSourceHeight,
+		unsigned int HTotal);
+
+void dml32_UseMinimumDCFCLK(
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		bool DRRDisplay[],
+		bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+		unsigned int MaxInterDCNTileRepeaters,
+		unsigned int MaxPrefetchMode,
+		double DRAMClockChangeLatencyFinal,
+		double FCLKChangeLatency,
+		double SREnterPlusExitTime,
+		unsigned int ReturnBusWidth,
+		unsigned int RoundTripPingLatencyCycles,
+		unsigned int ReorderingBytes,
+		unsigned int PixelChunkSizeInKByte,
+		unsigned int MetaChunkSize,
+		bool GPUVMEnable,
+		unsigned int GPUVMMaxPageTableLevels,
+		bool HostVMEnable,
+		unsigned int NumberOfActiveSurfaces,
+		double HostVMMinPageSize,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		bool DynamicMetadataVMEnabled,
+		bool ImmediateFlipRequirement,
+		bool ProgressiveToInterlaceUnitInOPP,
+		double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation,
+		double PercentOfIdealSDPPortBWReceivedAfterUrgLatency,
+		unsigned int VTotal[],
+		unsigned int VActive[],
+		unsigned int DynamicMetadataTransmittedBytes[],
+		unsigned int DynamicMetadataLinesBeforeActiveRequired[],
+		bool Interlace[],
+		double RequiredDPPCLKPerSurface[][2][DC__NUM_DPP__MAX],
+		double RequiredDISPCLK[][2],
+		double UrgLatency[],
+		unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX],
+		double ProjectedDCFClkDeepSleep[][2],
+		double MaximumVStartup[][2][DC__NUM_DPP__MAX],
+		unsigned int TotalNumberOfActiveDPP[][2],
+		unsigned int TotalNumberOfDCCActiveDPP[][2],
+		unsigned int dpte_group_bytes[],
+		double PrefetchLinesY[][2][DC__NUM_DPP__MAX],
+		double PrefetchLinesC[][2][DC__NUM_DPP__MAX],
+		unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		unsigned int BytePerPixelY[],
+		unsigned int BytePerPixelC[],
+		unsigned int HTotal[],
+		double PixelClock[],
+		double PDEAndMetaPTEBytesPerFrame[][2][DC__NUM_DPP__MAX],
+		double DPTEBytesPerRow[][2][DC__NUM_DPP__MAX],
+		double MetaRowBytes[][2][DC__NUM_DPP__MAX],
+		bool DynamicMetadataEnable[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double DCFCLKPerState[],
+		/* Output */
+		double DCFCLKState[][2]);
+
+unsigned int dml32_CalculateExtraLatencyBytes(unsigned int ReorderingBytes,
+		unsigned int TotalNumberOfActiveDPP,
+		unsigned int PixelChunkSizeInKByte,
+		unsigned int TotalNumberOfDCCActiveDPP,
+		unsigned int MetaChunkSize,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int NumberOfDPP[],
+		unsigned int dpte_group_bytes[],
+		double HostVMInefficiencyFactor,
+		double HostVMMinPageSize,
+		unsigned int HostVMMaxNonCachedPageTableLevels);
+
+void dml32_CalculateVUpdateAndDynamicMetadataParameters(
+		unsigned int MaxInterDCNTileRepeaters,
+		double Dppclk,
+		double Dispclk,
+		double DCFClkDeepSleep,
+		double PixelClock,
+		unsigned int HTotal,
+		unsigned int VBlank,
+		unsigned int DynamicMetadataTransmittedBytes,
+		unsigned int DynamicMetadataLinesBeforeActiveRequired,
+		unsigned int InterlaceEnable,
+		bool ProgressiveToInterlaceUnitInOPP,
+		double *TSetup,
+		double *Tdmbf,
+		double *Tdmec,
+		double *Tdmsks,
+		unsigned int *VUpdateOffsetPix,
+		double *VUpdateWidthPix,
+		double *VReadyOffsetPix);
+
+double dml32_CalculateTWait(
+		unsigned int PrefetchMode,
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange,
+		bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+		bool DRRDisplay,
+		double DRAMClockChangeLatency,
+		double FCLKChangeLatency,
+		double UrgentLatency,
+		double SREnterPlusExitTime);
+
+double dml32_get_return_bw_mbps(const soc_bounding_box_st *soc,
+		const int VoltageLevel,
+		const bool HostVMEnable,
+		const double DCFCLK,
+		const double FabricClock,
+		const double DRAMSpeed);
+
+double dml32_get_return_bw_mbps_vm_only(const soc_bounding_box_st *soc,
+		const int VoltageLevel,
+		const double DCFCLK,
+		const double FabricClock,
+		const double DRAMSpeed);
+
+double dml32_CalculateExtraLatency(
+		unsigned int RoundTripPingLatencyCycles,
+		unsigned int ReorderingBytes,
+		double DCFCLK,
+		unsigned int TotalNumberOfActiveDPP,
+		unsigned int PixelChunkSizeInKByte,
+		unsigned int TotalNumberOfDCCActiveDPP,
+		unsigned int MetaChunkSize,
+		double ReturnBW,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int NumberOfDPP[],
+		unsigned int dpte_group_bytes[],
+		double HostVMInefficiencyFactor,
+		double HostVMMinPageSize,
+		unsigned int HostVMMaxNonCachedPageTableLevels);
+
+bool dml32_CalculatePrefetchSchedule(
+		double HostVMInefficiencyFactor,
+		DmlPipe *myPipe,
+		unsigned int DSCDelay,
+		double DPPCLKDelaySubtotalPlusCNVCFormater,
+		double DPPCLKDelaySCL,
+		double DPPCLKDelaySCLLBOnly,
+		double DPPCLKDelayCNVCCursor,
+		double DISPCLKDelaySubtotal,
+		unsigned int DPP_RECOUT_WIDTH,
+		enum output_format_class OutputFormat,
+		unsigned int MaxInterDCNTileRepeaters,
+		unsigned int VStartup,
+		unsigned int MaxVStartup,
+		unsigned int GPUVMPageTableLevels,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		double HostVMMinPageSize,
+		bool DynamicMetadataEnable,
+		bool DynamicMetadataVMEnabled,
+		int DynamicMetadataLinesBeforeActiveRequired,
+		unsigned int DynamicMetadataTransmittedBytes,
+		double UrgentLatency,
+		double UrgentExtraLatency,
+		double TCalc,
+		unsigned int PDEAndMetaPTEBytesFrame,
+		unsigned int MetaRowByte,
+		unsigned int PixelPTEBytesPerRow,
+		double PrefetchSourceLinesY,
+		unsigned int SwathWidthY,
+		unsigned int VInitPreFillY,
+		unsigned int MaxNumSwathY,
+		double PrefetchSourceLinesC,
+		unsigned int SwathWidthC,
+		unsigned int VInitPreFillC,
+		unsigned int MaxNumSwathC,
+		unsigned int swath_width_luma_ub,
+		unsigned int swath_width_chroma_ub,
+		unsigned int SwathHeightY,
+		unsigned int SwathHeightC,
+		double TWait,
+		/* Output */
+		double   *DSTXAfterScaler,
+		double   *DSTYAfterScaler,
+		double *DestinationLinesForPrefetch,
+		double *PrefetchBandwidth,
+		double *DestinationLinesToRequestVMInVBlank,
+		double *DestinationLinesToRequestRowInVBlank,
+		double *VRatioPrefetchY,
+		double *VRatioPrefetchC,
+		double *RequiredPrefetchPixDataBWLuma,
+		double *RequiredPrefetchPixDataBWChroma,
+		bool   *NotEnoughTimeForDynamicMetadata,
+		double *Tno_bw,
+		double *prefetch_vmrow_bw,
+		double *Tdmdl_vm,
+		double *Tdmdl,
+		double *TSetup,
+		unsigned int   *VUpdateOffsetPix,
+		double   *VUpdateWidthPix,
+		double   *VReadyOffsetPix);
+
+void dml32_CalculateFlipSchedule(
+		double HostVMInefficiencyFactor,
+		double UrgentExtraLatency,
+		double UrgentLatency,
+		unsigned int GPUVMMaxPageTableLevels,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		bool GPUVMEnable,
+		double HostVMMinPageSize,
+		double PDEAndMetaPTEBytesPerFrame,
+		double MetaRowBytes,
+		double DPTEBytesPerRow,
+		double BandwidthAvailableForImmediateFlip,
+		unsigned int TotImmediateFlipBytes,
+		enum source_format_class SourcePixelFormat,
+		double LineTime,
+		double VRatio,
+		double VRatioChroma,
+		double Tno_bw,
+		bool DCCEnable,
+		unsigned int dpte_row_height,
+		unsigned int meta_row_height,
+		unsigned int dpte_row_height_chroma,
+		unsigned int meta_row_height_chroma,
+		bool    use_one_row_for_frame_flip,
+
+		/* Output */
+		double *DestinationLinesToRequestVMInImmediateFlip,
+		double *DestinationLinesToRequestRowInImmediateFlip,
+		double *final_flip_bw,
+		bool *ImmediateFlipSupportedForPipe);
+
+void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
+		bool USRRetrainingRequiredFinal,
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		unsigned int PrefetchMode,
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int MaxLineBufferLines,
+		unsigned int LineBufferSize,
+		unsigned int WritebackInterfaceBufferSize,
+		double DCFCLK,
+		double ReturnBW,
+		bool SynchronizeTimingsFinal,
+		bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+		bool DRRDisplay[],
+		unsigned int dpte_group_bytes[],
+		unsigned int meta_row_height[],
+		unsigned int meta_row_height_chroma[],
+		SOCParametersList mmSOCParameters,
+		unsigned int WritebackChunkSize,
+		double SOCCLK,
+		double DCFClkDeepSleep,
+		unsigned int DETBufferSizeY[],
+		unsigned int DETBufferSizeC[],
+		unsigned int SwathHeightY[],
+		unsigned int SwathHeightC[],
+		unsigned int LBBitPerPixel[],
+		double SwathWidthY[],
+		double SwathWidthC[],
+		double HRatio[],
+		double HRatioChroma[],
+		unsigned int VTaps[],
+		unsigned int VTapsChroma[],
+		double VRatio[],
+		double VRatioChroma[],
+		unsigned int HTotal[],
+		unsigned int VTotal[],
+		unsigned int VActive[],
+		double PixelClock[],
+		unsigned int BlendingAndTiming[],
+		unsigned int DPPPerSurface[],
+		double BytePerPixelDETY[],
+		double BytePerPixelDETC[],
+		double DSTXAfterScaler[],
+		double DSTYAfterScaler[],
+		bool WritebackEnable[],
+		enum source_format_class WritebackPixelFormat[],
+		double WritebackDestinationWidth[],
+		double WritebackDestinationHeight[],
+		double WritebackSourceHeight[],
+		bool UnboundedRequestEnabled,
+		unsigned int CompressedBufferSizeInkByte,
+
+		/* Output */
+		Watermarks *Watermark,
+		enum clock_change_support *DRAMClockChangeSupport,
+		double MaxActiveDRAMClockChangeLatencySupported[],
+		unsigned int SubViewportLinesNeededInMALL[],
+		enum dm_fclock_change_support *FCLKChangeSupport,
+		double *MinActiveFCLKChangeLatencySupported,
+		bool *USRRetrainingSupport,
+		double ActiveDRAMClockChangeLatencyMargin[]);
+
+double dml32_CalculateWriteBackDISPCLK(
+		enum source_format_class WritebackPixelFormat,
+		double PixelClock,
+		double WritebackHRatio,
+		double WritebackVRatio,
+		unsigned int WritebackHTaps,
+		unsigned int WritebackVTaps,
+		unsigned int   WritebackSourceWidth,
+		unsigned int   WritebackDestinationWidth,
+		unsigned int HTotal,
+		unsigned int WritebackLineBufferSize,
+		double DISPCLKDPPCLKVCOSpeed);
+
+void dml32_CalculateMinAndMaxPrefetchMode(
+		enum dm_prefetch_modes   AllowForPStateChangeOrStutterInVBlankFinal,
+		unsigned int             *MinPrefetchMode,
+		unsigned int             *MaxPrefetchMode);
+
+void dml32_CalculatePixelDeliveryTimes(
+		unsigned int             NumberOfActiveSurfaces,
+		double              VRatio[],
+		double              VRatioChroma[],
+		double              VRatioPrefetchY[],
+		double              VRatioPrefetchC[],
+		unsigned int             swath_width_luma_ub[],
+		unsigned int             swath_width_chroma_ub[],
+		unsigned int             DPPPerSurface[],
+		double              HRatio[],
+		double              HRatioChroma[],
+		double              PixelClock[],
+		double              PSCL_THROUGHPUT[],
+		double              PSCL_THROUGHPUT_CHROMA[],
+		double              Dppclk[],
+		unsigned int             BytePerPixelC[],
+		enum dm_rotation_angle   SourceRotation[],
+		unsigned int             NumberOfCursors[],
+		unsigned int             CursorWidth[][DC__NUM_CURSOR__MAX],
+		unsigned int             CursorBPP[][DC__NUM_CURSOR__MAX],
+		unsigned int             BlockWidth256BytesY[],
+		unsigned int             BlockHeight256BytesY[],
+		unsigned int             BlockWidth256BytesC[],
+		unsigned int             BlockHeight256BytesC[],
+
+		/* Output */
+		double              DisplayPipeLineDeliveryTimeLuma[],
+		double              DisplayPipeLineDeliveryTimeChroma[],
+		double              DisplayPipeLineDeliveryTimeLumaPrefetch[],
+		double              DisplayPipeLineDeliveryTimeChromaPrefetch[],
+		double              DisplayPipeRequestDeliveryTimeLuma[],
+		double              DisplayPipeRequestDeliveryTimeChroma[],
+		double              DisplayPipeRequestDeliveryTimeLumaPrefetch[],
+		double              DisplayPipeRequestDeliveryTimeChromaPrefetch[],
+		double              CursorRequestDeliveryTime[],
+		double              CursorRequestDeliveryTimePrefetch[]);
+
+void dml32_CalculateMetaAndPTETimes(
+		bool use_one_row_for_frame[],
+		unsigned int NumberOfActiveSurfaces,
+		bool GPUVMEnable,
+		unsigned int MetaChunkSize,
+		unsigned int MinMetaChunkSizeBytes,
+		unsigned int    HTotal[],
+		double  VRatio[],
+		double  VRatioChroma[],
+		double  DestinationLinesToRequestRowInVBlank[],
+		double  DestinationLinesToRequestRowInImmediateFlip[],
+		bool DCCEnable[],
+		double  PixelClock[],
+		unsigned int BytePerPixelY[],
+		unsigned int BytePerPixelC[],
+		enum dm_rotation_angle SourceRotation[],
+		unsigned int dpte_row_height[],
+		unsigned int dpte_row_height_chroma[],
+		unsigned int meta_row_width[],
+		unsigned int meta_row_width_chroma[],
+		unsigned int meta_row_height[],
+		unsigned int meta_row_height_chroma[],
+		unsigned int meta_req_width[],
+		unsigned int meta_req_width_chroma[],
+		unsigned int meta_req_height[],
+		unsigned int meta_req_height_chroma[],
+		unsigned int dpte_group_bytes[],
+		unsigned int    PTERequestSizeY[],
+		unsigned int    PTERequestSizeC[],
+		unsigned int    PixelPTEReqWidthY[],
+		unsigned int    PixelPTEReqHeightY[],
+		unsigned int    PixelPTEReqWidthC[],
+		unsigned int    PixelPTEReqHeightC[],
+		unsigned int    dpte_row_width_luma_ub[],
+		unsigned int    dpte_row_width_chroma_ub[],
+
+		/* Output */
+		double DST_Y_PER_PTE_ROW_NOM_L[],
+		double DST_Y_PER_PTE_ROW_NOM_C[],
+		double DST_Y_PER_META_ROW_NOM_L[],
+		double DST_Y_PER_META_ROW_NOM_C[],
+		double TimePerMetaChunkNominal[],
+		double TimePerChromaMetaChunkNominal[],
+		double TimePerMetaChunkVBlank[],
+		double TimePerChromaMetaChunkVBlank[],
+		double TimePerMetaChunkFlip[],
+		double TimePerChromaMetaChunkFlip[],
+		double time_per_pte_group_nom_luma[],
+		double time_per_pte_group_vblank_luma[],
+		double time_per_pte_group_flip_luma[],
+		double time_per_pte_group_nom_chroma[],
+		double time_per_pte_group_vblank_chroma[],
+		double time_per_pte_group_flip_chroma[]);
+
+void dml32_CalculateVMGroupAndRequestTimes(
+		unsigned int     NumberOfActiveSurfaces,
+		bool     GPUVMEnable,
+		unsigned int     GPUVMMaxPageTableLevels,
+		unsigned int     HTotal[],
+		unsigned int     BytePerPixelC[],
+		double      DestinationLinesToRequestVMInVBlank[],
+		double      DestinationLinesToRequestVMInImmediateFlip[],
+		bool     DCCEnable[],
+		double      PixelClock[],
+		unsigned int        dpte_row_width_luma_ub[],
+		unsigned int        dpte_row_width_chroma_ub[],
+		unsigned int     vm_group_bytes[],
+		unsigned int     dpde0_bytes_per_frame_ub_l[],
+		unsigned int     dpde0_bytes_per_frame_ub_c[],
+		unsigned int        meta_pte_bytes_per_frame_ub_l[],
+		unsigned int        meta_pte_bytes_per_frame_ub_c[],
+
+		/* Output */
+		double      TimePerVMGroupVBlank[],
+		double      TimePerVMGroupFlip[],
+		double      TimePerVMRequestVBlank[],
+		double      TimePerVMRequestFlip[]);
+
+void dml32_CalculateDCCConfiguration(
+		bool             DCCEnabled,
+		bool             DCCProgrammingAssumesScanDirectionUnknown,
+		enum source_format_class SourcePixelFormat,
+		unsigned int             SurfaceWidthLuma,
+		unsigned int             SurfaceWidthChroma,
+		unsigned int             SurfaceHeightLuma,
+		unsigned int             SurfaceHeightChroma,
+		unsigned int                nomDETInKByte,
+		unsigned int             RequestHeight256ByteLuma,
+		unsigned int             RequestHeight256ByteChroma,
+		enum dm_swizzle_mode     TilingFormat,
+		unsigned int             BytePerPixelY,
+		unsigned int             BytePerPixelC,
+		double              BytePerPixelDETY,
+		double              BytePerPixelDETC,
+		enum dm_rotation_angle   SourceRotation,
+		/* Output */
+		unsigned int        *MaxUncompressedBlockLuma,
+		unsigned int        *MaxUncompressedBlockChroma,
+		unsigned int        *MaxCompressedBlockLuma,
+		unsigned int        *MaxCompressedBlockChroma,
+		unsigned int        *IndependentBlockLuma,
+		unsigned int        *IndependentBlockChroma);
+
+void dml32_CalculateStutterEfficiency(
+		unsigned int      CompressedBufferSizeInkByte,
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		bool   UnboundedRequestEnabled,
+		unsigned int      MetaFIFOSizeInKEntries,
+		unsigned int      ZeroSizeBufferEntries,
+		unsigned int      PixelChunkSizeInKByte,
+		unsigned int   NumberOfActiveSurfaces,
+		unsigned int      ROBBufferSizeInKByte,
+		double    TotalDataReadBandwidth,
+		double    DCFCLK,
+		double    ReturnBW,
+		unsigned int      CompbufReservedSpace64B,
+		unsigned int      CompbufReservedSpaceZs,
+		double    SRExitTime,
+		double    SRExitZ8Time,
+		bool   SynchronizeTimingsFinal,
+		unsigned int   BlendingAndTiming[],
+		double    StutterEnterPlusExitWatermark,
+		double    Z8StutterEnterPlusExitWatermark,
+		bool   ProgressiveToInterlaceUnitInOPP,
+		bool   Interlace[],
+		double    MinTTUVBlank[],
+		unsigned int   DPPPerSurface[],
+		unsigned int      DETBufferSizeY[],
+		unsigned int   BytePerPixelY[],
+		double    BytePerPixelDETY[],
+		double      SwathWidthY[],
+		unsigned int   SwathHeightY[],
+		unsigned int   SwathHeightC[],
+		double    NetDCCRateLuma[],
+		double    NetDCCRateChroma[],
+		double    DCCFractionOfZeroSizeRequestsLuma[],
+		double    DCCFractionOfZeroSizeRequestsChroma[],
+		unsigned int      HTotal[],
+		unsigned int      VTotal[],
+		double    PixelClock[],
+		double    VRatio[],
+		enum dm_rotation_angle SourceRotation[],
+		unsigned int   BlockHeight256BytesY[],
+		unsigned int   BlockWidth256BytesY[],
+		unsigned int   BlockHeight256BytesC[],
+		unsigned int   BlockWidth256BytesC[],
+		unsigned int   DCCYMaxUncompressedBlock[],
+		unsigned int   DCCCMaxUncompressedBlock[],
+		unsigned int      VActive[],
+		bool   DCCEnable[],
+		bool   WritebackEnable[],
+		double    ReadBandwidthSurfaceLuma[],
+		double    ReadBandwidthSurfaceChroma[],
+		double    meta_row_bw[],
+		double    dpte_row_bw[],
+
+		/* Output */
+		double   *StutterEfficiencyNotIncludingVBlank,
+		double   *StutterEfficiency,
+		unsigned int     *NumberOfStutterBurstsPerFrame,
+		double   *Z8StutterEfficiencyNotIncludingVBlank,
+		double   *Z8StutterEfficiency,
+		unsigned int     *Z8NumberOfStutterBurstsPerFrame,
+		double   *StutterPeriod,
+		bool  *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE);
+
+void dml32_CalculateMaxDETAndMinCompressedBufferSize(
+		unsigned int    ConfigReturnBufferSizeInKByte,
+		unsigned int    ROBBufferSizeInKByte,
+		unsigned int MaxNumDPP,
+		bool nomDETInKByteOverrideEnable, // VBA_DELTA, allow DV to override default DET size
+		unsigned int nomDETInKByteOverrideValue,  // VBA_DELTA
+
+		/* Output */
+		unsigned int *MaxTotalDETInKByte,
+		unsigned int *nomDETInKByte,
+		unsigned int *MinCompressedBufferSizeInKByte);
+
+bool dml32_CalculateVActiveBandwithSupport(unsigned int NumberOfActiveSurfaces,
+		double ReturnBW,
+		bool NotUrgentLatencyHiding[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double cursor_bw[],
+		double meta_row_bandwidth[],
+		double dpte_row_bandwidth[],
+		unsigned int NumberOfDPP[],
+		double UrgentBurstFactorLuma[],
+		double UrgentBurstFactorChroma[],
+		double UrgentBurstFactorCursor[]);
+
+void dml32_CalculatePrefetchBandwithSupport(unsigned int NumberOfActiveSurfaces,
+		double ReturnBW,
+		bool NotUrgentLatencyHiding[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double PrefetchBandwidthLuma[],
+		double PrefetchBandwidthChroma[],
+		double cursor_bw[],
+		double meta_row_bandwidth[],
+		double dpte_row_bandwidth[],
+		double cursor_bw_pre[],
+		double prefetch_vmrow_bw[],
+		unsigned int NumberOfDPP[],
+		double UrgentBurstFactorLuma[],
+		double UrgentBurstFactorChroma[],
+		double UrgentBurstFactorCursor[],
+		double UrgentBurstFactorLumaPre[],
+		double UrgentBurstFactorChromaPre[],
+		double UrgentBurstFactorCursorPre[],
+
+		/* output */
+		double  *PrefetchBandwidth,
+		double  *FractionOfUrgentBandwidth,
+		bool *PrefetchBandwidthSupport);
+
+double dml32_CalculateBandwidthAvailableForImmediateFlip(unsigned int NumberOfActiveSurfaces,
+		double ReturnBW,
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double PrefetchBandwidthLuma[],
+		double PrefetchBandwidthChroma[],
+		double cursor_bw[],
+		double cursor_bw_pre[],
+		unsigned int NumberOfDPP[],
+		double UrgentBurstFactorLuma[],
+		double UrgentBurstFactorChroma[],
+		double UrgentBurstFactorCursor[],
+		double UrgentBurstFactorLumaPre[],
+		double UrgentBurstFactorChromaPre[],
+		double UrgentBurstFactorCursorPre[]);
+
+void dml32_CalculateImmediateFlipBandwithSupport(unsigned int NumberOfActiveSurfaces,
+		double ReturnBW,
+		enum immediate_flip_requirement ImmediateFlipRequirement[],
+		double final_flip_bw[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double PrefetchBandwidthLuma[],
+		double PrefetchBandwidthChroma[],
+		double cursor_bw[],
+		double meta_row_bandwidth[],
+		double dpte_row_bandwidth[],
+		double cursor_bw_pre[],
+		double prefetch_vmrow_bw[],
+		unsigned int NumberOfDPP[],
+		double UrgentBurstFactorLuma[],
+		double UrgentBurstFactorChroma[],
+		double UrgentBurstFactorCursor[],
+		double UrgentBurstFactorLumaPre[],
+		double UrgentBurstFactorChromaPre[],
+		double UrgentBurstFactorCursorPre[],
+
+		/* output */
+		double  *TotalBandwidth,
+		double  *FractionOfUrgentBandwidth,
+		bool *ImmediateFlipBandwidthSupport);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
new file mode 100644
index 0000000000000..269bdfc4bc40e
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
@@ -0,0 +1,616 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "../display_mode_lib.h"
+#include "../display_mode_vba.h"
+#include "../dml_inline_defs.h"
+#include "display_rq_dlg_calc_32.h"
+
+static bool is_dual_plane(enum source_format_class source_format)
+{
+	bool ret_val = 0;
+
+	if ((source_format == dm_420_12) || (source_format == dm_420_8) || (source_format == dm_420_10)
+		|| (source_format == dm_rgbe_alpha))
+		ret_val = 1;
+
+	return ret_val;
+}
+
+void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs,
+		struct display_mode_lib *mode_lib,
+		const display_e2e_pipe_params_st *e2e_pipe_param,
+		const unsigned int num_pipes,
+		const unsigned int pipe_idx)
+{
+	const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
+	bool dual_plane = is_dual_plane((enum source_format_class) (src->source_format));
+    double stored_swath_l_bytes;
+    double stored_swath_c_bytes;
+    bool is_phantom_pipe;
+	uint32_t pixel_chunk_bytes = 0;
+	uint32_t min_pixel_chunk_bytes = 0;
+	uint32_t meta_chunk_bytes = 0;
+	uint32_t min_meta_chunk_bytes = 0;
+	uint32_t dpte_group_bytes = 0;
+	uint32_t mpte_group_bytes = 0;
+
+	uint32_t p1_pixel_chunk_bytes = 0;
+	uint32_t p1_min_pixel_chunk_bytes = 0;
+	uint32_t p1_meta_chunk_bytes = 0;
+	uint32_t p1_min_meta_chunk_bytes = 0;
+	uint32_t p1_dpte_group_bytes = 0;
+	uint32_t p1_mpte_group_bytes = 0;
+
+    unsigned int detile_buf_size_in_bytes;
+    unsigned int detile_buf_plane1_addr;
+    unsigned int pte_row_height_linear;
+
+	memset(rq_regs, 0, sizeof(*rq_regs));
+
+	dml_print("DML_DLG::%s: Calculation for pipe[%d] start, num_pipes=%d\n", __func__, pipe_idx, num_pipes);
+
+	pixel_chunk_bytes = get_pixel_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024; // From VBA
+	min_pixel_chunk_bytes = get_min_pixel_chunk_size_in_byte(mode_lib, e2e_pipe_param, num_pipes); // From VBA
+
+	if (pixel_chunk_bytes == 64 * 1024)
+		min_pixel_chunk_bytes = 0;
+
+	meta_chunk_bytes = get_meta_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024; // From VBA
+	min_meta_chunk_bytes = get_min_meta_chunk_size_in_byte(mode_lib, e2e_pipe_param, num_pipes); // From VBA
+
+	dpte_group_bytes = get_dpte_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
+	mpte_group_bytes = get_vm_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
+
+	p1_pixel_chunk_bytes = pixel_chunk_bytes;
+	p1_min_pixel_chunk_bytes = min_pixel_chunk_bytes;
+	p1_meta_chunk_bytes = meta_chunk_bytes;
+	p1_min_meta_chunk_bytes = min_meta_chunk_bytes;
+	p1_dpte_group_bytes = dpte_group_bytes;
+	p1_mpte_group_bytes = mpte_group_bytes;
+
+	if ((enum source_format_class) src->source_format == dm_rgbe_alpha)
+		p1_pixel_chunk_bytes = get_alpha_pixel_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024;
+
+	rq_regs->rq_regs_l.chunk_size = dml_log2(pixel_chunk_bytes) - 10;
+	rq_regs->rq_regs_c.chunk_size = dml_log2(p1_pixel_chunk_bytes) - 10;
+
+	if (min_pixel_chunk_bytes == 0)
+		rq_regs->rq_regs_l.min_chunk_size = 0;
+	else
+		rq_regs->rq_regs_l.min_chunk_size = dml_log2(min_pixel_chunk_bytes) - 8 + 1;
+
+	if (p1_min_pixel_chunk_bytes == 0)
+		rq_regs->rq_regs_c.min_chunk_size = 0;
+	else
+		rq_regs->rq_regs_c.min_chunk_size = dml_log2(p1_min_pixel_chunk_bytes) - 8 + 1;
+
+	rq_regs->rq_regs_l.meta_chunk_size = dml_log2(meta_chunk_bytes) - 10;
+	rq_regs->rq_regs_c.meta_chunk_size = dml_log2(p1_meta_chunk_bytes) - 10;
+
+	if (min_meta_chunk_bytes == 0)
+		rq_regs->rq_regs_l.min_meta_chunk_size = 0;
+	else
+		rq_regs->rq_regs_l.min_meta_chunk_size = dml_log2(min_meta_chunk_bytes) - 6 + 1;
+
+	if (min_meta_chunk_bytes == 0)
+		rq_regs->rq_regs_c.min_meta_chunk_size = 0;
+	else
+		rq_regs->rq_regs_c.min_meta_chunk_size = dml_log2(p1_min_meta_chunk_bytes) - 6 + 1;
+
+	rq_regs->rq_regs_l.dpte_group_size = dml_log2(dpte_group_bytes) - 6;
+	rq_regs->rq_regs_l.mpte_group_size = dml_log2(mpte_group_bytes) - 6;
+	rq_regs->rq_regs_c.dpte_group_size = dml_log2(p1_dpte_group_bytes) - 6;
+	rq_regs->rq_regs_c.mpte_group_size = dml_log2(p1_mpte_group_bytes) - 6;
+
+	detile_buf_size_in_bytes = get_det_buffer_size_kbytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * 1024;
+	detile_buf_plane1_addr = 0;
+	pte_row_height_linear = get_dpte_row_height_linear_l(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx);
+
+	if (src->sw_mode == dm_sw_linear)
+		ASSERT(pte_row_height_linear >= 8);
+
+	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(pte_row_height_linear), 1) - 3;
+
+	if (dual_plane) {
+		unsigned int p1_pte_row_height_linear = get_dpte_row_height_linear_c(mode_lib, e2e_pipe_param,
+				num_pipes, pipe_idx);
+		;
+		if (src->sw_mode == dm_sw_linear)
+			ASSERT(p1_pte_row_height_linear >= 8);
+
+		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(p1_pte_row_height_linear), 1) - 3;
+	}
+
+	rq_regs->rq_regs_l.swath_height = dml_log2(get_swath_height_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx));
+	rq_regs->rq_regs_c.swath_height = dml_log2(get_swath_height_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx));
+
+	// FIXME: take the max between luma, chroma chunk size?
+	// okay for now, as we are setting pixel_chunk_bytes to 8kb anyways
+	if (pixel_chunk_bytes >= 32 * 1024 || (dual_plane && p1_pixel_chunk_bytes >= 32 * 1024)) { //32kb
+		rq_regs->drq_expansion_mode = 0;
+	} else {
+		rq_regs->drq_expansion_mode = 2;
+	}
+	rq_regs->prq_expansion_mode = 1;
+	rq_regs->mrq_expansion_mode = 1;
+	rq_regs->crq_expansion_mode = 1;
+
+	stored_swath_l_bytes = get_det_stored_buffer_size_l_bytes(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx);
+	stored_swath_c_bytes = get_det_stored_buffer_size_c_bytes(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx);
+	is_phantom_pipe = get_is_phantom_pipe(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
+
+	// Note: detile_buf_plane1_addr is in unit of 1KB
+	if (dual_plane) {
+		if (is_phantom_pipe) {
+			detile_buf_plane1_addr = ((1024.0 * 1024.0) / 2.0 / 1024.0); // half to chroma
+		} else {
+			if (stored_swath_l_bytes / stored_swath_c_bytes <= 1.5) {
+				detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+				dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d (1/2 to chroma)\n",
+						__func__, detile_buf_plane1_addr);
+#endif
+			} else {
+				detile_buf_plane1_addr =
+						dml_round_to_multiple(
+								(unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0),
+								1024, 0) / 1024.0; // 2/3 to luma
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+				dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d (1/3 chroma)\n",
+						__func__, detile_buf_plane1_addr);
+#endif
+			}
+		}
+	}
+	rq_regs->plane1_base_address = detile_buf_plane1_addr;
+
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+	dml_print("DML_DLG: %s: is_phantom_pipe = %d\n", __func__, is_phantom_pipe);
+	dml_print("DML_DLG: %s: stored_swath_l_bytes = %f\n", __func__, stored_swath_l_bytes);
+	dml_print("DML_DLG: %s: stored_swath_c_bytes = %f\n", __func__, stored_swath_c_bytes);
+	dml_print("DML_DLG: %s: detile_buf_size_in_bytes = %d\n", __func__, detile_buf_size_in_bytes);
+	dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d\n", __func__, detile_buf_plane1_addr);
+	dml_print("DML_DLG: %s: plane1_base_address = %d\n", __func__, rq_regs->plane1_base_address);
+#endif
+	print__rq_regs_st(mode_lib, rq_regs);
+	dml_print("DML_DLG::%s: Calculation for pipe[%d] done, num_pipes=%d\n", __func__, pipe_idx, num_pipes);
+}
+
+void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
+		display_dlg_regs_st *dlg_regs,
+		display_ttu_regs_st *ttu_regs,
+		display_e2e_pipe_params_st *e2e_pipe_param,
+		const unsigned int num_pipes,
+		const unsigned int pipe_idx)
+{
+	const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
+	const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
+	const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
+	double refcyc_per_req_delivery_pre_cur0 = 0.;
+	double refcyc_per_req_delivery_cur0 = 0.;
+	double refcyc_per_req_delivery_pre_c = 0.;
+	double refcyc_per_req_delivery_c = 0.;
+    double refcyc_per_req_delivery_pre_l;
+    double refcyc_per_req_delivery_l;
+	double refcyc_per_line_delivery_pre_c = 0.;
+	double refcyc_per_line_delivery_c = 0.;
+    double refcyc_per_line_delivery_pre_l;
+    double refcyc_per_line_delivery_l;
+    double min_ttu_vblank;
+    double vratio_pre_l;
+    double vratio_pre_c;
+    unsigned int min_dst_y_next_start;
+	unsigned int htotal = dst->htotal;
+	unsigned int hblank_end = dst->hblank_end;
+	unsigned int vblank_end = dst->vblank_end;
+	bool interlaced = dst->interlaced;
+	double pclk_freq_in_mhz = dst->pixel_rate_mhz;
+    unsigned int vready_after_vcount0;
+	double refclk_freq_in_mhz = clks->refclk_mhz;
+	double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
+	bool dual_plane = 0;
+	unsigned int pipe_index_in_combine[DC__NUM_PIPES__MAX];
+    int unsigned dst_x_after_scaler;
+    int unsigned dst_y_after_scaler;
+    double dst_y_prefetch;
+    double dst_y_per_vm_vblank;
+    double dst_y_per_row_vblank;
+    double dst_y_per_vm_flip;
+    double dst_y_per_row_flip;
+    double max_dst_y_per_vm_vblank = 32.0;
+    double max_dst_y_per_row_vblank = 16.0;
+
+    double dst_y_per_pte_row_nom_l;
+    double dst_y_per_pte_row_nom_c;
+    double dst_y_per_meta_row_nom_l;
+    double dst_y_per_meta_row_nom_c;
+    double refcyc_per_pte_group_nom_l;
+    double refcyc_per_pte_group_nom_c;
+    double refcyc_per_pte_group_vblank_l;
+    double refcyc_per_pte_group_vblank_c;
+    double refcyc_per_pte_group_flip_l; 
+    double refcyc_per_pte_group_flip_c; 
+    double refcyc_per_meta_chunk_nom_l;
+    double refcyc_per_meta_chunk_nom_c;
+    double refcyc_per_meta_chunk_vblank_l;
+    double refcyc_per_meta_chunk_vblank_c;
+    double refcyc_per_meta_chunk_flip_l;
+    double refcyc_per_meta_chunk_flip_c;
+
+	memset(dlg_regs, 0, sizeof(*dlg_regs));
+	memset(ttu_regs, 0, sizeof(*ttu_regs));
+	dml_print("DML_DLG::%s: Calculation for pipe[%d] starts, num_pipes=%d\n", __func__, pipe_idx, num_pipes);
+	dml_print("DML_DLG: %s: refclk_freq_in_mhz     = %3.2f\n", __func__, refclk_freq_in_mhz);
+	dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz);
+	dml_print("DML_DLG: %s: ref_freq_to_pix_freq   = %3.2f\n", __func__, ref_freq_to_pix_freq);
+	dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced);
+	ASSERT(ref_freq_to_pix_freq < 4.0);
+
+	dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));
+	dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8));
+	dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
+
+	min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
+	min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
+
+	dml_print("DML_DLG: %s: min_ttu_vblank (us)    = %3.2f\n", __func__, min_ttu_vblank);
+	dml_print("DML_DLG: %s: min_dst_y_next_start = %d\n", __func__, min_dst_y_next_start);
+	dml_print("DML_DLG: %s: ref_freq_to_pix_freq   = %3.2f\n", __func__, ref_freq_to_pix_freq);
+
+	dual_plane = is_dual_plane((enum source_format_class) (src->source_format));
+
+	vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx); // From VBA
+	dlg_regs->vready_after_vcount0 = vready_after_vcount0;
+
+	dml_print("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, dlg_regs->vready_after_vcount0);
+
+	dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
+	dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
+
+	// do some adjustment on the dst_after scaler to account for odm combine mode
+	dml_print("DML_DLG: %s: input dst_x_after_scaler   = %d\n", __func__, dst_x_after_scaler);
+	dml_print("DML_DLG: %s: input dst_y_after_scaler   = %d\n", __func__, dst_y_after_scaler);
+
+	// need to figure out which side of odm combine we're in
+	if (dst->odm_combine == dm_odm_combine_mode_2to1 || dst->odm_combine == dm_odm_combine_mode_4to1) {
+		// figure out which pipes go together
+		bool visited[DC__NUM_PIPES__MAX];
+		unsigned int i, j, k;
+
+		for (k = 0; k < num_pipes; ++k) {
+			visited[k] = false;
+			pipe_index_in_combine[k] = 0;
+		}
+
+		for (i = 0; i < num_pipes; i++) {
+			if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) {
+
+				unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp;
+				unsigned int grp_idx = 0;
+
+				for (j = i; j < num_pipes; j++) {
+					if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp
+						&& e2e_pipe_param[j].pipe.src.is_hsplit && !visited[j]) {
+						pipe_index_in_combine[j] = grp_idx;
+						dml_print("DML_DLG: %s: pipe[%d] is in grp %d idx %d\n",
+								__func__, j, grp, grp_idx);
+						grp_idx++;
+						visited[j] = true;
+					}
+				}
+			}
+		}
+	}
+
+	if (dst->odm_combine == dm_odm_combine_mode_disabled) {
+		// FIXME how about ODM split??
+		dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end * ref_freq_to_pix_freq);
+	} else {
+		if (dst->odm_combine == dm_odm_combine_mode_2to1 || dst->odm_combine == dm_odm_combine_mode_4to1) {
+			// TODO: We should really check that 4to1 is supported before setting it to 4
+			unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4);
+			unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx];
+
+			dlg_regs->refcyc_h_blank_end = (unsigned int) (((double) hblank_end
+				+ odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq);
+		}
+	}
+	ASSERT(dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));
+
+	dml_print("DML_DLG: %s: htotal= %d\n", __func__, htotal);
+	dml_print("DML_DLG: %s: dst_x_after_scaler[%d]= %d\n", __func__, pipe_idx, dst_x_after_scaler);
+	dml_print("DML_DLG: %s: dst_y_after_scaler[%d] = %d\n", __func__, pipe_idx, dst_y_after_scaler);
+
+	dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);        // From VBA
+	// From VBA
+	dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
+	// From VBA
+	dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
+	dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);    // From VBA
+	dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);  // From VBA
+
+	// magic!
+	if (htotal <= 75) {
+		max_dst_y_per_vm_vblank = 100.0;
+		max_dst_y_per_row_vblank = 100.0;
+	}
+
+	dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch);
+	dml_print("DML_DLG: %s: dst_y_per_vm_flip    = %3.2f\n", __func__, dst_y_per_vm_flip);
+	dml_print("DML_DLG: %s: dst_y_per_row_flip   = %3.2f\n", __func__, dst_y_per_row_flip);
+	dml_print("DML_DLG: %s: dst_y_per_vm_vblank  = %3.2f\n", __func__, dst_y_per_vm_vblank);
+	dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank);
+
+	ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank);
+	ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank);
+	ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
+
+	vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);    // From VBA
+	vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);    // From VBA
+
+	dml_print("DML_DLG: %s: vratio_pre_l = %3.2f\n", __func__, vratio_pre_l);
+	dml_print("DML_DLG: %s: vratio_pre_c = %3.2f\n", __func__, vratio_pre_c);
+
+	// Active
+	refcyc_per_line_delivery_pre_l = get_refcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;   // From VBA
+	refcyc_per_line_delivery_l = get_refcyc_per_line_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz;       // From VBA
+
+	dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", __func__, refcyc_per_line_delivery_pre_l);
+	dml_print("DML_DLG: %s: refcyc_per_line_delivery_l     = %3.2f\n", __func__, refcyc_per_line_delivery_l);
+
+	if (dual_plane) {
+		refcyc_per_line_delivery_pre_c = get_refcyc_per_line_delivery_pre_c_in_us(mode_lib, e2e_pipe_param,
+				num_pipes, pipe_idx) * refclk_freq_in_mhz;     // From VBA
+		refcyc_per_line_delivery_c = get_refcyc_per_line_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes,
+				pipe_idx) * refclk_freq_in_mhz; // From VBA
+
+		dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n",
+				__func__, refcyc_per_line_delivery_pre_c);
+		dml_print("DML_DLG: %s: refcyc_per_line_delivery_c     = %3.2f\n",
+				__func__, refcyc_per_line_delivery_c);
+	}
+
+	if (src->dynamic_metadata_enable && src->gpuvm)
+		dlg_regs->refcyc_per_vm_dmdata = get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes,
+				pipe_idx) * refclk_freq_in_mhz; // From VBA
+
+	dlg_regs->dmdata_dl_delta = get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)
+		* refclk_freq_in_mhz; // From VBA
+
+	refcyc_per_req_delivery_pre_l = get_refcyc_per_req_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
+	refcyc_per_req_delivery_l = get_refcyc_per_req_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz;     // From VBA
+
+	dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, refcyc_per_req_delivery_pre_l);
+	dml_print("DML_DLG: %s: refcyc_per_req_delivery_l     = %3.2f\n", __func__, refcyc_per_req_delivery_l);
+
+	if (dual_plane) {
+		refcyc_per_req_delivery_pre_c = get_refcyc_per_req_delivery_pre_c_in_us(mode_lib, e2e_pipe_param,
+				num_pipes, pipe_idx) * refclk_freq_in_mhz;  // From VBA
+		refcyc_per_req_delivery_c = get_refcyc_per_req_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes,
+				pipe_idx) * refclk_freq_in_mhz;      // From VBA
+
+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n",
+				__func__, refcyc_per_req_delivery_pre_c);
+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_c     = %3.2f\n", __func__, refcyc_per_req_delivery_c);
+	}
+
+	// TTU - Cursor
+	ASSERT(src->num_cursors <= 1);
+	if (src->num_cursors > 0) {
+		refcyc_per_req_delivery_pre_cur0 = get_refcyc_per_cursor_req_delivery_pre_in_us(mode_lib,
+				e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;  // From VBA
+		refcyc_per_req_delivery_cur0 = get_refcyc_per_cursor_req_delivery_in_us(mode_lib, e2e_pipe_param,
+				num_pipes, pipe_idx) * refclk_freq_in_mhz;      // From VBA
+
+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur0 = %3.2f\n",
+				__func__, refcyc_per_req_delivery_pre_cur0);
+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur0     = %3.2f\n",
+				__func__, refcyc_per_req_delivery_cur0);
+	}
+
+	// Assign to register structures
+	dlg_regs->min_dst_y_next_start = min_dst_y_next_start * dml_pow(2, 2);
+	ASSERT(dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
+
+	dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line
+	dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk
+	dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));
+	dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));
+	dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));
+	dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));
+	dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));
+
+	dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));
+	dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));
+
+	dml_print("DML_DLG: %s: dlg_regs->dst_y_per_vm_vblank  = 0x%x\n", __func__, dlg_regs->dst_y_per_vm_vblank);
+	dml_print("DML_DLG: %s: dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, dlg_regs->dst_y_per_row_vblank);
+	dml_print("DML_DLG: %s: dlg_regs->dst_y_per_vm_flip    = 0x%x\n", __func__, dlg_regs->dst_y_per_vm_flip);
+	dml_print("DML_DLG: %s: dlg_regs->dst_y_per_row_flip   = 0x%x\n", __func__, dlg_regs->dst_y_per_row_flip);
+
+	dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param,
+			num_pipes, pipe_idx) * refclk_freq_in_mhz;               // From VBA
+	dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz;                 // From VBA
+	dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10);                 // From VBA
+	dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10);  // From VBA
+
+	// From VBA
+	dst_y_per_pte_row_nom_l = get_dst_y_per_pte_row_nom_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
+	// From VBA
+	dst_y_per_pte_row_nom_c = get_dst_y_per_pte_row_nom_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
+	// From VBA
+	dst_y_per_meta_row_nom_l = get_dst_y_per_meta_row_nom_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
+	// From VBA
+	dst_y_per_meta_row_nom_c = get_dst_y_per_meta_row_nom_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
+
+	refcyc_per_pte_group_nom_l = get_refcyc_per_pte_group_nom_l_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz;         // From VBA
+	refcyc_per_pte_group_nom_c = get_refcyc_per_pte_group_nom_c_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz;         // From VBA
+	refcyc_per_pte_group_vblank_l = get_refcyc_per_pte_group_vblank_l_in_us(mode_lib, e2e_pipe_param,
+			num_pipes, pipe_idx) * refclk_freq_in_mhz;      // From VBA
+	refcyc_per_pte_group_vblank_c = get_refcyc_per_pte_group_vblank_c_in_us(mode_lib, e2e_pipe_param,
+			num_pipes, pipe_idx) * refclk_freq_in_mhz;      // From VBA
+	refcyc_per_pte_group_flip_l = get_refcyc_per_pte_group_flip_l_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz;        // From VBA
+	refcyc_per_pte_group_flip_c = get_refcyc_per_pte_group_flip_c_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz;        // From VBA
+
+	refcyc_per_meta_chunk_nom_l = get_refcyc_per_meta_chunk_nom_l_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz;        // From VBA
+	refcyc_per_meta_chunk_nom_c = get_refcyc_per_meta_chunk_nom_c_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz;        // From VBA
+	refcyc_per_meta_chunk_vblank_l = get_refcyc_per_meta_chunk_vblank_l_in_us(mode_lib, e2e_pipe_param,
+			num_pipes, pipe_idx) * refclk_freq_in_mhz;     // From VBA
+	refcyc_per_meta_chunk_vblank_c = get_refcyc_per_meta_chunk_vblank_c_in_us(mode_lib, e2e_pipe_param,
+			num_pipes, pipe_idx) * refclk_freq_in_mhz;     // From VBA
+	refcyc_per_meta_chunk_flip_l = get_refcyc_per_meta_chunk_flip_l_in_us(mode_lib, e2e_pipe_param,
+			num_pipes, pipe_idx) * refclk_freq_in_mhz;       // From VBA
+	refcyc_per_meta_chunk_flip_c = get_refcyc_per_meta_chunk_flip_c_in_us(mode_lib, e2e_pipe_param,
+			num_pipes, pipe_idx) * refclk_freq_in_mhz;       // From VBA
+
+	dlg_regs->dst_y_per_pte_row_nom_l = dst_y_per_pte_row_nom_l * dml_pow(2, 2);
+	dlg_regs->dst_y_per_pte_row_nom_c = dst_y_per_pte_row_nom_c * dml_pow(2, 2);
+	dlg_regs->dst_y_per_meta_row_nom_l = dst_y_per_meta_row_nom_l * dml_pow(2, 2);
+	dlg_regs->dst_y_per_meta_row_nom_c = dst_y_per_meta_row_nom_c * dml_pow(2, 2);
+	dlg_regs->refcyc_per_pte_group_nom_l = refcyc_per_pte_group_nom_l;
+	dlg_regs->refcyc_per_pte_group_nom_c = refcyc_per_pte_group_nom_c;
+	dlg_regs->refcyc_per_pte_group_vblank_l = refcyc_per_pte_group_vblank_l;
+	dlg_regs->refcyc_per_pte_group_vblank_c = refcyc_per_pte_group_vblank_c;
+	dlg_regs->refcyc_per_pte_group_flip_l = refcyc_per_pte_group_flip_l;
+	dlg_regs->refcyc_per_pte_group_flip_c = refcyc_per_pte_group_flip_c;
+	dlg_regs->refcyc_per_meta_chunk_nom_l = refcyc_per_meta_chunk_nom_l;
+	dlg_regs->refcyc_per_meta_chunk_nom_c = refcyc_per_meta_chunk_nom_c;
+	dlg_regs->refcyc_per_meta_chunk_vblank_l = refcyc_per_meta_chunk_vblank_l;
+	dlg_regs->refcyc_per_meta_chunk_vblank_c = refcyc_per_meta_chunk_vblank_c;
+	dlg_regs->refcyc_per_meta_chunk_flip_l = refcyc_per_meta_chunk_flip_l;
+	dlg_regs->refcyc_per_meta_chunk_flip_c = refcyc_per_meta_chunk_flip_c;
+	dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1);
+	dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, 1);
+	dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, 1);
+	dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c, 1);
+
+	dlg_regs->chunk_hdl_adjust_cur0 = 3;
+	dlg_regs->dst_y_offset_cur0 = 0;
+	dlg_regs->chunk_hdl_adjust_cur1 = 3;
+	dlg_regs->dst_y_offset_cur1 = 0;
+
+	dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
+
+	ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l * dml_pow(2, 10));
+	ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l * dml_pow(2, 10));
+	ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10));
+	ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c * dml_pow(2, 10));
+	ttu_regs->refcyc_per_req_delivery_pre_cur0 =
+			(unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));
+	ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10));
+	ttu_regs->refcyc_per_req_delivery_pre_cur1 = 0;
+	ttu_regs->refcyc_per_req_delivery_cur1 = 0;
+	ttu_regs->qos_level_low_wm = 0;
+
+	ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal * ref_freq_to_pix_freq);
+
+	ttu_regs->qos_level_flip = 14;
+	ttu_regs->qos_level_fixed_l = 8;
+	ttu_regs->qos_level_fixed_c = 8;
+	ttu_regs->qos_level_fixed_cur0 = 8;
+	ttu_regs->qos_ramp_disable_l = 0;
+	ttu_regs->qos_ramp_disable_c = 0;
+	ttu_regs->qos_ramp_disable_cur0 = 0;
+	ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
+
+	// CHECK for HW registers' range, assert or clamp
+	ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));
+	ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
+	ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));
+	ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
+	if (dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23))
+		dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1;
+
+	if (dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23))
+		dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1;
+
+	if (dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23))
+		dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1;
+
+	if (dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23))
+		dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1;
+
+	ASSERT(dlg_regs->dst_y_after_scaler < (unsigned int) 8);
+	ASSERT(dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));
+	ASSERT(dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));
+	if (dual_plane) {
+		if (dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {
+			// FIXME what so special about chroma, can we just assert?
+			dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u > register max U15.2 %u\n",
+					__func__, dlg_regs->dst_y_per_pte_row_nom_c, (unsigned int)dml_pow(2, 17) - 1);
+		}
+	}
+	ASSERT(dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));
+	ASSERT(dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17));
+
+	if (dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))
+		dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;
+	if (dual_plane) {
+		if (dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))
+			dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;
+	}
+	ASSERT(dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));
+	if (dual_plane) {
+		ASSERT(dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13));
+	}
+
+	if (dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))
+		dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;
+	if (dual_plane) {
+		if (dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))
+			dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;
+	}
+	ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));
+	ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_c < (unsigned int)dml_pow(2, 13));
+	ASSERT(dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13));
+	ASSERT(dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));
+	ASSERT(dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13));
+	ASSERT(dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));
+	ASSERT(ttu_regs->qos_level_low_wm < dml_pow(2, 14));
+	ASSERT(ttu_regs->qos_level_high_wm < dml_pow(2, 14));
+	ASSERT(ttu_regs->min_ttu_vblank < dml_pow(2, 24));
+
+	print__ttu_regs_st(mode_lib, ttu_regs);
+	print__dlg_regs_st(mode_lib, dlg_regs);
+	dml_print("DML_DLG::%s: Calculation for pipe[%d] done, num_pipes=%d\n", __func__, pipe_idx, num_pipes);
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.h
new file mode 100644
index 0000000000000..ebee365293cd8
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DML32_DISPLAY_RQ_DLG_CALC_H__
+#define __DML32_DISPLAY_RQ_DLG_CALC_H__
+
+#include "../display_rq_dlg_helpers.h"
+
+struct display_mode_lib;
+
+/*
+* Function: dml_rq_dlg_get_rq_reg
+*  Main entry point for test to get the register values out of this DML class.
+*  This function calls <get_rq_param> and <extract_rq_regs> functions to calculate
+*  and then populate the rq_regs struct
+* Input:
+*  pipe_param - pipe source configuration (e.g. vp, pitch, scaling, dest, etc.)
+* Output:
+*  rq_regs - struct that holds all the RQ registers field value.
+*            See also: <display_rq_regs_st>
+*/
+void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs,
+		struct display_mode_lib *mode_lib,
+		const display_e2e_pipe_params_st *e2e_pipe_param,
+		const unsigned int num_pipes,
+		const unsigned int pipe_idx);
+
+/*
+* Function: dml_rq_dlg_get_dlg_reg
+*   Calculate and return DLG and TTU register struct given the system setting
+* Output:
+*  dlg_regs - output DLG register struct
+*  ttu_regs - output DLG TTU register struct
+* Input:
+*  e2e_pipe_param - "compacted" array of e2e pipe param struct
+*  num_pipes - num of active "pipe" or "route"
+*  pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
+*  cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
+*           Added for legacy or unrealistic timing tests.
+*/
+void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
+		display_dlg_regs_st *dlg_regs,
+		display_ttu_regs_st *ttu_regs,
+		display_e2e_pipe_params_st *e2e_pipe_param,
+		const unsigned int num_pipes,
+		const unsigned int pipe_idx);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
index edb9f7567d6d9..f394b3f3922a8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
@@ -26,7 +26,11 @@
 #define __DISPLAY_MODE_ENUMS_H__
 
 enum output_encoder_class {
-	dm_dp = 0, dm_hdmi = 1, dm_wb = 2, dm_edp
+	dm_dp = 0,
+	dm_hdmi = 1,
+	dm_wb = 2,
+	dm_edp = 3,
+	dm_dp2p0 = 5,
 };
 enum output_format_class {
 	dm_444 = 0, dm_420 = 1, dm_n422, dm_s422
@@ -105,6 +109,10 @@ enum clock_change_support {
 	dm_dram_clock_change_uninitialized = 0,
 	dm_dram_clock_change_vactive,
 	dm_dram_clock_change_vblank,
+	dm_dram_clock_change_vactive_w_mall_full_frame,
+	dm_dram_clock_change_vactive_w_mall_sub_vp,
+	dm_dram_clock_change_vblank_w_mall_full_frame,
+	dm_dram_clock_change_vblank_w_mall_sub_vp,
 	dm_dram_clock_change_unsupported
 };
 
@@ -169,6 +177,9 @@ enum odm_combine_mode {
 	dm_odm_combine_mode_disabled,
 	dm_odm_combine_mode_2to1,
 	dm_odm_combine_mode_4to1,
+	dm_odm_split_mode_1to2,
+	dm_odm_mode_mso_1to2,
+	dm_odm_mode_mso_1to4
 };
 
 enum odm_combine_policy {
@@ -176,11 +187,15 @@ enum odm_combine_policy {
 	dm_odm_combine_policy_none,
 	dm_odm_combine_policy_2to1,
 	dm_odm_combine_policy_4to1,
+	dm_odm_split_policy_1to2,
+	dm_odm_mso_policy_1to2,
+	dm_odm_mso_policy_1to4,
 };
 
 enum immediate_flip_requirement {
 	dm_immediate_flip_not_required,
 	dm_immediate_flip_required,
+	dm_immediate_flip_opportunistic,
 };
 
 enum unbounded_requesting_policy {
@@ -189,4 +204,75 @@ enum unbounded_requesting_policy {
 	dm_unbounded_requesting_disable
 };
 
+enum dm_rotation_angle {
+	dm_rotation_0,
+	dm_rotation_90,
+	dm_rotation_180,
+	dm_rotation_270,
+	dm_rotation_0m,
+	dm_rotation_90m,
+	dm_rotation_180m,
+	dm_rotation_270m,
+};
+
+enum dm_use_mall_for_pstate_change_mode {
+	dm_use_mall_pstate_change_disable,
+	dm_use_mall_pstate_change_full_frame,
+	dm_use_mall_pstate_change_sub_viewport,
+	dm_use_mall_pstate_change_phantom_pipe
+};
+
+enum dm_use_mall_for_static_screen_mode {
+	dm_use_mall_static_screen_disable,
+	dm_use_mall_static_screen_optimize,
+	dm_use_mall_static_screen_enable,
+};
+
+enum dm_output_link_dp_rate {
+	dm_dp_rate_na,
+	dm_dp_rate_hbr,
+	dm_dp_rate_hbr2,
+	dm_dp_rate_hbr3,
+	dm_dp_rate_uhbr10,
+	dm_dp_rate_uhbr13p5,
+	dm_dp_rate_uhbr20,
+};
+
+enum dm_fclock_change_support {
+	dm_fclock_change_vactive,
+	dm_fclock_change_vblank,
+	dm_fclock_change_unsupported,
+};
+
+enum dm_prefetch_modes {
+	dm_prefetch_support_uclk_fclk_and_stutter_if_possible,
+	dm_prefetch_support_uclk_fclk_and_stutter,
+	dm_prefetch_support_fclk_and_stutter,
+	dm_prefetch_support_stutter,
+	dm_prefetch_support_none,
+};
+enum dm_output_type {
+	dm_output_type_unknown,
+	dm_output_type_dp,
+	dm_output_type_edp,
+	dm_output_type_dp2p0,
+	dm_output_type_hdmi,
+	dm_output_type_hdmifrl,
+};
+
+enum dm_output_rate {
+	dm_output_rate_unknown,
+	dm_output_rate_dp_rate_hbr,
+	dm_output_rate_dp_rate_hbr2,
+	dm_output_rate_dp_rate_hbr3,
+	dm_output_rate_dp_rate_uhbr10,
+	dm_output_rate_dp_rate_uhbr13p5,
+	dm_output_rate_dp_rate_uhbr20,
+	dm_output_rate_hdmi_rate_3x3,
+	dm_output_rate_hdmi_rate_6x3,
+	dm_output_rate_hdmi_rate_6x4,
+	dm_output_rate_hdmi_rate_8x4,
+	dm_output_rate_hdmi_rate_10x4,
+	dm_output_rate_hdmi_rate_12x4,
+};
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
index 30db51fbd8cdf..5d27ff0ebb5fa 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
@@ -35,6 +35,8 @@
 #include "dcn30/display_rq_dlg_calc_30.h"
 #include "dcn31/display_mode_vba_31.h"
 #include "dcn31/display_rq_dlg_calc_31.h"
+#include "dcn32/display_mode_vba_32.h"
+#include "dcn32/display_rq_dlg_calc_32.h"
 #include "dml_logger.h"
 
 const struct dml_funcs dml20_funcs = {
@@ -72,6 +74,13 @@ const struct dml_funcs dml31_funcs = {
 	.rq_dlg_get_rq_reg = dml31_rq_dlg_get_rq_reg
 };
 
+const struct dml_funcs dml32_funcs = {
+	.validate = dml32_ModeSupportAndSystemConfigurationFull,
+    .recalculate = dml32_recalculate,
+	.rq_dlg_get_dlg_reg_v2 = dml32_rq_dlg_get_dlg_reg,
+	.rq_dlg_get_rq_reg_v2 = dml32_rq_dlg_get_rq_reg
+};
+
 void dml_init_instance(struct display_mode_lib *lib,
 		const struct _vcs_dpi_soc_bounding_box_st *soc_bb,
 		const struct _vcs_dpi_ip_params_st *ip_params,
@@ -98,6 +107,9 @@ void dml_init_instance(struct display_mode_lib *lib,
 	case DML_PROJECT_DCN31_FPGA:
 		lib->funcs = dml31_funcs;
 		break;
+	case DML_PROJECT_DCN32:
+		lib->funcs = dml32_funcs;
+		break;
 
 	default:
 		break;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
index d76251fd15669..2bdd6ed22611d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
@@ -41,6 +41,7 @@ enum dml_project {
 	DML_PROJECT_DCN30,
 	DML_PROJECT_DCN31,
 	DML_PROJECT_DCN31_FPGA,
+	DML_PROJECT_DCN32,
 };
 
 struct display_mode_lib;
@@ -62,6 +63,20 @@ struct dml_funcs {
 		struct display_mode_lib *mode_lib,
 		display_rq_regs_st *rq_regs,
 		const display_pipe_params_st *pipe_param);
+	// DLG interfaces have different function parameters in DCN32.
+	// Create new function pointers to address the changes
+	void (*rq_dlg_get_dlg_reg_v2)(
+			struct display_mode_lib *mode_lib,
+			display_dlg_regs_st *dlg_regs,
+			display_ttu_regs_st *ttu_regs,
+			display_e2e_pipe_params_st *e2e_pipe_param,
+			const unsigned int num_pipes,
+			const unsigned int pipe_idx);
+	void (*rq_dlg_get_rq_reg_v2)(display_rq_regs_st *rq_regs,
+			struct display_mode_lib *mode_lib,
+			const display_e2e_pipe_params_st *e2e_pipe_param,
+			const unsigned int num_pipes,
+			const unsigned int pipe_idx);
 	void (*recalculate)(struct display_mode_lib *mode_lib);
 	void (*validate)(struct display_mode_lib *mode_lib);
 };
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 2df660cd8801b..967d3e1ce8869 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -54,12 +54,102 @@ typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st;
 typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st;
 typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st;
 
+typedef struct {
+	double UrgentWatermark;
+	double WritebackUrgentWatermark;
+	double DRAMClockChangeWatermark;
+	double FCLKChangeWatermark;
+	double WritebackDRAMClockChangeWatermark;
+	double WritebackFCLKChangeWatermark;
+	double StutterExitWatermark;
+	double StutterEnterPlusExitWatermark;
+	double Z8StutterExitWatermark;
+	double Z8StutterEnterPlusExitWatermark;
+	double USRRetrainingWatermark;
+} Watermarks;
+
+typedef struct {
+	double UrgentLatency;
+	double ExtraLatency;
+	double WritebackLatency;
+	double DRAMClockChangeLatency;
+	double FCLKChangeLatency;
+	double SRExitTime;
+	double SREnterPlusExitTime;
+	double SRExitZ8Time;
+	double SREnterPlusExitZ8Time;
+	double USRRetrainingLatencyPlusSMNLatency;
+} Latencies;
+
+typedef struct {
+	double Dppclk;
+	double Dispclk;
+	double PixelClock;
+	double DCFClkDeepSleep;
+	unsigned int DPPPerSurface;
+	bool ScalerEnabled;
+	enum dm_rotation_angle SourceRotation;
+	unsigned int ViewportHeight;
+	unsigned int ViewportHeightChroma;
+	unsigned int BlockWidth256BytesY;
+	unsigned int BlockHeight256BytesY;
+	unsigned int BlockWidth256BytesC;
+	unsigned int BlockHeight256BytesC;
+	unsigned int BlockWidthY;
+	unsigned int BlockHeightY;
+	unsigned int BlockWidthC;
+	unsigned int BlockHeightC;
+	unsigned int InterlaceEnable;
+	unsigned int NumberOfCursors;
+	unsigned int VBlank;
+	unsigned int HTotal;
+	unsigned int HActive;
+	bool DCCEnable;
+	enum odm_combine_mode ODMMode;
+	enum source_format_class SourcePixelFormat;
+	enum dm_swizzle_mode SurfaceTiling;
+	unsigned int BytePerPixelY;
+	unsigned int BytePerPixelC;
+	bool ProgressiveToInterlaceUnitInOPP;
+	double VRatio;
+	double VRatioChroma;
+	unsigned int VTaps;
+	unsigned int VTapsChroma;
+	unsigned int PitchY;
+	unsigned int DCCMetaPitchY;
+	unsigned int PitchC;
+	unsigned int DCCMetaPitchC;
+	bool ViewportStationary;
+	unsigned int ViewportXStart;
+	unsigned int ViewportYStart;
+	unsigned int ViewportXStartC;
+	unsigned int ViewportYStartC;
+	bool FORCE_ONE_ROW_FOR_FRAME;
+	unsigned int SwathHeightY;
+	unsigned int SwathHeightC;
+} DmlPipe;
+
+typedef struct {
+	double UrgentLatency;
+	double ExtraLatency;
+	double WritebackLatency;
+	double DRAMClockChangeLatency;
+	double FCLKChangeLatency;
+	double SRExitTime;
+	double SREnterPlusExitTime;
+	double SRExitZ8Time;
+	double SREnterPlusExitZ8Time;
+	double USRRetrainingLatency;
+	double SMNLatency;
+} SOCParametersList;
+
 struct _vcs_dpi_voltage_scaling_st {
 	int state;
 	double dscclk_mhz;
 	double dcfclk_mhz;
 	double socclk_mhz;
 	double phyclk_d18_mhz;
+	double phyclk_d32_mhz;
 	double dram_speed_mts;
 	double fabricclk_mhz;
 	double dispclk_mhz;
@@ -80,6 +170,15 @@ struct _vcs_dpi_soc_bounding_box_st {
 	double urgent_latency_pixel_data_only_us;
 	double urgent_latency_pixel_mixed_with_vm_data_us;
 	double urgent_latency_vm_data_only_us;
+	double usr_retraining_latency_us;
+	double smn_latency_us;
+	double fclk_change_latency_us;
+	double mall_allocated_for_dcn_mbytes;
+	double pct_ideal_fabric_bw_after_urgent;
+	double pct_ideal_dram_bw_after_urgent_strobe;
+	double max_avg_fabric_bw_use_normal_percent;
+	double max_avg_dram_bw_use_normal_strobe_percent;
+	enum dm_prefetch_modes allow_for_pstate_or_stutter_in_vblank_final;
 	double writeback_latency_us;
 	double ideal_dram_bw_after_urgent_percent;
 	double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
@@ -148,6 +247,9 @@ struct _vcs_dpi_ip_params_st {
 	unsigned int dpp_output_buffer_pixels;
 	unsigned int opp_output_buffer_lines;
 	unsigned int pixel_chunk_size_kbytes;
+	unsigned int alpha_pixel_chunk_size_kbytes;
+	unsigned int min_pixel_chunk_size_bytes;
+	unsigned int dcc_meta_buffer_size_bytes;
 	unsigned char pte_enable;
 	unsigned int pte_chunk_size_kbytes;
 	unsigned int meta_chunk_size_kbytes;
@@ -168,6 +270,7 @@ struct _vcs_dpi_ip_params_st {
 	double writeback_min_hscl_ratio;
 	double writeback_min_vscl_ratio;
 	unsigned int maximum_dsc_bits_per_component;
+	unsigned int maximum_pixels_per_line_per_dsc_unit;
 	unsigned int writeback_max_hscl_taps;
 	unsigned int writeback_max_vscl_taps;
 	unsigned int writeback_line_buffer_luma_buffer_size;
@@ -224,6 +327,8 @@ struct _vcs_dpi_ip_params_st {
 	unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
 	unsigned int bug_forcing_LC_req_same_size_fixed;
 	unsigned int number_of_cursors;
+	unsigned int max_num_dp2p0_outputs;
+	unsigned int max_num_dp2p0_streams;
 };
 
 struct _vcs_dpi_display_xfc_params_st {
@@ -250,6 +355,7 @@ struct _vcs_dpi_display_pipe_source_params_st {
 	bool hostvm_levels_force_en;
 	unsigned int hostvm_levels_force;
 	int source_scan;
+	int source_rotation; // new in dml32
 	int sw_mode;
 	int macro_tile_size;
 	unsigned int surface_width_y;
@@ -264,6 +370,15 @@ struct _vcs_dpi_display_pipe_source_params_st {
 	unsigned int viewport_height_c;
 	unsigned int viewport_width_max;
 	unsigned int viewport_height_max;
+	unsigned int viewport_x_y;
+	unsigned int viewport_x_c;
+	bool viewport_stationary;
+	unsigned int dcc_rate_luma;
+	unsigned int gpuvm_min_page_size_kbytes;
+	unsigned int use_mall_for_pstate_change;
+	unsigned int use_mall_for_static_screen;
+	bool force_one_row_for_frame;
+	bool pte_buffer_mode;
 	unsigned int data_pitch;
 	unsigned int data_pitch_c;
 	unsigned int meta_pitch;
@@ -296,10 +411,17 @@ struct writeback_st {
 	int wb_vtaps_luma;
 	int wb_htaps_chroma;
 	int wb_vtaps_chroma;
+	unsigned int wb_htaps;
+	unsigned int wb_vtaps;
 	double wb_hratio;
 	double wb_vratio;
 };
 
+struct display_audio_params_st {
+	unsigned int   audio_sample_rate_khz;
+	int    		   audio_sample_layout;
+};
+
 struct _vcs_dpi_display_output_params_st {
 	int dp_lanes;
 	double output_bpp;
@@ -313,6 +435,11 @@ struct _vcs_dpi_display_output_params_st {
 	int dsc_slices;
 	int max_audio_sample_rate;
 	struct writeback_st wb;
+	struct display_audio_params_st audio;
+	unsigned int output_bpc;
+	int dp_rate;
+	unsigned int dp_multistream_id;
+	bool dp_multistream_en;
 };
 
 struct _vcs_dpi_scaler_ratio_depth_st {
@@ -361,6 +488,8 @@ struct _vcs_dpi_display_pipe_dest_params_st {
 	unsigned char use_maximum_vstartup;
 	unsigned int vtotal_max;
 	unsigned int vtotal_min;
+	unsigned int refresh_rate;
+	bool synchronize_timings;
 };
 
 struct _vcs_dpi_display_pipe_params_st {
@@ -558,6 +687,9 @@ struct _vcs_dpi_display_arb_params_st {
 	int max_req_outstanding;
 	int min_req_outstanding;
 	int sat_level_us;
+	int hvm_min_req_outstand_commit_threshold;
+	int hvm_max_qos_commit_threshold;
+	int compbuf_reserved_space_kbytes;
 };
 
 #endif /*__DISPLAY_MODE_STRUCTS_H__*/
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index c0740dbdcc2e6..2676710a5f2b6 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -110,6 +110,15 @@ dml_get_attr_func(return_bw, mode_lib->vba.ReturnBW);
 dml_get_attr_func(tcalc, mode_lib->vba.TCalc);
 dml_get_attr_func(fraction_of_urgent_bandwidth, mode_lib->vba.FractionOfUrgentBandwidth);
 dml_get_attr_func(fraction_of_urgent_bandwidth_imm_flip, mode_lib->vba.FractionOfUrgentBandwidthImmediateFlip);
+dml_get_attr_func(cstate_max_cap_mode, mode_lib->vba.DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE);
+dml_get_attr_func(comp_buffer_size_kbytes, mode_lib->vba.CompressedBufferSizeInkByte);
+dml_get_attr_func(pixel_chunk_size_in_kbyte, mode_lib->vba.PixelChunkSizeInKByte);
+dml_get_attr_func(alpha_pixel_chunk_size_in_kbyte, mode_lib->vba.AlphaPixelChunkSizeInKByte);
+dml_get_attr_func(meta_chunk_size_in_kbyte, mode_lib->vba.MetaChunkSize);
+dml_get_attr_func(min_pixel_chunk_size_in_byte, mode_lib->vba.MinPixelChunkSizeBytes);
+dml_get_attr_func(min_meta_chunk_size_in_byte, mode_lib->vba.MinMetaChunkSizeBytes);
+dml_get_attr_func(fclk_watermark, mode_lib->vba.Watermark.FCLKChangeWatermark);
+dml_get_attr_func(usr_retraining_watermark, mode_lib->vba.Watermark.USRRetrainingWatermark);
 
 #define dml_get_pipe_attr_func(attr, var)  double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe) \
 {\
@@ -165,6 +174,27 @@ dml_get_pipe_attr_func(vupdate_width, mode_lib->vba.VUpdateWidthPix);
 dml_get_pipe_attr_func(vready_offset, mode_lib->vba.VReadyOffsetPix);
 dml_get_pipe_attr_func(vready_at_or_after_vsync, mode_lib->vba.VREADY_AT_OR_AFTER_VSYNC);
 dml_get_pipe_attr_func(min_dst_y_next_start, mode_lib->vba.MIN_DST_Y_NEXT_START);
+dml_get_pipe_attr_func(dst_y_per_pte_row_nom_l, mode_lib->vba.DST_Y_PER_PTE_ROW_NOM_L);
+dml_get_pipe_attr_func(dst_y_per_pte_row_nom_c, mode_lib->vba.DST_Y_PER_PTE_ROW_NOM_C);
+dml_get_pipe_attr_func(dst_y_per_meta_row_nom_l, mode_lib->vba.DST_Y_PER_META_ROW_NOM_L);
+dml_get_pipe_attr_func(dst_y_per_meta_row_nom_c, mode_lib->vba.DST_Y_PER_META_ROW_NOM_C);
+dml_get_pipe_attr_func(refcyc_per_pte_group_nom_l_in_us, mode_lib->vba.time_per_pte_group_nom_luma);
+dml_get_pipe_attr_func(refcyc_per_pte_group_nom_c_in_us, mode_lib->vba.time_per_pte_group_nom_chroma);
+dml_get_pipe_attr_func(refcyc_per_pte_group_vblank_l_in_us, mode_lib->vba.time_per_pte_group_vblank_luma);
+dml_get_pipe_attr_func(refcyc_per_pte_group_vblank_c_in_us, mode_lib->vba.time_per_pte_group_vblank_chroma);
+dml_get_pipe_attr_func(refcyc_per_pte_group_flip_l_in_us, mode_lib->vba.time_per_pte_group_flip_luma);
+dml_get_pipe_attr_func(refcyc_per_pte_group_flip_c_in_us, mode_lib->vba.time_per_pte_group_flip_chroma);
+dml_get_pipe_attr_func(vstartup_calculated, mode_lib->vba.VStartup);
+dml_get_pipe_attr_func(dpte_row_height_linear_c, mode_lib->vba.dpte_row_height_linear_chroma);
+dml_get_pipe_attr_func(swath_height_l, mode_lib->vba.SwathHeightY);
+dml_get_pipe_attr_func(swath_height_c, mode_lib->vba.SwathHeightC);
+dml_get_pipe_attr_func(det_stored_buffer_size_l_bytes, mode_lib->vba.DETBufferSizeY);
+dml_get_pipe_attr_func(det_stored_buffer_size_c_bytes, mode_lib->vba.DETBufferSizeC);
+dml_get_pipe_attr_func(dpte_group_size_in_bytes, mode_lib->vba.dpte_group_bytes);
+dml_get_pipe_attr_func(vm_group_size_in_bytes, mode_lib->vba.vm_group_bytes);
+dml_get_pipe_attr_func(dpte_row_height_linear_l, mode_lib->vba.dpte_row_height_linear);
+dml_get_pipe_attr_func(pte_buffer_mode, mode_lib->vba.PTE_BUFFER_MODE);
+dml_get_pipe_attr_func(subviewport_lines_needed_in_mall, mode_lib->vba.SubViewportLinesNeededInMALL);
 
 double get_total_immediate_flip_bytes(
 		struct display_mode_lib *mode_lib,
@@ -202,6 +232,67 @@ double get_total_prefetch_bw(
 	return total_prefetch_bw;
 }
 
+unsigned int get_total_surface_size_in_mall_bytes(
+		struct display_mode_lib *mode_lib,
+		const display_e2e_pipe_params_st *pipes,
+		unsigned int num_pipes)
+{
+	unsigned int k;
+	unsigned int size = 0.0;
+	recalculate_params(mode_lib, pipes, num_pipes);
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
+		size += mode_lib->vba.SurfaceSizeInMALL[k];
+	return size;
+}
+
+unsigned int get_pipe_idx(struct display_mode_lib *mode_lib, unsigned int plane_idx)
+{
+	int pipe_idx = -1;
+	int i;
+
+	ASSERT(plane_idx < DC__NUM_DPP__MAX);
+
+	for (i = 0; i < DC__NUM_DPP__MAX ; i++) {
+		if (plane_idx == mode_lib->vba.pipe_plane[i]) {
+			pipe_idx = i;
+			break;
+		}
+	}
+	ASSERT(pipe_idx >= 0);
+
+	return pipe_idx;
+}
+
+
+double get_det_buffer_size_kbytes(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes,
+		unsigned int num_pipes, unsigned int pipe_idx)
+{
+	unsigned int plane_idx;
+	double det_buf_size_kbytes;
+
+	recalculate_params(mode_lib, pipes, num_pipes);
+	plane_idx = mode_lib->vba.pipe_plane[pipe_idx];
+
+	dml_print("DML::%s: num_pipes=%d pipe_idx=%d plane_idx=%0d\n", __func__, num_pipes, pipe_idx, plane_idx);
+	det_buf_size_kbytes = mode_lib->vba.DETBufferSizeInKByte[plane_idx]; // per hubp DET buffer size
+
+	dml_print("DML::%s: det_buf_size_kbytes=%3.2f\n", __func__, det_buf_size_kbytes);
+
+	return det_buf_size_kbytes;
+}
+
+bool get_is_phantom_pipe(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes,
+		unsigned int num_pipes, unsigned int pipe_idx)
+{
+	unsigned int plane_idx;
+
+	recalculate_params(mode_lib, pipes, num_pipes);
+	plane_idx = mode_lib->vba.pipe_plane[pipe_idx];
+	dml_print("DML::%s: num_pipes=%d pipe_idx=%d UseMALLForPStateChange=%0d\n", __func__, num_pipes, pipe_idx,
+			mode_lib->vba.UsesMALLForPStateChange[plane_idx]);
+	return (mode_lib->vba.UsesMALLForPStateChange[plane_idx] == dm_use_mall_pstate_change_phantom_pipe);
+}
+
 static void fetch_socbb_params(struct display_mode_lib *mode_lib)
 {
 	soc_bounding_box_st *soc = &mode_lib->vba.soc;
@@ -241,6 +332,22 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
 			soc->max_avg_sdp_bw_use_normal_percent;
 	mode_lib->vba.SRExitZ8Time = soc->sr_exit_z8_time_us;
 	mode_lib->vba.SREnterPlusExitZ8Time = soc->sr_enter_plus_exit_z8_time_us;
+	mode_lib->vba.FCLKChangeLatency = soc->fclk_change_latency_us;
+	mode_lib->vba.USRRetrainingLatency = soc->usr_retraining_latency_us;
+	mode_lib->vba.SMNLatency = soc->smn_latency_us;
+	mode_lib->vba.MALLAllocatedForDCNFinal = soc->mall_allocated_for_dcn_mbytes;
+
+	mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE = soc->pct_ideal_dram_bw_after_urgent_strobe;
+	mode_lib->vba.MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation =
+			soc->max_avg_fabric_bw_use_normal_percent;
+	mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE =
+			soc->max_avg_dram_bw_use_normal_strobe_percent;
+
+	mode_lib->vba.DRAMClockChangeRequirementFinal = 1;
+	mode_lib->vba.FCLKChangeRequirementFinal = 1;
+	mode_lib->vba.USRRetrainingRequiredFinal = 1;
+	mode_lib->vba.ConfigurableDETSizeEnFinal = 0;
+	mode_lib->vba.AllowForPStateChangeOrStutterInVBlankFinal = soc->allow_for_pstate_or_stutter_in_vblank_final;
 	mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us;
 	mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us;
 	mode_lib->vba.DRAMClockChangeSupportsVActive = !soc->disable_dram_clock_change_vactive_support ||
@@ -283,6 +390,7 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
 		mode_lib->vba.SOCCLKPerState[i] = soc->clock_limits[i].socclk_mhz;
 		mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz;
 		mode_lib->vba.PHYCLKD18PerState[i] = soc->clock_limits[i].phyclk_d18_mhz;
+		mode_lib->vba.PHYCLKD32PerState[i] = soc->clock_limits[i].phyclk_d32_mhz;
 		mode_lib->vba.MaxDppclk[i] = soc->clock_limits[i].dppclk_mhz;
 		mode_lib->vba.MaxDSCCLK[i] = soc->clock_limits[i].dscclk_mhz;
 		mode_lib->vba.DRAMSpeedPerState[i] = soc->clock_limits[i].dram_speed_mts;
@@ -325,6 +433,18 @@ static void fetch_ip_params(struct display_mode_lib *mode_lib)
 	mode_lib->vba.COMPBUF_RESERVED_SPACE_ZS = ip->compbuf_reserved_space_zs;
 	mode_lib->vba.MaximumDSCBitsPerComponent = ip->maximum_dsc_bits_per_component;
 	mode_lib->vba.DSC422NativeSupport = ip->dsc422_native_support;
+    /* In DCN3.2, nomDETInKByte should be initialized correctly. */
+	mode_lib->vba.nomDETInKByte = ip->det_buffer_size_kbytes;
+	mode_lib->vba.CompbufReservedSpace64B  = ip->compbuf_reserved_space_64b;
+	mode_lib->vba.CompbufReservedSpaceZs = ip->compbuf_reserved_space_zs;
+	mode_lib->vba.CompressedBufferSegmentSizeInkByteFinal = ip->compressed_buffer_segment_size_in_kbytes;
+	mode_lib->vba.LineBufferSizeFinal = ip->line_buffer_size_bits;
+	mode_lib->vba.AlphaPixelChunkSizeInKByte = ip->alpha_pixel_chunk_size_kbytes; // not ysed
+	mode_lib->vba.MinPixelChunkSizeBytes = ip->min_pixel_chunk_size_bytes; // not used
+	mode_lib->vba.MaximumPixelsPerLinePerDSCUnit = ip->maximum_pixels_per_line_per_dsc_unit;
+	mode_lib->vba.MaxNumDP2p0Outputs = ip->max_num_dp2p0_outputs;
+	mode_lib->vba.MaxNumDP2p0Streams = ip->max_num_dp2p0_streams;
+	mode_lib->vba.DCCMetaBufferSizeBytes = ip->dcc_meta_buffer_size_bytes;
 
 	mode_lib->vba.PixelChunkSizeInKByte = ip->pixel_chunk_size_kbytes;
 	mode_lib->vba.MetaChunkSize = ip->meta_chunk_size_kbytes;
@@ -399,6 +519,7 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
 		visited[k] = false;
 
 	mode_lib->vba.NumberOfActivePlanes = 0;
+	mode_lib->vba.NumberOfActiveSurfaces = 0;
 	mode_lib->vba.ImmediateFlipSupport = false;
 	for (j = 0; j < mode_lib->vba.cache_num_pipes; ++j) {
 		display_pipe_source_params_st *src = &pipes[j].pipe.src;
@@ -429,6 +550,21 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
 				src->viewport_y_y;
 		mode_lib->vba.ViewportYStartC[mode_lib->vba.NumberOfActivePlanes] =
 				src->viewport_y_c;
+		mode_lib->vba.SourceRotation[mode_lib->vba.NumberOfActiveSurfaces] = src->source_rotation;
+		mode_lib->vba.ViewportXStartY[mode_lib->vba.NumberOfActiveSurfaces] = src->viewport_x_y;
+		mode_lib->vba.ViewportXStartC[mode_lib->vba.NumberOfActiveSurfaces] = src->viewport_x_c;
+		// TODO: Assign correct value to viewport_stationary
+		mode_lib->vba.ViewportStationary[mode_lib->vba.NumberOfActivePlanes] =
+				src->viewport_stationary;
+		mode_lib->vba.UsesMALLForPStateChange[mode_lib->vba.NumberOfActivePlanes] = src->use_mall_for_pstate_change;
+		mode_lib->vba.UseMALLForStaticScreen[mode_lib->vba.NumberOfActivePlanes] = src->use_mall_for_static_screen;
+		mode_lib->vba.GPUVMMinPageSizeKBytes[mode_lib->vba.NumberOfActivePlanes] = src->gpuvm_min_page_size_kbytes;
+		mode_lib->vba.RefreshRate[mode_lib->vba.NumberOfActivePlanes] = dst->refresh_rate; //todo remove this
+		mode_lib->vba.OutputLinkDPRate[mode_lib->vba.NumberOfActivePlanes] = dout->dp_rate;
+		mode_lib->vba.ODMUse[mode_lib->vba.NumberOfActivePlanes] = dst->odm_combine;
+		//TODO: Need to assign correct values to dp_multistream vars
+		mode_lib->vba.OutputMultistreamEn[mode_lib->vba.NumberOfActiveSurfaces] = dout->dp_multistream_en;
+		mode_lib->vba.OutputMultistreamId[mode_lib->vba.NumberOfActiveSurfaces] = dout->dp_multistream_id;
 		mode_lib->vba.PitchY[mode_lib->vba.NumberOfActivePlanes] = src->data_pitch;
 		mode_lib->vba.SurfaceWidthY[mode_lib->vba.NumberOfActivePlanes] = src->surface_width_y;
 		mode_lib->vba.SurfaceHeightY[mode_lib->vba.NumberOfActivePlanes] = src->surface_height_y;
@@ -677,6 +813,7 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
 		}
 
 		mode_lib->vba.NumberOfActivePlanes++;
+		mode_lib->vba.NumberOfActiveSurfaces++;
 	}
 
 	// handle overlays through BlendingAndTiming
@@ -702,6 +839,8 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
 		}
 	}
 
+	mode_lib->vba.SynchronizeTimingsFinal = pipes[0].pipe.dest.synchronize_timings;
+	mode_lib->vba.DCCProgrammingAssumesScanDirectionUnknownFinal = false;
 	mode_lib->vba.UseUnboundedRequesting = dm_unbounded_requesting;
 	for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) {
 		if (pipes[k].pipe.src.unbounded_req_mode == 0)
@@ -745,6 +884,32 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
 
 	mode_lib->vba.GPUVMEnable = mode_lib->vba.GPUVMEnable && !!ip->gpuvm_enable;
 	mode_lib->vba.HostVMEnable = mode_lib->vba.HostVMEnable && !!ip->hostvm_enable;
+
+	for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) {
+		mode_lib->vba.ForceOneRowForFrame[k] = pipes[k].pipe.src.force_one_row_for_frame;
+		mode_lib->vba.PteBufferMode[k] = pipes[k].pipe.src.pte_buffer_mode;
+
+		if (mode_lib->vba.PteBufferMode[k] == 0 && mode_lib->vba.GPUVMEnable) {
+			if (mode_lib->vba.ForceOneRowForFrame[k] ||
+				(mode_lib->vba.GPUVMMinPageSizeKBytes[k] > 64*1024) ||
+				(mode_lib->vba.UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_disable) ||
+				(mode_lib->vba.UseMALLForStaticScreen[k] != dm_use_mall_static_screen_disable)) {
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: ERROR: Invalid PteBufferMode=%d for plane %0d!\n",
+						__func__, mode_lib->vba.PteBufferMode[k], k);
+				dml_print("DML::%s:  -  ForceOneRowForFrame     = %d\n",
+						__func__, mode_lib->vba.ForceOneRowForFrame[k]);
+				dml_print("DML::%s:  -  GPUVMMinPageSizeKBytes  = %d\n",
+						__func__, mode_lib->vba.GPUVMMinPageSizeKBytes[k]);
+				dml_print("DML::%s:  -  UseMALLForPStateChange  = %d\n",
+						__func__, (int) mode_lib->vba.UsesMALLForPStateChange[k]);
+				dml_print("DML::%s:  -  UseMALLForStaticScreen  = %d\n",
+						__func__, (int) mode_lib->vba.UseMALLForStaticScreen[k]);
+#endif
+				ASSERT(0);
+			}
+		}
+	}
 }
 
 /**
@@ -896,6 +1061,7 @@ void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib)
 	soc_bounding_box_st *soc = &mode_lib->vba.soc;
 	unsigned int k;
 	unsigned int total_pipes = 0;
+	unsigned int pipe_idx = 0;
 
 	mode_lib->vba.VoltageLevel = mode_lib->vba.cache_pipes[0].clks_cfg.voltage;
 	mode_lib->vba.ReturnBW = mode_lib->vba.ReturnBWPerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb];
@@ -917,6 +1083,11 @@ void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib)
 	// Total Available Pipes Support Check
 	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
 		total_pipes += mode_lib->vba.DPPPerPlane[k];
+		pipe_idx = get_pipe_idx(mode_lib, k);
+		if (mode_lib->vba.cache_pipes[pipe_idx].clks_cfg.dppclk_mhz > 0.0)
+			mode_lib->vba.DPPCLK[k] = mode_lib->vba.cache_pipes[pipe_idx].clks_cfg.dppclk_mhz;
+		else
+			mode_lib->vba.DPPCLK[k] = soc->clock_limits[mode_lib->vba.VoltageLevel].dppclk_mhz;
 	}
 	ASSERT(total_pipes <= DC__NUM_DPP__MAX);
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 0603b32971a6f..ddf8b19c490e9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -58,6 +58,15 @@ dml_get_attr_decl(return_bw);
 dml_get_attr_decl(tcalc);
 dml_get_attr_decl(fraction_of_urgent_bandwidth);
 dml_get_attr_decl(fraction_of_urgent_bandwidth_imm_flip);
+dml_get_attr_decl(cstate_max_cap_mode);
+dml_get_attr_decl(comp_buffer_size_kbytes);
+dml_get_attr_decl(pixel_chunk_size_in_kbyte);
+dml_get_attr_decl(alpha_pixel_chunk_size_in_kbyte);
+dml_get_attr_decl(meta_chunk_size_in_kbyte);
+dml_get_attr_decl(min_pixel_chunk_size_in_byte);
+dml_get_attr_decl(min_meta_chunk_size_in_byte);
+dml_get_attr_decl(fclk_watermark);
+dml_get_attr_decl(usr_retraining_watermark);
 
 #define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe)
 
@@ -75,6 +84,26 @@ dml_get_pipe_attr_decl(dst_y_per_row_vblank);
 dml_get_pipe_attr_decl(dst_y_prefetch);
 dml_get_pipe_attr_decl(dst_y_per_vm_flip);
 dml_get_pipe_attr_decl(dst_y_per_row_flip);
+dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_l);
+dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_c);
+dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_l);
+dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_c);
+dml_get_pipe_attr_decl(dpte_row_height_linear_c);
+dml_get_pipe_attr_decl(swath_height_l);
+dml_get_pipe_attr_decl(swath_height_c);
+dml_get_pipe_attr_decl(det_stored_buffer_size_l_bytes);
+dml_get_pipe_attr_decl(det_stored_buffer_size_c_bytes);
+dml_get_pipe_attr_decl(dpte_group_size_in_bytes);
+dml_get_pipe_attr_decl(vm_group_size_in_bytes);
+dml_get_pipe_attr_decl(det_buffer_size_kbytes);
+dml_get_pipe_attr_decl(dpte_row_height_linear_l);
+dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_l_in_us);
+dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_c_in_us);
+dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_l_in_us);
+dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_c_in_us);
+dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_l_in_us);
+dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_c_in_us);
+dml_get_pipe_attr_decl(pte_buffer_mode);
 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank);
 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip);
 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank);
@@ -108,6 +137,8 @@ dml_get_pipe_attr_decl(vupdate_width);
 dml_get_pipe_attr_decl(vready_offset);
 dml_get_pipe_attr_decl(vready_at_or_after_vsync);
 dml_get_pipe_attr_decl(min_dst_y_next_start);
+dml_get_pipe_attr_decl(vstartup_calculated);
+dml_get_pipe_attr_decl(subviewport_lines_needed_in_mall);
 
 double get_total_immediate_flip_bytes(
 		struct display_mode_lib *mode_lib,
@@ -126,6 +157,16 @@ unsigned int dml_get_voltage_level(
 		const display_e2e_pipe_params_st *pipes,
 		unsigned int num_pipes);
 
+unsigned int get_total_surface_size_in_mall_bytes(
+		struct display_mode_lib *mode_lib,
+		const display_e2e_pipe_params_st *pipes,
+		unsigned int num_pipes);
+unsigned int get_pipe_idx(struct display_mode_lib *mode_lib, unsigned int plane_idx);
+
+bool get_is_phantom_pipe(struct display_mode_lib *mode_lib,
+		const display_e2e_pipe_params_st *pipes,
+		unsigned int num_pipes,
+		unsigned int pipe_idx);
 void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib);
 
 bool Calculate256BBlockSizes(
@@ -138,6 +179,39 @@ bool Calculate256BBlockSizes(
 		unsigned int *BlockWidth256BytesY,
 		unsigned int *BlockWidth256BytesC);
 
+struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation {
+	unsigned int dummy_integer_array[2][DC__NUM_DPP__MAX];
+	double dummy_single_array[2][DC__NUM_DPP__MAX];
+	unsigned int dummy_long_array[2][DC__NUM_DPP__MAX];
+	double dummy_double_array[2][DC__NUM_DPP__MAX];
+	bool dummy_boolean_array[DC__NUM_DPP__MAX];
+	bool dummy_boolean;
+	bool dummy_boolean2;
+	enum output_encoder_class dummy_output_encoder_array[DC__NUM_DPP__MAX];
+	DmlPipe SurfaceParameters[DC__NUM_DPP__MAX];
+	bool dummy_boolean_array2[2][DC__NUM_DPP__MAX];
+	unsigned int ReorderBytes;
+	unsigned int VMDataOnlyReturnBW;
+	double HostVMInefficiencyFactor;
+};
+
+struct dml32_ModeSupportAndSystemConfigurationFull {
+	unsigned int dummy_integer_array[8][DC__NUM_DPP__MAX];
+	double dummy_double_array[2][DC__NUM_DPP__MAX];
+	DmlPipe SurfParameters[DC__NUM_DPP__MAX];
+	double dummy_single[5];
+	double dummy_single2[5];
+	SOCParametersList mSOCParameters;
+	unsigned int MaximumSwathWidthSupportLuma;
+	unsigned int MaximumSwathWidthSupportChroma;
+};
+
+struct dummy_vars {
+	struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+	DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation;
+	struct dml32_ModeSupportAndSystemConfigurationFull dml32_ModeSupportAndSystemConfigurationFull;
+};
+
 struct vba_vars_st {
 	ip_params_st ip;
 	soc_bounding_box_st soc;
@@ -154,6 +228,7 @@ struct vba_vars_st {
 	double DISPCLKWithRampingRoundedToDFSGranularity;
 	double DISPCLKWithoutRampingRoundedToDFSGranularity;
 	double MaxDispclkRoundedToDFSGranularity;
+	double MaxDppclkRoundedToDFSGranularity;
 	bool DCCEnabledAnyPlane;
 	double ReturnBandwidthToDCN;
 	unsigned int TotalActiveDPP;
@@ -169,6 +244,8 @@ struct vba_vars_st {
 	double NextMaxVStartup;
 	double VBlankTime;
 	double SmallestVBlank;
+	enum dm_prefetch_modes AllowForPStateChangeOrStutterInVBlankFinal; // Mode Support only
+	double DCFCLKDeepSleepPerSurface[DC__NUM_DPP__MAX];
 	double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX];
 	double EffectiveDETPlusLBLinesLuma;
 	double EffectiveDETPlusLBLinesChroma;
@@ -212,6 +289,14 @@ struct vba_vars_st {
 	double UrgentLatencyPixelMixedWithVMData;
 	double UrgentLatencyVMDataOnly;
 	double UrgentLatency; // max of the above three
+	double USRRetrainingLatency;
+	double SMNLatency;
+	double FCLKChangeLatency;
+	unsigned int MALLAllocatedForDCNFinal;
+	double DefaultGPUVMMinPageSizeKBytes; // Default for the project
+	double MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation;
+	double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE;
+	double PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE;
 	double WritebackLatency;
 	double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly; // Mode Support
 	double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData; // Mode Support
@@ -284,6 +369,14 @@ struct vba_vars_st {
 	double DPPCLKDelayCNVCCursor;
 	double DISPCLKDelaySubtotal;
 	bool ProgressiveToInterlaceUnitInOPP;
+	unsigned int CompressedBufferSegmentSizeInkByteFinal;
+	unsigned int CompbufReservedSpace64B;
+	unsigned int CompbufReservedSpaceZs;
+	unsigned int LineBufferSizeFinal;
+	unsigned int MaximumPixelsPerLinePerDSCUnit;
+	unsigned int AlphaPixelChunkSizeInKByte;
+	double MinPixelChunkSizeBytes;
+	unsigned int DCCMetaBufferSizeBytes;
 	// Pipe/Plane Parameters
 	int VoltageLevel;
 	double FabricClock;
@@ -291,6 +384,23 @@ struct vba_vars_st {
 	double DISPCLK;
 	double SOCCLK;
 	double DCFCLK;
+	unsigned int MaxTotalDETInKByte;
+	unsigned int MinCompressedBufferSizeInKByte;
+	unsigned int NumberOfActiveSurfaces;
+	bool ViewportStationary[DC__NUM_DPP__MAX];
+	unsigned int RefreshRate[DC__NUM_DPP__MAX];
+	double       OutputBPP[DC__NUM_DPP__MAX];
+	unsigned int GPUVMMinPageSizeKBytes[DC__NUM_DPP__MAX];
+	bool SynchronizeTimingsFinal;
+	bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal;
+	bool ForceOneRowForFrame[DC__NUM_DPP__MAX];
+	unsigned int ViewportXStartY[DC__NUM_DPP__MAX];
+	unsigned int ViewportXStartC[DC__NUM_DPP__MAX];
+	enum dm_rotation_angle SourceRotation[DC__NUM_DPP__MAX];
+	bool DRRDisplay[DC__NUM_DPP__MAX];
+	bool PteBufferMode[DC__NUM_DPP__MAX];
+	enum dm_output_type OutputType[DC__NUM_DPP__MAX];
+	enum dm_output_rate OutputRate[DC__NUM_DPP__MAX];
 
 	unsigned int NumberOfActivePlanes;
 	unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX];
@@ -392,6 +502,12 @@ struct vba_vars_st {
 	double StutterEfficiencyNotIncludingVBlank;
 	double NonUrgentLatencyTolerance;
 	double MinActiveDRAMClockChangeLatencySupported;
+	double Z8StutterEfficiencyBestCase;
+	unsigned int Z8NumberOfStutterBurstsPerFrameBestCase;
+	double Z8StutterEfficiencyNotIncludingVBlankBestCase;
+	double StutterPeriodBestCase;
+	Watermarks      Watermark;
+	bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
 
 	// These are the clocks calcuated by the library but they are not actually
 	// used explicitly. They are fetched by tests and then possibly used. The
@@ -399,6 +515,10 @@ struct vba_vars_st {
 	double DISPCLK_calculated;
 	double DPPCLK_calculated[DC__NUM_DPP__MAX];
 
+	bool ImmediateFlipSupportedSurface[DC__NUM_DPP__MAX];
+
+	bool Use_One_Row_For_Frame[DC__NUM_DPP__MAX];
+	bool Use_One_Row_For_Frame_Flip[DC__NUM_DPP__MAX];
 	unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX];
 	double VUpdateWidthPix[DC__NUM_DPP__MAX];
 	double VReadyOffsetPix[DC__NUM_DPP__MAX];
@@ -429,6 +549,7 @@ struct vba_vars_st {
 	double DRAMSpeedPerState[DC__VOLTAGE_STATES];
 	double MaxDispclk[DC__VOLTAGE_STATES];
 	int VoltageOverrideLevel;
+	double PHYCLKD32PerState[DC__VOLTAGE_STATES];
 
 	/*outputs*/
 	bool ScaleRatioAndTapsSupport;
@@ -452,6 +573,51 @@ struct vba_vars_st {
 	bool PitchSupport;
 	enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES];
 
+	/* Mode Support Reason */
+	bool P2IWith420;
+	bool DSCOnlyIfNecessaryWithBPP;
+	bool DSC422NativeNotSupported;
+	bool LinkRateDoesNotMatchDPVersion;
+	bool LinkRateForMultistreamNotIndicated;
+	bool BPPForMultistreamNotIndicated;
+	bool MultistreamWithHDMIOreDP;
+	bool MSOOrODMSplitWithNonDPLink;
+	bool NotEnoughLanesForMSO;
+	bool ViewportExceedsSurface;
+
+	bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified;
+	bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;
+	bool InvalidCombinationOfMALLUseForPStateAndStaticScreen;
+	bool InvalidCombinationOfMALLUseForPState;
+
+	enum dm_output_link_dp_rate OutputLinkDPRate[DC__NUM_DPP__MAX];
+	double PrefetchLinesYThisState[DC__NUM_DPP__MAX];
+	double PrefetchLinesCThisState[DC__NUM_DPP__MAX];
+	double meta_row_bandwidth_this_state[DC__NUM_DPP__MAX];
+	double dpte_row_bandwidth_this_state[DC__NUM_DPP__MAX];
+	double DPTEBytesPerRowThisState[DC__NUM_DPP__MAX];
+	double PDEAndMetaPTEBytesPerFrameThisState[DC__NUM_DPP__MAX];
+	double MetaRowBytesThisState[DC__NUM_DPP__MAX];
+	bool use_one_row_for_frame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
+	bool use_one_row_for_frame_flip[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
+	bool use_one_row_for_frame_this_state[DC__NUM_DPP__MAX];
+	bool use_one_row_for_frame_flip_this_state[DC__NUM_DPP__MAX];
+
+	unsigned int OutputTypeAndRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
+	double RequiredDISPCLKPerSurface[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
+	unsigned int MicroTileHeightY[DC__NUM_DPP__MAX];
+	unsigned int MicroTileHeightC[DC__NUM_DPP__MAX];
+	unsigned int MicroTileWidthY[DC__NUM_DPP__MAX];
+	unsigned int MicroTileWidthC[DC__NUM_DPP__MAX];
+	bool ImmediateFlipRequiredFinal;
+	bool DCCProgrammingAssumesScanDirectionUnknownFinal;
+	bool EnoughWritebackUnits;
+	bool ODMCombine2To1SupportCheckOK[DC__VOLTAGE_STATES];
+	bool NumberOfDP2p0Support;
+	unsigned int MaxNumDP2p0Streams;
+	unsigned int MaxNumDP2p0Outputs;
+	enum dm_output_type OutputTypePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
+	enum dm_output_rate OutputRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 	double WritebackLineBufferLumaBufferSize;
 	double WritebackLineBufferChromaBufferSize;
 	double WritebackMinHSCLRatio;
@@ -647,6 +813,7 @@ struct vba_vars_st {
 	double         dummy7[DC__NUM_DPP__MAX];
 	double         dummy8[DC__NUM_DPP__MAX];
 	double         dummy13[DC__NUM_DPP__MAX];
+	double         dummy_double_array[2][DC__NUM_DPP__MAX];
 	unsigned int        dummyinteger1ms[DC__NUM_DPP__MAX];
 	double        dummyinteger2ms[DC__NUM_DPP__MAX];
 	unsigned int        dummyinteger3[DC__NUM_DPP__MAX];
@@ -666,6 +833,9 @@ struct vba_vars_st {
 	unsigned int        dummyintegerarr2[DC__NUM_DPP__MAX];
 	unsigned int        dummyintegerarr3[DC__NUM_DPP__MAX];
 	unsigned int        dummyintegerarr4[DC__NUM_DPP__MAX];
+	unsigned int        dummy_integer_array[8][DC__NUM_DPP__MAX];
+	unsigned int        dummy_integer_array22[22][DC__NUM_DPP__MAX];
+
 	bool           dummysinglestring;
 	bool           SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
 	double         PlaneRequiredDISPCLKWithODMCombine2To1;
@@ -896,8 +1066,8 @@ struct vba_vars_st {
 	double meta_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 	double DETBufferSizeYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 	double DETBufferSizeCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
-	int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
-	int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
+	unsigned int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
+	unsigned int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 	bool NotUrgentLatencyHiding[DC__VOLTAGE_STATES][2];
 	unsigned int SwathHeightYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 	unsigned int SwathHeightCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
@@ -972,6 +1142,74 @@ struct vba_vars_st {
 	int Z8NumberOfStutterBurstsPerFrame;
 	unsigned int MaximumDSCBitsPerComponent;
 	unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2];
+	double UrgentLatencyWithUSRRetraining;
+	double UrgLatencyWithUSRRetraining[DC__VOLTAGE_STATES];
+	double ReadBandwidthSurfaceLuma[DC__NUM_DPP__MAX];
+	double ReadBandwidthSurfaceChroma[DC__NUM_DPP__MAX];
+	double SurfaceRequiredDISPCLKWithoutODMCombine;
+	double SurfaceRequiredDISPCLK;
+	double SurfaceRequiredDISPCLKWithODMCombine2To1;
+	double SurfaceRequiredDISPCLKWithODMCombine4To1;
+	double MinActiveFCLKChangeLatencySupported;
+	double dummy14;
+	double dummy15;
+	int MinVoltageLevel;
+	int MaxVoltageLevel;
+	unsigned int TotalNumberOfSingleDPPSurfaces[DC__VOLTAGE_STATES][2];
+	unsigned int CompressedBufferSizeInkByteAllStates[DC__VOLTAGE_STATES][2];
+	unsigned int DETBufferSizeInKByteAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
+	unsigned int DETBufferSizeInKByteThisState[DC__NUM_DPP__MAX];
+	unsigned int SurfaceSizeInMALL[DC__NUM_DPP__MAX];
+	bool ExceededMALLSize;
+	bool PTE_BUFFER_MODE[DC__NUM_DPP__MAX];
+	unsigned int BIGK_FRAGMENT_SIZE[DC__NUM_DPP__MAX];
+	unsigned int dummyinteger33;
+	unsigned int CompressedBufferSizeInkByteThisState;
+	enum dm_fclock_change_support FCLKChangeSupport[DC__VOLTAGE_STATES][2];
+	Latencies myLatency;
+	Latencies mLatency;
+	Watermarks DummyWatermark;
+	bool USRRetrainingSupport[DC__VOLTAGE_STATES][2];
+	bool dummyBooleanvector1[DC__NUM_DPP__MAX];
+	bool dummyBooleanvector2[DC__NUM_DPP__MAX];
+	enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[DC__NUM_DPP__MAX];
+	bool NotEnoughUrgentLatencyHiding_dml32[DC__VOLTAGE_STATES][2];
+	bool UnboundedRequestEnabledAllStates[DC__VOLTAGE_STATES][2];
+	bool SingleDPPViewportSizeSupportPerSurface[DC__NUM_DPP__MAX];
+	enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[DC__NUM_DPP__MAX];
+	bool UnboundedRequestEnabledThisState;
+	bool DRAMClockChangeRequirementFinal;
+	bool FCLKChangeRequirementFinal;
+	bool USRRetrainingRequiredFinal;
+	bool MALLUseFinal;
+	bool ConfigurableDETSizeEnFinal;
+	bool dummyboolean;
+	unsigned int DETSizeOverride[DC__NUM_DPP__MAX];
+	unsigned int nomDETInKByte;
+	enum mpc_combine_affinity  MPCCombineUse[DC__NUM_DPP__MAX];
+	bool MPCCombineMethodIncompatible;
+	unsigned int RequiredSlots[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
+	bool ExceededMultistreamSlots[DC__VOLTAGE_STATES];
+	enum odm_combine_policy ODMUse[DC__NUM_DPP__MAX];
+	unsigned int OutputMultistreamId[DC__NUM_DPP__MAX];
+	bool OutputMultistreamEn[DC__NUM_DPP__MAX];
+	bool UsesMALLForStaticScreen[DC__NUM_DPP__MAX];
+	double MaxActiveDRAMClockChangeLatencySupported[DC__NUM_DPP__MAX];
+	double WritebackAllowFCLKChangeEndPosition[DC__NUM_DPP__MAX];
+	bool PTEBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
+	bool DCCMetaBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
+	bool NotEnoughDSCSlices[DC__VOLTAGE_STATES];
+	bool PixelsPerLinePerDSCUnitSupport[DC__VOLTAGE_STATES];
+	bool DCCMetaBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
+	unsigned int dpte_row_height_linear[DC__NUM_DPP__MAX];
+	unsigned int dpte_row_height_linear_chroma[DC__NUM_DPP__MAX];
+	unsigned int BlockHeightY[DC__NUM_DPP__MAX];
+	unsigned int BlockHeightC[DC__NUM_DPP__MAX];
+	unsigned int BlockWidthY[DC__NUM_DPP__MAX];
+	unsigned int BlockWidthC[DC__NUM_DPP__MAX];
+	unsigned int SubViewportLinesNeededInMALL[DC__NUM_DPP__MAX];
+	bool VActiveBandwithSupport[DC__VOLTAGE_STATES][2];
+	struct dummy_vars dummy_vars;
 };
 
 bool CalculateMinAndMaxPrefetchMode(
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
index d2273674e8729..b4b51e51fc25c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
@@ -23,7 +23,6 @@
  *
  */
 
-#include "dml_wrapper.h"
 #include "resource.h"
 #include "core_types.h"
 #include "dsc.h"
@@ -86,25 +85,6 @@ static void get_pixel_clock_parameters(
 
 }
 
-static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
-{
-	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
-
-	if (pipe_ctx->clock_source)
-		pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
-			pipe_ctx->clock_source,
-			&pipe_ctx->stream_res.pix_clk_params,
-			&pipe_ctx->pll_settings);
-
-	pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
-
-	resource_build_bit_depth_reduction_params(pipe_ctx->stream,
-					&pipe_ctx->stream->bit_depth_params);
-	build_clamping_params(pipe_ctx->stream);
-
-	return DC_OK;
-}
-
 static void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
 		struct bit_depth_reduction_params *fmt_bit_depth)
 {
@@ -231,6 +211,30 @@ static void resource_build_bit_depth_reduction_params(struct dc_stream_state *st
 	fmt_bit_depth->pixel_encoding = pixel_encoding;
 }
 
+/* Move this after the above function as VS complains about
+ * declaration issues for resource_build_bit_depth_reduction_params.
+ */
+
+static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
+{
+
+	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
+
+	if (pipe_ctx->clock_source)
+		pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
+			pipe_ctx->clock_source,
+			&pipe_ctx->stream_res.pix_clk_params,
+			&pipe_ctx->pll_settings);
+
+	pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
+
+	resource_build_bit_depth_reduction_params(pipe_ctx->stream,
+		&pipe_ctx->stream->bit_depth_params);
+	build_clamping_params(pipe_ctx->stream);
+
+	return DC_OK;
+}
+
 bool dml_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
 {
 	int i;
@@ -1130,7 +1134,7 @@ static int dml_populate_dml_pipes_from_context(
 {
 	int i, pipe_cnt;
 	struct resource_context *res_ctx = &context->res_ctx;
-	struct pipe_ctx *pipe;
+	struct pipe_ctx *pipe = NULL;	// Fix potentially uninitialized error from VS
 
 	populate_dml_pipes_from_context_base(dc, context, pipes, fast_validate);
 
@@ -1296,6 +1300,7 @@ static void dml_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
 		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
 		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
 		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
+		context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;
 	}
 }
 
@@ -1593,11 +1598,8 @@ static void dml_calculate_dlg_params(
 		context->bw_ctx.bw.dcn.clk.z9_support = DCN_Z9_SUPPORT_ALLOW;
 	*/
 	context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
-	/* TODO : Uncomment the below line and make changes
-	 * as per DML nomenclature once it is available.
-	 * context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = context->bw_ctx.dml.vba.fclk_pstate_support;
-	 */
-
+	context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support =
+		context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
 	if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
 		context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
 
@@ -1699,12 +1701,11 @@ static void dml_calculate_wm_and_dlg(
 	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 	context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-	//context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_wm_fclk_pstate(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 	//context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_wm_usr_retraining(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 
 	/* Temporary, to have some fclk_pstate_change_ns and usr_retraining_ns wm values until DML is implemented */
-	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns / 4;
-	context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns / 8;
+	//context->bw_ctx.bw.dcn.watermarks.b.usr_retraining = context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns / 8;
 
 	/* Set D:
 	 * All clocks min.
@@ -1736,13 +1737,11 @@ static void dml_calculate_wm_and_dlg(
 	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 	context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-	//context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_wm_fclk_pstate(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 	//context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_wm_usr_retraining(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 
 	/* Temporary, to have some fclk_pstate_change_ns and usr_retraining_ns wm values until DML is implemented */
-	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns / 4;
-	context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns / 8;
-
+	//context->bw_ctx.bw.dcn.watermarks.d.usr_retraining = context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns / 8;
 	/* Set C, for Dummy P-State:
 	 * All clocks min.
 	 * DCFCLK: Min, as reported by PM FW, when available
@@ -1773,13 +1772,11 @@ static void dml_calculate_wm_and_dlg(
 	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 	context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-	//context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_wm_fclk_pstate(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 	//context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_wm_usr_retraining(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 
 	/* Temporary, to have some fclk_pstate_change_ns and usr_retraining_ns wm values until DML is implemented */
-	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns / 4;
-	context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns / 8;
-
+	//context->bw_ctx.bw.dcn.watermarks.c.usr_retraining = context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns / 8;
 	if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) {
 		/* The only difference between A and C is p-state latency, if p-state is not supported
 		 * with full p-state latency we want to calculate DLG based on dummy p-state latency,
-- 
GitLab


From 265280b99822e5562eb431b102f2ba773c7b2a0a Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Mon, 21 Feb 2022 17:01:06 -0500
Subject: [PATCH 0155/1731] drm/amd/display: add CLKMGR changes for DCN32/321

Add support for managing DCN3.2.x clocks.

v2: squash in smu interface updates (Alex)
v3: Drop unused SMU header (Alex)

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/dc/clk_mgr/Makefile   |   35 +
 .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c  |   17 +-
 .../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c  |   15 +-
 .../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h  |   60 +
 .../drm/amd/display/dc/clk_mgr/dcn32/dalsmc.h |   65 +
 .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c  |  628 +++++
 .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h  |   39 +
 .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c  |  117 +
 .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h  |   49 +
 .../dc/clk_mgr/dcn32/smu13_driver_if.h        |  108 +
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |    3 +
 drivers/gpu/drm/amd/display/dc/dc.h           |    3 +
 .../amd/display/dc/dcn321/dcn321_resource.c   | 2325 +++++++++++++++++
 .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h   |    2 +
 .../amd/display/dc/inc/hw/clk_mgr_internal.h  |   45 +-
 15 files changed, 3506 insertions(+), 5 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dalsmc.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
index 8178719176329..c935c10b5f4f5 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
@@ -172,4 +172,39 @@ AMD_DAL_CLK_MGR_DCN316 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn316/,$(CLK_MGR_
 
 AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN316)
 
+###############################################################################
+# DCN32
+###############################################################################
+CLK_MGR_DCN32 = dcn32_clk_mgr.o dcn32_clk_mgr_smu_msg.o
+
+AMD_DAL_CLK_MGR_DCN32 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn32/,$(CLK_MGR_DCN32))
+
+ifdef CONFIG_X86
+CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -msse
+endif
+
+ifdef CONFIG_PPC64
+CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -mhard-float -maltivec
+endif
+
+ifdef CONFIG_CC_IS_GCC
+ifeq ($(call cc-ifversion, -lt, 0701, y), y)
+IS_OLD_GCC = 1
+endif
+CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -mhard-float
+endif
+
+ifdef CONFIG_X86
+ifdef IS_OLD_GCC
+# Stack alignment mismatch, proceed with caution.
+# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+# (8B stack alignment).
+CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -mpreferred-stack-boundary=4
+else
+CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -msse2
+endif
+endif
+
+AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN32)
+
 endif
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index 772bffda68cc7..e803e59abd56c 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -45,6 +45,7 @@
 #include "dcn31/dcn31_clk_mgr.h"
 #include "dcn315/dcn315_clk_mgr.h"
 #include "dcn316/dcn316_clk_mgr.h"
+#include "dcn32/dcn32_clk_mgr.h"
 
 
 int clk_mgr_helper_get_active_display_cnt(
@@ -316,8 +317,19 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
 		return &clk_mgr->base.base;
 	}
 		break;
-#endif
+	case AMDGPU_FAMILY_GC_11_0_0: {
+	    struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
+
+	    if (clk_mgr == NULL) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	    }
 
+	    dcn32_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+	    return &clk_mgr->base;
+	    break;
+#endif
+	}
 	default:
 		ASSERT(0); /* Unknown Asic */
 		break;
@@ -360,6 +372,9 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
 		dcn316_clk_mgr_destroy(clk_mgr);
 		break;
 
+	case AMDGPU_FAMILY_GC_11_0_0:
+		dcn32_clk_mgr_destroy(clk_mgr);
+		break;
 	default:
 		break;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
index 5ed6a93d1708c..914708cefc795 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
@@ -129,7 +129,7 @@ static noinline void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
 
 	/* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;
-	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dummy_pstate_latency_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 0;
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
@@ -137,6 +137,14 @@ static noinline void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
+	clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = 1600;
+	clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38;
+	clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = 8000;
+	clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9;
+	clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = 10000;
+	clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8;
+	clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = 16000;
+	clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5;
 
 	/* Set D - MALL - SR enter and exit times adjusted for MALL */
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
@@ -517,6 +525,8 @@ static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct d
 	if (!clk_mgr->smu_present)
 		return;
 
+	/* TODO - DP2.0 HW: calculate link 128b/132 link rate in clock manager with new formula */
+
 	clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
 
 	for (i = 0; i < MAX_PIPES * 2; i++) {
@@ -620,7 +630,8 @@ void dcn3_clk_mgr_construct(
 
 void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
 {
-	kfree(clk_mgr->base.bw_params);
+	if (clk_mgr->base.bw_params)
+		kfree(clk_mgr->base.bw_params);
 
 	if (clk_mgr->wm_range_table)
 		dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h
index dd4a0bd72458e..2cd95ec382668 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h
@@ -26,6 +26,66 @@
 #ifndef __DCN30_CLK_MGR_H__
 #define __DCN30_CLK_MGR_H__
 
+//CLK1_CLK_PLL_REQ
+#ifndef CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT
+#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT                                                                   0x0
+#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT                                                                  0xc
+#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT                                                                  0x10
+#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int_MASK                                                                     0x000001FFL
+#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv_MASK                                                                    0x0000F000L
+#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac_MASK                                                                    0xFFFF0000L
+//CLK1_CLK0_DFS_CNTL
+#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER__SHIFT                                                               0x0
+#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER_MASK                                                                 0x0000007FL
+/*DPREF clock related*/
+#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT                                                               0x0
+#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK                                                                 0x0000007FL
+#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT                                                               0x0
+#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK                                                                 0x0000007FL
+#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT                                                               0x0
+#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK                                                                 0x0000007FL
+#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT                                                               0x0
+#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK                                                                 0x0000007FL
+
+//CLK3_0_CLK3_CLK_PLL_REQ
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT                                                            0x0
+#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT                                                           0xc
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT                                                           0x10
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK                                                              0x000001FFL
+#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK                                                             0x0000F000L
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK                                                             0xFFFF0000L
+
+#define mmCLK0_CLK2_DFS_CNTL                            0x16C55
+#define mmCLK00_CLK0_CLK2_DFS_CNTL                      0x16C55
+#define mmCLK01_CLK0_CLK2_DFS_CNTL                      0x16E55
+#define mmCLK02_CLK0_CLK2_DFS_CNTL                      0x17055
+
+#define mmCLK0_CLK3_DFS_CNTL                            0x16C60
+#define mmCLK00_CLK0_CLK3_DFS_CNTL                      0x16C60
+#define mmCLK01_CLK0_CLK3_DFS_CNTL                      0x16E60
+#define mmCLK02_CLK0_CLK3_DFS_CNTL                      0x17060
+#define mmCLK03_CLK0_CLK3_DFS_CNTL                      0x17260
+
+#define mmCLK0_CLK_PLL_REQ                              0x16C10
+#define mmCLK00_CLK0_CLK_PLL_REQ                        0x16C10
+#define mmCLK01_CLK0_CLK_PLL_REQ                        0x16E10
+#define mmCLK02_CLK0_CLK_PLL_REQ                        0x17010
+#define mmCLK03_CLK0_CLK_PLL_REQ                        0x17210
+
+#define mmCLK1_CLK_PLL_REQ                              0x1B00D
+#define mmCLK10_CLK1_CLK_PLL_REQ                        0x1B00D
+#define mmCLK11_CLK1_CLK_PLL_REQ                        0x1B20D
+#define mmCLK12_CLK1_CLK_PLL_REQ                        0x1B40D
+#define mmCLK13_CLK1_CLK_PLL_REQ                        0x1B60D
+
+#define mmCLK2_CLK_PLL_REQ                              0x17E0D
+
+/*AMCLK*/
+
+#define mmCLK11_CLK1_CLK0_DFS_CNTL                      0x1B23F
+#define mmCLK11_CLK1_CLK_PLL_REQ                        0x1B20D
+
+#endif
 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base);
 
 void dcn3_clk_mgr_construct(struct dc_context *ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dalsmc.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dalsmc.h
new file mode 100644
index 0000000000000..c427be6add8af
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dalsmc.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef DALSMC_H
+#define DALSMC_H
+
+#define DALSMC_VERSION 0x1
+
+// SMU Response Codes:
+#define DALSMC_Result_OK                   0x1
+#define DALSMC_Result_Failed               0xFF
+#define DALSMC_Result_UnknownCmd           0xFE
+#define DALSMC_Result_CmdRejectedPrereq    0xFD
+#define DALSMC_Result_CmdRejectedBusy      0xFC
+
+// Message Definitions:
+#define DALSMC_MSG_TestMessage                    0x1
+#define DALSMC_MSG_GetSmuVersion                  0x2
+#define DALSMC_MSG_GetDriverIfVersion             0x3
+#define DALSMC_MSG_GetMsgHeaderVersion            0x4
+#define DALSMC_MSG_SetDalDramAddrHigh             0x5
+#define DALSMC_MSG_SetDalDramAddrLow              0x6
+#define DALSMC_MSG_TransferTableSmu2Dram          0x7
+#define DALSMC_MSG_TransferTableDram2Smu          0x8
+#define DALSMC_MSG_SetHardMinByFreq               0x9
+#define DALSMC_MSG_SetHardMaxByFreq               0xA
+#define DALSMC_MSG_GetDpmFreqByIndex              0xB
+#define DALSMC_MSG_GetDcModeMaxDpmFreq            0xC
+#define DALSMC_MSG_SetMinDeepSleepDcfclk          0xD
+#define DALSMC_MSG_NumOfDisplays                  0xE
+#define DALSMC_MSG_SetExternalClientDfCstateAllow 0xF
+#define DALSMC_MSG_BacoAudioD3PME                 0x10
+#define DALSMC_MSG_SetFclkSwitchAllow             0x11
+#define DALSMC_MSG_SetCabForUclkPstate            0x12
+#define DALSMC_MSG_SetWorstCaseUclkLatency        0x13
+#define DALSMC_Message_Count                      0x14
+
+typedef enum {
+	FCLK_SWITCH_DISALLOW,
+	FCLK_SWITCH_ALLOW,
+} FclkSwitchAllow_e;
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
new file mode 100644
index 0000000000000..419cc83b3d21f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -0,0 +1,628 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dccg.h"
+#include "clk_mgr_internal.h"
+
+#include "dcn32/dcn32_clk_mgr_smu_msg.h"
+#include "dcn20/dcn20_clk_mgr.h"
+#include "dce100/dce_clk_mgr.h"
+#include "reg_helper.h"
+#include "core_types.h"
+#include "dm_helpers.h"
+
+#include "atomfirmware.h"
+#include "smu13_driver_if.h"
+
+#include "dcn/dcn_3_2_0_offset.h"
+#include "dcn/dcn_3_2_0_sh_mask.h"
+
+#include "dcn32/dcn32_clk_mgr.h"
+
+#define DCN_BASE__INST0_SEG1                       0x000000C0
+
+#define mmCLK1_CLK_PLL_REQ                              0x16E37
+#define mmCLK1_CLK0_DFS_CNTL                            0x16E69
+#define mmCLK1_CLK1_DFS_CNTL                            0x16E6C
+#define mmCLK1_CLK2_DFS_CNTL                            0x16E6F
+#define mmCLK1_CLK3_DFS_CNTL                            0x16E72
+#define mmCLK1_CLK4_DFS_CNTL                            0x16E75
+
+#define CLK1_CLK_PLL_REQ__FbMult_int_MASK               0x000001ffUL
+#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK              0x0000f000UL
+#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK              0xffff0000UL
+#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT             0x00000000
+#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT            0x0000000c
+#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT            0x00000010
+
+#define mmCLK01_CLK0_CLK_PLL_REQ                        0x16E37
+#define mmCLK01_CLK0_CLK0_DFS_CNTL                      0x16E64
+#define mmCLK01_CLK0_CLK1_DFS_CNTL                      0x16E67
+#define mmCLK01_CLK0_CLK2_DFS_CNTL                      0x16E6A
+#define mmCLK01_CLK0_CLK3_DFS_CNTL                      0x16E6D
+#define mmCLK01_CLK0_CLK4_DFS_CNTL                      0x16E70
+
+#define CLK0_CLK_PLL_REQ__FbMult_int_MASK               0x000001ffL
+#define CLK0_CLK_PLL_REQ__PllSpineDiv_MASK              0x0000f000L
+#define CLK0_CLK_PLL_REQ__FbMult_frac_MASK              0xffff0000L
+#define CLK0_CLK_PLL_REQ__FbMult_int__SHIFT             0x00000000
+#define CLK0_CLK_PLL_REQ__PllSpineDiv__SHIFT            0x0000000c
+#define CLK0_CLK_PLL_REQ__FbMult_frac__SHIFT            0x00000010
+
+#undef FN
+#define FN(reg_name, field_name) \
+	clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
+
+#define REG(reg) \
+	(clk_mgr->regs->reg)
+
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+#define BASE(seg) BASE_INNER(seg)
+
+#define SR(reg_name)\
+		.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
+					reg ## reg_name
+
+#define CLK_SR_DCN32(reg_name)\
+	.reg_name = mm ## reg_name
+
+static const struct clk_mgr_registers clk_mgr_regs_dcn32 = {
+	CLK_REG_LIST_DCN32()
+};
+
+static const struct clk_mgr_shift clk_mgr_shift_dcn32 = {
+	CLK_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct clk_mgr_mask clk_mgr_mask_dcn32 = {
+	CLK_COMMON_MASK_SH_LIST_DCN32(_MASK)
+};
+
+
+#define CLK_SR_DCN321(reg_name, block, inst)\
+	.reg_name = mm ## block ## _ ## reg_name
+
+static const struct clk_mgr_registers clk_mgr_regs_dcn321 = {
+	CLK_REG_LIST_DCN321()
+};
+
+static const struct clk_mgr_shift clk_mgr_shift_dcn321 = {
+	CLK_COMMON_MASK_SH_LIST_DCN321(__SHIFT)
+};
+
+static const struct clk_mgr_mask clk_mgr_mask_dcn321 = {
+	CLK_COMMON_MASK_SH_LIST_DCN321(_MASK)
+};
+
+
+/* Query SMU for all clock states for a particular clock */
+static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,
+		unsigned int *num_levels)
+{
+	unsigned int i;
+	char *entry_i = (char *)entry_0;
+
+	uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
+
+	if (ret & (1 << 31))
+		/* fine-grained, only min and max */
+		*num_levels = 2;
+	else
+		/* discrete, a number of fixed states */
+		/* will set num_levels to 0 on failure */
+		*num_levels = ret & 0xFF;
+
+	/* if the initial message failed, num_levels will be 0 */
+	for (i = 0; i < *num_levels; i++) {
+		*((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
+		entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
+	}
+}
+
+static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
+{
+	/* defaults */
+	double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;
+	double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us;
+	double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;
+	double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
+	/* For min clocks use as reported by PM FW and report those as min */
+	uint16_t min_uclk_mhz			= clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
+	uint16_t min_dcfclk_mhz			= clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
+	uint16_t setb_min_uclk_mhz		= min_uclk_mhz;
+	uint16_t setb_min_dcfclk_mhz	= min_dcfclk_mhz;
+	/* For Set B ranges use min clocks state 2 when available, and report those to PM FW */
+	if (clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz)
+		setb_min_dcfclk_mhz = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;
+	if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz)
+		setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz;
+
+	/* Set A - Normal - default values */
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_latency_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
+
+	/* Set B - Performance - higher clocks, using DPM[2] DCFCLK and UCLK */
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us = fclk_change_latency_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = setb_min_dcfclk_mhz;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = setb_min_uclk_mhz;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;
+
+	/* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */
+	/* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */
+	if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 38;
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_latency_us;
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
+		clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16;
+		clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38;
+		clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16;
+		clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9;
+		clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16;
+		clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8;
+		clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16;
+		clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5;
+	}
+	/* Set D - MALL - SR enter and exit time specific to MALL, TBD after bringup or later phase for now use DRAM values / 2 */
+	/* For MALL DRAM clock change latency is N/A, for watermak calculations use lowest value dummy P state latency */
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us = fclk_change_latency_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2; // TBD
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us / 2; // TBD
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;
+}
+
+void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	unsigned int num_levels;
+
+	memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
+	clk_mgr_base->clks.p_state_change_support = true;
+	clk_mgr_base->clks.prev_p_state_change_support = true;
+	clk_mgr_base->clks.fclk_prev_p_state_change_support = true;
+	clk_mgr->smu_present = false;
+
+	if (!clk_mgr_base->bw_params)
+		return;
+
+	if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
+		clk_mgr->smu_present = true;
+
+	if (!clk_mgr->smu_present)
+		return;
+
+	dcn30_smu_check_driver_if_version(clk_mgr);
+	dcn30_smu_check_msg_header_version(clk_mgr);
+
+	/* DCFCLK */
+	dcn32_init_single_clock(clk_mgr, PPCLK_DCFCLK,
+			&clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
+			&num_levels);
+
+	/* SOCCLK */
+	dcn32_init_single_clock(clk_mgr, PPCLK_SOCCLK,
+					&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
+					&num_levels);
+	/* DTBCLK */
+	dcn32_init_single_clock(clk_mgr, PPCLK_DTBCLK,
+			&clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
+			&num_levels);
+
+	/* DISPCLK */
+	dcn32_init_single_clock(clk_mgr, PPCLK_DISPCLK,
+			&clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
+			&num_levels);
+
+
+	/* Get UCLK, update bounding box */
+	clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
+
+	/* WM range table */
+	dcn32_build_wm_range_table(clk_mgr);
+}
+
+static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
+			struct dc_state *context,
+			bool safe_to_lower)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
+	struct dc *dc = clk_mgr_base->ctx->dc;
+	int display_count;
+	bool update_dppclk = false;
+	bool update_dispclk = false;
+	bool enter_display_off = false;
+	bool dpp_clock_lowered = false;
+	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
+	bool force_reset = false;
+	bool update_uclk = false;
+	bool p_state_change_support;
+	bool fclk_p_state_change_support;
+	int total_plane_count;
+
+	if (dc->work_arounds.skip_clock_update)
+		return;
+
+	if (clk_mgr_base->clks.dispclk_khz == 0 ||
+			(dc->debug.force_clock_mode & 0x1)) {
+		/* This is from resume or boot up, if forced_clock cfg option used,
+		 * we bypass program dispclk and DPPCLK, but need set them for S3.
+		 */
+		force_reset = true;
+
+		dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
+
+		/* Force_clock_mode 0x1:  force reset the clock even it is the same clock
+		 * as long as it is in Passive level.
+		 */
+	}
+	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
+
+	if (display_count == 0)
+		enter_display_off = true;
+
+	if (enter_display_off == safe_to_lower)
+		dcn30_smu_set_num_of_displays(clk_mgr, display_count);
+
+	if (dc->debug.force_min_dcfclk_mhz > 0)
+		new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
+				new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
+
+	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
+		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
+		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
+	}
+
+	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
+		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
+		dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
+	}
+
+	if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
+		/* We don't actually care about socclk, don't notify SMU of hard min */
+		clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
+
+	clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
+	clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support;
+
+	total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
+	p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
+	fclk_p_state_change_support = new_clocks->fclk_p_state_change_support || (total_plane_count == 0);
+	if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
+		clk_mgr_base->clks.p_state_change_support = p_state_change_support;
+
+		/* to disable P-State switching, set UCLK min = max */
+		if (!clk_mgr_base->clks.p_state_change_support)
+			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
+					clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
+	}
+
+	if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) {
+		clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
+
+		/* To disable FCLK P-state switching, send FCLK_PSTATE_NOTSUPPORTED message to PMFW */
+		if (!clk_mgr_base->clks.fclk_p_state_change_support) {
+			/* Handle code for sending a message to PMFW that FCLK P-state change is not supported */
+			dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED);
+		}
+	}
+
+	/* Always update saved value, even if new value not set due to P-State switching unsupported */
+	if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
+		clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
+		update_uclk = true;
+	}
+
+	/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
+	if (clk_mgr_base->clks.p_state_change_support &&
+			(update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))
+		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
+
+	if (clk_mgr_base->clks.fclk_p_state_change_support &&
+			(update_uclk || !clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
+		/* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
+		dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED);
+	}
+
+	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
+		if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
+			dpp_clock_lowered = true;
+
+		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
+		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
+		update_dppclk = true;
+	}
+
+	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
+		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
+		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));
+		update_dispclk = true;
+	}
+
+	if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
+		if (dpp_clock_lowered) {
+			/* if clock is being lowered, increase DTO before lowering refclk */
+			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
+			dcn20_update_clocks_update_dentist(clk_mgr, context);
+		} else {
+			/* if clock is being raised, increase refclk before lowering DTO */
+			if (update_dppclk || update_dispclk)
+				dcn20_update_clocks_update_dentist(clk_mgr, context);
+			/* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures
+			 * that we do not lower dto when it is not safe to lower. We do not need to
+			 * compare the current and new dppclk before calling this function.
+			 */
+			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
+		}
+	}
+
+	if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
+		/*update dmcu for wait_loop count*/
+		dmcu->funcs->set_psr_wait_loop(dmcu,
+				clk_mgr_base->clks.dispclk_khz / 1000 / 7);
+}
+
+void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)
+{
+	struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
+	int ss_info_num = bp->funcs->get_ss_entry_number(
+			bp, AS_SIGNAL_TYPE_GPU_PLL);
+
+	if (ss_info_num) {
+		struct spread_spectrum_info info = { { 0 } };
+		enum bp_result result = bp->funcs->get_spread_spectrum_info(
+				bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
+
+		/* SSInfo.spreadSpectrumPercentage !=0 would be sign
+		 * that SS is enabled
+		 */
+		if (result == BP_RESULT_OK &&
+				info.spread_spectrum_percentage != 0) {
+			clk_mgr->ss_on_dprefclk = true;
+			clk_mgr->dprefclk_ss_divider = info.spread_percentage_divider;
+
+			if (info.type.CENTER_MODE == 0) {
+				/* Currently for DP Reference clock we
+				 * need only SS percentage for
+				 * downspread
+				 */
+				clk_mgr->dprefclk_ss_percentage =
+						info.spread_spectrum_percentage;
+			}
+		}
+	}
+}
+static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
+
+	if (!clk_mgr->smu_present)
+		return;
+
+	if (!table)
+		return;
+
+	memset(table, 0, sizeof(*table));
+
+	dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
+	dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
+	dcn32_smu_transfer_wm_table_dram_2_smu(clk_mgr);
+}
+
+/* Set min memclk to minimum, either constrained by the current mode or DPM0 */
+static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+
+	if (!clk_mgr->smu_present)
+		return;
+
+	if (current_mode) {
+		if (clk_mgr_base->clks.p_state_change_support)
+			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
+					khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
+		else
+			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
+					clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
+	} else {
+		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
+				clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
+	}
+}
+
+/* Set max memclk to highest DPM value */
+static void dcn32_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+
+	if (!clk_mgr->smu_present)
+		return;
+
+	dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
+			clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
+}
+
+/* Get current memclk states, update bounding box */
+static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	unsigned int num_levels;
+
+	if (!clk_mgr->smu_present)
+		return;
+
+	/* Refresh memclk states */
+	dcn32_init_single_clock(clk_mgr, PPCLK_UCLK,
+			&clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
+			&num_levels);
+	clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
+
+	/* Refresh bounding box */
+	clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
+			clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
+}
+
+static bool dcn32_are_clock_states_equal(struct dc_clocks *a,
+					struct dc_clocks *b)
+{
+	if (a->dispclk_khz != b->dispclk_khz)
+		return false;
+	else if (a->dppclk_khz != b->dppclk_khz)
+		return false;
+	else if (a->dcfclk_khz != b->dcfclk_khz)
+		return false;
+	else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
+		return false;
+	else if (a->dramclk_khz != b->dramclk_khz)
+		return false;
+	else if (a->p_state_change_support != b->p_state_change_support)
+		return false;
+	else if (a->fclk_p_state_change_support != b->fclk_p_state_change_support)
+		return false;
+
+	return true;
+}
+
+static void dcn32_enable_pme_wa(struct clk_mgr *clk_mgr_base)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+
+	if (!clk_mgr->smu_present)
+		return;
+
+	dcn30_smu_set_pme_workaround(clk_mgr);
+}
+
+static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	return clk_mgr->smu_present;
+}
+
+
+static struct clk_mgr_funcs dcn32_funcs = {
+		.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
+		.update_clocks = dcn32_update_clocks,
+		.init_clocks = dcn32_init_clocks,
+		.notify_wm_ranges = dcn32_notify_wm_ranges,
+		.set_hard_min_memclk = dcn32_set_hard_min_memclk,
+		.set_hard_max_memclk = dcn32_set_hard_max_memclk,
+		.get_memclk_states_from_smu = dcn32_get_memclk_states_from_smu,
+		.are_clock_states_equal = dcn32_are_clock_states_equal,
+		.enable_pme_wa = dcn32_enable_pme_wa,
+		.is_smu_present = dcn32_is_smu_present,
+};
+
+void dcn32_clk_mgr_construct(
+		struct dc_context *ctx,
+		struct clk_mgr_internal *clk_mgr,
+		struct pp_smu_funcs *pp_smu,
+		struct dccg *dccg)
+{
+	clk_mgr->base.ctx = ctx;
+	clk_mgr->base.funcs = &dcn32_funcs;
+	if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
+		clk_mgr->regs = &clk_mgr_regs_dcn321;
+		clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn321;
+		clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn321;
+	} else {
+		clk_mgr->regs = &clk_mgr_regs_dcn32;
+		clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn32;
+		clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn32;
+	}
+
+	clk_mgr->dccg = dccg;
+	clk_mgr->dfs_bypass_disp_clk = 0;
+
+	clk_mgr->dprefclk_ss_percentage = 0;
+	clk_mgr->dprefclk_ss_divider = 1000;
+	clk_mgr->ss_on_dprefclk = false;
+	clk_mgr->dfs_ref_freq_khz = 100000;
+
+	clk_mgr->base.dprefclk_khz = 717000; /* Changed as per DCN3.2_clock_frequency doc */
+	clk_mgr->dccg->ref_dtbclk_khz = 477800;
+
+	/* integer part is now VCO frequency in kHz */
+	clk_mgr->base.dentist_vco_freq_khz = 4300000;//dcn32_get_vco_frequency_from_reg(clk_mgr);
+	/* in case we don't get a value from the register, use default */
+	if (clk_mgr->base.dentist_vco_freq_khz == 0)
+		clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */
+
+	if (clk_mgr->base.boot_snapshot.dprefclk != 0) {
+		//ASSERT(clk_mgr->base.dprefclk_khz == clk_mgr->base.boot_snapshot.dprefclk);
+		//clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;
+	}
+	dcn32_clock_read_ss_info(clk_mgr);
+
+	clk_mgr->dfs_bypass_enabled = false;
+
+	clk_mgr->smu_present = false;
+
+	clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
+
+	/* need physical address of table to give to PMFW */
+	clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
+			DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
+			&clk_mgr->wm_range_table_addr);
+}
+
+void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
+{
+	if (clk_mgr->base.bw_params)
+		kfree(clk_mgr->base.bw_params);
+
+	if (clk_mgr->wm_range_table)
+		dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
+				clk_mgr->wm_range_table);
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h
new file mode 100644
index 0000000000000..57e09c7c95f5b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DCN32_CLK_MGR_H_
+#define __DCN32_CLK_MGR_H_
+
+void dcn32_init_clocks(struct clk_mgr *clk_mgr_base);
+
+void dcn32_clk_mgr_construct(struct dc_context *ctx,
+		struct clk_mgr_internal *clk_mgr,
+		struct pp_smu_funcs *pp_smu,
+		struct dccg *dccg);
+
+void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);
+
+
+
+#endif /* __DCN32_CLK_MGR_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
new file mode 100644
index 0000000000000..35e8afe6db933
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dcn32_clk_mgr_smu_msg.h"
+
+#include "clk_mgr_internal.h"
+#include "reg_helper.h"
+
+#define mmDAL_MSG_REG  0x1628A
+#define mmDAL_ARG_REG  0x16273
+#define mmDAL_RESP_REG 0x16274
+
+#define DALSMC_MSG_TransferTableDram2Smu          0x8
+
+#define REG(reg_name) \
+	mm ## reg_name
+
+#include "logger_types.h"
+#include "dalsmc.h"
+#include "smu13_driver_if.h"
+
+#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
+
+
+/*
+ * Function to be used instead of REG_WAIT macro because the wait ends when
+ * the register is NOT EQUAL to zero, and because the translation in msg_if.h
+ * won't work with REG_WAIT.
+ */
+static uint32_t dcn32_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
+{
+	uint32_t reg = 0;
+
+	do {
+		reg = REG_READ(DAL_RESP_REG);
+		if (reg)
+			break;
+
+		if (delay_us >= 1000)
+			msleep(delay_us/1000);
+		else if (delay_us > 0)
+			udelay(delay_us);
+	} while (max_retries--);
+
+	return reg;
+}
+
+static bool dcn32_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)
+{
+	/* Wait for response register to be ready */
+	dcn32_smu_wait_for_response(clk_mgr, 10, 200000);
+
+	/* Clear response register */
+	REG_WRITE(DAL_RESP_REG, 0);
+
+	/* Set the parameter register for the SMU message */
+	REG_WRITE(DAL_ARG_REG, param_in);
+
+	/* Trigger the message transaction by writing the message ID */
+	REG_WRITE(DAL_MSG_REG, msg_id);
+
+	/* Wait for response */
+	if (dcn32_smu_wait_for_response(clk_mgr, 10, 200000) == DALSMC_Result_OK) {
+		if (param_out)
+			*param_out = REG_READ(DAL_ARG_REG);
+
+		return true;
+	}
+
+	return false;
+}
+
+void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable)
+{
+	smu_print("FCLK P-state support value is : %d\n", enable);
+
+	dcn32_smu_send_msg_with_param(clk_mgr,
+			DALSMC_MSG_SetFclkSwitchAllow, enable ? FCLK_PSTATE_SUPPORTED : FCLK_PSTATE_NOTSUPPORTED, NULL);
+}
+
+void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
+{
+       smu_print("SMU Transfer WM table DRAM 2 SMU\n");
+
+       dcn32_smu_send_msg_with_param(clk_mgr,
+                       DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL);
+}
+
+void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways)
+{
+	smu_print("Numways for SubVP : %d\n", num_ways);
+
+	dcn32_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_SetCabForUclkPstate, num_ways, NULL);
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
new file mode 100644
index 0000000000000..11b25de1527fb
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DCN32_CLK_MGR_SMU_MSG_H_
+#define __DCN32_CLK_MGR_SMU_MSG_H_
+
+#include "core_types.h"
+#include "dcn30/dcn30_clk_mgr_smu_msg.h"
+
+#define FCLK_PSTATE_NOTSUPPORTED       0x00
+#define FCLK_PSTATE_SUPPORTED          0x01
+
+/* TODO Remove this MSG ID define after it becomes available in dalsmc */
+#define DALSMC_MSG_SetFclkSwitchAllow	0x11
+#define DALSMC_MSG_SetCabForUclkPstate	0x12
+#define DALSMC_Result_OK				0x1
+
+void
+dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr,
+				   bool enable);
+
+void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
+
+void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways);
+
+
+#endif /* __DCN32_CLK_MGR_SMU_MSG_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h
new file mode 100644
index 0000000000000..deeb85047e7ba
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef SMU13_DRIVER_IF_DCN32_H
+#define SMU13_DRIVER_IF_DCN32_H
+
+// *** IMPORTANT ***
+// PMFW TEAM: Always increment the interface version on any change to this file
+#define SMU13_DRIVER_IF_VERSION  0x18
+
+//Only Clks that have DPM descriptors are listed here
+typedef enum {
+  PPCLK_GFXCLK = 0,
+  PPCLK_SOCCLK,
+  PPCLK_UCLK,
+  PPCLK_FCLK,
+  PPCLK_DCLK_0,
+  PPCLK_VCLK_0,
+  PPCLK_DCLK_1,
+  PPCLK_VCLK_1,
+  PPCLK_DISPCLK,
+  PPCLK_DPPCLK,
+  PPCLK_DPREFCLK,
+  PPCLK_DCFCLK,
+  PPCLK_DTBCLK,
+  PPCLK_COUNT,
+} PPCLK_e;
+
+typedef enum {
+  UCLK_DIV_BY_1 = 0,
+  UCLK_DIV_BY_2,
+  UCLK_DIV_BY_4,
+  UCLK_DIV_BY_8,
+} UCLK_DIV_e;
+
+typedef struct {
+  uint8_t  WmSetting;
+  uint8_t  Flags;
+  uint8_t  Padding[2];
+
+} WatermarkRowGeneric_t;
+
+#define NUM_WM_RANGES 4
+
+typedef enum {
+  WATERMARKS_CLOCK_RANGE = 0,
+  WATERMARKS_DUMMY_PSTATE,
+  WATERMARKS_MALL,
+  WATERMARKS_COUNT,
+} WATERMARKS_FLAGS_e;
+
+typedef struct {
+  // Watermarks
+  WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES];
+} Watermarks_t;
+
+typedef struct {
+  Watermarks_t Watermarks;
+  uint32_t  Spare[16];
+
+  uint32_t     MmHubPadding[8]; // SMU internal use
+} WatermarksExternal_t;
+
+// These defines are used with the following messages:
+// SMC_MSG_TransferTableDram2Smu
+// SMC_MSG_TransferTableSmu2Dram
+
+// Table transfer status
+#define TABLE_TRANSFER_OK         0x0
+#define TABLE_TRANSFER_FAILED     0xFF
+#define TABLE_TRANSFER_PENDING    0xAB
+
+// Table types
+#define TABLE_PMFW_PPTABLE            0
+#define TABLE_COMBO_PPTABLE           1
+#define TABLE_WATERMARKS              2
+#define TABLE_AVFS_PSM_DEBUG          3
+#define TABLE_PMSTATUSLOG             4
+#define TABLE_SMU_METRICS             5
+#define TABLE_DRIVER_SMU_CONFIG       6
+#define TABLE_ACTIVITY_MONITOR_COEFF  7
+#define TABLE_OVERDRIVE               8
+#define TABLE_I2C_COMMANDS            9
+#define TABLE_DRIVER_INFO             10
+#define TABLE_COUNT                   11
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index bea77172bd14f..1ec81426498f4 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3975,6 +3975,9 @@ static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_
 	return true;
 }
 
+bool FORCE_RATE = false;
+uint32_t FORCE_LANE_COUNT = 0;
+
 void decide_link_settings(struct dc_stream_state *stream,
 	struct dc_link_settings *link_setting)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 11b02a98cf0f9..52d6da5ea9a7c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -418,12 +418,15 @@ struct dc_clocks {
 	enum dcn_zstate_support_state zstate_support;
 	bool dtbclk_en;
 	int ref_dtbclk_khz;
+	int dtbclk_khz;
+	bool fclk_p_state_change_support;
 	enum dcn_pwr_state pwr_state;
 	/*
 	 * Elements below are not compared for the purposes of
 	 * optimization required
 	 */
 	bool prev_p_state_change_support;
+	bool fclk_prev_p_state_change_support;
 	enum dtm_pstate dtm_level;
 	int max_supported_dppclk_khz;
 	int max_supported_dispclk_khz;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
new file mode 100644
index 0000000000000..a8fb4ab8ced1a
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -0,0 +1,2325 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "dm_services.h"
+#include "dc.h"
+
+#include "dcn32/dcn32_init.h"
+
+#include "resource.h"
+#include "include/irq_service_interface.h"
+#include "dcn32/dcn32_resource.h"
+#include "dcn321_resource.h"
+
+#include "dcn20/dcn20_resource.h"
+#include "dcn30/dcn30_resource.h"
+
+#include "dcn10/dcn10_ipp.h"
+#include "dcn30/dcn30_hubbub.h"
+#include "dcn31/dcn31_hubbub.h"
+#include "dcn32/dcn32_hubbub.h"
+#include "dcn32/dcn32_mpc.h"
+#include "dcn32/dcn32_hubp.h"
+#include "irq/dcn32/irq_service_dcn32.h"
+#include "dcn32/dcn32_dpp.h"
+#include "dcn32/dcn32_optc.h"
+#include "dcn20/dcn20_hwseq.h"
+#include "dcn30/dcn30_hwseq.h"
+#include "dce110/dce110_hw_sequencer.h"
+#include "dcn30/dcn30_opp.h"
+#include "dcn20/dcn20_dsc.h"
+#include "dcn30/dcn30_vpg.h"
+#include "dcn30/dcn30_afmt.h"
+#include "dcn30/dcn30_dio_stream_encoder.h"
+#include "dcn32/dcn32_dio_stream_encoder.h"
+#include "dcn31/dcn31_hpo_dp_stream_encoder.h"
+#include "dcn31/dcn31_hpo_dp_link_encoder.h"
+#include "dcn32/dcn32_hpo_dp_link_encoder.h"
+#include "dc_link_dp.h"
+#include "dcn31/dcn31_apg.h"
+#include "dcn31/dcn31_dio_link_encoder.h"
+#include "dcn32/dcn32_dio_link_encoder.h"
+#include "dce/dce_clock_source.h"
+#include "dce/dce_audio.h"
+#include "dce/dce_hwseq.h"
+#include "clk_mgr.h"
+#include "virtual/virtual_stream_encoder.h"
+#include "dml/display_mode_vba.h"
+#include "dcn32/dcn32_dccg.h"
+#include "dcn10/dcn10_resource.h"
+#include "dc_link_ddc.h"
+#include "dcn31/dcn31_panel_cntl.h"
+
+#include "dcn30/dcn30_dwb.h"
+#include "dcn32/dcn32_mmhubbub.h"
+
+#include "dcn/dcn_3_2_1_offset.h"
+#include "dcn/dcn_3_2_1_sh_mask.h"
+#include "nbio/nbio_4_3_0_offset.h"
+
+#include "reg_helper.h"
+#include "dce/dmub_abm.h"
+#include "dce/dmub_psr.h"
+#include "dce/dce_aux.h"
+#include "dce/dce_i2c.h"
+
+#include "dml/dcn30/display_mode_vba_30.h"
+#include "vm_helper.h"
+#include "dcn20/dcn20_vmid.h"
+
+#define DCN_BASE__INST0_SEG1                       0x000000C0
+#define DCN_BASE__INST0_SEG2                       0x000034C0
+#define DCN_BASE__INST0_SEG3                       0x00009000
+#define NBIO_BASE__INST0_SEG1                      0x00000014
+
+#define MAX_INSTANCE                                        8
+#define MAX_SEGMENT                                         6
+
+
+struct IP_BASE_INSTANCE
+{
+    unsigned int segment[MAX_SEGMENT];
+};
+
+struct IP_BASE
+{
+    struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
+};
+
+static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+
+#define DC_LOGGER_INIT(logger)
+#define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
+#define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
+
+#define DCN3_2_DEFAULT_DET_SIZE 256
+
+struct _vcs_dpi_ip_params_st dcn3_21_ip = {
+	.gpuvm_enable = 1,
+	.gpuvm_max_page_table_levels = 1,
+	.hostvm_enable = 0,
+	.rob_buffer_size_kbytes = 128,
+	.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE,
+	.config_return_buffer_size_in_kbytes = 1280,
+	.compressed_buffer_segment_size_in_kbytes = 64,
+	.meta_fifo_size_in_kentries = 22,
+	.zero_size_buffer_entries = 512,
+	.compbuf_reserved_space_64b = 256,
+	.compbuf_reserved_space_zs = 64,
+	.dpp_output_buffer_pixels = 2560,
+	.opp_output_buffer_lines = 1,
+	.pixel_chunk_size_kbytes = 8,
+	.alpha_pixel_chunk_size_kbytes = 4, // not appearing in spreadsheet, match c code from hw team
+	.min_pixel_chunk_size_bytes = 1024,
+	.dcc_meta_buffer_size_bytes = 6272,
+	.meta_chunk_size_kbytes = 2,
+	.min_meta_chunk_size_bytes = 256,
+	.writeback_chunk_size_kbytes = 8,
+	.ptoi_supported = false,
+	.num_dsc = 4,
+	.maximum_dsc_bits_per_component = 12,
+	.maximum_pixels_per_line_per_dsc_unit = 6016,
+	.dsc422_native_support = true,
+	.is_line_buffer_bpp_fixed = true,
+	.line_buffer_fixed_bpp = 57,
+	.line_buffer_size_bits = 1171920, //DPP doc, DCN3_2_DisplayMode_73.xlsm still shows as 986880 bits with 48 bpp
+	.max_line_buffer_lines = 32,
+	.writeback_interface_buffer_size_kbytes = 90,
+	.max_num_dpp = 4,
+	.max_num_otg = 4,
+	.max_num_hdmi_frl_outputs = 1,
+	.max_num_wb = 1,
+	.max_dchub_pscl_bw_pix_per_clk = 4,
+	.max_pscl_lb_bw_pix_per_clk = 2,
+	.max_lb_vscl_bw_pix_per_clk = 4,
+	.max_vscl_hscl_bw_pix_per_clk = 4,
+	.max_hscl_ratio = 6,
+	.max_vscl_ratio = 6,
+	.max_hscl_taps = 8,
+	.max_vscl_taps = 8,
+	.dpte_buffer_size_in_pte_reqs_luma = 64,
+	.dpte_buffer_size_in_pte_reqs_chroma = 34,
+	.dispclk_ramp_margin_percent = 1,
+	.max_inter_dcn_tile_repeaters = 8,
+	.cursor_buffer_size = 16,
+	.cursor_chunk_size = 2,
+	.writeback_line_buffer_buffer_size = 0,
+	.writeback_min_hscl_ratio = 1,
+	.writeback_min_vscl_ratio = 1,
+	.writeback_max_hscl_ratio = 1,
+	.writeback_max_vscl_ratio = 1,
+	.writeback_max_hscl_taps = 1,
+	.writeback_max_vscl_taps = 1,
+	.dppclk_delay_subtotal = 47,
+	.dppclk_delay_scl = 50,
+	.dppclk_delay_scl_lb_only = 16,
+	.dppclk_delay_cnvc_formatter = 28,
+	.dppclk_delay_cnvc_cursor = 6,
+	.dispclk_delay_subtotal = 125,
+	.dynamic_metadata_vm_enabled = false,
+	.odm_combine_4to1_supported = false,
+	.dcc_supported = true,
+	.max_num_dp2p0_outputs = 2,
+	.max_num_dp2p0_streams = 4,
+};
+
+struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = {
+	.clock_limits = {
+		{
+			.state = 0,
+			.dcfclk_mhz = 1564.0,
+			.fabricclk_mhz = 400.0,
+			.dispclk_mhz = 2150.0,
+			.dppclk_mhz = 2150.0,
+			.phyclk_mhz = 810.0,
+			.phyclk_d18_mhz = 667.0,
+			.phyclk_d32_mhz = 625.0,
+			.socclk_mhz = 1200.0,
+			.dscclk_mhz = 716.667,
+			.dram_speed_mts = 1600.0,
+			.dtbclk_mhz = 1564.0,
+		},
+	},
+	.num_states = 1,
+	.sr_exit_time_us = 5.20,
+	.sr_enter_plus_exit_time_us = 9.60,
+	.sr_exit_z8_time_us = 285.0,
+	.sr_enter_plus_exit_z8_time_us = 320,
+	.writeback_latency_us = 12.0,
+	.round_trip_ping_latency_dcfclk_cycles = 263,
+	.urgent_latency_pixel_data_only_us = 4.0,
+	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
+	.urgent_latency_vm_data_only_us = 4.0,
+	.fclk_change_latency_us = 20,
+	.usr_retraining_latency_us = 2,
+	.smn_latency_us = 2,
+	.mall_allocated_for_dcn_mbytes = 64,
+	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
+	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
+	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
+	.pct_ideal_sdp_bw_after_urgent = 100.0,
+	.pct_ideal_fabric_bw_after_urgent = 67.0,
+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0,
+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented
+	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented
+	.pct_ideal_dram_bw_after_urgent_strobe = 67.0,
+	.max_avg_sdp_bw_use_normal_percent = 80.0,
+	.max_avg_fabric_bw_use_normal_percent = 60.0,
+	.max_avg_dram_bw_use_normal_strobe_percent = 50.0,
+	.max_avg_dram_bw_use_normal_percent = 15.0,
+	.num_chans = 8,
+	.dram_channel_width_bytes = 2,
+	.fabric_datapath_to_dcn_data_return_bytes = 64,
+	.return_bus_width_bytes = 64,
+	.downspread_percent = 0.38,
+	.dcn_downspread_percent = 0.5,
+	.dram_clock_change_latency_us = 400,
+	.dispclk_dppclk_vco_speed_mhz = 4300.0,
+	.do_urgent_latency_adjustment = true,
+	.urgent_latency_adjustment_fabric_clock_component_us = 1.0,
+	.urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
+};
+
+enum dcn321_clk_src_array_id {
+	DCN321_CLK_SRC_PLL0,
+	DCN321_CLK_SRC_PLL1,
+	DCN321_CLK_SRC_PLL2,
+	DCN321_CLK_SRC_PLL3,
+	DCN321_CLK_SRC_PLL4,
+	DCN321_CLK_SRC_TOTAL
+};
+
+/* begin *********************
+ * macros to expend register list macro defined in HW object header file
+ */
+
+/* DCN */
+/* TODO awful hack. fixup dcn20_dwb.h */
+#undef BASE_INNER
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+#define BASE(seg) BASE_INNER(seg)
+
+#define SR(reg_name)\
+		.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
+					reg ## reg_name
+
+#define SRI(reg_name, block, id)\
+	.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRI2(reg_name, block, id)\
+	.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
+					reg ## reg_name
+
+#define SRIR(var_name, reg_name, block, id)\
+	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRII(reg_name, block, id)\
+	.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRII_MPC_RMU(reg_name, block, id)\
+	.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRII_DWB(reg_name, temp_name, block, id)\
+	.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## temp_name
+
+#define DCCG_SRII(reg_name, block, id)\
+	.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define VUPDATE_SRII(reg_name, block, id)\
+	.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
+					reg ## reg_name ## _ ## block ## id
+
+/* NBIO */
+#define NBIO_BASE_INNER(seg) \
+	NBIO_BASE__INST0_SEG ## seg
+
+#define NBIO_BASE(seg) \
+	NBIO_BASE_INNER(seg)
+
+#define NBIO_SR(reg_name)\
+		.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
+					regBIF_BX0_ ## reg_name
+
+#define CTX ctx
+#define REG(reg_name) \
+	(DCN_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
+
+static const struct bios_registers bios_regs = {
+		NBIO_SR(BIOS_SCRATCH_3),
+		NBIO_SR(BIOS_SCRATCH_6)
+};
+
+#define clk_src_regs(index, pllid)\
+[index] = {\
+	CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
+}
+
+static const struct dce110_clk_src_regs clk_src_regs[] = {
+	clk_src_regs(0, A),
+	clk_src_regs(1, B),
+	clk_src_regs(2, C),
+	clk_src_regs(3, D)
+};
+
+static const struct dce110_clk_src_shift cs_shift = {
+		CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
+};
+
+static const struct dce110_clk_src_mask cs_mask = {
+		CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
+};
+
+#define abm_regs(id)\
+[id] = {\
+		ABM_DCN32_REG_LIST(id)\
+}
+
+static const struct dce_abm_registers abm_regs[] = {
+		abm_regs(0),
+		abm_regs(1),
+		abm_regs(2),
+		abm_regs(3),
+};
+
+static const struct dce_abm_shift abm_shift = {
+		ABM_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dce_abm_mask abm_mask = {
+		ABM_MASK_SH_LIST_DCN32(_MASK)
+};
+
+#define audio_regs(id)\
+[id] = {\
+		AUD_COMMON_REG_LIST(id)\
+}
+
+static const struct dce_audio_registers audio_regs[] = {
+	audio_regs(0),
+	audio_regs(1),
+	audio_regs(2),
+	audio_regs(3),
+	audio_regs(4)
+};
+
+#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
+		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
+
+static const struct dce_audio_shift audio_shift = {
+		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_audio_mask audio_mask = {
+		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
+};
+
+#define vpg_regs(id)\
+[id] = {\
+	VPG_DCN3_REG_LIST(id)\
+}
+
+static const struct dcn30_vpg_registers vpg_regs[] = {
+	vpg_regs(0),
+	vpg_regs(1),
+	vpg_regs(2),
+	vpg_regs(3),
+	vpg_regs(4),
+	vpg_regs(5),
+	vpg_regs(6),
+	vpg_regs(7),
+	vpg_regs(8),
+	vpg_regs(9),
+};
+
+static const struct dcn30_vpg_shift vpg_shift = {
+	DCN3_VPG_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn30_vpg_mask vpg_mask = {
+	DCN3_VPG_MASK_SH_LIST(_MASK)
+};
+
+#define afmt_regs(id)\
+[id] = {\
+	AFMT_DCN3_REG_LIST(id)\
+}
+
+static const struct dcn30_afmt_registers afmt_regs[] = {
+	afmt_regs(0),
+	afmt_regs(1),
+	afmt_regs(2),
+	afmt_regs(3),
+	afmt_regs(4),
+	afmt_regs(5)
+};
+
+static const struct dcn30_afmt_shift afmt_shift = {
+	DCN3_AFMT_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn30_afmt_mask afmt_mask = {
+	DCN3_AFMT_MASK_SH_LIST(_MASK)
+};
+
+#define apg_regs(id)\
+[id] = {\
+	APG_DCN31_REG_LIST(id)\
+}
+
+static const struct dcn31_apg_registers apg_regs[] = {
+	apg_regs(0),
+	apg_regs(1),
+	apg_regs(2),
+	apg_regs(3)
+};
+
+static const struct dcn31_apg_shift apg_shift = {
+	DCN31_APG_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn31_apg_mask apg_mask = {
+		DCN31_APG_MASK_SH_LIST(_MASK)
+};
+
+#define stream_enc_regs(id)\
+[id] = {\
+	SE_DCN32_REG_LIST(id)\
+}
+
+static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
+	stream_enc_regs(0),
+	stream_enc_regs(1),
+	stream_enc_regs(2),
+	stream_enc_regs(3),
+	stream_enc_regs(4)
+};
+
+static const struct dcn10_stream_encoder_shift se_shift = {
+		SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dcn10_stream_encoder_mask se_mask = {
+		SE_COMMON_MASK_SH_LIST_DCN32(_MASK)
+};
+
+
+#define aux_regs(id)\
+[id] = {\
+	DCN2_AUX_REG_LIST(id)\
+}
+
+static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
+		aux_regs(0),
+		aux_regs(1),
+		aux_regs(2),
+		aux_regs(3),
+		aux_regs(4)
+};
+
+#define hpd_regs(id)\
+[id] = {\
+	HPD_REG_LIST(id)\
+}
+
+static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
+		hpd_regs(0),
+		hpd_regs(1),
+		hpd_regs(2),
+		hpd_regs(3),
+		hpd_regs(4)
+};
+
+#define link_regs(id, phyid)\
+[id] = {\
+	LE_DCN31_REG_LIST(id), \
+	UNIPHY_DCN2_REG_LIST(phyid), \
+	/*DPCS_DCN31_REG_LIST(id),*/ \
+}
+
+static const struct dcn10_link_enc_registers link_enc_regs[] = {
+	link_regs(0, A),
+	link_regs(1, B),
+	link_regs(2, C),
+	link_regs(3, D),
+	link_regs(4, E)
+};
+
+static const struct dcn10_link_enc_shift le_shift = {
+	LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
+//	DPCS_DCN31_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn10_link_enc_mask le_mask = {
+	LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
+//	DPCS_DCN31_MASK_SH_LIST(_MASK)
+};
+
+#define hpo_dp_stream_encoder_reg_list(id)\
+[id] = {\
+	DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
+}
+
+static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
+	hpo_dp_stream_encoder_reg_list(0),
+	hpo_dp_stream_encoder_reg_list(1),
+	hpo_dp_stream_encoder_reg_list(2),
+	hpo_dp_stream_encoder_reg_list(3),
+};
+
+static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
+	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
+	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
+};
+
+
+#define hpo_dp_link_encoder_reg_list(id)\
+[id] = {\
+	DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
+	/*DCN3_1_RDPCSTX_REG_LIST(0),*/\
+	/*DCN3_1_RDPCSTX_REG_LIST(1),*/\
+	/*DCN3_1_RDPCSTX_REG_LIST(2),*/\
+	/*DCN3_1_RDPCSTX_REG_LIST(3),*/\
+	/*DCN3_1_RDPCSTX_REG_LIST(4)*/\
+}
+
+static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
+	hpo_dp_link_encoder_reg_list(0),
+	hpo_dp_link_encoder_reg_list(1),
+};
+
+static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
+	DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
+	DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
+};
+
+#define dpp_regs(id)\
+[id] = {\
+	DPP_REG_LIST_DCN30_COMMON(id),\
+}
+
+static const struct dcn3_dpp_registers dpp_regs[] = {
+	dpp_regs(0),
+	dpp_regs(1),
+	dpp_regs(2),
+	dpp_regs(3)
+};
+
+static const struct dcn3_dpp_shift tf_shift = {
+		DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT)
+};
+
+static const struct dcn3_dpp_mask tf_mask = {
+		DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK)
+};
+
+
+#define opp_regs(id)\
+[id] = {\
+	OPP_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn20_opp_registers opp_regs[] = {
+	opp_regs(0),
+	opp_regs(1),
+	opp_regs(2),
+	opp_regs(3)
+};
+
+static const struct dcn20_opp_shift opp_shift = {
+	OPP_MASK_SH_LIST_DCN20(__SHIFT)
+};
+
+static const struct dcn20_opp_mask opp_mask = {
+	OPP_MASK_SH_LIST_DCN20(_MASK)
+};
+
+#define aux_engine_regs(id)\
+[id] = {\
+	AUX_COMMON_REG_LIST0(id), \
+	.AUXN_IMPCAL = 0, \
+	.AUXP_IMPCAL = 0, \
+	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
+}
+
+static const struct dce110_aux_registers aux_engine_regs[] = {
+		aux_engine_regs(0),
+		aux_engine_regs(1),
+		aux_engine_regs(2),
+		aux_engine_regs(3),
+		aux_engine_regs(4)
+};
+
+static const struct dce110_aux_registers_shift aux_shift = {
+	DCN_AUX_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce110_aux_registers_mask aux_mask = {
+	DCN_AUX_MASK_SH_LIST(_MASK)
+};
+
+
+#define dwbc_regs_dcn3(id)\
+[id] = {\
+	DWBC_COMMON_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn30_dwbc_registers dwbc30_regs[] = {
+	dwbc_regs_dcn3(0),
+};
+
+static const struct dcn30_dwbc_shift dwbc30_shift = {
+	DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn30_dwbc_mask dwbc30_mask = {
+	DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define mcif_wb_regs_dcn3(id)\
+[id] = {\
+	MCIF_WB_COMMON_REG_LIST_DCN32(id),\
+}
+
+static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
+	mcif_wb_regs_dcn3(0)
+};
+
+static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
+	MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
+	MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
+};
+
+#define dsc_regsDCN20(id)\
+[id] = {\
+	DSC_REG_LIST_DCN20(id)\
+}
+
+static const struct dcn20_dsc_registers dsc_regs[] = {
+	dsc_regsDCN20(0),
+	dsc_regsDCN20(1),
+	dsc_regsDCN20(2),
+	dsc_regsDCN20(3)
+};
+
+static const struct dcn20_dsc_shift dsc_shift = {
+	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
+};
+
+static const struct dcn20_dsc_mask dsc_mask = {
+	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
+};
+
+static const struct dcn30_mpc_registers mpc_regs = {
+		MPC_REG_LIST_DCN3_0(0),
+		MPC_REG_LIST_DCN3_0(1),
+		MPC_REG_LIST_DCN3_0(2),
+		MPC_REG_LIST_DCN3_0(3),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(2),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(3),
+		MPC_MCM_REG_LIST_DCN32(0),
+		MPC_MCM_REG_LIST_DCN32(1),
+		MPC_MCM_REG_LIST_DCN32(2),
+		MPC_MCM_REG_LIST_DCN32(3),
+		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
+};
+
+static const struct dcn30_mpc_shift mpc_shift = {
+	MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dcn30_mpc_mask mpc_mask = {
+	MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
+};
+
+#define optc_regs(id)\
+[id] = {OPTC_COMMON_REG_LIST_DCN3_2(id)}
+
+static const struct dcn_optc_registers optc_regs[] = {
+	optc_regs(0),
+	optc_regs(1),
+	optc_regs(2),
+	optc_regs(3)
+};
+
+static const struct dcn_optc_shift optc_shift = {
+	OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
+};
+
+static const struct dcn_optc_mask optc_mask = {
+	OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
+};
+
+#define hubp_regs(id)\
+[id] = {\
+	HUBP_REG_LIST_DCN32(id)\
+}
+
+static const struct dcn_hubp2_registers hubp_regs[] = {
+		hubp_regs(0),
+		hubp_regs(1),
+		hubp_regs(2),
+		hubp_regs(3)
+};
+
+
+static const struct dcn_hubp2_shift hubp_shift = {
+		HUBP_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dcn_hubp2_mask hubp_mask = {
+		HUBP_MASK_SH_LIST_DCN32(_MASK)
+};
+static const struct dcn_hubbub_registers hubbub_reg = {
+		HUBBUB_REG_LIST_DCN32(0)
+};
+
+static const struct dcn_hubbub_shift hubbub_shift = {
+		HUBBUB_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dcn_hubbub_mask hubbub_mask = {
+		HUBBUB_MASK_SH_LIST_DCN32(_MASK)
+};
+
+static const struct dccg_registers dccg_regs = {
+		DCCG_REG_LIST_DCN32()
+};
+
+static const struct dccg_shift dccg_shift = {
+		DCCG_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dccg_mask dccg_mask = {
+		DCCG_MASK_SH_LIST_DCN32(_MASK)
+};
+
+
+#define SRII2(reg_name_pre, reg_name_post, id)\
+	.reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
+			## id ## _ ## reg_name_post ## _BASE_IDX) + \
+			reg ## reg_name_pre ## id ## _ ## reg_name_post
+
+
+#define HWSEQ_DCN32_REG_LIST()\
+	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
+	SR(DIO_MEM_PWR_CTRL), \
+	SR(ODM_MEM_PWR_CTRL3), \
+	SR(MMHUBBUB_MEM_PWR_CNTL), \
+	SR(DCCG_GATE_DISABLE_CNTL), \
+	SR(DCCG_GATE_DISABLE_CNTL2), \
+	SR(DCFCLK_CNTL),\
+	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
+	SRII(PIXEL_RATE_CNTL, OTG, 0), \
+	SRII(PIXEL_RATE_CNTL, OTG, 1),\
+	SRII(PIXEL_RATE_CNTL, OTG, 2),\
+	SRII(PIXEL_RATE_CNTL, OTG, 3),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
+	SR(MICROSECOND_TIME_BASE_DIV), \
+	SR(MILLISECOND_TIME_BASE_DIV), \
+	SR(DISPCLK_FREQ_CHANGE_CNTL), \
+	SR(RBBMIF_TIMEOUT_DIS), \
+	SR(RBBMIF_TIMEOUT_DIS_2), \
+	SR(DCHUBBUB_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
+	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
+	SR(MPC_CRC_CTRL), \
+	SR(MPC_CRC_RESULT_GB), \
+	SR(MPC_CRC_RESULT_C), \
+	SR(MPC_CRC_RESULT_AR), \
+	SR(DOMAIN0_PG_CONFIG), \
+	SR(DOMAIN1_PG_CONFIG), \
+	SR(DOMAIN2_PG_CONFIG), \
+	SR(DOMAIN3_PG_CONFIG), \
+	SR(DOMAIN16_PG_CONFIG), \
+	SR(DOMAIN17_PG_CONFIG), \
+	SR(DOMAIN18_PG_CONFIG), \
+	SR(DOMAIN19_PG_CONFIG), \
+	SR(DOMAIN0_PG_STATUS), \
+	SR(DOMAIN1_PG_STATUS), \
+	SR(DOMAIN2_PG_STATUS), \
+	SR(DOMAIN3_PG_STATUS), \
+	SR(DOMAIN16_PG_STATUS), \
+	SR(DOMAIN17_PG_STATUS), \
+	SR(DOMAIN18_PG_STATUS), \
+	SR(DOMAIN19_PG_STATUS), \
+	SR(D1VGA_CONTROL), \
+	SR(D2VGA_CONTROL), \
+	SR(D3VGA_CONTROL), \
+	SR(D4VGA_CONTROL), \
+	SR(D5VGA_CONTROL), \
+	SR(D6VGA_CONTROL), \
+	SR(DC_IP_REQUEST_CNTL), \
+	SR(AZALIA_AUDIO_DTO), \
+	SR(AZALIA_CONTROLLER_CLOCK_GATING)
+
+static const struct dce_hwseq_registers hwseq_reg = {
+		HWSEQ_DCN32_REG_LIST()
+};
+
+#define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\
+	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
+	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
+	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
+	HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
+	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
+	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
+	HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
+
+static const struct dce_hwseq_shift hwseq_shift = {
+		HWSEQ_DCN32_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_hwseq_mask hwseq_mask = {
+		HWSEQ_DCN32_MASK_SH_LIST(_MASK)
+};
+#define vmid_regs(id)\
+[id] = {\
+		DCN20_VMID_REG_LIST(id)\
+}
+
+static const struct dcn_vmid_registers vmid_regs[] = {
+	vmid_regs(0),
+	vmid_regs(1),
+	vmid_regs(2),
+	vmid_regs(3),
+	vmid_regs(4),
+	vmid_regs(5),
+	vmid_regs(6),
+	vmid_regs(7),
+	vmid_regs(8),
+	vmid_regs(9),
+	vmid_regs(10),
+	vmid_regs(11),
+	vmid_regs(12),
+	vmid_regs(13),
+	vmid_regs(14),
+	vmid_regs(15)
+};
+
+static const struct dcn20_vmid_shift vmid_shifts = {
+		DCN20_VMID_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn20_vmid_mask vmid_masks = {
+		DCN20_VMID_MASK_SH_LIST(_MASK)
+};
+
+static const struct resource_caps res_cap_dcn321 = {
+	.num_timing_generator = 4,
+	.num_opp = 4,
+	.num_video_plane = 4,
+	.num_audio = 5,
+	.num_stream_encoder = 5,
+	.num_hpo_dp_stream_encoder = 4,
+	.num_hpo_dp_link_encoder = 2,
+	.num_pll = 5,
+	.num_dwb = 1,
+	.num_ddc = 5,
+	.num_vmid = 16,
+	.num_mpc_3dlut = 4,
+	.num_dsc = 4,
+};
+
+static const struct dc_plane_cap plane_cap = {
+	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
+	.blends_with_above = true,
+	.blends_with_below = true,
+	.per_pixel_alpha = true,
+
+	.pixel_format_support = {
+			.argb8888 = true,
+			.nv12 = true,
+			.fp16 = true,
+			.p010 = true,
+			.ayuv = false,
+	},
+
+	.max_upscale_factor = {
+			.argb8888 = 16000,
+			.nv12 = 16000,
+			.fp16 = 16000
+	},
+
+	// 6:1 downscaling ratio: 1000/6 = 166.666
+	.max_downscale_factor = {
+			.argb8888 = 167,
+			.nv12 = 167,
+			.fp16 = 167
+	},
+	64,
+	64
+};
+
+static const struct dc_debug_options debug_defaults_drv = {
+	.disable_dmcu = true,
+	.force_abm_enable = false,
+	.timing_trace = false,
+	.clock_trace = true,
+	.disable_pplib_clock_request = false,
+	.pipe_split_policy = MPC_SPLIT_DYNAMIC,
+	.force_single_disp_pipe_split = false,
+	.disable_dcc = DCC_ENABLE,
+	.vsr_support = true,
+	.performance_trace = false,
+	.max_downscale_src_width = 7680,/*upto 8K*/
+	.disable_pplib_wm_range = false,
+	.scl_reset_length10 = true,
+	.sanity_checks = false,
+	.underflow_assert_delay_us = 0xFFFFFFFF,
+	.dwb_fi_phase = -1, // -1 = disable,
+	.dmub_command_table = true,
+	.enable_mem_low_power = {
+		.bits = {
+			.vga = false,
+			.i2c = false,
+			.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
+			.dscl = false,
+			.cm = false,
+			.mpc = false,
+			.optc = false,
+		}
+	},
+	.use_max_lb = true,
+	.force_disable_subvp = true
+};
+
+static const struct dc_debug_options debug_defaults_diags = {
+	.disable_dmcu = true,
+	.force_abm_enable = false,
+	.timing_trace = true,
+	.clock_trace = true,
+	.disable_dpp_power_gate = true,
+	.disable_hubp_power_gate = true,
+	.disable_dsc_power_gate = true,
+	.disable_clock_gate = true,
+	.disable_pplib_clock_request = true,
+	.disable_pplib_wm_range = true,
+	.disable_stutter = false,
+	.scl_reset_length10 = true,
+	.dwb_fi_phase = -1, // -1 = disable
+	.dmub_command_table = true,
+	.enable_tri_buf = true,
+	.use_max_lb = true,
+	.force_disable_subvp = true
+};
+
+
+static struct dce_aux *dcn321_aux_engine_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct aux_engine_dce110 *aux_engine =
+		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
+
+	if (!aux_engine)
+		return NULL;
+
+	dce110_aux_engine_construct(aux_engine, ctx, inst,
+				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+				    &aux_engine_regs[inst],
+					&aux_mask,
+					&aux_shift,
+					ctx->dc->caps.extended_aux_timeout_support);
+
+	return &aux_engine->base;
+}
+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
+
+static const struct dce_i2c_registers i2c_hw_regs[] = {
+		i2c_inst_regs(1),
+		i2c_inst_regs(2),
+		i2c_inst_regs(3),
+		i2c_inst_regs(4),
+		i2c_inst_regs(5),
+};
+
+static const struct dce_i2c_shift i2c_shifts = {
+		I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dce_i2c_mask i2c_masks = {
+		I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+static struct dce_i2c_hw *dcn321_i2c_hw_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dce_i2c_hw *dce_i2c_hw =
+		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
+
+	if (!dce_i2c_hw)
+		return NULL;
+
+	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
+				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
+
+	return dce_i2c_hw;
+}
+
+static struct clock_source *dcn321_clock_source_create(
+		struct dc_context *ctx,
+		struct dc_bios *bios,
+		enum clock_source_id id,
+		const struct dce110_clk_src_regs *regs,
+		bool dp_clk_src)
+{
+	struct dce110_clk_src *clk_src =
+		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
+
+	if (!clk_src)
+		return NULL;
+
+	if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
+			regs, &cs_shift, &cs_mask)) {
+		clk_src->base.dp_clk_src = dp_clk_src;
+		return &clk_src->base;
+	}
+
+	BREAK_TO_DEBUGGER();
+	return NULL;
+}
+
+static struct hubbub *dcn321_hubbub_create(struct dc_context *ctx)
+{
+	int i;
+
+	struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub),
+					  GFP_KERNEL);
+
+	if (!hubbub2)
+		return NULL;
+
+	hubbub32_construct(hubbub2, ctx,
+			&hubbub_reg,
+			&hubbub_shift,
+			&hubbub_mask,
+			ctx->dc->dml.ip.det_buffer_size_kbytes,
+			ctx->dc->dml.ip.pixel_chunk_size_kbytes,
+			ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);
+
+
+	for (i = 0; i < res_cap_dcn321.num_vmid; i++) {
+		struct dcn20_vmid *vmid = &hubbub2->vmid[i];
+
+		vmid->ctx = ctx;
+
+		vmid->regs = &vmid_regs[i];
+		vmid->shifts = &vmid_shifts;
+		vmid->masks = &vmid_masks;
+	}
+
+	return &hubbub2->base;
+}
+
+static struct hubp *dcn321_hubp_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn20_hubp *hubp2 =
+		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
+
+	if (!hubp2)
+		return NULL;
+
+	if (hubp32_construct(hubp2, ctx, inst,
+			&hubp_regs[inst], &hubp_shift, &hubp_mask))
+		return &hubp2->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(hubp2);
+	return NULL;
+}
+
+static void dcn321_dpp_destroy(struct dpp **dpp)
+{
+	kfree(TO_DCN30_DPP(*dpp));
+	*dpp = NULL;
+}
+
+static struct dpp *dcn321_dpp_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn3_dpp *dpp3 =
+		kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
+
+	if (!dpp3)
+		return NULL;
+
+	if (dpp32_construct(dpp3, ctx, inst,
+			&dpp_regs[inst], &tf_shift, &tf_mask))
+		return &dpp3->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(dpp3);
+	return NULL;
+}
+
+static struct mpc *dcn321_mpc_create(
+		struct dc_context *ctx,
+		int num_mpcc,
+		int num_rmu)
+{
+	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
+					  GFP_KERNEL);
+
+	if (!mpc30)
+		return NULL;
+
+	dcn32_mpc_construct(mpc30, ctx,
+			&mpc_regs,
+			&mpc_shift,
+			&mpc_mask,
+			num_mpcc,
+			num_rmu);
+
+	return &mpc30->base;
+}
+
+static struct output_pixel_processor *dcn321_opp_create(
+	struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn20_opp *opp2 =
+		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
+
+	if (!opp2) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	dcn20_opp_construct(opp2, ctx, inst,
+			&opp_regs[inst], &opp_shift, &opp_mask);
+	return &opp2->base;
+}
+
+
+static struct timing_generator *dcn321_timing_generator_create(
+		struct dc_context *ctx,
+		uint32_t instance)
+{
+	struct optc *tgn10 =
+		kzalloc(sizeof(struct optc), GFP_KERNEL);
+
+	if (!tgn10)
+		return NULL;
+
+	tgn10->base.inst = instance;
+	tgn10->base.ctx = ctx;
+
+	tgn10->tg_regs = &optc_regs[instance];
+	tgn10->tg_shift = &optc_shift;
+	tgn10->tg_mask = &optc_mask;
+
+	dcn32_timing_generator_init(tgn10);
+
+	return &tgn10->base;
+}
+
+static const struct encoder_feature_support link_enc_feature = {
+		.max_hdmi_deep_color = COLOR_DEPTH_121212,
+		.max_hdmi_pixel_clock = 600000,
+		.hdmi_ycbcr420_supported = true,
+		.dp_ycbcr420_supported = true,
+		.fec_supported = true,
+		.flags.bits.IS_HBR2_CAPABLE = true,
+		.flags.bits.IS_HBR3_CAPABLE = true,
+		.flags.bits.IS_TPS3_CAPABLE = true,
+		.flags.bits.IS_TPS4_CAPABLE = true
+};
+
+static struct link_encoder *dcn321_link_encoder_create(
+	const struct encoder_init_data *enc_init_data)
+{
+	struct dcn20_link_encoder *enc20 =
+		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
+
+	if (!enc20)
+		return NULL;
+
+	dcn32_link_encoder_construct(enc20,
+			enc_init_data,
+			&link_enc_feature,
+			&link_enc_regs[enc_init_data->transmitter],
+			&link_enc_aux_regs[enc_init_data->channel - 1],
+			&link_enc_hpd_regs[enc_init_data->hpd_source],
+			&le_shift,
+			&le_mask);
+
+	return &enc20->enc10.base;
+}
+
+static void read_dce_straps(
+	struct dc_context *ctx,
+	struct resource_straps *straps)
+{
+	generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
+		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
+
+}
+
+static struct audio *dcn321_create_audio(
+		struct dc_context *ctx, unsigned int inst)
+{
+	return dce_audio_create(ctx, inst,
+			&audio_regs[inst], &audio_shift, &audio_mask);
+}
+
+static struct vpg *dcn321_vpg_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
+
+	if (!vpg3)
+		return NULL;
+
+	vpg3_construct(vpg3, ctx, inst,
+			&vpg_regs[inst],
+			&vpg_shift,
+			&vpg_mask);
+
+	return &vpg3->base;
+}
+
+static struct afmt *dcn321_afmt_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
+
+	if (!afmt3)
+		return NULL;
+
+	afmt3_construct(afmt3, ctx, inst,
+			&afmt_regs[inst],
+			&afmt_shift,
+			&afmt_mask);
+
+	return &afmt3->base;
+}
+
+static struct apg *dcn321_apg_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
+
+	if (!apg31)
+		return NULL;
+
+	apg31_construct(apg31, ctx, inst,
+			&apg_regs[inst],
+			&apg_shift,
+			&apg_mask);
+
+	return &apg31->base;
+}
+
+static struct stream_encoder *dcn321_stream_encoder_create(
+	enum engine_id eng_id,
+	struct dc_context *ctx)
+{
+	struct dcn10_stream_encoder *enc1;
+	struct vpg *vpg;
+	struct afmt *afmt;
+	int vpg_inst;
+	int afmt_inst;
+
+	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
+	if (eng_id <= ENGINE_ID_DIGF) {
+		vpg_inst = eng_id;
+		afmt_inst = eng_id;
+	} else
+		return NULL;
+
+	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
+	vpg = dcn321_vpg_create(ctx, vpg_inst);
+	afmt = dcn321_afmt_create(ctx, afmt_inst);
+
+	if (!enc1 || !vpg || !afmt) {
+		kfree(enc1);
+		kfree(vpg);
+		kfree(afmt);
+		return NULL;
+	}
+
+	dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
+					eng_id, vpg, afmt,
+					&stream_enc_regs[eng_id],
+					&se_shift, &se_mask);
+
+	return &enc1->base;
+}
+
+static struct hpo_dp_stream_encoder *dcn321_hpo_dp_stream_encoder_create(
+	enum engine_id eng_id,
+	struct dc_context *ctx)
+{
+	struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
+	struct vpg *vpg;
+	struct apg *apg;
+	uint32_t hpo_dp_inst;
+	uint32_t vpg_inst;
+	uint32_t apg_inst;
+
+	ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
+	hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
+
+	/* Mapping of VPG register blocks to HPO DP block instance:
+	 * VPG[6] -> HPO_DP[0]
+	 * VPG[7] -> HPO_DP[1]
+	 * VPG[8] -> HPO_DP[2]
+	 * VPG[9] -> HPO_DP[3]
+	 */
+	vpg_inst = hpo_dp_inst + 6;
+
+	/* Mapping of APG register blocks to HPO DP block instance:
+	 * APG[0] -> HPO_DP[0]
+	 * APG[1] -> HPO_DP[1]
+	 * APG[2] -> HPO_DP[2]
+	 * APG[3] -> HPO_DP[3]
+	 */
+	apg_inst = hpo_dp_inst;
+
+	/* allocate HPO stream encoder and create VPG sub-block */
+	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
+	vpg = dcn321_vpg_create(ctx, vpg_inst);
+	apg = dcn321_apg_create(ctx, apg_inst);
+
+	if (!hpo_dp_enc31 || !vpg || !apg) {
+		kfree(hpo_dp_enc31);
+		kfree(vpg);
+		kfree(apg);
+		return NULL;
+	}
+
+	dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
+					hpo_dp_inst, eng_id, vpg, apg,
+					&hpo_dp_stream_enc_regs[hpo_dp_inst],
+					&hpo_dp_se_shift, &hpo_dp_se_mask);
+
+	return &hpo_dp_enc31->base;
+}
+
+static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create(
+	uint8_t inst,
+	struct dc_context *ctx)
+{
+	struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
+
+	/* allocate HPO link encoder */
+	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
+
+	hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
+					&hpo_dp_link_enc_regs[inst],
+					&hpo_dp_le_shift, &hpo_dp_le_mask);
+
+	return &hpo_dp_enc31->base;
+}
+
+static struct dce_hwseq *dcn321_hwseq_create(
+	struct dc_context *ctx)
+{
+	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
+
+	if (hws) {
+		hws->ctx = ctx;
+		hws->regs = &hwseq_reg;
+		hws->shifts = &hwseq_shift;
+		hws->masks = &hwseq_mask;
+	}
+	return hws;
+}
+static const struct resource_create_funcs res_create_funcs = {
+	.read_dce_straps = read_dce_straps,
+	.create_audio = dcn321_create_audio,
+	.create_stream_encoder = dcn321_stream_encoder_create,
+	.create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create,
+	.create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create,
+	.create_hwseq = dcn321_hwseq_create,
+};
+
+static const struct resource_create_funcs res_create_maximus_funcs = {
+	.read_dce_straps = NULL,
+	.create_audio = NULL,
+	.create_stream_encoder = NULL,
+	.create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create,
+	.create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create,
+	.create_hwseq = dcn321_hwseq_create,
+};
+
+static void dcn321_resource_destruct(struct dcn321_resource_pool *pool)
+{
+	unsigned int i;
+
+	for (i = 0; i < pool->base.stream_enc_count; i++) {
+		if (pool->base.stream_enc[i] != NULL) {
+			if (pool->base.stream_enc[i]->vpg != NULL) {
+				kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
+				pool->base.stream_enc[i]->vpg = NULL;
+			}
+			if (pool->base.stream_enc[i]->afmt != NULL) {
+				kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
+				pool->base.stream_enc[i]->afmt = NULL;
+			}
+			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
+			pool->base.stream_enc[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
+		if (pool->base.hpo_dp_stream_enc[i] != NULL) {
+			if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
+				kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
+				pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
+			}
+			if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
+				kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
+				pool->base.hpo_dp_stream_enc[i]->apg = NULL;
+			}
+			kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
+			pool->base.hpo_dp_stream_enc[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
+		if (pool->base.hpo_dp_link_enc[i] != NULL) {
+			kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
+			pool->base.hpo_dp_link_enc[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+		if (pool->base.dscs[i] != NULL)
+			dcn20_dsc_destroy(&pool->base.dscs[i]);
+	}
+
+	if (pool->base.mpc != NULL) {
+		kfree(TO_DCN20_MPC(pool->base.mpc));
+		pool->base.mpc = NULL;
+	}
+	if (pool->base.hubbub != NULL) {
+		kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
+		pool->base.hubbub = NULL;
+	}
+	for (i = 0; i < pool->base.pipe_count; i++) {
+		if (pool->base.dpps[i] != NULL)
+			dcn321_dpp_destroy(&pool->base.dpps[i]);
+
+		if (pool->base.ipps[i] != NULL)
+			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
+
+		if (pool->base.hubps[i] != NULL) {
+			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
+			pool->base.hubps[i] = NULL;
+		}
+
+		if (pool->base.irqs != NULL) {
+			dal_irq_service_destroy(&pool->base.irqs);
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+		if (pool->base.engines[i] != NULL)
+			dce110_engine_destroy(&pool->base.engines[i]);
+		if (pool->base.hw_i2cs[i] != NULL) {
+			kfree(pool->base.hw_i2cs[i]);
+			pool->base.hw_i2cs[i] = NULL;
+		}
+		if (pool->base.sw_i2cs[i] != NULL) {
+			kfree(pool->base.sw_i2cs[i]);
+			pool->base.sw_i2cs[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+		if (pool->base.opps[i] != NULL)
+			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+		if (pool->base.timing_generators[i] != NULL)	{
+			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
+			pool->base.timing_generators[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+		if (pool->base.dwbc[i] != NULL) {
+			kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
+			pool->base.dwbc[i] = NULL;
+		}
+		if (pool->base.mcif_wb[i] != NULL) {
+			kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
+			pool->base.mcif_wb[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.audio_count; i++) {
+		if (pool->base.audios[i])
+			dce_aud_destroy(&pool->base.audios[i]);
+	}
+
+	for (i = 0; i < pool->base.clk_src_count; i++) {
+		if (pool->base.clock_sources[i] != NULL) {
+			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
+			pool->base.clock_sources[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+		if (pool->base.mpc_lut[i] != NULL) {
+			dc_3dlut_func_release(pool->base.mpc_lut[i]);
+			pool->base.mpc_lut[i] = NULL;
+		}
+		if (pool->base.mpc_shaper[i] != NULL) {
+			dc_transfer_func_release(pool->base.mpc_shaper[i]);
+			pool->base.mpc_shaper[i] = NULL;
+		}
+	}
+
+	if (pool->base.dp_clock_source != NULL) {
+		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
+		pool->base.dp_clock_source = NULL;
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+		if (pool->base.multiple_abms[i] != NULL)
+			dce_abm_destroy(&pool->base.multiple_abms[i]);
+	}
+
+	if (pool->base.psr != NULL)
+		dmub_psr_destroy(&pool->base.psr);
+
+	if (pool->base.dccg != NULL)
+		dcn_dccg_destroy(&pool->base.dccg);
+
+	if (pool->base.oem_device != NULL)
+		dal_ddc_service_destroy(&pool->base.oem_device);
+}
+
+
+static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+	int i;
+	uint32_t dwb_count = pool->res_cap->num_dwb;
+
+	for (i = 0; i < dwb_count; i++) {
+		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
+						    GFP_KERNEL);
+
+		if (!dwbc30) {
+			dm_error("DC: failed to create dwbc30!\n");
+			return false;
+		}
+
+		dcn30_dwbc_construct(dwbc30, ctx,
+				&dwbc30_regs[i],
+				&dwbc30_shift,
+				&dwbc30_mask,
+				i);
+
+		pool->dwbc[i] = &dwbc30->base;
+	}
+	return true;
+}
+
+static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+	int i;
+	uint32_t dwb_count = pool->res_cap->num_dwb;
+
+	for (i = 0; i < dwb_count; i++) {
+		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
+						    GFP_KERNEL);
+
+		if (!mcif_wb30) {
+			dm_error("DC: failed to create mcif_wb30!\n");
+			return false;
+		}
+
+		dcn32_mmhubbub_construct(mcif_wb30, ctx,
+				&mcif_wb30_regs[i],
+				&mcif_wb30_shift,
+				&mcif_wb30_mask,
+				i);
+
+		pool->mcif_wb[i] = &mcif_wb30->base;
+	}
+	return true;
+}
+
+static struct display_stream_compressor *dcn321_dsc_create(
+	struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn20_dsc *dsc =
+		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
+
+	if (!dsc) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
+	return &dsc->base;
+}
+
+static void dcn321_destroy_resource_pool(struct resource_pool **pool)
+{
+	struct dcn321_resource_pool *dcn321_pool = TO_DCN321_RES_POOL(*pool);
+
+	dcn321_resource_destruct(dcn321_pool);
+	kfree(dcn321_pool);
+	*pool = NULL;
+}
+
+static struct dc_cap_funcs cap_funcs = {
+	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
+};
+
+
+static void dcn321_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
+		unsigned int *optimal_dcfclk,
+		unsigned int *optimal_fclk)
+{
+	double bw_from_dram, bw_from_dram1, bw_from_dram2;
+
+	bw_from_dram1 = uclk_mts * dcn3_21_soc.num_chans *
+		dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_dram_bw_use_normal_percent / 100);
+	bw_from_dram2 = uclk_mts * dcn3_21_soc.num_chans *
+		dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100);
+
+	bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
+
+	if (optimal_fclk)
+		*optimal_fclk = bw_from_dram /
+		(dcn3_21_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100));
+
+	if (optimal_dcfclk)
+		*optimal_dcfclk =  bw_from_dram /
+		(dcn3_21_soc.return_bus_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100));
+}
+
+/* dcn321_update_bw_bounding_box
+ * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from spreadsheet
+ * with actual values as per dGPU SKU:
+ * -with passed few options from dc->config
+ * -with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might need to get it from PM FW)
+ * -with passed latency values (passed in ns units) in dc-> bb override for debugging purposes
+ * -with passed latencies from VBIOS (in 100_ns units) if available for certain dGPU SKU
+ * -with number of DRAM channels from VBIOS (which differ for certain dGPU SKU of the same ASIC)
+ * -clocks levels with passed clk_table entries from Clk Mgr as reported by PM FW for different
+ *  clocks (which might differ for certain dGPU SKU of the same ASIC)
+ */
+static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
+{
+	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+		/* Overrides from dc->config options */
+		dcn3_21_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
+
+		/* Override from passed dc->bb_overrides if available*/
+		if ((int)(dcn3_21_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
+				&& dc->bb_overrides.sr_exit_time_ns) {
+			dcn3_21_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
+		}
+
+		if ((int)(dcn3_21_soc.sr_enter_plus_exit_time_us * 1000)
+				!= dc->bb_overrides.sr_enter_plus_exit_time_ns
+				&& dc->bb_overrides.sr_enter_plus_exit_time_ns) {
+			dcn3_21_soc.sr_enter_plus_exit_time_us =
+				dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
+		}
+
+		if ((int)(dcn3_21_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
+			&& dc->bb_overrides.urgent_latency_ns) {
+			dcn3_21_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
+		}
+
+		if ((int)(dcn3_21_soc.dram_clock_change_latency_us * 1000)
+				!= dc->bb_overrides.dram_clock_change_latency_ns
+				&& dc->bb_overrides.dram_clock_change_latency_ns) {
+			dcn3_21_soc.dram_clock_change_latency_us =
+				dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
+		}
+
+		if ((int)(dcn3_21_soc.dummy_pstate_latency_us * 1000)
+				!= dc->bb_overrides.dummy_clock_change_latency_ns
+				&& dc->bb_overrides.dummy_clock_change_latency_ns) {
+			dcn3_21_soc.dummy_pstate_latency_us =
+				dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
+		}
+
+		/* Override from VBIOS if VBIOS bb_info available */
+		if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
+			struct bp_soc_bb_info bb_info = {0};
+
+			if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
+				if (bb_info.dram_clock_change_latency_100ns > 0)
+					dcn3_21_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
+
+			if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
+				dcn3_21_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
+
+			if (bb_info.dram_sr_exit_latency_100ns > 0)
+				dcn3_21_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
+			}
+		}
+
+		/* Override from VBIOS for num_chan */
+		if (dc->ctx->dc_bios->vram_info.num_chans)
+			dcn3_21_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
+
+		if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
+			dcn3_21_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
+
+	}
+
+	/* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
+	dcn3_21_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
+	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
+
+	/* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */
+	if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) {
+		unsigned int i = 0, j = 0, num_states = 0;
+
+		unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
+		unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
+		unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
+		unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
+
+		unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564};
+		unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0;
+		unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
+
+		for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
+			if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
+				max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
+			if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
+				max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
+			if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
+				max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
+			if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
+				max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
+		}
+		if (!max_dcfclk_mhz)
+			max_dcfclk_mhz = dcn3_21_soc.clock_limits[0].dcfclk_mhz;
+		if (!max_dispclk_mhz)
+			max_dispclk_mhz = dcn3_21_soc.clock_limits[0].dispclk_mhz;
+		if (!max_dppclk_mhz)
+			max_dppclk_mhz = dcn3_21_soc.clock_limits[0].dppclk_mhz;
+		if (!max_phyclk_mhz)
+			max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz;
+
+		if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
+			// If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
+			dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
+			num_dcfclk_sta_targets++;
+		} else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
+			// If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
+			for (i = 0; i < num_dcfclk_sta_targets; i++) {
+				if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
+					dcfclk_sta_targets[i] = max_dcfclk_mhz;
+					break;
+				}
+			}
+			// Update size of array since we "removed" duplicates
+			num_dcfclk_sta_targets = i + 1;
+		}
+
+		num_uclk_states = bw_params->clk_table.num_entries;
+
+		// Calculate optimal dcfclk for each uclk
+		for (i = 0; i < num_uclk_states; i++) {
+			dcn321_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
+					&optimal_dcfclk_for_uclk[i], NULL);
+			if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
+				optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
+			}
+		}
+
+		// Calculate optimal uclk for each dcfclk sta target
+		for (i = 0; i < num_dcfclk_sta_targets; i++) {
+			for (j = 0; j < num_uclk_states; j++) {
+				if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
+					optimal_uclk_for_dcfclk_sta_targets[i] =
+							bw_params->clk_table.entries[j].memclk_mhz * 16;
+					break;
+				}
+			}
+		}
+
+		i = 0;
+		j = 0;
+		// create the final dcfclk and uclk table
+		while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
+			if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
+				dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
+				dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
+			} else {
+				if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
+					dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
+					dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
+				} else {
+					j = num_uclk_states;
+				}
+			}
+		}
+
+		while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
+			dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
+			dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
+		}
+
+		while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
+				optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
+			dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
+			dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
+		}
+
+		dcn3_21_soc.num_states = num_states;
+		for (i = 0; i < dcn3_21_soc.num_states; i++) {
+			dcn3_21_soc.clock_limits[i].state = i;
+			dcn3_21_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
+			dcn3_21_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
+			dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
+
+			/* Fill all states with max values of all these clocks */
+			dcn3_21_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
+			dcn3_21_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
+			dcn3_21_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
+			dcn3_21_soc.clock_limits[i].dscclk_mhz  = max_dispclk_mhz / 3;
+
+			/* Populate from bw_params for DTBCLK, SOCCLK */
+			if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0)
+				dcn3_21_soc.clock_limits[i].dtbclk_mhz  = dcn3_21_soc.clock_limits[i-1].dtbclk_mhz;
+			else
+				dcn3_21_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
+
+			if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
+				dcn3_21_soc.clock_limits[i].socclk_mhz = dcn3_21_soc.clock_limits[i-1].socclk_mhz;
+			else
+				dcn3_21_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
+
+			/* These clocks cannot come from bw_params, always fill from dcn3_21_soc[0] */
+			/* PHYCLK_D18, PHYCLK_D32 */
+			dcn3_21_soc.clock_limits[i].phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz;
+			dcn3_21_soc.clock_limits[i].phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz;
+		}
+
+		/* Re-init DML with updated bb */
+		dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
+		if (dc->current_state)
+			dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
+	}
+}
+
+static struct resource_funcs dcn321_res_pool_funcs = {
+	.destroy = dcn321_destroy_resource_pool,
+	.link_enc_create = dcn321_link_encoder_create,
+	.link_enc_create_minimal = NULL,
+	.panel_cntl_create = dcn32_panel_cntl_create,
+	.validate_bandwidth = dcn32_validate_bandwidth,
+	.calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,
+	.populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
+	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
+	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
+	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
+	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
+	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
+	.set_mcif_arb_params = dcn30_set_mcif_arb_params,
+	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
+	.acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
+	.release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
+	.update_bw_bounding_box = dcn321_update_bw_bounding_box,
+	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
+	.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
+	.add_phantom_pipes = dcn32_add_phantom_pipes,
+	.remove_phantom_pipes = dcn32_remove_phantom_pipes,
+};
+
+
+static bool dcn321_resource_construct(
+	uint8_t num_virtual_links,
+	struct dc *dc,
+	struct dcn321_resource_pool *pool)
+{
+	int i, j;
+	struct dc_context *ctx = dc->ctx;
+	struct irq_service_init_data init_data;
+	struct ddc_service_init_data ddc_init_data = {0};
+	uint32_t pipe_fuses = 0;
+	uint32_t num_pipes  = 4;
+
+	ctx->dc_bios->regs = &bios_regs;
+
+	pool->base.res_cap = &res_cap_dcn321;
+	/* max number of pipes for ASIC before checking for pipe fuses */
+	num_pipes  = pool->base.res_cap->num_timing_generator;
+	pipe_fuses = REG_READ(CC_DC_PIPE_DIS);
+
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
+		if (pipe_fuses & 1 << i)
+			num_pipes--;
+
+	if (pipe_fuses & 1)
+		ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
+
+	if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
+		ASSERT(0); //Entire DCN is harvested!
+
+	/* within dml lib, initial value is hard coded, if ASIC pipe is fused, the
+	 * value will be changed, update max_num_dpp and max_num_otg for dml.
+	 */
+	dcn3_21_ip.max_num_dpp = num_pipes;
+	dcn3_21_ip.max_num_otg = num_pipes;
+
+	pool->base.funcs = &dcn321_res_pool_funcs;
+
+	/*************************************************
+	 *  Resource + asic cap harcoding                *
+	 *************************************************/
+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+	pool->base.timing_generator_count = num_pipes;
+	pool->base.pipe_count = num_pipes;
+	pool->base.mpcc_count = num_pipes;
+	dc->caps.max_downscale_ratio = 600;
+	dc->caps.i2c_speed_in_khz = 100;
+	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/
+	dc->caps.max_cursor_size = 256;
+	dc->caps.min_horizontal_blanking_period = 80;
+	dc->caps.dmdata_alloc_size = 2048;
+	dc->caps.mall_size_per_mem_channel = 0;
+	dc->caps.mall_size_total = 0;
+	dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
+	dc->caps.cache_line_size = 64;
+	dc->caps.cache_num_ways = 16;
+	dc->caps.max_cab_allocation_bytes = 33554432; // 32MB = 1024 * 1024 * 32
+	dc->caps.subvp_fw_processing_delay_us = 15;
+	dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
+	dc->caps.subvp_pstate_allow_width_us = 20;
+
+	dc->caps.max_slave_planes = 1;
+	dc->caps.max_slave_yuv_planes = 1;
+	dc->caps.max_slave_rgb_planes = 1;
+	dc->caps.post_blend_color_processing = true;
+	dc->caps.force_dp_tps4_for_cp2520 = true;
+	dc->caps.dp_hpo = true;
+	dc->caps.edp_dsc_support = true;
+	dc->caps.extended_aux_timeout_support = true;
+	dc->caps.dmcub_support = true;
+
+	/* Color pipeline capabilities */
+	dc->caps.color.dpp.dcn_arch = 1;
+	dc->caps.color.dpp.input_lut_shared = 0;
+	dc->caps.color.dpp.icsc = 1;
+	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
+	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
+	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
+	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
+	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
+	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
+	dc->caps.color.dpp.post_csc = 1;
+	dc->caps.color.dpp.gamma_corr = 1;
+	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
+
+	dc->caps.color.dpp.hw_3d_lut = 0; //3DLUT removed from DPP
+	dc->caps.color.dpp.ogam_ram = 0;  //Blnd Gam also removed
+	// no OGAM ROM on DCN2 and later ASICs
+	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
+	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
+	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
+	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
+	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
+	dc->caps.color.dpp.ocsc = 0;
+
+	dc->caps.color.mpc.gamut_remap = 1;
+	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
+	dc->caps.color.mpc.ogam_ram = 1;
+	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
+	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
+	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
+	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
+	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
+	dc->caps.color.mpc.ocsc = 1;
+
+	/* read VBIOS LTTPR caps */
+	{
+		if (ctx->dc_bios->funcs->get_lttpr_caps) {
+			enum bp_result bp_query_result;
+			uint8_t is_vbios_lttpr_enable = 0;
+
+			bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
+			dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
+		}
+
+		/* interop bit is implicit */
+		{
+			dc->caps.vbios_lttpr_aware = true;
+		}
+	}
+
+	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
+		dc->debug = debug_defaults_drv;
+	else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
+		dc->debug = debug_defaults_diags;
+	} else
+		dc->debug = debug_defaults_diags;
+	// Init the vm_helper
+	if (dc->vm_helper)
+		vm_helper_init(dc->vm_helper, 16);
+
+	/*************************************************
+	 *  Create resources                             *
+	 *************************************************/
+
+	/* Clock Sources for Pixel Clock*/
+	pool->base.clock_sources[DCN321_CLK_SRC_PLL0] =
+			dcn321_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL0,
+				&clk_src_regs[0], false);
+	pool->base.clock_sources[DCN321_CLK_SRC_PLL1] =
+			dcn321_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL1,
+				&clk_src_regs[1], false);
+	pool->base.clock_sources[DCN321_CLK_SRC_PLL2] =
+			dcn321_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL2,
+				&clk_src_regs[2], false);
+	pool->base.clock_sources[DCN321_CLK_SRC_PLL3] =
+			dcn321_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL3,
+				&clk_src_regs[3], false);
+	pool->base.clock_sources[DCN321_CLK_SRC_PLL4] =
+			dcn321_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL4,
+				&clk_src_regs[4], false);
+
+	pool->base.clk_src_count = DCN321_CLK_SRC_TOTAL;
+
+	/* todo: not reuse phy_pll registers */
+	pool->base.dp_clock_source =
+			dcn321_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_ID_DP_DTO,
+				&clk_src_regs[0], true);
+
+	for (i = 0; i < pool->base.clk_src_count; i++) {
+		if (pool->base.clock_sources[i] == NULL) {
+			dm_error("DC: failed to create clock sources!\n");
+			BREAK_TO_DEBUGGER();
+			goto create_fail;
+		}
+	}
+
+	/* DCCG */
+	pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
+	if (pool->base.dccg == NULL) {
+		dm_error("DC: failed to create dccg!\n");
+		BREAK_TO_DEBUGGER();
+		goto create_fail;
+	}
+
+	/* DML */
+	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
+		dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
+
+	/* IRQ Service */
+	init_data.ctx = dc->ctx;
+	pool->base.irqs = dal_irq_service_dcn32_create(&init_data);
+	if (!pool->base.irqs)
+		goto create_fail;
+
+	/* HUBBUB */
+	pool->base.hubbub = dcn321_hubbub_create(ctx);
+	if (pool->base.hubbub == NULL) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create hubbub!\n");
+		goto create_fail;
+	}
+
+	/* HUBPs, DPPs, OPPs, TGs, ABMs */
+	for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+
+		/* if pipe is disabled, skip instance of HW pipe,
+		 * i.e, skip ASIC register instance
+		 */
+		if (pipe_fuses & 1 << i)
+			continue;
+
+		pool->base.hubps[j] = dcn321_hubp_create(ctx, i);
+		if (pool->base.hubps[j] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC: failed to create hubps!\n");
+			goto create_fail;
+		}
+
+		pool->base.dpps[j] = dcn321_dpp_create(ctx, i);
+		if (pool->base.dpps[j] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC: failed to create dpps!\n");
+			goto create_fail;
+		}
+
+		pool->base.opps[j] = dcn321_opp_create(ctx, i);
+		if (pool->base.opps[j] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC: failed to create output pixel processor!\n");
+			goto create_fail;
+		}
+
+		pool->base.timing_generators[j] = dcn321_timing_generator_create(
+				ctx, i);
+		if (pool->base.timing_generators[j] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create tg!\n");
+			goto create_fail;
+		}
+
+		pool->base.multiple_abms[j] = dmub_abm_create(ctx,
+				&abm_regs[i],
+				&abm_shift,
+				&abm_mask);
+		if (pool->base.multiple_abms[j] == NULL) {
+			dm_error("DC: failed to create abm for pipe %d!\n", i);
+			BREAK_TO_DEBUGGER();
+			goto create_fail;
+		}
+
+		/* index for resource pool arrays for next valid pipe */
+		j++;
+	}
+
+	/* PSR */
+	pool->base.psr = dmub_psr_create(ctx);
+	if (pool->base.psr == NULL) {
+		dm_error("DC: failed to create psr obj!\n");
+		BREAK_TO_DEBUGGER();
+		goto create_fail;
+	}
+
+	/* MPCCs */
+	pool->base.mpc = dcn321_mpc_create(ctx,  pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
+	if (pool->base.mpc == NULL) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create mpc!\n");
+		goto create_fail;
+	}
+
+	/* DSCs */
+	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+		pool->base.dscs[i] = dcn321_dsc_create(ctx, i);
+		if (pool->base.dscs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create display stream compressor %d!\n", i);
+			goto create_fail;
+		}
+	}
+
+	/* DWB */
+	if (!dcn321_dwbc_create(ctx, &pool->base)) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create dwbc!\n");
+		goto create_fail;
+	}
+
+	/* MMHUBBUB */
+	if (!dcn321_mmhubbub_create(ctx, &pool->base)) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create mcif_wb!\n");
+		goto create_fail;
+	}
+
+	/* AUX and I2C */
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+		pool->base.engines[i] = dcn321_aux_engine_create(ctx, i);
+		if (pool->base.engines[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create aux engine!!\n");
+			goto create_fail;
+		}
+		pool->base.hw_i2cs[i] = dcn321_i2c_hw_create(ctx, i);
+		if (pool->base.hw_i2cs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create hw i2c!!\n");
+			goto create_fail;
+		}
+		pool->base.sw_i2cs[i] = NULL;
+	}
+
+	/* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
+	if (!resource_construct(num_virtual_links, dc, &pool->base,
+			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
+			&res_create_funcs : &res_create_maximus_funcs)))
+			goto create_fail;
+
+	/* HW Sequencer init functions and Plane caps */
+	dcn32_hw_sequencer_init_functions(dc);
+
+	dc->caps.max_planes =  pool->base.pipe_count;
+
+	for (i = 0; i < dc->caps.max_planes; ++i)
+		dc->caps.planes[i] = plane_cap;
+
+	dc->cap_funcs = cap_funcs;
+
+	if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
+		ddc_init_data.ctx = dc->ctx;
+		ddc_init_data.link = NULL;
+		ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
+		ddc_init_data.id.enum_id = 0;
+		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
+		pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
+	} else {
+		pool->base.oem_device = NULL;
+	}
+
+	return true;
+
+create_fail:
+
+	dcn321_resource_destruct(pool);
+
+	return false;
+}
+
+struct resource_pool *dcn321_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc)
+{
+	struct dcn321_resource_pool *pool =
+		kzalloc(sizeof(struct dcn321_resource_pool), GFP_KERNEL);
+
+	if (!pool)
+		return NULL;
+
+	if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool))
+		return &pool->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(pool);
+	return NULL;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index b5570aa8e39d9..4dd461e6c14ba 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -125,6 +125,7 @@ struct nv_wm_range_entry {
 		double pstate_latency_us;
 		double sr_exit_time_us;
 		double sr_enter_plus_exit_time_us;
+		double fclk_change_latency_us;
 	} dml_input;
 };
 
@@ -142,6 +143,7 @@ struct clk_state_registers_and_bypass {
 	uint32_t dprefclk;
 	uint32_t dispclk;
 	uint32_t dppclk;
+	uint32_t dtbclk;
 
 	uint32_t dppclk_bypass;
 	uint32_t dcfclk_bypass;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index 1391c20f18524..68c2ed434d2c4 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -112,9 +112,10 @@ enum dentist_divider_range {
 	CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \
 	CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0)
 
-// TODO:
 #define CLK_REG_LIST_DCN3()	  \
-	SR(DENTIST_DISPCLK_CNTL)
+	CLK_COMMON_REG_LIST_DCN_BASE(), \
+	CLK_SRI(CLK0_CLK_PLL_REQ,   CLK02, 0), \
+	CLK_SRI(CLK0_CLK2_DFS_CNTL, CLK02, 0)
 
 #define CLK_SF(reg_name, field_name, post_fix)\
 	.field_name = reg_name ## __ ## field_name ## post_fix
@@ -155,6 +156,34 @@ enum dentist_divider_range {
 	CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh),\
 	CLK_SF(CLK4_0_CLK4_CLK_PLL_REQ, FbMult_int, mask_sh)
 
+#define CLK_REG_LIST_DCN32()	  \
+	SR(DENTIST_DISPCLK_CNTL), \
+	CLK_SR_DCN32(CLK1_CLK_PLL_REQ), \
+	CLK_SR_DCN32(CLK1_CLK0_DFS_CNTL), \
+	CLK_SR_DCN32(CLK1_CLK1_DFS_CNTL), \
+	CLK_SR_DCN32(CLK1_CLK2_DFS_CNTL), \
+	CLK_SR_DCN32(CLK1_CLK3_DFS_CNTL), \
+	CLK_SR_DCN32(CLK1_CLK4_DFS_CNTL)
+
+#define CLK_COMMON_MASK_SH_LIST_DCN32(mask_sh) \
+	CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
+	CLK_SF(CLK1_CLK_PLL_REQ, FbMult_int, mask_sh),\
+	CLK_SF(CLK1_CLK_PLL_REQ, FbMult_frac, mask_sh)
+
+#define CLK_REG_LIST_DCN321()	  \
+	SR(DENTIST_DISPCLK_CNTL), \
+	CLK_SR_DCN321(CLK0_CLK_PLL_REQ,   CLK01, 0), \
+	CLK_SR_DCN321(CLK0_CLK0_DFS_CNTL, CLK01, 0), \
+	CLK_SR_DCN321(CLK0_CLK1_DFS_CNTL, CLK01, 0), \
+	CLK_SR_DCN321(CLK0_CLK2_DFS_CNTL, CLK01, 0), \
+	CLK_SR_DCN321(CLK0_CLK3_DFS_CNTL, CLK01, 0), \
+	CLK_SR_DCN321(CLK0_CLK4_DFS_CNTL, CLK01, 0)
+
+#define CLK_COMMON_MASK_SH_LIST_DCN321(mask_sh) \
+	CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
+	CLK_SF(CLK0_CLK_PLL_REQ, FbMult_int, mask_sh),\
+	CLK_SF(CLK0_CLK_PLL_REQ, FbMult_frac, mask_sh)
+
 #define CLK_REG_FIELD_LIST(type) \
 	type DPREFCLK_SRC_SEL; \
 	type DENTIST_DPREFCLK_WDIVIDER; \
@@ -199,6 +228,18 @@ struct clk_mgr_registers {
 	uint32_t CLK0_CLK2_DFS_CNTL;
 	uint32_t CLK0_CLK_PLL_REQ;
 
+	uint32_t CLK1_CLK_PLL_REQ;
+	uint32_t CLK1_CLK0_DFS_CNTL;
+	uint32_t CLK1_CLK1_DFS_CNTL;
+	uint32_t CLK1_CLK2_DFS_CNTL;
+	uint32_t CLK1_CLK3_DFS_CNTL;
+	uint32_t CLK1_CLK4_DFS_CNTL;
+
+	uint32_t CLK0_CLK0_DFS_CNTL;
+	uint32_t CLK0_CLK1_DFS_CNTL;
+	uint32_t CLK0_CLK3_DFS_CNTL;
+	uint32_t CLK0_CLK4_DFS_CNTL;
+
 	uint32_t MP1_SMN_C2PMSG_67;
 	uint32_t MP1_SMN_C2PMSG_83;
 	uint32_t MP1_SMN_C2PMSG_91;
-- 
GitLab


From 235c67634230b0f9ad8c0185272fed36c892b1c4 Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Wed, 23 Feb 2022 17:46:31 -0500
Subject: [PATCH 0156/1731] drm/amd/display: add DCN32/321 specific files for
 Display Core

Add core DC support for DCN 3.2.x.

v2: squash in fixup (Alex)

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn32/Makefile |   37 +
 .../gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c |  299 ++
 .../gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h |  155 +
 .../display/dc/dcn32/dcn32_dio_link_encoder.c |  283 ++
 .../display/dc/dcn32/dcn32_dio_link_encoder.h |   42 +
 .../dc/dcn32/dcn32_dio_stream_encoder.c       |  427 ++
 .../dc/dcn32/dcn32_dio_stream_encoder.h       |  254 ++
 .../gpu/drm/amd/display/dc/dcn32/dcn32_dpp.c  |  164 +
 .../gpu/drm/amd/display/dc/dcn32/dcn32_dpp.h  |   38 +
 .../dc/dcn32/dcn32_hpo_dp_link_encoder.c      |   90 +
 .../dc/dcn32/dcn32_hpo_dp_link_encoder.h      |   63 +
 .../drm/amd/display/dc/dcn32/dcn32_hubbub.c   |  964 ++++
 .../drm/amd/display/dc/dcn32/dcn32_hubbub.h   |  172 +
 .../gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c |  148 +
 .../gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h |   69 +
 .../drm/amd/display/dc/dcn32/dcn32_hwseq.c    |  891 ++++
 .../drm/amd/display/dc/dcn32/dcn32_hwseq.h    |   64 +
 .../gpu/drm/amd/display/dc/dcn32/dcn32_init.c |  155 +
 .../gpu/drm/amd/display/dc/dcn32/dcn32_init.h |   33 +
 .../drm/amd/display/dc/dcn32/dcn32_mmhubbub.c |  239 +
 .../drm/amd/display/dc/dcn32/dcn32_mmhubbub.h |  225 +
 .../gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c  |  810 ++++
 .../gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h  |  213 +
 .../gpu/drm/amd/display/dc/dcn32/dcn32_optc.c |  236 +
 .../gpu/drm/amd/display/dc/dcn32/dcn32_optc.h |  253 ++
 .../drm/amd/display/dc/dcn32/dcn32_resource.c | 3976 +++++++++++++++++
 .../drm/amd/display/dc/dcn32/dcn32_resource.h |   88 +
 .../gpu/drm/amd/display/dc/dcn321/Makefile    |   34 +
 .../amd/display/dc/dcn321/dcn321_resource.c   |   32 +-
 .../amd/display/dc/dcn321/dcn321_resource.h   |   42 +
 30 files changed, 10478 insertions(+), 18 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/Makefile
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn321/Makefile
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.h

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/Makefile b/drivers/gpu/drm/amd/display/dc/dcn32/Makefile
new file mode 100644
index 0000000000000..6e0328060255c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/Makefile
@@ -0,0 +1,37 @@
+#
+# (c) Copyright 2022 Advanced Micro Devices, Inc. All the rights reserved
+#
+#  All rights reserved.  This notice is intended as a precaution against
+#  inadvertent publication and does not imply publication or any waiver
+#  of confidentiality.  The year included in the foregoing notice is the
+#  year of creation of the work.
+#
+#  Authors: AMD
+#
+# Makefile for dcn32.
+
+DCN32 = dcn32_resource.o dcn32_hubbub.o dcn32_hwseq.o dcn32_init.o \
+		dcn32_dccg.o dcn32_optc.o dcn32_mmhubbub.o dcn32_hubp.o dcn32_dpp.o \
+		dcn32_dio_stream_encoder.o dcn32_dio_link_encoder.o dcn32_hpo_dp_link_encoder.o \
+		dcn32_mpc.o
+
+CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o := -mhard-float -msse
+
+ifdef CONFIG_CC_IS_GCC
+ifeq ($(call cc-ifversion, -lt, 0701, y), y)
+IS_OLD_GCC = 1
+endif
+endif
+
+ifdef IS_OLD_GCC
+# Stack alignment mismatch, proceed with caution.
+# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+# (8B stack alignment).
+CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o += -mpreferred-stack-boundary=4
+else
+CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o += -msse2
+endif
+
+AMD_DAL_DCN32 = $(addprefix $(AMDDALPATH)/dc/dcn32/,$(DCN32))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DCN32)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
new file mode 100644
index 0000000000000..12633561be3f1
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
@@ -0,0 +1,299 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+#include "core_types.h"
+#include "dcn32_dccg.h"
+
+#define TO_DCN_DCCG(dccg)\
+	container_of(dccg, struct dcn_dccg, base)
+
+#define REG(reg) \
+	(dccg_dcn->regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+	dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
+
+#define CTX \
+	dccg_dcn->base.ctx
+#define DC_LOGGER \
+	dccg->ctx->logger
+
+enum pixel_rate_div {
+	PIXEL_RATE_DIV_BY_1 = 0,
+	PIXEL_RATE_DIV_BY_2 = 1,
+	PIXEL_RATE_DIV_BY_4 = 3
+};
+
+static void dccg32_set_pixel_rate_div(
+		struct dccg *dccg,
+		uint32_t otg_inst,
+		enum pixel_rate_div k1,
+		enum pixel_rate_div k2)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	switch (otg_inst) {
+	case 0:
+		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
+				OTG0_PIXEL_RATE_DIVK1, k1,
+				OTG0_PIXEL_RATE_DIVK2, k2);
+		break;
+	case 1:
+		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
+				OTG1_PIXEL_RATE_DIVK1, k1,
+				OTG1_PIXEL_RATE_DIVK2, k2);
+		break;
+	case 2:
+		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
+				OTG2_PIXEL_RATE_DIVK1, k1,
+				OTG2_PIXEL_RATE_DIVK2, k2);
+		break;
+	case 3:
+		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
+				OTG3_PIXEL_RATE_DIVK1, k1,
+				OTG3_PIXEL_RATE_DIVK2, k2);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		return;
+	}
+}
+
+static void dccg32_set_dtbclk_p_src(
+		struct dccg *dccg,
+		enum streamclk_source src,
+		uint32_t otg_inst)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	uint32_t p_src_sel = 0; /* selects dprefclk */
+	if (src == DTBCLK0)
+		p_src_sel = 2;  /* selects dtbclk0 */
+
+	switch (otg_inst) {
+	case 0:
+		if (src == REFCLK)
+			REG_UPDATE(DTBCLK_P_CNTL,
+					DTBCLK_P0_EN, 0);
+		else
+			REG_UPDATE_2(DTBCLK_P_CNTL,
+					DTBCLK_P0_SRC_SEL, p_src_sel,
+					DTBCLK_P0_EN, 1);
+		break;
+	case 1:
+		if (src == REFCLK)
+			REG_UPDATE(DTBCLK_P_CNTL,
+					DTBCLK_P1_EN, 0);
+		else
+			REG_UPDATE_2(DTBCLK_P_CNTL,
+					DTBCLK_P1_SRC_SEL, p_src_sel,
+					DTBCLK_P1_EN, 1);
+		break;
+	case 2:
+		if (src == REFCLK)
+			REG_UPDATE(DTBCLK_P_CNTL,
+					DTBCLK_P2_EN, 0);
+		else
+			REG_UPDATE_2(DTBCLK_P_CNTL,
+					DTBCLK_P2_SRC_SEL, p_src_sel,
+					DTBCLK_P2_EN, 1);
+		break;
+	case 3:
+		if (src == REFCLK)
+			REG_UPDATE(DTBCLK_P_CNTL,
+					DTBCLK_P3_EN, 0);
+		else
+			REG_UPDATE_2(DTBCLK_P_CNTL,
+					DTBCLK_P3_SRC_SEL, p_src_sel,
+					DTBCLK_P3_EN, 1);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		return;
+	}
+
+}
+
+/* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
+void dccg32_set_dtbclk_dto(
+		struct dccg *dccg,
+		int otg_inst,
+		int pixclk_khz,
+		int num_odm_segments,
+		const struct dc_crtc_timing *timing)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+	/* DTO Output Rate / Pixel Rate = 1/4 */
+	int req_dtbclk_khz = pixclk_khz / 4;
+
+	if (dccg->ref_dtbclk_khz && req_dtbclk_khz) {
+		uint32_t modulo, phase;
+
+		// phase / modulo = dtbclk / dtbclk ref
+		modulo = 0xffffffff;
+		phase = (((unsigned long long)modulo * req_dtbclk_khz) + dccg->ref_dtbclk_khz - 1) / dccg->ref_dtbclk_khz;
+
+		REG_WRITE(DTBCLK_DTO_MODULO[otg_inst], modulo);
+		REG_WRITE(DTBCLK_DTO_PHASE[otg_inst], phase);
+
+		REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
+				DTBCLK_DTO_ENABLE[otg_inst], 1);
+
+		REG_WAIT(OTG_PIXEL_RATE_CNTL[otg_inst],
+				DTBCLKDTO_ENABLE_STATUS[otg_inst], 1,
+				1, 100);
+
+		/* program OTG_PIXEL_RATE_DIV for DIVK1 and DIVK2 fields */
+		dccg32_set_pixel_rate_div(dccg, otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);
+
+		/* The recommended programming sequence to enable DTBCLK DTO to generate
+		 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should
+		 * be set only after DTO is enabled
+		 */
+		REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
+				PIPE_DTO_SRC_SEL[otg_inst], 2);
+
+		dccg->dtbclk_khz[otg_inst] = req_dtbclk_khz;
+	} else {
+		REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst],
+				DTBCLK_DTO_ENABLE[otg_inst], 0,
+				PIPE_DTO_SRC_SEL[otg_inst], 1);
+
+		REG_WRITE(DTBCLK_DTO_MODULO[otg_inst], 0);
+		REG_WRITE(DTBCLK_DTO_PHASE[otg_inst], 0);
+
+		dccg->dtbclk_khz[otg_inst] = 0;
+	}
+}
+
+static void dccg32_get_dccg_ref_freq(struct dccg *dccg,
+		unsigned int xtalin_freq_inKhz,
+		unsigned int *dccg_ref_freq_inKhz)
+{
+	/*
+	 * Assume refclk is sourced from xtalin
+	 * expect 100MHz
+	 */
+	*dccg_ref_freq_inKhz = xtalin_freq_inKhz;
+	return;
+}
+
+void dccg32_set_dpstreamclk(
+		struct dccg *dccg,
+		enum streamclk_source src,
+		int otg_inst)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	/* set the dtbclk_p source */
+	dccg32_set_dtbclk_p_src(dccg, src, otg_inst);
+
+	/* enabled to select one of the DTBCLKs for pipe */
+	switch (otg_inst)
+	{
+	case 0:
+		REG_UPDATE_2(DPSTREAMCLK_CNTL,
+			     DPSTREAMCLK0_EN,
+			     (src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, 0);
+		break;
+	case 1:
+		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN,
+			     (src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, 1);
+		break;
+	case 2:
+		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN,
+			     (src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, 2);
+		break;
+	case 3:
+		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN,
+			     (src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, 3);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		return;
+	}
+}
+
+void dccg32_otg_add_pixel(struct dccg *dccg,
+		uint32_t otg_inst)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
+			OTG_ADD_PIXEL[otg_inst], 1);
+}
+
+void dccg32_otg_drop_pixel(struct dccg *dccg,
+		uint32_t otg_inst)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
+			OTG_DROP_PIXEL[otg_inst], 1);
+}
+
+static const struct dccg_funcs dccg32_funcs = {
+	.update_dpp_dto = dccg2_update_dpp_dto,
+	.get_dccg_ref_freq = dccg32_get_dccg_ref_freq,
+	.dccg_init = dccg31_init,
+	.set_dpstreamclk = dccg32_set_dpstreamclk,
+	.enable_symclk32_se = dccg31_enable_symclk32_se,
+	.disable_symclk32_se = dccg31_disable_symclk32_se,
+	.enable_symclk32_le = dccg31_enable_symclk32_le,
+	.disable_symclk32_le = dccg31_disable_symclk32_le,
+	.set_physymclk = dccg31_set_physymclk,
+	.set_dtbclk_dto = dccg32_set_dtbclk_dto,
+	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
+	.set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,
+	.otg_add_pixel = dccg32_otg_add_pixel,
+	.otg_drop_pixel = dccg32_otg_drop_pixel,
+};
+
+struct dccg *dccg32_create(
+	struct dc_context *ctx,
+	const struct dccg_registers *regs,
+	const struct dccg_shift *dccg_shift,
+	const struct dccg_mask *dccg_mask)
+{
+	struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);
+	struct dccg *base;
+
+	if (dccg_dcn == NULL) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	base = &dccg_dcn->base;
+	base->ctx = ctx;
+	base->funcs = &dccg32_funcs;
+
+	dccg_dcn->regs = regs;
+	dccg_dcn->dccg_shift = dccg_shift;
+	dccg_dcn->dccg_mask = dccg_mask;
+
+	return &dccg_dcn->base;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h
new file mode 100644
index 0000000000000..0e54c0a105a10
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DCN32_DCCG_H__
+#define __DCN32_DCCG_H__
+
+#include "dcn31/dcn31_dccg.h"
+
+#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\
+	.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
+
+
+#define DCCG_REG_LIST_DCN32() \
+	SR(DPPCLK_DTO_CTRL),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
+	DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),\
+	SR(PHYASYMCLK_CLOCK_CNTL),\
+	SR(PHYBSYMCLK_CLOCK_CNTL),\
+	SR(PHYCSYMCLK_CLOCK_CNTL),\
+	SR(PHYDSYMCLK_CLOCK_CNTL),\
+	SR(PHYESYMCLK_CLOCK_CNTL),\
+	SR(DPSTREAMCLK_CNTL),\
+	SR(SYMCLK32_SE_CNTL),\
+	SR(SYMCLK32_LE_CNTL),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
+	DCCG_SRII(MODULO, DTBCLK_DTO, 0),\
+	DCCG_SRII(MODULO, DTBCLK_DTO, 1),\
+	DCCG_SRII(MODULO, DTBCLK_DTO, 2),\
+	DCCG_SRII(MODULO, DTBCLK_DTO, 3),\
+	DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
+	DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
+	DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
+	DCCG_SRII(PHASE, DTBCLK_DTO, 3),\
+	SR(DCCG_AUDIO_DTBCLK_DTO_MODULO),\
+	SR(DCCG_AUDIO_DTBCLK_DTO_PHASE),\
+	SR(OTG_PIXEL_RATE_DIV),\
+	SR(DTBCLK_P_CNTL),\
+	SR(DCCG_AUDIO_DTO_SOURCE)
+
+
+#define DCCG_MASK_SH_LIST_DCN32(mask_sh) \
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\
+	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
+	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
+	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\
+	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_SRC_SEL, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_SRC_SEL, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_SRC_SEL, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_SRC_SEL, mask_sh),\
+	DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_EN, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_PIXEL_RATE_DIVK1, mask_sh),\
+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_PIXEL_RATE_DIVK2, mask_sh),\
+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_PIXEL_RATE_DIVK1, mask_sh),\
+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_PIXEL_RATE_DIVK2, mask_sh),\
+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_PIXEL_RATE_DIVK1, mask_sh),\
+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_PIXEL_RATE_DIVK2, mask_sh),\
+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK1, mask_sh),\
+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK2, mask_sh),\
+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK2, mask_sh),\
+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_SRC_SEL, mask_sh),\
+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_EN, mask_sh),\
+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_SRC_SEL, mask_sh),\
+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_EN, mask_sh),\
+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_SRC_SEL, mask_sh),\
+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\
+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_SRC_SEL, mask_sh),\
+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\
+	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh)
+
+
+struct dccg *dccg32_create(
+	struct dc_context *ctx,
+	const struct dccg_registers *regs,
+	const struct dccg_shift *dccg_shift,
+	const struct dccg_mask *dccg_mask);
+
+#endif //__DCN32_DCCG_H__
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c
new file mode 100644
index 0000000000000..7170a9aa82a47
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c
@@ -0,0 +1,283 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "reg_helper.h"
+
+#include "core_types.h"
+#include "link_encoder.h"
+#include "dcn31/dcn31_dio_link_encoder.h"
+#include "dcn32_dio_link_encoder.h"
+#include "stream_encoder.h"
+#include "i2caux_interface.h"
+#include "dc_bios_types.h"
+
+#include "gpio_service_interface.h"
+
+#ifndef MIN
+#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
+#endif
+
+#define CTX \
+	enc10->base.ctx
+#define DC_LOGGER \
+	enc10->base.ctx->logger
+
+#define REG(reg)\
+	(enc10->link_regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+	enc10->link_shift->field_name, enc10->link_mask->field_name
+
+#define AUX_REG(reg)\
+	(enc10->aux_regs->reg)
+
+#define AUX_REG_READ(reg_name) \
+		dm_read_reg(CTX, AUX_REG(reg_name))
+
+#define AUX_REG_WRITE(reg_name, val) \
+			dm_write_reg(CTX, AUX_REG(reg_name), val)
+
+
+void enc32_hw_init(struct link_encoder *enc)
+{
+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+
+/*
+	00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
+	01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
+	02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
+	03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
+	04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
+	05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
+	06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
+	07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
+*/
+
+/*
+	AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
+	AUX_RX_START_WINDOW = 1 [6:4]
+	AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
+	AUX_RX_HALF_SYM_DETECT_LEN  = 1 [13:12] default is 1
+	AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
+	AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0  default is 0
+	AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1  default is 1
+	AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1  default is 1
+	AUX_RX_PHASE_DETECT_LEN,  [21,20] = 0x3 default is 3
+	AUX_RX_DETECTION_THRESHOLD [30:28] = 1
+*/
+	AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
+
+	AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
+
+	//AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
+	// Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
+	// 27MHz -> 0xd
+	// 100MHz -> 0x32
+	// 48MHz -> 0x18
+
+	// Set TMDS_CTL0 to 1.  This is a legacy setting.
+	REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
+
+	dcn10_aux_initialize(enc10);
+}
+
+
+void dcn32_link_encoder_enable_dp_output(
+	struct link_encoder *enc,
+	const struct dc_link_settings *link_settings,
+	enum clock_source_id clock_source)
+{
+	if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
+		dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source);
+		return;
+	}
+}
+
+bool dcn32_link_encoder_is_in_alt_mode(struct link_encoder *enc)
+{
+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+	uint32_t dp_alt_mode_disable = 0;
+	bool is_usb_c_alt_mode = false;
+
+	if (enc->features.flags.bits.DP_IS_USB_C) {
+		/* if value == 1 alt mode is disabled, otherwise it is enabled */
+		//REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
+		is_usb_c_alt_mode = (dp_alt_mode_disable == 0);
+	}
+
+	return is_usb_c_alt_mode;
+}
+
+void dcn32_link_encoder_get_max_link_cap(struct link_encoder *enc,
+	struct dc_link_settings *link_settings)
+{
+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+	uint32_t is_in_usb_c_dp4_mode = 0;
+
+	dcn10_link_encoder_get_max_link_cap(enc, link_settings);
+
+	/* in usb c dp2 mode, max lane count is 2 */
+	if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) {
+//		REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
+		if (!is_in_usb_c_dp4_mode)
+			link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
+	}
+
+}
+
+static const struct link_encoder_funcs dcn32_link_enc_funcs = {
+	.read_state = link_enc2_read_state,
+	.validate_output_with_stream =
+			dcn30_link_encoder_validate_output_with_stream,
+	.hw_init = enc32_hw_init,
+	.setup = dcn10_link_encoder_setup,
+	.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
+	.enable_dp_output = dcn32_link_encoder_enable_dp_output,
+	.enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
+	.disable_output = dcn10_link_encoder_disable_output,
+	.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
+	.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
+	.update_mst_stream_allocation_table =
+		dcn10_link_encoder_update_mst_stream_allocation_table,
+	.psr_program_dp_dphy_fast_training =
+			dcn10_psr_program_dp_dphy_fast_training,
+	.psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
+	.connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
+	.enable_hpd = dcn10_link_encoder_enable_hpd,
+	.disable_hpd = dcn10_link_encoder_disable_hpd,
+	.is_dig_enabled = dcn10_is_dig_enabled,
+	.destroy = dcn10_link_encoder_destroy,
+	.fec_set_enable = enc2_fec_set_enable,
+	.fec_set_ready = enc2_fec_set_ready,
+	.fec_is_active = enc2_fec_is_active,
+	.get_dig_frontend = dcn10_get_dig_frontend,
+	.get_dig_mode = dcn10_get_dig_mode,
+	.is_in_alt_mode = dcn32_link_encoder_is_in_alt_mode,
+	.get_max_link_cap = dcn32_link_encoder_get_max_link_cap,
+	.set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
+};
+
+void dcn32_link_encoder_construct(
+	struct dcn20_link_encoder *enc20,
+	const struct encoder_init_data *init_data,
+	const struct encoder_feature_support *enc_features,
+	const struct dcn10_link_enc_registers *link_regs,
+	const struct dcn10_link_enc_aux_registers *aux_regs,
+	const struct dcn10_link_enc_hpd_registers *hpd_regs,
+	const struct dcn10_link_enc_shift *link_shift,
+	const struct dcn10_link_enc_mask *link_mask)
+{
+	struct bp_connector_speed_cap_info bp_cap_info = {0};
+	const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
+	enum bp_result result = BP_RESULT_OK;
+	struct dcn10_link_encoder *enc10 = &enc20->enc10;
+
+	enc10->base.funcs = &dcn32_link_enc_funcs;
+	enc10->base.ctx = init_data->ctx;
+	enc10->base.id = init_data->encoder;
+
+	enc10->base.hpd_source = init_data->hpd_source;
+	enc10->base.connector = init_data->connector;
+
+	enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
+
+	enc10->base.features = *enc_features;
+
+	enc10->base.transmitter = init_data->transmitter;
+
+	/* set the flag to indicate whether driver poll the I2C data pin
+	 * while doing the DP sink detect
+	 */
+
+/*	if (dal_adapter_service_is_feature_supported(as,
+		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
+		enc10->base.features.flags.bits.
+			DP_SINK_DETECT_POLL_DATA_PIN = true;*/
+
+	enc10->base.output_signals =
+		SIGNAL_TYPE_DVI_SINGLE_LINK |
+		SIGNAL_TYPE_DVI_DUAL_LINK |
+		SIGNAL_TYPE_LVDS |
+		SIGNAL_TYPE_DISPLAY_PORT |
+		SIGNAL_TYPE_DISPLAY_PORT_MST |
+		SIGNAL_TYPE_EDP |
+		SIGNAL_TYPE_HDMI_TYPE_A;
+
+	enc10->link_regs = link_regs;
+	enc10->aux_regs = aux_regs;
+	enc10->hpd_regs = hpd_regs;
+	enc10->link_shift = link_shift;
+	enc10->link_mask = link_mask;
+
+	switch (enc10->base.transmitter) {
+	case TRANSMITTER_UNIPHY_A:
+		enc10->base.preferred_engine = ENGINE_ID_DIGA;
+	break;
+	case TRANSMITTER_UNIPHY_B:
+		enc10->base.preferred_engine = ENGINE_ID_DIGB;
+	break;
+	case TRANSMITTER_UNIPHY_C:
+		enc10->base.preferred_engine = ENGINE_ID_DIGC;
+	break;
+	case TRANSMITTER_UNIPHY_D:
+		enc10->base.preferred_engine = ENGINE_ID_DIGD;
+	break;
+	case TRANSMITTER_UNIPHY_E:
+		enc10->base.preferred_engine = ENGINE_ID_DIGE;
+	break;
+	default:
+		ASSERT_CRITICAL(false);
+		enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
+	}
+
+	/* default to one to mirror Windows behavior */
+	enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
+
+	if (bp_funcs->get_connector_speed_cap_info)
+		result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios,
+						enc10->base.connector, &bp_cap_info);
+
+	/* Override features with DCE-specific values */
+	if (result == BP_RESULT_OK) {
+		enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
+				bp_cap_info.DP_HBR2_EN;
+		enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
+				bp_cap_info.DP_HBR3_EN;
+		enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
+		enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1;
+		enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;
+		enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;
+		enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;
+	} else {
+		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
+				__func__,
+				result);
+	}
+	if (enc10->base.ctx->dc->debug.hdmi20_disable) {
+		enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
+	}
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h
new file mode 100644
index 0000000000000..e880b76d5f252
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_LINK_ENCODER__DCN32_H__
+#define __DC_LINK_ENCODER__DCN32_H__
+
+#include "dcn30/dcn30_dio_link_encoder.h"
+
+void dcn32_link_encoder_construct(
+	struct dcn20_link_encoder *enc20,
+	const struct encoder_init_data *init_data,
+	const struct encoder_feature_support *enc_features,
+	const struct dcn10_link_enc_registers *link_regs,
+	const struct dcn10_link_enc_aux_registers *aux_regs,
+	const struct dcn10_link_enc_hpd_registers *hpd_regs,
+	const struct dcn10_link_enc_shift *link_shift,
+	const struct dcn10_link_enc_mask *link_mask);
+
+
+#endif /* __DC_LINK_ENCODER__DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
new file mode 100644
index 0000000000000..62532da949137
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
@@ -0,0 +1,427 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "dc_bios_types.h"
+#include "dcn30/dcn30_dio_stream_encoder.h"
+#include "dcn32_dio_stream_encoder.h"
+#include "reg_helper.h"
+#include "hw_shared.h"
+#include "inc/link_dpcd.h"
+#include "dpcd_defs.h"
+
+#define DC_LOGGER \
+		enc1->base.ctx->logger
+
+#define REG(reg)\
+	(enc1->regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+	enc1->se_shift->field_name, enc1->se_mask->field_name
+
+#define VBI_LINE_0 0
+#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
+
+#define CTX \
+	enc1->base.ctx
+
+
+
+static void enc32_dp_set_odm_combine(
+	struct stream_encoder *enc,
+	bool odm_combine)
+{
+	//struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+	//TODO: REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine);
+}
+
+/* setup stream encoder in dvi mode */
+void enc32_stream_encoder_dvi_set_stream_attribute(
+	struct stream_encoder *enc,
+	struct dc_crtc_timing *crtc_timing,
+	bool is_dual_link)
+{
+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+	if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
+		struct bp_encoder_control cntl = {0};
+
+		cntl.action = ENCODER_CONTROL_SETUP;
+		cntl.engine_id = enc1->base.id;
+		cntl.signal = is_dual_link ?
+			SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
+		cntl.enable_dp_audio = false;
+		cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
+		cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
+
+		if (enc1->base.bp->funcs->encoder_control(
+				enc1->base.bp, &cntl) != BP_RESULT_OK)
+			return;
+
+	} else {
+
+		//Set pattern for clock channel, default vlue 0x63 does not work
+		REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
+
+		//DIG_BE_TMDS_DVI_MODE : TMDS-DVI mode is already set in link_encoder_setup
+
+		//DIG_SOURCE_SELECT is already set in dig_connect_to_otg
+
+		/* DIG_START is removed from the register spec */
+	}
+
+	ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
+	ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
+	enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
+}
+
+/* setup stream encoder in hdmi mode */
+static void enc32_stream_encoder_hdmi_set_stream_attribute(
+	struct stream_encoder *enc,
+	struct dc_crtc_timing *crtc_timing,
+	int actual_pix_clk_khz,
+	bool enable_audio)
+{
+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+	if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
+		struct bp_encoder_control cntl = {0};
+
+		cntl.action = ENCODER_CONTROL_SETUP;
+		cntl.engine_id = enc1->base.id;
+		cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
+		cntl.enable_dp_audio = enable_audio;
+		cntl.pixel_clock = actual_pix_clk_khz;
+		cntl.lanes_number = LANE_COUNT_FOUR;
+
+		if (enc1->base.bp->funcs->encoder_control(
+				enc1->base.bp, &cntl) != BP_RESULT_OK)
+			return;
+
+	} else {
+
+		//Set pattern for clock channel, default vlue 0x63 does not work
+		REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
+
+		//DIG_BE_TMDS_HDMI_MODE : TMDS-HDMI mode is already set in link_encoder_setup
+
+		//DIG_SOURCE_SELECT is already set in dig_connect_to_otg
+
+		/* DIG_START is removed from the register spec */
+	}
+
+	/* Configure pixel encoding */
+	enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
+
+	/* setup HDMI engine */
+	REG_UPDATE_6(HDMI_CONTROL,
+		HDMI_PACKET_GEN_VERSION, 1,
+		HDMI_KEEPOUT_MODE, 1,
+		HDMI_DEEP_COLOR_ENABLE, 0,
+		HDMI_DATA_SCRAMBLE_EN, 0,
+		HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,
+		HDMI_CLOCK_CHANNEL_RATE, 0);
+
+	/* Configure color depth */
+	switch (crtc_timing->display_color_depth) {
+	case COLOR_DEPTH_888:
+		REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
+		break;
+	case COLOR_DEPTH_101010:
+		if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
+			REG_UPDATE_2(HDMI_CONTROL,
+					HDMI_DEEP_COLOR_DEPTH, 1,
+					HDMI_DEEP_COLOR_ENABLE, 0);
+		} else {
+			REG_UPDATE_2(HDMI_CONTROL,
+					HDMI_DEEP_COLOR_DEPTH, 1,
+					HDMI_DEEP_COLOR_ENABLE, 1);
+			}
+		break;
+	case COLOR_DEPTH_121212:
+		if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
+			REG_UPDATE_2(HDMI_CONTROL,
+					HDMI_DEEP_COLOR_DEPTH, 2,
+					HDMI_DEEP_COLOR_ENABLE, 0);
+		} else {
+			REG_UPDATE_2(HDMI_CONTROL,
+					HDMI_DEEP_COLOR_DEPTH, 2,
+					HDMI_DEEP_COLOR_ENABLE, 1);
+			}
+		break;
+	case COLOR_DEPTH_161616:
+		REG_UPDATE_2(HDMI_CONTROL,
+				HDMI_DEEP_COLOR_DEPTH, 3,
+				HDMI_DEEP_COLOR_ENABLE, 1);
+		break;
+	default:
+		break;
+	}
+
+	if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
+		/* enable HDMI data scrambler
+		 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
+		 * Clock channel frequency is 1/4 of character rate.
+		 */
+		REG_UPDATE_2(HDMI_CONTROL,
+			HDMI_DATA_SCRAMBLE_EN, 1,
+			HDMI_CLOCK_CHANNEL_RATE, 1);
+	} else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
+
+		/* TODO: New feature for DCE11, still need to implement */
+
+		/* enable HDMI data scrambler
+		 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
+		 * Clock channel frequency is the same
+		 * as character rate
+		 */
+		REG_UPDATE_2(HDMI_CONTROL,
+			HDMI_DATA_SCRAMBLE_EN, 1,
+			HDMI_CLOCK_CHANNEL_RATE, 0);
+	}
+
+
+	/* Enable transmission of General Control packet on every frame */
+	REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
+		HDMI_GC_CONT, 1,
+		HDMI_GC_SEND, 1,
+		HDMI_NULL_SEND, 1);
+
+	/* Disable Audio Content Protection packet transmission */
+	REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);
+
+	/* following belongs to audio */
+	/* Enable Audio InfoFrame packet transmission. */
+	REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
+
+	/* update double-buffered AUDIO_INFO registers immediately */
+	ASSERT(enc->afmt);
+	enc->afmt->funcs->audio_info_immediate_update(enc->afmt);
+
+	/* Select line number on which to send Audio InfoFrame packets */
+	REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
+				VBI_LINE_0 + 2);
+
+	/* set HDMI GC AVMUTE */
+	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
+}
+
+
+
+static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
+{
+	bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
+
+	two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
+			&& !timing->dsc_cfg.ycbcr422_simple);
+	return two_pix;
+}
+
+static void enc32_stream_encoder_dp_unblank(
+        struct dc_link *link,
+		struct stream_encoder *enc,
+		const struct encoder_unblank_param *param)
+{
+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+	if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
+		uint32_t n_vid = 0x8000;
+		uint32_t m_vid;
+		uint32_t n_multiply = 0;
+		uint64_t m_vid_l = n_vid;
+
+		/* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
+		if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1) {
+			/*this logic should be the same in get_pixel_clock_parameters() */
+			n_multiply = 1;
+		}
+		/* M / N = Fstream / Flink
+		 * m_vid / n_vid = pixel rate / link rate
+		 */
+
+		m_vid_l *= param->timing.pix_clk_100hz / 10;
+		m_vid_l = div_u64(m_vid_l,
+			param->link_settings.link_rate
+				* LINK_RATE_REF_FREQ_IN_KHZ);
+
+		m_vid = (uint32_t) m_vid_l;
+
+		/* enable auto measurement */
+
+		REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
+
+		/* auto measurement need 1 full 0x8000 symbol cycle to kick in,
+		 * therefore program initial value for Mvid and Nvid
+		 */
+
+		REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
+
+		REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
+
+		REG_UPDATE_2(DP_VID_TIMING,
+				DP_VID_M_N_GEN_EN, 1,
+				DP_VID_N_MUL, n_multiply);
+	}
+
+	/* make sure stream is disabled before resetting steer fifo */
+	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
+	REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);
+
+	/* DIG_START is removed from the register spec */
+
+	/* switch DP encoder to CRTC data, but reset it the fifo first. It may happen
+	 * that it overflows during mode transition, and sometimes doesn't recover.
+	 */
+	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);
+	udelay(10);
+
+	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
+
+	/* wait 100us for DIG/DP logic to prime
+	 * (i.e. a few video lines)
+	 */
+	udelay(100);
+
+	/* the hardware would start sending video at the start of the next DP
+	 * frame (i.e. rising edge of the vblank).
+	 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
+	 * register has no effect on enable transition! HW always guarantees
+	 * VID_STREAM enable at start of next frame, and this is not
+	 * programmable
+	 */
+
+	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
+
+	dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);
+}
+
+/* Set DSC-related configuration.
+ *   dsc_mode: 0 disables DSC, other values enable DSC in specified format
+ *   sc_bytes_per_pixel: DP_DSC_BYTES_PER_PIXEL removed in DCN32
+ *   dsc_slice_width: DP_DSC_SLICE_WIDTH removed in DCN32
+ */
+static void enc32_dp_set_dsc_config(struct stream_encoder *enc,
+					enum optc_dsc_mode dsc_mode,
+					uint32_t dsc_bytes_per_pixel,
+					uint32_t dsc_slice_width)
+{
+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+	REG_UPDATE(DP_DSC_CNTL,	DP_DSC_MODE, dsc_mode);
+}
+
+/* this function read dsc related register fields to be logged later in dcn10_log_hw_state
+ * into a dcn_dsc_state struct.
+ */
+static void enc32_read_state(struct stream_encoder *enc, struct enc_state *s)
+{
+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+	//if dsc is enabled, continue to read
+	REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);
+	if (s->dsc_mode) {
+		REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num);
+
+		REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference);
+		REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num);
+
+		REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable);
+		REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
+	}
+}
+
+
+static const struct stream_encoder_funcs dcn32_str_enc_funcs = {
+	.dp_set_odm_combine =
+		enc32_dp_set_odm_combine,
+	.dp_set_stream_attribute =
+		enc2_stream_encoder_dp_set_stream_attribute,
+	.hdmi_set_stream_attribute =
+		enc32_stream_encoder_hdmi_set_stream_attribute,
+	.dvi_set_stream_attribute =
+		enc32_stream_encoder_dvi_set_stream_attribute,
+	.set_throttled_vcp_size =
+		enc1_stream_encoder_set_throttled_vcp_size,
+	.update_hdmi_info_packets =
+		enc3_stream_encoder_update_hdmi_info_packets,
+	.stop_hdmi_info_packets =
+		enc3_stream_encoder_stop_hdmi_info_packets,
+	.update_dp_info_packets =
+		enc3_stream_encoder_update_dp_info_packets,
+	.stop_dp_info_packets =
+		enc1_stream_encoder_stop_dp_info_packets,
+	.reset_fifo =
+		enc1_stream_encoder_reset_fifo,
+	.dp_blank =
+		enc1_stream_encoder_dp_blank,
+	.dp_unblank =
+		enc32_stream_encoder_dp_unblank,
+	.audio_mute_control = enc3_audio_mute_control,
+
+	.dp_audio_setup = enc3_se_dp_audio_setup,
+	.dp_audio_enable = enc3_se_dp_audio_enable,
+	.dp_audio_disable = enc1_se_dp_audio_disable,
+
+	.hdmi_audio_setup = enc3_se_hdmi_audio_setup,
+	.hdmi_audio_disable = enc1_se_hdmi_audio_disable,
+	.setup_stereo_sync  = enc1_setup_stereo_sync,
+	.set_avmute = enc1_stream_encoder_set_avmute,
+	.dig_connect_to_otg = enc1_dig_connect_to_otg,
+	.dig_source_otg = enc1_dig_source_otg,
+
+	.dp_get_pixel_format  = enc1_stream_encoder_dp_get_pixel_format,
+
+	.enc_read_state = enc32_read_state,
+	.dp_set_dsc_config = enc32_dp_set_dsc_config,
+	.dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet,
+	.set_dynamic_metadata = enc2_set_dynamic_metadata,
+	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
+};
+
+void dcn32_dio_stream_encoder_construct(
+	struct dcn10_stream_encoder *enc1,
+	struct dc_context *ctx,
+	struct dc_bios *bp,
+	enum engine_id eng_id,
+	struct vpg *vpg,
+	struct afmt *afmt,
+	const struct dcn10_stream_enc_registers *regs,
+	const struct dcn10_stream_encoder_shift *se_shift,
+	const struct dcn10_stream_encoder_mask *se_mask)
+{
+	enc1->base.funcs = &dcn32_str_enc_funcs;
+	enc1->base.ctx = ctx;
+	enc1->base.id = eng_id;
+	enc1->base.bp = bp;
+	enc1->base.vpg = vpg;
+	enc1->base.afmt = afmt;
+	enc1->regs = regs;
+	enc1->se_shift = se_shift;
+	enc1->se_mask = se_mask;
+	enc1->base.stream_enc_inst = vpg->inst;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h
new file mode 100644
index 0000000000000..7241080b15533
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h
@@ -0,0 +1,254 @@
+/*
+ * Copyright 2021 - Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_DIO_STREAM_ENCODER_DCN32_H__
+#define __DC_DIO_STREAM_ENCODER_DCN32_H__
+
+#include "dcn30/dcn30_vpg.h"
+#include "dcn30/dcn30_afmt.h"
+#include "stream_encoder.h"
+#include "dcn20/dcn20_stream_encoder.h"
+
+#define SE_DCN32_REG_LIST(id)\
+	SRI(AFMT_CNTL, DIG, id), \
+	SRI(DIG_FE_CNTL, DIG, id), \
+	SRI(HDMI_CONTROL, DIG, id), \
+	SRI(HDMI_DB_CONTROL, DIG, id), \
+	SRI(HDMI_GC, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \
+	SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
+	SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
+	SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
+	SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
+	SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
+	SRI(HDMI_ACR_32_0, DIG, id),\
+	SRI(HDMI_ACR_32_1, DIG, id),\
+	SRI(HDMI_ACR_44_0, DIG, id),\
+	SRI(HDMI_ACR_44_1, DIG, id),\
+	SRI(HDMI_ACR_48_0, DIG, id),\
+	SRI(HDMI_ACR_48_1, DIG, id),\
+	SRI(DP_DB_CNTL, DP, id), \
+	SRI(DP_MSA_MISC, DP, id), \
+	SRI(DP_MSA_VBID_MISC, DP, id), \
+	SRI(DP_MSA_COLORIMETRY, DP, id), \
+	SRI(DP_MSA_TIMING_PARAM1, DP, id), \
+	SRI(DP_MSA_TIMING_PARAM2, DP, id), \
+	SRI(DP_MSA_TIMING_PARAM3, DP, id), \
+	SRI(DP_MSA_TIMING_PARAM4, DP, id), \
+	SRI(DP_MSE_RATE_CNTL, DP, id), \
+	SRI(DP_MSE_RATE_UPDATE, DP, id), \
+	SRI(DP_PIXEL_FORMAT, DP, id), \
+	SRI(DP_SEC_CNTL, DP, id), \
+	SRI(DP_SEC_CNTL2, DP, id), \
+	SRI(DP_SEC_CNTL6, DP, id), \
+	SRI(DP_STEER_FIFO, DP, id), \
+	SRI(DP_VID_M, DP, id), \
+	SRI(DP_VID_N, DP, id), \
+	SRI(DP_VID_STREAM_CNTL, DP, id), \
+	SRI(DP_VID_TIMING, DP, id), \
+	SRI(DP_SEC_AUD_N, DP, id), \
+	SRI(DP_SEC_TIMESTAMP, DP, id), \
+	SRI(DP_DSC_CNTL, DP, id), \
+	SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
+	SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
+	SRI(DP_SEC_FRAMING4, DP, id), \
+	SRI(DP_GSP11_CNTL, DP, id), \
+	SRI(DME_CONTROL, DME, id),\
+	SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
+	SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
+	SRI(DIG_FE_CNTL, DIG, id), \
+	SRI(DIG_CLOCK_PATTERN, DIG, id)
+
+
+#define SE_COMMON_MASK_SH_LIST_DCN32_BASE(mask_sh)\
+	SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
+	SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
+	SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
+	SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
+	SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
+	SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
+	SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
+	SE_SF(DIG0_HDMI_CONTROL, HDMI_NO_EXTRA_NULL_PACKET_FILLED, mask_sh),\
+	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
+	SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
+	SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
+	SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP5_LINE_REFERENCE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL4, DP_SEC_GSP4_LINE_NUM, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL5, DP_SEC_GSP5_LINE_NUM, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, mask_sh),\
+	SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
+	SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
+	SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
+	SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
+	SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
+	SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
+	SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
+	SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
+	SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
+	SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
+	SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
+	SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
+	SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
+	SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
+	SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
+	SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
+	SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
+	SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
+	SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
+	SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
+	SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
+	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
+	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_SEND, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP11_PPS, mask_sh),\
+	SE_SF(DP0_DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, mask_sh),\
+	SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
+	SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\
+	SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\
+	SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\
+	SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\
+	SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\
+	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\
+	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\
+	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\
+	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\
+	SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\
+	SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
+	SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
+	SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\
+	SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh), \
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC8_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC8_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC9_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC9_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC10_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC10_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC11_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC11_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC12_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC12_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC13_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC13_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC14_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC14_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC0_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC1_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC2_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC3_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC4_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC5_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC6_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC7_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL7, HDMI_GENERIC8_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL7, HDMI_GENERIC9_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL8, HDMI_GENERIC10_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL8, HDMI_GENERIC11_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL9, HDMI_GENERIC12_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL9, HDMI_GENERIC13_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL10, HDMI_GENERIC14_LINE, mask_sh),\
+	SE_SF(DP0_DP_DSC_CNTL, DP_DSC_MODE, mask_sh),\
+	SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, mask_sh),\
+	SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, mask_sh),\
+	SE_SF(DME0_DME_CONTROL, METADATA_ENGINE_EN, mask_sh),\
+	SE_SF(DME0_DME_CONTROL, METADATA_HUBP_REQUESTOR_ID, mask_sh),\
+	SE_SF(DME0_DME_CONTROL, METADATA_STREAM_TYPE, mask_sh),\
+	SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE_REFERENCE, mask_sh),\
+	SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_ENABLE, mask_sh),\
+	SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE_REFERENCE, mask_sh),\
+	SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE, mask_sh),\
+	SE_SF(DIG0_DIG_FE_CNTL, DOLBY_VISION_EN, mask_sh),\
+	SE_SF(DP0_DP_SEC_FRAMING4, DP_SST_SDP_SPLITTING, mask_sh),\
+	SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh)
+
+#define SE_COMMON_MASK_SH_LIST_DCN32(mask_sh)\
+	SE_COMMON_MASK_SH_LIST_DCN32_BASE(mask_sh),\
+	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh)
+
+void dcn32_dio_stream_encoder_construct(
+	struct dcn10_stream_encoder *enc1,
+	struct dc_context *ctx,
+	struct dc_bios *bp,
+	enum engine_id eng_id,
+	struct vpg *vpg,
+	struct afmt *afmt,
+	const struct dcn10_stream_enc_registers *regs,
+	const struct dcn10_stream_encoder_shift *se_shift,
+	const struct dcn10_stream_encoder_mask *se_mask);
+
+#endif /* __DC_DIO_STREAM_ENCODER_DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.c
new file mode 100644
index 0000000000000..f349cbe2a0f0c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "core_types.h"
+#include "reg_helper.h"
+#include "dcn32_dpp.h"
+#include "basics/conversion.h"
+#include "dcn30/dcn30_cm_common.h"
+
+/* Compute the maximum number of lines that we can fit in the line buffer */
+void dscl32_calc_lb_num_partitions(
+		const struct scaler_data *scl_data,
+		enum lb_memory_config lb_config,
+		int *num_part_y,
+		int *num_part_c)
+{
+	int memory_line_size_y, memory_line_size_c, memory_line_size_a,
+	lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a;
+
+	int line_size = scl_data->viewport.width < scl_data->recout.width ?
+			scl_data->viewport.width : scl_data->recout.width;
+	int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ?
+			scl_data->viewport_c.width : scl_data->recout.width;
+
+	if (line_size == 0)
+		line_size = 1;
+
+	if (line_size_c == 0)
+		line_size_c = 1;
+
+	memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */
+	memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */
+	memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */
+
+	if (lb_config == LB_MEMORY_CONFIG_1) {
+		lb_memory_size = 970;
+		lb_memory_size_c = 970;
+		lb_memory_size_a = 970;
+	} else if (lb_config == LB_MEMORY_CONFIG_2) {
+		lb_memory_size = 1290;
+		lb_memory_size_c = 1290;
+		lb_memory_size_a = 1290;
+	} else if (lb_config == LB_MEMORY_CONFIG_3) {
+		if (scl_data->viewport.width  == scl_data->h_active &&
+			scl_data->viewport.height == scl_data->v_active) {
+			/* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */
+			/* use increased LB size for calculation only if Scaler not enabled */
+			lb_memory_size = 970 + 1290 + 1170 + 1170 + 1170;
+			lb_memory_size_c = 970 + 1290;
+			lb_memory_size_a = 970 + 1290 + 1170;
+		} else {
+			/* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */
+			lb_memory_size = 970 + 1290 + 484 + 484 + 484;
+			lb_memory_size_c = 970 + 1290;
+			lb_memory_size_a = 970 + 1290 + 484;
+		}
+	} else {
+		if (scl_data->viewport.width  == scl_data->h_active &&
+			scl_data->viewport.height == scl_data->v_active) {
+			/* use increased LB size for calculation only if Scaler not enabled */
+			lb_memory_size = 970 + 1290 + 1170;
+			lb_memory_size_c = 970 + 1290 + 1170;
+			lb_memory_size_a = 970 + 1290 + 1170;
+		} else {
+			lb_memory_size = 970 + 1290 + 484;
+			lb_memory_size_c = 970 + 1290 + 484;
+			lb_memory_size_a = 970 + 1290 + 484;
+		}
+	}
+	*num_part_y = lb_memory_size / memory_line_size_y;
+	*num_part_c = lb_memory_size_c / memory_line_size_c;
+	num_partitions_a = lb_memory_size_a / memory_line_size_a;
+
+	if (scl_data->lb_params.alpha_en
+			&& (num_partitions_a < *num_part_y))
+		*num_part_y = num_partitions_a;
+
+	if (*num_part_y > 32)
+		*num_part_y = 32;
+	if (*num_part_c > 32)
+		*num_part_c = 32;
+}
+
+static struct dpp_funcs dcn32_dpp_funcs = {
+	.dpp_program_gamcor_lut		= dpp3_program_gamcor_lut,
+	.dpp_read_state				= dpp30_read_state,
+	.dpp_reset					= dpp_reset,
+	.dpp_set_scaler				= dpp1_dscl_set_scaler_manual_scale,
+	.dpp_get_optimal_number_of_taps	= dpp3_get_optimal_number_of_taps,
+	.dpp_set_gamut_remap		= dpp3_cm_set_gamut_remap,
+	.dpp_set_csc_adjustment		= NULL,
+	.dpp_set_csc_default		= NULL,
+	.dpp_program_regamma_pwl	= NULL,
+	.dpp_set_pre_degam			= dpp3_set_pre_degam,
+	.dpp_program_input_lut		= NULL,
+	.dpp_full_bypass			= dpp1_full_bypass,
+	.dpp_setup					= dpp3_cnv_setup,
+	.dpp_program_degamma_pwl	= NULL,
+	.dpp_program_cm_dealpha		= dpp3_program_cm_dealpha,
+	.dpp_program_cm_bias		= dpp3_program_cm_bias,
+
+	.dpp_program_blnd_lut		= NULL, // BLNDGAM is removed completely in DCN3.2 DPP
+	.dpp_program_shaper_lut		= NULL, // CM SHAPER block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)
+	.dpp_program_3dlut			= NULL, // CM 3DLUT block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)
+
+	.dpp_program_bias_and_scale	= NULL,
+	.dpp_cnv_set_alpha_keyer	= dpp2_cnv_set_alpha_keyer,
+	.set_cursor_attributes		= dpp3_set_cursor_attributes,
+	.set_cursor_position		= dpp1_set_cursor_position,
+	.set_optional_cursor_attributes	= dpp1_cnv_set_optional_cursor_attributes,
+	.dpp_dppclk_control			= dpp1_dppclk_control,
+	.dpp_set_hdr_multiplier		= dpp3_set_hdr_multiplier,
+};
+
+
+static struct dpp_caps dcn32_dpp_cap = {
+	.dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,
+	.max_lb_partitions = 31,
+	.dscl_calc_lb_num_partitions = dscl32_calc_lb_num_partitions,
+};
+
+bool dpp32_construct(
+	struct dcn3_dpp *dpp,
+	struct dc_context *ctx,
+	uint32_t inst,
+	const struct dcn3_dpp_registers *tf_regs,
+	const struct dcn3_dpp_shift *tf_shift,
+	const struct dcn3_dpp_mask *tf_mask)
+{
+	dpp->base.ctx = ctx;
+
+	dpp->base.inst = inst;
+	dpp->base.funcs = &dcn32_dpp_funcs;
+	dpp->base.caps = &dcn32_dpp_cap;
+
+	dpp->tf_regs = tf_regs;
+	dpp->tf_shift = tf_shift;
+	dpp->tf_mask = tf_mask;
+
+	return true;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.h
new file mode 100644
index 0000000000000..572958d287eb5
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.h
@@ -0,0 +1,38 @@
+/* Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DCN32_DPP_H__
+#define __DCN32_DPP_H__
+
+#include "dcn20/dcn20_dpp.h"
+#include "dcn30/dcn30_dpp.h"
+
+bool dpp32_construct(struct dcn3_dpp *dpp3,
+	struct dc_context *ctx,
+	uint32_t inst,
+	const struct dcn3_dpp_registers *tf_regs,
+	const struct dcn3_dpp_shift *tf_shift,
+	const struct dcn3_dpp_mask *tf_mask);
+
+#endif /* __DCN32_DPP_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.c
new file mode 100644
index 0000000000000..4dbad8d4b4fc2
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#include "dc_bios_types.h"
+#include "dcn31/dcn31_hpo_dp_link_encoder.h"
+#include "dcn32_hpo_dp_link_encoder.h"
+#include "reg_helper.h"
+#include "dc_link.h"
+#include "stream_encoder.h"
+
+#define DC_LOGGER \
+		enc3->base.ctx->logger
+
+#define REG(reg)\
+	(enc3->regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+	enc3->hpo_le_shift->field_name, enc3->hpo_le_mask->field_name
+
+#define CTX \
+	enc3->base.ctx
+
+static bool dcn32_hpo_dp_link_enc_is_in_alt_mode(
+		struct hpo_dp_link_encoder *enc)
+{
+	struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
+	uint32_t dp_alt_mode_disable = 0;
+
+	ASSERT((enc->transmitter >= TRANSMITTER_UNIPHY_A) && (enc->transmitter <= TRANSMITTER_UNIPHY_E));
+
+	/* if value == 1 alt mode is disabled, otherwise it is enabled */
+	REG_GET(RDPCSTX_PHY_CNTL6[enc->transmitter], RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
+	return (dp_alt_mode_disable == 0);
+}
+
+
+
+static struct hpo_dp_link_encoder_funcs dcn32_hpo_dp_link_encoder_funcs = {
+	.enable_link_phy = dcn31_hpo_dp_link_enc_enable_dp_output,
+	.disable_link_phy = dcn31_hpo_dp_link_enc_disable_output,
+	.link_enable = dcn31_hpo_dp_link_enc_enable,
+	.link_disable = dcn31_hpo_dp_link_enc_disable,
+	.set_link_test_pattern = dcn31_hpo_dp_link_enc_set_link_test_pattern,
+	.update_stream_allocation_table = dcn31_hpo_dp_link_enc_update_stream_allocation_table,
+	.set_throttled_vcp_size = dcn31_hpo_dp_link_enc_set_throttled_vcp_size,
+	.is_in_alt_mode = dcn32_hpo_dp_link_enc_is_in_alt_mode,
+	.read_state = dcn31_hpo_dp_link_enc_read_state,
+	.set_ffe = dcn31_hpo_dp_link_enc_set_ffe,
+};
+
+void hpo_dp_link_encoder32_construct(struct dcn31_hpo_dp_link_encoder *enc31,
+		struct dc_context *ctx,
+		uint32_t inst,
+		const struct dcn31_hpo_dp_link_encoder_registers *hpo_le_regs,
+		const struct dcn31_hpo_dp_link_encoder_shift *hpo_le_shift,
+		const struct dcn31_hpo_dp_link_encoder_mask *hpo_le_mask)
+{
+	enc31->base.ctx = ctx;
+
+	enc31->base.inst = inst;
+	enc31->base.funcs = &dcn32_hpo_dp_link_encoder_funcs;
+	enc31->base.hpd_source = HPD_SOURCEID_UNKNOWN;
+	enc31->base.transmitter = TRANSMITTER_UNKNOWN;
+
+	enc31->regs = hpo_le_regs;
+	enc31->hpo_le_shift = hpo_le_shift;
+	enc31->hpo_le_mask = hpo_le_mask;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.h
new file mode 100644
index 0000000000000..9db1323e19337
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_DCN32_HPO_DP_LINK_ENCODER_H__
+#define __DAL_DCN32_HPO_DP_LINK_ENCODER_H__
+
+#include "link_encoder.h"
+
+#define DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(mask_sh)\
+	SE_SF(DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC_CLOCK_EN, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, DPHY_RESET, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, DPHY_ENABLE, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, PRECODER_ENABLE, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, MODE, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, NUM_LANES, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS, STATUS, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS, SAT_UPDATE_PENDING, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS, RATE_UPDATE_PENDING, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0, TP_CUSTOM, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT0, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT1, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT2, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT3, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL0, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL1, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL2, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL3, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0, SAT_STREAM_SOURCE, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0, SAT_SLOT_COUNT, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0, STREAM_VC_RATE_X, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0, STREAM_VC_RATE_Y, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE, SAT_UPDATE, mask_sh)
+
+void hpo_dp_link_encoder32_construct(struct dcn31_hpo_dp_link_encoder *enc31,
+	struct dc_context *ctx,
+	uint32_t inst,
+	const struct dcn31_hpo_dp_link_encoder_registers *hpo_le_regs,
+	const struct dcn31_hpo_dp_link_encoder_shift *hpo_le_shift,
+	const struct dcn31_hpo_dp_link_encoder_mask *hpo_le_mask);
+
+#endif   // __DAL_DCN32_HPO_DP_LINK_ENCODER_H__
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
new file mode 100644
index 0000000000000..27813374f2bb7
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
@@ -0,0 +1,964 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "dcn30/dcn30_hubbub.h"
+#include "dcn32_hubbub.h"
+#include "dm_services.h"
+#include "reg_helper.h"
+
+
+#define CTX \
+	hubbub2->base.ctx
+#define DC_LOGGER \
+	hubbub2->base.ctx->logger
+#define REG(reg)\
+	hubbub2->regs->reg
+
+#undef FN
+#define FN(reg_name, field_name) \
+	hubbub2->shifts->field_name, hubbub2->masks->field_name
+
+#define DCN32_CRB_SEGMENT_SIZE_KB 64
+
+static void dcn32_init_crb(struct hubbub *hubbub)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+
+	REG_GET(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT,
+		&hubbub2->det0_size);
+
+	REG_GET(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT,
+		&hubbub2->det1_size);
+
+	REG_GET(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT,
+		&hubbub2->det2_size);
+
+	REG_GET(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT,
+		&hubbub2->det3_size);
+
+	REG_GET(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT,
+		&hubbub2->compbuf_size_segments);
+
+	REG_SET_2(COMPBUF_RESERVED_SPACE, 0,
+			COMPBUF_RESERVED_SPACE_64B, hubbub2->pixel_chunk_size / 32,
+			COMPBUF_RESERVED_SPACE_ZS, hubbub2->pixel_chunk_size / 128);
+	REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x17F);
+}
+
+static void dcn32_program_det_size(struct hubbub *hubbub, int hubp_inst, unsigned int det_buffer_size_in_kbyte)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+
+	unsigned int det_size_segments = (det_buffer_size_in_kbyte + DCN32_CRB_SEGMENT_SIZE_KB - 1) / DCN32_CRB_SEGMENT_SIZE_KB;
+
+	switch (hubp_inst) {
+	case 0:
+		REG_UPDATE(DCHUBBUB_DET0_CTRL,
+					DET0_SIZE, det_size_segments);
+		hubbub2->det0_size = det_size_segments;
+		break;
+	case 1:
+		REG_UPDATE(DCHUBBUB_DET1_CTRL,
+					DET1_SIZE, det_size_segments);
+		hubbub2->det1_size = det_size_segments;
+		break;
+	case 2:
+		REG_UPDATE(DCHUBBUB_DET2_CTRL,
+					DET2_SIZE, det_size_segments);
+		hubbub2->det2_size = det_size_segments;
+		break;
+	case 3:
+		REG_UPDATE(DCHUBBUB_DET3_CTRL,
+					DET3_SIZE, det_size_segments);
+		hubbub2->det3_size = det_size_segments;
+		break;
+	default:
+		break;
+	}
+	/* Should never be hit, if it is we have an erroneous hw config*/
+	ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size
+			+ hubbub2->det3_size + hubbub2->compbuf_size_segments <= hubbub2->crb_size_segs);
+}
+
+static void dcn32_program_compbuf_size(struct hubbub *hubbub, unsigned int compbuf_size_kb, bool safe_to_increase)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	unsigned int compbuf_size_segments = (compbuf_size_kb + DCN32_CRB_SEGMENT_SIZE_KB - 1) / DCN32_CRB_SEGMENT_SIZE_KB;
+
+	if (safe_to_increase || compbuf_size_segments <= hubbub2->compbuf_size_segments) {
+		if (compbuf_size_segments > hubbub2->compbuf_size_segments) {
+			REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1, 100);
+			REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2->det1_size, 1, 100);
+			REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2->det2_size, 1, 100);
+			REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2->det3_size, 1, 100);
+		}
+		/* Should never be hit, if it is we have an erroneous hw config*/
+		ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size
+				+ hubbub2->det3_size + compbuf_size_segments <= hubbub2->crb_size_segs);
+		REG_UPDATE(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, compbuf_size_segments);
+		REG_WAIT(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, compbuf_size_segments, 1, 100);
+		hubbub2->compbuf_size_segments = compbuf_size_segments;
+	}
+}
+
+static uint32_t convert_and_clamp(
+	uint32_t wm_ns,
+	uint32_t refclk_mhz,
+	uint32_t clamp_value)
+{
+	uint32_t ret_val = 0;
+	ret_val = wm_ns * refclk_mhz;
+
+	ret_val /= 1000;
+
+	if (ret_val > clamp_value)
+		ret_val = clamp_value;
+
+	return ret_val;
+}
+
+static bool hubbub32_program_urgent_watermarks(
+		struct hubbub *hubbub,
+		struct dcn_watermark_set *watermarks,
+		unsigned int refclk_mhz,
+		bool safe_to_lower)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	uint32_t prog_wm_value;
+	bool wm_pending = false;
+
+	/* Repeat for water mark set A, B, C and D. */
+	/* clock state A */
+	if (safe_to_lower || watermarks->a.urgent_ns > hubbub2->watermarks.a.urgent_ns) {
+		hubbub2->watermarks.a.urgent_ns = watermarks->a.urgent_ns;
+		prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,
+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
+
+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_A calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->a.urgent_ns, prog_wm_value);
+	} else if (watermarks->a.urgent_ns < hubbub2->watermarks.a.urgent_ns)
+		wm_pending = true;
+
+	/* determine the transfer time for a quantity of data for a particular requestor.*/
+	if (safe_to_lower || watermarks->a.frac_urg_bw_flip
+			> hubbub2->watermarks.a.frac_urg_bw_flip) {
+		hubbub2->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, watermarks->a.frac_urg_bw_flip);
+	} else if (watermarks->a.frac_urg_bw_flip
+			< hubbub2->watermarks.a.frac_urg_bw_flip)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->a.frac_urg_bw_nom
+			> hubbub2->watermarks.a.frac_urg_bw_nom) {
+		hubbub2->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, watermarks->a.frac_urg_bw_nom);
+	} else if (watermarks->a.frac_urg_bw_nom
+			< hubbub2->watermarks.a.frac_urg_bw_nom)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->a.urgent_latency_ns > hubbub2->watermarks.a.urgent_latency_ns) {
+		hubbub2->watermarks.a.urgent_latency_ns = watermarks->a.urgent_latency_ns;
+		prog_wm_value = convert_and_clamp(watermarks->a.urgent_latency_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0,
+				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, prog_wm_value);
+	} else if (watermarks->a.urgent_latency_ns < hubbub2->watermarks.a.urgent_latency_ns)
+		wm_pending = true;
+
+	/* clock state B */
+	if (safe_to_lower || watermarks->b.urgent_ns > hubbub2->watermarks.b.urgent_ns) {
+		hubbub2->watermarks.b.urgent_ns = watermarks->b.urgent_ns;
+		prog_wm_value = convert_and_clamp(watermarks->b.urgent_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0,
+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
+
+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_B calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->b.urgent_ns, prog_wm_value);
+	} else if (watermarks->b.urgent_ns < hubbub2->watermarks.b.urgent_ns)
+		wm_pending = true;
+
+	/* determine the transfer time for a quantity of data for a particular requestor.*/
+	if (safe_to_lower || watermarks->b.frac_urg_bw_flip
+			> hubbub2->watermarks.b.frac_urg_bw_flip) {
+		hubbub2->watermarks.b.frac_urg_bw_flip = watermarks->b.frac_urg_bw_flip;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, watermarks->b.frac_urg_bw_flip);
+	} else if (watermarks->b.frac_urg_bw_flip
+			< hubbub2->watermarks.b.frac_urg_bw_flip)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->b.frac_urg_bw_nom
+			> hubbub2->watermarks.b.frac_urg_bw_nom) {
+		hubbub2->watermarks.b.frac_urg_bw_nom = watermarks->b.frac_urg_bw_nom;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, watermarks->b.frac_urg_bw_nom);
+	} else if (watermarks->b.frac_urg_bw_nom
+			< hubbub2->watermarks.b.frac_urg_bw_nom)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->b.urgent_latency_ns > hubbub2->watermarks.b.urgent_latency_ns) {
+		hubbub2->watermarks.b.urgent_latency_ns = watermarks->b.urgent_latency_ns;
+		prog_wm_value = convert_and_clamp(watermarks->b.urgent_latency_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0,
+				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, prog_wm_value);
+	} else if (watermarks->b.urgent_latency_ns < hubbub2->watermarks.b.urgent_latency_ns)
+		wm_pending = true;
+
+	/* clock state C */
+	if (safe_to_lower || watermarks->c.urgent_ns > hubbub2->watermarks.c.urgent_ns) {
+		hubbub2->watermarks.c.urgent_ns = watermarks->c.urgent_ns;
+		prog_wm_value = convert_and_clamp(watermarks->c.urgent_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0,
+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
+
+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_C calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->c.urgent_ns, prog_wm_value);
+	} else if (watermarks->c.urgent_ns < hubbub2->watermarks.c.urgent_ns)
+		wm_pending = true;
+
+	/* determine the transfer time for a quantity of data for a particular requestor.*/
+	if (safe_to_lower || watermarks->c.frac_urg_bw_flip
+			> hubbub2->watermarks.c.frac_urg_bw_flip) {
+		hubbub2->watermarks.c.frac_urg_bw_flip = watermarks->c.frac_urg_bw_flip;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, watermarks->c.frac_urg_bw_flip);
+	} else if (watermarks->c.frac_urg_bw_flip
+			< hubbub2->watermarks.c.frac_urg_bw_flip)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->c.frac_urg_bw_nom
+			> hubbub2->watermarks.c.frac_urg_bw_nom) {
+		hubbub2->watermarks.c.frac_urg_bw_nom = watermarks->c.frac_urg_bw_nom;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, watermarks->c.frac_urg_bw_nom);
+	} else if (watermarks->c.frac_urg_bw_nom
+			< hubbub2->watermarks.c.frac_urg_bw_nom)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->c.urgent_latency_ns > hubbub2->watermarks.c.urgent_latency_ns) {
+		hubbub2->watermarks.c.urgent_latency_ns = watermarks->c.urgent_latency_ns;
+		prog_wm_value = convert_and_clamp(watermarks->c.urgent_latency_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, 0,
+				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, prog_wm_value);
+	} else if (watermarks->c.urgent_latency_ns < hubbub2->watermarks.c.urgent_latency_ns)
+		wm_pending = true;
+
+	/* clock state D */
+	if (safe_to_lower || watermarks->d.urgent_ns > hubbub2->watermarks.d.urgent_ns) {
+		hubbub2->watermarks.d.urgent_ns = watermarks->d.urgent_ns;
+		prog_wm_value = convert_and_clamp(watermarks->d.urgent_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0,
+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
+
+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_D calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->d.urgent_ns, prog_wm_value);
+	} else if (watermarks->d.urgent_ns < hubbub2->watermarks.d.urgent_ns)
+		wm_pending = true;
+
+	/* determine the transfer time for a quantity of data for a particular requestor.*/
+	if (safe_to_lower || watermarks->d.frac_urg_bw_flip
+			> hubbub2->watermarks.d.frac_urg_bw_flip) {
+		hubbub2->watermarks.d.frac_urg_bw_flip = watermarks->d.frac_urg_bw_flip;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, watermarks->d.frac_urg_bw_flip);
+	} else if (watermarks->d.frac_urg_bw_flip
+			< hubbub2->watermarks.d.frac_urg_bw_flip)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->d.frac_urg_bw_nom
+			> hubbub2->watermarks.d.frac_urg_bw_nom) {
+		hubbub2->watermarks.d.frac_urg_bw_nom = watermarks->d.frac_urg_bw_nom;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, watermarks->d.frac_urg_bw_nom);
+	} else if (watermarks->d.frac_urg_bw_nom
+			< hubbub2->watermarks.d.frac_urg_bw_nom)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->d.urgent_latency_ns > hubbub2->watermarks.d.urgent_latency_ns) {
+		hubbub2->watermarks.d.urgent_latency_ns = watermarks->d.urgent_latency_ns;
+		prog_wm_value = convert_and_clamp(watermarks->d.urgent_latency_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, 0,
+				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, prog_wm_value);
+	} else if (watermarks->d.urgent_latency_ns < hubbub2->watermarks.d.urgent_latency_ns)
+		wm_pending = true;
+
+	return wm_pending;
+}
+
+static bool hubbub32_program_stutter_watermarks(
+		struct hubbub *hubbub,
+		struct dcn_watermark_set *watermarks,
+		unsigned int refclk_mhz,
+		bool safe_to_lower)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	uint32_t prog_wm_value;
+	bool wm_pending = false;
+
+	/* clock state A */
+	if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns
+			> hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) {
+		hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
+				watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+	} else if (watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns
+			< hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_ns
+			> hubbub2->watermarks.a.cstate_pstate.cstate_exit_ns) {
+		hubbub2->watermarks.a.cstate_pstate.cstate_exit_ns =
+				watermarks->a.cstate_pstate.cstate_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->a.cstate_pstate.cstate_exit_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_A calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
+	} else if (watermarks->a.cstate_pstate.cstate_exit_ns
+			< hubbub2->watermarks.a.cstate_pstate.cstate_exit_ns)
+		wm_pending = true;
+
+	/* clock state B */
+	if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns
+			> hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) {
+		hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
+				watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_B calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+	} else if (watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns
+			< hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_ns
+			> hubbub2->watermarks.b.cstate_pstate.cstate_exit_ns) {
+		hubbub2->watermarks.b.cstate_pstate.cstate_exit_ns =
+				watermarks->b.cstate_pstate.cstate_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->b.cstate_pstate.cstate_exit_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_B calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
+	} else if (watermarks->b.cstate_pstate.cstate_exit_ns
+			< hubbub2->watermarks.b.cstate_pstate.cstate_exit_ns)
+		wm_pending = true;
+
+	/* clock state C */
+	if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns
+			> hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) {
+		hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
+				watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_C calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+	} else if (watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns
+			< hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_ns
+			> hubbub2->watermarks.c.cstate_pstate.cstate_exit_ns) {
+		hubbub2->watermarks.c.cstate_pstate.cstate_exit_ns =
+				watermarks->c.cstate_pstate.cstate_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->c.cstate_pstate.cstate_exit_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_C calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
+	} else if (watermarks->c.cstate_pstate.cstate_exit_ns
+			< hubbub2->watermarks.c.cstate_pstate.cstate_exit_ns)
+		wm_pending = true;
+
+	/* clock state D */
+	if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns
+			> hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) {
+		hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
+				watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_D calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+	} else if (watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns
+			< hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_ns
+			> hubbub2->watermarks.d.cstate_pstate.cstate_exit_ns) {
+		hubbub2->watermarks.d.cstate_pstate.cstate_exit_ns =
+				watermarks->d.cstate_pstate.cstate_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->d.cstate_pstate.cstate_exit_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_D calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
+	} else if (watermarks->d.cstate_pstate.cstate_exit_ns
+			< hubbub2->watermarks.d.cstate_pstate.cstate_exit_ns)
+		wm_pending = true;
+
+	return wm_pending;
+}
+
+
+static bool hubbub32_program_pstate_watermarks(
+		struct hubbub *hubbub,
+		struct dcn_watermark_set *watermarks,
+		unsigned int refclk_mhz,
+		bool safe_to_lower)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	uint32_t prog_wm_value;
+
+	bool wm_pending = false;
+
+	/* Section for UCLK_PSTATE_CHANGE_WATERMARKS */
+	/* clock state A */
+	if (safe_to_lower || watermarks->a.cstate_pstate.pstate_change_ns
+			> hubbub2->watermarks.a.cstate_pstate.pstate_change_ns) {
+		hubbub2->watermarks.a.cstate_pstate.pstate_change_ns =
+				watermarks->a.cstate_pstate.pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->a.cstate_pstate.pstate_change_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, 0,
+				DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
+	} else if (watermarks->a.cstate_pstate.pstate_change_ns
+			< hubbub2->watermarks.a.cstate_pstate.pstate_change_ns)
+		wm_pending = true;
+
+	/* clock state B */
+	if (safe_to_lower || watermarks->b.cstate_pstate.pstate_change_ns
+			> hubbub2->watermarks.b.cstate_pstate.pstate_change_ns) {
+		hubbub2->watermarks.b.cstate_pstate.pstate_change_ns =
+				watermarks->b.cstate_pstate.pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->b.cstate_pstate.pstate_change_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, 0,
+				DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
+	} else if (watermarks->b.cstate_pstate.pstate_change_ns
+			< hubbub2->watermarks.b.cstate_pstate.pstate_change_ns)
+		wm_pending = true;
+
+	/* clock state C */
+	if (safe_to_lower || watermarks->c.cstate_pstate.pstate_change_ns
+			> hubbub2->watermarks.c.cstate_pstate.pstate_change_ns) {
+		hubbub2->watermarks.c.cstate_pstate.pstate_change_ns =
+				watermarks->c.cstate_pstate.pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->c.cstate_pstate.pstate_change_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, 0,
+				DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
+	} else if (watermarks->c.cstate_pstate.pstate_change_ns
+			< hubbub2->watermarks.c.cstate_pstate.pstate_change_ns)
+		wm_pending = true;
+
+	/* clock state D */
+	if (safe_to_lower || watermarks->d.cstate_pstate.pstate_change_ns
+			> hubbub2->watermarks.d.cstate_pstate.pstate_change_ns) {
+		hubbub2->watermarks.d.cstate_pstate.pstate_change_ns =
+				watermarks->d.cstate_pstate.pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->d.cstate_pstate.pstate_change_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, 0,
+				DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
+	} else if (watermarks->d.cstate_pstate.pstate_change_ns
+			< hubbub2->watermarks.d.cstate_pstate.pstate_change_ns)
+		wm_pending = true;
+
+	/* Section for FCLK_PSTATE_CHANGE_WATERMARKS */
+	/* clock state A */
+	if (safe_to_lower || watermarks->a.cstate_pstate.fclk_pstate_change_ns
+			> hubbub2->watermarks.a.cstate_pstate.fclk_pstate_change_ns) {
+		hubbub2->watermarks.a.cstate_pstate.fclk_pstate_change_ns =
+				watermarks->a.cstate_pstate.fclk_pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->a.cstate_pstate.fclk_pstate_change_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, 0,
+				DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("FCLK_CHANGE_WATERMARK_A calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->a.cstate_pstate.fclk_pstate_change_ns, prog_wm_value);
+	} else if (watermarks->a.cstate_pstate.fclk_pstate_change_ns
+			< hubbub2->watermarks.a.cstate_pstate.fclk_pstate_change_ns)
+		wm_pending = true;
+
+	/* clock state B */
+	if (safe_to_lower || watermarks->b.cstate_pstate.fclk_pstate_change_ns
+			> hubbub2->watermarks.b.cstate_pstate.fclk_pstate_change_ns) {
+		hubbub2->watermarks.b.cstate_pstate.fclk_pstate_change_ns =
+				watermarks->b.cstate_pstate.fclk_pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->b.cstate_pstate.fclk_pstate_change_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, 0,
+				DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("FCLK_CHANGE_WATERMARK_B calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->b.cstate_pstate.fclk_pstate_change_ns, prog_wm_value);
+	} else if (watermarks->b.cstate_pstate.fclk_pstate_change_ns
+			< hubbub2->watermarks.b.cstate_pstate.fclk_pstate_change_ns)
+		wm_pending = true;
+
+	/* clock state C */
+	if (safe_to_lower || watermarks->c.cstate_pstate.fclk_pstate_change_ns
+			> hubbub2->watermarks.c.cstate_pstate.fclk_pstate_change_ns) {
+		hubbub2->watermarks.c.cstate_pstate.fclk_pstate_change_ns =
+				watermarks->c.cstate_pstate.fclk_pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->c.cstate_pstate.fclk_pstate_change_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, 0,
+				DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("FCLK_CHANGE_WATERMARK_C calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->c.cstate_pstate.fclk_pstate_change_ns, prog_wm_value);
+	} else if (watermarks->c.cstate_pstate.fclk_pstate_change_ns
+			< hubbub2->watermarks.c.cstate_pstate.fclk_pstate_change_ns)
+		wm_pending = true;
+
+	/* clock state D */
+	if (safe_to_lower || watermarks->d.cstate_pstate.fclk_pstate_change_ns
+			> hubbub2->watermarks.d.cstate_pstate.fclk_pstate_change_ns) {
+		hubbub2->watermarks.d.cstate_pstate.fclk_pstate_change_ns =
+				watermarks->d.cstate_pstate.fclk_pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->d.cstate_pstate.fclk_pstate_change_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, 0,
+				DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("FCLK_CHANGE_WATERMARK_D calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->d.cstate_pstate.fclk_pstate_change_ns, prog_wm_value);
+	} else if (watermarks->d.cstate_pstate.fclk_pstate_change_ns
+			< hubbub2->watermarks.d.cstate_pstate.fclk_pstate_change_ns)
+		wm_pending = true;
+
+	return wm_pending;
+}
+
+
+static bool hubbub32_program_usr_watermarks(
+		struct hubbub *hubbub,
+		struct dcn_watermark_set *watermarks,
+		unsigned int refclk_mhz,
+		bool safe_to_lower)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	uint32_t prog_wm_value;
+
+	bool wm_pending = false;
+
+	/* clock state A */
+	if (safe_to_lower || watermarks->a.usr_retraining_ns
+			> hubbub2->watermarks.a.usr_retraining_ns) {
+		hubbub2->watermarks.a.usr_retraining_ns = watermarks->a.usr_retraining_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->a.usr_retraining_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, 0,
+				DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("USR_RETRAINING_WATERMARK_A calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->a.usr_retraining_ns, prog_wm_value);
+	} else if (watermarks->a.usr_retraining_ns
+			< hubbub2->watermarks.a.usr_retraining_ns)
+		wm_pending = true;
+
+	/* clock state B */
+	if (safe_to_lower || watermarks->b.usr_retraining_ns
+			> hubbub2->watermarks.b.usr_retraining_ns) {
+		hubbub2->watermarks.b.usr_retraining_ns = watermarks->b.usr_retraining_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->b.usr_retraining_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, 0,
+				DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("USR_RETRAINING_WATERMARK_B calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->b.usr_retraining_ns, prog_wm_value);
+	} else if (watermarks->b.usr_retraining_ns
+			< hubbub2->watermarks.b.usr_retraining_ns)
+		wm_pending = true;
+
+	/* clock state C */
+	if (safe_to_lower || watermarks->c.usr_retraining_ns
+			> hubbub2->watermarks.c.usr_retraining_ns) {
+		hubbub2->watermarks.c.usr_retraining_ns =
+				watermarks->c.usr_retraining_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->c.usr_retraining_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, 0,
+				DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("USR_RETRAINING_WATERMARK_C calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->c.usr_retraining_ns, prog_wm_value);
+	} else if (watermarks->c.usr_retraining_ns
+			< hubbub2->watermarks.c.usr_retraining_ns)
+		wm_pending = true;
+
+	/* clock state D */
+	if (safe_to_lower || watermarks->d.usr_retraining_ns
+			> hubbub2->watermarks.d.usr_retraining_ns) {
+		hubbub2->watermarks.d.usr_retraining_ns =
+				watermarks->d.usr_retraining_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->d.usr_retraining_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, 0,
+				DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("USR_RETRAINING_WATERMARK_D calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->d.usr_retraining_ns, prog_wm_value);
+	} else if (watermarks->d.usr_retraining_ns
+			< hubbub2->watermarks.d.usr_retraining_ns)
+		wm_pending = true;
+
+	return wm_pending;
+}
+
+void hubbub32_force_usr_retraining_allow(struct hubbub *hubbub, bool allow)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+
+	/*
+	 * DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE = 1 means enabling forcing value
+	 * DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE = 1 or 0,  means value to be forced when force enable
+	 */
+
+	REG_UPDATE_2(DCHUBBUB_ARB_USR_RETRAINING_CNTL,
+			DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE, allow,
+			DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE, allow);
+}
+
+static bool hubbub32_program_watermarks(
+		struct hubbub *hubbub,
+		struct dcn_watermark_set *watermarks,
+		unsigned int refclk_mhz,
+		bool safe_to_lower)
+{
+	bool wm_pending = false;
+
+	if (hubbub32_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
+		wm_pending = true;
+
+	if (hubbub32_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
+		wm_pending = true;
+
+	if (hubbub32_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
+		wm_pending = true;
+
+	if (hubbub32_program_usr_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
+		wm_pending = true;
+
+	/*
+	 * The DCHub arbiter has a mechanism to dynamically rate limit the DCHub request stream to the fabric.
+	 * If the memory controller is fully utilized and the DCHub requestors are
+	 * well ahead of their amortized schedule, then it is safe to prevent the next winner
+	 * from being committed and sent to the fabric.
+	 * The utilization of the memory controller is approximated by ensuring that
+	 * the number of outstanding requests is greater than a threshold specified
+	 * by the ARB_MIN_REQ_OUTSTANDING. To determine that the DCHub requestors are well ahead of the amortized schedule,
+	 * the slack of the next winner is compared with the ARB_SAT_LEVEL in DLG RefClk cycles.
+	 *
+	 * TODO: Revisit request limit after figure out right number. request limit for RM isn't decided yet, set maximum value (0x1FF)
+	 * to turn off it for now.
+	 */
+	/*REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,
+			DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
+	REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
+			DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);*/
+
+	hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
+
+	hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow);
+
+	return wm_pending;
+}
+
+/* Copy values from WM set A to all other sets */
+void hubbub32_init_watermarks(struct hubbub *hubbub)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	uint32_t reg;
+
+	reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
+	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A);
+	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A);
+	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A);
+	REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A);
+	REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A);
+	REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A);
+	REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, reg);
+}
+
+void hubbub32_wm_read_state(struct hubbub *hubbub,
+		struct dcn_hubbub_wm *wm)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	struct dcn_hubbub_wm_set *s;
+
+	memset(wm, 0, sizeof(struct dcn_hubbub_wm));
+
+	s = &wm->sets[0];
+	s->wm_set = 0;
+	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A,
+			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, &s->data_urgent);
+
+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A,
+			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, &s->sr_enter);
+
+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A,
+			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, &s->sr_exit);
+
+	REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A,
+			 DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, &s->dram_clk_chanage);
+
+	REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A,
+			 DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, &s->usr_retrain);
+
+	REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A,
+			 DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, &s->fclk_pstate_change);
+
+	s = &wm->sets[1];
+	s->wm_set = 1;
+	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B,
+			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, &s->data_urgent);
+
+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B,
+			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, &s->sr_enter);
+
+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B,
+			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, &s->sr_exit);
+
+	REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B,
+			DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, &s->dram_clk_chanage);
+
+	REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B,
+			 DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, &s->usr_retrain);
+
+	REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B,
+			DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, &s->fclk_pstate_change);
+
+	s = &wm->sets[2];
+	s->wm_set = 2;
+	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C,
+			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, &s->data_urgent);
+
+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C,
+			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, &s->sr_enter);
+
+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C,
+			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, &s->sr_exit);
+
+	REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C,
+			DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, &s->dram_clk_chanage);
+
+	REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C,
+			 DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, &s->usr_retrain);
+
+	REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C,
+			DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, &s->fclk_pstate_change);
+
+	s = &wm->sets[3];
+	s->wm_set = 3;
+	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D,
+			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, &s->data_urgent);
+
+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D,
+			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, &s->sr_enter);
+
+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D,
+			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, &s->sr_exit);
+
+	REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D,
+			DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, &s->dram_clk_chanage);
+
+	REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D,
+			 DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, &s->usr_retrain);
+
+	REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D,
+			DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, &s->fclk_pstate_change);
+}
+
+void hubbub32_force_wm_propagate_to_pipes(struct hubbub *hubbub)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	uint32_t refclk_mhz = hubbub->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
+	uint32_t prog_wm_value = convert_and_clamp(hubbub2->watermarks.a.urgent_ns,
+			refclk_mhz, 0x3fff);
+
+	REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,
+			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
+}
+
+static const struct hubbub_funcs hubbub32_funcs = {
+	.update_dchub = hubbub2_update_dchub,
+	.init_dchub_sys_ctx = hubbub3_init_dchub_sys_ctx,
+	.init_vm_ctx = hubbub2_init_vm_ctx,
+	.dcc_support_swizzle = hubbub3_dcc_support_swizzle,
+	.dcc_support_pixel_format = hubbub2_dcc_support_pixel_format,
+	.get_dcc_compression_cap = hubbub3_get_dcc_compression_cap,
+	.wm_read_state = hubbub32_wm_read_state,
+	.get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,
+	.program_watermarks = hubbub32_program_watermarks,
+	.allow_self_refresh_control = hubbub1_allow_self_refresh_control,
+	.is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
+	.force_wm_propagate_to_pipes = hubbub32_force_wm_propagate_to_pipes,
+	.force_pstate_change_control = hubbub3_force_pstate_change_control,
+	.init_watermarks = hubbub32_init_watermarks,
+	.program_det_size = dcn32_program_det_size,
+	.program_compbuf_size = dcn32_program_compbuf_size,
+	.init_crb = dcn32_init_crb,
+	.hubbub_read_state = hubbub2_read_state,
+	.force_usr_retraining_allow = hubbub32_force_usr_retraining_allow,
+};
+
+void hubbub32_construct(struct dcn20_hubbub *hubbub2,
+	struct dc_context *ctx,
+	const struct dcn_hubbub_registers *hubbub_regs,
+	const struct dcn_hubbub_shift *hubbub_shift,
+	const struct dcn_hubbub_mask *hubbub_mask,
+	int det_size_kb,
+	int pixel_chunk_size_kb,
+	int config_return_buffer_size_kb)
+{
+	hubbub2->base.ctx = ctx;
+	hubbub2->base.funcs = &hubbub32_funcs;
+	hubbub2->regs = hubbub_regs;
+	hubbub2->shifts = hubbub_shift;
+	hubbub2->masks = hubbub_mask;
+
+	hubbub2->debug_test_index_pstate = 0xB;
+	hubbub2->detile_buf_size = det_size_kb * 1024;
+	hubbub2->pixel_chunk_size = pixel_chunk_size_kb * 1024;
+	hubbub2->crb_size_segs = config_return_buffer_size_kb / DCN32_CRB_SEGMENT_SIZE_KB;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h
new file mode 100644
index 0000000000000..8d3ea8ee5b3b4
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_HUBBUB_DCN32_H__
+#define __DC_HUBBUB_DCN32_H__
+
+#include "dcn21/dcn21_hubbub.h"
+
+#define HUBBUB_REG_LIST_DCN32(id)\
+	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
+	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
+	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
+	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
+	SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
+	SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
+	SR(DCHUBBUB_ARB_SAT_LEVEL),\
+	SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
+	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
+	SR(DCHUBBUB_SOFT_RESET),\
+	SR(DCHUBBUB_CRC_CTRL), \
+	SR(DCN_VM_FB_LOCATION_BASE),\
+	SR(DCN_VM_FB_LOCATION_TOP),\
+	SR(DCN_VM_FB_OFFSET),\
+	SR(DCN_VM_AGP_BOT),\
+	SR(DCN_VM_AGP_TOP),\
+	SR(DCN_VM_AGP_BASE),\
+	HUBBUB_SR_WATERMARK_REG_LIST(), \
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\
+	SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\
+	SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\
+	SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C),\
+	SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D),\
+	SR(DCHUBBUB_DET0_CTRL),\
+	SR(DCHUBBUB_DET1_CTRL),\
+	SR(DCHUBBUB_DET2_CTRL),\
+	SR(DCHUBBUB_DET3_CTRL),\
+	SR(DCHUBBUB_COMPBUF_CTRL),\
+	SR(COMPBUF_RESERVED_SPACE),\
+	SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL),\
+	SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A),\
+	SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B),\
+	SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C),\
+	SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D),\
+	SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A),\
+	SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B),\
+	SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C),\
+	SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D),\
+	SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A),\
+	SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B),\
+	SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C),\
+	SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D),\
+	SR(DCN_VM_FAULT_ADDR_MSB),\
+	SR(DCN_VM_FAULT_ADDR_LSB),\
+	SR(DCN_VM_FAULT_CNTL),\
+	SR(DCN_VM_FAULT_STATUS)
+
+#define HUBBUB_MASK_SH_LIST_DCN32(mask_sh)\
+	HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_SOFT_RESET, DCHUBBUB_GLOBAL_SOFT_RESET, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, mask_sh), \
+	HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
+	HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
+	HUBBUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh), \
+	HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \
+	HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \
+	HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \
+	HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
+	HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET2_CTRL, DET2_SIZE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET3_CTRL, DET3_SIZE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, mask_sh),\
+	HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_64B, mask_sh),\
+	HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_ZS, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_ADDR_MSB, DCN_VM_FAULT_ADDR_MSB, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_ADDR_LSB, DCN_VM_FAULT_ADDR_LSB, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_CLEAR, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_INTERRUPT_ENABLE, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_RANGE_FAULT_DISABLE, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_PRQ_FAULT_DISABLE, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_TABLE_LEVEL, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh)
+
+
+void hubbub32_construct(struct dcn20_hubbub *hubbub2,
+	struct dc_context *ctx,
+	const struct dcn_hubbub_registers *hubbub_regs,
+	const struct dcn_hubbub_shift *hubbub_shift,
+	const struct dcn_hubbub_mask *hubbub_mask,
+	int det_size_kb,
+	int pixel_chunk_size_kb,
+	int config_return_buffer_size_kb);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c
new file mode 100644
index 0000000000000..0a7d64306481b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2012-20 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "dce_calcs.h"
+#include "reg_helper.h"
+#include "basics/conversion.h"
+#include "dcn32_hubp.h"
+
+#define REG(reg)\
+	hubp2->hubp_regs->reg
+
+#define CTX \
+	hubp2->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+	hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
+
+void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow)
+{
+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+	REG_UPDATE_2(UCLK_PSTATE_FORCE,
+			DATA_UCLK_PSTATE_FORCE_EN, pstate_disallow,
+			DATA_UCLK_PSTATE_FORCE_VALUE, 0);
+}
+
+void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel)
+{
+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+
+	// Also cache cursor in MALL if using MALL for SS
+	REG_UPDATE_2(DCHUBP_MALL_CONFIG, USE_MALL_SEL, mall_sel,
+			USE_MALL_FOR_CURSOR, mall_sel == 2 ? 1 : 0);
+}
+
+void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable)
+{
+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+	REG_UPDATE(DCHUBP_VMPG_CONFIG, FORCE_ONE_ROW_FOR_FRAME, enable);
+
+	/* Programming guide suggests CURSOR_REQ_MODE = 1 for SubVP:
+	 * For Pstate change using the MALL with sub-viewport buffering,
+	 * the cursor does not use the MALL (USE_MALL_FOR_CURSOR is ignored)
+	 * and sub-viewport positioning by Display FW has to avoid the cursor
+	 * requests to DRAM (set CURSOR_REQ_MODE = 1 to minimize this exclusion).
+	 *
+	 * CURSOR_REQ_MODE = 1 begins fetching cursor data at the beginning of display prefetch.
+	 * Setting this should allow the sub-viewport position to always avoid the cursor because
+	 * we do not allow the sub-viewport region to overlap with display prefetch (i.e. during blank).
+	 */
+	REG_UPDATE(CURSOR_CONTROL, CURSOR_REQ_MODE, enable);
+}
+
+void hubp32_phantom_hubp_post_enable(struct hubp *hubp)
+{
+	uint32_t reg_val;
+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+
+	REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, 1);
+	reg_val = REG_READ(DCHUBP_CNTL);
+	if (reg_val) {
+		/* init sequence workaround: in case HUBP is
+		 * power gated, this wait would timeout.
+		 *
+		 * we just wrote reg_val to non-0, if it stay 0
+		 * it means HUBP is gated
+		 */
+		REG_WAIT(DCHUBP_CNTL,
+				HUBP_NO_OUTSTANDING_REQ, 1,
+				1, 200);
+	}
+}
+
+static struct hubp_funcs dcn32_hubp_funcs = {
+	.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
+	.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
+	.hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr,
+	.hubp_program_surface_config = hubp3_program_surface_config,
+	.hubp_is_flip_pending = hubp2_is_flip_pending,
+	.hubp_setup = hubp3_setup,
+	.hubp_setup_interdependent = hubp2_setup_interdependent,
+	.hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings,
+	.set_blank = hubp2_set_blank,
+	.dcc_control = hubp3_dcc_control,
+	.mem_program_viewport = min_set_viewport,
+	.set_cursor_attributes	= hubp2_cursor_set_attributes,
+	.set_cursor_position	= hubp2_cursor_set_position,
+	.hubp_clk_cntl = hubp2_clk_cntl,
+	.hubp_vtg_sel = hubp2_vtg_sel,
+	.dmdata_set_attributes = hubp3_dmdata_set_attributes,
+	.dmdata_load = hubp2_dmdata_load,
+	.dmdata_status_done = hubp2_dmdata_status_done,
+	.hubp_read_state = hubp3_read_state,
+	.hubp_clear_underflow = hubp2_clear_underflow,
+	.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
+	.hubp_init = hubp3_init,
+	.set_unbounded_requesting = hubp31_set_unbounded_requesting,
+	.hubp_soft_reset = hubp31_soft_reset,
+	.hubp_in_blank = hubp1_in_blank,
+	.hubp_update_force_pstate_disallow = hubp32_update_force_pstate_disallow,
+	.phantom_hubp_post_enable = hubp32_phantom_hubp_post_enable,
+	.hubp_update_mall_sel = hubp32_update_mall_sel,
+	.hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering,
+	.hubp_set_flip_int = hubp1_set_flip_int
+};
+
+bool hubp32_construct(
+	struct dcn20_hubp *hubp2,
+	struct dc_context *ctx,
+	uint32_t inst,
+	const struct dcn_hubp2_registers *hubp_regs,
+	const struct dcn_hubp2_shift *hubp_shift,
+	const struct dcn_hubp2_mask *hubp_mask)
+{
+	hubp2->base.funcs = &dcn32_hubp_funcs;
+	hubp2->base.ctx = ctx;
+	hubp2->hubp_regs = hubp_regs;
+	hubp2->hubp_shift = hubp_shift;
+	hubp2->hubp_mask = hubp_mask;
+	hubp2->base.inst = inst;
+	hubp2->base.opp_id = OPP_ID_INVALID;
+	hubp2->base.mpcc_id = 0xf;
+
+	return true;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h
new file mode 100644
index 0000000000000..00b4211389c27
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2012-20 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_HUBP_DCN32_H__
+#define __DC_HUBP_DCN32_H__
+
+#include "dcn20/dcn20_hubp.h"
+#include "dcn21/dcn21_hubp.h"
+#include "dcn30/dcn30_hubp.h"
+#include "dcn31/dcn31_hubp.h"
+
+#define HUBP_REG_LIST_DCN32(id)\
+	HUBP_REG_LIST_DCN30(id),\
+	SRI(DCHUBP_MALL_CONFIG, HUBP, id),\
+	SRI(DCHUBP_VMPG_CONFIG, HUBP, id),\
+	SRI(UCLK_PSTATE_FORCE, HUBPREQ, id)
+
+#define HUBP_MASK_SH_LIST_DCN32(mask_sh)\
+	HUBP_MASK_SH_LIST_DCN31(mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_MALL_CONFIG, USE_MALL_SEL, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, VMPG_SIZE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, PTE_BUFFER_MODE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, BIGK_FRAGMENT_SIZE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, FORCE_ONE_ROW_FOR_FRAME, mask_sh),\
+	HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, DATA_UCLK_PSTATE_FORCE_EN, mask_sh),\
+	HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, DATA_UCLK_PSTATE_FORCE_VALUE, mask_sh),\
+	HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, CURSOR_UCLK_PSTATE_FORCE_EN, mask_sh),\
+	HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, CURSOR_UCLK_PSTATE_FORCE_VALUE, mask_sh)
+
+void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow);
+
+void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel);
+
+void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable);
+
+void hubp32_phantom_hubp_post_enable(struct hubp *hubp);
+
+bool hubp32_construct(
+	struct dcn20_hubp *hubp2,
+	struct dc_context *ctx,
+	uint32_t inst,
+	const struct dcn_hubp2_registers *hubp_regs,
+	const struct dcn_hubp2_shift *hubp_shift,
+	const struct dcn_hubp2_mask *hubp_mask);
+
+#endif /* __DC_HUBP_DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
new file mode 100644
index 0000000000000..d0a222f1a09c0
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -0,0 +1,891 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "dm_services.h"
+#include "dm_helpers.h"
+#include "core_types.h"
+#include "resource.h"
+#include "dccg.h"
+#include "dce/dce_hwseq.h"
+#include "dcn30/dcn30_cm_common.h"
+#include "reg_helper.h"
+#include "abm.h"
+#include "hubp.h"
+#include "dchubbub.h"
+#include "timing_generator.h"
+#include "opp.h"
+#include "ipp.h"
+#include "mpc.h"
+#include "mcif_wb.h"
+#include "dc_dmub_srv.h"
+#include "link_hwss.h"
+#include "dpcd_defs.h"
+#include "dcn32_hwseq.h"
+#include "clk_mgr.h"
+#include "dsc.h"
+#include "dcn20/dcn20_optc.h"
+
+#define DC_LOGGER_INIT(logger)
+
+#define CTX \
+	hws->ctx
+#define REG(reg)\
+	hws->regs->reg
+#define DC_LOGGER \
+		dc->ctx->logger
+
+
+#undef FN
+#define FN(reg_name, field_name) \
+	hws->shifts->field_name, hws->masks->field_name
+
+void dcn32_dsc_pg_control(
+		struct dce_hwseq *hws,
+		unsigned int dsc_inst,
+		bool power_on)
+{
+	uint32_t power_gate = power_on ? 0 : 1;
+	uint32_t pwr_status = power_on ? 0 : 2;
+	uint32_t org_ip_request_cntl = 0;
+
+	if (hws->ctx->dc->debug.disable_dsc_power_gate)
+		return;
+
+	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
+	if (org_ip_request_cntl == 0)
+		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
+
+	switch (dsc_inst) {
+	case 0: /* DSC0 */
+		REG_UPDATE(DOMAIN16_PG_CONFIG,
+				DOMAIN_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN16_PG_STATUS,
+				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 1: /* DSC1 */
+		REG_UPDATE(DOMAIN17_PG_CONFIG,
+				DOMAIN_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN17_PG_STATUS,
+				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 2: /* DSC2 */
+		REG_UPDATE(DOMAIN18_PG_CONFIG,
+				DOMAIN_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN18_PG_STATUS,
+				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 3: /* DSC3 */
+		REG_UPDATE(DOMAIN19_PG_CONFIG,
+				DOMAIN_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN19_PG_STATUS,
+				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		break;
+	}
+
+	if (org_ip_request_cntl == 0)
+		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
+}
+
+
+void dcn32_enable_power_gating_plane(
+	struct dce_hwseq *hws,
+	bool enable)
+{
+	bool force_on = true; /* disable power gating */
+
+	if (enable)
+		force_on = false;
+
+	/* DCHUBP0/1/2/3 */
+	REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+	REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+	REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+	REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+
+	/* DCS0/1/2/3 */
+	REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+	REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+	REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+	REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+}
+
+void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
+{
+	uint32_t power_gate = power_on ? 0 : 1;
+	uint32_t pwr_status = power_on ? 0 : 2;
+
+	if (hws->ctx->dc->debug.disable_hubp_power_gate)
+		return;
+
+	if (REG(DOMAIN0_PG_CONFIG) == 0)
+		return;
+
+	switch (hubp_inst) {
+	case 0:
+		REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
+		REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
+		break;
+	case 1:
+		REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
+		REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
+		break;
+	case 2:
+		REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
+		REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
+		break;
+	case 3:
+		REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
+		REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		break;
+	}
+}
+
+static bool dcn32_check_no_memory_request_for_cab(struct dc *dc)
+{
+	int i;
+
+    /* First, check no-memory-request case */
+	for (i = 0; i < dc->current_state->stream_count; i++) {
+		if (dc->current_state->stream_status[i].plane_count)
+			/* Fail eligibility on a visible stream */
+			break;
+	}
+
+	if (i == dc->current_state->stream_count)
+		return true;
+
+	return false;
+}
+
+/* This function takes in the start address and surface size to be cached in CAB
+ * and calculates the total number of cache lines required to store the surface.
+ * The number of cache lines used for each surface is calculated independently of
+ * one another. For example, if there is a primary surface(1), meta surface(2), and
+ * cursor(3), this function should be called 3 times to calculate the number of cache
+ * lines used for each of those surfaces.
+ */
+static uint32_t dcn32_cache_lines_for_surface(struct dc *dc, uint32_t surface_size, uint64_t start_address)
+{
+	uint32_t lines_used = 1;
+	uint32_t num_cached_bytes = 0;
+	uint32_t remaining_size = 0;
+	uint32_t cache_line_size = dc->caps.cache_line_size;
+
+	/* 1. Calculate surface size minus the number of bytes stored
+	 * in the first cache line (all bytes in first cache line might
+	 * not be fully used).
+	 */
+	num_cached_bytes = cache_line_size - (start_address % cache_line_size);
+	remaining_size = surface_size - num_cached_bytes;
+
+	/* 2. Calculate number of cache lines that will be fully used with
+	 * the remaining number of bytes to be stored.
+	 */
+	lines_used += (remaining_size / cache_line_size);
+
+	/* 3. Check if we need an extra line due to the remaining size not being
+	 * a multiple of CACHE_LINE_SIZE.
+	 */
+	if (remaining_size % cache_line_size > 0)
+		lines_used++;
+
+	return lines_used;
+}
+
+/* This function loops through every surface that needs to be cached in CAB for SS,
+ * and calculates the total number of ways required to store all surfaces (primary,
+ * meta, cursor).
+ */
+static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)
+{
+	uint8_t i, j;
+	struct dc_stream_state *stream = NULL;
+	struct dc_plane_state *plane = NULL;
+	uint32_t surface_size = 0;
+	uint32_t cursor_size = 0;
+	uint32_t cache_lines_used = 0;
+	uint32_t total_lines = 0;
+	uint32_t lines_per_way = 0;
+	uint32_t num_ways = 0;
+
+	for (i = 0; i < ctx->stream_count; i++) {
+		stream = ctx->streams[i];
+
+		// Don't include PSR surface in the total surface size for CAB allocation
+		if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED)
+			continue;
+
+		if (ctx->stream_status[i].plane_count == 0)
+			continue;
+
+		// For each stream, loop through each plane to calculate the number of cache
+		// lines required to store the surface in CAB
+		for (j = 0; j < ctx->stream_status[i].plane_count; j++) {
+			plane = ctx->stream_status[i].plane_states[j];
+
+			// Calculate total surface size
+			surface_size = plane->plane_size.surface_pitch *
+					plane->plane_size.surface_size.height *
+					(plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);
+
+			// Convert surface size + starting address to number of cache lines required
+			// (alignment accounted for)
+			cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size,
+					plane->address.grph.addr.quad_part);
+
+			if (plane->address.grph.meta_addr.quad_part) {
+				// Meta surface
+				cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size,
+						plane->address.grph.meta_addr.quad_part);
+			}
+		}
+
+		// Include cursor size for CAB allocation
+		if (stream->cursor_position.enable && plane->address.grph.cursor_cache_addr.quad_part) {
+			cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size;
+			switch (stream->cursor_attributes.color_format) {
+			case CURSOR_MODE_MONO:
+				cursor_size /= 2;
+				break;
+			case CURSOR_MODE_COLOR_1BIT_AND:
+			case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
+			case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
+				cursor_size *= 4;
+				break;
+
+			case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
+			case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
+				cursor_size *= 8;
+				break;
+			}
+			cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size,
+					plane->address.grph.cursor_cache_addr.quad_part);
+		}
+	}
+
+	// Convert number of cache lines required to number of ways
+	total_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size;
+	lines_per_way = total_lines / dc->caps.cache_num_ways;
+	num_ways = cache_lines_used / lines_per_way;
+
+	if (cache_lines_used % lines_per_way > 0)
+		num_ways++;
+
+	return num_ways;
+}
+
+bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)
+{
+	union dmub_rb_cmd cmd;
+	uint8_t ways;
+
+	if (!dc->ctx->dmub_srv)
+		return false;
+
+	if (enable) {
+		if (dc->current_state) {
+
+			/* 1. Check no memory request case for CAB.
+			 * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message
+			 */
+			if (dcn32_check_no_memory_request_for_cab(dc)) {
+				/* Enable no-memory-requests case */
+				memset(&cmd, 0, sizeof(cmd));
+				cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
+				cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ;
+				cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
+
+				dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
+				dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
+
+				return true;
+			}
+
+			/* 2. Check if all surfaces can fit in CAB.
+			 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message
+			 * and configure HUBP's to fetch from MALL
+			 */
+			ways = dcn32_calculate_cab_allocation(dc, dc->current_state);
+			if (ways <= dc->caps.cache_num_ways) {
+				memset(&cmd, 0, sizeof(cmd));
+				cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
+				cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;
+				cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
+				cmd.cab.cab_alloc_ways = ways;
+
+				dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
+				dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
+
+				return true;
+			}
+
+		}
+		return false;
+	}
+
+	/* Disable CAB */
+	memset(&cmd, 0, sizeof(cmd));
+	cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
+	cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION;
+	cmd.cab.header.payload_bytes =
+			sizeof(cmd.cab) - sizeof(cmd.cab.header);
+
+	dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
+	dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
+	dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
+
+	return false;
+}
+
+/* Send DMCUB message with SubVP pipe info
+ * - For each pipe in context, populate payload with required SubVP information
+ *   if the pipe is using SubVP for MCLK switch
+ * - This function must be called while the DMUB HW lock is acquired by driver
+ */
+void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context)
+{
+/*
+	int i;
+	bool enable_subvp = false;
+
+	if (!dc->ctx || !dc->ctx->dmub_srv)
+		return;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+		if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream &&
+				pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) {
+			// There is at least 1 SubVP pipe, so enable SubVP
+			enable_subvp = true;
+			break;
+		}
+	}
+	dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp);
+*/
+}
+
+static bool dcn32_set_mpc_shaper_3dlut(
+	struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream)
+{
+	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
+	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
+	struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
+	bool result = false;
+
+	const struct pwl_params *shaper_lut = NULL;
+	//get the shaper lut params
+	if (stream->func_shaper) {
+		if (stream->func_shaper->type == TF_TYPE_HWPWL)
+			shaper_lut = &stream->func_shaper->pwl;
+		else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
+			cm_helper_translate_curve_to_hw_format(
+					stream->func_shaper,
+					&dpp_base->shaper_params, true);
+			shaper_lut = &dpp_base->shaper_params;
+		}
+	}
+
+	if (stream->lut3d_func &&
+		stream->lut3d_func->state.bits.initialized == 1) {
+
+		result = mpc->funcs->program_3dlut(mpc,
+								&stream->lut3d_func->lut_3d,
+								mpcc_id);
+
+		result = mpc->funcs->program_shaper(mpc,
+								shaper_lut,
+								mpcc_id);
+	}
+
+	return result;
+}
+bool dcn32_set_output_transfer_func(struct dc *dc,
+				struct pipe_ctx *pipe_ctx,
+				const struct dc_stream_state *stream)
+{
+	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
+	struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
+	struct pwl_params *params = NULL;
+	bool ret = false;
+
+	/* program OGAM or 3DLUT only for the top pipe*/
+	if (pipe_ctx->top_pipe == NULL) {
+		/*program shaper and 3dlut in MPC*/
+		ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);
+		if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
+			if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
+				params = &stream->out_transfer_func->pwl;
+			else if (pipe_ctx->stream->out_transfer_func->type ==
+					TF_TYPE_DISTRIBUTED_POINTS &&
+					cm3_helper_translate_curve_to_hw_format(
+					stream->out_transfer_func,
+					&mpc->blender_params, false))
+				params = &mpc->blender_params;
+		 /* there are no ROM LUTs in OUTGAM */
+		if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
+			BREAK_TO_DEBUGGER();
+		}
+	}
+
+	mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
+	return ret;
+}
+
+/* Program P-State force value according to if pipe is using SubVP or not:
+ * 1. Reset P-State force on all pipes first
+ * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB)
+ */
+void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context)
+{
+	int i;
+	int num_subvp = 0;
+	/* Unforce p-state for each pipe
+	 */
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		struct hubp *hubp = pipe->plane_res.hubp;
+
+		if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
+			hubp->funcs->hubp_update_force_pstate_disallow(hubp, false);
+		if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN)
+			num_subvp++;
+	}
+
+	if (num_subvp == 0)
+		return;
+
+	/* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false.
+	 */
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+		if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
+			struct hubp *hubp = pipe->plane_res.hubp;
+
+			if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
+				hubp->funcs->hubp_update_force_pstate_disallow(hubp, true);
+		}
+	}
+}
+
+/* Update MALL_SEL register based on if pipe / plane
+ * is a phantom pipe, main pipe, and if using MALL
+ * for SS.
+ */
+void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context)
+{
+	int i;
+	unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context);
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		struct hubp *hubp = pipe->plane_res.hubp;
+
+		if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {
+			if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
+					hubp->funcs->hubp_update_mall_sel(hubp, 1);
+			} else {
+				hubp->funcs->hubp_update_mall_sel(hubp,
+					num_ways <= dc->caps.cache_num_ways &&
+					pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED ? 2 : 0);
+			}
+		}
+	}
+}
+
+/* Program the sub-viewport pipe configuration after the main / phantom pipes
+ * have been programmed in hardware.
+ * 1. Update force P-State for all the main pipes (disallow P-state)
+ * 2. Update MALL_SEL register
+ * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes
+ */
+void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context)
+{
+	int i;
+	struct dce_hwseq *hws = dc->hwseq;
+	// Update force P-state for each pipe accordingly
+	if (hws && hws->funcs.subvp_update_force_pstate)
+		hws->funcs.subvp_update_force_pstate(dc, context);
+
+	// Update MALL_SEL register for each pipe
+	if (hws && hws->funcs.update_mall_sel)
+		hws->funcs.update_mall_sel(dc, context);
+
+	// Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		struct hubp *hubp = pipe->plane_res.hubp;
+
+		if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) {
+			if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
+				hubp->funcs->hubp_prepare_subvp_buffering(hubp, true);
+			} else {
+				hubp->funcs->hubp_prepare_subvp_buffering(hubp, false);
+			}
+		}
+	}
+}
+
+void dcn32_init_hw(struct dc *dc)
+{
+	struct abm **abms = dc->res_pool->multiple_abms;
+	struct dce_hwseq *hws = dc->hwseq;
+	struct dc_bios *dcb = dc->ctx->dc_bios;
+	struct resource_pool *res_pool = dc->res_pool;
+	int i;
+	int edp_num;
+	uint32_t backlight = MAX_BACKLIGHT_LEVEL;
+
+	dc->debug.disable_idle_power_optimizations = true;
+	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
+		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
+
+	// Initialize the dccg
+	if (res_pool->dccg->funcs->dccg_init)
+		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
+
+	if (!dcb->funcs->is_accelerated_mode(dcb)) {
+		hws->funcs.bios_golden_init(dc);
+		hws->funcs.disable_vga(dc->hwseq);
+	}
+
+	// Set default OPTC memory power states
+	if (dc->debug.enable_mem_low_power.bits.optc) {
+		// Shutdown when unassigned and light sleep in VBLANK
+		REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
+	}
+
+	if (dc->debug.enable_mem_low_power.bits.vga) {
+		// Power down VGA memory
+		REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
+	}
+
+	if (dc->ctx->dc_bios->fw_info_valid) {
+		res_pool->ref_clocks.xtalin_clock_inKhz =
+				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
+
+		if (res_pool->dccg && res_pool->hubbub) {
+			(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
+					dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
+					&res_pool->ref_clocks.dccg_ref_clock_inKhz);
+
+			(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
+					res_pool->ref_clocks.dccg_ref_clock_inKhz,
+					&res_pool->ref_clocks.dchub_ref_clock_inKhz);
+		} else {
+			// Not all ASICs have DCCG sw component
+			res_pool->ref_clocks.dccg_ref_clock_inKhz =
+					res_pool->ref_clocks.xtalin_clock_inKhz;
+			res_pool->ref_clocks.dchub_ref_clock_inKhz =
+					res_pool->ref_clocks.xtalin_clock_inKhz;
+		}
+	} else
+		ASSERT_CRITICAL(false);
+
+	for (i = 0; i < dc->link_count; i++) {
+		/* Power up AND update implementation according to the
+		 * required signal (which may be different from the
+		 * default signal on connector).
+		 */
+		struct dc_link *link = dc->links[i];
+
+		link->link_enc->funcs->hw_init(link->link_enc);
+
+		/* Check for enabled DIG to identify enabled display */
+		if (link->link_enc->funcs->is_dig_enabled &&
+			link->link_enc->funcs->is_dig_enabled(link->link_enc))
+			link->link_status.link_active = true;
+	}
+
+	/* Power gate DSCs */
+	for (i = 0; i < res_pool->res_cap->num_dsc; i++)
+		if (hws->funcs.dsc_pg_control != NULL)
+			hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
+
+	/* we want to turn off all dp displays before doing detection */
+	dc_link_blank_all_dp_displays(dc);
+
+	/* If taking control over from VBIOS, we may want to optimize our first
+	 * mode set, so we need to skip powering down pipes until we know which
+	 * pipes we want to use.
+	 * Otherwise, if taking control is not possible, we need to power
+	 * everything down.
+	 */
+	if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
+		hws->funcs.init_pipes(dc, dc->current_state);
+		if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
+			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
+					!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
+	}
+
+	/* In headless boot cases, DIG may be turned
+	 * on which causes HW/SW discrepancies.
+	 * To avoid this, power down hardware on boot
+	 * if DIG is turned on and seamless boot not enabled
+	 */
+	if (dc->config.power_down_display_on_boot) {
+		struct dc_link *edp_links[MAX_NUM_EDP];
+		struct dc_link *edp_link;
+
+		get_edp_links(dc, edp_links, &edp_num);
+		if (edp_num) {
+			for (i = 0; i < edp_num; i++) {
+				edp_link = edp_links[i];
+				if (edp_link->link_enc->funcs->is_dig_enabled &&
+						edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
+						dc->hwss.edp_backlight_control &&
+						dc->hwss.power_down &&
+						dc->hwss.edp_power_control) {
+					dc->hwss.edp_backlight_control(edp_link, false);
+					dc->hwss.power_down(dc);
+					dc->hwss.edp_power_control(edp_link, false);
+				}
+			}
+		} else {
+			for (i = 0; i < dc->link_count; i++) {
+				struct dc_link *link = dc->links[i];
+
+				if (link->link_enc->funcs->is_dig_enabled &&
+						link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
+						dc->hwss.power_down) {
+					dc->hwss.power_down(dc);
+					break;
+				}
+
+			}
+		}
+	}
+
+	for (i = 0; i < res_pool->audio_count; i++) {
+		struct audio *audio = res_pool->audios[i];
+
+		audio->funcs->hw_init(audio);
+	}
+
+	for (i = 0; i < dc->link_count; i++) {
+		struct dc_link *link = dc->links[i];
+
+		if (link->panel_cntl)
+			backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
+	}
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		if (abms[i] != NULL && abms[i]->funcs != NULL)
+			abms[i]->funcs->abm_init(abms[i], backlight);
+	}
+
+	/* power AFMT HDMI memory TODO: may move to dis/en output save power*/
+	REG_WRITE(DIO_MEM_PWR_CTRL, 0);
+
+	if (!dc->debug.disable_clock_gate) {
+		/* enable all DCN clock gating */
+		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
+
+		REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
+
+		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
+	}
+	if (hws->funcs.enable_power_gating_plane)
+		hws->funcs.enable_power_gating_plane(dc->hwseq, true);
+
+	if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
+		dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
+
+	if (dc->clk_mgr->funcs->notify_wm_ranges)
+		dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
+
+	if (dc->clk_mgr->funcs->set_hard_max_memclk)
+		dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
+
+	if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
+		dc->res_pool->hubbub->funcs->force_pstate_change_control(
+				dc->res_pool->hubbub, false, false);
+
+	if (dc->res_pool->hubbub->funcs->init_crb)
+		dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
+
+	// Get DMCUB capabilities
+    if (dc->ctx->dmub_srv) {
+	dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);
+	dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
+    }
+}
+
+static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
+		int opp_cnt)
+{
+	bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
+	int flow_ctrl_cnt;
+
+	if (opp_cnt >= 2)
+		hblank_halved = true;
+
+	flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
+			stream->timing.h_border_left -
+			stream->timing.h_border_right;
+
+	if (hblank_halved)
+		flow_ctrl_cnt /= 2;
+
+	/* ODM combine 4:1 case */
+	if (opp_cnt == 4)
+		flow_ctrl_cnt /= 2;
+
+	return flow_ctrl_cnt;
+}
+
+static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+{
+	struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
+	struct dc_stream_state *stream = pipe_ctx->stream;
+	struct pipe_ctx *odm_pipe;
+	int opp_cnt = 1;
+
+	ASSERT(dsc);
+	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
+		opp_cnt++;
+
+	if (enable) {
+		struct dsc_config dsc_cfg;
+		struct dsc_optc_config dsc_optc_cfg;
+		enum optc_dsc_mode optc_dsc_mode;
+
+		/* Enable DSC hw block */
+		dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
+		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
+		dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
+		dsc_cfg.color_depth = stream->timing.display_color_depth;
+		dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
+		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
+		ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
+		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
+
+		dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
+		dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
+		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+			struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
+
+			ASSERT(odm_dsc);
+			odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
+			odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
+		}
+		dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
+		dsc_cfg.pic_width *= opp_cnt;
+
+		optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
+
+		/* Enable DSC in OPTC */
+		DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
+		pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
+							optc_dsc_mode,
+							dsc_optc_cfg.bytes_per_pixel,
+							dsc_optc_cfg.slice_width);
+	} else {
+		/* disable DSC in OPTC */
+		pipe_ctx->stream_res.tg->funcs->set_dsc_config(
+				pipe_ctx->stream_res.tg,
+				OPTC_DSC_DISABLED, 0, 0);
+
+		/* disable DSC block */
+		dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
+		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+			ASSERT(odm_pipe->stream_res.dsc);
+			odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
+		}
+	}
+}
+
+void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
+{
+	struct pipe_ctx *odm_pipe;
+	int opp_cnt = 1;
+	int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
+	bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing));
+	struct mpc_dwb_flow_control flow_control;
+	struct mpc *mpc = dc->res_pool->mpc;
+	int i;
+
+	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+		opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
+		opp_cnt++;
+	}
+
+	if (opp_cnt > 1)
+		pipe_ctx->stream_res.tg->funcs->set_odm_combine(
+				pipe_ctx->stream_res.tg,
+				opp_inst, opp_cnt,
+				&pipe_ctx->stream->timing);
+	else
+		pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
+				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+
+	rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
+	flow_control.flow_ctrl_mode = 0;
+	flow_control.flow_ctrl_cnt0 = 0x80;
+	flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt);
+	if (mpc->funcs->set_out_rate_control) {
+		for (i = 0; i < opp_cnt; ++i) {
+			mpc->funcs->set_out_rate_control(
+					mpc, opp_inst[i],
+					true,
+					rate_control_2x_pclk,
+					&flow_control);
+		}
+	}
+
+	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+		odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
+				odm_pipe->stream_res.opp,
+				true);
+	}
+
+	// Don't program pixel clock after link is already enabled
+/*	if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
+			pipe_ctx->clock_source,
+			&pipe_ctx->stream_res.pix_clk_params,
+			&pipe_ctx->pll_settings)) {
+		BREAK_TO_DEBUGGER();
+	}*/
+
+	if (pipe_ctx->stream_res.dsc)
+		update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
new file mode 100644
index 0000000000000..737a7fac5cf99
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
@@ -0,0 +1,64 @@
+/*
+* Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_HWSS_DCN32_H__
+#define __DC_HWSS_DCN32_H__
+
+#include "hw_sequencer_private.h"
+
+struct dc;
+
+void dcn32_dsc_pg_control(
+		struct dce_hwseq *hws,
+		unsigned int dsc_inst,
+		bool power_on);
+
+void dcn32_enable_power_gating_plane(
+	struct dce_hwseq *hws,
+	bool enable);
+
+void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
+
+bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable);
+
+void dcn32_cab_for_ss_control(struct dc *dc, bool enable);
+
+void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);
+
+bool dcn32_set_output_transfer_func(struct dc *dc,
+				struct pipe_ctx *pipe_ctx,
+				const struct dc_stream_state *stream);
+
+void dcn32_init_hw(struct dc *dc);
+
+void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context);
+
+void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context);
+
+void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context);
+
+void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
+
+#endif /* __DC_HWSS_DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
new file mode 100644
index 0000000000000..d1e3db1bc4882
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
@@ -0,0 +1,155 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dce110/dce110_hw_sequencer.h"
+#include "dcn10/dcn10_hw_sequencer.h"
+#include "dcn20/dcn20_hwseq.h"
+#include "dcn21/dcn21_hwseq.h"
+#include "dcn30/dcn30_hwseq.h"
+#include "dcn31/dcn31_hwseq.h"
+#include "dcn32_hwseq.h"
+
+static const struct hw_sequencer_funcs dcn32_funcs = {
+	.program_gamut_remap = dcn10_program_gamut_remap,
+	.init_hw = dcn32_init_hw,
+	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
+	.apply_ctx_for_surface = NULL,
+	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
+	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
+	.update_plane_addr = dcn20_update_plane_addr,
+	.update_dchub = dcn10_update_dchub,
+	.update_pending_status = dcn10_update_pending_status,
+	.program_output_csc = dcn20_program_output_csc,
+	.enable_accelerated_mode = dce110_enable_accelerated_mode,
+	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
+	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
+	.update_info_frame = dcn31_update_info_frame,
+	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
+	.enable_stream = dcn20_enable_stream,
+	.disable_stream = dce110_disable_stream,
+	.unblank_stream = dcn20_unblank_stream,
+	.blank_stream = dce110_blank_stream,
+	.enable_audio_stream = dce110_enable_audio_stream,
+	.disable_audio_stream = dce110_disable_audio_stream,
+	.disable_plane = dcn20_disable_plane,
+	.pipe_control_lock = dcn20_pipe_control_lock,
+	.interdependent_update_lock = dcn10_lock_all_pipes,
+	.cursor_lock = dcn10_cursor_lock,
+	.prepare_bandwidth = dcn20_prepare_bandwidth,
+	.optimize_bandwidth = dcn20_optimize_bandwidth,
+	.update_bandwidth = dcn20_update_bandwidth,
+	.set_drr = dcn10_set_drr,
+	.get_position = dcn10_get_position,
+	.set_static_screen_control = dcn10_set_static_screen_control,
+	.setup_stereo = dcn10_setup_stereo,
+	.set_avmute = dcn30_set_avmute,
+	.log_hw_state = dcn10_log_hw_state,
+	.get_hw_state = dcn10_get_hw_state,
+	.clear_status_bits = dcn10_clear_status_bits,
+	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+	.edp_backlight_control = dce110_edp_backlight_control,
+	.edp_power_control = dce110_edp_power_control,
+	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+	.edp_wait_for_T12 = dce110_edp_wait_for_T12,
+	.set_cursor_position = dcn10_set_cursor_position,
+	.set_cursor_attribute = dcn10_set_cursor_attribute,
+	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
+	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
+	.set_clock = dcn10_set_clock,
+	.get_clock = dcn10_get_clock,
+	.program_triplebuffer = dcn20_program_triple_buffer,
+	.enable_writeback = dcn30_enable_writeback,
+	.disable_writeback = dcn30_disable_writeback,
+	.update_writeback = dcn30_update_writeback,
+	.mmhubbub_warmup = dcn30_mmhubbub_warmup,
+	.dmdata_status_done = dcn20_dmdata_status_done,
+	.program_dmdata_engine = dcn30_program_dmdata_engine,
+	.set_dmdata_attributes = dcn20_set_dmdata_attributes,
+	.init_sys_ctx = dcn20_init_sys_ctx,
+	.init_vm_ctx = dcn20_init_vm_ctx,
+	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
+	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
+	.calc_vupdate_position = dcn10_calc_vupdate_position,
+	.apply_idle_power_optimizations = dcn32_apply_idle_power_optimizations,
+	.does_plane_fit_in_mall = dcn30_does_plane_fit_in_mall,
+	.set_backlight_level = dcn21_set_backlight_level,
+	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
+	.hardware_release = dcn30_hardware_release,
+	.set_pipe = dcn21_set_pipe,
+	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
+	.get_dcc_en_bits = dcn10_get_dcc_en_bits,
+	.commit_subvp_config = dcn32_commit_subvp_config,
+	.update_visual_confirm_color = dcn20_update_visual_confirm_color,
+};
+
+static const struct hwseq_private_funcs dcn32_private_funcs = {
+	.init_pipes = dcn10_init_pipes,
+	.update_plane_addr = dcn20_update_plane_addr,
+	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
+	.update_mpcc = dcn20_update_mpcc,
+	.set_input_transfer_func = dcn30_set_input_transfer_func,
+	.set_output_transfer_func = dcn32_set_output_transfer_func,
+	.power_down = dce110_power_down,
+	.enable_display_power_gating = dcn10_dummy_display_power_gating,
+	.blank_pixel_data = dcn20_blank_pixel_data,
+	.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
+	.enable_stream_timing = dcn20_enable_stream_timing,
+	.edp_backlight_control = dce110_edp_backlight_control,
+	.disable_stream_gating = dcn20_disable_stream_gating,
+	.enable_stream_gating = dcn20_enable_stream_gating,
+	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
+	.did_underflow_occur = dcn10_did_underflow_occur,
+	.init_blank = dcn20_init_blank,
+	.disable_vga = dcn20_disable_vga,
+	.bios_golden_init = dcn10_bios_golden_init,
+	.plane_atomic_disable = dcn20_plane_atomic_disable,
+	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
+	.enable_power_gating_plane = dcn32_enable_power_gating_plane,
+	.hubp_pg_control = dcn32_hubp_pg_control,
+	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
+	.update_odm = dcn32_update_odm,
+	.dsc_pg_control = dcn32_dsc_pg_control,
+	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
+	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
+	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
+	.dccg_init = dcn20_dccg_init,
+	.set_blend_lut = dcn30_set_blend_lut,
+	.set_shaper_3dlut = dcn20_set_shaper_3dlut,
+	.program_mall_pipe_config = dcn32_program_mall_pipe_config,
+	.subvp_update_force_pstate = dcn32_subvp_update_force_pstate,
+	.update_mall_sel = dcn32_update_mall_sel,
+};
+
+void dcn32_hw_sequencer_init_functions(struct dc *dc)
+{
+	dc->hwss = dcn32_funcs;
+	dc->hwseq->funcs = dcn32_private_funcs;
+
+	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+		dc->hwss.init_hw = dcn20_fpga_init_hw;
+		dc->hwseq->funcs.init_pipes = NULL;
+	}
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.h
new file mode 100644
index 0000000000000..89a591eb2c230
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_DCN32_INIT_H__
+#define __DC_DCN32_INIT_H__
+
+struct dc;
+
+void dcn32_hw_sequencer_init_functions(struct dc *dc);
+
+#endif /* __DC_DCN32_INIT_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c
new file mode 100644
index 0000000000000..adf93cc8359cc
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "reg_helper.h"
+#include "resource.h"
+#include "mcif_wb.h"
+#include "dcn32_mmhubbub.h"
+
+
+#define REG(reg)\
+	mcif_wb30->mcif_wb_regs->reg
+
+#define CTX \
+	mcif_wb30->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+	mcif_wb30->mcif_wb_shift->field_name, mcif_wb30->mcif_wb_mask->field_name
+
+#define MCIF_ADDR(addr) (((unsigned long long)addr & 0xffffffffff) + 0xFE) >> 8
+#define MCIF_ADDR_HIGH(addr) (unsigned long long)addr >> 40
+
+/* wbif programming guide:
+ * 1. set up wbif parameter:
+ *    unsigned long long   luma_address[4];       //4 frame buffer
+ *    unsigned long long   chroma_address[4];
+ *    unsigned int	   luma_pitch;
+ *    unsigned int	   chroma_pitch;
+ *    unsigned int         warmup_pitch=0x10;     //256B align, the page size is 4KB when it is 0x10
+ *    unsigned int	   slice_lines;           //slice size
+ *    unsigned int         time_per_pixel;        // time per pixel, in ns
+ *    unsigned int         arbitration_slice;     // 0: 2048 bytes 1: 4096 bytes 2: 8192 Bytes
+ *    unsigned int         max_scaled_time;       // used for QOS generation
+ *    unsigned int         swlock=0x0;
+ *    unsigned int         cli_watermark[4];      //4 group urgent watermark
+ *    unsigned int         pstate_watermark[4];   //4 group pstate watermark
+ *    unsigned int         sw_int_en;             // Software interrupt enable, frame end and overflow
+ *    unsigned int         sw_slice_int_en;       // slice end interrupt enable
+ *    unsigned int         sw_overrun_int_en;     // overrun error interrupt enable
+ *    unsigned int         vce_int_en;            // VCE interrupt enable, frame end and overflow
+ *    unsigned int         vce_slice_int_en;      // VCE slice end interrupt enable, frame end and overflow
+ *
+ * 2. configure wbif register
+ *    a. call mmhubbub_config_wbif()
+ *
+ * 3. Enable wbif
+ *    call set_wbif_bufmgr_enable();
+ *
+ * 4. wbif_dump_status(), option, for debug purpose
+ *    the bufmgr status can show the progress of write back, can be used for debug purpose
+ */
+
+static void mmhubbub32_warmup_mcif(struct mcif_wb *mcif_wb,
+		struct mcif_warmup_params *params)
+{
+	struct dcn30_mmhubbub *mcif_wb30 = TO_DCN30_MMHUBBUB(mcif_wb);
+	union large_integer start_address_shift = {.quad_part = params->start_address.quad_part >> 5};
+
+	/* Set base address and region size for warmup */
+	REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, 0, MMHUBBUB_WARMUP_BASE_ADDR_HIGH, start_address_shift.high_part);
+	REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_LOW, 0, MMHUBBUB_WARMUP_BASE_ADDR_LOW, start_address_shift.low_part);
+	REG_SET(MMHUBBUB_WARMUP_ADDR_REGION, 0, MMHUBBUB_WARMUP_ADDR_REGION, params->region_size >> 5);
+//	REG_SET(MMHUBBUB_WARMUP_P_VMID, 0, MMHUBBUB_WARMUP_P_VMID, params->p_vmid);
+
+	/* Set address increment and enable warmup */
+	REG_SET_3(MMHUBBUB_WARMUP_CONTROL_STATUS, 0, MMHUBBUB_WARMUP_EN, true,
+			MMHUBBUB_WARMUP_SW_INT_EN, true,
+			MMHUBBUB_WARMUP_INC_ADDR, params->address_increment >> 5);
+
+	/* Wait for an interrupt to signal warmup is completed */
+	REG_WAIT(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_STATUS, 1, 20, 100);
+
+	/* Acknowledge interrupt */
+	REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, 1);
+
+	/* Disable warmup */
+	REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, false);
+}
+
+void mmhubbub32_config_mcif_buf(struct mcif_wb *mcif_wb,
+		struct mcif_buf_params *params,
+		unsigned int dest_height)
+{
+	struct dcn30_mmhubbub *mcif_wb30 = TO_DCN30_MMHUBBUB(mcif_wb);
+
+	/* buffer address for packing mode or Luma in planar mode */
+	REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0]));
+	REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[0]));
+
+	/* buffer address for Chroma in planar mode (unused in packing mode) */
+	REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0]));
+	REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[0]));
+
+	/* buffer address for packing mode or Luma in planar mode */
+	REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1]));
+	REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[1]));
+
+	/* buffer address for Chroma in planar mode (unused in packing mode) */
+	REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1]));
+	REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[1]));
+
+	/* buffer address for packing mode or Luma in planar mode */
+	REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, MCIF_ADDR(params->luma_address[2]));
+	REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[2]));
+
+	/* buffer address for Chroma in planar mode (unused in packing mode) */
+	REG_UPDATE(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, MCIF_ADDR(params->chroma_address[2]));
+	REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[2]));
+
+	/* buffer address for packing mode or Luma in planar mode */
+	REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, MCIF_ADDR(params->luma_address[3]));
+	REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[3]));
+
+	/* buffer address for Chroma in planar mode (unused in packing mode) */
+	REG_UPDATE(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, MCIF_ADDR(params->chroma_address[3]));
+	REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[3]));
+
+	/* setup luma & chroma size
+	 * should be enough to contain a whole frame Luma data,
+	 * the programmed value is frame buffer size [27:8], 256-byte aligned
+	 */
+	REG_UPDATE(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, (params->luma_pitch>>8) * dest_height);
+	REG_UPDATE(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, (params->chroma_pitch>>8) * dest_height);
+
+	/* enable address fence */
+	REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, 1);
+
+	/* setup pitch, the programmed value is [15:8], 256B align */
+	REG_UPDATE_2(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, params->luma_pitch >> 8,
+			MCIF_WB_BUF_CHROMA_PITCH, params->chroma_pitch >> 8);
+}
+
+static void mmhubbub32_config_mcif_arb(struct mcif_wb *mcif_wb,
+		struct mcif_arb_params *params)
+{
+	struct dcn30_mmhubbub *mcif_wb30 = TO_DCN30_MMHUBBUB(mcif_wb);
+
+	/* Programmed by the video driver based on the CRTC timing (for DWB) */
+	REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, params->time_per_pixel);
+
+	/* Programming dwb watermark */
+	/* Watermark to generate urgent in MCIF_WB_CLI, value is determined by MCIF_WB_CLI_WATERMARK_MASK. */
+	/* Program in ns. A formula will be provided in the pseudo code to calculate the value. */
+	REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x0);
+	/* urgent_watermarkA */
+	REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK,  params->cli_watermark[0]);
+	REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x1);
+	/* urgent_watermarkB */
+	REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK,  params->cli_watermark[1]);
+	REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x2);
+	/* urgent_watermarkC */
+	REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK,  params->cli_watermark[2]);
+	REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x3);
+	/* urgent_watermarkD */
+	REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK,  params->cli_watermark[3]);
+
+	/* Programming nb pstate watermark */
+	/* nbp_state_change_watermarkA */
+	REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x0);
+	REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
+			NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[0]);
+	/* nbp_state_change_watermarkB */
+	REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x1);
+	REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
+			NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[1]);
+	/* nbp_state_change_watermarkC */
+	REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x2);
+	REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
+			NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[2]);
+	/* nbp_state_change_watermarkD */
+	REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x3);
+	REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
+			NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[3]);
+
+	/* dram_speed_change_duration - register removed */
+	//REG_UPDATE(MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI,
+	//		MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI, params->dram_speed_change_duration);
+
+	/* max_scaled_time */
+	REG_UPDATE(MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, params->max_scaled_time);
+
+	/* slice_lines */
+	REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, params->slice_lines-1);
+
+	/* Set arbitration unit for Luma/Chroma */
+	/* arb_unit=2 should be chosen for more efficiency */
+	/* Arbitration size, 0: 2048 bytes 1: 4096 bytes 2: 8192 Bytes */
+	REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE,  params->arbitration_slice);
+}
+
+const struct mcif_wb_funcs dcn32_mmhubbub_funcs = {
+	.warmup_mcif		= mmhubbub32_warmup_mcif,
+	.enable_mcif		= mmhubbub2_enable_mcif,
+	.disable_mcif		= mmhubbub2_disable_mcif,
+	.config_mcif_buf	= mmhubbub32_config_mcif_buf,
+	.config_mcif_arb	= mmhubbub32_config_mcif_arb,
+	.config_mcif_irq	= mmhubbub2_config_mcif_irq,
+	.dump_frame			= mcifwb2_dump_frame,
+};
+
+void dcn32_mmhubbub_construct(struct dcn30_mmhubbub *mcif_wb30,
+		struct dc_context *ctx,
+		const struct dcn30_mmhubbub_registers *mcif_wb_regs,
+		const struct dcn30_mmhubbub_shift *mcif_wb_shift,
+		const struct dcn30_mmhubbub_mask *mcif_wb_mask,
+		int inst)
+{
+	mcif_wb30->base.ctx = ctx;
+
+	mcif_wb30->base.inst = inst;
+	mcif_wb30->base.funcs = &dcn32_mmhubbub_funcs;
+
+	mcif_wb30->mcif_wb_regs = mcif_wb_regs;
+	mcif_wb30->mcif_wb_shift = mcif_wb_shift;
+	mcif_wb30->mcif_wb_mask = mcif_wb_mask;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h
new file mode 100644
index 0000000000000..22355051f5f73
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_MCIF_WB_DCN32_H__
+#define __DC_MCIF_WB_DCN32_H__
+
+#include "dcn20/dcn20_mmhubbub.h"
+#include "dcn30/dcn30_mmhubbub.h"
+
+#define MCIF_WB_COMMON_REG_LIST_DCN32(inst) \
+	SRI2(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\
+	SRI2(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
+	SRI2(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
+	SRI2(MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB, inst),\
+	SRI2(MCIF_WB_TEST_DEBUG_DATA, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
+	SRI2(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MMHUBBUB, inst),\
+	SRI2(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
+	SRI2(MCIF_WB_WATERMARK, MMHUBBUB, inst),\
+	SRI2(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),\
+	SRI2(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),\
+	SRI2(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),\
+	SRI2(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),\
+	SRI2(MMHUBBUB_MEM_PWR_CNTL, MMHUBBUB, inst),\
+	SRI2(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB, inst),\
+	SRI2(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB, inst),\
+	SRI2(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB, inst),\
+	SRI2(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB, inst)
+
+
+#define MCIF_WB_COMMON_MASK_SH_LIST_DCN32(mask_sh) \
+	SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
+	SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
+	SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
+	SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
+	SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
+	SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
+	SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
+	SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_VCE_INT_STATUS, mask_sh),\
+	SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\
+	SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\
+	SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_BUF, mask_sh),\
+	SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_BUFTAG, mask_sh),\
+	SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_LINE_L, mask_sh),\
+	SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_NEXT_BUF, mask_sh),\
+	SF(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
+	SF(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_ACTIVE, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_SW_LOCKED, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_VCE_LOCKED, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_OVERFLOW, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_DISABLE, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_BUFTAG, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_NXT_BUF, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_CUR_LINE_L, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_NEW_CONTENT, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_COLOR_DEPTH, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ_BLACK_PIXEL, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_Y_OVERRUN, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_C_OVERRUN, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_ACTIVE, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_SW_LOCKED, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_VCE_LOCKED, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_OVERFLOW, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_DISABLE, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_BUFTAG, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_NXT_BUF, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_CUR_LINE_L, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_NEW_CONTENT, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_COLOR_DEPTH, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ_BLACK_PIXEL, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_Y_OVERRUN, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_C_OVERRUN, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_ACTIVE, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_SW_LOCKED, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_VCE_LOCKED, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_OVERFLOW, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_DISABLE, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_BUFTAG, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_NXT_BUF, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_CUR_LINE_L, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_NEW_CONTENT, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_COLOR_DEPTH, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ_BLACK_PIXEL, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_Y_OVERRUN, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_C_OVERRUN, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_ACTIVE, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_SW_LOCKED, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_VCE_LOCKED, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_OVERFLOW, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_DISABLE, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_BUFTAG, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_NXT_BUF, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_CUR_LINE_L, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_NEW_CONTENT, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_COLOR_DEPTH, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ_BLACK_PIXEL, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_Y_OVERRUN, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_C_OVERRUN, mask_sh),\
+	SF(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\
+	SF(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\
+	SF(MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\
+	SF(MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB_TEST_DEBUG_INDEX, mask_sh),\
+	SF(MCIF_WB_TEST_DEBUG_DATA, MCIF_WB_TEST_DEBUG_DATA, mask_sh),\
+	SF(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\
+	SF(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\
+	SF(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\
+	SF(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\
+	SF(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\
+	SF(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\
+	SF(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\
+	SF(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\
+	SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\
+	SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\
+	SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\
+	SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\
+	SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\
+	SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\
+	SF(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\
+	SF(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
+	SF(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\
+	SF(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
+	SF(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\
+	SF(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB_CLI_CLOCK_GATER_OVERRIDE, mask_sh),\
+	SF(MCIF_WB_SELF_REFRESH_CONTROL, PERFRAME_SELF_REFRESH, mask_sh),\
+	SF(MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, mask_sh),\
+	SF(MCIF_WB_SECURITY_LEVEL, MCIF_WB_SECURITY_LEVEL, mask_sh),\
+	SF(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\
+	SF(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh),\
+	SF(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, mask_sh),\
+	SF(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, mask_sh),\
+	SF(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, mask_sh),\
+	SF(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, mask_sh),\
+	SF(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, mask_sh),\
+	SF(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, mask_sh),\
+	SF(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, mask_sh),\
+	SF(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, mask_sh),\
+	SF(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_WIDTH, mask_sh),\
+	SF(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_HEIGHT, mask_sh),\
+	SF(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_WIDTH, mask_sh),\
+	SF(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_HEIGHT, mask_sh),\
+	SF(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_WIDTH, mask_sh),\
+	SF(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_HEIGHT, mask_sh),\
+	SF(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_WIDTH, mask_sh),\
+	SF(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_HEIGHT, mask_sh),\
+	SF(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB_WARMUP_ADDR_REGION, mask_sh),\
+	SF(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB_WARMUP_BASE_ADDR_HIGH, mask_sh),\
+	SF(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB_WARMUP_BASE_ADDR_LOW, mask_sh),\
+	SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, mask_sh),\
+	SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_EN, mask_sh),\
+	SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_STATUS, mask_sh),\
+	SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, mask_sh),\
+	SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_INC_ADDR, mask_sh)
+
+
+void dcn32_mmhubbub_construct(struct dcn30_mmhubbub *mcif_wb30,
+	struct dc_context *ctx,
+	const struct dcn30_mmhubbub_registers *mcif_wb_regs,
+	const struct dcn30_mmhubbub_shift *mcif_wb_shift,
+	const struct dcn30_mmhubbub_mask *mcif_wb_mask,
+	int inst);
+
+#endif //__DC_MCIF_WB_DCN32_H__
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
new file mode 100644
index 0000000000000..a308f33d3d0d2
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
@@ -0,0 +1,810 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+#include "dcn30/dcn30_mpc.h"
+#include "dcn30/dcn30_cm_common.h"
+#include "dcn30/dcn30_mpc.h"
+#include "basics/conversion.h"
+#include "dcn10/dcn10_cm_common.h"
+#include "dc.h"
+
+#define REG(reg)\
+	mpc30->mpc_regs->reg
+
+#define CTX \
+	mpc30->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+	mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
+
+
+static void mpc32_mpc_init(struct mpc *mpc)
+{
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+	int mpcc_id;
+
+	mpc1_mpc_init(mpc);
+
+	if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
+		if (mpc30->mpc_mask->MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE) {
+			for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) {
+				REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, 3);
+				REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, 3);
+				REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, 3);
+			}
+		}
+		if (mpc30->mpc_mask->MPCC_OGAM_MEM_LOW_PWR_MODE) {
+			for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++)
+				REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_LOW_PWR_MODE, 3);
+		}
+	}
+}
+
+
+static enum dc_lut_mode mpc32_get_shaper_current(struct mpc *mpc, uint32_t mpcc_id)
+{
+	enum dc_lut_mode mode;
+	uint32_t state_mode;
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	REG_GET(MPCC_MCM_SHAPER_CONTROL[mpcc_id],
+			MPCC_MCM_SHAPER_MODE_CURRENT, &state_mode);
+
+		switch (state_mode) {
+		case 0:
+			mode = LUT_BYPASS;
+			break;
+		case 1:
+			mode = LUT_RAM_A;
+			break;
+		case 2:
+			mode = LUT_RAM_B;
+			break;
+		default:
+			mode = LUT_BYPASS;
+			break;
+		}
+		return mode;
+}
+
+
+static void mpc32_configure_shaper_lut(
+		struct mpc *mpc,
+		bool is_ram_a,
+		uint32_t mpcc_id)
+{
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id],
+			MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, 7);
+	REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id],
+			MPCC_MCM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
+	REG_SET(MPCC_MCM_SHAPER_LUT_INDEX[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_INDEX, 0);
+}
+
+
+static void mpc32_program_shaper_luta_settings(
+		struct mpc *mpc,
+		const struct pwl_params *params,
+		uint32_t mpcc_id)
+{
+	const struct gamma_curve *curve;
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_B[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
+	REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_G[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
+	REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_R[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
+
+	REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_B[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
+	REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_G[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y);
+	REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_R[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y);
+
+	curve = params->arr_curve_points;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_0_1[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_2_3[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_4_5[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_6_7[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_8_9[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_10_11[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_12_13[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_14_15[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_16_17[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_18_19[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_20_21[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_22_23[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_24_25[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_26_27[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_28_29[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_30_31[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_32_33[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+}
+
+
+static void mpc32_program_shaper_lutb_settings(
+		struct mpc *mpc,
+		const struct pwl_params *params,
+		uint32_t mpcc_id)
+{
+	const struct gamma_curve *curve;
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_B[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
+	REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_G[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
+	REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_R[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
+
+	REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_B[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
+	REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_G[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y);
+	REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_R[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y);
+
+	curve = params->arr_curve_points;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_0_1[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_2_3[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_4_5[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_6_7[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_8_9[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_10_11[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_12_13[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_14_15[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_16_17[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_18_19[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_20_21[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_22_23[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_24_25[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_26_27[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_28_29[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_30_31[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_32_33[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+}
+
+
+static void mpc32_program_shaper_lut(
+		struct mpc *mpc,
+		const struct pwl_result_data *rgb,
+		uint32_t num,
+		uint32_t mpcc_id)
+{
+	uint32_t i, red, green, blue;
+	uint32_t  red_delta, green_delta, blue_delta;
+	uint32_t  red_value, green_value, blue_value;
+
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	for (i = 0 ; i < num; i++) {
+
+		red   = rgb[i].red_reg;
+		green = rgb[i].green_reg;
+		blue  = rgb[i].blue_reg;
+
+		red_delta   = rgb[i].delta_red_reg;
+		green_delta = rgb[i].delta_green_reg;
+		blue_delta  = rgb[i].delta_blue_reg;
+
+		red_value   = ((red_delta   & 0x3ff) << 14) | (red   & 0x3fff);
+		green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff);
+		blue_value  = ((blue_delta  & 0x3ff) << 14) | (blue  & 0x3fff);
+
+		REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, red_value);
+		REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, green_value);
+		REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, blue_value);
+	}
+
+}
+
+
+static void mpc32_power_on_shaper_3dlut(
+		struct mpc *mpc,
+		uint32_t mpcc_id,
+		bool power_on)
+{
+	uint32_t power_status_shaper = 2;
+	uint32_t power_status_3dlut  = 2;
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+	int max_retries = 10;
+
+	REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
+	MPCC_MCM_3DLUT_MEM_PWR_DIS, power_on == true ? 1:0);
+	/* wait for memory to fully power up */
+	if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
+		REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, 0, 1, max_retries);
+		REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, 0, 1, max_retries);
+	}
+
+	/*read status is not mandatory, it is just for debugging*/
+	REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, &power_status_shaper);
+	REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, &power_status_3dlut);
+
+	if (power_status_shaper != 0 && power_on == true)
+		BREAK_TO_DEBUGGER();
+
+	if (power_status_3dlut != 0 && power_on == true)
+		BREAK_TO_DEBUGGER();
+}
+
+
+bool mpc32_program_shaper(
+		struct mpc *mpc,
+		const struct pwl_params *params,
+		uint32_t mpcc_id)
+{
+	enum dc_lut_mode current_mode;
+	enum dc_lut_mode next_mode;
+
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	if (params == NULL) {
+		REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, 0);
+		return false;
+	}
+
+	if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)
+		mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);
+
+	current_mode = mpc32_get_shaper_current(mpc, mpcc_id);
+
+	if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
+		next_mode = LUT_RAM_B;
+	else
+		next_mode = LUT_RAM_A;
+
+	mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A ? true:false, mpcc_id);
+
+	if (next_mode == LUT_RAM_A)
+		mpc32_program_shaper_luta_settings(mpc, params, mpcc_id);
+	else
+		mpc32_program_shaper_lutb_settings(mpc, params, mpcc_id);
+
+	mpc32_program_shaper_lut(
+			mpc, params->rgb_resulted, params->hw_points_num, mpcc_id);
+
+	REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);
+	mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);
+
+	return true;
+}
+
+
+static enum dc_lut_mode get3dlut_config(
+			struct mpc *mpc,
+			bool *is_17x17x17,
+			bool *is_12bits_color_channel,
+			int mpcc_id)
+{
+	uint32_t i_mode, i_enable_10bits, lut_size;
+	enum dc_lut_mode mode;
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id],
+			MPCC_MCM_3DLUT_MODE_CURRENT,  &i_mode);
+
+	REG_GET(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id],
+			MPCC_MCM_3DLUT_30BIT_EN, &i_enable_10bits);
+
+	switch (i_mode) {
+	case 0:
+		mode = LUT_BYPASS;
+		break;
+	case 1:
+		mode = LUT_RAM_A;
+		break;
+	case 2:
+		mode = LUT_RAM_B;
+		break;
+	default:
+		mode = LUT_BYPASS;
+		break;
+	}
+	if (i_enable_10bits > 0)
+		*is_12bits_color_channel = false;
+	else
+		*is_12bits_color_channel = true;
+
+	REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &lut_size);
+
+	if (lut_size == 0)
+		*is_17x17x17 = true;
+	else
+		*is_17x17x17 = false;
+
+	return mode;
+}
+
+
+static void mpc32_select_3dlut_ram(
+		struct mpc *mpc,
+		enum dc_lut_mode mode,
+		bool is_color_channel_12bits,
+		uint32_t mpcc_id)
+{
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	REG_UPDATE_2(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id],
+		MPCC_MCM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,
+		MPCC_MCM_3DLUT_30BIT_EN, is_color_channel_12bits == true ? 0:1);
+}
+
+
+static void mpc32_select_3dlut_ram_mask(
+		struct mpc *mpc,
+		uint32_t ram_selection_mask,
+		uint32_t mpcc_id)
+{
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_WRITE_EN_MASK,
+			ram_selection_mask);
+	REG_SET(MPCC_MCM_3DLUT_INDEX[mpcc_id], 0, MPCC_MCM_3DLUT_INDEX, 0);
+}
+
+
+static void mpc32_set3dlut_ram12(
+		struct mpc *mpc,
+		const struct dc_rgb *lut,
+		uint32_t entries,
+		uint32_t mpcc_id)
+{
+	uint32_t i, red, green, blue, red1, green1, blue1;
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	for (i = 0 ; i < entries; i += 2) {
+		red   = lut[i].red<<4;
+		green = lut[i].green<<4;
+		blue  = lut[i].blue<<4;
+		red1   = lut[i+1].red<<4;
+		green1 = lut[i+1].green<<4;
+		blue1  = lut[i+1].blue<<4;
+
+		REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
+				MPCC_MCM_3DLUT_DATA0, red,
+				MPCC_MCM_3DLUT_DATA1, red1);
+
+		REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
+				MPCC_MCM_3DLUT_DATA0, green,
+				MPCC_MCM_3DLUT_DATA1, green1);
+
+		REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
+				MPCC_MCM_3DLUT_DATA0, blue,
+				MPCC_MCM_3DLUT_DATA1, blue1);
+	}
+}
+
+
+static void mpc32_set3dlut_ram10(
+		struct mpc *mpc,
+		const struct dc_rgb *lut,
+		uint32_t entries,
+		uint32_t mpcc_id)
+{
+	uint32_t i, red, green, blue, value;
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	for (i = 0; i < entries; i++) {
+		red   = lut[i].red;
+		green = lut[i].green;
+		blue  = lut[i].blue;
+		//should we shift red 22bit and green 12?
+		value = (red<<20) | (green<<10) | blue;
+
+		REG_SET(MPCC_MCM_3DLUT_DATA_30BIT[mpcc_id], 0, MPCC_MCM_3DLUT_DATA_30BIT, value);
+	}
+
+}
+
+
+static void mpc32_set_3dlut_mode(
+		struct mpc *mpc,
+		enum dc_lut_mode mode,
+		bool is_color_channel_12bits,
+		bool is_lut_size17x17x17,
+		uint32_t mpcc_id)
+{
+	uint32_t lut_mode;
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	if (mode == LUT_BYPASS)
+		lut_mode = 0;
+	else if (mode == LUT_RAM_A)
+		lut_mode = 1;
+	else
+		lut_mode = 2;
+
+	REG_UPDATE_2(MPCC_MCM_3DLUT_MODE[mpcc_id],
+			MPCC_MCM_3DLUT_MODE, lut_mode,
+			MPCC_MCM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);
+}
+
+
+bool mpc32_program_3dlut(
+		struct mpc *mpc,
+		const struct tetrahedral_params *params,
+		int mpcc_id)
+{
+	enum dc_lut_mode mode;
+	bool is_17x17x17;
+	bool is_12bits_color_channel;
+	const struct dc_rgb *lut0;
+	const struct dc_rgb *lut1;
+	const struct dc_rgb *lut2;
+	const struct dc_rgb *lut3;
+	int lut_size0;
+	int lut_size;
+
+	if (params == NULL) {
+		mpc32_set_3dlut_mode(mpc, LUT_BYPASS, false, false, mpcc_id);
+		return false;
+	}
+	mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);
+
+	mode = get3dlut_config(mpc, &is_17x17x17, &is_12bits_color_channel, mpcc_id);
+
+	if (mode == LUT_BYPASS || mode == LUT_RAM_B)
+		mode = LUT_RAM_A;
+	else
+		mode = LUT_RAM_B;
+
+	is_17x17x17 = !params->use_tetrahedral_9;
+	is_12bits_color_channel = params->use_12bits;
+	if (is_17x17x17) {
+		lut0 = params->tetrahedral_17.lut0;
+		lut1 = params->tetrahedral_17.lut1;
+		lut2 = params->tetrahedral_17.lut2;
+		lut3 = params->tetrahedral_17.lut3;
+		lut_size0 = sizeof(params->tetrahedral_17.lut0)/
+					sizeof(params->tetrahedral_17.lut0[0]);
+		lut_size  = sizeof(params->tetrahedral_17.lut1)/
+					sizeof(params->tetrahedral_17.lut1[0]);
+	} else {
+		lut0 = params->tetrahedral_9.lut0;
+		lut1 = params->tetrahedral_9.lut1;
+		lut2 = params->tetrahedral_9.lut2;
+		lut3 = params->tetrahedral_9.lut3;
+		lut_size0 = sizeof(params->tetrahedral_9.lut0)/
+				sizeof(params->tetrahedral_9.lut0[0]);
+		lut_size  = sizeof(params->tetrahedral_9.lut1)/
+				sizeof(params->tetrahedral_9.lut1[0]);
+		}
+
+	mpc32_select_3dlut_ram(mpc, mode,
+				is_12bits_color_channel, mpcc_id);
+	mpc32_select_3dlut_ram_mask(mpc, 0x1, mpcc_id);
+	if (is_12bits_color_channel)
+		mpc32_set3dlut_ram12(mpc, lut0, lut_size0, mpcc_id);
+	else
+		mpc32_set3dlut_ram10(mpc, lut0, lut_size0, mpcc_id);
+
+	mpc32_select_3dlut_ram_mask(mpc, 0x2, mpcc_id);
+	if (is_12bits_color_channel)
+		mpc32_set3dlut_ram12(mpc, lut1, lut_size, mpcc_id);
+	else
+		mpc32_set3dlut_ram10(mpc, lut1, lut_size, mpcc_id);
+
+	mpc32_select_3dlut_ram_mask(mpc, 0x4, mpcc_id);
+	if (is_12bits_color_channel)
+		mpc32_set3dlut_ram12(mpc, lut2, lut_size, mpcc_id);
+	else
+		mpc32_set3dlut_ram10(mpc, lut2, lut_size, mpcc_id);
+
+	mpc32_select_3dlut_ram_mask(mpc, 0x8, mpcc_id);
+	if (is_12bits_color_channel)
+		mpc32_set3dlut_ram12(mpc, lut3, lut_size, mpcc_id);
+	else
+		mpc32_set3dlut_ram10(mpc, lut3, lut_size, mpcc_id);
+
+	mpc32_set_3dlut_mode(mpc, mode, is_12bits_color_channel,
+					is_17x17x17, mpcc_id);
+
+	if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)
+		mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);
+
+	return true;
+}
+
+const struct mpc_funcs dcn32_mpc_funcs = {
+	.read_mpcc_state = mpc1_read_mpcc_state,
+	.insert_plane = mpc1_insert_plane,
+	.remove_mpcc = mpc1_remove_mpcc,
+	.mpc_init = mpc32_mpc_init,
+	.mpc_init_single_inst = mpc1_mpc_init_single_inst,
+	.update_blending = mpc2_update_blending,
+	.cursor_lock = mpc1_cursor_lock,
+	.get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
+	.wait_for_idle = mpc2_assert_idle_mpcc,
+	.assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect,
+	.init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
+	.set_denorm =  mpc3_set_denorm,
+	.set_denorm_clamp = mpc3_set_denorm_clamp,
+	.set_output_csc = mpc3_set_output_csc,
+	.set_ocsc_default = mpc3_set_ocsc_default,
+	.set_output_gamma = mpc3_set_output_gamma,
+	.insert_plane_to_secondary = NULL,
+	.remove_mpcc_from_secondary =  NULL,
+	.set_dwb_mux = mpc3_set_dwb_mux,
+	.disable_dwb_mux = mpc3_disable_dwb_mux,
+	.is_dwb_idle = mpc3_is_dwb_idle,
+	.set_out_rate_control = mpc3_set_out_rate_control,
+	.set_gamut_remap = mpc3_set_gamut_remap,
+	.program_shaper = mpc32_program_shaper,
+	.program_3dlut = mpc32_program_3dlut,
+	.acquire_rmu = NULL,
+	.release_rmu = NULL,
+	.power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut,
+	.get_mpc_out_mux = mpc1_get_mpc_out_mux,
+	.set_bg_color = mpc1_set_bg_color,
+};
+
+
+void dcn32_mpc_construct(struct dcn30_mpc *mpc30,
+	struct dc_context *ctx,
+	const struct dcn30_mpc_registers *mpc_regs,
+	const struct dcn30_mpc_shift *mpc_shift,
+	const struct dcn30_mpc_mask *mpc_mask,
+	int num_mpcc,
+	int num_rmu)
+{
+	int i;
+
+	mpc30->base.ctx = ctx;
+
+	mpc30->base.funcs = &dcn32_mpc_funcs;
+
+	mpc30->mpc_regs = mpc_regs;
+	mpc30->mpc_shift = mpc_shift;
+	mpc30->mpc_mask = mpc_mask;
+
+	mpc30->mpcc_in_use_mask = 0;
+	mpc30->num_mpcc = num_mpcc;
+	mpc30->num_rmu = num_rmu;
+
+	for (i = 0; i < MAX_MPCC; i++)
+		mpc3_init_mpcc(&mpc30->base.mpcc_array[i], i);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h
new file mode 100644
index 0000000000000..d4be3c89ec7b0
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h
@@ -0,0 +1,213 @@
+/* Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_MPCC_DCN32_H__
+#define __DC_MPCC_DCN32_H__
+
+#include "dcn20/dcn20_mpc.h"
+#include "dcn30/dcn30_mpc.h"
+
+#define MPC_MCM_REG_LIST_DCN32(inst) \
+	SRII(MPCC_MCM_SHAPER_CONTROL, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_LUT_INDEX, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_LUT_DATA, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_G, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_R, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_G, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_R, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_2_3, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_4_5, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_6_7, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_8_9, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_10_11, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_12_13, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_14_15, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_16_17, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_18_19, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_20_21, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_22_23, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_24_25, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_26_27, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_28_29, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_30_31, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_32_33, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_B, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_G, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_R, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_B, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_G, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_R, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_0_1, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_2_3, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_4_5, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_6_7, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_8_9, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_10_11, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_12_13, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_14_15, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_16_17, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_18_19, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_20_21, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_22_23, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_24_25, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_26_27, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_28_29, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_30_31, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_32_33, MPCC_MCM, inst), \
+	SRII(MPCC_MCM_3DLUT_MODE, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_3DLUT_INDEX, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_3DLUT_DATA, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_3DLUT_DATA_30BIT, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_3DLUT_OUT_NORM_FACTOR, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_3DLUT_OUT_OFFSET_R, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_3DLUT_OUT_OFFSET_G, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_3DLUT_OUT_OFFSET_B, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM, inst)
+
+
+#define MPC_COMMON_MASK_SH_LIST_DCN32(mask_sh) \
+	MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\
+	SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
+	SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
+	SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
+	SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
+	SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
+	SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
+	SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
+	SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
+	SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
+	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
+	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
+	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_LOW_PWR_MODE, mask_sh),\
+	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\
+	SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\
+	SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\
+	SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\
+	SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\
+	SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\
+	SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
+	SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\
+	SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\
+	SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\
+	SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
+	SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\
+	SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\
+	SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\
+	SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\
+	SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_DBG, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_MODE, MPCC_MCM_3DLUT_MODE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_MODE, MPCC_MCM_3DLUT_SIZE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_MODE, MPCC_MCM_3DLUT_MODE_CURRENT, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_WRITE_EN_MASK, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_RAM_SEL, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_30BIT_EN, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_READ_SEL, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_INDEX, MPCC_MCM_3DLUT_INDEX, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_DATA, MPCC_MCM_3DLUT_DATA0, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_DATA, MPCC_MCM_3DLUT_DATA1, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT, MPCC_MCM_3DLUT_DATA_30BIT, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL, MPCC_MCM_SHAPER_LUT_MODE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL, MPCC_MCM_SHAPER_MODE_CURRENT, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM_SHAPER_OFFSET_R, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM_SHAPER_OFFSET_G, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM_SHAPER_OFFSET_B, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM_SHAPER_SCALE_R, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM_SHAPER_SCALE_G, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM_SHAPER_SCALE_B, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX, MPCC_MCM_SHAPER_LUT_INDEX, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA, MPCC_MCM_SHAPER_LUT_DATA, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM_SHAPER_LUT_WRITE_SEL, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_PWR_FORCE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_PWR_DIS, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_PWR_FORCE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_PWR_DIS, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_PWR_FORCE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_PWR_DIS, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_PWR_STATE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_PWR_STATE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_PWR_STATE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL, MPCC_MCM_SHAPER_MODE_CURRENT, mask_sh),\
+	SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh)
+
+
+void dcn32_mpc_construct(struct dcn30_mpc *mpc30,
+	struct dc_context *ctx,
+	const struct dcn30_mpc_registers *mpc_regs,
+	const struct dcn30_mpc_shift *mpc_shift,
+	const struct dcn30_mpc_mask *mpc_mask,
+	int num_mpcc,
+	int num_rmu);
+
+#endif		//__DC_MPCC_DCN32_H__
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
new file mode 100644
index 0000000000000..f1ed25e972f29
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
@@ -0,0 +1,236 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dcn32_optc.h"
+
+#include "dcn30/dcn30_optc.h"
+#include "reg_helper.h"
+#include "dc.h"
+#include "dcn_calc_math.h"
+
+#define REG(reg)\
+	optc1->tg_regs->reg
+
+#define CTX \
+	optc1->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+	optc1->tg_shift->field_name, optc1->tg_mask->field_name
+
+static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
+		struct dc_crtc_timing *timing)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+	uint32_t memory_mask = 0;
+	int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
+	int mpcc_hactive = h_active / opp_cnt;
+	/* Each memory instance is 2048x(32x2) bits to support half line of 4096 */
+	int odm_mem_count = (h_active + 2047) / 2048;
+
+	/*
+	 * display <= 4k : 2 memories + 2 pipes
+	 * 4k < display <= 8k : 4 memories + 2 pipes
+	 * 8k < display <= 12k : 6 memories + 4 pipes
+	 */
+	if (opp_cnt == 4) {
+		if (odm_mem_count <= 2)
+			memory_mask = 0x3;
+		else if (odm_mem_count <= 4)
+			memory_mask = 0xf;
+		else
+			memory_mask = 0x3f;
+	} else {
+		if (odm_mem_count <= 2)
+			memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
+		else if (odm_mem_count <= 4)
+			memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
+		else
+			memory_mask = 0x77;
+	}
+
+	REG_SET(OPTC_MEMORY_CONFIG, 0,
+		OPTC_MEM_SEL, memory_mask);
+
+	if (opp_cnt == 2) {
+		REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
+				OPTC_NUM_OF_INPUT_SEGMENT, 1,
+				OPTC_SEG0_SRC_SEL, opp_id[0],
+				OPTC_SEG1_SRC_SEL, opp_id[1]);
+	} else if (opp_cnt == 4) {
+		REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
+				OPTC_NUM_OF_INPUT_SEGMENT, 3,
+				OPTC_SEG0_SRC_SEL, opp_id[0],
+				OPTC_SEG1_SRC_SEL, opp_id[1],
+				OPTC_SEG2_SRC_SEL, opp_id[2],
+				OPTC_SEG3_SRC_SEL, opp_id[3]);
+	}
+
+	REG_UPDATE(OPTC_WIDTH_CONTROL,
+			OPTC_SEGMENT_WIDTH, mpcc_hactive);
+
+	REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
+	optc1->opp_count = opp_cnt;
+}
+
+/**
+ * Enable CRTC
+ * Enable CRTC - call ASIC Control Object to enable Timing generator.
+ */
+static bool optc32_enable_crtc(struct timing_generator *optc)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	/* opp instance for OTG, 1 to 1 mapping and odm will adjust */
+	REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
+			OPTC_SEG0_SRC_SEL, optc->inst);
+
+	/* VTG enable first is for HW workaround */
+	REG_UPDATE(CONTROL,
+			VTG0_ENABLE, 1);
+
+	REG_SEQ_START();
+
+	/* Enable CRTC */
+	REG_UPDATE_2(OTG_CONTROL,
+			OTG_DISABLE_POINT_CNTL, 2,
+			OTG_MASTER_EN, 1);
+
+	REG_SEQ_SUBMIT();
+	REG_SEQ_WAIT_DONE();
+
+	return true;
+}
+
+/* disable_crtc */
+static bool optc32_disable_crtc(struct timing_generator *optc)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	/* disable otg request until end of the first line
+	 * in the vertical blank region
+	 */
+	REG_UPDATE(OTG_CONTROL,
+			OTG_MASTER_EN, 0);
+
+	REG_UPDATE(CONTROL,
+			VTG0_ENABLE, 0);
+
+	/* CRTC disabled, so disable  clock. */
+	REG_WAIT(OTG_CLOCK_CONTROL,
+			OTG_BUSY, 0,
+			1, 100000);
+
+	return true;
+}
+
+void optc32_phantom_crtc_post_enable(struct timing_generator *optc)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	/* Disable immediately. */
+	REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
+
+	/* CRTC disabled, so disable  clock. */
+	REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
+}
+
+
+static struct timing_generator_funcs dcn32_tg_funcs = {
+		.validate_timing = optc1_validate_timing,
+		.program_timing = optc1_program_timing,
+		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
+		.setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
+		.setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
+		.program_global_sync = optc1_program_global_sync,
+		.enable_crtc = optc32_enable_crtc,
+		.disable_crtc = optc32_disable_crtc,
+		.phantom_crtc_post_enable = optc32_phantom_crtc_post_enable,
+		/* used by enable_timing_synchronization. Not need for FPGA */
+		.is_counter_moving = optc1_is_counter_moving,
+		.get_position = optc1_get_position,
+		.get_frame_count = optc1_get_vblank_counter,
+		.get_scanoutpos = optc1_get_crtc_scanoutpos,
+		.get_otg_active_size = optc1_get_otg_active_size,
+		.set_early_control = optc1_set_early_control,
+		/* used by enable_timing_synchronization. Not need for FPGA */
+		.wait_for_state = optc1_wait_for_state,
+		.set_blank_color = optc3_program_blank_color,
+		.did_triggered_reset_occur = optc1_did_triggered_reset_occur,
+		.triplebuffer_lock = optc3_triplebuffer_lock,
+		.triplebuffer_unlock = optc2_triplebuffer_unlock,
+		.enable_reset_trigger = optc1_enable_reset_trigger,
+		.enable_crtc_reset = optc1_enable_crtc_reset,
+		.disable_reset_trigger = optc1_disable_reset_trigger,
+		.lock = optc3_lock,
+		.unlock = optc1_unlock,
+		.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
+		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
+		.enable_optc_clock = optc1_enable_optc_clock,
+		.set_vrr_m_const = optc3_set_vrr_m_const,
+		.set_drr = optc1_set_drr,
+		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
+		.set_vtotal_min_max = optc1_set_vtotal_min_max,
+		.set_static_screen_control = optc1_set_static_screen_control,
+		.program_stereo = optc1_program_stereo,
+		.is_stereo_left_eye = optc1_is_stereo_left_eye,
+		.tg_init = optc3_tg_init,
+		.is_tg_enabled = optc1_is_tg_enabled,
+		.is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
+		.clear_optc_underflow = optc1_clear_optc_underflow,
+		.setup_global_swap_lock = NULL,
+		.get_crc = optc1_get_crc,
+		.configure_crc = optc1_configure_crc,
+		.set_dsc_config = optc3_set_dsc_config,
+		.get_dsc_status = optc2_get_dsc_status,
+		.set_dwb_source = NULL,
+		.set_odm_bypass = optc3_set_odm_bypass,
+		.set_odm_combine = optc32_set_odm_combine,
+		.get_optc_source = optc2_get_optc_source,
+		.set_out_mux = optc3_set_out_mux,
+		.set_drr_trigger_window = optc3_set_drr_trigger_window,
+		.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
+		.set_gsl = optc2_set_gsl,
+		.set_gsl_source_select = optc2_set_gsl_source_select,
+		.set_vtg_params = optc1_set_vtg_params,
+		.program_manual_trigger = optc2_program_manual_trigger,
+		.setup_manual_trigger = optc2_setup_manual_trigger,
+		.get_hw_timing = optc1_get_hw_timing,
+};
+
+void dcn32_timing_generator_init(struct optc *optc1)
+{
+	optc1->base.funcs = &dcn32_tg_funcs;
+
+	optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
+	optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
+
+	optc1->min_h_blank = 32;
+	optc1->min_v_blank = 3;
+	optc1->min_v_blank_interlace = 5;
+	optc1->min_h_sync_width = 4;
+	optc1->min_v_sync_width = 1;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
new file mode 100644
index 0000000000000..e07b317ed3f45
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
@@ -0,0 +1,253 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_OPTC_DCN32_H__
+#define __DC_OPTC_DCN32_H__
+
+#include "dcn10/dcn10_optc.h"
+
+#define OPTC_COMMON_REG_LIST_DCN3_2(inst) \
+	SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
+	SRI(OTG_VUPDATE_PARAM, OTG, inst),\
+	SRI(OTG_VREADY_PARAM, OTG, inst),\
+	SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
+	SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
+	SRI(OTG_H_TOTAL, OTG, inst),\
+	SRI(OTG_H_BLANK_START_END, OTG, inst),\
+	SRI(OTG_H_SYNC_A, OTG, inst),\
+	SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
+	SRI(OTG_H_TIMING_CNTL, OTG, inst),\
+	SRI(OTG_V_TOTAL, OTG, inst),\
+	SRI(OTG_V_BLANK_START_END, OTG, inst),\
+	SRI(OTG_V_SYNC_A, OTG, inst),\
+	SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
+	SRI(OTG_CONTROL, OTG, inst),\
+	SRI(OTG_STEREO_CONTROL, OTG, inst),\
+	SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
+	SRI(OTG_STEREO_STATUS, OTG, inst),\
+	SRI(OTG_V_TOTAL_MAX, OTG, inst),\
+	SRI(OTG_V_TOTAL_MIN, OTG, inst),\
+	SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
+	SRI(OTG_TRIGA_CNTL, OTG, inst),\
+	SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
+	SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
+	SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
+	SRI(OTG_STATUS, OTG, inst),\
+	SRI(OTG_STATUS_POSITION, OTG, inst),\
+	SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
+	SRI(OTG_M_CONST_DTO0, OTG, inst),\
+	SRI(OTG_M_CONST_DTO1, OTG, inst),\
+	SRI(OTG_CLOCK_CONTROL, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
+	SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
+	SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
+	SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
+	SRI(CONTROL, VTG, inst),\
+	SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
+	SRI(OTG_GSL_CONTROL, OTG, inst),\
+	SRI(OTG_CRC_CNTL, OTG, inst),\
+	SRI(OTG_CRC0_DATA_RG, OTG, inst),\
+	SRI(OTG_CRC0_DATA_B, OTG, inst),\
+	SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
+	SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
+	SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
+	SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
+	SR(GSL_SOURCE_SELECT),\
+	SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
+	SRI(OTG_GSL_WINDOW_X, OTG, inst),\
+	SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
+	SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
+	SRI(OTG_DSC_START_POSITION, OTG, inst),\
+	SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\
+	SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\
+	SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
+	SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
+	SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
+	SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
+	SRI(OTG_DRR_CONTROL, OTG, inst)
+
+#define OPTC_COMMON_MASK_SH_LIST_DCN3_2(mask_sh)\
+	SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
+	SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
+	SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
+	SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
+	SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
+	SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\
+	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
+	SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
+	SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
+	SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
+	SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
+	SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
+	SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
+	SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
+	SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
+	SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
+	SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
+	SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
+	SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\
+	SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
+	SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
+	SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
+	SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
+	SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
+	SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
+	SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
+	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
+	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
+	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
+	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
+	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
+	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
+	SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
+	SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
+	SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
+	SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
+	SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
+	SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
+	SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
+	SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
+	SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\
+	SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\
+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
+	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
+	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
+	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
+	SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
+	SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
+	SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
+	SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
+	SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
+	SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
+	SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
+	SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
+	SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
+	SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
+	SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
+	SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
+	SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
+	SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
+	SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
+	SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
+	SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
+	SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
+	SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
+	SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
+	SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
+	SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
+	SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
+	SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
+	SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\
+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\
+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
+	SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
+	SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
+	SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
+	SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
+	SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
+	SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
+	SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\
+	SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
+	SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
+	SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
+	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
+	SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
+
+void dcn32_timing_generator_init(struct optc *optc1);
+
+#endif /* __DC_OPTC_DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
new file mode 100644
index 0000000000000..17a287bc89ce8
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -0,0 +1,3976 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "dc.h"
+
+#include "dcn32_init.h"
+
+#include "resource.h"
+#include "include/irq_service_interface.h"
+#include "dcn32_resource.h"
+
+#include "dcn20/dcn20_resource.h"
+#include "dcn30/dcn30_resource.h"
+
+#include "dcn10/dcn10_ipp.h"
+#include "dcn30/dcn30_hubbub.h"
+#include "dcn31/dcn31_hubbub.h"
+#include "dcn32/dcn32_hubbub.h"
+#include "dcn32/dcn32_mpc.h"
+#include "dcn32_hubp.h"
+#include "irq/dcn32/irq_service_dcn32.h"
+#include "dcn32/dcn32_dpp.h"
+#include "dcn32/dcn32_optc.h"
+#include "dcn20/dcn20_hwseq.h"
+#include "dcn30/dcn30_hwseq.h"
+#include "dce110/dce110_hw_sequencer.h"
+#include "dcn30/dcn30_opp.h"
+#include "dcn20/dcn20_dsc.h"
+#include "dcn30/dcn30_vpg.h"
+#include "dcn30/dcn30_afmt.h"
+#include "dcn30/dcn30_dio_stream_encoder.h"
+#include "dcn32/dcn32_dio_stream_encoder.h"
+#include "dcn31/dcn31_hpo_dp_stream_encoder.h"
+#include "dcn31/dcn31_hpo_dp_link_encoder.h"
+#include "dcn32/dcn32_hpo_dp_link_encoder.h"
+#include "dc_link_dp.h"
+#include "dcn31/dcn31_apg.h"
+#include "dcn31/dcn31_dio_link_encoder.h"
+#include "dcn32/dcn32_dio_link_encoder.h"
+#include "dce/dce_clock_source.h"
+#include "dce/dce_audio.h"
+#include "dce/dce_hwseq.h"
+#include "clk_mgr.h"
+#include "virtual/virtual_stream_encoder.h"
+#include "dml/display_mode_vba.h"
+#include "dcn32/dcn32_dccg.h"
+#include "dcn10/dcn10_resource.h"
+#include "dc_link_ddc.h"
+#include "dcn31/dcn31_panel_cntl.h"
+
+#include "dcn30/dcn30_dwb.h"
+#include "dcn32/dcn32_mmhubbub.h"
+
+#include "dcn/dcn_3_2_0_offset.h"
+#include "dcn/dcn_3_2_0_sh_mask.h"
+#include "dcn/nbio_4_3_0_offset.h"
+
+#include "reg_helper.h"
+#include "dce/dmub_abm.h"
+#include "dce/dmub_psr.h"
+#include "dce/dce_aux.h"
+#include "dce/dce_i2c.h"
+
+#include "dml/dcn30/display_mode_vba_30.h"
+#include "vm_helper.h"
+#include "dcn20/dcn20_vmid.h"
+
+#define DCN_BASE__INST0_SEG1                       0x000000C0
+#define DCN_BASE__INST0_SEG2                       0x000034C0
+#define DCN_BASE__INST0_SEG3                       0x00009000
+#define NBIO_BASE__INST0_SEG1                      0x00000014
+
+#define MAX_INSTANCE                                        6
+#define MAX_SEGMENT                                         6
+
+struct IP_BASE_INSTANCE {
+	unsigned int segment[MAX_SEGMENT];
+};
+
+struct IP_BASE {
+	struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
+};
+
+static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } } } };
+
+#define DC_LOGGER_INIT(logger)
+
+#define DCN3_2_DEFAULT_DET_SIZE 256
+#define DCN3_2_MAX_DET_SIZE 1152
+#define DCN3_2_MIN_DET_SIZE 128
+#define DCN3_2_MIN_COMPBUF_SIZE_KB 128
+
+struct _vcs_dpi_ip_params_st dcn3_2_ip = {
+	.gpuvm_enable = 1,
+	.gpuvm_max_page_table_levels = 1,
+	.hostvm_enable = 0,
+	.rob_buffer_size_kbytes = 128,
+	.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE,
+	.config_return_buffer_size_in_kbytes = 1280,
+	.compressed_buffer_segment_size_in_kbytes = 64,
+	.meta_fifo_size_in_kentries = 22,
+	.zero_size_buffer_entries = 512,
+	.compbuf_reserved_space_64b = 256,
+	.compbuf_reserved_space_zs = 64,
+	.dpp_output_buffer_pixels = 2560,
+	.opp_output_buffer_lines = 1,
+	.pixel_chunk_size_kbytes = 8,
+	.alpha_pixel_chunk_size_kbytes = 4, // not appearing in spreadsheet, match c code from hw team
+	.min_pixel_chunk_size_bytes = 1024,
+	.dcc_meta_buffer_size_bytes = 6272,
+	.meta_chunk_size_kbytes = 2,
+	.min_meta_chunk_size_bytes = 256,
+	.writeback_chunk_size_kbytes = 8,
+	.ptoi_supported = false,
+	.num_dsc = 4,
+	.maximum_dsc_bits_per_component = 12,
+	.maximum_pixels_per_line_per_dsc_unit = 6016,
+	.dsc422_native_support = true,
+	.is_line_buffer_bpp_fixed = true,
+	.line_buffer_fixed_bpp = 57,
+	.line_buffer_size_bits = 1171920, //DPP doc, DCN3_2_DisplayMode_73.xlsm still shows as 986880 bits with 48 bpp
+	.max_line_buffer_lines = 32,
+	.writeback_interface_buffer_size_kbytes = 90,
+	.max_num_dpp = 4,
+	.max_num_otg = 4,
+	.max_num_hdmi_frl_outputs = 1,
+	.max_num_wb = 1,
+	.max_dchub_pscl_bw_pix_per_clk = 4,
+	.max_pscl_lb_bw_pix_per_clk = 2,
+	.max_lb_vscl_bw_pix_per_clk = 4,
+	.max_vscl_hscl_bw_pix_per_clk = 4,
+	.max_hscl_ratio = 6,
+	.max_vscl_ratio = 6,
+	.max_hscl_taps = 8,
+	.max_vscl_taps = 8,
+	.dpte_buffer_size_in_pte_reqs_luma = 64,
+	.dpte_buffer_size_in_pte_reqs_chroma = 34,
+	.dispclk_ramp_margin_percent = 1,
+	.max_inter_dcn_tile_repeaters = 8,
+	.cursor_buffer_size = 16,
+	.cursor_chunk_size = 2,
+	.writeback_line_buffer_buffer_size = 0,
+	.writeback_min_hscl_ratio = 1,
+	.writeback_min_vscl_ratio = 1,
+	.writeback_max_hscl_ratio = 1,
+	.writeback_max_vscl_ratio = 1,
+	.writeback_max_hscl_taps = 1,
+	.writeback_max_vscl_taps = 1,
+	.dppclk_delay_subtotal = 47,
+	.dppclk_delay_scl = 50,
+	.dppclk_delay_scl_lb_only = 16,
+	.dppclk_delay_cnvc_formatter = 28,
+	.dppclk_delay_cnvc_cursor = 6,
+	.dispclk_delay_subtotal = 125,
+	.dynamic_metadata_vm_enabled = false,
+	.odm_combine_4to1_supported = false,
+	.dcc_supported = true,
+	.max_num_dp2p0_outputs = 2,
+	.max_num_dp2p0_streams = 4,
+};
+
+struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
+	.clock_limits = {
+		{
+			.state = 0,
+			.dcfclk_mhz = 1564.0,
+			.fabricclk_mhz = 400.0,
+			.dispclk_mhz = 2150.0,
+			.dppclk_mhz = 2150.0,
+			.phyclk_mhz = 810.0,
+			.phyclk_d18_mhz = 667.0,
+			.phyclk_d32_mhz = 625.0,
+			.socclk_mhz = 1200.0,
+			.dscclk_mhz = 716.667,
+			.dram_speed_mts = 1600.0,
+			.dtbclk_mhz = 1564.0,
+		},
+	},
+	.num_states = 1,
+	.sr_exit_time_us = 5.20,
+	.sr_enter_plus_exit_time_us = 9.60,
+	.sr_exit_z8_time_us = 285.0,
+	.sr_enter_plus_exit_z8_time_us = 320,
+	.writeback_latency_us = 12.0,
+	.round_trip_ping_latency_dcfclk_cycles = 263,
+	.urgent_latency_pixel_data_only_us = 4.0,
+	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
+	.urgent_latency_vm_data_only_us = 4.0,
+	.fclk_change_latency_us = 20,
+	.usr_retraining_latency_us = 2,
+	.smn_latency_us = 2,
+	.mall_allocated_for_dcn_mbytes = 64,
+	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
+	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
+	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
+	.pct_ideal_sdp_bw_after_urgent = 100.0,
+	.pct_ideal_fabric_bw_after_urgent = 67.0,
+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0,
+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented
+	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented
+	.pct_ideal_dram_bw_after_urgent_strobe = 67.0,
+	.max_avg_sdp_bw_use_normal_percent = 80.0,
+	.max_avg_fabric_bw_use_normal_percent = 60.0,
+	.max_avg_dram_bw_use_normal_strobe_percent = 50.0,
+	.max_avg_dram_bw_use_normal_percent = 15.0,
+	.num_chans = 8,
+	.dram_channel_width_bytes = 2,
+	.fabric_datapath_to_dcn_data_return_bytes = 64,
+	.return_bus_width_bytes = 64,
+	.downspread_percent = 0.38,
+	.dcn_downspread_percent = 0.5,
+	.dram_clock_change_latency_us = 400,
+	.dispclk_dppclk_vco_speed_mhz = 4300.0,
+	.do_urgent_latency_adjustment = true,
+	.urgent_latency_adjustment_fabric_clock_component_us = 1.0,
+	.urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
+};
+
+enum dcn32_clk_src_array_id {
+	DCN32_CLK_SRC_PLL0,
+	DCN32_CLK_SRC_PLL1,
+	DCN32_CLK_SRC_PLL2,
+	DCN32_CLK_SRC_PLL3,
+	DCN32_CLK_SRC_PLL4,
+	DCN32_CLK_SRC_TOTAL
+};
+
+/* begin *********************
+ * macros to expend register list macro defined in HW object header file
+ */
+
+/* DCN */
+/* TODO awful hack. fixup dcn20_dwb.h */
+#undef BASE_INNER
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+#define BASE(seg) BASE_INNER(seg)
+
+#define SR(reg_name)\
+		.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
+					reg ## reg_name
+
+#define SRI(reg_name, block, id)\
+	.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRI2(reg_name, block, id)\
+	.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
+					reg ## reg_name
+
+#define SRIR(var_name, reg_name, block, id)\
+	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRII(reg_name, block, id)\
+	.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRII_MPC_RMU(reg_name, block, id)\
+	.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRII_DWB(reg_name, temp_name, block, id)\
+	.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## temp_name
+
+#define DCCG_SRII(reg_name, block, id)\
+	.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define VUPDATE_SRII(reg_name, block, id)\
+	.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
+					reg ## reg_name ## _ ## block ## id
+
+/* NBIO */
+#define NBIO_BASE_INNER(seg) \
+	NBIO_BASE__INST0_SEG ## seg
+
+#define NBIO_BASE(seg) \
+	NBIO_BASE_INNER(seg)
+
+#define NBIO_SR(reg_name)\
+		.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
+					regBIF_BX0_ ## reg_name
+
+#define CTX ctx
+#define REG(reg_name) \
+	(DCN_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
+
+static const struct bios_registers bios_regs = {
+		NBIO_SR(BIOS_SCRATCH_3),
+		NBIO_SR(BIOS_SCRATCH_6)
+};
+
+#define clk_src_regs(index, pllid)\
+[index] = {\
+	CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
+}
+
+static const struct dce110_clk_src_regs clk_src_regs[] = {
+	clk_src_regs(0, A),
+	clk_src_regs(1, B),
+	clk_src_regs(2, C),
+	clk_src_regs(3, D)
+};
+
+static const struct dce110_clk_src_shift cs_shift = {
+		CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
+};
+
+static const struct dce110_clk_src_mask cs_mask = {
+		CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
+};
+
+#define abm_regs(id)\
+[id] = {\
+		ABM_DCN32_REG_LIST(id)\
+}
+
+static const struct dce_abm_registers abm_regs[] = {
+		abm_regs(0),
+		abm_regs(1),
+		abm_regs(2),
+		abm_regs(3),
+};
+
+static const struct dce_abm_shift abm_shift = {
+		ABM_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dce_abm_mask abm_mask = {
+		ABM_MASK_SH_LIST_DCN32(_MASK)
+};
+
+#define audio_regs(id)\
+[id] = {\
+		AUD_COMMON_REG_LIST(id)\
+}
+
+static const struct dce_audio_registers audio_regs[] = {
+	audio_regs(0),
+	audio_regs(1),
+	audio_regs(2),
+	audio_regs(3),
+	audio_regs(4)
+};
+
+#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
+		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
+
+static const struct dce_audio_shift audio_shift = {
+		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_audio_mask audio_mask = {
+		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
+};
+
+#define vpg_regs(id)\
+[id] = {\
+	VPG_DCN3_REG_LIST(id)\
+}
+
+static const struct dcn30_vpg_registers vpg_regs[] = {
+	vpg_regs(0),
+	vpg_regs(1),
+	vpg_regs(2),
+	vpg_regs(3),
+	vpg_regs(4),
+	vpg_regs(5),
+	vpg_regs(6),
+	vpg_regs(7),
+	vpg_regs(8),
+	vpg_regs(9),
+};
+
+static const struct dcn30_vpg_shift vpg_shift = {
+	DCN3_VPG_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn30_vpg_mask vpg_mask = {
+	DCN3_VPG_MASK_SH_LIST(_MASK)
+};
+
+#define afmt_regs(id)\
+[id] = {\
+	AFMT_DCN3_REG_LIST(id)\
+}
+
+static const struct dcn30_afmt_registers afmt_regs[] = {
+	afmt_regs(0),
+	afmt_regs(1),
+	afmt_regs(2),
+	afmt_regs(3),
+	afmt_regs(4),
+	afmt_regs(5)
+};
+
+static const struct dcn30_afmt_shift afmt_shift = {
+	DCN3_AFMT_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn30_afmt_mask afmt_mask = {
+	DCN3_AFMT_MASK_SH_LIST(_MASK)
+};
+
+#define apg_regs(id)\
+[id] = {\
+	APG_DCN31_REG_LIST(id)\
+}
+
+static const struct dcn31_apg_registers apg_regs[] = {
+	apg_regs(0),
+	apg_regs(1),
+	apg_regs(2),
+	apg_regs(3)
+};
+
+static const struct dcn31_apg_shift apg_shift = {
+	DCN31_APG_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn31_apg_mask apg_mask = {
+		DCN31_APG_MASK_SH_LIST(_MASK)
+};
+
+#define stream_enc_regs(id)\
+[id] = {\
+	SE_DCN32_REG_LIST(id)\
+}
+
+static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
+	stream_enc_regs(0),
+	stream_enc_regs(1),
+	stream_enc_regs(2),
+	stream_enc_regs(3),
+	stream_enc_regs(4)
+};
+
+static const struct dcn10_stream_encoder_shift se_shift = {
+		SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dcn10_stream_encoder_mask se_mask = {
+		SE_COMMON_MASK_SH_LIST_DCN32(_MASK)
+};
+
+
+#define aux_regs(id)\
+[id] = {\
+	DCN2_AUX_REG_LIST(id)\
+}
+
+static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
+		aux_regs(0),
+		aux_regs(1),
+		aux_regs(2),
+		aux_regs(3),
+		aux_regs(4)
+};
+
+#define hpd_regs(id)\
+[id] = {\
+	HPD_REG_LIST(id)\
+}
+
+static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
+		hpd_regs(0),
+		hpd_regs(1),
+		hpd_regs(2),
+		hpd_regs(3),
+		hpd_regs(4)
+};
+
+#define link_regs(id, phyid)\
+[id] = {\
+	LE_DCN31_REG_LIST(id), \
+	UNIPHY_DCN2_REG_LIST(phyid), \
+	/*DPCS_DCN31_REG_LIST(id),*/ \
+}
+
+static const struct dcn10_link_enc_registers link_enc_regs[] = {
+	link_regs(0, A),
+	link_regs(1, B),
+	link_regs(2, C),
+	link_regs(3, D),
+	link_regs(4, E)
+};
+
+static const struct dcn10_link_enc_shift le_shift = {
+	LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
+	//DPCS_DCN31_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn10_link_enc_mask le_mask = {
+	LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
+
+	//DPCS_DCN31_MASK_SH_LIST(_MASK)
+};
+
+#define hpo_dp_stream_encoder_reg_list(id)\
+[id] = {\
+	DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
+}
+
+static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
+	hpo_dp_stream_encoder_reg_list(0),
+	hpo_dp_stream_encoder_reg_list(1),
+	hpo_dp_stream_encoder_reg_list(2),
+	hpo_dp_stream_encoder_reg_list(3),
+};
+
+static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
+	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
+	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
+};
+
+
+#define hpo_dp_link_encoder_reg_list(id)\
+[id] = {\
+	DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
+	/*DCN3_1_RDPCSTX_REG_LIST(0),*/\
+	/*DCN3_1_RDPCSTX_REG_LIST(1),*/\
+	/*DCN3_1_RDPCSTX_REG_LIST(2),*/\
+	/*DCN3_1_RDPCSTX_REG_LIST(3),*/\
+	/*DCN3_1_RDPCSTX_REG_LIST(4)*/\
+}
+
+static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
+	hpo_dp_link_encoder_reg_list(0),
+	hpo_dp_link_encoder_reg_list(1),
+};
+
+static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
+	DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
+	DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
+};
+
+#define dpp_regs(id)\
+[id] = {\
+	DPP_REG_LIST_DCN30_COMMON(id),\
+}
+
+static const struct dcn3_dpp_registers dpp_regs[] = {
+	dpp_regs(0),
+	dpp_regs(1),
+	dpp_regs(2),
+	dpp_regs(3)
+};
+
+static const struct dcn3_dpp_shift tf_shift = {
+		DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT)
+};
+
+static const struct dcn3_dpp_mask tf_mask = {
+		DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK)
+};
+
+
+#define opp_regs(id)\
+[id] = {\
+	OPP_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn20_opp_registers opp_regs[] = {
+	opp_regs(0),
+	opp_regs(1),
+	opp_regs(2),
+	opp_regs(3)
+};
+
+static const struct dcn20_opp_shift opp_shift = {
+	OPP_MASK_SH_LIST_DCN20(__SHIFT)
+};
+
+static const struct dcn20_opp_mask opp_mask = {
+	OPP_MASK_SH_LIST_DCN20(_MASK)
+};
+
+#define aux_engine_regs(id)\
+[id] = {\
+	AUX_COMMON_REG_LIST0(id), \
+	.AUXN_IMPCAL = 0, \
+	.AUXP_IMPCAL = 0, \
+	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
+}
+
+static const struct dce110_aux_registers aux_engine_regs[] = {
+		aux_engine_regs(0),
+		aux_engine_regs(1),
+		aux_engine_regs(2),
+		aux_engine_regs(3),
+		aux_engine_regs(4)
+};
+
+static const struct dce110_aux_registers_shift aux_shift = {
+	DCN_AUX_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce110_aux_registers_mask aux_mask = {
+	DCN_AUX_MASK_SH_LIST(_MASK)
+};
+
+
+#define dwbc_regs_dcn3(id)\
+[id] = {\
+	DWBC_COMMON_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn30_dwbc_registers dwbc30_regs[] = {
+	dwbc_regs_dcn3(0),
+};
+
+static const struct dcn30_dwbc_shift dwbc30_shift = {
+	DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn30_dwbc_mask dwbc30_mask = {
+	DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define mcif_wb_regs_dcn3(id)\
+[id] = {\
+	MCIF_WB_COMMON_REG_LIST_DCN32(id),\
+}
+
+static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
+	mcif_wb_regs_dcn3(0)
+};
+
+static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
+	MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
+	MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
+};
+
+#define dsc_regsDCN20(id)\
+[id] = {\
+	DSC_REG_LIST_DCN20(id)\
+}
+
+static const struct dcn20_dsc_registers dsc_regs[] = {
+	dsc_regsDCN20(0),
+	dsc_regsDCN20(1),
+	dsc_regsDCN20(2),
+	dsc_regsDCN20(3)
+};
+
+static const struct dcn20_dsc_shift dsc_shift = {
+	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
+};
+
+static const struct dcn20_dsc_mask dsc_mask = {
+	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
+};
+
+static const struct dcn30_mpc_registers mpc_regs = {
+		MPC_REG_LIST_DCN3_0(0),
+		MPC_REG_LIST_DCN3_0(1),
+		MPC_REG_LIST_DCN3_0(2),
+		MPC_REG_LIST_DCN3_0(3),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(2),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(3),
+		MPC_MCM_REG_LIST_DCN32(0),
+		MPC_MCM_REG_LIST_DCN32(1),
+		MPC_MCM_REG_LIST_DCN32(2),
+		MPC_MCM_REG_LIST_DCN32(3),
+		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
+};
+
+static const struct dcn30_mpc_shift mpc_shift = {
+	MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dcn30_mpc_mask mpc_mask = {
+	MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
+};
+
+#define optc_regs(id)\
+[id] = {OPTC_COMMON_REG_LIST_DCN3_2(id)}
+
+//#ifdef DIAGS_BUILD
+//static struct dcn_optc_registers optc_regs[] = {
+//#else
+static const struct dcn_optc_registers optc_regs[] = {
+//#endif
+	optc_regs(0),
+	optc_regs(1),
+	optc_regs(2),
+	optc_regs(3)
+};
+
+static const struct dcn_optc_shift optc_shift = {
+	OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
+};
+
+static const struct dcn_optc_mask optc_mask = {
+	OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
+};
+
+#define hubp_regs(id)\
+[id] = {\
+	HUBP_REG_LIST_DCN32(id)\
+}
+
+static const struct dcn_hubp2_registers hubp_regs[] = {
+		hubp_regs(0),
+		hubp_regs(1),
+		hubp_regs(2),
+		hubp_regs(3)
+};
+
+
+static const struct dcn_hubp2_shift hubp_shift = {
+		HUBP_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dcn_hubp2_mask hubp_mask = {
+		HUBP_MASK_SH_LIST_DCN32(_MASK)
+};
+static const struct dcn_hubbub_registers hubbub_reg = {
+		HUBBUB_REG_LIST_DCN32(0)
+};
+
+static const struct dcn_hubbub_shift hubbub_shift = {
+		HUBBUB_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dcn_hubbub_mask hubbub_mask = {
+		HUBBUB_MASK_SH_LIST_DCN32(_MASK)
+};
+
+static const struct dccg_registers dccg_regs = {
+		DCCG_REG_LIST_DCN32()
+};
+
+static const struct dccg_shift dccg_shift = {
+		DCCG_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dccg_mask dccg_mask = {
+		DCCG_MASK_SH_LIST_DCN32(_MASK)
+};
+
+
+#define SRII2(reg_name_pre, reg_name_post, id)\
+	.reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
+			## id ## _ ## reg_name_post ## _BASE_IDX) + \
+			reg ## reg_name_pre ## id ## _ ## reg_name_post
+
+
+#define HWSEQ_DCN32_REG_LIST()\
+	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
+	SR(DIO_MEM_PWR_CTRL), \
+	SR(ODM_MEM_PWR_CTRL3), \
+	SR(MMHUBBUB_MEM_PWR_CNTL), \
+	SR(DCCG_GATE_DISABLE_CNTL), \
+	SR(DCCG_GATE_DISABLE_CNTL2), \
+	SR(DCFCLK_CNTL),\
+	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
+	SRII(PIXEL_RATE_CNTL, OTG, 0), \
+	SRII(PIXEL_RATE_CNTL, OTG, 1),\
+	SRII(PIXEL_RATE_CNTL, OTG, 2),\
+	SRII(PIXEL_RATE_CNTL, OTG, 3),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
+	SR(MICROSECOND_TIME_BASE_DIV), \
+	SR(MILLISECOND_TIME_BASE_DIV), \
+	SR(DISPCLK_FREQ_CHANGE_CNTL), \
+	SR(RBBMIF_TIMEOUT_DIS), \
+	SR(RBBMIF_TIMEOUT_DIS_2), \
+	SR(DCHUBBUB_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
+	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
+	SR(MPC_CRC_CTRL), \
+	SR(MPC_CRC_RESULT_GB), \
+	SR(MPC_CRC_RESULT_C), \
+	SR(MPC_CRC_RESULT_AR), \
+	SR(DOMAIN0_PG_CONFIG), \
+	SR(DOMAIN1_PG_CONFIG), \
+	SR(DOMAIN2_PG_CONFIG), \
+	SR(DOMAIN3_PG_CONFIG), \
+	SR(DOMAIN16_PG_CONFIG), \
+	SR(DOMAIN17_PG_CONFIG), \
+	SR(DOMAIN18_PG_CONFIG), \
+	SR(DOMAIN19_PG_CONFIG), \
+	SR(DOMAIN0_PG_STATUS), \
+	SR(DOMAIN1_PG_STATUS), \
+	SR(DOMAIN2_PG_STATUS), \
+	SR(DOMAIN3_PG_STATUS), \
+	SR(DOMAIN16_PG_STATUS), \
+	SR(DOMAIN17_PG_STATUS), \
+	SR(DOMAIN18_PG_STATUS), \
+	SR(DOMAIN19_PG_STATUS), \
+	SR(D1VGA_CONTROL), \
+	SR(D2VGA_CONTROL), \
+	SR(D3VGA_CONTROL), \
+	SR(D4VGA_CONTROL), \
+	SR(D5VGA_CONTROL), \
+	SR(D6VGA_CONTROL), \
+	SR(DC_IP_REQUEST_CNTL), \
+	SR(AZALIA_AUDIO_DTO), \
+	SR(AZALIA_CONTROLLER_CLOCK_GATING)
+
+static const struct dce_hwseq_registers hwseq_reg = {
+		HWSEQ_DCN32_REG_LIST()
+};
+
+#define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\
+	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
+	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
+	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
+	HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
+	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
+	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
+	HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
+
+static const struct dce_hwseq_shift hwseq_shift = {
+		HWSEQ_DCN32_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_hwseq_mask hwseq_mask = {
+		HWSEQ_DCN32_MASK_SH_LIST(_MASK)
+};
+#define vmid_regs(id)\
+[id] = {\
+		DCN20_VMID_REG_LIST(id)\
+}
+
+static const struct dcn_vmid_registers vmid_regs[] = {
+	vmid_regs(0),
+	vmid_regs(1),
+	vmid_regs(2),
+	vmid_regs(3),
+	vmid_regs(4),
+	vmid_regs(5),
+	vmid_regs(6),
+	vmid_regs(7),
+	vmid_regs(8),
+	vmid_regs(9),
+	vmid_regs(10),
+	vmid_regs(11),
+	vmid_regs(12),
+	vmid_regs(13),
+	vmid_regs(14),
+	vmid_regs(15)
+};
+
+static const struct dcn20_vmid_shift vmid_shifts = {
+		DCN20_VMID_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn20_vmid_mask vmid_masks = {
+		DCN20_VMID_MASK_SH_LIST(_MASK)
+};
+
+static const struct resource_caps res_cap_dcn32 = {
+	.num_timing_generator = 4,
+	.num_opp = 4,
+	.num_video_plane = 4,
+	.num_audio = 5,
+	.num_stream_encoder = 5,
+	.num_hpo_dp_stream_encoder = 4,
+	.num_hpo_dp_link_encoder = 2,
+	.num_pll = 5,
+	.num_dwb = 1,
+	.num_ddc = 5,
+	.num_vmid = 16,
+	.num_mpc_3dlut = 4,
+	.num_dsc = 4,
+};
+
+static const struct dc_plane_cap plane_cap = {
+	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
+	.blends_with_above = true,
+	.blends_with_below = true,
+	.per_pixel_alpha = true,
+
+	.pixel_format_support = {
+			.argb8888 = true,
+			.nv12 = true,
+			.fp16 = true,
+			.p010 = true,
+			.ayuv = false,
+	},
+
+	.max_upscale_factor = {
+			.argb8888 = 16000,
+			.nv12 = 16000,
+			.fp16 = 16000
+	},
+
+	// 6:1 downscaling ratio: 1000/6 = 166.666
+	.max_downscale_factor = {
+			.argb8888 = 167,
+			.nv12 = 167,
+			.fp16 = 167
+	},
+	64,
+	64
+};
+
+static const struct dc_debug_options debug_defaults_drv = {
+	.disable_dmcu = true,
+	.force_abm_enable = false,
+	.timing_trace = false,
+	.clock_trace = true,
+	.disable_pplib_clock_request = false,
+	.pipe_split_policy = MPC_SPLIT_DYNAMIC,
+	.force_single_disp_pipe_split = false,
+	.disable_dcc = DCC_ENABLE,
+	.vsr_support = true,
+	.performance_trace = false,
+	.max_downscale_src_width = 7680,/*upto 8K*/
+	.disable_pplib_wm_range = false,
+	.scl_reset_length10 = true,
+	.sanity_checks = false,
+	.underflow_assert_delay_us = 0xFFFFFFFF,
+	.dwb_fi_phase = -1, // -1 = disable,
+	.dmub_command_table = true,
+	.enable_mem_low_power = {
+		.bits = {
+			.vga = false,
+			.i2c = false,
+			.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
+			.dscl = false,
+			.cm = false,
+			.mpc = false,
+			.optc = false,
+		}
+	},
+	.use_max_lb = true,
+	.force_disable_subvp = true
+};
+
+static const struct dc_debug_options debug_defaults_diags = {
+	.disable_dmcu = true,
+	.force_abm_enable = false,
+	.timing_trace = true,
+	.clock_trace = true,
+	.disable_dpp_power_gate = true,
+	.disable_hubp_power_gate = true,
+	.disable_dsc_power_gate = true,
+	.disable_clock_gate = true,
+	.disable_pplib_clock_request = true,
+	.disable_pplib_wm_range = true,
+	.disable_stutter = false,
+	.scl_reset_length10 = true,
+	.dwb_fi_phase = -1, // -1 = disable
+	.dmub_command_table = true,
+	.enable_tri_buf = true,
+	.use_max_lb = true,
+	.force_disable_subvp = true
+};
+
+static struct dce_aux *dcn32_aux_engine_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct aux_engine_dce110 *aux_engine =
+		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
+
+	if (!aux_engine)
+		return NULL;
+
+	dce110_aux_engine_construct(aux_engine, ctx, inst,
+				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+				    &aux_engine_regs[inst],
+					&aux_mask,
+					&aux_shift,
+					ctx->dc->caps.extended_aux_timeout_support);
+
+	return &aux_engine->base;
+}
+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
+
+static const struct dce_i2c_registers i2c_hw_regs[] = {
+		i2c_inst_regs(1),
+		i2c_inst_regs(2),
+		i2c_inst_regs(3),
+		i2c_inst_regs(4),
+		i2c_inst_regs(5),
+};
+
+static const struct dce_i2c_shift i2c_shifts = {
+		I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dce_i2c_mask i2c_masks = {
+		I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+static struct dce_i2c_hw *dcn32_i2c_hw_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dce_i2c_hw *dce_i2c_hw =
+		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
+
+	if (!dce_i2c_hw)
+		return NULL;
+
+	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
+				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
+
+	return dce_i2c_hw;
+}
+
+static struct clock_source *dcn32_clock_source_create(
+		struct dc_context *ctx,
+		struct dc_bios *bios,
+		enum clock_source_id id,
+		const struct dce110_clk_src_regs *regs,
+		bool dp_clk_src)
+{
+	struct dce110_clk_src *clk_src =
+		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
+
+	if (!clk_src)
+		return NULL;
+
+	if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
+			regs, &cs_shift, &cs_mask)) {
+		clk_src->base.dp_clk_src = dp_clk_src;
+		return &clk_src->base;
+	}
+
+	BREAK_TO_DEBUGGER();
+	return NULL;
+}
+
+static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx)
+{
+	int i;
+
+	struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub),
+					  GFP_KERNEL);
+
+	if (!hubbub2)
+		return NULL;
+
+	hubbub32_construct(hubbub2, ctx,
+			&hubbub_reg,
+			&hubbub_shift,
+			&hubbub_mask,
+			ctx->dc->dml.ip.det_buffer_size_kbytes,
+			ctx->dc->dml.ip.pixel_chunk_size_kbytes,
+			ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);
+
+
+	for (i = 0; i < res_cap_dcn32.num_vmid; i++) {
+		struct dcn20_vmid *vmid = &hubbub2->vmid[i];
+
+		vmid->ctx = ctx;
+
+		vmid->regs = &vmid_regs[i];
+		vmid->shifts = &vmid_shifts;
+		vmid->masks = &vmid_masks;
+	}
+
+	return &hubbub2->base;
+}
+
+static struct hubp *dcn32_hubp_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn20_hubp *hubp2 =
+		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
+
+	if (!hubp2)
+		return NULL;
+
+	if (hubp32_construct(hubp2, ctx, inst,
+			&hubp_regs[inst], &hubp_shift, &hubp_mask))
+		return &hubp2->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(hubp2);
+	return NULL;
+}
+
+static void dcn32_dpp_destroy(struct dpp **dpp)
+{
+	kfree(TO_DCN30_DPP(*dpp));
+	*dpp = NULL;
+}
+
+static struct dpp *dcn32_dpp_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn3_dpp *dpp3 =
+		kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
+
+	if (!dpp3)
+		return NULL;
+
+	if (dpp32_construct(dpp3, ctx, inst,
+			&dpp_regs[inst], &tf_shift, &tf_mask))
+		return &dpp3->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(dpp3);
+	return NULL;
+}
+
+static struct mpc *dcn32_mpc_create(
+		struct dc_context *ctx,
+		int num_mpcc,
+		int num_rmu)
+{
+	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
+					  GFP_KERNEL);
+
+	if (!mpc30)
+		return NULL;
+
+	dcn32_mpc_construct(mpc30, ctx,
+			&mpc_regs,
+			&mpc_shift,
+			&mpc_mask,
+			num_mpcc,
+			num_rmu);
+
+	return &mpc30->base;
+}
+
+static struct output_pixel_processor *dcn32_opp_create(
+	struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn20_opp *opp2 =
+		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
+
+	if (!opp2) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	dcn20_opp_construct(opp2, ctx, inst,
+			&opp_regs[inst], &opp_shift, &opp_mask);
+	return &opp2->base;
+}
+
+
+static struct timing_generator *dcn32_timing_generator_create(
+		struct dc_context *ctx,
+		uint32_t instance)
+{
+	struct optc *tgn10 =
+		kzalloc(sizeof(struct optc), GFP_KERNEL);
+
+	if (!tgn10)
+		return NULL;
+
+	tgn10->base.inst = instance;
+	tgn10->base.ctx = ctx;
+
+	tgn10->tg_regs = &optc_regs[instance];
+	tgn10->tg_shift = &optc_shift;
+	tgn10->tg_mask = &optc_mask;
+
+	dcn32_timing_generator_init(tgn10);
+
+	return &tgn10->base;
+}
+
+static const struct encoder_feature_support link_enc_feature = {
+		.max_hdmi_deep_color = COLOR_DEPTH_121212,
+		.max_hdmi_pixel_clock = 600000,
+		.hdmi_ycbcr420_supported = true,
+		.dp_ycbcr420_supported = true,
+		.fec_supported = true,
+		.flags.bits.IS_HBR2_CAPABLE = true,
+		.flags.bits.IS_HBR3_CAPABLE = true,
+		.flags.bits.IS_TPS3_CAPABLE = true,
+		.flags.bits.IS_TPS4_CAPABLE = true
+};
+
+static struct link_encoder *dcn32_link_encoder_create(
+	const struct encoder_init_data *enc_init_data)
+{
+	struct dcn20_link_encoder *enc20 =
+		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
+
+	if (!enc20)
+		return NULL;
+
+	dcn32_link_encoder_construct(enc20,
+			enc_init_data,
+			&link_enc_feature,
+			&link_enc_regs[enc_init_data->transmitter],
+			&link_enc_aux_regs[enc_init_data->channel - 1],
+			&link_enc_hpd_regs[enc_init_data->hpd_source],
+			&le_shift,
+			&le_mask);
+
+	return &enc20->enc10.base;
+}
+
+struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data)
+{
+	struct dcn31_panel_cntl *panel_cntl =
+		kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
+
+	if (!panel_cntl)
+		return NULL;
+
+	dcn31_panel_cntl_construct(panel_cntl, init_data);
+
+	return &panel_cntl->base;
+}
+
+static void read_dce_straps(
+	struct dc_context *ctx,
+	struct resource_straps *straps)
+{
+	generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
+		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
+
+}
+
+static struct audio *dcn32_create_audio(
+		struct dc_context *ctx, unsigned int inst)
+{
+	return dce_audio_create(ctx, inst,
+			&audio_regs[inst], &audio_shift, &audio_mask);
+}
+
+static struct vpg *dcn32_vpg_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
+
+	if (!vpg3)
+		return NULL;
+
+	vpg3_construct(vpg3, ctx, inst,
+			&vpg_regs[inst],
+			&vpg_shift,
+			&vpg_mask);
+
+	return &vpg3->base;
+}
+
+static struct afmt *dcn32_afmt_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
+
+	if (!afmt3)
+		return NULL;
+
+	afmt3_construct(afmt3, ctx, inst,
+			&afmt_regs[inst],
+			&afmt_shift,
+			&afmt_mask);
+
+	return &afmt3->base;
+}
+
+static struct apg *dcn31_apg_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
+
+	if (!apg31)
+		return NULL;
+
+	apg31_construct(apg31, ctx, inst,
+			&apg_regs[inst],
+			&apg_shift,
+			&apg_mask);
+
+	return &apg31->base;
+}
+
+static struct stream_encoder *dcn32_stream_encoder_create(
+	enum engine_id eng_id,
+	struct dc_context *ctx)
+{
+	struct dcn10_stream_encoder *enc1;
+	struct vpg *vpg;
+	struct afmt *afmt;
+	int vpg_inst;
+	int afmt_inst;
+
+	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
+	if (eng_id <= ENGINE_ID_DIGF) {
+		vpg_inst = eng_id;
+		afmt_inst = eng_id;
+	} else
+		return NULL;
+
+	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
+	vpg = dcn32_vpg_create(ctx, vpg_inst);
+	afmt = dcn32_afmt_create(ctx, afmt_inst);
+
+	if (!enc1 || !vpg || !afmt) {
+		kfree(enc1);
+		kfree(vpg);
+		kfree(afmt);
+		return NULL;
+	}
+
+	dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
+					eng_id, vpg, afmt,
+					&stream_enc_regs[eng_id],
+					&se_shift, &se_mask);
+
+	return &enc1->base;
+}
+
+static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create(
+	enum engine_id eng_id,
+	struct dc_context *ctx)
+{
+	struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
+	struct vpg *vpg;
+	struct apg *apg;
+	uint32_t hpo_dp_inst;
+	uint32_t vpg_inst;
+	uint32_t apg_inst;
+
+	ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
+	hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
+
+	/* Mapping of VPG register blocks to HPO DP block instance:
+	 * VPG[6] -> HPO_DP[0]
+	 * VPG[7] -> HPO_DP[1]
+	 * VPG[8] -> HPO_DP[2]
+	 * VPG[9] -> HPO_DP[3]
+	 */
+	vpg_inst = hpo_dp_inst + 6;
+
+	/* Mapping of APG register blocks to HPO DP block instance:
+	 * APG[0] -> HPO_DP[0]
+	 * APG[1] -> HPO_DP[1]
+	 * APG[2] -> HPO_DP[2]
+	 * APG[3] -> HPO_DP[3]
+	 */
+	apg_inst = hpo_dp_inst;
+
+	/* allocate HPO stream encoder and create VPG sub-block */
+	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
+	vpg = dcn32_vpg_create(ctx, vpg_inst);
+	apg = dcn31_apg_create(ctx, apg_inst);
+
+	if (!hpo_dp_enc31 || !vpg || !apg) {
+		kfree(hpo_dp_enc31);
+		kfree(vpg);
+		kfree(apg);
+		return NULL;
+	}
+
+	dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
+					hpo_dp_inst, eng_id, vpg, apg,
+					&hpo_dp_stream_enc_regs[hpo_dp_inst],
+					&hpo_dp_se_shift, &hpo_dp_se_mask);
+
+	return &hpo_dp_enc31->base;
+}
+
+static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create(
+	uint8_t inst,
+	struct dc_context *ctx)
+{
+	struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
+
+	/* allocate HPO link encoder */
+	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
+
+	hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
+					&hpo_dp_link_enc_regs[inst],
+					&hpo_dp_le_shift, &hpo_dp_le_mask);
+
+	return &hpo_dp_enc31->base;
+}
+
+static struct dce_hwseq *dcn32_hwseq_create(
+	struct dc_context *ctx)
+{
+	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
+
+	if (hws) {
+		hws->ctx = ctx;
+		hws->regs = &hwseq_reg;
+		hws->shifts = &hwseq_shift;
+		hws->masks = &hwseq_mask;
+	}
+	return hws;
+}
+static const struct resource_create_funcs res_create_funcs = {
+	.read_dce_straps = read_dce_straps,
+	.create_audio = dcn32_create_audio,
+	.create_stream_encoder = dcn32_stream_encoder_create,
+	.create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create,
+	.create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create,
+	.create_hwseq = dcn32_hwseq_create,
+};
+
+static const struct resource_create_funcs res_create_maximus_funcs = {
+	.read_dce_straps = NULL,
+	.create_audio = NULL,
+	.create_stream_encoder = NULL,
+	.create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create,
+	.create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create,
+	.create_hwseq = dcn32_hwseq_create,
+};
+
+static void dcn32_resource_destruct(struct dcn32_resource_pool *pool)
+{
+	unsigned int i;
+
+	for (i = 0; i < pool->base.stream_enc_count; i++) {
+		if (pool->base.stream_enc[i] != NULL) {
+			if (pool->base.stream_enc[i]->vpg != NULL) {
+				kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
+				pool->base.stream_enc[i]->vpg = NULL;
+			}
+			if (pool->base.stream_enc[i]->afmt != NULL) {
+				kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
+				pool->base.stream_enc[i]->afmt = NULL;
+			}
+			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
+			pool->base.stream_enc[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
+		if (pool->base.hpo_dp_stream_enc[i] != NULL) {
+			if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
+				kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
+				pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
+			}
+			if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
+				kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
+				pool->base.hpo_dp_stream_enc[i]->apg = NULL;
+			}
+			kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
+			pool->base.hpo_dp_stream_enc[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
+		if (pool->base.hpo_dp_link_enc[i] != NULL) {
+			kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
+			pool->base.hpo_dp_link_enc[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+		if (pool->base.dscs[i] != NULL)
+			dcn20_dsc_destroy(&pool->base.dscs[i]);
+	}
+
+	if (pool->base.mpc != NULL) {
+		kfree(TO_DCN20_MPC(pool->base.mpc));
+		pool->base.mpc = NULL;
+	}
+	if (pool->base.hubbub != NULL) {
+		kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
+		pool->base.hubbub = NULL;
+	}
+	for (i = 0; i < pool->base.pipe_count; i++) {
+		if (pool->base.dpps[i] != NULL)
+			dcn32_dpp_destroy(&pool->base.dpps[i]);
+
+		if (pool->base.ipps[i] != NULL)
+			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
+
+		if (pool->base.hubps[i] != NULL) {
+			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
+			pool->base.hubps[i] = NULL;
+		}
+
+		if (pool->base.irqs != NULL) {
+			dal_irq_service_destroy(&pool->base.irqs);
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+		if (pool->base.engines[i] != NULL)
+			dce110_engine_destroy(&pool->base.engines[i]);
+		if (pool->base.hw_i2cs[i] != NULL) {
+			kfree(pool->base.hw_i2cs[i]);
+			pool->base.hw_i2cs[i] = NULL;
+		}
+		if (pool->base.sw_i2cs[i] != NULL) {
+			kfree(pool->base.sw_i2cs[i]);
+			pool->base.sw_i2cs[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+		if (pool->base.opps[i] != NULL)
+			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+		if (pool->base.timing_generators[i] != NULL)	{
+			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
+			pool->base.timing_generators[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+		if (pool->base.dwbc[i] != NULL) {
+			kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
+			pool->base.dwbc[i] = NULL;
+		}
+		if (pool->base.mcif_wb[i] != NULL) {
+			kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
+			pool->base.mcif_wb[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.audio_count; i++) {
+		if (pool->base.audios[i])
+			dce_aud_destroy(&pool->base.audios[i]);
+	}
+
+	for (i = 0; i < pool->base.clk_src_count; i++) {
+		if (pool->base.clock_sources[i] != NULL) {
+			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
+			pool->base.clock_sources[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+		if (pool->base.mpc_lut[i] != NULL) {
+			dc_3dlut_func_release(pool->base.mpc_lut[i]);
+			pool->base.mpc_lut[i] = NULL;
+		}
+		if (pool->base.mpc_shaper[i] != NULL) {
+			dc_transfer_func_release(pool->base.mpc_shaper[i]);
+			pool->base.mpc_shaper[i] = NULL;
+		}
+	}
+
+	if (pool->base.dp_clock_source != NULL) {
+		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
+		pool->base.dp_clock_source = NULL;
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+		if (pool->base.multiple_abms[i] != NULL)
+			dce_abm_destroy(&pool->base.multiple_abms[i]);
+	}
+
+	if (pool->base.psr != NULL)
+		dmub_psr_destroy(&pool->base.psr);
+
+	if (pool->base.dccg != NULL)
+		dcn_dccg_destroy(&pool->base.dccg);
+
+	if (pool->base.oem_device != NULL)
+		dal_ddc_service_destroy(&pool->base.oem_device);
+}
+
+
+static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+	int i;
+	uint32_t dwb_count = pool->res_cap->num_dwb;
+
+	for (i = 0; i < dwb_count; i++) {
+		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
+						    GFP_KERNEL);
+
+		if (!dwbc30) {
+			dm_error("DC: failed to create dwbc30!\n");
+			return false;
+		}
+
+		dcn30_dwbc_construct(dwbc30, ctx,
+				&dwbc30_regs[i],
+				&dwbc30_shift,
+				&dwbc30_mask,
+				i);
+
+		pool->dwbc[i] = &dwbc30->base;
+	}
+	return true;
+}
+
+static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+	int i;
+	uint32_t dwb_count = pool->res_cap->num_dwb;
+
+	for (i = 0; i < dwb_count; i++) {
+		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
+						    GFP_KERNEL);
+
+		if (!mcif_wb30) {
+			dm_error("DC: failed to create mcif_wb30!\n");
+			return false;
+		}
+
+		dcn32_mmhubbub_construct(mcif_wb30, ctx,
+				&mcif_wb30_regs[i],
+				&mcif_wb30_shift,
+				&mcif_wb30_mask,
+				i);
+
+		pool->mcif_wb[i] = &mcif_wb30->base;
+	}
+	return true;
+}
+
+static struct display_stream_compressor *dcn32_dsc_create(
+	struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn20_dsc *dsc =
+		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
+
+	if (!dsc) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
+	return &dsc->base;
+}
+
+static void dcn32_destroy_resource_pool(struct resource_pool **pool)
+{
+	struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool);
+
+	dcn32_resource_destruct(dcn32_pool);
+	kfree(dcn32_pool);
+	*pool = NULL;
+}
+
+bool dcn32_acquire_post_bldn_3dlut(
+		struct resource_context *res_ctx,
+		const struct resource_pool *pool,
+		int mpcc_id,
+		struct dc_3dlut **lut,
+		struct dc_transfer_func **shaper)
+{
+	bool ret = false;
+	union dc_3dlut_state *state;
+
+	ASSERT(*lut == NULL && *shaper == NULL);
+	*lut = NULL;
+	*shaper = NULL;
+
+	if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) {
+		*lut = pool->mpc_lut[mpcc_id];
+		*shaper = pool->mpc_shaper[mpcc_id];
+		state = &pool->mpc_lut[mpcc_id]->state;
+		res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true;
+		ret = true;
+	}
+	return ret;
+}
+
+bool dcn32_release_post_bldn_3dlut(
+		struct resource_context *res_ctx,
+		const struct resource_pool *pool,
+		struct dc_3dlut **lut,
+		struct dc_transfer_func **shaper)
+{
+	int i;
+	bool ret = false;
+
+	for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
+		if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
+			res_ctx->is_mpc_3dlut_acquired[i] = false;
+			pool->mpc_lut[i]->state.raw = 0;
+			*lut = NULL;
+			*shaper = NULL;
+			ret = true;
+			break;
+		}
+	}
+	return ret;
+}
+
+/**
+ ********************************************************************************************
+ * dcn32_get_num_free_pipes: Calculate number of free pipes
+ *
+ * This function assumes that a "used" pipe is a pipe that has
+ * both a stream and a plane assigned to it.
+ *
+ * @param [in] dc: current dc state
+ * @param [in] context: new dc state
+ *
+ * @return: Number of free pipes available in the context
+ *
+ ********************************************************************************************
+ */
+static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context)
+{
+	unsigned int i;
+	unsigned int free_pipes = 0;
+	unsigned int num_pipes = 0;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+		if (pipe->stream && pipe->plane_state && !pipe->top_pipe) {
+			while (pipe) {
+				num_pipes++;
+				pipe = pipe->bottom_pipe;
+			}
+		}
+	}
+
+	free_pipes = dc->res_pool->pipe_count - num_pipes;
+	return free_pipes;
+}
+
+/**
+ ********************************************************************************************
+ * dcn32_assign_subvp_pipe: Function to decide which pipe will use Sub-VP.
+ *
+ * We enter this function if we are Sub-VP capable (i.e. enough pipes available)
+ * and regular P-State switching (i.e. VACTIVE/VBLANK) is not supported, or if
+ * we are forcing SubVP P-State switching on the current config.
+ *
+ * The number of pipes used for the chosen surface must be less than or equal to the
+ * number of free pipes available.
+ *
+ * In general we choose surfaces that have ActiveDRAMClockChangeLatencyMargin <= 0 first,
+ * then among those surfaces we choose the one with the smallest VBLANK time. We only consider
+ * surfaces with ActiveDRAMClockChangeLatencyMargin > 0 if we are forcing a Sub-VP config.
+ *
+ * @param [in] dc: current dc state
+ * @param [in] context: new dc state
+ * @param [out] index: dc pipe index for the pipe chosen to have phantom pipes assigned
+ *
+ * @return: True if a valid pipe assignment was found for Sub-VP. Otherwise false.
+ *
+ ********************************************************************************************
+ */
+
+static bool dcn32_assign_subvp_pipe(struct dc *dc,
+		struct dc_state *context,
+		unsigned int *index)
+{
+	unsigned int i, pipe_idx;
+	unsigned int min_vblank_us = INT_MAX;
+	struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
+	bool valid_assignment_found = false;
+	unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context);
+
+	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		unsigned int num_pipes = 0;
+
+		if (!pipe->stream)
+			continue;
+
+		if (pipe->plane_state && !pipe->top_pipe &&
+				pipe->stream->mall_stream_config.type == SUBVP_NONE) {
+			while (pipe) {
+				num_pipes++;
+				pipe = pipe->bottom_pipe;
+			}
+
+			pipe = &context->res_ctx.pipe_ctx[i];
+			if (num_pipes <= free_pipes) {
+				struct dc_stream_state *stream = pipe->stream;
+				unsigned int vblank_us = ((stream->timing.v_total - stream->timing.v_addressable) *
+							stream->timing.h_total /
+							(double)(stream->timing.pix_clk_100hz * 100)) * 1000000;
+				if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] <= 0 &&
+						vblank_us < min_vblank_us) {
+					*index = i;
+					min_vblank_us = vblank_us;
+					valid_assignment_found = true;
+				} else if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0 &&
+						dc->debug.force_subvp_mclk_switch && !valid_assignment_found) {
+					// Handle case for forcing Sub-VP config. In this case we can assign
+					// phantom pipes to a surface that has active margin > 0.
+					*index = i;
+					valid_assignment_found = true;
+				}
+			}
+		}
+		pipe_idx++;
+	}
+	return valid_assignment_found;
+}
+
+/**
+ * ***************************************************************************************
+ * dcn32_enough_pipes_for_subvp: Function to check if there are "enough" pipes for SubVP.
+ *
+ * This function returns true if there are enough free pipes
+ * to create the required phantom pipes for any given stream
+ * (that does not already have phantom pipe assigned).
+ *
+ * e.g. For a 2 stream config where the first stream uses one
+ * pipe and the second stream uses 2 pipes (i.e. pipe split),
+ * this function will return true because there is 1 remaining
+ * pipe which can be used as the phantom pipe for the non pipe
+ * split pipe.
+ *
+ * @param [in] dc: current dc state
+ * @param [in] context: new dc state
+ *
+ * @return: True if there are enough free pipes to assign phantom pipes to at least one
+ *          stream that does not already have phantom pipes assigned. Otherwise false.
+ *
+ * ***************************************************************************************
+ */
+static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context)
+{
+	unsigned int i, split_cnt, free_pipes;
+	unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1
+	bool subvp_possible = false;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+		// Find the minimum pipe split count for non SubVP pipes
+		if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
+				pipe->stream->mall_stream_config.type == SUBVP_NONE) {
+			split_cnt = 0;
+			while (pipe) {
+				split_cnt++;
+				pipe = pipe->bottom_pipe;
+			}
+
+			if (split_cnt < min_pipe_split)
+				min_pipe_split = split_cnt;
+		}
+	}
+
+	free_pipes = dcn32_get_num_free_pipes(dc, context);
+
+	// SubVP only possible if at least one pipe is being used (i.e. free_pipes
+	// should not equal to the pipe_count)
+	if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count)
+		subvp_possible = true;
+
+	return subvp_possible;
+}
+
+static void dcn32_enable_phantom_plane(struct dc *dc,
+		struct dc_state *context,
+		struct dc_stream_state *phantom_stream,
+		unsigned int dc_pipe_idx)
+{
+	struct dc_plane_state *phantom_plane = NULL;
+	struct dc_plane_state *prev_phantom_plane = NULL;
+	struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
+
+	while (curr_pipe) {
+		if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state)
+			phantom_plane = prev_phantom_plane;
+		else
+			phantom_plane = dc_create_plane_state(dc);
+
+		memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address));
+		memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality,
+				sizeof(phantom_plane->scaling_quality));
+		memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect));
+		memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect));
+		memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect));
+		memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size,
+				sizeof(phantom_plane->plane_size));
+		memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info,
+				sizeof(phantom_plane->tiling_info));
+		memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc));
+		phantom_plane->format = curr_pipe->plane_state->format;
+		phantom_plane->rotation = curr_pipe->plane_state->rotation;
+		phantom_plane->visible = curr_pipe->plane_state->visible;
+
+		/* Shadow pipe has small viewport. */
+		phantom_plane->clip_rect.y = 0;
+		phantom_plane->clip_rect.height = phantom_stream->timing.v_addressable;
+
+		dc_add_plane_to_context(dc, phantom_stream, phantom_plane, context);
+
+		curr_pipe = curr_pipe->bottom_pipe;
+		prev_phantom_plane = phantom_plane;
+	}
+}
+
+/**
+ * ***************************************************************************************
+ * dcn32_set_phantom_stream_timing: Set timing params for the phantom stream
+ *
+ * Set timing params of the phantom stream based on calculated output from DML.
+ * This function first gets the DML pipe index using the DC pipe index, then
+ * calls into DML (get_subviewport_lines_needed_in_mall) to get the number of
+ * lines required for SubVP MCLK switching and assigns to the phantom stream
+ * accordingly.
+ *
+ * - The number of SubVP lines calculated in DML does not take into account
+ * FW processing delays and required pstate allow width, so we must include
+ * that separately.
+ *
+ * - Set phantom backporch = vstartup of main pipe
+ *
+ * @param [in] dc: current dc state
+ * @param [in] context: new dc state
+ * @param [in] ref_pipe: Main pipe for the phantom stream
+ * @param [in] pipes: DML pipe params
+ * @param [in] pipe_cnt: number of DML pipes
+ * @param [in] dc_pipe_idx: DC pipe index for the main pipe (i.e. ref_pipe)
+ *
+ * @return: void
+ *
+ * ***************************************************************************************
+ */
+static void dcn32_set_phantom_stream_timing(struct dc *dc,
+		struct dc_state *context,
+		struct pipe_ctx *ref_pipe,
+		struct dc_stream_state *phantom_stream,
+		display_e2e_pipe_params_st *pipes,
+		unsigned int pipe_cnt,
+		unsigned int dc_pipe_idx)
+{
+	unsigned int i, pipe_idx;
+	struct pipe_ctx *pipe;
+	uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines;
+	unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel;
+	unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
+	unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel];
+
+	// Find DML pipe index (pipe_idx) using dc_pipe_idx
+	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+		pipe = &context->res_ctx.pipe_ctx[i];
+
+		if (!pipe->stream)
+			continue;
+
+		if (i == dc_pipe_idx)
+			break;
+
+		pipe_idx++;
+	}
+
+	// Calculate lines required for pstate allow width and FW processing delays
+	pstate_width_fw_delay_lines = ((double)(dc->caps.subvp_fw_processing_delay_us +
+			dc->caps.subvp_pstate_allow_width_us) / 1000000) *
+			(ref_pipe->stream->timing.pix_clk_100hz * 100) /
+			(double)ref_pipe->stream->timing.h_total;
+
+	// Update clks_cfg for calling into recalculate
+	pipes[0].clks_cfg.voltage = vlevel;
+	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
+	pipes[0].clks_cfg.socclk_mhz = socclk;
+
+	// DML calculation for MALL region doesn't take into account FW delay
+	// and required pstate allow width for multi-display cases
+	phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) +
+				pstate_width_fw_delay_lines;
+
+	// For backporch of phantom pipe, use vstartup of the main pipe
+	phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
+
+	phantom_stream->dst.y = 0;
+	phantom_stream->dst.height = phantom_vactive;
+	phantom_stream->src.y = 0;
+	phantom_stream->src.height = phantom_vactive;
+
+	phantom_stream->timing.v_addressable = phantom_vactive;
+	phantom_stream->timing.v_front_porch = 1;
+	phantom_stream->timing.v_total = phantom_stream->timing.v_addressable +
+						phantom_stream->timing.v_front_porch +
+						phantom_stream->timing.v_sync_width +
+						phantom_bp;
+}
+
+static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc,
+		struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		unsigned int pipe_cnt,
+		unsigned int dc_pipe_idx)
+{
+	struct dc_stream_state *phantom_stream = NULL;
+	struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
+
+	phantom_stream = dc_create_stream_for_sink(ref_pipe->stream->sink);
+	phantom_stream->signal = SIGNAL_TYPE_VIRTUAL;
+	phantom_stream->dpms_off = true;
+	phantom_stream->mall_stream_config.type = SUBVP_PHANTOM;
+	phantom_stream->mall_stream_config.paired_stream = ref_pipe->stream;
+	ref_pipe->stream->mall_stream_config.type = SUBVP_MAIN;
+	ref_pipe->stream->mall_stream_config.paired_stream = phantom_stream;
+
+	/* stream has limited viewport and small timing */
+	memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing));
+	memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src));
+	memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst));
+	dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx);
+
+	dc_add_stream_to_ctx(dc, context, phantom_stream);
+	return phantom_stream;
+}
+
+void dcn32_remove_phantom_pipes(struct dc *dc, struct dc_state *context)
+{
+	int i;
+	bool removed_pipe = false;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		// build scaling params for phantom pipes
+		if (pipe->plane_state && pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
+			dc_rem_all_planes_for_stream(dc, pipe->stream, context);
+			dc_remove_stream_from_ctx(dc, context, pipe->stream);
+			removed_pipe = true;
+		}
+
+		// Clear all phantom stream info
+		if (pipe->stream) {
+			pipe->stream->mall_stream_config.type = SUBVP_NONE;
+			pipe->stream->mall_stream_config.paired_stream = NULL;
+		}
+	}
+	if (removed_pipe)
+		dc->hwss.apply_ctx_to_hw(dc, context);
+}
+
+/* TODO: Input to this function should indicate which pipe indexes (or streams)
+ * require a phantom pipe / stream
+ */
+void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		unsigned int pipe_cnt,
+		unsigned int index)
+{
+	struct dc_stream_state *phantom_stream = NULL;
+	unsigned int i;
+
+	// The index of the DC pipe passed into this function is guarenteed to
+	// be a valid candidate for SubVP (i.e. has a plane, stream, doesn't
+	// already have phantom pipe assigned, etc.) by previous checks.
+	phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index);
+	dcn32_enable_phantom_plane(dc, context, phantom_stream, index);
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+		// Build scaling params for phantom pipes which were newly added.
+		// We determine which phantom pipes were added by comparing with
+		// the phantom stream.
+		if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream &&
+				pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
+			pipe->stream->use_dynamic_meta = false;
+			pipe->plane_state->flip_immediate = false;
+			if (!resource_build_scaling_params(pipe)) {
+				// Log / remove phantom pipes since failed to build scaling params
+			}
+		}
+	}
+}
+
+static bool dcn32_split_stream_for_mpc_or_odm(
+		const struct dc *dc,
+		struct resource_context *res_ctx,
+		struct pipe_ctx *pri_pipe,
+		struct pipe_ctx *sec_pipe,
+		bool odm)
+{
+	int pipe_idx = sec_pipe->pipe_idx;
+	const struct resource_pool *pool = dc->res_pool;
+
+	if (pri_pipe->plane_state) {
+		/* ODM + window MPO, where MPO window is on left half only */
+		if (pri_pipe->plane_state->clip_rect.x + pri_pipe->plane_state->clip_rect.width <=
+				pri_pipe->stream->src.x + pri_pipe->stream->src.width/2)
+			return true;
+
+		/* ODM + window MPO, where MPO window is on right half only */
+		if (pri_pipe->plane_state->clip_rect.x >= pri_pipe->stream->src.width/2)
+			return true;
+	}
+
+	*sec_pipe = *pri_pipe;
+
+	sec_pipe->pipe_idx = pipe_idx;
+	sec_pipe->plane_res.mi = pool->mis[pipe_idx];
+	sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
+	sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
+	sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
+	sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
+	sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
+	sec_pipe->stream_res.dsc = NULL;
+	if (odm) {
+		if (pri_pipe->next_odm_pipe) {
+			ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
+			sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
+			sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
+		}
+		if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
+			pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
+			sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
+		}
+		if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
+			pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
+			sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
+		}
+		pri_pipe->next_odm_pipe = sec_pipe;
+		sec_pipe->prev_odm_pipe = pri_pipe;
+		ASSERT(sec_pipe->top_pipe == NULL);
+
+		if (!sec_pipe->top_pipe)
+			sec_pipe->stream_res.opp = pool->opps[pipe_idx];
+		else
+			sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
+		if (sec_pipe->stream->timing.flags.DSC == 1) {
+			dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
+			ASSERT(sec_pipe->stream_res.dsc);
+			if (sec_pipe->stream_res.dsc == NULL)
+				return false;
+		}
+	} else {
+		if (pri_pipe->bottom_pipe) {
+			ASSERT(pri_pipe->bottom_pipe != sec_pipe);
+			sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
+			sec_pipe->bottom_pipe->top_pipe = sec_pipe;
+		}
+		pri_pipe->bottom_pipe = sec_pipe;
+		sec_pipe->top_pipe = pri_pipe;
+
+		ASSERT(pri_pipe->plane_state);
+	}
+
+	return true;
+}
+
+static struct pipe_ctx *dcn32_find_split_pipe(
+		struct dc *dc,
+		struct dc_state *context,
+		int old_index)
+{
+	struct pipe_ctx *pipe = NULL;
+	int i;
+
+	if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
+		pipe = &context->res_ctx.pipe_ctx[old_index];
+		pipe->pipe_idx = old_index;
+	}
+
+	if (!pipe)
+		for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
+			if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
+					&& dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
+				if (context->res_ctx.pipe_ctx[i].stream == NULL) {
+					pipe = &context->res_ctx.pipe_ctx[i];
+					pipe->pipe_idx = i;
+					break;
+				}
+			}
+		}
+
+	/*
+	 * May need to fix pipes getting tossed from 1 opp to another on flip
+	 * Add for debugging transient underflow during topology updates:
+	 * ASSERT(pipe);
+	 */
+	if (!pipe)
+		for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
+			if (context->res_ctx.pipe_ctx[i].stream == NULL) {
+				pipe = &context->res_ctx.pipe_ctx[i];
+				pipe->pipe_idx = i;
+				break;
+			}
+		}
+
+	return pipe;
+}
+
+
+/**
+ * ***************************************************************************************
+ * subvp_subvp_schedulable: Determine if SubVP + SubVP config is schedulable
+ *
+ * High level algorithm:
+ * 1. Find longest microschedule length (in us) between the two SubVP pipes
+ * 2. Check if the worst case overlap (VBLANK in middle of ACTIVE) for both
+ * pipes still allows for the maximum microschedule to fit in the active
+ * region for both pipes.
+ *
+ * @param [in] dc: current dc state
+ * @param [in] context: new dc state
+ *
+ * @return: bool - True if the SubVP + SubVP config is schedulable, false otherwise
+ *
+ * ***************************************************************************************
+ */
+static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context)
+{
+	struct pipe_ctx *subvp_pipes[2];
+	struct dc_stream_state *phantom = NULL;
+	uint32_t microschedule_lines = 0;
+	uint32_t index = 0;
+	uint32_t i;
+	uint32_t max_microschedule_us = 0;
+	int32_t vactive1_us, vactive2_us, vblank1_us, vblank2_us;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		uint32_t time_us = 0;
+
+		/* Loop to calculate the maximum microschedule time between the two SubVP pipes,
+		 * and also to store the two main SubVP pipe pointers in subvp_pipes[2].
+		 */
+		if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
+				pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
+			phantom = pipe->stream->mall_stream_config.paired_stream;
+			microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) +
+					phantom->timing.v_addressable;
+
+			// Round up when calculating microschedule time
+			time_us = ((microschedule_lines * phantom->timing.h_total +
+					phantom->timing.pix_clk_100hz * 100 - 1) /
+					(double)(phantom->timing.pix_clk_100hz * 100)) * 1000000 +
+						dc->caps.subvp_prefetch_end_to_mall_start_us +
+						dc->caps.subvp_fw_processing_delay_us;
+			if (time_us > max_microschedule_us)
+				max_microschedule_us = time_us;
+
+			subvp_pipes[index] = pipe;
+			index++;
+
+			// Maximum 2 SubVP pipes
+			if (index == 2)
+				break;
+		}
+	}
+	vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) /
+			(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
+	vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) /
+				(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
+	vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) *
+			subvp_pipes[0]->stream->timing.h_total) /
+			(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
+	vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) *
+			subvp_pipes[1]->stream->timing.h_total) /
+			(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
+
+	if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us &&
+			(vactive2_us - vblank1_us) / 2 > max_microschedule_us)
+		return true;
+
+	return false;
+}
+
+/**
+ * ***************************************************************************************
+ * subvp_drr_schedulable: Determine if SubVP + DRR config is schedulable
+ *
+ * High level algorithm:
+ * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
+ * 2. Determine the frame time for the DRR display when adding required margin for MCLK switching
+ * (the margin is equal to the MALL region + DRR margin (500us))
+ * 3.If (SubVP Active - Prefetch > Stretched DRR frame + max(MALL region, Stretched DRR frame))
+ * then report the configuration as supported
+ *
+ * @param [in] dc: current dc state
+ * @param [in] context: new dc state
+ * @param [in] drr_pipe: DRR pipe_ctx for the SubVP + DRR config
+ *
+ * @return: bool - True if the SubVP + DRR config is schedulable, false otherwise
+ *
+ * ***************************************************************************************
+ */
+static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context, struct pipe_ctx *drr_pipe)
+{
+	bool schedulable = false;
+	uint32_t i;
+	struct pipe_ctx *pipe = NULL;
+	struct dc_crtc_timing *main_timing = NULL;
+	struct dc_crtc_timing *phantom_timing = NULL;
+	struct dc_crtc_timing *drr_timing = NULL;
+	int16_t prefetch_us = 0;
+	int16_t mall_region_us = 0;
+	int16_t drr_frame_us = 0;	// nominal frame time
+	int16_t subvp_active_us = 0;
+	int16_t stretched_drr_us = 0;
+	int16_t drr_stretched_vblank_us = 0;
+	int16_t max_vblank_mallregion = 0;
+
+	// Find SubVP pipe
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		pipe = &context->res_ctx.pipe_ctx[i];
+
+		// We check for master pipe, but it shouldn't matter since we only need
+		// the pipe for timing info (stream should be same for any pipe splits)
+		if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)
+			continue;
+
+		// Find the SubVP pipe
+		if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
+			break;
+	}
+
+	main_timing = &pipe->stream->timing;
+	phantom_timing = &pipe->stream->mall_stream_config.paired_stream->timing;
+	drr_timing = &drr_pipe->stream->timing;
+	prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
+			(double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
+			dc->caps.subvp_prefetch_end_to_mall_start_us;
+	subvp_active_us = main_timing->v_addressable * main_timing->h_total /
+			(double)(main_timing->pix_clk_100hz * 100) * 1000000;
+	drr_frame_us = drr_timing->v_total * drr_timing->h_total /
+			(double)(drr_timing->pix_clk_100hz * 100) * 1000000;
+	// P-State allow width and FW delays already included phantom_timing->v_addressable
+	mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
+			(double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
+	stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
+	drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total /
+			(double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us);
+	max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us;
+
+	/* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the
+	 * highest refresh rate + margin that can support UCLK P-State switch) passes the static analysis
+	 * for VBLANK: (VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
+	 * and the max of (VBLANK blanking time, MALL region)).
+	 */
+	if (stretched_drr_us < (1 / (double)drr_timing->min_refresh_in_uhz) * 1000000 * 1000000 &&
+			subvp_active_us - prefetch_us - stretched_drr_us - max_vblank_mallregion > 0)
+		schedulable = true;
+
+	return schedulable;
+}
+
+/**
+ * ***************************************************************************************
+ * subvp_vblank_schedulable: Determine if SubVP + VBLANK config is schedulable
+ *
+ * High level algorithm:
+ * 1. Get timing for SubVP pipe, phantom pipe, and VBLANK pipe
+ * 2. If (SubVP Active - Prefetch > Vblank Frame Time + max(MALL region, Vblank blanking time))
+ * then report the configuration as supported
+ * 3. If the VBLANK display is DRR, then take the DRR static schedulability path
+ *
+ * @param [in] dc: current dc state
+ * @param [in] context: new dc state
+ *
+ * @return: bool - True if the SubVP + VBLANK/DRR config is schedulable, false otherwise
+ *
+ * ***************************************************************************************
+ */
+static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)
+{
+	struct pipe_ctx *pipe = NULL;
+	struct pipe_ctx *subvp_pipe = NULL;
+	bool found = false;
+	bool schedulable = false;
+	uint32_t i = 0;
+	uint8_t vblank_index = 0;
+	int16_t prefetch_us = 0;
+	int16_t mall_region_us = 0;
+	int16_t vblank_frame_us = 0;
+	int16_t subvp_active_us = 0;
+	int16_t vblank_blank_us = 0;
+	int16_t max_vblank_mallregion = 0;
+	struct dc_crtc_timing *main_timing = NULL;
+	struct dc_crtc_timing *phantom_timing = NULL;
+	struct dc_crtc_timing *vblank_timing = NULL;
+
+	/* For SubVP + VBLANK/DRR cases, we assume there can only be
+	 * a single VBLANK/DRR display. If DML outputs SubVP + VBLANK
+	 * is supported, it is either a single VBLANK case or two VBLANK
+	 * displays which are synchronized (in which case they have identical
+	 * timings).
+	 */
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		pipe = &context->res_ctx.pipe_ctx[i];
+
+		// We check for master pipe, but it shouldn't matter since we only need
+		// the pipe for timing info (stream should be same for any pipe splits)
+		if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)
+			continue;
+
+		if (!found && pipe->stream->mall_stream_config.type == SUBVP_NONE) {
+			// Found pipe which is not SubVP or Phantom (i.e. the VBLANK pipe).
+			vblank_index = i;
+			found = true;
+		}
+
+		if (!subvp_pipe && pipe->stream->mall_stream_config.type == SUBVP_MAIN)
+			subvp_pipe = pipe;
+	}
+	// Use ignore_msa_timing_param flag to identify as DRR
+	if (found && pipe->stream->ignore_msa_timing_param) {
+		// SUBVP + DRR case
+		schedulable = subvp_drr_schedulable(dc, context, &context->res_ctx.pipe_ctx[vblank_index]);
+	} else if (found) {
+		main_timing = &subvp_pipe->stream->timing;
+		phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
+		vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;
+		// Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe
+		// Also include the prefetch end to mallstart delay time
+		prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
+				(double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
+				dc->caps.subvp_prefetch_end_to_mall_start_us;
+		// P-State allow width and FW delays already included phantom_timing->v_addressable
+		mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
+				(double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
+		vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total /
+				(double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
+		vblank_blank_us =  (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total /
+				(double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
+		subvp_active_us = main_timing->v_addressable * main_timing->h_total /
+				(double)(main_timing->pix_clk_100hz * 100) * 1000000;
+		max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us;
+
+		// Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
+		// and the max of (VBLANK blanking time, MALL region)
+		// TODO: Possibly add some margin (i.e. the below conditions should be [...] > X instead of [...] > 0)
+		if (subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion > 0)
+			schedulable = true;
+	}
+	return schedulable;
+}
+
+/**
+ * ********************************************************************************************
+ * subvp_validate_static_schedulability: Check which SubVP case is calculated and handle
+ * static analysis based on the case.
+ *
+ * Three cases:
+ * 1. SubVP + SubVP
+ * 2. SubVP + VBLANK (DRR checked internally)
+ * 3. SubVP + VACTIVE (currently unsupported)
+ *
+ * @param [in] dc: current dc state
+ * @param [in] context: new dc state
+ * @param [in] vlevel: Voltage level calculated by DML
+ *
+ * @return: bool - True if statically schedulable, false otherwise
+ *
+ * ********************************************************************************************
+ */
+static bool subvp_validate_static_schedulability(struct dc *dc,
+				struct dc_state *context,
+				int vlevel)
+{
+	bool schedulable = true;	// true by default for single display case
+	struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
+	uint32_t i, pipe_idx;
+	uint8_t subvp_count = 0;
+	uint8_t vactive_count = 0;
+
+	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+		if (!pipe->stream)
+			continue;
+
+		if (pipe->plane_state && !pipe->top_pipe &&
+				pipe->stream->mall_stream_config.type == SUBVP_MAIN)
+			subvp_count++;
+
+		// Count how many planes are capable of VACTIVE switching (SubVP + VACTIVE unsupported)
+		if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0) {
+			vactive_count++;
+		}
+		pipe_idx++;
+	}
+
+	if (subvp_count == 2) {
+		// Static schedulability check for SubVP + SubVP case
+		schedulable = subvp_subvp_schedulable(dc, context);
+	} else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp) {
+		// Static schedulability check for SubVP + VBLANK case. Also handle the case where
+		// DML outputs SubVP + VBLANK + VACTIVE (DML will report as SubVP + VBLANK)
+		if (vactive_count > 0)
+			schedulable = false;
+		else
+			schedulable = subvp_vblank_schedulable(dc, context);
+	} else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_mall_sub_vp) {
+		// SubVP + VACTIVE currently unsupported
+		schedulable = false;
+	}
+	return schedulable;
+}
+
+static void dcn32_full_validate_bw_helper(struct dc *dc,
+		struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int *vlevel,
+		int *split,
+		bool *merge,
+		int *pipe_cnt)
+{
+	struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
+	unsigned int dc_pipe_idx = 0;
+	bool found_supported_config = false;
+	struct pipe_ctx *pipe = NULL;
+	uint32_t non_subvp_pipes = 0;
+	bool drr_pipe_found = false;
+	uint32_t drr_pipe_index = 0;
+	uint32_t i = 0;
+
+	/*
+	 * DML favors voltage over p-state, but we're more interested in
+	 * supporting p-state over voltage. We can't support p-state in
+	 * prefetch mode > 0 so try capping the prefetch mode to start.
+	 */
+	context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
+			dm_prefetch_support_uclk_fclk_and_stutter;
+	*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
+	/* This may adjust vlevel and maxMpcComb */
+	if (*vlevel < context->bw_ctx.dml.soc.num_states)
+		*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
+
+	/* Conditions for setting up phantom pipes for SubVP:
+	 * 1. Not force disable SubVP
+	 * 2. Full update (i.e. !fast_validate)
+	 * 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?)
+	 * 4. Display configuration passes validation
+	 * 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc->debug.force_subvp_mclk_switch)
+	 */
+	if (!dc->debug.force_disable_subvp &&
+			(*vlevel == context->bw_ctx.dml.soc.num_states ||
+			vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported ||
+			dc->debug.force_subvp_mclk_switch)) {
+
+		while (!found_supported_config && dcn32_enough_pipes_for_subvp(dc, context) &&
+				dcn32_assign_subvp_pipe(dc, context, &dc_pipe_idx)) {
+
+			dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx);
+
+			*pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
+			*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
+
+			if (*vlevel < context->bw_ctx.dml.soc.num_states &&
+					vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported
+					&& subvp_validate_static_schedulability(dc, context, *vlevel)) {
+				found_supported_config = true;
+			} else if (*vlevel < context->bw_ctx.dml.soc.num_states &&
+					vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
+				/* Case where 1 SubVP is added, and DML reports MCLK unsupported. This handles
+				 * the case for SubVP + DRR, where the DRR display does not support MCLK switch
+				 * at it's native refresh rate / timing.
+				 */
+				for (i = 0; i < dc->res_pool->pipe_count; i++) {
+					pipe = &context->res_ctx.pipe_ctx[i];
+					if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
+							pipe->stream->mall_stream_config.type == SUBVP_NONE) {
+						non_subvp_pipes++;
+						// Use ignore_msa_timing_param flag to identify as DRR
+						if (pipe->stream->ignore_msa_timing_param) {
+							drr_pipe_found = true;
+							drr_pipe_index = i;
+						}
+					}
+				}
+				// If there is only 1 remaining non SubVP pipe that is DRR, check static
+				// schedulability for SubVP + DRR.
+				if (non_subvp_pipes == 1 && drr_pipe_found) {
+					found_supported_config = subvp_drr_schedulable(dc,
+							context, &context->res_ctx.pipe_ctx[drr_pipe_index]);
+				}
+			}
+		}
+
+		// If SubVP pipe config is unsupported (or cannot be used for UCLK switching)
+		// remove phantom pipes and repopulate dml pipes
+		if (!found_supported_config) {
+			dc->res_pool->funcs->remove_phantom_pipes(dc, context);
+			*pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
+		} else {
+			// only call dcn20_validate_apply_pipe_split_flags if we found a supported config
+			memset(split, 0, MAX_PIPES * sizeof(int));
+			memset(merge, 0, MAX_PIPES * sizeof(bool));
+			*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
+
+			// If found a supported SubVP config, phantom pipes were added to the context.
+			// Program timing for the phantom pipes.
+			dc->hwss.apply_ctx_to_hw(dc, context);
+		}
+	}
+}
+
+static bool dcn32_internal_validate_bw(
+		struct dc *dc,
+		struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int *pipe_cnt_out,
+		int *vlevel_out,
+		bool fast_validate)
+{
+	bool out = false;
+	bool repopulate_pipes = false;
+	int split[MAX_PIPES] = { 0 };
+	bool merge[MAX_PIPES] = { false };
+	bool newly_split[MAX_PIPES] = { false };
+	int pipe_cnt, i, pipe_idx, vlevel;
+	struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
+
+	ASSERT(pipes);
+	if (!pipes)
+		return false;
+
+	// For each full update, remove all existing phantom pipes first
+	dc->res_pool->funcs->remove_phantom_pipes(dc, context);
+
+	dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
+
+	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
+
+	if (!pipe_cnt) {
+		out = true;
+		goto validate_out;
+	}
+
+	dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
+
+	if (!fast_validate) {
+		dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt);
+	}
+
+	if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
+			vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
+		/*
+		 * If mode is unsupported or there's still no p-state support then
+		 * fall back to favoring voltage.
+		 *
+		 * We don't actually support prefetch mode 2, so require that we
+		 * at least support prefetch mode 1.
+		 */
+		context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
+				dm_prefetch_support_stutter;
+
+		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
+		if (vlevel < context->bw_ctx.dml.soc.num_states) {
+			memset(split, 0, MAX_PIPES * sizeof(int));
+			memset(merge, 0, MAX_PIPES * sizeof(bool));
+			vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
+		}
+	}
+
+	dml_log_mode_support_params(&context->bw_ctx.dml);
+
+	if (vlevel == context->bw_ctx.dml.soc.num_states)
+		goto validate_fail;
+
+	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
+
+		if (!pipe->stream)
+			continue;
+
+		/* We only support full screen mpo with ODM */
+		if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
+				&& pipe->plane_state && mpo_pipe
+				&& memcmp(&mpo_pipe->plane_res.scl_data.recout,
+						&pipe->plane_res.scl_data.recout,
+						sizeof(struct rect)) != 0) {
+			ASSERT(mpo_pipe->plane_state != pipe->plane_state);
+			goto validate_fail;
+		}
+		pipe_idx++;
+	}
+
+	/* merge pipes if necessary */
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+		/*skip pipes that don't need merging*/
+		if (!merge[i])
+			continue;
+
+		/* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
+		if (pipe->prev_odm_pipe) {
+			/*split off odm pipe*/
+			pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
+			if (pipe->next_odm_pipe)
+				pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
+
+			pipe->bottom_pipe = NULL;
+			pipe->next_odm_pipe = NULL;
+			pipe->plane_state = NULL;
+			pipe->stream = NULL;
+			pipe->top_pipe = NULL;
+			pipe->prev_odm_pipe = NULL;
+			if (pipe->stream_res.dsc)
+				dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
+			memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
+			memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
+			repopulate_pipes = true;
+		} else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
+			struct pipe_ctx *top_pipe = pipe->top_pipe;
+			struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
+
+			top_pipe->bottom_pipe = bottom_pipe;
+			if (bottom_pipe)
+				bottom_pipe->top_pipe = top_pipe;
+
+			pipe->top_pipe = NULL;
+			pipe->bottom_pipe = NULL;
+			pipe->plane_state = NULL;
+			pipe->stream = NULL;
+			memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
+			memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
+			repopulate_pipes = true;
+		} else
+			ASSERT(0); /* Should never try to merge master pipe */
+
+	}
+
+	for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+		struct pipe_ctx *hsplit_pipe = NULL;
+		bool odm;
+		int old_index = -1;
+
+		if (!pipe->stream || newly_split[i])
+			continue;
+
+		pipe_idx++;
+		odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
+
+		if (!pipe->plane_state && !odm)
+			continue;
+
+		if (split[i]) {
+			if (odm) {
+				if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
+					old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
+				else if (old_pipe->next_odm_pipe)
+					old_index = old_pipe->next_odm_pipe->pipe_idx;
+			} else {
+				if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
+						old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
+					old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
+				else if (old_pipe->bottom_pipe &&
+						old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
+					old_index = old_pipe->bottom_pipe->pipe_idx;
+			}
+			hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index);
+			ASSERT(hsplit_pipe);
+			if (!hsplit_pipe)
+				goto validate_fail;
+
+			if (!dcn32_split_stream_for_mpc_or_odm(
+					dc, &context->res_ctx,
+					pipe, hsplit_pipe, odm))
+				goto validate_fail;
+
+			newly_split[hsplit_pipe->pipe_idx] = true;
+			repopulate_pipes = true;
+		}
+		if (split[i] == 4) {
+			struct pipe_ctx *pipe_4to1;
+
+			if (odm && old_pipe->next_odm_pipe)
+				old_index = old_pipe->next_odm_pipe->pipe_idx;
+			else if (!odm && old_pipe->bottom_pipe &&
+						old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
+				old_index = old_pipe->bottom_pipe->pipe_idx;
+			else
+				old_index = -1;
+			pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
+			ASSERT(pipe_4to1);
+			if (!pipe_4to1)
+				goto validate_fail;
+			if (!dcn32_split_stream_for_mpc_or_odm(
+					dc, &context->res_ctx,
+					pipe, pipe_4to1, odm))
+				goto validate_fail;
+			newly_split[pipe_4to1->pipe_idx] = true;
+
+			if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
+					&& old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
+				old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
+			else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
+					old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
+					old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
+				old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
+			else
+				old_index = -1;
+			pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
+			ASSERT(pipe_4to1);
+			if (!pipe_4to1)
+				goto validate_fail;
+			if (!dcn32_split_stream_for_mpc_or_odm(
+					dc, &context->res_ctx,
+					hsplit_pipe, pipe_4to1, odm))
+				goto validate_fail;
+			newly_split[pipe_4to1->pipe_idx] = true;
+		}
+		if (odm)
+			dcn20_build_mapped_resource(dc, context, pipe->stream);
+	}
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+		if (pipe->plane_state) {
+			if (!resource_build_scaling_params(pipe))
+				goto validate_fail;
+		}
+	}
+
+	/* Actual dsc count per stream dsc validation*/
+	if (!dcn20_validate_dsc(dc, context)) {
+		vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
+		goto validate_fail;
+	}
+
+	if (repopulate_pipes)
+		pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
+	*vlevel_out = vlevel;
+	*pipe_cnt_out = pipe_cnt;
+
+	out = true;
+	goto validate_out;
+
+validate_fail:
+	out = false;
+
+validate_out:
+	return out;
+}
+
+bool dcn32_validate_bandwidth(struct dc *dc,
+		struct dc_state *context,
+		bool fast_validate)
+{
+	bool out = false;
+
+	BW_VAL_TRACE_SETUP();
+
+	int vlevel = 0;
+	int pipe_cnt = 0;
+	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
+	DC_LOGGER_INIT(dc->ctx->logger);
+
+	BW_VAL_TRACE_COUNT();
+
+    DC_FP_START();
+	out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
+    DC_FP_END();
+
+	if (pipe_cnt == 0)
+		goto validate_out;
+
+	if (!out)
+		goto validate_fail;
+
+	BW_VAL_TRACE_END_VOLTAGE_LEVEL();
+
+	if (fast_validate) {
+		BW_VAL_TRACE_SKIP(fast);
+		goto validate_out;
+	}
+
+	dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
+
+	BW_VAL_TRACE_END_WATERMARKS();
+
+	goto validate_out;
+
+validate_fail:
+	DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
+		dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
+
+	BW_VAL_TRACE_SKIP(fail);
+	out = false;
+
+validate_out:
+	kfree(pipes);
+
+	BW_VAL_TRACE_FINISH();
+
+	return out;
+}
+
+
+static bool is_dual_plane(enum surface_pixel_format format)
+{
+	return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
+}
+
+int dcn32_populate_dml_pipes_from_context(
+	struct dc *dc, struct dc_state *context,
+	display_e2e_pipe_params_st *pipes,
+	bool fast_validate)
+{
+	int i, pipe_cnt;
+	struct resource_context *res_ctx = &context->res_ctx;
+	struct pipe_ctx *pipe;
+
+	dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
+
+	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
+		struct dc_crtc_timing *timing;
+
+		if (!res_ctx->pipe_ctx[i].stream)
+			continue;
+		pipe = &res_ctx->pipe_ctx[i];
+		timing = &pipe->stream->timing;
+
+		pipes[pipe_cnt].pipe.src.gpuvm = true;
+		pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
+		pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
+		pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
+		pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet
+		pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
+		pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19;
+
+		switch (pipe->stream->mall_stream_config.type) {
+		case SUBVP_MAIN:
+			pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport;
+			break;
+		case SUBVP_PHANTOM:
+			pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe;
+			pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_enable;
+			break;
+		case SUBVP_NONE:
+			pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable;
+			pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable;
+			break;
+		default:
+			break;
+		}
+
+		pipes[pipe_cnt].dout.dsc_input_bpc = 0;
+		if (pipes[pipe_cnt].dout.dsc_enable) {
+			switch (timing->display_color_depth) {
+			case COLOR_DEPTH_888:
+				pipes[pipe_cnt].dout.dsc_input_bpc = 8;
+				break;
+			case COLOR_DEPTH_101010:
+				pipes[pipe_cnt].dout.dsc_input_bpc = 10;
+				break;
+			case COLOR_DEPTH_121212:
+				pipes[pipe_cnt].dout.dsc_input_bpc = 12;
+				break;
+			default:
+				ASSERT(0);
+				break;
+			}
+		}
+		pipe_cnt++;
+	}
+	context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE;
+
+	if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
+		if (!is_dual_plane(pipe->plane_state->format)) {
+			context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
+			pipes[0].pipe.src.unbounded_req_mode = true;
+		}
+	}
+
+	return pipe_cnt;
+}
+
+void dcn32_calculate_wm_and_dlg_fp(
+		struct dc *dc, struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int pipe_cnt,
+		int vlevel)
+{
+	int i, pipe_idx, vlevel_temp = 0;
+
+	double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
+	double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
+	unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
+	bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=
+			dm_dram_clock_change_unsupported;
+
+	/* Set B:
+	 * For Set B calculations use clocks from clock_limits[2] when available i.e. when SMU is present,
+	 * otherwise use arbitrary low value from spreadsheet for DCFCLK as lower is safer for watermark
+	 * calculations to cover bootup clocks.
+	 * DCFCLK: soc.clock_limits[2] when available
+	 * UCLK: soc.clock_limits[2] when available
+	 */
+	if (dcn3_2_soc.num_states > 2) {
+		vlevel_temp = 2;
+		dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz;
+	} else
+		dcfclk = 615; //DCFCLK Vmin_lv
+
+	pipes[0].clks_cfg.voltage = vlevel_temp;
+	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
+	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
+
+	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
+		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
+		context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us;
+		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
+		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
+	}
+	context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+
+	/* Set D:
+	 * All clocks min.
+	 * DCFCLK: Min, as reported by PM FW when available
+	 * UCLK  : Min, as reported by PM FW when available
+	 * sr_enter_exit/sr_exit should be lower than used for DRAM (TBD after bringup or later, use as decided in Clk Mgr)
+	 */
+
+	if (dcn3_2_soc.num_states > 2) {
+		vlevel_temp = 0;
+		dcfclk = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
+	} else
+		dcfclk = 615; //DCFCLK Vmin_lv
+
+	pipes[0].clks_cfg.voltage = vlevel_temp;
+	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
+	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
+
+	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
+		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
+		context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us;
+		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
+		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
+	}
+	context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+
+	/* Set C, for Dummy P-State:
+	 * All clocks min.
+	 * DCFCLK: Min, as reported by PM FW, when available
+	 * UCLK  : Min,  as reported by PM FW, when available
+	 * pstate latency as per UCLK state dummy pstate latency
+	 */
+
+	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
+		unsigned int min_dram_speed_mts_margin = 160;
+
+		if ((!pstate_en))
+			min_dram_speed_mts = dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz * 16;
+
+		/* find largest table entry that is lower than dram speed, but lower than DPM0 still uses DPM0 */
+		for (i = 3; i > 0; i--)
+			if (min_dram_speed_mts + min_dram_speed_mts_margin > dc->clk_mgr->bw_params->dummy_pstate_table[i].dram_speed_mts)
+				break;
+
+		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[i].dummy_pstate_latency_us;
+		context->bw_ctx.dml.soc.dummy_pstate_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[i].dummy_pstate_latency_us;
+		context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us;
+		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
+		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
+	}
+	context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+
+	if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) {
+		/* The only difference between A and C is p-state latency, if p-state is not supported
+		 * with full p-state latency we want to calculate DLG based on dummy p-state latency,
+		 * Set A p-state watermark set to 0 on DCN32, when p-state unsupported, for now keep as DCN32.
+		 */
+		context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;
+		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;
+	} else {
+		/* Set A:
+		 * All clocks min.
+		 * DCFCLK: Min, as reported by PM FW, when available
+		 * UCLK: Min, as reported by PM FW, when available
+		 */
+		dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
+		context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+		context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+		context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+		context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+		context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+		context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	}
+
+	pipes[0].clks_cfg.voltage = vlevel;
+	pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_validation;
+	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
+
+	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+		if (!context->res_ctx.pipe_ctx[i].stream)
+			continue;
+
+		pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
+		pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
+
+		if (dc->config.forced_clocks) {
+			pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
+			pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
+		}
+		if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
+			pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
+		if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
+			pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
+
+		pipe_idx++;
+	}
+
+	context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod;
+
+	dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
+
+	if (!pstate_en)
+		/* Restore full p-state latency */
+		context->bw_ctx.dml.soc.dram_clock_change_latency_us =
+				dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
+}
+
+static struct dc_cap_funcs cap_funcs = {
+	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
+};
+
+
+static void dcn32_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
+		unsigned int *optimal_dcfclk,
+		unsigned int *optimal_fclk)
+{
+	double bw_from_dram, bw_from_dram1, bw_from_dram2;
+
+	bw_from_dram1 = uclk_mts * dcn3_2_soc.num_chans *
+		dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_dram_bw_use_normal_percent / 100);
+	bw_from_dram2 = uclk_mts * dcn3_2_soc.num_chans *
+		dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100);
+
+	bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
+
+	if (optimal_fclk)
+		*optimal_fclk = bw_from_dram /
+		(dcn3_2_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));
+
+	if (optimal_dcfclk)
+		*optimal_dcfclk =  bw_from_dram /
+		(dcn3_2_soc.return_bus_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));
+}
+
+void dcn32_calculate_wm_and_dlg(
+		struct dc *dc, struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int pipe_cnt,
+		int vlevel)
+{
+    DC_FP_START();
+    dcn32_calculate_wm_and_dlg_fp(
+		dc, context,
+		pipes,
+		pipe_cnt,
+		vlevel);
+    DC_FP_END();
+}
+
+static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
+{
+	int i;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		if (!context->res_ctx.pipe_ctx[i].stream)
+			continue;
+		if (is_dp_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))
+			return true;
+	}
+	return false;
+}
+
+void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes,
+		int pipe_cnt, int vlevel)
+{
+	int i, pipe_idx;
+	bool usr_retraining_support = false;
+
+	/* Writeback MCIF_WB arbitration parameters */
+	dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
+
+	context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
+	context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
+	context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
+	context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
+	context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
+	context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
+	context->bw_ctx.bw.dcn.clk.p_state_change_support =
+			context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
+					!= dm_dram_clock_change_unsupported;
+
+	/*
+	 * TODO: needs FAMS
+	 * Pstate change might not be supported by hardware, but it might be
+	 * possible with firmware driven vertical blank stretching.
+	 */
+	// context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;
+
+	context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
+	context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
+	if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported)
+		context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false;
+	else
+		context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;
+
+	usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
+	ASSERT(usr_retraining_support);
+
+	if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
+		context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
+
+	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+		if (!context->res_ctx.pipe_ctx[i].stream)
+			continue;
+		pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt,
+				pipe_idx);
+		pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
+				pipe_idx);
+		pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt,
+				pipe_idx);
+		pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
+				pipe_idx);
+		if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
+			// Phantom pipe requires that DET_SIZE = 0 and no unbounded requests
+			context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;
+			context->res_ctx.pipe_ctx[i].unbounded_req = false;
+		} else {
+			context->res_ctx.pipe_ctx[i].det_buffer_size_kb =
+					context->bw_ctx.dml.ip.det_buffer_size_kbytes;
+			context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
+		}
+		if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
+			context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
+		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
+		context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
+		pipe_idx++;
+	}
+	/*save a original dppclock copy*/
+	context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
+	context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
+	context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz
+			* 1000;
+	context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz
+			* 1000;
+
+	context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes
+			- context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx;
+
+	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+
+		if (!context->res_ctx.pipe_ctx[i].stream)
+			continue;
+
+		/* cstate disabled on 201 */
+//		if (dc->ctx->dce_version == DCN_VERSION_2_01)
+//			cstate_en = false;
+
+
+		context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml,
+				&context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes,
+				pipe_cnt, pipe_idx);
+
+		context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs,
+				&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
+
+		pipe_idx++;
+	}
+}
+
+/* dcn32_update_bw_bounding_box
+ * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from spreadsheet
+ * with actual values as per dGPU SKU:
+ * -with passed few options from dc->config
+ * -with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might need to get it from PM FW)
+ * -with passed latency values (passed in ns units) in dc-> bb override for debugging purposes
+ * -with passed latencies from VBIOS (in 100_ns units) if available for certain dGPU SKU
+ * -with number of DRAM channels from VBIOS (which differ for certain dGPU SKU of the same ASIC)
+ * -clocks levels with passed clk_table entries from Clk Mgr as reported by PM FW for different
+ *  clocks (which might differ for certain dGPU SKU of the same ASIC)
+ */
+static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
+{
+	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+
+		/* Overrides from dc->config options */
+		dcn3_2_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
+
+		/* Override from passed dc->bb_overrides if available*/
+		if ((int)(dcn3_2_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
+				&& dc->bb_overrides.sr_exit_time_ns) {
+			dcn3_2_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
+		}
+
+		if ((int)(dcn3_2_soc.sr_enter_plus_exit_time_us * 1000)
+				!= dc->bb_overrides.sr_enter_plus_exit_time_ns
+				&& dc->bb_overrides.sr_enter_plus_exit_time_ns) {
+			dcn3_2_soc.sr_enter_plus_exit_time_us =
+				dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
+		}
+
+		if ((int)(dcn3_2_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
+			&& dc->bb_overrides.urgent_latency_ns) {
+			dcn3_2_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
+		}
+
+		if ((int)(dcn3_2_soc.dram_clock_change_latency_us * 1000)
+				!= dc->bb_overrides.dram_clock_change_latency_ns
+				&& dc->bb_overrides.dram_clock_change_latency_ns) {
+			dcn3_2_soc.dram_clock_change_latency_us =
+				dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
+		}
+
+		if ((int)(dcn3_2_soc.dummy_pstate_latency_us * 1000)
+				!= dc->bb_overrides.dummy_clock_change_latency_ns
+				&& dc->bb_overrides.dummy_clock_change_latency_ns) {
+			dcn3_2_soc.dummy_pstate_latency_us =
+				dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
+		}
+
+		/* Override from VBIOS if VBIOS bb_info available */
+		if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
+			struct bp_soc_bb_info bb_info = {0};
+
+			if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
+				if (bb_info.dram_clock_change_latency_100ns > 0)
+					dcn3_2_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
+
+			if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
+				dcn3_2_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
+
+			if (bb_info.dram_sr_exit_latency_100ns > 0)
+				dcn3_2_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
+			}
+		}
+
+		/* Override from VBIOS for num_chan */
+		if (dc->ctx->dc_bios->vram_info.num_chans)
+			dcn3_2_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
+
+		if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
+			dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
+
+	}
+
+	/* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
+	dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
+	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
+
+	/* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */
+	if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) {
+		unsigned int i = 0, j = 0, num_states = 0;
+
+		unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
+		unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
+		unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
+		unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
+
+		unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564};
+		unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0;
+		unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
+
+		for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
+			if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
+				max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
+			if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
+				max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
+			if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
+				max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
+			if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
+				max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
+		}
+		if (!max_dcfclk_mhz)
+			max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
+		if (!max_dispclk_mhz)
+			max_dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz;
+		if (!max_dppclk_mhz)
+			max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz;
+		if (!max_phyclk_mhz)
+			max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz;
+
+		if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
+			// If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
+			dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
+			num_dcfclk_sta_targets++;
+		} else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
+			// If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
+			for (i = 0; i < num_dcfclk_sta_targets; i++) {
+				if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
+					dcfclk_sta_targets[i] = max_dcfclk_mhz;
+					break;
+				}
+			}
+			// Update size of array since we "removed" duplicates
+			num_dcfclk_sta_targets = i + 1;
+		}
+
+		num_uclk_states = bw_params->clk_table.num_entries;
+
+		// Calculate optimal dcfclk for each uclk
+		for (i = 0; i < num_uclk_states; i++) {
+			dcn32_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
+					&optimal_dcfclk_for_uclk[i], NULL);
+			if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
+				optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
+			}
+		}
+
+		// Calculate optimal uclk for each dcfclk sta target
+		for (i = 0; i < num_dcfclk_sta_targets; i++) {
+			for (j = 0; j < num_uclk_states; j++) {
+				if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
+					optimal_uclk_for_dcfclk_sta_targets[i] =
+							bw_params->clk_table.entries[j].memclk_mhz * 16;
+					break;
+				}
+			}
+		}
+
+		i = 0;
+		j = 0;
+		// create the final dcfclk and uclk table
+		while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
+			if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
+				dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
+				dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
+			} else {
+				if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
+					dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
+					dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
+				} else {
+					j = num_uclk_states;
+				}
+			}
+		}
+
+		while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
+			dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
+			dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
+		}
+
+		while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
+				optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
+			dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
+			dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
+		}
+
+		dcn3_2_soc.num_states = num_states;
+		for (i = 0; i < dcn3_2_soc.num_states; i++) {
+			dcn3_2_soc.clock_limits[i].state = i;
+			dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
+			dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
+			dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
+
+			/* Fill all states with max values of all these clocks */
+			dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
+			dcn3_2_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
+			dcn3_2_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
+			dcn3_2_soc.clock_limits[i].dscclk_mhz  = max_dispclk_mhz / 3;
+
+			/* Populate from bw_params for DTBCLK, SOCCLK */
+			if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0)
+				dcn3_2_soc.clock_limits[i].dtbclk_mhz  = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz;
+			else
+				dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
+
+			if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
+				dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz;
+			else
+				dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
+
+			/* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */
+			/* PHYCLK_D18, PHYCLK_D32 */
+			dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;
+			dcn3_2_soc.clock_limits[i].phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
+		}
+
+		/* Re-init DML with updated bb */
+		dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
+		if (dc->current_state)
+			dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
+	}
+}
+
+static struct resource_funcs dcn32_res_pool_funcs = {
+	.destroy = dcn32_destroy_resource_pool,
+	.link_enc_create = dcn32_link_encoder_create,
+	.link_enc_create_minimal = NULL,
+	.panel_cntl_create = dcn32_panel_cntl_create,
+	.validate_bandwidth = dcn32_validate_bandwidth,
+	.calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,
+	.populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
+	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
+	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
+	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
+	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
+	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
+	.set_mcif_arb_params = dcn30_set_mcif_arb_params,
+	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
+	.acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
+	.release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
+	.update_bw_bounding_box = dcn32_update_bw_bounding_box,
+	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
+	.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
+	.add_phantom_pipes = dcn32_add_phantom_pipes,
+	.remove_phantom_pipes = dcn32_remove_phantom_pipes,
+};
+
+
+static bool dcn32_resource_construct(
+	uint8_t num_virtual_links,
+	struct dc *dc,
+	struct dcn32_resource_pool *pool)
+{
+	int i, j;
+	struct dc_context *ctx = dc->ctx;
+	struct irq_service_init_data init_data;
+	struct ddc_service_init_data ddc_init_data = {0};
+	uint32_t pipe_fuses = 0;
+	uint32_t num_pipes  = 4;
+
+    DC_FP_START();
+
+	ctx->dc_bios->regs = &bios_regs;
+
+	pool->base.res_cap = &res_cap_dcn32;
+	/* max number of pipes for ASIC before checking for pipe fuses */
+	num_pipes  = pool->base.res_cap->num_timing_generator;
+	pipe_fuses = REG_READ(CC_DC_PIPE_DIS);
+
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
+		if (pipe_fuses & 1 << i)
+			num_pipes--;
+
+	if (pipe_fuses & 1)
+		ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
+
+	if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
+		ASSERT(0); //Entire DCN is harvested!
+
+	/* within dml lib, initial value is hard coded, if ASIC pipe is fused, the
+	 * value will be changed, update max_num_dpp and max_num_otg for dml.
+	 */
+	dcn3_2_ip.max_num_dpp = num_pipes;
+	dcn3_2_ip.max_num_otg = num_pipes;
+
+	pool->base.funcs = &dcn32_res_pool_funcs;
+
+	/*************************************************
+	 *  Resource + asic cap harcoding                *
+	 *************************************************/
+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+	pool->base.timing_generator_count = num_pipes;
+	pool->base.pipe_count = num_pipes;
+	pool->base.mpcc_count = num_pipes;
+	dc->caps.max_downscale_ratio = 600;
+	dc->caps.i2c_speed_in_khz = 100;
+	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/
+	dc->caps.max_cursor_size = 256;
+	dc->caps.min_horizontal_blanking_period = 80;
+	dc->caps.dmdata_alloc_size = 2048;
+	dc->caps.mall_size_per_mem_channel = 0;
+	dc->caps.mall_size_total = 0;
+	dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
+
+	dc->caps.cache_line_size = 64;
+	dc->caps.cache_num_ways = 16;
+	dc->caps.max_cab_allocation_bytes = 67108864; // 64MB = 1024 * 1024 * 64
+	dc->caps.subvp_fw_processing_delay_us = 15;
+	dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
+	dc->caps.subvp_pstate_allow_width_us = 20;
+	dc->caps.subvp_vertical_int_margin_us = 30;
+
+	dc->caps.max_slave_planes = 2;
+	dc->caps.max_slave_yuv_planes = 2;
+	dc->caps.max_slave_rgb_planes = 2;
+	dc->caps.post_blend_color_processing = true;
+	dc->caps.force_dp_tps4_for_cp2520 = true;
+	dc->caps.dp_hpo = true;
+	dc->caps.edp_dsc_support = true;
+	dc->caps.extended_aux_timeout_support = true;
+	dc->caps.dmcub_support = true;
+
+	/* Color pipeline capabilities */
+	dc->caps.color.dpp.dcn_arch = 1;
+	dc->caps.color.dpp.input_lut_shared = 0;
+	dc->caps.color.dpp.icsc = 1;
+	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
+	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
+	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
+	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
+	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
+	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
+	dc->caps.color.dpp.post_csc = 1;
+	dc->caps.color.dpp.gamma_corr = 1;
+	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
+
+	dc->caps.color.dpp.hw_3d_lut = 1;
+	dc->caps.color.dpp.ogam_ram = 0;  //Blnd Gam also removed
+	// no OGAM ROM on DCN2 and later ASICs
+	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
+	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
+	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
+	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
+	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
+	dc->caps.color.dpp.ocsc = 0;
+
+	dc->caps.color.mpc.gamut_remap = 1;
+	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
+	dc->caps.color.mpc.ogam_ram = 1;
+	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
+	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
+	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
+	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
+	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
+	dc->caps.color.mpc.ocsc = 1;
+
+	/* Use pipe context based otg sync logic */
+	dc->config.use_pipe_ctx_sync_logic = true;
+
+	/* read VBIOS LTTPR caps */
+	{
+		if (ctx->dc_bios->funcs->get_lttpr_caps) {
+			enum bp_result bp_query_result;
+			uint8_t is_vbios_lttpr_enable = 0;
+
+			bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
+			dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
+		}
+
+		/* interop bit is implicit */
+		{
+			dc->caps.vbios_lttpr_aware = true;
+		}
+	}
+
+	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
+		dc->debug = debug_defaults_drv;
+	else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
+		dc->debug = debug_defaults_diags;
+	} else
+		dc->debug = debug_defaults_diags;
+	// Init the vm_helper
+	if (dc->vm_helper)
+		vm_helper_init(dc->vm_helper, 16);
+
+	/*************************************************
+	 *  Create resources                             *
+	 *************************************************/
+
+	/* Clock Sources for Pixel Clock*/
+	pool->base.clock_sources[DCN32_CLK_SRC_PLL0] =
+			dcn32_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL0,
+				&clk_src_regs[0], false);
+	pool->base.clock_sources[DCN32_CLK_SRC_PLL1] =
+			dcn32_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL1,
+				&clk_src_regs[1], false);
+	pool->base.clock_sources[DCN32_CLK_SRC_PLL2] =
+			dcn32_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL2,
+				&clk_src_regs[2], false);
+	pool->base.clock_sources[DCN32_CLK_SRC_PLL3] =
+			dcn32_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL3,
+				&clk_src_regs[3], false);
+	pool->base.clock_sources[DCN32_CLK_SRC_PLL4] =
+			dcn32_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL4,
+				&clk_src_regs[4], false);
+
+	pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL;
+
+	/* todo: not reuse phy_pll registers */
+	pool->base.dp_clock_source =
+			dcn32_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_ID_DP_DTO,
+				&clk_src_regs[0], true);
+
+	for (i = 0; i < pool->base.clk_src_count; i++) {
+		if (pool->base.clock_sources[i] == NULL) {
+			dm_error("DC: failed to create clock sources!\n");
+			BREAK_TO_DEBUGGER();
+			goto create_fail;
+		}
+	}
+
+	/* DCCG */
+	pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
+	if (pool->base.dccg == NULL) {
+		dm_error("DC: failed to create dccg!\n");
+		BREAK_TO_DEBUGGER();
+		goto create_fail;
+	}
+
+	/* DML */
+	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
+		dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
+
+	/* IRQ Service */
+	init_data.ctx = dc->ctx;
+	pool->base.irqs = dal_irq_service_dcn32_create(&init_data);
+	if (!pool->base.irqs)
+		goto create_fail;
+
+	/* HUBBUB */
+	pool->base.hubbub = dcn32_hubbub_create(ctx);
+	if (pool->base.hubbub == NULL) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create hubbub!\n");
+		goto create_fail;
+	}
+
+	/* HUBPs, DPPs, OPPs, TGs, ABMs */
+	for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+
+		/* if pipe is disabled, skip instance of HW pipe,
+		 * i.e, skip ASIC register instance
+		 */
+		if (pipe_fuses & 1 << i)
+			continue;
+
+		/* HUBPs */
+		pool->base.hubps[j] = dcn32_hubp_create(ctx, i);
+		if (pool->base.hubps[j] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC: failed to create hubps!\n");
+			goto create_fail;
+		}
+
+		/* DPPs */
+		pool->base.dpps[j] = dcn32_dpp_create(ctx, i);
+		if (pool->base.dpps[j] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC: failed to create dpps!\n");
+			goto create_fail;
+		}
+
+		/* OPPs */
+		pool->base.opps[j] = dcn32_opp_create(ctx, i);
+		if (pool->base.opps[j] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC: failed to create output pixel processor!\n");
+			goto create_fail;
+		}
+
+		/* TGs */
+		pool->base.timing_generators[j] = dcn32_timing_generator_create(
+				ctx, i);
+		if (pool->base.timing_generators[j] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create tg!\n");
+			goto create_fail;
+		}
+
+		/* ABMs */
+		pool->base.multiple_abms[j] = dmub_abm_create(ctx,
+				&abm_regs[i],
+				&abm_shift,
+				&abm_mask);
+		if (pool->base.multiple_abms[j] == NULL) {
+			dm_error("DC: failed to create abm for pipe %d!\n", i);
+			BREAK_TO_DEBUGGER();
+			goto create_fail;
+		}
+
+		/* index for resource pool arrays for next valid pipe */
+		j++;
+	}
+
+	/* PSR */
+	pool->base.psr = dmub_psr_create(ctx);
+	if (pool->base.psr == NULL) {
+		dm_error("DC: failed to create psr obj!\n");
+		BREAK_TO_DEBUGGER();
+		goto create_fail;
+	}
+
+	/* MPCCs */
+	pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
+	if (pool->base.mpc == NULL) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create mpc!\n");
+		goto create_fail;
+	}
+
+	/* DSCs */
+	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+		pool->base.dscs[i] = dcn32_dsc_create(ctx, i);
+		if (pool->base.dscs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create display stream compressor %d!\n", i);
+			goto create_fail;
+		}
+	}
+
+	/* DWB */
+	if (!dcn32_dwbc_create(ctx, &pool->base)) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create dwbc!\n");
+		goto create_fail;
+	}
+
+	/* MMHUBBUB */
+	if (!dcn32_mmhubbub_create(ctx, &pool->base)) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create mcif_wb!\n");
+		goto create_fail;
+	}
+
+	/* AUX and I2C */
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+		pool->base.engines[i] = dcn32_aux_engine_create(ctx, i);
+		if (pool->base.engines[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create aux engine!!\n");
+			goto create_fail;
+		}
+		pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i);
+		if (pool->base.hw_i2cs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create hw i2c!!\n");
+			goto create_fail;
+		}
+		pool->base.sw_i2cs[i] = NULL;
+	}
+
+	/* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
+	if (!resource_construct(num_virtual_links, dc, &pool->base,
+			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
+			&res_create_funcs : &res_create_maximus_funcs)))
+			goto create_fail;
+
+	/* HW Sequencer init functions and Plane caps */
+	dcn32_hw_sequencer_init_functions(dc);
+
+	dc->caps.max_planes =  pool->base.pipe_count;
+
+	for (i = 0; i < dc->caps.max_planes; ++i)
+		dc->caps.planes[i] = plane_cap;
+
+	dc->cap_funcs = cap_funcs;
+
+	if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
+		ddc_init_data.ctx = dc->ctx;
+		ddc_init_data.link = NULL;
+		ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
+		ddc_init_data.id.enum_id = 0;
+		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
+		pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
+	} else {
+		pool->base.oem_device = NULL;
+	}
+
+    DC_FP_END();
+
+	return true;
+
+create_fail:
+
+    DC_FP_END();
+
+	dcn32_resource_destruct(pool);
+
+	return false;
+}
+
+struct resource_pool *dcn32_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc)
+{
+	struct dcn32_resource_pool *pool =
+		kzalloc(sizeof(struct dcn32_resource_pool), GFP_KERNEL);
+
+	if (!pool)
+		return NULL;
+
+	if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool))
+		return &pool->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(pool);
+	return NULL;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
new file mode 100644
index 0000000000000..10b58f1c724a1
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN32_RESOURCE_H_
+#define _DCN32_RESOURCE_H_
+
+#include "core_types.h"
+
+#define TO_DCN32_RES_POOL(pool)\
+	container_of(pool, struct dcn32_resource_pool, base)
+
+struct dcn32_resource_pool {
+	struct resource_pool base;
+};
+
+struct resource_pool *dcn32_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+
+void dcn32_calculate_dlg_params(
+		struct dc *dc, struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int pipe_cnt,
+		int vlevel);
+
+struct panel_cntl *dcn32_panel_cntl_create(
+		const struct panel_cntl_init_data *init_data);
+
+bool dcn32_acquire_post_bldn_3dlut(
+		struct resource_context *res_ctx,
+		const struct resource_pool *pool,
+		int mpcc_id,
+		struct dc_3dlut **lut,
+		struct dc_transfer_func **shaper);
+
+bool dcn32_release_post_bldn_3dlut(
+		struct resource_context *res_ctx,
+		const struct resource_pool *pool,
+		struct dc_3dlut **lut,
+		struct dc_transfer_func **shaper);
+
+void dcn32_remove_phantom_pipes(struct dc *dc,
+		struct dc_state *context);
+
+void dcn32_add_phantom_pipes(struct dc *dc,
+		struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		unsigned int pipe_cnt,
+		unsigned int index);
+
+bool dcn32_validate_bandwidth(struct dc *dc,
+		struct dc_state *context,
+		bool fast_validate);
+
+int dcn32_populate_dml_pipes_from_context(
+	struct dc *dc, struct dc_state *context,
+	display_e2e_pipe_params_st *pipes,
+	bool fast_validate);
+
+void dcn32_calculate_wm_and_dlg(
+		struct dc *dc, struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int pipe_cnt,
+		int vlevel);
+
+#endif /* _DCN32_RESOURCE_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/Makefile b/drivers/gpu/drm/amd/display/dc/dcn321/Makefile
new file mode 100644
index 0000000000000..99515cb3ed311
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/Makefile
@@ -0,0 +1,34 @@
+#
+# (c) Copyright 2020 Advanced Micro Devices, Inc. All the rights reserved
+#
+#  All rights reserved.  This notice is intended as a precaution against
+#  inadvertent publication and does not imply publication or any waiver
+#  of confidentiality.  The year included in the foregoing notice is the
+#  year of creation of the work.
+#
+#  Authors: AMD
+#
+# Makefile for dcn321.
+
+DCN321 = dcn321_resource.o
+
+CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o := -mhard-float -msse
+
+ifdef CONFIG_CC_IS_GCC
+ifeq ($(call cc-ifversion, -lt, 0701, y), y)
+IS_OLD_GCC = 1
+endif
+endif
+
+ifdef IS_OLD_GCC
+# Stack alignment mismatch, proceed with caution.
+# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+# (8B stack alignment).
+CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o += -mpreferred-stack-boundary=4
+else
+CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o += -msse2
+endif
+
+AMD_DAL_DCN321 = $(addprefix $(AMDDALPATH)/dc/dcn321/,$(DCN321))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DCN321)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index a8fb4ab8ced1a..6bc477a212b09 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: MIT
 /*
  * Copyright 2019 Advanced Micro Devices, Inc.
  *
@@ -23,7 +24,6 @@
  *
  */
 
-
 #include "dm_services.h"
 #include "dc.h"
 
@@ -98,28 +98,25 @@
 #define MAX_INSTANCE                                        8
 #define MAX_SEGMENT                                         6
 
-
-struct IP_BASE_INSTANCE
-{
-    unsigned int segment[MAX_SEGMENT];
+struct IP_BASE_INSTANCE {
+	unsigned int segment[MAX_SEGMENT];
 };
 
-struct IP_BASE
-{
-    struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
+struct IP_BASE {
+	struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
 };
 
 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
-                                        { { 0, 0, 0, 0, 0, 0 } },
-                                        { { 0, 0, 0, 0, 0, 0 } },
-                                        { { 0, 0, 0, 0, 0, 0 } },
-                                        { { 0, 0, 0, 0, 0, 0 } },
-                                        { { 0, 0, 0, 0, 0, 0 } },
-                                        { { 0, 0, 0, 0, 0, 0 } },
-                                        { { 0, 0, 0, 0, 0, 0 } } } };
+					{ { 0, 0, 0, 0, 0, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } } } };
 
 #define DC_LOGGER_INIT(logger)
-#define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
+#define fixed16_to_double(x) (((double)x) / ((double) (1 << 16)))
 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
 
 #define DCN3_2_DEFAULT_DET_SIZE 256
@@ -1534,9 +1531,8 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool)
 			pool->base.hubps[i] = NULL;
 		}
 
-		if (pool->base.irqs != NULL) {
+		if (pool->base.irqs != NULL)
 			dal_irq_service_destroy(&pool->base.irqs);
-		}
 	}
 
 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.h b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.h
new file mode 100644
index 0000000000000..2732085a0e884
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN321_RESOURCE_H_
+#define _DCN321_RESOURCE_H_
+
+#include "core_types.h"
+
+#define TO_DCN321_RES_POOL(pool)\
+	container_of(pool, struct dcn321_resource_pool, base)
+
+struct dcn321_resource_pool {
+	struct resource_pool base;
+};
+
+struct resource_pool *dcn321_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+
+#endif /* _DCN321_RESOURCE_H_ */
-- 
GitLab


From d3dfceb58de5f897640cdd424f6c2538d9514367 Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Wed, 23 Feb 2022 17:48:45 -0500
Subject: [PATCH 0157/1731] drm/amd/display: Add dependant changes for
 DCN32/321

[Why&How]
This patch adds necessary changes needed in DC files outside DCN32/321
specific tree

v2: squash in updates (Alex)

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/Makefile       |   2 +
 .../drm/amd/display/dc/bios/bios_parser2.c    | 949 ++++++++++++++----
 .../dc/bios/bios_parser_types_internal2.h     |   1 +
 .../display/dc/bios/command_table_helper2.c   |   2 +
 .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c  |   2 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c      |  14 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |  20 +-
 drivers/gpu/drm/amd/display/dc/dc.h           |  19 +
 .../gpu/drm/amd/display/dc/dc_bios_types.h    |   5 +
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h  |   1 +
 drivers/gpu/drm/amd/display/dc/dc_stream.h    |  21 +
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h  |  45 +
 .../drm/amd/display/dc/dce/dce_clock_source.h |  15 +
 .../drm/amd/display/dc/dcn10/dcn10_hubbub.h   |  33 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |   5 -
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |   2 +
 .../display/dc/dcn10/dcn10_stream_encoder.h   |  25 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h |  34 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h |  25 +-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  32 +-
 .../dc/dcn30/dcn30_dio_stream_encoder.c       |  16 +-
 .../dc/dcn30/dcn30_dio_stream_encoder.h       |  35 +
 .../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c  |   8 +-
 .../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h  |  16 +
 .../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c  |  14 +-
 .../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h  | 147 +++
 .../gpu/drm/amd/display/dc/dcn30/dcn30_optc.h |   9 +
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c |  28 +-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h |  14 +-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_optc.c |  22 +-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_optc.h |   6 +-
 .../gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c |  45 +-
 .../dc/dcn32/dcn32_dio_stream_encoder.c       |  36 +-
 .../dc/dcn32/dcn32_dio_stream_encoder.h       |  15 +-
 .../drm/amd/display/dc/dcn32/dcn32_hwseq.c    |   4 +-
 .../gpu/drm/amd/display/dc/dcn32/dcn32_optc.c |  36 +-
 .../drm/amd/display/dc/dcn32/dcn32_resource.c |   2 +-
 .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c  |  59 +-
 .../gpu/drm/amd/display/dc/inc/core_types.h   |  10 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h  |   5 +-
 .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h  |   3 +
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |   7 +
 .../gpu/drm/amd/display/dc/inc/hw/mem_input.h |   2 +
 .../amd/display/dc/inc/hw/stream_encoder.h    |   4 +
 .../amd/display/dc/inc/hw/timing_generator.h  |  10 +-
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |   2 +
 .../amd/display/dc/inc/hw_sequencer_private.h |   5 +
 drivers/gpu/drm/amd/display/dc/inc/resource.h |   7 +
 .../amd/display/include/bios_parser_types.h   |  10 +
 49 files changed, 1521 insertions(+), 308 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index b4eca02364358..4de8e18717115 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -38,6 +38,8 @@ DC_LIBS += dcn303
 DC_LIBS += dcn31
 DC_LIBS += dcn315
 DC_LIBS += dcn316
+DC_LIBS += dcn32
+DC_LIBS += dcn321
 endif
 
 DC_LIBS += dce120
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 23a3b640f0ee9..bbc0a5769e884 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -165,9 +165,21 @@ static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
 	unsigned int count = 0;
 	unsigned int i;
 
-	for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
-		if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0)
-			count++;
+	switch (bp->object_info_tbl.revision.minor) {
+	default:
+	case 4:
+		for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++)
+			if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0)
+				count++;
+
+		break;
+
+	case 5:
+		for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++)
+			if (bp->object_info_tbl.v1_5->display_path[i].encoderobjid != 0)
+				count++;
+
+		break;
 	}
 	return count;
 }
@@ -182,16 +194,34 @@ static struct graphics_object_id bios_parser_get_connector_id(
 	struct object_info_table *tbl = &bp->object_info_tbl;
 	struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4;
 
-	if (v1_4->number_of_path > i) {
-		/* If display_objid is generic object id,  the encoderObj
-		 * /extencoderobjId should be 0
-		 */
-		if (v1_4->display_path[i].encoderobjid != 0 &&
-				v1_4->display_path[i].display_objid != 0)
-			object_id = object_id_from_bios_object_id(
+	struct display_object_info_table_v1_5 *v1_5 = tbl->v1_5;
+
+	switch (bp->object_info_tbl.revision.minor) {
+	default:
+	case 4:
+		if (v1_4->number_of_path > i) {
+			/* If display_objid is generic object id,  the encoderObj
+			 * /extencoderobjId should be 0
+			 */
+			if (v1_4->display_path[i].encoderobjid != 0 &&
+			    v1_4->display_path[i].display_objid != 0)
+				object_id = object_id_from_bios_object_id(
 					v1_4->display_path[i].display_objid);
-	}
+		}
+		break;
 
+	case 5:
+		if (v1_5->number_of_path > i) {
+			/* If display_objid is generic object id,  the encoderObjId
+		 * should be 0
+		 */
+			if (v1_5->display_path[i].encoderobjid != 0 &&
+			    v1_5->display_path[i].display_objid != 0)
+				object_id = object_id_from_bios_object_id(
+					v1_5->display_path[i].display_objid);
+		}
+		break;
+	}
 	return object_id;
 }
 
@@ -201,8 +231,8 @@ static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
 {
 	struct bios_parser *bp = BP_FROM_DCB(dcb);
 	unsigned int i;
-	enum bp_result  bp_result = BP_RESULT_BADINPUT;
-	struct graphics_object_id obj_id = {0};
+	enum bp_result bp_result = BP_RESULT_BADINPUT;
+	struct graphics_object_id obj_id = { 0 };
 	struct object_info_table *tbl = &bp->object_info_tbl;
 
 	if (!src_object_id)
@@ -217,37 +247,84 @@ static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
 		 * If found in for loop, should break.
 		 * DAL2 implementation may be changed too
 		 */
-		for (i = 0; i < tbl->v1_4->number_of_path; i++) {
-			obj_id = object_id_from_bios_object_id(
-			tbl->v1_4->display_path[i].encoderobjid);
-			if (object_id.type == obj_id.type &&
-					object_id.id == obj_id.id &&
-						object_id.enum_id ==
-							obj_id.enum_id) {
-				*src_object_id =
-				object_id_from_bios_object_id(0x1100);
-				/* break; */
+		switch (bp->object_info_tbl.revision.minor) {
+		default:
+		case 4:
+			for (i = 0; i < tbl->v1_4->number_of_path; i++) {
+				obj_id = object_id_from_bios_object_id(
+					tbl->v1_4->display_path[i].encoderobjid);
+				if (object_id.type == obj_id.type &&
+				    object_id.id == obj_id.id &&
+				    object_id.enum_id == obj_id.enum_id) {
+					*src_object_id =
+						object_id_from_bios_object_id(
+							0x1100);
+					/* break; */
+				}
+			}
+			bp_result = BP_RESULT_OK;
+			break;
+
+		case 5:
+			for (i = 0; i < tbl->v1_5->number_of_path; i++) {
+				obj_id = object_id_from_bios_object_id(
+					tbl->v1_5->display_path[i].encoderobjid);
+				if (object_id.type == obj_id.type &&
+				    object_id.id == obj_id.id &&
+				    object_id.enum_id == obj_id.enum_id) {
+					*src_object_id =
+						object_id_from_bios_object_id(
+							0x1100);
+					/* break; */
+				}
 			}
+			bp_result = BP_RESULT_OK;
+			break;
 		}
-		bp_result = BP_RESULT_OK;
 		break;
 	case OBJECT_TYPE_CONNECTOR:
-		for (i = 0; i < tbl->v1_4->number_of_path; i++) {
-			obj_id = object_id_from_bios_object_id(
-				tbl->v1_4->display_path[i].display_objid);
-
-			if (object_id.type == obj_id.type &&
-				object_id.id == obj_id.id &&
-					object_id.enum_id == obj_id.enum_id) {
-				*src_object_id =
-				object_id_from_bios_object_id(
-				tbl->v1_4->display_path[i].encoderobjid);
-				/* break; */
+		switch (bp->object_info_tbl.revision.minor) {
+		default:
+		case 4:
+			for (i = 0; i < tbl->v1_4->number_of_path; i++) {
+				obj_id = object_id_from_bios_object_id(
+					tbl->v1_4->display_path[i]
+						.display_objid);
+
+				if (object_id.type == obj_id.type &&
+				    object_id.id == obj_id.id &&
+				    object_id.enum_id == obj_id.enum_id) {
+					*src_object_id =
+						object_id_from_bios_object_id(
+							tbl->v1_4
+								->display_path[i]
+								.encoderobjid);
+					/* break; */
+				}
 			}
+			bp_result = BP_RESULT_OK;
+			break;
 		}
 		bp_result = BP_RESULT_OK;
 		break;
+		case 5:
+			for (i = 0; i < tbl->v1_5->number_of_path; i++) {
+				obj_id = object_id_from_bios_object_id(
+								       tbl->v1_5->display_path[i].display_objid);
+
+				if (object_id.type == obj_id.type &&
+				    object_id.id == obj_id.id &&
+				    object_id.enum_id == obj_id.enum_id) {
+					*src_object_id = object_id_from_bios_object_id(
+										       tbl->v1_5->display_path[i].encoderobjid);
+					/* break; */
+				}
+			}
+		bp_result = BP_RESULT_OK;
+		break;
+
 	default:
+		bp_result = BP_RESULT_OK;
 		break;
 	}
 
@@ -290,12 +367,55 @@ static struct atom_display_object_path_v2 *get_bios_object(
 	}
 }
 
+/* from graphics_object_id, find display path which includes the object_id */
+static struct atom_display_object_path_v3 *get_bios_object_from_path_v3(
+	struct bios_parser *bp,
+	struct graphics_object_id id)
+{
+	unsigned int i;
+	struct graphics_object_id obj_id = {0};
+
+	switch (id.type) {
+	case OBJECT_TYPE_ENCODER:
+		for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) {
+			obj_id = object_id_from_bios_object_id(
+					bp->object_info_tbl.v1_5->display_path[i].encoderobjid);
+			if (id.type == obj_id.type && id.id == obj_id.id
+					&& id.enum_id == obj_id.enum_id)
+				return &bp->object_info_tbl.v1_5->display_path[i];
+		}
+        break;
+
+	case OBJECT_TYPE_CONNECTOR:
+	case OBJECT_TYPE_GENERIC:
+		/* Both Generic and Connector Object ID
+		 * will be stored on display_objid
+		 */
+		for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) {
+			obj_id = object_id_from_bios_object_id(
+					bp->object_info_tbl.v1_5->display_path[i].display_objid);
+			if (id.type == obj_id.type && id.id == obj_id.id
+					&& id.enum_id == obj_id.enum_id)
+				return &bp->object_info_tbl.v1_5->display_path[i];
+		}
+        break;
+
+	default:
+		return NULL;
+	}
+
+    return NULL;
+}
+
 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
 	struct graphics_object_id id,
 	struct graphics_object_i2c_info *info)
 {
 	uint32_t offset;
 	struct atom_display_object_path_v2 *object;
+
+	struct atom_display_object_path_v3 *object_path_v3;
+
 	struct atom_common_record_header *header;
 	struct atom_i2c_record *record;
 	struct atom_i2c_record dummy_record = {0};
@@ -313,12 +433,25 @@ static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
 			return BP_RESULT_NORECORD;
 	}
 
-	object = get_bios_object(bp, id);
+	switch (bp->object_info_tbl.revision.minor) {
+	    case 4:
+	    default:
+	        object = get_bios_object(bp, id);
 
-	if (!object)
-		return BP_RESULT_BADINPUT;
+	        if (!object)
+				return BP_RESULT_BADINPUT;
 
-	offset = object->disp_recordoffset + bp->object_info_tbl_offset;
+	        offset = object->disp_recordoffset + bp->object_info_tbl_offset;
+	        break;
+	    case 5:
+		object_path_v3 = get_bios_object_from_path_v3(bp, id);
+
+		if (!object_path_v3)
+			return BP_RESULT_BADINPUT;
+
+		offset = object_path_v3->disp_recordoffset + bp->object_info_tbl_offset;
+		break;
+	}
 
 	for (;;) {
 		header = GET_IMAGE(struct atom_common_record_header, offset);
@@ -421,6 +554,41 @@ static enum bp_result get_gpio_i2c_info(
 	return BP_RESULT_OK;
 }
 
+static struct atom_hpd_int_record *get_hpd_record_for_path_v3(
+	struct bios_parser *bp,
+	struct atom_display_object_path_v3 *object)
+{
+	struct atom_common_record_header *header;
+	uint32_t offset;
+
+	if (!object) {
+		BREAK_TO_DEBUGGER(); /* Invalid object */
+		return NULL;
+	}
+
+	offset = object->disp_recordoffset + bp->object_info_tbl_offset;
+
+	for (;;) {
+		header = GET_IMAGE(struct atom_common_record_header, offset);
+
+		if (!header)
+			return NULL;
+
+		if (header->record_type == ATOM_RECORD_END_TYPE ||
+			!header->record_size)
+			break;
+
+		if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
+			&& sizeof(struct atom_hpd_int_record) <=
+							header->record_size)
+			return (struct atom_hpd_int_record *) header;
+
+		offset += header->record_size;
+	}
+
+	return NULL;
+}
+
 static enum bp_result bios_parser_get_hpd_info(
 	struct dc_bios *dcb,
 	struct graphics_object_id id,
@@ -428,17 +596,32 @@ static enum bp_result bios_parser_get_hpd_info(
 {
 	struct bios_parser *bp = BP_FROM_DCB(dcb);
 	struct atom_display_object_path_v2 *object;
+	struct atom_display_object_path_v3 *object_path_v3;
 	struct atom_hpd_int_record *record = NULL;
 
 	if (!info)
 		return BP_RESULT_BADINPUT;
 
-	object = get_bios_object(bp, id);
+	switch (bp->object_info_tbl.revision.minor) {
+	    case 4:
+	    default:
+	        object = get_bios_object(bp, id);
 
-	if (!object)
-		return BP_RESULT_BADINPUT;
+			if (!object)
+				return BP_RESULT_BADINPUT;
+
+	        record = get_hpd_record(bp, object);
+
+	        break;
+	    case 5:
+		object_path_v3 = get_bios_object_from_path_v3(bp, id);
 
-	record = get_hpd_record(bp, object);
+		if (!object_path_v3)
+			return BP_RESULT_BADINPUT;
+
+		record = get_hpd_record_for_path_v3(bp, object_path_v3);
+		break;
+	}
 
 	if (record != NULL) {
 		info->hpd_int_gpio_uid = record->pin_id;
@@ -526,25 +709,9 @@ static enum bp_result bios_parser_get_gpio_pin_info(
 		return BP_RESULT_UNSUPPORTED;
 
 	/* Temporary hard code gpio pin info */
-#if defined(FOR_SIMNOW_BOOT)
-	{
-		struct  atom_gpio_pin_assignment  gpio_pin[8] = {
-				{0x5db5, 0, 0, 1, 0},
-				{0x5db5, 8, 8, 2, 0},
-				{0x5db5, 0x10, 0x10, 3, 0},
-				{0x5db5, 0x18, 0x14, 4, 0},
-				{0x5db5, 0x1A, 0x18, 5, 0},
-				{0x5db5, 0x1C, 0x1C, 6, 0},
-		};
-
-		count = 6;
-		memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin));
-	}
-#else
 	count = (le16_to_cpu(header->table_header.structuresize)
 			- sizeof(struct atom_common_table_header))
 				/ sizeof(struct atom_gpio_pin_assignment);
-#endif
 	for (i = 0; i < count; ++i) {
 		if (header->gpio_pin[i].gpio_id != gpio_id)
 			continue;
@@ -633,19 +800,37 @@ static enum bp_result bios_parser_get_device_tag(
 	struct bios_parser *bp = BP_FROM_DCB(dcb);
 	struct atom_display_object_path_v2 *object;
 
+	struct atom_display_object_path_v3 *object_path_v3;
+
+
 	if (!info)
 		return BP_RESULT_BADINPUT;
 
-	/* getBiosObject will return MXM object */
-	object = get_bios_object(bp, connector_object_id);
+	switch (bp->object_info_tbl.revision.minor) {
+	    case 4:
+	    default:
+	        /* getBiosObject will return MXM object */
+	        object = get_bios_object(bp, connector_object_id);
 
-	if (!object) {
-		BREAK_TO_DEBUGGER(); /* Invalid object id */
-		return BP_RESULT_BADINPUT;
-	}
+			if (!object) {
+				BREAK_TO_DEBUGGER(); /* Invalid object id */
+				return BP_RESULT_BADINPUT;
+			}
 
-	info->acpi_device = 0; /* BIOS no longer provides this */
-	info->dev_id = device_type_from_device_id(object->device_tag);
+	        info->acpi_device = 0; /* BIOS no longer provides this */
+	        info->dev_id = device_type_from_device_id(object->device_tag);
+	        break;
+	    case 5:
+		object_path_v3 = get_bios_object_from_path_v3(bp, connector_object_id);
+
+		if (!object_path_v3) {
+			BREAK_TO_DEBUGGER(); /* Invalid object id */
+			return BP_RESULT_BADINPUT;
+		}
+		info->acpi_device = 0; /* BIOS no longer provides this */
+		info->dev_id = device_type_from_device_id(object_path_v3->device_tag);
+		break;
+	}
 
 	return BP_RESULT_OK;
 }
@@ -803,6 +988,71 @@ static enum bp_result get_ss_info_v4_2(
 	return result;
 }
 
+static enum bp_result get_ss_info_v4_5(
+	struct bios_parser *bp,
+	uint32_t id,
+	uint32_t index,
+	struct spread_spectrum_info *ss_info)
+{
+	enum bp_result result = BP_RESULT_OK;
+	struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
+
+	if (!ss_info)
+		return BP_RESULT_BADINPUT;
+
+	if (!DATA_TABLES(dce_info))
+		return BP_RESULT_BADBIOSTABLE;
+
+	disp_cntl_tbl =  GET_IMAGE(struct atom_display_controller_info_v4_5,
+							DATA_TABLES(dce_info));
+	if (!disp_cntl_tbl)
+		return BP_RESULT_BADBIOSTABLE;
+
+	ss_info->type.STEP_AND_DELAY_INFO = false;
+	ss_info->spread_percentage_divider = 1000;
+	/* BIOS no longer uses target clock.  Always enable for now */
+	ss_info->target_clock_range = 0xffffffff;
+
+	switch (id) {
+	case AS_SIGNAL_TYPE_DVI:
+		ss_info->spread_spectrum_percentage =
+				disp_cntl_tbl->dvi_ss_percentage;
+		ss_info->spread_spectrum_range =
+				disp_cntl_tbl->dvi_ss_rate_10hz * 10;
+		if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
+			ss_info->type.CENTER_MODE = true;
+		break;
+	case AS_SIGNAL_TYPE_HDMI:
+		ss_info->spread_spectrum_percentage =
+				disp_cntl_tbl->hdmi_ss_percentage;
+		ss_info->spread_spectrum_range =
+				disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
+		if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
+			ss_info->type.CENTER_MODE = true;
+		break;
+	case AS_SIGNAL_TYPE_DISPLAY_PORT:
+		ss_info->spread_spectrum_percentage =
+				disp_cntl_tbl->dp_ss_percentage;
+		ss_info->spread_spectrum_range =
+				disp_cntl_tbl->dp_ss_rate_10hz * 10;
+		if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
+			ss_info->type.CENTER_MODE = true;
+		break;
+	case AS_SIGNAL_TYPE_GPU_PLL:
+		/* atom_smu_info_v4_0 does not have fields for SS for SMU Display PLL anymore.
+		 * SMU Display PLL supposed to be without spread.
+		 * Better place for it would be in atom_display_controller_info_v4_5 table.
+		 */
+		result = BP_RESULT_UNSUPPORTED;
+		break;
+	default:
+		result = BP_RESULT_UNSUPPORTED;
+		break;
+	}
+
+	return result;
+}
+
 /**
  * bios_parser_get_spread_spectrum_info
  * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
@@ -847,6 +1097,9 @@ static enum bp_result bios_parser_get_spread_spectrum_info(
 		case 3:
 		case 4:
 			return get_ss_info_v4_2(bp, signal, index, ss_info);
+		case 5:
+			return get_ss_info_v4_5(bp, signal, index, ss_info);
+
 		default:
 			ASSERT(0);
 			break;
@@ -887,6 +1140,31 @@ static enum bp_result get_soc_bb_info_v4_4(
 	return result;
 }
 
+static enum bp_result get_soc_bb_info_v4_5(
+	struct bios_parser *bp,
+	struct bp_soc_bb_info *soc_bb_info)
+{
+	enum bp_result result = BP_RESULT_OK;
+	struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
+
+	if (!soc_bb_info)
+		return BP_RESULT_BADINPUT;
+
+	if (!DATA_TABLES(dce_info))
+		return BP_RESULT_BADBIOSTABLE;
+
+	disp_cntl_tbl =  GET_IMAGE(struct atom_display_controller_info_v4_5,
+							DATA_TABLES(dce_info));
+	if (!disp_cntl_tbl)
+		return BP_RESULT_BADBIOSTABLE;
+
+	soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat;
+	soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat;
+	soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat;
+
+	return result;
+}
+
 static enum bp_result bios_parser_get_soc_bb_info(
 	struct dc_bios *dcb,
 	struct bp_soc_bb_info *soc_bb_info)
@@ -916,6 +1194,9 @@ static enum bp_result bios_parser_get_soc_bb_info(
 		case 4:
 			result = get_soc_bb_info_v4_4(bp, soc_bb_info);
 			break;
+		case 5:
+			result = get_soc_bb_info_v4_5(bp, soc_bb_info);
+			break;
 		default:
 			break;
 		}
@@ -1023,6 +1304,30 @@ static enum bp_result get_disp_caps_v4_4(
 	return result;
 }
 
+static enum bp_result get_disp_caps_v4_5(
+	struct bios_parser *bp,
+	uint8_t *dce_caps)
+{
+	enum bp_result result = BP_RESULT_OK;
+	struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
+
+	if (!dce_caps)
+		return BP_RESULT_BADINPUT;
+
+	if (!DATA_TABLES(dce_info))
+		return BP_RESULT_BADBIOSTABLE;
+
+	disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5,
+							DATA_TABLES(dce_info));
+
+	if (!disp_cntl_tbl)
+		return BP_RESULT_BADBIOSTABLE;
+
+	*dce_caps = disp_cntl_tbl->display_caps;
+
+	return result;
+}
+
 static enum bp_result bios_parser_get_lttpr_interop(
 	struct dc_bios *dcb,
 	uint8_t *dce_caps)
@@ -1057,6 +1362,11 @@ static enum bp_result bios_parser_get_lttpr_interop(
 			result = get_disp_caps_v4_4(bp, dce_caps);
 			*dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
 			break;
+		case 5:
+			result = get_disp_caps_v4_5(bp, dce_caps);
+			*dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
+			break;
+
 		default:
 			break;
 		}
@@ -1102,6 +1412,10 @@ static enum bp_result bios_parser_get_lttpr_caps(
 			result = get_disp_caps_v4_4(bp, dce_caps);
 			*dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
 			break;
+		case 5:
+			result = get_disp_caps_v4_5(bp, dce_caps);
+			*dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
+
 		default:
 			break;
 		}
@@ -1218,7 +1532,6 @@ static enum bp_result bios_parser_get_embedded_panel_info(
 		default:
 			break;
 		}
-		break;
 	default:
 		break;
 	}
@@ -1274,8 +1587,17 @@ static bool bios_parser_is_device_id_supported(
 
 	uint32_t mask = get_support_mask_for_device_id(id);
 
-	return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) &
-								mask) != 0;
+	switch (bp->object_info_tbl.revision.minor) {
+	    case 4:
+	    default:
+	        return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & mask) != 0;
+			break;
+	    case 5:
+			return (le16_to_cpu(bp->object_info_tbl.v1_5->supporteddevices) & mask) != 0;
+			break;
+	}
+
+    return false;
 }
 
 static uint32_t bios_parser_get_ss_entry_number(
@@ -1408,12 +1730,21 @@ static void bios_parser_set_scratch_critical_state(
 	bios_set_scratch_critical_state(dcb, state);
 }
 
+struct atom_dig_transmitter_info_header_v5_3 {
+    struct atom_common_table_header table_header;
+    uint16_t dpphy_hdmi_settings_offset;
+    uint16_t dpphy_dvi_settings_offset;
+    uint16_t dpphy_dp_setting_table_offset;
+    uint16_t uniphy_xbar_settings_v2_table_offset;
+    uint16_t dpphy_internal_reg_overide_offset;
+};
+
 static enum bp_result bios_parser_get_firmware_info(
 	struct dc_bios *dcb,
 	struct dc_firmware_info *info)
 {
 	struct bios_parser *bp = BP_FROM_DCB(dcb);
-	enum bp_result result = BP_RESULT_BADBIOSTABLE;
+	static enum bp_result result = BP_RESULT_BADBIOSTABLE;
 	struct atom_common_table_header *header;
 
 	struct atom_data_revision revision;
@@ -1590,6 +1921,11 @@ static enum bp_result get_firmware_info_v3_4(
 	struct atom_data_revision revision;
 	struct atom_display_controller_info_v4_1 *dce_info_v4_1 = NULL;
 	struct atom_display_controller_info_v4_4 *dce_info_v4_4 = NULL;
+
+	struct atom_smu_info_v3_5 *smu_info_v3_5 = NULL;
+	struct atom_display_controller_info_v4_5 *dce_info_v4_5 = NULL;
+	struct atom_smu_info_v4_0 *smu_info_v4_0 = NULL;
+
 	if (!info)
 		return BP_RESULT_BADINPUT;
 
@@ -1609,6 +1945,22 @@ static enum bp_result get_firmware_info_v3_4(
 	switch (revision.major) {
 	case 4:
 		switch (revision.minor) {
+		case 5:
+			dce_info_v4_5 = GET_IMAGE(struct atom_display_controller_info_v4_5,
+							DATA_TABLES(dce_info));
+
+			if (!dce_info_v4_5)
+				return BP_RESULT_BADBIOSTABLE;
+
+			 /* 100MHz expected */
+			info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10;
+			info->dp_phy_ref_clk             = dce_info_v4_5->dpphy_refclk_10khz * 10;
+			 /* 50MHz expected */
+			info->i2c_engine_ref_clk         = dce_info_v4_5->i2c_engine_refclk_10khz * 10;
+
+			/* For DCN32/321 Display PLL VCO Frequency from dce_info_v4_5 may not be reliable */
+			break;
+
 		case 4:
 			dce_info_v4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4,
 							DATA_TABLES(dce_info));
@@ -1650,6 +2002,45 @@ static enum bp_result get_firmware_info_v3_4(
 					DATA_TABLES(smu_info));
 	get_atom_data_table_revision(header, &revision);
 
+	switch (revision.major) {
+	case 3:
+		switch (revision.minor) {
+		case 5:
+			smu_info_v3_5 = GET_IMAGE(struct atom_smu_info_v3_5,
+							DATA_TABLES(smu_info));
+
+			if (!smu_info_v3_5)
+				return BP_RESULT_BADBIOSTABLE;
+
+			info->default_engine_clk = smu_info_v3_5->bootup_dcefclk_10khz * 10;
+			break;
+
+		default:
+			break;
+		}
+		break;
+
+	case 4:
+		switch (revision.minor) {
+		case 0:
+			smu_info_v4_0 = GET_IMAGE(struct atom_smu_info_v4_0,
+							DATA_TABLES(smu_info));
+
+			if (!smu_info_v4_0)
+				return BP_RESULT_BADBIOSTABLE;
+
+			/* For DCN32/321 bootup DCFCLK from smu_info_v4_0 may not be reliable */
+			break;
+
+		default:
+			break;
+		}
+		break;
+
+	default:
+		break;
+	}
+
 	 // We need to convert from 10KHz units into KHz units.
 	info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
 
@@ -1675,6 +2066,12 @@ static enum bp_result bios_parser_get_encoder_cap_info(
 	if (!info)
 		return BP_RESULT_BADINPUT;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	/* encoder cap record not available in v1_5 */
+	if (bp->object_info_tbl.revision.minor == 5)
+		return BP_RESULT_NORECORD;
+#endif
+
 	object = get_bios_object(bp, object_id);
 
 	if (!object)
@@ -1781,6 +2178,42 @@ static struct atom_disp_connector_caps_record *get_disp_connector_caps_record(
 	return NULL;
 }
 
+static struct atom_connector_caps_record *get_connector_caps_record(
+	struct bios_parser *bp,
+	struct atom_display_object_path_v3 *object)
+{
+	struct atom_common_record_header *header;
+	uint32_t offset;
+
+	if (!object) {
+		BREAK_TO_DEBUGGER(); /* Invalid object */
+		return NULL;
+	}
+
+	offset = object->disp_recordoffset + bp->object_info_tbl_offset;
+
+	for (;;) {
+		header = GET_IMAGE(struct atom_common_record_header, offset);
+
+		if (!header)
+			return NULL;
+
+		offset += header->record_size;
+
+		if (header->record_type == ATOM_RECORD_END_TYPE ||
+				!header->record_size)
+			break;
+
+		if (header->record_type != ATOM_CONNECTOR_CAP_RECORD_TYPE)
+			continue;
+
+		if (sizeof(struct atom_connector_caps_record) <= header->record_size)
+			return (struct atom_connector_caps_record *)header;
+	}
+
+	return NULL;
+}
+
 static enum bp_result bios_parser_get_disp_connector_caps_info(
 	struct dc_bios *dcb,
 	struct graphics_object_id object_id,
@@ -1788,25 +2221,116 @@ static enum bp_result bios_parser_get_disp_connector_caps_info(
 {
 	struct bios_parser *bp = BP_FROM_DCB(dcb);
 	struct atom_display_object_path_v2 *object;
+
+	struct atom_display_object_path_v3 *object_path_v3;
+	struct atom_connector_caps_record *record_path_v3;
+
 	struct atom_disp_connector_caps_record *record = NULL;
 
 	if (!info)
 		return BP_RESULT_BADINPUT;
 
-	object = get_bios_object(bp, object_id);
+	switch (bp->object_info_tbl.revision.minor) {
+	    case 4:
+	    default:
+		    object = get_bios_object(bp, object_id);
 
-	if (!object)
+		    if (!object)
+			    return BP_RESULT_BADINPUT;
+
+		    record = get_disp_connector_caps_record(bp, object);
+		    if (!record)
+			    return BP_RESULT_NORECORD;
+
+		    info->INTERNAL_DISPLAY =
+			    (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) ? 1 : 0;
+		    info->INTERNAL_DISPLAY_BL =
+			    (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) ? 1 : 0;
+		    break;
+	    case 5:
+		object_path_v3 = get_bios_object_from_path_v3(bp, object_id);
+
+		if (!object_path_v3)
+			return BP_RESULT_BADINPUT;
+
+		record_path_v3 = get_connector_caps_record(bp, object_path_v3);
+		if (!record_path_v3)
+			return BP_RESULT_NORECORD;
+
+		info->INTERNAL_DISPLAY = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY)
+									? 1 : 0;
+		info->INTERNAL_DISPLAY_BL = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL)
+										? 1 : 0;
+		break;
+	}
+
+	return BP_RESULT_OK;
+}
+
+static struct atom_connector_speed_record *get_connector_speed_cap_record(
+	struct bios_parser *bp,
+	struct atom_display_object_path_v3 *object)
+{
+	struct atom_common_record_header *header;
+	uint32_t offset;
+
+	if (!object) {
+		BREAK_TO_DEBUGGER(); /* Invalid object */
+		return NULL;
+	}
+
+	offset = object->disp_recordoffset + bp->object_info_tbl_offset;
+
+	for (;;) {
+		header = GET_IMAGE(struct atom_common_record_header, offset);
+
+		if (!header)
+			return NULL;
+
+		offset += header->record_size;
+
+		if (header->record_type == ATOM_RECORD_END_TYPE ||
+				!header->record_size)
+			break;
+
+		if (header->record_type != ATOM_CONNECTOR_SPEED_UPTO)
+			continue;
+
+		if (sizeof(struct atom_connector_speed_record) <= header->record_size)
+			return (struct atom_connector_speed_record *)header;
+	}
+
+	return NULL;
+}
+
+static enum bp_result bios_parser_get_connector_speed_cap_info(
+	struct dc_bios *dcb,
+	struct graphics_object_id object_id,
+	struct bp_connector_speed_cap_info *info)
+{
+	struct bios_parser *bp = BP_FROM_DCB(dcb);
+	struct atom_display_object_path_v3 *object_path_v3;
+	//struct atom_connector_speed_record *record = NULL;
+	struct atom_connector_speed_record *record;
+
+	if (!info)
+		return BP_RESULT_BADINPUT;
+
+	object_path_v3 = get_bios_object_from_path_v3(bp, object_id);
+
+	if (!object_path_v3)
 		return BP_RESULT_BADINPUT;
 
-	record = get_disp_connector_caps_record(bp, object);
+	record = get_connector_speed_cap_record(bp, object_path_v3);
 	if (!record)
 		return BP_RESULT_NORECORD;
 
-	info->INTERNAL_DISPLAY = (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY)
-									? 1 : 0;
-	info->INTERNAL_DISPLAY_BL = (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL)
-											? 1 : 0;
-
+	info->DP_HBR2_EN = (record->connector_max_speed >= 5400) ? 1 : 0;
+	info->DP_HBR3_EN = (record->connector_max_speed >= 8100) ? 1 : 0;
+	info->HDMI_6GB_EN = (record->connector_max_speed >= 5940) ? 1 : 0;
+	info->DP_UHBR10_EN = (record->connector_max_speed >= 10000) ? 1 : 0;
+	info->DP_UHBR13_5_EN = (record->connector_max_speed >= 13500) ? 1 : 0;
+	info->DP_UHBR20_EN = (record->connector_max_speed >= 20000) ? 1 : 0;
 	return BP_RESULT_OK;
 }
 
@@ -1815,7 +2339,7 @@ static enum bp_result get_vram_info_v23(
 	struct dc_vram_info *info)
 {
 	struct atom_vram_info_header_v2_3 *info_v23;
-	enum bp_result result = BP_RESULT_OK;
+	static enum bp_result result = BP_RESULT_OK;
 
 	info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3,
 						DATA_TABLES(vram_info));
@@ -1834,7 +2358,7 @@ static enum bp_result get_vram_info_v24(
 	struct dc_vram_info *info)
 {
 	struct atom_vram_info_header_v2_4 *info_v24;
-	enum bp_result result = BP_RESULT_OK;
+	static enum bp_result result = BP_RESULT_OK;
 
 	info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4,
 						DATA_TABLES(vram_info));
@@ -1853,7 +2377,7 @@ static enum bp_result get_vram_info_v25(
 	struct dc_vram_info *info)
 {
 	struct atom_vram_info_header_v2_5 *info_v25;
-	enum bp_result result = BP_RESULT_OK;
+	static enum bp_result result = BP_RESULT_OK;
 
 	info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5,
 						DATA_TABLES(vram_info));
@@ -1878,7 +2402,7 @@ static enum bp_result get_vram_info_v25(
  * integrated_info *info - [out] store and output integrated info
  *
  * @return
- * enum bp_result - BP_RESULT_OK if information is available,
+ * static enum bp_result - BP_RESULT_OK if information is available,
  *                  BP_RESULT_BADBIOSTABLE otherwise.
  */
 static enum bp_result get_integrated_info_v11(
@@ -2369,17 +2893,19 @@ static enum bp_result get_integrated_info_v2_2(
  * integrated_info *info - [out] store and output integrated info
  *
  * @return
- * enum bp_result - BP_RESULT_OK if information is available,
+ * static enum bp_result - BP_RESULT_OK if information is available,
  *                  BP_RESULT_BADBIOSTABLE otherwise.
  */
 static enum bp_result construct_integrated_info(
 	struct bios_parser *bp,
 	struct integrated_info *info)
 {
-	enum bp_result result = BP_RESULT_BADBIOSTABLE;
+	static enum bp_result result = BP_RESULT_BADBIOSTABLE;
 
 	struct atom_common_table_header *header;
 	struct atom_data_revision revision;
+
+	struct clock_voltage_caps temp = {0, 0};
 	uint32_t i;
 	uint32_t j;
 
@@ -2427,8 +2953,10 @@ static enum bp_result construct_integrated_info(
 				info->disp_clk_voltage[j-1].max_supported_clk
 				) {
 				/* swap j and j - 1*/
-				swap(info->disp_clk_voltage[j - 1],
-				     info->disp_clk_voltage[j]);
+				temp = info->disp_clk_voltage[j-1];
+				info->disp_clk_voltage[j-1] =
+					info->disp_clk_voltage[j];
+				info->disp_clk_voltage[j] = temp;
 			}
 		}
 	}
@@ -2441,7 +2969,7 @@ static enum bp_result bios_parser_get_vram_info(
 		struct dc_vram_info *info)
 {
 	struct bios_parser *bp = BP_FROM_DCB(dcb);
-	enum bp_result result = BP_RESULT_BADBIOSTABLE;
+	static enum bp_result result = BP_RESULT_BADBIOSTABLE;
 	struct atom_common_table_header *header;
 	struct atom_data_revision revision;
 
@@ -2507,7 +3035,7 @@ static enum bp_result update_slot_layout_info(
 	struct atom_display_object_path_v2 *object;
 	struct atom_bracket_layout_record *record;
 	struct atom_common_record_header *record_header;
-	enum bp_result result;
+	static enum bp_result result;
 	struct bios_parser *bp;
 	struct object_info_table *tbl;
 	struct display_object_info_table_v1_4 *v1_4;
@@ -2613,6 +3141,104 @@ static enum bp_result update_slot_layout_info(
 	return result;
 }
 
+static enum bp_result update_slot_layout_info_v2(
+	struct dc_bios *dcb,
+	unsigned int i,
+	struct slot_layout_info *slot_layout_info)
+{
+	unsigned int record_offset;
+	struct atom_display_object_path_v3 *object;
+	struct atom_bracket_layout_record_v2 *record;
+	struct atom_common_record_header *record_header;
+	static enum bp_result result;
+	struct bios_parser *bp;
+	struct object_info_table *tbl;
+	struct display_object_info_table_v1_5 *v1_5;
+	struct graphics_object_id connector_id;
+
+	record = NULL;
+	record_header = NULL;
+	result = BP_RESULT_NORECORD;
+
+	bp = BP_FROM_DCB(dcb);
+	tbl = &bp->object_info_tbl;
+	v1_5 = tbl->v1_5;
+
+	object = &v1_5->display_path[i];
+	record_offset = (unsigned int)
+		(object->disp_recordoffset) +
+		(unsigned int)(bp->object_info_tbl_offset);
+
+	for (;;) {
+
+		record_header = (struct atom_common_record_header *)
+			GET_IMAGE(struct atom_common_record_header,
+			record_offset);
+		if (record_header == NULL) {
+			result = BP_RESULT_BADBIOSTABLE;
+			break;
+		}
+
+		/* the end of the list */
+		if (record_header->record_type == ATOM_RECORD_END_TYPE ||
+			record_header->record_size == 0)	{
+			break;
+		}
+
+		if (record_header->record_type ==
+			ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE &&
+			sizeof(struct atom_bracket_layout_record_v2)
+			<= record_header->record_size) {
+			record = (struct atom_bracket_layout_record_v2 *)
+				(record_header);
+			result = BP_RESULT_OK;
+			break;
+		}
+
+		record_offset += record_header->record_size;
+	}
+
+	/* return if the record not found */
+	if (result != BP_RESULT_OK)
+		return result;
+
+	/* get slot sizes */
+	connector_id = object_id_from_bios_object_id(object->display_objid);
+
+	slot_layout_info->length = record->bracketlen;
+	slot_layout_info->width = record->bracketwidth;
+	slot_layout_info->num_of_connectors = v1_5->number_of_path;
+	slot_layout_info->connectors[i].position = record->conn_num;
+	slot_layout_info->connectors[i].connector_id = connector_id;
+
+	switch (connector_id.id) {
+	case CONNECTOR_ID_SINGLE_LINK_DVID:
+	case CONNECTOR_ID_DUAL_LINK_DVID:
+		slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DVI_D;
+		slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DVI;
+		break;
+
+	case CONNECTOR_ID_HDMI_TYPE_A:
+		slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_HDMI;
+		slot_layout_info->connectors[i].length = CONNECTOR_SIZE_HDMI;
+		break;
+
+	case CONNECTOR_ID_DISPLAY_PORT:
+		if (record->mini_type == MINI_TYPE_NORMAL) {
+			slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DP;
+			slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DP;
+		} else {
+			slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_MINI_DP;
+			slot_layout_info->connectors[i].length = CONNECTOR_SIZE_MINI_DP;
+		}
+		break;
+
+	default:
+		slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_UNKNOWN;
+		slot_layout_info->connectors[i].length = CONNECTOR_SIZE_UNKNOWN;
+	}
+	return result;
+}
 
 static enum bp_result get_bracket_layout_record(
 	struct dc_bios *dcb,
@@ -2621,9 +3247,10 @@ static enum bp_result get_bracket_layout_record(
 {
 	unsigned int i;
 	struct bios_parser *bp = BP_FROM_DCB(dcb);
-	enum bp_result result;
+	static enum bp_result result;
 	struct object_info_table *tbl;
 	struct display_object_info_table_v1_4 *v1_4;
+    struct display_object_info_table_v1_5 *v1_5;
 
 	if (slot_layout_info == NULL) {
 		DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n");
@@ -2633,14 +3260,21 @@ static enum bp_result get_bracket_layout_record(
 	v1_4 = tbl->v1_4;
 
 	result = BP_RESULT_NORECORD;
-	for (i = 0; i < v1_4->number_of_path; ++i)	{
-
-		if (bracket_layout_id ==
-			v1_4->display_path[i].display_objid) {
-			result = update_slot_layout_info(dcb, i,
-				slot_layout_info);
+	switch (bp->object_info_tbl.revision.minor) {
+		case 4:
+		default:
+			for (i = 0; i < v1_4->number_of_path; ++i)	{
+				if (bracket_layout_id ==
+					v1_4->display_path[i].display_objid) {
+					result = update_slot_layout_info(dcb, i, slot_layout_info);
+					break;
+				}
+			}
+		    break;
+		case 5:
+			for (i = 0; i < v1_5->number_of_path; ++i)
+				result = update_slot_layout_info_v2(dcb, i, slot_layout_info);
 			break;
-		}
 	}
 	return result;
 }
@@ -2650,7 +3284,10 @@ static enum bp_result bios_get_board_layout_info(
 	struct board_layout_info *board_layout_info)
 {
 	unsigned int i;
-	enum bp_result record_result;
+
+	struct bios_parser *bp;
+
+	static enum bp_result record_result;
 
 	const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
 		GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1,
@@ -2658,6 +3295,9 @@ static enum bp_result bios_get_board_layout_info(
 		0, 0
 	};
 
+
+	bp = BP_FROM_DCB(dcb);
+
 	if (board_layout_info == NULL) {
 		DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
 		return BP_RESULT_BADINPUT;
@@ -2692,99 +3332,6 @@ static uint16_t bios_parser_pack_data_tables(
 	struct dc_bios *dcb,
 	void *dst)
 {
-#ifdef PACK_BIOS_DATA
-	struct bios_parser *bp = BP_FROM_DCB(dcb);
-	struct atom_rom_header_v2_2 *rom_header = NULL;
-	struct atom_rom_header_v2_2 *packed_rom_header = NULL;
-	struct atom_common_table_header *data_tbl_header = NULL;
-	struct atom_master_list_of_data_tables_v2_1 *data_tbl_list = NULL;
-	struct atom_master_data_table_v2_1 *packed_master_data_tbl = NULL;
-	struct atom_data_revision tbl_rev = {0};
-	uint16_t *rom_header_offset = NULL;
-	const uint8_t *bios = bp->base.bios;
-	uint8_t *bios_dst = (uint8_t *)dst;
-	uint16_t packed_rom_header_offset;
-	uint16_t packed_masterdatatable_offset;
-	uint16_t packed_data_tbl_offset;
-	uint16_t data_tbl_offset;
-	unsigned int i;
-
-	rom_header_offset =
-		GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
-
-	if (!rom_header_offset)
-		return 0;
-
-	rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset);
-
-	if (!rom_header)
-		return 0;
-
-	get_atom_data_table_revision(&rom_header->table_header, &tbl_rev);
-	if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2))
-		return 0;
-
-	get_atom_data_table_revision(&bp->master_data_tbl->table_header, &tbl_rev);
-	if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 1))
-		return 0;
-
-	packed_rom_header_offset =
-		OFFSET_TO_ATOM_ROM_HEADER_POINTER + sizeof(*rom_header_offset);
-
-	packed_masterdatatable_offset =
-		packed_rom_header_offset + rom_header->table_header.structuresize;
-
-	packed_data_tbl_offset =
-		packed_masterdatatable_offset +
-		bp->master_data_tbl->table_header.structuresize;
-
-	packed_rom_header =
-		(struct atom_rom_header_v2_2 *)(bios_dst + packed_rom_header_offset);
-
-	packed_master_data_tbl =
-		(struct atom_master_data_table_v2_1 *)(bios_dst +
-		packed_masterdatatable_offset);
-
-	memcpy(bios_dst, bios, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
-
-	*((uint16_t *)(bios_dst + OFFSET_TO_ATOM_ROM_HEADER_POINTER)) =
-		packed_rom_header_offset;
-
-	memcpy(bios_dst + packed_rom_header_offset, rom_header,
-		rom_header->table_header.structuresize);
-
-	packed_rom_header->masterdatatable_offset = packed_masterdatatable_offset;
-
-	memcpy(&packed_master_data_tbl->table_header,
-		&bp->master_data_tbl->table_header,
-		sizeof(bp->master_data_tbl->table_header));
-
-	data_tbl_list = &bp->master_data_tbl->listOfdatatables;
-
-	/* Each data table offset in data table list is 2 bytes,
-	 * we can use that to iterate through listOfdatatables
-	 * without knowing the name of each member.
-	 */
-	for (i = 0; i < sizeof(*data_tbl_list)/sizeof(uint16_t); i++) {
-		data_tbl_offset = *((uint16_t *)data_tbl_list + i);
-
-		if (data_tbl_offset) {
-			data_tbl_header =
-				(struct atom_common_table_header *)(bios + data_tbl_offset);
-
-			memcpy(bios_dst + packed_data_tbl_offset, data_tbl_header,
-				data_tbl_header->structuresize);
-
-			*((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) =
-				packed_data_tbl_offset;
-
-			packed_data_tbl_offset += data_tbl_header->structuresize;
-		} else {
-			*((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) = 0;
-		}
-	}
-	return packed_data_tbl_offset;
-#endif
 	// TODO: There is data bytes alignment issue, disable it for now.
 	return 0;
 }
@@ -2814,6 +3361,13 @@ static struct atom_dc_golden_table_v1 *bios_get_golden_table(
 			dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset;
 			*dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver;
 			break;
+		case 5:
+		default:
+			/* For atom_display_controller_info_v4_5 there is no need to get golden table from
+			 * dc_golden_table_offset as all these fields previously in golden table used for AUX
+			 * pre-charge settings are now available directly in atom_display_controller_info_v4_5.
+			 */
+			break;
 		}
 		break;
 	}
@@ -2916,6 +3470,7 @@ static const struct dc_vbios_funcs vbios_funcs = {
 	.bios_parser_destroy = firmware_parser_destroy,
 
 	.get_board_layout_info = bios_get_board_layout_info,
+	/* TODO: use this fn in hw init?*/
 	.pack_data_tables = bios_parser_pack_data_tables,
 
 	.get_atom_dc_golden_table = bios_get_atom_dc_golden_table,
@@ -2929,6 +3484,8 @@ static const struct dc_vbios_funcs vbios_funcs = {
 	.get_lttpr_caps = bios_parser_get_lttpr_caps,
 
 	.get_lttpr_interop = bios_parser_get_lttpr_interop,
+
+	.get_connector_speed_cap_info = bios_parser_get_connector_speed_cap_info,
 };
 
 static bool bios_parser2_construct(
@@ -3002,6 +3559,16 @@ static bool bios_parser2_construct(
 			return false;
 
 		bp->object_info_tbl.v1_4 = tbl_v1_4;
+	} else if (bp->object_info_tbl.revision.major == 1
+		&& bp->object_info_tbl.revision.minor == 5) {
+		struct display_object_info_table_v1_5 *tbl_v1_5;
+
+		tbl_v1_5 = GET_IMAGE(struct display_object_info_table_v1_5,
+			bp->object_info_tbl_offset);
+		if (!tbl_v1_5)
+			return false;
+
+		bp->object_info_tbl.v1_5 = tbl_v1_5;
 	} else {
 		ASSERT(0);
 		return false;
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h
index bf1f5c86e65cc..41d02d4730821 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h
@@ -40,6 +40,7 @@ struct object_info_table {
 	struct atom_data_revision revision;
 	union {
 		struct display_object_info_table_v1_4 *v1_4;
+		struct display_object_info_table_v1_5 *v1_5;
 	};
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index f3792286f571a..f22593bcb862e 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -77,6 +77,8 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
 	case DCN_VERSION_3_1:
 	case DCN_VERSION_3_15:
 	case DCN_VERSION_3_16:
+	case DCN_VERSION_3_2:
+	case DCN_VERSION_3_21:
 		*h = dal_cmd_tbl_helper_dce112_get_table2();
 		return true;
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index e803e59abd56c..d145dcbca7786 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -328,8 +328,8 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
 	    dcn32_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
 	    return &clk_mgr->base;
 	    break;
-#endif
 	}
+#endif
 	default:
 		ASSERT(0); /* Unknown Asic */
 		break;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f144494011882..e3e3b27916322 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3054,11 +3054,15 @@ static void commit_planes_for_stream(struct dc *dc,
 
 	}
 
-	if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
-		dc->hwss.interdependent_update_lock(dc, context, false);
-	} else {
-		dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
-	}
+#ifdef CONFIG_DRM_AMD_DC_DCN
+		if (update_type != UPDATE_TYPE_FAST)
+			if (dc->hwss.commit_subvp_config)
+				dc->hwss.commit_subvp_config(dc, context);
+#endif
+		if (should_lock_all_pipes && dc->hwss.interdependent_update_lock)
+			dc->hwss.interdependent_update_lock(dc, context, false);
+		else
+			dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
 
 	if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
 		if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 6774dd8bb53e1..b087452e45908 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -67,6 +67,8 @@
 #include "dcn31/dcn31_resource.h"
 #include "dcn315/dcn315_resource.h"
 #include "dcn316/dcn316_resource.h"
+#include "../dcn32/dcn32_resource.h"
+#include "../dcn321/dcn321_resource.h"
 
 #define DC_LOGGER_INIT(logger)
 
@@ -162,7 +164,11 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
 		if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev))
 			dc_version = DCN_VERSION_3_16;
 		break;
-
+	case AMDGPU_FAMILY_GC_11_0_0:
+		dc_version = DCN_VERSION_3_2;
+		if (ASICREV_IS_GC_11_0_2(asic_id.hw_internal_rev))
+			dc_version = DCN_VERSION_3_21;
+		break;
 	default:
 		dc_version = DCE_VERSION_UNKNOWN;
 		break;
@@ -258,6 +264,12 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,
 	case DCN_VERSION_3_16:
 		res_pool = dcn316_create_resource_pool(init_data, dc);
 		break;
+	case DCN_VERSION_3_2:
+		res_pool = dcn32_create_resource_pool(init_data, dc);
+		break;
+	case DCN_VERSION_3_21:
+		res_pool = dcn321_create_resource_pool(init_data, dc);
+		break;
 #endif
 	default:
 		break;
@@ -1982,6 +1994,11 @@ enum dc_status dc_remove_stream_from_ctx(
 				dc->res_pool,
 			del_pipe->stream_res.stream_enc,
 			false);
+	/* Release link encoder from stream in new dc_state. */
+	if (dc->res_pool->funcs->link_enc_unassign)
+		dc->res_pool->funcs->link_enc_unassign(new_ctx, del_pipe->stream);
+
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	if (is_dp_128b_132b_signal(del_pipe)) {
 		update_hpo_dp_stream_engine_usage(
 			&new_ctx->res_ctx, dc->res_pool,
@@ -1989,6 +2006,7 @@ enum dc_status dc_remove_stream_from_ctx(
 			false);
 		remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream);
 	}
+#endif
 
 	if (del_pipe->stream_res.audio)
 		update_audio_usage(
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 52d6da5ea9a7c..691654653ebb1 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -162,6 +162,10 @@ struct dc_color_caps {
 	struct mpc_color_caps mpc;
 };
 
+struct dc_dmub_caps {
+    bool psr;
+};
+
 struct dc_caps {
 	uint32_t max_streams;
 	uint32_t max_links;
@@ -196,12 +200,22 @@ struct dc_caps {
 	unsigned int cursor_cache_size;
 	struct dc_plane_cap planes[MAX_PLANES];
 	struct dc_color_caps color;
+	struct dc_dmub_caps dmub_caps;
 	bool dp_hpo;
 	bool hdmi_frl_pcon_support;
 	bool edp_dsc_support;
 	bool vbios_lttpr_aware;
 	bool vbios_lttpr_enable;
 	uint32_t max_otg_num;
+#ifdef CONFIG_DRM_AMD_DC_DCN
+	uint32_t max_cab_allocation_bytes;
+	uint32_t cache_line_size;
+	uint32_t cache_num_ways;
+	uint16_t subvp_fw_processing_delay_us;
+	uint16_t subvp_prefetch_end_to_mall_start_us;
+	uint16_t subvp_pstate_allow_width_us;
+	uint16_t subvp_vertical_int_margin_us;
+#endif
 };
 
 struct dc_bug_wa {
@@ -427,6 +441,8 @@ struct dc_clocks {
 	 */
 	bool prev_p_state_change_support;
 	bool fclk_prev_p_state_change_support;
+	int num_ways;
+	int prev_num_ways;
 	enum dtm_pstate dtm_level;
 	int max_supported_dppclk_khz;
 	int max_supported_dispclk_khz;
@@ -721,6 +737,9 @@ struct dc_debug_options {
 	bool enable_z9_disable_interface;
 	bool enable_sw_cntl_psr;
 	union dpia_debug_options dpia_debug;
+	bool force_disable_subvp;
+	bool force_subvp_mclk_switch;
+	bool force_usr_allow;
 	bool apply_vendor_specific_lttpr_wa;
 	bool extended_blank_optimization;
 	union aux_wake_wa_options aux_wake_wa;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
index 67abda44eb1f4..260ac4458870b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
@@ -156,6 +156,11 @@ struct dc_vbios_funcs {
 	enum bp_result (*get_lttpr_interop)(
 			struct dc_bios *dcb,
 			uint8_t *dce_caps);
+
+	enum bp_result (*get_connector_speed_cap_info)(
+		struct dc_bios *bios,
+		struct graphics_object_id object_id,
+		struct bp_connector_speed_cap_info *info);
 };
 
 struct bios_registers {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index aa7e3a07191d9..d75416dc9faee 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -780,6 +780,7 @@ struct dc_crtc_timing {
 	uint32_t v_sync_width;
 
 	uint32_t pix_clk_100hz;
+	uint32_t min_refresh_in_uhz;
 
 	uint32_t vic;
 	uint32_t hdmi_vic;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 58941f4defb35..772b4a61f166a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -145,6 +145,24 @@ struct test_pattern {
 	unsigned int cust_pattern_size;
 };
 
+#ifdef CONFIG_DRM_AMD_DC_DCN
+#define SUBVP_DRR_MARGIN_US 500 // 500us for DRR margin (SubVP + DRR)
+
+enum mall_stream_type {
+	SUBVP_NONE, // subvp not in use
+	SUBVP_MAIN, // subvp in use, this stream is main stream
+	SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream
+};
+
+struct mall_stream_config {
+	/* MALL stream config to indicate if the stream is phantom or not.
+	 * We will use a phantom stream to indicate that the pipe is phantom.
+	 */
+	enum mall_stream_type type;
+	struct dc_stream_state *paired_stream;	// master / slave stream
+};
+#endif
+
 struct dc_stream_state {
 	// sink is deprecated, new code should not reference
 	// this pointer
@@ -255,6 +273,9 @@ struct dc_stream_state {
 
 	bool has_non_synchronizable_pclk;
 	bool vblank_synchronized;
+#ifdef CONFIG_DRM_AMD_DC_DCN
+	struct mall_stream_config mall_stream_config;
+#endif
 };
 
 #define ABM_LEVEL_IMMEDIATE_DISABLE 255
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
index b699d1b2ba83c..e6c06325742a0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
@@ -128,6 +128,21 @@
 	SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
 	NBIO_SR(BIOS_SCRATCH_2)
 
+#define ABM_DCN32_REG_LIST(id)\
+	SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
+	SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
+	SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
+	SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
+	SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
+	SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
+	SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
+	SRI(BL1_PWM_USER_LEVEL, ABM, id), \
+	SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
+	SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
+	SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
+	SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
+	NBIO_SR(BIOS_SCRATCH_2)
+
 #define ABM_SF(reg_name, field_name, post_fix)\
 	.field_name = reg_name ## __ ## field_name ## post_fix
 
@@ -203,6 +218,36 @@
 
 #define ABM_MASK_SH_LIST_DCN30(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh)
 
+#define ABM_MASK_SH_LIST_DCN32(mask_sh) \
+	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
+			ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
+	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
+			ABM1_HG_VMAX_SEL, mask_sh), \
+	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
+			ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
+	ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
+			ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
+	ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
+			ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
+	ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
+			ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
+	ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
+			BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
+	ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
+			BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
+	ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
+			BL1_PWM_USER_LEVEL, mask_sh), \
+	ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
+			ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
+	ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
+			ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
+	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
+			ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
+	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
+			ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
+	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
+			ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
+
 #define ABM_REG_FIELD_LIST(type) \
 	type ABM1_HG_NUM_OF_BINS_SEL; \
 	type ABM1_HG_VMAX_SEL; \
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
index 9eec3524335fb..e0c390fcc12ce 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
@@ -164,6 +164,10 @@
 	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
 	CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
 
+#define CS_COMMON_MASK_SH_LIST_DCN3_2(mask_sh)\
+	CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh),\
+	CS_SF(OTG0_PIXEL_RATE_CNTL, PIPE0_DTO_SRC_SEL, mask_sh)
+
 #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \
 		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
 		SRII(PHASE, DP_DTO, 0),\
@@ -197,12 +201,23 @@
 	type DP_DTO0_MODULO; \
 	type DP_DTO0_ENABLE;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+#define CS_REG_FIELD_LIST_DCN32(type) \
+	type PIPE0_DTO_SRC_SEL;
+#endif
+
 struct dce110_clk_src_shift {
 	CS_REG_FIELD_LIST(uint8_t)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	CS_REG_FIELD_LIST_DCN32(uint8_t)
+#endif
 };
 
 struct dce110_clk_src_mask{
 	CS_REG_FIELD_LIST(uint32_t)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	CS_REG_FIELD_LIST_DCN32(uint32_t)
+#endif
 };
 
 struct dce110_clk_src_regs {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
index 39485bdeb90ec..e48fd044f5720 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
@@ -158,8 +158,39 @@ struct dcn_hubbub_registers {
 	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C;
 	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D;
 	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D;
+	uint32_t DCHUBBUB_ARB_USR_RETRAINING_CNTL;
+	uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A;
+	uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B;
+	uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C;
+	uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D;
+	uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A;
+	uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B;
+	uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C;
+	uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D;
+	uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A;
+	uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B;
+	uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C;
+	uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D;
 };
 
+#define HUBBUB_REG_FIELD_LIST_DCN32(type) \
+		type DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE;\
+		type DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE;\
+		type DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST;\
+		type DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE;\
+		type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A;\
+		type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B;\
+		type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C;\
+		type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D;\
+		type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A;\
+		type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B;\
+		type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C;\
+		type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D;\
+		type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A;\
+		type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B;\
+		type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C;\
+		type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D
+
 /* set field name */
 #define HUBBUB_SF(reg_name, field_name, post_fix)\
 	.field_name = reg_name ## __ ## field_name ## post_fix
@@ -337,6 +368,7 @@ struct dcn_hubbub_shift {
 	HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t);
 	HUBBUB_HVM_REG_FIELD_LIST(uint8_t);
 	HUBBUB_RET_REG_FIELD_LIST(uint8_t);
+	HUBBUB_REG_FIELD_LIST_DCN32(uint8_t);
 };
 
 struct dcn_hubbub_mask {
@@ -344,6 +376,7 @@ struct dcn_hubbub_mask {
 	HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t);
 	HUBBUB_HVM_REG_FIELD_LIST(uint32_t);
 	HUBBUB_RET_REG_FIELD_LIST(uint32_t);
+	HUBBUB_REG_FIELD_LIST_DCN32(uint32_t);
 };
 
 struct dc;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index e3a62873c0e70..1cb206dc83526 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1375,11 +1375,6 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
 		pipe_ctx->stream_res.tg = NULL;
 		pipe_ctx->plane_res.hubp = NULL;
 
-		if (tg->funcs->is_tg_enabled(tg)) {
-			if (tg->funcs->init_odm)
-				tg->funcs->init_odm(tg);
-		}
-
 		tg->funcs->tg_init(tg);
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index c50c29984d51d..df155cc2bfea0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -514,6 +514,7 @@ struct dcn_optc_registers {
 	type DIG_UPDATE_POSITION_X;\
 	type DIG_UPDATE_POSITION_Y;\
 	type OTG_H_TIMING_DIV_MODE;\
+	type OTG_H_TIMING_DIV_MODE_MANUAL;\
 	type OTG_DRR_TIMING_DBUF_UPDATE_MODE;\
 	type OTG_CRC_DSC_MODE;\
 	type OTG_CRC_DATA_STREAM_COMBINE_MODE;\
@@ -553,6 +554,7 @@ struct optc {
 	int vupdate_offset;
 	int vupdate_width;
 	int vready_offset;
+	struct dc_crtc_timing orginal_patched_timing;
 	enum signal_type signal;
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index 293595a339821..02c77076fa499 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -73,6 +73,7 @@
 	SRI(HDMI_ACR_48_1, DIG, id),\
 	SRI(DP_DB_CNTL, DP, id), \
 	SRI(DP_MSA_MISC, DP, id), \
+	SRI(DP_MSA_VBID_MISC, DP, id), \
 	SRI(DP_MSA_COLORIMETRY, DP, id), \
 	SRI(DP_MSA_TIMING_PARAM1, DP, id), \
 	SRI(DP_MSA_TIMING_PARAM2, DP, id), \
@@ -186,6 +187,7 @@ struct dcn10_stream_enc_registers {
 	uint32_t HDMI_GENERIC_PACKET_CONTROL9;
 	uint32_t HDMI_GENERIC_PACKET_CONTROL10;
 	uint32_t DIG_CLOCK_PATTERN;
+	uint32_t DIG_FIFO_CTRL0;
 };
 
 
@@ -337,8 +339,14 @@ struct dcn10_stream_enc_registers {
 	SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh),\
 	SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh)
 
+#if defined(CONFIG_DRM_AMD_DC_HDCP)
+#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
+	SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh),\
+	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh)
+#else
 #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
 	SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)
+#endif
 
 #define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\
 	SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
@@ -567,16 +575,33 @@ struct dcn10_stream_enc_registers {
 	type DP_SEC_GSP11_ENABLE;\
 	type DP_SEC_GSP11_LINE_NUM
 
+#define SE_REG_FIELD_LIST_DCN3_2(type) \
+	type DIG_SYMCLK_FE_ON;\
+	type DIG_FIFO_READ_START_LEVEL;\
+	type DIG_FIFO_ENABLE;\
+	type DIG_FIFO_RESET;\
+	type DIG_FIFO_RESET_DONE
+
 struct dcn10_stream_encoder_shift {
 	SE_REG_FIELD_LIST_DCN1_0(uint8_t);
+#if defined(CONFIG_DRM_AMD_DC_HDCP)
+	uint8_t HDMI_ACP_SEND;
+#endif
 	SE_REG_FIELD_LIST_DCN2_0(uint8_t);
 	SE_REG_FIELD_LIST_DCN3_0(uint8_t);
+	SE_REG_FIELD_LIST_DCN3_2(uint8_t);
+
 };
 
 struct dcn10_stream_encoder_mask {
 	SE_REG_FIELD_LIST_DCN1_0(uint32_t);
+#if defined(CONFIG_DRM_AMD_DC_HDCP)
+	uint32_t HDMI_ACP_SEND;
+#endif
 	SE_REG_FIELD_LIST_DCN2_0(uint32_t);
 	SE_REG_FIELD_LIST_DCN3_0(uint32_t);
+	SE_REG_FIELD_LIST_DCN3_2(uint32_t);
+
 };
 
 struct dcn10_stream_encoder {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index b3c9a9724efdd..2b9d3e63191b2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -133,6 +133,8 @@
 	type OTG_DROP_PIXEL[MAX_PIPES];
 
 #define DCCG3_REG_FIELD_LIST(type) \
+	type HDMICHARCLK0_EN;\
+	type HDMICHARCLK0_SRC_SEL;\
 	type PHYASYMCLK_FORCE_EN;\
 	type PHYASYMCLK_FORCE_SRC_SEL;\
 	type PHYBSYMCLK_FORCE_EN;\
@@ -203,16 +205,45 @@
 	type PHYDSYMCLK_GATE_DISABLE; \
 	type PHYESYMCLK_GATE_DISABLE;
 
+#define DCCG32_REG_FIELD_LIST(type) \
+	type DPSTREAMCLK0_EN;\
+	type DPSTREAMCLK1_EN;\
+	type DPSTREAMCLK2_EN;\
+	type DPSTREAMCLK3_EN;\
+	type DPSTREAMCLK0_SRC_SEL;\
+	type DPSTREAMCLK1_SRC_SEL;\
+	type DPSTREAMCLK2_SRC_SEL;\
+	type DPSTREAMCLK3_SRC_SEL;\
+	type HDMISTREAMCLK0_EN;\
+	type OTG0_PIXEL_RATE_DIVK1;\
+	type OTG0_PIXEL_RATE_DIVK2;\
+	type OTG1_PIXEL_RATE_DIVK1;\
+	type OTG1_PIXEL_RATE_DIVK2;\
+	type OTG2_PIXEL_RATE_DIVK1;\
+	type OTG2_PIXEL_RATE_DIVK2;\
+	type OTG3_PIXEL_RATE_DIVK1;\
+	type OTG3_PIXEL_RATE_DIVK2;\
+	type DTBCLK_P0_SRC_SEL;\
+	type DTBCLK_P0_EN;\
+	type DTBCLK_P1_SRC_SEL;\
+	type DTBCLK_P1_EN;\
+	type DTBCLK_P2_SRC_SEL;\
+	type DTBCLK_P2_EN;\
+	type DTBCLK_P3_SRC_SEL;\
+	type DTBCLK_P3_EN;
+
 struct dccg_shift {
 	DCCG_REG_FIELD_LIST(uint8_t)
 	DCCG3_REG_FIELD_LIST(uint8_t)
 	DCCG31_REG_FIELD_LIST(uint8_t)
+	DCCG32_REG_FIELD_LIST(uint8_t)
 };
 
 struct dccg_mask {
 	DCCG_REG_FIELD_LIST(uint32_t)
 	DCCG3_REG_FIELD_LIST(uint32_t)
 	DCCG31_REG_FIELD_LIST(uint32_t)
+	DCCG32_REG_FIELD_LIST(uint32_t)
 };
 
 struct dccg_registers {
@@ -247,7 +278,8 @@ struct dccg_registers {
 	uint32_t DCCG_GATE_DISABLE_CNTL3;
 	uint32_t HDMISTREAMCLK0_DTO_PARAM;
 	uint32_t DCCG_GATE_DISABLE_CNTL4;
-
+	uint32_t OTG_PIXEL_RATE_DIV;
+	uint32_t DTBCLK_P_CNTL;
 };
 
 struct dcn_dccg {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
index 9204c3ef323b2..efa2adf4f83dd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
@@ -161,6 +161,12 @@
 	DCN21_HUBP_REG_COMMON_VARIABLE_LIST;\
 	uint32_t DCN_DMDATA_VM_CNTL
 
+#define DCN32_HUBP_REG_COMMON_VARIABLE_LIST \
+	DCN30_HUBP_REG_COMMON_VARIABLE_LIST;\
+	uint32_t DCHUBP_MALL_CONFIG;\
+	uint32_t DCHUBP_VMPG_CONFIG;\
+	uint32_t UCLK_PSTATE_FORCE
+
 #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \
 	DCN_HUBP_REG_FIELD_BASE_LIST(type); \
 	type DMDATA_ADDRESS_HIGH;\
@@ -222,16 +228,29 @@
 	type CURSOR_REQ_MODE;\
 	type HUBP_SOFT_RESET
 
+#define DCN32_HUBP_REG_FIELD_VARIABLE_LIST(type) \
+	DCN31_HUBP_REG_FIELD_VARIABLE_LIST(type);\
+	type USE_MALL_SEL; \
+	type USE_MALL_FOR_CURSOR;\
+	type VMPG_SIZE; \
+	type PTE_BUFFER_MODE; \
+	type BIGK_FRAGMENT_SIZE; \
+	type FORCE_ONE_ROW_FOR_FRAME; \
+	type DATA_UCLK_PSTATE_FORCE_EN; \
+	type DATA_UCLK_PSTATE_FORCE_VALUE; \
+	type CURSOR_UCLK_PSTATE_FORCE_EN; \
+	type CURSOR_UCLK_PSTATE_FORCE_VALUE
+
 struct dcn_hubp2_registers {
-	DCN30_HUBP_REG_COMMON_VARIABLE_LIST;
+	DCN32_HUBP_REG_COMMON_VARIABLE_LIST;
 };
 
 struct dcn_hubp2_shift {
-	DCN31_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
+	DCN32_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
 };
 
 struct dcn_hubp2_mask {
-	DCN31_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
+	DCN32_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
 };
 
 struct dcn20_hubp {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index ec6aa8d8b251a..d00a27893ab02 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -768,6 +768,10 @@ enum dc_status dcn20_enable_stream_timing(
 	/* TODO enable stream if timing changed */
 	/* TODO unblank stream if DP */
 
+	if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) {
+		if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)
+			pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);
+	}
 	return DC_OK;
 }
 
@@ -1247,6 +1251,16 @@ void dcn20_pipe_control_lock(
 					lock,
 					&hw_locks,
 					&inst_flags);
+	} else if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
+		union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
+		hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;
+		hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;
+		hw_lock_cmd.bits.lock_pipe = 1;
+		hw_lock_cmd.bits.otg_inst = pipe->stream_res.tg->inst;
+		hw_lock_cmd.bits.lock = lock;
+		if (!lock)
+			hw_lock_cmd.bits.should_release = 1;
+		dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);
 	} else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
 		if (lock)
 			pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
@@ -1564,10 +1578,12 @@ static void dcn20_update_dchubp_dpp(
 		plane_state->update_flags.bits.addr_update)
 		hws->funcs.update_plane_addr(dc, pipe_ctx);
 
-
-
 	if (pipe_ctx->update_flags.bits.enable)
 		hubp->funcs->set_blank(hubp, false);
+	/* If the stream paired with this plane is phantom, the plane is also phantom */
+	if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM
+			&& hubp->funcs->phantom_hubp_post_enable)
+		hubp->funcs->phantom_hubp_post_enable(hubp);
 }
 
 
@@ -1578,6 +1594,7 @@ static void dcn20_program_pipe(
 {
 	struct dce_hwseq *hws = dc->hwseq;
 	/* Only need to unblank on top pipe */
+
 	if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
 			&& !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
 		hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
@@ -1585,7 +1602,6 @@ static void dcn20_program_pipe(
 	/* Only update TG on top pipe */
 	if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe
 			&& !pipe_ctx->prev_odm_pipe) {
-
 		pipe_ctx->stream_res.tg->funcs->program_global_sync(
 				pipe_ctx->stream_res.tg,
 				pipe_ctx->pipe_dlg_param.vready_offset,
@@ -1593,7 +1609,12 @@ static void dcn20_program_pipe(
 				pipe_ctx->pipe_dlg_param.vupdate_offset,
 				pipe_ctx->pipe_dlg_param.vupdate_width);
 
-		pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
+		if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) {
+			pipe_ctx->stream_res.tg->funcs->wait_for_state(
+				pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
+			pipe_ctx->stream_res.tg->funcs->wait_for_state(
+				pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
+		}
 
 		pipe_ctx->stream_res.tg->funcs->set_vtg_params(
 				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
@@ -1749,6 +1770,8 @@ void dcn20_program_front_end_for_ctx(
 			pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp);
 		}
 	}
+	if (hws->funcs.program_mall_pipe_config)
+		hws->funcs.program_mall_pipe_config(dc, context);
 }
 
 void dcn20_post_unlock_program_front_end(
@@ -2409,6 +2432,7 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 			NULL,
 			hubp->inst,
 			mpcc_id);
+
 	dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
 
 	ASSERT(new_mpcc != NULL);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
index a04ca4a983925..b683ad8171067 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
@@ -195,7 +195,7 @@ static void enc3_update_hdmi_info_packet(
 	}
 }
 
-static void enc3_stream_encoder_update_hdmi_info_packets(
+void enc3_stream_encoder_update_hdmi_info_packets(
 	struct stream_encoder *enc,
 	const struct encoder_info_frame *info_frame)
 {
@@ -214,7 +214,7 @@ static void enc3_stream_encoder_update_hdmi_info_packets(
 	enc3_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd);
 }
 
-static void enc3_stream_encoder_stop_hdmi_info_packets(
+void enc3_stream_encoder_stop_hdmi_info_packets(
 	struct stream_encoder *enc)
 {
 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
@@ -318,7 +318,7 @@ static void enc3_dp_set_dsc_config(struct stream_encoder *enc,
 }
 
 
-static void enc3_dp_set_dsc_pps_info_packet(struct stream_encoder *enc,
+void enc3_dp_set_dsc_pps_info_packet(struct stream_encoder *enc,
 					bool enable,
 					uint8_t *dsc_packed_pps,
 					bool immediate_update)
@@ -404,7 +404,7 @@ static void enc3_read_state(struct stream_encoder *enc, struct enc_state *s)
 	}
 }
 
-static void enc3_stream_encoder_update_dp_info_packets(
+void enc3_stream_encoder_update_dp_info_packets(
 	struct stream_encoder *enc,
 	const struct encoder_info_frame *info_frame)
 {
@@ -652,7 +652,7 @@ static void enc3_stream_encoder_hdmi_set_stream_attribute(
 	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
 }
 
-static void enc3_audio_mute_control(
+void enc3_audio_mute_control(
 	struct stream_encoder *enc,
 	bool mute)
 {
@@ -660,7 +660,7 @@ static void enc3_audio_mute_control(
 	enc->afmt->funcs->audio_mute_control(enc->afmt, mute);
 }
 
-static void enc3_se_dp_audio_setup(
+void enc3_se_dp_audio_setup(
 	struct stream_encoder *enc,
 	unsigned int az_inst,
 	struct audio_info *info)
@@ -691,7 +691,7 @@ static void enc3_se_setup_dp_audio(
 	enc->afmt->funcs->setup_dp_audio(enc->afmt);
 }
 
-static void enc3_se_dp_audio_enable(
+void enc3_se_dp_audio_enable(
 	struct stream_encoder *enc)
 {
 	enc1_se_enable_audio_clock(enc, true);
@@ -757,7 +757,7 @@ static void enc3_se_setup_hdmi_audio(
 	 */
 }
 
-static void enc3_se_hdmi_audio_setup(
+void enc3_se_hdmi_audio_setup(
 	struct stream_encoder *enc,
 	unsigned int az_inst,
 	struct audio_info *info,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h
index 42140e73c3b24..d2207b35f15f4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h
@@ -287,4 +287,39 @@ void dcn30_dio_stream_encoder_construct(
 	const struct dcn10_stream_encoder_shift *se_shift,
 	const struct dcn10_stream_encoder_mask *se_mask);
 
+void enc3_stream_encoder_update_hdmi_info_packets(
+	struct stream_encoder *enc,
+	const struct encoder_info_frame *info_frame);
+
+void enc3_stream_encoder_stop_hdmi_info_packets(
+	struct stream_encoder *enc);
+
+void enc3_stream_encoder_update_dp_info_packets(
+	struct stream_encoder *enc,
+	const struct encoder_info_frame *info_frame);
+
+void enc3_audio_mute_control(
+	struct stream_encoder *enc,
+	bool mute);
+
+void enc3_se_dp_audio_setup(
+	struct stream_encoder *enc,
+	unsigned int az_inst,
+	struct audio_info *info);
+
+void enc3_se_dp_audio_enable(
+	struct stream_encoder *enc);
+
+void enc3_se_hdmi_audio_setup(
+	struct stream_encoder *enc,
+	unsigned int az_inst,
+	struct audio_info *info,
+	struct audio_crtc_info *audio_crtc_info);
+
+void enc3_dp_set_dsc_pps_info_packet(
+	struct stream_encoder *enc,
+	bool enable,
+	uint8_t *dsc_packed_pps,
+    bool immediate_update);
+
 #endif /* __DC_DIO_STREAM_ENCODER_DCN30_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
index ab3918c0a15b0..9cca59bf2ae0a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
@@ -41,9 +41,9 @@
 	dpp->tf_shift->field_name, dpp->tf_mask->field_name
 
 
-static void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)
+void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)
 {
-	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
+	struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 
 	REG_GET(DPP_CONTROL,
 			DPP_CLOCK_ENABLE, &s->is_enabled);
@@ -167,7 +167,7 @@ void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined t
 			PRE_DEGAM_SELECT, degamma_lut_selection);
 }
 
-static void dpp3_cnv_setup (
+void dpp3_cnv_setup (
 		struct dpp *dpp_base,
 		enum surface_pixel_format format,
 		enum expansion_mode mode,
@@ -372,7 +372,7 @@ void dpp3_set_cursor_attributes(
 }
 
 
-static bool dpp3_get_optimal_number_of_taps(
+bool dpp3_get_optimal_number_of_taps(
 		struct dpp *dpp,
 		struct scaler_data *scl_data,
 		const struct scaling_taps *in_taps)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
index ac644ae6b9f26..6263408d71fca 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
@@ -588,6 +588,22 @@ void dpp3_program_CM_dealpha(
 		struct dpp *dpp_base,
 		uint32_t enable, uint32_t additive_blending);
 
+void dpp30_read_state(struct dpp *dpp_base,
+		struct dcn_dpp_state *s);
+
+bool dpp3_get_optimal_number_of_taps(
+		struct dpp *dpp,
+		struct scaler_data *scl_data,
+		const struct scaling_taps *in_taps);
+
+void dpp3_cnv_setup (
+		struct dpp *dpp_base,
+		enum surface_pixel_format format,
+		enum expansion_mode mode,
+		struct dc_csc_transform input_csc_color_matrix,
+		enum dc_color_space input_color_space,
+		struct cnv_alpha_2bit_lut *alpha_2bit_lut);
+
 void dpp3_program_CM_bias(
 		struct dpp *dpp_base,
 		struct CM_bias_params *bias_params);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
index 0ce0d6165f43a..1981a71b961b7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
@@ -44,7 +44,7 @@
 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
 
 
-static bool mpc3_is_dwb_idle(
+bool mpc3_is_dwb_idle(
 	struct mpc *mpc,
 	int dwb_id)
 {
@@ -59,7 +59,7 @@ static bool mpc3_is_dwb_idle(
 		return false;
 }
 
-static void mpc3_set_dwb_mux(
+void mpc3_set_dwb_mux(
 	struct mpc *mpc,
 	int dwb_id,
 	int mpcc_id)
@@ -70,7 +70,7 @@ static void mpc3_set_dwb_mux(
 		MPC_DWB0_MUX, mpcc_id);
 }
 
-static void mpc3_disable_dwb_mux(
+void mpc3_disable_dwb_mux(
 	struct mpc *mpc,
 	int dwb_id)
 {
@@ -80,7 +80,7 @@ static void mpc3_disable_dwb_mux(
 		MPC_DWB0_MUX, 0xf);
 }
 
-static void mpc3_set_out_rate_control(
+void mpc3_set_out_rate_control(
 	struct mpc *mpc,
 	int opp_id,
 	bool enable,
@@ -99,7 +99,7 @@ static void mpc3_set_out_rate_control(
 			MPC_OUT_FLOW_CONTROL_COUNT, flow_control->flow_ctrl_cnt1);
 }
 
-static enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id)
+enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id)
 {
 	/*Contrary to DCN2 and DCN1 wherein a single status register field holds this info;
 	 *in DCN3/3AG, we need to read two separate fields to retrieve the same info
@@ -137,7 +137,7 @@ static enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id)
 		return mode;
 }
 
-static void mpc3_power_on_ogam_lut(
+void mpc3_power_on_ogam_lut(
 		struct mpc *mpc, int mpcc_id,
 		bool power_on)
 {
@@ -1035,7 +1035,7 @@ static void mpc3_set3dlut_ram10(
 }
 
 
-static void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
+void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
 {
 	mpcc->mpcc_id = mpcc_inst;
 	mpcc->dpp_id = 0xf;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h
index 34b9cedbd0129..a4d8f77d43bc9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h
@@ -282,6 +282,73 @@
 	uint32_t MPCC_OGAM_RAMB_START_BASE_CNTL_R[MAX_MPCC]; \
 	uint32_t MPC_OUT_CSC_COEF_FORMAT
 
+#define MPC_REG_VARIABLE_LIST_DCN32 \
+	uint32_t MPCC_MCM_SHAPER_CONTROL[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_OFFSET_R[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_OFFSET_G[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_OFFSET_B[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_SCALE_R[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_SCALE_G_B[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_LUT_INDEX[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_LUT_DATA[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_START_CNTL_B[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_START_CNTL_G[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_START_CNTL_R[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_END_CNTL_B[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_END_CNTL_G[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_END_CNTL_R[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_0_1[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_2_3[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_4_5[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_6_7[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_8_9[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_10_11[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_12_13[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_14_15[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_16_17[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_18_19[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_20_21[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_22_23[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_24_25[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_26_27[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_28_29[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_30_31[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_32_33[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_START_CNTL_B[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_START_CNTL_G[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_START_CNTL_R[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_END_CNTL_B[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_END_CNTL_G[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_END_CNTL_R[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_0_1[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_2_3[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_4_5[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_6_7[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_8_9[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_10_11[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_12_13[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_14_15[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_16_17[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_18_19[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_20_21[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_22_23[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_24_25[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_26_27[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_28_29[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_30_31[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_32_33[MAX_MPCC]; \
+	uint32_t MPCC_MCM_3DLUT_MODE[MAX_MPCC]; \
+	uint32_t MPCC_MCM_3DLUT_INDEX[MAX_MPCC]; \
+	uint32_t MPCC_MCM_3DLUT_DATA[MAX_MPCC]; \
+	uint32_t MPCC_MCM_3DLUT_DATA_30BIT[MAX_MPCC]; \
+	uint32_t MPCC_MCM_3DLUT_READ_WRITE_CONTROL[MAX_MPCC]; \
+	uint32_t MPCC_MCM_3DLUT_OUT_NORM_FACTOR[MAX_MPCC]; \
+	uint32_t MPCC_MCM_3DLUT_OUT_OFFSET_R[MAX_MPCC]; \
+	uint32_t MPCC_MCM_3DLUT_OUT_OFFSET_G[MAX_MPCC]; \
+	uint32_t MPCC_MCM_3DLUT_OUT_OFFSET_B[MAX_MPCC]; \
+	uint32_t MPCC_MCM_MEM_PWR_CTRL[MAX_MPCC]
+
 #define MPC_COMMON_MASK_SH_LIST_DCN3_0(mask_sh) \
 	MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\
 	SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
@@ -580,6 +647,53 @@
 	type MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS;\
 	type MPC_RMU_SHAPER_MODE_CURRENT
 
+#define MPC_REG_FIELD_LIST_DCN32(type) \
+	type MPCC_MCM_SHAPER_MEM_PWR_FORCE;\
+	type MPCC_MCM_SHAPER_MEM_PWR_DIS;\
+	type MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE;\
+	type MPCC_MCM_3DLUT_MEM_PWR_FORCE;\
+	type MPCC_MCM_3DLUT_MEM_PWR_DIS;\
+	type MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE;\
+	type MPCC_MCM_1DLUT_MEM_PWR_FORCE;\
+	type MPCC_MCM_1DLUT_MEM_PWR_DIS;\
+	type MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE;\
+	type MPCC_MCM_SHAPER_MEM_PWR_STATE;\
+	type MPCC_MCM_3DLUT_MEM_PWR_STATE;\
+	type MPCC_MCM_1DLUT_MEM_PWR_STATE;\
+	type MPCC_MCM_3DLUT_MODE; \
+	type MPCC_MCM_3DLUT_SIZE; \
+	type MPCC_MCM_3DLUT_MODE_CURRENT; \
+	type MPCC_MCM_3DLUT_WRITE_EN_MASK;\
+	type MPCC_MCM_3DLUT_RAM_SEL;\
+	type MPCC_MCM_3DLUT_30BIT_EN;\
+	type MPCC_MCM_3DLUT_CONFIG_STATUS;\
+	type MPCC_MCM_3DLUT_READ_SEL;\
+	type MPCC_MCM_3DLUT_INDEX;\
+	type MPCC_MCM_3DLUT_DATA0;\
+	type MPCC_MCM_3DLUT_DATA1;\
+	type MPCC_MCM_3DLUT_DATA_30BIT;\
+	type MPCC_MCM_SHAPER_LUT_MODE;\
+	type MPCC_MCM_SHAPER_MODE_CURRENT;\
+	type MPCC_MCM_SHAPER_OFFSET_R;\
+	type MPCC_MCM_SHAPER_OFFSET_G;\
+	type MPCC_MCM_SHAPER_OFFSET_B;\
+	type MPCC_MCM_SHAPER_SCALE_R;\
+	type MPCC_MCM_SHAPER_SCALE_G;\
+	type MPCC_MCM_SHAPER_SCALE_B;\
+	type MPCC_MCM_SHAPER_LUT_INDEX;\
+	type MPCC_MCM_SHAPER_LUT_DATA;\
+	type MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK;\
+	type MPCC_MCM_SHAPER_LUT_WRITE_SEL;\
+	type MPCC_MCM_SHAPER_CONFIG_STATUS;\
+	type MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B;\
+	type MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B;\
+	type MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B;\
+	type MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B;\
+	type MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET;\
+	type MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS;\
+	type MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET;\
+	type MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS
+
 #define MPC_COMMON_MASK_SH_LIST_DCN303(mask_sh) \
 	MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\
 	SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
@@ -758,14 +872,17 @@
 
 struct dcn30_mpc_registers {
 	MPC_REG_VARIABLE_LIST_DCN3_0;
+	MPC_REG_VARIABLE_LIST_DCN32;
 };
 
 struct dcn30_mpc_shift {
 	MPC_REG_FIELD_LIST_DCN3_0(uint8_t);
+	MPC_REG_FIELD_LIST_DCN32(uint8_t);
 };
 
 struct dcn30_mpc_mask {
 	MPC_REG_FIELD_LIST_DCN3_0(uint32_t);
+	MPC_REG_FIELD_LIST_DCN32(uint32_t);
 };
 
 struct dcn30_mpc {
@@ -841,4 +958,34 @@ void mpc3_set_rmu_mux(
 	int rmu_idx,
 	int value);
 
+void mpc3_set_dwb_mux(
+	struct mpc *mpc,
+	int dwb_id,
+	int mpcc_id);
+
+void mpc3_disable_dwb_mux(
+	struct mpc *mpc,
+	int dwb_id);
+
+bool mpc3_is_dwb_idle(
+	struct mpc *mpc,
+	int dwb_id);
+
+void mpc3_set_out_rate_control(
+	struct mpc *mpc,
+	int opp_id,
+	bool enable,
+	bool rate_2x_mode,
+	struct mpc_dwb_flow_control *flow_control);
+
+void mpc3_power_on_ogam_lut(
+	struct mpc *mpc, int mpcc_id,
+	bool power_on);
+
+void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst);
+
+enum dc_lut_mode mpc3_get_ogam_current(
+	struct mpc *mpc,
+	int mpcc_id);
+
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
index 97f11ef6e9f02..33bd12f5dc174 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
@@ -28,6 +28,7 @@
 
 #include "dcn20/dcn20_optc.h"
 
+#define V_TOTAL_REGS_DCN30_SRI(inst)
 
 #define OPTC_COMMON_REG_LIST_DCN3_BASE(inst) \
 	SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
@@ -55,6 +56,7 @@
 	SRI(OTG_V_TOTAL_MAX, OTG, inst),\
 	SRI(OTG_V_TOTAL_MIN, OTG, inst),\
 	SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
+	V_TOTAL_REGS_DCN30_SRI(inst)\
 	SRI(OTG_TRIGA_CNTL, OTG, inst),\
 	SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
 	SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
@@ -80,6 +82,7 @@
 	SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
 	SRI(OTG_GSL_CONTROL, OTG, inst),\
 	SRI(OTG_CRC_CNTL, OTG, inst),\
+	SRI(OTG_CRC_CNTL2, OTG, inst),\
 	SRI(OTG_CRC0_DATA_RG, OTG, inst),\
 	SRI(OTG_CRC0_DATA_B, OTG, inst),\
 	SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
@@ -108,6 +111,7 @@
 	SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
 	SR(DWB_SOURCE_SELECT)
 
+#define DCN30_VTOTAL_REGS_SF(mask_sh)
 
 #define OPTC_COMMON_MASK_SH_LIST_DCN3_BASE(mask_sh)\
 	SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
@@ -161,6 +165,7 @@
 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\
 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
+	DCN30_VTOTAL_REGS_SF(mask_sh)\
 	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
 	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
 	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
@@ -219,6 +224,10 @@
 	SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
 	SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
 	SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
 	SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
 	SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
 	SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 4519ecef2e7b7..13dbf99af2205 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -158,10 +158,9 @@ static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst)
 	}
 }
 
-void dccg31_set_dpstreamclk(
-		struct dccg *dccg,
-		enum hdmistreamclk_source src,
-		int otg_inst)
+void dccg31_set_dpstreamclk(struct dccg *dccg,
+			    enum streamclk_source src,
+			    int otg_inst)
 {
 	if (src == REFCLK)
 		dccg31_disable_dpstreamclk(dccg, otg_inst);
@@ -662,6 +661,24 @@ void dccg31_init(struct dccg *dccg)
 	}
 }
 
+void dccg31_otg_add_pixel(struct dccg *dccg,
+		uint32_t otg_inst)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
+			OTG_ADD_PIXEL[otg_inst], 1);
+}
+
+void dccg31_otg_drop_pixel(struct dccg *dccg,
+		uint32_t otg_inst)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
+			OTG_DROP_PIXEL[otg_inst], 1);
+}
+
 static const struct dccg_funcs dccg31_funcs = {
 	.update_dpp_dto = dccg31_update_dpp_dto,
 	.get_dccg_ref_freq = dccg31_get_dccg_ref_freq,
@@ -674,6 +691,9 @@ static const struct dccg_funcs dccg31_funcs = {
 	.set_physymclk = dccg31_set_physymclk,
 	.set_dtbclk_dto = dccg31_set_dtbclk_dto,
 	.set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,
+	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
+	.otg_add_pixel = dccg31_otg_add_pixel,
+	.otg_drop_pixel = dccg31_otg_drop_pixel,
 	.set_dispclk_change_mode = dccg31_set_dispclk_change_mode,
 	.disable_dsc = dccg31_disable_dscclk,
 	.enable_dsc = dccg31_enable_dscclk,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
index f158c1ea214b3..80bd80707991d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
@@ -28,10 +28,6 @@
 
 #include "dcn30/dcn30_dccg.h"
 
-#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\
-	.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
-
-
 #define DCCG_REG_LIST_DCN31() \
 	SR(DPPCLK_DTO_CTRL),\
 	DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
@@ -124,6 +120,10 @@
 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 1, mask_sh),\
 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 2, mask_sh),\
 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 3, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
 	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
 	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
 	DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh), \
@@ -163,7 +163,7 @@ void dccg31_init(struct dccg *dccg);
 
 void dccg31_set_dpstreamclk(
 		struct dccg *dccg,
-		enum hdmistreamclk_source src,
+		enum streamclk_source src,
 		int otg_inst);
 
 void dccg31_enable_symclk32_se(
@@ -194,8 +194,4 @@ void dccg31_set_audio_dtbclk_dto(
 		struct dccg *dccg,
 		const struct dtbclk_dto_params *params);
 
-void dccg31_set_hdmistreamclk(
-		struct dccg *dccg,
-		enum hdmistreamclk_source src);
-
 #endif //__DCN31_DCCG_H__
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
index c51f7dca94f8e..96fac715a77b4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
@@ -213,26 +213,6 @@ void optc31_set_drr(
 	}
 }
 
-void optc3_init_odm(struct timing_generator *optc)
-{
-	struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-	REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
-			OPTC_NUM_OF_INPUT_SEGMENT, 0,
-			OPTC_SEG0_SRC_SEL, optc->inst,
-			OPTC_SEG1_SRC_SEL, 0xf,
-			OPTC_SEG2_SRC_SEL, 0xf,
-			OPTC_SEG3_SRC_SEL, 0xf
-			);
-
-	REG_SET(OTG_H_TIMING_CNTL, 0,
-			OTG_H_TIMING_DIV_MODE, 0);
-
-	REG_SET(OPTC_MEMORY_CONFIG, 0,
-			OPTC_MEM_SEL, 0);
-	optc1->opp_count = 1;
-}
-
 static struct timing_generator_funcs dcn31_tg_funcs = {
 		.validate_timing = optc1_validate_timing,
 		.program_timing = optc1_program_timing,
@@ -266,6 +246,7 @@ static struct timing_generator_funcs dcn31_tg_funcs = {
 		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
 		.enable_optc_clock = optc1_enable_optc_clock,
 		.set_drr = optc31_set_drr,
+		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
 		.set_vtotal_min_max = optc1_set_vtotal_min_max,
 		.set_static_screen_control = optc1_set_static_screen_control,
 		.program_stereo = optc1_program_stereo,
@@ -292,7 +273,6 @@ static struct timing_generator_funcs dcn31_tg_funcs = {
 		.program_manual_trigger = optc2_program_manual_trigger,
 		.setup_manual_trigger = optc2_setup_manual_trigger,
 		.get_hw_timing = optc1_get_hw_timing,
-		.init_odm = optc3_init_odm,
 };
 
 void dcn31_timing_generator_init(struct optc *optc1)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
index 9e881f2ce74ba..3706e6f7880ee 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
@@ -98,7 +98,8 @@
 	SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
 	SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
 	SRI(OTG_CRC_CNTL2, OTG, inst),\
-	SR(DWB_SOURCE_SELECT)
+	SR(DWB_SOURCE_SELECT),\
+	SRI(OTG_DRR_CONTROL, OTG, inst)
 
 #define OPTC_COMMON_MASK_SH_LIST_DCN3_1(mask_sh)\
 	SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
@@ -252,7 +253,8 @@
 	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
 	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
 	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
-	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh)
+	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
+	SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
 
 void dcn31_timing_generator_init(struct optc *optc1);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
index 12633561be3f1..5609ac6d60407 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
@@ -141,52 +141,45 @@ static void dccg32_set_dtbclk_p_src(
 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
 void dccg32_set_dtbclk_dto(
 		struct dccg *dccg,
-		int otg_inst,
-		int pixclk_khz,
-		int num_odm_segments,
-		const struct dc_crtc_timing *timing)
+		const struct dtbclk_dto_params *params)
 {
 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 	/* DTO Output Rate / Pixel Rate = 1/4 */
-	int req_dtbclk_khz = pixclk_khz / 4;
+	int req_dtbclk_khz = params->pixclk_khz / 4;
 
-	if (dccg->ref_dtbclk_khz && req_dtbclk_khz) {
+	if (params->ref_dtbclk_khz && req_dtbclk_khz) {
 		uint32_t modulo, phase;
 
 		// phase / modulo = dtbclk / dtbclk ref
-		modulo = 0xffffffff;
-		phase = (((unsigned long long)modulo * req_dtbclk_khz) + dccg->ref_dtbclk_khz - 1) / dccg->ref_dtbclk_khz;
+		modulo = params->ref_dtbclk_khz * 1000;
+		phase = req_dtbclk_khz * 1000;
 
-		REG_WRITE(DTBCLK_DTO_MODULO[otg_inst], modulo);
-		REG_WRITE(DTBCLK_DTO_PHASE[otg_inst], phase);
+		REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo);
+		REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
 
-		REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
-				DTBCLK_DTO_ENABLE[otg_inst], 1);
+		REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
+				DTBCLK_DTO_ENABLE[params->otg_inst], 1);
 
-		REG_WAIT(OTG_PIXEL_RATE_CNTL[otg_inst],
-				DTBCLKDTO_ENABLE_STATUS[otg_inst], 1,
+		REG_WAIT(OTG_PIXEL_RATE_CNTL[params->otg_inst],
+				DTBCLKDTO_ENABLE_STATUS[params->otg_inst], 1,
 				1, 100);
 
 		/* program OTG_PIXEL_RATE_DIV for DIVK1 and DIVK2 fields */
-		dccg32_set_pixel_rate_div(dccg, otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);
+		dccg32_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);
 
 		/* The recommended programming sequence to enable DTBCLK DTO to generate
 		 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should
 		 * be set only after DTO is enabled
 		 */
-		REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
-				PIPE_DTO_SRC_SEL[otg_inst], 2);
-
-		dccg->dtbclk_khz[otg_inst] = req_dtbclk_khz;
+		REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
+				PIPE_DTO_SRC_SEL[params->otg_inst], 2);
 	} else {
-		REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst],
-				DTBCLK_DTO_ENABLE[otg_inst], 0,
-				PIPE_DTO_SRC_SEL[otg_inst], 1);
-
-		REG_WRITE(DTBCLK_DTO_MODULO[otg_inst], 0);
-		REG_WRITE(DTBCLK_DTO_PHASE[otg_inst], 0);
+		REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst],
+				DTBCLK_DTO_ENABLE[params->otg_inst], 0,
+				PIPE_DTO_SRC_SEL[params->otg_inst], 1);
 
-		dccg->dtbclk_khz[otg_inst] = 0;
+		REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
+		REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
 	}
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
index 62532da949137..4d7588f2ee793 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
@@ -211,8 +211,10 @@ static void enc32_stream_encoder_hdmi_set_stream_attribute(
 		HDMI_GC_SEND, 1,
 		HDMI_NULL_SEND, 1);
 
+#if defined(CONFIG_DRM_AMD_DC_HDCP)
 	/* Disable Audio Content Protection packet transmission */
 	REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);
+#endif
 
 	/* following belongs to audio */
 	/* Enable Audio InfoFrame packet transmission. */
@@ -301,6 +303,21 @@ static void enc32_stream_encoder_dp_unblank(
 
 	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
 
+	/* DIG Resync FIFO now needs to be explicitly enabled
+	 */
+	// TODO: Confirm if we need to wait for DIG_SYMCLK_FE_ON
+	REG_WAIT(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, 1, 10, 5000);
+
+	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1);
+
+	REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000);
+
+	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0);
+
+	REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000);
+
+	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);
+
 	/* wait 100us for DIG/DP logic to prime
 	 * (i.e. a few video lines)
 	 */
@@ -354,6 +371,23 @@ static void enc32_read_state(struct stream_encoder *enc, struct enc_state *s)
 	}
 }
 
+static void enc32_stream_encoder_reset_fifo(struct stream_encoder *enc)
+{
+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+	uint32_t fifo_enabled;
+
+	REG_GET(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, &fifo_enabled);
+
+	if (fifo_enabled == 0) {
+		/* reset DIG resync FIFO */
+		REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1);
+		/* TODO: fix timeout when wait for DIG_FIFO_RESET_DONE */
+		//REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 1, 100);
+		udelay(1);
+		REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0);
+		REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 1, 100);
+	}
+}
 
 static const struct stream_encoder_funcs dcn32_str_enc_funcs = {
 	.dp_set_odm_combine =
@@ -375,7 +409,7 @@ static const struct stream_encoder_funcs dcn32_str_enc_funcs = {
 	.stop_dp_info_packets =
 		enc1_stream_encoder_stop_dp_info_packets,
 	.reset_fifo =
-		enc1_stream_encoder_reset_fifo,
+		enc32_stream_encoder_reset_fifo,
 	.dp_blank =
 		enc1_stream_encoder_dp_blank,
 	.dp_unblank =
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h
index 7241080b15533..77da0a13525b9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h
@@ -89,7 +89,8 @@
 	SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
 	SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
 	SRI(DIG_FE_CNTL, DIG, id), \
-	SRI(DIG_CLOCK_PATTERN, DIG, id)
+	SRI(DIG_CLOCK_PATTERN, DIG, id), \
+	SRI(DIG_FIFO_CTRL0, DIG, id)
 
 
 #define SE_COMMON_MASK_SH_LIST_DCN32_BASE(mask_sh)\
@@ -233,12 +234,22 @@
 	SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE_REFERENCE, mask_sh),\
 	SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE, mask_sh),\
 	SE_SF(DIG0_DIG_FE_CNTL, DOLBY_VISION_EN, mask_sh),\
+	SE_SF(DIG0_DIG_FE_CNTL, DIG_SYMCLK_FE_ON, mask_sh),\
 	SE_SF(DP0_DP_SEC_FRAMING4, DP_SST_SDP_SPLITTING, mask_sh),\
-	SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh)
+	SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, mask_sh)
 
+#if defined(CONFIG_DRM_AMD_DC_HDCP)
 #define SE_COMMON_MASK_SH_LIST_DCN32(mask_sh)\
 	SE_COMMON_MASK_SH_LIST_DCN32_BASE(mask_sh),\
 	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh)
+#else
+#define SE_COMMON_MASK_SH_LIST_DCN32(mask_sh)\
+	SE_COMMON_MASK_SH_LIST_DCN32_BASE(mask_sh)
+#endif
 
 void dcn32_dio_stream_encoder_construct(
 	struct dcn10_stream_encoder *enc1,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index d0a222f1a09c0..40afd33ffec65 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -649,7 +649,7 @@ void dcn32_init_hw(struct dc *dc)
 	 * Otherwise, if taking control is not possible, we need to power
 	 * everything down.
 	 */
-	if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
+	if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.seamless_boot_edp_requested) {
 		hws->funcs.init_pipes(dc, dc->current_state);
 		if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
 			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
@@ -661,7 +661,7 @@ void dcn32_init_hw(struct dc *dc)
 	 * To avoid this, power down hardware on boot
 	 * if DIG is turned on and seamless boot not enabled
 	 */
-	if (dc->config.power_down_display_on_boot) {
+	if (dc->config.seamless_boot_edp_requested) {
 		struct dc_link *edp_links[MAX_NUM_EDP];
 		struct dc_link *edp_link;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
index f1ed25e972f29..88275ea4193cd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
@@ -91,10 +91,18 @@ static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, i
 	REG_UPDATE(OPTC_WIDTH_CONTROL,
 			OPTC_SEGMENT_WIDTH, mpcc_hactive);
 
-	REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
+	REG_UPDATE(OTG_H_TIMING_CNTL,
+			OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
 	optc1->opp_count = opp_cnt;
 }
 
+static void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	REG_UPDATE(OTG_H_TIMING_CNTL,
+			OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0);
+}
 /**
  * Enable CRTC
  * Enable CRTC - call ASIC Control Object to enable Timing generator.
@@ -157,6 +165,29 @@ void optc32_phantom_crtc_post_enable(struct timing_generator *optc)
 	REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
 }
 
+static void optc32_set_odm_bypass(struct timing_generator *optc,
+		const struct dc_crtc_timing *dc_crtc_timing)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+	enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
+
+	REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
+			OPTC_NUM_OF_INPUT_SEGMENT, 0,
+			OPTC_SEG0_SRC_SEL, optc->inst,
+			OPTC_SEG1_SRC_SEL, 0xf,
+			OPTC_SEG2_SRC_SEL, 0xf,
+			OPTC_SEG3_SRC_SEL, 0xf
+			);
+
+	h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
+	REG_UPDATE(OTG_H_TIMING_CNTL,
+			OTG_H_TIMING_DIV_MODE, h_div);
+
+	REG_SET(OPTC_MEMORY_CONFIG, 0,
+			OPTC_MEM_SEL, 0);
+	optc1->opp_count = 1;
+}
+
 
 static struct timing_generator_funcs dcn32_tg_funcs = {
 		.validate_timing = optc1_validate_timing,
@@ -206,8 +237,9 @@ static struct timing_generator_funcs dcn32_tg_funcs = {
 		.set_dsc_config = optc3_set_dsc_config,
 		.get_dsc_status = optc2_get_dsc_status,
 		.set_dwb_source = NULL,
-		.set_odm_bypass = optc3_set_odm_bypass,
+		.set_odm_bypass = optc32_set_odm_bypass,
 		.set_odm_combine = optc32_set_odm_combine,
+		.set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode,
 		.get_optc_source = optc2_get_optc_source,
 		.set_out_mux = optc3_set_out_mux,
 		.set_drr_trigger_window = optc3_set_drr_trigger_window,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 17a287bc89ce8..7ac6428aae52b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -77,7 +77,7 @@
 
 #include "dcn/dcn_3_2_0_offset.h"
 #include "dcn/dcn_3_2_0_sh_mask.h"
-#include "dcn/nbio_4_3_0_offset.h"
+#include "nbio/nbio_4_3_0_offset.h"
 
 #include "reg_helper.h"
 #include "dce/dmub_abm.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index f79dd40f8d811..8d4c74b0fc900 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -811,9 +811,14 @@ void dcn20_calculate_dlg_params(
 		pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 		pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 		pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
-		context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;
-		context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
-
+		if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
+			// Phantom pipe requires that DET_SIZE = 0 and no unbounded requests
+			context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;
+			context->res_ctx.pipe_ctx[i].unbounded_req = false;
+		} else {
+			context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;
+			context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
+		}
 		if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
 			context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
 		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
@@ -1013,6 +1018,31 @@ int dcn20_populate_dml_pipes_from_context(
 			pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
 		pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
 		pipes[pipe_cnt].dout.dp_lanes = 4;
+		if (res_ctx->pipe_ctx[i].stream->link) {
+			switch (res_ctx->pipe_ctx[i].stream->link->cur_link_settings.link_rate) {
+			case LINK_RATE_HIGH:
+				pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr;
+				break;
+			case LINK_RATE_HIGH2:
+				pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr2;
+				break;
+			case LINK_RATE_HIGH3:
+				pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr3;
+				break;
+			case LINK_RATE_UHBR10:
+				pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_uhbr10;
+				break;
+			case LINK_RATE_UHBR13_5:
+				pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_uhbr13p5;
+				break;
+			case LINK_RATE_UHBR20:
+				pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_uhbr20;
+				break;
+			default:
+				pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_na;
+				break;
+			}
+		}
 		pipes[pipe_cnt].dout.is_virtual = 0;
 		pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
 		pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
@@ -1070,6 +1100,7 @@ int dcn20_populate_dml_pipes_from_context(
 			pipes[pipe_cnt].dout.is_virtual = 1;
 			pipes[pipe_cnt].dout.output_type = dm_dp;
 			pipes[pipe_cnt].dout.dp_lanes = 4;
+			pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr2;
 		}
 
 		switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
@@ -1138,7 +1169,8 @@ int dcn20_populate_dml_pipes_from_context(
 		 * bw calculations due to cursor on/off
 		 */
 		if (res_ctx->pipe_ctx[i].plane_state &&
-				res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
+				(res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE ||
+				 res_ctx->pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM))
 			pipes[pipe_cnt].pipe.src.num_cursors = 0;
 		else
 			pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors;
@@ -1149,6 +1181,7 @@ int dcn20_populate_dml_pipes_from_context(
 		if (!res_ctx->pipe_ctx[i].plane_state) {
 			pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
 			pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
+			pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_0;
 			pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_4kb_s;
 			pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
 			pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
@@ -1201,8 +1234,26 @@ int dcn20_populate_dml_pipes_from_context(
 
 			pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
 					|| pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
+			switch (pln->rotation) {
+			case ROTATION_ANGLE_0:
+				pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_0;
+				break;
+			case ROTATION_ANGLE_90:
+				pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_90;
+				break;
+			case ROTATION_ANGLE_180:
+				pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_180;
+				break;
+			case ROTATION_ANGLE_270:
+				pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_270;
+				break;
+			default:
+				break;
+			}
 			pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
 			pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
+			pipes[pipe_cnt].pipe.src.viewport_x_y = scl->viewport.x;
+			pipes[pipe_cnt].pipe.src.viewport_x_c = scl->viewport_c.x;
 			pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
 			pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
 			pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 555d4d9e14545..0317af5bb8ca8 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -195,6 +195,16 @@ struct resource_funcs {
 	enum dc_status (*add_dsc_to_stream_resource)(
 			struct dc *dc, struct dc_state *state,
 			struct dc_stream_state *stream);
+
+	void (*add_phantom_pipes)(
+            struct dc *dc,
+            struct dc_state *context,
+            display_e2e_pipe_params_st *pipes,
+			unsigned int pipe_cnt,
+            unsigned int index);
+	void (*remove_phantom_pipes)(
+            struct dc *dc,
+            struct dc_state *context);
 };
 
 struct audio_support{
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index c1023cc84f553..b5acc6b9f3c9c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -45,9 +45,10 @@ enum physymclk_clock_source {
 	PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DCIO.
 };
 
-enum hdmistreamclk_source {
+enum streamclk_source {
 	REFCLK,                   // Selects REFCLK as source for hdmistreamclk.
 	DTBCLK0,                  // Selects DTBCLK0 as source for hdmistreamclk.
+	DPREFCLK,                 // Selects DPREFCLK as source for hdmistreamclk
 };
 
 enum dentist_dispclk_change_mode {
@@ -91,7 +92,7 @@ struct dccg_funcs {
 
 	void (*set_dpstreamclk)(
 			struct dccg *dccg,
-			enum hdmistreamclk_source src,
+			enum streamclk_source src,
 			int otg_inst);
 
 	void (*enable_symclk32_se)(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index 9195dec294c2d..e7571c6f5ead4 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -47,6 +47,8 @@ struct dcn_hubbub_wm_set {
 	uint32_t sr_enter;
 	uint32_t sr_exit;
 	uint32_t dram_clk_chanage;
+	uint32_t usr_retrain;
+	uint32_t fclk_pstate_change;
 };
 
 struct dcn_hubbub_wm {
@@ -168,6 +170,7 @@ struct hubbub_funcs {
 	void (*program_det_size)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_in_kbyte);
 	void (*program_compbuf_size)(struct hubbub *hubbub, unsigned compbuf_size_kb, bool safe_to_increase);
 	void (*init_crb)(struct hubbub *hubbub);
+	void (*force_usr_retraining_allow)(struct hubbub *hubbub, bool allow);
 };
 
 struct hubbub {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index ad69d78c4ac34..b2cdb6bfc9b88 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -140,6 +140,9 @@ struct hubp_funcs {
 
 	void (*set_blank)(struct hubp *hubp, bool blank);
 	void (*set_blank_regs)(struct hubp *hubp, bool blank);
+#ifdef CONFIG_DRM_AMD_DC_DCN
+	void (*phantom_hubp_post_enable)(struct hubp *hubp);
+#endif
 	void (*set_hubp_blank_en)(struct hubp *hubp, bool blank);
 
 	void (*set_cursor_attributes)(
@@ -193,6 +196,10 @@ struct hubp_funcs {
 	bool (*hubp_in_blank)(struct hubp *hubp);
 	void (*hubp_soft_reset)(struct hubp *hubp, bool reset);
 
+	void (*hubp_update_force_pstate_disallow)(struct hubp *hubp, bool allow);
+	void (*hubp_update_mall_sel)(struct hubp *hubp, uint32_t mall_sel);
+	void (*hubp_prepare_subvp_buffering)(struct hubp *hubp, bool enable);
+
 	void (*hubp_set_flip_int)(struct hubp *hubp);
 
 	void (*program_extended_blank)(struct hubp *hubp,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
index 8798cfa11a4dd..b72fb314d804a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
@@ -37,6 +37,7 @@ struct cstate_pstate_watermarks_st {
 	uint32_t cstate_enter_plus_exit_z8_ns;
 	uint32_t cstate_enter_plus_exit_ns;
 	uint32_t pstate_change_ns;
+	uint32_t fclk_pstate_change_ns;
 };
 
 struct dcn_watermarks {
@@ -46,6 +47,7 @@ struct dcn_watermarks {
 	uint32_t frac_urg_bw_flip;
 	int32_t urgent_latency_ns;
 	struct cstate_pstate_watermarks_st cstate_pstate;
+	uint32_t usr_retraining_ns;
 };
 
 struct dcn_watermark_set {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
index 678c2065e5e88..36ec56524afde 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
@@ -164,6 +164,10 @@ struct stream_encoder_funcs {
 	void (*stop_dp_info_packets)(
 		struct stream_encoder *enc);
 
+	void (*reset_fifo)(
+		struct stream_encoder *enc
+	);
+
 	void (*dp_blank)(
 		struct dc_link *link,
 		struct stream_encoder *enc);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 554d2e33bd7f1..a89b2230cd2c4 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -174,6 +174,9 @@ struct timing_generator_funcs {
 
 	bool (*enable_crtc)(struct timing_generator *tg);
 	bool (*disable_crtc)(struct timing_generator *tg);
+#ifdef CONFIG_DRM_AMD_DC_DCN
+	void (*phantom_crtc_post_enable)(struct timing_generator *tg);
+#endif
 	bool (*immediate_disable_crtc)(struct timing_generator *tg);
 	bool (*is_counter_moving)(struct timing_generator *tg);
 	void (*get_position)(struct timing_generator *tg,
@@ -293,6 +296,7 @@ struct timing_generator_funcs {
 	void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing);
 	void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
 			struct dc_crtc_timing *timing);
+	void (*set_h_timing_div_manual_mode)(struct timing_generator *optc, bool manual_mode);
 	void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);
 	void (*set_gsl_source_select)(struct timing_generator *optc,
 			int group_idx,
@@ -310,8 +314,10 @@ struct timing_generator_funcs {
 			uint32_t slave_pixel_clock_100Hz,
 			uint8_t master_clock_divider,
 			uint8_t slave_clock_divider);
-
-	void (*init_odm)(struct timing_generator *tg);
+	bool (*validate_vmin_vmax)(struct timing_generator *optc,
+			int vmin, int vmax);
+	bool (*validate_vtotal_change_limit)(struct timing_generator *optc,
+			uint32_t vtotal_change_limit);
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 05053f3b4ab7b..eb616a4ed508f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -244,6 +244,8 @@ struct hw_sequencer_funcs {
 			struct pipe_ctx *pipe_ctx,
 			struct tg_color *color,
 			int mpcc_id);
+
+	void (*commit_subvp_config)(struct dc *dc, struct dc_state *context);
 };
 
 void color_space_to_black_color(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
index d2cb0e7945000..fd869e93cf541 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
@@ -145,6 +145,11 @@ struct hwseq_private_funcs {
 	void (*PLAT_58856_wa)(struct dc_state *context,
 			struct pipe_ctx *pipe_ctx);
 	void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);
+#ifdef CONFIG_DRM_AMD_DC_DCN
+	void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context);
+	void (*subvp_update_force_pstate)(struct dc *dc, struct dc_state *context);
+	void (*update_mall_sel)(struct dc *dc, struct dc_state *context);
+#endif
 };
 
 struct dce_hwseq {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index 2369f38ed06f1..58158764adc0a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -205,6 +205,13 @@ bool get_temp_dp_link_res(struct dc_link *link,
 		struct link_resource *link_res,
 		struct dc_link_settings *link_settings);
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt(
+		const struct resource_context *res_ctx,
+		const struct resource_pool *pool,
+		const struct dc_link *link);
+#endif
+
 void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,
 	struct dc_state *context);
 
diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
index cf4027cc3f4cf..83058bcbb2e8b 100644
--- a/drivers/gpu/drm/amd/display/include/bios_parser_types.h
+++ b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
@@ -335,4 +335,14 @@ struct bp_soc_bb_info {
 	uint32_t dram_sr_enter_exit_latency_100ns;
 };
 
+struct bp_connector_speed_cap_info {
+	uint32_t DP_HBR2_EN:1;
+	uint32_t DP_HBR3_EN:1;
+	uint32_t HDMI_6GB_EN:1;
+	uint32_t DP_UHBR10_EN:1;
+	uint32_t DP_UHBR13_5_EN:1;
+	uint32_t DP_UHBR20_EN:1;
+	uint32_t RESERVED:29;
+};
+
 #endif /*__DAL_BIOS_PARSER_TYPES_H__ */
-- 
GitLab


From 3b1229741eda70116e0163affdda377484a788ae Mon Sep 17 00:00:00 2001
From: Jack Xiao <Jack.Xiao@amd.com>
Date: Wed, 18 May 2022 14:11:20 +0800
Subject: [PATCH 0158/1731] drm/amdgpu/mes11: update mes11 api interface

fix mes11 api interface.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/include/mes_v11_api_def.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/include/mes_v11_api_def.h b/drivers/gpu/drm/amd/include/mes_v11_api_def.h
index e30064477d82a..f9d02d7bdf776 100644
--- a/drivers/gpu/drm/amd/include/mes_v11_api_def.h
+++ b/drivers/gpu/drm/amd/include/mes_v11_api_def.h
@@ -193,7 +193,7 @@ struct MES_LOG_BUFFER {
 };
 
 enum MES_SWIP_TO_HWIP_DEF {
-	MES_MAX_HWIP_SEGMENT = 6,
+	MES_MAX_HWIP_SEGMENT = 8,
 };
 
 union MESAPI_SET_HW_RESOURCES {
-- 
GitLab


From 577359ca178262a64236cc96299714dbff21e9c7 Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Wed, 23 Feb 2022 19:05:09 -0500
Subject: [PATCH 0159/1731] drm/amd/display: Add DM support for DCN32/DCN321

Add Display Manager specific changes for DCN3.2.x.  DM
handles the interaction between the core DC modesetting
code and the drm modesetting infrastructure.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 +++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1c23a844b1612..7280db2821ef7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -118,6 +118,11 @@ MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 
+#define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
+MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
+#define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
+MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
+
 #define FIRMWARE_RAVEN_DMCU		"amdgpu/raven_dmcu.bin"
 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 
@@ -1803,6 +1808,8 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
 		case IP_VERSION(3, 1, 3):
 		case IP_VERSION(3, 1, 5):
 		case IP_VERSION(3, 1, 6):
+		case IP_VERSION(3, 2, 0):
+		case IP_VERSION(3, 2, 1):
 			return 0;
 		default:
 			break;
@@ -1926,6 +1933,14 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
 		dmub_asic = DMUB_ASIC_DCN316;
 		fw_name_dmub = FIRMWARE_DCN316_DMUB;
 		break;
+	case IP_VERSION(3, 2, 0):
+		dmub_asic = DMUB_ASIC_DCN32;
+		fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
+		break;
+	case IP_VERSION(3, 2, 1):
+		dmub_asic = DMUB_ASIC_DCN321;
+		fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
+		break;
 	default:
 		/* ASIC doesn't support DMUB. */
 		return 0;
@@ -4235,6 +4250,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 	case IP_VERSION(3, 1, 3):
 	case IP_VERSION(3, 1, 5):
 	case IP_VERSION(3, 1, 6):
+	case IP_VERSION(3, 2, 0):
+	case IP_VERSION(3, 2, 1):
 	case IP_VERSION(2, 1, 0):
 		if (register_outbox_irq_handlers(dm->adev)) {
 			DRM_ERROR("DM: Failed to initialize IRQ\n");
@@ -4253,6 +4270,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 		case IP_VERSION(3, 1, 3):
 		case IP_VERSION(3, 1, 5):
 		case IP_VERSION(3, 1, 6):
+		case IP_VERSION(3, 2, 0):
+		case IP_VERSION(3, 2, 1):
 			psr_feature_enabled = true;
 			break;
 		default:
@@ -4370,6 +4389,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 		case IP_VERSION(3, 1, 3):
 		case IP_VERSION(3, 1, 5):
 		case IP_VERSION(3, 1, 6):
+		case IP_VERSION(3, 2, 0):
+		case IP_VERSION(3, 2, 1):
 			if (dcn10_register_irq_handlers(dm->adev)) {
 				DRM_ERROR("DM: Failed to initialize IRQ\n");
 				goto fail;
@@ -4556,6 +4577,8 @@ static int dm_early_init(void *handle)
 		case IP_VERSION(3, 1, 3):
 		case IP_VERSION(3, 1, 5):
 		case IP_VERSION(3, 1, 6):
+		case IP_VERSION(3, 2, 0):
+		case IP_VERSION(3, 2, 1):
 			adev->mode_info.num_crtc = 4;
 			adev->mode_info.num_hpd = 4;
 			adev->mode_info.num_dig = 4;
-- 
GitLab


From 85b0cc35efab0cbc78c083d4506250bea6a755ad Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Mon, 25 Apr 2022 18:33:23 -0400
Subject: [PATCH 0160/1731] drm/amd/display: add DCN32 to IP discovery table

[Why&How]
Add DCN32 to IP discovery to enable automatic initialization of AMDGPU
Display Manager

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 47f0344205edb..91f21b725a434 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1709,6 +1709,8 @@ static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
 		case IP_VERSION(3, 1, 3):
 		case IP_VERSION(3, 1, 5):
 		case IP_VERSION(3, 1, 6):
+		case IP_VERSION(3, 2, 0):
+		case IP_VERSION(3, 2, 1):
 			amdgpu_device_ip_block_add(adev, &dm_ip_block);
 			break;
 		default:
-- 
GitLab


From 49401d3a5c86f5ead12ea7cbe98031edb512b13a Mon Sep 17 00:00:00 2001
From: Kenneth Feng <kenneth.feng@amd.com>
Date: Tue, 31 May 2022 09:51:40 +0800
Subject: [PATCH 0161/1731] drm/amd/amdgpu: align the cg and pg settings

align the cg and pg settings between gc_v11_0 and gc_v11_2

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/soc21.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 9e18a2b22607b..09efef506e8f8 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -555,8 +555,11 @@ static int soc21_common_early_init(void *handle)
 		adev->cg_flags =
 			AMD_CG_SUPPORT_GFX_CGCG |
 			AMD_CG_SUPPORT_GFX_CGLS |
+			AMD_CG_SUPPORT_REPEATER_FGCG |
 			AMD_CG_SUPPORT_VCN_MGCG |
-			AMD_CG_SUPPORT_JPEG_MGCG;
+			AMD_CG_SUPPORT_JPEG_MGCG |
+			AMD_CG_SUPPORT_ATHUB_MGCG |
+			AMD_CG_SUPPORT_ATHUB_LS;
 		adev->pg_flags =
 			AMD_PG_SUPPORT_VCN |
 			AMD_PG_SUPPORT_VCN_DPG |
-- 
GitLab


From 543036a2de71f14f8ad566c858e5e9ff61736a86 Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Mon, 21 Feb 2022 15:33:05 -0500
Subject: [PATCH 0162/1731] drm/amd: Add GFX11 modifiers support to AMDGPU (v3)

GFX11 IP introduces new tiling mode. Various combinations of DCC
settings are possible and the most preferred settings must be exposed
for optimal use of the hardware.

add_gfx11_modifiers() is based on recommendation from Marek for the
preferred tiling modifier that are most efficient for the hardware.

v2: microtiling fix noticed by Marek
v3: keep Z tiling check

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   | 52 ++++++++++---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 76 ++++++++++++++++++-
 include/uapi/drm/drm_fourcc.h                 |  2 +
 3 files changed, 117 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 17c9bbe0cbc59..8ef489fad7076 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -30,6 +30,9 @@
 #include "atom.h"
 #include "amdgpu_connectors.h"
 #include "amdgpu_display.h"
+#include "soc15_common.h"
+#include "gc/gc_11_0_0_offset.h"
+#include "gc/gc_11_0_0_sh_mask.h"
 #include <asm/div64.h>
 
 #include <linux/pci.h>
@@ -663,6 +666,11 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 {
 	struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
 	uint64_t modifier = 0;
+	int num_pipes = 0;
+	int num_pkrs = 0;
+
+	num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
+	num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes;
 
 	if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
 		modifier = DRM_FORMAT_MOD_LINEAR;
@@ -675,7 +683,7 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 		int bank_xor_bits = 0;
 		int packers = 0;
 		int rb = 0;
-		int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
+		int pipes = ilog2(num_pipes);
 		uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
 
 		switch (swizzle >> 2) {
@@ -691,12 +699,17 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 		case 6: /* 64 KiB _X */
 			block_size_bits = 16;
 			break;
+		case 7: /* 256 KiB */
+			block_size_bits = 18;
+			break;
 		default:
 			/* RESERVED or VAR */
 			return -EINVAL;
 		}
 
-		if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
+		if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0))
+			version = AMD_FMT_MOD_TILE_VER_GFX11;
+		else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
 			version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
 		else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0))
 			version = AMD_FMT_MOD_TILE_VER_GFX10;
@@ -707,19 +720,33 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 		case 0: /* Z microtiling */
 			return -EINVAL;
 		case 1: /* S microtiling */
-			if (!has_xor)
-				version = AMD_FMT_MOD_TILE_VER_GFX9;
+			if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) {
+				if (!has_xor)
+					version = AMD_FMT_MOD_TILE_VER_GFX9;
+			}
 			break;
 		case 2:
-			if (!has_xor && afb->base.format->cpp[0] != 4)
-				version = AMD_FMT_MOD_TILE_VER_GFX9;
+			if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) {
+				if (!has_xor && afb->base.format->cpp[0] != 4)
+					version = AMD_FMT_MOD_TILE_VER_GFX9;
+			}
 			break;
 		case 3:
 			break;
 		}
 
 		if (has_xor) {
+			if (num_pipes == num_pkrs && num_pkrs == 0) {
+				DRM_ERROR("invalid number of pipes and packers\n");
+				return -EINVAL;
+			}
+
 			switch (version) {
+			case AMD_FMT_MOD_TILE_VER_GFX11:
+				pipe_xor_bits = min(block_size_bits - 8, pipes);
+				packers = min(block_size_bits - 8 - pipe_xor_bits,
+						ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
+				break;
 			case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
 				pipe_xor_bits = min(block_size_bits - 8, pipes);
 				packers = min(block_size_bits - 8 - pipe_xor_bits,
@@ -753,9 +780,10 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 			u64 render_dcc_offset;
 
 			/* Enable constant encode on RAVEN2 and later. */
-			bool dcc_constant_encode = adev->asic_type > CHIP_RAVEN ||
+			bool dcc_constant_encode = (adev->asic_type > CHIP_RAVEN ||
 						   (adev->asic_type == CHIP_RAVEN &&
-						    adev->external_rev_id >= 0x81);
+						    adev->external_rev_id >= 0x81)) &&
+						    adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0);
 
 			int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B :
 					      dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B :
@@ -870,10 +898,11 @@ static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned,
 		return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12);
 	}
 	case AMD_FMT_MOD_TILE_VER_GFX10:
-	case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: {
+	case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
+	case AMD_FMT_MOD_TILE_VER_GFX11: {
 		int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
 
-		if (ver == AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 &&
+		if (ver >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 &&
 		    AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2)
 			++pipes_log2;
 
@@ -966,6 +995,9 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)
 			case DC_SW_64KB_S_X:
 				block_size_log2 = 16;
 				break;
+			case DC_SW_VAR_S_X:
+				block_size_log2 = 18;
+				break;
 			default:
 				drm_dbg_kms(rfb->base.dev,
 					    "Swizzle mode with unknown block size: %d\n", swizzle);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 7280db2821ef7..872b7899b645b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -89,10 +89,14 @@
 #include "dcn/dcn_1_0_offset.h"
 #include "dcn/dcn_1_0_sh_mask.h"
 #include "soc15_hw_ip.h"
+#include "soc15_common.h"
 #include "vega10_ip_offset.h"
 
 #include "soc15_common.h"
 
+#include "gc/gc_11_0_0_offset.h"
+#include "gc/gc_11_0_0_sh_mask.h"
+
 #include "modules/inc/mod_freesync.h"
 #include "modules/power/power_helpers.h"
 #include "modules/inc/mod_info_packet.h"
@@ -4888,7 +4892,9 @@ fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev,
 	unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier);
 	unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
 	unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier);
-	unsigned int pipes_log2 = min(4u, mod_pipe_xor_bits);
+	unsigned int pipes_log2;
+
+	pipes_log2 = min(5u, mod_pipe_xor_bits);
 
 	fill_gfx9_tiling_info_from_device(adev, tiling_info);
 
@@ -5224,8 +5230,69 @@ add_gfx10_3_modifiers(const struct amdgpu_device *adev,
 		    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
 }
 
+static void
+add_gfx11_modifiers(struct amdgpu_device *adev,
+		      uint64_t **mods, uint64_t *size, uint64_t *capacity)
+{
+	int num_pipes = 0;
+	int pipe_xor_bits = 0;
+	int num_pkrs = 0;
+	int pkrs = 0;
+	u32 gb_addr_config;
+	unsigned swizzle_r_x;
+	uint64_t modifier_r_x;
+	uint64_t modifier_dcc_best;
+	uint64_t modifier_dcc_4k;
+
+	/* TODO: GFX11 IP HW init hasnt finish and we get zero if we read from
+	 * adev->gfx.config.gb_addr_config_fields.num_{pkrs,pipes} */
+	gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);
+	ASSERT(gb_addr_config != 0);
+
+	num_pkrs = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
+	pkrs = ilog2(num_pkrs);
+	num_pipes = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PIPES);
+	pipe_xor_bits = ilog2(num_pipes);
+
+	/* R_X swizzle modes are the best for rendering and DCC requires them. */
+	swizzle_r_x = num_pipes > 16 ? AMD_FMT_MOD_TILE_GFX11_256K_R_X :
+                                              AMD_FMT_MOD_TILE_GFX9_64K_R_X;
+
+	modifier_r_x = AMD_FMT_MOD |
+		AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
+		AMD_FMT_MOD_SET(TILE, swizzle_r_x) |
+		AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+		AMD_FMT_MOD_SET(PACKERS, pkrs);
+
+	/* DCC_CONSTANT_ENCODE is not set because it can't vary with gfx11 (it's implied to be 1). */
+	modifier_dcc_best = modifier_r_x |
+		AMD_FMT_MOD_SET(DCC, 1) |
+		AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 0) |
+		AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
+		AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B);
+
+	/* DCC settings for 4K and greater resolutions. (required by display hw) */
+	modifier_dcc_4k = modifier_r_x |
+			AMD_FMT_MOD_SET(DCC, 1) |
+			AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
+			AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
+			AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B);
+
+	add_modifier(mods, size, capacity, modifier_dcc_best);
+	add_modifier(mods, size, capacity, modifier_dcc_4k);
+
+	add_modifier(mods, size, capacity, modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1));
+	add_modifier(mods, size, capacity, modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1));
+
+	add_modifier(mods, size, capacity, modifier_r_x);
+
+	add_modifier(mods, size, capacity, AMD_FMT_MOD |
+             AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
+			 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D));
+}
+
 static int
-get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods)
+get_plane_modifiers(struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods)
 {
 	uint64_t size = 0, capacity = 128;
 	*mods = NULL;
@@ -5257,6 +5324,9 @@ get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, u
 		else
 			add_gfx10_1_modifiers(adev, mods, &size, &capacity);
 		break;
+	case AMDGPU_FAMILY_GC_11_0_0:
+		add_gfx11_modifiers(adev, mods, &size, &capacity);
+		break;
 	}
 
 	add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR);
@@ -5295,7 +5365,7 @@ fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev,
 		dcc->enable = 1;
 		dcc->meta_pitch = afb->base.pitches[1];
 		dcc->independent_64b_blks = independent_64b_blks;
-		if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) {
+		if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) {
 			if (independent_64b_blks && independent_128b_blks)
 				dcc->dcc_ind_blk = hubp_ind_block_64b_no_128bcl;
 			else if (independent_128b_blks)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index f1972154a5940..1d717c75e1717 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -1363,6 +1363,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
 #define AMD_FMT_MOD_TILE_VER_GFX9 1
 #define AMD_FMT_MOD_TILE_VER_GFX10 2
 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
+#define AMD_FMT_MOD_TILE_VER_GFX11 4
 
 /*
  * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
@@ -1378,6 +1379,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
+#define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31
 
 #define AMD_FMT_MOD_DCC_BLOCK_64B 0
 #define AMD_FMT_MOD_DCC_BLOCK_128B 1
-- 
GitLab


From e42ce1366ae806ba2c1f884997703be68df428f4 Mon Sep 17 00:00:00 2001
From: Dillon Varone <dillon.varone@amd.com>
Date: Tue, 1 Mar 2022 16:15:03 -0500
Subject: [PATCH 0163/1731] drm/amd/display: Fix USBC link creation

[Description]

Add USBC connector ID to align with new VBIOS parsing.

Add seperate DCN321 link encoder due to different PHY version affecting
DP ALT related registers.

Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../drm/amd/display/dc/bios/bios_parser2.c    |   1 +
 .../drm/amd/display/dc/bios/command_table.c   |   4 +-
 .../amd/display/dc/dcn10/dcn10_link_encoder.h |   6 +
 .../display/dc/dcn10/dcn10_stream_encoder.h   |   3 +
 .../display/dc/dcn32/dcn32_dio_link_encoder.c |  15 +-
 .../display/dc/dcn32/dcn32_dio_link_encoder.h |  20 +-
 .../gpu/drm/amd/display/dc/dcn321/Makefile    |   2 +-
 .../dc/dcn321/dcn321_dio_link_encoder.c       | 199 ++++++++++++++++++
 .../dc/dcn321/dcn321_dio_link_encoder.h       |  42 ++++
 .../amd/display/dc/dcn321/dcn321_resource.c   |   3 +-
 .../drm/amd/display/dc/inc/hw/link_encoder.h  |   2 +
 .../amd/display/include/bios_parser_types.h   |   3 +-
 12 files changed, 292 insertions(+), 8 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.h

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index bbc0a5769e884..3540b46765fb0 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -3224,6 +3224,7 @@ static enum bp_result update_slot_layout_info_v2(
 		break;
 
 	case CONNECTOR_ID_DISPLAY_PORT:
+	case CONNECTOR_ID_USBC:
 		if (record->mini_type == MINI_TYPE_NORMAL) {
 			slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DP;
 			slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DP;
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
index 32efa92422e89..818a529cacc37 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
@@ -522,8 +522,8 @@ static enum bp_result transmitter_control_v2(
 		 */
 		params.acConfig.ucEncoderSel = 1;
 
-	if (CONNECTOR_ID_DISPLAY_PORT == connector_id
-		|| CONNECTOR_ID_USBC == connector_id)
+	if (CONNECTOR_ID_DISPLAY_PORT == connector_id ||
+	    CONNECTOR_ID_USBC == connector_id)
 		/* Bit4: DP connector flag
 		 * =0 connector is none-DP connector
 		 * =1 connector is DP connector
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index 663aac0a164a3..773380ef4997b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -167,6 +167,7 @@ struct dcn10_link_enc_registers {
 	uint32_t DIO_LINKD_CNTL;
 	uint32_t DIO_LINKE_CNTL;
 	uint32_t DIO_LINKF_CNTL;
+	uint32_t DIG_FIFO_CTRL0;
 };
 
 #define LE_SF(reg_name, field_name, post_fix)\
@@ -472,11 +473,15 @@ struct dcn10_link_enc_registers {
 	type HPO_DP_ENC_SEL;\
 	type HPO_HDMI_ENC_SEL
 
+#define DCN32_LINK_ENCODER_REG_FIELD_LIST(type) \
+	type DIG_FIFO_OUTPUT_PIXEL_MODE
+
 struct dcn10_link_enc_shift {
 	DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 	DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 	DCN31_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
+	DCN32_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 };
 
 struct dcn10_link_enc_mask {
@@ -484,6 +489,7 @@ struct dcn10_link_enc_mask {
 	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
 	DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
 	DCN31_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
+	DCN32_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
 };
 
 struct dcn10_link_encoder {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index 02c77076fa499..dd9bb86da4de1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -659,6 +659,9 @@ void enc1_stream_encoder_send_immediate_sdp_message(
 void enc1_stream_encoder_stop_dp_info_packets(
 	struct stream_encoder *enc);
 
+void enc1_stream_encoder_reset_fifo(
+	struct stream_encoder *enc);
+
 void enc1_stream_encoder_dp_blank(
 	struct dc_link *link,
 	struct stream_encoder *enc);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c
index 7170a9aa82a47..d6855d4f749b1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c
@@ -33,6 +33,7 @@
 #include "stream_encoder.h"
 #include "i2caux_interface.h"
 #include "dc_bios_types.h"
+#include "link_enc_cfg.h"
 
 #include "gpio_service_interface.h"
 
@@ -125,7 +126,7 @@ bool dcn32_link_encoder_is_in_alt_mode(struct link_encoder *enc)
 
 	if (enc->features.flags.bits.DP_IS_USB_C) {
 		/* if value == 1 alt mode is disabled, otherwise it is enabled */
-		//REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
+		REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
 		is_usb_c_alt_mode = (dp_alt_mode_disable == 0);
 	}
 
@@ -142,13 +143,19 @@ void dcn32_link_encoder_get_max_link_cap(struct link_encoder *enc,
 
 	/* in usb c dp2 mode, max lane count is 2 */
 	if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) {
-//		REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
+		REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
 		if (!is_in_usb_c_dp4_mode)
 			link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
 	}
 
 }
 
+void enc32_set_dig_output_mode(struct link_encoder *enc, uint8_t pix_per_container)
+{
+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, pix_per_container);
+}
+ 
 static const struct link_encoder_funcs dcn32_link_enc_funcs = {
 	.read_state = link_enc2_read_state,
 	.validate_output_with_stream =
@@ -179,6 +186,7 @@ static const struct link_encoder_funcs dcn32_link_enc_funcs = {
 	.is_in_alt_mode = dcn32_link_encoder_is_in_alt_mode,
 	.get_max_link_cap = dcn32_link_encoder_get_max_link_cap,
 	.set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
+	.set_dig_output_mode = enc32_set_dig_output_mode,
 };
 
 void dcn32_link_encoder_construct(
@@ -203,6 +211,9 @@ void dcn32_link_encoder_construct(
 	enc10->base.hpd_source = init_data->hpd_source;
 	enc10->base.connector = init_data->connector;
 
+	if (enc10->base.connector.id == CONNECTOR_ID_USBC)
+		enc10->base.features.flags.bits.DP_IS_USB_C = 1;
+
 	enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
 
 	enc10->base.features = *enc_features;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h
index e880b76d5f252..749a1e8cb8113 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h
@@ -26,7 +26,15 @@
 #ifndef __DC_LINK_ENCODER__DCN32_H__
 #define __DC_LINK_ENCODER__DCN32_H__
 
-#include "dcn30/dcn30_dio_link_encoder.h"
+#include "dcn31/dcn31_dio_link_encoder.h"
+
+#define LE_DCN32_REG_LIST(id)\
+	LE_DCN31_REG_LIST(id),\
+	SRI(DIG_FIFO_CTRL0, DIG, id)
+
+#define LINK_ENCODER_MASK_SH_LIST_DCN32(mask_sh) \
+	LINK_ENCODER_MASK_SH_LIST_DCN31(mask_sh),\
+	LE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, mask_sh)
 
 void dcn32_link_encoder_construct(
 	struct dcn20_link_encoder *enc20,
@@ -38,5 +46,15 @@ void dcn32_link_encoder_construct(
 	const struct dcn10_link_enc_shift *link_shift,
 	const struct dcn10_link_enc_mask *link_mask);
 
+void enc32_hw_init(struct link_encoder *enc);
+
+void dcn32_link_encoder_enable_dp_output(
+	struct link_encoder *enc,
+	const struct dc_link_settings *link_settings,
+	enum clock_source_id clock_source);
+
+void enc32_set_dig_output_mode(
+		struct link_encoder *enc,
+		uint8_t pix_per_container);
 
 #endif /* __DC_LINK_ENCODER__DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/Makefile b/drivers/gpu/drm/amd/display/dc/dcn321/Makefile
index 99515cb3ed311..9b61d08700ca6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/Makefile
@@ -10,7 +10,7 @@
 #
 # Makefile for dcn321.
 
-DCN321 = dcn321_resource.o
+DCN321 = dcn321_resource.o dcn321_dio_link_encoder.o
 
 CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o := -mhard-float -msse
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.c
new file mode 100644
index 0000000000000..49682a31ecbd7
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "reg_helper.h"
+
+#include "core_types.h"
+#include "link_encoder.h"
+#include "dcn321_dio_link_encoder.h"
+#include "dcn31/dcn31_dio_link_encoder.h"
+#include "stream_encoder.h"
+#include "i2caux_interface.h"
+#include "dc_bios_types.h"
+
+#include "gpio_service_interface.h"
+
+#ifndef MIN
+#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
+#endif
+
+#define CTX \
+	enc10->base.ctx
+#define DC_LOGGER \
+	enc10->base.ctx->logger
+
+#define REG(reg)\
+	(enc10->link_regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+	enc10->link_shift->field_name, enc10->link_mask->field_name
+
+#define AUX_REG(reg)\
+	(enc10->aux_regs->reg)
+
+#define AUX_REG_READ(reg_name) \
+		dm_read_reg(CTX, AUX_REG(reg_name))
+
+#define AUX_REG_WRITE(reg_name, val) \
+			dm_write_reg(CTX, AUX_REG(reg_name), val)
+
+static const struct link_encoder_funcs dcn321_link_enc_funcs = {
+	.read_state = link_enc2_read_state,
+	.validate_output_with_stream =
+			dcn30_link_encoder_validate_output_with_stream,
+	.hw_init = enc32_hw_init,
+	.setup = dcn10_link_encoder_setup,
+	.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
+	.enable_dp_output = dcn32_link_encoder_enable_dp_output,
+	.enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
+	.disable_output = dcn10_link_encoder_disable_output,
+	.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
+	.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
+	.update_mst_stream_allocation_table =
+		dcn10_link_encoder_update_mst_stream_allocation_table,
+	.psr_program_dp_dphy_fast_training =
+			dcn10_psr_program_dp_dphy_fast_training,
+	.psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
+	.connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
+	.enable_hpd = dcn10_link_encoder_enable_hpd,
+	.disable_hpd = dcn10_link_encoder_disable_hpd,
+	.is_dig_enabled = dcn10_is_dig_enabled,
+	.destroy = dcn10_link_encoder_destroy,
+	.fec_set_enable = enc2_fec_set_enable,
+	.fec_set_ready = enc2_fec_set_ready,
+	.fec_is_active = enc2_fec_is_active,
+	.get_dig_frontend = dcn10_get_dig_frontend,
+	.get_dig_mode = dcn10_get_dig_mode,
+	.is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
+	.get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
+	.set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
+	.set_dig_output_mode = enc32_set_dig_output_mode,
+};
+
+void dcn321_link_encoder_construct(
+	struct dcn20_link_encoder *enc20,
+	const struct encoder_init_data *init_data,
+	const struct encoder_feature_support *enc_features,
+	const struct dcn10_link_enc_registers *link_regs,
+	const struct dcn10_link_enc_aux_registers *aux_regs,
+	const struct dcn10_link_enc_hpd_registers *hpd_regs,
+	const struct dcn10_link_enc_shift *link_shift,
+	const struct dcn10_link_enc_mask *link_mask)
+{
+	struct bp_connector_speed_cap_info bp_cap_info = {0};
+	const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
+	enum bp_result result = BP_RESULT_OK;
+	struct dcn10_link_encoder *enc10 = &enc20->enc10;
+
+	enc10->base.funcs = &dcn321_link_enc_funcs;
+	enc10->base.ctx = init_data->ctx;
+	enc10->base.id = init_data->encoder;
+
+	enc10->base.hpd_source = init_data->hpd_source;
+	enc10->base.connector = init_data->connector;
+
+	if (enc10->base.connector.id == CONNECTOR_ID_USBC)
+		enc10->base.features.flags.bits.DP_IS_USB_C = 1;
+
+	enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
+
+	enc10->base.features = *enc_features;
+
+	enc10->base.transmitter = init_data->transmitter;
+
+	/* set the flag to indicate whether driver poll the I2C data pin
+	 * while doing the DP sink detect
+	 */
+
+/*	if (dal_adapter_service_is_feature_supported(as,
+		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
+		enc10->base.features.flags.bits.
+			DP_SINK_DETECT_POLL_DATA_PIN = true;*/
+
+	enc10->base.output_signals =
+		SIGNAL_TYPE_DVI_SINGLE_LINK |
+		SIGNAL_TYPE_DVI_DUAL_LINK |
+		SIGNAL_TYPE_LVDS |
+		SIGNAL_TYPE_DISPLAY_PORT |
+		SIGNAL_TYPE_DISPLAY_PORT_MST |
+		SIGNAL_TYPE_EDP |
+		SIGNAL_TYPE_HDMI_TYPE_A;
+
+	enc10->link_regs = link_regs;
+	enc10->aux_regs = aux_regs;
+	enc10->hpd_regs = hpd_regs;
+	enc10->link_shift = link_shift;
+	enc10->link_mask = link_mask;
+
+	switch (enc10->base.transmitter) {
+	case TRANSMITTER_UNIPHY_A:
+		enc10->base.preferred_engine = ENGINE_ID_DIGA;
+	break;
+	case TRANSMITTER_UNIPHY_B:
+		enc10->base.preferred_engine = ENGINE_ID_DIGB;
+	break;
+	case TRANSMITTER_UNIPHY_C:
+		enc10->base.preferred_engine = ENGINE_ID_DIGC;
+	break;
+	case TRANSMITTER_UNIPHY_D:
+		enc10->base.preferred_engine = ENGINE_ID_DIGD;
+	break;
+	case TRANSMITTER_UNIPHY_E:
+		enc10->base.preferred_engine = ENGINE_ID_DIGE;
+	break;
+	default:
+		ASSERT_CRITICAL(false);
+		enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
+	}
+
+	/* default to one to mirror Windows behavior */
+	enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
+
+	if (bp_funcs->get_connector_speed_cap_info)
+		result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios,
+						enc10->base.connector, &bp_cap_info);
+
+	/* Override features with DCE-specific values */
+	if (result == BP_RESULT_OK) {
+		enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
+				bp_cap_info.DP_HBR2_EN;
+		enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
+				bp_cap_info.DP_HBR3_EN;
+		enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
+		enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1;
+		enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;
+		enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;
+		enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;
+	} else {
+		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
+				__func__,
+				result);
+	}
+	if (enc10->base.ctx->dc->debug.hdmi20_disable) {
+		enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
+	}
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.h
new file mode 100644
index 0000000000000..2205f39b0a241
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_LINK_ENCODER__DCN321_H__
+#define __DC_LINK_ENCODER__DCN321_H__
+
+#include "dcn32/dcn32_dio_link_encoder.h"
+
+void dcn321_link_encoder_construct(
+	struct dcn20_link_encoder *enc20,
+	const struct encoder_init_data *init_data,
+	const struct encoder_feature_support *enc_features,
+	const struct dcn10_link_enc_registers *link_regs,
+	const struct dcn10_link_enc_aux_registers *aux_regs,
+	const struct dcn10_link_enc_hpd_registers *hpd_regs,
+	const struct dcn10_link_enc_shift *link_shift,
+	const struct dcn10_link_enc_mask *link_mask);
+
+
+#endif /* __DC_LINK_ENCODER__DCN321_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index 6bc477a212b09..4db2cdf7c9e5c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -62,6 +62,7 @@
 #include "dcn31/dcn31_apg.h"
 #include "dcn31/dcn31_dio_link_encoder.h"
 #include "dcn32/dcn32_dio_link_encoder.h"
+#include "dcn321_dio_link_encoder.h"
 #include "dce/dce_clock_source.h"
 #include "dce/dce_audio.h"
 #include "dce/dce_hwseq.h"
@@ -1253,7 +1254,7 @@ static struct link_encoder *dcn321_link_encoder_create(
 	if (!enc20)
 		return NULL;
 
-	dcn32_link_encoder_construct(enc20,
+	dcn321_link_encoder_construct(enc20,
 			enc_init_data,
 			&link_enc_feature,
 			&link_enc_regs[enc_init_data->transmitter],
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 2013a70603aed..d8433c6792012 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -200,6 +200,8 @@ struct link_encoder_funcs {
 		struct link_encoder *enc,
 		enum encoder_type_select sel,
 		uint32_t hpo_inst);
+	void (*set_dig_output_mode)(
+			struct link_encoder *enc, uint8_t pix_per_container);
 };
 
 /*
diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
index 83058bcbb2e8b..812377d9e48f6 100644
--- a/drivers/gpu/drm/amd/display/include/bios_parser_types.h
+++ b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
@@ -342,7 +342,8 @@ struct bp_connector_speed_cap_info {
 	uint32_t DP_UHBR10_EN:1;
 	uint32_t DP_UHBR13_5_EN:1;
 	uint32_t DP_UHBR20_EN:1;
-	uint32_t RESERVED:29;
+	uint32_t DP_IS_USB_C:1;
+	uint32_t RESERVED:28;
 };
 
 #endif /*__DAL_BIOS_PARSER_TYPES_H__ */
-- 
GitLab


From 3dc35cf8789ac93d656f255539f9b37c5051ebf6 Mon Sep 17 00:00:00 2001
From: Alvin Lee <alvin.lee2@amd.com>
Date: Mon, 28 Feb 2022 17:24:00 -0500
Subject: [PATCH 0164/1731] drm/amd/display: Add missing instance for clock
 source register

[Description]
Need to add inst 5 for clk_src_regs because
there are 5 PHY instances in DCN32 & DCN321.

Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c   | 3 ++-
 drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 7ac6428aae52b..ca9da3d4b1b59 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -330,7 +330,8 @@ static const struct dce110_clk_src_regs clk_src_regs[] = {
 	clk_src_regs(0, A),
 	clk_src_regs(1, B),
 	clk_src_regs(2, C),
-	clk_src_regs(3, D)
+	clk_src_regs(3, D),
+	clk_src_regs(4, E)
 };
 
 static const struct dce110_clk_src_shift cs_shift = {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index 4db2cdf7c9e5c..28e4d7904d54d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -333,7 +333,8 @@ static const struct dce110_clk_src_regs clk_src_regs[] = {
 	clk_src_regs(0, A),
 	clk_src_regs(1, B),
 	clk_src_regs(2, C),
-	clk_src_regs(3, D)
+	clk_src_regs(3, D),
+	clk_src_regs(4, E)
 };
 
 static const struct dce110_clk_src_shift cs_shift = {
-- 
GitLab


From 2cb6915dcf70a2bf7ee10fcf3f56b083beec1086 Mon Sep 17 00:00:00 2001
From: Eric Bernstein <eric.bernstein@amd.com>
Date: Thu, 3 Mar 2022 14:11:46 -0500
Subject: [PATCH 0165/1731] drm/amd/display: Use DTBCLK for valid pixel clock

Use DTBCLK for valid pixel clock generation

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Acked-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 20 +++++++++++++------
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h  | 17 ++++++++++++++++
 2 files changed, 31 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
index 5609ac6d60407..b78775e8c13cd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
@@ -42,12 +42,6 @@
 #define DC_LOGGER \
 	dccg->ctx->logger
 
-enum pixel_rate_div {
-	PIXEL_RATE_DIV_BY_1 = 0,
-	PIXEL_RATE_DIV_BY_2 = 1,
-	PIXEL_RATE_DIV_BY_4 = 3
-};
-
 static void dccg32_set_pixel_rate_div(
 		struct dccg *dccg,
 		uint32_t otg_inst,
@@ -183,6 +177,19 @@ void dccg32_set_dtbclk_dto(
 	}
 }
 
+void dccg32_set_valid_pixel_rate(
+		struct dccg *dccg,
+		int otg_inst,
+		int pixclk_khz)
+{
+	struct dtbclk_dto_params dto_params = {0};
+
+	dto_params.otg_inst = otg_inst;
+	dto_params.pixclk_khz = pixclk_khz;
+
+	dccg32_set_dtbclk_dto(dccg, &dto_params);
+}
+
 static void dccg32_get_dccg_ref_freq(struct dccg *dccg,
 		unsigned int xtalin_freq_inKhz,
 		unsigned int *dccg_ref_freq_inKhz)
@@ -260,6 +267,7 @@ static const struct dccg_funcs dccg32_funcs = {
 	.disable_symclk32_le = dccg31_disable_symclk32_le,
 	.set_physymclk = dccg31_set_physymclk,
 	.set_dtbclk_dto = dccg32_set_dtbclk_dto,
+	.set_valid_pixel_rate = dccg32_set_valid_pixel_rate,
 	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
 	.set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,
 	.otg_add_pixel = dccg32_otg_add_pixel,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index b5acc6b9f3c9c..8b450a7274ae4 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -56,6 +56,12 @@ enum dentist_dispclk_change_mode {
 	DISPCLK_CHANGE_MODE_RAMPING,
 };
 
+enum pixel_rate_div {
+   PIXEL_RATE_DIV_BY_1 = 0,
+   PIXEL_RATE_DIV_BY_2 = 1,
+   PIXEL_RATE_DIV_BY_4 = 3
+};
+
 struct dccg {
 	struct dc_context *ctx;
 	const struct dccg_funcs *funcs;
@@ -139,6 +145,17 @@ struct dccg_funcs {
 		struct dccg *dccg,
 		int inst);
 
+void (*set_pixel_rate_div)(
+        struct dccg *dccg,
+        uint32_t otg_inst,
+        enum pixel_rate_div k1,
+        enum pixel_rate_div k2);
+
+void (*set_valid_pixel_rate)(
+        struct dccg *dccg,
+        int otg_inst,
+        int pixclk_khz);
+
 };
 
 #endif //__DAL_DCCG_H__
-- 
GitLab


From 542a0f2ef9ea2ccfadf2b8a3b53368c61fc97a0f Mon Sep 17 00:00:00 2001
From: Huang Rui <ray.huang@amd.com>
Date: Fri, 20 May 2022 11:04:04 +0800
Subject: [PATCH 0166/1731] drm/amdgpu: introduce two work mode for imu

IMU has two work mode such as debug mode and mission mode. Current GC
v11_0_0 is using the debug mode.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h |  6 +++++
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c  |  1 +
 drivers/gpu/drm/amd/amdgpu/imu_v11_0.c  | 30 ++++++++++++++-----------
 3 files changed, 24 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
index 56cf127cdf93d..cfc4a92837f03 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
@@ -24,6 +24,11 @@
 #ifndef __AMDGPU_IMU_H__
 #define __AMDGPU_IMU_H__
 
+enum imu_work_mode {
+	DEBUG_MODE,
+	MISSION_MODE
+};
+
 struct amdgpu_imu_funcs {
     int (*init_microcode)(struct amdgpu_device *adev);
     int (*load_microcode)(struct amdgpu_device *adev);
@@ -46,6 +51,7 @@ struct imu_rlc_ram_golden {
 
 struct amdgpu_imu {
     const struct amdgpu_imu_funcs *funcs;
+    enum imu_work_mode mode;
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 10e180b2d0f52..abe22749cccc8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -6292,6 +6292,7 @@ static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev)
 
 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev)
 {
+	adev->gfx.imu.mode = DEBUG_MODE;
 	adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
index d63d3f2b8a161..05d2b93a534cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
@@ -125,9 +125,11 @@ static void imu_v11_0_setup(struct amdgpu_device *adev)
 	WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff);
 	WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0xffff);
 
-	imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16);
-	imu_reg_val |= 0x1;
-	WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val);
+	if (adev->gfx.imu.mode == DEBUG_MODE) {
+		imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16);
+		imu_reg_val |= 0x1;
+		WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val);
+	}
 
 	//disble imu Rtavfs, SmsRepair, DfllBTC, and ClkB
 	imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10);
@@ -144,16 +146,18 @@ static int imu_v11_0_start(struct amdgpu_device *adev)
 	imu_reg_val &= 0xfffffffe;
 	WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val);
 
-	for (i = 0; i < adev->usec_timeout; i++) {
-		imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
-		if ((imu_reg_val & 0x1f) == 0x1f)
-			break;
-		udelay(1);
-	}
-
-	if (i >= adev->usec_timeout) {
-		dev_err(adev->dev, "init imu: IMU start timeout\n");
-		return -ETIMEDOUT;
+	if (adev->gfx.imu.mode == DEBUG_MODE) {
+		for (i = 0; i < adev->usec_timeout; i++) {
+			imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
+			if ((imu_reg_val & 0x1f) == 0x1f)
+				break;
+			udelay(1);
+		}
+
+		if (i >= adev->usec_timeout) {
+			dev_err(adev->dev, "init imu: IMU start timeout\n");
+			return -ETIMEDOUT;
+		}
 	}
 
 	return 0;
-- 
GitLab


From a839a73b18157fe30eb4acd2a1f1ffdb890762ff Mon Sep 17 00:00:00 2001
From: Dillon Varone <dillon.varone@amd.com>
Date: Tue, 8 Mar 2022 15:32:06 -0500
Subject: [PATCH 0167/1731] drm/amd/display: Add guard for FCLK pstate message
 to PMFW for DCN321

[WHY?]
DCN321 does not support FCLK DPM, and thus it should not send messages to
PMFW regarding it.

Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 419cc83b3d21f..4ff12b8166142 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -346,7 +346,8 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 					clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
 	}
 
-	if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) {
+	if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) &&
+			clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21) {
 		clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
 
 		/* To disable FCLK P-state switching, send FCLK_PSTATE_NOTSUPPORTED message to PMFW */
-- 
GitLab


From 9761843250f1367043ae2a483461af287aecc879 Mon Sep 17 00:00:00 2001
From: Dillon Varone <dillon.varone@amd.com>
Date: Tue, 8 Mar 2022 18:45:08 -0500
Subject: [PATCH 0168/1731] drm/amd/display: Various DML fixes to enable higher
 timings

Fixes to enable higher rate timings for DCN3.2.x.

Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
Signed-off-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../drm/amd/display/dc/dcn32/dcn32_hubbub.c   |  4 +--
 .../drm/amd/display/dc/dcn32/dcn32_resource.c | 33 ++++++++++++-------
 .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c  | 27 ++-------------
 3 files changed, 26 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
index 27813374f2bb7..99eb239bbc7bb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
@@ -65,7 +65,7 @@ static void dcn32_init_crb(struct hubbub *hubbub)
 	REG_SET_2(COMPBUF_RESERVED_SPACE, 0,
 			COMPBUF_RESERVED_SPACE_64B, hubbub2->pixel_chunk_size / 32,
 			COMPBUF_RESERVED_SPACE_ZS, hubbub2->pixel_chunk_size / 128);
-	REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x17F);
+	REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x47F);
 }
 
 static void dcn32_program_det_size(struct hubbub *hubbub, int hubp_inst, unsigned int det_buffer_size_in_kbyte)
@@ -119,8 +119,8 @@ static void dcn32_program_compbuf_size(struct hubbub *hubbub, unsigned int compb
 		ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size
 				+ hubbub2->det3_size + compbuf_size_segments <= hubbub2->crb_size_segs);
 		REG_UPDATE(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, compbuf_size_segments);
-		REG_WAIT(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, compbuf_size_segments, 1, 100);
 		hubbub2->compbuf_size_segments = compbuf_size_segments;
+		ASSERT(REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, &compbuf_size_segments) && !compbuf_size_segments);
 	}
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index ca9da3d4b1b59..8a10a7a4c3e1c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -3015,13 +3015,30 @@ int dcn32_populate_dml_pipes_from_context(
 		}
 		pipe_cnt++;
 	}
-	context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE;
 
-	if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
-		if (!is_dual_plane(pipe->plane_state->format)) {
-			context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
-			pipes[0].pipe.src.unbounded_req_mode = true;
+	switch (pipe_cnt) {
+	case 1:
+		context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_MAX_DET_SIZE;
+		if (pipe->plane_state && !dc->debug.disable_z9_mpc) {
+			if (!is_dual_plane(pipe->plane_state->format)) {
+				context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE;
+				pipes[0].pipe.src.unbounded_req_mode = true;
+				if (pipe->plane_state->src_rect.width >= 5120 &&
+					pipe->plane_state->src_rect.height >= 2880)
+					context->bw_ctx.dml.ip.det_buffer_size_kbytes = 320; // 5K or higher
+			}
 		}
+		break;
+	case 2:
+		context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_MAX_DET_SIZE / 2; // 576 KB (9 segments)
+		break;
+	case 3:
+		context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_MAX_DET_SIZE / 3; // 384 KB (6 segments)
+		break;
+	case 4:
+	default:
+		context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE; // 256 KB (4 segments)
+		break;
 	}
 
 	return pipe_cnt;
@@ -3283,7 +3300,6 @@ void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display
 	 * possible with firmware driven vertical blank stretching.
 	 */
 	// context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;
-
 	context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
 	context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
 	if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported)
@@ -3339,11 +3355,6 @@ void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display
 		if (!context->res_ctx.pipe_ctx[i].stream)
 			continue;
 
-		/* cstate disabled on 201 */
-//		if (dc->ctx->dce_version == DCN_VERSION_2_01)
-//			cstate_en = false;
-
-
 		context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml,
 				&context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes,
 				pipe_cnt, pipe_idx);
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index 8d4c74b0fc900..eeec40f6fd0aa 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -1018,31 +1018,8 @@ int dcn20_populate_dml_pipes_from_context(
 			pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
 		pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
 		pipes[pipe_cnt].dout.dp_lanes = 4;
-		if (res_ctx->pipe_ctx[i].stream->link) {
-			switch (res_ctx->pipe_ctx[i].stream->link->cur_link_settings.link_rate) {
-			case LINK_RATE_HIGH:
-				pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr;
-				break;
-			case LINK_RATE_HIGH2:
-				pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr2;
-				break;
-			case LINK_RATE_HIGH3:
-				pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr3;
-				break;
-			case LINK_RATE_UHBR10:
-				pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_uhbr10;
-				break;
-			case LINK_RATE_UHBR13_5:
-				pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_uhbr13p5;
-				break;
-			case LINK_RATE_UHBR20:
-				pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_uhbr20;
-				break;
-			default:
-				pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_na;
-				break;
-			}
-		}
+		if (res_ctx->pipe_ctx[i].stream->link)
+			pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_na;
 		pipes[pipe_cnt].dout.is_virtual = 0;
 		pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
 		pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
-- 
GitLab


From e06c5f59ffe1006f1c6f533113b72ad48a6d4564 Mon Sep 17 00:00:00 2001
From: Alvin Lee <alvin.lee2@amd.com>
Date: Mon, 14 Mar 2022 19:54:53 -0400
Subject: [PATCH 0169/1731] drm/amd/display: Implement WM table transfer for
 DCN32/DCN321

Add support for watermark table transfers.

Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c   | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 4ff12b8166142..93fbecbc80650 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -444,6 +444,7 @@ void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)
 }
 static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
 {
+	unsigned int i;
 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 	WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
 
@@ -455,6 +456,12 @@ static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
 
 	memset(table, 0, sizeof(*table));
 
+	/* collect valid ranges, place in pmfw table */
+	for (i = 0; i < WM_SET_COUNT; i++)
+		if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
+			table->Watermarks.WatermarkRow[i].WmSetting = i;
+			table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
+		}
 	dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
 	dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
 	dcn32_smu_transfer_wm_table_dram_2_smu(clk_mgr);
-- 
GitLab


From b3f2c796634613bca511266b37084560f36b67c1 Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Thu, 24 Mar 2022 14:59:09 -0400
Subject: [PATCH 0170/1731] drm/amd/display: add missing interrupt handlers for
 DCN32/DCN321

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../display/dc/irq/dcn32/irq_service_dcn32.c  | 65 ++++++++++++++++++-
 1 file changed, 64 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
index 3f9d6531c5633..3a213ca2f0771 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
@@ -54,6 +54,18 @@ enum dc_irq_source to_dal_irq_source_dcn32(
 		return DC_IRQ_SOURCE_VBLANK5;
 	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
 		return DC_IRQ_SOURCE_VBLANK6;
+	case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC1_VLINE0;
+	case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC2_VLINE0;
+	case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC3_VLINE0;
+	case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC4_VLINE0;
+	case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC5_VLINE0;
+	case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC6_VLINE0;
 	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
 		return DC_IRQ_SOURCE_PFLIP1;
 	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
@@ -78,7 +90,8 @@ enum dc_irq_source to_dal_irq_source_dcn32(
 		return DC_IRQ_SOURCE_VUPDATE5;
 	case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 		return DC_IRQ_SOURCE_VUPDATE6;
-
+	case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
+		return DC_IRQ_SOURCE_DMCUB_OUTBOX;
 	case DCN_1_0__SRCID__DC_HPD1_INT:
 		/* generic src_id for all HPD and HPDRX interrupts */
 		switch (ext_id) {
@@ -168,6 +181,16 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
 	.ack = NULL
 };
 
+static const struct irq_source_info_funcs outbox_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs vline0_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
 #undef BASE_INNER
 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 
@@ -179,6 +202,10 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
 	BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 			reg ## block ## id ## _ ## reg_name
 
+#define SRI_DMUB(reg_name)\
+	BASE(reg ## reg_name ## _BASE_IDX) + \
+			reg ## reg_name
+
 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
 	.enable_reg = SRI(reg1, block, reg_num),\
 	.enable_mask = \
@@ -193,6 +220,20 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
 	.ack_value = \
 		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
 
+#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
+	.enable_reg = SRI_DMUB(reg1),\
+	.enable_mask = \
+		reg1 ## __ ## mask1 ## _MASK,\
+	.enable_value = {\
+		reg1 ## __ ## mask1 ## _MASK,\
+		~reg1 ## __ ## mask1 ## _MASK \
+	},\
+	.ack_reg = SRI_DMUB(reg2),\
+	.ack_mask = \
+		reg2 ## __ ## mask2 ## _MASK,\
+	.ack_value = \
+		reg2 ## __ ## mask2 ## _MASK \
+
 #define hpd_int_entry(reg_num)\
 	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
 		IRQ_REG_ENTRY(HPD, reg_num,\
@@ -237,6 +278,21 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
 		.funcs = &vblank_irq_info_funcs\
 }
 
+#define vline0_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
+		IRQ_REG_ENTRY(OTG, reg_num,\
+			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
+			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
+		.funcs = &vline0_irq_info_funcs\
+	}
+#define dmub_outbox_int_entry()\
+	[DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
+		IRQ_REG_ENTRY_DMUB(\
+			DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
+			DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
+		.funcs = &outbox_irq_info_funcs\
+	}
+
 #define dummy_irq_entry() \
 	{\
 		.funcs = &dummy_irq_info_funcs\
@@ -339,6 +395,13 @@ irq_source_info_dcn32[DAL_IRQ_SOURCES_NUMBER] = {
 	vblank_int_entry(1),
 	vblank_int_entry(2),
 	vblank_int_entry(3),
+	vline0_int_entry(0),
+	vline0_int_entry(1),
+	vline0_int_entry(2),
+	vline0_int_entry(3),
+	[DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
+	[DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
+	dmub_outbox_int_entry(),
 };
 
 static const struct irq_service_funcs irq_service_funcs_dcn32 = {
-- 
GitLab


From 6a640b95b061fe340214ebd4638974b8b6f08efe Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Thu, 24 Mar 2022 15:42:17 -0400
Subject: [PATCH 0171/1731] drm/amd/display: disable idle optimizations

Disable idle optimizations until SMU can handle them to prevent DMUB
timeout and subsequent system freeze

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 8a10a7a4c3e1c..64d1a6bf06834 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -976,6 +976,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 	.timing_trace = false,
 	.clock_trace = true,
 	.disable_pplib_clock_request = false,
+	.disable_idle_power_optimizations = true,
 	.pipe_split_policy = MPC_SPLIT_DYNAMIC,
 	.force_single_disp_pipe_split = false,
 	.disable_dcc = DCC_ENABLE,
-- 
GitLab


From cbd3e8440e2e6a4d83479235c9bf278b89360946 Mon Sep 17 00:00:00 2001
From: "Stanley.Yang" <Stanley.Yang@amd.com>
Date: Fri, 20 May 2022 21:03:09 +0800
Subject: [PATCH 0172/1731] drm/amdgpu: print umc correctable error address

Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Acked-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h       |  5 ++
 drivers/gpu/drm/amd/amdgpu/umc_v6_7.c         | 50 ++++++++++++++++++-
 .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c    |  1 +
 3 files changed, 54 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
index 28e603243b672..bf5a95104ec11 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
@@ -333,6 +333,11 @@ struct ecc_info_per_ch {
 
 struct umc_ecc_info {
 	struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM];
+
+	/* Determine smu ecctable whether support
+	 * record correctable error address
+	 */
+	int record_ce_addr_supported;
 };
 
 struct amdgpu_ras {
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
index 606892dbea1c7..bf7524f16b669 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
@@ -119,6 +119,24 @@ static void umc_v6_7_ecc_info_query_correctable_error_count(struct amdgpu_device
 		*error_count += 1;
 
 		umc_v6_7_query_error_status_helper(adev, mc_umc_status, umc_reg_offset);
+
+		if (ras->umc_ecc.record_ce_addr_supported)	{
+			uint64_t err_addr, soc_pa;
+			uint32_t channel_index =
+				adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
+
+			err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_ceumc_addr;
+			err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
+			/* translate umc channel address to soc pa, 3 parts are included */
+			soc_pa = ADDR_OF_8KB_BLOCK(err_addr) |
+					ADDR_OF_256B_BLOCK(channel_index) |
+					OFFSET_IN_256B_BLOCK(err_addr);
+
+			/* The umc channel bits are not original values, they are hashed */
+			SET_CHANNEL_HASH(channel_index, soc_pa);
+
+			dev_info(adev->dev, "Error Address(PA): 0x%llx\n", soc_pa);
+		}
 	}
 }
 
@@ -251,7 +269,9 @@ static void umc_v6_7_ecc_info_query_ras_error_address(struct amdgpu_device *adev
 
 static void umc_v6_7_query_correctable_error_count(struct amdgpu_device *adev,
 						   uint32_t umc_reg_offset,
-						   unsigned long *error_count)
+						   unsigned long *error_count,
+						   uint32_t ch_inst,
+						   uint32_t umc_inst)
 {
 	uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
 	uint32_t ecc_err_cnt, ecc_err_cnt_addr;
@@ -295,6 +315,31 @@ static void umc_v6_7_query_correctable_error_count(struct amdgpu_device *adev,
 		*error_count += 1;
 
 		umc_v6_7_query_error_status_helper(adev, mc_umc_status, umc_reg_offset);
+
+		{
+			uint64_t err_addr, soc_pa;
+			uint32_t mc_umc_addrt0;
+			uint32_t channel_index;
+
+			mc_umc_addrt0 =
+				SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);
+
+			channel_index =
+				adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
+
+			err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);
+			err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
+
+			/* translate umc channel address to soc pa, 3 parts are included */
+			soc_pa = ADDR_OF_8KB_BLOCK(err_addr) |
+					ADDR_OF_256B_BLOCK(channel_index) |
+					OFFSET_IN_256B_BLOCK(err_addr);
+
+			/* The umc channel bits are not original values, they are hashed */
+			SET_CHANNEL_HASH(channel_index, soc_pa);
+
+			dev_info(adev->dev, "Error Address(PA): 0x%llx\n", soc_pa);
+		}
 	}
 }
 
@@ -395,7 +440,8 @@ static void umc_v6_7_query_ras_error_count(struct amdgpu_device *adev,
 							 ch_inst);
 		umc_v6_7_query_correctable_error_count(adev,
 						       umc_reg_offset,
-						       &(err_data->ce_count));
+						       &(err_data->ce_count),
+						       ch_inst, umc_inst);
 		umc_v6_7_querry_uncorrectable_error_count(adev,
 							  umc_reg_offset,
 							  &(err_data->ue_count));
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index bf124bc98b804..bb3c238213239 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -1884,6 +1884,7 @@ static ssize_t aldebaran_get_ecc_info(struct smu_context *smu,
 			ecc_info_per_channel->mca_ceumc_addr =
 				ecc_table->EccInfo_V2[i].mca_ceumc_addr;
 		}
+		eccinfo->record_ce_addr_supported = 1;
 	}
 
 	return ret;
-- 
GitLab


From 1908a07cffdfc7c57ba5116418c3f2b5ef05e0f6 Mon Sep 17 00:00:00 2001
From: Dillon Varone <dillon.varone@amd.com>
Date: Fri, 1 Apr 2022 16:45:40 -0400
Subject: [PATCH 0173/1731] drm/amd/display: Select correct DTO source

[WHY&HOW]
Change criteria for setting DTO source value, and always set it regardless of
the signal type.

Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../drm/amd/display/dc/dce/dce_clock_source.c | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 845aa8a1027d8..4b57657b53226 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -992,7 +992,18 @@ static bool dcn31_program_pix_clk(
 			REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
 			REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
 		}
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+		/* Enable DTO */
+		if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
+			REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
+					DP_DTO0_ENABLE, 1,
+					PIPE0_DTO_SRC_SEL, 1);
+		else
+			REG_UPDATE(PIXEL_RATE_CNTL[inst],
+					DP_DTO0_ENABLE, 1);
+#else
 		REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
+#endif
 	} else {
 		if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
 			unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
@@ -1004,10 +1015,26 @@ static bool dcn31_program_pix_clk(
 			REG_WRITE(MODULO[inst], dp_dto_ref_100hz);
 
 			/* Enable DTO */
+	#if defined(CONFIG_DRM_AMD_DC_DCN)
+			if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
+				REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
+						DP_DTO0_ENABLE, 1,
+						PIPE0_DTO_SRC_SEL, 1);
+			else
+				REG_UPDATE(PIXEL_RATE_CNTL[inst],
+						DP_DTO0_ENABLE, 1);
+	#else
 			REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
+	#endif
 			return true;
 		}
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+		if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
+			REG_UPDATE(PIXEL_RATE_CNTL[inst],
+					PIPE0_DTO_SRC_SEL, 0);
+#endif
+
 		/*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
 		bp_pc_params.controller_id = pix_clk_params->controller_id;
 		bp_pc_params.pll_id = clock_source->id;
-- 
GitLab


From 218987fdead218ae0e714cd9059bc9fc480220f9 Mon Sep 17 00:00:00 2001
From: Charlene Liu <Charlene.Liu@amd.com>
Date: Tue, 5 Apr 2022 16:13:45 -0400
Subject: [PATCH 0174/1731] drm/amd/display: use updated clock source init
 routine

[why]
Use correct clock source initialization routine for DCN32/321

Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 64d1a6bf06834..7772beadd0006 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -1090,7 +1090,7 @@ static struct clock_source *dcn32_clock_source_create(
 	if (!clk_src)
 		return NULL;
 
-	if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
+	if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
 			regs, &cs_shift, &cs_mask)) {
 		clk_src->base.dp_clk_src = dp_clk_src;
 		return &clk_src->base;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index 28e4d7904d54d..0b420466b6dd7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -1088,7 +1088,7 @@ static struct clock_source *dcn321_clock_source_create(
 	if (!clk_src)
 		return NULL;
 
-	if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
+	if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
 			regs, &cs_shift, &cs_mask)) {
 		clk_src->base.dp_clk_src = dp_clk_src;
 		return &clk_src->base;
-- 
GitLab


From 9fe5d08fc8230adb64128986ee4af267a54e56dd Mon Sep 17 00:00:00 2001
From: Dillon Varone <dillon.varone@amd.com>
Date: Thu, 14 Apr 2022 16:57:17 -0400
Subject: [PATCH 0175/1731] drm/amd/display: Ensure that DMCUB fw in use is
 loaded by DC and not VBIOS

[Why?]
On wake from S3/S4, driver checks if DMUB is initialized. On S4 VBIOS loads
DMUB, and driver does not reload as it appears to be initialized already.

[How?]
Add a check for the DAL_FW bit to ensure that loaded FW is from driver and
not VBIOS.

Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
index 0a498082ccc6b..d298f6016e0b5 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
@@ -299,11 +299,13 @@ void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
 
 bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub)
 {
+	union dmub_fw_boot_status status;
 	uint32_t is_hw_init;
 
+	status.all = REG_READ(DMCUB_SCRATCH0);
 	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
 
-	return is_hw_init != 0;
+	return is_hw_init != 0 && status.bits.dal_fw;
 }
 
 bool dmub_dcn32_is_supported(struct dmub_srv *dmub)
-- 
GitLab


From 16600b7d66367482dc8526f8bc3a30b32aaef329 Mon Sep 17 00:00:00 2001
From: Huang Rui <ray.huang@amd.com>
Date: Fri, 20 May 2022 11:04:05 +0800
Subject: [PATCH 0176/1731] drm/amdgpu: use the callback function for reset
 status polling on IMU

Switch to use the callback function to poll the reset status on IMU.
Because it will have different sequency on other ASICs.

v2: drop unused variable (Alex)

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h |  1 +
 drivers/gpu/drm/amd/amdgpu/imu_v11_0.c  | 37 +++++++++++++++----------
 2 files changed, 24 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
index cfc4a92837f03..484e936812e45 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
@@ -35,6 +35,7 @@ struct amdgpu_imu_funcs {
     void (*setup_imu)(struct amdgpu_device *adev);
     int (*start_imu)(struct amdgpu_device *adev);
     void (*program_rlc_ram)(struct amdgpu_device *adev);
+    int (*wait_for_reset_status)(struct amdgpu_device *adev);
 };
 
 struct imu_rlc_ram_golden {
diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
index 05d2b93a534cb..fd053158abbdd 100644
--- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
@@ -117,6 +117,25 @@ static int imu_v11_0_load_microcode(struct amdgpu_device *adev)
 	return 0;
 }
 
+static int imu_v11_0_wait_for_reset_status(struct amdgpu_device *adev)
+{
+	int i, imu_reg_val = 0;
+
+	for (i = 0; i < adev->usec_timeout; i++) {
+		imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
+		if ((imu_reg_val & 0x1f) == 0x1f)
+			break;
+		udelay(1);
+	}
+
+	if (i >= adev->usec_timeout) {
+		dev_err(adev->dev, "init imu: IMU start timeout\n");
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
 static void imu_v11_0_setup(struct amdgpu_device *adev)
 {
 	int imu_reg_val;
@@ -139,26 +158,15 @@ static void imu_v11_0_setup(struct amdgpu_device *adev)
 
 static int imu_v11_0_start(struct amdgpu_device *adev)
 {
-	int imu_reg_val, i;
+	int imu_reg_val;
 
 	//Start IMU by set GFX_IMU_CORE_CTRL.CRESET = 0
 	imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL);
 	imu_reg_val &= 0xfffffffe;
 	WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val);
 
-	if (adev->gfx.imu.mode == DEBUG_MODE) {
-		for (i = 0; i < adev->usec_timeout; i++) {
-			imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
-			if ((imu_reg_val & 0x1f) == 0x1f)
-				break;
-			udelay(1);
-		}
-
-		if (i >= adev->usec_timeout) {
-			dev_err(adev->dev, "init imu: IMU start timeout\n");
-			return -ETIMEDOUT;
-		}
-	}
+	if (adev->gfx.imu.mode == DEBUG_MODE)
+		return imu_v11_0_wait_for_reset_status(adev);
 
 	return 0;
 }
@@ -368,4 +376,5 @@ const struct amdgpu_imu_funcs gfx_v11_0_imu_funcs = {
 	.setup_imu = imu_v11_0_setup,
 	.start_imu = imu_v11_0_start,
 	.program_rlc_ram = imu_v11_0_program_rlc_ram,
+	.wait_for_reset_status = imu_v11_0_wait_for_reset_status,
 };
-- 
GitLab


From d57716702deac8e0ec440739eb4cd6eb0872ddd4 Mon Sep 17 00:00:00 2001
From: Huang Rui <ray.huang@amd.com>
Date: Thu, 12 May 2022 16:03:34 +0800
Subject: [PATCH 0177/1731] drm/amdgpu: add mmhub v3_0_1 headers

Add mmhub v3_0_1 headers, because there are many differeces with v3_0_0.

v2: squash in updates (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../asic_reg/mmhub/mmhub_3_0_1_offset.h       | 1769 ++++
 .../asic_reg/mmhub/mmhub_3_0_1_sh_mask.h      | 7483 +++++++++++++++++
 2 files changed, 9252 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_offset.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_sh_mask.h

diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_offset.h
new file mode 100644
index 0000000000000..6baac6ae2007a
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_offset.h
@@ -0,0 +1,1769 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _mmhub_3_0_1_OFFSET_HEADER
+#define _mmhub_3_0_1_OFFSET_HEADER
+
+
+
+// addressBlock: mmhub_dagbdec
+// base address: 0x68000
+#define regDAGB0_RDCLI0                                                                                 0x0000
+#define regDAGB0_RDCLI0_BASE_IDX                                                                        1
+#define regDAGB0_RDCLI1                                                                                 0x0001
+#define regDAGB0_RDCLI1_BASE_IDX                                                                        1
+#define regDAGB0_RDCLI2                                                                                 0x0002
+#define regDAGB0_RDCLI2_BASE_IDX                                                                        1
+#define regDAGB0_RDCLI3                                                                                 0x0003
+#define regDAGB0_RDCLI3_BASE_IDX                                                                        1
+#define regDAGB0_RDCLI4                                                                                 0x0004
+#define regDAGB0_RDCLI4_BASE_IDX                                                                        1
+#define regDAGB0_RDCLI5                                                                                 0x0005
+#define regDAGB0_RDCLI5_BASE_IDX                                                                        1
+#define regDAGB0_RDCLI6                                                                                 0x0006
+#define regDAGB0_RDCLI6_BASE_IDX                                                                        1
+#define regDAGB0_RDCLI7                                                                                 0x0007
+#define regDAGB0_RDCLI7_BASE_IDX                                                                        1
+#define regDAGB0_RDCLI8                                                                                 0x0008
+#define regDAGB0_RDCLI8_BASE_IDX                                                                        1
+#define regDAGB0_RDCLI9                                                                                 0x0009
+#define regDAGB0_RDCLI9_BASE_IDX                                                                        1
+#define regDAGB0_RDCLI10                                                                                0x000a
+#define regDAGB0_RDCLI10_BASE_IDX                                                                       1
+#define regDAGB0_RDCLI11                                                                                0x000b
+#define regDAGB0_RDCLI11_BASE_IDX                                                                       1
+#define regDAGB0_RDCLI12                                                                                0x000c
+#define regDAGB0_RDCLI12_BASE_IDX                                                                       1
+#define regDAGB0_RDCLI13                                                                                0x000d
+#define regDAGB0_RDCLI13_BASE_IDX                                                                       1
+#define regDAGB0_RDCLI14                                                                                0x000e
+#define regDAGB0_RDCLI14_BASE_IDX                                                                       1
+#define regDAGB0_RDCLI15                                                                                0x000f
+#define regDAGB0_RDCLI15_BASE_IDX                                                                       1
+#define regDAGB0_RDCLI16                                                                                0x0010
+#define regDAGB0_RDCLI16_BASE_IDX                                                                       1
+#define regDAGB0_RDCLI17                                                                                0x0011
+#define regDAGB0_RDCLI17_BASE_IDX                                                                       1
+#define regDAGB0_RDCLI18                                                                                0x0012
+#define regDAGB0_RDCLI18_BASE_IDX                                                                       1
+#define regDAGB0_RDCLI19                                                                                0x0013
+#define regDAGB0_RDCLI19_BASE_IDX                                                                       1
+#define regDAGB0_RDCLI20                                                                                0x0014
+#define regDAGB0_RDCLI20_BASE_IDX                                                                       1
+#define regDAGB0_RDCLI21                                                                                0x0015
+#define regDAGB0_RDCLI21_BASE_IDX                                                                       1
+#define regDAGB0_RDCLI22                                                                                0x0016
+#define regDAGB0_RDCLI22_BASE_IDX                                                                       1
+#define regDAGB0_RDCLI23                                                                                0x0017
+#define regDAGB0_RDCLI23_BASE_IDX                                                                       1
+#define regDAGB0_RDCLI24                                                                                0x0018
+#define regDAGB0_RDCLI24_BASE_IDX                                                                       1
+#define regDAGB0_RDCLI25                                                                                0x0019
+#define regDAGB0_RDCLI25_BASE_IDX                                                                       1
+#define regDAGB0_RDCLI26                                                                                0x001a
+#define regDAGB0_RDCLI26_BASE_IDX                                                                       1
+#define regDAGB0_RDCLI27                                                                                0x001b
+#define regDAGB0_RDCLI27_BASE_IDX                                                                       1
+#define regDAGB0_RDCLI28                                                                                0x001c
+#define regDAGB0_RDCLI28_BASE_IDX                                                                       1
+#define regDAGB0_RDCLI29                                                                                0x001d
+#define regDAGB0_RDCLI29_BASE_IDX                                                                       1
+#define regDAGB0_RD_CNTL                                                                                0x001e
+#define regDAGB0_RD_CNTL_BASE_IDX                                                                       1
+#define regDAGB0_RD_IO_CNTL                                                                             0x001f
+#define regDAGB0_RD_IO_CNTL_BASE_IDX                                                                    1
+#define regDAGB0_RD_GMI_CNTL                                                                            0x0020
+#define regDAGB0_RD_GMI_CNTL_BASE_IDX                                                                   1
+#define regDAGB0_RD_ADDR_DAGB                                                                           0x0021
+#define regDAGB0_RD_ADDR_DAGB_BASE_IDX                                                                  1
+#define regDAGB0_RD_CGTT_CLK_CTRL                                                                       0x0022
+#define regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX                                                              1
+#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL                                                                 0x0023
+#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX                                                        1
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0                                                                0x0024
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX                                                       1
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0                                                               0x0025
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1                                                                0x0026
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX                                                       1
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1                                                               0x0027
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST2                                                                0x0028
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX                                                       1
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2                                                               0x0029
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX                                                      1
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST3                                                                0x002a
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST3_BASE_IDX                                                       1
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER3                                                               0x002b
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER3_BASE_IDX                                                      1
+#define regDAGB0_RD_VC0_CNTL                                                                            0x002c
+#define regDAGB0_RD_VC0_CNTL_BASE_IDX                                                                   1
+#define regDAGB0_RD_VC1_CNTL                                                                            0x002d
+#define regDAGB0_RD_VC1_CNTL_BASE_IDX                                                                   1
+#define regDAGB0_RD_VC2_CNTL                                                                            0x002e
+#define regDAGB0_RD_VC2_CNTL_BASE_IDX                                                                   1
+#define regDAGB0_RD_VC3_CNTL                                                                            0x002f
+#define regDAGB0_RD_VC3_CNTL_BASE_IDX                                                                   1
+#define regDAGB0_RD_VC4_CNTL                                                                            0x0030
+#define regDAGB0_RD_VC4_CNTL_BASE_IDX                                                                   1
+#define regDAGB0_RD_VC5_CNTL                                                                            0x0031
+#define regDAGB0_RD_VC5_CNTL_BASE_IDX                                                                   1
+#define regDAGB0_RD_IO_VC_CNTL                                                                          0x0032
+#define regDAGB0_RD_IO_VC_CNTL_BASE_IDX                                                                 1
+#define regDAGB0_RD_GMI_VC_CNTL                                                                         0x0033
+#define regDAGB0_RD_GMI_VC_CNTL_BASE_IDX                                                                1
+#define regDAGB0_RD_CNTL_MISC                                                                           0x0034
+#define regDAGB0_RD_CNTL_MISC_BASE_IDX                                                                  1
+#define regDAGB0_RD_TLB_CREDIT                                                                          0x0035
+#define regDAGB0_RD_TLB_CREDIT_BASE_IDX                                                                 1
+#define regDAGB0_RDCLI_ASK_PENDING                                                                      0x0036
+#define regDAGB0_RDCLI_ASK_PENDING_BASE_IDX                                                             1
+#define regDAGB0_RDCLI_GO_PENDING                                                                       0x0037
+#define regDAGB0_RDCLI_GO_PENDING_BASE_IDX                                                              1
+#define regDAGB0_RDCLI_GBLSEND_PENDING                                                                  0x0038
+#define regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX                                                         1
+#define regDAGB0_RDCLI_TLB_PENDING                                                                      0x0039
+#define regDAGB0_RDCLI_TLB_PENDING_BASE_IDX                                                             1
+#define regDAGB0_RDCLI_OARB_PENDING                                                                     0x003a
+#define regDAGB0_RDCLI_OARB_PENDING_BASE_IDX                                                            1
+#define regDAGB0_RDCLI_ASK2ARB_PENDING                                                                  0x003b
+#define regDAGB0_RDCLI_ASK2ARB_PENDING_BASE_IDX                                                         1
+#define regDAGB0_RDCLI_ASK2DF_PENDING                                                                   0x003c
+#define regDAGB0_RDCLI_ASK2DF_PENDING_BASE_IDX                                                          1
+#define regDAGB0_RDCLI_OSD_PENDING                                                                      0x003d
+#define regDAGB0_RDCLI_OSD_PENDING_BASE_IDX                                                             1
+#define regDAGB0_RDCLI_ASK_OSD_PENDING                                                                  0x003e
+#define regDAGB0_RDCLI_ASK_OSD_PENDING_BASE_IDX                                                         1
+#define regDAGB0_WRCLI0                                                                                 0x003f
+#define regDAGB0_WRCLI0_BASE_IDX                                                                        1
+#define regDAGB0_WRCLI1                                                                                 0x0040
+#define regDAGB0_WRCLI1_BASE_IDX                                                                        1
+#define regDAGB0_WRCLI2                                                                                 0x0041
+#define regDAGB0_WRCLI2_BASE_IDX                                                                        1
+#define regDAGB0_WRCLI3                                                                                 0x0042
+#define regDAGB0_WRCLI3_BASE_IDX                                                                        1
+#define regDAGB0_WRCLI4                                                                                 0x0043
+#define regDAGB0_WRCLI4_BASE_IDX                                                                        1
+#define regDAGB0_WRCLI5                                                                                 0x0044
+#define regDAGB0_WRCLI5_BASE_IDX                                                                        1
+#define regDAGB0_WRCLI6                                                                                 0x0045
+#define regDAGB0_WRCLI6_BASE_IDX                                                                        1
+#define regDAGB0_WRCLI7                                                                                 0x0046
+#define regDAGB0_WRCLI7_BASE_IDX                                                                        1
+#define regDAGB0_WRCLI8                                                                                 0x0047
+#define regDAGB0_WRCLI8_BASE_IDX                                                                        1
+#define regDAGB0_WRCLI9                                                                                 0x0048
+#define regDAGB0_WRCLI9_BASE_IDX                                                                        1
+#define regDAGB0_WRCLI10                                                                                0x0049
+#define regDAGB0_WRCLI10_BASE_IDX                                                                       1
+#define regDAGB0_WRCLI11                                                                                0x004a
+#define regDAGB0_WRCLI11_BASE_IDX                                                                       1
+#define regDAGB0_WRCLI12                                                                                0x004b
+#define regDAGB0_WRCLI12_BASE_IDX                                                                       1
+#define regDAGB0_WRCLI13                                                                                0x004c
+#define regDAGB0_WRCLI13_BASE_IDX                                                                       1
+#define regDAGB0_WRCLI14                                                                                0x004d
+#define regDAGB0_WRCLI14_BASE_IDX                                                                       1
+#define regDAGB0_WRCLI15                                                                                0x004e
+#define regDAGB0_WRCLI15_BASE_IDX                                                                       1
+#define regDAGB0_WRCLI16                                                                                0x004f
+#define regDAGB0_WRCLI16_BASE_IDX                                                                       1
+#define regDAGB0_WRCLI17                                                                                0x0050
+#define regDAGB0_WRCLI17_BASE_IDX                                                                       1
+#define regDAGB0_WRCLI18                                                                                0x0051
+#define regDAGB0_WRCLI18_BASE_IDX                                                                       1
+#define regDAGB0_WRCLI19                                                                                0x0052
+#define regDAGB0_WRCLI19_BASE_IDX                                                                       1
+#define regDAGB0_WRCLI20                                                                                0x0053
+#define regDAGB0_WRCLI20_BASE_IDX                                                                       1
+#define regDAGB0_WRCLI21                                                                                0x0054
+#define regDAGB0_WRCLI21_BASE_IDX                                                                       1
+#define regDAGB0_WRCLI22                                                                                0x0055
+#define regDAGB0_WRCLI22_BASE_IDX                                                                       1
+#define regDAGB0_WRCLI23                                                                                0x0056
+#define regDAGB0_WRCLI23_BASE_IDX                                                                       1
+#define regDAGB0_WRCLI24                                                                                0x0057
+#define regDAGB0_WRCLI24_BASE_IDX                                                                       1
+#define regDAGB0_WRCLI25                                                                                0x0058
+#define regDAGB0_WRCLI25_BASE_IDX                                                                       1
+#define regDAGB0_WRCLI26                                                                                0x0059
+#define regDAGB0_WRCLI26_BASE_IDX                                                                       1
+#define regDAGB0_WRCLI27                                                                                0x005a
+#define regDAGB0_WRCLI27_BASE_IDX                                                                       1
+#define regDAGB0_WRCLI28                                                                                0x005b
+#define regDAGB0_WRCLI28_BASE_IDX                                                                       1
+#define regDAGB0_WRCLI29                                                                                0x005c
+#define regDAGB0_WRCLI29_BASE_IDX                                                                       1
+#define regDAGB0_WR_CNTL                                                                                0x005d
+#define regDAGB0_WR_CNTL_BASE_IDX                                                                       1
+#define regDAGB0_WR_IO_CNTL                                                                             0x005e
+#define regDAGB0_WR_IO_CNTL_BASE_IDX                                                                    1
+#define regDAGB0_WR_GMI_CNTL                                                                            0x005f
+#define regDAGB0_WR_GMI_CNTL_BASE_IDX                                                                   1
+#define regDAGB0_WR_ADDR_DAGB                                                                           0x0060
+#define regDAGB0_WR_ADDR_DAGB_BASE_IDX                                                                  1
+#define regDAGB0_WR_CGTT_CLK_CTRL                                                                       0x0061
+#define regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX                                                              1
+#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL                                                                 0x0062
+#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX                                                        1
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0                                                                0x0063
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX                                                       1
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0                                                               0x0064
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1                                                                0x0065
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX                                                       1
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1                                                               0x0066
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST2                                                                0x0067
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX                                                       1
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2                                                               0x0068
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX                                                      1
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST3                                                                0x0069
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST3_BASE_IDX                                                       1
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER3                                                               0x006a
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER3_BASE_IDX                                                      1
+#define regDAGB0_WR_DATA_DAGB                                                                           0x006b
+#define regDAGB0_WR_DATA_DAGB_BASE_IDX                                                                  1
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST0                                                                0x006c
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX                                                       1
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0                                                               0x006d
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST1                                                                0x006e
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX                                                       1
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1                                                               0x006f
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST2                                                                0x0070
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX                                                       1
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2                                                               0x0071
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX                                                      1
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST3                                                                0x0072
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST3_BASE_IDX                                                       1
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER3                                                               0x0073
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER3_BASE_IDX                                                      1
+#define regDAGB0_WR_VC0_CNTL                                                                            0x0074
+#define regDAGB0_WR_VC0_CNTL_BASE_IDX                                                                   1
+#define regDAGB0_WR_VC1_CNTL                                                                            0x0075
+#define regDAGB0_WR_VC1_CNTL_BASE_IDX                                                                   1
+#define regDAGB0_WR_VC2_CNTL                                                                            0x0076
+#define regDAGB0_WR_VC2_CNTL_BASE_IDX                                                                   1
+#define regDAGB0_WR_VC3_CNTL                                                                            0x0077
+#define regDAGB0_WR_VC3_CNTL_BASE_IDX                                                                   1
+#define regDAGB0_WR_VC4_CNTL                                                                            0x0078
+#define regDAGB0_WR_VC4_CNTL_BASE_IDX                                                                   1
+#define regDAGB0_WR_VC5_CNTL                                                                            0x0079
+#define regDAGB0_WR_VC5_CNTL_BASE_IDX                                                                   1
+#define regDAGB0_WR_IO_VC_CNTL                                                                          0x007a
+#define regDAGB0_WR_IO_VC_CNTL_BASE_IDX                                                                 1
+#define regDAGB0_WR_GMI_VC_CNTL                                                                         0x007b
+#define regDAGB0_WR_GMI_VC_CNTL_BASE_IDX                                                                1
+#define regDAGB0_WR_CNTL_MISC                                                                           0x007c
+#define regDAGB0_WR_CNTL_MISC_BASE_IDX                                                                  1
+#define regDAGB0_WR_TLB_CREDIT                                                                          0x007d
+#define regDAGB0_WR_TLB_CREDIT_BASE_IDX                                                                 1
+#define regDAGB0_WR_DATA_CREDIT                                                                         0x007e
+#define regDAGB0_WR_DATA_CREDIT_BASE_IDX                                                                1
+#define regDAGB0_WR_MISC_CREDIT                                                                         0x007f
+#define regDAGB0_WR_MISC_CREDIT_BASE_IDX                                                                1
+#define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1                                                              0x0080
+#define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_BASE_IDX                                                     1
+#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1                                                            0x0081
+#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX                                                   1
+#define regDAGB0_WRCLI_ASK_PENDING                                                                      0x0082
+#define regDAGB0_WRCLI_ASK_PENDING_BASE_IDX                                                             1
+#define regDAGB0_WRCLI_GO_PENDING                                                                       0x0083
+#define regDAGB0_WRCLI_GO_PENDING_BASE_IDX                                                              1
+#define regDAGB0_WRCLI_GBLSEND_PENDING                                                                  0x0084
+#define regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX                                                         1
+#define regDAGB0_WRCLI_TLB_PENDING                                                                      0x0085
+#define regDAGB0_WRCLI_TLB_PENDING_BASE_IDX                                                             1
+#define regDAGB0_WRCLI_OARB_PENDING                                                                     0x0086
+#define regDAGB0_WRCLI_OARB_PENDING_BASE_IDX                                                            1
+#define regDAGB0_WRCLI_ASK2ARB_PENDING                                                                  0x0087
+#define regDAGB0_WRCLI_ASK2ARB_PENDING_BASE_IDX                                                         1
+#define regDAGB0_WRCLI_ASK2DF_PENDING                                                                   0x0088
+#define regDAGB0_WRCLI_ASK2DF_PENDING_BASE_IDX                                                          1
+#define regDAGB0_WRCLI_OSD_PENDING                                                                      0x0089
+#define regDAGB0_WRCLI_OSD_PENDING_BASE_IDX                                                             1
+#define regDAGB0_WRCLI_ASK_OSD_PENDING                                                                  0x008a
+#define regDAGB0_WRCLI_ASK_OSD_PENDING_BASE_IDX                                                         1
+#define regDAGB0_WRCLI_DBUS_ASK_PENDING                                                                 0x008b
+#define regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX                                                        1
+#define regDAGB0_WRCLI_DBUS_GO_PENDING                                                                  0x008c
+#define regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX                                                         1
+#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE                                                               0x008d
+#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX                                                      1
+#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE                                                         0x008e
+#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX                                                1
+#define regDAGB0_DAGB_DLY                                                                               0x008f
+#define regDAGB0_DAGB_DLY_BASE_IDX                                                                      1
+#define regDAGB0_CNTL_MISC                                                                              0x0090
+#define regDAGB0_CNTL_MISC_BASE_IDX                                                                     1
+#define regDAGB0_CNTL_MISC2                                                                             0x0091
+#define regDAGB0_CNTL_MISC2_BASE_IDX                                                                    1
+#define regDAGB0_FIFO_EMPTY                                                                             0x0092
+#define regDAGB0_FIFO_EMPTY_BASE_IDX                                                                    1
+#define regDAGB0_FIFO_FULL                                                                              0x0093
+#define regDAGB0_FIFO_FULL_BASE_IDX                                                                     1
+#define regDAGB0_RD_CREDITS_FULL                                                                        0x0094
+#define regDAGB0_RD_CREDITS_FULL_BASE_IDX                                                               1
+#define regDAGB0_WR_CREDITS_FULL                                                                        0x0095
+#define regDAGB0_WR_CREDITS_FULL_BASE_IDX                                                               1
+#define regDAGB0_PERFCOUNTER_LO                                                                         0x0096
+#define regDAGB0_PERFCOUNTER_LO_BASE_IDX                                                                1
+#define regDAGB0_PERFCOUNTER_HI                                                                         0x0097
+#define regDAGB0_PERFCOUNTER_HI_BASE_IDX                                                                1
+#define regDAGB0_PERFCOUNTER0_CFG                                                                       0x0098
+#define regDAGB0_PERFCOUNTER0_CFG_BASE_IDX                                                              1
+#define regDAGB0_PERFCOUNTER1_CFG                                                                       0x0099
+#define regDAGB0_PERFCOUNTER1_CFG_BASE_IDX                                                              1
+#define regDAGB0_PERFCOUNTER2_CFG                                                                       0x009a
+#define regDAGB0_PERFCOUNTER2_CFG_BASE_IDX                                                              1
+#define regDAGB0_PERFCOUNTER_RSLT_CNTL                                                                  0x009b
+#define regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                         1
+#define regDAGB0_L1TLB_REG_RW                                                                           0x009c
+#define regDAGB0_L1TLB_REG_RW_BASE_IDX                                                                  1
+#define regDAGB0_RESERVE1                                                                               0x009d
+#define regDAGB0_RESERVE1_BASE_IDX                                                                      1
+#define regDAGB0_RESERVE2                                                                               0x009e
+#define regDAGB0_RESERVE2_BASE_IDX                                                                      1
+#define regDAGB0_RESERVE3                                                                               0x009f
+#define regDAGB0_RESERVE3_BASE_IDX                                                                      1
+#define regDAGB0_RESERVE4                                                                               0x00a0
+#define regDAGB0_RESERVE4_BASE_IDX                                                                      1
+#define regDAGB0_SDP_RD_BW_CNTL                                                                         0x00a1
+#define regDAGB0_SDP_RD_BW_CNTL_BASE_IDX                                                                1
+#define regDAGB0_SDP_PRIORITY_OVERRIDE                                                                  0x00a2
+#define regDAGB0_SDP_PRIORITY_OVERRIDE_BASE_IDX                                                         1
+#define regDAGB0_SDP_RD_PRIORITY                                                                        0x00a3
+#define regDAGB0_SDP_RD_PRIORITY_BASE_IDX                                                               1
+#define regDAGB0_SDP_WR_PRIORITY                                                                        0x00a4
+#define regDAGB0_SDP_WR_PRIORITY_BASE_IDX                                                               1
+#define regDAGB0_SDP_RD_CLI2SDP_VC_MAP                                                                  0x00a5
+#define regDAGB0_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX                                                         1
+#define regDAGB0_SDP_WR_CLI2SDP_VC_MAP                                                                  0x00a6
+#define regDAGB0_SDP_WR_CLI2SDP_VC_MAP_BASE_IDX                                                         1
+#define regDAGB0_SDP_ENABLE                                                                             0x00a7
+#define regDAGB0_SDP_ENABLE_BASE_IDX                                                                    1
+#define regDAGB0_SDP_CREDITS                                                                            0x00a8
+#define regDAGB0_SDP_CREDITS_BASE_IDX                                                                   1
+#define regDAGB0_SDP_TAG_RESERVE0                                                                       0x00a9
+#define regDAGB0_SDP_TAG_RESERVE0_BASE_IDX                                                              1
+#define regDAGB0_SDP_TAG_RESERVE1                                                                       0x00aa
+#define regDAGB0_SDP_TAG_RESERVE1_BASE_IDX                                                              1
+#define regDAGB0_SDP_VCC_RESERVE0                                                                       0x00ab
+#define regDAGB0_SDP_VCC_RESERVE0_BASE_IDX                                                              1
+#define regDAGB0_SDP_VCC_RESERVE1                                                                       0x00ac
+#define regDAGB0_SDP_VCC_RESERVE1_BASE_IDX                                                              1
+#define regDAGB0_SDP_ERR_STATUS                                                                         0x00ad
+#define regDAGB0_SDP_ERR_STATUS_BASE_IDX                                                                1
+#define regDAGB0_SDP_REQ_CNTL                                                                           0x00ae
+#define regDAGB0_SDP_REQ_CNTL_BASE_IDX                                                                  1
+#define regDAGB0_SDP_MISC_AON                                                                           0x00af
+#define regDAGB0_SDP_MISC_AON_BASE_IDX                                                                  1
+#define regDAGB0_SDP_MISC                                                                               0x00b0
+#define regDAGB0_SDP_MISC_BASE_IDX                                                                      1
+#define regDAGB0_SDP_MISC2                                                                              0x00b1
+#define regDAGB0_SDP_MISC2_BASE_IDX                                                                     1
+#define regDAGB0_SDP_VCD_RESERVE0                                                                       0x00b3
+#define regDAGB0_SDP_VCD_RESERVE0_BASE_IDX                                                              1
+#define regDAGB0_SDP_VCD_RESERVE1                                                                       0x00b4
+#define regDAGB0_SDP_VCD_RESERVE1_BASE_IDX                                                              1
+#define regDAGB0_SDP_ARB_CNTL0                                                                          0x00b5
+#define regDAGB0_SDP_ARB_CNTL0_BASE_IDX                                                                 1
+#define regDAGB0_SDP_ARB_CNTL1                                                                          0x00b6
+#define regDAGB0_SDP_ARB_CNTL1_BASE_IDX                                                                 1
+#define regDAGB0_SDP_CGTT_CLK_CTRL                                                                      0x00b7
+#define regDAGB0_SDP_CGTT_CLK_CTRL_BASE_IDX                                                             1
+#define regDAGB0_SDP_LATENCY_SAMPLING                                                                   0x00b8
+#define regDAGB0_SDP_LATENCY_SAMPLING_BASE_IDX                                                          1
+
+
+// addressBlock: mmhub_pctldec
+// base address: 0x68e00
+#define regPCTL_CTRL                                                                                    0x0380
+#define regPCTL_CTRL_BASE_IDX                                                                           1
+#define regPCTL_MMHUB_DEEPSLEEP_IB                                                                      0x0381
+#define regPCTL_MMHUB_DEEPSLEEP_IB_BASE_IDX                                                             1
+#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE                                                                0x0382
+#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX                                                       1
+#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB                                                             0x0383
+#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX                                                    1
+#define regPCTL_PG_IGNORE_DEEPSLEEP                                                                     0x0384
+#define regPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX                                                            1
+#define regPCTL_PG_IGNORE_DEEPSLEEP_IB                                                                  0x0385
+#define regPCTL_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX                                                         1
+#define regPCTL_SLICE0_CFG_DAGB_WRBUSY                                                                  0x0386
+#define regPCTL_SLICE0_CFG_DAGB_WRBUSY_BASE_IDX                                                         1
+#define regPCTL_SLICE0_CFG_DAGB_RDBUSY                                                                  0x0387
+#define regPCTL_SLICE0_CFG_DAGB_RDBUSY_BASE_IDX                                                         1
+#define regPCTL_SLICE0_CFG_DS_ALLOW                                                                     0x0388
+#define regPCTL_SLICE0_CFG_DS_ALLOW_BASE_IDX                                                            1
+#define regPCTL_SLICE0_CFG_DS_ALLOW_IB                                                                  0x0389
+#define regPCTL_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX                                                         1
+#define regPCTL_SLICE1_CFG_DAGB_WRBUSY                                                                  0x038a
+#define regPCTL_SLICE1_CFG_DAGB_WRBUSY_BASE_IDX                                                         1
+#define regPCTL_SLICE1_CFG_DAGB_RDBUSY                                                                  0x038b
+#define regPCTL_SLICE1_CFG_DAGB_RDBUSY_BASE_IDX                                                         1
+#define regPCTL_SLICE1_CFG_DS_ALLOW                                                                     0x038c
+#define regPCTL_SLICE1_CFG_DS_ALLOW_BASE_IDX                                                            1
+#define regPCTL_SLICE1_CFG_DS_ALLOW_IB                                                                  0x038d
+#define regPCTL_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX                                                         1
+#define regPCTL_UTCL2_MISC                                                                              0x038e
+#define regPCTL_UTCL2_MISC_BASE_IDX                                                                     1
+#define regPCTL_SLICE0_MISC                                                                             0x038f
+#define regPCTL_SLICE0_MISC_BASE_IDX                                                                    1
+#define regPCTL_SLICE1_MISC                                                                             0x0390
+#define regPCTL_SLICE1_MISC_BASE_IDX                                                                    1
+#define regPCTL_RENG_CTRL                                                                               0x0391
+#define regPCTL_RENG_CTRL_BASE_IDX                                                                      1
+#define regPCTL_UTCL2_RENG_EXECUTE                                                                      0x0392
+#define regPCTL_UTCL2_RENG_EXECUTE_BASE_IDX                                                             1
+#define regPCTL_SLICE0_RENG_EXECUTE                                                                     0x0393
+#define regPCTL_SLICE0_RENG_EXECUTE_BASE_IDX                                                            1
+#define regPCTL_SLICE1_RENG_EXECUTE                                                                     0x0394
+#define regPCTL_SLICE1_RENG_EXECUTE_BASE_IDX                                                            1
+#define regPCTL_UTCL2_RENG_RAM_INDEX                                                                    0x0395
+#define regPCTL_UTCL2_RENG_RAM_INDEX_BASE_IDX                                                           1
+#define regPCTL_UTCL2_RENG_RAM_DATA                                                                     0x0396
+#define regPCTL_UTCL2_RENG_RAM_DATA_BASE_IDX                                                            1
+#define regPCTL_SLICE0_RENG_RAM_INDEX                                                                   0x0397
+#define regPCTL_SLICE0_RENG_RAM_INDEX_BASE_IDX                                                          1
+#define regPCTL_SLICE0_RENG_RAM_DATA                                                                    0x0398
+#define regPCTL_SLICE0_RENG_RAM_DATA_BASE_IDX                                                           1
+#define regPCTL_SLICE1_RENG_RAM_INDEX                                                                   0x0399
+#define regPCTL_SLICE1_RENG_RAM_INDEX_BASE_IDX                                                          1
+#define regPCTL_SLICE1_RENG_RAM_DATA                                                                    0x039a
+#define regPCTL_SLICE1_RENG_RAM_DATA_BASE_IDX                                                           1
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0                                                       0x039b
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                              1
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1                                                       0x039c
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX                                              1
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2                                                       0x039d
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX                                              1
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3                                                       0x039e
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX                                              1
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4                                                       0x039f
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX                                              1
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0                                                    0x03a0
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX                                           1
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1                                                    0x03a1
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX                                           1
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0                                                      0x03a2
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                             1
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1                                                      0x03a3
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX                                             1
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2                                                      0x03a4
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX                                             1
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3                                                      0x03a5
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX                                             1
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4                                                      0x03a6
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX                                             1
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0                                                   0x03a7
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX                                          1
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1                                                   0x03a8
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX                                          1
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0                                                      0x03a9
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                             1
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1                                                      0x03aa
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX                                             1
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2                                                      0x03ab
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX                                             1
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3                                                      0x03ac
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX                                             1
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4                                                      0x03ad
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX                                             1
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0                                                   0x03ae
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX                                          1
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1                                                   0x03af
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX                                          1
+#define regPCTL_STATUS                                                                                  0x03b0
+#define regPCTL_STATUS_BASE_IDX                                                                         1
+#define regPCTL_PERFCOUNTER_LO                                                                          0x03b1
+#define regPCTL_PERFCOUNTER_LO_BASE_IDX                                                                 1
+#define regPCTL_PERFCOUNTER_HI                                                                          0x03b2
+#define regPCTL_PERFCOUNTER_HI_BASE_IDX                                                                 1
+#define regPCTL_PERFCOUNTER0_CFG                                                                        0x03b3
+#define regPCTL_PERFCOUNTER0_CFG_BASE_IDX                                                               1
+#define regPCTL_PERFCOUNTER1_CFG                                                                        0x03b4
+#define regPCTL_PERFCOUNTER1_CFG_BASE_IDX                                                               1
+#define regPCTL_PERFCOUNTER_RSLT_CNTL                                                                   0x03b5
+#define regPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                          1
+#define regPCTL_RESERVED_0                                                                              0x03b6
+#define regPCTL_RESERVED_0_BASE_IDX                                                                     1
+#define regPCTL_RESERVED_1                                                                              0x03b7
+#define regPCTL_RESERVED_1_BASE_IDX                                                                     1
+#define regPCTL_RESERVED_2                                                                              0x03b8
+#define regPCTL_RESERVED_2_BASE_IDX                                                                     1
+#define regPCTL_RESERVED_3                                                                              0x03b9
+#define regPCTL_RESERVED_3_BASE_IDX                                                                     1
+
+
+// addressBlock: mmhub_l1tlb_mmutcl1pfdec
+// base address: 0x69600
+#define regMMMC_VM_MX_L1_TLB0_STATUS                                                                    0x0588
+#define regMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLB1_STATUS                                                                    0x0589
+#define regMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLB2_STATUS                                                                    0x058a
+#define regMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLB3_STATUS                                                                    0x058b
+#define regMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLB4_STATUS                                                                    0x058c
+#define regMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLB5_STATUS                                                                    0x058d
+#define regMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLB6_STATUS                                                                    0x058e
+#define regMMMC_VM_MX_L1_TLB6_STATUS_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLB7_STATUS                                                                    0x058f
+#define regMMMC_VM_MX_L1_TLB7_STATUS_BASE_IDX                                                           1
+
+
+// addressBlock: mmhub_l1tlb_mmutcl1pldec
+// base address: 0x69670
+#define regMMMC_VM_MX_L1_PERFCOUNTER0_CFG                                                               0x059c
+#define regMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX                                                      1
+#define regMMMC_VM_MX_L1_PERFCOUNTER1_CFG                                                               0x059d
+#define regMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX                                                      1
+#define regMMMC_VM_MX_L1_PERFCOUNTER2_CFG                                                               0x059e
+#define regMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX                                                      1
+#define regMMMC_VM_MX_L1_PERFCOUNTER3_CFG                                                               0x059f
+#define regMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX                                                      1
+#define regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL                                                          0x05a0
+#define regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                 1
+
+
+// addressBlock: mmhub_l1tlb_mmutcl1prdec
+// base address: 0x69690
+#define regMMMC_VM_MX_L1_PERFCOUNTER_LO                                                                 0x05a4
+#define regMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX                                                        1
+#define regMMMC_VM_MX_L1_PERFCOUNTER_HI                                                                 0x05a5
+#define regMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX                                                        1
+
+
+// addressBlock: mmhub_l1tlb_mmvmtlspfdec
+// base address: 0x696c0
+#define regMMMC_VM_MX_L1_TLS0_CNTL                                                                      0x05b0
+#define regMMMC_VM_MX_L1_TLS0_CNTL_BASE_IDX                                                             1
+#define regMMMC_VM_MX_L1_TLS0_CNTL0                                                                     0x05b1
+#define regMMMC_VM_MX_L1_TLS0_CNTL0_BASE_IDX                                                            1
+#define regMMMC_VM_MX_L1_TLS0_CNTL1                                                                     0x05b2
+#define regMMMC_VM_MX_L1_TLS0_CNTL1_BASE_IDX                                                            1
+#define regMMMC_VM_MX_L1_TLS0_CNTL2                                                                     0x05b3
+#define regMMMC_VM_MX_L1_TLS0_CNTL2_BASE_IDX                                                            1
+#define regMMMC_VM_MX_L1_TLS0_CNTL3                                                                     0x05b4
+#define regMMMC_VM_MX_L1_TLS0_CNTL3_BASE_IDX                                                            1
+#define regMMMC_VM_MX_L1_TLS0_CNTL4                                                                     0x05b5
+#define regMMMC_VM_MX_L1_TLS0_CNTL4_BASE_IDX                                                            1
+#define regMMMC_VM_MX_L1_TLS0_CNTL5                                                                     0x05b6
+#define regMMMC_VM_MX_L1_TLS0_CNTL5_BASE_IDX                                                            1
+#define regMMMC_VM_MX_L1_TLS0_CNTL6                                                                     0x05b7
+#define regMMMC_VM_MX_L1_TLS0_CNTL6_BASE_IDX                                                            1
+#define regMMMC_VM_MX_L1_TLS0_CNTL7                                                                     0x05b8
+#define regMMMC_VM_MX_L1_TLS0_CNTL7_BASE_IDX                                                            1
+#define regMMMC_VM_MX_L1_TLS0_CNTL8                                                                     0x05b9
+#define regMMMC_VM_MX_L1_TLS0_CNTL8_BASE_IDX                                                            1
+#define regMMMC_VM_MX_L1_TLS0_CNTL9                                                                     0x05ba
+#define regMMMC_VM_MX_L1_TLS0_CNTL9_BASE_IDX                                                            1
+#define regMMMC_VM_MX_L1_TLS0_CNTL10                                                                    0x05bb
+#define regMMMC_VM_MX_L1_TLS0_CNTL10_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL11                                                                    0x05bc
+#define regMMMC_VM_MX_L1_TLS0_CNTL11_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL12                                                                    0x05bd
+#define regMMMC_VM_MX_L1_TLS0_CNTL12_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL13                                                                    0x05be
+#define regMMMC_VM_MX_L1_TLS0_CNTL13_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL14                                                                    0x05bf
+#define regMMMC_VM_MX_L1_TLS0_CNTL14_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL15                                                                    0x05c0
+#define regMMMC_VM_MX_L1_TLS0_CNTL15_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL16                                                                    0x05c1
+#define regMMMC_VM_MX_L1_TLS0_CNTL16_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL17                                                                    0x05c2
+#define regMMMC_VM_MX_L1_TLS0_CNTL17_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL18                                                                    0x05c3
+#define regMMMC_VM_MX_L1_TLS0_CNTL18_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL19                                                                    0x05c4
+#define regMMMC_VM_MX_L1_TLS0_CNTL19_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL20                                                                    0x05c5
+#define regMMMC_VM_MX_L1_TLS0_CNTL20_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL21                                                                    0x05c6
+#define regMMMC_VM_MX_L1_TLS0_CNTL21_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL22                                                                    0x05c7
+#define regMMMC_VM_MX_L1_TLS0_CNTL22_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL23                                                                    0x05c8
+#define regMMMC_VM_MX_L1_TLS0_CNTL23_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL24                                                                    0x05c9
+#define regMMMC_VM_MX_L1_TLS0_CNTL24_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL25                                                                    0x05ca
+#define regMMMC_VM_MX_L1_TLS0_CNTL25_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL26                                                                    0x05cb
+#define regMMMC_VM_MX_L1_TLS0_CNTL26_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL27                                                                    0x05cc
+#define regMMMC_VM_MX_L1_TLS0_CNTL27_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL28                                                                    0x05cd
+#define regMMMC_VM_MX_L1_TLS0_CNTL28_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL29                                                                    0x05ce
+#define regMMMC_VM_MX_L1_TLS0_CNTL29_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL30                                                                    0x05cf
+#define regMMMC_VM_MX_L1_TLS0_CNTL30_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL31                                                                    0x05d0
+#define regMMMC_VM_MX_L1_TLS0_CNTL31_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL32                                                                    0x05d1
+#define regMMMC_VM_MX_L1_TLS0_CNTL32_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL33                                                                    0x05d2
+#define regMMMC_VM_MX_L1_TLS0_CNTL33_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL34                                                                    0x05d3
+#define regMMMC_VM_MX_L1_TLS0_CNTL34_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL35                                                                    0x05d4
+#define regMMMC_VM_MX_L1_TLS0_CNTL35_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL36                                                                    0x05d5
+#define regMMMC_VM_MX_L1_TLS0_CNTL36_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_CNTL37                                                                    0x05d6
+#define regMMMC_VM_MX_L1_TLS0_CNTL37_BASE_IDX                                                           1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32                                                          0x05d7
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32_BASE_IDX                                                 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32                                                          0x05d8
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32_BASE_IDX                                                 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32                                                          0x05d9
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32_BASE_IDX                                                 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32                                                          0x05da
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32_BASE_IDX                                                 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32                                                          0x05db
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32_BASE_IDX                                                 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32                                                          0x05dc
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32_BASE_IDX                                                 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32                                                          0x05dd
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32_BASE_IDX                                                 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32                                                          0x05de
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32_BASE_IDX                                                 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32                                                          0x05df
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32_BASE_IDX                                                 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32                                                          0x05e0
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32_BASE_IDX                                                 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32                                                          0x05e1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32_BASE_IDX                                                 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32                                                          0x05e2
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32_BASE_IDX                                                 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32                                                          0x05e3
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32_BASE_IDX                                                 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32                                                          0x05e4
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32_BASE_IDX                                                 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32                                                          0x05e5
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32_BASE_IDX                                                 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32                                                          0x05e6
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32_BASE_IDX                                                 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32                                                          0x05e7
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32_BASE_IDX                                                 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32                                                          0x05e8
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32_BASE_IDX                                                 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32                                                          0x05e9
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32_BASE_IDX                                                 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32                                                          0x05ea
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32_BASE_IDX                                                 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32                                                         0x05eb
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32                                                         0x05ec
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32                                                         0x05ed
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32                                                         0x05ee
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32                                                         0x05ef
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32                                                         0x05f0
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32                                                         0x05f1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32                                                         0x05f2
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32                                                         0x05f3
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32                                                         0x05f4
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32                                                         0x05f5
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32                                                         0x05f6
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32                                                         0x05f7
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32                                                         0x05f8
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32                                                         0x05f9
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32                                                         0x05fa
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32                                                         0x05fb
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32                                                         0x05fc
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32                                                         0x05fd
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32                                                         0x05fe
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32                                                         0x05ff
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32                                                         0x0600
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32                                                         0x0601
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32                                                         0x0602
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32                                                         0x0603
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32                                                         0x0604
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32                                                         0x0605
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32                                                         0x0606
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32                                                         0x0607
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32                                                         0x0608
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32                                                         0x0609
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32                                                         0x060a
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32                                                         0x060b
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32                                                         0x060c
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32                                                         0x060d
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32                                                         0x060e
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32                                                         0x060f
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32                                                         0x0610
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32                                                         0x0611
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32                                                         0x0612
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32                                                         0x0613
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32                                                         0x0614
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32                                                         0x0615
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32                                                         0x0616
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32                                                         0x0617
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32                                                         0x0618
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32                                                         0x0619
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32                                                         0x061a
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32                                                         0x061b
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32                                                         0x061c
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32                                                         0x061d
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32                                                         0x061e
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32                                                         0x061f
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32                                                         0x0620
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32                                                         0x0621
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32                                                         0x0622
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32_BASE_IDX                                                1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32                                                            0x0623
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32_BASE_IDX                                                   1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32                                                            0x0624
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32_BASE_IDX                                                   1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32                                                            0x0625
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32_BASE_IDX                                                   1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32                                                            0x0626
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32_BASE_IDX                                                   1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32                                                            0x0627
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32_BASE_IDX                                                   1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32                                                            0x0628
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32_BASE_IDX                                                   1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32                                                            0x0629
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32_BASE_IDX                                                   1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32                                                            0x062a
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32_BASE_IDX                                                   1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32                                                            0x062b
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32_BASE_IDX                                                   1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32                                                            0x062c
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32_BASE_IDX                                                   1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32                                                            0x062d
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32_BASE_IDX                                                   1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32                                                            0x062e
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32_BASE_IDX                                                   1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32                                                            0x062f
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32_BASE_IDX                                                   1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32                                                            0x0630
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32_BASE_IDX                                                   1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32                                                            0x0631
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32_BASE_IDX                                                   1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32                                                            0x0632
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32_BASE_IDX                                                   1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32                                                            0x0633
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32_BASE_IDX                                                   1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32                                                            0x0634
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32_BASE_IDX                                                   1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32                                                            0x0635
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32_BASE_IDX                                                   1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32                                                            0x0636
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32_BASE_IDX                                                   1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32                                                           0x0637
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32                                                           0x0638
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32                                                           0x0639
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32                                                           0x063a
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32                                                           0x063b
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32                                                           0x063c
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32                                                           0x063d
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32                                                           0x063e
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32                                                           0x063f
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32                                                           0x0640
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32                                                           0x0641
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32                                                           0x0642
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32                                                           0x0643
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32                                                           0x0644
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32                                                           0x0645
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32                                                           0x0646
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32                                                           0x0647
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32                                                           0x0648
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32                                                           0x0649
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32                                                           0x064a
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32                                                           0x064b
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32                                                           0x064c
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32                                                           0x064d
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32                                                           0x064e
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32                                                           0x064f
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32                                                           0x0650
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32                                                           0x0651
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32                                                           0x0652
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32                                                           0x0653
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32                                                           0x0654
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32                                                           0x0655
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32                                                           0x0656
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32                                                           0x0657
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32                                                           0x0658
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32                                                           0x0659
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32                                                           0x065a
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32                                                           0x065b
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32                                                           0x065c
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32                                                           0x065d
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32                                                           0x065e
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32                                                           0x065f
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32                                                           0x0660
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32                                                           0x0661
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32                                                           0x0662
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32                                                           0x0663
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32                                                           0x0664
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32                                                           0x0665
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32                                                           0x0666
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32                                                           0x0667
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32                                                           0x0668
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32                                                           0x0669
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32                                                           0x066a
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32                                                           0x066b
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32                                                           0x066c
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32                                                           0x066d
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32                                                           0x066e
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32_BASE_IDX                                                  1
+#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32                                                    0x066f
+#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32_BASE_IDX                                           1
+#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32                                                    0x0670
+#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32_BASE_IDX                                           1
+#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32                                           0x0671
+#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32_BASE_IDX                                  1
+#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32                                           0x0672
+#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32_BASE_IDX                                  1
+#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS                                                   0x0673
+#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS_BASE_IDX                                          1
+#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32                                                0x0674
+#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32_BASE_IDX                                       1
+#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32                                                0x0675
+#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32_BASE_IDX                                       1
+#define regMMVM_L2_SAW_CNTL                                                                             0x0676
+#define regMMVM_L2_SAW_CNTL_BASE_IDX                                                                    1
+#define regMMVM_L2_SAW_CNTL2                                                                            0x0677
+#define regMMVM_L2_SAW_CNTL2_BASE_IDX                                                                   1
+#define regMMVM_L2_SAW_CNTL3                                                                            0x0678
+#define regMMVM_L2_SAW_CNTL3_BASE_IDX                                                                   1
+#define regMMVM_L2_SAW_CNTL4                                                                            0x0679
+#define regMMVM_L2_SAW_CNTL4_BASE_IDX                                                                   1
+#define regMMVM_L2_SAW_CONTEXT0_CNTL                                                                    0x067a
+#define regMMVM_L2_SAW_CONTEXT0_CNTL_BASE_IDX                                                           1
+#define regMMVM_L2_SAW_CONTEXT0_CNTL2                                                                   0x067b
+#define regMMVM_L2_SAW_CONTEXT0_CNTL2_BASE_IDX                                                          1
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                               0x067c
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                      1
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                               0x067d
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                      1
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                              0x067e
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                     1
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                              0x067f
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                     1
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                0x0680
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                       1
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                0x0681
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                       1
+#define regMMVM_L2_SAW_CONTEXTS_DISABLE                                                                 0x0682
+#define regMMVM_L2_SAW_CONTEXTS_DISABLE_BASE_IDX                                                        1
+#define regMMVM_L2_SAW_PIPES_BUSY_LO32                                                                  0x0683
+#define regMMVM_L2_SAW_PIPES_BUSY_LO32_BASE_IDX                                                         1
+#define regMMVM_L2_SAW_PIPES_BUSY_HI32                                                                  0x0684
+#define regMMVM_L2_SAW_PIPES_BUSY_HI32_BASE_IDX                                                         1
+#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS                                                        0x0685
+#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS_BASE_IDX                                               1
+#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32                                                   0x0686
+#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32_BASE_IDX                                          1
+#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32                                                   0x0687
+#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32_BASE_IDX                                          1
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2dec
+// base address: 0x69b00
+#define regMM_ATC_L2_CNTL                                                                               0x06c0
+#define regMM_ATC_L2_CNTL_BASE_IDX                                                                      1
+#define regMM_ATC_L2_CNTL2                                                                              0x06c1
+#define regMM_ATC_L2_CNTL2_BASE_IDX                                                                     1
+#define regMM_ATC_L2_CACHE_DATA0                                                                        0x06c4
+#define regMM_ATC_L2_CACHE_DATA0_BASE_IDX                                                               1
+#define regMM_ATC_L2_CACHE_DATA1                                                                        0x06c5
+#define regMM_ATC_L2_CACHE_DATA1_BASE_IDX                                                               1
+#define regMM_ATC_L2_CACHE_DATA2                                                                        0x06c6
+#define regMM_ATC_L2_CACHE_DATA2_BASE_IDX                                                               1
+#define regMM_ATC_L2_CNTL3                                                                              0x06c7
+#define regMM_ATC_L2_CNTL3_BASE_IDX                                                                     1
+#define regMM_ATC_L2_CNTL4                                                                              0x06c8
+#define regMM_ATC_L2_CNTL4_BASE_IDX                                                                     1
+#define regMM_ATC_L2_CNTL5                                                                              0x06c9
+#define regMM_ATC_L2_CNTL5_BASE_IDX                                                                     1
+#define regMM_ATC_L2_MM_GROUP_RT_CLASSES                                                                0x06ca
+#define regMM_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX                                                       1
+#define regMM_ATC_L2_STATUS                                                                             0x06cb
+#define regMM_ATC_L2_STATUS_BASE_IDX                                                                    1
+#define regMM_ATC_L2_STATUS2                                                                            0x06cc
+#define regMM_ATC_L2_STATUS2_BASE_IDX                                                                   1
+#define regMM_ATC_L2_MISC_CG                                                                            0x06cd
+#define regMM_ATC_L2_MISC_CG_BASE_IDX                                                                   1
+#define regMM_ATC_L2_MEM_POWER_LS                                                                       0x06ce
+#define regMM_ATC_L2_MEM_POWER_LS_BASE_IDX                                                              1
+#define regMM_ATC_L2_CGTT_CLK_CTRL                                                                      0x06cf
+#define regMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX                                                             1
+#define regMM_ATC_L2_SDPPORT_CTRL                                                                       0x06d2
+#define regMM_ATC_L2_SDPPORT_CTRL_BASE_IDX                                                              1
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pfdec
+// base address: 0x69c00
+#define regMMVM_L2_CNTL                                                                                 0x0700
+#define regMMVM_L2_CNTL_BASE_IDX                                                                        1
+#define regMMVM_L2_CNTL2                                                                                0x0701
+#define regMMVM_L2_CNTL2_BASE_IDX                                                                       1
+#define regMMVM_L2_CNTL3                                                                                0x0702
+#define regMMVM_L2_CNTL3_BASE_IDX                                                                       1
+#define regMMVM_L2_STATUS                                                                               0x0703
+#define regMMVM_L2_STATUS_BASE_IDX                                                                      1
+#define regMMVM_DUMMY_PAGE_FAULT_CNTL                                                                   0x0704
+#define regMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX                                                          1
+#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32                                                              0x0705
+#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX                                                     1
+#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32                                                              0x0706
+#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX                                                     1
+#define regMMVM_INVALIDATE_CNTL                                                                         0x0707
+#define regMMVM_INVALIDATE_CNTL_BASE_IDX                                                                1
+#define regMMVM_L2_PROTECTION_FAULT_CNTL                                                                0x0708
+#define regMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX                                                       1
+#define regMMVM_L2_PROTECTION_FAULT_CNTL2                                                               0x0709
+#define regMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX                                                      1
+#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3                                                            0x070a
+#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX                                                   1
+#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4                                                            0x070b
+#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX                                                   1
+#define regMMVM_L2_PROTECTION_FAULT_STATUS                                                              0x070c
+#define regMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX                                                     1
+#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32                                                           0x070d
+#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX                                                  1
+#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32                                                           0x070e
+#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX                                                  1
+#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32                                                   0x070f
+#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX                                          1
+#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32                                                   0x0710
+#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX                                          1
+#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32                                             0x0712
+#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX                                    1
+#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32                                             0x0713
+#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX                                    1
+#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32                                            0x0714
+#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX                                   1
+#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32                                            0x0715
+#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX                                   1
+#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32                                                0x0716
+#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX                                       1
+#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32                                                0x0717
+#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX                                       1
+#define regMMVM_L2_CNTL4                                                                                0x0718
+#define regMMVM_L2_CNTL4_BASE_IDX                                                                       1
+#define regMMVM_L2_MM_GROUP_RT_CLASSES                                                                  0x0719
+#define regMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX                                                         1
+#define regMMVM_L2_BANK_SELECT_RESERVED_CID                                                             0x071a
+#define regMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX                                                    1
+#define regMMVM_L2_BANK_SELECT_RESERVED_CID2                                                            0x071b
+#define regMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX                                                   1
+#define regMMVM_L2_CACHE_PARITY_CNTL                                                                    0x071c
+#define regMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX                                                           1
+#define regMMVM_L2_CGTT_CLK_CTRL                                                                        0x071d
+#define regMMVM_L2_CGTT_CLK_CTRL_BASE_IDX                                                               1
+#define regMMVM_L2_CNTL5                                                                                0x071e
+#define regMMVM_L2_CNTL5_BASE_IDX                                                                       1
+#define regMMVM_L2_GCR_CNTL                                                                             0x071f
+#define regMMVM_L2_GCR_CNTL_BASE_IDX                                                                    1
+#define regMMVM_L2_CGTT_BUSY_CTRL                                                                       0x0720
+#define regMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX                                                              1
+#define regMMVM_L2_PTE_CACHE_DUMP_CNTL                                                                  0x0721
+#define regMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX                                                         1
+#define regMMVM_L2_PTE_CACHE_DUMP_READ                                                                  0x0722
+#define regMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX                                                         1
+#define regMMVM_L2_BANK_SELECT_MASKS                                                                    0x0725
+#define regMMVM_L2_BANK_SELECT_MASKS_BASE_IDX                                                           1
+#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC                                                          0x0726
+#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX                                                 1
+#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC                                               0x0727
+#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX                                      1
+#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC                                             0x0728
+#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX                                    1
+#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT                                                      0x0729
+#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX                                             1
+#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ                                                      0x072a
+#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX                                             1
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2vcdec
+// base address: 0x69d00
+#define regMMVM_CONTEXT0_CNTL                                                                           0x0740
+#define regMMVM_CONTEXT0_CNTL_BASE_IDX                                                                  1
+#define regMMVM_CONTEXT1_CNTL                                                                           0x0741
+#define regMMVM_CONTEXT1_CNTL_BASE_IDX                                                                  1
+#define regMMVM_CONTEXT2_CNTL                                                                           0x0742
+#define regMMVM_CONTEXT2_CNTL_BASE_IDX                                                                  1
+#define regMMVM_CONTEXT3_CNTL                                                                           0x0743
+#define regMMVM_CONTEXT3_CNTL_BASE_IDX                                                                  1
+#define regMMVM_CONTEXT4_CNTL                                                                           0x0744
+#define regMMVM_CONTEXT4_CNTL_BASE_IDX                                                                  1
+#define regMMVM_CONTEXT5_CNTL                                                                           0x0745
+#define regMMVM_CONTEXT5_CNTL_BASE_IDX                                                                  1
+#define regMMVM_CONTEXT6_CNTL                                                                           0x0746
+#define regMMVM_CONTEXT6_CNTL_BASE_IDX                                                                  1
+#define regMMVM_CONTEXT7_CNTL                                                                           0x0747
+#define regMMVM_CONTEXT7_CNTL_BASE_IDX                                                                  1
+#define regMMVM_CONTEXT8_CNTL                                                                           0x0748
+#define regMMVM_CONTEXT8_CNTL_BASE_IDX                                                                  1
+#define regMMVM_CONTEXT9_CNTL                                                                           0x0749
+#define regMMVM_CONTEXT9_CNTL_BASE_IDX                                                                  1
+#define regMMVM_CONTEXT10_CNTL                                                                          0x074a
+#define regMMVM_CONTEXT10_CNTL_BASE_IDX                                                                 1
+#define regMMVM_CONTEXT11_CNTL                                                                          0x074b
+#define regMMVM_CONTEXT11_CNTL_BASE_IDX                                                                 1
+#define regMMVM_CONTEXT12_CNTL                                                                          0x074c
+#define regMMVM_CONTEXT12_CNTL_BASE_IDX                                                                 1
+#define regMMVM_CONTEXT13_CNTL                                                                          0x074d
+#define regMMVM_CONTEXT13_CNTL_BASE_IDX                                                                 1
+#define regMMVM_CONTEXT14_CNTL                                                                          0x074e
+#define regMMVM_CONTEXT14_CNTL_BASE_IDX                                                                 1
+#define regMMVM_CONTEXT15_CNTL                                                                          0x074f
+#define regMMVM_CONTEXT15_CNTL_BASE_IDX                                                                 1
+#define regMMVM_CONTEXTS_DISABLE                                                                        0x0750
+#define regMMVM_CONTEXTS_DISABLE_BASE_IDX                                                               1
+#define regMMVM_INVALIDATE_ENG0_SEM                                                                     0x0751
+#define regMMVM_INVALIDATE_ENG0_SEM_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG1_SEM                                                                     0x0752
+#define regMMVM_INVALIDATE_ENG1_SEM_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG2_SEM                                                                     0x0753
+#define regMMVM_INVALIDATE_ENG2_SEM_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG3_SEM                                                                     0x0754
+#define regMMVM_INVALIDATE_ENG3_SEM_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG4_SEM                                                                     0x0755
+#define regMMVM_INVALIDATE_ENG4_SEM_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG5_SEM                                                                     0x0756
+#define regMMVM_INVALIDATE_ENG5_SEM_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG6_SEM                                                                     0x0757
+#define regMMVM_INVALIDATE_ENG6_SEM_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG7_SEM                                                                     0x0758
+#define regMMVM_INVALIDATE_ENG7_SEM_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG8_SEM                                                                     0x0759
+#define regMMVM_INVALIDATE_ENG8_SEM_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG9_SEM                                                                     0x075a
+#define regMMVM_INVALIDATE_ENG9_SEM_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG10_SEM                                                                    0x075b
+#define regMMVM_INVALIDATE_ENG10_SEM_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG11_SEM                                                                    0x075c
+#define regMMVM_INVALIDATE_ENG11_SEM_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG12_SEM                                                                    0x075d
+#define regMMVM_INVALIDATE_ENG12_SEM_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG13_SEM                                                                    0x075e
+#define regMMVM_INVALIDATE_ENG13_SEM_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG14_SEM                                                                    0x075f
+#define regMMVM_INVALIDATE_ENG14_SEM_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG15_SEM                                                                    0x0760
+#define regMMVM_INVALIDATE_ENG15_SEM_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG16_SEM                                                                    0x0761
+#define regMMVM_INVALIDATE_ENG16_SEM_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG17_SEM                                                                    0x0762
+#define regMMVM_INVALIDATE_ENG17_SEM_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG0_REQ                                                                     0x0763
+#define regMMVM_INVALIDATE_ENG0_REQ_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG1_REQ                                                                     0x0764
+#define regMMVM_INVALIDATE_ENG1_REQ_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG2_REQ                                                                     0x0765
+#define regMMVM_INVALIDATE_ENG2_REQ_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG3_REQ                                                                     0x0766
+#define regMMVM_INVALIDATE_ENG3_REQ_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG4_REQ                                                                     0x0767
+#define regMMVM_INVALIDATE_ENG4_REQ_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG5_REQ                                                                     0x0768
+#define regMMVM_INVALIDATE_ENG5_REQ_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG6_REQ                                                                     0x0769
+#define regMMVM_INVALIDATE_ENG6_REQ_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG7_REQ                                                                     0x076a
+#define regMMVM_INVALIDATE_ENG7_REQ_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG8_REQ                                                                     0x076b
+#define regMMVM_INVALIDATE_ENG8_REQ_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG9_REQ                                                                     0x076c
+#define regMMVM_INVALIDATE_ENG9_REQ_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG10_REQ                                                                    0x076d
+#define regMMVM_INVALIDATE_ENG10_REQ_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG11_REQ                                                                    0x076e
+#define regMMVM_INVALIDATE_ENG11_REQ_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG12_REQ                                                                    0x076f
+#define regMMVM_INVALIDATE_ENG12_REQ_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG13_REQ                                                                    0x0770
+#define regMMVM_INVALIDATE_ENG13_REQ_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG14_REQ                                                                    0x0771
+#define regMMVM_INVALIDATE_ENG14_REQ_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG15_REQ                                                                    0x0772
+#define regMMVM_INVALIDATE_ENG15_REQ_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG16_REQ                                                                    0x0773
+#define regMMVM_INVALIDATE_ENG16_REQ_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG17_REQ                                                                    0x0774
+#define regMMVM_INVALIDATE_ENG17_REQ_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG0_ACK                                                                     0x0775
+#define regMMVM_INVALIDATE_ENG0_ACK_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG1_ACK                                                                     0x0776
+#define regMMVM_INVALIDATE_ENG1_ACK_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG2_ACK                                                                     0x0777
+#define regMMVM_INVALIDATE_ENG2_ACK_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG3_ACK                                                                     0x0778
+#define regMMVM_INVALIDATE_ENG3_ACK_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG4_ACK                                                                     0x0779
+#define regMMVM_INVALIDATE_ENG4_ACK_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG5_ACK                                                                     0x077a
+#define regMMVM_INVALIDATE_ENG5_ACK_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG6_ACK                                                                     0x077b
+#define regMMVM_INVALIDATE_ENG6_ACK_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG7_ACK                                                                     0x077c
+#define regMMVM_INVALIDATE_ENG7_ACK_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG8_ACK                                                                     0x077d
+#define regMMVM_INVALIDATE_ENG8_ACK_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG9_ACK                                                                     0x077e
+#define regMMVM_INVALIDATE_ENG9_ACK_BASE_IDX                                                            1
+#define regMMVM_INVALIDATE_ENG10_ACK                                                                    0x077f
+#define regMMVM_INVALIDATE_ENG10_ACK_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG11_ACK                                                                    0x0780
+#define regMMVM_INVALIDATE_ENG11_ACK_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG12_ACK                                                                    0x0781
+#define regMMVM_INVALIDATE_ENG12_ACK_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG13_ACK                                                                    0x0782
+#define regMMVM_INVALIDATE_ENG13_ACK_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG14_ACK                                                                    0x0783
+#define regMMVM_INVALIDATE_ENG14_ACK_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG15_ACK                                                                    0x0784
+#define regMMVM_INVALIDATE_ENG15_ACK_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG16_ACK                                                                    0x0785
+#define regMMVM_INVALIDATE_ENG16_ACK_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG17_ACK                                                                    0x0786
+#define regMMVM_INVALIDATE_ENG17_ACK_BASE_IDX                                                           1
+#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32                                                         0x0787
+#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX                                                1
+#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32                                                         0x0788
+#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX                                                1
+#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32                                                         0x0789
+#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX                                                1
+#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32                                                         0x078a
+#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX                                                1
+#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32                                                         0x078b
+#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX                                                1
+#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32                                                         0x078c
+#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX                                                1
+#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32                                                         0x078d
+#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX                                                1
+#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32                                                         0x078e
+#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX                                                1
+#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32                                                         0x078f
+#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX                                                1
+#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32                                                         0x0790
+#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX                                                1
+#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32                                                         0x0791
+#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX                                                1
+#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32                                                         0x0792
+#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX                                                1
+#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32                                                         0x0793
+#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX                                                1
+#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32                                                         0x0794
+#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX                                                1
+#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32                                                         0x0795
+#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX                                                1
+#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32                                                         0x0796
+#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX                                                1
+#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32                                                         0x0797
+#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX                                                1
+#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32                                                         0x0798
+#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX                                                1
+#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32                                                         0x0799
+#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX                                                1
+#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32                                                         0x079a
+#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX                                                1
+#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32                                                        0x079b
+#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX                                               1
+#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32                                                        0x079c
+#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX                                               1
+#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32                                                        0x079d
+#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX                                               1
+#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32                                                        0x079e
+#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX                                               1
+#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32                                                        0x079f
+#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX                                               1
+#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32                                                        0x07a0
+#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX                                               1
+#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32                                                        0x07a1
+#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX                                               1
+#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32                                                        0x07a2
+#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX                                               1
+#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32                                                        0x07a3
+#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX                                               1
+#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32                                                        0x07a4
+#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX                                               1
+#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32                                                        0x07a5
+#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX                                               1
+#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32                                                        0x07a6
+#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX                                               1
+#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32                                                        0x07a7
+#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX                                               1
+#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32                                                        0x07a8
+#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX                                               1
+#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32                                                        0x07a9
+#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX                                               1
+#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32                                                        0x07aa
+#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX                                               1
+#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                      0x07ab
+#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             1
+#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                      0x07ac
+#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             1
+#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                      0x07ad
+#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             1
+#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                      0x07ae
+#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             1
+#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                      0x07af
+#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             1
+#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                      0x07b0
+#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             1
+#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                      0x07b1
+#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             1
+#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                      0x07b2
+#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             1
+#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                      0x07b3
+#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             1
+#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                      0x07b4
+#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             1
+#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                      0x07b5
+#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             1
+#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                      0x07b6
+#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             1
+#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                      0x07b7
+#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             1
+#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                      0x07b8
+#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             1
+#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                      0x07b9
+#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             1
+#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                      0x07ba
+#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             1
+#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                      0x07bb
+#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             1
+#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                      0x07bc
+#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             1
+#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                      0x07bd
+#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             1
+#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                      0x07be
+#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             1
+#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                     0x07bf
+#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            1
+#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                     0x07c0
+#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            1
+#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                     0x07c1
+#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            1
+#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                     0x07c2
+#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            1
+#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                     0x07c3
+#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            1
+#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                     0x07c4
+#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            1
+#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                     0x07c5
+#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            1
+#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                     0x07c6
+#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            1
+#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                     0x07c7
+#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            1
+#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                     0x07c8
+#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            1
+#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                     0x07c9
+#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            1
+#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                     0x07ca
+#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            1
+#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                     0x07cb
+#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            1
+#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                     0x07cc
+#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            1
+#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                     0x07cd
+#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            1
+#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                     0x07ce
+#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            1
+#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                     0x07cf
+#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            1
+#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                     0x07d0
+#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            1
+#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                     0x07d1
+#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            1
+#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                     0x07d2
+#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            1
+#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                     0x07d3
+#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            1
+#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                     0x07d4
+#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            1
+#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                     0x07d5
+#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            1
+#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                     0x07d6
+#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            1
+#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                     0x07d7
+#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            1
+#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                     0x07d8
+#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            1
+#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                     0x07d9
+#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            1
+#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                     0x07da
+#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            1
+#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                     0x07db
+#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            1
+#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                     0x07dc
+#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            1
+#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                     0x07dd
+#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            1
+#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                     0x07de
+#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            1
+#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                    0x07df
+#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           1
+#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                    0x07e0
+#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           1
+#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                    0x07e1
+#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           1
+#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                    0x07e2
+#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           1
+#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                    0x07e3
+#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           1
+#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                    0x07e4
+#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           1
+#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                    0x07e5
+#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           1
+#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                    0x07e6
+#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           1
+#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                    0x07e7
+#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           1
+#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                    0x07e8
+#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           1
+#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                    0x07e9
+#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           1
+#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                    0x07ea
+#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           1
+#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                       0x07eb
+#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              1
+#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                       0x07ec
+#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              1
+#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                       0x07ed
+#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              1
+#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                       0x07ee
+#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              1
+#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                       0x07ef
+#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              1
+#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                       0x07f0
+#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              1
+#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                       0x07f1
+#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              1
+#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                       0x07f2
+#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              1
+#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                       0x07f3
+#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              1
+#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                       0x07f4
+#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              1
+#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                       0x07f5
+#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              1
+#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                       0x07f6
+#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              1
+#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                       0x07f7
+#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              1
+#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                       0x07f8
+#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              1
+#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                       0x07f9
+#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              1
+#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                       0x07fa
+#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              1
+#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                       0x07fb
+#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              1
+#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                       0x07fc
+#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              1
+#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                       0x07fd
+#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              1
+#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                       0x07fe
+#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              1
+#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                      0x07ff
+#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             1
+#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                      0x0800
+#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             1
+#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                      0x0801
+#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             1
+#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                      0x0802
+#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             1
+#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                      0x0803
+#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             1
+#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                      0x0804
+#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             1
+#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                      0x0805
+#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             1
+#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                      0x0806
+#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             1
+#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                      0x0807
+#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             1
+#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                      0x0808
+#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             1
+#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                      0x0809
+#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             1
+#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                      0x080a
+#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             1
+#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                                    0x080b
+#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                           1
+#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x080c
+#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  1
+#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x080d
+#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  1
+#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x080e
+#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  1
+#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x080f
+#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  1
+#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x0810
+#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  1
+#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x0811
+#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  1
+#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x0812
+#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  1
+#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x0813
+#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  1
+#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x0814
+#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  1
+#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x0815
+#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  1
+#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x0816
+#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 1
+#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x0817
+#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 1
+#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x0818
+#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 1
+#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x0819
+#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 1
+#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x081a
+#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 1
+#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x081b
+#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 1
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pldec
+// base address: 0x6a090
+#define regMMMC_VM_L2_PERFCOUNTER0_CFG                                                                  0x0824
+#define regMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX                                                         1
+#define regMMMC_VM_L2_PERFCOUNTER1_CFG                                                                  0x0825
+#define regMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX                                                         1
+#define regMMMC_VM_L2_PERFCOUNTER2_CFG                                                                  0x0826
+#define regMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX                                                         1
+#define regMMMC_VM_L2_PERFCOUNTER3_CFG                                                                  0x0827
+#define regMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX                                                         1
+#define regMMMC_VM_L2_PERFCOUNTER4_CFG                                                                  0x0828
+#define regMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX                                                         1
+#define regMMMC_VM_L2_PERFCOUNTER5_CFG                                                                  0x0829
+#define regMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX                                                         1
+#define regMMMC_VM_L2_PERFCOUNTER6_CFG                                                                  0x082a
+#define regMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX                                                         1
+#define regMMMC_VM_L2_PERFCOUNTER7_CFG                                                                  0x082b
+#define regMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX                                                         1
+#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL                                                             0x082c
+#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                    1
+#define regMMUTCL2_PERFCOUNTER0_CFG                                                                     0x082d
+#define regMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX                                                            1
+#define regMMUTCL2_PERFCOUNTER1_CFG                                                                     0x082e
+#define regMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX                                                            1
+#define regMMUTCL2_PERFCOUNTER2_CFG                                                                     0x082f
+#define regMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX                                                            1
+#define regMMUTCL2_PERFCOUNTER3_CFG                                                                     0x0830
+#define regMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX                                                            1
+#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL                                                                0x0831
+#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                       1
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2prdec
+// base address: 0x6a0e0
+#define regMMMC_VM_L2_PERFCOUNTER_LO                                                                    0x0838
+#define regMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX                                                           1
+#define regMMMC_VM_L2_PERFCOUNTER_HI                                                                    0x0839
+#define regMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX                                                           1
+#define regMMUTCL2_PERFCOUNTER_LO                                                                       0x083a
+#define regMMUTCL2_PERFCOUNTER_LO_BASE_IDX                                                              1
+#define regMMUTCL2_PERFCOUNTER_HI                                                                       0x083b
+#define regMMUTCL2_PERFCOUNTER_HI_BASE_IDX                                                              1
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec
+// base address: 0x6a130
+#define regMMVM_PCIE_ATS_CNTL                                                                           0x084c
+#define regMMVM_PCIE_ATS_CNTL_BASE_IDX                                                                  1
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec
+// base address: 0x6a340
+#define regMMMC_VM_NB_MMIOBASE                                                                          0x08d0
+#define regMMMC_VM_NB_MMIOBASE_BASE_IDX                                                                 1
+#define regMMMC_VM_NB_MMIOLIMIT                                                                         0x08d1
+#define regMMMC_VM_NB_MMIOLIMIT_BASE_IDX                                                                1
+#define regMMMC_VM_NB_PCI_CTRL                                                                          0x08d2
+#define regMMMC_VM_NB_PCI_CTRL_BASE_IDX                                                                 1
+#define regMMMC_VM_NB_PCI_ARB                                                                           0x08d3
+#define regMMMC_VM_NB_PCI_ARB_BASE_IDX                                                                  1
+#define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1                                                                 0x08d4
+#define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX                                                        1
+#define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2                                                                0x08d5
+#define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX                                                       1
+#define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2                                                                0x08d6
+#define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX                                                       1
+#define regMMMC_VM_FB_OFFSET                                                                            0x08d7
+#define regMMMC_VM_FB_OFFSET_BASE_IDX                                                                   1
+#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB                                                     0x08d8
+#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX                                            1
+#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB                                                     0x08d9
+#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX                                            1
+#define regMMMC_VM_STEERING                                                                             0x08da
+#define regMMMC_VM_STEERING_BASE_IDX                                                                    1
+#define regMMMC_SHARED_VIRT_RESET_REQ                                                                   0x08db
+#define regMMMC_SHARED_VIRT_RESET_REQ_BASE_IDX                                                          1
+#define regMMMC_MEM_POWER_LS                                                                            0x08dc
+#define regMMMC_MEM_POWER_LS_BASE_IDX                                                                   1
+#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START                                                         0x08dd
+#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX                                                1
+#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END                                                           0x08de
+#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX                                                  1
+#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START                                                           0x08df
+#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX                                                  1
+#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END                                                             0x08e0
+#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX                                                    1
+#define regMMMC_VM_APT_CNTL                                                                             0x08e1
+#define regMMMC_VM_APT_CNTL_BASE_IDX                                                                    1
+#define regMMMC_VM_LOCAL_FB_ADDRESS_START                                                               0x08e2
+#define regMMMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX                                                      1
+#define regMMMC_VM_LOCAL_FB_ADDRESS_END                                                                 0x08e3
+#define regMMMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX                                                        1
+#define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL                                                           0x08e4
+#define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX                                                  1
+#define regMMUTCL2_CGTT_CLK_CTRL                                                                        0x08e5
+#define regMMUTCL2_CGTT_CLK_CTRL_BASE_IDX                                                               1
+#define regMMMC_SHARED_ACTIVE_FCN_ID                                                                    0x08e6
+#define regMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX                                                           1
+#define regMMUTCL2_CGTT_BUSY_CTRL                                                                       0x08e7
+#define regMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX                                                              1
+#define regMMUTCL2_HARVEST_BYPASS_GROUPS                                                                0x08e8
+#define regMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX                                                       1
+#define regMMUTCL2_GROUP_RET_FAULT_STATUS                                                               0x08ea
+#define regMMUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX                                                      1
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec
+// base address: 0x6a3b0
+#define regMMMC_VM_FB_LOCATION_BASE                                                                     0x08ec
+#define regMMMC_VM_FB_LOCATION_BASE_BASE_IDX                                                            1
+#define regMMMC_VM_FB_LOCATION_TOP                                                                      0x08ed
+#define regMMMC_VM_FB_LOCATION_TOP_BASE_IDX                                                             1
+#define regMMMC_VM_AGP_TOP                                                                              0x08ee
+#define regMMMC_VM_AGP_TOP_BASE_IDX                                                                     1
+#define regMMMC_VM_AGP_BOT                                                                              0x08ef
+#define regMMMC_VM_AGP_BOT_BASE_IDX                                                                     1
+#define regMMMC_VM_AGP_BASE                                                                             0x08f0
+#define regMMMC_VM_AGP_BASE_BASE_IDX                                                                    1
+#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR                                                             0x08f1
+#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                                    1
+#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR                                                            0x08f2
+#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                                   1
+#define regMMMC_VM_MX_L1_TLB_CNTL                                                                       0x08f3
+#define regMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX                                                              1
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec
+// base address: 0x6a400
+#define regMM_ATC_L2_PERFCOUNTER_LO                                                                     0x0900
+#define regMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX                                                            1
+#define regMM_ATC_L2_PERFCOUNTER_HI                                                                     0x0901
+#define regMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX                                                            1
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec
+// base address: 0x6a420
+#define regMM_ATC_L2_PERFCOUNTER0_CFG                                                                   0x0908
+#define regMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX                                                          1
+#define regMM_ATC_L2_PERFCOUNTER1_CFG                                                                   0x0909
+#define regMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX                                                          1
+#define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL                                                              0x090a
+#define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                     1
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pspdec
+// base address: 0x6aa50
+#define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID                                                           0x0a94
+#define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX                                                  1
+#define regMMVM_IOMMU_CONTROL_REGISTER                                                                  0x0a97
+#define regMMVM_IOMMU_CONTROL_REGISTER_BASE_IDX                                                         1
+#define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER                                         0x0a98
+#define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX                                1
+#define regMMUTC_TRANSLATION_FAULT_CNTL0                                                                0x0a99
+#define regMMUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX                                                       1
+#define regMMUTC_TRANSLATION_FAULT_CNTL1                                                                0x0a9a
+#define regMMUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX                                                       1
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbpspdec
+// base address: 0x6aa80
+#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL                                                     0x0aa0
+#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX                                            1
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pspdec
+// base address: 0x6aa90
+#define regMM_ATC_L2_IOV_MODE_CNTL                                                                      0x0aa4
+#define regMM_ATC_L2_IOV_MODE_CNTL_BASE_IDX                                                             1
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbpfdec
+// base address: 0x6aac0
+#define regMML2TLB_TLB0_STATUS                                                                          0x0ab1
+#define regMML2TLB_TLB0_STATUS_BASE_IDX                                                                 1
+#define regMML2TLB_TMZ_CNTL                                                                             0x0ab2
+#define regMML2TLB_TMZ_CNTL_BASE_IDX                                                                    1
+#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO                                               0x0ab3
+#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX                                      1
+#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI                                               0x0ab4
+#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX                                      1
+#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO                                              0x0ab5
+#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX                                     1
+#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI                                              0x0ab6
+#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX                                     1
+#define regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ                                                      0x0ab7
+#define regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX                                             1
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbpldec
+// base address: 0x6ab00
+#define regMML2TLB_PERFCOUNTER0_CFG                                                                     0x0ac0
+#define regMML2TLB_PERFCOUNTER0_CFG_BASE_IDX                                                            1
+#define regMML2TLB_PERFCOUNTER1_CFG                                                                     0x0ac1
+#define regMML2TLB_PERFCOUNTER1_CFG_BASE_IDX                                                            1
+#define regMML2TLB_PERFCOUNTER2_CFG                                                                     0x0ac2
+#define regMML2TLB_PERFCOUNTER2_CFG_BASE_IDX                                                            1
+#define regMML2TLB_PERFCOUNTER3_CFG                                                                     0x0ac3
+#define regMML2TLB_PERFCOUNTER3_CFG_BASE_IDX                                                            1
+#define regMML2TLB_PERFCOUNTER_RSLT_CNTL                                                                0x0ac4
+#define regMML2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                       1
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbprdec
+// base address: 0x6ab20
+#define regMML2TLB_PERFCOUNTER_LO                                                                       0x0ac8
+#define regMML2TLB_PERFCOUNTER_LO_BASE_IDX                                                              1
+#define regMML2TLB_PERFCOUNTER_HI                                                                       0x0ac9
+#define regMML2TLB_PERFCOUNTER_HI_BASE_IDX                                                              1
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_sh_mask.h
new file mode 100644
index 0000000000000..f949666f0667a
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_sh_mask.h
@@ -0,0 +1,7483 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _mmhub_3_0_1_SH_MASK_HEADER
+#define _mmhub_3_0_1_SH_MASK_HEADER
+
+
+// addressBlock: mmhub_dagbdec
+//DAGB0_RDCLI0
+#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_RDCLI0__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_RDCLI0__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_RDCLI0__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_RDCLI1
+#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_RDCLI1__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_RDCLI1__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_RDCLI1__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_RDCLI2
+#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_RDCLI2__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_RDCLI2__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_RDCLI2__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_RDCLI3
+#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_RDCLI3__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_RDCLI3__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_RDCLI3__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_RDCLI4
+#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_RDCLI4__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_RDCLI4__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_RDCLI4__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_RDCLI5
+#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_RDCLI5__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_RDCLI5__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_RDCLI5__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_RDCLI6
+#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_RDCLI6__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_RDCLI6__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_RDCLI6__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_RDCLI7
+#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_RDCLI7__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_RDCLI7__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_RDCLI7__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_RDCLI8
+#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_RDCLI8__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_RDCLI8__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_RDCLI8__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_RDCLI9
+#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_RDCLI9__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_RDCLI9__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_RDCLI9__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_RDCLI10
+#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI10__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI10__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI10__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI11
+#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI11__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI11__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI11__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI12
+#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI12__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI12__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI12__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI13
+#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI13__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI13__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI13__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI14
+#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI14__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI14__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI14__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI15
+#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI15__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI15__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI15__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI16
+#define DAGB0_RDCLI16__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI16__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI16__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI16__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI16__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI16__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI16__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI16__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI16__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI16__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI16__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI16__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI17
+#define DAGB0_RDCLI17__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI17__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI17__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI17__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI17__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI17__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI17__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI17__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI17__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI17__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI17__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI17__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI18
+#define DAGB0_RDCLI18__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI18__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI18__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI18__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI18__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI18__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI18__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI18__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI18__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI18__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI18__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI18__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI19
+#define DAGB0_RDCLI19__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI19__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI19__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI19__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI19__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI19__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI19__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI19__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI19__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI19__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI19__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI19__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI19__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI19__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI20
+#define DAGB0_RDCLI20__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI20__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI20__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI20__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI20__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI20__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI20__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI20__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI20__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI20__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI20__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI20__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI20__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI20__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI21
+#define DAGB0_RDCLI21__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI21__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI21__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI21__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI21__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI21__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI21__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI21__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI21__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI21__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI21__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI21__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI21__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI21__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI22
+#define DAGB0_RDCLI22__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI22__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI22__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI22__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI22__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI22__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI22__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI22__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI22__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI22__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI22__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI22__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI22__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI22__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI23
+#define DAGB0_RDCLI23__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI23__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI23__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI23__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI23__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI23__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI23__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI23__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI23__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI23__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI23__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI23__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI23__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI23__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI24
+#define DAGB0_RDCLI24__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI24__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI24__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI24__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI24__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI24__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI24__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI24__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI24__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI24__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI24__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI24__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI24__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI24__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI24__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI24__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI24__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI24__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI24__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI24__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI25
+#define DAGB0_RDCLI25__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI25__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI25__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI25__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI25__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI25__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI25__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI25__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI25__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI25__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI25__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI25__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI25__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI25__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI25__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI25__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI25__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI25__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI25__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI25__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI26
+#define DAGB0_RDCLI26__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI26__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI26__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI26__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI26__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI26__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI26__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI26__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI26__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI26__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI26__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI26__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI26__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI26__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI26__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI26__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI26__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI26__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI26__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI26__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI27
+#define DAGB0_RDCLI27__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI27__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI27__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI27__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI27__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI27__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI27__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI27__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI27__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI27__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI27__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI27__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI27__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI27__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI27__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI27__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI27__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI27__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI27__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI27__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI28
+#define DAGB0_RDCLI28__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI28__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI28__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI28__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI28__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI28__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI28__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI28__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI28__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI28__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI28__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI28__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI28__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI28__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI28__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI28__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI28__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI28__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI28__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI28__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI29
+#define DAGB0_RDCLI29__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI29__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI29__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI29__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI29__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI29__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI29__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI29__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI29__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI29__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI29__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI29__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI29__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI29__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI29__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI29__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI29__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI29__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI29__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI29__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RD_CNTL
+#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x0
+#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0x6
+#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0xc
+#define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT                                                                0xf
+#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x0000003FL
+#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x00000FC0L
+#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x00007000L
+#define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN_MASK                                                                  0x00008000L
+//DAGB0_RD_IO_CNTL
+#define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT                                                             0x0
+#define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT                                                           0x1
+#define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT                                                          0x4
+#define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT                                                             0x9
+#define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT                                                           0xa
+#define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT                                                          0xd
+#define DAGB0_RD_IO_CNTL__COMMON_PRIORITY__SHIFT                                                              0x12
+#define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK                                                               0x00000001L
+#define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK                                                             0x0000000EL
+#define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK                                                            0x000001F0L
+#define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK                                                               0x00000200L
+#define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK                                                             0x00001C00L
+#define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK                                                            0x0003E000L
+#define DAGB0_RD_IO_CNTL__COMMON_PRIORITY_MASK                                                                0x001C0000L
+//DAGB0_RD_GMI_CNTL
+#define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT                                                            0x0
+#define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT                                                          0x1
+#define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT                                                         0x4
+#define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT                                                            0x9
+#define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT                                                          0xa
+#define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT                                                         0xd
+#define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT                                                             0x12
+#define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK                                                              0x00000001L
+#define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK                                                            0x0000000EL
+#define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK                                                           0x000001F0L
+#define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK                                                              0x00000200L
+#define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK                                                            0x00001C00L
+#define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK                                                           0x0003E000L
+#define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY_MASK                                                               0x001C0000L
+//DAGB0_RD_ADDR_DAGB
+#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
+#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
+#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
+#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
+#define DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT                                                                  0xd
+#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
+#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
+#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
+#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
+#define DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK                                                                    0x00002000L
+//DAGB0_RD_CGTT_CLK_CTRL
+#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
+#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x5
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT                                                   0xd
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT                                                             0x1e
+#define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT                                                          0x1f
+#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000001FL
+#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00001FE0L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK                                                     0x1FFFE000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK                                                               0x40000000L
+#define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK                                                            0x80000000L
+//DAGB0_L1TLB_RD_CGTT_CLK_CTRL
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x5
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT                                             0xd
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT                                                       0x1e
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT                                                    0x1f
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000001FL
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00001FE0L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK                                               0x1FFFE000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK                                                         0x40000000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK                                                      0x80000000L
+//DAGB0_RD_ADDR_DAGB_MAX_BURST0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
+//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
+//DAGB0_RD_ADDR_DAGB_MAX_BURST1
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
+//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
+//DAGB0_RD_ADDR_DAGB_MAX_BURST2
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT                                                        0x0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT                                                        0x4
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT                                                        0x8
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT                                                        0xc
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT                                                        0x10
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT                                                        0x14
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT                                                        0x18
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT                                                        0x1c
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK                                                          0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK                                                          0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK                                                          0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK                                                          0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK                                                          0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK                                                          0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK                                                          0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK                                                          0xF0000000L
+//DAGB0_RD_ADDR_DAGB_LAZY_TIMER2
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT                                                       0x0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT                                                       0x4
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT                                                       0x8
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT                                                       0xc
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT                                                       0x10
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT                                                       0x14
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT                                                       0x18
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT                                                       0x1c
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK                                                         0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK                                                         0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK                                                         0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK                                                         0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK                                                         0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK                                                         0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK                                                         0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK                                                         0xF0000000L
+//DAGB0_RD_ADDR_DAGB_MAX_BURST3
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT                                                        0x0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT                                                        0x4
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT                                                        0x8
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT                                                        0xc
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT                                                        0x10
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT                                                        0x14
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT                                                        0x18
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT                                                        0x1c
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK                                                          0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK                                                          0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK                                                          0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK                                                          0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK                                                          0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK                                                          0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK                                                          0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK                                                          0xF0000000L
+//DAGB0_RD_ADDR_DAGB_LAZY_TIMER3
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT                                                       0x0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT                                                       0x4
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT                                                       0x8
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT                                                       0xc
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT                                                       0x10
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT                                                       0x14
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT                                                       0x18
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT                                                       0x1c
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK                                                         0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK                                                         0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK                                                         0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK                                                         0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK                                                         0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK                                                         0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK                                                         0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK                                                         0xF0000000L
+//DAGB0_RD_VC0_CNTL
+#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_RD_VC1_CNTL
+#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_RD_VC2_CNTL
+#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_RD_VC3_CNTL
+#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_RD_VC4_CNTL
+#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_RD_VC5_CNTL
+#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_RD_IO_VC_CNTL
+#define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT                                                             0x0
+#define DAGB0_RD_IO_VC_CNTL__MAX_BW__SHIFT                                                                    0xc
+#define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT                                                             0x14
+#define DAGB0_RD_IO_VC_CNTL__MIN_BW__SHIFT                                                                    0x15
+#define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                        0x18
+#define DAGB0_RD_IO_VC_CNTL__MAX_OSD__SHIFT                                                                   0x19
+#define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK                                                               0x00000001L
+#define DAGB0_RD_IO_VC_CNTL__MAX_BW_MASK                                                                      0x000FF000L
+#define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK                                                               0x00100000L
+#define DAGB0_RD_IO_VC_CNTL__MIN_BW_MASK                                                                      0x00E00000L
+#define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK                                                          0x01000000L
+#define DAGB0_RD_IO_VC_CNTL__MAX_OSD_MASK                                                                     0xFE000000L
+//DAGB0_RD_GMI_VC_CNTL
+#define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT                                                            0x0
+#define DAGB0_RD_GMI_VC_CNTL__MAX_BW__SHIFT                                                                   0xc
+#define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT                                                            0x14
+#define DAGB0_RD_GMI_VC_CNTL__MIN_BW__SHIFT                                                                   0x15
+#define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                       0x18
+#define DAGB0_RD_GMI_VC_CNTL__MAX_OSD__SHIFT                                                                  0x19
+#define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK                                                              0x00000001L
+#define DAGB0_RD_GMI_VC_CNTL__MAX_BW_MASK                                                                     0x000FF000L
+#define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK                                                              0x00100000L
+#define DAGB0_RD_GMI_VC_CNTL__MIN_BW_MASK                                                                     0x00E00000L
+#define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK                                                         0x01000000L
+#define DAGB0_RD_GMI_VC_CNTL__MAX_OSD_MASK                                                                    0xFE000000L
+//DAGB0_RD_CNTL_MISC
+#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
+#define DAGB0_RD_CNTL_MISC__UTCL2_VCI__SHIFT                                                                  0x6
+#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
+#define DAGB0_RD_CNTL_MISC__UTCL2_VCI_MASK                                                                    0x000001C0L
+//DAGB0_RD_TLB_CREDIT
+#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
+#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
+#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
+#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
+#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
+#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
+#define DAGB0_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
+#define DAGB0_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
+#define DAGB0_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
+#define DAGB0_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
+#define DAGB0_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
+#define DAGB0_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
+//DAGB0_RDCLI_ASK_PENDING
+#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
+#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
+//DAGB0_RDCLI_GO_PENDING
+#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
+#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
+//DAGB0_RDCLI_GBLSEND_PENDING
+#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
+#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
+//DAGB0_RDCLI_TLB_PENDING
+#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
+#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
+//DAGB0_RDCLI_OARB_PENDING
+#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
+#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
+//DAGB0_RDCLI_ASK2ARB_PENDING
+#define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT                                                              0x0
+#define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
+//DAGB0_RDCLI_ASK2DF_PENDING
+#define DAGB0_RDCLI_ASK2DF_PENDING__BUSY__SHIFT                                                               0x0
+#define DAGB0_RDCLI_ASK2DF_PENDING__BUSY_MASK                                                                 0xFFFFFFFFL
+//DAGB0_RDCLI_OSD_PENDING
+#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
+#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
+//DAGB0_RDCLI_ASK_OSD_PENDING
+#define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT                                                              0x0
+#define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
+//DAGB0_WRCLI0
+#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_WRCLI0__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_WRCLI0__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_WRCLI0__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_WRCLI1
+#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_WRCLI1__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_WRCLI1__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_WRCLI1__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_WRCLI2
+#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_WRCLI2__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_WRCLI2__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_WRCLI2__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_WRCLI3
+#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_WRCLI3__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_WRCLI3__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_WRCLI3__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_WRCLI4
+#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_WRCLI4__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_WRCLI4__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_WRCLI4__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_WRCLI5
+#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_WRCLI5__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_WRCLI5__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_WRCLI5__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_WRCLI6
+#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_WRCLI6__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_WRCLI6__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_WRCLI6__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_WRCLI7
+#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_WRCLI7__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_WRCLI7__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_WRCLI7__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_WRCLI8
+#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_WRCLI8__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_WRCLI8__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_WRCLI8__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_WRCLI9
+#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_WRCLI9__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_WRCLI9__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_WRCLI9__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_WRCLI10
+#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI10__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI10__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI10__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI11
+#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI11__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI11__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI11__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI12
+#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI12__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI12__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI12__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI13
+#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI13__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI13__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI13__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI14
+#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI14__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI14__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI14__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI15
+#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI15__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI15__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI15__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI16
+#define DAGB0_WRCLI16__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI16__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI16__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI16__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI16__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI16__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI16__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI16__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI16__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI16__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI16__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI16__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI17
+#define DAGB0_WRCLI17__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI17__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI17__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI17__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI17__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI17__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI17__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI17__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI17__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI17__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI17__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI17__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI18
+#define DAGB0_WRCLI18__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI18__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI18__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI18__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI18__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI18__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI18__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI18__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI18__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI18__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI18__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI18__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI19
+#define DAGB0_WRCLI19__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI19__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI19__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI19__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI19__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI19__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI19__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI19__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI19__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI19__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI19__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI19__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI19__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI19__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI20
+#define DAGB0_WRCLI20__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI20__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI20__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI20__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI20__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI20__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI20__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI20__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI20__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI20__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI20__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI20__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI20__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI20__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI21
+#define DAGB0_WRCLI21__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI21__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI21__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI21__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI21__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI21__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI21__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI21__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI21__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI21__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI21__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI21__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI21__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI21__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI22
+#define DAGB0_WRCLI22__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI22__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI22__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI22__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI22__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI22__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI22__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI22__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI22__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI22__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI22__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI22__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI22__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI22__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI23
+#define DAGB0_WRCLI23__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI23__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI23__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI23__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI23__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI23__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI23__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI23__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI23__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI23__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI23__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI23__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI23__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI23__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI24
+#define DAGB0_WRCLI24__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI24__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI24__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI24__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI24__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI24__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI24__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI24__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI24__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI24__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI24__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI24__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI24__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI24__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI24__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI24__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI24__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI24__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI24__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI24__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI25
+#define DAGB0_WRCLI25__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI25__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI25__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI25__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI25__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI25__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI25__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI25__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI25__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI25__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI25__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI25__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI25__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI25__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI25__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI25__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI25__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI25__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI25__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI25__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI26
+#define DAGB0_WRCLI26__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI26__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI26__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI26__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI26__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI26__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI26__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI26__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI26__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI26__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI26__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI26__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI26__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI26__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI26__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI26__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI26__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI26__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI26__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI26__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI27
+#define DAGB0_WRCLI27__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI27__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI27__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI27__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI27__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI27__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI27__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI27__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI27__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI27__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI27__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI27__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI27__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI27__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI27__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI27__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI27__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI27__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI27__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI27__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI28
+#define DAGB0_WRCLI28__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI28__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI28__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI28__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI28__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI28__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI28__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI28__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI28__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI28__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI28__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI28__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI28__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI28__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI28__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI28__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI28__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI28__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI28__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI28__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI29
+#define DAGB0_WRCLI29__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI29__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI29__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI29__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI29__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI29__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI29__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI29__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI29__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI29__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI29__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI29__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI29__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI29__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI29__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI29__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI29__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI29__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI29__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI29__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WR_CNTL
+#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x0
+#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0x6
+#define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN__SHIFT                                                                0xc
+#define DAGB0_WR_CNTL__UPDATE_FED__SHIFT                                                                      0xd
+#define DAGB0_WR_CNTL__UPDATE_NACK__SHIFT                                                                     0xe
+#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x0000003FL
+#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x00000FC0L
+#define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN_MASK                                                                  0x00001000L
+#define DAGB0_WR_CNTL__UPDATE_FED_MASK                                                                        0x00002000L
+#define DAGB0_WR_CNTL__UPDATE_NACK_MASK                                                                       0x00004000L
+//DAGB0_WR_IO_CNTL
+#define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE__SHIFT                                                             0x0
+#define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT                                                           0x1
+#define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT                                                          0x4
+#define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE__SHIFT                                                             0x9
+#define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT                                                           0xa
+#define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT                                                          0xd
+#define DAGB0_WR_IO_CNTL__COMMON_PRIORITY__SHIFT                                                              0x12
+#define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE_MASK                                                               0x00000001L
+#define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY_MASK                                                             0x0000000EL
+#define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK                                                            0x000001F0L
+#define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE_MASK                                                               0x00000200L
+#define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY_MASK                                                             0x00001C00L
+#define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK                                                            0x0003E000L
+#define DAGB0_WR_IO_CNTL__COMMON_PRIORITY_MASK                                                                0x001C0000L
+//DAGB0_WR_GMI_CNTL
+#define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT                                                            0x0
+#define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT                                                          0x1
+#define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT                                                         0x4
+#define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT                                                            0x9
+#define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT                                                          0xa
+#define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT                                                         0xd
+#define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY__SHIFT                                                             0x12
+#define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE_MASK                                                              0x00000001L
+#define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY_MASK                                                            0x0000000EL
+#define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK                                                           0x000001F0L
+#define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE_MASK                                                              0x00000200L
+#define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY_MASK                                                            0x00001C00L
+#define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK                                                           0x0003E000L
+#define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY_MASK                                                               0x001C0000L
+//DAGB0_WR_ADDR_DAGB
+#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
+#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
+#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
+#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
+#define DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT                                                                  0xd
+#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
+#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
+#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
+#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
+#define DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK                                                                    0x00002000L
+//DAGB0_WR_CGTT_CLK_CTRL
+#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
+#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x5
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT                                                   0xd
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT                                                             0x1e
+#define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT                                                          0x1f
+#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000001FL
+#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00001FE0L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK                                                     0x1FFFE000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK                                                               0x40000000L
+#define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK                                                            0x80000000L
+//DAGB0_L1TLB_WR_CGTT_CLK_CTRL
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x5
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT                                             0xd
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT                                                       0x1e
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT                                                    0x1f
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000001FL
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00001FE0L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK                                               0x1FFFE000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK                                                         0x40000000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK                                                      0x80000000L
+//DAGB0_WR_ADDR_DAGB_MAX_BURST0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
+//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
+//DAGB0_WR_ADDR_DAGB_MAX_BURST1
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
+//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
+//DAGB0_WR_ADDR_DAGB_MAX_BURST2
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT                                                        0x0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT                                                        0x4
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT                                                        0x8
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT                                                        0xc
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT                                                        0x10
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT                                                        0x14
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT                                                        0x18
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT                                                        0x1c
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK                                                          0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK                                                          0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK                                                          0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK                                                          0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK                                                          0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK                                                          0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK                                                          0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK                                                          0xF0000000L
+//DAGB0_WR_ADDR_DAGB_LAZY_TIMER2
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT                                                       0x0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT                                                       0x4
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT                                                       0x8
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT                                                       0xc
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT                                                       0x10
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT                                                       0x14
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT                                                       0x18
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT                                                       0x1c
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK                                                         0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK                                                         0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK                                                         0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK                                                         0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK                                                         0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK                                                         0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK                                                         0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK                                                         0xF0000000L
+//DAGB0_WR_ADDR_DAGB_MAX_BURST3
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT                                                        0x0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT                                                        0x4
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT                                                        0x8
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT                                                        0xc
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT                                                        0x10
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT                                                        0x14
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT                                                        0x18
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT                                                        0x1c
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK                                                          0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK                                                          0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK                                                          0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK                                                          0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK                                                          0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK                                                          0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK                                                          0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK                                                          0xF0000000L
+//DAGB0_WR_ADDR_DAGB_LAZY_TIMER3
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT                                                       0x0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT                                                       0x4
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT                                                       0x8
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT                                                       0xc
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT                                                       0x10
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT                                                       0x14
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT                                                       0x18
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT                                                       0x1c
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK                                                         0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK                                                         0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK                                                         0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK                                                         0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK                                                         0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK                                                         0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK                                                         0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK                                                         0xF0000000L
+//DAGB0_WR_DATA_DAGB
+#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
+#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
+#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
+#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
+#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
+#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
+#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
+#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
+//DAGB0_WR_DATA_DAGB_MAX_BURST0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
+//DAGB0_WR_DATA_DAGB_LAZY_TIMER0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
+//DAGB0_WR_DATA_DAGB_MAX_BURST1
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
+//DAGB0_WR_DATA_DAGB_LAZY_TIMER1
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
+//DAGB0_WR_DATA_DAGB_MAX_BURST2
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT                                                        0x0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT                                                        0x4
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT                                                        0x8
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT                                                        0xc
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT                                                        0x10
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT                                                        0x14
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT                                                        0x18
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT                                                        0x1c
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK                                                          0x0000000FL
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK                                                          0x000000F0L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK                                                          0x00000F00L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK                                                          0x0000F000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK                                                          0x000F0000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK                                                          0x00F00000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK                                                          0x0F000000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK                                                          0xF0000000L
+//DAGB0_WR_DATA_DAGB_LAZY_TIMER2
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT                                                       0x0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT                                                       0x4
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT                                                       0x8
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT                                                       0xc
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT                                                       0x10
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT                                                       0x14
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT                                                       0x18
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT                                                       0x1c
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK                                                         0x0000000FL
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK                                                         0x000000F0L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK                                                         0x00000F00L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK                                                         0x0000F000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK                                                         0x000F0000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK                                                         0x00F00000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK                                                         0x0F000000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK                                                         0xF0000000L
+//DAGB0_WR_DATA_DAGB_MAX_BURST3
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24__SHIFT                                                        0x0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25__SHIFT                                                        0x4
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26__SHIFT                                                        0x8
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27__SHIFT                                                        0xc
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28__SHIFT                                                        0x10
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29__SHIFT                                                        0x14
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30__SHIFT                                                        0x18
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31__SHIFT                                                        0x1c
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24_MASK                                                          0x0000000FL
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25_MASK                                                          0x000000F0L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26_MASK                                                          0x00000F00L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27_MASK                                                          0x0000F000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28_MASK                                                          0x000F0000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29_MASK                                                          0x00F00000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30_MASK                                                          0x0F000000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31_MASK                                                          0xF0000000L
+//DAGB0_WR_DATA_DAGB_LAZY_TIMER3
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24__SHIFT                                                       0x0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25__SHIFT                                                       0x4
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26__SHIFT                                                       0x8
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27__SHIFT                                                       0xc
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28__SHIFT                                                       0x10
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29__SHIFT                                                       0x14
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30__SHIFT                                                       0x18
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31__SHIFT                                                       0x1c
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24_MASK                                                         0x0000000FL
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25_MASK                                                         0x000000F0L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26_MASK                                                         0x00000F00L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27_MASK                                                         0x0000F000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28_MASK                                                         0x000F0000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29_MASK                                                         0x00F00000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30_MASK                                                         0x0F000000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31_MASK                                                         0xF0000000L
+//DAGB0_WR_VC0_CNTL
+#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_WR_VC1_CNTL
+#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_WR_VC2_CNTL
+#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_WR_VC3_CNTL
+#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_WR_VC4_CNTL
+#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_WR_VC5_CNTL
+#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_WR_IO_VC_CNTL
+#define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT                                                             0x0
+#define DAGB0_WR_IO_VC_CNTL__MAX_BW__SHIFT                                                                    0xc
+#define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT                                                             0x14
+#define DAGB0_WR_IO_VC_CNTL__MIN_BW__SHIFT                                                                    0x15
+#define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                        0x18
+#define DAGB0_WR_IO_VC_CNTL__MAX_OSD__SHIFT                                                                   0x19
+#define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE_MASK                                                               0x00000001L
+#define DAGB0_WR_IO_VC_CNTL__MAX_BW_MASK                                                                      0x000FF000L
+#define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE_MASK                                                               0x00100000L
+#define DAGB0_WR_IO_VC_CNTL__MIN_BW_MASK                                                                      0x00E00000L
+#define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK                                                          0x01000000L
+#define DAGB0_WR_IO_VC_CNTL__MAX_OSD_MASK                                                                     0xFE000000L
+//DAGB0_WR_GMI_VC_CNTL
+#define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT                                                            0x0
+#define DAGB0_WR_GMI_VC_CNTL__MAX_BW__SHIFT                                                                   0xc
+#define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT                                                            0x14
+#define DAGB0_WR_GMI_VC_CNTL__MIN_BW__SHIFT                                                                   0x15
+#define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                       0x18
+#define DAGB0_WR_GMI_VC_CNTL__MAX_OSD__SHIFT                                                                  0x19
+#define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE_MASK                                                              0x00000001L
+#define DAGB0_WR_GMI_VC_CNTL__MAX_BW_MASK                                                                     0x000FF000L
+#define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE_MASK                                                              0x00100000L
+#define DAGB0_WR_GMI_VC_CNTL__MIN_BW_MASK                                                                     0x00E00000L
+#define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK                                                         0x01000000L
+#define DAGB0_WR_GMI_VC_CNTL__MAX_OSD_MASK                                                                    0xFE000000L
+//DAGB0_WR_CNTL_MISC
+#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
+#define DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT                                                                    0x6
+#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
+#define DAGB0_WR_CNTL_MISC__HDP_CID_MASK                                                                      0x000007C0L
+//DAGB0_WR_TLB_CREDIT
+#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
+#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
+#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
+#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
+#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
+#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
+#define DAGB0_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
+#define DAGB0_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
+#define DAGB0_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
+#define DAGB0_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
+#define DAGB0_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
+#define DAGB0_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
+//DAGB0_WR_DATA_CREDIT
+#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
+#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
+#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
+#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
+#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
+#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
+#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
+#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
+//DAGB0_WR_MISC_CREDIT
+#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
+#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
+#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
+#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
+//DAGB0_WR_DATA_FIFO_CREDIT_CNTL1
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT                                                    0x0
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT                                                    0x5
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT                                                    0xa
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT                                                    0xf
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT                                                   0x14
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT                                                       0x19
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT                                                        0x1a
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0__SHIFT                                                          0x1b
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK                                                      0x0000001FL
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK                                                      0x000003E0L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK                                                      0x00007C00L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK                                                      0x000F8000L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK                                                     0x01F00000L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE_MASK                                                         0x02000000L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ_MASK                                                          0x04000000L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0_MASK                                                            0x08000000L
+//DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT                                                  0x0
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT                                                  0x5
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT                                                  0xa
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT                                                  0xf
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT                                                 0x14
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT                                                     0x1a
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT                                                      0x1b
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT                                                        0x1c
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK                                                    0x0000001FL
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK                                                    0x000003E0L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK                                                    0x00007C00L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK                                                    0x000F8000L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK                                                   0x03F00000L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK                                                       0x04000000L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK                                                        0x08000000L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK                                                          0x10000000L
+//DAGB0_WRCLI_ASK_PENDING
+#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
+#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
+//DAGB0_WRCLI_GO_PENDING
+#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
+#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
+//DAGB0_WRCLI_GBLSEND_PENDING
+#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
+#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
+//DAGB0_WRCLI_TLB_PENDING
+#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
+#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
+//DAGB0_WRCLI_OARB_PENDING
+#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
+#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
+//DAGB0_WRCLI_ASK2ARB_PENDING
+#define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY__SHIFT                                                              0x0
+#define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
+//DAGB0_WRCLI_ASK2DF_PENDING
+#define DAGB0_WRCLI_ASK2DF_PENDING__BUSY__SHIFT                                                               0x0
+#define DAGB0_WRCLI_ASK2DF_PENDING__BUSY_MASK                                                                 0xFFFFFFFFL
+//DAGB0_WRCLI_OSD_PENDING
+#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
+#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
+//DAGB0_WRCLI_ASK_OSD_PENDING
+#define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY__SHIFT                                                              0x0
+#define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
+//DAGB0_WRCLI_DBUS_ASK_PENDING
+#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
+#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
+//DAGB0_WRCLI_DBUS_GO_PENDING
+#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
+#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
+//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE
+#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT                                                         0x0
+#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK                                                           0xFFFFFFFFL
+//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE
+#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT                                                   0x0
+#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK                                                     0xFFFFFFFFL
+//DAGB0_DAGB_DLY
+#define DAGB0_DAGB_DLY__DLY__SHIFT                                                                            0x0
+#define DAGB0_DAGB_DLY__CLI__SHIFT                                                                            0x8
+#define DAGB0_DAGB_DLY__POS__SHIFT                                                                            0x10
+#define DAGB0_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
+#define DAGB0_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
+#define DAGB0_DAGB_DLY__POS_MASK                                                                              0x000F0000L
+//DAGB0_CNTL_MISC
+#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x0
+#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x0000003FL
+//DAGB0_CNTL_MISC2
+#define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT                                                             0x0
+#define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT                                                             0x1
+#define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT                                                          0x2
+#define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT                                                          0x3
+#define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT                                                            0x4
+#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0x5
+#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT                                                          0x6
+#define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT                                                      0x7
+#define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT                                                       0x8
+#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0x9
+#define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT                                                 0xa
+#define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT                                                 0xb
+#define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK                                                               0x00000001L
+#define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK                                                               0x00000002L
+#define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK                                                            0x00000004L
+#define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK                                                            0x00000008L
+#define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK                                                              0x00000010L
+#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000020L
+#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK                                                            0x00000040L
+#define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK                                                        0x00000080L
+#define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK                                                         0x00000100L
+#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000200L
+#define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK                                                   0x00000400L
+#define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK                                                   0x00000800L
+//DAGB0_FIFO_EMPTY
+#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
+#define DAGB0_FIFO_EMPTY__EMPTY_MASK                                                                          0x0001FFFFL
+//DAGB0_FIFO_FULL
+#define DAGB0_FIFO_FULL__FULL__SHIFT                                                                          0x0
+#define DAGB0_FIFO_FULL__FULL_MASK                                                                            0x0000FFFFL
+//DAGB0_RD_CREDITS_FULL
+#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
+#define DAGB0_RD_CREDITS_FULL__FULL_MASK                                                                      0x0000007FL
+//DAGB0_WR_CREDITS_FULL
+#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
+#define DAGB0_WR_CREDITS_FULL__FULL_MASK                                                                      0x0001FFFFL
+//DAGB0_PERFCOUNTER_LO
+#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
+#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
+//DAGB0_PERFCOUNTER_HI
+#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
+#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
+#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
+#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
+//DAGB0_PERFCOUNTER0_CFG
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
+#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
+#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
+#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
+#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
+#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
+#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
+//DAGB0_PERFCOUNTER1_CFG
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
+#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
+#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
+#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
+#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
+#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
+#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
+//DAGB0_PERFCOUNTER2_CFG
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
+#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
+#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
+#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
+#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
+#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
+#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
+//DAGB0_PERFCOUNTER_RSLT_CNTL
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x00000003L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
+//DAGB0_L1TLB_REG_RW
+#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT                                                       0x0
+#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT                                                        0x1
+#define DAGB0_L1TLB_REG_RW__RESERVE__SHIFT                                                                    0x2
+#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK                                                         0x00000001L
+#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK                                                          0x00000002L
+#define DAGB0_L1TLB_REG_RW__RESERVE_MASK                                                                      0x3FFFFFFCL
+//DAGB0_RESERVE1
+#define DAGB0_RESERVE1__RESERVE__SHIFT                                                                        0x0
+#define DAGB0_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
+//DAGB0_RESERVE2
+#define DAGB0_RESERVE2__RESERVE__SHIFT                                                                        0x0
+#define DAGB0_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
+//DAGB0_RESERVE3
+#define DAGB0_RESERVE3__RESERVE__SHIFT                                                                        0x0
+#define DAGB0_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
+//DAGB0_RESERVE4
+#define DAGB0_RESERVE4__RESERVE__SHIFT                                                                        0x0
+#define DAGB0_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL
+//DAGB0_SDP_RD_BW_CNTL
+#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT                                                            0x0
+#define DAGB0_SDP_RD_BW_CNTL__MAX_BW__SHIFT                                                                   0x1
+#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT                                                            0x9
+#define DAGB0_SDP_RD_BW_CNTL__MIN_BW__SHIFT                                                                   0xa
+#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT                                                            0xd
+#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK                                                              0x00000001L
+#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_MASK                                                                     0x000001FEL
+#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK                                                              0x00000200L
+#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_MASK                                                                     0x00001C00L
+#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK                                                              0x0007E000L
+//DAGB0_SDP_PRIORITY_OVERRIDE
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT                                                0x0
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT                                               0x4
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT                                          0x9
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT                                          0xa
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT                                           0xb
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT                                           0xc
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT                                            0xd
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT                                            0xe
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT                                                0x10
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT                                               0x14
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT                                          0x19
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT                                          0x1a
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT                                           0x1b
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT                                           0x1c
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT                                            0x1d
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT                                            0x1e
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK                                                  0x0000000FL
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK                                                 0x000001F0L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK                                            0x00000200L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK                                            0x00000400L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK                                             0x00000800L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK                                             0x00001000L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK                                              0x00002000L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK                                              0x00004000L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK                                                  0x000F0000L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK                                                 0x01F00000L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK                                            0x02000000L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK                                            0x04000000L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK                                             0x08000000L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK                                             0x10000000L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK                                              0x20000000L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK                                              0x40000000L
+//DAGB0_SDP_RD_PRIORITY
+#define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT                                                         0x0
+#define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT                                                         0x4
+#define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT                                                         0x8
+#define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT                                                         0xc
+#define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT                                                         0x10
+#define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT                                                         0x14
+#define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK                                                           0x0000000FL
+#define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK                                                           0x000000F0L
+#define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK                                                           0x00000F00L
+#define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK                                                           0x0000F000L
+#define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK                                                           0x000F0000L
+#define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK                                                           0x00F00000L
+//DAGB0_SDP_WR_PRIORITY
+#define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY__SHIFT                                                         0x0
+#define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY__SHIFT                                                         0x4
+#define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY__SHIFT                                                         0x8
+#define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY__SHIFT                                                         0xc
+#define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY__SHIFT                                                         0x10
+#define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY__SHIFT                                                         0x14
+#define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY_MASK                                                           0x0000000FL
+#define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY_MASK                                                           0x000000F0L
+#define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY_MASK                                                           0x00000F00L
+#define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY_MASK                                                           0x0000F000L
+#define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY_MASK                                                           0x000F0000L
+#define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY_MASK                                                           0x00F00000L
+//DAGB0_SDP_RD_CLI2SDP_VC_MAP
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT                                                        0x0
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT                                                        0x3
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT                                                      0x6
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT                                                        0x9
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT                                                         0xc
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT                                                        0xf
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK                                                          0x00000007L
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK                                                          0x00000038L
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK                                                        0x000001C0L
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK                                                          0x00000E00L
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK                                                           0x00007000L
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK                                                          0x00038000L
+//DAGB0_SDP_WR_CLI2SDP_VC_MAP
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT                                                        0x0
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT                                                        0x3
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT                                                      0x6
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT                                                        0x9
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT                                                         0xc
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT                                                        0xf
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK                                                          0x00000007L
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK                                                          0x00000038L
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK                                                        0x000001C0L
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK                                                          0x00000E00L
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP_MASK                                                           0x00007000L
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK                                                          0x00038000L
+//DAGB0_SDP_ENABLE
+#define DAGB0_SDP_ENABLE__ENABLE__SHIFT                                                                       0x0
+#define DAGB0_SDP_ENABLE__ENABLE_MASK                                                                         0x00000001L
+//DAGB0_SDP_CREDITS
+#define DAGB0_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
+#define DAGB0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
+#define DAGB0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
+#define DAGB0_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
+#define DAGB0_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
+#define DAGB0_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x01FF0000L
+//DAGB0_SDP_TAG_RESERVE0
+#define DAGB0_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
+#define DAGB0_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
+#define DAGB0_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
+#define DAGB0_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
+#define DAGB0_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
+#define DAGB0_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
+#define DAGB0_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
+#define DAGB0_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
+//DAGB0_SDP_TAG_RESERVE1
+#define DAGB0_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
+#define DAGB0_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
+#define DAGB0_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
+#define DAGB0_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
+#define DAGB0_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
+#define DAGB0_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
+#define DAGB0_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
+#define DAGB0_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
+//DAGB0_SDP_VCC_RESERVE0
+#define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
+#define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
+#define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
+#define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
+#define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
+#define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
+#define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
+#define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
+#define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
+#define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
+//DAGB0_SDP_VCC_RESERVE1
+#define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
+#define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
+#define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
+#define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
+#define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
+#define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
+#define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
+#define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
+//DAGB0_SDP_ERR_STATUS
+#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                         0x0
+#define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                         0x4
+#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                     0x8
+#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                               0xa
+#define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                       0xb
+#define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                            0xc
+#define DAGB0_SDP_ERR_STATUS__FUE_FLAG__SHIFT                                                                 0xd
+#define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT                                                         0xe
+#define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT                                                       0xf
+#define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT                                               0x10
+#define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT                                                          0x11
+#define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT                                                 0x12
+#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                           0x0000000FL
+#define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                           0x000000F0L
+#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                       0x00000300L
+#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                 0x00000400L
+#define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                         0x00000800L
+#define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK                                                              0x00001000L
+#define DAGB0_SDP_ERR_STATUS__FUE_FLAG_MASK                                                                   0x00002000L
+#define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK                                                           0x00004000L
+#define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK                                                         0x00008000L
+#define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK                                                 0x00010000L
+#define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK                                                            0x00020000L
+#define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK                                                   0x00040000L
+//DAGB0_SDP_REQ_CNTL
+#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
+#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
+#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
+#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
+#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
+#define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
+#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT                                                       0x6
+#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT                                                      0x8
+#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT                                                     0xa
+#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
+#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
+#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
+#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
+#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
+#define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
+#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK                                                         0x000000C0L
+#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK                                                        0x00000300L
+#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK                                                       0x00000C00L
+//DAGB0_SDP_MISC_AON
+#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT                                                 0x0
+#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT                                              0x2
+#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK                                                   0x00000003L
+#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK                                                0x00000004L
+//DAGB0_SDP_MISC
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                          0x0
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                          0x1
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                          0x2
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                          0x3
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                          0x4
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                          0x5
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                          0x6
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                          0x7
+#define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                             0x8
+#define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                           0x9
+#define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                         0xb
+#define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                        0xd
+#define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                         0xf
+#define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT                                                           0x14
+#define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT                                                           0x15
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                            0x00000001L
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                            0x00000002L
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                            0x00000004L
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                            0x00000008L
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                            0x00000010L
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                            0x00000020L
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                            0x00000040L
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                            0x00000080L
+#define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA_MASK                                                               0x00000100L
+#define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                             0x00000600L
+#define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                           0x00001800L
+#define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                          0x00006000L
+#define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                           0x000F8000L
+#define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK                                                             0x00100000L
+#define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK                                                             0x00200000L
+//DAGB0_SDP_MISC2
+#define DAGB0_SDP_MISC2__RRET_SWAP_MODE__SHIFT                                                                0x0
+#define DAGB0_SDP_MISC2__BLOCK_REQUESTS__SHIFT                                                                0x1
+#define DAGB0_SDP_MISC2__REQUESTS_BLOCKED__SHIFT                                                              0x2
+#define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT                                                         0x3
+#define DAGB0_SDP_MISC2__RRET_SWAP_MODE_MASK                                                                  0x00000001L
+#define DAGB0_SDP_MISC2__BLOCK_REQUESTS_MASK                                                                  0x00000002L
+#define DAGB0_SDP_MISC2__REQUESTS_BLOCKED_MASK                                                                0x00000004L
+#define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK                                                           0x00000008L
+//DAGB0_SDP_VCD_RESERVE0
+#define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
+#define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
+#define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
+#define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
+#define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
+#define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
+#define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
+#define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
+#define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
+#define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
+//DAGB0_SDP_VCD_RESERVE1
+#define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
+#define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
+#define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
+#define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x12
+#define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
+#define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
+#define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
+#define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x00040000L
+//DAGB0_SDP_ARB_CNTL0
+#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT                                                        0x0
+#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT                                                        0x1
+#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT                                                        0x2
+#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT                                                        0x3
+#define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT                                                        0x4
+#define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT                                                         0x5
+#define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT                                                          0x6
+#define DAGB0_SDP_ARB_CNTL0__DED_MODE__SHIFT                                                                  0x7
+#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK                                                          0x00000001L
+#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK                                                          0x00000002L
+#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK                                                          0x00000004L
+#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK                                                          0x00000008L
+#define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK                                                          0x00000010L
+#define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK                                                           0x00000020L
+#define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK                                                            0x00000040L
+#define DAGB0_SDP_ARB_CNTL0__DED_MODE_MASK                                                                    0x00000080L
+//DAGB0_SDP_ARB_CNTL1
+#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT                                                       0x0
+#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT                                                       0x8
+#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT                                                       0x10
+#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT                                                       0x18
+#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
+#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK                                                         0x00007F00L
+#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK                                                         0x007F0000L
+#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK                                                         0x7F000000L
+//DAGB0_SDP_CGTT_CLK_CTRL
+#define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                              0x0
+#define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                        0x5
+#define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT                                                  0xd
+#define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT                                                            0x1e
+#define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT                                                         0x1f
+#define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                0x0000001FL
+#define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                          0x00001FE0L
+#define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK                                                    0x1FFFE000L
+#define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK                                                              0x40000000L
+#define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK                                                           0x80000000L
+//DAGB0_SDP_LATENCY_SAMPLING
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                      0x0
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                      0x1
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                       0x2
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                       0x3
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                        0x4
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                        0x5
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                      0x6
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                      0x7
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                     0x8
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                     0x9
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                0xa
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                0xb
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                              0xc
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                              0xd
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                        0xe
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                        0x16
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                        0x00000001L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                        0x00000002L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                         0x00000004L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                         0x00000008L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                          0x00000010L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                          0x00000020L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                        0x00000040L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                        0x00000080L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                       0x00000100L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                       0x00000200L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                  0x00000400L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                  0x00000800L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                0x00001000L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                0x00002000L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                          0x003FC000L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                          0x3FC00000L
+
+
+// addressBlock: mmhub_pctldec
+//PCTL_CTRL
+#define PCTL_CTRL__PG_ENABLE__SHIFT                                                                           0x0
+#define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT                                                               0x1
+#define PCTL_CTRL__RSMU_RDTIMER_ENABLE__SHIFT                                                                 0x4
+#define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD__SHIFT                                                              0x5
+#define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT                                                          0x7
+#define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT                                                          0xe
+#define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT                                                      0x13
+#define PCTL_CTRL__UTCL2_LEGACY_MODE__SHIFT                                                                   0x14
+#define PCTL_CTRL__SDP_DISCONNECT_MODE__SHIFT                                                                 0x15
+#define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD__SHIFT                                                           0x16
+#define PCTL_CTRL__ZSC_TIMER_ENABLE__SHIFT                                                                    0x1b
+#define PCTL_CTRL__Z9_PWRDOWN__SHIFT                                                                          0x1c
+#define PCTL_CTRL__Z9_PWRUP__SHIFT                                                                            0x1d
+#define PCTL_CTRL__SNR_DISABLE__SHIFT                                                                         0x1e
+#define PCTL_CTRL__WRACK_GUARD__SHIFT                                                                         0x1f
+#define PCTL_CTRL__PG_ENABLE_MASK                                                                             0x00000001L
+#define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK                                                                 0x0000000EL
+#define PCTL_CTRL__RSMU_RDTIMER_ENABLE_MASK                                                                   0x00000010L
+#define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD_MASK                                                                0x00000060L
+#define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK                                                            0x00003F80L
+#define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK                                                            0x0007C000L
+#define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK                                                        0x00080000L
+#define PCTL_CTRL__UTCL2_LEGACY_MODE_MASK                                                                     0x00100000L
+#define PCTL_CTRL__SDP_DISCONNECT_MODE_MASK                                                                   0x00200000L
+#define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD_MASK                                                             0x07C00000L
+#define PCTL_CTRL__ZSC_TIMER_ENABLE_MASK                                                                      0x08000000L
+#define PCTL_CTRL__Z9_PWRDOWN_MASK                                                                            0x10000000L
+#define PCTL_CTRL__Z9_PWRUP_MASK                                                                              0x20000000L
+#define PCTL_CTRL__SNR_DISABLE_MASK                                                                           0x40000000L
+#define PCTL_CTRL__WRACK_GUARD_MASK                                                                           0x80000000L
+//PCTL_MMHUB_DEEPSLEEP_IB
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS0__SHIFT                                                                   0x0
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS1__SHIFT                                                                   0x1
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS2__SHIFT                                                                   0x2
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS3__SHIFT                                                                   0x3
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS4__SHIFT                                                                   0x4
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS5__SHIFT                                                                   0x5
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS6__SHIFT                                                                   0x6
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS7__SHIFT                                                                   0x7
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS8__SHIFT                                                                   0x8
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS9__SHIFT                                                                   0x9
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS10__SHIFT                                                                  0xa
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS11__SHIFT                                                                  0xb
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS12__SHIFT                                                                  0xc
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS13__SHIFT                                                                  0xd
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS14__SHIFT                                                                  0xe
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS15__SHIFT                                                                  0xf
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS16__SHIFT                                                                  0x10
+#define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT                                                              0x1f
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS0_MASK                                                                     0x00000001L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS1_MASK                                                                     0x00000002L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS2_MASK                                                                     0x00000004L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS3_MASK                                                                     0x00000008L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS4_MASK                                                                     0x00000010L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS5_MASK                                                                     0x00000020L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS6_MASK                                                                     0x00000040L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS7_MASK                                                                     0x00000080L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS8_MASK                                                                     0x00000100L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS9_MASK                                                                     0x00000200L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS10_MASK                                                                    0x00000400L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS11_MASK                                                                    0x00000800L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS12_MASK                                                                    0x00001000L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS13_MASK                                                                    0x00002000L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS14_MASK                                                                    0x00004000L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS15_MASK                                                                    0x00008000L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS16_MASK                                                                    0x00010000L
+#define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK                                                                0x80000000L
+//PCTL_MMHUB_DEEPSLEEP_OVERRIDE
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT                                                             0x0
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT                                                             0x1
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT                                                             0x2
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT                                                             0x3
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT                                                             0x4
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT                                                             0x5
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT                                                             0x6
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT                                                             0x7
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT                                                             0x8
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT                                                             0x9
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT                                                            0xa
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT                                                            0xb
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT                                                            0xc
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT                                                            0xd
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT                                                            0xe
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT                                                            0xf
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT                                                            0x10
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT                                                        0x11
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK                                                               0x00000001L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK                                                               0x00000002L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK                                                               0x00000004L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK                                                               0x00000008L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK                                                               0x00000010L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK                                                               0x00000020L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK                                                               0x00000040L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK                                                               0x00000080L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK                                                               0x00000100L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK                                                               0x00000200L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK                                                              0x00000400L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK                                                              0x00000800L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK                                                              0x00001000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK                                                              0x00002000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK                                                              0x00004000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK                                                              0x00008000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK                                                              0x00010000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK                                                          0x00020000L
+//PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT                                                          0x0
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT                                                          0x1
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT                                                          0x2
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT                                                          0x3
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT                                                          0x4
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT                                                          0x5
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT                                                          0x6
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT                                                          0x7
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT                                                          0x8
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT                                                          0x9
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT                                                         0xa
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT                                                         0xb
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT                                                         0xc
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT                                                         0xd
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT                                                         0xe
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT                                                         0xf
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT                                                         0x10
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK                                                            0x00000001L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK                                                            0x00000002L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK                                                            0x00000004L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK                                                            0x00000008L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK                                                            0x00000010L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK                                                            0x00000020L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK                                                            0x00000040L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK                                                            0x00000080L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK                                                            0x00000100L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK                                                            0x00000200L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK                                                           0x00000400L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK                                                           0x00000800L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK                                                           0x00001000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK                                                           0x00002000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK                                                           0x00004000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK                                                           0x00008000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK                                                           0x00010000L
+//PCTL_PG_IGNORE_DEEPSLEEP
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT                                                                  0x0
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT                                                                  0x1
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT                                                                  0x2
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT                                                                  0x3
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT                                                                  0x4
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT                                                                  0x5
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT                                                                  0x6
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT                                                                  0x7
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT                                                                  0x8
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT                                                                  0x9
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT                                                                 0xa
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT                                                                 0xb
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT                                                                 0xc
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT                                                                 0xd
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT                                                                 0xe
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT                                                                 0xf
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT                                                                 0x10
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT                                                             0x11
+#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT                                                               0x12
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK                                                                    0x00000001L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK                                                                    0x00000002L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK                                                                    0x00000004L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK                                                                    0x00000008L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK                                                                    0x00000010L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK                                                                    0x00000020L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK                                                                    0x00000040L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK                                                                    0x00000080L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK                                                                    0x00000100L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK                                                                    0x00000200L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK                                                                   0x00000400L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK                                                                   0x00000800L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK                                                                   0x00001000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK                                                                   0x00002000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK                                                                   0x00004000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK                                                                   0x00008000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK                                                                   0x00010000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK                                                               0x00020000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK                                                                 0x00040000L
+//PCTL_PG_IGNORE_DEEPSLEEP_IB
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT                                                               0x0
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT                                                               0x1
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT                                                               0x2
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT                                                               0x3
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT                                                               0x4
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT                                                               0x5
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT                                                               0x6
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT                                                               0x7
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT                                                               0x8
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT                                                               0x9
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT                                                              0xa
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT                                                              0xb
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT                                                              0xc
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT                                                              0xd
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT                                                              0xe
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT                                                              0xf
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT                                                              0x10
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT                                                            0x11
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK                                                                 0x00000001L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK                                                                 0x00000002L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK                                                                 0x00000004L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK                                                                 0x00000008L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK                                                                 0x00000010L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK                                                                 0x00000020L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK                                                                 0x00000040L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK                                                                 0x00000080L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK                                                                 0x00000100L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK                                                                 0x00000200L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK                                                                0x00000400L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK                                                                0x00000800L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK                                                                0x00001000L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK                                                                0x00002000L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK                                                                0x00004000L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK                                                                0x00008000L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK                                                                0x00010000L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK                                                              0x00020000L
+//PCTL_SLICE0_CFG_DAGB_WRBUSY
+#define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT                                                          0x0
+#define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG_MASK                                                            0xFFFFFFFFL
+//PCTL_SLICE0_CFG_DAGB_RDBUSY
+#define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT                                                          0x0
+#define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG_MASK                                                            0xFFFFFFFFL
+//PCTL_SLICE0_CFG_DS_ALLOW
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS0__SHIFT                                                                  0x0
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS1__SHIFT                                                                  0x1
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS2__SHIFT                                                                  0x2
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS3__SHIFT                                                                  0x3
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS4__SHIFT                                                                  0x4
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS5__SHIFT                                                                  0x5
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS6__SHIFT                                                                  0x6
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS7__SHIFT                                                                  0x7
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS8__SHIFT                                                                  0x8
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS9__SHIFT                                                                  0x9
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS10__SHIFT                                                                 0xa
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS11__SHIFT                                                                 0xb
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS12__SHIFT                                                                 0xc
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS13__SHIFT                                                                 0xd
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS14__SHIFT                                                                 0xe
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS15__SHIFT                                                                 0xf
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS16__SHIFT                                                                 0x10
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS0_MASK                                                                    0x00000001L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS1_MASK                                                                    0x00000002L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS2_MASK                                                                    0x00000004L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS3_MASK                                                                    0x00000008L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS4_MASK                                                                    0x00000010L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS5_MASK                                                                    0x00000020L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS6_MASK                                                                    0x00000040L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS7_MASK                                                                    0x00000080L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS8_MASK                                                                    0x00000100L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS9_MASK                                                                    0x00000200L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS10_MASK                                                                   0x00000400L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS11_MASK                                                                   0x00000800L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS12_MASK                                                                   0x00001000L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS13_MASK                                                                   0x00002000L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS14_MASK                                                                   0x00004000L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS15_MASK                                                                   0x00008000L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS16_MASK                                                                   0x00010000L
+//PCTL_SLICE0_CFG_DS_ALLOW_IB
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT                                                               0x0
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT                                                               0x1
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT                                                               0x2
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT                                                               0x3
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT                                                               0x4
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT                                                               0x5
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT                                                               0x6
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT                                                               0x7
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT                                                               0x8
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT                                                               0x9
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT                                                              0xa
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT                                                              0xb
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT                                                              0xc
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT                                                              0xd
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT                                                              0xe
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT                                                              0xf
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT                                                              0x10
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK                                                                 0x00000001L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK                                                                 0x00000002L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK                                                                 0x00000004L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK                                                                 0x00000008L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK                                                                 0x00000010L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK                                                                 0x00000020L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK                                                                 0x00000040L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK                                                                 0x00000080L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK                                                                 0x00000100L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK                                                                 0x00000200L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK                                                                0x00000400L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK                                                                0x00000800L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK                                                                0x00001000L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK                                                                0x00002000L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK                                                                0x00004000L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK                                                                0x00008000L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK                                                                0x00010000L
+//PCTL_SLICE1_CFG_DAGB_WRBUSY
+#define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT                                                          0x0
+#define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG_MASK                                                            0xFFFFFFFFL
+//PCTL_SLICE1_CFG_DAGB_RDBUSY
+#define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT                                                          0x0
+#define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG_MASK                                                            0xFFFFFFFFL
+//PCTL_SLICE1_CFG_DS_ALLOW
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS0__SHIFT                                                                  0x0
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS1__SHIFT                                                                  0x1
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS2__SHIFT                                                                  0x2
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS3__SHIFT                                                                  0x3
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS4__SHIFT                                                                  0x4
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS5__SHIFT                                                                  0x5
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS6__SHIFT                                                                  0x6
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS7__SHIFT                                                                  0x7
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS8__SHIFT                                                                  0x8
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS9__SHIFT                                                                  0x9
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS10__SHIFT                                                                 0xa
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS11__SHIFT                                                                 0xb
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS12__SHIFT                                                                 0xc
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS13__SHIFT                                                                 0xd
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS14__SHIFT                                                                 0xe
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS15__SHIFT                                                                 0xf
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS16__SHIFT                                                                 0x10
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS0_MASK                                                                    0x00000001L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS1_MASK                                                                    0x00000002L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS2_MASK                                                                    0x00000004L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS3_MASK                                                                    0x00000008L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS4_MASK                                                                    0x00000010L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS5_MASK                                                                    0x00000020L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS6_MASK                                                                    0x00000040L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS7_MASK                                                                    0x00000080L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS8_MASK                                                                    0x00000100L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS9_MASK                                                                    0x00000200L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS10_MASK                                                                   0x00000400L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS11_MASK                                                                   0x00000800L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS12_MASK                                                                   0x00001000L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS13_MASK                                                                   0x00002000L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS14_MASK                                                                   0x00004000L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS15_MASK                                                                   0x00008000L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS16_MASK                                                                   0x00010000L
+//PCTL_SLICE1_CFG_DS_ALLOW_IB
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT                                                               0x0
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT                                                               0x1
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT                                                               0x2
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT                                                               0x3
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT                                                               0x4
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT                                                               0x5
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT                                                               0x6
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT                                                               0x7
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT                                                               0x8
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT                                                               0x9
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT                                                              0xa
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT                                                              0xb
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT                                                              0xc
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT                                                              0xd
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT                                                              0xe
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT                                                              0xf
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT                                                              0x10
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK                                                                 0x00000001L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK                                                                 0x00000002L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK                                                                 0x00000004L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK                                                                 0x00000008L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK                                                                 0x00000010L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK                                                                 0x00000020L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK                                                                 0x00000040L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK                                                                 0x00000080L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK                                                                 0x00000100L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK                                                                 0x00000200L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK                                                                0x00000400L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK                                                                0x00000800L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK                                                                0x00001000L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK                                                                0x00002000L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK                                                                0x00004000L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK                                                                0x00008000L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK                                                                0x00010000L
+//PCTL_UTCL2_MISC
+#define PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT                                              0x0
+#define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT                                                            0xb
+#define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                           0xc
+#define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                            0xf
+#define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                   0x10
+#define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                    0x11
+#define PCTL_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT                                                               0x12
+#define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE__SHIFT                                                            0x13
+#define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER__SHIFT                                                             0x14
+#define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER__SHIFT                                                          0x1a
+#define PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK                                                0x000007FFL
+#define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK                                                              0x00000800L
+#define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK                                                             0x00007000L
+#define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK                                                              0x00008000L
+#define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                     0x00010000L
+#define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                      0x00020000L
+#define PCTL_UTCL2_MISC__RD_TIMER_ENABLE_MASK                                                                 0x00040000L
+#define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE_MASK                                                              0x00080000L
+#define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER_MASK                                                               0x03F00000L
+#define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER_MASK                                                            0x3C000000L
+//PCTL_SLICE0_MISC
+#define PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT                                             0x0
+#define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT                                                           0xa
+#define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                          0xb
+#define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                           0xe
+#define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                  0xf
+#define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                            0x10
+#define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                   0x11
+#define PCTL_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT                                                              0x12
+#define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE__SHIFT                                                           0x13
+#define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER__SHIFT                                                            0x14
+#define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER__SHIFT                                                         0x1a
+#define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK__SHIFT                                                          0x1e
+#define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK__SHIFT                                                          0x1f
+#define PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK                                               0x000003FFL
+#define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK                                                             0x00000400L
+#define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK                                                            0x00003800L
+#define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK                                                             0x00004000L
+#define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                    0x00008000L
+#define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK                                                              0x00010000L
+#define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                     0x00020000L
+#define PCTL_SLICE0_MISC__RD_TIMER_ENABLE_MASK                                                                0x00040000L
+#define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE_MASK                                                             0x00080000L
+#define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER_MASK                                                              0x03F00000L
+#define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER_MASK                                                           0x3C000000L
+#define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK_MASK                                                            0x40000000L
+#define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK_MASK                                                            0x80000000L
+//PCTL_SLICE1_MISC
+#define PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT                                             0x0
+#define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT                                                           0xa
+#define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                          0xb
+#define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                           0xe
+#define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                  0xf
+#define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                            0x10
+#define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                   0x11
+#define PCTL_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT                                                              0x12
+#define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE__SHIFT                                                           0x13
+#define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER__SHIFT                                                            0x14
+#define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER__SHIFT                                                         0x1a
+#define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK__SHIFT                                                          0x1e
+#define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK__SHIFT                                                          0x1f
+#define PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK                                               0x000003FFL
+#define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK                                                             0x00000400L
+#define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK                                                            0x00003800L
+#define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK                                                             0x00004000L
+#define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                    0x00008000L
+#define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK                                                              0x00010000L
+#define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                     0x00020000L
+#define PCTL_SLICE1_MISC__RD_TIMER_ENABLE_MASK                                                                0x00040000L
+#define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE_MASK                                                             0x00080000L
+#define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER_MASK                                                              0x03F00000L
+#define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER_MASK                                                           0x3C000000L
+#define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK_MASK                                                            0x40000000L
+#define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK_MASK                                                            0x80000000L
+//PCTL_RENG_CTRL
+#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW__SHIFT                                                               0x0
+#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE__SHIFT                                                          0x1
+#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MASK                                                                 0x00000001L
+#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE_MASK                                                            0x00000002L
+//PCTL_UTCL2_RENG_EXECUTE
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                      0x0
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                                 0x1
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                            0x2
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                  0xd
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                        0x00000001L
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                   0x00000002L
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                              0x00001FFCL
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                    0x00FFE000L
+//PCTL_SLICE0_RENG_EXECUTE
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                     0x0
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                                0x1
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                           0x2
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                 0xc
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                       0x00000001L
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                  0x00000002L
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                             0x00000FFCL
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                   0x003FF000L
+//PCTL_SLICE1_RENG_EXECUTE
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                     0x0
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                                0x1
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                           0x2
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                 0xc
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                       0x00000001L
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                  0x00000002L
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                             0x00000FFCL
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                   0x003FF000L
+//PCTL_UTCL2_RENG_RAM_INDEX
+#define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                      0x0
+#define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                        0x000007FFL
+//PCTL_UTCL2_RENG_RAM_DATA
+#define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                        0x0
+#define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                          0xFFFFFFFFL
+//PCTL_SLICE0_RENG_RAM_INDEX
+#define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                     0x0
+#define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                       0x000003FFL
+//PCTL_SLICE0_RENG_RAM_DATA
+#define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                       0x0
+#define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                         0xFFFFFFFFL
+//PCTL_SLICE1_RENG_RAM_INDEX
+#define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                     0x0
+#define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                       0x000003FFL
+//PCTL_SLICE1_RENG_RAM_DATA
+#define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                       0x0
+#define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                         0xFFFFFFFFL
+//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                              0x0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                             0x10
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                                0x0000FFFFL
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                               0xFFFF0000L
+//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                              0x0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                             0x10
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                                0x0000FFFFL
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                               0xFFFF0000L
+//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                              0x0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                             0x10
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                                0x0000FFFFL
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                               0xFFFF0000L
+//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                              0x0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                             0x10
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                                0x0000FFFFL
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                               0xFFFF0000L
+//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                              0x0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                             0x10
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                                0x0000FFFFL
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                               0xFFFF0000L
+//PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                          0x0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                          0x10
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                            0x0000FFFFL
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                            0xFFFF0000L
+//PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT                          0x0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT                          0x10
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK                            0x0000FFFFL
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK                            0xFFFF0000L
+//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
+//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
+//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
+//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
+//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
+//PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                         0x0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                         0x10
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                           0x0000FFFFL
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                           0xFFFF0000L
+//PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT                         0x0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT                         0x10
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK                           0x0000FFFFL
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK                           0xFFFF0000L
+//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
+//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
+//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
+//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
+//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
+//PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                         0x0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                         0x10
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                           0x0000FFFFL
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                           0xFFFF0000L
+//PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT                         0x0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT                         0x10
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK                           0x0000FFFFL
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK                           0xFFFF0000L
+//PCTL_STATUS
+#define PCTL_STATUS__MMHUB_CONFIG_DONE__SHIFT                                                                 0x0
+#define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE__SHIFT                                                            0x1
+#define PCTL_STATUS__MMHUB_FENCE_REQ__SHIFT                                                                   0x2
+#define PCTL_STATUS__MMHUB_FENCE_ACK__SHIFT                                                                   0x3
+#define PCTL_STATUS__MMHUB_IDLE__SHIFT                                                                        0x4
+#define PCTL_STATUS__PGFSM_CMD_STATUS__SHIFT                                                                  0x5
+#define PCTL_STATUS__RSMU_RDTIMEOUT_CNT__SHIFT                                                                0x7
+#define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR__SHIFT                                                              0xf
+#define PCTL_STATUS__MMHUB_POWER__SHIFT                                                                       0x10
+#define PCTL_STATUS__RENG_RAM_STALE__SHIFT                                                                    0x11
+#define PCTL_STATUS__UTCL2_RENG_RAM_STALE__SHIFT                                                              0x12
+#define PCTL_STATUS__SLICE0_RENG_RAM_STALE__SHIFT                                                             0x13
+#define PCTL_STATUS__SLICE1_RENG_RAM_STALE__SHIFT                                                             0x14
+#define PCTL_STATUS__MMHUB_CONFIG_DONE_MASK                                                                   0x00000001L
+#define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE_MASK                                                              0x00000002L
+#define PCTL_STATUS__MMHUB_FENCE_REQ_MASK                                                                     0x00000004L
+#define PCTL_STATUS__MMHUB_FENCE_ACK_MASK                                                                     0x00000008L
+#define PCTL_STATUS__MMHUB_IDLE_MASK                                                                          0x00000010L
+#define PCTL_STATUS__PGFSM_CMD_STATUS_MASK                                                                    0x00000060L
+#define PCTL_STATUS__RSMU_RDTIMEOUT_CNT_MASK                                                                  0x00007F80L
+#define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR_MASK                                                                0x00008000L
+#define PCTL_STATUS__MMHUB_POWER_MASK                                                                         0x00010000L
+#define PCTL_STATUS__RENG_RAM_STALE_MASK                                                                      0x00020000L
+#define PCTL_STATUS__UTCL2_RENG_RAM_STALE_MASK                                                                0x00040000L
+#define PCTL_STATUS__SLICE0_RENG_RAM_STALE_MASK                                                               0x00080000L
+#define PCTL_STATUS__SLICE1_RENG_RAM_STALE_MASK                                                               0x00100000L
+//PCTL_PERFCOUNTER_LO
+#define PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                                0x0
+#define PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                  0xFFFFFFFFL
+//PCTL_PERFCOUNTER_HI
+#define PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                                0x0
+#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                             0x10
+#define PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                  0x0000FFFFL
+#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                               0xFFFF0000L
+//PCTL_PERFCOUNTER0_CFG
+#define PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                                0x0
+#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                            0x8
+#define PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                               0x18
+#define PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                  0x1c
+#define PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                   0x1d
+#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                  0x000000FFL
+#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                              0x0000FF00L
+#define PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                 0x0F000000L
+#define PCTL_PERFCOUNTER0_CFG__ENABLE_MASK                                                                    0x10000000L
+#define PCTL_PERFCOUNTER0_CFG__CLEAR_MASK                                                                     0x20000000L
+//PCTL_PERFCOUNTER1_CFG
+#define PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                                0x0
+#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                            0x8
+#define PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                               0x18
+#define PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                  0x1c
+#define PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                   0x1d
+#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                  0x000000FFL
+#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                              0x0000FF00L
+#define PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                 0x0F000000L
+#define PCTL_PERFCOUNTER1_CFG__ENABLE_MASK                                                                    0x10000000L
+#define PCTL_PERFCOUNTER1_CFG__CLEAR_MASK                                                                     0x20000000L
+//PCTL_PERFCOUNTER_RSLT_CNTL
+#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                                0x0
+#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                      0x8
+#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                       0x10
+#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                         0x18
+#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                          0x19
+#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                               0x1a
+#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                  0x0000000FL
+#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                        0x0000FF00L
+#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                         0x00FF0000L
+#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                           0x01000000L
+#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                            0x02000000L
+#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                 0x04000000L
+//PCTL_RESERVED_0
+#define PCTL_RESERVED_0__WORD__SHIFT                                                                          0x0
+#define PCTL_RESERVED_0__BYTE__SHIFT                                                                          0x10
+#define PCTL_RESERVED_0__BIT7__SHIFT                                                                          0x18
+#define PCTL_RESERVED_0__BIT6__SHIFT                                                                          0x19
+#define PCTL_RESERVED_0__BIT5__SHIFT                                                                          0x1a
+#define PCTL_RESERVED_0__BIT4__SHIFT                                                                          0x1b
+#define PCTL_RESERVED_0__BIT3__SHIFT                                                                          0x1c
+#define PCTL_RESERVED_0__BIT2__SHIFT                                                                          0x1d
+#define PCTL_RESERVED_0__BIT1__SHIFT                                                                          0x1e
+#define PCTL_RESERVED_0__BIT0__SHIFT                                                                          0x1f
+#define PCTL_RESERVED_0__WORD_MASK                                                                            0x0000FFFFL
+#define PCTL_RESERVED_0__BYTE_MASK                                                                            0x00FF0000L
+#define PCTL_RESERVED_0__BIT7_MASK                                                                            0x01000000L
+#define PCTL_RESERVED_0__BIT6_MASK                                                                            0x02000000L
+#define PCTL_RESERVED_0__BIT5_MASK                                                                            0x04000000L
+#define PCTL_RESERVED_0__BIT4_MASK                                                                            0x08000000L
+#define PCTL_RESERVED_0__BIT3_MASK                                                                            0x10000000L
+#define PCTL_RESERVED_0__BIT2_MASK                                                                            0x20000000L
+#define PCTL_RESERVED_0__BIT1_MASK                                                                            0x40000000L
+#define PCTL_RESERVED_0__BIT0_MASK                                                                            0x80000000L
+//PCTL_RESERVED_1
+#define PCTL_RESERVED_1__WORD__SHIFT                                                                          0x0
+#define PCTL_RESERVED_1__BYTE__SHIFT                                                                          0x10
+#define PCTL_RESERVED_1__BIT7__SHIFT                                                                          0x18
+#define PCTL_RESERVED_1__BIT6__SHIFT                                                                          0x19
+#define PCTL_RESERVED_1__BIT5__SHIFT                                                                          0x1a
+#define PCTL_RESERVED_1__BIT4__SHIFT                                                                          0x1b
+#define PCTL_RESERVED_1__BIT3__SHIFT                                                                          0x1c
+#define PCTL_RESERVED_1__BIT2__SHIFT                                                                          0x1d
+#define PCTL_RESERVED_1__BIT1__SHIFT                                                                          0x1e
+#define PCTL_RESERVED_1__BIT0__SHIFT                                                                          0x1f
+#define PCTL_RESERVED_1__WORD_MASK                                                                            0x0000FFFFL
+#define PCTL_RESERVED_1__BYTE_MASK                                                                            0x00FF0000L
+#define PCTL_RESERVED_1__BIT7_MASK                                                                            0x01000000L
+#define PCTL_RESERVED_1__BIT6_MASK                                                                            0x02000000L
+#define PCTL_RESERVED_1__BIT5_MASK                                                                            0x04000000L
+#define PCTL_RESERVED_1__BIT4_MASK                                                                            0x08000000L
+#define PCTL_RESERVED_1__BIT3_MASK                                                                            0x10000000L
+#define PCTL_RESERVED_1__BIT2_MASK                                                                            0x20000000L
+#define PCTL_RESERVED_1__BIT1_MASK                                                                            0x40000000L
+#define PCTL_RESERVED_1__BIT0_MASK                                                                            0x80000000L
+//PCTL_RESERVED_2
+#define PCTL_RESERVED_2__WORD__SHIFT                                                                          0x0
+#define PCTL_RESERVED_2__BYTE__SHIFT                                                                          0x10
+#define PCTL_RESERVED_2__BIT7__SHIFT                                                                          0x18
+#define PCTL_RESERVED_2__BIT6__SHIFT                                                                          0x19
+#define PCTL_RESERVED_2__BIT5__SHIFT                                                                          0x1a
+#define PCTL_RESERVED_2__BIT4__SHIFT                                                                          0x1b
+#define PCTL_RESERVED_2__BIT3__SHIFT                                                                          0x1c
+#define PCTL_RESERVED_2__BIT2__SHIFT                                                                          0x1d
+#define PCTL_RESERVED_2__BIT1__SHIFT                                                                          0x1e
+#define PCTL_RESERVED_2__BIT0__SHIFT                                                                          0x1f
+#define PCTL_RESERVED_2__WORD_MASK                                                                            0x0000FFFFL
+#define PCTL_RESERVED_2__BYTE_MASK                                                                            0x00FF0000L
+#define PCTL_RESERVED_2__BIT7_MASK                                                                            0x01000000L
+#define PCTL_RESERVED_2__BIT6_MASK                                                                            0x02000000L
+#define PCTL_RESERVED_2__BIT5_MASK                                                                            0x04000000L
+#define PCTL_RESERVED_2__BIT4_MASK                                                                            0x08000000L
+#define PCTL_RESERVED_2__BIT3_MASK                                                                            0x10000000L
+#define PCTL_RESERVED_2__BIT2_MASK                                                                            0x20000000L
+#define PCTL_RESERVED_2__BIT1_MASK                                                                            0x40000000L
+#define PCTL_RESERVED_2__BIT0_MASK                                                                            0x80000000L
+//PCTL_RESERVED_3
+#define PCTL_RESERVED_3__WORD__SHIFT                                                                          0x0
+#define PCTL_RESERVED_3__BYTE__SHIFT                                                                          0x10
+#define PCTL_RESERVED_3__BIT7__SHIFT                                                                          0x18
+#define PCTL_RESERVED_3__BIT6__SHIFT                                                                          0x19
+#define PCTL_RESERVED_3__BIT5__SHIFT                                                                          0x1a
+#define PCTL_RESERVED_3__BIT4__SHIFT                                                                          0x1b
+#define PCTL_RESERVED_3__BIT3__SHIFT                                                                          0x1c
+#define PCTL_RESERVED_3__BIT2__SHIFT                                                                          0x1d
+#define PCTL_RESERVED_3__BIT1__SHIFT                                                                          0x1e
+#define PCTL_RESERVED_3__BIT0__SHIFT                                                                          0x1f
+#define PCTL_RESERVED_3__WORD_MASK                                                                            0x0000FFFFL
+#define PCTL_RESERVED_3__BYTE_MASK                                                                            0x00FF0000L
+#define PCTL_RESERVED_3__BIT7_MASK                                                                            0x01000000L
+#define PCTL_RESERVED_3__BIT6_MASK                                                                            0x02000000L
+#define PCTL_RESERVED_3__BIT5_MASK                                                                            0x04000000L
+#define PCTL_RESERVED_3__BIT4_MASK                                                                            0x08000000L
+#define PCTL_RESERVED_3__BIT3_MASK                                                                            0x10000000L
+#define PCTL_RESERVED_3__BIT2_MASK                                                                            0x20000000L
+#define PCTL_RESERVED_3__BIT1_MASK                                                                            0x40000000L
+#define PCTL_RESERVED_3__BIT0_MASK                                                                            0x80000000L
+
+
+// addressBlock: mmhub_l1tlb_mmutcl1pfdec
+//MMMC_VM_MX_L1_TLB0_STATUS
+#define MMMC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT                                                                0x0
+#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
+#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT                                               0x2
+#define MMMC_VM_MX_L1_TLB0_STATUS__BUSY_MASK                                                                  0x00000001L
+#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
+#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK                                                 0x00000004L
+//MMMC_VM_MX_L1_TLB1_STATUS
+#define MMMC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT                                                                0x0
+#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
+#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS__SHIFT                                               0x2
+#define MMMC_VM_MX_L1_TLB1_STATUS__BUSY_MASK                                                                  0x00000001L
+#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
+#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS_MASK                                                 0x00000004L
+//MMMC_VM_MX_L1_TLB2_STATUS
+#define MMMC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT                                                                0x0
+#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
+#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS__SHIFT                                               0x2
+#define MMMC_VM_MX_L1_TLB2_STATUS__BUSY_MASK                                                                  0x00000001L
+#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
+#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS_MASK                                                 0x00000004L
+//MMMC_VM_MX_L1_TLB3_STATUS
+#define MMMC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT                                                                0x0
+#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
+#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS__SHIFT                                               0x2
+#define MMMC_VM_MX_L1_TLB3_STATUS__BUSY_MASK                                                                  0x00000001L
+#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
+#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS_MASK                                                 0x00000004L
+//MMMC_VM_MX_L1_TLB4_STATUS
+#define MMMC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT                                                                0x0
+#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
+#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS__SHIFT                                               0x2
+#define MMMC_VM_MX_L1_TLB4_STATUS__BUSY_MASK                                                                  0x00000001L
+#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
+#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS_MASK                                                 0x00000004L
+//MMMC_VM_MX_L1_TLB5_STATUS
+#define MMMC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT                                                                0x0
+#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
+#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS__SHIFT                                               0x2
+#define MMMC_VM_MX_L1_TLB5_STATUS__BUSY_MASK                                                                  0x00000001L
+#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
+#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS_MASK                                                 0x00000004L
+//MMMC_VM_MX_L1_TLB6_STATUS
+#define MMMC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT                                                                0x0
+#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
+#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_APERTURE_FAULTS__SHIFT                                               0x2
+#define MMMC_VM_MX_L1_TLB6_STATUS__BUSY_MASK                                                                  0x00000001L
+#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
+#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_APERTURE_FAULTS_MASK                                                 0x00000004L
+//MMMC_VM_MX_L1_TLB7_STATUS
+#define MMMC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT                                                                0x0
+#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
+#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_APERTURE_FAULTS__SHIFT                                               0x2
+#define MMMC_VM_MX_L1_TLB7_STATUS__BUSY_MASK                                                                  0x00000001L
+#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
+#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_APERTURE_FAULTS_MASK                                                 0x00000004L
+
+
+// addressBlock: mmhub_l1tlb_mmutcl1pldec
+//MMMC_VM_MX_L1_PERFCOUNTER0_CFG
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                   0x8
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                      0x18
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                         0x1c
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                          0x1d
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                         0x000000FFL
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                        0x0F000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK                                                           0x10000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK                                                            0x20000000L
+//MMMC_VM_MX_L1_PERFCOUNTER1_CFG
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                   0x8
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                      0x18
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                         0x1c
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                          0x1d
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                         0x000000FFL
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                        0x0F000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK                                                           0x10000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK                                                            0x20000000L
+//MMMC_VM_MX_L1_PERFCOUNTER2_CFG
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                   0x8
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                      0x18
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                         0x1c
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                          0x1d
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                         0x000000FFL
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                        0x0F000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK                                                           0x10000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK                                                            0x20000000L
+//MMMC_VM_MX_L1_PERFCOUNTER3_CFG
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                   0x8
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                      0x18
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                         0x1c
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                          0x1d
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                         0x000000FFL
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                        0x0F000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK                                                           0x10000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK                                                            0x20000000L
+//MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                       0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                             0x8
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                              0x10
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                0x18
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                 0x19
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                      0x1a
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                         0x0000000FL
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                               0x0000FF00L
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                0x00FF0000L
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                  0x01000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                   0x02000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                        0x04000000L
+
+
+// addressBlock: mmhub_l1tlb_mmutcl1prdec
+//MMMC_VM_MX_L1_PERFCOUNTER_LO
+#define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK                                                         0xFFFFFFFFL
+//MMMC_VM_MX_L1_PERFCOUNTER_HI
+#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                    0x10
+#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK                                                         0x0000FFFFL
+#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                      0xFFFF0000L
+
+
+// addressBlock: mmhub_l1tlb_mmvmtlspfdec
+//MMMC_VM_MX_L1_TLS0_CNTL
+#define MMMC_VM_MX_L1_TLS0_CNTL__PREFETCH_COUNT__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x4
+#define MMMC_VM_MX_L1_TLS0_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT                 0x5
+#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_SNOOP_SELECT__SHIFT                                                    0x6
+#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SYSTEM__SHIFT                                                  0x8
+#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SNOOP__SHIFT                                                   0x9
+#define MMMC_VM_MX_L1_TLS0_CNTL__DEBUG_ECO_BITS__SHIFT                                                        0x10
+#define MMMC_VM_MX_L1_TLS0_CNTL__PREFETCH_COUNT_MASK                                                          0x0000000FL
+#define MMMC_VM_MX_L1_TLS0_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00000010L
+#define MMMC_VM_MX_L1_TLS0_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK                   0x00000020L
+#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_SNOOP_SELECT_MASK                                                      0x000000C0L
+#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SYSTEM_MASK                                                    0x00000100L
+#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SNOOP_MASK                                                     0x00000200L
+#define MMMC_VM_MX_L1_TLS0_CNTL__DEBUG_ECO_BITS_MASK                                                          0xFFFF0000L
+//MMMC_VM_MX_L1_TLS0_CNTL0
+#define MMMC_VM_MX_L1_TLS0_CNTL0__REQ_STREAM_ID__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL0__EN__SHIFT                                                                   0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL0__PREFETCH_DONE__SHIFT                                                        0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL0__REQ_STREAM_ID_MASK                                                          0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL0__EN_MASK                                                                     0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL0__PREFETCH_DONE_MASK                                                          0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL1
+#define MMMC_VM_MX_L1_TLS0_CNTL1__REQ_STREAM_ID__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL1__EN__SHIFT                                                                   0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL1__PREFETCH_DONE__SHIFT                                                        0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL1__REQ_STREAM_ID_MASK                                                          0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL1__EN_MASK                                                                     0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL1__PREFETCH_DONE_MASK                                                          0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL2
+#define MMMC_VM_MX_L1_TLS0_CNTL2__REQ_STREAM_ID__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL2__EN__SHIFT                                                                   0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL2__PREFETCH_DONE__SHIFT                                                        0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL2__REQ_STREAM_ID_MASK                                                          0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL2__EN_MASK                                                                     0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL2__PREFETCH_DONE_MASK                                                          0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL3
+#define MMMC_VM_MX_L1_TLS0_CNTL3__REQ_STREAM_ID__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL3__EN__SHIFT                                                                   0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL3__PREFETCH_DONE__SHIFT                                                        0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL3__REQ_STREAM_ID_MASK                                                          0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL3__EN_MASK                                                                     0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL3__PREFETCH_DONE_MASK                                                          0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL4
+#define MMMC_VM_MX_L1_TLS0_CNTL4__REQ_STREAM_ID__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL4__EN__SHIFT                                                                   0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL4__PREFETCH_DONE__SHIFT                                                        0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL4__REQ_STREAM_ID_MASK                                                          0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL4__EN_MASK                                                                     0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL4__PREFETCH_DONE_MASK                                                          0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL5
+#define MMMC_VM_MX_L1_TLS0_CNTL5__REQ_STREAM_ID__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL5__EN__SHIFT                                                                   0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL5__PREFETCH_DONE__SHIFT                                                        0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL5__REQ_STREAM_ID_MASK                                                          0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL5__EN_MASK                                                                     0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL5__PREFETCH_DONE_MASK                                                          0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL6
+#define MMMC_VM_MX_L1_TLS0_CNTL6__REQ_STREAM_ID__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL6__EN__SHIFT                                                                   0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL6__PREFETCH_DONE__SHIFT                                                        0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL6__REQ_STREAM_ID_MASK                                                          0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL6__EN_MASK                                                                     0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL6__PREFETCH_DONE_MASK                                                          0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL7
+#define MMMC_VM_MX_L1_TLS0_CNTL7__REQ_STREAM_ID__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL7__EN__SHIFT                                                                   0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL7__PREFETCH_DONE__SHIFT                                                        0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL7__REQ_STREAM_ID_MASK                                                          0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL7__EN_MASK                                                                     0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL7__PREFETCH_DONE_MASK                                                          0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL8
+#define MMMC_VM_MX_L1_TLS0_CNTL8__REQ_STREAM_ID__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL8__EN__SHIFT                                                                   0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL8__PREFETCH_DONE__SHIFT                                                        0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL8__REQ_STREAM_ID_MASK                                                          0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL8__EN_MASK                                                                     0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL8__PREFETCH_DONE_MASK                                                          0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL9
+#define MMMC_VM_MX_L1_TLS0_CNTL9__REQ_STREAM_ID__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL9__EN__SHIFT                                                                   0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL9__PREFETCH_DONE__SHIFT                                                        0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL9__REQ_STREAM_ID_MASK                                                          0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL9__EN_MASK                                                                     0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL9__PREFETCH_DONE_MASK                                                          0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL10
+#define MMMC_VM_MX_L1_TLS0_CNTL10__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL10__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL10__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL10__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL10__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL10__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL11
+#define MMMC_VM_MX_L1_TLS0_CNTL11__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL11__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL11__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL11__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL11__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL11__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL12
+#define MMMC_VM_MX_L1_TLS0_CNTL12__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL12__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL12__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL12__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL12__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL12__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL13
+#define MMMC_VM_MX_L1_TLS0_CNTL13__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL13__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL13__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL13__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL13__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL13__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL14
+#define MMMC_VM_MX_L1_TLS0_CNTL14__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL14__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL14__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL14__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL14__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL14__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL15
+#define MMMC_VM_MX_L1_TLS0_CNTL15__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL15__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL15__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL15__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL15__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL15__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL16
+#define MMMC_VM_MX_L1_TLS0_CNTL16__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL16__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL16__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL16__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL16__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL16__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL17
+#define MMMC_VM_MX_L1_TLS0_CNTL17__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL17__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL17__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL17__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL17__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL17__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL18
+#define MMMC_VM_MX_L1_TLS0_CNTL18__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL18__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL18__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL18__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL18__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL18__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL19
+#define MMMC_VM_MX_L1_TLS0_CNTL19__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL19__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL19__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL19__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL19__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL19__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL20
+#define MMMC_VM_MX_L1_TLS0_CNTL20__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL20__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL20__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL20__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL20__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL20__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL21
+#define MMMC_VM_MX_L1_TLS0_CNTL21__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL21__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL21__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL21__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL21__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL21__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL22
+#define MMMC_VM_MX_L1_TLS0_CNTL22__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL22__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL22__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL22__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL22__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL22__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL23
+#define MMMC_VM_MX_L1_TLS0_CNTL23__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL23__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL23__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL23__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL23__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL23__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL24
+#define MMMC_VM_MX_L1_TLS0_CNTL24__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL24__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL24__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL24__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL24__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL24__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL25
+#define MMMC_VM_MX_L1_TLS0_CNTL25__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL25__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL25__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL25__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL25__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL25__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL26
+#define MMMC_VM_MX_L1_TLS0_CNTL26__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL26__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL26__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL26__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL26__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL26__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL27
+#define MMMC_VM_MX_L1_TLS0_CNTL27__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL27__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL27__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL27__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL27__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL27__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL28
+#define MMMC_VM_MX_L1_TLS0_CNTL28__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL28__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL28__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL28__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL28__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL28__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL29
+#define MMMC_VM_MX_L1_TLS0_CNTL29__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL29__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL29__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL29__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL29__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL29__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL30
+#define MMMC_VM_MX_L1_TLS0_CNTL30__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL30__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL30__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL30__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL30__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL30__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL31
+#define MMMC_VM_MX_L1_TLS0_CNTL31__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL31__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL31__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL31__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL31__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL31__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL32
+#define MMMC_VM_MX_L1_TLS0_CNTL32__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL32__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL32__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL32__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL32__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL32__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL33
+#define MMMC_VM_MX_L1_TLS0_CNTL33__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL33__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL33__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL33__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL33__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL33__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL34
+#define MMMC_VM_MX_L1_TLS0_CNTL34__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL34__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL34__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL34__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL34__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL34__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL35
+#define MMMC_VM_MX_L1_TLS0_CNTL35__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL35__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL35__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL35__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL35__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL35__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL36
+#define MMMC_VM_MX_L1_TLS0_CNTL36__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL36__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL36__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL36__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL36__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL36__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL37
+#define MMMC_VM_MX_L1_TLS0_CNTL37__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL37__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL37__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL37__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL37__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL37__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32__START_ADDR_LO32__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32__START_ADDR_HI4__SHIFT                                            0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32__START_ADDR_LO32__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32__START_ADDR_HI4__SHIFT                                            0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32__START_ADDR_LO32__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32__START_ADDR_HI4__SHIFT                                            0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32__START_ADDR_LO32__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32__START_ADDR_HI4__SHIFT                                            0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32__START_ADDR_LO32__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32__START_ADDR_HI4__SHIFT                                            0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32__START_ADDR_LO32__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32__START_ADDR_HI4__SHIFT                                            0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32__START_ADDR_LO32__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32__START_ADDR_HI4__SHIFT                                            0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32__START_ADDR_LO32__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32__START_ADDR_HI4__SHIFT                                            0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32__START_ADDR_LO32__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32__START_ADDR_HI4__SHIFT                                            0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32__START_ADDR_LO32__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32__START_ADDR_HI4__SHIFT                                            0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32__END_ADDR_LO32__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32__END_ADDR_HI4__SHIFT                                                0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32__END_ADDR_LO32__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32__END_ADDR_HI4__SHIFT                                                0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32__END_ADDR_LO32__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32__END_ADDR_HI4__SHIFT                                                0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32__END_ADDR_LO32__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32__END_ADDR_HI4__SHIFT                                                0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32__END_ADDR_LO32__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32__END_ADDR_HI4__SHIFT                                                0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32__END_ADDR_LO32__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32__END_ADDR_HI4__SHIFT                                                0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32__END_ADDR_LO32__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32__END_ADDR_HI4__SHIFT                                                0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32__END_ADDR_LO32__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32__END_ADDR_HI4__SHIFT                                                0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32__END_ADDR_LO32__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32__END_ADDR_HI4__SHIFT                                                0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32__END_ADDR_LO32__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32__END_ADDR_HI4__SHIFT                                                0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32__INVALIDATE_STREAM_LO32__SHIFT                              0x0
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32__INVALIDATE_STREAM_LO32_MASK                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32__INVALIDATE_STREAM_HI6__SHIFT                               0x0
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32__INVALIDATE_STREAM_HI6_MASK                                 0x0000003FL
+//MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32__INVALIDATE_REQUEST_PENDING_LO32__SHIFT            0x0
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32__INVALIDATE_REQUEST_PENDING_LO32_MASK              0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32__INVALIDATE_REQUEST_PENDING_HI6__SHIFT             0x0
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32__INVALIDATE_REQUEST_PENDING_HI6_MASK               0x0000003FL
+//MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT                                        0x0
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT                                   0xc
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT                                   0x18
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__VMID__SHIFT                                               0x19
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT                                             0x1d
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK                                          0x000000FFL
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK                                     0x001FF000L
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK                                     0x01000000L
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__VMID_MASK                                                 0x1E000000L
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC_MASK                                               0x20000000L
+//MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT                          0x0
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT                           0x0
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK                             0x0000000FL
+//MMVM_L2_SAW_CNTL
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_CACHE__SHIFT                                                              0x0
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT                                                0x1
+#define MMVM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT                                                0x2
+#define MMVM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT                                                0x4
+#define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT                                            0x8
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                      0x9
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                     0xa
+#define MMVM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                     0xb
+#define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT                                                     0xc
+#define MMVM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT                                                      0xf
+#define MMVM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT                                                     0x12
+#define MMVM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT                                                0x13
+#define MMVM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT                                                  0x15
+#define MMVM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT                                              0x1a
+#define MMVM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT                                            0x1c
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_CACHE_MASK                                                                0x00000001L
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK                                                  0x00000002L
+#define MMVM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK                                                  0x0000000CL
+#define MMVM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK                                                  0x00000030L
+#define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK                                              0x00000100L
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK                                        0x00000200L
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK                                       0x00000400L
+#define MMVM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                       0x00000800L
+#define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK                                                       0x00007000L
+#define MMVM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK                                                        0x00038000L
+#define MMVM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION_MASK                                                       0x00040000L
+#define MMVM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK                                                  0x00180000L
+#define MMVM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK                                                    0x03E00000L
+#define MMVM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK                                                0x0C000000L
+#define MMVM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK                                              0x70000000L
+//MMVM_L2_SAW_CNTL2
+#define MMVM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT                                                      0x0
+#define MMVM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE__SHIFT                                                         0x1
+#define MMVM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT                                               0x15
+#define MMVM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT                                             0x16
+#define MMVM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT                                                     0x17
+#define MMVM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE__SHIFT                                                       0x1a
+#define MMVM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                    0x1c
+#define MMVM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK                                                        0x00000001L
+#define MMVM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE_MASK                                                           0x00000002L
+#define MMVM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK                                                 0x00200000L
+#define MMVM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK                                               0x00400000L
+#define MMVM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK                                                       0x03800000L
+#define MMVM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE_MASK                                                         0x0C000000L
+#define MMVM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK                                                      0x70000000L
+//MMVM_L2_SAW_CNTL3
+#define MMVM_L2_SAW_CNTL3__BANK_SELECT__SHIFT                                                                 0x0
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT                                                        0x6
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                    0x8
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                                                 0xf
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT                                                 0x14
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                  0x15
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT                                                0x18
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT                                                      0x1c
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT                                                    0x1d
+#define MMVM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT                                                        0x1e
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT                                                   0x1f
+#define MMVM_L2_SAW_CNTL3__BANK_SELECT_MASK                                                                   0x0000003FL
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE_MASK                                                          0x000000C0L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                      0x00001F00L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                                                   0x000F8000L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK                                                   0x00100000L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                    0x00E00000L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                  0x0F000000L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK                                                        0x10000000L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK                                                      0x20000000L
+#define MMVM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS_MASK                                                          0x40000000L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK                                                     0x80000000L
+//MMVM_L2_SAW_CNTL4
+#define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT                                                 0x0
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT                                       0x6
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT                                         0x7
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT                                          0x8
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT                                       0x9
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT                                         0xa
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT                                          0xb
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT                                       0xc
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT                                         0xd
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT                                          0xe
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT                                       0xf
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT                                         0x10
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT                                          0x11
+#define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING__SHIFT                                               0x12
+#define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK                                                   0x0000003FL
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK                                         0x00000040L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK                                           0x00000080L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK                                            0x00000100L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK                                         0x00000200L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK                                           0x00000400L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK                                            0x00000800L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK                                         0x00001000L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK                                           0x00002000L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK                                            0x00004000L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK                                         0x00008000L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK                                           0x00010000L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK                                            0x00020000L
+#define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING_MASK                                                 0x00040000L
+//MMVM_L2_SAW_CONTEXT0_CNTL
+#define MMVM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
+#define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x3
+#define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x4
+#define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0x6
+#define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0x7
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT                                   0xb
+#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xc
+#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xd
+#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT                                  0xe
+#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
+#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
+#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT                                   0x11
+#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x12
+#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x13
+#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT                                  0x14
+#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
+#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
+#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT                                0x17
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x18
+#define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x1c
+#define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x1d
+#define MMVM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000008L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000010L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000040L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00000080L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK                                     0x00000800L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00001000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00002000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK                                    0x00004000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK                                     0x00020000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00040000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00080000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK                                    0x00100000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK                                  0x00800000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x0F000000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x10000000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x20000000L
+//MMVM_L2_SAW_CONTEXT0_CNTL2
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                 0x0
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT  0x1
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT      0x2
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT              0x3
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT                                      0x4
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                   0x00000001L
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK    0x00000002L
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK        0x00000004L
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK                0x00000008L
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK                                        0x00000010L
+//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
+//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
+//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
+//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
+//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
+//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
+//MMVM_L2_SAW_CONTEXTS_DISABLE
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT                                                0x0
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT                                                0x1
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT                                                0x2
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT                                                0x3
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT                                                0x4
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT                                                0x5
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT                                                0x6
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT                                                0x7
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT                                                0x8
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT                                                0x9
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT                                               0xa
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT                                               0xb
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT                                               0xc
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT                                               0xd
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT                                               0xe
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT                                               0xf
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK                                                  0x00000001L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK                                                  0x00000002L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK                                                  0x00000004L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK                                                  0x00000008L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK                                                  0x00000010L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK                                                  0x00000020L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK                                                  0x00000040L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK                                                  0x00000080L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK                                                  0x00000100L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK                                                  0x00000200L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK                                                 0x00000400L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK                                                 0x00000800L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK                                                 0x00001000L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK                                                 0x00002000L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK                                                 0x00004000L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK                                                 0x00008000L
+//MMVM_L2_SAW_PIPES_BUSY_LO32
+#define MMVM_L2_SAW_PIPES_BUSY_LO32__PIPES_BUSY_LO32__SHIFT                                                   0x0
+#define MMVM_L2_SAW_PIPES_BUSY_LO32__PIPES_BUSY_LO32_MASK                                                     0xFFFFFFFFL
+//MMVM_L2_SAW_PIPES_BUSY_HI32
+#define MMVM_L2_SAW_PIPES_BUSY_HI32__PIPES_BUSY_HI32__SHIFT                                                   0x0
+#define MMVM_L2_SAW_PIPES_BUSY_HI32__PIPES_BUSY_HI32_MASK                                                     0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__MORE_FAULTS__SHIFT                                             0x0
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__ABORT_STATUS__SHIFT                                            0x1
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__STREAM_ID__SHIFT                                               0x3
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__MORE_FAULTS_MASK                                               0x00000001L
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__ABORT_STATUS_MASK                                              0x00000006L
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__STREAM_ID_MASK                                                 0x000001F8L
+//MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT                             0x0
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK                               0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT                              0x0
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK                                0x0000000FL
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2dec
+//MM_ATC_L2_CNTL
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT                                            0x0
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT                                           0x3
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT                                0x6
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT                               0x7
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT                                       0x8
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT                                      0xb
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT                           0xe
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT                          0xf
+#define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT                                                          0x10
+#define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                       0x13
+#define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT                                                            0x14
+#define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT                                                          0x16
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK                                              0x00000003L
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK                                             0x00000018L
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK                                  0x00000040L
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK                                 0x00000080L
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK                                         0x00000300L
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK                                        0x00001800L
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK                             0x00004000L
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK                            0x00008000L
+#define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK                                                            0x00070000L
+#define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                         0x00080000L
+#define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK                                                              0x00300000L
+#define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK                                                            0x0FC00000L
+//MM_ATC_L2_CNTL2
+#define MM_ATC_L2_CNTL2__BANK_SELECT__SHIFT                                                                   0x0
+#define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT                                                                0x6
+#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT                                                          0x9
+#define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                           0xb
+#define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT                                                  0xc
+#define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT                                                            0xf
+#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                      0x12
+#define MM_ATC_L2_CNTL2__BANK_SELECT_MASK                                                                     0x0000003FL
+#define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK                                                                  0x000001C0L
+#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK                                                            0x00000600L
+#define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK                                             0x00000800L
+#define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK                                                    0x00007000L
+#define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK                                                              0x00038000L
+#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                        0x00FC0000L
+//MM_ATC_L2_CACHE_DATA0
+#define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT                                                     0x0
+#define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT                                                       0x1
+#define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT                                                       0x2
+#define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT                                               0x18
+#define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK                                                       0x00000001L
+#define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK                                                         0x00000002L
+#define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK                                                         0x00FFFFFCL
+#define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK                                                 0x0F000000L
+//MM_ATC_L2_CACHE_DATA1
+#define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT                                                0x0
+#define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK                                                  0xFFFFFFFFL
+//MM_ATC_L2_CACHE_DATA2
+#define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT                                                   0x0
+#define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK                                                     0xFFFFFFFFL
+//MM_ATC_L2_CNTL3
+#define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT                                                 0x0
+#define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE__SHIFT                                                   0x6
+#define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE__SHIFT                                                   0xc
+#define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT                                               0x12
+#define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT                                                     0x15
+#define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT                                                     0x1b
+#define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT                                                             0x1e
+#define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE_MASK                                                   0x0000003FL
+#define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE_MASK                                                     0x00000FC0L
+#define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE_MASK                                                     0x0003F000L
+#define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK                                                 0x001C0000L
+#define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK                                                       0x07E00000L
+#define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK                                                       0x38000000L
+#define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK                                                               0x40000000L
+//MM_ATC_L2_CNTL4
+#define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT                                              0x0
+#define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE__SHIFT                                                0x6
+#define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE__SHIFT                                                0xc
+#define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE_MASK                                                0x0000003FL
+#define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE_MASK                                                  0x00000FC0L
+#define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE_MASK                                                  0x0003F000L
+//MM_ATC_L2_CNTL5
+#define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                       0x0
+#define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                      0xa
+#define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                         0x000003FFL
+#define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                        0x000FFC00L
+//MM_ATC_L2_MM_GROUP_RT_CLASSES
+#define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT                                                  0x0
+#define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK                                                    0xFFFFFFFFL
+//MM_ATC_L2_STATUS
+#define MM_ATC_L2_STATUS__BUSY__SHIFT                                                                         0x0
+#define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS__SHIFT                                                   0x1
+#define MM_ATC_L2_STATUS__BUSY_MASK                                                                           0x00000001L
+#define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS_MASK                                                     0x00000002L
+//MM_ATC_L2_STATUS2
+#define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT                                           0x0
+#define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT                                               0x8
+#define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK                                             0x000000FFL
+#define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK                                                 0x0000FF00L
+//MM_ATC_L2_MISC_CG
+#define MM_ATC_L2_MISC_CG__OFFDLY__SHIFT                                                                      0x6
+#define MM_ATC_L2_MISC_CG__ENABLE__SHIFT                                                                      0x12
+#define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT                                                               0x13
+#define MM_ATC_L2_MISC_CG__OFFDLY_MASK                                                                        0x00000FC0L
+#define MM_ATC_L2_MISC_CG__ENABLE_MASK                                                                        0x00040000L
+#define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK                                                                 0x00080000L
+//MM_ATC_L2_MEM_POWER_LS
+#define MM_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT                                                               0x0
+#define MM_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT                                                                0x6
+#define MM_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK                                                                 0x0000003FL
+#define MM_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK                                                                  0x00000FC0L
+//MM_ATC_L2_CGTT_CLK_CTRL
+#define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                              0x0
+#define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                        0x5
+#define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT                                                  0xd
+#define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT                                                            0x1e
+#define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT                                                         0x1f
+#define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                0x0000001FL
+#define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                          0x00001FE0L
+#define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK                                                    0x1FFFE000L
+#define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK                                                              0x40000000L
+#define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK                                                           0x80000000L
+//MM_ATC_L2_SDPPORT_CTRL
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT                                                      0x0
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT                                                   0x1
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT                                                  0x2
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT                                               0x3
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT                                                      0x4
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT                                                   0x5
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT                                                        0x6
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT                                                     0x7
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT                                                   0x8
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT                                                0x9
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK                                                        0x00000001L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK                                                     0x00000002L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK                                                    0x00000004L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK                                                 0x00000008L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK                                                        0x00000010L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK                                                     0x00000020L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK                                                          0x00000040L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK                                                       0x00000080L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK                                                     0x00000100L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK                                                  0x00000200L
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pfdec
+//MMVM_L2_CNTL
+#define MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT                                                                  0x0
+#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT                                                    0x1
+#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT                                                    0x2
+#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT                                                    0x4
+#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT                                                0x8
+#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                          0x9
+#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                         0xa
+#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                         0xb
+#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT                                                         0xc
+#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT                                                          0xf
+#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT                                                         0x12
+#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT                                                    0x13
+#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT                                                      0x15
+#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT                                                           0x1a
+#define MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK                                                                    0x00000001L
+#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK                                                      0x00000002L
+#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK                                                      0x0000000CL
+#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK                                                      0x00000030L
+#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK                                                  0x00000100L
+#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK                                            0x00000200L
+#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK                                           0x00000400L
+#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                           0x00000800L
+#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK                                                           0x00007000L
+#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK                                                            0x00038000L
+#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK                                                           0x00040000L
+#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK                                                      0x00180000L
+#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK                                                        0x03E00000L
+#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK                                                             0x0C000000L
+//MMVM_L2_CNTL2
+#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT                                                          0x0
+#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT                                                             0x1
+#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT                                                   0x15
+#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT                                                 0x16
+#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT                                                          0x17
+#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT                                                           0x1a
+#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                        0x1c
+#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK                                                            0x00000001L
+#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK                                                               0x00000002L
+#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK                                                     0x00200000L
+#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK                                                   0x00400000L
+#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK                                                            0x03800000L
+#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK                                                             0x0C000000L
+#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK                                                          0x70000000L
+//MMVM_L2_CNTL3
+#define MMVM_L2_CNTL3__BANK_SELECT__SHIFT                                                                     0x0
+#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT                                                            0x6
+#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                        0x8
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                                                     0xf
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT                                                     0x14
+#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                      0x15
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT                                                    0x18
+#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT                                                          0x1c
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT                                                        0x1d
+#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT                                                            0x1e
+#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT                                                       0x1f
+#define MMVM_L2_CNTL3__BANK_SELECT_MASK                                                                       0x0000003FL
+#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK                                                              0x000000C0L
+#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                          0x00001F00L
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                                                       0x000F8000L
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK                                                       0x00100000L
+#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                        0x00E00000L
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                      0x0F000000L
+#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK                                                            0x10000000L
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK                                                          0x20000000L
+#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK                                                              0x40000000L
+#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK                                                         0x80000000L
+//MMVM_L2_STATUS
+#define MMVM_L2_STATUS__L2_BUSY__SHIFT                                                                        0x0
+#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT                                                            0x1
+#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT                                               0x11
+#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT                                             0x12
+#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT                                                 0x13
+#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT                                                 0x14
+#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT                                                 0x15
+#define MMVM_L2_STATUS__L2_BUSY_MASK                                                                          0x00000001L
+#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK                                                              0x0001FFFEL
+#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK                                                 0x00020000L
+#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK                                               0x00040000L
+#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK                                                   0x00080000L
+#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK                                                   0x00100000L
+#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK                                                   0x00200000L
+//MMVM_DUMMY_PAGE_FAULT_CNTL
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT                                            0x0
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT                                         0x1
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT                                            0x2
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK                                              0x00000001L
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK                                           0x00000002L
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK                                              0x000000FCL
+//MMVM_DUMMY_PAGE_FAULT_ADDR_LO32
+#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT                                          0x0
+#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMVM_DUMMY_PAGE_FAULT_ADDR_HI32
+#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT                                           0x0
+#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK                                             0x0000000FL
+//MMVM_INVALIDATE_CNTL
+#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT                                                      0x0
+#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT                                                      0x8
+#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK                                                        0x000000FFL
+#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK                                                        0x0000FF00L
+//MMVM_L2_PROTECTION_FAULT_CNTL
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                              0x0
+#define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT           0x1
+#define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0x2
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0x3
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0x4
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0x5
+#define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT               0x6
+#define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0x7
+#define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0x8
+#define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0x9
+#define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0xa
+#define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xb
+#define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                         0xc
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                              0xd
+#define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                        0x1d
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT                                         0x1e
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT                                            0x1f
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                0x00000001L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK             0x00000002L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00000004L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000008L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000010L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000020L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                 0x00000040L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000080L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000100L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00000200L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000400L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00000800L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                           0x00001000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                                0x1FFFE000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                          0x20000000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK                                           0x40000000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK                                              0x80000000L
+//MMVM_L2_PROTECTION_FAULT_CNTL2
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                                  0x0
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                            0x10
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT                                      0x11
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT                           0x12
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT                                   0x13
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                                    0x0000FFFFL
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                              0x00010000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK                                        0x00020000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK                             0x00040000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK                                     0x00080000L
+//MMVM_L2_PROTECTION_FAULT_MM_CNTL3
+#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                0x0
+#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                  0xFFFFFFFFL
+//MMVM_L2_PROTECTION_FAULT_MM_CNTL4
+#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT               0x0
+#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                 0xFFFFFFFFL
+//MMVM_L2_PROTECTION_FAULT_STATUS
+#define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT                                                   0x0
+#define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT                                                  0x1
+#define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT                                             0x4
+#define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT                                                 0x8
+#define MMVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT                                                           0x9
+#define MMVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT                                                            0x12
+#define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT                                                        0x13
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT                                                          0x14
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT                                                            0x18
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT                                                          0x19
+#define MMVM_L2_PROTECTION_FAULT_STATUS__PRT__SHIFT                                                           0x1d
+#define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK                                                     0x00000001L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK                                                    0x0000000EL
+#define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK                                               0x000000F0L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK                                                   0x00000100L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__CID_MASK                                                             0x0003FE00L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__RW_MASK                                                              0x00040000L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK                                                          0x00080000L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK                                                            0x00F00000L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VF_MASK                                                              0x01000000L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK                                                            0x1E000000L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__PRT_MASK                                                             0x20000000L
+//MMVM_L2_PROTECTION_FAULT_ADDR_LO32
+#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT                                     0x0
+#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK                                       0xFFFFFFFFL
+//MMVM_L2_PROTECTION_FAULT_ADDR_HI32
+#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT                                      0x0
+#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK                                        0x0000000FL
+//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
+#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT                            0x0
+#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK                              0xFFFFFFFFL
+//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
+#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT                             0x0
+#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK                               0x0000000FL
+//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                     0x0
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                       0xFFFFFFFFL
+//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                      0x0
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                        0x0000000FL
+//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                    0x0
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                      0xFFFFFFFFL
+//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                     0x0
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                       0x0000000FL
+//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
+#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT                       0x0
+#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK                         0xFFFFFFFFL
+//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
+#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT                        0x0
+#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK                          0x0000000FL
+//MMVM_L2_CNTL4
+#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT                                                     0x0
+#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT                                                    0x6
+#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT                                                    0x7
+#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                         0x8
+#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                        0x12
+#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT                                                             0x1c
+#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT                                                                  0x1d
+#define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT                                                             0x1e
+#define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT                                                        0x1f
+#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK                                                       0x0000003FL
+#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK                                                      0x00000040L
+#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK                                                      0x00000080L
+#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                           0x0003FF00L
+#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                          0x0FFC0000L
+#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK                                                               0x10000000L
+#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK                                                                    0x20000000L
+#define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK                                                               0x40000000L
+#define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK                                                          0x80000000L
+//MMVM_L2_MM_GROUP_RT_CLASSES
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT                                                  0x0
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT                                                  0x1
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT                                                  0x2
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT                                                  0x3
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT                                                  0x4
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT                                                  0x5
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT                                                  0x6
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT                                                  0x7
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT                                                  0x8
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT                                                  0x9
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT                                                 0xa
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT                                                 0xb
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT                                                 0xc
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT                                                 0xd
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT                                                 0xe
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT                                                 0xf
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT                                                 0x10
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT                                                 0x11
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT                                                 0x12
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT                                                 0x13
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT                                                 0x14
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT                                                 0x15
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT                                                 0x16
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT                                                 0x17
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT                                                 0x18
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT                                                 0x19
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT                                                 0x1a
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT                                                 0x1b
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT                                                 0x1c
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT                                                 0x1d
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT                                                 0x1e
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT                                                 0x1f
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK                                                    0x00000001L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK                                                    0x00000002L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK                                                    0x00000004L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK                                                    0x00000008L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK                                                    0x00000010L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK                                                    0x00000020L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK                                                    0x00000040L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK                                                    0x00000080L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK                                                    0x00000100L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK                                                    0x00000200L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK                                                   0x00000400L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK                                                   0x00000800L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK                                                   0x00001000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK                                                   0x00002000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK                                                   0x00004000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK                                                   0x00008000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK                                                   0x00010000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK                                                   0x00020000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK                                                   0x00040000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK                                                   0x00080000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK                                                   0x00100000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK                                                   0x00200000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK                                                   0x00400000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK                                                   0x00800000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK                                                   0x01000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK                                                   0x02000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK                                                   0x04000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK                                                   0x08000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK                                                   0x10000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK                                                   0x20000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK                                                   0x40000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK                                                   0x80000000L
+//MMVM_L2_BANK_SELECT_RESERVED_CID
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT                                      0x0
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT                                     0xa
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT                                                       0x14
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                             0x18
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                          0x19
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT                                 0x1a
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK                                        0x000001FFL
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK                                       0x0007FC00L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK                                                         0x00100000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK                               0x01000000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                            0x02000000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK                                   0x7C000000L
+//MMVM_L2_BANK_SELECT_RESERVED_CID2
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT                                     0x0
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT                                    0xa
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT                                                      0x14
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                            0x18
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                         0x19
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT                                0x1a
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK                                       0x000001FFL
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK                                      0x0007FC00L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK                                                        0x00100000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK                              0x01000000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                           0x02000000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK                                  0x7C000000L
+//MMVM_L2_CACHE_PARITY_CNTL
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT                               0x0
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT                             0x1
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT                                  0x2
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT                               0x3
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT                             0x4
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT                                  0x5
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT                                                    0x6
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT                                                  0x9
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT                                                   0xc
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK                                 0x00000001L
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK                               0x00000002L
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK                                    0x00000004L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK                                 0x00000008L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK                               0x00000010L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK                                    0x00000020L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK                                                      0x000001C0L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK                                                    0x00000E00L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK                                                     0x0000F000L
+//MMVM_L2_CGTT_CLK_CTRL
+#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                0x0
+#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                          0x5
+#define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT                                                    0xd
+#define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT                                                              0x1e
+#define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT                                                           0x1f
+#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                  0x0000001FL
+#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                            0x00001FE0L
+#define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK                                                      0x1FFFE000L
+#define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK                                                                0x40000000L
+#define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK                                                             0x80000000L
+//MMVM_L2_CNTL5
+#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT                                                   0x0
+#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT                                                       0x5
+#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT                                                 0xe
+#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT                                                   0xf
+#define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF__SHIFT                                                          0x10
+#define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT                                                          0x11
+#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                                                     0x0000001FL
+#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK                                                         0x00003FE0L
+#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK                                                   0x00004000L
+#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK                                                     0x00008000L
+#define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF_MASK                                                            0x00010000L
+#define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK                                                            0x00020000L
+//MMVM_L2_GCR_CNTL
+#define MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT                                                                   0x0
+#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT                                                                0x1
+#define MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK                                                                     0x00000001L
+#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK                                                                  0x000003FEL
+//MMVM_L2_CGTT_BUSY_CTRL
+#define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT                                                             0x0
+#define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT                                                            0x5
+#define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK                                                               0x0000001FL
+#define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK                                                              0x00000020L
+//MMVM_L2_PTE_CACHE_DUMP_CNTL
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT                                                            0x0
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT                                                             0x1
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT                                                              0x4
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT                                                             0x8
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT                                                             0xc
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT                                                             0x10
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK                                                              0x00000001L
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK                                                               0x00000002L
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK                                                                0x000000F0L
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK                                                               0x00000F00L
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK                                                               0x0000F000L
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK                                                               0xFFFF0000L
+//MMVM_L2_PTE_CACHE_DUMP_READ
+#define MMVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT                                                              0x0
+#define MMVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK                                                                0xFFFFFFFFL
+//MMVM_L2_BANK_SELECT_MASKS
+#define MMVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT                                                               0x0
+#define MMVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT                                                               0x4
+#define MMVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT                                                               0x8
+#define MMVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT                                                               0xc
+#define MMVM_L2_BANK_SELECT_MASKS__MASK0_MASK                                                                 0x0000000FL
+#define MMVM_L2_BANK_SELECT_MASKS__MASK1_MASK                                                                 0x000000F0L
+#define MMVM_L2_BANK_SELECT_MASKS__MASK2_MASK                                                                 0x00000F00L
+#define MMVM_L2_BANK_SELECT_MASKS__MASK3_MASK                                                                 0x0000F000L
+//MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC
+#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT                                                   0x0
+#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT                                                    0xa
+#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK                                                     0x000003FFL
+#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK                                                      0x00000400L
+//MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC
+#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT                                        0x0
+#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT                                         0xa
+#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK                                          0x000003FFL
+#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK                                           0x00000400L
+//MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC
+#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT                                      0x0
+#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT                                       0xa
+#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK                                        0x000003FFL
+#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK                                         0x00000400L
+//MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT
+#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT                                               0x0
+#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT                                                0xa
+#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK                                                 0x000003FFL
+#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK                                                  0x00000400L
+//MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ
+#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT                                               0x0
+#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT                                                0xa
+#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK                                                 0x000003FFL
+#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK                                                  0x00000400L
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2vcdec
+//MMVM_CONTEXT0_CNTL
+#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
+#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
+#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
+#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
+#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
+#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
+#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
+#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
+#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
+#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
+#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
+#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
+#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
+#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
+#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
+#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
+#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
+#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
+#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
+#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
+#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
+#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
+#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
+#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
+#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
+#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
+#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
+#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
+#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
+#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
+#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
+#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
+#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
+#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
+#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
+#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
+#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
+#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
+#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
+#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
+#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
+#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
+//MMVM_CONTEXT1_CNTL
+#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
+#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
+#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
+#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
+#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
+#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
+#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
+#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
+#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
+#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
+#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
+#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
+#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
+#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
+#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
+#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
+#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
+#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
+#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
+#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
+#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
+#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
+#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
+#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
+#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
+#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
+#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
+#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
+#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
+#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
+#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
+#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
+#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
+#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
+#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
+#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
+#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
+#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
+#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
+#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
+#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
+#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
+//MMVM_CONTEXT2_CNTL
+#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
+#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
+#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
+#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
+#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
+#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
+#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
+#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
+#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
+#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
+#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
+#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
+#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
+#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
+#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
+#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
+#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
+#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
+#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
+#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
+#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
+#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
+#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
+#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
+#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
+#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
+#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
+#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
+#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
+#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
+#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
+#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
+#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
+#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
+#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
+#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
+#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
+#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
+#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
+#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
+#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
+#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
+//MMVM_CONTEXT3_CNTL
+#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
+#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
+#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
+#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
+#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
+#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
+#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
+#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
+#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
+#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
+#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
+#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
+#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
+#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
+#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
+#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
+#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
+#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
+#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
+#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
+#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
+#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
+#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
+#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
+#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
+#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
+#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
+#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
+#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
+#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
+#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
+#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
+#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
+#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
+#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
+#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
+#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
+#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
+#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
+#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
+#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
+#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
+//MMVM_CONTEXT4_CNTL
+#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
+#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
+#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
+#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
+#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
+#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
+#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
+#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
+#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
+#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
+#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
+#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
+#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
+#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
+#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
+#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
+#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
+#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
+#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
+#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
+#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
+#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
+#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
+#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
+#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
+#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
+#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
+#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
+#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
+#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
+#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
+#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
+#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
+#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
+#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
+#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
+#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
+#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
+#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
+#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
+#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
+#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
+//MMVM_CONTEXT5_CNTL
+#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
+#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
+#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
+#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
+#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
+#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
+#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
+#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
+#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
+#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
+#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
+#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
+#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
+#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
+#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
+#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
+#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
+#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
+#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
+#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
+#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
+#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
+#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
+#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
+#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
+#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
+#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
+#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
+#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
+#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
+#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
+#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
+#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
+#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
+#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
+#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
+#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
+#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
+#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
+#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
+#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
+#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
+//MMVM_CONTEXT6_CNTL
+#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
+#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
+#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
+#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
+#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
+#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
+#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
+#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
+#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
+#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
+#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
+#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
+#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
+#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
+#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
+#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
+#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
+#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
+#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
+#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
+#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
+#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
+#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
+#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
+#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
+#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
+#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
+#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
+#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
+#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
+#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
+#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
+#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
+#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
+#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
+#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
+#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
+#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
+#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
+#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
+#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
+#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
+//MMVM_CONTEXT7_CNTL
+#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
+#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
+#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
+#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
+#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
+#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
+#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
+#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
+#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
+#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
+#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
+#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
+#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
+#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
+#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
+#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
+#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
+#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
+#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
+#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
+#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
+#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
+#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
+#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
+#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
+#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
+#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
+#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
+#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
+#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
+#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
+#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
+#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
+#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
+#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
+#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
+#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
+#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
+#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
+#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
+#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
+#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
+//MMVM_CONTEXT8_CNTL
+#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
+#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
+#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
+#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
+#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
+#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
+#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
+#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
+#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
+#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
+#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
+#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
+#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
+#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
+#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
+#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
+#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
+#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
+#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
+#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
+#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
+#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
+#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
+#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
+#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
+#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
+#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
+#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
+#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
+#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
+#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
+#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
+#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
+#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
+#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
+#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
+#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
+#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
+#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
+#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
+#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
+#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
+//MMVM_CONTEXT9_CNTL
+#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
+#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
+#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
+#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
+#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
+#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
+#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
+#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
+#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
+#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
+#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
+#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
+#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
+#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
+#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
+#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
+#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
+#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
+#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
+#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
+#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
+#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
+#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
+#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
+#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
+#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
+#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
+#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
+#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
+#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
+#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
+#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
+#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
+#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
+#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
+#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
+#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
+#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
+#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
+#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
+#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
+#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
+//MMVM_CONTEXT10_CNTL
+#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
+#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
+#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
+#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
+#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
+#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
+#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
+#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
+#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
+#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
+#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
+#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
+#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
+#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
+#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
+#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
+#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
+#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
+#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
+#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x17
+#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x18
+#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
+#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
+#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
+#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
+#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
+#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
+#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
+#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
+#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
+#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
+#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
+#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
+#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
+#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
+#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
+#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
+#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
+#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
+#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
+#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00800000L
+#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x01000000L
+//MMVM_CONTEXT11_CNTL
+#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
+#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
+#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
+#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
+#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
+#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
+#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
+#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
+#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
+#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
+#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
+#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
+#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
+#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
+#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
+#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
+#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
+#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
+#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
+#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x17
+#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x18
+#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
+#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
+#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
+#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
+#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
+#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
+#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
+#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
+#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
+#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
+#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
+#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
+#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
+#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
+#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
+#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
+#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
+#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
+#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
+#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00800000L
+#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x01000000L
+//MMVM_CONTEXT12_CNTL
+#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
+#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
+#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
+#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
+#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
+#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
+#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
+#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
+#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
+#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
+#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
+#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
+#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
+#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
+#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
+#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
+#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
+#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
+#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
+#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x17
+#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x18
+#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
+#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
+#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
+#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
+#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
+#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
+#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
+#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
+#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
+#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
+#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
+#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
+#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
+#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
+#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
+#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
+#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
+#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
+#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
+#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00800000L
+#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x01000000L
+//MMVM_CONTEXT13_CNTL
+#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
+#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
+#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
+#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
+#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
+#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
+#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
+#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
+#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
+#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
+#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
+#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
+#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
+#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
+#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
+#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
+#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
+#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
+#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
+#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x17
+#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x18
+#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
+#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
+#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
+#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
+#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
+#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
+#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
+#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
+#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
+#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
+#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
+#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
+#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
+#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
+#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
+#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
+#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
+#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
+#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
+#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00800000L
+#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x01000000L
+//MMVM_CONTEXT14_CNTL
+#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
+#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
+#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
+#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
+#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
+#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
+#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
+#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
+#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
+#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
+#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
+#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
+#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
+#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
+#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
+#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
+#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
+#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
+#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
+#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x17
+#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x18
+#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
+#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
+#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
+#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
+#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
+#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
+#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
+#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
+#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
+#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
+#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
+#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
+#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
+#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
+#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
+#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
+#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
+#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
+#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
+#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00800000L
+#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x01000000L
+//MMVM_CONTEXT15_CNTL
+#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
+#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
+#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
+#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
+#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
+#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
+#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
+#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
+#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
+#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
+#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
+#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
+#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
+#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
+#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
+#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
+#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
+#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
+#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
+#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x17
+#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x18
+#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
+#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
+#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
+#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
+#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
+#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
+#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
+#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
+#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
+#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
+#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
+#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
+#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
+#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
+#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
+#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
+#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
+#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
+#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
+#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00800000L
+#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x01000000L
+//MMVM_CONTEXTS_DISABLE
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT                                                       0x0
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT                                                       0x1
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT                                                       0x2
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT                                                       0x3
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT                                                       0x4
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT                                                       0x5
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT                                                       0x6
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT                                                       0x7
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT                                                       0x8
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT                                                       0x9
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT                                                      0xa
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT                                                      0xb
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT                                                      0xc
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT                                                      0xd
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT                                                      0xe
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT                                                      0xf
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK                                                         0x00000001L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK                                                         0x00000002L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK                                                         0x00000004L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK                                                         0x00000008L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK                                                         0x00000010L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK                                                         0x00000020L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK                                                         0x00000040L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK                                                         0x00000080L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK                                                         0x00000100L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK                                                         0x00000200L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK                                                        0x00000400L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK                                                        0x00000800L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK                                                        0x00001000L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK                                                        0x00002000L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK                                                        0x00004000L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK                                                        0x00008000L
+//MMVM_INVALIDATE_ENG0_SEM
+#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT                                                            0x0
+#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK                                                              0x00000001L
+//MMVM_INVALIDATE_ENG1_SEM
+#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT                                                            0x0
+#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK                                                              0x00000001L
+//MMVM_INVALIDATE_ENG2_SEM
+#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT                                                            0x0
+#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK                                                              0x00000001L
+//MMVM_INVALIDATE_ENG3_SEM
+#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT                                                            0x0
+#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK                                                              0x00000001L
+//MMVM_INVALIDATE_ENG4_SEM
+#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT                                                            0x0
+#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK                                                              0x00000001L
+//MMVM_INVALIDATE_ENG5_SEM
+#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT                                                            0x0
+#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK                                                              0x00000001L
+//MMVM_INVALIDATE_ENG6_SEM
+#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT                                                            0x0
+#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK                                                              0x00000001L
+//MMVM_INVALIDATE_ENG7_SEM
+#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT                                                            0x0
+#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK                                                              0x00000001L
+//MMVM_INVALIDATE_ENG8_SEM
+#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT                                                            0x0
+#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK                                                              0x00000001L
+//MMVM_INVALIDATE_ENG9_SEM
+#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT                                                            0x0
+#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK                                                              0x00000001L
+//MMVM_INVALIDATE_ENG10_SEM
+#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK                                                             0x00000001L
+//MMVM_INVALIDATE_ENG11_SEM
+#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK                                                             0x00000001L
+//MMVM_INVALIDATE_ENG12_SEM
+#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK                                                             0x00000001L
+//MMVM_INVALIDATE_ENG13_SEM
+#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK                                                             0x00000001L
+//MMVM_INVALIDATE_ENG14_SEM
+#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK                                                             0x00000001L
+//MMVM_INVALIDATE_ENG15_SEM
+#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK                                                             0x00000001L
+//MMVM_INVALIDATE_ENG16_SEM
+#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK                                                             0x00000001L
+//MMVM_INVALIDATE_ENG17_SEM
+#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK                                                             0x00000001L
+//MMVM_INVALIDATE_ENG0_REQ
+#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
+#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
+#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT                                                          0x19
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
+#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
+#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
+#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK                                                            0x02000000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
+//MMVM_INVALIDATE_ENG1_REQ
+#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
+#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
+#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT                                                          0x19
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
+#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
+#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
+#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK                                                            0x02000000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
+//MMVM_INVALIDATE_ENG2_REQ
+#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
+#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
+#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT                                                          0x19
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
+#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
+#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
+#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK                                                            0x02000000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
+//MMVM_INVALIDATE_ENG3_REQ
+#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
+#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
+#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT                                                          0x19
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
+#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
+#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
+#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK                                                            0x02000000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
+//MMVM_INVALIDATE_ENG4_REQ
+#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
+#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
+#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT                                                          0x19
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
+#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
+#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
+#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK                                                            0x02000000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
+//MMVM_INVALIDATE_ENG5_REQ
+#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
+#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
+#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT                                                          0x19
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
+#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
+#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
+#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK                                                            0x02000000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
+//MMVM_INVALIDATE_ENG6_REQ
+#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
+#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
+#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT                                                          0x19
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
+#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
+#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
+#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK                                                            0x02000000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
+//MMVM_INVALIDATE_ENG7_REQ
+#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
+#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
+#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT                                                          0x19
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
+#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
+#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
+#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK                                                            0x02000000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
+//MMVM_INVALIDATE_ENG8_REQ
+#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
+#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
+#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT                                                          0x19
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
+#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
+#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
+#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK                                                            0x02000000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
+//MMVM_INVALIDATE_ENG9_REQ
+#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
+#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
+#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT                                                          0x19
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
+#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
+#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
+#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK                                                            0x02000000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
+//MMVM_INVALIDATE_ENG10_REQ
+#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT                                                          0x10
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
+#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
+#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT                                                         0x19
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
+#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
+#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
+#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK                                                           0x02000000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
+//MMVM_INVALIDATE_ENG11_REQ
+#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT                                                          0x10
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
+#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
+#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT                                                         0x19
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
+#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
+#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
+#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK                                                           0x02000000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
+//MMVM_INVALIDATE_ENG12_REQ
+#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT                                                          0x10
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
+#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
+#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT                                                         0x19
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
+#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
+#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
+#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK                                                           0x02000000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
+//MMVM_INVALIDATE_ENG13_REQ
+#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT                                                          0x10
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
+#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
+#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT                                                         0x19
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
+#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
+#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
+#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK                                                           0x02000000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
+//MMVM_INVALIDATE_ENG14_REQ
+#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT                                                          0x10
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
+#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
+#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT                                                         0x19
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
+#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
+#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
+#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK                                                           0x02000000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
+//MMVM_INVALIDATE_ENG15_REQ
+#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT                                                          0x10
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
+#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
+#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT                                                         0x19
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
+#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
+#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
+#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK                                                           0x02000000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
+//MMVM_INVALIDATE_ENG16_REQ
+#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT                                                          0x10
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
+#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
+#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT                                                         0x19
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
+#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
+#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
+#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK                                                           0x02000000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
+//MMVM_INVALIDATE_ENG17_REQ
+#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT                                                          0x10
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
+#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
+#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT                                                         0x19
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
+#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
+#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
+#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK                                                           0x02000000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
+//MMVM_INVALIDATE_ENG0_ACK
+#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT                                                            0x10
+#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK                                                              0x00010000L
+//MMVM_INVALIDATE_ENG1_ACK
+#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT                                                            0x10
+#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK                                                              0x00010000L
+//MMVM_INVALIDATE_ENG2_ACK
+#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT                                                            0x10
+#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK                                                              0x00010000L
+//MMVM_INVALIDATE_ENG3_ACK
+#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT                                                            0x10
+#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK                                                              0x00010000L
+//MMVM_INVALIDATE_ENG4_ACK
+#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT                                                            0x10
+#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK                                                              0x00010000L
+//MMVM_INVALIDATE_ENG5_ACK
+#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT                                                            0x10
+#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK                                                              0x00010000L
+//MMVM_INVALIDATE_ENG6_ACK
+#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT                                                            0x10
+#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK                                                              0x00010000L
+//MMVM_INVALIDATE_ENG7_ACK
+#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT                                                            0x10
+#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK                                                              0x00010000L
+//MMVM_INVALIDATE_ENG8_ACK
+#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT                                                            0x10
+#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK                                                              0x00010000L
+//MMVM_INVALIDATE_ENG9_ACK
+#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT                                                            0x10
+#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK                                                              0x00010000L
+//MMVM_INVALIDATE_ENG10_ACK
+#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK                                                             0x00010000L
+//MMVM_INVALIDATE_ENG11_ACK
+#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK                                                             0x00010000L
+//MMVM_INVALIDATE_ENG12_ACK
+#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK                                                             0x00010000L
+//MMVM_INVALIDATE_ENG13_ACK
+#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK                                                             0x00010000L
+//MMVM_INVALIDATE_ENG14_ACK
+#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK                                                             0x00010000L
+//MMVM_INVALIDATE_ENG15_ACK
+#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK                                                             0x00010000L
+//MMVM_INVALIDATE_ENG16_ACK
+#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK                                                             0x00010000L
+//MMVM_INVALIDATE_ENG17_ACK
+#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK                                                             0x00010000L
+//MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
+//MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
+//MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
+//MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
+//MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
+//MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
+//MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
+//MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
+//MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
+//MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
+//MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
+//MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
+//MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
+//MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
+//MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
+//MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
+//MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
+//MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
+//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
+//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
+//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
+//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
+//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
+//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
+//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
+//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
+//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
+//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
+//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
+//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
+//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
+//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
+//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
+//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
+//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
+//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
+//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
+//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
+//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
+//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
+//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
+//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
+//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
+//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
+//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
+//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
+//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
+//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
+//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
+//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
+//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
+//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
+//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
+//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
+//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
+//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
+//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
+//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
+//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
+//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
+//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
+//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
+//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
+//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
+//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
+//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
+//MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT                       0x0
+#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                         0x5
+#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                         0xa
+#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                         0x0000001FL
+#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                           0x000003E0L
+#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                           0x0000FC00L
+//MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
+#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
+#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
+#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
+#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
+#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
+//MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
+#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
+#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
+#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
+#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
+#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
+//MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
+#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
+#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
+#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
+#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
+#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
+//MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
+#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
+#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
+#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
+#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
+#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
+//MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
+#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
+#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
+#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
+#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
+#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
+//MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
+#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
+#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
+#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
+#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
+#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
+//MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
+#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
+#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
+#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
+#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
+#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
+//MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
+#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
+#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
+#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
+#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
+#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
+//MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
+#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
+#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
+#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
+#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
+#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
+//MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
+#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
+#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
+#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
+#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
+#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
+//MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
+#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
+#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
+#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
+#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
+#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
+//MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
+#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
+#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
+#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
+#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
+#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
+//MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
+#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
+#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
+#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
+#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
+#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
+//MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
+#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
+#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
+#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
+#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
+#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
+//MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
+#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
+#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
+#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
+#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
+#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
+//MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
+#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
+#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
+#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
+#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
+#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pldec
+//MMMC_VM_L2_PERFCOUNTER0_CFG
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                      0x8
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                         0x18
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                            0x1c
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                             0x1d
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                            0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                           0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                              0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                               0x20000000L
+//MMMC_VM_L2_PERFCOUNTER1_CFG
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                      0x8
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                         0x18
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                            0x1c
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                             0x1d
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                            0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                           0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                              0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                               0x20000000L
+//MMMC_VM_L2_PERFCOUNTER2_CFG
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                      0x8
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                         0x18
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                            0x1c
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                             0x1d
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                            0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                           0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK                                                              0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK                                                               0x20000000L
+//MMMC_VM_L2_PERFCOUNTER3_CFG
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                      0x8
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                         0x18
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                            0x1c
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                             0x1d
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                            0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                           0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK                                                              0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK                                                               0x20000000L
+//MMMC_VM_L2_PERFCOUNTER4_CFG
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT                                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT                                                      0x8
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT                                                         0x18
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT                                                            0x1c
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT                                                             0x1d
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK                                                            0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK                                                           0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK                                                              0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK                                                               0x20000000L
+//MMMC_VM_L2_PERFCOUNTER5_CFG
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT                                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT                                                      0x8
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT                                                         0x18
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT                                                            0x1c
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT                                                             0x1d
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK                                                            0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK                                                           0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK                                                              0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK                                                               0x20000000L
+//MMMC_VM_L2_PERFCOUNTER6_CFG
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT                                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT                                                      0x8
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT                                                         0x18
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT                                                            0x1c
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT                                                             0x1d
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK                                                            0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK                                                           0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK                                                              0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK                                                               0x20000000L
+//MMMC_VM_L2_PERFCOUNTER7_CFG
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT                                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT                                                      0x8
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT                                                         0x18
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT                                                            0x1c
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT                                                             0x1d
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK                                                            0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK                                                           0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK                                                              0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK                                                               0x20000000L
+//MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                0x8
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                 0x10
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                   0x18
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                    0x19
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                         0x1a
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                            0x0000000FL
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                  0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                   0x00FF0000L
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                     0x01000000L
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                      0x02000000L
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                           0x04000000L
+//MMUTCL2_PERFCOUNTER0_CFG
+#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                             0x0
+#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                         0x8
+#define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                            0x18
+#define MMUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                               0x1c
+#define MMUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                0x1d
+#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                               0x000000FFL
+#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
+#define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                              0x0F000000L
+#define MMUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK                                                                 0x10000000L
+#define MMUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                  0x20000000L
+//MMUTCL2_PERFCOUNTER1_CFG
+#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                             0x0
+#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                         0x8
+#define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                            0x18
+#define MMUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                               0x1c
+#define MMUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                0x1d
+#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                               0x000000FFL
+#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
+#define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                              0x0F000000L
+#define MMUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK                                                                 0x10000000L
+#define MMUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                  0x20000000L
+//MMUTCL2_PERFCOUNTER2_CFG
+#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                             0x0
+#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                         0x8
+#define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                            0x18
+#define MMUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                               0x1c
+#define MMUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                0x1d
+#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                               0x000000FFL
+#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
+#define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                              0x0F000000L
+#define MMUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK                                                                 0x10000000L
+#define MMUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK                                                                  0x20000000L
+//MMUTCL2_PERFCOUNTER3_CFG
+#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                             0x0
+#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                         0x8
+#define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                            0x18
+#define MMUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                               0x1c
+#define MMUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                                0x1d
+#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                               0x000000FFL
+#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
+#define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                              0x0F000000L
+#define MMUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK                                                                 0x10000000L
+#define MMUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK                                                                  0x20000000L
+//MMUTCL2_PERFCOUNTER_RSLT_CNTL
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                             0x0
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                   0x8
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                    0x10
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                      0x18
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                       0x19
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                            0x1a
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                               0x0000000FL
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                     0x0000FF00L
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                      0x00FF0000L
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                        0x01000000L
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                         0x02000000L
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                              0x04000000L
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2prdec
+//MMMC_VM_L2_PERFCOUNTER_LO
+#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                            0xFFFFFFFFL
+//MMMC_VM_L2_PERFCOUNTER_HI
+#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                       0x10
+#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                            0x0000FFFFL
+#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                         0xFFFF0000L
+//MMUTCL2_PERFCOUNTER_LO
+#define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                             0x0
+#define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                               0xFFFFFFFFL
+//MMUTCL2_PERFCOUNTER_HI
+#define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                             0x0
+#define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                          0x10
+#define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                               0x0000FFFFL
+#define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                            0xFFFF0000L
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec
+//MMVM_PCIE_ATS_CNTL
+#define MMVM_PCIE_ATS_CNTL__STU__SHIFT                                                                        0x10
+#define MMVM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                                 0x1f
+#define MMVM_PCIE_ATS_CNTL__STU_MASK                                                                          0x001F0000L
+#define MMVM_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                                   0x80000000L
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec
+//MMMC_VM_NB_MMIOBASE
+#define MMMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT                                                                  0x0
+#define MMMC_VM_NB_MMIOBASE__MMIOBASE_MASK                                                                    0xFFFFFFFFL
+//MMMC_VM_NB_MMIOLIMIT
+#define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT                                                                0x0
+#define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK                                                                  0xFFFFFFFFL
+//MMMC_VM_NB_PCI_CTRL
+#define MMMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT                                                                0x17
+#define MMMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK                                                                  0x00800000L
+//MMMC_VM_NB_PCI_ARB
+#define MMMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT                                                                   0x3
+#define MMMC_VM_NB_PCI_ARB__VGA_HOLE_MASK                                                                     0x00000008L
+//MMMC_VM_NB_TOP_OF_DRAM_SLOT1
+#define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT                                                      0x17
+#define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK                                                        0xFF800000L
+//MMMC_VM_NB_LOWER_TOP_OF_DRAM2
+#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT                                                          0x0
+#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT                                                      0x17
+#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK                                                            0x00000001L
+#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK                                                        0xFF800000L
+//MMMC_VM_NB_UPPER_TOP_OF_DRAM2
+#define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT                                                      0x0
+#define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK                                                        0x00000FFFL
+//MMMC_VM_FB_OFFSET
+#define MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                                   0x0
+#define MMMC_VM_FB_OFFSET__FB_OFFSET_MASK                                                                     0x00FFFFFFL
+//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
+#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT                             0x0
+#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK                               0xFFFFFFFFL
+//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
+#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT                             0x0
+#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK                               0x0000000FL
+//MMMC_VM_STEERING
+#define MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT                                                             0x0
+#define MMMC_VM_STEERING__DEFAULT_STEERING_MASK                                                               0x00000003L
+//MMMC_SHARED_VIRT_RESET_REQ
+#define MMMC_SHARED_VIRT_RESET_REQ__VF__SHIFT                                                                 0x0
+#define MMMC_SHARED_VIRT_RESET_REQ__PF__SHIFT                                                                 0x1f
+#define MMMC_SHARED_VIRT_RESET_REQ__VF_MASK                                                                   0x0000FFFFL
+#define MMMC_SHARED_VIRT_RESET_REQ__PF_MASK                                                                   0x80000000L
+//MMMC_MEM_POWER_LS
+#define MMMC_MEM_POWER_LS__LS_SETUP__SHIFT                                                                    0x0
+#define MMMC_MEM_POWER_LS__LS_HOLD__SHIFT                                                                     0x6
+#define MMMC_MEM_POWER_LS__LS_SETUP_MASK                                                                      0x0000003FL
+#define MMMC_MEM_POWER_LS__LS_HOLD_MASK                                                                       0x00000FC0L
+//MMMC_VM_CACHEABLE_DRAM_ADDRESS_START
+#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT                                                  0x0
+#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK                                                    0x000FFFFFL
+//MMMC_VM_CACHEABLE_DRAM_ADDRESS_END
+#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT                                                    0x0
+#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK                                                      0x000FFFFFL
+//MMMC_VM_LOCAL_SYSMEM_ADDRESS_START
+#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT                                                    0x0
+#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK                                                      0x000FFFFFL
+//MMMC_VM_LOCAL_SYSMEM_ADDRESS_END
+#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT                                                      0x0
+#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK                                                        0x000FFFFFL
+//MMMC_VM_APT_CNTL
+#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT                                                               0x0
+#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT                                                             0x1
+#define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT                                                          0x2
+#define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT                                                               0x4
+#define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT                                                             0x5
+#define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT                                                   0x6
+#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK                                                                 0x00000001L
+#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK                                                               0x00000002L
+#define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK                                                            0x0000000CL
+#define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK                                                                 0x00000010L
+#define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK                                                               0x00000020L
+#define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK                                                     0x000000C0L
+//MMMC_VM_LOCAL_FB_ADDRESS_START
+#define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT                                                        0x0
+#define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK                                                          0x000FFFFFL
+//MMMC_VM_LOCAL_FB_ADDRESS_END
+#define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT                                                          0x0
+#define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK                                                            0x000FFFFFL
+//MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL
+#define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                                       0x0
+#define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK                                                         0x00000001L
+//MMUTCL2_CGTT_CLK_CTRL
+#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                0x0
+#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                          0x5
+#define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT                                                    0xd
+#define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT                                                              0x1e
+#define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT                                                           0x1f
+#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                  0x0000001FL
+#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                            0x00001FE0L
+#define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK                                                      0x1FFFE000L
+#define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE_MASK                                                                0x40000000L
+#define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK                                                             0x80000000L
+//MMMC_SHARED_ACTIVE_FCN_ID
+#define MMMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT                                                                0x0
+#define MMMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT                                                                  0x1e
+#define MMMC_SHARED_ACTIVE_FCN_ID__VFID_MASK                                                                  0x0000000FL
+#define MMMC_SHARED_ACTIVE_FCN_ID__VF_MASK                                                                    0x40000000L
+//MMUTCL2_CGTT_BUSY_CTRL
+#define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT                                                             0x0
+#define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT                                                            0x5
+#define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK                                                               0x0000001FL
+#define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK                                                              0x00000020L
+//MMUTCL2_HARVEST_BYPASS_GROUPS
+#define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT                                                   0x0
+#define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK                                                     0xFFFFFFFFL
+//MMUTCL2_GROUP_RET_FAULT_STATUS
+#define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT                                                   0x0
+#define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK                                                     0xFFFFFFFFL
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec
+//MMMC_VM_FB_LOCATION_BASE
+#define MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                              0x0
+#define MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                                0x00FFFFFFL
+//MMMC_VM_FB_LOCATION_TOP
+#define MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                                0x0
+#define MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                                  0x00FFFFFFL
+//MMMC_VM_AGP_TOP
+#define MMMC_VM_AGP_TOP__AGP_TOP__SHIFT                                                                       0x0
+#define MMMC_VM_AGP_TOP__AGP_TOP_MASK                                                                         0x00FFFFFFL
+//MMMC_VM_AGP_BOT
+#define MMMC_VM_AGP_BOT__AGP_BOT__SHIFT                                                                       0x0
+#define MMMC_VM_AGP_BOT__AGP_BOT_MASK                                                                         0x00FFFFFFL
+//MMMC_VM_AGP_BASE
+#define MMMC_VM_AGP_BASE__AGP_BASE__SHIFT                                                                     0x0
+#define MMMC_VM_AGP_BASE__AGP_BASE_MASK                                                                       0x00FFFFFFL
+//MMMC_VM_SYSTEM_APERTURE_LOW_ADDR
+#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT                                                 0x0
+#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK                                                   0x3FFFFFFFL
+//MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT                                                0x0
+#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK                                                  0x3FFFFFFFL
+//MMMC_VM_MX_L1_TLB_CNTL
+#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                          0x0
+#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                                     0x3
+#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                        0x5
+#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                           0x6
+#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT                                                               0x7
+#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT                                                                  0xb
+#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                            0x00000001L
+#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                                       0x00000018L
+#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                          0x00000020L
+#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                             0x00000040L
+#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK                                                                 0x00000780L
+#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK                                                                    0x00003800L
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec
+//MM_ATC_L2_PERFCOUNTER_LO
+#define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                           0x0
+#define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                             0xFFFFFFFFL
+//MM_ATC_L2_PERFCOUNTER_HI
+#define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                           0x0
+#define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                        0x10
+#define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                             0x0000FFFFL
+#define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                          0xFFFF0000L
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec
+//MM_ATC_L2_PERFCOUNTER0_CFG
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                           0x0
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                       0x8
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                          0x18
+#define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                             0x1c
+#define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                              0x1d
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                             0x000000FFL
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                         0x0000FF00L
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                            0x0F000000L
+#define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                               0x10000000L
+#define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                0x20000000L
+//MM_ATC_L2_PERFCOUNTER1_CFG
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                           0x0
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                       0x8
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                          0x18
+#define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                             0x1c
+#define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                              0x1d
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                             0x000000FFL
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                         0x0000FF00L
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                            0x0F000000L
+#define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                               0x10000000L
+#define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                0x20000000L
+//MM_ATC_L2_PERFCOUNTER_RSLT_CNTL
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                           0x0
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                 0x8
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                  0x10
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                    0x18
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                     0x19
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                          0x1a
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                             0x0000000FL
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                   0x0000FF00L
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                    0x00FF0000L
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                      0x01000000L
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                       0x02000000L
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                            0x04000000L
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pspdec
+//MMUTCL2_TRANSLATION_BYPASS_BY_VMID
+#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT                                         0x0
+#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT                                             0x10
+#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK                                           0x0000FFFFL
+#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK                                               0xFFFF0000L
+//MMVM_IOMMU_CONTROL_REGISTER
+#define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT                                                           0x0
+#define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK                                                             0x00000001L
+//MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
+#define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT                                0xd
+#define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK                                  0x00002000L
+//MMUTC_TRANSLATION_FAULT_CNTL0
+#define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT                               0x0
+#define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK                                 0xFFFFFFFFL
+//MMUTC_TRANSLATION_FAULT_CNTL1
+#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT                               0x0
+#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT                                                      0x4
+#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT                                                     0x5
+#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT                                                   0x6
+#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK                                 0x0000000FL
+#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK                                                        0x00000010L
+#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK                                                       0x00000020L
+#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK                                                     0x00000040L
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbpspdec
+//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT                                               0x0
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK                                                 0x00000001L
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pspdec
+//MM_ATC_L2_IOV_MODE_CNTL
+#define MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN__SHIFT                                                         0x0
+#define MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN_MASK                                                           0x00000001L
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbpfdec
+//MML2TLB_TLB0_STATUS
+#define MML2TLB_TLB0_STATUS__BUSY__SHIFT                                                                      0x0
+#define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                       0x1
+#define MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT                                                     0x2
+#define MML2TLB_TLB0_STATUS__BUSY_MASK                                                                        0x00000001L
+#define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK                                                         0x00000002L
+#define MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK                                                       0x00000004L
+//MML2TLB_TMZ_CNTL
+#define MML2TLB_TMZ_CNTL__TMZ_MODULATION__SHIFT                                                               0x0
+#define MML2TLB_TMZ_CNTL__TMZ_MODULATION_MASK                                                                 0x00000001L
+//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT                                           0x0
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK                                             0xFFFFFFFFL
+//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT                                           0x0
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT                                           0x4
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT                                           0x8
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT                                             0xc
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT                                            0xd
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT                                        0xf
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT                                        0x10
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT                                        0x11
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT                                      0x12
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT                                            0x1e
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK                                             0x0000000FL
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK                                             0x000000F0L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK                                             0x00000F00L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK                                               0x00001000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK                                              0x00006000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK                                          0x00008000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK                                          0x00010000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK                                          0x00020000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK                                        0x07FC0000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK                                              0x40000000L
+//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT                                          0x0
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK                                            0xFFFFFFFFL
+//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT                                          0x0
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT                                         0x4
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT                                 0x7
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT                                         0xd
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT                                           0xe
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT                                            0xf
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT                                       0x10
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT                                        0x11
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT                                         0x12
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT                                        0x15
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT                                          0x16
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT                                   0x18
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT                                           0x1f
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK                                            0x0000000FL
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK                                           0x00000070L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK                                   0x00001F80L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK                                           0x00002000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK                                             0x00004000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK                                              0x00008000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK                                         0x00010000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK                                          0x00020000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK                                           0x001C0000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK                                          0x00200000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK                                            0x00C00000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK                                     0x01000000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK                                             0x80000000L
+//MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ
+#define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT                                               0x0
+#define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE__SHIFT                                                 0xa
+#define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK                                                 0x000003FFL
+#define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE_MASK                                                   0x00000400L
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbpldec
+//MML2TLB_PERFCOUNTER0_CFG
+#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                             0x0
+#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                         0x8
+#define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                            0x18
+#define MML2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                               0x1c
+#define MML2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                0x1d
+#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                               0x000000FFL
+#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
+#define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                              0x0F000000L
+#define MML2TLB_PERFCOUNTER0_CFG__ENABLE_MASK                                                                 0x10000000L
+#define MML2TLB_PERFCOUNTER0_CFG__CLEAR_MASK                                                                  0x20000000L
+//MML2TLB_PERFCOUNTER1_CFG
+#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                             0x0
+#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                         0x8
+#define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                            0x18
+#define MML2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                               0x1c
+#define MML2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                0x1d
+#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                               0x000000FFL
+#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
+#define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                              0x0F000000L
+#define MML2TLB_PERFCOUNTER1_CFG__ENABLE_MASK                                                                 0x10000000L
+#define MML2TLB_PERFCOUNTER1_CFG__CLEAR_MASK                                                                  0x20000000L
+//MML2TLB_PERFCOUNTER2_CFG
+#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                             0x0
+#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                         0x8
+#define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                            0x18
+#define MML2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                               0x1c
+#define MML2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                0x1d
+#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                               0x000000FFL
+#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
+#define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                              0x0F000000L
+#define MML2TLB_PERFCOUNTER2_CFG__ENABLE_MASK                                                                 0x10000000L
+#define MML2TLB_PERFCOUNTER2_CFG__CLEAR_MASK                                                                  0x20000000L
+//MML2TLB_PERFCOUNTER3_CFG
+#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                             0x0
+#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                         0x8
+#define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                            0x18
+#define MML2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                               0x1c
+#define MML2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                                0x1d
+#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                               0x000000FFL
+#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
+#define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                              0x0F000000L
+#define MML2TLB_PERFCOUNTER3_CFG__ENABLE_MASK                                                                 0x10000000L
+#define MML2TLB_PERFCOUNTER3_CFG__CLEAR_MASK                                                                  0x20000000L
+//MML2TLB_PERFCOUNTER_RSLT_CNTL
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                             0x0
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                   0x8
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                    0x10
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                      0x18
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                       0x19
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                            0x1a
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                               0x0000000FL
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                     0x0000FF00L
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                      0x00FF0000L
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                        0x01000000L
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                         0x02000000L
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                              0x04000000L
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbprdec
+//MML2TLB_PERFCOUNTER_LO
+#define MML2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                             0x0
+#define MML2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK                                                               0xFFFFFFFFL
+//MML2TLB_PERFCOUNTER_HI
+#define MML2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                             0x0
+#define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                          0x10
+#define MML2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK                                                               0x0000FFFFL
+#define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                            0xFFFF0000L
+
+#endif
-- 
GitLab


From 10c4ad3ae025dd0e343a09d2ea4b0e71f8d10797 Mon Sep 17 00:00:00 2001
From: Huang Rui <ray.huang@amd.com>
Date: Thu, 12 May 2022 16:13:07 +0800
Subject: [PATCH 0178/1731] drm/amdgpu: add mmhub v3_0_1 ip block

This adds mmhub v3_0_1 ip block support

v2: rebase (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/Makefile       |   3 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c    |   4 +
 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c | 555 ++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.h |  28 ++
 4 files changed, 589 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 3e0e2eb7e2351..a87e42c2c8dc8 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -88,7 +88,8 @@ amdgpu-y += \
 	gmc_v8_0.o \
 	gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o mmhub_v9_4.o \
 	gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o mmhub_v2_3.o \
-	mmhub_v1_7.o gfxhub_v3_0.o mmhub_v3_0.o mmhub_v3_0_2.o gmc_v11_0.o
+	mmhub_v1_7.o gfxhub_v3_0.o mmhub_v3_0.o mmhub_v3_0_2.o gmc_v11_0.o \
+	mmhub_v3_0_1.o
 
 # add UMC block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 7f4b480ae66e1..9c225553f5b53 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -37,6 +37,7 @@
 #include "nbio_v4_3.h"
 #include "gfxhub_v3_0.h"
 #include "mmhub_v3_0.h"
+#include "mmhub_v3_0_1.h"
 #include "mmhub_v3_0_2.h"
 #include "athub_v3_0.h"
 
@@ -548,6 +549,9 @@ static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev)
 static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev)
 {
 	switch (adev->ip_versions[MMHUB_HWIP][0]) {
+	case IP_VERSION(3, 0, 1):
+		adev->mmhub.funcs = &mmhub_v3_0_1_funcs;
+		break;
 	case IP_VERSION(3, 0, 2):
 		adev->mmhub.funcs = &mmhub_v3_0_2_funcs;
 		break;
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
new file mode 100644
index 0000000000000..cac72ced94c85
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
@@ -0,0 +1,555 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+#include "mmhub_v3_0_1.h"
+
+#include "mmhub/mmhub_3_0_1_offset.h"
+#include "mmhub/mmhub_3_0_1_sh_mask.h"
+#include "navi10_enum.h"
+
+#include "soc15_common.h"
+
+#define regMMVM_L2_CNTL3_DEFAULT				0x80100007
+#define regMMVM_L2_CNTL4_DEFAULT				0x000000c1
+#define regMMVM_L2_CNTL5_DEFAULT				0x00003fe0
+
+static const char *mmhub_client_ids_v3_0_1[][2] = {
+	[0][0] = "VMC",
+	[4][0] = "DCEDMC",
+	[5][0] = "DCEVGA",
+	[6][0] = "MP0",
+	[7][0] = "MP1",
+	[8][0] = "MPIO",
+	[16][0] = "HDP",
+	[17][0] = "LSDMA",
+	[18][0] = "JPEG",
+	[19][0] = "VCNU0",
+	[21][0] = "VSCH",
+	[22][0] = "VCNU1",
+	[23][0] = "VCN1",
+	[32+20][0] = "VCN0",
+	[2][1] = "DBGUNBIO",
+	[3][1] = "DCEDWB",
+	[4][1] = "DCEDMC",
+	[5][1] = "DCEVGA",
+	[6][1] = "MP0",
+	[7][1] = "MP1",
+	[8][1] = "MPIO",
+	[10][1] = "DBGU0",
+	[11][1] = "DBGU1",
+	[12][1] = "DBGU2",
+	[13][1] = "DBGU3",
+	[14][1] = "XDP",
+	[15][1] = "OSSSYS",
+	[16][1] = "HDP",
+	[17][1] = "LSDMA",
+	[18][1] = "JPEG",
+	[19][1] = "VCNU0",
+	[20][1] = "VCN0",
+	[21][1] = "VSCH",
+	[22][1] = "VCNU1",
+	[23][1] = "VCN1",
+};
+
+static uint32_t mmhub_v3_0_1_get_invalidate_req(unsigned int vmid,
+						uint32_t flush_type)
+{
+	u32 req = 0;
+
+	/* invalidate using legacy mode on vmid*/
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
+			    PER_VMID_INVALIDATE_REQ, 1 << vmid);
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
+			    CLEAR_PROTECTION_FAULT_STATUS_ADDR,	0);
+
+	return req;
+}
+
+static void
+mmhub_v3_0_1_print_l2_protection_fault_status(struct amdgpu_device *adev,
+					      uint32_t status)
+{
+	uint32_t cid, rw;
+	const char *mmhub_cid = NULL;
+
+	cid = REG_GET_FIELD(status,
+			    MMVM_L2_PROTECTION_FAULT_STATUS, CID);
+	rw = REG_GET_FIELD(status,
+			   MMVM_L2_PROTECTION_FAULT_STATUS, RW);
+
+	dev_err(adev->dev,
+		"MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
+		status);
+
+	switch (adev->ip_versions[MMHUB_HWIP][0]) {
+	case IP_VERSION(3, 0, 1):
+		mmhub_cid = mmhub_client_ids_v3_0_1[cid][rw];
+		break;
+	default:
+		mmhub_cid = NULL;
+		break;
+	}
+
+	dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
+		mmhub_cid ? mmhub_cid : "unknown", cid);
+	dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
+		REG_GET_FIELD(status,
+		MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
+	dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
+		REG_GET_FIELD(status,
+		MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
+	dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
+		REG_GET_FIELD(status,
+		MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
+	dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
+		REG_GET_FIELD(status,
+		MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
+	dev_err(adev->dev, "\t RW: 0x%x\n", rw);
+}
+
+static void mmhub_v3_0_1_setup_vm_pt_regs(struct amdgpu_device *adev,
+					  uint32_t vmid,
+					  uint64_t page_table_base)
+{
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
+
+	WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+			    hub->ctx_addr_distance * vmid,
+			    lower_32_bits(page_table_base));
+
+	WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
+			    hub->ctx_addr_distance * vmid,
+			    upper_32_bits(page_table_base));
+}
+
+static void mmhub_v3_0_1_init_gart_aperture_regs(struct amdgpu_device *adev)
+{
+	uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
+
+	mmhub_v3_0_1_setup_vm_pt_regs(adev, 0, pt_base);
+
+	WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
+		     (u32)(adev->gmc.gart_start >> 12));
+	WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
+		     (u32)(adev->gmc.gart_start >> 44));
+
+	WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
+		     (u32)(adev->gmc.gart_end >> 12));
+	WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
+		     (u32)(adev->gmc.gart_end >> 44));
+}
+
+static void mmhub_v3_0_1_init_system_aperture_regs(struct amdgpu_device *adev)
+{
+	uint64_t value;
+	uint32_t tmp;
+
+	/* Program the AGP BAR */
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
+
+	/*
+	 * the new L1 policy will block SRIOV guest from writing
+	 * these regs, and they will be programed at host.
+	 * so skip programing these regs.
+	 */
+	/* Program the system aperture low logical page number. */
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
+		     adev->gmc.vram_start >> 18);
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+		     adev->gmc.vram_end >> 18);
+
+	/* Set default page address. */
+	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
+		adev->vm_manager.vram_base_offset;
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
+		     (u32)(value >> 12));
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
+		     (u32)(value >> 44));
+
+	/* Program "protection fault". */
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
+		     (u32)(adev->dummy_page_addr >> 12));
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
+		     (u32)((u64)adev->dummy_page_addr >> 44));
+
+	tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
+			    ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
+}
+
+static void mmhub_v3_0_1_init_tlb_regs(struct amdgpu_device *adev)
+{
+	uint32_t tmp;
+
+	/* Setup TLB control */
+	tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
+
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
+			    ENABLE_ADVANCED_DRIVER_MODEL, 1);
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
+			    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
+			    MTYPE, MTYPE_UC); /* UC, uncached */
+
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
+}
+
+static void mmhub_v3_0_1_init_cache_regs(struct amdgpu_device *adev)
+{
+	uint32_t tmp;
+
+	/* Setup L2 cache */
+	tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
+			    ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
+	/* XXX for emulation, Refer to closed source code.*/
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
+			    0);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
+
+	tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp);
+
+	tmp = regMMVM_L2_CNTL3_DEFAULT;
+	if (adev->gmc.translate_further) {
+		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
+		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
+				    L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
+	} else {
+		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
+		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
+				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
+	}
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp);
+
+	tmp = regMMVM_L2_CNTL4_DEFAULT;
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp);
+
+	tmp = regMMVM_L2_CNTL5_DEFAULT;
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
+	WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);
+}
+
+static void mmhub_v3_0_1_enable_system_domain(struct amdgpu_device *adev)
+{
+	uint32_t tmp;
+
+	tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
+	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
+	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
+	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
+			    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
+	WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp);
+}
+
+static void mmhub_v3_0_1_disable_identity_aperture(struct amdgpu_device *adev)
+{
+	WREG32_SOC15(MMHUB, 0,
+		     regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
+		     0xFFFFFFFF);
+	WREG32_SOC15(MMHUB, 0,
+		     regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
+		     0x0000000F);
+
+	WREG32_SOC15(MMHUB, 0,
+		     regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
+	WREG32_SOC15(MMHUB, 0,
+		     regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
+
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
+		     0);
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
+		     0);
+}
+
+static void mmhub_v3_0_1_setup_vmid_config(struct amdgpu_device *adev)
+{
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
+	int i;
+	uint32_t tmp;
+
+	for (i = 0; i <= 14; i++) {
+		tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
+				    adev->vm_manager.num_level);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
+				    1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    PAGE_TABLE_BLOCK_SIZE,
+				    adev->vm_manager.block_size - 9);
+		/* Send no-retry XNACK on fault to suppress VM fault storm. */
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
+				    !amdgpu_noretry);
+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL,
+				    i * hub->ctx_distance, tmp);
+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
+				    i * hub->ctx_addr_distance, 0);
+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
+				    i * hub->ctx_addr_distance, 0);
+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
+				    i * hub->ctx_addr_distance,
+				    lower_32_bits(adev->vm_manager.max_pfn - 1));
+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
+				    i * hub->ctx_addr_distance,
+				    upper_32_bits(adev->vm_manager.max_pfn - 1));
+	}
+
+	hub->vm_cntx_cntl = tmp;
+}
+
+static void mmhub_v3_0_1_program_invalidation(struct amdgpu_device *adev)
+{
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
+	unsigned i;
+
+	for (i = 0; i < 18; ++i) {
+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
+				    i * hub->eng_addr_distance, 0xffffffff);
+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
+				    i * hub->eng_addr_distance, 0x1f);
+	}
+}
+
+static int mmhub_v3_0_1_gart_enable(struct amdgpu_device *adev)
+{
+	/* GART Enable. */
+	mmhub_v3_0_1_init_gart_aperture_regs(adev);
+	mmhub_v3_0_1_init_system_aperture_regs(adev);
+	mmhub_v3_0_1_init_tlb_regs(adev);
+	mmhub_v3_0_1_init_cache_regs(adev);
+
+	mmhub_v3_0_1_enable_system_domain(adev);
+	mmhub_v3_0_1_disable_identity_aperture(adev);
+	mmhub_v3_0_1_setup_vmid_config(adev);
+	mmhub_v3_0_1_program_invalidation(adev);
+
+	return 0;
+}
+
+static void mmhub_v3_0_1_gart_disable(struct amdgpu_device *adev)
+{
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
+	u32 tmp;
+	u32 i;
+
+	/* Disable all tables */
+	for (i = 0; i < 16; i++)
+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL,
+				    i * hub->ctx_distance, 0);
+
+	/* Setup TLB control */
+	tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
+			    ENABLE_ADVANCED_DRIVER_MODEL, 0);
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
+
+	/* Setup L2 cache */
+	tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0);
+}
+
+/**
+ * mmhub_v3_0_1_set_fault_enable_default - update GART/VM fault handling
+ *
+ * @adev: amdgpu_device pointer
+ * @value: true redirects VM faults to the default page
+ */
+static void mmhub_v3_0_1_set_fault_enable_default(struct amdgpu_device *adev,
+						  bool value)
+{
+	u32 tmp;
+
+	tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
+			    value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	if (!value) {
+		tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+				CRASH_ON_NO_RETRY_FAULT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+				CRASH_ON_RETRY_FAULT, 1);
+	}
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
+}
+
+static const struct amdgpu_vmhub_funcs mmhub_v3_0_1_vmhub_funcs = {
+	.print_l2_protection_fault_status = mmhub_v3_0_1_print_l2_protection_fault_status,
+	.get_invalidate_req = mmhub_v3_0_1_get_invalidate_req,
+};
+
+static void mmhub_v3_0_1_init(struct amdgpu_device *adev)
+{
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
+
+	hub->ctx0_ptb_addr_lo32 =
+		SOC15_REG_OFFSET(MMHUB, 0,
+				 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
+	hub->ctx0_ptb_addr_hi32 =
+		SOC15_REG_OFFSET(MMHUB, 0,
+				 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
+	hub->vm_inv_eng0_sem =
+		SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM);
+	hub->vm_inv_eng0_req =
+		SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ);
+	hub->vm_inv_eng0_ack =
+		SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK);
+	hub->vm_context0_cntl =
+		SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
+	hub->vm_l2_pro_fault_status =
+		SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS);
+	hub->vm_l2_pro_fault_cntl =
+		SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
+
+	hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL;
+	hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
+		regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
+	hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ -
+		regMMVM_INVALIDATE_ENG0_REQ;
+	hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
+		regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
+
+	hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+		MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+		MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+		MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+		MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+		MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+		MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
+
+	hub->vmhub_funcs = &mmhub_v3_0_1_vmhub_funcs;
+}
+
+static u64 mmhub_v3_0_1_get_fb_location(struct amdgpu_device *adev)
+{
+	u64 base;
+
+	base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);
+	base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
+	base <<= 24;
+
+	return base;
+}
+
+static u64 mmhub_v3_0_1_get_mc_fb_offset(struct amdgpu_device *adev)
+{
+	return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;
+}
+
+static void mmhub_v3_0_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+							  bool enable)
+{
+	//TODO
+}
+
+static void mmhub_v3_0_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
+							 bool enable)
+{
+	//TODO
+}
+
+static int mmhub_v3_0_1_set_clockgating(struct amdgpu_device *adev,
+					enum amd_clockgating_state state)
+{
+	mmhub_v3_0_1_update_medium_grain_clock_gating(adev,
+			state == AMD_CG_STATE_GATE);
+	mmhub_v3_0_1_update_medium_grain_light_sleep(adev,
+			state == AMD_CG_STATE_GATE);
+	return 0;
+}
+
+static void mmhub_v3_0_1_get_clockgating(struct amdgpu_device *adev, u64 *flags)
+{
+	//TODO
+}
+
+const struct amdgpu_mmhub_funcs mmhub_v3_0_1_funcs = {
+	.init = mmhub_v3_0_1_init,
+	.get_fb_location = mmhub_v3_0_1_get_fb_location,
+	.get_mc_fb_offset = mmhub_v3_0_1_get_mc_fb_offset,
+	.gart_enable = mmhub_v3_0_1_gart_enable,
+	.set_fault_enable_default = mmhub_v3_0_1_set_fault_enable_default,
+	.gart_disable = mmhub_v3_0_1_gart_disable,
+	.set_clockgating = mmhub_v3_0_1_set_clockgating,
+	.get_clockgating = mmhub_v3_0_1_get_clockgating,
+	.setup_vm_pt_regs = mmhub_v3_0_1_setup_vm_pt_regs,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.h
new file mode 100644
index 0000000000000..4c1246735e7d8
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __MMHUB_V3_0_1_H__
+#define __MMHUB_V3_0_1_H__
+
+extern const struct amdgpu_mmhub_funcs mmhub_v3_0_1_funcs;
+
+#endif
-- 
GitLab


From 8763e4c1a0e6710dccb8fccba96fcd6caaa50cae Mon Sep 17 00:00:00 2001
From: Huang Rui <ray.huang@amd.com>
Date: Tue, 17 May 2022 14:58:41 +0800
Subject: [PATCH 0179/1731] drm/amdgpu/pm: update MP v13_0_4 smu message
 register marco

Update MP v13_0_4 register macro for SMU message

v2: squash in missed case (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 5de7da75d14a3..5215ead4978fd 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -51,6 +51,15 @@
 #define mmMP1_SMN_C2PMSG_90                                                                            0x029a
 #define mmMP1_SMN_C2PMSG_90_BASE_IDX                                                                   0
 
+#define mmMP1_SMN_C2PMSG_66_V13_0_4			0x0282
+#define mmMP1_SMN_C2PMSG_66_V13_0_4_BASE_IDX            1
+
+#define mmMP1_SMN_C2PMSG_82_V13_0_4			0x0292
+#define mmMP1_SMN_C2PMSG_82_V13_0_4_BASE_IDX            1
+
+#define mmMP1_SMN_C2PMSG_90_V13_0_4			0x029a
+#define mmMP1_SMN_C2PMSG_90_V13_0_4_BASE_IDX		1
+
 /* SMU 13.0.5 has its specific mailbox messaging registers */
 
 #define mmMP1_C2PMSG_2                                                                            (0xbee142 + 0xb00000 / 4)
@@ -92,6 +101,8 @@ static void smu_cmn_read_arg(struct smu_context *smu,
 
 	if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5))
 		*arg = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34);
+	else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4))
+		*arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4);
 	else
 		*arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
 }
@@ -141,6 +152,8 @@ static u32 __smu_cmn_poll_stat(struct smu_context *smu)
 	for ( ; timeout > 0; timeout--) {
 		if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5))
 			reg = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_33);
+		else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4))
+			reg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90_V13_0_4);
 		else
 			reg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
 		if ((reg & MP1_C2PMSG_90__CONTENT_MASK) != 0)
@@ -167,6 +180,9 @@ static void __smu_cmn_reg_print_error(struct smu_context *smu,
 		if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) {
 			msg_idx = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2);
 			prm     = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34);
+		} else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) {
+			msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66_V13_0_4);
+			prm     = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4);
 		} else {
 			msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66);
 			prm     = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
@@ -268,6 +284,10 @@ static void __smu_cmn_send_msg(struct smu_context *smu,
 		WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_33, 0);
 		WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34, param);
 		WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2, msg);
+	} else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) {
+		WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90_V13_0_4, 0);
+		WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4, param);
+		WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66_V13_0_4, msg);
 	} else {
 		WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 		WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
-- 
GitLab


From 7101ab97e3b00ec1c68d09826bb0521d17783673 Mon Sep 17 00:00:00 2001
From: Huang Rui <ray.huang@amd.com>
Date: Wed, 18 May 2022 21:19:32 +0800
Subject: [PATCH 0180/1731] drm/amdgpu/pm: implement the SMU_MSG_EnableGfxImu
 function

GC v11_0_1 asic needs to issue the EnableGfxImu message after start IMU.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/amdgpu_dpm.c                | 14 ++++++++++++++
 drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h            |  2 ++
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c          |  9 ++++++++-
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h      |  7 +++++++
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h       |  2 ++
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c     | 10 ++++++++++
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c   |  1 +
 7 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index d1bf073adf543..956b6ce81c846 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
@@ -107,6 +107,20 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block
 	return ret;
 }
 
+int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev)
+{
+	struct smu_context *smu = adev->powerplay.pp_handle;
+	int ret = -EOPNOTSUPP;
+
+	mutex_lock(&adev->pm.mutex);
+	ret = smu_set_gfx_power_up_by_imu(smu);
+	mutex_unlock(&adev->pm.mutex);
+
+	msleep(10);
+
+	return ret;
+}
+
 int amdgpu_dpm_baco_enter(struct amdgpu_device *adev)
 {
 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
index 3e78b3057277d..524fb09437e57 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
@@ -386,6 +386,8 @@ int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev);
 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,
 			     enum pp_mp1_state mp1_state);
 
+int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev);
+
 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev);
 
 int amdgpu_dpm_baco_enter(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index a601024ba4de8..ae595ee544dca 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -134,6 +134,14 @@ int smu_get_dpm_freq_range(struct smu_context *smu,
 	return ret;
 }
 
+int smu_set_gfx_power_up_by_imu(struct smu_context *smu)
+{
+	if (!smu->ppt_funcs && !smu->ppt_funcs->set_gfx_power_up_by_imu)
+		return -EOPNOTSUPP;
+
+	return smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
+}
+
 static u32 smu_get_mclk(void *handle, bool low)
 {
 	struct smu_context *smu = handle;
@@ -2467,7 +2475,6 @@ static int smu_set_power_profile_mode(void *handle,
 	return smu_bump_power_profile_mode(smu, param, param_size);
 }
 
-
 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode)
 {
 	struct smu_context *smu = handle;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index a6a7b6c33683e..c3d5a616e572e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -697,6 +697,11 @@ struct pptable_funcs {
 	 */
 	int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable);
 
+	/**
+	 * @set_gfx_power_up_by_imu: Enable GFX engine with IMU
+	 */
+	int (*set_gfx_power_up_by_imu)(struct smu_context *smu);
+
 	/**
 	 * @read_sensor: Read data from a sensor.
 	 * &sensor: Sensor to read data from.
@@ -1438,6 +1443,8 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 			    uint32_t min, uint32_t max);
 
+int smu_set_gfx_power_up_by_imu(struct smu_context *smu);
+
 int smu_set_ac_dc(struct smu_context *smu);
 
 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index 036fd2810ecca..08270d8528d9b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -292,6 +292,8 @@ int smu_v13_0_baco_enter(struct smu_context *smu);
 
 int smu_v13_0_baco_exit(struct smu_context *smu);
 
+int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu);
+
 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
 				enum PP_OD_DPM_TABLE_COMMAND type,
 				long input[],
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 7be4f6875a7bc..a56dddc9fb884 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2297,6 +2297,16 @@ int smu_v13_0_baco_exit(struct smu_context *smu)
 					SMU_BACO_STATE_EXIT);
 }
 
+int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu)
+{
+	uint16_t index;
+
+	index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
+					       SMU_MSG_EnableGfxImu);
+
+	return smu_cmn_send_msg_without_waiting(smu, index, 0);
+}
+
 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
 				enum PP_OD_DPM_TABLE_COMMAND type,
 				long input[], uint32_t size)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
index 5a17b51aa0f9f..29fcce04a91aa 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -1030,6 +1030,7 @@ static const struct pptable_funcs smu_v13_0_4_ppt_funcs = {
 	.force_clk_levels = smu_v13_0_4_force_clk_levels,
 	.set_performance_level = smu_v13_0_4_set_performance_level,
 	.set_fine_grain_gfx_freq_parameters = smu_v13_0_4_set_fine_grain_gfx_freq_parameters,
+	.set_gfx_power_up_by_imu = smu_v13_0_set_gfx_power_up_by_imu,
 };
 
 void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu)
-- 
GitLab


From 80d46fff373775fdea9917a7d13f6fb6fa5147ad Mon Sep 17 00:00:00 2001
From: Huang Rui <ray.huang@amd.com>
Date: Wed, 18 May 2022 22:05:03 +0800
Subject: [PATCH 0181/1731] drm/amdgpu: add apu sequence in the imu v11

APU required to issue the enable GFX IMU message after IMU reset.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 6 +++++-
 drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 7 ++++---
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index abe22749cccc8..5f20b41bcb93a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -6292,7 +6292,11 @@ static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev)
 
 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev)
 {
-	adev->gfx.imu.mode = DEBUG_MODE;
+	if (adev->flags & AMD_IS_APU)
+		adev->gfx.imu.mode = MISSION_MODE;
+	else
+		adev->gfx.imu.mode = DEBUG_MODE;
+
 	adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
index fd053158abbdd..76383baa3929a 100644
--- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
@@ -24,6 +24,7 @@
 #include <linux/firmware.h>
 #include "amdgpu.h"
 #include "amdgpu_imu.h"
+#include "amdgpu_dpm.h"
 
 #include "gc/gc_11_0_0_offset.h"
 #include "gc/gc_11_0_0_sh_mask.h"
@@ -165,10 +166,10 @@ static int imu_v11_0_start(struct amdgpu_device *adev)
 	imu_reg_val &= 0xfffffffe;
 	WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val);
 
-	if (adev->gfx.imu.mode == DEBUG_MODE)
-		return imu_v11_0_wait_for_reset_status(adev);
+	if (adev->flags & AMD_IS_APU)
+		amdgpu_dpm_set_gfx_power_up_by_imu(adev);
 
-	return 0;
+	return imu_v11_0_wait_for_reset_status(adev);
 }
 
 static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11[] =
-- 
GitLab


From cb12d72b426caa7594890c62df69fe4b83c96e58 Mon Sep 17 00:00:00 2001
From: Xiaojian Du <Xiaojian.Du@amd.com>
Date: Fri, 20 May 2022 22:27:57 +0800
Subject: [PATCH 0182/1731] drm/amdgpu: add CSDMA reg offsets for NBIO v7.7.0

This patch will add CSDMA reg offsets for NBIO v7.7.0

Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../drm/amd/include/asic_reg/nbio/nbio_7_7_0_offset.h  |  4 ++++
 .../drm/amd/include/asic_reg/nbio/nbio_7_7_0_sh_mask.h | 10 ++++++++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_offset.h
index 162d9017b2383..2ed95790a6006 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_offset.h
@@ -4005,6 +4005,8 @@
 #define regGDC0_BIF_VCN0_DOORBELL_RANGE_BASE_IDX                                                        3
 #define regGDC0_BIF_RLC_DOORBELL_RANGE                                                                  0x4f0af5
 #define regGDC0_BIF_RLC_DOORBELL_RANGE_BASE_IDX                                                         3
+#define regGDC0_BIF_CSDMA_DOORBELL_RANGE                                                                0x4f0afb
+#define regGDC0_BIF_CSDMA_DOORBELL_RANGE_BASE_IDX                                                       3
 #define regGDC0_ATDMA_MISC_CNTL                                                                         0x4f0afd
 #define regGDC0_ATDMA_MISC_CNTL_BASE_IDX                                                                3
 #define regGDC0_BIF_DOORBELL_FENCE_CNTL                                                                 0x4f0afe
@@ -21535,6 +21537,8 @@
 #define regGDC1_BIF_SDMA4_DOORBELL_RANGE_BASE_IDX                                                       5
 #define regGDC1_BIF_SDMA5_DOORBELL_RANGE                                                                0x2ffc0efa
 #define regGDC1_BIF_SDMA5_DOORBELL_RANGE_BASE_IDX                                                       5
+#define regGDC1_BIF_CSDMA_DOORBELL_RANGE                                                                0x2ffc0efb
+#define regGDC1_BIF_CSDMA_DOORBELL_RANGE_BASE_IDX                                                       5
 #define regGDC1_ATDMA_MISC_CNTL                                                                         0x2ffc0efd
 #define regGDC1_ATDMA_MISC_CNTL_BASE_IDX                                                                5
 #define regGDC1_BIF_DOORBELL_FENCE_CNTL                                                                 0x2ffc0efe
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_sh_mask.h
index cc3f04cfdbf78..eb62a18fcc480 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_sh_mask.h
@@ -31641,6 +31641,11 @@
 #define GDC0_BIF_RLC_DOORBELL_RANGE__SIZE__SHIFT                                                              0x10
 #define GDC0_BIF_RLC_DOORBELL_RANGE__OFFSET_MASK                                                              0x00000FFCL
 #define GDC0_BIF_RLC_DOORBELL_RANGE__SIZE_MASK                                                                0x001F0000L
+//GDC0_BIF_CSDMA_DOORBELL_RANGE
+#define GDC0_BIF_CSDMA_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
+#define GDC0_BIF_CSDMA_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
+#define GDC0_BIF_CSDMA_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
+#define GDC0_BIF_CSDMA_DOORBELL_RANGE__SIZE_MASK                                                              0x00FF0000L
 //GDC0_ATDMA_MISC_CNTL
 #define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT                                                             0x0
 #define GDC0_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN__SHIFT                                 0x1
@@ -119765,6 +119770,11 @@
 #define GDC1_BIF_SDMA5_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
 #define GDC1_BIF_SDMA5_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
 #define GDC1_BIF_SDMA5_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
+//GDC1_BIF_CSDMA_DOORBELL_RANGE
+#define GDC1_BIF_CSDMA_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
+#define GDC1_BIF_CSDMA_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
+#define GDC1_BIF_CSDMA_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
+#define GDC1_BIF_CSDMA_DOORBELL_RANGE__SIZE_MASK                                                              0x00FF0000L
 //GDC1_ATDMA_MISC_CNTL
 #define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT                                                             0x0
 #define GDC1_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN__SHIFT                                 0x1
-- 
GitLab


From 72b5f23ccb0aee46029476cbb072074384aef591 Mon Sep 17 00:00:00 2001
From: Xiaojian Du <Xiaojian.Du@amd.com>
Date: Fri, 20 May 2022 21:33:29 +0800
Subject: [PATCH 0183/1731] drm/amdgpu: fix sdma doorbell issue on SDMA v6.0
 and NBIO v7.7

This patch will fix sdma doorbell issue on SDMA v6.0 and NBIO v7.7.0.
NBIO v7.7.0 uses a new reg function -- Common SDMA to allow a common
doorbell range for all SDMA queues, this is different to the old
NBIO version. This patch will add configuration for CSDMA and enable
SDMA doorbell function.

Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
index cdc0c97798483..e786b825cea9a 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
@@ -58,10 +58,16 @@ static void nbio_v7_7_sdma_doorbell_range(struct amdgpu_device *adev, int instan
 					  bool use_doorbell, int doorbell_index,
 					  int doorbell_size)
 {
-	u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE);
+	u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_CSDMA_DOORBELL_RANGE);
 	u32 doorbell_range = RREG32_PCIE_PORT(reg);
 
 	if (use_doorbell) {
+		doorbell_range = REG_SET_FIELD(doorbell_range,
+					       GDC0_BIF_CSDMA_DOORBELL_RANGE,
+					       OFFSET, doorbell_index);
+		doorbell_range = REG_SET_FIELD(doorbell_range,
+					       GDC0_BIF_CSDMA_DOORBELL_RANGE,
+					       SIZE, doorbell_size);
 		doorbell_range = REG_SET_FIELD(doorbell_range,
 					       GDC0_BIF_SDMA0_DOORBELL_RANGE,
 					       OFFSET, doorbell_index);
-- 
GitLab


From 3ccb9ea9976022034d8fffd8d929d6e70a24e0c6 Mon Sep 17 00:00:00 2001
From: Dillon Varone <dillon.varone@amd.com>
Date: Thu, 14 Apr 2022 17:03:28 -0400
Subject: [PATCH 0184/1731] drm/amd/display: Add additional guard for FCLK
 pstate message for DCN321

Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c   | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 93fbecbc80650..9d2d2cda5543b 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -346,8 +346,8 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 					clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
 	}
 
-	if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) &&
-			clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21) {
+	if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 &&
+			should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) {
 		clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
 
 		/* To disable FCLK P-state switching, send FCLK_PSTATE_NOTSUPPORTED message to PMFW */
@@ -368,7 +368,8 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 			(update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))
 		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
 
-	if (clk_mgr_base->clks.fclk_p_state_change_support &&
+	if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 &&
+			clk_mgr_base->clks.fclk_p_state_change_support &&
 			(update_uclk || !clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
 		/* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
 		dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED);
-- 
GitLab


From 2388a778bdacad0c936dbb01048362864847f8ad Mon Sep 17 00:00:00 2001
From: Fangzhi Zuo <Jerry.Zuo@amd.com>
Date: Tue, 19 Apr 2022 15:49:48 -0400
Subject: [PATCH 0185/1731] drm/amd/display: Halve DTB Clock Value for DCN32

VBIOS default clock value was halved, so the hardcoded dtb value should be
halved as well.

dtb clock should come from SMU eventually, but now dtb clock switching is not
fully supported yet in SMU.

Halve the dtb hardcoded value for now to have UHBR10 light up. Will rely on
SMU for dtb clock switching once available. The w/a is for DCN32 only, DCN321
should adopt the original value.

Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 9d2d2cda5543b..774de29fa5324 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -599,7 +599,7 @@ void dcn32_clk_mgr_construct(
 	clk_mgr->dfs_ref_freq_khz = 100000;
 
 	clk_mgr->base.dprefclk_khz = 717000; /* Changed as per DCN3.2_clock_frequency doc */
-	clk_mgr->dccg->ref_dtbclk_khz = 477800;
+	clk_mgr->dccg->ref_dtbclk_khz = 268750;
 
 	/* integer part is now VCO frequency in kHz */
 	clk_mgr->base.dentist_vco_freq_khz = 4300000;//dcn32_get_vco_frequency_from_reg(clk_mgr);
-- 
GitLab


From 9d6b2041761ff6d5a33941919c8b5a805ecbed6c Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Tue, 24 May 2022 10:02:16 -0400
Subject: [PATCH 0186/1731] drm/amdgpu: convert
 sienna_cichlid_populate_umd_state_clk() to use IP version

Rather than asic type.

Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c    | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 6b452e3f5ee38..1c5ce9c5cba9e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1464,19 +1464,19 @@ static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
 	pstate_table->socclk_pstate.min = soc_table->min;
 	pstate_table->socclk_pstate.peak = soc_table->max;
 
-	switch (adev->asic_type) {
-	case CHIP_SIENNA_CICHLID:
-	case CHIP_NAVY_FLOUNDER:
+	switch (adev->ip_versions[MP1_HWIP][0]) {
+	case IP_VERSION(11, 0, 7):
+	case IP_VERSION(11, 0, 11):
 		pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
 		pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
 		pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
 		break;
-	case CHIP_DIMGREY_CAVEFISH:
+	case IP_VERSION(11, 0, 12):
 		pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;
 		pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;
 		pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;
 		break;
-	case CHIP_BEIGE_GOBY:
+	case IP_VERSION(11, 0, 13):
 		pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;
 		pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;
 		pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;
-- 
GitLab


From 1d6c363330834fa534c1c7ee01620ff134aade1f Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Tue, 24 May 2022 09:55:51 -0400
Subject: [PATCH 0187/1731] drm/amdgpu: simplify the logic in
 amdgpu_device_parse_gpu_info_fw()

Drop all of the extra cases in the default case.

Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29 ----------------------
 1 file changed, 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e9155dc1c30c9..00ed666811b13 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1942,35 +1942,6 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
 	}
 
 	switch (adev->asic_type) {
-#ifdef CONFIG_DRM_AMDGPU_SI
-	case CHIP_VERDE:
-	case CHIP_TAHITI:
-	case CHIP_PITCAIRN:
-	case CHIP_OLAND:
-	case CHIP_HAINAN:
-#endif
-#ifdef CONFIG_DRM_AMDGPU_CIK
-	case CHIP_BONAIRE:
-	case CHIP_HAWAII:
-	case CHIP_KAVERI:
-	case CHIP_KABINI:
-	case CHIP_MULLINS:
-#endif
-	case CHIP_TOPAZ:
-	case CHIP_TONGA:
-	case CHIP_FIJI:
-	case CHIP_POLARIS10:
-	case CHIP_POLARIS11:
-	case CHIP_POLARIS12:
-	case CHIP_VEGAM:
-	case CHIP_CARRIZO:
-	case CHIP_STONEY:
-	case CHIP_VEGA20:
-	case CHIP_ALDEBARAN:
-	case CHIP_SIENNA_CICHLID:
-	case CHIP_NAVY_FLOUNDER:
-	case CHIP_DIMGREY_CAVEFISH:
-	case CHIP_BEIGE_GOBY:
 	default:
 		return 0;
 	case CHIP_VEGA10:
-- 
GitLab


From be77243327d962a87bcf03615bae12d73efb9b7c Mon Sep 17 00:00:00 2001
From: Dillon Varone <dillon.varone@amd.com>
Date: Mon, 18 Apr 2022 14:39:20 -0400
Subject: [PATCH 0188/1731] drm/amd/display: set dram speed for all states

[WHY?]
If higher states have memory speed set to 0 MT/s currently they do not get set
to the highest value which can cause validation failures.

[HOW?]
Set unpopulated higher states to max value.

Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c   | 6 +++++-
 drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 6 +++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 7772beadd0006..3f93b1f2d872b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -3549,7 +3549,6 @@ static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw
 			dcn3_2_soc.clock_limits[i].state = i;
 			dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
 			dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
-			dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
 
 			/* Fill all states with max values of all these clocks */
 			dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
@@ -3568,6 +3567,11 @@ static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw
 			else
 				dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
 
+			if (!dram_speed_mts[i] && i > 0)
+				dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts;
+			else
+				dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
+
 			/* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */
 			/* PHYCLK_D18, PHYCLK_D32 */
 			dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index 0b420466b6dd7..27d3aa7d751f2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -1899,7 +1899,6 @@ static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b
 			dcn3_21_soc.clock_limits[i].state = i;
 			dcn3_21_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
 			dcn3_21_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
-			dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
 
 			/* Fill all states with max values of all these clocks */
 			dcn3_21_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
@@ -1918,6 +1917,11 @@ static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b
 			else
 				dcn3_21_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
 
+			if (!dram_speed_mts[i] && i > 0)
+				dcn3_21_soc.clock_limits[i].dram_speed_mts = dcn3_21_soc.clock_limits[i-1].dram_speed_mts;
+			else
+				dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
+
 			/* These clocks cannot come from bw_params, always fill from dcn3_21_soc[0] */
 			/* PHYCLK_D18, PHYCLK_D32 */
 			dcn3_21_soc.clock_limits[i].phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz;
-- 
GitLab


From ac1ac694f7173a0fbb0b60ab0f26226dd334479a Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Tue, 24 May 2022 10:27:33 -0400
Subject: [PATCH 0189/1731] drm/amdgpu: convert
 nbio_v2_3_clear_doorbell_interrupt() to IP version

Check IP version rather than asic type.

Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index 6cd1fb2eb9131..34c610b9157d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -547,7 +547,7 @@ static void nbio_v2_3_clear_doorbell_interrupt(struct amdgpu_device *adev)
 {
 	uint32_t reg, reg_data;
 
-	if (adev->asic_type != CHIP_SIENNA_CICHLID)
+	if (adev->ip_versions[NBIO_HWIP][0] != IP_VERSION(3, 3, 0))
 		return;
 
 	reg = RREG32_SOC15(NBIO, 0, mmBIF_RB_CNTL);
-- 
GitLab


From 2cfe34e18970d26bff73c63f16c76dae22138d19 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Thu, 26 May 2022 12:48:51 -0400
Subject: [PATCH 0190/1731] drm/amdgpu/gmc11: enable AGP aperture
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Enable the AGP aperture on chips with GMC v11.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c  | 7 ++++---
 drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c    | 1 +
 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c   | 6 +++---
 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c | 6 +++---
 4 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
index 5eccaa2c7ca0e..f99d7641bb217 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
@@ -154,10 +154,11 @@ static void gfxhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev)
 {
 	uint64_t value;
 
-	/* Disable AGP. */
+	/* Program the AGP BAR */
 	WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0);
-	WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, 0);
-	WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, 0x00FFFFFF);
+	WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
+	WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
+
 
 	/* Program the system aperture low logical page number. */
 	WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 9c225553f5b53..454a25cc00461 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -611,6 +611,7 @@ static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev,
 
 	amdgpu_gmc_vram_location(adev, &adev->gmc, base);
 	amdgpu_gmc_gart_location(adev, mc);
+	amdgpu_gmc_agp_location(adev, mc);
 
 	/* base offset of vram pages */
 	adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
index bc11b2de37aeb..4926fa82c1c4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
@@ -169,10 +169,10 @@ static void mmhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev)
 	uint64_t value;
 	uint32_t tmp;
 
-	/* Disable AGP. */
+	/* Program the AGP BAR */
 	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
-	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0);
-	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FFFFFF);
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 
 	if (!amdgpu_sriov_vf(adev)) {
 		/*
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
index 770be0a8f7ce7..5e5b884d83573 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
@@ -162,10 +162,10 @@ static void mmhub_v3_0_2_init_system_aperture_regs(struct amdgpu_device *adev)
 	uint64_t value;
 	uint32_t tmp;
 
-	/* Disable AGP. */
+	/* Program the AGP BAR */
 	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
-	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0);
-	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FFFFFF);
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 
 	if (!amdgpu_sriov_vf(adev)) {
 		/*
-- 
GitLab


From 2267a195e28cc438cb45936c4562f958502d4038 Mon Sep 17 00:00:00 2001
From: Dillon Varone <dillon.varone@amd.com>
Date: Wed, 13 Apr 2022 17:54:19 -0400
Subject: [PATCH 0191/1731] drm/amd/display: Disable DTB Ref Clock Switching in
 dcn32

[How & Why]
To be enabled once PMFW supports it.

Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 774de29fa5324..f147c65137c6c 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -607,6 +607,10 @@ void dcn32_clk_mgr_construct(
 	if (clk_mgr->base.dentist_vco_freq_khz == 0)
 		clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */
 
+	if (clk_mgr->dccg->ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) {
+		clk_mgr->dccg->ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk;
+	}
+
 	if (clk_mgr->base.boot_snapshot.dprefclk != 0) {
 		//ASSERT(clk_mgr->base.dprefclk_khz == clk_mgr->base.boot_snapshot.dprefclk);
 		//clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;
-- 
GitLab


From da1db031cd30fefc99d1c82211d3c24b73857bbe Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Thu, 26 May 2022 11:55:36 -0400
Subject: [PATCH 0192/1731] drm/amdgpu/swsmu: add SMU mailbox registers in SMU
 context

So we can eventaully use them in the common smu code for
accessing the SMU mailboxes without needing a lot of
per asic logic in the common code.

Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h  |  4 ++++
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h   |  2 ++
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h   |  2 ++
 .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c  |  1 +
 .../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c    |  1 +
 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c    |  1 +
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c    |  1 +
 drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c |  9 +++++++++
 .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c   |  1 +
 .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c    | 14 ++++++++++++++
 .../gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c |  1 +
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 18 ++++++++++++++++++
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c   |  1 +
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c   | 14 ++++++++++++++
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c   | 14 ++++++++++++++
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c   |  1 +
 .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c   |  1 +
 17 files changed, 86 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index c3d5a616e572e..6d51e4340aadc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -563,6 +563,10 @@ struct smu_context
 	struct stb_context stb_context;
 
 	struct firmware pptable_firmware;
+
+	u32 param_reg;
+	u32 msg_reg;
+	u32 resp_reg;
 };
 
 struct i2c_adapter;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
index acb3be2920968..a9215494dcddb 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
@@ -316,5 +316,7 @@ int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable);
 
 int smu_v11_0_restore_user_od_settings(struct smu_context *smu);
 
+void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu);
+
 #endif
 #endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index 08270d8528d9b..fe9c47c87abc9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -300,5 +300,7 @@ int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
 				uint32_t size);
 
 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu);
+
+void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu);
 #endif
 #endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 201563072189d..bfabcd3c45aa2 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -2509,4 +2509,5 @@ void arcturus_set_ppt_funcs(struct smu_context *smu)
 	smu->table_map = arcturus_table_map;
 	smu->pwr_src_map = arcturus_pwr_src_map;
 	smu->workload_map = arcturus_workload_map;
+	smu_v11_0_set_smu_mailbox_registers(smu);
 }
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
index f1a4a720d4261..ca4d97b7f576c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
@@ -591,4 +591,5 @@ void cyan_skillfish_set_ppt_funcs(struct smu_context *smu)
 	smu->message_map = cyan_skillfish_message_map;
 	smu->table_map = cyan_skillfish_table_map;
 	smu->is_apu = true;
+	smu_v11_0_set_smu_mailbox_registers(smu);
 }
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 5f22fc3430f43..0bcd4fe0ef177 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -3580,4 +3580,5 @@ void navi10_set_ppt_funcs(struct smu_context *smu)
 	smu->table_map = navi10_table_map;
 	smu->pwr_src_map = navi10_pwr_src_map;
 	smu->workload_map = navi10_workload_map;
+	smu_v11_0_set_smu_mailbox_registers(smu);
 }
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 1c5ce9c5cba9e..b71860e5324af 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -4357,4 +4357,5 @@ void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
 	smu->table_map = sienna_cichlid_table_map;
 	smu->pwr_src_map = sienna_cichlid_pwr_src_map;
 	smu->workload_map = sienna_cichlid_workload_map;
+	smu_v11_0_set_smu_mailbox_registers(smu);
 }
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index b87f550af26ba..974b8fe1dbb6b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -2197,3 +2197,12 @@ int smu_v11_0_restore_user_od_settings(struct smu_context *smu)
 
 	return ret;
 }
+
+void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu)
+{
+	struct amdgpu_device *adev = smu->adev;
+
+	smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
+	smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
+	smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 5551e1426ef59..e2d8ac90cf365 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -2213,4 +2213,5 @@ void vangogh_set_ppt_funcs(struct smu_context *smu)
 	smu->table_map = vangogh_table_map;
 	smu->workload_map = vangogh_workload_map;
 	smu->is_apu = true;
+	smu_v11_0_set_smu_mailbox_registers(smu);
 }
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index 012e3bd99cc23..85e22210963fc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -41,6 +41,15 @@
 #undef pr_info
 #undef pr_debug
 
+#define mmMP1_SMN_C2PMSG_66                                                                            0x0282
+#define mmMP1_SMN_C2PMSG_66_BASE_IDX                                                                   0
+
+#define mmMP1_SMN_C2PMSG_82                                                                            0x0292
+#define mmMP1_SMN_C2PMSG_82_BASE_IDX                                                                   0
+
+#define mmMP1_SMN_C2PMSG_90                                                                            0x029a
+#define mmMP1_SMN_C2PMSG_90_BASE_IDX                                                                   0
+
 static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = {
 	MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                  1),
 	MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,                1),
@@ -1447,6 +1456,8 @@ static const struct pptable_funcs renoir_ppt_funcs = {
 
 void renoir_set_ppt_funcs(struct smu_context *smu)
 {
+	struct amdgpu_device *adev = smu->adev;
+
 	smu->ppt_funcs = &renoir_ppt_funcs;
 	smu->message_map = renoir_message_map;
 	smu->clock_map = renoir_clk_map;
@@ -1454,4 +1465,7 @@ void renoir_set_ppt_funcs(struct smu_context *smu)
 	smu->workload_map = renoir_workload_map;
 	smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION;
 	smu->is_apu = true;
+	smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
+	smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
+	smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
 }
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index bb3c238213239..1133edd34e4d0 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -2147,4 +2147,5 @@ void aldebaran_set_ppt_funcs(struct smu_context *smu)
 	smu->clock_map = aldebaran_clk_map;
 	smu->feature_map = aldebaran_feature_mask_map;
 	smu->table_map = aldebaran_table_map;
+	smu_v13_0_set_smu_mailbox_registers(smu);
 }
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index a56dddc9fb884..6db10e49db7e9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -60,6 +60,15 @@ MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
 MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
 MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
 
+#define mmMP1_SMN_C2PMSG_66                                                                            0x0282
+#define mmMP1_SMN_C2PMSG_66_BASE_IDX                                                                   0
+
+#define mmMP1_SMN_C2PMSG_82                                                                            0x0292
+#define mmMP1_SMN_C2PMSG_82_BASE_IDX                                                                   0
+
+#define mmMP1_SMN_C2PMSG_90                                                                            0x029a
+#define mmMP1_SMN_C2PMSG_90_BASE_IDX                                                                   0
+
 #define SMU13_VOLTAGE_SCALE 4
 
 #define LINK_WIDTH_MAX				6
@@ -2396,3 +2405,12 @@ int smu_v13_0_set_default_dpm_tables(struct smu_context *smu)
 	return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
 				    smu_table->clocks_table, false);
 }
+
+void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu)
+{
+	struct amdgpu_device *adev = smu->adev;
+
+	smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
+	smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
+	smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 5c74a72577c68..418480e0c0777 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -1651,4 +1651,5 @@ void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
 	smu->table_map = smu_v13_0_0_table_map;
 	smu->pwr_src_map = smu_v13_0_0_pwr_src_map;
 	smu->workload_map = smu_v13_0_0_workload_map;
+	smu_v13_0_set_smu_mailbox_registers(smu);
 }
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
index 29fcce04a91aa..196670345552b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -43,6 +43,15 @@
 #undef pr_info
 #undef pr_debug
 
+#define mmMP1_SMN_C2PMSG_66			0x0282
+#define mmMP1_SMN_C2PMSG_66_BASE_IDX            1
+
+#define mmMP1_SMN_C2PMSG_82			0x0292
+#define mmMP1_SMN_C2PMSG_82_BASE_IDX            1
+
+#define mmMP1_SMN_C2PMSG_90			0x029a
+#define mmMP1_SMN_C2PMSG_90_BASE_IDX		1
+
 #define FEATURE_MASK(feature) (1ULL << feature)
 
 #define SMC_DPM_FEATURE ( \
@@ -1035,9 +1044,14 @@ static const struct pptable_funcs smu_v13_0_4_ppt_funcs = {
 
 void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu)
 {
+	struct amdgpu_device *adev = smu->adev;
+
 	smu->ppt_funcs = &smu_v13_0_4_ppt_funcs;
 	smu->message_map = smu_v13_0_4_message_map;
 	smu->feature_map = smu_v13_0_4_feature_mask_map;
 	smu->table_map = smu_v13_0_4_table_map;
 	smu->is_apu = true;
+	smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
+	smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
+	smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
 }
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
index b81711c4ff335..47360ef5c1758 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
@@ -42,6 +42,15 @@
 #undef pr_info
 #undef pr_debug
 
+#define mmMP1_C2PMSG_2                                                                            (0xbee142 + 0xb00000 / 4)
+#define mmMP1_C2PMSG_2_BASE_IDX                                                                   0
+
+#define mmMP1_C2PMSG_34                                                                           (0xbee262 + 0xb00000 / 4)
+#define mmMP1_C2PMSG_34_BASE_IDX                                                                   0
+
+#define mmMP1_C2PMSG_33                                                                                (0xbee261 + 0xb00000 / 4)
+#define mmMP1_C2PMSG_33_BASE_IDX                                                                   0
+
 #define FEATURE_MASK(feature) (1ULL << feature)
 #define SMC_DPM_FEATURE ( \
 	FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
@@ -1049,9 +1058,14 @@ static const struct pptable_funcs smu_v13_0_5_ppt_funcs = {
 
 void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu)
 {
+	struct amdgpu_device *adev = smu->adev;
+
 	smu->ppt_funcs = &smu_v13_0_5_ppt_funcs;
 	smu->message_map = smu_v13_0_5_message_map;
 	smu->feature_map = smu_v13_0_5_feature_mask_map;
 	smu->table_map = smu_v13_0_5_table_map;
 	smu->is_apu = true;
+	smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_34);
+	smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_2);
+	smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_33);
 }
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 4e1861fb2c6a4..bdea7bca3805c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1594,4 +1594,5 @@ void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
 	smu->table_map = smu_v13_0_7_table_map;
 	smu->pwr_src_map = smu_v13_0_7_pwr_src_map;
 	smu->workload_map = smu_v13_0_7_workload_map;
+	smu_v13_0_set_smu_mailbox_registers(smu);
 }
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index feff4f8c927cc..70cbc46341a39 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -1203,4 +1203,5 @@ void yellow_carp_set_ppt_funcs(struct smu_context *smu)
 	smu->feature_map = yellow_carp_feature_mask_map;
 	smu->table_map = yellow_carp_table_map;
 	smu->is_apu = true;
+	smu_v13_0_set_smu_mailbox_registers(smu);
 }
-- 
GitLab


From 3378aed7e2ec7212889116335a2120a6e35c80ce Mon Sep 17 00:00:00 2001
From: Dillon Varone <dillon.varone@amd.com>
Date: Mon, 11 Apr 2022 10:29:57 -0400
Subject: [PATCH 0193/1731] drm/amd/display: change dsc image width cap for
 dcn32 and dcn321

Set appropriate caps for DCN3.2.x.

Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c   | 3 +++
 drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 3f93b1f2d872b..f2850071478c1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -1695,6 +1695,9 @@ static struct display_stream_compressor *dcn32_dsc_create(
 	}
 
 	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
+
+	dsc->max_image_width = 6016;
+
 	return &dsc->base;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index 27d3aa7d751f2..376dd586b6434 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -1679,6 +1679,9 @@ static struct display_stream_compressor *dcn321_dsc_create(
 	}
 
 	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
+
+	dsc->max_image_width = 6016;
+
 	return &dsc->base;
 }
 
-- 
GitLab


From 7a09f61f8e842dd027afa1ce8be8bd86062c8a7b Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Thu, 26 May 2022 12:04:38 -0400
Subject: [PATCH 0194/1731] drm/amdgpu/swsmu: use new register offsets for
 smu_cmn.c

Use the per asic offsets so the we don't have to have
asic specific logic in the common code.

Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 77 +++-----------------------
 1 file changed, 7 insertions(+), 70 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 5215ead4978fd..53cd62ccab5dc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -37,40 +37,6 @@
 #undef pr_info
 #undef pr_debug
 
-/*
- * Although these are defined in each ASIC's specific header file.
- * They share the same definitions and values. That makes common
- * APIs for SMC messages issuing for all ASICs possible.
- */
-#define mmMP1_SMN_C2PMSG_66                                                                            0x0282
-#define mmMP1_SMN_C2PMSG_66_BASE_IDX                                                                   0
-
-#define mmMP1_SMN_C2PMSG_82                                                                            0x0292
-#define mmMP1_SMN_C2PMSG_82_BASE_IDX                                                                   0
-
-#define mmMP1_SMN_C2PMSG_90                                                                            0x029a
-#define mmMP1_SMN_C2PMSG_90_BASE_IDX                                                                   0
-
-#define mmMP1_SMN_C2PMSG_66_V13_0_4			0x0282
-#define mmMP1_SMN_C2PMSG_66_V13_0_4_BASE_IDX            1
-
-#define mmMP1_SMN_C2PMSG_82_V13_0_4			0x0292
-#define mmMP1_SMN_C2PMSG_82_V13_0_4_BASE_IDX            1
-
-#define mmMP1_SMN_C2PMSG_90_V13_0_4			0x029a
-#define mmMP1_SMN_C2PMSG_90_V13_0_4_BASE_IDX		1
-
-/* SMU 13.0.5 has its specific mailbox messaging registers */
-
-#define mmMP1_C2PMSG_2                                                                            (0xbee142 + 0xb00000 / 4)
-#define mmMP1_C2PMSG_2_BASE_IDX                                                                   0
-
-#define mmMP1_C2PMSG_34                                                                           (0xbee262 + 0xb00000 / 4)
-#define mmMP1_C2PMSG_34_BASE_IDX                                                                   0
-
-#define mmMP1_C2PMSG_33                                                                                (0xbee261 + 0xb00000 / 4)
-#define mmMP1_C2PMSG_33_BASE_IDX                                                                   0
-
 #define MP1_C2PMSG_90__CONTENT_MASK                                                                    0xFFFFFFFFL
 
 #undef __SMU_DUMMY_MAP
@@ -99,12 +65,7 @@ static void smu_cmn_read_arg(struct smu_context *smu,
 {
 	struct amdgpu_device *adev = smu->adev;
 
-	if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5))
-		*arg = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34);
-	else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4))
-		*arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4);
-	else
-		*arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
+	*arg = RREG32(smu->param_reg);
 }
 
 /* Redefine the SMU error codes here.
@@ -150,12 +111,7 @@ static u32 __smu_cmn_poll_stat(struct smu_context *smu)
 	u32 reg;
 
 	for ( ; timeout > 0; timeout--) {
-		if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5))
-			reg = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_33);
-		else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4))
-			reg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90_V13_0_4);
-		else
-			reg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
+		reg = RREG32(smu->resp_reg);
 		if ((reg & MP1_C2PMSG_90__CONTENT_MASK) != 0)
 			break;
 
@@ -177,16 +133,8 @@ static void __smu_cmn_reg_print_error(struct smu_context *smu,
 
 	switch (reg_c2pmsg_90) {
 	case SMU_RESP_NONE: {
-		if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) {
-			msg_idx = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2);
-			prm     = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34);
-		} else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) {
-			msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66_V13_0_4);
-			prm     = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4);
-		} else {
-			msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66);
-			prm     = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
-		}
+		msg_idx = RREG32(smu->msg_reg);
+		prm     = RREG32(smu->param_reg);
 		dev_err_ratelimited(adev->dev,
 				    "SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x%08X SMN_C2PMSG_82:0x%08X",
 				    msg_idx, prm);
@@ -280,20 +228,9 @@ static void __smu_cmn_send_msg(struct smu_context *smu,
 {
 	struct amdgpu_device *adev = smu->adev;
 
-	if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) {
-		WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_33, 0);
-		WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34, param);
-		WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2, msg);
-	} else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) {
-		WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90_V13_0_4, 0);
-		WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4, param);
-		WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66_V13_0_4, msg);
-	} else {
-		WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
-		WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
-		WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
-	}
-
+	WREG32(smu->resp_reg, 0);
+	WREG32(smu->param_reg, param);
+	WREG32(smu->msg_reg, msg);
 }
 
 /**
-- 
GitLab


From 4c1b3d0803aef6d39913f1e9d2cfe2c1ccce18e8 Mon Sep 17 00:00:00 2001
From: Dan Carpenter <dan.carpenter@oracle.com>
Date: Mon, 30 May 2022 14:42:25 +0300
Subject: [PATCH 0195/1731] drm/amdgpu: delete duplicate condition in
 gfx_v11_0_soft_reset()

We know that "grbm_soft_reset" is true because we're already inside an
if (grbm_soft_reset) condition.  No need to test again.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 24 +++++++++++-------------
 1 file changed, 11 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 5f20b41bcb93a..ca37289c644ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4780,19 +4780,17 @@ static int gfx_v11_0_soft_reset(void *handle)
 		/* Disable MEC parsing/prefetching */
 		gfx_v11_0_cp_compute_enable(adev, false);
 
-		if (grbm_soft_reset) {
-			tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
-			tmp |= grbm_soft_reset;
-			dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
-			WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
-			tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
-
-			udelay(50);
-
-			tmp &= ~grbm_soft_reset;
-			WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
-			tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
-		}
+		tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
+		tmp |= grbm_soft_reset;
+		dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
+		WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
+		tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
+
+		udelay(50);
+
+		tmp &= ~grbm_soft_reset;
+		WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
+		tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
 
 		/* Wait a little for things to settle down */
 		udelay(50);
-- 
GitLab


From e87b92c6af537843daf7da9235e622988bae7eae Mon Sep 17 00:00:00 2001
From: Samson Tam <Samson.Tam@amd.com>
Date: Thu, 7 Apr 2022 12:04:42 -0400
Subject: [PATCH 0196/1731] drm/amd/display: do not override CURSOR_REQ_MODE
 when SubVP is not enabled

[Why]
HUBP_UNBOUNDED_REQ_MODE and CURSOR_REQ_MODE are normally set together.
In hubp32_prepare_subvp_buffering() call, CURSOR_REQ_MODE is set based on
whether SubVP is enabled or not.  For non MPO case, both REQ_MODE
registers are set to 1.  But since SubVP is not enabled, then
CURSOR_REQ_MODE is set to 0, overriding the previous value.

[How]
Do not set CURSOR_REQ_MODE to 0 if SubVP is not enabled.  This
will allow CURSOR_REQ_MODE to stay as 1 in the non MPO case.
Add note to follow up and check case for single pipe MPO and
SubVP enabled as this would cause both REQ_MODE registers to be
set to 0 but SubVP enabled would override CURSOR_REQ_MODE to 1.

Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 40afd33ffec65..8eed05aad54cd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -555,10 +555,13 @@ void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context)
 		struct hubp *hubp = pipe->plane_res.hubp;
 
 		if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) {
+			/* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases
+			 *      - need to investigate single pipe MPO + SubVP case to
+			 *        see if CURSOR_REQ_MODE will be back to 1 for SubVP
+			 *        when it should be 0 for MPO
+			 */
 			if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
 				hubp->funcs->hubp_prepare_subvp_buffering(hubp, true);
-			} else {
-				hubp->funcs->hubp_prepare_subvp_buffering(hubp, false);
 			}
 		}
 	}
-- 
GitLab


From b5a0168e1406176cf98487833b7468a1ea5872d3 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Tue, 24 May 2022 10:11:33 -0400
Subject: [PATCH 0197/1731] drm/amdgpu: fix up comment in
 amdgpu_device_asic_has_dc_support()

LVDS support was implemented in DC a while ago.  Just DAC
support is left to do.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 00ed666811b13..4831148342b75 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3287,7 +3287,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
 	case CHIP_MULLINS:
 		/*
 		 * We have systems in the wild with these ASICs that require
-		 * LVDS and VGA support which is not supported with DC.
+		 * VGA support which is not supported with DC.
 		 *
 		 * Fallback to the non-DC driver here by default so as not to
 		 * cause regressions.
-- 
GitLab


From 452e9214431f1f6385bb20fdf6e1b5692947071f Mon Sep 17 00:00:00 2001
From: Alvin Lee <Alvin.Lee2@amd.com>
Date: Tue, 5 Apr 2022 14:46:30 -0400
Subject: [PATCH 0198/1731] drm/amd/display: Remove W/A for ODM memory pins

[Description]
By default we can now set
ODM_MEM_VBLANK_PWR_MODE=1

Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index f2850071478c1..b492eb424d193 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -997,7 +997,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 			.dscl = false,
 			.cm = false,
 			.mpc = false,
-			.optc = false,
+			.optc = true,
 		}
 	},
 	.use_max_lb = true,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index 376dd586b6434..780409eb0e981 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -994,7 +994,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 			.dscl = false,
 			.cm = false,
 			.mpc = false,
-			.optc = false,
+			.optc = true,
 		}
 	},
 	.use_max_lb = true,
-- 
GitLab


From 49f594995a9255ff734f79c1fc22bd06119ebe8f Mon Sep 17 00:00:00 2001
From: Jun Lei <Jun.Lei@amd.com>
Date: Sun, 20 Feb 2022 13:58:51 -0500
Subject: [PATCH 0199/1731] drm/amd/display: add new pixel rate programming

[why]
New dividers in DCCG need to be programmed depending
on encoder/stream type since pixels per clock in
OTG/DIO is different

DIO also needs additional programming depending on
pixels per clock

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 .../display/dc/dcn10/dcn10_stream_encoder.h   |  1 +
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 14 ++++
 .../gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c |  1 +
 .../dc/dcn32/dcn32_dio_stream_encoder.h       |  3 +-
 .../drm/amd/display/dc/dcn32/dcn32_hwseq.c    | 72 +++++++++++++++++--
 .../drm/amd/display/dc/dcn32/dcn32_hwseq.h    |  2 +
 .../gpu/drm/amd/display/dc/dcn32/dcn32_init.c |  1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h  |  3 +-
 .../amd/display/dc/inc/hw/stream_encoder.h    |  3 +
 .../amd/display/dc/inc/hw_sequencer_private.h |  3 +
 10 files changed, 95 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index dd9bb86da4de1..f8d22ba6a6e40 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -576,6 +576,7 @@ struct dcn10_stream_enc_registers {
 	type DP_SEC_GSP11_LINE_NUM
 
 #define SE_REG_FIELD_LIST_DCN3_2(type) \
+	type DIG_FIFO_OUTPUT_PIXEL_MODE;\
 	type DIG_SYMCLK_FE_ON;\
 	type DIG_FIFO_READ_START_LEVEL;\
 	type DIG_FIFO_ENABLE;\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index d00a27893ab02..aed8ab06b41d3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -661,7 +661,17 @@ enum dc_status dcn20_enable_stream_timing(
 	struct mpc_dwb_flow_control flow_control;
 	struct mpc *mpc = dc->res_pool->mpc;
 	bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing));
+	unsigned int k1_div = PIXEL_RATE_DIV_NA;
+	unsigned int k2_div = PIXEL_RATE_DIV_NA;
 
+	if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
+		hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
+
+		dc->res_pool->dccg->funcs->set_pixel_rate_div(
+			dc->res_pool->dccg,
+			pipe_ctx->stream_res.tg->inst,
+			k1_div, k2_div);
+	}
 	/* by upper caller loop, pipe0 is parent pipe and be called first.
 	 * back end is set up by for pipe0. Other children pipe share back end
 	 * with pipe 0. No program is needed.
@@ -2485,6 +2495,10 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
 
 	tg->funcs->set_early_control(tg, early_control);
 
+	if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)
+		pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,
+			timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 ? 2 : 1);
+
 	/* enable audio only within mode set */
 	if (pipe_ctx->stream_res.audio != NULL) {
 		if (is_dp_128b_132b_signal(pipe_ctx))
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
index b78775e8c13cd..070be7e8ad0db 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
@@ -272,6 +272,7 @@ static const struct dccg_funcs dccg32_funcs = {
 	.set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,
 	.otg_add_pixel = dccg32_otg_add_pixel,
 	.otg_drop_pixel = dccg32_otg_drop_pixel,
+	.set_pixel_rate_div = dccg32_set_pixel_rate_div,
 };
 
 struct dccg *dccg32_create(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h
index 77da0a13525b9..042bc9aca944f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h
@@ -240,7 +240,8 @@
 	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, mask_sh),\
 	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, mask_sh),\
 	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET, mask_sh),\
-	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, mask_sh)
+	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, mask_sh)
 
 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 #define SE_COMMON_MASK_SH_LIST_DCN32(mask_sh)\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 8eed05aad54cd..5994edc3dd0ce 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -47,6 +47,7 @@
 #include "clk_mgr.h"
 #include "dsc.h"
 #include "dcn20/dcn20_optc.h"
+#include "dc_link_dp.h"
 
 #define DC_LOGGER_INIT(logger)
 
@@ -836,20 +837,44 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
 	}
 }
 
+/*
+* Given any pipe_ctx, return the total ODM combine factor, and optionally return
+* the OPPids which are used
+* */
+static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
+{
+	unsigned int opp_count = 1;
+	struct pipe_ctx *odm_pipe;
+
+	/* First get to the top pipe */
+	for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)
+		;
+
+	/* First pipe is always used */
+	if (opp_instances)
+		opp_instances[0] = odm_pipe->stream_res.opp->inst;
+
+	/* Find and count odm pipes, if any */
+	for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+		if (opp_instances)
+			opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;
+		opp_count++;
+	}
+
+	return opp_count;
+}
+
 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
 {
 	struct pipe_ctx *odm_pipe;
-	int opp_cnt = 1;
-	int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
+	int opp_cnt = 0;
+	int opp_inst[MAX_PIPES] = {0};
 	bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing));
 	struct mpc_dwb_flow_control flow_control;
 	struct mpc *mpc = dc->res_pool->mpc;
 	int i;
 
-	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
-		opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
-		opp_cnt++;
-	}
+	opp_cnt = get_odm_config(pipe_ctx, opp_inst);
 
 	if (opp_cnt > 1)
 		pipe_ctx->stream_res.tg->funcs->set_odm_combine(
@@ -892,3 +917,38 @@ void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *
 		update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
 }
 
+unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
+{
+	struct dc_stream_state *stream = pipe_ctx->stream;
+	unsigned int odm_combine_factor = 0;
+
+	odm_combine_factor = get_odm_config(pipe_ctx, NULL);
+
+	if (is_dp_128b_132b_signal(pipe_ctx)) {
+		*k2_div = PIXEL_RATE_DIV_BY_1;
+	} else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) {
+		*k1_div = PIXEL_RATE_DIV_BY_1;
+		if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
+			*k2_div = PIXEL_RATE_DIV_BY_2;
+		else
+			*k2_div = PIXEL_RATE_DIV_BY_4;
+	} else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
+		if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
+			*k1_div = PIXEL_RATE_DIV_BY_1;
+			*k2_div = PIXEL_RATE_DIV_BY_2;
+		} else if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) {
+			*k1_div = PIXEL_RATE_DIV_BY_2;
+			*k2_div = PIXEL_RATE_DIV_BY_2;
+		} else {
+			if (odm_combine_factor == 1)
+				*k2_div = PIXEL_RATE_DIV_BY_4;
+			else if (odm_combine_factor == 2)
+				*k2_div = PIXEL_RATE_DIV_BY_2;
+		}
+	}
+
+	if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
+		ASSERT(false);
+
+	return odm_combine_factor;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
index 737a7fac5cf99..2a5bdcf58bc6c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
@@ -61,4 +61,6 @@ void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context);
 
 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
 
+unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);
+
 #endif /* __DC_HWSS_DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
index d1e3db1bc4882..7f492734f881b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
@@ -141,6 +141,7 @@ static const struct hwseq_private_funcs dcn32_private_funcs = {
 	.program_mall_pipe_config = dcn32_program_mall_pipe_config,
 	.subvp_update_force_pstate = dcn32_subvp_update_force_pstate,
 	.update_mall_sel = dcn32_update_mall_sel,
+	.calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,
 };
 
 void dcn32_hw_sequencer_init_functions(struct dc *dc)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index 8b450a7274ae4..e0dd04626eb58 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -59,7 +59,8 @@ enum dentist_dispclk_change_mode {
 enum pixel_rate_div {
    PIXEL_RATE_DIV_BY_1 = 0,
    PIXEL_RATE_DIV_BY_2 = 1,
-   PIXEL_RATE_DIV_BY_4 = 3
+   PIXEL_RATE_DIV_BY_4 = 3,
+   PIXEL_RATE_DIV_NA = 0xF
 };
 
 struct dccg {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
index 36ec56524afde..e5fe0f6adc86c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
@@ -247,6 +247,9 @@ struct stream_encoder_funcs {
 
 	uint32_t (*get_fifo_cal_average_level)(
 		struct stream_encoder *enc);
+
+	void (*set_input_mode)(
+		struct stream_encoder *enc, unsigned int pix_per_container);
 };
 
 struct hpo_dp_stream_encoder_state {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
index fd869e93cf541..62a62e4fc4a8d 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
@@ -149,6 +149,9 @@ struct hwseq_private_funcs {
 	void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context);
 	void (*subvp_update_force_pstate)(struct dc *dc, struct dc_state *context);
 	void (*update_mall_sel)(struct dc *dc, struct dc_state *context);
+	unsigned int (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx,
+			unsigned int *k1_div,
+			unsigned int *k2_div);
 #endif
 };
 
-- 
GitLab


From 6ea843e01bce520cf5dea86bc30c5133e0d0822d Mon Sep 17 00:00:00 2001
From: Jingwen Zhu <Jingwen.Zhu@github.amd.com>
Date: Tue, 15 Mar 2022 13:15:27 +0800
Subject: [PATCH 0200/1731] drm/amd/display: set link fec status during init
 for DCN32

We can now enable FEC.

Signed-off-by: Jingwen Zhu <Jingwen.Zhu@github.amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 5994edc3dd0ce..04360553a43f3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -635,8 +635,12 @@ void dcn32_init_hw(struct dc *dc)
 
 		/* Check for enabled DIG to identify enabled display */
 		if (link->link_enc->funcs->is_dig_enabled &&
-			link->link_enc->funcs->is_dig_enabled(link->link_enc))
+			link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
 			link->link_status.link_active = true;
+			if (link->link_enc->funcs->fec_is_active &&
+					link->link_enc->funcs->fec_is_active(link->link_enc))
+				link->fec_state = dc_link_fec_enabled;
+		}
 	}
 
 	/* Power gate DSCs */
-- 
GitLab


From e127306d433ff99f29d1b083c6b3aa128bbd9c5e Mon Sep 17 00:00:00 2001
From: Jun Lei <Jun.Lei@amd.com>
Date: Sun, 20 Feb 2022 14:33:56 -0500
Subject: [PATCH 0201/1731] drm/amd/display: Introduce new update_clocks logic

[why]
DCN has sidebands to control some clocks, it is useful for clk_mgr to
always update the clocks it explicitly controls rather than skip them
because it enables more configurations to work without SMU

[how]
only skip handling clocks where SMU manages the frequency for clocks
with DENTIST sideband (DISP/DPP), only skip the voltage request when SMU
not available, but otherwise proceed normally

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c  | 125 ++++++++++--------
 1 file changed, 73 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index f147c65137c6c..9f35a74a1d7dd 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -310,69 +310,84 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 	if (display_count == 0)
 		enter_display_off = true;
 
-	if (enter_display_off == safe_to_lower)
-		dcn30_smu_set_num_of_displays(clk_mgr, display_count);
+	if (clk_mgr->smu_present) {
+		if (enter_display_off == safe_to_lower)
+			dcn30_smu_set_num_of_displays(clk_mgr, display_count);
 
-	if (dc->debug.force_min_dcfclk_mhz > 0)
-		new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
-				new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
+		if (dc->debug.force_min_dcfclk_mhz > 0)
+			new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
+					new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
 
-	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
-		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
-		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
-	}
+		if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
+			clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
+			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
+		}
 
-	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
-		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
-		dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
-	}
+		if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
+			clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
+			dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
+		}
 
-	if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
-		/* We don't actually care about socclk, don't notify SMU of hard min */
-		clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
+		if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
+			/* We don't actually care about socclk, don't notify SMU of hard min */
+			clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
 
-	clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
-	clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support;
+		clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
+		clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support;
+		clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways;
 
-	total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
-	p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
-	fclk_p_state_change_support = new_clocks->fclk_p_state_change_support || (total_plane_count == 0);
-	if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
-		clk_mgr_base->clks.p_state_change_support = p_state_change_support;
+		if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
+				clk_mgr_base->clks.num_ways < new_clocks->num_ways) {
+			clk_mgr_base->clks.num_ways = new_clocks->num_ways;
+			dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
+		}
 
-		/* to disable P-State switching, set UCLK min = max */
-		if (!clk_mgr_base->clks.p_state_change_support)
-			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
-					clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
-	}
+		total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
+		p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
+		fclk_p_state_change_support = new_clocks->fclk_p_state_change_support || (total_plane_count == 0);
+		if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
+			clk_mgr_base->clks.p_state_change_support = p_state_change_support;
+
+			/* to disable P-State switching, set UCLK min = max */
+			if (!clk_mgr_base->clks.p_state_change_support)
+				dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
+						clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
+		}
+
+		if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 &&
+				should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) {
+			clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
 
-	if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 &&
-			should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) {
-		clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
+			/* To disable FCLK P-state switching, send FCLK_PSTATE_NOTSUPPORTED message to PMFW */
+			if (!clk_mgr_base->clks.fclk_p_state_change_support) {
+				/* Handle code for sending a message to PMFW that FCLK P-state change is not supported */
+				dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED);
+			}
+		}
 
-		/* To disable FCLK P-state switching, send FCLK_PSTATE_NOTSUPPORTED message to PMFW */
-		if (!clk_mgr_base->clks.fclk_p_state_change_support) {
-			/* Handle code for sending a message to PMFW that FCLK P-state change is not supported */
-			dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED);
+		/* Always update saved value, even if new value not set due to P-State switching unsupported */
+		if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
+			clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
+			update_uclk = true;
 		}
-	}
 
-	/* Always update saved value, even if new value not set due to P-State switching unsupported */
-	if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
-		clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
-		update_uclk = true;
-	}
+		/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
+		if (clk_mgr_base->clks.p_state_change_support &&
+				(update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))
+			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
+
+		if (clk_mgr_base->clks.fclk_p_state_change_support &&
+				(update_uclk || !clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
 
-	/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
-	if (clk_mgr_base->clks.p_state_change_support &&
-			(update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))
-		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
+			/* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
+			dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED);
+		}
 
-	if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 &&
-			clk_mgr_base->clks.fclk_p_state_change_support &&
-			(update_uclk || !clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
-		/* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
-		dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED);
+		if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
+				clk_mgr_base->clks.num_ways > new_clocks->num_ways) {
+			clk_mgr_base->clks.num_ways = new_clocks->num_ways;
+			dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
+		}
 	}
 
 	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
@@ -380,13 +395,19 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 			dpp_clock_lowered = true;
 
 		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
-		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
+
+		if (clk_mgr->smu_present)
+			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
+
 		update_dppclk = true;
 	}
 
 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
-		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));
+
+		if (clk_mgr->smu_present)
+			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));
+
 		update_dispclk = true;
 	}
 
-- 
GitLab


From 0c9ed6044c5d08562d38d56e94279badef39e4c7 Mon Sep 17 00:00:00 2001
From: Chaitanya Dhere <chaitanya.dhere@amd.com>
Date: Mon, 11 Apr 2022 13:37:21 -0400
Subject: [PATCH 0202/1731] drm/amd/display: FCLK P-state support updates

[Why]
Previously we used to send FCLK P-state enable messages upon each call
to update_clocks based on dml output. This resulted in increased message
transactions between DC and PMFW.

[How]
Update the code to check safe_to_lower status and send the message based
on dml input only on boot. This reduces message transactions. Also
remove other unwanted code based on current code status.

Signed-off-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c  | 11 +++++++----
 .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h  |  1 -
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 9f35a74a1d7dd..3d2807fc769f1 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -284,7 +284,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 	bool dpp_clock_lowered = false;
 	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
 	bool force_reset = false;
-	bool update_uclk = false;
+	bool update_uclk = false, update_fclk = false;
 	bool p_state_change_support;
 	bool fclk_p_state_change_support;
 	int total_plane_count;
@@ -371,14 +371,17 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 			update_uclk = true;
 		}
 
+		/* Always update saved value, even if new value not set due to P-State switching unsupported. Also check safe_to_lower for FCLK */
+		if (safe_to_lower && (clk_mgr_base->clks.fclk_p_state_change_support != clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
+			update_fclk = true;
+		}
+
 		/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
 		if (clk_mgr_base->clks.p_state_change_support &&
 				(update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))
 			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
 
-		if (clk_mgr_base->clks.fclk_p_state_change_support &&
-				(update_uclk || !clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
-
+		if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && clk_mgr_base->clks.fclk_p_state_change_support && update_fclk) {
 			/* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
 			dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED);
 		}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
index 11b25de1527fb..674a52dbecad8 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
@@ -33,7 +33,6 @@
 #define FCLK_PSTATE_SUPPORTED          0x01
 
 /* TODO Remove this MSG ID define after it becomes available in dalsmc */
-#define DALSMC_MSG_SetFclkSwitchAllow	0x11
 #define DALSMC_MSG_SetCabForUclkPstate	0x12
 #define DALSMC_Result_OK				0x1
 
-- 
GitLab


From 327f79d7a1d2dcc10aeda05983c4d1532dd0830a Mon Sep 17 00:00:00 2001
From: Samson Tam <Samson.Tam@amd.com>
Date: Fri, 4 Mar 2022 09:34:58 -0500
Subject: [PATCH 0203/1731] drm/amd/display: Updates for OTG and DCCG clocks

Use DTBCLK for valid pixel clock generation

Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 5 ++++-
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h | 4 ++++
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h | 1 +
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index df155cc2bfea0..3fe5882ed0188 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -514,7 +514,6 @@ struct dcn_optc_registers {
 	type DIG_UPDATE_POSITION_X;\
 	type DIG_UPDATE_POSITION_Y;\
 	type OTG_H_TIMING_DIV_MODE;\
-	type OTG_H_TIMING_DIV_MODE_MANUAL;\
 	type OTG_DRR_TIMING_DBUF_UPDATE_MODE;\
 	type OTG_CRC_DSC_MODE;\
 	type OTG_CRC_DATA_STREAM_COMBINE_MODE;\
@@ -522,13 +521,17 @@ struct dcn_optc_registers {
 	type OTG_CRC_DATA_FORMAT;\
 	type OTG_V_TOTAL_LAST_USED_BY_DRR;
 
+#define TG_REG_FIELD_LIST_DCN3_2(type) \
+	type OTG_H_TIMING_DIV_MODE_MANUAL;
 
 struct dcn_optc_shift {
 	TG_REG_FIELD_LIST(uint8_t)
+	TG_REG_FIELD_LIST_DCN3_2(uint8_t)
 };
 
 struct dcn_optc_mask {
 	TG_REG_FIELD_LIST(uint32_t)
+	TG_REG_FIELD_LIST_DCN3_2(uint32_t)
 };
 
 struct optc {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h
index 0e54c0a105a10..1c46fad0977bf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h
@@ -45,6 +45,7 @@
 	SR(PHYDSYMCLK_CLOCK_CNTL),\
 	SR(PHYESYMCLK_CLOCK_CNTL),\
 	SR(DPSTREAMCLK_CNTL),\
+	SR(HDMISTREAMCLK_CNTL),\
 	SR(SYMCLK32_SE_CNTL),\
 	SR(SYMCLK32_LE_CNTL),\
 	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
@@ -98,6 +99,8 @@
 	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_SRC_SEL, mask_sh),\
 	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_SRC_SEL, mask_sh),\
 	DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_EN, mask_sh),\
+	DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_DTO_FORCE_DIS, mask_sh),\
+	DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_SRC_SEL, mask_sh),\
 	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\
 	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\
 	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\
@@ -143,6 +146,7 @@
 	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\
 	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_SRC_SEL, mask_sh),\
 	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\
+	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
 	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh)
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
index e07b317ed3f45..5e57c39235fab 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
@@ -245,6 +245,7 @@
 	SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
 	SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
 	SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
+	SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\
 	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
 	SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
 
-- 
GitLab


From 214d72f62978c28fe27d22d0d498d04493e9ce86 Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Tue, 26 Apr 2022 14:29:15 -0400
Subject: [PATCH 0204/1731] drm/amd/display: update disp pattern generator
 routine for DCN30

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.c    | 33 ++-----------------
 1 file changed, 2 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 782b8db451b43..ecdc7c7812172 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -959,35 +959,6 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
 		const struct tg_color *solid_color,
 		int width, int height, int offset)
 {
-	struct stream_resource *stream_res = &pipe_ctx->stream_res;
-	struct pipe_ctx *mpcc_pipe;
-
-	if (test_pattern != CONTROLLER_DP_TEST_PATTERN_VIDEOMODE) {
-		pipe_ctx->vtp_locked = false;
-		/* turning on DPG */
-		stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp, test_pattern, color_space,
-				color_depth, solid_color, width, height, offset);
-
-		/* Defer hubp blank if tg is locked */
-		if (stream_res->tg->funcs->is_tg_enabled(stream_res->tg)) {
-			if (stream_res->tg->funcs->is_locked(stream_res->tg))
-				pipe_ctx->vtp_locked = true;
-			else {
-				/* Blank HUBP to allow p-state during blank on all timings */
-				pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, true);
-
-				for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
-					mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true);
-			}
-		}
-	} else {
-		/* turning off DPG */
-		pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, false);
-		for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
-			if (mpcc_pipe->plane_res.hubp)
-				mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, false);
-
-		stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp, test_pattern, color_space,
-				color_depth, solid_color, width, height, offset);
-	}
+	pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
+			color_space, color_depth, solid_color, width, height, offset);
 }
-- 
GitLab


From 80fb7a409c64ef304e4040320e87dbb2f10968ca Mon Sep 17 00:00:00 2001
From: Martin Leung <Martin.Leung@amd.com>
Date: Sun, 20 Feb 2022 21:44:26 -0500
Subject: [PATCH 0205/1731] drm/amd/display: cleaning up smu_if to add future
 flexibility

This commit cleans up code that uses old variables and adds some SMU
interfaces for future flexibility.

Signed-off-by: Martin Leung <Martin.Leung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c  | 19 +++---
 .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h  |  7 +--
 .../dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h  | 63 +++++++++++++++++++
 .../gpu/drm/amd/display/dmub/src/dmub_dcn32.c |  5 +-
 4 files changed, 78 insertions(+), 16 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
index 35e8afe6db933..95ab268e91795 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
@@ -27,6 +27,8 @@
 
 #include "clk_mgr_internal.h"
 #include "reg_helper.h"
+#include "dalsmc.h"
+#include "smu13_driver_if.h"
 
 #define mmDAL_MSG_REG  0x1628A
 #define mmDAL_ARG_REG  0x16273
@@ -38,8 +40,6 @@
 	mm ## reg_name
 
 #include "logger_types.h"
-#include "dalsmc.h"
-#include "smu13_driver_if.h"
 
 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
 
@@ -100,14 +100,6 @@ void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool e
 			DALSMC_MSG_SetFclkSwitchAllow, enable ? FCLK_PSTATE_SUPPORTED : FCLK_PSTATE_NOTSUPPORTED, NULL);
 }
 
-void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
-{
-       smu_print("SMU Transfer WM table DRAM 2 SMU\n");
-
-       dcn32_smu_send_msg_with_param(clk_mgr,
-                       DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL);
-}
-
 void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways)
 {
 	smu_print("Numways for SubVP : %d\n", num_ways);
@@ -115,3 +107,10 @@ void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsig
 	dcn32_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_SetCabForUclkPstate, num_ways, NULL);
 }
 
+void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
+{
+	smu_print("SMU Transfer WM table DRAM 2 SMU\n");
+
+	dcn32_smu_send_msg_with_param(clk_mgr,
+			DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
index 674a52dbecad8..5f69cdcb98855 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
@@ -37,12 +37,9 @@
 #define DALSMC_Result_OK				0x1
 
 void
-dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr,
-				   bool enable);
-
+dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable);
 void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
-
 void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways);
-
+void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
 
 #endif /* __DCN32_CLK_MGR_SMU_MSG_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h
new file mode 100644
index 0000000000000..d30fbbdd1792c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h
@@ -0,0 +1,63 @@
+// This is a stripped-down version of the smu13_driver_if.h file for the relevant DAL interfaces.
+
+#define SMU13_DRIVER_IF_VERSION  0x18
+
+//Only Clks that have DPM descriptors are listed here
+typedef enum {
+	PPCLK_GFXCLK = 0,
+	PPCLK_SOCCLK,
+	PPCLK_UCLK,
+	PPCLK_FCLK,
+	PPCLK_DCLK_0,
+	PPCLK_VCLK_0,
+	PPCLK_DCLK_1,
+	PPCLK_VCLK_1,
+	PPCLK_DISPCLK,
+	PPCLK_DPPCLK,
+	PPCLK_DPREFCLK,
+	PPCLK_DCFCLK,
+	PPCLK_DTBCLK,
+	PPCLK_COUNT,
+} PPCLK_e;
+
+typedef struct {
+	uint8_t  WmSetting;
+	uint8_t  Flags;
+	uint8_t  Padding[2];
+
+} WatermarkRowGeneric_t;
+
+#define NUM_WM_RANGES 4
+
+typedef enum {
+	WATERMARKS_CLOCK_RANGE = 0,
+	WATERMARKS_DUMMY_PSTATE,
+	WATERMARKS_MALL,
+	WATERMARKS_COUNT,
+} WATERMARKS_FLAGS_e;
+
+typedef struct {
+	// Watermarks
+	WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES];
+} Watermarks_t;
+
+typedef struct {
+	Watermarks_t Watermarks;
+	uint32_t  Spare[16];
+
+	uint32_t     MmHubPadding[8]; // SMU internal use
+} WatermarksExternal_t;
+
+// Table types
+#define TABLE_PMFW_PPTABLE            0
+#define TABLE_COMBO_PPTABLE           1
+#define TABLE_WATERMARKS              2
+#define TABLE_AVFS_PSM_DEBUG          3
+#define TABLE_PMSTATUSLOG             4
+#define TABLE_SMU_METRICS             5
+#define TABLE_DRIVER_SMU_CONFIG       6
+#define TABLE_ACTIVITY_MONITOR_COEFF  7
+#define TABLE_OVERDRIVE               8
+#define TABLE_I2C_COMMANDS            9
+#define TABLE_DRIVER_INFO             10
+#define TABLE_COUNT                   11
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
index d298f6016e0b5..a76da0131addd 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
@@ -39,7 +39,10 @@
 
 const struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs = {
 #define DMUB_SR(reg) REG_OFFSET_EXP(reg),
-		{ DMUB_DCN32_REGS() },
+	{
+		DMUB_DCN32_REGS()
+		DMCUB_INTERNAL_REGS()
+	},
 #undef DMUB_SR
 
 #define DMUB_SF(reg, field) FD_MASK(reg, field),
-- 
GitLab


From b6a93844145395068574cbbfaf3aea91d1f24f1a Mon Sep 17 00:00:00 2001
From: Samson Tam <Samson.Tam@amd.com>
Date: Mon, 21 Mar 2022 10:22:19 -0400
Subject: [PATCH 0206/1731] drm/amd/display: Match dprefclk with clk registers

Update base.dprefclk_khz to match result from dcn32_dump_clk_registers()

Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 3d2807fc769f1..6a1d7c86e6b71 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -622,7 +622,11 @@ void dcn32_clk_mgr_construct(
 	clk_mgr->ss_on_dprefclk = false;
 	clk_mgr->dfs_ref_freq_khz = 100000;
 
-	clk_mgr->base.dprefclk_khz = 717000; /* Changed as per DCN3.2_clock_frequency doc */
+	/* Changed from DCN3.2_clock_frequency doc to match
+	 * dcn32_dump_clk_registers from 4 * dentist_vco_freq_khz /
+	 * dprefclk DID divider
+	 */
+	clk_mgr->base.dprefclk_khz = 716666;
 	clk_mgr->dccg->ref_dtbclk_khz = 268750;
 
 	/* integer part is now VCO frequency in kHz */
@@ -636,8 +640,7 @@ void dcn32_clk_mgr_construct(
 	}
 
 	if (clk_mgr->base.boot_snapshot.dprefclk != 0) {
-		//ASSERT(clk_mgr->base.dprefclk_khz == clk_mgr->base.boot_snapshot.dprefclk);
-		//clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;
+		clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;
 	}
 	dcn32_clock_read_ss_info(clk_mgr);
 
-- 
GitLab


From 405bb9eea36a02798631e8409f1182705699d092 Mon Sep 17 00:00:00 2001
From: Alvin Lee <Alvin.Lee2@amd.com>
Date: Fri, 29 Apr 2022 20:41:10 -0400
Subject: [PATCH 0207/1731] drm/amd/display: Implement DTBCLK ref switching on
 dcn32

[WHY & HOW]
Implements DTB ref clock switching with reg key default to OFF.
Refactors dccg DTBCLK logic to not store redundant state information
dccg. Also removes duplicated functions that should be inherited from
other dcn versions.

Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c  | 87 +++++++++++++++----
 .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c  | 18 ++++
 .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h  |  1 +
 drivers/gpu/drm/amd/display/dc/dc.h           |  5 +-
 .../display/dc/dce110/dce110_hw_sequencer.c   |  9 +-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c |  1 +
 .../gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c |  2 +
 .../drm/amd/display/dc/dcn32/dcn32_resource.c | 12 ++-
 .../amd/display/dc/dcn321/dcn321_resource.c   | 11 ++-
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h  |  3 +-
 10 files changed, 118 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 6a1d7c86e6b71..1db61029481ba 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -29,9 +29,11 @@
 #include "dcn32/dcn32_clk_mgr_smu_msg.h"
 #include "dcn20/dcn20_clk_mgr.h"
 #include "dce100/dce_clk_mgr.h"
+#include "dcn31/dcn31_clk_mgr.h"
 #include "reg_helper.h"
 #include "core_types.h"
 #include "dm_helpers.h"
+#include "dc_link_dp.h"
 
 #include "atomfirmware.h"
 #include "smu13_driver_if.h"
@@ -253,9 +255,10 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
 					&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
 					&num_levels);
 	/* DTBCLK */
-	dcn32_init_single_clock(clk_mgr, PPCLK_DTBCLK,
-			&clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
-			&num_levels);
+	if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch)
+		dcn32_init_single_clock(clk_mgr, PPCLK_DTBCLK,
+				&clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
+				&num_levels);
 
 	/* DISPCLK */
 	dcn32_init_single_clock(clk_mgr, PPCLK_DISPCLK,
@@ -270,6 +273,39 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
 	dcn32_build_wm_range_table(clk_mgr);
 }
 
+static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
+			struct dc_state *context,
+			int ref_dtbclk_khz)
+{
+	struct dccg *dccg = clk_mgr->dccg;
+	uint32_t tg_mask = 0;
+	int i;
+
+	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+		struct dtbclk_dto_params dto_params = {0};
+
+		/* use mask to program DTO once per tg */
+		if (pipe_ctx->stream_res.tg &&
+				!(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {
+			tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);
+
+			dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
+			dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
+
+			if (is_dp_128b_132b_signal(pipe_ctx)) {
+				dto_params.pixclk_khz = pipe_ctx->stream->phy_pix_clk;
+
+				if (pipe_ctx->stream_res.audio != NULL)
+					dto_params.req_audio_dtbclk_khz = 24000;
+			}
+
+			dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
+			//dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params);
+		}
+	}
+}
+
 static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 			struct dc_state *context,
 			bool safe_to_lower)
@@ -320,7 +356,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 
 		if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
 			clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
-			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
+			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
 		}
 
 		if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
@@ -350,7 +386,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 
 			/* to disable P-State switching, set UCLK min = max */
 			if (!clk_mgr_base->clks.p_state_change_support)
-				dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
+				dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
 						clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
 		}
 
@@ -379,7 +415,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 		/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
 		if (clk_mgr_base->clks.p_state_change_support &&
 				(update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))
-			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
+			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
 
 		if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && clk_mgr_base->clks.fclk_p_state_change_support && update_fclk) {
 			/* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
@@ -400,7 +436,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
 
 		if (clk_mgr->smu_present)
-			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
+			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
 
 		update_dppclk = true;
 	}
@@ -409,11 +445,25 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
 
 		if (clk_mgr->smu_present)
-			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));
+			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));
 
 		update_dispclk = true;
 	}
 
+	if (!new_clocks->dtbclk_en) {
+		new_clocks->ref_dtbclk_khz = 0;
+	}
+
+	/* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
+	if (!dc->debug.disable_dtb_ref_clk_switch &&
+			should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
+		/* DCCG requires KHz precision for DTBCLK */
+		clk_mgr_base->clks.ref_dtbclk_khz =
+				dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));
+
+		dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz);
+	}
+
 	if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
 		if (dpp_clock_lowered) {
 			/* if clock is being lowered, increase DTO before lowering refclk */
@@ -502,13 +552,13 @@ static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current
 
 	if (current_mode) {
 		if (clk_mgr_base->clks.p_state_change_support)
-			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
+			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
 					khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
 		else
-			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
+			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
 					clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
 	} else {
-		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
+		dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
 				clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
 	}
 }
@@ -584,7 +634,7 @@ static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base)
 
 
 static struct clk_mgr_funcs dcn32_funcs = {
-		.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
+		.get_dp_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
 		.update_clocks = dcn32_update_clocks,
 		.init_clocks = dcn32_init_clocks,
 		.notify_wm_ranges = dcn32_notify_wm_ranges,
@@ -627,7 +677,13 @@ void dcn32_clk_mgr_construct(
 	 * dprefclk DID divider
 	 */
 	clk_mgr->base.dprefclk_khz = 716666;
-	clk_mgr->dccg->ref_dtbclk_khz = 268750;
+	if (ctx->dc->debug.disable_dtb_ref_clk_switch) {
+		//initialize DTB ref clock value if DPM disabled
+		if (ctx->dce_version == DCN_VERSION_3_21)
+			clk_mgr->base.clks.ref_dtbclk_khz = 477800;
+		else
+			clk_mgr->base.clks.ref_dtbclk_khz = 268750;
+	}
 
 	/* integer part is now VCO frequency in kHz */
 	clk_mgr->base.dentist_vco_freq_khz = 4300000;//dcn32_get_vco_frequency_from_reg(clk_mgr);
@@ -635,8 +691,9 @@ void dcn32_clk_mgr_construct(
 	if (clk_mgr->base.dentist_vco_freq_khz == 0)
 		clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */
 
-	if (clk_mgr->dccg->ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) {
-		clk_mgr->dccg->ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk;
+	if (ctx->dc->debug.disable_dtb_ref_clk_switch &&
+			clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) {
+		clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk;
 	}
 
 	if (clk_mgr->base.boot_snapshot.dprefclk != 0) {
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
index 95ab268e91795..d7c99e9179be5 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
@@ -114,3 +114,21 @@ void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
 	dcn32_smu_send_msg_with_param(clk_mgr,
 			DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL);
 }
+
+/* Returns the actual frequency that was set in MHz, 0 on failure */
+unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)
+{
+	uint32_t response = 0;
+
+	/* bits 23:16 for clock type, lower 16 bits for frequency in MHz */
+	uint32_t param = (clk << 16) | freq_mhz;
+
+	smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);
+
+	dcn32_smu_send_msg_with_param(clk_mgr,
+			DALSMC_MSG_SetHardMinByFreq, param, &response);
+
+	smu_print("SMU Frequency set = %d KHz\n", response);
+
+	return response;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
index 5f69cdcb98855..352435edbd79a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
@@ -41,5 +41,6 @@ dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable
 void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
 void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways);
 void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
+unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);
 
 #endif /* __DCN32_CLK_MGR_SMU_MSG_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 691654653ebb1..7bb67ab979e1a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -432,7 +432,6 @@ struct dc_clocks {
 	enum dcn_zstate_support_state zstate_support;
 	bool dtbclk_en;
 	int ref_dtbclk_khz;
-	int dtbclk_khz;
 	bool fclk_p_state_change_support;
 	enum dcn_pwr_state pwr_state;
 	/*
@@ -740,11 +739,11 @@ struct dc_debug_options {
 	bool force_disable_subvp;
 	bool force_subvp_mclk_switch;
 	bool force_usr_allow;
+	/* uses value at boot and disables switch */
+	bool disable_dtb_ref_clk_switch;
 	bool apply_vendor_specific_lttpr_wa;
 	bool extended_blank_optimization;
 	union aux_wake_wa_options aux_wake_wa;
-	/* uses value at boot and disables switch */
-	bool disable_dtb_ref_clk_switch;
 	uint8_t psr_power_use_phy_fsm;
 	enum dml_hostvm_override_opts dml_hostvm_override;
 };
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index a76523c95ab26..631a8a2f9fc37 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2191,18 +2191,15 @@ static void dce110_setup_audio_dto(
 			build_audio_output(context, pipe_ctx, &audio_output);
 
 			if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
-				struct dtbclk_dto_params dto_params = {0};
+				/* disable audio DTBCLK DTO */
+				dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
+					dc->res_pool->dccg, 0);
 
 				pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
 						pipe_ctx->stream_res.audio,
 						pipe_ctx->stream->signal,
 						&audio_output.crtc_info,
 						&audio_output.pll_info);
-
-				dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
-					dc->res_pool->dccg,
-					&dto_params);
-
 			} else
 				pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
 					pipe_ctx->stream_res.audio,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 13dbf99af2205..8eeb3b69b5b93 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -590,6 +590,7 @@ void dccg31_set_audio_dtbclk_dto(
 		phase = div_u64((((unsigned long long)modulo * params->req_audio_dtbclk_khz) + params->ref_dtbclk_khz - 1),
 			params->ref_dtbclk_khz);
 
+
 		REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, modulo);
 		REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, phase);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
index 070be7e8ad0db..08232d05d8943 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
@@ -179,11 +179,13 @@ void dccg32_set_dtbclk_dto(
 
 void dccg32_set_valid_pixel_rate(
 		struct dccg *dccg,
+		int ref_dtbclk_khz,
 		int otg_inst,
 		int pixclk_khz)
 {
 	struct dtbclk_dto_params dto_params = {0};
 
+	dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
 	dto_params.otg_inst = otg_inst;
 	dto_params.pixclk_khz = pixclk_khz;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index b492eb424d193..1ea6d258a20d4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -3306,6 +3306,7 @@ void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display
 	// context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;
 	context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
 	context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
+	context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000;
 	if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported)
 		context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false;
 	else
@@ -3560,10 +3561,15 @@ static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw
 			dcn3_2_soc.clock_limits[i].dscclk_mhz  = max_dispclk_mhz / 3;
 
 			/* Populate from bw_params for DTBCLK, SOCCLK */
-			if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0)
-				dcn3_2_soc.clock_limits[i].dtbclk_mhz  = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz;
-			else
+			if (i > 0) {
+				if (!bw_params->clk_table.entries[i].dtbclk_mhz) {
+					dcn3_2_soc.clock_limits[i].dtbclk_mhz  = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz;
+				} else {
+					dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
+				}
+			} else if (bw_params->clk_table.entries[i].dtbclk_mhz) {
 				dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
+			}
 
 			if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
 				dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index 780409eb0e981..48af91affb0c0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -1910,10 +1910,15 @@ static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b
 			dcn3_21_soc.clock_limits[i].dscclk_mhz  = max_dispclk_mhz / 3;
 
 			/* Populate from bw_params for DTBCLK, SOCCLK */
-			if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0)
-				dcn3_21_soc.clock_limits[i].dtbclk_mhz  = dcn3_21_soc.clock_limits[i-1].dtbclk_mhz;
-			else
+			if (i > 0) {
+				if (!bw_params->clk_table.entries[i].dtbclk_mhz) {
+					dcn3_21_soc.clock_limits[i].dtbclk_mhz = dcn3_21_soc.clock_limits[i-1].dtbclk_mhz;
+				} else {
+					dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
+				}
+			} else if (bw_params->clk_table.entries[i].dtbclk_mhz) {
 				dcn3_21_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
+			}
 
 			if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
 				dcn3_21_soc.clock_limits[i].socclk_mhz = dcn3_21_soc.clock_limits[i-1].socclk_mhz;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index e0dd04626eb58..025169457cc86 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -70,7 +70,7 @@ struct dccg {
 	int ref_dppclk;
 	//int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */
 	//int audio_dtbclk_khz;/* TODO needs to be removed */
-	int ref_dtbclk_khz;/* TODO needs to be removed */
+	//int ref_dtbclk_khz;/* TODO needs to be removed */
 };
 
 struct dtbclk_dto_params {
@@ -154,6 +154,7 @@ void (*set_pixel_rate_div)(
 
 void (*set_valid_pixel_rate)(
         struct dccg *dccg,
+	int ref_dtbclk_khz,
         int otg_inst,
         int pixclk_khz);
 
-- 
GitLab


From 3e80a5b068a5fedc69ada30ba1a2d1e0b76dfc25 Mon Sep 17 00:00:00 2001
From: Duncan Ma <duncan.ma@amd.com>
Date: Thu, 31 Mar 2022 15:13:22 -0400
Subject: [PATCH 0208/1731] drm/amd/display: Add ODM seamless boot support

Revised validation logic when marking for seamless boot. Init resources
accordingly when Pre-OS has ODM enabled. Reset ODM when transitioning
Pre-OS odm to Post-OS non-odm to avoid corruption. Apply logic to set
odm accordingly upon commit.

Signed-off-by: Duncan Ma <duncan.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c |  9 +++++++-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  5 +++++
 .../gpu/drm/amd/display/dc/dcn31/dcn31_optc.c | 21 +++++++++++++++++++
 .../drm/amd/display/dc/dcn32/dcn32_hwseq.c    |  4 ++--
 .../amd/display/dc/inc/hw/timing_generator.h  |  2 ++
 5 files changed, 38 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index b087452e45908..7072b79d1207d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2165,7 +2165,7 @@ static int acquire_resource_from_hw_enabled_state(
 
 		if (pipe_ctx->stream_res.tg->funcs->get_optc_source)
 			pipe_ctx->stream_res.tg->funcs->get_optc_source(pipe_ctx->stream_res.tg,
-					&numPipes, &id_src[0], &id_src[1]);
+						&numPipes, &id_src[0], &id_src[1]);
 
 		if (id_src[0] == 0xf && id_src[1] == 0xf) {
 			id_src[0] = tg_inst;
@@ -2177,6 +2177,8 @@ static int acquire_resource_from_hw_enabled_state(
 			if (id_src[i] == 0xf)
 				return -1;
 
+			pipe_ctx = &res_ctx->pipe_ctx[id_src[i]];
+
 			pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
 			pipe_ctx->plane_res.mi = pool->mis[id_src[i]];
 			pipe_ctx->plane_res.hubp = pool->hubps[id_src[i]];
@@ -2190,13 +2192,17 @@ static int acquire_resource_from_hw_enabled_state(
 
 				if (pool->mpc->funcs->read_mpcc_state) {
 					struct mpcc_state s = {0};
+
 					pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
+
 					if (s.dpp_id < MAX_MPCC)
 						pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id =
 								s.dpp_id;
+
 					if (s.bot_mpcc_id < MAX_MPCC)
 						pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
 								&pool->mpc->mpcc_array[s.bot_mpcc_id];
+
 					if (s.opp_id < MAX_OPP)
 						pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
 				}
@@ -2205,6 +2211,7 @@ static int acquire_resource_from_hw_enabled_state(
 
 			if (id_src[i] >= pool->timing_generator_count) {
 				id_src[i] = pool->timing_generator_count - 1;
+
 				pipe_ctx->stream_res.tg = pool->timing_generators[id_src[i]];
 				pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
 			}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 1cb206dc83526..e3a62873c0e70 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1375,6 +1375,11 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
 		pipe_ctx->stream_res.tg = NULL;
 		pipe_ctx->plane_res.hubp = NULL;
 
+		if (tg->funcs->is_tg_enabled(tg)) {
+			if (tg->funcs->init_odm)
+				tg->funcs->init_odm(tg);
+		}
+
 		tg->funcs->tg_init(tg);
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
index 96fac715a77b4..c4304f25ce953 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
@@ -213,6 +213,26 @@ void optc31_set_drr(
 	}
 }
 
+void optc3_init_odm(struct timing_generator *optc)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
+			OPTC_NUM_OF_INPUT_SEGMENT, 0,
+			OPTC_SEG0_SRC_SEL, optc->inst,
+			OPTC_SEG1_SRC_SEL, 0xf,
+			OPTC_SEG2_SRC_SEL, 0xf,
+			OPTC_SEG3_SRC_SEL, 0xf
+			);
+
+	REG_SET(OTG_H_TIMING_CNTL, 0,
+			OTG_H_TIMING_DIV_MODE, 0);
+
+	REG_SET(OPTC_MEMORY_CONFIG, 0,
+			OPTC_MEM_SEL, 0);
+	optc1->opp_count = 1;
+}
+
 static struct timing_generator_funcs dcn31_tg_funcs = {
 		.validate_timing = optc1_validate_timing,
 		.program_timing = optc1_program_timing,
@@ -273,6 +293,7 @@ static struct timing_generator_funcs dcn31_tg_funcs = {
 		.program_manual_trigger = optc2_program_manual_trigger,
 		.setup_manual_trigger = optc2_setup_manual_trigger,
 		.get_hw_timing = optc1_get_hw_timing,
+		.init_odm = optc3_init_odm,
 };
 
 void dcn31_timing_generator_init(struct optc *optc1)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 04360553a43f3..a10ec59191941 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -657,7 +657,7 @@ void dcn32_init_hw(struct dc *dc)
 	 * Otherwise, if taking control is not possible, we need to power
 	 * everything down.
 	 */
-	if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.seamless_boot_edp_requested) {
+	if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
 		hws->funcs.init_pipes(dc, dc->current_state);
 		if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
 			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
@@ -669,7 +669,7 @@ void dcn32_init_hw(struct dc *dc)
 	 * To avoid this, power down hardware on boot
 	 * if DIG is turned on and seamless boot not enabled
 	 */
-	if (dc->config.seamless_boot_edp_requested) {
+	if (!dc->config.seamless_boot_edp_requested) {
 		struct dc_link *edp_links[MAX_NUM_EDP];
 		struct dc_link *edp_link;
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index a89b2230cd2c4..62d4683f17a24 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -318,6 +318,8 @@ struct timing_generator_funcs {
 			int vmin, int vmax);
 	bool (*validate_vtotal_change_limit)(struct timing_generator *optc,
 			uint32_t vtotal_change_limit);
+
+	void (*init_odm)(struct timing_generator *tg);
 };
 
 #endif
-- 
GitLab


From d8e4fb9112e88d8d87ffbc38fa511e7118042d4f Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Wed, 1 Jun 2022 22:22:07 -0400
Subject: [PATCH 0209/1731] drm/amdgpu/display: Protect some functions with
 CONFIG_DRM_AMD_DC_DCN

Protect remove_hpo_dp_link_enc_from_ctx() and release_hpo_dp_link_enc()
with CONFIG_DRM_AMD_DC_DCN as the functions are only called from code
that is protected by CONFIG_DRM_AMD_DC_DCN.  Fixes build fail with
-Werror=unused-function.

Fixes: 9b0e0d433f74 ("drm/amd/display: Add dependant changes for DCN32/321")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 7072b79d1207d..9bbdfcd6b3a47 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1801,6 +1801,7 @@ static inline void retain_hpo_dp_link_enc(
 	res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]++;
 }
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 static inline void release_hpo_dp_link_enc(
 		struct resource_context *res_ctx,
 		int enc_index)
@@ -1808,6 +1809,7 @@ static inline void release_hpo_dp_link_enc(
 	ASSERT(res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] > 0);
 	res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]--;
 }
+#endif
 
 static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx,
 		const struct resource_pool *pool,
@@ -1832,6 +1834,7 @@ static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx,
 	return pipe_ctx->link_res.hpo_dp_link_enc != NULL;
 }
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx,
 		struct pipe_ctx *pipe_ctx,
 		struct dc_stream_state *stream)
@@ -1845,6 +1848,7 @@ static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx,
 		pipe_ctx->link_res.hpo_dp_link_enc = NULL;
 	}
 }
+#endif
 
 /* TODO: release audio object */
 void update_audio_usage(
-- 
GitLab


From 8b67e738ca17fb52a275b1cc0191dfce0e9cd7a5 Mon Sep 17 00:00:00 2001
From: Alan Liu <HaoPing.Liu@amd.com>
Date: Thu, 2 Jun 2022 19:41:58 +0800
Subject: [PATCH 0210/1731] drm/amdgpu/display/dc: Add ACP_DATA register

Define ixAZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA
Define AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK/SHIFT

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h       | 1 +
 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h
index 6df651a94b0a1..581ba639b4ea5 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h
@@ -6981,6 +6981,7 @@
 #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                        0x23
 #define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                            0x24
 #define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                           0x25
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA                                  0x27
 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                         0x28
 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                         0x29
 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                         0x2a
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h
index fa1f4374fafe8..fd387c7363b67 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h
@@ -13639,6 +13639,8 @@
 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
 #define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40
 #define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK 0x40
+#define AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT 0x6
 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x7f
 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0xff00
-- 
GitLab


From 83eb5385b4f021c2674b1d78675bfd10443cdf74 Mon Sep 17 00:00:00 2001
From: David Zhang <dingchen.zhang@amd.com>
Date: Mon, 14 Mar 2022 11:31:12 -0400
Subject: [PATCH 0211/1731] drm/amd/display: align dmub cmd header to latest
 dmub FW to support PSR-SU

[why]
PSR-SU is implemented in upstreamed dmub FW but not enabled on
DM and DC. We'd add necessary and missing definitions in dmub
cmd header to align w/ the up-to-date DMUB FW for PSR-SU support.

[how]
Add definitions and items below into dmub cmd header:
- DMUB psr version enumeration for PSR-SU
- dirty rectangle structure
- psr debug flag of forcing full frame update
- dmub command of updating dirty rectangle and cursor infor
- dmub psr command type of setting sink vtotal in PSR active
- dmub psr su debug flags structure
- dmub cmd structure for
  - updating dirty rectangle
  - cursor infor
  - setting sink vtotal
- dmub ringbuffer command items

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 250 +++++++++++++++++-
 1 file changed, 245 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 8fc1846f07087..f6ad1b8c7034f 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -101,6 +101,11 @@
 /* Trace buffer offset for entry */
 #define TRACE_BUFFER_ENTRY_OFFSET  16
 
+/**
+ * Maximum number of dirty rects supported by FW.
+ */
+#define DMUB_MAX_DIRTY_RECTS 3
+
 /**
  *
  * PSR control version legacy
@@ -165,6 +170,31 @@ union dmub_addr {
 	uint64_t quad_part; /*<< 64 bit address */
 };
 
+/**
+ * Dirty rect definition.
+ */
+struct dmub_rect {
+	/**
+	 * Dirty rect x offset.
+	 */
+	uint32_t x;
+
+	/**
+	 * Dirty rect y offset.
+	 */
+	uint32_t y;
+
+	/**
+	 * Dirty rect width.
+	 */
+	uint32_t width;
+
+	/**
+	 * Dirty rect height.
+	 */
+	uint32_t height;
+};
+
 /**
  * Flags that can be set by driver to change some PSR behaviour.
  */
@@ -177,6 +207,12 @@ union dmub_psr_debug_flags {
 		 * Enable visual confirm in FW.
 		 */
 		uint32_t visual_confirm : 1;
+
+		/**
+		 * Force all selective updates to bw full frame updates.
+		 */
+		uint32_t force_full_frame_update : 1;
+
 		/**
 		 * Use HW Lock Mgr object to do HW locking in FW.
 		 */
@@ -616,6 +652,14 @@ enum dmub_cmd_type {
 	 * Command type used for all ABM commands.
 	 */
 	DMUB_CMD__ABM = 66,
+	/**
+	 * Command type used to update dirty rects in FW.
+	 */
+	DMUB_CMD__UPDATE_DIRTY_RECT = 67,
+	/**
+	 * Command type used to update cursor info in FW.
+	 */
+	DMUB_CMD__UPDATE_CURSOR_INFO = 68,
 	/**
 	 * Command type used for HW locking in FW.
 	 */
@@ -1439,6 +1483,10 @@ enum dmub_cmd_psr_type {
 	 * Forces PSR enabled until an explicit PSR disable call.
 	 */
 	DMUB_CMD__PSR_FORCE_STATIC		= 5,
+	/**
+	 * Set vtotal in psr active for FreeSync PSR.
+	 */
+	DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6,
 	/**
 	 * Set PSR power option
 	 */
@@ -1453,6 +1501,10 @@ enum psr_version {
 	 * PSR version 1.
 	 */
 	PSR_VERSION_1				= 0,
+	/**
+	 * Freesync PSR SU.
+	 */
+	PSR_VERSION_SU_1			= 1,
 	/**
 	 * PSR not supported.
 	 */
@@ -1620,9 +1672,15 @@ struct dmub_cmd_psr_copy_settings_data {
 	 */
 	uint8_t frame_cap_ind;
 	/**
-	 * Explicit padding to 4 byte boundary.
+	 * Granularity of Y offset supported by sink.
 	 */
-	uint8_t pad[2];
+	uint8_t su_y_granularity;
+	/**
+	 * Indicates whether sink should start capturing
+	 * immediately following active scan line,
+	 * or starting with the 2nd active scan line.
+	 */
+	uint8_t line_capture_indication;
 	/**
 	 * Multi-display optimizations are implemented on certain ASICs.
 	 */
@@ -1633,9 +1691,13 @@ struct dmub_cmd_psr_copy_settings_data {
 	 */
 	uint16_t init_sdp_deadline;
 	/**
-	 * Explicit padding to 4 byte boundary.
+	 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities
+	 */
+	uint8_t rate_control_caps ;
+	/*
+	 * Force PSRSU always doing full frame update
 	 */
-	uint16_t pad2;
+	uint8_t force_ffu_mode;
 	/**
 	 * Length of each horizontal line in us.
 	 */
@@ -1827,6 +1889,164 @@ struct dmub_rb_cmd_psr_force_static {
 	struct dmub_cmd_psr_force_static_data psr_force_static_data;
 };
 
+/**
+ * PSR SU debug flags.
+ */
+union dmub_psr_su_debug_flags {
+	/**
+	 * PSR SU debug flags.
+	 */
+	struct {
+		/**
+		 * Update dirty rect in SW only.
+		 */
+		uint8_t update_dirty_rect_only : 1;
+		/**
+		 * Reset the cursor/plane state before processing the call.
+		 */
+		uint8_t reset_state : 1;
+	} bitfields;
+
+	/**
+	 * Union for debug flags.
+	 */
+	uint32_t u32All;
+};
+
+/**
+ * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
+ * This triggers a selective update for PSR SU.
+ */
+struct dmub_cmd_update_dirty_rect_data {
+	/**
+	 * Dirty rects from OS.
+	 */
+	struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS];
+	/**
+	 * PSR SU debug flags.
+	 */
+	union dmub_psr_su_debug_flags debug_flags;
+	/**
+	 * OTG HW instance.
+	 */
+	uint8_t pipe_idx;
+	/**
+	 * Number of dirty rects.
+	 */
+	uint8_t dirty_rect_count;
+	/**
+	 * PSR control version.
+	 */
+	uint8_t cmd_version;
+	/**
+	 * Panel Instance.
+	 * Panel isntance to identify which psr_state to use
+	 * Currently the support is only for 0 or 1
+	 */
+	uint8_t panel_inst;
+};
+
+/**
+ * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
+ */
+struct dmub_rb_cmd_update_dirty_rect {
+	/**
+	 * Command header.
+	 */
+	struct dmub_cmd_header header;
+	/**
+	 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
+	 */
+	struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data;
+};
+
+/**
+ * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
+ */
+struct dmub_cmd_update_cursor_info_data {
+	/**
+	 * Cursor dirty rects.
+	 */
+	struct dmub_rect cursor_rect;
+	/**
+	 * PSR SU debug flags.
+	 */
+	union dmub_psr_su_debug_flags debug_flags;
+	/**
+	 * Cursor enable/disable.
+	 */
+	uint8_t enable;
+	/**
+	 * OTG HW instance.
+	 */
+	uint8_t pipe_idx;
+	/**
+	 * PSR control version.
+	 */
+	uint8_t cmd_version;
+	/**
+	 * Panel Instance.
+	 * Panel isntance to identify which psr_state to use
+	 * Currently the support is only for 0 or 1
+	 */
+	uint8_t panel_inst;
+};
+/**
+ * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
+ */
+struct dmub_rb_cmd_update_cursor_info {
+	/**
+	 * Command header.
+	 */
+	struct dmub_cmd_header header;
+	/**
+	 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
+	 */
+	struct dmub_cmd_update_cursor_info_data update_cursor_info_data;
+};
+
+/**
+ * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
+ */
+struct dmub_cmd_psr_set_vtotal_data {
+	/**
+	 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle..
+	 */
+	uint16_t psr_vtotal_idle;
+	/**
+	 * PSR control version.
+	 */
+	uint8_t cmd_version;
+	/**
+	 * Panel Instance.
+	 * Panel isntance to identify which psr_state to use
+	 * Currently the support is only for 0 or 1
+	 */
+	uint8_t panel_inst;
+	/*
+	 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU.
+	 */
+	uint16_t psr_vtotal_su;
+	/**
+	 * Explicit padding to 4 byte boundary.
+	 */
+	uint8_t pad2[2];
+};
+
+/**
+ * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
+ */
+struct dmub_rb_cmd_psr_set_vtotal {
+	/**
+	 * Command header.
+	 */
+	struct dmub_cmd_header header;
+	/**
+	 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
+	 */
+	struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data;
+};
+
 /**
  * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command.
  */
@@ -1937,6 +2157,10 @@ enum hw_lock_client {
 	 * Driver is the client of HW Lock Manager.
 	 */
 	HW_LOCK_CLIENT_DRIVER = 0,
+	/**
+	 * PSR SU is the client of HW Lock Manager.
+	 */
+	HW_LOCK_CLIENT_PSR_SU		= 1,
 	/**
 	 * Invalid client.
 	 */
@@ -2640,7 +2864,6 @@ struct dmub_rb_cmd_get_usbc_cable_id {
  * union dmub_rb_cmd - DMUB inbox command.
  */
 union dmub_rb_cmd {
-	struct dmub_rb_cmd_lock_hw lock_hw;
 	/**
 	 * Elements shared with all commands.
 	 */
@@ -2701,6 +2924,23 @@ union dmub_rb_cmd {
 	 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
 	 */
 	struct dmub_rb_cmd_psr_force_static psr_force_static;
+	/**
+	 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
+	 */
+	struct dmub_rb_cmd_update_dirty_rect update_dirty_rect;
+	/**
+	 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
+	 */
+	struct dmub_rb_cmd_update_cursor_info update_cursor_info;
+	/**
+	 * Definition of a DMUB_CMD__HW_LOCK command.
+	 * Command is used by driver and FW.
+	 */
+	struct dmub_rb_cmd_lock_hw lock_hw;
+	/**
+	 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
+	 */
+	struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal;
 	/**
 	 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
 	 */
-- 
GitLab


From 5b7419ae1d208cab1e2826d473d8dab045aa75c7 Mon Sep 17 00:00:00 2001
From: Phillip Potter <phil@philpotter.co.uk>
Date: Sat, 21 May 2022 21:47:41 +0100
Subject: [PATCH 0212/1731] staging: r8188eu: fix rtw_alloc_hwxmits error
 detection for now

In _rtw_init_xmit_priv, we use the res variable to store the error
return from the newly converted rtw_alloc_hwxmits function. Sadly, the
calling function interprets res using _SUCCESS and _FAIL still, meaning
we change the semantics of the variable, even in the success case.

This leads to the following on boot:
r8188eu 1-2:1.0: _rtw_init_xmit_priv failed

In the long term, we should reverse these semantics, but for now, this
fixes the driver. Also, inside rtw_alloc_hwxmits remove the if blocks,
as HWXMIT_ENTRY is always 4.

Fixes: f94b47c6bde6 ("staging: r8188eu: add check for kzalloc")
Signed-off-by: Phillip Potter <phil@philpotter.co.uk>
Link: https://lore.kernel.org/r/20220521204741.921-1-phil@philpotter.co.uk
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/staging/r8188eu/core/rtw_xmit.c | 20 +++++---------------
 1 file changed, 5 insertions(+), 15 deletions(-)

diff --git a/drivers/staging/r8188eu/core/rtw_xmit.c b/drivers/staging/r8188eu/core/rtw_xmit.c
index 3d8e9dea76514..7135d89caac11 100644
--- a/drivers/staging/r8188eu/core/rtw_xmit.c
+++ b/drivers/staging/r8188eu/core/rtw_xmit.c
@@ -178,8 +178,7 @@ s32	_rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, struct adapter *padapter)
 
 	pxmitpriv->free_xmit_extbuf_cnt = num_xmit_extbuf;
 
-	res = rtw_alloc_hwxmits(padapter);
-	if (res) {
+	if (rtw_alloc_hwxmits(padapter)) {
 		res = _FAIL;
 		goto exit;
 	}
@@ -1483,19 +1482,10 @@ int rtw_alloc_hwxmits(struct adapter *padapter)
 
 	hwxmits = pxmitpriv->hwxmits;
 
-	if (pxmitpriv->hwxmit_entry == 5) {
-		hwxmits[0] .sta_queue = &pxmitpriv->bm_pending;
-		hwxmits[1] .sta_queue = &pxmitpriv->vo_pending;
-		hwxmits[2] .sta_queue = &pxmitpriv->vi_pending;
-		hwxmits[3] .sta_queue = &pxmitpriv->bk_pending;
-		hwxmits[4] .sta_queue = &pxmitpriv->be_pending;
-	} else if (pxmitpriv->hwxmit_entry == 4) {
-		hwxmits[0] .sta_queue = &pxmitpriv->vo_pending;
-		hwxmits[1] .sta_queue = &pxmitpriv->vi_pending;
-		hwxmits[2] .sta_queue = &pxmitpriv->be_pending;
-		hwxmits[3] .sta_queue = &pxmitpriv->bk_pending;
-	} else {
-	}
+	hwxmits[0].sta_queue = &pxmitpriv->vo_pending;
+	hwxmits[1].sta_queue = &pxmitpriv->vi_pending;
+	hwxmits[2].sta_queue = &pxmitpriv->be_pending;
+	hwxmits[3].sta_queue = &pxmitpriv->bk_pending;
 
 	return 0;
 }
-- 
GitLab


From 96f0a54e8e65a765b3a4ad4b53751581f23279f3 Mon Sep 17 00:00:00 2001
From: Larry Finger <Larry.Finger@lwfinger.net>
Date: Mon, 30 May 2022 20:31:03 -0500
Subject: [PATCH 0213/1731] staging: r8188eu: Fix warning of array overflow in
 ioctl_linux.c
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Building with -Warray-bounds results in the following warning plus others
related to the same problem:

CC [M]  drivers/staging/r8188eu/os_dep/ioctl_linux.o
In function ‘wpa_set_encryption’,
    inlined from ‘rtw_wx_set_enc_ext’ at drivers/staging/r8188eu/os_dep/ioctl_linux.c:1868:9:
drivers/staging/r8188eu/os_dep/ioctl_linux.c:412:41: warning: array subscript ‘struct ndis_802_11_wep[0]’ is partly outside array bounds of ‘void[25]’ [-Warray-bounds]
  412 |                         pwep->KeyLength = wep_key_len;
      |                         ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~
In file included from drivers/staging/r8188eu/os_dep/../include/osdep_service.h:19,
                 from drivers/staging/r8188eu/os_dep/ioctl_linux.c:4:
In function ‘kmalloc’,
    inlined from ‘kzalloc’ at ./include/linux/slab.h:733:9,
    inlined from ‘wpa_set_encryption’ at drivers/staging/r8188eu/os_dep/ioctl_linux.c:408:11,
    inlined from ‘rtw_wx_set_enc_ext’ at drivers/staging/r8188eu/os_dep/ioctl_linux.c:1868:9:
./include/linux/slab.h:605:16: note: object of size [17, 25] allocated by ‘__kmalloc’
  605 |         return __kmalloc(size, flags);
      |                ^~~~~~~~~~~~~~~~~~~~~~
./include/linux/slab.h:600:24: note: object of size [17, 25] allocated by ‘kmem_cache_alloc_trace’
  600 |                 return kmem_cache_alloc_trace(
      |                        ^~~~~~~~~~~~~~~~~~~~~~~
  601 |                                 kmalloc_caches[kmalloc_type(flags)][index],
      |                                 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  602 |                                 flags, size);
      |                                 ~~~~~~~~~~~~

Although it is unlikely that anyone is still using WEP encryption, the
size of the allocation needs to be increased just in case.

Fixes commit 2b42bd58b321 ("staging: r8188eu: introduce new os_dep dir for RTL8188eu driver")

Fixes: 2b42bd58b321 ("staging: r8188eu: introduce new os_dep dir for RTL8188eu driver")
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
Cc: Phillip Potter <phil@philpotter.co.uk>
Cc: Dan Carpenter <dan.carpenter@oracle.com>
Link: https://lore.kernel.org/r/20220531013103.2175-3-Larry.Finger@lwfinger.net
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/staging/r8188eu/os_dep/ioctl_linux.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/r8188eu/os_dep/ioctl_linux.c b/drivers/staging/r8188eu/os_dep/ioctl_linux.c
index 1b09462ca908d..8dd280e2739a2 100644
--- a/drivers/staging/r8188eu/os_dep/ioctl_linux.c
+++ b/drivers/staging/r8188eu/os_dep/ioctl_linux.c
@@ -403,7 +403,7 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param,
 
 		if (wep_key_len > 0) {
 			wep_key_len = wep_key_len <= 5 ? 5 : 13;
-			wep_total_len = wep_key_len + FIELD_OFFSET(struct ndis_802_11_wep, KeyMaterial);
+			wep_total_len = wep_key_len + sizeof(*pwep);
 			pwep = kzalloc(wep_total_len, GFP_KERNEL);
 			if (!pwep)
 				goto exit;
-- 
GitLab


From f84d83d8165570380f55f4ce578bfb131a9266c5 Mon Sep 17 00:00:00 2001
From: David Virag <virag.david003@gmail.com>
Date: Thu, 26 May 2022 07:58:40 +0200
Subject: [PATCH 0214/1731] arm64: dts: exynos: Correct UART clocks on
 Exynos7885

The clocks in the serial UART nodes were swapped by mistake on
Exynos7885. This only worked correctly because of a mistake in the clock
driver which has been fixed. With the fixed clock driver in place, the
baudrate of the UARTs get miscalculated. Fix this by correcting the
clocks in the dtsi.

Fixes: 06874015327b ("arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC")
Signed-off-by: David Virag <virag.david003@gmail.com>
Link: https://lore.kernel.org/r/20220526055840.45209-3-virag.david003@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 arch/arm64/boot/dts/exynos/exynos7885.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
index 3170661f5b672..9c233c56558ce 100644
--- a/arch/arm64/boot/dts/exynos/exynos7885.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
@@ -280,8 +280,8 @@
 			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&uart0_bus>;
-			clocks = <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>,
-				 <&cmu_peri CLK_GOUT_UART0_PCLK>;
+			clocks = <&cmu_peri CLK_GOUT_UART0_PCLK>,
+				 <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>;
 			clock-names = "uart", "clk_uart_baud0";
 			samsung,uart-fifosize = <64>;
 			status = "disabled";
@@ -293,8 +293,8 @@
 			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&uart1_bus>;
-			clocks = <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>,
-				 <&cmu_peri CLK_GOUT_UART1_PCLK>;
+			clocks = <&cmu_peri CLK_GOUT_UART1_PCLK>,
+				 <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>;
 			clock-names = "uart", "clk_uart_baud0";
 			samsung,uart-fifosize = <256>;
 			status = "disabled";
@@ -306,8 +306,8 @@
 			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&uart2_bus>;
-			clocks = <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>,
-				 <&cmu_peri CLK_GOUT_UART2_PCLK>;
+			clocks = <&cmu_peri CLK_GOUT_UART2_PCLK>,
+				 <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>;
 			clock-names = "uart", "clk_uart_baud0";
 			samsung,uart-fifosize = <256>;
 			status = "disabled";
-- 
GitLab


From c4c79525042a4a7df96b73477feaf232fe44ae81 Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Mon, 23 May 2022 18:55:13 +0400
Subject: [PATCH 0215/1731] ARM: exynos: Fix refcount leak in exynos_map_pmu

of_find_matching_node() returns a node pointer with refcount
incremented, we should use of_node_put() on it when not need anymore.
Add missing of_node_put() to avoid refcount leak.
of_node_put() checks null pointer.

Fixes: fce9e5bb2526 ("ARM: EXYNOS: Add support for mapping PMU base address via DT")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Link: https://lore.kernel.org/r/20220523145513.12341-1-linmq006@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 arch/arm/mach-exynos/exynos.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 8b48326be9fd5..51a247ca4da8c 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -149,6 +149,7 @@ static void exynos_map_pmu(void)
 	np = of_find_matching_node(NULL, exynos_dt_pmu_match);
 	if (np)
 		pmu_base_addr = of_iomap(np, 0);
+	of_node_put(np);
 }
 
 static void __init exynos_init_irq(void)
-- 
GitLab


From 67c7fc6cd915d809be4de2eed323aa5f2205c52f Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Tue, 10 May 2022 11:29:13 +0200
Subject: [PATCH 0216/1731] memory: omap-gpmc: OMAP_GPMC should depend on
 ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3

The Texas Instruments OMAP General Purpose Memory Controller (GPMC) is
only present on TI OMAP2/3/4/5, Keystone, AM33xx, AM43x, DRA7xx, TI81xx,
and K3 SoCs.  Hence add a dependency on ARCH_OMAP2PLUS || ARCH_KEYSTONE
|| ARCH_K3, to prevent asking the user about this driver when
configuring a kernel without OMAP2+, Keystone, or K3 SoC family support.

Fixes: be34f45f0d4aa91c ("memory: omap-gpmc: Make OMAP_GPMC config visible and selectable")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/f6780f572f882ed6ab5934321942cf2b412bf8d1.1652174849.git.geert+renesas@glider.be
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 drivers/memory/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index b7800b37af78a..ac1a411648d86 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -105,6 +105,7 @@ config TI_EMIF
 config OMAP_GPMC
 	tristate "Texas Instruments OMAP SoC GPMC driver"
 	depends on OF_ADDRESS
+	depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST
 	select GPIOLIB
 	help
 	  This driver is for the General Purpose Memory Controller (GPMC)
-- 
GitLab


From 038ae37c510fd57cbc543ac82db1e7b23b28557a Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Wed, 1 Jun 2022 16:01:18 +0400
Subject: [PATCH 0217/1731] memory: mtk-smi: add missing put_device() call in
 mtk_smi_device_link_common

The reference taken by 'of_find_device_by_node()' must be released when
not needed anymore.
Add the corresponding 'put_device()' in the error handling paths.

Fixes: 47404757702e ("memory: mtk-smi: Add device link for smi-sub-common")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Link: https://lore.kernel.org/r/20220601120118.60225-1-linmq006@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 drivers/memory/mtk-smi.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index 86a3d34f418e8..4c5154e0bf00c 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -404,13 +404,16 @@ static int mtk_smi_device_link_common(struct device *dev, struct device **com_de
 	of_node_put(smi_com_node);
 	if (smi_com_pdev) {
 		/* smi common is the supplier, Make sure it is ready before */
-		if (!platform_get_drvdata(smi_com_pdev))
+		if (!platform_get_drvdata(smi_com_pdev)) {
+			put_device(&smi_com_pdev->dev);
 			return -EPROBE_DEFER;
+		}
 		smi_com_dev = &smi_com_pdev->dev;
 		link = device_link_add(dev, smi_com_dev,
 				       DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
 		if (!link) {
 			dev_err(dev, "Unable to link smi-common dev\n");
+			put_device(&smi_com_pdev->dev);
 			return -ENODEV;
 		}
 		*com_dev = smi_com_dev;
-- 
GitLab


From 1332661e09304b7b8e84e5edc11811ba08d12abe Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Thu, 2 Jun 2022 08:17:21 +0400
Subject: [PATCH 0218/1731] memory: samsung: exynos5422-dmc: Fix refcount leak
 in of_get_dram_timings

of_parse_phandle() returns a node pointer with refcount
incremented, we should use of_node_put() on it when not need anymore.
This function doesn't call of_node_put() in some error paths.
To unify the structure, Add put_node label and goto it on errors.

Fixes: 6e7674c3c6df ("memory: Add DMC driver for Exynos5422")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Reviewed-by: Lukasz Luba <lukasz.luba@arm.com>
Link: https://lore.kernel.org/r/20220602041721.64348-1-linmq006@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 drivers/memory/samsung/exynos5422-dmc.c | 29 +++++++++++++++----------
 1 file changed, 18 insertions(+), 11 deletions(-)

diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c
index 4733e7898ffe5..c491cd549644f 100644
--- a/drivers/memory/samsung/exynos5422-dmc.c
+++ b/drivers/memory/samsung/exynos5422-dmc.c
@@ -1187,33 +1187,39 @@ static int of_get_dram_timings(struct exynos5_dmc *dmc)
 
 	dmc->timing_row = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
 					     sizeof(u32), GFP_KERNEL);
-	if (!dmc->timing_row)
-		return -ENOMEM;
+	if (!dmc->timing_row) {
+		ret = -ENOMEM;
+		goto put_node;
+	}
 
 	dmc->timing_data = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
 					      sizeof(u32), GFP_KERNEL);
-	if (!dmc->timing_data)
-		return -ENOMEM;
+	if (!dmc->timing_data) {
+		ret = -ENOMEM;
+		goto put_node;
+	}
 
 	dmc->timing_power = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
 					       sizeof(u32), GFP_KERNEL);
-	if (!dmc->timing_power)
-		return -ENOMEM;
+	if (!dmc->timing_power) {
+		ret = -ENOMEM;
+		goto put_node;
+	}
 
 	dmc->timings = of_lpddr3_get_ddr_timings(np_ddr, dmc->dev,
 						 DDR_TYPE_LPDDR3,
 						 &dmc->timings_arr_size);
 	if (!dmc->timings) {
-		of_node_put(np_ddr);
 		dev_warn(dmc->dev, "could not get timings from DT\n");
-		return -EINVAL;
+		ret = -EINVAL;
+		goto put_node;
 	}
 
 	dmc->min_tck = of_lpddr3_get_min_tck(np_ddr, dmc->dev);
 	if (!dmc->min_tck) {
-		of_node_put(np_ddr);
 		dev_warn(dmc->dev, "could not get tck from DT\n");
-		return -EINVAL;
+		ret = -EINVAL;
+		goto put_node;
 	}
 
 	/* Sorted array of OPPs with frequency ascending */
@@ -1227,13 +1233,14 @@ static int of_get_dram_timings(struct exynos5_dmc *dmc)
 					     clk_period_ps);
 	}
 
-	of_node_put(np_ddr);
 
 	/* Take the highest frequency's timings as 'bypass' */
 	dmc->bypass_timing_row = dmc->timing_row[idx - 1];
 	dmc->bypass_timing_data = dmc->timing_data[idx - 1];
 	dmc->bypass_timing_power = dmc->timing_power[idx - 1];
 
+put_node:
+	of_node_put(np_ddr);
 	return ret;
 }
 
-- 
GitLab


From ba79c5e45eecb9e009eca7f5da224f6e42bd4fcb Mon Sep 17 00:00:00 2001
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Date: Mon, 30 May 2022 14:57:50 +0300
Subject: [PATCH 0219/1731] MAINTAINERS: Update Intel pin control to Supported

The actual status of the code is Supported.

Reported-by: dave.hansen@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index a6d3bd9d2a8d0..bb033cf3dd323 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15730,7 +15730,7 @@ F:	drivers/pinctrl/freescale/
 PIN CONTROLLER - INTEL
 M:	Mika Westerberg <mika.westerberg@linux.intel.com>
 M:	Andy Shevchenko <andy@kernel.org>
-S:	Maintained
+S:	Supported
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git
 F:	drivers/pinctrl/intel/
 
-- 
GitLab


From 21b511ddee09a78909035ec47a6a594349fe3296 Mon Sep 17 00:00:00 2001
From: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Date: Mon, 6 Jun 2022 11:55:25 +0530
Subject: [PATCH 0220/1731] spi: spi-cadence: Fix SPI CS gets toggling
 sporadically

As part of unprepare_transfer_hardware, SPI controller will be disabled
which will indirectly deassert the CS line. This will create a problem
in some of the devices where message will be transferred with
cs_change flag set(CS should not be deasserted).
As per SPI controller implementation, if SPI controller is disabled then
all output enables are inactive and all pins are set to input mode which
means CS will go to default state high(deassert). This leads to an issue
when core explicitly ask not to deassert the CS (cs_change = 1). This
patch fix the above issue by checking the Slave select status bits from
configuration register before disabling the SPI.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Link: https://lore.kernel.org/r/20220606062525.18447-1-amit.kumar-mahapatra@xilinx.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 drivers/spi/spi-cadence.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c
index a23d4f6329f50..00f0d1b3a7222 100644
--- a/drivers/spi/spi-cadence.c
+++ b/drivers/spi/spi-cadence.c
@@ -69,6 +69,7 @@
 #define CDNS_SPI_BAUD_DIV_SHIFT		3 /* Baud rate divisor shift in CR */
 #define CDNS_SPI_SS_SHIFT		10 /* Slave Select field shift in CR */
 #define CDNS_SPI_SS0			0x1 /* Slave Select zero */
+#define CDNS_SPI_NOSS			0x3C /* No Slave select */
 
 /*
  * SPI Interrupt Registers bit Masks
@@ -450,15 +451,20 @@ static int cdns_prepare_transfer_hardware(struct spi_master *master)
  * @master:	Pointer to the spi_master structure which provides
  *		information about the controller.
  *
- * This function disables the SPI master controller.
+ * This function disables the SPI master controller when no slave selected.
  *
  * Return:	0 always
  */
 static int cdns_unprepare_transfer_hardware(struct spi_master *master)
 {
 	struct cdns_spi *xspi = spi_master_get_devdata(master);
+	u32 ctrl_reg;
 
-	cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
+	/* Disable the SPI if slave is deselected */
+	ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
+	ctrl_reg = (ctrl_reg & CDNS_SPI_CR_SSCTRL) >>  CDNS_SPI_SS_SHIFT;
+	if (ctrl_reg == CDNS_SPI_NOSS)
+		cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
 
 	return 0;
 }
-- 
GitLab


From 7b40322f7183a92c4303457528ae7cda571c60b9 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Fri, 27 May 2022 11:11:43 +0200
Subject: [PATCH 0221/1731] spi: cadence: Detect transmit FIFO depth

The depth of the transmit FIFO for the Cadence SPI controller is currently
hardcoded to 128. But the depth is a synthesis configuration parameter of
the core and can vary between different SoCs.

If the configured FIFO size is less than 128 the driver will busy loop in
the cdns_spi_fill_tx_fifo() function waiting for FIFO space to become
available.

Depending on the length and speed of the transfer it can spin for a
significant amount of time. The cdns_spi_fill_tx_fifo() function is called
from the drivers interrupt handler, so it can leave interrupts disabled for
a prolonged amount of time.

In addition the read FIFO will also overflow and data will be discarded.

To avoid this detect the actual size of the FIFO and use that rather than
the hardcoded value.

To detect the FIFO size the FIFO threshold register is used. The register
is sized so that it can hold FIFO size - 1 as its maximum value. Bits that
are not needed to hold the threshold value will always read 0. By writing
0xffff to the register and then reading back the value in the register we
get the FIFO size.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Link: https://lore.kernel.org/r/20220527091143.3780378-1-lars@metafoo.de
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 drivers/spi/spi-cadence.c | 27 +++++++++++++++++++++++----
 1 file changed, 23 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c
index 00f0d1b3a7222..31d778e9d255b 100644
--- a/drivers/spi/spi-cadence.c
+++ b/drivers/spi/spi-cadence.c
@@ -93,9 +93,6 @@
 #define CDNS_SPI_ER_ENABLE	0x00000001 /* SPI Enable Bit Mask */
 #define CDNS_SPI_ER_DISABLE	0x0 /* SPI Disable Bit Mask */
 
-/* SPI FIFO depth in bytes */
-#define CDNS_SPI_FIFO_DEPTH	128
-
 /* Default number of chip select lines */
 #define CDNS_SPI_DEFAULT_NUM_CS		4
 
@@ -111,6 +108,7 @@
  * @rx_bytes:		Number of bytes requested
  * @dev_busy:		Device busy flag
  * @is_decoded_cs:	Flag for decoder property set or not
+ * @tx_fifo_depth:	Depth of the TX FIFO
  */
 struct cdns_spi {
 	void __iomem *regs;
@@ -124,6 +122,7 @@ struct cdns_spi {
 	int rx_bytes;
 	u8 dev_busy;
 	u32 is_decoded_cs;
+	unsigned int tx_fifo_depth;
 };
 
 /* Macros for the SPI controller read/write */
@@ -305,7 +304,7 @@ static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)
 {
 	unsigned long trans_cnt = 0;
 
-	while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
+	while ((trans_cnt < xspi->tx_fifo_depth) &&
 	       (xspi->tx_bytes > 0)) {
 
 		/* When xspi in busy condition, bytes may send failed,
@@ -469,6 +468,24 @@ static int cdns_unprepare_transfer_hardware(struct spi_master *master)
 	return 0;
 }
 
+/**
+ * cdns_spi_detect_fifo_depth - Detect the FIFO depth of the hardware
+ * @xspi:	Pointer to the cdns_spi structure
+ *
+ * The depth of the TX FIFO is a synthesis configuration parameter of the SPI
+ * IP. The FIFO threshold register is sized so that its maximum value can be the
+ * FIFO size - 1. This is used to detect the size of the FIFO.
+ */
+static void cdns_spi_detect_fifo_depth(struct cdns_spi *xspi)
+{
+	/* The MSBs will get truncated giving us the size of the FIFO */
+	cdns_spi_write(xspi, CDNS_SPI_THLD, 0xffff);
+	xspi->tx_fifo_depth = cdns_spi_read(xspi, CDNS_SPI_THLD) + 1;
+
+	/* Reset to default */
+	cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
+}
+
 /**
  * cdns_spi_probe - Probe method for the SPI driver
  * @pdev:	Pointer to the platform_device structure
@@ -541,6 +558,8 @@ static int cdns_spi_probe(struct platform_device *pdev)
 	if (ret < 0)
 		xspi->is_decoded_cs = 0;
 
+	cdns_spi_detect_fifo_depth(xspi);
+
 	/* SPI controller initializations */
 	cdns_spi_init_hw(xspi);
 
-- 
GitLab


From 2283679f4c468df367830b7eb8f22d48a6940e19 Mon Sep 17 00:00:00 2001
From: Patrice Chotard <patrice.chotard@foss.st.com>
Date: Thu, 2 Jun 2022 11:10:22 +0200
Subject: [PATCH 0222/1731] spi: spi-mem: Fix spi_mem_poll_status()

In spi_mem_exec_op(), in case cs_gpiod descriptor is set, exec_op()
callback can't be used.
The same must be applied in spi_mem_poll_status(), poll_status()
callback can't be used, we must use the legacy path using
read_poll_timeout().

Tested on STM32mp257c-ev1 specific evaluation board on which a
spi-nand was mounted instead of a spi-nor.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20220602091022.358127-1-patrice.chotard@foss.st.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 drivers/spi/spi-mem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index e8de4f5017cdc..0c79193d96972 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -808,7 +808,7 @@ int spi_mem_poll_status(struct spi_mem *mem,
 	    op->data.dir != SPI_MEM_DATA_IN)
 		return -EINVAL;
 
-	if (ctlr->mem_ops && ctlr->mem_ops->poll_status) {
+	if (ctlr->mem_ops && ctlr->mem_ops->poll_status && !mem->spi->cs_gpiod) {
 		ret = spi_mem_access_start(mem);
 		if (ret)
 			return ret;
-- 
GitLab


From 6aa27071e4354c351d98e345fc888b70f335f185 Mon Sep 17 00:00:00 2001
From: Rob Herring <robh@kernel.org>
Date: Wed, 25 May 2022 20:41:41 -0500
Subject: [PATCH 0223/1731] spi: dt-bindings: Fix unevaluatedProperties
 warnings in examples

The 'unevaluatedProperties' schema checks is not fully working and doesn't
catch some cases where there's a $ref to another schema. A fix is pending,
but results in new warnings in examples.

'spi-max-frequency' is supposed to be a per SPI peripheral device property,
not a SPI controller property, so drop it.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220526014141.2872567-1-robh@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml | 1 -
 Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml | 1 -
 2 files changed, 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
index ece261b8e963f..7326c0a28d160 100644
--- a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
@@ -47,6 +47,5 @@ examples:
         clocks = <&clkcfg CLK_SPI0>;
         interrupt-parent = <&plic>;
         interrupts = <54>;
-        spi-max-frequency = <25000000>;
     };
 ...
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
index e2c7b934c50d5..78ceb9d67754f 100644
--- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
@@ -110,7 +110,6 @@ examples:
         pinctrl-names = "default";
         pinctrl-0 = <&qup_spi1_default>;
         interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
-        spi-max-frequency = <50000000>;
         #address-cells = <1>;
         #size-cells = <0>;
     };
-- 
GitLab


From b7fb767b1658b3154da712844cf834c5d66ddb2b Mon Sep 17 00:00:00 2001
From: "jason-jh.lin" <jason-jh.lin@mediatek.com>
Date: Thu, 26 May 2022 18:21:22 +0800
Subject: [PATCH 0224/1731] drm/mediatek: Add DSC support for mediatek-drm

DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
video bit stream.

Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220526102126.19756-2-jason-jh.lin@mediatek.com/
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 47 +++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  1 +
 2 files changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 5d7504a72b11c..2af1641a49f21 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -40,6 +40,12 @@
 #define DITHER_LSB_ERR_SHIFT_G(x)		(((x) & 0x7) << 12)
 #define DITHER_ADD_LSHIFT_G(x)			(((x) & 0x7) << 4)
 
+#define DISP_REG_DSC_CON			0x0000
+#define DSC_EN					BIT(0)
+#define DSC_DUAL_INOUT				BIT(2)
+#define DSC_BYPASS				BIT(4)
+#define DSC_UFOE_SEL				BIT(16)
+
 #define DISP_REG_OD_EN				0x0000
 #define DISP_REG_OD_CFG				0x0020
 #define OD_RELAYMODE				BIT(0)
@@ -181,6 +187,36 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc,
 			      DISP_DITHERING, cmdq_pkt);
 }
 
+static void mtk_dsc_config(struct device *dev, unsigned int w,
+			   unsigned int h, unsigned int vrefresh,
+			   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	/* dsc bypass mode */
+	mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_BYPASS);
+	mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_UFOE_SEL);
+	mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_DUAL_INOUT);
+}
+
+static void mtk_dsc_start(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	/* write with mask to reserve the value set in mtk_dsc_config */
+	mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN);
+}
+
+static void mtk_dsc_stop(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
+}
+
 static void mtk_od_config(struct device *dev, unsigned int w,
 			  unsigned int h, unsigned int vrefresh,
 			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -270,6 +306,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
 	.stop = mtk_dpi_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_dsc = {
+	.clk_enable = mtk_ddp_clk_enable,
+	.clk_disable = mtk_ddp_clk_disable,
+	.config = mtk_dsc_config,
+	.start = mtk_dsc_start,
+	.stop = mtk_dsc_stop,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_dsi = {
 	.start = mtk_dsi_ddp_start,
 	.stop = mtk_dsi_ddp_stop,
@@ -343,6 +387,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_CCORR] = "ccorr",
 	[MTK_DISP_COLOR] = "color",
 	[MTK_DISP_DITHER] = "dither",
+	[MTK_DISP_DSC] = "dsc",
 	[MTK_DISP_GAMMA] = "gamma",
 	[MTK_DISP_MUTEX] = "mutex",
 	[MTK_DISP_OD] = "od",
@@ -373,6 +418,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DITHER]		= { MTK_DISP_DITHER,	0, &ddp_dither },
 	[DDP_COMPONENT_DPI0]		= { MTK_DPI,		0, &ddp_dpi },
 	[DDP_COMPONENT_DPI1]		= { MTK_DPI,		1, &ddp_dpi },
+	[DDP_COMPONENT_DSC0]		= { MTK_DISP_DSC,	0, &ddp_dsc },
+	[DDP_COMPONENT_DSC1]		= { MTK_DISP_DSC,	1, &ddp_dsc },
 	[DDP_COMPONENT_DSI0]		= { MTK_DSI,		0, &ddp_dsi },
 	[DDP_COMPONENT_DSI1]		= { MTK_DSI,		1, &ddp_dsi },
 	[DDP_COMPONENT_DSI2]		= { MTK_DSI,		2, &ddp_dsi },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 1cbc6332282dc..238776bd3b723 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_CCORR,
 	MTK_DISP_COLOR,
 	MTK_DISP_DITHER,
+	MTK_DISP_DSC,
 	MTK_DISP_GAMMA,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
-- 
GitLab


From bd448b8867b7e0c30ecd09f944a86018596fa4ad Mon Sep 17 00:00:00 2001
From: "jason-jh.lin" <jason-jh.lin@mediatek.com>
Date: Thu, 26 May 2022 18:21:23 +0800
Subject: [PATCH 0225/1731] drm/mediatek: Add MERGE support for mediatek-drm

Add MERGE engine file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.

Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220526102126.19756-3-jason-jh.lin@mediatek.com/
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/Makefile           |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
 drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 246 ++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  16 ++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
 7 files changed, 276 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 29098d7c8307c..a38e88e82d123 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -4,6 +4,7 @@ mediatek-drm-y := mtk_disp_aal.o \
 		  mtk_disp_ccorr.o \
 		  mtk_disp_color.o \
 		  mtk_disp_gamma.o \
+		  mtk_disp_merge.o \
 		  mtk_disp_ovl.o \
 		  mtk_disp_rdma.o \
 		  mtk_drm_crtc.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 763be99e8d33e..f13a6f5d512aa 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -55,6 +55,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state, bool
 void mtk_gamma_start(struct device *dev);
 void mtk_gamma_stop(struct device *dev);
 
+int mtk_merge_clk_enable(struct device *dev);
+void mtk_merge_clk_disable(struct device *dev);
+void mtk_merge_config(struct device *dev, unsigned int width,
+		      unsigned int height, unsigned int vrefresh,
+		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_start(struct device *dev);
+void mtk_merge_stop(struct device *dev);
+
 void mtk_ovl_bgclr_in_on(struct device *dev);
 void mtk_ovl_bgclr_in_off(struct device *dev);
 void mtk_ovl_bypass_shadow(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
new file mode 100644
index 0000000000000..45face6381531
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_MERGE_CTRL		0x000
+#define MERGE_EN				1
+#define DISP_REG_MERGE_CFG_0		0x010
+#define DISP_REG_MERGE_CFG_4		0x020
+#define DISP_REG_MERGE_CFG_10		0x038
+/* no swap */
+#define SWAP_MODE				0
+#define FLD_SWAP_MODE				GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_12		0x040
+#define CFG_10_10_1PI_2PO_BUF_MODE		6
+#define CFG_10_10_2PI_2PO_BUF_MODE		8
+#define FLD_CFG_MERGE_MODE			GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_24		0x070
+#define DISP_REG_MERGE_CFG_25		0x074
+#define DISP_REG_MERGE_CFG_36		0x0a0
+#define ULTRA_EN				BIT(0)
+#define PREULTRA_EN				BIT(4)
+#define DISP_REG_MERGE_CFG_37		0x0a4
+/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
+#define BUFFER_MODE				3
+#define FLD_BUFFER_MODE				GENMASK(1, 0)
+/*
+ * For the ultra and preultra settings, 6us ~ 9us is experience value
+ * and the maximum frequency of mmsys clock is 594MHz.
+ */
+#define DISP_REG_MERGE_CFG_40		0x0b0
+/* 6 us, 594M pixel/sec */
+#define ULTRA_TH_LOW				(6 * 594)
+/* 8 us, 594M pixel/sec */
+#define ULTRA_TH_HIGH				(8 * 594)
+#define FLD_ULTRA_TH_LOW			GENMASK(15, 0)
+#define FLD_ULTRA_TH_HIGH			GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_41		0x0b4
+/* 8 us, 594M pixel/sec */
+#define PREULTRA_TH_LOW				(8 * 594)
+/* 9 us, 594M pixel/sec */
+#define PREULTRA_TH_HIGH			(9 * 594)
+#define FLD_PREULTRA_TH_LOW			GENMASK(15, 0)
+#define FLD_PREULTRA_TH_HIGH			GENMASK(31, 16)
+
+struct mtk_disp_merge {
+	void __iomem			*regs;
+	struct clk			*clk;
+	struct clk			*async_clk;
+	struct cmdq_client_reg		cmdq_reg;
+	bool				fifo_en;
+};
+
+void mtk_merge_start(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_stop(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
+				   struct cmdq_pkt *cmdq_pkt)
+{
+	mtk_ddp_write(cmdq_pkt, ULTRA_EN | PREULTRA_EN,
+		      &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36);
+
+	mtk_ddp_write_mask(cmdq_pkt, BUFFER_MODE,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37,
+			   FLD_BUFFER_MODE);
+
+	mtk_ddp_write_mask(cmdq_pkt, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40,
+			   FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
+
+	mtk_ddp_write_mask(cmdq_pkt, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41,
+			   FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH);
+}
+
+void mtk_merge_config(struct device *dev, unsigned int w,
+		      unsigned int h, unsigned int vrefresh,
+		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+	unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
+
+	if (!h || !w) {
+		dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
+		return;
+	}
+
+	if (priv->fifo_en) {
+		mtk_merge_fifo_setting(priv, cmdq_pkt);
+		mode = CFG_10_10_2PI_2PO_BUF_MODE;
+	}
+
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_0);
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_4);
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_24);
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_25);
+	mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
+	mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE);
+}
+
+int mtk_merge_clk_enable(struct device *dev)
+{
+	int ret = 0;
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	ret = clk_prepare_enable(priv->clk);
+	if (ret) {
+		dev_err(dev, "merge clk prepare enable failed\n");
+		return ret;
+	}
+
+	ret = clk_prepare_enable(priv->async_clk);
+	if (ret) {
+		/* should clean up the state of priv->clk */
+		clk_disable_unprepare(priv->clk);
+
+		dev_err(dev, "async clk prepare enable failed\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+void mtk_merge_clk_disable(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	clk_disable_unprepare(priv->async_clk);
+	clk_disable_unprepare(priv->clk);
+}
+
+static int mtk_disp_merge_bind(struct device *dev, struct device *master,
+			       void *data)
+{
+	return 0;
+}
+
+static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
+				  void *data)
+{
+}
+
+static const struct component_ops mtk_disp_merge_component_ops = {
+	.bind	= mtk_disp_merge_bind,
+	.unbind = mtk_disp_merge_unbind,
+};
+
+static int mtk_disp_merge_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct mtk_disp_merge *priv;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->regs)) {
+		dev_err(dev, "failed to ioremap merge\n");
+		return PTR_ERR(priv->regs);
+	}
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(dev, "failed to get merge clk\n");
+		return PTR_ERR(priv->clk);
+	}
+
+	priv->async_clk = devm_clk_get_optional(dev, "merge_async");
+	if (IS_ERR(priv->async_clk)) {
+		dev_err(dev, "failed to get merge async clock\n");
+		return PTR_ERR(priv->async_clk);
+	}
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+	if (ret)
+		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+	priv->fifo_en = of_property_read_bool(dev->of_node,
+					      "mediatek,merge-fifo-en");
+
+	platform_set_drvdata(pdev, priv);
+
+	ret = component_add(dev, &mtk_disp_merge_component_ops);
+	if (ret != 0)
+		dev_err(dev, "Failed to add component: %d\n", ret);
+
+	return ret;
+}
+
+static int mtk_disp_merge_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &mtk_disp_merge_component_ops);
+
+	return 0;
+}
+
+static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
+	{ .compatible = "mediatek,mt8195-disp-merge", },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
+
+struct platform_driver mtk_disp_merge_driver = {
+	.probe = mtk_disp_merge_probe,
+	.remove = mtk_disp_merge_remove,
+	.driver = {
+		.name = "mediatek-disp-merge",
+		.owner = THIS_MODULE,
+		.of_match_table = mtk_disp_merge_driver_dt_match,
+	},
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 2af1641a49f21..aefd64a370359 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -328,6 +328,14 @@ static const struct mtk_ddp_comp_funcs ddp_gamma = {
 	.stop = mtk_gamma_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_merge = {
+	.clk_enable = mtk_merge_clk_enable,
+	.clk_disable = mtk_merge_clk_disable,
+	.start = mtk_merge_start,
+	.stop = mtk_merge_stop,
+	.config = mtk_merge_config,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_od = {
 	.clk_enable = mtk_ddp_clk_enable,
 	.clk_disable = mtk_ddp_clk_disable,
@@ -389,6 +397,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_DITHER] = "dither",
 	[MTK_DISP_DSC] = "dsc",
 	[MTK_DISP_GAMMA] = "gamma",
+	[MTK_DISP_MERGE] = "merge",
 	[MTK_DISP_MUTEX] = "mutex",
 	[MTK_DISP_OD] = "od",
 	[MTK_DISP_OVL] = "ovl",
@@ -425,6 +434,12 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DSI2]		= { MTK_DSI,		2, &ddp_dsi },
 	[DDP_COMPONENT_DSI3]		= { MTK_DSI,		3, &ddp_dsi },
 	[DDP_COMPONENT_GAMMA]		= { MTK_DISP_GAMMA,	0, &ddp_gamma },
+	[DDP_COMPONENT_MERGE0]		= { MTK_DISP_MERGE,	0, &ddp_merge },
+	[DDP_COMPONENT_MERGE1]		= { MTK_DISP_MERGE,	1, &ddp_merge },
+	[DDP_COMPONENT_MERGE2]		= { MTK_DISP_MERGE,	2, &ddp_merge },
+	[DDP_COMPONENT_MERGE3]		= { MTK_DISP_MERGE,	3, &ddp_merge },
+	[DDP_COMPONENT_MERGE4]		= { MTK_DISP_MERGE,	4, &ddp_merge },
+	[DDP_COMPONENT_MERGE5]		= { MTK_DISP_MERGE,	5, &ddp_merge },
 	[DDP_COMPONENT_OD0]		= { MTK_DISP_OD,	0, &ddp_od },
 	[DDP_COMPONENT_OD1]		= { MTK_DISP_OD,	1, &ddp_od },
 	[DDP_COMPONENT_OVL0]		= { MTK_DISP_OVL,	0, &ddp_ovl },
@@ -527,6 +542,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
 	    type == MTK_DISP_CCORR ||
 	    type == MTK_DISP_COLOR ||
 	    type == MTK_DISP_GAMMA ||
+	    type == MTK_DISP_MERGE ||
 	    type == MTK_DISP_OVL ||
 	    type == MTK_DISP_OVL_2L ||
 	    type == MTK_DISP_PWM ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 238776bd3b723..a43d82c12a9a7 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_DITHER,
 	MTK_DISP_DSC,
 	MTK_DISP_GAMMA,
+	MTK_DISP_MERGE,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
 	MTK_DISP_OVL,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 6abe6bcacbdc6..5c1c657ceb6e9 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -628,7 +628,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		private->comp_node[comp_id] = of_node_get(node);
 
 		/*
-		 * Currently only the AAL, CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI
+		 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
 		 * blocks have separate component platform drivers and initialize their own
 		 * DDP component structure. The others are initialized here.
 		 */
@@ -636,6 +636,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		    comp_type == MTK_DISP_CCORR ||
 		    comp_type == MTK_DISP_COLOR ||
 		    comp_type == MTK_DISP_GAMMA ||
+		    comp_type == MTK_DISP_MERGE ||
 		    comp_type == MTK_DISP_OVL ||
 		    comp_type == MTK_DISP_OVL_2L ||
 		    comp_type == MTK_DISP_RDMA ||
@@ -734,6 +735,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_disp_ccorr_driver,
 	&mtk_disp_color_driver,
 	&mtk_disp_gamma_driver,
+	&mtk_disp_merge_driver,
 	&mtk_disp_ovl_driver,
 	&mtk_disp_rdma_driver,
 	&mtk_dpi_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 3e7d1e6fbe010..a58cebd01d351 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -50,6 +50,7 @@ extern struct platform_driver mtk_disp_aal_driver;
 extern struct platform_driver mtk_disp_ccorr_driver;
 extern struct platform_driver mtk_disp_color_driver;
 extern struct platform_driver mtk_disp_gamma_driver;
+extern struct platform_driver mtk_disp_merge_driver;
 extern struct platform_driver mtk_disp_ovl_driver;
 extern struct platform_driver mtk_disp_rdma_driver;
 extern struct platform_driver mtk_dpi_driver;
-- 
GitLab


From 7266e90a51a32722a94daa3cb5b8fa278059e49e Mon Sep 17 00:00:00 2001
From: "jason-jh.lin" <jason-jh.lin@mediatek.com>
Date: Thu, 26 May 2022 18:21:24 +0800
Subject: [PATCH 0226/1731] drm/mediatek: Add mediatek-drm of vdosys0 support
 for mt8195

1. Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
2. Add get driver data function to identify which vdosys by io_start.

Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220526102126.19756-4-jason-jh.lin@mediatek.com/
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c |   6 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 150 +++++++++++++++++++++--
 drivers/gpu/drm/mediatek/mtk_drm_drv.h   |   6 +
 3 files changed, 153 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 1be4caf9ff963..a000bba04e015 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -372,6 +372,10 @@ static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
 	.fifo_size = 5 * SZ_1K,
 };
 
+static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
+	.fifo_size = 1920,
+};
+
 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt2701-disp-rdma",
 	  .data = &mt2701_rdma_driver_data},
@@ -381,6 +385,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	  .data = &mt8183_rdma_driver_data},
 	{ .compatible = "mediatek,mt8192-disp-rdma",
 	  .data = &mt8192_rdma_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = &mt8195_rdma_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 5c1c657ceb6e9..eb477c17a0ce0 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -4,6 +4,8 @@
  * Author: YT SHEN <yt.shen@mediatek.com>
  */
 
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/component.h>
 #include <linux/iommu.h>
 #include <linux/module.h>
@@ -195,6 +197,19 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
 	DDP_COMPONENT_DPI0,
 };
 
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
+	DDP_COMPONENT_OVL0,
+	DDP_COMPONENT_RDMA0,
+	DDP_COMPONENT_COLOR0,
+	DDP_COMPONENT_CCORR,
+	DDP_COMPONENT_AAL0,
+	DDP_COMPONENT_GAMMA,
+	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DSC0,
+	DDP_COMPONENT_MERGE0,
+	DDP_COMPONENT_DP_INTF0,
+};
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.main_path = mt2701_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -203,6 +218,13 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.shadow_register = true,
 };
 
+static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt2701_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
 	.main_path = mt7623_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
@@ -211,6 +233,13 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
 	.shadow_register = true,
 };
 
+static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt7623_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
 	.main_path = mt2712_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
@@ -220,11 +249,25 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
 	.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
 };
 
+static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt2712_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
 	.main_path = mt8167_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
 };
 
+static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8167_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.main_path = mt8173_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
@@ -232,6 +275,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8173_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.main_path = mt8183_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
@@ -239,6 +289,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8183_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 	.main_path = mt8186_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8186_mtk_ddp_main),
@@ -246,6 +303,13 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8186_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.main_path = mt8192_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
@@ -253,6 +317,31 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8192_mmsys_driver_data,
+	},
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+	.io_start = 0x1c01a000,
+	.main_path = mt8195_mtk_ddp_main,
+	.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+	.io_start = 0x1c100000,
+};
+
+static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8195_vdosys0_driver_data,
+		&mt8195_vdosys1_driver_data,
+	},
+};
+
 static int mtk_drm_kms_init(struct drm_device *drm)
 {
 	struct mtk_drm_private *private = drm->dev_private;
@@ -470,12 +559,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_DITHER },
 	{ .compatible = "mediatek,mt8183-disp-dither",
 	  .data = (void *)MTK_DISP_DITHER },
+	{ .compatible = "mediatek,mt8195-disp-dsc",
+	  .data = (void *)MTK_DISP_DSC },
 	{ .compatible = "mediatek,mt8167-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8173-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8183-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
+	{ .compatible = "mediatek,mt8195-disp-merge",
+	  .data = (void *)MTK_DISP_MERGE },
 	{ .compatible = "mediatek,mt2701-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt2712-disp-mutex",
@@ -490,6 +583,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8192-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
+	{ .compatible = "mediatek,mt8195-disp-mutex",
+	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8173-disp-od",
 	  .data = (void *)MTK_DISP_OD },
 	{ .compatible = "mediatek,mt2701-disp-ovl",
@@ -524,6 +619,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8192-disp-rdma",
 	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8173-disp-ufoe",
 	  .data = (void *)MTK_DISP_UFOE },
 	{ .compatible = "mediatek,mt8173-disp-wdma",
@@ -549,30 +646,53 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 
 static const struct of_device_id mtk_drm_of_ids[] = {
 	{ .compatible = "mediatek,mt2701-mmsys",
-	  .data = &mt2701_mmsys_driver_data},
+	  .data = &mt2701_mmsys_match_data},
 	{ .compatible = "mediatek,mt7623-mmsys",
-	  .data = &mt7623_mmsys_driver_data},
+	  .data = &mt7623_mmsys_match_data},
 	{ .compatible = "mediatek,mt2712-mmsys",
-	  .data = &mt2712_mmsys_driver_data},
+	  .data = &mt2712_mmsys_match_data},
 	{ .compatible = "mediatek,mt8167-mmsys",
-	  .data = &mt8167_mmsys_driver_data},
+	  .data = &mt8167_mmsys_match_data},
 	{ .compatible = "mediatek,mt8173-mmsys",
-	  .data = &mt8173_mmsys_driver_data},
+	  .data = &mt8173_mmsys_match_data},
 	{ .compatible = "mediatek,mt8183-mmsys",
-	  .data = &mt8183_mmsys_driver_data},
+	  .data = &mt8183_mmsys_match_data},
 	{ .compatible = "mediatek,mt8186-mmsys",
-	  .data = &mt8186_mmsys_driver_data},
+	  .data = &mt8186_mmsys_match_data},
 	{ .compatible = "mediatek,mt8192-mmsys",
-	  .data = &mt8192_mmsys_driver_data},
+	  .data = &mt8192_mmsys_match_data},
+	{ .compatible = "mediatek,mt8195-mmsys",
+	  .data = &mt8195_mmsys_match_data},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
 
+static int mtk_drm_find_match_data(struct device *dev,
+				   const struct mtk_mmsys_match_data *match_data)
+{
+	int i;
+	struct platform_device *pdev = of_find_device_by_node(dev->parent->of_node);
+	struct resource *res;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(dev, "failed to get parent resource\n");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < match_data->num_drv_data; i++)
+		if (match_data->drv_data[i]->io_start == res->start)
+			return i;
+
+	return -EINVAL;
+}
+
 static int mtk_drm_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct device_node *phandle = dev->parent->of_node;
 	const struct of_device_id *of_id;
+	const struct mtk_mmsys_match_data *match_data;
 	struct mtk_drm_private *private;
 	struct device_node *node;
 	struct component_match *match = NULL;
@@ -593,7 +713,19 @@ static int mtk_drm_probe(struct platform_device *pdev)
 	if (!of_id)
 		return -ENODEV;
 
-	private->data = of_id->data;
+	match_data = of_id->data;
+	if (match_data->num_drv_data > 1) {
+		/* This SoC has multiple mmsys channels */
+		ret = mtk_drm_find_match_data(dev, match_data);
+		if (ret < 0) {
+			dev_err(dev, "Couldn't get match driver data\n");
+			return ret;
+		}
+		private->data = match_data->drv_data[ret];
+	} else {
+		dev_dbg(dev, "Using single mmsys channel\n");
+		private->data = match_data->drv_data[0];
+	}
 
 	/* Iterate over sibling DISP function blocks */
 	for_each_child_of_node(phandle->parent, node) {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index a58cebd01d351..9fc922b1684f5 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -21,6 +21,7 @@ struct drm_property;
 struct regmap;
 
 struct mtk_mmsys_driver_data {
+	const resource_size_t io_start;
 	const enum mtk_ddp_comp_id *main_path;
 	unsigned int main_len;
 	const enum mtk_ddp_comp_id *ext_path;
@@ -31,6 +32,11 @@ struct mtk_mmsys_driver_data {
 	bool shadow_register;
 };
 
+struct mtk_mmsys_match_data {
+	unsigned short num_drv_data;
+	const struct mtk_mmsys_driver_data *drv_data[];
+};
+
 struct mtk_drm_private {
 	struct drm_device *drm;
 	struct device *dma_dev;
-- 
GitLab


From 9c1b06a509dfaf539ced98cecce9e797fb2ee3eb Mon Sep 17 00:00:00 2001
From: "jason-jh.lin" <jason-jh.lin@mediatek.com>
Date: Thu, 26 May 2022 18:21:25 +0800
Subject: [PATCH 0227/1731] drm/mediatek: Add suffix 0 to DDP_COMPONENT_DITHER
 for mt8195 vdosys0

Because mt8195 vdosys0 has 2 DITHER components,
so the suffix 0 need to be added to DDP_COMPONENT_DITHER.

Then DITHER enum will become:
DDP_COMPONENT_DITHER0 and DDP_COMPONENT_DITHER1.

Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220526102126.19756-5-jason-jh.lin@mediatek.com/
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  2 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      | 10 +++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index aefd64a370359..a848ca7e167ae 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -424,7 +424,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_CCORR]		= { MTK_DISP_CCORR,	0, &ddp_ccorr },
 	[DDP_COMPONENT_COLOR0]		= { MTK_DISP_COLOR,	0, &ddp_color },
 	[DDP_COMPONENT_COLOR1]		= { MTK_DISP_COLOR,	1, &ddp_color },
-	[DDP_COMPONENT_DITHER]		= { MTK_DISP_DITHER,	0, &ddp_dither },
+	[DDP_COMPONENT_DITHER0]		= { MTK_DISP_DITHER,	0, &ddp_dither },
 	[DDP_COMPONENT_DPI0]		= { MTK_DPI,		0, &ddp_dpi },
 	[DDP_COMPONENT_DPI1]		= { MTK_DPI,		1, &ddp_dpi },
 	[DDP_COMPONENT_DSC0]		= { MTK_DISP_DSC,	0, &ddp_dsc },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index eb477c17a0ce0..076ef59c0c0b3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -118,7 +118,7 @@ static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = {
 	DDP_COMPONENT_CCORR,
 	DDP_COMPONENT_AAL0,
 	DDP_COMPONENT_GAMMA,
-	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_RDMA0,
 	DDP_COMPONENT_DSI0,
 };
@@ -150,7 +150,7 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {
 	DDP_COMPONENT_CCORR,
 	DDP_COMPONENT_AAL0,
 	DDP_COMPONENT_GAMMA,
-	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_DSI0,
 };
 
@@ -168,7 +168,7 @@ static const enum mtk_ddp_comp_id mt8186_mtk_ddp_main[] = {
 	DDP_COMPONENT_AAL0,
 	DDP_COMPONENT_GAMMA,
 	DDP_COMPONENT_POSTMASK0,
-	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_DSI0,
 };
 
@@ -187,7 +187,7 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
 	DDP_COMPONENT_AAL0,
 	DDP_COMPONENT_GAMMA,
 	DDP_COMPONENT_POSTMASK0,
-	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_DSI0,
 };
 
@@ -204,7 +204,7 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
 	DDP_COMPONENT_CCORR,
 	DDP_COMPONENT_AAL0,
 	DDP_COMPONENT_GAMMA,
-	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_DSC0,
 	DDP_COMPONENT_MERGE0,
 	DDP_COMPONENT_DP_INTF0,
-- 
GitLab


From 1d742694571655e49e11ea8f391bcafaf0f5ee74 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com>
Date: Thu, 2 Jun 2022 13:17:30 -0700
Subject: [PATCH 0228/1731] drm/i915/display/fbc: Do not apply WA 22014263786
 to DG2
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This workaround brings some regressions to DG2 and if really necessary
for DG2 an alternative workaround will be implemented.

BSpec: 54077
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220602201730.199418-1-jose.souza@intel.com
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index bbdc34a23d548..8b807284cde1f 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -813,8 +813,8 @@ static void intel_fbc_program_cfb(struct intel_fbc *fbc)
 
 static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
 {
-	/* Wa_22014263786:icl,jsl,tgl,dg1,rkl,adls,dg2,adlp */
-	if (DISPLAY_VER(fbc->i915) >= 11)
+	/* Wa_22014263786:icl,jsl,tgl,dg1,rkl,adls,adlp */
+	if (DISPLAY_VER(fbc->i915) >= 11 && !IS_DG2(fbc->i915))
 		intel_de_rmw(fbc->i915, ILK_DPFC_CHICKEN(fbc->id), 0,
 			     DPFC_CHICKEN_FORCE_SLB_INVALIDATION);
 }
-- 
GitLab


From 31e70e527806c546a72262f2fc3d982ee23c42d3 Mon Sep 17 00:00:00 2001
From: Filipe Manana <fdmanana@suse.com>
Date: Wed, 18 May 2022 10:41:48 +0100
Subject: [PATCH 0229/1731] btrfs: fix hang during unmount when block group
 reclaim task is running

When we start an unmount, at close_ctree(), if we have the reclaim task
running and in the middle of a data block group relocation, we can trigger
a deadlock when stopping an async reclaim task, producing a trace like the
following:

[629724.498185] task:kworker/u16:7   state:D stack:    0 pid:681170 ppid:     2 flags:0x00004000
[629724.499760] Workqueue: events_unbound btrfs_async_reclaim_metadata_space [btrfs]
[629724.501267] Call Trace:
[629724.501759]  <TASK>
[629724.502174]  __schedule+0x3cb/0xed0
[629724.502842]  schedule+0x4e/0xb0
[629724.503447]  btrfs_wait_on_delayed_iputs+0x7c/0xc0 [btrfs]
[629724.504534]  ? prepare_to_wait_exclusive+0xc0/0xc0
[629724.505442]  flush_space+0x423/0x630 [btrfs]
[629724.506296]  ? rcu_read_unlock_trace_special+0x20/0x50
[629724.507259]  ? lock_release+0x220/0x4a0
[629724.507932]  ? btrfs_get_alloc_profile+0xb3/0x290 [btrfs]
[629724.508940]  ? do_raw_spin_unlock+0x4b/0xa0
[629724.509688]  btrfs_async_reclaim_metadata_space+0x139/0x320 [btrfs]
[629724.510922]  process_one_work+0x252/0x5a0
[629724.511694]  ? process_one_work+0x5a0/0x5a0
[629724.512508]  worker_thread+0x52/0x3b0
[629724.513220]  ? process_one_work+0x5a0/0x5a0
[629724.514021]  kthread+0xf2/0x120
[629724.514627]  ? kthread_complete_and_exit+0x20/0x20
[629724.515526]  ret_from_fork+0x22/0x30
[629724.516236]  </TASK>
[629724.516694] task:umount          state:D stack:    0 pid:719055 ppid:695412 flags:0x00004000
[629724.518269] Call Trace:
[629724.518746]  <TASK>
[629724.519160]  __schedule+0x3cb/0xed0
[629724.519835]  schedule+0x4e/0xb0
[629724.520467]  schedule_timeout+0xed/0x130
[629724.521221]  ? lock_release+0x220/0x4a0
[629724.521946]  ? lock_acquired+0x19c/0x420
[629724.522662]  ? trace_hardirqs_on+0x1b/0xe0
[629724.523411]  __wait_for_common+0xaf/0x1f0
[629724.524189]  ? usleep_range_state+0xb0/0xb0
[629724.524997]  __flush_work+0x26d/0x530
[629724.525698]  ? flush_workqueue_prep_pwqs+0x140/0x140
[629724.526580]  ? lock_acquire+0x1a0/0x310
[629724.527324]  __cancel_work_timer+0x137/0x1c0
[629724.528190]  close_ctree+0xfd/0x531 [btrfs]
[629724.529000]  ? evict_inodes+0x166/0x1c0
[629724.529510]  generic_shutdown_super+0x74/0x120
[629724.530103]  kill_anon_super+0x14/0x30
[629724.530611]  btrfs_kill_super+0x12/0x20 [btrfs]
[629724.531246]  deactivate_locked_super+0x31/0xa0
[629724.531817]  cleanup_mnt+0x147/0x1c0
[629724.532319]  task_work_run+0x5c/0xa0
[629724.532984]  exit_to_user_mode_prepare+0x1a6/0x1b0
[629724.533598]  syscall_exit_to_user_mode+0x16/0x40
[629724.534200]  do_syscall_64+0x48/0x90
[629724.534667]  entry_SYSCALL_64_after_hwframe+0x44/0xae
[629724.535318] RIP: 0033:0x7fa2b90437a7
[629724.535804] RSP: 002b:00007ffe0b7e4458 EFLAGS: 00000246 ORIG_RAX: 00000000000000a6
[629724.536912] RAX: 0000000000000000 RBX: 00007fa2b9182264 RCX: 00007fa2b90437a7
[629724.538156] RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000555d6cf20dd0
[629724.539053] RBP: 0000555d6cf20ba0 R08: 0000000000000000 R09: 00007ffe0b7e3200
[629724.539956] R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000000
[629724.540883] R13: 0000555d6cf20dd0 R14: 0000555d6cf20cb0 R15: 0000000000000000
[629724.541796]  </TASK>

This happens because:

1) Before entering close_ctree() we have the async block group reclaim
   task running and relocating a data block group;

2) There's an async metadata (or data) space reclaim task running;

3) We enter close_ctree() and park the cleaner kthread;

4) The async space reclaim task is at flush_space() and runs all the
   existing delayed iputs;

5) Before the async space reclaim task calls
   btrfs_wait_on_delayed_iputs(), the block group reclaim task which is
   doing the data block group relocation, creates a delayed iput at
   replace_file_extents() (called when COWing leaves that have file extent
   items pointing to relocated data extents, during the merging phase
   of relocation roots);

6) The async reclaim space reclaim task blocks at
   btrfs_wait_on_delayed_iputs(), since we have a new delayed iput;

7) The task at close_ctree() then calls cancel_work_sync() to stop the
   async space reclaim task, but it blocks since that task is waiting for
   the delayed iput to be run;

8) The delayed iput is never run because the cleaner kthread is parked,
   and no one else runs delayed iputs, resulting in a hang.

So fix this by stopping the async block group reclaim task before we
park the cleaner kthread.

Fixes: 18bb8bbf13c183 ("btrfs: zoned: automatically reclaim zones")
CC: stable@vger.kernel.org # 5.15+
Signed-off-by: Filipe Manana <fdmanana@suse.com>
Signed-off-by: David Sterba <dsterba@suse.com>
---
 fs/btrfs/disk-io.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c
index f33093513360d..d92cc78936107 100644
--- a/fs/btrfs/disk-io.c
+++ b/fs/btrfs/disk-io.c
@@ -4631,6 +4631,17 @@ void __cold close_ctree(struct btrfs_fs_info *fs_info)
 	int ret;
 
 	set_bit(BTRFS_FS_CLOSING_START, &fs_info->flags);
+
+	/*
+	 * We may have the reclaim task running and relocating a data block group,
+	 * in which case it may create delayed iputs. So stop it before we park
+	 * the cleaner kthread otherwise we can get new delayed iputs after
+	 * parking the cleaner, and that can make the async reclaim task to hang
+	 * if it's waiting for delayed iputs to complete, since the cleaner is
+	 * parked and can not run delayed iputs - this will make us hang when
+	 * trying to stop the async reclaim task.
+	 */
+	cancel_work_sync(&fs_info->reclaim_bgs_work);
 	/*
 	 * We don't want the cleaner to start new transactions, add more delayed
 	 * iputs, etc. while we're closing. We can't use kthread_stop() yet
@@ -4671,8 +4682,6 @@ void __cold close_ctree(struct btrfs_fs_info *fs_info)
 	cancel_work_sync(&fs_info->async_data_reclaim_work);
 	cancel_work_sync(&fs_info->preempt_reclaim_work);
 
-	cancel_work_sync(&fs_info->reclaim_bgs_work);
-
 	/* Cancel or finish ongoing discard work */
 	btrfs_discard_cleanup(fs_info);
 
-- 
GitLab


From 0591f04036218d572d54349ea8c7914ad9c82b2b Mon Sep 17 00:00:00 2001
From: Qu Wenruo <wqu@suse.com>
Date: Wed, 18 May 2022 13:03:09 +0800
Subject: [PATCH 0230/1731] btrfs: prevent remounting to v1 space cache for
 subpage mount

Upstream commit 9f73f1aef98b ("btrfs: force v2 space cache usage for
subpage mount") forces subpage mount to use v2 cache, to avoid
deprecated v1 cache which doesn't support subpage properly.

But there is a loophole that user can still remount to v1 cache.

The existing check will only give users a warning, but does not really
prevent to do the remount.

Although remounting to v1 will not cause any problems since the v1 cache
will always be marked invalid when mounted with a different page size,
it's still better to prevent v1 cache at all for subpage mounts.

Fixes: 9f73f1aef98b ("btrfs: force v2 space cache usage for subpage mount")
CC: stable@vger.kernel.org # 5.15+
Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: David Sterba <dsterba@suse.com>
Signed-off-by: David Sterba <dsterba@suse.com>
---
 fs/btrfs/super.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c
index b1fdc6a26c76e..1387fbe935c14 100644
--- a/fs/btrfs/super.c
+++ b/fs/btrfs/super.c
@@ -1985,6 +1985,14 @@ static int btrfs_remount(struct super_block *sb, int *flags, char *data)
 	if (ret)
 		goto restore;
 
+	/* V1 cache is not supported for subpage mount. */
+	if (fs_info->sectorsize < PAGE_SIZE && btrfs_test_opt(fs_info, SPACE_CACHE)) {
+		btrfs_warn(fs_info,
+	"v1 space cache is not supported for page size %lu with sectorsize %u",
+			   PAGE_SIZE, fs_info->sectorsize);
+		ret = -EINVAL;
+		goto restore;
+	}
 	btrfs_remount_begin(fs_info, old_opts, *flags);
 	btrfs_resize_thread_pool(fs_info,
 		fs_info->thread_pool_size, old_thread_pool_size);
-- 
GitLab


From 122839b58a089ff7f231759e2c8f63790724cae2 Mon Sep 17 00:00:00 2001
From: Cristian Marussi <cristian.marussi@arm.com>
Date: Mon, 23 May 2022 18:15:59 +0100
Subject: [PATCH 0231/1731] firmware: arm_scmi: Relax base protocol sanity
 checks on the protocol list

Even though malformed replies from firmware must be treated carefully to
avoid memory corruption in the kernel, some out-of-spec SCMI replies can
be tolerated to avoid breaking existing deployed system, as long as they
won't cause memory issues.

Relax the sanity checks on the recieved protocol list in the base protocol
to avoid breaking one of the deployed platform whose firmware is not easily
upgradable currently.

Link: https://lore.kernel.org/r/20220523171559.472112-1-cristian.marussi@arm.com
Cc: Etienne Carriere <etienne.carriere@linaro.org>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Reported-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Tested-By: Frank Wunderlich <frank-w@public-files.de>
Acked-by: Michael Riesch <michael.riesch@wolfvision.net>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Cristian Marussi <cristian.marussi@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
 drivers/firmware/arm_scmi/base.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/firmware/arm_scmi/base.c b/drivers/firmware/arm_scmi/base.c
index 20fba7370f4e5..d0ac96da1ddff 100644
--- a/drivers/firmware/arm_scmi/base.c
+++ b/drivers/firmware/arm_scmi/base.c
@@ -221,11 +221,17 @@ scmi_base_implementation_list_get(const struct scmi_protocol_handle *ph,
 		calc_list_sz = (1 + (loop_num_ret - 1) / sizeof(u32)) *
 				sizeof(u32);
 		if (calc_list_sz != real_list_sz) {
-			dev_err(dev,
-				"Malformed reply - real_sz:%zd  calc_sz:%u\n",
-				real_list_sz, calc_list_sz);
-			ret = -EPROTO;
-			break;
+			dev_warn(dev,
+				 "Malformed reply - real_sz:%zd  calc_sz:%u  (loop_num_ret:%d)\n",
+				 real_list_sz, calc_list_sz, loop_num_ret);
+			/*
+			 * Bail out if the expected list size is bigger than the
+			 * total payload size of the received reply.
+			 */
+			if (calc_list_sz > real_list_sz) {
+				ret = -EPROTO;
+				break;
+			}
 		}
 
 		for (loop = 0; loop < loop_num_ret; loop++)
-- 
GitLab


From d0c94bef70e71e364c0a016b0e92307cd4d1d719 Mon Sep 17 00:00:00 2001
From: Cristian Marussi <cristian.marussi@arm.com>
Date: Mon, 30 May 2022 12:52:36 +0100
Subject: [PATCH 0232/1731] firmware: arm_scmi: Remove all the unused local
 variables

While using SCMI iterators helpers a few local automatic variables are
defined but then used only as input for sizeof operators.

cppcheck is fooled to complain about this with:

 | drivers/firmware/arm_scmi/sensors.c:341:48: warning: Variable 'msg' is
 |				not assigned a value. [unassignedVariable]
 |	 struct scmi_msg_sensor_list_update_intervals *msg;

Even though this is an innocuos warning, since the uninitialized variable
is at the end never used in the reported cases, fix these occurences all
over SCMI stack to avoid keeping unneeded objects on the stack.

Link: https://lore.kernel.org/r/20220530115237.277077-1-cristian.marussi@arm.com
Cc: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Cristian Marussi <cristian.marussi@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
 drivers/firmware/arm_scmi/clock.c   |  5 ++---
 drivers/firmware/arm_scmi/perf.c    |  4 ++--
 drivers/firmware/arm_scmi/sensors.c | 12 ++++++------
 drivers/firmware/arm_scmi/voltage.c |  4 ++--
 4 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/drivers/firmware/arm_scmi/clock.c b/drivers/firmware/arm_scmi/clock.c
index 4d36a9a133d1e..1a718faa41924 100644
--- a/drivers/firmware/arm_scmi/clock.c
+++ b/drivers/firmware/arm_scmi/clock.c
@@ -266,9 +266,7 @@ scmi_clock_describe_rates_get(const struct scmi_protocol_handle *ph, u32 clk_id,
 			      struct scmi_clock_info *clk)
 {
 	int ret;
-
 	void *iter;
-	struct scmi_msg_clock_describe_rates *msg;
 	struct scmi_iterator_ops ops = {
 		.prepare_message = iter_clk_describe_prepare_message,
 		.update_state = iter_clk_describe_update_state,
@@ -281,7 +279,8 @@ scmi_clock_describe_rates_get(const struct scmi_protocol_handle *ph, u32 clk_id,
 
 	iter = ph->hops->iter_response_init(ph, &ops, SCMI_MAX_NUM_RATES,
 					    CLOCK_DESCRIBE_RATES,
-					    sizeof(*msg), &cpriv);
+					    sizeof(struct scmi_msg_clock_describe_rates),
+					    &cpriv);
 	if (IS_ERR(iter))
 		return PTR_ERR(iter);
 
diff --git a/drivers/firmware/arm_scmi/perf.c b/drivers/firmware/arm_scmi/perf.c
index 8f4051aca2200..c1f7016230582 100644
--- a/drivers/firmware/arm_scmi/perf.c
+++ b/drivers/firmware/arm_scmi/perf.c
@@ -332,7 +332,6 @@ scmi_perf_describe_levels_get(const struct scmi_protocol_handle *ph, u32 domain,
 {
 	int ret;
 	void *iter;
-	struct scmi_msg_perf_describe_levels *msg;
 	struct scmi_iterator_ops ops = {
 		.prepare_message = iter_perf_levels_prepare_message,
 		.update_state = iter_perf_levels_update_state,
@@ -345,7 +344,8 @@ scmi_perf_describe_levels_get(const struct scmi_protocol_handle *ph, u32 domain,
 
 	iter = ph->hops->iter_response_init(ph, &ops, MAX_OPPS,
 					    PERF_DESCRIBE_LEVELS,
-					    sizeof(*msg), &ppriv);
+					    sizeof(struct scmi_msg_perf_describe_levels),
+					    &ppriv);
 	if (IS_ERR(iter))
 		return PTR_ERR(iter);
 
diff --git a/drivers/firmware/arm_scmi/sensors.c b/drivers/firmware/arm_scmi/sensors.c
index 21e0ce89b153a..75b9d716508ea 100644
--- a/drivers/firmware/arm_scmi/sensors.c
+++ b/drivers/firmware/arm_scmi/sensors.c
@@ -338,7 +338,6 @@ static int scmi_sensor_update_intervals(const struct scmi_protocol_handle *ph,
 					struct scmi_sensor_info *s)
 {
 	void *iter;
-	struct scmi_msg_sensor_list_update_intervals *msg;
 	struct scmi_iterator_ops ops = {
 		.prepare_message = iter_intervals_prepare_message,
 		.update_state = iter_intervals_update_state,
@@ -351,7 +350,8 @@ static int scmi_sensor_update_intervals(const struct scmi_protocol_handle *ph,
 
 	iter = ph->hops->iter_response_init(ph, &ops, s->intervals.count,
 					    SENSOR_LIST_UPDATE_INTERVALS,
-					    sizeof(*msg), &upriv);
+					    sizeof(struct scmi_msg_sensor_list_update_intervals),
+					    &upriv);
 	if (IS_ERR(iter))
 		return PTR_ERR(iter);
 
@@ -459,7 +459,6 @@ scmi_sensor_axis_extended_names_get(const struct scmi_protocol_handle *ph,
 				    struct scmi_sensor_info *s)
 {
 	void *iter;
-	struct scmi_msg_sensor_axis_description_get *msg;
 	struct scmi_iterator_ops ops = {
 		.prepare_message = iter_axes_desc_prepare_message,
 		.update_state = iter_axes_extended_name_update_state,
@@ -468,7 +467,8 @@ scmi_sensor_axis_extended_names_get(const struct scmi_protocol_handle *ph,
 
 	iter = ph->hops->iter_response_init(ph, &ops, s->num_axis,
 					    SENSOR_AXIS_NAME_GET,
-					    sizeof(*msg), s);
+					    sizeof(struct scmi_msg_sensor_axis_description_get),
+					    s);
 	if (IS_ERR(iter))
 		return PTR_ERR(iter);
 
@@ -481,7 +481,6 @@ static int scmi_sensor_axis_description(const struct scmi_protocol_handle *ph,
 {
 	int ret;
 	void *iter;
-	struct scmi_msg_sensor_axis_description_get *msg;
 	struct scmi_iterator_ops ops = {
 		.prepare_message = iter_axes_desc_prepare_message,
 		.update_state = iter_axes_desc_update_state,
@@ -495,7 +494,8 @@ static int scmi_sensor_axis_description(const struct scmi_protocol_handle *ph,
 
 	iter = ph->hops->iter_response_init(ph, &ops, s->num_axis,
 					    SENSOR_AXIS_DESCRIPTION_GET,
-					    sizeof(*msg), s);
+					    sizeof(struct scmi_msg_sensor_axis_description_get),
+					    s);
 	if (IS_ERR(iter))
 		return PTR_ERR(iter);
 
diff --git a/drivers/firmware/arm_scmi/voltage.c b/drivers/firmware/arm_scmi/voltage.c
index 9d195d8719ab3..97df6d3dd1318 100644
--- a/drivers/firmware/arm_scmi/voltage.c
+++ b/drivers/firmware/arm_scmi/voltage.c
@@ -180,7 +180,6 @@ static int scmi_voltage_levels_get(const struct scmi_protocol_handle *ph,
 {
 	int ret;
 	void *iter;
-	struct scmi_msg_cmd_describe_levels *msg;
 	struct scmi_iterator_ops ops = {
 		.prepare_message = iter_volt_levels_prepare_message,
 		.update_state = iter_volt_levels_update_state,
@@ -193,7 +192,8 @@ static int scmi_voltage_levels_get(const struct scmi_protocol_handle *ph,
 
 	iter = ph->hops->iter_response_init(ph, &ops, v->num_levels,
 					    VOLTAGE_DESCRIBE_LEVELS,
-					    sizeof(*msg), &vpriv);
+					    sizeof(struct scmi_msg_cmd_describe_levels),
+					    &vpriv);
 	if (IS_ERR(iter))
 		return PTR_ERR(iter);
 
-- 
GitLab


From fe44fb23d6ccde4c914c44ef74ab8d9d9ba02bea Mon Sep 17 00:00:00 2001
From: Trond Myklebust <trond.myklebust@hammerspace.com>
Date: Tue, 31 May 2022 11:03:06 -0400
Subject: [PATCH 0233/1731] pNFS: Don't keep retrying if the server replied
 NFS4ERR_LAYOUTUNAVAILABLE

If the server tells us that a pNFS layout is not available for a
specific file, then we should not keep pounding it with further
layoutget requests.

Fixes: 183d9e7b112a ("pnfs: rework LAYOUTGET retry handling")
Signed-off-by: Trond Myklebust <trond.myklebust@hammerspace.com>
Signed-off-by: Anna Schumaker <Anna.Schumaker@Netapp.com>
---
 fs/nfs/pnfs.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/fs/nfs/pnfs.c b/fs/nfs/pnfs.c
index 68a87be3e6f96..4609e641710e4 100644
--- a/fs/nfs/pnfs.c
+++ b/fs/nfs/pnfs.c
@@ -2152,6 +2152,12 @@ lookup_again:
 		case -ERECALLCONFLICT:
 		case -EAGAIN:
 			break;
+		case -ENODATA:
+			/* The server returned NFS4ERR_LAYOUTUNAVAILABLE */
+			pnfs_layout_set_fail_bit(
+				lo, pnfs_iomode_to_fail_bit(iomode));
+			lseg = NULL;
+			goto out_put_layout_hdr;
 		default:
 			if (!nfs_error_is_fatal(PTR_ERR(lseg))) {
 				pnfs_layout_clear_fail_bit(lo, pnfs_iomode_to_fail_bit(iomode));
-- 
GitLab


From 880265c77ac415090090d1fe72a188fee71cb458 Mon Sep 17 00:00:00 2001
From: Trond Myklebust <trond.myklebust@hammerspace.com>
Date: Tue, 31 May 2022 11:03:07 -0400
Subject: [PATCH 0234/1731] pNFS: Avoid a live lock condition in
 pnfs_update_layout()

If we're about to send the first layoutget for an empty layout, we want
to make sure that we drain out the existing pending layoutget calls
first. The reason is that these layouts may have been already implicitly
returned to the server by a recall to which the client gave a
NFS4ERR_NOMATCHING_LAYOUT response.

The problem is that wait_var_event_killable() could in principle see the
plh_outstanding count go back to '1' when the first process to wake up
starts sending a new layoutget. If it fails to get a layout, then this
loop can continue ad infinitum...

Fixes: 0b77f97a7e42 ("NFSv4/pnfs: Fix layoutget behaviour after invalidation")
Signed-off-by: Trond Myklebust <trond.myklebust@hammerspace.com>
Signed-off-by: Anna Schumaker <Anna.Schumaker@Netapp.com>
---
 fs/nfs/callback_proc.c |  1 +
 fs/nfs/pnfs.c          | 15 +++++++++------
 fs/nfs/pnfs.h          |  1 +
 3 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/fs/nfs/callback_proc.c b/fs/nfs/callback_proc.c
index c8520284dda78..c1eda73254e16 100644
--- a/fs/nfs/callback_proc.c
+++ b/fs/nfs/callback_proc.c
@@ -288,6 +288,7 @@ static u32 initiate_file_draining(struct nfs_client *clp,
 		rv = NFS4_OK;
 		break;
 	case -ENOENT:
+		set_bit(NFS_LAYOUT_DRAIN, &lo->plh_flags);
 		/* Embrace your forgetfulness! */
 		rv = NFS4ERR_NOMATCHING_LAYOUT;
 
diff --git a/fs/nfs/pnfs.c b/fs/nfs/pnfs.c
index 4609e641710e4..41a9b6b58fb9f 100644
--- a/fs/nfs/pnfs.c
+++ b/fs/nfs/pnfs.c
@@ -469,6 +469,7 @@ pnfs_mark_layout_stateid_invalid(struct pnfs_layout_hdr *lo,
 		pnfs_clear_lseg_state(lseg, lseg_list);
 	pnfs_clear_layoutreturn_info(lo);
 	pnfs_free_returned_lsegs(lo, lseg_list, &range, 0);
+	set_bit(NFS_LAYOUT_DRAIN, &lo->plh_flags);
 	if (test_bit(NFS_LAYOUT_RETURN, &lo->plh_flags) &&
 	    !test_and_set_bit(NFS_LAYOUT_RETURN_LOCK, &lo->plh_flags))
 		pnfs_clear_layoutreturn_waitbit(lo);
@@ -1917,8 +1918,9 @@ static void nfs_layoutget_begin(struct pnfs_layout_hdr *lo)
 
 static void nfs_layoutget_end(struct pnfs_layout_hdr *lo)
 {
-	if (atomic_dec_and_test(&lo->plh_outstanding))
-		wake_up_var(&lo->plh_outstanding);
+	if (atomic_dec_and_test(&lo->plh_outstanding) &&
+	    test_and_clear_bit(NFS_LAYOUT_DRAIN, &lo->plh_flags))
+		wake_up_bit(&lo->plh_flags, NFS_LAYOUT_DRAIN);
 }
 
 static bool pnfs_is_first_layoutget(struct pnfs_layout_hdr *lo)
@@ -2025,11 +2027,11 @@ lookup_again:
 	 * If the layout segment list is empty, but there are outstanding
 	 * layoutget calls, then they might be subject to a layoutrecall.
 	 */
-	if ((list_empty(&lo->plh_segs) || !pnfs_layout_is_valid(lo)) &&
+	if (test_bit(NFS_LAYOUT_DRAIN, &lo->plh_flags) &&
 	    atomic_read(&lo->plh_outstanding) != 0) {
 		spin_unlock(&ino->i_lock);
-		lseg = ERR_PTR(wait_var_event_killable(&lo->plh_outstanding,
-					!atomic_read(&lo->plh_outstanding)));
+		lseg = ERR_PTR(wait_on_bit(&lo->plh_flags, NFS_LAYOUT_DRAIN,
+					   TASK_KILLABLE));
 		if (IS_ERR(lseg))
 			goto out_put_layout_hdr;
 		pnfs_put_layout_hdr(lo);
@@ -2413,7 +2415,8 @@ pnfs_layout_process(struct nfs4_layoutget *lgp)
 		goto out_forget;
 	}
 
-	if (!pnfs_layout_is_valid(lo) && !pnfs_is_first_layoutget(lo))
+	if (test_bit(NFS_LAYOUT_DRAIN, &lo->plh_flags) &&
+	    !pnfs_is_first_layoutget(lo))
 		goto out_forget;
 
 	if (nfs4_stateid_match_other(&lo->plh_stateid, &res->stateid)) {
diff --git a/fs/nfs/pnfs.h b/fs/nfs/pnfs.h
index 07f11489e4e9f..f331f067691b0 100644
--- a/fs/nfs/pnfs.h
+++ b/fs/nfs/pnfs.h
@@ -105,6 +105,7 @@ enum {
 	NFS_LAYOUT_FIRST_LAYOUTGET,	/* Serialize first layoutget */
 	NFS_LAYOUT_INODE_FREEING,	/* The inode is being freed */
 	NFS_LAYOUT_HASHED,		/* The layout visible */
+	NFS_LAYOUT_DRAIN,
 };
 
 enum layoutdriver_policy_flags {
-- 
GitLab


From b3d0c0f2dfbe610ae5ac6b2d70dd450645dce3cb Mon Sep 17 00:00:00 2001
From: David Zhang <dingchen.zhang@amd.com>
Date: Tue, 3 May 2022 18:36:28 -0400
Subject: [PATCH 0235/1731] drm/amd/display: feed PSR-SU as psr version to dmub
 FW

[why & how]
set psr version as PSR-SU in kernel-FW interface function to ensure
the correct dmub command parameter is fed into FW.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 1d4f0c45b5368..f1411a22cf1ec 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -133,6 +133,9 @@ static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *
 	case DC_PSR_VERSION_1:
 		cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_1;
 		break;
+	case DC_PSR_VERSION_SU_1:
+		cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_SU_1;
+		break;
 	case DC_PSR_VERSION_UNSUPPORTED:
 	default:
 		cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_UNSUPPORTED;
-- 
GitLab


From 1da5dab029c08e178784a0750203365ea7c3b4f4 Mon Sep 17 00:00:00 2001
From: David Zhang <dingchen.zhang@amd.com>
Date: Fri, 29 Apr 2022 15:55:16 -0400
Subject: [PATCH 0236/1731] drm/amd/display: combine dirty rectangles in DMUB
 FW

[why]
In PSR-SU design, the DMUB FW handles the combination of multiple
dirty rectangles.

[how]
- create DC dmub update dirty rectangle helper which sends the
  dirty rectangles per pipe from DC to DMUB, and DMUB FW will
  handle to combine the dirty RECTs
- call the helper from DC commit plane update function.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   | 54 ++++++++++++++++++++++
 drivers/gpu/drm/amd/display/dc/dc_stream.h |  5 ++
 2 files changed, 59 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index e3e3b27916322..d4173be119031 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -72,6 +72,9 @@
 #include "dmub/dmub_srv.h"
 
 #include "i2caux_interface.h"
+
+#include "dce/dmub_psr.h"
+
 #include "dce/dmub_hw_lock_mgr.h"
 
 #include "dc_trace.h"
@@ -2824,6 +2827,55 @@ static void commit_planes_do_stream_update(struct dc *dc,
 	}
 }
 
+void dc_dmub_update_dirty_rect(struct dc *dc,
+			       int surface_count,
+			       struct dc_stream_state *stream,
+			       struct dc_surface_update *srf_updates,
+			       struct dc_state *context)
+{
+	union dmub_rb_cmd cmd;
+	struct dc_context *dc_ctx = dc->ctx;
+	struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
+	unsigned int i, j;
+
+	if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1)
+		return;
+
+	memset(&cmd, 0x0, sizeof(cmd));
+	cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
+	cmd.update_dirty_rect.header.sub_type = 0;
+	cmd.update_dirty_rect.header.payload_bytes =
+		sizeof(cmd.update_dirty_rect) -
+		sizeof(cmd.update_dirty_rect.header);
+	update_dirty_rect = &cmd.update_dirty_rect.update_dirty_rect_data;
+	for (i = 0; i < surface_count; i++) {
+		struct dc_plane_state *plane_state = srf_updates[i].surface;
+		const struct dc_flip_addrs *flip_addr = srf_updates[i].flip_addr;
+
+		if (!srf_updates[i].surface || !flip_addr)
+			continue;
+		/* Do not send in immediate flip mode */
+		if (srf_updates[i].surface->flip_immediate)
+			continue;
+
+		update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
+		memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
+				sizeof(flip_addr->dirty_rects));
+		for (j = 0; j < dc->res_pool->pipe_count; j++) {
+			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
+
+			if (pipe_ctx->stream != stream)
+				continue;
+			if (pipe_ctx->plane_state != plane_state)
+				continue;
+
+			update_dirty_rect->pipe_idx = j;
+			dc_dmub_srv_cmd_queue(dc_ctx->dmub_srv, &cmd);
+			dc_dmub_srv_cmd_execute(dc_ctx->dmub_srv);
+		}
+	}
+}
+
 static void commit_planes_for_stream(struct dc *dc,
 		struct dc_surface_update *srf_updates,
 		int surface_count,
@@ -2911,6 +2963,8 @@ static void commit_planes_for_stream(struct dc *dc,
 		dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
 	}
 
+	dc_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context);
+
 	// Stream updates
 	if (stream_update)
 		commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 772b4a61f166a..f8f66790d09bf 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -550,4 +550,9 @@ bool dc_stream_get_crtc_position(struct dc *dc,
 
 struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream);
 
+void dc_dmub_update_dirty_rect(struct dc *dc,
+			       int surface_count,
+			       struct dc_stream_state *stream,
+			       struct dc_surface_update *srf_updates,
+			       struct dc_state *context);
 #endif /* DC_STREAM_H_ */
-- 
GitLab


From 3a6dce778de7c120a37983d80b6ccc8c2c4ff6ec Mon Sep 17 00:00:00 2001
From: David Zhang <dingchen.zhang@amd.com>
Date: Fri, 29 Apr 2022 17:32:56 -0400
Subject: [PATCH 0237/1731] drm/amd/display: update GSP1 generic info packet
 for PSRSU

[why & how]
Based on PSRSU specification, every selective update frame need to use
two SDP to indicate the frame active range. So we occupy another GSP1
for PSRSU execution.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../display/dc/dcn30/dcn30_dio_stream_encoder.c   | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
index b683ad8171067..1a26ce87c16e3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
@@ -419,6 +419,21 @@ void enc3_stream_encoder_update_dp_info_packets(
 				&info_frame->vsc,
 				true);
 	}
+	/* TODO: VSC SDP at packetIndex 1 should be restricted only if PSR-SU on.
+	 * There should have another Infopacket type (e.g. vsc_psrsu) for PSR_SU.
+	 * In addition, currently the driver check the valid bit then update and
+	 * send the corresponding Infopacket. For PSR-SU, the SDP only be sent
+	 * while entering PSR-SU mode. So we need another parameter(e.g. send)
+	 * in dc_info_packet to indicate which infopacket should be enabled by
+	 * default here.
+	 */
+	if (info_frame->vsc.valid) {
+		enc->vpg->funcs->update_generic_info_packet(
+				enc->vpg,
+				1,  /* packetIndex */
+				&info_frame->vsc,
+				true);
+	}
 	if (info_frame->spd.valid) {
 		enc->vpg->funcs->update_generic_info_packet(
 				enc->vpg,
-- 
GitLab


From aa303964bc349914de8e1d3ff7b517581839d01b Mon Sep 17 00:00:00 2001
From: David Zhang <dingchen.zhang@amd.com>
Date: Fri, 29 Apr 2022 17:38:14 -0400
Subject: [PATCH 0238/1731] drm/amd/display: revise Start/End SDP data

[why & how]
We need to implement the VSC packet rev4 that is required by PSRSU.

Follow the eDP 1.5 spec pg. 257

changes in v2:
-------------------
- set vsc packet rev2 for PSR1

Cc: Chandan Vurdigerenataraj <chandan.vurdigerenataraj@amd.com>

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../display/modules/info_packet/info_packet.c | 29 +++++++++++++++++--
 1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
index 79bc207415bcb..27ceba9d6d658 100644
--- a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
+++ b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
@@ -145,8 +145,10 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
 		stereo3dSupport = true;
 	}
 
-	/*VSC packet set to 2 when DP revision >= 1.2*/
-	if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED)
+	/* VSC packet set to 4 for PSR-SU, or 2 for PSR1 */
+	if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
+		vsc_packet_revision = vsc_packet_rev4;
+	else if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_1)
 		vsc_packet_revision = vsc_packet_rev2;
 
 	/* Update to revision 5 for extended colorimetry support */
@@ -159,6 +161,29 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
 	if (vsc_packet_revision == vsc_packet_undefined)
 		return;
 
+	if (vsc_packet_revision == vsc_packet_rev4) {
+		/* Secondary-data Packet ID = 0*/
+		info_packet->hb0 = 0x00;
+		/* 07h - Packet Type Value indicating Video
+		 * Stream Configuration packet
+		 */
+		info_packet->hb1 = 0x07;
+		/* 04h = VSC SDP supporting 3D stereo + PSR/PSR2 + Y-coordinate
+		 * (applies to eDP v1.4 or higher).
+		 */
+		info_packet->hb2 = 0x04;
+		/* 0Eh = VSC SDP supporting 3D stereo + PSR2
+		 * (HB2 = 04h), with Y-coordinate of first scan
+		 * line of the SU region
+		 */
+		info_packet->hb3 = 0x0E;
+
+		for (i = 0; i < 28; i++)
+			info_packet->sb[i] = 0;
+
+		info_packet->valid = true;
+	}
+
 	if (vsc_packet_revision == vsc_packet_rev2) {
 		/* Secondary-data Packet ID = 0*/
 		info_packet->hb0 = 0x00;
-- 
GitLab


From 6d1044a070b2eef0be45f3b99274a6cebee25053 Mon Sep 17 00:00:00 2001
From: David Zhang <dingchen.zhang@amd.com>
Date: Mon, 2 May 2022 11:05:56 -0400
Subject: [PATCH 0239/1731] drm/amd/display: program PSR2 DPCD Configuration

[Why]
To support PSR2 Source DPCD configuration

[How]
Update the PSR2 Source DPCD settings while the PSR2 enabled

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 23 ++++++++++++++++++-
 .../drm/amd/display/dc/inc/hw/link_encoder.h  | 13 ++++++++++-
 2 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 55a8f58ee2392..97bb2d8764269 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3206,6 +3206,7 @@ bool dc_link_setup_psr(struct dc_link *link,
 	unsigned int panel_inst;
 	/* updateSinkPsrDpcdConfig*/
 	union dpcd_psr_configuration psr_configuration;
+	union dpcd_alpm_configuration alpm_configuration;
 
 	psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
 
@@ -3231,7 +3232,7 @@ bool dc_link_setup_psr(struct dc_link *link,
 			psr_config->psr_frame_capture_indication_req;
 
 	/* Check for PSR v2*/
-	if (psr_config->psr_version == 0x2) {
+	if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
 		/* For PSR v2 selective update.
 		 * Indicates whether sink should start capturing
 		 * immediately following active scan line,
@@ -3242,6 +3243,14 @@ bool dc_link_setup_psr(struct dc_link *link,
 		 * IRQ_HPD when CRC mismatch is detected.
 		 */
 		psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
+		/* For PSR v2, set the bit when the Source device will
+		 * be enabling PSR2 operation.
+		 */
+		psr_configuration.bits.ENABLE_PSR2    = 1;
+		/* For PSR v2, the Sink device must be able to receive
+		 * SU region updates early in the frame time.
+		 */
+		psr_configuration.bits.EARLY_TRANSPORT_ENABLE    = 1;
 	}
 
 	dm_helpers_dp_write_dpcd(
@@ -3251,6 +3260,18 @@ bool dc_link_setup_psr(struct dc_link *link,
 		&psr_configuration.raw,
 		sizeof(psr_configuration.raw));
 
+	if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
+		memset(&alpm_configuration, 0, sizeof(alpm_configuration));
+
+		alpm_configuration.bits.ENABLE = 1;
+		dm_helpers_dp_write_dpcd(
+			link->ctx,
+			link,
+			DP_RECEIVER_ALPM_CONFIG,
+			&alpm_configuration.raw,
+			sizeof(alpm_configuration.raw));
+	}
+
 	psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
 	psr_context->transmitterId = link->link_enc->transmitter;
 	psr_context->engineId = link->link_enc->preferred_engine;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index d8433c6792012..6e6bd007babc1 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -85,7 +85,18 @@ union dpcd_psr_configuration {
 		unsigned char LINE_CAPTURE_INDICATION   : 1;
 		/* For eDP 1.4, PSR v2*/
 		unsigned char IRQ_HPD_WITH_CRC_ERROR    : 1;
-		unsigned char RESERVED                  : 2;
+		unsigned char ENABLE_PSR2               : 1;
+		/* For eDP 1.5, PSR v2 w/ early transport */
+		unsigned char EARLY_TRANSPORT_ENABLE    : 1;
+	} bits;
+	unsigned char raw;
+};
+
+union dpcd_alpm_configuration {
+	struct {
+		unsigned char ENABLE                    : 1;
+		unsigned char IRQ_HPD_ENABLE            : 1;
+		unsigned char RESERVED                  : 6;
 	} bits;
 	unsigned char raw;
 };
-- 
GitLab


From 651d7ee63f338b82d18273c30e9ea804ae174342 Mon Sep 17 00:00:00 2001
From: Somalapuram Amaranath <Amaranath.Somalapuram@amd.com>
Date: Thu, 2 Jun 2022 12:54:58 +0530
Subject: [PATCH 0240/1731] drm/amdgpu: save the reset dump register value for
 devcoredump

Allocate memory for register value and use the same values for devcoredump.
v1 -> v2: Change krealloc_array() to kmalloc_array()
v2 -> v3: Fix alignment

Signed-off-by: Somalapuram Amaranath <Amaranath.Somalapuram@amd.com>
Reviewed-by: Shashank Sharma <Shashank.sharma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h         | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 7 +++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c  | 6 +++---
 3 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 3ec7427c018c9..1525fa1d6798b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1044,6 +1044,7 @@ struct amdgpu_device {
 
 	/* reset dump register */
 	uint32_t                        *reset_dump_reg_list;
+	uint32_t			*reset_dump_reg_value;
 	int                             num_regs;
 
 	bool                            scpm_enabled;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index eedb12f6b8a32..f3ac7912c29c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1709,17 +1709,24 @@ static ssize_t amdgpu_reset_dump_register_list_write(struct file *f,
 		i++;
 	} while (len < size);
 
+	new = kmalloc_array(i, sizeof(uint32_t), GFP_KERNEL);
+	if (!new) {
+		ret = -ENOMEM;
+		goto error_free;
+	}
 	ret = down_write_killable(&adev->reset_domain->sem);
 	if (ret)
 		goto error_free;
 
 	swap(adev->reset_dump_reg_list, tmp);
+	swap(adev->reset_dump_reg_value, new);
 	adev->num_regs = i;
 	up_write(&adev->reset_domain->sem);
 	ret = size;
 
 error_free:
 	kfree(tmp);
+	kfree(new);
 	return ret;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 4831148342b75..c56b04e9ce9a9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4666,15 +4666,15 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
 
 static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)
 {
-	uint32_t reg_value;
 	int i;
 
 	lockdep_assert_held(&adev->reset_domain->sem);
 	dump_stack();
 
 	for (i = 0; i < adev->num_regs; i++) {
-		reg_value = RREG32(adev->reset_dump_reg_list[i]);
-		trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i], reg_value);
+		adev->reset_dump_reg_value[i] = RREG32(adev->reset_dump_reg_list[i]);
+		trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i],
+					     adev->reset_dump_reg_value[i]);
 	}
 
 	return 0;
-- 
GitLab


From 3d8785f6c04a953868384db455bb2fdd0b22c11c Mon Sep 17 00:00:00 2001
From: Somalapuram Amaranath <Amaranath.Somalapuram@amd.com>
Date: Thu, 2 Jun 2022 13:01:27 +0530
Subject: [PATCH 0241/1731] drm/amdgpu: adding device coredump support

Added device coredump information:
- Kernel version
- Module
- Time
- VRAM status
- Guilty process name and PID
- GPU register dumps
v1 -> v2: Variable name change
v1 -> v2: NULL check
v1 -> v2: Code alignment
v1 -> v2: Adding dummy amdgpu_devcoredump_free
v1 -> v2: memset reset_task_info to zero
v2 -> v3: add CONFIG_DEV_COREDUMP for variables
v2 -> v3: remove NULL check on amdgpu_devcoredump_read

Signed-off-by: Somalapuram Amaranath <Amaranath.Somalapuram@amd.com>
Reviewed-by: Shashank Sharma <Shashank.sharma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  5 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 64 ++++++++++++++++++++++
 2 files changed, 69 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 1525fa1d6798b..c67069645a2c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1046,6 +1046,11 @@ struct amdgpu_device {
 	uint32_t                        *reset_dump_reg_list;
 	uint32_t			*reset_dump_reg_value;
 	int                             num_regs;
+#ifdef CONFIG_DEV_COREDUMP
+	struct amdgpu_task_info         reset_task_info;
+	bool                            reset_vram_lost;
+	struct timespec64               reset_time;
+#endif
 
 	bool                            scpm_enabled;
 	uint32_t                        scpm_status;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c56b04e9ce9a9..620afd75dae76 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -32,6 +32,8 @@
 #include <linux/slab.h>
 #include <linux/iommu.h>
 #include <linux/pci.h>
+#include <linux/devcoredump.h>
+#include <generated/utsrelease.h>
 
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_probe_helper.h>
@@ -4680,6 +4682,59 @@ static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)
 	return 0;
 }
 
+#ifdef CONFIG_DEV_COREDUMP
+static ssize_t amdgpu_devcoredump_read(char *buffer, loff_t offset,
+		size_t count, void *data, size_t datalen)
+{
+	struct drm_printer p;
+	struct amdgpu_device *adev = data;
+	struct drm_print_iterator iter;
+	int i;
+
+	iter.data = buffer;
+	iter.offset = 0;
+	iter.start = offset;
+	iter.remain = count;
+
+	p = drm_coredump_printer(&iter);
+
+	drm_printf(&p, "**** AMDGPU Device Coredump ****\n");
+	drm_printf(&p, "kernel: " UTS_RELEASE "\n");
+	drm_printf(&p, "module: " KBUILD_MODNAME "\n");
+	drm_printf(&p, "time: %lld.%09ld\n", adev->reset_time.tv_sec, adev->reset_time.tv_nsec);
+	if (adev->reset_task_info.pid)
+		drm_printf(&p, "process_name: %s PID: %d\n",
+			   adev->reset_task_info.process_name,
+			   adev->reset_task_info.pid);
+
+	if (adev->reset_vram_lost)
+		drm_printf(&p, "VRAM is lost due to GPU reset!\n");
+	if (adev->num_regs) {
+		drm_printf(&p, "AMDGPU register dumps:\nOffset:     Value:\n");
+
+		for (i = 0; i < adev->num_regs; i++)
+			drm_printf(&p, "0x%08x: 0x%08x\n",
+				   adev->reset_dump_reg_list[i],
+				   adev->reset_dump_reg_value[i]);
+	}
+
+	return count - iter.remain;
+}
+
+static void amdgpu_devcoredump_free(void *data)
+{
+}
+
+static void amdgpu_reset_capture_coredumpm(struct amdgpu_device *adev)
+{
+	struct drm_device *dev = adev_to_drm(adev);
+
+	ktime_get_ts64(&adev->reset_time);
+	dev_coredumpm(dev->dev, THIS_MODULE, adev, 0, GFP_KERNEL,
+		      amdgpu_devcoredump_read, amdgpu_devcoredump_free);
+}
+#endif
+
 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
 			 struct amdgpu_reset_context *reset_context)
 {
@@ -4764,6 +4819,15 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle,
 					goto out;
 
 				vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
+#ifdef CONFIG_DEV_COREDUMP
+				tmp_adev->reset_vram_lost = vram_lost;
+				memset(&tmp_adev->reset_task_info, 0,
+						sizeof(tmp_adev->reset_task_info));
+				if (reset_context->job && reset_context->job->vm)
+					tmp_adev->reset_task_info =
+						reset_context->job->vm->task_info;
+				amdgpu_reset_capture_coredumpm(tmp_adev);
+#endif
 				if (vram_lost) {
 					DRM_INFO("VRAM is lost due to GPU reset!\n");
 					amdgpu_inc_vram_lost(tmp_adev);
-- 
GitLab


From b07d1d73b09ef40e91ace51a2e167391676a8175 Mon Sep 17 00:00:00 2001
From: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
Date: Mon, 6 Jun 2022 13:06:30 +0530
Subject: [PATCH 0242/1731] drm/amd/amdgpu: Enable high priority gfx queue
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Starting from SIENNA CICHLID asic supports two gfx pipes, enabling
two graphics queues, 1 on each pipe, pipe0 queue0 would be the normal
piority queue and pipe1 queue0 would be the high priority queue

Only one queue per pipe is visble to SPI, SPI looks at the priority
value assigned to CP_GFX_HQD_QUEUE_PRIORITY from each of the queue's
HQD/MQD.

Create contexts applying AMDGPU_CTX_PRIORITY_HIGH which submits job
to the high priority queue on GFX pipe1. There would be starvation
of LP workload if HP workload is always available.

v2:
  - remove unnecessary check(Nirmoy)
  - make pipe1 hardware support a separate patch(Nirmoy)
  - remove duplicate code(Shashank)
  - add CSA support for second gfx pipe(Alex)

v3(Christian):
  - fix incorrect indentation
  - merge COMPUTE and GFX switch cases as both calls the same function.

v4:
  - rebase w/ latest code base

Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c  |  7 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c  | 55 +++++++++++++++++++-----
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h  |  2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 12 +++---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c   | 32 +++++++++++---
 5 files changed, 81 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 7dc92ef36b2b0..2ef5296216d64 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -110,7 +110,7 @@ static int amdgpu_ctx_priority_permit(struct drm_file *filp,
 	return -EACCES;
 }
 
-static enum amdgpu_gfx_pipe_priority amdgpu_ctx_prio_to_compute_prio(int32_t prio)
+static enum amdgpu_gfx_pipe_priority amdgpu_ctx_prio_to_gfx_pipe_prio(int32_t prio)
 {
 	switch (prio) {
 	case AMDGPU_CTX_PRIORITY_HIGH:
@@ -143,8 +143,9 @@ static unsigned int amdgpu_ctx_get_hw_prio(struct amdgpu_ctx *ctx, u32 hw_ip)
 			ctx->init_priority : ctx->override_priority;
 
 	switch (hw_ip) {
+	case AMDGPU_HW_IP_GFX:
 	case AMDGPU_HW_IP_COMPUTE:
-		hw_prio = amdgpu_ctx_prio_to_compute_prio(ctx_prio);
+		hw_prio = amdgpu_ctx_prio_to_gfx_pipe_prio(ctx_prio);
 		break;
 	case AMDGPU_HW_IP_VCE:
 	case AMDGPU_HW_IP_VCN_ENC:
@@ -779,7 +780,7 @@ static void amdgpu_ctx_set_entity_priority(struct amdgpu_ctx *ctx,
 				      amdgpu_ctx_to_drm_sched_prio(priority));
 
 	/* set hw priority */
-	if (hw_ip == AMDGPU_HW_IP_COMPUTE) {
+	if (hw_ip == AMDGPU_HW_IP_COMPUTE || hw_ip == AMDGPU_HW_IP_GFX) {
 		hw_prio = amdgpu_ctx_get_hw_prio(ctx, hw_ip);
 		hw_prio = array_index_nospec(hw_prio, AMDGPU_RING_PRIO_MAX);
 		scheds = adev->gpu_sched[hw_ip][hw_prio].sched;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 16699158e00d8..00c69f0a9f52e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -142,7 +142,12 @@ void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_s
 	}
 }
 
-static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
+static bool amdgpu_gfx_is_graphics_multipipe_capable(struct amdgpu_device *adev)
+{
+	return amdgpu_async_gfx_ring && adev->gfx.me.num_pipe_per_me > 1;
+}
+
+static bool amdgpu_gfx_is_compute_multipipe_capable(struct amdgpu_device *adev)
 {
 	if (amdgpu_compute_multipipe != -1) {
 		DRM_INFO("amdgpu: forcing compute pipe policy %d\n",
@@ -158,6 +163,28 @@ static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
 	return adev->gfx.mec.num_mec > 1;
 }
 
+bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
+						struct amdgpu_ring *ring)
+{
+	int queue = ring->queue;
+	int pipe = ring->pipe;
+
+	/* Policy: use pipe1 queue0 as high priority graphics queue if we
+	 * have more than one gfx pipe.
+	 */
+	if (amdgpu_gfx_is_graphics_multipipe_capable(adev) &&
+	    adev->gfx.num_gfx_rings > 1 && pipe == 1 && queue == 0) {
+		int me = ring->me;
+		int bit;
+
+		bit = amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue);
+		if (ring == &adev->gfx.gfx_ring[bit])
+			return true;
+	}
+
+	return false;
+}
+
 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
 					       struct amdgpu_ring *ring)
 {
@@ -174,7 +201,7 @@ bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
 {
 	int i, queue, pipe;
-	bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev);
+	bool multipipe_policy = amdgpu_gfx_is_compute_multipipe_capable(adev);
 	int max_queues_per_mec = min(adev->gfx.mec.num_pipe_per_mec *
 				     adev->gfx.mec.num_queue_per_pipe,
 				     adev->gfx.num_compute_rings);
@@ -200,18 +227,24 @@ void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
 
 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
 {
-	int i, queue, me;
-
-	for (i = 0; i < AMDGPU_MAX_GFX_QUEUES; ++i) {
-		queue = i % adev->gfx.me.num_queue_per_pipe;
-		me = (i / adev->gfx.me.num_queue_per_pipe)
-		      / adev->gfx.me.num_pipe_per_me;
+	int i, queue, pipe;
+	bool multipipe_policy = amdgpu_gfx_is_graphics_multipipe_capable(adev);
+	int max_queues_per_me = adev->gfx.me.num_pipe_per_me *
+					adev->gfx.me.num_queue_per_pipe;
 
-		if (me >= adev->gfx.me.num_me)
-			break;
+	if (multipipe_policy) {
 		/* policy: amdgpu owns the first queue per pipe at this stage
 		 * will extend to mulitple queues per pipe later */
-		if (me == 0 && queue < 1)
+		for (i = 0; i < max_queues_per_me; i++) {
+			pipe = i % adev->gfx.me.num_pipe_per_me;
+			queue = (i / adev->gfx.me.num_pipe_per_me) %
+				adev->gfx.me.num_queue_per_pipe;
+
+			set_bit(pipe * adev->gfx.me.num_queue_per_pipe + queue,
+					adev->gfx.me.queue_bitmap);
+		}
+	} else {
+		for (i = 0; i < max_queues_per_me; ++i)
 			set_bit(i, adev->gfx.me.queue_bitmap);
 	}
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 53526ffb2ce16..23a696d38390d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -396,6 +396,8 @@ bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
 				     int pipe, int queue);
 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
 					       struct amdgpu_ring *ring);
+bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
+						struct amdgpu_ring *ring);
 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
 			       int pipe, int queue);
 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 13db99d653bd3..1fa9edf040225 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -543,12 +543,12 @@ static void amdgpu_ring_to_mqd_prop(struct amdgpu_ring *ring,
 	 */
 	prop->hqd_active = ring->funcs->type == AMDGPU_RING_TYPE_KIQ;
 
-	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
-		if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
-			prop->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
-			prop->hqd_queue_priority =
-				AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
-		}
+	if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE &&
+	    amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) ||
+	    (ring->funcs->type == AMDGPU_RING_TYPE_GFX &&
+	    amdgpu_gfx_is_high_priority_graphics_queue(adev, ring))) {
+		prop->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
+		prop->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
 	}
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index c5f46d264b23d..6831d1eb18bf4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -53,7 +53,7 @@
  * 2. Async ring
  */
 #define GFX10_NUM_GFX_RINGS_NV1X	1
-#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid	1
+#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid	2
 #define GFX10_MEC_HPD_SIZE	2048
 
 #define F32_CE_PROGRAM_RAM_SIZE		65536
@@ -4711,6 +4711,7 @@ static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
 {
 	struct amdgpu_ring *ring;
 	unsigned int irq_type;
+	unsigned int hw_prio;
 
 	ring = &adev->gfx.gfx_ring[ring_id];
 
@@ -4728,8 +4729,10 @@ static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
 	sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 
 	irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
+	hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
+			AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
 	return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
-			     AMDGPU_RING_PRIO_DEFAULT, NULL);
+				hw_prio, NULL);
 }
 
 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
@@ -6581,6 +6584,24 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
 	}
 }
 
+static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
+					   struct v10_gfx_mqd *mqd,
+					   struct amdgpu_mqd_prop *prop)
+{
+	bool priority = 0;
+	u32 tmp;
+
+	/* set up default queue priority level
+	 * 0x0 = low priority, 0x1 = high priority
+	 */
+	if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
+		priority = 1;
+
+	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
+	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
+	mqd->cp_gfx_hqd_queue_priority = tmp;
+}
+
 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
 				  struct amdgpu_mqd_prop *prop)
 {
@@ -6609,11 +6630,8 @@ static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
 	mqd->cp_gfx_hqd_vmid = 0;
 
-	/* set up default queue priority level
-	 * 0x0 = low priority, 0x1 = high priority */
-	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
-	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
-	mqd->cp_gfx_hqd_queue_priority = tmp;
+	/* set up gfx queue priority */
+	gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);
 
 	/* set up time quantum */
 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
-- 
GitLab


From 4c7631800e6bf0eced08dd7b4f793fcd972f597d Mon Sep 17 00:00:00 2001
From: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
Date: Mon, 6 Jun 2022 13:59:13 +0530
Subject: [PATCH 0243/1731] drm/amd/amdgpu: add pipe1 hardware support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Enable pipe1 support starting from SIENNA CICHLID asic

Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 6831d1eb18bf4..797e90e8ce28b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4794,7 +4794,7 @@ static int gfx_v10_0_sw_init(void *handle)
 	case IP_VERSION(10, 3, 3):
 	case IP_VERSION(10, 3, 7):
 		adev->gfx.me.num_me = 1;
-		adev->gfx.me.num_pipe_per_me = 1;
+		adev->gfx.me.num_pipe_per_me = 2;
 		adev->gfx.me.num_queue_per_pipe = 1;
 		adev->gfx.mec.num_mec = 2;
 		adev->gfx.mec.num_pipe_per_mec = 4;
-- 
GitLab


From a35806b36ea44724b21f7f110b38b5941fc9c393 Mon Sep 17 00:00:00 2001
From: David Zhang <dingchen.zhang@amd.com>
Date: Mon, 2 May 2022 11:21:25 -0400
Subject: [PATCH 0244/1731] drm/amd/display: Passing Y-granularity to dmub fw

[Why]
The Y-granularity panel parameter indicate the grid
pattern granularity in the Y direction for PSRSU.

[How]
Send the Y-granularity data by PSR_COPY_SETTINGS dmub command.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++++
 drivers/gpu/drm/amd/display/dc/dc_types.h     | 8 ++++++++
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 6 ++++++
 3 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 97bb2d8764269..dc1d75b204cde 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3270,6 +3270,10 @@ bool dc_link_setup_psr(struct dc_link *link,
 			DP_RECEIVER_ALPM_CONFIG,
 			&alpm_configuration.raw,
 			sizeof(alpm_configuration.raw));
+		psr_context->su_granularity_required =
+			psr_config->su_granularity_required;
+		psr_context->su_y_granularity =
+			psr_config->su_y_granularity;
 	}
 
 	psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 2ba9f528c0fe7..d61ea3e2bfbfb 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -672,6 +672,10 @@ struct psr_config {
 	unsigned int psr_sdp_transmit_line_num_deadline;
 	bool allow_smu_optimizations;
 	bool allow_multi_disp_optimizations;
+	/* Panel self refresh 2 selective update granularity required */
+	bool su_granularity_required;
+	/* psr2 selective update y granularity capability */
+	uint8_t su_y_granularity;
 };
 
 union dmcu_psr_level {
@@ -775,6 +779,10 @@ struct psr_context {
 	unsigned int frame_delay;
 	bool allow_smu_optimizations;
 	bool allow_multi_disp_optimizations;
+	/* Panel self refresh 2 selective update granularity required */
+	bool su_granularity_required;
+	/* psr2 selective update y granularity capability */
+	uint8_t su_y_granularity;
 };
 
 struct colorspace_transform {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index f1411a22cf1ec..6883dd5b80d66 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -333,6 +333,12 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 	copy_settings_data->debug.u32All = 0;
 	copy_settings_data->debug.bitfields.visual_confirm	= dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR;
 	copy_settings_data->debug.bitfields.use_hw_lock_mgr		= 1;
+
+	if (psr_context->su_granularity_required == 0)
+		copy_settings_data->su_y_granularity = 0;
+	else
+		copy_settings_data->su_y_granularity = psr_context->su_y_granularity;
+
 	copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
 	copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
 	copy_settings_data->cmd_version =  DMUB_CMD_PSR_CONTROL_VERSION_1;
-- 
GitLab


From 65657d98754c581ad66b56680d3c9ed679890071 Mon Sep 17 00:00:00 2001
From: David Zhang <dingchen.zhang@amd.com>
Date: Mon, 2 May 2022 11:48:22 -0400
Subject: [PATCH 0245/1731] drm/amd/display: Set default value of
 line_capture_indication

[Why & how]
We only support line capture indication as 0 for PSRSU

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 6883dd5b80d66..bc4943205bce1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -339,6 +339,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 	else
 		copy_settings_data->su_y_granularity = psr_context->su_y_granularity;
 
+	copy_settings_data->line_capture_indication = 0;
 	copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
 	copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
 	copy_settings_data->cmd_version =  DMUB_CMD_PSR_CONTROL_VERSION_1;
-- 
GitLab


From 32c453f18dccd93a27d6f026ca690167c8cc9639 Mon Sep 17 00:00:00 2001
From: David Zhang <dingchen.zhang@amd.com>
Date: Mon, 2 May 2022 11:59:58 -0400
Subject: [PATCH 0246/1731] drm/amd/display: add vline time in micro sec to PSR
 context

[why]
The current PSR SU programming margin is fixed base on FHD 60HZ
panel. If the resolution and refresh rate become higher, the time
of current margin might not cover the programming SU time.

[how]
Notice that the programming SU time is the same among different
panels.

Instead of fixing the margin with target line number, change the
margin unit to micro second which indicate the time needed for
programming SU. Then FW set the margin line number base on the
line time and margin time.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 ++
 drivers/gpu/drm/amd/display/dc/dc_types.h     | 2 ++
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 1 +
 3 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index dc1d75b204cde..68e9fc6b510cb 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3274,6 +3274,8 @@ bool dc_link_setup_psr(struct dc_link *link,
 			psr_config->su_granularity_required;
 		psr_context->su_y_granularity =
 			psr_config->su_y_granularity;
+		psr_context->line_time_in_us =
+			psr_config->line_time_in_us;
 	}
 
 	psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index d61ea3e2bfbfb..119ce8b7a5558 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -676,6 +676,7 @@ struct psr_config {
 	bool su_granularity_required;
 	/* psr2 selective update y granularity capability */
 	uint8_t su_y_granularity;
+	unsigned int line_time_in_us;
 };
 
 union dmcu_psr_level {
@@ -783,6 +784,7 @@ struct psr_context {
 	bool su_granularity_required;
 	/* psr2 selective update y granularity capability */
 	uint8_t su_y_granularity;
+	unsigned int line_time_in_us;
 };
 
 struct colorspace_transform {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index bc4943205bce1..c2d65756ce5d0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -340,6 +340,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 		copy_settings_data->su_y_granularity = psr_context->su_y_granularity;
 
 	copy_settings_data->line_capture_indication = 0;
+	copy_settings_data->line_time_in_us = psr_context->line_time_in_us;
 	copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
 	copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
 	copy_settings_data->cmd_version =  DMUB_CMD_PSR_CONTROL_VERSION_1;
-- 
GitLab


From 6cc5c77300afbb285c4f41e04f3435ae3c484c40 Mon Sep 17 00:00:00 2001
From: David Zhang <dingchen.zhang@amd.com>
Date: Tue, 3 May 2022 10:49:52 -0400
Subject: [PATCH 0247/1731] drm/amd/display: fix system hang when PSR exits

[why]
When DC driver send PSR exit dmub command to DMUB FW, it might not
wait until PSR exit. Then it may hit the following deadlock situation.
1. DC driver send HW LOCK command to DMUB FW due to frame update
2. DMUB FW Set the HW lock
3. DMUB execute PSR exit sequence and stuck at polling DPG Pending
register due to the HW Lock is set
4. DC driver ask DMUB FW to unlock HW lock, but DMUB FW is polling
DPG pending register

[how]
The reason why DC driver doesn't wait until PSR exit is because some of
the PSR state machine state is not update the dc driver. So when DC
driver read back the PSR state, it take the state for PSR inactive.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc_types.h     |  7 +++++++
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 16 ++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 119ce8b7a5558..144c387010c23 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -657,10 +657,17 @@ enum dc_psr_state {
 	PSR_STATE4b,
 	PSR_STATE4c,
 	PSR_STATE4d,
+	PSR_STATE4_FULL_FRAME,
+	PSR_STATE4a_FULL_FRAME,
+	PSR_STATE4b_FULL_FRAME,
+	PSR_STATE4c_FULL_FRAME,
+	PSR_STATE4_FULL_FRAME_POWERUP,
 	PSR_STATE5,
 	PSR_STATE5a,
 	PSR_STATE5b,
 	PSR_STATE5c,
+	PSR_STATE_HWLOCK_MGR,
+	PSR_STATE_POLLVUPDATE,
 	PSR_STATE_INVALID = 0xFF
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index c2d65756ce5d0..e784002fe312f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -74,6 +74,22 @@ static enum dc_psr_state convert_psr_state(uint32_t raw_state)
 		state = PSR_STATE5b;
 	else if (raw_state == 0x53)
 		state = PSR_STATE5c;
+	else if (raw_state == 0x4A)
+		state = PSR_STATE4_FULL_FRAME;
+	else if (raw_state == 0x4B)
+		state = PSR_STATE4a_FULL_FRAME;
+	else if (raw_state == 0x4C)
+		state = PSR_STATE4b_FULL_FRAME;
+	else if (raw_state == 0x4D)
+		state = PSR_STATE4c_FULL_FRAME;
+	else if (raw_state == 0x4E)
+		state = PSR_STATE4_FULL_FRAME_POWERUP;
+	else if (raw_state == 0x60)
+		state = PSR_STATE_HWLOCK_MGR;
+	else if (raw_state == 0x61)
+		state = PSR_STATE_POLLVUPDATE;
+	else
+		state = PSR_STATE_INVALID;
 
 	return state;
 }
-- 
GitLab


From c7eac19eda0a82f0c1dd9455012754445772fd09 Mon Sep 17 00:00:00 2001
From: David Zhang <dingchen.zhang@amd.com>
Date: Tue, 3 May 2022 10:56:54 -0400
Subject: [PATCH 0248/1731] drm/amd/display: Set PSR level to enable ALPM by
 default

[Why & How]
While support ALPM, do ALPM state transition while PSR entry/exit.
ALPM is needed for PSR-SU feature, and since the function is ready,
we'd enable it by default.

- Add psr level definition to enable/disable ALPM and set ALPM
  powerdone mode.
- Enable ALPM by default

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++++
 drivers/gpu/drm/amd/display/dc/dc_types.h     | 4 +++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 68e9fc6b510cb..31ffb961e18b5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3364,6 +3364,10 @@ bool dc_link_setup_psr(struct dc_link *link,
 	 */
 	psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
 
+	/* enable ALPM */
+	psr_context->psr_level.bits.DISABLE_ALPM = 0;
+	psr_context->psr_level.bits.ALPM_DEFAULT_PD_MODE = 1;
+
 	/* Controls additional delay after remote frame capture before
 	 * continuing power down, default = 0
 	 */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 144c387010c23..26b62f50ac4e9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -698,7 +698,9 @@ union dmcu_psr_level {
 		unsigned int SKIP_AUTO_STATE_ADVANCE:1;
 		unsigned int DISABLE_PSR_ENTRY_ABORT:1;
 		unsigned int SKIP_SINGLE_OTG_DISABLE:1;
-		unsigned int RESERVED:22;
+		unsigned int DISABLE_ALPM:1;
+		unsigned int ALPM_DEFAULT_PD_MODE:1;
+		unsigned int RESERVED:20;
 	} bits;
 	unsigned int u32all;
 };
-- 
GitLab


From c2a050c5e07faf9ed2fa1daa1eb642d9da4a879d Mon Sep 17 00:00:00 2001
From: David Zhang <dingchen.zhang@amd.com>
Date: Tue, 3 May 2022 17:28:18 -0400
Subject: [PATCH 0249/1731] drm/amd/display: use HW lock mgr for PSR-SU

[why]
Feature requires synchronization of dig, pipe, and cursor locking
between driver and DMUB fw for PSR-SU

[how]
return True if PSR-SU in the checker should_use_dmub_lock()

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
index b1b2e3c6f379d..3f32e9c3fbaf4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
@@ -65,5 +65,7 @@ void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
 
 bool should_use_dmub_lock(struct dc_link *link)
 {
+	if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
+		return true;
 	return false;
 }
-- 
GitLab


From e61a048eabf9d1245f86e67ec4787d2f10e5a1e0 Mon Sep 17 00:00:00 2001
From: David Zhang <dingchen.zhang@amd.com>
Date: Tue, 3 May 2022 18:19:39 -0400
Subject: [PATCH 0250/1731] drm/amd/display: PSRSU+DSC WA for specific TCON

[why]
Some specific TCON chip has HW limitation to support PSRSU+DSC.

[how]
Force ffu mode when DSC enabled if we detect it is the specific
model from sink OUI DPCD. And disable ABM update for this case.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc_link.h      |  1 +
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 14 ++++++++++++++
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index a3c37ee3f849c..0bec986a6de81 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -108,6 +108,7 @@ struct psr_settings {
 	 */
 	bool psr_frame_capture_indication_req;
 	unsigned int psr_sdp_transmit_line_num_deadline;
+	uint8_t force_ffu_mode;
 	unsigned int psr_power_opt;
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index e784002fe312f..9ca0cbb0af9b2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -349,6 +349,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 	copy_settings_data->debug.u32All = 0;
 	copy_settings_data->debug.bitfields.visual_confirm	= dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR;
 	copy_settings_data->debug.bitfields.use_hw_lock_mgr		= 1;
+	copy_settings_data->debug.bitfields.force_full_frame_update	= 0;
 
 	if (psr_context->su_granularity_required == 0)
 		copy_settings_data->su_y_granularity = 0;
@@ -363,6 +364,19 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 	copy_settings_data->panel_inst = panel_inst;
 	copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);
 
+	/**
+	 * WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update)
+	 * Note that PSRSU+DSC is still under development.
+	 */
+	if (copy_settings_data->dsc_enable_status &&
+		link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 &&
+		!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1,
+			sizeof(link->dpcd_caps.sink_dev_id_str)))
+		link->psr_settings.force_ffu_mode = 1;
+	else
+		link->psr_settings.force_ffu_mode = 0;
+	copy_settings_data->force_ffu_mode = link->psr_settings.force_ffu_mode;
+
 	if (link->fec_state == dc_link_fec_enabled &&
 		(!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1,
 			sizeof(link->dpcd_caps.sink_dev_id_str)) ||
-- 
GitLab


From 65e7a17499e15771339d85eaa1ba686ad2fe342c Mon Sep 17 00:00:00 2001
From: David Zhang <dingchen.zhang@amd.com>
Date: Mon, 25 Apr 2022 18:08:13 -0400
Subject: [PATCH 0251/1731] drm/amd/display: add shared helpers to update psr
 config fields to power module

[why]
Currently the amdgpu DM psr configuration parameters are hardcoded
before feeding into the DC helper to setup PSR. We would define a
helper which is to calculate parts of the psr config fields to
avoid hard-coding.

[how]
To make helper shareable, declare and define the helper in the
module_helper, to set/update below fields:
- psr remote buffer setup time
- sdp tx line number deadline
- line time in us
- su_y_granularity
- su_granularity_required
- psr_frame_capture_indication_req
- psr_exit_link_training_required

add another helper to check given the stream context, if there is
only one stream and the output is eDP panel connected.

changes in v2:
------------------
- add detailed comment for how psr setup time is calculated as per
  eDP 1.5 spec

Cc: Chandan Vurdigerenataraj <chandan.vurdigerenataraj@amd.com>

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../amd/display/modules/power/power_helpers.c | 84 +++++++++++++++++++
 .../amd/display/modules/power/power_helpers.h |  6 ++
 2 files changed, 90 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index 97928d4c3b9ab..bc239d38c3c7e 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -822,3 +822,87 @@ bool is_psr_su_specific_panel(struct dc_link *link)
 
 	return false;
 }
+
+/**
+ * mod_power_calc_psr_configs() - calculate/update generic psr configuration fields.
+ * @psr_config: [output], psr configuration structure to be updated
+ * @link: [input] dc link pointer
+ * @stream: [input] dc stream state pointer
+ *
+ * calculate and update the psr configuration fields that are not DM specific, i.e. such
+ * fields which are based on DPCD caps or timing information. To setup PSR in DMUB FW,
+ * this helper is assumed to be called before the call of the DC helper dc_link_setup_psr().
+ *
+ * PSR config fields to be updated within the helper:
+ * - psr_rfb_setup_time
+ * - psr_sdp_transmit_line_num_deadline
+ * - line_time_in_us
+ * - su_y_granularity
+ * - su_granularity_required
+ * - psr_frame_capture_indication_req
+ * - psr_exit_link_training_required
+ *
+ * PSR config fields that are DM specific and NOT updated within the helper:
+ * - allow_smu_optimizations
+ * - allow_multi_disp_optimizations
+ */
+void mod_power_calc_psr_configs(struct psr_config *psr_config,
+		struct dc_link *link,
+		const struct dc_stream_state *stream)
+{
+	unsigned int num_vblank_lines = 0;
+	unsigned int vblank_time_in_us = 0;
+	unsigned int sdp_tx_deadline_in_us = 0;
+	unsigned int line_time_in_us = 0;
+	struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
+	const int psr_setup_time_step_in_us = 55;	/* refer to eDP spec DPCD 0x071h */
+
+	/* timing parameters */
+	num_vblank_lines = stream->timing.v_total -
+			 stream->timing.v_addressable -
+			 stream->timing.v_border_top -
+			 stream->timing.v_border_bottom;
+
+	vblank_time_in_us = (stream->timing.h_total * num_vblank_lines * 1000) / (stream->timing.pix_clk_100hz / 10);
+
+	line_time_in_us = ((stream->timing.h_total * 1000) / (stream->timing.pix_clk_100hz / 10)) + 1;
+
+	/**
+	 * psr configuration fields
+	 *
+	 * as per eDP 1.5 pg. 377 of 459, DPCD 0x071h bits [3:1], psr setup time bits interpreted as below
+	 * 000b <--> 330 us (default)
+	 * 001b <--> 275 us
+	 * 010b <--> 220 us
+	 * 011b <--> 165 us
+	 * 100b <--> 110 us
+	 * 101b <--> 055 us
+	 * 110b <--> 000 us
+	 */
+	psr_config->psr_rfb_setup_time =
+		(6 - dpcd_caps->psr_info.psr_dpcd_caps.bits.PSR_SETUP_TIME) * psr_setup_time_step_in_us;
+
+	if (psr_config->psr_rfb_setup_time > vblank_time_in_us) {
+		link->psr_settings.psr_frame_capture_indication_req = true;
+		link->psr_settings.psr_sdp_transmit_line_num_deadline = num_vblank_lines;
+	} else {
+		sdp_tx_deadline_in_us = vblank_time_in_us - psr_config->psr_rfb_setup_time;
+
+		/* Set the last possible line SDP may be transmitted without violating the RFB setup time */
+		link->psr_settings.psr_frame_capture_indication_req = false;
+		link->psr_settings.psr_sdp_transmit_line_num_deadline = sdp_tx_deadline_in_us / line_time_in_us;
+	}
+
+	psr_config->psr_sdp_transmit_line_num_deadline = link->psr_settings.psr_sdp_transmit_line_num_deadline;
+	psr_config->line_time_in_us = line_time_in_us;
+	psr_config->su_y_granularity = dpcd_caps->psr_info.psr2_su_y_granularity_cap;
+	psr_config->su_granularity_required = dpcd_caps->psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED;
+	psr_config->psr_frame_capture_indication_req = link->psr_settings.psr_frame_capture_indication_req;
+	psr_config->psr_exit_link_training_required =
+		!link->dpcd_caps.psr_info.psr_dpcd_caps.bits.LINK_TRAINING_ON_EXIT_NOT_REQUIRED;
+}
+
+bool mod_power_only_edp(const struct dc_state *context, const struct dc_stream_state *stream)
+{
+	return context && context->stream_count == 1 && dc_is_embedded_signal(stream->signal);
+}
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
index 1a634d8c78c58..316452e9dbc91 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
@@ -27,6 +27,7 @@
 
 #include "dc/inc/hw/dmcu.h"
 #include "dc/inc/hw/abm.h"
+#include "dc/inc/core_types.h"
 
 struct resource_pool;
 
@@ -53,4 +54,9 @@ bool dmub_init_abm_config(struct resource_pool *res_pool,
 		unsigned int inst);
 
 bool is_psr_su_specific_panel(struct dc_link *link);
+void mod_power_calc_psr_configs(struct psr_config *psr_config,
+		struct dc_link *link,
+		const struct dc_stream_state *stream);
+bool mod_power_only_edp(const struct dc_state *context,
+		const struct dc_stream_state *stream);
 #endif /* MODULES_POWER_POWER_HELPERS_H_ */
-- 
GitLab


From 381b590c307f29d0990c4b99ae3a2e02aff2a5b9 Mon Sep 17 00:00:00 2001
From: David Zhang <dingchen.zhang@amd.com>
Date: Tue, 26 Apr 2022 11:44:02 -0400
Subject: [PATCH 0252/1731] drm/amd/display: calculate psr config settings in
 runtime in DM

[why]
Currently the psr configuration parameters are hardcoded before
feeding into the DC helper before passing to DMUB FW. We'd rework
to call a shared helper to calculate/update generic psr config
fields which are relying on the stream timing and eDP sink PSR
caps to avoid hard-coding.

[how]
- drop part of hard-coded psr config fields by replacing w/ the
  call of helper from DM before feeding into DC link setup psr
  helper
- For those DM specific psr config fields, e.g. allow smu opt, is
  not to be set/updated from the shared helper but to rely on the
  DC feature mask
- for the psr version field in psr_config structure, since only
  the field psr_version of DC link psr_settings matters for that
  fed to DMUB FW, thus no need to set/update the psr_version field
  of psr_config structure.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
index 141fd2721501e..52508bdda8e95 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -97,19 +97,24 @@ bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
 	struct dc_link *link = NULL;
 	struct psr_config psr_config = {0};
 	struct psr_context psr_context = {0};
+	struct dc *dc = NULL;
 	bool ret = false;
 
 	if (stream == NULL)
 		return false;
 
 	link = stream->link;
+	dc = link->ctx->dc;
 
 	if (link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) {
-		psr_config.psr_version = link->psr_settings.psr_version;
-		psr_config.psr_frame_capture_indication_req = 0;
-		psr_config.psr_rfb_setup_time = 0x37;
-		psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
-		psr_config.allow_smu_optimizations = 0x0;
+		mod_power_calc_psr_configs(&psr_config, link, stream);
+
+		/* linux DM specific updating for psr config fields */
+		psr_config.allow_smu_optimizations =
+			(amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT) &&
+			mod_power_only_edp(dc->current_state, stream);
+		psr_config.allow_multi_disp_optimizations =
+			(amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT);
 
 		ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
 
-- 
GitLab


From 1b0da5a3e90d3920f6967e4303fdeaaec6f62208 Mon Sep 17 00:00:00 2001
From: David Zhang <dingchen.zhang@amd.com>
Date: Wed, 4 May 2022 12:30:24 -0400
Subject: [PATCH 0253/1731] drm/amd/display: update cursor position to DMUB FW

[why]
To involve the cursor position into dirty rectangle calculation.

[how]
- separate plane and cursor update by different DMUB command
- send the cursor information while cursor updating, when updating
  cursor position/attribute, store cursor pos/attr to hubp, and
  notify dmub FW to exit psr before program cursor registers

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |   2 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 131 ++++++++++++++++++
 .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c |   2 +
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |   1 +
 4 files changed, 136 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 3a7f76e2c5989..564e061ccb589 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -1188,6 +1188,8 @@ void hubp1_cursor_set_position(
 	uint32_t dst_x_offset;
 	uint32_t cur_en = pos->enable ? 1 : 0;
 
+	hubp->curs_pos = *pos;
+
 	/*
 	 * Guard aganst cursor_set_position() from being called with invalid
 	 * attributes
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index e3a62873c0e70..351a923fbf735 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -51,6 +51,8 @@
 #include "link_hwss.h"
 #include "dpcd_defs.h"
 #include "dsc.h"
+#include "dce/dmub_psr.h"
+#include "dc_dmub_srv.h"
 #include "dce/dmub_hw_lock_mgr.h"
 #include "dc_trace.h"
 #include "dce/dmub_outbox.h"
@@ -3328,6 +3330,115 @@ static bool dcn10_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
 	return false;
 }
 
+static void dcn10_dmub_update_cursor_data(
+		struct pipe_ctx *pipe_ctx,
+		struct hubp *hubp,
+		const struct dc_cursor_mi_param *param,
+		const struct dc_cursor_position *cur_pos,
+		const struct dc_cursor_attributes *cur_attr)
+{
+	union dmub_rb_cmd cmd;
+	struct dmub_cmd_update_cursor_info_data *update_cursor_info;
+	const struct dc_cursor_position *pos;
+	const struct dc_cursor_attributes *attr;
+	int src_x_offset = 0;
+	int src_y_offset = 0;
+	int x_hotspot = 0;
+	int cursor_height = 0;
+	int cursor_width = 0;
+	uint32_t cur_en = 0;
+	unsigned int panel_inst = 0;
+
+	struct dc_debug_options *debug = &hubp->ctx->dc->debug;
+
+	if (!debug->enable_sw_cntl_psr && pipe_ctx->stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1)
+		return;
+
+	if (pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED ||
+		pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
+		return;
+
+	/**
+	 * if cur_pos == NULL means the caller is from cursor_set_attribute
+	 * then driver use previous cursor position data
+	 * if cur_attr == NULL means the caller is from cursor_set_position
+	 * then driver use previous cursor attribute
+	 * if cur_pos or cur_attr is not NULL then update it
+	 */
+	if (cur_pos != NULL)
+		pos = cur_pos;
+	else
+		pos = &hubp->curs_pos;
+
+	if (cur_attr != NULL)
+		attr = cur_attr;
+	else
+		attr = &hubp->curs_attr;
+
+	if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, pipe_ctx->stream->link, &panel_inst))
+		return;
+
+	src_x_offset = pos->x - pos->x_hotspot - param->viewport.x;
+	src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
+	x_hotspot = pos->x_hotspot;
+	cursor_height = (int)attr->height;
+	cursor_width = (int)attr->width;
+	cur_en = pos->enable ? 1:0;
+
+	// Rotated cursor width/height and hotspots tweaks for offset calculation
+	if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
+		swap(cursor_height, cursor_width);
+		if (param->rotation == ROTATION_ANGLE_90) {
+			src_x_offset = pos->x - pos->y_hotspot - param->viewport.x;
+			src_y_offset = pos->y - pos->x_hotspot - param->viewport.y;
+		}
+	} else if (param->rotation == ROTATION_ANGLE_180) {
+		src_x_offset = pos->x - param->viewport.x;
+		src_y_offset = pos->y - param->viewport.y;
+	}
+
+	if (param->mirror) {
+		x_hotspot = param->viewport.width - x_hotspot;
+		src_x_offset = param->viewport.x + param->viewport.width - src_x_offset;
+	}
+
+	if (src_x_offset >= (int)param->viewport.width)
+		cur_en = 0;  /* not visible beyond right edge*/
+
+	if (src_x_offset + cursor_width <= 0)
+		cur_en = 0;  /* not visible beyond left edge*/
+
+	if (src_y_offset >= (int)param->viewport.height)
+		cur_en = 0;  /* not visible beyond bottom edge*/
+
+	if (src_y_offset + cursor_height <= 0)
+		cur_en = 0;  /* not visible beyond top edge*/
+
+	// Cursor bitmaps have different hotspot values
+	// There's a possibility that the above logic returns a negative value, so we clamp them to 0
+	if (src_x_offset < 0)
+		src_x_offset = 0;
+	if (src_y_offset < 0)
+		src_y_offset = 0;
+
+	memset(&cmd, 0x0, sizeof(cmd));
+	cmd.update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO;
+	cmd.update_cursor_info.header.payload_bytes =
+			sizeof(cmd.update_cursor_info.update_cursor_info_data);
+	update_cursor_info = &cmd.update_cursor_info.update_cursor_info_data;
+	update_cursor_info->cursor_rect.x = src_x_offset + param->viewport.x;
+	update_cursor_info->cursor_rect.y = src_y_offset + param->viewport.y;
+	update_cursor_info->cursor_rect.width = attr->width;
+	update_cursor_info->cursor_rect.height = attr->height;
+	update_cursor_info->enable = cur_en;
+	update_cursor_info->pipe_idx = pipe_ctx->pipe_idx;
+	update_cursor_info->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
+	update_cursor_info->panel_inst = panel_inst;
+	dc_dmub_srv_cmd_queue(pipe_ctx->stream->ctx->dmub_srv, &cmd);
+	dc_dmub_srv_cmd_execute(pipe_ctx->stream->ctx->dmub_srv);
+	dc_dmub_srv_wait_idle(pipe_ctx->stream->ctx->dmub_srv);
+}
+
 void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
 {
 	struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
@@ -3526,6 +3637,7 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
 			pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.y;
 	}
 
+	dcn10_dmub_update_cursor_data(pipe_ctx, hubp, &param, &pos_cpy, NULL);
 	hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
 	dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);
 }
@@ -3533,6 +3645,25 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
 void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
 {
 	struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
+	struct dc_cursor_mi_param param = { 0 };
+
+	/**
+	 * If enter PSR without cursor attribute update
+	 * the cursor attribute of dmub_restore_plane
+	 * are initial value. call dmub to exit PSR and
+	 * restore plane then update cursor attribute to
+	 * avoid override with initial value
+	 */
+	if (pipe_ctx->plane_state != NULL) {
+		param.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
+		param.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz;
+		param.viewport = pipe_ctx->plane_res.scl_data.viewport;
+		param.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz;
+		param.v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert;
+		param.rotation = pipe_ctx->plane_state->rotation;
+		param.mirror = pipe_ctx->plane_state->horizontal_mirror;
+		dcn10_dmub_update_cursor_data(pipe_ctx, pipe_ctx->plane_res.hubp, &param, NULL, attributes);
+	}
 
 	pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
 			pipe_ctx->plane_res.hubp, attributes);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
index a665af19f2017..9570c2118ccc7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
@@ -967,6 +967,8 @@ void hubp2_cursor_set_position(
 	uint32_t dst_x_offset;
 	uint32_t cur_en = pos->enable ? 1 : 0;
 
+	hubp->curs_pos = *pos;
+
 	/*
 	 * Guard aganst cursor_set_position() from being called with invalid
 	 * attributes
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index b2cdb6bfc9b88..906818e792dd1 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -63,6 +63,7 @@ struct hubp {
 	int opp_id;
 	int mpcc_id;
 	struct dc_cursor_attributes curs_attr;
+	struct dc_cursor_position curs_pos;
 	bool power_gated;
 };
 
-- 
GitLab


From 7cc191ee7621b7145c6cc9c18a4e1929bb5f136e Mon Sep 17 00:00:00 2001
From: Leo Li <sunpeng.li@amd.com>
Date: Wed, 30 Mar 2022 12:45:09 -0400
Subject: [PATCH 0254/1731] drm/amd/display: Implement MPO PSR SU

[WHY]

For additional power savings, PSR SU (also referred to as PSR2) can be
enabled on eDP panels with PSR SU support.

PSR2 saves more power compared to PSR1 by allowing more opportunities
for the display hardware to be shut down. In comparison to PSR1, Shut
down can now occur in-between frames, as well as in display regions
where there is no visible update. In otherwords, it allows for some
display hw components to be enabled only for a **selectively updated**
region of the visible display. Hence PSR SU.

[HOW]

To define the SU region, support from the OS is required. OS needs to
inform driver of damaged regions that need to be flushed to the eDP
panel. Today, such support is lacking in most compositors.

Therefore, an in-between solution is to implement PSR SU for MPO and
cursor scenarios. The plane bounds can be used to define the damaged
region to be flushed to panel. This is achieved by:

* Leveraging dm_crtc_state->mpo_requested flag to identify when MPO is
  enabled.
* If MPO is enabled, only add updated plane bounds to dirty region.
  Determine plane update by either:
    * Existence of drm damaged clips attached to the plane (added by a
      damage-aware compositor)
    * Change in fb id (flip)
    * Change in plane bounds (position and dimensions)
* If cursor is enabled, the old_pos and new_pos of cursor plus cursor
  size is used as damaged regions(*).

(*) Cursor updates follow a different code path through DC. PSR SU for
cursor is already implemented in DC, and the only thing required to
enable is to set DC_PSR_VERSION_SU_1 on the eDP link. See
dcn10_dmub_update_cursor_data().

Signed-off-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 142 +++++++++++++++++-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c |   6 +-
 2 files changed, 144 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 872b7899b645b..2bb316fa62b1e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1265,10 +1265,20 @@ static void vblank_control_worker(struct work_struct *work)
 
 	DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0);
 
-	/* Control PSR based on vblank requirements from OS */
+	/*
+	 * Control PSR based on vblank requirements from OS
+	 *
+	 * If panel supports PSR SU, there's no need to disable PSR when OS is
+	 * submitting fast atomic commits (we infer this by whether the OS
+	 * requests vblank events). Fast atomic commits will simply trigger a
+	 * full-frame-update (FFU); a specific case of selective-update (SU)
+	 * where the SU region is the full hactive*vactive region. See
+	 * fill_dc_dirty_rects().
+	 */
 	if (vblank_work->stream && vblank_work->stream->link) {
 		if (vblank_work->enable) {
-			if (vblank_work->stream->link->psr_settings.psr_allow_active)
+			if (vblank_work->stream->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 &&
+			    vblank_work->stream->link->psr_settings.psr_allow_active)
 				amdgpu_dm_psr_disable(vblank_work->stream);
 		} else if (vblank_work->stream->link->psr_settings.psr_feature_enabled &&
 			   !vblank_work->stream->link->psr_settings.psr_allow_active &&
@@ -5733,6 +5743,117 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,
 	return 0;
 }
 
+/**
+ * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
+ *
+ * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
+ *         remote fb
+ * @old_plane_state: Old state of @plane
+ * @new_plane_state: New state of @plane
+ * @crtc_state: New state of CRTC connected to the @plane
+ * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
+ *
+ * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
+ * (referred to as "damage clips" in DRM nomenclature) that require updating on
+ * the eDP remote buffer. The responsibility of specifying the dirty regions is
+ * amdgpu_dm's.
+ *
+ * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
+ * plane with regions that require flushing to the eDP remote buffer. In
+ * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
+ * implicitly provide damage clips without any client support via the plane
+ * bounds.
+ *
+ * Today, amdgpu_dm only supports the MPO and cursor usecase.
+ *
+ * TODO: Also enable for FB_DAMAGE_CLIPS
+ */
+static void fill_dc_dirty_rects(struct drm_plane *plane,
+				struct drm_plane_state *old_plane_state,
+				struct drm_plane_state *new_plane_state,
+				struct drm_crtc_state *crtc_state,
+				struct dc_flip_addrs *flip_addrs)
+{
+	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
+	struct rect *dirty_rects = flip_addrs->dirty_rects;
+	uint32_t num_clips;
+	bool bb_changed;
+	bool fb_changed;
+	uint32_t i = 0;
+
+	flip_addrs->dirty_rect_count = 0;
+
+	/*
+	 * Cursor plane has it's own dirty rect update interface. See
+	 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
+	 */
+	if (plane->type == DRM_PLANE_TYPE_CURSOR)
+		return;
+
+	/*
+	 * Today, we only consider MPO use-case for PSR SU. If MPO not
+	 * requested, and there is a plane update, do FFU.
+	 */
+	if (!dm_crtc_state->mpo_requested) {
+		dirty_rects[0].x = 0;
+		dirty_rects[0].y = 0;
+		dirty_rects[0].width = dm_crtc_state->base.mode.crtc_hdisplay;
+		dirty_rects[0].height = dm_crtc_state->base.mode.crtc_vdisplay;
+		flip_addrs->dirty_rect_count = 1;
+		DRM_DEBUG_DRIVER("[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
+				 new_plane_state->plane->base.id,
+				 dm_crtc_state->base.mode.crtc_hdisplay,
+				 dm_crtc_state->base.mode.crtc_vdisplay);
+		return;
+	}
+
+	/*
+	 * MPO is requested. Add entire plane bounding box to dirty rects if
+	 * flipped to or damaged.
+	 *
+	 * If plane is moved or resized, also add old bounding box to dirty
+	 * rects.
+	 */
+	num_clips = drm_plane_get_damage_clips_count(new_plane_state);
+	fb_changed = old_plane_state->fb->base.id !=
+		     new_plane_state->fb->base.id;
+	bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
+		      old_plane_state->crtc_y != new_plane_state->crtc_y ||
+		      old_plane_state->crtc_w != new_plane_state->crtc_w ||
+		      old_plane_state->crtc_h != new_plane_state->crtc_h);
+
+	DRM_DEBUG_DRIVER("[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
+			 new_plane_state->plane->base.id,
+			 bb_changed, fb_changed, num_clips);
+
+	if (num_clips || fb_changed || bb_changed) {
+		dirty_rects[i].x = new_plane_state->crtc_x;
+		dirty_rects[i].y = new_plane_state->crtc_y;
+		dirty_rects[i].width = new_plane_state->crtc_w;
+		dirty_rects[i].height = new_plane_state->crtc_h;
+		DRM_DEBUG_DRIVER("[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)\n",
+				 new_plane_state->plane->base.id,
+				 dirty_rects[i].x, dirty_rects[i].y,
+				 dirty_rects[i].width, dirty_rects[i].height);
+		i += 1;
+	}
+
+	/* Add old plane bounding-box if plane is moved or resized */
+	if (bb_changed) {
+		dirty_rects[i].x = old_plane_state->crtc_x;
+		dirty_rects[i].y = old_plane_state->crtc_y;
+		dirty_rects[i].width = old_plane_state->crtc_w;
+		dirty_rects[i].height = old_plane_state->crtc_h;
+		DRM_DEBUG_DRIVER("[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)\n",
+				old_plane_state->plane->base.id,
+				dirty_rects[i].x, dirty_rects[i].y,
+				dirty_rects[i].width, dirty_rects[i].height);
+		i += 1;
+	}
+
+	flip_addrs->dirty_rect_count = i;
+}
+
 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
 					   const struct dm_connector_state *dm_state,
 					   struct dc_stream_state *stream)
@@ -6681,6 +6802,7 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
 	state->cm_has_degamma = cur->cm_has_degamma;
 	state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
 	state->force_dpms_off = cur->force_dpms_off;
+	state->mpo_requested = cur->mpo_requested;
 	/* TODO Duplicate dc_stream after objects are stream object is flattened */
 
 	return &state->base;
@@ -9328,6 +9450,10 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 		bundle->surface_updates[planes_count].plane_info =
 			&bundle->plane_infos[planes_count];
 
+		fill_dc_dirty_rects(plane, old_plane_state, new_plane_state,
+				    new_crtc_state,
+				    &bundle->flip_addrs[planes_count]);
+
 		/*
 		 * Only allow immediate flips for fast updates that don't
 		 * change FB pitch, DCC state, rotation or mirroing.
@@ -9523,6 +9649,18 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 
 			/* Allow PSR when skip count is 0. */
 			acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
+
+			/*
+			 * If sink supports PSR SU, there is no need to rely on
+			 * a vblank event disable request to enable PSR. PSR SU
+			 * can be enabled immediately once OS demonstrates an
+			 * adequate number of fast atomic commits to notify KMD
+			 * of update events. See `vblank_control_worker()`.
+			 */
+			if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
+			    acrtc_attach->dm_irq_params.allow_psr_entry &&
+			    !acrtc_state->stream->link->psr_settings.psr_allow_active)
+				amdgpu_dm_psr_enable(acrtc_state->stream);
 		} else {
 			acrtc_attach->dm_irq_params.allow_psr_entry = false;
 		}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
index 52508bdda8e95..c8da18e45b0e8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -79,10 +79,12 @@ void amdgpu_dm_set_psr_caps(struct dc_link *link)
 		link->psr_settings.psr_feature_enabled = true;
 	}
 
-	DRM_INFO("PSR support %d, DC PSR ver %d, sink PSR ver %d\n",
+	DRM_INFO("PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n",
 		link->psr_settings.psr_feature_enabled,
 		link->psr_settings.psr_version,
-		link->dpcd_caps.psr_info.psr_version);
+		link->dpcd_caps.psr_info.psr_version,
+		link->dpcd_caps.psr_info.psr_dpcd_caps.raw,
+		link->dpcd_caps.psr_info.psr2_su_y_granularity_cap);
 
 }
 
-- 
GitLab


From 84de5c2e92dccb2bcfd5ff68af44960b808fe6bb Mon Sep 17 00:00:00 2001
From: Gabe Teeger <gabe.teeger@amd.com>
Date: Thu, 12 May 2022 12:47:23 -0400
Subject: [PATCH 0255/1731] drm/amd/display: Update optimized blank calc and
 programming

[Why]
The existing calculations in DCN3.1 were placeholder and need to be
replaced with HW team approved calculations.

[How]
The new calculations add new parameters to the bounding box and pipe
params - VblankNom and the bounding box default.

The placeholder calculations are dropped from DCN3.1 in the meantime
while we work out hardware approved replacements.
Also fix a bug where we wipe out other register contents with a REG_SET
instead of a REG_UPDATE for the register we were programming the
min_dst_y_next_start_optimized.

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Gabe Teeger <gabe.teeger@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c    |  2 +-
 .../drm/amd/display/dc/dcn31/dcn31_resource.c    |  1 -
 .../dc/dml/dcn31/display_rq_dlg_calc_31.c        | 16 ++--------------
 .../amd/display/dc/dml/display_mode_structs.h    |  1 +
 .../drm/amd/display/dc/dml/display_mode_vba.h    |  1 +
 5 files changed, 5 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c
index 197a5cae068b0..84e1486f3d515 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c
@@ -59,7 +59,7 @@ static void hubp31_program_extended_blank(struct hubp *hubp,
 {
 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 
-	REG_SET(BLANK_OFFSET_1, 0, MIN_DST_Y_NEXT_START, min_dst_y_next_start_optimized);
+	REG_UPDATE(BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, min_dst_y_next_start_optimized);
 }
 
 static struct hubp_funcs dcn31_hubp_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 3d9f07d4770bf..a67475251188f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1651,7 +1651,6 @@ int dcn31_populate_dml_pipes_from_context(
 			continue;
 		pipe = &res_ctx->pipe_ctx[i];
 		timing = &pipe->stream->timing;
-
 		if (pipe->plane_state &&
 				(pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||
 				pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width))
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
index 53d760e169e61..dd570689c095a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
@@ -1055,7 +1055,6 @@ static void dml_rq_dlg_get_dlg_params(
 
 	float vba__refcyc_per_req_delivery_pre_l = get_refcyc_per_req_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;  // From VBA
 	float vba__refcyc_per_req_delivery_l = get_refcyc_per_req_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;  // From VBA
-	int blank_lines;
 
 	memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs));
 	memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs));
@@ -1079,20 +1078,9 @@ static void dml_rq_dlg_get_dlg_params(
 	min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);	// From VBA
 
 	dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
-
 	disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2));
-	blank_lines = (dst->vblank_end + dst->vtotal_min - dst->vblank_start - dst->vstartup_start - 1);
-	if (blank_lines < 0)
-		blank_lines = 0;
-	if (blank_lines != 0) {
-		disp_dlg_regs->optimized_min_dst_y_next_start_us =
-			((unsigned int) blank_lines * dst->hactive) / (unsigned int) dst->pixel_rate_mhz;
-		disp_dlg_regs->optimized_min_dst_y_next_start =
-			(unsigned int)(((double) (dlg_vblank_start + blank_lines)) * dml_pow(2, 2));
-	} else {
-		// use unoptimized value
-		disp_dlg_regs->optimized_min_dst_y_next_start = disp_dlg_regs->min_dst_y_next_start;
-	}
+	disp_dlg_regs->optimized_min_dst_y_next_start_us = 0;
+	disp_dlg_regs->optimized_min_dst_y_next_start = disp_dlg_regs->min_dst_y_next_start;
 	ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
 
 	dml_print("DML_DLG: %s: min_ttu_vblank (us)         = %3.2f\n", __func__, min_ttu_vblank);
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 967d3e1ce8869..74afa10e70f89 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -329,6 +329,7 @@ struct _vcs_dpi_ip_params_st {
 	unsigned int number_of_cursors;
 	unsigned int max_num_dp2p0_outputs;
 	unsigned int max_num_dp2p0_streams;
+	unsigned int VBlankNomDefaultUS;
 };
 
 struct _vcs_dpi_display_xfc_params_st {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index ddf8b19c490e9..43e3270805521 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -465,6 +465,7 @@ struct vba_vars_st {
 	unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
 	bool XFCEnabled[DC__NUM_DPP__MAX];
 	bool ScalerEnabled[DC__NUM_DPP__MAX];
+	unsigned int VBlankNom[DC__NUM_DPP__MAX];
 
 	// Intermediates/Informational
 	bool ImmediateFlipSupport;
-- 
GitLab


From 453b0016a054df0f442fda8a145b97a33816cab9 Mon Sep 17 00:00:00 2001
From: Wayne Lin <Wayne.Lin@amd.com>
Date: Wed, 20 Apr 2022 10:32:15 +0800
Subject: [PATCH 0256/1731] drm/amd/display: Detect dpcd_rev when hotplug mst
 monitor

[Why]
Once mst topology is constructed, later on new connected monitors
are reported to source by CSN message. Within CSN, there is no
carried info of DPCD_REV comparing to LINK_ADDRESS reply. As the
result, we might leave some ports connected to DP but without DPCD
revision number which will affect us determining the capability of
the DP Rx.

[How]
Send out remote DPCD read when the port's dpcd_rev is 0x0 in
detect_ctx(). Firstly, read out the value from DPCD 0x2200. If the
return value is 0x0, it's likely the DP1.2 DP Rx then we reques
revision from DPCD 0x0 again.

Reviewed-by: Hersen Wu <hersenwu@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 38 ++++++++++++++++++-
 1 file changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 9221b6690a4a9..a6d551ff89d1f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -344,12 +344,48 @@ dm_dp_mst_detect(struct drm_connector *connector,
 {
 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 	struct amdgpu_dm_connector *master = aconnector->mst_port;
+	struct drm_dp_mst_port *port = aconnector->port;
+	int connection_status;
 
 	if (drm_connector_is_unregistered(connector))
 		return connector_status_disconnected;
 
-	return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
+	connection_status = drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
 				      aconnector->port);
+
+	if (port->pdt != DP_PEER_DEVICE_NONE && !port->dpcd_rev) {
+		uint8_t dpcd_rev;
+		int ret;
+
+		ret = drm_dp_dpcd_readb(&port->aux, DP_DP13_DPCD_REV, &dpcd_rev);
+
+		if (ret == 1) {
+			port->dpcd_rev = dpcd_rev;
+
+			/* Could be DP1.2 DP Rx case*/
+			if (!dpcd_rev) {
+				ret = drm_dp_dpcd_readb(&port->aux, DP_DPCD_REV, &dpcd_rev);
+
+				if (ret == 1)
+					port->dpcd_rev = dpcd_rev;
+			}
+
+			if (!dpcd_rev)
+				DRM_DEBUG_KMS("Can't decide DPCD revision number!");
+		}
+
+		/*
+		 * Could be legacy sink, logical port etc on DP1.2.
+		 * Will get Nack under these cases when issue remote
+		 * DPCD read.
+		 */
+		if (ret != 1)
+			DRM_DEBUG_KMS("Can't access DPCD");
+	} else if (port->pdt == DP_PEER_DEVICE_NONE) {
+		port->dpcd_rev = 0;
+	}
+
+	return connection_status;
 }
 
 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
-- 
GitLab


From 031ac4e419dfd8f099a0adba31f7f735013eb628 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Thu, 2 Jun 2022 12:06:12 -0400
Subject: [PATCH 0257/1731] drm/amdgpu/discovery: add comments about VCN
 instance handling

Add comments to clarify code that is safe, but triggers and
smatch warning.

Link: https://lists.freedesktop.org/archives/amd-gfx/2022-June/079905.html
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Dan Carpenter <dan.carpenter@oracle.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 91f21b725a434..b0811287f017f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1435,6 +1435,11 @@ static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)
 		return -EINVAL;
 	}
 
+	/* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
+	 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES
+	 * but that may change in the future with new GPUs so keep this
+	 * check for defensive purposes.
+	 */
 	if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) {
 		dev_err(adev->dev, "invalid vcn instances\n");
 		return -EINVAL;
@@ -1450,6 +1455,9 @@ static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)
 
 	switch (le16_to_cpu(vcn_info->v1.header.version_major)) {
 	case 1:
+		/* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
+		 * so this won't overflow.
+		 */
 		for (v = 0; v < adev->vcn.num_vcn_inst; v++) {
 			adev->vcn.vcn_codec_disable_mask[v] =
 				le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits);
-- 
GitLab


From b94b02d72e2b979a32addc8f5099fcf1f6ce9e7b Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Mon, 6 Jun 2022 09:59:52 -0400
Subject: [PATCH 0258/1731] drm/amdgpu/display: make some functions static

Fixes "no previous prototype" warnings.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c  | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c         | 8 ++++----
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c         | 2 +-
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 1db61029481ba..ed70ae10bdb1f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -487,7 +487,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 				clk_mgr_base->clks.dispclk_khz / 1000 / 7);
 }
 
-void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)
+static void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)
 {
 	struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
 	int ss_info_num = bp->funcs->get_ss_entry_number(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 8eeb3b69b5b93..0faa1abd35ba6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -662,8 +662,8 @@ void dccg31_init(struct dccg *dccg)
 	}
 }
 
-void dccg31_otg_add_pixel(struct dccg *dccg,
-		uint32_t otg_inst)
+static void dccg31_otg_add_pixel(struct dccg *dccg,
+				 uint32_t otg_inst)
 {
 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 
@@ -671,8 +671,8 @@ void dccg31_otg_add_pixel(struct dccg *dccg,
 			OTG_ADD_PIXEL[otg_inst], 1);
 }
 
-void dccg31_otg_drop_pixel(struct dccg *dccg,
-		uint32_t otg_inst)
+static void dccg31_otg_drop_pixel(struct dccg *dccg,
+				  uint32_t otg_inst)
 {
 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
index 08232d05d8943..152a76ad7957b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
@@ -177,7 +177,7 @@ void dccg32_set_dtbclk_dto(
 	}
 }
 
-void dccg32_set_valid_pixel_rate(
+static void dccg32_set_valid_pixel_rate(
 		struct dccg *dccg,
 		int ref_dtbclk_khz,
 		int otg_inst,
-- 
GitLab


From d1b08baf93352bb3c88d637055dc21187a456646 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Mon, 6 Jun 2022 11:34:46 -0400
Subject: [PATCH 0259/1731] drm/amdgpu/display: fix DCN3.2 Makefiles for
 non-x86

Add proper handling for PPC64.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn32/Makefile  | 9 ++++++++-
 drivers/gpu/drm/amd/display/dc/dcn321/Makefile | 9 ++++++++-
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/Makefile b/drivers/gpu/drm/amd/display/dc/dcn32/Makefile
index 6e0328060255c..3d09db3070f45 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/Makefile
@@ -15,12 +15,19 @@ DCN32 = dcn32_resource.o dcn32_hubbub.o dcn32_hwseq.o dcn32_init.o \
 		dcn32_dio_stream_encoder.o dcn32_dio_link_encoder.o dcn32_hpo_dp_link_encoder.o \
 		dcn32_mpc.o
 
-CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o := -mhard-float -msse
+ifdef CONFIG_X86
+CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o := -msse
+endif
+
+ifdef CONFIG_PPC64
+CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o := -mhard-float -maltivec
+endif
 
 ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
 IS_OLD_GCC = 1
 endif
+CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o += -mhard-float
 endif
 
 ifdef IS_OLD_GCC
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/Makefile b/drivers/gpu/drm/amd/display/dc/dcn321/Makefile
index 9b61d08700ca6..5896ca303e396 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/Makefile
@@ -12,12 +12,19 @@
 
 DCN321 = dcn321_resource.o dcn321_dio_link_encoder.o
 
-CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o := -mhard-float -msse
+ifdef CONFIG_X86
+CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o := -msse
+endif
+
+ifdef CONFIG_PPC64
+CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o := -mhard-float -maltivec
+endif
 
 ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
 IS_OLD_GCC = 1
 endif
+CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o += -mhard-float
 endif
 
 ifdef IS_OLD_GCC
-- 
GitLab


From 136f614931a2bb73616b292cf542da3a18daefd5 Mon Sep 17 00:00:00 2001
From: Alexey Kodanev <aleksei.kodanev@bell-sw.com>
Date: Mon, 6 Jun 2022 16:50:54 +0300
Subject: [PATCH 0260/1731] drm/radeon: fix potential buffer overflow in
 ni_set_mc_special_registers()

The last case label can write two buffers 'mc_reg_address[j]' and
'mc_data[j]' with 'j' offset equal to SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE
since there are no checks for this value in both case labels after the
last 'j++'.

Instead of changing '>' to '>=' there, add the bounds check at the start
of the second 'case' (the first one already has it).

Also, remove redundant last checks for 'j' index bigger than array size.
The expression is always false. Moreover, before or after the patch
'table->last' can be equal to SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE and it
seems it can be a valid value.

Detected using the static analysis tool - Svace.
Fixes: 69e0b57a91ad ("drm/radeon/kms: add dpm support for cayman (v5)")
Signed-off-by: Alexey Kodanev <aleksei.kodanev@bell-sw.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/radeon/ni_dpm.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c
index 769f666335ac4..672d2239293e0 100644
--- a/drivers/gpu/drm/radeon/ni_dpm.c
+++ b/drivers/gpu/drm/radeon/ni_dpm.c
@@ -2741,10 +2741,10 @@ static int ni_set_mc_special_registers(struct radeon_device *rdev,
 					table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
 			}
 			j++;
-			if (j > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
-				return -EINVAL;
 			break;
 		case MC_SEQ_RESERVE_M >> 2:
+			if (j >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
+				return -EINVAL;
 			temp_reg = RREG32(MC_PMG_CMD_MRS1);
 			table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
 			table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
@@ -2753,8 +2753,6 @@ static int ni_set_mc_special_registers(struct radeon_device *rdev,
 					(temp_reg & 0xffff0000) |
 					(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
 			j++;
-			if (j > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
-				return -EINVAL;
 			break;
 		default:
 			break;
-- 
GitLab


From ea64228d26fee9b766bc9615e92a319da5ef94ef Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Wed, 11 May 2022 17:31:27 -0400
Subject: [PATCH 0261/1731] drm/amdgpu/soc21: add mode2 asic reset for SMU IP
 v13.0.4

Set the default reset method to mode2 for SMU IP v13.0.4

Acked-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Tim Huang <tim.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/soc21.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 09efef506e8f8..57eaafb70d725 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -310,6 +310,7 @@ static enum amd_reset_method
 soc21_asic_reset_method(struct amdgpu_device *adev)
 {
 	if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
+	    amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
 	    amdgpu_reset_method == AMD_RESET_METHOD_BACO)
 		return amdgpu_reset_method;
 
@@ -320,6 +321,8 @@ soc21_asic_reset_method(struct amdgpu_device *adev)
 	switch (adev->ip_versions[MP1_HWIP][0]) {
 	case IP_VERSION(13, 0, 0):
 		return AMD_RESET_METHOD_MODE1;
+	case IP_VERSION(13, 0, 4):
+		return AMD_RESET_METHOD_MODE2;
 	default:
 		if (amdgpu_dpm_is_baco_supported(adev))
 			return AMD_RESET_METHOD_BACO;
@@ -341,6 +344,10 @@ static int soc21_asic_reset(struct amdgpu_device *adev)
 		dev_info(adev->dev, "BACO reset\n");
 		ret = amdgpu_dpm_baco_reset(adev);
 		break;
+	case AMD_RESET_METHOD_MODE2:
+		dev_info(adev->dev, "MODE2 reset\n");
+		ret = amdgpu_dpm_mode2_reset(adev);
+		break;
 	default:
 		dev_info(adev->dev, "MODE1 reset\n");
 		ret = amdgpu_device_mode1_reset(adev);
-- 
GitLab


From c2f75a43f5ae48b9babeb5b82c9f23fe18d3d144 Mon Sep 17 00:00:00 2001
From: Josh Poimboeuf <jpoimboe@kernel.org>
Date: Wed, 1 Jun 2022 09:42:12 -0700
Subject: [PATCH 0262/1731] objtool: Fix obsolete reference to CONFIG_X86_SMAP

CONFIG_X86_SMAP no longer exists.  For objtool's purposes it has been
replaced with CONFIG_HAVE_UACCESS_VALIDATION.

Fixes: 03f16cd020eb ("objtool: Add CONFIG_OBJTOOL")
Reported-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Signed-off-by: Josh Poimboeuf <jpoimboe@kernel.org>
Link: https://lore.kernel.org/r/44c57668768c1ba1b4ba1ff541ec54781636e07c.1654101721.git.jpoimboe@kernel.org
---
 lib/Kconfig.ubsan | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/Kconfig.ubsan b/lib/Kconfig.ubsan
index c4fe15d38b60e..a9f7eb0477685 100644
--- a/lib/Kconfig.ubsan
+++ b/lib/Kconfig.ubsan
@@ -94,7 +94,7 @@ config UBSAN_UNREACHABLE
 	bool "Perform checking for unreachable code"
 	# objtool already handles unreachable checking and gets angry about
 	# seeing UBSan instrumentation located in unreachable places.
-	depends on !(OBJTOOL && (STACK_VALIDATION || UNWINDER_ORC || X86_SMAP))
+	depends on !(OBJTOOL && (STACK_VALIDATION || UNWINDER_ORC || HAVE_UACCESS_VALIDATION))
 	depends on $(cc-option,-fsanitize=unreachable)
 	help
 	  This option enables -fsanitize=unreachable which checks for control
-- 
GitLab


From dcea997beed694cbd8705100ca1a6eb0d886de69 Mon Sep 17 00:00:00 2001
From: Josh Poimboeuf <jpoimboe@kernel.org>
Date: Wed, 1 Jun 2022 17:42:22 -0700
Subject: [PATCH 0263/1731] faddr2line: Fix overlapping text section failures,
 the sequel

If a function lives in a section other than .text, but .text also exists
in the object, faddr2line may wrongly assume .text.  This can result in
comically wrong output.  For example:

  $ scripts/faddr2line vmlinux.o enter_from_user_mode+0x1c
  enter_from_user_mode+0x1c/0x30:
  find_next_bit at /home/jpoimboe/git/linux/./include/linux/find.h:40
  (inlined by) perf_clear_dirty_counters at /home/jpoimboe/git/linux/arch/x86/events/core.c:2504

Fix it by passing the section name to addr2line, unless the object file
is vmlinux, in which case the symbol table uses absolute addresses.

Fixes: 1d1a0e7c5100 ("scripts/faddr2line: Fix overlapping text section failures")
Reported-by: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Josh Poimboeuf <jpoimboe@kernel.org>
Link: https://lore.kernel.org/r/7d25bc1408bd3a750ac26e60d2f2815a5f4a8363.1654130536.git.jpoimboe@kernel.org
---
 scripts/faddr2line | 45 ++++++++++++++++++++++++++++++++++-----------
 1 file changed, 34 insertions(+), 11 deletions(-)

diff --git a/scripts/faddr2line b/scripts/faddr2line
index 0e6268d598835..94ed98dd899f3 100755
--- a/scripts/faddr2line
+++ b/scripts/faddr2line
@@ -95,17 +95,25 @@ __faddr2line() {
 	local print_warnings=$4
 
 	local sym_name=${func_addr%+*}
-	local offset=${func_addr#*+}
-	offset=${offset%/*}
+	local func_offset=${func_addr#*+}
+	func_offset=${func_offset%/*}
 	local user_size=
+	local file_type
+	local is_vmlinux=0
 	[[ $func_addr =~ "/" ]] && user_size=${func_addr#*/}
 
-	if [[ -z $sym_name ]] || [[ -z $offset ]] || [[ $sym_name = $func_addr ]]; then
+	if [[ -z $sym_name ]] || [[ -z $func_offset ]] || [[ $sym_name = $func_addr ]]; then
 		warn "bad func+offset $func_addr"
 		DONE=1
 		return
 	fi
 
+	# vmlinux uses absolute addresses in the section table rather than
+	# section offsets.
+	local file_type=$(${READELF} --file-header $objfile |
+		${AWK} '$1 == "Type:" { print $2; exit }')
+	[[ $file_type = "EXEC" ]] && is_vmlinux=1
+
 	# Go through each of the object's symbols which match the func name.
 	# In rare cases there might be duplicates, in which case we print all
 	# matches.
@@ -114,9 +122,11 @@ __faddr2line() {
 		local sym_addr=0x${fields[1]}
 		local sym_elf_size=${fields[2]}
 		local sym_sec=${fields[6]}
+		local sec_size
+		local sec_name
 
 		# Get the section size:
-		local sec_size=$(${READELF} --section-headers --wide $objfile |
+		sec_size=$(${READELF} --section-headers --wide $objfile |
 			sed 's/\[ /\[/' |
 			${AWK} -v sec=$sym_sec '$1 == "[" sec "]" { print "0x" $6; exit }')
 
@@ -126,6 +136,17 @@ __faddr2line() {
 			return
 		fi
 
+		# Get the section name:
+		sec_name=$(${READELF} --section-headers --wide $objfile |
+			sed 's/\[ /\[/' |
+			${AWK} -v sec=$sym_sec '$1 == "[" sec "]" { print $2; exit }')
+
+		if [[ -z $sec_name ]]; then
+			warn "bad section name: section: $sym_sec"
+			DONE=1
+			return
+		fi
+
 		# Calculate the symbol size.
 		#
 		# Unfortunately we can't use the ELF size, because kallsyms
@@ -174,10 +195,10 @@ __faddr2line() {
 
 		sym_size=0x$(printf %x $sym_size)
 
-		# Calculate the section address from user-supplied offset:
-		local addr=$(($sym_addr + $offset))
+		# Calculate the address from user-supplied offset:
+		local addr=$(($sym_addr + $func_offset))
 		if [[ -z $addr ]] || [[ $addr = 0 ]]; then
-			warn "bad address: $sym_addr + $offset"
+			warn "bad address: $sym_addr + $func_offset"
 			DONE=1
 			return
 		fi
@@ -191,9 +212,9 @@ __faddr2line() {
 		fi
 
 		# Make sure the provided offset is within the symbol's range:
-		if [[ $offset -gt $sym_size ]]; then
+		if [[ $func_offset -gt $sym_size ]]; then
 			[[ $print_warnings = 1 ]] &&
-				echo "skipping $sym_name address at $addr due to size mismatch ($offset > $sym_size)"
+				echo "skipping $sym_name address at $addr due to size mismatch ($func_offset > $sym_size)"
 			continue
 		fi
 
@@ -202,11 +223,13 @@ __faddr2line() {
 		[[ $FIRST = 0 ]] && echo
 		FIRST=0
 
-		echo "$sym_name+$offset/$sym_size:"
+		echo "$sym_name+$func_offset/$sym_size:"
 
 		# Pass section address to addr2line and strip absolute paths
 		# from the output:
-		local output=$(${ADDR2LINE} -fpie $objfile $addr | sed "s; $dir_prefix\(\./\)*; ;")
+		local args="--functions --pretty-print --inlines --exe=$objfile"
+		[[ $is_vmlinux = 0 ]] && args="$args --section=$sec_name"
+		local output=$(${ADDR2LINE} $args $addr | sed "s; $dir_prefix\(\./\)*; ;")
 		[[ -z $output ]] && continue
 
 		# Default output (non --list):
-- 
GitLab


From 7b6c7a877cc616bc7dc9cd39646fe454acbed48b Mon Sep 17 00:00:00 2001
From: Josh Poimboeuf <jpoimboe@kernel.org>
Date: Fri, 3 Jun 2022 08:04:44 -0700
Subject: [PATCH 0264/1731] x86/ftrace: Remove OBJECT_FILES_NON_STANDARD usage

The file-wide OBJECT_FILES_NON_STANDARD annotation is used with
CONFIG_FRAME_POINTER to tell objtool to skip the entire file when frame
pointers are enabled.  However that annotation is now deprecated because
it doesn't work with IBT, where objtool runs on vmlinux.o instead of
individual translation units.

Instead, use more fine-grained function-specific annotations:

- The 'save_mcount_regs' macro does funny things with the frame pointer.
  Use STACK_FRAME_NON_STANDARD_FP to tell objtool to ignore the
  functions using it.

- The return_to_handler() "function" isn't actually a callable function.
  Instead of being called, it's returned to.  The real return address
  isn't on the stack, so unwinding is already doomed no matter which
  unwinder is used.  So just remove the STT_FUNC annotation, telling
  objtool to ignore it.  That also removes the implicit
  ANNOTATE_NOENDBR, which now needs to be made explicit.

Fixes the following warning:

  vmlinux.o: warning: objtool: __fentry__+0x16: return with modified stack frame

Fixes: ed53a0d97192 ("x86/alternative: Use .ibt_endbr_seal to seal indirect calls")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Josh Poimboeuf <jpoimboe@kernel.org>
Link: https://lore.kernel.org/r/b7a7a42fe306aca37826043dac89e113a1acdbac.1654268610.git.jpoimboe@kernel.org
---
 arch/x86/kernel/Makefile      |  4 ----
 arch/x86/kernel/ftrace_64.S   | 11 ++++++++---
 include/linux/objtool.h       |  6 ++++++
 tools/include/linux/objtool.h |  6 ++++++
 4 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 03364dc40d8d9..4c8b6ae802ac3 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -36,10 +36,6 @@ KCSAN_SANITIZE := n
 
 OBJECT_FILES_NON_STANDARD_test_nx.o			:= y
 
-ifdef CONFIG_FRAME_POINTER
-OBJECT_FILES_NON_STANDARD_ftrace_$(BITS).o		:= y
-endif
-
 # If instrumentation of this dir is enabled, boot hangs during first second.
 # Probably could be more selective here, but note that files related to irqs,
 # boot, dumpstack/stacktrace, etc are either non-interesting or can lead to
diff --git a/arch/x86/kernel/ftrace_64.S b/arch/x86/kernel/ftrace_64.S
index 4ec13608d3c62..dfeb227de5617 100644
--- a/arch/x86/kernel/ftrace_64.S
+++ b/arch/x86/kernel/ftrace_64.S
@@ -175,6 +175,7 @@ SYM_INNER_LABEL(ftrace_caller_end, SYM_L_GLOBAL)
 
 	jmp ftrace_epilogue
 SYM_FUNC_END(ftrace_caller);
+STACK_FRAME_NON_STANDARD_FP(ftrace_caller)
 
 SYM_FUNC_START(ftrace_epilogue)
 /*
@@ -282,6 +283,7 @@ SYM_INNER_LABEL(ftrace_regs_caller_end, SYM_L_GLOBAL)
 	jmp	ftrace_epilogue
 
 SYM_FUNC_END(ftrace_regs_caller)
+STACK_FRAME_NON_STANDARD_FP(ftrace_regs_caller)
 
 
 #else /* ! CONFIG_DYNAMIC_FTRACE */
@@ -311,10 +313,14 @@ trace:
 	jmp ftrace_stub
 SYM_FUNC_END(__fentry__)
 EXPORT_SYMBOL(__fentry__)
+STACK_FRAME_NON_STANDARD_FP(__fentry__)
+
 #endif /* CONFIG_DYNAMIC_FTRACE */
 
 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
-SYM_FUNC_START(return_to_handler)
+SYM_CODE_START(return_to_handler)
+	UNWIND_HINT_EMPTY
+	ANNOTATE_NOENDBR
 	subq  $16, %rsp
 
 	/* Save the return values */
@@ -339,7 +345,6 @@ SYM_FUNC_START(return_to_handler)
 	int3
 .Ldo_rop:
 	mov %rdi, (%rsp)
-	UNWIND_HINT_FUNC
 	RET
-SYM_FUNC_END(return_to_handler)
+SYM_CODE_END(return_to_handler)
 #endif
diff --git a/include/linux/objtool.h b/include/linux/objtool.h
index 6491fa8fba6d5..15b940ec1eac9 100644
--- a/include/linux/objtool.h
+++ b/include/linux/objtool.h
@@ -143,6 +143,12 @@ struct unwind_hint {
 	.popsection
 .endm
 
+.macro STACK_FRAME_NON_STANDARD_FP func:req
+#ifdef CONFIG_FRAME_POINTER
+	STACK_FRAME_NON_STANDARD \func
+#endif
+.endm
+
 .macro ANNOTATE_NOENDBR
 .Lhere_\@:
 	.pushsection .discard.noendbr
diff --git a/tools/include/linux/objtool.h b/tools/include/linux/objtool.h
index 6491fa8fba6d5..15b940ec1eac9 100644
--- a/tools/include/linux/objtool.h
+++ b/tools/include/linux/objtool.h
@@ -143,6 +143,12 @@ struct unwind_hint {
 	.popsection
 .endm
 
+.macro STACK_FRAME_NON_STANDARD_FP func:req
+#ifdef CONFIG_FRAME_POINTER
+	STACK_FRAME_NON_STANDARD \func
+#endif
+.endm
+
 .macro ANNOTATE_NOENDBR
 .Lhere_\@:
 	.pushsection .discard.noendbr
-- 
GitLab


From 7f6335c6a258edf4d5ff1b904bc033188dc7b48b Mon Sep 17 00:00:00 2001
From: Xinlei Lee <xinlei.lee@mediatek.com>
Date: Fri, 20 May 2022 10:00:04 +0800
Subject: [PATCH 0265/1731] drm/mediatek: Modify dsi funcs to atomic operations

Because .enable & .disable are deprecated.
Use .atomic_enable & .atomic_disable instead.

Link: https://patchwork.kernel.org/project/linux-mediatek/patch/1653012007-11854-2-git-send-email-xinlei.lee@mediatek.com/
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index d9f10a33e6fad..6e7793f935dab 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -763,14 +763,16 @@ static void mtk_dsi_bridge_mode_set(struct drm_bridge *bridge,
 	drm_display_mode_to_videomode(adjusted, &dsi->vm);
 }
 
-static void mtk_dsi_bridge_disable(struct drm_bridge *bridge)
+static void mtk_dsi_bridge_atomic_disable(struct drm_bridge *bridge,
+					  struct drm_bridge_state *old_bridge_state)
 {
 	struct mtk_dsi *dsi = bridge_to_dsi(bridge);
 
 	mtk_output_dsi_disable(dsi);
 }
 
-static void mtk_dsi_bridge_enable(struct drm_bridge *bridge)
+static void mtk_dsi_bridge_atomic_enable(struct drm_bridge *bridge,
+					 struct drm_bridge_state *old_bridge_state)
 {
 	struct mtk_dsi *dsi = bridge_to_dsi(bridge);
 
@@ -779,8 +781,8 @@ static void mtk_dsi_bridge_enable(struct drm_bridge *bridge)
 
 static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = {
 	.attach = mtk_dsi_bridge_attach,
-	.disable = mtk_dsi_bridge_disable,
-	.enable = mtk_dsi_bridge_enable,
+	.atomic_disable = mtk_dsi_bridge_atomic_disable,
+	.atomic_enable = mtk_dsi_bridge_atomic_enable,
 	.mode_set = mtk_dsi_bridge_mode_set,
 };
 
-- 
GitLab


From cde7e2e35c2866d22a3a012e72a41052dfcc255d Mon Sep 17 00:00:00 2001
From: Jitao Shi <jitao.shi@mediatek.com>
Date: Fri, 20 May 2022 10:00:05 +0800
Subject: [PATCH 0266/1731] drm/mediatek: Separate poweron/poweroff from
 enable/disable and define new funcs

In order to match the changes of "Use the drm_panel_bridge API",
the poweron/poweroff of dsi is extracted from enable/disable and
defined as new funcs (atomic_pre_enable/atomic_post_disable).

Since dsi_poweron is moved from dsi_enable to pre_enable function, in
order to avoid poweron failure, the operation of dsi register fails to
cause bus hang. Therefore, the protection mechanism is added to the
dsi_enable function.

Fixes: 2dd8075d2185 ("drm/mediatek: mtk_dsi: Use the drm_panel_bridge API")

Link: https://patchwork.kernel.org/project/linux-mediatek/patch/1653012007-11854-3-git-send-email-xinlei.lee@mediatek.com/
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 53 +++++++++++++++++++-----------
 1 file changed, 34 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 6e7793f935dab..966a4729bb417 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -691,16 +691,6 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
 	if (--dsi->refcount != 0)
 		return;
 
-	/*
-	 * mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since
-	 * mtk_dsi_stop() should be called after mtk_drm_crtc_atomic_disable(),
-	 * which needs irq for vblank, and mtk_dsi_stop() will disable irq.
-	 * mtk_dsi_start() needs to be called in mtk_output_dsi_enable(),
-	 * after dsi is fully set.
-	 */
-	mtk_dsi_stop(dsi);
-
-	mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);
 	mtk_dsi_reset_engine(dsi);
 	mtk_dsi_lane0_ulp_mode_enter(dsi);
 	mtk_dsi_clk_ulp_mode_enter(dsi);
@@ -715,17 +705,9 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
 
 static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
 {
-	int ret;
-
 	if (dsi->enabled)
 		return;
 
-	ret = mtk_dsi_poweron(dsi);
-	if (ret < 0) {
-		DRM_ERROR("failed to power on dsi\n");
-		return;
-	}
-
 	mtk_dsi_set_mode(dsi);
 	mtk_dsi_clk_hs_mode(dsi, 1);
 
@@ -739,7 +721,16 @@ static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
 	if (!dsi->enabled)
 		return;
 
-	mtk_dsi_poweroff(dsi);
+	/*
+	 * mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since
+	 * mtk_dsi_stop() should be called after mtk_drm_crtc_atomic_disable(),
+	 * which needs irq for vblank, and mtk_dsi_stop() will disable irq.
+	 * mtk_dsi_start() needs to be called in mtk_output_dsi_enable(),
+	 * after dsi is fully set.
+	 */
+	mtk_dsi_stop(dsi);
+
+	mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);
 
 	dsi->enabled = false;
 }
@@ -776,13 +767,37 @@ static void mtk_dsi_bridge_atomic_enable(struct drm_bridge *bridge,
 {
 	struct mtk_dsi *dsi = bridge_to_dsi(bridge);
 
+	if (dsi->refcount == 0)
+		return;
+
 	mtk_output_dsi_enable(dsi);
 }
 
+static void mtk_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
+					     struct drm_bridge_state *old_bridge_state)
+{
+	struct mtk_dsi *dsi = bridge_to_dsi(bridge);
+	int ret;
+
+	ret = mtk_dsi_poweron(dsi);
+	if (ret < 0)
+		DRM_ERROR("failed to power on dsi\n");
+}
+
+static void mtk_dsi_bridge_atomic_post_disable(struct drm_bridge *bridge,
+					       struct drm_bridge_state *old_bridge_state)
+{
+	struct mtk_dsi *dsi = bridge_to_dsi(bridge);
+
+	mtk_dsi_poweroff(dsi);
+}
+
 static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = {
 	.attach = mtk_dsi_bridge_attach,
 	.atomic_disable = mtk_dsi_bridge_atomic_disable,
 	.atomic_enable = mtk_dsi_bridge_atomic_enable,
+	.atomic_pre_enable = mtk_dsi_bridge_atomic_pre_enable,
+	.atomic_post_disable = mtk_dsi_bridge_atomic_post_disable,
 	.mode_set = mtk_dsi_bridge_mode_set,
 };
 
-- 
GitLab


From 39e8d062b03c3dc257d880d82bd55cdd9e185a3b Mon Sep 17 00:00:00 2001
From: Jitao Shi <jitao.shi@mediatek.com>
Date: Fri, 20 May 2022 10:00:06 +0800
Subject: [PATCH 0267/1731] drm/mediatek: Keep dsi as LP00 before dcs cmds
 transfer

To comply with the panel sequence, hold the mipi signal to LP00 before
the dcs cmds transmission, and pull the mipi signal high from LP00 to
LP11 until the start of the dcs cmds transmission.

The normal panel timing is :
(1) pp1800 DC pull up
(2) avdd & avee AC pull high
(3) lcm_reset pull high -> pull low -> pull high
(4) Pull MIPI signal high (LP11) -> initial code -> send video data
    (HS mode)

The power-off sequence is reversed.
If dsi is not in cmd mode, then dsi will pull the mipi signal high in
the mtk_output_dsi_enable function. The delay in lane_ready func is
the reaction time of dsi_rx after pulling up the mipi signal.

Fixes: 2dd8075d2185 ("drm/mediatek: mtk_dsi: Use the drm_panel_bridge API")

Link: https://patchwork.kernel.org/project/linux-mediatek/patch/1653012007-11854-4-git-send-email-xinlei.lee@mediatek.com/
Cc: <stable@vger.kernel.org> # 5.10.x: 7f6335c6a258: drm/mediatek: Modify dsi funcs to atomic operations
Cc: <stable@vger.kernel.org> # 5.10.x: cde7e2e35c28: drm/mediatek: Separate poweron/poweroff from enable/disable and define new funcs
Cc: <stable@vger.kernel.org> # 5.10.x
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 28 +++++++++++++++++++++-------
 1 file changed, 21 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 966a4729bb417..907d07eda0009 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -203,6 +203,7 @@ struct mtk_dsi {
 	struct mtk_phy_timing phy_timing;
 	int refcount;
 	bool enabled;
+	bool lanes_ready;
 	u32 irq_data;
 	wait_queue_head_t irq_wait_queue;
 	const struct mtk_dsi_driver_data *driver_data;
@@ -661,18 +662,11 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
 	mtk_dsi_reset_engine(dsi);
 	mtk_dsi_phy_timconfig(dsi);
 
-	mtk_dsi_rxtx_control(dsi);
-	usleep_range(30, 100);
-	mtk_dsi_reset_dphy(dsi);
 	mtk_dsi_ps_control_vact(dsi);
 	mtk_dsi_set_vm_cmd(dsi);
 	mtk_dsi_config_vdo_timing(dsi);
 	mtk_dsi_set_interrupt_enable(dsi);
 
-	mtk_dsi_clk_ulp_mode_leave(dsi);
-	mtk_dsi_lane0_ulp_mode_leave(dsi);
-	mtk_dsi_clk_hs_mode(dsi, 0);
-
 	return 0;
 err_disable_engine_clk:
 	clk_disable_unprepare(dsi->engine_clk);
@@ -701,6 +695,23 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
 	clk_disable_unprepare(dsi->digital_clk);
 
 	phy_power_off(dsi->phy);
+
+	dsi->lanes_ready = false;
+}
+
+static void mtk_dsi_lane_ready(struct mtk_dsi *dsi)
+{
+	if (!dsi->lanes_ready) {
+		dsi->lanes_ready = true;
+		mtk_dsi_rxtx_control(dsi);
+		usleep_range(30, 100);
+		mtk_dsi_reset_dphy(dsi);
+		mtk_dsi_clk_ulp_mode_leave(dsi);
+		mtk_dsi_lane0_ulp_mode_leave(dsi);
+		mtk_dsi_clk_hs_mode(dsi, 0);
+		msleep(20);
+		/* The reaction time after pulling up the mipi signal for dsi_rx */
+	}
 }
 
 static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
@@ -708,6 +719,7 @@ static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
 	if (dsi->enabled)
 		return;
 
+	mtk_dsi_lane_ready(dsi);
 	mtk_dsi_set_mode(dsi);
 	mtk_dsi_clk_hs_mode(dsi, 1);
 
@@ -1017,6 +1029,8 @@ static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
 	if (MTK_DSI_HOST_IS_READ(msg->type))
 		irq_flag |= LPRX_RD_RDY_INT_FLAG;
 
+	mtk_dsi_lane_ready(dsi);
+
 	ret = mtk_dsi_host_send_cmd(dsi, msg, irq_flag);
 	if (ret)
 		goto restore_dsi_mode;
-- 
GitLab


From fa5d0a0205c34734c5b8daa77e39ac2817f63a10 Mon Sep 17 00:00:00 2001
From: Xinlei Lee <xinlei.lee@mediatek.com>
Date: Fri, 20 May 2022 10:00:07 +0800
Subject: [PATCH 0268/1731] drm/mediatek: Add pull-down MIPI operation in
 mtk_dsi_poweroff function

In the dsi_enable function, mtk_dsi_rxtx_control is to
pull up the MIPI signal operation. Before dsi_disable,
MIPI should also be pulled down by writing a register
instead of disabling dsi.

If disable dsi without pulling the mipi signal low, the value of
the register will still maintain the setting of the mipi signal being
pulled high.
After resume, even if the mipi signal is not pulled high, it will still
be in the high state.

Fixes: 2e54c14e310f ("drm/mediatek: Add DSI sub driver")

Link: https://patchwork.kernel.org/project/linux-mediatek/patch/1653012007-11854-5-git-send-email-xinlei.lee@mediatek.com/
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 907d07eda0009..af2f123e9a9a9 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -688,6 +688,8 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
 	mtk_dsi_reset_engine(dsi);
 	mtk_dsi_lane0_ulp_mode_enter(dsi);
 	mtk_dsi_clk_ulp_mode_enter(dsi);
+	/* set the lane number as 0 to pull down mipi */
+	writel(0, dsi->regs + DSI_TXRX_CTRL);
 
 	mtk_dsi_disable(dsi);
 
-- 
GitLab


From 4266e2f70d4388b8c6a95056169954ff049ced94 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <festevam@gmail.com>
Date: Sat, 14 May 2022 11:35:05 -0300
Subject: [PATCH 0269/1731] arm64: s32g2: Pass unit name to soc node

Pass unit name to soc node to fix the following W=1 build warning:

arch/arm64/boot/dts/freescale/s32g2.dtsi:82.6-123.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Chester Lin <clin@suse.com>
Signed-off-by: Chester Lin <clin@suse.com>
Link: https://lore.kernel.org/r/20220514143505.1554813-1-festevam@gmail.com
---
 arch/arm64/boot/dts/freescale/s32g2.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 59ea8a25aa4c1..824d401e7a2c5 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -79,7 +79,7 @@
 		};
 	};
 
-	soc {
+	soc@0 {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
-- 
GitLab


From 680c0aee97690c3f595e074a5f677599aac5d26b Mon Sep 17 00:00:00 2001
From: Chester Lin <clin@suse.com>
Date: Wed, 25 May 2022 09:49:22 +0800
Subject: [PATCH 0270/1731] MAINTAINERS: add a new reviewer for S32G

Add the NXP S32 Linux team as a designated review group of s32g.

Signed-off-by: Chester Lin <clin@suse.com>
Link: https://lore.kernel.org/r/20220525161422.14156-1-clin@suse.com
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index a6d3bd9d2a8d0..fbe76ce119ea1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2467,6 +2467,7 @@ ARM/NXP S32G ARCHITECTURE
 M:	Chester Lin <clin@suse.com>
 R:	Andreas Färber <afaerber@suse.de>
 R:	Matthias Brugger <mbrugger@suse.com>
+R:	NXP S32 Linux Team <s32@nxp.com>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
 F:	arch/arm64/boot/dts/freescale/s32g*.dts*
-- 
GitLab


From 118f767413ada4eef7825fbd4af7c0866f883441 Mon Sep 17 00:00:00 2001
From: Kamal Heib <kamalheib1@gmail.com>
Date: Wed, 25 May 2022 16:20:29 +0300
Subject: [PATCH 0271/1731] RDMA/qedr: Fix reporting QP timeout attribute
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Make sure to save the passed QP timeout attribute when the QP gets modified,
so when calling query QP the right value is reported and not the
converted value that is required by the firmware. This issue was found
while running the pyverbs tests.

Fixes: cecbcddf6461 ("qedr: Add support for QP verbs")
Link: https://lore.kernel.org/r/20220525132029.84813-1-kamalheib1@gmail.com
Signed-off-by: Kamal Heib <kamalheib1@gmail.com>
Acked-by: Michal Kalderon <michal.kalderon@marvell.com>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
---
 drivers/infiniband/hw/qedr/qedr.h  | 1 +
 drivers/infiniband/hw/qedr/verbs.c | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/infiniband/hw/qedr/qedr.h b/drivers/infiniband/hw/qedr/qedr.h
index 8def88cfa3009..db9ef3e1eb97c 100644
--- a/drivers/infiniband/hw/qedr/qedr.h
+++ b/drivers/infiniband/hw/qedr/qedr.h
@@ -418,6 +418,7 @@ struct qedr_qp {
 	u32 sq_psn;
 	u32 qkey;
 	u32 dest_qp_num;
+	u8 timeout;
 
 	/* Relevant to qps created from kernel space only (ULPs) */
 	u8 prev_wqe_size;
diff --git a/drivers/infiniband/hw/qedr/verbs.c b/drivers/infiniband/hw/qedr/verbs.c
index f0f43b6db89ee..03ed7c0fae505 100644
--- a/drivers/infiniband/hw/qedr/verbs.c
+++ b/drivers/infiniband/hw/qedr/verbs.c
@@ -2613,6 +2613,8 @@ int qedr_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
 					1 << max_t(int, attr->timeout - 8, 0);
 		else
 			qp_params.ack_timeout = 0;
+
+		qp->timeout = attr->timeout;
 	}
 
 	if (attr_mask & IB_QP_RETRY_CNT) {
@@ -2772,7 +2774,7 @@ int qedr_query_qp(struct ib_qp *ibqp,
 	rdma_ah_set_dgid_raw(&qp_attr->ah_attr, &params.dgid.bytes[0]);
 	rdma_ah_set_port_num(&qp_attr->ah_attr, 1);
 	rdma_ah_set_sl(&qp_attr->ah_attr, 0);
-	qp_attr->timeout = params.timeout;
+	qp_attr->timeout = qp->timeout;
 	qp_attr->rnr_retry = params.rnr_retry;
 	qp_attr->retry_cnt = params.retry_cnt;
 	qp_attr->min_rnr_timer = params.min_rnr_nak_timer;
-- 
GitLab


From 1d0811b03eb30b2f0793acaa96c6ce90b8b9c87a Mon Sep 17 00:00:00 2001
From: Helge Deller <deller@gmx.de>
Date: Tue, 7 Jun 2022 12:57:58 +0200
Subject: [PATCH 0272/1731] parisc/stifb: Fix fb_is_primary_device() only
 available with CONFIG_FB_STI

Fix this build error noticed by the kernel test robot:

drivers/video/console/sticore.c:1132:5: error: redefinition of 'fb_is_primary_device'
 arch/parisc/include/asm/fb.h:18:19: note: previous definition of 'fb_is_primary_device'

Signed-off-by: Helge Deller <deller@gmx.de>
Reported-by: kernel test robot <lkp@intel.com>
Cc: stable@vger.kernel.org   # v5.10+
---
 arch/parisc/include/asm/fb.h    | 2 +-
 drivers/video/console/sticore.c | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/parisc/include/asm/fb.h b/arch/parisc/include/asm/fb.h
index d63a2acb91f2b..55d29c4f716e6 100644
--- a/arch/parisc/include/asm/fb.h
+++ b/arch/parisc/include/asm/fb.h
@@ -12,7 +12,7 @@ static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
 	pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE;
 }
 
-#if defined(CONFIG_STI_CONSOLE) || defined(CONFIG_FB_STI)
+#if defined(CONFIG_FB_STI)
 int fb_is_primary_device(struct fb_info *info);
 #else
 static inline int fb_is_primary_device(struct fb_info *info)
diff --git a/drivers/video/console/sticore.c b/drivers/video/console/sticore.c
index fa23bf0247b04..bd4dc97d4d340 100644
--- a/drivers/video/console/sticore.c
+++ b/drivers/video/console/sticore.c
@@ -1148,6 +1148,7 @@ int sti_call(const struct sti_struct *sti, unsigned long func,
 	return ret;
 }
 
+#if defined(CONFIG_FB_STI)
 /* check if given fb_info is the primary device */
 int fb_is_primary_device(struct fb_info *info)
 {
@@ -1163,6 +1164,7 @@ int fb_is_primary_device(struct fb_info *info)
 	return (sti->info == info);
 }
 EXPORT_SYMBOL(fb_is_primary_device);
+#endif
 
 MODULE_AUTHOR("Philipp Rumpf, Helge Deller, Thomas Bogendoerfer");
 MODULE_DESCRIPTION("Core STI driver for HP's NGLE series graphics cards in HP PARISC machines");
-- 
GitLab


From 5e3f89ad8e0cbd75aa3479e9ceb96d9e1c5585b8 Mon Sep 17 00:00:00 2001
From: Rob Herring <robh@kernel.org>
Date: Mon, 6 Jun 2022 16:22:22 -0500
Subject: [PATCH 0273/1731] dt-bindings: hwmon: ti,tmp401: Drop 'items' from
 'ti,n-factor' property

'ti,n-factor' is a scalar type, so 'items' should not be used as that is
for arrays/matrix.

A pending meta-schema change will catch future cases.

Fixes: bd90c5b93950 ("dt-bindings: hwmon: Add TMP401, TMP411 and TMP43x")
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220606212223.1360395-1-robh@kernel.org
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
---
 Documentation/devicetree/bindings/hwmon/ti,tmp401.yaml | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/hwmon/ti,tmp401.yaml b/Documentation/devicetree/bindings/hwmon/ti,tmp401.yaml
index fe0ac08faa1a7..0e8ddf0ad7890 100644
--- a/Documentation/devicetree/bindings/hwmon/ti,tmp401.yaml
+++ b/Documentation/devicetree/bindings/hwmon/ti,tmp401.yaml
@@ -40,9 +40,8 @@ properties:
       value to be used for converting remote channel measurements to
       temperature.
     $ref: /schemas/types.yaml#/definitions/int32
-    items:
-      minimum: -128
-      maximum: 127
+    minimum: -128
+    maximum: 127
 
   ti,beta-compensation:
     description:
-- 
GitLab


From ac6888ac5a11c0a47d1f1da4b7809c0c595fdc5d Mon Sep 17 00:00:00 2001
From: Eddie James <eajames@linux.ibm.com>
Date: Mon, 6 Jun 2022 13:54:55 -0500
Subject: [PATCH 0274/1731] hwmon: (occ) Lock mutex in shutdown to prevent race
 with occ_active

Unbinding the driver or removing the parent device at the same time
as using the OCC active sysfs file can cause the driver to unregister
the hwmon device twice. Prevent this by locking the occ mutex in the
shutdown function.

Signed-off-by: Eddie James <eajames@linux.ibm.com>
Link: https://lore.kernel.org/r/20220606185455.21126-1-eajames@linux.ibm.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
---
 drivers/hwmon/occ/common.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/hwmon/occ/common.c b/drivers/hwmon/occ/common.c
index d78f4bebc7189..ea070b91e5b98 100644
--- a/drivers/hwmon/occ/common.c
+++ b/drivers/hwmon/occ/common.c
@@ -1228,10 +1228,15 @@ EXPORT_SYMBOL_GPL(occ_setup);
 
 void occ_shutdown(struct occ *occ)
 {
+	mutex_lock(&occ->lock);
+
 	occ_shutdown_sysfs(occ);
 
 	if (occ->hwmon)
 		hwmon_device_unregister(occ->hwmon);
+	occ->hwmon = NULL;
+
+	mutex_unlock(&occ->lock);
 }
 EXPORT_SYMBOL_GPL(occ_shutdown);
 
-- 
GitLab


From d52d165d67c5aa26c8c89909003c94a66492d23d Mon Sep 17 00:00:00 2001
From: Marc Zyngier <maz@kernel.org>
Date: Sat, 28 May 2022 12:38:11 +0100
Subject: [PATCH 0275/1731] KVM: arm64: Always start with clearing SVE flag on
 load

On each vcpu load, we set the KVM_ARM64_HOST_SVE_ENABLED
flag if SVE is enabled for EL0 on the host. This is used to restore
the correct state on vpcu put.

However, it appears that nothing ever clears this flag. Once
set, it will stick until the vcpu is destroyed, which has the
potential to spuriously enable SVE for userspace.

We probably never saw the issue because no VMM uses SVE, but
that's still pretty bad. Unconditionally clearing the flag
on vcpu load addresses the issue.

Fixes: 8383741ab2e7 ("KVM: arm64: Get rid of host SVE tracking/saving")
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: stable@vger.kernel.org
Reviewed-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220528113829.1043361-2-maz@kernel.org
---
 arch/arm64/kvm/fpsimd.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c
index 3d251a4d2cf7b..8267ff4642d36 100644
--- a/arch/arm64/kvm/fpsimd.c
+++ b/arch/arm64/kvm/fpsimd.c
@@ -80,6 +80,7 @@ void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu)
 	vcpu->arch.flags &= ~KVM_ARM64_FP_ENABLED;
 	vcpu->arch.flags |= KVM_ARM64_FP_HOST;
 
+	vcpu->arch.flags &= ~KVM_ARM64_HOST_SVE_ENABLED;
 	if (read_sysreg(cpacr_el1) & CPACR_EL1_ZEN_EL0EN)
 		vcpu->arch.flags |= KVM_ARM64_HOST_SVE_ENABLED;
 
-- 
GitLab


From 039f49c4cafb785504c678f28664d088e0108d35 Mon Sep 17 00:00:00 2001
From: Marc Zyngier <maz@kernel.org>
Date: Sat, 28 May 2022 12:38:12 +0100
Subject: [PATCH 0276/1731] KVM: arm64: Always start with clearing SME flag on
 load

On each vcpu load, we set the KVM_ARM64_HOST_SME_ENABLED
flag if SME is enabled for EL0 on the host. This is used to
restore the correct state on vpcu put.

However, it appears that nothing ever clears this flag. Once
set, it will stick until the vcpu is destroyed, which has the
potential to spuriously enable SME for userspace. As it turns
out, this is due to the SME code being more or less copied from
SVE, and inheriting the same shortcomings.

We never saw the issue because nothing uses SME, and the amount
of testing is probably still pretty low.

Fixes: 861262ab8627 ("KVM: arm64: Handle SME host state when running guests")
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviwed-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220528113829.1043361-3-maz@kernel.org
---
 arch/arm64/kvm/fpsimd.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c
index 8267ff4642d36..6012b08ecb14e 100644
--- a/arch/arm64/kvm/fpsimd.c
+++ b/arch/arm64/kvm/fpsimd.c
@@ -94,6 +94,7 @@ void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu)
 	 * operations. Do this for ZA as well for now for simplicity.
 	 */
 	if (system_supports_sme()) {
+		vcpu->arch.flags &= ~KVM_ARM64_HOST_SME_ENABLED;
 		if (read_sysreg(cpacr_el1) & CPACR_EL1_SMEN_EL0EN)
 			vcpu->arch.flags |= KVM_ARM64_HOST_SME_ENABLED;
 
-- 
GitLab


From e3fe65e0d3671ee5ae8a2723e429ee4830a7c89c Mon Sep 17 00:00:00 2001
From: sunliming <sunliming@kylinos.cn>
Date: Thu, 2 Jun 2022 10:48:05 +0800
Subject: [PATCH 0277/1731] KVM: arm64: Fix inconsistent indenting

Fix the following smatch warnings:

arch/arm64/kvm/vmid.c:62 flush_context() warn: inconsistent indenting

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: sunliming <sunliming@kylinos.cn>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220602024805.511457-1-sunliming@kylinos.cn
---
 arch/arm64/kvm/vmid.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/kvm/vmid.c b/arch/arm64/kvm/vmid.c
index 8d5f0506fd87f..d78ae63d7c15f 100644
--- a/arch/arm64/kvm/vmid.c
+++ b/arch/arm64/kvm/vmid.c
@@ -66,7 +66,7 @@ static void flush_context(void)
 	 * the next context-switch, we broadcast TLB flush + I-cache
 	 * invalidation over the inner shareable domain on rollover.
 	 */
-	 kvm_call_hyp(__kvm_flush_vm_context);
+	kvm_call_hyp(__kvm_flush_vm_context);
 }
 
 static bool check_update_reserved_vmid(u64 vmid, u64 newvmid)
-- 
GitLab


From 304791255a2dc1c9be7e7c8a6cbdb31b6847b0e5 Mon Sep 17 00:00:00 2001
From: Scott Mayhew <smayhew@redhat.com>
Date: Wed, 1 Jun 2022 13:34:49 -0400
Subject: [PATCH 0278/1731] sunrpc: set cl_max_connect when cloning an rpc_clnt

If the initial attempt at trunking detection using the krb5i auth flavor
fails with -EACCES, -NFS4ERR_CLID_INUSE, or -NFS4ERR_WRONGSEC, then the
NFS client tries again using auth_sys, cloning the rpc_clnt in the
process.  If this second attempt at trunking detection succeeds, then
the resulting nfs_client->cl_rpcclient winds up having cl_max_connect=0
and subsequent attempts to add additional transport connections to the
rpc_clnt will fail with a message similar to the following being logged:

[502044.312640] SUNRPC: reached max allowed number (0) did not add
transport to server: 192.168.122.3

Signed-off-by: Scott Mayhew <smayhew@redhat.com>
Fixes: dc48e0abee24 ("SUNRPC enforce creation of no more than max_connect xprts")
Signed-off-by: Anna Schumaker <Anna.Schumaker@Netapp.com>
---
 net/sunrpc/clnt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/net/sunrpc/clnt.c b/net/sunrpc/clnt.c
index e2c6eca0271b3..b6781ada3aa8d 100644
--- a/net/sunrpc/clnt.c
+++ b/net/sunrpc/clnt.c
@@ -651,6 +651,7 @@ static struct rpc_clnt *__rpc_clone_client(struct rpc_create_args *args,
 	new->cl_discrtry = clnt->cl_discrtry;
 	new->cl_chatty = clnt->cl_chatty;
 	new->cl_principal = clnt->cl_principal;
+	new->cl_max_connect = clnt->cl_max_connect;
 	return new;
 
 out_err:
-- 
GitLab


From 2cdea19a34c2340b3aa69508804efe4e3750fcec Mon Sep 17 00:00:00 2001
From: Marc Zyngier <maz@kernel.org>
Date: Tue, 7 Jun 2022 14:14:25 +0100
Subject: [PATCH 0279/1731] KVM: arm64: Don't read a HW interrupt pending state
 in user context

Since 5bfa685e62e9 ("KVM: arm64: vgic: Read HW interrupt pending state
from the HW"), we're able to source the pending bit for an interrupt
that is stored either on the physical distributor or on a device.

However, this state is only available when the vcpu is loaded,
and is not intended to be accessed from userspace. Unfortunately,
the GICv2 emulation doesn't provide specific userspace accessors,
and we fallback with the ones that are intended for the guest,
with fatal consequences.

Add a new vgic_uaccess_read_pending() accessor for userspace
to use, build on top of the existing vgic_mmio_read_pending().

Reported-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Fixes: 5bfa685e62e9 ("KVM: arm64: vgic: Read HW interrupt pending state from the HW")
Link: https://lore.kernel.org/r/20220607131427.1164881-2-maz@kernel.org
Cc: stable@vger.kernel.org
---
 arch/arm64/kvm/vgic/vgic-mmio-v2.c |  4 ++--
 arch/arm64/kvm/vgic/vgic-mmio.c    | 19 ++++++++++++++++---
 arch/arm64/kvm/vgic/vgic-mmio.h    |  3 +++
 3 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v2.c b/arch/arm64/kvm/vgic/vgic-mmio-v2.c
index 77a67e9d3d14b..e070cda86e12f 100644
--- a/arch/arm64/kvm/vgic/vgic-mmio-v2.c
+++ b/arch/arm64/kvm/vgic/vgic-mmio-v2.c
@@ -429,11 +429,11 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = {
 		VGIC_ACCESS_32bit),
 	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_SET,
 		vgic_mmio_read_pending, vgic_mmio_write_spending,
-		NULL, vgic_uaccess_write_spending, 1,
+		vgic_uaccess_read_pending, vgic_uaccess_write_spending, 1,
 		VGIC_ACCESS_32bit),
 	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_CLEAR,
 		vgic_mmio_read_pending, vgic_mmio_write_cpending,
-		NULL, vgic_uaccess_write_cpending, 1,
+		vgic_uaccess_read_pending, vgic_uaccess_write_cpending, 1,
 		VGIC_ACCESS_32bit),
 	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_SET,
 		vgic_mmio_read_active, vgic_mmio_write_sactive,
diff --git a/arch/arm64/kvm/vgic/vgic-mmio.c b/arch/arm64/kvm/vgic/vgic-mmio.c
index 49837d3a3ef56..dc8c52487e470 100644
--- a/arch/arm64/kvm/vgic/vgic-mmio.c
+++ b/arch/arm64/kvm/vgic/vgic-mmio.c
@@ -226,8 +226,9 @@ int vgic_uaccess_write_cenable(struct kvm_vcpu *vcpu,
 	return 0;
 }
 
-unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
-				     gpa_t addr, unsigned int len)
+static unsigned long __read_pending(struct kvm_vcpu *vcpu,
+				    gpa_t addr, unsigned int len,
+				    bool is_user)
 {
 	u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 	u32 value = 0;
@@ -248,7 +249,7 @@ unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
 						    IRQCHIP_STATE_PENDING,
 						    &val);
 			WARN_RATELIMIT(err, "IRQ %d", irq->host_irq);
-		} else if (vgic_irq_is_mapped_level(irq)) {
+		} else if (!is_user && vgic_irq_is_mapped_level(irq)) {
 			val = vgic_get_phys_line_level(irq);
 		} else {
 			val = irq_is_pending(irq);
@@ -263,6 +264,18 @@ unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
 	return value;
 }
 
+unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
+				     gpa_t addr, unsigned int len)
+{
+	return __read_pending(vcpu, addr, len, false);
+}
+
+unsigned long vgic_uaccess_read_pending(struct kvm_vcpu *vcpu,
+					gpa_t addr, unsigned int len)
+{
+	return __read_pending(vcpu, addr, len, true);
+}
+
 static bool is_vgic_v2_sgi(struct kvm_vcpu *vcpu, struct vgic_irq *irq)
 {
 	return (vgic_irq_is_sgi(irq->intid) &&
diff --git a/arch/arm64/kvm/vgic/vgic-mmio.h b/arch/arm64/kvm/vgic/vgic-mmio.h
index 3fa696f198a37..6082d4b66d398 100644
--- a/arch/arm64/kvm/vgic/vgic-mmio.h
+++ b/arch/arm64/kvm/vgic/vgic-mmio.h
@@ -149,6 +149,9 @@ int vgic_uaccess_write_cenable(struct kvm_vcpu *vcpu,
 unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
 				     gpa_t addr, unsigned int len);
 
+unsigned long vgic_uaccess_read_pending(struct kvm_vcpu *vcpu,
+					gpa_t addr, unsigned int len);
+
 void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,
 			      gpa_t addr, unsigned int len,
 			      unsigned long val);
-- 
GitLab


From e3a4167c880cf889f66887a152799df4d609dd21 Mon Sep 17 00:00:00 2001
From: David Sterba <dsterba@suse.com>
Date: Thu, 2 Jun 2022 23:57:17 +0200
Subject: [PATCH 0280/1731] btrfs: add error messages to all unrecognized mount
 options

Almost none of the errors stemming from a valid mount option but wrong
value prints a descriptive message which would help to identify why
mount failed. Like in the linked report:

  $ uname -r
  v4.19
  $ mount -o compress=zstd /dev/sdb /mnt
  mount: /mnt: wrong fs type, bad option, bad superblock on
  /dev/sdb, missing codepage or helper program, or other error.
  $ dmesg
  ...
  BTRFS error (device sdb): open_ctree failed

Errors caused by memory allocation failures are left out as it's not a
user error so reporting that would be confusing.

Link: https://lore.kernel.org/linux-btrfs/9c3fec36-fc61-3a33-4977-a7e207c3fa4e@gmx.de/
CC: stable@vger.kernel.org # 4.9+
Reviewed-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Nikolay Borisov <nborisov@suse.com>
Reviewed-by: Anand Jain <anand.jain@oracle.com>
Signed-off-by: David Sterba <dsterba@suse.com>
---
 fs/btrfs/super.c | 39 ++++++++++++++++++++++++++++++++-------
 1 file changed, 32 insertions(+), 7 deletions(-)

diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c
index 1387fbe935c14..6627dd7875ee0 100644
--- a/fs/btrfs/super.c
+++ b/fs/btrfs/super.c
@@ -763,6 +763,8 @@ int btrfs_parse_options(struct btrfs_fs_info *info, char *options,
 				compress_force = false;
 				no_compress++;
 			} else {
+				btrfs_err(info, "unrecognized compression value %s",
+					  args[0].from);
 				ret = -EINVAL;
 				goto out;
 			}
@@ -821,8 +823,11 @@ int btrfs_parse_options(struct btrfs_fs_info *info, char *options,
 		case Opt_thread_pool:
 			ret = match_int(&args[0], &intarg);
 			if (ret) {
+				btrfs_err(info, "unrecognized thread_pool value %s",
+					  args[0].from);
 				goto out;
 			} else if (intarg == 0) {
+				btrfs_err(info, "invalid value 0 for thread_pool");
 				ret = -EINVAL;
 				goto out;
 			}
@@ -883,8 +888,11 @@ int btrfs_parse_options(struct btrfs_fs_info *info, char *options,
 			break;
 		case Opt_ratio:
 			ret = match_int(&args[0], &intarg);
-			if (ret)
+			if (ret) {
+				btrfs_err(info, "unrecognized metadata_ratio value %s",
+					  args[0].from);
 				goto out;
+			}
 			info->metadata_ratio = intarg;
 			btrfs_info(info, "metadata ratio %u",
 				   info->metadata_ratio);
@@ -901,6 +909,8 @@ int btrfs_parse_options(struct btrfs_fs_info *info, char *options,
 				btrfs_set_and_info(info, DISCARD_ASYNC,
 						   "turning on async discard");
 			} else {
+				btrfs_err(info, "unrecognized discard mode value %s",
+					  args[0].from);
 				ret = -EINVAL;
 				goto out;
 			}
@@ -933,6 +943,8 @@ int btrfs_parse_options(struct btrfs_fs_info *info, char *options,
 				btrfs_set_and_info(info, FREE_SPACE_TREE,
 						   "enabling free space tree");
 			} else {
+				btrfs_err(info, "unrecognized space_cache value %s",
+					  args[0].from);
 				ret = -EINVAL;
 				goto out;
 			}
@@ -1014,8 +1026,12 @@ int btrfs_parse_options(struct btrfs_fs_info *info, char *options,
 			break;
 		case Opt_check_integrity_print_mask:
 			ret = match_int(&args[0], &intarg);
-			if (ret)
+			if (ret) {
+				btrfs_err(info,
+				"unrecognized check_integrity_print_mask value %s",
+					args[0].from);
 				goto out;
+			}
 			info->check_integrity_print_mask = intarg;
 			btrfs_info(info, "check_integrity_print_mask 0x%x",
 				   info->check_integrity_print_mask);
@@ -1030,13 +1046,15 @@ int btrfs_parse_options(struct btrfs_fs_info *info, char *options,
 			goto out;
 #endif
 		case Opt_fatal_errors:
-			if (strcmp(args[0].from, "panic") == 0)
+			if (strcmp(args[0].from, "panic") == 0) {
 				btrfs_set_opt(info->mount_opt,
 					      PANIC_ON_FATAL_ERROR);
-			else if (strcmp(args[0].from, "bug") == 0)
+			} else if (strcmp(args[0].from, "bug") == 0) {
 				btrfs_clear_opt(info->mount_opt,
 					      PANIC_ON_FATAL_ERROR);
-			else {
+			} else {
+				btrfs_err(info, "unrecognized fatal_errors value %s",
+					  args[0].from);
 				ret = -EINVAL;
 				goto out;
 			}
@@ -1044,8 +1062,12 @@ int btrfs_parse_options(struct btrfs_fs_info *info, char *options,
 		case Opt_commit_interval:
 			intarg = 0;
 			ret = match_int(&args[0], &intarg);
-			if (ret)
+			if (ret) {
+				btrfs_err(info, "unrecognized commit_interval value %s",
+					  args[0].from);
+				ret = -EINVAL;
 				goto out;
+			}
 			if (intarg == 0) {
 				btrfs_info(info,
 					   "using default commit interval %us",
@@ -1059,8 +1081,11 @@ int btrfs_parse_options(struct btrfs_fs_info *info, char *options,
 			break;
 		case Opt_rescue:
 			ret = parse_rescue_options(info, args[0].from);
-			if (ret < 0)
+			if (ret < 0) {
+				btrfs_err(info, "unrecognized rescue value %s",
+					  args[0].from);
 				goto out;
+			}
 			break;
 #ifdef CONFIG_BTRFS_DEBUG
 		case Opt_fragment_all:
-- 
GitLab


From 34b68c17e9895ba66fc809224b0122a2eed7aa40 Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Tue, 7 Jun 2022 12:22:07 +0300
Subject: [PATCH 0281/1731] drm/i915/client: only include what's needed

Only the uapi header is required.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220607092207.476653-1-jani.nikula@intel.com
---
 drivers/gpu/drm/i915/i915_drm_client.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drm_client.h b/drivers/gpu/drm/i915/i915_drm_client.h
index f796c5e8e0606..69496af996d9e 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.h
+++ b/drivers/gpu/drm/i915/i915_drm_client.h
@@ -11,7 +11,7 @@
 #include <linux/spinlock.h>
 #include <linux/xarray.h>
 
-#include "gt/intel_engine_types.h"
+#include <uapi/drm/i915_drm.h>
 
 #define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_COMPUTE
 
-- 
GitLab


From 330c1b3180b0d79fef7c05331647f3695661b79e Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Tue, 7 Jun 2022 12:42:05 +0300
Subject: [PATCH 0282/1731] drm/i915/tasklet: separate local hacks around
 struct tasklet_struct

Add a dedicated file for the local functions around struct
tasklet_struct. Far from ideal, but better placed in a dedicated file
than i915_gem.h.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220607094207.536699-1-jani.nikula@intel.com
---
 drivers/gpu/drm/i915/TODO.txt         |  2 +-
 drivers/gpu/drm/i915/i915_gem.h       | 33 --------------------
 drivers/gpu/drm/i915/i915_scheduler.h |  1 +
 drivers/gpu/drm/i915/i915_tasklet.h   | 43 +++++++++++++++++++++++++++
 4 files changed, 45 insertions(+), 34 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_tasklet.h

diff --git a/drivers/gpu/drm/i915/TODO.txt b/drivers/gpu/drm/i915/TODO.txt
index 81a82c9c203f5..879b08ca32b36 100644
--- a/drivers/gpu/drm/i915/TODO.txt
+++ b/drivers/gpu/drm/i915/TODO.txt
@@ -37,5 +37,5 @@ Smaller things:
 
   https://lore.kernel.org/linux-mm/20210301083320.943079-1-hch@lst.de/
 
-- tasklet helpers in i915_gem.h also look a bit misplaced and should
+- tasklet helpers in i915_tasklet.h also look a bit misplaced and should
   probably be moved to tasklet headers.
diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index a2be323a4be55..68d8d52bd541d 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -26,7 +26,6 @@
 #define __I915_GEM_H__
 
 #include <linux/bug.h>
-#include <linux/interrupt.h>
 
 #include <drm/drm_drv.h>
 
@@ -85,36 +84,4 @@ struct drm_i915_private;
 
 #define I915_GEM_IDLE_TIMEOUT (HZ / 5)
 
-static inline void tasklet_lock(struct tasklet_struct *t)
-{
-	while (!tasklet_trylock(t))
-		cpu_relax();
-}
-
-static inline bool tasklet_is_locked(const struct tasklet_struct *t)
-{
-	return test_bit(TASKLET_STATE_RUN, &t->state);
-}
-
-static inline void __tasklet_disable_sync_once(struct tasklet_struct *t)
-{
-	if (!atomic_fetch_inc(&t->count))
-		tasklet_unlock_spin_wait(t);
-}
-
-static inline bool __tasklet_is_enabled(const struct tasklet_struct *t)
-{
-	return !atomic_read(&t->count);
-}
-
-static inline bool __tasklet_enable(struct tasklet_struct *t)
-{
-	return atomic_dec_and_test(&t->count);
-}
-
-static inline bool __tasklet_is_scheduled(struct tasklet_struct *t)
-{
-	return test_bit(TASKLET_STATE_SCHED, &t->state);
-}
-
 #endif /* __I915_GEM_H__ */
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h
index 0b9b86af6c7f1..c229c91071d7f 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -12,6 +12,7 @@
 #include <linux/kernel.h>
 
 #include "i915_scheduler_types.h"
+#include "i915_tasklet.h"
 
 struct drm_printer;
 
diff --git a/drivers/gpu/drm/i915/i915_tasklet.h b/drivers/gpu/drm/i915/i915_tasklet.h
new file mode 100644
index 0000000000000..5d7069bdf2c07
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_tasklet.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __I915_TASKLET_H__
+#define __I915_TASKLET_H__
+
+#include <linux/interrupt.h>
+
+static inline void tasklet_lock(struct tasklet_struct *t)
+{
+	while (!tasklet_trylock(t))
+		cpu_relax();
+}
+
+static inline bool tasklet_is_locked(const struct tasklet_struct *t)
+{
+	return test_bit(TASKLET_STATE_RUN, &t->state);
+}
+
+static inline void __tasklet_disable_sync_once(struct tasklet_struct *t)
+{
+	if (!atomic_fetch_inc(&t->count))
+		tasklet_unlock_spin_wait(t);
+}
+
+static inline bool __tasklet_is_enabled(const struct tasklet_struct *t)
+{
+	return !atomic_read(&t->count);
+}
+
+static inline bool __tasklet_enable(struct tasklet_struct *t)
+{
+	return atomic_dec_and_test(&t->count);
+}
+
+static inline bool __tasklet_is_scheduled(struct tasklet_struct *t)
+{
+	return test_bit(TASKLET_STATE_SCHED, &t->state);
+}
+
+#endif /* __I915_TASKLET_H__ */
-- 
GitLab


From 38353a5e3da0b26fab9eeff13a482b135512d9c0 Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Tue, 7 Jun 2022 12:42:06 +0300
Subject: [PATCH 0283/1731] drm/i915/drv: drop intel_bios.h include

No longer needed after panel data was moved.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220607094207.536699-2-jani.nikula@intel.com
---
 drivers/gpu/drm/i915/i915_drv.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c70c80f5799a2..4ac8d636ecc99 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -37,7 +37,6 @@
 #include <drm/drm_connector.h>
 #include <drm/ttm/ttm_device.h>
 
-#include "display/intel_bios.h"
 #include "display/intel_cdclk.h"
 #include "display/intel_display.h"
 #include "display/intel_display_power.h"
-- 
GitLab


From aec23025ebc86b770beb9dab6610b671e63d36a2 Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Tue, 7 Jun 2022 12:42:07 +0300
Subject: [PATCH 0284/1731] drm/i915/utils: throw out unused stuff

Remove some of the unused helpers from i915_utils.h.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220607094207.536699-3-jani.nikula@intel.com
---
 drivers/gpu/drm/i915/i915_utils.h | 40 -------------------------------
 1 file changed, 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_utils.h b/drivers/gpu/drm/i915/i915_utils.h
index ea7648e3aa0e2..c10d68cdc3ca5 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -115,39 +115,6 @@ bool i915_error_injected(void);
 #define overflows_type(x, T) \
 	(sizeof(x) > sizeof(T) && (x) >> BITS_PER_TYPE(T))
 
-static inline bool
-__check_struct_size(size_t base, size_t arr, size_t count, size_t *size)
-{
-	size_t sz;
-
-	if (check_mul_overflow(count, arr, &sz))
-		return false;
-
-	if (check_add_overflow(sz, base, &sz))
-		return false;
-
-	*size = sz;
-	return true;
-}
-
-/**
- * check_struct_size() - Calculate size of structure with trailing array.
- * @p: Pointer to the structure.
- * @member: Name of the array member.
- * @n: Number of elements in the array.
- * @sz: Total size of structure and array
- *
- * Calculates size of memory needed for structure @p followed by an
- * array of @n @member elements, like struct_size() but reports
- * whether it overflowed, and the resultant size in @sz
- *
- * Return: false if the calculation overflowed.
- */
-#define check_struct_size(p, member, n, sz) \
-	likely(__check_struct_size(sizeof(*(p)), \
-				   sizeof(*(p)->member) + __must_be_array((p)->member), \
-				   n, sz))
-
 #define ptr_mask_bits(ptr, n) ({					\
 	unsigned long __v = (unsigned long)(ptr);			\
 	(typeof(ptr))(__v & -BIT(n));					\
@@ -184,8 +151,6 @@ __check_struct_size(size_t base, size_t arr, size_t count, size_t *size)
 
 #define struct_member(T, member) (((T *)0)->member)
 
-#define ptr_offset(ptr, member) offsetof(typeof(*(ptr)), member)
-
 #define fetch_and_zero(ptr) ({						\
 	typeof(*ptr) __T = *(ptr);					\
 	*(ptr) = (typeof(*ptr))0;					\
@@ -228,11 +193,6 @@ static __always_inline ptrdiff_t ptrdiff(const void *a, const void *b)
 	get_user(mbz__, (U)) ? -EFAULT : mbz__ ? -EINVAL : 0;		\
 })
 
-static inline u64 ptr_to_u64(const void *ptr)
-{
-	return (uintptr_t)ptr;
-}
-
 #define u64_to_ptr(T, x) ({						\
 	typecheck(u64, x);						\
 	(T *)(uintptr_t)(x);						\
-- 
GitLab


From 4464bd825dd56c2f900038c5922408d70aab01fc Mon Sep 17 00:00:00 2001
From: Luca Coelho <luciano.coelho@intel.com>
Date: Tue, 7 Jun 2022 10:44:33 +0300
Subject: [PATCH 0285/1731] drm/i915: remove noisy logs in
 intel_dp_dsc_get_output_bpp()

The intel_dp_dsc_get_output_bpp() function outputs two lines of
unconditional logs, which was okay when it was called only once.  But
now, we also call this function from intel_dp_mode_valid(), which is
in turn called for every mode we need to validate.  This causes a lot
of useless noise.

Remove the unconditional prints to avoid spamming the logs.  Also
remove one more print that is not unconditional, but is related.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220607074433.1202917-1-luca@coelho.fi
---
 drivers/gpu/drm/i915/display/intel_dp.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a00c82ac46f48..3d630f98b1f14 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -657,7 +657,6 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 	 */
 	bits_per_pixel = (link_clock * lane_count * 8) /
 			 intel_dp_mode_to_fec_clock(mode_clock);
-	drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
 
 	/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 	max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
@@ -666,9 +665,6 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 	if (bigjoiner)
 		max_bpp_small_joiner_ram *= 2;
 
-	drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
-		    max_bpp_small_joiner_ram);
-
 	/*
 	 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 	 * check, output bpp from small joiner RAM check)
@@ -680,7 +676,6 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 			i915->max_cdclk_freq * 48 /
 			intel_dp_mode_to_fec_clock(mode_clock);
 
-		drm_dbg_kms(&i915->drm, "Max big joiner bpp: %u\n", max_bpp_bigjoiner);
 		bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
 	}
 
-- 
GitLab


From 5871321fb4558c55bf9567052b618ff0be6b975e Mon Sep 17 00:00:00 2001
From: Mark Brown <broonie@kernel.org>
Date: Sat, 4 Jun 2022 11:52:46 +0100
Subject: [PATCH 0286/1731] ASoC: ops: Fix off by one in range control
 validation

We currently report that range controls accept a range of 0..(max-min) but
accept writes in the range 0..(max-min+1). Remove that extra +1.

Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220604105246.4055214-1-broonie@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/soc-ops.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/soc/soc-ops.c b/sound/soc/soc-ops.c
index e693070f51fe8..d867f449d82db 100644
--- a/sound/soc/soc-ops.c
+++ b/sound/soc/soc-ops.c
@@ -526,7 +526,7 @@ int snd_soc_put_volsw_range(struct snd_kcontrol *kcontrol,
 		return -EINVAL;
 	if (mc->platform_max && tmp > mc->platform_max)
 		return -EINVAL;
-	if (tmp > mc->max - mc->min + 1)
+	if (tmp > mc->max - mc->min)
 		return -EINVAL;
 
 	if (invert)
@@ -547,7 +547,7 @@ int snd_soc_put_volsw_range(struct snd_kcontrol *kcontrol,
 			return -EINVAL;
 		if (mc->platform_max && tmp > mc->platform_max)
 			return -EINVAL;
-		if (tmp > mc->max - mc->min + 1)
+		if (tmp > mc->max - mc->min)
 			return -EINVAL;
 
 		if (invert)
-- 
GitLab


From 122e951eb8045338089b086c8bd9b0b9afb04a92 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sat, 4 Jun 2022 21:33:00 +0200
Subject: [PATCH 0287/1731] regulator: qcom_smd: correct MP5496 ranges

Currently set MP5496 Buck and LDO ranges dont match its datasheet[1].
According to the datasheet:
Buck range is 0.6-2.1875V with a 12.5mV step
LDO range is 0.8-3.975V with a 25mV step.

So, correct the ranges according to the datasheet[1].

[1] https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/MP5496GR/document_id/6906/

Signed-off-by: Robert Marko <robimarko@gmail.com>
Link: https://lore.kernel.org/r/20220604193300.125758-2-robimarko@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 drivers/regulator/qcom_smd-regulator.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/regulator/qcom_smd-regulator.c b/drivers/regulator/qcom_smd-regulator.c
index 7dff94a2eb7e9..ef6e47d025cad 100644
--- a/drivers/regulator/qcom_smd-regulator.c
+++ b/drivers/regulator/qcom_smd-regulator.c
@@ -723,19 +723,19 @@ static const struct regulator_desc pms405_pldo600 = {
 
 static const struct regulator_desc mp5496_smpa2 = {
 	.linear_ranges = (struct linear_range[]) {
-		REGULATOR_LINEAR_RANGE(725000, 0, 27, 12500),
+		REGULATOR_LINEAR_RANGE(600000, 0, 127, 12500),
 	},
 	.n_linear_ranges = 1,
-	.n_voltages = 28,
+	.n_voltages = 128,
 	.ops = &rpm_mp5496_ops,
 };
 
 static const struct regulator_desc mp5496_ldoa2 = {
 	.linear_ranges = (struct linear_range[]) {
-		REGULATOR_LINEAR_RANGE(1800000, 0, 60, 25000),
+		REGULATOR_LINEAR_RANGE(800000, 0, 127, 25000),
 	},
 	.n_linear_ranges = 1,
-	.n_voltages = 61,
+	.n_voltages = 128,
 	.ops = &rpm_mp5496_ops,
 };
 
-- 
GitLab


From ae204faa949d76eb89fa31f18c51c09ada5dad4f Mon Sep 17 00:00:00 2001
From: Guchun Chen <guchun.chen@amd.com>
Date: Mon, 6 Jun 2022 10:09:48 +0800
Subject: [PATCH 0288/1731] Revert "drm/amdgpu: Ensure the DMA engine is
 deactivated during set ups"

This reverts commit b992a19085885c096b19625a85c674cb89829ca1.

This causes regression in GPU reset related test.

Cc: Alexander Deucher <Alexander.Deucher@amd.com>
Cc: ricetons@gmail.com
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 109 ++++++++++---------------
 1 file changed, 45 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 06b2635b142a5..83c6ccaaa9e4e 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -469,6 +469,7 @@ static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se
 	}
 }
 
+
 /**
  * sdma_v5_2_gfx_stop - stop the gfx async dma engines
  *
@@ -514,21 +515,17 @@ static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
 }
 
 /**
- * sdma_v5_2_ctx_switch_enable_for_instance - start the async dma engines
- * context switch for an instance
+ * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch
  *
  * @adev: amdgpu_device pointer
- * @instance_idx: the index of the SDMA instance
+ * @enable: enable/disable the DMA MEs context switch.
  *
- * Unhalt the async dma engines context switch.
+ * Halt or unhalt the async dma engines context switch.
  */
-static void sdma_v5_2_ctx_switch_enable_for_instance(struct amdgpu_device *adev, int instance_idx)
+static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 {
 	u32 f32_cntl, phase_quantum = 0;
-
-	if (WARN_ON(instance_idx >= adev->sdma.num_instances)) {
-		return;
-	}
+	int i;
 
 	if (amdgpu_sdma_phase_quantum) {
 		unsigned value = amdgpu_sdma_phase_quantum;
@@ -552,68 +549,50 @@ static void sdma_v5_2_ctx_switch_enable_for_instance(struct amdgpu_device *adev,
 		phase_quantum =
 			value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 			unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
-
-		WREG32_SOC15_IP(GC,
-			sdma_v5_2_get_reg_offset(adev, instance_idx, mmSDMA0_PHASE0_QUANTUM),
-			phase_quantum);
-		WREG32_SOC15_IP(GC,
-			sdma_v5_2_get_reg_offset(adev, instance_idx, mmSDMA0_PHASE1_QUANTUM),
-		    phase_quantum);
-		WREG32_SOC15_IP(GC,
-			sdma_v5_2_get_reg_offset(adev, instance_idx, mmSDMA0_PHASE2_QUANTUM),
-		    phase_quantum);
 	}
 
-	if (!amdgpu_sriov_vf(adev)) {
-		f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, instance_idx, mmSDMA0_CNTL));
-		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
-				AUTO_CTXSW_ENABLE, 1);
-		WREG32(sdma_v5_2_get_reg_offset(adev, instance_idx, mmSDMA0_CNTL), f32_cntl);
+	for (i = 0; i < adev->sdma.num_instances; i++) {
+		if (enable && amdgpu_sdma_phase_quantum) {
+			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
+			       phase_quantum);
+			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
+			       phase_quantum);
+			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
+			       phase_quantum);
+		}
+
+		if (!amdgpu_sriov_vf(adev)) {
+			f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
+			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
+					AUTO_CTXSW_ENABLE, enable ? 1 : 0);
+			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
+		}
 	}
+
 }
 
 /**
- * sdma_v5_2_ctx_switch_disable_all - stop the async dma engines context switch
+ * sdma_v5_2_enable - stop the async dma engines
  *
  * @adev: amdgpu_device pointer
+ * @enable: enable/disable the DMA MEs.
  *
- * Halt the async dma engines context switch.
+ * Halt or unhalt the async dma engines.
  */
-static void sdma_v5_2_ctx_switch_disable_all(struct amdgpu_device *adev)
+static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
 {
 	u32 f32_cntl;
 	int i;
 
-	if (amdgpu_sriov_vf(adev))
-		return;
-
-	for (i = 0; i < adev->sdma.num_instances; i++) {
-		f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
-		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
-				AUTO_CTXSW_ENABLE, 0);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
+	if (!enable) {
+		sdma_v5_2_gfx_stop(adev);
+		sdma_v5_2_rlc_stop(adev);
 	}
-}
-
-/**
- * sdma_v5_2_halt - stop the async dma engines
- *
- * @adev: amdgpu_device pointer
- *
- * Halt the async dma engines.
- */
-static void sdma_v5_2_halt(struct amdgpu_device *adev)
-{
-	int i;
-	u32 f32_cntl;
-
-	sdma_v5_2_gfx_stop(adev);
-	sdma_v5_2_rlc_stop(adev);
 
 	if (!amdgpu_sriov_vf(adev)) {
 		for (i = 0; i < adev->sdma.num_instances; i++) {
 			f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
-			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
+			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 		}
 	}
@@ -625,9 +604,6 @@ static void sdma_v5_2_halt(struct amdgpu_device *adev)
  * @adev: amdgpu_device pointer
  *
  * Set up the gfx DMA ring buffers and enable them.
- * It assumes that the dma engine is stopped for each instance.
- * The function enables the engine and preemptions sequentially for each instance.
- *
  * Returns 0 for success, error for failure.
  */
 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
@@ -769,7 +745,10 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 
 		ring->sched.ready = true;
 
-		sdma_v5_2_ctx_switch_enable_for_instance(adev, i);
+		if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
+			sdma_v5_2_ctx_switch_enable(adev, true);
+			sdma_v5_2_enable(adev, true);
+		}
 
 		r = amdgpu_ring_test_ring(ring);
 		if (r) {
@@ -813,7 +792,7 @@ static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
 	int i, j;
 
 	/* halt the MEs */
-	sdma_v5_2_halt(adev);
+	sdma_v5_2_enable(adev, false);
 
 	for (i = 0; i < adev->sdma.num_instances; i++) {
 		if (!adev->sdma.instance[i].fw)
@@ -885,8 +864,8 @@ static int sdma_v5_2_start(struct amdgpu_device *adev)
 	int r = 0;
 
 	if (amdgpu_sriov_vf(adev)) {
-		sdma_v5_2_ctx_switch_disable_all(adev);
-		sdma_v5_2_halt(adev);
+		sdma_v5_2_ctx_switch_enable(adev, false);
+		sdma_v5_2_enable(adev, false);
 
 		/* set RB registers */
 		r = sdma_v5_2_gfx_resume(adev);
@@ -910,10 +889,12 @@ static int sdma_v5_2_start(struct amdgpu_device *adev)
 		amdgpu_gfx_off_ctrl(adev, false);
 
 	sdma_v5_2_soft_reset(adev);
+	/* unhalt the MEs */
+	sdma_v5_2_enable(adev, true);
+	/* enable sdma ring preemption */
+	sdma_v5_2_ctx_switch_enable(adev, true);
 
-	/* Soft reset supposes to disable the dma engine and preemption.
-	 * Now start the gfx rings and rlc compute queues.
-	 */
+	/* start the gfx rings and rlc compute queues */
 	r = sdma_v5_2_gfx_resume(adev);
 	if (adev->in_s0ix)
 		amdgpu_gfx_off_ctrl(adev, true);
@@ -1447,8 +1428,8 @@ static int sdma_v5_2_hw_fini(void *handle)
 	if (amdgpu_sriov_vf(adev))
 		return 0;
 
-	sdma_v5_2_ctx_switch_disable_all(adev);
-	sdma_v5_2_halt(adev);
+	sdma_v5_2_ctx_switch_enable(adev, false);
+	sdma_v5_2_enable(adev, false);
 
 	return 0;
 }
-- 
GitLab


From 165ab7b4319d8ecbb689f3d68f0cd6bda4d82b1c Mon Sep 17 00:00:00 2001
From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Date: Tue, 17 May 2022 10:12:27 -0400
Subject: [PATCH 0289/1731] Revert "drm/amd/display: Pass the new context into
 disable OTG WA"

This reverts commit 8440f57532496d398a461887e56ca6f45089fbcf.

Causes a hang when hotplugging DP, shutting down system, or
enabling dual eDP.

Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c  | 8 ++++----
 .../drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c    | 8 ++++----
 .../drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c    | 8 ++++----
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
index 6a81c1aea0be5..bca5f01da7637 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
@@ -99,13 +99,13 @@ static int dcn31_get_active_display_cnt_wa(
 	return display_count;
 }
 
-static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
+static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
 {
 	struct dc *dc = clk_mgr_base->ctx->dc;
 	int i;
 
 	for (i = 0; i < dc->res_pool->pipe_count; ++i) {
-		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 
 		if (pipe->top_pipe || pipe->prev_odm_pipe)
 			continue;
@@ -211,11 +211,11 @@ void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
 	}
 
 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
-		dcn31_disable_otg_wa(clk_mgr_base, context, true);
+		dcn31_disable_otg_wa(clk_mgr_base, true);
 
 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
 		dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
-		dcn31_disable_otg_wa(clk_mgr_base, context, false);
+		dcn31_disable_otg_wa(clk_mgr_base, false);
 
 		update_dispclk = true;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
index aa01a18df419f..fb4ae800e9193 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
@@ -79,13 +79,13 @@ static int dcn315_get_active_display_cnt_wa(
 	return display_count;
 }
 
-static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
+static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
 {
 	struct dc *dc = clk_mgr_base->ctx->dc;
 	int i;
 
 	for (i = 0; i < dc->res_pool->pipe_count; ++i) {
-		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 
 		if (pipe->top_pipe || pipe->prev_odm_pipe)
 			continue;
@@ -173,11 +173,11 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
 	}
 
 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
-		dcn315_disable_otg_wa(clk_mgr_base, context, true);
+		dcn315_disable_otg_wa(clk_mgr_base, true);
 
 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
 		dcn315_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
-		dcn315_disable_otg_wa(clk_mgr_base, context, false);
+		dcn315_disable_otg_wa(clk_mgr_base, false);
 
 		update_dispclk = true;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
index 7192f30858eb4..e4bb9c6193b57 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
@@ -112,13 +112,13 @@ static int dcn316_get_active_display_cnt_wa(
 	return display_count;
 }
 
-static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
+static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
 {
 	struct dc *dc = clk_mgr_base->ctx->dc;
 	int i;
 
 	for (i = 0; i < dc->res_pool->pipe_count; ++i) {
-		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 
 		if (pipe->top_pipe || pipe->prev_odm_pipe)
 			continue;
@@ -221,11 +221,11 @@ static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base,
 	}
 
 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
-		dcn316_disable_otg_wa(clk_mgr_base, context, true);
+		dcn316_disable_otg_wa(clk_mgr_base, true);
 
 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
 		dcn316_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
-		dcn316_disable_otg_wa(clk_mgr_base, context, false);
+		dcn316_disable_otg_wa(clk_mgr_base, false);
 
 		update_dispclk = true;
 	}
-- 
GitLab


From 77361ed89a8b03c7e121f4b8c517d7be93ccd8df Mon Sep 17 00:00:00 2001
From: Jimmy Kizito <Jimmy.Kizito@amd.com>
Date: Thu, 24 Mar 2022 13:42:45 -0400
Subject: [PATCH 0290/1731] drm/amd/display: Avoid reading LTTPR caps in
 non-LTTPR mode.

[Why]
LTTPR capable devices on the DisplayPort path may assume that
extended LTTPR AUX timeouts will be used after LTTPR capabilities
are read.

When DPTX operates in non-LTTPR mode, AUX timeouts are not
extended and this can result in AUX transactions timing out.

[How]
Use shared helper function to determine LTTPR mode and do not
read LTTPR capabilities in non-LTTPR mode.

Reviewed-by: Mustapha Ghaddar <Mustapha.Ghaddar@amd.com>
Reviewed-by: Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 44 +++++++++++++------
 1 file changed, 31 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 1ec81426498f4..2d0e41761c322 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -5129,16 +5129,13 @@ static bool dpcd_read_sink_ext_caps(struct dc_link *link)
 	return true;
 }
 
-bool dp_retrieve_lttpr_cap(struct dc_link *link)
+/* Logic to determine LTTPR mode */
+static void determine_lttpr_mode(struct dc_link *link)
 {
-	uint8_t lttpr_dpcd_data[8];
 	bool allow_lttpr_non_transparent_mode = 0;
 	bool vbios_lttpr_enable = link->dc->caps.vbios_lttpr_enable;
 	bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;
-	enum dc_status status = DC_ERROR_UNEXPECTED;
-	bool is_lttpr_present = false;
 
-	memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
 
 	if ((link->dc->config.allow_lttpr_non_transparent_mode.bits.DP2_0 &&
 			link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED)) {
@@ -5148,9 +5145,6 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
 		allow_lttpr_non_transparent_mode = 1;
 	}
 
-	/*
-	 * Logic to determine LTTPR mode
-	 */
 	link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
 	if (vbios_lttpr_enable && vbios_lttpr_interop)
 		link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
@@ -5172,6 +5166,18 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
 	    link->dc->debug.dpia_debug.bits.force_non_lttpr)
 		link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
 #endif
+}
+
+bool dp_retrieve_lttpr_cap(struct dc_link *link)
+{
+	uint8_t lttpr_dpcd_data[8];
+	enum dc_status status = DC_ERROR_UNEXPECTED;
+	bool is_lttpr_present = false;
+
+	memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
+
+	/* Logic to determine LTTPR mode*/
+	determine_lttpr_mode(link);
 
 	if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
 		/* By reading LTTPR capability, RX assumes that we will enable
@@ -5287,11 +5293,23 @@ static enum dc_status wa_try_to_wake_dprx(struct dc_link *link, uint64_t timeout
 	uint64_t time_taken_ms = 0;
 	enum dc_connection_type type = dc_connection_none;
 
-	status = core_link_read_dpcd(
-			link,
-			DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
-			&dpcd_data,
-			sizeof(dpcd_data));
+	determine_lttpr_mode(link);
+
+	/* Issue an AUX read to test DPRX responsiveness. If LTTPR is supported the first read is expected to
+	 * be to determine LTTPR capabilities. Otherwise trying to read power state should be an innocuous AUX read.
+	 */
+	if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT)
+		status = core_link_read_dpcd(
+				link,
+				DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
+				&dpcd_data,
+				sizeof(dpcd_data));
+	else
+		status = core_link_read_dpcd(
+				link,
+				DP_SET_POWER,
+				&dpcd_data,
+				sizeof(dpcd_data));
 
 	if (status != DC_OK) {
 		DC_LOG_WARNING("%s: Read DPCD LTTPR_CAP failed - try to toggle DPCD SET_POWER for %lld ms.",
-- 
GitLab


From 2d017189e2b39cf2fae63984215385401b77ea83 Mon Sep 17 00:00:00 2001
From: Duncan Ma <duncan.ma@amd.com>
Date: Thu, 12 May 2022 14:46:24 -0400
Subject: [PATCH 0291/1731] drm/amd/display: Blank eDP on enable drv if odm
 enabled

[Why]
For panels with pixel clock > 1200MHz that require ODM
in pre-OS, when driver is disabled in OS, odm is enabled.
Upon driver enablement, corruption is seen if
odm was originally enabled. DP_PIXEL_COMBINE and
pixelclk must be programmed prior to programming the
optc-odm registers. However, eDP displays aren't blanked
prior to initializing odm in this case.

[How]
Upon driver enablement, check whether odm is enabled,
if so, blank eDP prior to programming optc-odm
registers.

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 20 +++++++++++++++++
 drivers/gpu/drm/amd/display/dc/dc.h           |  1 +
 drivers/gpu/drm/amd/display/dc/dc_link.h      |  1 +
 .../drm/amd/display/dc/dcn31/dcn31_hwseq.c    | 22 +++++++++++++++++++
 4 files changed, 44 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 31ffb961e18b5..38a4581417919 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2126,6 +2126,26 @@ void dc_link_blank_all_dp_displays(struct dc *dc)
 
 }
 
+void dc_link_blank_all_edp_displays(struct dc *dc)
+{
+	unsigned int i;
+	uint8_t dpcd_power_state = '\0';
+	enum dc_status status = DC_ERROR_UNEXPECTED;
+
+	for (i = 0; i < dc->link_count; i++) {
+		if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) ||
+			(!dc->links[i]->edp_sink_present))
+			continue;
+
+		/* if any of the displays are lit up turn them off */
+		status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
+							&dpcd_power_state, sizeof(dpcd_power_state));
+
+		if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0)
+			dc_link_blank_dp_stream(dc->links[i], true);
+	}
+}
+
 void dc_link_blank_dp_stream(struct dc_link *link, bool hw_init)
 {
 	unsigned int j;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 7bb67ab979e1a..5a6c9a139e85b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -216,6 +216,7 @@ struct dc_caps {
 	uint16_t subvp_pstate_allow_width_us;
 	uint16_t subvp_vertical_int_margin_us;
 #endif
+	bool seamless_odm;
 };
 
 struct dc_bug_wa {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 0bec986a6de81..c4a42d758b4e8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -322,6 +322,7 @@ bool dc_link_setup_psr(struct dc_link *dc_link,
 void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency);
 
 void dc_link_blank_all_dp_displays(struct dc *dc);
+void dc_link_blank_all_edp_displays(struct dc *dc);
 
 void dc_link_blank_dp_stream(struct dc_link *link, bool hw_init);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 531dd2c65007d..55f2e30b8e5aa 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -213,6 +213,28 @@ void dcn31_init_hw(struct dc *dc)
 	 * everything down.
 	 */
 	if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
+
+		// we want to turn off edp displays if odm is enabled and no seamless boot
+		if (!dc->caps.seamless_odm) {
+			for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
+				struct timing_generator *tg = dc->res_pool->timing_generators[i];
+				uint32_t num_opps, opp_id_src0, opp_id_src1;
+
+				num_opps = 1;
+				if (tg) {
+					if (tg->funcs->is_tg_enabled(tg) && tg->funcs->get_optc_source) {
+						tg->funcs->get_optc_source(tg, &num_opps,
+								&opp_id_src0, &opp_id_src1);
+					}
+				}
+
+				if (num_opps > 1) {
+					dc_link_blank_all_edp_displays(dc);
+					break;
+				}
+			}
+		}
+
 		hws->funcs.init_pipes(dc, dc->current_state);
 		if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
 			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
-- 
GitLab


From 0c56705d8aae9696348cc320b71d531ede001b79 Mon Sep 17 00:00:00 2001
From: Duncan Ma <duncan.ma@amd.com>
Date: Tue, 17 May 2022 17:50:23 -0400
Subject: [PATCH 0292/1731] drm/amd/display: Correct min comp buffer size

[Why]
In 3-way mpo pipes, there is a case that we
overbook the CRB buffer size. At rare instances,
overbooking the crb will cause underflow. This only
happens when det_size changes dynamically
based on pipe_cnt.

[How]
Set min compbuff size to 1 segment when preparing BW.

Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
index 54db2eca9e6b7..1b02f0ebe957d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
@@ -201,7 +201,7 @@ struct _vcs_dpi_ip_params_st dcn3_15_ip = {
 	.hostvm_max_page_table_levels = 2,
 	.rob_buffer_size_kbytes = 64,
 	.det_buffer_size_kbytes = DCN3_15_DEFAULT_DET_SIZE,
-	.min_comp_buffer_size_kbytes = DCN3_15_MIN_COMPBUF_SIZE_KB,
+	.min_comp_buffer_size_kbytes = 64,
 	.config_return_buffer_size_in_kbytes = 1024,
 	.compressed_buffer_segment_size_in_kbytes = 64,
 	.meta_fifo_size_in_kentries = 32,
@@ -297,6 +297,7 @@ struct _vcs_dpi_ip_params_st dcn3_16_ip = {
 	.hostvm_max_page_table_levels = 2,
 	.rob_buffer_size_kbytes = 64,
 	.det_buffer_size_kbytes = DCN3_16_DEFAULT_DET_SIZE,
+	.min_comp_buffer_size_kbytes = 64,
 	.config_return_buffer_size_in_kbytes = 1024,
 	.compressed_buffer_segment_size_in_kbytes = 64,
 	.meta_fifo_size_in_kentries = 32,
-- 
GitLab


From e5309d7f66105011e0597fd55ff2ef7f636f52c6 Mon Sep 17 00:00:00 2001
From: Wenjing Liu <wenjing.liu@amd.com>
Date: Fri, 13 May 2022 11:43:45 -0400
Subject: [PATCH 0293/1731] drm/amd/display: add DP sanity checks during enable
 stream

[why]
1. When HPD deassertion is pulled in the middle of
enabe stream link training, we will abort current training
and turn off PHY. This causes current link settings
to be zeroed this causes later stream enablement
sequence to fail as we prefer to carry on enablement
process despite of link training failure for SST.
2. When HPD is toggled after detection before before
the enable stream sequence as a result. There could be
a race condition where we could end up enable stream based
on the previous link even though the link is updated
after the HPD toggle. This causes an issue where our link
bandwidth is no longer enough to accommodate the timing
therefore causes us to oversubscribe MST payload time
slots. As discussed we decided to add basic sanity check
to make sure that our code can handle the oversubscription
failure silently without system hang.

[how]
1. Keep PHY powered on when HPD is deasserted during
enable stream and wait for the detection sequence to power
it off later.
2. Do not allocate payload if the required timeslot for
current timing is greater than 64 timeslots.

Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_debug.c   |  2 ++
 drivers/gpu/drm/amd/display/dc/core/dc_link.c    |  1 +
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 16 +++++++++++-----
 drivers/gpu/drm/amd/display/dc/inc/core_status.h |  2 +-
 4 files changed, 15 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index 72376075db0cd..283957dbdf93a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -422,6 +422,8 @@ char *dc_status_to_str(enum dc_status status)
 		return "The value specified is not supported.";
 	case DC_NO_LINK_ENC_RESOURCE:
 		return "No link encoder resource";
+	case DC_FAIL_DP_PAYLOAD_ALLOCATION:
+		return "Fail dp payload allocation";
 	case DC_ERROR_UNEXPECTED:
 		return "Unexpected error";
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 38a4581417919..ab9655d6e5c8a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3597,6 +3597,7 @@ static enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx,
 						"allocation table for "
 						"pipe idx: %d\n",
 						pipe_ctx->pipe_idx);
+		return DC_FAIL_DP_PAYLOAD_ALLOCATION;
 	}
 
 	proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 2d0e41761c322..0496828e86739 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2875,10 +2875,13 @@ bool perform_link_training_with_retries(
 
 		fail_count++;
 		dp_trace_lt_fail_count_update(link, fail_count, false);
-		/* latest link training still fail, skip delay and keep PHY on
-		 */
-		if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY)
-			break;
+		if (link->ep_type == DISPLAY_ENDPOINT_PHY) {
+			/* latest link training still fail or link training is aborted
+			 * skip delay and keep PHY on
+			 */
+			if (j == (attempts - 1) || (status == LINK_TRAINING_ABORT))
+				break;
+		}
 
 		DC_LOG_WARNING("%s: Link training attempt %u of %d failed @ rate(%d) x lane(%d)\n",
 			__func__, (unsigned int)j + 1, attempts, cur_link_settings.link_rate,
@@ -6890,6 +6893,10 @@ bool dpcd_write_128b_132b_sst_payload_allocation_table(
 	if (allocate)	{
 		avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, link);
 		req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
+		/// Validation should filter out modes that exceed link BW
+		ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT);
+		if (req_slot_count > MAX_MTP_SLOT_COUNT)
+			return false;
 	} else {
 		/// Leave req_slot_count = 0 if allocate is false.
 	}
@@ -6917,7 +6924,6 @@ bool dpcd_write_128b_132b_sst_payload_allocation_table(
 			&start_time_slot,
 			1);
 
-	ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); /// Validation should filter out modes that exceed link BW
 	core_link_write_dpcd(
 			link,
 			DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
index 444182a97e6ee..8eb8d4afa876e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
@@ -54,7 +54,7 @@ enum dc_status {
 	DC_UNSUPPORTED_VALUE = 25,
 
 	DC_NO_LINK_ENC_RESOURCE = 26,
-
+	DC_FAIL_DP_PAYLOAD_ALLOCATION = 27,
 	DC_ERROR_UNEXPECTED = -1
 };
 
-- 
GitLab


From d8791dc7f941f3dc78ef2c6aa71d7c752d5b529e Mon Sep 17 00:00:00 2001
From: Roman Li <roman.li@amd.com>
Date: Thu, 19 May 2022 14:41:16 -0400
Subject: [PATCH 0294/1731] drm/amd/display: Cap OLED brightness per max
 frame-average luminance

[Why]
For OLED eDP the Display Manager uses max_cll value as a limit
for brightness control.
max_cll defines the content light luminance for individual pixel.
Whereas max_fall defines frame-average level luminance.
The user may not observe the difference in brightness in between
max_fall and max_cll.
That negatively impacts the user experience.

[How]
Use max_fall value instead of max_cll as a limit for brightness control.

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 2bb316fa62b1e..e668bb1560da7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2843,7 +2843,7 @@ static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
 
 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
 {
-	u32 max_cll, min_cll, max, min, q, r;
+	u32 max_avg, min_cll, max, min, q, r;
 	struct amdgpu_dm_backlight_caps *caps;
 	struct amdgpu_display_manager *dm;
 	struct drm_connector *conn_base;
@@ -2873,7 +2873,7 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
 	caps = &dm->backlight_caps[i];
 	caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
 	caps->aux_support = false;
-	max_cll = conn_base->hdr_sink_metadata.hdmi_type1.max_cll;
+	max_avg = conn_base->hdr_sink_metadata.hdmi_type1.max_fall;
 	min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll;
 
 	if (caps->ext_caps->bits.oled == 1 /*||
@@ -2901,8 +2901,8 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
 	 * The results of the above expressions can be verified at
 	 * pre_computed_values.
 	 */
-	q = max_cll >> 5;
-	r = max_cll % 32;
+	q = max_avg >> 5;
+	r = max_avg % 32;
 	max = (1 << q) * pre_computed_values[r];
 
 	// min luminance: maxLum * (CV/255)^2 / 100
-- 
GitLab


From 8246370341e8e816ad22aaf8d8bfca850339ce0a Mon Sep 17 00:00:00 2001
From: Hansen Dsouza <Hansen.Dsouza@amd.com>
Date: Fri, 20 May 2022 16:39:29 -0400
Subject: [PATCH 0295/1731] drm/amd/display: Enable 3 plane MPO

[why and how]
3 plane MPO is a new feature missing in a few resource files
Enable 3 plane MPO by setting slave planes to 2

Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Hansen Dsouza <Hansen.Dsouza@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c | 6 +++---
 drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
index 2b42af030b330..4f45753484fe8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
@@ -1762,9 +1762,9 @@ static bool dcn315_resource_construct(
 	dc->caps.max_cursor_size = 256;
 	dc->caps.min_horizontal_blanking_period = 80;
 	dc->caps.dmdata_alloc_size = 2048;
-	dc->caps.max_slave_planes = 1;
-	dc->caps.max_slave_yuv_planes = 1;
-	dc->caps.max_slave_rgb_planes = 1;
+	dc->caps.max_slave_planes = 2;
+	dc->caps.max_slave_yuv_planes = 2;
+	dc->caps.max_slave_rgb_planes = 2;
 	dc->caps.post_blend_color_processing = true;
 	dc->caps.force_dp_tps4_for_cp2520 = true;
 	dc->caps.dp_hpo = true;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
index ef16260b7f3f2..f9cee05aeccc6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
@@ -1764,9 +1764,9 @@ static bool dcn316_resource_construct(
 	dc->caps.max_cursor_size = 256;
 	dc->caps.min_horizontal_blanking_period = 80;
 	dc->caps.dmdata_alloc_size = 2048;
-	dc->caps.max_slave_planes = 1;
-	dc->caps.max_slave_yuv_planes = 1;
-	dc->caps.max_slave_rgb_planes = 1;
+	dc->caps.max_slave_planes = 2;
+	dc->caps.max_slave_yuv_planes = 2;
+	dc->caps.max_slave_rgb_planes = 2;
 	dc->caps.post_blend_color_processing = true;
 	dc->caps.force_dp_tps4_for_cp2520 = true;
 	dc->caps.dp_hpo = true;
-- 
GitLab


From 874714feff3128dc691fc309ee8b9d479f541aa6 Mon Sep 17 00:00:00 2001
From: Anthony Koo <Anthony.Koo@amd.com>
Date: Sun, 22 May 2022 12:03:35 -0400
Subject: [PATCH 0296/1731] drm/amd/display: [FW Promotion] Release 0.0.119.0

Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index f6ad1b8c7034f..bf6f017858a68 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -1427,6 +1427,7 @@ struct dmub_rb_cmd_dp_set_config_reply {
 struct dmub_cmd_hpd_state_query_data {
 	uint8_t instance; /**< HPD instance or DPIA instance */
 	uint8_t result; /**< For returning HPD state */
+	uint16_t pad; /** < Alignment */
 	enum aux_channel_type ch_type; /**< enum aux_channel_type */
 	enum aux_return_code_type status; /**< for returning the status of command */
 };
-- 
GitLab


From a0b9e4531b2eaf066a1ccb2986f4d2f9efa6c313 Mon Sep 17 00:00:00 2001
From: Aric Cyr <aric.cyr@amd.com>
Date: Tue, 24 May 2022 09:29:28 -0400
Subject: [PATCH 0297/1731] drm/amd/display: 3.2.188

This version brings along the following:
- Optimized blank calculations
- More robust DP MST hotplug support
- eDP bug fix relating to ODM
- Revert a patch that caused a regression with DP
- min comp buffer size fix
- Make DP easier to debug
- Calculate the maximum OLED brightness correctly
- 3 plane MPO.

Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 5a6c9a139e85b..a1c965a84eba1 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -47,7 +47,7 @@ struct aux_payload;
 struct set_config_cmd_payload;
 struct dmub_notification;
 
-#define DC_VER "3.2.187"
+#define DC_VER "3.2.188"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
GitLab


From d4965c53b95d7533dfc2309d2fc25838bd33220e Mon Sep 17 00:00:00 2001
From: Duncan Ma <duncan.ma@amd.com>
Date: Wed, 25 May 2022 16:28:49 -0400
Subject: [PATCH 0298/1731] drm/amd/display: Fix dpp dto for disabled pipes

[Why]
When switching from 1 pipe to 4to1 mpc combine,
DppDtoClk aren't enabled for the disabled pipes
pior to programming the pipes. Upon optimizing
bandwidth, DppDto are enabled causing intermittent
underflow.

[How]
Update dppclk dto whenever pipe are flagged to
enable.

Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Reviewed-by: Hansen Dsouza <Hansen.Dsouza@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index aed8ab06b41d3..facd4e01b7ac1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1436,11 +1436,15 @@ static void dcn20_update_dchubp_dpp(
 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
+	struct dccg *dccg = dc->res_pool->dccg;
 	bool viewport_changed = false;
 
 	if (pipe_ctx->update_flags.bits.dppclk)
 		dpp->funcs->dpp_dppclk_control(dpp, false, true);
 
+	if (pipe_ctx->update_flags.bits.enable)
+		dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);
+
 	/* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
 	 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
 	 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
-- 
GitLab


From 6b6d12b6ff204cc224cd2369bda2b0580a80a5b3 Mon Sep 17 00:00:00 2001
From: Jimmy Kizito <Jimmy.Kizito@amd.com>
Date: Tue, 17 May 2022 13:31:03 -0400
Subject: [PATCH 0299/1731] drm/amd/display: Fix entry into transient encoder
 assignment mode.

[Why]
In some scenarios it is possible for the encoder assignment module to be
set to "transient" mode even though there are no new encoder
assignments.

This can lead to incorrect results when querying encoder assignment,
which in turn can cause incorrect displays to be manipulated.

[How]
Only allow encoder assignment to be in transient mode of operation when
there are valid new encoder assignments.

Reviewed-by: Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 17 ++++---
 .../drm/amd/display/dc/core/dc_link_enc_cfg.c | 45 ++++++++++++++++++-
 .../display/dc/dcn31/dcn31_dio_link_encoder.c |  6 +++
 .../drm/amd/display/dc/dcn31/dcn31_hwseq.c    |  2 +-
 .../gpu/drm/amd/display/dc/inc/link_enc_cfg.h |  7 +++
 5 files changed, 69 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 0496828e86739..c1207049dbc59 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2812,8 +2812,8 @@ bool perform_link_training_with_retries(
 	j = 0;
 	while (j < attempts && fail_count < (attempts * 10)) {
 
-		DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d @ rate(%d) x lane(%d)\n",
-			__func__, (unsigned int)j + 1, attempts, cur_link_settings.link_rate,
+		DC_LOG_HW_LINK_TRAINING("%s: Beginning link(%d) training attempt %u of %d @ rate(%d) x lane(%d)\n",
+			__func__, link->link_index, (unsigned int)j + 1, attempts, cur_link_settings.link_rate,
 			cur_link_settings.lane_count);
 
 		dp_enable_link_phy(
@@ -2883,8 +2883,8 @@ bool perform_link_training_with_retries(
 				break;
 		}
 
-		DC_LOG_WARNING("%s: Link training attempt %u of %d failed @ rate(%d) x lane(%d)\n",
-			__func__, (unsigned int)j + 1, attempts, cur_link_settings.link_rate,
+		DC_LOG_WARNING("%s: Link(%d) training attempt %u of %d failed @ rate(%d) x lane(%d)\n",
+			__func__, link->link_index, (unsigned int)j + 1, attempts, cur_link_settings.link_rate,
 			cur_link_settings.lane_count);
 
 		dp_disable_link_phy(link, &pipe_ctx->link_res, signal);
@@ -2927,8 +2927,13 @@ bool perform_link_training_with_retries(
 			 */
 			req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
 			link_bw = dc_link_bandwidth_kbps(link, &cur_link_settings);
-			if (req_bw > link_bw)
-				break;
+			is_link_bw_low = (req_bw > link_bw);
+			is_link_bw_min = ((cur_link_settings.link_rate <= LINK_RATE_LOW) &&
+				(cur_link_settings.lane_count <= LANE_COUNT_ONE));
+			if (is_link_bw_low)
+				DC_LOG_WARNING(
+					"%s: Link(%d) bandwidth too low after fallback req_bw(%d) > link_bw(%d)\n",
+					__func__, link->link_index, req_bw, link_bw);
 		}
 
 		msleep(delay_between_attempts);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
index 42da7f4301132..639a0a276a08e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
@@ -26,6 +26,8 @@
 #include "resource.h"
 #include "dc_link_dp.h"
 
+#define DC_LOGGER dc->ctx->logger
+
 /* Check whether stream is supported by DIG link encoders. */
 static bool is_dig_link_enc_stream(struct dc_stream_state *stream)
 {
@@ -383,6 +385,30 @@ void link_enc_cfg_link_encs_assign(
 			state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];
 	}
 
+	/* Log encoder assignments. */
+	for (i = 0; i < MAX_PIPES; i++) {
+		struct link_enc_assignment assignment =
+				dc->current_state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];
+
+		if (assignment.valid)
+			DC_LOG_DEBUG("%s: CUR %s(%d) - enc_id(%d)\n",
+					__func__,
+					assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ? "PHY" : "DPIA",
+					assignment.ep_id.link_id.enum_id - 1,
+					assignment.eng_id);
+	}
+	for (i = 0; i < MAX_PIPES; i++) {
+		struct link_enc_assignment assignment =
+				state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];
+
+		if (assignment.valid)
+			DC_LOG_DEBUG("%s: NEW %s(%d) - enc_id(%d)\n",
+					__func__,
+					assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ? "PHY" : "DPIA",
+					assignment.ep_id.link_id.enum_id - 1,
+					assignment.eng_id);
+	}
+
 	/* Current state mode will be set to steady once this state committed. */
 	state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY;
 }
@@ -658,8 +684,25 @@ bool link_enc_cfg_validate(struct dc *dc, struct dc_state *state)
 			((valid_uniqueness & 0x1) << 2) |
 			((valid_avail & 0x1) << 3) |
 			((valid_streams & 0x1) << 4);
-		dm_error("Invalid link encoder assignments: 0x%x\n", valid_bitmap);
+		DC_LOG_ERROR("%s: Invalid link encoder assignments - 0x%x\n", __func__, valid_bitmap);
 	}
 
 	return is_valid;
 }
+
+void link_enc_cfg_set_transient_mode(struct dc *dc, struct dc_state *current_state, struct dc_state *new_state)
+{
+	int i = 0;
+	int num_transient_assignments = 0;
+
+	for (i = 0; i < MAX_PIPES; i++) {
+		if (current_state->res_ctx.link_enc_cfg_ctx.transient_assignments[i].valid)
+			num_transient_assignments++;
+	}
+
+	/* Only enter transient mode if the new encoder assignments are valid. */
+	if (new_state->stream_count == num_transient_assignments) {
+		current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_TRANSIENT;
+		DC_LOG_DEBUG("%s: current_state(%p) mode(%d)\n", __func__, current_state, LINK_ENC_CFG_TRANSIENT);
+	}
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
index 8b12b4111c887..a788d160953b5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
@@ -458,6 +458,7 @@ void dcn31_link_encoder_enable_dp_output(
 	/* Enable transmitter and encoder. */
 	if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {
 
+		DC_LOG_DEBUG("%s: enc_id(%d)\n", __func__, enc->preferred_engine);
 		dcn20_link_encoder_enable_dp_output(enc, link_settings, clock_source);
 
 	} else {
@@ -489,6 +490,7 @@ void dcn31_link_encoder_enable_dp_output(
 			return;
 		}
 
+		DC_LOG_DEBUG("%s: DPIA(%d) - enc_id(%d)\n", __func__, dpia_control.dpia_id, dpia_control.enc_id);
 		link_dpia_control(enc->ctx, &dpia_control);
 	}
 }
@@ -503,6 +505,7 @@ void dcn31_link_encoder_enable_dp_mst_output(
 	/* Enable transmitter and encoder. */
 	if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {
 
+		DC_LOG_DEBUG("%s: enc_id(%d)\n", __func__, enc->preferred_engine);
 		dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source);
 
 	} else {
@@ -534,6 +537,7 @@ void dcn31_link_encoder_enable_dp_mst_output(
 			return;
 		}
 
+		DC_LOG_DEBUG("%s: DPIA(%d) - enc_id(%d)\n", __func__, dpia_control.dpia_id, dpia_control.enc_id);
 		link_dpia_control(enc->ctx, &dpia_control);
 	}
 }
@@ -547,6 +551,7 @@ void dcn31_link_encoder_disable_output(
 	/* Disable transmitter and encoder. */
 	if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {
 
+		DC_LOG_DEBUG("%s: enc_id(%d)\n", __func__, enc->preferred_engine);
 		dcn10_link_encoder_disable_output(enc, signal);
 
 	} else {
@@ -578,6 +583,7 @@ void dcn31_link_encoder_disable_output(
 			return;
 		}
 
+		DC_LOG_DEBUG("%s: DPIA(%d) - enc_id(%d)\n", __func__, dpia_control.dpia_id, dpia_control.enc_id);
 		link_dpia_control(enc->ctx, &dpia_control);
 
 		link_encoder_disable(enc10);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 55f2e30b8e5aa..1ed1404e969df 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -613,7 +613,7 @@ void dcn31_reset_hw_ctx_wrap(
 	}
 
 	/* New dc_state in the process of being applied to hardware. */
-	dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_TRANSIENT;
+	link_enc_cfg_set_transient_mode(dc, dc->current_state, context);
 }
 
 void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
index c6f6baa6e6774..7beb14169f92c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
@@ -110,4 +110,11 @@ bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id, struct
 /* Returns true if encoder assignments in supplied state pass validity checks. */
 bool link_enc_cfg_validate(struct dc *dc, struct dc_state *state);
 
+/* Set the link encoder assignment mode for the current_state to LINK_ENC_CFG_TRANSIENT mode.
+ * This indicates that a new_state is in the process of being applied to hardware.
+ * During this transition, old and new encoder assignments should be accessible from the old_state.
+ * Only allow transition into transient mode if new encoder assignments are valid.
+ */
+void link_enc_cfg_set_transient_mode(struct dc *dc, struct dc_state *current_state, struct dc_state *new_state);
+
 #endif /* DC_INC_LINK_ENC_CFG_H_ */
-- 
GitLab


From d445dd7b39c56a66872386a3ce0c8a862e59be46 Mon Sep 17 00:00:00 2001
From: "Lei, Jun" <Jun.Lei@amd.com>
Date: Thu, 26 May 2022 16:58:25 -0400
Subject: [PATCH 0300/1731] drm/amd/display: Extend soc BB capabilitiy

[why]
Some parts are consuming dangerously close to maximum number of states
supported when updating the BB (i.e. 8).

[how]
Change maximum stages from 9 to 20.

Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Jun Lei <jun.lei@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h              | 1 +
 drivers/gpu/drm/amd/display/dc/dml/dc_features.h | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index a1c965a84eba1..7f80cec01b2ed 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -747,6 +747,7 @@ struct dc_debug_options {
 	union aux_wake_wa_options aux_wake_wa;
 	uint8_t psr_power_use_phy_fsm;
 	enum dml_hostvm_override_opts dml_hostvm_override;
+	bool use_legacy_soc_bb_mechanism;
 };
 
 struct gpu_info_soc_bounding_box_v1_0;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dc_features.h b/drivers/gpu/drm/amd/display/dc/dml/dc_features.h
index 2a1983324629d..74e86732e3010 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dc_features.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dc_features.h
@@ -29,7 +29,7 @@
 #define DC__PRESENT 1
 #define DC__PRESENT__1 1
 #define DC__NUM_DPP 4
-#define DC__VOLTAGE_STATES 9
+#define DC__VOLTAGE_STATES 20
 #define DC__NUM_DPP__4 1
 #define DC__NUM_DPP__0_PRESENT 1
 #define DC__NUM_DPP__1_PRESENT 1
-- 
GitLab


From 9d001360b47b792a475250bf7ef2bcfbd17ba09f Mon Sep 17 00:00:00 2001
From: Chris Park <chris.park@amd.com>
Date: Wed, 25 May 2022 23:22:11 -0400
Subject: [PATCH 0301/1731] drm/amd/display: Add HDMI member to DTO

[Why]
For Pixel Rate control, when on HDMI, HDMI DTO
should be selected instead of DP DTO.

[How]
Add HDMI member to dtbclk_dto_params, so it can be used tell apart HDMI
and DP DTO in the future.

Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Chris Park <chris.park@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index 025169457cc86..c2d116cce119b 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -80,6 +80,7 @@ struct dtbclk_dto_params {
 	int req_audio_dtbclk_khz;
 	int num_odm_segments;
 	int ref_dtbclk_khz;
+	bool is_hdmi;
 };
 
 struct dccg_funcs {
-- 
GitLab


From 44961f6ebce9a7dccb2ec3dca312c5dbf85920e5 Mon Sep 17 00:00:00 2001
From: Aric Cyr <aric.cyr@amd.com>
Date: Sun, 29 May 2022 22:58:52 -0400
Subject: [PATCH 0302/1731] drm/amd/display: 3.2.189

This version brings along the following:
- DPP DTO fix
- Transient encoder fix
- Restrict the reading of LTTPR capabilities in LTTPR mode
- Increase maximum stages for BB
- Distinguish HDMI DTO from DP DTO

Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 7f80cec01b2ed..76db013aac6e0 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -47,7 +47,7 @@ struct aux_payload;
 struct set_config_cmd_payload;
 struct dmub_notification;
 
-#define DC_VER "3.2.188"
+#define DC_VER "3.2.189"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
GitLab


From 6bad4ff84cb57f548d42a41091159b750eed9ef9 Mon Sep 17 00:00:00 2001
From: David Zhang <dingchen.zhang@amd.com>
Date: Tue, 3 May 2022 17:53:44 -0400
Subject: [PATCH 0303/1731] drm/amd/display: expose AMD specific DPCD for
 PSR-SU-RC support

[why & how]

Expose vendor specific DPCD registers for rate controlling the eDP sink
TCON's refresh rate during PSR active. When used in combination with
PSR-SU and Freesync, it is called PSR-SU Rate Contorol, or PSR-SU-RC for
short.

v2: Add all DPCD registers required

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/include/ddc_service_types.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
index 20a3d4e23f661..05096c644a60b 100644
--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
@@ -41,6 +41,10 @@
 #define DP_DEVICE_ID_38EC11 0x38EC11
 #define DP_FORCE_PSRSU_CAPABILITY 0x40F
 
+#define DP_SINK_PSR_ACTIVE_VTOTAL		0x373
+#define DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE	0x375
+#define DP_SOURCE_PSR_ACTIVE_VTOTAL		0x376
+
 enum ddc_result {
 	DDC_RESULT_UNKNOWN = 0,
 	DDC_RESULT_SUCESSFULL,
-- 
GitLab


From 6651875ad7796ed3cd84b3bafb3885d05bb543ff Mon Sep 17 00:00:00 2001
From: David Zhang <dingchen.zhang@amd.com>
Date: Tue, 3 May 2022 18:12:05 -0400
Subject: [PATCH 0304/1731] drm/amd/display: Add PSR-SU-RC support in DC

[Why]

PSR-SU Rate Control - or PSR-SU-RC - enables PSR-SU panels to work with
variable refresh rate to allow for more power savings. Lowering the
refresh rate can increase PSR residency by expanding the eDP main link
shut down duration. It can also lower panel power consumption.

There is a complication with PSR, since the eDP main link can be shut
down. Therefore, the timing controller (TCON) on the eDP sink nees to be
able to scan out its remote buffer independent of the main link. To
allow the eDP source to specify the sink's refresh rate while the link
is off, vendor-specific DPCD registers are used. This allows the eDP
source to then "Rate Control" the panel during PSR active.

[How]

Add DC support to communicate with PSR-SU-RC supported eDP sinks. The
sink will need to know the desired VTotal during PSR active.

This change only adds support to DC, support in amdgpu_dm is still
pending to enable this fully.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 22 ++++++++++++++++++
 drivers/gpu/drm/amd/display/dc/dc_link.h      |  3 +++
 drivers/gpu/drm/amd/display/dc/dc_types.h     |  2 ++
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 23 +++++++++++++++++++
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |  2 ++
 .../drm/amd/display/dc/inc/hw/link_encoder.h  |  8 +++++++
 6 files changed, 60 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index ab9655d6e5c8a..7884530cc02be 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1795,6 +1795,7 @@ static bool dc_link_construct_legacy(struct dc_link *link,
 	 */
 	program_hpd_filter(link);
 
+	link->psr_settings.psr_vtotal_control_support = false;
 	link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
 
 	DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
@@ -3227,6 +3228,7 @@ bool dc_link_setup_psr(struct dc_link *link,
 	/* updateSinkPsrDpcdConfig*/
 	union dpcd_psr_configuration psr_configuration;
 	union dpcd_alpm_configuration alpm_configuration;
+	union dpcd_sink_active_vtotal_control_mode vtotal_control = {0};
 
 	psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
 
@@ -3296,6 +3298,13 @@ bool dc_link_setup_psr(struct dc_link *link,
 			psr_config->su_y_granularity;
 		psr_context->line_time_in_us =
 			psr_config->line_time_in_us;
+
+		if (link->psr_settings.psr_vtotal_control_support) {
+			psr_context->rate_control_caps = psr_config->rate_control_caps;
+			vtotal_control.bits.ENABLE = true;
+			core_link_write_dpcd(link, DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE,
+							&vtotal_control.raw, sizeof(vtotal_control.raw));
+		}
 	}
 
 	psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
@@ -3428,6 +3437,19 @@ void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
 		*residency = 0;
 }
 
+bool dc_link_set_sink_vtotal_in_psr_active(const struct dc_link *link, uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
+{
+	struct dc *dc = link->ctx->dc;
+	struct dmub_psr *psr = dc->res_pool->psr;
+
+	if (psr == NULL || !link->psr_settings.psr_feature_enabled || !link->psr_settings.psr_vtotal_control_support)
+		return false;
+
+	psr->funcs->psr_set_sink_vtotal_in_psr_active(psr, psr_vtotal_idle, psr_vtotal_su);
+
+	return true;
+}
+
 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
 {
 	return &link->link_status;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index c4a42d758b4e8..29c0040a6dd49 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -100,6 +100,7 @@ struct psr_settings {
 	bool psr_feature_enabled;		// PSR is supported by sink
 	bool psr_allow_active;			// PSR is currently active
 	enum dc_psr_version psr_version;		// Internal PSR version, determined based on DPCD
+	bool psr_vtotal_control_support;	// Vtotal control is supported by sink
 
 	/* These parameters are calculated in Driver,
 	 * based on display timing and Sink capabilities.
@@ -325,6 +326,8 @@ void dc_link_blank_all_dp_displays(struct dc *dc);
 void dc_link_blank_all_edp_displays(struct dc *dc);
 
 void dc_link_blank_dp_stream(struct dc_link *link, bool hw_init);
+bool dc_link_set_sink_vtotal_in_psr_active(const struct dc_link *link,
+		uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su);
 
 /* Request DC to detect if there is a Panel connected.
  * boot - If this call is during initial boot.
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 26b62f50ac4e9..fa735d5f730f9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -684,6 +684,7 @@ struct psr_config {
 	/* psr2 selective update y granularity capability */
 	uint8_t su_y_granularity;
 	unsigned int line_time_in_us;
+	uint8_t rate_control_caps;
 };
 
 union dmcu_psr_level {
@@ -794,6 +795,7 @@ struct psr_context {
 	/* psr2 selective update y granularity capability */
 	uint8_t su_y_granularity;
 	unsigned int line_time_in_us;
+	uint8_t rate_control_caps;
 };
 
 struct colorspace_transform {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 9ca0cbb0af9b2..0df06740ec391 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -250,6 +250,27 @@ static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_
 	dc_dmub_srv_wait_idle(dc->dmub_srv);
 }
 
+/**
+ * Set PSR vtotal requirement for FreeSync PSR.
+ */
+static void dmub_psr_set_sink_vtotal_in_psr_active(struct dmub_psr *dmub,
+		uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
+{
+	union dmub_rb_cmd cmd;
+	struct dc_context *dc = dmub->ctx;
+
+	memset(&cmd, 0, sizeof(cmd));
+	cmd.psr_set_vtotal.header.type = DMUB_CMD__PSR;
+	cmd.psr_set_vtotal.header.sub_type = DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE;
+	cmd.psr_set_vtotal.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_vtotal_data);
+	cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_idle = psr_vtotal_idle;
+	cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_su = psr_vtotal_su;
+
+	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
+	dc_dmub_srv_cmd_execute(dc->dmub_srv);
+	dc_dmub_srv_wait_idle(dc->dmub_srv);
+}
+
 /*
  * Set PSR power optimization flags.
  */
@@ -358,6 +379,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 
 	copy_settings_data->line_capture_indication = 0;
 	copy_settings_data->line_time_in_us = psr_context->line_time_in_us;
+	copy_settings_data->rate_control_caps = psr_context->rate_control_caps;
 	copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
 	copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
 	copy_settings_data->cmd_version =  DMUB_CMD_PSR_CONTROL_VERSION_1;
@@ -435,6 +457,7 @@ static const struct dmub_psr_funcs psr_funcs = {
 	.psr_set_level			= dmub_psr_set_level,
 	.psr_force_static		= dmub_psr_force_static,
 	.psr_get_residency		= dmub_psr_get_residency,
+	.psr_set_sink_vtotal_in_psr_active	= dmub_psr_set_sink_vtotal_in_psr_active,
 	.psr_set_power_opt		= dmub_psr_set_power_opt,
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
index 01acc01cc1911..74005b9d352a2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
@@ -46,6 +46,8 @@ struct dmub_psr_funcs {
 	void (*psr_force_static)(struct dmub_psr *dmub, uint8_t panel_inst);
 	void (*psr_get_residency)(struct dmub_psr *dmub, uint32_t *residency,
 	uint8_t panel_inst);
+	void (*psr_set_sink_vtotal_in_psr_active)(struct dmub_psr *dmub,
+	uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su);
 	void (*psr_set_power_opt)(struct dmub_psr *dmub, unsigned int power_opt, uint8_t panel_inst);
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 6e6bd007babc1..ec572a9e40547 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -101,6 +101,14 @@ union dpcd_alpm_configuration {
 	unsigned char raw;
 };
 
+union dpcd_sink_active_vtotal_control_mode {
+	struct {
+		unsigned char ENABLE                    : 1;
+		unsigned char RESERVED                  : 7;
+	} bits;
+	unsigned char raw;
+};
+
 union psr_error_status {
 	struct {
 		unsigned char LINK_CRC_ERROR        :1;
-- 
GitLab


From f9f4daf15398c3aa0aa2dcd05ed4ea2544bcc62c Mon Sep 17 00:00:00 2001
From: David Zhang <dingchen.zhang@amd.com>
Date: Wed, 11 May 2022 13:29:54 -0400
Subject: [PATCH 0305/1731] drm/amd/display: pass panel instance in DMUB dirty
 rect command

[Why]

In cases where there are multiple eDP instances, DMUB needs to know
which instance the command is for. Today, the field for specifying the
panel_inst exists in both dmub_cmd_update_dirty_rect_data and
dmub_cmd_update_cursor_info_data.

For cursor updates, we already specify the panel_inst, but that's not
the case for dirty_rect updates. Today, a value of '0' is used (due
to initial memsetting of the cmd struct to 0)

[how]

In dc_dmub_update_dirty_rect(), Call dc_get_edp_link_panel_inst() to get
the panel_inst, and fill it in the DMUB cmd struct.

v2: Update commit message for clarity.

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d4173be119031..31d83297bcb56 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2837,10 +2837,14 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
 	struct dc_context *dc_ctx = dc->ctx;
 	struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
 	unsigned int i, j;
+	unsigned int panel_inst = 0;
 
 	if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1)
 		return;
 
+	if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
+		return;
+
 	memset(&cmd, 0x0, sizeof(cmd));
 	cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
 	cmd.update_dirty_rect.header.sub_type = 0;
@@ -2869,6 +2873,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
 			if (pipe_ctx->plane_state != plane_state)
 				continue;
 
+			update_dirty_rect->panel_inst = panel_inst;
 			update_dirty_rect->pipe_idx = j;
 			dc_dmub_srv_cmd_queue(dc_ctx->dmub_srv, &cmd);
 			dc_dmub_srv_cmd_execute(dc_ctx->dmub_srv);
-- 
GitLab


From 2ff6a14b20298db0763772b62cd4fb030e6d7f75 Mon Sep 17 00:00:00 2001
From: Robin Chen <po-tchen@amd.com>
Date: Fri, 22 Apr 2022 17:25:38 +0800
Subject: [PATCH 0306/1731] drm/amd/display: refactor dirty rect dmub command
 decision

[Why]
To wrap the decision logic of sending dirty rect dmub command
for both frame update and cursor update path.

Signed-off-by: Robin Chen <po-tchen@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c      | 14 ++++++++++-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 24 ++++++++++++++-----
 2 files changed, 31 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 31d83297bcb56..645ec5bc3a7d7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2827,6 +2827,18 @@ static void commit_planes_do_stream_update(struct dc *dc,
 	}
 }
 
+static bool dc_dmub_should_send_dirty_rect_cmd(struct dc *dc, struct dc_stream_state *stream)
+{
+	if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
+		return true;
+
+	if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_1 &&
+	    dc->debug.enable_sw_cntl_psr)
+		return true;
+
+	return false;
+}
+
 void dc_dmub_update_dirty_rect(struct dc *dc,
 			       int surface_count,
 			       struct dc_stream_state *stream,
@@ -2839,7 +2851,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
 	unsigned int i, j;
 	unsigned int panel_inst = 0;
 
-	if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1)
+	if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))
 		return;
 
 	if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 351a923fbf735..573d5be9e302d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -3330,6 +3330,23 @@ static bool dcn10_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
 	return false;
 }
 
+static bool dcn10_dmub_should_update_cursor_data(
+		struct pipe_ctx *pipe_ctx,
+		struct dc_debug_options *debug)
+{
+	if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
+		return false;
+
+	if (pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
+		return true;
+
+	if (pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1 &&
+	    debug->enable_sw_cntl_psr)
+		return true;
+
+	return false;
+}
+
 static void dcn10_dmub_update_cursor_data(
 		struct pipe_ctx *pipe_ctx,
 		struct hubp *hubp,
@@ -3351,13 +3368,8 @@ static void dcn10_dmub_update_cursor_data(
 
 	struct dc_debug_options *debug = &hubp->ctx->dc->debug;
 
-	if (!debug->enable_sw_cntl_psr && pipe_ctx->stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1)
+	if (!dcn10_dmub_should_update_cursor_data(pipe_ctx, debug))
 		return;
-
-	if (pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED ||
-		pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
-		return;
-
 	/**
 	 * if cur_pos == NULL means the caller is from cursor_set_attribute
 	 * then driver use previous cursor position data
-- 
GitLab


From ce0db505bc0c51ef5e9ba446c660de7e26f78f29 Mon Sep 17 00:00:00 2001
From: Maximilian Luz <luzmaximilian@gmail.com>
Date: Mon, 6 Jun 2022 23:13:05 +0200
Subject: [PATCH 0307/1731] drm/msm: Fix double pm_runtime_disable() call

Following commit 17e822f7591f ("drm/msm: fix unbalanced
pm_runtime_enable in adreno_gpu_{init, cleanup}"), any call to
adreno_unbind() will disable runtime PM twice, as indicated by the call
trees below:

  adreno_unbind()
   -> pm_runtime_force_suspend()
   -> pm_runtime_disable()

  adreno_unbind()
   -> gpu->funcs->destroy() [= aNxx_destroy()]
   -> adreno_gpu_cleanup()
   -> pm_runtime_disable()

Note that pm_runtime_force_suspend() is called right before
gpu->funcs->destroy() and both functions are called unconditionally.

With recent addition of the eDP AUX bus code, this problem manifests
itself when the eDP panel cannot be found yet and probing is deferred.
On the first probe attempt, we disable runtime PM twice as described
above. This then causes any later probe attempt to fail with

  [drm:adreno_load_gpu [msm]] *ERROR* Couldn't power up the GPU: -13

preventing the driver from loading.

As there seem to be scenarios where the aNxx_destroy() functions are not
called from adreno_unbind(), simply removing pm_runtime_disable() from
inside adreno_unbind() does not seem to be the proper fix. This is what
commit 17e822f7591f ("drm/msm: fix unbalanced pm_runtime_enable in
adreno_gpu_{init, cleanup}") intended to fix. Therefore, instead check
whether runtime PM is still enabled, and only disable it in that case.

Fixes: 17e822f7591f ("drm/msm: fix unbalanced pm_runtime_enable in adreno_gpu_{init, cleanup}")
Signed-off-by: Maximilian Luz <luzmaximilian@gmail.com>
Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Link: https://lore.kernel.org/r/20220606211305.189585-1-luzmaximilian@gmail.com
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 4e665c806a14e..f944b69e2a258 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -1057,7 +1057,8 @@ void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
 	for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++)
 		release_firmware(adreno_gpu->fw[i]);
 
-	pm_runtime_disable(&priv->gpu_pdev->dev);
+	if (pm_runtime_enabled(&priv->gpu_pdev->dev))
+		pm_runtime_disable(&priv->gpu_pdev->dev);
 
 	msm_gpu_cleanup(&adreno_gpu->base);
 }
-- 
GitLab


From c6e3806705d679edf135dff5d540a278fc406f15 Mon Sep 17 00:00:00 2001
From: Anshuman Gupta <anshuman.gupta@intel.com>
Date: Tue, 7 Jun 2022 16:15:42 +0530
Subject: [PATCH 0308/1731] drm/i915/dg2: Add Wa_14015795083

i915 must disable Render DOP clock gating globally.

v2:
- Addressed cosmetic review comments.

Bspec: 52621
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Badal Nilawar <badal.nilawar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220607104542.8559-1-anshuman.gupta@intel.com
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 6aa1ceaa8d271..c8129a3517316 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -631,6 +631,7 @@
 
 #define GEN7_MISCCPCTL				_MMIO(0x9424)
 #define   GEN7_DOP_CLOCK_GATE_ENABLE		(1 << 0)
+#define   GEN12_DOP_CLOCK_GATE_RENDER_ENABLE	REG_BIT(1)
 #define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE	(1 << 2)
 #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE	(1 << 4)
 #define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE	(1 << 6)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 6e875d4f5f651..1e7ca3863f207 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1486,6 +1486,9 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 	 * performance guide section.
 	 */
 	wa_write_or(wal, GEN12_SQCM, EN_32B_ACCESS);
+
+	/* Wa_14015795083 */
+	wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
 }
 
 static void
-- 
GitLab


From 81298056a78c5163b216f17d17c43736e7069961 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Tue, 7 Jun 2022 08:47:24 -0700
Subject: [PATCH 0309/1731] drm/i915/dg2: Correct DSS check for Wa_1308578152

When converting our DSS masks to bitmaps, we fumbled the condition used
to check whether any DSS are present in the first gslice.  Since
intel_sseu_find_first_xehp_dss() returns a 0-based number, we need a >=
condition rather than >.

Fixes: b87d39019651 ("drm/i915/sseu: Disassociate internal subslice mask representation from uapi")
Reported-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220607154724.3155521-1-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 1e7ca3863f207..0ac7f5daacc42 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2062,7 +2062,7 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 
 static bool needs_wa_1308578152(struct intel_engine_cs *engine)
 {
-	return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
+	return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >=
 		GEN_DSS_PER_GSLICE;
 }
 
-- 
GitLab


From 46d6e11320d21dc40fce229ab3504125847de27e Mon Sep 17 00:00:00 2001
From: Nicolas Saenz Julienne <nsaenz@kernel.org>
Date: Fri, 3 Jun 2022 09:30:12 +0200
Subject: [PATCH 0310/1731] MAINTAINERS: Update BCM2711/BCM2835 maintainer

I haven't been able to find time to maintain BCM2711/BCM2835 these last
months, so it's only fair to pass the baton to Florian who's been doing
the work.

Signed-off-by: Nicolas Saenz Julienne <nsaenz@kernel.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 MAINTAINERS | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index a6d3bd9d2a8d0..320a2ac788dc4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3789,12 +3789,12 @@ N:	bcmbca
 N:	bcm[9]?47622
 
 BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE
-M:	Nicolas Saenz Julienne <nsaenz@kernel.org>
+M:	Florian Fainelli <f.fainelli@gmail.com>
 R:	Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
 L:	linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers)
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
-T:	git git://git.kernel.org/pub/scm/linux/kernel/git/nsaenz/linux-rpi.git
+T:	git git://github.com/broadcom/stblinux.git
 F:	Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
 F:	drivers/pci/controller/pcie-brcmstb.c
 F:	drivers/staging/vc04_services
-- 
GitLab


From ab9db127ee03487785509f960e7b5b91cdb6b92d Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Fri, 6 May 2022 15:04:05 +0300
Subject: [PATCH 0311/1731] drm/i915/pxp: fix sparse warning for not declared
 symbol

Fix:

drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c:61:6: warning: symbol
'intel_pxp_debugfs_register' was not declared. Should it be static?

Sort and remove the redundant pxp prefixes from the includes while at
it.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220506120405.2582372-1-jani.nikula@intel.com
---
 drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c
index c9da1015eb426..e888b5124a07a 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c
@@ -9,9 +9,10 @@
 #include <drm/drm_print.h>
 
 #include "gt/intel_gt_debugfs.h"
-#include "pxp/intel_pxp.h"
-#include "pxp/intel_pxp_irq.h"
 #include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_debugfs.h"
+#include "intel_pxp_irq.h"
 
 static int pxp_info_show(struct seq_file *m, void *data)
 {
-- 
GitLab


From eb20cf30c57c37ed05f44966dfabc2c34bf46cab Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Mon, 16 May 2022 11:10:15 +0300
Subject: [PATCH 0312/1731] drm/i915/overlay: remove redundant GEM_BUG_ON()

There's an early return for !engine->kernel_context.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220516081015.1058987-1-jani.nikula@intel.com
---
 drivers/gpu/drm/i915/display/intel_overlay.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index ee46561b5ae84..79ed8bd04a072 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -1399,8 +1399,6 @@ void intel_overlay_setup(struct drm_i915_private *dev_priv)
 
 	overlay->i915 = dev_priv;
 	overlay->context = engine->kernel_context;
-	GEM_BUG_ON(!overlay->context);
-
 	overlay->color_key = 0x0101fe;
 	overlay->color_key_enabled = true;
 	overlay->brightness = -19;
-- 
GitLab


From 5821a0bbb4c39960975d29d6b58ae290088db0ed Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Wed, 11 May 2022 12:46:19 +0300
Subject: [PATCH 0313/1731] drm/i915/uc: remove accidental static from a local
 variable

The arrays are static const, but the pointer shouldn't be static.

Fixes: 3d832f370d16 ("drm/i915/uc: Allow platforms to have GuC but not HuC")
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220511094619.27889-1-jani.nikula@intel.com
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 9361532726d6c..d2c5c9367cc4f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -156,7 +156,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct intel_uc_fw *uc_fw)
 		[INTEL_UC_FW_TYPE_GUC] = { blobs_guc, ARRAY_SIZE(blobs_guc) },
 		[INTEL_UC_FW_TYPE_HUC] = { blobs_huc, ARRAY_SIZE(blobs_huc) },
 	};
-	static const struct uc_fw_platform_requirement *fw_blobs;
+	const struct uc_fw_platform_requirement *fw_blobs;
 	enum intel_platform p = INTEL_INFO(i915)->platform;
 	u32 fw_count;
 	u8 rev = INTEL_REVID(i915);
-- 
GitLab


From 98432ccdec9f178ba041e1e5f9f32dbd71576504 Mon Sep 17 00:00:00 2001
From: Marc Zyngier <maz@kernel.org>
Date: Tue, 7 Jun 2022 14:14:26 +0100
Subject: [PATCH 0314/1731] KVM: arm64: Replace vgic_v3_uaccess_read_pending
 with vgic_uaccess_read_pending

Now that GICv2 has a proper userspace accessor for the pending state,
switch GICv3 over to it, dropping the local version, moving over the
specific behaviours that CGIv3 requires (such as the distinction
between pending latch and line level which were never enforced
with GICv2).

We also gain extra locking that isn't really necessary for userspace,
but that's a small price to pay for getting rid of superfluous code.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Link: https://lore.kernel.org/r/20220607131427.1164881-3-maz@kernel.org
---
 arch/arm64/kvm/vgic/vgic-mmio-v3.c | 40 ++----------------------------
 arch/arm64/kvm/vgic/vgic-mmio.c    | 21 +++++++++++++++-
 2 files changed, 22 insertions(+), 39 deletions(-)

diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-mmio-v3.c
index f7aa7bcd6fb8c..f15e29cc63ce1 100644
--- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c
+++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c
@@ -353,42 +353,6 @@ static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
 	return 0;
 }
 
-static unsigned long vgic_v3_uaccess_read_pending(struct kvm_vcpu *vcpu,
-						  gpa_t addr, unsigned int len)
-{
-	u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
-	u32 value = 0;
-	int i;
-
-	/*
-	 * pending state of interrupt is latched in pending_latch variable.
-	 * Userspace will save and restore pending state and line_level
-	 * separately.
-	 * Refer to Documentation/virt/kvm/devices/arm-vgic-v3.rst
-	 * for handling of ISPENDR and ICPENDR.
-	 */
-	for (i = 0; i < len * 8; i++) {
-		struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
-		bool state = irq->pending_latch;
-
-		if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
-			int err;
-
-			err = irq_get_irqchip_state(irq->host_irq,
-						    IRQCHIP_STATE_PENDING,
-						    &state);
-			WARN_ON(err);
-		}
-
-		if (state)
-			value |= (1U << i);
-
-		vgic_put_irq(vcpu->kvm, irq);
-	}
-
-	return value;
-}
-
 static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu,
 					 gpa_t addr, unsigned int len,
 					 unsigned long val)
@@ -666,7 +630,7 @@ static const struct vgic_register_region vgic_v3_dist_registers[] = {
 		VGIC_ACCESS_32bit),
 	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
 		vgic_mmio_read_pending, vgic_mmio_write_spending,
-		vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1,
+		vgic_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1,
 		VGIC_ACCESS_32bit),
 	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
 		vgic_mmio_read_pending, vgic_mmio_write_cpending,
@@ -750,7 +714,7 @@ static const struct vgic_register_region vgic_v3_rd_registers[] = {
 		VGIC_ACCESS_32bit),
 	REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISPENDR0,
 		vgic_mmio_read_pending, vgic_mmio_write_spending,
-		vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4,
+		vgic_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4,
 		VGIC_ACCESS_32bit),
 	REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICPENDR0,
 		vgic_mmio_read_pending, vgic_mmio_write_cpending,
diff --git a/arch/arm64/kvm/vgic/vgic-mmio.c b/arch/arm64/kvm/vgic/vgic-mmio.c
index dc8c52487e470..997d0fce20883 100644
--- a/arch/arm64/kvm/vgic/vgic-mmio.c
+++ b/arch/arm64/kvm/vgic/vgic-mmio.c
@@ -240,6 +240,15 @@ static unsigned long __read_pending(struct kvm_vcpu *vcpu,
 		unsigned long flags;
 		bool val;
 
+		/*
+		 * When used from userspace with a GICv3 model:
+		 *
+		 * Pending state of interrupt is latched in pending_latch
+		 * variable.  Userspace will save and restore pending state
+		 * and line_level separately.
+		 * Refer to Documentation/virt/kvm/devices/arm-vgic-v3.rst
+		 * for handling of ISPENDR and ICPENDR.
+		 */
 		raw_spin_lock_irqsave(&irq->irq_lock, flags);
 		if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
 			int err;
@@ -252,7 +261,17 @@ static unsigned long __read_pending(struct kvm_vcpu *vcpu,
 		} else if (!is_user && vgic_irq_is_mapped_level(irq)) {
 			val = vgic_get_phys_line_level(irq);
 		} else {
-			val = irq_is_pending(irq);
+			switch (vcpu->kvm->arch.vgic.vgic_model) {
+			case KVM_DEV_TYPE_ARM_VGIC_V3:
+				if (is_user) {
+					val = irq->pending_latch;
+					break;
+				}
+				fallthrough;
+			default:
+				val = irq_is_pending(irq);
+				break;
+			}
 		}
 
 		value |= ((u32)val << i);
-- 
GitLab


From efedd01de475e126e43a07d0b1221bb65e497163 Mon Sep 17 00:00:00 2001
From: Marc Zyngier <maz@kernel.org>
Date: Tue, 7 Jun 2022 14:14:27 +0100
Subject: [PATCH 0315/1731] KVM: arm64: Warn if accessing timer pending state
 outside of vcpu context

A recurrent bug in the KVM/arm64 code base consists in trying to
access the timer pending state outside of the vcpu context, which
makes zero sense (the pending state only exists when the vcpu
is loaded).

In order to avoid more embarassing crashes and catch the offenders
red-handed, add a warning to kvm_arch_timer_get_input_level() and
return the state as non-pending. This avoids taking the system down,
and still helps tracking down silly bugs.

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220607131427.1164881-4-maz@kernel.org
---
 arch/arm64/kvm/arch_timer.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c
index 4e39ace073af0..3b8d062e30ea4 100644
--- a/arch/arm64/kvm/arch_timer.c
+++ b/arch/arm64/kvm/arch_timer.c
@@ -1230,6 +1230,9 @@ bool kvm_arch_timer_get_input_level(int vintid)
 	struct kvm_vcpu *vcpu = kvm_get_running_vcpu();
 	struct arch_timer_context *timer;
 
+	if (WARN(!vcpu, "No vcpu context!\n"))
+		return false;
+
 	if (vintid == vcpu_vtimer(vcpu)->irq.irq)
 		timer = vcpu_vtimer(vcpu);
 	else if (vintid == vcpu_ptimer(vcpu)->irq.irq)
-- 
GitLab


From 37d838de369b07b596c19ff3662bf0293fdb09ee Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Thu, 26 May 2022 11:53:22 +0400
Subject: [PATCH 0316/1731] soc: bcm: brcmstb: pm: pm-arm: Fix refcount leak in
 brcmstb_pm_probe

of_find_matching_node() returns a node pointer with refcount
incremented, we should use of_node_put() on it when not need anymore.
Add missing of_node_put() to avoid refcount leak.

In brcmstb_init_sram, it pass dn to of_address_to_resource(),
of_address_to_resource() will call of_find_device_by_node() to take
reference, so we should release the reference returned by
of_find_matching_node().

Fixes: 0b741b8234c8 ("soc: bcm: brcmstb: Add support for S2/S3/S5 suspend states (ARM)")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 drivers/soc/bcm/brcmstb/pm/pm-arm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/soc/bcm/brcmstb/pm/pm-arm.c b/drivers/soc/bcm/brcmstb/pm/pm-arm.c
index 3cbb165d6e309..70ad0f3dce283 100644
--- a/drivers/soc/bcm/brcmstb/pm/pm-arm.c
+++ b/drivers/soc/bcm/brcmstb/pm/pm-arm.c
@@ -783,6 +783,7 @@ static int brcmstb_pm_probe(struct platform_device *pdev)
 	}
 
 	ret = brcmstb_init_sram(dn);
+	of_node_put(dn);
 	if (ret) {
 		pr_err("error setting up SRAM for PM\n");
 		return ret;
-- 
GitLab


From f09d2b0bdd78ffd38227426fb2ceab7ebd141391 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Fri, 3 Jun 2022 19:58:41 +0300
Subject: [PATCH 0317/1731] drm/i915: Initialize eDP source rates after
 per-panel VBT parsing
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

We'll need to know the VBT panel_type before we can determine the
maximum link rate for eDP. To that end move
intel_dp_set_source_rates() & co. to be called after the per-panel
VBT parsing has been done.

intel_dp_mst_encoder_init() depends on the source rates so we'll
have to do it a bit later as well.

v2: Fix the intel_dp_mst_encoder_init() oops

Reviewed-by: Jani Nikula <jani.nikula@intel.com> #v1
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220603165841.15481-1-ville.syrjala@linux.intel.com
---
 drivers/gpu/drm/i915/display/intel_dp.c | 19 ++++++++-----------
 1 file changed, 8 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3d630f98b1f14..3d791c10003c0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2846,9 +2846,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
 		intel_dp_set_sink_rates(intel_dp);
 	intel_dp_set_max_sink_lane_count(intel_dp);
 
-	intel_dp_set_common_rates(intel_dp);
-	intel_dp_reset_max_link_params(intel_dp);
-
 	/* Read the eDP DSC DPCD registers */
 	if (DISPLAY_VER(dev_priv) >= 10)
 		intel_dp_get_dsc_sink_cap(intel_dp);
@@ -5336,11 +5333,8 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
 		type = DRM_MODE_CONNECTOR_DisplayPort;
 	}
 
-	intel_dp_set_source_rates(intel_dp);
 	intel_dp_set_default_sink_rates(intel_dp);
 	intel_dp_set_default_max_sink_lane_count(intel_dp);
-	intel_dp_set_common_rates(intel_dp);
-	intel_dp_reset_max_link_params(intel_dp);
 
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
@@ -5368,16 +5362,19 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
 	else
 		intel_connector->get_hw_state = intel_connector_get_hw_state;
 
-	/* init MST on ports that can support it */
-	intel_dp_mst_encoder_init(dig_port,
-				  intel_connector->base.base.id);
-
 	if (!intel_edp_init_connector(intel_dp, intel_connector)) {
 		intel_dp_aux_fini(intel_dp);
-		intel_dp_mst_encoder_cleanup(dig_port);
 		goto fail;
 	}
 
+	intel_dp_set_source_rates(intel_dp);
+	intel_dp_set_common_rates(intel_dp);
+	intel_dp_reset_max_link_params(intel_dp);
+
+	/* init MST on ports that can support it */
+	intel_dp_mst_encoder_init(dig_port,
+				  intel_connector->base.base.id);
+
 	intel_dp_add_properties(intel_dp, connector);
 
 	if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
-- 
GitLab


From f06d1d66d54c223e4f0f73393d94afd88105b6f3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Thu, 2 Jun 2022 23:56:49 +0300
Subject: [PATCH 0318/1731] drm/i915: Update eDP fast link training link rate
 parsing
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

We're not parsing the 5.4 Gbps value for the old eDP fast link
training link rate, nor are we parsing the new fast link training
link rate field. Remedy both.

Also we'll now use the actual link rate instead of the DPCD BW
register value.

Note that we're not even using this information for anything
currently, so should perhaps just nuke it all unless someone
is planning on implementing fast link training finally...

v2: Stop using the DPCD BW values (Jani)
    *20 instead of *2 to get the rate in correct units (Jani)

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220602205649.11283-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 32 ++++++++++++-------
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |  1 +
 2 files changed, 21 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 0f95ca6521159..ccd39daacdbf5 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1366,18 +1366,26 @@ parse_edp(struct drm_i915_private *i915,
 
 	panel->vbt.edp.pps = *edp_pps;
 
-	switch (edp_link_params->rate) {
-	case EDP_RATE_1_62:
-		panel->vbt.edp.rate = DP_LINK_BW_1_62;
-		break;
-	case EDP_RATE_2_7:
-		panel->vbt.edp.rate = DP_LINK_BW_2_7;
-		break;
-	default:
-		drm_dbg_kms(&i915->drm,
-			    "VBT has unknown eDP link rate value %u\n",
-			     edp_link_params->rate);
-		break;
+	if (i915->vbt.version >= 224) {
+		panel->vbt.edp.rate =
+			edp->edp_fast_link_training_rate[panel_type] * 20;
+	} else {
+		switch (edp_link_params->rate) {
+		case EDP_RATE_1_62:
+			panel->vbt.edp.rate = 162000;
+			break;
+		case EDP_RATE_2_7:
+			panel->vbt.edp.rate = 270000;
+			break;
+		case EDP_RATE_5_4:
+			panel->vbt.edp.rate = 540000;
+			break;
+		default:
+			drm_dbg_kms(&i915->drm,
+				    "VBT has unknown eDP link rate value %u\n",
+				    edp_link_params->rate);
+			break;
+		}
 	}
 
 	switch (edp_link_params->lanes) {
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 14f1e1cc92c5f..58aee0a040cfb 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -638,6 +638,7 @@ struct bdb_sdvo_panel_dtds {
 #define EDP_30BPP	2
 #define EDP_RATE_1_62	0
 #define EDP_RATE_2_7	1
+#define EDP_RATE_5_4	2
 #define EDP_LANE_1	0
 #define EDP_LANE_2	1
 #define EDP_LANE_4	3
-- 
GitLab


From 24b8b74eb2eb578fee046c70681000f61afa5680 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Thu, 2 Jun 2022 23:57:23 +0300
Subject: [PATCH 0319/1731] drm/i915: Parse max link rate from the eDP BDB
 block
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The eDP BDB block has gained yet another max link rate field.
Let's parse it and consult it during the source rate filtering.

v2: *20 instead of *2 to get the correct units (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220602205723.11341-1-ville.syrjala@linux.intel.com
---
 drivers/gpu/drm/i915/display/intel_bios.c     |  4 ++++
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 23 +++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |  1 +
 4 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index ccd39daacdbf5..b165feb593ab1 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1460,6 +1460,10 @@ parse_edp(struct drm_i915_private *i915,
 
 	panel->vbt.edp.drrs_msa_timing_delay =
 		(edp->sdrrs_msa_timing_delay >> (panel_type * 2)) & 3;
+
+	if (i915->vbt.version >= 244)
+		panel->vbt.edp.max_link_rate =
+			edp->edp_max_port_link_rate[panel_type] * 20;
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 09a664c51a4a5..e4a6fc7390fcb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -300,6 +300,7 @@ struct intel_vbt_panel_data {
 	enum drrs_type drrs_type;
 
 	struct {
+		int max_link_rate;
 		int rate;
 		int lanes;
 		int preemphasis;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3d791c10003c0..368bd4cdf2eeb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -407,6 +407,26 @@ static int ehl_max_source_rate(struct intel_dp *intel_dp)
 	return 810000;
 }
 
+static int vbt_max_link_rate(struct intel_dp *intel_dp)
+{
+	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+	int max_rate;
+
+	max_rate = intel_bios_dp_max_link_rate(encoder);
+
+	if (intel_dp_is_edp(intel_dp)) {
+		struct intel_connector *connector = intel_dp->attached_connector;
+		int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
+
+		if (max_rate && edp_max_rate)
+			max_rate = min(max_rate, edp_max_rate);
+		else if (edp_max_rate)
+			max_rate = edp_max_rate;
+	}
+
+	return max_rate;
+}
+
 static void
 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 {
@@ -428,7 +448,6 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
 		162000, 270000
 	};
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-	struct intel_encoder *encoder = &dig_port->base;
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 	const int *source_rates;
 	int size, max_rate = 0, vbt_max_rate;
@@ -464,7 +483,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
 		size = ARRAY_SIZE(g4x_rates);
 	}
 
-	vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
+	vbt_max_rate = vbt_max_link_rate(intel_dp);
 	if (max_rate && vbt_max_rate)
 		max_rate = min(max_rate, vbt_max_rate);
 	else if (vbt_max_rate)
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 58aee0a040cfb..f8e5097222f2a 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -697,6 +697,7 @@ struct bdb_edp {
 	u16 apical_enable;					/* 203 */
 	struct edp_apical_params apical_params[16];		/* 203 */
 	u16 edp_fast_link_training_rate[16];			/* 224 */
+	u16 edp_max_port_link_rate[16];				/* 244 */
 } __packed;
 
 /*
-- 
GitLab


From b1fd94e704571f98b21027340eecf821b2bdffba Mon Sep 17 00:00:00 2001
From: Florian Westphal <fw@strlen.de>
Date: Wed, 18 May 2022 20:15:31 +0200
Subject: [PATCH 0320/1731] netfilter: use get_random_u32 instead of prandom

bh might occur while updating per-cpu rnd_state from user context,
ie. local_out path.

BUG: using smp_processor_id() in preemptible [00000000] code: nginx/2725
caller is nft_ng_random_eval+0x24/0x54 [nft_numgen]
Call Trace:
 check_preemption_disabled+0xde/0xe0
 nft_ng_random_eval+0x24/0x54 [nft_numgen]

Use the random driver instead, this also avoids need for local prandom
state. Moreover, prandom now uses the random driver since d4150779e60f
("random32: use real rng for non-deterministic randomness").

Based on earlier patch from Pablo Neira.

Fixes: 6b2faee0ca91 ("netfilter: nft_meta: place prandom handling in a helper")
Fixes: 978d8f9055c3 ("netfilter: nft_numgen: add map lookups for numgen random operations")
Signed-off-by: Florian Westphal <fw@strlen.de>
Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
---
 net/netfilter/nft_meta.c   | 13 ++-----------
 net/netfilter/nft_numgen.c | 12 +++---------
 2 files changed, 5 insertions(+), 20 deletions(-)

diff --git a/net/netfilter/nft_meta.c b/net/netfilter/nft_meta.c
index ac4859241e177..55d2d49c34259 100644
--- a/net/netfilter/nft_meta.c
+++ b/net/netfilter/nft_meta.c
@@ -14,6 +14,7 @@
 #include <linux/in.h>
 #include <linux/ip.h>
 #include <linux/ipv6.h>
+#include <linux/random.h>
 #include <linux/smp.h>
 #include <linux/static_key.h>
 #include <net/dst.h>
@@ -32,8 +33,6 @@
 #define NFT_META_SECS_PER_DAY		86400
 #define NFT_META_DAYS_PER_WEEK		7
 
-static DEFINE_PER_CPU(struct rnd_state, nft_prandom_state);
-
 static u8 nft_meta_weekday(void)
 {
 	time64_t secs = ktime_get_real_seconds();
@@ -271,13 +270,6 @@ static bool nft_meta_get_eval_ifname(enum nft_meta_keys key, u32 *dest,
 	return true;
 }
 
-static noinline u32 nft_prandom_u32(void)
-{
-	struct rnd_state *state = this_cpu_ptr(&nft_prandom_state);
-
-	return prandom_u32_state(state);
-}
-
 #ifdef CONFIG_IP_ROUTE_CLASSID
 static noinline bool
 nft_meta_get_eval_rtclassid(const struct sk_buff *skb, u32 *dest)
@@ -389,7 +381,7 @@ void nft_meta_get_eval(const struct nft_expr *expr,
 		break;
 #endif
 	case NFT_META_PRANDOM:
-		*dest = nft_prandom_u32();
+		*dest = get_random_u32();
 		break;
 #ifdef CONFIG_XFRM
 	case NFT_META_SECPATH:
@@ -518,7 +510,6 @@ int nft_meta_get_init(const struct nft_ctx *ctx,
 		len = IFNAMSIZ;
 		break;
 	case NFT_META_PRANDOM:
-		prandom_init_once(&nft_prandom_state);
 		len = sizeof(u32);
 		break;
 #ifdef CONFIG_XFRM
diff --git a/net/netfilter/nft_numgen.c b/net/netfilter/nft_numgen.c
index 81b40c663d86a..45d3dc9e96f2c 100644
--- a/net/netfilter/nft_numgen.c
+++ b/net/netfilter/nft_numgen.c
@@ -9,12 +9,11 @@
 #include <linux/netlink.h>
 #include <linux/netfilter.h>
 #include <linux/netfilter/nf_tables.h>
+#include <linux/random.h>
 #include <linux/static_key.h>
 #include <net/netfilter/nf_tables.h>
 #include <net/netfilter/nf_tables_core.h>
 
-static DEFINE_PER_CPU(struct rnd_state, nft_numgen_prandom_state);
-
 struct nft_ng_inc {
 	u8			dreg;
 	u32			modulus;
@@ -135,12 +134,9 @@ struct nft_ng_random {
 	u32			offset;
 };
 
-static u32 nft_ng_random_gen(struct nft_ng_random *priv)
+static u32 nft_ng_random_gen(const struct nft_ng_random *priv)
 {
-	struct rnd_state *state = this_cpu_ptr(&nft_numgen_prandom_state);
-
-	return reciprocal_scale(prandom_u32_state(state), priv->modulus) +
-	       priv->offset;
+	return reciprocal_scale(get_random_u32(), priv->modulus) + priv->offset;
 }
 
 static void nft_ng_random_eval(const struct nft_expr *expr,
@@ -168,8 +164,6 @@ static int nft_ng_random_init(const struct nft_ctx *ctx,
 	if (priv->offset + priv->modulus - 1 < priv->offset)
 		return -EOVERFLOW;
 
-	prandom_init_once(&nft_numgen_prandom_state);
-
 	return nft_parse_register_store(ctx, tb[NFTA_NG_DREG], &priv->dreg,
 					NULL, NFT_DATA_VALUE, sizeof(u32));
 }
-- 
GitLab


From 6640b5df1a38801be6d0595c8cd2177d968d7ee0 Mon Sep 17 00:00:00 2001
From: Saurabh Sengar <ssengar@linux.microsoft.com>
Date: Fri, 27 May 2022 00:43:59 -0700
Subject: [PATCH 0321/1731] Drivers: hv: vmbus: Don't assign VMbus channel
 interrupts to isolated CPUs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When initially assigning a VMbus channel interrupt to a CPU, don’t choose
a managed IRQ isolated CPU (as specified on the kernel boot line with
parameter 'isolcpus=managed_irq,<#cpu>'). Also, when using sysfs to change
the CPU that a VMbus channel will interrupt, don't allow changing to a
managed IRQ isolated CPU.

Signed-off-by: Saurabh Sengar <ssengar@linux.microsoft.com>
Reviewed-by: Michael Kelley <mikelley@microsoft.com>
Link: https://lore.kernel.org/r/1653637439-23060-1-git-send-email-ssengar@linux.microsoft.com
Signed-off-by: Wei Liu <wei.liu@kernel.org>
---
 drivers/hv/channel_mgmt.c | 17 ++++++++++++-----
 drivers/hv/vmbus_drv.c    |  4 ++++
 2 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/hv/channel_mgmt.c b/drivers/hv/channel_mgmt.c
index b60f13481bdcb..280b529277589 100644
--- a/drivers/hv/channel_mgmt.c
+++ b/drivers/hv/channel_mgmt.c
@@ -21,6 +21,7 @@
 #include <linux/cpu.h>
 #include <linux/hyperv.h>
 #include <asm/mshyperv.h>
+#include <linux/sched/isolation.h>
 
 #include "hyperv_vmbus.h"
 
@@ -728,16 +729,20 @@ static void init_vp_index(struct vmbus_channel *channel)
 	u32 i, ncpu = num_online_cpus();
 	cpumask_var_t available_mask;
 	struct cpumask *allocated_mask;
+	const struct cpumask *hk_mask = housekeeping_cpumask(HK_TYPE_MANAGED_IRQ);
 	u32 target_cpu;
 	int numa_node;
 
 	if (!perf_chn ||
-	    !alloc_cpumask_var(&available_mask, GFP_KERNEL)) {
+	    !alloc_cpumask_var(&available_mask, GFP_KERNEL) ||
+	    cpumask_empty(hk_mask)) {
 		/*
 		 * If the channel is not a performance critical
 		 * channel, bind it to VMBUS_CONNECT_CPU.
 		 * In case alloc_cpumask_var() fails, bind it to
 		 * VMBUS_CONNECT_CPU.
+		 * If all the cpus are isolated, bind it to
+		 * VMBUS_CONNECT_CPU.
 		 */
 		channel->target_cpu = VMBUS_CONNECT_CPU;
 		if (perf_chn)
@@ -758,17 +763,19 @@ static void init_vp_index(struct vmbus_channel *channel)
 		}
 		allocated_mask = &hv_context.hv_numa_map[numa_node];
 
-		if (cpumask_equal(allocated_mask, cpumask_of_node(numa_node))) {
+retry:
+		cpumask_xor(available_mask, allocated_mask, cpumask_of_node(numa_node));
+		cpumask_and(available_mask, available_mask, hk_mask);
+
+		if (cpumask_empty(available_mask)) {
 			/*
 			 * We have cycled through all the CPUs in the node;
 			 * reset the allocated map.
 			 */
 			cpumask_clear(allocated_mask);
+			goto retry;
 		}
 
-		cpumask_xor(available_mask, allocated_mask,
-			    cpumask_of_node(numa_node));
-
 		target_cpu = cpumask_first(available_mask);
 		cpumask_set_cpu(target_cpu, allocated_mask);
 
diff --git a/drivers/hv/vmbus_drv.c b/drivers/hv/vmbus_drv.c
index 714d549b7b46f..547ae334e5cd8 100644
--- a/drivers/hv/vmbus_drv.c
+++ b/drivers/hv/vmbus_drv.c
@@ -21,6 +21,7 @@
 #include <linux/kernel_stat.h>
 #include <linux/clockchips.h>
 #include <linux/cpu.h>
+#include <linux/sched/isolation.h>
 #include <linux/sched/task_stack.h>
 
 #include <linux/delay.h>
@@ -1770,6 +1771,9 @@ static ssize_t target_cpu_store(struct vmbus_channel *channel,
 	if (target_cpu >= nr_cpumask_bits)
 		return -EINVAL;
 
+	if (!cpumask_test_cpu(target_cpu, housekeeping_cpumask(HK_TYPE_MANAGED_IRQ)))
+		return -EINVAL;
+
 	/* No CPUs should come up or down during this. */
 	cpus_read_lock();
 
-- 
GitLab


From 92ec746bcea0c51cd29fb46e510fb71fe15282df Mon Sep 17 00:00:00 2001
From: Xiang wangx <wangxiang@cdjrlc.com>
Date: Sun, 5 Jun 2022 16:55:24 +0800
Subject: [PATCH 0322/1731] Drivers: hv: Fix syntax errors in comments

Delete the redundant word 'in'.

Signed-off-by: Xiang wangx <wangxiang@cdjrlc.com>
Reviewed-by: Michael Kelley <mikelley@microsoft.com>
Link: https://lore.kernel.org/r/20220605085524.11289-1-wangxiang@cdjrlc.com
Signed-off-by: Wei Liu <wei.liu@kernel.org>
---
 drivers/hv/hv_kvp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/hv/hv_kvp.c b/drivers/hv/hv_kvp.c
index c698592b83e42..d35b60c061148 100644
--- a/drivers/hv/hv_kvp.c
+++ b/drivers/hv/hv_kvp.c
@@ -394,7 +394,7 @@ kvp_send_key(struct work_struct *dummy)
 	in_msg = kvp_transaction.kvp_msg;
 
 	/*
-	 * The key/value strings sent from the host are encoded in
+	 * The key/value strings sent from the host are encoded
 	 * in utf16; convert it to utf8 strings.
 	 * The host assures us that the utf16 strings will not exceed
 	 * the max lengths specified. We will however, reserve room
-- 
GitLab


From 245b993d8f6c4e25f19191edfbd8080b645e12b1 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <masahiroy@kernel.org>
Date: Mon, 6 Jun 2022 14:02:38 +0900
Subject: [PATCH 0323/1731] clocksource: hyper-v: unexport __init-annotated
 hv_init_clocksource()

EXPORT_SYMBOL and __init is a bad combination because the .init.text
section is freed up after the initialization. Hence, modules cannot
use symbols annotated __init. The access to a freed symbol may end up
with kernel panic.

modpost used to detect it, but it has been broken for a decade.

Recently, I fixed modpost so it started to warn it again, then this
showed up in linux-next builds.

There are two ways to fix it:

  - Remove __init
  - Remove EXPORT_SYMBOL

I chose the latter for this case because the only in-tree call-site,
arch/x86/kernel/cpu/mshyperv.c is never compiled as modular.
(CONFIG_HYPERVISOR_GUEST is boolean)

Fixes: dd2cb348613b ("clocksource/drivers: Continue making Hyper-V clocksource ISA agnostic")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Reviewed-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Reviewed-by: Michael Kelley <mikelley@microsoft.com>
Link: https://lore.kernel.org/r/20220606050238.4162200-1-masahiroy@kernel.org
Signed-off-by: Wei Liu <wei.liu@kernel.org>
---
 drivers/clocksource/hyperv_timer.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/clocksource/hyperv_timer.c b/drivers/clocksource/hyperv_timer.c
index ff188ab68496e..bb47610bbd1c4 100644
--- a/drivers/clocksource/hyperv_timer.c
+++ b/drivers/clocksource/hyperv_timer.c
@@ -565,4 +565,3 @@ void __init hv_init_clocksource(void)
 	hv_sched_clock_offset = hv_read_reference_counter();
 	hv_setup_sched_clock(read_hv_sched_clock_msr);
 }
-EXPORT_SYMBOL_GPL(hv_init_clocksource);
-- 
GitLab


From f5f93d7f5a5cbfef02609dead21e7056e83f4fab Mon Sep 17 00:00:00 2001
From: Michael Kelley <mikelley@microsoft.com>
Date: Tue, 7 Jun 2022 20:49:37 -0700
Subject: [PATCH 0324/1731] HID: hyperv: Correctly access fields declared as
 __le16

Add the use of le16_to_cpu() for fields declared as __le16. Because
Hyper-V only runs in Little Endian mode, there's no actual bug.
The change is made in the interest of general correctness in
addition to making sparse happy. No functional change.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Michael Kelley <mikelley@microsoft.com>
Link: https://lore.kernel.org/r/1654660177-115463-1-git-send-email-mikelley@microsoft.com
Signed-off-by: Wei Liu <wei.liu@kernel.org>
---
 drivers/hid/hid-hyperv.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/hid/hid-hyperv.c b/drivers/hid/hid-hyperv.c
index 978ee2aab2d40..e0bc731241960 100644
--- a/drivers/hid/hid-hyperv.c
+++ b/drivers/hid/hid-hyperv.c
@@ -199,7 +199,8 @@ static void mousevsc_on_receive_device_info(struct mousevsc_dev *input_device,
 	if (!input_device->hid_desc)
 		goto cleanup;
 
-	input_device->report_desc_size = desc->desc[0].wDescriptorLength;
+	input_device->report_desc_size = le16_to_cpu(
+					desc->desc[0].wDescriptorLength);
 	if (input_device->report_desc_size == 0) {
 		input_device->dev_info_status = -EINVAL;
 		goto cleanup;
@@ -217,7 +218,7 @@ static void mousevsc_on_receive_device_info(struct mousevsc_dev *input_device,
 
 	memcpy(input_device->report_desc,
 	       ((unsigned char *)desc) + desc->bLength,
-	       desc->desc[0].wDescriptorLength);
+	       le16_to_cpu(desc->desc[0].wDescriptorLength));
 
 	/* Send the ack */
 	memset(&ack, 0, sizeof(struct mousevsc_prt_msg));
-- 
GitLab


From c5cb0002d14b6f7aabaf7d67d0515fe70aea7167 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Tue, 7 Jun 2022 17:51:08 -0700
Subject: [PATCH 0325/1731] drm/i915: More PVC+DG2 workarounds

A new PVC+DG2 workaround has appeared recently:
 - Wa_16015675438

And a couple existing DG2 workarounds have been extended to PVC:
 - Wa_14015795083
 - Wa_18018781329

Note that Wa_16015675438 asks us to program a register that is in the
0x2xxx range typically associated with the RCS engine, even though PVC
does not have an RCS.  By default the GuC will think we've made a
mistake and throw an exception when it sees this register on a CCS
engine's save/restore list, so we need to pass an extra GuC control flag
to tell it that this is expected and not a problem.

Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220608005108.3717895-1-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h     |  1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +++++++++++++++------
 drivers/gpu/drm/i915/gt/uc/intel_guc.c      |  4 ++++
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h |  1 +
 4 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index c8129a3517316..2265570180371 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -140,6 +140,7 @@
 #define FF_SLICE_CS_CHICKEN2			_MMIO(0x20e4)
 #define   GEN9_TSG_BARRIER_ACK_DISABLE		(1 << 8)
 #define   GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE	(1 << 10)
+#define   GEN12_PERF_FIX_BALANCING_CFE_DISABLE	REG_BIT(15)
 
 #define GEN9_CS_DEBUG_MODE1			_MMIO(0x20ec)
 #define   FF_DOP_CLOCK_GATE_DISABLE		REG_BIT(1)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 0ac7f5daacc42..aeadbb3b72cbc 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1491,13 +1491,20 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 	wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
 }
 
+static void
+pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
+{
+	/* Wa_14015795083 */
+	wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
+}
+
 static void
 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
 {
 	struct drm_i915_private *i915 = gt->i915;
 
 	if (IS_PONTEVECCHIO(i915))
-		; /* none yet */
+		pvc_gt_workarounds_init(gt, wal);
 	else if (IS_DG2(i915))
 		dg2_gt_workarounds_init(gt, wal);
 	else if (IS_XEHPSDV(i915))
@@ -2082,12 +2089,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 		 * performance guide section.
 		 */
 		wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
-
-		/* Wa_18018781329:dg2 */
-		wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
-		wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
-		wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
-		wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
 	}
 
 	if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
@@ -2700,6 +2701,15 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 
 		/* Wa_22014226127:dg2,pvc */
 		wa_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
+
+		/* Wa_16015675438:dg2,pvc */
+		wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
+
+		/* Wa_18018781329:dg2,pvc */
+		wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
+		wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
+		wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
+		wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 2c4ad4a650899..35887cb532019 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -327,6 +327,10 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
 	    IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_FOREVER))
 		flags |= GUC_WA_CONTEXT_ISOLATION;
 
+	/* Wa_16015675438 */
+	if (!RCS_MASK(gt))
+		flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;
+
 	return flags;
 }
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 42cb7a9a6199c..b3c9a9327f764 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -105,6 +105,7 @@
 #define   GUC_WA_PRE_PARSER		BIT(14)
 #define   GUC_WA_HOLD_CCS_SWITCHOUT	BIT(17)
 #define   GUC_WA_POLLCS			BIT(18)
+#define   GUC_WA_RCS_REGS_IN_CCS_REGS_LIST	BIT(21)
 
 #define GUC_CTL_FEATURE			2
 #define   GUC_CTL_ENABLE_SLPC		BIT(2)
-- 
GitLab


From 17f65658c8adce6233f9e53be59d399af6180059 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Tue, 7 Jun 2022 10:57:16 -0700
Subject: [PATCH 0326/1731] drm/i915/xehp: Correct steering initialization

Another mistake during the conversion to DSS bitmaps:  after retrieving
the DSS ID intel_sseu_find_first_xehp_dss() we forgot to modulo it down
to obtain which ID within the current gslice it is.

Fixes: b87d39019651 ("drm/i915/sseu: Disassociate internal subslice mask representation from uapi")
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220607175716.3338661-1-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index aeadbb3b72cbc..1ee54a83e459b 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1177,8 +1177,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
 	}
 
 	slice = __ffs(slice_mask);
-	subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice);
-	WARN_ON(subslice > GEN_DSS_PER_GSLICE);
+	subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice) %
+		GEN_DSS_PER_GSLICE;
 
 	__add_mcr_wa(gt, wal, slice, subslice);
 
-- 
GitLab


From 68e355c00f2d58ba0426cf9a4d9df77077493018 Mon Sep 17 00:00:00 2001
From: Jesse Zhang <Jesse.Zhang@amd.com>
Date: Tue, 7 Jun 2022 10:44:57 +0800
Subject: [PATCH 0327/1731] drm/amdkfd:Fix fw version for 10.3.6

fix fw error when loading fw for 10.3.6

Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index f8635e7685136..bf42004577722 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -182,7 +182,9 @@ static void kfd_device_info_init(struct kfd_dev *kfd,
 
 		if (gc_version < IP_VERSION(11, 0, 0)) {
 			/* Navi2x+, Navi1x+ */
-			if (gc_version >= IP_VERSION(10, 3, 0))
+			if (gc_version == IP_VERSION(10, 3, 6))
+				kfd->device_info.no_atomic_fw_version = 14;
+			else if (gc_version >= IP_VERSION(10, 3, 0))
 				kfd->device_info.no_atomic_fw_version = 92;
 			else if (gc_version >= IP_VERSION(10, 1, 1))
 				kfd->device_info.no_atomic_fw_version = 145;
-- 
GitLab


From 61243c173cd26fc8c6bea74d6d47a37ab520dacc Mon Sep 17 00:00:00 2001
From: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
Date: Tue, 7 Jun 2022 12:06:21 +0530
Subject: [PATCH 0328/1731] drm/amd/amdgpu: Fix alignment issue
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Fix alignment problems reported by zuul for the
commit b07d1d73b09e ("drm/amd/amdgpu: Enable high priority gfx queue")

Fixes: b07d1d73b09e ("drm/amd/amdgpu: Enable high priority gfx queue")
Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c  | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 00c69f0a9f52e..b697353e5a7ae 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -241,7 +241,7 @@ void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
 				adev->gfx.me.num_queue_per_pipe;
 
 			set_bit(pipe * adev->gfx.me.num_queue_per_pipe + queue,
-					adev->gfx.me.queue_bitmap);
+				adev->gfx.me.queue_bitmap);
 		}
 	} else {
 		for (i = 0; i < max_queues_per_me; ++i)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 1fa9edf040225..d3558c34d406c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -544,9 +544,9 @@ static void amdgpu_ring_to_mqd_prop(struct amdgpu_ring *ring,
 	prop->hqd_active = ring->funcs->type == AMDGPU_RING_TYPE_KIQ;
 
 	if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE &&
-	    amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) ||
+	     amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) ||
 	    (ring->funcs->type == AMDGPU_RING_TYPE_GFX &&
-	    amdgpu_gfx_is_high_priority_graphics_queue(adev, ring))) {
+	     amdgpu_gfx_is_high_priority_graphics_queue(adev, ring))) {
 		prop->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
 		prop->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
 	}
-- 
GitLab


From 143fee0ccc97284e6ece1cf86b7d50721b522448 Mon Sep 17 00:00:00 2001
From: Joseph Greathouse <Joseph.Greathouse@amd.com>
Date: Mon, 6 Jun 2022 16:09:25 -0500
Subject: [PATCH 0329/1731] drm/amdgpu: Add MODE register to wave debug info in
 gfx11

All other chips, from gfx6-gfx10, now include the MODE register at the
end of the wave debug state. This appears to have been missed in gfx11,
so this patch adds in MODE to the debug state for gfx11.

Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index ca37289c644ff..05359df6c3548 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -1096,6 +1096,7 @@ static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd,
 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
 }
 
 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
-- 
GitLab


From 0dc662318d36e060268751fbd3309660acd3c5aa Mon Sep 17 00:00:00 2001
From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Date: Fri, 3 Jun 2022 11:58:35 -0400
Subject: [PATCH 0330/1731] drm/amd/display: Remove duplicated macro

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/include/dal_asic_id.h | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 11391eead954e..a0dffe30b3944 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -221,10 +221,6 @@ enum {
 #ifndef ASICREV_IS_VANGOGH
 #define ASICREV_IS_VANGOGH(eChipRev) ((eChipRev >= VANGOGH_A0) && (eChipRev < VANGOGH_UNKNOWN))
 #endif
-#define GREEN_SARDINE_A0 0xA1
-#ifndef ASICREV_IS_GREEN_SARDINE
-#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF))
-#endif
 
 #define FAMILY_YELLOW_CARP                     146
 #define YELLOW_CARP_A0 0x01
@@ -288,6 +284,4 @@ enum {
 
 #define	FAMILY_UNKNOWN 0xFF
 
-
-
 #endif /* __DAL_ASIC_ID_H__ */
-- 
GitLab


From c55300ad4a1814bac9191a4d2c7b0d74273aec7c Mon Sep 17 00:00:00 2001
From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Date: Wed, 1 Jun 2022 10:26:54 -0400
Subject: [PATCH 0331/1731] drm/amd/display: Reduce frame size in the bouding
 box for DCN20

GCC throw warnings for the function dcn20_update_bounding_box due to its
frame size that looks like this:

 error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]

This commit fixes this issue by eliminating an intermediary variable
that creates a large array.

Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Hamza Mahfooz <hamza.mahfooz@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c  | 38 +++++++++----------
 1 file changed, 18 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index eeec40f6fd0aa..d9cc178f6980e 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -1456,21 +1456,20 @@ void dcn20_calculate_wm(
 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
 		struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
 {
-	struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES];
-	int i;
 	int num_calculated_states = 0;
 	int min_dcfclk = 0;
+	int i;
 
 	dc_assert_fp_enabled();
 
 	if (num_states == 0)
 		return;
 
-	memset(calculated_states, 0, sizeof(calculated_states));
+	memset(bb->clock_limits, 0, sizeof(bb->clock_limits));
 
-	if (dc->bb_overrides.min_dcfclk_mhz > 0)
+	if (dc->bb_overrides.min_dcfclk_mhz > 0) {
 		min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
-	else {
+	} else {
 		if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
 			min_dcfclk = 310;
 		else
@@ -1481,36 +1480,35 @@ void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
 
 	for (i = 0; i < num_states; i++) {
 		int min_fclk_required_by_uclk;
-		calculated_states[i].state = i;
-		calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
+		bb->clock_limits[i].state = i;
+		bb->clock_limits[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
 
 		// FCLK:UCLK ratio is 1.08
 		min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080,
 			1000000);
 
-		calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
+		bb->clock_limits[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
 				min_dcfclk : min_fclk_required_by_uclk;
 
-		calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
-				max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
+		bb->clock_limits[i].socclk_mhz = (bb->clock_limits[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
+				max_clocks->socClockInKhz / 1000 : bb->clock_limits[i].fabricclk_mhz;
 
-		calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
-				max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
+		bb->clock_limits[i].dcfclk_mhz = (bb->clock_limits[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
+				max_clocks->dcfClockInKhz / 1000 : bb->clock_limits[i].fabricclk_mhz;
 
-		calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
-		calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
-		calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
+		bb->clock_limits[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
+		bb->clock_limits[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
+		bb->clock_limits[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
 
-		calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
+		bb->clock_limits[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
 
 		num_calculated_states++;
 	}
 
-	calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
-	calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
-	calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
+	bb->clock_limits[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
+	bb->clock_limits[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
+	bb->clock_limits[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
 
-	memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
 	bb->num_states = num_calculated_states;
 
 	// Duplicate the last state, DML always an extra state identical to max state to work
-- 
GitLab


From 6fbfc3a23c98bdcda679161c4f4e31368008af8a Mon Sep 17 00:00:00 2001
From: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
Date: Thu, 26 May 2022 11:51:08 -0500
Subject: [PATCH 0332/1731] drm/amdkfd: Define config HSA_AMD_P2P to support
 peer-to-peer

Extend current kernel config requirements of amdgpu by adding config
HSA_AMD_P2P. Enabling HSA_AMD_P2P is REQUIRED to support peer-to-peer
communication between AMD GPU devices over PCIe bus

Signed-off-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/Kconfig | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/Kconfig b/drivers/gpu/drm/amd/amdkfd/Kconfig
index 8cc0a76ddf9fa..93bd4eda0d94f 100644
--- a/drivers/gpu/drm/amd/amdkfd/Kconfig
+++ b/drivers/gpu/drm/amd/amdkfd/Kconfig
@@ -25,3 +25,17 @@ config HSA_AMD_SVM
 	  preemptions and one based on page faults. To enable page fault
 	  based memory management on most GFXv9 GPUs, set the module
 	  parameter amdgpu.noretry=0.
+
+config HSA_AMD_P2P
+	bool "HSA kernel driver support for peer-to-peer for AMD GPU devices"
+	depends on HSA_AMD && PCI_P2PDMA && DMABUF_MOVE_NOTIFY
+	help
+	  Enable peer-to-peer (P2P) communication between AMD GPUs over
+	  the PCIe bus. This can improve performance of multi-GPU compute
+	  applications and libraries by enabling GPUs to access data directly
+	  in peer GPUs' memory without intermediate copies in system memory.
+
+	  This P2P feature is only enabled on compatible chipsets, and between
+	  GPUs with large memory BARs that expose the entire VRAM in PCIe bus
+	  address space within the physical address limits of the GPUs.
+
-- 
GitLab


From 08a2fd23c6c21e5ef24248a9c1b09e929655eb3b Mon Sep 17 00:00:00 2001
From: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
Date: Thu, 26 May 2022 12:24:23 -0500
Subject: [PATCH 0333/1731] drm/amdgpu: Add peer-to-peer support among PCIe
 connected AMD GPUs

Add support for peer-to-peer communication among AMD GPUs over PCIe
bus. Support REQUIRES enablement of config HSA_AMD_P2P.

Signed-off-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h           |   3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h    |   1 +
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 300 ++++++++++++++----
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    |  31 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c       |  10 +
 5 files changed, 283 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index c67069645a2c1..47bcf86cd0f3f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -223,6 +223,9 @@ static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
 static const bool __maybe_unused debug_evictions; /* = false */
 static const bool __maybe_unused no_system_mem_limit;
 #endif
+#ifdef CONFIG_HSA_AMD_P2P
+extern bool pcie_p2p;
+#endif
 
 extern int amdgpu_tmz;
 extern int amdgpu_reset_method;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index f8b9f27adcf51..5c00ea1df21cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -48,6 +48,7 @@ enum kfd_mem_attachment_type {
 	KFD_MEM_ATT_SHARED,	/* Share kgd_mem->bo or another attachment's */
 	KFD_MEM_ATT_USERPTR,	/* SG bo to DMA map pages from a userptr bo */
 	KFD_MEM_ATT_DMABUF,	/* DMAbuf to DMA map TTM BOs */
+	KFD_MEM_ATT_SG		/* Tag to DMA map SG BOs */
 };
 
 struct kfd_mem_attachment {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 6b6d46e29e6e8..9798551900314 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -241,6 +241,42 @@ void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
 	kfree(bo->kfd_bo);
 }
 
+/**
+ * @create_dmamap_sg_bo: Creates a amdgpu_bo object to reflect information
+ * about USERPTR or DOOREBELL or MMIO BO.
+ * @adev: Device for which dmamap BO is being created
+ * @mem: BO of peer device that is being DMA mapped. Provides parameters
+ *	 in building the dmamap BO
+ * @bo_out: Output parameter updated with handle of dmamap BO
+ */
+static int
+create_dmamap_sg_bo(struct amdgpu_device *adev,
+		 struct kgd_mem *mem, struct amdgpu_bo **bo_out)
+{
+	struct drm_gem_object *gem_obj;
+	int ret, align;
+
+	ret = amdgpu_bo_reserve(mem->bo, false);
+	if (ret)
+		return ret;
+
+	align = 1;
+	ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, align,
+			AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE,
+			ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj);
+
+	amdgpu_bo_unreserve(mem->bo);
+
+	if (ret) {
+		pr_err("Error in creating DMA mappable SG BO on domain: %d\n", ret);
+		return -EINVAL;
+	}
+
+	*bo_out = gem_to_amdgpu_bo(gem_obj);
+	(*bo_out)->parent = amdgpu_bo_ref(mem->bo);
+	return ret;
+}
+
 /* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's
  *  reservation object.
  *
@@ -446,6 +482,38 @@ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
 	return pte_flags;
 }
 
+/**
+ * create_sg_table() - Create an sg_table for a contiguous DMA addr range
+ * @addr: The starting address to point to
+ * @size: Size of memory area in bytes being pointed to
+ *
+ * Allocates an instance of sg_table and initializes it to point to memory
+ * area specified by input parameters. The address used to build is assumed
+ * to be DMA mapped, if needed.
+ *
+ * DOORBELL or MMIO BOs use only one scatterlist node in their sg_table
+ * because they are physically contiguous.
+ *
+ * Return: Initialized instance of SG Table or NULL
+ */
+static struct sg_table *create_sg_table(uint64_t addr, uint32_t size)
+{
+	struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL);
+
+	if (!sg)
+		return NULL;
+	if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
+		kfree(sg);
+		return NULL;
+	}
+	sg_dma_address(sg->sgl) = addr;
+	sg->sgl->length = size;
+#ifdef CONFIG_NEED_SG_DMA_LENGTH
+	sg->sgl->dma_length = size;
+#endif
+	return sg;
+}
+
 static int
 kfd_mem_dmamap_userptr(struct kgd_mem *mem,
 		       struct kfd_mem_attachment *attachment)
@@ -510,6 +578,87 @@ kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment)
 	return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 }
 
+/**
+ * kfd_mem_dmamap_sg_bo() - Create DMA mapped sg_table to access DOORBELL or MMIO BO
+ * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
+ * @attachment: Virtual address attachment of the BO on accessing device
+ *
+ * An access request from the device that owns DOORBELL does not require DMA mapping.
+ * This is because the request doesn't go through PCIe root complex i.e. it instead
+ * loops back. The need to DMA map arises only when accessing peer device's DOORBELL
+ *
+ * In contrast, all access requests for MMIO need to be DMA mapped without regard to
+ * device ownership. This is because access requests for MMIO go through PCIe root
+ * complex.
+ *
+ * This is accomplished in two steps:
+ *   - Obtain DMA mapped address of DOORBELL or MMIO memory that could be used
+ *         in updating requesting device's page table
+ *   - Signal TTM to mark memory pointed to by requesting device's BO as GPU
+ *         accessible. This allows an update of requesting device's page table
+ *         with entries associated with DOOREBELL or MMIO memory
+ *
+ * This method is invoked in the following contexts:
+ *   - Mapping of DOORBELL or MMIO BO of same or peer device
+ *   - Validating an evicted DOOREBELL or MMIO BO on device seeking access
+ *
+ * Return: ZERO if successful, NON-ZERO otherwise
+ */
+static int
+kfd_mem_dmamap_sg_bo(struct kgd_mem *mem,
+		     struct kfd_mem_attachment *attachment)
+{
+	struct ttm_operation_ctx ctx = {.interruptible = true};
+	struct amdgpu_bo *bo = attachment->bo_va->base.bo;
+	struct amdgpu_device *adev = attachment->adev;
+	struct ttm_tt *ttm = bo->tbo.ttm;
+	enum dma_data_direction dir;
+	dma_addr_t dma_addr;
+	bool mmio;
+	int ret;
+
+	/* Expect SG Table of dmapmap BO to be NULL */
+	mmio = (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP);
+	if (unlikely(ttm->sg)) {
+		pr_err("SG Table of %d BO for peer device is UNEXPECTEDLY NON-NULL", mmio);
+		return -EINVAL;
+	}
+
+	dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
+			DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
+	dma_addr = mem->bo->tbo.sg->sgl->dma_address;
+	pr_debug("%d BO size: %d\n", mmio, mem->bo->tbo.sg->sgl->length);
+	pr_debug("%d BO address before DMA mapping: %llx\n", mmio, dma_addr);
+	dma_addr = dma_map_resource(adev->dev, dma_addr,
+			mem->bo->tbo.sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
+	ret = dma_mapping_error(adev->dev, dma_addr);
+	if (unlikely(ret))
+		return ret;
+	pr_debug("%d BO address after DMA mapping: %llx\n", mmio, dma_addr);
+
+	ttm->sg = create_sg_table(dma_addr, mem->bo->tbo.sg->sgl->length);
+	if (unlikely(!ttm->sg)) {
+		ret = -ENOMEM;
+		goto unmap_sg;
+	}
+
+	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
+	ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
+	if (unlikely(ret))
+		goto free_sg;
+
+	return ret;
+
+free_sg:
+	sg_free_table(ttm->sg);
+	kfree(ttm->sg);
+	ttm->sg = NULL;
+unmap_sg:
+	dma_unmap_resource(adev->dev, dma_addr, mem->bo->tbo.sg->sgl->length,
+			   dir, DMA_ATTR_SKIP_CPU_SYNC);
+	return ret;
+}
+
 static int
 kfd_mem_dmamap_attachment(struct kgd_mem *mem,
 			  struct kfd_mem_attachment *attachment)
@@ -521,6 +670,8 @@ kfd_mem_dmamap_attachment(struct kgd_mem *mem,
 		return kfd_mem_dmamap_userptr(mem, attachment);
 	case KFD_MEM_ATT_DMABUF:
 		return kfd_mem_dmamap_dmabuf(attachment);
+	case KFD_MEM_ATT_SG:
+		return kfd_mem_dmamap_sg_bo(mem, attachment);
 	default:
 		WARN_ON_ONCE(1);
 	}
@@ -561,6 +712,50 @@ kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment)
 	ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 }
 
+/**
+ * kfd_mem_dmaunmap_sg_bo() - Free DMA mapped sg_table of DOORBELL or MMIO BO
+ * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
+ * @attachment: Virtual address attachment of the BO on accessing device
+ *
+ * The method performs following steps:
+ *   - Signal TTM to mark memory pointed to by BO as GPU inaccessible
+ *   - Free SG Table that is used to encapsulate DMA mapped memory of
+ *          peer device's DOORBELL or MMIO memory
+ *
+ * This method is invoked in the following contexts:
+ *     UNMapping of DOORBELL or MMIO BO on a device having access to its memory
+ *     Eviction of DOOREBELL or MMIO BO on device having access to its memory
+ *
+ * Return: void
+ */
+static void
+kfd_mem_dmaunmap_sg_bo(struct kgd_mem *mem,
+		       struct kfd_mem_attachment *attachment)
+{
+	struct ttm_operation_ctx ctx = {.interruptible = true};
+	struct amdgpu_bo *bo = attachment->bo_va->base.bo;
+	struct amdgpu_device *adev = attachment->adev;
+	struct ttm_tt *ttm = bo->tbo.ttm;
+	enum dma_data_direction dir;
+
+	if (unlikely(!ttm->sg)) {
+		pr_err("SG Table of BO is UNEXPECTEDLY NULL");
+		return;
+	}
+
+	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
+	ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
+
+	dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
+				DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
+	dma_unmap_resource(adev->dev, ttm->sg->sgl->dma_address,
+			ttm->sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
+	sg_free_table(ttm->sg);
+	kfree(ttm->sg);
+	ttm->sg = NULL;
+	bo->tbo.sg = NULL;
+}
+
 static void
 kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
 			    struct kfd_mem_attachment *attachment)
@@ -574,38 +769,14 @@ kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
 	case KFD_MEM_ATT_DMABUF:
 		kfd_mem_dmaunmap_dmabuf(attachment);
 		break;
+	case KFD_MEM_ATT_SG:
+		kfd_mem_dmaunmap_sg_bo(mem, attachment);
+		break;
 	default:
 		WARN_ON_ONCE(1);
 	}
 }
 
-static int
-kfd_mem_attach_userptr(struct amdgpu_device *adev, struct kgd_mem *mem,
-		       struct amdgpu_bo **bo)
-{
-	unsigned long bo_size = mem->bo->tbo.base.size;
-	struct drm_gem_object *gobj;
-	int ret;
-
-	ret = amdgpu_bo_reserve(mem->bo, false);
-	if (ret)
-		return ret;
-
-	ret = amdgpu_gem_object_create(adev, bo_size, 1,
-				       AMDGPU_GEM_DOMAIN_CPU,
-				       AMDGPU_GEM_CREATE_PREEMPTIBLE,
-				       ttm_bo_type_sg, mem->bo->tbo.base.resv,
-				       &gobj);
-	amdgpu_bo_unreserve(mem->bo);
-	if (ret)
-		return ret;
-
-	*bo = gem_to_amdgpu_bo(gobj);
-	(*bo)->parent = amdgpu_bo_ref(mem->bo);
-
-	return 0;
-}
-
 static int
 kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem,
 		      struct amdgpu_bo **bo)
@@ -656,6 +827,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
 	uint64_t va = mem->va;
 	struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
 	struct amdgpu_bo *bo[2] = {NULL, NULL};
+	bool same_hive = false;
 	int i, ret;
 
 	if (!va) {
@@ -663,6 +835,24 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
 		return -EINVAL;
 	}
 
+	/* Determine access to VRAM, MMIO and DOORBELL BOs of peer devices
+	 *
+	 * The access path of MMIO and DOORBELL BOs of is always over PCIe.
+	 * In contrast the access path of VRAM BOs depens upon the type of
+	 * link that connects the peer device. Access over PCIe is allowed
+	 * if peer device has large BAR. In contrast, access over xGMI is
+	 * allowed for both small and large BAR configurations of peer device
+	 */
+	if ((adev != bo_adev) &&
+	    ((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) ||
+	     (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) ||
+	     (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
+		if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM)
+			same_hive = amdgpu_xgmi_same_hive(adev, bo_adev);
+		if (!same_hive && !amdgpu_device_is_peer_accessible(bo_adev, adev))
+			return -EINVAL;
+	}
+
 	for (i = 0; i <= is_aql; i++) {
 		attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL);
 		if (unlikely(!attachment[i])) {
@@ -673,9 +863,9 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
 		pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
 			 va + bo_size, vm);
 
-		if (adev == bo_adev ||
-		   (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && adev->ram_is_direct_mapped) ||
-		   (mem->domain == AMDGPU_GEM_DOMAIN_VRAM && amdgpu_xgmi_same_hive(adev, bo_adev))) {
+		if ((adev == bo_adev && !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) ||
+		    (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && adev->ram_is_direct_mapped) ||
+		    same_hive) {
 			/* Mappings on the local GPU, or VRAM mappings in the
 			 * local hive, or userptr mapping IOMMU direct map mode
 			 * share the original BO
@@ -691,26 +881,30 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
 		} else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
 			/* Create an SG BO to DMA-map userptrs on other GPUs */
 			attachment[i]->type = KFD_MEM_ATT_USERPTR;
-			ret = kfd_mem_attach_userptr(adev, mem, &bo[i]);
+			ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
 			if (ret)
 				goto unwind;
-		} else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT &&
-			   mem->bo->tbo.type != ttm_bo_type_sg) {
-			/* GTT BOs use DMA-mapping ability of dynamic-attach
-			 * DMA bufs. TODO: The same should work for VRAM on
-			 * large-BAR GPUs.
-			 */
+		/* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */
+		} else if (mem->bo->tbo.type == ttm_bo_type_sg) {
+			WARN_ONCE(!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL ||
+				    mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP),
+				  "Handing invalid SG BO in ATTACH request");
+			attachment[i]->type = KFD_MEM_ATT_SG;
+			ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
+			if (ret)
+				goto unwind;
+		/* Enable acces to GTT and VRAM BOs of peer devices */
+		} else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT ||
+			   mem->domain == AMDGPU_GEM_DOMAIN_VRAM) {
 			attachment[i]->type = KFD_MEM_ATT_DMABUF;
 			ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]);
 			if (ret)
 				goto unwind;
+			pr_debug("Employ DMABUF mechanim to enable peer GPU access\n");
 		} else {
-			/* FIXME: Need to DMA-map other BO types:
-			 * large-BAR VRAM, doorbells, MMIO remap
-			 */
-			attachment[i]->type = KFD_MEM_ATT_SHARED;
-			bo[i] = mem->bo;
-			drm_gem_object_get(&bo[i]->tbo.base);
+			WARN_ONCE(true, "Handling invalid ATTACH request");
+			ret = -EINVAL;
+			goto unwind;
 		}
 
 		/* Add BO to VM internal data structures */
@@ -1111,24 +1305,6 @@ update_gpuvm_pte_failed:
 	return ret;
 }
 
-static struct sg_table *create_doorbell_sg(uint64_t addr, uint32_t size)
-{
-	struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL);
-
-	if (!sg)
-		return NULL;
-	if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
-		kfree(sg);
-		return NULL;
-	}
-	sg->sgl->dma_address = addr;
-	sg->sgl->length = size;
-#ifdef CONFIG_NEED_SG_DMA_LENGTH
-	sg->sgl->dma_length = size;
-#endif
-	return sg;
-}
-
 static int process_validate_vms(struct amdkfd_process_info *process_info)
 {
 	struct amdgpu_vm *peer_vm;
@@ -1497,7 +1673,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 			bo_type = ttm_bo_type_sg;
 			if (size > UINT_MAX)
 				return -EINVAL;
-			sg = create_doorbell_sg(*offset, size);
+			sg = create_sg_table(*offset, size);
 			if (!sg)
 				return -ENOMEM;
 		} else {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 620afd75dae76..b9d50cb6c2361 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -34,6 +34,7 @@
 #include <linux/pci.h>
 #include <linux/devcoredump.h>
 #include <generated/utsrelease.h>
+#include <linux/pci-p2pdma.h>
 
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_probe_helper.h>
@@ -5499,6 +5500,36 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
 	}
 }
 
+/**
+ * amdgpu_device_is_peer_accessible - Check peer access through PCIe BAR
+ *
+ * @adev: amdgpu_device pointer
+ * @peer_adev: amdgpu_device pointer for peer device trying to access @adev
+ *
+ * Return true if @peer_adev can access (DMA) @adev through the PCIe
+ * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of
+ * @peer_adev.
+ */
+bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
+				      struct amdgpu_device *peer_adev)
+{
+#ifdef CONFIG_HSA_AMD_P2P
+	uint64_t address_mask = peer_adev->dev->dma_mask ?
+		~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1);
+	resource_size_t aper_limit =
+		adev->gmc.aper_base + adev->gmc.aper_size - 1;
+	bool p2p_access = !(pci_p2pdma_distance_many(adev->pdev,
+					&peer_adev->dev, 1, true) < 0);
+
+	return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size &&
+		adev->gmc.real_vram_size == adev->gmc.visible_vram_size &&
+		!(adev->gmc.aper_base & address_mask ||
+		  aper_limit & address_mask));
+#else
+	return false;
+#endif
+}
+
 int amdgpu_device_baco_enter(struct drm_device *dev)
 {
 	struct amdgpu_device *adev = drm_to_adev(dev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 8890300766a5b..e3d1397081606 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -802,6 +802,16 @@ MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (
 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
 #endif
 
+/**
+ * DOC: pcie_p2p (bool)
+ * Enable PCIe P2P (requires large-BAR). Default value: true (on)
+ */
+#ifdef CONFIG_HSA_AMD_P2P
+bool pcie_p2p = true;
+module_param(pcie_p2p, bool, 0444);
+MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))");
+#endif
+
 /**
  * DOC: dcfeaturemask (uint)
  * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
-- 
GitLab


From 136788cc74cbd9fabc2922b77bfdd38a53eb7155 Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Tue, 7 Jun 2022 09:43:02 -0400
Subject: [PATCH 0334/1731] drm/amd/display: fix null pointer deref error

[Why]
0 was passed in place of a pointer which triggered null pointer
dereference.

Causes a backtrace like:

[   41.159466] RIP: 0010:dccg31_set_audio_dtbclk_dto+0x10/0x120 [amdgpu]
[   41.159928] Code: c0 00 00 00 6a 01 8b 92 84 01 00 00 52 0f b6 40 61 e9 30 ff ff ff 0f 1f 40 00 0f 1f 44 00 00 55 48 89 e5 41 56 41 55 41 54 53 <44> 8b 66 18 48 89 fb 48 8b 47 30 48 8b 3f 45 85 e4 74 09 4c 63 6e
[   41.159932] RSP: 0018:ffffaee54055afd0 EFLAGS: 00010246
[   41.159936] RAX: 0000000000000000 RBX: 0000000000000000 RCX: ffff917445901800
[   41.159939] RDX: ffffffffc15e6ca0 RSI: 0000000000000000 RDI: ffff91744dbd8c60
[   41.159941] RBP: ffffaee54055aff0 R08: 0000000000000100 R09: ffffaee54055afe8
[   41.159944] R10: 0000000000000001 R11: 0000000000000009 R12: ffff91747ca201f0
[   41.159946] R13: ffff91747ca20000 R14: ffff917448720438 R15: ffff91747ca20000
[   41.159948] FS:  00007f5e13e5f740(0000) GS:ffff91775ca40000(0000) knlGS:0000000000000000
[   41.159951] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[   41.159954] CR2: 0000000000000018 CR3: 000000010fea0000 CR4: 00000000003506e0
[   41.159956] Call Trace:
[   41.159959]  <TASK>
[   41.159964]  dce110_setup_audio_dto.isra.0+0xd8/0x1f0 [amdgpu]
[   41.160411]  dce110_apply_ctx_to_hw+0x1aa/0x780 [amdgpu]
[   41.160842]  ? __free_pages+0x88/0xb0
[   41.160850]  ? kfree+0x360/0x3e0
[   41.160857]  dc_commit_state+0x337/0xac0 [amdgpu]
[   41.161135]  amdgpu_dm_atomic_commit_tail+0x5e3/0x2680 [amdgpu]

[How]
Pass in a pointer that contains nullified parameters instead of null
pointer.

Fixes: 405bb9eea36a ("drm/amd/display: Implement DTBCLK ref switching on dcn32")
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c  | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 631a8a2f9fc37..e7944c8811484 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2191,15 +2191,18 @@ static void dce110_setup_audio_dto(
 			build_audio_output(context, pipe_ctx, &audio_output);
 
 			if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
-				/* disable audio DTBCLK DTO */
-				dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
-					dc->res_pool->dccg, 0);
+				struct dtbclk_dto_params dto_params = {0};
 
 				pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
 						pipe_ctx->stream_res.audio,
 						pipe_ctx->stream->signal,
 						&audio_output.crtc_info,
 						&audio_output.pll_info);
+
+				/* disable audio DTBCLK DTO */
+				dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
+					dc->res_pool->dccg, &dto_params);
+
 			} else
 				pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
 					pipe_ctx->stream_res.audio,
-- 
GitLab


From 87d6b28e4a753f4a0572a695fcee094510dc6519 Mon Sep 17 00:00:00 2001
From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Date: Wed, 1 Jun 2022 10:39:37 -0400
Subject: [PATCH 0335/1731] drm/amd/display: Reduce frame size in the bouding
 box for DCN301

GCC throw warnings for the function dcn301_fpu_update_bw_bounding_box
due to its frame size that looks like this:

 error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]

For fixing this issue I dropped an intermadiate variable.

Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Hamza Mahfooz <hamza.mahfooz@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../amd/display/dc/dml/dcn301/dcn301_fpu.c    | 30 ++++++++-----------
 1 file changed, 13 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
index 0a7a338649731..62cf283d9f410 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
@@ -249,7 +249,6 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
 {
 	struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool);
 	struct clk_limit_table *clk_table = &bw_params->clk_table;
-	struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
 	unsigned int i, closest_clk_lvl;
 	int j;
 
@@ -271,24 +270,21 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
 				}
 			}
 
-			clock_limits[i].state = i;
-			clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
-			clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
-			clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
-			clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
-
-			clock_limits[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
-			clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
-			clock_limits[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
-			clock_limits[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
-			clock_limits[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
-			clock_limits[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
-			clock_limits[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+			dcn3_01_soc.clock_limits[i].state = i;
+			dcn3_01_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+			dcn3_01_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+			dcn3_01_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
+			dcn3_01_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
+
+			dcn3_01_soc.clock_limits[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
+			dcn3_01_soc.clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
+			dcn3_01_soc.clock_limits[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
+			dcn3_01_soc.clock_limits[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
+			dcn3_01_soc.clock_limits[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
+			dcn3_01_soc.clock_limits[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
+			dcn3_01_soc.clock_limits[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
 		}
 
-		for (i = 0; i < clk_table->num_entries; i++)
-			dcn3_01_soc.clock_limits[i] = clock_limits[i];
-
 		if (clk_table->num_entries) {
 			dcn3_01_soc.num_states = clk_table->num_entries;
 			/* duplicate last level */
-- 
GitLab


From 284498206f31e655fb61b1e08d0506dccbffe55f Mon Sep 17 00:00:00 2001
From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Date: Wed, 1 Jun 2022 10:52:06 -0400
Subject: [PATCH 0336/1731] drm/amd/display: Reduce frame size in the bouding
 box for DCN31/316

GCC throw warnings for the function dcn31_update_bw_bounding_box and
dcn316_update_bw_bounding_box due to its frame size that looks like
this:

 error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]

For fixing this issue I dropped an intermadiate variable.

Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Hamza Mahfooz <hamza.mahfooz@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../drm/amd/display/dc/dml/dcn31/dcn31_fpu.c  | 58 +++++++++----------
 1 file changed, 26 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
index 1b02f0ebe957d..6da7029232269 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
@@ -575,7 +575,6 @@ void dcn31_calculate_wm_and_dlg_fp(
 void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
 {
 	struct clk_limit_table *clk_table = &bw_params->clk_table;
-	struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
 	unsigned int i, closest_clk_lvl;
 	int j;
 
@@ -608,29 +607,27 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
 				}
 			}
 
-			clock_limits[i].state = i;
+			dcn3_1_soc.clock_limits[i].state = i;
 
 			/* Clocks dependent on voltage level. */
-			clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
-			clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
-			clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
-			clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
+			dcn3_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+			dcn3_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+			dcn3_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
+			dcn3_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
 
 			/* Clocks independent of voltage level. */
-			clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
+			dcn3_1_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
 				dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
 
-			clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
+			dcn3_1_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
 				dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
 
-			clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
-			clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
-			clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
-			clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
-			clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+			dcn3_1_soc.clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
+			dcn3_1_soc.clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
+			dcn3_1_soc.clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
+			dcn3_1_soc.clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
+			dcn3_1_soc.clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
 		}
-		for (i = 0; i < clk_table->num_entries; i++)
-			dcn3_1_soc.clock_limits[i] = clock_limits[i];
 		if (clk_table->num_entries) {
 			dcn3_1_soc.num_states = clk_table->num_entries;
 		}
@@ -702,7 +699,6 @@ void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
 void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
 {
 	struct clk_limit_table *clk_table = &bw_params->clk_table;
-	struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
 	unsigned int i, closest_clk_lvl;
 	int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
 	int j;
@@ -740,34 +736,32 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
 				closest_clk_lvl = dcn3_16_soc.num_states - 1;
 			}
 
-			clock_limits[i].state = i;
+			dcn3_16_soc.clock_limits[i].state = i;
 
 			/* Clocks dependent on voltage level. */
-			clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+			dcn3_16_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
 			if (clk_table->num_entries == 1 &&
-				clock_limits[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
+				dcn3_16_soc.clock_limits[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
 				/*SMU fix not released yet*/
-				clock_limits[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
+				dcn3_16_soc.clock_limits[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
 			}
-			clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
-			clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
-			clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
+			dcn3_16_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+			dcn3_16_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
+			dcn3_16_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
 
 			/* Clocks independent of voltage level. */
-			clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
+			dcn3_16_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
 				dcn3_16_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
 
-			clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
+			dcn3_16_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
 				dcn3_16_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
 
-			clock_limits[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
-			clock_limits[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
-			clock_limits[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
-			clock_limits[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
-			clock_limits[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+			dcn3_16_soc.clock_limits[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
+			dcn3_16_soc.clock_limits[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
+			dcn3_16_soc.clock_limits[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
+			dcn3_16_soc.clock_limits[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
+			dcn3_16_soc.clock_limits[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
 		}
-		for (i = 0; i < clk_table->num_entries; i++)
-			dcn3_16_soc.clock_limits[i] = clock_limits[i];
 		if (clk_table->num_entries) {
 			dcn3_16_soc.num_states = clk_table->num_entries;
 		}
-- 
GitLab


From c4d7738c9efc81a4f0364da1e673ab1b1cf91735 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Tue, 24 May 2022 09:57:49 -0400
Subject: [PATCH 0337/1731] drm/amdgpu: simplify amdgpu_ucode_get_load_type()

This is the same as the default case, so drop the extra
logic.

Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 20 --------------------
 1 file changed, 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index ffa4c0d207db6..c312577df596f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -486,26 +486,6 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
 	case CHIP_POLARIS12:
 	case CHIP_VEGAM:
 		return AMDGPU_FW_LOAD_SMU;
-	case CHIP_VEGA10:
-	case CHIP_RAVEN:
-	case CHIP_VEGA12:
-	case CHIP_VEGA20:
-	case CHIP_ARCTURUS:
-	case CHIP_RENOIR:
-	case CHIP_NAVI10:
-	case CHIP_NAVI14:
-	case CHIP_NAVI12:
-	case CHIP_SIENNA_CICHLID:
-	case CHIP_NAVY_FLOUNDER:
-	case CHIP_VANGOGH:
-	case CHIP_DIMGREY_CAVEFISH:
-	case CHIP_ALDEBARAN:
-	case CHIP_BEIGE_GOBY:
-	case CHIP_YELLOW_CARP:
-		if (!load_type)
-			return AMDGPU_FW_LOAD_DIRECT;
-		else
-			return AMDGPU_FW_LOAD_PSP;
 	case CHIP_CYAN_SKILLFISH:
 		if (!(load_type &&
 		      adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2))
-- 
GitLab


From feb54650bae25f2a2adfc493e3e254e7c27a3fba Mon Sep 17 00:00:00 2001
From: Xiaohui Zhang <xiaohuizhang@ruc.edu.cn>
Date: Tue, 7 Jun 2022 23:36:31 +0800
Subject: [PATCH 0338/1731] drm/radeon: integer overflow in
 radeon_mode_dumb_create()

Similar to the handling of amdgpu_mode_dumb_create in commit 54ef0b5461c0
("drm/amdgpu: integer overflow in amdgpu_mode_dumb_create()"),
we thought a patch might be needed here as well.

args->size is a u64.  arg->pitch and args->height are u32.  The
multiplication will overflow instead of using the high 32 bits as
intended.

Signed-off-by: Xiaohui Zhang <xiaohuizhang@ruc.edu.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/radeon/radeon_gem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index 8c01a7f0e0270..84843b3b3aef4 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -833,7 +833,7 @@ int radeon_mode_dumb_create(struct drm_file *file_priv,
 
 	args->pitch = radeon_align_pitch(rdev, args->width,
 					 DIV_ROUND_UP(args->bpp, 8), 0);
-	args->size = args->pitch * args->height;
+	args->size = (u64)args->pitch * args->height;
 	args->size = ALIGN(args->size, PAGE_SIZE);
 
 	r = radeon_gem_object_create(rdev, args->size, 0,
-- 
GitLab


From 0f28cca87e9afc22280c44d378d2a6e249933977 Mon Sep 17 00:00:00 2001
From: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
Date: Thu, 26 May 2022 14:21:22 -0500
Subject: [PATCH 0339/1731] drm/amdkfd: Extend KFD device topology to surface
 peer-to-peer links

Extend KFD device topology to surface peer-to-peer links among
GPU devices connected over PCIe or xGMI. Enabling HSA_AMD_P2P is
REQUIRED to surface peer-to-peer links.

Prior to this KFD did not expose to user mode any P2P links or
indirect links that go over two or more direct hops. Old versions
of the Thunk used to make up their own P2P and indirect links without
the information about peer-accessibility and chipset support available
to the kernel mode driver. In this patch we expose P2P links in a new
sysfs directory to provide more reliable P2P link information to user
mode.

Old versions of the Thunk will continue to work as before and ignore
the new directory. This avoids conflicts between P2P links exposed by
KFD and P2P links created by the Thunk itself. New versions of the Thunk
will use only the P2P links provided in the new p2p_links directory, if
it exists, or fall back to the old code path on older KFDs that don't
expose p2p_links.

Signed-off-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 319 +++++++++++++++++++++-
 drivers/gpu/drm/amd/amdkfd/kfd_topology.h |   3 +
 2 files changed, 320 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 8d50d207cf663..3e240b22ec912 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -40,6 +40,7 @@
 #include "kfd_svm.h"
 #include "amdgpu_amdkfd.h"
 #include "amdgpu_ras.h"
+#include "amdgpu.h"
 
 /* topology_device_list - Master list of all topology devices */
 static struct list_head topology_device_list;
@@ -148,6 +149,7 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev)
 	struct kfd_mem_properties *mem;
 	struct kfd_cache_properties *cache;
 	struct kfd_iolink_properties *iolink;
+	struct kfd_iolink_properties *p2plink;
 	struct kfd_perf_properties *perf;
 
 	list_del(&dev->list);
@@ -173,6 +175,13 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev)
 		kfree(iolink);
 	}
 
+	while (dev->p2p_link_props.next != &dev->p2p_link_props) {
+		p2plink = container_of(dev->p2p_link_props.next,
+				struct kfd_iolink_properties, list);
+		list_del(&p2plink->list);
+		kfree(p2plink);
+	}
+
 	while (dev->perf_props.next != &dev->perf_props) {
 		perf = container_of(dev->perf_props.next,
 				struct kfd_perf_properties, list);
@@ -214,6 +223,7 @@ struct kfd_topology_device *kfd_create_topology_device(
 	INIT_LIST_HEAD(&dev->mem_props);
 	INIT_LIST_HEAD(&dev->cache_props);
 	INIT_LIST_HEAD(&dev->io_link_props);
+	INIT_LIST_HEAD(&dev->p2p_link_props);
 	INIT_LIST_HEAD(&dev->perf_props);
 
 	list_add_tail(&dev->list, device_list);
@@ -465,6 +475,8 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr,
 			      dev->node_props.caches_count);
 	sysfs_show_32bit_prop(buffer, offs, "io_links_count",
 			      dev->node_props.io_links_count);
+	sysfs_show_32bit_prop(buffer, offs, "p2p_links_count",
+			      dev->node_props.p2p_links_count);
 	sysfs_show_32bit_prop(buffer, offs, "cpu_core_id_base",
 			      dev->node_props.cpu_core_id_base);
 	sysfs_show_32bit_prop(buffer, offs, "simd_id_base",
@@ -568,6 +580,7 @@ static void kfd_remove_sysfs_file(struct kobject *kobj, struct attribute *attr)
 
 static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev)
 {
+	struct kfd_iolink_properties *p2plink;
 	struct kfd_iolink_properties *iolink;
 	struct kfd_cache_properties *cache;
 	struct kfd_mem_properties *mem;
@@ -585,6 +598,18 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev)
 		dev->kobj_iolink = NULL;
 	}
 
+	if (dev->kobj_p2plink) {
+		list_for_each_entry(p2plink, &dev->p2p_link_props, list)
+			if (p2plink->kobj) {
+				kfd_remove_sysfs_file(p2plink->kobj,
+							&p2plink->attr);
+				p2plink->kobj = NULL;
+			}
+		kobject_del(dev->kobj_p2plink);
+		kobject_put(dev->kobj_p2plink);
+		dev->kobj_p2plink = NULL;
+	}
+
 	if (dev->kobj_cache) {
 		list_for_each_entry(cache, &dev->cache_props, list)
 			if (cache->kobj) {
@@ -631,6 +656,7 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev)
 static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev,
 		uint32_t id)
 {
+	struct kfd_iolink_properties *p2plink;
 	struct kfd_iolink_properties *iolink;
 	struct kfd_cache_properties *cache;
 	struct kfd_mem_properties *mem;
@@ -668,6 +694,10 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev,
 	if (!dev->kobj_iolink)
 		return -ENOMEM;
 
+	dev->kobj_p2plink = kobject_create_and_add("p2p_links", dev->kobj_node);
+	if (!dev->kobj_p2plink)
+		return -ENOMEM;
+
 	dev->kobj_perf = kobject_create_and_add("perf", dev->kobj_node);
 	if (!dev->kobj_perf)
 		return -ENOMEM;
@@ -757,6 +787,27 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev,
 		i++;
 	}
 
+	i = 0;
+	list_for_each_entry(p2plink, &dev->p2p_link_props, list) {
+		p2plink->kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
+		if (!p2plink->kobj)
+			return -ENOMEM;
+		ret = kobject_init_and_add(p2plink->kobj, &iolink_type,
+				dev->kobj_p2plink, "%d", i);
+		if (ret < 0) {
+			kobject_put(p2plink->kobj);
+			return ret;
+		}
+
+		p2plink->attr.name = "properties";
+		p2plink->attr.mode = KFD_SYSFS_FILE_MODE;
+		sysfs_attr_init(&iolink->attr);
+		ret = sysfs_create_file(p2plink->kobj, &p2plink->attr);
+		if (ret < 0)
+			return ret;
+		i++;
+	}
+
 	/* All hardware blocks have the same number of attributes. */
 	num_attrs = ARRAY_SIZE(perf_attr_iommu);
 	list_for_each_entry(perf, &dev->perf_props, list) {
@@ -1145,6 +1196,7 @@ static struct kfd_topology_device *kfd_assign_gpu(struct kfd_dev *gpu)
 	struct kfd_mem_properties *mem;
 	struct kfd_cache_properties *cache;
 	struct kfd_iolink_properties *iolink;
+	struct kfd_iolink_properties *p2plink;
 
 	down_write(&topology_lock);
 	list_for_each_entry(dev, &topology_device_list, list) {
@@ -1165,6 +1217,8 @@ static struct kfd_topology_device *kfd_assign_gpu(struct kfd_dev *gpu)
 				cache->gpu = dev->gpu;
 			list_for_each_entry(iolink, &dev->io_link_props, list)
 				iolink->gpu = dev->gpu;
+			list_for_each_entry(p2plink, &dev->p2p_link_props, list)
+				p2plink->gpu = dev->gpu;
 			break;
 		}
 	}
@@ -1287,6 +1341,250 @@ static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev)
 			kfd_set_iolink_non_coherent(peer_dev, link, inbound_link);
 		}
 	}
+
+	/* Create indirect links so apply flags setting to all */
+	list_for_each_entry(link, &dev->p2p_link_props, list) {
+		link->flags = CRAT_IOLINK_FLAGS_ENABLED;
+		kfd_set_iolink_no_atomics(dev, NULL, link);
+		peer_dev = kfd_topology_device_by_proximity_domain(
+				link->node_to);
+
+		if (!peer_dev)
+			continue;
+
+		list_for_each_entry(inbound_link, &peer_dev->p2p_link_props,
+									list) {
+			if (inbound_link->node_to != link->node_from)
+				continue;
+
+			inbound_link->flags = CRAT_IOLINK_FLAGS_ENABLED;
+			kfd_set_iolink_no_atomics(peer_dev, dev, inbound_link);
+			kfd_set_iolink_non_coherent(peer_dev, link, inbound_link);
+		}
+	}
+}
+
+static int kfd_build_p2p_node_entry(struct kfd_topology_device *dev,
+				struct kfd_iolink_properties *p2plink)
+{
+	int ret;
+
+	p2plink->kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
+	if (!p2plink->kobj)
+		return -ENOMEM;
+
+	ret = kobject_init_and_add(p2plink->kobj, &iolink_type,
+			dev->kobj_p2plink, "%d", dev->node_props.p2p_links_count - 1);
+	if (ret < 0) {
+		kobject_put(p2plink->kobj);
+		return ret;
+	}
+
+	p2plink->attr.name = "properties";
+	p2plink->attr.mode = KFD_SYSFS_FILE_MODE;
+	sysfs_attr_init(&p2plink->attr);
+	ret = sysfs_create_file(p2plink->kobj, &p2plink->attr);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static int kfd_create_indirect_link_prop(struct kfd_topology_device *kdev, int gpu_node)
+{
+	struct kfd_iolink_properties *props = NULL, *props2 = NULL;
+	struct kfd_iolink_properties *gpu_link, *cpu_link;
+	struct kfd_topology_device *cpu_dev;
+	int ret = 0;
+	int i, num_cpu;
+
+	num_cpu = 0;
+	list_for_each_entry(cpu_dev, &topology_device_list, list) {
+		if (cpu_dev->gpu)
+			break;
+		num_cpu++;
+	}
+
+	gpu_link = list_first_entry(&kdev->io_link_props,
+					struct kfd_iolink_properties, list);
+	if (!gpu_link)
+		return -ENOMEM;
+
+	for (i = 0; i < num_cpu; i++) {
+		/* CPU <--> GPU */
+		if (gpu_link->node_to == i)
+			continue;
+
+		/* find CPU <-->  CPU links */
+		cpu_dev = kfd_topology_device_by_proximity_domain(i);
+		if (cpu_dev) {
+			list_for_each_entry(cpu_link,
+					&cpu_dev->io_link_props, list) {
+				if (cpu_link->node_to == gpu_link->node_to)
+					break;
+			}
+		}
+
+		if (cpu_link->node_to != gpu_link->node_to)
+			return -ENOMEM;
+
+		/* CPU <--> CPU <--> GPU, GPU node*/
+		props = kfd_alloc_struct(props);
+		if (!props)
+			return -ENOMEM;
+
+		memcpy(props, gpu_link, sizeof(struct kfd_iolink_properties));
+		props->weight = gpu_link->weight + cpu_link->weight;
+		props->min_latency = gpu_link->min_latency + cpu_link->min_latency;
+		props->max_latency = gpu_link->max_latency + cpu_link->max_latency;
+		props->min_bandwidth = min(gpu_link->min_bandwidth, cpu_link->min_bandwidth);
+		props->max_bandwidth = min(gpu_link->max_bandwidth, cpu_link->max_bandwidth);
+
+		props->node_from = gpu_node;
+		props->node_to = i;
+		kdev->node_props.p2p_links_count++;
+		list_add_tail(&props->list, &kdev->p2p_link_props);
+		ret = kfd_build_p2p_node_entry(kdev, props);
+		if (ret < 0)
+			return ret;
+
+		/* for small Bar, no CPU --> GPU in-direct links */
+		if (kfd_dev_is_large_bar(kdev->gpu)) {
+			/* CPU <--> CPU <--> GPU, CPU node*/
+			props2 = kfd_alloc_struct(props2);
+			if (!props2)
+				return -ENOMEM;
+
+			memcpy(props2, props, sizeof(struct kfd_iolink_properties));
+			props2->node_from = i;
+			props2->node_to = gpu_node;
+			props2->kobj = NULL;
+			cpu_dev->node_props.p2p_links_count++;
+			list_add_tail(&props2->list, &cpu_dev->p2p_link_props);
+			ret = kfd_build_p2p_node_entry(cpu_dev, props2);
+			if (ret < 0)
+				return ret;
+		}
+	}
+	return ret;
+}
+
+#if defined(CONFIG_HSA_AMD_P2P)
+static int kfd_add_peer_prop(struct kfd_topology_device *kdev,
+		struct kfd_topology_device *peer, int from, int to)
+{
+	struct kfd_iolink_properties *props = NULL;
+	struct kfd_iolink_properties *iolink1, *iolink2, *iolink3;
+	struct kfd_topology_device *cpu_dev;
+	int ret = 0;
+
+	if (!amdgpu_device_is_peer_accessible(
+				kdev->gpu->adev,
+				peer->gpu->adev))
+		return ret;
+
+	iolink1 = list_first_entry(&kdev->io_link_props,
+							struct kfd_iolink_properties, list);
+	if (!iolink1)
+		return -ENOMEM;
+
+	iolink2 = list_first_entry(&peer->io_link_props,
+							struct kfd_iolink_properties, list);
+	if (!iolink2)
+		return -ENOMEM;
+
+	props = kfd_alloc_struct(props);
+	if (!props)
+		return -ENOMEM;
+
+	memcpy(props, iolink1, sizeof(struct kfd_iolink_properties));
+
+	props->weight = iolink1->weight + iolink2->weight;
+	props->min_latency = iolink1->min_latency + iolink2->min_latency;
+	props->max_latency = iolink1->max_latency + iolink2->max_latency;
+	props->min_bandwidth = min(iolink1->min_bandwidth, iolink2->min_bandwidth);
+	props->max_bandwidth = min(iolink2->max_bandwidth, iolink2->max_bandwidth);
+
+	if (iolink1->node_to != iolink2->node_to) {
+		/* CPU->CPU  link*/
+		cpu_dev = kfd_topology_device_by_proximity_domain(iolink1->node_to);
+		if (cpu_dev) {
+			list_for_each_entry(iolink3, &cpu_dev->io_link_props, list)
+				if (iolink3->node_to == iolink2->node_to)
+					break;
+
+			props->weight += iolink3->weight;
+			props->min_latency += iolink3->min_latency;
+			props->max_latency += iolink3->max_latency;
+			props->min_bandwidth = min(props->min_bandwidth,
+							iolink3->min_bandwidth);
+			props->max_bandwidth = min(props->max_bandwidth,
+							iolink3->max_bandwidth);
+		} else {
+			WARN(1, "CPU node not found");
+		}
+	}
+
+	props->node_from = from;
+	props->node_to = to;
+	peer->node_props.p2p_links_count++;
+	list_add_tail(&props->list, &peer->p2p_link_props);
+	ret = kfd_build_p2p_node_entry(peer, props);
+
+	return ret;
+}
+#endif
+
+static int kfd_dev_create_p2p_links(void)
+{
+	struct kfd_topology_device *dev;
+	struct kfd_topology_device *new_dev;
+	uint32_t i, k;
+	int ret = 0;
+
+	k = 0;
+	list_for_each_entry(dev, &topology_device_list, list)
+		k++;
+	if (k < 2)
+		return 0;
+
+	new_dev = list_last_entry(&topology_device_list, struct kfd_topology_device, list);
+	if (WARN_ON(!new_dev->gpu))
+		return 0;
+
+	k--;
+	i = 0;
+
+	/* create in-direct links */
+	ret = kfd_create_indirect_link_prop(new_dev, k);
+	if (ret < 0)
+		goto out;
+
+	/* create p2p links */
+#if defined(CONFIG_HSA_AMD_P2P)
+	list_for_each_entry(dev, &topology_device_list, list) {
+		if (dev == new_dev)
+			break;
+		if (!dev->gpu || !dev->gpu->adev ||
+		    (dev->gpu->hive_id &&
+		     dev->gpu->hive_id == new_dev->gpu->hive_id))
+			goto next;
+
+		/* check if node(s) is/are peer accessible in one direction or bi-direction */
+		ret = kfd_add_peer_prop(new_dev, dev, i, k);
+		if (ret < 0)
+			goto out;
+
+		ret = kfd_add_peer_prop(dev, new_dev, k, i);
+		if (ret < 0)
+			goto out;
+next:
+		i++;
+	}
+#endif
+
+out:
+	return ret;
 }
 
 int kfd_topology_add_device(struct kfd_dev *gpu)
@@ -1305,7 +1603,6 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
 	INIT_LIST_HEAD(&temp_topology_device_list);
 
 	gpu_id = kfd_generate_gpu_id(gpu);
-
 	pr_debug("Adding new GPU (ID: 0x%x) to topology\n", gpu_id);
 
 	/* Check to see if this gpu device exists in the topology_device_list.
@@ -1362,6 +1659,8 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
 	dev->gpu_id = gpu_id;
 	gpu->id = gpu_id;
 
+	kfd_dev_create_p2p_links();
+
 	/* TODO: Move the following lines to function
 	 *	kfd_add_non_crat_information
 	 */
@@ -1507,7 +1806,7 @@ err:
 static void kfd_topology_update_io_links(int proximity_domain)
 {
 	struct kfd_topology_device *dev;
-	struct kfd_iolink_properties *iolink, *tmp;
+	struct kfd_iolink_properties *iolink, *p2plink, *tmp;
 
 	list_for_each_entry(dev, &topology_device_list, list) {
 		if (dev->proximity_domain > proximity_domain)
@@ -1529,6 +1828,22 @@ static void kfd_topology_update_io_links(int proximity_domain)
 					iolink->node_to--;
 			}
 		}
+
+		list_for_each_entry_safe(p2plink, tmp, &dev->p2p_link_props, list) {
+			/*
+			 * If there is a p2p link to the dev being deleted
+			 * then remove that p2p link also.
+			 */
+			if (p2plink->node_to == proximity_domain) {
+				list_del(&p2plink->list);
+				dev->node_props.p2p_links_count--;
+			} else {
+				if (p2plink->node_from > proximity_domain)
+					p2plink->node_from--;
+				if (p2plink->node_to > proximity_domain)
+					p2plink->node_to--;
+			}
+		}
 	}
 }
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
index 4f80d2ea1000f..2fb5664e10411 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
@@ -38,6 +38,7 @@ struct kfd_node_properties {
 	uint32_t mem_banks_count;
 	uint32_t caches_count;
 	uint32_t io_links_count;
+	uint32_t p2p_links_count;
 	uint32_t cpu_core_id_base;
 	uint32_t simd_id_base;
 	uint32_t capability;
@@ -131,12 +132,14 @@ struct kfd_topology_device {
 	struct list_head		cache_props;
 	uint32_t			io_link_count;
 	struct list_head		io_link_props;
+	struct list_head		p2p_link_props;
 	struct list_head		perf_props;
 	struct kfd_dev			*gpu;
 	struct kobject			*kobj_node;
 	struct kobject			*kobj_mem;
 	struct kobject			*kobj_cache;
 	struct kobject			*kobj_iolink;
+	struct kobject			*kobj_p2plink;
 	struct kobject			*kobj_perf;
 	struct attribute		attr_gpuid;
 	struct attribute		attr_name;
-- 
GitLab


From cac3bfcaedbf4d5c93cabaa7882f243099afb8ab Mon Sep 17 00:00:00 2001
From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Date: Wed, 1 Jun 2022 10:57:33 -0400
Subject: [PATCH 0340/1731] drm/amd/display: Reduce frame size in the bouding
 box for DCN21

GCC throw warnings for the function dcn21_update_bw_bounding_box and
dcn316_update_bw_bounding_box due to its frame size that looks like
this:

 error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]

For fixing this issue I dropped an intermadiate variable.

Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Hamza Mahfooz <hamza.mahfooz@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c  | 29 +++++++++----------
 1 file changed, 13 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index d9cc178f6980e..c2fec0d85da42 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -2004,7 +2004,6 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
 {
 	struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
 	struct clk_limit_table *clk_table = &bw_params->clk_table;
-	struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
 	unsigned int i, closest_clk_lvl = 0, k = 0;
 	int j;
 
@@ -2017,7 +2016,7 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
 	ASSERT(clk_table->num_entries);
 	/* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */
 	for (i = 0; i < dcn2_1_soc.num_states + 1; i++) {
-		clock_limits[i] = dcn2_1_soc.clock_limits[i];
+		dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i];
 	}
 
 	for (i = 0; i < clk_table->num_entries; i++) {
@@ -2033,24 +2032,22 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
 		if (i == 1)
 			k++;
 
-		clock_limits[k].state = k;
-		clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
-		clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
-		clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
-		clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
+		dcn2_1_soc.clock_limits[k].state = k;
+		dcn2_1_soc.clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+		dcn2_1_soc.clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+		dcn2_1_soc.clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
+		dcn2_1_soc.clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
 
-		clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
-		clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
-		clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
-		clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
-		clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
-		clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
-		clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+		dcn2_1_soc.clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
+		dcn2_1_soc.clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
+		dcn2_1_soc.clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
+		dcn2_1_soc.clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
+		dcn2_1_soc.clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
+		dcn2_1_soc.clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
+		dcn2_1_soc.clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
 
 		k++;
 	}
-	for (i = 0; i < clk_table->num_entries + 1; i++)
-		dcn2_1_soc.clock_limits[i] = clock_limits[i];
 	if (clk_table->num_entries) {
 		dcn2_1_soc.num_states = clk_table->num_entries + 1;
 		/* fill in min DF PState */
-- 
GitLab


From 4e2d10443580d934188f226f48eda7d650711e03 Mon Sep 17 00:00:00 2001
From: Felix Kuehling <Felix.Kuehling@amd.com>
Date: Tue, 31 May 2022 10:35:53 -0400
Subject: [PATCH 0341/1731] drm/amdkfd: Document and fix GTT BO kmap API

Removed an unused parameter from two functions and added kernel-doc
comments.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h    |  7 ++---
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 28 ++++++++++++++++---
 drivers/gpu/drm/amd/amdkfd/kfd_events.c       |  5 ++--
 drivers/gpu/drm/amd/amdkfd/kfd_process.c      |  6 ++--
 4 files changed, 32 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 5c00ea1df21cc..bbe7d81bb0df8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -280,10 +280,9 @@ int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
 		struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv);
 int amdgpu_amdkfd_gpuvm_sync_memory(
 		struct amdgpu_device *adev, struct kgd_mem *mem, bool intr);
-int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct amdgpu_device *adev,
-		struct kgd_mem *mem, void **kptr, uint64_t *size);
-void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct amdgpu_device *adev,
-		struct kgd_mem *mem);
+int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
+					     void **kptr, uint64_t *size);
+void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem);
 
 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,
 					    struct dma_fence **ef);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 9798551900314..f386b0d256d25 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -2083,8 +2083,21 @@ int amdgpu_amdkfd_gpuvm_sync_memory(
 	return ret;
 }
 
-int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct amdgpu_device *adev,
-		struct kgd_mem *mem, void **kptr, uint64_t *size)
+/** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Map a GTT BO for kernel CPU access
+ *
+ * @mem: Buffer object to be mapped for CPU access
+ * @kptr[out]: pointer in kernel CPU address space
+ * @size[out]: size of the buffer
+ *
+ * Pins the BO and maps it for kernel CPU access. The eviction fence is removed
+ * from the BO, since pinned BOs cannot be evicted. The bo must remain on the
+ * validate_list, so the GPU mapping can be restored after a page table was
+ * evicted.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
+					     void **kptr, uint64_t *size)
 {
 	int ret;
 	struct amdgpu_bo *bo = mem->bo;
@@ -2135,8 +2148,15 @@ bo_reserve_failed:
 	return ret;
 }
 
-void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct amdgpu_device *adev,
-						  struct kgd_mem *mem)
+/** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Unmap a GTT BO for kernel CPU access
+ *
+ * @mem: Buffer object to be unmapped for CPU access
+ *
+ * Removes the kernel CPU mapping and unpins the BO. It does not restore the
+ * eviction fence, so this function should only be used for cleanup before the
+ * BO is destroyed.
+ */
+void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem)
 {
 	struct amdgpu_bo *bo = mem->bo;
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
index 4df9c36146ba9..3942a56c28bbb 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
@@ -377,8 +377,7 @@ int kfd_kmap_event_page(struct kfd_process *p, uint64_t event_page_offset)
 		return -EINVAL;
 	}
 
-	err = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(kfd->adev,
-					mem, &kern_addr, &size);
+	err = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(mem, &kern_addr, &size);
 	if (err) {
 		pr_err("Failed to map event page to kernel\n");
 		return err;
@@ -387,7 +386,7 @@ int kfd_kmap_event_page(struct kfd_process *p, uint64_t event_page_offset)
 	err = kfd_event_page_set(p, kern_addr, size, event_page_offset);
 	if (err) {
 		pr_err("Failed to set event page\n");
-		amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(kfd->adev, mem);
+		amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(mem);
 		return err;
 	}
 	return err;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index e3d64ec8c3537..a13e60d48b735 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -693,7 +693,7 @@ static void kfd_process_free_gpuvm(struct kgd_mem *mem,
 	struct kfd_dev *dev = pdd->dev;
 
 	if (kptr) {
-		amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(dev->adev, mem);
+		amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(mem);
 		kptr = NULL;
 	}
 
@@ -733,7 +733,7 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd,
 	}
 
 	if (kptr) {
-		err = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(kdev->adev,
+		err = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(
 				(struct kgd_mem *)*mem, kptr, NULL);
 		if (err) {
 			pr_debug("Map GTT BO to kernel failed\n");
@@ -999,7 +999,7 @@ static void kfd_process_kunmap_signal_bo(struct kfd_process *p)
 	if (!mem)
 		goto out;
 
-	amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(kdev->adev, mem);
+	amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(mem);
 
 out:
 	mutex_unlock(&p->mutex);
-- 
GitLab


From 0381ac3ca2e727d4dfb7264d9416a8ba6bb6c18b Mon Sep 17 00:00:00 2001
From: Xiaohui Zhang <xiaohuizhang@ruc.edu.cn>
Date: Tue, 7 Jun 2022 23:19:33 +0800
Subject: [PATCH 0342/1731] drm/radeon: Initialize fences array entries in
 radeon_sa_bo_next_hole

Similar to the handling of amdgpu_sa_bo_next_hole in commit 6a15f3ff19a8
("drm/amdgpu: Initialize fences array entries in amdgpu_sa_bo_next_hole"),
we thought a patch might be needed here as well.

The entries were only initialized once in radeon_sa_bo_new. If a fence
wasn't signalled yet in the first radeon_sa_bo_next_hole call, but then
got signalled before a later radeon_sa_bo_next_hole call, it could
destroy the fence but leave its pointer in the array, resulting in
use-after-free in radeon_sa_bo_new.

Signed-off-by: Xiaohui Zhang <xiaohuizhang@ruc.edu.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/radeon/radeon_sa.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_sa.c b/drivers/gpu/drm/radeon/radeon_sa.c
index 310c322c71129..0981948bd9edc 100644
--- a/drivers/gpu/drm/radeon/radeon_sa.c
+++ b/drivers/gpu/drm/radeon/radeon_sa.c
@@ -267,6 +267,8 @@ static bool radeon_sa_bo_next_hole(struct radeon_sa_manager *sa_manager,
 	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 		struct radeon_sa_bo *sa_bo;
 
+		fences[i] = NULL;
+
 		if (list_empty(&sa_manager->flist[i])) {
 			continue;
 		}
@@ -332,10 +334,8 @@ int radeon_sa_bo_new(struct radeon_device *rdev,
 
 	spin_lock(&sa_manager->wq.lock);
 	do {
-		for (i = 0; i < RADEON_NUM_RINGS; ++i) {
-			fences[i] = NULL;
+		for (i = 0; i < RADEON_NUM_RINGS; ++i)
 			tries[i] = 0;
-		}
 
 		do {
 			radeon_sa_bo_try_free(sa_manager);
-- 
GitLab


From 851dd8625320fb626b6ab6399b2402fd84abcdfb Mon Sep 17 00:00:00 2001
From: ZhenGuo Yin <zhenguo.yin@amd.com>
Date: Mon, 6 Jun 2022 10:36:13 +0800
Subject: [PATCH 0343/1731] drm/amdgpu: fix scratch register access method in
 SRIOV

The scratch register should be accessed through MMIO instead of RLCG
in SRIOV, since it being used in RLCG register access function.

Fixes: d54762cc3e6a ("drm/amdgpu: nuke dynamic gfx scratch reg allocation")
Signed-off-by: ZhenGuo Yin <zhenguo.yin@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 797e90e8ce28b..abf2bf7f1a791 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3780,11 +3780,12 @@ static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
+	uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
 	uint32_t tmp = 0;
 	unsigned i;
 	int r;
 
-	WREG32_SOC15(GC, 0, mmSCRATCH_REG0, 0xCAFEDEAD);
+	WREG32(scratch, 0xCAFEDEAD);
 	r = amdgpu_ring_alloc(ring, 3);
 	if (r) {
 		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
@@ -3793,13 +3794,13 @@ static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
 	}
 
 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
-	amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0) -
+	amdgpu_ring_write(ring, scratch -
 			  PACKET3_SET_UCONFIG_REG_START);
 	amdgpu_ring_write(ring, 0xDEADBEEF);
 	amdgpu_ring_commit(ring);
 
 	for (i = 0; i < adev->usec_timeout; i++) {
-		tmp = RREG32_SOC15(GC, 0, mmSCRATCH_REG0);
+		tmp = RREG32(scratch);
 		if (tmp == 0xDEADBEEF)
 			break;
 		if (amdgpu_emu_mode == 1)
-- 
GitLab


From cde83d47482e2578432f9ce029748f4f0d029e9e Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Fri, 20 May 2022 16:18:07 +0800
Subject: [PATCH 0344/1731] drm/amd/pm: enable FW CTF feature for SMU 13.0.0

The new 78.40.0 PMFW has this feature supported.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 418480e0c0777..2ee17b3e8ac34 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -302,6 +302,8 @@ smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu,
 
 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT);
 
+	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT);
+
 	return 0;
 }
 
-- 
GitLab


From bb50bba9c6c741f5e359f009dde3b25f12a84e3d Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Mon, 23 May 2022 11:37:58 +0800
Subject: [PATCH 0345/1731] drm/amd/pm: drop unneeded thermal_controller_type
 check

As there is actually no direct dependence between them.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 6db10e49db7e9..0991c1ffe5251 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -1076,10 +1076,7 @@ int smu_v13_0_set_power_limit(struct smu_context *smu,
 
 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
 {
-	if (smu->smu_table.thermal_controller_type)
-		return amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
-
-	return 0;
+	return amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
 }
 
 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
-- 
GitLab


From 6f73d6762694c3e91c49e6708077a0de2a75f2f5 Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Wed, 25 May 2022 16:51:47 +0800
Subject: [PATCH 0346/1731] drm/amd/pm: optimize the interface for dpm feature
 status query

Drop extra CMN2ASIC_MAPPING_FEATURE transform. Also some cosmetic
fixes for better readability.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 26 ++++++++------------------
 1 file changed, 8 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 53cd62ccab5dc..15e4298c7cc83 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -682,16 +682,13 @@ static const char *smu_get_feature_name(struct smu_context *smu,
 size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
 				   char *buf)
 {
+	int8_t sort_feature[max(SMU_FEATURE_COUNT, SMU_FEATURE_MAX)];
 	uint64_t feature_mask;
-	int feature_index = 0;
+	int i, feature_index;
 	uint32_t count = 0;
-	int8_t sort_feature[SMU_FEATURE_COUNT];
 	size_t size = 0;
-	int ret = 0, i;
-	int feature_id;
 
-	ret = __smu_get_enabled_features(smu, &feature_mask);
-	if (ret)
+	if (__smu_get_enabled_features(smu, &feature_mask))
 		return 0;
 
 	size =  sysfs_emit_at(buf, size, "features high: 0x%08x low: 0x%08x\n",
@@ -712,22 +709,15 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
 	size += sysfs_emit_at(buf, size, "%-2s. %-20s  %-3s : %-s\n",
 			"No", "Feature", "Bit", "State");
 
-	for (i = 0; i < SMU_FEATURE_COUNT; i++) {
-		if (sort_feature[i] < 0)
-			continue;
-
-		/* convert to asic spcific feature ID */
-		feature_id = smu_cmn_to_asic_specific_index(smu,
-							    CMN2ASIC_MAPPING_FEATURE,
-							    sort_feature[i]);
-		if (feature_id < 0)
+	for (feature_index = 0; feature_index < SMU_FEATURE_MAX; feature_index++) {
+		if (sort_feature[feature_index] < 0)
 			continue;
 
 		size += sysfs_emit_at(buf, size, "%02d. %-20s (%2d) : %s\n",
 				count++,
-				smu_get_feature_name(smu, sort_feature[i]),
-				i,
-				!!test_bit(feature_id, (unsigned long *)&feature_mask) ?
+				smu_get_feature_name(smu, sort_feature[feature_index]),
+				feature_index,
+				!!test_bit(feature_index, (unsigned long *)&feature_mask) ?
 				"enabled" : "disabled");
 	}
 
-- 
GitLab


From 62f8f5c3bfc2968461b0a74f0e393325bec16c69 Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Thu, 28 Apr 2022 16:51:04 +0800
Subject: [PATCH 0347/1731] drm/amdgpu: enable ASPM support for PCIE
 7.4.0/7.6.0

Enable ASPM support for PCIE 7.4.0 and 7.6.0.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h           |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c |   1 +
 drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c        | 116 ++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/soc21.c            |   7 +-
 .../include/asic_reg/nbio/nbio_4_3_0_offset.h |   2 +
 .../asic_reg/nbio/nbio_4_3_0_sh_mask.h        |   1 +
 6 files changed, 125 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 47bcf86cd0f3f..7971d9208ecf2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -670,6 +670,7 @@ enum amd_hw_ip_block_type {
 	RSMU_HWIP,
 	XGMI_HWIP,
 	DCI_HWIP,
+	PCIE_HWIP,
 	MAX_HWIP
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index b0811287f017f..1369a1b74929a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -194,6 +194,7 @@ static int hw_id_map[MAX_HWIP] = {
 	[UMC_HWIP]	= UMC_HWID,
 	[XGMI_HWIP]	= XGMI_HWID,
 	[DCI_HWIP]	= DCI_HWID,
+	[PCIE_HWIP]	= PCIE_HWID,
 };
 
 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
index ed31d133f07ae..233be735165aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
@@ -344,6 +344,121 @@ static u32 nbio_v4_3_get_rom_offset(struct amdgpu_device *adev)
 	return rom_offset;
 }
 
+#ifdef CONFIG_PCIEASPM
+static void nbio_v4_3_program_ltr(struct amdgpu_device *adev)
+{
+	uint32_t def, data;
+
+	def = RREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);
+	data = 0x35EB;
+	data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK;
+	data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2);
+	data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
+	if (adev->pdev->ltr_path)
+		data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
+	else
+		data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
+}
+#endif
+
+static void nbio_v4_3_program_aspm(struct amdgpu_device *adev)
+{
+#ifdef CONFIG_PCIEASPM
+	uint32_t def, data;
+
+	if (!(adev->ip_versions[PCIE_HWIP][0] == IP_VERSION(7, 4, 0)) &&
+	      !(adev->ip_versions[PCIE_HWIP][0] == IP_VERSION(7, 6, 0)))
+		return;
+
+	def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL);
+	data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
+	data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
+	data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL7);
+	data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL7, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3);
+	data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3);
+	data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK;
+	data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5);
+	data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
+	data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
+
+	WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001);
+
+	def = data = RREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2);
+	data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |
+		PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;
+	data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL4);
+	data |= PCIE_LC_CNTL4__LC_L1_POWERDOWN_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL4, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL);
+	data |= PCIE_LC_RXRECOVER_RXSTANDBY_CNTL__LC_RX_L0S_STANDBY_EN_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL, data);
+
+	nbio_v4_3_program_ltr(adev);
+
+	def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3);
+	data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;
+	data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5);
+	data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL);
+	data |= 0x0 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT;
+	data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
+	data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3);
+	data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3, data);
+#endif
+}
+
 const struct amdgpu_nbio_funcs nbio_v4_3_funcs = {
 	.get_hdp_flush_req_offset = nbio_v4_3_get_hdp_flush_req_offset,
 	.get_hdp_flush_done_offset = nbio_v4_3_get_hdp_flush_done_offset,
@@ -365,4 +480,5 @@ const struct amdgpu_nbio_funcs nbio_v4_3_funcs = {
 	.init_registers = nbio_v4_3_init_registers,
 	.remap_hdp_registers = nbio_v4_3_remap_hdp_registers,
 	.get_rom_offset = nbio_v4_3_get_rom_offset,
+	.program_aspm = nbio_v4_3_program_aspm,
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 57eaafb70d725..495848515edfa 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -386,11 +386,12 @@ static void soc21_pcie_gen3_enable(struct amdgpu_device *adev)
 
 static void soc21_program_aspm(struct amdgpu_device *adev)
 {
-
-	if (amdgpu_aspm == 0)
+	if (!amdgpu_device_should_use_aspm(adev))
 		return;
 
-	/* todo */
+	if (!(adev->flags & AMD_IS_APU) &&
+	    (adev->nbio.funcs->program_aspm))
+		adev->nbio.funcs->program_aspm(adev);
 }
 
 static void soc21_enable_doorbell_aperture(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_offset.h
index 53802d674e13e..4b489d64deaae 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_offset.h
@@ -6918,6 +6918,8 @@
 #define regPSWUSCFG0_SSID_CAP                                                                           0x2880031
 #define regPSWUSCFG0_SSID_CAP_BASE_IDX                                                                  5
 
+#define regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL                                                             0x2890102
+#define regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL_BASE_IDX                                                    5
 
 // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
 // base address: 0x10100000
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h
index f3cda48bfaeb3..d038fd915351c 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h
@@ -82045,5 +82045,6 @@
 #define BIF_CFG_DEV0_EPF3_1_RTR_DATA2__FLR_TIME_MASK                                                          0x00000FFFL
 #define BIF_CFG_DEV0_EPF3_1_RTR_DATA2__D3HOTD0_TIME_MASK                                                      0x00FFF000L
 
+#define PCIE_LC_RXRECOVER_RXSTANDBY_CNTL__LC_RX_L0S_STANDBY_EN_MASK                                           0x00010000L
 
 #endif
-- 
GitLab


From 1b3aa89550a2ce4f4af41e11162c5cc0b0b07b4f Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Tue, 24 May 2022 16:15:06 +0800
Subject: [PATCH 0348/1731] drm/amdgpu: avoid to perform undesired clockgating
 operation

Make sure the clockgating feature is supported before action.
Otherwise, the feature may be disabled unexpectedly on enablement
request.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
index 233be735165aa..982a89f841d56 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
@@ -240,8 +240,11 @@ static void nbio_v4_3_update_medium_grain_clock_gating(struct amdgpu_device *ade
 {
 	uint32_t def, data;
 
+	if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
+		return;
+
 	def = data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL);
-	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
+	if (enable) {
 		data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
 			 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
 			 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
@@ -266,9 +269,12 @@ static void nbio_v4_3_update_medium_grain_light_sleep(struct amdgpu_device *adev
 {
 	uint32_t def, data;
 
+	if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
+		return;
+
 	/* TODO: need update in future */
 	def = data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2);
-	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
+	if (enable) {
 		data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
 	} else {
 		data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
-- 
GitLab


From d7053e631e891698f7532712066014ca140c8ff3 Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Tue, 31 May 2022 14:52:20 +0800
Subject: [PATCH 0349/1731] drm/amd/pm: enable mode1 reset support for SMU
 13.0.0

Fulfill the interfaces for mode1 reset related.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h  |  2 ++
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c    | 11 ++++++++++
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 20 +++++++++++++++++++
 3 files changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index fe9c47c87abc9..ba6adf09bfc30 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -302,5 +302,7 @@ int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu);
 
 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu);
+
+int smu_v13_0_mode1_reset(struct smu_context *smu);
 #endif
 #endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 0991c1ffe5251..f9c36d2944481 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2411,3 +2411,14 @@ void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu)
 	smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
 	smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
 }
+
+int smu_v13_0_mode1_reset(struct smu_context *smu)
+{
+	int ret = 0;
+
+	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
+	if (!ret)
+		msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
+
+	return ret;
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 2ee17b3e8ac34..26fb72a588e78 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -117,6 +117,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] =
 	MSG_MAP(SetMGpuFanBoostLimitRpm,	PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
 	MSG_MAP(GetPptLimit,			PPSMC_MSG_GetPptLimit,                 0),
 	MSG_MAP(NotifyPowerSource,		PPSMC_MSG_NotifyPowerSource,           0),
+	MSG_MAP(Mode1Reset,			PPSMC_MSG_Mode1Reset,                  0),
 };
 
 static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {
@@ -1580,6 +1581,23 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu,
 					       NULL);
 }
 
+static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu)
+{
+	struct amdgpu_device *adev = smu->adev;
+	u32 smu_version;
+
+	/* SRIOV does not support SMU mode1 reset */
+	if (amdgpu_sriov_vf(adev))
+		return false;
+
+	/* PMFW support is available since 78.41 */
+	smu_cmn_get_smc_version(smu, NULL, &smu_version);
+	if (smu_version < 0x004e2900)
+		return false;
+
+	return true;
+}
+
 static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
 	.get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,
 	.set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,
@@ -1642,6 +1660,8 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
 	.baco_set_state = smu_v13_0_baco_set_state,
 	.baco_enter = smu_v13_0_baco_enter,
 	.baco_exit = smu_v13_0_baco_exit,
+	.mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported,
+	.mode1_reset = smu_v13_0_mode1_reset,
 };
 
 void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
-- 
GitLab


From da4d45b7da937dfbeb918b87c66a5bf9a3079ed8 Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Tue, 31 May 2022 15:13:24 +0800
Subject: [PATCH 0350/1731] drm/amd/pm: drop redundant declarations

Drop those redundant declarations in smu_v13_0.h.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 14 --------------
 1 file changed, 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index ba6adf09bfc30..a11d36db1b8a0 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -278,20 +278,6 @@ int smu_v13_0_run_btc(struct smu_context *smu);
 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
 				 bool enablement);
 
-int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
-			      bool enablement);
-
-bool smu_v13_0_baco_is_support(struct smu_context *smu);
-
-enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu);
-
-int smu_v13_0_baco_set_state(struct smu_context *smu,
-			     enum smu_baco_state state);
-
-int smu_v13_0_baco_enter(struct smu_context *smu);
-
-int smu_v13_0_baco_exit(struct smu_context *smu);
-
 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu);
 
 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
-- 
GitLab


From 26c763875e0c15921a0480e008e2be07665e7f56 Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Thu, 2 Jun 2022 11:34:10 +0800
Subject: [PATCH 0351/1731] drm/amd/pm: drop unneeded dpm features disablement
 for SMU 13.0.0/7

PMFW will handle that properly. Driver involvement may cause some
unexpected issues.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index ae595ee544dca..fb04d82f66e63 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1407,6 +1407,18 @@ static int smu_disable_dpms(struct smu_context *smu)
 		  (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
 		 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)));
 
+	/*
+	 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others)
+	 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues.
+	 */
+	switch (adev->ip_versions[MP1_HWIP][0]) {
+	case IP_VERSION(13, 0, 0):
+	case IP_VERSION(13, 0, 7):
+		return 0;
+	default:
+		break;
+	}
+
 	/*
 	 * For custom pptable uploading, skip the DPM features
 	 * disable process on Navi1x ASICs.
@@ -1444,7 +1456,6 @@ static int smu_disable_dpms(struct smu_context *smu)
 		case IP_VERSION(11, 0, 0):
 		case IP_VERSION(11, 0, 5):
 		case IP_VERSION(11, 0, 9):
-		case IP_VERSION(13, 0, 0):
 			return 0;
 		default:
 			break;
-- 
GitLab


From 8728df26dd24a63b24e4e5a6c847172add2fa149 Mon Sep 17 00:00:00 2001
From: Yifan Zhang <yifan1.zhang@amd.com>
Date: Fri, 3 Jun 2022 10:24:31 +0800
Subject: [PATCH 0352/1731] drm/amdgpu/mes: only invalid/prime icache when
 finish loading both pipe MES FWs.

invalid/prime icahce operation takes effect both pipes cuconrrently,
therefore CP_MES_IC_BASE_LO/HI and CP_MES_MDBASE_LO/HI both have to be
set before prime icache. Otherwise MES hardware gets garbage data in
above regsters and causes page fault

[  470.873200] amdgpu 0000:33:00.0: amdgpu: [gfxhub] page fault (src_id:0 ring:217 vmid:0 pasid:0, for process  pid 0 thread  pid 0)
[  470.873222] amdgpu 0000:33:00.0: amdgpu:   in page starting at address 0x000092cb89b00000 from client 10
[  470.873234] amdgpu 0000:33:00.0: amdgpu: GCVM_L2_PROTECTION_FAULT_STATUS:0x00000BB3
[  470.873242] amdgpu 0000:33:00.0: amdgpu:      Faulty UTCL2 client ID: CPC (0x5)
[  470.873247] amdgpu 0000:33:00.0: amdgpu:      MORE_FAULTS: 0x1
[  470.873251] amdgpu 0000:33:00.0: amdgpu:      WALKER_ERROR: 0x1
[  470.873256] amdgpu 0000:33:00.0: amdgpu:      PERMISSION_FAULTS: 0xb
[  470.873260] amdgpu 0000:33:00.0: amdgpu:      MAPPING_ERROR: 0x1
[  470.873264] amdgpu 0000:33:00.0: amdgpu:      RW: 0x0

Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 36 ++++++++++++++------------
 1 file changed, 20 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index fcf51947bb186..7eee004cf3ce3 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -541,7 +541,7 @@ static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)
 
 /* This function is for backdoor MES firmware */
 static int mes_v11_0_load_microcode(struct amdgpu_device *adev,
-				    enum admgpu_mes_pipe pipe)
+				    enum admgpu_mes_pipe pipe, bool prime_icache)
 {
 	int r;
 	uint32_t data;
@@ -593,16 +593,18 @@ static int mes_v11_0_load_microcode(struct amdgpu_device *adev,
 	/* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */
 	WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF);
 
-	/* invalidate ICACHE */
-	data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
-	data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
-	data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
-	WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
-
-	/* prime the ICACHE. */
-	data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
-	data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
-	WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
+	if (prime_icache) {
+		/* invalidate ICACHE */
+		data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
+		data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
+		data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
+		WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
+
+		/* prime the ICACHE. */
+		data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
+		data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
+		WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
+	}
 
 	soc21_grbm_select(adev, 0, 0, 0, 0);
 	mutex_unlock(&adev->srbm_mutex);
@@ -1044,17 +1046,19 @@ static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)
 	int r = 0;
 
 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
-		r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE);
+
+		r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false);
 		if (r) {
-			DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);
+			DRM_ERROR("failed to load MES fw, r=%d\n", r);
 			return r;
 		}
 
-		r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE);
+		r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true);
 		if (r) {
-			DRM_ERROR("failed to load MES fw, r=%d\n", r);
+			DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);
 			return r;
 		}
+
 	}
 
 	mes_v11_0_enable(adev, true);
@@ -1086,7 +1090,7 @@ static int mes_v11_0_hw_init(void *handle)
 	if (!adev->enable_mes_kiq) {
 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 			r = mes_v11_0_load_microcode(adev,
-					     AMDGPU_MES_SCHED_PIPE);
+					     AMDGPU_MES_SCHED_PIPE, true);
 			if (r) {
 				DRM_ERROR("failed to MES fw, r=%d\n", r);
 				return r;
-- 
GitLab


From 5d88cb162c9d70f8cb98030624b412b0f6f1c081 Mon Sep 17 00:00:00 2001
From: Mohammad Zafar Ziya <Mohammadzafar.ziya@amd.com>
Date: Tue, 7 Jun 2022 11:38:16 +0800
Subject: [PATCH 0353/1731] drm/amdgpu/jpeg2: Add jpeg vmid update under IB
 submit
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add jpeg vmid update under IB submit

Signed-off-by: Mohammad Zafar Ziya <Mohammadzafar.ziya@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 6 +++++-
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h | 1 +
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
index d2722adabd1ba..f3c1af5130abc 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
@@ -535,6 +535,10 @@ void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
 {
 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 
+	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JPEG_IH_CTRL_INTERNAL_OFFSET,
+		0, 0, PACKETJ_TYPE0));
+	amdgpu_ring_write(ring, (vmid << JPEG_IH_CTRL__IH_VMID__SHIFT));
+
 	amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,
 		0, 0, PACKETJ_TYPE0));
 	amdgpu_ring_write(ring, (vmid | (vmid << 4)));
@@ -768,7 +772,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {
 		8 + /* jpeg_v2_0_dec_ring_emit_vm_flush */
 		18 + 18 + /* jpeg_v2_0_dec_ring_emit_fence x2 vm fence */
 		8 + 16,
-	.emit_ib_size = 22, /* jpeg_v2_0_dec_ring_emit_ib */
+	.emit_ib_size = 24, /* jpeg_v2_0_dec_ring_emit_ib */
 	.emit_ib = jpeg_v2_0_dec_ring_emit_ib,
 	.emit_fence = jpeg_v2_0_dec_ring_emit_fence,
 	.emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h
index 1a03baa597557..654e43e83e2c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h
@@ -41,6 +41,7 @@
 #define mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET				0x4084
 #define mmUVD_JRBC_STATUS_INTERNAL_OFFSET				0x4089
 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET				0x401f
+#define mmUVD_JPEG_IH_CTRL_INTERNAL_OFFSET				0x4149
 
 #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR				0x18000
 
-- 
GitLab


From 9e68c3841390c43521d4fde6c51e91fcb2d4131f Mon Sep 17 00:00:00 2001
From: Kenneth Feng <kenneth.feng@amd.com>
Date: Tue, 12 Apr 2022 18:46:22 +0800
Subject: [PATCH 0354/1731] drm/amd/pm: add interface to deallocate
 power_context for smu_v13_0_7

add interface to deallocate power_context for smu_v13_0_7

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index bdea7bca3805c..7da42cae5d6ee 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1541,6 +1541,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
 	.load_microcode = smu_v13_0_load_microcode,
 	.init_smc_tables = smu_v13_0_7_init_smc_tables,
 	.init_power = smu_v13_0_init_power,
+	.fini_power = smu_v13_0_fini_power,
 	.check_fw_status = smu_v13_0_7_check_fw_status,
 	.setup_pptable = smu_v13_0_7_setup_pptable,
 	.check_fw_version = smu_v13_0_check_fw_version,
-- 
GitLab


From 5b644783396b2150eeccb9a079498cad5dff3c42 Mon Sep 17 00:00:00 2001
From: Kenneth Feng <kenneth.feng@amd.com>
Date: Wed, 8 Jun 2022 16:31:18 +0800
Subject: [PATCH 0355/1731] drm/amd/pm: enable BACO on smu_v13_0_7

enable BACO on smu_v13_0_7

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c            | 1 +
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 7 +++++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index fb04d82f66e63..f57710790b8cd 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1456,6 +1456,7 @@ static int smu_disable_dpms(struct smu_context *smu)
 		case IP_VERSION(11, 0, 0):
 		case IP_VERSION(11, 0, 5):
 		case IP_VERSION(11, 0, 9):
+		case IP_VERSION(13, 0, 7):
 			return 0;
 		default:
 			break;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 7da42cae5d6ee..dc614befcdf5b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -97,6 +97,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] =
 	MSG_MAP(UseDefaultPPTable,		PPSMC_MSG_UseDefaultPPTable,           0),
 	MSG_MAP(RunDcBtc,			PPSMC_MSG_RunDcBtc,                    0),
 	MSG_MAP(EnterBaco,			PPSMC_MSG_EnterBaco,                   0),
+	MSG_MAP(ExitBaco,           PPSMC_MSG_ExitBaco,        			   0),
 	MSG_MAP(SetSoftMinByFreq,		PPSMC_MSG_SetSoftMinByFreq,            1),
 	MSG_MAP(SetSoftMaxByFreq,		PPSMC_MSG_SetSoftMaxByFreq,            1),
 	MSG_MAP(SetHardMinByFreq,		PPSMC_MSG_SetHardMinByFreq,            1),
@@ -281,6 +282,7 @@ smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu,
 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT);
 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_PCC_DFLL_BIT);
 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT);
+	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT);
 
 	if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT);
@@ -1584,6 +1586,11 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
 	.set_tool_table_location = smu_v13_0_set_tool_table_location,
 	.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
 	.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
+	.baco_is_support = smu_v13_0_baco_is_support,
+	.baco_get_state = smu_v13_0_baco_get_state,
+	.baco_set_state = smu_v13_0_baco_set_state,
+	.baco_enter = smu_v13_0_baco_enter,
+	.baco_exit = smu_v13_0_baco_exit,
 };
 
 void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
-- 
GitLab


From 250195ff744f260c169f5427422b6f39c58cb883 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
Date: Fri, 3 Jun 2022 12:21:06 +0200
Subject: [PATCH 0356/1731] drm/amdgpu: fix limiting AV1 to the first instance
 on VCN3
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The job is not yet initialized here.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2037
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Tested-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Fixes: cdc7893fc93f ("drm/amdgpu: use job and ib structures directly in CS parsers")
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 3cabceee5f57a..39405f0db8241 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -1761,23 +1761,21 @@ static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = {
 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
 };
 
-static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p,
-				struct amdgpu_job *job)
+static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p)
 {
 	struct drm_gpu_scheduler **scheds;
 
 	/* The create msg must be in the first IB submitted */
-	if (atomic_read(&job->base.entity->fence_seq))
+	if (atomic_read(&p->entity->fence_seq))
 		return -EINVAL;
 
 	scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC]
 		[AMDGPU_RING_PRIO_DEFAULT].sched;
-	drm_sched_entity_modify_sched(job->base.entity, scheds, 1);
+	drm_sched_entity_modify_sched(p->entity, scheds, 1);
 	return 0;
 }
 
-static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job,
-			    uint64_t addr)
+static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr)
 {
 	struct ttm_operation_ctx ctx = { false, false };
 	struct amdgpu_bo_va_mapping *map;
@@ -1848,7 +1846,7 @@ static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job,
 		if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11)
 			continue;
 
-		r = vcn_v3_0_limit_sched(p, job);
+		r = vcn_v3_0_limit_sched(p);
 		if (r)
 			goto out;
 	}
@@ -1862,7 +1860,7 @@ static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
 					   struct amdgpu_job *job,
 					   struct amdgpu_ib *ib)
 {
-	struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched);
+	struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
 	uint32_t msg_lo = 0, msg_hi = 0;
 	unsigned i;
 	int r;
@@ -1881,8 +1879,7 @@ static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
 			msg_hi = val;
 		} else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0) &&
 			   val == 0) {
-			r = vcn_v3_0_dec_msg(p, job,
-					     ((u64)msg_hi) << 32 | msg_lo);
+			r = vcn_v3_0_dec_msg(p, ((u64)msg_hi) << 32 | msg_lo);
 			if (r)
 				return r;
 		}
-- 
GitLab


From 64f6516e60b0bbe6abfc9f1d9f1999012e0f11a6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
Date: Fri, 3 Jun 2022 15:05:04 +0200
Subject: [PATCH 0357/1731] drm/amdgpu: always flush the TLB on gfx8
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The TLB on GFX8 stores each block of 8 PTEs where any of the valid bits
are set.

Fixes: 5255e146c99a ("drm/amdgpu: rework TLB flushing")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Tested-by: Michal Kubecek <mkubecek@suse.cz>
Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 109d8dd71c116..dc76d2b3ce52f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -793,6 +793,11 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 	flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
 		     adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0);
 
+	/*
+	 * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
+	 */
+	flush_tlb |= adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 0);
+
 	memset(&params, 0, sizeof(params));
 	params.adev = adev;
 	params.vm = vm;
-- 
GitLab


From 8c4811e7a5a60443139369a623ca504bad9e3675 Mon Sep 17 00:00:00 2001
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Date: Mon, 30 May 2022 15:02:47 +0300
Subject: [PATCH 0358/1731] MAINTAINERS: Update Synopsys DesignWare I2C to
 Supported

The actual status of the code is Supported (from x86 perspective).

Reported-by: dave.hansen@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
[wsa: fixed "DesignWare" spelling]
Signed-off-by: Wolfram Sang <wsa@kernel.org>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index a6d3bd9d2a8d0..cb2342ce3b55a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19288,7 +19288,7 @@ R:	Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 R:	Mika Westerberg <mika.westerberg@linux.intel.com>
 R:	Jan Dabros <jsd@semihalf.com>
 L:	linux-i2c@vger.kernel.org
-S:	Maintained
+S:	Supported
 F:	drivers/i2c/busses/i2c-designware-*
 
 SYNOPSYS DESIGNWARE MMC/SD/SDIO DRIVER
-- 
GitLab


From 6ba12b56b9b844b83ed54fb7ed59fb0eb41e4045 Mon Sep 17 00:00:00 2001
From: Jiasheng Jiang <jiasheng@iscas.ac.cn>
Date: Thu, 26 May 2022 17:41:00 +0800
Subject: [PATCH 0359/1731] i2c: npcm7xx: Add check for
 platform_driver_register

As platform_driver_register() could fail, it should be better
to deal with the return value in order to maintain the code
consisitency.

Fixes: 56a1485b102e ("i2c: npcm7xx: Add Nuvoton NPCM I2C controller driver")
Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn>
Acked-by: Tali Perry <tali.perry1@gmail.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
---
 drivers/i2c/busses/i2c-npcm7xx.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-npcm7xx.c b/drivers/i2c/busses/i2c-npcm7xx.c
index 5960ccde65741..aede9d551130b 100644
--- a/drivers/i2c/busses/i2c-npcm7xx.c
+++ b/drivers/i2c/busses/i2c-npcm7xx.c
@@ -2372,8 +2372,7 @@ static struct platform_driver npcm_i2c_bus_driver = {
 static int __init npcm_i2c_init(void)
 {
 	npcm_i2c_debugfs_dir = debugfs_create_dir("npcm_i2c", NULL);
-	platform_driver_register(&npcm_i2c_bus_driver);
-	return 0;
+	return platform_driver_register(&npcm_i2c_bus_driver);
 }
 module_init(npcm_i2c_init);
 
-- 
GitLab


From ea6c1213217dec65a8f9f396752b4d8bbcf226ea Mon Sep 17 00:00:00 2001
From: Julia Lawall <Julia.Lawall@inria.fr>
Date: Thu, 9 Jun 2022 09:18:15 +0530
Subject: [PATCH 0360/1731] RISC-V: KVM: fix typos in comments

Various spelling mistakes in comments.
Detected with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Signed-off-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/kvm/vmid.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/kvm/vmid.c b/arch/riscv/kvm/vmid.c
index 9f764df125db9..6cd93995fb65e 100644
--- a/arch/riscv/kvm/vmid.c
+++ b/arch/riscv/kvm/vmid.c
@@ -97,7 +97,7 @@ void kvm_riscv_gstage_vmid_update(struct kvm_vcpu *vcpu)
 		 * We ran out of VMIDs so we increment vmid_version and
 		 * start assigning VMIDs from 1.
 		 *
-		 * This also means existing VMIDs assignement to all Guest
+		 * This also means existing VMIDs assignment to all Guest
 		 * instances is invalid and we have force VMID re-assignement
 		 * for all Guest instances. The Guest instances that were not
 		 * running will automatically pick-up new VMIDs because will
-- 
GitLab


From 1a12b25274b9e54b0d2d59e21620f8cf13b268cb Mon Sep 17 00:00:00 2001
From: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Date: Thu, 9 Jun 2022 09:18:22 +0530
Subject: [PATCH 0361/1731] MAINTAINERS: Limit KVM RISC-V entry to existing
 selftests

Commit fed9b26b2501 ("MAINTAINERS: Update KVM RISC-V entry to cover
selftests support") optimistically adds a file entry for
tools/testing/selftests/kvm/riscv/, but this directory does not exist.

Hence, ./scripts/get_maintainer.pl --self-test=patterns complains about a
broken reference. The script is very useful to keep MAINTAINERS up to date
and MAINTAINERS can be kept in a state where the script emits no warning.

So, just drop the non-matching file entry rather than starting to collect
exceptions of entries that may match in some close or distant future.

Fixes: fed9b26b2501 ("MAINTAINERS: Update KVM RISC-V entry to cover selftests support")
Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
---
 MAINTAINERS | 1 -
 1 file changed, 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index a6d3bd9d2a8d0..e549a84e21c88 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10863,7 +10863,6 @@ F:	arch/riscv/include/asm/kvm*
 F:	arch/riscv/include/uapi/asm/kvm*
 F:	arch/riscv/kvm/
 F:	tools/testing/selftests/kvm/*/riscv/
-F:	tools/testing/selftests/kvm/riscv/
 
 KERNEL VIRTUAL MACHINE for s390 (KVM/s390)
 M:	Christian Borntraeger <borntraeger@linux.ibm.com>
-- 
GitLab


From c132fe78ad7b4ce8b5d49a501a15c29d08eeb23a Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Sun, 5 Jun 2022 08:27:23 +0400
Subject: [PATCH 0362/1731] dmaengine: ti: Fix refcount leak in
 ti_dra7_xbar_route_allocate

of_parse_phandle() returns a node pointer with refcount
incremented, we should use of_node_put() on it when not needed anymore.

Add missing of_node_put() in to fix this.

Fixes: ec9bfa1e1a79 ("dmaengine: ti-dma-crossbar: dra7: Use bitops instead of idr")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Link: https://lore.kernel.org/r/20220605042723.17668-2-linmq006@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/dma/ti/dma-crossbar.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/dma/ti/dma-crossbar.c b/drivers/dma/ti/dma-crossbar.c
index 71d24fc07c003..e34cfb50d2416 100644
--- a/drivers/dma/ti/dma-crossbar.c
+++ b/drivers/dma/ti/dma-crossbar.c
@@ -268,6 +268,7 @@ static void *ti_dra7_xbar_route_allocate(struct of_phandle_args *dma_spec,
 		mutex_unlock(&xbar->mutex);
 		dev_err(&pdev->dev, "Run out of free DMA requests\n");
 		kfree(map);
+		of_node_put(dma_spec->np);
 		return ERR_PTR(-ENOMEM);
 	}
 	set_bit(map->xbar_out, xbar->dma_inuse);
-- 
GitLab


From 615a4bfc426e11dba05c2cf343f9ac752fb381d2 Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Sun, 5 Jun 2022 08:27:22 +0400
Subject: [PATCH 0363/1731] dmaengine: ti: Add missing put_device in
 ti_dra7_xbar_route_allocate

of_find_device_by_node() takes reference, we should use put_device()
to release it when not need anymore.

Fixes: a074ae38f859 ("dmaengine: Add driver for TI DMA crossbar on DRA7x")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com>
Link: https://lore.kernel.org/r/20220605042723.17668-1-linmq006@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/dma/ti/dma-crossbar.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/dma/ti/dma-crossbar.c b/drivers/dma/ti/dma-crossbar.c
index e34cfb50d2416..f744ddbbbad7f 100644
--- a/drivers/dma/ti/dma-crossbar.c
+++ b/drivers/dma/ti/dma-crossbar.c
@@ -245,6 +245,7 @@ static void *ti_dra7_xbar_route_allocate(struct of_phandle_args *dma_spec,
 	if (dma_spec->args[0] >= xbar->xbar_requests) {
 		dev_err(&pdev->dev, "Invalid XBAR request number: %d\n",
 			dma_spec->args[0]);
+		put_device(&pdev->dev);
 		return ERR_PTR(-EINVAL);
 	}
 
@@ -252,12 +253,14 @@ static void *ti_dra7_xbar_route_allocate(struct of_phandle_args *dma_spec,
 	dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", 0);
 	if (!dma_spec->np) {
 		dev_err(&pdev->dev, "Can't get DMA master\n");
+		put_device(&pdev->dev);
 		return ERR_PTR(-EINVAL);
 	}
 
 	map = kzalloc(sizeof(*map), GFP_KERNEL);
 	if (!map) {
 		of_node_put(dma_spec->np);
+		put_device(&pdev->dev);
 		return ERR_PTR(-ENOMEM);
 	}
 
@@ -269,6 +272,7 @@ static void *ti_dra7_xbar_route_allocate(struct of_phandle_args *dma_spec,
 		dev_err(&pdev->dev, "Run out of free DMA requests\n");
 		kfree(map);
 		of_node_put(dma_spec->np);
+		put_device(&pdev->dev);
 		return ERR_PTR(-ENOMEM);
 	}
 	set_bit(map->xbar_out, xbar->dma_inuse);
-- 
GitLab


From 646728dff254f8070da5d2f82494a065d4287e26 Mon Sep 17 00:00:00 2001
From: Vinod Koul <vkoul@kernel.org>
Date: Mon, 6 Jun 2022 23:19:06 +0530
Subject: [PATCH 0364/1731] dmaengine: Revert "dmaengine: add verification of
 DMA_INTERRUPT capability for dmatest"

This reverts commit a8facc7b9885 ("dmaengine: add verification of
DMA_INTERRUPT capability for dmatest") as it causes regression due to
the fact that DMA_INTERRUPT in linked to dma_prep_interrupt() so
checking that is incorrect here

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20220606174906.3979283-1-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/dma/dmatest.c | 13 +++----------
 1 file changed, 3 insertions(+), 10 deletions(-)

diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c
index 0a2168a4ccb0c..f696246f57fdb 100644
--- a/drivers/dma/dmatest.c
+++ b/drivers/dma/dmatest.c
@@ -675,16 +675,10 @@ static int dmatest_func(void *data)
 	/*
 	 * src and dst buffers are freed by ourselves below
 	 */
-	if (params->polled) {
+	if (params->polled)
 		flags = DMA_CTRL_ACK;
-	} else {
-		if (dma_has_cap(DMA_INTERRUPT, dev->cap_mask)) {
-			flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
-		} else {
-			pr_err("Channel does not support interrupt!\n");
-			goto err_pq_array;
-		}
-	}
+	else
+		flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 
 	ktime = ktime_get();
 	while (!(kthread_should_stop() ||
@@ -912,7 +906,6 @@ error_unmap_continue:
 	runtime = ktime_to_us(ktime);
 
 	ret = 0;
-err_pq_array:
 	kfree(dma_pq);
 err_srcs_array:
 	kfree(srcs);
-- 
GitLab


From a7cd3cf0b2e5aaacfe5e02c472bd28e98e640be7 Mon Sep 17 00:00:00 2001
From: Peter Robinson <pbrobinson@gmail.com>
Date: Mon, 6 Jun 2022 17:10:34 +0100
Subject: [PATCH 0365/1731] dmaengine: imx-sdma: Allow imx8m for imx7 FW revs

The revision of the imx-sdma IP that is in the i.MX8M series is the
same is that as that in the i.MX7 series but the imx7d MODULE_FIRMWARE
directive is wrapped in a condiditional which means it's not defined
when built for aarch64 SOC_IMX8M platforms and hence you get the
following errors when the driver loads on imx8m devices:

imx-sdma 302c0000.dma-controller: Direct firmware load for imx/sdma/sdma-imx7d.bin failed with error -2
imx-sdma 302c0000.dma-controller: external firmware not found, using ROM firmware

Add the SOC_IMX8M into the check so the firmware can load on i.MX8.

Fixes: 1474d48bd639 ("arm64: dts: imx8mq: Add SDMA nodes")
Fixes: 941acd566b18 ("dmaengine: imx-sdma: Only check ratio on parts that support 1:1")
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Cc: stable@vger.kernel.org   # v5.2+
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Link: https://lore.kernel.org/r/20220606161034.3544803-1-pbrobinson@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/dma/imx-sdma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 8535018ee7a2e..900cafdaf3594 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -2346,7 +2346,7 @@ MODULE_DESCRIPTION("i.MX SDMA driver");
 #if IS_ENABLED(CONFIG_SOC_IMX6Q)
 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
 #endif
-#if IS_ENABLED(CONFIG_SOC_IMX7D)
+#if IS_ENABLED(CONFIG_SOC_IMX7D) || IS_ENABLED(CONFIG_SOC_IMX8M)
 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");
 #endif
 MODULE_LICENSE("GPL");
-- 
GitLab


From b6c8cd80ace30f308aeec0ecf946f55dec60cc68 Mon Sep 17 00:00:00 2001
From: Guenter Roeck <linux@roeck-us.net>
Date: Fri, 3 Jun 2022 06:14:19 -0700
Subject: [PATCH 0366/1731] watchdog: gxp: Add missing MODULE_LICENSE

The build system says:

ERROR: modpost: missing MODULE_LICENSE() in drivers/watchdog/gxp-wdt.o

Add the missing MODULE_LICENSE.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/all/20220603131419.2948578-1-linux@roeck-us.net/
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
---
 drivers/watchdog/gxp-wdt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/watchdog/gxp-wdt.c b/drivers/watchdog/gxp-wdt.c
index b0b2d7a6fdde7..2fd85be882786 100644
--- a/drivers/watchdog/gxp-wdt.c
+++ b/drivers/watchdog/gxp-wdt.c
@@ -172,3 +172,4 @@ module_platform_driver(gxp_wdt_driver);
 MODULE_AUTHOR("Nick Hawkins <nick.hawkins@hpe.com>");
 MODULE_AUTHOR("Jean-Marie Verdun <verdun@hpe.com>");
 MODULE_DESCRIPTION("Driver for GXP watchdog timer");
+MODULE_LICENSE("GPL");
-- 
GitLab


From 908e698f2149c3d6a67d9ae15c75545a3f392559 Mon Sep 17 00:00:00 2001
From: Robert Eckelmann <longnoserob@gmail.com>
Date: Sat, 21 May 2022 23:08:08 +0900
Subject: [PATCH 0367/1731] USB: serial: io_ti: add Agilent E5805A support

Add support for Agilent E5805A (rebranded ION Edgeport/4) to io_ti.

Signed-off-by: Robert Eckelmann <longnoserob@gmail.com>
Link: https://lore.kernel.org/r/20220521230808.30931eca@octoberrain
Cc: stable@vger.kernel.org
Signed-off-by: Johan Hovold <johan@kernel.org>
---
 drivers/usb/serial/io_ti.c      | 2 ++
 drivers/usb/serial/io_usbvend.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/usb/serial/io_ti.c b/drivers/usb/serial/io_ti.c
index a7b3c15957ba9..feba2a8d1233a 100644
--- a/drivers/usb/serial/io_ti.c
+++ b/drivers/usb/serial/io_ti.c
@@ -166,6 +166,7 @@ static const struct usb_device_id edgeport_2port_id_table[] = {
 	{ USB_DEVICE(USB_VENDOR_ID_ION, ION_DEVICE_ID_TI_EDGEPORT_8S) },
 	{ USB_DEVICE(USB_VENDOR_ID_ION, ION_DEVICE_ID_TI_EDGEPORT_416) },
 	{ USB_DEVICE(USB_VENDOR_ID_ION, ION_DEVICE_ID_TI_EDGEPORT_416B) },
+	{ USB_DEVICE(USB_VENDOR_ID_ION, ION_DEVICE_ID_E5805A) },
 	{ }
 };
 
@@ -204,6 +205,7 @@ static const struct usb_device_id id_table_combined[] = {
 	{ USB_DEVICE(USB_VENDOR_ID_ION, ION_DEVICE_ID_TI_EDGEPORT_8S) },
 	{ USB_DEVICE(USB_VENDOR_ID_ION, ION_DEVICE_ID_TI_EDGEPORT_416) },
 	{ USB_DEVICE(USB_VENDOR_ID_ION, ION_DEVICE_ID_TI_EDGEPORT_416B) },
+	{ USB_DEVICE(USB_VENDOR_ID_ION, ION_DEVICE_ID_E5805A) },
 	{ }
 };
 
diff --git a/drivers/usb/serial/io_usbvend.h b/drivers/usb/serial/io_usbvend.h
index 52cbc353051fe..9a6f742ad3abd 100644
--- a/drivers/usb/serial/io_usbvend.h
+++ b/drivers/usb/serial/io_usbvend.h
@@ -212,6 +212,7 @@
 //
 // Definitions for other product IDs
 #define ION_DEVICE_ID_MT4X56USB			0x1403	// OEM device
+#define ION_DEVICE_ID_E5805A			0x1A01  // OEM device (rebranded Edgeport/4)
 
 
 #define	GENERATION_ID_FROM_USB_PRODUCT_ID(ProductId)				\
-- 
GitLab


From ae187fec75aa670a551d9662f83e3947d3f02a69 Mon Sep 17 00:00:00 2001
From: Will Deacon <will@kernel.org>
Date: Thu, 9 Jun 2022 13:12:18 +0100
Subject: [PATCH 0368/1731] KVM: arm64: Return error from kvm_arch_init_vm() on
 allocation failure

If we fail to allocate the 'supported_cpus' cpumask in kvm_arch_init_vm()
then be sure to return -ENOMEM instead of success (0) on the failure
path.

Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220609121223.2551-2-will@kernel.org
---
 arch/arm64/kvm/arm.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index 400bb0fe2745b..0da0f06037dbb 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -150,8 +150,10 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 	if (ret)
 		goto out_free_stage2_pgd;
 
-	if (!zalloc_cpumask_var(&kvm->arch.supported_cpus, GFP_KERNEL))
+	if (!zalloc_cpumask_var(&kvm->arch.supported_cpus, GFP_KERNEL)) {
+		ret = -ENOMEM;
 		goto out_free_stage2_pgd;
+	}
 	cpumask_copy(kvm->arch.supported_cpus, cpu_possible_mask);
 
 	kvm_vgic_early_init(kvm);
-- 
GitLab


From fa7a17214488ef7df347dcd1a5594f69ea17f4dc Mon Sep 17 00:00:00 2001
From: Marc Zyngier <maz@kernel.org>
Date: Thu, 9 Jun 2022 13:12:19 +0100
Subject: [PATCH 0369/1731] KVM: arm64: Handle all ID registers trapped for a
 protected VM

A protected VM accessing ID_AA64ISAR2_EL1 gets punished with an UNDEF,
while it really should only get a zero back if the register is not
handled by the hypervisor emulation (as mandated by the architecture).

Introduce all the missing ID registers (including the unallocated ones),
and have them to return 0.

Reported-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220609121223.2551-3-will@kernel.org
---
 arch/arm64/kvm/hyp/nvhe/sys_regs.c | 42 ++++++++++++++++++++++++------
 1 file changed, 34 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c
index b6d86e423319f..35a4331ba5f31 100644
--- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c
+++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c
@@ -243,15 +243,9 @@ u64 pvm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
 	case SYS_ID_AA64MMFR2_EL1:
 		return get_pvm_id_aa64mmfr2(vcpu);
 	default:
-		/*
-		 * Should never happen because all cases are covered in
-		 * pvm_sys_reg_descs[].
-		 */
-		WARN_ON(1);
-		break;
+		/* Unhandled ID register, RAZ */
+		return 0;
 	}
-
-	return 0;
 }
 
 static u64 read_id_reg(const struct kvm_vcpu *vcpu,
@@ -332,6 +326,16 @@ static bool pvm_gic_read_sre(struct kvm_vcpu *vcpu,
 /* Mark the specified system register as an AArch64 feature id register. */
 #define AARCH64(REG) { SYS_DESC(REG), .access = pvm_access_id_aarch64 }
 
+/*
+ * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
+ * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
+ * (1 <= crm < 8, 0 <= Op2 < 8).
+ */
+#define ID_UNALLOCATED(crm, op2) {			\
+	Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2),	\
+	.access = pvm_access_id_aarch64,		\
+}
+
 /* Mark the specified system register as Read-As-Zero/Write-Ignored */
 #define RAZ_WI(REG) { SYS_DESC(REG), .access = pvm_access_raz_wi }
 
@@ -375,24 +379,46 @@ static const struct sys_reg_desc pvm_sys_reg_descs[] = {
 	AARCH32(SYS_MVFR0_EL1),
 	AARCH32(SYS_MVFR1_EL1),
 	AARCH32(SYS_MVFR2_EL1),
+	ID_UNALLOCATED(3,3),
 	AARCH32(SYS_ID_PFR2_EL1),
 	AARCH32(SYS_ID_DFR1_EL1),
 	AARCH32(SYS_ID_MMFR5_EL1),
+	ID_UNALLOCATED(3,7),
 
 	/* AArch64 ID registers */
 	/* CRm=4 */
 	AARCH64(SYS_ID_AA64PFR0_EL1),
 	AARCH64(SYS_ID_AA64PFR1_EL1),
+	ID_UNALLOCATED(4,2),
+	ID_UNALLOCATED(4,3),
 	AARCH64(SYS_ID_AA64ZFR0_EL1),
+	ID_UNALLOCATED(4,5),
+	ID_UNALLOCATED(4,6),
+	ID_UNALLOCATED(4,7),
 	AARCH64(SYS_ID_AA64DFR0_EL1),
 	AARCH64(SYS_ID_AA64DFR1_EL1),
+	ID_UNALLOCATED(5,2),
+	ID_UNALLOCATED(5,3),
 	AARCH64(SYS_ID_AA64AFR0_EL1),
 	AARCH64(SYS_ID_AA64AFR1_EL1),
+	ID_UNALLOCATED(5,6),
+	ID_UNALLOCATED(5,7),
 	AARCH64(SYS_ID_AA64ISAR0_EL1),
 	AARCH64(SYS_ID_AA64ISAR1_EL1),
+	AARCH64(SYS_ID_AA64ISAR2_EL1),
+	ID_UNALLOCATED(6,3),
+	ID_UNALLOCATED(6,4),
+	ID_UNALLOCATED(6,5),
+	ID_UNALLOCATED(6,6),
+	ID_UNALLOCATED(6,7),
 	AARCH64(SYS_ID_AA64MMFR0_EL1),
 	AARCH64(SYS_ID_AA64MMFR1_EL1),
 	AARCH64(SYS_ID_AA64MMFR2_EL1),
+	ID_UNALLOCATED(7,3),
+	ID_UNALLOCATED(7,4),
+	ID_UNALLOCATED(7,5),
+	ID_UNALLOCATED(7,6),
+	ID_UNALLOCATED(7,7),
 
 	/* Scalable Vector Registers are restricted. */
 
-- 
GitLab


From cde5042adf11b0a30a6ce0ec3d071afcf8d2efaf Mon Sep 17 00:00:00 2001
From: Will Deacon <will@kernel.org>
Date: Thu, 9 Jun 2022 13:12:20 +0100
Subject: [PATCH 0370/1731] KVM: arm64: Ignore 'kvm-arm.mode=protected' when
 using VHE

Ignore 'kvm-arm.mode=protected' when using VHE so that kvm_get_mode()
only returns KVM_MODE_PROTECTED on systems where the feature is available.

Cc: David Brazdil <dbrazdil@google.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220609121223.2551-4-will@kernel.org
---
 Documentation/admin-guide/kernel-parameters.txt |  1 -
 arch/arm64/kernel/cpufeature.c                  | 10 +---------
 arch/arm64/kvm/arm.c                            |  6 +++++-
 3 files changed, 6 insertions(+), 11 deletions(-)

diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 8090130b544b0..97c16aa2f53fd 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -2469,7 +2469,6 @@
 
 			protected: nVHE-based mode with support for guests whose
 				   state is kept private from the host.
-				   Not valid if the kernel is running in EL2.
 
 			Defaults to VHE/nVHE based on hardware support. Setting
 			mode to "protected" will disable kexec and hibernation
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 42ea2bd856c60..79fac13ab2efc 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1974,15 +1974,7 @@ static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
 #ifdef CONFIG_KVM
 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused)
 {
-	if (kvm_get_mode() != KVM_MODE_PROTECTED)
-		return false;
-
-	if (is_kernel_in_hyp_mode()) {
-		pr_warn("Protected KVM not available with VHE\n");
-		return false;
-	}
-
-	return true;
+	return kvm_get_mode() == KVM_MODE_PROTECTED;
 }
 #endif /* CONFIG_KVM */
 
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index 0da0f06037dbb..a0188144a122b 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -2273,7 +2273,11 @@ static int __init early_kvm_mode_cfg(char *arg)
 		return -EINVAL;
 
 	if (strcmp(arg, "protected") == 0) {
-		kvm_mode = KVM_MODE_PROTECTED;
+		if (!is_kernel_in_hyp_mode())
+			kvm_mode = KVM_MODE_PROTECTED;
+		else
+			pr_warn_once("Protected KVM not available with VHE\n");
+
 		return 0;
 	}
 
-- 
GitLab


From 112f3bab41113dc53b4f35e9034b2208245bc002 Mon Sep 17 00:00:00 2001
From: Will Deacon <will@kernel.org>
Date: Thu, 9 Jun 2022 13:12:21 +0100
Subject: [PATCH 0371/1731] KVM: arm64: Extend comment in has_vhe()

has_vhe() expands to a compile-time constant when evaluated from the VHE
or nVHE code, alternatively checking a static key when called from
elsewhere in the kernel. On face value, this looks like a case of
premature optimization, but in fact this allows symbol references on
VHE-specific code paths to be dropped from the nVHE object.

Expand the comment in has_vhe() to make this clearer, hopefully
discouraging anybody from simplifying the code.

Cc: David Brazdil <dbrazdil@google.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220609121223.2551-5-will@kernel.org
---
 arch/arm64/include/asm/virt.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/include/asm/virt.h b/arch/arm64/include/asm/virt.h
index 3c8af033a9976..0e80db4327b60 100644
--- a/arch/arm64/include/asm/virt.h
+++ b/arch/arm64/include/asm/virt.h
@@ -113,6 +113,9 @@ static __always_inline bool has_vhe(void)
 	/*
 	 * Code only run in VHE/NVHE hyp context can assume VHE is present or
 	 * absent. Otherwise fall back to caps.
+	 * This allows the compiler to discard VHE-specific code from the
+	 * nVHE object, reducing the number of external symbol references
+	 * needed to link.
 	 */
 	if (is_vhe_hyp_code())
 		return true;
-- 
GitLab


From 5879c97f37022ff22a3f13174c24fcf2807fdbc0 Mon Sep 17 00:00:00 2001
From: Will Deacon <will@kernel.org>
Date: Thu, 9 Jun 2022 13:12:22 +0100
Subject: [PATCH 0372/1731] KVM: arm64: Remove redundant hyp_assert_lock_held()
 assertions

host_stage2_try() asserts that the KVM host lock is held, so there's no
need to duplicate the assertion in its wrappers.

Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220609121223.2551-6-will@kernel.org
---
 arch/arm64/kvm/hyp/nvhe/mem_protect.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/arm64/kvm/hyp/nvhe/mem_protect.c b/arch/arm64/kvm/hyp/nvhe/mem_protect.c
index 78edf077fa3b6..1e78acf9662eb 100644
--- a/arch/arm64/kvm/hyp/nvhe/mem_protect.c
+++ b/arch/arm64/kvm/hyp/nvhe/mem_protect.c
@@ -314,15 +314,11 @@ static int host_stage2_adjust_range(u64 addr, struct kvm_mem_range *range)
 int host_stage2_idmap_locked(phys_addr_t addr, u64 size,
 			     enum kvm_pgtable_prot prot)
 {
-	hyp_assert_lock_held(&host_kvm.lock);
-
 	return host_stage2_try(__host_stage2_idmap, addr, addr + size, prot);
 }
 
 int host_stage2_set_owner_locked(phys_addr_t addr, u64 size, u8 owner_id)
 {
-	hyp_assert_lock_held(&host_kvm.lock);
-
 	return host_stage2_try(kvm_pgtable_stage2_set_owner, &host_kvm.pgt,
 			       addr, size, &host_s2_pool, owner_id);
 }
-- 
GitLab


From bcbfb588cf323929ac46767dd14e392016bbce04 Mon Sep 17 00:00:00 2001
From: Marc Zyngier <maz@kernel.org>
Date: Thu, 9 Jun 2022 13:12:23 +0100
Subject: [PATCH 0373/1731] KVM: arm64: Drop stale comment

The layout of 'struct kvm_vcpu_arch' has evolved significantly since
the initial port of KVM/arm64, so remove the stale comment suggesting
that a prefix of the structure is used exclusively from assembly code.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220609121223.2551-7-will@kernel.org
---
 arch/arm64/include/asm/kvm_host.h | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 47a1e25e25bbc..de32152cea048 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -362,11 +362,6 @@ struct kvm_vcpu_arch {
 	struct arch_timer_cpu timer_cpu;
 	struct kvm_pmu pmu;
 
-	/*
-	 * Anything that is not used directly from assembly code goes
-	 * here.
-	 */
-
 	/*
 	 * Guest registers we preserve during guest debugging.
 	 *
-- 
GitLab


From 204e6ceaa1035cb7b92b156517e88842ebb4c7ff Mon Sep 17 00:00:00 2001
From: Sungjong Seo <sj1557.seo@samsung.com>
Date: Wed, 8 Jun 2022 00:05:21 +0900
Subject: [PATCH 0374/1731] exfat: use updated exfat_chain directly during
 renaming

In order for a file to access its own directory entry set,
exfat_inode_info(ei) has two copied values. One is ei->dir, which is
a snapshot of exfat_chain of the parent directory, and the other is
ei->entry, which is the offset of the start of the directory entry set
in the parent directory.

Since the parent directory can be updated after the snapshot point,
it should be used only for accessing one's own directory entry set.

However, as of now, during renaming, it could try to traverse or to
allocate clusters via snapshot values, it does not make sense.

This potential problem has been revealed when exfat_update_parent_info()
was removed by commit d8dad2588add ("exfat: fix referencing wrong parent
directory information after renaming"). However, I don't think it's good
idea to bring exfat_update_parent_info() back.

Instead, let's use the updated exfat_chain of parent directory diectly.

Fixes: d8dad2588add ("exfat: fix referencing wrong parent directory information after renaming")
Reported-by: Wang Yugui <wangyugui@e16-tech.com>
Signed-off-by: Sungjong Seo <sj1557.seo@samsung.com>
Tested-by: Wang Yugui <wangyugui@e16-tech.com>
Signed-off-by: Namjae Jeon <linkinjeon@kernel.org>
---
 fs/exfat/namei.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/fs/exfat/namei.c b/fs/exfat/namei.c
index 76acc3721951f..c6eaf7e9ea743 100644
--- a/fs/exfat/namei.c
+++ b/fs/exfat/namei.c
@@ -1198,7 +1198,9 @@ static int __exfat_rename(struct inode *old_parent_inode,
 		return -ENOENT;
 	}
 
-	exfat_chain_dup(&olddir, &ei->dir);
+	exfat_chain_set(&olddir, EXFAT_I(old_parent_inode)->start_clu,
+		EXFAT_B_TO_CLU_ROUND_UP(i_size_read(old_parent_inode), sbi),
+		EXFAT_I(old_parent_inode)->flags);
 	dentry = ei->entry;
 
 	ep = exfat_get_dentry(sb, &olddir, dentry, &old_bh);
-- 
GitLab


From 158f7585bfcea4aae0ad4128d032a80fec550df1 Mon Sep 17 00:00:00 2001
From: Slark Xiao <slark_xiao@163.com>
Date: Wed, 1 Jun 2022 11:47:40 +0800
Subject: [PATCH 0375/1731] USB: serial: option: add support for Cinterion MV31
 with new baseline

Adding support for Cinterion device MV31 with Qualcomm
new baseline. Use different PIDs to separate it from
previous base line products.
All interfaces settings keep same as previous.

Below is test evidence:
T:  Bus=03 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#=  6 Spd=480 MxCh= 0
D:  Ver= 2.10 Cls=ef(misc ) Sub=02 Prot=01 MxPS=64 #Cfgs=  1
P:  Vendor=1e2d ProdID=00b8 Rev=04.14
S:  Manufacturer=Cinterion
S:  Product=Cinterion PID 0x00B8 USB Mobile Broadband
S:  SerialNumber=90418e79
C:  #Ifs= 6 Cfg#= 1 Atr=a0 MxPwr=500mA
I:  If#=0x0 Alt= 0 #EPs= 1 Cls=02(commc) Sub=0e Prot=00 Driver=cdc_mbim
I:  If#=0x1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=02 Driver=cdc_mbim
I:  If#=0x2 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=40 Driver=option
I:  If#=0x3 Alt= 0 #EPs= 1 Cls=ff(vend.) Sub=ff Prot=ff Driver=(none)
I:  If#=0x4 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=60 Driver=option
I:  If#=0x5 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=30 Driver=option

T:  Bus=03 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#=  7 Spd=480 MxCh= 0
D:  Ver= 2.10 Cls=ef(misc ) Sub=02 Prot=01 MxPS=64 #Cfgs=  1
P:  Vendor=1e2d ProdID=00b9 Rev=04.14
S:  Manufacturer=Cinterion
S:  Product=Cinterion PID 0x00B9 USB Mobile Broadband
S:  SerialNumber=90418e79
C:  #Ifs= 4 Cfg#= 1 Atr=a0 MxPwr=500mA
I:  If#=0x0 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=50 Driver=qmi_wwan
I:  If#=0x1 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=40 Driver=option
I:  If#=0x2 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=60 Driver=option
I:  If#=0x3 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=30 Driver=option

For PID 00b8, interface 3 is GNSS port which don't use serial driver.

Signed-off-by: Slark Xiao <slark_xiao@163.com>
Link: https://lore.kernel.org/r/20220601034740.5438-1-slark_xiao@163.com
[ johan: rename defines using a "2" infix ]
Cc: stable@vger.kernel.org
Signed-off-by: Johan Hovold <johan@kernel.org>
---
 drivers/usb/serial/option.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
index e60425bbf5376..ed1e50d83ccab 100644
--- a/drivers/usb/serial/option.c
+++ b/drivers/usb/serial/option.c
@@ -432,6 +432,8 @@ static void option_instat_callback(struct urb *urb);
 #define CINTERION_PRODUCT_CLS8			0x00b0
 #define CINTERION_PRODUCT_MV31_MBIM		0x00b3
 #define CINTERION_PRODUCT_MV31_RMNET		0x00b7
+#define CINTERION_PRODUCT_MV31_2_MBIM		0x00b8
+#define CINTERION_PRODUCT_MV31_2_RMNET		0x00b9
 #define CINTERION_PRODUCT_MV32_WA		0x00f1
 #define CINTERION_PRODUCT_MV32_WB		0x00f2
 
@@ -1979,6 +1981,10 @@ static const struct usb_device_id option_ids[] = {
 	  .driver_info = RSVD(3)},
 	{ USB_DEVICE_INTERFACE_CLASS(CINTERION_VENDOR_ID, CINTERION_PRODUCT_MV31_RMNET, 0xff),
 	  .driver_info = RSVD(0)},
+	{ USB_DEVICE_INTERFACE_CLASS(CINTERION_VENDOR_ID, CINTERION_PRODUCT_MV31_2_MBIM, 0xff),
+	  .driver_info = RSVD(3)},
+	{ USB_DEVICE_INTERFACE_CLASS(CINTERION_VENDOR_ID, CINTERION_PRODUCT_MV31_2_RMNET, 0xff),
+	  .driver_info = RSVD(0)},
 	{ USB_DEVICE_INTERFACE_CLASS(CINTERION_VENDOR_ID, CINTERION_PRODUCT_MV32_WA, 0xff),
 	  .driver_info = RSVD(3)},
 	{ USB_DEVICE_INTERFACE_CLASS(CINTERION_VENDOR_ID, CINTERION_PRODUCT_MV32_WB, 0xff),
-- 
GitLab


From 2c5947cffd81ac8181346efacdca3c777ab330ba Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Tue, 7 Jun 2022 20:59:18 +0200
Subject: [PATCH 0376/1731] Revert "mtd: rawnand: add support for Toshiba
 TC58NVG0S3HTA00 NAND flash"

This reverts commit 3380557fc7e28d9bce7607e16d98f123d36da4ca.

It turned out this "4-byte" ID might have been an honest mistake.
Regrettably, the chip Andreas has might be a counterfeit or is
damaged in some other way and shouldn't have ended up in a router.

Andreas reported his chip is returning just four bytes:
"98 f1 80 15 00 00 00 00".

However, according to Kioxia/Toshiba's datasheet, there should
have been at least another byte that would have contained the
correct OOB size that Andreas needed.

Miquel and Andreas are both favoring reverting the patch over
further, possibly hacky modifications:
"[Reverting] is the safest option here. Apart from this device, we
do not know how many devices have these damaged/counterfeit chips.
If it is just a couple and only on Fritzboxes, as suggested in the
Github issue the patch could be carried through OpenWrt[...]"

Thanks to several users on the openwrt forum and github issue,
who stayed along for the ride:
 - Peter-vdL for reporting the issue and testing patches.
 - neg2led and Hannu Nyman who did all the
   datasheet digging and debugging.

Cc: Andreas Boehler <dev@aboehler.at>
Suggested-by: Andreas Boehler <dev@aboehler.at>
Suggested-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://github.com/openwrt/openwrt/issues/9962
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20220607185918.1048204-1-chunkeey@gmail.com
---
 drivers/mtd/nand/raw/nand_ids.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c
index 88c2440b47d84..dacc5529b3df9 100644
--- a/drivers/mtd/nand/raw/nand_ids.c
+++ b/drivers/mtd/nand/raw/nand_ids.c
@@ -29,9 +29,6 @@ struct nand_flash_dev nand_flash_ids[] = {
 	{"TC58NVG0S3E 1G 3.3V 8-bit",
 		{ .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
 		  SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
-	{"TC58NVG0S3HTA00 1G 3.3V 8-bit",
-		{ .id = {0x98, 0xf1, 0x80, 0x15} },
-		  SZ_2K, SZ_128, SZ_128K, 0, 4, 128, NAND_ECC_INFO(8, SZ_512), },
 	{"TC58NVG2S0F 4G 3.3V 8-bit",
 		{ .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
 		  SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
-- 
GitLab


From 4527d47bb63a134c4483a1a478d0ff5874b466c7 Mon Sep 17 00:00:00 2001
From: "GONG, Ruiqi" <gongruiqi1@huawei.com>
Date: Tue, 7 Jun 2022 19:08:48 +0800
Subject: [PATCH 0377/1731] drm/atomic: fix warning of unused variable

Fix the `unused-but-set-variable` warning as how other iteration
wrappers do.

Link: https://lore.kernel.org/all/202206071049.pofHsRih-lkp@intel.com/
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: GONG, Ruiqi <gongruiqi1@huawei.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20220607110848.941486-1-gongruiqi1@huawei.com
---
 include/drm/drm_atomic.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
index 0777725085df6..10b1990bc1f68 100644
--- a/include/drm/drm_atomic.h
+++ b/include/drm/drm_atomic.h
@@ -1022,6 +1022,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p);
 	for ((__i) = 0; \
 	     (__i) < (__state)->num_private_objs && \
 		     ((obj) = (__state)->private_objs[__i].ptr, \
+		      (void)(obj) /* Only to avoid unused-but-set-variable warning */, \
 		      (new_obj_state) = (__state)->private_objs[__i].new_state, 1); \
 	     (__i)++)
 
-- 
GitLab


From e0d7371b46c7b47cdf5391717292033365801437 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Wed, 8 Jun 2022 10:07:00 -0700
Subject: [PATCH 0378/1731] drm/i915/pvc: Add register steering

Ponte Vecchio no longer has MSLICE or LNCF steering, but the bspec does
document several new types of multicast register ranges.  Fortunately,
most of the different MCR types all provide valid values at instance
(0,0) so there's no need to read fuse registers and calculate a
non-terminated instance.  We'll lump all of those range types (BSLICE,
HALFBSLICE, TILEPSMI, CC, and L3BANK) into a single category called
"INSTANCE0" to keep things simple.  We'll also perform explicit steering
for each of these multicast register types, even if the implicit
steering setup for COMPUTE/DSS ranges would have worked too; this is
based on guidance from our hardware architects who suggested that we
move away from implicit steering and start explicitly steer all MCR
register accesses on modern platforms (we'll work on transitioning
COMPUTE/DSS to explicit steering in the future).

Note that there's one additional MCR range type defined in the bspec
(SQIDI) that we don't handle here.  Those ranges use a different
steering control register that we never touch; since instance 0 is also
always a valid setting there, we can just ignore those ranges.

Finally, we'll rename the HAS_MSLICES() macro to HAS_MSLICE_STEERING().
PVC hardware still has units referred to as mslices, but there's no
register steering based on mslice for this platform.

v2:
 - Rebase on other recent changes
 - Swap two table rows to keep table sorted & easy to read.  (Harish)

Bspec: 67609
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Harish Chegondi <harish.chegondi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220608170700.4026648-1-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/intel_gt.c          | 50 ++++++++++++++++++---
 drivers/gpu/drm/i915/gt/intel_gt_types.h    |  7 +++
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 16 +++++++
 drivers/gpu/drm/i915/i915_drv.h             |  3 +-
 drivers/gpu/drm/i915/i915_pci.c             |  3 +-
 drivers/gpu/drm/i915/intel_device_info.h    |  2 +-
 6 files changed, 71 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index ddfb98f704898..f33290358c518 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -106,6 +106,7 @@ static const char * const intel_steering_types[] = {
 	"L3BANK",
 	"MSLICE",
 	"LNCF",
+	"INSTANCE 0",
 };
 
 static const struct intel_mmio_range icl_l3bank_steering_table[] = {
@@ -133,6 +134,27 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = {
 	{},
 };
 
+/*
+ * We have several types of MCR registers on PVC where steering to (0,0)
+ * will always provide us with a non-terminated value.  We'll stick them
+ * all in the same table for simplicity.
+ */
+static const struct intel_mmio_range pvc_instance0_steering_table[] = {
+	{ 0x004000, 0x004AFF },		/* HALF-BSLICE */
+	{ 0x008800, 0x00887F },		/* CC */
+	{ 0x008A80, 0x008AFF },		/* TILEPSMI */
+	{ 0x00B000, 0x00B0FF },		/* HALF-BSLICE */
+	{ 0x00B100, 0x00B3FF },		/* L3BANK */
+	{ 0x00C800, 0x00CFFF },		/* HALF-BSLICE */
+	{ 0x00D800, 0x00D8FF },		/* HALF-BSLICE */
+	{ 0x00DD00, 0x00DDFF },		/* BSLICE */
+	{ 0x00E900, 0x00E9FF },		/* HALF-BSLICE */
+	{ 0x00EC00, 0x00EEFF },		/* HALF-BSLICE */
+	{ 0x00F000, 0x00FFFF },		/* HALF-BSLICE */
+	{ 0x024180, 0x0241FF },		/* HALF-BSLICE */
+	{},
+};
+
 int intel_gt_init_mmio(struct intel_gt *gt)
 {
 	struct drm_i915_private *i915 = gt->i915;
@@ -146,7 +168,7 @@ int intel_gt_init_mmio(struct intel_gt *gt)
 	 * An mslice is unavailable only if both the meml3 for the slice is
 	 * disabled *and* all of the DSS in the slice (quadrant) are disabled.
 	 */
-	if (HAS_MSLICES(i915)) {
+	if (HAS_MSLICE_STEERING(i915)) {
 		gt->info.mslice_mask =
 			intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
 							  GEN_DSS_PER_MSLICE);
@@ -158,7 +180,9 @@ int intel_gt_init_mmio(struct intel_gt *gt)
 			drm_warn(&i915->drm, "mslice mask all zero!\n");
 	}
 
-	if (IS_DG2(i915)) {
+	if (IS_PONTEVECCHIO(i915)) {
+		gt->steering_table[INSTANCE0] = pvc_instance0_steering_table;
+	} else if (IS_DG2(i915)) {
 		gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
 		gt->steering_table[LNCF] = dg2_lncf_steering_table;
 	} else if (IS_XEHPSDV(i915)) {
@@ -172,7 +196,11 @@ int intel_gt_init_mmio(struct intel_gt *gt)
 			GEN10_L3BANK_MASK;
 		if (!gt->info.l3bank_mask) /* should be impossible! */
 			drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
-	} else if (HAS_MSLICES(i915)) {
+	} else if (GRAPHICS_VER(i915) >= 11) {
+		/*
+		 * We expect all modern platforms to have at least some
+		 * type of steering that needs to be initialized.
+		 */
 		MISSING_CASE(INTEL_INFO(i915)->platform);
 	}
 
@@ -888,7 +916,7 @@ static void intel_gt_get_valid_steering(struct intel_gt *gt,
 		*subsliceid = __ffs(gt->info.l3bank_mask);
 		break;
 	case MSLICE:
-		GEM_WARN_ON(!HAS_MSLICES(gt->i915));
+		GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915));
 		*sliceid = __ffs(gt->info.mslice_mask);
 		*subsliceid = 0;	/* unused */
 		break;
@@ -897,10 +925,18 @@ static void intel_gt_get_valid_steering(struct intel_gt *gt,
 		 * An LNCF is always present if its mslice is present, so we
 		 * can safely just steer to LNCF 0 in all cases.
 		 */
-		GEM_WARN_ON(!HAS_MSLICES(gt->i915));
+		GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915));
 		*sliceid = __ffs(gt->info.mslice_mask) << 1;
 		*subsliceid = 0;	/* unused */
 		break;
+	case INSTANCE0:
+		/*
+		 * There are a lot of MCR types for which instance (0, 0)
+		 * will always provide a non-terminated value.
+		 */
+		*sliceid = 0;
+		*subsliceid = 0;
+		break;
 	default:
 		MISSING_CASE(type);
 		*sliceid = 0;
@@ -1020,7 +1056,9 @@ void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
 		   gt->default_steering.groupid,
 		   gt->default_steering.instanceid);
 
-	if (HAS_MSLICES(gt->i915)) {
+	if (IS_PONTEVECCHIO(gt->i915)) {
+		report_steering_type(p, gt, INSTANCE0, dump_table);
+	} else if (HAS_MSLICE_STEERING(gt->i915)) {
 		report_steering_type(p, gt, MSLICE, dump_table);
 		report_steering_type(p, gt, LNCF, dump_table);
 	}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 993f003dad1dc..df708802889df 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -59,6 +59,13 @@ enum intel_steering_type {
 	MSLICE,
 	LNCF,
 
+	/*
+	 * On some platforms there are multiple types of MCR registers that
+	 * will always return a non-terminated value at instance (0, 0).  We'll
+	 * lump those all into a single category to keep things simple.
+	 */
+	INSTANCE0,
+
 	NUM_STEERING_TYPES
 };
 
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 1ee54a83e459b..1e982ac931dc9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1195,6 +1195,20 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
 	__set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2);
 }
 
+static void
+pvc_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
+{
+	unsigned int dss;
+
+	/*
+	 * Setup implicit steering for COMPUTE and DSS ranges to the first
+	 * non-fused-off DSS.  All other types of MCR registers will be
+	 * explicitly steered.
+	 */
+	dss = intel_sseu_find_first_xehp_dss(&gt->info.sseu, 0, 0);
+	__add_mcr_wa(gt, wal, dss / GEN_DSS_PER_CSLICE, dss % GEN_DSS_PER_CSLICE);
+}
+
 static void
 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 {
@@ -1494,6 +1508,8 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 static void
 pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 {
+	pvc_init_mcr(gt, wal);
+
 	/* Wa_14015795083 */
 	wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fbea4d1ede7c8..59cd888209fe1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1346,8 +1346,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
 
-#define HAS_MSLICES(dev_priv) \
-	(INTEL_INFO(dev_priv)->has_mslices)
+#define HAS_MSLICE_STEERING(dev_priv)	(INTEL_INFO(dev_priv)->has_mslice_steering)
 
 /*
  * Set this flag, when platform requires 64K GTT page sizes or larger for
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b8244f72e4329..d6d875b2d3799 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1021,7 +1021,7 @@ static const struct intel_device_info adl_p_info = {
 	.has_llc = 1, \
 	.has_logical_ring_contexts = 1, \
 	.has_logical_ring_elsq = 1, \
-	.has_mslices = 1, \
+	.has_mslice_steering = 1, \
 	.has_rc6 = 1, \
 	.has_reset_engine = 1, \
 	.has_rps = 1, \
@@ -1092,6 +1092,7 @@ static const struct intel_device_info ats_m_info = {
 	.has_3d_pipeline = 0, \
 	.has_guc_deprivilege = 1, \
 	.has_l3_ccs_read = 1, \
+	.has_mslice_steering = 0, \
 	.has_one_eu_per_fuse_bit = 1
 
 __maybe_unused
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 346f17f2dce8c..08341174ee0a5 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -157,7 +157,7 @@ enum intel_ppgtt_type {
 	func(has_logical_ring_contexts); \
 	func(has_logical_ring_elsq); \
 	func(has_media_ratio_mode); \
-	func(has_mslices); \
+	func(has_mslice_steering); \
 	func(has_one_eu_per_fuse_bit); \
 	func(has_pooled_eu); \
 	func(has_pxp); \
-- 
GitLab


From d2263de1372a452cb64666990043b8be5c40b2a1 Mon Sep 17 00:00:00 2001
From: Yuan Yao <yuan.yao@intel.com>
Date: Wed, 8 Jun 2022 09:20:15 +0800
Subject: [PATCH 0379/1731] KVM: x86/mmu: Set memory encryption "value", not
 "mask", in shadow PDPTRs

Assign shadow_me_value, not shadow_me_mask, to PAE root entries,
a.k.a. shadow PDPTRs, when host memory encryption is supported.  The
"mask" is the set of all possible memory encryption bits, e.g. MKTME
KeyIDs, whereas "value" holds the actual value that needs to be
stuffed into host page tables.

Using shadow_me_mask results in a failed VM-Entry due to setting
reserved PA bits in the PDPTRs, and ultimately causes an OOPS due to
physical addresses with non-zero MKTME bits sending to_shadow_page()
into the weeds:

set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.
BUG: unable to handle page fault for address: ffd43f00063049e8
PGD 86dfd8067 P4D 0
Oops: 0000 [#1] PREEMPT SMP
RIP: 0010:mmu_free_root_page+0x3c/0x90 [kvm]
 kvm_mmu_free_roots+0xd1/0x200 [kvm]
 __kvm_mmu_unload+0x29/0x70 [kvm]
 kvm_mmu_unload+0x13/0x20 [kvm]
 kvm_arch_destroy_vm+0x8a/0x190 [kvm]
 kvm_put_kvm+0x197/0x2d0 [kvm]
 kvm_vm_release+0x21/0x30 [kvm]
 __fput+0x8e/0x260
 ____fput+0xe/0x10
 task_work_run+0x6f/0xb0
 do_exit+0x327/0xa90
 do_group_exit+0x35/0xa0
 get_signal+0x911/0x930
 arch_do_signal_or_restart+0x37/0x720
 exit_to_user_mode_prepare+0xb2/0x140
 syscall_exit_to_user_mode+0x16/0x30
 do_syscall_64+0x4e/0x90
 entry_SYSCALL_64_after_hwframe+0x44/0xae

Fixes: e54f1ff244ac ("KVM: x86/mmu: Add shadow_me_value and repurpose shadow_me_mask")
Signed-off-by: Yuan Yao <yuan.yao@intel.com>
Reviewed-by: Kai Huang <kai.huang@intel.com>
Message-Id: <20220608012015.19566-1-yuan.yao@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/mmu/mmu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index e826ee9138fa8..17252f39bd7c2 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -3411,7 +3411,7 @@ static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
 			root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT),
 					      i << 30, PT32_ROOT_LEVEL, true);
 			mmu->pae_root[i] = root | PT_PRESENT_MASK |
-					   shadow_me_mask;
+					   shadow_me_value;
 		}
 		mmu->root.hpa = __pa(mmu->pae_root);
 	} else {
-- 
GitLab


From a9603ae0e4ee6e7de0184801d4abe5925f43b49c Mon Sep 17 00:00:00 2001
From: Maxim Levitsky <mlevitsk@redhat.com>
Date: Mon, 6 Jun 2022 21:08:23 +0300
Subject: [PATCH 0380/1731] KVM: x86: document AVIC/APICv inhibit reasons

These days there are too many AVIC/APICv inhibit
reasons, and it doesn't hurt to have some documentation
for them.

Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
Message-Id: <20220606180829.102503-2-mlevitsk@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/include/asm/kvm_host.h | 59 +++++++++++++++++++++++++++++++--
 1 file changed, 57 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 3a240a64ac68f..1f9e47b895cf9 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -1047,14 +1047,69 @@ struct kvm_x86_msr_filter {
 };
 
 enum kvm_apicv_inhibit {
+
+	/********************************************************************/
+	/* INHIBITs that are relevant to both Intel's APICv and AMD's AVIC. */
+	/********************************************************************/
+
+	/*
+	 * APIC acceleration is disabled by a module parameter
+	 * and/or not supported in hardware.
+	 */
 	APICV_INHIBIT_REASON_DISABLE,
+
+	/*
+	 * APIC acceleration is inhibited because AutoEOI feature is
+	 * being used by a HyperV guest.
+	 */
 	APICV_INHIBIT_REASON_HYPERV,
+
+	/*
+	 * APIC acceleration is inhibited because the userspace didn't yet
+	 * enable the kernel/split irqchip.
+	 */
+	APICV_INHIBIT_REASON_ABSENT,
+
+	/* APIC acceleration is inhibited because KVM_GUESTDBG_BLOCKIRQ
+	 * (out of band, debug measure of blocking all interrupts on this vCPU)
+	 * was enabled, to avoid AVIC/APICv bypassing it.
+	 */
+	APICV_INHIBIT_REASON_BLOCKIRQ,
+
+	/******************************************************/
+	/* INHIBITs that are relevant only to the AMD's AVIC. */
+	/******************************************************/
+
+	/*
+	 * AVIC is inhibited on a vCPU because it runs a nested guest.
+	 *
+	 * This is needed because unlike APICv, the peers of this vCPU
+	 * cannot use the doorbell mechanism to signal interrupts via AVIC when
+	 * a vCPU runs nested.
+	 */
 	APICV_INHIBIT_REASON_NESTED,
+
+	/*
+	 * On SVM, the wait for the IRQ window is implemented with pending vIRQ,
+	 * which cannot be injected when the AVIC is enabled, thus AVIC
+	 * is inhibited while KVM waits for IRQ window.
+	 */
 	APICV_INHIBIT_REASON_IRQWIN,
+
+	/*
+	 * PIT (i8254) 're-inject' mode, relies on EOI intercept,
+	 * which AVIC doesn't support for edge triggered interrupts.
+	 */
 	APICV_INHIBIT_REASON_PIT_REINJ,
+
+	/*
+	 * AVIC is inhibited because the guest has x2apic in its CPUID.
+	 */
 	APICV_INHIBIT_REASON_X2APIC,
-	APICV_INHIBIT_REASON_BLOCKIRQ,
-	APICV_INHIBIT_REASON_ABSENT,
+
+	/*
+	 * AVIC is disabled because SEV doesn't support it.
+	 */
 	APICV_INHIBIT_REASON_SEV,
 };
 
-- 
GitLab


From 3743c2f0251743b8ae968329708bbbeefff244cf Mon Sep 17 00:00:00 2001
From: Maxim Levitsky <mlevitsk@redhat.com>
Date: Mon, 6 Jun 2022 21:08:24 +0300
Subject: [PATCH 0381/1731] KVM: x86: inhibit APICv/AVIC on changes to APIC ID
 or APIC base

Neither of these settings should be changed by the guest and it is
a burden to support it in the acceleration code, so just inhibit
this code instead.

Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
Message-Id: <20220606180829.102503-3-mlevitsk@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/include/asm/kvm_host.h |  8 ++++++++
 arch/x86/kvm/lapic.c            | 27 +++++++++++++++++++++++----
 arch/x86/kvm/svm/avic.c         |  4 +++-
 arch/x86/kvm/vmx/vmx.c          |  4 +++-
 4 files changed, 37 insertions(+), 6 deletions(-)

diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 1f9e47b895cf9..9217bd6cf0d14 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -1076,6 +1076,14 @@ enum kvm_apicv_inhibit {
 	 */
 	APICV_INHIBIT_REASON_BLOCKIRQ,
 
+	/*
+	 * For simplicity, the APIC acceleration is inhibited
+	 * first time either APIC ID or APIC base are changed by the guest
+	 * from their reset values.
+	 */
+	APICV_INHIBIT_REASON_APIC_ID_MODIFIED,
+	APICV_INHIBIT_REASON_APIC_BASE_MODIFIED,
+
 	/******************************************************/
 	/* INHIBITs that are relevant only to the AMD's AVIC. */
 	/******************************************************/
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index f1bdac3f5aa8a..0e68b4c937fcd 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2039,6 +2039,19 @@ static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
 	}
 }
 
+static void kvm_lapic_xapic_id_updated(struct kvm_lapic *apic)
+{
+	struct kvm *kvm = apic->vcpu->kvm;
+
+	if (KVM_BUG_ON(apic_x2apic_mode(apic), kvm))
+		return;
+
+	if (kvm_xapic_id(apic) == apic->vcpu->vcpu_id)
+		return;
+
+	kvm_set_apicv_inhibit(apic->vcpu->kvm, APICV_INHIBIT_REASON_APIC_ID_MODIFIED);
+}
+
 static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 {
 	int ret = 0;
@@ -2047,10 +2060,12 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 
 	switch (reg) {
 	case APIC_ID:		/* Local APIC ID */
-		if (!apic_x2apic_mode(apic))
+		if (!apic_x2apic_mode(apic)) {
 			kvm_apic_set_xapic_id(apic, val >> 24);
-		else
+			kvm_lapic_xapic_id_updated(apic);
+		} else {
 			ret = 1;
+		}
 		break;
 
 	case APIC_TASKPRI:
@@ -2336,8 +2351,10 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
 			     MSR_IA32_APICBASE_BASE;
 
 	if ((value & MSR_IA32_APICBASE_ENABLE) &&
-	     apic->base_address != APIC_DEFAULT_PHYS_BASE)
-		pr_warn_once("APIC base relocation is unsupported by KVM");
+	     apic->base_address != APIC_DEFAULT_PHYS_BASE) {
+		kvm_set_apicv_inhibit(apic->vcpu->kvm,
+				      APICV_INHIBIT_REASON_APIC_BASE_MODIFIED);
+	}
 }
 
 void kvm_apic_update_apicv(struct kvm_vcpu *vcpu)
@@ -2648,6 +2665,8 @@ static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
 			icr = __kvm_lapic_get_reg64(s->regs, APIC_ICR);
 			__kvm_lapic_set_reg(s->regs, APIC_ICR2, icr >> 32);
 		}
+	} else {
+		kvm_lapic_xapic_id_updated(vcpu->arch.apic);
 	}
 
 	return 0;
diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c
index 54fe03714f8a6..8dffd67f60862 100644
--- a/arch/x86/kvm/svm/avic.c
+++ b/arch/x86/kvm/svm/avic.c
@@ -910,7 +910,9 @@ bool avic_check_apicv_inhibit_reasons(enum kvm_apicv_inhibit reason)
 			  BIT(APICV_INHIBIT_REASON_PIT_REINJ) |
 			  BIT(APICV_INHIBIT_REASON_X2APIC) |
 			  BIT(APICV_INHIBIT_REASON_BLOCKIRQ) |
-			  BIT(APICV_INHIBIT_REASON_SEV);
+			  BIT(APICV_INHIBIT_REASON_SEV      |
+			  BIT(APICV_INHIBIT_REASON_APIC_ID_MODIFIED) |
+			  BIT(APICV_INHIBIT_REASON_APIC_BASE_MODIFIED));
 
 	return supported & BIT(reason);
 }
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 9bd86ecccdab5..553dd2317b9cb 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -7709,7 +7709,9 @@ static bool vmx_check_apicv_inhibit_reasons(enum kvm_apicv_inhibit reason)
 	ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
 			  BIT(APICV_INHIBIT_REASON_ABSENT) |
 			  BIT(APICV_INHIBIT_REASON_HYPERV) |
-			  BIT(APICV_INHIBIT_REASON_BLOCKIRQ);
+			  BIT(APICV_INHIBIT_REASON_BLOCKIRQ) |
+			  BIT(APICV_INHIBIT_REASON_APIC_ID_MODIFIED) |
+			  BIT(APICV_INHIBIT_REASON_APIC_BASE_MODIFIED);
 
 	return supported & BIT(reason);
 }
-- 
GitLab


From f5f9089f76ddc882b915c5d78e4beeb48dcabd1b Mon Sep 17 00:00:00 2001
From: Maxim Levitsky <mlevitsk@redhat.com>
Date: Mon, 6 Jun 2022 21:08:25 +0300
Subject: [PATCH 0382/1731] KVM: x86: SVM: remove avic's broken code that
 updated APIC ID

AVIC is now inhibited if the guest changes the apic id,
and therefore this code is no longer needed.

There are several ways this code was broken, including:

1. a vCPU was only allowed to change its apic id to an apic id
of an existing vCPU.

2. After such change, the vCPU whose apic id entry was overwritten,
could not correctly change its own apic id, because its own
entry is already overwritten.

Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
Message-Id: <20220606180829.102503-4-mlevitsk@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/svm/avic.c | 35 -----------------------------------
 1 file changed, 35 deletions(-)

diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c
index 8dffd67f60862..072e2c8cc66aa 100644
--- a/arch/x86/kvm/svm/avic.c
+++ b/arch/x86/kvm/svm/avic.c
@@ -508,35 +508,6 @@ static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
 	return ret;
 }
 
-static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
-{
-	u64 *old, *new;
-	struct vcpu_svm *svm = to_svm(vcpu);
-	u32 id = kvm_xapic_id(vcpu->arch.apic);
-
-	if (vcpu->vcpu_id == id)
-		return 0;
-
-	old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
-	new = avic_get_physical_id_entry(vcpu, id);
-	if (!new || !old)
-		return 1;
-
-	/* We need to move physical_id_entry to new offset */
-	*new = *old;
-	*old = 0ULL;
-	to_svm(vcpu)->avic_physical_id_cache = new;
-
-	/*
-	 * Also update the guest physical APIC ID in the logical
-	 * APIC ID table entry if already setup the LDR.
-	 */
-	if (svm->ldr_reg)
-		avic_handle_ldr_update(vcpu);
-
-	return 0;
-}
-
 static void avic_handle_dfr_update(struct kvm_vcpu *vcpu)
 {
 	struct vcpu_svm *svm = to_svm(vcpu);
@@ -555,10 +526,6 @@ static int avic_unaccel_trap_write(struct kvm_vcpu *vcpu)
 				AVIC_UNACCEL_ACCESS_OFFSET_MASK;
 
 	switch (offset) {
-	case APIC_ID:
-		if (avic_handle_apic_id_update(vcpu))
-			return 0;
-		break;
 	case APIC_LDR:
 		if (avic_handle_ldr_update(vcpu))
 			return 0;
@@ -650,8 +617,6 @@ int avic_init_vcpu(struct vcpu_svm *svm)
 
 void avic_apicv_post_state_restore(struct kvm_vcpu *vcpu)
 {
-	if (avic_handle_apic_id_update(vcpu) != 0)
-		return;
 	avic_handle_dfr_update(vcpu);
 	avic_handle_ldr_update(vcpu);
 }
-- 
GitLab


From 603ccef42ce9f07840cf4c0448f3261413460b07 Mon Sep 17 00:00:00 2001
From: Maxim Levitsky <mlevitsk@redhat.com>
Date: Mon, 6 Jun 2022 21:08:26 +0300
Subject: [PATCH 0383/1731] KVM: x86: SVM: fix avic_kick_target_vcpus_fast
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

There are two issues in avic_kick_target_vcpus_fast

1. It is legal to issue an IPI request with APIC_DEST_NOSHORT
   and a physical destination of 0xFF (or 0xFFFFFFFF in case of x2apic),
   which must be treated as a broadcast destination.

   Fix this by explicitly checking for it.
   Also don’t use ‘index’ in this case as it gives no new information.

2. It is legal to issue a logical IPI request to more than one target.
   Index field only provides index in physical id table of first
   such target and therefore can't be used before we are sure
   that only a single target was addressed.

   Instead, parse the ICRL/ICRH, double check that a unicast interrupt
   was requested, and use that info to figure out the physical id
   of the target vCPU.
   At that point there is no need to use the index field as well.

In addition to fixing the above	issues,	also skip the call to
kvm_apic_match_dest.

It is possible to do this now, because now as long as AVIC is not
inhibited, it is guaranteed that none of the vCPUs changed their
apic id from its default value.

This fixes boot of windows guest with AVIC enabled because it uses
IPI with 0xFF destination and no destination shorthand.

Fixes: 7223fd2d5338 ("KVM: SVM: Use target APIC ID to complete AVIC IRQs when possible")
Cc: stable@vger.kernel.org

Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
Message-Id: <20220606180829.102503-5-mlevitsk@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/svm/avic.c | 105 ++++++++++++++++++++++++++--------------
 1 file changed, 69 insertions(+), 36 deletions(-)

diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c
index 072e2c8cc66aa..5d98ac575dedc 100644
--- a/arch/x86/kvm/svm/avic.c
+++ b/arch/x86/kvm/svm/avic.c
@@ -291,58 +291,91 @@ void avic_ring_doorbell(struct kvm_vcpu *vcpu)
 static int avic_kick_target_vcpus_fast(struct kvm *kvm, struct kvm_lapic *source,
 				       u32 icrl, u32 icrh, u32 index)
 {
-	u32 dest, apic_id;
-	struct kvm_vcpu *vcpu;
+	u32 l1_physical_id, dest;
+	struct kvm_vcpu *target_vcpu;
 	int dest_mode = icrl & APIC_DEST_MASK;
 	int shorthand = icrl & APIC_SHORT_MASK;
 	struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
-	u32 *avic_logical_id_table = page_address(kvm_svm->avic_logical_id_table_page);
 
 	if (shorthand != APIC_DEST_NOSHORT)
 		return -EINVAL;
 
-	/*
-	 * The AVIC incomplete IPI #vmexit info provides index into
-	 * the physical APIC ID table, which can be used to derive
-	 * guest physical APIC ID.
-	 */
+	if (apic_x2apic_mode(source))
+		dest = icrh;
+	else
+		dest = GET_APIC_DEST_FIELD(icrh);
+
 	if (dest_mode == APIC_DEST_PHYSICAL) {
-		apic_id = index;
+		/* broadcast destination, use slow path */
+		if (apic_x2apic_mode(source) && dest == X2APIC_BROADCAST)
+			return -EINVAL;
+		if (!apic_x2apic_mode(source) && dest == APIC_BROADCAST)
+			return -EINVAL;
+
+		l1_physical_id = dest;
+
+		if (WARN_ON_ONCE(l1_physical_id != index))
+			return -EINVAL;
+
 	} else {
-		if (!apic_x2apic_mode(source)) {
-			/* For xAPIC logical mode, the index is for logical APIC table. */
-			apic_id = avic_logical_id_table[index] & 0x1ff;
+		u32 bitmap, cluster;
+		int logid_index;
+
+		if (apic_x2apic_mode(source)) {
+			/* 16 bit dest mask, 16 bit cluster id */
+			bitmap = dest & 0xFFFF0000;
+			cluster = (dest >> 16) << 4;
+		} else if (kvm_lapic_get_reg(source, APIC_DFR) == APIC_DFR_FLAT) {
+			/* 8 bit dest mask*/
+			bitmap = dest;
+			cluster = 0;
 		} else {
-			return -EINVAL;
+			/* 4 bit desk mask, 4 bit cluster id */
+			bitmap = dest & 0xF;
+			cluster = (dest >> 4) << 2;
 		}
-	}
 
-	/*
-	 * Assuming vcpu ID is the same as physical apic ID,
-	 * and use it to retrieve the target vCPU.
-	 */
-	vcpu = kvm_get_vcpu_by_id(kvm, apic_id);
-	if (!vcpu)
-		return -EINVAL;
+		if (unlikely(!bitmap))
+			/* guest bug: nobody to send the logical interrupt to */
+			return 0;
 
-	if (apic_x2apic_mode(vcpu->arch.apic))
-		dest = icrh;
-	else
-		dest = GET_APIC_DEST_FIELD(icrh);
+		if (!is_power_of_2(bitmap))
+			/* multiple logical destinations, use slow path */
+			return -EINVAL;
 
-	/*
-	 * Try matching the destination APIC ID with the vCPU.
-	 */
-	if (kvm_apic_match_dest(vcpu, source, shorthand, dest, dest_mode)) {
-		vcpu->arch.apic->irr_pending = true;
-		svm_complete_interrupt_delivery(vcpu,
-						icrl & APIC_MODE_MASK,
-						icrl & APIC_INT_LEVELTRIG,
-						icrl & APIC_VECTOR_MASK);
-		return 0;
+		logid_index = cluster + __ffs(bitmap);
+
+		if (apic_x2apic_mode(source)) {
+			l1_physical_id = logid_index;
+		} else {
+			u32 *avic_logical_id_table =
+				page_address(kvm_svm->avic_logical_id_table_page);
+
+			u32 logid_entry = avic_logical_id_table[logid_index];
+
+			if (WARN_ON_ONCE(index != logid_index))
+				return -EINVAL;
+
+			/* guest bug: non existing/reserved logical destination */
+			if (unlikely(!(logid_entry & AVIC_LOGICAL_ID_ENTRY_VALID_MASK)))
+				return 0;
+
+			l1_physical_id = logid_entry &
+					 AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
+		}
 	}
 
-	return -EINVAL;
+	target_vcpu = kvm_get_vcpu_by_id(kvm, l1_physical_id);
+	if (unlikely(!target_vcpu))
+		/* guest bug: non existing vCPU is a target of this IPI*/
+		return 0;
+
+	target_vcpu->arch.apic->irr_pending = true;
+	svm_complete_interrupt_delivery(target_vcpu,
+					icrl & APIC_MODE_MASK,
+					icrl & APIC_INT_LEVELTRIG,
+					icrl & APIC_VECTOR_MASK);
+	return 0;
 }
 
 static void avic_kick_target_vcpus(struct kvm *kvm, struct kvm_lapic *source,
-- 
GitLab


From 66c768d30e64e1280520f34dbef83419f55f3459 Mon Sep 17 00:00:00 2001
From: Maxim Levitsky <mlevitsk@redhat.com>
Date: Mon, 6 Jun 2022 21:08:27 +0300
Subject: [PATCH 0384/1731] KVM: x86: disable preemption while updating apicv
 inhibition

Currently nothing prevents preemption in kvm_vcpu_update_apicv.

On SVM, If the preemption happens after we update the
vcpu->arch.apicv_active, the preemption itself will
'update' the inhibition since the AVIC will be first disabled
on vCPU unload and then enabled, when the current task
is loaded again.

Then we will try to update it again, which will lead to a warning
in __avic_vcpu_load, that the AVIC is already enabled.

Fix this by disabling preemption in this code.

Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
Message-Id: <20220606180829.102503-6-mlevitsk@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/x86.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 03fbfbbec460f..158b2e135efce 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -9850,6 +9850,7 @@ void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
 		return;
 
 	down_read(&vcpu->kvm->arch.apicv_update_lock);
+	preempt_disable();
 
 	activate = kvm_vcpu_apicv_activated(vcpu);
 
@@ -9870,6 +9871,7 @@ void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
 		kvm_make_request(KVM_REQ_EVENT, vcpu);
 
 out:
+	preempt_enable();
 	up_read(&vcpu->kvm->arch.apicv_update_lock);
 }
 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
-- 
GitLab


From 18869f26df1a11ed11031dfb7392bc7d774062e8 Mon Sep 17 00:00:00 2001
From: Maxim Levitsky <mlevitsk@redhat.com>
Date: Mon, 6 Jun 2022 21:08:28 +0300
Subject: [PATCH 0385/1731] KVM: x86: disable preemption around the call to
 kvm_arch_vcpu_{un|}blocking

On SVM, if preemption happens right after the call to finish_rcuwait
but before call to kvm_arch_vcpu_unblocking on SVM/AVIC, it itself
will re-enable AVIC, and then we will try to re-enable it again
in kvm_arch_vcpu_unblocking which will lead to a warning
in __avic_vcpu_load.

The same problem can happen if the vCPU is preempted right after the call
to kvm_arch_vcpu_blocking but before the call to prepare_to_rcuwait
and in this case, we will end up with AVIC enabled during sleep -
Ooops.

Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
Message-Id: <20220606180829.102503-7-mlevitsk@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 virt/kvm/kvm_main.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c
index 44c47670447aa..a49df8988cd6a 100644
--- a/virt/kvm/kvm_main.c
+++ b/virt/kvm/kvm_main.c
@@ -3328,9 +3328,11 @@ bool kvm_vcpu_block(struct kvm_vcpu *vcpu)
 
 	vcpu->stat.generic.blocking = 1;
 
+	preempt_disable();
 	kvm_arch_vcpu_blocking(vcpu);
-
 	prepare_to_rcuwait(wait);
+	preempt_enable();
+
 	for (;;) {
 		set_current_state(TASK_INTERRUPTIBLE);
 
@@ -3340,9 +3342,11 @@ bool kvm_vcpu_block(struct kvm_vcpu *vcpu)
 		waited = true;
 		schedule();
 	}
-	finish_rcuwait(wait);
 
+	preempt_disable();
+	finish_rcuwait(wait);
 	kvm_arch_vcpu_unblocking(vcpu);
+	preempt_enable();
 
 	vcpu->stat.generic.blocking = 0;
 
-- 
GitLab


From ba8ec273240a7a67819b5957c8d06a267ec54db7 Mon Sep 17 00:00:00 2001
From: Maxim Levitsky <mlevitsk@redhat.com>
Date: Mon, 6 Jun 2022 21:08:29 +0300
Subject: [PATCH 0386/1731] KVM: x86: SVM: drop preempt-safe wrappers for
 avic_vcpu_load/put

Now that these functions are always called with preemption disabled,
remove the preempt_disable()/preempt_enable() pair inside them.

No functional change intended.

Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
Message-Id: <20220606180829.102503-8-mlevitsk@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/svm/avic.c | 27 ++++-----------------------
 arch/x86/kvm/svm/svm.c  |  4 ++--
 arch/x86/kvm/svm/svm.h  |  4 ++--
 3 files changed, 8 insertions(+), 27 deletions(-)

diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c
index 5d98ac575dedc..5542d8959e114 100644
--- a/arch/x86/kvm/svm/avic.c
+++ b/arch/x86/kvm/svm/avic.c
@@ -946,7 +946,7 @@ out:
 	return ret;
 }
 
-void __avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
+void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 {
 	u64 entry;
 	int h_physical_id = kvm_cpu_get_apicid(cpu);
@@ -978,7 +978,7 @@ void __avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 	avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, true);
 }
 
-void __avic_vcpu_put(struct kvm_vcpu *vcpu)
+void avic_vcpu_put(struct kvm_vcpu *vcpu)
 {
 	u64 entry;
 	struct vcpu_svm *svm = to_svm(vcpu);
@@ -997,25 +997,6 @@ void __avic_vcpu_put(struct kvm_vcpu *vcpu)
 	WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
 }
 
-static void avic_vcpu_load(struct kvm_vcpu *vcpu)
-{
-	int cpu = get_cpu();
-
-	WARN_ON(cpu != vcpu->cpu);
-
-	__avic_vcpu_load(vcpu, cpu);
-
-	put_cpu();
-}
-
-static void avic_vcpu_put(struct kvm_vcpu *vcpu)
-{
-	preempt_disable();
-
-	__avic_vcpu_put(vcpu);
-
-	preempt_enable();
-}
 
 void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
 {
@@ -1042,7 +1023,7 @@ void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
 	vmcb_mark_dirty(vmcb, VMCB_AVIC);
 
 	if (activated)
-		avic_vcpu_load(vcpu);
+		avic_vcpu_load(vcpu, vcpu->cpu);
 	else
 		avic_vcpu_put(vcpu);
 
@@ -1075,5 +1056,5 @@ void avic_vcpu_unblocking(struct kvm_vcpu *vcpu)
 	if (!kvm_vcpu_apicv_active(vcpu))
 		return;
 
-	avic_vcpu_load(vcpu);
+	avic_vcpu_load(vcpu, vcpu->cpu);
 }
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 1dc02cdf69602..1ac66fbceaa1d 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -1400,13 +1400,13 @@ static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 		indirect_branch_prediction_barrier();
 	}
 	if (kvm_vcpu_apicv_active(vcpu))
-		__avic_vcpu_load(vcpu, cpu);
+		avic_vcpu_load(vcpu, cpu);
 }
 
 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 {
 	if (kvm_vcpu_apicv_active(vcpu))
-		__avic_vcpu_put(vcpu);
+		avic_vcpu_put(vcpu);
 
 	svm_prepare_host_switch(vcpu);
 
diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h
index 500348c1cb350..1bddd336a27e0 100644
--- a/arch/x86/kvm/svm/svm.h
+++ b/arch/x86/kvm/svm/svm.h
@@ -610,8 +610,8 @@ void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb *vmcb);
 int avic_incomplete_ipi_interception(struct kvm_vcpu *vcpu);
 int avic_unaccelerated_access_interception(struct kvm_vcpu *vcpu);
 int avic_init_vcpu(struct vcpu_svm *svm);
-void __avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
-void __avic_vcpu_put(struct kvm_vcpu *vcpu);
+void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
+void avic_vcpu_put(struct kvm_vcpu *vcpu);
 void avic_apicv_post_state_restore(struct kvm_vcpu *vcpu);
 void avic_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
 void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu);
-- 
GitLab


From e3cdaab5ff022874e65df80ae8b8382ccc0a4fe0 Mon Sep 17 00:00:00 2001
From: Paolo Bonzini <pbonzini@redhat.com>
Date: Tue, 31 May 2022 13:57:32 -0400
Subject: [PATCH 0387/1731] KVM: x86: SVM: fix nested PAUSE filtering when L0
 intercepts PAUSE

Commit 74fd41ed16fd ("KVM: x86: nSVM: support PAUSE filtering when L0
doesn't intercept PAUSE") introduced passthrough support for nested pause
filtering, (when the host doesn't intercept PAUSE) (either disabled with
kvm module param, or disabled with '-overcommit cpu-pm=on')

Before this commit, L1 KVM didn't intercept PAUSE at all; afterwards,
the feature was exposed as supported by KVM cpuid unconditionally, thus
if L1 could try to use it even when the L0 KVM can't really support it.

In this case the fallback caused KVM to intercept each PAUSE instruction;
in some cases, such intercept can slow down the nested guest so much
that it can fail to boot.  Instead, before the problematic commit KVM
was already setting both thresholds to 0 in vmcb02, but after the first
userspace VM exit shrink_ple_window was called and would reset the
pause_filter_count to the default value.

To fix this, change the fallback strategy - ignore the guest threshold
values, but use/update the host threshold values unless the guest
specifically requests disabling PAUSE filtering (either simple or
advanced).

Also fix a minor bug: on nested VM exit, when PAUSE filter counter
were copied back to vmcb01, a dirty bit was not set.

Thanks a lot to Suravee Suthikulpanit for debugging this!

Fixes: 74fd41ed16fd ("KVM: x86: nSVM: support PAUSE filtering when L0 doesn't intercept PAUSE")
Reported-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Tested-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Co-developed-by: Maxim Levitsky <mlevitsk@redhat.com>
Message-Id: <20220518072709.730031-1-mlevitsk@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/svm/nested.c | 39 +++++++++++++++++++++------------------
 arch/x86/kvm/svm/svm.c    |  4 ++--
 2 files changed, 23 insertions(+), 20 deletions(-)

diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c
index 3361258640a27..ba7cd26f438fc 100644
--- a/arch/x86/kvm/svm/nested.c
+++ b/arch/x86/kvm/svm/nested.c
@@ -616,6 +616,8 @@ static void nested_vmcb02_prepare_control(struct vcpu_svm *svm)
 	struct kvm_vcpu *vcpu = &svm->vcpu;
 	struct vmcb *vmcb01 = svm->vmcb01.ptr;
 	struct vmcb *vmcb02 = svm->nested.vmcb02.ptr;
+	u32 pause_count12;
+	u32 pause_thresh12;
 
 	/*
 	 * Filled at exit: exit_code, exit_code_hi, exit_info_1, exit_info_2,
@@ -671,27 +673,25 @@ static void nested_vmcb02_prepare_control(struct vcpu_svm *svm)
 	if (!nested_vmcb_needs_vls_intercept(svm))
 		vmcb02->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
 
+	pause_count12 = svm->pause_filter_enabled ? svm->nested.ctl.pause_filter_count : 0;
+	pause_thresh12 = svm->pause_threshold_enabled ? svm->nested.ctl.pause_filter_thresh : 0;
 	if (kvm_pause_in_guest(svm->vcpu.kvm)) {
-		/* use guest values since host doesn't use them */
-		vmcb02->control.pause_filter_count =
-				svm->pause_filter_enabled ?
-				svm->nested.ctl.pause_filter_count : 0;
+		/* use guest values since host doesn't intercept PAUSE */
+		vmcb02->control.pause_filter_count = pause_count12;
+		vmcb02->control.pause_filter_thresh = pause_thresh12;
 
-		vmcb02->control.pause_filter_thresh =
-				svm->pause_threshold_enabled ?
-				svm->nested.ctl.pause_filter_thresh : 0;
-
-	} else if (!vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_PAUSE)) {
-		/* use host values when guest doesn't use them */
+	} else {
+		/* start from host values otherwise */
 		vmcb02->control.pause_filter_count = vmcb01->control.pause_filter_count;
 		vmcb02->control.pause_filter_thresh = vmcb01->control.pause_filter_thresh;
-	} else {
-		/*
-		 * Intercept every PAUSE otherwise and
-		 * ignore both host and guest values
-		 */
-		vmcb02->control.pause_filter_count = 0;
-		vmcb02->control.pause_filter_thresh = 0;
+
+		/* ... but ensure filtering is disabled if so requested.  */
+		if (vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_PAUSE)) {
+			if (!pause_count12)
+				vmcb02->control.pause_filter_count = 0;
+			if (!pause_thresh12)
+				vmcb02->control.pause_filter_thresh = 0;
+		}
 	}
 
 	nested_svm_transition_tlb_flush(vcpu);
@@ -951,8 +951,11 @@ int nested_svm_vmexit(struct vcpu_svm *svm)
 	vmcb12->control.event_inj         = svm->nested.ctl.event_inj;
 	vmcb12->control.event_inj_err     = svm->nested.ctl.event_inj_err;
 
-	if (!kvm_pause_in_guest(vcpu->kvm) && vmcb02->control.pause_filter_count)
+	if (!kvm_pause_in_guest(vcpu->kvm)) {
 		vmcb01->control.pause_filter_count = vmcb02->control.pause_filter_count;
+		vmcb_mark_dirty(vmcb01, VMCB_INTERCEPTS);
+
+	}
 
 	nested_svm_copy_common_state(svm->nested.vmcb02.ptr, svm->vmcb01.ptr);
 
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 1ac66fbceaa1d..87da90360bc76 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -921,7 +921,7 @@ static void grow_ple_window(struct kvm_vcpu *vcpu)
 	struct vmcb_control_area *control = &svm->vmcb->control;
 	int old = control->pause_filter_count;
 
-	if (kvm_pause_in_guest(vcpu->kvm) || !old)
+	if (kvm_pause_in_guest(vcpu->kvm))
 		return;
 
 	control->pause_filter_count = __grow_ple_window(old,
@@ -942,7 +942,7 @@ static void shrink_ple_window(struct kvm_vcpu *vcpu)
 	struct vmcb_control_area *control = &svm->vmcb->control;
 	int old = control->pause_filter_count;
 
-	if (kvm_pause_in_guest(vcpu->kvm) || !old)
+	if (kvm_pause_in_guest(vcpu->kvm))
 		return;
 
 	control->pause_filter_count =
-- 
GitLab


From 4ee602e78d706e740a48be9b6ddb239df4a113b5 Mon Sep 17 00:00:00 2001
From: David Matlack <dmatlack@google.com>
Date: Fri, 20 May 2022 23:32:39 +0000
Subject: [PATCH 0388/1731] KVM: selftests: Replace x86_page_size with
 PG_LEVEL_XX

x86_page_size is an enum used to communicate the desired page size with
which to map a range of memory. Under the hood they just encode the
desired level at which to map the page. This ends up being clunky in a
few ways:

 - The name suggests it encodes the size of the page rather than the
   level.
 - In other places in x86_64/processor.c we just use a raw int to encode
   the level.

Simplify this by adopting the kernel style of PG_LEVEL_XX enums and pass
around raw ints when referring to the level. This makes the code easier
to understand since these macros are very common in KVM MMU code.

Signed-off-by: David Matlack <dmatlack@google.com>
Message-Id: <20220520233249.3776001-2-dmatlack@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 .../selftests/kvm/include/x86_64/processor.h  | 18 +++++++----
 .../selftests/kvm/lib/x86_64/processor.c      | 31 +++++++++----------
 .../selftests/kvm/max_guest_memory_test.c     |  2 +-
 .../selftests/kvm/x86_64/mmu_role_test.c      |  2 +-
 4 files changed, 29 insertions(+), 24 deletions(-)

diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools/testing/selftests/kvm/include/x86_64/processor.h
index d0d51adec76eb..273c70e91647d 100644
--- a/tools/testing/selftests/kvm/include/x86_64/processor.h
+++ b/tools/testing/selftests/kvm/include/x86_64/processor.h
@@ -482,13 +482,19 @@ void vcpu_set_hv_cpuid(struct kvm_vm *vm, uint32_t vcpuid);
 struct kvm_cpuid2 *vcpu_get_supported_hv_cpuid(struct kvm_vm *vm, uint32_t vcpuid);
 void vm_xsave_req_perm(int bit);
 
-enum x86_page_size {
-	X86_PAGE_SIZE_4K = 0,
-	X86_PAGE_SIZE_2M,
-	X86_PAGE_SIZE_1G,
+enum pg_level {
+	PG_LEVEL_NONE,
+	PG_LEVEL_4K,
+	PG_LEVEL_2M,
+	PG_LEVEL_1G,
+	PG_LEVEL_512G,
+	PG_LEVEL_NUM
 };
-void __virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr,
-		   enum x86_page_size page_size);
+
+#define PG_LEVEL_SHIFT(_level) ((_level - 1) * 9 + 12)
+#define PG_LEVEL_SIZE(_level) (1ull << PG_LEVEL_SHIFT(_level))
+
+void __virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, int level);
 
 /*
  * Basic CPU control in CR0
diff --git a/tools/testing/selftests/kvm/lib/x86_64/processor.c b/tools/testing/selftests/kvm/lib/x86_64/processor.c
index 33ea5e9955d9b..ead7011ee8f61 100644
--- a/tools/testing/selftests/kvm/lib/x86_64/processor.c
+++ b/tools/testing/selftests/kvm/lib/x86_64/processor.c
@@ -158,7 +158,7 @@ static void *virt_get_pte(struct kvm_vm *vm, uint64_t pt_pfn, uint64_t vaddr,
 			  int level)
 {
 	uint64_t *page_table = addr_gpa2hva(vm, pt_pfn << vm->page_shift);
-	int index = vaddr >> (vm->page_shift + level * 9) & 0x1ffu;
+	int index = (vaddr >> PG_LEVEL_SHIFT(level)) & 0x1ffu;
 
 	return &page_table[index];
 }
@@ -167,14 +167,14 @@ static uint64_t *virt_create_upper_pte(struct kvm_vm *vm,
 				       uint64_t pt_pfn,
 				       uint64_t vaddr,
 				       uint64_t paddr,
-				       int level,
-				       enum x86_page_size page_size)
+				       int current_level,
+				       int target_level)
 {
-	uint64_t *pte = virt_get_pte(vm, pt_pfn, vaddr, level);
+	uint64_t *pte = virt_get_pte(vm, pt_pfn, vaddr, current_level);
 
 	if (!(*pte & PTE_PRESENT_MASK)) {
 		*pte = PTE_PRESENT_MASK | PTE_WRITABLE_MASK;
-		if (level == page_size)
+		if (current_level == target_level)
 			*pte |= PTE_LARGE_MASK | (paddr & PHYSICAL_PAGE_MASK);
 		else
 			*pte |= vm_alloc_page_table(vm) & PHYSICAL_PAGE_MASK;
@@ -184,20 +184,19 @@ static uint64_t *virt_create_upper_pte(struct kvm_vm *vm,
 		 * a hugepage at this level, and that there isn't a hugepage at
 		 * this level.
 		 */
-		TEST_ASSERT(level != page_size,
+		TEST_ASSERT(current_level != target_level,
 			    "Cannot create hugepage at level: %u, vaddr: 0x%lx\n",
-			    page_size, vaddr);
+			    current_level, vaddr);
 		TEST_ASSERT(!(*pte & PTE_LARGE_MASK),
 			    "Cannot create page table at level: %u, vaddr: 0x%lx\n",
-			    level, vaddr);
+			    current_level, vaddr);
 	}
 	return pte;
 }
 
-void __virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr,
-		   enum x86_page_size page_size)
+void __virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, int level)
 {
-	const uint64_t pg_size = 1ull << ((page_size * 9) + 12);
+	const uint64_t pg_size = PG_LEVEL_SIZE(level);
 	uint64_t *pml4e, *pdpe, *pde;
 	uint64_t *pte;
 
@@ -222,20 +221,20 @@ void __virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr,
 	 * early if a hugepage was created.
 	 */
 	pml4e = virt_create_upper_pte(vm, vm->pgd >> vm->page_shift,
-				      vaddr, paddr, 3, page_size);
+				      vaddr, paddr, PG_LEVEL_512G, level);
 	if (*pml4e & PTE_LARGE_MASK)
 		return;
 
-	pdpe = virt_create_upper_pte(vm, PTE_GET_PFN(*pml4e), vaddr, paddr, 2, page_size);
+	pdpe = virt_create_upper_pte(vm, PTE_GET_PFN(*pml4e), vaddr, paddr, PG_LEVEL_1G, level);
 	if (*pdpe & PTE_LARGE_MASK)
 		return;
 
-	pde = virt_create_upper_pte(vm, PTE_GET_PFN(*pdpe), vaddr, paddr, 1, page_size);
+	pde = virt_create_upper_pte(vm, PTE_GET_PFN(*pdpe), vaddr, paddr, PG_LEVEL_2M, level);
 	if (*pde & PTE_LARGE_MASK)
 		return;
 
 	/* Fill in page table entry. */
-	pte = virt_get_pte(vm, PTE_GET_PFN(*pde), vaddr, 0);
+	pte = virt_get_pte(vm, PTE_GET_PFN(*pde), vaddr, PG_LEVEL_4K);
 	TEST_ASSERT(!(*pte & PTE_PRESENT_MASK),
 		    "PTE already present for 4k page at vaddr: 0x%lx\n", vaddr);
 	*pte = PTE_PRESENT_MASK | PTE_WRITABLE_MASK | (paddr & PHYSICAL_PAGE_MASK);
@@ -243,7 +242,7 @@ void __virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr,
 
 void virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr)
 {
-	__virt_pg_map(vm, vaddr, paddr, X86_PAGE_SIZE_4K);
+	__virt_pg_map(vm, vaddr, paddr, PG_LEVEL_4K);
 }
 
 static uint64_t *_vm_get_page_table_entry(struct kvm_vm *vm, int vcpuid,
diff --git a/tools/testing/selftests/kvm/max_guest_memory_test.c b/tools/testing/selftests/kvm/max_guest_memory_test.c
index 3875c4b23a04f..15f046e19cb2c 100644
--- a/tools/testing/selftests/kvm/max_guest_memory_test.c
+++ b/tools/testing/selftests/kvm/max_guest_memory_test.c
@@ -244,7 +244,7 @@ int main(int argc, char *argv[])
 #ifdef __x86_64__
 		/* Identity map memory in the guest using 1gb pages. */
 		for (i = 0; i < slot_size; i += size_1gb)
-			__virt_pg_map(vm, gpa + i, gpa + i, X86_PAGE_SIZE_1G);
+			__virt_pg_map(vm, gpa + i, gpa + i, PG_LEVEL_1G);
 #else
 		for (i = 0; i < slot_size; i += vm_get_page_size(vm))
 			virt_pg_map(vm, gpa + i, gpa + i);
diff --git a/tools/testing/selftests/kvm/x86_64/mmu_role_test.c b/tools/testing/selftests/kvm/x86_64/mmu_role_test.c
index da2325fcad87b..bdecd532f9356 100644
--- a/tools/testing/selftests/kvm/x86_64/mmu_role_test.c
+++ b/tools/testing/selftests/kvm/x86_64/mmu_role_test.c
@@ -35,7 +35,7 @@ static void mmu_role_test(u32 *cpuid_reg, u32 evil_cpuid_val)
 	run = vcpu_state(vm, VCPU_ID);
 
 	/* Map 1gb page without a backing memlot. */
-	__virt_pg_map(vm, MMIO_GPA, MMIO_GPA, X86_PAGE_SIZE_1G);
+	__virt_pg_map(vm, MMIO_GPA, MMIO_GPA, PG_LEVEL_1G);
 
 	r = _vcpu_run(vm, VCPU_ID);
 
-- 
GitLab


From c5a0ccec4cb4edde8e5b7e369dbe4d169b111e42 Mon Sep 17 00:00:00 2001
From: David Matlack <dmatlack@google.com>
Date: Fri, 20 May 2022 23:32:40 +0000
Subject: [PATCH 0389/1731] KVM: selftests: Add option to create 2M and 1G EPT
 mappings

The current EPT mapping code in the selftests only supports mapping 4K
pages. This commit extends that support with an option to map at 2M or
1G. This will be used in a future commit to create large page mappings
to test eager page splitting.

No functional change intended.

Signed-off-by: David Matlack <dmatlack@google.com>
Message-Id: <20220520233249.3776001-3-dmatlack@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/lib/x86_64/vmx.c | 110 ++++++++++---------
 1 file changed, 60 insertions(+), 50 deletions(-)

diff --git a/tools/testing/selftests/kvm/lib/x86_64/vmx.c b/tools/testing/selftests/kvm/lib/x86_64/vmx.c
index d089d8b850b5c..fdc1e6deb9229 100644
--- a/tools/testing/selftests/kvm/lib/x86_64/vmx.c
+++ b/tools/testing/selftests/kvm/lib/x86_64/vmx.c
@@ -392,80 +392,90 @@ void nested_vmx_check_supported(void)
 	}
 }
 
-void nested_pg_map(struct vmx_pages *vmx, struct kvm_vm *vm,
-		   uint64_t nested_paddr, uint64_t paddr)
+static void nested_create_pte(struct kvm_vm *vm,
+			      struct eptPageTableEntry *pte,
+			      uint64_t nested_paddr,
+			      uint64_t paddr,
+			      int current_level,
+			      int target_level)
+{
+	if (!pte->readable) {
+		pte->writable = true;
+		pte->readable = true;
+		pte->executable = true;
+		pte->page_size = (current_level == target_level);
+		if (pte->page_size)
+			pte->address = paddr >> vm->page_shift;
+		else
+			pte->address = vm_alloc_page_table(vm) >> vm->page_shift;
+	} else {
+		/*
+		 * Entry already present.  Assert that the caller doesn't want
+		 * a hugepage at this level, and that there isn't a hugepage at
+		 * this level.
+		 */
+		TEST_ASSERT(current_level != target_level,
+			    "Cannot create hugepage at level: %u, nested_paddr: 0x%lx\n",
+			    current_level, nested_paddr);
+		TEST_ASSERT(!pte->page_size,
+			    "Cannot create page table at level: %u, nested_paddr: 0x%lx\n",
+			    current_level, nested_paddr);
+	}
+}
+
+
+void __nested_pg_map(struct vmx_pages *vmx, struct kvm_vm *vm,
+		     uint64_t nested_paddr, uint64_t paddr, int target_level)
 {
-	uint16_t index[4];
-	struct eptPageTableEntry *pml4e;
+	const uint64_t page_size = PG_LEVEL_SIZE(target_level);
+	struct eptPageTableEntry *pt = vmx->eptp_hva, *pte;
+	uint16_t index;
 
 	TEST_ASSERT(vm->mode == VM_MODE_PXXV48_4K, "Attempt to use "
 		    "unknown or unsupported guest mode, mode: 0x%x", vm->mode);
 
-	TEST_ASSERT((nested_paddr % vm->page_size) == 0,
+	TEST_ASSERT((nested_paddr % page_size) == 0,
 		    "Nested physical address not on page boundary,\n"
-		    "  nested_paddr: 0x%lx vm->page_size: 0x%x",
-		    nested_paddr, vm->page_size);
+		    "  nested_paddr: 0x%lx page_size: 0x%lx",
+		    nested_paddr, page_size);
 	TEST_ASSERT((nested_paddr >> vm->page_shift) <= vm->max_gfn,
 		    "Physical address beyond beyond maximum supported,\n"
 		    "  nested_paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
 		    paddr, vm->max_gfn, vm->page_size);
-	TEST_ASSERT((paddr % vm->page_size) == 0,
+	TEST_ASSERT((paddr % page_size) == 0,
 		    "Physical address not on page boundary,\n"
-		    "  paddr: 0x%lx vm->page_size: 0x%x",
-		    paddr, vm->page_size);
+		    "  paddr: 0x%lx page_size: 0x%lx",
+		    paddr, page_size);
 	TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn,
 		    "Physical address beyond beyond maximum supported,\n"
 		    "  paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
 		    paddr, vm->max_gfn, vm->page_size);
 
-	index[0] = (nested_paddr >> 12) & 0x1ffu;
-	index[1] = (nested_paddr >> 21) & 0x1ffu;
-	index[2] = (nested_paddr >> 30) & 0x1ffu;
-	index[3] = (nested_paddr >> 39) & 0x1ffu;
-
-	/* Allocate page directory pointer table if not present. */
-	pml4e = vmx->eptp_hva;
-	if (!pml4e[index[3]].readable) {
-		pml4e[index[3]].address = vm_alloc_page_table(vm) >> vm->page_shift;
-		pml4e[index[3]].writable = true;
-		pml4e[index[3]].readable = true;
-		pml4e[index[3]].executable = true;
-	}
+	for (int level = PG_LEVEL_512G; level >= PG_LEVEL_4K; level--) {
+		index = (nested_paddr >> PG_LEVEL_SHIFT(level)) & 0x1ffu;
+		pte = &pt[index];
 
-	/* Allocate page directory table if not present. */
-	struct eptPageTableEntry *pdpe;
-	pdpe = addr_gpa2hva(vm, pml4e[index[3]].address * vm->page_size);
-	if (!pdpe[index[2]].readable) {
-		pdpe[index[2]].address = vm_alloc_page_table(vm) >> vm->page_shift;
-		pdpe[index[2]].writable = true;
-		pdpe[index[2]].readable = true;
-		pdpe[index[2]].executable = true;
-	}
+		nested_create_pte(vm, pte, nested_paddr, paddr, level, target_level);
 
-	/* Allocate page table if not present. */
-	struct eptPageTableEntry *pde;
-	pde = addr_gpa2hva(vm, pdpe[index[2]].address * vm->page_size);
-	if (!pde[index[1]].readable) {
-		pde[index[1]].address = vm_alloc_page_table(vm) >> vm->page_shift;
-		pde[index[1]].writable = true;
-		pde[index[1]].readable = true;
-		pde[index[1]].executable = true;
-	}
+		if (pte->page_size)
+			break;
 
-	/* Fill in page table entry. */
-	struct eptPageTableEntry *pte;
-	pte = addr_gpa2hva(vm, pde[index[1]].address * vm->page_size);
-	pte[index[0]].address = paddr >> vm->page_shift;
-	pte[index[0]].writable = true;
-	pte[index[0]].readable = true;
-	pte[index[0]].executable = true;
+		pt = addr_gpa2hva(vm, pte->address * vm->page_size);
+	}
 
 	/*
 	 * For now mark these as accessed and dirty because the only
 	 * testcase we have needs that.  Can be reconsidered later.
 	 */
-	pte[index[0]].accessed = true;
-	pte[index[0]].dirty = true;
+	pte->accessed = true;
+	pte->dirty = true;
+
+}
+
+void nested_pg_map(struct vmx_pages *vmx, struct kvm_vm *vm,
+		   uint64_t nested_paddr, uint64_t paddr)
+{
+	__nested_pg_map(vmx, vm, nested_paddr, paddr, PG_LEVEL_4K);
 }
 
 /*
-- 
GitLab


From b8ca01ea19068b54938ebb4ebc06814a89dee8ea Mon Sep 17 00:00:00 2001
From: David Matlack <dmatlack@google.com>
Date: Fri, 20 May 2022 23:32:41 +0000
Subject: [PATCH 0390/1731] KVM: selftests: Drop stale function parameter
 comment for nested_map()

nested_map() does not take a parameter named eptp_memslot. Drop the
comment referring to it.

Reviewed-by: Peter Xu <peterx@redhat.com>
Signed-off-by: David Matlack <dmatlack@google.com>
Message-Id: <20220520233249.3776001-4-dmatlack@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/lib/x86_64/vmx.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/tools/testing/selftests/kvm/lib/x86_64/vmx.c b/tools/testing/selftests/kvm/lib/x86_64/vmx.c
index fdc1e6deb9229..baeaa35de1139 100644
--- a/tools/testing/selftests/kvm/lib/x86_64/vmx.c
+++ b/tools/testing/selftests/kvm/lib/x86_64/vmx.c
@@ -486,7 +486,6 @@ void nested_pg_map(struct vmx_pages *vmx, struct kvm_vm *vm,
  *   nested_paddr - Nested guest physical address to map
  *   paddr - VM Physical Address
  *   size - The size of the range to map
- *   eptp_memslot - Memory region slot for new virtual translation tables
  *
  * Output Args: None
  *
-- 
GitLab


From ce690e9c17d27486af879defc506679cbbb14777 Mon Sep 17 00:00:00 2001
From: David Matlack <dmatlack@google.com>
Date: Fri, 20 May 2022 23:32:42 +0000
Subject: [PATCH 0391/1731] KVM: selftests: Refactor nested_map() to specify
 target level

Refactor nested_map() to specify that it explicityl wants 4K mappings
(the existing behavior) and push the implementation down into
__nested_map(), which can be used in subsequent commits to create huge
page mappings.

No function change intended.

Reviewed-by: Peter Xu <peterx@redhat.com>
Signed-off-by: David Matlack <dmatlack@google.com>
Message-Id: <20220520233249.3776001-5-dmatlack@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/lib/x86_64/vmx.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/tools/testing/selftests/kvm/lib/x86_64/vmx.c b/tools/testing/selftests/kvm/lib/x86_64/vmx.c
index baeaa35de1139..b8cfe4914a3aa 100644
--- a/tools/testing/selftests/kvm/lib/x86_64/vmx.c
+++ b/tools/testing/selftests/kvm/lib/x86_64/vmx.c
@@ -486,6 +486,7 @@ void nested_pg_map(struct vmx_pages *vmx, struct kvm_vm *vm,
  *   nested_paddr - Nested guest physical address to map
  *   paddr - VM Physical Address
  *   size - The size of the range to map
+ *   level - The level at which to map the range
  *
  * Output Args: None
  *
@@ -494,22 +495,29 @@ void nested_pg_map(struct vmx_pages *vmx, struct kvm_vm *vm,
  * Within the VM given by vm, creates a nested guest translation for the
  * page range starting at nested_paddr to the page range starting at paddr.
  */
-void nested_map(struct vmx_pages *vmx, struct kvm_vm *vm,
-		uint64_t nested_paddr, uint64_t paddr, uint64_t size)
+void __nested_map(struct vmx_pages *vmx, struct kvm_vm *vm,
+		  uint64_t nested_paddr, uint64_t paddr, uint64_t size,
+		  int level)
 {
-	size_t page_size = vm->page_size;
+	size_t page_size = PG_LEVEL_SIZE(level);
 	size_t npages = size / page_size;
 
 	TEST_ASSERT(nested_paddr + size > nested_paddr, "Vaddr overflow");
 	TEST_ASSERT(paddr + size > paddr, "Paddr overflow");
 
 	while (npages--) {
-		nested_pg_map(vmx, vm, nested_paddr, paddr);
+		__nested_pg_map(vmx, vm, nested_paddr, paddr, level);
 		nested_paddr += page_size;
 		paddr += page_size;
 	}
 }
 
+void nested_map(struct vmx_pages *vmx, struct kvm_vm *vm,
+		uint64_t nested_paddr, uint64_t paddr, uint64_t size)
+{
+	__nested_map(vmx, vm, nested_paddr, paddr, size, PG_LEVEL_4K);
+}
+
 /* Prepare an identity extended page table that maps all the
  * physical pages in VM.
  */
-- 
GitLab


From b6c086d04c0a1ba356145cdba5b46bd6cea2b9bd Mon Sep 17 00:00:00 2001
From: David Matlack <dmatlack@google.com>
Date: Fri, 20 May 2022 23:32:43 +0000
Subject: [PATCH 0392/1731] KVM: selftests: Move VMX_EPT_VPID_CAP_AD_BITS to
 vmx.h

This is a VMX-related macro so move it to vmx.h. While here, open code
the mask like the rest of the VMX bitmask macros.

No functional change intended.

Reviewed-by: Peter Xu <peterx@redhat.com>
Signed-off-by: David Matlack <dmatlack@google.com>
Message-Id: <20220520233249.3776001-6-dmatlack@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/include/x86_64/processor.h | 3 ---
 tools/testing/selftests/kvm/include/x86_64/vmx.h       | 2 ++
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools/testing/selftests/kvm/include/x86_64/processor.h
index 273c70e91647d..d78f97f502b5c 100644
--- a/tools/testing/selftests/kvm/include/x86_64/processor.h
+++ b/tools/testing/selftests/kvm/include/x86_64/processor.h
@@ -511,9 +511,6 @@ void __virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, int level)
 #define X86_CR0_CD          (1UL<<30) /* Cache Disable */
 #define X86_CR0_PG          (1UL<<31) /* Paging */
 
-/* VMX_EPT_VPID_CAP bits */
-#define VMX_EPT_VPID_CAP_AD_BITS       (1ULL << 21)
-
 #define XSTATE_XTILE_CFG_BIT		17
 #define XSTATE_XTILE_DATA_BIT		18
 
diff --git a/tools/testing/selftests/kvm/include/x86_64/vmx.h b/tools/testing/selftests/kvm/include/x86_64/vmx.h
index 583ceb0d14574..3b1794baa97cb 100644
--- a/tools/testing/selftests/kvm/include/x86_64/vmx.h
+++ b/tools/testing/selftests/kvm/include/x86_64/vmx.h
@@ -96,6 +96,8 @@
 #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK	0x0000001f
 #define VMX_MISC_SAVE_EFER_LMA			0x00000020
 
+#define VMX_EPT_VPID_CAP_AD_BITS		0x00200000
+
 #define EXIT_REASON_FAILED_VMENTRY	0x80000000
 #define EXIT_REASON_EXCEPTION_NMI	0
 #define EXIT_REASON_EXTERNAL_INTERRUPT	1
-- 
GitLab


From c363d95986b1b930947305e2372665141721d15f Mon Sep 17 00:00:00 2001
From: David Matlack <dmatlack@google.com>
Date: Fri, 20 May 2022 23:32:44 +0000
Subject: [PATCH 0393/1731] KVM: selftests: Add a helper to check EPT/VPID
 capabilities

Create a small helper function to check if a given EPT/VPID capability
is supported. This will be re-used in a follow-up commit to check for 1G
page support.

No functional change intended.

Reviewed-by: Peter Xu <peterx@redhat.com>
Signed-off-by: David Matlack <dmatlack@google.com>
Message-Id: <20220520233249.3776001-7-dmatlack@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/lib/x86_64/vmx.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/tools/testing/selftests/kvm/lib/x86_64/vmx.c b/tools/testing/selftests/kvm/lib/x86_64/vmx.c
index b8cfe4914a3aa..5bf1691794557 100644
--- a/tools/testing/selftests/kvm/lib/x86_64/vmx.c
+++ b/tools/testing/selftests/kvm/lib/x86_64/vmx.c
@@ -198,6 +198,11 @@ bool load_vmcs(struct vmx_pages *vmx)
 	return true;
 }
 
+static bool ept_vpid_cap_supported(uint64_t mask)
+{
+	return rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & mask;
+}
+
 /*
  * Initialize the control fields to the most basic settings possible.
  */
@@ -215,7 +220,7 @@ static inline void init_vmcs_control_fields(struct vmx_pages *vmx)
 		struct eptPageTablePointer eptp = {
 			.memory_type = VMX_BASIC_MEM_TYPE_WB,
 			.page_walk_length = 3, /* + 1 */
-			.ad_enabled = !!(rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & VMX_EPT_VPID_CAP_AD_BITS),
+			.ad_enabled = ept_vpid_cap_supported(VMX_EPT_VPID_CAP_AD_BITS),
 			.address = vmx->eptp_gpa >> PAGE_SHIFT_4K,
 		};
 
-- 
GitLab


From acf57736e755ba5c467fc6fa85e4a0750cc36150 Mon Sep 17 00:00:00 2001
From: David Matlack <dmatlack@google.com>
Date: Fri, 20 May 2022 23:32:45 +0000
Subject: [PATCH 0394/1731] KVM: selftests: Drop unnecessary rule for
 STATIC_LIBS

Drop the "all: $(STATIC_LIBS)" rule. The KVM selftests already depend
on $(STATIC_LIBS), so there is no reason to have an extra "all" rule.

Suggested-by: Peter Xu <peterx@redhat.com>
Signed-off-by: David Matlack <dmatlack@google.com>
Message-Id: <20220520233249.3776001-8-dmatlack@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/Makefile | 1 -
 1 file changed, 1 deletion(-)

diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
index 81470a99ed1c0..e7d65e04b16a9 100644
--- a/tools/testing/selftests/kvm/Makefile
+++ b/tools/testing/selftests/kvm/Makefile
@@ -192,7 +192,6 @@ $(OUTPUT)/libkvm.a: $(LIBKVM_OBJS)
 	$(AR) crs $@ $^
 
 x := $(shell mkdir -p $(sort $(dir $(TEST_GEN_PROGS))))
-all: $(STATIC_LIBS)
 $(TEST_GEN_PROGS): $(STATIC_LIBS)
 
 cscope: include_paths = $(LINUX_TOOL_INCLUDE) $(LINUX_HDR_PATH) include lib ..
-- 
GitLab


From cdc979dae265cc77a035b736f78f58e4c7309bb2 Mon Sep 17 00:00:00 2001
From: David Matlack <dmatlack@google.com>
Date: Fri, 20 May 2022 23:32:46 +0000
Subject: [PATCH 0395/1731] KVM: selftests: Link selftests directly with lib
 object files

The linker does obey strong/weak symbols when linking static libraries,
it simply resolves an undefined symbol to the first-encountered symbol.
This means that defining __weak arch-generic functions and then defining
arch-specific strong functions to override them in libkvm will not
always work.

More specifically, if we have:

lib/generic.c:

  void __weak foo(void)
  {
          pr_info("weak\n");
  }

  void bar(void)
  {
          foo();
  }

lib/x86_64/arch.c:

  void foo(void)
  {
          pr_info("strong\n");
  }

And a selftest that calls bar(), it will print "weak". Now if you make
generic.o explicitly depend on arch.o (e.g. add function to arch.c that
is called directly from generic.c) it will print "strong". In other
words, it seems that the linker is free to throw out arch.o when linking
because generic.o does not explicitly depend on it, which causes the
linker to lose the strong symbol.

One solution is to link libkvm.a with --whole-archive so that the linker
doesn't throw away object files it thinks are unnecessary. However that
is a bit difficult to plumb since we are using the common selftests
makefile rules. An easier solution is to drop libkvm.a just link
selftests with all the .o files that were originally in libkvm.a.

Reviewed-by: Peter Xu <peterx@redhat.com>
Signed-off-by: David Matlack <dmatlack@google.com>
Message-Id: <20220520233249.3776001-9-dmatlack@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/Makefile | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
index e7d65e04b16a9..804bf927618a1 100644
--- a/tools/testing/selftests/kvm/Makefile
+++ b/tools/testing/selftests/kvm/Makefile
@@ -173,12 +173,13 @@ LDFLAGS += -pthread $(no-pie-option) $(pgste-option)
 # $(TEST_GEN_PROGS) starts with $(OUTPUT)/
 include ../lib.mk
 
-STATIC_LIBS := $(OUTPUT)/libkvm.a
 LIBKVM_C := $(filter %.c,$(LIBKVM))
 LIBKVM_S := $(filter %.S,$(LIBKVM))
 LIBKVM_C_OBJ := $(patsubst %.c, $(OUTPUT)/%.o, $(LIBKVM_C))
 LIBKVM_S_OBJ := $(patsubst %.S, $(OUTPUT)/%.o, $(LIBKVM_S))
-EXTRA_CLEAN += $(LIBKVM_C_OBJ) $(LIBKVM_S_OBJ) $(STATIC_LIBS) cscope.*
+LIBKVM_OBJS = $(LIBKVM_C_OBJ) $(LIBKVM_S_OBJ)
+
+EXTRA_CLEAN += $(LIBKVM_OBJS) cscope.*
 
 x := $(shell mkdir -p $(sort $(dir $(LIBKVM_C_OBJ) $(LIBKVM_S_OBJ))))
 $(LIBKVM_C_OBJ): $(OUTPUT)/%.o: %.c
@@ -187,12 +188,8 @@ $(LIBKVM_C_OBJ): $(OUTPUT)/%.o: %.c
 $(LIBKVM_S_OBJ): $(OUTPUT)/%.o: %.S
 	$(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
 
-LIBKVM_OBJS = $(LIBKVM_C_OBJ) $(LIBKVM_S_OBJ)
-$(OUTPUT)/libkvm.a: $(LIBKVM_OBJS)
-	$(AR) crs $@ $^
-
 x := $(shell mkdir -p $(sort $(dir $(TEST_GEN_PROGS))))
-$(TEST_GEN_PROGS): $(STATIC_LIBS)
+$(TEST_GEN_PROGS): $(LIBKVM_OBJS)
 
 cscope: include_paths = $(LINUX_TOOL_INCLUDE) $(LINUX_HDR_PATH) include lib ..
 cscope:
-- 
GitLab


From cf97d5e99f69f876dc310ea21b5f97c3a493a18a Mon Sep 17 00:00:00 2001
From: David Matlack <dmatlack@google.com>
Date: Fri, 20 May 2022 23:32:47 +0000
Subject: [PATCH 0396/1731] KVM: selftests: Clean up LIBKVM files in Makefile

Break up the long lines for LIBKVM and alphabetize each architecture.
This makes reading the Makefile easier, and will make reading diffs to
LIBKVM easier.

No functional change intended.

Reviewed-by: Peter Xu <peterx@redhat.com>
Signed-off-by: David Matlack <dmatlack@google.com>
Message-Id: <20220520233249.3776001-10-dmatlack@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/Makefile | 36 ++++++++++++++++++++++++----
 1 file changed, 31 insertions(+), 5 deletions(-)

diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
index 804bf927618a1..14566c0a330d4 100644
--- a/tools/testing/selftests/kvm/Makefile
+++ b/tools/testing/selftests/kvm/Makefile
@@ -37,11 +37,37 @@ ifeq ($(ARCH),riscv)
 	UNAME_M := riscv
 endif
 
-LIBKVM = lib/assert.c lib/elf.c lib/io.c lib/kvm_util.c lib/rbtree.c lib/sparsebit.c lib/test_util.c lib/guest_modes.c lib/perf_test_util.c
-LIBKVM_x86_64 = lib/x86_64/apic.c lib/x86_64/processor.c lib/x86_64/vmx.c lib/x86_64/svm.c lib/x86_64/ucall.c lib/x86_64/handlers.S
-LIBKVM_aarch64 = lib/aarch64/processor.c lib/aarch64/ucall.c lib/aarch64/handlers.S lib/aarch64/spinlock.c lib/aarch64/gic.c lib/aarch64/gic_v3.c lib/aarch64/vgic.c
-LIBKVM_s390x = lib/s390x/processor.c lib/s390x/ucall.c lib/s390x/diag318_test_handler.c
-LIBKVM_riscv = lib/riscv/processor.c lib/riscv/ucall.c
+LIBKVM += lib/assert.c
+LIBKVM += lib/elf.c
+LIBKVM += lib/guest_modes.c
+LIBKVM += lib/io.c
+LIBKVM += lib/kvm_util.c
+LIBKVM += lib/perf_test_util.c
+LIBKVM += lib/rbtree.c
+LIBKVM += lib/sparsebit.c
+LIBKVM += lib/test_util.c
+
+LIBKVM_x86_64 += lib/x86_64/apic.c
+LIBKVM_x86_64 += lib/x86_64/handlers.S
+LIBKVM_x86_64 += lib/x86_64/processor.c
+LIBKVM_x86_64 += lib/x86_64/svm.c
+LIBKVM_x86_64 += lib/x86_64/ucall.c
+LIBKVM_x86_64 += lib/x86_64/vmx.c
+
+LIBKVM_aarch64 += lib/aarch64/gic.c
+LIBKVM_aarch64 += lib/aarch64/gic_v3.c
+LIBKVM_aarch64 += lib/aarch64/handlers.S
+LIBKVM_aarch64 += lib/aarch64/processor.c
+LIBKVM_aarch64 += lib/aarch64/spinlock.c
+LIBKVM_aarch64 += lib/aarch64/ucall.c
+LIBKVM_aarch64 += lib/aarch64/vgic.c
+
+LIBKVM_s390x += lib/s390x/diag318_test_handler.c
+LIBKVM_s390x += lib/s390x/processor.c
+LIBKVM_s390x += lib/s390x/ucall.c
+
+LIBKVM_riscv += lib/riscv/processor.c
+LIBKVM_riscv += lib/riscv/ucall.c
 
 TEST_GEN_PROGS_x86_64 = x86_64/cpuid_test
 TEST_GEN_PROGS_x86_64 += x86_64/cr4_cpuid_sync_test
-- 
GitLab


From 71d489661904fcc3ec31b343acd5c0dac84b5410 Mon Sep 17 00:00:00 2001
From: David Matlack <dmatlack@google.com>
Date: Fri, 20 May 2022 23:32:48 +0000
Subject: [PATCH 0397/1731] KVM: selftests: Add option to run
 dirty_log_perf_test vCPUs in L2

Add an option to dirty_log_perf_test that configures the vCPUs to run in
L2 instead of L1. This makes it possible to benchmark the dirty logging
performance of nested virtualization, which is particularly interesting
because KVM must shadow L1's EPT/NPT tables.

For now this support only works on x86_64 CPUs with VMX. Otherwise
passing -n results in the test being skipped.

Signed-off-by: David Matlack <dmatlack@google.com>
Message-Id: <20220520233249.3776001-11-dmatlack@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/Makefile          |   1 +
 .../selftests/kvm/dirty_log_perf_test.c       |  10 +-
 .../selftests/kvm/include/perf_test_util.h    |   9 ++
 .../selftests/kvm/include/x86_64/processor.h  |   4 +
 .../selftests/kvm/include/x86_64/vmx.h        |   4 +
 .../selftests/kvm/lib/perf_test_util.c        |  35 +++++-
 .../selftests/kvm/lib/x86_64/perf_test_util.c | 112 ++++++++++++++++++
 tools/testing/selftests/kvm/lib/x86_64/vmx.c  |  15 +++
 8 files changed, 182 insertions(+), 8 deletions(-)
 create mode 100644 tools/testing/selftests/kvm/lib/x86_64/perf_test_util.c

diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
index 14566c0a330d4..22423c871ed61 100644
--- a/tools/testing/selftests/kvm/Makefile
+++ b/tools/testing/selftests/kvm/Makefile
@@ -49,6 +49,7 @@ LIBKVM += lib/test_util.c
 
 LIBKVM_x86_64 += lib/x86_64/apic.c
 LIBKVM_x86_64 += lib/x86_64/handlers.S
+LIBKVM_x86_64 += lib/x86_64/perf_test_util.c
 LIBKVM_x86_64 += lib/x86_64/processor.c
 LIBKVM_x86_64 += lib/x86_64/svm.c
 LIBKVM_x86_64 += lib/x86_64/ucall.c
diff --git a/tools/testing/selftests/kvm/dirty_log_perf_test.c b/tools/testing/selftests/kvm/dirty_log_perf_test.c
index 7b47ae4f952e6..d60a34cdfaee1 100644
--- a/tools/testing/selftests/kvm/dirty_log_perf_test.c
+++ b/tools/testing/selftests/kvm/dirty_log_perf_test.c
@@ -336,8 +336,8 @@ static void run_test(enum vm_guest_mode mode, void *arg)
 static void help(char *name)
 {
 	puts("");
-	printf("usage: %s [-h] [-i iterations] [-p offset] [-g]"
-	       "[-m mode] [-b vcpu bytes] [-v vcpus] [-o] [-s mem type]"
+	printf("usage: %s [-h] [-i iterations] [-p offset] [-g] "
+	       "[-m mode] [-n] [-b vcpu bytes] [-v vcpus] [-o] [-s mem type]"
 	       "[-x memslots]\n", name);
 	puts("");
 	printf(" -i: specify iteration counts (default: %"PRIu64")\n",
@@ -351,6 +351,7 @@ static void help(char *name)
 	printf(" -p: specify guest physical test memory offset\n"
 	       "     Warning: a low offset can conflict with the loaded test code.\n");
 	guest_modes_help();
+	printf(" -n: Run the vCPUs in nested mode (L2)\n");
 	printf(" -b: specify the size of the memory region which should be\n"
 	       "     dirtied by each vCPU. e.g. 10M or 3G.\n"
 	       "     (default: 1G)\n");
@@ -387,7 +388,7 @@ int main(int argc, char *argv[])
 
 	guest_modes_append_default();
 
-	while ((opt = getopt(argc, argv, "ghi:p:m:b:f:v:os:x:")) != -1) {
+	while ((opt = getopt(argc, argv, "ghi:p:m:nb:f:v:os:x:")) != -1) {
 		switch (opt) {
 		case 'g':
 			dirty_log_manual_caps = 0;
@@ -401,6 +402,9 @@ int main(int argc, char *argv[])
 		case 'm':
 			guest_modes_cmdline(optarg);
 			break;
+		case 'n':
+			perf_test_args.nested = true;
+			break;
 		case 'b':
 			guest_percpu_mem_size = parse_size(optarg);
 			break;
diff --git a/tools/testing/selftests/kvm/include/perf_test_util.h b/tools/testing/selftests/kvm/include/perf_test_util.h
index a86f953d8d365..d822cb670f1cd 100644
--- a/tools/testing/selftests/kvm/include/perf_test_util.h
+++ b/tools/testing/selftests/kvm/include/perf_test_util.h
@@ -30,10 +30,15 @@ struct perf_test_vcpu_args {
 
 struct perf_test_args {
 	struct kvm_vm *vm;
+	/* The starting address and size of the guest test region. */
 	uint64_t gpa;
+	uint64_t size;
 	uint64_t guest_page_size;
 	int wr_fract;
 
+	/* Run vCPUs in L2 instead of L1, if the architecture supports it. */
+	bool nested;
+
 	struct perf_test_vcpu_args vcpu_args[KVM_MAX_VCPUS];
 };
 
@@ -49,5 +54,9 @@ void perf_test_set_wr_fract(struct kvm_vm *vm, int wr_fract);
 
 void perf_test_start_vcpu_threads(int vcpus, void (*vcpu_fn)(struct perf_test_vcpu_args *));
 void perf_test_join_vcpu_threads(int vcpus);
+void perf_test_guest_code(uint32_t vcpu_id);
+
+uint64_t perf_test_nested_pages(int nr_vcpus);
+void perf_test_setup_nested(struct kvm_vm *vm, int nr_vcpus);
 
 #endif /* SELFTEST_KVM_PERF_TEST_UTIL_H */
diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools/testing/selftests/kvm/include/x86_64/processor.h
index d78f97f502b5c..6ce185449259f 100644
--- a/tools/testing/selftests/kvm/include/x86_64/processor.h
+++ b/tools/testing/selftests/kvm/include/x86_64/processor.h
@@ -494,6 +494,10 @@ enum pg_level {
 #define PG_LEVEL_SHIFT(_level) ((_level - 1) * 9 + 12)
 #define PG_LEVEL_SIZE(_level) (1ull << PG_LEVEL_SHIFT(_level))
 
+#define PG_SIZE_4K PG_LEVEL_SIZE(PG_LEVEL_4K)
+#define PG_SIZE_2M PG_LEVEL_SIZE(PG_LEVEL_2M)
+#define PG_SIZE_1G PG_LEVEL_SIZE(PG_LEVEL_1G)
+
 void __virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, int level);
 
 /*
diff --git a/tools/testing/selftests/kvm/include/x86_64/vmx.h b/tools/testing/selftests/kvm/include/x86_64/vmx.h
index 3b1794baa97cb..cc3604f8f1d3c 100644
--- a/tools/testing/selftests/kvm/include/x86_64/vmx.h
+++ b/tools/testing/selftests/kvm/include/x86_64/vmx.h
@@ -96,6 +96,7 @@
 #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK	0x0000001f
 #define VMX_MISC_SAVE_EFER_LMA			0x00000020
 
+#define VMX_EPT_VPID_CAP_1G_PAGES		0x00020000
 #define VMX_EPT_VPID_CAP_AD_BITS		0x00200000
 
 #define EXIT_REASON_FAILED_VMENTRY	0x80000000
@@ -608,6 +609,7 @@ bool load_vmcs(struct vmx_pages *vmx);
 
 bool nested_vmx_supported(void);
 void nested_vmx_check_supported(void);
+bool ept_1g_pages_supported(void);
 
 void nested_pg_map(struct vmx_pages *vmx, struct kvm_vm *vm,
 		   uint64_t nested_paddr, uint64_t paddr);
@@ -615,6 +617,8 @@ void nested_map(struct vmx_pages *vmx, struct kvm_vm *vm,
 		 uint64_t nested_paddr, uint64_t paddr, uint64_t size);
 void nested_map_memslot(struct vmx_pages *vmx, struct kvm_vm *vm,
 			uint32_t memslot);
+void nested_identity_map_1g(struct vmx_pages *vmx, struct kvm_vm *vm,
+			    uint64_t addr, uint64_t size);
 void prepare_eptp(struct vmx_pages *vmx, struct kvm_vm *vm,
 		  uint32_t eptp_memslot);
 void prepare_virtualize_apic_accesses(struct vmx_pages *vmx, struct kvm_vm *vm);
diff --git a/tools/testing/selftests/kvm/lib/perf_test_util.c b/tools/testing/selftests/kvm/lib/perf_test_util.c
index 722df3a28791c..b2ff2cee2e51c 100644
--- a/tools/testing/selftests/kvm/lib/perf_test_util.c
+++ b/tools/testing/selftests/kvm/lib/perf_test_util.c
@@ -40,7 +40,7 @@ static bool all_vcpu_threads_running;
  * Continuously write to the first 8 bytes of each page in the
  * specified region.
  */
-static void guest_code(uint32_t vcpu_id)
+void perf_test_guest_code(uint32_t vcpu_id)
 {
 	struct perf_test_args *pta = &perf_test_args;
 	struct perf_test_vcpu_args *vcpu_args = &pta->vcpu_args[vcpu_id];
@@ -108,7 +108,7 @@ struct kvm_vm *perf_test_create_vm(enum vm_guest_mode mode, int vcpus,
 {
 	struct perf_test_args *pta = &perf_test_args;
 	struct kvm_vm *vm;
-	uint64_t guest_num_pages;
+	uint64_t guest_num_pages, slot0_pages = DEFAULT_GUEST_PHY_PAGES;
 	uint64_t backing_src_pagesz = get_backing_src_pagesz(backing_src);
 	int i;
 
@@ -134,13 +134,20 @@ struct kvm_vm *perf_test_create_vm(enum vm_guest_mode mode, int vcpus,
 		    "Guest memory cannot be evenly divided into %d slots.",
 		    slots);
 
+	/*
+	 * If using nested, allocate extra pages for the nested page tables and
+	 * in-memory data structures.
+	 */
+	if (pta->nested)
+		slot0_pages += perf_test_nested_pages(vcpus);
+
 	/*
 	 * Pass guest_num_pages to populate the page tables for test memory.
 	 * The memory is also added to memslot 0, but that's a benign side
 	 * effect as KVM allows aliasing HVAs in meslots.
 	 */
-	vm = vm_create_with_vcpus(mode, vcpus, DEFAULT_GUEST_PHY_PAGES,
-				  guest_num_pages, 0, guest_code, NULL);
+	vm = vm_create_with_vcpus(mode, vcpus, slot0_pages, guest_num_pages, 0,
+				  perf_test_guest_code, NULL);
 
 	pta->vm = vm;
 
@@ -161,7 +168,9 @@ struct kvm_vm *perf_test_create_vm(enum vm_guest_mode mode, int vcpus,
 	/* Align to 1M (segment size) */
 	pta->gpa = align_down(pta->gpa, 1 << 20);
 #endif
-	pr_info("guest physical test memory offset: 0x%lx\n", pta->gpa);
+	pta->size = guest_num_pages * pta->guest_page_size;
+	pr_info("guest physical test memory: [0x%lx, 0x%lx)\n",
+		pta->gpa, pta->gpa + pta->size);
 
 	/* Add extra memory slots for testing */
 	for (i = 0; i < slots; i++) {
@@ -178,6 +187,11 @@ struct kvm_vm *perf_test_create_vm(enum vm_guest_mode mode, int vcpus,
 
 	perf_test_setup_vcpus(vm, vcpus, vcpu_memory_bytes, partition_vcpu_memory_access);
 
+	if (pta->nested) {
+		pr_info("Configuring vCPUs to run in L2 (nested).\n");
+		perf_test_setup_nested(vm, vcpus);
+	}
+
 	ucall_init(vm, NULL);
 
 	/* Export the shared variables to the guest. */
@@ -198,6 +212,17 @@ void perf_test_set_wr_fract(struct kvm_vm *vm, int wr_fract)
 	sync_global_to_guest(vm, perf_test_args);
 }
 
+uint64_t __weak perf_test_nested_pages(int nr_vcpus)
+{
+	return 0;
+}
+
+void __weak perf_test_setup_nested(struct kvm_vm *vm, int nr_vcpus)
+{
+	pr_info("%s() not support on this architecture, skipping.\n", __func__);
+	exit(KSFT_SKIP);
+}
+
 static void *vcpu_thread_main(void *data)
 {
 	struct vcpu_thread *vcpu = data;
diff --git a/tools/testing/selftests/kvm/lib/x86_64/perf_test_util.c b/tools/testing/selftests/kvm/lib/x86_64/perf_test_util.c
new file mode 100644
index 0000000000000..e258524435a06
--- /dev/null
+++ b/tools/testing/selftests/kvm/lib/x86_64/perf_test_util.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * x86_64-specific extensions to perf_test_util.c.
+ *
+ * Copyright (C) 2022, Google, Inc.
+ */
+#include <stdio.h>
+#include <stdlib.h>
+#include <linux/bitmap.h>
+#include <linux/bitops.h>
+
+#include "test_util.h"
+#include "kvm_util.h"
+#include "perf_test_util.h"
+#include "../kvm_util_internal.h"
+#include "processor.h"
+#include "vmx.h"
+
+void perf_test_l2_guest_code(uint64_t vcpu_id)
+{
+	perf_test_guest_code(vcpu_id);
+	vmcall();
+}
+
+extern char perf_test_l2_guest_entry[];
+__asm__(
+"perf_test_l2_guest_entry:"
+"	mov (%rsp), %rdi;"
+"	call perf_test_l2_guest_code;"
+"	ud2;"
+);
+
+static void perf_test_l1_guest_code(struct vmx_pages *vmx, uint64_t vcpu_id)
+{
+#define L2_GUEST_STACK_SIZE 64
+	unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE];
+	unsigned long *rsp;
+
+	GUEST_ASSERT(vmx->vmcs_gpa);
+	GUEST_ASSERT(prepare_for_vmx_operation(vmx));
+	GUEST_ASSERT(load_vmcs(vmx));
+	GUEST_ASSERT(ept_1g_pages_supported());
+
+	rsp = &l2_guest_stack[L2_GUEST_STACK_SIZE - 1];
+	*rsp = vcpu_id;
+	prepare_vmcs(vmx, perf_test_l2_guest_entry, rsp);
+
+	GUEST_ASSERT(!vmlaunch());
+	GUEST_ASSERT(vmreadz(VM_EXIT_REASON) == EXIT_REASON_VMCALL);
+	GUEST_DONE();
+}
+
+uint64_t perf_test_nested_pages(int nr_vcpus)
+{
+	/*
+	 * 513 page tables is enough to identity-map 256 TiB of L2 with 1G
+	 * pages and 4-level paging, plus a few pages per-vCPU for data
+	 * structures such as the VMCS.
+	 */
+	return 513 + 10 * nr_vcpus;
+}
+
+void perf_test_setup_ept(struct vmx_pages *vmx, struct kvm_vm *vm)
+{
+	uint64_t start, end;
+
+	prepare_eptp(vmx, vm, 0);
+
+	/*
+	 * Identity map the first 4G and the test region with 1G pages so that
+	 * KVM can shadow the EPT12 with the maximum huge page size supported
+	 * by the backing source.
+	 */
+	nested_identity_map_1g(vmx, vm, 0, 0x100000000ULL);
+
+	start = align_down(perf_test_args.gpa, PG_SIZE_1G);
+	end = align_up(perf_test_args.gpa + perf_test_args.size, PG_SIZE_1G);
+	nested_identity_map_1g(vmx, vm, start, end - start);
+}
+
+void perf_test_setup_nested(struct kvm_vm *vm, int nr_vcpus)
+{
+	struct vmx_pages *vmx, *vmx0 = NULL;
+	struct kvm_regs regs;
+	vm_vaddr_t vmx_gva;
+	int vcpu_id;
+
+	nested_vmx_check_supported();
+
+	for (vcpu_id = 0; vcpu_id < nr_vcpus; vcpu_id++) {
+		vmx = vcpu_alloc_vmx(vm, &vmx_gva);
+
+		if (vcpu_id == 0) {
+			perf_test_setup_ept(vmx, vm);
+			vmx0 = vmx;
+		} else {
+			/* Share the same EPT table across all vCPUs. */
+			vmx->eptp = vmx0->eptp;
+			vmx->eptp_hva = vmx0->eptp_hva;
+			vmx->eptp_gpa = vmx0->eptp_gpa;
+		}
+
+		/*
+		 * Override the vCPU to run perf_test_l1_guest_code() which will
+		 * bounce it into L2 before calling perf_test_guest_code().
+		 */
+		vcpu_regs_get(vm, vcpu_id, &regs);
+		regs.rip = (unsigned long) perf_test_l1_guest_code;
+		vcpu_regs_set(vm, vcpu_id, &regs);
+		vcpu_args_set(vm, vcpu_id, 2, vmx_gva, vcpu_id);
+	}
+}
diff --git a/tools/testing/selftests/kvm/lib/x86_64/vmx.c b/tools/testing/selftests/kvm/lib/x86_64/vmx.c
index 5bf1691794557..b77a01d0a2713 100644
--- a/tools/testing/selftests/kvm/lib/x86_64/vmx.c
+++ b/tools/testing/selftests/kvm/lib/x86_64/vmx.c
@@ -203,6 +203,11 @@ static bool ept_vpid_cap_supported(uint64_t mask)
 	return rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & mask;
 }
 
+bool ept_1g_pages_supported(void)
+{
+	return ept_vpid_cap_supported(VMX_EPT_VPID_CAP_1G_PAGES);
+}
+
 /*
  * Initialize the control fields to the most basic settings possible.
  */
@@ -439,6 +444,9 @@ void __nested_pg_map(struct vmx_pages *vmx, struct kvm_vm *vm,
 	TEST_ASSERT(vm->mode == VM_MODE_PXXV48_4K, "Attempt to use "
 		    "unknown or unsupported guest mode, mode: 0x%x", vm->mode);
 
+	TEST_ASSERT((nested_paddr >> 48) == 0,
+		    "Nested physical address 0x%lx requires 5-level paging",
+		    nested_paddr);
 	TEST_ASSERT((nested_paddr % page_size) == 0,
 		    "Nested physical address not on page boundary,\n"
 		    "  nested_paddr: 0x%lx page_size: 0x%lx",
@@ -547,6 +555,13 @@ void nested_map_memslot(struct vmx_pages *vmx, struct kvm_vm *vm,
 	}
 }
 
+/* Identity map a region with 1GiB Pages. */
+void nested_identity_map_1g(struct vmx_pages *vmx, struct kvm_vm *vm,
+			    uint64_t addr, uint64_t size)
+{
+	__nested_map(vmx, vm, addr, addr, size, PG_LEVEL_1G);
+}
+
 void prepare_eptp(struct vmx_pages *vmx, struct kvm_vm *vm,
 		  uint32_t eptp_memslot)
 {
-- 
GitLab


From e0f3f46e42064a51573914766897b4ab95d943e3 Mon Sep 17 00:00:00 2001
From: David Matlack <dmatlack@google.com>
Date: Fri, 20 May 2022 23:32:49 +0000
Subject: [PATCH 0398/1731] KVM: selftests: Restrict test region to 48-bit
 physical addresses when using nested

The selftests nested code only supports 4-level paging at the moment.
This means it cannot map nested guest physical addresses with more than
48 bits. Allow perf_test_util nested mode to work on hosts with more
than 48 physical addresses by restricting the guest test region to
48-bits.

While here, opportunistically fix an off-by-one error when dealing with
vm_get_max_gfn(). perf_test_util.c was treating this as the maximum
number of GFNs, rather than the maximum allowed GFN. This didn't result
in any correctness issues, but it did end up shifting the test region
down slightly when using huge pages.

Suggested-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: David Matlack <dmatlack@google.com>
Message-Id: <20220520233249.3776001-12-dmatlack@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 .../testing/selftests/kvm/lib/perf_test_util.c | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/tools/testing/selftests/kvm/lib/perf_test_util.c b/tools/testing/selftests/kvm/lib/perf_test_util.c
index b2ff2cee2e51c..f989ff91f022a 100644
--- a/tools/testing/selftests/kvm/lib/perf_test_util.c
+++ b/tools/testing/selftests/kvm/lib/perf_test_util.c
@@ -110,6 +110,7 @@ struct kvm_vm *perf_test_create_vm(enum vm_guest_mode mode, int vcpus,
 	struct kvm_vm *vm;
 	uint64_t guest_num_pages, slot0_pages = DEFAULT_GUEST_PHY_PAGES;
 	uint64_t backing_src_pagesz = get_backing_src_pagesz(backing_src);
+	uint64_t region_end_gfn;
 	int i;
 
 	pr_info("Testing guest mode: %s\n", vm_guest_mode_string(mode));
@@ -151,18 +152,29 @@ struct kvm_vm *perf_test_create_vm(enum vm_guest_mode mode, int vcpus,
 
 	pta->vm = vm;
 
+	/* Put the test region at the top guest physical memory. */
+	region_end_gfn = vm_get_max_gfn(vm) + 1;
+
+#ifdef __x86_64__
+	/*
+	 * When running vCPUs in L2, restrict the test region to 48 bits to
+	 * avoid needing 5-level page tables to identity map L2.
+	 */
+	if (pta->nested)
+		region_end_gfn = min(region_end_gfn, (1UL << 48) / pta->guest_page_size);
+#endif
 	/*
 	 * If there should be more memory in the guest test region than there
 	 * can be pages in the guest, it will definitely cause problems.
 	 */
-	TEST_ASSERT(guest_num_pages < vm_get_max_gfn(vm),
+	TEST_ASSERT(guest_num_pages < region_end_gfn,
 		    "Requested more guest memory than address space allows.\n"
 		    "    guest pages: %" PRIx64 " max gfn: %" PRIx64
 		    " vcpus: %d wss: %" PRIx64 "]\n",
-		    guest_num_pages, vm_get_max_gfn(vm), vcpus,
+		    guest_num_pages, region_end_gfn - 1, vcpus,
 		    vcpu_memory_bytes);
 
-	pta->gpa = (vm_get_max_gfn(vm) - guest_num_pages) * pta->guest_page_size;
+	pta->gpa = (region_end_gfn - guest_num_pages) * pta->guest_page_size;
 	pta->gpa = align_down(pta->gpa, backing_src_pagesz);
 #ifdef __s390x__
 	/* Align to 1M (segment size) */
-- 
GitLab


From 668a9fe5c6a1bcac6b65d5e9b91a9eca86f782a3 Mon Sep 17 00:00:00 2001
From: Marc Zyngier <maz@kernel.org>
Date: Wed, 8 Jun 2022 14:45:35 +0100
Subject: [PATCH 0399/1731] genirq: PM: Use runtime PM for chained interrupts

When requesting an interrupt, we correctly call into the runtime
PM framework to guarantee that the underlying interrupt controller
is up and running.

However, we fail to do so for chained interrupt controllers, as
the mux interrupt is not requested along the same path.

Augment __irq_do_set_handler() to call into the runtime PM code
in this case, making sure the PM flow is the same for all interrupts.

Reported-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/26973cddee5f527ea17184c0f3fccb70bc8969a0.camel@pengutronix.de
---
 kernel/irq/chip.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
index e6b8e564b37f0..886789dcee435 100644
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -1006,8 +1006,10 @@ __irq_do_set_handler(struct irq_desc *desc, irq_flow_handler_t handle,
 		if (desc->irq_data.chip != &no_irq_chip)
 			mask_ack_irq(desc);
 		irq_state_set_disabled(desc);
-		if (is_chained)
+		if (is_chained) {
 			desc->action = NULL;
+			WARN_ON(irq_chip_pm_put(irq_desc_get_irq_data(desc)));
+		}
 		desc->depth = 1;
 	}
 	desc->handle_irq = handle;
@@ -1033,6 +1035,7 @@ __irq_do_set_handler(struct irq_desc *desc, irq_flow_handler_t handle,
 		irq_settings_set_norequest(desc);
 		irq_settings_set_nothread(desc);
 		desc->action = &chained_action;
+		WARN_ON(irq_chip_pm_get(irq_desc_get_irq_data(desc)));
 		irq_activate_and_startup(desc, IRQ_RESEND);
 	}
 }
-- 
GitLab


From 22ffb89ee3ab3557d2caa57fb67f8a195f252be0 Mon Sep 17 00:00:00 2001
From: Xinlei Lee <xinlei.lee@mediatek.com>
Date: Wed, 4 May 2022 17:19:20 +0800
Subject: [PATCH 0400/1731] dt-bindings: display: mediatek: dsi: Convert
 dsi_dtbinding to .yaml

Convert mediatek,dsi.txt to mediatek,dsi.yaml format

Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220504091923.2219-2-rex-bc.chen@mediatek.com/
Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 .../display/mediatek/mediatek,dsi.txt         |  62 ----------
 .../display/mediatek/mediatek,dsi.yaml        | 115 ++++++++++++++++++
 2 files changed, 115 insertions(+), 62 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
deleted file mode 100644
index 36b01458f45cf..0000000000000
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ /dev/null
@@ -1,62 +0,0 @@
-Mediatek DSI Device
-===================
-
-The Mediatek DSI function block is a sink of the display subsystem and can
-drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
-channel output.
-
-Required properties:
-- compatible: "mediatek,<chip>-dsi"
-- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
-- reg: Physical base address and length of the controller's registers
-- interrupts: The interrupt signal from the function block.
-- clocks: device clocks
-  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- clock-names: must contain "engine", "digital", and "hs"
-- phys: phandle link to the MIPI D-PHY controller.
-- phy-names: must contain "dphy"
-- port: Output port node with endpoint definitions as described in
-  Documentation/devicetree/bindings/graph.txt. This port should be connected
-  to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
-
-Optional properties:
-- resets: list of phandle + reset specifier pair, as described in [1].
-
-[1] Documentation/devicetree/bindings/reset/reset.txt
-
-MIPI TX Configuration Module
-============================
-
-See phy/mediatek,dsi-phy.yaml
-
-Example:
-
-mipi_tx0: mipi-dphy@10215000 {
-	compatible = "mediatek,mt8173-mipi-tx";
-	reg = <0 0x10215000 0 0x1000>;
-	clocks = <&clk26m>;
-	clock-output-names = "mipi_tx0_pll";
-	#clock-cells = <0>;
-	#phy-cells = <0>;
-	drive-strength-microamp = <4600>;
-	nvmem-cells= <&mipi_tx_calibration>;
-	nvmem-cell-names = "calibration-data";
-};
-
-dsi0: dsi@1401b000 {
-	compatible = "mediatek,mt8173-dsi";
-	reg = <0 0x1401b000 0 0x1000>;
-	interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
-	clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
-		 <&mipi_tx0>;
-	clock-names = "engine", "digital", "hs";
-	resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
-	phys = <&mipi_tx0>;
-	phy-names = "dphy";
-
-	port {
-		dsi0_out: endpoint {
-			remote-endpoint = <&panel_in>;
-		};
-	};
-};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
new file mode 100644
index 0000000000000..fa5bdf28668ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek DSI Controller Device Tree Bindings
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+  - Jitao Shi <jitao.shi@mediatek.com>
+  - Xinlei Lee <xinlei.lee@mediatek.com>
+
+description: |
+  The MediaTek DSI function block is a sink of the display subsystem and can
+  drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
+  channel output.
+
+allOf:
+  - $ref: /schemas/display/dsi-controller.yaml#
+
+properties:
+  compatible:
+    enum:
+      - mediatek,mt2701-dsi
+      - mediatek,mt7623-dsi
+      - mediatek,mt8167-dsi
+      - mediatek,mt8173-dsi
+      - mediatek,mt8183-dsi
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Engine Clock
+      - description: Digital Clock
+      - description: HS Clock
+
+  clock-names:
+    items:
+      - const: engine
+      - const: digital
+      - const: hs
+
+  resets:
+    maxItems: 1
+
+  phys:
+    maxItems: 1
+
+  phy-names:
+    items:
+      - const: dphy
+
+  port:
+    $ref: /schemas/graph.yaml#/properties/port
+    description:
+      Output port node. This port should be connected to the input
+      port of an attached DSI panel or DSI-to-eDP encoder chip.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+  - clock-names
+  - phys
+  - phy-names
+  - port
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/mt8183-clk.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/power/mt8183-power.h>
+    #include <dt-bindings/phy/phy.h>
+    #include <dt-bindings/reset/mt8183-resets.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        dsi0: dsi@14014000 {
+            compatible = "mediatek,mt8183-dsi";
+            reg = <0 0x14014000 0 0x1000>;
+            interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
+            power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+            clocks = <&mmsys CLK_MM_DSI0_MM>,
+                <&mmsys CLK_MM_DSI0_IF>,
+                <&mipi_tx0>;
+            clock-names = "engine", "digital", "hs";
+            resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
+            phys = <&mipi_tx0>;
+            phy-names = "dphy";
+            port {
+                dsi0_out: endpoint {
+                    remote-endpoint = <&panel_in>;
+                };
+            };
+        };
+    };
+
+...
-- 
GitLab


From f7fe4264ad5852bfb99a89e2649e48b8abcc4fc4 Mon Sep 17 00:00:00 2001
From: Xinlei Lee <xinlei.lee@mediatek.com>
Date: Wed, 4 May 2022 17:19:21 +0800
Subject: [PATCH 0401/1731] dt-bindings: display: mediatek: dsi: Add compatible
 for MediaTek MT8186

Add dt-binding documentation of dsi for MediaTek MT8186 SoC.

Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220504091923.2219-3-rex-bc.chen@mediatek.com/
Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 .../devicetree/bindings/display/mediatek/mediatek,dsi.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
index fa5bdf28668ac..b18d6a57c6e1b 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
@@ -28,6 +28,7 @@ properties:
       - mediatek,mt8167-dsi
       - mediatek,mt8173-dsi
       - mediatek,mt8183-dsi
+      - mediatek,mt8186-dsi
 
   reg:
     maxItems: 1
-- 
GitLab


From 03d7adc41027a5216dc2cc9c3c09de02477b94b3 Mon Sep 17 00:00:00 2001
From: Xinlei Lee <xinlei.lee@mediatek.com>
Date: Wed, 4 May 2022 17:19:22 +0800
Subject: [PATCH 0402/1731] drm/mediatek: Add mt8186 dsi compatible to
 mtk_dsi.c

Add the compatible because use different cmdq addresses in mt8186.

Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220504091923.2219-4-rex-bc.chen@mediatek.com/
Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index af2f123e9a9a9..9cc406e1eee19 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -1199,6 +1199,12 @@ static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
 	.has_size_ctl = true,
 };
 
+static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = {
+	.reg_cmdq_off = 0xd00,
+	.has_shadow_ctl = true,
+	.has_size_ctl = true,
+};
+
 static const struct of_device_id mtk_dsi_of_match[] = {
 	{ .compatible = "mediatek,mt2701-dsi",
 	  .data = &mt2701_dsi_driver_data },
@@ -1206,6 +1212,8 @@ static const struct of_device_id mtk_dsi_of_match[] = {
 	  .data = &mt8173_dsi_driver_data },
 	{ .compatible = "mediatek,mt8183-dsi",
 	  .data = &mt8183_dsi_driver_data },
+	{ .compatible = "mediatek,mt8186-dsi",
+	  .data = &mt8186_dsi_driver_data },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, mtk_dsi_of_match);
-- 
GitLab


From 5bb4f80716e2f0b2a059f8273acd6c69f3bce239 Mon Sep 17 00:00:00 2001
From: Rex-BC Chen <rex-bc.chen@mediatek.com>
Date: Wed, 4 May 2022 17:19:23 +0800
Subject: [PATCH 0403/1731] drm/mediatek: Add MT8186 DSI compatible for
 mtk_drm_drv.c

The compatible "mediatek,mt8186-dsi" is used by MT8186 DSI, so
add it to mtk_ddp_comp_dt_ids in mtk_drm_drv.c.

Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220504091923.2219-5-rex-bc.chen@mediatek.com/
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 076ef59c0c0b3..42e27ca423a22 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -641,6 +641,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DSI },
 	{ .compatible = "mediatek,mt8183-dsi",
 	  .data = (void *)MTK_DSI },
+	{ .compatible = "mediatek,mt8186-dsi",
+	  .data = (void *)MTK_DSI },
 	{ }
 };
 
-- 
GitLab


From c3238d36c3a2be0a29a9d848d6c51e1b14be6692 Mon Sep 17 00:00:00 2001
From: Grzegorz Szczurek <grzegorzx.szczurek@intel.com>
Date: Fri, 29 Apr 2022 14:27:08 +0200
Subject: [PATCH 0404/1731] i40e: Fix adding ADQ filter to TC0

Procedure of configure tc flower filters erroneously allows to create
filters on TC0 where unfiltered packets are also directed by default.
Issue was caused by insufficient checks of hw_tc parameter specifying
the hardware traffic class to pass matching packets to.

Fix checking hw_tc parameter which blocks creation of filters on TC0.

Fixes: 2f4b411a3d67 ("i40e: Enable cloud filters via tc-flower")
Signed-off-by: Grzegorz Szczurek <grzegorzx.szczurek@intel.com>
Signed-off-by: Jedrzej Jagielski <jedrzej.jagielski@intel.com>
Tested-by: Bharathi Sreenivas <bharathi.sreenivas@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
---
 drivers/net/ethernet/intel/i40e/i40e_main.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c
index 332a608dbaa68..72576bb3e94d4 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_main.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_main.c
@@ -8542,6 +8542,11 @@ static int i40e_configure_clsflower(struct i40e_vsi *vsi,
 		return -EOPNOTSUPP;
 	}
 
+	if (!tc) {
+		dev_err(&pf->pdev->dev, "Unable to add filter because of invalid destination");
+		return -EINVAL;
+	}
+
 	if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
 	    test_bit(__I40E_RESET_INTR_RECEIVED, pf->state))
 		return -EBUSY;
-- 
GitLab


From 0bb050670ac90a167ecfa3f9590f92966c9a3677 Mon Sep 17 00:00:00 2001
From: Grzegorz Szczurek <grzegorzx.szczurek@intel.com>
Date: Fri, 29 Apr 2022 14:40:23 +0200
Subject: [PATCH 0405/1731] i40e: Fix calculating the number of queue pairs

If ADQ is enabled for a VF, then actual number of queue pair
is a number of currently available traffic classes for this VF.

Without this change the configuration of the Rx/Tx queues
fails with error.

Fixes: d29e0d233e0d ("i40e: missing input validation on VF message handling by the PF")
Signed-off-by: Grzegorz Szczurek <grzegorzx.szczurek@intel.com>
Signed-off-by: Jedrzej Jagielski <jedrzej.jagielski@intel.com>
Tested-by: Bharathi Sreenivas <bharathi.sreenivas@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
---
 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
index 2606e8f0f19be..033ea71763e3d 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
@@ -2282,7 +2282,7 @@ static int i40e_vc_config_queues_msg(struct i40e_vf *vf, u8 *msg)
 	}
 
 	if (vf->adq_enabled) {
-		for (i = 0; i < I40E_MAX_VF_VSI; i++)
+		for (i = 0; i < vf->num_tc; i++)
 			num_qps_all += vf->ch[i].num_qps;
 		if (num_qps_all != qci->num_queue_pairs) {
 			aq_ret = I40E_ERR_PARAM;
-- 
GitLab


From fd5855e6b1358e816710afee68a1d2bc685176ca Mon Sep 17 00:00:00 2001
From: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Date: Thu, 19 May 2022 16:01:45 +0200
Subject: [PATCH 0406/1731] i40e: Fix call trace in setup_tx_descriptors

After PF reset and ethtool -t there was call trace in dmesg
sometimes leading to panic. When there was some time, around 5
seconds, between reset and test there were no errors.

Problem was that pf reset calls i40e_vsi_close in prep_for_reset
and ethtool -t calls i40e_vsi_close in diag_test. If there was not
enough time between those commands the second i40e_vsi_close starts
before previous i40e_vsi_close was done which leads to crash.

Add check to diag_test if pf is in reset and don't start offline
tests if it is true.
Add netif_info("testing failed") into unhappy path of i40e_diag_test()

Fixes: e17bc411aea8 ("i40e: Disable offline diagnostics if VFs are enabled")
Fixes: 510efb2682b3 ("i40e: Fix ethtool offline diagnostic with netqueues")
Signed-off-by: Michal Jaron <michalx.jaron@intel.com>
Signed-off-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Tested-by: Gurucharan <gurucharanx.g@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
---
 .../net/ethernet/intel/i40e/i40e_ethtool.c    | 25 +++++++++++++------
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c
index 610f00cbaff98..19704f5c8291c 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c
@@ -2586,15 +2586,16 @@ static void i40e_diag_test(struct net_device *netdev,
 
 		set_bit(__I40E_TESTING, pf->state);
 
+		if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
+		    test_bit(__I40E_RESET_INTR_RECEIVED, pf->state)) {
+			dev_warn(&pf->pdev->dev,
+				 "Cannot start offline testing when PF is in reset state.\n");
+			goto skip_ol_tests;
+		}
+
 		if (i40e_active_vfs(pf) || i40e_active_vmdqs(pf)) {
 			dev_warn(&pf->pdev->dev,
 				 "Please take active VFs and Netqueues offline and restart the adapter before running NIC diagnostics\n");
-			data[I40E_ETH_TEST_REG]		= 1;
-			data[I40E_ETH_TEST_EEPROM]	= 1;
-			data[I40E_ETH_TEST_INTR]	= 1;
-			data[I40E_ETH_TEST_LINK]	= 1;
-			eth_test->flags |= ETH_TEST_FL_FAILED;
-			clear_bit(__I40E_TESTING, pf->state);
 			goto skip_ol_tests;
 		}
 
@@ -2641,9 +2642,17 @@ static void i40e_diag_test(struct net_device *netdev,
 		data[I40E_ETH_TEST_INTR] = 0;
 	}
 
-skip_ol_tests:
-
 	netif_info(pf, drv, netdev, "testing finished\n");
+	return;
+
+skip_ol_tests:
+	data[I40E_ETH_TEST_REG]		= 1;
+	data[I40E_ETH_TEST_EEPROM]	= 1;
+	data[I40E_ETH_TEST_INTR]	= 1;
+	data[I40E_ETH_TEST_LINK]	= 1;
+	eth_test->flags |= ETH_TEST_FL_FAILED;
+	clear_bit(__I40E_TESTING, pf->state);
+	netif_info(pf, drv, netdev, "testing failed\n");
 }
 
 static void i40e_get_wol(struct net_device *netdev,
-- 
GitLab


From 645603844270b69175899268be68b871295764fe Mon Sep 17 00:00:00 2001
From: Michal Wilczynski <michal.wilczynski@intel.com>
Date: Fri, 20 May 2022 13:19:27 +0200
Subject: [PATCH 0407/1731] iavf: Fix issue with MAC address of VF shown as
 zero

After reinitialization of iavf, ice driver gets VIRTCHNL_OP_ADD_ETH_ADDR
message with incorrectly set type of MAC address. Hardware address should
have is_primary flag set as true. This way ice driver knows what it has
to set as a MAC address.

Check if the address is primary in iavf_add_filter function and set flag
accordingly.

To test set all-zero MAC on a VF. This triggers iavf re-initialization
and VIRTCHNL_OP_ADD_ETH_ADDR message gets sent to PF.
For example:

ip link set dev ens785 vf 0 mac 00:00:00:00:00:00

This triggers re-initialization of iavf. New MAC should be assigned.
Now check if MAC is non-zero:

ip link show dev ens785

Fixes: a3e839d539e0 ("iavf: Add usage of new virtchnl format to set default MAC")
Signed-off-by: Michal Wilczynski <michal.wilczynski@intel.com>
Reviewed-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com>
Tested-by: Konrad Jankowski <konrad0.jankowski@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
---
 drivers/net/ethernet/intel/iavf/iavf_main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/intel/iavf/iavf_main.c b/drivers/net/ethernet/intel/iavf/iavf_main.c
index 7dfcf78b57fb5..f3ecb3bca33dd 100644
--- a/drivers/net/ethernet/intel/iavf/iavf_main.c
+++ b/drivers/net/ethernet/intel/iavf/iavf_main.c
@@ -984,7 +984,7 @@ struct iavf_mac_filter *iavf_add_filter(struct iavf_adapter *adapter,
 		list_add_tail(&f->list, &adapter->mac_filter_list);
 		f->add = true;
 		f->is_new_mac = true;
-		f->is_primary = false;
+		f->is_primary = ether_addr_equal(macaddr, adapter->hw.mac.addr);
 		adapter->aq_required |= IAVF_FLAG_AQ_ADD_MAC_FILTER;
 	} else {
 		f->remove = false;
-- 
GitLab


From b84dc7f0e3646d480b6972c5f25586215c5f33e2 Mon Sep 17 00:00:00 2001
From: Jamie Iles <jamie@jamieiles.com>
Date: Mon, 6 Jun 2022 22:39:52 +0100
Subject: [PATCH 0408/1731] irqchip/xilinx: Remove microblaze+zynq dependency

The Xilinx IRQ controller doesn't really have any architecture
dependencies - it's a generic AXI component that can be used for any
FPGA core from Zynq hard processor systems to microblaze+riscv soft
cores and more.

Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220606213952.298686-1-jamie@jamieiles.com
---
 drivers/irqchip/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 4ab1038b54828..1f23a6be7d882 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -298,7 +298,7 @@ config XTENSA_MX
 
 config XILINX_INTC
 	bool "Xilinx Interrupt Controller IP"
-	depends on MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP
+	depends on OF
 	select IRQ_DOMAIN
 	help
 	  Support for the Xilinx Interrupt Controller IP core.
-- 
GitLab


From f4b98e314888cc51486421bcf6d52852452ea48b Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Wed, 1 Jun 2022 12:09:25 +0400
Subject: [PATCH 0409/1731] irqchip/gic/realview: Fix refcount leak in
 realview_gic_of_init

of_find_matching_node_and_match() returns a node pointer with refcount
incremented, we should use of_node_put() on it when not need anymore.
Add missing of_node_put() to avoid refcount leak.

Fixes: 82b0a434b436 ("irqchip/gic/realview: Support more RealView DCC variants")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220601080930.31005-2-linmq006@gmail.com
---
 drivers/irqchip/irq-gic-realview.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/irqchip/irq-gic-realview.c b/drivers/irqchip/irq-gic-realview.c
index b4c1924f02554..38fab02ffe9d0 100644
--- a/drivers/irqchip/irq-gic-realview.c
+++ b/drivers/irqchip/irq-gic-realview.c
@@ -57,6 +57,7 @@ realview_gic_of_init(struct device_node *node, struct device_node *parent)
 
 	/* The PB11MPCore GIC needs to be configured in the syscon */
 	map = syscon_node_to_regmap(np);
+	of_node_put(np);
 	if (!IS_ERR(map)) {
 		/* new irq mode with no DCC */
 		regmap_write(map, REALVIEW_SYS_LOCK_OFFSET,
-- 
GitLab


From b1ac803f47cb1615468f35cf1ccb553c52087301 Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Wed, 1 Jun 2022 12:09:26 +0400
Subject: [PATCH 0410/1731] irqchip/apple-aic: Fix refcount leak in
 build_fiq_affinity

of_find_node_by_phandle() returns a node pointer with refcount
incremented, we should use of_node_put() on it when not need anymore.
Add missing of_node_put() to avoid refcount leak.

Fixes: a5e8801202b3 ("irqchip/apple-aic: Parse FIQ affinities from device-tree")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220601080930.31005-3-linmq006@gmail.com
---
 drivers/irqchip/irq-apple-aic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-aic.c
index 12dd48727a15f..478d0af16d9fa 100644
--- a/drivers/irqchip/irq-apple-aic.c
+++ b/drivers/irqchip/irq-apple-aic.c
@@ -1035,6 +1035,7 @@ static void build_fiq_affinity(struct aic_irq_chip *ic, struct device_node *aff)
 			continue;
 
 		cpu = of_cpu_node_to_id(cpu_node);
+		of_node_put(cpu_node);
 		if (WARN_ON(cpu < 0))
 			continue;
 
-- 
GitLab


From 3d45670fab3c25a7452721e4588cc95c51cda134 Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Wed, 1 Jun 2022 12:09:27 +0400
Subject: [PATCH 0411/1731] irqchip/apple-aic: Fix refcount leak in
 aic_of_ic_init

of_get_child_by_name() returns a node pointer with refcount
incremented, we should use of_node_put() on it when not need anymore.
Add missing of_node_put() to avoid refcount leak.

Fixes: a5e8801202b3 ("irqchip/apple-aic: Parse FIQ affinities from device-tree")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220601080930.31005-4-linmq006@gmail.com
---
 drivers/irqchip/irq-apple-aic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-aic.c
index 478d0af16d9fa..5ac83185ff479 100644
--- a/drivers/irqchip/irq-apple-aic.c
+++ b/drivers/irqchip/irq-apple-aic.c
@@ -1144,6 +1144,7 @@ static int __init aic_of_ic_init(struct device_node *node, struct device_node *p
 		for_each_child_of_node(affs, chld)
 			build_fiq_affinity(irqc, chld);
 	}
+	of_node_put(affs);
 
 	set_handle_irq(aic_handle_irq);
 	set_handle_fiq(aic_handle_fiq);
-- 
GitLab


From ec8401a429ffee34ccf38cebf3443f8d5ae6cb0d Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Wed, 1 Jun 2022 12:09:28 +0400
Subject: [PATCH 0412/1731] irqchip/gic-v3: Fix error handling in
 gic_populate_ppi_partitions

of_get_child_by_name() returns a node pointer with refcount
incremented, we should use of_node_put() on it when not need anymore.
When kcalloc fails, it missing of_node_put() and results in refcount
leak. Fix this by goto out_put_node label.

Fixes: 52085d3f2028 ("irqchip/gic-v3: Dynamically allocate PPI partition descriptors")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220601080930.31005-5-linmq006@gmail.com
---
 drivers/irqchip/irq-gic-v3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 2be8dea6b6b00..1d5b4755a27e2 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -1932,7 +1932,7 @@ static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
 
 	gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL);
 	if (!gic_data.ppi_descs)
-		return;
+		goto out_put_node;
 
 	nr_parts = of_get_child_count(parts_node);
 
-- 
GitLab


From fa1ad9d4cc47ca2470cd904ad4519f05d7e43a2b Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Wed, 1 Jun 2022 12:09:29 +0400
Subject: [PATCH 0413/1731] irqchip/gic-v3: Fix refcount leak in
 gic_populate_ppi_partitions

of_find_node_by_phandle() returns a node pointer with refcount
incremented, we should use of_node_put() on it when not need anymore.
Add missing of_node_put() to avoid refcount leak.

Fixes: e3825ba1af3a ("irqchip/gic-v3: Add support for partitioned PPIs")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220601080930.31005-6-linmq006@gmail.com
---
 drivers/irqchip/irq-gic-v3.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 1d5b4755a27e2..5c1cf907ee68d 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -1973,12 +1973,15 @@ static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
 				continue;
 
 			cpu = of_cpu_node_to_id(cpu_node);
-			if (WARN_ON(cpu < 0))
+			if (WARN_ON(cpu < 0)) {
+				of_node_put(cpu_node);
 				continue;
+			}
 
 			pr_cont("%pOF[%d] ", cpu_node, cpu);
 
 			cpumask_set_cpu(cpu, &part->mask);
+			of_node_put(cpu_node);
 		}
 
 		pr_cont("}\n");
-- 
GitLab


From eff4780f83d0ae3e5b6c02ff5d999dc4c1c5c8ce Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Wed, 1 Jun 2022 12:09:30 +0400
Subject: [PATCH 0414/1731] irqchip/realtek-rtl: Fix refcount leak in
 map_interrupts

of_find_node_by_phandle() returns a node pointer with refcount
incremented, we should use of_node_put() on it when not need anymore.
This function doesn't call of_node_put() in error path.
Call of_node_put() directly after of_property_read_u32() to cover
both normal path and error path.

Fixes: 9f3a0f34b84a ("irqchip: Add support for Realtek RTL838x/RTL839x interrupt controller")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220601080930.31005-7-linmq006@gmail.com
---
 drivers/irqchip/irq-realtek-rtl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-realtek-rtl.c b/drivers/irqchip/irq-realtek-rtl.c
index 50a56820c99bc..56bf502d9c673 100644
--- a/drivers/irqchip/irq-realtek-rtl.c
+++ b/drivers/irqchip/irq-realtek-rtl.c
@@ -134,9 +134,9 @@ static int __init map_interrupts(struct device_node *node, struct irq_domain *do
 		if (!cpu_ictl)
 			return -EINVAL;
 		ret = of_property_read_u32(cpu_ictl, "#interrupt-cells", &tmp);
+		of_node_put(cpu_ictl);
 		if (ret || tmp != 1)
 			return -EINVAL;
-		of_node_put(cpu_ictl);
 
 		cpu_int = be32_to_cpup(imap + 2);
 		if (cpu_int > 7 || cpu_int < 2)
-- 
GitLab


From df089e6f07e3c94cb7a330dc74f5041db800009c Mon Sep 17 00:00:00 2001
From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Date: Fri, 20 May 2022 14:17:01 +0900
Subject: [PATCH 0415/1731] dt-bindings: interrupt-controller/uniphier-aidet:
 Add bindings for NX1 SoC

Update uniphier-aidet binding document for UniPhier NX1 SoC.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/1653023822-19229-2-git-send-email-hayashi.kunihiko@socionext.com
---
 .../bindings/interrupt-controller/socionext,uniphier-aidet.yaml  | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.yaml b/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.yaml
index f89ebde76dab3..de7c5e59bae14 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.yaml
@@ -30,6 +30,7 @@ properties:
       - socionext,uniphier-ld11-aidet
       - socionext,uniphier-ld20-aidet
       - socionext,uniphier-pxs3-aidet
+      - socionext,uniphier-nx1-aidet
 
   reg:
     maxItems: 1
-- 
GitLab


From e3f056a7aafabe4ac3ad4b7465ba821b44a7e639 Mon Sep 17 00:00:00 2001
From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Date: Fri, 20 May 2022 14:17:02 +0900
Subject: [PATCH 0416/1731] irqchip/uniphier-aidet: Add compatible string for
 NX1 SoC

Add the compatible string to support UniPhier NX1 SoC, which has the same
kinds of controls as the other UniPhier SoCs.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/1653023822-19229-3-git-send-email-hayashi.kunihiko@socionext.com
---
 drivers/irqchip/irq-uniphier-aidet.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/irqchip/irq-uniphier-aidet.c b/drivers/irqchip/irq-uniphier-aidet.c
index 89121b39be269..716b1bb88bf2b 100644
--- a/drivers/irqchip/irq-uniphier-aidet.c
+++ b/drivers/irqchip/irq-uniphier-aidet.c
@@ -237,6 +237,7 @@ static const struct of_device_id uniphier_aidet_match[] = {
 	{ .compatible = "socionext,uniphier-ld11-aidet" },
 	{ .compatible = "socionext,uniphier-ld20-aidet" },
 	{ .compatible = "socionext,uniphier-pxs3-aidet" },
+	{ .compatible = "socionext,uniphier-nx1-aidet" },
 	{ /* sentinel */ }
 };
 
-- 
GitLab


From 5c57c099f442acab13129c9e15ad2a0c31151c98 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com>
Date: Wed, 8 Jun 2022 13:33:44 -0700
Subject: [PATCH 0417/1731] drm/i915/display: Fix handling of enable_psr
 parameter
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Commit 3cf050762534 ("drm/i915/bios: Split VBT data into per-panel vs.
global parts") cause PSR to be disabled when enable_psr has the
default value and there is at least one DP port that do not supports
PSR.

That was happening because intel_psr_init() is called for every DP
port and then enable_psr is globaly set to 0 based on the PSR support
of the DP port.

Here dropping the enable_psr overwritten and using the VBT PSR value
when enable_psr is set as default.

Fixes: 3cf050762534 ("drm/i915/bios: Split VBT data into per-panel vs. global parts")
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Jouni Högander <jouni.hogander@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220608203344.513082-1-jose.souza@intel.com
---
 drivers/gpu/drm/i915/display/intel_psr.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index aedb3e0e69ecd..7d61c55184e51 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -86,10 +86,13 @@
 
 static bool psr_global_enabled(struct intel_dp *intel_dp)
 {
+	struct intel_connector *connector = intel_dp->attached_connector;
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 
 	switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
 	case I915_PSR_DEBUG_DEFAULT:
+		if (i915->params.enable_psr == -1)
+			return connector->panel.vbt.psr.enable;
 		return i915->params.enable_psr;
 	case I915_PSR_DEBUG_DISABLE:
 		return false;
@@ -2394,10 +2397,6 @@ void intel_psr_init(struct intel_dp *intel_dp)
 
 	intel_dp->psr.source_support = true;
 
-	if (dev_priv->params.enable_psr == -1)
-		if (!connector->panel.vbt.psr.enable)
-			dev_priv->params.enable_psr = 0;
-
 	/* Set link_standby x link_off defaults */
 	if (DISPLAY_VER(dev_priv) < 12)
 		/* For new platforms up to TGL let's respect VBT back again */
-- 
GitLab


From a1ea0857b59757733d58908dd55bf4b722ee574f Mon Sep 17 00:00:00 2001
From: Wei Yongjun <weiyongjun1@huawei.com>
Date: Wed, 8 Jun 2022 02:11:54 +0000
Subject: [PATCH 0418/1731] clk: stm32: rcc_reset: Fix missing spin_lock_init()

The driver allocates the spinlock but not initialize it.
Use spin_lock_init() on it to initialize it correctly.

Fixes: 637cee5ffc71 ("clk: stm32: Introduce STM32MP13 RCC drivers (Reset Clock Controller)")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Link: https://lore.kernel.org/r/20220608021154.990347-1-weiyongjun1@huawei.com
Tested-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
 drivers/clk/stm32/reset-stm32.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/stm32/reset-stm32.c b/drivers/clk/stm32/reset-stm32.c
index 040870130e4b8..e89381528af99 100644
--- a/drivers/clk/stm32/reset-stm32.c
+++ b/drivers/clk/stm32/reset-stm32.c
@@ -111,6 +111,7 @@ int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match,
 	if (!reset_data)
 		return -ENOMEM;
 
+	spin_lock_init(&reset_data->lock);
 	reset_data->membase = base;
 	reset_data->rcdev.owner = THIS_MODULE;
 	reset_data->rcdev.ops = &stm32_reset_ops;
-- 
GitLab


From 34d2cd3fccced12b958b8848e3eff0ee4296764c Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Thu, 12 May 2022 06:16:10 +0400
Subject: [PATCH 0419/1731] ARM: meson: Fix refcount leak in
 meson_smp_prepare_cpus

of_find_compatible_node() returns a node pointer with refcount
incremented, we should use of_node_put() on it when done.
Add missing of_node_put() to avoid refcount leak.

Fixes: d850f3e5d296 ("ARM: meson: Add SMP bringup code for Meson8 and Meson8b")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20220512021611.47921-1-linmq006@gmail.com
---
 arch/arm/mach-meson/platsmp.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-meson/platsmp.c b/arch/arm/mach-meson/platsmp.c
index 4b8ad728bb42a..32ac60b89fdcc 100644
--- a/arch/arm/mach-meson/platsmp.c
+++ b/arch/arm/mach-meson/platsmp.c
@@ -71,6 +71,7 @@ static void __init meson_smp_prepare_cpus(const char *scu_compatible,
 	}
 
 	sram_base = of_iomap(node, 0);
+	of_node_put(node);
 	if (!sram_base) {
 		pr_err("Couldn't map SRAM registers\n");
 		return;
@@ -91,6 +92,7 @@ static void __init meson_smp_prepare_cpus(const char *scu_compatible,
 	}
 
 	scu_base = of_iomap(node, 0);
+	of_node_put(node);
 	if (!scu_base) {
 		pr_err("Couldn't map SCU registers\n");
 		return;
-- 
GitLab


From de0952f267ffe9d4ecbfeab7c476f7e29e028b3e Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas <javierm@redhat.com>
Date: Fri, 10 Jun 2022 00:34:24 +0200
Subject: [PATCH 0420/1731] staging: olpc_dcon: mark driver as broken

The commit eecb3e4e5d9d ("staging: olpc_dcon: add OLPC display controller
(DCON) support") added this driver in 2010, and has been in staging since
then. It was marked as broken at some point because it didn't even build
but that got removed once the build issues were addressed.

But it seems that the work to move this driver out of staging has stalled,
the last non-trivial change to fix one of the items mentioned in its todo
file was commit e40219d5e4b2 ("staging: olpc_dcon: allow simultaneous XO-1
and XO-1.5 support") in 2019.

And even if work to destage the driver is resumed, the fbdev subsystem has
been deprecated for a long time and instead it should be ported to DRM.

Now this driver is preventing to land a kernel wide change, that makes the
num_registered_fb symbol to be private to the fbmem.c file.

So let's just mark the driver as broken. Someone can then work on making
it not depend on the num_registered_fb symbol, allowing to drop the broken
dependency again.

Suggested-by: Sam Ravnborg <sam@ravnborg.org>
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Link: https://lore.kernel.org/r/20220609223424.907174-1-javierm@redhat.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/staging/olpc_dcon/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/olpc_dcon/Kconfig b/drivers/staging/olpc_dcon/Kconfig
index d1a0dea09ef01..d0ba34cc32f7a 100644
--- a/drivers/staging/olpc_dcon/Kconfig
+++ b/drivers/staging/olpc_dcon/Kconfig
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 config FB_OLPC_DCON
 	tristate "One Laptop Per Child Display CONtroller support"
-	depends on OLPC && FB
+	depends on OLPC && FB && BROKEN
 	depends on I2C
 	depends on GPIO_CS5535 && ACPI
 	select BACKLIGHT_CLASS_DEVICE
-- 
GitLab


From 67ea0a2adbf667cd6da4965fbcfd0da741035084 Mon Sep 17 00:00:00 2001
From: Kees Cook <keescook@chromium.org>
Date: Wed, 8 Jun 2022 14:55:12 -0700
Subject: [PATCH 0421/1731] staging: rtl8723bs: Allocate full pwep structure

The pwep allocation was always being allocated smaller than the true
structure size. Avoid this by always allocating the full structure.
Found with GCC 12 and -Warray-bounds:

../drivers/staging/rtl8723bs/os_dep/ioctl_linux.c: In function 'rtw_set_encryption':
../drivers/staging/rtl8723bs/os_dep/ioctl_linux.c:591:29: warning: array subscript 'struct ndis_802_11_wep[0]' is partly outside array bounds of 'void[25]' [-Warray-bounds]
  591 |                         pwep->length = wep_total_len;
      |                             ^~

Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Fabio Aiuto <fabioaiuto83@gmail.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: linux-staging@lists.linux.dev
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/20220608215512.1070847-1-keescook@chromium.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/rtl8723bs/os_dep/ioctl_linux.c b/drivers/staging/rtl8723bs/os_dep/ioctl_linux.c
index ece97e37ac91d..30374a820496e 100644
--- a/drivers/staging/rtl8723bs/os_dep/ioctl_linux.c
+++ b/drivers/staging/rtl8723bs/os_dep/ioctl_linux.c
@@ -90,7 +90,8 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param,
 		if (wep_key_len > 0) {
 			wep_key_len = wep_key_len <= 5 ? 5 : 13;
 			wep_total_len = wep_key_len + FIELD_OFFSET(struct ndis_802_11_wep, key_material);
-			pwep = kzalloc(wep_total_len, GFP_KERNEL);
+			/* Allocate a full structure to avoid potentially running off the end. */
+			pwep = kzalloc(sizeof(*pwep), GFP_KERNEL);
 			if (!pwep) {
 				ret = -ENOMEM;
 				goto exit;
@@ -582,7 +583,8 @@ static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param,
 		if (wep_key_len > 0) {
 			wep_key_len = wep_key_len <= 5 ? 5 : 13;
 			wep_total_len = wep_key_len + FIELD_OFFSET(struct ndis_802_11_wep, key_material);
-			pwep = kzalloc(wep_total_len, GFP_KERNEL);
+			/* Allocate a full structure to avoid potentially running off the end. */
+			pwep = kzalloc(sizeof(*pwep), GFP_KERNEL);
 			if (!pwep)
 				goto exit;
 
-- 
GitLab


From 6fac824f40987a54a08dfbcc36145869d02e45b1 Mon Sep 17 00:00:00 2001
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: Thu, 9 Jun 2022 18:52:41 +0100
Subject: [PATCH 0422/1731] irqchip/loongson-liointc: Use architecture register
 to get coreid

fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for
LoongArch") replaced get_ebase_cpunum with physical processor
id from SMP facilities. However that breaks MIPS non-SMP build
and makes booting from other cores inpossible on non-SMP kernel.

Thus we revert get_ebase_cpunum back and use get_csr_cpuid for
LoongArch.

Fixes: fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for LoongArch")
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220609175242.977-1-jiaxun.yang@flygoat.com
---
 drivers/irqchip/irq-loongson-liointc.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index aed88857d90f1..8d05d8bcf56fe 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -39,6 +39,12 @@
 
 #define LIOINTC_ERRATA_IRQ	10
 
+#if defined(CONFIG_MIPS)
+#define liointc_core_id get_ebase_cpunum()
+#else
+#define liointc_core_id get_csr_cpuid()
+#endif
+
 struct liointc_handler_data {
 	struct liointc_priv	*priv;
 	u32			parent_int_map;
@@ -57,7 +63,7 @@ static void liointc_chained_handle_irq(struct irq_desc *desc)
 	struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 	struct irq_chip_generic *gc = handler->priv->gc;
-	int core = cpu_logical_map(smp_processor_id()) % LIOINTC_NUM_CORES;
+	int core = liointc_core_id % LIOINTC_NUM_CORES;
 	u32 pending;
 
 	chained_irq_enter(chip, desc);
-- 
GitLab


From b2e6b3d9bbb0a59ba7c710cc06e44cc548301f5f Mon Sep 17 00:00:00 2001
From: Soham Sen <contact@sohamsen.me>
Date: Thu, 9 Jun 2022 23:49:20 +0530
Subject: [PATCH 0423/1731] ALSA: hda/realtek: Add mute LED quirk for HP Omen
 laptop

The HP Omen 15 laptop needs a quirk to toggle the mute LED. It already is implemented for a different variant of the HP Omen laptop so a fixup entry is needed for this variant.

Signed-off-by: Soham Sen <contact@sohamsen.me>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20220609181919.45535-1-contact@sohamsen.me
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/pci/hda/patch_realtek.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index b0f954118e72e..a1a7842e7b5f3 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -9022,6 +9022,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
 		      ALC285_FIXUP_HP_GPIO_AMP_INIT),
 	SND_PCI_QUIRK(0x103c, 0x8783, "HP ZBook Fury 15 G7 Mobile Workstation",
 		      ALC285_FIXUP_HP_GPIO_AMP_INIT),
+	SND_PCI_QUIRK(0x103c, 0x8787, "HP OMEN 15", ALC285_FIXUP_HP_MUTE_LED),
 	SND_PCI_QUIRK(0x103c, 0x8788, "HP OMEN 15", ALC285_FIXUP_HP_MUTE_LED),
 	SND_PCI_QUIRK(0x103c, 0x87c8, "HP", ALC287_FIXUP_HP_GPIO_LED),
 	SND_PCI_QUIRK(0x103c, 0x87e5, "HP ProBook 440 G8 Notebook PC", ALC236_FIXUP_HP_GPIO_LED),
-- 
GitLab


From 552ca27929ab28b341ae9b2629f0de3a84c98ee8 Mon Sep 17 00:00:00 2001
From: Alexander Stein <alexander.stein@ew.tq-group.com>
Date: Tue, 10 May 2022 07:46:12 +0200
Subject: [PATCH 0424/1731] ARM: dts: imx7: Move hsic_phy power domain to HSIC
 PHY node

Move the power domain to its actual user. This keeps the power domain
enabled even when the USB host is runtime suspended. This is necessary
to detect any downstream events, like device attach.

Fixes: 02f8eb40ef7b ("ARM: dts: imx7s: Add power domain for imx7d HSIC")
Suggested-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 arch/arm/boot/dts/imx7s.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 008e3da460f1b..039eed79d2e73 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -120,6 +120,7 @@
 		compatible = "usb-nop-xceiv";
 		clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
 		clock-names = "main_clk";
+		power-domains = <&pgc_hsic_phy>;
 		#phy-cells = <0>;
 	};
 
@@ -1153,7 +1154,6 @@
 				compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
 				reg = <0x30b30000 0x200>;
 				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
-				power-domains = <&pgc_hsic_phy>;
 				clocks = <&clks IMX7D_USB_CTRL_CLK>;
 				fsl,usbphy = <&usbphynop3>;
 				fsl,usbmisc = <&usbmisc3 0>;
-- 
GitLab


From 656c5ba50b7172a0ea25dc1b37606bd51d01fe8d Mon Sep 17 00:00:00 2001
From: Saurabh Sengar <ssengar@linux.microsoft.com>
Date: Thu, 9 Jun 2022 10:16:36 -0700
Subject: [PATCH 0425/1731] Drivers: hv: vmbus: Release cpu lock in error case

In case of invalid sub channel, release cpu lock before returning.

Fixes: a949e86c0d780 ("Drivers: hv: vmbus: Resolve race between init_vp_index() and CPU hotplug")
Signed-off-by: Saurabh Sengar <ssengar@linux.microsoft.com>
Reviewed-by: Michael Kelley <mikelley@microsoft.com>
Link: https://lore.kernel.org/r/1654794996-13244-1-git-send-email-ssengar@linux.microsoft.com
Signed-off-by: Wei Liu <wei.liu@kernel.org>
---
 drivers/hv/channel_mgmt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/hv/channel_mgmt.c b/drivers/hv/channel_mgmt.c
index 280b529277589..5b120402d4057 100644
--- a/drivers/hv/channel_mgmt.c
+++ b/drivers/hv/channel_mgmt.c
@@ -639,6 +639,7 @@ static void vmbus_process_offer(struct vmbus_channel *newchannel)
 		 */
 		if (newchannel->offermsg.offer.sub_channel_index == 0) {
 			mutex_unlock(&vmbus_connection.channel_mutex);
+			cpus_read_unlock();
 			/*
 			 * Don't call free_channel(), because newchannel->kobj
 			 * is not initialized yet.
-- 
GitLab


From 9c1e916960c1192e746bf615e4dae25423473a64 Mon Sep 17 00:00:00 2001
From: Wesley Cheng <quic_wcheng@quicinc.com>
Date: Mon, 23 May 2022 14:39:48 -0700
Subject: [PATCH 0426/1731] usb: dwc3: gadget: Fix IN endpoint max packet size
 allocation

The current logic to assign the max packet limit for IN endpoints attempts
to take the default HW value and apply the optimal endpoint settings based
on it.  However, if the default value reports a TxFIFO size large enough
for only one max packet, it will divide the value and assign a smaller ep
max packet limit.

For example, if the default TxFIFO size fits 1024B, current logic will
assign 1024/3 = 341B to ep max packet size.  If function drivers attempt to
request for an endpoint with a wMaxPacketSize of 1024B (SS BULK max packet
size) then it will fail, as the gadget is unable to find an endpoint which
can fit the requested size.

Functionally, if the TxFIFO has enough space to fit one max packet, it will
be sufficient, at least when initializing the endpoints.

Fixes: d94ea5319813 ("usb: dwc3: gadget: Properly set maxpacket limit")
Cc: stable <stable@kernel.org>
Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
Link: https://lore.kernel.org/r/20220523213948.22142-1-quic_wcheng@quicinc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/dwc3/gadget.c | 26 +++++++++++++++-----------
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 00427d108ab9c..8716bece10720 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -2976,6 +2976,7 @@ static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
 	struct dwc3 *dwc = dep->dwc;
 	u32 mdwidth;
 	int size;
+	int maxpacket;
 
 	mdwidth = dwc3_mdwidth(dwc);
 
@@ -2988,21 +2989,24 @@ static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
 	else
 		size = DWC31_GTXFIFOSIZ_TXFDEP(size);
 
-	/* FIFO Depth is in MDWDITH bytes. Multiply */
-	size *= mdwidth;
-
 	/*
-	 * To meet performance requirement, a minimum TxFIFO size of 3x
-	 * MaxPacketSize is recommended for endpoints that support burst and a
-	 * minimum TxFIFO size of 2x MaxPacketSize for endpoints that don't
-	 * support burst. Use those numbers and we can calculate the max packet
-	 * limit as below.
+	 * maxpacket size is determined as part of the following, after assuming
+	 * a mult value of one maxpacket:
+	 * DWC3 revision 280A and prior:
+	 * fifo_size = mult * (max_packet / mdwidth) + 1;
+	 * maxpacket = mdwidth * (fifo_size - 1);
+	 *
+	 * DWC3 revision 290A and onwards:
+	 * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
+	 * maxpacket = mdwidth * ((fifo_size - 1) - 1) - mdwidth;
 	 */
-	if (dwc->maximum_speed >= USB_SPEED_SUPER)
-		size /= 3;
+	if (DWC3_VER_IS_PRIOR(DWC3, 290A))
+		maxpacket = mdwidth * (size - 1);
 	else
-		size /= 2;
+		maxpacket = mdwidth * ((size - 1) - 1) - mdwidth;
 
+	/* Functionally, space for one max packet is sufficient */
+	size = min_t(int, maxpacket, 1024);
 	usb_ep_set_maxpacket_limit(&dep->endpoint, size);
 
 	dep->endpoint.max_streams = 16;
-- 
GitLab


From 7ddda2614d62ef7fdef7fd85f5151cdf665b22d8 Mon Sep 17 00:00:00 2001
From: Stephan Gerhold <stephan@gerhold.net>
Date: Sat, 28 May 2022 19:09:13 +0200
Subject: [PATCH 0427/1731] usb: dwc3: pci: Restore line lost in merge conflict
 resolution

Commit 582ab24e096f ("usb: dwc3: pci: Set "linux,phy_charger_detect"
property on some Bay Trail boards") added a new swnode similar to the
existing ones for boards where the PHY handles charger detection.

Unfortunately, the "linux,sysdev_is_parent" property got lost in the
merge conflict resolution of commit ca9400ef7f67 ("Merge 5.17-rc6 into
usb-next"). Now dwc3_pci_intel_phy_charger_detect_properties is the
only swnode in dwc3-pci that is missing "linux,sysdev_is_parent".

It does not seem to cause any obvious functional issues, but it's
certainly unintended so restore the line to make the properties
consistent again.

Fixes: ca9400ef7f67 ("Merge 5.17-rc6 into usb-next")
Cc: stable@vger.kernel.org
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20220528170913.9240-1-stephan@gerhold.net
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/dwc3/dwc3-pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index ba51de7dd7605..6b018048fe2e1 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -127,6 +127,7 @@ static const struct property_entry dwc3_pci_intel_phy_charger_detect_properties[
 	PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
 	PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
 	PROPERTY_ENTRY_BOOL("linux,phy_charger_detect"),
+	PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 	{}
 };
 
-- 
GitLab


From 3755278f078460b021cd0384562977bf2039a57a Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Mon, 30 May 2022 12:54:12 +0400
Subject: [PATCH 0428/1731] usb: dwc2: Fix memory leak in dwc2_hcd_init

usb_create_hcd will alloc memory for hcd, and we should
call usb_put_hcd to free it when platform_get_resource()
fails to prevent memory leak.
goto error2 label instead error1 to fix this.

Fixes: 856e6e8e0f93 ("usb: dwc2: check return value after calling platform_get_resource()")
Cc: stable <stable@kernel.org>
Acked-by: Minas Harutyunyan <hminas@synopsys.com>
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Link: https://lore.kernel.org/r/20220530085413.44068-1-linmq006@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/dwc2/hcd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index f63a27d11fac8..3f107a06817d8 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -5190,7 +5190,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
 		retval = -EINVAL;
-		goto error1;
+		goto error2;
 	}
 	hcd->rsrc_start = res->start;
 	hcd->rsrc_len = resource_size(res);
-- 
GitLab


From 4757c9ade34178b351580133771f510b5ffcf9c8 Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Fri, 3 Jun 2022 18:02:44 +0400
Subject: [PATCH 0429/1731] usb: gadget: lpc32xx_udc: Fix refcount leak in
 lpc32xx_udc_probe

of_parse_phandle() returns a node pointer with refcount
incremented, we should use of_node_put() on it when not need anymore.
Add missing of_node_put() to avoid refcount leak.
of_node_put() will check NULL pointer.

Fixes: 24a28e428351 ("USB: gadget driver for LPC32xx")
Cc: stable <stable@kernel.org>
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Link: https://lore.kernel.org/r/20220603140246.64529-1-linmq006@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/gadget/udc/lpc32xx_udc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/gadget/udc/lpc32xx_udc.c b/drivers/usb/gadget/udc/lpc32xx_udc.c
index 6117ae8e7242b..cea10cdb83ae5 100644
--- a/drivers/usb/gadget/udc/lpc32xx_udc.c
+++ b/drivers/usb/gadget/udc/lpc32xx_udc.c
@@ -3016,6 +3016,7 @@ static int lpc32xx_udc_probe(struct platform_device *pdev)
 	}
 
 	udc->isp1301_i2c_client = isp1301_get_client(isp1301_node);
+	of_node_put(isp1301_node);
 	if (!udc->isp1301_i2c_client) {
 		return -EPROBE_DEFER;
 	}
-- 
GitLab


From b337af3a4d6147000b7ca6b3438bf5c820849b37 Mon Sep 17 00:00:00 2001
From: Marian Postevca <posteuca@mutex.one>
Date: Fri, 3 Jun 2022 18:34:59 +0300
Subject: [PATCH 0430/1731] usb: gadget: u_ether: fix regression in setting
 fixed MAC address

In systemd systems setting a fixed MAC address through
the "dev_addr" module argument fails systematically.
When checking the MAC address after the interface is created
it always has the same but different MAC address to the one
supplied as argument.

This is partially caused by systemd which by default will
set an internally generated permanent MAC address for interfaces
that are marked as having a randomly generated address.

Commit 890d5b40908bfd1a ("usb: gadget: u_ether: fix race in
setting MAC address in setup phase") didn't take into account
the fact that the interface must be marked as having a set
MAC address when it's set as module argument.

Fixed by marking the interface with NET_ADDR_SET when
the "dev_addr" module argument is supplied.

Fixes: 890d5b40908bfd1a ("usb: gadget: u_ether: fix race in setting MAC address in setup phase")
Cc: stable@vger.kernel.org
Signed-off-by: Marian Postevca <posteuca@mutex.one>
Link: https://lore.kernel.org/r/20220603153459.32722-1-posteuca@mutex.one
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/gadget/function/u_ether.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/gadget/function/u_ether.c b/drivers/usb/gadget/function/u_ether.c
index 6f5d45ef2e39a..f51694f29de92 100644
--- a/drivers/usb/gadget/function/u_ether.c
+++ b/drivers/usb/gadget/function/u_ether.c
@@ -775,9 +775,13 @@ struct eth_dev *gether_setup_name(struct usb_gadget *g,
 	dev->qmult = qmult;
 	snprintf(net->name, sizeof(net->name), "%s%%d", netname);
 
-	if (get_ether_addr(dev_addr, addr))
+	if (get_ether_addr(dev_addr, addr)) {
+		net->addr_assign_type = NET_ADDR_RANDOM;
 		dev_warn(&g->dev,
 			"using random %s ethernet address\n", "self");
+	} else {
+		net->addr_assign_type = NET_ADDR_SET;
+	}
 	eth_hw_addr_set(net, addr);
 	if (get_ether_addr(host_addr, dev->host_mac))
 		dev_warn(&g->dev,
@@ -844,6 +848,10 @@ struct net_device *gether_setup_name_default(const char *netname)
 
 	eth_random_addr(dev->dev_mac);
 	pr_warn("using random %s ethernet address\n", "self");
+
+	/* by default we always have a random MAC address */
+	net->addr_assign_type = NET_ADDR_RANDOM;
+
 	eth_random_addr(dev->host_mac);
 	pr_warn("using random %s ethernet address\n", "host");
 
@@ -871,7 +879,6 @@ int gether_register_netdev(struct net_device *net)
 	dev = netdev_priv(net);
 	g = dev->gadget;
 
-	net->addr_assign_type = NET_ADDR_RANDOM;
 	eth_hw_addr_set(net, dev->dev_mac);
 
 	status = register_netdev(net);
@@ -912,6 +919,7 @@ int gether_set_dev_addr(struct net_device *net, const char *dev_addr)
 	if (get_ether_addr(dev_addr, new_addr))
 		return -EINVAL;
 	memcpy(dev->dev_mac, new_addr, ETH_ALEN);
+	net->addr_assign_type = NET_ADDR_SET;
 	return 0;
 }
 EXPORT_SYMBOL_GPL(gether_set_dev_addr);
-- 
GitLab


From 5c7578c39c3fffe85b7d15ca1cf8cf7ac38ec0c1 Mon Sep 17 00:00:00 2001
From: Jing Leng <jleng@ambarella.com>
Date: Thu, 9 Jun 2022 10:11:34 +0800
Subject: [PATCH 0431/1731] usb: cdnsp: Fixed setting last_trb incorrectly

When ZLP occurs in bulk transmission, currently cdnsp will set last_trb
for the last two TRBs, it will trigger an error "ERROR Transfer event TRB
DMA ptr not part of current TD ...".

Fixes: e913aada0683 ("usb: cdnsp: Fixed issue with ZLP")
Cc: stable <stable@kernel.org>
Acked-by: Pawel Laszczak <pawell@cadence.com>
Signed-off-by: Jing Leng <jleng@ambarella.com>
Link: https://lore.kernel.org/r/20220609021134.1606-1-3090101217@zju.edu.cn
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/cdns3/cdnsp-ring.c | 19 +++++++++++--------
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/usb/cdns3/cdnsp-ring.c b/drivers/usb/cdns3/cdnsp-ring.c
index e45c3d6e1536c..794e413800ae8 100644
--- a/drivers/usb/cdns3/cdnsp-ring.c
+++ b/drivers/usb/cdns3/cdnsp-ring.c
@@ -1941,13 +1941,16 @@ int cdnsp_queue_bulk_tx(struct cdnsp_device *pdev, struct cdnsp_request *preq)
 		}
 
 		if (enqd_len + trb_buff_len >= full_len) {
-			if (need_zero_pkt)
-				zero_len_trb = !zero_len_trb;
-
-			field &= ~TRB_CHAIN;
-			field |= TRB_IOC;
-			more_trbs_coming = false;
-			preq->td.last_trb = ring->enqueue;
+			if (need_zero_pkt && !zero_len_trb) {
+				zero_len_trb = true;
+			} else {
+				zero_len_trb = false;
+				field &= ~TRB_CHAIN;
+				field |= TRB_IOC;
+				more_trbs_coming = false;
+				need_zero_pkt = false;
+				preq->td.last_trb = ring->enqueue;
+			}
 		}
 
 		/* Only set interrupt on short packet for OUT endpoints. */
@@ -1962,7 +1965,7 @@ int cdnsp_queue_bulk_tx(struct cdnsp_device *pdev, struct cdnsp_request *preq)
 		length_field = TRB_LEN(trb_buff_len) | TRB_TD_SIZE(remainder) |
 			TRB_INTR_TARGET(0);
 
-		cdnsp_queue_trb(pdev, ring, more_trbs_coming | zero_len_trb,
+		cdnsp_queue_trb(pdev, ring, more_trbs_coming,
 				lower_32_bits(send_addr),
 				upper_32_bits(send_addr),
 				length_field,
-- 
GitLab


From 8bd6b8c4b1009d7d2662138d6bdc6fe58a9274c5 Mon Sep 17 00:00:00 2001
From: Stephen Rothwell <sfr@canb.auug.org.au>
Date: Tue, 26 Apr 2022 15:27:39 +1000
Subject: [PATCH 0432/1731] USB: fixup for merge issue with "usb: dwc3: Don't
 switch OTG -> peripheral if extcon is present"

Today's linux-next merge of the extcon tree got a conflict in:

  drivers/usb/dwc3/drd.c

between commit:

  0f0101719138 ("usb: dwc3: Don't switch OTG -> peripheral if extcon is present")

from the usb tree and commit:

  88490c7f43c4 ("extcon: Fix extcon_get_extcon_dev() error handling")

from the extcon tree.

I fixed it up (the former moved the code modified by the latter, so I
used the former version of this files and added the following merge fix
patch) and can carry the fix as necessary.

Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Link: https://lore.kernel.org/r/20220426152739.62f6836e@canb.auug.org.au
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/dwc3/core.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index e027c0420dc30..573421984948a 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1644,13 +1644,8 @@ static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
 	 * This device property is for kernel internal use only and
 	 * is expected to be set by the glue code.
 	 */
-	if (device_property_read_string(dev, "linux,extcon-name", &name) == 0) {
-		edev = extcon_get_extcon_dev(name);
-		if (!edev)
-			return ERR_PTR(-EPROBE_DEFER);
-
-		return edev;
-	}
+	if (device_property_read_string(dev, "linux,extcon-name", &name) == 0)
+		return extcon_get_extcon_dev(name);
 
 	/*
 	 * Try to get an extcon device from the USB PHY controller's "port"
-- 
GitLab


From 81b0d0e4f811553cbe2d58c8a495c124fb626432 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
Date: Fri, 3 Jun 2022 12:43:50 +0200
Subject: [PATCH 0433/1731] drm/ttm: fix missing NULL check in
 ttm_device_swapout
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Resources about to be destructed are not tied to BOs any more.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Fixes: 6a9b02899402 ("drm/ttm: move the LRU into resource handling v4")
Link: https://patchwork.freedesktop.org/patch/msgid/20220603104604.456991-1-christian.koenig@amd.com
---
 drivers/gpu/drm/ttm/ttm_device.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c
index a0562ab386f51..e7147e3046378 100644
--- a/drivers/gpu/drm/ttm/ttm_device.c
+++ b/drivers/gpu/drm/ttm/ttm_device.c
@@ -156,8 +156,12 @@ int ttm_device_swapout(struct ttm_device *bdev, struct ttm_operation_ctx *ctx,
 
 		ttm_resource_manager_for_each_res(man, &cursor, res) {
 			struct ttm_buffer_object *bo = res->bo;
-			uint32_t num_pages = PFN_UP(bo->base.size);
+			uint32_t num_pages;
 
+			if (!bo)
+				continue;
+
+			num_pages = PFN_UP(bo->base.size);
 			ret = ttm_bo_swapout(bo, ctx, gfp_flags);
 			/* ttm_bo_swapout has dropped the lru_lock */
 			if (!ret)
-- 
GitLab


From e74024b2eccbb784824a0f9feaeaaa3b47514b79 Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Mon, 23 May 2022 18:50:52 +0300
Subject: [PATCH 0434/1731] tty: n_gsm: Debug output allocation must use
 GFP_ATOMIC

Dan Carpenter <dan.carpenter@oracle.com> reported the following Smatch
warning:

drivers/tty/n_gsm.c:720 gsm_data_kick()
warn: sleeping in atomic context

This is because gsm_control_message() is holding a spin lock so
gsm_hex_dump_bytes() needs to use GFP_ATOMIC instead of GFP_KERNEL.

Fixes: 925ea0fa5277 ("tty: n_gsm: Fix packet data hex dump output")
Cc: stable <stable@kernel.org>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20220523155052.57129-1-tony@atomide.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/tty/n_gsm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/n_gsm.c b/drivers/tty/n_gsm.c
index 137eebdcfda91..fd4d24f61c46b 100644
--- a/drivers/tty/n_gsm.c
+++ b/drivers/tty/n_gsm.c
@@ -455,7 +455,7 @@ static void gsm_hex_dump_bytes(const char *fname, const u8 *data,
 		return;
 	}
 
-	prefix = kasprintf(GFP_KERNEL, "%s: ", fname);
+	prefix = kasprintf(GFP_ATOMIC, "%s: ", fname);
 	if (!prefix)
 		return;
 	print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 16, 1, data, len,
-- 
GitLab


From cfab87c2c2715763dc7e43d9968bdaa01cde4bc3 Mon Sep 17 00:00:00 2001
From: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>
Date: Wed, 8 Jun 2022 00:22:44 +0530
Subject: [PATCH 0435/1731] serial: core: Introduce callback for start_rx and
 do stop_rx in suspend only if this callback implementation is present.

In suspend sequence there is a need to perform stop_rx during suspend
sequence to prevent any asynchronous data over rx line. However this
can cause problem to drivers which dont do re-start_rx during set_termios.

Add new callback start_rx and perform stop_rx only when implementation of
start_rx is present. Also add call to start_rx in resume sequence so that
drivers who come across this problem can make use of this framework.

Fixes: c9d2325cdb92 ("serial: core: Do stop_rx in suspend path for console if console_suspend is disabled")
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>
Link: https://lore.kernel.org/r/1654627965-1461-2-git-send-email-quic_vnivarth@quicinc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/tty/serial/serial_core.c | 9 ++++++---
 include/linux/serial_core.h      | 1 +
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
index 9a85b41caa0a4..338ebadfd44b8 100644
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
@@ -2214,11 +2214,12 @@ int uart_suspend_port(struct uart_driver *drv, struct uart_port *uport)
 	/*
 	 * Nothing to do if the console is not suspending
 	 * except stop_rx to prevent any asynchronous data
-	 * over RX line. Re-start_rx, when required, is
-	 * done by set_termios in resume sequence
+	 * over RX line. However ensure that we will be
+	 * able to Re-start_rx later.
 	 */
 	if (!console_suspend_enabled && uart_console(uport)) {
-		uport->ops->stop_rx(uport);
+		if (uport->ops->start_rx)
+			uport->ops->stop_rx(uport);
 		goto unlock;
 	}
 
@@ -2310,6 +2311,8 @@ int uart_resume_port(struct uart_driver *drv, struct uart_port *uport)
 		if (console_suspend_enabled)
 			uart_change_pm(state, UART_PM_STATE_ON);
 		uport->ops->set_termios(uport, &termios, NULL);
+		if (!console_suspend_enabled && uport->ops->start_rx)
+			uport->ops->start_rx(uport);
 		if (console_suspend_enabled)
 			console_start(uport->cons);
 	}
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index cbd5070bc87f4..657a0fc68a3fb 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -45,6 +45,7 @@ struct uart_ops {
 	void		(*unthrottle)(struct uart_port *);
 	void		(*send_xchar)(struct uart_port *, char ch);
 	void		(*stop_rx)(struct uart_port *);
+	void		(*start_rx)(struct uart_port *);
 	void		(*enable_ms)(struct uart_port *);
 	void		(*break_ctl)(struct uart_port *, int ctl);
 	int		(*startup)(struct uart_port *);
-- 
GitLab


From 654a8d6c93e77ecff2256ca3ab2cd98967821f0a Mon Sep 17 00:00:00 2001
From: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>
Date: Wed, 8 Jun 2022 00:22:45 +0530
Subject: [PATCH 0436/1731] tty: serial: qcom-geni-serial: Implement start_rx
 callback

In suspend sequence stop_rx will be performed only if implementation for
start_rx callback is present.

Set qcom_geni_serial_start_rx as callback for start_rx so that stop_rx is
performed.

Fixes: c9d2325cdb92 ("serial: core: Do stop_rx in suspend path for console if console_suspend is disabled")
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>
Link: https://lore.kernel.org/r/1654627965-1461-3-git-send-email-quic_vnivarth@quicinc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/tty/serial/qcom_geni_serial.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c
index 4733a233bd0c5..f8f950641ad9f 100644
--- a/drivers/tty/serial/qcom_geni_serial.c
+++ b/drivers/tty/serial/qcom_geni_serial.c
@@ -1306,6 +1306,7 @@ static const struct uart_ops qcom_geni_console_pops = {
 	.stop_tx = qcom_geni_serial_stop_tx,
 	.start_tx = qcom_geni_serial_start_tx,
 	.stop_rx = qcom_geni_serial_stop_rx,
+	.start_rx = qcom_geni_serial_start_rx,
 	.set_termios = qcom_geni_serial_set_termios,
 	.startup = qcom_geni_serial_startup,
 	.request_port = qcom_geni_serial_request_port,
-- 
GitLab


From 499e13aac6c762e1e828172b0f0f5275651d6512 Mon Sep 17 00:00:00 2001
From: Vincent Whitchurch <vincent.whitchurch@axis.com>
Date: Thu, 9 Jun 2022 16:17:04 +0200
Subject: [PATCH 0437/1731] tty: goldfish: Fix free_irq() on remove

Pass the correct dev_id to free_irq() to fix this splat when the driver
is unbound:

 WARNING: CPU: 0 PID: 30 at kernel/irq/manage.c:1895 free_irq
 Trying to free already-free IRQ 65
 Call Trace:
  warn_slowpath_fmt
  free_irq
  goldfish_tty_remove
  platform_remove
  device_remove
  device_release_driver_internal
  device_driver_detach
  unbind_store
  drv_attr_store
  ...

Fixes: 465893e18878e119 ("tty: goldfish: support platform_device with id -1")
Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com>
Link: https://lore.kernel.org/r/20220609141704.1080024-1-vincent.whitchurch@axis.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/tty/goldfish.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/goldfish.c b/drivers/tty/goldfish.c
index c7968aecd8702..d02de3f0326fb 100644
--- a/drivers/tty/goldfish.c
+++ b/drivers/tty/goldfish.c
@@ -426,7 +426,7 @@ static int goldfish_tty_remove(struct platform_device *pdev)
 	tty_unregister_device(goldfish_tty_driver, qtty->console.index);
 	iounmap(qtty->base);
 	qtty->base = NULL;
-	free_irq(qtty->irq, pdev);
+	free_irq(qtty->irq, qtty);
 	tty_port_destroy(&qtty->port);
 	goldfish_tty_current_line_count--;
 	if (goldfish_tty_current_line_count == 0)
-- 
GitLab


From be03b0651ffd8bab69dfd574c6818b446c0753ce Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= <ilpo.jarvinen@linux.intel.com>
Date: Fri, 20 May 2022 13:35:41 +0300
Subject: [PATCH 0438/1731] serial: 8250: Store to lsr_save_flags after lsr
 read
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Not all LSR register flags are preserved across reads. Therefore, LSR
readers must store the non-preserved bits into lsr_save_flags.

This fix was initially mixed into feature commit f6f586102add ("serial:
8250: Handle UART without interrupt on TEMT using em485"). However,
that feature change had a flaw and it was reverted to make room for
simpler approach providing the same feature. The embedded fix got
reverted with the feature change.

Re-add the lsr_save_flags fix and properly mark it's a fix.

Link: https://lore.kernel.org/all/1d6c31d-d194-9e6a-ddf9-5f29af829f3@linux.intel.com/T/#m1737eef986bd20cf19593e344cebd7b0244945fc
Fixes: e490c9144cfa ("tty: Add software emulated RS485 support for 8250")
Cc: stable <stable@kernel.org>
Acked-by: Uwe Kleine-König <u.kleine-koenig@penugtronix.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Link: https://lore.kernel.org/r/f4d774be-1437-a550-8334-19d8722ab98c@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/tty/serial/8250/8250_port.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
index 78b6dedc43e6b..8f32fe9e149e9 100644
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -1517,6 +1517,8 @@ static inline void __stop_tx(struct uart_8250_port *p)
 		unsigned char lsr = serial_in(p, UART_LSR);
 		u64 stop_delay = 0;
 
+		p->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
+
 		if (!(lsr & UART_LSR_THRE))
 			return;
 		/*
-- 
GitLab


From 802dcafc420af536fcde1b44ac51ca211f4ec673 Mon Sep 17 00:00:00 2001
From: Mathias Nyman <mathias.nyman@linux.intel.com>
Date: Fri, 10 Jun 2022 14:53:38 +0300
Subject: [PATCH 0439/1731] xhci: Fix null pointer dereference in resume if
 xhci has only one roothub

In the re-init path xhci_resume() passes 'hcd->primary_hcd' to hci_init(),
however this field isn't initialized by __usb_create_hcd() for a HCD
without secondary controller.

xhci_resume() is called once per xHC device, not per hcd, so the extra
checking for primary hcd can be removed.

Fixes: e0fe986972f5 ("usb: host: xhci-plat: prepare operation w/o shared hcd")
Reported-by: Matthias Kaehlcke <mka@chromium.org>
Tested-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Link: https://lore.kernel.org/r/20220610115338.863152-2-mathias.nyman@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/host/xhci.c | 15 +++++----------
 1 file changed, 5 insertions(+), 10 deletions(-)

diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index f0ab631380165..9ac56e9ffc645 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -1107,7 +1107,6 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
 {
 	u32			command, temp = 0;
 	struct usb_hcd		*hcd = xhci_to_hcd(xhci);
-	struct usb_hcd		*secondary_hcd;
 	int			retval = 0;
 	bool			comp_timer_running = false;
 	bool			pending_portevent = false;
@@ -1214,23 +1213,19 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
 		 * first with the primary HCD, and then with the secondary HCD.
 		 * If we don't do the same, the host will never be started.
 		 */
-		if (!usb_hcd_is_primary_hcd(hcd))
-			secondary_hcd = hcd;
-		else
-			secondary_hcd = xhci->shared_hcd;
-
 		xhci_dbg(xhci, "Initialize the xhci_hcd\n");
-		retval = xhci_init(hcd->primary_hcd);
+		retval = xhci_init(hcd);
 		if (retval)
 			return retval;
 		comp_timer_running = true;
 
 		xhci_dbg(xhci, "Start the primary HCD\n");
-		retval = xhci_run(hcd->primary_hcd);
-		if (!retval && secondary_hcd) {
+		retval = xhci_run(hcd);
+		if (!retval && xhci->shared_hcd) {
 			xhci_dbg(xhci, "Start the secondary HCD\n");
-			retval = xhci_run(secondary_hcd);
+			retval = xhci_run(xhci->shared_hcd);
 		}
+
 		hcd->state = HC_STATE_SUSPENDED;
 		if (xhci->shared_hcd)
 			xhci->shared_hcd->state = HC_STATE_SUSPENDED;
-- 
GitLab


From fb1f16d74e263baa4ad11e31e28b68f144aa55ed Mon Sep 17 00:00:00 2001
From: Linyu Yuan <quic_linyyuan@quicinc.com>
Date: Fri, 10 Jun 2022 20:17:57 +0800
Subject: [PATCH 0440/1731] usb: gadget: f_fs: change ep->status safe in
 ffs_epfile_io()

If a task read/write data in blocking mode, it will wait the completion
in ffs_epfile_io(), if function unbind occurs, ffs_func_unbind() will
kfree ffs ep, once the task wake up, it still dereference the ffs ep to
obtain the request status.

Fix it by moving the request status to io_data which is stack-safe.

Cc: <stable@vger.kernel.org> # 5.15
Reported-by: Michael Wu <michael@allwinnertech.com>
Tested-by: Michael Wu <michael@allwinnertech.com>
Reviewed-by: John Keeping <john@metanate.com>
Signed-off-by: Linyu Yuan <quic_linyyuan@quicinc.com>
Link: https://lore.kernel.org/r/1654863478-26228-2-git-send-email-quic_linyyuan@quicinc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/gadget/function/f_fs.c | 34 +++++++++++++++++-------------
 1 file changed, 19 insertions(+), 15 deletions(-)

diff --git a/drivers/usb/gadget/function/f_fs.c b/drivers/usb/gadget/function/f_fs.c
index 4585ee3a444a8..e1fcd8bc80a14 100644
--- a/drivers/usb/gadget/function/f_fs.c
+++ b/drivers/usb/gadget/function/f_fs.c
@@ -122,8 +122,6 @@ struct ffs_ep {
 	struct usb_endpoint_descriptor	*descs[3];
 
 	u8				num;
-
-	int				status;	/* P: epfile->mutex */
 };
 
 struct ffs_epfile {
@@ -227,6 +225,9 @@ struct ffs_io_data {
 	bool use_sg;
 
 	struct ffs_data *ffs;
+
+	int status;
+	struct completion done;
 };
 
 struct ffs_desc_helper {
@@ -707,12 +708,15 @@ static const struct file_operations ffs_ep0_operations = {
 
 static void ffs_epfile_io_complete(struct usb_ep *_ep, struct usb_request *req)
 {
+	struct ffs_io_data *io_data = req->context;
+
 	ENTER();
-	if (req->context) {
-		struct ffs_ep *ep = _ep->driver_data;
-		ep->status = req->status ? req->status : req->actual;
-		complete(req->context);
-	}
+	if (req->status)
+		io_data->status = req->status;
+	else
+		io_data->status = req->actual;
+
+	complete(&io_data->done);
 }
 
 static ssize_t ffs_copy_to_iter(void *data, int data_len, struct iov_iter *iter)
@@ -1050,7 +1054,6 @@ static ssize_t ffs_epfile_io(struct file *file, struct ffs_io_data *io_data)
 		WARN(1, "%s: data_len == -EINVAL\n", __func__);
 		ret = -EINVAL;
 	} else if (!io_data->aio) {
-		DECLARE_COMPLETION_ONSTACK(done);
 		bool interrupted = false;
 
 		req = ep->req;
@@ -1066,7 +1069,8 @@ static ssize_t ffs_epfile_io(struct file *file, struct ffs_io_data *io_data)
 
 		io_data->buf = data;
 
-		req->context  = &done;
+		init_completion(&io_data->done);
+		req->context  = io_data;
 		req->complete = ffs_epfile_io_complete;
 
 		ret = usb_ep_queue(ep->ep, req, GFP_ATOMIC);
@@ -1075,7 +1079,7 @@ static ssize_t ffs_epfile_io(struct file *file, struct ffs_io_data *io_data)
 
 		spin_unlock_irq(&epfile->ffs->eps_lock);
 
-		if (wait_for_completion_interruptible(&done)) {
+		if (wait_for_completion_interruptible(&io_data->done)) {
 			/*
 			 * To avoid race condition with ffs_epfile_io_complete,
 			 * dequeue the request first then check
@@ -1083,17 +1087,17 @@ static ssize_t ffs_epfile_io(struct file *file, struct ffs_io_data *io_data)
 			 * condition with req->complete callback.
 			 */
 			usb_ep_dequeue(ep->ep, req);
-			wait_for_completion(&done);
-			interrupted = ep->status < 0;
+			wait_for_completion(&io_data->done);
+			interrupted = io_data->status < 0;
 		}
 
 		if (interrupted)
 			ret = -EINTR;
-		else if (io_data->read && ep->status > 0)
-			ret = __ffs_epfile_read_data(epfile, data, ep->status,
+		else if (io_data->read && io_data->status > 0)
+			ret = __ffs_epfile_read_data(epfile, data, io_data->status,
 						     &io_data->data);
 		else
-			ret = ep->status;
+			ret = io_data->status;
 		goto error_mutex;
 	} else if (!(req = usb_ep_alloc_request(ep->ep, GFP_ATOMIC))) {
 		ret = -ENOMEM;
-- 
GitLab


From 0698f0209d8032e8869525aeb68f65ee7fde12ad Mon Sep 17 00:00:00 2001
From: Linyu Yuan <quic_linyyuan@quicinc.com>
Date: Fri, 10 Jun 2022 20:17:58 +0800
Subject: [PATCH 0441/1731] usb: gadget: f_fs: change ep->ep safe in
 ffs_epfile_io()

In ffs_epfile_io(), when read/write data in blocking mode, it will wait
the completion in interruptible mode, if task receive a signal, it will
terminate the wait, at same time, if function unbind occurs,
ffs_func_unbind() will kfree all eps, ffs_epfile_io() still try to
dequeue request by dereferencing ep which may become invalid.

Fix it by add ep spinlock and will not dereference ep if it is not valid.

Cc: <stable@vger.kernel.org> # 5.15
Reported-by: Michael Wu <michael@allwinnertech.com>
Tested-by: Michael Wu <michael@allwinnertech.com>
Reviewed-by: John Keeping <john@metanate.com>
Signed-off-by: Linyu Yuan <quic_linyyuan@quicinc.com>
Link: https://lore.kernel.org/r/1654863478-26228-3-git-send-email-quic_linyyuan@quicinc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/gadget/function/f_fs.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/usb/gadget/function/f_fs.c b/drivers/usb/gadget/function/f_fs.c
index e1fcd8bc80a14..e0fa4b186ec6d 100644
--- a/drivers/usb/gadget/function/f_fs.c
+++ b/drivers/usb/gadget/function/f_fs.c
@@ -1080,6 +1080,11 @@ static ssize_t ffs_epfile_io(struct file *file, struct ffs_io_data *io_data)
 		spin_unlock_irq(&epfile->ffs->eps_lock);
 
 		if (wait_for_completion_interruptible(&io_data->done)) {
+			spin_lock_irq(&epfile->ffs->eps_lock);
+			if (epfile->ep != ep) {
+				ret = -ESHUTDOWN;
+				goto error_lock;
+			}
 			/*
 			 * To avoid race condition with ffs_epfile_io_complete,
 			 * dequeue the request first then check
@@ -1087,6 +1092,7 @@ static ssize_t ffs_epfile_io(struct file *file, struct ffs_io_data *io_data)
 			 * condition with req->complete callback.
 			 */
 			usb_ep_dequeue(ep->ep, req);
+			spin_unlock_irq(&epfile->ffs->eps_lock);
 			wait_for_completion(&io_data->done);
 			interrupted = io_data->status < 0;
 		}
-- 
GitLab


From 242439f7e279d86b3f73b5de724bc67b2f8aeb07 Mon Sep 17 00:00:00 2001
From: Ian Abbott <abbotti@mev.co.uk>
Date: Tue, 7 Jun 2022 18:18:19 +0100
Subject: [PATCH 0442/1731] comedi: vmk80xx: fix expression for tx buffer size

The expression for setting the size of the allocated bulk TX buffer
(`devpriv->usb_tx_buf`) is calling `usb_endpoint_maxp(devpriv->ep_rx)`,
which is using the wrong endpoint (should be `devpriv->ep_tx`).  Fix it.

Fixes: a23461c47482 ("comedi: vmk80xx: fix transfer-buffer overflow")
Cc: Johan Hovold <johan@kernel.org>
Cc: stable@vger.kernel.org # 4.9+
Reviewed-by: Johan Hovold <johan@kernel.org>
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Link: https://lore.kernel.org/r/20220607171819.4121-1-abbotti@mev.co.uk
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/comedi/drivers/vmk80xx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/comedi/drivers/vmk80xx.c b/drivers/comedi/drivers/vmk80xx.c
index 46023adc53958..4536ed43f65b2 100644
--- a/drivers/comedi/drivers/vmk80xx.c
+++ b/drivers/comedi/drivers/vmk80xx.c
@@ -684,7 +684,7 @@ static int vmk80xx_alloc_usb_buffers(struct comedi_device *dev)
 	if (!devpriv->usb_rx_buf)
 		return -ENOMEM;
 
-	size = max(usb_endpoint_maxp(devpriv->ep_rx), MIN_BUF_SIZE);
+	size = max(usb_endpoint_maxp(devpriv->ep_tx), MIN_BUF_SIZE);
 	devpriv->usb_tx_buf = kzalloc(size, GFP_KERNEL);
 	if (!devpriv->usb_tx_buf)
 		return -ENOMEM;
-- 
GitLab


From bd476c1306ea989d6d9eb65295572e98d93edeb6 Mon Sep 17 00:00:00 2001
From: Nathan Chancellor <nathan@kernel.org>
Date: Mon, 23 May 2022 08:05:22 -0700
Subject: [PATCH 0443/1731] misc: rtsx: Fix clang -Wsometimes-uninitialized in
 rts5261_init_from_hw()

Clang warns:

  drivers/misc/cardreader/rts5261.c:406:13: error: variable 'setting_reg2' is used uninitialized whenever 'if' condition is false [-Werror,-Wsometimes-uninitialized]
          } else if (efuse_valid == 0) {
                     ^~~~~~~~~~~~~~~~
  drivers/misc/cardreader/rts5261.c:412:30: note: uninitialized use occurs here
          pci_read_config_dword(pdev, setting_reg2, &lval2);
                                      ^~~~~~~~~~~~

efuse_valid == 1 is not a valid value so just return early from the
function to avoid using setting_reg2 uninitialized.

Fixes: b1c5f3085149 ("misc: rtsx: add rts5261 efuse function")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Tom Rix <trix@redhat.com>
Suggested-by: Ricky WU <ricky_wu@realtek.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Link: https://lore.kernel.org/r/20220523150521.2947108-1-nathan@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/misc/cardreader/rts5261.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/misc/cardreader/rts5261.c b/drivers/misc/cardreader/rts5261.c
index 749cc5a46d138..b1e76030cafda 100644
--- a/drivers/misc/cardreader/rts5261.c
+++ b/drivers/misc/cardreader/rts5261.c
@@ -407,6 +407,8 @@ static void rts5261_init_from_hw(struct rtsx_pcr *pcr)
 		// default
 		setting_reg1 = PCR_SETTING_REG1;
 		setting_reg2 = PCR_SETTING_REG2;
+	} else {
+		return;
 	}
 
 	pci_read_config_dword(pdev, setting_reg2, &lval2);
-- 
GitLab


From 6497e7776441e0567c02b9c12b133d2ba51918df Mon Sep 17 00:00:00 2001
From: Shreenidhi Shedi <sshedi@vmware.com>
Date: Fri, 3 Jun 2022 18:30:40 +0530
Subject: [PATCH 0444/1731] char: lp: remove redundant initialization of err

err is getting assigned with an appropriate value before returning,
hence this initialization is unnecessary.

Signed-off-by: Shreenidhi Shedi <sshedi@vmware.com>
Link: https://lore.kernel.org/r/20220603130040.601673-2-sshedi@vmware.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/char/lp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/char/lp.c b/drivers/char/lp.c
index 0e22e3b0a04e7..38aad99ebb615 100644
--- a/drivers/char/lp.c
+++ b/drivers/char/lp.c
@@ -1019,7 +1019,7 @@ static struct parport_driver lp_driver = {
 
 static int __init lp_init(void)
 {
-	int i, err = 0;
+	int i, err;
 
 	if (parport_nr[0] == LP_PARPORT_OFF)
 		return 0;
-- 
GitLab


From 1c245358ce0b13669f6d1625f7a4e05c41f28980 Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Wed, 1 Jun 2022 16:30:26 +0400
Subject: [PATCH 0445/1731] misc: atmel-ssc: Fix IRQ check in ssc_probe

platform_get_irq() returns negative error number instead 0 on failure.
And the doc of platform_get_irq() provides a usage example:

    int irq = platform_get_irq(pdev, 0);
    if (irq < 0)
        return irq;

Fix the check of return value to catch errors correctly.

Fixes: eb1f2930609b ("Driver for the Atmel on-chip SSC on AT32AP and AT91")
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Link: https://lore.kernel.org/r/20220601123026.7119-1-linmq006@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/misc/atmel-ssc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/misc/atmel-ssc.c b/drivers/misc/atmel-ssc.c
index d6cd5537126c6..69f9b0336410d 100644
--- a/drivers/misc/atmel-ssc.c
+++ b/drivers/misc/atmel-ssc.c
@@ -232,9 +232,9 @@ static int ssc_probe(struct platform_device *pdev)
 	clk_disable_unprepare(ssc->clk);
 
 	ssc->irq = platform_get_irq(pdev, 0);
-	if (!ssc->irq) {
+	if (ssc->irq < 0) {
 		dev_dbg(&pdev->dev, "could not get irq\n");
-		return -ENXIO;
+		return ssc->irq;
 	}
 
 	mutex_lock(&user_lock);
-- 
GitLab


From cd756dafd86ee3a4969906086f3c2537e0c6d9d0 Mon Sep 17 00:00:00 2001
From: Peter Robinson <pbrobinson@gmail.com>
Date: Mon, 6 Jun 2022 14:22:00 +0100
Subject: [PATCH 0446/1731] staging: Also remove the Unisys visorbus.h

The commit that removed the Unisys s-Par and visorbus drivers
left around the include/linux/visorbus.h file mentioned in the
MAINTAINERS entry, we can also remove that too.

Fixes: e5f45b011e4a ("staging: Remove the drivers for the Unisys s-Par")
Reviewed-by: Fabio M. De Francesco <fmdefrancesco@gmail.com>
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Link: https://lore.kernel.org/r/20220606132200.2873243-1-pbrobinson@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 include/linux/visorbus.h | 344 ---------------------------------------
 1 file changed, 344 deletions(-)
 delete mode 100644 include/linux/visorbus.h

diff --git a/include/linux/visorbus.h b/include/linux/visorbus.h
deleted file mode 100644
index 0d8bd6769b13d..0000000000000
--- a/include/linux/visorbus.h
+++ /dev/null
@@ -1,344 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2010 - 2013 UNISYS CORPORATION
- * All rights reserved.
- */
-
-/*
- *  This header file is to be included by other kernel mode components that
- *  implement a particular kind of visor_device.  Each of these other kernel
- *  mode components is called a visor device driver.  Refer to visortemplate
- *  for a minimal sample visor device driver.
- *
- *  There should be nothing in this file that is private to the visorbus
- *  bus implementation itself.
- */
-
-#ifndef __VISORBUS_H__
-#define __VISORBUS_H__
-
-#include <linux/device.h>
-
-#define VISOR_CHANNEL_SIGNATURE ('L' << 24 | 'N' << 16 | 'C' << 8 | 'E')
-
-/*
- * enum channel_serverstate
- * @CHANNELSRV_UNINITIALIZED: Channel is in an undefined state.
- * @CHANNELSRV_READY:	      Channel has been initialized by server.
- */
-enum channel_serverstate {
-	CHANNELSRV_UNINITIALIZED = 0,
-	CHANNELSRV_READY = 1
-};
-
-/*
- * enum channel_clientstate
- * @CHANNELCLI_DETACHED:
- * @CHANNELCLI_DISABLED:  Client can see channel but is NOT allowed to use it
- *			  unless given TBD* explicit request
- *			  (should actually be < DETACHED).
- * @CHANNELCLI_ATTACHING: Legacy EFI client request for EFI server to attach.
- * @CHANNELCLI_ATTACHED:  Idle, but client may want to use channel any time.
- * @CHANNELCLI_BUSY:	  Client either wants to use or is using channel.
- * @CHANNELCLI_OWNED:	  "No worries" state - client can access channel
- *			  anytime.
- */
-enum channel_clientstate {
-	CHANNELCLI_DETACHED = 0,
-	CHANNELCLI_DISABLED = 1,
-	CHANNELCLI_ATTACHING = 2,
-	CHANNELCLI_ATTACHED = 3,
-	CHANNELCLI_BUSY = 4,
-	CHANNELCLI_OWNED = 5
-};
-
-/*
- * Values for VISOR_CHANNEL_PROTOCOL.Features: This define exists so that
- * a guest can look at the FeatureFlags in the io channel, and configure the
- * driver to use interrupts or not based on this setting. All feature bits for
- * all channels should be defined here. The io channel feature bits are defined
- * below.
- */
-#define VISOR_DRIVER_ENABLES_INTS (0x1ULL << 1)
-#define VISOR_CHANNEL_IS_POLLING (0x1ULL << 3)
-#define VISOR_IOVM_OK_DRIVER_DISABLING_INTS (0x1ULL << 4)
-#define VISOR_DRIVER_DISABLES_INTS (0x1ULL << 5)
-#define VISOR_DRIVER_ENHANCED_RCVBUF_CHECKING (0x1ULL << 6)
-
-/*
- * struct channel_header - Common Channel Header
- * @signature:	       Signature.
- * @legacy_state:      DEPRECATED - being replaced by.
- * @header_size:       sizeof(struct channel_header).
- * @size:	       Total size of this channel in bytes.
- * @features:	       Flags to modify behavior.
- * @chtype:	       Channel type: data, bus, control, etc..
- * @partition_handle:  ID of guest partition.
- * @handle:	       Device number of this channel in client.
- * @ch_space_offset:   Offset in bytes to channel specific area.
- * @version_id:	       Struct channel_header Version ID.
- * @partition_index:   Index of guest partition.
- * @zone_uuid:	       Guid of Channel's zone.
- * @cli_str_offset:    Offset from channel header to null-terminated
- *		       ClientString (0 if ClientString not present).
- * @cli_state_boot:    CHANNEL_CLIENTSTATE of pre-boot EFI client of this
- *		       channel.
- * @cmd_state_cli:     CHANNEL_COMMANDSTATE (overloaded in Windows drivers, see
- *		       ServerStateUp, ServerStateDown, etc).
- * @cli_state_os:      CHANNEL_CLIENTSTATE of Guest OS client of this channel.
- * @ch_characteristic: CHANNEL_CHARACTERISTIC_<xxx>.
- * @cmd_state_srv:     CHANNEL_COMMANDSTATE (overloaded in Windows drivers, see
- *		       ServerStateUp, ServerStateDown, etc).
- * @srv_state:	       CHANNEL_SERVERSTATE.
- * @cli_error_boot:    Bits to indicate err states for boot clients, so err
- *		       messages can be throttled.
- * @cli_error_os:      Bits to indicate err states for OS clients, so err
- *		       messages can be throttled.
- * @filler:	       Pad out to 128 byte cacheline.
- * @recover_channel:   Please add all new single-byte values below here.
- */
-struct channel_header {
-	u64 signature;
-	u32 legacy_state;
-	/* SrvState, CliStateBoot, and CliStateOS below */
-	u32 header_size;
-	u64 size;
-	u64 features;
-	guid_t chtype;
-	u64 partition_handle;
-	u64 handle;
-	u64 ch_space_offset;
-	u32 version_id;
-	u32 partition_index;
-	guid_t zone_guid;
-	u32 cli_str_offset;
-	u32 cli_state_boot;
-	u32 cmd_state_cli;
-	u32 cli_state_os;
-	u32 ch_characteristic;
-	u32 cmd_state_srv;
-	u32 srv_state;
-	u8 cli_error_boot;
-	u8 cli_error_os;
-	u8 filler[1];
-	u8 recover_channel;
-} __packed;
-
-#define VISOR_CHANNEL_ENABLE_INTS (0x1ULL << 0)
-
-/*
- * struct signal_queue_header - Subheader for the Signal Type variation of the
- *                              Common Channel.
- * @version:	      SIGNAL_QUEUE_HEADER Version ID.
- * @chtype:	      Queue type: storage, network.
- * @size:	      Total size of this queue in bytes.
- * @sig_base_offset:  Offset to signal queue area.
- * @features:	      Flags to modify behavior.
- * @num_sent:	      Total # of signals placed in this queue.
- * @num_overflows:    Total # of inserts failed due to full queue.
- * @signal_size:      Total size of a signal for this queue.
- * @max_slots:        Max # of slots in queue, 1 slot is always empty.
- * @max_signals:      Max # of signals in queue (MaxSignalSlots-1).
- * @head:	      Queue head signal #.
- * @num_received:     Total # of signals removed from this queue.
- * @tail:	      Queue tail signal.
- * @reserved1:	      Reserved field.
- * @reserved2:	      Reserved field.
- * @client_queue:
- * @num_irq_received: Total # of Interrupts received. This is incremented by the
- *		      ISR in the guest windows driver.
- * @num_empty:	      Number of times that visor_signal_remove is called and
- *		      returned Empty Status.
- * @errorflags:	      Error bits set during SignalReinit to denote trouble with
- *		      client's fields.
- * @filler:	      Pad out to 64 byte cacheline.
- */
-struct signal_queue_header {
-	/* 1st cache line */
-	u32 version;
-	u32 chtype;
-	u64 size;
-	u64 sig_base_offset;
-	u64 features;
-	u64 num_sent;
-	u64 num_overflows;
-	u32 signal_size;
-	u32 max_slots;
-	u32 max_signals;
-	u32 head;
-	/* 2nd cache line */
-	u64 num_received;
-	u32 tail;
-	u32 reserved1;
-	u64 reserved2;
-	u64 client_queue;
-	u64 num_irq_received;
-	u64 num_empty;
-	u32 errorflags;
-	u8 filler[12];
-} __packed;
-
-/* VISORCHANNEL Guids */
-/* {414815ed-c58c-11da-95a9-00e08161165f} */
-#define VISOR_VHBA_CHANNEL_GUID \
-	GUID_INIT(0x414815ed, 0xc58c, 0x11da, \
-		  0x95, 0xa9, 0x0, 0xe0, 0x81, 0x61, 0x16, 0x5f)
-#define VISOR_VHBA_CHANNEL_GUID_STR \
-	"414815ed-c58c-11da-95a9-00e08161165f"
-struct visorchipset_state {
-	u32 created:1;
-	u32 attached:1;
-	u32 configured:1;
-	u32 running:1;
-	/* Remaining bits in this 32-bit word are reserved. */
-};
-
-/**
- * struct visor_device - A device type for things "plugged" into the visorbus
- *                       bus
- * @visorchannel:		Points to the channel that the device is
- *				associated with.
- * @channel_type_guid:		Identifies the channel type to the bus driver.
- * @device:			Device struct meant for use by the bus driver
- *				only.
- * @list_all:			Used by the bus driver to enumerate devices.
- * @timer:		        Timer fired periodically to do interrupt-type
- *				activity.
- * @being_removed:		Indicates that the device is being removed from
- *				the bus. Private bus driver use only.
- * @visordriver_callback_lock:	Used by the bus driver to lock when adding and
- *				removing devices.
- * @pausing:			Indicates that a change towards a paused state.
- *				is in progress. Only modified by the bus driver.
- * @resuming:			Indicates that a change towards a running state
- *				is in progress. Only modified by the bus driver.
- * @chipset_bus_no:		Private field used by the bus driver.
- * @chipset_dev_no:		Private field used the bus driver.
- * @state:			Used to indicate the current state of the
- *				device.
- * @inst:			Unique GUID for this instance of the device.
- * @name:			Name of the device.
- * @pending_msg_hdr:		For private use by bus driver to respond to
- *				hypervisor requests.
- * @vbus_hdr_info:		A pointer to header info. Private use by bus
- *				driver.
- * @partition_guid:		Indicates client partion id. This should be the
- *				same across all visor_devices in the current
- *				guest. Private use by bus driver only.
- */
-struct visor_device {
-	struct visorchannel *visorchannel;
-	guid_t channel_type_guid;
-	/* These fields are for private use by the bus driver only. */
-	struct device device;
-	struct list_head list_all;
-	struct timer_list timer;
-	bool timer_active;
-	bool being_removed;
-	struct mutex visordriver_callback_lock; /* synchronize probe/remove */
-	bool pausing;
-	bool resuming;
-	u32 chipset_bus_no;
-	u32 chipset_dev_no;
-	struct visorchipset_state state;
-	guid_t inst;
-	u8 *name;
-	struct controlvm_message_header *pending_msg_hdr;
-	void *vbus_hdr_info;
-	guid_t partition_guid;
-	struct dentry *debugfs_dir;
-	struct dentry *debugfs_bus_info;
-};
-
-#define to_visor_device(x) container_of(x, struct visor_device, device)
-
-typedef void (*visorbus_state_complete_func) (struct visor_device *dev,
-					      int status);
-
-/*
- * This struct describes a specific visor channel, by providing its GUID, name,
- * and sizes.
- */
-struct visor_channeltype_descriptor {
-	const guid_t guid;
-	const char *name;
-	u64 min_bytes;
-	u32 version;
-};
-
-/**
- * struct visor_driver - Information provided by each visor driver when it
- *                       registers with the visorbus driver
- * @name:		Name of the visor driver.
- * @owner:		The module owner.
- * @channel_types:	Types of channels handled by this driver, ending with
- *			a zero GUID. Our specialized BUS.match() method knows
- *			about this list, and uses it to determine whether this
- *			driver will in fact handle a new device that it has
- *			detected.
- * @probe:		Called when a new device comes online, by our probe()
- *			function specified by driver.probe() (triggered
- *			ultimately by some call to driver_register(),
- *			bus_add_driver(), or driver_attach()).
- * @remove:		Called when a new device is removed, by our remove()
- *			function specified by driver.remove() (triggered
- *			ultimately by some call to device_release_driver()).
- * @channel_interrupt:	Called periodically, whenever there is a possiblity
- *			that "something interesting" may have happened to the
- *			channel.
- * @pause:		Called to initiate a change of the device's state.  If
- *			the return valu`e is < 0, there was an error and the
- *			state transition will NOT occur.  If the return value
- *			is >= 0, then the state transition was INITIATED
- *			successfully, and complete_func() will be called (or
- *			was just called) with the final status when either the
- *			state transition fails or completes successfully.
- * @resume:		Behaves similar to pause.
- * @driver:		Private reference to the device driver. For use by bus
- *			driver only.
- */
-struct visor_driver {
-	const char *name;
-	struct module *owner;
-	struct visor_channeltype_descriptor *channel_types;
-	int (*probe)(struct visor_device *dev);
-	void (*remove)(struct visor_device *dev);
-	void (*channel_interrupt)(struct visor_device *dev);
-	int (*pause)(struct visor_device *dev,
-		     visorbus_state_complete_func complete_func);
-	int (*resume)(struct visor_device *dev,
-		      visorbus_state_complete_func complete_func);
-
-	/* These fields are for private use by the bus driver only. */
-	struct device_driver driver;
-};
-
-#define to_visor_driver(x) (container_of(x, struct visor_driver, driver))
-
-int visor_check_channel(struct channel_header *ch, struct device *dev,
-			const guid_t *expected_uuid, char *chname,
-			u64 expected_min_bytes,	u32 expected_version,
-			u64 expected_signature);
-
-int visorbus_register_visor_driver(struct visor_driver *drv);
-void visorbus_unregister_visor_driver(struct visor_driver *drv);
-int visorbus_read_channel(struct visor_device *dev,
-			  unsigned long offset, void *dest,
-			  unsigned long nbytes);
-int visorbus_write_channel(struct visor_device *dev,
-			   unsigned long offset, void *src,
-			   unsigned long nbytes);
-int visorbus_enable_channel_interrupts(struct visor_device *dev);
-void visorbus_disable_channel_interrupts(struct visor_device *dev);
-
-int visorchannel_signalremove(struct visorchannel *channel, u32 queue,
-			      void *msg);
-int visorchannel_signalinsert(struct visorchannel *channel, u32 queue,
-			      void *msg);
-bool visorchannel_signalempty(struct visorchannel *channel, u32 queue);
-const guid_t *visorchannel_get_guid(struct visorchannel *channel);
-
-#define BUS_ROOT_DEVICE UINT_MAX
-struct visor_device *visorbus_get_device_by_id(u32 bus_no, u32 dev_no,
-					       struct visor_device *from);
-#endif
-- 
GitLab


From 9f4639373e6756e1ccf0029f861f1061db3c3616 Mon Sep 17 00:00:00 2001
From: Alexander Usyskin <alexander.usyskin@intel.com>
Date: Mon, 6 Jun 2022 17:42:23 +0300
Subject: [PATCH 0447/1731] mei: me: set internal pg flag to off on hardware
 reset

Link reset flow is always performed in the runtime resumed state.
The internal PG state may be left as ON after the suspend
and will not be updated upon the resume if the D0i3 is not supported.

Ensure that the internal PG state is set to the right value on the flow
entrance in case the firmware does not support D0i3.

Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Link: https://lore.kernel.org/r/20220606144225.282375-1-tomas.winkler@intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/misc/mei/hw-me.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
index 9870bf7179797..befa491e33445 100644
--- a/drivers/misc/mei/hw-me.c
+++ b/drivers/misc/mei/hw-me.c
@@ -1154,6 +1154,8 @@ static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
 			ret = mei_me_d0i3_exit_sync(dev);
 			if (ret)
 				return ret;
+		} else {
+			hw->pg_state = MEI_PG_OFF;
 		}
 	}
 
-- 
GitLab


From 68553650bc9c57c7e530c84e5b2945e9dfe1a560 Mon Sep 17 00:00:00 2001
From: Alexander Usyskin <alexander.usyskin@intel.com>
Date: Mon, 6 Jun 2022 17:42:24 +0300
Subject: [PATCH 0448/1731] mei: hbm: drop capability response on early
 shutdown

Drop HBM responses also in the early shutdown phase where
the usual traffic is allowed.
Extend the rule that drop HBM responses received during the shutdown
phase by also in MEI_DEV_POWERING_DOWN state.
This resolves the stall if the driver is stopping in the middle
of the link initialization or link reset.

Drop the capabilities response on early shutdown.

Fixes: 6d7163f2c49f ("mei: hbm: drop hbm responses on early shutdown")
Cc: <stable@vger.kernel.org>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Link: https://lore.kernel.org/r/20220606144225.282375-2-tomas.winkler@intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/misc/mei/hbm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/misc/mei/hbm.c b/drivers/misc/mei/hbm.c
index cebcca6d6d3ef..cf2b8261da144 100644
--- a/drivers/misc/mei/hbm.c
+++ b/drivers/misc/mei/hbm.c
@@ -1351,7 +1351,8 @@ int mei_hbm_dispatch(struct mei_device *dev, struct mei_msg_hdr *hdr)
 
 		if (dev->dev_state != MEI_DEV_INIT_CLIENTS ||
 		    dev->hbm_state != MEI_HBM_CAP_SETUP) {
-			if (dev->dev_state == MEI_DEV_POWER_DOWN) {
+			if (dev->dev_state == MEI_DEV_POWER_DOWN ||
+			    dev->dev_state == MEI_DEV_POWERING_DOWN) {
 				dev_dbg(dev->dev, "hbm: capabilities response: on shutdown, ignoring\n");
 				return 0;
 			}
-- 
GitLab


From 3ed8c7d39cfef831fe508fc1308f146912fa72e6 Mon Sep 17 00:00:00 2001
From: Alexander Usyskin <alexander.usyskin@intel.com>
Date: Mon, 6 Jun 2022 17:42:25 +0300
Subject: [PATCH 0449/1731] mei: me: add raptor lake point S DID

Add Raptor (Point) Lake S device id.

Cc: <stable@vger.kernel.org>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Link: https://lore.kernel.org/r/20220606144225.282375-3-tomas.winkler@intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/misc/mei/hw-me-regs.h | 2 ++
 drivers/misc/mei/pci-me.c     | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/misc/mei/hw-me-regs.h b/drivers/misc/mei/hw-me-regs.h
index 64ce3f830262b..15e8e2b322b1a 100644
--- a/drivers/misc/mei/hw-me-regs.h
+++ b/drivers/misc/mei/hw-me-regs.h
@@ -109,6 +109,8 @@
 #define MEI_DEV_ID_ADP_P      0x51E0  /* Alder Lake Point P */
 #define MEI_DEV_ID_ADP_N      0x54E0  /* Alder Lake Point N */
 
+#define MEI_DEV_ID_RPL_S      0x7A68  /* Raptor Lake Point S */
+
 /*
  * MEI HW Section
  */
diff --git a/drivers/misc/mei/pci-me.c b/drivers/misc/mei/pci-me.c
index 33e58821e4785..5435604327a71 100644
--- a/drivers/misc/mei/pci-me.c
+++ b/drivers/misc/mei/pci-me.c
@@ -116,6 +116,8 @@ static const struct pci_device_id mei_me_pci_tbl[] = {
 	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)},
 	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)},
 
+	{MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_CFG)},
+
 	/* required last entry */
 	{0, }
 };
-- 
GitLab


From 928ea98252ad75118950941683893cf904541da9 Mon Sep 17 00:00:00 2001
From: Shin'ichiro Kawasaki <shinichiro.kawasaki@wdc.com>
Date: Wed, 1 Jun 2022 19:51:59 +0900
Subject: [PATCH 0450/1731] bus: fsl-mc-bus: fix KASAN use-after-free in
 fsl_mc_bus_remove()

In fsl_mc_bus_remove(), mc->root_mc_bus_dev->mc_io is passed to
fsl_destroy_mc_io(). However, mc->root_mc_bus_dev is already freed in
fsl_mc_device_remove(). Then reference to mc->root_mc_bus_dev->mc_io
triggers KASAN use-after-free. To avoid the use-after-free, keep the
reference to mc->root_mc_bus_dev->mc_io in a local variable and pass to
fsl_destroy_mc_io().

This patch needs rework to apply to kernels older than v5.15.

Fixes: f93627146f0e ("staging: fsl-mc: fix asymmetry in destroy of mc_io")
Cc: stable@vger.kernel.org # v5.15+
Signed-off-by: Shin'ichiro Kawasaki <shinichiro.kawasaki@wdc.com>
Link: https://lore.kernel.org/r/20220601105159.87752-1-shinichiro.kawasaki@wdc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/bus/fsl-mc/fsl-mc-bus.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/bus/fsl-mc/fsl-mc-bus.c b/drivers/bus/fsl-mc/fsl-mc-bus.c
index e81a9700cfd03..6143dbf31f311 100644
--- a/drivers/bus/fsl-mc/fsl-mc-bus.c
+++ b/drivers/bus/fsl-mc/fsl-mc-bus.c
@@ -1239,14 +1239,14 @@ error_cleanup_mc_io:
 static int fsl_mc_bus_remove(struct platform_device *pdev)
 {
 	struct fsl_mc *mc = platform_get_drvdata(pdev);
+	struct fsl_mc_io *mc_io;
 
 	if (!fsl_mc_is_root_dprc(&mc->root_mc_bus_dev->dev))
 		return -EINVAL;
 
+	mc_io = mc->root_mc_bus_dev->mc_io;
 	fsl_mc_device_remove(mc->root_mc_bus_dev);
-
-	fsl_destroy_mc_io(mc->root_mc_bus_dev->mc_io);
-	mc->root_mc_bus_dev->mc_io = NULL;
+	fsl_destroy_mc_io(mc_io);
 
 	bus_unregister_notifier(&fsl_mc_bus_type, &fsl_mc_nb);
 
-- 
GitLab


From 0a35780c755ccec097d15c6b4ff8b246a89f1689 Mon Sep 17 00:00:00 2001
From: Brad Bishop <bradleyb@fuzziesquirrel.com>
Date: Tue, 24 May 2022 16:51:42 -0500
Subject: [PATCH 0451/1731] eeprom: at25: Split reads into chunks and cap write
 size

Make use of spi_max_transfer_size to avoid requesting transfers that are
too large for some spi controllers.

Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220524215142.60047-1-eajames@linux.ibm.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/misc/eeprom/at25.c | 93 ++++++++++++++++++++++----------------
 1 file changed, 53 insertions(+), 40 deletions(-)

diff --git a/drivers/misc/eeprom/at25.c b/drivers/misc/eeprom/at25.c
index 8d169a35cf130..c9c56fd194c13 100644
--- a/drivers/misc/eeprom/at25.c
+++ b/drivers/misc/eeprom/at25.c
@@ -79,6 +79,11 @@ static int at25_ee_read(void *priv, unsigned int offset,
 {
 	struct at25_data *at25 = priv;
 	char *buf = val;
+	size_t max_chunk = spi_max_transfer_size(at25->spi);
+	size_t num_msgs = DIV_ROUND_UP(count, max_chunk);
+	size_t nr_bytes = 0;
+	unsigned int msg_offset;
+	size_t msg_count;
 	u8			*cp;
 	ssize_t			status;
 	struct spi_transfer	t[2];
@@ -92,54 +97,59 @@ static int at25_ee_read(void *priv, unsigned int offset,
 	if (unlikely(!count))
 		return -EINVAL;
 
-	cp = at25->command;
+	msg_offset = (unsigned int)offset;
+	msg_count = min(count, max_chunk);
+	while (num_msgs) {
+		cp = at25->command;
 
-	instr = AT25_READ;
-	if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
-		if (offset >= BIT(at25->addrlen * 8))
-			instr |= AT25_INSTR_BIT3;
+		instr = AT25_READ;
+		if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
+			if (msg_offset >= BIT(at25->addrlen * 8))
+				instr |= AT25_INSTR_BIT3;
 
-	mutex_lock(&at25->lock);
+		mutex_lock(&at25->lock);
 
-	*cp++ = instr;
-
-	/* 8/16/24-bit address is written MSB first */
-	switch (at25->addrlen) {
-	default:	/* case 3 */
-		*cp++ = offset >> 16;
-		fallthrough;
-	case 2:
-		*cp++ = offset >> 8;
-		fallthrough;
-	case 1:
-	case 0:	/* can't happen: for better code generation */
-		*cp++ = offset >> 0;
-	}
+		*cp++ = instr;
 
-	spi_message_init(&m);
-	memset(t, 0, sizeof(t));
+		/* 8/16/24-bit address is written MSB first */
+		switch (at25->addrlen) {
+		default:	/* case 3 */
+			*cp++ = msg_offset >> 16;
+			fallthrough;
+		case 2:
+			*cp++ = msg_offset >> 8;
+			fallthrough;
+		case 1:
+		case 0:	/* can't happen: for better code generation */
+			*cp++ = msg_offset >> 0;
+		}
 
-	t[0].tx_buf = at25->command;
-	t[0].len = at25->addrlen + 1;
-	spi_message_add_tail(&t[0], &m);
+		spi_message_init(&m);
+		memset(t, 0, sizeof(t));
 
-	t[1].rx_buf = buf;
-	t[1].len = count;
-	spi_message_add_tail(&t[1], &m);
+		t[0].tx_buf = at25->command;
+		t[0].len = at25->addrlen + 1;
+		spi_message_add_tail(&t[0], &m);
 
-	/*
-	 * Read it all at once.
-	 *
-	 * REVISIT that's potentially a problem with large chips, if
-	 * other devices on the bus need to be accessed regularly or
-	 * this chip is clocked very slowly.
-	 */
-	status = spi_sync(at25->spi, &m);
-	dev_dbg(&at25->spi->dev, "read %zu bytes at %d --> %zd\n",
-		count, offset, status);
+		t[1].rx_buf = buf + nr_bytes;
+		t[1].len = msg_count;
+		spi_message_add_tail(&t[1], &m);
 
-	mutex_unlock(&at25->lock);
-	return status;
+		status = spi_sync(at25->spi, &m);
+
+		mutex_unlock(&at25->lock);
+
+		if (status)
+			return status;
+
+		--num_msgs;
+		msg_offset += msg_count;
+		nr_bytes += msg_count;
+	}
+
+	dev_dbg(&at25->spi->dev, "read %zu bytes at %d\n",
+		count, offset);
+	return 0;
 }
 
 /* Read extra registers as ID or serial number */
@@ -190,6 +200,7 @@ ATTRIBUTE_GROUPS(sernum);
 static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count)
 {
 	struct at25_data *at25 = priv;
+	size_t maxsz = spi_max_transfer_size(at25->spi);
 	const char *buf = val;
 	int			status = 0;
 	unsigned		buf_size;
@@ -253,6 +264,8 @@ static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count)
 		segment = buf_size - (offset % buf_size);
 		if (segment > count)
 			segment = count;
+		if (segment > maxsz)
+			segment = maxsz;
 		memcpy(cp, buf, segment);
 		status = spi_write(at25->spi, bounce,
 				segment + at25->addrlen + 1);
-- 
GitLab


From 566d3c57eb526f32951af15866086e236ce1fc8a Mon Sep 17 00:00:00 2001
From: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Date: Wed, 8 Jun 2022 10:13:02 +0900
Subject: [PATCH 0452/1731] scsi: scsi_debug: Fix zone transition to full
 condition

When a write command to a sequential write required or sequential write
preferred zone result in the zone write pointer reaching the end of the
zone, the zone condition must be set to full AND the number of implicitly
or explicitly open zones updated to have a correct accounting for zone
resources. However, the function zbc_inc_wp() only sets the zone condition
to full without updating the open zone counters, resulting in a zone state
machine breakage.

Introduce the helper function zbc_set_zone_full() and use it in
zbc_inc_wp() to correctly transition zones to the full condition.

Link: https://lore.kernel.org/r/20220608011302.92061-1-damien.lemoal@opensource.wdc.com
Fixes: f0d1cf9378bd ("scsi: scsi_debug: Add ZBC zone commands")
Reviewed-by: Niklas Cassel <niklas.cassel@wdc.com>
Acked-by: Douglas Gilbert <dgilbert@interlog.com>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
---
 drivers/scsi/scsi_debug.c | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/scsi/scsi_debug.c b/drivers/scsi/scsi_debug.c
index 1f423f723d064..b8a76b89f85a3 100644
--- a/drivers/scsi/scsi_debug.c
+++ b/drivers/scsi/scsi_debug.c
@@ -2826,6 +2826,24 @@ static void zbc_open_zone(struct sdebug_dev_info *devip,
 	}
 }
 
+static inline void zbc_set_zone_full(struct sdebug_dev_info *devip,
+				     struct sdeb_zone_state *zsp)
+{
+	switch (zsp->z_cond) {
+	case ZC2_IMPLICIT_OPEN:
+		devip->nr_imp_open--;
+		break;
+	case ZC3_EXPLICIT_OPEN:
+		devip->nr_exp_open--;
+		break;
+	default:
+		WARN_ONCE(true, "Invalid zone %llu condition %x\n",
+			  zsp->z_start, zsp->z_cond);
+		break;
+	}
+	zsp->z_cond = ZC5_FULL;
+}
+
 static void zbc_inc_wp(struct sdebug_dev_info *devip,
 		       unsigned long long lba, unsigned int num)
 {
@@ -2838,7 +2856,7 @@ static void zbc_inc_wp(struct sdebug_dev_info *devip,
 	if (zsp->z_type == ZBC_ZTYPE_SWR) {
 		zsp->z_wp += num;
 		if (zsp->z_wp >= zend)
-			zsp->z_cond = ZC5_FULL;
+			zbc_set_zone_full(devip, zsp);
 		return;
 	}
 
@@ -2857,7 +2875,7 @@ static void zbc_inc_wp(struct sdebug_dev_info *devip,
 			n = num;
 		}
 		if (zsp->z_wp >= zend)
-			zsp->z_cond = ZC5_FULL;
+			zbc_set_zone_full(devip, zsp);
 
 		num -= n;
 		lba += n;
-- 
GitLab


From 8e60294c8012fe4c66c3590376670998902fd822 Mon Sep 17 00:00:00 2001
From: Cristian Marussi <cristian.marussi@arm.com>
Date: Wed, 8 Jun 2022 17:40:51 +0100
Subject: [PATCH 0453/1731] firmware: arm_scmi: Fix SENSOR_AXIS_NAME_GET
 behaviour when unsupported

Avoid to invoke SENSOR_AXIS_NAME_GET on sensors that have not declared at
least one of their axes as supporting extended names.

Since the returned list of axes supporting extended names is not
necessarily comprising all the existing axes of the specified sensor,
take care also to properly pick the axis descriptor from the ID embedded
in the response.

Link: https://lore.kernel.org/r/20220608164051.2326087-1-cristian.marussi@arm.com
Fixes: 802b0bed011e ("firmware: arm_scmi: Add SCMI v3.1 SENSOR_AXIS_NAME_GET support")
Cc: Peter Hilber <peter.hilber@opensynergy.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Peter Hilber <peter.hilber@opensynergy.com>
Signed-off-by: Cristian Marussi <cristian.marussi@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
 drivers/firmware/arm_scmi/sensors.c | 56 +++++++++++++++++++++++------
 1 file changed, 46 insertions(+), 10 deletions(-)

diff --git a/drivers/firmware/arm_scmi/sensors.c b/drivers/firmware/arm_scmi/sensors.c
index 75b9d716508ea..8a93dd944c49c 100644
--- a/drivers/firmware/arm_scmi/sensors.c
+++ b/drivers/firmware/arm_scmi/sensors.c
@@ -358,15 +358,20 @@ static int scmi_sensor_update_intervals(const struct scmi_protocol_handle *ph,
 	return ph->hops->iter_response_run(iter);
 }
 
+struct scmi_apriv {
+	bool any_axes_support_extended_names;
+	struct scmi_sensor_info *s;
+};
+
 static void iter_axes_desc_prepare_message(void *message,
 					   const unsigned int desc_index,
 					   const void *priv)
 {
 	struct scmi_msg_sensor_axis_description_get *msg = message;
-	const struct scmi_sensor_info *s = priv;
+	const struct scmi_apriv *apriv = priv;
 
 	/* Set the number of sensors to be skipped/already read */
-	msg->id = cpu_to_le32(s->id);
+	msg->id = cpu_to_le32(apriv->s->id);
 	msg->axis_desc_index = cpu_to_le32(desc_index);
 }
 
@@ -393,12 +398,14 @@ iter_axes_desc_process_response(const struct scmi_protocol_handle *ph,
 	u32 attrh, attrl;
 	struct scmi_sensor_axis_info *a;
 	size_t dsize = SCMI_MSG_RESP_AXIS_DESCR_BASE_SZ;
-	struct scmi_sensor_info *s = priv;
+	struct scmi_apriv *apriv = priv;
 	const struct scmi_axis_descriptor *adesc = st->priv;
 
 	attrl = le32_to_cpu(adesc->attributes_low);
+	if (SUPPORTS_EXTENDED_AXIS_NAMES(attrl))
+		apriv->any_axes_support_extended_names = true;
 
-	a = &s->axis[st->desc_index + st->loop_idx];
+	a = &apriv->s->axis[st->desc_index + st->loop_idx];
 	a->id = le32_to_cpu(adesc->id);
 	a->extended_attrs = SUPPORTS_EXTEND_ATTRS(attrl);
 
@@ -444,10 +451,19 @@ iter_axes_extended_name_process_response(const struct scmi_protocol_handle *ph,
 					 void *priv)
 {
 	struct scmi_sensor_axis_info *a;
-	const struct scmi_sensor_info *s = priv;
+	const struct scmi_apriv *apriv = priv;
 	struct scmi_sensor_axis_name_descriptor *adesc = st->priv;
+	u32 axis_id = le32_to_cpu(adesc->axis_id);
+
+	if (axis_id >= st->max_resources)
+		return -EPROTO;
 
-	a = &s->axis[st->desc_index + st->loop_idx];
+	/*
+	 * Pick the corresponding descriptor based on the axis_id embedded
+	 * in the reply since the list of axes supporting extended names
+	 * can be a subset of all the axes.
+	 */
+	a = &apriv->s->axis[axis_id];
 	strscpy(a->name, adesc->name, SCMI_MAX_STR_SIZE);
 	st->priv = ++adesc;
 
@@ -458,21 +474,36 @@ static int
 scmi_sensor_axis_extended_names_get(const struct scmi_protocol_handle *ph,
 				    struct scmi_sensor_info *s)
 {
+	int ret;
 	void *iter;
 	struct scmi_iterator_ops ops = {
 		.prepare_message = iter_axes_desc_prepare_message,
 		.update_state = iter_axes_extended_name_update_state,
 		.process_response = iter_axes_extended_name_process_response,
 	};
+	struct scmi_apriv apriv = {
+		.any_axes_support_extended_names = false,
+		.s = s,
+	};
 
 	iter = ph->hops->iter_response_init(ph, &ops, s->num_axis,
 					    SENSOR_AXIS_NAME_GET,
 					    sizeof(struct scmi_msg_sensor_axis_description_get),
-					    s);
+					    &apriv);
 	if (IS_ERR(iter))
 		return PTR_ERR(iter);
 
-	return ph->hops->iter_response_run(iter);
+	/*
+	 * Do not cause whole protocol initialization failure when failing to
+	 * get extended names for axes.
+	 */
+	ret = ph->hops->iter_response_run(iter);
+	if (ret)
+		dev_warn(ph->dev,
+			 "Failed to get axes extended names for %s (ret:%d).\n",
+			 s->name, ret);
+
+	return 0;
 }
 
 static int scmi_sensor_axis_description(const struct scmi_protocol_handle *ph,
@@ -486,6 +517,10 @@ static int scmi_sensor_axis_description(const struct scmi_protocol_handle *ph,
 		.update_state = iter_axes_desc_update_state,
 		.process_response = iter_axes_desc_process_response,
 	};
+	struct scmi_apriv apriv = {
+		.any_axes_support_extended_names = false,
+		.s = s,
+	};
 
 	s->axis = devm_kcalloc(ph->dev, s->num_axis,
 			       sizeof(*s->axis), GFP_KERNEL);
@@ -495,7 +530,7 @@ static int scmi_sensor_axis_description(const struct scmi_protocol_handle *ph,
 	iter = ph->hops->iter_response_init(ph, &ops, s->num_axis,
 					    SENSOR_AXIS_DESCRIPTION_GET,
 					    sizeof(struct scmi_msg_sensor_axis_description_get),
-					    s);
+					    &apriv);
 	if (IS_ERR(iter))
 		return PTR_ERR(iter);
 
@@ -503,7 +538,8 @@ static int scmi_sensor_axis_description(const struct scmi_protocol_handle *ph,
 	if (ret)
 		return ret;
 
-	if (PROTOCOL_REV_MAJOR(version) >= 0x3)
+	if (PROTOCOL_REV_MAJOR(version) >= 0x3 &&
+	    apriv.any_axes_support_extended_names)
 		ret = scmi_sensor_axis_extended_names_get(ph, s);
 
 	return ret;
-- 
GitLab


From 4314f9f4f85832b5082f4e38b07b63b11baa538c Mon Sep 17 00:00:00 2001
From: Cristian Marussi <cristian.marussi@arm.com>
Date: Wed, 8 Jun 2022 10:55:28 +0100
Subject: [PATCH 0454/1731] firmware: arm_scmi: Avoid using extended
 string-buffers sizes if not necessary

Commit b260fccaebdc2 ("firmware: arm_scmi: Add SCMI v3.1 protocol extended
names support") moved all the name string buffers to use the extended buffer
size of 64 instead of the required 16 bytes. While that should be fine if
the firmware terminates the string before 16 bytes, there is possibility
of copying random data if the name is not NULL terminated by the firmware.

SCMI base protocol agent_name/vendor_id/sub_vendor_id are defined by the
specification as NULL-terminated ASCII strings up to 16-bytes in length.

The underlying buffers and message descriptors are currently bigger than
needed; resize them to fit only the strictly needed 16 bytes to avoid
any possible leaks when reading data from the firmware.

Change the size argument of strlcpy to use SCMI_SHORT_NAME_MAX_SIZE always
when dealing with short domain names, so as to limit the possibility that
an ill-formed non-NULL terminated short reply from the SCMI platform
firmware can leak stale content laying in the underlying transport shared
memory area.

While at that, convert all strings handling routines to use the preferred
strscpy.

Link: https://lore.kernel.org/r/20220608095530.497879-1-cristian.marussi@arm.com
Fixes: b260fccaebdc2 ("firmware: arm_scmi: Add SCMI v3.1 protocol extended names support")
Signed-off-by: Cristian Marussi <cristian.marussi@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
 drivers/firmware/arm_scmi/base.c      | 8 ++++----
 drivers/firmware/arm_scmi/clock.c     | 2 +-
 drivers/firmware/arm_scmi/perf.c      | 2 +-
 drivers/firmware/arm_scmi/power.c     | 2 +-
 drivers/firmware/arm_scmi/protocols.h | 2 --
 drivers/firmware/arm_scmi/reset.c     | 2 +-
 drivers/firmware/arm_scmi/sensors.c   | 4 ++--
 drivers/firmware/arm_scmi/voltage.c   | 2 +-
 include/linux/scmi_protocol.h         | 9 +++++----
 9 files changed, 16 insertions(+), 17 deletions(-)

diff --git a/drivers/firmware/arm_scmi/base.c b/drivers/firmware/arm_scmi/base.c
index d0ac96da1ddff..a52f084a6a87b 100644
--- a/drivers/firmware/arm_scmi/base.c
+++ b/drivers/firmware/arm_scmi/base.c
@@ -36,7 +36,7 @@ struct scmi_msg_resp_base_attributes {
 
 struct scmi_msg_resp_base_discover_agent {
 	__le32 agent_id;
-	u8 name[SCMI_MAX_STR_SIZE];
+	u8 name[SCMI_SHORT_NAME_MAX_SIZE];
 };
 
 
@@ -119,7 +119,7 @@ scmi_base_vendor_id_get(const struct scmi_protocol_handle *ph, bool sub_vendor)
 
 	ret = ph->xops->do_xfer(ph, t);
 	if (!ret)
-		memcpy(vendor_id, t->rx.buf, size);
+		strscpy(vendor_id, t->rx.buf, size);
 
 	ph->xops->xfer_put(ph, t);
 
@@ -276,7 +276,7 @@ static int scmi_base_discover_agent_get(const struct scmi_protocol_handle *ph,
 	ret = ph->xops->do_xfer(ph, t);
 	if (!ret) {
 		agent_info = t->rx.buf;
-		strlcpy(name, agent_info->name, SCMI_MAX_STR_SIZE);
+		strscpy(name, agent_info->name, SCMI_SHORT_NAME_MAX_SIZE);
 	}
 
 	ph->xops->xfer_put(ph, t);
@@ -375,7 +375,7 @@ static int scmi_base_protocol_init(const struct scmi_protocol_handle *ph)
 	int id, ret;
 	u8 *prot_imp;
 	u32 version;
-	char name[SCMI_MAX_STR_SIZE];
+	char name[SCMI_SHORT_NAME_MAX_SIZE];
 	struct device *dev = ph->dev;
 	struct scmi_revision_info *rev = scmi_revision_area_get(ph);
 
diff --git a/drivers/firmware/arm_scmi/clock.c b/drivers/firmware/arm_scmi/clock.c
index 1a718faa41924..c7a83f6e38e5a 100644
--- a/drivers/firmware/arm_scmi/clock.c
+++ b/drivers/firmware/arm_scmi/clock.c
@@ -153,7 +153,7 @@ static int scmi_clock_attributes_get(const struct scmi_protocol_handle *ph,
 	if (!ret) {
 		u32 latency = 0;
 		attributes = le32_to_cpu(attr->attributes);
-		strlcpy(clk->name, attr->name, SCMI_MAX_STR_SIZE);
+		strscpy(clk->name, attr->name, SCMI_SHORT_NAME_MAX_SIZE);
 		/* clock_enable_latency field is present only since SCMI v3.1 */
 		if (PROTOCOL_REV_MAJOR(version) >= 0x2)
 			latency = le32_to_cpu(attr->clock_enable_latency);
diff --git a/drivers/firmware/arm_scmi/perf.c b/drivers/firmware/arm_scmi/perf.c
index c1f7016230582..bbb0331801ff4 100644
--- a/drivers/firmware/arm_scmi/perf.c
+++ b/drivers/firmware/arm_scmi/perf.c
@@ -252,7 +252,7 @@ scmi_perf_domain_attributes_get(const struct scmi_protocol_handle *ph,
 			dom_info->mult_factor =
 					(dom_info->sustained_freq_khz * 1000) /
 					dom_info->sustained_perf_level;
-		strlcpy(dom_info->name, attr->name, SCMI_MAX_STR_SIZE);
+		strscpy(dom_info->name, attr->name, SCMI_SHORT_NAME_MAX_SIZE);
 	}
 
 	ph->xops->xfer_put(ph, t);
diff --git a/drivers/firmware/arm_scmi/power.c b/drivers/firmware/arm_scmi/power.c
index 964882cc87471..356e83631664d 100644
--- a/drivers/firmware/arm_scmi/power.c
+++ b/drivers/firmware/arm_scmi/power.c
@@ -122,7 +122,7 @@ scmi_power_domain_attributes_get(const struct scmi_protocol_handle *ph,
 		dom_info->state_set_notify = SUPPORTS_STATE_SET_NOTIFY(flags);
 		dom_info->state_set_async = SUPPORTS_STATE_SET_ASYNC(flags);
 		dom_info->state_set_sync = SUPPORTS_STATE_SET_SYNC(flags);
-		strlcpy(dom_info->name, attr->name, SCMI_MAX_STR_SIZE);
+		strscpy(dom_info->name, attr->name, SCMI_SHORT_NAME_MAX_SIZE);
 	}
 	ph->xops->xfer_put(ph, t);
 
diff --git a/drivers/firmware/arm_scmi/protocols.h b/drivers/firmware/arm_scmi/protocols.h
index 73304af5ec4ac..c679f3fb8718b 100644
--- a/drivers/firmware/arm_scmi/protocols.h
+++ b/drivers/firmware/arm_scmi/protocols.h
@@ -24,8 +24,6 @@
 
 #include <asm/unaligned.h>
 
-#define SCMI_SHORT_NAME_MAX_SIZE	16
-
 #define PROTOCOL_REV_MINOR_MASK	GENMASK(15, 0)
 #define PROTOCOL_REV_MAJOR_MASK	GENMASK(31, 16)
 #define PROTOCOL_REV_MAJOR(x)	((u16)(FIELD_GET(PROTOCOL_REV_MAJOR_MASK, (x))))
diff --git a/drivers/firmware/arm_scmi/reset.c b/drivers/firmware/arm_scmi/reset.c
index a420a91020940..673f3eb498f43 100644
--- a/drivers/firmware/arm_scmi/reset.c
+++ b/drivers/firmware/arm_scmi/reset.c
@@ -116,7 +116,7 @@ scmi_reset_domain_attributes_get(const struct scmi_protocol_handle *ph,
 		dom_info->latency_us = le32_to_cpu(attr->latency);
 		if (dom_info->latency_us == U32_MAX)
 			dom_info->latency_us = 0;
-		strlcpy(dom_info->name, attr->name, SCMI_MAX_STR_SIZE);
+		strscpy(dom_info->name, attr->name, SCMI_SHORT_NAME_MAX_SIZE);
 	}
 
 	ph->xops->xfer_put(ph, t);
diff --git a/drivers/firmware/arm_scmi/sensors.c b/drivers/firmware/arm_scmi/sensors.c
index 8a93dd944c49c..7288c61178380 100644
--- a/drivers/firmware/arm_scmi/sensors.c
+++ b/drivers/firmware/arm_scmi/sensors.c
@@ -412,7 +412,7 @@ iter_axes_desc_process_response(const struct scmi_protocol_handle *ph,
 	attrh = le32_to_cpu(adesc->attributes_high);
 	a->scale = S32_EXT(SENSOR_SCALE(attrh));
 	a->type = SENSOR_TYPE(attrh);
-	strscpy(a->name, adesc->name, SCMI_MAX_STR_SIZE);
+	strscpy(a->name, adesc->name, SCMI_SHORT_NAME_MAX_SIZE);
 
 	if (a->extended_attrs) {
 		unsigned int ares = le32_to_cpu(adesc->resolution);
@@ -634,7 +634,7 @@ iter_sens_descr_process_response(const struct scmi_protocol_handle *ph,
 			    SUPPORTS_AXIS(attrh) ?
 			    SENSOR_AXIS_NUMBER(attrh) : 0,
 			    SCMI_MAX_NUM_SENSOR_AXIS);
-	strscpy(s->name, sdesc->name, SCMI_MAX_STR_SIZE);
+	strscpy(s->name, sdesc->name, SCMI_SHORT_NAME_MAX_SIZE);
 
 	/*
 	 * If supported overwrite short name with the extended
diff --git a/drivers/firmware/arm_scmi/voltage.c b/drivers/firmware/arm_scmi/voltage.c
index 97df6d3dd1318..5de93f637bd47 100644
--- a/drivers/firmware/arm_scmi/voltage.c
+++ b/drivers/firmware/arm_scmi/voltage.c
@@ -233,7 +233,7 @@ static int scmi_voltage_descriptors_get(const struct scmi_protocol_handle *ph,
 		v = vinfo->domains + dom;
 		v->id = dom;
 		attributes = le32_to_cpu(resp_dom->attr);
-		strlcpy(v->name, resp_dom->name, SCMI_MAX_STR_SIZE);
+		strscpy(v->name, resp_dom->name, SCMI_SHORT_NAME_MAX_SIZE);
 
 		/*
 		 * If supported overwrite short name with the extended one;
diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h
index 1c58646ba381c..704111f639937 100644
--- a/include/linux/scmi_protocol.h
+++ b/include/linux/scmi_protocol.h
@@ -13,8 +13,9 @@
 #include <linux/notifier.h>
 #include <linux/types.h>
 
-#define SCMI_MAX_STR_SIZE	64
-#define SCMI_MAX_NUM_RATES	16
+#define SCMI_MAX_STR_SIZE		64
+#define SCMI_SHORT_NAME_MAX_SIZE	16
+#define SCMI_MAX_NUM_RATES		16
 
 /**
  * struct scmi_revision_info - version information structure
@@ -36,8 +37,8 @@ struct scmi_revision_info {
 	u8 num_protocols;
 	u8 num_agents;
 	u32 impl_ver;
-	char vendor_id[SCMI_MAX_STR_SIZE];
-	char sub_vendor_id[SCMI_MAX_STR_SIZE];
+	char vendor_id[SCMI_SHORT_NAME_MAX_SIZE];
+	char sub_vendor_id[SCMI_SHORT_NAME_MAX_SIZE];
 };
 
 struct scmi_clock_info {
-- 
GitLab


From ce19bbe46fcfb88e75a6c7f691df4753a72daa81 Mon Sep 17 00:00:00 2001
From: Chandan Vurdigere Nataraj <chandan.vurdigerenataraj@amd.com>
Date: Tue, 7 Jun 2022 14:58:57 +0530
Subject: [PATCH 0455/1731] drm/amdgpu/display: Remove unnecessary typecasts
 and fix build issues

[Why]
Getting below errors:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1414:5: error: implicit conversion from enumeration type 'enum scan_direction_class' to different enumeration type 'enum dm_rotation_angle' [-Werror,-Wenum-conversion]
                                mode_lib->vba.SourceScan[k],
                                ^~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1744:22: error: implicit conversion from enumeration type 'enum scan_direction_class' to different enumeration type 'enum dm_rotation_angle' [-Werror,-Wenum-conversion]
                        && (!(!IsVertical(mode_lib->vba.SourceScan[k])) || mode_lib->vba.DCCEnable[k] == true)) {
                               ~~~~~~~~~~ ^~~~~~~~~~~~~~~~~~~~~~~~~~~
2 errors generated.

drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.c:5484:18: error: implicit conversion from enumeration type 'RequestType' to different enumeration type 'enum RequestType' [-Werror,-Wenum-conversion]
                        RequestLuma = REQ_256Bytes;
                                    ~ ^~~~~~~~~~~~
18 errors of similar kind

[How]
1. Add typecast at relevant places
2. Move the enum RequestType definition ahead of declarations

Signed-off-by: Chandan Vurdigere Nataraj <chandan.vurdigerenataraj@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../dc/dml/dcn32/display_mode_vba_32.c        |  5 ++--
 .../dc/dml/dcn32/display_mode_vba_util_32.c   | 25 +++++++++----------
 2 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index b77a1ae792d12..5828e60f291d4 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -1411,7 +1411,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 				v->BytePerPixelC[k],
 				v->BytePerPixelDETY[k],
 				v->BytePerPixelDETC[k],
-				mode_lib->vba.SourceScan[k],
+				(enum dm_rotation_angle) mode_lib->vba.SourceScan[k],
 				/* Output */
 				&v->DCCYMaxUncompressedBlock[k],
 				&v->DCCCMaxUncompressedBlock[k],
@@ -1741,7 +1741,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 	mode_lib->vba.SourceFormatPixelAndScanSupport = true;
 	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
 		if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
-			&& (!(!IsVertical(mode_lib->vba.SourceScan[k])) || mode_lib->vba.DCCEnable[k] == true)) {
+			&& (!(!IsVertical((enum dm_rotation_angle) mode_lib->vba.SourceScan[k]))
+				|| mode_lib->vba.DCCEnable[k] == true)) {
 			mode_lib->vba.SourceFormatPixelAndScanSupport = false;
 		}
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index 6509a84eeb640..07f3a85f8edf3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -5314,9 +5314,15 @@ void dml32_CalculateDCCConfiguration(
 		unsigned int        *IndependentBlockLuma,
 		unsigned int        *IndependentBlockChroma)
 {
+	typedef enum {
+		REQ_256Bytes,
+		REQ_128BytesNonContiguous,
+		REQ_128BytesContiguous,
+		REQ_NA
+	} RequestType;
 
-	enum RequestType   RequestLuma;
-	enum RequestType   RequestChroma;
+	RequestType   RequestLuma;
+	RequestType   RequestChroma;
 
 	unsigned int   segment_order_horz_contiguous_luma;
 	unsigned int   segment_order_horz_contiguous_chroma;
@@ -5350,13 +5356,6 @@ void dml32_CalculateDCCConfiguration(
 	double   detile_buf_vp_horz_limit;
 	double   detile_buf_vp_vert_limit;
 
-	typedef enum {
-		REQ_256Bytes,
-		REQ_128BytesNonContiguous,
-		REQ_128BytesContiguous,
-		REQ_NA
-	} RequestType;
-
 	yuv420 = ((SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 ||
 			SourcePixelFormat == dm_420_12) ? 1 : 0);
 	horz_div_l = 1;
@@ -5527,11 +5526,11 @@ void dml32_CalculateDCCConfiguration(
 			RequestChroma = REQ_128BytesContiguous;
 	}
 
-	if (RequestLuma == (enum RequestType) REQ_256Bytes) {
+	if (RequestLuma == REQ_256Bytes) {
 		*MaxUncompressedBlockLuma = 256;
 		*MaxCompressedBlockLuma = 256;
 		*IndependentBlockLuma = 0;
-	} else if (RequestLuma == (enum RequestType) REQ_128BytesContiguous) {
+	} else if (RequestLuma == REQ_128BytesContiguous) {
 		*MaxUncompressedBlockLuma = 256;
 		*MaxCompressedBlockLuma = 128;
 		*IndependentBlockLuma = 128;
@@ -5541,11 +5540,11 @@ void dml32_CalculateDCCConfiguration(
 		*IndependentBlockLuma = 64;
 	}
 
-	if (RequestChroma == (enum RequestType) REQ_256Bytes) {
+	if (RequestChroma == REQ_256Bytes) {
 		*MaxUncompressedBlockChroma = 256;
 		*MaxCompressedBlockChroma = 256;
 		*IndependentBlockChroma = 0;
-	} else if (RequestChroma == (enum RequestType) REQ_128BytesContiguous) {
+	} else if (RequestChroma == REQ_128BytesContiguous) {
 		*MaxUncompressedBlockChroma = 256;
 		*MaxCompressedBlockChroma = 128;
 		*IndependentBlockChroma = 128;
-- 
GitLab


From 7aade9ceeb88d8ca674141d2c245f0107032afb1 Mon Sep 17 00:00:00 2001
From: Chandan Vurdigere Nataraj <chandan.vurdigerenataraj@amd.com>
Date: Tue, 7 Jun 2022 13:47:29 +0530
Subject: [PATCH 0456/1731] drm/amdgpu/display: Fix compilation issues

[Why]
Getting below build errors:
drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:1419:3: error: unannotated fall-through between switch labels [-Werror,-Wimplicit-fallthrough]
                default:
                ^
drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:1535:2: error: unannotated fall-through between switch labels [-Werror,-Wimplicit-fallthrough]
        default:
        ^

drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:3276:20: error: variable 'v1_5' is uninitialized when used here [-Werror,-Wuninitialized]
                        for (i = 0; i < v1_5->number_of_path; ++i)
                                        ^~~~

[How]
Fix compilation issues

Signed-off-by: Chandan Vurdigere Nataraj <chandan.vurdigerenataraj@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 3540b46765fb0..25791ed0559d5 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -1415,7 +1415,7 @@ static enum bp_result bios_parser_get_lttpr_caps(
 		case 5:
 			result = get_disp_caps_v4_5(bp, dce_caps);
 			*dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
-
+			break;
 		default:
 			break;
 		}
@@ -1532,6 +1532,7 @@ static enum bp_result bios_parser_get_embedded_panel_info(
 		default:
 			break;
 		}
+		break;
 	default:
 		break;
 	}
@@ -3251,7 +3252,7 @@ static enum bp_result get_bracket_layout_record(
 	static enum bp_result result;
 	struct object_info_table *tbl;
 	struct display_object_info_table_v1_4 *v1_4;
-    struct display_object_info_table_v1_5 *v1_5;
+	struct display_object_info_table_v1_5 *v1_5;
 
 	if (slot_layout_info == NULL) {
 		DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n");
@@ -3259,6 +3260,7 @@ static enum bp_result get_bracket_layout_record(
 	}
 	tbl = &bp->object_info_tbl;
 	v1_4 = tbl->v1_4;
+	v1_5 = tbl->v1_5;
 
 	result = BP_RESULT_NORECORD;
 	switch (bp->object_info_tbl.revision.minor) {
-- 
GitLab


From 4c59b571fce6cedefc1c8e5158f7548f05c05ed6 Mon Sep 17 00:00:00 2001
From: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
Date: Mon, 6 Jun 2022 06:04:37 -0500
Subject: [PATCH 0457/1731] drm/amdkfd: Remove field io_link_count from struct
 kfd_topology_device

The field is redundant and does not serve any functional role

Signed-off-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_crat.c     | 2 --
 drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 1 -
 drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 1 -
 3 files changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index cbfb32b3d2352..a5409531a2fdf 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -1040,7 +1040,6 @@ static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink,
 			props->rec_transfer_size =
 					iolink->recommended_transfer_size;
 
-			dev->io_link_count++;
 			dev->node_props.io_links_count++;
 			list_add_tail(&props->list, &dev->io_link_props);
 			break;
@@ -1067,7 +1066,6 @@ static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink,
 		props2->node_from = id_to;
 		props2->node_to = id_from;
 		props2->kobj = NULL;
-		to_dev->io_link_count++;
 		to_dev->node_props.io_links_count++;
 		list_add_tail(&props2->list, &to_dev->io_link_props);
 	}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 3e240b22ec912..304322ac39e68 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1819,7 +1819,6 @@ static void kfd_topology_update_io_links(int proximity_domain)
 			 */
 			if (iolink->node_to == proximity_domain) {
 				list_del(&iolink->list);
-				dev->io_link_count--;
 				dev->node_props.io_links_count--;
 			} else {
 				if (iolink->node_from > proximity_domain)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
index 2fb5664e10411..9f6c949186c19 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
@@ -130,7 +130,6 @@ struct kfd_topology_device {
 	struct list_head		mem_props;
 	uint32_t			cache_count;
 	struct list_head		cache_props;
-	uint32_t			io_link_count;
 	struct list_head		io_link_props;
 	struct list_head		p2p_link_props;
 	struct list_head		perf_props;
-- 
GitLab


From 73b4b53276a1d6290cd4f47dbbc885b6e6e59ac6 Mon Sep 17 00:00:00 2001
From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Date: Thu, 19 May 2022 09:47:28 -0400
Subject: [PATCH 0458/1731] Revert "workqueue: remove unused cancel_work()"
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This reverts commit 6417250d3f894e66a68ba1cd93676143f2376a6f.

amdpgu need this function in order to prematurly stop pending
reset works when another reset work already in progress.

Acked-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Lai Jiangshan<jiangshanlai@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 include/linux/workqueue.h | 1 +
 kernel/workqueue.c        | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/include/linux/workqueue.h b/include/linux/workqueue.h
index 7fee9b6cfedef..9e41e12261938 100644
--- a/include/linux/workqueue.h
+++ b/include/linux/workqueue.h
@@ -453,6 +453,7 @@ extern int schedule_on_each_cpu(work_func_t func);
 int execute_in_process_context(work_func_t fn, struct execute_work *);
 
 extern bool flush_work(struct work_struct *work);
+extern bool cancel_work(struct work_struct *work);
 extern bool cancel_work_sync(struct work_struct *work);
 
 extern bool flush_delayed_work(struct delayed_work *dwork);
diff --git a/kernel/workqueue.c b/kernel/workqueue.c
index 0d2514b4ff0d2..20d226d5bbc26 100644
--- a/kernel/workqueue.c
+++ b/kernel/workqueue.c
@@ -3258,6 +3258,15 @@ static bool __cancel_work(struct work_struct *work, bool is_dwork)
 	return ret;
 }
 
+/*
+ * See cancel_delayed_work()
+ */
+bool cancel_work(struct work_struct *work)
+{
+	return __cancel_work(work, false);
+}
+EXPORT_SYMBOL(cancel_work);
+
 /**
  * cancel_delayed_work - cancel a delayed work
  * @dwork: delayed_work to cancel
-- 
GitLab


From ab9a0b1f3661157d144fb744f3a197563e8e0ff4 Mon Sep 17 00:00:00 2001
From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Date: Tue, 17 May 2022 11:17:35 -0400
Subject: [PATCH 0459/1731] drm/amdgpu: Cache result of last reset at reset
 domain level.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Will be read by executors of async reset like debugfs.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h  | 1 +
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b9d50cb6c2361..6abec88cb5a87 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5318,6 +5318,8 @@ skip_sched_resume:
 
 	if (r)
 		dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
+
+	atomic_set(&adev->reset_domain->reset_res, r);
 	return r;
 }
 
@@ -5332,7 +5334,7 @@ static void amdgpu_device_queue_gpu_recover_work(struct work_struct *work)
 {
 	struct amdgpu_recover_work_struct *recover_work = container_of(work, struct amdgpu_recover_work_struct, base);
 
-	recover_work->ret = amdgpu_device_gpu_recover_imp(recover_work->adev, recover_work->job);
+	amdgpu_device_gpu_recover_imp(recover_work->adev, recover_work->job);
 }
 /*
  * Serialize gpu recover into reset domain single threaded wq
@@ -5349,7 +5351,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
 
 	flush_work(&work.base);
 
-	return work.ret;
+	return atomic_read(&adev->reset_domain->reset_res);
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
index c80af0889773e..32c86a0b145ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
@@ -132,6 +132,7 @@ struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_d
 	}
 
 	atomic_set(&reset_domain->in_gpu_reset, 0);
+	atomic_set(&reset_domain->reset_res, 0);
 	init_rwsem(&reset_domain->sem);
 
 	return reset_domain;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
index 1949dbe28a865..9e55a5d7a8253 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
@@ -82,6 +82,7 @@ struct amdgpu_reset_domain {
 	enum amdgpu_reset_domain_type type;
 	struct rw_semaphore sem;
 	atomic_t in_gpu_reset;
+	atomic_t reset_res;
 };
 
 
-- 
GitLab


From 25a2b22e4148b1ac91960e13f4f5de020ed04d05 Mon Sep 17 00:00:00 2001
From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Date: Tue, 17 May 2022 12:09:27 -0400
Subject: [PATCH 0460/1731] drm/admgpu: Serialize RAS recovery work directly
 into reset domain queue.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Save the extra usless work schedule.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index dac202ae864dd..b3b5ebbae82fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -35,6 +35,8 @@
 #include "amdgpu_xgmi.h"
 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
 #include "atom.h"
+#include "amdgpu_reset.h"
+
 #ifdef CONFIG_X86_MCE_AMD
 #include <asm/mce.h>
 
@@ -1937,7 +1939,7 @@ static void amdgpu_ras_do_recovery(struct work_struct *work)
 	}
 
 	if (amdgpu_device_should_recover_gpu(ras->adev))
-		amdgpu_device_gpu_recover(ras->adev, NULL);
+		amdgpu_device_gpu_recover_imp(ras->adev, NULL);
 	atomic_set(&ras->in_recovery, 0);
 }
 
@@ -2946,7 +2948,7 @@ int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 
 	if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
-		schedule_work(&ras->recovery_work);
+		amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work);
 	return 0;
 }
 
-- 
GitLab


From 2f83658ffc8c259f05e79dc632e34b26bb8b75c5 Mon Sep 17 00:00:00 2001
From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Date: Tue, 17 May 2022 14:14:19 -0400
Subject: [PATCH 0461/1731] drm/amdgpu: Add work_struct for GPU reset from
 debugfs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

We need to have a work_struct to cancel this reset if another
already in progress.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h       |  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 19 +++++++++++++++++--
 2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 7971d9208ecf2..ddb36c33b4bce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1058,6 +1058,8 @@ struct amdgpu_device {
 
 	bool                            scpm_enabled;
 	uint32_t                        scpm_status;
+
+	struct work_struct		reset_work;
 };
 
 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index d16c8c1f72db2..b0498ffcf7c33 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -39,6 +39,7 @@
 #include <drm/drm_drv.h>
 #include "amdgpu.h"
 #include "amdgpu_trace.h"
+#include "amdgpu_reset.h"
 
 /*
  * Fences
@@ -798,7 +799,10 @@ static int gpu_recover_get(void *data, u64 *val)
 		return 0;
 	}
 
-	*val = amdgpu_device_gpu_recover(adev, NULL);
+	if (amdgpu_reset_domain_schedule(adev->reset_domain, &adev->reset_work))
+		flush_work(&adev->reset_work);
+
+	*val = atomic_read(&adev->reset_domain->reset_res);
 
 	pm_runtime_mark_last_busy(dev->dev);
 	pm_runtime_put_autosuspend(dev->dev);
@@ -810,6 +814,14 @@ DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_fence_info);
 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gpu_recover_fops, gpu_recover_get, NULL,
 			 "%lld\n");
 
+static void amdgpu_debugfs_reset_work(struct work_struct *work)
+{
+	struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
+						  reset_work);
+
+	amdgpu_device_gpu_recover_imp(adev, NULL);
+}
+
 #endif
 
 void amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
@@ -821,9 +833,12 @@ void amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
 	debugfs_create_file("amdgpu_fence_info", 0444, root, adev,
 			    &amdgpu_debugfs_fence_info_fops);
 
-	if (!amdgpu_sriov_vf(adev))
+	if (!amdgpu_sriov_vf(adev)) {
+
+		INIT_WORK(&adev->reset_work, amdgpu_debugfs_reset_work);
 		debugfs_create_file("amdgpu_gpu_recover", 0444, root, adev,
 				    &amdgpu_debugfs_gpu_recover_fops);
+	}
 #endif
 }
 
-- 
GitLab


From b5fd0cf3ea377a7332721df8a8c8e7715f93c8d4 Mon Sep 17 00:00:00 2001
From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Date: Tue, 17 May 2022 14:25:20 -0400
Subject: [PATCH 0462/1731] drm/amdgpu: Add work_struct for GPU reset from kfd.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

We need to have a work_struct to cancel this reset if another
already in progress.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 15 ++++++++++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 31 ----------------------
 3 files changed, 15 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 1f8161cd507f0..a23abc0e86e72 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -33,6 +33,7 @@
 #include <uapi/linux/kfd_ioctl.h>
 #include "amdgpu_ras.h"
 #include "amdgpu_umc.h"
+#include "amdgpu_reset.h"
 
 /* Total memory size in system memory and all GPU VRAM. Used to
  * estimate worst case amount of memory to reserve for page tables
@@ -122,6 +123,15 @@ static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
 	}
 }
 
+
+static void amdgpu_amdkfd_reset_work(struct work_struct *work)
+{
+	struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
+						  kfd.reset_work);
+
+	amdgpu_device_gpu_recover_imp(adev, NULL);
+}
+
 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
 {
 	int i;
@@ -180,6 +190,8 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
 
 		adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev,
 						adev_to_drm(adev), &gpu_resources);
+
+		INIT_WORK(&adev->kfd.reset_work, amdgpu_amdkfd_reset_work);
 	}
 }
 
@@ -247,7 +259,8 @@ int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev)
 {
 	if (amdgpu_device_should_recover_gpu(adev))
-		amdgpu_device_gpu_recover(adev, NULL);
+		amdgpu_reset_domain_schedule(adev->reset_domain,
+					     &adev->kfd.reset_work);
 }
 
 int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index bbe7d81bb0df8..ffb2b7d9b9a53 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -97,6 +97,7 @@ struct amdgpu_kfd_dev {
 	struct kfd_dev *dev;
 	uint64_t vram_used;
 	bool init_complete;
+	struct work_struct reset_work;
 };
 
 enum kgd_engine_type {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 6abec88cb5a87..2d490941e7275 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5323,37 +5323,6 @@ skip_sched_resume:
 	return r;
 }
 
-struct amdgpu_recover_work_struct {
-	struct work_struct base;
-	struct amdgpu_device *adev;
-	struct amdgpu_job *job;
-	int ret;
-};
-
-static void amdgpu_device_queue_gpu_recover_work(struct work_struct *work)
-{
-	struct amdgpu_recover_work_struct *recover_work = container_of(work, struct amdgpu_recover_work_struct, base);
-
-	amdgpu_device_gpu_recover_imp(recover_work->adev, recover_work->job);
-}
-/*
- * Serialize gpu recover into reset domain single threaded wq
- */
-int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
-				    struct amdgpu_job *job)
-{
-	struct amdgpu_recover_work_struct work = {.adev = adev, .job = job};
-
-	INIT_WORK(&work.base, amdgpu_device_queue_gpu_recover_work);
-
-	if (!amdgpu_reset_domain_schedule(adev->reset_domain, &work.base))
-		return -EAGAIN;
-
-	flush_work(&work.base);
-
-	return atomic_read(&adev->reset_domain->reset_res);
-}
-
 /**
  * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
  *
-- 
GitLab


From cf727044144d47c3e8482b9a7775bd3f04a87341 Mon Sep 17 00:00:00 2001
From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Date: Tue, 17 May 2022 14:27:49 -0400
Subject: [PATCH 0463/1731] drm/amdgpu: Rename amdgpu_device_gpu_recover_imp
 back to amdgpu_device_gpu_recover
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

We removed the wrapper that was queueing the recover function
into reset domain queue who was using this name.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c  | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c    | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c    | 2 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c      | 2 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c      | 2 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c      | 2 +-
 9 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ddb36c33b4bce..fb9399a999aef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1254,7 +1254,7 @@ bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
 			      struct amdgpu_job* job);
-int amdgpu_device_gpu_recover_imp(struct amdgpu_device *adev,
+int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
 			      struct amdgpu_job *job);
 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
 int amdgpu_device_pci_reset(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index a23abc0e86e72..513c57f839d81 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -129,7 +129,7 @@ static void amdgpu_amdkfd_reset_work(struct work_struct *work)
 	struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
 						  kfd.reset_work);
 
-	amdgpu_device_gpu_recover_imp(adev, NULL);
+	amdgpu_device_gpu_recover(adev, NULL);
 }
 
 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2d490941e7275..2d5a623598b81 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5076,7 +5076,7 @@ retry:
  * Returns 0 for success or an error on failure.
  */
 
-int amdgpu_device_gpu_recover_imp(struct amdgpu_device *adev,
+int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
 			      struct amdgpu_job *job)
 {
 	struct list_head device_list, *device_list_handle =  NULL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index b0498ffcf7c33..957437a5558c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -819,7 +819,7 @@ static void amdgpu_debugfs_reset_work(struct work_struct *work)
 	struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
 						  reset_work);
 
-	amdgpu_device_gpu_recover_imp(adev, NULL);
+	amdgpu_device_gpu_recover(adev, NULL);
 }
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 67f66f2f1809c..26ede765eed89 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -64,7 +64,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)
 		  ti.process_name, ti.tgid, ti.task_name, ti.pid);
 
 	if (amdgpu_device_should_recover_gpu(ring->adev)) {
-		r = amdgpu_device_gpu_recover_imp(ring->adev, job);
+		r = amdgpu_device_gpu_recover(ring->adev, job);
 		if (r)
 			DRM_ERROR("GPU Recovery Failed: %d\n", r);
 	} else {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index b3b5ebbae82fe..285534bfc084b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1939,7 +1939,7 @@ static void amdgpu_ras_do_recovery(struct work_struct *work)
 	}
 
 	if (amdgpu_device_should_recover_gpu(ras->adev))
-		amdgpu_device_gpu_recover_imp(ras->adev, NULL);
+		amdgpu_device_gpu_recover(ras->adev, NULL);
 	atomic_set(&ras->in_recovery, 0);
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
index b81acf59870c5..7ec5b5cf4bb94 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
@@ -284,7 +284,7 @@ flr_done:
 	if (amdgpu_device_should_recover_gpu(adev)
 		&& (!amdgpu_device_has_job_running(adev) ||
 		adev->sdma_timeout == MAX_SCHEDULE_TIMEOUT))
-		amdgpu_device_gpu_recover_imp(adev, NULL);
+		amdgpu_device_gpu_recover(adev, NULL);
 }
 
 static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
index 22c10b97ea81f..e18b75c8fde66 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
@@ -311,7 +311,7 @@ flr_done:
 		adev->gfx_timeout == MAX_SCHEDULE_TIMEOUT ||
 		adev->compute_timeout == MAX_SCHEDULE_TIMEOUT ||
 		adev->video_timeout == MAX_SCHEDULE_TIMEOUT))
-		amdgpu_device_gpu_recover_imp(adev, NULL);
+		amdgpu_device_gpu_recover(adev, NULL);
 }
 
 static int xgpu_nv_set_mailbox_rcv_irq(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
index 7b63d30b9b79e..c5016a9263317 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
@@ -523,7 +523,7 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct *work)
 
 	/* Trigger recovery due to world switch failure */
 	if (amdgpu_device_should_recover_gpu(adev))
-		amdgpu_device_gpu_recover_imp(adev, NULL);
+		amdgpu_device_gpu_recover(adev, NULL);
 }
 
 static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev,
-- 
GitLab


From 247c7b0dac3cf1141b8bf5520adf2fac1a797aa9 Mon Sep 17 00:00:00 2001
From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Date: Tue, 17 May 2022 14:56:34 -0400
Subject: [PATCH 0464/1731] drm/amdgpu: Stop any pending reset if another in
 progress.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

We skip rest requests if another one is already in progress.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 27 ++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2d5a623598b81..45dc96aee39ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5065,6 +5065,27 @@ retry:
 	}
 }
 
+static inline void amdggpu_device_stop_pedning_resets(struct amdgpu_device *adev)
+{
+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+
+#if defined(CONFIG_DEBUG_FS)
+	if (!amdgpu_sriov_vf(adev))
+		cancel_work(&adev->reset_work);
+#endif
+
+	if (adev->kfd.dev)
+		cancel_work(&adev->kfd.reset_work);
+
+	if (amdgpu_sriov_vf(adev))
+		cancel_work(&adev->virt.flr_work);
+
+	if (con && adev->ras_enabled)
+		cancel_work(&con->recovery_work);
+
+}
+
+
 /**
  * amdgpu_device_gpu_recover_imp - reset the asic and recover scheduler
  *
@@ -5220,6 +5241,12 @@ retry:	/* Rest of adevs pre asic reset from XGMI hive. */
 				  r, adev_to_drm(tmp_adev)->unique);
 			tmp_adev->asic_reset_res = r;
 		}
+
+		/*
+		 * Drop all pending non scheduler resets. Scheduler resets
+		 * were already dropped during drm_sched_stop
+		 */
+		amdggpu_device_stop_pedning_resets(tmp_adev);
 	}
 
 	tmp_vram_lost_counter = atomic_read(&((adev)->vram_lost_counter));
-- 
GitLab


From e3c60b4ef42d4db5b8d1434fa1741abd7f2fc850 Mon Sep 17 00:00:00 2001
From: Kenneth Feng <kenneth.feng@amd.com>
Date: Wed, 8 Jun 2022 16:40:14 +0800
Subject: [PATCH 0465/1731] drm/amd/pm: update the driver if header for
 smu_v13_0_7

update the driver if header for smu_v13_0_7

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../inc/pmfw_if/smu13_driver_if_v13_0_7.h     | 62 +++++++++++++------
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h  |  2 +-
 2 files changed, 45 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h
index d99b4b47d49d7..132da684e3799 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h
@@ -25,10 +25,10 @@
 
 // *** IMPORTANT ***
 // PMFW TEAM: Always increment the interface version on any change to this file
-#define SMU13_DRIVER_IF_VERSION  0x28
+#define SMU13_DRIVER_IF_VERSION  0x2A
 
 //Increment this version if SkuTable_t or BoardTable_t change
-#define PPTABLE_VERSION 0x1D
+#define PPTABLE_VERSION 0x1E
 
 #define NUM_GFXCLK_DPM_LEVELS    16
 #define NUM_SOCCLK_DPM_LEVELS    8
@@ -112,6 +112,22 @@
 #define FEATURE_SPARE_63_BIT                  63
 #define NUM_FEATURES                          64
 
+#define ALLOWED_FEATURE_CTRL_DEFAULT 0xFFFFFFFFFFFFFFFFULL
+#define ALLOWED_FEATURE_CTRL_SCPM        (1 << FEATURE_DPM_GFXCLK_BIT) | \
+                                         (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \
+                                         (1 << FEATURE_DPM_UCLK_BIT) | \
+                                         (1 << FEATURE_DPM_FCLK_BIT) | \
+                                         (1 << FEATURE_DPM_SOCCLK_BIT) | \
+                                         (1 << FEATURE_DPM_MP0CLK_BIT) | \
+                                         (1 << FEATURE_DPM_LINK_BIT) | \
+                                         (1 << FEATURE_DPM_DCN_BIT) | \
+                                         (1 << FEATURE_DS_GFXCLK_BIT) | \
+                                         (1 << FEATURE_DS_SOCCLK_BIT) | \
+                                         (1 << FEATURE_DS_FCLK_BIT) | \
+                                         (1 << FEATURE_DS_LCLK_BIT) | \
+                                         (1 << FEATURE_DS_DCFCLK_BIT) | \
+                                         (1 << FEATURE_DS_UCLK_BIT)
+
 //For use with feature control messages
 typedef enum {
   FEATURE_PWR_ALL,
@@ -662,7 +678,7 @@ typedef struct {
 #define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1
 
 
-#define PP_OD_FEATURE_VF_CURVE_BIT  0
+#define PP_OD_FEATURE_GFX_VF_CURVE_BIT  0
 #define PP_OD_FEATURE_VMAX_BIT      1
 #define PP_OD_FEATURE_PPT_BIT       2
 #define PP_OD_FEATURE_FAN_CURVE_BIT 3
@@ -671,6 +687,8 @@ typedef struct {
 #define PP_OD_FEATURE_TDC_BIT      6
 #define PP_OD_FEATURE_GFXCLK_BIT      7
 #define PP_OD_FEATURE_UCLK_BIT      8
+#define PP_OD_FEATURE_ZERO_FAN_BIT      9
+#define PP_OD_FEATURE_TEMPERATURE_BIT 10
 
 typedef enum {
   PP_OD_POWER_FEATURE_ALWAYS_ENABLED,
@@ -689,8 +707,8 @@ typedef struct {
   uint8_t                RuntimePwrSavingFeaturesCtrl;
 
   //Frequency changes
-  uint16_t               GfxclkFmin;           // MHz
-  uint16_t               GfxclkFmax;           // MHz
+  int16_t               GfxclkFmin;           // MHz
+  int16_t               GfxclkFmax;           // MHz
   uint16_t               UclkFmin;             // MHz
   uint16_t               UclkFmax;             // MHz
 
@@ -701,17 +719,17 @@ typedef struct {
   //Fan control
   uint8_t                FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS];
   uint8_t                FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS];
-  uint16_t               FanMaximumRpm;
   uint16_t               FanMinimumPwm;
-  uint16_t               FanAcousticLimitRpm;
+  uint16_t               AcousticTargetRpmThreshold;
+  uint16_t               AcousticLimitRpmThreshold;
   uint16_t               FanTargetTemperature; // Degree Celcius
   uint8_t                FanZeroRpmEnable;
   uint8_t                FanZeroRpmStopTemp;
   uint8_t                FanMode;
-  uint8_t                Padding[1];
-
+  uint8_t                MaxOpTemp;
+  uint8_t                Padding[4];
 
-  uint32_t               Spare[13];
+  uint32_t               Spare[12];
   uint32_t               MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround
 } OverDriveTable_t;
 
@@ -740,17 +758,17 @@ typedef struct {
 
   uint8_t                FanLinearPwmPoints;
   uint8_t                FanLinearTempPoints;
-  uint16_t               FanMaximumRpm;
   uint16_t               FanMinimumPwm;
-  uint16_t               FanAcousticLimitRpm;
+  uint16_t               AcousticTargetRpmThreshold;
+  uint16_t               AcousticLimitRpmThreshold;
   uint16_t               FanTargetTemperature; // Degree Celcius
   uint8_t                FanZeroRpmEnable;
   uint8_t                FanZeroRpmStopTemp;
   uint8_t                FanMode;
-  uint8_t                Padding[1];
+  uint8_t                MaxOpTemp;
+  uint8_t                Padding[4];
 
-
-  uint32_t               Spare[13];
+  uint32_t               Spare[12];
 
 } OverDriveLimits_t;
 
@@ -1018,7 +1036,8 @@ typedef struct {
   uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms
   uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms
 
-  uint32_t       SpareVmin[12];
+  QuadraticInt_t Vmin_droop;
+  uint32_t       SpareVmin[9];
 
 
   //SECTION: DPM Configuration 1
@@ -1307,7 +1326,6 @@ typedef struct {
   uint32_t    PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued
   uint32_t    BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS
 
-
   // SECTION: Board Reserved
   uint32_t     BoardSpare[64];
 
@@ -1382,8 +1400,14 @@ typedef struct {
   uint16_t AverageDclk0Frequency  ;
   uint16_t AverageVclk1Frequency  ;
   uint16_t AverageDclk1Frequency  ;
+  uint16_t PCIeBusy               ;
+  uint16_t dGPU_W_MAX             ;
+  uint16_t padding                ;
+
+  uint32_t MetricsCounter         ;
 
   uint16_t AvgVoltage[SVI_PLANE_COUNT];
+  uint16_t AvgCurrent[SVI_PLANE_COUNT];
 
   uint16_t AverageGfxActivity    ;
   uint16_t AverageUclkActivity   ;
@@ -1415,11 +1439,13 @@ typedef struct {
 
   uint16_t AverageUclkActivity_MAX;
 
+  uint32_t PublicSerialNumberLower;
+  uint32_t PublicSerialNumberUpper;
 } SmuMetrics_t;
 
 typedef struct {
   SmuMetrics_t SmuMetrics;
-  uint32_t Spare[32];
+  uint32_t Spare[30];
 
   // Padding - ignore
   uint32_t     MmHubPadding[8]; // SMU internal use
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index a11d36db1b8a0..e3454a876cacd 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -31,7 +31,7 @@
 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x04
 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04
 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x29
-#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x28
+#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x2A
 
 #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500  //500ms
 
-- 
GitLab


From 5d6ec040ab44d23953a2efebfe02e41337952be7 Mon Sep 17 00:00:00 2001
From: Kenneth Feng <kenneth.feng@amd.com>
Date: Wed, 8 Jun 2022 16:59:52 +0800
Subject: [PATCH 0466/1731] drm/amd/pm: enable gfxoff on smu_v13_0_7

enable gfxoff on smu_v13_0_7

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index dc614befcdf5b..b635c2b4f81ca 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -249,6 +249,9 @@ smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu,
 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT);
 	}
 
+	if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
+
 	if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) {
 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT);
-- 
GitLab


From 7fc83cd079bba8b96b0f46e31f26c8f31c814146 Mon Sep 17 00:00:00 2001
From: Kenneth Feng <kenneth.feng@amd.com>
Date: Wed, 1 Jun 2022 09:20:28 +0800
Subject: [PATCH 0467/1731] drm/amd/pm: support BAMACO reset on smu_v13_0_7

support BAMACO reset on smu_v13_0_7, take BAMACO as a subset of BACO
for the low latency, and it only happens on specific platforms.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  1 +
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  | 57 ++++++++++++++++++-
 2 files changed, 56 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 6d51e4340aadc..b81c657c73860 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -432,6 +432,7 @@ struct smu_baco_context
 {
 	uint32_t state;
 	bool platform_support;
+	bool maco_support;
 };
 
 struct smu_freq_info {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index b635c2b4f81ca..a92ab32660919 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -303,6 +303,8 @@ static int smu_v13_0_7_check_powerplay_table(struct smu_context *smu)
 	struct smu_13_0_7_powerplay_table *powerplay_table =
 		table_context->power_play_table;
 	struct smu_baco_context *smu_baco = &smu->smu_baco;
+	PPTable_t *smc_pptable = table_context->driver_pptable;
+	BoardTable_t *BoardTable = &smc_pptable->BoardTable;
 
 	if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_HARDWAREDC)
 		smu->dc_controlled_by_gpio = true;
@@ -311,6 +313,9 @@ static int smu_v13_0_7_check_powerplay_table(struct smu_context *smu)
 	    powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO)
 		smu_baco->platform_support = true;
 
+	if (smu_baco->platform_support && (BoardTable->HsrEnabled || BoardTable->VddqOffEnabled))
+		smu_baco->maco_support = true;
+
 	table_context->thermal_controller_type =
 		powerplay_table->thermal_controller_type;
 
@@ -1537,6 +1542,54 @@ static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *inp
 	return ret;
 }
 
+static int smu_v13_0_7_baco_set_state(struct smu_context *smu,
+			     enum smu_baco_state state)
+{
+	struct smu_baco_context *smu_baco = &smu->smu_baco;
+	struct amdgpu_device *adev = smu->adev;
+	bool is_maco_support = smu_baco->maco_support;
+	int ret;
+
+	if (smu_v13_0_baco_get_state(smu) == state)
+		return 0;
+
+	if (state == SMU_BACO_STATE_ENTER) {
+		ret = smu_cmn_send_smc_msg_with_param(smu,
+						      SMU_MSG_EnterBaco,
+						      (is_maco_support ? 2 : 0),
+						      NULL);
+	} else {
+		ret = smu_cmn_send_smc_msg(smu,
+					   SMU_MSG_ExitBaco,
+					   NULL);
+		if (ret)
+			return ret;
+
+		/* clear vbios scratch 6 and 7 for coming asic reinit */
+		WREG32(adev->bios_scratch_reg_offset + 6, 0);
+		WREG32(adev->bios_scratch_reg_offset + 7, 0);
+	}
+
+	if (!ret)
+		smu_baco->state = state;
+
+	return ret;
+}
+
+static int smu_v13_0_7_baco_enter(struct smu_context *smu)
+{
+	int ret = 0;
+
+	ret = smu_v13_0_7_baco_set_state(smu,
+				       SMU_BACO_STATE_ENTER);
+	if (ret)
+		return ret;
+
+	msleep(10);
+
+	return ret;
+}
+
 static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
 	.get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask,
 	.set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,
@@ -1591,8 +1644,8 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
 	.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
 	.baco_is_support = smu_v13_0_baco_is_support,
 	.baco_get_state = smu_v13_0_baco_get_state,
-	.baco_set_state = smu_v13_0_baco_set_state,
-	.baco_enter = smu_v13_0_baco_enter,
+	.baco_set_state = smu_v13_0_7_baco_set_state,
+	.baco_enter = smu_v13_0_7_baco_enter,
 	.baco_exit = smu_v13_0_baco_exit,
 };
 
-- 
GitLab


From c349ae5f831cb9817a45e4e36705d2f7d47c7bc3 Mon Sep 17 00:00:00 2001
From: Xin Long <lucien.xin@gmail.com>
Date: Thu, 9 Jun 2022 11:17:13 -0400
Subject: [PATCH 0468/1731] Documentation: add description for
 net.sctp.reconf_enable

Describe it in networking/ip-sysctl.rst like other SCTP options.

Fixes: c0d8bab6ae51 ("sctp: add get and set sockopt for reconf_enable")
Signed-off-by: Xin Long <lucien.xin@gmail.com>
Acked-by: Marcelo Ricardo Leitner <marcelo.leitner@gmail.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 Documentation/networking/ip-sysctl.rst | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/Documentation/networking/ip-sysctl.rst b/Documentation/networking/ip-sysctl.rst
index 04216564a03cb..aebf87b19fba6 100644
--- a/Documentation/networking/ip-sysctl.rst
+++ b/Documentation/networking/ip-sysctl.rst
@@ -2925,6 +2925,17 @@ plpmtud_probe_interval - INTEGER
 
 	Default: 0
 
+reconf_enable - BOOLEAN
+        Enable or disable extension of Stream Reconfiguration functionality
+        specified in RFC6525. This extension provides the ability to "reset"
+        a stream, and it includes the Parameters of "Outgoing/Incoming SSN
+        Reset", "SSN/TSN Reset" and "Add Outgoing/Incoming Streams".
+
+	- 1: Enable extension.
+	- 0: Disable extension.
+
+	Default: 0
+
 
 ``/proc/sys/net/core/*``
 ========================
-- 
GitLab


From e65775fdd389e4f47eb1972ef6372e20c6c2cc05 Mon Sep 17 00:00:00 2001
From: Xin Long <lucien.xin@gmail.com>
Date: Thu, 9 Jun 2022 11:17:14 -0400
Subject: [PATCH 0469/1731] Documentation: add description for
 net.sctp.intl_enable

Describe it in networking/ip-sysctl.rst like other SCTP options.
We need to document this especially as when using the feature
of User Message Interleaving, some socket options also needs
to be set.

Fixes: 463118c34a35 ("sctp: support sysctl to allow users to use stream interleave")
Signed-off-by: Xin Long <lucien.xin@gmail.com>
Acked-by: Marcelo Ricardo Leitner <marcelo.leitner@gmail.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 Documentation/networking/ip-sysctl.rst | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/Documentation/networking/ip-sysctl.rst b/Documentation/networking/ip-sysctl.rst
index aebf87b19fba6..5fe837505d430 100644
--- a/Documentation/networking/ip-sysctl.rst
+++ b/Documentation/networking/ip-sysctl.rst
@@ -2936,6 +2936,20 @@ reconf_enable - BOOLEAN
 
 	Default: 0
 
+intl_enable - BOOLEAN
+        Enable or disable extension of User Message Interleaving functionality
+        specified in RFC8260. This extension allows the interleaving of user
+        messages sent on different streams. With this feature enabled, I-DATA
+        chunk will replace DATA chunk to carry user messages if also supported
+        by the peer. Note that to use this feature, one needs to set this option
+        to 1 and also needs to set socket options SCTP_FRAGMENT_INTERLEAVE to 2
+        and SCTP_INTERLEAVING_SUPPORTED to 1.
+
+	- 1: Enable extension.
+	- 0: Disable extension.
+
+	Default: 0
+
 
 ``/proc/sys/net/core/*``
 ========================
-- 
GitLab


From 249eddaf651fda7cb32e9ebae4c6d5904b390d81 Mon Sep 17 00:00:00 2001
From: Xin Long <lucien.xin@gmail.com>
Date: Thu, 9 Jun 2022 11:17:15 -0400
Subject: [PATCH 0470/1731] Documentation: add description for
 net.sctp.ecn_enable

Describe it in networking/ip-sysctl.rst like other SCTP options.

Fixes: 2f5268a9249b ("sctp: allow users to set netns ecn flag with sysctl")
Signed-off-by: Xin Long <lucien.xin@gmail.com>
Acked-by: Marcelo Ricardo Leitner <marcelo.leitner@gmail.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 Documentation/networking/ip-sysctl.rst | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Documentation/networking/ip-sysctl.rst b/Documentation/networking/ip-sysctl.rst
index 5fe837505d430..9f41961d11d52 100644
--- a/Documentation/networking/ip-sysctl.rst
+++ b/Documentation/networking/ip-sysctl.rst
@@ -2950,6 +2950,18 @@ intl_enable - BOOLEAN
 
 	Default: 0
 
+ecn_enable - BOOLEAN
+        Control use of Explicit Congestion Notification (ECN) by SCTP.
+        Like in TCP, ECN is used only when both ends of the SCTP connection
+        indicate support for it. This feature is useful in avoiding losses
+        due to congestion by allowing supporting routers to signal congestion
+        before having to drop packets.
+
+        1: Enable ecn.
+        0: Disable ecn.
+
+        Default: 1
+
 
 ``/proc/sys/net/core/*``
 ========================
-- 
GitLab


From fe0fde09e1cb83effcf8fafa372533f438d93a1a Mon Sep 17 00:00:00 2001
From: Namjae Jeon <linkinjeon@kernel.org>
Date: Thu, 2 Jun 2022 10:07:38 +0900
Subject: [PATCH 0471/1731] ksmbd: use SOCK_NONBLOCK type for kernel_accept()

I found that normally it is O_NONBLOCK but there are different value
for some arch.

/include/linux/net.h:
#ifndef SOCK_NONBLOCK
#define SOCK_NONBLOCK   O_NONBLOCK
#endif

/arch/alpha/include/asm/socket.h:
#define SOCK_NONBLOCK   0x40000000

Use SOCK_NONBLOCK instead of O_NONBLOCK for kernel_accept().

Suggested-by: David Howells <dhowells@redhat.com>
Signed-off-by: Namjae Jeon <linkinjeon@kerne.org>
Reviewed-by: Hyunchul Lee <hyc.lee@gmail.com>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/ksmbd/transport_tcp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/ksmbd/transport_tcp.c b/fs/ksmbd/transport_tcp.c
index 8fef9de787d34..143bba4e4db81 100644
--- a/fs/ksmbd/transport_tcp.c
+++ b/fs/ksmbd/transport_tcp.c
@@ -230,7 +230,7 @@ static int ksmbd_kthread_fn(void *p)
 			break;
 		}
 		ret = kernel_accept(iface->ksmbd_socket, &client_sk,
-				    O_NONBLOCK);
+				    SOCK_NONBLOCK);
 		mutex_unlock(&iface->sock_release_lock);
 		if (ret) {
 			if (ret == -EAGAIN)
-- 
GitLab


From 06ee1c0aebd5dfdf6bf237165b22415f64f38b7c Mon Sep 17 00:00:00 2001
From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Date: Sat, 11 Jun 2022 10:32:44 +0200
Subject: [PATCH 0472/1731] ksmbd: smbd: Remove useless license text when
 SPDX-License-Identifier is already used

An SPDX-License-Identifier is already in place. There is no need to
duplicate part of the corresponding license.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Acked-by: Namjae Jeon <linkinjeon@kernel.org>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/ksmbd/transport_rdma.c | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/fs/ksmbd/transport_rdma.c b/fs/ksmbd/transport_rdma.c
index d035e060c2f0a..35b55ee94fe54 100644
--- a/fs/ksmbd/transport_rdma.c
+++ b/fs/ksmbd/transport_rdma.c
@@ -5,16 +5,6 @@
  *
  *   Author(s): Long Li <longli@microsoft.com>,
  *		Hyunchul Lee <hyc.lee@gmail.com>
- *
- *   This program is free software;  you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY;  without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
- *   the GNU General Public License for more details.
  */
 
 #define SUBMOD_NAME	"smb_direct"
-- 
GitLab


From abfed87e2a12bd246047d78c01d81eb9529f1d06 Mon Sep 17 00:00:00 2001
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
Date: Sat, 28 May 2022 12:24:29 +0200
Subject: [PATCH 0473/1731] crypto: memneq - move into lib/

This is used by code that doesn't need CONFIG_CRYPTO, so move this into
lib/ with a Kconfig option so that it can be selected by whatever needs
it.

This fixes a linker error Zheng pointed out when
CRYPTO_MANAGER_DISABLE_TESTS!=y and CRYPTO=m:

  lib/crypto/curve25519-selftest.o: In function `curve25519_selftest':
  curve25519-selftest.c:(.init.text+0x60): undefined reference to `__crypto_memneq'
  curve25519-selftest.c:(.init.text+0xec): undefined reference to `__crypto_memneq'
  curve25519-selftest.c:(.init.text+0x114): undefined reference to `__crypto_memneq'
  curve25519-selftest.c:(.init.text+0x154): undefined reference to `__crypto_memneq'

Reported-by: Zheng Bin <zhengbin13@huawei.com>
Cc: Eric Biggers <ebiggers@kernel.org>
Cc: stable@vger.kernel.org
Fixes: aa127963f1ca ("crypto: lib/curve25519 - re-add selftests")
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
---
 crypto/Kconfig           | 1 +
 crypto/Makefile          | 2 +-
 lib/Kconfig              | 3 +++
 lib/Makefile             | 1 +
 lib/crypto/Kconfig       | 1 +
 {crypto => lib}/memneq.c | 0
 6 files changed, 7 insertions(+), 1 deletion(-)
 rename {crypto => lib}/memneq.c (100%)

diff --git a/crypto/Kconfig b/crypto/Kconfig
index 19197469cfab3..1d44893a997ba 100644
--- a/crypto/Kconfig
+++ b/crypto/Kconfig
@@ -15,6 +15,7 @@ source "crypto/async_tx/Kconfig"
 #
 menuconfig CRYPTO
 	tristate "Cryptographic API"
+	select LIB_MEMNEQ
 	help
 	  This option provides the core Cryptographic API.
 
diff --git a/crypto/Makefile b/crypto/Makefile
index 43bc33e247d19..ceaaa9f34145a 100644
--- a/crypto/Makefile
+++ b/crypto/Makefile
@@ -4,7 +4,7 @@
 #
 
 obj-$(CONFIG_CRYPTO) += crypto.o
-crypto-y := api.o cipher.o compress.o memneq.o
+crypto-y := api.o cipher.o compress.o
 
 obj-$(CONFIG_CRYPTO_ENGINE) += crypto_engine.o
 obj-$(CONFIG_CRYPTO_FIPS) += fips.o
diff --git a/lib/Kconfig b/lib/Kconfig
index 6a843639814fb..eaaad4d85bf24 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -120,6 +120,9 @@ config INDIRECT_IOMEM_FALLBACK
 
 source "lib/crypto/Kconfig"
 
+config LIB_MEMNEQ
+	bool
+
 config CRC_CCITT
 	tristate "CRC-CCITT functions"
 	help
diff --git a/lib/Makefile b/lib/Makefile
index ea54294d73bf4..f99bf61f8bbc6 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -251,6 +251,7 @@ obj-$(CONFIG_DIMLIB) += dim/
 obj-$(CONFIG_SIGNATURE) += digsig.o
 
 lib-$(CONFIG_CLZ_TAB) += clz_tab.o
+lib-$(CONFIG_LIB_MEMNEQ) += memneq.o
 
 obj-$(CONFIG_GENERIC_STRNCPY_FROM_USER) += strncpy_from_user.o
 obj-$(CONFIG_GENERIC_STRNLEN_USER) += strnlen_user.o
diff --git a/lib/crypto/Kconfig b/lib/crypto/Kconfig
index 9856e291f4141..2082af43d51fb 100644
--- a/lib/crypto/Kconfig
+++ b/lib/crypto/Kconfig
@@ -71,6 +71,7 @@ config CRYPTO_LIB_CURVE25519
 	tristate "Curve25519 scalar multiplication library"
 	depends on CRYPTO_ARCH_HAVE_LIB_CURVE25519 || !CRYPTO_ARCH_HAVE_LIB_CURVE25519
 	select CRYPTO_LIB_CURVE25519_GENERIC if CRYPTO_ARCH_HAVE_LIB_CURVE25519=n
+	select LIB_MEMNEQ
 	help
 	  Enable the Curve25519 library interface. This interface may be
 	  fulfilled by either the generic implementation or an arch-specific
diff --git a/crypto/memneq.c b/lib/memneq.c
similarity index 100%
rename from crypto/memneq.c
rename to lib/memneq.c
-- 
GitLab


From 5e757deddd918edb8cb2fdb56eb79656ffc6dade Mon Sep 17 00:00:00 2001
From: Conor Dooley <conor.dooley@microchip.com>
Date: Fri, 3 Jun 2022 09:38:26 +0100
Subject: [PATCH 0474/1731] riscv: dts: microchip: re-add pdma to mpfs device
 tree

PolarFire SoC /does/ have a SiFive pdma, despite what I suggested as a
conflict resolution to Zong. Somehow the entry fell through the cracks
between versions of my dt patches, so re-add it with Zong's updated
compatible & dma-channels property.

Fixes: c5094f371008 ("riscv: dts: microchip: refactor icicle kit device tree")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/microchip/mpfs.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 8c32591341942..3095d08453a11 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -192,6 +192,15 @@
 			riscv,ndev = <186>;
 		};
 
+		pdma: dma-controller@3000000 {
+			compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
+			reg = <0x0 0x3000000 0x0 0x8000>;
+			interrupt-parent = <&plic>;
+			interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
+			dma-channels = <4>;
+			#dma-cells = <1>;
+		};
+
 		clkcfg: clkcfg@20002000 {
 			compatible = "microchip,mpfs-clkcfg";
 			reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
-- 
GitLab


From 44dbdf3bb3f44bf08897ed5f22eb262edcf3d926 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ludvig=20P=C3=A4rsson?= <ludvig.parsson@axis.com>
Date: Fri, 10 Jun 2022 16:00:55 +0200
Subject: [PATCH 0475/1731] firmware: arm_scmi: Fix incorrect error propagation
 in scmi_voltage_descriptors_get
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

scmi_voltage_descriptors_get() will incorrecly return an error code if
the last iteration of the for loop that retrieves the descriptors is
skipped due to an error. Skipping an iteration in the loop is not an
error, but the `ret` value from the last iteration will be propagated
when the function returns.

Fix by not saving return values that should not be propagated. This
solution also minimizes the risk of future patches accidentally
re-introducing this bug.

Link: https://lore.kernel.org/r/20220610140055.31491-1-ludvig.parsson@axis.com
Reviewed-by: Cristian Marussi <cristian.marussi@arm.com>
Signed-off-by: Ludvig Pärsson <ludvig.parsson@axis.com>
[sudeep.holla: Removed unneeded reset_rx_to_maxsz and check for return
value from scmi_voltage_levels_get as suggested by Cristian]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
 drivers/firmware/arm_scmi/voltage.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/firmware/arm_scmi/voltage.c b/drivers/firmware/arm_scmi/voltage.c
index 5de93f637bd47..eaa8d944926a3 100644
--- a/drivers/firmware/arm_scmi/voltage.c
+++ b/drivers/firmware/arm_scmi/voltage.c
@@ -225,9 +225,8 @@ static int scmi_voltage_descriptors_get(const struct scmi_protocol_handle *ph,
 
 		/* Retrieve domain attributes at first ... */
 		put_unaligned_le32(dom, td->tx.buf);
-		ret = ph->xops->do_xfer(ph, td);
 		/* Skip domain on comms error */
-		if (ret)
+		if (ph->xops->do_xfer(ph, td))
 			continue;
 
 		v = vinfo->domains + dom;
@@ -249,12 +248,8 @@ static int scmi_voltage_descriptors_get(const struct scmi_protocol_handle *ph,
 				v->async_level_set = true;
 		}
 
-		ret = scmi_voltage_levels_get(ph, v);
 		/* Skip invalid voltage descriptors */
-		if (ret)
-			continue;
-
-		ph->xops->reset_rx_to_maxsz(ph, td);
+		scmi_voltage_levels_get(ph, v);
 	}
 
 	ph->xops->xfer_put(ph, td);
-- 
GitLab


From 3ddbe35d9a2ebd4924d458e0246b4ba6c13bb456 Mon Sep 17 00:00:00 2001
From: Daniil Dementev <d.dementev@ispras.ru>
Date: Fri, 10 Jun 2022 19:57:32 +0300
Subject: [PATCH 0476/1731] ALSA: usb-audio: US16x08: Move overflow check
 before array access

Buffer overflow could occur in the loop "while", due to accessing an
array element before checking the index.

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Signed-off-by: Daniil Dementev <d.dementev@ispras.ru>
Reviewed-by: Alexey Khoroshilov <khoroshilov@ispras.ru>
Link: https://lore.kernel.org/r/20220610165732.2904-1-d.dementev@ispras.ru
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/usb/mixer_us16x08.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/sound/usb/mixer_us16x08.c b/sound/usb/mixer_us16x08.c
index b7b6f3834ed5e..6eb7d93b358d9 100644
--- a/sound/usb/mixer_us16x08.c
+++ b/sound/usb/mixer_us16x08.c
@@ -637,10 +637,10 @@ static int snd_get_meter_comp_index(struct snd_us16x08_meter_store *store)
 		}
 	} else {
 		/* skip channels with no compressor active */
-		while (!store->comp_store->val[
+		while (store->comp_index <= SND_US16X08_MAX_CHANNELS
+			&& !store->comp_store->val[
 			COMP_STORE_IDX(SND_US16X08_ID_COMP_SWITCH)]
-			[store->comp_index - 1]
-			&& store->comp_index <= SND_US16X08_MAX_CHANNELS) {
+			[store->comp_index - 1]) {
 			store->comp_index++;
 		}
 		ret = store->comp_index++;
-- 
GitLab


From e32683c6f7d22ba624e0bfc58b02cf3348bdca63 Mon Sep 17 00:00:00 2001
From: Josh Poimboeuf <jpoimboe@kernel.org>
Date: Thu, 9 Jun 2022 00:17:32 -0700
Subject: [PATCH 0477/1731] x86/mm: Fix RESERVE_BRK() for older binutils

With binutils 2.26, RESERVE_BRK() causes a build failure:

  /tmp/ccnGOKZ5.s: Assembler messages:
  /tmp/ccnGOKZ5.s:98: Error: missing ')'
  /tmp/ccnGOKZ5.s:98: Error: missing ')'
  /tmp/ccnGOKZ5.s:98: Error: missing ')'
  /tmp/ccnGOKZ5.s:98: Error: junk at end of line, first unrecognized
  character is `U'

The problem is this line:

  RESERVE_BRK(early_pgt_alloc, INIT_PGT_BUF_SIZE)

Specifically, the INIT_PGT_BUF_SIZE macro which (via PAGE_SIZE's use
_AC()) has a "1UL", which makes older versions of the assembler unhappy.
Unfortunately the _AC() macro doesn't work for inline asm.

Inline asm was only needed here to convince the toolchain to add the
STT_NOBITS flag.  However, if a C variable is placed in a section whose
name is prefixed with ".bss", GCC and Clang automatically set
STT_NOBITS.  In fact, ".bss..page_aligned" already relies on this trick.

So fix the build failure (and simplify the macro) by allocating the
variable in C.

Also, add NOLOAD to the ".brk" output section clause in the linker
script.  This is a failsafe in case the ".bss" prefix magic trick ever
stops working somehow.  If there's a section type mismatch, the GNU
linker will force the ".brk" output section to be STT_NOBITS.  The LLVM
linker will fail with a "section type mismatch" error.

Note this also changes the name of the variable from .brk.##name to
__brk_##name.  The variable names aren't actually used anywhere, so it's
harmless.

Fixes: a1e2c031ec39 ("x86/mm: Simplify RESERVE_BRK()")
Reported-by: Joe Damato <jdamato@fastly.com>
Reported-by: Byungchul Park <byungchul.park@lge.com>
Signed-off-by: Josh Poimboeuf <jpoimboe@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: Joe Damato <jdamato@fastly.com>
Link: https://lore.kernel.org/r/22d07a44c80d8e8e1e82b9a806ddc8c6bbb2606e.1654759036.git.jpoimboe@kernel.org
---
 arch/x86/include/asm/setup.h  | 38 +++++++++++++++++++----------------
 arch/x86/kernel/setup.c       |  5 -----
 arch/x86/kernel/vmlinux.lds.S |  4 ++--
 3 files changed, 23 insertions(+), 24 deletions(-)

diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h
index 7590ac2570b96..f8b9ee97a8913 100644
--- a/arch/x86/include/asm/setup.h
+++ b/arch/x86/include/asm/setup.h
@@ -108,19 +108,16 @@ extern unsigned long _brk_end;
 void *extend_brk(size_t size, size_t align);
 
 /*
- * Reserve space in the brk section.  The name must be unique within the file,
- * and somewhat descriptive.  The size is in bytes.
+ * Reserve space in the .brk section, which is a block of memory from which the
+ * caller is allowed to allocate very early (before even memblock is available)
+ * by calling extend_brk().  All allocated memory will be eventually converted
+ * to memblock.  Any leftover unallocated memory will be freed.
  *
- * The allocation is done using inline asm (rather than using a section
- * attribute on a normal variable) in order to allow the use of @nobits, so
- * that it doesn't take up any space in the vmlinux file.
+ * The size is in bytes.
  */
-#define RESERVE_BRK(name, size)						\
-	asm(".pushsection .brk_reservation,\"aw\",@nobits\n\t"		\
-	    ".brk." #name ":\n\t"					\
-	    ".skip " __stringify(size) "\n\t"				\
-	    ".size .brk." #name ", " __stringify(size) "\n\t"		\
-	    ".popsection\n\t")
+#define RESERVE_BRK(name, size)					\
+	__section(".bss..brk") __aligned(1) __used	\
+	static char __brk_##name[size]
 
 extern void probe_roms(void);
 #ifdef __i386__
@@ -133,12 +130,19 @@ asmlinkage void __init x86_64_start_reservations(char *real_mode_data);
 
 #endif /* __i386__ */
 #endif /* _SETUP */
-#else
-#define RESERVE_BRK(name,sz)				\
-	.pushsection .brk_reservation,"aw",@nobits;	\
-.brk.name:						\
-1:	.skip sz;					\
-	.size .brk.name,.-1b;				\
+
+#else  /* __ASSEMBLY */
+
+.macro __RESERVE_BRK name, size
+	.pushsection .bss..brk, "aw"
+SYM_DATA_START(__brk_\name)
+	.skip \size
+SYM_DATA_END(__brk_\name)
 	.popsection
+.endm
+
+#define RESERVE_BRK(name, size) __RESERVE_BRK name, size
+
 #endif /* __ASSEMBLY__ */
+
 #endif /* _ASM_X86_SETUP_H */
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 3ebb85327edb1..bd6c6fd373aee 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -67,11 +67,6 @@ RESERVE_BRK(dmi_alloc, 65536);
 #endif
 
 
-/*
- * Range of the BSS area. The size of the BSS area is determined
- * at link time, with RESERVE_BRK() facility reserving additional
- * chunks.
- */
 unsigned long _brk_start = (unsigned long)__brk_base;
 unsigned long _brk_end   = (unsigned long)__brk_base;
 
diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S
index f5f6dc2e80072..81aba718ecd56 100644
--- a/arch/x86/kernel/vmlinux.lds.S
+++ b/arch/x86/kernel/vmlinux.lds.S
@@ -385,10 +385,10 @@ SECTIONS
 	__end_of_kernel_reserve = .;
 
 	. = ALIGN(PAGE_SIZE);
-	.brk : AT(ADDR(.brk) - LOAD_OFFSET) {
+	.brk (NOLOAD) : AT(ADDR(.brk) - LOAD_OFFSET) {
 		__brk_base = .;
 		. += 64 * 1024;		/* 64k alignment slop space */
-		*(.brk_reservation)	/* areas brk users have reserved */
+		*(.bss..brk)		/* areas brk users have reserved */
 		__brk_limit = .;
 	}
 
-- 
GitLab


From 04193d590b390ec7a0592630f46d559ec6564ba1 Mon Sep 17 00:00:00 2001
From: Peter Zijlstra <peterz@infradead.org>
Date: Tue, 7 Jun 2022 22:41:55 +0200
Subject: [PATCH 0478/1731] sched: Fix balance_push() vs __sched_setscheduler()

The purpose of balance_push() is to act as a filter on task selection
in the case of CPU hotplug, specifically when taking the CPU out.

It does this by (ab)using the balance callback infrastructure, with
the express purpose of keeping all the unlikely/odd cases in a single
place.

In order to serve its purpose, the balance_push_callback needs to be
(exclusively) on the callback list at all times (noting that the
callback always places itself back on the list the moment it runs,
also noting that when the CPU goes down, regular balancing concerns
are moot, so ignoring them is fine).

And here-in lies the problem, __sched_setscheduler()'s use of
splice_balance_callbacks() takes the callbacks off the list across a
lock-break, making it possible for, an interleaving, __schedule() to
see an empty list and not get filtered.

Fixes: ae7927023243 ("sched: Optimize finish_lock_switch()")
Reported-by: Jing-Ting Wu <jing-ting.wu@mediatek.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: Jing-Ting Wu <jing-ting.wu@mediatek.com>
Link: https://lkml.kernel.org/r/20220519134706.GH2578@worktop.programming.kicks-ass.net
---
 kernel/sched/core.c  | 36 +++++++++++++++++++++++++++++++++---
 kernel/sched/sched.h |  5 +++++
 2 files changed, 38 insertions(+), 3 deletions(-)

diff --git a/kernel/sched/core.c b/kernel/sched/core.c
index bfa7452ca92e7..da0bf6fe9ecdc 100644
--- a/kernel/sched/core.c
+++ b/kernel/sched/core.c
@@ -4798,25 +4798,55 @@ static void do_balance_callbacks(struct rq *rq, struct callback_head *head)
 
 static void balance_push(struct rq *rq);
 
+/*
+ * balance_push_callback is a right abuse of the callback interface and plays
+ * by significantly different rules.
+ *
+ * Where the normal balance_callback's purpose is to be ran in the same context
+ * that queued it (only later, when it's safe to drop rq->lock again),
+ * balance_push_callback is specifically targeted at __schedule().
+ *
+ * This abuse is tolerated because it places all the unlikely/odd cases behind
+ * a single test, namely: rq->balance_callback == NULL.
+ */
 struct callback_head balance_push_callback = {
 	.next = NULL,
 	.func = (void (*)(struct callback_head *))balance_push,
 };
 
-static inline struct callback_head *splice_balance_callbacks(struct rq *rq)
+static inline struct callback_head *
+__splice_balance_callbacks(struct rq *rq, bool split)
 {
 	struct callback_head *head = rq->balance_callback;
 
+	if (likely(!head))
+		return NULL;
+
 	lockdep_assert_rq_held(rq);
-	if (head)
+	/*
+	 * Must not take balance_push_callback off the list when
+	 * splice_balance_callbacks() and balance_callbacks() are not
+	 * in the same rq->lock section.
+	 *
+	 * In that case it would be possible for __schedule() to interleave
+	 * and observe the list empty.
+	 */
+	if (split && head == &balance_push_callback)
+		head = NULL;
+	else
 		rq->balance_callback = NULL;
 
 	return head;
 }
 
+static inline struct callback_head *splice_balance_callbacks(struct rq *rq)
+{
+	return __splice_balance_callbacks(rq, true);
+}
+
 static void __balance_callbacks(struct rq *rq)
 {
-	do_balance_callbacks(rq, splice_balance_callbacks(rq));
+	do_balance_callbacks(rq, __splice_balance_callbacks(rq, false));
 }
 
 static inline void balance_callbacks(struct rq *rq, struct callback_head *head)
diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h
index 01259611beb94..47b89a0fc6e55 100644
--- a/kernel/sched/sched.h
+++ b/kernel/sched/sched.h
@@ -1693,6 +1693,11 @@ queue_balance_callback(struct rq *rq,
 {
 	lockdep_assert_rq_held(rq);
 
+	/*
+	 * Don't (re)queue an already queued item; nor queue anything when
+	 * balance_push() is active, see the comment with
+	 * balance_push_callback.
+	 */
 	if (unlikely(head->next || rq->balance_callback == &balance_push_callback))
 		return;
 
-- 
GitLab


From 4051a81774d6d8e28192742c26999d6f29bc0e68 Mon Sep 17 00:00:00 2001
From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date: Tue, 17 May 2022 11:16:14 +0200
Subject: [PATCH 0479/1731] locking/lockdep: Use sched_clock() for random
 numbers

Since the rewrote of prandom_u32(), in the commit mentioned below, the
function uses sleeping locks which extracing random numbers and filling
the batch.
This breaks lockdep on PREEMPT_RT because lock_pin_lock() disables
interrupts while calling __lock_pin_lock(). This can't be moved earlier
because the main user of the function (rq_pin_lock()) invokes that
function after disabling interrupts in order to acquire the lock.

The cookie does not require random numbers as its goal is to provide a
random value in order to notice unexpected "unlock + lock" sites.

Use sched_clock() to provide random numbers.

Fixes: a0103f4d86f88 ("random32: use real rng for non-deterministic randomness")
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/YoNn3pTkm5+QzE5k@linutronix.de
---
 kernel/locking/lockdep.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/locking/lockdep.c b/kernel/locking/lockdep.c
index 81e87280513ea..f06b91ca6482d 100644
--- a/kernel/locking/lockdep.c
+++ b/kernel/locking/lockdep.c
@@ -5432,7 +5432,7 @@ static struct pin_cookie __lock_pin_lock(struct lockdep_map *lock)
 			 * be guessable and still allows some pin nesting in
 			 * our u32 pin_count.
 			 */
-			cookie.val = 1 + (prandom_u32() >> 16);
+			cookie.val = 1 + (sched_clock() & 0xffff);
 			hlock->pin_count += cookie.val;
 			return cookie;
 		}
-- 
GitLab


From b0380bf6dad4601d92025841e2b7a135d566c6e3 Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Mon, 13 Jun 2022 06:32:44 +0100
Subject: [PATCH 0480/1731] io_uring: fix races with file table unregister

Fixed file table quiesce might unlock ->uring_lock, potentially letting
new requests to be submitted, don't allow those requests to use the
table as they will race with unregistration.

Reported-and-tested-by: van fantasy <g1042620637@gmail.com>
Fixes: 05f3fb3c53975 ("io_uring: avoid ring quiesce for fixed file set unregister and update")
Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
---
 fs/io_uring.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index ed3416a7b2e94..00d2667469166 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -9768,11 +9768,19 @@ static void __io_sqe_files_unregister(struct io_ring_ctx *ctx)
 
 static int io_sqe_files_unregister(struct io_ring_ctx *ctx)
 {
+	unsigned nr = ctx->nr_user_files;
 	int ret;
 
 	if (!ctx->file_data)
 		return -ENXIO;
+
+	/*
+	 * Quiesce may unlock ->uring_lock, and while it's not held
+	 * prevent new requests using the table.
+	 */
+	ctx->nr_user_files = 0;
 	ret = io_rsrc_ref_quiesce(ctx->file_data, ctx);
+	ctx->nr_user_files = nr;
 	if (!ret)
 		__io_sqe_files_unregister(ctx);
 	return ret;
-- 
GitLab


From d11d31fc5d8a96f707facee0babdcffaafa38de2 Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Mon, 13 Jun 2022 06:30:06 +0100
Subject: [PATCH 0481/1731] io_uring: fix races with buffer table unregister

Fixed buffer table quiesce might unlock ->uring_lock, potentially
letting new requests to be submitted, don't allow those requests to
use the table as they will race with unregistration.

Reported-and-tested-by: van fantasy <g1042620637@gmail.com>
Fixes: bd54b6fe3316ec ("io_uring: implement fixed buffers registration similar to fixed files")
Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
---
 fs/io_uring.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index 00d2667469166..be05f375a7764 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -10680,12 +10680,19 @@ static void __io_sqe_buffers_unregister(struct io_ring_ctx *ctx)
 
 static int io_sqe_buffers_unregister(struct io_ring_ctx *ctx)
 {
+	unsigned nr = ctx->nr_user_bufs;
 	int ret;
 
 	if (!ctx->buf_data)
 		return -ENXIO;
 
+	/*
+	 * Quiesce may unlock ->uring_lock, and while it's not held
+	 * prevent new requests using the table.
+	 */
+	ctx->nr_user_bufs = 0;
 	ret = io_rsrc_ref_quiesce(ctx->buf_data, ctx);
+	ctx->nr_user_bufs = nr;
 	if (!ret)
 		__io_sqe_buffers_unregister(ctx);
 	return ret;
-- 
GitLab


From 05b538c1765f8d14a71ccf5f85258dcbeaf189f7 Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Thu, 9 Jun 2022 08:34:35 +0100
Subject: [PATCH 0482/1731] io_uring: fix not locked access to fixed buf table

We can look inside the fixed buffer table only while holding
->uring_lock, however in some cases we don't do the right async prep for
IORING_OP_{WRITE,READ}_FIXED ending up with NULL req->imu forcing making
an io-wq worker to try to resolve the fixed buffer without proper
locking.

Move req->imu setup into early req init paths, i.e. io_prep_rw(), which
is called unconditionally for rw requests and under uring_lock.

Fixes: 634d00df5e1cf ("io_uring: add full-fledged dynamic buffers support")
Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
---
 fs/io_uring.c | 34 +++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index be05f375a7764..fd8a1ffe6a1a2 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -3636,6 +3636,20 @@ static int io_prep_rw(struct io_kiocb *req, const struct io_uring_sqe *sqe)
 	int ret;
 
 	kiocb->ki_pos = READ_ONCE(sqe->off);
+	/* used for fixed read/write too - just read unconditionally */
+	req->buf_index = READ_ONCE(sqe->buf_index);
+
+	if (req->opcode == IORING_OP_READ_FIXED ||
+	    req->opcode == IORING_OP_WRITE_FIXED) {
+		struct io_ring_ctx *ctx = req->ctx;
+		u16 index;
+
+		if (unlikely(req->buf_index >= ctx->nr_user_bufs))
+			return -EFAULT;
+		index = array_index_nospec(req->buf_index, ctx->nr_user_bufs);
+		req->imu = ctx->user_bufs[index];
+		io_req_set_rsrc_node(req, ctx, 0);
+	}
 
 	ioprio = READ_ONCE(sqe->ioprio);
 	if (ioprio) {
@@ -3648,12 +3662,9 @@ static int io_prep_rw(struct io_kiocb *req, const struct io_uring_sqe *sqe)
 		kiocb->ki_ioprio = get_current_ioprio();
 	}
 
-	req->imu = NULL;
 	req->rw.addr = READ_ONCE(sqe->addr);
 	req->rw.len = READ_ONCE(sqe->len);
 	req->rw.flags = READ_ONCE(sqe->rw_flags);
-	/* used for fixed read/write too - just read unconditionally */
-	req->buf_index = READ_ONCE(sqe->buf_index);
 	return 0;
 }
 
@@ -3785,20 +3796,9 @@ static int __io_import_fixed(struct io_kiocb *req, int rw, struct iov_iter *iter
 static int io_import_fixed(struct io_kiocb *req, int rw, struct iov_iter *iter,
 			   unsigned int issue_flags)
 {
-	struct io_mapped_ubuf *imu = req->imu;
-	u16 index, buf_index = req->buf_index;
-
-	if (likely(!imu)) {
-		struct io_ring_ctx *ctx = req->ctx;
-
-		if (unlikely(buf_index >= ctx->nr_user_bufs))
-			return -EFAULT;
-		io_req_set_rsrc_node(req, ctx, issue_flags);
-		index = array_index_nospec(buf_index, ctx->nr_user_bufs);
-		imu = READ_ONCE(ctx->user_bufs[index]);
-		req->imu = imu;
-	}
-	return __io_import_fixed(req, rw, iter, imu);
+	if (WARN_ON_ONCE(!req->imu))
+		return -EFAULT;
+	return __io_import_fixed(req, rw, iter, req->imu);
 }
 
 static int io_buffer_add_list(struct io_ring_ctx *ctx,
-- 
GitLab


From c9b576d0c7bf55aeae1a736da7974fa202c4394d Mon Sep 17 00:00:00 2001
From: Alan Previn <alan.previn.teres.alexis@intel.com>
Date: Thu, 10 Mar 2022 16:43:11 -0800
Subject: [PATCH 0483/1731] drm/i915/reset: Fix error_state_read ptr + offset
 use

Fix our pointer offset usage in error_state_read
when there is no i915_gpu_coredump but buf offset
is non-zero.

This fixes a kernel page fault can happen when
multiple tests are running concurrently in a loop
and one is producing engine resets and consuming
the i915 error_state dump while the other is
forcing full GT resets. (takes a while to trigger).

The dmesg call trace:

[ 5590.803000] BUG: unable to handle page fault for address:
               ffffffffa0b0e000
[ 5590.803009] #PF: supervisor read access in kernel mode
[ 5590.803013] #PF: error_code(0x0000) - not-present page
[ 5590.803016] PGD 5814067 P4D 5814067 PUD 5815063 PMD 109de4067
               PTE 0
[ 5590.803022] Oops: 0000 [#1] PREEMPT SMP NOPTI
[ 5590.803026] CPU: 5 PID: 13656 Comm: i915_hangman Tainted: G U
                    5.17.0-rc5-ups69-guc-err-capt-rev6+ #136
[ 5590.803033] Hardware name: Intel Corporation Alder Lake Client
                    Platform/AlderLake-M LP4x RVP, BIOS ADLPFWI1.R00.
                    3031.A02.2201171222	01/17/2022
[ 5590.803039] RIP: 0010:memcpy_erms+0x6/0x10
[ 5590.803045] Code: fe ff ff cc eb 1e 0f 1f 00 48 89 f8 48 89 d1
                     48 c1 e9 03 83 e2 07 f3 48 a5 89 d1 f3 a4 c3
                     66 0f 1f 44 00 00 48 89 f8 48 89 d1 <f3> a4
                     c3 0f 1f 80 00 00 00 00 48 89 f8 48 83 fa 20
                     72 7e 40 38 fe
[ 5590.803054] RSP: 0018:ffffc90003a8fdf0 EFLAGS: 00010282
[ 5590.803057] RAX: ffff888107ee9000 RBX: ffff888108cb1a00
               RCX: 0000000000000f8f
[ 5590.803061] RDX: 0000000000001000 RSI: ffffffffa0b0e000
               RDI: ffff888107ee9071
[ 5590.803065] RBP: 0000000000000000 R08: 0000000000000001
               R09: 0000000000000001
[ 5590.803069] R10: 0000000000000001 R11: 0000000000000002
               R12: 0000000000000019
[ 5590.803073] R13: 0000000000174fff R14: 0000000000001000
               R15: ffff888107ee9000
[ 5590.803077] FS: 00007f62a99bee80(0000) GS:ffff88849f880000(0000)
               knlGS:0000000000000000
[ 5590.803082] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 5590.803085] CR2: ffffffffa0b0e000 CR3: 000000010a1a8004
               CR4: 0000000000770ee0
[ 5590.803089] PKRU: 55555554
[ 5590.803091] Call Trace:
[ 5590.803093] <TASK>
[ 5590.803096] error_state_read+0xa1/0xd0 [i915]
[ 5590.803175] kernfs_fop_read_iter+0xb2/0x1b0
[ 5590.803180] new_sync_read+0x116/0x1a0
[ 5590.803185] vfs_read+0x114/0x1b0
[ 5590.803189] ksys_read+0x63/0xe0
[ 5590.803193] do_syscall_64+0x38/0xc0
[ 5590.803197] entry_SYSCALL_64_after_hwframe+0x44/0xae
[ 5590.803201] RIP: 0033:0x7f62aaea5912
[ 5590.803204] Code: c0 e9 b2 fe ff ff 50 48 8d 3d 5a b9 0c 00 e8 05
                     19 02 00 0f 1f 44 00 00 f3 0f 1e fa 64 8b 04 25
                     18 00 00 00 85 c0 75 10 0f 05 <48> 3d 00 f0 ff
                     ff 77 56 c3 0f 1f 44 00 00 48 83 ec 28 48 89 54 24
[ 5590.803213] RSP: 002b:00007fff5b659ae8 EFLAGS: 00000246
               ORIG_RAX: 0000000000000000
[ 5590.803218] RAX: ffffffffffffffda RBX: 0000000000100000
               RCX: 00007f62aaea5912
[ 5590.803221] RDX: 000000000008b000 RSI: 00007f62a8c4000f
               RDI: 0000000000000006
[ 5590.803225] RBP: 00007f62a8bcb00f R08: 0000000000200010
               R09: 0000000000101000
[ 5590.803229] R10: 0000000000000001 R11: 0000000000000246
               R12: 0000000000000006
[ 5590.803233] R13: 0000000000075000 R14: 00007f62a8acb010
               R15: 0000000000200000
[ 5590.803238] </TASK>
[ 5590.803240] Modules linked in: i915 ttm drm_buddy drm_dp_helper
                        drm_kms_helper syscopyarea sysfillrect sysimgblt
                        fb_sys_fops prime_numbers nfnetlink br_netfilter
                        overlay mei_pxp mei_hdcp x86_pkg_temp_thermal
                        coretemp kvm_intel snd_hda_codec_hdmi snd_hda_intel
                        snd_intel_dspcfg snd_hda_codec snd_hwdep
                        snd_hda_core snd_pcm mei_me mei fuse ip_tables
                        x_tables crct10dif_pclmul e1000e crc32_pclmul ptp
                        i2c_i801 ghash_clmulni_intel i2c_smbus pps_core
                        [last unloa ded: ttm]
[ 5590.803277] CR2: ffffffffa0b0e000
[ 5590.803280] ---[ end trace 0000000000000000 ]---

Fixes: 0e39037b3165 ("drm/i915: Cache the error string")
Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220311004311.514198-2-alan.previn.teres.alexis@intel.com
(cherry picked from commit 3304033a1e69cd81a2044b4422f0d7e593afb4e6)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_sysfs.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 8521daba212a7..a4e3b6dbb231d 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -166,7 +166,14 @@ static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
 	struct device *kdev = kobj_to_dev(kobj);
 	struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
 	struct i915_gpu_coredump *gpu;
-	ssize_t ret;
+	ssize_t ret = 0;
+
+	/*
+	 * FIXME: Concurrent clients triggering resets and reading + clearing
+	 * dumps can cause inconsistent sysfs reads when a user calls in with a
+	 * non-zero offset to complete a prior partial read but the
+	 * gpu_coredump has been cleared or replaced.
+	 */
 
 	gpu = i915_first_error_state(i915);
 	if (IS_ERR(gpu)) {
@@ -178,8 +185,10 @@ static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
 		const char *str = "No error state collected\n";
 		size_t len = strlen(str);
 
-		ret = min_t(size_t, count, len - off);
-		memcpy(buf, str + off, ret);
+		if (off < len) {
+			ret = min_t(size_t, count, len - off);
+			memcpy(buf, str + off, ret);
+		}
 	}
 
 	return ret;
-- 
GitLab


From 6e3f3c239ee547c5b55a85f467c92a6ba7eee83a Mon Sep 17 00:00:00 2001
From: Ashutosh Dixit <ashutosh.dixit@intel.com>
Date: Wed, 25 May 2022 06:19:20 -0700
Subject: [PATCH 0484/1731] drm/i915/gt: Fix memory leaks in per-gt sysfs

All kmalloc'd kobjects need a kobject_put() to free memory. For example in
previous code, kobj_gt_release() never gets called. The requirement of
kobject_put() now results in a slightly different code organization.

v2: s/gtn/gt/ (Andi)

Fixes: b770bcfae9ad ("drm/i915/gt: create per-tile sysfs interface")
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Acked-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/a6f6686517c85fba61a0c45097f5bb4fe7e257fb.1653484574.git.ashutosh.dixit@intel.com
(cherry picked from commit 69d6bf5c3754ffc491896632438417d1cedc2c68)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt.c       |  1 +
 drivers/gpu/drm/i915/gt/intel_gt_sysfs.c | 29 ++++++++++--------------
 drivers/gpu/drm/i915/gt/intel_gt_sysfs.h |  6 +----
 drivers/gpu/drm/i915/gt/intel_gt_types.h |  3 +++
 drivers/gpu/drm/i915/i915_sysfs.c        |  2 ++
 5 files changed, 19 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 53307ca0eed0c..51a0fe60c050d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -785,6 +785,7 @@ void intel_gt_driver_unregister(struct intel_gt *gt)
 {
 	intel_wakeref_t wakeref;
 
+	intel_gt_sysfs_unregister(gt);
 	intel_rps_driver_unregister(&gt->rps);
 	intel_gsc_fini(&gt->gsc);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
index 8ec8bc660c8c2..9e4ebf53379bc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
@@ -24,7 +24,7 @@ bool is_object_gt(struct kobject *kobj)
 
 static struct intel_gt *kobj_to_gt(struct kobject *kobj)
 {
-	return container_of(kobj, struct kobj_gt, base)->gt;
+	return container_of(kobj, struct intel_gt, sysfs_gt);
 }
 
 struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
@@ -72,9 +72,9 @@ static struct attribute *id_attrs[] = {
 };
 ATTRIBUTE_GROUPS(id);
 
+/* A kobject needs a release() method even if it does nothing */
 static void kobj_gt_release(struct kobject *kobj)
 {
-	kfree(kobj);
 }
 
 static struct kobj_type kobj_gt_type = {
@@ -85,8 +85,6 @@ static struct kobj_type kobj_gt_type = {
 
 void intel_gt_sysfs_register(struct intel_gt *gt)
 {
-	struct kobj_gt *kg;
-
 	/*
 	 * We need to make things right with the
 	 * ABI compatibility. The files were originally
@@ -98,25 +96,22 @@ void intel_gt_sysfs_register(struct intel_gt *gt)
 	if (gt_is_root(gt))
 		intel_gt_sysfs_pm_init(gt, gt_get_parent_obj(gt));
 
-	kg = kzalloc(sizeof(*kg), GFP_KERNEL);
-	if (!kg)
+	/* init and xfer ownership to sysfs tree */
+	if (kobject_init_and_add(&gt->sysfs_gt, &kobj_gt_type,
+				 gt->i915->sysfs_gt, "gt%d", gt->info.id))
 		goto exit_fail;
 
-	kobject_init(&kg->base, &kobj_gt_type);
-	kg->gt = gt;
-
-	/* xfer ownership to sysfs tree */
-	if (kobject_add(&kg->base, gt->i915->sysfs_gt, "gt%d", gt->info.id))
-		goto exit_kobj_put;
-
-	intel_gt_sysfs_pm_init(gt, &kg->base);
+	intel_gt_sysfs_pm_init(gt, &gt->sysfs_gt);
 
 	return;
 
-exit_kobj_put:
-	kobject_put(&kg->base);
-
 exit_fail:
+	kobject_put(&gt->sysfs_gt);
 	drm_warn(&gt->i915->drm,
 		 "failed to initialize gt%d sysfs root\n", gt->info.id);
 }
+
+void intel_gt_sysfs_unregister(struct intel_gt *gt)
+{
+	kobject_put(&gt->sysfs_gt);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
index 9471b26752cfc..a99aa7e8b01a6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
@@ -13,11 +13,6 @@
 
 struct intel_gt;
 
-struct kobj_gt {
-	struct kobject base;
-	struct intel_gt *gt;
-};
-
 bool is_object_gt(struct kobject *kobj);
 
 struct drm_i915_private *kobj_to_i915(struct kobject *kobj);
@@ -28,6 +23,7 @@ intel_gt_create_kobj(struct intel_gt *gt,
 		     const char *name);
 
 void intel_gt_sysfs_register(struct intel_gt *gt);
+void intel_gt_sysfs_unregister(struct intel_gt *gt);
 struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
 					    const char *name);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index b06611c1d4ada..edd7a3cf5f5f5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -224,6 +224,9 @@ struct intel_gt {
 	} mocs;
 
 	struct intel_pxp pxp;
+
+	/* gt/gtN sysfs */
+	struct kobject sysfs_gt;
 };
 
 enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index a4e3b6dbb231d..1e27502108313 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -268,4 +268,6 @@ void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
 
 	device_remove_bin_file(kdev,  &dpf_attrs_1);
 	device_remove_bin_file(kdev,  &dpf_attrs);
+
+	kobject_put(dev_priv->sysfs_gt);
 }
-- 
GitLab


From 842d9346b2fdda4d2fb8ccb5b87faef1ac01ab51 Mon Sep 17 00:00:00 2001
From: Nirmoy Das <nirmoy.das@intel.com>
Date: Wed, 25 May 2022 11:59:55 +0200
Subject: [PATCH 0485/1731] drm/i915: Individualize fences before adding to
 dma_resv obj

_i915_vma_move_to_active() can receive > 1 fences for
multiple batch buffers submission. Because dma_resv_add_fence()
can only accept one fence at a time, change _i915_vma_move_to_active()
to be aware of multiple fences so that it can add individual
fences to the dma resv object.

v6: fix multi-line comment.
v5: remove double fence reservation for batch VMAs.
v4: Reserve fences for composite_fence on multi-batch contexts and
    also reserve fence slots to composite_fence for each VMAs.
v3: dma_resv_reserve_fences is not cumulative so pass num_fences.
v2: make sure to reserve enough fence slots before adding.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5614
Fixes: 544460c33821 ("drm/i915: Multi-BB execbuf")
Cc: <stable@vger.kernel.org> # v5.16+
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220525095955.15371-1-nirmoy.das@intel.com
(cherry picked from commit 420a07b841d03f6a436d8c06571c69aa5c783897)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/gem/i915_gem_execbuffer.c    |  3 +-
 drivers/gpu/drm/i915/i915_vma.c               | 48 +++++++++++--------
 2 files changed, 30 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index c326bd2b444fc..30fe847c6664d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -999,7 +999,8 @@ static int eb_validate_vmas(struct i915_execbuffer *eb)
 			}
 		}
 
-		err = dma_resv_reserve_fences(vma->obj->base.resv, 1);
+		/* Reserve enough slots to accommodate composite fences */
+		err = dma_resv_reserve_fences(vma->obj->base.resv, eb->num_batches);
 		if (err)
 			return err;
 
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 4f6db539571aa..0bffb70b3c5f5 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -23,6 +23,7 @@
  */
 
 #include <linux/sched/mm.h>
+#include <linux/dma-fence-array.h>
 #include <drm/drm_gem.h>
 
 #include "display/intel_frontbuffer.h"
@@ -1823,6 +1824,21 @@ int _i915_vma_move_to_active(struct i915_vma *vma,
 	if (unlikely(err))
 		return err;
 
+	/*
+	 * Reserve fences slot early to prevent an allocation after preparing
+	 * the workload and associating fences with dma_resv.
+	 */
+	if (fence && !(flags & __EXEC_OBJECT_NO_RESERVE)) {
+		struct dma_fence *curr;
+		int idx;
+
+		dma_fence_array_for_each(curr, idx, fence)
+			;
+		err = dma_resv_reserve_fences(vma->obj->base.resv, idx);
+		if (unlikely(err))
+			return err;
+	}
+
 	if (flags & EXEC_OBJECT_WRITE) {
 		struct intel_frontbuffer *front;
 
@@ -1832,31 +1848,23 @@ int _i915_vma_move_to_active(struct i915_vma *vma,
 				i915_active_add_request(&front->write, rq);
 			intel_frontbuffer_put(front);
 		}
+	}
 
-		if (!(flags & __EXEC_OBJECT_NO_RESERVE)) {
-			err = dma_resv_reserve_fences(vma->obj->base.resv, 1);
-			if (unlikely(err))
-				return err;
-		}
+	if (fence) {
+		struct dma_fence *curr;
+		enum dma_resv_usage usage;
+		int idx;
 
-		if (fence) {
-			dma_resv_add_fence(vma->obj->base.resv, fence,
-					   DMA_RESV_USAGE_WRITE);
+		obj->read_domains = 0;
+		if (flags & EXEC_OBJECT_WRITE) {
+			usage = DMA_RESV_USAGE_WRITE;
 			obj->write_domain = I915_GEM_DOMAIN_RENDER;
-			obj->read_domains = 0;
-		}
-	} else {
-		if (!(flags & __EXEC_OBJECT_NO_RESERVE)) {
-			err = dma_resv_reserve_fences(vma->obj->base.resv, 1);
-			if (unlikely(err))
-				return err;
+		} else {
+			usage = DMA_RESV_USAGE_READ;
 		}
 
-		if (fence) {
-			dma_resv_add_fence(vma->obj->base.resv, fence,
-					   DMA_RESV_USAGE_READ);
-			obj->write_domain = 0;
-		}
+		dma_fence_array_for_each(curr, idx, fence)
+			dma_resv_add_fence(vma->obj->base.resv, curr, usage);
 	}
 
 	if (flags & EXEC_OBJECT_NEEDS_FENCE && vma->fence)
-- 
GitLab


From e71d7c56dd69f720169c1675f87a1d22d8167767 Mon Sep 17 00:00:00 2001
From: Hao Xu <howeyxu@tencent.com>
Date: Sat, 11 Jun 2022 20:22:20 +0800
Subject: [PATCH 0486/1731] io_uring: openclose: fix bug of closing wrong fixed
 file

Don't update ret until fixed file is closed, otherwise the file slot
becomes the error code.

Fixes: a7c41b4687f5 ("io_uring: let IORING_OP_FILES_UPDATE support choosing fixed file slots")
Signed-off-by: Hao Xu <howeyxu@tencent.com>
[pavel: 5.19 rebase]
Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
---
 fs/io_uring.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index fd8a1ffe6a1a2..e6d8cafdd28e6 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -8035,8 +8035,8 @@ static int io_files_update_with_index_alloc(struct io_kiocb *req,
 		if (ret < 0)
 			break;
 		if (copy_to_user(&fds[done], &ret, sizeof(ret))) {
-			ret = -EFAULT;
 			__io_close_fixed(req, issue_flags, ret);
+			ret = -EFAULT;
 			break;
 		}
 	}
-- 
GitLab


From 42db0c00e275877eb92480beaa16b33507dc3bda Mon Sep 17 00:00:00 2001
From: Hao Xu <howeyxu@tencent.com>
Date: Sat, 11 Jun 2022 20:29:52 +0800
Subject: [PATCH 0487/1731] io_uring: kbuf: fix bug of not consuming ring
 buffer in partial io case

When we use ring-mapped provided buffer, we should consume it before
arm poll if partial io has been done. Otherwise the buffer may be used
by other requests and thus we lost the data.

Fixes: c7fb19428d67 ("io_uring: add support for ring mapped supplied buffers")
Signed-off-by: Hao Xu <howeyxu@tencent.com>
[pavel: 5.19 rebase]
Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
---
 fs/io_uring.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index e6d8cafdd28e6..84b45ed91b2d3 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -1729,9 +1729,16 @@ static void io_kbuf_recycle(struct io_kiocb *req, unsigned issue_flags)
 
 	if (!(req->flags & (REQ_F_BUFFER_SELECTED|REQ_F_BUFFER_RING)))
 		return;
-	/* don't recycle if we already did IO to this buffer */
-	if (req->flags & REQ_F_PARTIAL_IO)
+	/*
+	 * For legacy provided buffer mode, don't recycle if we already did
+	 * IO to this buffer. For ring-mapped provided buffer mode, we should
+	 * increment ring->head to explicitly monopolize the buffer to avoid
+	 * multiple use.
+	 */
+	if ((req->flags & REQ_F_BUFFER_SELECTED) &&
+	    (req->flags & REQ_F_PARTIAL_IO))
 		return;
+
 	/*
 	 * We don't need to recycle for REQ_F_BUFFER_RING, we can just clear
 	 * the flag and hence ensure that bl->head doesn't get incremented.
@@ -1739,8 +1746,13 @@ static void io_kbuf_recycle(struct io_kiocb *req, unsigned issue_flags)
 	 */
 	if (req->flags & REQ_F_BUFFER_RING) {
 		if (req->buf_list) {
-			req->buf_index = req->buf_list->bgid;
-			req->flags &= ~REQ_F_BUFFER_RING;
+			if (req->flags & REQ_F_PARTIAL_IO) {
+				req->buf_list->head++;
+				req->buf_list = NULL;
+			} else {
+				req->buf_index = req->buf_list->bgid;
+				req->flags &= ~REQ_F_BUFFER_RING;
+			}
 		}
 		return;
 	}
-- 
GitLab


From fc9375e3f763b06c3c90c5f5b2b84d3e07c1f4c2 Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Sun, 12 Jun 2022 14:31:38 +0100
Subject: [PATCH 0488/1731] io_uring: fix double unlock for pbuf select

io_buffer_select(), which is the only caller of io_ring_buffer_select(),
fully handles locking, mutex unlock in io_ring_buffer_select() will lead
to double unlock.

Fixes: c7fb19428d67d ("io_uring: add support for ring mapped supplied buffers")
Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
---
 fs/io_uring.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index 84b45ed91b2d3..4719eaee3b453 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -3849,10 +3849,8 @@ static void __user *io_ring_buffer_select(struct io_kiocb *req, size_t *len,
 	struct io_uring_buf *buf;
 	__u32 head = bl->head;
 
-	if (unlikely(smp_load_acquire(&br->tail) == head)) {
-		io_ring_submit_unlock(req->ctx, issue_flags);
+	if (unlikely(smp_load_acquire(&br->tail) == head))
 		return NULL;
-	}
 
 	head &= bl->mask;
 	if (head < IO_BUFFER_LIST_BUF_PER_PAGE) {
-- 
GitLab


From 2636e008112465ca54559ac4898da5a2515e118a Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Wed, 11 May 2022 12:46:19 +0300
Subject: [PATCH 0489/1731] drm/i915/uc: remove accidental static from a local
 variable

The arrays are static const, but the pointer shouldn't be static.

Fixes: 3d832f370d16 ("drm/i915/uc: Allow platforms to have GuC but not HuC")
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220511094619.27889-1-jani.nikula@intel.com
(cherry picked from commit 5821a0bbb4c39960975d29d6b58ae290088db0ed)
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index d078f884b5e32..f0d7b57b741e7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -156,7 +156,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct intel_uc_fw *uc_fw)
 		[INTEL_UC_FW_TYPE_GUC] = { blobs_guc, ARRAY_SIZE(blobs_guc) },
 		[INTEL_UC_FW_TYPE_HUC] = { blobs_huc, ARRAY_SIZE(blobs_huc) },
 	};
-	static const struct uc_fw_platform_requirement *fw_blobs;
+	const struct uc_fw_platform_requirement *fw_blobs;
 	enum intel_platform p = INTEL_INFO(i915)->platform;
 	u32 fw_count;
 	u8 rev = INTEL_REVID(i915);
-- 
GitLab


From 9eda7d8bcbdb6909f202edeedff51948f1cad1e5 Mon Sep 17 00:00:00 2001
From: Guangbin Huang <huangguangbin2@huawei.com>
Date: Sat, 11 Jun 2022 20:25:24 +0800
Subject: [PATCH 0490/1731] net: hns3: set port base vlan tbl_sta to false
 before removing old vlan

When modify port base vlan, the port base vlan tbl_sta needs to set to
false before removing old vlan, to indicate this operation is not finish.

Fixes: c0f46de30c96 ("net: hns3: fix port base vlan add fail when concurrent with reset")
Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index 1ebad0e50e6a2..fc0265b633315 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -10117,6 +10117,7 @@ static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport,
 	if (ret)
 		return ret;
 
+	vport->port_base_vlan_cfg.tbl_sta = false;
 	/* remove old VLAN tag */
 	if (old_info->vlan_tag == 0)
 		ret = hclge_set_vf_vlan_common(hdev, vport->vport_id,
-- 
GitLab


From 283847e3ef6dbf79bf67083b5ce7b8033e8b6f34 Mon Sep 17 00:00:00 2001
From: Jian Shen <shenjian15@huawei.com>
Date: Sat, 11 Jun 2022 20:25:25 +0800
Subject: [PATCH 0491/1731] net: hns3: don't push link state to VF if unalive

It's unnecessary to push link state to unalive VF, and the VF will
query link state from PF when it being start works.

Fixes: 18b6e31f8bf4 ("net: hns3: PF add support for pushing link status to VFs")
Signed-off-by: Jian Shen <shenjian15@huawei.com>
Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index fc0265b633315..2e891b837c51e 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -3376,6 +3376,12 @@ static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf,
 	link_state_old = vport->vf_info.link_state;
 	vport->vf_info.link_state = link_state;
 
+	/* return success directly if the VF is unalive, VF will
+	 * query link state itself when it starts work.
+	 */
+	if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
+		return 0;
+
 	ret = hclge_push_vf_link_status(vport);
 	if (ret) {
 		vport->vf_info.link_state = link_state_old;
-- 
GitLab


From cfd80687a5388e731b3db65ad6a557ede9b45905 Mon Sep 17 00:00:00 2001
From: Jie Wang <wangjie125@huawei.com>
Date: Sat, 11 Jun 2022 20:25:26 +0800
Subject: [PATCH 0492/1731] net: hns3: modify the ring param print info

Currently tx push is also a ring param. So the original ring param print
info in hns3_is_ringparam_changed should be adjusted.

Fixes: 07fdc163ac88 ("net: hns3: refactor hns3_set_ringparam()")
Signed-off-by: Jie Wang <wangjie125@huawei.com>
Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
index 6d20974519fef..4c7988e308a2f 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
@@ -1129,7 +1129,7 @@ hns3_is_ringparam_changed(struct net_device *ndev,
 	if (old_ringparam->tx_desc_num == new_ringparam->tx_desc_num &&
 	    old_ringparam->rx_desc_num == new_ringparam->rx_desc_num &&
 	    old_ringparam->rx_buf_len == new_ringparam->rx_buf_len) {
-		netdev_info(ndev, "ringparam not changed\n");
+		netdev_info(ndev, "descriptor number and rx buffer length not changed\n");
 		return false;
 	}
 
-- 
GitLab


From e93530ae0e5d8fcf2d908933d206e0c93bc3c09b Mon Sep 17 00:00:00 2001
From: Guangbin Huang <huangguangbin2@huawei.com>
Date: Sat, 11 Jun 2022 20:25:27 +0800
Subject: [PATCH 0493/1731] net: hns3: restore tm priority/qset to default
 settings when tc disabled

Currently, settings parameters of schedule mode, dwrr, shaper of tm
priority or qset of one tc are only be set when tc is enabled, they are
not restored to the default settings when tc is disabled. It confuses
users when they cat tm_priority or tm_qset files of debugfs. So this
patch fixes it.

Fixes: 848440544b41 ("net: hns3: Add support of TX Scheduler & Shaper to HNS3 driver")
Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  1 +
 .../ethernet/hisilicon/hns3/hns3pf/hclge_tm.c | 95 +++++++++++++------
 2 files changed, 65 insertions(+), 31 deletions(-)

diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
index 8a3a446219f74..94f80e1c4020c 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
@@ -769,6 +769,7 @@ struct hnae3_tc_info {
 	u8 prio_tc[HNAE3_MAX_USER_PRIO]; /* TC indexed by prio */
 	u16 tqp_count[HNAE3_MAX_TC];
 	u16 tqp_offset[HNAE3_MAX_TC];
+	u8 max_tc; /* Total number of TCs */
 	u8 num_tc; /* Total number of enabled TCs */
 	bool mqprio_active;
 };
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
index 1f87a8a3fe321..ad53a34473221 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
@@ -282,8 +282,8 @@ static int hclge_tm_pg_to_pri_map_cfg(struct hclge_dev *hdev,
 	return hclge_cmd_send(&hdev->hw, &desc, 1);
 }
 
-static int hclge_tm_qs_to_pri_map_cfg(struct hclge_dev *hdev,
-				      u16 qs_id, u8 pri)
+static int hclge_tm_qs_to_pri_map_cfg(struct hclge_dev *hdev, u16 qs_id, u8 pri,
+				      bool link_vld)
 {
 	struct hclge_qs_to_pri_link_cmd *map;
 	struct hclge_desc desc;
@@ -294,7 +294,7 @@ static int hclge_tm_qs_to_pri_map_cfg(struct hclge_dev *hdev,
 
 	map->qs_id = cpu_to_le16(qs_id);
 	map->priority = pri;
-	map->link_vld = HCLGE_TM_QS_PRI_LINK_VLD_MSK;
+	map->link_vld = link_vld ? HCLGE_TM_QS_PRI_LINK_VLD_MSK : 0;
 
 	return hclge_cmd_send(&hdev->hw, &desc, 1);
 }
@@ -642,11 +642,13 @@ static void hclge_tm_update_kinfo_rss_size(struct hclge_vport *vport)
 	 * one tc for VF for simplicity. VF's vport_id is non zero.
 	 */
 	if (vport->vport_id) {
+		kinfo->tc_info.max_tc = 1;
 		kinfo->tc_info.num_tc = 1;
 		vport->qs_offset = HNAE3_MAX_TC +
 				   vport->vport_id - HCLGE_VF_VPORT_START_NUM;
 		vport_max_rss_size = hdev->vf_rss_size_max;
 	} else {
+		kinfo->tc_info.max_tc = hdev->tc_max;
 		kinfo->tc_info.num_tc =
 			min_t(u16, vport->alloc_tqps, hdev->tm_info.num_tc);
 		vport->qs_offset = 0;
@@ -714,14 +716,22 @@ static void hclge_tm_vport_info_update(struct hclge_dev *hdev)
 
 static void hclge_tm_tc_info_init(struct hclge_dev *hdev)
 {
-	u8 i;
+	u8 i, tc_sch_mode;
+	u32 bw_limit;
+
+	for (i = 0; i < hdev->tc_max; i++) {
+		if (i < hdev->tm_info.num_tc) {
+			tc_sch_mode = HCLGE_SCH_MODE_DWRR;
+			bw_limit = hdev->tm_info.pg_info[0].bw_limit;
+		} else {
+			tc_sch_mode = HCLGE_SCH_MODE_SP;
+			bw_limit = 0;
+		}
 
-	for (i = 0; i < hdev->tm_info.num_tc; i++) {
 		hdev->tm_info.tc_info[i].tc_id = i;
-		hdev->tm_info.tc_info[i].tc_sch_mode = HCLGE_SCH_MODE_DWRR;
+		hdev->tm_info.tc_info[i].tc_sch_mode = tc_sch_mode;
 		hdev->tm_info.tc_info[i].pgid = 0;
-		hdev->tm_info.tc_info[i].bw_limit =
-			hdev->tm_info.pg_info[0].bw_limit;
+		hdev->tm_info.tc_info[i].bw_limit = bw_limit;
 	}
 
 	for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
@@ -926,10 +936,13 @@ static int hclge_tm_pri_q_qs_cfg_tc_base(struct hclge_dev *hdev)
 	for (k = 0; k < hdev->num_alloc_vport; k++) {
 		struct hnae3_knic_private_info *kinfo = &vport[k].nic.kinfo;
 
-		for (i = 0; i < kinfo->tc_info.num_tc; i++) {
+		for (i = 0; i < kinfo->tc_info.max_tc; i++) {
+			u8 pri = i < kinfo->tc_info.num_tc ? i : 0;
+			bool link_vld = i < kinfo->tc_info.num_tc;
+
 			ret = hclge_tm_qs_to_pri_map_cfg(hdev,
 							 vport[k].qs_offset + i,
-							 i);
+							 pri, link_vld);
 			if (ret)
 				return ret;
 		}
@@ -949,7 +962,7 @@ static int hclge_tm_pri_q_qs_cfg_vnet_base(struct hclge_dev *hdev)
 		for (i = 0; i < HNAE3_MAX_TC; i++) {
 			ret = hclge_tm_qs_to_pri_map_cfg(hdev,
 							 vport[k].qs_offset + i,
-							 k);
+							 k, true);
 			if (ret)
 				return ret;
 		}
@@ -989,33 +1002,39 @@ static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev)
 {
 	u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate;
 	struct hclge_shaper_ir_para ir_para;
-	u32 shaper_para;
+	u32 shaper_para_c, shaper_para_p;
 	int ret;
 	u32 i;
 
-	for (i = 0; i < hdev->tm_info.num_tc; i++) {
+	for (i = 0; i < hdev->tc_max; i++) {
 		u32 rate = hdev->tm_info.tc_info[i].bw_limit;
 
-		ret = hclge_shaper_para_calc(rate, HCLGE_SHAPER_LVL_PRI,
-					     &ir_para, max_tm_rate);
-		if (ret)
-			return ret;
+		if (rate) {
+			ret = hclge_shaper_para_calc(rate, HCLGE_SHAPER_LVL_PRI,
+						     &ir_para, max_tm_rate);
+			if (ret)
+				return ret;
+
+			shaper_para_c = hclge_tm_get_shapping_para(0, 0, 0,
+								   HCLGE_SHAPER_BS_U_DEF,
+								   HCLGE_SHAPER_BS_S_DEF);
+			shaper_para_p = hclge_tm_get_shapping_para(ir_para.ir_b,
+								   ir_para.ir_u,
+								   ir_para.ir_s,
+								   HCLGE_SHAPER_BS_U_DEF,
+								   HCLGE_SHAPER_BS_S_DEF);
+		} else {
+			shaper_para_c = 0;
+			shaper_para_p = 0;
+		}
 
-		shaper_para = hclge_tm_get_shapping_para(0, 0, 0,
-							 HCLGE_SHAPER_BS_U_DEF,
-							 HCLGE_SHAPER_BS_S_DEF);
 		ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET, i,
-						shaper_para, rate);
+						shaper_para_c, rate);
 		if (ret)
 			return ret;
 
-		shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b,
-							 ir_para.ir_u,
-							 ir_para.ir_s,
-							 HCLGE_SHAPER_BS_U_DEF,
-							 HCLGE_SHAPER_BS_S_DEF);
 		ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET, i,
-						shaper_para, rate);
+						shaper_para_p, rate);
 		if (ret)
 			return ret;
 	}
@@ -1125,7 +1144,7 @@ static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev)
 	int ret;
 	u32 i, k;
 
-	for (i = 0; i < hdev->tm_info.num_tc; i++) {
+	for (i = 0; i < hdev->tc_max; i++) {
 		pg_info =
 			&hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];
 		dwrr = pg_info->tc_dwrr[i];
@@ -1135,9 +1154,15 @@ static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev)
 			return ret;
 
 		for (k = 0; k < hdev->num_alloc_vport; k++) {
+			struct hnae3_knic_private_info *kinfo = &vport[k].nic.kinfo;
+
+			if (i >= kinfo->tc_info.max_tc)
+				continue;
+
+			dwrr = i < kinfo->tc_info.num_tc ? vport[k].dwrr : 0;
 			ret = hclge_tm_qs_weight_cfg(
 				hdev, vport[k].qs_offset + i,
-				vport[k].dwrr);
+				dwrr);
 			if (ret)
 				return ret;
 		}
@@ -1303,6 +1328,7 @@ static int hclge_tm_schd_mode_tc_base_cfg(struct hclge_dev *hdev, u8 pri_id)
 {
 	struct hclge_vport *vport = hdev->vport;
 	int ret;
+	u8 mode;
 	u16 i;
 
 	ret = hclge_tm_pri_schd_mode_cfg(hdev, pri_id);
@@ -1310,9 +1336,16 @@ static int hclge_tm_schd_mode_tc_base_cfg(struct hclge_dev *hdev, u8 pri_id)
 		return ret;
 
 	for (i = 0; i < hdev->num_alloc_vport; i++) {
+		struct hnae3_knic_private_info *kinfo = &vport[i].nic.kinfo;
+
+		if (pri_id >= kinfo->tc_info.max_tc)
+			continue;
+
+		mode = pri_id < kinfo->tc_info.num_tc ? HCLGE_SCH_MODE_DWRR :
+		       HCLGE_SCH_MODE_SP;
 		ret = hclge_tm_qs_schd_mode_cfg(hdev,
 						vport[i].qs_offset + pri_id,
-						HCLGE_SCH_MODE_DWRR);
+						mode);
 		if (ret)
 			return ret;
 	}
@@ -1353,7 +1386,7 @@ static int hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev *hdev)
 	u8 i;
 
 	if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
-		for (i = 0; i < hdev->tm_info.num_tc; i++) {
+		for (i = 0; i < hdev->tc_max; i++) {
 			ret = hclge_tm_schd_mode_tc_base_cfg(hdev, i);
 			if (ret)
 				return ret;
-- 
GitLab


From 71b215f36dca1a3d5d1c576b2099e6d7ea03047e Mon Sep 17 00:00:00 2001
From: Jie Wang <wangjie125@huawei.com>
Date: Sat, 11 Jun 2022 20:25:28 +0800
Subject: [PATCH 0494/1731] net: hns3: fix PF rss size initialization bug

Currently hns3 driver misuses the VF rss size to initialize the PF rss size
in hclge_tm_vport_tc_info_update. So this patch fix it by checking the
vport id before initialization.

Fixes: 7347255ea389 ("net: hns3: refactor PF rss get APIs with new common rss get APIs")
Signed-off-by: Jie Wang <wangjie125@huawei.com>
Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
index ad53a34473221..f5296ff606944 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
@@ -681,7 +681,9 @@ static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport)
 	kinfo->num_tqps = hclge_vport_get_tqp_num(vport);
 	vport->dwrr = 100;  /* 100 percent as init */
 	vport->bw_limit = hdev->tm_info.pg_info[0].bw_limit;
-	hdev->rss_cfg.rss_size = kinfo->rss_size;
+
+	if (vport->vport_id == PF_VPORT_ID)
+		hdev->rss_cfg.rss_size = kinfo->rss_size;
 
 	/* when enable mqprio, the tc_info has been updated. */
 	if (kinfo->tc_info.mqprio_active)
-- 
GitLab


From 12a3670887725df364cc3e030cf3bede6f13b364 Mon Sep 17 00:00:00 2001
From: Guangbin Huang <huangguangbin2@huawei.com>
Date: Sat, 11 Jun 2022 20:25:29 +0800
Subject: [PATCH 0495/1731] net: hns3: fix tm port shapping of fibre port is
 incorrect after driver initialization

Currently in driver initialization process, driver will set shapping
parameters of tm port to default speed read from firmware. However, the
speed of SFP module may not be default speed, so shapping parameters of
tm port may be incorrect.

To fix this problem, driver sets new shapping parameters for tm port
after getting exact speed of SFP module in this case.

Fixes: 88d10bd6f730 ("net: hns3: add support for multiple media type")
Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 .../net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c   | 11 ++++++++---
 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c |  2 +-
 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h |  1 +
 3 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index 2e891b837c51e..fae79764dc442 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -3268,7 +3268,7 @@ static int hclge_tp_port_init(struct hclge_dev *hdev)
 static int hclge_update_port_info(struct hclge_dev *hdev)
 {
 	struct hclge_mac *mac = &hdev->hw.mac;
-	int speed = HCLGE_MAC_SPEED_UNKNOWN;
+	int speed;
 	int ret;
 
 	/* get the port info from SFP cmd if not copper port */
@@ -3279,10 +3279,13 @@ static int hclge_update_port_info(struct hclge_dev *hdev)
 	if (!hdev->support_sfp_query)
 		return 0;
 
-	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
+	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
+		speed = mac->speed;
 		ret = hclge_get_sfp_info(hdev, mac);
-	else
+	} else {
+		speed = HCLGE_MAC_SPEED_UNKNOWN;
 		ret = hclge_get_sfp_speed(hdev, &speed);
+	}
 
 	if (ret == -EOPNOTSUPP) {
 		hdev->support_sfp_query = false;
@@ -3294,6 +3297,8 @@ static int hclge_update_port_info(struct hclge_dev *hdev)
 	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
 		if (mac->speed_type == QUERY_ACTIVE_SPEED) {
 			hclge_update_port_capability(hdev, mac);
+			if (mac->speed != speed)
+				(void)hclge_tm_port_shaper_cfg(hdev);
 			return 0;
 		}
 		return hclge_cfg_mac_speed_dup(hdev, mac->speed,
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
index f5296ff606944..2f33b036a47a7 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
@@ -420,7 +420,7 @@ static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev,
 	return hclge_cmd_send(&hdev->hw, &desc, 1);
 }
 
-static int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev)
+int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev)
 {
 	struct hclge_port_shapping_cmd *shap_cfg_cmd;
 	struct hclge_shaper_ir_para ir_para;
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
index 619cc30a2dfcc..d943943912f76 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
@@ -237,6 +237,7 @@ int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr);
 void hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats);
 void hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats);
 int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate);
+int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev);
 int hclge_tm_get_qset_num(struct hclge_dev *hdev, u16 *qset_num);
 int hclge_tm_get_pri_num(struct hclge_dev *hdev, u8 *pri_num);
 int hclge_tm_get_qset_map_pri(struct hclge_dev *hdev, u16 qset_id, u8 *priority,
-- 
GitLab


From 97da4a537924d87e2261773f3ac9365abb191fc9 Mon Sep 17 00:00:00 2001
From: Dylan Yudaken <dylany@fb.com>
Date: Mon, 13 Jun 2022 03:11:55 -0700
Subject: [PATCH 0496/1731] io_uring: fix index calculation

When indexing into a provided buffer ring, do not subtract 1 from the
index.

Fixes: c7fb19428d67 ("io_uring: add support for ring mapped supplied buffers")
Signed-off-by: Dylan Yudaken <dylany@fb.com>
Link: https://lore.kernel.org/r/20220613101157.3687-2-dylany@fb.com
Reviewed-by: Hao Xu <howeyxu@tencent.com>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index 3aab4182fd892..9cf9aff51b70d 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -3888,7 +3888,7 @@ static void __user *io_ring_buffer_select(struct io_kiocb *req, size_t *len,
 		buf = &br->bufs[head];
 	} else {
 		int off = head & (IO_BUFFER_LIST_BUF_PER_PAGE - 1);
-		int index = head / IO_BUFFER_LIST_BUF_PER_PAGE - 1;
+		int index = head / IO_BUFFER_LIST_BUF_PER_PAGE;
 		buf = page_address(bl->buf_pages[index]);
 		buf += off;
 	}
-- 
GitLab


From c6e9fa5c0ab811f4bec36a96337f4b1bb77d142c Mon Sep 17 00:00:00 2001
From: Dylan Yudaken <dylany@fb.com>
Date: Mon, 13 Jun 2022 03:11:56 -0700
Subject: [PATCH 0497/1731] io_uring: fix types in provided buffer ring

The type of head needs to match that of tail in order for rollover and
comparisons to work correctly.

Without this change the comparison of tail to head might incorrectly allow
io_uring to use a buffer that userspace had not given it.

Fixes: c7fb19428d67 ("io_uring: add support for ring mapped supplied buffers")
Signed-off-by: Dylan Yudaken <dylany@fb.com>
Link: https://lore.kernel.org/r/20220613101157.3687-3-dylany@fb.com
Reviewed-by: Hao Xu <howeyxu@tencent.com>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index 9cf9aff51b70d..6eea18e8330c8 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -298,8 +298,8 @@ struct io_buffer_list {
 	/* below is for ring provided buffers */
 	__u16 buf_nr_pages;
 	__u16 nr_entries;
-	__u32 head;
-	__u32 mask;
+	__u16 head;
+	__u16 mask;
 };
 
 struct io_buffer {
@@ -3876,7 +3876,7 @@ static void __user *io_ring_buffer_select(struct io_kiocb *req, size_t *len,
 {
 	struct io_uring_buf_ring *br = bl->buf_ring;
 	struct io_uring_buf *buf;
-	__u32 head = bl->head;
+	__u16 head = bl->head;
 
 	if (unlikely(smp_load_acquire(&br->tail) == head)) {
 		io_ring_submit_unlock(req->ctx, issue_flags);
-- 
GitLab


From f9437ac0f851cea2374d53594f52fbbefdd977bd Mon Sep 17 00:00:00 2001
From: Dylan Yudaken <dylany@fb.com>
Date: Mon, 13 Jun 2022 03:11:57 -0700
Subject: [PATCH 0498/1731] io_uring: limit size of provided buffer ring

The type of head and tail do not allow more than 2^15 entries in a
provided buffer ring, so do not allow this.
At 2^16 while each entry can be indexed, there is no way to
disambiguate full vs empty.

Signed-off-by: Dylan Yudaken <dylany@fb.com>
Link: https://lore.kernel.org/r/20220613101157.3687-4-dylany@fb.com
Reviewed-by: Hao Xu <howeyxu@tencent.com>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index 6eea18e8330c8..85b116ddfd2a9 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -13002,6 +13002,10 @@ static int io_register_pbuf_ring(struct io_ring_ctx *ctx, void __user *arg)
 	if (!is_power_of_2(reg.ring_entries))
 		return -EINVAL;
 
+	/* cannot disambiguate full vs empty due to head/tail size */
+	if (reg.ring_entries >= 65536)
+		return -EINVAL;
+
 	if (unlikely(reg.bgid < BGID_ARRAY && !ctx->io_bl)) {
 		int ret = io_init_bl_list(ctx);
 		if (ret)
-- 
GitLab


From 00be43a74ca262267ceb96c0c5e3f51d3a56342e Mon Sep 17 00:00:00 2001
From: Andy Chiu <andy.chiu@sifive.com>
Date: Mon, 13 Jun 2022 11:42:01 +0800
Subject: [PATCH 0499/1731] net: axienet: make the 64b addresable DMA depends
 on 64b archectures

Currently it is not safe to config the IP as 64-bit addressable on 32-bit
archectures, which cannot perform a double-word store on its descriptor
pointers. The pointer is 64-bit wide if the IP is configured as 64-bit,
and the device would process the partially updated pointer on some
states if the pointer was updated via two store-words. To prevent such
condition, we force a probe fail if we discover that the IP has 64-bit
capability but it is not running on a 64-Bit kernel.

This is a series of patch (1/2). The next patch must be applied in order
to make 64b DMA safe on 64b archectures.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reported-by: Max Hsu <max.hsu@sifive.com>
Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/xilinx/xilinx_axienet.h  | 36 +++++++++++++++++++
 .../net/ethernet/xilinx/xilinx_axienet_main.c | 28 +++------------
 2 files changed, 40 insertions(+), 24 deletions(-)

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h
index 4225efbeda3da..6c95676ba172a 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet.h
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
@@ -547,6 +547,42 @@ static inline void axienet_iow(struct axienet_local *lp, off_t offset,
 	iowrite32(value, lp->regs + offset);
 }
 
+/**
+ * axienet_dma_out32 - Memory mapped Axi DMA register write.
+ * @lp:		Pointer to axienet local structure
+ * @reg:	Address offset from the base address of the Axi DMA core
+ * @value:	Value to be written into the Axi DMA register
+ *
+ * This function writes the desired value into the corresponding Axi DMA
+ * register.
+ */
+
+static inline void axienet_dma_out32(struct axienet_local *lp,
+				     off_t reg, u32 value)
+{
+	iowrite32(value, lp->dma_regs + reg);
+}
+
+#ifdef CONFIG_64BIT
+static void axienet_dma_out_addr(struct axienet_local *lp, off_t reg,
+				 dma_addr_t addr)
+{
+	axienet_dma_out32(lp, reg, lower_32_bits(addr));
+
+	if (lp->features & XAE_FEATURE_DMA_64BIT)
+		axienet_dma_out32(lp, reg + 4, upper_32_bits(addr));
+}
+
+#else /* CONFIG_64BIT */
+
+static void axienet_dma_out_addr(struct axienet_local *lp, off_t reg,
+				 dma_addr_t addr)
+{
+	axienet_dma_out32(lp, reg, lower_32_bits(addr));
+}
+
+#endif /* CONFIG_64BIT */
+
 /* Function prototypes visible in xilinx_axienet_mdio.c for other files */
 int axienet_mdio_enable(struct axienet_local *lp);
 void axienet_mdio_disable(struct axienet_local *lp);
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index 93c9f305bba42..fa7bcd2c18928 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -133,30 +133,6 @@ static inline u32 axienet_dma_in32(struct axienet_local *lp, off_t reg)
 	return ioread32(lp->dma_regs + reg);
 }
 
-/**
- * axienet_dma_out32 - Memory mapped Axi DMA register write.
- * @lp:		Pointer to axienet local structure
- * @reg:	Address offset from the base address of the Axi DMA core
- * @value:	Value to be written into the Axi DMA register
- *
- * This function writes the desired value into the corresponding Axi DMA
- * register.
- */
-static inline void axienet_dma_out32(struct axienet_local *lp,
-				     off_t reg, u32 value)
-{
-	iowrite32(value, lp->dma_regs + reg);
-}
-
-static void axienet_dma_out_addr(struct axienet_local *lp, off_t reg,
-				 dma_addr_t addr)
-{
-	axienet_dma_out32(lp, reg, lower_32_bits(addr));
-
-	if (lp->features & XAE_FEATURE_DMA_64BIT)
-		axienet_dma_out32(lp, reg + 4, upper_32_bits(addr));
-}
-
 static void desc_set_phys_addr(struct axienet_local *lp, dma_addr_t addr,
 			       struct axidma_bd *desc)
 {
@@ -2061,6 +2037,10 @@ static int axienet_probe(struct platform_device *pdev)
 			iowrite32(0x0, desc);
 		}
 	}
+	if (!IS_ENABLED(CONFIG_64BIT) && lp->features & XAE_FEATURE_DMA_64BIT) {
+		dev_err(&pdev->dev, "64-bit addressable DMA is not compatible with 32-bit archecture\n");
+		goto cleanup_clk;
+	}
 
 	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_width));
 	if (ret) {
-- 
GitLab


From b690f8df6497b654c2c871871e0a598e9750c0eb Mon Sep 17 00:00:00 2001
From: Andy Chiu <andy.chiu@sifive.com>
Date: Mon, 13 Jun 2022 11:42:02 +0800
Subject: [PATCH 0500/1731] net: axienet: Use iowrite64 to write all 64b
 descriptor pointers

According to commit f735c40ed93c ("net: axienet: Autodetect 64-bit DMA
capability") and AXI-DMA spec (pg021), on 64-bit capable dma, only
writing MSB part of tail descriptor pointer causes DMA engine to start
fetching descriptors. However, we found that it is true only if dma is in
idle state. In other words, dma would use a tailp even if it only has LSB
updated, when the dma is running.

The non-atomicity of this behavior could be problematic if enough
delay were introduced in between the 2 writes. For example, if an
interrupt comes right after the LSB write and the cpu spends long
enough time in the handler for the dma to get back into idle state by
completing descriptors, then the seconcd write to MSB would treat dma
to start fetching descriptors again. Since the descriptor next to the
one pointed by current tail pointer is not filled by the kernel yet,
fetching a null descriptor here causes a dma internal error and halt
the dma engine down.

We suggest that the dma engine should start process a 64-bit MMIO write
to the descriptor pointer only if ONE 32-bit part of it is written on all
states. Or we should restrict the use of 64-bit addressable dma on 32-bit
platforms, since those devices have no instruction to guarantee the write
to LSB and MSB part of tail pointer occurs atomically to the dma.

initial condition:
curp =  x-3;
tailp = x-2;
LSB = x;
MSB = 0;

cpu:                       |dma:
 iowrite32(LSB, tailp)     |  completes #(x-3) desc, curp = x-3
 ...                       |  tailp updated
 => irq                    |  completes #(x-2) desc, curp = x-2
    ...                    |  completes #(x-1) desc, curp = x-1
    ...                    |  ...
    ...                    |  completes #x desc, curp = tailp = x
 <= irqreturn              |  reaches tailp == curp = x, idle
 iowrite32(MSB, tailp + 4) |  ...
                           |  tailp updated, starts fetching...
                           |  fetches #(x + 1) desc, sees cntrl = 0
                           |  post Tx error, halt

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reported-by: Max Hsu <max.hsu@sifive.com>
Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/xilinx/xilinx_axienet.h | 21 +++++++++++++++++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h
index 6c95676ba172a..97ddc0273b8a8 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet.h
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
@@ -564,13 +564,28 @@ static inline void axienet_dma_out32(struct axienet_local *lp,
 }
 
 #ifdef CONFIG_64BIT
+/**
+ * axienet_dma_out64 - Memory mapped Axi DMA register write.
+ * @lp:		Pointer to axienet local structure
+ * @reg:	Address offset from the base address of the Axi DMA core
+ * @value:	Value to be written into the Axi DMA register
+ *
+ * This function writes the desired value into the corresponding Axi DMA
+ * register.
+ */
+static inline void axienet_dma_out64(struct axienet_local *lp,
+				     off_t reg, u64 value)
+{
+	iowrite64(value, lp->dma_regs + reg);
+}
+
 static void axienet_dma_out_addr(struct axienet_local *lp, off_t reg,
 				 dma_addr_t addr)
 {
-	axienet_dma_out32(lp, reg, lower_32_bits(addr));
-
 	if (lp->features & XAE_FEATURE_DMA_64BIT)
-		axienet_dma_out32(lp, reg + 4, upper_32_bits(addr));
+		axienet_dma_out64(lp, reg, addr);
+	else
+		axienet_dma_out32(lp, reg, lower_32_bits(addr));
 }
 
 #else /* CONFIG_64BIT */
-- 
GitLab


From 5f7b84151a89f6f3a8d1db4db2bc4f5b270d66ee Mon Sep 17 00:00:00 2001
From: "David S. Miller" <davem@davemloft.net>
Date: Mon, 13 Jun 2022 12:49:21 +0100
Subject: [PATCH 0501/1731] xilinx:  Fix build on x86.

CONFIG_64BIT is not sufficient for checking for availability of
iowrite64() and friends.

Also, the out_addr helpers need to be inline.

Fixes: b690f8df6497 ("net: axienet: Use iowrite64 to write all 64b descriptor pointers")
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/xilinx/xilinx_axienet.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h
index 97ddc0273b8a8..f2e2261b4b7d9 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet.h
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
@@ -563,7 +563,7 @@ static inline void axienet_dma_out32(struct axienet_local *lp,
 	iowrite32(value, lp->dma_regs + reg);
 }
 
-#ifdef CONFIG_64BIT
+#if defined(CONFIG_64BIT) && defined(iowrite64)
 /**
  * axienet_dma_out64 - Memory mapped Axi DMA register write.
  * @lp:		Pointer to axienet local structure
@@ -579,8 +579,8 @@ static inline void axienet_dma_out64(struct axienet_local *lp,
 	iowrite64(value, lp->dma_regs + reg);
 }
 
-static void axienet_dma_out_addr(struct axienet_local *lp, off_t reg,
-				 dma_addr_t addr)
+static inline void axienet_dma_out_addr(struct axienet_local *lp, off_t reg,
+					dma_addr_t addr)
 {
 	if (lp->features & XAE_FEATURE_DMA_64BIT)
 		axienet_dma_out64(lp, reg, addr);
@@ -590,7 +590,7 @@ static void axienet_dma_out_addr(struct axienet_local *lp, off_t reg,
 
 #else /* CONFIG_64BIT */
 
-static void axienet_dma_out_addr(struct axienet_local *lp, off_t reg,
+static inline void axienet_dma_out_addr(struct axienet_local *lp, off_t reg,
 				 dma_addr_t addr)
 {
 	axienet_dma_out32(lp, reg, lower_32_bits(addr));
-- 
GitLab


From 619c010a65391d06bc96e79fa0e7725790e5d1a9 Mon Sep 17 00:00:00 2001
From: Suman Ghosh <sumang@marvell.com>
Date: Sun, 12 Jun 2022 23:15:36 +0530
Subject: [PATCH 0502/1731] octeontx2-vf: Add support for adaptive interrupt
 coalescing

Fixes: 6e144b47f560 (octeontx2-pf: Add support for adaptive interrupt coalescing)
Added support for VF interfaces as well.

Signed-off-by: Suman Ghosh <sumang@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c
index bc614a4def9ef..3f60a80e34c82 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c
@@ -1390,7 +1390,8 @@ static int otx2vf_get_link_ksettings(struct net_device *netdev,
 
 static const struct ethtool_ops otx2vf_ethtool_ops = {
 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |
-				     ETHTOOL_COALESCE_MAX_FRAMES,
+				     ETHTOOL_COALESCE_MAX_FRAMES |
+				     ETHTOOL_COALESCE_USE_ADAPTIVE,
 	.supported_ring_params  = ETHTOOL_RING_USE_RX_BUF_LEN |
 				  ETHTOOL_RING_USE_CQE_SIZE,
 	.get_link		= otx2_get_link,
-- 
GitLab


From 6e21408774da49b34fbe258d161e6329a43fcbe8 Mon Sep 17 00:00:00 2001
From: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Date: Mon, 13 Jun 2022 13:46:14 +0200
Subject: [PATCH 0503/1731] MAINTAINERS: add include/dt-bindings/i2c to I2C
 SUBSYSTEM HOST DRIVERS

Maintainers of the directory Documentation/devicetree/bindings/i2c
are also the maintainers of the corresponding directory
include/dt-bindings/i2c.

Add the file entry for include/dt-bindings/i2c to the appropriate
section in MAINTAINERS.

Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index cb2342ce3b55a..d6de26c5bd5d2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9283,6 +9283,7 @@ T:	git git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git
 F:	Documentation/devicetree/bindings/i2c/
 F:	drivers/i2c/algos/
 F:	drivers/i2c/busses/
+F:	include/dt-bindings/i2c/
 
 I2C-TAOS-EVM DRIVER
 M:	Jean Delvare <jdelvare@suse.com>
-- 
GitLab


From 5edc99f0c5b753eb34defad1cdb164824056a487 Mon Sep 17 00:00:00 2001
From: Wolfram Sang <wsa@kernel.org>
Date: Mon, 13 Jun 2022 16:45:19 +0200
Subject: [PATCH 0504/1731] MAINTAINERS: core DT include belongs to core

Signed-off-by: Wolfram Sang <wsa@kernel.org>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index d6de26c5bd5d2..c512a083d6590 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9268,6 +9268,7 @@ T:	git git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git
 F:	Documentation/devicetree/bindings/i2c/i2c.txt
 F:	Documentation/i2c/
 F:	drivers/i2c/*
+F:	include/dt-bindings/i2c/i2c.h
 F:	include/linux/i2c-dev.h
 F:	include/linux/i2c-smbus.h
 F:	include/linux/i2c.h
-- 
GitLab


From 27071b5cbca59d8e8f8750c199a6cbf8c9799963 Mon Sep 17 00:00:00 2001
From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Date: Fri, 10 Jun 2022 10:42:33 +0300
Subject: [PATCH 0505/1731] i2c: designware: Use standard optional ref clock
 implementation

Even though the DW I2C controller reference clock source is requested by
the method devm_clk_get() with non-optional clock requirement the way the
clock handler is used afterwards has a pure optional clock semantic
(though in some circumstances we can get a warning about the clock missing
printed in the system console). There is no point in reimplementing that
functionality seeing the kernel clock framework already supports the
optional interface from scratch. Thus let's convert the platform driver to
using it.

Note by providing this commit we get to fix two problems. The first one
was introduced in commit c62ebb3d5f0d ("i2c: designware: Add support for
an interface clock"). It causes not having the interface clock (pclk)
enabled/disabled in case if the reference clock isn't provided. The second
problem was first introduced in commit b33af11de236 ("i2c: designware: Do
not require clock when SSCN and FFCN are provided"). Since that
modification the deferred probe procedure has been unsupported in case if
the interface clock isn't ready.

Fixes: c62ebb3d5f0d ("i2c: designware: Add support for an interface clock")
Fixes: b33af11de236 ("i2c: designware: Do not require clock when SSCN and FFCN are provided")
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
---
 drivers/i2c/busses/i2c-designware-common.c  |  3 ---
 drivers/i2c/busses/i2c-designware-platdrv.c | 13 +++++++++++--
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busses/i2c-designware-common.c
index e7d316b1401a1..c023b691441ea 100644
--- a/drivers/i2c/busses/i2c-designware-common.c
+++ b/drivers/i2c/busses/i2c-designware-common.c
@@ -477,9 +477,6 @@ int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare)
 {
 	int ret;
 
-	if (IS_ERR(dev->clk))
-		return PTR_ERR(dev->clk);
-
 	if (prepare) {
 		/* Optional interface clock */
 		ret = clk_prepare_enable(dev->pclk);
diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
index 70ade5306e458..ba043b5473936 100644
--- a/drivers/i2c/busses/i2c-designware-platdrv.c
+++ b/drivers/i2c/busses/i2c-designware-platdrv.c
@@ -320,8 +320,17 @@ static int dw_i2c_plat_probe(struct platform_device *pdev)
 		goto exit_reset;
 	}
 
-	dev->clk = devm_clk_get(&pdev->dev, NULL);
-	if (!i2c_dw_prepare_clk(dev, true)) {
+	dev->clk = devm_clk_get_optional(&pdev->dev, NULL);
+	if (IS_ERR(dev->clk)) {
+		ret = PTR_ERR(dev->clk);
+		goto exit_reset;
+	}
+
+	ret = i2c_dw_prepare_clk(dev, true);
+	if (ret)
+		goto exit_reset;
+
+	if (dev->clk) {
 		u64 clk_khz;
 
 		dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
-- 
GitLab


From c4cf6785599b8126ea29160800fec5f1db0a6a30 Mon Sep 17 00:00:00 2001
From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date: Tue, 7 Jun 2022 17:20:10 +0200
Subject: [PATCH 0506/1731] mm/slub: Move the stackdepot related allocation out
 of IRQ-off section.

The set_track() invocation in free_debug_processing() is invoked with
acquired slab_lock(). The lock disables interrupts on PREEMPT_RT and
this forbids to allocate memory which is done in stack_depot_save().

Split set_track() into two parts: set_track_prepare() which allocate
memory and set_track_update() which only performs the assignment of the
trace data structure. Use set_track_prepare() before disabling
interrupts.

[ vbabka@suse.cz: make set_track() call set_track_update() instead of
  open-coded assignments ]

Fixes: 5cf909c553e9e ("mm/slub: use stackdepot to save stack trace in objects")
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-by: Hyeonggon Yoo <42.hyeyoo@gmail.com>
Signed-off-by: Vlastimil Babka <vbabka@suse.cz>
Link: https://lore.kernel.org/r/Yp9sqoUi4fVa5ExF@linutronix.de
---
 mm/slub.c | 41 ++++++++++++++++++++++++++++++++++-------
 1 file changed, 34 insertions(+), 7 deletions(-)

diff --git a/mm/slub.c b/mm/slub.c
index e5535020e0fdf..a5b14c1dfd86f 100644
--- a/mm/slub.c
+++ b/mm/slub.c
@@ -726,25 +726,48 @@ static struct track *get_track(struct kmem_cache *s, void *object,
 	return kasan_reset_tag(p + alloc);
 }
 
-static void noinline set_track(struct kmem_cache *s, void *object,
-			enum track_item alloc, unsigned long addr)
-{
-	struct track *p = get_track(s, object, alloc);
-
 #ifdef CONFIG_STACKDEPOT
+static noinline depot_stack_handle_t set_track_prepare(void)
+{
+	depot_stack_handle_t handle;
 	unsigned long entries[TRACK_ADDRS_COUNT];
 	unsigned int nr_entries;
 
 	nr_entries = stack_trace_save(entries, ARRAY_SIZE(entries), 3);
-	p->handle = stack_depot_save(entries, nr_entries, GFP_NOWAIT);
+	handle = stack_depot_save(entries, nr_entries, GFP_NOWAIT);
+
+	return handle;
+}
+#else
+static inline depot_stack_handle_t set_track_prepare(void)
+{
+	return 0;
+}
 #endif
 
+static void set_track_update(struct kmem_cache *s, void *object,
+			     enum track_item alloc, unsigned long addr,
+			     depot_stack_handle_t handle)
+{
+	struct track *p = get_track(s, object, alloc);
+
+#ifdef CONFIG_STACKDEPOT
+	p->handle = handle;
+#endif
 	p->addr = addr;
 	p->cpu = smp_processor_id();
 	p->pid = current->pid;
 	p->when = jiffies;
 }
 
+static __always_inline void set_track(struct kmem_cache *s, void *object,
+				      enum track_item alloc, unsigned long addr)
+{
+	depot_stack_handle_t handle = set_track_prepare();
+
+	set_track_update(s, object, alloc, addr, handle);
+}
+
 static void init_tracking(struct kmem_cache *s, void *object)
 {
 	struct track *p;
@@ -1373,6 +1396,10 @@ static noinline int free_debug_processing(
 	int cnt = 0;
 	unsigned long flags, flags2;
 	int ret = 0;
+	depot_stack_handle_t handle = 0;
+
+	if (s->flags & SLAB_STORE_USER)
+		handle = set_track_prepare();
 
 	spin_lock_irqsave(&n->list_lock, flags);
 	slab_lock(slab, &flags2);
@@ -1391,7 +1418,7 @@ next_object:
 	}
 
 	if (s->flags & SLAB_STORE_USER)
-		set_track(s, object, TRACK_FREE, addr);
+		set_track_update(s, object, TRACK_FREE, addr, handle);
 	trace(s, slab, object, 0);
 	/* Freepointer not overwritten by init_object(), SLAB_POISON moved it */
 	init_object(s, object, SLUB_RED_INACTIVE);
-- 
GitLab


From eeaa345e128515135ccb864c04482180c08e3259 Mon Sep 17 00:00:00 2001
From: Jann Horn <jannh@google.com>
Date: Wed, 8 Jun 2022 20:22:05 +0200
Subject: [PATCH 0507/1731] mm/slub: add missing TID updates on slab
 deactivation

The fastpath in slab_alloc_node() assumes that c->slab is stable as long as
the TID stays the same. However, two places in __slab_alloc() currently
don't update the TID when deactivating the CPU slab.

If multiple operations race the right way, this could lead to an object
getting lost; or, in an even more unlikely situation, it could even lead to
an object being freed onto the wrong slab's freelist, messing up the
`inuse` counter and eventually causing a page to be freed to the page
allocator while it still contains slab objects.

(I haven't actually tested these cases though, this is just based on
looking at the code. Writing testcases for this stuff seems like it'd be
a pain...)

The race leading to state inconsistency is (all operations on the same CPU
and kmem_cache):

 - task A: begin do_slab_free():
    - read TID
    - read pcpu freelist (==NULL)
    - check `slab == c->slab` (true)
 - [PREEMPT A->B]
 - task B: begin slab_alloc_node():
    - fastpath fails (`c->freelist` is NULL)
    - enter __slab_alloc()
    - slub_get_cpu_ptr() (disables preemption)
    - enter ___slab_alloc()
    - take local_lock_irqsave()
    - read c->freelist as NULL
    - get_freelist() returns NULL
    - write `c->slab = NULL`
    - drop local_unlock_irqrestore()
    - goto new_slab
    - slub_percpu_partial() is NULL
    - get_partial() returns NULL
    - slub_put_cpu_ptr() (enables preemption)
 - [PREEMPT B->A]
 - task A: finish do_slab_free():
    - this_cpu_cmpxchg_double() succeeds()
    - [CORRUPT STATE: c->slab==NULL, c->freelist!=NULL]

From there, the object on c->freelist will get lost if task B is allowed to
continue from here: It will proceed to the retry_load_slab label,
set c->slab, then jump to load_freelist, which clobbers c->freelist.

But if we instead continue as follows, we get worse corruption:

 - task A: run __slab_free() on object from other struct slab:
    - CPU_PARTIAL_FREE case (slab was on no list, is now on pcpu partial)
 - task A: run slab_alloc_node() with NUMA node constraint:
    - fastpath fails (c->slab is NULL)
    - call __slab_alloc()
    - slub_get_cpu_ptr() (disables preemption)
    - enter ___slab_alloc()
    - c->slab is NULL: goto new_slab
    - slub_percpu_partial() is non-NULL
    - set c->slab to slub_percpu_partial(c)
    - [CORRUPT STATE: c->slab points to slab-1, c->freelist has objects
      from slab-2]
    - goto redo
    - node_match() fails
    - goto deactivate_slab
    - existing c->freelist is passed into deactivate_slab()
    - inuse count of slab-1 is decremented to account for object from
      slab-2

At this point, the inuse count of slab-1 is 1 lower than it should be.
This means that if we free all allocated objects in slab-1 except for one,
SLUB will think that slab-1 is completely unused, and may free its page,
leading to use-after-free.

Fixes: c17dda40a6a4e ("slub: Separate out kmem_cache_cpu processing from deactivate_slab")
Fixes: 03e404af26dc2 ("slub: fast release on full slab")
Cc: stable@vger.kernel.org
Signed-off-by: Jann Horn <jannh@google.com>
Acked-by: Christoph Lameter <cl@linux.com>
Acked-by: David Rientjes <rientjes@google.com>
Reviewed-by: Muchun Song <songmuchun@bytedance.com>
Tested-by: Hyeonggon Yoo <42.hyeyoo@gmail.com>
Signed-off-by: Vlastimil Babka <vbabka@suse.cz>
Link: https://lore.kernel.org/r/20220608182205.2945720-1-jannh@google.com
---
 mm/slub.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/mm/slub.c b/mm/slub.c
index a5b14c1dfd86f..b1281b8654bd3 100644
--- a/mm/slub.c
+++ b/mm/slub.c
@@ -2963,6 +2963,7 @@ redo:
 
 	if (!freelist) {
 		c->slab = NULL;
+		c->tid = next_tid(c->tid);
 		local_unlock_irqrestore(&s->cpu_slab->lock, flags);
 		stat(s, DEACTIVATE_BYPASS);
 		goto new_slab;
@@ -2995,6 +2996,7 @@ deactivate_slab:
 	freelist = c->freelist;
 	c->slab = NULL;
 	c->freelist = NULL;
+	c->tid = next_tid(c->tid);
 	local_unlock_irqrestore(&s->cpu_slab->lock, flags);
 	deactivate_slab(s, slab, freelist);
 
-- 
GitLab


From fe6900bd8156467365bd5b976df64928fdebfeb0 Mon Sep 17 00:00:00 2001
From: Kailang Yang <kailang@realtek.com>
Date: Mon, 13 Jun 2022 14:57:19 +0800
Subject: [PATCH 0508/1731] ALSA: hda/realtek - ALC897 headset MIC no sound

There is not have Headset Mic verb table in BIOS default.
So, it will have recording issue from headset MIC.
Add the verb table value without jack detect. It will turn on Headset Mic.

Signed-off-by: Kailang Yang <kailang@realtek.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/719133a27d8844a890002cb817001dfa@realtek.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/pci/hda/patch_realtek.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index a1a7842e7b5f3..9b6ee775ee3ff 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -10738,6 +10738,7 @@ enum {
 	ALC668_FIXUP_MIC_DET_COEF,
 	ALC897_FIXUP_LENOVO_HEADSET_MIC,
 	ALC897_FIXUP_HEADSET_MIC_PIN,
+	ALC897_FIXUP_HP_HSMIC_VERB,
 };
 
 static const struct hda_fixup alc662_fixups[] = {
@@ -11157,6 +11158,13 @@ static const struct hda_fixup alc662_fixups[] = {
 		.chained = true,
 		.chain_id = ALC897_FIXUP_LENOVO_HEADSET_MIC
 	},
+	[ALC897_FIXUP_HP_HSMIC_VERB] = {
+		.type = HDA_FIXUP_PINS,
+		.v.pins = (const struct hda_pintbl[]) {
+			{ 0x19, 0x01a1913c }, /* use as headset mic, without its own jack detect */
+			{ }
+		},
+	},
 };
 
 static const struct snd_pci_quirk alc662_fixup_tbl[] = {
@@ -11182,6 +11190,7 @@ static const struct snd_pci_quirk alc662_fixup_tbl[] = {
 	SND_PCI_QUIRK(0x1028, 0x0698, "Dell", ALC668_FIXUP_DELL_MIC_NO_PRESENCE),
 	SND_PCI_QUIRK(0x1028, 0x069f, "Dell", ALC668_FIXUP_DELL_MIC_NO_PRESENCE),
 	SND_PCI_QUIRK(0x103c, 0x1632, "HP RP5800", ALC662_FIXUP_HP_RP5800),
+	SND_PCI_QUIRK(0x103c, 0x8719, "HP", ALC897_FIXUP_HP_HSMIC_VERB),
 	SND_PCI_QUIRK(0x103c, 0x873e, "HP", ALC671_FIXUP_HP_HEADSET_MIC2),
 	SND_PCI_QUIRK(0x103c, 0x885f, "HP 288 Pro G8", ALC671_FIXUP_HP_HEADSET_MIC2),
 	SND_PCI_QUIRK(0x1043, 0x1080, "Asus UX501VW", ALC668_FIXUP_HEADSET_MODE),
-- 
GitLab


From 97a4087a363888b818225d890c912a52a24b9f73 Mon Sep 17 00:00:00 2001
From: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Date: Mon, 13 Jun 2022 13:11:34 +0200
Subject: [PATCH 0509/1731] MAINTAINERS: add include/dt-bindings/gpio to GPIO
 SUBSYSTEM

Maintainers of the directory Documentation/devicetree/bindings/gpio
are also the maintainers of the corresponding directory
include/dt-bindings/gpio.

Add the file entry for include/dt-bindings/gpio to the appropriate
section in MAINTAINERS.

Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 1fc9ead83d2aa..ef73aaae2bd2b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8479,6 +8479,7 @@ F:	Documentation/devicetree/bindings/gpio/
 F:	Documentation/driver-api/gpio/
 F:	drivers/gpio/
 F:	include/asm-generic/gpio.h
+F:	include/dt-bindings/gpio/
 F:	include/linux/gpio.h
 F:	include/linux/gpio/
 F:	include/linux/of_gpio.h
-- 
GitLab


From 30756cc1645080445c957192bc8a7af3b193d617 Mon Sep 17 00:00:00 2001
From: Tom Schwindl <schwindl@posteo.de>
Date: Sun, 12 Jun 2022 19:01:09 +0000
Subject: [PATCH 0510/1731] docs: driver-api: gpio: Fix filename mismatch

The filenames were changed a while ago, but board.rst, consumer.rst and
intro.rst still refer to the old names. Fix those references to match the
Actual names and avoid possible confusion.

Signed-off-by: Tom Schwindl <schwindl@posteo.de>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
---
 Documentation/driver-api/gpio/board.rst    | 2 +-
 Documentation/driver-api/gpio/consumer.rst | 6 +++---
 Documentation/driver-api/gpio/intro.rst    | 6 +++---
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/Documentation/driver-api/gpio/board.rst b/Documentation/driver-api/gpio/board.rst
index 4e3adf31c8d1d..b33aa04f213fe 100644
--- a/Documentation/driver-api/gpio/board.rst
+++ b/Documentation/driver-api/gpio/board.rst
@@ -6,7 +6,7 @@ This document explains how GPIOs can be assigned to given devices and functions.
 
 Note that it only applies to the new descriptor-based interface. For a
 description of the deprecated integer-based GPIO interface please refer to
-gpio-legacy.txt (actually, there is no real mapping possible with the old
+legacy.rst (actually, there is no real mapping possible with the old
 interface; you just fetch an integer from somewhere and request the
 corresponding GPIO).
 
diff --git a/Documentation/driver-api/gpio/consumer.rst b/Documentation/driver-api/gpio/consumer.rst
index 47869ca8ccf03..72bcf5f5e3a21 100644
--- a/Documentation/driver-api/gpio/consumer.rst
+++ b/Documentation/driver-api/gpio/consumer.rst
@@ -4,7 +4,7 @@ GPIO Descriptor Consumer Interface
 
 This document describes the consumer interface of the GPIO framework. Note that
 it describes the new descriptor-based interface. For a description of the
-deprecated integer-based GPIO interface please refer to gpio-legacy.txt.
+deprecated integer-based GPIO interface please refer to legacy.rst.
 
 
 Guidelines for GPIOs consumers
@@ -78,7 +78,7 @@ whether the line is configured active high or active low (see
 
 The two last flags are used for use cases where open drain is mandatory, such
 as I2C: if the line is not already configured as open drain in the mappings
-(see board.txt), then open drain will be enforced anyway and a warning will be
+(see board.rst), then open drain will be enforced anyway and a warning will be
 printed that the board configuration needs to be updated to match the use case.
 
 Both functions return either a valid GPIO descriptor, or an error code checkable
@@ -270,7 +270,7 @@ driven.
 The same is applicable for open drain or open source output lines: those do not
 actively drive their output high (open drain) or low (open source), they just
 switch their output to a high impedance value. The consumer should not need to
-care. (For details read about open drain in driver.txt.)
+care. (For details read about open drain in driver.rst.)
 
 With this, all the gpiod_set_(array)_value_xxx() functions interpret the
 parameter "value" as "asserted" ("1") or "de-asserted" ("0"). The physical line
diff --git a/Documentation/driver-api/gpio/intro.rst b/Documentation/driver-api/gpio/intro.rst
index 2e924fb5b3d53..c9c19243b97f8 100644
--- a/Documentation/driver-api/gpio/intro.rst
+++ b/Documentation/driver-api/gpio/intro.rst
@@ -14,12 +14,12 @@ Due to the history of GPIO interfaces in the kernel, there are two different
 ways to obtain and use GPIOs:
 
   - The descriptor-based interface is the preferred way to manipulate GPIOs,
-    and is described by all the files in this directory excepted gpio-legacy.txt.
+    and is described by all the files in this directory excepted legacy.rst.
   - The legacy integer-based interface which is considered deprecated (but still
-    usable for compatibility reasons) is documented in gpio-legacy.txt.
+    usable for compatibility reasons) is documented in legacy.rst.
 
 The remainder of this document applies to the new descriptor-based interface.
-gpio-legacy.txt contains the same information applied to the legacy
+legacy.rst contains the same information applied to the legacy
 integer-based interface.
 
 
-- 
GitLab


From a01a40e334996b05df92d5a9d594cb5937dd3cc0 Mon Sep 17 00:00:00 2001
From: Sander Vanheule <sander@svanheule.net>
Date: Sun, 12 Jun 2022 13:23:09 +0200
Subject: [PATCH 0511/1731] gpio: realtek-otto: Make the irqchip immutable

Since commit 6c846d026d49 ("gpio: Don't fiddle with irqchips marked as
immutable") a warning is issued for the realtek-otto driver:

    gpio gpiochip0: (18003500.gpio): not an immutable chip, please consider fixing it!

Make the driver's irqchip immutable to fix this.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
---
 drivers/gpio/gpio-realtek-otto.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-realtek-otto.c b/drivers/gpio/gpio-realtek-otto.c
index c52b2cb1acaeb..63dcf42f7c206 100644
--- a/drivers/gpio/gpio-realtek-otto.c
+++ b/drivers/gpio/gpio-realtek-otto.c
@@ -172,6 +172,8 @@ static void realtek_gpio_irq_unmask(struct irq_data *data)
 	unsigned long flags;
 	u16 m;
 
+	gpiochip_enable_irq(&ctrl->gc, line);
+
 	raw_spin_lock_irqsave(&ctrl->lock, flags);
 	m = ctrl->intr_mask[port];
 	m |= realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK);
@@ -195,6 +197,8 @@ static void realtek_gpio_irq_mask(struct irq_data *data)
 	ctrl->intr_mask[port] = m;
 	realtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m);
 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
+
+	gpiochip_disable_irq(&ctrl->gc, line);
 }
 
 static int realtek_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
@@ -315,13 +319,15 @@ static int realtek_gpio_irq_init(struct gpio_chip *gc)
 	return 0;
 }
 
-static struct irq_chip realtek_gpio_irq_chip = {
+static const struct irq_chip realtek_gpio_irq_chip = {
 	.name = "realtek-otto-gpio",
 	.irq_ack = realtek_gpio_irq_ack,
 	.irq_mask = realtek_gpio_irq_mask,
 	.irq_unmask = realtek_gpio_irq_unmask,
 	.irq_set_type = realtek_gpio_irq_set_type,
 	.irq_set_affinity = realtek_gpio_irq_set_affinity,
+	.flags = IRQCHIP_IMMUTABLE,
+	GPIOCHIP_IRQ_RESOURCE_HELPERS,
 };
 
 static const struct of_device_id realtek_gpio_of_match[] = {
@@ -404,7 +410,7 @@ static int realtek_gpio_probe(struct platform_device *pdev)
 	irq = platform_get_irq_optional(pdev, 0);
 	if (!(dev_flags & GPIO_INTERRUPTS_DISABLED) && irq > 0) {
 		girq = &ctrl->gc.irq;
-		girq->chip = &realtek_gpio_irq_chip;
+		gpio_irq_chip_set_chip(girq, &realtek_gpio_irq_chip);
 		girq->default_type = IRQ_TYPE_NONE;
 		girq->handler = handle_bad_irq;
 		girq->parent_handler = realtek_gpio_irq_handler;
-- 
GitLab


From 57cd6d157eb479f0a8e820fd36b7240845c8a937 Mon Sep 17 00:00:00 2001
From: Sami Tolvanen <samitolvanen@google.com>
Date: Tue, 31 May 2022 10:59:10 -0700
Subject: [PATCH 0512/1731] cfi: Fix __cfi_slowpath_diag RCU usage with cpuidle

RCU_NONIDLE usage during __cfi_slowpath_diag can result in an invalid
RCU state in the cpuidle code path:

  WARNING: CPU: 1 PID: 0 at kernel/rcu/tree.c:613 rcu_eqs_enter+0xe4/0x138
  ...
  Call trace:
    rcu_eqs_enter+0xe4/0x138
    rcu_idle_enter+0xa8/0x100
    cpuidle_enter_state+0x154/0x3a8
    cpuidle_enter+0x3c/0x58
    do_idle.llvm.6590768638138871020+0x1f4/0x2ec
    cpu_startup_entry+0x28/0x2c
    secondary_start_kernel+0x1b8/0x220
    __secondary_switched+0x94/0x98

Instead, call rcu_irq_enter/exit to wake up RCU only when needed and
disable interrupts for the entire CFI shadow/module check when we do.

Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
Link: https://lore.kernel.org/r/20220531175910.890307-1-samitolvanen@google.com
Fixes: cf68fffb66d6 ("add support for Clang CFI")
Cc: stable@vger.kernel.org
Signed-off-by: Kees Cook <keescook@chromium.org>
---
 kernel/cfi.c | 22 ++++++++++++++++------
 1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/kernel/cfi.c b/kernel/cfi.c
index 9594cfd1cf2cf..08102d19ec15a 100644
--- a/kernel/cfi.c
+++ b/kernel/cfi.c
@@ -281,6 +281,8 @@ static inline cfi_check_fn find_module_check_fn(unsigned long ptr)
 static inline cfi_check_fn find_check_fn(unsigned long ptr)
 {
 	cfi_check_fn fn = NULL;
+	unsigned long flags;
+	bool rcu_idle;
 
 	if (is_kernel_text(ptr))
 		return __cfi_check;
@@ -290,13 +292,21 @@ static inline cfi_check_fn find_check_fn(unsigned long ptr)
 	 * the shadow and __module_address use RCU, so we need to wake it
 	 * up if necessary.
 	 */
-	RCU_NONIDLE({
-		if (IS_ENABLED(CONFIG_CFI_CLANG_SHADOW))
-			fn = find_shadow_check_fn(ptr);
+	rcu_idle = !rcu_is_watching();
+	if (rcu_idle) {
+		local_irq_save(flags);
+		rcu_irq_enter();
+	}
+
+	if (IS_ENABLED(CONFIG_CFI_CLANG_SHADOW))
+		fn = find_shadow_check_fn(ptr);
+	if (!fn)
+		fn = find_module_check_fn(ptr);
 
-		if (!fn)
-			fn = find_module_check_fn(ptr);
-	});
+	if (rcu_idle) {
+		rcu_irq_exit();
+		local_irq_restore(flags);
+	}
 
 	return fn;
 }
-- 
GitLab


From 993d0b287e2ef7bee2e8b13b0ce4d2b5066f278e Mon Sep 17 00:00:00 2001
From: "Matthew Wilcox (Oracle)" <willy@infradead.org>
Date: Sun, 12 Jun 2022 22:32:25 +0100
Subject: [PATCH 0513/1731] usercopy: Handle vm_map_ram() areas

vmalloc does not allocate a vm_struct for vm_map_ram() areas.  That causes
us to deny usercopies from those areas.  This affects XFS which uses
vm_map_ram() for its directories.

Fix this by calling find_vmap_area() instead of find_vm_area().

Fixes: 0aef499f3172 ("mm/usercopy: Detect vmalloc overruns")
Signed-off-by: Matthew Wilcox (Oracle) <willy@infradead.org>
Reviewed-by: Uladzislau Rezki (Sony) <urezki@gmail.com>
Tested-by: Zorro Lang <zlang@redhat.com>
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/20220612213227.3881769-2-willy@infradead.org
---
 include/linux/vmalloc.h |  1 +
 mm/usercopy.c           | 10 ++++------
 mm/vmalloc.c            |  2 +-
 3 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/include/linux/vmalloc.h b/include/linux/vmalloc.h
index b159c27899612..096d48aa34373 100644
--- a/include/linux/vmalloc.h
+++ b/include/linux/vmalloc.h
@@ -215,6 +215,7 @@ extern struct vm_struct *__get_vm_area_caller(unsigned long size,
 void free_vm_area(struct vm_struct *area);
 extern struct vm_struct *remove_vm_area(const void *addr);
 extern struct vm_struct *find_vm_area(const void *addr);
+struct vmap_area *find_vmap_area(unsigned long addr);
 
 static inline bool is_vm_area_hugepages(const void *addr)
 {
diff --git a/mm/usercopy.c b/mm/usercopy.c
index baeacc735b83f..cd4b41d9bf760 100644
--- a/mm/usercopy.c
+++ b/mm/usercopy.c
@@ -173,16 +173,14 @@ static inline void check_heap_object(const void *ptr, unsigned long n,
 	}
 
 	if (is_vmalloc_addr(ptr)) {
-		struct vm_struct *area = find_vm_area(ptr);
+		struct vmap_area *area = find_vmap_area((unsigned long)ptr);
 		unsigned long offset;
 
-		if (!area) {
+		if (!area)
 			usercopy_abort("vmalloc", "no area", to_user, 0, n);
-			return;
-		}
 
-		offset = ptr - area->addr;
-		if (offset + n > get_vm_area_size(area))
+		offset = (unsigned long)ptr - area->va_start;
+		if ((unsigned long)ptr + n > area->va_end)
 			usercopy_abort("vmalloc", NULL, to_user, offset, n);
 		return;
 	}
diff --git a/mm/vmalloc.c b/mm/vmalloc.c
index 07db42455dd4d..effd1ff6a4b41 100644
--- a/mm/vmalloc.c
+++ b/mm/vmalloc.c
@@ -1798,7 +1798,7 @@ static void free_unmap_vmap_area(struct vmap_area *va)
 	free_vmap_area_noflush(va);
 }
 
-static struct vmap_area *find_vmap_area(unsigned long addr)
+struct vmap_area *find_vmap_area(unsigned long addr)
 {
 	struct vmap_area *va;
 
-- 
GitLab


From 35fb9ae4aa2e838b234323e6f7cf6336ff019e5a Mon Sep 17 00:00:00 2001
From: "Matthew Wilcox (Oracle)" <willy@infradead.org>
Date: Sun, 12 Jun 2022 22:32:26 +0100
Subject: [PATCH 0514/1731] usercopy: Cast pointer to an integer once

Get rid of a lot of annoying casts by setting 'addr' once at the top
of the function.

Signed-off-by: Matthew Wilcox (Oracle) <willy@infradead.org>
Reviewed-by: Uladzislau Rezki (Sony) <urezki@gmail.com>
Tested-by: Zorro Lang <zlang@redhat.com>
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/20220612213227.3881769-3-willy@infradead.org
---
 mm/usercopy.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/mm/usercopy.c b/mm/usercopy.c
index cd4b41d9bf760..30a4db3cb1df4 100644
--- a/mm/usercopy.c
+++ b/mm/usercopy.c
@@ -161,26 +161,27 @@ static inline void check_bogus_address(const unsigned long ptr, unsigned long n,
 static inline void check_heap_object(const void *ptr, unsigned long n,
 				     bool to_user)
 {
+	uintptr_t addr = (uintptr_t)ptr;
 	struct folio *folio;
 
 	if (is_kmap_addr(ptr)) {
-		unsigned long page_end = (unsigned long)ptr | (PAGE_SIZE - 1);
+		unsigned long page_end = addr | (PAGE_SIZE - 1);
 
-		if ((unsigned long)ptr + n - 1 > page_end)
+		if (addr + n - 1 > page_end)
 			usercopy_abort("kmap", NULL, to_user,
 					offset_in_page(ptr), n);
 		return;
 	}
 
 	if (is_vmalloc_addr(ptr)) {
-		struct vmap_area *area = find_vmap_area((unsigned long)ptr);
+		struct vmap_area *area = find_vmap_area(addr);
 		unsigned long offset;
 
 		if (!area)
 			usercopy_abort("vmalloc", "no area", to_user, 0, n);
 
-		offset = (unsigned long)ptr - area->va_start;
-		if ((unsigned long)ptr + n > area->va_end)
+		offset = addr - area->va_start;
+		if (addr + n > area->va_end)
 			usercopy_abort("vmalloc", NULL, to_user, offset, n);
 		return;
 	}
-- 
GitLab


From 1dfbe9fcda4afc957f0e371e207ae3cb7e8f3b0e Mon Sep 17 00:00:00 2001
From: "Matthew Wilcox (Oracle)" <willy@infradead.org>
Date: Sun, 12 Jun 2022 22:32:27 +0100
Subject: [PATCH 0515/1731] usercopy: Make usercopy resilient against
 ridiculously large copies

If 'n' is so large that it's negative, we might wrap around and mistakenly
think that the copy is OK when it's not.  Such a copy would probably
crash, but just doing the arithmetic in a more simple way lets us detect
and refuse this case.

Signed-off-by: Matthew Wilcox (Oracle) <willy@infradead.org>
Reviewed-by: Uladzislau Rezki (Sony) <urezki@gmail.com>
Tested-by: Zorro Lang <zlang@redhat.com>
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/20220612213227.3881769-4-willy@infradead.org
---
 mm/usercopy.c | 19 +++++++++----------
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/mm/usercopy.c b/mm/usercopy.c
index 30a4db3cb1df4..4e1da708699bb 100644
--- a/mm/usercopy.c
+++ b/mm/usercopy.c
@@ -162,27 +162,26 @@ static inline void check_heap_object(const void *ptr, unsigned long n,
 				     bool to_user)
 {
 	uintptr_t addr = (uintptr_t)ptr;
+	unsigned long offset;
 	struct folio *folio;
 
 	if (is_kmap_addr(ptr)) {
-		unsigned long page_end = addr | (PAGE_SIZE - 1);
-
-		if (addr + n - 1 > page_end)
-			usercopy_abort("kmap", NULL, to_user,
-					offset_in_page(ptr), n);
+		offset = offset_in_page(ptr);
+		if (n > PAGE_SIZE - offset)
+			usercopy_abort("kmap", NULL, to_user, offset, n);
 		return;
 	}
 
 	if (is_vmalloc_addr(ptr)) {
 		struct vmap_area *area = find_vmap_area(addr);
-		unsigned long offset;
 
 		if (!area)
 			usercopy_abort("vmalloc", "no area", to_user, 0, n);
 
-		offset = addr - area->va_start;
-		if (addr + n > area->va_end)
+		if (n > area->va_end - addr) {
+			offset = addr - area->va_start;
 			usercopy_abort("vmalloc", NULL, to_user, offset, n);
+		}
 		return;
 	}
 
@@ -195,8 +194,8 @@ static inline void check_heap_object(const void *ptr, unsigned long n,
 		/* Check slab allocator for flags and size. */
 		__check_heap_object(ptr, n, folio_slab(folio), to_user);
 	} else if (folio_test_large(folio)) {
-		unsigned long offset = ptr - folio_address(folio);
-		if (offset + n > folio_size(folio))
+		offset = ptr - folio_address(folio);
+		if (n > folio_size(folio) - offset)
 			usercopy_abort("page alloc", NULL, to_user, offset, n);
 	}
 }
-- 
GitLab


From 1fc766b5c08417248e0008bca14c3572ac0f1c26 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= <linux@weissschuh.net>
Date: Tue, 7 Jun 2022 17:55:55 +0200
Subject: [PATCH 0516/1731] nvme: add device name to warning in uuid_show()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This provides more context to users.

Old message:

[   00.000000] No UUID available providing old NGUID

New message:

[   00.000000] block nvme0n1: No UUID available providing old NGUID

Fixes: d934f9848a77 ("nvme: provide UUID value to userspace")
Signed-off-by: Thomas Weißschuh <linux@weissschuh.net>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/host/core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c
index 24165daee3c8f..9409b88438724 100644
--- a/drivers/nvme/host/core.c
+++ b/drivers/nvme/host/core.c
@@ -3285,8 +3285,8 @@ static ssize_t uuid_show(struct device *dev, struct device_attribute *attr,
 	 * we have no UUID set
 	 */
 	if (uuid_is_null(&ids->uuid)) {
-		printk_ratelimited(KERN_WARNING
-				   "No UUID available providing old NGUID\n");
+		dev_warn_ratelimited(dev,
+			"No UUID available providing old NGUID\n");
 		return sysfs_emit(buf, "%pU\n", ids->nguid);
 	}
 	return sysfs_emit(buf, "%pU\n", &ids->uuid);
-- 
GitLab


From 2f0dad1719cbbd690e916a42d937b7605ee63964 Mon Sep 17 00:00:00 2001
From: Keith Busch <kbusch@kernel.org>
Date: Tue, 7 Jun 2022 08:30:29 -0700
Subject: [PATCH 0517/1731] nvme: add bug report info for global duplicate id

The recent global id check is finding poorly implemented devices in the
wild. Include relavant device information in the output to help quicken
an appropriate quirk patch.

Signed-off-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/host/core.c |  1 +
 drivers/nvme/host/nvme.h | 28 ++++++++++++++++++++++++++++
 drivers/nvme/host/pci.c  | 16 ++++++++++++++++
 3 files changed, 45 insertions(+)

diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c
index 9409b88438724..3ab2cfd254a44 100644
--- a/drivers/nvme/host/core.c
+++ b/drivers/nvme/host/core.c
@@ -3863,6 +3863,7 @@ static int nvme_init_ns_head(struct nvme_ns *ns, unsigned nsid,
 	if (ret) {
 		dev_err(ctrl->device,
 			"globally duplicate IDs for nsid %d\n", nsid);
+		nvme_print_device_info(ctrl);
 		return ret;
 	}
 
diff --git a/drivers/nvme/host/nvme.h b/drivers/nvme/host/nvme.h
index 9b72b6ecf33c9..0da94b233feda 100644
--- a/drivers/nvme/host/nvme.h
+++ b/drivers/nvme/host/nvme.h
@@ -503,6 +503,7 @@ struct nvme_ctrl_ops {
 	void (*submit_async_event)(struct nvme_ctrl *ctrl);
 	void (*delete_ctrl)(struct nvme_ctrl *ctrl);
 	int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size);
+	void (*print_device_info)(struct nvme_ctrl *ctrl);
 };
 
 /*
@@ -548,6 +549,33 @@ static inline struct request *nvme_cid_to_rq(struct blk_mq_tags *tags,
 	return blk_mq_tag_to_rq(tags, nvme_tag_from_cid(command_id));
 }
 
+/*
+ * Return the length of the string without the space padding
+ */
+static inline int nvme_strlen(char *s, int len)
+{
+	while (s[len - 1] == ' ')
+		len--;
+	return len;
+}
+
+static inline void nvme_print_device_info(struct nvme_ctrl *ctrl)
+{
+	struct nvme_subsystem *subsys = ctrl->subsys;
+
+	if (ctrl->ops->print_device_info) {
+		ctrl->ops->print_device_info(ctrl);
+		return;
+	}
+
+	dev_err(ctrl->device,
+		"VID:%04x model:%.*s firmware:%.*s\n", subsys->vendor_id,
+		nvme_strlen(subsys->model, sizeof(subsys->model)),
+		subsys->model, nvme_strlen(subsys->firmware_rev,
+					   sizeof(subsys->firmware_rev)),
+		subsys->firmware_rev);
+}
+
 #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS
 void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj,
 			    const char *dev_name);
diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 48f4f6eb877bc..96579d48002a1 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -2976,6 +2976,21 @@ static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
 	return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
 }
 
+
+static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
+{
+	struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
+	struct nvme_subsystem *subsys = ctrl->subsys;
+
+	dev_err(ctrl->device,
+		"VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
+		pdev->vendor, pdev->device,
+		nvme_strlen(subsys->model, sizeof(subsys->model)),
+		subsys->model, nvme_strlen(subsys->firmware_rev,
+					   sizeof(subsys->firmware_rev)),
+		subsys->firmware_rev);
+}
+
 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
 	.name			= "pcie",
 	.module			= THIS_MODULE,
@@ -2987,6 +3002,7 @@ static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
 	.free_ctrl		= nvme_pci_free_ctrl,
 	.submit_async_event	= nvme_pci_submit_async_event,
 	.get_address		= nvme_pci_get_address,
+	.print_device_info	= nvme_pci_print_device_info,
 };
 
 static int nvme_dev_map(struct nvme_dev *dev)
-- 
GitLab


From 4641a8e6e145f595059e695f0f8dbbe608134086 Mon Sep 17 00:00:00 2001
From: Keith Busch <kbusch@kernel.org>
Date: Mon, 6 Jun 2022 09:53:17 -0700
Subject: [PATCH 0518/1731] nvme-pci: add trouble shooting steps for timeouts

Many users have encountered IO timeouts with a CSTS value of 0xffffffff,
which indicates a failure to read the register. While there are various
potential causes for this observation, faulty NVMe APST has been the
culprit quite frequently. Add the recommended troubleshooting steps in
the error output when this condition occurs.

Signed-off-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Chaitanya Kulkarni <kch@nvidia.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/host/pci.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 96579d48002a1..be053d943731b 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -1334,6 +1334,14 @@ static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
 		dev_warn(dev->ctrl.device,
 			 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
 			 csts, result);
+
+	if (csts != ~0)
+		return;
+
+	dev_warn(dev->ctrl.device,
+		 "Does your device have a faulty power saving mode enabled?\n");
+	dev_warn(dev->ctrl.device,
+		 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
 }
 
 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
-- 
GitLab


From 3765fad508964f433ac111c127d6bedd19bdfa04 Mon Sep 17 00:00:00 2001
From: Stefan Reiter <stefan@pimaker.at>
Date: Mon, 6 Jun 2022 13:01:29 +0000
Subject: [PATCH 0519/1731] nvme-pci: add NVME_QUIRK_BOGUS_NID for ADATA XPG
 GAMMIX S50

ADATA XPG GAMMIX S50 drives report bogus eui64 values that appear to
be the same across drives in one system. Quirk them out so they are
not marked as "non globally unique" duplicates.

Signed-off-by: Stefan Reiter <stefan@pimaker.at>
Reviewed-by: Chaitanya Kulkarni <kch@nvidia.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/host/pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index be053d943731b..631add46e439e 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -3487,6 +3487,8 @@ static const struct pci_device_id nvme_id_table[] = {
 		.driver_data = NVME_QUIRK_BOGUS_NID, },
 	{ PCI_DEVICE(0x1e4B, 0x1202),   /* MAXIO MAP1202 */
 		.driver_data = NVME_QUIRK_BOGUS_NID, },
+	{ PCI_DEVICE(0x1cc1, 0x5350),   /* ADATA XPG GAMMIX S50 */
+		.driver_data = NVME_QUIRK_BOGUS_NID, },
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
 		.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
-- 
GitLab


From 2cf7a77ed5f8903606f4f7833d02d67b08650442 Mon Sep 17 00:00:00 2001
From: Keith Busch <kbusch@kernel.org>
Date: Mon, 13 Jun 2022 07:45:47 -0700
Subject: [PATCH 0520/1731] nvme-pci: phison e12 has bogus namespace ids

Add the quirk.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=216049
Signed-off-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/host/pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 631add46e439e..156723d3af83c 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -3461,6 +3461,8 @@ static const struct pci_device_id nvme_id_table[] = {
 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
 				NVME_QUIRK_DISABLE_WRITE_ZEROES|
 				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
+	{ PCI_DEVICE(0x1987, 0x5012),	/* Phison E12 */
+		.driver_data = NVME_QUIRK_BOGUS_NID, },
 	{ PCI_DEVICE(0x1987, 0x5016),	/* Phison E16 */
 		.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
 	{ PCI_DEVICE(0x1b4b, 0x1092),	/* Lexar 256 GB SSD */
-- 
GitLab


From c98a879312caf775c9768faed25ce1c013b4df04 Mon Sep 17 00:00:00 2001
From: Keith Busch <kbusch@kernel.org>
Date: Mon, 13 Jun 2022 07:45:48 -0700
Subject: [PATCH 0521/1731] nvme-pci: smi has bogus namespace ids

Add the quirk.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=216096
Signed-off-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/host/pci.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 156723d3af83c..0d21134685233 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -3445,7 +3445,8 @@ static const struct pci_device_id nvme_id_table[] = {
 	{ PCI_VDEVICE(REDHAT, 0x0010),	/* Qemu emulated controller */
 		.driver_data = NVME_QUIRK_BOGUS_NID, },
 	{ PCI_DEVICE(0x126f, 0x2263),	/* Silicon Motion unidentified */
-		.driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
+		.driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
+				NVME_QUIRK_BOGUS_NID, },
 	{ PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
 				NVME_QUIRK_NO_NS_DESC_LIST, },
-- 
GitLab


From c4f01a776b28378f4f61b53f8cb0e358f4fa3721 Mon Sep 17 00:00:00 2001
From: Keith Busch <kbusch@kernel.org>
Date: Mon, 13 Jun 2022 07:45:49 -0700
Subject: [PATCH 0522/1731] nvme-pci: sk hynix p31 has bogus namespace ids

Add the quirk.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=216049
Signed-off-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/host/pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 0d21134685233..82b4daa9bf953 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -3476,6 +3476,8 @@ static const struct pci_device_id nvme_id_table[] = {
 				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
 	{ PCI_DEVICE(0x1c5c, 0x1504),   /* SK Hynix PC400 */
 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
+	{ PCI_DEVICE(0x1c5c, 0x174a),   /* SK Hynix P31 SSD */
+		.driver_data = NVME_QUIRK_BOGUS_NID, },
 	{ PCI_DEVICE(0x15b7, 0x2001),   /*  Sandisk Skyhawk */
 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
 	{ PCI_DEVICE(0x1d97, 0x2263),   /* SPCC */
-- 
GitLab


From 6b961bce50e489186232cef51036ddb8d672bc3b Mon Sep 17 00:00:00 2001
From: Ning Wang <ningwang35@outlook.com>
Date: Sun, 5 Jun 2022 20:36:48 +0000
Subject: [PATCH 0523/1731] nvme-pci: avoid the deepest sleep state on ZHITAI
 TiPro7000 SSDs

When ZHITAI TiPro7000 SSDs entered deepest power state(ps4)
it has the same APST sleep problem as Kingston A2000.
by chance the system crashes and displays the same dmesg info:

https://bugzilla.kernel.org/show_bug.cgi?id=195039#c65

As the Archlinux wiki suggest (enlat + exlat) < 25000 is fine
and my testing shows no system crashes ever since.
Therefore disabling the deepest power state will fix the APST sleep issue.

https://wiki.archlinux.org/title/Solid_state_drive/NVMe

This is the APST data from 'nvme id-ctrl /dev/nvme1'

NVME Identify Controller:
vid       : 0x1e49
ssvid     : 0x1e49
sn        : [...]
mn        : ZHITAI TiPro7000 1TB
fr        : ZTA32F3Y
[...]
ps    0 : mp:3.50W operational enlat:5 exlat:5 rrt:0 rrl:0
          rwt:0 rwl:0 idle_power:- active_power:-
ps    1 : mp:3.30W operational enlat:50 exlat:100 rrt:1 rrl:1
          rwt:1 rwl:1 idle_power:- active_power:-
ps    2 : mp:2.80W operational enlat:50 exlat:200 rrt:2 rrl:2
          rwt:2 rwl:2 idle_power:- active_power:-
ps    3 : mp:0.1500W non-operational enlat:500 exlat:5000 rrt:3 rrl:3
          rwt:3 rwl:3 idle_power:- active_power:-
ps    4 : mp:0.0200W non-operational enlat:2000 exlat:60000 rrt:4 rrl:4
          rwt:4 rwl:4 idle_power:- active_power:-

Signed-off-by: Ning Wang <ningwang35@outlook.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/host/pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 82b4daa9bf953..b6f536f9ee78b 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -3494,6 +3494,8 @@ static const struct pci_device_id nvme_id_table[] = {
 		.driver_data = NVME_QUIRK_BOGUS_NID, },
 	{ PCI_DEVICE(0x1cc1, 0x5350),   /* ADATA XPG GAMMIX S50 */
 		.driver_data = NVME_QUIRK_BOGUS_NID, },
+	{ PCI_DEVICE(0x1e49, 0x0041),   /* ZHITAI TiPro7000 NVMe SSD */
+		.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
 		.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
-- 
GitLab


From 43047e082b90ead395c44b0e8497bc853bd13845 Mon Sep 17 00:00:00 2001
From: "rasheed.hsueh" <rasheed.hsueh@lcfc.corp-partner.google.com>
Date: Fri, 10 Jun 2022 14:27:34 +0800
Subject: [PATCH 0524/1731] nvme-pci: disable write zeros support on UMIC and
 Samsung SSDs

Like commit 5611ec2b9814 ("nvme-pci: prevent SK hynix PC400 from using
Write Zeroes command"), UMIS and Samsung has the same issue:
[ 6305.633887] blk_update_request: operation not supported error,
dev nvme0n1, sector 340812032 op 0x9:(WRITE_ZEROES) flags 0x0
phys_seg 0 prio class 0

So also disable Write Zeroes command on UMIS and Samsung.

Signed-off-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com>
Reviewed-by: Chaitanya Kulkarni <kch@nvidia.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/host/pci.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index b6f536f9ee78b..c7012e85d035d 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -3482,6 +3482,14 @@ static const struct pci_device_id nvme_id_table[] = {
 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
 	{ PCI_DEVICE(0x1d97, 0x2263),   /* SPCC */
 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
+	{ PCI_DEVICE(0x144d, 0xa80b),   /* Samsung PM9B1 256G and 512G */
+		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
+	{ PCI_DEVICE(0x144d, 0xa809),   /* Samsung MZALQ256HBJD 256G */
+		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
+	{ PCI_DEVICE(0x1cc4, 0x6303),   /* UMIS RPJTJ512MGE1QDY 512G */
+		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
+	{ PCI_DEVICE(0x1cc4, 0x6302),   /* UMIS RPJTJ256MGE1QDY 256G */
+		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
 	{ PCI_DEVICE(0x2646, 0x2262),   /* KINGSTON SKC2000 NVMe SSD */
 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
 	{ PCI_DEVICE(0x2646, 0x2263),   /* KINGSTON A2000 NVMe SSD  */
-- 
GitLab


From 49e477610087a02c3604061b8f3ee3a25a493987 Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Wed, 8 Jun 2022 09:13:34 -0700
Subject: [PATCH 0525/1731] drm/msm: Switch ordering of runpm put vs
 devfreq_idle

In msm_devfreq_suspend() we cancel idle_work synchronously so that it
doesn't run after we power of the hw or in the resume path.  But this
means that we want to ensure that idle_work is not scheduled *after* we
no longer hold a runpm ref.  So switch the ordering of pm_runtime_put()
vs msm_devfreq_idle().

v2. Only move the runpm _put_autosuspend, and not the _mark_last_busy()

Fixes: 9bc95570175a ("drm/msm: Devfreq tuning")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Link: https://lore.kernel.org/r/20210927152928.831245-1-robdclark@gmail.com
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20220608161334.2140611-1-robdclark@gmail.com
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/msm_gpu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index eb8a6663f309f..244511f850444 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -672,7 +672,6 @@ static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
 	msm_submit_retire(submit);
 
 	pm_runtime_mark_last_busy(&gpu->pdev->dev);
-	pm_runtime_put_autosuspend(&gpu->pdev->dev);
 
 	spin_lock_irqsave(&ring->submit_lock, flags);
 	list_del(&submit->node);
@@ -686,6 +685,8 @@ static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
 		msm_devfreq_idle(gpu);
 	mutex_unlock(&gpu->active_lock);
 
+	pm_runtime_put_autosuspend(&gpu->pdev->dev);
+
 	msm_gem_submit_put(submit);
 }
 
-- 
GitLab


From f6eed15f3ea76596ccc689331e1cc850b999133b Mon Sep 17 00:00:00 2001
From: Sergey Gorenko <sergeygo@nvidia.com>
Date: Mon, 13 Jun 2022 15:38:54 +0300
Subject: [PATCH 0526/1731] scsi: iscsi: Exclude zero from the endpoint ID
 range

The kernel returns an endpoint ID as r.ep_connect_ret.handle in the
iscsi_uevent. The iscsid validates a received endpoint ID and treats zero
as an error. The commit referenced in the fixes line changed the endpoint
ID range, and zero is always assigned to the first endpoint ID.  So, the
first attempt to create a new iSER connection always fails.

Link: https://lore.kernel.org/r/20220613123854.55073-1-sergeygo@nvidia.com
Fixes: 3c6ae371b8a1 ("scsi: iscsi: Release endpoint ID when its freed")
Reviewed-by: Max Gurtovoy <mgurtovoy@nvidia.com>
Reviewed-by: Mike Christie <michael.christie@oracle.com>
Reviewed-by: Lee Duncan <lduncan@suse.com>
Signed-off-by: Sergey Gorenko <sergeygo@nvidia.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
---
 drivers/scsi/scsi_transport_iscsi.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/scsi/scsi_transport_iscsi.c b/drivers/scsi/scsi_transport_iscsi.c
index 2c0dd64159b09..5d21f07456c6d 100644
--- a/drivers/scsi/scsi_transport_iscsi.c
+++ b/drivers/scsi/scsi_transport_iscsi.c
@@ -212,7 +212,12 @@ iscsi_create_endpoint(int dd_size)
 		return NULL;
 
 	mutex_lock(&iscsi_ep_idr_mutex);
-	id = idr_alloc(&iscsi_ep_idr, ep, 0, -1, GFP_NOIO);
+
+	/*
+	 * First endpoint id should be 1 to comply with user space
+	 * applications (iscsid).
+	 */
+	id = idr_alloc(&iscsi_ep_idr, ep, 1, -1, GFP_NOIO);
 	if (id < 0) {
 		mutex_unlock(&iscsi_ep_idr_mutex);
 		printk(KERN_ERR "Could not allocate endpoint ID. Error %d.\n",
-- 
GitLab


From 93a8ba2a619816d631bd69e9ce2172b4d7a481b8 Mon Sep 17 00:00:00 2001
From: Lucas Stach <l.stach@pengutronix.de>
Date: Wed, 11 May 2022 18:08:23 +0200
Subject: [PATCH 0527/1731] ARM: dts: imx6qdl: correct PU regulator ramp delay

Contrary to what was believed at the time, the ramp delay of 150us is not
plenty for the PU LDO with the default step time of 512 pulses of the 24MHz
clock. Measurements have shown that after enabling the LDO the voltage on
VDDPU_CAP jumps to ~750mV in the first step and after that the regulator
executes the normal ramp up as defined by the step size control.

This means it takes the regulator between 360us and 370us to ramp up to
the nominal 1.15V voltage for this power domain. With the old setting of
the ramp delay the power up of the PU GPC domain would happen in the middle
of the regulator ramp with the voltage being at around 900mV. Apparently
this was enough for most units to properly power up the peripherals in the
domain and execute the reset. Some units however, fail to power up properly,
especially when the chip is at a low temperature. In that case any access
to the GPU registers would yield an incorrect result with no way to recover
from this situation.

Change the ramp delay to 380us to cover the measured ramp up time with a
bit of additional slack.

Fixes: 40130d327f72 ("ARM: dts: imx6qdl: Allow disabling the PU regulator, add a enable ramp delay")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 arch/arm/boot/dts/imx6qdl.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index d27beb47f9a3b..652feff334966 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -762,7 +762,7 @@
 					regulator-name = "vddpu";
 					regulator-min-microvolt = <725000>;
 					regulator-max-microvolt = <1450000>;
-					regulator-enable-ramp-delay = <150>;
+					regulator-enable-ramp-delay = <380>;
 					anatop-reg-offset = <0x140>;
 					anatop-vol-bit-shift = <9>;
 					anatop-vol-bit-width = <5>;
-- 
GitLab


From b426310e509a1fde077fbe684ecc4a4a694d2bab Mon Sep 17 00:00:00 2001
From: Max Krummenacher <max.krummenacher@toradex.com>
Date: Fri, 13 May 2022 12:26:12 +0200
Subject: [PATCH 0528/1731] ARM: dts: imx6qdl-colibri: Fix capacitive touch
 reset polarity

The commit feedaacdadfc ("Input: atmel_mxt_ts - fix up inverted RESET
handler") requires the reset GPIO to have GPIO_ACTIVE_LOW.

Fixes: 1524b27c94a6 ("ARM: dts: imx6dl-colibri: Move common nodes to SoM dtsi")
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 arch/arm/boot/dts/imx6qdl-colibri.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
index c383e0e4110c8..7df270cea2928 100644
--- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
@@ -593,7 +593,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_atmel_conn>;
 		reg = <0x4a>;
-		reset-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;	/* SODIMM 106 */
+		reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;	/* SODIMM 106 */
 		status = "disabled";
 	};
 };
-- 
GitLab


From 7c7eaeefb0ae226da9233d5db265652d900e1fcb Mon Sep 17 00:00:00 2001
From: Alexander Stein <alexander.stein@ew.tq-group.com>
Date: Tue, 24 May 2022 09:39:34 +0200
Subject: [PATCH 0529/1731] soc: imx: imx8m-blk-ctrl: fix display clock for
 LCDIF2 power domain

LCDIF2 has its own display clock, use this one.

Fixes: 07614fed00e9 ("soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl")
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Paul Elder <paul.elder@ideasonboard.com>
Tested-by: Martyn Welch <martyn.welch@collabora.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 drivers/soc/imx/imx8m-blk-ctrl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
index 7f49385ed2f8e..7ebc28709e945 100644
--- a/drivers/soc/imx/imx8m-blk-ctrl.c
+++ b/drivers/soc/imx/imx8m-blk-ctrl.c
@@ -667,7 +667,7 @@ static const struct imx8m_blk_ctrl_domain_data imx8mp_media_blk_ctl_domain_data[
 	},
 	[IMX8MP_MEDIABLK_PD_LCDIF_2] = {
 		.name = "mediablk-lcdif-2",
-		.clk_names = (const char *[]){ "disp1", "apb", "axi", },
+		.clk_names = (const char *[]){ "disp2", "apb", "axi", },
 		.num_clks = 3,
 		.gpc_name = "lcdif2",
 		.rst_mask = BIT(11) | BIT(12) | BIT(24),
-- 
GitLab


From 884c65e4daf3eab8730b2bbd5abc5a2c0403b3f3 Mon Sep 17 00:00:00 2001
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: Thu, 9 Jun 2022 17:14:59 +0100
Subject: [PATCH 0530/1731] amd-xgbe: Use platform_irq_count()

The AMD XGbE driver currently counts the number of interrupts assigned
to the device by inspecting the pdev->resource array. Since commit
a1a2b7125e10 ("of/platform: Drop static setup of IRQ resource from DT
core") removed IRQs from this array, the driver now attempts to get all
interrupts from 1 to -1U and gives up probing once it reaches an invalid
interrupt index.

Obtain the number of IRQs with platform_irq_count() instead.

Fixes: a1a2b7125e10 ("of/platform: Drop static setup of IRQ resource from DT core")
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Tom Lendacky <thomas.lendacky@amd.com>
Link: https://lore.kernel.org/r/20220609161457.69614-1-jean-philippe@linaro.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/ethernet/amd/xgbe/xgbe-platform.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-platform.c b/drivers/net/ethernet/amd/xgbe/xgbe-platform.c
index 4ebd2410185a9..4d790a89fe771 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-platform.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-platform.c
@@ -338,7 +338,7 @@ static int xgbe_platform_probe(struct platform_device *pdev)
 		 *   the PHY resources listed last
 		 */
 		phy_memnum = xgbe_resource_count(pdev, IORESOURCE_MEM) - 3;
-		phy_irqnum = xgbe_resource_count(pdev, IORESOURCE_IRQ) - 1;
+		phy_irqnum = platform_irq_count(pdev) - 1;
 		dma_irqnum = 1;
 		dma_irqend = phy_irqnum;
 	} else {
@@ -348,7 +348,7 @@ static int xgbe_platform_probe(struct platform_device *pdev)
 		phy_memnum = 0;
 		phy_irqnum = 0;
 		dma_irqnum = 1;
-		dma_irqend = xgbe_resource_count(pdev, IORESOURCE_IRQ);
+		dma_irqend = platform_irq_count(pdev);
 	}
 
 	/* Obtain the mmio areas for the device */
-- 
GitLab


From 9cc8ea99bf7ae6f5a5a305bb14a6f1e3f18f5f54 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>
Date: Fri, 10 Jun 2022 09:28:08 +0200
Subject: [PATCH 0531/1731] docs: networking: phy: Fix a typo
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Write "to be operated" instead of "to be operate".

Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20220610072809.352962-1-j.neuschaefer@gmx.net
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 Documentation/networking/phy.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/networking/phy.rst b/Documentation/networking/phy.rst
index d43da709bf40a..704f31da51672 100644
--- a/Documentation/networking/phy.rst
+++ b/Documentation/networking/phy.rst
@@ -104,7 +104,7 @@ Whenever possible, use the PHY side RGMII delay for these reasons:
 
 * PHY device drivers in PHYLIB being reusable by nature, being able to
   configure correctly a specified delay enables more designs with similar delay
-  requirements to be operate correctly
+  requirements to be operated correctly
 
 For cases where the PHY is not capable of providing this delay, but the
 Ethernet MAC driver is capable of doing so, the correct phy_interface_t value
-- 
GitLab


From 0f9cd1ea10d307cad221d6693b648a8956e812b0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
Date: Mon, 13 Jun 2022 09:37:03 +0200
Subject: [PATCH 0532/1731] drm/ttm: fix bulk move handling v2
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The resource must be on the LRU before ttm_lru_bulk_move_add() is called
and we need to check if the BO is pinned or not before adding it.

Additional to that we missed taking the LRU spinlock in ttm_bo_unpin().

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
Acked-by: Luben Tuikov <luben.tuikov@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220613080816.4965-1-christian.koenig@amd.com
Fixes: fee2ede15542 ("drm/ttm: rework bulk move handling v5")
---
 drivers/gpu/drm/ttm/ttm_bo.c       | 22 ++++++++-----
 drivers/gpu/drm/ttm/ttm_resource.c | 52 +++++++++++++++++++++---------
 include/drm/ttm/ttm_resource.h     |  8 ++---
 3 files changed, 54 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 75d308ec173d3..406e9c324e76a 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -109,11 +109,11 @@ void ttm_bo_set_bulk_move(struct ttm_buffer_object *bo,
 		return;
 
 	spin_lock(&bo->bdev->lru_lock);
-	if (bo->bulk_move && bo->resource)
-		ttm_lru_bulk_move_del(bo->bulk_move, bo->resource);
+	if (bo->resource)
+		ttm_resource_del_bulk_move(bo->resource, bo);
 	bo->bulk_move = bulk;
-	if (bo->bulk_move && bo->resource)
-		ttm_lru_bulk_move_add(bo->bulk_move, bo->resource);
+	if (bo->resource)
+		ttm_resource_add_bulk_move(bo->resource, bo);
 	spin_unlock(&bo->bdev->lru_lock);
 }
 EXPORT_SYMBOL(ttm_bo_set_bulk_move);
@@ -689,8 +689,11 @@ void ttm_bo_pin(struct ttm_buffer_object *bo)
 {
 	dma_resv_assert_held(bo->base.resv);
 	WARN_ON_ONCE(!kref_read(&bo->kref));
-	if (!(bo->pin_count++) && bo->bulk_move && bo->resource)
-		ttm_lru_bulk_move_del(bo->bulk_move, bo->resource);
+	spin_lock(&bo->bdev->lru_lock);
+	if (bo->resource)
+		ttm_resource_del_bulk_move(bo->resource, bo);
+	++bo->pin_count;
+	spin_unlock(&bo->bdev->lru_lock);
 }
 EXPORT_SYMBOL(ttm_bo_pin);
 
@@ -707,8 +710,11 @@ void ttm_bo_unpin(struct ttm_buffer_object *bo)
 	if (WARN_ON_ONCE(!bo->pin_count))
 		return;
 
-	if (!(--bo->pin_count) && bo->bulk_move && bo->resource)
-		ttm_lru_bulk_move_add(bo->bulk_move, bo->resource);
+	spin_lock(&bo->bdev->lru_lock);
+	--bo->pin_count;
+	if (bo->resource)
+		ttm_resource_add_bulk_move(bo->resource, bo);
+	spin_unlock(&bo->bdev->lru_lock);
 }
 EXPORT_SYMBOL(ttm_bo_unpin);
 
diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c
index 65889b3caf502..20f9adcc3235f 100644
--- a/drivers/gpu/drm/ttm/ttm_resource.c
+++ b/drivers/gpu/drm/ttm/ttm_resource.c
@@ -91,8 +91,8 @@ static void ttm_lru_bulk_move_pos_tail(struct ttm_lru_bulk_move_pos *pos,
 }
 
 /* Add the resource to a bulk_move cursor */
-void ttm_lru_bulk_move_add(struct ttm_lru_bulk_move *bulk,
-			   struct ttm_resource *res)
+static void ttm_lru_bulk_move_add(struct ttm_lru_bulk_move *bulk,
+				  struct ttm_resource *res)
 {
 	struct ttm_lru_bulk_move_pos *pos = ttm_lru_bulk_move_pos(bulk, res);
 
@@ -105,8 +105,8 @@ void ttm_lru_bulk_move_add(struct ttm_lru_bulk_move *bulk,
 }
 
 /* Remove the resource from a bulk_move range */
-void ttm_lru_bulk_move_del(struct ttm_lru_bulk_move *bulk,
-			   struct ttm_resource *res)
+static void ttm_lru_bulk_move_del(struct ttm_lru_bulk_move *bulk,
+				  struct ttm_resource *res)
 {
 	struct ttm_lru_bulk_move_pos *pos = ttm_lru_bulk_move_pos(bulk, res);
 
@@ -122,6 +122,22 @@ void ttm_lru_bulk_move_del(struct ttm_lru_bulk_move *bulk,
 	}
 }
 
+/* Add the resource to a bulk move if the BO is configured for it */
+void ttm_resource_add_bulk_move(struct ttm_resource *res,
+				struct ttm_buffer_object *bo)
+{
+	if (bo->bulk_move && !bo->pin_count)
+		ttm_lru_bulk_move_add(bo->bulk_move, res);
+}
+
+/* Remove the resource from a bulk move if the BO is configured for it */
+void ttm_resource_del_bulk_move(struct ttm_resource *res,
+				struct ttm_buffer_object *bo)
+{
+	if (bo->bulk_move && !bo->pin_count)
+		ttm_lru_bulk_move_del(bo->bulk_move, res);
+}
+
 /* Move a resource to the LRU or bulk tail */
 void ttm_resource_move_to_lru_tail(struct ttm_resource *res)
 {
@@ -169,15 +185,14 @@ void ttm_resource_init(struct ttm_buffer_object *bo,
 	res->bus.is_iomem = false;
 	res->bus.caching = ttm_cached;
 	res->bo = bo;
-	INIT_LIST_HEAD(&res->lru);
 
 	man = ttm_manager_type(bo->bdev, place->mem_type);
 	spin_lock(&bo->bdev->lru_lock);
-	man->usage += res->num_pages << PAGE_SHIFT;
-	if (bo->bulk_move)
-		ttm_lru_bulk_move_add(bo->bulk_move, res);
+	if (bo->pin_count)
+		list_add_tail(&res->lru, &bo->bdev->pinned);
 	else
-		ttm_resource_move_to_lru_tail(res);
+		list_add_tail(&res->lru, &man->lru[bo->priority]);
+	man->usage += res->num_pages << PAGE_SHIFT;
 	spin_unlock(&bo->bdev->lru_lock);
 }
 EXPORT_SYMBOL(ttm_resource_init);
@@ -210,8 +225,16 @@ int ttm_resource_alloc(struct ttm_buffer_object *bo,
 {
 	struct ttm_resource_manager *man =
 		ttm_manager_type(bo->bdev, place->mem_type);
+	int ret;
+
+	ret = man->func->alloc(man, bo, place, res_ptr);
+	if (ret)
+		return ret;
 
-	return man->func->alloc(man, bo, place, res_ptr);
+	spin_lock(&bo->bdev->lru_lock);
+	ttm_resource_add_bulk_move(*res_ptr, bo);
+	spin_unlock(&bo->bdev->lru_lock);
+	return 0;
 }
 
 void ttm_resource_free(struct ttm_buffer_object *bo, struct ttm_resource **res)
@@ -221,12 +244,9 @@ void ttm_resource_free(struct ttm_buffer_object *bo, struct ttm_resource **res)
 	if (!*res)
 		return;
 
-	if (bo->bulk_move) {
-		spin_lock(&bo->bdev->lru_lock);
-		ttm_lru_bulk_move_del(bo->bulk_move, *res);
-		spin_unlock(&bo->bdev->lru_lock);
-	}
-
+	spin_lock(&bo->bdev->lru_lock);
+	ttm_resource_del_bulk_move(*res, bo);
+	spin_unlock(&bo->bdev->lru_lock);
 	man = ttm_manager_type(bo->bdev, (*res)->mem_type);
 	man->func->free(man, *res);
 	*res = NULL;
diff --git a/include/drm/ttm/ttm_resource.h b/include/drm/ttm/ttm_resource.h
index 441653693970c..ca89a48c24609 100644
--- a/include/drm/ttm/ttm_resource.h
+++ b/include/drm/ttm/ttm_resource.h
@@ -311,12 +311,12 @@ ttm_resource_manager_cleanup(struct ttm_resource_manager *man)
 }
 
 void ttm_lru_bulk_move_init(struct ttm_lru_bulk_move *bulk);
-void ttm_lru_bulk_move_add(struct ttm_lru_bulk_move *bulk,
-			   struct ttm_resource *res);
-void ttm_lru_bulk_move_del(struct ttm_lru_bulk_move *bulk,
-			   struct ttm_resource *res);
 void ttm_lru_bulk_move_tail(struct ttm_lru_bulk_move *bulk);
 
+void ttm_resource_add_bulk_move(struct ttm_resource *res,
+				struct ttm_buffer_object *bo);
+void ttm_resource_del_bulk_move(struct ttm_resource *res,
+				struct ttm_buffer_object *bo);
 void ttm_resource_move_to_lru_tail(struct ttm_resource *res);
 
 void ttm_resource_init(struct ttm_buffer_object *bo,
-- 
GitLab


From 89931cb463d861faf987dbbff9db986fe59293f7 Mon Sep 17 00:00:00 2001
From: Alexandre Torgue <alexandre.torgue@foss.st.com>
Date: Mon, 13 Jun 2022 09:19:20 +0200
Subject: [PATCH 0533/1731] ARM: dts: stm32: move SCMI related nodes in a
 dedicated file for stm32mp15

Adding a "secure" version of STM32 boards (DK1/DK2/ED1/EV1), SCMI (clock/
reset) protocol and OP-TEE node have been added in SoC dtsi file
(stm32mp151.dtsi). They have been added with a status disabled in order to
keep our legacy unchanged. It is actually not enough to keep our legacy
unchanged.

First, just a reminder about our use case: TF-A (BL2) loads and starts
OP-TEE, then loads and runs U-Boot. U-Boot code checks if an OP-TEE is
running, if yes it searches in Kernel device tree if an OP-TEE node is
present:

-If the OP-TEE node is not present then U-Boot copies OP-TEE node and its
reserved memory region from U-Boot device tree to the kernel device tree.

-If the OP-TEE node is present then it does nothing (this OP-TEE node will
be used by Linux). So U-Boot lets the kernel device tree unchanged thinking
it is correct for an OP-TEE usage. It is the case for our legacy boards,
the OP-TEE node is present (although disabled) but the reserved memory
region is not declared. As no memory region has been reserved for OP-TEE,
the end of DDR is seen by the kernel as free and then used for CMA. But as
OP-TEE is running, this end of DDR is already used by OP-TEE. So as soon as
kernel tries to access to the CMA region OP-TEE raises an error.

To fix it, all OP-TEE node and SCMI is moved in a dedicated file.

Fixes: 40b4157dbd8c ("ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP15")
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Link: https://lore.kernel.org/r/20220613071920.5463-1-alexandre.torgue@foss.st.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/boot/dts/stm32mp15-scmi.dtsi      | 47 ++++++++++++++++++++++
 arch/arm/boot/dts/stm32mp151.dtsi          | 41 -------------------
 arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts | 13 +-----
 arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts | 13 +-----
 arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts | 13 +-----
 arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts | 13 +-----
 6 files changed, 51 insertions(+), 89 deletions(-)
 create mode 100644 arch/arm/boot/dts/stm32mp15-scmi.dtsi

diff --git a/arch/arm/boot/dts/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/stm32mp15-scmi.dtsi
new file mode 100644
index 0000000000000..e90cf3acd0b31
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15-scmi.dtsi
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/ {
+	firmware {
+		optee: optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+
+		scmi: scmi {
+			compatible = "linaro,scmi-optee";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			linaro,optee-channel-id = <0>;
+			shmem = <&scmi_shm>;
+
+			scmi_clk: protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
+
+			scmi_reset: protocol@16 {
+				reg = <0x16>;
+				#reset-cells = <1>;
+			};
+		};
+	};
+
+	soc {
+		scmi_sram: sram@2ffff000 {
+			compatible = "mmio-sram";
+			reg = <0x2ffff000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x2ffff000 0x1000>;
+
+			scmi_shm: scmi-sram@0 {
+				compatible = "arm,scmi-shmem";
+				reg = <0 0x80>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi
index 1b2fd3426a810..7fdc324b3cf95 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -115,33 +115,6 @@
 		status = "disabled";
 	};
 
-	firmware {
-		optee: optee {
-			compatible = "linaro,optee-tz";
-			method = "smc";
-			status = "disabled";
-		};
-
-		scmi: scmi {
-			compatible = "linaro,scmi-optee";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			linaro,optee-channel-id = <0>;
-			shmem = <&scmi_shm>;
-			status = "disabled";
-
-			scmi_clk: protocol@14 {
-				reg = <0x14>;
-				#clock-cells = <1>;
-			};
-
-			scmi_reset: protocol@16 {
-				reg = <0x16>;
-				#reset-cells = <1>;
-			};
-		};
-	};
-
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -149,20 +122,6 @@
 		interrupt-parent = <&intc>;
 		ranges;
 
-		scmi_sram: sram@2ffff000 {
-			compatible = "mmio-sram";
-			reg = <0x2ffff000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x2ffff000 0x1000>;
-
-			scmi_shm: scmi-sram@0 {
-				compatible = "arm,scmi-shmem";
-				reg = <0 0x80>;
-				status = "disabled";
-			};
-		};
-
 		timers2: timer@40000000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
diff --git a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts
index e3d3f3f30c7da..36371d6ed6604 100644
--- a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts
+++ b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts
@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include "stm32mp157a-dk1.dts"
+#include "stm32mp15-scmi.dtsi"
 
 / {
 	model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board";
@@ -54,10 +55,6 @@
 	resets = <&scmi_reset RST_SCMI_MCU>;
 };
 
-&optee {
-	status = "okay";
-};
-
 &rcc {
 	compatible = "st,stm32mp1-rcc-secure", "syscon";
 	clock-names = "hse", "hsi", "csi", "lse", "lsi";
@@ -76,11 +73,3 @@
 &rtc {
 	clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
 };
-
-&scmi {
-	status = "okay";
-};
-
-&scmi_shm {
-	status = "okay";
-};
diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts
index 45dcd299aa9e7..03226a5969046 100644
--- a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts
+++ b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts
@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include "stm32mp157c-dk2.dts"
+#include "stm32mp15-scmi.dtsi"
 
 / {
 	model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board";
@@ -63,10 +64,6 @@
 	resets = <&scmi_reset RST_SCMI_MCU>;
 };
 
-&optee {
-	status = "okay";
-};
-
 &rcc {
 	compatible = "st,stm32mp1-rcc-secure", "syscon";
 	clock-names = "hse", "hsi", "csi", "lse", "lsi";
@@ -85,11 +82,3 @@
 &rtc {
 	clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
 };
-
-&scmi {
-	status = "okay";
-};
-
-&scmi_shm {
-	status = "okay";
-};
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts
index 458e0ca3cded3..c1a79272c0688 100644
--- a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts
@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include "stm32mp157c-ed1.dts"
+#include "stm32mp15-scmi.dtsi"
 
 / {
 	model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter";
@@ -59,10 +60,6 @@
 	resets = <&scmi_reset RST_SCMI_MCU>;
 };
 
-&optee {
-	status = "okay";
-};
-
 &rcc {
 	compatible = "st,stm32mp1-rcc-secure", "syscon";
 	clock-names = "hse", "hsi", "csi", "lse", "lsi";
@@ -81,11 +78,3 @@
 &rtc {
 	clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
 };
-
-&scmi {
-	status = "okay";
-};
-
-&scmi_shm {
-	status = "okay";
-};
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts
index df9c113edb4b5..7842384ddbe45 100644
--- a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts
@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include "stm32mp157c-ev1.dts"
+#include "stm32mp15-scmi.dtsi"
 
 / {
 	model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother";
@@ -68,10 +69,6 @@
 	resets = <&scmi_reset RST_SCMI_MCU>;
 };
 
-&optee {
-	status = "okay";
-};
-
 &rcc {
 	compatible = "st,stm32mp1-rcc-secure", "syscon";
 	clock-names = "hse", "hsi", "csi", "lse", "lsi";
@@ -90,11 +87,3 @@
 &rtc {
 	clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
 };
-
-&scmi {
-	status = "okay";
-};
-
-&scmi_shm {
-	status = "okay";
-};
-- 
GitLab


From 168f912893407a5acb798a4a58613b5f1f98c717 Mon Sep 17 00:00:00 2001
From: Christian Brauner <brauner@kernel.org>
Date: Mon, 13 Jun 2022 13:15:17 +0200
Subject: [PATCH 0534/1731] fs: account for group membership

When calling setattr_prepare() to determine the validity of the
attributes the ia_{g,u}id fields contain the value that will be written
to inode->i_{g,u}id. This is exactly the same for idmapped and
non-idmapped mounts and allows callers to pass in the values they want
to see written to inode->i_{g,u}id.

When group ownership is changed a caller whose fsuid owns the inode can
change the group of the inode to any group they are a member of. When
searching through the caller's groups we need to use the gid mapped
according to the idmapped mount otherwise we will fail to change
ownership for unprivileged users.

Consider a caller running with fsuid and fsgid 1000 using an idmapped
mount that maps id 65534 to 1000 and 65535 to 1001. Consequently, a file
owned by 65534:65535 in the filesystem will be owned by 1000:1001 in the
idmapped mount.

The caller now requests the gid of the file to be changed to 1000 going
through the idmapped mount. In the vfs we will immediately map the
requested gid to the value that will need to be written to inode->i_gid
and place it in attr->ia_gid. Since this idmapped mount maps 65534 to
1000 we place 65534 in attr->ia_gid.

When we check whether the caller is allowed to change group ownership we
first validate that their fsuid matches the inode's uid. The
inode->i_uid is 65534 which is mapped to uid 1000 in the idmapped mount.
Since the caller's fsuid is 1000 we pass the check.

We now check whether the caller is allowed to change inode->i_gid to the
requested gid by calling in_group_p(). This will compare the passed in
gid to the caller's fsgid and search the caller's additional groups.

Since we're dealing with an idmapped mount we need to pass in the gid
mapped according to the idmapped mount. This is akin to checking whether
a caller is privileged over the future group the inode is owned by. And
that needs to take the idmapped mount into account. Note, all helpers
are nops without idmapped mounts.

New regression test sent to xfstests.

Link: https://github.com/lxc/lxd/issues/10537
Link: https://lore.kernel.org/r/20220613111517.2186646-1-brauner@kernel.org
Fixes: 2f221d6f7b88 ("attr: handle idmapped mounts")
Cc: Seth Forshee <sforshee@digitalocean.com>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Aleksa Sarai <cyphar@cyphar.com>
Cc: Al Viro <viro@zeniv.linux.org.uk>
Cc: stable@vger.kernel.org # 5.15+
CC: linux-fsdevel@vger.kernel.org
Reviewed-by: Seth Forshee <sforshee@digitalocean.com>
Signed-off-by: Christian Brauner (Microsoft) <brauner@kernel.org>
---
 fs/attr.c | 26 ++++++++++++++++++++------
 1 file changed, 20 insertions(+), 6 deletions(-)

diff --git a/fs/attr.c b/fs/attr.c
index 66899b6e9bd86..dbe996b0dedfc 100644
--- a/fs/attr.c
+++ b/fs/attr.c
@@ -61,9 +61,15 @@ static bool chgrp_ok(struct user_namespace *mnt_userns,
 		     const struct inode *inode, kgid_t gid)
 {
 	kgid_t kgid = i_gid_into_mnt(mnt_userns, inode);
-	if (uid_eq(current_fsuid(), i_uid_into_mnt(mnt_userns, inode)) &&
-	    (in_group_p(gid) || gid_eq(gid, inode->i_gid)))
-		return true;
+	if (uid_eq(current_fsuid(), i_uid_into_mnt(mnt_userns, inode))) {
+		kgid_t mapped_gid;
+
+		if (gid_eq(gid, inode->i_gid))
+			return true;
+		mapped_gid = mapped_kgid_fs(mnt_userns, i_user_ns(inode), gid);
+		if (in_group_p(mapped_gid))
+			return true;
+	}
 	if (capable_wrt_inode_uidgid(mnt_userns, inode, CAP_CHOWN))
 		return true;
 	if (gid_eq(kgid, INVALID_GID) &&
@@ -123,12 +129,20 @@ int setattr_prepare(struct user_namespace *mnt_userns, struct dentry *dentry,
 
 	/* Make sure a caller can chmod. */
 	if (ia_valid & ATTR_MODE) {
+		kgid_t mapped_gid;
+
 		if (!inode_owner_or_capable(mnt_userns, inode))
 			return -EPERM;
+
+		if (ia_valid & ATTR_GID)
+			mapped_gid = mapped_kgid_fs(mnt_userns,
+						i_user_ns(inode), attr->ia_gid);
+		else
+			mapped_gid = i_gid_into_mnt(mnt_userns, inode);
+
 		/* Also check the setgid bit! */
-               if (!in_group_p((ia_valid & ATTR_GID) ? attr->ia_gid :
-                                i_gid_into_mnt(mnt_userns, inode)) &&
-                    !capable_wrt_inode_uidgid(mnt_userns, inode, CAP_FSETID))
+		if (!in_group_p(mapped_gid) &&
+		    !capable_wrt_inode_uidgid(mnt_userns, inode, CAP_FSETID))
 			attr->ia_mode &= ~S_ISGID;
 	}
 
-- 
GitLab


From 7c7ff68daa93d8c4cdea482da4f2429c0398fcde Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Wed, 1 Jun 2022 13:05:48 +0400
Subject: [PATCH 0535/1731] ARM: Fix refcount leak in axxia_boot_secondary

of_find_compatible_node() returns a node pointer with refcount
incremented, we should use of_node_put() on it when done.
Add missing of_node_put() to avoid refcount leak.

Fixes: 1d22924e1c4e ("ARM: Add platform support for LSI AXM55xx SoC")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Link: https://lore.kernel.org/r/20220601090548.47616-1-linmq006@gmail.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/mach-axxia/platsmp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-axxia/platsmp.c b/arch/arm/mach-axxia/platsmp.c
index 512943eae30a5..2e203626eda52 100644
--- a/arch/arm/mach-axxia/platsmp.c
+++ b/arch/arm/mach-axxia/platsmp.c
@@ -39,6 +39,7 @@ static int axxia_boot_secondary(unsigned int cpu, struct task_struct *idle)
 		return -ENOENT;
 
 	syscon = of_iomap(syscon_np, 0);
+	of_node_put(syscon_np);
 	if (!syscon)
 		return -ENOMEM;
 
-- 
GitLab


From be5cddef05f519a321a543906f255ac247246074 Mon Sep 17 00:00:00 2001
From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Date: Fri, 10 Jun 2022 13:40:29 +0300
Subject: [PATCH 0536/1731] bus: bt1-apb: Don't print error on -EPROBE_DEFER

The Baikal-T1 APB bus driver correctly handles the deferred probe
situation, but still pollutes the system log with a misleading error
message. Let's fix that by using the dev_err_probe() method to print the
log message in case of the clocks/resets request errors.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Link: https://lore.kernel.org/r/20220610104030.28399-1-Sergey.Semin@baikalelectronics.ru'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 drivers/bus/bt1-apb.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/bus/bt1-apb.c b/drivers/bus/bt1-apb.c
index b25ff941e7c7f..63b1b4a76671d 100644
--- a/drivers/bus/bt1-apb.c
+++ b/drivers/bus/bt1-apb.c
@@ -175,10 +175,9 @@ static int bt1_apb_request_rst(struct bt1_apb *apb)
 	int ret;
 
 	apb->prst = devm_reset_control_get_optional_exclusive(apb->dev, "prst");
-	if (IS_ERR(apb->prst)) {
-		dev_warn(apb->dev, "Couldn't get reset control line\n");
-		return PTR_ERR(apb->prst);
-	}
+	if (IS_ERR(apb->prst))
+		return dev_err_probe(apb->dev, PTR_ERR(apb->prst),
+				     "Couldn't get reset control line\n");
 
 	ret = reset_control_deassert(apb->prst);
 	if (ret)
@@ -199,10 +198,9 @@ static int bt1_apb_request_clk(struct bt1_apb *apb)
 	int ret;
 
 	apb->pclk = devm_clk_get(apb->dev, "pclk");
-	if (IS_ERR(apb->pclk)) {
-		dev_err(apb->dev, "Couldn't get APB clock descriptor\n");
-		return PTR_ERR(apb->pclk);
-	}
+	if (IS_ERR(apb->pclk))
+		return dev_err_probe(apb->dev, PTR_ERR(apb->pclk),
+				     "Couldn't get APB clock descriptor\n");
 
 	ret = clk_prepare_enable(apb->pclk);
 	if (ret) {
-- 
GitLab


From 5e93207e962a6d23893ff4405f6c5d4396fb5934 Mon Sep 17 00:00:00 2001
From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Date: Fri, 10 Jun 2022 13:40:30 +0300
Subject: [PATCH 0537/1731] bus: bt1-axi: Don't print error on -EPROBE_DEFER

The Baikal-T1 AXI bus driver correctly handles the deferred probe
situation, but still pollutes the system log with a misleading error
message. Let's fix that by using the dev_err_probe() method to print the
log message in case of the clocks/resets request errors.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Link: https://lore.kernel.org/r/20220610104030.28399-2-Sergey.Semin@baikalelectronics.ru'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 drivers/bus/bt1-axi.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/bus/bt1-axi.c b/drivers/bus/bt1-axi.c
index e7a6744acc7b8..70e49a6e53746 100644
--- a/drivers/bus/bt1-axi.c
+++ b/drivers/bus/bt1-axi.c
@@ -135,10 +135,9 @@ static int bt1_axi_request_rst(struct bt1_axi *axi)
 	int ret;
 
 	axi->arst = devm_reset_control_get_optional_exclusive(axi->dev, "arst");
-	if (IS_ERR(axi->arst)) {
-		dev_warn(axi->dev, "Couldn't get reset control line\n");
-		return PTR_ERR(axi->arst);
-	}
+	if (IS_ERR(axi->arst))
+		return dev_err_probe(axi->dev, PTR_ERR(axi->arst),
+				     "Couldn't get reset control line\n");
 
 	ret = reset_control_deassert(axi->arst);
 	if (ret)
@@ -159,10 +158,9 @@ static int bt1_axi_request_clk(struct bt1_axi *axi)
 	int ret;
 
 	axi->aclk = devm_clk_get(axi->dev, "aclk");
-	if (IS_ERR(axi->aclk)) {
-		dev_err(axi->dev, "Couldn't get AXI Interconnect clock\n");
-		return PTR_ERR(axi->aclk);
-	}
+	if (IS_ERR(axi->aclk))
+		return dev_err_probe(axi->dev, PTR_ERR(axi->aclk),
+				     "Couldn't get AXI Interconnect clock\n");
 
 	ret = clk_prepare_enable(axi->aclk);
 	if (ret) {
-- 
GitLab


From 623411c293d180ed51f1c3b5753c5acf2c2a4077 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Wed, 4 May 2022 15:33:50 +0300
Subject: [PATCH 0538/1731] drm/i915: Extract intel_crtc_dotclock()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Extract intel_crtc_dotclock() from ddi_dotclock_get(). We'll reuse
this during state computation in order to determine the actual final
dotclcok after the DPLL computation has been done (which may not give
us the exact same port_clock that we fed in).

v2: Add the prototype

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220504123350.13235-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c     | 18 ++++++++++++------
 drivers/gpu/drm/i915/display/intel_display.h |  1 +
 2 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 132bf5a17d157..5d448e0563be4 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -323,14 +323,10 @@ static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
 	}
 }
 
-static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
+int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
 {
 	int dotclock;
 
-	/* CRT dotclock is determined via other means */
-	if (pipe_config->has_pch_encoder)
-		return;
-
 	if (intel_crtc_has_dp_encoder(pipe_config))
 		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 						    &pipe_config->dp_m_n);
@@ -346,7 +342,17 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 	if (pipe_config->pixel_multiplier)
 		dotclock /= pipe_config->pixel_multiplier;
 
-	pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
+	return dotclock;
+}
+
+static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
+{
+	/* CRT dotclock is determined via other means */
+	if (pipe_config->has_pch_encoder)
+		return;
+
+	pipe_config->hw.adjusted_mode.crtc_clock =
+		intel_crtc_dotclock(pipe_config);
 }
 
 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 187910d94ec65..7af6b5a413dc0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -635,6 +635,7 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 			 struct intel_crtc_state *pipe_config);
 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
+int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
 enum intel_display_power_domain
 intel_aux_power_domain(struct intel_digital_port *dig_port);
-- 
GitLab


From 97708335b04df3eef0e650b0601cdf6c5ab16dcd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Thu, 5 May 2022 00:21:09 +0300
Subject: [PATCH 0539/1731] drm/i915: Introduce struct iclkip_params
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Pull the various iCLKIP parameters into a struct. Later on
we'll reuse this during the state computation to determine
the exact dotclock the hardware will be generating for us.

v2: Don't lose the phaseinc calculation
v3: Drop the misplaced '#include <intel_pch_refclk.h>' from intel_crt.c (Jani)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220504212109.26369-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_pch_refclk.c   | 92 ++++++++++++-------
 1 file changed, 57 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index b688fd87e3dab..752dab11667f4 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -122,16 +122,29 @@ void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
 	mutex_unlock(&dev_priv->sb_lock);
 }
 
-/* Program iCLKIP clock to the desired frequency */
-void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
+struct iclkip_params {
+	u32 iclk_virtual_root_freq;
+	u32 iclk_pi_range;
+	u32 divsel, phaseinc, auxdiv, phasedir, desired_divisor;
+};
+
+static void iclkip_params_init(struct iclkip_params *p)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
-	u32 divsel, phaseinc, auxdiv, phasedir = 0;
-	u32 temp;
+	memset(p, 0, sizeof(*p));
 
-	lpt_disable_iclkip(dev_priv);
+	p->iclk_virtual_root_freq = 172800 * 1000;
+	p->iclk_pi_range = 64;
+}
+
+static int lpt_iclkip_freq(struct iclkip_params *p)
+{
+	return DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq,
+				 p->desired_divisor << p->auxdiv);
+}
+
+static void lpt_compute_iclkip(struct iclkip_params *p, int clock)
+{
+	iclkip_params_init(p);
 
 	/* The iCLK virtual clock root frequency is in MHz,
 	 * but the adjusted_mode->crtc_clock in KHz. To get the
@@ -139,50 +152,61 @@ void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
 	 * convert the virtual clock precision to KHz here for higher
 	 * precision.
 	 */
-	for (auxdiv = 0; auxdiv < 2; auxdiv++) {
-		u32 iclk_virtual_root_freq = 172800 * 1000;
-		u32 iclk_pi_range = 64;
-		u32 desired_divisor;
-
-		desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
-						    clock << auxdiv);
-		divsel = (desired_divisor / iclk_pi_range) - 2;
-		phaseinc = desired_divisor % iclk_pi_range;
+	for (p->auxdiv = 0; p->auxdiv < 2; p->auxdiv++) {
+		p->desired_divisor = DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq,
+						       clock << p->auxdiv);
+		p->divsel = (p->desired_divisor / p->iclk_pi_range) - 2;
+		p->phaseinc = p->desired_divisor % p->iclk_pi_range;
 
 		/*
 		 * Near 20MHz is a corner case which is
 		 * out of range for the 7-bit divisor
 		 */
-		if (divsel <= 0x7f)
+		if (p->divsel <= 0x7f)
 			break;
 	}
+}
+
+/* Program iCLKIP clock to the desired frequency */
+void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
+	struct iclkip_params p;
+	u32 temp;
+
+	lpt_disable_iclkip(dev_priv);
+
+	lpt_compute_iclkip(&p, clock);
+	drm_WARN_ON(&dev_priv->drm, lpt_iclkip_freq(&p) != clock);
 
 	/* This should not happen with any sane values */
-	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
+	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(p.divsel) &
 		    ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
-	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
+	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(p.phasedir) &
 		    ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
 
 	drm_dbg_kms(&dev_priv->drm,
 		    "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
-		    clock, auxdiv, divsel, phasedir, phaseinc);
+		    clock, p.auxdiv, p.divsel, p.phasedir, p.phaseinc);
 
 	mutex_lock(&dev_priv->sb_lock);
 
 	/* Program SSCDIVINTPHASE6 */
 	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
 	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
-	temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
+	temp |= SBI_SSCDIVINTPHASE_DIVSEL(p.divsel);
 	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
-	temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
-	temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
+	temp |= SBI_SSCDIVINTPHASE_INCVAL(p.phaseinc);
+	temp |= SBI_SSCDIVINTPHASE_DIR(p.phasedir);
 	temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
 	intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
 
 	/* Program SSCAUXDIV */
 	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
 	temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
-	temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
+	temp |= SBI_SSCAUXDIV_FINALDIV2SEL(p.auxdiv);
 	intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
 
 	/* Enable modulator and associated divider */
@@ -200,15 +224,14 @@ void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
 
 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
 {
-	u32 divsel, phaseinc, auxdiv;
-	u32 iclk_virtual_root_freq = 172800 * 1000;
-	u32 iclk_pi_range = 64;
-	u32 desired_divisor;
+	struct iclkip_params p;
 	u32 temp;
 
 	if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
 		return 0;
 
+	iclkip_params_init(&p);
+
 	mutex_lock(&dev_priv->sb_lock);
 
 	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
@@ -218,21 +241,20 @@ int lpt_get_iclkip(struct drm_i915_private *dev_priv)
 	}
 
 	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
-	divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
+	p.divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
 		SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
-	phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
+	p.phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
 		SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
 
 	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
-	auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
+	p.auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
 		SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
 
 	mutex_unlock(&dev_priv->sb_lock);
 
-	desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
+	p.desired_divisor = (p.divsel + 2) * p.iclk_pi_range + p.phaseinc;
 
-	return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
-				 desired_divisor << auxdiv);
+	return lpt_iclkip_freq(&p);
 }
 
 /* Implements 3 different sequences from BSpec chapter "Display iCLK
-- 
GitLab


From c9ae7b866f32043d23a34d00a5e6e8d86d2cf10e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 3 May 2022 21:22:30 +0300
Subject: [PATCH 0540/1731] drm/i915: Skip FDI vs. dotclock sanity check during
 readout
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The VBIOS/GOP may not program the FDI M/n vs. dotclock entirely
consistently. Eg. on a SNB Thinkpad X220 LVDS I see dotclock of
69.286 MHz (the best the DPLL can do) vs. FDI M/N 69.3 MHz
(matches what the EDID actually declares).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-15-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d7363640cf6ba..f1d7cce261a6a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10268,8 +10268,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 			crtc_state->min_voltage_level;
 
 		intel_bw_crtc_update(bw_state, crtc_state);
-
-		intel_pipe_config_sanity_check(dev_priv, crtc_state);
 	}
 }
 
-- 
GitLab


From 5c2b745173347ba21e3995d815f26925c91c517d Mon Sep 17 00:00:00 2001
From: Dan Carpenter <dan.carpenter@oracle.com>
Date: Fri, 8 Apr 2022 13:21:34 +0300
Subject: [PATCH 0541/1731] drm/exynos: fix IS_ERR() vs NULL check in probe

The of_drm_find_bridge() does not return error pointers, it returns
NULL on error.

Fixes: dd8b6803bc49 ("exynos: drm: dsi: Attach in_bridge in MIC driver")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
---
 drivers/gpu/drm/exynos/exynos_drm_mic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_mic.c b/drivers/gpu/drm/exynos/exynos_drm_mic.c
index 9e06f8e2a8635..07e04ceb24761 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_mic.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_mic.c
@@ -434,9 +434,9 @@ static int exynos_mic_probe(struct platform_device *pdev)
 
 	remote = of_graph_get_remote_node(dev->of_node, 1, 0);
 	mic->next_bridge = of_drm_find_bridge(remote);
-	if (IS_ERR(mic->next_bridge)) {
+	if (!mic->next_bridge) {
 		DRM_DEV_ERROR(dev, "mic: Failed to find next bridge\n");
-		ret = PTR_ERR(mic->next_bridge);
+		ret = -EPROBE_DEFER;
 		goto err;
 	}
 
-- 
GitLab


From 7d787184a18f0f84e996de8ff007e4395c1978ea Mon Sep 17 00:00:00 2001
From: Marek Szyprowski <m.szyprowski@samsung.com>
Date: Fri, 13 May 2022 10:31:05 +0200
Subject: [PATCH 0542/1731] drm/exynos: mic: Rework initialization

Commit dd8b6803bc49 ("exynos: drm: dsi: Attach in_bridge in MIC driver")
moved Exynos MIC attaching from DSI to MIC driver. However the method
proposed there is incomplete and cannot really work. To properly attach
it to the bridge chain, access to the respective encoder is needed. The
Exynos MIC driver always attaches to the encoder created by the Exynos
DSI driver, so grab it via available helpers for getting access to the
CRTC and encoders. This also requires to change the order of driver
component binding to let DSI to be bound before MIC.

Fixes: dd8b6803bc49 ("exynos: drm: dsi: Attach in_bridge in MIC driver")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Fixed merge conflict.
Signed-off-by: Inki Dae <inki.dae@samsung.com>
---
 drivers/gpu/drm/exynos/exynos_drm_drv.c |  6 ++--
 drivers/gpu/drm/exynos/exynos_drm_mic.c | 42 +++++++------------------
 2 files changed, 15 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c
index 424ea23eec32a..16c539657f730 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
@@ -176,15 +176,15 @@ static struct exynos_drm_driver_info exynos_drm_drivers[] = {
 	}, {
 		DRV_PTR(mixer_driver, CONFIG_DRM_EXYNOS_MIXER),
 		DRM_COMPONENT_DRIVER
-	}, {
-		DRV_PTR(mic_driver, CONFIG_DRM_EXYNOS_MIC),
-		DRM_COMPONENT_DRIVER
 	}, {
 		DRV_PTR(dp_driver, CONFIG_DRM_EXYNOS_DP),
 		DRM_COMPONENT_DRIVER
 	}, {
 		DRV_PTR(dsi_driver, CONFIG_DRM_EXYNOS_DSI),
 		DRM_COMPONENT_DRIVER
+	}, {
+		DRV_PTR(mic_driver, CONFIG_DRM_EXYNOS_MIC),
+		DRM_COMPONENT_DRIVER
 	}, {
 		DRV_PTR(hdmi_driver, CONFIG_DRM_EXYNOS_HDMI),
 		DRM_COMPONENT_DRIVER
diff --git a/drivers/gpu/drm/exynos/exynos_drm_mic.c b/drivers/gpu/drm/exynos/exynos_drm_mic.c
index 07e04ceb24761..09ce28ee08d91 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_mic.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_mic.c
@@ -26,6 +26,7 @@
 #include <drm/drm_print.h>
 
 #include "exynos_drm_drv.h"
+#include "exynos_drm_crtc.h"
 
 /* Sysreg registers for MIC */
 #define DSD_CFG_MUX	0x1004
@@ -100,9 +101,7 @@ struct exynos_mic {
 
 	bool i80_mode;
 	struct videomode vm;
-	struct drm_encoder *encoder;
 	struct drm_bridge bridge;
-	struct drm_bridge *next_bridge;
 
 	bool enabled;
 };
@@ -229,8 +228,6 @@ static void mic_set_reg_on(struct exynos_mic *mic, bool enable)
 	writel(reg, mic->reg + MIC_OP);
 }
 
-static void mic_disable(struct drm_bridge *bridge) { }
-
 static void mic_post_disable(struct drm_bridge *bridge)
 {
 	struct exynos_mic *mic = bridge->driver_private;
@@ -297,34 +294,30 @@ unlock:
 	mutex_unlock(&mic_mutex);
 }
 
-static void mic_enable(struct drm_bridge *bridge) { }
-
-static int mic_attach(struct drm_bridge *bridge,
-		      enum drm_bridge_attach_flags flags)
-{
-	struct exynos_mic *mic = bridge->driver_private;
-
-	return drm_bridge_attach(bridge->encoder, mic->next_bridge,
-				 &mic->bridge, flags);
-}
-
 static const struct drm_bridge_funcs mic_bridge_funcs = {
-	.disable = mic_disable,
 	.post_disable = mic_post_disable,
 	.mode_set = mic_mode_set,
 	.pre_enable = mic_pre_enable,
-	.enable = mic_enable,
-	.attach = mic_attach,
 };
 
 static int exynos_mic_bind(struct device *dev, struct device *master,
 			   void *data)
 {
 	struct exynos_mic *mic = dev_get_drvdata(dev);
+	struct drm_device *drm_dev = data;
+	struct exynos_drm_crtc *crtc = exynos_drm_crtc_get_by_type(drm_dev,
+						       EXYNOS_DISPLAY_TYPE_LCD);
+	struct drm_encoder *e, *encoder = NULL;
+
+	drm_for_each_encoder(e, drm_dev)
+		if (e->possible_crtcs == drm_crtc_mask(&crtc->base))
+			encoder = e;
+	if (!encoder)
+		return -ENODEV;
 
 	mic->bridge.driver_private = mic;
 
-	return 0;
+	return drm_bridge_attach(encoder, &mic->bridge, NULL, 0);
 }
 
 static void exynos_mic_unbind(struct device *dev, struct device *master,
@@ -388,7 +381,6 @@ static int exynos_mic_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct exynos_mic *mic;
-	struct device_node *remote;
 	struct resource res;
 	int ret, i;
 
@@ -432,16 +424,6 @@ static int exynos_mic_probe(struct platform_device *pdev)
 		}
 	}
 
-	remote = of_graph_get_remote_node(dev->of_node, 1, 0);
-	mic->next_bridge = of_drm_find_bridge(remote);
-	if (!mic->next_bridge) {
-		DRM_DEV_ERROR(dev, "mic: Failed to find next bridge\n");
-		ret = -EPROBE_DEFER;
-		goto err;
-	}
-
-	of_node_put(remote);
-
 	platform_set_drvdata(pdev, mic);
 
 	mic->bridge.funcs = &mic_bridge_funcs;
-- 
GitLab


From 4b7a632ac4e7101ceefee8484d5c2ca505d347b3 Mon Sep 17 00:00:00 2001
From: Petr Machata <petrm@nvidia.com>
Date: Mon, 13 Jun 2022 15:50:17 +0300
Subject: [PATCH 0543/1731] mlxsw: spectrum_cnt: Reorder counter pools

Both RIF and ACL flow counters use a 24-bit SW-managed counter address to
communicate which counter they want to bind.

In a number of Spectrum FW releases, binding a RIF counter is broken and
slices the counter index to 16 bits. As a result, on Spectrum-2 and above,
no more than about 410 RIF counters can be effectively used. This
translates to 205 netdevices for which L3 HW stats can be enabled. (This
does not happen on Spectrum-1, because there are fewer counters available
overall and the counter index never exceeds 16 bits.)

Binding counters to ACLs does not have this issue. Therefore reorder the
counter allocation scheme so that RIF counters come first and therefore get
lower indices that are below the 16-bit barrier.

Fixes: 98e60dce4da1 ("Merge branch 'mlxsw-Introduce-initial-Spectrum-2-support'")
Reported-by: Maksym Yaremchuk <maksymy@nvidia.com>
Signed-off-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Link: https://lore.kernel.org/r/20220613125017.2018162-1-idosch@nvidia.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
 drivers/net/ethernet/mellanox/mlxsw/spectrum_cnt.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_cnt.h b/drivers/net/ethernet/mellanox/mlxsw/spectrum_cnt.h
index a68d931090dd5..15c8d4de83508 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_cnt.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_cnt.h
@@ -8,8 +8,8 @@
 #include "spectrum.h"
 
 enum mlxsw_sp_counter_sub_pool_id {
-	MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 	MLXSW_SP_COUNTER_SUB_POOL_RIF,
+	MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 };
 
 int mlxsw_sp_counter_alloc(struct mlxsw_sp *mlxsw_sp,
-- 
GitLab


From a6e944f25cdbe6b82275402b8bc9a55ad7aac10b Mon Sep 17 00:00:00 2001
From: Ciara Loftus <ciara.loftus@intel.com>
Date: Tue, 14 Jun 2022 07:07:46 +0000
Subject: [PATCH 0544/1731] xsk: Fix generic transmit when completion queue
 reservation fails

Two points of potential failure in the generic transmit function are:

  1. completion queue (cq) reservation failure.
  2. skb allocation failure

Originally the cq reservation was performed first, followed by the skb
allocation. Commit 675716400da6 ("xdp: fix possible cq entry leak")
reversed the order because at the time there was no mechanism available
to undo the cq reservation which could have led to possible cq entry leaks
in the event of skb allocation failure. However if the skb allocation is
performed first and the cq reservation then fails, the xsk skb destructor
is called which blindly adds the skb address to the already full cq leading
to undefined behavior.

This commit restores the original order (cq reservation followed by skb
allocation) and uses the xskq_prod_cancel helper to undo the cq reserve
in event of skb allocation failure.

Fixes: 675716400da6 ("xdp: fix possible cq entry leak")
Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Magnus Karlsson <magnus.karlsson@intel.com>
Link: https://lore.kernel.org/bpf/20220614070746.8871-1-ciara.loftus@intel.com
---
 net/xdp/xsk.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/net/xdp/xsk.c b/net/xdp/xsk.c
index 19ac872a66240..09002387987ea 100644
--- a/net/xdp/xsk.c
+++ b/net/xdp/xsk.c
@@ -538,12 +538,6 @@ static int xsk_generic_xmit(struct sock *sk)
 			goto out;
 		}
 
-		skb = xsk_build_skb(xs, &desc);
-		if (IS_ERR(skb)) {
-			err = PTR_ERR(skb);
-			goto out;
-		}
-
 		/* This is the backpressure mechanism for the Tx path.
 		 * Reserve space in the completion queue and only proceed
 		 * if there is space in it. This avoids having to implement
@@ -552,11 +546,19 @@ static int xsk_generic_xmit(struct sock *sk)
 		spin_lock_irqsave(&xs->pool->cq_lock, flags);
 		if (xskq_prod_reserve(xs->pool->cq)) {
 			spin_unlock_irqrestore(&xs->pool->cq_lock, flags);
-			kfree_skb(skb);
 			goto out;
 		}
 		spin_unlock_irqrestore(&xs->pool->cq_lock, flags);
 
+		skb = xsk_build_skb(xs, &desc);
+		if (IS_ERR(skb)) {
+			err = PTR_ERR(skb);
+			spin_lock_irqsave(&xs->pool->cq_lock, flags);
+			xskq_prod_cancel(xs->pool->cq);
+			spin_unlock_irqrestore(&xs->pool->cq_lock, flags);
+			goto out;
+		}
+
 		err = __dev_direct_xmit(skb, xs->queue_id);
 		if  (err == NETDEV_TX_BUSY) {
 			/* Tell user-space to retry the send */
-- 
GitLab


From 71a579f0d3777a704355e6f1572dfba92a9b58b2 Mon Sep 17 00:00:00 2001
From: Michal Michalik <michal.michalik@intel.com>
Date: Tue, 10 May 2022 13:03:43 +0200
Subject: [PATCH 0545/1731] ice: Fix PTP TX timestamp offset calculation

The offset was being incorrectly calculated for E822 - that led to
collisions in choosing TX timestamp register location when more than
one port was trying to use timestamping mechanism.

In E822 one quad is being logically split between ports, so quad 0 is
having trackers for ports 0-3, quad 1 ports 4-7 etc. Each port should
have separate memory location for tracking timestamps. Due to error for
example ports 1 and 2 had been assigned to quad 0 with same offset (0),
while port 1 should have offset 0 and 1 offset 16.

Fix it by correctly calculating quad offset.

Fixes: 3a7496234d17 ("ice: implement basic E822 PTP support")
Signed-off-by: Michal Michalik <michal.michalik@intel.com>
Tested-by: Gurucharan <gurucharanx.g@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
---
 drivers/net/ethernet/intel/ice/ice_ptp.c |  2 +-
 drivers/net/ethernet/intel/ice/ice_ptp.h | 31 ++++++++++++++++++++++++
 2 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c
index 662947c882e8b..ef9344ef0d8e4 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp.c
@@ -2271,7 +2271,7 @@ static int
 ice_ptp_init_tx_e822(struct ice_pf *pf, struct ice_ptp_tx *tx, u8 port)
 {
 	tx->quad = port / ICE_PORTS_PER_QUAD;
-	tx->quad_offset = tx->quad * INDEX_PER_PORT;
+	tx->quad_offset = (port % ICE_PORTS_PER_QUAD) * INDEX_PER_PORT;
 	tx->len = INDEX_PER_PORT;
 
 	return ice_ptp_alloc_tx_tracker(tx);
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.h b/drivers/net/ethernet/intel/ice/ice_ptp.h
index afd048d699598..10e396abf1309 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp.h
+++ b/drivers/net/ethernet/intel/ice/ice_ptp.h
@@ -49,6 +49,37 @@ struct ice_perout_channel {
  * To allow multiple ports to access the shared register block independently,
  * the blocks are split up so that indexes are assigned to each port based on
  * hardware logical port number.
+ *
+ * The timestamp blocks are handled differently for E810- and E822-based
+ * devices. In E810 devices, each port has its own block of timestamps, while in
+ * E822 there is a need to logically break the block of registers into smaller
+ * chunks based on the port number to avoid collisions.
+ *
+ * Example for port 5 in E810:
+ *  +--------+--------+--------+--------+--------+--------+--------+--------+
+ *  |register|register|register|register|register|register|register|register|
+ *  | block  | block  | block  | block  | block  | block  | block  | block  |
+ *  |  for   |  for   |  for   |  for   |  for   |  for   |  for   |  for   |
+ *  | port 0 | port 1 | port 2 | port 3 | port 4 | port 5 | port 6 | port 7 |
+ *  +--------+--------+--------+--------+--------+--------+--------+--------+
+ *                                               ^^
+ *                                               ||
+ *                                               |---  quad offset is always 0
+ *                                               ---- quad number
+ *
+ * Example for port 5 in E822:
+ * +-----------------------------+-----------------------------+
+ * |  register block for quad 0  |  register block for quad 1  |
+ * |+------+------+------+------+|+------+------+------+------+|
+ * ||port 0|port 1|port 2|port 3|||port 0|port 1|port 2|port 3||
+ * |+------+------+------+------+|+------+------+------+------+|
+ * +-----------------------------+-------^---------------------+
+ *                                ^      |
+ *                                |      --- quad offset*
+ *                                ---- quad number
+ *
+ *   * PHY port 5 is port 1 in quad 1
+ *
  */
 
 /**
-- 
GitLab


From 9542ef4fba8c73e176b8aa18a8adf04aecb889e5 Mon Sep 17 00:00:00 2001
From: Roman Storozhenko <roman.storozhenko@intel.com>
Date: Tue, 7 Jun 2022 08:54:57 +0200
Subject: [PATCH 0546/1731] ice: Sync VLAN filtering features for DVM

VLAN filtering features, that is C-Tag and S-Tag, in DVM mode must be
both enabled or disabled.
In case of turning off/on only one of the features, another feature must
be turned off/on automatically with issuing an appropriate message to
the kernel log.

Fixes: 1babaf77f49d ("ice: Advertise 802.1ad VLAN filtering and offloads for PF netdev")
Signed-off-by: Roman Storozhenko <roman.storozhenko@intel.com>
Co-developed-by: Anatolii Gerasymenko <anatolii.gerasymenko@intel.com>
Signed-off-by: Anatolii Gerasymenko <anatolii.gerasymenko@intel.com>
Tested-by: Gurucharan <gurucharanx.g@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
---
 drivers/net/ethernet/intel/ice/ice_main.c | 49 ++++++++++++++---------
 1 file changed, 31 insertions(+), 18 deletions(-)

diff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c
index e1cae253412c7..c1ac2f7467148 100644
--- a/drivers/net/ethernet/intel/ice/ice_main.c
+++ b/drivers/net/ethernet/intel/ice/ice_main.c
@@ -5763,25 +5763,38 @@ static netdev_features_t
 ice_fix_features(struct net_device *netdev, netdev_features_t features)
 {
 	struct ice_netdev_priv *np = netdev_priv(netdev);
-	netdev_features_t supported_vlan_filtering;
-	netdev_features_t requested_vlan_filtering;
-	struct ice_vsi *vsi = np->vsi;
-
-	requested_vlan_filtering = features & NETIF_VLAN_FILTERING_FEATURES;
-
-	/* make sure supported_vlan_filtering works for both SVM and DVM */
-	supported_vlan_filtering = NETIF_F_HW_VLAN_CTAG_FILTER;
-	if (ice_is_dvm_ena(&vsi->back->hw))
-		supported_vlan_filtering |= NETIF_F_HW_VLAN_STAG_FILTER;
-
-	if (requested_vlan_filtering &&
-	    requested_vlan_filtering != supported_vlan_filtering) {
-		if (requested_vlan_filtering & NETIF_F_HW_VLAN_CTAG_FILTER) {
-			netdev_warn(netdev, "cannot support requested VLAN filtering settings, enabling all supported VLAN filtering settings\n");
-			features |= supported_vlan_filtering;
+	netdev_features_t req_vlan_fltr, cur_vlan_fltr;
+	bool cur_ctag, cur_stag, req_ctag, req_stag;
+
+	cur_vlan_fltr = netdev->features & NETIF_VLAN_FILTERING_FEATURES;
+	cur_ctag = cur_vlan_fltr & NETIF_F_HW_VLAN_CTAG_FILTER;
+	cur_stag = cur_vlan_fltr & NETIF_F_HW_VLAN_STAG_FILTER;
+
+	req_vlan_fltr = features & NETIF_VLAN_FILTERING_FEATURES;
+	req_ctag = req_vlan_fltr & NETIF_F_HW_VLAN_CTAG_FILTER;
+	req_stag = req_vlan_fltr & NETIF_F_HW_VLAN_STAG_FILTER;
+
+	if (req_vlan_fltr != cur_vlan_fltr) {
+		if (ice_is_dvm_ena(&np->vsi->back->hw)) {
+			if (req_ctag && req_stag) {
+				features |= NETIF_VLAN_FILTERING_FEATURES;
+			} else if (!req_ctag && !req_stag) {
+				features &= ~NETIF_VLAN_FILTERING_FEATURES;
+			} else if ((!cur_ctag && req_ctag && !cur_stag) ||
+				   (!cur_stag && req_stag && !cur_ctag)) {
+				features |= NETIF_VLAN_FILTERING_FEATURES;
+				netdev_warn(netdev,  "802.1Q and 802.1ad VLAN filtering must be either both on or both off. VLAN filtering has been enabled for both types.\n");
+			} else if ((cur_ctag && !req_ctag && cur_stag) ||
+				   (cur_stag && !req_stag && cur_ctag)) {
+				features &= ~NETIF_VLAN_FILTERING_FEATURES;
+				netdev_warn(netdev,  "802.1Q and 802.1ad VLAN filtering must be either both on or both off. VLAN filtering has been disabled for both types.\n");
+			}
 		} else {
-			netdev_warn(netdev, "cannot support requested VLAN filtering settings, clearing all supported VLAN filtering settings\n");
-			features &= ~supported_vlan_filtering;
+			if (req_vlan_fltr & NETIF_F_HW_VLAN_STAG_FILTER)
+				netdev_warn(netdev, "cannot support requested 802.1ad filtering setting in SVM mode\n");
+
+			if (req_vlan_fltr & NETIF_F_HW_VLAN_CTAG_FILTER)
+				features |= NETIF_F_HW_VLAN_CTAG_FILTER;
 		}
 	}
 
-- 
GitLab


From be2af71496a54a7195ac62caba6fab49cfe5006c Mon Sep 17 00:00:00 2001
From: Przemyslaw Patynowski <przemyslawx.patynowski@intel.com>
Date: Thu, 2 Jun 2022 12:09:04 +0200
Subject: [PATCH 0547/1731] ice: Fix queue config fail handling

Disable VF's RX/TX queues, when VIRTCHNL_OP_CONFIG_VSI_QUEUES fail.
Not disabling them might lead to scenario, where PF driver leaves VF
queues enabled, when VF's VSI failed queue config.
In this scenario VF should not have RX/TX queues enabled. If PF failed
to set up VF's queues, VF will reset due to TX timeouts in VF driver.
Initialize iterator 'i' to -1, so if error happens prior to configuring
queues then error path code will not disable queue 0. Loop that
configures queues will is using same iterator, so error path code will
only disable queues that were configured.

Fixes: 77ca27c41705 ("ice: add support for virtchnl_queue_select.[tx|rx]_queues bitmap")
Suggested-by: Slawomir Laba <slawomirx.laba@intel.com>
Signed-off-by: Przemyslaw Patynowski <przemyslawx.patynowski@intel.com>
Signed-off-by: Mateusz Palczewski <mateusz.palczewski@intel.com>
Tested-by: Konrad Jankowski <konrad0.jankowski@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
---
 drivers/net/ethernet/intel/ice/ice_virtchnl.c | 53 +++++++++----------
 1 file changed, 26 insertions(+), 27 deletions(-)

diff --git a/drivers/net/ethernet/intel/ice/ice_virtchnl.c b/drivers/net/ethernet/intel/ice/ice_virtchnl.c
index 1d9b84c3937aa..4547bc1f7cee7 100644
--- a/drivers/net/ethernet/intel/ice/ice_virtchnl.c
+++ b/drivers/net/ethernet/intel/ice/ice_virtchnl.c
@@ -1569,35 +1569,27 @@ error_param:
  */
 static int ice_vc_cfg_qs_msg(struct ice_vf *vf, u8 *msg)
 {
-	enum virtchnl_status_code v_ret = VIRTCHNL_STATUS_SUCCESS;
 	struct virtchnl_vsi_queue_config_info *qci =
 	    (struct virtchnl_vsi_queue_config_info *)msg;
 	struct virtchnl_queue_pair_info *qpi;
 	struct ice_pf *pf = vf->pf;
 	struct ice_vsi *vsi;
-	int i, q_idx;
+	int i = -1, q_idx;
 
-	if (!test_bit(ICE_VF_STATE_ACTIVE, vf->vf_states)) {
-		v_ret = VIRTCHNL_STATUS_ERR_PARAM;
+	if (!test_bit(ICE_VF_STATE_ACTIVE, vf->vf_states))
 		goto error_param;
-	}
 
-	if (!ice_vc_isvalid_vsi_id(vf, qci->vsi_id)) {
-		v_ret = VIRTCHNL_STATUS_ERR_PARAM;
+	if (!ice_vc_isvalid_vsi_id(vf, qci->vsi_id))
 		goto error_param;
-	}
 
 	vsi = ice_get_vf_vsi(vf);
-	if (!vsi) {
-		v_ret = VIRTCHNL_STATUS_ERR_PARAM;
+	if (!vsi)
 		goto error_param;
-	}
 
 	if (qci->num_queue_pairs > ICE_MAX_RSS_QS_PER_VF ||
 	    qci->num_queue_pairs > min_t(u16, vsi->alloc_txq, vsi->alloc_rxq)) {
 		dev_err(ice_pf_to_dev(pf), "VF-%d requesting more than supported number of queues: %d\n",
 			vf->vf_id, min_t(u16, vsi->alloc_txq, vsi->alloc_rxq));
-		v_ret = VIRTCHNL_STATUS_ERR_PARAM;
 		goto error_param;
 	}
 
@@ -1610,7 +1602,6 @@ static int ice_vc_cfg_qs_msg(struct ice_vf *vf, u8 *msg)
 		    !ice_vc_isvalid_ring_len(qpi->txq.ring_len) ||
 		    !ice_vc_isvalid_ring_len(qpi->rxq.ring_len) ||
 		    !ice_vc_isvalid_q_id(vf, qci->vsi_id, qpi->txq.queue_id)) {
-			v_ret = VIRTCHNL_STATUS_ERR_PARAM;
 			goto error_param;
 		}
 
@@ -1620,7 +1611,6 @@ static int ice_vc_cfg_qs_msg(struct ice_vf *vf, u8 *msg)
 		 * for selected "vsi"
 		 */
 		if (q_idx >= vsi->alloc_txq || q_idx >= vsi->alloc_rxq) {
-			v_ret = VIRTCHNL_STATUS_ERR_PARAM;
 			goto error_param;
 		}
 
@@ -1630,14 +1620,13 @@ static int ice_vc_cfg_qs_msg(struct ice_vf *vf, u8 *msg)
 			vsi->tx_rings[i]->count = qpi->txq.ring_len;
 
 			/* Disable any existing queue first */
-			if (ice_vf_vsi_dis_single_txq(vf, vsi, q_idx)) {
-				v_ret = VIRTCHNL_STATUS_ERR_PARAM;
+			if (ice_vf_vsi_dis_single_txq(vf, vsi, q_idx))
 				goto error_param;
-			}
 
 			/* Configure a queue with the requested settings */
 			if (ice_vsi_cfg_single_txq(vsi, vsi->tx_rings, q_idx)) {
-				v_ret = VIRTCHNL_STATUS_ERR_PARAM;
+				dev_warn(ice_pf_to_dev(pf), "VF-%d failed to configure TX queue %d\n",
+					 vf->vf_id, i);
 				goto error_param;
 			}
 		}
@@ -1651,17 +1640,13 @@ static int ice_vc_cfg_qs_msg(struct ice_vf *vf, u8 *msg)
 
 			if (qpi->rxq.databuffer_size != 0 &&
 			    (qpi->rxq.databuffer_size > ((16 * 1024) - 128) ||
-			     qpi->rxq.databuffer_size < 1024)) {
-				v_ret = VIRTCHNL_STATUS_ERR_PARAM;
+			     qpi->rxq.databuffer_size < 1024))
 				goto error_param;
-			}
 			vsi->rx_buf_len = qpi->rxq.databuffer_size;
 			vsi->rx_rings[i]->rx_buf_len = vsi->rx_buf_len;
 			if (qpi->rxq.max_pkt_size > max_frame_size ||
-			    qpi->rxq.max_pkt_size < 64) {
-				v_ret = VIRTCHNL_STATUS_ERR_PARAM;
+			    qpi->rxq.max_pkt_size < 64)
 				goto error_param;
-			}
 
 			vsi->max_frame = qpi->rxq.max_pkt_size;
 			/* add space for the port VLAN since the VF driver is
@@ -1672,16 +1657,30 @@ static int ice_vc_cfg_qs_msg(struct ice_vf *vf, u8 *msg)
 				vsi->max_frame += VLAN_HLEN;
 
 			if (ice_vsi_cfg_single_rxq(vsi, q_idx)) {
-				v_ret = VIRTCHNL_STATUS_ERR_PARAM;
+				dev_warn(ice_pf_to_dev(pf), "VF-%d failed to configure RX queue %d\n",
+					 vf->vf_id, i);
 				goto error_param;
 			}
 		}
 	}
 
+	/* send the response to the VF */
+	return ice_vc_send_msg_to_vf(vf, VIRTCHNL_OP_CONFIG_VSI_QUEUES,
+				     VIRTCHNL_STATUS_SUCCESS, NULL, 0);
 error_param:
+	/* disable whatever we can */
+	for (; i >= 0; i--) {
+		if (ice_vsi_ctrl_one_rx_ring(vsi, false, i, true))
+			dev_err(ice_pf_to_dev(pf), "VF-%d could not disable RX queue %d\n",
+				vf->vf_id, i);
+		if (ice_vf_vsi_dis_single_txq(vf, vsi, i))
+			dev_err(ice_pf_to_dev(pf), "VF-%d could not disable TX queue %d\n",
+				vf->vf_id, i);
+	}
+
 	/* send the response to the VF */
-	return ice_vc_send_msg_to_vf(vf, VIRTCHNL_OP_CONFIG_VSI_QUEUES, v_ret,
-				     NULL, 0);
+	return ice_vc_send_msg_to_vf(vf, VIRTCHNL_OP_CONFIG_VSI_QUEUES,
+				     VIRTCHNL_STATUS_ERR_PARAM, NULL, 0);
 }
 
 /**
-- 
GitLab


From efe41860008e57fb6b69855b4b93fdf34bc42798 Mon Sep 17 00:00:00 2001
From: Przemyslaw Patynowski <przemyslawx.patynowski@intel.com>
Date: Thu, 2 Jun 2022 12:09:17 +0200
Subject: [PATCH 0548/1731] ice: Fix memory corruption in VF driver

Disable VF's RX/TX queues, when it's disabled. VF can have queues enabled,
when it requests a reset. If PF driver assumes that VF is disabled,
while VF still has queues configured, VF may unmap DMA resources.
In such scenario device still can map packets to memory, which ends up
silently corrupting it.
Previously, VF driver could experience memory corruption, which lead to
crash:
[ 5119.170157] BUG: unable to handle kernel paging request at 00001b9780003237
[ 5119.170166] PGD 0 P4D 0
[ 5119.170173] Oops: 0002 [#1] PREEMPT_RT SMP PTI
[ 5119.170181] CPU: 30 PID: 427592 Comm: kworker/u96:2 Kdump: loaded Tainted: G        W I      --------- -  - 4.18.0-372.9.1.rt7.166.el8.x86_64 #1
[ 5119.170189] Hardware name: Dell Inc. PowerEdge R740/014X06, BIOS 2.3.10 08/15/2019
[ 5119.170193] Workqueue: iavf iavf_adminq_task [iavf]
[ 5119.170219] RIP: 0010:__page_frag_cache_drain+0x5/0x30
[ 5119.170238] Code: 0f 0f b6 77 51 85 f6 74 07 31 d2 e9 05 df ff ff e9 90 fe ff ff 48 8b 05 49 db 33 01 eb b4 0f 1f 80 00 00 00 00 0f 1f 44 00 00 <f0> 29 77 34 74 01 c3 48 8b 07 f6 c4 80 74 0f 0f b6 77 51 85 f6 74
[ 5119.170244] RSP: 0018:ffffa43b0bdcfd78 EFLAGS: 00010282
[ 5119.170250] RAX: ffffffff896b3e40 RBX: ffff8fb282524000 RCX: 0000000000000002
[ 5119.170254] RDX: 0000000049000000 RSI: 0000000000000000 RDI: 00001b9780003203
[ 5119.170259] RBP: ffff8fb248217b00 R08: 0000000000000022 R09: 0000000000000009
[ 5119.170262] R10: 2b849d6300000000 R11: 0000000000000020 R12: 0000000000000000
[ 5119.170265] R13: 0000000000001000 R14: 0000000000000009 R15: 0000000000000000
[ 5119.170269] FS:  0000000000000000(0000) GS:ffff8fb1201c0000(0000) knlGS:0000000000000000
[ 5119.170274] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 5119.170279] CR2: 00001b9780003237 CR3: 00000008f3e1a003 CR4: 00000000007726e0
[ 5119.170283] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[ 5119.170286] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
[ 5119.170290] PKRU: 55555554
[ 5119.170292] Call Trace:
[ 5119.170298]  iavf_clean_rx_ring+0xad/0x110 [iavf]
[ 5119.170324]  iavf_free_rx_resources+0xe/0x50 [iavf]
[ 5119.170342]  iavf_free_all_rx_resources.part.51+0x30/0x40 [iavf]
[ 5119.170358]  iavf_virtchnl_completion+0xd8a/0x15b0 [iavf]
[ 5119.170377]  ? iavf_clean_arq_element+0x210/0x280 [iavf]
[ 5119.170397]  iavf_adminq_task+0x126/0x2e0 [iavf]
[ 5119.170416]  process_one_work+0x18f/0x420
[ 5119.170429]  worker_thread+0x30/0x370
[ 5119.170437]  ? process_one_work+0x420/0x420
[ 5119.170445]  kthread+0x151/0x170
[ 5119.170452]  ? set_kthread_struct+0x40/0x40
[ 5119.170460]  ret_from_fork+0x35/0x40
[ 5119.170477] Modules linked in: iavf sctp ip6_udp_tunnel udp_tunnel mlx4_en mlx4_core nfp tls vhost_net vhost vhost_iotlb tap tun xt_CHECKSUM ipt_MASQUERADE xt_conntrack ipt_REJECT nf_reject_ipv4 nft_compat nft_counter nft_chain_nat nf_nat nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 nf_tables nfnetlink bridge stp llc rpcsec_gss_krb5 auth_rpcgss nfsv4 dns_resolver nfs lockd grace fscache sunrpc intel_rapl_msr iTCO_wdt iTCO_vendor_support dell_smbios wmi_bmof dell_wmi_descriptor dcdbas kvm_intel kvm irqbypass intel_rapl_common isst_if_common skx_edac irdma nfit libnvdimm x86_pkg_temp_thermal i40e intel_powerclamp coretemp crct10dif_pclmul crc32_pclmul ghash_clmulni_intel ib_uverbs rapl ipmi_ssif intel_cstate intel_uncore mei_me pcspkr acpi_ipmi ib_core mei lpc_ich i2c_i801 ipmi_si ipmi_devintf wmi ipmi_msghandler acpi_power_meter xfs libcrc32c sd_mod t10_pi sg mgag200 drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops ice ahci drm libahci crc32c_intel libata tg3 megaraid_sas
[ 5119.170613]  i2c_algo_bit dm_mirror dm_region_hash dm_log dm_mod fuse [last unloaded: iavf]
[ 5119.170627] CR2: 00001b9780003237

Fixes: ec4f5a436bdf ("ice: Check if VF is disabled for Opcode and other operations")
Signed-off-by: Przemyslaw Patynowski <przemyslawx.patynowski@intel.com>
Co-developed-by: Slawomir Laba <slawomirx.laba@intel.com>
Signed-off-by: Slawomir Laba <slawomirx.laba@intel.com>
Signed-off-by: Mateusz Palczewski <mateusz.palczewski@intel.com>
Tested-by: Konrad Jankowski <konrad0.jankowski@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
---
 drivers/net/ethernet/intel/ice/ice_vf_lib.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/net/ethernet/intel/ice/ice_vf_lib.c b/drivers/net/ethernet/intel/ice/ice_vf_lib.c
index cd8e6b50968c1..7adf9ddf129eb 100644
--- a/drivers/net/ethernet/intel/ice/ice_vf_lib.c
+++ b/drivers/net/ethernet/intel/ice/ice_vf_lib.c
@@ -504,6 +504,11 @@ int ice_reset_vf(struct ice_vf *vf, u32 flags)
 	}
 
 	if (ice_is_vf_disabled(vf)) {
+		vsi = ice_get_vf_vsi(vf);
+		if (WARN_ON(!vsi))
+			return -EINVAL;
+		ice_vsi_stop_lan_tx_rings(vsi, ICE_NO_RESET, vf->vf_id);
+		ice_vsi_stop_all_rx_rings(vsi);
 		dev_dbg(dev, "VF is already disabled, there is no need for resetting it, telling VM, all is fine %d\n",
 			vf->vf_id);
 		return 0;
-- 
GitLab


From 8899ce4b2f7364a90e3b9cf332dfd9993c61f46c Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Tue, 14 Jun 2022 17:51:16 +0100
Subject: [PATCH 0549/1731] Revert "io_uring: support CQE32 for nop operation"

This reverts commit 2bb04df7c2af9dad5d28771c723bc39b01cf7df4.

CQE32 nops were used for debugging and benchmarking but it doesn't
target any real use case. Revert it, we can return it back if someone
finds a good way to use it.

Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
Link: https://lore.kernel.org/r/5ff623d84ccb4b3f3b92a3ea41cdcfa612f3d96f.1655224415.git.asml.silence@gmail.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 21 +--------------------
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index ca6170a66e62f..bf556f77d4abc 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -784,12 +784,6 @@ struct io_msg {
 	u32 len;
 };
 
-struct io_nop {
-	struct file			*file;
-	u64				extra1;
-	u64				extra2;
-};
-
 struct io_async_connect {
 	struct sockaddr_storage		address;
 };
@@ -994,7 +988,6 @@ struct io_kiocb {
 		struct io_msg		msg;
 		struct io_xattr		xattr;
 		struct io_socket	sock;
-		struct io_nop		nop;
 		struct io_uring_cmd	uring_cmd;
 	};
 
@@ -5268,14 +5261,6 @@ done:
 
 static int io_nop_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe)
 {
-	/*
-	 * If the ring is setup with CQE32, relay back addr/addr
-	 */
-	if (req->ctx->flags & IORING_SETUP_CQE32) {
-		req->nop.extra1 = READ_ONCE(sqe->addr);
-		req->nop.extra2 = READ_ONCE(sqe->addr2);
-	}
-
 	return 0;
 }
 
@@ -5296,11 +5281,7 @@ static int io_nop(struct io_kiocb *req, unsigned int issue_flags)
 	}
 
 	cflags = io_put_kbuf(req, issue_flags);
-	if (!(req->ctx->flags & IORING_SETUP_CQE32))
-		__io_req_complete(req, issue_flags, 0, cflags);
-	else
-		__io_req_complete32(req, issue_flags, 0, cflags,
-				    req->nop.extra1, req->nop.extra2);
+	__io_req_complete(req, issue_flags, 0, cflags);
 	return 0;
 }
 
-- 
GitLab


From aa165d6d2bb55f8b1bb5047fd634311681316fa2 Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Tue, 14 Jun 2022 17:51:17 +0100
Subject: [PATCH 0550/1731] Revert "io_uring: add buffer selection support to
 IORING_OP_NOP"

This reverts commit 3d200242a6c968af321913b635fc4014b238cba4.

Buffer selection with nops was used for debugging and benchmarking but
is useless in real life. Let's revert it before it's released.

Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
Link: https://lore.kernel.org/r/c5012098ca6b51dfbdcb190f8c4e3c0bf1c965dc.1655224415.git.asml.silence@gmail.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 15 +--------------
 1 file changed, 1 insertion(+), 14 deletions(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index bf556f77d4abc..1b95c6750a81b 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -1114,7 +1114,6 @@ static const struct io_op_def io_op_defs[] = {
 	[IORING_OP_NOP] = {
 		.audit_skip		= 1,
 		.iopoll			= 1,
-		.buffer_select		= 1,
 	},
 	[IORING_OP_READV] = {
 		.needs_file		= 1,
@@ -5269,19 +5268,7 @@ static int io_nop_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe)
  */
 static int io_nop(struct io_kiocb *req, unsigned int issue_flags)
 {
-	unsigned int cflags;
-	void __user *buf;
-
-	if (req->flags & REQ_F_BUFFER_SELECT) {
-		size_t len = 1;
-
-		buf = io_buffer_select(req, &len, issue_flags);
-		if (!buf)
-			return -ENOBUFS;
-	}
-
-	cflags = io_put_kbuf(req, issue_flags);
-	__io_req_complete(req, issue_flags, 0, cflags);
+	__io_req_complete(req, issue_flags, 0, 0);
 	return 0;
 }
 
-- 
GitLab


From d884b6498d2f022098502e106d5a45ab635f2e9a Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Tue, 14 Jun 2022 17:51:18 +0100
Subject: [PATCH 0551/1731] io_uring: remove IORING_CLOSE_FD_AND_FILE_SLOT

This partially reverts a7c41b4687f5902af70cd559806990930c8a307b

Even though IORING_CLOSE_FD_AND_FILE_SLOT might save cycles for some
users, but it tries to do two things at a time and it's not clear how to
handle errors and what to return in a single result field when one part
fails and another completes well. Kill it for now.

Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
Link: https://lore.kernel.org/r/837c745019b3795941eee4fcfd7de697886d645b.1655224415.git.asml.silence@gmail.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c                 | 12 +++---------
 include/uapi/linux/io_uring.h |  6 ------
 2 files changed, 3 insertions(+), 15 deletions(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index 1b95c6750a81b..1b0b6099e7174 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -576,7 +576,6 @@ struct io_close {
 	struct file			*file;
 	int				fd;
 	u32				file_slot;
-	u32				flags;
 };
 
 struct io_timeout_data {
@@ -5966,18 +5965,14 @@ static int io_statx(struct io_kiocb *req, unsigned int issue_flags)
 
 static int io_close_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe)
 {
-	if (sqe->off || sqe->addr || sqe->len || sqe->buf_index)
+	if (sqe->off || sqe->addr || sqe->len || sqe->rw_flags || sqe->buf_index)
 		return -EINVAL;
 	if (req->flags & REQ_F_FIXED_FILE)
 		return -EBADF;
 
 	req->close.fd = READ_ONCE(sqe->fd);
 	req->close.file_slot = READ_ONCE(sqe->file_index);
-	req->close.flags = READ_ONCE(sqe->close_flags);
-	if (req->close.flags & ~IORING_CLOSE_FD_AND_FILE_SLOT)
-		return -EINVAL;
-	if (!(req->close.flags & IORING_CLOSE_FD_AND_FILE_SLOT) &&
-	    req->close.file_slot && req->close.fd)
+	if (req->close.file_slot && req->close.fd)
 		return -EINVAL;
 
 	return 0;
@@ -5993,8 +5988,7 @@ static int io_close(struct io_kiocb *req, unsigned int issue_flags)
 
 	if (req->close.file_slot) {
 		ret = io_close_fixed(req, issue_flags);
-		if (ret || !(req->close.flags & IORING_CLOSE_FD_AND_FILE_SLOT))
-			goto err;
+		goto err;
 	}
 
 	spin_lock(&files->file_lock);
diff --git a/include/uapi/linux/io_uring.h b/include/uapi/linux/io_uring.h
index 776e0278f9dd4..53e7dae92e42e 100644
--- a/include/uapi/linux/io_uring.h
+++ b/include/uapi/linux/io_uring.h
@@ -47,7 +47,6 @@ struct io_uring_sqe {
 		__u32		unlink_flags;
 		__u32		hardlink_flags;
 		__u32		xattr_flags;
-		__u32		close_flags;
 	};
 	__u64	user_data;	/* data to be passed back at completion time */
 	/* pack this to avoid bogus arm OABI complaints */
@@ -259,11 +258,6 @@ enum io_uring_op {
  */
 #define IORING_ACCEPT_MULTISHOT	(1U << 0)
 
-/*
- * close flags, store in sqe->close_flags
- */
-#define IORING_CLOSE_FD_AND_FILE_SLOT	(1U << 0)
-
 /*
  * IO completion data structure (Completion Queue Entry)
  */
-- 
GitLab


From c904e3acbab3fd97649cd4ab1ff7f1521ad3a255 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <mdaenzer@redhat.com>
Date: Fri, 10 Jun 2022 15:54:26 +0200
Subject: [PATCH 0552/1731] drm/amdgpu: Fix GTT size reporting in amdgpu_ioctl
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The commit below changed the TTM manager size unit from pages to
bytes, but failed to adjust the corresponding calculations in
amdgpu_ioctl.

Fixes: dfa714b88eb0 ("drm/amdgpu: remove GTT accounting v2")
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1930
Bug: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6642
Tested-by: Martin Roukala <martin.roukala@mupuf.org>
Tested-by: Mike Lothian <mike@fireburn.co.uk>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <mdaenzer@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 5.18.x
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 801f6fa692e98..6de63ea6687eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -642,7 +642,6 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 			    atomic64_read(&adev->visible_pin_size),
 			    vram_gtt.vram_size);
 		vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
-		vram_gtt.gtt_size *= PAGE_SIZE;
 		vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 		return copy_to_user(out, &vram_gtt,
 				    min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
@@ -675,7 +674,6 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 			mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 
 		mem.gtt.total_heap_size = gtt_man->size;
-		mem.gtt.total_heap_size *= PAGE_SIZE;
 		mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 			atomic64_read(&adev->gart_pin_size);
 		mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
-- 
GitLab


From 4fd17f2ac0aa4e48823ac2ede5b050fb70300bf4 Mon Sep 17 00:00:00 2001
From: Roman Li <roman.li@amd.com>
Date: Thu, 19 May 2022 14:41:16 -0400
Subject: [PATCH 0553/1731] drm/amd/display: Cap OLED brightness per max
 frame-average luminance

[Why]
For OLED eDP the Display Manager uses max_cll value as a limit
for brightness control.
max_cll defines the content light luminance for individual pixel.
Whereas max_fall defines frame-average level luminance.
The user may not observe the difference in brightness in between
max_fall and max_cll.
That negatively impacts the user experience.

[How]
Use max_fall value instead of max_cll as a limit for brightness control.

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 70be67a566737..39b425d83bb1a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2812,7 +2812,7 @@ static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
 
 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
 {
-	u32 max_cll, min_cll, max, min, q, r;
+	u32 max_avg, min_cll, max, min, q, r;
 	struct amdgpu_dm_backlight_caps *caps;
 	struct amdgpu_display_manager *dm;
 	struct drm_connector *conn_base;
@@ -2842,7 +2842,7 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
 	caps = &dm->backlight_caps[i];
 	caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
 	caps->aux_support = false;
-	max_cll = conn_base->hdr_sink_metadata.hdmi_type1.max_cll;
+	max_avg = conn_base->hdr_sink_metadata.hdmi_type1.max_fall;
 	min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll;
 
 	if (caps->ext_caps->bits.oled == 1 /*||
@@ -2870,8 +2870,8 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
 	 * The results of the above expressions can be verified at
 	 * pre_computed_values.
 	 */
-	q = max_cll >> 5;
-	r = max_cll % 32;
+	q = max_avg >> 5;
+	r = max_avg % 32;
 	max = (1 << q) * pre_computed_values[r];
 
 	// min luminance: maxLum * (CV/255)^2 / 100
-- 
GitLab


From 795285ef242543bb636556b7225f20adb7d3795c Mon Sep 17 00:00:00 2001
From: Mark Brown <broonie@kernel.org>
Date: Tue, 14 Jun 2022 13:10:45 +0100
Subject: [PATCH 0554/1731] selftests: Fix clang cross compilation

Unlike GCC clang uses a single compiler image to support multiple target
architectures meaning that we can't simply rely on CROSS_COMPILE to select
the output architecture. Instead we must pass --target to the compiler to
tell it what to output, kselftest was not doing this so cross compilation
of kselftest using clang resulted in kselftest being built for the host
architecture.

More work is required to fix tests using custom rules but this gets the
bulk of things building.

Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
---
 tools/testing/selftests/lib.mk | 25 +++++++++++++++++++++++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/tools/testing/selftests/lib.mk b/tools/testing/selftests/lib.mk
index 2a2d240cdc1b4..1a5cc3cd97ec0 100644
--- a/tools/testing/selftests/lib.mk
+++ b/tools/testing/selftests/lib.mk
@@ -7,10 +7,31 @@ else ifneq ($(filter -%,$(LLVM)),)
 LLVM_SUFFIX := $(LLVM)
 endif
 
-CC := $(LLVM_PREFIX)clang$(LLVM_SUFFIX)
+CLANG_TARGET_FLAGS_arm          := arm-linux-gnueabi
+CLANG_TARGET_FLAGS_arm64        := aarch64-linux-gnu
+CLANG_TARGET_FLAGS_hexagon      := hexagon-linux-musl
+CLANG_TARGET_FLAGS_m68k         := m68k-linux-gnu
+CLANG_TARGET_FLAGS_mips         := mipsel-linux-gnu
+CLANG_TARGET_FLAGS_powerpc      := powerpc64le-linux-gnu
+CLANG_TARGET_FLAGS_riscv        := riscv64-linux-gnu
+CLANG_TARGET_FLAGS_s390         := s390x-linux-gnu
+CLANG_TARGET_FLAGS_x86          := x86_64-linux-gnu
+CLANG_TARGET_FLAGS              := $(CLANG_TARGET_FLAGS_$(ARCH))
+
+ifeq ($(CROSS_COMPILE),)
+ifeq ($(CLANG_TARGET_FLAGS),)
+$(error Specify CROSS_COMPILE or add '--target=' option to lib.mk
+else
+CLANG_FLAGS     += --target=$(CLANG_TARGET_FLAGS)
+endif # CLANG_TARGET_FLAGS
+else
+CLANG_FLAGS     += --target=$(notdir $(CROSS_COMPILE:%-=%))
+endif # CROSS_COMPILE
+
+CC := $(LLVM_PREFIX)clang$(LLVM_SUFFIX) $(CLANG_FLAGS) -fintegrated-as
 else
 CC := $(CROSS_COMPILE)gcc
-endif
+endif # LLVM
 
 ifeq (0,$(MAKELEVEL))
     ifeq ($(OUTPUT),)
-- 
GitLab


From 018ab4fabddd94f1c96f3b59e180691b9e88d5d8 Mon Sep 17 00:00:00 2001
From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Tue, 14 Jun 2022 10:36:11 -0700
Subject: [PATCH 0555/1731] netfs: fix up netfs_inode_init() docbook comment

Commit e81fb4198e27 ("netfs: Further cleanups after struct netfs_inode
wrapper introduced") changed the argument types and names, and actually
updated the comment too (although that was thanks to David Howells, not
me: my original patch only changed the code).

But the comment fixup didn't go quite far enough, and didn't change the
argument name in the comment, resulting in

  include/linux/netfs.h:314: warning: Function parameter or member 'ctx' not described in 'netfs_inode_init'
  include/linux/netfs.h:314: warning: Excess function parameter 'inode' description in 'netfs_inode_init'

during htmldoc generation.

Fixes: e81fb4198e27 ("netfs: Further cleanups after struct netfs_inode wrapper introduced")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
---
 include/linux/netfs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/netfs.h b/include/linux/netfs.h
index 097cdd6446652..1773e5df8e65b 100644
--- a/include/linux/netfs.h
+++ b/include/linux/netfs.h
@@ -304,7 +304,7 @@ static inline struct netfs_inode *netfs_inode(struct inode *inode)
 
 /**
  * netfs_inode_init - Initialise a netfslib inode context
- * @inode: The netfs inode to initialise
+ * @ctx: The netfs inode to initialise
  * @ops: The netfs's operations list
  *
  * Initialise the netfs library context struct.  This is expected to follow on
-- 
GitLab


From 62b5e322fb6cc5a5a91fdeba0e4e57e75d9f4387 Mon Sep 17 00:00:00 2001
From: Jonathan Marek <jonathan@marek.ca>
Date: Mon, 13 Jun 2022 18:10:19 -0400
Subject: [PATCH 0556/1731] drm/msm: use for_each_sgtable_sg to iterate over
 scatterlist

The dma_map_sgtable() call (used to invalidate cache) overwrites sgt->nents
with 1, so msm_iommu_pagetable_map maps only the first physical segment.

To fix this problem use for_each_sgtable_sg(), which uses orig_nents.

Fixes: b145c6e65eb0 ("drm/msm: Add support to create a local pagetable")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20220613221019.11399-1-jonathan@marek.ca
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/msm_iommu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index bcaddbba564df..a54ed354578b5 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu/drm/msm/msm_iommu.c
@@ -58,7 +58,7 @@ static int msm_iommu_pagetable_map(struct msm_mmu *mmu, u64 iova,
 	u64 addr = iova;
 	unsigned int i;
 
-	for_each_sg(sgt->sgl, sg, sgt->nents, i) {
+	for_each_sgtable_sg(sgt, sg, i) {
 		size_t size = sg->length;
 		phys_addr_t phys = sg_phys(sg);
 
-- 
GitLab


From de87b603b0919e31578c8fa312a3541f1fb37e1c Mon Sep 17 00:00:00 2001
From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Date: Sun, 22 May 2022 14:22:07 +0200
Subject: [PATCH 0557/1731] i2c: mediatek: Fix an error handling path in
 mtk_i2c_probe()

The clsk are prepared, enabled, then disabled. So if an error occurs after
the disable step, they are still prepared.

Add an error handling path to unprepare the clks in such a case, as already
done in the .remove function.

Fixes: 8b4fc246c3ff ("i2c: mediatek: Optimize master_xfer() and avoid circular locking")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Qii Wang <qii.wang@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
---
 drivers/i2c/busses/i2c-mt65xx.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index bdecb78bfc26d..8e6985354fd59 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -1420,17 +1420,22 @@ static int mtk_i2c_probe(struct platform_device *pdev)
 	if (ret < 0) {
 		dev_err(&pdev->dev,
 			"Request I2C IRQ %d fail\n", irq);
-		return ret;
+		goto err_bulk_unprepare;
 	}
 
 	i2c_set_adapdata(&i2c->adap, i2c);
 	ret = i2c_add_adapter(&i2c->adap);
 	if (ret)
-		return ret;
+		goto err_bulk_unprepare;
 
 	platform_set_drvdata(pdev, i2c);
 
 	return 0;
+
+err_bulk_unprepare:
+	clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
+
+	return ret;
 }
 
 static int mtk_i2c_remove(struct platform_device *pdev)
-- 
GitLab


From e591fcf6b4e39335c9b128b17738fcd2fdd278ae Mon Sep 17 00:00:00 2001
From: Chevron Li <chevron.li@bayhubtech.com>
Date: Thu, 2 Jun 2022 06:25:43 -0700
Subject: [PATCH 0558/1731] mmc: sdhci-pci-o2micro: Fix card detect by dealing
 with debouncing

The result from ->get_cd() may be incorrect as the card detect debouncing
isn't managed correctly. Let's fix it.

Signed-off-by: Chevron Li<chevron.li@bayhubtech.com>
Fixes: 7d44061704dd ("mmc: sdhci-pci-o2micro: Fix O2 Host data read/write DLL Lock phase shift issue")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20220602132543.596-1-chevron.li@bayhubtech.com
[Ulf: Updated the commit message]
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
---
 drivers/mmc/host/sdhci-pci-o2micro.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
index 92c20cb8074a6..0d4d343dbb77d 100644
--- a/drivers/mmc/host/sdhci-pci-o2micro.c
+++ b/drivers/mmc/host/sdhci-pci-o2micro.c
@@ -152,6 +152,8 @@ static int sdhci_o2_get_cd(struct mmc_host *mmc)
 
 	if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS))
 		sdhci_o2_enable_internal_clock(host);
+	else
+		sdhci_o2_wait_card_detect_stable(host);
 
 	return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
 }
-- 
GitLab


From 9affc1b87ecba31458567359b5a28b0b08920a24 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Fri, 10 Jun 2022 16:08:01 -0700
Subject: [PATCH 0559/1731] drm/i915/pvc: Adjust EU per SS according to
 HAS_ONE_EU_PER_FUSE_BIT()

If we're treating each bit in the EU fuse register as a single EU
instead of a pair of EUs, then that also cuts the number of potential
EUs per subslice in half.

Fixes: 5ac342ef84d7 ("drm/i915/pvc: Add SSEU changes")
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220610230801.459577-1-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 7ef75f0d9c9e0..c6d3050604c89 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -229,7 +229,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
 	 */
 	intel_sseu_set_info(sseu, 1,
 			    32 * max(num_geometry_regs, num_compute_regs),
-			    16);
+			    HAS_ONE_EU_PER_FUSE_BIT(gt->i915) ? 8 : 16);
 	sseu->has_xehp_dss = 1;
 
 	xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask,
-- 
GitLab


From 72aeb6ee0c78fafc476c02d1b19b5b38defcb57f Mon Sep 17 00:00:00 2001
From: Yang Wang <KevinYang.Wang@amd.com>
Date: Thu, 9 Jun 2022 19:20:47 +0800
Subject: [PATCH 0560/1731] drm/amd/pm: fix driver reload SMC firmware fail
 issue for smu13

issue calltrace:
[  402.773695] [drm] failed to load ucode SMC(0x2C)
[  402.773754] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0x0)
[  402.773762] [drm:psp_load_smu_fw [amdgpu]] *ERROR* PSP load smu failed!
[  402.966758] [drm:psp_v13_0_ring_destroy [amdgpu]] *ERROR* Fail to stop psp ring
[  402.966949] [drm:psp_hw_init [amdgpu]] *ERROR* PSP firmware loading failed
[  402.967116] [drm:amdgpu_device_fw_loading [amdgpu]] *ERROR* hw_init of IP block <psp> failed -22
[  402.967252] amdgpu 0000:03:00.0: amdgpu: amdgpu_device_ip_init failed
[  402.967255] amdgpu 0000:03:00.0: amdgpu: Fatal error during GPU init

if not reset mp1 state during kernel driver unload, it will cause psp
load pmfw fail at the second time.

add PPSMC_MSG_PrepareMp1ForUnload support for smu_v13_0_0/smu_v13_0_7

Signed-off-by: Yang Wang <KevinYang.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c            | 7 +++++++
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 2 ++
 3 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index f57710790b8cd..3d269d1c27494 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -66,6 +66,7 @@ static int smu_set_fan_control_mode(void *handle, u32 value);
 static int smu_set_power_limit(void *handle, uint32_t limit);
 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed);
 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
+static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state);
 
 static int smu_sys_get_pp_feature_mask(void *handle,
 				       char *buf)
@@ -1414,6 +1415,12 @@ static int smu_disable_dpms(struct smu_context *smu)
 	switch (adev->ip_versions[MP1_HWIP][0]) {
 	case IP_VERSION(13, 0, 0):
 	case IP_VERSION(13, 0, 7):
+		ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD);
+		if (ret) {
+			dev_err(adev->dev, "Fail set mp1 state to UNLOAD!\n");
+			return ret;
+		}
+
 		return 0;
 	default:
 		break;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 26fb72a588e78..fda89e309b079 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -118,6 +118,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] =
 	MSG_MAP(GetPptLimit,			PPSMC_MSG_GetPptLimit,                 0),
 	MSG_MAP(NotifyPowerSource,		PPSMC_MSG_NotifyPowerSource,           0),
 	MSG_MAP(Mode1Reset,			PPSMC_MSG_Mode1Reset,                  0),
+	MSG_MAP(PrepareMp1ForUnload,		PPSMC_MSG_PrepareMp1ForUnload,         0),
 };
 
 static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {
@@ -1662,6 +1663,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
 	.baco_exit = smu_v13_0_baco_exit,
 	.mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported,
 	.mode1_reset = smu_v13_0_mode1_reset,
+	.set_mp1_state = smu_cmn_set_mp1_state,
 };
 
 void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index a92ab32660919..185058637f7d5 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -116,6 +116,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] =
 	MSG_MAP(DramLogSetDramSize,		PPSMC_MSG_DramLogSetDramSize,          0),
 	MSG_MAP(AllowGfxOff,			PPSMC_MSG_AllowGfxOff,                 0),
 	MSG_MAP(DisallowGfxOff,			PPSMC_MSG_DisallowGfxOff,              0),
+	MSG_MAP(PrepareMp1ForUnload,		PPSMC_MSG_PrepareMp1ForUnload,         0),
 };
 
 static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {
@@ -1647,6 +1648,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
 	.baco_set_state = smu_v13_0_7_baco_set_state,
 	.baco_enter = smu_v13_0_7_baco_enter,
 	.baco_exit = smu_v13_0_baco_exit,
+	.set_mp1_state = smu_cmn_set_mp1_state,
 };
 
 void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
-- 
GitLab


From 438eac25d033a1701d839bad16c6ad78f683a293 Mon Sep 17 00:00:00 2001
From: Yifan Zhang <yifan1.zhang@amd.com>
Date: Wed, 8 Jun 2022 18:29:33 +0800
Subject: [PATCH 0561/1731] drm/amdgpu/discovery: enable vcn/jpeg v4_0_2

Enable vcn/jpeg 4_0_2.

Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 1369a1b74929a..11bbd76c581c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1897,6 +1897,7 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
 			amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 			break;
 		case IP_VERSION(4, 0, 0):
+		case IP_VERSION(4, 0, 2):
 		case IP_VERSION(4, 0, 4):
 			amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block);
 			amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block);
-- 
GitLab


From f2a5002541d0698509d4f3adfbfcc55a9c1e2dd1 Mon Sep 17 00:00:00 2001
From: Yifan Zhang <yifan1.zhang@amd.com>
Date: Thu, 9 Jun 2022 17:03:48 +0800
Subject: [PATCH 0562/1731] drm/amd: disable GPA mode in backdoor load

GPA mode should be disabled in direct load.

Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 05359df6c3548..942d41a65f2f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4563,6 +4563,9 @@ static int gfx_v11_0_hw_init(void *handle)
 				if (adev->gfx.imu.funcs->start_imu)
 					adev->gfx.imu.funcs->start_imu(adev);
 			}
+
+			/* disable gpa mode in backdoor loading */
+			gfx_v11_0_disable_gpa_mode(adev);
 		}
 	}
 
-- 
GitLab


From 5089c4a8ebea3c3ad9eedf038dad7098ebc06131 Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Tue, 7 Jun 2022 22:43:42 -0400
Subject: [PATCH 0563/1731] drm/amd/display: ignore modifiers when checking for
 format support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

[Why&How]
There are cases where swizzle modes are set but modifiers arent. For
such a userspace, we need not check modifiers while checking
compatibilty in the drm hook for checking plane format.

Ignore checking modifiers but check the DCN generation for the
supported swizzle mode.

v2: squash in unused variable removal (Alex)

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 53 ++++++++++++++++---
 1 file changed, 46 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e668bb1560da7..4a90ee111aec9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4936,8 +4936,7 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane,
 {
 	struct amdgpu_device *adev = drm_to_adev(plane->dev);
 	const struct drm_format_info *info = drm_format_info(format);
-	int i;
-
+	struct hw_asic_id asic_id = adev->dm.dc->ctx->asic_id;
 	enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3;
 
 	if (!info)
@@ -4953,13 +4952,53 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane,
 		return true;
 	}
 
-	/* Check that the modifier is on the list of the plane's supported modifiers. */
-	for (i = 0; i < plane->modifier_count; i++) {
-		if (modifier == plane->modifiers[i])
+	/* check if swizzle mode is supported by this version of DCN */
+	switch (asic_id.chip_family) {
+		case FAMILY_SI:
+		case FAMILY_CI:
+		case FAMILY_KV:
+		case FAMILY_CZ:
+		case FAMILY_VI:
+			/* asics before AI does not have modifier support */
+			return false;
+			break;
+		case FAMILY_AI:
+		case FAMILY_RV:
+		case FAMILY_NV:
+		case FAMILY_VGH:
+		case FAMILY_YELLOW_CARP:
+		case AMDGPU_FAMILY_GC_10_3_6:
+		case AMDGPU_FAMILY_GC_10_3_7:
+			switch (AMD_FMT_MOD_GET(TILE, modifier)) {
+				case AMD_FMT_MOD_TILE_GFX9_64K_R_X:
+				case AMD_FMT_MOD_TILE_GFX9_64K_D_X:
+				case AMD_FMT_MOD_TILE_GFX9_64K_S_X:
+				case AMD_FMT_MOD_TILE_GFX9_64K_D:
+					return true;
+					break;
+				default:
+					return false;
+					break;
+			}
+			break;
+		case AMDGPU_FAMILY_GC_11_0_0:
+			switch (AMD_FMT_MOD_GET(TILE, modifier)) {
+				case AMD_FMT_MOD_TILE_GFX11_256K_R_X:
+				case AMD_FMT_MOD_TILE_GFX9_64K_R_X:
+				case AMD_FMT_MOD_TILE_GFX9_64K_D_X:
+				case AMD_FMT_MOD_TILE_GFX9_64K_S_X:
+				case AMD_FMT_MOD_TILE_GFX9_64K_D:
+					return true;
+					break;
+				default:
+					return false;
+					break;
+			}
+			break;
+		default:
+			ASSERT(0); /* Unknown asic */
 			break;
 	}
-	if (i == plane->modifier_count)
-		return false;
 
 	/*
 	 * For D swizzle the canonical modifier depends on the bpp, so check
-- 
GitLab


From d52ea3dc65a9d504afa7a03ff24e17866670bdac Mon Sep 17 00:00:00 2001
From: Tim Huang <tim.huang@amd.com>
Date: Wed, 1 Jun 2022 18:12:08 +0800
Subject: [PATCH 0564/1731] drm/amdgpu/pm: correct the firmware flag address
 for SMU IP v13.0.4

For SMU IP v13.0.4, the smnMP1_FIRMWARE_FLAGS address is different,
we need this to correct the reading address.

Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h   |  1 +
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 12 ++++++++++--
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index e3454a876cacd..43de0a8d4bd94 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -43,6 +43,7 @@
 
 /* address block */
 #define smnMP1_FIRMWARE_FLAGS		0x3010024
+#define smnMP1_V13_0_4_FIRMWARE_FLAGS	0x3010028
 #define smnMP0_FW_INTF			0x30101c0
 #define smnMP1_PUB_CTRL			0x3010b14
 
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index f9c36d2944481..fba0b87d01fbe 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -273,8 +273,16 @@ int smu_v13_0_check_fw_status(struct smu_context *smu)
 	struct amdgpu_device *adev = smu->adev;
 	uint32_t mp1_fw_flags;
 
-	mp1_fw_flags = RREG32_PCIE(MP1_Public |
-				   (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
+	switch (adev->ip_versions[MP1_HWIP][0]) {
+	case IP_VERSION(13, 0, 4):
+		mp1_fw_flags = RREG32_PCIE(MP1_Public |
+					   (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff));
+		break;
+	default:
+		mp1_fw_flags = RREG32_PCIE(MP1_Public |
+					   (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
+		break;
+	}
 
 	if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 	    MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
-- 
GitLab


From 526e6ca5d1d5fd22c79033cf5a8eb07d98a11274 Mon Sep 17 00:00:00 2001
From: Tim Huang <tim.huang@amd.com>
Date: Mon, 6 Jun 2022 16:27:06 +0800
Subject: [PATCH 0565/1731] drm/amdgpu/pm: remove the repeated EnableGfxImu
 message sending

The EnableGfxImu message will be issued in the set_gfx_power_up_by_imu.

Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c    | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
index 196670345552b..82d3718d83244 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -219,15 +219,10 @@ static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en)
 {
 	struct amdgpu_device *adev = smu->adev;
 	int ret = 0;
-	/* SMU fw need this message to trigger IMU to complete the initialization */
-	if (en)
-		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxImu, NULL);
-	else {
-		if (!adev->in_s0ix)
-			ret = smu_cmn_send_smc_msg(smu,
-						   SMU_MSG_PrepareMp1ForUnload,
-						   NULL);
-	}
+
+	if (!en && !adev->in_s0ix)
+		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
+
 	return ret;
 }
 
-- 
GitLab


From ea937ad6e925994b94d17555e4c2f2f9a99234e1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <mdaenzer@redhat.com>
Date: Fri, 10 Jun 2022 15:54:26 +0200
Subject: [PATCH 0566/1731] drm/amdgpu: Fix GTT size reporting in amdgpu_ioctl
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The commit below changed the TTM manager size unit from pages to
bytes, but failed to adjust the corresponding calculations in
amdgpu_ioctl.

Fixes: dfa714b88eb0 ("drm/amdgpu: remove GTT accounting v2")
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1930
Bug: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6642
Tested-by: Martin Roukala <martin.roukala@mupuf.org>
Tested-by: Mike Lothian <mike@fireburn.co.uk>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <mdaenzer@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 801f6fa692e98..6de63ea6687eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -642,7 +642,6 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 			    atomic64_read(&adev->visible_pin_size),
 			    vram_gtt.vram_size);
 		vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
-		vram_gtt.gtt_size *= PAGE_SIZE;
 		vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 		return copy_to_user(out, &vram_gtt,
 				    min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
@@ -675,7 +674,6 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 			mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 
 		mem.gtt.total_heap_size = gtt_man->size;
-		mem.gtt.total_heap_size *= PAGE_SIZE;
 		mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 			atomic64_read(&adev->gart_pin_size);
 		mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
-- 
GitLab


From 1f474c8742fd53a048cc8cc4b20e20b2614397eb Mon Sep 17 00:00:00 2001
From: Leo Li <sunpeng.li@amd.com>
Date: Wed, 8 Jun 2022 12:17:44 -0400
Subject: [PATCH 0567/1731] drm/amd/display: Use pre-allocated temp struct for
 bounding box update

[Why]

There is a theoretical problem in prior patches for reducing the stack
size of *update_bw_bounding_box() functions.

By modifying the soc.clock_limits[n] struct directly, this can cause
unintended behavior as the for loop attempts to swap rows in
clock_limits[n]. A temporary struct is still required to make sure we
stay functinoally equivalent.

[How]

Add a temporary clock_limits table to the SOC struct, and use it when
swapping rows.

Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c  | 33 +++++-----
 .../amd/display/dc/dml/dcn301/dcn301_fpu.c    | 36 ++++++-----
 .../drm/amd/display/dc/dml/dcn31/dcn31_fpu.c  | 64 +++++++++++--------
 .../amd/display/dc/dml/display_mode_structs.h |  5 ++
 4 files changed, 82 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index c2fec0d85da42..e247b2270b1db 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -2015,9 +2015,8 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
 
 	ASSERT(clk_table->num_entries);
 	/* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */
-	for (i = 0; i < dcn2_1_soc.num_states + 1; i++) {
-		dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i];
-	}
+	memcpy(&dcn2_1_soc._clock_tmp, &dcn2_1_soc.clock_limits,
+	       sizeof(dcn2_1_soc.clock_limits));
 
 	for (i = 0; i < clk_table->num_entries; i++) {
 		/* loop backwards*/
@@ -2032,22 +2031,26 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
 		if (i == 1)
 			k++;
 
-		dcn2_1_soc.clock_limits[k].state = k;
-		dcn2_1_soc.clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
-		dcn2_1_soc.clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
-		dcn2_1_soc.clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
-		dcn2_1_soc.clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
+		dcn2_1_soc._clock_tmp[k].state = k;
+		dcn2_1_soc._clock_tmp[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+		dcn2_1_soc._clock_tmp[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+		dcn2_1_soc._clock_tmp[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
+		dcn2_1_soc._clock_tmp[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
 
-		dcn2_1_soc.clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
-		dcn2_1_soc.clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
-		dcn2_1_soc.clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
-		dcn2_1_soc.clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
-		dcn2_1_soc.clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
-		dcn2_1_soc.clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
-		dcn2_1_soc.clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+		dcn2_1_soc._clock_tmp[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
+		dcn2_1_soc._clock_tmp[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
+		dcn2_1_soc._clock_tmp[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
+		dcn2_1_soc._clock_tmp[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
+		dcn2_1_soc._clock_tmp[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
+		dcn2_1_soc._clock_tmp[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
+		dcn2_1_soc._clock_tmp[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
 
 		k++;
 	}
+
+	memcpy(&dcn2_1_soc.clock_limits, &dcn2_1_soc._clock_tmp,
+	       sizeof(dcn2_1_soc.clock_limits));
+
 	if (clk_table->num_entries) {
 		dcn2_1_soc.num_states = clk_table->num_entries + 1;
 		/* fill in min DF PState */
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
index 62cf283d9f410..e4863f0bf0f61 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
@@ -254,6 +254,9 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
 
 	dc_assert_fp_enabled();
 
+	memcpy(&dcn3_01_soc._clock_tmp, &dcn3_01_soc.clock_limits,
+	       sizeof(dcn3_01_soc.clock_limits));
+
 	/* Default clock levels are used for diags, which may lead to overclocking. */
 	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
 		dcn3_01_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
@@ -270,29 +273,32 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
 				}
 			}
 
-			dcn3_01_soc.clock_limits[i].state = i;
-			dcn3_01_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
-			dcn3_01_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
-			dcn3_01_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
-			dcn3_01_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
-
-			dcn3_01_soc.clock_limits[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
-			dcn3_01_soc.clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
-			dcn3_01_soc.clock_limits[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
-			dcn3_01_soc.clock_limits[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
-			dcn3_01_soc.clock_limits[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
-			dcn3_01_soc.clock_limits[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
-			dcn3_01_soc.clock_limits[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+			dcn3_01_soc._clock_tmp[i].state = i;
+			dcn3_01_soc._clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+			dcn3_01_soc._clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+			dcn3_01_soc._clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
+			dcn3_01_soc._clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
+
+			dcn3_01_soc._clock_tmp[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
+			dcn3_01_soc._clock_tmp[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
+			dcn3_01_soc._clock_tmp[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
+			dcn3_01_soc._clock_tmp[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
+			dcn3_01_soc._clock_tmp[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
+			dcn3_01_soc._clock_tmp[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
+			dcn3_01_soc._clock_tmp[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
 		}
 
 		if (clk_table->num_entries) {
 			dcn3_01_soc.num_states = clk_table->num_entries;
 			/* duplicate last level */
-			dcn3_01_soc.clock_limits[dcn3_01_soc.num_states] = dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1];
-			dcn3_01_soc.clock_limits[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states;
+			dcn3_01_soc._clock_tmp[dcn3_01_soc.num_states] = dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1];
+			dcn3_01_soc._clock_tmp[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states;
 		}
 	}
 
+	memcpy(&dcn3_01_soc.clock_limits, &dcn3_01_soc._clock_tmp,
+	       sizeof(dcn3_01_soc.clock_limits));
+
 	dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
 	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
index 6da7029232269..7be3476989ce9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
@@ -580,6 +580,9 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
 
 	dc_assert_fp_enabled();
 
+	memcpy(&dcn3_1_soc._clock_tmp, &dcn3_1_soc.clock_limits,
+	       sizeof(dcn3_1_soc.clock_limits));
+
 	// Default clock levels are used for diags, which may lead to overclocking.
 	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
 		int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
@@ -607,32 +610,35 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
 				}
 			}
 
-			dcn3_1_soc.clock_limits[i].state = i;
+			dcn3_1_soc._clock_tmp[i].state = i;
 
 			/* Clocks dependent on voltage level. */
-			dcn3_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
-			dcn3_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
-			dcn3_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
-			dcn3_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
+			dcn3_1_soc._clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+			dcn3_1_soc._clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+			dcn3_1_soc._clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
+			dcn3_1_soc._clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
 
 			/* Clocks independent of voltage level. */
-			dcn3_1_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
+			dcn3_1_soc._clock_tmp[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
 				dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
 
-			dcn3_1_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
+			dcn3_1_soc._clock_tmp[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
 				dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
 
-			dcn3_1_soc.clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
-			dcn3_1_soc.clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
-			dcn3_1_soc.clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
-			dcn3_1_soc.clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
-			dcn3_1_soc.clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+			dcn3_1_soc._clock_tmp[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
+			dcn3_1_soc._clock_tmp[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
+			dcn3_1_soc._clock_tmp[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
+			dcn3_1_soc._clock_tmp[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
+			dcn3_1_soc._clock_tmp[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
 		}
 		if (clk_table->num_entries) {
 			dcn3_1_soc.num_states = clk_table->num_entries;
 		}
 	}
 
+	memcpy(&dcn3_1_soc.clock_limits, &dcn3_1_soc._clock_tmp,
+	       sizeof(dcn3_1_soc.clock_limits));
+
 	dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
 	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
 
@@ -705,6 +711,9 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
 
 	dc_assert_fp_enabled();
 
+	memcpy(&dcn3_16_soc._clock_tmp, &dcn3_16_soc.clock_limits,
+	       sizeof(dcn3_16_soc.clock_limits));
+
 	// Default clock levels are used for diags, which may lead to overclocking.
 	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
 
@@ -736,37 +745,40 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
 				closest_clk_lvl = dcn3_16_soc.num_states - 1;
 			}
 
-			dcn3_16_soc.clock_limits[i].state = i;
+			dcn3_16_soc._clock_tmp[i].state = i;
 
 			/* Clocks dependent on voltage level. */
-			dcn3_16_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+			dcn3_16_soc._clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
 			if (clk_table->num_entries == 1 &&
-				dcn3_16_soc.clock_limits[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
+			    dcn3_16_soc._clock_tmp[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
 				/*SMU fix not released yet*/
-				dcn3_16_soc.clock_limits[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
+				dcn3_16_soc._clock_tmp[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
 			}
-			dcn3_16_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
-			dcn3_16_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
-			dcn3_16_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
+			dcn3_16_soc._clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+			dcn3_16_soc._clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
+			dcn3_16_soc._clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
 
 			/* Clocks independent of voltage level. */
-			dcn3_16_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
+			dcn3_16_soc._clock_tmp[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
 				dcn3_16_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
 
-			dcn3_16_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
+			dcn3_16_soc._clock_tmp[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
 				dcn3_16_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
 
-			dcn3_16_soc.clock_limits[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
-			dcn3_16_soc.clock_limits[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
-			dcn3_16_soc.clock_limits[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
-			dcn3_16_soc.clock_limits[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
-			dcn3_16_soc.clock_limits[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+			dcn3_16_soc._clock_tmp[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
+			dcn3_16_soc._clock_tmp[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
+			dcn3_16_soc._clock_tmp[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
+			dcn3_16_soc._clock_tmp[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
+			dcn3_16_soc._clock_tmp[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
 		}
 		if (clk_table->num_entries) {
 			dcn3_16_soc.num_states = clk_table->num_entries;
 		}
 	}
 
+	memcpy(&dcn3_16_soc.clock_limits, &dcn3_16_soc._clock_tmp,
+	       sizeof(dcn3_16_soc.clock_limits));
+
 	if (max_dispclk_mhz) {
 		dcn3_16_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
 		dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 74afa10e70f89..2bdf608467625 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -161,6 +161,11 @@ struct _vcs_dpi_voltage_scaling_st {
 
 struct _vcs_dpi_soc_bounding_box_st {
 	struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
+	/*
+	 * This is a temporary stash for updating @clock_limits with the PMFW
+	 * clock table. Do not use outside of *update_bw_boudning_box functions.
+	 */
+	struct _vcs_dpi_voltage_scaling_st _clock_tmp[DC__VOLTAGE_STATES];
 	unsigned int num_states;
 	double sr_exit_time_us;
 	double sr_enter_plus_exit_time_us;
-- 
GitLab


From d6aa8424bcac64b2608452589c9a09984251c01c Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Fri, 10 Jun 2022 13:13:31 -0400
Subject: [PATCH 0568/1731] drm/amd/display: dml: move some variables to heap

[Why&How]
To reduce stack usage, move some variables into heap in the DML function
dml32_ModeSupportAndSystemConfigurationFull()

Fixes: dda4fb85e433 ("drm/amd/display: DML changes for DCN32/321")
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../display/dc/dml/dcn32/display_mode_vba_32.c  | 17 +++++++----------
 .../drm/amd/display/dc/dml/display_mode_vba.h   |  3 +++
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 5828e60f291d4..b9f5bfa67791b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -1675,9 +1675,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 	bool FullFrameMALLPStateMethod;
 	bool SubViewportMALLPStateMethod;
 	bool PhantomPipeMALLPStateMethod;
-	double MaxTotalVActiveRDBandwidth;
-	double DSTYAfterScaler[DC__NUM_DPP__MAX];
-	double DSTXAfterScaler[DC__NUM_DPP__MAX];
 	unsigned int MaximumMPCCombine;
 
 #ifdef __DML_VBA_DEBUG__
@@ -3095,10 +3092,10 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 	}
 
 	//Vertical Active BW support check
-	MaxTotalVActiveRDBandwidth = 0;
+	v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaxTotalVActiveRDBandwidth = 0;
 
 	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
-		MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + mode_lib->vba.ReadBandwidthLuma[k]
+		v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaxTotalVActiveRDBandwidth += mode_lib->vba.ReadBandwidthLuma[k]
 				+ mode_lib->vba.ReadBandwidthChroma[k];
 	}
 
@@ -3115,7 +3112,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 					* mode_lib->vba.DRAMChannelWidth
 					* (i < 2 ? mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE : mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation) / 100);
 
-			if (MaxTotalVActiveRDBandwidth
+			if (v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaxTotalVActiveRDBandwidth
 					<= mode_lib->vba.MaxTotalVerticalActiveAvailableBandwidth[i][j]) {
 				mode_lib->vba.TotalVerticalActiveBandwidthSupport[i][j] = true;
 			} else {
@@ -3281,8 +3278,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 							mode_lib->vba.SwathHeightCThisState[k], mode_lib->vba.TWait,
 
 							/* Output */
-							&DSTXAfterScaler[k],
-							&DSTYAfterScaler[k],
+							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler[k],
+							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTYAfterScaler[k],
 							&mode_lib->vba.LineTimesForPrefetch[k],
 							&mode_lib->vba.PrefetchBW[k],
 							&mode_lib->vba.LinesForMetaPTE[k],
@@ -3579,8 +3576,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 						mode_lib->vba.NoOfDPPThisState,
 						mode_lib->vba.BytePerPixelInDETY,
 						mode_lib->vba.BytePerPixelInDETC,
-						DSTXAfterScaler,
-						DSTYAfterScaler,
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler,
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTYAfterScaler,
 						mode_lib->vba.WritebackEnable,
 						mode_lib->vba.WritebackPixelFormat,
 						mode_lib->vba.WritebackDestinationWidth,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 43e3270805521..9ad49ad38814f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -204,6 +204,9 @@ struct dml32_ModeSupportAndSystemConfigurationFull {
 	SOCParametersList mSOCParameters;
 	unsigned int MaximumSwathWidthSupportLuma;
 	unsigned int MaximumSwathWidthSupportChroma;
+	double DSTYAfterScaler[DC__NUM_DPP__MAX];
+	double DSTXAfterScaler[DC__NUM_DPP__MAX];
+	double MaxTotalVActiveRDBandwidth;
 };
 
 struct dummy_vars {
-- 
GitLab


From d11737f26ffeae88350b835caa37c7449da22550 Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Mon, 6 Jun 2022 11:21:07 +0800
Subject: [PATCH 0569/1731] drm/amd/pm: enable UCLK DS feature for SMU 13.0.0

The feature is ready with latest PMFW and IFWI.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index fda89e309b079..495713e4ebd43 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -306,6 +306,8 @@ smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu,
 
 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT);
 
+	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_UCLK_BIT);
+
 	return 0;
 }
 
-- 
GitLab


From 272308add589bd46ddb5899685e25fc9f6a58b1e Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Tue, 7 Jun 2022 14:40:24 +0800
Subject: [PATCH 0570/1731] drm/amd/pm: enable MACO support for SMU 13.0.0

Enable BAMACO reset support for SMU 13.0.0.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c    |  3 +-
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  |  3 ++
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  | 52 +------------------
 3 files changed, 7 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index fba0b87d01fbe..f18f9605e586e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2271,7 +2271,8 @@ int smu_v13_0_baco_set_state(struct smu_context *smu,
 	if (state == SMU_BACO_STATE_ENTER) {
 		ret = smu_cmn_send_smc_msg_with_param(smu,
 						      SMU_MSG_EnterBaco,
-						      0,
+						      smu_baco->maco_support ?
+						      BACO_SEQ_BAMACO : BACO_SEQ_BACO,
 						      NULL);
 	} else {
 		ret = smu_cmn_send_smc_msg(smu,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 495713e4ebd43..6fb2b072a730e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -325,6 +325,9 @@ static int smu_v13_0_0_check_powerplay_table(struct smu_context *smu)
 	    powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO)
 		smu_baco->platform_support = true;
 
+	if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO)
+		smu_baco->maco_support = true;
+
 	table_context->thermal_controller_type =
 		powerplay_table->thermal_controller_type;
 
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 185058637f7d5..193222fdd1c46 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1543,54 +1543,6 @@ static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *inp
 	return ret;
 }
 
-static int smu_v13_0_7_baco_set_state(struct smu_context *smu,
-			     enum smu_baco_state state)
-{
-	struct smu_baco_context *smu_baco = &smu->smu_baco;
-	struct amdgpu_device *adev = smu->adev;
-	bool is_maco_support = smu_baco->maco_support;
-	int ret;
-
-	if (smu_v13_0_baco_get_state(smu) == state)
-		return 0;
-
-	if (state == SMU_BACO_STATE_ENTER) {
-		ret = smu_cmn_send_smc_msg_with_param(smu,
-						      SMU_MSG_EnterBaco,
-						      (is_maco_support ? 2 : 0),
-						      NULL);
-	} else {
-		ret = smu_cmn_send_smc_msg(smu,
-					   SMU_MSG_ExitBaco,
-					   NULL);
-		if (ret)
-			return ret;
-
-		/* clear vbios scratch 6 and 7 for coming asic reinit */
-		WREG32(adev->bios_scratch_reg_offset + 6, 0);
-		WREG32(adev->bios_scratch_reg_offset + 7, 0);
-	}
-
-	if (!ret)
-		smu_baco->state = state;
-
-	return ret;
-}
-
-static int smu_v13_0_7_baco_enter(struct smu_context *smu)
-{
-	int ret = 0;
-
-	ret = smu_v13_0_7_baco_set_state(smu,
-				       SMU_BACO_STATE_ENTER);
-	if (ret)
-		return ret;
-
-	msleep(10);
-
-	return ret;
-}
-
 static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
 	.get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask,
 	.set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,
@@ -1645,8 +1597,8 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
 	.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
 	.baco_is_support = smu_v13_0_baco_is_support,
 	.baco_get_state = smu_v13_0_baco_get_state,
-	.baco_set_state = smu_v13_0_7_baco_set_state,
-	.baco_enter = smu_v13_0_7_baco_enter,
+	.baco_set_state = smu_v13_0_baco_set_state,
+	.baco_enter = smu_v13_0_baco_enter,
 	.baco_exit = smu_v13_0_baco_exit,
 	.set_mp1_state = smu_cmn_set_mp1_state,
 };
-- 
GitLab


From 1a65327a84db5b9081a51ccb1c562083f59bfcec Mon Sep 17 00:00:00 2001
From: Chengming Gui <Jack.Gui@amd.com>
Date: Mon, 13 Jun 2022 14:52:54 +0800
Subject: [PATCH 0571/1731] Revert "drm/amdgpu/gmc11: enable AGP aperture"

This reverts commit 2cfe34e18970d26bff73c63f16c76dae22138d19.
Enable AGP aperture cause SDMA page fault for gfx11.0.2,
so temp disable AGP aperture until SDMA FW resolved this.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Gui <Jack.Gui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c  | 7 +++----
 drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c    | 1 -
 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c   | 6 +++---
 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c | 6 +++---
 4 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
index f99d7641bb217..5eccaa2c7ca0e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
@@ -154,11 +154,10 @@ static void gfxhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev)
 {
 	uint64_t value;
 
-	/* Program the AGP BAR */
+	/* Disable AGP. */
 	WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0);
-	WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
-	WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
-
+	WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, 0);
+	WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, 0x00FFFFFF);
 
 	/* Program the system aperture low logical page number. */
 	WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 454a25cc00461..9c225553f5b53 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -611,7 +611,6 @@ static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev,
 
 	amdgpu_gmc_vram_location(adev, &adev->gmc, base);
 	amdgpu_gmc_gart_location(adev, mc);
-	amdgpu_gmc_agp_location(adev, mc);
 
 	/* base offset of vram pages */
 	adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
index 4926fa82c1c4d..bc11b2de37aeb 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
@@ -169,10 +169,10 @@ static void mmhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev)
 	uint64_t value;
 	uint32_t tmp;
 
-	/* Program the AGP BAR */
+	/* Disable AGP. */
 	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
-	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
-	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0);
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FFFFFF);
 
 	if (!amdgpu_sriov_vf(adev)) {
 		/*
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
index 5e5b884d83573..770be0a8f7ce7 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
@@ -162,10 +162,10 @@ static void mmhub_v3_0_2_init_system_aperture_regs(struct amdgpu_device *adev)
 	uint64_t value;
 	uint32_t tmp;
 
-	/* Program the AGP BAR */
+	/* Disable AGP. */
 	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
-	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
-	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0);
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FFFFFF);
 
 	if (!amdgpu_sriov_vf(adev)) {
 		/*
-- 
GitLab


From 9731dd4cadc53251ef80b3655c8d841fed52fa3d Mon Sep 17 00:00:00 2001
From: Daniel Phillips <Daniel.Phillips@amd.com>
Date: Mon, 30 May 2022 11:21:22 -0400
Subject: [PATCH 0572/1731] drm/amdkfd: Add available memory ioctl

Add a new KFD ioctl to return the largest possible memory size that
can be allocated as a buffer object using
kfd_ioctl_alloc_memory_of_gpu. It attempts to use exactly the same
accept/reject criteria as that function so that allocating a new
buffer object of the size returned by this new ioctl is guaranteed to
succeed, barring races with other allocating tasks.

This IOCTL will be used by libhsakmt:
https://www.mail-archive.com/amd-gfx@lists.freedesktop.org/msg75743.html

Signed-off-by: Daniel Phillips <Daniel.Phillips@amd.com>
Signed-off-by: David Yat Sin <David.YatSin@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h    |  1 +
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 38 +++++++++++++++++--
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c      | 34 +++++++++++++++++
 include/uapi/linux/kfd_ioctl.h                | 14 ++++++-
 4 files changed, 81 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index ffb2b7d9b9a53..648c031942e92 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -268,6 +268,7 @@ int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
 void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
 					void *drm_priv);
 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv);
+size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev);
 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 		struct amdgpu_device *adev, uint64_t va, uint64_t size,
 		void *drm_priv, struct kgd_mem **mem,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index f386b0d256d25..8805bd1eed372 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -38,6 +38,12 @@
  */
 #define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
 
+/*
+ * Align VRAM allocations to 2MB to avoid fragmentation caused by 4K allocations in the tail 2MB
+ * BO chunk
+ */
+#define VRAM_ALLOCATION_ALIGN (1 << 21)
+
 /* Impose limit on how much memory KFD can use */
 static struct {
 	uint64_t max_system_mem_limit;
@@ -108,7 +114,7 @@ void amdgpu_amdkfd_reserve_system_mem(uint64_t size)
  * compromise that should work in most cases without reserving too
  * much memory for page tables unnecessarily (factor 16K, >> 14).
  */
-#define ESTIMATE_PT_SIZE(mem_size) ((mem_size) >> 14)
+#define ESTIMATE_PT_SIZE(mem_size) max(((mem_size) >> 14), AMDGPU_VM_RESERVED_VRAM)
 
 static size_t amdgpu_amdkfd_acc_size(uint64_t size)
 {
@@ -148,7 +154,13 @@ static int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
 	} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
 		system_mem_needed = acc_size;
 		ttm_mem_needed = acc_size;
-		vram_needed = size;
+
+		/*
+		 * Conservatively round up the allocation requirement to 2 MB
+		 * to avoid fragmentation caused by 4K allocations in the tail
+		 * 2M BO chunk.
+		 */
+		vram_needed = ALIGN(size, VRAM_ALLOCATION_ALIGN);
 	} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
 		system_mem_needed = acc_size + size;
 		ttm_mem_needed = acc_size;
@@ -173,7 +185,9 @@ static int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
 	    (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
 	     kfd_mem_limit.max_ttm_mem_limit) ||
 	    (adev->kfd.vram_used + vram_needed >
-	     adev->gmc.real_vram_size - reserved_for_pt)) {
+	     adev->gmc.real_vram_size -
+	     atomic64_read(&adev->vram_pin_size) -
+	     reserved_for_pt)) {
 		ret = -ENOMEM;
 		goto release;
 	}
@@ -205,7 +219,7 @@ static void unreserve_mem_limit(struct amdgpu_device *adev,
 	} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
 		kfd_mem_limit.system_mem_used -= acc_size;
 		kfd_mem_limit.ttm_mem_used -= acc_size;
-		adev->kfd.vram_used -= size;
+		adev->kfd.vram_used -= ALIGN(size, VRAM_ALLOCATION_ALIGN);
 	} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
 		kfd_mem_limit.system_mem_used -= (acc_size + size);
 		kfd_mem_limit.ttm_mem_used -= acc_size;
@@ -1633,6 +1647,22 @@ out_unlock:
 	return ret;
 }
 
+size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev)
+{
+	uint64_t reserved_for_pt =
+		ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
+	size_t available;
+
+	spin_lock(&kfd_mem_limit.mem_limit_lock);
+	available = adev->gmc.real_vram_size
+		- adev->kfd.vram_used
+		- atomic64_read(&adev->vram_pin_size)
+		- reserved_for_pt;
+	spin_unlock(&kfd_mem_limit.mem_limit_lock);
+
+	return ALIGN_DOWN(available, VRAM_ALLOCATION_ALIGN);
+}
+
 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 		struct amdgpu_device *adev, uint64_t va, uint64_t size,
 		void *drm_priv, struct kgd_mem **mem,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 1c7016958d6d9..3bcf9bf29acbb 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -65,6 +65,25 @@ static int kfd_char_dev_major = -1;
 static struct class *kfd_class;
 struct device *kfd_device;
 
+static inline struct kfd_process_device *kfd_lock_pdd_by_id(struct kfd_process *p, __u32 gpu_id)
+{
+	struct kfd_process_device *pdd;
+
+	mutex_lock(&p->mutex);
+	pdd = kfd_process_device_data_by_id(p, gpu_id);
+
+	if (pdd)
+		return pdd;
+
+	mutex_unlock(&p->mutex);
+	return NULL;
+}
+
+static inline void kfd_unlock_pdd(struct kfd_process_device *pdd)
+{
+	mutex_unlock(&pdd->process->mutex);
+}
+
 int kfd_chardev_init(void)
 {
 	int err = 0;
@@ -958,6 +977,19 @@ bool kfd_dev_is_large_bar(struct kfd_dev *dev)
 	return false;
 }
 
+static int kfd_ioctl_get_available_memory(struct file *filep,
+					  struct kfd_process *p, void *data)
+{
+	struct kfd_ioctl_get_available_memory_args *args = data;
+	struct kfd_process_device *pdd = kfd_lock_pdd_by_id(p, args->gpu_id);
+
+	if (!pdd)
+		return -EINVAL;
+	args->available = amdgpu_amdkfd_get_available_memory(pdd->dev->adev);
+	kfd_unlock_pdd(pdd);
+	return 0;
+}
+
 static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,
 					struct kfd_process *p, void *data)
 {
@@ -2648,6 +2680,8 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_CRIU_OP,
 			kfd_ioctl_criu, KFD_IOC_FLAG_CHECKPOINT_RESTORE),
 
+	AMDKFD_IOCTL_DEF(AMDKFD_IOC_AVAILABLE_MEMORY,
+			kfd_ioctl_get_available_memory, 0),
 };
 
 #define AMDKFD_CORE_IOCTL_COUNT	ARRAY_SIZE(amdkfd_ioctls)
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index 42975e940758d..231eb010b823e 100644
--- a/include/uapi/linux/kfd_ioctl.h
+++ b/include/uapi/linux/kfd_ioctl.h
@@ -34,9 +34,10 @@
  * - 1.6 - Query clear flags in SVM get_attr API
  * - 1.7 - Checkpoint Restore (CRIU) API
  * - 1.8 - CRIU - Support for SDMA transfers with GTT BOs
+ * - 1.9 - Add available memory ioctl
  */
 #define KFD_IOCTL_MAJOR_VERSION 1
-#define KFD_IOCTL_MINOR_VERSION 8
+#define KFD_IOCTL_MINOR_VERSION 9
 
 struct kfd_ioctl_get_version_args {
 	__u32 major_version;	/* from KFD */
@@ -100,6 +101,12 @@ struct kfd_ioctl_get_queue_wave_state_args {
 	__u32 pad;
 };
 
+struct kfd_ioctl_get_available_memory_args {
+	__u64 available;	/* from KFD */
+	__u32 gpu_id;		/* to KFD */
+	__u32 pad;
+};
+
 /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */
 #define KFD_IOC_CACHE_POLICY_COHERENT 0
 #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1
@@ -826,7 +833,10 @@ struct kfd_ioctl_set_xnack_mode_args {
 #define AMDKFD_IOC_CRIU_OP			\
 		AMDKFD_IOWR(0x22, struct kfd_ioctl_criu_args)
 
+#define AMDKFD_IOC_AVAILABLE_MEMORY		\
+		AMDKFD_IOWR(0x23, struct kfd_ioctl_get_available_memory_args)
+
 #define AMDKFD_COMMAND_START		0x01
-#define AMDKFD_COMMAND_END		0x23
+#define AMDKFD_COMMAND_END		0x24
 
 #endif
-- 
GitLab


From c443514a7d6d648bc497efbe502e2a49738b94de Mon Sep 17 00:00:00 2001
From: Wenjing Liu <wenjing.liu@amd.com>
Date: Thu, 26 May 2022 15:52:42 -0400
Subject: [PATCH 0573/1731] drm/amd/display: lower lane count first when CR
 done partially fails in EQ

[why]
According to DP specs, in EQ DONE phase of link training, we
should lower lane count when at least one CR DONE bit is set to 1, while
lower link rate when all CR DONE bits are 0s. However in our code, we will
treat both cases as latter. This is not exactly correct based on the specs
expectation.

[how]
Check lane0 CR DONE bit when it is still set but CR DONE fails,
we treat it as a partial CR DONE failure in EQ DONE phase, we
will follow the same fallback flow as when ED DONE fails in EQ
DONE phase.

Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c    | 13 +++++++------
 .../drm/amd/display/include/link_service_types.h    |  2 ++
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index c1207049dbc59..f9c10d044da6a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1326,7 +1326,9 @@ static enum link_training_result perform_channel_equalization_sequence(
 
 		/* 5. check CR done*/
 		if (!dp_is_cr_done(lane_count, dpcd_lane_status))
-			return LINK_TRAINING_EQ_FAIL_CR;
+			return dpcd_lane_status[0].bits.CR_DONE_0 ?
+					LINK_TRAINING_EQ_FAIL_CR_PARTIAL :
+					LINK_TRAINING_EQ_FAIL_CR;
 
 		/* 6. check CHEQ done*/
 		if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
@@ -1882,6 +1884,9 @@ static void print_status_message(
 	case LINK_TRAINING_EQ_FAIL_CR:
 		lt_result = "CR failed in EQ";
 		break;
+	case LINK_TRAINING_EQ_FAIL_CR_PARTIAL:
+		lt_result = "CR failed in EQ partially";
+		break;
 	case LINK_TRAINING_EQ_FAIL_EQ:
 		lt_result = "EQ failed";
 		break;
@@ -3612,11 +3617,6 @@ static bool decide_fallback_link_setting(
 		struct dc_link_settings *cur,
 		enum link_training_result training_result)
 {
-	if (!cur)
-		return false;
-	if (!max)
-		return false;
-
 	if (dp_get_link_encoding_format(max) == DP_128b_132b_ENCODING ||
 			link->dc->debug.force_dp2_lt_fallback_method)
 		return decide_fallback_link_setting_max_bw_policy(link, max, cur,
@@ -3646,6 +3646,7 @@ static bool decide_fallback_link_setting(
 		break;
 	}
 	case LINK_TRAINING_EQ_FAIL_EQ:
+	case LINK_TRAINING_EQ_FAIL_CR_PARTIAL:
 	{
 		if (!reached_minimum_lane_count(cur->lane_count)) {
 			cur->lane_count = reduce_lane_count(cur->lane_count);
diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h
index 447a56286dd06..23f7d7354aaa5 100644
--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
@@ -67,6 +67,8 @@ enum link_training_result {
 	LINK_TRAINING_CR_FAIL_LANE23,
 	/* CR DONE bit is cleared during EQ step */
 	LINK_TRAINING_EQ_FAIL_CR,
+	/* CR DONE bit is cleared but LANE0_CR_DONE is set during EQ step */
+	LINK_TRAINING_EQ_FAIL_CR_PARTIAL,
 	/* other failure during EQ step */
 	LINK_TRAINING_EQ_FAIL_EQ,
 	LINK_TRAINING_LQA_FAIL,
-- 
GitLab


From b840b64bc8ed3fc46f6d6aa7f97c43862a33bea5 Mon Sep 17 00:00:00 2001
From: Shah Dharati <dharshah@amd.com>
Date: Tue, 31 May 2022 09:58:12 -0400
Subject: [PATCH 0574/1731] drm/amd/display: Fix monitor flash issue

[Why & How]
For a some specific monitors, when connected on boot or hot plug,
monitor flash for 1/2 seconds can happen during first HDCP query
operation. Ading some delay in the init sequence for these monitors
fixes the issue, so it is implemented as monitor specific patch.

Co-authored-by: Shah Dharati <dharshah@amd.com>
Reviewed-by: Hansen Dsouza <Hansen.Dsouza@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Shah Dharati <dharshah@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
index 1f4095b264097..c5f6c11de7e5d 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
@@ -524,7 +524,7 @@ enum mod_hdcp_status mod_hdcp_hdcp2_dp_transition(struct mod_hdcp *hdcp,
 			set_watchdog_in_ms(hdcp, 3000, output);
 			set_state_id(hdcp, output, D2_A6_WAIT_FOR_RX_ID_LIST);
 		} else {
-			callback_in_ms(0, output);
+			callback_in_ms(1, output);
 			set_state_id(hdcp, output, D2_SEND_CONTENT_STREAM_TYPE);
 		}
 		break;
-- 
GitLab


From 71be4b16d39ac8b25a8a04eda66cb65581e1a03c Mon Sep 17 00:00:00 2001
From: hersen wu <hersenxs.wu@amd.com>
Date: Sun, 29 May 2022 10:54:30 -0400
Subject: [PATCH 0575/1731] drm/amd/display: dsc validate fail not pass to
 atomic check

[Why] when 4k@144hz dp connect to dp1.4 dsc mst hub, requested
bandwidth exceeds caps of dsc hub. but dsc bw valid functions,
increase_dsc_bpp, try_disable_dsc, pre_validate_dsc,
compute_mst_dsc_configs_for_state, do not return false to
atomic check. this cause user mode initiate mode set to kernel,
then cause kernel assert, system hang.

[How] dsc bandwidth valid functions return pass or fail to atomic
check.

Reviewed-by: Wayne Lin <Wayne.Lin@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  6 ++-
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 43 +++++++++++++------
 .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |  2 +-
 3 files changed, 35 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 4a90ee111aec9..60fb99b747131 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -11255,7 +11255,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 				}
 			}
 		}
-		pre_validate_dsc(state, &dm_state, vars);
+		if (!pre_validate_dsc(state, &dm_state, vars)) {
+			ret = -EINVAL;
+			goto fail;
+		}
 	}
 #endif
 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
@@ -11501,6 +11504,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 		if (!compute_mst_dsc_configs_for_state(state, dm_state->context, vars)) {
 			DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
+			ret = -EINVAL;
 			goto fail;
 		}
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index a6d551ff89d1f..7e246a798c8a4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -670,7 +670,7 @@ static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
 	return dsc_config.bits_per_pixel;
 }
 
-static void increase_dsc_bpp(struct drm_atomic_state *state,
+static bool increase_dsc_bpp(struct drm_atomic_state *state,
 			     struct dc_link *dc_link,
 			     struct dsc_mst_fairness_params *params,
 			     struct dsc_mst_fairness_vars *vars,
@@ -730,7 +730,7 @@ static void increase_dsc_bpp(struct drm_atomic_state *state,
 							  params[next_index].port,
 							  vars[next_index].pbn,
 							  pbn_per_timeslot) < 0)
-				return;
+				return false;
 			if (!drm_dp_mst_atomic_check(state)) {
 				vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
 			} else {
@@ -740,7 +740,7 @@ static void increase_dsc_bpp(struct drm_atomic_state *state,
 								  params[next_index].port,
 								  vars[next_index].pbn,
 								  pbn_per_timeslot) < 0)
-					return;
+					return false;
 			}
 		} else {
 			vars[next_index].pbn += initial_slack[next_index];
@@ -749,7 +749,7 @@ static void increase_dsc_bpp(struct drm_atomic_state *state,
 							  params[next_index].port,
 							  vars[next_index].pbn,
 							  pbn_per_timeslot) < 0)
-				return;
+				return false;
 			if (!drm_dp_mst_atomic_check(state)) {
 				vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
 			} else {
@@ -759,16 +759,17 @@ static void increase_dsc_bpp(struct drm_atomic_state *state,
 								  params[next_index].port,
 								  vars[next_index].pbn,
 								  pbn_per_timeslot) < 0)
-					return;
+					return false;
 			}
 		}
 
 		bpp_increased[next_index] = true;
 		remaining_to_increase--;
 	}
+	return true;
 }
 
-static void try_disable_dsc(struct drm_atomic_state *state,
+static bool try_disable_dsc(struct drm_atomic_state *state,
 			    struct dc_link *dc_link,
 			    struct dsc_mst_fairness_params *params,
 			    struct dsc_mst_fairness_vars *vars,
@@ -816,7 +817,7 @@ static void try_disable_dsc(struct drm_atomic_state *state,
 						  params[next_index].port,
 						  vars[next_index].pbn,
 						  dm_mst_get_pbn_divider(dc_link)) < 0)
-			return;
+			return false;
 
 		if (!drm_dp_mst_atomic_check(state)) {
 			vars[next_index].dsc_enabled = false;
@@ -828,12 +829,13 @@ static void try_disable_dsc(struct drm_atomic_state *state,
 							  params[next_index].port,
 							  vars[next_index].pbn,
 							  dm_mst_get_pbn_divider(dc_link)) < 0)
-				return;
+				return false;
 		}
 
 		tried[next_index] = true;
 		remaining_to_try--;
 	}
+	return true;
 }
 
 static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
@@ -949,9 +951,11 @@ static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 		return false;
 
 	/* Optimize degree of compression */
-	increase_dsc_bpp(state, dc_link, params, vars, count, k);
+	if (!increase_dsc_bpp(state, dc_link, params, vars, count, k))
+		return false;
 
-	try_disable_dsc(state, dc_link, params, vars, count, k);
+	if (!try_disable_dsc(state, dc_link, params, vars, count, k))
+		return false;
 
 	set_dsc_configs_from_fairness_vars(params, vars, count, k);
 
@@ -1223,21 +1227,22 @@ static bool is_dsc_precompute_needed(struct drm_atomic_state *state)
 	return ret;
 }
 
-void pre_validate_dsc(struct drm_atomic_state *state,
+bool pre_validate_dsc(struct drm_atomic_state *state,
 		      struct dm_atomic_state **dm_state_ptr,
 		      struct dsc_mst_fairness_vars *vars)
 {
 	int i;
 	struct dm_atomic_state *dm_state;
 	struct dc_state *local_dc_state = NULL;
+	int ret = 0;
 
 	if (!is_dsc_precompute_needed(state)) {
 		DRM_INFO_ONCE("DSC precompute is not needed.\n");
-		return;
+		return true;
 	}
 	if (dm_atomic_get_state(state, dm_state_ptr)) {
 		DRM_INFO_ONCE("dm_atomic_get_state() failed\n");
-		return;
+		return false;
 	}
 	dm_state = *dm_state_ptr;
 
@@ -1249,7 +1254,7 @@ void pre_validate_dsc(struct drm_atomic_state *state,
 
 	local_dc_state = kmemdup(dm_state->context, sizeof(struct dc_state), GFP_KERNEL);
 	if (!local_dc_state)
-		return;
+		return false;
 
 	for (i = 0; i < local_dc_state->stream_count; i++) {
 		struct dc_stream_state *stream = dm_state->context->streams[i];
@@ -1275,11 +1280,19 @@ void pre_validate_dsc(struct drm_atomic_state *state,
 								&state->crtcs[ind].new_state->mode,
 								dm_new_conn_state,
 								dm_old_crtc_state->stream);
+			if (local_dc_state->streams[i] == NULL) {
+				ret = -EINVAL;
+				break;
+			}
 		}
 	}
 
+	if (ret != 0)
+		goto clean_exit;
+
 	if (!pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars)) {
 		DRM_INFO_ONCE("pre_compute_mst_dsc_configs_for_state() failed\n");
+		ret = -EINVAL;
 		goto clean_exit;
 	}
 
@@ -1309,5 +1322,7 @@ clean_exit:
 	}
 
 	kfree(local_dc_state);
+
+	return (ret == 0);
 }
 #endif
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
index 85628ad59e6c1..2e13027d9b884 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
@@ -59,7 +59,7 @@ bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
 
 bool needs_dsc_aux_workaround(struct dc_link *link);
 
-void pre_validate_dsc(struct drm_atomic_state *state,
+bool pre_validate_dsc(struct drm_atomic_state *state,
 		      struct dm_atomic_state **dm_state_ptr,
 		      struct dsc_mst_fairness_vars *vars);
 
-- 
GitLab


From a141d2083b462505727e14d98db5fc3cd43d59c6 Mon Sep 17 00:00:00 2001
From: Alvin Lee <Alvin.Lee2@amd.com>
Date: Fri, 3 Jun 2022 16:39:48 -0400
Subject: [PATCH 0576/1731] drm/amd/display: Add debug option for exiting idle
 optimizations on cursor updates

[Description]
- Have option to exit idle opt on cursor updates
for debug and optimizations purposes

Reviewed-by: Samson Tam <Samson.Tam@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 5 +++--
 drivers/gpu/drm/amd/display/dc/dc.h             | 1 +
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index de8b214132a29..167bb33108776 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -389,7 +389,7 @@ bool dc_stream_set_cursor_position(
 	struct dc_stream_state *stream,
 	const struct dc_cursor_position *position)
 {
-	struct dc  *dc;
+	struct dc  *dc = stream->ctx->dc;
 	bool reset_idle_optimizations = false;
 
 	if (NULL == stream) {
@@ -406,7 +406,8 @@ bool dc_stream_set_cursor_position(
 	dc_z10_restore(dc);
 
 	/* disable idle optimizations if enabling cursor */
-	if (dc->idle_optimizations_allowed && !stream->cursor_position.enable && position->enable) {
+	if (dc->idle_optimizations_allowed && (!stream->cursor_position.enable || dc->debug.exit_idle_opt_for_cursor_updates)
+			&& position->enable) {
 		dc_allow_idle_optimizations(dc, false);
 		reset_idle_optimizations = true;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 76db013aac6e0..7191fc48c2e70 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -748,6 +748,7 @@ struct dc_debug_options {
 	uint8_t psr_power_use_phy_fsm;
 	enum dml_hostvm_override_opts dml_hostvm_override;
 	bool use_legacy_soc_bb_mechanism;
+	bool exit_idle_opt_for_cursor_updates;
 };
 
 struct gpu_info_soc_bounding_box_v1_0;
-- 
GitLab


From f51d22b0d04aa33e94d663fb63aa61e4da168523 Mon Sep 17 00:00:00 2001
From: Qingqing Zhuo <qingqing.zhuo@amd.com>
Date: Fri, 3 Jun 2022 14:44:58 -0400
Subject: [PATCH 0577/1731] drm/amd/display: update topology_update_input_v3
 struct

[Why]
DIO parameters were missing in topology_update_intput_v3 struct.

[How]
Add DIO parameters in v3 struct and update in functions perspectively.

Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c    |  2 ++
 drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c   |  4 ++++
 drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h   | 11 +++++++++++
 3 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index 15c0e3f2a9c36..fcafe07ed9087 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -476,6 +476,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
 	link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1;
 	display->stream_enc_idx = config->stream_enc_idx;
 	link->link_enc_idx = config->link_enc_idx;
+	link->dio_output_id = config->dio_output_idx;
 	link->phy_idx = config->phy_idx;
 	if (sink)
 		link_is_hdcp14 = dc_link_is_hdcp14(aconnector->dc_link, sink->sink_signal);
@@ -483,6 +484,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
 	link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw;
 	link->dp.assr_enabled = config->assr_enabled;
 	link->dp.mst_enabled = config->mst_enabled;
+	link->dp.usb4_enabled = config->usb4_enabled;
 	display->adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION;
 	link->adjust.auth_delay = 3;
 	link->adjust.hdcp1.disable = 0;
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
index be61975f14703..ee67a35c2a8ed 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
@@ -202,6 +202,10 @@ static enum mod_hdcp_status add_display_to_topology_v3(
 	dtm_cmd->dtm_status = TA_DTM_STATUS__GENERIC_FAILURE;
 	dtm_cmd->dtm_in_message.topology_update_v3.phy_id = link->phy_idx;
 	dtm_cmd->dtm_in_message.topology_update_v3.link_hdcp_cap = link->hdcp_supported_informational;
+	dtm_cmd->dtm_in_message.topology_update_v3.dio_output_type = link->dp.usb4_enabled ?
+			TA_DTM_DIO_OUTPUT_TYPE__DPIA :
+			TA_DTM_DIO_OUTPUT_TYPE__DIRECT;
+	dtm_cmd->dtm_in_message.topology_update_v3.dio_output_id = link->dio_output_id;
 
 	psp_dtm_invoke(psp, dtm_cmd->cmd_id);
 	mutex_unlock(&psp->dtm_context.mutex);
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
index 2937b4b614614..5b71bc96b98c5 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
@@ -94,6 +94,15 @@ enum ta_dtm_encoder_type {
 	TA_DTM_ENCODER_TYPE__DIG        = 0x10
 };
 
+/* @enum ta_dtm_dio_output_type
+ * This enum defines software value for dio_output_type
+ */
+typedef enum {
+    TA_DTM_DIO_OUTPUT_TYPE__INVALID,
+    TA_DTM_DIO_OUTPUT_TYPE__DIRECT,
+    TA_DTM_DIO_OUTPUT_TYPE__DPIA
+} ta_dtm_dio_output_type;
+
 struct ta_dtm_topology_update_input_v3 {
 	/* display handle is unique across the driver and is used to identify a display */
 	/* for all security interfaces which reference displays such as HDCP */
@@ -111,6 +120,8 @@ struct ta_dtm_topology_update_input_v3 {
 	enum ta_dtm_encoder_type encoder_type;
 	uint32_t phy_id;
 	uint32_t link_hdcp_cap;
+	ta_dtm_dio_output_type dio_output_type;
+	uint32_t dio_output_id;
 };
 
 struct ta_dtm_topology_assr_enable {
-- 
GitLab


From 5f034aef8479ac80e8732958dcb66b8eda650659 Mon Sep 17 00:00:00 2001
From: Aric Cyr <aric.cyr@amd.com>
Date: Sun, 5 Jun 2022 22:50:30 -0400
Subject: [PATCH 0578/1731] drm/amd/display: 3.2.190

This version brings along the following:
- DP fixes
- Exiting idle optimizations on mouse updates

Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 7191fc48c2e70..0549fa2c572a8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -47,7 +47,7 @@ struct aux_payload;
 struct set_config_cmd_payload;
 struct dmub_notification;
 
-#define DC_VER "3.2.189"
+#define DC_VER "3.2.190"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
GitLab


From 85ee819fd08eff7617c186775fd958e6258216db Mon Sep 17 00:00:00 2001
From: Oliver Logush <oliver.logush@amd.com>
Date: Fri, 13 Aug 2021 13:44:56 -0400
Subject: [PATCH 0579/1731] drm/amd/display: Drop unused privacy_mask setters
 and getters

[Why and How]
dwbc_funcs.set/get_privacy_mask isn't being used anymore, drop it

Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Oliver Logush <oliver.logush@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
index fd6572ba3fb28..b982be64c7928 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
@@ -219,12 +219,6 @@ struct dwbc_funcs {
 		struct dwbc *dwbc,
 		const struct dc_transfer_func *in_transfer_func_dwb_ogam);
 
-	void (*get_privacy_mask)(
-		struct dwbc *dwbc, uint32_t *mask_id);
-
-	void (*set_privacy_mask)(
-		struct dwbc *dwbc, uint32_t mask_id);
-
 	//TODO: merge with output_transfer_func?
 	bool (*dwb_ogam_set_input_transfer_func)(
 		struct dwbc *dwbc,
-- 
GitLab


From f69e98a91a01fd7c5755dd710e94a17d6e9f583f Mon Sep 17 00:00:00 2001
From: Samson Tam <Samson.Tam@amd.com>
Date: Tue, 9 Mar 2021 17:23:10 -0500
Subject: [PATCH 0580/1731] drm/amd/display: Fix comments

[Why & how]
Fix format and typo of comments.

Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  |  1 -
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  8 ++++++--
 .../dc/gpio/dcn20/hw_translate_dcn20.c        | 17 ++++++++++-------
 .../dc/gpio/dcn21/hw_translate_dcn21.c        | 17 ++++++++++-------
 .../dc/gpio/dcn30/hw_translate_dcn30.c        | 19 +++++++++++--------
 5 files changed, 37 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index cac80ba69072d..fb82e9f9738ef 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -436,7 +436,6 @@ void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base)
 		clk_mgr_base->clks.dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
 				* clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
 	}
-
 }
 
 void dcn2_get_clock(struct clk_mgr *clk_mgr,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 7884530cc02be..199868925fe48 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1379,7 +1379,9 @@ bool dc_link_get_hpd_state(struct dc_link *dc_link)
 static enum hpd_source_id get_hpd_line(struct dc_link *link)
 {
 	struct gpio *hpd;
-	enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
+	enum hpd_source_id hpd_id;
+
+	hpd_id = HPD_SOURCEID_UNKNOWN;
 
 	hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 			   link->ctx->gpio_service);
@@ -1418,7 +1420,9 @@ static enum hpd_source_id get_hpd_line(struct dc_link *link)
 static enum channel_id get_ddc_line(struct dc_link *link)
 {
 	struct ddc *ddc;
-	enum channel_id channel = CHANNEL_ID_UNKNOWN;
+	enum channel_id channel;
+
+	channel = CHANNEL_ID_UNKNOWN;
 
 	ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
index 52ba62b3b5e41..3005ee7751a03 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
@@ -150,7 +150,8 @@ static bool offset_to_id(
 	/* DDC */
 	/* we don't care about the GPIO_ID for DDC
 	 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
-	 * directly in the create method */
+	 * directly in the create method
+	 */
 	case REG(DC_GPIO_DDC1_A):
 		*en = GPIO_DDC_LINE_DDC1;
 		return true;
@@ -173,14 +174,16 @@ static bool offset_to_id(
 		*en = GPIO_DDC_LINE_DDC_VGA;
 		return true;
 
-//	case REG(DC_GPIO_I2CPAD_A): not exit
-//	case REG(DC_GPIO_PWRSEQ_A):
-//	case REG(DC_GPIO_PAD_STRENGTH_1):
-//	case REG(DC_GPIO_PAD_STRENGTH_2):
-//	case REG(DC_GPIO_DEBUG):
+/*
+ *	case REG(DC_GPIO_I2CPAD_A): not exit
+ *	case REG(DC_GPIO_PWRSEQ_A):
+ *	case REG(DC_GPIO_PAD_STRENGTH_1):
+ *	case REG(DC_GPIO_PAD_STRENGTH_2):
+ *	case REG(DC_GPIO_DEBUG):
+ */
 	/* UNEXPECTED */
 	default:
-//	case REG(DC_GPIO_SYNCA_A): not exist
+/*	case REG(DC_GPIO_SYNCA_A): not exist */
 		ASSERT_CRITICAL(false);
 		return false;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
index 291966efe63df..d734e3a134d18 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
@@ -153,7 +153,8 @@ static bool offset_to_id(
 	/* DDC */
 	/* we don't care about the GPIO_ID for DDC
 	 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
-	 * directly in the create method */
+	 * directly in the create method
+	 */
 	case REG(DC_GPIO_DDC1_A):
 		*en = GPIO_DDC_LINE_DDC1;
 		return true;
@@ -173,14 +174,16 @@ static bool offset_to_id(
 		*en = GPIO_DDC_LINE_DDC_VGA;
 		return true;
 
-//	case REG(DC_GPIO_I2CPAD_A): not exit
-//	case REG(DC_GPIO_PWRSEQ_A):
-//	case REG(DC_GPIO_PAD_STRENGTH_1):
-//	case REG(DC_GPIO_PAD_STRENGTH_2):
-//	case REG(DC_GPIO_DEBUG):
+/*
+ *	case REG(DC_GPIO_I2CPAD_A): not exit
+ *	case REG(DC_GPIO_PWRSEQ_A):
+ *	case REG(DC_GPIO_PAD_STRENGTH_1):
+ *	case REG(DC_GPIO_PAD_STRENGTH_2):
+ *	case REG(DC_GPIO_DEBUG):
+ */
 	/* UNEXPECTED */
 	default:
-//	case REG(DC_GPIO_SYNCA_A): not exist
+/*	case REG(DC_GPIO_SYNCA_A): not exista */
 #ifdef PALLADIUM_SUPPORTED
 		*id = GPIO_ID_HPD;
 		*en = GPIO_DDC_LINE_DDC1;
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
index 3169c567475f6..49d6250037a9a 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
@@ -155,7 +155,8 @@ static bool offset_to_id(
 	/* DDC */
 	/* we don't care about the GPIO_ID for DDC
 	 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
-	 * directly in the create method */
+	 * directly in the create method
+	 */
 	case REG(DC_GPIO_DDC1_A):
 		*en = GPIO_DDC_LINE_DDC1;
 		return true;
@@ -178,14 +179,16 @@ static bool offset_to_id(
 		*en = GPIO_DDC_LINE_DDC_VGA;
 		return true;
 
-//	case REG(DC_GPIO_I2CPAD_A): not exit
-//	case REG(DC_GPIO_PWRSEQ_A):
-//	case REG(DC_GPIO_PAD_STRENGTH_1):
-//	case REG(DC_GPIO_PAD_STRENGTH_2):
-//	case REG(DC_GPIO_DEBUG):
+/*
+ *	case REG(DC_GPIO_I2CPAD_A): not exit
+ *	case REG(DC_GPIO_PWRSEQ_A):
+ *	case REG(DC_GPIO_PAD_STRENGTH_1):
+ *	case REG(DC_GPIO_PAD_STRENGTH_2):
+ *	case REG(DC_GPIO_DEBUG):
+ */
 	/* UNEXPECTED */
 	default:
-//	case REG(DC_GPIO_SYNCA_A): not exist
+/*	case REG(DC_GPIO_SYNCA_A): not exist */
 		ASSERT_CRITICAL(false);
 		return false;
 	}
@@ -369,7 +372,7 @@ static const struct hw_translate_funcs funcs = {
 };
 
 /*
- * dal_hw_translate_dcn10_init
+ * dal_hw_translate_dcn30_init
  *
  * @brief
  * Initialize Hw translate function pointers.
-- 
GitLab


From a34136a3b3526369e1b3e678590e3760e7653f0f Mon Sep 17 00:00:00 2001
From: Ian Chen <ian.chen@amd.com>
Date: Mon, 10 May 2021 12:17:26 +0800
Subject: [PATCH 0581/1731] drm/amd/display: DAL ACR, dc part, fix missing
 dcn30

[Why]
- missing in dcn30 function
- Fix a divide by 0 when ACR trigger

[How]
- Add IS_SMU_TIMEOUT() to dcn30_smu_send_msg_with_param
- Add zero check in dcn20_update_clocks_update_dentist

Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Ian Chen <ian.chen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  | 22 +++++++++++++------
 .../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c  | 11 +++++++++-
 2 files changed, 25 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index fb82e9f9738ef..0d30d1d9d67e9 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -126,16 +126,24 @@ void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
 
 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct dc_state *context)
 {
-	int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
-			* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
-	int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
-			* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
-
-	uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
-	uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
+	int dpp_divider = 0;
+	int disp_divider = 0;
+	uint32_t dppclk_wdivider = 0;
+	uint32_t dispclk_wdivider = 0;
 	uint32_t current_dispclk_wdivider;
 	uint32_t i;
 
+	if (clk_mgr->base.clks.dppclk_khz == 0 || clk_mgr->base.clks.dispclk_khz == 0)
+		return;
+
+	dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+		* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
+	disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+		* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
+
+	dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
+	dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
+
 	REG_GET(DENTIST_DISPCLK_CNTL,
 			DENTIST_DISPCLK_WDIVIDER, &current_dispclk_wdivider);
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
index bfc960579760c..1fbf1c105dc12 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
@@ -28,6 +28,8 @@
 
 #include "clk_mgr_internal.h"
 #include "reg_helper.h"
+#include "dm_helpers.h"
+
 #include "dalsmc.h"
 #include "dcn30_smu11_driver_if.h"
 
@@ -74,6 +76,7 @@ static uint32_t dcn30_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, un
 
 static bool dcn30_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)
 {
+	uint32_t result;
 	/* Wait for response register to be ready */
 	dcn30_smu_wait_for_response(clk_mgr, 10, 200000);
 
@@ -86,8 +89,14 @@ static bool dcn30_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint
 	/* Trigger the message transaction by writing the message ID */
 	REG_WRITE(DAL_MSG_REG, msg_id);
 
+	result = dcn30_smu_wait_for_response(clk_mgr, 10, 200000);
+
+	if (IS_SMU_TIMEOUT(result)) {
+		dm_helpers_smu_timeout(CTX, msg_id, param_in, 10 * 200000);
+	}
+
 	/* Wait for response */
-	if (dcn30_smu_wait_for_response(clk_mgr, 10, 200000) == DALSMC_Result_OK) {
+	if (result == DALSMC_Result_OK) {
 		if (param_out)
 			*param_out = REG_READ(DAL_ARG_REG);
 
-- 
GitLab


From c2fbe663ec4f991832d67f936d3941f781884156 Mon Sep 17 00:00:00 2001
From: Felipe Clark <felipe.clark@amd.com>
Date: Sun, 7 Mar 2021 13:27:30 -0500
Subject: [PATCH 0582/1731] drm/amd/display: Firmware assisted MCLK switch and
 FS

[WHY]
Memory clock switching has great potential for power savings.

[HOW]
The driver code was modified to notify the DMCUB firmware that it should
stretch the vertical blank of frames when a memory clock switch is about
to start so that no blackouts happen on the screen due to unavailability
of the frame buffer.
The driver logic to determine when such firmware assisted strategy can
be initiated is also implemented and consists on checking prerequisites
of the feature.

Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Felipe Clark <felipe.clark@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c      |  8 ++++--
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c  |  2 ++
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h  |  5 +++-
 drivers/gpu/drm/amd/display/dc/dc_stream.h    |  3 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  1 -
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  1 -
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.c    | 28 +++++++++++--------
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.h    | 11 ++++++--
 .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c |  2 +-
 .../gpu/drm/amd/display/dc/dcn30/dcn30_optc.c |  1 +
 .../drm/amd/display/dc/dcn30/dcn30_resource.c |  1 +
 .../amd/display/dc/inc/hw_sequencer_private.h |  1 +
 .../amd/display/modules/freesync/freesync.c   |  5 ++++
 .../amd/display/modules/inc/mod_freesync.h    |  4 +++
 14 files changed, 51 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 645ec5bc3a7d7..cfa6c2d1fc692 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -397,7 +397,6 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 		struct dc_crtc_timing_adjust *adjust)
 {
 	int i;
-	bool ret = false;
 
 	stream->adjust.v_total_max = adjust->v_total_max;
 	stream->adjust.v_total_mid = adjust->v_total_mid;
@@ -412,10 +411,10 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 					1,
 					*adjust);
 
-			ret = true;
+			return true;
 		}
 	}
-	return ret;
+	return false;
 }
 
 /**
@@ -2650,6 +2649,9 @@ static void copy_stream_update_to_stream(struct dc *dc,
 	if (update->vrr_infopacket)
 		stream->vrr_infopacket = *update->vrr_infopacket;
 
+	if (update->allow_freesync)
+		stream->allow_freesync = *update->allow_freesync;
+
 	if (update->crtc_timing_adjust)
 		stream->adjust = *update->crtc_timing_adjust;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 11597bca966ab..548c91ad1b820 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -27,6 +27,8 @@
 #include "dc_dmub_srv.h"
 #include "../dmub/dmub_srv.h"
 #include "dm_helpers.h"
+#include "dc_hw_types.h"
+#include "core_types.h"
 
 #define CTX dc_dmub_srv->ctx
 #define DC_LOGGER CTX->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
index 50e44b53f14c2..52758ff1e4057 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
@@ -31,6 +31,10 @@
 
 struct dmub_srv;
 struct dc;
+struct pipe_ctx;
+struct dc_crtc_timing_adjust;
+struct dc_crtc_timing;
+struct dc_state;
 
 struct dc_reg_helper_state {
 	bool gather_in_progress;
@@ -69,7 +73,6 @@ bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_bu
 void dc_dmub_trace_event_control(struct dc *dc, bool enable);
 
 void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub);
-
 void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv);
 void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv);
 void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_data_register data);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index f8f66790d09bf..68cf06a5a3e3c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -205,6 +205,7 @@ struct dc_stream_state {
 	bool use_vsc_sdp_for_colorimetry;
 	bool ignore_msa_timing_param;
 
+	bool allow_freesync;
 	bool freesync_on_desktop;
 
 	bool converter_disable_audio;
@@ -295,9 +296,9 @@ struct dc_stream_update {
 	struct dc_info_packet *vrr_infopacket;
 	struct dc_info_packet *vsc_infopacket;
 	struct dc_info_packet *vsp_infopacket;
-
 	bool *dpms_off;
 	bool integer_scaling_update;
+	bool *allow_freesync;
 
 	struct colorspace_transform *gamut_remap;
 	enum dc_color_space *output_color_space;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 573d5be9e302d..fff724e94eed0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2613,7 +2613,6 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 	dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
 
 	ASSERT(new_mpcc != NULL);
-
 	hubp->opp_id = pipe_ctx->stream_res.opp->inst;
 	hubp->mpcc_id = mpcc_id;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index facd4e01b7ac1..76f8b40b21651 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2446,7 +2446,6 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 			NULL,
 			hubp->inst,
 			mpcc_id);
-
 	dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
 
 	ASSERT(new_mpcc != NULL);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index ecdc7c7812172..08b8893ff1453 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -48,6 +48,8 @@
 #include "dc_dmub_srv.h"
 #include "link_hwss.h"
 #include "dpcd_defs.h"
+#include "../dcn20/dcn20_hwseq.h"
+#include "dcn30_resource.h"
 #include "inc/dc_link_dp.h"
 #include "inc/link_dpcd.h"
 
@@ -344,17 +346,6 @@ void dcn30_enable_writeback(
 	dwb->funcs->enable(dwb, &wb_info->dwb_params);
 }
 
-void dcn30_prepare_bandwidth(struct dc *dc,
- 	struct dc_state *context)
-{
-	if (dc->clk_mgr->dc_mode_softmax_enabled)
-		if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
-				context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
-			dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
-
- 	dcn20_prepare_bandwidth(dc, context);
-}
-
 void dcn30_disable_writeback(
 		struct dc *dc,
 		unsigned int dwb_pipe_inst)
@@ -647,6 +638,9 @@ void dcn30_init_hw(struct dc *dc)
 	if (dc->res_pool->hubbub->funcs->init_crb)
 		dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
 
+	// Get DMCUB capabilities
+	dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);
+	dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
 }
 
 void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
@@ -962,3 +956,15 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
 	pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
 			color_space, color_depth, solid_color, width, height, offset);
 }
+
+void dcn30_prepare_bandwidth(struct dc *dc,
+ 	struct dc_state *context)
+{
+	if (dc->clk_mgr->dc_mode_softmax_enabled)
+		if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
+				context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
+			dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
+
+ 	dcn20_prepare_bandwidth(dc, context);
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
index 73e7b690e82c9..a24a8e33a3d28 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
@@ -47,9 +47,6 @@ void dcn30_disable_writeback(
 		struct dc *dc,
 		unsigned int dwb_pipe_inst);
 
-void dcn30_prepare_bandwidth(struct dc *dc,
- 	struct dc_state *context);
-
 bool dcn30_mmhubbub_warmup(
 	struct dc *dc,
 	unsigned int num_dwb,
@@ -83,4 +80,12 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
 		const struct tg_color *solid_color,
 		int width, int height, int offset);
 
+void dcn30_set_hubp_blank(const struct dc *dc,
+		struct pipe_ctx *pipe_ctx,
+		bool blank_enable);
+
+void dcn30_prepare_bandwidth(struct dc *dc,
+	struct dc_state *context);
+
+
 #endif /* __DC_HWSS_DCN30_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
index bb347319de83a..4c06e6e1ba4a6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
@@ -59,7 +59,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
 	.pipe_control_lock = dcn20_pipe_control_lock,
 	.interdependent_update_lock = dcn10_lock_all_pipes,
 	.cursor_lock = dcn10_cursor_lock,
-	.prepare_bandwidth = dcn20_prepare_bandwidth,
+	.prepare_bandwidth = dcn30_prepare_bandwidth,
 	.optimize_bandwidth = dcn20_optimize_bandwidth,
 	.update_bandwidth = dcn20_update_bandwidth,
 	.set_drr = dcn10_set_drr,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
index b604fb26f288d..9a440ae8f8657 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
@@ -27,6 +27,7 @@
 #include "dcn30_optc.h"
 #include "dc.h"
 #include "dcn_calc_math.h"
+#include "dc_dmub_srv.h"
 
 #include "dml/dcn30/dcn30_fpu.h"
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 1c1a67c4cec1c..4cf9a6cff46ea 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -89,6 +89,7 @@
 #include "vm_helper.h"
 #include "dcn20/dcn20_vmid.h"
 #include "amdgpu_socbb.h"
+#include "dc_dmub_srv.h"
 
 #define DC_LOGGER_INIT(logger)
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
index 62a62e4fc4a8d..ded45f8f4b821 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
@@ -68,6 +68,7 @@ struct dce_hwseq;
 struct timing_generator;
 struct tg_color;
 struct output_pixel_processor;
+struct mpcc_blnd_cfg;
 
 struct hwseq_private_funcs {
 
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 03fa63d56fa65..aa121d45d9b8f 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -1374,6 +1374,11 @@ unsigned long long mod_freesync_calc_field_rate_from_timing(
 	return field_rate_in_uhz;
 }
 
+bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr, struct dc_stream_state *const pStream)
+{
+	return (pVrr->state != VRR_STATE_UNSUPPORTED) && (pVrr->state != VRR_STATE_DISABLED);
+}
+
 bool mod_freesync_is_valid_range(uint32_t min_refresh_cap_in_uhz,
 		uint32_t max_refresh_cap_in_uhz,
 		uint32_t nominal_field_rate_in_uhz)
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
index cf6bc94462445..62e326dd29a8d 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
@@ -194,4 +194,8 @@ unsigned int mod_freesync_calc_v_total_from_refresh(
 		const struct dc_stream_state *stream,
 		unsigned int refresh_in_uhz);
 
+// Returns true when FreeSync is supported and enabled (even if it is inactive)
+bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr,
+		struct dc_stream_state *const pStream);
+
 #endif
-- 
GitLab


From 2bbb54bbacd674c692306351d1be5a9b5e61a1e4 Mon Sep 17 00:00:00 2001
From: Ahmad Othman <ahmad.othman@amd.com>
Date: Mon, 4 Feb 2019 16:11:44 -0500
Subject: [PATCH 0583/1731] drm/amd/display: Add support for HF-VSIF

[Why]
- Currently there is no support for HF-VSIF
- The current support of VSIF is limited to H14b infoframe

[How]
- refactor VSIF
- Added new builder for HF-VSIF
- Added the HF-VSIF packet to DisplayTarget
- Updates DC to apply HF-VSIF updates when updating streams

Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Ahmad Othman <ahmad.othman@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c              |  3 ++-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c     | 11 +++++++++++
 drivers/gpu/drm/amd/display/dc/dc_stream.h            |  2 ++
 .../drm/amd/display/dc/dcn10/dcn10_stream_encoder.c   |  8 +++++---
 4 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index cfa6c2d1fc692..7d71fd61c0a56 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2732,7 +2732,8 @@ static void commit_planes_do_stream_update(struct dc *dc,
 			if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
 					stream_update->vrr_infopacket ||
 					stream_update->vsc_infopacket ||
-					stream_update->vsp_infopacket) {
+					stream_update->vsp_infopacket ||
+					stream_update->hfvsif_infopacket) {
 				resource_build_info_frame(pipe_ctx);
 				dc->hwss.update_info_frame(pipe_ctx);
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 9bbdfcd6b3a47..9bb0ae0dc8364 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2806,6 +2806,15 @@ static void set_vsc_info_packet(
 
 	*info_packet = stream->vsc_infopacket;
 }
+static void set_hfvs_info_packet(
+		struct dc_info_packet *info_packet,
+		struct dc_stream_state *stream)
+{
+	if (!stream->hfvsif_infopacket.valid)
+		return;
+
+	*info_packet = stream->hfvsif_infopacket;
+}
 
 void dc_resource_state_destruct(struct dc_state *context)
 {
@@ -2886,6 +2895,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
 	info->spd.valid = false;
 	info->hdrsmd.valid = false;
 	info->vsc.valid = false;
+	info->hfvsif.valid = false;
 
 	signal = pipe_ctx->stream->signal;
 
@@ -2894,6 +2904,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
 		set_avi_info_frame(&info->avi, pipe_ctx);
 
 		set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
+		set_hfvs_info_packet(&info->hfvsif, pipe_ctx->stream);
 
 		set_spd_info_packet(&info->spd, pipe_ctx->stream);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 68cf06a5a3e3c..376dddf54ec15 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -180,6 +180,7 @@ struct dc_stream_state {
 	struct dc_info_packet vrr_infopacket;
 	struct dc_info_packet vsc_infopacket;
 	struct dc_info_packet vsp_infopacket;
+	struct dc_info_packet hfvsif_infopacket;
 	uint8_t dsc_packed_pps[128];
 	struct rect src; /* composition area */
 	struct rect dst; /* stream addressable area */
@@ -296,6 +297,7 @@ struct dc_stream_update {
 	struct dc_info_packet *vrr_infopacket;
 	struct dc_info_packet *vsc_infopacket;
 	struct dc_info_packet *vsp_infopacket;
+	struct dc_info_packet *hfvsif_infopacket;
 	bool *dpms_off;
 	bool integer_scaling_update;
 	bool *allow_freesync;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index 7608187751c87..92f474e6a96bd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -675,11 +675,13 @@ static void enc1_stream_encoder_update_hdmi_info_packets(
 	/* for bring up, disable dp double  TODO */
 	REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
 
+	/*Always add mandatory packets first followed by optional ones*/
 	enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
-	enc1_update_hdmi_info_packet(enc1, 1, &info_frame->vendor);
+	enc1_update_hdmi_info_packet(enc1, 1, &info_frame->hfvsif);
 	enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
-	enc1_update_hdmi_info_packet(enc1, 3, &info_frame->spd);
-	enc1_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd);
+	enc1_update_hdmi_info_packet(enc1, 3, &info_frame->vendor);
+	enc1_update_hdmi_info_packet(enc1, 4, &info_frame->spd);
+	enc1_update_hdmi_info_packet(enc1, 5, &info_frame->hdrsmd);
 }
 
 static void enc1_stream_encoder_stop_hdmi_info_packets(
-- 
GitLab


From 28fdd0c32daf9a50a606530d54784fcfa29d88b7 Mon Sep 17 00:00:00 2001
From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Date: Tue, 14 May 2019 09:19:01 -0400
Subject: [PATCH 0584/1731] drm/amd/display: Copy hfvsif_infopacket when stream
 update

[Why & How]
Miss to copy hfvsif_infopacket when copying stream updates.
Check and copy it.

Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 7d71fd61c0a56..400b37e393b75 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2658,6 +2658,9 @@ static void copy_stream_update_to_stream(struct dc *dc,
 	if (update->dpms_off)
 		stream->dpms_off = *update->dpms_off;
 
+	if (update->hfvsif_infopacket)
+		stream->hfvsif_infopacket = *update->hfvsif_infopacket;
+
 	if (update->vsc_infopacket)
 		stream->vsc_infopacket = *update->vsc_infopacket;
 
-- 
GitLab


From 9a4c9de4838fd8ccfcfcfdcd7bd472dddd11f264 Mon Sep 17 00:00:00 2001
From: Ahmad Othman <ahmad.othman@amd.com>
Date: Thu, 1 Aug 2019 15:05:04 -0400
Subject: [PATCH 0585/1731] drm/amd/display: Adding VTEM to dc

[Why]
Video Timing Extended Metadata packet (VTEM) is required for features
like VRR and FVA

[How]
Adding support for VTEM transmission to stream encoders in DCN20 and DCN30
as part of FVA support

Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Ahmad Othman <ahmad.othman@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c           |  6 +++++-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 14 +++++++++++++-
 drivers/gpu/drm/amd/display/dc/dc_stream.h         |  2 ++
 .../amd/display/dc/dcn20/dcn20_stream_encoder.c    |  1 +
 .../display/dc/dcn30/dcn30_dio_stream_encoder.c    |  1 +
 .../gpu/drm/amd/display/dc/inc/hw/stream_encoder.h |  1 +
 6 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 400b37e393b75..7c2b652261319 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2661,6 +2661,9 @@ static void copy_stream_update_to_stream(struct dc *dc,
 	if (update->hfvsif_infopacket)
 		stream->hfvsif_infopacket = *update->hfvsif_infopacket;
 
+	if (update->vtem_infopacket)
+		stream->vtem_infopacket = *update->vtem_infopacket;
+
 	if (update->vsc_infopacket)
 		stream->vsc_infopacket = *update->vsc_infopacket;
 
@@ -2736,7 +2739,8 @@ static void commit_planes_do_stream_update(struct dc *dc,
 					stream_update->vrr_infopacket ||
 					stream_update->vsc_infopacket ||
 					stream_update->vsp_infopacket ||
-					stream_update->hfvsif_infopacket) {
+					stream_update->hfvsif_infopacket ||
+					stream_update->vtem_infopacket) {
 				resource_build_info_frame(pipe_ctx);
 				dc->hwss.update_info_frame(pipe_ctx);
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 9bb0ae0dc8364..463ff12adbc8f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2816,6 +2816,17 @@ static void set_hfvs_info_packet(
 	*info_packet = stream->hfvsif_infopacket;
 }
 
+
+static void set_vtem_info_packet(
+		struct dc_info_packet *info_packet,
+		struct dc_stream_state *stream)
+{
+	if (!stream->vtem_infopacket.valid)
+		return;
+
+	*info_packet = stream->vtem_infopacket;
+}
+
 void dc_resource_state_destruct(struct dc_state *context)
 {
 	int i, j;
@@ -2896,7 +2907,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
 	info->hdrsmd.valid = false;
 	info->vsc.valid = false;
 	info->hfvsif.valid = false;
-
+	info->vtem.valid = false;
 	signal = pipe_ctx->stream->signal;
 
 	/* HDMi and DP have different info packets*/
@@ -2905,6 +2916,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
 
 		set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
 		set_hfvs_info_packet(&info->hfvsif, pipe_ctx->stream);
+		set_vtem_info_packet(&info->vtem, pipe_ctx->stream);
 
 		set_spd_info_packet(&info->spd, pipe_ctx->stream);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 376dddf54ec15..c76fac3c153db 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -181,6 +181,7 @@ struct dc_stream_state {
 	struct dc_info_packet vsc_infopacket;
 	struct dc_info_packet vsp_infopacket;
 	struct dc_info_packet hfvsif_infopacket;
+	struct dc_info_packet vtem_infopacket;
 	uint8_t dsc_packed_pps[128];
 	struct rect src; /* composition area */
 	struct rect dst; /* stream addressable area */
@@ -298,6 +299,7 @@ struct dc_stream_update {
 	struct dc_info_packet *vsc_infopacket;
 	struct dc_info_packet *vsp_infopacket;
 	struct dc_info_packet *hfvsif_infopacket;
+	struct dc_info_packet *vtem_infopacket;
 	bool *dpms_off;
 	bool integer_scaling_update;
 	bool *allow_freesync;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
index aab25ca8343ab..e8f5c01688ec9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
@@ -159,6 +159,7 @@ static void enc2_stream_encoder_update_hdmi_info_packets(
 	enc2_update_hdmi_info_packet(enc1, 3, &info_frame->vendor);
 	enc2_update_hdmi_info_packet(enc1, 4, &info_frame->spd);
 	enc2_update_hdmi_info_packet(enc1, 5, &info_frame->hdrsmd);
+	enc2_update_hdmi_info_packet(enc1, 6, &info_frame->vtem);
 }
 
 static void enc2_stream_encoder_stop_hdmi_info_packets(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
index 1a26ce87c16e3..25e5c3bc1be92 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
@@ -212,6 +212,7 @@ void enc3_stream_encoder_update_hdmi_info_packets(
 	enc3_update_hdmi_info_packet(enc1, 1, &info_frame->vendor);
 	enc3_update_hdmi_info_packet(enc1, 3, &info_frame->spd);
 	enc3_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd);
+	enc3_update_hdmi_info_packet(enc1, 6, &info_frame->vtem);
 }
 
 void enc3_stream_encoder_stop_hdmi_info_packets(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
index e5fe0f6adc86c..e04a51a57c939 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
@@ -77,6 +77,7 @@ struct encoder_info_frame {
 	struct dc_info_packet gamut;
 	struct dc_info_packet vendor;
 	struct dc_info_packet hfvsif;
+	struct dc_info_packet vtem;
 	/* source product description */
 	struct dc_info_packet spd;
 	/* video stream configuration */
-- 
GitLab


From 3de58f22f544ec9c692993fb1f3bc77163d3d5d8 Mon Sep 17 00:00:00 2001
From: Felipe Clark <Felipe.Clark@amd.com>
Date: Fri, 26 Mar 2021 15:01:20 -0400
Subject: [PATCH 0586/1731] drm/amd/display: Pass vrr mode to dcn

[WHY]
New features will require knowing the vrr mode for their enablement.

[HOW]
Pass the state via a member of dc_stream.

Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Felipe Clark <Felipe.Clark@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc_stream.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index c76fac3c153db..ae9382ce82d32 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -208,6 +208,7 @@ struct dc_stream_state {
 	bool ignore_msa_timing_param;
 
 	bool allow_freesync;
+	bool vrr_active_variable;
 	bool freesync_on_desktop;
 
 	bool converter_disable_audio;
-- 
GitLab


From ebfb15262af3bec6c3cc263ce04164e44eea4b30 Mon Sep 17 00:00:00 2001
From: Harry VanZyllDeJong <harry.vanzylldejong@amd.com>
Date: Mon, 10 May 2021 19:30:24 -0400
Subject: [PATCH 0587/1731] drm/amd/display: Add vrr_active_variable to
 dc_stream_update

[WHY]
The display driver on some OSes need to track it in order to
perform memory clock switching decisions.

[HOW]
Propagate the vrr active state to dirty bit so that on mode set it
disables dynamic memory clock switching.

Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Harry VanZyllDeJong <harry.vanzylldejong@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c                | 3 +++
 drivers/gpu/drm/amd/display/dc/dc_stream.h              | 1 +
 drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 2 +-
 drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h  | 3 +--
 4 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 7c2b652261319..49339c5c72301 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2652,6 +2652,9 @@ static void copy_stream_update_to_stream(struct dc *dc,
 	if (update->allow_freesync)
 		stream->allow_freesync = *update->allow_freesync;
 
+	if (update->vrr_active_variable)
+		stream->vrr_active_variable = *update->vrr_active_variable;
+
 	if (update->crtc_timing_adjust)
 		stream->adjust = *update->crtc_timing_adjust;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index ae9382ce82d32..5a894c19b0ea9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -304,6 +304,7 @@ struct dc_stream_update {
 	bool *dpms_off;
 	bool integer_scaling_update;
 	bool *allow_freesync;
+	bool *vrr_active_variable;
 
 	struct colorspace_transform *gamut_remap;
 	enum dc_color_space *output_color_space;
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index aa121d45d9b8f..0686223034de0 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -1374,7 +1374,7 @@ unsigned long long mod_freesync_calc_field_rate_from_timing(
 	return field_rate_in_uhz;
 }
 
-bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr, struct dc_stream_state *const pStream)
+bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr)
 {
 	return (pVrr->state != VRR_STATE_UNSUPPORTED) && (pVrr->state != VRR_STATE_DISABLED);
 }
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
index 62e326dd29a8d..afe1f6cce5289 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
@@ -195,7 +195,6 @@ unsigned int mod_freesync_calc_v_total_from_refresh(
 		unsigned int refresh_in_uhz);
 
 // Returns true when FreeSync is supported and enabled (even if it is inactive)
-bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr,
-		struct dc_stream_state *const pStream);
+bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr);
 
 #endif
-- 
GitLab


From ac31a24d9188a9599dfbce7664cb11e6292873a5 Mon Sep 17 00:00:00 2001
From: Charlene Liu <Charlene.Liu@amd.com>
Date: Fri, 3 Apr 2020 21:06:53 -0400
Subject: [PATCH 0588/1731] drm/amd/display: FVA timing adjustment

[why]
need to add timing adjustment for fva.

[how]
add hook to optc and hwseq.

Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index b1671b00ce405..e1a9a45b03b65 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -165,6 +165,7 @@ void optc1_program_timing(
 	optc1->vupdate_width = vupdate_width;
 	patched_crtc_timing = *dc_crtc_timing;
 	apply_front_porch_workaround(&patched_crtc_timing);
+	optc1->orginal_patched_timing = patched_crtc_timing;
 
 	/* Load horizontal timing */
 
-- 
GitLab


From ac78fa502afa539cce3a285e50d7fefaf4d2115e Mon Sep 17 00:00:00 2001
From: Martin Leung <martin.leung@amd.com>
Date: Wed, 30 Oct 2019 14:19:30 -0400
Subject: [PATCH 0589/1731] drm/amd/display: Add null check to
 dc_submit_i2c_oem

[why]
dc_submit_i2c_oem could be called with ddc null

[how]
add null check and fail the call instead

Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Martin Leung <martin.leung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 49339c5c72301..258322c39e9a7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3477,10 +3477,13 @@ bool dc_submit_i2c_oem(
 		struct i2c_command *cmd)
 {
 	struct ddc_service *ddc = dc->res_pool->oem_device;
-	return dce_i2c_submit_command(
-		dc->res_pool,
-		ddc->ddc_pin,
-		cmd);
+	if (ddc)
+		return dce_i2c_submit_command(
+			dc->res_pool,
+			ddc->ddc_pin,
+			cmd);
+
+	return false;
 }
 
 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
-- 
GitLab


From ba8b460445f8d19d530646729c29319c278dbb38 Mon Sep 17 00:00:00 2001
From: Joshua Aberback <joshua.aberback@amd.com>
Date: Thu, 28 May 2020 11:11:34 -0400
Subject: [PATCH 0590/1731] drm/amd/display: Blank for uclk OC in dm instead of
 dc

[Why]
All displays need to be blanked during the uclk OC interface so that we can
guarantee pstate switching support. If the display config doesn't support
pstate switching, only using core_link_disable_stream will not enable it
as the front-end is untouched. We need to go through the full plane removal
sequence to properly program the pipe to allow pstate switching.

[How]
 - guard clk_mgr functions with non-NULL checks

Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 34 +++++++++---------------
 drivers/gpu/drm/amd/display/dc/dc.h      | 10 ++-----
 2 files changed, 14 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 258322c39e9a7..48a14a5bda563 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3666,37 +3666,27 @@ void dc_allow_idle_optimizations(struct dc *dc, bool allow)
 		dc->idle_optimizations_allowed = allow;
 }
 
-/*
- * blank all streams, and set min and max memory clock to
- * lowest and highest DPM level, respectively
- */
+/* set min and max memory clock to lowest and highest DPM level, respectively */
 void dc_unlock_memory_clock_frequency(struct dc *dc)
 {
-	unsigned int i;
-
-	for (i = 0; i < MAX_PIPES; i++)
-		if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
-			core_link_disable_stream(&dc->current_state->res_ctx.pipe_ctx[i]);
+	if (dc->clk_mgr->funcs->set_hard_min_memclk)
+		dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
 
-	dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
-	dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
+	if (dc->clk_mgr->funcs->set_hard_max_memclk)
+		dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
 }
 
-/*
- * set min memory clock to the min required for current mode,
- * max to maxDPM, and unblank streams
- */
+/* set min memory clock to the min required for current mode, max to maxDPM */
 void dc_lock_memory_clock_frequency(struct dc *dc)
 {
-	unsigned int i;
+	if (dc->clk_mgr->funcs->get_memclk_states_from_smu)
+		dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
 
-	dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
-	dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
-	dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
+	if (dc->clk_mgr->funcs->set_hard_min_memclk)
+		dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
 
-	for (i = 0; i < MAX_PIPES; i++)
-		if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
-			core_link_enable_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);
+	if (dc->clk_mgr->funcs->set_hard_max_memclk)
+		dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
 }
 
 static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memclk_mhz)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 0549fa2c572a8..ba57e03d3d9e9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1437,16 +1437,10 @@ bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_
 
 void dc_allow_idle_optimizations(struct dc *dc, bool allow);
 
-/*
- * blank all streams, and set min and max memory clock to
- * lowest and highest DPM level, respectively
- */
+/* set min and max memory clock to lowest and highest DPM level, respectively */
 void dc_unlock_memory_clock_frequency(struct dc *dc);
 
-/*
- * set min memory clock to the min required for current mode,
- * max to maxDPM, and unblank streams
- */
+/* set min memory clock to the min required for current mode, max to maxDPM */
 void dc_lock_memory_clock_frequency(struct dc *dc);
 
 /* set soft max for memclk, to be used for AC/DC switching clock limitations */
-- 
GitLab


From 68ad7f90c790a178f47ef08408d97a81cbb71b37 Mon Sep 17 00:00:00 2001
From: Yifan Zhang <yifan1.zhang@amd.com>
Date: Sun, 12 Jun 2022 12:12:34 +0800
Subject: [PATCH 0591/1731] drm/amdgpu: remove redundant enable_mes and
 enable_mes_kiq

enable_mes and enable_mes_kiq are set in both device init and
MES IP init. Leave the ones in MES IP init, since it is
a more accurate way to judge from GC IP version.

Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 45dc96aee39ef..ea9a9d781d8c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3615,14 +3615,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 	if (amdgpu_mcbp)
 		DRM_INFO("MCBP is enabled\n");
 
-	if (adev->asic_type >= CHIP_NAVI10) {
-		if (amdgpu_mes || amdgpu_mes_kiq)
-			adev->enable_mes = true;
-
-		if (amdgpu_mes_kiq)
-			adev->enable_mes_kiq = true;
-	}
-
 	/*
 	 * Reset domain needs to be present early, before XGMI hive discovered
 	 * (if any) and intitialized to use reset sem and in_gpu reset flag
-- 
GitLab


From 914da384ae9a77079314f07022c18063c7e77778 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Fri, 10 Jun 2022 11:38:05 -0400
Subject: [PATCH 0592/1731] drm/amdkfd: fix warning when CONFIG_HSA_AMD_P2P is
 not set
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c:1542:11:
warning: variable 'i' set but not used [-Wunused-but-set-variable]

Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 304322ac39e68..25990bec600d0 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1539,7 +1539,10 @@ static int kfd_dev_create_p2p_links(void)
 {
 	struct kfd_topology_device *dev;
 	struct kfd_topology_device *new_dev;
-	uint32_t i, k;
+#if defined(CONFIG_HSA_AMD_P2P)
+	uint32_t i;
+#endif
+	uint32_t k;
 	int ret = 0;
 
 	k = 0;
@@ -1553,7 +1556,6 @@ static int kfd_dev_create_p2p_links(void)
 		return 0;
 
 	k--;
-	i = 0;
 
 	/* create in-direct links */
 	ret = kfd_create_indirect_link_prop(new_dev, k);
@@ -1562,6 +1564,7 @@ static int kfd_dev_create_p2p_links(void)
 
 	/* create p2p links */
 #if defined(CONFIG_HSA_AMD_P2P)
+	i = 0;
 	list_for_each_entry(dev, &topology_device_list, list) {
 		if (dev == new_dev)
 			break;
-- 
GitLab


From 4e1db0119c64fd81509005a961790d263e99b21b Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Tue, 14 Jun 2022 09:57:26 -0400
Subject: [PATCH 0593/1731] Revert "drm/amdgpu/display: Protect some functions
 with CONFIG_DRM_AMD_DC_DCN"

This reverts commit d8e4fb9112e88d8d87ffbc38fa511e7118042d4f.

This is no longer necessary as newer patches require these functions
without CONFIG_DRM_AMD_DC_DCN.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 463ff12adbc8f..31f0262fc9308 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1801,7 +1801,6 @@ static inline void retain_hpo_dp_link_enc(
 	res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]++;
 }
 
-#if defined(CONFIG_DRM_AMD_DC_DCN)
 static inline void release_hpo_dp_link_enc(
 		struct resource_context *res_ctx,
 		int enc_index)
@@ -1809,7 +1808,6 @@ static inline void release_hpo_dp_link_enc(
 	ASSERT(res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] > 0);
 	res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]--;
 }
-#endif
 
 static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx,
 		const struct resource_pool *pool,
@@ -1834,7 +1832,6 @@ static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx,
 	return pipe_ctx->link_res.hpo_dp_link_enc != NULL;
 }
 
-#if defined(CONFIG_DRM_AMD_DC_DCN)
 static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx,
 		struct pipe_ctx *pipe_ctx,
 		struct dc_stream_state *stream)
@@ -1848,7 +1845,6 @@ static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx,
 		pipe_ctx->link_res.hpo_dp_link_enc = NULL;
 	}
 }
-#endif
 
 /* TODO: release audio object */
 void update_audio_usage(
-- 
GitLab


From 2595fe04a44d8ac7a56db27dbd1c54698d97fc0b Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Fri, 10 Jun 2022 11:17:59 -0400
Subject: [PATCH 0594/1731] drm/amdgpu/display: make FP handling in Makefiles
 consistent

Use the same pattern as the DML Makefile and while we are here
add a missing x86 guard around the msse flags for DCN3.2.x.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile | 3 +--
 drivers/gpu/drm/amd/display/dc/dcn201/Makefile  | 1 -
 drivers/gpu/drm/amd/display/dc/dcn30/Makefile   | 6 ++----
 drivers/gpu/drm/amd/display/dc/dcn302/Makefile  | 8 +++++++-
 drivers/gpu/drm/amd/display/dc/dcn32/Makefile   | 5 +++--
 drivers/gpu/drm/amd/display/dc/dcn321/Makefile  | 5 +++--
 6 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
index c935c10b5f4f5..7b505e1e93089 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
@@ -180,7 +180,7 @@ CLK_MGR_DCN32 = dcn32_clk_mgr.o dcn32_clk_mgr_smu_msg.o
 AMD_DAL_CLK_MGR_DCN32 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn32/,$(CLK_MGR_DCN32))
 
 ifdef CONFIG_X86
-CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -msse
+CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -mhard-float -msse
 endif
 
 ifdef CONFIG_PPC64
@@ -191,7 +191,6 @@ ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
 IS_OLD_GCC = 1
 endif
-CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -mhard-float
 endif
 
 ifdef CONFIG_X86
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/Makefile b/drivers/gpu/drm/amd/display/dc/dcn201/Makefile
index f68038ceb1b15..96cbd4ccd344c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/Makefile
@@ -18,7 +18,6 @@ ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
 IS_OLD_GCC = 1
 endif
-CFLAGS_$(AMDDALPATH)/dc/dcn201/dcn201_resource.o += -mhard-float
 endif
 
 ifdef CONFIG_X86
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
index dfd77b3cc84d8..c20331eb62e01 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
@@ -32,8 +32,8 @@ DCN30 = dcn30_init.o dcn30_hubbub.o dcn30_hubp.o dcn30_dpp.o dcn30_optc.o \
 
 
 ifdef CONFIG_X86
-CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -msse
-CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -msse
+CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mhard-float -msse
+CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -msse
 endif
 
 ifdef CONFIG_PPC64
@@ -45,8 +45,6 @@ ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
 IS_OLD_GCC = 1
 endif
-CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o += -mhard-float
-CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o += -mhard-float
 endif
 
 ifdef CONFIG_X86
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/Makefile b/drivers/gpu/drm/amd/display/dc/dcn302/Makefile
index f9561d7f97a1d..e4b69ad0dde56 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/Makefile
@@ -8,7 +8,7 @@
 DCN3_02 = dcn302_init.o dcn302_hwseq.o dcn302_resource.o
 
 ifdef CONFIG_X86
-CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -msse
+CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -mhard-float -msse
 endif
 
 ifdef CONFIG_PPC64
@@ -16,6 +16,12 @@ CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -mhard-float -maltivec
 endif
 
 ifdef CONFIG_X86
+ifdef CONFIG_CC_IS_GCC
+ifeq ($(call cc-ifversion, -lt, 0701, y), y)
+IS_OLD_GCC = 1
+endif
+endif
+
 ifdef IS_OLD_GCC
 # Stack alignment mismatch, proceed with caution.
 # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/Makefile b/drivers/gpu/drm/amd/display/dc/dcn32/Makefile
index 3d09db3070f45..34f2e37b67046 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/Makefile
@@ -16,7 +16,7 @@ DCN32 = dcn32_resource.o dcn32_hubbub.o dcn32_hwseq.o dcn32_init.o \
 		dcn32_mpc.o
 
 ifdef CONFIG_X86
-CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o := -msse
+CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o := -mhard-float -msse
 endif
 
 ifdef CONFIG_PPC64
@@ -27,9 +27,9 @@ ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
 IS_OLD_GCC = 1
 endif
-CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o += -mhard-float
 endif
 
+ifdef CONFIG_X86
 ifdef IS_OLD_GCC
 # Stack alignment mismatch, proceed with caution.
 # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
@@ -38,6 +38,7 @@ CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o += -mpreferred-stack-boundary=4
 else
 CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o += -msse2
 endif
+endif
 
 AMD_DAL_DCN32 = $(addprefix $(AMDDALPATH)/dc/dcn32/,$(DCN32))
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/Makefile b/drivers/gpu/drm/amd/display/dc/dcn321/Makefile
index 5896ca303e396..e554fd6c16f21 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/Makefile
@@ -13,7 +13,7 @@
 DCN321 = dcn321_resource.o dcn321_dio_link_encoder.o
 
 ifdef CONFIG_X86
-CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o := -msse
+CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o := -mhard-float -msse
 endif
 
 ifdef CONFIG_PPC64
@@ -24,9 +24,9 @@ ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
 IS_OLD_GCC = 1
 endif
-CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o += -mhard-float
 endif
 
+ifdef CONFIG_X86
 ifdef IS_OLD_GCC
 # Stack alignment mismatch, proceed with caution.
 # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
@@ -35,6 +35,7 @@ CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o += -mpreferred-stack-boundary=4
 else
 CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o += -msse2
 endif
+endif
 
 AMD_DAL_DCN321 = $(addprefix $(AMDDALPATH)/dc/dcn321/,$(DCN321))
 
-- 
GitLab


From d7dd6eccfbc95ac47a12396f84e7e1b361db654b Mon Sep 17 00:00:00 2001
From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Date: Mon, 13 Jun 2022 22:53:50 +0200
Subject: [PATCH 0595/1731] net: bgmac: Fix an erroneous kfree() in
 bgmac_remove()

'bgmac' is part of a managed resource allocated with bgmac_alloc(). It
should not be freed explicitly.

Remove the erroneous kfree() from the .remove() function.

Fixes: 34a5102c3235 ("net: bgmac: allocate struct bgmac just once & don't copy it")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/a026153108dd21239036a032b95c25b5cece253b.1655153616.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/ethernet/broadcom/bgmac-bcma.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/net/ethernet/broadcom/bgmac-bcma.c b/drivers/net/ethernet/broadcom/bgmac-bcma.c
index e6f48786949c0..02bd3cf9a260e 100644
--- a/drivers/net/ethernet/broadcom/bgmac-bcma.c
+++ b/drivers/net/ethernet/broadcom/bgmac-bcma.c
@@ -332,7 +332,6 @@ static void bgmac_remove(struct bcma_device *core)
 	bcma_mdio_mii_unregister(bgmac->mii_bus);
 	bgmac_enet_remove(bgmac);
 	bcma_set_drvdata(core, NULL);
-	kfree(bgmac);
 }
 
 static struct bcma_driver bgmac_bcma_driver = {
-- 
GitLab


From beca774fc51a9ba8abbc869cf0c3d965ff17cd24 Mon Sep 17 00:00:00 2001
From: Dominique Martinet <asmadeus@codewreck.org>
Date: Sun, 12 Jun 2022 16:00:05 +0900
Subject: [PATCH 0596/1731] 9p: fix fid refcount leak in
 v9fs_vfs_atomic_open_dotl

We need to release directory fid if we fail halfway through open

This fixes fid leaking with xfstests generic 531

Link: https://lkml.kernel.org/r/20220612085330.1451496-2-asmadeus@codewreck.org
Fixes: 6636b6dcc3db ("9p: add refcount to p9_fid struct")
Cc: stable@vger.kernel.org
Reported-by: Tyler Hicks <tyhicks@linux.microsoft.com>
Reviewed-by: Tyler Hicks <tyhicks@linux.microsoft.com>
Reviewed-by: Christian Schoenebeck <linux_oss@crudebyte.com>
Signed-off-by: Dominique Martinet <asmadeus@codewreck.org>
---
 fs/9p/vfs_inode_dotl.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/fs/9p/vfs_inode_dotl.c b/fs/9p/vfs_inode_dotl.c
index d17502a738a94..b6eb1160296c3 100644
--- a/fs/9p/vfs_inode_dotl.c
+++ b/fs/9p/vfs_inode_dotl.c
@@ -274,6 +274,7 @@ v9fs_vfs_atomic_open_dotl(struct inode *dir, struct dentry *dentry,
 	if (IS_ERR(ofid)) {
 		err = PTR_ERR(ofid);
 		p9_debug(P9_DEBUG_VFS, "p9_client_walk failed %d\n", err);
+		p9_client_clunk(dfid);
 		goto out;
 	}
 
@@ -285,6 +286,7 @@ v9fs_vfs_atomic_open_dotl(struct inode *dir, struct dentry *dentry,
 	if (err) {
 		p9_debug(P9_DEBUG_VFS, "Failed to get acl values in creat %d\n",
 			 err);
+		p9_client_clunk(dfid);
 		goto error;
 	}
 	err = p9_client_create_dotl(ofid, name, v9fs_open_to_dotl_flags(flags),
@@ -292,6 +294,7 @@ v9fs_vfs_atomic_open_dotl(struct inode *dir, struct dentry *dentry,
 	if (err < 0) {
 		p9_debug(P9_DEBUG_VFS, "p9_client_open_dotl failed in creat %d\n",
 			 err);
+		p9_client_clunk(dfid);
 		goto error;
 	}
 	v9fs_invalidate_inode_attr(dir);
-- 
GitLab


From e5690f263208c5abce7451370b7786eb25b405eb Mon Sep 17 00:00:00 2001
From: Dominique Martinet <asmadeus@codewreck.org>
Date: Sun, 12 Jun 2022 17:14:55 +0900
Subject: [PATCH 0597/1731] 9p: fix fid refcount leak in v9fs_vfs_get_link

we check for protocol version later than required, after a fid has
been obtained. Just move the version check earlier.

Link: https://lkml.kernel.org/r/20220612085330.1451496-3-asmadeus@codewreck.org
Fixes: 6636b6dcc3db ("9p: add refcount to p9_fid struct")
Cc: stable@vger.kernel.org
Reviewed-by: Tyler Hicks <tyhicks@linux.microsoft.com>
Reviewed-by: Christian Schoenebeck <linux_oss@crudebyte.com>
Signed-off-by: Dominique Martinet <asmadeus@codewreck.org>
---
 fs/9p/vfs_inode.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/fs/9p/vfs_inode.c b/fs/9p/vfs_inode.c
index 419d2f3cf2c26..3d8297714772c 100644
--- a/fs/9p/vfs_inode.c
+++ b/fs/9p/vfs_inode.c
@@ -1251,15 +1251,15 @@ static const char *v9fs_vfs_get_link(struct dentry *dentry,
 		return ERR_PTR(-ECHILD);
 
 	v9ses = v9fs_dentry2v9ses(dentry);
-	fid = v9fs_fid_lookup(dentry);
+	if (!v9fs_proto_dotu(v9ses))
+		return ERR_PTR(-EBADF);
+
 	p9_debug(P9_DEBUG_VFS, "%pd\n", dentry);
+	fid = v9fs_fid_lookup(dentry);
 
 	if (IS_ERR(fid))
 		return ERR_CAST(fid);
 
-	if (!v9fs_proto_dotu(v9ses))
-		return ERR_PTR(-EBADF);
-
 	st = p9_client_stat(fid);
 	p9_client_clunk(fid);
 	if (IS_ERR(st))
-- 
GitLab


From 2a3dcbccd64ba35c045fac92272ff981c4cbef44 Mon Sep 17 00:00:00 2001
From: Tyler Hicks <tyhicks@linux.microsoft.com>
Date: Thu, 26 May 2022 18:59:59 -0500
Subject: [PATCH 0598/1731] 9p: Fix refcounting during full path walks for fid
 lookups

Decrement the refcount of the parent dentry's fid after walking
each path component during a full path walk for a lookup. Failure to do
so can lead to fids that are not clunked until the filesystem is
unmounted, as indicated by this warning:

 9pnet: found fid 3 not clunked

The improper refcounting after walking resulted in open(2) returning
-EIO on any directories underneath the mount point when using the virtio
transport. When using the fd transport, there's no apparent issue until
the filesytem is unmounted and the warning above is emitted to the logs.

In some cases, the user may not yet be attached to the filesystem and a
new root fid, associated with the user, is created and attached to the
root dentry before the full path walk is performed. Increment the new
root fid's refcount to two in that situation so that it can be safely
decremented to one after it is used for the walk operation. The new fid
will still be attached to the root dentry when
v9fs_fid_lookup_with_uid() returns so a final refcount of one is
correct/expected.

Link: https://lkml.kernel.org/r/20220527000003.355812-2-tyhicks@linux.microsoft.com
Link: https://lkml.kernel.org/r/20220612085330.1451496-4-asmadeus@codewreck.org
Fixes: 6636b6dcc3db ("9p: add refcount to p9_fid struct")
Cc: stable@vger.kernel.org
Signed-off-by: Tyler Hicks <tyhicks@linux.microsoft.com>
Reviewed-by: Christian Schoenebeck <linux_oss@crudebyte.com>
[Dominique: fix clunking fid multiple times discussed in second link]
Signed-off-by: Dominique Martinet <asmadeus@codewreck.org>
---
 fs/9p/fid.c | 22 +++++++++-------------
 1 file changed, 9 insertions(+), 13 deletions(-)

diff --git a/fs/9p/fid.c b/fs/9p/fid.c
index 79df61fe0e596..baf2b152229e3 100644
--- a/fs/9p/fid.c
+++ b/fs/9p/fid.c
@@ -152,7 +152,7 @@ static struct p9_fid *v9fs_fid_lookup_with_uid(struct dentry *dentry,
 	const unsigned char **wnames, *uname;
 	int i, n, l, clone, access;
 	struct v9fs_session_info *v9ses;
-	struct p9_fid *fid, *old_fid = NULL;
+	struct p9_fid *fid, *old_fid;
 
 	v9ses = v9fs_dentry2v9ses(dentry);
 	access = v9ses->flags & V9FS_ACCESS_MASK;
@@ -194,13 +194,12 @@ static struct p9_fid *v9fs_fid_lookup_with_uid(struct dentry *dentry,
 		if (IS_ERR(fid))
 			return fid;
 
+		refcount_inc(&fid->count);
 		v9fs_fid_add(dentry->d_sb->s_root, fid);
 	}
 	/* If we are root ourself just return that */
-	if (dentry->d_sb->s_root == dentry) {
-		refcount_inc(&fid->count);
+	if (dentry->d_sb->s_root == dentry)
 		return fid;
-	}
 	/*
 	 * Do a multipath walk with attached root.
 	 * When walking parent we need to make sure we
@@ -212,6 +211,7 @@ static struct p9_fid *v9fs_fid_lookup_with_uid(struct dentry *dentry,
 		fid = ERR_PTR(n);
 		goto err_out;
 	}
+	old_fid = fid;
 	clone = 1;
 	i = 0;
 	while (i < n) {
@@ -221,19 +221,15 @@ static struct p9_fid *v9fs_fid_lookup_with_uid(struct dentry *dentry,
 		 * walk to ensure none of the patch component change
 		 */
 		fid = p9_client_walk(fid, l, &wnames[i], clone);
+		/* non-cloning walk will return the same fid */
+		if (fid != old_fid) {
+			p9_client_clunk(old_fid);
+			old_fid = fid;
+		}
 		if (IS_ERR(fid)) {
-			if (old_fid) {
-				/*
-				 * If we fail, clunk fid which are mapping
-				 * to path component and not the last component
-				 * of the path.
-				 */
-				p9_client_clunk(old_fid);
-			}
 			kfree(wnames);
 			goto err_out;
 		}
-		old_fid = fid;
 		i += l;
 		clone = 0;
 	}
-- 
GitLab


From 56315b6bf7fc63d2b26c37869d2753f765849bd6 Mon Sep 17 00:00:00 2001
From: Oleksij Rempel <o.rempel@pengutronix.de>
Date: Fri, 10 Jun 2022 10:16:21 +0200
Subject: [PATCH 0599/1731] ARM: dts: at91: ksz9477_evb: fix port/phy
 validation

Latest drivers version requires phy-mode to be set. Otherwise we will
use "NA" mode and the switch driver will invalidate this port mode.

Fixes: 65ac79e18120 ("net: dsa: microchip: add the phylink get_caps")
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Link: https://lore.kernel.org/r/20220610081621.584393-1-o.rempel@pengutronix.de
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts b/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts
index 443e8b0228977..14af1fd6d247d 100644
--- a/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts
+++ b/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts
@@ -120,26 +120,31 @@
 			port@0 {
 				reg = <0>;
 				label = "lan1";
+				phy-mode = "internal";
 			};
 
 			port@1 {
 				reg = <1>;
 				label = "lan2";
+				phy-mode = "internal";
 			};
 
 			port@2 {
 				reg = <2>;
 				label = "lan3";
+				phy-mode = "internal";
 			};
 
 			port@3 {
 				reg = <3>;
 				label = "lan4";
+				phy-mode = "internal";
 			};
 
 			port@4 {
 				reg = <4>;
 				label = "lan5";
+				phy-mode = "internal";
 			};
 
 			port@5 {
-- 
GitLab


From 56ec3e755bd1041d35bdec020a99b327697ee470 Mon Sep 17 00:00:00 2001
From: Takashi Iwai <tiwai@suse.de>
Date: Tue, 14 Jun 2022 07:48:31 +0200
Subject: [PATCH 0600/1731] ALSA: hda/realtek: Apply fixup for Lenovo Yoga Duet
 7 properly

It turned out that Lenovo shipped two completely different products
with the very same PCI SSID, where both require different quirks;
namely, Lenovo C940 has already the fixup for its speaker
(ALC298_FIXUP_LENOVO_SPK_VOLUME) with the PCI SSID 17aa:3818, while
Yoga Duet 7 has also the very same PCI SSID but requires a different
quirk, ALC287_FIXUP_YOGA7_14TIL_SPEAKERS.

Fortunately, both are with different codecs (C940 with ALC298 and Duet
7 with ALC287), hence we can apply different fixes by checking the
codec ID.  This patch implements that special fixup function.

For easier handling, the internal function for applying a specific
fixup entry is exported as __snd_hda_apply_fixup(), so that it can be
called from the codec driver.  The rest is simply calling it with a
different fixup ID depending on the codec ID.

Reported-by: Hans de Goede <hdegoede@redhat.com>
Tested-by: nikitashvets@flyium.com
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/5ca147d1-3a2d-60c6-c491-8aa844183222@redhat.com
Link: https://lore.kernel.org/r/20220614054831.14648-1-tiwai@suse.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/pci/hda/hda_auto_parser.c |  7 ++++---
 sound/pci/hda/hda_local.h       |  1 +
 sound/pci/hda/patch_realtek.c   | 24 +++++++++++++++++++++++-
 3 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/sound/pci/hda/hda_auto_parser.c b/sound/pci/hda/hda_auto_parser.c
index cd1db943b7e07..7c6b1fe8dfcce 100644
--- a/sound/pci/hda/hda_auto_parser.c
+++ b/sound/pci/hda/hda_auto_parser.c
@@ -819,7 +819,7 @@ static void set_pin_targets(struct hda_codec *codec,
 		snd_hda_set_pin_ctl_cache(codec, cfg->nid, cfg->val);
 }
 
-static void apply_fixup(struct hda_codec *codec, int id, int action, int depth)
+void __snd_hda_apply_fixup(struct hda_codec *codec, int id, int action, int depth)
 {
 	const char *modelname = codec->fixup_name;
 
@@ -829,7 +829,7 @@ static void apply_fixup(struct hda_codec *codec, int id, int action, int depth)
 		if (++depth > 10)
 			break;
 		if (fix->chained_before)
-			apply_fixup(codec, fix->chain_id, action, depth + 1);
+			__snd_hda_apply_fixup(codec, fix->chain_id, action, depth + 1);
 
 		switch (fix->type) {
 		case HDA_FIXUP_PINS:
@@ -870,6 +870,7 @@ static void apply_fixup(struct hda_codec *codec, int id, int action, int depth)
 		id = fix->chain_id;
 	}
 }
+EXPORT_SYMBOL_GPL(__snd_hda_apply_fixup);
 
 /**
  * snd_hda_apply_fixup - Apply the fixup chain with the given action
@@ -879,7 +880,7 @@ static void apply_fixup(struct hda_codec *codec, int id, int action, int depth)
 void snd_hda_apply_fixup(struct hda_codec *codec, int action)
 {
 	if (codec->fixup_list)
-		apply_fixup(codec, codec->fixup_id, action, 0);
+		__snd_hda_apply_fixup(codec, codec->fixup_id, action, 0);
 }
 EXPORT_SYMBOL_GPL(snd_hda_apply_fixup);
 
diff --git a/sound/pci/hda/hda_local.h b/sound/pci/hda/hda_local.h
index aca592651870e..682dca2057dbe 100644
--- a/sound/pci/hda/hda_local.h
+++ b/sound/pci/hda/hda_local.h
@@ -348,6 +348,7 @@ void snd_hda_apply_verbs(struct hda_codec *codec);
 void snd_hda_apply_pincfgs(struct hda_codec *codec,
 			   const struct hda_pintbl *cfg);
 void snd_hda_apply_fixup(struct hda_codec *codec, int action);
+void __snd_hda_apply_fixup(struct hda_codec *codec, int id, int action, int depth);
 void snd_hda_pick_fixup(struct hda_codec *codec,
 			const struct hda_model_fixup *models,
 			const struct snd_pci_quirk *quirk,
diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index 9b6ee775ee3ff..b937f63d0d09e 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -7004,6 +7004,7 @@ enum {
 	ALC287_FIXUP_LEGION_15IMHG05_SPEAKERS,
 	ALC287_FIXUP_LEGION_15IMHG05_AUTOMUTE,
 	ALC287_FIXUP_YOGA7_14ITL_SPEAKERS,
+	ALC298_FIXUP_LENOVO_C940_DUET7,
 	ALC287_FIXUP_13S_GEN2_SPEAKERS,
 	ALC256_FIXUP_SET_COEF_DEFAULTS,
 	ALC256_FIXUP_SYSTEM76_MIC_NO_PRESENCE,
@@ -7022,6 +7023,23 @@ enum {
 	ALC295_FIXUP_FRAMEWORK_LAPTOP_MIC_NO_PRESENCE,
 };
 
+/* A special fixup for Lenovo C940 and Yoga Duet 7;
+ * both have the very same PCI SSID, and we need to apply different fixups
+ * depending on the codec ID
+ */
+static void alc298_fixup_lenovo_c940_duet7(struct hda_codec *codec,
+					   const struct hda_fixup *fix,
+					   int action)
+{
+	int id;
+
+	if (codec->core.vendor_id == 0x10ec0298)
+		id = ALC298_FIXUP_LENOVO_SPK_VOLUME; /* C940 */
+	else
+		id = ALC287_FIXUP_YOGA7_14ITL_SPEAKERS; /* Duet 7 */
+	__snd_hda_apply_fixup(codec, id, action, 0);
+}
+
 static const struct hda_fixup alc269_fixups[] = {
 	[ALC269_FIXUP_GPIO2] = {
 		.type = HDA_FIXUP_FUNC,
@@ -8721,6 +8739,10 @@ static const struct hda_fixup alc269_fixups[] = {
 		.chained = true,
 		.chain_id = ALC269_FIXUP_HEADSET_MODE,
 	},
+	[ALC298_FIXUP_LENOVO_C940_DUET7] = {
+		.type = HDA_FIXUP_FUNC,
+		.v.func = alc298_fixup_lenovo_c940_duet7,
+	},
 	[ALC287_FIXUP_13S_GEN2_SPEAKERS] = {
 		.type = HDA_FIXUP_VERBS,
 		.v.verbs = (const struct hda_verb[]) {
@@ -9274,7 +9296,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
 	SND_PCI_QUIRK(0x17aa, 0x31af, "ThinkCentre Station", ALC623_FIXUP_LENOVO_THINKSTATION_P340),
 	SND_PCI_QUIRK(0x17aa, 0x3802, "Lenovo Yoga DuetITL 2021", ALC287_FIXUP_YOGA7_14ITL_SPEAKERS),
 	SND_PCI_QUIRK(0x17aa, 0x3813, "Legion 7i 15IMHG05", ALC287_FIXUP_LEGION_15IMHG05_SPEAKERS),
-	SND_PCI_QUIRK(0x17aa, 0x3818, "Lenovo C940", ALC298_FIXUP_LENOVO_SPK_VOLUME),
+	SND_PCI_QUIRK(0x17aa, 0x3818, "Lenovo C940 / Yoga Duet 7", ALC298_FIXUP_LENOVO_C940_DUET7),
 	SND_PCI_QUIRK(0x17aa, 0x3819, "Lenovo 13s Gen2 ITL", ALC287_FIXUP_13S_GEN2_SPEAKERS),
 	SND_PCI_QUIRK(0x17aa, 0x3820, "Yoga Duet 7 13ITL6", ALC287_FIXUP_YOGA7_14ITL_SPEAKERS),
 	SND_PCI_QUIRK(0x17aa, 0x3824, "Legion Y9000X 2020", ALC285_FIXUP_LEGION_Y9000X_SPEAKERS),
-- 
GitLab


From b60377de779052bf00b34a62f0bae03c92b88776 Mon Sep 17 00:00:00 2001
From: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Date: Mon, 13 Jun 2022 14:18:26 +0200
Subject: [PATCH 0601/1731] MAINTAINERS: add include/dt-bindings/net to
 NETWORKING DRIVERS

Maintainers of the directory Documentation/devicetree/bindings/net
are also the maintainers of the corresponding directory
include/dt-bindings/net.

Add the file entry for include/dt-bindings/net to the appropriate
section in MAINTAINERS.

Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Link: https://lore.kernel.org/r/20220613121826.11484-1-lukas.bulwahn@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 96158b337b407..0c3847fb2bbc7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13799,6 +13799,7 @@ T:	git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git
 F:	Documentation/devicetree/bindings/net/
 F:	drivers/connector/
 F:	drivers/net/
+F:	include/dt-bindings/net/
 F:	include/linux/etherdevice.h
 F:	include/linux/fcdevice.h
 F:	include/linux/fddidevice.h
-- 
GitLab


From 869968225718ec7d77c418e2f6be996206d0428e Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Fri, 10 Jun 2022 17:10:25 +0300
Subject: [PATCH 0602/1731] drm/i915/bios: use dvi and hdmi support helpers
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Improve clarity by using the helpers we have.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/3a0b52593f19a465dc0dd898db5f6bf13537d734.1654870175.git.jani.nikula@intel.com
---
 drivers/gpu/drm/i915/display/intel_bios.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index b165feb593ab1..1b1cf250a377a 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2471,10 +2471,10 @@ static void sanitize_device_type(struct intel_bios_encoder_data *devdata,
 	if (port != PORT_A || DISPLAY_VER(i915) >= 12)
 		return;
 
-	if (!(devdata->child.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING))
+	if (!intel_bios_encoder_supports_dvi(devdata))
 		return;
 
-	is_hdmi = !(devdata->child.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT);
+	is_hdmi = intel_bios_encoder_supports_hdmi(devdata);
 
 	drm_dbg_kms(&i915->drm, "VBT claims port A supports DVI%s, ignoring\n",
 		    is_hdmi ? "/HDMI" : "");
-- 
GitLab


From c78783f3227f41053e9a44f536d13f05383b875a Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Fri, 10 Jun 2022 17:10:26 +0300
Subject: [PATCH 0603/1731] drm/i915/bios: no need to pass i915 to
 parse_ddi_port()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

i915 is available via devdata, grab it there instead of passing.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/45c97c93bb9262c08aefa7b4bfe31f3f3481c998.1654870175.git.jani.nikula@intel.com
---
 drivers/gpu/drm/i915/display/intel_bios.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 1b1cf250a377a..a6ceff1819772 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2560,9 +2560,9 @@ static bool is_port_valid(struct drm_i915_private *i915, enum port port)
 	return true;
 }
 
-static void parse_ddi_port(struct drm_i915_private *i915,
-			   struct intel_bios_encoder_data *devdata)
+static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
 {
+	struct drm_i915_private *i915 = devdata->i915;
 	const struct child_device_config *child = &devdata->child;
 	bool is_dvi, is_hdmi, is_dp, is_edp, is_crt, supports_typec_usb, supports_tbt;
 	int dp_boost_level, dp_max_link_rate, hdmi_boost_level, hdmi_level_shift, max_tmds_clock;
@@ -2658,7 +2658,7 @@ static void parse_ddi_ports(struct drm_i915_private *i915)
 		return;
 
 	list_for_each_entry(devdata, &i915->vbt.display_devices, node)
-		parse_ddi_port(i915, devdata);
+		parse_ddi_port(devdata);
 }
 
 static void
-- 
GitLab


From 8d2ba05b099aedfcece0326a5bbb2e7cc33261ae Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Fri, 10 Jun 2022 17:10:27 +0300
Subject: [PATCH 0604/1731] drm/i915/bios: split ddi port parsing and debug
 printing
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Split ddi port parsing and debug printing to clarify the functional
parts of parse_ddi_port(), which are quite small nowadays.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/34e0dd92b7f7e9076df1f01b542347e599ec6653.1654870175.git.jani.nikula@intel.com
---
 drivers/gpu/drm/i915/display/intel_bios.c | 65 +++++++++++++----------
 1 file changed, 37 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index a6ceff1819772..64ee418c0c5d5 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2560,33 +2560,13 @@ static bool is_port_valid(struct drm_i915_private *i915, enum port port)
 	return true;
 }
 
-static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
+static void print_ddi_port(const struct intel_bios_encoder_data *devdata,
+			   enum port port)
 {
 	struct drm_i915_private *i915 = devdata->i915;
 	const struct child_device_config *child = &devdata->child;
 	bool is_dvi, is_hdmi, is_dp, is_edp, is_crt, supports_typec_usb, supports_tbt;
 	int dp_boost_level, dp_max_link_rate, hdmi_boost_level, hdmi_level_shift, max_tmds_clock;
-	enum port port;
-
-	port = dvo_port_to_port(i915, child->dvo_port);
-	if (port == PORT_NONE)
-		return;
-
-	if (!is_port_valid(i915, port)) {
-		drm_dbg_kms(&i915->drm,
-			    "VBT reports port %c as supported, but that can't be true: skipping\n",
-			    port_name(port));
-		return;
-	}
-
-	if (i915->vbt.ports[port]) {
-		drm_dbg_kms(&i915->drm,
-			    "More than one child device for port %c in VBT, using the first.\n",
-			    port_name(port));
-		return;
-	}
-
-	sanitize_device_type(devdata, port);
 
 	is_dvi = intel_bios_encoder_supports_dvi(devdata);
 	is_dp = intel_bios_encoder_supports_dp(devdata);
@@ -2604,12 +2584,6 @@ static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
 		    supports_typec_usb, supports_tbt,
 		    devdata->dsc != NULL);
 
-	if (is_dvi)
-		sanitize_ddc_pin(devdata, port);
-
-	if (is_dp)
-		sanitize_aux_ch(devdata, port);
-
 	hdmi_level_shift = _intel_bios_hdmi_level_shift(devdata);
 	if (hdmi_level_shift >= 0) {
 		drm_dbg_kms(&i915->drm,
@@ -2641,6 +2615,41 @@ static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
 		drm_dbg_kms(&i915->drm,
 			    "Port %c VBT DP max link rate: %d\n",
 			    port_name(port), dp_max_link_rate);
+}
+
+static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
+{
+	struct drm_i915_private *i915 = devdata->i915;
+	const struct child_device_config *child = &devdata->child;
+	enum port port;
+
+	port = dvo_port_to_port(i915, child->dvo_port);
+	if (port == PORT_NONE)
+		return;
+
+	if (!is_port_valid(i915, port)) {
+		drm_dbg_kms(&i915->drm,
+			    "VBT reports port %c as supported, but that can't be true: skipping\n",
+			    port_name(port));
+		return;
+	}
+
+	if (i915->vbt.ports[port]) {
+		drm_dbg_kms(&i915->drm,
+			    "More than one child device for port %c in VBT, using the first.\n",
+			    port_name(port));
+		return;
+	}
+
+	sanitize_device_type(devdata, port);
+
+	print_ddi_port(devdata, port);
+
+	if (intel_bios_encoder_supports_dvi(devdata))
+		sanitize_ddc_pin(devdata, port);
+
+	if (intel_bios_encoder_supports_dp(devdata))
+		sanitize_aux_ch(devdata, port);
 
 	i915->vbt.ports[port] = devdata;
 }
-- 
GitLab


From 36a15e1cb134c0395261ba1940762703f778438c Mon Sep 17 00:00:00 2001
From: Jose Alonso <joalonsof@gmail.com>
Date: Mon, 13 Jun 2022 15:32:44 -0300
Subject: [PATCH 0605/1731] net: usb: ax88179_178a needs FLAG_SEND_ZLP

The extra byte inserted by usbnet.c when
 (length % dev->maxpacket == 0) is causing problems to device.

This patch sets FLAG_SEND_ZLP to avoid this.

Tested with: 0b95:1790 ASIX Electronics Corp. AX88179 Gigabit Ethernet

Problems observed:
======================================================================
1) Using ssh/sshfs. The remote sshd daemon can abort with the message:
   "message authentication code incorrect"
   This happens because the tcp message sent is corrupted during the
   USB "Bulk out". The device calculate the tcp checksum and send a
   valid tcp message to the remote sshd. Then the encryption detects
   the error and aborts.
2) NETDEV WATCHDOG: ... (ax88179_178a): transmit queue 0 timed out
3) Stop normal work without any log message.
   The "Bulk in" continue receiving packets normally.
   The host sends "Bulk out" and the device responds with -ECONNRESET.
   (The netusb.c code tx_complete ignore -ECONNRESET)
Under normal conditions these errors take days to happen and in
intense usage take hours.

A test with ping gives packet loss, showing that something is wrong:
ping -4 -s 462 {destination}	# 462 = 512 - 42 - 8
Not all packets fail.
My guess is that the device tries to find another packet starting
at the extra byte and will fail or not depending on the next
bytes (old buffer content).
======================================================================

Signed-off-by: Jose Alonso <joalonsof@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/usb/ax88179_178a.c | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/net/usb/ax88179_178a.c b/drivers/net/usb/ax88179_178a.c
index 7a8c11a26eb5f..4704ed6f00efe 100644
--- a/drivers/net/usb/ax88179_178a.c
+++ b/drivers/net/usb/ax88179_178a.c
@@ -1750,7 +1750,7 @@ static const struct driver_info ax88179_info = {
 	.link_reset = ax88179_link_reset,
 	.reset = ax88179_reset,
 	.stop = ax88179_stop,
-	.flags = FLAG_ETHER | FLAG_FRAMING_AX,
+	.flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_SEND_ZLP,
 	.rx_fixup = ax88179_rx_fixup,
 	.tx_fixup = ax88179_tx_fixup,
 };
@@ -1763,7 +1763,7 @@ static const struct driver_info ax88178a_info = {
 	.link_reset = ax88179_link_reset,
 	.reset = ax88179_reset,
 	.stop = ax88179_stop,
-	.flags = FLAG_ETHER | FLAG_FRAMING_AX,
+	.flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_SEND_ZLP,
 	.rx_fixup = ax88179_rx_fixup,
 	.tx_fixup = ax88179_tx_fixup,
 };
@@ -1776,7 +1776,7 @@ static const struct driver_info cypress_GX3_info = {
 	.link_reset = ax88179_link_reset,
 	.reset = ax88179_reset,
 	.stop = ax88179_stop,
-	.flags = FLAG_ETHER | FLAG_FRAMING_AX,
+	.flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_SEND_ZLP,
 	.rx_fixup = ax88179_rx_fixup,
 	.tx_fixup = ax88179_tx_fixup,
 };
@@ -1789,7 +1789,7 @@ static const struct driver_info dlink_dub1312_info = {
 	.link_reset = ax88179_link_reset,
 	.reset = ax88179_reset,
 	.stop = ax88179_stop,
-	.flags = FLAG_ETHER | FLAG_FRAMING_AX,
+	.flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_SEND_ZLP,
 	.rx_fixup = ax88179_rx_fixup,
 	.tx_fixup = ax88179_tx_fixup,
 };
@@ -1802,7 +1802,7 @@ static const struct driver_info sitecom_info = {
 	.link_reset = ax88179_link_reset,
 	.reset = ax88179_reset,
 	.stop = ax88179_stop,
-	.flags = FLAG_ETHER | FLAG_FRAMING_AX,
+	.flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_SEND_ZLP,
 	.rx_fixup = ax88179_rx_fixup,
 	.tx_fixup = ax88179_tx_fixup,
 };
@@ -1815,7 +1815,7 @@ static const struct driver_info samsung_info = {
 	.link_reset = ax88179_link_reset,
 	.reset = ax88179_reset,
 	.stop = ax88179_stop,
-	.flags = FLAG_ETHER | FLAG_FRAMING_AX,
+	.flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_SEND_ZLP,
 	.rx_fixup = ax88179_rx_fixup,
 	.tx_fixup = ax88179_tx_fixup,
 };
@@ -1828,7 +1828,7 @@ static const struct driver_info lenovo_info = {
 	.link_reset = ax88179_link_reset,
 	.reset = ax88179_reset,
 	.stop = ax88179_stop,
-	.flags = FLAG_ETHER | FLAG_FRAMING_AX,
+	.flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_SEND_ZLP,
 	.rx_fixup = ax88179_rx_fixup,
 	.tx_fixup = ax88179_tx_fixup,
 };
@@ -1841,7 +1841,7 @@ static const struct driver_info belkin_info = {
 	.link_reset = ax88179_link_reset,
 	.reset	= ax88179_reset,
 	.stop	= ax88179_stop,
-	.flags	= FLAG_ETHER | FLAG_FRAMING_AX,
+	.flags	= FLAG_ETHER | FLAG_FRAMING_AX | FLAG_SEND_ZLP,
 	.rx_fixup = ax88179_rx_fixup,
 	.tx_fixup = ax88179_tx_fixup,
 };
@@ -1854,7 +1854,7 @@ static const struct driver_info toshiba_info = {
 	.link_reset = ax88179_link_reset,
 	.reset	= ax88179_reset,
 	.stop = ax88179_stop,
-	.flags	= FLAG_ETHER | FLAG_FRAMING_AX,
+	.flags	= FLAG_ETHER | FLAG_FRAMING_AX | FLAG_SEND_ZLP,
 	.rx_fixup = ax88179_rx_fixup,
 	.tx_fixup = ax88179_tx_fixup,
 };
@@ -1867,7 +1867,7 @@ static const struct driver_info mct_info = {
 	.link_reset = ax88179_link_reset,
 	.reset	= ax88179_reset,
 	.stop	= ax88179_stop,
-	.flags	= FLAG_ETHER | FLAG_FRAMING_AX,
+	.flags	= FLAG_ETHER | FLAG_FRAMING_AX | FLAG_SEND_ZLP,
 	.rx_fixup = ax88179_rx_fixup,
 	.tx_fixup = ax88179_tx_fixup,
 };
@@ -1880,7 +1880,7 @@ static const struct driver_info at_umc2000_info = {
 	.link_reset = ax88179_link_reset,
 	.reset  = ax88179_reset,
 	.stop   = ax88179_stop,
-	.flags  = FLAG_ETHER | FLAG_FRAMING_AX,
+	.flags  = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_SEND_ZLP,
 	.rx_fixup = ax88179_rx_fixup,
 	.tx_fixup = ax88179_tx_fixup,
 };
@@ -1893,7 +1893,7 @@ static const struct driver_info at_umc200_info = {
 	.link_reset = ax88179_link_reset,
 	.reset  = ax88179_reset,
 	.stop   = ax88179_stop,
-	.flags  = FLAG_ETHER | FLAG_FRAMING_AX,
+	.flags  = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_SEND_ZLP,
 	.rx_fixup = ax88179_rx_fixup,
 	.tx_fixup = ax88179_tx_fixup,
 };
@@ -1906,7 +1906,7 @@ static const struct driver_info at_umc2000sp_info = {
 	.link_reset = ax88179_link_reset,
 	.reset  = ax88179_reset,
 	.stop   = ax88179_stop,
-	.flags  = FLAG_ETHER | FLAG_FRAMING_AX,
+	.flags  = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_SEND_ZLP,
 	.rx_fixup = ax88179_rx_fixup,
 	.tx_fixup = ax88179_tx_fixup,
 };
-- 
GitLab


From 91ef75a7db0d0855284b78d60d3fcec5c353ec5a Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Wed, 15 Jun 2022 11:23:02 +0100
Subject: [PATCH 0606/1731] io_uring: get rid of __io_fill_cqe{32}_req()

There are too many cqe filling helpers, kill __io_fill_cqe{32}_req(),
use __io_fill_cqe{32}_req_filled() instead, and then rename it. It'll
simplify fixing in following patches.

Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
Link: https://lore.kernel.org/r/c18e0d191014fb574f24721245e4e3fddd0b6917.1655287457.git.asml.silence@gmail.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 70 ++++++++++++++++-----------------------------------
 1 file changed, 21 insertions(+), 49 deletions(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index 1b0b6099e7174..654c2f897497d 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -2464,8 +2464,8 @@ static inline bool __io_fill_cqe(struct io_ring_ctx *ctx, u64 user_data,
 	return io_cqring_event_overflow(ctx, user_data, res, cflags, 0, 0);
 }
 
-static inline bool __io_fill_cqe_req_filled(struct io_ring_ctx *ctx,
-					    struct io_kiocb *req)
+static inline bool __io_fill_cqe_req(struct io_ring_ctx *ctx,
+				     struct io_kiocb *req)
 {
 	struct io_uring_cqe *cqe;
 
@@ -2486,8 +2486,8 @@ static inline bool __io_fill_cqe_req_filled(struct io_ring_ctx *ctx,
 					req->cqe.res, req->cqe.flags, 0, 0);
 }
 
-static inline bool __io_fill_cqe32_req_filled(struct io_ring_ctx *ctx,
-					      struct io_kiocb *req)
+static inline bool __io_fill_cqe32_req(struct io_ring_ctx *ctx,
+				       struct io_kiocb *req)
 {
 	struct io_uring_cqe *cqe;
 	u64 extra1 = req->extra1;
@@ -2513,44 +2513,6 @@ static inline bool __io_fill_cqe32_req_filled(struct io_ring_ctx *ctx,
 					req->cqe.flags, extra1, extra2);
 }
 
-static inline bool __io_fill_cqe_req(struct io_kiocb *req, s32 res, u32 cflags)
-{
-	trace_io_uring_complete(req->ctx, req, req->cqe.user_data, res, cflags, 0, 0);
-	return __io_fill_cqe(req->ctx, req->cqe.user_data, res, cflags);
-}
-
-static inline void __io_fill_cqe32_req(struct io_kiocb *req, s32 res, u32 cflags,
-				u64 extra1, u64 extra2)
-{
-	struct io_ring_ctx *ctx = req->ctx;
-	struct io_uring_cqe *cqe;
-
-	if (WARN_ON_ONCE(!(ctx->flags & IORING_SETUP_CQE32)))
-		return;
-	if (req->flags & REQ_F_CQE_SKIP)
-		return;
-
-	trace_io_uring_complete(ctx, req, req->cqe.user_data, res, cflags,
-				extra1, extra2);
-
-	/*
-	 * If we can't get a cq entry, userspace overflowed the
-	 * submission (by quite a lot). Increment the overflow count in
-	 * the ring.
-	 */
-	cqe = io_get_cqe(ctx);
-	if (likely(cqe)) {
-		WRITE_ONCE(cqe->user_data, req->cqe.user_data);
-		WRITE_ONCE(cqe->res, res);
-		WRITE_ONCE(cqe->flags, cflags);
-		WRITE_ONCE(cqe->big_cqe[0], extra1);
-		WRITE_ONCE(cqe->big_cqe[1], extra2);
-		return;
-	}
-
-	io_cqring_event_overflow(ctx, req->cqe.user_data, res, cflags, extra1, extra2);
-}
-
 static noinline bool io_fill_cqe_aux(struct io_ring_ctx *ctx, u64 user_data,
 				     s32 res, u32 cflags)
 {
@@ -2593,16 +2555,24 @@ static void __io_req_complete_put(struct io_kiocb *req)
 static void __io_req_complete_post(struct io_kiocb *req, s32 res,
 				   u32 cflags)
 {
-	if (!(req->flags & REQ_F_CQE_SKIP))
-		__io_fill_cqe_req(req, res, cflags);
+	if (!(req->flags & REQ_F_CQE_SKIP)) {
+		req->cqe.res = res;
+		req->cqe.flags = cflags;
+		__io_fill_cqe_req(req->ctx, req);
+	}
 	__io_req_complete_put(req);
 }
 
 static void __io_req_complete_post32(struct io_kiocb *req, s32 res,
 				   u32 cflags, u64 extra1, u64 extra2)
 {
-	if (!(req->flags & REQ_F_CQE_SKIP))
-		__io_fill_cqe32_req(req, res, cflags, extra1, extra2);
+	if (!(req->flags & REQ_F_CQE_SKIP)) {
+		req->cqe.res = res;
+		req->cqe.flags = cflags;
+		req->extra1 = extra1;
+		req->extra2 = extra2;
+		__io_fill_cqe32_req(req->ctx, req);
+	}
 	__io_req_complete_put(req);
 }
 
@@ -3207,9 +3177,9 @@ static void __io_submit_flush_completions(struct io_ring_ctx *ctx)
 
 			if (!(req->flags & REQ_F_CQE_SKIP)) {
 				if (!(ctx->flags & IORING_SETUP_CQE32))
-					__io_fill_cqe_req_filled(ctx, req);
+					__io_fill_cqe_req(ctx, req);
 				else
-					__io_fill_cqe32_req_filled(ctx, req);
+					__io_fill_cqe32_req(ctx, req);
 			}
 		}
 
@@ -3329,7 +3299,9 @@ static int io_do_iopoll(struct io_ring_ctx *ctx, bool force_nonspin)
 		nr_events++;
 		if (unlikely(req->flags & REQ_F_CQE_SKIP))
 			continue;
-		__io_fill_cqe_req(req, req->cqe.res, io_put_kbuf(req, 0));
+
+		req->cqe.flags = io_put_kbuf(req, 0);
+		__io_fill_cqe_req(req->ctx, req);
 	}
 
 	if (unlikely(!nr_events))
-- 
GitLab


From f43de1f88841d59f27f761219b6550bd6ce3dcc1 Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Wed, 15 Jun 2022 11:23:03 +0100
Subject: [PATCH 0607/1731] io_uring: unite fill_cqe and the 32B version

We want just one function that will handle both normal cqes and 32B
cqes. Combine __io_fill_cqe_req() and __io_fill_cqe_req32(). It's still
not entirely correct yet, but saves us from cases when we fill an CQE of
a wrong size.

Fixes: 76c68fbf1a1f9 ("io_uring: enable CQE32")
Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
Link: https://lore.kernel.org/r/8085c5b2f74141520f60decd45334f87e389b718.1655287457.git.asml.silence@gmail.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 61 +++++++++++++++++++++++++++++++++++----------------
 1 file changed, 42 insertions(+), 19 deletions(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index 654c2f897497d..eb858cf92af94 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -2469,21 +2469,48 @@ static inline bool __io_fill_cqe_req(struct io_ring_ctx *ctx,
 {
 	struct io_uring_cqe *cqe;
 
-	trace_io_uring_complete(req->ctx, req, req->cqe.user_data,
-				req->cqe.res, req->cqe.flags, 0, 0);
+	if (!(ctx->flags & IORING_SETUP_CQE32)) {
+		trace_io_uring_complete(req->ctx, req, req->cqe.user_data,
+					req->cqe.res, req->cqe.flags, 0, 0);
 
-	/*
-	 * If we can't get a cq entry, userspace overflowed the
-	 * submission (by quite a lot). Increment the overflow count in
-	 * the ring.
-	 */
-	cqe = io_get_cqe(ctx);
-	if (likely(cqe)) {
-		memcpy(cqe, &req->cqe, sizeof(*cqe));
-		return true;
+		/*
+		 * If we can't get a cq entry, userspace overflowed the
+		 * submission (by quite a lot). Increment the overflow count in
+		 * the ring.
+		 */
+		cqe = io_get_cqe(ctx);
+		if (likely(cqe)) {
+			memcpy(cqe, &req->cqe, sizeof(*cqe));
+			return true;
+		}
+
+		return io_cqring_event_overflow(ctx, req->cqe.user_data,
+						req->cqe.res, req->cqe.flags,
+						0, 0);
+	} else {
+		u64 extra1 = req->extra1;
+		u64 extra2 = req->extra2;
+
+		trace_io_uring_complete(req->ctx, req, req->cqe.user_data,
+					req->cqe.res, req->cqe.flags, extra1, extra2);
+
+		/*
+		 * If we can't get a cq entry, userspace overflowed the
+		 * submission (by quite a lot). Increment the overflow count in
+		 * the ring.
+		 */
+		cqe = io_get_cqe(ctx);
+		if (likely(cqe)) {
+			memcpy(cqe, &req->cqe, sizeof(struct io_uring_cqe));
+			WRITE_ONCE(cqe->big_cqe[0], extra1);
+			WRITE_ONCE(cqe->big_cqe[1], extra2);
+			return true;
+		}
+
+		return io_cqring_event_overflow(ctx, req->cqe.user_data,
+				req->cqe.res, req->cqe.flags,
+				extra1, extra2);
 	}
-	return io_cqring_event_overflow(ctx, req->cqe.user_data,
-					req->cqe.res, req->cqe.flags, 0, 0);
 }
 
 static inline bool __io_fill_cqe32_req(struct io_ring_ctx *ctx,
@@ -3175,12 +3202,8 @@ static void __io_submit_flush_completions(struct io_ring_ctx *ctx)
 			struct io_kiocb *req = container_of(node, struct io_kiocb,
 						    comp_list);
 
-			if (!(req->flags & REQ_F_CQE_SKIP)) {
-				if (!(ctx->flags & IORING_SETUP_CQE32))
-					__io_fill_cqe_req(ctx, req);
-				else
-					__io_fill_cqe32_req(ctx, req);
-			}
+			if (!(req->flags & REQ_F_CQE_SKIP))
+				__io_fill_cqe_req(ctx, req);
 		}
 
 		io_commit_cqring(ctx);
-- 
GitLab


From 29ede2014c87576d2fc83680aa4c1d7403db0dfe Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Wed, 15 Jun 2022 11:23:04 +0100
Subject: [PATCH 0608/1731] io_uring: fill extra big cqe fields from req

The only user of io_req_complete32()-like functions is cmd
requests. Instead of keeping the whole complete32 family, remove them
and provide the extras in already added for inline completions
req->extra{1,2}. When fill_cqe_res() finds CQE32 option enabled
it'll use those fields to fill a 32B cqe.

Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
Link: https://lore.kernel.org/r/af1319eb661b1f9a0abceb51cbbf72b8002e019d.1655287457.git.asml.silence@gmail.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 78 +++++++--------------------------------------------
 1 file changed, 10 insertions(+), 68 deletions(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index eb858cf92af94..10901db93f7ee 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -2513,33 +2513,6 @@ static inline bool __io_fill_cqe_req(struct io_ring_ctx *ctx,
 	}
 }
 
-static inline bool __io_fill_cqe32_req(struct io_ring_ctx *ctx,
-				       struct io_kiocb *req)
-{
-	struct io_uring_cqe *cqe;
-	u64 extra1 = req->extra1;
-	u64 extra2 = req->extra2;
-
-	trace_io_uring_complete(req->ctx, req, req->cqe.user_data,
-				req->cqe.res, req->cqe.flags, extra1, extra2);
-
-	/*
-	 * If we can't get a cq entry, userspace overflowed the
-	 * submission (by quite a lot). Increment the overflow count in
-	 * the ring.
-	 */
-	cqe = io_get_cqe(ctx);
-	if (likely(cqe)) {
-		memcpy(cqe, &req->cqe, sizeof(struct io_uring_cqe));
-		cqe->big_cqe[0] = extra1;
-		cqe->big_cqe[1] = extra2;
-		return true;
-	}
-
-	return io_cqring_event_overflow(ctx, req->cqe.user_data, req->cqe.res,
-					req->cqe.flags, extra1, extra2);
-}
-
 static noinline bool io_fill_cqe_aux(struct io_ring_ctx *ctx, u64 user_data,
 				     s32 res, u32 cflags)
 {
@@ -2590,19 +2563,6 @@ static void __io_req_complete_post(struct io_kiocb *req, s32 res,
 	__io_req_complete_put(req);
 }
 
-static void __io_req_complete_post32(struct io_kiocb *req, s32 res,
-				   u32 cflags, u64 extra1, u64 extra2)
-{
-	if (!(req->flags & REQ_F_CQE_SKIP)) {
-		req->cqe.res = res;
-		req->cqe.flags = cflags;
-		req->extra1 = extra1;
-		req->extra2 = extra2;
-		__io_fill_cqe32_req(req->ctx, req);
-	}
-	__io_req_complete_put(req);
-}
-
 static void io_req_complete_post(struct io_kiocb *req, s32 res, u32 cflags)
 {
 	struct io_ring_ctx *ctx = req->ctx;
@@ -2614,18 +2574,6 @@ static void io_req_complete_post(struct io_kiocb *req, s32 res, u32 cflags)
 	io_cqring_ev_posted(ctx);
 }
 
-static void io_req_complete_post32(struct io_kiocb *req, s32 res,
-				   u32 cflags, u64 extra1, u64 extra2)
-{
-	struct io_ring_ctx *ctx = req->ctx;
-
-	spin_lock(&ctx->completion_lock);
-	__io_req_complete_post32(req, res, cflags, extra1, extra2);
-	io_commit_cqring(ctx);
-	spin_unlock(&ctx->completion_lock);
-	io_cqring_ev_posted(ctx);
-}
-
 static inline void io_req_complete_state(struct io_kiocb *req, s32 res,
 					 u32 cflags)
 {
@@ -2643,19 +2591,6 @@ static inline void __io_req_complete(struct io_kiocb *req, unsigned issue_flags,
 		io_req_complete_post(req, res, cflags);
 }
 
-static inline void __io_req_complete32(struct io_kiocb *req,
-				       unsigned int issue_flags, s32 res,
-				       u32 cflags, u64 extra1, u64 extra2)
-{
-	if (issue_flags & IO_URING_F_COMPLETE_DEFER) {
-		io_req_complete_state(req, res, cflags);
-		req->extra1 = extra1;
-		req->extra2 = extra2;
-	} else {
-		io_req_complete_post32(req, res, cflags, extra1, extra2);
-	}
-}
-
 static inline void io_req_complete(struct io_kiocb *req, s32 res)
 {
 	if (res < 0)
@@ -5079,6 +5014,13 @@ void io_uring_cmd_complete_in_task(struct io_uring_cmd *ioucmd,
 }
 EXPORT_SYMBOL_GPL(io_uring_cmd_complete_in_task);
 
+static inline void io_req_set_cqe32_extra(struct io_kiocb *req,
+					  u64 extra1, u64 extra2)
+{
+	req->extra1 = extra1;
+	req->extra2 = extra2;
+}
+
 /*
  * Called by consumers of io_uring_cmd, if they originally returned
  * -EIOCBQUEUED upon receiving the command.
@@ -5089,10 +5031,10 @@ void io_uring_cmd_done(struct io_uring_cmd *ioucmd, ssize_t ret, ssize_t res2)
 
 	if (ret < 0)
 		req_set_fail(req);
+
 	if (req->ctx->flags & IORING_SETUP_CQE32)
-		__io_req_complete32(req, 0, ret, 0, res2, 0);
-	else
-		io_req_complete(req, ret);
+		io_req_set_cqe32_extra(req, res2, 0);
+	io_req_complete(req, ret);
 }
 EXPORT_SYMBOL_GPL(io_uring_cmd_done);
 
-- 
GitLab


From 2caf9822f0507463168a9e83f93c75b3e3fac971 Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Wed, 15 Jun 2022 11:23:05 +0100
Subject: [PATCH 0609/1731] io_uring: fix ->extra{1,2} misuse

We don't really know the state of req->extra{1,2] fields in
__io_fill_cqe_req(), if an opcode handler is not aware of CQE32 option,
it never sets them up properly. Track the state of those fields with a
request flag.

Fixes: 76c68fbf1a1f9 ("io_uring: enable CQE32")
Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
Link: https://lore.kernel.org/r/4b3e5be512fbf4debec7270fd485b8a3b014d464.1655287457.git.asml.silence@gmail.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index 10901db93f7ee..808b7f4ace0ba 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -844,6 +844,7 @@ enum {
 	REQ_F_SINGLE_POLL_BIT,
 	REQ_F_DOUBLE_POLL_BIT,
 	REQ_F_PARTIAL_IO_BIT,
+	REQ_F_CQE32_INIT_BIT,
 	REQ_F_APOLL_MULTISHOT_BIT,
 	/* keep async read/write and isreg together and in order */
 	REQ_F_SUPPORT_NOWAIT_BIT,
@@ -913,6 +914,8 @@ enum {
 	REQ_F_PARTIAL_IO	= BIT(REQ_F_PARTIAL_IO_BIT),
 	/* fast poll multishot mode */
 	REQ_F_APOLL_MULTISHOT	= BIT(REQ_F_APOLL_MULTISHOT_BIT),
+	/* ->extra1 and ->extra2 are initialised */
+	REQ_F_CQE32_INIT	= BIT(REQ_F_CQE32_INIT_BIT),
 };
 
 struct async_poll {
@@ -2488,8 +2491,12 @@ static inline bool __io_fill_cqe_req(struct io_ring_ctx *ctx,
 						req->cqe.res, req->cqe.flags,
 						0, 0);
 	} else {
-		u64 extra1 = req->extra1;
-		u64 extra2 = req->extra2;
+		u64 extra1 = 0, extra2 = 0;
+
+		if (req->flags & REQ_F_CQE32_INIT) {
+			extra1 = req->extra1;
+			extra2 = req->extra2;
+		}
 
 		trace_io_uring_complete(req->ctx, req, req->cqe.user_data,
 					req->cqe.res, req->cqe.flags, extra1, extra2);
@@ -5019,6 +5026,7 @@ static inline void io_req_set_cqe32_extra(struct io_kiocb *req,
 {
 	req->extra1 = extra1;
 	req->extra2 = extra2;
+	req->flags |= REQ_F_CQE32_INIT;
 }
 
 /*
-- 
GitLab


From cd94903d3ba50d7ae797c603f68996af8d1ba1a1 Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Wed, 15 Jun 2022 11:23:06 +0100
Subject: [PATCH 0610/1731] io_uring: remove __io_fill_cqe() helper

In preparation for the following patch, inline __io_fill_cqe(), there is
only one user.

Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
Link: https://lore.kernel.org/r/71dab9afc3cde3f8b64d26f20d3b60bdc40726ff.1655287457.git.asml.silence@gmail.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 37 ++++++++++++++++---------------------
 1 file changed, 16 insertions(+), 21 deletions(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index 808b7f4ace0ba..792e9c95d2176 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -2447,26 +2447,6 @@ static bool io_cqring_event_overflow(struct io_ring_ctx *ctx, u64 user_data,
 	return true;
 }
 
-static inline bool __io_fill_cqe(struct io_ring_ctx *ctx, u64 user_data,
-				 s32 res, u32 cflags)
-{
-	struct io_uring_cqe *cqe;
-
-	/*
-	 * If we can't get a cq entry, userspace overflowed the
-	 * submission (by quite a lot). Increment the overflow count in
-	 * the ring.
-	 */
-	cqe = io_get_cqe(ctx);
-	if (likely(cqe)) {
-		WRITE_ONCE(cqe->user_data, user_data);
-		WRITE_ONCE(cqe->res, res);
-		WRITE_ONCE(cqe->flags, cflags);
-		return true;
-	}
-	return io_cqring_event_overflow(ctx, user_data, res, cflags, 0, 0);
-}
-
 static inline bool __io_fill_cqe_req(struct io_ring_ctx *ctx,
 				     struct io_kiocb *req)
 {
@@ -2523,9 +2503,24 @@ static inline bool __io_fill_cqe_req(struct io_ring_ctx *ctx,
 static noinline bool io_fill_cqe_aux(struct io_ring_ctx *ctx, u64 user_data,
 				     s32 res, u32 cflags)
 {
+	struct io_uring_cqe *cqe;
+
 	ctx->cq_extra++;
 	trace_io_uring_complete(ctx, NULL, user_data, res, cflags, 0, 0);
-	return __io_fill_cqe(ctx, user_data, res, cflags);
+
+	/*
+	 * If we can't get a cq entry, userspace overflowed the
+	 * submission (by quite a lot). Increment the overflow count in
+	 * the ring.
+	 */
+	cqe = io_get_cqe(ctx);
+	if (likely(cqe)) {
+		WRITE_ONCE(cqe->user_data, user_data);
+		WRITE_ONCE(cqe->res, res);
+		WRITE_ONCE(cqe->flags, cflags);
+		return true;
+	}
+	return io_cqring_event_overflow(ctx, user_data, res, cflags, 0, 0);
 }
 
 static void __io_req_complete_put(struct io_kiocb *req)
-- 
GitLab


From c5595975b53a487bf329eeba65b5c5f34605a4c0 Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Wed, 15 Jun 2022 11:23:07 +0100
Subject: [PATCH 0611/1731] io_uring: make io_fill_cqe_aux honour CQE32

Don't let io_fill_cqe_aux() post 16B cqes for CQE32 rings, neither the
kernel nor the userspace expect this to happen.

Fixes: 76c68fbf1a1f9 ("io_uring: enable CQE32")
Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
Link: https://lore.kernel.org/r/64fae669fae1b7083aa15d0cd807f692b0880b9a.1655287457.git.asml.silence@gmail.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index 792e9c95d2176..5d479428d8e52 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -2518,6 +2518,11 @@ static noinline bool io_fill_cqe_aux(struct io_ring_ctx *ctx, u64 user_data,
 		WRITE_ONCE(cqe->user_data, user_data);
 		WRITE_ONCE(cqe->res, res);
 		WRITE_ONCE(cqe->flags, cflags);
+
+		if (ctx->flags & IORING_SETUP_CQE32) {
+			WRITE_ONCE(cqe->big_cqe[0], 0);
+			WRITE_ONCE(cqe->big_cqe[1], 0);
+		}
 		return true;
 	}
 	return io_cqring_event_overflow(ctx, user_data, res, cflags, 0, 0);
-- 
GitLab


From 219b51a6f040fa5367adadd7d58c4dda0896a01d Mon Sep 17 00:00:00 2001
From: Duoming Zhou <duoming@zju.edu.cn>
Date: Tue, 14 Jun 2022 17:25:57 +0800
Subject: [PATCH 0612/1731] net: ax25: Fix deadlock caused by skb_recv_datagram
 in ax25_recvmsg

The skb_recv_datagram() in ax25_recvmsg() will hold lock_sock
and block until it receives a packet from the remote. If the client
doesn`t connect to server and calls read() directly, it will not
receive any packets forever. As a result, the deadlock will happen.

The fail log caused by deadlock is shown below:

[  369.606973] INFO: task ax25_deadlock:157 blocked for more than 245 seconds.
[  369.608919] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
[  369.613058] Call Trace:
[  369.613315]  <TASK>
[  369.614072]  __schedule+0x2f9/0xb20
[  369.615029]  schedule+0x49/0xb0
[  369.615734]  __lock_sock+0x92/0x100
[  369.616763]  ? destroy_sched_domains_rcu+0x20/0x20
[  369.617941]  lock_sock_nested+0x6e/0x70
[  369.618809]  ax25_bind+0xaa/0x210
[  369.619736]  __sys_bind+0xca/0xf0
[  369.620039]  ? do_futex+0xae/0x1b0
[  369.620387]  ? __x64_sys_futex+0x7c/0x1c0
[  369.620601]  ? fpregs_assert_state_consistent+0x19/0x40
[  369.620613]  __x64_sys_bind+0x11/0x20
[  369.621791]  do_syscall_64+0x3b/0x90
[  369.622423]  entry_SYSCALL_64_after_hwframe+0x46/0xb0
[  369.623319] RIP: 0033:0x7f43c8aa8af7
[  369.624301] RSP: 002b:00007f43c8197ef8 EFLAGS: 00000246 ORIG_RAX: 0000000000000031
[  369.625756] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f43c8aa8af7
[  369.626724] RDX: 0000000000000010 RSI: 000055768e2021d0 RDI: 0000000000000005
[  369.628569] RBP: 00007f43c8197f00 R08: 0000000000000011 R09: 00007f43c8198700
[  369.630208] R10: 0000000000000000 R11: 0000000000000246 R12: 00007fff845e6afe
[  369.632240] R13: 00007fff845e6aff R14: 00007f43c8197fc0 R15: 00007f43c8198700

This patch replaces skb_recv_datagram() with an open-coded variant of it
releasing the socket lock before the __skb_wait_for_more_packets() call
and re-acquiring it after such call in order that other functions that
need socket lock could be executed.

what's more, the socket lock will be released only when recvmsg() will
block and that should produce nicer overall behavior.

Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Suggested-by: Thomas Osterried <thomas@osterried.de>
Signed-off-by: Duoming Zhou <duoming@zju.edu.cn>
Reported-by: Thomas Habets <thomas@@habets.se>
Acked-by: Paolo Abeni <pabeni@redhat.com>
Reviewed-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/ax25/af_ax25.c | 33 ++++++++++++++++++++++++++++-----
 1 file changed, 28 insertions(+), 5 deletions(-)

diff --git a/net/ax25/af_ax25.c b/net/ax25/af_ax25.c
index 95393bb2760b3..4c7030ed8d331 100644
--- a/net/ax25/af_ax25.c
+++ b/net/ax25/af_ax25.c
@@ -1661,9 +1661,12 @@ static int ax25_recvmsg(struct socket *sock, struct msghdr *msg, size_t size,
 			int flags)
 {
 	struct sock *sk = sock->sk;
-	struct sk_buff *skb;
+	struct sk_buff *skb, *last;
+	struct sk_buff_head *sk_queue;
 	int copied;
 	int err = 0;
+	int off = 0;
+	long timeo;
 
 	lock_sock(sk);
 	/*
@@ -1675,10 +1678,29 @@ static int ax25_recvmsg(struct socket *sock, struct msghdr *msg, size_t size,
 		goto out;
 	}
 
-	/* Now we can treat all alike */
-	skb = skb_recv_datagram(sk, flags, &err);
-	if (skb == NULL)
-		goto out;
+	/*  We need support for non-blocking reads. */
+	sk_queue = &sk->sk_receive_queue;
+	skb = __skb_try_recv_datagram(sk, sk_queue, flags, &off, &err, &last);
+	/* If no packet is available, release_sock(sk) and try again. */
+	if (!skb) {
+		if (err != -EAGAIN)
+			goto out;
+		release_sock(sk);
+		timeo = sock_rcvtimeo(sk, flags & MSG_DONTWAIT);
+		while (timeo && !__skb_wait_for_more_packets(sk, sk_queue, &err,
+							     &timeo, last)) {
+			skb = __skb_try_recv_datagram(sk, sk_queue, flags, &off,
+						      &err, &last);
+			if (skb)
+				break;
+
+			if (err != -EAGAIN)
+				goto done;
+		}
+		if (!skb)
+			goto done;
+		lock_sock(sk);
+	}
 
 	if (!sk_to_ax25(sk)->pidincl)
 		skb_pull(skb, 1);		/* Remove PID */
@@ -1725,6 +1747,7 @@ static int ax25_recvmsg(struct socket *sock, struct msghdr *msg, size_t size,
 out:
 	release_sock(sk);
 
+done:
 	return err;
 }
 
-- 
GitLab


From 933b5f9f98da29af646b51b36a0753692908ef64 Mon Sep 17 00:00:00 2001
From: Dmitry Klochkov <kdmitry556@gmail.com>
Date: Tue, 14 Jun 2022 15:11:41 +0300
Subject: [PATCH 0613/1731] tools/kvm_stat: fix display of error when multiple
 processes are found

Instead of printing an error message, kvm_stat script fails when we
restrict statistics to a guest by its name and there are multiple guests
with such name:

  # kvm_stat -g my_vm
  Traceback (most recent call last):
    File "/usr/bin/kvm_stat", line 1819, in <module>
      main()
    File "/usr/bin/kvm_stat", line 1779, in main
      options = get_options()
    File "/usr/bin/kvm_stat", line 1718, in get_options
      options = argparser.parse_args()
    File "/usr/lib64/python3.10/argparse.py", line 1825, in parse_args
      args, argv = self.parse_known_args(args, namespace)
    File "/usr/lib64/python3.10/argparse.py", line 1858, in parse_known_args
      namespace, args = self._parse_known_args(args, namespace)
    File "/usr/lib64/python3.10/argparse.py", line 2067, in _parse_known_args
      start_index = consume_optional(start_index)
    File "/usr/lib64/python3.10/argparse.py", line 2007, in consume_optional
      take_action(action, args, option_string)
    File "/usr/lib64/python3.10/argparse.py", line 1935, in take_action
      action(self, namespace, argument_values, option_string)
    File "/usr/bin/kvm_stat", line 1649, in __call__
      ' to specify the desired pid'.format(" ".join(pids)))
  TypeError: sequence item 0: expected str instance, int found

To avoid this, it's needed to convert pids int values to strings before
pass them to join().

Signed-off-by: Dmitry Klochkov <kdmitry556@gmail.com>
Message-Id: <20220614121141.160689-1-kdmitry556@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/kvm/kvm_stat/kvm_stat | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/tools/kvm/kvm_stat/kvm_stat b/tools/kvm/kvm_stat/kvm_stat
index 5a5bd74f55bd5..9c366b3a676db 100755
--- a/tools/kvm/kvm_stat/kvm_stat
+++ b/tools/kvm/kvm_stat/kvm_stat
@@ -1646,7 +1646,8 @@ Press any other key to refresh statistics immediately.
                          .format(values))
             if len(pids) > 1:
                 sys.exit('Error: Multiple processes found (pids: {}). Use "-p"'
-                         ' to specify the desired pid'.format(" ".join(pids)))
+                         ' to specify the desired pid'
+                         .format(" ".join(map(str, pids))))
             namespace.pid = pids[0]
 
     argparser = argparse.ArgumentParser(description=description_text,
-- 
GitLab


From c435f61d0eb334dc8367164a125aea45d9dd9508 Mon Sep 17 00:00:00 2001
From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Date: Thu, 19 May 2022 13:51:42 -0400
Subject: [PATCH 0614/1731] drm/amd/display: Drop unnecessary guard from DC
 resource

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 31f0262fc9308..28803ca9e3f2c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1998,7 +1998,6 @@ enum dc_status dc_remove_stream_from_ctx(
 	if (dc->res_pool->funcs->link_enc_unassign)
 		dc->res_pool->funcs->link_enc_unassign(new_ctx, del_pipe->stream);
 
-#if defined(CONFIG_DRM_AMD_DC_DCN)
 	if (is_dp_128b_132b_signal(del_pipe)) {
 		update_hpo_dp_stream_engine_usage(
 			&new_ctx->res_ctx, dc->res_pool,
@@ -2006,7 +2005,6 @@ enum dc_status dc_remove_stream_from_ctx(
 			false);
 		remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream);
 	}
-#endif
 
 	if (del_pipe->stream_res.audio)
 		update_audio_usage(
-- 
GitLab


From 84a85d3fef2e75b1fe9fc2af6f5267122555a1ed Mon Sep 17 00:00:00 2001
From: Haowen Bai <baihaowen@meizu.com>
Date: Thu, 21 Apr 2022 10:26:59 +0800
Subject: [PATCH 0615/1731] pinctrl: aspeed: Fix potential NULL dereference in
 aspeed_pinmux_set_mux()

pdesc could be null but still dereference pdesc->name and it will lead to
a null pointer access. So we move a null check before dereference.

Signed-off-by: Haowen Bai <baihaowen@meizu.com>
Link: https://lore.kernel.org/r/1650508019-22554-1-git-send-email-baihaowen@meizu.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 drivers/pinctrl/aspeed/pinctrl-aspeed.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
index c94e24aadf922..83d47ff1cea8f 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
@@ -236,11 +236,11 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
 		const struct aspeed_sig_expr **funcs;
 		const struct aspeed_sig_expr ***prios;
 
-		pr_debug("Muxing pin %s for %s\n", pdesc->name, pfunc->name);
-
 		if (!pdesc)
 			return -EINVAL;
 
+		pr_debug("Muxing pin %s for %s\n", pdesc->name, pfunc->name);
+
 		prios = pdesc->prios;
 
 		if (!prios)
-- 
GitLab


From aaefa29270d9551b604165a08406543efa9d16f5 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Wed, 25 May 2022 21:49:56 -0500
Subject: [PATCH 0616/1731] pinctrl: sunxi: a83t: Fix NAND function name for
 some pins

The other NAND pins on Port C use the "nand0" function name.
"nand0" also matches all of the other Allwinner SoCs.

Fixes: 4730f33f0d82 ("pinctrl: sunxi: add allwinner A83T PIO controller support")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220526024956.49500-1-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
index 4ada80317a3bd..b5c1a8f363f32 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
@@ -158,26 +158,26 @@ static const struct sunxi_desc_pin sun8i_a83t_pins[] = {
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
-		  SUNXI_FUNCTION(0x2, "nand"),		/* DQ6 */
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ6 */
 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D6 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
-		  SUNXI_FUNCTION(0x2, "nand"),		/* DQ7 */
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ7 */
 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D7 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
-		  SUNXI_FUNCTION(0x2, "nand"),		/* DQS */
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQS */
 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* RST */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
-		  SUNXI_FUNCTION(0x2, "nand")),		/* CE2 */
+		  SUNXI_FUNCTION(0x2, "nand0")),	/* CE2 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
-		  SUNXI_FUNCTION(0x2, "nand")),		/* CE3 */
+		  SUNXI_FUNCTION(0x2, "nand0")),	/* CE3 */
 	/* Hole */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
-- 
GitLab


From 3046a827316c0e55fc563b4fb78c93b9ca5c7c37 Mon Sep 17 00:00:00 2001
From: Jon Maxwell <jmaxwell37@gmail.com>
Date: Wed, 15 Jun 2022 11:15:40 +1000
Subject: [PATCH 0617/1731] bpf: Fix request_sock leak in sk lookup helpers

A customer reported a request_socket leak in a Calico cloud environment. We
found that a BPF program was doing a socket lookup with takes a refcnt on
the socket and that it was finding the request_socket but returning the parent
LISTEN socket via sk_to_full_sk() without decrementing the child request socket
1st, resulting in request_sock slab object leak. This patch retains the
existing behaviour of returning full socks to the caller but it also decrements
the child request_socket if one is present before doing so to prevent the leak.

Thanks to Curtis Taylor for all the help in diagnosing and testing this. And
thanks to Antoine Tenart for the reproducer and patch input.

v2 of this patch contains, refactor as per Daniel Borkmann's suggestions to
validate RCU flags on the listen socket so that it balances with bpf_sk_release()
and update comments as per Martin KaFai Lau's suggestion. One small change to
Daniels suggestion, put "sk = sk2" under "if (sk2 != sk)" to avoid an extra
instruction.

Fixes: f7355a6c0497 ("bpf: Check sk_fullsock() before returning from bpf_sk_lookup()")
Fixes: edbf8c01de5a ("bpf: add skc_lookup_tcp helper")
Co-developed-by: Antoine Tenart <atenart@kernel.org>
Signed-off-by: Antoine Tenart <atenart@kernel.org>
Signed-off-by: Jon Maxwell <jmaxwell37@gmail.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Tested-by: Curtis Taylor <cutaylor-pub@yahoo.com>
Cc: Martin KaFai Lau <kafai@fb.com>
Link: https://lore.kernel.org/bpf/56d6f898-bde0-bb25-3427-12a330b29fb8@iogearbox.net
Link: https://lore.kernel.org/bpf/20220615011540.813025-1-jmaxwell37@gmail.com
---
 net/core/filter.c | 34 ++++++++++++++++++++++++++++------
 1 file changed, 28 insertions(+), 6 deletions(-)

diff --git a/net/core/filter.c b/net/core/filter.c
index 5af58eb485875..5d16d66727fc8 100644
--- a/net/core/filter.c
+++ b/net/core/filter.c
@@ -6516,10 +6516,21 @@ __bpf_sk_lookup(struct sk_buff *skb, struct bpf_sock_tuple *tuple, u32 len,
 					   ifindex, proto, netns_id, flags);
 
 	if (sk) {
-		sk = sk_to_full_sk(sk);
-		if (!sk_fullsock(sk)) {
+		struct sock *sk2 = sk_to_full_sk(sk);
+
+		/* sk_to_full_sk() may return (sk)->rsk_listener, so make sure the original sk
+		 * sock refcnt is decremented to prevent a request_sock leak.
+		 */
+		if (!sk_fullsock(sk2))
+			sk2 = NULL;
+		if (sk2 != sk) {
 			sock_gen_put(sk);
-			return NULL;
+			/* Ensure there is no need to bump sk2 refcnt */
+			if (unlikely(sk2 && !sock_flag(sk2, SOCK_RCU_FREE))) {
+				WARN_ONCE(1, "Found non-RCU, unreferenced socket!");
+				return NULL;
+			}
+			sk = sk2;
 		}
 	}
 
@@ -6553,10 +6564,21 @@ bpf_sk_lookup(struct sk_buff *skb, struct bpf_sock_tuple *tuple, u32 len,
 					 flags);
 
 	if (sk) {
-		sk = sk_to_full_sk(sk);
-		if (!sk_fullsock(sk)) {
+		struct sock *sk2 = sk_to_full_sk(sk);
+
+		/* sk_to_full_sk() may return (sk)->rsk_listener, so make sure the original sk
+		 * sock refcnt is decremented to prevent a request_sock leak.
+		 */
+		if (!sk_fullsock(sk2))
+			sk2 = NULL;
+		if (sk2 != sk) {
 			sock_gen_put(sk);
-			return NULL;
+			/* Ensure there is no need to bump sk2 refcnt */
+			if (unlikely(sk2 && !sock_flag(sk2, SOCK_RCU_FREE))) {
+				WARN_ONCE(1, "Found non-RCU, unreferenced socket!");
+				return NULL;
+			}
+			sk = sk2;
 		}
 	}
 
-- 
GitLab


From 27d8fa207835fa5c7cd6f969c6cc94d1123951ee Mon Sep 17 00:00:00 2001
From: Catalin Marinas <catalin.marinas@arm.com>
Date: Wed, 15 Jun 2022 14:22:38 +0100
Subject: [PATCH 0618/1731] Revert "arm64: Initialize jump labels before
 setup_machine_fdt()"

This reverts commit 73e2d827a501d48dceeb5b9b267a4cd283d6b1ae.

The reverted patch was needed as a fix after commit f5bda35fba61
("random: use static branch for crng_ready()"). However, this was
already fixed by 60e5b2886b92 ("random: do not use jump labels before
they are initialized") and hence no longer necessary to initialise jump
labels before setup_machine_fdt().

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/kernel/setup.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index cf3a759f10d4e..fea3223704b63 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -303,14 +303,13 @@ void __init __no_sanitize_address setup_arch(char **cmdline_p)
 	early_fixmap_init();
 	early_ioremap_init();
 
+	setup_machine_fdt(__fdt_pointer);
+
 	/*
 	 * Initialise the static keys early as they may be enabled by the
-	 * cpufeature code, early parameters, and DT setup.
+	 * cpufeature code and early parameters.
 	 */
 	jump_label_init();
-
-	setup_machine_fdt(__fdt_pointer);
-
 	parse_early_param();
 
 	/*
-- 
GitLab


From ec41c6d82056cbbd7ec8f44eed6d86fea50acf4e Mon Sep 17 00:00:00 2001
From: Michael Carns <mike@carns.com>
Date: Wed, 15 Jun 2022 14:25:44 +0200
Subject: [PATCH 0619/1731] hwmon: (asus-ec-sensors) add missing comma in board
 name list.

This fixes a regression where coma lead to concatenating board names
and broke module loading for C8H.

Fixes: 5b4285c57b6f ("hwmon: (asus-ec-sensors) fix Formula VIII definition")

Signed-off-by: Michael Carns <mike@carns.com>
Signed-off-by: Eugene Shalygin <eugene.shalygin@gmail.com>
Link: https://lore.kernel.org/r/20220615122544.140340-1-eugene.shalygin@gmail.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
---
 drivers/hwmon/asus-ec-sensors.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/hwmon/asus-ec-sensors.c b/drivers/hwmon/asus-ec-sensors.c
index 57e11b2bab742..3633ab691662b 100644
--- a/drivers/hwmon/asus-ec-sensors.c
+++ b/drivers/hwmon/asus-ec-sensors.c
@@ -259,7 +259,7 @@ static const struct ec_board_info board_info[] = {
 	},
 	{
 		.board_names = {
-			"ROG CROSSHAIR VIII FORMULA"
+			"ROG CROSSHAIR VIII FORMULA",
 			"ROG CROSSHAIR VIII HERO",
 			"ROG CROSSHAIR VIII HERO (WI-FI)",
 		},
-- 
GitLab


From 3eefdf9d1e406f3da47470b2854347009ffcb6fa Mon Sep 17 00:00:00 2001
From: Mark Rutland <mark.rutland@arm.com>
Date: Tue, 14 Jun 2022 09:09:42 +0100
Subject: [PATCH 0620/1731] arm64: ftrace: fix branch range checks

The branch range checks in ftrace_make_call() and ftrace_make_nop() are
incorrect, erroneously permitting a forwards branch of 128M and
erroneously rejecting a backwards branch of 128M.

This is because both functions calculate the offset backwards,
calculating the offset *from* the target *to* the branch, rather than
the other way around as the later comparisons expect.

If an out-of-range branch were erroeously permitted, this would later be
rejected by aarch64_insn_gen_branch_imm() as branch_imm_common() checks
the bounds correctly, resulting in warnings and the placement of a BRK
instruction. Note that this can only happen for a forwards branch of
exactly 128M, and so the caller would need to be exactly 128M bytes
below the relevant ftrace trampoline.

If an in-range branch were erroeously rejected, then:

* For modules when CONFIG_ARM64_MODULE_PLTS=y, this would result in the
  use of a PLT entry, which is benign.

  Note that this is the common case, as this is selected by
  CONFIG_RANDOMIZE_BASE (and therefore RANDOMIZE_MODULE_REGION_FULL),
  which distributions typically seelct. This is also selected by
  CONFIG_ARM64_ERRATUM_843419.

* For modules when CONFIG_ARM64_MODULE_PLTS=n, this would result in
  internal ftrace failures.

* For core kernel text, this would result in internal ftrace failues.

  Note that for this to happen, the kernel text would need to be at
  least 128M bytes in size, and typical configurations are smaller tha
  this.

Fix this by calculating the offset *from* the branch *to* the target in
both functions.

Fixes: f8af0b364e24 ("arm64: ftrace: don't validate branch via PLT in ftrace_make_nop()")
Fixes: e71a4e1bebaf ("arm64: ftrace: add support for far branches to dynamic ftrace")
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Will Deacon <will@kernel.org>
Tested-by: "Ivan T. Ivanov" <iivanov@suse.de>
Reviewed-by: Chengming Zhou <zhouchengming@bytedance.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20220614080944.1349146-2-mark.rutland@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/kernel/ftrace.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/kernel/ftrace.c b/arch/arm64/kernel/ftrace.c
index f447c4a36f694..e1c88234b8827 100644
--- a/arch/arm64/kernel/ftrace.c
+++ b/arch/arm64/kernel/ftrace.c
@@ -84,7 +84,7 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
 {
 	unsigned long pc = rec->ip;
 	u32 old, new;
-	long offset = (long)pc - (long)addr;
+	long offset = (long)addr - (long)pc;
 
 	if (offset < -SZ_128M || offset >= SZ_128M) {
 		struct module *mod;
@@ -183,7 +183,7 @@ int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec,
 	unsigned long pc = rec->ip;
 	bool validate = true;
 	u32 old = 0, new;
-	long offset = (long)pc - (long)addr;
+	long offset = (long)addr - (long)pc;
 
 	if (offset < -SZ_128M || offset >= SZ_128M) {
 		u32 replaced;
-- 
GitLab


From a6253579977e4c6f7818eeb05bf2bc65678a7187 Mon Sep 17 00:00:00 2001
From: Mark Rutland <mark.rutland@arm.com>
Date: Tue, 14 Jun 2022 09:09:43 +0100
Subject: [PATCH 0621/1731] arm64: ftrace: consistently handle PLTs.

Sometimes it is necessary to use a PLT entry to call an ftrace
trampoline. This is handled by ftrace_make_call() and ftrace_make_nop(),
with each having *almost* identical logic, but this is not handled by
ftrace_modify_call() since its introduction in commit:

  3b23e4991fb66f6d ("arm64: implement ftrace with regs")

Due to this, if we ever were to call ftrace_modify_call() for a callsite
which requires a PLT entry for a trampoline, then either:

a) If the old addr requires a trampoline, ftrace_modify_call() will use
   an out-of-range address to generate the 'old' branch instruction.
   This will result in warnings from aarch64_insn_gen_branch_imm() and
   ftrace_modify_code(), and no instructions will be modified. As
   ftrace_modify_call() will return an error, this will result in
   subsequent internal ftrace errors.

b) If the old addr does not require a trampoline, but the new addr does,
   ftrace_modify_call() will use an out-of-range address to generate the
   'new' branch instruction. This will result in warnings from
   aarch64_insn_gen_branch_imm(), and ftrace_modify_code() will replace
   the 'old' branch with a BRK. This will result in a kernel panic when
   this BRK is later executed.

Practically speaking, case (a) is vastly more likely than case (b), and
typically this will result in internal ftrace errors that don't
necessarily affect the rest of the system. This can be demonstrated with
an out-of-tree test module which triggers ftrace_modify_call(), e.g.

| # insmod test_ftrace.ko
| test_ftrace: Function test_function raw=0xffffb3749399201c, callsite=0xffffb37493992024
| branch_imm_common: offset out of range
| branch_imm_common: offset out of range
| ------------[ ftrace bug ]------------
| ftrace failed to modify
| [<ffffb37493992024>] test_function+0x8/0x38 [test_ftrace]
|  actual:   1d:00:00:94
| Updating ftrace call site to call a different ftrace function
| ftrace record flags: e0000002
|  (2) R
|  expected tramp: ffffb374ae42ed54
| ------------[ cut here ]------------
| WARNING: CPU: 0 PID: 165 at kernel/trace/ftrace.c:2085 ftrace_bug+0x280/0x2b0
| Modules linked in: test_ftrace(+)
| CPU: 0 PID: 165 Comm: insmod Not tainted 5.19.0-rc2-00002-g4d9ead8b45ce #13
| Hardware name: linux,dummy-virt (DT)
| pstate: 60400005 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
| pc : ftrace_bug+0x280/0x2b0
| lr : ftrace_bug+0x280/0x2b0
| sp : ffff80000839ba00
| x29: ffff80000839ba00 x28: 0000000000000000 x27: ffff80000839bcf0
| x26: ffffb37493994180 x25: ffffb374b0991c28 x24: ffffb374b0d70000
| x23: 00000000ffffffea x22: ffffb374afcc33b0 x21: ffffb374b08f9cc8
| x20: ffff572b8462c000 x19: ffffb374b08f9000 x18: ffffffffffffffff
| x17: 6c6c6163202c6331 x16: ffffb374ae5ad110 x15: ffffb374b0d51ee4
| x14: 0000000000000000 x13: 3435646532346561 x12: 3437336266666666
| x11: 203a706d61727420 x10: 6465746365707865 x9 : ffffb374ae5149e8
| x8 : 336266666666203a x7 : 706d617274206465 x6 : 00000000fffff167
| x5 : ffff572bffbc4a08 x4 : 00000000fffff167 x3 : 0000000000000000
| x2 : 0000000000000000 x1 : ffff572b84461e00 x0 : 0000000000000022
| Call trace:
|  ftrace_bug+0x280/0x2b0
|  ftrace_replace_code+0x98/0xa0
|  ftrace_modify_all_code+0xe0/0x144
|  arch_ftrace_update_code+0x14/0x20
|  ftrace_startup+0xf8/0x1b0
|  register_ftrace_function+0x38/0x90
|  test_ftrace_init+0xd0/0x1000 [test_ftrace]
|  do_one_initcall+0x50/0x2b0
|  do_init_module+0x50/0x1f0
|  load_module+0x17c8/0x1d64
|  __do_sys_finit_module+0xa8/0x100
|  __arm64_sys_finit_module+0x2c/0x3c
|  invoke_syscall+0x50/0x120
|  el0_svc_common.constprop.0+0xdc/0x100
|  do_el0_svc+0x3c/0xd0
|  el0_svc+0x34/0xb0
|  el0t_64_sync_handler+0xbc/0x140
|  el0t_64_sync+0x18c/0x190
| ---[ end trace 0000000000000000 ]---

We can solve this by consistently determining whether to use a PLT entry
for an address.

Note that since (the earlier) commit:

  f1a54ae9af0da4d7 ("arm64: module/ftrace: intialize PLT at load time")

... we can consistently determine the PLT address that a given callsite
will use, and therefore ftrace_make_nop() does not need to skip
validation when a PLT is in use.

This patch factors the existing logic out of ftrace_make_call() and
ftrace_make_nop() into a common ftrace_find_callable_addr() helper
function, which is used by ftrace_make_call(), ftrace_make_nop(), and
ftrace_modify_call(). In ftrace_make_nop() the patching is consistently
validated by ftrace_modify_code() as we can always determine what the
old instruction should have been.

Fixes: 3b23e4991fb6 ("arm64: implement ftrace with regs")
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Will Deacon <will@kernel.org>
Tested-by: "Ivan T. Ivanov" <iivanov@suse.de>
Reviewed-by: Chengming Zhou <zhouchengming@bytedance.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20220614080944.1349146-3-mark.rutland@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/kernel/ftrace.c | 137 ++++++++++++++++++-------------------
 1 file changed, 66 insertions(+), 71 deletions(-)

diff --git a/arch/arm64/kernel/ftrace.c b/arch/arm64/kernel/ftrace.c
index e1c88234b8827..ea5dc7c90f465 100644
--- a/arch/arm64/kernel/ftrace.c
+++ b/arch/arm64/kernel/ftrace.c
@@ -78,47 +78,76 @@ static struct plt_entry *get_ftrace_plt(struct module *mod, unsigned long addr)
 }
 
 /*
- * Turn on the call to ftrace_caller() in instrumented function
+ * Find the address the callsite must branch to in order to reach '*addr'.
+ *
+ * Due to the limited range of 'BL' instructions, modules may be placed too far
+ * away to branch directly and must use a PLT.
+ *
+ * Returns true when '*addr' contains a reachable target address, or has been
+ * modified to contain a PLT address. Returns false otherwise.
  */
-int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
+static bool ftrace_find_callable_addr(struct dyn_ftrace *rec,
+				      struct module *mod,
+				      unsigned long *addr)
 {
 	unsigned long pc = rec->ip;
-	u32 old, new;
-	long offset = (long)addr - (long)pc;
+	long offset = (long)*addr - (long)pc;
+	struct plt_entry *plt;
 
-	if (offset < -SZ_128M || offset >= SZ_128M) {
-		struct module *mod;
-		struct plt_entry *plt;
+	/*
+	 * When the target is within range of the 'BL' instruction, use 'addr'
+	 * as-is and branch to that directly.
+	 */
+	if (offset >= -SZ_128M && offset < SZ_128M)
+		return true;
 
-		if (!IS_ENABLED(CONFIG_ARM64_MODULE_PLTS))
-			return -EINVAL;
+	/*
+	 * When the target is outside of the range of a 'BL' instruction, we
+	 * must use a PLT to reach it. We can only place PLTs for modules, and
+	 * only when module PLT support is built-in.
+	 */
+	if (!IS_ENABLED(CONFIG_ARM64_MODULE_PLTS))
+		return false;
 
-		/*
-		 * On kernels that support module PLTs, the offset between the
-		 * branch instruction and its target may legally exceed the
-		 * range of an ordinary relative 'bl' opcode. In this case, we
-		 * need to branch via a trampoline in the module.
-		 *
-		 * NOTE: __module_text_address() must be called with preemption
-		 * disabled, but we can rely on ftrace_lock to ensure that 'mod'
-		 * retains its validity throughout the remainder of this code.
-		 */
+	/*
+	 * 'mod' is only set at module load time, but if we end up
+	 * dealing with an out-of-range condition, we can assume it
+	 * is due to a module being loaded far away from the kernel.
+	 *
+	 * NOTE: __module_text_address() must be called with preemption
+	 * disabled, but we can rely on ftrace_lock to ensure that 'mod'
+	 * retains its validity throughout the remainder of this code.
+	 */
+	if (!mod) {
 		preempt_disable();
 		mod = __module_text_address(pc);
 		preempt_enable();
+	}
 
-		if (WARN_ON(!mod))
-			return -EINVAL;
+	if (WARN_ON(!mod))
+		return false;
 
-		plt = get_ftrace_plt(mod, addr);
-		if (!plt) {
-			pr_err("ftrace: no module PLT for %ps\n", (void *)addr);
-			return -EINVAL;
-		}
-
-		addr = (unsigned long)plt;
+	plt = get_ftrace_plt(mod, *addr);
+	if (!plt) {
+		pr_err("ftrace: no module PLT for %ps\n", (void *)*addr);
+		return false;
 	}
 
+	*addr = (unsigned long)plt;
+	return true;
+}
+
+/*
+ * Turn on the call to ftrace_caller() in instrumented function
+ */
+int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
+{
+	unsigned long pc = rec->ip;
+	u32 old, new;
+
+	if (!ftrace_find_callable_addr(rec, NULL, &addr))
+		return -EINVAL;
+
 	old = aarch64_insn_gen_nop();
 	new = aarch64_insn_gen_branch_imm(pc, addr, AARCH64_INSN_BRANCH_LINK);
 
@@ -132,6 +161,11 @@ int ftrace_modify_call(struct dyn_ftrace *rec, unsigned long old_addr,
 	unsigned long pc = rec->ip;
 	u32 old, new;
 
+	if (!ftrace_find_callable_addr(rec, NULL, &old_addr))
+		return -EINVAL;
+	if (!ftrace_find_callable_addr(rec, NULL, &addr))
+		return -EINVAL;
+
 	old = aarch64_insn_gen_branch_imm(pc, old_addr,
 					  AARCH64_INSN_BRANCH_LINK);
 	new = aarch64_insn_gen_branch_imm(pc, addr, AARCH64_INSN_BRANCH_LINK);
@@ -181,54 +215,15 @@ int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec,
 		    unsigned long addr)
 {
 	unsigned long pc = rec->ip;
-	bool validate = true;
 	u32 old = 0, new;
-	long offset = (long)addr - (long)pc;
 
-	if (offset < -SZ_128M || offset >= SZ_128M) {
-		u32 replaced;
-
-		if (!IS_ENABLED(CONFIG_ARM64_MODULE_PLTS))
-			return -EINVAL;
-
-		/*
-		 * 'mod' is only set at module load time, but if we end up
-		 * dealing with an out-of-range condition, we can assume it
-		 * is due to a module being loaded far away from the kernel.
-		 */
-		if (!mod) {
-			preempt_disable();
-			mod = __module_text_address(pc);
-			preempt_enable();
-
-			if (WARN_ON(!mod))
-				return -EINVAL;
-		}
-
-		/*
-		 * The instruction we are about to patch may be a branch and
-		 * link instruction that was redirected via a PLT entry. In
-		 * this case, the normal validation will fail, but we can at
-		 * least check that we are dealing with a branch and link
-		 * instruction that points into the right module.
-		 */
-		if (aarch64_insn_read((void *)pc, &replaced))
-			return -EFAULT;
-
-		if (!aarch64_insn_is_bl(replaced) ||
-		    !within_module(pc + aarch64_get_branch_offset(replaced),
-				   mod))
-			return -EINVAL;
-
-		validate = false;
-	} else {
-		old = aarch64_insn_gen_branch_imm(pc, addr,
-						  AARCH64_INSN_BRANCH_LINK);
-	}
+	if (!ftrace_find_callable_addr(rec, mod, &addr))
+		return -EINVAL;
 
+	old = aarch64_insn_gen_branch_imm(pc, addr, AARCH64_INSN_BRANCH_LINK);
 	new = aarch64_insn_gen_nop();
 
-	return ftrace_modify_code(pc, old, new, validate);
+	return ftrace_modify_code(pc, old, new, true);
 }
 
 void arch_ftrace_update_code(int command)
-- 
GitLab


From 0d8116ccd83b7e5384cf04de570ae19771e8a3d0 Mon Sep 17 00:00:00 2001
From: Mark Rutland <mark.rutland@arm.com>
Date: Tue, 14 Jun 2022 09:09:44 +0100
Subject: [PATCH 0622/1731] arm64: ftrace: remove redundant label

Since commit:

  c4a0ebf87cebbfa2 ("arm64/ftrace: Make function graph use ftrace directly")

The 'ftrace_common_return' label has been unused.

Remove it.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Chengming Zhou <zhouchengming@bytedance.com>
Cc: Will Deacon <will@kernel.org>
Tested-by: "Ivan T. Ivanov" <iivanov@suse.de>
Reviewed-by: Chengming Zhou <zhouchengming@bytedance.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20220614080944.1349146-4-mark.rutland@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/kernel/entry-ftrace.S | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm64/kernel/entry-ftrace.S b/arch/arm64/kernel/entry-ftrace.S
index d42a205ef6259..bd5df50e46432 100644
--- a/arch/arm64/kernel/entry-ftrace.S
+++ b/arch/arm64/kernel/entry-ftrace.S
@@ -102,7 +102,6 @@ SYM_INNER_LABEL(ftrace_call, SYM_L_GLOBAL)
  * x19-x29 per the AAPCS, and we created frame records upon entry, so we need
  * to restore x0-x8, x29, and x30.
  */
-ftrace_common_return:
 	/* Restore function arguments */
 	ldp	x0, x1, [sp]
 	ldp	x2, x3, [sp, #S_X2]
-- 
GitLab


From 10eb3a0d517fcc83eeea4242c149461205675eb4 Mon Sep 17 00:00:00 2001
From: Benjamin Marzinski <bmarzins@redhat.com>
Date: Tue, 14 Jun 2022 11:10:28 -0500
Subject: [PATCH 0623/1731] dm: fix race in dm_start_io_acct

After commit 82f6cdcc3676c ("dm: switch dm_io booleans over to proper
flags") dm_start_io_acct stopped atomically checking and setting
was_accounted, which turned into the DM_IO_ACCOUNTED flag. This opened
the possibility for a race where IO accounting is started twice for
duplicate bios. To remove the race, check the flag while holding the
io->lock.

Fixes: 82f6cdcc3676c ("dm: switch dm_io booleans over to proper flags")
Cc: stable@vger.kernel.org
Signed-off-by: Benjamin Marzinski <bmarzins@redhat.com>
Signed-off-by: Mike Snitzer <snitzer@kernel.org>
---
 drivers/md/dm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/md/dm.c b/drivers/md/dm.c
index d8f16183bf27c..d5e6d33700e50 100644
--- a/drivers/md/dm.c
+++ b/drivers/md/dm.c
@@ -555,6 +555,10 @@ static void dm_start_io_acct(struct dm_io *io, struct bio *clone)
 		unsigned long flags;
 		/* Can afford locking given DM_TIO_IS_DUPLICATE_BIO */
 		spin_lock_irqsave(&io->lock, flags);
+		if (dm_io_flagged(io, DM_IO_ACCOUNTED)) {
+			spin_unlock_irqrestore(&io->lock, flags);
+			return;
+		}
 		dm_io_set_flag(io, DM_IO_ACCOUNTED);
 		spin_unlock_irqrestore(&io->lock, flags);
 	}
-- 
GitLab


From 89bcd9a64b849380ef57e3032b307574e48db524 Mon Sep 17 00:00:00 2001
From: Mengqi Zhang <mengqi.zhang@mediatek.com>
Date: Thu, 9 Jun 2022 19:22:39 +0800
Subject: [PATCH 0624/1731] mmc: mediatek: wait dma stop bit reset to 0

MediaTek IP requires that after dma stop, it need to wait this dma stop
bit auto-reset to 0. When bus is in high loading state, it will take a
while for the dma stop complete. If there is no waiting operation here,
when program runs to clear fifo and reset, bus will hang.

In addition, there should be no return in msdc_data_xfer_next() if
there is data need be transferred, because no matter what error occurs
here, it should continue to excute to the following mmc_request_done.
Otherwise the core layer may wait complete forever.

Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20220609112239.18911-1-mengqi.zhang@mediatek.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
---
 drivers/mmc/host/mtk-sd.c | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 195dc897188b9..9da4489dc345a 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -1356,7 +1356,7 @@ static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq)
 		msdc_request_done(host, mrq);
 }
 
-static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
+static void msdc_data_xfer_done(struct msdc_host *host, u32 events,
 				struct mmc_request *mrq, struct mmc_data *data)
 {
 	struct mmc_command *stop;
@@ -1376,7 +1376,7 @@ static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
 	spin_unlock_irqrestore(&host->lock, flags);
 
 	if (done)
-		return true;
+		return;
 	stop = data->stop;
 
 	if (check_data || (stop && stop->error)) {
@@ -1385,12 +1385,15 @@ static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
 		sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
 				1);
 
+		ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val,
+						!(val & MSDC_DMA_CTRL_STOP), 1, 20000);
+		if (ret)
+			dev_dbg(host->dev, "DMA stop timed out\n");
+
 		ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val,
 						!(val & MSDC_DMA_CFG_STS), 1, 20000);
-		if (ret) {
-			dev_dbg(host->dev, "DMA stop timed out\n");
-			return false;
-		}
+		if (ret)
+			dev_dbg(host->dev, "DMA inactive timed out\n");
 
 		sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
 		dev_dbg(host->dev, "DMA stop\n");
@@ -1415,9 +1418,7 @@ static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
 		}
 
 		msdc_data_xfer_next(host, mrq);
-		done = true;
 	}
-	return done;
 }
 
 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
@@ -2416,6 +2417,9 @@ static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
 	if (recovery) {
 		sdr_set_field(host->base + MSDC_DMA_CTRL,
 			      MSDC_DMA_CTRL_STOP, 1);
+		if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val,
+			!(val & MSDC_DMA_CTRL_STOP), 1, 3000)))
+			return;
 		if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val,
 			!(val & MSDC_DMA_CFG_STS), 1, 3000)))
 			return;
-- 
GitLab


From d0a180341fe00cd0bd1cc259d196dc255c13f229 Mon Sep 17 00:00:00 2001
From: Guoqing Jiang <guoqing.jiang@linux.dev>
Date: Tue, 7 Jun 2022 10:03:56 +0800
Subject: [PATCH 0625/1731] Revert "md: don't unregister sync_thread with
 reconfig_mutex held"

The 07reshape5intr test is broke because of below path.

    md_reap_sync_thread
            -> mddev_unlock
            -> md_unregister_thread(&mddev->sync_thread)

And md_check_recovery is triggered by,

mddev_unlock -> md_wakeup_thread(mddev->thread)

then mddev->reshape_position is set to MaxSector in raid5_finish_reshape
since MD_RECOVERY_INTR is cleared in md_check_recovery, which means
feature_map is not set with MD_FEATURE_RESHAPE_ACTIVE and superblock's
reshape_position can't be updated accordingly.

Fixes: 8b48ec23cc51a ("md: don't unregister sync_thread with reconfig_mutex held")
Reported-by: Logan Gunthorpe <logang@deltatee.com>
Signed-off-by: Guoqing Jiang <guoqing.jiang@linux.dev>
Signed-off-by: Song Liu <song@kernel.org>
---
 drivers/md/dm-raid.c |  2 +-
 drivers/md/md.c      | 14 +++++---------
 drivers/md/md.h      |  2 +-
 3 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/drivers/md/dm-raid.c b/drivers/md/dm-raid.c
index 5e41fbae3f6b0..9526ccbedafba 100644
--- a/drivers/md/dm-raid.c
+++ b/drivers/md/dm-raid.c
@@ -3725,7 +3725,7 @@ static int raid_message(struct dm_target *ti, unsigned int argc, char **argv,
 	if (!strcasecmp(argv[0], "idle") || !strcasecmp(argv[0], "frozen")) {
 		if (mddev->sync_thread) {
 			set_bit(MD_RECOVERY_INTR, &mddev->recovery);
-			md_reap_sync_thread(mddev, false);
+			md_reap_sync_thread(mddev);
 		}
 	} else if (decipher_sync_action(mddev, mddev->recovery) != st_idle)
 		return -EBUSY;
diff --git a/drivers/md/md.c b/drivers/md/md.c
index 8273ac5eef06a..c7ecb0bffda0d 100644
--- a/drivers/md/md.c
+++ b/drivers/md/md.c
@@ -4831,7 +4831,7 @@ action_store(struct mddev *mddev, const char *page, size_t len)
 				flush_workqueue(md_misc_wq);
 			if (mddev->sync_thread) {
 				set_bit(MD_RECOVERY_INTR, &mddev->recovery);
-				md_reap_sync_thread(mddev, true);
+				md_reap_sync_thread(mddev);
 			}
 			mddev_unlock(mddev);
 		}
@@ -6197,7 +6197,7 @@ static void __md_stop_writes(struct mddev *mddev)
 		flush_workqueue(md_misc_wq);
 	if (mddev->sync_thread) {
 		set_bit(MD_RECOVERY_INTR, &mddev->recovery);
-		md_reap_sync_thread(mddev, true);
+		md_reap_sync_thread(mddev);
 	}
 
 	del_timer_sync(&mddev->safemode_timer);
@@ -9303,7 +9303,7 @@ void md_check_recovery(struct mddev *mddev)
 			 * ->spare_active and clear saved_raid_disk
 			 */
 			set_bit(MD_RECOVERY_INTR, &mddev->recovery);
-			md_reap_sync_thread(mddev, true);
+			md_reap_sync_thread(mddev);
 			clear_bit(MD_RECOVERY_RECOVER, &mddev->recovery);
 			clear_bit(MD_RECOVERY_NEEDED, &mddev->recovery);
 			clear_bit(MD_SB_CHANGE_PENDING, &mddev->sb_flags);
@@ -9338,7 +9338,7 @@ void md_check_recovery(struct mddev *mddev)
 			goto unlock;
 		}
 		if (mddev->sync_thread) {
-			md_reap_sync_thread(mddev, true);
+			md_reap_sync_thread(mddev);
 			goto unlock;
 		}
 		/* Set RUNNING before clearing NEEDED to avoid
@@ -9411,18 +9411,14 @@ void md_check_recovery(struct mddev *mddev)
 }
 EXPORT_SYMBOL(md_check_recovery);
 
-void md_reap_sync_thread(struct mddev *mddev, bool reconfig_mutex_held)
+void md_reap_sync_thread(struct mddev *mddev)
 {
 	struct md_rdev *rdev;
 	sector_t old_dev_sectors = mddev->dev_sectors;
 	bool is_reshaped = false;
 
-	if (reconfig_mutex_held)
-		mddev_unlock(mddev);
 	/* resync has finished, collect result */
 	md_unregister_thread(&mddev->sync_thread);
-	if (reconfig_mutex_held)
-		mddev_lock_nointr(mddev);
 	if (!test_bit(MD_RECOVERY_INTR, &mddev->recovery) &&
 	    !test_bit(MD_RECOVERY_REQUESTED, &mddev->recovery) &&
 	    mddev->degraded != mddev->raid_disks) {
diff --git a/drivers/md/md.h b/drivers/md/md.h
index 5f62c46ac2d33..cf2cbb17acbd4 100644
--- a/drivers/md/md.h
+++ b/drivers/md/md.h
@@ -719,7 +719,7 @@ extern struct md_thread *md_register_thread(
 extern void md_unregister_thread(struct md_thread **threadp);
 extern void md_wakeup_thread(struct md_thread *thread);
 extern void md_check_recovery(struct mddev *mddev);
-extern void md_reap_sync_thread(struct mddev *mddev, bool reconfig_mutex_held);
+extern void md_reap_sync_thread(struct mddev *mddev);
 extern int mddev_init_writes_pending(struct mddev *mddev);
 extern bool md_write_start(struct mddev *mddev, struct bio *bi);
 extern void md_write_inc(struct mddev *mddev, struct bio *bi);
-- 
GitLab


From d1a374a1aeb7e31191448e225ed2f9c5e894f280 Mon Sep 17 00:00:00 2001
From: Kumar Kartikeya Dwivedi <memxor@gmail.com>
Date: Wed, 15 Jun 2022 09:51:51 +0530
Subject: [PATCH 0626/1731] bpf: Limit maximum modifier chain length in
 btf_check_type_tags

On processing a module BTF of module built for an older kernel, we might
sometimes find that some type points to itself forming a loop. If such a
type is a modifier, btf_check_type_tags's while loop following modifier
chain will be caught in an infinite loop.

Fix this by defining a maximum chain length and bailing out if we spin
any longer than that.

Fixes: eb596b090558 ("bpf: Ensure type tags precede modifiers in BTF")
Reported-by: Daniel Borkmann <daniel@iogearbox.net>
Signed-off-by: Kumar Kartikeya Dwivedi <memxor@gmail.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Yonghong Song <yhs@fb.com>
Link: https://lore.kernel.org/bpf/20220615042151.2266537-1-memxor@gmail.com
---
 kernel/bpf/btf.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/kernel/bpf/btf.c b/kernel/bpf/btf.c
index 63d0ac7dfe2fb..eb12d4f705cce 100644
--- a/kernel/bpf/btf.c
+++ b/kernel/bpf/btf.c
@@ -4815,6 +4815,7 @@ static int btf_check_type_tags(struct btf_verifier_env *env,
 	n = btf_nr_types(btf);
 	for (i = start_id; i < n; i++) {
 		const struct btf_type *t;
+		int chain_limit = 32;
 		u32 cur_id = i;
 
 		t = btf_type_by_id(btf, i);
@@ -4827,6 +4828,10 @@ static int btf_check_type_tags(struct btf_verifier_env *env,
 
 		in_tags = btf_type_is_type_tag(t);
 		while (btf_type_is_modifier(t)) {
+			if (!chain_limit--) {
+				btf_verifier_log(env, "Max chain length or cycle detected");
+				return -ELOOP;
+			}
 			if (btf_type_is_type_tag(t)) {
 				if (!in_tags) {
 					btf_verifier_log(env, "Type tags don't precede modifiers");
-- 
GitLab


From f34fdcd4a0e7a0b92340ad7e48e7bcff9393fab5 Mon Sep 17 00:00:00 2001
From: Logan Gunthorpe <logang@deltatee.com>
Date: Wed, 8 Jun 2022 10:27:46 -0600
Subject: [PATCH 0627/1731] md/raid5-ppl: Fix argument order in
 bio_alloc_bioset()

bio_alloc_bioset() takes a block device, number of vectors, the
OP flags, the GFP mask and the bio set. However when the prototype
was changed, the callisite in ppl_do_flush() had the OP flags and
the GFP flags reversed. This introduced some sparse error:

  drivers/md/raid5-ppl.c:632:57: warning: incorrect type in argument 3
				    (different base types)
  drivers/md/raid5-ppl.c:632:57:    expected unsigned int opf
  drivers/md/raid5-ppl.c:632:57:    got restricted gfp_t [usertype]
  drivers/md/raid5-ppl.c:633:61: warning: incorrect type in argument 4
  				    (different base types)
  drivers/md/raid5-ppl.c:633:61:    expected restricted gfp_t [usertype]
				    gfp_mask
  drivers/md/raid5-ppl.c:633:61:    got unsigned long long

The sparse error introduction may not have been reported correctly by
0day due to other work that was cleaning up other sparse errors in this
area.

Fixes: 609be1066731 ("block: pass a block_device and opf to bio_alloc_bioset")
Cc: stable@vger.kernel.org # 5.18+
Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Song Liu <song@kernel.org>
---
 drivers/md/raid5-ppl.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/md/raid5-ppl.c b/drivers/md/raid5-ppl.c
index 973e2e06f19c2..0a2e4806b1ece 100644
--- a/drivers/md/raid5-ppl.c
+++ b/drivers/md/raid5-ppl.c
@@ -629,9 +629,9 @@ static void ppl_do_flush(struct ppl_io_unit *io)
 		if (bdev) {
 			struct bio *bio;
 
-			bio = bio_alloc_bioset(bdev, 0, GFP_NOIO,
+			bio = bio_alloc_bioset(bdev, 0,
 					       REQ_OP_WRITE | REQ_PREFLUSH,
-					       &ppl_conf->flush_bs);
+					       GFP_NOIO, &ppl_conf->flush_bs);
 			bio->bi_private = io;
 			bio->bi_end_io = ppl_flush_endio;
 
-- 
GitLab


From 60428d8bc27f52e8f1540f98e1b6ef0156d43f0d Mon Sep 17 00:00:00 2001
From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Date: Tue, 14 Jun 2022 15:01:33 +0300
Subject: [PATCH 0628/1731] x86/tdx: Fix early #VE handling

tdx_early_handle_ve() does not increment RIP after successfully
handling the exception.  That leads to infinite loop of exceptions.

Move RIP when exceptions are successfully handled.

[ dhansen: make problem statement more clear ]

Fixes: 32e72854fa5f ("x86/tdx: Port I/O: Add early boot support")
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Link: https://lkml.kernel.org/r/20220614120135.14812-2-kirill.shutemov@linux.intel.com
---
 arch/x86/coco/tdx/tdx.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c
index 03deb4d6920d5..faae53f8d5595 100644
--- a/arch/x86/coco/tdx/tdx.c
+++ b/arch/x86/coco/tdx/tdx.c
@@ -447,13 +447,17 @@ static bool handle_io(struct pt_regs *regs, u32 exit_qual)
 __init bool tdx_early_handle_ve(struct pt_regs *regs)
 {
 	struct ve_info ve;
+	bool ret;
 
 	tdx_get_ve_info(&ve);
 
 	if (ve.exit_reason != EXIT_REASON_IO_INSTRUCTION)
 		return false;
 
-	return handle_io(regs, ve.exit_qual);
+	ret = handle_io(regs, ve.exit_qual);
+	if (ret)
+		regs->ip += ve.instr_len;
+	return ret;
 }
 
 void tdx_get_ve_info(struct ve_info *ve)
-- 
GitLab


From 1556c3b4c7ed2c8f17f200d53897251fc68b7377 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Mon, 13 Jun 2022 09:53:14 -0700
Subject: [PATCH 0629/1731] drm/i915/pvc: Add recommended MMIO setting
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

As with past platforms, the bspec's performance tuning guide provides
recommended MMIO settings.  Although not technically "workarounds" we
apply these through the workaround framework to ensure that they're
re-applied at the proper times (e.g., on engine resets) and that any
conflicts with real workarounds are flagged.

Bspec: 72161
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220613165314.862029-1-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 5 +++++
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 2265570180371..07ef111947b8c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -981,6 +981,11 @@
 #define XEHP_L3SCQREG7				_MMIO(0xb188)
 #define   BLEND_FILL_CACHING_OPT_DIS		REG_BIT(3)
 
+#define XEHPC_L3SCRUB				_MMIO(0xb18c)
+#define   SCRUB_CL_DWNGRADE_SHARED		REG_BIT(12)
+#define   SCRUB_RATE_PER_BANK_MASK		REG_GENMASK(2, 0)
+#define   SCRUB_RATE_4B_PER_CLK			REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6)
+
 #define L3SQCREG1_CCS0				_MMIO(0xb200)
 #define   FLUSHALLNONCOH			REG_BIT(5)
 
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 1e982ac931dc9..c4af51144216a 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2679,6 +2679,15 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 {
 	struct drm_i915_private *i915 = engine->i915;
 
+	if (IS_PONTEVECCHIO(i915)) {
+		/*
+		 * The following is not actually a "workaround" but rather
+		 * a recommended tuning setting documented in the bspec's
+		 * performance guide section.
+		 */
+		wa_write(wal, XEHPC_L3SCRUB, SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
+	}
+
 	if (IS_XEHPSDV(i915)) {
 		/* Wa_1409954639 */
 		wa_masked_en(wal,
-- 
GitLab


From cdd85786f4b3b9273e4376e69aa95a2d71722764 Mon Sep 17 00:00:00 2001
From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Date: Tue, 14 Jun 2022 15:01:34 +0300
Subject: [PATCH 0630/1731] x86/tdx: Clarify RIP adjustments in #VE handler

After successful #VE handling, tdx_handle_virt_exception() has to move
RIP to the next instruction. The handler needs to know the length of the
instruction.

If the #VE happened due to instruction execution, the GET_VEINFO TDX
module call provides info on the instruction in R10, including its length.

For #VE due to EPT violation, the info in R10 is not populand and the
kernel must decode the instruction manually to find out its length.

Restructure the code to make it explicit that the instruction length
depends on the type of #VE. Make individual #VE handlers return
the instruction length on success or -errno on failure.

[ dhansen: fix up changelog and comments ]

Suggested-by: Dave Hansen <dave.hansen@intel.com>
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Link: https://lkml.kernel.org/r/20220614120135.14812-3-kirill.shutemov@linux.intel.com
---
 arch/x86/coco/tdx/tdx.c | 178 +++++++++++++++++++++++++++-------------
 1 file changed, 123 insertions(+), 55 deletions(-)

diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c
index faae53f8d5595..c8d44f4632838 100644
--- a/arch/x86/coco/tdx/tdx.c
+++ b/arch/x86/coco/tdx/tdx.c
@@ -124,6 +124,51 @@ static u64 get_cc_mask(void)
 	return BIT_ULL(gpa_width - 1);
 }
 
+/*
+ * The TDX module spec states that #VE may be injected for a limited set of
+ * reasons:
+ *
+ *  - Emulation of the architectural #VE injection on EPT violation;
+ *
+ *  - As a result of guest TD execution of a disallowed instruction,
+ *    a disallowed MSR access, or CPUID virtualization;
+ *
+ *  - A notification to the guest TD about anomalous behavior;
+ *
+ * The last one is opt-in and is not used by the kernel.
+ *
+ * The Intel Software Developer's Manual describes cases when instruction
+ * length field can be used in section "Information for VM Exits Due to
+ * Instruction Execution".
+ *
+ * For TDX, it ultimately means GET_VEINFO provides reliable instruction length
+ * information if #VE occurred due to instruction execution, but not for EPT
+ * violations.
+ */
+static int ve_instr_len(struct ve_info *ve)
+{
+	switch (ve->exit_reason) {
+	case EXIT_REASON_HLT:
+	case EXIT_REASON_MSR_READ:
+	case EXIT_REASON_MSR_WRITE:
+	case EXIT_REASON_CPUID:
+	case EXIT_REASON_IO_INSTRUCTION:
+		/* It is safe to use ve->instr_len for #VE due instructions */
+		return ve->instr_len;
+	case EXIT_REASON_EPT_VIOLATION:
+		/*
+		 * For EPT violations, ve->insn_len is not defined. For those,
+		 * the kernel must decode instructions manually and should not
+		 * be using this function.
+		 */
+		WARN_ONCE(1, "ve->instr_len is not defined for EPT violations");
+		return 0;
+	default:
+		WARN_ONCE(1, "Unexpected #VE-type: %lld\n", ve->exit_reason);
+		return ve->instr_len;
+	}
+}
+
 static u64 __cpuidle __halt(const bool irq_disabled, const bool do_sti)
 {
 	struct tdx_hypercall_args args = {
@@ -147,7 +192,7 @@ static u64 __cpuidle __halt(const bool irq_disabled, const bool do_sti)
 	return __tdx_hypercall(&args, do_sti ? TDX_HCALL_ISSUE_STI : 0);
 }
 
-static bool handle_halt(void)
+static int handle_halt(struct ve_info *ve)
 {
 	/*
 	 * Since non safe halt is mainly used in CPU offlining
@@ -158,9 +203,9 @@ static bool handle_halt(void)
 	const bool do_sti = false;
 
 	if (__halt(irq_disabled, do_sti))
-		return false;
+		return -EIO;
 
-	return true;
+	return ve_instr_len(ve);
 }
 
 void __cpuidle tdx_safe_halt(void)
@@ -180,7 +225,7 @@ void __cpuidle tdx_safe_halt(void)
 		WARN_ONCE(1, "HLT instruction emulation failed\n");
 }
 
-static bool read_msr(struct pt_regs *regs)
+static int read_msr(struct pt_regs *regs, struct ve_info *ve)
 {
 	struct tdx_hypercall_args args = {
 		.r10 = TDX_HYPERCALL_STANDARD,
@@ -194,14 +239,14 @@ static bool read_msr(struct pt_regs *regs)
 	 * (GHCI), section titled "TDG.VP.VMCALL<Instruction.RDMSR>".
 	 */
 	if (__tdx_hypercall(&args, TDX_HCALL_HAS_OUTPUT))
-		return false;
+		return -EIO;
 
 	regs->ax = lower_32_bits(args.r11);
 	regs->dx = upper_32_bits(args.r11);
-	return true;
+	return ve_instr_len(ve);
 }
 
-static bool write_msr(struct pt_regs *regs)
+static int write_msr(struct pt_regs *regs, struct ve_info *ve)
 {
 	struct tdx_hypercall_args args = {
 		.r10 = TDX_HYPERCALL_STANDARD,
@@ -215,10 +260,13 @@ static bool write_msr(struct pt_regs *regs)
 	 * can be found in TDX Guest-Host-Communication Interface
 	 * (GHCI) section titled "TDG.VP.VMCALL<Instruction.WRMSR>".
 	 */
-	return !__tdx_hypercall(&args, 0);
+	if (__tdx_hypercall(&args, 0))
+		return -EIO;
+
+	return ve_instr_len(ve);
 }
 
-static bool handle_cpuid(struct pt_regs *regs)
+static int handle_cpuid(struct pt_regs *regs, struct ve_info *ve)
 {
 	struct tdx_hypercall_args args = {
 		.r10 = TDX_HYPERCALL_STANDARD,
@@ -236,7 +284,7 @@ static bool handle_cpuid(struct pt_regs *regs)
 	 */
 	if (regs->ax < 0x40000000 || regs->ax > 0x4FFFFFFF) {
 		regs->ax = regs->bx = regs->cx = regs->dx = 0;
-		return true;
+		return ve_instr_len(ve);
 	}
 
 	/*
@@ -245,7 +293,7 @@ static bool handle_cpuid(struct pt_regs *regs)
 	 * (GHCI), section titled "VP.VMCALL<Instruction.CPUID>".
 	 */
 	if (__tdx_hypercall(&args, TDX_HCALL_HAS_OUTPUT))
-		return false;
+		return -EIO;
 
 	/*
 	 * As per TDX GHCI CPUID ABI, r12-r15 registers contain contents of
@@ -257,7 +305,7 @@ static bool handle_cpuid(struct pt_regs *regs)
 	regs->cx = args.r14;
 	regs->dx = args.r15;
 
-	return true;
+	return ve_instr_len(ve);
 }
 
 static bool mmio_read(int size, unsigned long addr, unsigned long *val)
@@ -283,7 +331,7 @@ static bool mmio_write(int size, unsigned long addr, unsigned long val)
 			       EPT_WRITE, addr, val);
 }
 
-static bool handle_mmio(struct pt_regs *regs, struct ve_info *ve)
+static int handle_mmio(struct pt_regs *regs, struct ve_info *ve)
 {
 	char buffer[MAX_INSN_SIZE];
 	unsigned long *reg, val;
@@ -294,34 +342,36 @@ static bool handle_mmio(struct pt_regs *regs, struct ve_info *ve)
 
 	/* Only in-kernel MMIO is supported */
 	if (WARN_ON_ONCE(user_mode(regs)))
-		return false;
+		return -EFAULT;
 
 	if (copy_from_kernel_nofault(buffer, (void *)regs->ip, MAX_INSN_SIZE))
-		return false;
+		return -EFAULT;
 
 	if (insn_decode(&insn, buffer, MAX_INSN_SIZE, INSN_MODE_64))
-		return false;
+		return -EINVAL;
 
 	mmio = insn_decode_mmio(&insn, &size);
 	if (WARN_ON_ONCE(mmio == MMIO_DECODE_FAILED))
-		return false;
+		return -EINVAL;
 
 	if (mmio != MMIO_WRITE_IMM && mmio != MMIO_MOVS) {
 		reg = insn_get_modrm_reg_ptr(&insn, regs);
 		if (!reg)
-			return false;
+			return -EINVAL;
 	}
 
-	ve->instr_len = insn.length;
-
 	/* Handle writes first */
 	switch (mmio) {
 	case MMIO_WRITE:
 		memcpy(&val, reg, size);
-		return mmio_write(size, ve->gpa, val);
+		if (!mmio_write(size, ve->gpa, val))
+			return -EIO;
+		return insn.length;
 	case MMIO_WRITE_IMM:
 		val = insn.immediate.value;
-		return mmio_write(size, ve->gpa, val);
+		if (!mmio_write(size, ve->gpa, val))
+			return -EIO;
+		return insn.length;
 	case MMIO_READ:
 	case MMIO_READ_ZERO_EXTEND:
 	case MMIO_READ_SIGN_EXTEND:
@@ -334,15 +384,15 @@ static bool handle_mmio(struct pt_regs *regs, struct ve_info *ve)
 		 * decoded or handled properly. It was likely not using io.h
 		 * helpers or accessed MMIO accidentally.
 		 */
-		return false;
+		return -EINVAL;
 	default:
 		WARN_ONCE(1, "Unknown insn_decode_mmio() decode value?");
-		return false;
+		return -EINVAL;
 	}
 
 	/* Handle reads */
 	if (!mmio_read(size, ve->gpa, &val))
-		return false;
+		return -EIO;
 
 	switch (mmio) {
 	case MMIO_READ:
@@ -364,13 +414,13 @@ static bool handle_mmio(struct pt_regs *regs, struct ve_info *ve)
 	default:
 		/* All other cases has to be covered with the first switch() */
 		WARN_ON_ONCE(1);
-		return false;
+		return -EINVAL;
 	}
 
 	if (extend_size)
 		memset(reg, extend_val, extend_size);
 	memcpy(reg, &val, size);
-	return true;
+	return insn.length;
 }
 
 static bool handle_in(struct pt_regs *regs, int size, int port)
@@ -421,13 +471,14 @@ static bool handle_out(struct pt_regs *regs, int size, int port)
  *
  * Return True on success or False on failure.
  */
-static bool handle_io(struct pt_regs *regs, u32 exit_qual)
+static int handle_io(struct pt_regs *regs, struct ve_info *ve)
 {
+	u32 exit_qual = ve->exit_qual;
 	int size, port;
-	bool in;
+	bool in, ret;
 
 	if (VE_IS_IO_STRING(exit_qual))
-		return false;
+		return -EIO;
 
 	in   = VE_IS_IO_IN(exit_qual);
 	size = VE_GET_IO_SIZE(exit_qual);
@@ -435,9 +486,13 @@ static bool handle_io(struct pt_regs *regs, u32 exit_qual)
 
 
 	if (in)
-		return handle_in(regs, size, port);
+		ret = handle_in(regs, size, port);
 	else
-		return handle_out(regs, size, port);
+		ret = handle_out(regs, size, port);
+	if (!ret)
+		return -EIO;
+
+	return ve_instr_len(ve);
 }
 
 /*
@@ -447,17 +502,19 @@ static bool handle_io(struct pt_regs *regs, u32 exit_qual)
 __init bool tdx_early_handle_ve(struct pt_regs *regs)
 {
 	struct ve_info ve;
-	bool ret;
+	int insn_len;
 
 	tdx_get_ve_info(&ve);
 
 	if (ve.exit_reason != EXIT_REASON_IO_INSTRUCTION)
 		return false;
 
-	ret = handle_io(regs, ve.exit_qual);
-	if (ret)
-		regs->ip += ve.instr_len;
-	return ret;
+	insn_len = handle_io(regs, &ve);
+	if (insn_len < 0)
+		return false;
+
+	regs->ip += insn_len;
+	return true;
 }
 
 void tdx_get_ve_info(struct ve_info *ve)
@@ -490,54 +547,65 @@ void tdx_get_ve_info(struct ve_info *ve)
 	ve->instr_info  = upper_32_bits(out.r10);
 }
 
-/* Handle the user initiated #VE */
-static bool virt_exception_user(struct pt_regs *regs, struct ve_info *ve)
+/*
+ * Handle the user initiated #VE.
+ *
+ * On success, returns the number of bytes RIP should be incremented (>=0)
+ * or -errno on error.
+ */
+static int virt_exception_user(struct pt_regs *regs, struct ve_info *ve)
 {
 	switch (ve->exit_reason) {
 	case EXIT_REASON_CPUID:
-		return handle_cpuid(regs);
+		return handle_cpuid(regs, ve);
 	default:
 		pr_warn("Unexpected #VE: %lld\n", ve->exit_reason);
-		return false;
+		return -EIO;
 	}
 }
 
-/* Handle the kernel #VE */
-static bool virt_exception_kernel(struct pt_regs *regs, struct ve_info *ve)
+/*
+ * Handle the kernel #VE.
+ *
+ * On success, returns the number of bytes RIP should be incremented (>=0)
+ * or -errno on error.
+ */
+static int virt_exception_kernel(struct pt_regs *regs, struct ve_info *ve)
 {
 	switch (ve->exit_reason) {
 	case EXIT_REASON_HLT:
-		return handle_halt();
+		return handle_halt(ve);
 	case EXIT_REASON_MSR_READ:
-		return read_msr(regs);
+		return read_msr(regs, ve);
 	case EXIT_REASON_MSR_WRITE:
-		return write_msr(regs);
+		return write_msr(regs, ve);
 	case EXIT_REASON_CPUID:
-		return handle_cpuid(regs);
+		return handle_cpuid(regs, ve);
 	case EXIT_REASON_EPT_VIOLATION:
 		return handle_mmio(regs, ve);
 	case EXIT_REASON_IO_INSTRUCTION:
-		return handle_io(regs, ve->exit_qual);
+		return handle_io(regs, ve);
 	default:
 		pr_warn("Unexpected #VE: %lld\n", ve->exit_reason);
-		return false;
+		return -EIO;
 	}
 }
 
 bool tdx_handle_virt_exception(struct pt_regs *regs, struct ve_info *ve)
 {
-	bool ret;
+	int insn_len;
 
 	if (user_mode(regs))
-		ret = virt_exception_user(regs, ve);
+		insn_len = virt_exception_user(regs, ve);
 	else
-		ret = virt_exception_kernel(regs, ve);
+		insn_len = virt_exception_kernel(regs, ve);
+	if (insn_len < 0)
+		return false;
 
 	/* After successful #VE handling, move the IP */
-	if (ret)
-		regs->ip += ve->instr_len;
+	regs->ip += insn_len;
 
-	return ret;
+	return true;
 }
 
 static bool tdx_tlb_flush_required(bool private)
-- 
GitLab


From 49d6a3c062a1026a5ba957c46f3603c372288ab6 Mon Sep 17 00:00:00 2001
From: Tianyu Lan <Tianyu.Lan@microsoft.com>
Date: Mon, 13 Jun 2022 21:45:53 -0400
Subject: [PATCH 0631/1731] x86/Hyper-V: Add SEV negotiate protocol support in
 Isolation VM

Hyper-V Isolation VM current code uses sev_es_ghcb_hv_call()
to read/write MSR via GHCB page and depends on the sev code.
This may cause regression when sev code changes interface
design.

The latest SEV-ES code requires to negotiate GHCB version before
reading/writing MSR via GHCB page and sev_es_ghcb_hv_call() doesn't
work for Hyper-V Isolation VM. Add Hyper-V ghcb related implementation
to decouple SEV and Hyper-V code. Negotiate GHCB version in the
hyperv_init() and use the version to communicate with Hyper-V
in the ghcb hv call function.

Fixes: 2ea29c5abbc2 ("x86/sev: Save the negotiated GHCB version")
Signed-off-by: Tianyu Lan <Tianyu.Lan@microsoft.com>
Reviewed-by: Michael Kelley <mikelley@microsoft.com>
Link: https://lore.kernel.org/r/20220614014553.1915929-1-ltykernel@gmail.com
Signed-off-by: Wei Liu <wei.liu@kernel.org>
---
 arch/x86/hyperv/hv_init.c       |  6 +++
 arch/x86/hyperv/ivm.c           | 84 ++++++++++++++++++++++++++++++---
 arch/x86/include/asm/mshyperv.h |  4 ++
 3 files changed, 88 insertions(+), 6 deletions(-)

diff --git a/arch/x86/hyperv/hv_init.c b/arch/x86/hyperv/hv_init.c
index 8b392b6b7b934..3de6d8b533672 100644
--- a/arch/x86/hyperv/hv_init.c
+++ b/arch/x86/hyperv/hv_init.c
@@ -13,6 +13,7 @@
 #include <linux/io.h>
 #include <asm/apic.h>
 #include <asm/desc.h>
+#include <asm/sev.h>
 #include <asm/hypervisor.h>
 #include <asm/hyperv-tlfs.h>
 #include <asm/mshyperv.h>
@@ -405,6 +406,11 @@ void __init hyperv_init(void)
 	}
 
 	if (hv_isolation_type_snp()) {
+		/* Negotiate GHCB Version. */
+		if (!hv_ghcb_negotiate_protocol())
+			hv_ghcb_terminate(SEV_TERM_SET_GEN,
+					  GHCB_SEV_ES_PROT_UNSUPPORTED);
+
 		hv_ghcb_pg = alloc_percpu(union hv_ghcb *);
 		if (!hv_ghcb_pg)
 			goto free_vp_assist_page;
diff --git a/arch/x86/hyperv/ivm.c b/arch/x86/hyperv/ivm.c
index 2b994117581e2..1dbcbd9da74d4 100644
--- a/arch/x86/hyperv/ivm.c
+++ b/arch/x86/hyperv/ivm.c
@@ -53,6 +53,8 @@ union hv_ghcb {
 	} hypercall;
 } __packed __aligned(HV_HYP_PAGE_SIZE);
 
+static u16 hv_ghcb_version __ro_after_init;
+
 u64 hv_ghcb_hypercall(u64 control, void *input, void *output, u32 input_size)
 {
 	union hv_ghcb *hv_ghcb;
@@ -96,12 +98,85 @@ u64 hv_ghcb_hypercall(u64 control, void *input, void *output, u32 input_size)
 	return status;
 }
 
+static inline u64 rd_ghcb_msr(void)
+{
+	return __rdmsr(MSR_AMD64_SEV_ES_GHCB);
+}
+
+static inline void wr_ghcb_msr(u64 val)
+{
+	native_wrmsrl(MSR_AMD64_SEV_ES_GHCB, val);
+}
+
+static enum es_result hv_ghcb_hv_call(struct ghcb *ghcb, u64 exit_code,
+				   u64 exit_info_1, u64 exit_info_2)
+{
+	/* Fill in protocol and format specifiers */
+	ghcb->protocol_version = hv_ghcb_version;
+	ghcb->ghcb_usage       = GHCB_DEFAULT_USAGE;
+
+	ghcb_set_sw_exit_code(ghcb, exit_code);
+	ghcb_set_sw_exit_info_1(ghcb, exit_info_1);
+	ghcb_set_sw_exit_info_2(ghcb, exit_info_2);
+
+	VMGEXIT();
+
+	if (ghcb->save.sw_exit_info_1 & GENMASK_ULL(31, 0))
+		return ES_VMM_ERROR;
+	else
+		return ES_OK;
+}
+
+void hv_ghcb_terminate(unsigned int set, unsigned int reason)
+{
+	u64 val = GHCB_MSR_TERM_REQ;
+
+	/* Tell the hypervisor what went wrong. */
+	val |= GHCB_SEV_TERM_REASON(set, reason);
+
+	/* Request Guest Termination from Hypvervisor */
+	wr_ghcb_msr(val);
+	VMGEXIT();
+
+	while (true)
+		asm volatile("hlt\n" : : : "memory");
+}
+
+bool hv_ghcb_negotiate_protocol(void)
+{
+	u64 ghcb_gpa;
+	u64 val;
+
+	/* Save ghcb page gpa. */
+	ghcb_gpa = rd_ghcb_msr();
+
+	/* Do the GHCB protocol version negotiation */
+	wr_ghcb_msr(GHCB_MSR_SEV_INFO_REQ);
+	VMGEXIT();
+	val = rd_ghcb_msr();
+
+	if (GHCB_MSR_INFO(val) != GHCB_MSR_SEV_INFO_RESP)
+		return false;
+
+	if (GHCB_MSR_PROTO_MAX(val) < GHCB_PROTOCOL_MIN ||
+	    GHCB_MSR_PROTO_MIN(val) > GHCB_PROTOCOL_MAX)
+		return false;
+
+	hv_ghcb_version = min_t(size_t, GHCB_MSR_PROTO_MAX(val),
+			     GHCB_PROTOCOL_MAX);
+
+	/* Write ghcb page back after negotiating protocol. */
+	wr_ghcb_msr(ghcb_gpa);
+	VMGEXIT();
+
+	return true;
+}
+
 void hv_ghcb_msr_write(u64 msr, u64 value)
 {
 	union hv_ghcb *hv_ghcb;
 	void **ghcb_base;
 	unsigned long flags;
-	struct es_em_ctxt ctxt;
 
 	if (!hv_ghcb_pg)
 		return;
@@ -120,8 +195,7 @@ void hv_ghcb_msr_write(u64 msr, u64 value)
 	ghcb_set_rax(&hv_ghcb->ghcb, lower_32_bits(value));
 	ghcb_set_rdx(&hv_ghcb->ghcb, upper_32_bits(value));
 
-	if (sev_es_ghcb_hv_call(&hv_ghcb->ghcb, false, &ctxt,
-				SVM_EXIT_MSR, 1, 0))
+	if (hv_ghcb_hv_call(&hv_ghcb->ghcb, SVM_EXIT_MSR, 1, 0))
 		pr_warn("Fail to write msr via ghcb %llx.\n", msr);
 
 	local_irq_restore(flags);
@@ -133,7 +207,6 @@ void hv_ghcb_msr_read(u64 msr, u64 *value)
 	union hv_ghcb *hv_ghcb;
 	void **ghcb_base;
 	unsigned long flags;
-	struct es_em_ctxt ctxt;
 
 	/* Check size of union hv_ghcb here. */
 	BUILD_BUG_ON(sizeof(union hv_ghcb) != HV_HYP_PAGE_SIZE);
@@ -152,8 +225,7 @@ void hv_ghcb_msr_read(u64 msr, u64 *value)
 	}
 
 	ghcb_set_rcx(&hv_ghcb->ghcb, msr);
-	if (sev_es_ghcb_hv_call(&hv_ghcb->ghcb, false, &ctxt,
-				SVM_EXIT_MSR, 0, 0))
+	if (hv_ghcb_hv_call(&hv_ghcb->ghcb, SVM_EXIT_MSR, 0, 0))
 		pr_warn("Fail to read msr via ghcb %llx.\n", msr);
 	else
 		*value = (u64)lower_32_bits(hv_ghcb->ghcb.save.rax)
diff --git a/arch/x86/include/asm/mshyperv.h b/arch/x86/include/asm/mshyperv.h
index a82f603d4312d..61f0c206bff0f 100644
--- a/arch/x86/include/asm/mshyperv.h
+++ b/arch/x86/include/asm/mshyperv.h
@@ -179,9 +179,13 @@ int hv_set_mem_host_visibility(unsigned long addr, int numpages, bool visible);
 #ifdef CONFIG_AMD_MEM_ENCRYPT
 void hv_ghcb_msr_write(u64 msr, u64 value);
 void hv_ghcb_msr_read(u64 msr, u64 *value);
+bool hv_ghcb_negotiate_protocol(void);
+void hv_ghcb_terminate(unsigned int set, unsigned int reason);
 #else
 static inline void hv_ghcb_msr_write(u64 msr, u64 value) {}
 static inline void hv_ghcb_msr_read(u64 msr, u64 *value) {}
+static inline bool hv_ghcb_negotiate_protocol(void) { return false; }
+static inline void hv_ghcb_terminate(unsigned int set, unsigned int reason) {}
 #endif
 
 extern bool hv_isolation_type_snp(void);
-- 
GitLab


From 6a1c3767d82ed8233de1263aa7da81595e176087 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <masahiroy@kernel.org>
Date: Sun, 12 Jun 2022 02:22:30 +0900
Subject: [PATCH 0632/1731] certs/blacklist_hashes.c: fix const confusion in
 certs blacklist
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This file fails to compile as follows:

  CC      certs/blacklist_hashes.o
certs/blacklist_hashes.c:4:1: error: ignoring attribute ‘section (".init.data")’ because it conflicts with previous ‘section (".init.rodata")’ [-Werror=attributes]
    4 | const char __initdata *const blacklist_hashes[] = {
      | ^~~~~
In file included from certs/blacklist_hashes.c:2:
certs/blacklist.h:5:38: note: previous declaration here
    5 | extern const char __initconst *const blacklist_hashes[];
      |                                      ^~~~~~~~~~~~~~~~

Apply the same fix as commit 2be04df5668d ("certs/blacklist_nohashes.c:
fix const confusion in certs blacklist").

Fixes: 734114f8782f ("KEYS: Add a system blacklist keyring")
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Reviewed-by: Jarkko Sakkinen <jarkko@kernel.org>
Reviewed-by: Mickaël Salaün <mic@linux.microsoft.com>
Signed-off-by: Jarkko Sakkinen <jarkko@kernel.org>
---
 certs/blacklist_hashes.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/certs/blacklist_hashes.c b/certs/blacklist_hashes.c
index 344892337be07..d5961aa3d3380 100644
--- a/certs/blacklist_hashes.c
+++ b/certs/blacklist_hashes.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 #include "blacklist.h"
 
-const char __initdata *const blacklist_hashes[] = {
+const char __initconst *const blacklist_hashes[] = {
 #include CONFIG_SYSTEM_BLACKLIST_HASH_LIST
 	, NULL
 };
-- 
GitLab


From 27b5b22d252c6d71a2a37a4bdf18d0be6d25ee5a Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <masahiroy@kernel.org>
Date: Sun, 12 Jun 2022 02:22:31 +0900
Subject: [PATCH 0633/1731] certs: fix and refactor
 CONFIG_SYSTEM_BLACKLIST_HASH_LIST build
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Commit addf466389d9 ("certs: Check that builtin blacklist hashes are
valid") was applied 8 months after the submission.

In the meantime, the base code had been removed by commit b8c96a6b466c
("certs: simplify $(srctree)/ handling and remove config_filename
macro").

Fix the Makefile.

Create a local copy of $(CONFIG_SYSTEM_BLACKLIST_HASH_LIST). It is
included from certs/blacklist_hashes.c and also works as a timestamp.

Send error messages from check-blacklist-hashes.awk to stderr instead
of stdout.

Fixes: addf466389d9 ("certs: Check that builtin blacklist hashes are valid")
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Reviewed-by: Jarkko Sakkinen <jarkko@kernel.org>
Reviewed-by: Mickaël Salaün <mic@linux.microsoft.com>
Signed-off-by: Jarkko Sakkinen <jarkko@kernel.org>
---
 certs/.gitignore         |  2 +-
 certs/Makefile           | 20 ++++++++++----------
 certs/blacklist_hashes.c |  2 +-
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/certs/.gitignore b/certs/.gitignore
index 56637aceaf81c..cec5465f31c1c 100644
--- a/certs/.gitignore
+++ b/certs/.gitignore
@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-only
-/blacklist_hashes_checked
+/blacklist_hash_list
 /extract-cert
 /x509_certificate_list
 /x509_revocation_list
diff --git a/certs/Makefile b/certs/Makefile
index cb1a9da3fc581..a8d628fd5f7b7 100644
--- a/certs/Makefile
+++ b/certs/Makefile
@@ -7,22 +7,22 @@ obj-$(CONFIG_SYSTEM_TRUSTED_KEYRING) += system_keyring.o system_certificates.o c
 obj-$(CONFIG_SYSTEM_BLACKLIST_KEYRING) += blacklist.o common.o
 obj-$(CONFIG_SYSTEM_REVOCATION_LIST) += revocation_certificates.o
 ifneq ($(CONFIG_SYSTEM_BLACKLIST_HASH_LIST),)
-quiet_cmd_check_blacklist_hashes = CHECK   $(patsubst "%",%,$(2))
-      cmd_check_blacklist_hashes = $(AWK) -f $(srctree)/scripts/check-blacklist-hashes.awk $(2); touch $@
 
-$(eval $(call config_filename,SYSTEM_BLACKLIST_HASH_LIST))
+$(obj)/blacklist_hashes.o: $(obj)/blacklist_hash_list
+CFLAGS_blacklist_hashes.o := -I $(obj)
 
-$(obj)/blacklist_hashes.o: $(obj)/blacklist_hashes_checked
+quiet_cmd_check_and_copy_blacklist_hash_list = GEN     $@
+      cmd_check_and_copy_blacklist_hash_list = \
+	$(AWK) -f $(srctree)/scripts/check-blacklist-hashes.awk $(CONFIG_SYSTEM_BLACKLIST_HASH_LIST) >&2; \
+	cat $(CONFIG_SYSTEM_BLACKLIST_HASH_LIST) > $@
 
-CFLAGS_blacklist_hashes.o += -I$(srctree)
-
-targets += blacklist_hashes_checked
-$(obj)/blacklist_hashes_checked: $(SYSTEM_BLACKLIST_HASH_LIST_SRCPREFIX)$(SYSTEM_BLACKLIST_HASH_LIST_FILENAME) scripts/check-blacklist-hashes.awk FORCE
-	$(call if_changed,check_blacklist_hashes,$(SYSTEM_BLACKLIST_HASH_LIST_SRCPREFIX)$(CONFIG_SYSTEM_BLACKLIST_HASH_LIST))
+$(obj)/blacklist_hash_list: $(CONFIG_SYSTEM_BLACKLIST_HASH_LIST) FORCE
+	$(call if_changed,check_and_copy_blacklist_hash_list)
 obj-$(CONFIG_SYSTEM_BLACKLIST_KEYRING) += blacklist_hashes.o
 else
 obj-$(CONFIG_SYSTEM_BLACKLIST_KEYRING) += blacklist_nohashes.o
 endif
+targets += blacklist_hash_list
 
 quiet_cmd_extract_certs  = CERT    $@
       cmd_extract_certs  = $(obj)/extract-cert $(extract-cert-in) $@
@@ -33,7 +33,7 @@ $(obj)/system_certificates.o: $(obj)/x509_certificate_list
 $(obj)/x509_certificate_list: $(CONFIG_SYSTEM_TRUSTED_KEYS) $(obj)/extract-cert FORCE
 	$(call if_changed,extract_certs)
 
-targets += x509_certificate_list blacklist_hashes_checked
+targets += x509_certificate_list
 
 # If module signing is requested, say by allyesconfig, but a key has not been
 # supplied, then one will need to be generated to make sure the build does not
diff --git a/certs/blacklist_hashes.c b/certs/blacklist_hashes.c
index d5961aa3d3380..86d66fe113489 100644
--- a/certs/blacklist_hashes.c
+++ b/certs/blacklist_hashes.c
@@ -2,6 +2,6 @@
 #include "blacklist.h"
 
 const char __initconst *const blacklist_hashes[] = {
-#include CONFIG_SYSTEM_BLACKLIST_HASH_LIST
+#include "blacklist_hash_list"
 	, NULL
 };
-- 
GitLab


From 5ee3d10f84d0a32fc11a55c70c204b6d81fd9ef6 Mon Sep 17 00:00:00 2001
From: Dave Wysochanski <dwysocha@redhat.com>
Date: Thu, 9 Jun 2022 20:46:29 -0400
Subject: [PATCH 0634/1731] NFSv4: Add FMODE_CAN_ODIRECT after successful open
 of a NFS4.x file

Commit a2ad63daa88b ("VFS: add FMODE_CAN_ODIRECT file flag")
added the FMODE_CAN_ODIRECT flag for NFSv3 but neglected to add
it for NFSv4.x.  This causes direct io on NFSv4.x to fail open
with EINVAL:
  mount -o vers=4.2 127.0.0.1:/export /mnt/nfs4
  dd if=/dev/zero of=/mnt/nfs4/file.bin bs=128k count=1 oflag=direct
  dd: failed to open '/mnt/nfs4/file.bin': Invalid argument
  dd of=/dev/null if=/mnt/nfs4/file.bin bs=128k count=1 iflag=direct
  dd: failed to open '/mnt/dir1/file1.bin': Invalid argument

Fixes: a2ad63daa88b ("VFS: add FMODE_CAN_ODIRECT file flag")
Signed-off-by: Dave Wysochanski <dwysocha@redhat.com>
Signed-off-by: Anna Schumaker <Anna.Schumaker@Netapp.com>
---
 fs/nfs/dir.c      | 1 +
 fs/nfs/nfs4file.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/fs/nfs/dir.c b/fs/nfs/dir.c
index a8ecdd527662c..0c4e8dd6aa968 100644
--- a/fs/nfs/dir.c
+++ b/fs/nfs/dir.c
@@ -2124,6 +2124,7 @@ int nfs_atomic_open(struct inode *dir, struct dentry *dentry,
 		}
 		goto out;
 	}
+	file->f_mode |= FMODE_CAN_ODIRECT;
 
 	err = nfs_finish_open(ctx, ctx->dentry, file, open_flags);
 	trace_nfs_atomic_open_exit(dir, ctx, open_flags, err);
diff --git a/fs/nfs/nfs4file.c b/fs/nfs/nfs4file.c
index 03d3a270eff4f..e88f6b18445ec 100644
--- a/fs/nfs/nfs4file.c
+++ b/fs/nfs/nfs4file.c
@@ -93,6 +93,7 @@ nfs4_file_open(struct inode *inode, struct file *filp)
 	nfs_file_set_open_context(filp, ctx);
 	nfs_fscache_open_file(inode, filp);
 	err = 0;
+	filp->f_mode |= FMODE_CAN_ODIRECT;
 
 out_put_ctx:
 	put_nfs_open_context(ctx);
-- 
GitLab


From c3230283e2819a69dad2cf7a63143fde8bab8b5c Mon Sep 17 00:00:00 2001
From: Petr Mladek <pmladek@suse.com>
Date: Wed, 15 Jun 2022 18:28:04 +0200
Subject: [PATCH 0635/1731] printk: Block console kthreads when direct printing
 will be required

There are known situations when the console kthreads are not
reliable or does not work in principle, for example, early boot,
panic, shutdown.

For these situations there is the direct (legacy) mode when printk() tries
to get console_lock() and flush the messages directly. It works very well
during the early boot when the console kthreads are not available at all.
It gets more complicated in the other situations when console kthreads
might be actively printing and block console_trylock() in printk().

The same problem is in the legacy code as well. Any console_lock()
owner could block console_trylock() in printk(). It is solved by
a trick that the current console_lock() owner is responsible for
printing all pending messages. It is actually the reason why there
is the risk of softlockups and why the console kthreads were
introduced.

The console kthreads use the same approach. They are responsible
for printing the messages by definition. So that they handle
the messages anytime when they are awake and see new ones.
The global console_lock is available when there is nothing
to do.

It should work well when the problematic context is correctly
detected and printk() switches to the direct mode. But it seems
that it is not enough in practice. There are reports that
the messages are not printed during panic() or shutdown()
even though printk() tries to use the direct mode here.

The problem seems to be that console kthreads become active in these
situation as well. They steel the job before other CPUs are stopped.
Then they are stopped in the middle of the job and block the global
console_lock.

First part of the solution is to block console kthreads when
the system is in a problematic state and requires the direct
printk() mode.

Link: https://lore.kernel.org/r/20220610205038.GA3050413@paulmck-ThinkPad-P17-Gen-1
Link: https://lore.kernel.org/r/CAMdYzYpF4FNTBPZsEFeWRuEwSies36QM_As8osPWZSr2q-viEA@mail.gmail.com
Suggested-by: John Ogness <john.ogness@linutronix.de>
Tested-by: Paul E. McKenney <paulmck@kernel.org>
Signed-off-by: Petr Mladek <pmladek@suse.com>
Link: https://lore.kernel.org/r/20220615162805.27962-2-pmladek@suse.com
---
 kernel/printk/printk.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c
index ea3dd55709e72..45c6c2b0b1044 100644
--- a/kernel/printk/printk.c
+++ b/kernel/printk/printk.c
@@ -3729,7 +3729,9 @@ static bool printer_should_wake(struct console *con, u64 seq)
 		return true;
 
 	if (con->blocked ||
-	    console_kthreads_atomically_blocked()) {
+	    console_kthreads_atomically_blocked() ||
+	    system_state > SYSTEM_RUNNING ||
+	    oops_in_progress) {
 		return false;
 	}
 
-- 
GitLab


From b87f02307d3cfbda768520f0687c51ca77e14fc3 Mon Sep 17 00:00:00 2001
From: Petr Mladek <pmladek@suse.com>
Date: Wed, 15 Jun 2022 18:28:05 +0200
Subject: [PATCH 0636/1731] printk: Wait for the global console lock when the
 system is going down

There are reports that the console kthreads block the global console
lock when the system is going down, for example, reboot, panic.

First part of the solution was to block kthreads in these problematic
system states so they stopped handling newly added messages.

Second part of the solution is to wait when for the kthreads when
they are actively printing. It solves the problem when a message
was printed before the system entered the problematic state and
the kthreads managed to step in.

A busy waiting has to be used because panic() can be called in any
context and in an unknown state of the scheduler.

There must be a timeout because the kthread might get stuck or sleeping
and never release the lock. The timeout 10s is an arbitrary value
inspired by the softlockup timeout.

Link: https://lore.kernel.org/r/20220610205038.GA3050413@paulmck-ThinkPad-P17-Gen-1
Link: https://lore.kernel.org/r/CAMdYzYpF4FNTBPZsEFeWRuEwSies36QM_As8osPWZSr2q-viEA@mail.gmail.com
Signed-off-by: Petr Mladek <pmladek@suse.com>
Tested-by: Paul E. McKenney <paulmck@kernel.org>
Link: https://lore.kernel.org/r/20220615162805.27962-3-pmladek@suse.com
---
 include/linux/printk.h      |  5 +++++
 kernel/panic.c              |  2 ++
 kernel/printk/internal.h    |  2 ++
 kernel/printk/printk.c      |  4 ++++
 kernel/printk/printk_safe.c | 32 ++++++++++++++++++++++++++++++++
 kernel/reboot.c             |  2 ++
 6 files changed, 47 insertions(+)

diff --git a/include/linux/printk.h b/include/linux/printk.h
index cd26aab0ab2a0..c1e07c0652c7c 100644
--- a/include/linux/printk.h
+++ b/include/linux/printk.h
@@ -174,6 +174,7 @@ extern void printk_prefer_direct_enter(void);
 extern void printk_prefer_direct_exit(void);
 
 extern bool pr_flush(int timeout_ms, bool reset_on_progress);
+extern void try_block_console_kthreads(int timeout_ms);
 
 /*
  * Please don't use printk_ratelimit(), because it shares ratelimiting state
@@ -238,6 +239,10 @@ static inline bool pr_flush(int timeout_ms, bool reset_on_progress)
 	return true;
 }
 
+static inline void try_block_console_kthreads(int timeout_ms)
+{
+}
+
 static inline int printk_ratelimit(void)
 {
 	return 0;
diff --git a/kernel/panic.c b/kernel/panic.c
index 6737b23322753..fe73d18ecdf02 100644
--- a/kernel/panic.c
+++ b/kernel/panic.c
@@ -273,6 +273,7 @@ void panic(const char *fmt, ...)
 		 * unfortunately means it may not be hardened to work in a
 		 * panic situation.
 		 */
+		try_block_console_kthreads(10000);
 		smp_send_stop();
 	} else {
 		/*
@@ -280,6 +281,7 @@ void panic(const char *fmt, ...)
 		 * kmsg_dump, we will need architecture dependent extra
 		 * works in addition to stopping other CPUs.
 		 */
+		try_block_console_kthreads(10000);
 		crash_smp_send_stop();
 	}
 
diff --git a/kernel/printk/internal.h b/kernel/printk/internal.h
index d947ca6c84f99..e7d8578860adf 100644
--- a/kernel/printk/internal.h
+++ b/kernel/printk/internal.h
@@ -20,6 +20,8 @@ enum printk_info_flags {
 	LOG_CONT	= 8,	/* text is a fragment of a continuation line */
 };
 
+extern bool block_console_kthreads;
+
 __printf(4, 0)
 int vprintk_store(int facility, int level,
 		  const struct dev_printk_info *dev_info,
diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c
index 45c6c2b0b1044..b095fb5f5f61b 100644
--- a/kernel/printk/printk.c
+++ b/kernel/printk/printk.c
@@ -250,6 +250,9 @@ static atomic_t console_kthreads_active = ATOMIC_INIT(0);
 #define console_kthread_printing_exit() \
 	atomic_dec(&console_kthreads_active)
 
+/* Block console kthreads to avoid processing new messages. */
+bool block_console_kthreads;
+
 /*
  * Helper macros to handle lockdep when locking/unlocking console_sem. We use
  * macros instead of functions so that _RET_IP_ contains useful information.
@@ -3730,6 +3733,7 @@ static bool printer_should_wake(struct console *con, u64 seq)
 
 	if (con->blocked ||
 	    console_kthreads_atomically_blocked() ||
+	    block_console_kthreads ||
 	    system_state > SYSTEM_RUNNING ||
 	    oops_in_progress) {
 		return false;
diff --git a/kernel/printk/printk_safe.c b/kernel/printk/printk_safe.c
index ef0f9a2044da1..caac4de1ea59a 100644
--- a/kernel/printk/printk_safe.c
+++ b/kernel/printk/printk_safe.c
@@ -8,7 +8,9 @@
 #include <linux/smp.h>
 #include <linux/cpumask.h>
 #include <linux/printk.h>
+#include <linux/console.h>
 #include <linux/kprobes.h>
+#include <linux/delay.h>
 
 #include "internal.h"
 
@@ -50,3 +52,33 @@ asmlinkage int vprintk(const char *fmt, va_list args)
 	return vprintk_default(fmt, args);
 }
 EXPORT_SYMBOL(vprintk);
+
+/**
+ * try_block_console_kthreads() - Try to block console kthreads and
+ *	make the global console_lock() avaialble
+ *
+ * @timeout_ms:        The maximum time (in ms) to wait.
+ *
+ * Prevent console kthreads from starting processing new messages. Wait
+ * until the global console_lock() become available.
+ *
+ * Context: Can be called in any context.
+ */
+void try_block_console_kthreads(int timeout_ms)
+{
+	block_console_kthreads = true;
+
+	/* Do not wait when the console lock could not be safely taken. */
+	if (this_cpu_read(printk_context) || in_nmi())
+		return;
+
+	while (timeout_ms > 0) {
+		if (console_trylock()) {
+			console_unlock();
+			return;
+		}
+
+		udelay(1000);
+		timeout_ms -= 1;
+	}
+}
diff --git a/kernel/reboot.c b/kernel/reboot.c
index 4177645e74d6a..3103636855020 100644
--- a/kernel/reboot.c
+++ b/kernel/reboot.c
@@ -74,6 +74,7 @@ void kernel_restart_prepare(char *cmd)
 {
 	blocking_notifier_call_chain(&reboot_notifier_list, SYS_RESTART, cmd);
 	system_state = SYSTEM_RESTART;
+	try_block_console_kthreads(10000);
 	usermodehelper_disable();
 	device_shutdown();
 }
@@ -262,6 +263,7 @@ static void kernel_shutdown_prepare(enum system_states state)
 	blocking_notifier_call_chain(&reboot_notifier_list,
 		(state == SYSTEM_HALT) ? SYS_HALT : SYS_POWER_OFF, NULL);
 	system_state = state;
+	try_block_console_kthreads(10000);
 	usermodehelper_disable();
 	device_shutdown();
 }
-- 
GitLab


From 311e03c29c255665e10a31910308de3777f21274 Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Fri, 27 May 2022 10:23:40 -0700
Subject: [PATCH 0637/1731] drm/msm/gem: Separate object and vma unpin

Previously the BO_PINNED state in the submit was tracking two related
but different things: (1) that the buffer object was pinned, and (2)
that the vma (mapping within a set of pagetables) was pinned.  But with
fenced vma unpin (needed so that userspace couldn't race with retire
path for releasing a vma) these two were decoupled.  The fact that the
BO_PINNED flag was already cleared meant that we leaked the bo pin count
which should have been dropped when the submit was retired.

So split this state into BO_OBJ_PINNED and BO_VMA_PINNED, so they can be
dropped independently.

Fixes: 95d1deb02a9c ("drm/msm/gem: Add fenced vma unpin")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/487559/
Link: https://lore.kernel.org/r/20220527172341.2151005-1-robdclark@gmail.com
---
 drivers/gpu/drm/msm/msm_gem.c        |  7 +++----
 drivers/gpu/drm/msm/msm_gem.h        | 11 ++++++-----
 drivers/gpu/drm/msm/msm_gem_submit.c | 18 ++++++++++++------
 drivers/gpu/drm/msm/msm_ringbuffer.c |  2 +-
 4 files changed, 22 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 52fe6428a3411..916e7f418fe1a 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -439,14 +439,12 @@ int msm_gem_pin_vma_locked(struct drm_gem_object *obj, struct msm_gem_vma *vma)
 	return ret;
 }
 
-void msm_gem_unpin_vma_locked(struct drm_gem_object *obj, struct msm_gem_vma *vma)
+void msm_gem_unpin_locked(struct drm_gem_object *obj)
 {
 	struct msm_gem_object *msm_obj = to_msm_bo(obj);
 
 	GEM_WARN_ON(!msm_gem_is_locked(obj));
 
-	msm_gem_unpin_vma(vma);
-
 	msm_obj->pin_count--;
 	GEM_WARN_ON(msm_obj->pin_count < 0);
 
@@ -586,7 +584,8 @@ void msm_gem_unpin_iova(struct drm_gem_object *obj,
 	msm_gem_lock(obj);
 	vma = lookup_vma(obj, aspace);
 	if (!GEM_WARN_ON(!vma)) {
-		msm_gem_unpin_vma_locked(obj, vma);
+		msm_gem_unpin_vma(vma);
+		msm_gem_unpin_locked(obj);
 	}
 	msm_gem_unlock(obj);
 }
diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h
index c75d3b879a53b..6b7d5bb3b575f 100644
--- a/drivers/gpu/drm/msm/msm_gem.h
+++ b/drivers/gpu/drm/msm/msm_gem.h
@@ -145,7 +145,7 @@ struct msm_gem_object {
 
 uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
 int msm_gem_pin_vma_locked(struct drm_gem_object *obj, struct msm_gem_vma *vma);
-void msm_gem_unpin_vma_locked(struct drm_gem_object *obj, struct msm_gem_vma *vma);
+void msm_gem_unpin_locked(struct drm_gem_object *obj);
 struct msm_gem_vma *msm_gem_get_vma_locked(struct drm_gem_object *obj,
 					   struct msm_gem_address_space *aspace);
 int msm_gem_get_iova(struct drm_gem_object *obj,
@@ -377,10 +377,11 @@ struct msm_gem_submit {
 	} *cmd;  /* array of size nr_cmds */
 	struct {
 /* make sure these don't conflict w/ MSM_SUBMIT_BO_x */
-#define BO_VALID    0x8000   /* is current addr in cmdstream correct/valid? */
-#define BO_LOCKED   0x4000   /* obj lock is held */
-#define BO_ACTIVE   0x2000   /* active refcnt is held */
-#define BO_PINNED   0x1000   /* obj is pinned and on active list */
+#define BO_VALID	0x8000	/* is current addr in cmdstream correct/valid? */
+#define BO_LOCKED	0x4000	/* obj lock is held */
+#define BO_ACTIVE	0x2000	/* active refcnt is held */
+#define BO_OBJ_PINNED	0x1000	/* obj (pages) is pinned and on active list */
+#define BO_VMA_PINNED	0x0800	/* vma (virtual address) is pinned */
 		uint32_t flags;
 		union {
 			struct msm_gem_object *obj;
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c
index 9cd8c8708990b..286124008445d 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -232,8 +232,11 @@ static void submit_cleanup_bo(struct msm_gem_submit *submit, int i,
 	 */
 	submit->bos[i].flags &= ~cleanup_flags;
 
-	if (flags & BO_PINNED)
-		msm_gem_unpin_vma_locked(obj, submit->bos[i].vma);
+	if (flags & BO_VMA_PINNED)
+		msm_gem_unpin_vma(submit->bos[i].vma);
+
+	if (flags & BO_OBJ_PINNED)
+		msm_gem_unpin_locked(obj);
 
 	if (flags & BO_ACTIVE)
 		msm_gem_active_put(obj);
@@ -244,7 +247,9 @@ static void submit_cleanup_bo(struct msm_gem_submit *submit, int i,
 
 static void submit_unlock_unpin_bo(struct msm_gem_submit *submit, int i)
 {
-	submit_cleanup_bo(submit, i, BO_PINNED | BO_ACTIVE | BO_LOCKED);
+	unsigned cleanup_flags = BO_VMA_PINNED | BO_OBJ_PINNED |
+				 BO_ACTIVE | BO_LOCKED;
+	submit_cleanup_bo(submit, i, cleanup_flags);
 
 	if (!(submit->bos[i].flags & BO_VALID))
 		submit->bos[i].iova = 0;
@@ -377,7 +382,7 @@ static int submit_pin_objects(struct msm_gem_submit *submit)
 		if (ret)
 			break;
 
-		submit->bos[i].flags |= BO_PINNED;
+		submit->bos[i].flags |= BO_OBJ_PINNED | BO_VMA_PINNED;
 		submit->bos[i].vma = vma;
 
 		if (vma->iova == submit->bos[i].iova) {
@@ -511,7 +516,7 @@ static void submit_cleanup(struct msm_gem_submit *submit, bool error)
 	unsigned i;
 
 	if (error)
-		cleanup_flags |= BO_PINNED | BO_ACTIVE;
+		cleanup_flags |= BO_VMA_PINNED | BO_OBJ_PINNED | BO_ACTIVE;
 
 	for (i = 0; i < submit->nr_bos; i++) {
 		struct msm_gem_object *msm_obj = submit->bos[i].obj;
@@ -529,7 +534,8 @@ void msm_submit_retire(struct msm_gem_submit *submit)
 		struct drm_gem_object *obj = &submit->bos[i].obj->base;
 
 		msm_gem_lock(obj);
-		submit_cleanup_bo(submit, i, BO_PINNED | BO_ACTIVE);
+		/* Note, VMA already fence-unpinned before submit: */
+		submit_cleanup_bo(submit, i, BO_OBJ_PINNED | BO_ACTIVE);
 		msm_gem_unlock(obj);
 		drm_gem_object_put(obj);
 	}
diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c
index 43066320ff8c9..56eecb4a72dc6 100644
--- a/drivers/gpu/drm/msm/msm_ringbuffer.c
+++ b/drivers/gpu/drm/msm/msm_ringbuffer.c
@@ -25,7 +25,7 @@ static struct dma_fence *msm_job_run(struct drm_sched_job *job)
 
 		msm_gem_lock(obj);
 		msm_gem_unpin_vma_fenced(submit->bos[i].vma, fctx);
-		submit->bos[i].flags &= ~BO_PINNED;
+		submit->bos[i].flags &= ~BO_VMA_PINNED;
 		msm_gem_unlock(obj);
 	}
 
-- 
GitLab


From b4d329c451a299323b26039df97b32896fb46abc Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Fri, 10 Jun 2022 10:20:55 -0700
Subject: [PATCH 0638/1731] drm/msm/gem: Drop early returns in close/purge vma

Keep the warn, but drop the early return.  If we do manage to hit this
sort of issue, skipping the cleanup just makes things worse (dangling
drm_mm_nodes when the msm_gem_vma is freed, etc).  Whereas the worst
that happens if we tear down a mapping the GPU is accessing is that we
get GPU iova faults, but otherwise the world keeps spinning.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Reported-by: Steev Klimaszewski <steev@kali.org>
Patchwork: https://patchwork.freedesktop.org/patch/489115/
Link: https://lore.kernel.org/r/20220610172055.2337977-1-robdclark@gmail.com
---
 drivers/gpu/drm/msm/msm_gem_vma.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_gem_vma.c b/drivers/gpu/drm/msm/msm_gem_vma.c
index 3c1dc9241831b..c471aebcdbab2 100644
--- a/drivers/gpu/drm/msm/msm_gem_vma.c
+++ b/drivers/gpu/drm/msm/msm_gem_vma.c
@@ -62,8 +62,7 @@ void msm_gem_purge_vma(struct msm_gem_address_space *aspace,
 	unsigned size = vma->node.size;
 
 	/* Print a message if we try to purge a vma in use */
-	if (GEM_WARN_ON(msm_gem_vma_inuse(vma)))
-		return;
+	GEM_WARN_ON(msm_gem_vma_inuse(vma));
 
 	/* Don't do anything if the memory isn't mapped */
 	if (!vma->mapped)
@@ -128,8 +127,7 @@ msm_gem_map_vma(struct msm_gem_address_space *aspace,
 void msm_gem_close_vma(struct msm_gem_address_space *aspace,
 		struct msm_gem_vma *vma)
 {
-	if (GEM_WARN_ON(msm_gem_vma_inuse(vma) || vma->mapped))
-		return;
+	GEM_WARN_ON(msm_gem_vma_inuse(vma) || vma->mapped);
 
 	spin_lock(&aspace->lock);
 	if (vma->iova)
-- 
GitLab


From ef79c396c664be99d0c5660dc75fe863c1e20315 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Christian=20G=C3=B6ttsche?= <cgzones@googlemail.com>
Date: Wed, 15 Jun 2022 17:44:31 +0200
Subject: [PATCH 0639/1731] audit: free module name
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Reset the type of the record last as the helper `audit_free_module()`
depends on it.

    unreferenced object 0xffff888153b707f0 (size 16):
      comm "modprobe", pid 1319, jiffies 4295110033 (age 1083.016s)
      hex dump (first 16 bytes):
        62 69 6e 66 6d 74 5f 6d 69 73 63 00 6b 6b 6b a5  binfmt_misc.kkk.
      backtrace:
        [<ffffffffa07dbf9b>] kstrdup+0x2b/0x50
        [<ffffffffa04b0a9d>] __audit_log_kern_module+0x4d/0xf0
        [<ffffffffa03b6664>] load_module+0x9d4/0x2e10
        [<ffffffffa03b8f44>] __do_sys_finit_module+0x114/0x1b0
        [<ffffffffa1f47124>] do_syscall_64+0x34/0x80
        [<ffffffffa200007e>] entry_SYSCALL_64_after_hwframe+0x46/0xb0

Cc: stable@vger.kernel.org
Fixes: 12c5e81d3fd0 ("audit: prepare audit_context for use in calling contexts beyond syscalls")
Signed-off-by: Christian Göttsche <cgzones@googlemail.com>
Signed-off-by: Paul Moore <paul@paul-moore.com>
---
 kernel/auditsc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/auditsc.c b/kernel/auditsc.c
index f3a2abd6d1a19..3a8c9d744800a 100644
--- a/kernel/auditsc.c
+++ b/kernel/auditsc.c
@@ -1014,10 +1014,10 @@ static void audit_reset_context(struct audit_context *ctx)
 	ctx->target_comm[0] = '\0';
 	unroll_tree_refs(ctx, NULL, 0);
 	WARN_ON(!list_empty(&ctx->killed_trees));
-	ctx->type = 0;
 	audit_free_module(ctx);
 	ctx->fds[0] = -1;
 	audit_proctitle_free(ctx);
+	ctx->type = 0; /* reset last for audit_free_*() */
 }
 
 static inline struct audit_context *audit_alloc_context(enum audit_state state)
-- 
GitLab


From a79e69c8714f416bd324952d06d1dd7bce3f35bf Mon Sep 17 00:00:00 2001
From: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Date: Mon, 13 Jun 2022 10:51:00 +0200
Subject: [PATCH 0640/1731] MAINTAINERS: add include/dt-bindings/clock to
 COMMON CLK FRAMEWORK

Maintainers of the directory Documentation/devicetree/bindings/clock
are also the maintainers of the corresponding directory in
include/dt-bindings/clock.

Add the file entry for include/dt-bindings/clock to the appropriate
section in MAINTAINERS.

Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Link: https://lore.kernel.org/r/20220613085100.402-1-lukas.bulwahn@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index a6d3bd9d2a8d0..c1abc53f9e91b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4952,6 +4952,7 @@ Q:	http://patchwork.kernel.org/project/linux-clk/list/
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
 F:	Documentation/devicetree/bindings/clock/
 F:	drivers/clk/
+F:	include/dt-bindings/clock/
 F:	include/linux/clk-pr*
 F:	include/linux/clk/
 F:	include/linux/of_clk.h
-- 
GitLab


From cad140d00899e7a9cb6fe93b282051df589e671c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Christian=20G=C3=B6ttsche?= <cgzones@googlemail.com>
Date: Wed, 15 Jun 2022 17:38:39 +0200
Subject: [PATCH 0641/1731] selinux: free contexts previously transferred in
 selinux_add_opt()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

`selinux_add_opt()` stopped taking ownership of the passed context since
commit 70f4169ab421 ("selinux: parse contexts for mount options early").

    unreferenced object 0xffff888114dfd140 (size 64):
      comm "mount", pid 15182, jiffies 4295687028 (age 796.340s)
      hex dump (first 32 bytes):
        73 79 73 74 65 6d 5f 75 3a 6f 62 6a 65 63 74 5f  system_u:object_
        72 3a 74 65 73 74 5f 66 69 6c 65 73 79 73 74 65  r:test_filesyste
      backtrace:
        [<ffffffffa07dbef4>] kmemdup_nul+0x24/0x80
        [<ffffffffa0d34253>] selinux_sb_eat_lsm_opts+0x293/0x560
        [<ffffffffa0d13f08>] security_sb_eat_lsm_opts+0x58/0x80
        [<ffffffffa0af1eb2>] generic_parse_monolithic+0x82/0x180
        [<ffffffffa0a9c1a5>] do_new_mount+0x1f5/0x550
        [<ffffffffa0a9eccb>] path_mount+0x2ab/0x1570
        [<ffffffffa0aa019e>] __x64_sys_mount+0x20e/0x280
        [<ffffffffa1f47124>] do_syscall_64+0x34/0x80
        [<ffffffffa200007e>] entry_SYSCALL_64_after_hwframe+0x46/0xb0

    unreferenced object 0xffff888108e71640 (size 64):
      comm "fsmount", pid 7607, jiffies 4295044974 (age 1601.016s)
      hex dump (first 32 bytes):
        73 79 73 74 65 6d 5f 75 3a 6f 62 6a 65 63 74 5f  system_u:object_
        72 3a 74 65 73 74 5f 66 69 6c 65 73 79 73 74 65  r:test_filesyste
      backtrace:
        [<ffffffff861dc2b1>] memdup_user+0x21/0x90
        [<ffffffff861dc367>] strndup_user+0x47/0xa0
        [<ffffffff864f6965>] __do_sys_fsconfig+0x485/0x9f0
        [<ffffffff87940124>] do_syscall_64+0x34/0x80
        [<ffffffff87a0007e>] entry_SYSCALL_64_after_hwframe+0x46/0xb0

Cc: stable@vger.kernel.org
Fixes: 70f4169ab421 ("selinux: parse contexts for mount options early")
Signed-off-by: Christian Göttsche <cgzones@googlemail.com>
Signed-off-by: Paul Moore <paul@paul-moore.com>
---
 security/selinux/hooks.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/security/selinux/hooks.c b/security/selinux/hooks.c
index beceb89f68d9c..1bbd53321d133 100644
--- a/security/selinux/hooks.c
+++ b/security/selinux/hooks.c
@@ -2600,8 +2600,9 @@ static int selinux_sb_eat_lsm_opts(char *options, void **mnt_opts)
 				}
 			}
 			rc = selinux_add_opt(token, arg, mnt_opts);
+			kfree(arg);
+			arg = NULL;
 			if (unlikely(rc)) {
-				kfree(arg);
 				goto free_opt;
 			}
 		} else {
@@ -2792,17 +2793,13 @@ static int selinux_fs_context_parse_param(struct fs_context *fc,
 					  struct fs_parameter *param)
 {
 	struct fs_parse_result result;
-	int opt, rc;
+	int opt;
 
 	opt = fs_parse(fc, selinux_fs_parameters, param, &result);
 	if (opt < 0)
 		return opt;
 
-	rc = selinux_add_opt(opt, param->string, &fc->security);
-	if (!rc)
-		param->string = NULL;
-
-	return rc;
+	return selinux_add_opt(opt, param->string, &fc->security);
 }
 
 /* inode security operations */
-- 
GitLab


From f4288f01820e2d57722d21874c1fda661003c9b9 Mon Sep 17 00:00:00 2001
From: "Darrick J. Wong" <djwong@kernel.org>
Date: Sun, 5 Jun 2022 18:51:22 -0700
Subject: [PATCH 0642/1731] xfs: fix TOCTOU race involving the new logged
 xattrs control knob

I found a race involving the larp control knob, aka the debugging knob
that lets developers enable logging of extended attribute updates:

Thread 1			Thread 2

echo 0 > /sys/fs/xfs/debug/larp
				setxattr(REPLACE)
				xfs_has_larp (returns false)
				xfs_attr_set

echo 1 > /sys/fs/xfs/debug/larp

				xfs_attr_defer_replace
				xfs_attr_init_replace_state
				xfs_has_larp (returns true)
				xfs_attr_init_remove_state

				<oops, wrong DAS state!>

This isn't a particularly severe problem right now because xattr logging
is only enabled when CONFIG_XFS_DEBUG=y, and developers *should* know
what they're doing.

However, the eventual intent is that callers should be able to ask for
the assistance of the log in persisting xattr updates.  This capability
might not be required for /all/ callers, which means that dynamic
control must work correctly.  Once an xattr update has decided whether
or not to use logged xattrs, it needs to stay in that mode until the end
of the operation regardless of what subsequent parallel operations might
do.

Therefore, it is an error to continue sampling xfs_globals.larp once
xfs_attr_change has made a decision about larp, and it was not correct
for me to have told Allison that ->create_intent functions can sample
the global log incompat feature bitfield to decide to elide a log item.

Instead, create a new op flag for the xfs_da_args structure, and convert
all other callers of xfs_has_larp and xfs_sb_version_haslogxattrs within
the attr update state machine to look for the operations flag.

Signed-off-by: Darrick J. Wong <djwong@kernel.org>
Reviewed-by: Allison Henderson <allison.henderson@oracle.com>
---
 fs/xfs/libxfs/xfs_attr.c      |  6 ++++--
 fs/xfs/libxfs/xfs_attr.h      | 12 +-----------
 fs/xfs/libxfs/xfs_attr_leaf.c |  2 +-
 fs/xfs/libxfs/xfs_da_btree.h  |  4 +++-
 fs/xfs/xfs_attr_item.c        | 15 +++++++++------
 fs/xfs/xfs_xattr.c            | 17 ++++++++++++++++-
 6 files changed, 34 insertions(+), 22 deletions(-)

diff --git a/fs/xfs/libxfs/xfs_attr.c b/fs/xfs/libxfs/xfs_attr.c
index 836ab1b8ed7b0..0847b4e162378 100644
--- a/fs/xfs/libxfs/xfs_attr.c
+++ b/fs/xfs/libxfs/xfs_attr.c
@@ -997,9 +997,11 @@ xfs_attr_set(
 	/*
 	 * We have no control over the attribute names that userspace passes us
 	 * to remove, so we have to allow the name lookup prior to attribute
-	 * removal to fail as well.
+	 * removal to fail as well.  Preserve the logged flag, since we need
+	 * to pass that through to the logging code.
 	 */
-	args->op_flags = XFS_DA_OP_OKNOENT;
+	args->op_flags = XFS_DA_OP_OKNOENT |
+					(args->op_flags & XFS_DA_OP_LOGGED);
 
 	if (args->value) {
 		XFS_STATS_INC(mp, xs_attr_set);
diff --git a/fs/xfs/libxfs/xfs_attr.h b/fs/xfs/libxfs/xfs_attr.h
index e329da3e7afa9..b4a2fc77017e0 100644
--- a/fs/xfs/libxfs/xfs_attr.h
+++ b/fs/xfs/libxfs/xfs_attr.h
@@ -28,16 +28,6 @@ struct xfs_attr_list_context;
  */
 #define	ATTR_MAX_VALUELEN	(64*1024)	/* max length of a value */
 
-static inline bool xfs_has_larp(struct xfs_mount *mp)
-{
-#ifdef DEBUG
-	/* Logged xattrs require a V5 super for log_incompat */
-	return xfs_has_crc(mp) && xfs_globals.larp;
-#else
-	return false;
-#endif
-}
-
 /*
  * Kernel-internal version of the attrlist cursor.
  */
@@ -624,7 +614,7 @@ static inline enum xfs_delattr_state
 xfs_attr_init_replace_state(struct xfs_da_args *args)
 {
 	args->op_flags |= XFS_DA_OP_ADDNAME | XFS_DA_OP_REPLACE;
-	if (xfs_has_larp(args->dp->i_mount))
+	if (args->op_flags & XFS_DA_OP_LOGGED)
 		return xfs_attr_init_remove_state(args);
 	return xfs_attr_init_add_state(args);
 }
diff --git a/fs/xfs/libxfs/xfs_attr_leaf.c b/fs/xfs/libxfs/xfs_attr_leaf.c
index 15a9904094634..37e7c33f62839 100644
--- a/fs/xfs/libxfs/xfs_attr_leaf.c
+++ b/fs/xfs/libxfs/xfs_attr_leaf.c
@@ -1530,7 +1530,7 @@ xfs_attr3_leaf_add_work(
 	if (tmp)
 		entry->flags |= XFS_ATTR_LOCAL;
 	if (args->op_flags & XFS_DA_OP_REPLACE) {
-		if (!xfs_has_larp(mp))
+		if (!(args->op_flags & XFS_DA_OP_LOGGED))
 			entry->flags |= XFS_ATTR_INCOMPLETE;
 		if ((args->blkno2 == args->blkno) &&
 		    (args->index2 <= args->index)) {
diff --git a/fs/xfs/libxfs/xfs_da_btree.h b/fs/xfs/libxfs/xfs_da_btree.h
index d33b7686a0b3a..ffa3df5b2893f 100644
--- a/fs/xfs/libxfs/xfs_da_btree.h
+++ b/fs/xfs/libxfs/xfs_da_btree.h
@@ -92,6 +92,7 @@ typedef struct xfs_da_args {
 #define XFS_DA_OP_NOTIME	(1u << 5) /* don't update inode timestamps */
 #define XFS_DA_OP_REMOVE	(1u << 6) /* this is a remove operation */
 #define XFS_DA_OP_RECOVERY	(1u << 7) /* Log recovery operation */
+#define XFS_DA_OP_LOGGED	(1u << 8) /* Use intent items to track op */
 
 #define XFS_DA_OP_FLAGS \
 	{ XFS_DA_OP_JUSTCHECK,	"JUSTCHECK" }, \
@@ -101,7 +102,8 @@ typedef struct xfs_da_args {
 	{ XFS_DA_OP_CILOOKUP,	"CILOOKUP" }, \
 	{ XFS_DA_OP_NOTIME,	"NOTIME" }, \
 	{ XFS_DA_OP_REMOVE,	"REMOVE" }, \
-	{ XFS_DA_OP_RECOVERY,	"RECOVERY" }
+	{ XFS_DA_OP_RECOVERY,	"RECOVERY" }, \
+	{ XFS_DA_OP_LOGGED,	"LOGGED" }
 
 /*
  * Storage for holding state during Btree searches and split/join ops.
diff --git a/fs/xfs/xfs_attr_item.c b/fs/xfs/xfs_attr_item.c
index 4a28c2d770700..135d441334773 100644
--- a/fs/xfs/xfs_attr_item.c
+++ b/fs/xfs/xfs_attr_item.c
@@ -413,18 +413,20 @@ xfs_attr_create_intent(
 	struct xfs_mount		*mp = tp->t_mountp;
 	struct xfs_attri_log_item	*attrip;
 	struct xfs_attr_intent		*attr;
+	struct xfs_da_args		*args;
 
 	ASSERT(count == 1);
 
-	if (!xfs_sb_version_haslogxattrs(&mp->m_sb))
-		return NULL;
-
 	/*
 	 * Each attr item only performs one attribute operation at a time, so
 	 * this is a list of one
 	 */
 	attr = list_first_entry_or_null(items, struct xfs_attr_intent,
 			xattri_list);
+	args = attr->xattri_da_args;
+
+	if (!(args->op_flags & XFS_DA_OP_LOGGED))
+		return NULL;
 
 	/*
 	 * Create a buffer to store the attribute name and value.  This buffer
@@ -432,8 +434,6 @@ xfs_attr_create_intent(
 	 * and the lower level xattr log items.
 	 */
 	if (!attr->xattri_nameval) {
-		struct xfs_da_args	*args = attr->xattri_da_args;
-
 		/*
 		 * Transfer our reference to the name/value buffer to the
 		 * deferred work state structure.
@@ -617,7 +617,10 @@ xfs_attri_item_recover(
 	args->namelen = nv->name.i_len;
 	args->hashval = xfs_da_hashname(args->name, args->namelen);
 	args->attr_filter = attrp->alfi_attr_filter & XFS_ATTRI_FILTER_MASK;
-	args->op_flags = XFS_DA_OP_RECOVERY | XFS_DA_OP_OKNOENT;
+	args->op_flags = XFS_DA_OP_RECOVERY | XFS_DA_OP_OKNOENT |
+			 XFS_DA_OP_LOGGED;
+
+	ASSERT(xfs_sb_version_haslogxattrs(&mp->m_sb));
 
 	switch (attr->xattri_op_flags) {
 	case XFS_ATTRI_OP_FLAGS_SET:
diff --git a/fs/xfs/xfs_xattr.c b/fs/xfs/xfs_xattr.c
index 35e13e125ec6a..c325a28b89a8d 100644
--- a/fs/xfs/xfs_xattr.c
+++ b/fs/xfs/xfs_xattr.c
@@ -68,6 +68,18 @@ xfs_attr_rele_log_assist(
 	xlog_drop_incompat_feat(mp->m_log);
 }
 
+static inline bool
+xfs_attr_want_log_assist(
+	struct xfs_mount	*mp)
+{
+#ifdef DEBUG
+	/* Logged xattrs require a V5 super for log_incompat */
+	return xfs_has_crc(mp) && xfs_globals.larp;
+#else
+	return false;
+#endif
+}
+
 /*
  * Set or remove an xattr, having grabbed the appropriate logging resources
  * prior to calling libxfs.
@@ -80,11 +92,14 @@ xfs_attr_change(
 	bool			use_logging = false;
 	int			error;
 
-	if (xfs_has_larp(mp)) {
+	ASSERT(!(args->op_flags & XFS_DA_OP_LOGGED));
+
+	if (xfs_attr_want_log_assist(mp)) {
 		error = xfs_attr_grab_log_assist(mp);
 		if (error)
 			return error;
 
+		args->op_flags |= XFS_DA_OP_LOGGED;
 		use_logging = true;
 	}
 
-- 
GitLab


From 10930b254d5be1cb4350fb7a456ccd5ea7e3cbd9 Mon Sep 17 00:00:00 2001
From: "Darrick J. Wong" <djwong@kernel.org>
Date: Sun, 5 Jun 2022 18:51:22 -0700
Subject: [PATCH 0643/1731] xfs: fix variable state usage
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The variable @args is fed to a tracepoint, and that's the only place
it's used.  This is fine for the kernel, but for userspace, tracepoints
are #define'd out of existence, which results in this warning on gcc
11.2:

xfs_attr.c: In function ‘xfs_attr_node_try_addname’:
xfs_attr.c:1440:42: warning: unused variable ‘args’ [-Wunused-variable]
 1440 |         struct xfs_da_args              *args = attr->xattri_da_args;
      |                                          ^~~~

Clean this up.

Signed-off-by: Darrick J. Wong <djwong@kernel.org>
Reviewed-by: Dave Chinner <dchinner@redhat.com>
Reviewed-by: Allison Henderson <allison.henderson@oracle.com>
---
 fs/xfs/libxfs/xfs_attr.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/fs/xfs/libxfs/xfs_attr.c b/fs/xfs/libxfs/xfs_attr.c
index 0847b4e162378..1824f61621a24 100644
--- a/fs/xfs/libxfs/xfs_attr.c
+++ b/fs/xfs/libxfs/xfs_attr.c
@@ -1441,12 +1441,11 @@ static int
 xfs_attr_node_try_addname(
 	struct xfs_attr_intent		*attr)
 {
-	struct xfs_da_args		*args = attr->xattri_da_args;
 	struct xfs_da_state		*state = attr->xattri_da_state;
 	struct xfs_da_state_blk		*blk;
 	int				error;
 
-	trace_xfs_attr_node_addname(args);
+	trace_xfs_attr_node_addname(state->args);
 
 	blk = &state->path.blk[state->path.active-1];
 	ASSERT(blk->magic == XFS_ATTR_LEAF_MAGIC);
-- 
GitLab


From e89ab76d7e2564c65986add3d634cc5cf5bacf14 Mon Sep 17 00:00:00 2001
From: "Darrick J. Wong" <djwong@kernel.org>
Date: Sun, 5 Jun 2022 18:51:23 -0700
Subject: [PATCH 0644/1731] xfs: preserve DIFLAG2_NREXT64 when setting other
 inode attributes

It is vitally important that we preserve the state of the NREXT64 inode
flag when we're changing the other flags2 fields.

Fixes: 9b7d16e34bbe ("xfs: Introduce XFS_DIFLAG2_NREXT64 and associated helpers")
Signed-off-by: Darrick J. Wong <djwong@kernel.org>
Reviewed-by: Dave Chinner <dchinner@redhat.com>
Reviewed-by: Chandan Babu R <chandan.babu@oracle.com>
Reviewed-by: Allison Henderson <allison.henderson@oracle.com>
---
 fs/xfs/xfs_ioctl.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/fs/xfs/xfs_ioctl.c b/fs/xfs/xfs_ioctl.c
index 5a364a7d58fdd..0d67ff8a8961d 100644
--- a/fs/xfs/xfs_ioctl.c
+++ b/fs/xfs/xfs_ioctl.c
@@ -1096,7 +1096,8 @@ xfs_flags2diflags2(
 {
 	uint64_t		di_flags2 =
 		(ip->i_diflags2 & (XFS_DIFLAG2_REFLINK |
-				   XFS_DIFLAG2_BIGTIME));
+				   XFS_DIFLAG2_BIGTIME |
+				   XFS_DIFLAG2_NREXT64));
 
 	if (xflags & FS_XFLAG_DAX)
 		di_flags2 |= XFS_DIFLAG2_DAX;
-- 
GitLab


From 920169041baa0a7497ed702aa97d6a2d6285efd3 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Tue, 14 Jun 2022 02:31:00 -0500
Subject: [PATCH 0645/1731] drm/sun4i: dw-hdmi: Fix ddc-en GPIO consumer
 conflict

commit 6de79dd3a920 ("drm/bridge: display-connector: add ddc-en gpio
support") added a consumer for this GPIO in the HDMI connector device.
This new consumer conflicts with the pre-existing GPIO consumer in the
sun8i HDMI controller driver, which prevents the driver from probing:

  [    4.983358] display-connector connector: GPIO lookup for consumer ddc-en
  [    4.983364] display-connector connector: using device tree for GPIO lookup
  [    4.983392] gpio-226 (ddc-en): gpiod_request: status -16
  [    4.983399] sun8i-dw-hdmi 6000000.hdmi: Couldn't get ddc-en gpio
  [    4.983618] sun4i-drm display-engine: failed to bind 6000000.hdmi (ops sun8i_dw_hdmi_ops [sun8i_drm_hdmi]): -16
  [    4.984082] sun4i-drm display-engine: Couldn't bind all pipelines components
  [    4.984171] sun4i-drm display-engine: adev bind failed: -16
  [    4.984179] sun8i-dw-hdmi: probe of 6000000.hdmi failed with error -16

Both drivers have the same behavior: they leave the GPIO active for the
life of the device. Let's take advantage of the new implementation, and
drop the now-obsolete code from the HDMI controller driver.

Fixes: 6de79dd3a920 ("drm/bridge: display-connector: add ddc-en gpio support")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220614073100.11550-1-samuel@sholland.org
---
 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 54 ++-------------------------
 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h |  2 -
 2 files changed, 4 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
index a8d75fd7e9f42..477cb6985b4d2 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
@@ -93,34 +93,10 @@ crtcs_exit:
 	return crtcs;
 }
 
-static int sun8i_dw_hdmi_find_connector_pdev(struct device *dev,
-					     struct platform_device **pdev_out)
-{
-	struct platform_device *pdev;
-	struct device_node *remote;
-
-	remote = of_graph_get_remote_node(dev->of_node, 1, -1);
-	if (!remote)
-		return -ENODEV;
-
-	if (!of_device_is_compatible(remote, "hdmi-connector")) {
-		of_node_put(remote);
-		return -ENODEV;
-	}
-
-	pdev = of_find_device_by_node(remote);
-	of_node_put(remote);
-	if (!pdev)
-		return -ENODEV;
-
-	*pdev_out = pdev;
-	return 0;
-}
-
 static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
 			      void *data)
 {
-	struct platform_device *pdev = to_platform_device(dev), *connector_pdev;
+	struct platform_device *pdev = to_platform_device(dev);
 	struct dw_hdmi_plat_data *plat_data;
 	struct drm_device *drm = data;
 	struct device_node *phy_node;
@@ -167,30 +143,16 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
 		return dev_err_probe(dev, PTR_ERR(hdmi->regulator),
 				     "Couldn't get regulator\n");
 
-	ret = sun8i_dw_hdmi_find_connector_pdev(dev, &connector_pdev);
-	if (!ret) {
-		hdmi->ddc_en = gpiod_get_optional(&connector_pdev->dev,
-						  "ddc-en", GPIOD_OUT_HIGH);
-		platform_device_put(connector_pdev);
-
-		if (IS_ERR(hdmi->ddc_en)) {
-			dev_err(dev, "Couldn't get ddc-en gpio\n");
-			return PTR_ERR(hdmi->ddc_en);
-		}
-	}
-
 	ret = regulator_enable(hdmi->regulator);
 	if (ret) {
 		dev_err(dev, "Failed to enable regulator\n");
-		goto err_unref_ddc_en;
+		return ret;
 	}
 
-	gpiod_set_value(hdmi->ddc_en, 1);
-
 	ret = reset_control_deassert(hdmi->rst_ctrl);
 	if (ret) {
 		dev_err(dev, "Could not deassert ctrl reset control\n");
-		goto err_disable_ddc_en;
+		goto err_disable_regulator;
 	}
 
 	ret = clk_prepare_enable(hdmi->clk_tmds);
@@ -245,12 +207,8 @@ err_disable_clk_tmds:
 	clk_disable_unprepare(hdmi->clk_tmds);
 err_assert_ctrl_reset:
 	reset_control_assert(hdmi->rst_ctrl);
-err_disable_ddc_en:
-	gpiod_set_value(hdmi->ddc_en, 0);
+err_disable_regulator:
 	regulator_disable(hdmi->regulator);
-err_unref_ddc_en:
-	if (hdmi->ddc_en)
-		gpiod_put(hdmi->ddc_en);
 
 	return ret;
 }
@@ -264,11 +222,7 @@ static void sun8i_dw_hdmi_unbind(struct device *dev, struct device *master,
 	sun8i_hdmi_phy_deinit(hdmi->phy);
 	clk_disable_unprepare(hdmi->clk_tmds);
 	reset_control_assert(hdmi->rst_ctrl);
-	gpiod_set_value(hdmi->ddc_en, 0);
 	regulator_disable(hdmi->regulator);
-
-	if (hdmi->ddc_en)
-		gpiod_put(hdmi->ddc_en);
 }
 
 static const struct component_ops sun8i_dw_hdmi_ops = {
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
index bffe1b9cd3dcb..9ad09522947a5 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
@@ -9,7 +9,6 @@
 #include <drm/bridge/dw_hdmi.h>
 #include <drm/drm_encoder.h>
 #include <linux/clk.h>
-#include <linux/gpio/consumer.h>
 #include <linux/regmap.h>
 #include <linux/regulator/consumer.h>
 #include <linux/reset.h>
@@ -193,7 +192,6 @@ struct sun8i_dw_hdmi {
 	struct regulator		*regulator;
 	const struct sun8i_dw_hdmi_quirks *quirks;
 	struct reset_control		*rst_ctrl;
-	struct gpio_desc		*ddc_en;
 };
 
 extern struct platform_driver sun8i_hdmi_phy_driver;
-- 
GitLab


From 1342b5b23da9559a1578978eaff7f797d8a87d91 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Wed, 15 Jun 2022 00:42:53 -0500
Subject: [PATCH 0646/1731] drm/sun4i: Fix crash during suspend after component
 bind failure

If the component driver fails to bind, or is unbound, the driver data
for the top-level platform device points to a freed drm_device. If the
system is then suspended, the driver passes this dangling pointer to
drm_mode_config_helper_suspend(), which crashes.

Fix this by only setting the driver data while the platform driver holds
a reference to the drm_device.

Fixes: 624b4b48d9d8 ("drm: sun4i: Add support for suspending the display driver")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220615054254.16352-1-samuel@sholland.org
---
 drivers/gpu/drm/sun4i/sun4i_drv.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 275f7e4a03ae8..8841dba989ee4 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -73,7 +73,6 @@ static int sun4i_drv_bind(struct device *dev)
 		goto free_drm;
 	}
 
-	dev_set_drvdata(dev, drm);
 	drm->dev_private = drv;
 	INIT_LIST_HEAD(&drv->frontend_list);
 	INIT_LIST_HEAD(&drv->engine_list);
@@ -114,6 +113,8 @@ static int sun4i_drv_bind(struct device *dev)
 
 	drm_fbdev_generic_setup(drm, 32);
 
+	dev_set_drvdata(dev, drm);
+
 	return 0;
 
 finish_poll:
@@ -130,6 +131,7 @@ static void sun4i_drv_unbind(struct device *dev)
 {
 	struct drm_device *drm = dev_get_drvdata(dev);
 
+	dev_set_drvdata(dev, NULL);
 	drm_dev_unregister(drm);
 	drm_kms_helper_poll_fini(drm);
 	drm_atomic_helper_shutdown(drm);
-- 
GitLab


From 27cfa258951a465e3eae63ee1e715e902cd45578 Mon Sep 17 00:00:00 2001
From: Ye Bin <yebin10@huawei.com>
Date: Wed, 15 Jun 2022 17:00:10 +0800
Subject: [PATCH 0647/1731] ext2: fix fs corruption when trying to remove a
 non-empty directory with IO error

We got issue as follows:
[home]# mount  /dev/sdd  test
[home]# cd test
[test]# ls
dir1  lost+found
[test]# rmdir  dir1
ext2_empty_dir: inject fault
[test]# ls
lost+found
[test]# cd ..
[home]# umount test
[home]# fsck.ext2 -fn  /dev/sdd
e2fsck 1.42.9 (28-Dec-2013)
Pass 1: Checking inodes, blocks, and sizes
Inode 4065, i_size is 0, should be 1024.  Fix? no

Pass 2: Checking directory structure
Pass 3: Checking directory connectivity
Unconnected directory inode 4065 (/???)
Connect to /lost+found? no

'..' in ... (4065) is / (2), should be <The NULL inode> (0).
Fix? no

Pass 4: Checking reference counts
Inode 2 ref count is 3, should be 4.  Fix? no

Inode 4065 ref count is 2, should be 3.  Fix? no

Pass 5: Checking group summary information

/dev/sdd: ********** WARNING: Filesystem still has errors **********

/dev/sdd: 14/128016 files (0.0% non-contiguous), 18477/512000 blocks

Reason is same with commit 7aab5c84a0f6. We can't assume directory
is empty when read directory entry failed.

Link: https://lore.kernel.org/r/20220615090010.1544152-1-yebin10@huawei.com
Signed-off-by: Ye Bin <yebin10@huawei.com>
Signed-off-by: Jan Kara <jack@suse.cz>
---
 fs/ext2/dir.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/fs/ext2/dir.c b/fs/ext2/dir.c
index 2c2f179b69779..43de293cef56b 100644
--- a/fs/ext2/dir.c
+++ b/fs/ext2/dir.c
@@ -672,17 +672,14 @@ int ext2_empty_dir (struct inode * inode)
 	void *page_addr = NULL;
 	struct page *page = NULL;
 	unsigned long i, npages = dir_pages(inode);
-	int dir_has_error = 0;
 
 	for (i = 0; i < npages; i++) {
 		char *kaddr;
 		ext2_dirent * de;
-		page = ext2_get_page(inode, i, dir_has_error, &page_addr);
+		page = ext2_get_page(inode, i, 0, &page_addr);
 
-		if (IS_ERR(page)) {
-			dir_has_error = 1;
-			continue;
-		}
+		if (IS_ERR(page))
+			goto not_empty;
 
 		kaddr = page_addr;
 		de = (ext2_dirent *)kaddr;
-- 
GitLab


From 4bca7e80b6455772b4bf3f536dcbc19aac424d6a Mon Sep 17 00:00:00 2001
From: Jan Kara <jack@suse.cz>
Date: Wed, 15 Jun 2022 15:22:29 +0200
Subject: [PATCH 0648/1731] init: Initialize noop_backing_dev_info early

noop_backing_dev_info is used by superblocks of various
pseudofilesystems such as kdevtmpfs. After commit 10e14073107d
("writeback: Fix inode->i_io_list not be protected by inode->i_lock
error") this broke because __mark_inode_dirty() started to access more
fields from noop_backing_dev_info and this led to crashes inside
locked_inode_to_wb_and_lock_list() called from __mark_inode_dirty().
Fix the problem by initializing noop_backing_dev_info before the
filesystems get mounted.

Fixes: 10e14073107d ("writeback: Fix inode->i_io_list not be protected by inode->i_lock error")
Reported-and-tested-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reported-and-tested-by: Alexandru Elisei <alexandru.elisei@arm.com>
Reported-and-tested-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Jan Kara <jack@suse.cz>
---
 drivers/base/init.c         |  2 ++
 include/linux/backing-dev.h |  2 ++
 mm/backing-dev.c            | 11 ++---------
 3 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/base/init.c b/drivers/base/init.c
index d8d0fe687111a..397eb9880cecb 100644
--- a/drivers/base/init.c
+++ b/drivers/base/init.c
@@ -8,6 +8,7 @@
 #include <linux/init.h>
 #include <linux/memory.h>
 #include <linux/of.h>
+#include <linux/backing-dev.h>
 
 #include "base.h"
 
@@ -20,6 +21,7 @@
 void __init driver_init(void)
 {
 	/* These are the core pieces */
+	bdi_init(&noop_backing_dev_info);
 	devtmpfs_init();
 	devices_init();
 	buses_init();
diff --git a/include/linux/backing-dev.h b/include/linux/backing-dev.h
index 2bd073fa6bb53..d452071db572e 100644
--- a/include/linux/backing-dev.h
+++ b/include/linux/backing-dev.h
@@ -119,6 +119,8 @@ int bdi_set_max_ratio(struct backing_dev_info *bdi, unsigned int max_ratio);
 
 extern struct backing_dev_info noop_backing_dev_info;
 
+int bdi_init(struct backing_dev_info *bdi);
+
 /**
  * writeback_in_progress - determine whether there is writeback in progress
  * @wb: bdi_writeback of interest
diff --git a/mm/backing-dev.c b/mm/backing-dev.c
index ff60bd7d74e07..95550b8fa7fe2 100644
--- a/mm/backing-dev.c
+++ b/mm/backing-dev.c
@@ -231,20 +231,13 @@ static __init int bdi_class_init(void)
 }
 postcore_initcall(bdi_class_init);
 
-static int bdi_init(struct backing_dev_info *bdi);
-
 static int __init default_bdi_init(void)
 {
-	int err;
-
 	bdi_wq = alloc_workqueue("writeback", WQ_MEM_RECLAIM | WQ_UNBOUND |
 				 WQ_SYSFS, 0);
 	if (!bdi_wq)
 		return -ENOMEM;
-
-	err = bdi_init(&noop_backing_dev_info);
-
-	return err;
+	return 0;
 }
 subsys_initcall(default_bdi_init);
 
@@ -781,7 +774,7 @@ static void cgwb_remove_from_bdi_list(struct bdi_writeback *wb)
 
 #endif	/* CONFIG_CGROUP_WRITEBACK */
 
-static int bdi_init(struct backing_dev_info *bdi)
+int bdi_init(struct backing_dev_info *bdi)
 {
 	int ret;
 
-- 
GitLab


From cb468c7d84d174ab9cd638be9f5b3f1ba2b311a0 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime@cerno.tech>
Date: Fri, 10 Jun 2022 13:51:36 +0200
Subject: [PATCH 0649/1731] drm/vc4: plane: Prevent async update if we don't
 have a dlist

The vc4 planes are setup in hardware by creating a hardware descriptor
in a dedicated RAM. As part of the process to setup a plane in KMS, we
thus need to allocate some part of that dedicated RAM to store our
descriptor there.

The async update path will just reuse the descriptor already allocated
for that plane and will modify it directly in RAM to match whatever has
been asked for.

In order to do that, it will compare the descriptor for the old plane
state and the new plane state, will make sure they fit in the same size,
and check that only the position or buffer address have changed.

Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220610115149.964394-2-maxime@cerno.tech
---
 drivers/gpu/drm/vc4/vc4_plane.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index b3438f4a81ced..811a2d004cc47 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -1321,6 +1321,10 @@ static int vc4_plane_atomic_async_check(struct drm_plane *plane,
 
 	old_vc4_state = to_vc4_plane_state(plane->state);
 	new_vc4_state = to_vc4_plane_state(new_plane_state);
+
+	if (!new_vc4_state->hw_dlist)
+		return -EINVAL;
+
 	if (old_vc4_state->dlist_count != new_vc4_state->dlist_count ||
 	    old_vc4_state->pos0_offset != new_vc4_state->pos0_offset ||
 	    old_vc4_state->pos2_offset != new_vc4_state->pos2_offset ||
-- 
GitLab


From 1cbc91eb7b518cc5f80442ff9b517dc5b9d3b849 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime@cerno.tech>
Date: Fri, 10 Jun 2022 13:51:37 +0200
Subject: [PATCH 0650/1731] drm/vc4: Consolidate Hardware Revision Check

A new generation of controller has been introduced with the
BCM2711/RaspberryPi4. This generation needs a bunch of quirks, and over
time we've piled on a number of checks in most parts of the drivers.

All these checks are performed several times, and are not always
consistent. Let's create a single, global, variable to hold it and use
it everywhere.

Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220610115149.964394-3-maxime@cerno.tech
---
 drivers/gpu/drm/vc4/vc4_crtc.c  |  6 +++---
 drivers/gpu/drm/vc4/vc4_drv.c   |  4 ++++
 drivers/gpu/drm/vc4/vc4_drv.h   |  6 +++---
 drivers/gpu/drm/vc4/vc4_hvs.c   | 18 +++++++++---------
 drivers/gpu/drm/vc4/vc4_kms.c   | 12 +++++-------
 drivers/gpu/drm/vc4/vc4_plane.c | 13 ++++++-------
 6 files changed, 30 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 59b20c8f132b7..dd5fb25d0f431 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -256,7 +256,7 @@ static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
 		 * Removing 1 from the FIFO full level however
 		 * seems to completely remove that issue.
 		 */
-		if (!vc4->hvs->hvs5)
+		if (!vc4->is_vc5)
 			return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1;
 
 		return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
@@ -389,7 +389,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
 	if (is_dsi)
 		CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
 
-	if (vc4->hvs->hvs5)
+	if (vc4->is_vc5)
 		CRTC_WRITE(PV_MUX_CFG,
 			   VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP,
 					 PV_MUX_CFG_RGB_PIXEL_MUX_MODE));
@@ -1149,7 +1149,7 @@ int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
 				  crtc_funcs, NULL);
 	drm_crtc_helper_add(crtc, crtc_helper_funcs);
 
-	if (!vc4->hvs->hvs5) {
+	if (!vc4->is_vc5) {
 		drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
 
 		drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c
index 162bc18e7497f..53067525b5861 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.c
+++ b/drivers/gpu/drm/vc4/vc4_drv.c
@@ -217,10 +217,13 @@ static int vc4_drm_bind(struct device *dev)
 	struct vc4_dev *vc4;
 	struct device_node *node;
 	struct drm_crtc *crtc;
+	bool is_vc5;
 	int ret = 0;
 
 	dev->coherent_dma_mask = DMA_BIT_MASK(32);
 
+	is_vc5 = of_device_is_compatible(dev->of_node, "brcm,bcm2711-vc5");
+
 	/* If VC4 V3D is missing, don't advertise render nodes. */
 	node = of_find_matching_node_and_match(NULL, vc4_v3d_dt_match, NULL);
 	if (!node || !of_device_is_available(node))
@@ -230,6 +233,7 @@ static int vc4_drm_bind(struct device *dev)
 	vc4 = devm_drm_dev_alloc(dev, &vc4_drm_driver, struct vc4_dev, base);
 	if (IS_ERR(vc4))
 		return PTR_ERR(vc4);
+	vc4->is_vc5 = is_vc5;
 
 	drm = &vc4->base;
 	platform_set_drvdata(pdev, drm);
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 15e0c2ac3940e..82453a3bcffea 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -74,6 +74,8 @@ struct vc4_perfmon {
 struct vc4_dev {
 	struct drm_device base;
 
+	bool is_vc5;
+
 	unsigned int irq;
 
 	struct vc4_hvs *hvs;
@@ -316,6 +318,7 @@ struct vc4_v3d {
 };
 
 struct vc4_hvs {
+	struct vc4_dev *vc4;
 	struct platform_device *pdev;
 	void __iomem *regs;
 	u32 __iomem *dlist;
@@ -333,9 +336,6 @@ struct vc4_hvs {
 	struct drm_mm_node mitchell_netravali_filter;
 
 	struct debugfs_regset32 regset;
-
-	/* HVS version 5 flag, therefore requires updated dlist structures */
-	bool hvs5;
 };
 
 struct vc4_plane {
diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index 2a58fc421cf60..ba2c8e5a9b645 100644
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -220,10 +220,11 @@ u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo)
 
 int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output)
 {
+	struct vc4_dev *vc4 = hvs->vc4;
 	u32 reg;
 	int ret;
 
-	if (!hvs->hvs5)
+	if (!vc4->is_vc5)
 		return output;
 
 	switch (output) {
@@ -273,6 +274,7 @@ int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output)
 static int vc4_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc,
 				struct drm_display_mode *mode, bool oneshot)
 {
+	struct vc4_dev *vc4 = hvs->vc4;
 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 	struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
 	unsigned int chan = vc4_crtc_state->assigned_channel;
@@ -291,7 +293,7 @@ static int vc4_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc,
 	 */
 	dispctrl = SCALER_DISPCTRLX_ENABLE;
 
-	if (!hvs->hvs5)
+	if (!vc4->is_vc5)
 		dispctrl |= VC4_SET_FIELD(mode->hdisplay,
 					  SCALER_DISPCTRLX_WIDTH) |
 			    VC4_SET_FIELD(mode->vdisplay,
@@ -312,7 +314,7 @@ static int vc4_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc,
 
 	HVS_WRITE(SCALER_DISPBKGNDX(chan), dispbkgndx |
 		  SCALER_DISPBKGND_AUTOHS |
-		  ((!hvs->hvs5) ? SCALER_DISPBKGND_GAMMA : 0) |
+		  ((!vc4->is_vc5) ? SCALER_DISPBKGND_GAMMA : 0) |
 		  (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
 
 	/* Reload the LUT, since the SRAMs would have been disabled if
@@ -617,11 +619,9 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
 	if (!hvs)
 		return -ENOMEM;
 
+	hvs->vc4 = vc4;
 	hvs->pdev = pdev;
 
-	if (of_device_is_compatible(pdev->dev.of_node, "brcm,bcm2711-hvs"))
-		hvs->hvs5 = true;
-
 	hvs->regs = vc4_ioremap_regs(pdev, 0);
 	if (IS_ERR(hvs->regs))
 		return PTR_ERR(hvs->regs);
@@ -630,7 +630,7 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
 	hvs->regset.regs = hvs_regs;
 	hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
 
-	if (hvs->hvs5) {
+	if (vc4->is_vc5) {
 		hvs->core_clk = devm_clk_get(&pdev->dev, NULL);
 		if (IS_ERR(hvs->core_clk)) {
 			dev_err(&pdev->dev, "Couldn't get core clock\n");
@@ -644,7 +644,7 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
 		}
 	}
 
-	if (!hvs->hvs5)
+	if (!vc4->is_vc5)
 		hvs->dlist = hvs->regs + SCALER_DLIST_START;
 	else
 		hvs->dlist = hvs->regs + SCALER5_DLIST_START;
@@ -665,7 +665,7 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
 	 * between planes when they don't overlap on the screen, but
 	 * for now we just allocate globally.
 	 */
-	if (!hvs->hvs5)
+	if (!vc4->is_vc5)
 		/* 48k words of 2x12-bit pixels */
 		drm_mm_init(&hvs->lbm_mm, 0, 48 * 1024);
 	else
diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index c169bd72e53b1..3c232d85ab856 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -393,7 +393,7 @@ static void vc4_atomic_commit_tail(struct drm_atomic_state *state)
 		old_hvs_state->fifo_state[channel].pending_commit = NULL;
 	}
 
-	if (vc4->hvs->hvs5) {
+	if (vc4->is_vc5) {
 		unsigned long state_rate = max(old_hvs_state->core_clock_rate,
 					       new_hvs_state->core_clock_rate);
 		unsigned long core_rate = max_t(unsigned long,
@@ -412,7 +412,7 @@ static void vc4_atomic_commit_tail(struct drm_atomic_state *state)
 
 	vc4_ctm_commit(vc4, state);
 
-	if (vc4->hvs->hvs5)
+	if (vc4->is_vc5)
 		vc5_hvs_pv_muxing_commit(vc4, state);
 	else
 		vc4_hvs_pv_muxing_commit(vc4, state);
@@ -430,7 +430,7 @@ static void vc4_atomic_commit_tail(struct drm_atomic_state *state)
 
 	drm_atomic_helper_cleanup_planes(dev, state);
 
-	if (vc4->hvs->hvs5) {
+	if (vc4->is_vc5) {
 		drm_dbg(dev, "Running the core clock at %lu Hz\n",
 			new_hvs_state->core_clock_rate);
 
@@ -1000,8 +1000,6 @@ static const struct drm_mode_config_funcs vc4_mode_funcs = {
 int vc4_kms_load(struct drm_device *dev)
 {
 	struct vc4_dev *vc4 = to_vc4_dev(dev);
-	bool is_vc5 = of_device_is_compatible(dev->dev->of_node,
-					      "brcm,bcm2711-vc5");
 	int ret;
 
 	/*
@@ -1009,7 +1007,7 @@ int vc4_kms_load(struct drm_device *dev)
 	 * the BCM2711, but the load tracker computations are used for
 	 * the core clock rate calculation.
 	 */
-	if (!is_vc5) {
+	if (!vc4->is_vc5) {
 		/* Start with the load tracker enabled. Can be
 		 * disabled through the debugfs load_tracker file.
 		 */
@@ -1025,7 +1023,7 @@ int vc4_kms_load(struct drm_device *dev)
 		return ret;
 	}
 
-	if (is_vc5) {
+	if (vc4->is_vc5) {
 		dev->mode_config.max_width = 7680;
 		dev->mode_config.max_height = 7680;
 	} else {
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index 811a2d004cc47..ba7359516d75d 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -489,10 +489,10 @@ static u32 vc4_lbm_size(struct drm_plane_state *state)
 	}
 
 	/* Align it to 64 or 128 (hvs5) bytes */
-	lbm = roundup(lbm, vc4->hvs->hvs5 ? 128 : 64);
+	lbm = roundup(lbm, vc4->is_vc5 ? 128 : 64);
 
 	/* Each "word" of the LBM memory contains 2 or 4 (hvs5) pixels */
-	lbm /= vc4->hvs->hvs5 ? 4 : 2;
+	lbm /= vc4->is_vc5 ? 4 : 2;
 
 	return lbm;
 }
@@ -608,7 +608,7 @@ static int vc4_plane_allocate_lbm(struct drm_plane_state *state)
 		ret = drm_mm_insert_node_generic(&vc4->hvs->lbm_mm,
 						 &vc4_state->lbm,
 						 lbm_size,
-						 vc4->hvs->hvs5 ? 64 : 32,
+						 vc4->is_vc5 ? 64 : 32,
 						 0, 0);
 		spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
 
@@ -917,7 +917,7 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
 	mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
 			  fb->format->has_alpha;
 
-	if (!vc4->hvs->hvs5) {
+	if (!vc4->is_vc5) {
 	/* Control word */
 		vc4_dlist_write(vc4_state,
 				SCALER_CTL0_VALID |
@@ -1457,14 +1457,13 @@ static const struct drm_plane_funcs vc4_plane_funcs = {
 struct drm_plane *vc4_plane_init(struct drm_device *dev,
 				 enum drm_plane_type type)
 {
+	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	struct drm_plane *plane = NULL;
 	struct vc4_plane *vc4_plane;
 	u32 formats[ARRAY_SIZE(hvs_formats)];
 	int num_formats = 0;
 	int ret = 0;
 	unsigned i;
-	bool hvs5 = of_device_is_compatible(dev->dev->of_node,
-					    "brcm,bcm2711-vc5");
 	static const uint64_t modifiers[] = {
 		DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
 		DRM_FORMAT_MOD_BROADCOM_SAND128,
@@ -1480,7 +1479,7 @@ struct drm_plane *vc4_plane_init(struct drm_device *dev,
 		return ERR_PTR(-ENOMEM);
 
 	for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
-		if (!hvs_formats[i].hvs5_only || hvs5) {
+		if (!hvs_formats[i].hvs5_only || vc4->is_vc5) {
 			formats[num_formats] = hvs_formats[i].drm;
 			num_formats++;
 		}
-- 
GitLab


From dd2dfd44edc5ba5b2de3c2e6c1c823a62e8f1e92 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime@cerno.tech>
Date: Fri, 10 Jun 2022 13:51:38 +0200
Subject: [PATCH 0651/1731] drm/vc4: bo: Rename vc4_dumb_create

We're going to add a new variant of the dumb BO allocation function, so
let's rename vc4_dumb_create() to something a bit more specific.

Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220610115149.964394-4-maxime@cerno.tech
---
 drivers/gpu/drm/vc4/vc4_bo.c  | 6 +++---
 drivers/gpu/drm/vc4/vc4_drv.c | 2 +-
 drivers/gpu/drm/vc4/vc4_drv.h | 6 +++---
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_bo.c b/drivers/gpu/drm/vc4/vc4_bo.c
index 49c0f2ac868b7..6d505da6b6cfa 100644
--- a/drivers/gpu/drm/vc4/vc4_bo.c
+++ b/drivers/gpu/drm/vc4/vc4_bo.c
@@ -471,9 +471,9 @@ struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t unaligned_size,
 	return bo;
 }
 
-int vc4_dumb_create(struct drm_file *file_priv,
-		    struct drm_device *dev,
-		    struct drm_mode_create_dumb *args)
+int vc4_bo_dumb_create(struct drm_file *file_priv,
+		       struct drm_device *dev,
+		       struct drm_mode_create_dumb *args)
 {
 	int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
 	struct vc4_bo *bo = NULL;
diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c
index 53067525b5861..5f39e40ef2385 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.c
+++ b/drivers/gpu/drm/vc4/vc4_drv.c
@@ -175,7 +175,7 @@ static struct drm_driver vc4_drm_driver = {
 
 	.gem_create_object = vc4_create_object,
 
-	DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE(vc4_dumb_create),
+	DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE(vc4_bo_dumb_create),
 
 	.ioctls = vc4_drm_ioctls,
 	.num_ioctls = ARRAY_SIZE(vc4_drm_ioctls),
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 82453a3bcffea..37c93654480fe 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -814,9 +814,9 @@ struct vc4_validated_shader_info {
 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
 			     bool from_cache, enum vc4_kernel_bo_type type);
-int vc4_dumb_create(struct drm_file *file_priv,
-		    struct drm_device *dev,
-		    struct drm_mode_create_dumb *args);
+int vc4_bo_dumb_create(struct drm_file *file_priv,
+		       struct drm_device *dev,
+		       struct drm_mode_create_dumb *args);
 int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
 			struct drm_file *file_priv);
 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
-- 
GitLab


From 3d7637423be8340f40a669beb253aabbf08239ca Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime@cerno.tech>
Date: Fri, 10 Jun 2022 13:51:39 +0200
Subject: [PATCH 0652/1731] drm/vc4: bo: Split out Dumb buffers fixup

The vc4_bo_dumb_create() both fixes up the allocation arguments to match
the hardware constraints and actually performs the allocation.

Since we're going to introduce a new function that uses a different
allocator, let's split the arguments fixup to a separate function we
will be able to reuse.

Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220610115149.964394-5-maxime@cerno.tech
---
 drivers/gpu/drm/vc4/vc4_bo.c  |  9 +++------
 drivers/gpu/drm/vc4/vc4_drv.c | 13 +++++++++++++
 drivers/gpu/drm/vc4/vc4_drv.h |  1 +
 3 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_bo.c b/drivers/gpu/drm/vc4/vc4_bo.c
index 6d505da6b6cfa..3ca16d682fc0f 100644
--- a/drivers/gpu/drm/vc4/vc4_bo.c
+++ b/drivers/gpu/drm/vc4/vc4_bo.c
@@ -475,15 +475,12 @@ int vc4_bo_dumb_create(struct drm_file *file_priv,
 		       struct drm_device *dev,
 		       struct drm_mode_create_dumb *args)
 {
-	int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
 	struct vc4_bo *bo = NULL;
 	int ret;
 
-	if (args->pitch < min_pitch)
-		args->pitch = min_pitch;
-
-	if (args->size < args->pitch * args->height)
-		args->size = args->pitch * args->height;
+	ret = vc4_dumb_fixup_args(args);
+	if (ret)
+		return ret;
 
 	bo = vc4_bo_create(dev, args->size, false, VC4_BO_TYPE_DUMB);
 	if (IS_ERR(bo))
diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c
index 5f39e40ef2385..eb08940028d39 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.c
+++ b/drivers/gpu/drm/vc4/vc4_drv.c
@@ -63,6 +63,19 @@ void __iomem *vc4_ioremap_regs(struct platform_device *pdev, int index)
 	return map;
 }
 
+int vc4_dumb_fixup_args(struct drm_mode_create_dumb *args)
+{
+	int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
+
+	if (args->pitch < min_pitch)
+		args->pitch = min_pitch;
+
+	if (args->size < args->pitch * args->height)
+		args->size = args->pitch * args->height;
+
+	return 0;
+}
+
 static int vc4_get_param_ioctl(struct drm_device *dev, void *data,
 			       struct drm_file *file_priv)
 {
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 37c93654480fe..9c324c12c4106 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -885,6 +885,7 @@ static inline void vc4_debugfs_add_regset32(struct drm_device *drm,
 
 /* vc4_drv.c */
 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
+int vc4_dumb_fixup_args(struct drm_mode_create_dumb *args);
 
 /* vc4_dpi.c */
 extern struct platform_driver vc4_dpi_driver;
-- 
GitLab


From 538f111160618ef56743a5302e114530edb7df77 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime@cerno.tech>
Date: Fri, 10 Jun 2022 13:51:40 +0200
Subject: [PATCH 0653/1731] drm/vc4: drv: Register a different driver on
 BCM2711

Prior to the BCM2711/RaspberryPi4, the GPU was a part of the display
components of the SoC. It was thus a part of the vc4 driver.

However, with the BCM2711, it got split out and thus the v3d driver was
created. The vc4 driver now only handles the display part.

We didn't properly split out the code when doing the BCM2711 support
though, and most of the code around buffer allocations is still
involved, even though it doesn't have the backing hardware anymore.

Let's start the split out by creating a new drm_driver that only reports
and uses what we support on the BCM2711. The ioctl were properly
filtered already, but we were still exposing a .gem_create_object hook,
as well as having an .open and .postclose hooks which are only relevant
on older generations.

Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220610115149.964394-6-maxime@cerno.tech
---
 drivers/gpu/drm/vc4/vc4_drv.c | 51 ++++++++++++++++++++++++++++-------
 1 file changed, 42 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c
index eb08940028d39..528a1e2761f17 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.c
+++ b/drivers/gpu/drm/vc4/vc4_drv.c
@@ -76,6 +76,19 @@ int vc4_dumb_fixup_args(struct drm_mode_create_dumb *args)
 	return 0;
 }
 
+static int vc5_dumb_create(struct drm_file *file_priv,
+			   struct drm_device *dev,
+			   struct drm_mode_create_dumb *args)
+{
+	int ret;
+
+	ret = vc4_dumb_fixup_args(args);
+	if (ret)
+		return ret;
+
+	return drm_gem_cma_dumb_create_internal(file_priv, dev, args);
+}
+
 static int vc4_get_param_ioctl(struct drm_device *dev, void *data,
 			       struct drm_file *file_priv)
 {
@@ -173,7 +186,7 @@ static const struct drm_ioctl_desc vc4_drm_ioctls[] = {
 	DRM_IOCTL_DEF_DRV(VC4_PERFMON_GET_VALUES, vc4_perfmon_get_values_ioctl, DRM_RENDER_ALLOW),
 };
 
-static struct drm_driver vc4_drm_driver = {
+static const struct drm_driver vc4_drm_driver = {
 	.driver_features = (DRIVER_MODESET |
 			    DRIVER_ATOMIC |
 			    DRIVER_GEM |
@@ -202,6 +215,27 @@ static struct drm_driver vc4_drm_driver = {
 	.patchlevel = DRIVER_PATCHLEVEL,
 };
 
+static const struct drm_driver vc5_drm_driver = {
+	.driver_features = (DRIVER_MODESET |
+			    DRIVER_ATOMIC |
+			    DRIVER_GEM),
+
+#if defined(CONFIG_DEBUG_FS)
+	.debugfs_init = vc4_debugfs_init,
+#endif
+
+	DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE(vc5_dumb_create),
+
+	.fops = &vc4_drm_fops,
+
+	.name = DRIVER_NAME,
+	.desc = DRIVER_DESC,
+	.date = DRIVER_DATE,
+	.major = DRIVER_MAJOR,
+	.minor = DRIVER_MINOR,
+	.patchlevel = DRIVER_PATCHLEVEL,
+};
+
 static void vc4_match_add_drivers(struct device *dev,
 				  struct component_match **match,
 				  struct platform_driver *const *drivers,
@@ -225,6 +259,7 @@ static void vc4_match_add_drivers(struct device *dev,
 static int vc4_drm_bind(struct device *dev)
 {
 	struct platform_device *pdev = to_platform_device(dev);
+	const struct drm_driver *driver;
 	struct rpi_firmware *firmware = NULL;
 	struct drm_device *drm;
 	struct vc4_dev *vc4;
@@ -236,14 +271,12 @@ static int vc4_drm_bind(struct device *dev)
 	dev->coherent_dma_mask = DMA_BIT_MASK(32);
 
 	is_vc5 = of_device_is_compatible(dev->of_node, "brcm,bcm2711-vc5");
+	if (is_vc5)
+		driver = &vc5_drm_driver;
+	else
+		driver = &vc4_drm_driver;
 
-	/* If VC4 V3D is missing, don't advertise render nodes. */
-	node = of_find_matching_node_and_match(NULL, vc4_v3d_dt_match, NULL);
-	if (!node || !of_device_is_available(node))
-		vc4_drm_driver.driver_features &= ~DRIVER_RENDER;
-	of_node_put(node);
-
-	vc4 = devm_drm_dev_alloc(dev, &vc4_drm_driver, struct vc4_dev, base);
+	vc4 = devm_drm_dev_alloc(dev, driver, struct vc4_dev, base);
 	if (IS_ERR(vc4))
 		return PTR_ERR(vc4);
 	vc4->is_vc5 = is_vc5;
@@ -275,7 +308,7 @@ static int vc4_drm_bind(struct device *dev)
 			return -EPROBE_DEFER;
 	}
 
-	ret = drm_aperture_remove_framebuffers(false, &vc4_drm_driver);
+	ret = drm_aperture_remove_framebuffers(false, driver);
 	if (ret)
 		return ret;
 
-- 
GitLab


From 39a30ec64510f71d2a9f5059a7fc1283c4108a35 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime@cerno.tech>
Date: Fri, 10 Jun 2022 13:51:41 +0200
Subject: [PATCH 0654/1731] drm/vc4: kms: Register a different
 drm_mode_config_funcs on BCM2711

On the BCM2711, our current definition of drm_mode_config_funcs uses the
custom vc4_fb_create().

However, that function relies on the buffer allocation path that was
relying on the GPU, and is no longer relevant.

Let's create another drm_mode_config_funcs structure that we will
register on the BCM2711.

Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220610115149.964394-7-maxime@cerno.tech
---
 drivers/gpu/drm/vc4/vc4_kms.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index 3c232d85ab856..1d3b31fb71eaa 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -997,6 +997,12 @@ static const struct drm_mode_config_funcs vc4_mode_funcs = {
 	.fb_create = vc4_fb_create,
 };
 
+static const struct drm_mode_config_funcs vc5_mode_funcs = {
+	.atomic_check = vc4_atomic_check,
+	.atomic_commit = drm_atomic_helper_commit,
+	.fb_create = drm_gem_fb_create,
+};
+
 int vc4_kms_load(struct drm_device *dev)
 {
 	struct vc4_dev *vc4 = to_vc4_dev(dev);
@@ -1031,7 +1037,7 @@ int vc4_kms_load(struct drm_device *dev)
 		dev->mode_config.max_height = 2048;
 	}
 
-	dev->mode_config.funcs = &vc4_mode_funcs;
+	dev->mode_config.funcs = vc4->is_vc5 ? &vc5_mode_funcs : &vc4_mode_funcs;
 	dev->mode_config.helper_private = &vc4_mode_config_helpers;
 	dev->mode_config.preferred_depth = 24;
 	dev->mode_config.async_page_flip = true;
-- 
GitLab


From 2095848661481e31339b32847acf7759b5635f38 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime@cerno.tech>
Date: Fri, 10 Jun 2022 13:51:42 +0200
Subject: [PATCH 0655/1731] drm/vc4: plane: Register a different
 drm_plane_helper_funcs on BCM2711

On the BCM2711, our current definition of drm_plane_helper_funcs uses
the custom vc4_prepare_fb() and vc4_cleanup_fb().

Those functions rely on the buffer allocation path that was relying on
the GPU, and is no longer relevant.

Let's create another drm_plane_helper_funcs structure that we will
register on the BCM2711.

Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220610115149.964394-8-maxime@cerno.tech
---
 drivers/gpu/drm/vc4/vc4_plane.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index ba7359516d75d..1e866dc00ac32 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -1389,6 +1389,13 @@ static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = {
 	.atomic_async_update = vc4_plane_atomic_async_update,
 };
 
+static const struct drm_plane_helper_funcs vc5_plane_helper_funcs = {
+	.atomic_check = vc4_plane_atomic_check,
+	.atomic_update = vc4_plane_atomic_update,
+	.atomic_async_check = vc4_plane_atomic_async_check,
+	.atomic_async_update = vc4_plane_atomic_async_update,
+};
+
 static bool vc4_format_mod_supported(struct drm_plane *plane,
 				     uint32_t format,
 				     uint64_t modifier)
@@ -1493,7 +1500,10 @@ struct drm_plane *vc4_plane_init(struct drm_device *dev,
 	if (ret)
 		return ERR_PTR(ret);
 
-	drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
+	if (vc4->is_vc5)
+		drm_plane_helper_add(plane, &vc5_plane_helper_funcs);
+	else
+		drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
 
 	drm_plane_create_alpha_property(plane);
 	drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
-- 
GitLab


From 257add942a477bb99bdf4bacc6190703f796dcff Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime@cerno.tech>
Date: Fri, 10 Jun 2022 13:51:43 +0200
Subject: [PATCH 0656/1731] drm/vc4: drv: Skip BO Backend Initialization on
 BCM2711

On the BCM2711, we currently call the vc4_bo_cache_init() and
vc4_gem_init() functions. These functions initialize the BO and GEM
backends.

However, this code was initially created to accomodate the requirements
of the GPU on the older SoCs, while the BCM2711 has a separate driver
for it. So let's just skip these calls when we're on a newer hardware.

Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220610115149.964394-9-maxime@cerno.tech
---
 drivers/gpu/drm/vc4/vc4_drv.c | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c
index 528a1e2761f17..ef4ab0563168d 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.c
+++ b/drivers/gpu/drm/vc4/vc4_drv.c
@@ -285,19 +285,23 @@ static int vc4_drm_bind(struct device *dev)
 	platform_set_drvdata(pdev, drm);
 	INIT_LIST_HEAD(&vc4->debugfs_list);
 
-	mutex_init(&vc4->bin_bo_lock);
+	if (!is_vc5) {
+		mutex_init(&vc4->bin_bo_lock);
 
-	ret = vc4_bo_cache_init(drm);
-	if (ret)
-		return ret;
+		ret = vc4_bo_cache_init(drm);
+		if (ret)
+			return ret;
+	}
 
 	ret = drmm_mode_config_init(drm);
 	if (ret)
 		return ret;
 
-	ret = vc4_gem_init(drm);
-	if (ret)
-		return ret;
+	if (!is_vc5) {
+		ret = vc4_gem_init(drm);
+		if (ret)
+			return ret;
+	}
 
 	node = of_find_compatible_node(NULL, NULL, "raspberrypi,bcm2835-firmware");
 	if (node) {
-- 
GitLab


From 2523e9dcc3be91bf9fdc0d1e542557ca00bbef42 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime@cerno.tech>
Date: Fri, 10 Jun 2022 13:51:44 +0200
Subject: [PATCH 0657/1731] drm/vc4: crtc: Use an union to store the page flip
 callback

We'll need to extend the vc4_async_flip_state structure to rely on
another callback implementation, so let's move the current one into a
union.

Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220610115149.964394-10-maxime@cerno.tech
---
 drivers/gpu/drm/vc4/vc4_crtc.c | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index dd5fb25d0f431..1f247c037ce0d 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -775,17 +775,17 @@ struct vc4_async_flip_state {
 	struct drm_framebuffer *old_fb;
 	struct drm_pending_vblank_event *event;
 
-	struct vc4_seqno_cb cb;
+	union {
+		struct vc4_seqno_cb seqno;
+	} cb;
 };
 
 /* Called when the V3D execution for the BO being flipped to is done, so that
  * we can actually update the plane's address to point to it.
  */
 static void
-vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
+vc4_async_page_flip_complete(struct vc4_async_flip_state *flip_state)
 {
-	struct vc4_async_flip_state *flip_state =
-		container_of(cb, struct vc4_async_flip_state, cb);
 	struct drm_crtc *crtc = flip_state->crtc;
 	struct drm_device *dev = crtc->dev;
 	struct drm_plane *plane = crtc->primary;
@@ -821,6 +821,14 @@ vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
 	kfree(flip_state);
 }
 
+static void vc4_async_page_flip_seqno_complete(struct vc4_seqno_cb *cb)
+{
+	struct vc4_async_flip_state *flip_state =
+		container_of(cb, struct vc4_async_flip_state, cb.seqno);
+
+	vc4_async_page_flip_complete(flip_state);
+}
+
 /* Implements async (non-vblank-synced) page flips.
  *
  * The page flip ioctl needs to return immediately, so we grab the
@@ -881,8 +889,8 @@ static int vc4_async_page_flip(struct drm_crtc *crtc,
 	 */
 	drm_atomic_set_fb_for_plane(plane->state, fb);
 
-	vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
-			   vc4_async_page_flip_complete);
+	vc4_queue_seqno_cb(dev, &flip_state->cb.seqno, bo->seqno,
+			   vc4_async_page_flip_seqno_complete);
 
 	/* Driver takes ownership of state on successful async commit. */
 	return 0;
-- 
GitLab


From 4d12c36fb73b5c49fe2f95d06515fd9846010fd2 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime@cerno.tech>
Date: Fri, 10 Jun 2022 13:51:45 +0200
Subject: [PATCH 0658/1731] drm/vc4: crtc: Move the BO handling out of common
 page-flip callback

We'll soon introduce another completion callback source that won't need
to use the BO reference counting, so let's move it around to create a
function we will be able to share between both callbacks.

Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220610115149.964394-11-maxime@cerno.tech
---
 drivers/gpu/drm/vc4/vc4_crtc.c | 34 ++++++++++++++++++++--------------
 1 file changed, 20 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 1f247c037ce0d..0410db97b9d10 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -802,21 +802,8 @@ vc4_async_page_flip_complete(struct vc4_async_flip_state *flip_state)
 	drm_crtc_vblank_put(crtc);
 	drm_framebuffer_put(flip_state->fb);
 
-	/* Decrement the BO usecnt in order to keep the inc/dec calls balanced
-	 * when the planes are updated through the async update path.
-	 * FIXME: we should move to generic async-page-flip when it's
-	 * available, so that we can get rid of this hand-made cleanup_fb()
-	 * logic.
-	 */
-	if (flip_state->old_fb) {
-		struct drm_gem_cma_object *cma_bo;
-		struct vc4_bo *bo;
-
-		cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
-		bo = to_vc4_bo(&cma_bo->base);
-		vc4_bo_dec_usecnt(bo);
+	if (flip_state->old_fb)
 		drm_framebuffer_put(flip_state->old_fb);
-	}
 
 	kfree(flip_state);
 }
@@ -825,8 +812,27 @@ static void vc4_async_page_flip_seqno_complete(struct vc4_seqno_cb *cb)
 {
 	struct vc4_async_flip_state *flip_state =
 		container_of(cb, struct vc4_async_flip_state, cb.seqno);
+	struct vc4_bo *bo = NULL;
+
+	if (flip_state->old_fb) {
+		struct drm_gem_cma_object *cma_bo =
+			drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
+		bo = to_vc4_bo(&cma_bo->base);
+	}
 
 	vc4_async_page_flip_complete(flip_state);
+
+	/*
+	 * Decrement the BO usecnt in order to keep the inc/dec
+	 * calls balanced when the planes are updated through
+	 * the async update path.
+	 *
+	 * FIXME: we should move to generic async-page-flip when
+	 * it's available, so that we can get rid of this
+	 * hand-made cleanup_fb() logic.
+	 */
+	if (bo)
+		vc4_bo_dec_usecnt(bo);
 }
 
 /* Implements async (non-vblank-synced) page flips.
-- 
GitLab


From f6766fb265b18248d2c4bc643eb99e853f293dd6 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime@cerno.tech>
Date: Fri, 10 Jun 2022 13:51:46 +0200
Subject: [PATCH 0659/1731] drm/vc4: crtc: Move the BO Handling out of Common
 Page-Flip Handler

The function vc4_async_page_flip() handles asynchronous page-flips in
the vc4 driver.

However, it mixes some generic code with code that should only be run on
older generations that have the GPU handled by the vc4 driver.

Let's split the generic part out of vc4_async_page_flip() and into a
common function that we be reusable by an handler made for the BCM2711.

Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220610115149.964394-12-maxime@cerno.tech
---
 drivers/gpu/drm/vc4/vc4_crtc.c | 73 ++++++++++++++++++++++------------
 1 file changed, 48 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 0410db97b9d10..c00fb964c5347 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -835,40 +835,21 @@ static void vc4_async_page_flip_seqno_complete(struct vc4_seqno_cb *cb)
 		vc4_bo_dec_usecnt(bo);
 }
 
-/* Implements async (non-vblank-synced) page flips.
- *
- * The page flip ioctl needs to return immediately, so we grab the
- * modeset semaphore on the pipe, and queue the address update for
- * when V3D is done with the BO being flipped to.
- */
-static int vc4_async_page_flip(struct drm_crtc *crtc,
-			       struct drm_framebuffer *fb,
-			       struct drm_pending_vblank_event *event,
-			       uint32_t flags)
+static int
+vc4_async_page_flip_common(struct drm_crtc *crtc,
+			   struct drm_framebuffer *fb,
+			   struct drm_pending_vblank_event *event,
+			   uint32_t flags)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_plane *plane = crtc->primary;
-	int ret = 0;
 	struct vc4_async_flip_state *flip_state;
 	struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 	struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 
-	/* Increment the BO usecnt here, so that we never end up with an
-	 * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
-	 * plane is later updated through the non-async path.
-	 * FIXME: we should move to generic async-page-flip when it's
-	 * available, so that we can get rid of this hand-made prepare_fb()
-	 * logic.
-	 */
-	ret = vc4_bo_inc_usecnt(bo);
-	if (ret)
-		return ret;
-
 	flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
-	if (!flip_state) {
-		vc4_bo_dec_usecnt(bo);
+	if (!flip_state)
 		return -ENOMEM;
-	}
 
 	drm_framebuffer_get(fb);
 	flip_state->fb = fb;
@@ -902,6 +883,48 @@ static int vc4_async_page_flip(struct drm_crtc *crtc,
 	return 0;
 }
 
+/* Implements async (non-vblank-synced) page flips.
+ *
+ * The page flip ioctl needs to return immediately, so we grab the
+ * modeset semaphore on the pipe, and queue the address update for
+ * when V3D is done with the BO being flipped to.
+ */
+static int vc4_async_page_flip(struct drm_crtc *crtc,
+			       struct drm_framebuffer *fb,
+			       struct drm_pending_vblank_event *event,
+			       uint32_t flags)
+{
+	struct drm_device *dev = crtc->dev;
+	struct vc4_dev *vc4 = to_vc4_dev(dev);
+	struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
+	struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
+	int ret;
+
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
+	/*
+	 * Increment the BO usecnt here, so that we never end up with an
+	 * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
+	 * plane is later updated through the non-async path.
+	 *
+	 * FIXME: we should move to generic async-page-flip when
+	 * it's available, so that we can get rid of this
+	 * hand-made prepare_fb() logic.
+	 */
+	ret = vc4_bo_inc_usecnt(bo);
+	if (ret)
+		return ret;
+
+	ret = vc4_async_page_flip_common(crtc, fb, event, flags);
+	if (ret) {
+		vc4_bo_dec_usecnt(bo);
+		return ret;
+	}
+
+	return 0;
+}
+
 int vc4_page_flip(struct drm_crtc *crtc,
 		  struct drm_framebuffer *fb,
 		  struct drm_pending_vblank_event *event,
-- 
GitLab


From d87db1c79d6f9ec5505be2ff4ca8811d6e88a667 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime@cerno.tech>
Date: Fri, 10 Jun 2022 13:51:47 +0200
Subject: [PATCH 0660/1731] drm/vc4: crtc: Don't call into BO Handling on Async
 Page-Flips on BCM2711

The BCM2711 doesn't have a v3d GPU so we don't want to call into its BO
management code. Let's create an asynchronous page-flip handler for the
BCM2711 that just calls into the common code.

Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220610115149.964394-13-maxime@cerno.tech
---
 drivers/gpu/drm/vc4/vc4_crtc.c | 21 ++++++++++++++++++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index c00fb964c5347..a3c04d6cbd20f 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -925,16 +925,31 @@ static int vc4_async_page_flip(struct drm_crtc *crtc,
 	return 0;
 }
 
+static int vc5_async_page_flip(struct drm_crtc *crtc,
+			       struct drm_framebuffer *fb,
+			       struct drm_pending_vblank_event *event,
+			       uint32_t flags)
+{
+	return vc4_async_page_flip_common(crtc, fb, event, flags);
+}
+
 int vc4_page_flip(struct drm_crtc *crtc,
 		  struct drm_framebuffer *fb,
 		  struct drm_pending_vblank_event *event,
 		  uint32_t flags,
 		  struct drm_modeset_acquire_ctx *ctx)
 {
-	if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
-		return vc4_async_page_flip(crtc, fb, event, flags);
-	else
+	if (flags & DRM_MODE_PAGE_FLIP_ASYNC) {
+		struct drm_device *dev = crtc->dev;
+		struct vc4_dev *vc4 = to_vc4_dev(dev);
+
+		if (vc4->is_vc5)
+			return vc5_async_page_flip(crtc, fb, event, flags);
+		else
+			return vc4_async_page_flip(crtc, fb, event, flags);
+	} else {
 		return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
+	}
 }
 
 struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
-- 
GitLab


From d19e00ee06a9abf590b178c34cad637a516752f8 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime@cerno.tech>
Date: Fri, 10 Jun 2022 13:51:48 +0200
Subject: [PATCH 0661/1731] drm/vc4: crtc: Fix out of order frames during
 asynchronous page flips

When doing an asynchronous page flip (PAGE_FLIP ioctl with the
DRM_MODE_PAGE_FLIP_ASYNC flag set), the current code waits for the
possible GPU buffer being rendered through a call to
vc4_queue_seqno_cb().

On the BCM2835-37, the GPU driver is part of the vc4 driver and that
function is defined in vc4_gem.c to wait for the buffer to be rendered,
and once it's done, call a callback.

However, on the BCM2711 used on the RaspberryPi4, the GPU driver is
separate (v3d) and that function won't do anything. This was working
because we were going into a path, due to uninitialized variables, that
was always scheduling the callback.

However, we were never actually waiting for the buffer to be rendered
which was resulting in frames being displayed out of order.

The generic API to signal those kind of completion in the kernel are the
DMA fences, and fortunately the v3d drivers supports them and signal
when its job is done. That API also provides an equivalent function that
allows to have a callback being executed when the fence is signalled as
done.

Let's change our driver a bit to rely on the previous function for the
older SoCs, and on DMA fences for the BCM2711.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Reviewed-by: Melissa Wen <mwen@igalia.com>
Link: https://lore.kernel.org/r/20220610115149.964394-14-maxime@cerno.tech
---
 drivers/gpu/drm/vc4/vc4_crtc.c | 50 +++++++++++++++++++++++++++++++---
 1 file changed, 46 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index a3c04d6cbd20f..9355213dc883c 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -776,6 +776,7 @@ struct vc4_async_flip_state {
 	struct drm_pending_vblank_event *event;
 
 	union {
+		struct dma_fence_cb fence;
 		struct vc4_seqno_cb seqno;
 	} cb;
 };
@@ -835,6 +836,50 @@ static void vc4_async_page_flip_seqno_complete(struct vc4_seqno_cb *cb)
 		vc4_bo_dec_usecnt(bo);
 }
 
+static void vc4_async_page_flip_fence_complete(struct dma_fence *fence,
+					       struct dma_fence_cb *cb)
+{
+	struct vc4_async_flip_state *flip_state =
+		container_of(cb, struct vc4_async_flip_state, cb.fence);
+
+	vc4_async_page_flip_complete(flip_state);
+	dma_fence_put(fence);
+}
+
+static int vc4_async_set_fence_cb(struct drm_device *dev,
+				  struct vc4_async_flip_state *flip_state)
+{
+	struct drm_framebuffer *fb = flip_state->fb;
+	struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
+	struct vc4_dev *vc4 = to_vc4_dev(dev);
+	struct dma_fence *fence;
+	int ret;
+
+	if (!vc4->is_vc5) {
+		struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
+
+		return vc4_queue_seqno_cb(dev, &flip_state->cb.seqno, bo->seqno,
+					  vc4_async_page_flip_seqno_complete);
+	}
+
+	ret = dma_resv_get_singleton(cma_bo->base.resv, DMA_RESV_USAGE_READ, &fence);
+	if (ret)
+		return ret;
+
+	/* If there's no fence, complete the page flip immediately */
+	if (!fence) {
+		vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence);
+		return 0;
+	}
+
+	/* If the fence has already been completed, complete the page flip */
+	if (dma_fence_add_callback(fence, &flip_state->cb.fence,
+				   vc4_async_page_flip_fence_complete))
+		vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence);
+
+	return 0;
+}
+
 static int
 vc4_async_page_flip_common(struct drm_crtc *crtc,
 			   struct drm_framebuffer *fb,
@@ -844,8 +889,6 @@ vc4_async_page_flip_common(struct drm_crtc *crtc,
 	struct drm_device *dev = crtc->dev;
 	struct drm_plane *plane = crtc->primary;
 	struct vc4_async_flip_state *flip_state;
-	struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
-	struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 
 	flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 	if (!flip_state)
@@ -876,8 +919,7 @@ vc4_async_page_flip_common(struct drm_crtc *crtc,
 	 */
 	drm_atomic_set_fb_for_plane(plane->state, fb);
 
-	vc4_queue_seqno_cb(dev, &flip_state->cb.seqno, bo->seqno,
-			   vc4_async_page_flip_seqno_complete);
+	vc4_async_set_fence_cb(dev, flip_state);
 
 	/* Driver takes ownership of state on successful async commit. */
 	return 0;
-- 
GitLab


From 30f8c74ca9b7b3a2db55f6bb1d2e9f8c47a79f94 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime@cerno.tech>
Date: Fri, 10 Jun 2022 13:51:49 +0200
Subject: [PATCH 0662/1731] drm/vc4: Warn if some v3d code is run on BCM2711

The BCM2711 has a separate driver for the v3d, and thus we can't call
into any of the driver entrypoints that rely on the v3d being there.

Let's add a bunch of checks and complain loudly if that ever happen.

Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220610115149.964394-15-maxime@cerno.tech
---
 drivers/gpu/drm/vc4/vc4_bo.c               | 49 ++++++++++++++++++++++
 drivers/gpu/drm/vc4/vc4_drv.c              | 11 +++++
 drivers/gpu/drm/vc4/vc4_drv.h              |  6 +++
 drivers/gpu/drm/vc4/vc4_gem.c              | 40 ++++++++++++++++++
 drivers/gpu/drm/vc4/vc4_irq.c              | 16 +++++++
 drivers/gpu/drm/vc4/vc4_kms.c              |  4 ++
 drivers/gpu/drm/vc4/vc4_perfmon.c          | 47 ++++++++++++++++++++-
 drivers/gpu/drm/vc4/vc4_render_cl.c        |  4 ++
 drivers/gpu/drm/vc4/vc4_v3d.c              | 15 +++++++
 drivers/gpu/drm/vc4/vc4_validate.c         | 16 +++++++
 drivers/gpu/drm/vc4/vc4_validate_shaders.c |  4 ++
 11 files changed, 211 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/vc4/vc4_bo.c b/drivers/gpu/drm/vc4/vc4_bo.c
index 3ca16d682fc0f..b8d8563128464 100644
--- a/drivers/gpu/drm/vc4/vc4_bo.c
+++ b/drivers/gpu/drm/vc4/vc4_bo.c
@@ -248,6 +248,9 @@ void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo)
 {
 	struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev);
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return;
+
 	mutex_lock(&vc4->purgeable.lock);
 	list_add_tail(&bo->size_head, &vc4->purgeable.list);
 	vc4->purgeable.num++;
@@ -259,6 +262,9 @@ static void vc4_bo_remove_from_purgeable_pool_locked(struct vc4_bo *bo)
 {
 	struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev);
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return;
+
 	/* list_del_init() is used here because the caller might release
 	 * the purgeable lock in order to acquire the madv one and update the
 	 * madv status.
@@ -387,6 +393,9 @@ struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size)
 	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	struct vc4_bo *bo;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return ERR_PTR(-ENODEV);
+
 	bo = kzalloc(sizeof(*bo), GFP_KERNEL);
 	if (!bo)
 		return ERR_PTR(-ENOMEM);
@@ -413,6 +422,9 @@ struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t unaligned_size,
 	struct drm_gem_cma_object *cma_obj;
 	struct vc4_bo *bo;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return ERR_PTR(-ENODEV);
+
 	if (size == 0)
 		return ERR_PTR(-EINVAL);
 
@@ -475,9 +487,13 @@ int vc4_bo_dumb_create(struct drm_file *file_priv,
 		       struct drm_device *dev,
 		       struct drm_mode_create_dumb *args)
 {
+	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	struct vc4_bo *bo = NULL;
 	int ret;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	ret = vc4_dumb_fixup_args(args);
 	if (ret)
 		return ret;
@@ -598,8 +614,12 @@ static void vc4_bo_cache_time_work(struct work_struct *work)
 
 int vc4_bo_inc_usecnt(struct vc4_bo *bo)
 {
+	struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev);
 	int ret;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	/* Fast path: if the BO is already retained by someone, no need to
 	 * check the madv status.
 	 */
@@ -634,6 +654,11 @@ int vc4_bo_inc_usecnt(struct vc4_bo *bo)
 
 void vc4_bo_dec_usecnt(struct vc4_bo *bo)
 {
+	struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev);
+
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return;
+
 	/* Fast path: if the BO is still retained by someone, no need to test
 	 * the madv value.
 	 */
@@ -753,6 +778,9 @@ int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
 	struct vc4_bo *bo = NULL;
 	int ret;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	ret = vc4_grab_bin_bo(vc4, vc4file);
 	if (ret)
 		return ret;
@@ -776,9 +804,13 @@ int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
 		      struct drm_file *file_priv)
 {
+	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	struct drm_vc4_mmap_bo *args = data;
 	struct drm_gem_object *gem_obj;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	gem_obj = drm_gem_object_lookup(file_priv, args->handle);
 	if (!gem_obj) {
 		DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle);
@@ -802,6 +834,9 @@ vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
 	struct vc4_bo *bo = NULL;
 	int ret;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	if (args->size == 0)
 		return -EINVAL;
 
@@ -872,11 +907,15 @@ fail:
 int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
 			 struct drm_file *file_priv)
 {
+	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	struct drm_vc4_set_tiling *args = data;
 	struct drm_gem_object *gem_obj;
 	struct vc4_bo *bo;
 	bool t_format;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	if (args->flags != 0)
 		return -EINVAL;
 
@@ -915,10 +954,14 @@ int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
 int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
 			 struct drm_file *file_priv)
 {
+	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	struct drm_vc4_get_tiling *args = data;
 	struct drm_gem_object *gem_obj;
 	struct vc4_bo *bo;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	if (args->flags != 0 || args->modifier != 0)
 		return -EINVAL;
 
@@ -945,6 +988,9 @@ int vc4_bo_cache_init(struct drm_device *dev)
 	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	int i;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	/* Create the initial set of BO labels that the kernel will
 	 * use.  This lets us avoid a bunch of string reallocation in
 	 * the kernel's draw and BO allocation paths.
@@ -1004,6 +1050,9 @@ int vc4_label_bo_ioctl(struct drm_device *dev, void *data,
 	struct drm_gem_object *gem_obj;
 	int ret = 0, label;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	if (!args->len)
 		return -EINVAL;
 
diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c
index ef4ab0563168d..0f0f0263e744c 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.c
+++ b/drivers/gpu/drm/vc4/vc4_drv.c
@@ -99,6 +99,9 @@ static int vc4_get_param_ioctl(struct drm_device *dev, void *data,
 	if (args->pad != 0)
 		return -EINVAL;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	if (!vc4->v3d)
 		return -ENODEV;
 
@@ -142,11 +145,16 @@ static int vc4_get_param_ioctl(struct drm_device *dev, void *data,
 
 static int vc4_open(struct drm_device *dev, struct drm_file *file)
 {
+	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	struct vc4_file *vc4file;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	vc4file = kzalloc(sizeof(*vc4file), GFP_KERNEL);
 	if (!vc4file)
 		return -ENOMEM;
+	vc4file->dev = vc4;
 
 	vc4_perfmon_open_file(vc4file);
 	file->driver_priv = vc4file;
@@ -158,6 +166,9 @@ static void vc4_close(struct drm_device *dev, struct drm_file *file)
 	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	struct vc4_file *vc4file = file->driver_priv;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return;
+
 	if (vc4file->bin_bo_used)
 		vc4_v3d_bin_bo_put(vc4);
 
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 9c324c12c4106..93fd55b9e99ee 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -48,6 +48,8 @@ enum vc4_kernel_bo_type {
  * done. This way, only events related to a specific job will be counted.
  */
 struct vc4_perfmon {
+	struct vc4_dev *dev;
+
 	/* Tracks the number of users of the perfmon, when this counter reaches
 	 * zero the perfmon is destroyed.
 	 */
@@ -580,6 +582,8 @@ to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
 #define VC4_REG32(reg) { .name = #reg, .offset = reg }
 
 struct vc4_exec_info {
+	struct vc4_dev *dev;
+
 	/* Sequence number for this bin/render job. */
 	uint64_t seqno;
 
@@ -701,6 +705,8 @@ struct vc4_exec_info {
  * released when the DRM file is closed should be placed here.
  */
 struct vc4_file {
+	struct vc4_dev *dev;
+
 	struct {
 		struct idr idr;
 		struct mutex lock;
diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c
index 9eaf304fc20d4..fe10d9c3fff8a 100644
--- a/drivers/gpu/drm/vc4/vc4_gem.c
+++ b/drivers/gpu/drm/vc4/vc4_gem.c
@@ -76,6 +76,9 @@ vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
 	u32 i;
 	int ret = 0;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	if (!vc4->v3d) {
 		DRM_DEBUG("VC4_GET_HANG_STATE with no VC4 V3D probed\n");
 		return -ENODEV;
@@ -386,6 +389,9 @@ vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno, uint64_t timeout_ns,
 	unsigned long timeout_expire;
 	DEFINE_WAIT(wait);
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	if (vc4->finished_seqno >= seqno)
 		return 0;
 
@@ -468,6 +474,9 @@ vc4_submit_next_bin_job(struct drm_device *dev)
 	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	struct vc4_exec_info *exec;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return;
+
 again:
 	exec = vc4_first_bin_job(vc4);
 	if (!exec)
@@ -513,6 +522,9 @@ vc4_submit_next_render_job(struct drm_device *dev)
 	if (!exec)
 		return;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return;
+
 	/* A previous RCL may have written to one of our textures, and
 	 * our full cache flush at bin time may have occurred before
 	 * that RCL completed.  Flush the texture cache now, but not
@@ -531,6 +543,9 @@ vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec)
 	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	bool was_empty = list_empty(&vc4->render_job_list);
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return;
+
 	list_move_tail(&exec->head, &vc4->render_job_list);
 	if (was_empty)
 		vc4_submit_next_render_job(dev);
@@ -997,6 +1012,9 @@ vc4_job_handle_completed(struct vc4_dev *vc4)
 	unsigned long irqflags;
 	struct vc4_seqno_cb *cb, *cb_temp;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return;
+
 	spin_lock_irqsave(&vc4->job_lock, irqflags);
 	while (!list_empty(&vc4->job_done_list)) {
 		struct vc4_exec_info *exec =
@@ -1033,6 +1051,9 @@ int vc4_queue_seqno_cb(struct drm_device *dev,
 	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	unsigned long irqflags;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	cb->func = func;
 	INIT_WORK(&cb->work, vc4_seqno_cb_work);
 
@@ -1083,8 +1104,12 @@ int
 vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
 		     struct drm_file *file_priv)
 {
+	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	struct drm_vc4_wait_seqno *args = data;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	return vc4_wait_for_seqno_ioctl_helper(dev, args->seqno,
 					       &args->timeout_ns);
 }
@@ -1093,11 +1118,15 @@ int
 vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
 		  struct drm_file *file_priv)
 {
+	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	int ret;
 	struct drm_vc4_wait_bo *args = data;
 	struct drm_gem_object *gem_obj;
 	struct vc4_bo *bo;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	if (args->pad != 0)
 		return -EINVAL;
 
@@ -1144,6 +1173,9 @@ vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
 				  args->shader_rec_size,
 				  args->bo_handle_count);
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	if (!vc4->v3d) {
 		DRM_DEBUG("VC4_SUBMIT_CL with no VC4 V3D probed\n");
 		return -ENODEV;
@@ -1167,6 +1199,7 @@ vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
 		DRM_ERROR("malloc failure on exec struct\n");
 		return -ENOMEM;
 	}
+	exec->dev = vc4;
 
 	ret = vc4_v3d_pm_get(vc4);
 	if (ret) {
@@ -1276,6 +1309,9 @@ int vc4_gem_init(struct drm_device *dev)
 {
 	struct vc4_dev *vc4 = to_vc4_dev(dev);
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	vc4->dma_fence_context = dma_fence_context_alloc(1);
 
 	INIT_LIST_HEAD(&vc4->bin_job_list);
@@ -1321,11 +1357,15 @@ static void vc4_gem_destroy(struct drm_device *dev, void *unused)
 int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data,
 			  struct drm_file *file_priv)
 {
+	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	struct drm_vc4_gem_madvise *args = data;
 	struct drm_gem_object *gem_obj;
 	struct vc4_bo *bo;
 	int ret;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	switch (args->madv) {
 	case VC4_MADV_DONTNEED:
 	case VC4_MADV_WILLNEED:
diff --git a/drivers/gpu/drm/vc4/vc4_irq.c b/drivers/gpu/drm/vc4/vc4_irq.c
index 4342fb43e8c1d..2eacfb6773d28 100644
--- a/drivers/gpu/drm/vc4/vc4_irq.c
+++ b/drivers/gpu/drm/vc4/vc4_irq.c
@@ -265,6 +265,9 @@ vc4_irq_enable(struct drm_device *dev)
 {
 	struct vc4_dev *vc4 = to_vc4_dev(dev);
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return;
+
 	if (!vc4->v3d)
 		return;
 
@@ -279,6 +282,9 @@ vc4_irq_disable(struct drm_device *dev)
 {
 	struct vc4_dev *vc4 = to_vc4_dev(dev);
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return;
+
 	if (!vc4->v3d)
 		return;
 
@@ -296,8 +302,12 @@ vc4_irq_disable(struct drm_device *dev)
 
 int vc4_irq_install(struct drm_device *dev, int irq)
 {
+	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	int ret;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	if (irq == IRQ_NOTCONNECTED)
 		return -ENOTCONN;
 
@@ -316,6 +326,9 @@ void vc4_irq_uninstall(struct drm_device *dev)
 {
 	struct vc4_dev *vc4 = to_vc4_dev(dev);
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return;
+
 	vc4_irq_disable(dev);
 	free_irq(vc4->irq, dev);
 }
@@ -326,6 +339,9 @@ void vc4_irq_reset(struct drm_device *dev)
 	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	unsigned long irqflags;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return;
+
 	/* Acknowledge any stale IRQs. */
 	V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
 
diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index 1d3b31fb71eaa..893d831b24aa0 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -479,8 +479,12 @@ static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev,
 					     struct drm_file *file_priv,
 					     const struct drm_mode_fb_cmd2 *mode_cmd)
 {
+	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	struct drm_mode_fb_cmd2 mode_cmd_local;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return ERR_PTR(-ENODEV);
+
 	/* If the user didn't specify a modifier, use the
 	 * vc4_set_tiling_ioctl() state for the BO.
 	 */
diff --git a/drivers/gpu/drm/vc4/vc4_perfmon.c b/drivers/gpu/drm/vc4/vc4_perfmon.c
index 18abc06335c11..c7f5adb6bcf8b 100644
--- a/drivers/gpu/drm/vc4/vc4_perfmon.c
+++ b/drivers/gpu/drm/vc4/vc4_perfmon.c
@@ -17,13 +17,27 @@
 
 void vc4_perfmon_get(struct vc4_perfmon *perfmon)
 {
+	struct vc4_dev *vc4 = perfmon->dev;
+
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return;
+
 	if (perfmon)
 		refcount_inc(&perfmon->refcnt);
 }
 
 void vc4_perfmon_put(struct vc4_perfmon *perfmon)
 {
-	if (perfmon && refcount_dec_and_test(&perfmon->refcnt))
+	struct vc4_dev *vc4;
+
+	if (!perfmon)
+		return;
+
+	vc4 = perfmon->dev;
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return;
+
+	if (refcount_dec_and_test(&perfmon->refcnt))
 		kfree(perfmon);
 }
 
@@ -32,6 +46,9 @@ void vc4_perfmon_start(struct vc4_dev *vc4, struct vc4_perfmon *perfmon)
 	unsigned int i;
 	u32 mask;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return;
+
 	if (WARN_ON_ONCE(!perfmon || vc4->active_perfmon))
 		return;
 
@@ -49,6 +66,9 @@ void vc4_perfmon_stop(struct vc4_dev *vc4, struct vc4_perfmon *perfmon,
 {
 	unsigned int i;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return;
+
 	if (WARN_ON_ONCE(!vc4->active_perfmon ||
 			 perfmon != vc4->active_perfmon))
 		return;
@@ -64,8 +84,12 @@ void vc4_perfmon_stop(struct vc4_dev *vc4, struct vc4_perfmon *perfmon,
 
 struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id)
 {
+	struct vc4_dev *vc4 = vc4file->dev;
 	struct vc4_perfmon *perfmon;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return NULL;
+
 	mutex_lock(&vc4file->perfmon.lock);
 	perfmon = idr_find(&vc4file->perfmon.idr, id);
 	vc4_perfmon_get(perfmon);
@@ -76,8 +100,14 @@ struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id)
 
 void vc4_perfmon_open_file(struct vc4_file *vc4file)
 {
+	struct vc4_dev *vc4 = vc4file->dev;
+
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return;
+
 	mutex_init(&vc4file->perfmon.lock);
 	idr_init_base(&vc4file->perfmon.idr, VC4_PERFMONID_MIN);
+	vc4file->dev = vc4;
 }
 
 static int vc4_perfmon_idr_del(int id, void *elem, void *data)
@@ -91,6 +121,11 @@ static int vc4_perfmon_idr_del(int id, void *elem, void *data)
 
 void vc4_perfmon_close_file(struct vc4_file *vc4file)
 {
+	struct vc4_dev *vc4 = vc4file->dev;
+
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return;
+
 	mutex_lock(&vc4file->perfmon.lock);
 	idr_for_each(&vc4file->perfmon.idr, vc4_perfmon_idr_del, NULL);
 	idr_destroy(&vc4file->perfmon.idr);
@@ -107,6 +142,9 @@ int vc4_perfmon_create_ioctl(struct drm_device *dev, void *data,
 	unsigned int i;
 	int ret;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	if (!vc4->v3d) {
 		DRM_DEBUG("Creating perfmon no VC4 V3D probed\n");
 		return -ENODEV;
@@ -127,6 +165,7 @@ int vc4_perfmon_create_ioctl(struct drm_device *dev, void *data,
 			  GFP_KERNEL);
 	if (!perfmon)
 		return -ENOMEM;
+	perfmon->dev = vc4;
 
 	for (i = 0; i < req->ncounters; i++)
 		perfmon->events[i] = req->events[i];
@@ -157,6 +196,9 @@ int vc4_perfmon_destroy_ioctl(struct drm_device *dev, void *data,
 	struct drm_vc4_perfmon_destroy *req = data;
 	struct vc4_perfmon *perfmon;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	if (!vc4->v3d) {
 		DRM_DEBUG("Destroying perfmon no VC4 V3D probed\n");
 		return -ENODEV;
@@ -182,6 +224,9 @@ int vc4_perfmon_get_values_ioctl(struct drm_device *dev, void *data,
 	struct vc4_perfmon *perfmon;
 	int ret;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	if (!vc4->v3d) {
 		DRM_DEBUG("Getting perfmon no VC4 V3D probed\n");
 		return -ENODEV;
diff --git a/drivers/gpu/drm/vc4/vc4_render_cl.c b/drivers/gpu/drm/vc4/vc4_render_cl.c
index 3c918eeaf56ea..f6b7dc3df08cd 100644
--- a/drivers/gpu/drm/vc4/vc4_render_cl.c
+++ b/drivers/gpu/drm/vc4/vc4_render_cl.c
@@ -593,11 +593,15 @@ vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec,
 
 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec)
 {
+	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	struct vc4_rcl_setup setup = {0};
 	struct drm_vc4_submit_cl *args = exec->args;
 	bool has_bin = args->bin_cl_size != 0;
 	int ret;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	if (args->min_x_tile > args->max_x_tile ||
 	    args->min_y_tile > args->max_y_tile) {
 		DRM_DEBUG("Bad render tile set (%d,%d)-(%d,%d)\n",
diff --git a/drivers/gpu/drm/vc4/vc4_v3d.c b/drivers/gpu/drm/vc4/vc4_v3d.c
index 7bb3067f84256..cc714dcfe1f22 100644
--- a/drivers/gpu/drm/vc4/vc4_v3d.c
+++ b/drivers/gpu/drm/vc4/vc4_v3d.c
@@ -127,6 +127,9 @@ static int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused)
 int
 vc4_v3d_pm_get(struct vc4_dev *vc4)
 {
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	mutex_lock(&vc4->power_lock);
 	if (vc4->power_refcount++ == 0) {
 		int ret = pm_runtime_get_sync(&vc4->v3d->pdev->dev);
@@ -145,6 +148,9 @@ vc4_v3d_pm_get(struct vc4_dev *vc4)
 void
 vc4_v3d_pm_put(struct vc4_dev *vc4)
 {
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return;
+
 	mutex_lock(&vc4->power_lock);
 	if (--vc4->power_refcount == 0) {
 		pm_runtime_mark_last_busy(&vc4->v3d->pdev->dev);
@@ -172,6 +178,9 @@ int vc4_v3d_get_bin_slot(struct vc4_dev *vc4)
 	uint64_t seqno = 0;
 	struct vc4_exec_info *exec;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 try_again:
 	spin_lock_irqsave(&vc4->job_lock, irqflags);
 	slot = ffs(~vc4->bin_alloc_used);
@@ -316,6 +325,9 @@ int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used)
 {
 	int ret = 0;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	mutex_lock(&vc4->bin_bo_lock);
 
 	if (used && *used)
@@ -348,6 +360,9 @@ static void bin_bo_release(struct kref *ref)
 
 void vc4_v3d_bin_bo_put(struct vc4_dev *vc4)
 {
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return;
+
 	mutex_lock(&vc4->bin_bo_lock);
 	kref_put(&vc4->bin_bo_kref, bin_bo_release);
 	mutex_unlock(&vc4->bin_bo_lock);
diff --git a/drivers/gpu/drm/vc4/vc4_validate.c b/drivers/gpu/drm/vc4/vc4_validate.c
index eec76af49f041..833eb623d545f 100644
--- a/drivers/gpu/drm/vc4/vc4_validate.c
+++ b/drivers/gpu/drm/vc4/vc4_validate.c
@@ -105,9 +105,13 @@ size_is_lt(uint32_t width, uint32_t height, int cpp)
 struct drm_gem_cma_object *
 vc4_use_bo(struct vc4_exec_info *exec, uint32_t hindex)
 {
+	struct vc4_dev *vc4 = exec->dev;
 	struct drm_gem_cma_object *obj;
 	struct vc4_bo *bo;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return NULL;
+
 	if (hindex >= exec->bo_count) {
 		DRM_DEBUG("BO index %d greater than BO count %d\n",
 			  hindex, exec->bo_count);
@@ -160,10 +164,14 @@ vc4_check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo,
 		   uint32_t offset, uint8_t tiling_format,
 		   uint32_t width, uint32_t height, uint8_t cpp)
 {
+	struct vc4_dev *vc4 = exec->dev;
 	uint32_t aligned_width, aligned_height, stride, size;
 	uint32_t utile_w = utile_width(cpp);
 	uint32_t utile_h = utile_height(cpp);
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	/* The shaded vertex format stores signed 12.4 fixed point
 	 * (-2048,2047) offsets from the viewport center, so we should
 	 * never have a render target larger than 4096.  The texture
@@ -482,10 +490,14 @@ vc4_validate_bin_cl(struct drm_device *dev,
 		    void *unvalidated,
 		    struct vc4_exec_info *exec)
 {
+	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	uint32_t len = exec->args->bin_cl_size;
 	uint32_t dst_offset = 0;
 	uint32_t src_offset = 0;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	while (src_offset < len) {
 		void *dst_pkt = validated + dst_offset;
 		void *src_pkt = unvalidated + src_offset;
@@ -926,9 +938,13 @@ int
 vc4_validate_shader_recs(struct drm_device *dev,
 			 struct vc4_exec_info *exec)
 {
+	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	uint32_t i;
 	int ret = 0;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return -ENODEV;
+
 	for (i = 0; i < exec->shader_state_count; i++) {
 		ret = validate_gl_shader_rec(dev, exec, &exec->shader_state[i]);
 		if (ret)
diff --git a/drivers/gpu/drm/vc4/vc4_validate_shaders.c b/drivers/gpu/drm/vc4/vc4_validate_shaders.c
index 7cf82b071de29..e315aeb5fef5a 100644
--- a/drivers/gpu/drm/vc4/vc4_validate_shaders.c
+++ b/drivers/gpu/drm/vc4/vc4_validate_shaders.c
@@ -778,6 +778,7 @@ vc4_handle_branch_target(struct vc4_shader_validation_state *validation_state)
 struct vc4_validated_shader_info *
 vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
 {
+	struct vc4_dev *vc4 = to_vc4_dev(shader_obj->base.dev);
 	bool found_shader_end = false;
 	int shader_end_ip = 0;
 	uint32_t last_thread_switch_ip = -3;
@@ -785,6 +786,9 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
 	struct vc4_validated_shader_info *validated_shader = NULL;
 	struct vc4_shader_validation_state validation_state;
 
+	if (WARN_ON_ONCE(vc4->is_vc5))
+		return NULL;
+
 	memset(&validation_state, 0, sizeof(validation_state));
 	validation_state.shader = shader_obj->vaddr;
 	validation_state.max_ip = shader_obj->base.size / sizeof(uint64_t);
-- 
GitLab


From eb2983c09f4e053f2c3362763f5e1073b5e4cd7d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jouni=20H=C3=B6gander?= <jouni.hogander@intel.com>
Date: Fri, 10 Jun 2022 11:54:27 +0300
Subject: [PATCH 0663/1731] drm/i915/opregion: add function to check if
 headless sku
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Export headless sku bit (bit 13) from opregion->header->pcon as an
interface to check if our device is headless configuration.

This is mainly targeted for hybrid gfx systems. E.g. when display
is not supposed to be connected discrete graphics card it's
opregion can inform this is headless graphics card.

v3: Dummy version is now static inline function
v2: Check also opregion version

Bspec: 53441
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220610085429.52935-2-jouni.hogander@intel.com
---
 drivers/gpu/drm/i915/display/intel_opregion.c | 14 ++++++++++++++
 drivers/gpu/drm/i915/display/intel_opregion.h |  7 +++++++
 2 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index f31e8c3f8ce0e..6876ba30d5a9e 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -53,6 +53,8 @@
 #define MBOX_ASLE_EXT		BIT(4)	/* Mailbox #5 */
 #define MBOX_BACKLIGHT		BIT(5)	/* Mailbox #2 (valid from v3.x) */
 
+#define PCON_HEADLESS_SKU	BIT(13)
+
 struct opregion_header {
 	u8 signature[16];
 	u32 size;
@@ -1135,6 +1137,18 @@ struct edid *intel_opregion_get_edid(struct intel_connector *intel_connector)
 	return new_edid;
 }
 
+bool intel_opregion_headless_sku(struct drm_i915_private *i915)
+{
+	struct intel_opregion *opregion = &i915->opregion;
+	struct opregion_header *header = opregion->header;
+
+	if (!header || header->over.major < 2 ||
+	    (header->over.major == 2 && header->over.minor < 3))
+		return false;
+
+	return opregion->header->pcon & PCON_HEADLESS_SKU;
+}
+
 void intel_opregion_register(struct drm_i915_private *i915)
 {
 	struct intel_opregion *opregion = &i915->opregion;
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h b/drivers/gpu/drm/i915/display/intel_opregion.h
index 82cc0ba34af7e..2f261f9854008 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.h
+++ b/drivers/gpu/drm/i915/display/intel_opregion.h
@@ -76,6 +76,8 @@ int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
 int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
 struct edid *intel_opregion_get_edid(struct intel_connector *connector);
 
+bool intel_opregion_headless_sku(struct drm_i915_private *i915);
+
 #else /* CONFIG_ACPI*/
 
 static inline int intel_opregion_setup(struct drm_i915_private *dev_priv)
@@ -127,6 +129,11 @@ intel_opregion_get_edid(struct intel_connector *connector)
 	return NULL;
 }
 
+static inline bool intel_opregion_headless_sku(struct drm_i915_private *i915)
+{
+	return false;
+}
+
 #endif /* CONFIG_ACPI */
 
 #endif
-- 
GitLab


From 04770b082e2a207804c633fbfd5efec28cbc5673 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jouni=20H=C3=B6gander?= <jouni.hogander@intel.com>
Date: Fri, 10 Jun 2022 11:54:28 +0300
Subject: [PATCH 0664/1731] drm/i915: Do not start connector polling if display
 is disabled
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Currently we are starting connector polling if display is disabled
using disable_display module parameter. Polling is just returning
always "not connected" state. This can be optimized by not starting
polling at all.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220610085429.52935-3-jouni.hogander@intel.com
---
 drivers/gpu/drm/i915/display/intel_hotplug.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 8204126d17f9c..5f8b4f481cff9 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -668,7 +668,8 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
  */
 void intel_hpd_poll_enable(struct drm_i915_private *dev_priv)
 {
-	if (!HAS_DISPLAY(dev_priv))
+	if (!HAS_DISPLAY(dev_priv) ||
+	    !INTEL_DISPLAY_ENABLED(dev_priv))
 		return;
 
 	WRITE_ONCE(dev_priv->hotplug.poll_enabled, true);
-- 
GitLab


From d6346ae0779ef9a41562f5357ac28aa6a69b1c81 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jouni=20H=C3=B6gander?= <jouni.hogander@intel.com>
Date: Fri, 10 Jun 2022 11:54:29 +0300
Subject: [PATCH 0665/1731] drm/i915: Do not start connector polling on
 headless sku
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Connector polling is waking up the polled device. Polling
is unnecessary if our device is known to not have display.

Fix this and save some power by disabling starting connector
polling when we are having headless sku. Use information from
opregion.

v2: Move headless sku check into INTEL_DISPLAY_ENABLED macro

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220610085429.52935-4-jouni.hogander@intel.com
---
 drivers/gpu/drm/i915/i915_drv.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4ac8d636ecc99..2f6910050aa2c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1302,7 +1302,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 /* Only valid when HAS_DISPLAY() is true */
 #define INTEL_DISPLAY_ENABLED(dev_priv) \
-	(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
+	(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),		\
+	 !(dev_priv)->params.disable_display &&				\
+	 !intel_opregion_headless_sku(dev_priv))
 
 #define HAS_GUC_DEPRIVILEGE(dev_priv) \
 	(INTEL_INFO(dev_priv)->has_guc_deprivilege)
-- 
GitLab


From a76c0b31eef50fdb8b21d53a6d050f59241fb88e Mon Sep 17 00:00:00 2001
From: Jens Axboe <axboe@kernel.dk>
Date: Wed, 15 Jun 2022 19:51:11 -0600
Subject: [PATCH 0666/1731] io_uring: commit non-pollable provided mapped
 buffers upfront

For recv/recvmsg, IO either completes immediately or gets queued for a
retry. This isn't the case for read/readv, if eg a normal file or a block
device is used. Here, an operation can get queued with the block layer.
If this happens, ring mapped buffers must get committed immediately to
avoid that the next read can consume the same buffer.

Check if we're dealing with pollable file, when getting a new ring mapped
provided buffer. If it's not, commit it immediately rather than wait post
issue. If we don't wait, we can race with completions coming in, or just
plain buffer reuse by committing after a retry where others could have
grabbed the same buffer.

Fixes: c7fb19428d67 ("io_uring: add support for ring mapped supplied buffers")
Reviewed-by: Hao Xu <howeyxu@tencent.com>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index 5d479428d8e52..b6e75f69c6b1e 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -3836,7 +3836,7 @@ static void __user *io_ring_buffer_select(struct io_kiocb *req, size_t *len,
 	req->buf_list = bl;
 	req->buf_index = buf->bid;
 
-	if (issue_flags & IO_URING_F_UNLOCKED) {
+	if (issue_flags & IO_URING_F_UNLOCKED || !file_can_poll(req->file)) {
 		/*
 		 * If we came in unlocked, we have no choice but to consume the
 		 * buffer here. This does mean it'll be pinned until the IO
-- 
GitLab


From b8fec4400923eb91f995d7dbe97411b8991ea559 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Wed, 15 Jun 2022 20:48:50 +0300
Subject: [PATCH 0667/1731] drm/i915: Extract
 intel_sanitize_fifo_underrun_reporting()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Pull the underrun status sanitation into its own helper.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220615174851.20658-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 65 +++++++++++---------
 1 file changed, 37 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f1d7cce261a6a..3fac545414b45 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9897,11 +9897,46 @@ static struct intel_connector *intel_encoder_find_connector(struct intel_encoder
 	return NULL;
 }
 
+static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+	if (!crtc_state->hw.active && !HAS_GMCH(i915))
+		return;
+
+	/*
+	 * We start out with underrun reporting disabled to avoid races.
+	 * For correct bookkeeping mark this on active crtcs.
+	 *
+	 * Also on gmch platforms we dont have any hardware bits to
+	 * disable the underrun reporting. Which means we need to start
+	 * out with underrun reporting disabled also on inactive pipes,
+	 * since otherwise we'll complain about the garbage we read when
+	 * e.g. coming up after runtime pm.
+	 *
+	 * No protection against concurrent access is required - at
+	 * worst a fifo underrun happens which also sets this to false.
+	 */
+	crtc->cpu_fifo_underrun_disabled = true;
+
+	/*
+	 * We track the PCH trancoder underrun reporting state
+	 * within the crtc. With crtc for pipe A housing the underrun
+	 * reporting state for PCH transcoder A, crtc for pipe B housing
+	 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
+	 * and marking underrun reporting as disabled for the non-existing
+	 * PCH transcoders B and C would prevent enabling the south
+	 * error interrupt (see cpt_can_enable_serr_int()).
+	 */
+	if (intel_has_pch_trancoder(i915, crtc->pipe))
+		crtc->pch_fifo_underrun_disabled = true;
+}
+
 static void intel_sanitize_crtc(struct intel_crtc *crtc,
 				struct drm_modeset_acquire_ctx *ctx)
 {
 	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
 
 	if (crtc_state->hw.active) {
@@ -9928,33 +9963,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
 	    !intel_crtc_is_bigjoiner_slave(crtc_state))
 		intel_crtc_disable_noatomic(crtc, ctx);
 
-	if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
-		/*
-		 * We start out with underrun reporting disabled to avoid races.
-		 * For correct bookkeeping mark this on active crtcs.
-		 *
-		 * Also on gmch platforms we dont have any hardware bits to
-		 * disable the underrun reporting. Which means we need to start
-		 * out with underrun reporting disabled also on inactive pipes,
-		 * since otherwise we'll complain about the garbage we read when
-		 * e.g. coming up after runtime pm.
-		 *
-		 * No protection against concurrent access is required - at
-		 * worst a fifo underrun happens which also sets this to false.
-		 */
-		crtc->cpu_fifo_underrun_disabled = true;
-		/*
-		 * We track the PCH trancoder underrun reporting state
-		 * within the crtc. With crtc for pipe A housing the underrun
-		 * reporting state for PCH transcoder A, crtc for pipe B housing
-		 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
-		 * and marking underrun reporting as disabled for the non-existing
-		 * PCH transcoders B and C would prevent enabling the south
-		 * error interrupt (see cpt_can_enable_serr_int()).
-		 */
-		if (intel_has_pch_trancoder(dev_priv, crtc->pipe))
-			crtc->pch_fifo_underrun_disabled = true;
-	}
+	intel_sanitize_fifo_underrun_reporting(crtc_state);
 }
 
 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
-- 
GitLab


From 651d4a0fc4c5c6a2d20c95ef814f0d4381f71d55 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Wed, 15 Jun 2022 20:48:51 +0300
Subject: [PATCH 0668/1731] drm/i915: Sanitize underrun reporting before
 turning off any pipes
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Make sure FIFO underrun reporting is flagged as disabled very
early during the state readout so that we don't get any
spurious FIFO underruns reports from intel_crtc_disable_noatomic().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220615174851.20658-2-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3fac545414b45..88658090ac583 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9962,8 +9962,6 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
 	if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&
 	    !intel_crtc_is_bigjoiner_slave(crtc_state))
 		intel_crtc_disable_noatomic(crtc, ctx);
-
-	intel_sanitize_fifo_underrun_reporting(crtc_state);
 }
 
 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
@@ -10363,6 +10361,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
 		struct intel_crtc_state *crtc_state =
 			to_intel_crtc_state(crtc->base.state);
 
+		intel_sanitize_fifo_underrun_reporting(crtc_state);
+
 		drm_crtc_vblank_reset(&crtc->base);
 
 		if (crtc_state->hw.active)
-- 
GitLab


From bf9719f8c89addcf1947ce2b29cea29ea9d8f875 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Thu, 16 Jun 2022 12:55:30 +0300
Subject: [PATCH 0669/1731] drm/i915: Remove bogus LPT iCLKIP WARN
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The WARN shouldn't have been added yet. For the moment the
clock that gets passed here is just what the user has requested
(via the modeline) and may not be exactly what iCLKIP can
generate.

Later on the plan is to change things so that we already get
passed the exact clock here, at which point the WARN should
be reintroduced.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6246
Fixes: 97708335b04d ("drm/i915: Introduce struct iclkip_params")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220616095530.15024-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_pch_refclk.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index 752dab11667f4..9934c8a9e240f 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -179,7 +179,6 @@ void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
 	lpt_disable_iclkip(dev_priv);
 
 	lpt_compute_iclkip(&p, clock);
-	drm_WARN_ON(&dev_priv->drm, lpt_iclkip_freq(&p) != clock);
 
 	/* This should not happen with any sane values */
 	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(p.divsel) &
-- 
GitLab


From 0256ea13d169e9ef00ef1b1c9df395b1d6bad6f6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Wed, 15 Jun 2022 18:14:43 +0300
Subject: [PATCH 0670/1731] drm/i915/bios: Move panel_type stuff out of
 parse_panel_options()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Parsing the panel_type is a bit special and should be done
before we parse anything else potentially panel-specific from
the VBT. So move it out from parse_panel_options(). It doesn't
neet to be there anyway since it'll do its own LVDS options
block lookup.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220615151445.8531-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 64ee418c0c5d5..5ed8cebdd41f8 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -745,11 +745,10 @@ static int get_panel_type(struct drm_i915_private *i915,
 /* Parse general panel options */
 static void
 parse_panel_options(struct drm_i915_private *i915,
-		    struct intel_panel *panel,
-		    const struct edid *edid)
+		    struct intel_panel *panel)
 {
 	const struct bdb_lvds_options *lvds_options;
-	int panel_type;
+	int panel_type = panel->vbt.panel_type;
 	int drrs_mode;
 
 	lvds_options = find_section(i915, BDB_LVDS_OPTIONS);
@@ -758,10 +757,6 @@ parse_panel_options(struct drm_i915_private *i915,
 
 	panel->vbt.lvds_dither = lvds_options->pixel_dither;
 
-	panel_type = get_panel_type(i915, edid);
-
-	panel->vbt.panel_type = panel_type;
-
 	drrs_mode = (lvds_options->dps_panel_type_bits
 				>> (panel_type * 2)) & MODE_MASK;
 	/*
@@ -3116,7 +3111,9 @@ void intel_bios_init_panel(struct drm_i915_private *i915,
 {
 	init_vbt_panel_defaults(panel);
 
-	parse_panel_options(i915, panel, edid);
+	panel->vbt.panel_type = get_panel_type(i915, edid);
+
+	parse_panel_options(i915, panel);
 	parse_generic_dtd(i915, panel);
 	parse_lfp_data(i915, panel);
 	parse_lfp_backlight(i915, panel);
-- 
GitLab


From 5c9016b2ddb375662aff802d25c96f5483a4e024 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Wed, 15 Jun 2022 18:14:44 +0300
Subject: [PATCH 0671/1731] drm/i915/bios: Don't parse the DPS panel type when
 the VBT does not have it
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Older VBTs don't have all the stuff we've defined for the
LVDS options block (40). In particular we're currently parsing
the DPS panel type bits even though they may not exist, which
could mean we end up flagging the machine as supporting static
DRRS when the VBT declared no such thing.

We don't actually have a clear idea which VBT versions have
which bits so we rely on the block size instead.

Here's a quick list from my VBT stash:
mgm version 108 -> 4 bytes
alv version 120 -> 4 bytes
cst version 134 -> 14 bytes
pnv version 144 -> 14 bytes
cl  version 142 -> 16 bytes
ctg version 155 -> 24 bytes

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220615151445.8531-2-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 5ed8cebdd41f8..f37058fa525ce 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -757,6 +757,14 @@ parse_panel_options(struct drm_i915_private *i915,
 
 	panel->vbt.lvds_dither = lvds_options->pixel_dither;
 
+	/*
+	 * Empirical evidence indicates the block size can be
+	 * either 4,14,16,24+ bytes. For older VBTs no clear
+	 * relationship between the block size vs. BDB version.
+	 */
+	if (get_blocksize(lvds_options) < 16)
+		return;
+
 	drrs_mode = (lvds_options->dps_panel_type_bits
 				>> (panel_type * 2)) & MODE_MASK;
 	/*
-- 
GitLab


From a50cc4955623685402ed6deeffad7df93591a416 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Wed, 15 Jun 2022 18:14:45 +0300
Subject: [PATCH 0672/1731] drm/i915/bios: Introduce panel_bits() and
 panel_bool()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Abstract the bit extraction from the VBT per-panel bitfields
slightly.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220615151445.8531-3-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 31 +++++++++++++------
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |  3 --
 2 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index f37058fa525ce..82eef3b1ca879 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -742,6 +742,16 @@ static int get_panel_type(struct drm_i915_private *i915,
 	return panel_types[i].panel_type;
 }
 
+static unsigned int panel_bits(unsigned int value, int panel_type, int num_bits)
+{
+	return (value >> (panel_type * num_bits)) & (BIT(num_bits) - 1);
+}
+
+static bool panel_bool(unsigned int value, int panel_type)
+{
+	return panel_bits(value, panel_type, 1);
+}
+
 /* Parse general panel options */
 static void
 parse_panel_options(struct drm_i915_private *i915,
@@ -765,8 +775,8 @@ parse_panel_options(struct drm_i915_private *i915,
 	if (get_blocksize(lvds_options) < 16)
 		return;
 
-	drrs_mode = (lvds_options->dps_panel_type_bits
-				>> (panel_type * 2)) & MODE_MASK;
+	drrs_mode = panel_bits(lvds_options->dps_panel_type_bits,
+			       panel_type, 2);
 	/*
 	 * VBT has static DRRS = 0 and seamless DRRS = 2.
 	 * The below piece of code is required to adjust vbt.drrs_type
@@ -1312,7 +1322,7 @@ parse_power_conservation_features(struct drm_i915_private *i915,
 	if (!power)
 		return;
 
-	panel->vbt.psr.enable = power->psr & BIT(panel_type);
+	panel->vbt.psr.enable = panel_bool(power->psr, panel_type);
 
 	/*
 	 * If DRRS is not supported, drrs_type has to be set to 0.
@@ -1320,22 +1330,23 @@ parse_power_conservation_features(struct drm_i915_private *i915,
 	 * static DRRS is 0 and DRRS not supported is represented by
 	 * power->drrs & BIT(panel_type)=false
 	 */
-	if (!(power->drrs & BIT(panel_type)) && panel->vbt.drrs_type != DRRS_TYPE_NONE) {
+	if (!panel_bool(power->drrs, panel_type) && panel->vbt.drrs_type != DRRS_TYPE_NONE) {
 		/*
 		 * FIXME Should DMRRS perhaps be treated as seamless
 		 * but without the automatic downclocking?
 		 */
-		if (power->dmrrs & BIT(panel_type))
+		if (panel_bool(power->dmrrs, panel_type))
 			panel->vbt.drrs_type = DRRS_TYPE_STATIC;
 		else
 			panel->vbt.drrs_type = DRRS_TYPE_NONE;
 	}
 
 	if (i915->vbt.version >= 232)
-		panel->vbt.edp.hobl = power->hobl & BIT(panel_type);
+		panel->vbt.edp.hobl = panel_bool(power->hobl, panel_type);
 
 	if (i915->vbt.version >= 233)
-		panel->vbt.vrr = power->vrr_feature_enabled & BIT(panel_type);
+		panel->vbt.vrr = panel_bool(power->vrr_feature_enabled,
+					    panel_type);
 }
 
 static void
@@ -1351,7 +1362,7 @@ parse_edp(struct drm_i915_private *i915,
 	if (!edp)
 		return;
 
-	switch ((edp->color_depth >> (panel_type * 2)) & 3) {
+	switch (panel_bits(edp->color_depth, panel_type, 2)) {
 	case EDP_18BPP:
 		panel->vbt.edp.bpp = 18;
 		break;
@@ -1462,7 +1473,7 @@ parse_edp(struct drm_i915_private *i915,
 	}
 
 	panel->vbt.edp.drrs_msa_timing_delay =
-		(edp->sdrrs_msa_timing_delay >> (panel_type * 2)) & 3;
+		panel_bits(edp->sdrrs_msa_timing_delay, panel_type, 2);
 
 	if (i915->vbt.version >= 244)
 		panel->vbt.edp.max_link_rate =
@@ -1545,7 +1556,7 @@ parse_psr(struct drm_i915_private *i915,
 	if (i915->vbt.version >= 226) {
 		u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
 
-		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
+		wakeup_time = panel_bits(wakeup_time, panel_type, 2);
 		switch (wakeup_time) {
 		case 0:
 			wakeup_time = 500;
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index f8e5097222f2a..3766c09bd65d9 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -704,9 +704,6 @@ struct bdb_edp {
  * Block 40 - LFP Data Block
  */
 
-/* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
-#define MODE_MASK		0x3
-
 struct bdb_lvds_options {
 	u8 panel_type;
 	u8 panel_type2;						/* 212 */
-- 
GitLab


From 4f5bf12732fd78e225fc62b7c5c84d9032f8048a Mon Sep 17 00:00:00 2001
From: Yang Li <yang.lee@linux.alibaba.com>
Date: Thu, 12 May 2022 15:54:32 +0800
Subject: [PATCH 0673/1731] fs: fix jbd2_journal_try_to_free_buffers()
 kernel-doc comment

Add the description of @folio and remove @page in function kernel-doc
comment to remove warnings found by running scripts/kernel-doc, which
is caused by using 'make W=1'.

fs/jbd2/transaction.c:2149: warning: Function parameter or member
'folio' not described in 'jbd2_journal_try_to_free_buffers'
fs/jbd2/transaction.c:2149: warning: Excess function parameter 'page'
description in 'jbd2_journal_try_to_free_buffers'

Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Link: https://lore.kernel.org/r/20220512075432.31763-1-yang.lee@linux.alibaba.com
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
---
 fs/jbd2/transaction.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/jbd2/transaction.c b/fs/jbd2/transaction.c
index e49bb0938376b..e9c308ae475fd 100644
--- a/fs/jbd2/transaction.c
+++ b/fs/jbd2/transaction.c
@@ -2114,7 +2114,7 @@ out:
 /**
  * jbd2_journal_try_to_free_buffers() - try to free page buffers.
  * @journal: journal for operation
- * @page: to try and free
+ * @folio: Folio to detach data from.
  *
  * For all the buffers on this page,
  * if they are fully written out ordered data, move them onto BUF_CLEAN
-- 
GitLab


From 06781a5026350cde699d2d10c9914a25c1524f45 Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: Tue, 14 Jun 2022 10:31:38 +0200
Subject: [PATCH 0674/1731] mtd: rawnand: gpmi: Fix setting busy timeout
 setting

The DEVICE_BUSY_TIMEOUT value is described in the Reference Manual as:

| Timeout waiting for NAND Ready/Busy or ATA IRQ. Used in WAIT_FOR_READY
| mode. This value is the number of GPMI_CLK cycles multiplied by 4096.

So instead of multiplying the value in cycles with 4096, we have to
divide it by that value. Use DIV_ROUND_UP to make sure we are on the
safe side, especially when the calculated value in cycles is smaller
than 4096 as typically the case.

This bug likely never triggered because any timeout != 0 usually will
do. In my case the busy timeout in cycles was originally calculated as
2408, which multiplied with 4096 is 0x968000. The lower 16 bits were
taken for the 16 bit wide register field, so the register value was
0x8000. With 2970bf5a32f0 ("mtd: rawnand: gpmi: fix controller timings
setting") however the value in cycles became 2384, which multiplied
with 4096 is 0x950000. The lower 16 bit are 0x0 now resulting in an
intermediate timeout when reading from NAND.

Fixes: b1206122069aa ("mtd: rawnand: gpmi: use core timings instead of an empirical derivation")
Cc: stable@vger.kernel.org
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20220614083138.3455683-1-s.hauer@pengutronix.de
---
 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
index 0b68d05846e18..889e403299568 100644
--- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
@@ -890,7 +890,7 @@ static int gpmi_nfc_compute_timings(struct gpmi_nand_data *this,
 	hw->timing0 = BF_GPMI_TIMING0_ADDRESS_SETUP(addr_setup_cycles) |
 		      BF_GPMI_TIMING0_DATA_HOLD(data_hold_cycles) |
 		      BF_GPMI_TIMING0_DATA_SETUP(data_setup_cycles);
-	hw->timing1 = BF_GPMI_TIMING1_BUSY_TIMEOUT(busy_timeout_cycles * 4096);
+	hw->timing1 = BF_GPMI_TIMING1_BUSY_TIMEOUT(DIV_ROUND_UP(busy_timeout_cycles, 4096));
 
 	/*
 	 * Derive NFC ideal delay from {3}:
-- 
GitLab


From 48e02e6113825db81e4aacc035933c0d0e4e68ce Mon Sep 17 00:00:00 2001
From: Wang Jianjian <wangjianjian3@huawei.com>
Date: Fri, 20 May 2022 10:22:54 +0800
Subject: [PATCH 0675/1731] ext4: fix incorrect comment in
 ext4_bio_write_page()

Signed-off-by: Wang Jianjian <wangjianjian3@huawei.com>
Link: https://lore.kernel.org/r/20220520022255.2120576-1-wangjianjian3@huawei.com
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
---
 fs/ext4/page-io.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/ext4/page-io.c b/fs/ext4/page-io.c
index 14695e2b5042b..97fa7b4c645fd 100644
--- a/fs/ext4/page-io.c
+++ b/fs/ext4/page-io.c
@@ -465,7 +465,7 @@ int ext4_bio_write_page(struct ext4_io_submit *io,
 	/*
 	 * In the first loop we prepare and mark buffers to submit. We have to
 	 * mark all buffers in the page before submitting so that
-	 * end_page_writeback() cannot be called from ext4_bio_end_io() when IO
+	 * end_page_writeback() cannot be called from ext4_end_bio() when IO
 	 * on the first buffer finishes and we are still working on submitting
 	 * the second buffer.
 	 */
-- 
GitLab


From 3103084afcf2341e12b0ee2c7b2ed570164f44a2 Mon Sep 17 00:00:00 2001
From: Wang Jianjian <wangjianjian3@huawei.com>
Date: Fri, 20 May 2022 10:22:55 +0800
Subject: [PATCH 0676/1731] ext4, doc: remove unnecessary escaping

Signed-off-by: Wang Jianjian <wangjianjian3@huawei.com>
Link: https://lore.kernel.org/r/20220520022255.2120576-2-wangjianjian3@huawei.com
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
---
 Documentation/filesystems/ext4/attributes.rst |  68 +--
 Documentation/filesystems/ext4/bigalloc.rst   |   2 +-
 Documentation/filesystems/ext4/bitmaps.rst    |   6 +-
 Documentation/filesystems/ext4/blockgroup.rst |  30 +-
 Documentation/filesystems/ext4/blockmap.rst   |   2 +-
 Documentation/filesystems/ext4/checksums.rst  |  26 +-
 Documentation/filesystems/ext4/directory.rst  | 166 +++---
 Documentation/filesystems/ext4/eainode.rst    |  10 +-
 .../filesystems/ext4/group_descr.rst          | 126 ++--
 Documentation/filesystems/ext4/ifork.rst      |  60 +-
 Documentation/filesystems/ext4/inlinedata.rst |   8 +-
 Documentation/filesystems/ext4/inodes.rst     | 306 +++++-----
 Documentation/filesystems/ext4/journal.rst    | 214 +++----
 Documentation/filesystems/ext4/mmp.rst        |  36 +-
 Documentation/filesystems/ext4/overview.rst   |   2 +-
 .../filesystems/ext4/special_inodes.rst       |   8 +-
 Documentation/filesystems/ext4/super.rst      | 550 +++++++++---------
 17 files changed, 810 insertions(+), 810 deletions(-)

diff --git a/Documentation/filesystems/ext4/attributes.rst b/Documentation/filesystems/ext4/attributes.rst
index 871d2da7a0a91..87814696a65b5 100644
--- a/Documentation/filesystems/ext4/attributes.rst
+++ b/Documentation/filesystems/ext4/attributes.rst
@@ -13,8 +13,8 @@ disappeared as of Linux 3.0.
 
 There are two places where extended attributes can be found. The first
 place is between the end of each inode entry and the beginning of the
-next inode entry. For example, if inode.i\_extra\_isize = 28 and
-sb.inode\_size = 256, then there are 256 - (128 + 28) = 100 bytes
+next inode entry. For example, if inode.i_extra_isize = 28 and
+sb.inode_size = 256, then there are 256 - (128 + 28) = 100 bytes
 available for in-inode extended attribute storage. The second place
 where extended attributes can be found is in the block pointed to by
 ``inode.i_file_acl``. As of Linux 3.11, it is not possible for this
@@ -38,8 +38,8 @@ Extended attributes, when stored after the inode, have a header
      - Name
      - Description
    * - 0x0
-     - \_\_le32
-     - h\_magic
+     - __le32
+     - h_magic
      - Magic number for identification, 0xEA020000. This value is set by the
        Linux driver, though e2fsprogs doesn't seem to check it(?)
 
@@ -55,28 +55,28 @@ The beginning of an extended attribute block is in
      - Name
      - Description
    * - 0x0
-     - \_\_le32
-     - h\_magic
+     - __le32
+     - h_magic
      - Magic number for identification, 0xEA020000.
    * - 0x4
-     - \_\_le32
-     - h\_refcount
+     - __le32
+     - h_refcount
      - Reference count.
    * - 0x8
-     - \_\_le32
-     - h\_blocks
+     - __le32
+     - h_blocks
      - Number of disk blocks used.
    * - 0xC
-     - \_\_le32
-     - h\_hash
+     - __le32
+     - h_hash
      - Hash value of all attributes.
    * - 0x10
-     - \_\_le32
-     - h\_checksum
+     - __le32
+     - h_checksum
      - Checksum of the extended attribute block.
    * - 0x14
-     - \_\_u32
-     - h\_reserved[3]
+     - __u32
+     - h_reserved[3]
      - Zero.
 
 The checksum is calculated against the FS UUID, the 64-bit block number
@@ -100,46 +100,46 @@ Attributes stored inside an inode do not need be stored in sorted order.
      - Name
      - Description
    * - 0x0
-     - \_\_u8
-     - e\_name\_len
+     - __u8
+     - e_name_len
      - Length of name.
    * - 0x1
-     - \_\_u8
-     - e\_name\_index
+     - __u8
+     - e_name_index
      - Attribute name index. There is a discussion of this below.
    * - 0x2
-     - \_\_le16
-     - e\_value\_offs
+     - __le16
+     - e_value_offs
      - Location of this attribute's value on the disk block where it is stored.
        Multiple attributes can share the same value. For an inode attribute
        this value is relative to the start of the first entry; for a block this
        value is relative to the start of the block (i.e. the header).
    * - 0x4
-     - \_\_le32
-     - e\_value\_inum
+     - __le32
+     - e_value_inum
      - The inode where the value is stored. Zero indicates the value is in the
        same block as this entry. This field is only used if the
-       INCOMPAT\_EA\_INODE feature is enabled.
+       INCOMPAT_EA_INODE feature is enabled.
    * - 0x8
-     - \_\_le32
-     - e\_value\_size
+     - __le32
+     - e_value_size
      - Length of attribute value.
    * - 0xC
-     - \_\_le32
-     - e\_hash
+     - __le32
+     - e_hash
      - Hash value of attribute name and attribute value. The kernel doesn't
        update the hash for in-inode attributes, so for that case this value
        must be zero, because e2fsck validates any non-zero hash regardless of
        where the xattr lives.
    * - 0x10
      - char
-     - e\_name[e\_name\_len]
+     - e_name[e_name_len]
      - Attribute name. Does not include trailing NULL.
 
 Attribute values can follow the end of the entry table. There appears to
 be a requirement that they be aligned to 4-byte boundaries. The values
 are stored starting at the end of the block and grow towards the
-xattr\_header/xattr\_entry table. When the two collide, the overflow is
+xattr_header/xattr_entry table. When the two collide, the overflow is
 put into a separate disk block. If the disk block fills up, the
 filesystem returns -ENOSPC.
 
@@ -167,15 +167,15 @@ the key name. Here is a map of name index values to key prefixes:
    * - 1
      - “user.”
    * - 2
-     - “system.posix\_acl\_access”
+     - “system.posix_acl_access”
    * - 3
-     - “system.posix\_acl\_default”
+     - “system.posix_acl_default”
    * - 4
      - “trusted.”
    * - 6
      - “security.”
    * - 7
-     - “system.” (inline\_data only?)
+     - “system.” (inline_data only?)
    * - 8
      - “system.richacl” (SuSE kernels only?)
 
diff --git a/Documentation/filesystems/ext4/bigalloc.rst b/Documentation/filesystems/ext4/bigalloc.rst
index 72075aa608e4d..976a180b209c2 100644
--- a/Documentation/filesystems/ext4/bigalloc.rst
+++ b/Documentation/filesystems/ext4/bigalloc.rst
@@ -23,7 +23,7 @@ means that a block group addresses 32 gigabytes instead of 128 megabytes,
 also shrinking the amount of file system overhead for metadata.
 
 The administrator can set a block cluster size at mkfs time (which is
-stored in the s\_log\_cluster\_size field in the superblock); from then
+stored in the s_log_cluster_size field in the superblock); from then
 on, the block bitmaps track clusters, not individual blocks. This means
 that block groups can be several gigabytes in size (instead of just
 128MiB); however, the minimum allocation unit becomes a cluster, not a
diff --git a/Documentation/filesystems/ext4/bitmaps.rst b/Documentation/filesystems/ext4/bitmaps.rst
index c7546dbc197ae..91c45d86e9bb5 100644
--- a/Documentation/filesystems/ext4/bitmaps.rst
+++ b/Documentation/filesystems/ext4/bitmaps.rst
@@ -9,15 +9,15 @@ group.
 The inode bitmap records which entries in the inode table are in use.
 
 As with most bitmaps, one bit represents the usage status of one data
-block or inode table entry. This implies a block group size of 8 \*
-number\_of\_bytes\_in\_a\_logical\_block.
+block or inode table entry. This implies a block group size of 8 *
+number_of_bytes_in_a_logical_block.
 
 NOTE: If ``BLOCK_UNINIT`` is set for a given block group, various parts
 of the kernel and e2fsprogs code pretends that the block bitmap contains
 zeros (i.e. all blocks in the group are free). However, it is not
 necessarily the case that no blocks are in use -- if ``meta_bg`` is set,
 the bitmaps and group descriptor live inside the group. Unfortunately,
-ext2fs\_test\_block\_bitmap2() will return '0' for those locations,
+ext2fs_test_block_bitmap2() will return '0' for those locations,
 which produces confusing debugfs output.
 
 Inode Table
diff --git a/Documentation/filesystems/ext4/blockgroup.rst b/Documentation/filesystems/ext4/blockgroup.rst
index d5d652addce5e..46d78f860623f 100644
--- a/Documentation/filesystems/ext4/blockgroup.rst
+++ b/Documentation/filesystems/ext4/blockgroup.rst
@@ -56,39 +56,39 @@ established that the super block and the group descriptor table, if
 present, will be at the beginning of the block group. The bitmaps and
 the inode table can be anywhere, and it is quite possible for the
 bitmaps to come after the inode table, or for both to be in different
-groups (flex\_bg). Leftover space is used for file data blocks, indirect
+groups (flex_bg). Leftover space is used for file data blocks, indirect
 block maps, extent tree blocks, and extended attributes.
 
 Flexible Block Groups
 ---------------------
 
 Starting in ext4, there is a new feature called flexible block groups
-(flex\_bg). In a flex\_bg, several block groups are tied together as one
+(flex_bg). In a flex_bg, several block groups are tied together as one
 logical block group; the bitmap spaces and the inode table space in the
-first block group of the flex\_bg are expanded to include the bitmaps
-and inode tables of all other block groups in the flex\_bg. For example,
-if the flex\_bg size is 4, then group 0 will contain (in order) the
+first block group of the flex_bg are expanded to include the bitmaps
+and inode tables of all other block groups in the flex_bg. For example,
+if the flex_bg size is 4, then group 0 will contain (in order) the
 superblock, group descriptors, data block bitmaps for groups 0-3, inode
 bitmaps for groups 0-3, inode tables for groups 0-3, and the remaining
 space in group 0 is for file data. The effect of this is to group the
 block group metadata close together for faster loading, and to enable
 large files to be continuous on disk. Backup copies of the superblock
 and group descriptors are always at the beginning of block groups, even
-if flex\_bg is enabled. The number of block groups that make up a
-flex\_bg is given by 2 ^ ``sb.s_log_groups_per_flex``.
+if flex_bg is enabled. The number of block groups that make up a
+flex_bg is given by 2 ^ ``sb.s_log_groups_per_flex``.
 
 Meta Block Groups
 -----------------
 
-Without the option META\_BG, for safety concerns, all block group
+Without the option META_BG, for safety concerns, all block group
 descriptors copies are kept in the first block group. Given the default
 128MiB(2^27 bytes) block group size and 64-byte group descriptors, ext4
 can have at most 2^27/64 = 2^21 block groups. This limits the entire
 filesystem size to 2^21 * 2^27 = 2^48bytes or 256TiB.
 
 The solution to this problem is to use the metablock group feature
-(META\_BG), which is already in ext3 for all 2.6 releases. With the
-META\_BG feature, ext4 filesystems are partitioned into many metablock
+(META_BG), which is already in ext3 for all 2.6 releases. With the
+META_BG feature, ext4 filesystems are partitioned into many metablock
 groups. Each metablock group is a cluster of block groups whose group
 descriptor structures can be stored in a single disk block. For ext4
 filesystems with 4 KB block size, a single metablock group partition
@@ -110,7 +110,7 @@ bytes, a meta-block group contains 32 block groups for filesystems with
 a 1KB block size, and 128 block groups for filesystems with a 4KB
 blocksize. Filesystems can either be created using this new block group
 descriptor layout, or existing filesystems can be resized on-line, and
-the field s\_first\_meta\_bg in the superblock will indicate the first
+the field s_first_meta_bg in the superblock will indicate the first
 block group using this new layout.
 
 Please see an important note about ``BLOCK_UNINIT`` in the section about
@@ -121,15 +121,15 @@ Lazy Block Group Initialization
 
 A new feature for ext4 are three block group descriptor flags that
 enable mkfs to skip initializing other parts of the block group
-metadata. Specifically, the INODE\_UNINIT and BLOCK\_UNINIT flags mean
+metadata. Specifically, the INODE_UNINIT and BLOCK_UNINIT flags mean
 that the inode and block bitmaps for that group can be calculated and
 therefore the on-disk bitmap blocks are not initialized. This is
 generally the case for an empty block group or a block group containing
-only fixed-location block group metadata. The INODE\_ZEROED flag means
+only fixed-location block group metadata. The INODE_ZEROED flag means
 that the inode table has been initialized; mkfs will unset this flag and
 rely on the kernel to initialize the inode tables in the background.
 
 By not writing zeroes to the bitmaps and inode table, mkfs time is
-reduced considerably. Note the feature flag is RO\_COMPAT\_GDT\_CSUM,
-but the dumpe2fs output prints this as “uninit\_bg”. They are the same
+reduced considerably. Note the feature flag is RO_COMPAT_GDT_CSUM,
+but the dumpe2fs output prints this as “uninit_bg”. They are the same
 thing.
diff --git a/Documentation/filesystems/ext4/blockmap.rst b/Documentation/filesystems/ext4/blockmap.rst
index 30e25750d88a4..2bd990402a5c4 100644
--- a/Documentation/filesystems/ext4/blockmap.rst
+++ b/Documentation/filesystems/ext4/blockmap.rst
@@ -1,7 +1,7 @@
 .. SPDX-License-Identifier: GPL-2.0
 
 +---------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-| i.i\_block Offset   | Where It Points                                                                                                                                                                                                              |
+| i.i_block Offset   | Where It Points                                                                                                                                                                                                              |
 +=====================+==============================================================================================================================================================================================================================+
 | 0 to 11             | Direct map to file blocks 0 to 11.                                                                                                                                                                                           |
 +---------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
diff --git a/Documentation/filesystems/ext4/checksums.rst b/Documentation/filesystems/ext4/checksums.rst
index 5519e253810d6..e232749daf5f3 100644
--- a/Documentation/filesystems/ext4/checksums.rst
+++ b/Documentation/filesystems/ext4/checksums.rst
@@ -4,7 +4,7 @@ Checksums
 ---------
 
 Starting in early 2012, metadata checksums were added to all major ext4
-and jbd2 data structures. The associated feature flag is metadata\_csum.
+and jbd2 data structures. The associated feature flag is metadata_csum.
 The desired checksum algorithm is indicated in the superblock, though as
 of October 2012 the only supported algorithm is crc32c. Some data
 structures did not have space to fit a full 32-bit checksum, so only the
@@ -20,7 +20,7 @@ encounters directory blocks that lack sufficient empty space to add a
 checksum, it will request that you run ``e2fsck -D`` to have the
 directories rebuilt with checksums. This has the added benefit of
 removing slack space from the directory files and rebalancing the htree
-indexes. If you \_ignore\_ this step, your directories will not be
+indexes. If you _ignore_ this step, your directories will not be
 protected by a checksum!
 
 The following table describes the data elements that go into each type
@@ -35,39 +35,39 @@ of checksum. The checksum function is whatever the superblock describes
      - Length
      - Ingredients
    * - Superblock
-     - \_\_le32
+     - __le32
      - The entire superblock up to the checksum field. The UUID lives inside
        the superblock.
    * - MMP
-     - \_\_le32
+     - __le32
      - UUID + the entire MMP block up to the checksum field.
    * - Extended Attributes
-     - \_\_le32
+     - __le32
      - UUID + the entire extended attribute block. The checksum field is set to
        zero.
    * - Directory Entries
-     - \_\_le32
+     - __le32
      - UUID + inode number + inode generation + the directory block up to the
        fake entry enclosing the checksum field.
    * - HTREE Nodes
-     - \_\_le32
+     - __le32
      - UUID + inode number + inode generation + all valid extents + HTREE tail.
        The checksum field is set to zero.
    * - Extents
-     - \_\_le32
+     - __le32
      - UUID + inode number + inode generation + the entire extent block up to
        the checksum field.
    * - Bitmaps
-     - \_\_le32 or \_\_le16
+     - __le32 or __le16
      - UUID + the entire bitmap. Checksums are stored in the group descriptor,
        and truncated if the group descriptor size is 32 bytes (i.e. ^64bit)
    * - Inodes
-     - \_\_le32
+     - __le32
      - UUID + inode number + inode generation + the entire inode. The checksum
        field is set to zero. Each inode has its own checksum.
    * - Group Descriptors
-     - \_\_le16
-     - If metadata\_csum, then UUID + group number + the entire descriptor;
-       else if gdt\_csum, then crc16(UUID + group number + the entire
+     - __le16
+     - If metadata_csum, then UUID + group number + the entire descriptor;
+       else if gdt_csum, then crc16(UUID + group number + the entire
        descriptor). In all cases, only the lower 16 bits are stored.
 
diff --git a/Documentation/filesystems/ext4/directory.rst b/Documentation/filesystems/ext4/directory.rst
index 55f618b371445..6eece8e31df8b 100644
--- a/Documentation/filesystems/ext4/directory.rst
+++ b/Documentation/filesystems/ext4/directory.rst
@@ -42,24 +42,24 @@ is at most 263 bytes long, though on disk you'll need to reference
      - Name
      - Description
    * - 0x0
-     - \_\_le32
+     - __le32
      - inode
      - Number of the inode that this directory entry points to.
    * - 0x4
-     - \_\_le16
-     - rec\_len
+     - __le16
+     - rec_len
      - Length of this directory entry. Must be a multiple of 4.
    * - 0x6
-     - \_\_le16
-     - name\_len
+     - __le16
+     - name_len
      - Length of the file name.
    * - 0x8
      - char
-     - name[EXT4\_NAME\_LEN]
+     - name[EXT4_NAME_LEN]
      - File name.
 
 Since file names cannot be longer than 255 bytes, the new directory
-entry format shortens the name\_len field and uses the space for a file
+entry format shortens the name_len field and uses the space for a file
 type flag, probably to avoid having to load every inode during directory
 tree traversal. This format is ``ext4_dir_entry_2``, which is at most
 263 bytes long, though on disk you'll need to reference
@@ -74,24 +74,24 @@ tree traversal. This format is ``ext4_dir_entry_2``, which is at most
      - Name
      - Description
    * - 0x0
-     - \_\_le32
+     - __le32
      - inode
      - Number of the inode that this directory entry points to.
    * - 0x4
-     - \_\_le16
-     - rec\_len
+     - __le16
+     - rec_len
      - Length of this directory entry.
    * - 0x6
-     - \_\_u8
-     - name\_len
+     - __u8
+     - name_len
      - Length of the file name.
    * - 0x7
-     - \_\_u8
-     - file\_type
+     - __u8
+     - file_type
      - File type code, see ftype_ table below.
    * - 0x8
      - char
-     - name[EXT4\_NAME\_LEN]
+     - name[EXT4_NAME_LEN]
      - File name.
 
 .. _ftype:
@@ -137,19 +137,19 @@ entry uses this extension, it may be up to 271 bytes.
      - Name
      - Description
    * - 0x0
-     - \_\_le32
+     - __le32
      - hash
      - The hash of the directory name
    * - 0x4
-     - \_\_le32
-     - minor\_hash
+     - __le32
+     - minor_hash
      - The minor hash of the directory name
 
 
 In order to add checksums to these classic directory blocks, a phony
 ``struct ext4_dir_entry`` is placed at the end of each leaf block to
 hold the checksum. The directory entry is 12 bytes long. The inode
-number and name\_len fields are set to zero to fool old software into
+number and name_len fields are set to zero to fool old software into
 ignoring an apparently empty directory entry, and the checksum is stored
 in the place where the name normally goes. The structure is
 ``struct ext4_dir_entry_tail``:
@@ -163,24 +163,24 @@ in the place where the name normally goes. The structure is
      - Name
      - Description
    * - 0x0
-     - \_\_le32
-     - det\_reserved\_zero1
+     - __le32
+     - det_reserved_zero1
      - Inode number, which must be zero.
    * - 0x4
-     - \_\_le16
-     - det\_rec\_len
+     - __le16
+     - det_rec_len
      - Length of this directory entry, which must be 12.
    * - 0x6
-     - \_\_u8
-     - det\_reserved\_zero2
+     - __u8
+     - det_reserved_zero2
      - Length of the file name, which must be zero.
    * - 0x7
-     - \_\_u8
-     - det\_reserved\_ft
+     - __u8
+     - det_reserved_ft
      - File type, which must be 0xDE.
    * - 0x8
-     - \_\_le32
-     - det\_checksum
+     - __le32
+     - det_checksum
      - Directory leaf block checksum.
 
 The leaf directory block checksum is calculated against the FS UUID, the
@@ -194,7 +194,7 @@ Hash Tree Directories
 A linear array of directory entries isn't great for performance, so a
 new feature was added to ext3 to provide a faster (but peculiar)
 balanced tree keyed off a hash of the directory entry name. If the
-EXT4\_INDEX\_FL (0x1000) flag is set in the inode, this directory uses a
+EXT4_INDEX_FL (0x1000) flag is set in the inode, this directory uses a
 hashed btree (htree) to organize and find directory entries. For
 backwards read-only compatibility with ext2, this tree is actually
 hidden inside the directory file, masquerading as “empty” directory data
@@ -206,14 +206,14 @@ rest of the directory block is empty so that it moves on.
 The root of the tree always lives in the first data block of the
 directory. By ext2 custom, the '.' and '..' entries must appear at the
 beginning of this first block, so they are put here as two
-``struct ext4_dir_entry_2``\ s and not stored in the tree. The rest of
+``struct ext4_dir_entry_2`` s and not stored in the tree. The rest of
 the root node contains metadata about the tree and finally a hash->block
 map to find nodes that are lower in the htree. If
 ``dx_root.info.indirect_levels`` is non-zero then the htree has two
 levels; the data block pointed to by the root node's map is an interior
 node, which is indexed by a minor hash. Interior nodes in this tree
 contains a zeroed out ``struct ext4_dir_entry_2`` followed by a
-minor\_hash->block map to find leafe nodes. Leaf nodes contain a linear
+minor_hash->block map to find leafe nodes. Leaf nodes contain a linear
 array of all ``struct ext4_dir_entry_2``; all of these entries
 (presumably) hash to the same value. If there is an overflow, the
 entries simply overflow into the next leaf node, and the
@@ -245,83 +245,83 @@ of a data block:
      - Name
      - Description
    * - 0x0
-     - \_\_le32
+     - __le32
      - dot.inode
      - inode number of this directory.
    * - 0x4
-     - \_\_le16
-     - dot.rec\_len
+     - __le16
+     - dot.rec_len
      - Length of this record, 12.
    * - 0x6
      - u8
-     - dot.name\_len
+     - dot.name_len
      - Length of the name, 1.
    * - 0x7
      - u8
-     - dot.file\_type
+     - dot.file_type
      - File type of this entry, 0x2 (directory) (if the feature flag is set).
    * - 0x8
      - char
      - dot.name[4]
-     - “.\\0\\0\\0”
+     - “.\0\0\0”
    * - 0xC
-     - \_\_le32
+     - __le32
      - dotdot.inode
      - inode number of parent directory.
    * - 0x10
-     - \_\_le16
-     - dotdot.rec\_len
-     - block\_size - 12. The record length is long enough to cover all htree
+     - __le16
+     - dotdot.rec_len
+     - block_size - 12. The record length is long enough to cover all htree
        data.
    * - 0x12
      - u8
-     - dotdot.name\_len
+     - dotdot.name_len
      - Length of the name, 2.
    * - 0x13
      - u8
-     - dotdot.file\_type
+     - dotdot.file_type
      - File type of this entry, 0x2 (directory) (if the feature flag is set).
    * - 0x14
      - char
-     - dotdot\_name[4]
-     - “..\\0\\0”
+     - dotdot_name[4]
+     - “..\0\0”
    * - 0x18
-     - \_\_le32
-     - struct dx\_root\_info.reserved\_zero
+     - __le32
+     - struct dx_root_info.reserved_zero
      - Zero.
    * - 0x1C
      - u8
-     - struct dx\_root\_info.hash\_version
+     - struct dx_root_info.hash_version
      - Hash type, see dirhash_ table below.
    * - 0x1D
      - u8
-     - struct dx\_root\_info.info\_length
+     - struct dx_root_info.info_length
      - Length of the tree information, 0x8.
    * - 0x1E
      - u8
-     - struct dx\_root\_info.indirect\_levels
-     - Depth of the htree. Cannot be larger than 3 if the INCOMPAT\_LARGEDIR
+     - struct dx_root_info.indirect_levels
+     - Depth of the htree. Cannot be larger than 3 if the INCOMPAT_LARGEDIR
        feature is set; cannot be larger than 2 otherwise.
    * - 0x1F
      - u8
-     - struct dx\_root\_info.unused\_flags
+     - struct dx_root_info.unused_flags
      -
    * - 0x20
-     - \_\_le16
+     - __le16
      - limit
-     - Maximum number of dx\_entries that can follow this header, plus 1 for
+     - Maximum number of dx_entries that can follow this header, plus 1 for
        the header itself.
    * - 0x22
-     - \_\_le16
+     - __le16
      - count
-     - Actual number of dx\_entries that follow this header, plus 1 for the
+     - Actual number of dx_entries that follow this header, plus 1 for the
        header itself.
    * - 0x24
-     - \_\_le32
+     - __le32
      - block
      - The block number (within the directory file) that goes with hash=0.
    * - 0x28
-     - struct dx\_entry
+     - struct dx_entry
      - entries[0]
      - As many 8-byte ``struct dx_entry`` as fits in the rest of the data block.
 
@@ -362,38 +362,38 @@ also the full length of a data block:
      - Name
      - Description
    * - 0x0
-     - \_\_le32
+     - __le32
      - fake.inode
      - Zero, to make it look like this entry is not in use.
    * - 0x4
-     - \_\_le16
-     - fake.rec\_len
-     - The size of the block, in order to hide all of the dx\_node data.
+     - __le16
+     - fake.rec_len
+     - The size of the block, in order to hide all of the dx_node data.
    * - 0x6
      - u8
-     - name\_len
+     - name_len
      - Zero. There is no name for this “unused” directory entry.
    * - 0x7
      - u8
-     - file\_type
+     - file_type
      - Zero. There is no file type for this “unused” directory entry.
    * - 0x8
-     - \_\_le16
+     - __le16
      - limit
-     - Maximum number of dx\_entries that can follow this header, plus 1 for
+     - Maximum number of dx_entries that can follow this header, plus 1 for
        the header itself.
    * - 0xA
-     - \_\_le16
+     - __le16
      - count
-     - Actual number of dx\_entries that follow this header, plus 1 for the
+     - Actual number of dx_entries that follow this header, plus 1 for the
        header itself.
    * - 0xE
-     - \_\_le32
+     - __le32
      - block
      - The block number (within the directory file) that goes with the lowest
        hash value of this block. This value is stored in the parent block.
    * - 0x12
-     - struct dx\_entry
+     - struct dx_entry
      - entries[0]
      - As many 8-byte ``struct dx_entry`` as fits in the rest of the data block.
 
@@ -410,11 +410,11 @@ long:
      - Name
      - Description
    * - 0x0
-     - \_\_le32
+     - __le32
      - hash
      - Hash code.
    * - 0x4
-     - \_\_le32
+     - __le32
      - block
      - Block number (within the directory file, not filesystem blocks) of the
        next node in the htree.
@@ -423,13 +423,13 @@ long:
 author.)
 
 If metadata checksums are enabled, the last 8 bytes of the directory
-block (precisely the length of one dx\_entry) are used to store a
+block (precisely the length of one dx_entry) are used to store a
 ``struct dx_tail``, which contains the checksum. The ``limit`` and
-``count`` entries in the dx\_root/dx\_node structures are adjusted as
-necessary to fit the dx\_tail into the block. If there is no space for
-the dx\_tail, the user is notified to run e2fsck -D to rebuild the
+``count`` entries in the dx_root/dx_node structures are adjusted as
+necessary to fit the dx_tail into the block. If there is no space for
+the dx_tail, the user is notified to run e2fsck -D to rebuild the
 directory index (which will ensure that there's space for the checksum.
-The dx\_tail structure is 8 bytes long and looks like this:
+The dx_tail structure is 8 bytes long and looks like this:
 
 .. list-table::
    :widths: 8 8 24 40
@@ -441,13 +441,13 @@ The dx\_tail structure is 8 bytes long and looks like this:
      - Description
    * - 0x0
      - u32
-     - dt\_reserved
+     - dt_reserved
      - Zero.
    * - 0x4
-     - \_\_le32
-     - dt\_checksum
+     - __le32
+     - dt_checksum
      - Checksum of the htree directory block.
 
 The checksum is calculated against the FS UUID, the htree index header
-(dx\_root or dx\_node), all of the htree indices (dx\_entry) that are in
-use, and the tail block (dx\_tail).
+(dx_root or dx_node), all of the htree indices (dx_entry) that are in
+use, and the tail block (dx_tail).
diff --git a/Documentation/filesystems/ext4/eainode.rst b/Documentation/filesystems/ext4/eainode.rst
index ecc0d01a0a72c..7a2ef26b064ac 100644
--- a/Documentation/filesystems/ext4/eainode.rst
+++ b/Documentation/filesystems/ext4/eainode.rst
@@ -5,14 +5,14 @@ Large Extended Attribute Values
 
 To enable ext4 to store extended attribute values that do not fit in the
 inode or in the single extended attribute block attached to an inode,
-the EA\_INODE feature allows us to store the value in the data blocks of
+the EA_INODE feature allows us to store the value in the data blocks of
 a regular file inode. This “EA inode” is linked only from the extended
 attribute name index and must not appear in a directory entry. The
-inode's i\_atime field is used to store a checksum of the xattr value;
-and i\_ctime/i\_version store a 64-bit reference count, which enables
+inode's i_atime field is used to store a checksum of the xattr value;
+and i_ctime/i_version store a 64-bit reference count, which enables
 sharing of large xattr values between multiple owning inodes. For
 backward compatibility with older versions of this feature, the
-i\_mtime/i\_generation *may* store a back-reference to the inode number
-and i\_generation of the **one** owning inode (in cases where the EA
+i_mtime/i_generation *may* store a back-reference to the inode number
+and i_generation of the **one** owning inode (in cases where the EA
 inode is not referenced by multiple inodes) to verify that the EA inode
 is the correct one being accessed.
diff --git a/Documentation/filesystems/ext4/group_descr.rst b/Documentation/filesystems/ext4/group_descr.rst
index 7ba6114e7f5c2..392ec44f8fb00 100644
--- a/Documentation/filesystems/ext4/group_descr.rst
+++ b/Documentation/filesystems/ext4/group_descr.rst
@@ -7,34 +7,34 @@ Each block group on the filesystem has one of these descriptors
 associated with it. As noted in the Layout section above, the group
 descriptors (if present) are the second item in the block group. The
 standard configuration is for each block group to contain a full copy of
-the block group descriptor table unless the sparse\_super feature flag
+the block group descriptor table unless the sparse_super feature flag
 is set.
 
 Notice how the group descriptor records the location of both bitmaps and
 the inode table (i.e. they can float). This means that within a block
 group, the only data structures with fixed locations are the superblock
-and the group descriptor table. The flex\_bg mechanism uses this
+and the group descriptor table. The flex_bg mechanism uses this
 property to group several block groups into a flex group and lay out all
 of the groups' bitmaps and inode tables into one long run in the first
 group of the flex group.
 
-If the meta\_bg feature flag is set, then several block groups are
-grouped together into a meta group. Note that in the meta\_bg case,
+If the meta_bg feature flag is set, then several block groups are
+grouped together into a meta group. Note that in the meta_bg case,
 however, the first and last two block groups within the larger meta
 group contain only group descriptors for the groups inside the meta
 group.
 
-flex\_bg and meta\_bg do not appear to be mutually exclusive features.
+flex_bg and meta_bg do not appear to be mutually exclusive features.
 
 In ext2, ext3, and ext4 (when the 64bit feature is not enabled), the
 block group descriptor was only 32 bytes long and therefore ends at
-bg\_checksum. On an ext4 filesystem with the 64bit feature enabled, the
+bg_checksum. On an ext4 filesystem with the 64bit feature enabled, the
 block group descriptor expands to at least the 64 bytes described below;
 the size is stored in the superblock.
 
-If gdt\_csum is set and metadata\_csum is not set, the block group
+If gdt_csum is set and metadata_csum is not set, the block group
 checksum is the crc16 of the FS UUID, the group number, and the group
-descriptor structure. If metadata\_csum is set, then the block group
+descriptor structure. If metadata_csum is set, then the block group
 checksum is the lower 16 bits of the checksum of the FS UUID, the group
 number, and the group descriptor structure. Both block and inode bitmap
 checksums are calculated against the FS UUID, the group number, and the
@@ -51,59 +51,59 @@ The block group descriptor is laid out in ``struct ext4_group_desc``.
      - Name
      - Description
    * - 0x0
-     - \_\_le32
-     - bg\_block\_bitmap\_lo
+     - __le32
+     - bg_block_bitmap_lo
      - Lower 32-bits of location of block bitmap.
    * - 0x4
-     - \_\_le32
-     - bg\_inode\_bitmap\_lo
+     - __le32
+     - bg_inode_bitmap_lo
      - Lower 32-bits of location of inode bitmap.
    * - 0x8
-     - \_\_le32
-     - bg\_inode\_table\_lo
+     - __le32
+     - bg_inode_table_lo
      - Lower 32-bits of location of inode table.
    * - 0xC
-     - \_\_le16
-     - bg\_free\_blocks\_count\_lo
+     - __le16
+     - bg_free_blocks_count_lo
      - Lower 16-bits of free block count.
    * - 0xE
-     - \_\_le16
-     - bg\_free\_inodes\_count\_lo
+     - __le16
+     - bg_free_inodes_count_lo
      - Lower 16-bits of free inode count.
    * - 0x10
-     - \_\_le16
-     - bg\_used\_dirs\_count\_lo
+     - __le16
+     - bg_used_dirs_count_lo
      - Lower 16-bits of directory count.
    * - 0x12
-     - \_\_le16
-     - bg\_flags
+     - __le16
+     - bg_flags
      - Block group flags. See the bgflags_ table below.
    * - 0x14
-     - \_\_le32
-     - bg\_exclude\_bitmap\_lo
+     - __le32
+     - bg_exclude_bitmap_lo
      - Lower 32-bits of location of snapshot exclusion bitmap.
    * - 0x18
-     - \_\_le16
-     - bg\_block\_bitmap\_csum\_lo
+     - __le16
+     - bg_block_bitmap_csum_lo
      - Lower 16-bits of the block bitmap checksum.
    * - 0x1A
-     - \_\_le16
-     - bg\_inode\_bitmap\_csum\_lo
+     - __le16
+     - bg_inode_bitmap_csum_lo
      - Lower 16-bits of the inode bitmap checksum.
    * - 0x1C
-     - \_\_le16
-     - bg\_itable\_unused\_lo
+     - __le16
+     - bg_itable_unused_lo
      - Lower 16-bits of unused inode count. If set, we needn't scan past the
-       ``(sb.s_inodes_per_group - gdt.bg_itable_unused)``\ th entry in the
+       ``(sb.s_inodes_per_group - gdt.bg_itable_unused)`` th entry in the
        inode table for this group.
    * - 0x1E
-     - \_\_le16
-     - bg\_checksum
-     - Group descriptor checksum; crc16(sb\_uuid+group\_num+bg\_desc) if the
-       RO\_COMPAT\_GDT\_CSUM feature is set, or
-       crc32c(sb\_uuid+group\_num+bg\_desc) & 0xFFFF if the
-       RO\_COMPAT\_METADATA\_CSUM feature is set.  The bg\_checksum
-       field in bg\_desc is skipped when calculating crc16 checksum,
+     - __le16
+     - bg_checksum
+     - Group descriptor checksum; crc16(sb_uuid+group_num+bg_desc) if the
+       RO_COMPAT_GDT_CSUM feature is set, or
+       crc32c(sb_uuid+group_num+bg_desc) & 0xFFFF if the
+       RO_COMPAT_METADATA_CSUM feature is set.  The bg_checksum
+       field in bg_desc is skipped when calculating crc16 checksum,
        and set to zero if crc32c checksum is used.
    * -
      -
@@ -111,48 +111,48 @@ The block group descriptor is laid out in ``struct ext4_group_desc``.
      - These fields only exist if the 64bit feature is enabled and s_desc_size
        > 32.
    * - 0x20
-     - \_\_le32
-     - bg\_block\_bitmap\_hi
+     - __le32
+     - bg_block_bitmap_hi
      - Upper 32-bits of location of block bitmap.
    * - 0x24
-     - \_\_le32
-     - bg\_inode\_bitmap\_hi
+     - __le32
+     - bg_inode_bitmap_hi
      - Upper 32-bits of location of inodes bitmap.
    * - 0x28
-     - \_\_le32
-     - bg\_inode\_table\_hi
+     - __le32
+     - bg_inode_table_hi
      - Upper 32-bits of location of inodes table.
    * - 0x2C
-     - \_\_le16
-     - bg\_free\_blocks\_count\_hi
+     - __le16
+     - bg_free_blocks_count_hi
      - Upper 16-bits of free block count.
    * - 0x2E
-     - \_\_le16
-     - bg\_free\_inodes\_count\_hi
+     - __le16
+     - bg_free_inodes_count_hi
      - Upper 16-bits of free inode count.
    * - 0x30
-     - \_\_le16
-     - bg\_used\_dirs\_count\_hi
+     - __le16
+     - bg_used_dirs_count_hi
      - Upper 16-bits of directory count.
    * - 0x32
-     - \_\_le16
-     - bg\_itable\_unused\_hi
+     - __le16
+     - bg_itable_unused_hi
      - Upper 16-bits of unused inode count.
    * - 0x34
-     - \_\_le32
-     - bg\_exclude\_bitmap\_hi
+     - __le32
+     - bg_exclude_bitmap_hi
      - Upper 32-bits of location of snapshot exclusion bitmap.
    * - 0x38
-     - \_\_le16
-     - bg\_block\_bitmap\_csum\_hi
+     - __le16
+     - bg_block_bitmap_csum_hi
      - Upper 16-bits of the block bitmap checksum.
    * - 0x3A
-     - \_\_le16
-     - bg\_inode\_bitmap\_csum\_hi
+     - __le16
+     - bg_inode_bitmap_csum_hi
      - Upper 16-bits of the inode bitmap checksum.
    * - 0x3C
-     - \_\_u32
-     - bg\_reserved
+     - __u32
+     - bg_reserved
      - Padding to 64 bytes.
 
 .. _bgflags:
@@ -166,8 +166,8 @@ Block group flags can be any combination of the following:
    * - Value
      - Description
    * - 0x1
-     - inode table and bitmap are not initialized (EXT4\_BG\_INODE\_UNINIT).
+     - inode table and bitmap are not initialized (EXT4_BG_INODE_UNINIT).
    * - 0x2
-     - block bitmap is not initialized (EXT4\_BG\_BLOCK\_UNINIT).
+     - block bitmap is not initialized (EXT4_BG_BLOCK_UNINIT).
    * - 0x4
-     - inode table is zeroed (EXT4\_BG\_INODE\_ZEROED).
+     - inode table is zeroed (EXT4_BG_INODE_ZEROED).
diff --git a/Documentation/filesystems/ext4/ifork.rst b/Documentation/filesystems/ext4/ifork.rst
index b9816d5a896b7..dc31f505e6c83 100644
--- a/Documentation/filesystems/ext4/ifork.rst
+++ b/Documentation/filesystems/ext4/ifork.rst
@@ -1,6 +1,6 @@
 .. SPDX-License-Identifier: GPL-2.0
 
-The Contents of inode.i\_block
+The Contents of inode.i_block
 ------------------------------
 
 Depending on the type of file an inode describes, the 60 bytes of
@@ -47,7 +47,7 @@ In ext4, the file to logical block map has been replaced with an extent
 tree. Under the old scheme, allocating a contiguous run of 1,000 blocks
 requires an indirect block to map all 1,000 entries; with extents, the
 mapping is reduced to a single ``struct ext4_extent`` with
-``ee_len = 1000``. If flex\_bg is enabled, it is possible to allocate
+``ee_len = 1000``. If flex_bg is enabled, it is possible to allocate
 very large files with a single extent, at a considerable reduction in
 metadata block use, and some improvement in disk efficiency. The inode
 must have the extents flag (0x80000) flag set for this feature to be in
@@ -76,28 +76,28 @@ which is 12 bytes long:
      - Name
      - Description
    * - 0x0
-     - \_\_le16
-     - eh\_magic
+     - __le16
+     - eh_magic
      - Magic number, 0xF30A.
    * - 0x2
-     - \_\_le16
-     - eh\_entries
+     - __le16
+     - eh_entries
      - Number of valid entries following the header.
    * - 0x4
-     - \_\_le16
-     - eh\_max
+     - __le16
+     - eh_max
      - Maximum number of entries that could follow the header.
    * - 0x6
-     - \_\_le16
-     - eh\_depth
+     - __le16
+     - eh_depth
      - Depth of this extent node in the extent tree. 0 = this extent node
        points to data blocks; otherwise, this extent node points to other
        extent nodes. The extent tree can be at most 5 levels deep: a logical
        block number can be at most ``2^32``, and the smallest ``n`` that
        satisfies ``4*(((blocksize - 12)/12)^n) >= 2^32`` is 5.
    * - 0x8
-     - \_\_le32
-     - eh\_generation
+     - __le32
+     - eh_generation
      - Generation of the tree. (Used by Lustre, but not standard ext4).
 
 Internal nodes of the extent tree, also known as index nodes, are
@@ -112,22 +112,22 @@ recorded as ``struct ext4_extent_idx``, and are 12 bytes long:
      - Name
      - Description
    * - 0x0
-     - \_\_le32
-     - ei\_block
+     - __le32
+     - ei_block
      - This index node covers file blocks from 'block' onward.
    * - 0x4
-     - \_\_le32
-     - ei\_leaf\_lo
+     - __le32
+     - ei_leaf_lo
      - Lower 32-bits of the block number of the extent node that is the next
        level lower in the tree. The tree node pointed to can be either another
        internal node or a leaf node, described below.
    * - 0x8
-     - \_\_le16
-     - ei\_leaf\_hi
+     - __le16
+     - ei_leaf_hi
      - Upper 16-bits of the previous field.
    * - 0xA
-     - \_\_u16
-     - ei\_unused
+     - __u16
+     - ei_unused
      -
 
 Leaf nodes of the extent tree are recorded as ``struct ext4_extent``,
@@ -142,24 +142,24 @@ and are also 12 bytes long:
      - Name
      - Description
    * - 0x0
-     - \_\_le32
-     - ee\_block
+     - __le32
+     - ee_block
      - First file block number that this extent covers.
    * - 0x4
-     - \_\_le16
-     - ee\_len
+     - __le16
+     - ee_len
      - Number of blocks covered by extent. If the value of this field is <=
        32768, the extent is initialized. If the value of the field is > 32768,
        the extent is uninitialized and the actual extent length is ``ee_len`` -
        32768. Therefore, the maximum length of a initialized extent is 32768
        blocks, and the maximum length of an uninitialized extent is 32767.
    * - 0x6
-     - \_\_le16
-     - ee\_start\_hi
+     - __le16
+     - ee_start_hi
      - Upper 16-bits of the block number to which this extent points.
    * - 0x8
-     - \_\_le32
-     - ee\_start\_lo
+     - __le32
+     - ee_start_lo
      - Lower 32-bits of the block number to which this extent points.
 
 Prior to the introduction of metadata checksums, the extent header +
@@ -182,8 +182,8 @@ including) the checksum itself.
      - Name
      - Description
    * - 0x0
-     - \_\_le32
-     - eb\_checksum
+     - __le32
+     - eb_checksum
      - Checksum of the extent block, crc32c(uuid+inum+igeneration+extentblock)
 
 Inline Data
diff --git a/Documentation/filesystems/ext4/inlinedata.rst b/Documentation/filesystems/ext4/inlinedata.rst
index d1075178ce0b2..a728af0d2fd0c 100644
--- a/Documentation/filesystems/ext4/inlinedata.rst
+++ b/Documentation/filesystems/ext4/inlinedata.rst
@@ -11,12 +11,12 @@ file is smaller than 60 bytes, then the data are stored inline in
 attribute space, then it might be found as an extended attribute
 “system.data” within the inode body (“ibody EA”). This of course
 constrains the amount of extended attributes one can attach to an inode.
-If the data size increases beyond i\_block + ibody EA, a regular block
+If the data size increases beyond i_block + ibody EA, a regular block
 is allocated and the contents moved to that block.
 
 Pending a change to compact the extended attribute key used to store
 inline data, one ought to be able to store 160 bytes of data in a
-256-byte inode (as of June 2015, when i\_extra\_isize is 28). Prior to
+256-byte inode (as of June 2015, when i_extra_isize is 28). Prior to
 that, the limit was 156 bytes due to inefficient use of inode space.
 
 The inline data feature requires the presence of an extended attribute
@@ -25,12 +25,12 @@ for “system.data”, even if the attribute value is zero length.
 Inline Directories
 ~~~~~~~~~~~~~~~~~~
 
-The first four bytes of i\_block are the inode number of the parent
+The first four bytes of i_block are the inode number of the parent
 directory. Following that is a 56-byte space for an array of directory
 entries; see ``struct ext4_dir_entry``. If there is a “system.data”
 attribute in the inode body, the EA value is an array of
 ``struct ext4_dir_entry`` as well. Note that for inline directories, the
-i\_block and EA space are treated as separate dirent blocks; directory
+i_block and EA space are treated as separate dirent blocks; directory
 entries cannot span the two.
 
 Inline directory entries are not checksummed, as the inode checksum
diff --git a/Documentation/filesystems/ext4/inodes.rst b/Documentation/filesystems/ext4/inodes.rst
index 6c5ce666e63f3..cfc6c16599312 100644
--- a/Documentation/filesystems/ext4/inodes.rst
+++ b/Documentation/filesystems/ext4/inodes.rst
@@ -38,138 +38,138 @@ The inode table entry is laid out in ``struct ext4_inode``.
      - Name
      - Description
    * - 0x0
-     - \_\_le16
-     - i\_mode
+     - __le16
+     - i_mode
      - File mode. See the table i_mode_ below.
    * - 0x2
-     - \_\_le16
-     - i\_uid
+     - __le16
+     - i_uid
      - Lower 16-bits of Owner UID.
    * - 0x4
-     - \_\_le32
-     - i\_size\_lo
+     - __le32
+     - i_size_lo
      - Lower 32-bits of size in bytes.
    * - 0x8
-     - \_\_le32
-     - i\_atime
-     - Last access time, in seconds since the epoch. However, if the EA\_INODE
+     - __le32
+     - i_atime
+     - Last access time, in seconds since the epoch. However, if the EA_INODE
        inode flag is set, this inode stores an extended attribute value and
        this field contains the checksum of the value.
    * - 0xC
-     - \_\_le32
-     - i\_ctime
+     - __le32
+     - i_ctime
      - Last inode change time, in seconds since the epoch. However, if the
-       EA\_INODE inode flag is set, this inode stores an extended attribute
+       EA_INODE inode flag is set, this inode stores an extended attribute
        value and this field contains the lower 32 bits of the attribute value's
        reference count.
    * - 0x10
-     - \_\_le32
-     - i\_mtime
+     - __le32
+     - i_mtime
      - Last data modification time, in seconds since the epoch. However, if the
-       EA\_INODE inode flag is set, this inode stores an extended attribute
+       EA_INODE inode flag is set, this inode stores an extended attribute
        value and this field contains the number of the inode that owns the
        extended attribute.
    * - 0x14
-     - \_\_le32
-     - i\_dtime
+     - __le32
+     - i_dtime
      - Deletion Time, in seconds since the epoch.
    * - 0x18
-     - \_\_le16
-     - i\_gid
+     - __le16
+     - i_gid
      - Lower 16-bits of GID.
    * - 0x1A
-     - \_\_le16
-     - i\_links\_count
+     - __le16
+     - i_links_count
      - Hard link count. Normally, ext4 does not permit an inode to have more
        than 65,000 hard links. This applies to files as well as directories,
        which means that there cannot be more than 64,998 subdirectories in a
        directory (each subdirectory's '..' entry counts as a hard link, as does
-       the '.' entry in the directory itself). With the DIR\_NLINK feature
+       the '.' entry in the directory itself). With the DIR_NLINK feature
        enabled, ext4 supports more than 64,998 subdirectories by setting this
        field to 1 to indicate that the number of hard links is not known.
    * - 0x1C
-     - \_\_le32
-     - i\_blocks\_lo
-     - Lower 32-bits of “block” count. If the huge\_file feature flag is not
+     - __le32
+     - i_blocks_lo
+     - Lower 32-bits of “block” count. If the huge_file feature flag is not
        set on the filesystem, the file consumes ``i_blocks_lo`` 512-byte blocks
-       on disk. If huge\_file is set and EXT4\_HUGE\_FILE\_FL is NOT set in
+       on disk. If huge_file is set and EXT4_HUGE_FILE_FL is NOT set in
        ``inode.i_flags``, then the file consumes ``i_blocks_lo + (i_blocks_hi
-       << 32)`` 512-byte blocks on disk. If huge\_file is set and
-       EXT4\_HUGE\_FILE\_FL IS set in ``inode.i_flags``, then this file
+       << 32)`` 512-byte blocks on disk. If huge_file is set and
+       EXT4_HUGE_FILE_FL IS set in ``inode.i_flags``, then this file
        consumes (``i_blocks_lo + i_blocks_hi`` << 32) filesystem blocks on
        disk.
    * - 0x20
-     - \_\_le32
-     - i\_flags
+     - __le32
+     - i_flags
      - Inode flags. See the table i_flags_ below.
    * - 0x24
      - 4 bytes
-     - i\_osd1
+     - i_osd1
      - See the table i_osd1_ for more details.
    * - 0x28
      - 60 bytes
-     - i\_block[EXT4\_N\_BLOCKS=15]
-     - Block map or extent tree. See the section “The Contents of inode.i\_block”.
+     - i_block[EXT4_N_BLOCKS=15]
+     - Block map or extent tree. See the section “The Contents of inode.i_block”.
    * - 0x64
-     - \_\_le32
-     - i\_generation
+     - __le32
+     - i_generation
      - File version (for NFS).
    * - 0x68
-     - \_\_le32
-     - i\_file\_acl\_lo
+     - __le32
+     - i_file_acl_lo
      - Lower 32-bits of extended attribute block. ACLs are of course one of
        many possible extended attributes; I think the name of this field is a
        result of the first use of extended attributes being for ACLs.
    * - 0x6C
-     - \_\_le32
-     - i\_size\_high / i\_dir\_acl
+     - __le32
+     - i_size_high / i_dir_acl
      - Upper 32-bits of file/directory size. In ext2/3 this field was named
-       i\_dir\_acl, though it was usually set to zero and never used.
+       i_dir_acl, though it was usually set to zero and never used.
    * - 0x70
-     - \_\_le32
-     - i\_obso\_faddr
+     - __le32
+     - i_obso_faddr
      - (Obsolete) fragment address.
    * - 0x74
      - 12 bytes
-     - i\_osd2
+     - i_osd2
      - See the table i_osd2_ for more details.
    * - 0x80
-     - \_\_le16
-     - i\_extra\_isize
+     - __le16
+     - i_extra_isize
      - Size of this inode - 128. Alternately, the size of the extended inode
        fields beyond the original ext2 inode, including this field.
    * - 0x82
-     - \_\_le16
-     - i\_checksum\_hi
+     - __le16
+     - i_checksum_hi
      - Upper 16-bits of the inode checksum.
    * - 0x84
-     - \_\_le32
-     - i\_ctime\_extra
+     - __le32
+     - i_ctime_extra
      - Extra change time bits. This provides sub-second precision. See Inode
        Timestamps section.
    * - 0x88
-     - \_\_le32
-     - i\_mtime\_extra
+     - __le32
+     - i_mtime_extra
      - Extra modification time bits. This provides sub-second precision.
    * - 0x8C
-     - \_\_le32
-     - i\_atime\_extra
+     - __le32
+     - i_atime_extra
      - Extra access time bits. This provides sub-second precision.
    * - 0x90
-     - \_\_le32
-     - i\_crtime
+     - __le32
+     - i_crtime
      - File creation time, in seconds since the epoch.
    * - 0x94
-     - \_\_le32
-     - i\_crtime\_extra
+     - __le32
+     - i_crtime_extra
      - Extra file creation time bits. This provides sub-second precision.
    * - 0x98
-     - \_\_le32
-     - i\_version\_hi
+     - __le32
+     - i_version_hi
      - Upper 32-bits for version number.
    * - 0x9C
-     - \_\_le32
-     - i\_projid
+     - __le32
+     - i_projid
      - Project ID.
 
 .. _i_mode:
@@ -183,45 +183,45 @@ The ``i_mode`` value is a combination of the following flags:
    * - Value
      - Description
    * - 0x1
-     - S\_IXOTH (Others may execute)
+     - S_IXOTH (Others may execute)
    * - 0x2
-     - S\_IWOTH (Others may write)
+     - S_IWOTH (Others may write)
    * - 0x4
-     - S\_IROTH (Others may read)
+     - S_IROTH (Others may read)
    * - 0x8
-     - S\_IXGRP (Group members may execute)
+     - S_IXGRP (Group members may execute)
    * - 0x10
-     - S\_IWGRP (Group members may write)
+     - S_IWGRP (Group members may write)
    * - 0x20
-     - S\_IRGRP (Group members may read)
+     - S_IRGRP (Group members may read)
    * - 0x40
-     - S\_IXUSR (Owner may execute)
+     - S_IXUSR (Owner may execute)
    * - 0x80
-     - S\_IWUSR (Owner may write)
+     - S_IWUSR (Owner may write)
    * - 0x100
-     - S\_IRUSR (Owner may read)
+     - S_IRUSR (Owner may read)
    * - 0x200
-     - S\_ISVTX (Sticky bit)
+     - S_ISVTX (Sticky bit)
    * - 0x400
-     - S\_ISGID (Set GID)
+     - S_ISGID (Set GID)
    * - 0x800
-     - S\_ISUID (Set UID)
+     - S_ISUID (Set UID)
    * -
      - These are mutually-exclusive file types:
    * - 0x1000
-     - S\_IFIFO (FIFO)
+     - S_IFIFO (FIFO)
    * - 0x2000
-     - S\_IFCHR (Character device)
+     - S_IFCHR (Character device)
    * - 0x4000
-     - S\_IFDIR (Directory)
+     - S_IFDIR (Directory)
    * - 0x6000
-     - S\_IFBLK (Block device)
+     - S_IFBLK (Block device)
    * - 0x8000
-     - S\_IFREG (Regular file)
+     - S_IFREG (Regular file)
    * - 0xA000
-     - S\_IFLNK (Symbolic link)
+     - S_IFLNK (Symbolic link)
    * - 0xC000
-     - S\_IFSOCK (Socket)
+     - S_IFSOCK (Socket)
 
 .. _i_flags:
 
@@ -234,56 +234,56 @@ The ``i_flags`` field is a combination of these values:
    * - Value
      - Description
    * - 0x1
-     - This file requires secure deletion (EXT4\_SECRM\_FL). (not implemented)
+     - This file requires secure deletion (EXT4_SECRM_FL). (not implemented)
    * - 0x2
      - This file should be preserved, should undeletion be desired
-       (EXT4\_UNRM\_FL). (not implemented)
+       (EXT4_UNRM_FL). (not implemented)
    * - 0x4
-     - File is compressed (EXT4\_COMPR\_FL). (not really implemented)
+     - File is compressed (EXT4_COMPR_FL). (not really implemented)
    * - 0x8
-     - All writes to the file must be synchronous (EXT4\_SYNC\_FL).
+     - All writes to the file must be synchronous (EXT4_SYNC_FL).
    * - 0x10
-     - File is immutable (EXT4\_IMMUTABLE\_FL).
+     - File is immutable (EXT4_IMMUTABLE_FL).
    * - 0x20
-     - File can only be appended (EXT4\_APPEND\_FL).
+     - File can only be appended (EXT4_APPEND_FL).
    * - 0x40
-     - The dump(1) utility should not dump this file (EXT4\_NODUMP\_FL).
+     - The dump(1) utility should not dump this file (EXT4_NODUMP_FL).
    * - 0x80
-     - Do not update access time (EXT4\_NOATIME\_FL).
+     - Do not update access time (EXT4_NOATIME_FL).
    * - 0x100
-     - Dirty compressed file (EXT4\_DIRTY\_FL). (not used)
+     - Dirty compressed file (EXT4_DIRTY_FL). (not used)
    * - 0x200
-     - File has one or more compressed clusters (EXT4\_COMPRBLK\_FL). (not used)
+     - File has one or more compressed clusters (EXT4_COMPRBLK_FL). (not used)
    * - 0x400
-     - Do not compress file (EXT4\_NOCOMPR\_FL). (not used)
+     - Do not compress file (EXT4_NOCOMPR_FL). (not used)
    * - 0x800
-     - Encrypted inode (EXT4\_ENCRYPT\_FL). This bit value previously was
-       EXT4\_ECOMPR\_FL (compression error), which was never used.
+     - Encrypted inode (EXT4_ENCRYPT_FL). This bit value previously was
+       EXT4_ECOMPR_FL (compression error), which was never used.
    * - 0x1000
-     - Directory has hashed indexes (EXT4\_INDEX\_FL).
+     - Directory has hashed indexes (EXT4_INDEX_FL).
    * - 0x2000
-     - AFS magic directory (EXT4\_IMAGIC\_FL).
+     - AFS magic directory (EXT4_IMAGIC_FL).
    * - 0x4000
      - File data must always be written through the journal
-       (EXT4\_JOURNAL\_DATA\_FL).
+       (EXT4_JOURNAL_DATA_FL).
    * - 0x8000
-     - File tail should not be merged (EXT4\_NOTAIL\_FL). (not used by ext4)
+     - File tail should not be merged (EXT4_NOTAIL_FL). (not used by ext4)
    * - 0x10000
      - All directory entry data should be written synchronously (see
-       ``dirsync``) (EXT4\_DIRSYNC\_FL).
+       ``dirsync``) (EXT4_DIRSYNC_FL).
    * - 0x20000
-     - Top of directory hierarchy (EXT4\_TOPDIR\_FL).
+     - Top of directory hierarchy (EXT4_TOPDIR_FL).
    * - 0x40000
-     - This is a huge file (EXT4\_HUGE\_FILE\_FL).
+     - This is a huge file (EXT4_HUGE_FILE_FL).
    * - 0x80000
-     - Inode uses extents (EXT4\_EXTENTS\_FL).
+     - Inode uses extents (EXT4_EXTENTS_FL).
    * - 0x100000
-     - Verity protected file (EXT4\_VERITY\_FL).
+     - Verity protected file (EXT4_VERITY_FL).
    * - 0x200000
      - Inode stores a large extended attribute value in its data blocks
-       (EXT4\_EA\_INODE\_FL).
+       (EXT4_EA_INODE_FL).
    * - 0x400000
-     - This file has blocks allocated past EOF (EXT4\_EOFBLOCKS\_FL).
+     - This file has blocks allocated past EOF (EXT4_EOFBLOCKS_FL).
        (deprecated)
    * - 0x01000000
      - Inode is a snapshot (``EXT4_SNAPFILE_FL``). (not in mainline)
@@ -294,21 +294,21 @@ The ``i_flags`` field is a combination of these values:
      - Snapshot shrink has completed (``EXT4_SNAPFILE_SHRUNK_FL``). (not in
        mainline)
    * - 0x10000000
-     - Inode has inline data (EXT4\_INLINE\_DATA\_FL).
+     - Inode has inline data (EXT4_INLINE_DATA_FL).
    * - 0x20000000
-     - Create children with the same project ID (EXT4\_PROJINHERIT\_FL).
+     - Create children with the same project ID (EXT4_PROJINHERIT_FL).
    * - 0x80000000
-     - Reserved for ext4 library (EXT4\_RESERVED\_FL).
+     - Reserved for ext4 library (EXT4_RESERVED_FL).
    * -
      - Aggregate flags:
    * - 0x705BDFFF
      - User-visible flags.
    * - 0x604BC0FF
-     - User-modifiable flags. Note that while EXT4\_JOURNAL\_DATA\_FL and
-       EXT4\_EXTENTS\_FL can be set with setattr, they are not in the kernel's
-       EXT4\_FL\_USER\_MODIFIABLE mask, since it needs to handle the setting of
+     - User-modifiable flags. Note that while EXT4_JOURNAL_DATA_FL and
+       EXT4_EXTENTS_FL can be set with setattr, they are not in the kernel's
+       EXT4_FL_USER_MODIFIABLE mask, since it needs to handle the setting of
        these flags in a special manner and they are masked out of the set of
-       flags that are saved directly to i\_flags.
+       flags that are saved directly to i_flags.
 
 .. _i_osd1:
 
@@ -325,9 +325,9 @@ Linux:
      - Name
      - Description
    * - 0x0
-     - \_\_le32
-     - l\_i\_version
-     - Inode version. However, if the EA\_INODE inode flag is set, this inode
+     - __le32
+     - l_i_version
+     - Inode version. However, if the EA_INODE inode flag is set, this inode
        stores an extended attribute value and this field contains the upper 32
        bits of the attribute value's reference count.
 
@@ -342,8 +342,8 @@ Hurd:
      - Name
      - Description
    * - 0x0
-     - \_\_le32
-     - h\_i\_translator
+     - __le32
+     - h_i_translator
      - ??
 
 Masix:
@@ -357,8 +357,8 @@ Masix:
      - Name
      - Description
    * - 0x0
-     - \_\_le32
-     - m\_i\_reserved
+     - __le32
+     - m_i_reserved
      - ??
 
 .. _i_osd2:
@@ -376,30 +376,30 @@ Linux:
      - Name
      - Description
    * - 0x0
-     - \_\_le16
-     - l\_i\_blocks\_high
+     - __le16
+     - l_i_blocks_high
      - Upper 16-bits of the block count. Please see the note attached to
-       i\_blocks\_lo.
+       i_blocks_lo.
    * - 0x2
-     - \_\_le16
-     - l\_i\_file\_acl\_high
+     - __le16
+     - l_i_file_acl_high
      - Upper 16-bits of the extended attribute block (historically, the file
        ACL location). See the Extended Attributes section below.
    * - 0x4
-     - \_\_le16
-     - l\_i\_uid\_high
+     - __le16
+     - l_i_uid_high
      - Upper 16-bits of the Owner UID.
    * - 0x6
-     - \_\_le16
-     - l\_i\_gid\_high
+     - __le16
+     - l_i_gid_high
      - Upper 16-bits of the GID.
    * - 0x8
-     - \_\_le16
-     - l\_i\_checksum\_lo
+     - __le16
+     - l_i_checksum_lo
      - Lower 16-bits of the inode checksum.
    * - 0xA
-     - \_\_le16
-     - l\_i\_reserved
+     - __le16
+     - l_i_reserved
      - Unused.
 
 Hurd:
@@ -413,24 +413,24 @@ Hurd:
      - Name
      - Description
    * - 0x0
-     - \_\_le16
-     - h\_i\_reserved1
+     - __le16
+     - h_i_reserved1
      - ??
    * - 0x2
-     - \_\_u16
-     - h\_i\_mode\_high
+     - __u16
+     - h_i_mode_high
      - Upper 16-bits of the file mode.
    * - 0x4
-     - \_\_le16
-     - h\_i\_uid\_high
+     - __le16
+     - h_i_uid_high
      - Upper 16-bits of the Owner UID.
    * - 0x6
-     - \_\_le16
-     - h\_i\_gid\_high
+     - __le16
+     - h_i_gid_high
      - Upper 16-bits of the GID.
    * - 0x8
-     - \_\_u32
-     - h\_i\_author
+     - __u32
+     - h_i_author
      - Author code?
 
 Masix:
@@ -444,17 +444,17 @@ Masix:
      - Name
      - Description
    * - 0x0
-     - \_\_le16
-     - h\_i\_reserved1
+     - __le16
+     - h_i_reserved1
      - ??
    * - 0x2
-     - \_\_u16
-     - m\_i\_file\_acl\_high
+     - __u16
+     - m_i_file_acl_high
      - Upper 16-bits of the extended attribute block (historically, the file
        ACL location).
    * - 0x4
-     - \_\_u32
-     - m\_i\_reserved2[2]
+     - __u32
+     - m_i_reserved2[2]
      - ??
 
 Inode Size
@@ -466,11 +466,11 @@ In ext2 and ext3, the inode structure size was fixed at 128 bytes
 on-disk inode at format time for all inodes in the filesystem to provide
 space beyond the end of the original ext2 inode. The on-disk inode
 record size is recorded in the superblock as ``s_inode_size``. The
-number of bytes actually used by struct ext4\_inode beyond the original
+number of bytes actually used by struct ext4_inode beyond the original
 128-byte ext2 inode is recorded in the ``i_extra_isize`` field for each
-inode, which allows struct ext4\_inode to grow for a new kernel without
+inode, which allows struct ext4_inode to grow for a new kernel without
 having to upgrade all of the on-disk inodes. Access to fields beyond
-EXT2\_GOOD\_OLD\_INODE\_SIZE should be verified to be within
+EXT2_GOOD_OLD_INODE_SIZE should be verified to be within
 ``i_extra_isize``. By default, ext4 inode records are 256 bytes, and (as
 of August 2019) the inode structure is 160 bytes
 (``i_extra_isize = 32``). The extra space between the end of the inode
@@ -516,7 +516,7 @@ creation time (crtime); this field is 64-bits wide and decoded in the
 same manner as 64-bit [cma]time. Neither crtime nor dtime are accessible
 through the regular stat() interface, though debugfs will report them.
 
-We use the 32-bit signed time value plus (2^32 \* (extra epoch bits)).
+We use the 32-bit signed time value plus (2^32 * (extra epoch bits)).
 In other words:
 
 .. list-table::
@@ -525,8 +525,8 @@ In other words:
 
    * - Extra epoch bits
      - MSB of 32-bit time
-     - Adjustment for signed 32-bit to 64-bit tv\_sec
-     - Decoded 64-bit tv\_sec
+     - Adjustment for signed 32-bit to 64-bit tv_sec
+     - Decoded 64-bit tv_sec
      - valid time range
    * - 0 0
      - 1
diff --git a/Documentation/filesystems/ext4/journal.rst b/Documentation/filesystems/ext4/journal.rst
index 5fad38860f174..a6bef5293a600 100644
--- a/Documentation/filesystems/ext4/journal.rst
+++ b/Documentation/filesystems/ext4/journal.rst
@@ -63,8 +63,8 @@ Generally speaking, the journal has this format:
    :header-rows: 1
 
    * - Superblock
-     - descriptor\_block (data\_blocks or revocation\_block) [more data or
-       revocations] commmit\_block
+     - descriptor_block (data_blocks or revocation_block) [more data or
+       revocations] commmit_block
      - [more transactions...]
    * - 
      - One transaction
@@ -93,8 +93,8 @@ superblock.
    * - 1024 bytes of padding
      - ext4 Superblock
      - Journal Superblock
-     - descriptor\_block (data\_blocks or revocation\_block) [more data or
-       revocations] commmit\_block
+     - descriptor_block (data_blocks or revocation_block) [more data or
+       revocations] commmit_block
      - [more transactions...]
    * - 
      -
@@ -117,17 +117,17 @@ Every block in the journal starts with a common 12-byte header
      - Name
      - Description
    * - 0x0
-     - \_\_be32
-     - h\_magic
+     - __be32
+     - h_magic
      - jbd2 magic number, 0xC03B3998.
    * - 0x4
-     - \_\_be32
-     - h\_blocktype
+     - __be32
+     - h_blocktype
      - Description of what this block contains. See the jbd2_blocktype_ table
        below.
    * - 0x8
-     - \_\_be32
-     - h\_sequence
+     - __be32
+     - h_sequence
      - The transaction ID that goes with this block.
 
 .. _jbd2_blocktype:
@@ -177,99 +177,99 @@ which is 1024 bytes long:
      -
      - Static information describing the journal.
    * - 0x0
-     - journal\_header\_t (12 bytes)
-     - s\_header
+     - journal_header_t (12 bytes)
+     - s_header
      - Common header identifying this as a superblock.
    * - 0xC
-     - \_\_be32
-     - s\_blocksize
+     - __be32
+     - s_blocksize
      - Journal device block size.
    * - 0x10
-     - \_\_be32
-     - s\_maxlen
+     - __be32
+     - s_maxlen
      - Total number of blocks in this journal.
    * - 0x14
-     - \_\_be32
-     - s\_first
+     - __be32
+     - s_first
      - First block of log information.
    * -
      -
      -
      - Dynamic information describing the current state of the log.
    * - 0x18
-     - \_\_be32
-     - s\_sequence
+     - __be32
+     - s_sequence
      - First commit ID expected in log.
    * - 0x1C
-     - \_\_be32
-     - s\_start
+     - __be32
+     - s_start
      - Block number of the start of log. Contrary to the comments, this field
        being zero does not imply that the journal is clean!
    * - 0x20
-     - \_\_be32
-     - s\_errno
-     - Error value, as set by jbd2\_journal\_abort().
+     - __be32
+     - s_errno
+     - Error value, as set by jbd2_journal_abort().
    * -
      -
      -
      - The remaining fields are only valid in a v2 superblock.
    * - 0x24
-     - \_\_be32
-     - s\_feature\_compat;
+     - __be32
+     - s_feature_compat;
      - Compatible feature set. See the table jbd2_compat_ below.
    * - 0x28
-     - \_\_be32
-     - s\_feature\_incompat
+     - __be32
+     - s_feature_incompat
      - Incompatible feature set. See the table jbd2_incompat_ below.
    * - 0x2C
-     - \_\_be32
-     - s\_feature\_ro\_compat
+     - __be32
+     - s_feature_ro_compat
      - Read-only compatible feature set. There aren't any of these currently.
    * - 0x30
-     - \_\_u8
-     - s\_uuid[16]
+     - __u8
+     - s_uuid[16]
      - 128-bit uuid for journal. This is compared against the copy in the ext4
        super block at mount time.
    * - 0x40
-     - \_\_be32
-     - s\_nr\_users
+     - __be32
+     - s_nr_users
      - Number of file systems sharing this journal.
    * - 0x44
-     - \_\_be32
-     - s\_dynsuper
+     - __be32
+     - s_dynsuper
      - Location of dynamic super block copy. (Not used?)
    * - 0x48
-     - \_\_be32
-     - s\_max\_transaction
+     - __be32
+     - s_max_transaction
      - Limit of journal blocks per transaction. (Not used?)
    * - 0x4C
-     - \_\_be32
-     - s\_max\_trans\_data
+     - __be32
+     - s_max_trans_data
      - Limit of data blocks per transaction. (Not used?)
    * - 0x50
-     - \_\_u8
-     - s\_checksum\_type
+     - __u8
+     - s_checksum_type
      - Checksum algorithm used for the journal.  See jbd2_checksum_type_ for
        more info.
    * - 0x51
-     - \_\_u8[3]
-     - s\_padding2
+     - __u8[3]
+     - s_padding2
      -
    * - 0x54
-     - \_\_be32
-     - s\_num\_fc\_blocks
+     - __be32
+     - s_num_fc_blocks
      - Number of fast commit blocks in the journal.
    * - 0x58
-     - \_\_u32
-     - s\_padding[42]
+     - __u32
+     - s_padding[42]
      -
    * - 0xFC
-     - \_\_be32
-     - s\_checksum
+     - __be32
+     - s_checksum
      - Checksum of the entire superblock, with this field set to zero.
    * - 0x100
-     - \_\_u8
-     - s\_users[16\*48]
+     - __u8
+     - s_users[16*48]
      - ids of all file systems sharing the log. e2fsprogs/Linux don't allow
        shared external journals, but I imagine Lustre (or ocfs2?), which use
        the jbd2 code, might.
@@ -286,7 +286,7 @@ The journal compat features are any combination of the following:
      - Description
    * - 0x1
      - Journal maintains checksums on the data blocks.
-       (JBD2\_FEATURE\_COMPAT\_CHECKSUM)
+       (JBD2_FEATURE_COMPAT_CHECKSUM)
 
 .. _jbd2_incompat:
 
@@ -299,23 +299,23 @@ The journal incompat features are any combination of the following:
    * - Value
      - Description
    * - 0x1
-     - Journal has block revocation records. (JBD2\_FEATURE\_INCOMPAT\_REVOKE)
+     - Journal has block revocation records. (JBD2_FEATURE_INCOMPAT_REVOKE)
    * - 0x2
      - Journal can deal with 64-bit block numbers.
-       (JBD2\_FEATURE\_INCOMPAT\_64BIT)
+       (JBD2_FEATURE_INCOMPAT_64BIT)
    * - 0x4
-     - Journal commits asynchronously. (JBD2\_FEATURE\_INCOMPAT\_ASYNC\_COMMIT)
+     - Journal commits asynchronously. (JBD2_FEATURE_INCOMPAT_ASYNC_COMMIT)
    * - 0x8
      - This journal uses v2 of the checksum on-disk format. Each journal
        metadata block gets its own checksum, and the block tags in the
        descriptor table contain checksums for each of the data blocks in the
-       journal. (JBD2\_FEATURE\_INCOMPAT\_CSUM\_V2)
+       journal. (JBD2_FEATURE_INCOMPAT_CSUM_V2)
    * - 0x10
      - This journal uses v3 of the checksum on-disk format. This is the same as
        v2, but the journal block tag size is fixed regardless of the size of
-       block numbers. (JBD2\_FEATURE\_INCOMPAT\_CSUM\_V3)
+       block numbers. (JBD2_FEATURE_INCOMPAT_CSUM_V3)
    * - 0x20
-     - Journal has fast commit blocks. (JBD2\_FEATURE\_INCOMPAT\_FAST\_COMMIT)
+     - Journal has fast commit blocks. (JBD2_FEATURE_INCOMPAT_FAST_COMMIT)
 
 .. _jbd2_checksum_type:
 
@@ -355,11 +355,11 @@ Descriptor blocks consume at least 36 bytes, but use a full block:
      - Name
      - Descriptor
    * - 0x0
-     - journal\_header\_t
+     - journal_header_t
      - (open coded)
      - Common block header.
    * - 0xC
-     - struct journal\_block\_tag\_s
+     - struct journal_block_tag_s
      - open coded array[]
      - Enough tags either to fill up the block or to describe all the data
        blocks that follow this descriptor block.
@@ -367,7 +367,7 @@ Descriptor blocks consume at least 36 bytes, but use a full block:
 Journal block tags have any of the following formats, depending on which
 journal feature and block tag flags are set.
 
-If JBD2\_FEATURE\_INCOMPAT\_CSUM\_V3 is set, the journal block tag is
+If JBD2_FEATURE_INCOMPAT_CSUM_V3 is set, the journal block tag is
 defined as ``struct journal_block_tag3_s``, which looks like the
 following. The size is 16 or 32 bytes.
 
@@ -380,24 +380,24 @@ following. The size is 16 or 32 bytes.
      - Name
      - Descriptor
    * - 0x0
-     - \_\_be32
-     - t\_blocknr
+     - __be32
+     - t_blocknr
      - Lower 32-bits of the location of where the corresponding data block
        should end up on disk.
    * - 0x4
-     - \_\_be32
-     - t\_flags
+     - __be32
+     - t_flags
      - Flags that go with the descriptor. See the table jbd2_tag_flags_ for
        more info.
    * - 0x8
-     - \_\_be32
-     - t\_blocknr\_high
+     - __be32
+     - t_blocknr_high
      - Upper 32-bits of the location of where the corresponding data block
-       should end up on disk. This is zero if JBD2\_FEATURE\_INCOMPAT\_64BIT is
+       should end up on disk. This is zero if JBD2_FEATURE_INCOMPAT_64BIT is
        not enabled.
    * - 0xC
-     - \_\_be32
-     - t\_checksum
+     - __be32
+     - t_checksum
      - Checksum of the journal UUID, the sequence number, and the data block.
    * -
      -
@@ -433,7 +433,7 @@ The journal tag flags are any combination of the following:
    * - 0x8
      - This is the last tag in this descriptor block.
 
-If JBD2\_FEATURE\_INCOMPAT\_CSUM\_V3 is NOT set, the journal block tag
+If JBD2_FEATURE_INCOMPAT_CSUM_V3 is NOT set, the journal block tag
 is defined as ``struct journal_block_tag_s``, which looks like the
 following. The size is 8, 12, 24, or 28 bytes:
 
@@ -446,18 +446,18 @@ following. The size is 8, 12, 24, or 28 bytes:
      - Name
      - Descriptor
    * - 0x0
-     - \_\_be32
-     - t\_blocknr
+     - __be32
+     - t_blocknr
      - Lower 32-bits of the location of where the corresponding data block
        should end up on disk.
    * - 0x4
-     - \_\_be16
-     - t\_checksum
+     - __be16
+     - t_checksum
      - Checksum of the journal UUID, the sequence number, and the data block.
        Note that only the lower 16 bits are stored.
    * - 0x6
-     - \_\_be16
-     - t\_flags
+     - __be16
+     - t_flags
      - Flags that go with the descriptor. See the table jbd2_tag_flags_ for
        more info.
    * -
@@ -466,8 +466,8 @@ following. The size is 8, 12, 24, or 28 bytes:
      - This next field is only present if the super block indicates support for
        64-bit block numbers.
    * - 0x8
-     - \_\_be32
-     - t\_blocknr\_high
+     - __be32
+     - t_blocknr_high
      - Upper 32-bits of the location of where the corresponding data block
        should end up on disk.
    * -
@@ -483,8 +483,8 @@ following. The size is 8, 12, 24, or 28 bytes:
        ``j_uuid`` field in ``struct journal_s``, but only tune2fs touches that
        field.
 
-If JBD2\_FEATURE\_INCOMPAT\_CSUM\_V2 or
-JBD2\_FEATURE\_INCOMPAT\_CSUM\_V3 are set, the end of the block is a
+If JBD2_FEATURE_INCOMPAT_CSUM_V2 or
+JBD2_FEATURE_INCOMPAT_CSUM_V3 are set, the end of the block is a
 ``struct jbd2_journal_block_tail``, which looks like this:
 
 .. list-table::
@@ -496,8 +496,8 @@ JBD2\_FEATURE\_INCOMPAT\_CSUM\_V3 are set, the end of the block is a
      - Name
      - Descriptor
    * - 0x0
-     - \_\_be32
-     - t\_checksum
+     - __be32
+     - t_checksum
      - Checksum of the journal UUID + the descriptor block, with this field set
        to zero.
 
@@ -538,25 +538,25 @@ length, but use a full block:
      - Name
      - Description
    * - 0x0
-     - journal\_header\_t
-     - r\_header
+     - journal_header_t
+     - r_header
      - Common block header.
    * - 0xC
-     - \_\_be32
-     - r\_count
+     - __be32
+     - r_count
      - Number of bytes used in this block.
    * - 0x10
-     - \_\_be32 or \_\_be64
+     - __be32 or __be64
      - blocks[0]
      - Blocks to revoke.
 
-After r\_count is a linear array of block numbers that are effectively
+After r_count is a linear array of block numbers that are effectively
 revoked by this transaction. The size of each block number is 8 bytes if
 the superblock advertises 64-bit block number support, or 4 bytes
 otherwise.
 
-If JBD2\_FEATURE\_INCOMPAT\_CSUM\_V2 or
-JBD2\_FEATURE\_INCOMPAT\_CSUM\_V3 are set, the end of the revocation
+If JBD2_FEATURE_INCOMPAT_CSUM_V2 or
+JBD2_FEATURE_INCOMPAT_CSUM_V3 are set, the end of the revocation
 block is a ``struct jbd2_journal_revoke_tail``, which has this format:
 
 .. list-table::
@@ -568,8 +568,8 @@ block is a ``struct jbd2_journal_revoke_tail``, which has this format:
      - Name
      - Description
    * - 0x0
-     - \_\_be32
-     - r\_checksum
+     - __be32
+     - r_checksum
      - Checksum of the journal UUID + revocation block
 
 Commit Block
@@ -592,38 +592,38 @@ bytes long (but uses a full block):
      - Name
      - Descriptor
    * - 0x0
-     - journal\_header\_s
+     - journal_header_s
      - (open coded)
      - Common block header.
    * - 0xC
      - unsigned char
-     - h\_chksum\_type
+     - h_chksum_type
      - The type of checksum to use to verify the integrity of the data blocks
        in the transaction. See jbd2_checksum_type_ for more info.
    * - 0xD
      - unsigned char
-     - h\_chksum\_size
+     - h_chksum_size
      - The number of bytes used by the checksum. Most likely 4.
    * - 0xE
      - unsigned char
-     - h\_padding[2]
+     - h_padding[2]
      -
    * - 0x10
-     - \_\_be32
-     - h\_chksum[JBD2\_CHECKSUM\_BYTES]
+     - __be32
+     - h_chksum[JBD2_CHECKSUM_BYTES]
      - 32 bytes of space to store checksums. If
-       JBD2\_FEATURE\_INCOMPAT\_CSUM\_V2 or JBD2\_FEATURE\_INCOMPAT\_CSUM\_V3
+       JBD2_FEATURE_INCOMPAT_CSUM_V2 or JBD2_FEATURE_INCOMPAT_CSUM_V3
        are set, the first ``__be32`` is the checksum of the journal UUID and
        the entire commit block, with this field zeroed. If
-       JBD2\_FEATURE\_COMPAT\_CHECKSUM is set, the first ``__be32`` is the
+       JBD2_FEATURE_COMPAT_CHECKSUM is set, the first ``__be32`` is the
        crc32 of all the blocks already written to the transaction.
    * - 0x30
-     - \_\_be64
-     - h\_commit\_sec
+     - __be64
+     - h_commit_sec
      - The time that the transaction was committed, in seconds since the epoch.
    * - 0x38
-     - \_\_be32
-     - h\_commit\_nsec
+     - __be32
+     - h_commit_nsec
      - Nanoseconds component of the above timestamp.
 
 Fast commits
diff --git a/Documentation/filesystems/ext4/mmp.rst b/Documentation/filesystems/ext4/mmp.rst
index 25660981d93c2..174dd6538737d 100644
--- a/Documentation/filesystems/ext4/mmp.rst
+++ b/Documentation/filesystems/ext4/mmp.rst
@@ -7,8 +7,8 @@ Multiple mount protection (MMP) is a feature that protects the
 filesystem against multiple hosts trying to use the filesystem
 simultaneously. When a filesystem is opened (for mounting, or fsck,
 etc.), the MMP code running on the node (call it node A) checks a
-sequence number. If the sequence number is EXT4\_MMP\_SEQ\_CLEAN, the
-open continues. If the sequence number is EXT4\_MMP\_SEQ\_FSCK, then
+sequence number. If the sequence number is EXT4_MMP_SEQ_CLEAN, the
+open continues. If the sequence number is EXT4_MMP_SEQ_FSCK, then
 fsck is (hopefully) running, and open fails immediately. Otherwise, the
 open code will wait for twice the specified MMP check interval and check
 the sequence number again. If the sequence number has changed, then the
@@ -40,38 +40,38 @@ The MMP structure (``struct mmp_struct``) is as follows:
      - Name
      - Description
    * - 0x0
-     - \_\_le32
-     - mmp\_magic
+     - __le32
+     - mmp_magic
      - Magic number for MMP, 0x004D4D50 (“MMP”).
    * - 0x4
-     - \_\_le32
-     - mmp\_seq
+     - __le32
+     - mmp_seq
      - Sequence number, updated periodically.
    * - 0x8
-     - \_\_le64
-     - mmp\_time
+     - __le64
+     - mmp_time
      - Time that the MMP block was last updated.
    * - 0x10
      - char[64]
-     - mmp\_nodename
+     - mmp_nodename
      - Hostname of the node that opened the filesystem.
    * - 0x50
      - char[32]
-     - mmp\_bdevname
+     - mmp_bdevname
      - Block device name of the filesystem.
    * - 0x70
-     - \_\_le16
-     - mmp\_check\_interval
+     - __le16
+     - mmp_check_interval
      - The MMP re-check interval, in seconds.
    * - 0x72
-     - \_\_le16
-     - mmp\_pad1
+     - __le16
+     - mmp_pad1
      - Zero.
    * - 0x74
-     - \_\_le32[226]
-     - mmp\_pad2
+     - __le32[226]
+     - mmp_pad2
      - Zero.
    * - 0x3FC
-     - \_\_le32
-     - mmp\_checksum
+     - __le32
+     - mmp_checksum
      - Checksum of the MMP block.
diff --git a/Documentation/filesystems/ext4/overview.rst b/Documentation/filesystems/ext4/overview.rst
index 123ebfde47ee1..0fad6eda6e15d 100644
--- a/Documentation/filesystems/ext4/overview.rst
+++ b/Documentation/filesystems/ext4/overview.rst
@@ -7,7 +7,7 @@ An ext4 file system is split into a series of block groups. To reduce
 performance difficulties due to fragmentation, the block allocator tries
 very hard to keep each file's blocks within the same group, thereby
 reducing seek times. The size of a block group is specified in
-``sb.s_blocks_per_group`` blocks, though it can also calculated as 8 \*
+``sb.s_blocks_per_group`` blocks, though it can also calculated as 8 *
 ``block_size_in_bytes``. With the default block size of 4KiB, each group
 will contain 32,768 blocks, for a length of 128MiB. The number of block
 groups is the size of the device divided by the size of a block group.
diff --git a/Documentation/filesystems/ext4/special_inodes.rst b/Documentation/filesystems/ext4/special_inodes.rst
index 94f304e3a0a7b..fc0636901fa0e 100644
--- a/Documentation/filesystems/ext4/special_inodes.rst
+++ b/Documentation/filesystems/ext4/special_inodes.rst
@@ -34,7 +34,7 @@ ext4 reserves some inode for special features, as follows:
    * - 10
      - Replica inode, used for some non-upstream feature?
    * - 11
-     - Traditional first non-reserved inode. Usually this is the lost+found directory. See s\_first\_ino in the superblock.
+     - Traditional first non-reserved inode. Usually this is the lost+found directory. See s_first_ino in the superblock.
 
 Note that there are also some inodes allocated from non-reserved inode numbers
 for other filesystem features which are not referenced from standard directory
@@ -47,9 +47,9 @@ hierarchy. These are generally reference from the superblock. They are:
    * - Superblock field
      - Description
 
-   * - s\_lpf\_ino
+   * - s_lpf_ino
      - Inode number of lost+found directory.
-   * - s\_prj\_quota\_inum
+   * - s_prj_quota_inum
      - Inode number of quota file tracking project quotas
-   * - s\_orphan\_file\_inum
+   * - s_orphan_file_inum
      - Inode number of file tracking orphan inodes.
diff --git a/Documentation/filesystems/ext4/super.rst b/Documentation/filesystems/ext4/super.rst
index f6a548e957bb9..268888522e35c 100644
--- a/Documentation/filesystems/ext4/super.rst
+++ b/Documentation/filesystems/ext4/super.rst
@@ -7,7 +7,7 @@ The superblock records various information about the enclosing
 filesystem, such as block counts, inode counts, supported features,
 maintenance information, and more.
 
-If the sparse\_super feature flag is set, redundant copies of the
+If the sparse_super feature flag is set, redundant copies of the
 superblock and group descriptors are kept only in the groups whose group
 number is either 0 or a power of 3, 5, or 7. If the flag is not set,
 redundant copies are kept in all groups.
@@ -27,107 +27,107 @@ The ext4 superblock is laid out as follows in
      - Name
      - Description
    * - 0x0
-     - \_\_le32
-     - s\_inodes\_count
+     - __le32
+     - s_inodes_count
      - Total inode count.
    * - 0x4
-     - \_\_le32
-     - s\_blocks\_count\_lo
+     - __le32
+     - s_blocks_count_lo
      - Total block count.
    * - 0x8
-     - \_\_le32
-     - s\_r\_blocks\_count\_lo
+     - __le32
+     - s_r_blocks_count_lo
      - This number of blocks can only be allocated by the super-user.
    * - 0xC
-     - \_\_le32
-     - s\_free\_blocks\_count\_lo
+     - __le32
+     - s_free_blocks_count_lo
      - Free block count.
    * - 0x10
-     - \_\_le32
-     - s\_free\_inodes\_count
+     - __le32
+     - s_free_inodes_count
      - Free inode count.
    * - 0x14
-     - \_\_le32
-     - s\_first\_data\_block
+     - __le32
+     - s_first_data_block
      - First data block. This must be at least 1 for 1k-block filesystems and
        is typically 0 for all other block sizes.
    * - 0x18
-     - \_\_le32
-     - s\_log\_block\_size
-     - Block size is 2 ^ (10 + s\_log\_block\_size).
+     - __le32
+     - s_log_block_size
+     - Block size is 2 ^ (10 + s_log_block_size).
    * - 0x1C
-     - \_\_le32
-     - s\_log\_cluster\_size
-     - Cluster size is 2 ^ (10 + s\_log\_cluster\_size) blocks if bigalloc is
-       enabled. Otherwise s\_log\_cluster\_size must equal s\_log\_block\_size.
+     - __le32
+     - s_log_cluster_size
+     - Cluster size is 2 ^ (10 + s_log_cluster_size) blocks if bigalloc is
+       enabled. Otherwise s_log_cluster_size must equal s_log_block_size.
    * - 0x20
-     - \_\_le32
-     - s\_blocks\_per\_group
+     - __le32
+     - s_blocks_per_group
      - Blocks per group.
    * - 0x24
-     - \_\_le32
-     - s\_clusters\_per\_group
+     - __le32
+     - s_clusters_per_group
      - Clusters per group, if bigalloc is enabled. Otherwise
-       s\_clusters\_per\_group must equal s\_blocks\_per\_group.
+       s_clusters_per_group must equal s_blocks_per_group.
    * - 0x28
-     - \_\_le32
-     - s\_inodes\_per\_group
+     - __le32
+     - s_inodes_per_group
      - Inodes per group.
    * - 0x2C
-     - \_\_le32
-     - s\_mtime
+     - __le32
+     - s_mtime
      - Mount time, in seconds since the epoch.
    * - 0x30
-     - \_\_le32
-     - s\_wtime
+     - __le32
+     - s_wtime
      - Write time, in seconds since the epoch.
    * - 0x34
-     - \_\_le16
-     - s\_mnt\_count
+     - __le16
+     - s_mnt_count
      - Number of mounts since the last fsck.
    * - 0x36
-     - \_\_le16
-     - s\_max\_mnt\_count
+     - __le16
+     - s_max_mnt_count
      - Number of mounts beyond which a fsck is needed.
    * - 0x38
-     - \_\_le16
-     - s\_magic
+     - __le16
+     - s_magic
      - Magic signature, 0xEF53
    * - 0x3A
-     - \_\_le16
-     - s\_state
+     - __le16
+     - s_state
      - File system state. See super_state_ for more info.
    * - 0x3C
-     - \_\_le16
-     - s\_errors
+     - __le16
+     - s_errors
      - Behaviour when detecting errors. See super_errors_ for more info.
    * - 0x3E
-     - \_\_le16
-     - s\_minor\_rev\_level
+     - __le16
+     - s_minor_rev_level
      - Minor revision level.
    * - 0x40
-     - \_\_le32
-     - s\_lastcheck
+     - __le32
+     - s_lastcheck
      - Time of last check, in seconds since the epoch.
    * - 0x44
-     - \_\_le32
-     - s\_checkinterval
+     - __le32
+     - s_checkinterval
      - Maximum time between checks, in seconds.
    * - 0x48
-     - \_\_le32
-     - s\_creator\_os
+     - __le32
+     - s_creator_os
      - Creator OS. See the table super_creator_ for more info.
    * - 0x4C
-     - \_\_le32
-     - s\_rev\_level
+     - __le32
+     - s_rev_level
      - Revision level. See the table super_revision_ for more info.
    * - 0x50
-     - \_\_le16
-     - s\_def\_resuid
+     - __le16
+     - s_def_resuid
      - Default uid for reserved blocks.
    * - 0x52
-     - \_\_le16
-     - s\_def\_resgid
+     - __le16
+     - s_def_resgid
      - Default gid for reserved blocks.
    * -
      -
@@ -143,50 +143,50 @@ The ext4 superblock is laid out as follows in
        about a feature in either the compatible or incompatible feature set, it
        must abort and not try to meddle with things it doesn't understand...
    * - 0x54
-     - \_\_le32
-     - s\_first\_ino
+     - __le32
+     - s_first_ino
      - First non-reserved inode.
    * - 0x58
-     - \_\_le16
-     - s\_inode\_size
+     - __le16
+     - s_inode_size
      - Size of inode structure, in bytes.
    * - 0x5A
-     - \_\_le16
-     - s\_block\_group\_nr
+     - __le16
+     - s_block_group_nr
      - Block group # of this superblock.
    * - 0x5C
-     - \_\_le32
-     - s\_feature\_compat
+     - __le32
+     - s_feature_compat
      - Compatible feature set flags. Kernel can still read/write this fs even
        if it doesn't understand a flag; fsck should not do that. See the
        super_compat_ table for more info.
    * - 0x60
-     - \_\_le32
-     - s\_feature\_incompat
+     - __le32
+     - s_feature_incompat
      - Incompatible feature set. If the kernel or fsck doesn't understand one
        of these bits, it should stop. See the super_incompat_ table for more
        info.
    * - 0x64
-     - \_\_le32
-     - s\_feature\_ro\_compat
+     - __le32
+     - s_feature_ro_compat
      - Readonly-compatible feature set. If the kernel doesn't understand one of
        these bits, it can still mount read-only. See the super_rocompat_ table
        for more info.
    * - 0x68
-     - \_\_u8
-     - s\_uuid[16]
+     - __u8
+     - s_uuid[16]
      - 128-bit UUID for volume.
    * - 0x78
      - char
-     - s\_volume\_name[16]
+     - s_volume_name[16]
      - Volume label.
    * - 0x88
      - char
-     - s\_last\_mounted[64]
+     - s_last_mounted[64]
      - Directory where filesystem was last mounted.
    * - 0xC8
-     - \_\_le32
-     - s\_algorithm\_usage\_bitmap
+     - __le32
+     - s_algorithm_usage_bitmap
      - For compression (Not used in e2fsprogs/Linux)
    * -
      -
@@ -194,18 +194,18 @@ The ext4 superblock is laid out as follows in
      - Performance hints.  Directory preallocation should only happen if the
        EXT4_FEATURE_COMPAT_DIR_PREALLOC flag is on.
    * - 0xCC
-     - \_\_u8
-     - s\_prealloc\_blocks
+     - __u8
+     - s_prealloc_blocks
      - #. of blocks to try to preallocate for ... files? (Not used in
        e2fsprogs/Linux)
    * - 0xCD
-     - \_\_u8
-     - s\_prealloc\_dir\_blocks
+     - __u8
+     - s_prealloc_dir_blocks
      - #. of blocks to preallocate for directories. (Not used in
        e2fsprogs/Linux)
    * - 0xCE
-     - \_\_le16
-     - s\_reserved\_gdt\_blocks
+     - __le16
+     - s_reserved_gdt_blocks
      - Number of reserved GDT entries for future filesystem expansion.
    * -
      -
@@ -213,281 +213,281 @@ The ext4 superblock is laid out as follows in
      - Journalling support is valid only if EXT4_FEATURE_COMPAT_HAS_JOURNAL is
        set.
    * - 0xD0
-     - \_\_u8
-     - s\_journal\_uuid[16]
+     - __u8
+     - s_journal_uuid[16]
      - UUID of journal superblock
    * - 0xE0
-     - \_\_le32
-     - s\_journal\_inum
+     - __le32
+     - s_journal_inum
      - inode number of journal file.
    * - 0xE4
-     - \_\_le32
-     - s\_journal\_dev
+     - __le32
+     - s_journal_dev
      - Device number of journal file, if the external journal feature flag is
        set.
    * - 0xE8
-     - \_\_le32
-     - s\_last\_orphan
+     - __le32
+     - s_last_orphan
      - Start of list of orphaned inodes to delete.
    * - 0xEC
-     - \_\_le32
-     - s\_hash\_seed[4]
+     - __le32
+     - s_hash_seed[4]
      - HTREE hash seed.
    * - 0xFC
-     - \_\_u8
-     - s\_def\_hash\_version
+     - __u8
+     - s_def_hash_version
      - Default hash algorithm to use for directory hashes. See super_def_hash_
        for more info.
    * - 0xFD
-     - \_\_u8
-     - s\_jnl\_backup\_type
-     - If this value is 0 or EXT3\_JNL\_BACKUP\_BLOCKS (1), then the
+     - __u8
+     - s_jnl_backup_type
+     - If this value is 0 or EXT3_JNL_BACKUP_BLOCKS (1), then the
        ``s_jnl_blocks`` field contains a duplicate copy of the inode's
        ``i_block[]`` array and ``i_size``.
    * - 0xFE
-     - \_\_le16
-     - s\_desc\_size
+     - __le16
+     - s_desc_size
      - Size of group descriptors, in bytes, if the 64bit incompat feature flag
        is set.
    * - 0x100
-     - \_\_le32
-     - s\_default\_mount\_opts
+     - __le32
+     - s_default_mount_opts
      - Default mount options. See the super_mountopts_ table for more info.
    * - 0x104
-     - \_\_le32
-     - s\_first\_meta\_bg
-     - First metablock block group, if the meta\_bg feature is enabled.
+     - __le32
+     - s_first_meta_bg
+     - First metablock block group, if the meta_bg feature is enabled.
    * - 0x108
-     - \_\_le32
-     - s\_mkfs\_time
+     - __le32
+     - s_mkfs_time
      - When the filesystem was created, in seconds since the epoch.
    * - 0x10C
-     - \_\_le32
-     - s\_jnl\_blocks[17]
+     - __le32
+     - s_jnl_blocks[17]
      - Backup copy of the journal inode's ``i_block[]`` array in the first 15
-       elements and i\_size\_high and i\_size in the 16th and 17th elements,
+       elements and i_size_high and i_size in the 16th and 17th elements,
        respectively.
    * -
      -
      -
      - 64bit support is valid only if EXT4_FEATURE_COMPAT_64BIT is set.
    * - 0x150
-     - \_\_le32
-     - s\_blocks\_count\_hi
+     - __le32
+     - s_blocks_count_hi
      - High 32-bits of the block count.
    * - 0x154
-     - \_\_le32
-     - s\_r\_blocks\_count\_hi
+     - __le32
+     - s_r_blocks_count_hi
      - High 32-bits of the reserved block count.
    * - 0x158
-     - \_\_le32
-     - s\_free\_blocks\_count\_hi
+     - __le32
+     - s_free_blocks_count_hi
      - High 32-bits of the free block count.
    * - 0x15C
-     - \_\_le16
-     - s\_min\_extra\_isize
+     - __le16
+     - s_min_extra_isize
      - All inodes have at least # bytes.
    * - 0x15E
-     - \_\_le16
-     - s\_want\_extra\_isize
+     - __le16
+     - s_want_extra_isize
      - New inodes should reserve # bytes.
    * - 0x160
-     - \_\_le32
-     - s\_flags
+     - __le32
+     - s_flags
      - Miscellaneous flags. See the super_flags_ table for more info.
    * - 0x164
-     - \_\_le16
-     - s\_raid\_stride
+     - __le16
+     - s_raid_stride
      - RAID stride. This is the number of logical blocks read from or written
        to the disk before moving to the next disk. This affects the placement
        of filesystem metadata, which will hopefully make RAID storage faster.
    * - 0x166
-     - \_\_le16
-     - s\_mmp\_interval
+     - __le16
+     - s_mmp_interval
      - #. seconds to wait in multi-mount prevention (MMP) checking. In theory,
        MMP is a mechanism to record in the superblock which host and device
        have mounted the filesystem, in order to prevent multiple mounts. This
        feature does not seem to be implemented...
    * - 0x168
-     - \_\_le64
-     - s\_mmp\_block
+     - __le64
+     - s_mmp_block
      - Block # for multi-mount protection data.
    * - 0x170
-     - \_\_le32
-     - s\_raid\_stripe\_width
+     - __le32
+     - s_raid_stripe_width
      - RAID stripe width. This is the number of logical blocks read from or
        written to the disk before coming back to the current disk. This is used
        by the block allocator to try to reduce the number of read-modify-write
        operations in a RAID5/6.
    * - 0x174
-     - \_\_u8
-     - s\_log\_groups\_per\_flex
+     - __u8
+     - s_log_groups_per_flex
      - Size of a flexible block group is 2 ^ ``s_log_groups_per_flex``.
    * - 0x175
-     - \_\_u8
-     - s\_checksum\_type
+     - __u8
+     - s_checksum_type
      - Metadata checksum algorithm type. The only valid value is 1 (crc32c).
    * - 0x176
-     - \_\_le16
-     - s\_reserved\_pad
+     - __le16
+     - s_reserved_pad
      -
    * - 0x178
-     - \_\_le64
-     - s\_kbytes\_written
+     - __le64
+     - s_kbytes_written
      - Number of KiB written to this filesystem over its lifetime.
    * - 0x180
-     - \_\_le32
-     - s\_snapshot\_inum
+     - __le32
+     - s_snapshot_inum
      - inode number of active snapshot. (Not used in e2fsprogs/Linux.)
    * - 0x184
-     - \_\_le32
-     - s\_snapshot\_id
+     - __le32
+     - s_snapshot_id
      - Sequential ID of active snapshot. (Not used in e2fsprogs/Linux.)
    * - 0x188
-     - \_\_le64
-     - s\_snapshot\_r\_blocks\_count
+     - __le64
+     - s_snapshot_r_blocks_count
      - Number of blocks reserved for active snapshot's future use. (Not used in
        e2fsprogs/Linux.)
    * - 0x190
-     - \_\_le32
-     - s\_snapshot\_list
+     - __le32
+     - s_snapshot_list
      - inode number of the head of the on-disk snapshot list. (Not used in
        e2fsprogs/Linux.)
    * - 0x194
-     - \_\_le32
-     - s\_error\_count
+     - __le32
+     - s_error_count
      - Number of errors seen.
    * - 0x198
-     - \_\_le32
-     - s\_first\_error\_time
+     - __le32
+     - s_first_error_time
      - First time an error happened, in seconds since the epoch.
    * - 0x19C
-     - \_\_le32
-     - s\_first\_error\_ino
+     - __le32
+     - s_first_error_ino
      - inode involved in first error.
    * - 0x1A0
-     - \_\_le64
-     - s\_first\_error\_block
+     - __le64
+     - s_first_error_block
      - Number of block involved of first error.
    * - 0x1A8
-     - \_\_u8
-     - s\_first\_error\_func[32]
+     - __u8
+     - s_first_error_func[32]
      - Name of function where the error happened.
    * - 0x1C8
-     - \_\_le32
-     - s\_first\_error\_line
+     - __le32
+     - s_first_error_line
      - Line number where error happened.
    * - 0x1CC
-     - \_\_le32
-     - s\_last\_error\_time
+     - __le32
+     - s_last_error_time
      - Time of most recent error, in seconds since the epoch.
    * - 0x1D0
-     - \_\_le32
-     - s\_last\_error\_ino
+     - __le32
+     - s_last_error_ino
      - inode involved in most recent error.
    * - 0x1D4
-     - \_\_le32
-     - s\_last\_error\_line
+     - __le32
+     - s_last_error_line
      - Line number where most recent error happened.
    * - 0x1D8
-     - \_\_le64
-     - s\_last\_error\_block
+     - __le64
+     - s_last_error_block
      - Number of block involved in most recent error.
    * - 0x1E0
-     - \_\_u8
-     - s\_last\_error\_func[32]
+     - __u8
+     - s_last_error_func[32]
      - Name of function where the most recent error happened.
    * - 0x200
-     - \_\_u8
-     - s\_mount\_opts[64]
+     - __u8
+     - s_mount_opts[64]
      - ASCIIZ string of mount options.
    * - 0x240
-     - \_\_le32
-     - s\_usr\_quota\_inum
+     - __le32
+     - s_usr_quota_inum
      - Inode number of user `quota <quota>`__ file.
    * - 0x244
-     - \_\_le32
-     - s\_grp\_quota\_inum
+     - __le32
+     - s_grp_quota_inum
      - Inode number of group `quota <quota>`__ file.
    * - 0x248
-     - \_\_le32
-     - s\_overhead\_blocks
+     - __le32
+     - s_overhead_blocks
      - Overhead blocks/clusters in fs. (Huh? This field is always zero, which
        means that the kernel calculates it dynamically.)
    * - 0x24C
-     - \_\_le32
-     - s\_backup\_bgs[2]
-     - Block groups containing superblock backups (if sparse\_super2)
+     - __le32
+     - s_backup_bgs[2]
+     - Block groups containing superblock backups (if sparse_super2)
    * - 0x254
-     - \_\_u8
-     - s\_encrypt\_algos[4]
+     - __u8
+     - s_encrypt_algos[4]
      - Encryption algorithms in use. There can be up to four algorithms in use
        at any time; valid algorithm codes are given in the super_encrypt_ table
        below.
    * - 0x258
-     - \_\_u8
-     - s\_encrypt\_pw\_salt[16]
+     - __u8
+     - s_encrypt_pw_salt[16]
      - Salt for the string2key algorithm for encryption.
    * - 0x268
-     - \_\_le32
-     - s\_lpf\_ino
+     - __le32
+     - s_lpf_ino
      - Inode number of lost+found
    * - 0x26C
-     - \_\_le32
-     - s\_prj\_quota\_inum
+     - __le32
+     - s_prj_quota_inum
      - Inode that tracks project quotas.
    * - 0x270
-     - \_\_le32
-     - s\_checksum\_seed
-     - Checksum seed used for metadata\_csum calculations. This value is
-       crc32c(~0, $orig\_fs\_uuid).
+     - __le32
+     - s_checksum_seed
+     - Checksum seed used for metadata_csum calculations. This value is
+       crc32c(~0, $orig_fs_uuid).
    * - 0x274
-     - \_\_u8
-     - s\_wtime_hi
+     - __u8
+     - s_wtime_hi
      - Upper 8 bits of the s_wtime field.
    * - 0x275
-     - \_\_u8
-     - s\_mtime_hi
+     - __u8
+     - s_mtime_hi
      - Upper 8 bits of the s_mtime field.
    * - 0x276
-     - \_\_u8
-     - s\_mkfs_time_hi
+     - __u8
+     - s_mkfs_time_hi
      - Upper 8 bits of the s_mkfs_time field.
    * - 0x277
-     - \_\_u8
-     - s\_lastcheck_hi
+     - __u8
+     - s_lastcheck_hi
      - Upper 8 bits of the s_lastcheck_hi field.
    * - 0x278
-     - \_\_u8
-     - s\_first_error_time_hi
+     - __u8
+     - s_first_error_time_hi
      - Upper 8 bits of the s_first_error_time_hi field.
    * - 0x279
-     - \_\_u8
-     - s\_last_error_time_hi
+     - __u8
+     - s_last_error_time_hi
      - Upper 8 bits of the s_last_error_time_hi field.
    * - 0x27A
-     - \_\_u8
-     - s\_pad[2]
+     - __u8
+     - s_pad[2]
      - Zero padding.
    * - 0x27C
-     - \_\_le16
-     - s\_encoding
+     - __le16
+     - s_encoding
      - Filename charset encoding.
    * - 0x27E
-     - \_\_le16
-     - s\_encoding_flags
+     - __le16
+     - s_encoding_flags
      - Filename charset encoding flags.
    * - 0x280
-     - \_\_le32
-     - s\_orphan\_file\_inum
+     - __le32
+     - s_orphan_file_inum
      - Orphan file inode number.
    * - 0x284
-     - \_\_le32
-     - s\_reserved[94]
+     - __le32
+     - s_reserved[94]
      - Padding to the end of the block.
    * - 0x3FC
-     - \_\_le32
-     - s\_checksum
+     - __le32
+     - s_checksum
      - Superblock checksum.
 
 .. _super_state:
@@ -574,44 +574,44 @@ following:
    * - Value
      - Description
    * - 0x1
-     - Directory preallocation (COMPAT\_DIR\_PREALLOC).
+     - Directory preallocation (COMPAT_DIR_PREALLOC).
    * - 0x2
      - “imagic inodes”. Not clear from the code what this does
-       (COMPAT\_IMAGIC\_INODES).
+       (COMPAT_IMAGIC_INODES).
    * - 0x4
-     - Has a journal (COMPAT\_HAS\_JOURNAL).
+     - Has a journal (COMPAT_HAS_JOURNAL).
    * - 0x8
-     - Supports extended attributes (COMPAT\_EXT\_ATTR).
+     - Supports extended attributes (COMPAT_EXT_ATTR).
    * - 0x10
      - Has reserved GDT blocks for filesystem expansion
-       (COMPAT\_RESIZE\_INODE). Requires RO\_COMPAT\_SPARSE\_SUPER.
+       (COMPAT_RESIZE_INODE). Requires RO_COMPAT_SPARSE_SUPER.
    * - 0x20
-     - Has directory indices (COMPAT\_DIR\_INDEX).
+     - Has directory indices (COMPAT_DIR_INDEX).
    * - 0x40
      - “Lazy BG”. Not in Linux kernel, seems to have been for uninitialized
-       block groups? (COMPAT\_LAZY\_BG)
+       block groups? (COMPAT_LAZY_BG)
    * - 0x80
-     - “Exclude inode”. Not used. (COMPAT\_EXCLUDE\_INODE).
+     - “Exclude inode”. Not used. (COMPAT_EXCLUDE_INODE).
    * - 0x100
      - “Exclude bitmap”. Seems to be used to indicate the presence of
        snapshot-related exclude bitmaps? Not defined in kernel or used in
-       e2fsprogs (COMPAT\_EXCLUDE\_BITMAP).
+       e2fsprogs (COMPAT_EXCLUDE_BITMAP).
    * - 0x200
-     - Sparse Super Block, v2. If this flag is set, the SB field s\_backup\_bgs
+     - Sparse Super Block, v2. If this flag is set, the SB field s_backup_bgs
        points to the two block groups that contain backup superblocks
-       (COMPAT\_SPARSE\_SUPER2).
+       (COMPAT_SPARSE_SUPER2).
    * - 0x400
      - Fast commits supported. Although fast commits blocks are
        backward incompatible, fast commit blocks are not always
        present in the journal. If fast commit blocks are present in
        the journal, JBD2 incompat feature
-       (JBD2\_FEATURE\_INCOMPAT\_FAST\_COMMIT) gets
-       set (COMPAT\_FAST\_COMMIT).
+       (JBD2_FEATURE_INCOMPAT_FAST_COMMIT) gets
+       set (COMPAT_FAST_COMMIT).
    * - 0x1000
      - Orphan file allocated. This is the special file for more efficient
        tracking of unlinked but still open inodes. When there may be any
        entries in the file, we additionally set proper rocompat feature
-       (RO\_COMPAT\_ORPHAN\_PRESENT).
+       (RO_COMPAT_ORPHAN_PRESENT).
 
 .. _super_incompat:
 
@@ -625,45 +625,45 @@ following:
    * - Value
      - Description
    * - 0x1
-     - Compression (INCOMPAT\_COMPRESSION).
+     - Compression (INCOMPAT_COMPRESSION).
    * - 0x2
-     - Directory entries record the file type. See ext4\_dir\_entry\_2 below
-       (INCOMPAT\_FILETYPE).
+     - Directory entries record the file type. See ext4_dir_entry_2 below
+       (INCOMPAT_FILETYPE).
    * - 0x4
-     - Filesystem needs recovery (INCOMPAT\_RECOVER).
+     - Filesystem needs recovery (INCOMPAT_RECOVER).
    * - 0x8
-     - Filesystem has a separate journal device (INCOMPAT\_JOURNAL\_DEV).
+     - Filesystem has a separate journal device (INCOMPAT_JOURNAL_DEV).
    * - 0x10
      - Meta block groups. See the earlier discussion of this feature
-       (INCOMPAT\_META\_BG).
+       (INCOMPAT_META_BG).
    * - 0x40
-     - Files in this filesystem use extents (INCOMPAT\_EXTENTS).
+     - Files in this filesystem use extents (INCOMPAT_EXTENTS).
    * - 0x80
-     - Enable a filesystem size of 2^64 blocks (INCOMPAT\_64BIT).
+     - Enable a filesystem size of 2^64 blocks (INCOMPAT_64BIT).
    * - 0x100
-     - Multiple mount protection (INCOMPAT\_MMP).
+     - Multiple mount protection (INCOMPAT_MMP).
    * - 0x200
      - Flexible block groups. See the earlier discussion of this feature
-       (INCOMPAT\_FLEX\_BG).
+       (INCOMPAT_FLEX_BG).
    * - 0x400
      - Inodes can be used to store large extended attribute values
-       (INCOMPAT\_EA\_INODE).
+       (INCOMPAT_EA_INODE).
    * - 0x1000
-     - Data in directory entry (INCOMPAT\_DIRDATA). (Not implemented?)
+     - Data in directory entry (INCOMPAT_DIRDATA). (Not implemented?)
    * - 0x2000
      - Metadata checksum seed is stored in the superblock. This feature enables
-       the administrator to change the UUID of a metadata\_csum filesystem
+       the administrator to change the UUID of a metadata_csum filesystem
        while the filesystem is mounted; without it, the checksum definition
-       requires all metadata blocks to be rewritten (INCOMPAT\_CSUM\_SEED).
+       requires all metadata blocks to be rewritten (INCOMPAT_CSUM_SEED).
    * - 0x4000
-     - Large directory >2GB or 3-level htree (INCOMPAT\_LARGEDIR). Prior to
+     - Large directory >2GB or 3-level htree (INCOMPAT_LARGEDIR). Prior to
        this feature, directories could not be larger than 4GiB and could not
        have an htree more than 2 levels deep. If this feature is enabled,
        directories can be larger than 4GiB and have a maximum htree depth of 3.
    * - 0x8000
-     - Data in inode (INCOMPAT\_INLINE\_DATA).
+     - Data in inode (INCOMPAT_INLINE_DATA).
    * - 0x10000
-     - Encrypted inodes are present on the filesystem. (INCOMPAT\_ENCRYPT).
+     - Encrypted inodes are present on the filesystem. (INCOMPAT_ENCRYPT).
 
 .. _super_rocompat:
 
@@ -678,54 +678,54 @@ the following:
      - Description
    * - 0x1
      - Sparse superblocks. See the earlier discussion of this feature
-       (RO\_COMPAT\_SPARSE\_SUPER).
+       (RO_COMPAT_SPARSE_SUPER).
    * - 0x2
      - This filesystem has been used to store a file greater than 2GiB
-       (RO\_COMPAT\_LARGE\_FILE).
+       (RO_COMPAT_LARGE_FILE).
    * - 0x4
-     - Not used in kernel or e2fsprogs (RO\_COMPAT\_BTREE\_DIR).
+     - Not used in kernel or e2fsprogs (RO_COMPAT_BTREE_DIR).
    * - 0x8
      - This filesystem has files whose sizes are represented in units of
        logical blocks, not 512-byte sectors. This implies a very large file
-       indeed! (RO\_COMPAT\_HUGE\_FILE)
+       indeed! (RO_COMPAT_HUGE_FILE)
    * - 0x10
      - Group descriptors have checksums. In addition to detecting corruption,
        this is useful for lazy formatting with uninitialized groups
-       (RO\_COMPAT\_GDT\_CSUM).
+       (RO_COMPAT_GDT_CSUM).
    * - 0x20
      - Indicates that the old ext3 32,000 subdirectory limit no longer applies
-       (RO\_COMPAT\_DIR\_NLINK). A directory's i\_links\_count will be set to 1
+       (RO_COMPAT_DIR_NLINK). A directory's i_links_count will be set to 1
        if it is incremented past 64,999.
    * - 0x40
      - Indicates that large inodes exist on this filesystem
-       (RO\_COMPAT\_EXTRA\_ISIZE).
+       (RO_COMPAT_EXTRA_ISIZE).
    * - 0x80
-     - This filesystem has a snapshot (RO\_COMPAT\_HAS\_SNAPSHOT).
+     - This filesystem has a snapshot (RO_COMPAT_HAS_SNAPSHOT).
    * - 0x100
-     - `Quota <Quota>`__ (RO\_COMPAT\_QUOTA).
+     - `Quota <Quota>`__ (RO_COMPAT_QUOTA).
    * - 0x200
      - This filesystem supports “bigalloc”, which means that file extents are
        tracked in units of clusters (of blocks) instead of blocks
-       (RO\_COMPAT\_BIGALLOC).
+       (RO_COMPAT_BIGALLOC).
    * - 0x400
      - This filesystem supports metadata checksumming.
-       (RO\_COMPAT\_METADATA\_CSUM; implies RO\_COMPAT\_GDT\_CSUM, though
-       GDT\_CSUM must not be set)
+       (RO_COMPAT_METADATA_CSUM; implies RO_COMPAT_GDT_CSUM, though
+       GDT_CSUM must not be set)
    * - 0x800
      - Filesystem supports replicas. This feature is neither in the kernel nor
-       e2fsprogs. (RO\_COMPAT\_REPLICA)
+       e2fsprogs. (RO_COMPAT_REPLICA)
    * - 0x1000
      - Read-only filesystem image; the kernel will not mount this image
        read-write and most tools will refuse to write to the image.
-       (RO\_COMPAT\_READONLY)
+       (RO_COMPAT_READONLY)
    * - 0x2000
-     - Filesystem tracks project quotas. (RO\_COMPAT\_PROJECT)
+     - Filesystem tracks project quotas. (RO_COMPAT_PROJECT)
    * - 0x8000
-     - Verity inodes may be present on the filesystem. (RO\_COMPAT\_VERITY)
+     - Verity inodes may be present on the filesystem. (RO_COMPAT_VERITY)
    * - 0x10000
      - Indicates orphan file may have valid orphan entries and thus we need
        to clean them up when mounting the filesystem
-       (RO\_COMPAT\_ORPHAN\_PRESENT).
+       (RO_COMPAT_ORPHAN_PRESENT).
 
 .. _super_def_hash:
 
@@ -761,36 +761,36 @@ The ``s_default_mount_opts`` field is any combination of the following:
    * - Value
      - Description
    * - 0x0001
-     - Print debugging info upon (re)mount. (EXT4\_DEFM\_DEBUG)
+     - Print debugging info upon (re)mount. (EXT4_DEFM_DEBUG)
    * - 0x0002
      - New files take the gid of the containing directory (instead of the fsgid
-       of the current process). (EXT4\_DEFM\_BSDGROUPS)
+       of the current process). (EXT4_DEFM_BSDGROUPS)
    * - 0x0004
-     - Support userspace-provided extended attributes. (EXT4\_DEFM\_XATTR\_USER)
+     - Support userspace-provided extended attributes. (EXT4_DEFM_XATTR_USER)
    * - 0x0008
-     - Support POSIX access control lists (ACLs). (EXT4\_DEFM\_ACL)
+     - Support POSIX access control lists (ACLs). (EXT4_DEFM_ACL)
    * - 0x0010
-     - Do not support 32-bit UIDs. (EXT4\_DEFM\_UID16)
+     - Do not support 32-bit UIDs. (EXT4_DEFM_UID16)
    * - 0x0020
      - All data and metadata are commited to the journal.
-       (EXT4\_DEFM\_JMODE\_DATA)
+       (EXT4_DEFM_JMODE_DATA)
    * - 0x0040
      - All data are flushed to the disk before metadata are committed to the
-       journal. (EXT4\_DEFM\_JMODE\_ORDERED)
+       journal. (EXT4_DEFM_JMODE_ORDERED)
    * - 0x0060
      - Data ordering is not preserved; data may be written after the metadata
-       has been written. (EXT4\_DEFM\_JMODE\_WBACK)
+       has been written. (EXT4_DEFM_JMODE_WBACK)
    * - 0x0100
-     - Disable write flushes. (EXT4\_DEFM\_NOBARRIER)
+     - Disable write flushes. (EXT4_DEFM_NOBARRIER)
    * - 0x0200
      - Track which blocks in a filesystem are metadata and therefore should not
        be used as data blocks. This option will be enabled by default on 3.18,
-       hopefully. (EXT4\_DEFM\_BLOCK\_VALIDITY)
+       hopefully. (EXT4_DEFM_BLOCK_VALIDITY)
    * - 0x0400
      - Enable DISCARD support, where the storage device is told about blocks
-       becoming unused. (EXT4\_DEFM\_DISCARD)
+       becoming unused. (EXT4_DEFM_DISCARD)
    * - 0x0800
-     - Disable delayed allocation. (EXT4\_DEFM\_NODELALLOC)
+     - Disable delayed allocation. (EXT4_DEFM_NODELALLOC)
 
 .. _super_flags:
 
@@ -820,12 +820,12 @@ The ``s_encrypt_algos`` list can contain any of the following:
    * - Value
      - Description
    * - 0
-     - Invalid algorithm (ENCRYPTION\_MODE\_INVALID).
+     - Invalid algorithm (ENCRYPTION_MODE_INVALID).
    * - 1
-     - 256-bit AES in XTS mode (ENCRYPTION\_MODE\_AES\_256\_XTS).
+     - 256-bit AES in XTS mode (ENCRYPTION_MODE_AES_256_XTS).
    * - 2
-     - 256-bit AES in GCM mode (ENCRYPTION\_MODE\_AES\_256\_GCM).
+     - 256-bit AES in GCM mode (ENCRYPTION_MODE_AES_256_GCM).
    * - 3
-     - 256-bit AES in CBC mode (ENCRYPTION\_MODE\_AES\_256\_CBC).
+     - 256-bit AES in CBC mode (ENCRYPTION_MODE_AES_256_CBC).
 
 Total size of the superblock is 1024 bytes.
-- 
GitLab


From 32fc810b364f3dd30930c594e461ffa1761fef39 Mon Sep 17 00:00:00 2001
From: Dylan Yudaken <dylany@fb.com>
Date: Thu, 16 Jun 2022 06:50:11 -0700
Subject: [PATCH 0677/1731] io_uring: do not use prio task_work_add in
 uring_cmd

io_req_task_prio_work_add has a strict assumption that it will only be
used with io_req_task_complete. There is a codepath that assumes this is
the case and will not even call the completion function if it is hit.

For uring_cmd with an arbitrary completion function change the call to the
correct non-priority version.

Fixes: ee692a21e9bf8 ("fs,io_uring: add infrastructure for uring-cmd")
Signed-off-by: Dylan Yudaken <dylany@fb.com>
Reviewed-by: Pavel Begunkov <asml.silence@gmail.com>
Link: https://lore.kernel.org/r/20220616135011.441980-1-dylany@fb.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index b6e75f69c6b1e..95a1a78d799a1 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -5017,7 +5017,7 @@ void io_uring_cmd_complete_in_task(struct io_uring_cmd *ioucmd,
 
 	req->uring_cmd.task_work_cb = task_work_cb;
 	req->io_task_work.func = io_uring_cmd_work;
-	io_req_task_prio_work_add(req);
+	io_req_task_work_add(req);
 }
 EXPORT_SYMBOL_GPL(io_uring_cmd_complete_in_task);
 
-- 
GitLab


From 15baa7dcadf1c4f0b4f752dc054191855ff2d78e Mon Sep 17 00:00:00 2001
From: Zhang Yi <yi.zhang@huawei.com>
Date: Fri, 20 May 2022 10:32:16 +0800
Subject: [PATCH 0678/1731] ext4: fix warning when submitting superblock in
 ext4_commit_super()

We have already check the io_error and uptodate flag before submitting
the superblock buffer, and re-set the uptodate flag if it has been
failed to write out. But it was lockless and could be raced by another
ext4_commit_super(), and finally trigger '!uptodate' WARNING when
marking buffer dirty. Fix it by submit buffer directly.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Zhang Yi <yi.zhang@huawei.com>
Reviewed-by: Jan Kara <jack@suse.cz>
Reviewed-by: Ritesh Harjani <ritesh.list@gmail.com>
Link: https://lore.kernel.org/r/20220520023216.3065073-1-yi.zhang@huawei.com
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
---
 fs/ext4/super.c | 22 ++++++++++++++++------
 1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/fs/ext4/super.c b/fs/ext4/super.c
index 450c918d68fcf..b2ecae8adbfc0 100644
--- a/fs/ext4/super.c
+++ b/fs/ext4/super.c
@@ -5898,7 +5898,6 @@ static void ext4_update_super(struct super_block *sb)
 static int ext4_commit_super(struct super_block *sb)
 {
 	struct buffer_head *sbh = EXT4_SB(sb)->s_sbh;
-	int error = 0;
 
 	if (!sbh)
 		return -EINVAL;
@@ -5907,6 +5906,13 @@ static int ext4_commit_super(struct super_block *sb)
 
 	ext4_update_super(sb);
 
+	lock_buffer(sbh);
+	/* Buffer got discarded which means block device got invalidated */
+	if (!buffer_mapped(sbh)) {
+		unlock_buffer(sbh);
+		return -EIO;
+	}
+
 	if (buffer_write_io_error(sbh) || !buffer_uptodate(sbh)) {
 		/*
 		 * Oh, dear.  A previous attempt to write the
@@ -5921,17 +5927,21 @@ static int ext4_commit_super(struct super_block *sb)
 		clear_buffer_write_io_error(sbh);
 		set_buffer_uptodate(sbh);
 	}
-	BUFFER_TRACE(sbh, "marking dirty");
-	mark_buffer_dirty(sbh);
-	error = __sync_dirty_buffer(sbh,
-		REQ_SYNC | (test_opt(sb, BARRIER) ? REQ_FUA : 0));
+	get_bh(sbh);
+	/* Clear potential dirty bit if it was journalled update */
+	clear_buffer_dirty(sbh);
+	sbh->b_end_io = end_buffer_write_sync;
+	submit_bh(REQ_OP_WRITE,
+		  REQ_SYNC | (test_opt(sb, BARRIER) ? REQ_FUA : 0), sbh);
+	wait_on_buffer(sbh);
 	if (buffer_write_io_error(sbh)) {
 		ext4_msg(sb, KERN_ERR, "I/O error while writing "
 		       "superblock");
 		clear_buffer_write_io_error(sbh);
 		set_buffer_uptodate(sbh);
+		return -EIO;
 	}
-	return error;
+	return 0;
 }
 
 /*
-- 
GitLab


From 4deb96e35c5c3ebfeb9cf567f3ba80fa54e2cec1 Mon Sep 17 00:00:00 2001
From: Robin Murphy <robin.murphy@arm.com>
Date: Thu, 16 Jun 2022 14:46:46 +0100
Subject: [PATCH 0679/1731] irqchip/gicv3: Handle resource request failure
 consistently

Due to a silly oversight on my part, making the simple switch to
of_io_request_and_map() in the DT path inadvertently introduced
divergent behaviour, whereby failng to request an iomem region now
becomes fatal for DT, vs. being silently ignored for ACPI.

Refactor a bit harder, so that request errors are non-fatal in both
paths as intended, but also consistently reported as well.

Reported-by: Matt Ranostay <mranostay@ti.com>
Fixes: 2b2cd74a06c3 ("irqchip/gic-v3: Claim iomem resources")
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/5f2b57a0131f3082fae9d3002d360bf784ccb092.1655387206.git.robin.murphy@arm.com
---
 drivers/irqchip/irq-gic-v3.c | 41 +++++++++++++++++++++++++++---------
 1 file changed, 31 insertions(+), 10 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 5c1cf907ee68d..2d25bca63d2a1 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -2042,15 +2042,40 @@ static void __init gic_of_setup_kvm_info(struct device_node *node)
 	vgic_set_kvm_info(&gic_v3_kvm_info);
 }
 
+static void gic_request_region(resource_size_t base, resource_size_t size,
+			       const char *name)
+{
+	if (!request_mem_region(base, size, name))
+		pr_warn_once(FW_BUG "%s region %pa has overlapping address\n",
+			     name, &base);
+}
+
+static void __iomem *gic_of_iomap(struct device_node *node, int idx,
+				  const char *name, struct resource *res)
+{
+	void __iomem *base;
+	int ret;
+
+	ret = of_address_to_resource(node, idx, res);
+	if (ret)
+		return IOMEM_ERR_PTR(ret);
+
+	gic_request_region(res->start, resource_size(res), name);
+	base = of_iomap(node, idx);
+
+	return base ?: IOMEM_ERR_PTR(-ENOMEM);
+}
+
 static int __init gic_of_init(struct device_node *node, struct device_node *parent)
 {
 	void __iomem *dist_base;
 	struct redist_region *rdist_regs;
+	struct resource res;
 	u64 redist_stride;
 	u32 nr_redist_regions;
 	int err, i;
 
-	dist_base = of_io_request_and_map(node, 0, "GICD");
+	dist_base = gic_of_iomap(node, 0, "GICD", &res);
 	if (IS_ERR(dist_base)) {
 		pr_err("%pOF: unable to map gic dist registers\n", node);
 		return PTR_ERR(dist_base);
@@ -2073,12 +2098,8 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
 	}
 
 	for (i = 0; i < nr_redist_regions; i++) {
-		struct resource res;
-		int ret;
-
-		ret = of_address_to_resource(node, 1 + i, &res);
-		rdist_regs[i].redist_base = of_io_request_and_map(node, 1 + i, "GICR");
-		if (ret || IS_ERR(rdist_regs[i].redist_base)) {
+		rdist_regs[i].redist_base = gic_of_iomap(node, 1 + i, "GICR", &res);
+		if (IS_ERR(rdist_regs[i].redist_base)) {
 			pr_err("%pOF: couldn't map region %d\n", node, i);
 			err = -ENODEV;
 			goto out_unmap_rdist;
@@ -2151,7 +2172,7 @@ gic_acpi_parse_madt_redist(union acpi_subtable_headers *header,
 		pr_err("Couldn't map GICR region @%llx\n", redist->base_address);
 		return -ENOMEM;
 	}
-	request_mem_region(redist->base_address, redist->length, "GICR");
+	gic_request_region(redist->base_address, redist->length, "GICR");
 
 	gic_acpi_register_redist(redist->base_address, redist_base);
 	return 0;
@@ -2174,7 +2195,7 @@ gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header,
 	redist_base = ioremap(gicc->gicr_base_address, size);
 	if (!redist_base)
 		return -ENOMEM;
-	request_mem_region(gicc->gicr_base_address, size, "GICR");
+	gic_request_region(gicc->gicr_base_address, size, "GICR");
 
 	gic_acpi_register_redist(gicc->gicr_base_address, redist_base);
 	return 0;
@@ -2376,7 +2397,7 @@ gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end)
 		pr_err("Unable to map GICD registers\n");
 		return -ENOMEM;
 	}
-	request_mem_region(dist->base_address, ACPI_GICV3_DIST_MEM_SIZE, "GICD");
+	gic_request_region(dist->base_address, ACPI_GICV3_DIST_MEM_SIZE, "GICD");
 
 	err = gic_validate_dist_version(acpi_data.dist_base);
 	if (err) {
-- 
GitLab


From 8d5459c11f548131ce48b2fbf45cccc5c382558f Mon Sep 17 00:00:00 2001
From: Jan Kara <jack@suse.cz>
Date: Fri, 20 May 2022 13:14:02 +0200
Subject: [PATCH 0680/1731] ext4: improve write performance with disabled
 delalloc

When delayed allocation is disabled (either through mount option or
because we are running low on free space), ext4_write_begin() allocates
blocks with EXT4_GET_BLOCKS_IO_CREATE_EXT flag. With this flag extent
merging is disabled and since ext4_write_begin() is called for each page
separately, we end up with a *lot* of 1 block extents in the extent tree
and following writeback is writing 1 block at a time which results in
very poor write throughput (4 MB/s instead of 200 MB/s). These days when
ext4_get_block_unwritten() is used only by ext4_write_begin(),
ext4_page_mkwrite() and inline data conversion, we can safely allow
extent merging to happen from these paths since following writeback will
happen on different boundaries anyway. So use
EXT4_GET_BLOCKS_CREATE_UNRIT_EXT instead which restores the performance.

Signed-off-by: Jan Kara <jack@suse.cz>
Link: https://lore.kernel.org/r/20220520111402.4252-1-jack@suse.cz
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
---
 fs/ext4/inode.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c
index 3dce7d058985b..84c0eb55071d6 100644
--- a/fs/ext4/inode.c
+++ b/fs/ext4/inode.c
@@ -829,7 +829,7 @@ int ext4_get_block_unwritten(struct inode *inode, sector_t iblock,
 	ext4_debug("ext4_get_block_unwritten: inode %lu, create flag %d\n",
 		   inode->i_ino, create);
 	return _ext4_get_block(inode, iblock, bh_result,
-			       EXT4_GET_BLOCKS_IO_CREATE_EXT);
+			       EXT4_GET_BLOCKS_CREATE_UNWRIT_EXT);
 }
 
 /* Maximum number of blocks we map for direct IO at once. */
-- 
GitLab


From 3f77a1d0570e62cfce8d472319df00008bbeab38 Mon Sep 17 00:00:00 2001
From: Mark Brown <broonie@kernel.org>
Date: Wed, 15 Jun 2022 20:15:04 +0100
Subject: [PATCH 0681/1731] arm64/cpufeature: Unexport set_cpu_feature()

We currently export set_cpu_feature() to modules but there are no in tree
users that can be built as modules and it is hard to see cases where it
would make sense for there to be any such users. Remove the export to avoid
anyone else having to worry about why it is there and ensure that any users
that do get added get a bit more visiblity.

Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20220615191504.626604-1-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/kernel/cpufeature.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 42ea2bd856c60..d76fd95376f07 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -3109,7 +3109,6 @@ void cpu_set_feature(unsigned int num)
 	WARN_ON(num >= MAX_CPU_FEATURES);
 	elf_hwcap |= BIT(num);
 }
-EXPORT_SYMBOL_GPL(cpu_set_feature);
 
 bool cpu_have_feature(unsigned int num)
 {
-- 
GitLab


From 593d1ebe00a45af5cb7bda1235c0790987c2a2b2 Mon Sep 17 00:00:00 2001
From: Joanne Koong <joannelkoong@gmail.com>
Date: Wed, 15 Jun 2022 12:32:13 -0700
Subject: [PATCH 0682/1731] Revert "net: Add a second bind table hashed by port
 and address"

This reverts:

commit d5a42de8bdbe ("net: Add a second bind table hashed by port and address")
commit 538aaf9b2383 ("selftests: Add test for timing a bind request to a port with a populated bhash entry")
Link: https://lore.kernel.org/netdev/20220520001834.2247810-1-kuba@kernel.org/

There are a few things that need to be fixed here:
* Updating bhash2 in cases where the socket's rcv saddr changes
* Adding bhash2 hashbucket locks

Links to syzbot reports:
https://lore.kernel.org/netdev/00000000000022208805e0df247a@google.com/
https://lore.kernel.org/netdev/0000000000003f33bc05dfaf44fe@google.com/

Fixes: d5a42de8bdbe ("net: Add a second bind table hashed by port and address")
Reported-by: syzbot+015d756bbd1f8b5c8f09@syzkaller.appspotmail.com
Reported-by: syzbot+98fd2d1422063b0f8c44@syzkaller.appspotmail.com
Reported-by: syzbot+0a847a982613c6438fba@syzkaller.appspotmail.com
Signed-off-by: Joanne Koong <joannelkoong@gmail.com>
Link: https://lore.kernel.org/r/20220615193213.2419568-1-joannelkoong@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 include/net/inet_connection_sock.h            |   3 -
 include/net/inet_hashtables.h                 |  68 +----
 include/net/sock.h                            |  14 -
 net/dccp/proto.c                              |  33 +--
 net/ipv4/inet_connection_sock.c               | 247 +++++-------------
 net/ipv4/inet_hashtables.c                    | 193 +-------------
 net/ipv4/tcp.c                                |  14 +-
 tools/testing/selftests/net/.gitignore        |   1 -
 tools/testing/selftests/net/Makefile          |   2 -
 tools/testing/selftests/net/bind_bhash_test.c | 119 ---------
 10 files changed, 83 insertions(+), 611 deletions(-)
 delete mode 100644 tools/testing/selftests/net/bind_bhash_test.c

diff --git a/include/net/inet_connection_sock.h b/include/net/inet_connection_sock.h
index 077cd730ce2fb..85cd695e7fd1d 100644
--- a/include/net/inet_connection_sock.h
+++ b/include/net/inet_connection_sock.h
@@ -25,7 +25,6 @@
 #undef INET_CSK_CLEAR_TIMERS
 
 struct inet_bind_bucket;
-struct inet_bind2_bucket;
 struct tcp_congestion_ops;
 
 /*
@@ -58,7 +57,6 @@ struct inet_connection_sock_af_ops {
  *
  * @icsk_accept_queue:	   FIFO of established children
  * @icsk_bind_hash:	   Bind node
- * @icsk_bind2_hash:	   Bind node in the bhash2 table
  * @icsk_timeout:	   Timeout
  * @icsk_retransmit_timer: Resend (no ack)
  * @icsk_rto:		   Retransmit timeout
@@ -85,7 +83,6 @@ struct inet_connection_sock {
 	struct inet_sock	  icsk_inet;
 	struct request_sock_queue icsk_accept_queue;
 	struct inet_bind_bucket	  *icsk_bind_hash;
-	struct inet_bind2_bucket  *icsk_bind2_hash;
 	unsigned long		  icsk_timeout;
  	struct timer_list	  icsk_retransmit_timer;
  	struct timer_list	  icsk_delack_timer;
diff --git a/include/net/inet_hashtables.h b/include/net/inet_hashtables.h
index a0887b70967b6..ebfa3df6f8dc3 100644
--- a/include/net/inet_hashtables.h
+++ b/include/net/inet_hashtables.h
@@ -90,32 +90,11 @@ struct inet_bind_bucket {
 	struct hlist_head	owners;
 };
 
-struct inet_bind2_bucket {
-	possible_net_t		ib_net;
-	int			l3mdev;
-	unsigned short		port;
-	union {
-#if IS_ENABLED(CONFIG_IPV6)
-		struct in6_addr		v6_rcv_saddr;
-#endif
-		__be32			rcv_saddr;
-	};
-	/* Node in the inet2_bind_hashbucket chain */
-	struct hlist_node	node;
-	/* List of sockets hashed to this bucket */
-	struct hlist_head	owners;
-};
-
 static inline struct net *ib_net(struct inet_bind_bucket *ib)
 {
 	return read_pnet(&ib->ib_net);
 }
 
-static inline struct net *ib2_net(struct inet_bind2_bucket *ib)
-{
-	return read_pnet(&ib->ib_net);
-}
-
 #define inet_bind_bucket_for_each(tb, head) \
 	hlist_for_each_entry(tb, head, node)
 
@@ -124,15 +103,6 @@ struct inet_bind_hashbucket {
 	struct hlist_head	chain;
 };
 
-/* This is synchronized using the inet_bind_hashbucket's spinlock.
- * Instead of having separate spinlocks, the inet_bind2_hashbucket can share
- * the inet_bind_hashbucket's given that in every case where the bhash2 table
- * is useful, a lookup in the bhash table also occurs.
- */
-struct inet_bind2_hashbucket {
-	struct hlist_head	chain;
-};
-
 /* Sockets can be hashed in established or listening table.
  * We must use different 'nulls' end-of-chain value for all hash buckets :
  * A socket might transition from ESTABLISH to LISTEN state without
@@ -164,12 +134,6 @@ struct inet_hashinfo {
 	 */
 	struct kmem_cache		*bind_bucket_cachep;
 	struct inet_bind_hashbucket	*bhash;
-	/* The 2nd binding table hashed by port and address.
-	 * This is used primarily for expediting the resolution of bind
-	 * conflicts.
-	 */
-	struct kmem_cache		*bind2_bucket_cachep;
-	struct inet_bind2_hashbucket	*bhash2;
 	unsigned int			bhash_size;
 
 	/* The 2nd listener table hashed by local port and address */
@@ -229,36 +193,6 @@ inet_bind_bucket_create(struct kmem_cache *cachep, struct net *net,
 void inet_bind_bucket_destroy(struct kmem_cache *cachep,
 			      struct inet_bind_bucket *tb);
 
-static inline bool check_bind_bucket_match(struct inet_bind_bucket *tb,
-					   struct net *net,
-					   const unsigned short port,
-					   int l3mdev)
-{
-	return net_eq(ib_net(tb), net) && tb->port == port &&
-		tb->l3mdev == l3mdev;
-}
-
-struct inet_bind2_bucket *
-inet_bind2_bucket_create(struct kmem_cache *cachep, struct net *net,
-			 struct inet_bind2_hashbucket *head,
-			 const unsigned short port, int l3mdev,
-			 const struct sock *sk);
-
-void inet_bind2_bucket_destroy(struct kmem_cache *cachep,
-			       struct inet_bind2_bucket *tb);
-
-struct inet_bind2_bucket *
-inet_bind2_bucket_find(struct inet_hashinfo *hinfo, struct net *net,
-		       const unsigned short port, int l3mdev,
-		       struct sock *sk,
-		       struct inet_bind2_hashbucket **head);
-
-bool check_bind2_bucket_match_nulladdr(struct inet_bind2_bucket *tb,
-				       struct net *net,
-				       const unsigned short port,
-				       int l3mdev,
-				       const struct sock *sk);
-
 static inline u32 inet_bhashfn(const struct net *net, const __u16 lport,
 			       const u32 bhash_size)
 {
@@ -266,7 +200,7 @@ static inline u32 inet_bhashfn(const struct net *net, const __u16 lport,
 }
 
 void inet_bind_hash(struct sock *sk, struct inet_bind_bucket *tb,
-		    struct inet_bind2_bucket *tb2, const unsigned short snum);
+		    const unsigned short snum);
 
 /* Caller must disable local BH processing. */
 int __inet_inherit_port(const struct sock *sk, struct sock *child);
diff --git a/include/net/sock.h b/include/net/sock.h
index c585ef6565d93..72ca97ccb4607 100644
--- a/include/net/sock.h
+++ b/include/net/sock.h
@@ -348,7 +348,6 @@ struct sk_filter;
   *	@sk_txtime_report_errors: set report errors mode for SO_TXTIME
   *	@sk_txtime_unused: unused txtime flags
   *	@ns_tracker: tracker for netns reference
-  *	@sk_bind2_node: bind node in the bhash2 table
   */
 struct sock {
 	/*
@@ -538,7 +537,6 @@ struct sock {
 #endif
 	struct rcu_head		sk_rcu;
 	netns_tracker		ns_tracker;
-	struct hlist_node	sk_bind2_node;
 };
 
 enum sk_pacing {
@@ -819,16 +817,6 @@ static inline void sk_add_bind_node(struct sock *sk,
 	hlist_add_head(&sk->sk_bind_node, list);
 }
 
-static inline void __sk_del_bind2_node(struct sock *sk)
-{
-	__hlist_del(&sk->sk_bind2_node);
-}
-
-static inline void sk_add_bind2_node(struct sock *sk, struct hlist_head *list)
-{
-	hlist_add_head(&sk->sk_bind2_node, list);
-}
-
 #define sk_for_each(__sk, list) \
 	hlist_for_each_entry(__sk, list, sk_node)
 #define sk_for_each_rcu(__sk, list) \
@@ -846,8 +834,6 @@ static inline void sk_add_bind2_node(struct sock *sk, struct hlist_head *list)
 	hlist_for_each_entry_safe(__sk, tmp, list, sk_node)
 #define sk_for_each_bound(__sk, list) \
 	hlist_for_each_entry(__sk, list, sk_bind_node)
-#define sk_for_each_bound_bhash2(__sk, list) \
-	hlist_for_each_entry(__sk, list, sk_bind2_node)
 
 /**
  * sk_for_each_entry_offset_rcu - iterate over a list at a given struct offset
diff --git a/net/dccp/proto.c b/net/dccp/proto.c
index 2e78458900f28..eb8e128e43e8b 100644
--- a/net/dccp/proto.c
+++ b/net/dccp/proto.c
@@ -1120,12 +1120,6 @@ static int __init dccp_init(void)
 				  SLAB_HWCACHE_ALIGN | SLAB_ACCOUNT, NULL);
 	if (!dccp_hashinfo.bind_bucket_cachep)
 		goto out_free_hashinfo2;
-	dccp_hashinfo.bind2_bucket_cachep =
-		kmem_cache_create("dccp_bind2_bucket",
-				  sizeof(struct inet_bind2_bucket), 0,
-				  SLAB_HWCACHE_ALIGN | SLAB_ACCOUNT, NULL);
-	if (!dccp_hashinfo.bind2_bucket_cachep)
-		goto out_free_bind_bucket_cachep;
 
 	/*
 	 * Size and allocate the main established and bind bucket
@@ -1156,7 +1150,7 @@ static int __init dccp_init(void)
 
 	if (!dccp_hashinfo.ehash) {
 		DCCP_CRIT("Failed to allocate DCCP established hash table");
-		goto out_free_bind2_bucket_cachep;
+		goto out_free_bind_bucket_cachep;
 	}
 
 	for (i = 0; i <= dccp_hashinfo.ehash_mask; i++)
@@ -1182,23 +1176,14 @@ static int __init dccp_init(void)
 		goto out_free_dccp_locks;
 	}
 
-	dccp_hashinfo.bhash2 = (struct inet_bind2_hashbucket *)
-		__get_free_pages(GFP_ATOMIC | __GFP_NOWARN, bhash_order);
-
-	if (!dccp_hashinfo.bhash2) {
-		DCCP_CRIT("Failed to allocate DCCP bind2 hash table");
-		goto out_free_dccp_bhash;
-	}
-
 	for (i = 0; i < dccp_hashinfo.bhash_size; i++) {
 		spin_lock_init(&dccp_hashinfo.bhash[i].lock);
 		INIT_HLIST_HEAD(&dccp_hashinfo.bhash[i].chain);
-		INIT_HLIST_HEAD(&dccp_hashinfo.bhash2[i].chain);
 	}
 
 	rc = dccp_mib_init();
 	if (rc)
-		goto out_free_dccp_bhash2;
+		goto out_free_dccp_bhash;
 
 	rc = dccp_ackvec_init();
 	if (rc)
@@ -1222,38 +1207,30 @@ out_ackvec_exit:
 	dccp_ackvec_exit();
 out_free_dccp_mib:
 	dccp_mib_exit();
-out_free_dccp_bhash2:
-	free_pages((unsigned long)dccp_hashinfo.bhash2, bhash_order);
 out_free_dccp_bhash:
 	free_pages((unsigned long)dccp_hashinfo.bhash, bhash_order);
 out_free_dccp_locks:
 	inet_ehash_locks_free(&dccp_hashinfo);
 out_free_dccp_ehash:
 	free_pages((unsigned long)dccp_hashinfo.ehash, ehash_order);
-out_free_bind2_bucket_cachep:
-	kmem_cache_destroy(dccp_hashinfo.bind2_bucket_cachep);
 out_free_bind_bucket_cachep:
 	kmem_cache_destroy(dccp_hashinfo.bind_bucket_cachep);
 out_free_hashinfo2:
 	inet_hashinfo2_free_mod(&dccp_hashinfo);
 out_fail:
 	dccp_hashinfo.bhash = NULL;
-	dccp_hashinfo.bhash2 = NULL;
 	dccp_hashinfo.ehash = NULL;
 	dccp_hashinfo.bind_bucket_cachep = NULL;
-	dccp_hashinfo.bind2_bucket_cachep = NULL;
 	return rc;
 }
 
 static void __exit dccp_fini(void)
 {
-	int bhash_order = get_order(dccp_hashinfo.bhash_size *
-				    sizeof(struct inet_bind_hashbucket));
-
 	ccid_cleanup_builtins();
 	dccp_mib_exit();
-	free_pages((unsigned long)dccp_hashinfo.bhash, bhash_order);
-	free_pages((unsigned long)dccp_hashinfo.bhash2, bhash_order);
+	free_pages((unsigned long)dccp_hashinfo.bhash,
+		   get_order(dccp_hashinfo.bhash_size *
+			     sizeof(struct inet_bind_hashbucket)));
 	free_pages((unsigned long)dccp_hashinfo.ehash,
 		   get_order((dccp_hashinfo.ehash_mask + 1) *
 			     sizeof(struct inet_ehash_bucket)));
diff --git a/net/ipv4/inet_connection_sock.c b/net/ipv4/inet_connection_sock.c
index c0b7e6c213601..53f5f956d9485 100644
--- a/net/ipv4/inet_connection_sock.c
+++ b/net/ipv4/inet_connection_sock.c
@@ -117,32 +117,6 @@ bool inet_rcv_saddr_any(const struct sock *sk)
 	return !sk->sk_rcv_saddr;
 }
 
-static bool use_bhash2_on_bind(const struct sock *sk)
-{
-#if IS_ENABLED(CONFIG_IPV6)
-	int addr_type;
-
-	if (sk->sk_family == AF_INET6) {
-		addr_type = ipv6_addr_type(&sk->sk_v6_rcv_saddr);
-		return addr_type != IPV6_ADDR_ANY &&
-			addr_type != IPV6_ADDR_MAPPED;
-	}
-#endif
-	return sk->sk_rcv_saddr != htonl(INADDR_ANY);
-}
-
-static u32 get_bhash2_nulladdr_hash(const struct sock *sk, struct net *net,
-				    int port)
-{
-#if IS_ENABLED(CONFIG_IPV6)
-	struct in6_addr nulladdr = {};
-
-	if (sk->sk_family == AF_INET6)
-		return ipv6_portaddr_hash(net, &nulladdr, port);
-#endif
-	return ipv4_portaddr_hash(net, 0, port);
-}
-
 void inet_get_local_port_range(struct net *net, int *low, int *high)
 {
 	unsigned int seq;
@@ -156,71 +130,16 @@ void inet_get_local_port_range(struct net *net, int *low, int *high)
 }
 EXPORT_SYMBOL(inet_get_local_port_range);
 
-static bool bind_conflict_exist(const struct sock *sk, struct sock *sk2,
-				kuid_t sk_uid, bool relax,
-				bool reuseport_cb_ok, bool reuseport_ok)
-{
-	int bound_dev_if2;
-
-	if (sk == sk2)
-		return false;
-
-	bound_dev_if2 = READ_ONCE(sk2->sk_bound_dev_if);
-
-	if (!sk->sk_bound_dev_if || !bound_dev_if2 ||
-	    sk->sk_bound_dev_if == bound_dev_if2) {
-		if (sk->sk_reuse && sk2->sk_reuse &&
-		    sk2->sk_state != TCP_LISTEN) {
-			if (!relax || (!reuseport_ok && sk->sk_reuseport &&
-				       sk2->sk_reuseport && reuseport_cb_ok &&
-				       (sk2->sk_state == TCP_TIME_WAIT ||
-					uid_eq(sk_uid, sock_i_uid(sk2)))))
-				return true;
-		} else if (!reuseport_ok || !sk->sk_reuseport ||
-			   !sk2->sk_reuseport || !reuseport_cb_ok ||
-			   (sk2->sk_state != TCP_TIME_WAIT &&
-			    !uid_eq(sk_uid, sock_i_uid(sk2)))) {
-			return true;
-		}
-	}
-	return false;
-}
-
-static bool check_bhash2_conflict(const struct sock *sk,
-				  struct inet_bind2_bucket *tb2, kuid_t sk_uid,
-				  bool relax, bool reuseport_cb_ok,
-				  bool reuseport_ok)
-{
-	struct sock *sk2;
-
-	sk_for_each_bound_bhash2(sk2, &tb2->owners) {
-		if (sk->sk_family == AF_INET && ipv6_only_sock(sk2))
-			continue;
-
-		if (bind_conflict_exist(sk, sk2, sk_uid, relax,
-					reuseport_cb_ok, reuseport_ok))
-			return true;
-	}
-	return false;
-}
-
-/* This should be called only when the corresponding inet_bind_bucket spinlock
- * is held
- */
-static int inet_csk_bind_conflict(const struct sock *sk, int port,
-				  struct inet_bind_bucket *tb,
-				  struct inet_bind2_bucket *tb2, /* may be null */
+static int inet_csk_bind_conflict(const struct sock *sk,
+				  const struct inet_bind_bucket *tb,
 				  bool relax, bool reuseport_ok)
 {
-	struct inet_hashinfo *hinfo = sk->sk_prot->h.hashinfo;
-	kuid_t uid = sock_i_uid((struct sock *)sk);
-	struct sock_reuseport *reuseport_cb;
-	struct inet_bind2_hashbucket *head2;
-	bool reuseport_cb_ok;
 	struct sock *sk2;
-	struct net *net;
-	int l3mdev;
-	u32 hash;
+	bool reuseport_cb_ok;
+	bool reuse = sk->sk_reuse;
+	bool reuseport = !!sk->sk_reuseport;
+	struct sock_reuseport *reuseport_cb;
+	kuid_t uid = sock_i_uid((struct sock *)sk);
 
 	rcu_read_lock();
 	reuseport_cb = rcu_dereference(sk->sk_reuseport_cb);
@@ -231,42 +150,40 @@ static int inet_csk_bind_conflict(const struct sock *sk, int port,
 	/*
 	 * Unlike other sk lookup places we do not check
 	 * for sk_net here, since _all_ the socks listed
-	 * in tb->owners and tb2->owners list belong
-	 * to the same net
+	 * in tb->owners list belong to the same net - the
+	 * one this bucket belongs to.
 	 */
 
-	if (!use_bhash2_on_bind(sk)) {
-		sk_for_each_bound(sk2, &tb->owners)
-			if (bind_conflict_exist(sk, sk2, uid, relax,
-						reuseport_cb_ok, reuseport_ok) &&
-			    inet_rcv_saddr_equal(sk, sk2, true))
-				return true;
+	sk_for_each_bound(sk2, &tb->owners) {
+		int bound_dev_if2;
 
-		return false;
+		if (sk == sk2)
+			continue;
+		bound_dev_if2 = READ_ONCE(sk2->sk_bound_dev_if);
+		if ((!sk->sk_bound_dev_if ||
+		     !bound_dev_if2 ||
+		     sk->sk_bound_dev_if == bound_dev_if2)) {
+			if (reuse && sk2->sk_reuse &&
+			    sk2->sk_state != TCP_LISTEN) {
+				if ((!relax ||
+				     (!reuseport_ok &&
+				      reuseport && sk2->sk_reuseport &&
+				      reuseport_cb_ok &&
+				      (sk2->sk_state == TCP_TIME_WAIT ||
+				       uid_eq(uid, sock_i_uid(sk2))))) &&
+				    inet_rcv_saddr_equal(sk, sk2, true))
+					break;
+			} else if (!reuseport_ok ||
+				   !reuseport || !sk2->sk_reuseport ||
+				   !reuseport_cb_ok ||
+				   (sk2->sk_state != TCP_TIME_WAIT &&
+				    !uid_eq(uid, sock_i_uid(sk2)))) {
+				if (inet_rcv_saddr_equal(sk, sk2, true))
+					break;
+			}
+		}
 	}
-
-	if (tb2 && check_bhash2_conflict(sk, tb2, uid, relax, reuseport_cb_ok,
-					 reuseport_ok))
-		return true;
-
-	net = sock_net(sk);
-
-	/* check there's no conflict with an existing IPV6_ADDR_ANY (if ipv6) or
-	 * INADDR_ANY (if ipv4) socket.
-	 */
-	hash = get_bhash2_nulladdr_hash(sk, net, port);
-	head2 = &hinfo->bhash2[hash & (hinfo->bhash_size - 1)];
-
-	l3mdev = inet_sk_bound_l3mdev(sk);
-	inet_bind_bucket_for_each(tb2, &head2->chain)
-		if (check_bind2_bucket_match_nulladdr(tb2, net, port, l3mdev, sk))
-			break;
-
-	if (tb2 && check_bhash2_conflict(sk, tb2, uid, relax, reuseport_cb_ok,
-					 reuseport_ok))
-		return true;
-
-	return false;
+	return sk2 != NULL;
 }
 
 /*
@@ -274,20 +191,16 @@ static int inet_csk_bind_conflict(const struct sock *sk, int port,
  * inet_bind_hashbucket lock held.
  */
 static struct inet_bind_hashbucket *
-inet_csk_find_open_port(struct sock *sk, struct inet_bind_bucket **tb_ret,
-			struct inet_bind2_bucket **tb2_ret,
-			struct inet_bind2_hashbucket **head2_ret, int *port_ret)
+inet_csk_find_open_port(struct sock *sk, struct inet_bind_bucket **tb_ret, int *port_ret)
 {
 	struct inet_hashinfo *hinfo = sk->sk_prot->h.hashinfo;
-	struct inet_bind2_hashbucket *head2;
+	int port = 0;
 	struct inet_bind_hashbucket *head;
 	struct net *net = sock_net(sk);
+	bool relax = false;
 	int i, low, high, attempt_half;
-	struct inet_bind2_bucket *tb2;
 	struct inet_bind_bucket *tb;
 	u32 remaining, offset;
-	bool relax = false;
-	int port = 0;
 	int l3mdev;
 
 	l3mdev = inet_sk_bound_l3mdev(sk);
@@ -326,12 +239,10 @@ other_parity_scan:
 		head = &hinfo->bhash[inet_bhashfn(net, port,
 						  hinfo->bhash_size)];
 		spin_lock_bh(&head->lock);
-		tb2 = inet_bind2_bucket_find(hinfo, net, port, l3mdev, sk,
-					     &head2);
 		inet_bind_bucket_for_each(tb, &head->chain)
-			if (check_bind_bucket_match(tb, net, port, l3mdev)) {
-				if (!inet_csk_bind_conflict(sk, port, tb, tb2,
-							    relax, false))
+			if (net_eq(ib_net(tb), net) && tb->l3mdev == l3mdev &&
+			    tb->port == port) {
+				if (!inet_csk_bind_conflict(sk, tb, relax, false))
 					goto success;
 				goto next_port;
 			}
@@ -361,8 +272,6 @@ next_port:
 success:
 	*port_ret = port;
 	*tb_ret = tb;
-	*tb2_ret = tb2;
-	*head2_ret = head2;
 	return head;
 }
 
@@ -458,81 +367,54 @@ int inet_csk_get_port(struct sock *sk, unsigned short snum)
 {
 	bool reuse = sk->sk_reuse && sk->sk_state != TCP_LISTEN;
 	struct inet_hashinfo *hinfo = sk->sk_prot->h.hashinfo;
-	bool bhash_created = false, bhash2_created = false;
-	struct inet_bind2_bucket *tb2 = NULL;
-	struct inet_bind2_hashbucket *head2;
-	struct inet_bind_bucket *tb = NULL;
+	int ret = 1, port = snum;
 	struct inet_bind_hashbucket *head;
 	struct net *net = sock_net(sk);
-	int ret = 1, port = snum;
-	bool found_port = false;
+	struct inet_bind_bucket *tb = NULL;
 	int l3mdev;
 
 	l3mdev = inet_sk_bound_l3mdev(sk);
 
 	if (!port) {
-		head = inet_csk_find_open_port(sk, &tb, &tb2, &head2, &port);
+		head = inet_csk_find_open_port(sk, &tb, &port);
 		if (!head)
 			return ret;
-		if (tb && tb2)
-			goto success;
-		found_port = true;
-	} else {
-		head = &hinfo->bhash[inet_bhashfn(net, port,
-						  hinfo->bhash_size)];
-		spin_lock_bh(&head->lock);
-		inet_bind_bucket_for_each(tb, &head->chain)
-			if (check_bind_bucket_match(tb, net, port, l3mdev))
-				break;
-
-		tb2 = inet_bind2_bucket_find(hinfo, net, port, l3mdev, sk,
-					     &head2);
-	}
-
-	if (!tb) {
-		tb = inet_bind_bucket_create(hinfo->bind_bucket_cachep, net,
-					     head, port, l3mdev);
 		if (!tb)
-			goto fail_unlock;
-		bhash_created = true;
-	}
-
-	if (!tb2) {
-		tb2 = inet_bind2_bucket_create(hinfo->bind2_bucket_cachep,
-					       net, head2, port, l3mdev, sk);
-		if (!tb2)
-			goto fail_unlock;
-		bhash2_created = true;
+			goto tb_not_found;
+		goto success;
 	}
-
-	/* If we had to find an open port, we already checked for conflicts */
-	if (!found_port && !hlist_empty(&tb->owners)) {
+	head = &hinfo->bhash[inet_bhashfn(net, port,
+					  hinfo->bhash_size)];
+	spin_lock_bh(&head->lock);
+	inet_bind_bucket_for_each(tb, &head->chain)
+		if (net_eq(ib_net(tb), net) && tb->l3mdev == l3mdev &&
+		    tb->port == port)
+			goto tb_found;
+tb_not_found:
+	tb = inet_bind_bucket_create(hinfo->bind_bucket_cachep,
+				     net, head, port, l3mdev);
+	if (!tb)
+		goto fail_unlock;
+tb_found:
+	if (!hlist_empty(&tb->owners)) {
 		if (sk->sk_reuse == SK_FORCE_REUSE)
 			goto success;
 
 		if ((tb->fastreuse > 0 && reuse) ||
 		    sk_reuseport_match(tb, sk))
 			goto success;
-		if (inet_csk_bind_conflict(sk, port, tb, tb2, true, true))
+		if (inet_csk_bind_conflict(sk, tb, true, true))
 			goto fail_unlock;
 	}
 success:
 	inet_csk_update_fastreuse(tb, sk);
 
 	if (!inet_csk(sk)->icsk_bind_hash)
-		inet_bind_hash(sk, tb, tb2, port);
+		inet_bind_hash(sk, tb, port);
 	WARN_ON(inet_csk(sk)->icsk_bind_hash != tb);
-	WARN_ON(inet_csk(sk)->icsk_bind2_hash != tb2);
 	ret = 0;
 
 fail_unlock:
-	if (ret) {
-		if (bhash_created)
-			inet_bind_bucket_destroy(hinfo->bind_bucket_cachep, tb);
-		if (bhash2_created)
-			inet_bind2_bucket_destroy(hinfo->bind2_bucket_cachep,
-						  tb2);
-	}
 	spin_unlock_bh(&head->lock);
 	return ret;
 }
@@ -1079,7 +961,6 @@ struct sock *inet_csk_clone_lock(const struct sock *sk,
 
 		inet_sk_set_state(newsk, TCP_SYN_RECV);
 		newicsk->icsk_bind_hash = NULL;
-		newicsk->icsk_bind2_hash = NULL;
 
 		inet_sk(newsk)->inet_dport = inet_rsk(req)->ir_rmt_port;
 		inet_sk(newsk)->inet_num = inet_rsk(req)->ir_num;
diff --git a/net/ipv4/inet_hashtables.c b/net/ipv4/inet_hashtables.c
index 545f91b6cb5e7..b9d995b5ce24c 100644
--- a/net/ipv4/inet_hashtables.c
+++ b/net/ipv4/inet_hashtables.c
@@ -81,41 +81,6 @@ struct inet_bind_bucket *inet_bind_bucket_create(struct kmem_cache *cachep,
 	return tb;
 }
 
-struct inet_bind2_bucket *inet_bind2_bucket_create(struct kmem_cache *cachep,
-						   struct net *net,
-						   struct inet_bind2_hashbucket *head,
-						   const unsigned short port,
-						   int l3mdev,
-						   const struct sock *sk)
-{
-	struct inet_bind2_bucket *tb = kmem_cache_alloc(cachep, GFP_ATOMIC);
-
-	if (tb) {
-		write_pnet(&tb->ib_net, net);
-		tb->l3mdev    = l3mdev;
-		tb->port      = port;
-#if IS_ENABLED(CONFIG_IPV6)
-		if (sk->sk_family == AF_INET6)
-			tb->v6_rcv_saddr = sk->sk_v6_rcv_saddr;
-		else
-#endif
-			tb->rcv_saddr = sk->sk_rcv_saddr;
-		INIT_HLIST_HEAD(&tb->owners);
-		hlist_add_head(&tb->node, &head->chain);
-	}
-	return tb;
-}
-
-static bool bind2_bucket_addr_match(struct inet_bind2_bucket *tb2, struct sock *sk)
-{
-#if IS_ENABLED(CONFIG_IPV6)
-	if (sk->sk_family == AF_INET6)
-		return ipv6_addr_equal(&tb2->v6_rcv_saddr,
-				       &sk->sk_v6_rcv_saddr);
-#endif
-	return tb2->rcv_saddr == sk->sk_rcv_saddr;
-}
-
 /*
  * Caller must hold hashbucket lock for this tb with local BH disabled
  */
@@ -127,25 +92,12 @@ void inet_bind_bucket_destroy(struct kmem_cache *cachep, struct inet_bind_bucket
 	}
 }
 
-/* Caller must hold the lock for the corresponding hashbucket in the bhash table
- * with local BH disabled
- */
-void inet_bind2_bucket_destroy(struct kmem_cache *cachep, struct inet_bind2_bucket *tb)
-{
-	if (hlist_empty(&tb->owners)) {
-		__hlist_del(&tb->node);
-		kmem_cache_free(cachep, tb);
-	}
-}
-
 void inet_bind_hash(struct sock *sk, struct inet_bind_bucket *tb,
-		    struct inet_bind2_bucket *tb2, const unsigned short snum)
+		    const unsigned short snum)
 {
 	inet_sk(sk)->inet_num = snum;
 	sk_add_bind_node(sk, &tb->owners);
 	inet_csk(sk)->icsk_bind_hash = tb;
-	sk_add_bind2_node(sk, &tb2->owners);
-	inet_csk(sk)->icsk_bind2_hash = tb2;
 }
 
 /*
@@ -157,7 +109,6 @@ static void __inet_put_port(struct sock *sk)
 	const int bhash = inet_bhashfn(sock_net(sk), inet_sk(sk)->inet_num,
 			hashinfo->bhash_size);
 	struct inet_bind_hashbucket *head = &hashinfo->bhash[bhash];
-	struct inet_bind2_bucket *tb2;
 	struct inet_bind_bucket *tb;
 
 	spin_lock(&head->lock);
@@ -166,13 +117,6 @@ static void __inet_put_port(struct sock *sk)
 	inet_csk(sk)->icsk_bind_hash = NULL;
 	inet_sk(sk)->inet_num = 0;
 	inet_bind_bucket_destroy(hashinfo->bind_bucket_cachep, tb);
-
-	if (inet_csk(sk)->icsk_bind2_hash) {
-		tb2 = inet_csk(sk)->icsk_bind2_hash;
-		__sk_del_bind2_node(sk);
-		inet_csk(sk)->icsk_bind2_hash = NULL;
-		inet_bind2_bucket_destroy(hashinfo->bind2_bucket_cachep, tb2);
-	}
 	spin_unlock(&head->lock);
 }
 
@@ -189,19 +133,14 @@ int __inet_inherit_port(const struct sock *sk, struct sock *child)
 	struct inet_hashinfo *table = sk->sk_prot->h.hashinfo;
 	unsigned short port = inet_sk(child)->inet_num;
 	const int bhash = inet_bhashfn(sock_net(sk), port,
-				       table->bhash_size);
+			table->bhash_size);
 	struct inet_bind_hashbucket *head = &table->bhash[bhash];
-	struct inet_bind2_hashbucket *head_bhash2;
-	bool created_inet_bind_bucket = false;
-	struct net *net = sock_net(sk);
-	struct inet_bind2_bucket *tb2;
 	struct inet_bind_bucket *tb;
 	int l3mdev;
 
 	spin_lock(&head->lock);
 	tb = inet_csk(sk)->icsk_bind_hash;
-	tb2 = inet_csk(sk)->icsk_bind2_hash;
-	if (unlikely(!tb || !tb2)) {
+	if (unlikely(!tb)) {
 		spin_unlock(&head->lock);
 		return -ENOENT;
 	}
@@ -214,45 +153,25 @@ int __inet_inherit_port(const struct sock *sk, struct sock *child)
 		 * as that of the child socket. We have to look up or
 		 * create a new bind bucket for the child here. */
 		inet_bind_bucket_for_each(tb, &head->chain) {
-			if (check_bind_bucket_match(tb, net, port, l3mdev))
+			if (net_eq(ib_net(tb), sock_net(sk)) &&
+			    tb->l3mdev == l3mdev && tb->port == port)
 				break;
 		}
 		if (!tb) {
 			tb = inet_bind_bucket_create(table->bind_bucket_cachep,
-						     net, head, port, l3mdev);
+						     sock_net(sk), head, port,
+						     l3mdev);
 			if (!tb) {
 				spin_unlock(&head->lock);
 				return -ENOMEM;
 			}
-			created_inet_bind_bucket = true;
 		}
 		inet_csk_update_fastreuse(tb, child);
-
-		goto bhash2_find;
-	} else if (!bind2_bucket_addr_match(tb2, child)) {
-		l3mdev = inet_sk_bound_l3mdev(sk);
-
-bhash2_find:
-		tb2 = inet_bind2_bucket_find(table, net, port, l3mdev, child,
-					     &head_bhash2);
-		if (!tb2) {
-			tb2 = inet_bind2_bucket_create(table->bind2_bucket_cachep,
-						       net, head_bhash2, port,
-						       l3mdev, child);
-			if (!tb2)
-				goto error;
-		}
 	}
-	inet_bind_hash(child, tb, tb2, port);
+	inet_bind_hash(child, tb, port);
 	spin_unlock(&head->lock);
 
 	return 0;
-
-error:
-	if (created_inet_bind_bucket)
-		inet_bind_bucket_destroy(table->bind_bucket_cachep, tb);
-	spin_unlock(&head->lock);
-	return -ENOMEM;
 }
 EXPORT_SYMBOL_GPL(__inet_inherit_port);
 
@@ -756,76 +675,6 @@ void inet_unhash(struct sock *sk)
 }
 EXPORT_SYMBOL_GPL(inet_unhash);
 
-static bool check_bind2_bucket_match(struct inet_bind2_bucket *tb,
-				     struct net *net, unsigned short port,
-				     int l3mdev, struct sock *sk)
-{
-#if IS_ENABLED(CONFIG_IPV6)
-	if (sk->sk_family == AF_INET6)
-		return net_eq(ib2_net(tb), net) && tb->port == port &&
-			tb->l3mdev == l3mdev &&
-			ipv6_addr_equal(&tb->v6_rcv_saddr, &sk->sk_v6_rcv_saddr);
-	else
-#endif
-		return net_eq(ib2_net(tb), net) && tb->port == port &&
-			tb->l3mdev == l3mdev && tb->rcv_saddr == sk->sk_rcv_saddr;
-}
-
-bool check_bind2_bucket_match_nulladdr(struct inet_bind2_bucket *tb,
-				       struct net *net, const unsigned short port,
-				       int l3mdev, const struct sock *sk)
-{
-#if IS_ENABLED(CONFIG_IPV6)
-	struct in6_addr nulladdr = {};
-
-	if (sk->sk_family == AF_INET6)
-		return net_eq(ib2_net(tb), net) && tb->port == port &&
-			tb->l3mdev == l3mdev &&
-			ipv6_addr_equal(&tb->v6_rcv_saddr, &nulladdr);
-	else
-#endif
-		return net_eq(ib2_net(tb), net) && tb->port == port &&
-			tb->l3mdev == l3mdev && tb->rcv_saddr == 0;
-}
-
-static struct inet_bind2_hashbucket *
-inet_bhashfn_portaddr(struct inet_hashinfo *hinfo, const struct sock *sk,
-		      const struct net *net, unsigned short port)
-{
-	u32 hash;
-
-#if IS_ENABLED(CONFIG_IPV6)
-	if (sk->sk_family == AF_INET6)
-		hash = ipv6_portaddr_hash(net, &sk->sk_v6_rcv_saddr, port);
-	else
-#endif
-		hash = ipv4_portaddr_hash(net, sk->sk_rcv_saddr, port);
-	return &hinfo->bhash2[hash & (hinfo->bhash_size - 1)];
-}
-
-/* This should only be called when the spinlock for the socket's corresponding
- * bind_hashbucket is held
- */
-struct inet_bind2_bucket *
-inet_bind2_bucket_find(struct inet_hashinfo *hinfo, struct net *net,
-		       const unsigned short port, int l3mdev, struct sock *sk,
-		       struct inet_bind2_hashbucket **head)
-{
-	struct inet_bind2_bucket *bhash2 = NULL;
-	struct inet_bind2_hashbucket *h;
-
-	h = inet_bhashfn_portaddr(hinfo, sk, net, port);
-	inet_bind_bucket_for_each(bhash2, &h->chain) {
-		if (check_bind2_bucket_match(bhash2, net, port, l3mdev, sk))
-			break;
-	}
-
-	if (head)
-		*head = h;
-
-	return bhash2;
-}
-
 /* RFC 6056 3.3.4.  Algorithm 4: Double-Hash Port Selection Algorithm
  * Note that we use 32bit integers (vs RFC 'short integers')
  * because 2^16 is not a multiple of num_ephemeral and this
@@ -846,13 +695,10 @@ int __inet_hash_connect(struct inet_timewait_death_row *death_row,
 {
 	struct inet_hashinfo *hinfo = death_row->hashinfo;
 	struct inet_timewait_sock *tw = NULL;
-	struct inet_bind2_hashbucket *head2;
 	struct inet_bind_hashbucket *head;
 	int port = inet_sk(sk)->inet_num;
 	struct net *net = sock_net(sk);
-	struct inet_bind2_bucket *tb2;
 	struct inet_bind_bucket *tb;
-	bool tb_created = false;
 	u32 remaining, offset;
 	int ret, i, low, high;
 	int l3mdev;
@@ -909,7 +755,8 @@ other_parity_scan:
 		 * the established check is already unique enough.
 		 */
 		inet_bind_bucket_for_each(tb, &head->chain) {
-			if (check_bind_bucket_match(tb, net, port, l3mdev)) {
+			if (net_eq(ib_net(tb), net) && tb->l3mdev == l3mdev &&
+			    tb->port == port) {
 				if (tb->fastreuse >= 0 ||
 				    tb->fastreuseport >= 0)
 					goto next_port;
@@ -927,7 +774,6 @@ other_parity_scan:
 			spin_unlock_bh(&head->lock);
 			return -ENOMEM;
 		}
-		tb_created = true;
 		tb->fastreuse = -1;
 		tb->fastreuseport = -1;
 		goto ok;
@@ -943,17 +789,6 @@ next_port:
 	return -EADDRNOTAVAIL;
 
 ok:
-	/* Find the corresponding tb2 bucket since we need to
-	 * add the socket to the bhash2 table as well
-	 */
-	tb2 = inet_bind2_bucket_find(hinfo, net, port, l3mdev, sk, &head2);
-	if (!tb2) {
-		tb2 = inet_bind2_bucket_create(hinfo->bind2_bucket_cachep, net,
-					       head2, port, l3mdev, sk);
-		if (!tb2)
-			goto error;
-	}
-
 	/* Here we want to add a little bit of randomness to the next source
 	 * port that will be chosen. We use a max() with a random here so that
 	 * on low contention the randomness is maximal and on high contention
@@ -963,7 +798,7 @@ ok:
 	WRITE_ONCE(table_perturb[index], READ_ONCE(table_perturb[index]) + i + 2);
 
 	/* Head lock still held and bh's disabled */
-	inet_bind_hash(sk, tb, tb2, port);
+	inet_bind_hash(sk, tb, port);
 	if (sk_unhashed(sk)) {
 		inet_sk(sk)->inet_sport = htons(port);
 		inet_ehash_nolisten(sk, (struct sock *)tw, NULL);
@@ -975,12 +810,6 @@ ok:
 		inet_twsk_deschedule_put(tw);
 	local_bh_enable();
 	return 0;
-
-error:
-	if (tb_created)
-		inet_bind_bucket_destroy(hinfo->bind_bucket_cachep, tb);
-	spin_unlock_bh(&head->lock);
-	return -ENOMEM;
 }
 
 /*
diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c
index 9984d23a7f3e1..028513d3e2a2b 100644
--- a/net/ipv4/tcp.c
+++ b/net/ipv4/tcp.c
@@ -4604,12 +4604,6 @@ void __init tcp_init(void)
 				  SLAB_HWCACHE_ALIGN | SLAB_PANIC |
 				  SLAB_ACCOUNT,
 				  NULL);
-	tcp_hashinfo.bind2_bucket_cachep =
-		kmem_cache_create("tcp_bind2_bucket",
-				  sizeof(struct inet_bind2_bucket), 0,
-				  SLAB_HWCACHE_ALIGN | SLAB_PANIC |
-				  SLAB_ACCOUNT,
-				  NULL);
 
 	/* Size and allocate the main established and bind bucket
 	 * hash tables.
@@ -4632,9 +4626,8 @@ void __init tcp_init(void)
 	if (inet_ehash_locks_alloc(&tcp_hashinfo))
 		panic("TCP: failed to alloc ehash_locks");
 	tcp_hashinfo.bhash =
-		alloc_large_system_hash("TCP bind bhash tables",
-					sizeof(struct inet_bind_hashbucket) +
-					sizeof(struct inet_bind2_hashbucket),
+		alloc_large_system_hash("TCP bind",
+					sizeof(struct inet_bind_hashbucket),
 					tcp_hashinfo.ehash_mask + 1,
 					17, /* one slot per 128 KB of memory */
 					0,
@@ -4643,12 +4636,9 @@ void __init tcp_init(void)
 					0,
 					64 * 1024);
 	tcp_hashinfo.bhash_size = 1U << tcp_hashinfo.bhash_size;
-	tcp_hashinfo.bhash2 =
-		(struct inet_bind2_hashbucket *)(tcp_hashinfo.bhash + tcp_hashinfo.bhash_size);
 	for (i = 0; i < tcp_hashinfo.bhash_size; i++) {
 		spin_lock_init(&tcp_hashinfo.bhash[i].lock);
 		INIT_HLIST_HEAD(&tcp_hashinfo.bhash[i].chain);
-		INIT_HLIST_HEAD(&tcp_hashinfo.bhash2[i].chain);
 	}
 
 
diff --git a/tools/testing/selftests/net/.gitignore b/tools/testing/selftests/net/.gitignore
index b984f8c8d523e..a29f796189347 100644
--- a/tools/testing/selftests/net/.gitignore
+++ b/tools/testing/selftests/net/.gitignore
@@ -37,4 +37,3 @@ gro
 ioam6_parser
 toeplitz
 cmsg_sender
-bind_bhash_test
diff --git a/tools/testing/selftests/net/Makefile b/tools/testing/selftests/net/Makefile
index 464df13831f24..7ea54af554909 100644
--- a/tools/testing/selftests/net/Makefile
+++ b/tools/testing/selftests/net/Makefile
@@ -59,7 +59,6 @@ TEST_GEN_FILES += toeplitz
 TEST_GEN_FILES += cmsg_sender
 TEST_GEN_FILES += stress_reuseport_listen
 TEST_PROGS += test_vxlan_vnifiltering.sh
-TEST_GEN_FILES += bind_bhash_test
 
 TEST_FILES := settings
 
@@ -70,5 +69,4 @@ include bpf/Makefile
 
 $(OUTPUT)/reuseport_bpf_numa: LDLIBS += -lnuma
 $(OUTPUT)/tcp_mmap: LDLIBS += -lpthread
-$(OUTPUT)/bind_bhash_test: LDLIBS += -lpthread
 $(OUTPUT)/tcp_inq: LDLIBS += -lpthread
diff --git a/tools/testing/selftests/net/bind_bhash_test.c b/tools/testing/selftests/net/bind_bhash_test.c
deleted file mode 100644
index 252e73754e766..0000000000000
--- a/tools/testing/selftests/net/bind_bhash_test.c
+++ /dev/null
@@ -1,119 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * This times how long it takes to bind to a port when the port already
- * has multiple sockets in its bhash table.
- *
- * In the setup(), we populate the port's bhash table with
- * MAX_THREADS * MAX_CONNECTIONS number of entries.
- */
-
-#include <unistd.h>
-#include <stdio.h>
-#include <netdb.h>
-#include <pthread.h>
-
-#define MAX_THREADS 600
-#define MAX_CONNECTIONS 40
-
-static const char *bind_addr = "::1";
-static const char *port;
-
-static int fd_array[MAX_THREADS][MAX_CONNECTIONS];
-
-static int bind_socket(int opt, const char *addr)
-{
-	struct addrinfo *res, hint = {};
-	int sock_fd, reuse = 1, err;
-
-	sock_fd = socket(AF_INET6, SOCK_STREAM, 0);
-	if (sock_fd < 0) {
-		perror("socket fd err");
-		return -1;
-	}
-
-	hint.ai_family = AF_INET6;
-	hint.ai_socktype = SOCK_STREAM;
-
-	err = getaddrinfo(addr, port, &hint, &res);
-	if (err) {
-		perror("getaddrinfo failed");
-		return -1;
-	}
-
-	if (opt) {
-		err = setsockopt(sock_fd, SOL_SOCKET, opt, &reuse, sizeof(reuse));
-		if (err) {
-			perror("setsockopt failed");
-			return -1;
-		}
-	}
-
-	err = bind(sock_fd, res->ai_addr, res->ai_addrlen);
-	if (err) {
-		perror("failed to bind to port");
-		return -1;
-	}
-
-	return sock_fd;
-}
-
-static void *setup(void *arg)
-{
-	int sock_fd, i;
-	int *array = (int *)arg;
-
-	for (i = 0; i < MAX_CONNECTIONS; i++) {
-		sock_fd = bind_socket(SO_REUSEADDR | SO_REUSEPORT, bind_addr);
-		if (sock_fd < 0)
-			return NULL;
-		array[i] = sock_fd;
-	}
-
-	return NULL;
-}
-
-int main(int argc, const char *argv[])
-{
-	int listener_fd, sock_fd, i, j;
-	pthread_t tid[MAX_THREADS];
-	clock_t begin, end;
-
-	if (argc != 2) {
-		printf("Usage: listener <port>\n");
-		return -1;
-	}
-
-	port = argv[1];
-
-	listener_fd = bind_socket(SO_REUSEADDR | SO_REUSEPORT, bind_addr);
-	if (listen(listener_fd, 100) < 0) {
-		perror("listen failed");
-		return -1;
-	}
-
-	/* Set up threads to populate the bhash table entry for the port */
-	for (i = 0; i < MAX_THREADS; i++)
-		pthread_create(&tid[i], NULL, setup, fd_array[i]);
-
-	for (i = 0; i < MAX_THREADS; i++)
-		pthread_join(tid[i], NULL);
-
-	begin = clock();
-
-	/* Bind to the same port on a different address */
-	sock_fd  = bind_socket(0, "2001:0db8:0:f101::1");
-
-	end = clock();
-
-	printf("time spent = %f\n", (double)(end - begin) / CLOCKS_PER_SEC);
-
-	/* clean up */
-	close(sock_fd);
-	close(listener_fd);
-	for (i = 0; i < MAX_THREADS; i++) {
-		for (j = 0; i < MAX_THREADS; i++)
-			close(fd_array[i][j]);
-	}
-
-	return 0;
-}
-- 
GitLab


From 2e7bf4a6af482f73f01245f08b4a953412c77070 Mon Sep 17 00:00:00 2001
From: Yang Yingliang <yangyingliang@huawei.com>
Date: Thu, 16 Jun 2022 14:29:17 +0800
Subject: [PATCH 0683/1731] net: axienet: add missing error return code in
 axienet_probe()

It should return error code in error path in axienet_probe().

Fixes: 00be43a74ca2 ("net: axienet: make the 64b addresable DMA depends on 64b archectures")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Link: https://lore.kernel.org/r/20220616062917.3601-1-yangyingliang@huawei.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index fa7bcd2c18928..1760930ec0c49 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -2039,6 +2039,7 @@ static int axienet_probe(struct platform_device *pdev)
 	}
 	if (!IS_ENABLED(CONFIG_64BIT) && lp->features & XAE_FEATURE_DMA_64BIT) {
 		dev_err(&pdev->dev, "64-bit addressable DMA is not compatible with 32-bit archecture\n");
+		ret = -EINVAL;
 		goto cleanup_clk;
 	}
 
-- 
GitLab


From ff672c67ee7635ca1e28fb13729e8ef0d1f08ce5 Mon Sep 17 00:00:00 2001
From: Jakub Sitnicki <jakub@cloudflare.com>
Date: Thu, 16 Jun 2022 18:20:36 +0200
Subject: [PATCH 0684/1731] bpf, x86: Fix tail call count offset calculation on
 bpf2bpf call

On x86-64 the tail call count is passed from one BPF function to another
through %rax. Additionally, on function entry, the tail call count value
is stored on stack right after the BPF program stack, due to register
shortage.

The stored count is later loaded from stack either when performing a tail
call - to check if we have not reached the tail call limit - or before
calling another BPF function call in order to pass it via %rax.

In the latter case, we miscalculate the offset at which the tail call count
was stored on function entry. The JIT does not take into account that the
allocated BPF program stack is always a multiple of 8 on x86, while the
actual stack depth does not have to be.

This leads to a load from an offset that belongs to the BPF stack, as shown
in the example below:

SEC("tc")
int entry(struct __sk_buff *skb)
{
	/* Have data on stack which size is not a multiple of 8 */
	volatile char arr[1] = {};
	return subprog_tail(skb);
}

int entry(struct __sk_buff * skb):
   0: (b4) w2 = 0
   1: (73) *(u8 *)(r10 -1) = r2
   2: (85) call pc+1#bpf_prog_ce2f79bb5f3e06dd_F
   3: (95) exit

int entry(struct __sk_buff * skb):
   0xffffffffa0201788:  nop    DWORD PTR [rax+rax*1+0x0]
   0xffffffffa020178d:  xor    eax,eax
   0xffffffffa020178f:  push   rbp
   0xffffffffa0201790:  mov    rbp,rsp
   0xffffffffa0201793:  sub    rsp,0x8
   0xffffffffa020179a:  push   rax
   0xffffffffa020179b:  xor    esi,esi
   0xffffffffa020179d:  mov    BYTE PTR [rbp-0x1],sil
   0xffffffffa02017a1:  mov    rax,QWORD PTR [rbp-0x9]	!!! tail call count
   0xffffffffa02017a8:  call   0xffffffffa02017d8       !!! is at rbp-0x10
   0xffffffffa02017ad:  leave
   0xffffffffa02017ae:  ret

Fix it by rounding up the BPF stack depth to a multiple of 8, when
calculating the tail call count offset on stack.

Fixes: ebf7d1f508a7 ("bpf, x64: rework pro/epilogue and tailcall handling in JIT")
Signed-off-by: Jakub Sitnicki <jakub@cloudflare.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com>
Acked-by: Daniel Borkmann <daniel@iogearbox.net>
Link: https://lore.kernel.org/bpf/20220616162037.535469-2-jakub@cloudflare.com
---
 arch/x86/net/bpf_jit_comp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c
index f298b18a9a3d1..c98b8c0ed3b83 100644
--- a/arch/x86/net/bpf_jit_comp.c
+++ b/arch/x86/net/bpf_jit_comp.c
@@ -1420,8 +1420,9 @@ st:			if (is_imm8(insn->off))
 		case BPF_JMP | BPF_CALL:
 			func = (u8 *) __bpf_call_base + imm32;
 			if (tail_call_reachable) {
+				/* mov rax, qword ptr [rbp - rounded_stack_depth - 8] */
 				EMIT3_off32(0x48, 0x8B, 0x85,
-					    -(bpf_prog->aux->stack_depth + 8));
+					    -round_up(bpf_prog->aux->stack_depth, 8) - 8);
 				if (!imm32 || emit_call(&prog, func, image + addrs[i - 1] + 7))
 					return -EINVAL;
 			} else {
-- 
GitLab


From 5e0b0a4c52d30bb09659446f40b77a692361600d Mon Sep 17 00:00:00 2001
From: Jakub Sitnicki <jakub@cloudflare.com>
Date: Thu, 16 Jun 2022 18:20:37 +0200
Subject: [PATCH 0685/1731] selftests/bpf: Test tail call counting with bpf2bpf
 and data on stack

Cover the case when tail call count needs to be passed from BPF function to
BPF function, and the caller has data on stack. Specifically when the size
of data allocated on BPF stack is not a multiple on 8.

Signed-off-by: Jakub Sitnicki <jakub@cloudflare.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Link: https://lore.kernel.org/bpf/20220616162037.535469-3-jakub@cloudflare.com
---
 .../selftests/bpf/prog_tests/tailcalls.c      | 55 +++++++++++++++++++
 .../selftests/bpf/progs/tailcall_bpf2bpf6.c   | 42 ++++++++++++++
 2 files changed, 97 insertions(+)
 create mode 100644 tools/testing/selftests/bpf/progs/tailcall_bpf2bpf6.c

diff --git a/tools/testing/selftests/bpf/prog_tests/tailcalls.c b/tools/testing/selftests/bpf/prog_tests/tailcalls.c
index c4da87ec3ba47..19c70880cfb3a 100644
--- a/tools/testing/selftests/bpf/prog_tests/tailcalls.c
+++ b/tools/testing/selftests/bpf/prog_tests/tailcalls.c
@@ -831,6 +831,59 @@ out:
 	bpf_object__close(obj);
 }
 
+#include "tailcall_bpf2bpf6.skel.h"
+
+/* Tail call counting works even when there is data on stack which is
+ * not aligned to 8 bytes.
+ */
+static void test_tailcall_bpf2bpf_6(void)
+{
+	struct tailcall_bpf2bpf6 *obj;
+	int err, map_fd, prog_fd, main_fd, data_fd, i, val;
+	LIBBPF_OPTS(bpf_test_run_opts, topts,
+		.data_in = &pkt_v4,
+		.data_size_in = sizeof(pkt_v4),
+		.repeat = 1,
+	);
+
+	obj = tailcall_bpf2bpf6__open_and_load();
+	if (!ASSERT_OK_PTR(obj, "open and load"))
+		return;
+
+	main_fd = bpf_program__fd(obj->progs.entry);
+	if (!ASSERT_GE(main_fd, 0, "entry prog fd"))
+		goto out;
+
+	map_fd = bpf_map__fd(obj->maps.jmp_table);
+	if (!ASSERT_GE(map_fd, 0, "jmp_table map fd"))
+		goto out;
+
+	prog_fd = bpf_program__fd(obj->progs.classifier_0);
+	if (!ASSERT_GE(prog_fd, 0, "classifier_0 prog fd"))
+		goto out;
+
+	i = 0;
+	err = bpf_map_update_elem(map_fd, &i, &prog_fd, BPF_ANY);
+	if (!ASSERT_OK(err, "jmp_table map update"))
+		goto out;
+
+	err = bpf_prog_test_run_opts(main_fd, &topts);
+	ASSERT_OK(err, "entry prog test run");
+	ASSERT_EQ(topts.retval, 0, "tailcall retval");
+
+	data_fd = bpf_map__fd(obj->maps.bss);
+	if (!ASSERT_GE(map_fd, 0, "bss map fd"))
+		goto out;
+
+	i = 0;
+	err = bpf_map_lookup_elem(data_fd, &i, &val);
+	ASSERT_OK(err, "bss map lookup");
+	ASSERT_EQ(val, 1, "done flag is set");
+
+out:
+	tailcall_bpf2bpf6__destroy(obj);
+}
+
 void test_tailcalls(void)
 {
 	if (test__start_subtest("tailcall_1"))
@@ -855,4 +908,6 @@ void test_tailcalls(void)
 		test_tailcall_bpf2bpf_4(false);
 	if (test__start_subtest("tailcall_bpf2bpf_5"))
 		test_tailcall_bpf2bpf_4(true);
+	if (test__start_subtest("tailcall_bpf2bpf_6"))
+		test_tailcall_bpf2bpf_6();
 }
diff --git a/tools/testing/selftests/bpf/progs/tailcall_bpf2bpf6.c b/tools/testing/selftests/bpf/progs/tailcall_bpf2bpf6.c
new file mode 100644
index 0000000000000..41ce83da78e8b
--- /dev/null
+++ b/tools/testing/selftests/bpf/progs/tailcall_bpf2bpf6.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/bpf.h>
+#include <bpf/bpf_helpers.h>
+
+#define __unused __attribute__((unused))
+
+struct {
+	__uint(type, BPF_MAP_TYPE_PROG_ARRAY);
+	__uint(max_entries, 1);
+	__uint(key_size, sizeof(__u32));
+	__uint(value_size, sizeof(__u32));
+} jmp_table SEC(".maps");
+
+int done = 0;
+
+SEC("tc")
+int classifier_0(struct __sk_buff *skb __unused)
+{
+	done = 1;
+	return 0;
+}
+
+static __noinline
+int subprog_tail(struct __sk_buff *skb)
+{
+	/* Don't propagate the constant to the caller */
+	volatile int ret = 1;
+
+	bpf_tail_call_static(skb, &jmp_table, 0);
+	return ret;
+}
+
+SEC("tc")
+int entry(struct __sk_buff *skb)
+{
+	/* Have data on stack which size is not a multiple of 8 */
+	volatile char arr[1] = {};
+
+	return subprog_tail(skb);
+}
+
+char __license[] SEC("license") = "GPL";
-- 
GitLab


From d36bdd77b9e6aa7f5cb7b0f11ebbab8e5febf10b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Mon, 13 Jun 2022 23:14:39 +0300
Subject: [PATCH 0686/1731] drm/i915: Implement w/a 22010492432 for adl-s
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

adl-s needs the combo PLL DCO fraction w/a as well.
Gets us slightly more accurate clock out of the PLL.

Cc: stable@vger.kernel.org
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220613201439.23341-1-ville.syrjala@linux.intel.com
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 64708e874b135..982e5b9456803 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2459,7 +2459,7 @@ static void icl_wrpll_params_populate(struct skl_wrpll_params *params,
 }
 
 /*
- * Display WA #22010492432: ehl, tgl, adl-p
+ * Display WA #22010492432: ehl, tgl, adl-s, adl-p
  * Program half of the nominal DCO divider fraction value.
  */
 static bool
@@ -2467,7 +2467,7 @@ ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
 {
 	return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
 		 IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
-		 IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&
+		 IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) &&
 		 i915->dpll.ref_clks.nssc == 38400;
 }
 
-- 
GitLab


From 12a29115be72dfc72372af9ded4bc4ae7113a729 Mon Sep 17 00:00:00 2001
From: Yu Liao <liaoyu15@huawei.com>
Date: Tue, 14 Jun 2022 20:02:35 +0800
Subject: [PATCH 0687/1731] selftests dma: fix compile error for
 dma_map_benchmark

When building selftests/dma:
$ make -C tools/testing/selftests TARGETS=dma
I hit the following compilation error:

dma_map_benchmark.c:13:10: fatal error: linux/map_benchmark.h: No such file or directory
 #include <linux/map_benchmark.h>
          ^~~~~~~~~~~~~~~~~~~~~~~

dma/Makefile does not include the map_benchmark.h path, so add
more including path, and fix include order in dma_map_benchmark.c

Fixes: 8ddde07a3d28 ("dma-mapping: benchmark: extract a common header file for map_benchmark definition")
Signed-off-by: Yu Liao <liaoyu15@huawei.com>
Tested-by: Shuah Khan <skhan@linuxfoundation.org>
Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
---
 tools/testing/selftests/dma/Makefile            | 1 +
 tools/testing/selftests/dma/dma_map_benchmark.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/tools/testing/selftests/dma/Makefile b/tools/testing/selftests/dma/Makefile
index aa8e8b5b3864e..cd8c5ece1cba4 100644
--- a/tools/testing/selftests/dma/Makefile
+++ b/tools/testing/selftests/dma/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 CFLAGS += -I../../../../usr/include/
+CFLAGS += -I../../../../include/
 
 TEST_GEN_PROGS := dma_map_benchmark
 
diff --git a/tools/testing/selftests/dma/dma_map_benchmark.c b/tools/testing/selftests/dma/dma_map_benchmark.c
index c3b3c09e995e8..5c997f17fcbdb 100644
--- a/tools/testing/selftests/dma/dma_map_benchmark.c
+++ b/tools/testing/selftests/dma/dma_map_benchmark.c
@@ -10,8 +10,8 @@
 #include <unistd.h>
 #include <sys/ioctl.h>
 #include <sys/mman.h>
-#include <linux/map_benchmark.h>
 #include <linux/types.h>
+#include <linux/map_benchmark.h>
 
 #define NSEC_PER_MSEC	1000000L
 
-- 
GitLab


From 3084a4ec7f9bb1ec90036cfd01b1abadc5dd4fb2 Mon Sep 17 00:00:00 2001
From: Ding Xiang <dingxiang@cmss.chinamobile.com>
Date: Wed, 15 Jun 2022 17:36:29 +0800
Subject: [PATCH 0688/1731] selftests: vm: Fix resource leak when return error

When return on an error path, file handle need to be closed
to prevent resource leak

Signed-off-by: Ding Xiang <dingxiang@cmss.chinamobile.com>
Reviewed-by: Shuah Khan <skhan@linuxfoundation.org>
Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
---
 tools/testing/selftests/vm/ksm_tests.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tools/testing/selftests/vm/ksm_tests.c b/tools/testing/selftests/vm/ksm_tests.c
index 2fcf24312da88..f5e4e0bbd0815 100644
--- a/tools/testing/selftests/vm/ksm_tests.c
+++ b/tools/testing/selftests/vm/ksm_tests.c
@@ -54,6 +54,7 @@ static int ksm_write_sysfs(const char *file_path, unsigned long val)
 	}
 	if (fprintf(f, "%lu", val) < 0) {
 		perror("fprintf");
+		fclose(f);
 		return 1;
 	}
 	fclose(f);
@@ -72,6 +73,7 @@ static int ksm_read_sysfs(const char *file_path, unsigned long *val)
 	}
 	if (fscanf(f, "%lu", val) != 1) {
 		perror("fscanf");
+		fclose(f);
 		return 1;
 	}
 	fclose(f);
-- 
GitLab


From 14dc7a18abbe4176f5626c13c333670da8e06aa1 Mon Sep 17 00:00:00 2001
From: Bart Van Assche <bvanassche@acm.org>
Date: Wed, 15 Jun 2022 14:00:04 -0700
Subject: [PATCH 0689/1731] block: Fix handling of offline queues in
 blk_mq_alloc_request_hctx()

This patch prevents that test nvme/004 triggers the following:

UBSAN: array-index-out-of-bounds in block/blk-mq.h:135:9
index 512 is out of range for type 'long unsigned int [512]'
Call Trace:
 show_stack+0x52/0x58
 dump_stack_lvl+0x49/0x5e
 dump_stack+0x10/0x12
 ubsan_epilogue+0x9/0x3b
 __ubsan_handle_out_of_bounds.cold+0x44/0x49
 blk_mq_alloc_request_hctx+0x304/0x310
 __nvme_submit_sync_cmd+0x70/0x200 [nvme_core]
 nvmf_connect_io_queue+0x23e/0x2a0 [nvme_fabrics]
 nvme_loop_connect_io_queues+0x8d/0xb0 [nvme_loop]
 nvme_loop_create_ctrl+0x58e/0x7d0 [nvme_loop]
 nvmf_create_ctrl+0x1d7/0x4d0 [nvme_fabrics]
 nvmf_dev_write+0xae/0x111 [nvme_fabrics]
 vfs_write+0x144/0x560
 ksys_write+0xb7/0x140
 __x64_sys_write+0x42/0x50
 do_syscall_64+0x35/0x80
 entry_SYSCALL_64_after_hwframe+0x44/0xae

Cc: Christoph Hellwig <hch@lst.de>
Cc: Ming Lei <ming.lei@redhat.com>
Fixes: 20e4d8139319 ("blk-mq: simplify queue mapping & schedule with each possisble CPU")
Signed-off-by: Bart Van Assche <bvanassche@acm.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Ming Lei <ming.lei@redhat.com>
Link: https://lore.kernel.org/r/20220615210004.1031820-1-bvanassche@acm.org
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 block/blk-mq.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/block/blk-mq.c b/block/blk-mq.c
index e9bf950983c71..26a7f802d7eec 100644
--- a/block/blk-mq.c
+++ b/block/blk-mq.c
@@ -579,6 +579,8 @@ struct request *blk_mq_alloc_request_hctx(struct request_queue *q,
 	if (!blk_mq_hw_queue_mapped(data.hctx))
 		goto out_queue_exit;
 	cpu = cpumask_first_and(data.hctx->cpumask, cpu_online_mask);
+	if (cpu >= nr_cpu_ids)
+		goto out_queue_exit;
 	data.ctx = __blk_mq_get_ctx(q, cpu);
 
 	if (!q->elevator)
-- 
GitLab


From 5fd7a84a09e640016fe106dd3e992f5210e23dc7 Mon Sep 17 00:00:00 2001
From: Ming Lei <ming.lei@redhat.com>
Date: Thu, 16 Jun 2022 09:43:59 +0800
Subject: [PATCH 0690/1731] blk-mq: protect q->elevator by ->sysfs_lock in
 blk_mq_elv_switch_none

elevator can be tore down by sysfs switch interface or disk release, so
hold ->sysfs_lock before referring to q->elevator, then potential
use-after-free can be avoided.

Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Ming Lei <ming.lei@redhat.com>
Link: https://lore.kernel.org/r/20220616014401.817001-2-ming.lei@redhat.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 block/blk-mq.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/block/blk-mq.c b/block/blk-mq.c
index 26a7f802d7eec..c13d03b2e17c6 100644
--- a/block/blk-mq.c
+++ b/block/blk-mq.c
@@ -4440,12 +4440,14 @@ static bool blk_mq_elv_switch_none(struct list_head *head,
 	if (!qe)
 		return false;
 
+	/* q->elevator needs protection from ->sysfs_lock */
+	mutex_lock(&q->sysfs_lock);
+
 	INIT_LIST_HEAD(&qe->node);
 	qe->q = q;
 	qe->type = q->elevator->type;
 	list_add(&qe->node, head);
 
-	mutex_lock(&q->sysfs_lock);
 	/*
 	 * After elevator_switch_mq, the previous elevator_queue will be
 	 * released by elevator_release. The reference of the io scheduler
-- 
GitLab


From 4d337cebcb1c27d9b48c48b9a98e939d4552d584 Mon Sep 17 00:00:00 2001
From: Ming Lei <ming.lei@redhat.com>
Date: Thu, 16 Jun 2022 09:44:00 +0800
Subject: [PATCH 0691/1731] blk-mq: avoid to touch q->elevator without any
 protection

q->elevator is referred in blk_mq_has_sqsched() without any protection,
no .q_usage_counter is held, no queue srcu and rcu read lock is held,
so potential use-after-free may be triggered.

Fix the issue by adding one queue flag for checking if the elevator
uses single queue style dispatch. Meantime the elevator feature flag
of ELEVATOR_F_MQ_AWARE isn't needed any more.

Cc: Jan Kara <jack@suse.cz>
Signed-off-by: Ming Lei <ming.lei@redhat.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Link: https://lore.kernel.org/r/20220616014401.817001-3-ming.lei@redhat.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 block/bfq-iosched.c    |  3 +++
 block/blk-mq-sched.c   |  1 +
 block/blk-mq.c         | 18 ++----------------
 block/kyber-iosched.c  |  3 ++-
 block/mq-deadline.c    |  3 +++
 include/linux/blkdev.h |  4 ++--
 6 files changed, 13 insertions(+), 19 deletions(-)

diff --git a/block/bfq-iosched.c b/block/bfq-iosched.c
index 0d46cb728bbfa..caa55a5624bcc 100644
--- a/block/bfq-iosched.c
+++ b/block/bfq-iosched.c
@@ -7188,6 +7188,9 @@ static int bfq_init_queue(struct request_queue *q, struct elevator_type *e)
 	bfq_init_root_group(bfqd->root_group, bfqd);
 	bfq_init_entity(&bfqd->oom_bfqq.entity, bfqd->root_group);
 
+	/* We dispatch from request queue wide instead of hw queue */
+	blk_queue_flag_set(QUEUE_FLAG_SQ_SCHED, q);
+
 	wbt_disable_default(q);
 	return 0;
 
diff --git a/block/blk-mq-sched.c b/block/blk-mq-sched.c
index 9e56a69422b65..eb3c65a213625 100644
--- a/block/blk-mq-sched.c
+++ b/block/blk-mq-sched.c
@@ -564,6 +564,7 @@ int blk_mq_init_sched(struct request_queue *q, struct elevator_type *e)
 	int ret;
 
 	if (!e) {
+		blk_queue_flag_clear(QUEUE_FLAG_SQ_SCHED, q);
 		q->elevator = NULL;
 		q->nr_requests = q->tag_set->queue_depth;
 		return 0;
diff --git a/block/blk-mq.c b/block/blk-mq.c
index c13d03b2e17c6..4cdb08a709122 100644
--- a/block/blk-mq.c
+++ b/block/blk-mq.c
@@ -2142,20 +2142,6 @@ void blk_mq_run_hw_queue(struct blk_mq_hw_ctx *hctx, bool async)
 }
 EXPORT_SYMBOL(blk_mq_run_hw_queue);
 
-/*
- * Is the request queue handled by an IO scheduler that does not respect
- * hardware queues when dispatching?
- */
-static bool blk_mq_has_sqsched(struct request_queue *q)
-{
-	struct elevator_queue *e = q->elevator;
-
-	if (e && e->type->ops.dispatch_request &&
-	    !(e->type->elevator_features & ELEVATOR_F_MQ_AWARE))
-		return true;
-	return false;
-}
-
 /*
  * Return prefered queue to dispatch from (if any) for non-mq aware IO
  * scheduler.
@@ -2188,7 +2174,7 @@ void blk_mq_run_hw_queues(struct request_queue *q, bool async)
 	unsigned long i;
 
 	sq_hctx = NULL;
-	if (blk_mq_has_sqsched(q))
+	if (blk_queue_sq_sched(q))
 		sq_hctx = blk_mq_get_sq_hctx(q);
 	queue_for_each_hw_ctx(q, hctx, i) {
 		if (blk_mq_hctx_stopped(hctx))
@@ -2216,7 +2202,7 @@ void blk_mq_delay_run_hw_queues(struct request_queue *q, unsigned long msecs)
 	unsigned long i;
 
 	sq_hctx = NULL;
-	if (blk_mq_has_sqsched(q))
+	if (blk_queue_sq_sched(q))
 		sq_hctx = blk_mq_get_sq_hctx(q);
 	queue_for_each_hw_ctx(q, hctx, i) {
 		if (blk_mq_hctx_stopped(hctx))
diff --git a/block/kyber-iosched.c b/block/kyber-iosched.c
index 70ff2a599ef61..8f7c745b4a57c 100644
--- a/block/kyber-iosched.c
+++ b/block/kyber-iosched.c
@@ -421,6 +421,8 @@ static int kyber_init_sched(struct request_queue *q, struct elevator_type *e)
 
 	blk_stat_enable_accounting(q);
 
+	blk_queue_flag_clear(QUEUE_FLAG_SQ_SCHED, q);
+
 	eq->elevator_data = kqd;
 	q->elevator = eq;
 
@@ -1033,7 +1035,6 @@ static struct elevator_type kyber_sched = {
 #endif
 	.elevator_attrs = kyber_sched_attrs,
 	.elevator_name = "kyber",
-	.elevator_features = ELEVATOR_F_MQ_AWARE,
 	.elevator_owner = THIS_MODULE,
 };
 
diff --git a/block/mq-deadline.c b/block/mq-deadline.c
index 6ed602b2f80a5..1a9e835e816cd 100644
--- a/block/mq-deadline.c
+++ b/block/mq-deadline.c
@@ -642,6 +642,9 @@ static int dd_init_sched(struct request_queue *q, struct elevator_type *e)
 	spin_lock_init(&dd->lock);
 	spin_lock_init(&dd->zone_lock);
 
+	/* We dispatch from request queue wide instead of hw queue */
+	blk_queue_flag_set(QUEUE_FLAG_SQ_SCHED, q);
+
 	q->elevator = eq;
 	return 0;
 
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index 608d577734c29..bb6e3c31b3b7b 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -575,6 +575,7 @@ struct request_queue {
 #define QUEUE_FLAG_RQ_ALLOC_TIME 27	/* record rq->alloc_time_ns */
 #define QUEUE_FLAG_HCTX_ACTIVE	28	/* at least one blk-mq hctx is active */
 #define QUEUE_FLAG_NOWAIT       29	/* device supports NOWAIT */
+#define QUEUE_FLAG_SQ_SCHED     30	/* single queue style io dispatch */
 
 #define QUEUE_FLAG_MQ_DEFAULT	((1 << QUEUE_FLAG_IO_STAT) |		\
 				 (1 << QUEUE_FLAG_SAME_COMP) |		\
@@ -616,6 +617,7 @@ bool blk_queue_flag_test_and_set(unsigned int flag, struct request_queue *q);
 #define blk_queue_pm_only(q)	atomic_read(&(q)->pm_only)
 #define blk_queue_registered(q)	test_bit(QUEUE_FLAG_REGISTERED, &(q)->queue_flags)
 #define blk_queue_nowait(q)	test_bit(QUEUE_FLAG_NOWAIT, &(q)->queue_flags)
+#define blk_queue_sq_sched(q)	test_bit(QUEUE_FLAG_SQ_SCHED, &(q)->queue_flags)
 
 extern void blk_set_pm_only(struct request_queue *q);
 extern void blk_clear_pm_only(struct request_queue *q);
@@ -1006,8 +1008,6 @@ void disk_set_independent_access_ranges(struct gendisk *disk,
  */
 /* Supports zoned block devices sequential write constraint */
 #define ELEVATOR_F_ZBD_SEQ_WRITE	(1U << 0)
-/* Supports scheduling on multiple hardware queues */
-#define ELEVATOR_F_MQ_AWARE		(1U << 1)
 
 extern void blk_queue_required_elevator_features(struct request_queue *q,
 						 unsigned int features);
-- 
GitLab


From 6cfeadbff3f8905f2854735ebb88e581402c16c4 Mon Sep 17 00:00:00 2001
From: Ming Lei <ming.lei@redhat.com>
Date: Thu, 16 Jun 2022 09:44:01 +0800
Subject: [PATCH 0692/1731] blk-mq: don't clear flush_rq from tags->rqs[]

commit 364b61818f65 ("blk-mq: clearing flush request reference in
tags->rqs[]") is added to clear the to-be-free flush request from
tags->rqs[] for avoiding use-after-free on the flush rq.

Yu Kuai reported that blk_mq_clear_flush_rq_mapping() slows down boot time
by ~8s because running scsi probe which may create and remove lots of
unpresent LUNs on megaraid-sas which uses BLK_MQ_F_TAG_HCTX_SHARED and
each request queue has lots of hw queues.

Improve the situation by not running blk_mq_clear_flush_rq_mapping if
disk isn't added when there can't be any flush request issued.

Reviewed-by: Christoph Hellwig <hch@lst.de>
Reported-by: Yu Kuai <yukuai3@huawei.com>
Signed-off-by: Ming Lei <ming.lei@redhat.com>
Link: https://lore.kernel.org/r/20220616014401.817001-4-ming.lei@redhat.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 block/blk-mq.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/block/blk-mq.c b/block/blk-mq.c
index 4cdb08a709122..33145ba52c960 100644
--- a/block/blk-mq.c
+++ b/block/blk-mq.c
@@ -3431,8 +3431,9 @@ static void blk_mq_exit_hctx(struct request_queue *q,
 	if (blk_mq_hw_queue_mapped(hctx))
 		blk_mq_tag_idle(hctx);
 
-	blk_mq_clear_flush_rq_mapping(set->tags[hctx_idx],
-			set->queue_depth, flush_rq);
+	if (blk_queue_init_done(q))
+		blk_mq_clear_flush_rq_mapping(set->tags[hctx_idx],
+				set->queue_depth, flush_rq);
 	if (set->ops->exit_request)
 		set->ops->exit_request(set, flush_rq, hctx_idx);
 
-- 
GitLab


From b0017602fdf6bd3f344dd49eaee8b6ffeed6dbac Mon Sep 17 00:00:00 2001
From: Dominique Martinet <asmadeus@codewreck.org>
Date: Tue, 14 Jun 2022 12:19:02 +0900
Subject: [PATCH 0693/1731] 9p: fix EBADF errors in cached mode

cached operations sometimes need to do invalid operations (e.g. read
on a write only file)
Historic fscache had added a "writeback fid", a special handle opened
RW as root, for this. The conversion to new fscache missed that bit.

This commit reinstates a slightly lesser variant of the original code
that uses the writeback fid for partial pages backfills if the regular
user fid had been open as WRONLY, and thus would lack read permissions.

Link: https://lkml.kernel.org/r/20220614033802.1606738-1-asmadeus@codewreck.org
Fixes: eb497943fa21 ("9p: Convert to using the netfs helper lib to do reads and caching")
Cc: stable@vger.kernel.org
Cc: David Howells <dhowells@redhat.com>
Reported-By: Christian Schoenebeck <linux_oss@crudebyte.com>
Reviewed-by: Christian Schoenebeck <linux_oss@crudebyte.com>
Tested-by: Christian Schoenebeck <linux_oss@crudebyte.com>
Signed-off-by: Dominique Martinet <asmadeus@codewreck.org>
---
 fs/9p/vfs_addr.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/fs/9p/vfs_addr.c b/fs/9p/vfs_addr.c
index a8f512b44a851..d0833fa69faf1 100644
--- a/fs/9p/vfs_addr.c
+++ b/fs/9p/vfs_addr.c
@@ -58,8 +58,21 @@ static void v9fs_issue_read(struct netfs_io_subrequest *subreq)
  */
 static int v9fs_init_request(struct netfs_io_request *rreq, struct file *file)
 {
+	struct inode *inode = file_inode(file);
+	struct v9fs_inode *v9inode = V9FS_I(inode);
 	struct p9_fid *fid = file->private_data;
 
+	BUG_ON(!fid);
+
+	/* we might need to read from a fid that was opened write-only
+	 * for read-modify-write of page cache, use the writeback fid
+	 * for that */
+	if (rreq->origin == NETFS_READ_FOR_WRITE &&
+			(fid->mode & O_ACCMODE) == O_WRONLY) {
+		fid = v9inode->writeback_fid;
+		BUG_ON(!fid);
+	}
+
 	refcount_inc(&fid->count);
 	rreq->netfs_priv = fid;
 	return 0;
-- 
GitLab


From 21f356f990262329bc387910355833378524fe9f Mon Sep 17 00:00:00 2001
From: Heiko Stuebner <heiko@sntech.de>
Date: Thu, 26 May 2022 22:56:45 +0200
Subject: [PATCH 0694/1731] riscv: fix dependency for t-head errata

alternatives only work correctly on non-xip-kernels and while the
selected alternative-symbol has the correct dependency the symbol
selecting it also needs that dependency.

So add the missing dependency to the T-Head errata Kconfig symbol.

Reported-by: kernel test robot <yujie.liu@intel.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20220526205646.258337-5-heiko@sntech.de
Fixes: a35707c3d850 ("riscv: add memory-type errata for T-Head")
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 arch/riscv/Kconfig.erratas | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas
index ebfcd5cc6eaf2..457ac72c9b36d 100644
--- a/arch/riscv/Kconfig.erratas
+++ b/arch/riscv/Kconfig.erratas
@@ -35,6 +35,7 @@ config ERRATA_SIFIVE_CIP_1200
 
 config ERRATA_THEAD
 	bool "T-HEAD errata"
+	depends on !XIP_KERNEL
 	select RISCV_ALTERNATIVE
 	help
 	  All T-HEAD errata Kconfig depend on this Kconfig. Disabling
-- 
GitLab


From 237c0ee4742b6462cb41cdb3fda1ca55011e4aaf Mon Sep 17 00:00:00 2001
From: Heiko Stuebner <heiko@sntech.de>
Date: Thu, 26 May 2022 22:56:42 +0200
Subject: [PATCH 0695/1731] riscv: drop cpufeature_apply_feature tracking
 variable

The variable was tracking which feature patches got applied
but that information was never actually used - and thus resulted
in a warning as well.

Drop the variable.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Guo Ren <guoren@kernel.org>
Link: https://lore.kernel.org/r/20220526205646.258337-2-heiko@sntech.de
Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support")
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 arch/riscv/kernel/cpufeature.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index a6f62a6d1edd9..12b05ce164bbe 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -293,7 +293,6 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
 						  unsigned int stage)
 {
 	u32 cpu_req_feature = cpufeature_probe(stage);
-	u32 cpu_apply_feature = 0;
 	struct alt_entry *alt;
 	u32 tmp;
 
@@ -307,10 +306,8 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
 		}
 
 		tmp = (1U << alt->errata_id);
-		if (cpu_req_feature & tmp) {
+		if (cpu_req_feature & tmp)
 			patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len);
-			cpu_apply_feature |= tmp;
-		}
 	}
 }
 #endif
-- 
GitLab


From 924cbb8cbe3460ea192e6243017ceb0ceb255b1b Mon Sep 17 00:00:00 2001
From: Heiko Stuebner <heiko@sntech.de>
Date: Thu, 26 May 2022 22:56:43 +0200
Subject: [PATCH 0696/1731] riscv: Improve description for RISCV_ISA_SVPBMT
 Kconfig symbol

This improves the symbol's description to make it easier for
people to understand what it is about.

Suggested-by: Christoph Hellwig <hch@lst.de>
Suggested-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Guo Ren <guoren@kernel.org>
Link: https://lore.kernel.org/r/20220526205646.258337-3-heiko@sntech.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 arch/riscv/Kconfig | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index c22f581559484..32ffef9f6e5b4 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -364,8 +364,13 @@ config RISCV_ISA_SVPBMT
 	select RISCV_ALTERNATIVE
 	default y
 	help
-	   Adds support to dynamically detect the presence of the SVPBMT extension
-	   (Supervisor-mode: page-based memory types) and enable its usage.
+	   Adds support to dynamically detect the presence of the SVPBMT
+	   ISA-extension (Supervisor-mode: page-based memory types) and
+	   enable its usage.
+
+	   The memory type for a page contains a combination of attributes
+	   that indicate the cacheability, idempotency, and ordering
+	   properties for access to that page.
 
 	   The SVPBMT extension is only available on 64Bit cpus.
 
-- 
GitLab


From b96f3cab59654ee2c30e6adf0b1c13cf8c0850fa Mon Sep 17 00:00:00 2001
From: Bart Van Assche <bvanassche@acm.org>
Date: Mon, 13 Jun 2022 09:32:34 -0700
Subject: [PATCH 0697/1731] block/bfq: Enable I/O statistics

BFQ uses io_start_time_ns. That member variable is only set if I/O
statistics are enabled. Hence this patch that enables I/O statistics
at the time BFQ is associated with a request queue.

Compile-tested only.

Reported-by: Cixi Geng <cixi.geng1@unisoc.com>
Cc: Cixi Geng <cixi.geng1@unisoc.com>
Cc: Yu Kuai <yukuai3@huawei.com>
Cc: Paolo Valente <paolo.valente@unimore.it>
Reviewed-by: Jan Kara <jack@suse.cz>
Signed-off-by: Bart Van Assche <bvanassche@acm.org>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 block/bfq-iosched.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/block/bfq-iosched.c b/block/bfq-iosched.c
index caa55a5624bcc..e6d7e6b01a05c 100644
--- a/block/bfq-iosched.c
+++ b/block/bfq-iosched.c
@@ -7046,6 +7046,7 @@ static void bfq_exit_queue(struct elevator_queue *e)
 	spin_unlock_irq(&bfqd->lock);
 #endif
 
+	blk_stat_disable_accounting(bfqd->queue);
 	wbt_enable_default(bfqd->queue);
 
 	kfree(bfqd);
@@ -7192,6 +7193,8 @@ static int bfq_init_queue(struct request_queue *q, struct elevator_type *e)
 	blk_queue_flag_set(QUEUE_FLAG_SQ_SCHED, q);
 
 	wbt_disable_default(q);
+	blk_stat_enable_accounting(q);
+
 	return 0;
 
 out_free:
-- 
GitLab


From 9b4d5c01eb234f66a15a746b1c73e10209edb199 Mon Sep 17 00:00:00 2001
From: Joel Savitz <jsavitz@redhat.com>
Date: Thu, 9 Jun 2022 16:32:17 -0400
Subject: [PATCH 0698/1731] selftests: make use of GUP_TEST_FILE macro

Commit 17de1e559cf1 ("selftests: clarify common error when running
gup_test") had most of its hunks dropped due to a conflict with another
patch accepted into Linux around the same time that implemented the same
behavior as a subset of other changes.

However, the remaining hunk defines the GUP_TEST_FILE macro without
making use of it. This patch makes use of the macro in the two relevant
places.

Furthermore, the above mentioned commit's log message erroneously describes
the changes that were dropped from the patch.

This patch corrects the record.

Fixes: 17de1e559cf1 ("selftests: clarify common error when running gup_test")

Signed-off-by: Joel Savitz <jsavitz@redhat.com>
Reviewed-by: Shuah Khan <skhan@linuxfoundation.org>
Acked-by: Nico Pache <npache@redhat.com>
Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
---
 tools/testing/selftests/vm/gup_test.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/testing/selftests/vm/gup_test.c b/tools/testing/selftests/vm/gup_test.c
index 6bb36ca71cb50..a309876d832fb 100644
--- a/tools/testing/selftests/vm/gup_test.c
+++ b/tools/testing/selftests/vm/gup_test.c
@@ -209,7 +209,7 @@ int main(int argc, char **argv)
 	if (write)
 		gup.gup_flags |= FOLL_WRITE;
 
-	gup_fd = open("/sys/kernel/debug/gup_test", O_RDWR);
+	gup_fd = open(GUP_TEST_FILE, O_RDWR);
 	if (gup_fd == -1) {
 		switch (errno) {
 		case EACCES:
@@ -224,7 +224,7 @@ int main(int argc, char **argv)
 			printf("check if CONFIG_GUP_TEST is enabled in kernel config\n");
 			break;
 		default:
-			perror("failed to open /sys/kernel/debug/gup_test");
+			perror("failed to open " GUP_TEST_FILE);
 			break;
 		}
 		exit(KSFT_SKIP);
-- 
GitLab


From 7c05eae8db9296e28b5dd34deec1ca5ef96d0f08 Mon Sep 17 00:00:00 2001
From: Steve French <stfrench@microsoft.com>
Date: Wed, 15 Jun 2022 22:40:23 -0500
Subject: [PATCH 0699/1731] smb3: add trace point for SMB2_set_eof

In order to debug problems with file size being reported incorrectly
temporarily (in this case xfstest generic/584 intermittent failure)
we need to add trace point for the non-compounded code path where
we set the file size (SMB2_set_eof).  The new trace point is:
   "smb3_set_eof"

Here is sample output from the tracepoint:

            TASK-PID     CPU#  |||||  TIMESTAMP  FUNCTION
              | |         |   |||||     |         |
          xfs_io-75403   [002] ..... 95219.189835: smb3_set_eof: xid=221 sid=0xeef1cbd2 tid=0x27079ee6 fid=0x52edb58c offset=0x100000
 aio-dio-append--75418   [010] ..... 95219.242402: smb3_set_eof: xid=226 sid=0xeef1cbd2 tid=0x27079ee6 fid=0xae89852d offset=0x0

Reviewed-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/smb2pdu.c |  2 ++
 fs/cifs/trace.h   | 38 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 40 insertions(+)

diff --git a/fs/cifs/smb2pdu.c b/fs/cifs/smb2pdu.c
index eaf975f1ad893..b515140bad8d2 100644
--- a/fs/cifs/smb2pdu.c
+++ b/fs/cifs/smb2pdu.c
@@ -5154,6 +5154,8 @@ SMB2_set_eof(const unsigned int xid, struct cifs_tcon *tcon, u64 persistent_fid,
 	data = &info;
 	size = sizeof(struct smb2_file_eof_info);
 
+	trace_smb3_set_eof(xid, persistent_fid, tcon->tid, tcon->ses->Suid, le64_to_cpu(*eof));
+
 	return send_set_info(xid, tcon, persistent_fid, volatile_fid,
 			pid, FILE_END_OF_FILE_INFORMATION, SMB2_O_INFO_FILE,
 			0, 1, &data, &size);
diff --git a/fs/cifs/trace.h b/fs/cifs/trace.h
index 2be5e0c8564d1..6b88dc2e364f5 100644
--- a/fs/cifs/trace.h
+++ b/fs/cifs/trace.h
@@ -121,6 +121,44 @@ DEFINE_SMB3_RW_DONE_EVENT(query_dir_done);
 DEFINE_SMB3_RW_DONE_EVENT(zero_done);
 DEFINE_SMB3_RW_DONE_EVENT(falloc_done);
 
+/* For logging successful set EOF (truncate) */
+DECLARE_EVENT_CLASS(smb3_eof_class,
+	TP_PROTO(unsigned int xid,
+		__u64	fid,
+		__u32	tid,
+		__u64	sesid,
+		__u64	offset),
+	TP_ARGS(xid, fid, tid, sesid, offset),
+	TP_STRUCT__entry(
+		__field(unsigned int, xid)
+		__field(__u64, fid)
+		__field(__u32, tid)
+		__field(__u64, sesid)
+		__field(__u64, offset)
+	),
+	TP_fast_assign(
+		__entry->xid = xid;
+		__entry->fid = fid;
+		__entry->tid = tid;
+		__entry->sesid = sesid;
+		__entry->offset = offset;
+	),
+	TP_printk("xid=%u sid=0x%llx tid=0x%x fid=0x%llx offset=0x%llx",
+		__entry->xid, __entry->sesid, __entry->tid, __entry->fid,
+		__entry->offset)
+)
+
+#define DEFINE_SMB3_EOF_EVENT(name)         \
+DEFINE_EVENT(smb3_eof_class, smb3_##name,   \
+	TP_PROTO(unsigned int xid,		\
+		__u64	fid,			\
+		__u32	tid,			\
+		__u64	sesid,			\
+		__u64	offset),		\
+	TP_ARGS(xid, fid, tid, sesid, offset))
+
+DEFINE_SMB3_EOF_EVENT(set_eof);
+
 /*
  * For handle based calls other than read and write, and get/set info
  */
-- 
GitLab


From 5d7362d0d56da3b85b19b5e5ce657026c2eef479 Mon Sep 17 00:00:00 2001
From: Mikulas Patocka <mpatocka@redhat.com>
Date: Thu, 16 Jun 2022 13:21:27 -0400
Subject: [PATCH 0700/1731] dm: fix use-after-free in dm_put_live_table_bio

dm_put_live_table_bio is called from the end of dm_submit_bio.
However, at this point, the bio may be already finished and the caller
may have freed the bio. Consequently, dm_put_live_table_bio accesses
the stale "bio" pointer.

Fix this bug by loading the bi_opf value and passing it to
dm_get_live_table_bio and dm_put_live_table_bio instead of the bio.

This bug was found by running the lvm2 testsuite with kasan.

Fixes: 563a225c9fd2 ("dm: introduce dm_{get,put}_live_table_bio called from dm_submit_bio")
Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Signed-off-by: Mike Snitzer <snitzer@kernel.org>
---
 drivers/md/dm.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/md/dm.c b/drivers/md/dm.c
index d5e6d33700e50..6ea14ab94aa60 100644
--- a/drivers/md/dm.c
+++ b/drivers/md/dm.c
@@ -715,18 +715,18 @@ static void dm_put_live_table_fast(struct mapped_device *md) __releases(RCU)
 }
 
 static inline struct dm_table *dm_get_live_table_bio(struct mapped_device *md,
-						     int *srcu_idx, struct bio *bio)
+						     int *srcu_idx, unsigned bio_opf)
 {
-	if (bio->bi_opf & REQ_NOWAIT)
+	if (bio_opf & REQ_NOWAIT)
 		return dm_get_live_table_fast(md);
 	else
 		return dm_get_live_table(md, srcu_idx);
 }
 
 static inline void dm_put_live_table_bio(struct mapped_device *md, int srcu_idx,
-					 struct bio *bio)
+					 unsigned bio_opf)
 {
-	if (bio->bi_opf & REQ_NOWAIT)
+	if (bio_opf & REQ_NOWAIT)
 		dm_put_live_table_fast(md);
 	else
 		dm_put_live_table(md, srcu_idx);
@@ -1715,8 +1715,9 @@ static void dm_submit_bio(struct bio *bio)
 	struct mapped_device *md = bio->bi_bdev->bd_disk->private_data;
 	int srcu_idx;
 	struct dm_table *map;
+	unsigned bio_opf = bio->bi_opf;
 
-	map = dm_get_live_table_bio(md, &srcu_idx, bio);
+	map = dm_get_live_table_bio(md, &srcu_idx, bio_opf);
 
 	/* If suspended, or map not yet available, queue this IO for later */
 	if (unlikely(test_bit(DMF_BLOCK_IO_FOR_SUSPEND, &md->flags)) ||
@@ -1732,7 +1733,7 @@ static void dm_submit_bio(struct bio *bio)
 
 	dm_split_and_process_bio(md, map, bio);
 out:
-	dm_put_live_table_bio(md, srcu_idx, bio);
+	dm_put_live_table_bio(md, srcu_idx, bio_opf);
 }
 
 static bool dm_poll_dm_io(struct dm_io *io, struct io_comp_batch *iob,
-- 
GitLab


From 1ee88de395c3ad6791c4baeba40e83b6ec97657a Mon Sep 17 00:00:00 2001
From: Mikulas Patocka <mpatocka@redhat.com>
Date: Thu, 16 Jun 2022 14:14:39 -0400
Subject: [PATCH 0701/1731] dm: fix narrow race for REQ_NOWAIT bios being
 issued despite no support

Starting with the commit 63a225c9fd20, device mapper has an optimization
that it will take cheaper table lock (dm_get_live_table_fast instead of
dm_get_live_table) if the bio has REQ_NOWAIT. The bios with REQ_NOWAIT
must not block in the target request routine, if they did, we would be
blocking while holding rcu_read_lock, which is prohibited.

The targets that are suitable for REQ_NOWAIT optimization (and that don't
block in the map routine) have the flag DM_TARGET_NOWAIT set. Device
mapper will test if all the targets and all the devices in a table
support nowait (see the function dm_table_supports_nowait) and it will set
or clear the QUEUE_FLAG_NOWAIT flag on its request queue according to
this check.

There's a test in submit_bio_noacct: "if ((bio->bi_opf & REQ_NOWAIT) &&
!blk_queue_nowait(q)) goto not_supported" - this will make sure that
REQ_NOWAIT bios can't enter a request queue that doesn't support them.

This mechanism works to prevent REQ_NOWAIT bios from reaching dm targets
that don't support the REQ_NOWAIT flag (and that may block in the map
routine) - except that there is a small race condition:

submit_bio_noacct checks if the queue has the QUEUE_FLAG_NOWAIT without
holding any locks. Immediatelly after this check, the device mapper table
may be reloaded with a table that doesn't support REQ_NOWAIT (for example,
if we start moving the logical volume or if we activate a snapshot).
However the REQ_NOWAIT bio that already passed the check in
submit_bio_noacct would be sent to device mapper, where it could be
redirected to a dm target that doesn't support REQ_NOWAIT - the result is
sleeping while we hold rcu_read_lock.

In order to fix this race, we double-check if the target supports
REQ_NOWAIT while we hold the table lock (so that the table can't change
under us).

Fixes: 563a225c9fd2 ("dm: introduce dm_{get,put}_live_table_bio called from dm_submit_bio")
Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Signed-off-by: Mike Snitzer <snitzer@kernel.org>
---
 drivers/md/dm.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/md/dm.c b/drivers/md/dm.c
index 6ea14ab94aa60..b6b25d319ef70 100644
--- a/drivers/md/dm.c
+++ b/drivers/md/dm.c
@@ -1613,7 +1613,12 @@ static blk_status_t __split_and_process_bio(struct clone_info *ci)
 	ti = dm_table_find_target(ci->map, ci->sector);
 	if (unlikely(!ti))
 		return BLK_STS_IOERR;
-	else if (unlikely(ci->is_abnormal_io))
+
+	if (unlikely((ci->bio->bi_opf & REQ_NOWAIT) != 0) &&
+	    unlikely(!dm_target_supports_nowait(ti->type)))
+		return BLK_STS_NOTSUPP;
+
+	if (unlikely(ci->is_abnormal_io))
 		return __process_abnormal_io(ci, ti);
 
 	/*
-- 
GitLab


From 85e123c27d5cbc22cfdc01de1e2ca1d9003a02d0 Mon Sep 17 00:00:00 2001
From: Mikulas Patocka <mpatocka@redhat.com>
Date: Thu, 16 Jun 2022 13:28:57 -0400
Subject: [PATCH 0702/1731] dm mirror log: round up region bitmap size to
 BITS_PER_LONG

The code in dm-log rounds up bitset_size to 32 bits. It then uses
find_next_zero_bit_le on the allocated region. find_next_zero_bit_le
accesses the bitmap using unsigned long pointers. So, on 64-bit
architectures, it may access 4 bytes beyond the allocated size.

Fix this bug by rounding up bitset_size to BITS_PER_LONG.

This bug was found by running the lvm2 testsuite with kasan.

Fixes: 29121bd0b00e ("[PATCH] dm mirror log: bitset_size fix")
Cc: stable@vger.kernel.org
Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Signed-off-by: Mike Snitzer <snitzer@kernel.org>
---
 drivers/md/dm-log.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/md/dm-log.c b/drivers/md/dm-log.c
index 06f328928a7f5..2dda05aada231 100644
--- a/drivers/md/dm-log.c
+++ b/drivers/md/dm-log.c
@@ -415,8 +415,7 @@ static int create_log_context(struct dm_dirty_log *log, struct dm_target *ti,
 	/*
 	 * Work out how many "unsigned long"s we need to hold the bitset.
 	 */
-	bitset_size = dm_round_up(region_count,
-				  sizeof(*lc->clean_bits) << BYTE_SHIFT);
+	bitset_size = dm_round_up(region_count, BITS_PER_LONG);
 	bitset_size >>= BYTE_SHIFT;
 
 	lc->bitset_uint32_count = bitset_size / sizeof(*lc->clean_bits);
-- 
GitLab


From da8badd7d3583f447eac2ab65a332f2d773deca1 Mon Sep 17 00:00:00 2001
From: Bart Van Assche <bvanassche@acm.org>
Date: Mon, 13 Jun 2022 14:44:40 -0700
Subject: [PATCH 0703/1731] scsi: ufs: Simplify ufshcd_clear_cmd()

Remove the local variable 'err'. This patch does not change any
functionality.

Link: https://lore.kernel.org/r/20220613214442.212466-2-bvanassche@acm.org
Reviewed-by: Stanley Chu <stanley.chu@mediatek.com>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Bart Van Assche <bvanassche@acm.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
---
 drivers/ufs/core/ufshcd.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 01fb4bad86be8..2d479e31c5885 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -2866,7 +2866,6 @@ static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
 static int
 ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
 {
-	int err = 0;
 	unsigned long flags;
 	u32 mask = 1 << tag;
 
@@ -2879,11 +2878,8 @@ ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
 	 * wait for h/w to clear corresponding bit in door-bell.
 	 * max. wait is 1 sec.
 	 */
-	err = ufshcd_wait_for_register(hba,
-			REG_UTP_TRANSFER_REQ_DOOR_BELL,
-			mask, ~mask, 1000, 1000);
-
-	return err;
+	return ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL,
+					mask, ~mask, 1000, 1000);
 }
 
 static int
-- 
GitLab


From d1a7644648b7cdacaf8d1013a4285001911e9bc8 Mon Sep 17 00:00:00 2001
From: Bart Van Assche <bvanassche@acm.org>
Date: Mon, 13 Jun 2022 14:44:41 -0700
Subject: [PATCH 0704/1731] scsi: ufs: Support clearing multiple commands at
 once

Modify ufshcd_clear_cmd() such that it supports clearing multiple commands
at once instead of one command at a time. This change will be used in a
later patch to reduce the time spent in the reset handler.

Link: https://lore.kernel.org/r/20220613214442.212466-3-bvanassche@acm.org
Reviewed-by: Stanley Chu <stanley.chu@mediatek.com>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Bart Van Assche <bvanassche@acm.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
---
 drivers/ufs/core/ufshcd.c | 42 ++++++++++++++++++++++++++-------------
 1 file changed, 28 insertions(+), 14 deletions(-)

diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 2d479e31c5885..8789147760aeb 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -748,17 +748,28 @@ static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
 }
 
 /**
- * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
+ * ufshcd_utrl_clear() - Clear requests from the controller request list.
  * @hba: per adapter instance
- * @pos: position of the bit to be cleared
+ * @mask: mask with one bit set for each request to be cleared
  */
-static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
+static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask)
 {
 	if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
-		ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
-	else
-		ufshcd_writel(hba, ~(1 << pos),
-				REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+		mask = ~mask;
+	/*
+	 * From the UFSHCI specification: "UTP Transfer Request List CLear
+	 * Register (UTRLCLR): This field is bit significant. Each bit
+	 * corresponds to a slot in the UTP Transfer Request List, where bit 0
+	 * corresponds to request slot 0. A bit in this field is set to ‘0’
+	 * by host software to indicate to the host controller that a transfer
+	 * request slot is cleared. The host controller
+	 * shall free up any resources associated to the request slot
+	 * immediately, and shall set the associated bit in UTRLDBR to ‘0’. The
+	 * host software indicates no change to request slots by setting the
+	 * associated bits in this field to ‘1’. Bits in this field shall only
+	 * be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’."
+	 */
+	ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR);
 }
 
 /**
@@ -2863,15 +2874,18 @@ static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
 	return ufshcd_compose_devman_upiu(hba, lrbp);
 }
 
-static int
-ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
+/*
+ * Clear all the requests from the controller for which a bit has been set in
+ * @mask and wait until the controller confirms that these requests have been
+ * cleared.
+ */
+static int ufshcd_clear_cmds(struct ufs_hba *hba, u32 mask)
 {
 	unsigned long flags;
-	u32 mask = 1 << tag;
 
 	/* clear outstanding transaction before retry */
 	spin_lock_irqsave(hba->host->host_lock, flags);
-	ufshcd_utrl_clear(hba, tag);
+	ufshcd_utrl_clear(hba, mask);
 	spin_unlock_irqrestore(hba->host->host_lock, flags);
 
 	/*
@@ -2959,7 +2973,7 @@ static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
 		err = -ETIMEDOUT;
 		dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
 			__func__, lrbp->task_tag);
-		if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
+		if (!ufshcd_clear_cmds(hba, 1U << lrbp->task_tag))
 			/* successfully cleared the command, retry if needed */
 			err = -EAGAIN;
 		/*
@@ -6982,7 +6996,7 @@ static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
 	/* clear the commands that were pending for corresponding LUN */
 	for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
 		if (hba->lrb[pos].lun == lun) {
-			err = ufshcd_clear_cmd(hba, pos);
+			err = ufshcd_clear_cmds(hba, 1U << pos);
 			if (err)
 				break;
 			__ufshcd_transfer_req_compl(hba, 1U << pos);
@@ -7084,7 +7098,7 @@ static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag)
 		goto out;
 	}
 
-	err = ufshcd_clear_cmd(hba, tag);
+	err = ufshcd_clear_cmds(hba, 1U << tag);
 	if (err)
 		dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
 			__func__, tag, err);
-- 
GitLab


From 2acd76e7b8596e307fcec8fc6bc5fe5ab174749a Mon Sep 17 00:00:00 2001
From: Bart Van Assche <bvanassche@acm.org>
Date: Mon, 13 Jun 2022 14:44:42 -0700
Subject: [PATCH 0705/1731] scsi: ufs: Fix a race between the interrupt handler
 and the reset handler

Prevent that both the interrupt handler and the reset handler try to
complete a request at the same time. This patch is the result of an
analysis of the following crash:

Unable to handle kernel NULL pointer dereference at virtual address 0000000000000120
CPU: 0 PID: 0 Comm: swapper/0 Tainted: G           OE     5.10.107-android13-4-00051-g1e48e8970cca-ab8664745 #1
pc : ufshcd_release_scsi_cmd+0x30/0x46c
lr : __ufshcd_transfer_req_compl+0x4fc/0x9c0
Call trace:
 ufshcd_release_scsi_cmd+0x30/0x46c
 __ufshcd_transfer_req_compl+0x4fc/0x9c0
 ufshcd_poll+0xf0/0x208
 ufshcd_sl_intr+0xb8/0xf0
 ufshcd_intr+0x168/0x2f4
 __handle_irq_event_percpu+0xa0/0x30c
 handle_irq_event+0x84/0x178
 handle_fasteoi_irq+0x150/0x2e8
 __handle_domain_irq+0x114/0x1e4
 gic_handle_irq.31846+0x58/0x300
 el1_irq+0xe4/0x1c0
 cpuidle_enter_state+0x3ac/0x8c4
 do_idle+0x2fc/0x55c
 cpu_startup_entry+0x84/0x90
 kernel_init+0x0/0x310
 start_kernel+0x0/0x608
 start_kernel+0x4ec/0x608

Link: https://lore.kernel.org/r/20220613214442.212466-4-bvanassche@acm.org
Reviewed-by: Stanley Chu <stanley.chu@mediatek.com>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Bart Van Assche <bvanassche@acm.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
---
 drivers/ufs/core/ufshcd.c | 28 +++++++++++++++++++---------
 1 file changed, 19 insertions(+), 9 deletions(-)

diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 8789147760aeb..ce86d1b790c05 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -6968,14 +6968,14 @@ int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
 }
 
 /**
- * ufshcd_eh_device_reset_handler - device reset handler registered to
- *                                    scsi layer.
+ * ufshcd_eh_device_reset_handler() - Reset a single logical unit.
  * @cmd: SCSI command pointer
  *
  * Returns SUCCESS/FAILED
  */
 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
 {
+	unsigned long flags, pending_reqs = 0, not_cleared = 0;
 	struct Scsi_Host *host;
 	struct ufs_hba *hba;
 	u32 pos;
@@ -6994,14 +6994,24 @@ static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
 	}
 
 	/* clear the commands that were pending for corresponding LUN */
-	for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
-		if (hba->lrb[pos].lun == lun) {
-			err = ufshcd_clear_cmds(hba, 1U << pos);
-			if (err)
-				break;
-			__ufshcd_transfer_req_compl(hba, 1U << pos);
-		}
+	spin_lock_irqsave(&hba->outstanding_lock, flags);
+	for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs)
+		if (hba->lrb[pos].lun == lun)
+			__set_bit(pos, &pending_reqs);
+	hba->outstanding_reqs &= ~pending_reqs;
+	spin_unlock_irqrestore(&hba->outstanding_lock, flags);
+
+	if (ufshcd_clear_cmds(hba, pending_reqs) < 0) {
+		spin_lock_irqsave(&hba->outstanding_lock, flags);
+		not_cleared = pending_reqs &
+			ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
+		hba->outstanding_reqs |= not_cleared;
+		spin_unlock_irqrestore(&hba->outstanding_lock, flags);
+
+		dev_err(hba->dev, "%s: failed to clear requests %#lx\n",
+			__func__, not_cleared);
 	}
+	__ufshcd_transfer_req_compl(hba, pending_reqs & ~not_cleared);
 
 out:
 	hba->req_abort_count = 0;
-- 
GitLab


From 1d3e0980782fbafaf93285779fd3905e4f866802 Mon Sep 17 00:00:00 2001
From: Saurabh Sengar <ssengar@linux.microsoft.com>
Date: Tue, 14 Jun 2022 00:05:55 -0700
Subject: [PATCH 0706/1731] scsi: storvsc: Correct reporting of Hyper-V I/O
 size limits
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Current code is based on the idea that the max number of SGL entries
also determines the max size of an I/O request.  While this idea was
true in older versions of the storvsc driver when SGL entry length
was limited to 4 Kbytes, commit 3d9c3dcc58e9 ("scsi: storvsc: Enable
scatterlist entry lengths > 4Kbytes") removed that limitation. It's
now theoretically possible for the block layer to send requests that
exceed the maximum size supported by Hyper-V. This problem doesn't
currently happen in practice because the block layer defaults to a
512 Kbyte maximum, while Hyper-V in Azure supports 2 Mbyte I/O sizes.
But some future configuration of Hyper-V could have a smaller max I/O
size, and the block layer could exceed that max.

Fix this by correctly setting max_sectors as well as sg_tablesize to
reflect the maximum I/O size that Hyper-V reports. While allowing
I/O sizes larger than the block layer default of 512 Kbytes doesn’t
provide any noticeable performance benefit in the tests we ran, it's
still appropriate to report the correct underlying Hyper-V capabilities
to the Linux block layer.

Also tweak the virt_boundary_mask to reflect that the required
alignment derives from Hyper-V communication using a 4 Kbyte page size,
and not on the guest page size, which might be bigger (eg. ARM64).

Link: https://lore.kernel.org/r/1655190355-28722-1-git-send-email-ssengar@linux.microsoft.com
Fixes: 3d9c3dcc58e9 ("scsi: storvsc: Enable scatter list entry lengths > 4Kbytes")
Reviewed-by: Michael Kelley <mikelley@microsoft.com>
Signed-off-by: Saurabh Sengar <ssengar@linux.microsoft.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
---
 drivers/scsi/storvsc_drv.c | 27 ++++++++++++++++++++++-----
 1 file changed, 22 insertions(+), 5 deletions(-)

diff --git a/drivers/scsi/storvsc_drv.c b/drivers/scsi/storvsc_drv.c
index ca3530982e52c..fe000da113327 100644
--- a/drivers/scsi/storvsc_drv.c
+++ b/drivers/scsi/storvsc_drv.c
@@ -1844,7 +1844,7 @@ static struct scsi_host_template scsi_driver = {
 	.cmd_per_lun =		2048,
 	.this_id =		-1,
 	/* Ensure there are no gaps in presented sgls */
-	.virt_boundary_mask =	PAGE_SIZE-1,
+	.virt_boundary_mask =	HV_HYP_PAGE_SIZE - 1,
 	.no_write_same =	1,
 	.track_queue_depth =	1,
 	.change_queue_depth =	storvsc_change_queue_depth,
@@ -1895,6 +1895,7 @@ static int storvsc_probe(struct hv_device *device,
 	int target = 0;
 	struct storvsc_device *stor_device;
 	int max_sub_channels = 0;
+	u32 max_xfer_bytes;
 
 	/*
 	 * We support sub-channels for storage on SCSI and FC controllers.
@@ -1968,12 +1969,28 @@ static int storvsc_probe(struct hv_device *device,
 	}
 	/* max cmd length */
 	host->max_cmd_len = STORVSC_MAX_CMD_LEN;
-
 	/*
-	 * set the table size based on the info we got
-	 * from the host.
+	 * Any reasonable Hyper-V configuration should provide
+	 * max_transfer_bytes value aligning to HV_HYP_PAGE_SIZE,
+	 * protecting it from any weird value.
+	 */
+	max_xfer_bytes = round_down(stor_device->max_transfer_bytes, HV_HYP_PAGE_SIZE);
+	/* max_hw_sectors_kb */
+	host->max_sectors = max_xfer_bytes >> 9;
+	/*
+	 * There are 2 requirements for Hyper-V storvsc sgl segments,
+	 * based on which the below calculation for max segments is
+	 * done:
+	 *
+	 * 1. Except for the first and last sgl segment, all sgl segments
+	 *    should be align to HV_HYP_PAGE_SIZE, that also means the
+	 *    maximum number of segments in a sgl can be calculated by
+	 *    dividing the total max transfer length by HV_HYP_PAGE_SIZE.
+	 *
+	 * 2. Except for the first and last, each entry in the SGL must
+	 *    have an offset that is a multiple of HV_HYP_PAGE_SIZE.
 	 */
-	host->sg_tablesize = (stor_device->max_transfer_bytes >> PAGE_SHIFT);
+	host->sg_tablesize = (max_xfer_bytes >> HV_HYP_PAGE_SHIFT) + 1;
 	/*
 	 * For non-IDE disks, the host supports multiple channels.
 	 * Set the number of HW queues we are supporting.
-- 
GitLab


From 72ea7fe0db73d65c7d977208842d8ade9b823de9 Mon Sep 17 00:00:00 2001
From: Tyrel Datwyler <tyreld@linux.ibm.com>
Date: Thu, 16 Jun 2022 12:11:26 -0700
Subject: [PATCH 0707/1731] scsi: ibmvfc: Allocate/free queue resource only
 during probe/remove

Currently, the sub-queues and event pool resources are allocated/freed for
every CRQ connection event such as reset and LPM. This exposes the driver
to a couple issues. First the inefficiency of freeing and reallocating
memory that can simply be resued after being sanitized. Further, a system
under memory pressue runs the risk of allocation failures that could result
in a crippled driver. Finally, there is a race window where command
submission/compeletion can try to pull/return elements from/to an event
pool that is being deleted or already has been deleted due to the lack of
host state around freeing/allocating resources. The following is an example
of list corruption following a live partition migration (LPM):

Oops: Exception in kernel mode, sig: 5 [#1]
LE PAGE_SIZE=64K MMU=Hash SMP NR_CPUS=2048 NUMA pSeries
Modules linked in: vfat fat isofs cdrom ext4 mbcache jbd2 nft_counter nft_compat nf_tables nfnetlink rpadlpar_io rpaphp xsk_diag nfsv3 nfs_acl nfs lockd grace fscache netfs rfkill bonding tls sunrpc pseries_rng drm drm_panel_orientation_quirks xfs libcrc32c dm_service_time sd_mod t10_pi sg ibmvfc scsi_transport_fc ibmveth vmx_crypto dm_multipath dm_mirror dm_region_hash dm_log dm_mod ipmi_devintf ipmi_msghandler fuse
CPU: 0 PID: 2108 Comm: ibmvfc_0 Kdump: loaded Not tainted 5.14.0-70.9.1.el9_0.ppc64le #1
NIP: c0000000007c4bb0 LR: c0000000007c4bac CTR: 00000000005b9a10
REGS: c00000025c10b760 TRAP: 0700  Not tainted (5.14.0-70.9.1.el9_0.ppc64le)
MSR: 800000000282b033 <SF,VEC,VSX,EE,FP,ME,IR,DR,RI,LE> CR: 2800028f XER: 0000000f
CFAR: c0000000001f55bc IRQMASK: 0
        GPR00: c0000000007c4bac c00000025c10ba00 c000000002a47c00 000000000000004e
        GPR04: c0000031e3006f88 c0000031e308bd00 c00000025c10b768 0000000000000027
        GPR08: 0000000000000000 c0000031e3009dc0 00000031e0eb0000 0000000000000000
        GPR12: c0000031e2ffffa8 c000000002dd0000 c000000000187108 c00000020fcee2c0
        GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
        GPR20: 0000000000000000 0000000000000000 0000000000000000 c008000002f81300
        GPR24: 5deadbeef0000100 5deadbeef0000122 c000000263ba6910 c00000024cc88000
        GPR28: 000000000000003c c0000002430a0000 c0000002430ac300 000000000000c300
NIP [c0000000007c4bb0] __list_del_entry_valid+0x90/0x100
LR [c0000000007c4bac] __list_del_entry_valid+0x8c/0x100
Call Trace:
[c00000025c10ba00] [c0000000007c4bac] __list_del_entry_valid+0x8c/0x100 (unreliable)
[c00000025c10ba60] [c008000002f42284] ibmvfc_free_queue+0xec/0x210 [ibmvfc]
[c00000025c10bb10] [c008000002f4246c] ibmvfc_deregister_scsi_channel+0xc4/0x160 [ibmvfc]
[c00000025c10bba0] [c008000002f42580] ibmvfc_release_sub_crqs+0x78/0x130 [ibmvfc]
[c00000025c10bc20] [c008000002f4f6cc] ibmvfc_do_work+0x5c4/0xc70 [ibmvfc]
[c00000025c10bce0] [c008000002f4fdec] ibmvfc_work+0x74/0x1e8 [ibmvfc]
[c00000025c10bda0] [c0000000001872b8] kthread+0x1b8/0x1c0
[c00000025c10be10] [c00000000000cd64] ret_from_kernel_thread+0x5c/0x64
Instruction dump:
40820034 38600001 38210060 4e800020 7c0802a6 7c641b78 3c62fe7a 7d254b78
3863b590 f8010070 4ba309cd 60000000 <0fe00000> 7c0802a6 3c62fe7a 3863b640
---[ end trace 11a2b65a92f8b66c ]---
ibmvfc 30000003: Send warning. Receive queue closed, will retry.

Add registration/deregistration helpers that are called instead during
connection resets to sanitize and reconfigure the queues.

Link: https://lore.kernel.org/r/20220616191126.1281259-3-tyreld@linux.ibm.com
Fixes: 3034ebe26389 ("scsi: ibmvfc: Add alloc/dealloc routines for SCSI Sub-CRQ Channels")
Cc: stable@vger.kernel.org
Reviewed-by: Brian King <brking@linux.vnet.ibm.com>
Signed-off-by: Tyrel Datwyler <tyreld@linux.ibm.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
---
 drivers/scsi/ibmvscsi/ibmvfc.c | 79 ++++++++++++++++++++++++++--------
 1 file changed, 62 insertions(+), 17 deletions(-)

diff --git a/drivers/scsi/ibmvscsi/ibmvfc.c b/drivers/scsi/ibmvscsi/ibmvfc.c
index d0eab5700dc57..4cd03fe731831 100644
--- a/drivers/scsi/ibmvscsi/ibmvfc.c
+++ b/drivers/scsi/ibmvscsi/ibmvfc.c
@@ -160,8 +160,8 @@ static void ibmvfc_npiv_logout(struct ibmvfc_host *);
 static void ibmvfc_tgt_implicit_logout_and_del(struct ibmvfc_target *);
 static void ibmvfc_tgt_move_login(struct ibmvfc_target *);
 
-static void ibmvfc_release_sub_crqs(struct ibmvfc_host *);
-static void ibmvfc_init_sub_crqs(struct ibmvfc_host *);
+static void ibmvfc_dereg_sub_crqs(struct ibmvfc_host *);
+static void ibmvfc_reg_sub_crqs(struct ibmvfc_host *);
 
 static const char *unknown_error = "unknown error";
 
@@ -917,7 +917,7 @@ static int ibmvfc_reenable_crq_queue(struct ibmvfc_host *vhost)
 	struct vio_dev *vdev = to_vio_dev(vhost->dev);
 	unsigned long flags;
 
-	ibmvfc_release_sub_crqs(vhost);
+	ibmvfc_dereg_sub_crqs(vhost);
 
 	/* Re-enable the CRQ */
 	do {
@@ -936,7 +936,7 @@ static int ibmvfc_reenable_crq_queue(struct ibmvfc_host *vhost)
 	spin_unlock(vhost->crq.q_lock);
 	spin_unlock_irqrestore(vhost->host->host_lock, flags);
 
-	ibmvfc_init_sub_crqs(vhost);
+	ibmvfc_reg_sub_crqs(vhost);
 
 	return rc;
 }
@@ -955,7 +955,7 @@ static int ibmvfc_reset_crq(struct ibmvfc_host *vhost)
 	struct vio_dev *vdev = to_vio_dev(vhost->dev);
 	struct ibmvfc_queue *crq = &vhost->crq;
 
-	ibmvfc_release_sub_crqs(vhost);
+	ibmvfc_dereg_sub_crqs(vhost);
 
 	/* Close the CRQ */
 	do {
@@ -988,7 +988,7 @@ static int ibmvfc_reset_crq(struct ibmvfc_host *vhost)
 	spin_unlock(vhost->crq.q_lock);
 	spin_unlock_irqrestore(vhost->host->host_lock, flags);
 
-	ibmvfc_init_sub_crqs(vhost);
+	ibmvfc_reg_sub_crqs(vhost);
 
 	return rc;
 }
@@ -5757,9 +5757,6 @@ static int ibmvfc_register_scsi_channel(struct ibmvfc_host *vhost,
 
 	ENTER;
 
-	if (ibmvfc_alloc_queue(vhost, scrq, IBMVFC_SUB_CRQ_FMT))
-		return -ENOMEM;
-
 	rc = h_reg_sub_crq(vdev->unit_address, scrq->msg_token, PAGE_SIZE,
 			   &scrq->cookie, &scrq->hw_irq);
 
@@ -5800,7 +5797,6 @@ irq_failed:
 		rc = plpar_hcall_norets(H_FREE_SUB_CRQ, vdev->unit_address, scrq->cookie);
 	} while (rtas_busy_delay(rc));
 reg_failed:
-	ibmvfc_free_queue(vhost, scrq);
 	LEAVE;
 	return rc;
 }
@@ -5826,12 +5822,50 @@ static void ibmvfc_deregister_scsi_channel(struct ibmvfc_host *vhost, int index)
 	if (rc)
 		dev_err(dev, "Failed to free sub-crq[%d]: rc=%ld\n", index, rc);
 
-	ibmvfc_free_queue(vhost, scrq);
+	/* Clean out the queue */
+	memset(scrq->msgs.crq, 0, PAGE_SIZE);
+	scrq->cur = 0;
+
+	LEAVE;
+}
+
+static void ibmvfc_reg_sub_crqs(struct ibmvfc_host *vhost)
+{
+	int i, j;
+
+	ENTER;
+	if (!vhost->mq_enabled || !vhost->scsi_scrqs.scrqs)
+		return;
+
+	for (i = 0; i < nr_scsi_hw_queues; i++) {
+		if (ibmvfc_register_scsi_channel(vhost, i)) {
+			for (j = i; j > 0; j--)
+				ibmvfc_deregister_scsi_channel(vhost, j - 1);
+			vhost->do_enquiry = 0;
+			return;
+		}
+	}
+
+	LEAVE;
+}
+
+static void ibmvfc_dereg_sub_crqs(struct ibmvfc_host *vhost)
+{
+	int i;
+
+	ENTER;
+	if (!vhost->mq_enabled || !vhost->scsi_scrqs.scrqs)
+		return;
+
+	for (i = 0; i < nr_scsi_hw_queues; i++)
+		ibmvfc_deregister_scsi_channel(vhost, i);
+
 	LEAVE;
 }
 
 static void ibmvfc_init_sub_crqs(struct ibmvfc_host *vhost)
 {
+	struct ibmvfc_queue *scrq;
 	int i, j;
 
 	ENTER;
@@ -5847,30 +5881,41 @@ static void ibmvfc_init_sub_crqs(struct ibmvfc_host *vhost)
 	}
 
 	for (i = 0; i < nr_scsi_hw_queues; i++) {
-		if (ibmvfc_register_scsi_channel(vhost, i)) {
-			for (j = i; j > 0; j--)
-				ibmvfc_deregister_scsi_channel(vhost, j - 1);
+		scrq = &vhost->scsi_scrqs.scrqs[i];
+		if (ibmvfc_alloc_queue(vhost, scrq, IBMVFC_SUB_CRQ_FMT)) {
+			for (j = i; j > 0; j--) {
+				scrq = &vhost->scsi_scrqs.scrqs[j - 1];
+				ibmvfc_free_queue(vhost, scrq);
+			}
 			kfree(vhost->scsi_scrqs.scrqs);
 			vhost->scsi_scrqs.scrqs = NULL;
 			vhost->scsi_scrqs.active_queues = 0;
 			vhost->do_enquiry = 0;
-			break;
+			vhost->mq_enabled = 0;
+			return;
 		}
 	}
 
+	ibmvfc_reg_sub_crqs(vhost);
+
 	LEAVE;
 }
 
 static void ibmvfc_release_sub_crqs(struct ibmvfc_host *vhost)
 {
+	struct ibmvfc_queue *scrq;
 	int i;
 
 	ENTER;
 	if (!vhost->scsi_scrqs.scrqs)
 		return;
 
-	for (i = 0; i < nr_scsi_hw_queues; i++)
-		ibmvfc_deregister_scsi_channel(vhost, i);
+	ibmvfc_dereg_sub_crqs(vhost);
+
+	for (i = 0; i < nr_scsi_hw_queues; i++) {
+		scrq = &vhost->scsi_scrqs.scrqs[i];
+		ibmvfc_free_queue(vhost, scrq);
+	}
 
 	kfree(vhost->scsi_scrqs.scrqs);
 	vhost->scsi_scrqs.scrqs = NULL;
-- 
GitLab


From aeaadcde1a60138bceb65de3cdaeec78170b4459 Mon Sep 17 00:00:00 2001
From: Tyrel Datwyler <tyreld@linux.ibm.com>
Date: Thu, 16 Jun 2022 12:11:25 -0700
Subject: [PATCH 0708/1731] scsi: ibmvfc: Store vhost pointer during subcrq
 allocation

Currently the back pointer from a queue to the vhost adapter isn't set
until after subcrq interrupt registration. The value is available when a
queue is first allocated and can/should be also set for primary and async
queues as well as subcrqs.

This fixes a crash observed during kexec/kdump on Power 9 with legacy XICS
interrupt controller where a pending subcrq interrupt from the previous
kernel can be replayed immediately upon IRQ registration resulting in
dereference of a garbage backpointer in ibmvfc_interrupt_scsi().

Kernel attempted to read user page (58) - exploit attempt? (uid: 0)
BUG: Kernel NULL pointer dereference on read at 0x00000058
Faulting instruction address: 0xc008000003216a08
Oops: Kernel access of bad area, sig: 11 [#1]
...
NIP [c008000003216a08] ibmvfc_interrupt_scsi+0x40/0xb0 [ibmvfc]
LR [c0000000082079e8] __handle_irq_event_percpu+0x98/0x270
Call Trace:
[c000000047fa3d80] [c0000000123e6180] 0xc0000000123e6180 (unreliable)
[c000000047fa3df0] [c0000000082079e8] __handle_irq_event_percpu+0x98/0x270
[c000000047fa3ea0] [c000000008207d18] handle_irq_event+0x98/0x188
[c000000047fa3ef0] [c00000000820f564] handle_fasteoi_irq+0xc4/0x310
[c000000047fa3f40] [c000000008205c60] generic_handle_irq+0x50/0x80
[c000000047fa3f60] [c000000008015c40] __do_irq+0x70/0x1a0
[c000000047fa3f90] [c000000008016d7c] __do_IRQ+0x9c/0x130
[c000000014622f60] [0000000020000000] 0x20000000
[c000000014622ff0] [c000000008016e50] do_IRQ+0x40/0xa0
[c000000014623020] [c000000008017044] replay_soft_interrupts+0x194/0x2f0
[c000000014623210] [c0000000080172a8] arch_local_irq_restore+0x108/0x170
[c000000014623240] [c000000008eb1008] _raw_spin_unlock_irqrestore+0x58/0xb0
[c000000014623270] [c00000000820b12c] __setup_irq+0x49c/0x9f0
[c000000014623310] [c00000000820b7c0] request_threaded_irq+0x140/0x230
[c000000014623380] [c008000003212a50] ibmvfc_register_scsi_channel+0x1e8/0x2f0 [ibmvfc]
[c000000014623450] [c008000003213d1c] ibmvfc_init_sub_crqs+0xc4/0x1f0 [ibmvfc]
[c0000000146234d0] [c0080000032145a8] ibmvfc_reset_crq+0x150/0x210 [ibmvfc]
[c000000014623550] [c0080000032147c8] ibmvfc_init_crq+0x160/0x280 [ibmvfc]
[c0000000146235f0] [c00800000321a9cc] ibmvfc_probe+0x2a4/0x530 [ibmvfc]

Link: https://lore.kernel.org/r/20220616191126.1281259-2-tyreld@linux.ibm.com
Fixes: 3034ebe26389 ("scsi: ibmvfc: Add alloc/dealloc routines for SCSI Sub-CRQ Channels")
Cc: stable@vger.kernel.org
Reviewed-by: Brian King <brking@linux.vnet.ibm.com>
Signed-off-by: Tyrel Datwyler <tyreld@linux.ibm.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
---
 drivers/scsi/ibmvscsi/ibmvfc.c | 3 ++-
 drivers/scsi/ibmvscsi/ibmvfc.h | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/scsi/ibmvscsi/ibmvfc.c b/drivers/scsi/ibmvscsi/ibmvfc.c
index 4cd03fe731831..00684e11976be 100644
--- a/drivers/scsi/ibmvscsi/ibmvfc.c
+++ b/drivers/scsi/ibmvscsi/ibmvfc.c
@@ -5682,6 +5682,8 @@ static int ibmvfc_alloc_queue(struct ibmvfc_host *vhost,
 	queue->cur = 0;
 	queue->fmt = fmt;
 	queue->size = PAGE_SIZE / fmt_size;
+
+	queue->vhost = vhost;
 	return 0;
 }
 
@@ -5787,7 +5789,6 @@ static int ibmvfc_register_scsi_channel(struct ibmvfc_host *vhost,
 	}
 
 	scrq->hwq_id = index;
-	scrq->vhost = vhost;
 
 	LEAVE;
 	return 0;
diff --git a/drivers/scsi/ibmvscsi/ibmvfc.h b/drivers/scsi/ibmvscsi/ibmvfc.h
index 3718406e09887..c39a245f43d02 100644
--- a/drivers/scsi/ibmvscsi/ibmvfc.h
+++ b/drivers/scsi/ibmvscsi/ibmvfc.h
@@ -789,6 +789,7 @@ struct ibmvfc_queue {
 	spinlock_t _lock;
 	spinlock_t *q_lock;
 
+	struct ibmvfc_host *vhost;
 	struct ibmvfc_event_pool evt_pool;
 	struct list_head sent;
 	struct list_head free;
@@ -797,7 +798,6 @@ struct ibmvfc_queue {
 	union ibmvfc_iu cancel_rsp;
 
 	/* Sub-CRQ fields */
-	struct ibmvfc_host *vhost;
 	unsigned long cookie;
 	unsigned long vios_cookie;
 	unsigned long hw_irq;
-- 
GitLab


From 042999388ef3dba43e813fdc6d6133ec9ca405dc Mon Sep 17 00:00:00 2001
From: Yang Li <yang.lee@linux.alibaba.com>
Date: Thu, 2 Jun 2022 14:21:16 +0800
Subject: [PATCH 0709/1731] mm/page_isolation.c: fix one kernel-doc comment

Remove one warning found by running scripts/kernel-doc, which is caused by
using 'make W=1':

mm/page_isolation.c:304: warning: Function parameter or member
'skip_isolation' not described in 'isolate_single_pageblock'

Link: https://lkml.kernel.org/r/20220602062116.61199-1-yang.lee@linux.alibaba.com
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 mm/page_isolation.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/mm/page_isolation.c b/mm/page_isolation.c
index d200d41ad0d32..9d73dc38e3d75 100644
--- a/mm/page_isolation.c
+++ b/mm/page_isolation.c
@@ -286,6 +286,8 @@ __first_valid_page(unsigned long pfn, unsigned long nr_pages)
  * @flags:			isolation flags
  * @gfp_flags:			GFP flags used for migrating pages
  * @isolate_before:	isolate the pageblock before the boundary_pfn
+ * @skip_isolation:	the flag to skip the pageblock isolation in second
+ *			isolate_single_pageblock()
  *
  * Free and in-use pages can be as big as MAX_ORDER-1 and contain more than one
  * pageblock. When not all pageblocks within a page are isolated at the same
-- 
GitLab


From 31733463372e8d88ea54bfa1e35178aad9b2ffd2 Mon Sep 17 00:00:00 2001
From: Marcelo Tosatti <mtosatti@redhat.com>
Date: Mon, 30 May 2022 12:51:56 -0300
Subject: [PATCH 0710/1731] mm: lru_cache_disable: use
 synchronize_rcu_expedited

commit ff042f4a9b050 ("mm: lru_cache_disable: replace work queue
synchronization with synchronize_rcu") replaced lru_cache_disable's usage
of work queues with synchronize_rcu.

Some users reported large performance regressions due to this commit, for
example:
https://lore.kernel.org/all/20220521234616.GO1790663@paulmck-ThinkPad-P17-Gen-1/T/

Switching to synchronize_rcu_expedited fixes the problem.

Link: https://lkml.kernel.org/r/YpToHCmnx/HEcVyR@fuller.cnet
Fixes: ff042f4a9b050 ("mm: lru_cache_disable: replace work queue synchronization with synchronize_rcu")
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Tested-by: Michael Larabel <Michael@MichaelLarabel.com>
Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Cc: Nicolas Saenz Julienne <nsaenzju@redhat.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Minchan Kim <minchan@kernel.org>
Cc: Matthew Wilcox <willy@infradead.org>
Cc: Mel Gorman <mgorman@techsingularity.net>
Cc: Juri Lelli <juri.lelli@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Paul E. McKenney <paulmck@kernel.org>
Cc: Phil Elwell <phil@raspberrypi.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 mm/swap.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/mm/swap.c b/mm/swap.c
index f3922a96b2e9e..034bb24879a3b 100644
--- a/mm/swap.c
+++ b/mm/swap.c
@@ -881,7 +881,7 @@ void lru_cache_disable(void)
 	 * lru_disable_count = 0 will have exited the critical
 	 * section when synchronize_rcu() returns.
 	 */
-	synchronize_rcu();
+	synchronize_rcu_expedited();
 #ifdef CONFIG_SMP
 	__lru_add_drain_all(true);
 #else
-- 
GitLab


From d25c83c6606ffc3abdf0868136ad3399f648ad70 Mon Sep 17 00:00:00 2001
From: Petr Mladek <pmladek@suse.com>
Date: Tue, 15 Mar 2022 11:24:44 +0100
Subject: [PATCH 0711/1731] kthread: make it clear that
 kthread_create_on_node() might be terminated by any fatal signal

The comments in kernel/kthread.c create a feeling that only SIGKILL is
able to terminate the creation of kernel kthreads by
kthread_create()/_on_node()/_on_cpu() APIs.

In reality, wait_for_completion_killable() might be killed by any fatal
signal that does not have a custom handler:

	(!siginmask(signr, SIG_KERNEL_IGNORE_MASK|SIG_KERNEL_STOP_MASK) && \
	 (t)->sighand->action[(signr)-1].sa.sa_handler == SIG_DFL)

static inline void signal_wake_up(struct task_struct *t, bool resume)
{
	signal_wake_up_state(t, resume ? TASK_WAKEKILL : 0);
}

static void complete_signal(int sig, struct task_struct *p, enum pid_type type)
{
[...]
	/*
	 * Found a killable thread.  If the signal will be fatal,
	 * then start taking the whole group down immediately.
	 */
	if (sig_fatal(p, sig) ...) {
		if (!sig_kernel_coredump(sig)) {
		[...]
			do {
				task_clear_jobctl_pending(t, JOBCTL_PENDING_MASK);
				sigaddset(&t->pending.signal, SIGKILL);
				signal_wake_up(t, 1);
			} while_each_thread(p, t);
			return;
		}
	}
}

Update the comments in kernel/kthread.c to make this more obvious.

The motivation for this change was debugging why a module initialization
failed.  The module was being loaded from initrd.  It "magically" failed
when systemd was switching to the real root.  The clean up operations sent
SIGTERM to various pending processed that were started from initrd.

Link: https://lkml.kernel.org/r/20220315102444.2380-1-pmladek@suse.com
Signed-off-by: Petr Mladek <pmladek@suse.com>
Reviewed-by: "Eric W. Biederman" <ebiederm@xmission.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Cc: Kees Cook <keescook@chromium.org>
Cc: Marco Elver <elver@google.com>
Cc: Jens Axboe <axboe@kernel.dk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 kernel/kthread.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/kernel/kthread.c b/kernel/kthread.c
index 544fd40974068..3c677918d8f2f 100644
--- a/kernel/kthread.c
+++ b/kernel/kthread.c
@@ -340,7 +340,7 @@ static int kthread(void *_create)
 
 	self = to_kthread(current);
 
-	/* If user was SIGKILLed, I release the structure. */
+	/* Release the structure when caller killed by a fatal signal. */
 	done = xchg(&create->done, NULL);
 	if (!done) {
 		kfree(create);
@@ -398,7 +398,7 @@ static void create_kthread(struct kthread_create_info *create)
 	/* We want our own signal handler (we take no signals by default). */
 	pid = kernel_thread(kthread, create, CLONE_FS | CLONE_FILES | SIGCHLD);
 	if (pid < 0) {
-		/* If user was SIGKILLed, I release the structure. */
+		/* Release the structure when caller killed by a fatal signal. */
 		struct completion *done = xchg(&create->done, NULL);
 
 		if (!done) {
@@ -440,9 +440,9 @@ struct task_struct *__kthread_create_on_node(int (*threadfn)(void *data),
 	 */
 	if (unlikely(wait_for_completion_killable(&done))) {
 		/*
-		 * If I was SIGKILLed before kthreadd (or new kernel thread)
-		 * calls complete(), leave the cleanup of this structure to
-		 * that thread.
+		 * If I was killed by a fatal signal before kthreadd (or new
+		 * kernel thread) calls complete(), leave the cleanup of this
+		 * structure to that thread.
 		 */
 		if (xchg(&create->done, NULL))
 			return ERR_PTR(-EINTR);
@@ -876,7 +876,7 @@ fail_task:
  *
  * Returns a pointer to the allocated worker on success, ERR_PTR(-ENOMEM)
  * when the needed structures could not get allocated, and ERR_PTR(-EINTR)
- * when the worker was SIGKILLed.
+ * when the caller was killed by a fatal signal.
  */
 struct kthread_worker *
 kthread_create_worker(unsigned int flags, const char namefmt[], ...)
@@ -925,7 +925,7 @@ EXPORT_SYMBOL(kthread_create_worker);
  * Return:
  * The pointer to the allocated worker on success, ERR_PTR(-ENOMEM)
  * when the needed structures could not get allocated, and ERR_PTR(-EINTR)
- * when the worker was SIGKILLed.
+ * when the caller was killed by a fatal signal.
  */
 struct kthread_worker *
 kthread_create_worker_on_cpu(int cpu, unsigned int flags,
-- 
GitLab


From 2949282938135ab734c3829495ae393523ceb702 Mon Sep 17 00:00:00 2001
From: SeongJae Park <sj@kernel.org>
Date: Sat, 4 Jun 2022 19:50:51 +0000
Subject: [PATCH 0712/1731] mm/damon/reclaim: schedule 'damon_reclaim_timer'
 only after 'system_wq' is initialized

Commit 059342d1dd4e ("mm/damon/reclaim: fix the timer always stays
active") made DAMON_RECLAIM's 'enabled' parameter store callback,
'enabled_store()', to schedule 'damon_reclaim_timer'.  The scheduling uses
'system_wq', which is initialized in 'workqueue_init_early()'.  As kernel
parameters parsing function ('parse_args()') is called before
'workqueue_init_early()', 'enabled_store()' can be executed before
'workqueue_init_early()' and end up accessing the uninitialized
'system_wq'.  As a result, the booting hang[1].  This commit fixes the
issue by checking if the initialization is done before scheduling the
timer.

[1] https://lkml.kernel.org/20220604192222.1488-1-sj@kernel.org/

Link: https://lkml.kernel.org/r/20220604195051.1589-1-sj@kernel.org
Fixes: 059342d1dd4e ("mm/damon/reclaim: fix the timer always stays active")
Signed-off-by: SeongJae Park <sj@kernel.org>
Reported-by: Greg White <gwhite@kupulau.com>
Cc: Hailong Tu <tuhailong@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 mm/damon/reclaim.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/mm/damon/reclaim.c b/mm/damon/reclaim.c
index 8efbfb24f3a1e..4b07c29effe97 100644
--- a/mm/damon/reclaim.c
+++ b/mm/damon/reclaim.c
@@ -374,6 +374,8 @@ static void damon_reclaim_timer_fn(struct work_struct *work)
 }
 static DECLARE_DELAYED_WORK(damon_reclaim_timer, damon_reclaim_timer_fn);
 
+static bool damon_reclaim_initialized;
+
 static int enabled_store(const char *val,
 		const struct kernel_param *kp)
 {
@@ -382,6 +384,10 @@ static int enabled_store(const char *val,
 	if (rc < 0)
 		return rc;
 
+	/* system_wq might not initialized yet */
+	if (!damon_reclaim_initialized)
+		return rc;
+
 	if (enabled)
 		schedule_delayed_work(&damon_reclaim_timer, 0);
 
@@ -449,6 +455,8 @@ static int __init damon_reclaim_init(void)
 	damon_add_target(ctx, target);
 
 	schedule_delayed_work(&damon_reclaim_timer, 0);
+
+	damon_reclaim_initialized = true;
 	return 0;
 }
 
-- 
GitLab


From 515e1d86c982b169e77cfe245994d2a60fc0d012 Mon Sep 17 00:00:00 2001
From: Jarkko Sakkinen <jarkko@kernel.org>
Date: Tue, 7 Jun 2022 19:41:39 +0300
Subject: [PATCH 0713/1731] mailmap: add alias for jarkko@profian.com

Add alias for patches that I contribute on behalf of Profian
(my current employer).

Link: https://lkml.kernel.org/r/20220607164140.1230876-1-jarkko@kernel.org
Signed-off-by: Jarkko Sakkinen <jarkko@kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 .mailmap | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.mailmap b/.mailmap
index 825fae8e6b7bd..b2967aab53597 100644
--- a/.mailmap
+++ b/.mailmap
@@ -165,6 +165,7 @@ Jan Glauber <jan.glauber@gmail.com> <jang@de.ibm.com>
 Jan Glauber <jan.glauber@gmail.com> <jang@linux.vnet.ibm.com>
 Jan Glauber <jan.glauber@gmail.com> <jglauber@cavium.com>
 Jarkko Sakkinen <jarkko@kernel.org> <jarkko.sakkinen@linux.intel.com>
+Jarkko Sakkinen <jarkko@kernel.org> <jarkko@profian.com>
 Jason Gunthorpe <jgg@ziepe.ca> <jgg@mellanox.com>
 Jason Gunthorpe <jgg@ziepe.ca> <jgg@nvidia.com>
 Jason Gunthorpe <jgg@ziepe.ca> <jgunthorpe@obsidianresearch.com>
-- 
GitLab


From 6901c0b6df157a88721e5b71f85af4c684877949 Mon Sep 17 00:00:00 2001
From: Miaohe Lin <linmiaohe@huawei.com>
Date: Tue, 7 Jun 2022 22:51:35 +0800
Subject: [PATCH 0714/1731] MAINTAINERS: add Miaohe Lin as a memory-failure
 reviewer

I have been focusing on mm for the past two years.  e.g.  fixing bugs,
cleaning up the code and reviewing.  I would like to help maintainers and
people working on memory-failure by reviewing their work.

Let me be Cc'd on patches related to memory-failure.

Link: https://lkml.kernel.org/r/20220607145135.38670-1-linmiaohe@huawei.com
Signed-off-by: Miaohe Lin <linmiaohe@huawei.com>
Acked-by: Naoya Horiguchi <naoya.horiguchi@nec.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 1fc9ead83d2aa..96db6b61951a0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9132,6 +9132,7 @@ F:	drivers/media/platform/st/sti/hva
 
 HWPOISON MEMORY FAILURE HANDLING
 M:	Naoya Horiguchi <naoya.horiguchi@nec.com>
+R:	Miaohe Lin <linmiaohe@huawei.com>
 L:	linux-mm@kvack.org
 S:	Maintained
 F:	mm/hwpoison-inject.c
-- 
GitLab


From 7757e7627a05c01d137a7fb87ac9d1533f460d33 Mon Sep 17 00:00:00 2001
From: David Hildenbrand <david@redhat.com>
Date: Fri, 10 Jun 2022 12:12:58 +0200
Subject: [PATCH 0715/1731] MAINTAINERS: add MEMORY HOT(UN)PLUG section and add
 David as reviewer

There are certainly a lot more files that partially fall into the memory
hot(un)plug category, including parts of mm/sparse.c, mm/page_isolation.c
and mm/page_alloc.c.  Let's only add what's almost completely memory
hot(un)plug related.

Add myself as reviewer so it's easier for contributors to figure out
whom to CC.

Link: https://lkml.kernel.org/r/20220610101258.75738-1-david@redhat.com
Link: https://lkml.kernel.org/r/YqlaE/LYHwB0gpaW@localhost.localdomain
Signed-off-by: David Hildenbrand <david@redhat.com>
Acked-by: Muchun Song <songmuchun@bytedance.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Miaohe Lin <linmiaohe@huawei.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 MAINTAINERS | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 96db6b61951a0..59fbe15d469b5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12858,6 +12858,18 @@ F:	include/linux/vmalloc.h
 F:	mm/
 F:	tools/testing/selftests/vm/
 
+MEMORY HOT(UN)PLUG
+M:	David Hildenbrand <david@redhat.com>
+M:	Oscar Salvador <osalvador@suse.de>
+L:	linux-mm@kvack.org
+S:	Maintained
+F:	Documentation/admin-guide/mm/memory-hotplug.rst
+F:	Documentation/core-api/memory-hotplug.rst
+F:	drivers/base/memory.c
+F:	include/linux/memory_hotplug.h
+F:	mm/memory_hotplug.c
+F:	tools/testing/selftests/memory-hotplug/
+
 MEMORY TECHNOLOGY DEVICES (MTD)
 M:	Miquel Raynal <miquel.raynal@bootlin.com>
 M:	Richard Weinberger <richard@nod.at>
-- 
GitLab


From 8585c3971df4bc3b909b5e7e6c7656f379d2642d Mon Sep 17 00:00:00 2001
From: Abel Vesa <abelvesa@nxp.com>
Date: Sat, 11 Jun 2022 12:31:42 +0300
Subject: [PATCH 0716/1731] MAINTAINERS: update Abel Vesa's email

Use Abel Vesa's kernel.org account in maintainer entry and mailmap.

Link: https://lkml.kernel.org/r/20220611093142.202271-1-abelvesa@kernel.org
Signed-off-by: Abel Vesa <abelvesa@nxp.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 .mailmap    | 2 ++
 MAINTAINERS | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/.mailmap b/.mailmap
index b2967aab53597..dda0030573ca4 100644
--- a/.mailmap
+++ b/.mailmap
@@ -10,6 +10,8 @@
 # Please keep this list dictionary sorted.
 #
 Aaron Durbin <adurbin@google.com>
+Abel Vesa <abelvesa@kernel.org> <abel.vesa@nxp.com>
+Abel Vesa <abelvesa@kernel.org> <abelvesa@gmail.com>
 Abhinav Kumar <quic_abhinavk@quicinc.com> <abhinavk@codeaurora.org>
 Adam Oldham <oldhamca@gmail.com>
 Adam Radford <aradford@gmail.com>
diff --git a/MAINTAINERS b/MAINTAINERS
index 59fbe15d469b5..3dfb95897e167 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14274,7 +14274,7 @@ F:	drivers/iio/gyro/fxas21002c_i2c.c
 F:	drivers/iio/gyro/fxas21002c_spi.c
 
 NXP i.MX CLOCK DRIVERS
-M:	Abel Vesa <abel.vesa@nxp.com>
+M:	Abel Vesa <abelvesa@kernel.org>
 L:	linux-clk@vger.kernel.org
 L:	linux-imx@nxp.com
 S:	Maintained
-- 
GitLab


From f0a7d33a7184df3193e4bd9ef9283a0a92bed4a6 Mon Sep 17 00:00:00 2001
From: Andrew Morton <akpm@linux-foundation.org>
Date: Wed, 15 Jun 2022 14:22:44 -0700
Subject: [PATCH 0717/1731] MAINTAINERS: update MM tree references

Describe the new kernel.org location of the MM trees.

Suggested-by: David Hildenbrand <david@redhat.com>
Cc: Muchun Song <songmuchun@bytedance.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Miaohe Lin <linmiaohe@huawei.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 MAINTAINERS | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 3dfb95897e167..f3be1b26eecf9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12846,9 +12846,8 @@ M:	Andrew Morton <akpm@linux-foundation.org>
 L:	linux-mm@kvack.org
 S:	Maintained
 W:	http://www.linux-mm.org
-T:	quilt https://ozlabs.org/~akpm/mmotm/
-T:	quilt https://ozlabs.org/~akpm/mmots/
-T:	git git://github.com/hnaz/linux-mm.git
+T:	git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm
+T:	quilt git://git.kernel.org/pub/scm/linux/kernel/git/akpm/25-new
 F:	include/linux/gfp.h
 F:	include/linux/memory_hotplug.h
 F:	include/linux/mm.h
-- 
GitLab


From 8a6f62a26d1e4e6835fbd4591c2bedcfcceadb1d Mon Sep 17 00:00:00 2001
From: Huacai Chen <chenhuacai@loongson.cn>
Date: Thu, 16 Jun 2022 20:14:56 +0800
Subject: [PATCH 0718/1731] MAINTAINERS: add maillist information for LoongArch

Now there is a dedicated maillist (loongarch@lists.linux.dev) for
LoongArch, add it for better collaboration.

Link: https://lkml.kernel.org/r/20220616121456.3613470-1-chenhuacai@loongson.cn
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Reviewed-by: WANG Xuerui <git@xen0n.name>
Cc: Huacai Chen <chenhuacai@loongson.cn>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Xuefeng Li <lixuefeng@loongson.cn>
Cc: Guo Ren <guoren@kernel.org>
Cc: Xuerui Wang <kernel@xen0n.name>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index f3be1b26eecf9..95b44367f0cec 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11591,6 +11591,7 @@ F:	drivers/gpu/drm/bridge/lontium-lt8912b.c
 LOONGARCH
 M:	Huacai Chen <chenhuacai@kernel.org>
 R:	WANG Xuerui <kernel@xen0n.name>
+L:	loongarch@lists.linux.dev
 S:	Maintained
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git
 F:	arch/loongarch/
-- 
GitLab


From 327b18b7aaed5de3b548212e3ab75133bf323759 Mon Sep 17 00:00:00 2001
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
Date: Thu, 9 Jun 2022 14:33:19 +0200
Subject: [PATCH 0719/1731] mm/kfence: select random number before taking raw
 lock

The RNG uses vanilla spinlocks, not raw spinlocks, so kfence should pick
its random numbers before taking its raw spinlocks.  This also has the
nice effect of doing less work inside the lock.  It should fix a splat
that Geert saw with CONFIG_PROVE_RAW_LOCK_NESTING:

     dump_backtrace.part.0+0x98/0xc0
     show_stack+0x14/0x28
     dump_stack_lvl+0xac/0xec
     dump_stack+0x14/0x2c
     __lock_acquire+0x388/0x10a0
     lock_acquire+0x190/0x2c0
     _raw_spin_lock_irqsave+0x6c/0x94
     crng_make_state+0x148/0x1e4
     _get_random_bytes.part.0+0x4c/0xe8
     get_random_u32+0x4c/0x140
     __kfence_alloc+0x460/0x5c4
     kmem_cache_alloc_trace+0x194/0x1dc
     __kthread_create_on_node+0x5c/0x1a8
     kthread_create_on_node+0x58/0x7c
     printk_start_kthread.part.0+0x34/0xa8
     printk_activate_kthreads+0x4c/0x54
     do_one_initcall+0xec/0x278
     kernel_init_freeable+0x11c/0x214
     kernel_init+0x24/0x124
     ret_from_fork+0x10/0x20

Link: https://lkml.kernel.org/r/20220609123319.17576-1-Jason@zx2c4.com
Fixes: d4150779e60f ("random32: use real rng for non-deterministic randomness")
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Marco Elver <elver@google.com>
Reviewed-by: Petr Mladek <pmladek@suse.com>
Cc: John Ogness <john.ogness@linutronix.de>
Cc: Alexander Potapenko <glider@google.com>
Cc: Dmitry Vyukov <dvyukov@google.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 mm/kfence/core.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/mm/kfence/core.c b/mm/kfence/core.c
index 4e7cd4c8e687e..4b5e5a3d3a638 100644
--- a/mm/kfence/core.c
+++ b/mm/kfence/core.c
@@ -360,6 +360,9 @@ static void *kfence_guarded_alloc(struct kmem_cache *cache, size_t size, gfp_t g
 	unsigned long flags;
 	struct slab *slab;
 	void *addr;
+	const bool random_right_allocate = prandom_u32_max(2);
+	const bool random_fault = CONFIG_KFENCE_STRESS_TEST_FAULTS &&
+				  !prandom_u32_max(CONFIG_KFENCE_STRESS_TEST_FAULTS);
 
 	/* Try to obtain a free object. */
 	raw_spin_lock_irqsave(&kfence_freelist_lock, flags);
@@ -404,7 +407,7 @@ static void *kfence_guarded_alloc(struct kmem_cache *cache, size_t size, gfp_t g
 	 * is that the out-of-bounds accesses detected are deterministic for
 	 * such allocations.
 	 */
-	if (prandom_u32_max(2)) {
+	if (random_right_allocate) {
 		/* Allocate on the "right" side, re-calculate address. */
 		meta->addr += PAGE_SIZE - size;
 		meta->addr = ALIGN_DOWN(meta->addr, cache->align);
@@ -444,7 +447,7 @@ static void *kfence_guarded_alloc(struct kmem_cache *cache, size_t size, gfp_t g
 	if (cache->ctor)
 		cache->ctor(addr);
 
-	if (CONFIG_KFENCE_STRESS_TEST_FAULTS && !prandom_u32_max(CONFIG_KFENCE_STRESS_TEST_FAULTS))
+	if (random_fault)
 		kfence_protect(meta->addr); /* Random "faults" by protecting the object. */
 
 	atomic_long_inc(&counters[KFENCE_COUNTER_ALLOCATED]);
-- 
GitLab


From 034e5afad921f1c08c001bf147fb1ba76ae33498 Mon Sep 17 00:00:00 2001
From: Alex Williamson <alex.williamson@redhat.com>
Date: Fri, 10 Jun 2022 16:35:13 -0600
Subject: [PATCH 0720/1731] mm: re-allow pinning of zero pfns

The commit referenced below subtly and inadvertently changed the logic to
disallow pinning of zero pfns.  This breaks device assignment with vfio
and potentially various other users of gup.  Exclude the zero page test
from the negation.

Link: https://lkml.kernel.org/r/165490039431.944052.12458624139225785964.stgit@omen
Fixes: 1c563432588d ("mm: fix is_pinnable_page against a cma page")
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Acked-by: Minchan Kim <minchan@kernel.org>
Acked-by: David Hildenbrand <david@redhat.com>
Reported-by: Yishai Hadas <yishaih@nvidia.com>
Cc: Paul E. McKenney <paulmck@kernel.org>
Cc: John Hubbard <jhubbard@nvidia.com>
Cc: John Dias <joaodias@google.com>
Cc: Jason Gunthorpe <jgg@ziepe.ca>
Cc: Zhangfei Gao <zhangfei.gao@linaro.org>
Cc: Matthew Wilcox <willy@infradead.org>
Cc: Joao Martins <joao.m.martins@oracle.com>
Cc: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 include/linux/mm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/mm.h b/include/linux/mm.h
index bc8f326be0ce4..781fae17177d1 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -1600,7 +1600,7 @@ static inline bool is_pinnable_page(struct page *page)
 	if (mt == MIGRATE_CMA || mt == MIGRATE_ISOLATE)
 		return false;
 #endif
-	return !(is_zone_movable_page(page) || is_zero_pfn(page_to_pfn(page)));
+	return !is_zone_movable_page(page) || is_zero_pfn(page_to_pfn(page));
 }
 #else
 static inline bool is_pinnable_page(struct page *page)
-- 
GitLab


From df4ae285a3d5ce99d69efe81b21c4fed9bbc51b9 Mon Sep 17 00:00:00 2001
From: Yang Yang <yang.yang29@zte.com.cn>
Date: Fri, 10 Jun 2022 02:44:52 +0000
Subject: [PATCH 0721/1731] mm: memcontrol: reference to
 tools/cgroup/memcg_slabinfo.py

There is no slabinfo.py in tools/cgroup, but has memcg_slabinfo.py instead.

Link: https://lkml.kernel.org/r/20220610024451.744135-1-yang.yang29@zte.com.cn
Signed-off-by: Yang Yang <yang.yang29@zte.com.cn>
Reviewed-by: Muchun Song <songmuchun@bytedance.com>
Acked-by: Roman Gushchin <roman.gushchin@linux.dev>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 mm/memcontrol.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/mm/memcontrol.c b/mm/memcontrol.c
index abec50f31fe64..618c366a2f074 100644
--- a/mm/memcontrol.c
+++ b/mm/memcontrol.c
@@ -4859,7 +4859,7 @@ static int mem_cgroup_slab_show(struct seq_file *m, void *p)
 {
 	/*
 	 * Deprecated.
-	 * Please, take a look at tools/cgroup/slabinfo.py .
+	 * Please, take a look at tools/cgroup/memcg_slabinfo.py .
 	 */
 	return 0;
 }
-- 
GitLab


From 68d32527d340b0d13c8cf6495d6ab4332adca09a Mon Sep 17 00:00:00 2001
From: Mike Kravetz <mike.kravetz@oracle.com>
Date: Mon, 13 Jun 2022 13:36:48 -0700
Subject: [PATCH 0722/1731] hugetlbfs: zero partial pages during fallocate hole
 punch

hugetlbfs fallocate support was originally added with commit 70c3547e36f5
("hugetlbfs: add hugetlbfs_fallocate()").  Initial support only operated
on whole hugetlb pages.  This makes sense for populating files as other
interfaces such as mmap and truncate require hugetlb page size alignment.
Only operating on whole hugetlb pages for the hole punch case was a
simplification and there was no compelling use case to zero partial pages.

In a recent discussion[1] it was assumed that hugetlbfs hole punch would
zero partial hugetlb pages as that is in line with the man page
description saying 'partial filesystem blocks are zeroed'.  However, the
hugetlbfs hole punch code actually does this:

        hole_start = round_up(offset, hpage_size);
        hole_end = round_down(offset + len, hpage_size);

Modify code to zero partial hugetlb pages in hole punch range.  It is
possible that application code could note a change in behavior.  However,
that would imply the code is passing in an unaligned range and expecting
only whole pages be removed.  This is unlikely as the fallocate
documentation states the opposite.

The current hugetlbfs fallocate hole punch behavior is tested with the
libhugetlbfs test fallocate_align[2].  This test will be updated to
validate partial page zeroing.

[1] https://lore.kernel.org/linux-mm/20571829-9d3d-0b48-817c-b6b15565f651@redhat.com/
[2] https://github.com/libhugetlbfs/libhugetlbfs/blob/master/tests/fallocate_align.c

Link: https://lkml.kernel.org/r/YqeiMlZDKI1Kabfe@monkey
Signed-off-by: Mike Kravetz <mike.kravetz@oracle.com>
Reviewed-by: Muchun Song <songmuchun@bytedance.com>
Cc: David Hildenbrand <david@redhat.com>
Cc: Naoya Horiguchi <naoya.horiguchi@linux.dev>
Cc: Axel Rasmussen <axelrasmussen@google.com>
Cc: Dave Hansen <dave.hansen@intel.com>
Cc: Michal Hocko <mhocko@suse.com>
Cc: Matthew Wilcox <willy@infradead.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 fs/hugetlbfs/inode.c | 68 ++++++++++++++++++++++++++++++++++----------
 1 file changed, 53 insertions(+), 15 deletions(-)

diff --git a/fs/hugetlbfs/inode.c b/fs/hugetlbfs/inode.c
index 62408047e8d7b..02eb72351b15b 100644
--- a/fs/hugetlbfs/inode.c
+++ b/fs/hugetlbfs/inode.c
@@ -600,41 +600,79 @@ static void hugetlb_vmtruncate(struct inode *inode, loff_t offset)
 	remove_inode_hugepages(inode, offset, LLONG_MAX);
 }
 
+static void hugetlbfs_zero_partial_page(struct hstate *h,
+					struct address_space *mapping,
+					loff_t start,
+					loff_t end)
+{
+	pgoff_t idx = start >> huge_page_shift(h);
+	struct folio *folio;
+
+	folio = filemap_lock_folio(mapping, idx);
+	if (!folio)
+		return;
+
+	start = start & ~huge_page_mask(h);
+	end = end & ~huge_page_mask(h);
+	if (!end)
+		end = huge_page_size(h);
+
+	folio_zero_segment(folio, (size_t)start, (size_t)end);
+
+	folio_unlock(folio);
+	folio_put(folio);
+}
+
 static long hugetlbfs_punch_hole(struct inode *inode, loff_t offset, loff_t len)
 {
+	struct hugetlbfs_inode_info *info = HUGETLBFS_I(inode);
+	struct address_space *mapping = inode->i_mapping;
 	struct hstate *h = hstate_inode(inode);
 	loff_t hpage_size = huge_page_size(h);
 	loff_t hole_start, hole_end;
 
 	/*
-	 * For hole punch round up the beginning offset of the hole and
-	 * round down the end.
+	 * hole_start and hole_end indicate the full pages within the hole.
 	 */
 	hole_start = round_up(offset, hpage_size);
 	hole_end = round_down(offset + len, hpage_size);
 
-	if (hole_end > hole_start) {
-		struct address_space *mapping = inode->i_mapping;
-		struct hugetlbfs_inode_info *info = HUGETLBFS_I(inode);
+	inode_lock(inode);
 
-		inode_lock(inode);
+	/* protected by i_rwsem */
+	if (info->seals & (F_SEAL_WRITE | F_SEAL_FUTURE_WRITE)) {
+		inode_unlock(inode);
+		return -EPERM;
+	}
 
-		/* protected by i_rwsem */
-		if (info->seals & (F_SEAL_WRITE | F_SEAL_FUTURE_WRITE)) {
-			inode_unlock(inode);
-			return -EPERM;
-		}
+	i_mmap_lock_write(mapping);
+
+	/* If range starts before first full page, zero partial page. */
+	if (offset < hole_start)
+		hugetlbfs_zero_partial_page(h, mapping,
+				offset, min(offset + len, hole_start));
 
-		i_mmap_lock_write(mapping);
+	/* Unmap users of full pages in the hole. */
+	if (hole_end > hole_start) {
 		if (!RB_EMPTY_ROOT(&mapping->i_mmap.rb_root))
 			hugetlb_vmdelete_list(&mapping->i_mmap,
 					      hole_start >> PAGE_SHIFT,
 					      hole_end >> PAGE_SHIFT, 0);
-		i_mmap_unlock_write(mapping);
-		remove_inode_hugepages(inode, hole_start, hole_end);
-		inode_unlock(inode);
 	}
 
+	/* If range extends beyond last full page, zero partial page. */
+	if ((offset + len) > hole_end && (offset + len) > hole_start)
+		hugetlbfs_zero_partial_page(h, mapping,
+				hole_end, offset + len);
+
+	i_mmap_unlock_write(mapping);
+
+	/* Remove full pages from the file. */
+	if (hole_end > hole_start)
+		remove_inode_hugepages(inode, hole_start, hole_end);
+
+	inode_unlock(inode);
+
 	return 0;
 }
 
-- 
GitLab


From 67f22ba7750f940bcd7e1b12720896c505c2d63f Mon Sep 17 00:00:00 2001
From: zhenwei pi <pizhenwei@bytedance.com>
Date: Wed, 15 Jun 2022 17:32:09 +0800
Subject: [PATCH 0723/1731] mm/memory-failure: disable unpoison once hw error
 happens

Currently unpoison_memory(unsigned long pfn) is designed for soft
poison(hwpoison-inject) only.  Since 17fae1294ad9d, the KPTE gets cleared
on a x86 platform once hardware memory corrupts.

Unpoisoning a hardware corrupted page puts page back buddy only, the
kernel has a chance to access the page with *NOT PRESENT* KPTE.  This
leads BUG during accessing on the corrupted KPTE.

Suggested by David&Naoya, disable unpoison mechanism when a real HW error
happens to avoid BUG like this:

 Unpoison: Software-unpoisoned page 0x61234
 BUG: unable to handle page fault for address: ffff888061234000
 #PF: supervisor write access in kernel mode
 #PF: error_code(0x0002) - not-present page
 PGD 2c01067 P4D 2c01067 PUD 107267063 PMD 10382b063 PTE 800fffff9edcb062
 Oops: 0002 [#1] PREEMPT SMP NOPTI
 CPU: 4 PID: 26551 Comm: stress Kdump: loaded Tainted: G   M       OE     5.18.0.bm.1-amd64 #7
 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996) ...
 RIP: 0010:clear_page_erms+0x7/0x10
 Code: ...
 RSP: 0000:ffffc90001107bc8 EFLAGS: 00010246
 RAX: 0000000000000000 RBX: 0000000000000901 RCX: 0000000000001000
 RDX: ffffea0001848d00 RSI: ffffea0001848d40 RDI: ffff888061234000
 RBP: ffffea0001848d00 R08: 0000000000000901 R09: 0000000000001276
 R10: 0000000000000003 R11: 0000000000000000 R12: 0000000000000001
 R13: 0000000000000000 R14: 0000000000140dca R15: 0000000000000001
 FS:  00007fd8b2333740(0000) GS:ffff88813fd00000(0000) knlGS:0000000000000000
 CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
 CR2: ffff888061234000 CR3: 00000001023d2005 CR4: 0000000000770ee0
 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
 PKRU: 55555554
 Call Trace:
  <TASK>
  prep_new_page+0x151/0x170
  get_page_from_freelist+0xca0/0xe20
  ? sysvec_apic_timer_interrupt+0xab/0xc0
  ? asm_sysvec_apic_timer_interrupt+0x1b/0x20
  __alloc_pages+0x17e/0x340
  __folio_alloc+0x17/0x40
  vma_alloc_folio+0x84/0x280
  __handle_mm_fault+0x8d4/0xeb0
  handle_mm_fault+0xd5/0x2a0
  do_user_addr_fault+0x1d0/0x680
  ? kvm_read_and_reset_apf_flags+0x3b/0x50
  exc_page_fault+0x78/0x170
  asm_exc_page_fault+0x27/0x30

Link: https://lkml.kernel.org/r/20220615093209.259374-2-pizhenwei@bytedance.com
Fixes: 847ce401df392 ("HWPOISON: Add unpoisoning support")
Fixes: 17fae1294ad9d ("x86/{mce,mm}: Unmap the entire page if the whole page is affected and poisoned")
Signed-off-by: zhenwei pi <pizhenwei@bytedance.com>
Acked-by: David Hildenbrand <david@redhat.com>
Acked-by: Naoya Horiguchi <naoya.horiguchi@nec.com>
Reviewed-by: Miaohe Lin <linmiaohe@huawei.com>
Reviewed-by: Oscar Salvador <osalvador@suse.de>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: <stable@vger.kernel.org>	[5.8+]
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 Documentation/vm/hwpoison.rst |  3 ++-
 drivers/base/memory.c         |  2 +-
 include/linux/mm.h            |  1 +
 mm/hwpoison-inject.c          |  2 +-
 mm/madvise.c                  |  2 +-
 mm/memory-failure.c           | 12 ++++++++++++
 6 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/Documentation/vm/hwpoison.rst b/Documentation/vm/hwpoison.rst
index c742de1769d18..b9d5253c13057 100644
--- a/Documentation/vm/hwpoison.rst
+++ b/Documentation/vm/hwpoison.rst
@@ -120,7 +120,8 @@ Testing
   unpoison-pfn
 	Software-unpoison page at PFN echoed into this file. This way
 	a page can be reused again.  This only works for Linux
-	injected failures, not for real memory failures.
+	injected failures, not for real memory failures. Once any hardware
+	memory failure happens, this feature is disabled.
 
   Note these injection interfaces are not stable and might change between
   kernel versions
diff --git a/drivers/base/memory.c b/drivers/base/memory.c
index 084d67fd55cc8..bc60c9cd32308 100644
--- a/drivers/base/memory.c
+++ b/drivers/base/memory.c
@@ -558,7 +558,7 @@ static ssize_t hard_offline_page_store(struct device *dev,
 	if (kstrtoull(buf, 0, &pfn) < 0)
 		return -EINVAL;
 	pfn >>= PAGE_SHIFT;
-	ret = memory_failure(pfn, 0);
+	ret = memory_failure(pfn, MF_SW_SIMULATED);
 	if (ret == -EOPNOTSUPP)
 		ret = 0;
 	return ret ? ret : count;
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 781fae17177d1..cf3d0d673f6be 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -3232,6 +3232,7 @@ enum mf_flags {
 	MF_MUST_KILL = 1 << 2,
 	MF_SOFT_OFFLINE = 1 << 3,
 	MF_UNPOISON = 1 << 4,
+	MF_SW_SIMULATED = 1 << 5,
 };
 extern int memory_failure(unsigned long pfn, int flags);
 extern void memory_failure_queue(unsigned long pfn, int flags);
diff --git a/mm/hwpoison-inject.c b/mm/hwpoison-inject.c
index 5c0cddd815059..65e242b5a4327 100644
--- a/mm/hwpoison-inject.c
+++ b/mm/hwpoison-inject.c
@@ -48,7 +48,7 @@ static int hwpoison_inject(void *data, u64 val)
 
 inject:
 	pr_info("Injecting memory failure at pfn %#lx\n", pfn);
-	err = memory_failure(pfn, 0);
+	err = memory_failure(pfn, MF_SW_SIMULATED);
 	return (err == -EOPNOTSUPP) ? 0 : err;
 }
 
diff --git a/mm/madvise.c b/mm/madvise.c
index d7b4f26029491..0316bbc6441b2 100644
--- a/mm/madvise.c
+++ b/mm/madvise.c
@@ -1112,7 +1112,7 @@ static int madvise_inject_error(int behavior,
 		} else {
 			pr_info("Injecting memory failure for pfn %#lx at process virtual address %#lx\n",
 				 pfn, start);
-			ret = memory_failure(pfn, MF_COUNT_INCREASED);
+			ret = memory_failure(pfn, MF_COUNT_INCREASED | MF_SW_SIMULATED);
 			if (ret == -EOPNOTSUPP)
 				ret = 0;
 		}
diff --git a/mm/memory-failure.c b/mm/memory-failure.c
index b85661cbdc4aa..da39ec8afca85 100644
--- a/mm/memory-failure.c
+++ b/mm/memory-failure.c
@@ -69,6 +69,8 @@ int sysctl_memory_failure_recovery __read_mostly = 1;
 
 atomic_long_t num_poisoned_pages __read_mostly = ATOMIC_LONG_INIT(0);
 
+static bool hw_memory_failure __read_mostly = false;
+
 static bool __page_handle_poison(struct page *page)
 {
 	int ret;
@@ -1768,6 +1770,9 @@ int memory_failure(unsigned long pfn, int flags)
 
 	mutex_lock(&mf_mutex);
 
+	if (!(flags & MF_SW_SIMULATED))
+		hw_memory_failure = true;
+
 	p = pfn_to_online_page(pfn);
 	if (!p) {
 		res = arch_memory_failure(pfn, flags);
@@ -2103,6 +2108,13 @@ int unpoison_memory(unsigned long pfn)
 
 	mutex_lock(&mf_mutex);
 
+	if (hw_memory_failure) {
+		unpoison_pr_info("Unpoison: Disabled after HW memory failure %#lx\n",
+				 pfn, &unpoison_rs);
+		ret = -EOPNOTSUPP;
+		goto unlock_mutex;
+	}
+
 	if (!PageHWPoison(p)) {
 		unpoison_pr_info("Unpoison: Page was already unpoisoned %#lx\n",
 				 pfn, &unpoison_rs);
-- 
GitLab


From e67679cc4264cf9b318af4e8616eaa2a7565db1f Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 16 Jun 2022 00:50:12 +0200
Subject: [PATCH 0724/1731] mailmap: add entry for Christian Marangi

Add entry to map ansuelsmth@gmail.com to the unique identity of
Christian Marangi.

Link: https://lkml.kernel.org/r/20220615225012.18782-1-ansuelsmth@gmail.com
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Cc: Jens Axboe <axboe@kernel.dk>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 .mailmap | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.mailmap b/.mailmap
index dda0030573ca4..2ed1cf8691753 100644
--- a/.mailmap
+++ b/.mailmap
@@ -87,6 +87,7 @@ Christian Borntraeger <borntraeger@linux.ibm.com> <borntrae@de.ibm.com>
 Christian Brauner <brauner@kernel.org> <christian@brauner.io>
 Christian Brauner <brauner@kernel.org> <christian.brauner@canonical.com>
 Christian Brauner <brauner@kernel.org> <christian.brauner@ubuntu.com>
+Christian Marangi <ansuelsmth@gmail.com>
 Christophe Ricard <christophe.ricard@gmail.com>
 Christoph Hellwig <hch@lst.de>
 Colin Ian King <colin.king@intel.com> <colin.king@canonical.com>
-- 
GitLab


From ad8848535e97f4a5374fc68f7a5d16e2565940cc Mon Sep 17 00:00:00 2001
From: Jiri Olsa <jolsa@kernel.org>
Date: Wed, 15 Jun 2022 13:21:15 +0200
Subject: [PATCH 0725/1731] selftests/bpf: Shuffle cookies symbols in kprobe
 multi test

There's a kernel bug that causes cookies to be misplaced and
the reason we did not catch this with this test is that we
provide bpf_fentry_test* functions already sorted by name.

Shuffling function bpf_fentry_test2 deeper in the list and
keeping the current cookie values as before will trigger
the bug.

The kernel fix is coming in following changes.

Acked-by: Song Liu <songliubraving@fb.com>
Signed-off-by: Jiri Olsa <jolsa@kernel.org>
Link: https://lore.kernel.org/r/20220615112118.497303-2-jolsa@kernel.org
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
---
 .../selftests/bpf/prog_tests/bpf_cookie.c     | 78 +++++++++----------
 .../selftests/bpf/progs/kprobe_multi.c        | 24 +++---
 2 files changed, 51 insertions(+), 51 deletions(-)

diff --git a/tools/testing/selftests/bpf/prog_tests/bpf_cookie.c b/tools/testing/selftests/bpf/prog_tests/bpf_cookie.c
index 83ef55e3caa4a..2974b44f80faf 100644
--- a/tools/testing/selftests/bpf/prog_tests/bpf_cookie.c
+++ b/tools/testing/selftests/bpf/prog_tests/bpf_cookie.c
@@ -121,24 +121,24 @@ static void kprobe_multi_link_api_subtest(void)
 })
 
 	GET_ADDR("bpf_fentry_test1", addrs[0]);
-	GET_ADDR("bpf_fentry_test2", addrs[1]);
-	GET_ADDR("bpf_fentry_test3", addrs[2]);
-	GET_ADDR("bpf_fentry_test4", addrs[3]);
-	GET_ADDR("bpf_fentry_test5", addrs[4]);
-	GET_ADDR("bpf_fentry_test6", addrs[5]);
-	GET_ADDR("bpf_fentry_test7", addrs[6]);
+	GET_ADDR("bpf_fentry_test3", addrs[1]);
+	GET_ADDR("bpf_fentry_test4", addrs[2]);
+	GET_ADDR("bpf_fentry_test5", addrs[3]);
+	GET_ADDR("bpf_fentry_test6", addrs[4]);
+	GET_ADDR("bpf_fentry_test7", addrs[5]);
+	GET_ADDR("bpf_fentry_test2", addrs[6]);
 	GET_ADDR("bpf_fentry_test8", addrs[7]);
 
 #undef GET_ADDR
 
-	cookies[0] = 1;
-	cookies[1] = 2;
-	cookies[2] = 3;
-	cookies[3] = 4;
-	cookies[4] = 5;
-	cookies[5] = 6;
-	cookies[6] = 7;
-	cookies[7] = 8;
+	cookies[0] = 1; /* bpf_fentry_test1 */
+	cookies[1] = 2; /* bpf_fentry_test3 */
+	cookies[2] = 3; /* bpf_fentry_test4 */
+	cookies[3] = 4; /* bpf_fentry_test5 */
+	cookies[4] = 5; /* bpf_fentry_test6 */
+	cookies[5] = 6; /* bpf_fentry_test7 */
+	cookies[6] = 7; /* bpf_fentry_test2 */
+	cookies[7] = 8; /* bpf_fentry_test8 */
 
 	opts.kprobe_multi.addrs = (const unsigned long *) &addrs;
 	opts.kprobe_multi.cnt = ARRAY_SIZE(addrs);
@@ -149,14 +149,14 @@ static void kprobe_multi_link_api_subtest(void)
 	if (!ASSERT_GE(link1_fd, 0, "link1_fd"))
 		goto cleanup;
 
-	cookies[0] = 8;
-	cookies[1] = 7;
-	cookies[2] = 6;
-	cookies[3] = 5;
-	cookies[4] = 4;
-	cookies[5] = 3;
-	cookies[6] = 2;
-	cookies[7] = 1;
+	cookies[0] = 8; /* bpf_fentry_test1 */
+	cookies[1] = 7; /* bpf_fentry_test3 */
+	cookies[2] = 6; /* bpf_fentry_test4 */
+	cookies[3] = 5; /* bpf_fentry_test5 */
+	cookies[4] = 4; /* bpf_fentry_test6 */
+	cookies[5] = 3; /* bpf_fentry_test7 */
+	cookies[6] = 2; /* bpf_fentry_test2 */
+	cookies[7] = 1; /* bpf_fentry_test8 */
 
 	opts.kprobe_multi.flags = BPF_F_KPROBE_MULTI_RETURN;
 	prog_fd = bpf_program__fd(skel->progs.test_kretprobe);
@@ -181,12 +181,12 @@ static void kprobe_multi_attach_api_subtest(void)
 	struct kprobe_multi *skel = NULL;
 	const char *syms[8] = {
 		"bpf_fentry_test1",
-		"bpf_fentry_test2",
 		"bpf_fentry_test3",
 		"bpf_fentry_test4",
 		"bpf_fentry_test5",
 		"bpf_fentry_test6",
 		"bpf_fentry_test7",
+		"bpf_fentry_test2",
 		"bpf_fentry_test8",
 	};
 	__u64 cookies[8];
@@ -198,14 +198,14 @@ static void kprobe_multi_attach_api_subtest(void)
 	skel->bss->pid = getpid();
 	skel->bss->test_cookie = true;
 
-	cookies[0] = 1;
-	cookies[1] = 2;
-	cookies[2] = 3;
-	cookies[3] = 4;
-	cookies[4] = 5;
-	cookies[5] = 6;
-	cookies[6] = 7;
-	cookies[7] = 8;
+	cookies[0] = 1; /* bpf_fentry_test1 */
+	cookies[1] = 2; /* bpf_fentry_test3 */
+	cookies[2] = 3; /* bpf_fentry_test4 */
+	cookies[3] = 4; /* bpf_fentry_test5 */
+	cookies[4] = 5; /* bpf_fentry_test6 */
+	cookies[5] = 6; /* bpf_fentry_test7 */
+	cookies[6] = 7; /* bpf_fentry_test2 */
+	cookies[7] = 8; /* bpf_fentry_test8 */
 
 	opts.syms = syms;
 	opts.cnt = ARRAY_SIZE(syms);
@@ -216,14 +216,14 @@ static void kprobe_multi_attach_api_subtest(void)
 	if (!ASSERT_OK_PTR(link1, "bpf_program__attach_kprobe_multi_opts"))
 		goto cleanup;
 
-	cookies[0] = 8;
-	cookies[1] = 7;
-	cookies[2] = 6;
-	cookies[3] = 5;
-	cookies[4] = 4;
-	cookies[5] = 3;
-	cookies[6] = 2;
-	cookies[7] = 1;
+	cookies[0] = 8; /* bpf_fentry_test1 */
+	cookies[1] = 7; /* bpf_fentry_test3 */
+	cookies[2] = 6; /* bpf_fentry_test4 */
+	cookies[3] = 5; /* bpf_fentry_test5 */
+	cookies[4] = 4; /* bpf_fentry_test6 */
+	cookies[5] = 3; /* bpf_fentry_test7 */
+	cookies[6] = 2; /* bpf_fentry_test2 */
+	cookies[7] = 1; /* bpf_fentry_test8 */
 
 	opts.retprobe = true;
 
diff --git a/tools/testing/selftests/bpf/progs/kprobe_multi.c b/tools/testing/selftests/bpf/progs/kprobe_multi.c
index 93510f4f0f3aa..08f95a8155d1b 100644
--- a/tools/testing/selftests/bpf/progs/kprobe_multi.c
+++ b/tools/testing/selftests/bpf/progs/kprobe_multi.c
@@ -54,21 +54,21 @@ static void kprobe_multi_check(void *ctx, bool is_return)
 
 	if (is_return) {
 		SET(kretprobe_test1_result, &bpf_fentry_test1, 8);
-		SET(kretprobe_test2_result, &bpf_fentry_test2, 7);
-		SET(kretprobe_test3_result, &bpf_fentry_test3, 6);
-		SET(kretprobe_test4_result, &bpf_fentry_test4, 5);
-		SET(kretprobe_test5_result, &bpf_fentry_test5, 4);
-		SET(kretprobe_test6_result, &bpf_fentry_test6, 3);
-		SET(kretprobe_test7_result, &bpf_fentry_test7, 2);
+		SET(kretprobe_test2_result, &bpf_fentry_test2, 2);
+		SET(kretprobe_test3_result, &bpf_fentry_test3, 7);
+		SET(kretprobe_test4_result, &bpf_fentry_test4, 6);
+		SET(kretprobe_test5_result, &bpf_fentry_test5, 5);
+		SET(kretprobe_test6_result, &bpf_fentry_test6, 4);
+		SET(kretprobe_test7_result, &bpf_fentry_test7, 3);
 		SET(kretprobe_test8_result, &bpf_fentry_test8, 1);
 	} else {
 		SET(kprobe_test1_result, &bpf_fentry_test1, 1);
-		SET(kprobe_test2_result, &bpf_fentry_test2, 2);
-		SET(kprobe_test3_result, &bpf_fentry_test3, 3);
-		SET(kprobe_test4_result, &bpf_fentry_test4, 4);
-		SET(kprobe_test5_result, &bpf_fentry_test5, 5);
-		SET(kprobe_test6_result, &bpf_fentry_test6, 6);
-		SET(kprobe_test7_result, &bpf_fentry_test7, 7);
+		SET(kprobe_test2_result, &bpf_fentry_test2, 7);
+		SET(kprobe_test3_result, &bpf_fentry_test3, 2);
+		SET(kprobe_test4_result, &bpf_fentry_test4, 3);
+		SET(kprobe_test5_result, &bpf_fentry_test5, 4);
+		SET(kprobe_test6_result, &bpf_fentry_test6, 5);
+		SET(kprobe_test7_result, &bpf_fentry_test7, 6);
 		SET(kprobe_test8_result, &bpf_fentry_test8, 8);
 	}
 
-- 
GitLab


From eb1b2985fe5c5f02e43e4c0d47bbe7ed835007f3 Mon Sep 17 00:00:00 2001
From: Jiri Olsa <jolsa@kernel.org>
Date: Wed, 15 Jun 2022 13:21:16 +0200
Subject: [PATCH 0726/1731] ftrace: Keep address offset in
 ftrace_lookup_symbols

We want to store the resolved address on the same index as
the symbol string, because that's the user (bpf kprobe link)
code assumption.

Also making sure we don't store duplicates that might be
present in kallsyms.

Acked-by: Song Liu <songliubraving@fb.com>
Acked-by: Steven Rostedt (Google) <rostedt@goodmis.org>
Fixes: bed0d9a50dac ("ftrace: Add ftrace_lookup_symbols function")
Signed-off-by: Jiri Olsa <jolsa@kernel.org>
Link: https://lore.kernel.org/r/20220615112118.497303-3-jolsa@kernel.org
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
---
 kernel/trace/ftrace.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c
index e750fe141a606..601ccf1b2f091 100644
--- a/kernel/trace/ftrace.c
+++ b/kernel/trace/ftrace.c
@@ -8029,15 +8029,23 @@ static int kallsyms_callback(void *data, const char *name,
 			     struct module *mod, unsigned long addr)
 {
 	struct kallsyms_data *args = data;
+	const char **sym;
+	int idx;
 
-	if (!bsearch(&name, args->syms, args->cnt, sizeof(*args->syms), symbols_cmp))
+	sym = bsearch(&name, args->syms, args->cnt, sizeof(*args->syms), symbols_cmp);
+	if (!sym)
+		return 0;
+
+	idx = sym - args->syms;
+	if (args->addrs[idx])
 		return 0;
 
 	addr = ftrace_location(addr);
 	if (!addr)
 		return 0;
 
-	args->addrs[args->found++] = addr;
+	args->addrs[idx] = addr;
+	args->found++;
 	return args->found == args->cnt ? 1 : 0;
 }
 
@@ -8062,6 +8070,7 @@ int ftrace_lookup_symbols(const char **sorted_syms, size_t cnt, unsigned long *a
 	struct kallsyms_data args;
 	int err;
 
+	memset(addrs, 0, sizeof(*addrs) * cnt);
 	args.addrs = addrs;
 	args.syms = sorted_syms;
 	args.cnt = cnt;
-- 
GitLab


From eb5fb0325698d05f0bf78d322de82c451a3685a2 Mon Sep 17 00:00:00 2001
From: Jiri Olsa <jolsa@kernel.org>
Date: Wed, 15 Jun 2022 13:21:17 +0200
Subject: [PATCH 0727/1731] bpf: Force cookies array to follow symbols sorting

When user specifies symbols and cookies for kprobe_multi link
interface it's very likely the cookies will be misplaced and
returned to wrong functions (via get_attach_cookie helper).

The reason is that to resolve the provided functions we sort
them before passing them to ftrace_lookup_symbols, but we do
not do the same sort on the cookie values.

Fixing this by using sort_r function with custom swap callback
that swaps cookie values as well.

Fixes: 0236fec57a15 ("bpf: Resolve symbols with ftrace_lookup_symbols for kprobe multi link")
Signed-off-by: Jiri Olsa <jolsa@kernel.org>
Link: https://lore.kernel.org/r/20220615112118.497303-4-jolsa@kernel.org
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
---
 kernel/trace/bpf_trace.c | 60 ++++++++++++++++++++++++++++++----------
 1 file changed, 45 insertions(+), 15 deletions(-)

diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c
index 7a13e6ac6327c..88589d74a892e 100644
--- a/kernel/trace/bpf_trace.c
+++ b/kernel/trace/bpf_trace.c
@@ -2423,7 +2423,7 @@ kprobe_multi_link_handler(struct fprobe *fp, unsigned long entry_ip,
 	kprobe_multi_link_prog_run(link, entry_ip, regs);
 }
 
-static int symbols_cmp(const void *a, const void *b)
+static int symbols_cmp_r(const void *a, const void *b, const void *priv)
 {
 	const char **str_a = (const char **) a;
 	const char **str_b = (const char **) b;
@@ -2431,6 +2431,28 @@ static int symbols_cmp(const void *a, const void *b)
 	return strcmp(*str_a, *str_b);
 }
 
+struct multi_symbols_sort {
+	const char **funcs;
+	u64 *cookies;
+};
+
+static void symbols_swap_r(void *a, void *b, int size, const void *priv)
+{
+	const struct multi_symbols_sort *data = priv;
+	const char **name_a = a, **name_b = b;
+
+	swap(*name_a, *name_b);
+
+	/* If defined, swap also related cookies. */
+	if (data->cookies) {
+		u64 *cookie_a, *cookie_b;
+
+		cookie_a = data->cookies + (name_a - data->funcs);
+		cookie_b = data->cookies + (name_b - data->funcs);
+		swap(*cookie_a, *cookie_b);
+	}
+}
+
 int bpf_kprobe_multi_link_attach(const union bpf_attr *attr, struct bpf_prog *prog)
 {
 	struct bpf_kprobe_multi_link *link = NULL;
@@ -2468,38 +2490,46 @@ int bpf_kprobe_multi_link_attach(const union bpf_attr *attr, struct bpf_prog *pr
 	if (!addrs)
 		return -ENOMEM;
 
+	ucookies = u64_to_user_ptr(attr->link_create.kprobe_multi.cookies);
+	if (ucookies) {
+		cookies = kvmalloc_array(cnt, sizeof(*addrs), GFP_KERNEL);
+		if (!cookies) {
+			err = -ENOMEM;
+			goto error;
+		}
+		if (copy_from_user(cookies, ucookies, size)) {
+			err = -EFAULT;
+			goto error;
+		}
+	}
+
 	if (uaddrs) {
 		if (copy_from_user(addrs, uaddrs, size)) {
 			err = -EFAULT;
 			goto error;
 		}
 	} else {
+		struct multi_symbols_sort data = {
+			.cookies = cookies,
+		};
 		struct user_syms us;
 
 		err = copy_user_syms(&us, usyms, cnt);
 		if (err)
 			goto error;
 
-		sort(us.syms, cnt, sizeof(*us.syms), symbols_cmp, NULL);
+		if (cookies)
+			data.funcs = us.syms;
+
+		sort_r(us.syms, cnt, sizeof(*us.syms), symbols_cmp_r,
+		       symbols_swap_r, &data);
+
 		err = ftrace_lookup_symbols(us.syms, cnt, addrs);
 		free_user_syms(&us);
 		if (err)
 			goto error;
 	}
 
-	ucookies = u64_to_user_ptr(attr->link_create.kprobe_multi.cookies);
-	if (ucookies) {
-		cookies = kvmalloc_array(cnt, sizeof(*addrs), GFP_KERNEL);
-		if (!cookies) {
-			err = -ENOMEM;
-			goto error;
-		}
-		if (copy_from_user(cookies, ucookies, size)) {
-			err = -EFAULT;
-			goto error;
-		}
-	}
-
 	link = kzalloc(sizeof(*link), GFP_KERNEL);
 	if (!link) {
 		err = -ENOMEM;
-- 
GitLab


From 730067022c0137691b27726377c2d088f7f8e33c Mon Sep 17 00:00:00 2001
From: Jiri Olsa <jolsa@kernel.org>
Date: Wed, 15 Jun 2022 13:21:18 +0200
Subject: [PATCH 0728/1731] selftest/bpf: Fix kprobe_multi bench test

With [1] the available_filter_functions file contains records
starting with __ftrace_invalid_address___ and marking disabled
entries.

We need to filter them out for the bench test to pass only
resolvable symbols to kernel.

[1] commit b39181f7c690 ("ftrace: Add FTRACE_MCOUNT_MAX_OFFSET to avoid adding weak function")

Fixes: b39181f7c690 ("ftrace: Add FTRACE_MCOUNT_MAX_OFFSET to avoid adding weak function")
Signed-off-by: Jiri Olsa <jolsa@kernel.org>
Link: https://lore.kernel.org/r/20220615112118.497303-5-jolsa@kernel.org
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
---
 tools/testing/selftests/bpf/prog_tests/kprobe_multi_test.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tools/testing/selftests/bpf/prog_tests/kprobe_multi_test.c b/tools/testing/selftests/bpf/prog_tests/kprobe_multi_test.c
index 586dc52d6fb96..5b93d5d0bd931 100644
--- a/tools/testing/selftests/bpf/prog_tests/kprobe_multi_test.c
+++ b/tools/testing/selftests/bpf/prog_tests/kprobe_multi_test.c
@@ -364,6 +364,9 @@ static int get_syms(char ***symsp, size_t *cntp)
 			continue;
 		if (!strncmp(name, "rcu_", 4))
 			continue;
+		if (!strncmp(name, "__ftrace_invalid_address__",
+			     sizeof("__ftrace_invalid_address__") - 1))
+			continue;
 		err = hashmap__add(map, name, NULL);
 		if (err) {
 			free(name);
-- 
GitLab


From 9b7fd1670a94a57d974795acebde843a5c1a354e Mon Sep 17 00:00:00 2001
From: Claudiu Manoil <claudiu.manoil@nxp.com>
Date: Fri, 10 Jun 2022 11:40:37 +0300
Subject: [PATCH 0729/1731] phy: aquantia: Fix AN when higher speeds than 1G
 are not advertised

Even when the eth port is resticted to work with speeds not higher than 1G,
and so the eth driver is requesting the phy (via phylink) to advertise up
to 1000BASET support, the aquantia phy device is still advertising for 2.5G
and 5G speeds.
Clear these advertising defaults when requested.

Cc: Ondrej Spacek <ondrej.spacek@nxp.com>
Fixes: 09c4c57f7bc41 ("net: phy: aquantia: add support for auto-negotiation configuration")
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Link: https://lore.kernel.org/r/20220610084037.7625-1-claudiu.manoil@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/phy/aquantia_main.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/aquantia_main.c b/drivers/net/phy/aquantia_main.c
index a8db1a19011bd..c7047f5d7a9b0 100644
--- a/drivers/net/phy/aquantia_main.c
+++ b/drivers/net/phy/aquantia_main.c
@@ -34,6 +34,8 @@
 #define MDIO_AN_VEND_PROV			0xc400
 #define MDIO_AN_VEND_PROV_1000BASET_FULL	BIT(15)
 #define MDIO_AN_VEND_PROV_1000BASET_HALF	BIT(14)
+#define MDIO_AN_VEND_PROV_5000BASET_FULL	BIT(11)
+#define MDIO_AN_VEND_PROV_2500BASET_FULL	BIT(10)
 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN		BIT(4)
 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK	GENMASK(3, 0)
 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT	4
@@ -231,9 +233,20 @@ static int aqr_config_aneg(struct phy_device *phydev)
 			      phydev->advertising))
 		reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
 
+	/* Handle the case when the 2.5G and 5G speeds are not advertised */
+	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
+			      phydev->advertising))
+		reg |= MDIO_AN_VEND_PROV_2500BASET_FULL;
+
+	if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
+			      phydev->advertising))
+		reg |= MDIO_AN_VEND_PROV_5000BASET_FULL;
+
 	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
 				     MDIO_AN_VEND_PROV_1000BASET_HALF |
-				     MDIO_AN_VEND_PROV_1000BASET_FULL, reg);
+				     MDIO_AN_VEND_PROV_1000BASET_FULL |
+				     MDIO_AN_VEND_PROV_2500BASET_FULL |
+				     MDIO_AN_VEND_PROV_5000BASET_FULL, reg);
 	if (ret < 0)
 		return ret;
 	if (ret > 0)
-- 
GitLab


From 540a92bfe6dab7310b9df2e488ba247d784d0163 Mon Sep 17 00:00:00 2001
From: Edward Wu <edwardwu@realtek.com>
Date: Fri, 17 Jun 2022 11:32:20 +0800
Subject: [PATCH 0730/1731] ata: libata: add qc->flags in
 ata_qc_complete_template tracepoint

Add flags value to check the result of ata completion

Fixes: 255c03d15a29 ("libata: Add tracepoints")
Cc: stable@vger.kernel.org
Signed-off-by: Edward Wu <edwardwu@realtek.com>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
---
 include/trace/events/libata.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/trace/events/libata.h b/include/trace/events/libata.h
index d4e631aa976fb..6025dd8ba4aa1 100644
--- a/include/trace/events/libata.h
+++ b/include/trace/events/libata.h
@@ -288,6 +288,7 @@ DECLARE_EVENT_CLASS(ata_qc_complete_template,
 		__entry->hob_feature	= qc->result_tf.hob_feature;
 		__entry->nsect		= qc->result_tf.nsect;
 		__entry->hob_nsect	= qc->result_tf.hob_nsect;
+		__entry->flags		= qc->flags;
 	),
 
 	TP_printk("ata_port=%u ata_dev=%u tag=%d flags=%s status=%s " \
-- 
GitLab


From 45c64ecf97ee370bbdbd8eed7aed9c8ff5d1b0dd Mon Sep 17 00:00:00 2001
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date: Fri, 27 May 2022 08:24:52 +0100
Subject: [PATCH 0731/1731] drm/i915: Improve user experience and driver
 robustness under SIGINT or similar

We have long standing customer complaints that pressing Ctrl-C (or to the
effect of) causes engine resets with otherwise well behaving programs.

Not only is logging engine resets during normal operation not desirable
since it creates support incidents, but more fundamentally we should avoid
going the engine reset path when we can since any engine reset introduces
a chance of harming an innocent context.

Reason for this undesirable behaviour is that the driver currently does
not distinguish between banned contexts and non-persistent contexts which
have been closed.

To fix this we add the distinction between the two reasons for revoking
contexts, which then allows the strict timeout only be applied to banned,
while innocent contexts (well behaving) can preempt cleanly and exit
without triggering the engine reset path.

Note that the added context exiting category applies both to closed non-
persistent context, and any exiting context when hangcheck has been
disabled by the user.

At the same time we rename the backend operation from 'ban' to 'revoke'
which more accurately describes the actual semantics. (There is no ban at
the backend level since banning is a concept driven by the scheduling
frontend. Backends are simply able to revoke a running context so that
is the more appropriate name chosen.)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220527072452.2225610-1-tvrtko.ursulin@linux.intel.com
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c   | 23 +++++++++++------
 drivers/gpu/drm/i915/gt/intel_context.c       | 24 ++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_context.h       | 25 +++++++++++++------
 drivers/gpu/drm/i915/gt/intel_context_types.h |  4 ++-
 .../drm/i915/gt/intel_execlists_submission.c  |  6 ++---
 .../gpu/drm/i915/gt/intel_ring_submission.c   |  7 +++---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 15 ++++++-----
 drivers/gpu/drm/i915/i915_request.c           |  2 +-
 8 files changed, 77 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index a3bb73f5d53bf..e116f82fc37c6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1367,7 +1367,8 @@ static struct intel_engine_cs *active_engine(struct intel_context *ce)
 	return engine;
 }
 
-static void kill_engines(struct i915_gem_engines *engines, bool ban)
+static void
+kill_engines(struct i915_gem_engines *engines, bool exit, bool persistent)
 {
 	struct i915_gem_engines_iter it;
 	struct intel_context *ce;
@@ -1381,9 +1382,15 @@ static void kill_engines(struct i915_gem_engines *engines, bool ban)
 	 */
 	for_each_gem_engine(ce, engines, it) {
 		struct intel_engine_cs *engine;
+		bool skip = false;
 
-		if (ban && intel_context_ban(ce, NULL))
-			continue;
+		if (exit)
+			skip = intel_context_set_exiting(ce);
+		else if (!persistent)
+			skip = intel_context_exit_nonpersistent(ce, NULL);
+
+		if (skip)
+			continue; /* Already marked. */
 
 		/*
 		 * Check the current active state of this context; if we
@@ -1395,7 +1402,7 @@ static void kill_engines(struct i915_gem_engines *engines, bool ban)
 		engine = active_engine(ce);
 
 		/* First attempt to gracefully cancel the context */
-		if (engine && !__cancel_engine(engine) && ban)
+		if (engine && !__cancel_engine(engine) && (exit || !persistent))
 			/*
 			 * If we are unable to send a preemptive pulse to bump
 			 * the context from the GPU, we have to resort to a full
@@ -1407,8 +1414,6 @@ static void kill_engines(struct i915_gem_engines *engines, bool ban)
 
 static void kill_context(struct i915_gem_context *ctx)
 {
-	bool ban = (!i915_gem_context_is_persistent(ctx) ||
-		    !ctx->i915->params.enable_hangcheck);
 	struct i915_gem_engines *pos, *next;
 
 	spin_lock_irq(&ctx->stale.lock);
@@ -1421,7 +1426,8 @@ static void kill_context(struct i915_gem_context *ctx)
 
 		spin_unlock_irq(&ctx->stale.lock);
 
-		kill_engines(pos, ban);
+		kill_engines(pos, !ctx->i915->params.enable_hangcheck,
+			     i915_gem_context_is_persistent(ctx));
 
 		spin_lock_irq(&ctx->stale.lock);
 		GEM_BUG_ON(i915_sw_fence_signaled(&pos->fence));
@@ -1467,7 +1473,8 @@ static void engines_idle_release(struct i915_gem_context *ctx,
 
 kill:
 	if (list_empty(&engines->link)) /* raced, already closed */
-		kill_engines(engines, true);
+		kill_engines(engines, true,
+			     i915_gem_context_is_persistent(ctx));
 
 	i915_sw_fence_commit(&engines->fence);
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
index 4070cb5711d88..654a092ed3d69 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -601,6 +601,30 @@ u64 intel_context_get_avg_runtime_ns(struct intel_context *ce)
 	return avg;
 }
 
+bool intel_context_ban(struct intel_context *ce, struct i915_request *rq)
+{
+	bool ret = intel_context_set_banned(ce);
+
+	trace_intel_context_ban(ce);
+
+	if (ce->ops->revoke)
+		ce->ops->revoke(ce, rq,
+				INTEL_CONTEXT_BANNED_PREEMPT_TIMEOUT_MS);
+
+	return ret;
+}
+
+bool intel_context_exit_nonpersistent(struct intel_context *ce,
+				      struct i915_request *rq)
+{
+	bool ret = intel_context_set_exiting(ce);
+
+	if (ce->ops->revoke)
+		ce->ops->revoke(ce, rq, ce->engine->props.preempt_timeout_ms);
+
+	return ret;
+}
+
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 #include "selftest_context.c"
 #endif
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h b/drivers/gpu/drm/i915/gt/intel_context.h
index b7d3214d2cdd8..8e2d70630c49e 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -25,6 +25,8 @@
 		     ##__VA_ARGS__);					\
 } while (0)
 
+#define INTEL_CONTEXT_BANNED_PREEMPT_TIMEOUT_MS (1)
+
 struct i915_gem_ww_ctx;
 
 void intel_context_init(struct intel_context *ce,
@@ -309,18 +311,27 @@ static inline bool intel_context_set_banned(struct intel_context *ce)
 	return test_and_set_bit(CONTEXT_BANNED, &ce->flags);
 }
 
-static inline bool intel_context_ban(struct intel_context *ce,
-				     struct i915_request *rq)
+bool intel_context_ban(struct intel_context *ce, struct i915_request *rq);
+
+static inline bool intel_context_is_schedulable(const struct intel_context *ce)
 {
-	bool ret = intel_context_set_banned(ce);
+	return !test_bit(CONTEXT_EXITING, &ce->flags) &&
+	       !test_bit(CONTEXT_BANNED, &ce->flags);
+}
 
-	trace_intel_context_ban(ce);
-	if (ce->ops->ban)
-		ce->ops->ban(ce, rq);
+static inline bool intel_context_is_exiting(const struct intel_context *ce)
+{
+	return test_bit(CONTEXT_EXITING, &ce->flags);
+}
 
-	return ret;
+static inline bool intel_context_set_exiting(struct intel_context *ce)
+{
+	return test_and_set_bit(CONTEXT_EXITING, &ce->flags);
 }
 
+bool intel_context_exit_nonpersistent(struct intel_context *ce,
+				      struct i915_request *rq);
+
 static inline bool
 intel_context_force_single_submission(const struct intel_context *ce)
 {
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 09f82545789f1..d2d75d9c0c8dd 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -40,7 +40,8 @@ struct intel_context_ops {
 
 	int (*alloc)(struct intel_context *ce);
 
-	void (*ban)(struct intel_context *ce, struct i915_request *rq);
+	void (*revoke)(struct intel_context *ce, struct i915_request *rq,
+		       unsigned int preempt_timeout_ms);
 
 	int (*pre_pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww, void **vaddr);
 	int (*pin)(struct intel_context *ce, void *vaddr);
@@ -122,6 +123,7 @@ struct intel_context {
 #define CONTEXT_GUC_INIT		10
 #define CONTEXT_PERMA_PIN		11
 #define CONTEXT_IS_PARKING		12
+#define CONTEXT_EXITING			13
 
 	struct {
 		u64 timeout_us;
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 2b0266cab66b9..98f1c7258cc08 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -480,9 +480,9 @@ __execlists_schedule_in(struct i915_request *rq)
 
 	if (unlikely(intel_context_is_closed(ce) &&
 		     !intel_engine_has_heartbeat(engine)))
-		intel_context_set_banned(ce);
+		intel_context_set_exiting(ce);
 
-	if (unlikely(intel_context_is_banned(ce) || bad_request(rq)))
+	if (unlikely(!intel_context_is_schedulable(ce) || bad_request(rq)))
 		reset_active(rq, engine);
 
 	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
@@ -1243,7 +1243,7 @@ static unsigned long active_preempt_timeout(struct intel_engine_cs *engine,
 
 	/* Force a fast reset for terminated contexts (ignoring sysfs!) */
 	if (unlikely(intel_context_is_banned(rq->context) || bad_request(rq)))
-		return 1;
+		return INTEL_CONTEXT_BANNED_PREEMPT_TIMEOUT_MS;
 
 	return READ_ONCE(engine->props.preempt_timeout_ms);
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index f8f279a195c0c..d5d6f1fadcae3 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -598,8 +598,9 @@ static void ring_context_reset(struct intel_context *ce)
 	clear_bit(CONTEXT_VALID_BIT, &ce->flags);
 }
 
-static void ring_context_ban(struct intel_context *ce,
-			     struct i915_request *rq)
+static void ring_context_revoke(struct intel_context *ce,
+				struct i915_request *rq,
+				unsigned int preempt_timeout_ms)
 {
 	struct intel_engine_cs *engine;
 
@@ -634,7 +635,7 @@ static const struct intel_context_ops ring_context_ops = {
 
 	.cancel_request = ring_context_cancel_request,
 
-	.ban = ring_context_ban,
+	.revoke = ring_context_revoke,
 
 	.pre_pin = ring_context_pre_pin,
 	.pin = ring_context_pin,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 5a1dfacf24ea8..e62ea35513ea9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2790,7 +2790,9 @@ static void __guc_context_set_preemption_timeout(struct intel_guc *guc,
 	__guc_context_set_context_policies(guc, &policy, true);
 }
 
-static void guc_context_ban(struct intel_context *ce, struct i915_request *rq)
+static void
+guc_context_revoke(struct intel_context *ce, struct i915_request *rq,
+		   unsigned int preempt_timeout_ms)
 {
 	struct intel_guc *guc = ce_to_guc(ce);
 	struct intel_runtime_pm *runtime_pm =
@@ -2829,7 +2831,8 @@ static void guc_context_ban(struct intel_context *ce, struct i915_request *rq)
 		 * gets kicked off the HW ASAP.
 		 */
 		with_intel_runtime_pm(runtime_pm, wakeref) {
-			__guc_context_set_preemption_timeout(guc, guc_id, 1);
+			__guc_context_set_preemption_timeout(guc, guc_id,
+							     preempt_timeout_ms);
 			__guc_context_sched_disable(guc, ce, guc_id);
 		}
 	} else {
@@ -2837,7 +2840,7 @@ static void guc_context_ban(struct intel_context *ce, struct i915_request *rq)
 			with_intel_runtime_pm(runtime_pm, wakeref)
 				__guc_context_set_preemption_timeout(guc,
 								     ce->guc_id.id,
-								     1);
+								     preempt_timeout_ms);
 		spin_unlock_irqrestore(&ce->guc_state.lock, flags);
 	}
 }
@@ -3190,7 +3193,7 @@ static const struct intel_context_ops guc_context_ops = {
 	.unpin = guc_context_unpin,
 	.post_unpin = guc_context_post_unpin,
 
-	.ban = guc_context_ban,
+	.revoke = guc_context_revoke,
 
 	.cancel_request = guc_context_cancel_request,
 
@@ -3439,7 +3442,7 @@ static const struct intel_context_ops virtual_guc_context_ops = {
 	.unpin = guc_virtual_context_unpin,
 	.post_unpin = guc_context_post_unpin,
 
-	.ban = guc_context_ban,
+	.revoke = guc_context_revoke,
 
 	.cancel_request = guc_context_cancel_request,
 
@@ -3528,7 +3531,7 @@ static const struct intel_context_ops virtual_parent_context_ops = {
 	.unpin = guc_parent_context_unpin,
 	.post_unpin = guc_context_post_unpin,
 
-	.ban = guc_context_ban,
+	.revoke = guc_context_revoke,
 
 	.cancel_request = guc_context_cancel_request,
 
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index 73d5195146b0b..c3937640b1199 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -611,7 +611,7 @@ bool __i915_request_submit(struct i915_request *request)
 		goto active;
 	}
 
-	if (unlikely(intel_context_is_banned(request->context)))
+	if (unlikely(!intel_context_is_schedulable(request->context)))
 		i915_request_set_error_once(request, -EIO);
 
 	if (unlikely(fatal_error(request->fence.error)))
-- 
GitLab


From 9f1b1d0b2242171b2891a0398def233801601c14 Mon Sep 17 00:00:00 2001
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date: Thu, 16 Jun 2022 15:00:56 +0100
Subject: [PATCH 0732/1731] drm/i915/fdinfo: Don't show engine classes not
 present

Stop displaying engine classes with no engines - it is not a huge problem
if they are shown, since the values will correctly be all zeroes, but it
does count as misleading.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Fixes: 055634e4b62f ("drm/i915: Expose client engine utilisation via fdinfo")
Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220616140056.559074-1-tvrtko.ursulin@linux.intel.com
---
 drivers/gpu/drm/i915/i915_drm_client.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drm_client.c b/drivers/gpu/drm/i915/i915_drm_client.c
index 18d38cb59923d..b09d1d3865740 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.c
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -116,8 +116,9 @@ show_client_class(struct seq_file *m,
 		total += busy_add(ctx, class);
 	rcu_read_unlock();
 
-	seq_printf(m, "drm-engine-%s:\t%llu ns\n",
-		   uabi_class_names[class], total);
+	if (capacity)
+		seq_printf(m, "drm-engine-%s:\t%llu ns\n",
+			   uabi_class_names[class], total);
 
 	if (capacity > 1)
 		seq_printf(m, "drm-engine-capacity-%s:\t%u\n",
-- 
GitLab


From dda8ad0aa8af937feb5113952fb7886c74315010 Mon Sep 17 00:00:00 2001
From: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Date: Thu, 12 May 2022 20:20:37 +0900
Subject: [PATCH 0733/1731] firewire: cdev: fix potential leak of kernel stack
 due to uninitialized value

Recent change brings potential leak of value on kernel stack to userspace
due to uninitialized value.

This commit fixes the bug.

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Fixes: baa914cd81f5 ("firewire: add kernel API to access CYCLE_TIME register")
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Link: https://lore.kernel.org/r/20220512112037.103142-1-o-takashi@sakamocchi.jp
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 drivers/firewire/core-cdev.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/firewire/core-cdev.c b/drivers/firewire/core-cdev.c
index c9fe5903725a5..9c89f7d53e99d 100644
--- a/drivers/firewire/core-cdev.c
+++ b/drivers/firewire/core-cdev.c
@@ -1211,7 +1211,7 @@ static int ioctl_get_cycle_timer2(struct client *client, union ioctl_arg *arg)
 	struct fw_cdev_get_cycle_timer2 *a = &arg->get_cycle_timer2;
 	struct fw_card *card = client->device->card;
 	struct timespec64 ts = {0, 0};
-	u32 cycle_time;
+	u32 cycle_time = 0;
 	int ret = 0;
 
 	local_irq_disable();
-- 
GitLab


From 2328fe7a98db3b9d46c41def169e7915dda4b9a9 Mon Sep 17 00:00:00 2001
From: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
Date: Wed, 15 Jun 2022 21:15:03 +0900
Subject: [PATCH 0734/1731] firewire: convert sysfs sprintf/snprintf family to
 sysfs_emit

Fix the following coccicheck warning:

./drivers/firewire/core-device.c:375:8-16: WARNING: use scnprintf or
sprintf.

Reported-by: Abaci Robot<abaci@linux.alibaba.com>
Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Link: https://lore.kernel.org/r/20220615121505.61412-2-o-takashi@sakamocchi.jp
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 drivers/firewire/core-device.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/firewire/core-device.c b/drivers/firewire/core-device.c
index 90ed8fdaba754..adddd8c45d0c1 100644
--- a/drivers/firewire/core-device.c
+++ b/drivers/firewire/core-device.c
@@ -372,8 +372,7 @@ static ssize_t rom_index_show(struct device *dev,
 	struct fw_device *device = fw_device(dev->parent);
 	struct fw_unit *unit = fw_unit(dev);
 
-	return snprintf(buf, PAGE_SIZE, "%d\n",
-			(int)(unit->directory - device->config_rom));
+	return sysfs_emit(buf, "%td\n", unit->directory - device->config_rom);
 }
 
 static struct device_attribute fw_unit_attributes[] = {
@@ -403,8 +402,7 @@ static ssize_t guid_show(struct device *dev,
 	int ret;
 
 	down_read(&fw_device_rwsem);
-	ret = snprintf(buf, PAGE_SIZE, "0x%08x%08x\n",
-		       device->config_rom[3], device->config_rom[4]);
+	ret = sysfs_emit(buf, "0x%08x%08x\n", device->config_rom[3], device->config_rom[4]);
 	up_read(&fw_device_rwsem);
 
 	return ret;
-- 
GitLab


From 33fa35db8917118929edacc7fdeebdcde26a6803 Mon Sep 17 00:00:00 2001
From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Date: Thu, 16 Jun 2022 15:10:29 -0500
Subject: [PATCH 0735/1731] ALSA: hda: intel-dspcfg: use SOF for UpExtreme and
 UpExtreme11 boards
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The UpExtreme BIOS reports microphones that are not physically
present, so this module ends-up selecting SOF, while the UpExtreme11
BIOS does not report microphones so the snd-hda-intel driver is
selected.

For consistency use SOF unconditionally in autodetection mode. The use
of the snd-hda-intel driver can still be enabled with
'options snd-intel-dspcfg dsp_driver=1'

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://lore.kernel.org/r/20220616201029.130477-1-pierre-louis.bossart@linux.intel.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/hda/intel-dsp-config.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/sound/hda/intel-dsp-config.c b/sound/hda/intel-dsp-config.c
index a8fe01764b254..ec9cbb219bc14 100644
--- a/sound/hda/intel-dsp-config.c
+++ b/sound/hda/intel-dsp-config.c
@@ -196,6 +196,12 @@ static const struct config_entry config_table[] = {
 					DMI_MATCH(DMI_SYS_VENDOR, "Google"),
 				}
 			},
+			{
+				.ident = "UP-WHL",
+				.matches = {
+					DMI_MATCH(DMI_SYS_VENDOR, "AAEON"),
+				}
+			},
 			{}
 		}
 	},
@@ -358,6 +364,12 @@ static const struct config_entry config_table[] = {
 					DMI_MATCH(DMI_SYS_VENDOR, "Google"),
 				}
 			},
+			{
+				.ident = "UPX-TGL",
+				.matches = {
+					DMI_MATCH(DMI_SYS_VENDOR, "AAEON"),
+				}
+			},
 			{}
 		}
 	},
-- 
GitLab


From 6376ab02374822e1e8758a848ee736a182786a2e Mon Sep 17 00:00:00 2001
From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Date: Thu, 16 Jun 2022 17:05:59 -0500
Subject: [PATCH 0736/1731] ALSA: hda: intel-nhlt: remove use of __func__ in
 dev_dbg
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The module and function information can be added with
'modprobe foo dyndbg=+pmf'

Suggested-by: Greg KH <gregkh@linuxfoundation.org>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20220616220559.136160-1-pierre-louis.bossart@linux.intel.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/hda/intel-nhlt.c | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/sound/hda/intel-nhlt.c b/sound/hda/intel-nhlt.c
index 4063da3782833..9db5ccd9aa2db 100644
--- a/sound/hda/intel-nhlt.c
+++ b/sound/hda/intel-nhlt.c
@@ -55,8 +55,8 @@ int intel_nhlt_get_dmic_geo(struct device *dev, struct nhlt_acpi_table *nhlt)
 
 		/* find max number of channels based on format_configuration */
 		if (fmt_configs->fmt_count) {
-			dev_dbg(dev, "%s: found %d format definitions\n",
-				__func__, fmt_configs->fmt_count);
+			dev_dbg(dev, "found %d format definitions\n",
+				fmt_configs->fmt_count);
 
 			for (i = 0; i < fmt_configs->fmt_count; i++) {
 				struct wav_fmt_ext *fmt_ext;
@@ -66,9 +66,9 @@ int intel_nhlt_get_dmic_geo(struct device *dev, struct nhlt_acpi_table *nhlt)
 				if (fmt_ext->fmt.channels > max_ch)
 					max_ch = fmt_ext->fmt.channels;
 			}
-			dev_dbg(dev, "%s: max channels found %d\n", __func__, max_ch);
+			dev_dbg(dev, "max channels found %d\n", max_ch);
 		} else {
-			dev_dbg(dev, "%s: No format information found\n", __func__);
+			dev_dbg(dev, "No format information found\n");
 		}
 
 		if (cfg->device_config.config_type != NHLT_CONFIG_TYPE_MIC_ARRAY) {
@@ -95,17 +95,16 @@ int intel_nhlt_get_dmic_geo(struct device *dev, struct nhlt_acpi_table *nhlt)
 			}
 
 			if (dmic_geo > 0) {
-				dev_dbg(dev, "%s: Array with %d dmics\n", __func__, dmic_geo);
+				dev_dbg(dev, "Array with %d dmics\n", dmic_geo);
 			}
 			if (max_ch > dmic_geo) {
-				dev_dbg(dev, "%s: max channels %d exceed dmic number %d\n",
-					__func__, max_ch, dmic_geo);
+				dev_dbg(dev, "max channels %d exceed dmic number %d\n",
+					max_ch, dmic_geo);
 			}
 		}
 	}
 
-	dev_dbg(dev, "%s: dmic number %d max_ch %d\n",
-		__func__, dmic_geo, max_ch);
+	dev_dbg(dev, "dmic number %d max_ch %d\n", dmic_geo, max_ch);
 
 	return dmic_geo;
 }
-- 
GitLab


From e87c65aeb46ca4f5b7dc08531200bcb8a426c62e Mon Sep 17 00:00:00 2001
From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Date: Thu, 16 Jun 2022 17:29:09 -0500
Subject: [PATCH 0737/1731] ALSA: x86: intel_hdmi_audio: enable pm_runtime and
 set autosuspend delay

The existing code uses pm_runtime_get_sync/put_autosuspend, but
pm_runtime was not explicitly enabled. The autosuspend delay was not
set either, the value is set to 5s since HDMI is rather painful to
resume.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20220616222910.136854-2-pierre-louis.bossart@linux.intel.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/x86/intel_hdmi_audio.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/sound/x86/intel_hdmi_audio.c b/sound/x86/intel_hdmi_audio.c
index 0d828e35b4019..3b04c70a73e33 100644
--- a/sound/x86/intel_hdmi_audio.c
+++ b/sound/x86/intel_hdmi_audio.c
@@ -33,6 +33,8 @@
 #include <drm/intel_lpe_audio.h>
 #include "intel_hdmi_audio.h"
 
+#define INTEL_HDMI_AUDIO_SUSPEND_DELAY_MS  5000
+
 #define for_each_pipe(card_ctx, pipe) \
 	for ((pipe) = 0; (pipe) < (card_ctx)->num_pipes; (pipe)++)
 #define for_each_port(card_ctx, port) \
@@ -1802,8 +1804,11 @@ static int __hdmi_lpe_audio_probe(struct platform_device *pdev)
 	pdata->notify_audio_lpe = notify_audio_lpe;
 	spin_unlock_irq(&pdata->lpe_audio_slock);
 
+	pm_runtime_set_autosuspend_delay(&pdev->dev, INTEL_HDMI_AUDIO_SUSPEND_DELAY_MS);
 	pm_runtime_use_autosuspend(&pdev->dev);
+	pm_runtime_enable(&pdev->dev);
 	pm_runtime_mark_last_busy(&pdev->dev);
+	pm_runtime_idle(&pdev->dev);
 
 	dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__);
 	for_each_port(card_ctx, port) {
-- 
GitLab


From bb30b453fedac277d66220431fd7063d9ddc10d8 Mon Sep 17 00:00:00 2001
From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Date: Thu, 16 Jun 2022 17:29:10 -0500
Subject: [PATCH 0738/1731] ALSA: x86: intel_hdmi_audio: use
 pm_runtime_resume_and_get()

The current code does not check for errors and does not release the
reference on errors.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20220616222910.136854-3-pierre-louis.bossart@linux.intel.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/x86/intel_hdmi_audio.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/sound/x86/intel_hdmi_audio.c b/sound/x86/intel_hdmi_audio.c
index 3b04c70a73e33..ab95fb34a6358 100644
--- a/sound/x86/intel_hdmi_audio.c
+++ b/sound/x86/intel_hdmi_audio.c
@@ -1068,7 +1068,9 @@ static int had_pcm_open(struct snd_pcm_substream *substream)
 	intelhaddata = snd_pcm_substream_chip(substream);
 	runtime = substream->runtime;
 
-	pm_runtime_get_sync(intelhaddata->dev);
+	retval = pm_runtime_resume_and_get(intelhaddata->dev);
+	if (retval < 0)
+		return retval;
 
 	/* set the runtime hw parameter with local snd_pcm_hardware struct */
 	runtime->hw = had_pcm_hardware;
@@ -1536,8 +1538,12 @@ static void had_audio_wq(struct work_struct *work)
 		container_of(work, struct snd_intelhad, hdmi_audio_wq);
 	struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data;
 	struct intel_hdmi_lpe_audio_port_pdata *ppdata = &pdata->port[ctx->port];
+	int ret;
+
+	ret = pm_runtime_resume_and_get(ctx->dev);
+	if (ret < 0)
+		return;
 
-	pm_runtime_get_sync(ctx->dev);
 	mutex_lock(&ctx->mutex);
 	if (ppdata->pipe < 0) {
 		dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG : port = %d\n",
-- 
GitLab


From 56961c6331463cce2d84d0f973177a517fb33a82 Mon Sep 17 00:00:00 2001
From: Quentin Perret <qperret@google.com>
Date: Thu, 16 Jun 2022 16:11:34 +0000
Subject: [PATCH 0739/1731] KVM: arm64: Prevent kmemleak from accessing pKVM
 memory

Commit a7259df76702 ("memblock: make memblock_find_in_range method
private") changed the API using which memory is reserved for the pKVM
hypervisor. However, memblock_phys_alloc() differs from the original API in
terms of kmemleak semantics -- the old one didn't report the reserved
regions to kmemleak while the new one does. Unfortunately, when protected
KVM is enabled, all kernel accesses to pKVM-private memory result in a
fatal exception, which can now happen because of kmemleak scans:

$ echo scan > /sys/kernel/debug/kmemleak
[   34.991354] kvm [304]: nVHE hyp BUG at: [<ffff800008fa3750>] __kvm_nvhe_handle_host_mem_abort+0x270/0x290!
[   34.991580] kvm [304]: Hyp Offset: 0xfffe8be807e00000
[   34.991813] Kernel panic - not syncing: HYP panic:
[   34.991813] PS:600003c9 PC:0000f418011a3750 ESR:00000000f2000800
[   34.991813] FAR:ffff000439200000 HPFAR:0000000004792000 PAR:0000000000000000
[   34.991813] VCPU:0000000000000000
[   34.993660] CPU: 0 PID: 304 Comm: bash Not tainted 5.19.0-rc2 #102
[   34.994059] Hardware name: linux,dummy-virt (DT)
[   34.994452] Call trace:
[   34.994641]  dump_backtrace.part.0+0xcc/0xe0
[   34.994932]  show_stack+0x18/0x6c
[   34.995094]  dump_stack_lvl+0x68/0x84
[   34.995276]  dump_stack+0x18/0x34
[   34.995484]  panic+0x16c/0x354
[   34.995673]  __hyp_pgtable_total_pages+0x0/0x60
[   34.995933]  scan_block+0x74/0x12c
[   34.996129]  scan_gray_list+0xd8/0x19c
[   34.996332]  kmemleak_scan+0x2c8/0x580
[   34.996535]  kmemleak_write+0x340/0x4a0
[   34.996744]  full_proxy_write+0x60/0xbc
[   34.996967]  vfs_write+0xc4/0x2b0
[   34.997136]  ksys_write+0x68/0xf4
[   34.997311]  __arm64_sys_write+0x20/0x2c
[   34.997532]  invoke_syscall+0x48/0x114
[   34.997779]  el0_svc_common.constprop.0+0x44/0xec
[   34.998029]  do_el0_svc+0x2c/0xc0
[   34.998205]  el0_svc+0x2c/0x84
[   34.998421]  el0t_64_sync_handler+0xf4/0x100
[   34.998653]  el0t_64_sync+0x18c/0x190
[   34.999252] SMP: stopping secondary CPUs
[   35.000034] Kernel Offset: disabled
[   35.000261] CPU features: 0x800,00007831,00001086
[   35.000642] Memory Limit: none
[   35.001329] ---[ end Kernel panic - not syncing: HYP panic:
[   35.001329] PS:600003c9 PC:0000f418011a3750 ESR:00000000f2000800
[   35.001329] FAR:ffff000439200000 HPFAR:0000000004792000 PAR:0000000000000000
[   35.001329] VCPU:0000000000000000 ]---

Fix this by explicitly excluding the hypervisor's memory pool from
kmemleak like we already do for the hyp BSS.

Cc: Mike Rapoport <rppt@kernel.org>
Fixes: a7259df76702 ("memblock: make memblock_find_in_range method private")
Signed-off-by: Quentin Perret <qperret@google.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220616161135.3997786-1-qperret@google.com
---
 arch/arm64/kvm/arm.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index a0188144a122b..83a7f61354d3f 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -2112,11 +2112,11 @@ static int finalize_hyp_mode(void)
 		return 0;
 
 	/*
-	 * Exclude HYP BSS from kmemleak so that it doesn't get peeked
-	 * at, which would end badly once the section is inaccessible.
-	 * None of other sections should ever be introspected.
+	 * Exclude HYP sections from kmemleak so that they don't get peeked
+	 * at, which would end badly once inaccessible.
 	 */
 	kmemleak_free_part(__hyp_bss_start, __hyp_bss_end - __hyp_bss_start);
+	kmemleak_free_part(__va(hyp_mem_base), hyp_mem_size);
 	return pkvm_drop_host_privileges();
 }
 
-- 
GitLab


From cbc6d44867a24130ee528c20cffcbc28b3e09693 Mon Sep 17 00:00:00 2001
From: Marc Zyngier <maz@kernel.org>
Date: Thu, 16 Jun 2022 09:53:18 +0100
Subject: [PATCH 0740/1731] KVM: arm64: Add Oliver as a reviewer

Oliver Upton has agreed to help with reviewing the KVM/arm64
patches, and has been doing so for a while now, so adding him
as to the reviewer list.

Note that Oliver is using a different email address for this
purpose, rather than the one his been using for his other
contributions.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: Oliver Upton <oupton@google.com>
Link: https://lore.kernel.org/r/20220616085318.1303657-1-maz@kernel.org
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index a6d3bd9d2a8d0..7192d1277558d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10821,6 +10821,7 @@ M:	Marc Zyngier <maz@kernel.org>
 R:	James Morse <james.morse@arm.com>
 R:	Alexandru Elisei <alexandru.elisei@arm.com>
 R:	Suzuki K Poulose <suzuki.poulose@arm.com>
+R:	Oliver Upton <oliver.upton@linux.dev>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 L:	kvmarm@lists.cs.columbia.edu (moderated for non-subscribers)
 S:	Maintained
-- 
GitLab


From 88436dec47a89d944e834e27d83a5dfd49d032cd Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Thu, 16 Jun 2022 12:48:11 +0300
Subject: [PATCH 0741/1731] drm/i915/wm: move wm state verification to
 intel_pm.c
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

By moving wm state verification to intel_pm.c, we can make a bunch of
functions static, hiding the wm details better. Also declutter
intel_display.c.

v2: intel_wm_state_verify -> intel_wm_verify_state (Ville)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2a7e3141e87181c07eaddcd9c352b8810550b0ce.1655372759.git.jani.nikula@intel.com
---
 drivers/gpu/drm/i915/display/intel_display.c | 122 +---------------
 drivers/gpu/drm/i915/intel_pm.c              | 138 +++++++++++++++++--
 drivers/gpu/drm/i915/intel_pm.h              |  14 +-
 3 files changed, 132 insertions(+), 142 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 88658090ac583..5557f210799a0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6424,126 +6424,6 @@ static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
 	}
 }
 
-static void verify_wm_state(struct intel_crtc *crtc,
-			    struct intel_crtc_state *new_crtc_state)
-{
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	struct skl_hw_state {
-		struct skl_ddb_entry ddb[I915_MAX_PLANES];
-		struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
-		struct skl_pipe_wm wm;
-	} *hw;
-	const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;
-	int level, max_level = ilk_wm_max_level(dev_priv);
-	struct intel_plane *plane;
-	u8 hw_enabled_slices;
-
-	if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active)
-		return;
-
-	hw = kzalloc(sizeof(*hw), GFP_KERNEL);
-	if (!hw)
-		return;
-
-	skl_pipe_wm_get_hw_state(crtc, &hw->wm);
-
-	skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y);
-
-	hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
-
-	if (DISPLAY_VER(dev_priv) >= 11 &&
-	    hw_enabled_slices != dev_priv->dbuf.enabled_slices)
-		drm_err(&dev_priv->drm,
-			"mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
-			dev_priv->dbuf.enabled_slices,
-			hw_enabled_slices);
-
-	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
-		const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
-		const struct skl_wm_level *hw_wm_level, *sw_wm_level;
-
-		/* Watermarks */
-		for (level = 0; level <= max_level; level++) {
-			hw_wm_level = &hw->wm.planes[plane->id].wm[level];
-			sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level);
-
-			if (skl_wm_level_equals(hw_wm_level, sw_wm_level))
-				continue;
-
-			drm_err(&dev_priv->drm,
-				"[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
-				plane->base.base.id, plane->base.name, level,
-				sw_wm_level->enable,
-				sw_wm_level->blocks,
-				sw_wm_level->lines,
-				hw_wm_level->enable,
-				hw_wm_level->blocks,
-				hw_wm_level->lines);
-		}
-
-		hw_wm_level = &hw->wm.planes[plane->id].trans_wm;
-		sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id);
-
-		if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
-			drm_err(&dev_priv->drm,
-				"[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
-				plane->base.base.id, plane->base.name,
-				sw_wm_level->enable,
-				sw_wm_level->blocks,
-				sw_wm_level->lines,
-				hw_wm_level->enable,
-				hw_wm_level->blocks,
-				hw_wm_level->lines);
-		}
-
-		hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0;
-		sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0;
-
-		if (HAS_HW_SAGV_WM(dev_priv) &&
-		    !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
-			drm_err(&dev_priv->drm,
-				"[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
-				plane->base.base.id, plane->base.name,
-				sw_wm_level->enable,
-				sw_wm_level->blocks,
-				sw_wm_level->lines,
-				hw_wm_level->enable,
-				hw_wm_level->blocks,
-				hw_wm_level->lines);
-		}
-
-		hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm;
-		sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm;
-
-		if (HAS_HW_SAGV_WM(dev_priv) &&
-		    !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
-			drm_err(&dev_priv->drm,
-				"[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
-				plane->base.base.id, plane->base.name,
-				sw_wm_level->enable,
-				sw_wm_level->blocks,
-				sw_wm_level->lines,
-				hw_wm_level->enable,
-				hw_wm_level->blocks,
-				hw_wm_level->lines);
-		}
-
-		/* DDB */
-		hw_ddb_entry = &hw->ddb[PLANE_CURSOR];
-		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];
-
-		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
-			drm_err(&dev_priv->drm,
-				"[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n",
-				plane->base.base.id, plane->base.name,
-				sw_ddb_entry->start, sw_ddb_entry->end,
-				hw_ddb_entry->start, hw_ddb_entry->end);
-		}
-	}
-
-	kfree(hw);
-}
-
 static void
 verify_connector_state(struct intel_atomic_state *state,
 		       struct intel_crtc *crtc)
@@ -6836,7 +6716,7 @@ intel_modeset_verify_crtc(struct intel_crtc *crtc,
 	if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
 		return;
 
-	verify_wm_state(crtc, new_crtc_state);
+	intel_wm_state_verify(crtc, new_crtc_state);
 	verify_connector_state(state, crtc);
 	verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
 	verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index aacb21cbc62ec..25069751bd6c7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4368,9 +4368,9 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
 	skl_ddb_entry_init_from_hw(ddb_y, val);
 }
 
-void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
-			       struct skl_ddb_entry *ddb,
-			       struct skl_ddb_entry *ddb_y)
+static void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
+				      struct skl_ddb_entry *ddb,
+				      struct skl_ddb_entry *ddb_y)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum intel_display_power_domain power_domain;
@@ -4950,7 +4950,7 @@ skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state)
 	return data_rate;
 }
 
-const struct skl_wm_level *
+static const struct skl_wm_level *
 skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
 		   enum plane_id plane_id,
 		   int level)
@@ -4963,7 +4963,7 @@ skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
 	return &wm->wm[level];
 }
 
-const struct skl_wm_level *
+static const struct skl_wm_level *
 skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
 		   enum plane_id plane_id)
 {
@@ -5915,8 +5915,8 @@ void skl_write_cursor_wm(struct intel_plane *plane,
 	skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb);
 }
 
-bool skl_wm_level_equals(const struct skl_wm_level *l1,
-			 const struct skl_wm_level *l2)
+static bool skl_wm_level_equals(const struct skl_wm_level *l1,
+				const struct skl_wm_level *l2)
 {
 	return l1->enable == l2->enable &&
 		l1->ignore_lines == l2->ignore_lines &&
@@ -6488,8 +6488,8 @@ static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)
 	level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val);
 }
 
-void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
-			      struct skl_pipe_wm *out)
+static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
+				     struct skl_pipe_wm *out)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
@@ -7166,6 +7166,126 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
 		!(intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) & DISP_FBC_WM_DIS);
 }
 
+void intel_wm_state_verify(struct intel_crtc *crtc,
+			   struct intel_crtc_state *new_crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct skl_hw_state {
+		struct skl_ddb_entry ddb[I915_MAX_PLANES];
+		struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
+		struct skl_pipe_wm wm;
+	} *hw;
+	const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;
+	int level, max_level = ilk_wm_max_level(dev_priv);
+	struct intel_plane *plane;
+	u8 hw_enabled_slices;
+
+	if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active)
+		return;
+
+	hw = kzalloc(sizeof(*hw), GFP_KERNEL);
+	if (!hw)
+		return;
+
+	skl_pipe_wm_get_hw_state(crtc, &hw->wm);
+
+	skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y);
+
+	hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
+
+	if (DISPLAY_VER(dev_priv) >= 11 &&
+	    hw_enabled_slices != dev_priv->dbuf.enabled_slices)
+		drm_err(&dev_priv->drm,
+			"mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
+			dev_priv->dbuf.enabled_slices,
+			hw_enabled_slices);
+
+	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+		const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
+		const struct skl_wm_level *hw_wm_level, *sw_wm_level;
+
+		/* Watermarks */
+		for (level = 0; level <= max_level; level++) {
+			hw_wm_level = &hw->wm.planes[plane->id].wm[level];
+			sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level);
+
+			if (skl_wm_level_equals(hw_wm_level, sw_wm_level))
+				continue;
+
+			drm_err(&dev_priv->drm,
+				"[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
+				plane->base.base.id, plane->base.name, level,
+				sw_wm_level->enable,
+				sw_wm_level->blocks,
+				sw_wm_level->lines,
+				hw_wm_level->enable,
+				hw_wm_level->blocks,
+				hw_wm_level->lines);
+		}
+
+		hw_wm_level = &hw->wm.planes[plane->id].trans_wm;
+		sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id);
+
+		if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
+			drm_err(&dev_priv->drm,
+				"[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
+				plane->base.base.id, plane->base.name,
+				sw_wm_level->enable,
+				sw_wm_level->blocks,
+				sw_wm_level->lines,
+				hw_wm_level->enable,
+				hw_wm_level->blocks,
+				hw_wm_level->lines);
+		}
+
+		hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0;
+		sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0;
+
+		if (HAS_HW_SAGV_WM(dev_priv) &&
+		    !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
+			drm_err(&dev_priv->drm,
+				"[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
+				plane->base.base.id, plane->base.name,
+				sw_wm_level->enable,
+				sw_wm_level->blocks,
+				sw_wm_level->lines,
+				hw_wm_level->enable,
+				hw_wm_level->blocks,
+				hw_wm_level->lines);
+		}
+
+		hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm;
+		sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm;
+
+		if (HAS_HW_SAGV_WM(dev_priv) &&
+		    !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
+			drm_err(&dev_priv->drm,
+				"[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
+				plane->base.base.id, plane->base.name,
+				sw_wm_level->enable,
+				sw_wm_level->blocks,
+				sw_wm_level->lines,
+				hw_wm_level->enable,
+				hw_wm_level->blocks,
+				hw_wm_level->lines);
+		}
+
+		/* DDB */
+		hw_ddb_entry = &hw->ddb[PLANE_CURSOR];
+		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];
+
+		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
+			drm_err(&dev_priv->drm,
+				"[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n",
+				plane->base.base.id, plane->base.name,
+				sw_ddb_entry->start, sw_ddb_entry->end,
+				hw_ddb_entry->start, hw_ddb_entry->end);
+		}
+	}
+
+	kfree(hw);
+}
+
 void intel_enable_ipc(struct drm_i915_private *dev_priv)
 {
 	u32 val;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 50604cf7398c4..945503ae493eb 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -35,15 +35,12 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
+void intel_wm_state_verify(struct intel_crtc *crtc,
+			   struct intel_crtc_state *new_crtc_state);
 u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
-void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
-			       struct skl_ddb_entry *ddb_y,
-			       struct skl_ddb_entry *ddb_uv);
 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
 u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
 			    const struct skl_ddb_entry *entry);
-void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
-			      struct skl_pipe_wm *out);
 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
 void skl_wm_sanitize(struct drm_i915_private *dev_priv);
@@ -51,13 +48,6 @@ bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
 			   const struct intel_bw_state *bw_state);
 void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
 void intel_sagv_post_plane_update(struct intel_atomic_state *state);
-const struct skl_wm_level *skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
-					      enum plane_id plane_id,
-					      int level);
-const struct skl_wm_level *skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
-					      enum plane_id plane_id);
-bool skl_wm_level_equals(const struct skl_wm_level *l1,
-			 const struct skl_wm_level *l2);
 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
 				 const struct skl_ddb_entry *entries,
 				 int num_entries, int ignore_idx);
-- 
GitLab


From f0978e92c2f7e9a38fa05d30a3e901d16a30698a Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Thu, 16 Jun 2022 12:48:12 +0300
Subject: [PATCH 0742/1731] drm/i915/dpll: move shared dpll state verification
 to intel_dpll_mgr.c
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Keep the shared dpll implementation details together by moving the dpll
state verification to intel_dpll_mgr.c. Also declutter intel_display.c.

v2: intel_shared_dpll_verify_state -> intel_shared_dpll_state_verify (Ville)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/85b02186f1269dd374d11db35900130547a5f2c6.1655372759.git.jani.nikula@intel.com
---
 drivers/gpu/drm/i915/display/intel_display.c  | 94 +------------------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 88 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  5 +
 3 files changed, 95 insertions(+), 92 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5557f210799a0..0d1217c9798e9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6582,85 +6582,6 @@ intel_verify_planes(struct intel_atomic_state *state)
 			     plane_state->uapi.visible);
 }
 
-static void
-verify_single_dpll_state(struct drm_i915_private *dev_priv,
-			 struct intel_shared_dpll *pll,
-			 struct intel_crtc *crtc,
-			 struct intel_crtc_state *new_crtc_state)
-{
-	struct intel_dpll_hw_state dpll_hw_state;
-	u8 pipe_mask;
-	bool active;
-
-	memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
-
-	drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
-
-	active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state);
-
-	if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
-		I915_STATE_WARN(!pll->on && pll->active_mask,
-		     "pll in active use but not on in sw tracking\n");
-		I915_STATE_WARN(pll->on && !pll->active_mask,
-		     "pll is on but not used by any active pipe\n");
-		I915_STATE_WARN(pll->on != active,
-		     "pll on state mismatch (expected %i, found %i)\n",
-		     pll->on, active);
-	}
-
-	if (!crtc) {
-		I915_STATE_WARN(pll->active_mask & ~pll->state.pipe_mask,
-				"more active pll users than references: 0x%x vs 0x%x\n",
-				pll->active_mask, pll->state.pipe_mask);
-
-		return;
-	}
-
-	pipe_mask = BIT(crtc->pipe);
-
-	if (new_crtc_state->hw.active)
-		I915_STATE_WARN(!(pll->active_mask & pipe_mask),
-				"pll active mismatch (expected pipe %c in active mask 0x%x)\n",
-				pipe_name(crtc->pipe), pll->active_mask);
-	else
-		I915_STATE_WARN(pll->active_mask & pipe_mask,
-				"pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n",
-				pipe_name(crtc->pipe), pll->active_mask);
-
-	I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask),
-			"pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
-			pipe_mask, pll->state.pipe_mask);
-
-	I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
-					  &dpll_hw_state,
-					  sizeof(dpll_hw_state)),
-			"pll hw state mismatch\n");
-}
-
-static void
-verify_shared_dpll_state(struct intel_crtc *crtc,
-			 struct intel_crtc_state *old_crtc_state,
-			 struct intel_crtc_state *new_crtc_state)
-{
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-
-	if (new_crtc_state->shared_dpll)
-		verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
-
-	if (old_crtc_state->shared_dpll &&
-	    old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
-		u8 pipe_mask = BIT(crtc->pipe);
-		struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
-
-		I915_STATE_WARN(pll->active_mask & pipe_mask,
-				"pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
-				pipe_name(crtc->pipe), pll->active_mask);
-		I915_STATE_WARN(pll->state.pipe_mask & pipe_mask,
-				"pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n",
-				pipe_name(crtc->pipe), pll->state.pipe_mask);
-	}
-}
-
 static void
 verify_mpllb_state(struct intel_atomic_state *state,
 		   struct intel_crtc_state *new_crtc_state)
@@ -6719,28 +6640,17 @@ intel_modeset_verify_crtc(struct intel_crtc *crtc,
 	intel_wm_state_verify(crtc, new_crtc_state);
 	verify_connector_state(state, crtc);
 	verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
-	verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
+	intel_shared_dpll_state_verify(crtc, old_crtc_state, new_crtc_state);
 	verify_mpllb_state(state, new_crtc_state);
 }
 
-static void
-verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
-{
-	int i;
-
-	for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)
-		verify_single_dpll_state(dev_priv,
-					 &dev_priv->dpll.shared_dplls[i],
-					 NULL, NULL);
-}
-
 static void
 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
 			      struct intel_atomic_state *state)
 {
 	verify_encoder_state(dev_priv, state);
 	verify_connector_state(state, NULL);
-	verify_disabled_dpll_state(dev_priv);
+	intel_shared_dpll_verify_disabled(dev_priv);
 }
 
 int intel_modeset_all_pipes(struct intel_atomic_state *state)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 982e5b9456803..ddae7e42ac46d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4449,3 +4449,91 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
 			    hw_state->fp1);
 	}
 }
+
+static void
+verify_single_dpll_state(struct drm_i915_private *dev_priv,
+			 struct intel_shared_dpll *pll,
+			 struct intel_crtc *crtc,
+			 struct intel_crtc_state *new_crtc_state)
+{
+	struct intel_dpll_hw_state dpll_hw_state;
+	u8 pipe_mask;
+	bool active;
+
+	memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
+
+	drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
+
+	active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state);
+
+	if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
+		I915_STATE_WARN(!pll->on && pll->active_mask,
+				"pll in active use but not on in sw tracking\n");
+		I915_STATE_WARN(pll->on && !pll->active_mask,
+				"pll is on but not used by any active pipe\n");
+		I915_STATE_WARN(pll->on != active,
+				"pll on state mismatch (expected %i, found %i)\n",
+				pll->on, active);
+	}
+
+	if (!crtc) {
+		I915_STATE_WARN(pll->active_mask & ~pll->state.pipe_mask,
+				"more active pll users than references: 0x%x vs 0x%x\n",
+				pll->active_mask, pll->state.pipe_mask);
+
+		return;
+	}
+
+	pipe_mask = BIT(crtc->pipe);
+
+	if (new_crtc_state->hw.active)
+		I915_STATE_WARN(!(pll->active_mask & pipe_mask),
+				"pll active mismatch (expected pipe %c in active mask 0x%x)\n",
+				pipe_name(crtc->pipe), pll->active_mask);
+	else
+		I915_STATE_WARN(pll->active_mask & pipe_mask,
+				"pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n",
+				pipe_name(crtc->pipe), pll->active_mask);
+
+	I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask),
+			"pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
+			pipe_mask, pll->state.pipe_mask);
+
+	I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
+					  &dpll_hw_state,
+					  sizeof(dpll_hw_state)),
+			"pll hw state mismatch\n");
+}
+
+void intel_shared_dpll_state_verify(struct intel_crtc *crtc,
+				    struct intel_crtc_state *old_crtc_state,
+				    struct intel_crtc_state *new_crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+	if (new_crtc_state->shared_dpll)
+		verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll,
+					 crtc, new_crtc_state);
+
+	if (old_crtc_state->shared_dpll &&
+	    old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
+		u8 pipe_mask = BIT(crtc->pipe);
+		struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
+
+		I915_STATE_WARN(pll->active_mask & pipe_mask,
+				"pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
+				pipe_name(crtc->pipe), pll->active_mask);
+		I915_STATE_WARN(pll->state.pipe_mask & pipe_mask,
+				"pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n",
+				pipe_name(crtc->pipe), pll->state.pipe_mask);
+	}
+}
+
+void intel_shared_dpll_verify_disabled(struct drm_i915_private *i915)
+{
+	int i;
+
+	for (i = 0; i < i915->dpll.num_shared_dpll; i++)
+		verify_single_dpll_state(i915, &i915->dpll.shared_dplls[i],
+					 NULL, NULL);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 02412bf7625ca..3247dc300ae40 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -368,4 +368,9 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
 bool intel_dpll_is_combophy(enum intel_dpll_id id);
 
+void intel_shared_dpll_state_verify(struct intel_crtc *crtc,
+				    struct intel_crtc_state *old_crtc_state,
+				    struct intel_crtc_state *new_crtc_state);
+void intel_shared_dpll_verify_disabled(struct drm_i915_private *i915);
+
 #endif /* _INTEL_DPLL_MGR_H_ */
-- 
GitLab


From 109406c92f971e739af04b278ef75dd0fee68a40 Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Thu, 16 Jun 2022 12:48:13 +0300
Subject: [PATCH 0743/1731] drm/i915/mpllb: use I915_STATE_WARN() for state
 mismatch warnings
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The pipe_config_mismatch() function is primarily for logging comparison
results.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/167e54e13a9a41c944910a274e79cbfd39d963b1.1655372759.git.jani.nikula@intel.com
---
 drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0d1217c9798e9..b2232d042841e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6601,14 +6601,12 @@ verify_mpllb_state(struct intel_atomic_state *state,
 	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
 	intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state);
 
-#define MPLLB_CHECK(name) do { \
-	if (mpllb_sw_state->name != mpllb_hw_state.name) { \
-		pipe_config_mismatch(false, crtc, "MPLLB:" __stringify(name), \
-				     "(expected 0x%08x, found 0x%08x)", \
-				     mpllb_sw_state->name, \
-				     mpllb_hw_state.name); \
-	} \
-} while (0)
+#define MPLLB_CHECK(__name)						\
+	I915_STATE_WARN(mpllb_sw_state->__name != mpllb_hw_state.__name,	\
+			"[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \
+			crtc->base.base.id, crtc->base.name,		\
+			__stringify(__name),				\
+			mpllb_sw_state->__name, mpllb_hw_state.__name)
 
 	MPLLB_CHECK(mpllb_cp);
 	MPLLB_CHECK(mpllb_div);
-- 
GitLab


From 781c336a6caa67c68fe3a25b108d1dc38b0e7cc0 Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Thu, 16 Jun 2022 12:48:14 +0300
Subject: [PATCH 0744/1731] drm/i915/mpllb: move mpllb state check to
 intel_snps_phy.c
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Keep the mpllb implementation details together in intel_snps_phy.c. Also
declutter intel_display.c.

v2: intel_mpllb_verify_state -> void intel_mpllb_state_verify (Ville)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e7340bb0e399aeb2676c4820461187eeb1d4db15.1655372759.git.jani.nikula@intel.com
---
 drivers/gpu/drm/i915/display/intel_display.c  | 46 +------------------
 drivers/gpu/drm/i915/display/intel_snps_phy.c | 43 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_snps_phy.h |  5 +-
 3 files changed, 48 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b2232d042841e..1679dd83d5d1e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6582,50 +6582,6 @@ intel_verify_planes(struct intel_atomic_state *state)
 			     plane_state->uapi.visible);
 }
 
-static void
-verify_mpllb_state(struct intel_atomic_state *state,
-		   struct intel_crtc_state *new_crtc_state)
-{
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
-	struct intel_mpllb_state mpllb_hw_state = { 0 };
-	struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state;
-	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
-	struct intel_encoder *encoder;
-
-	if (!IS_DG2(i915))
-		return;
-
-	if (!new_crtc_state->hw.active)
-		return;
-
-	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
-	intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state);
-
-#define MPLLB_CHECK(__name)						\
-	I915_STATE_WARN(mpllb_sw_state->__name != mpllb_hw_state.__name,	\
-			"[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \
-			crtc->base.base.id, crtc->base.name,		\
-			__stringify(__name),				\
-			mpllb_sw_state->__name, mpllb_hw_state.__name)
-
-	MPLLB_CHECK(mpllb_cp);
-	MPLLB_CHECK(mpllb_div);
-	MPLLB_CHECK(mpllb_div2);
-	MPLLB_CHECK(mpllb_fracn1);
-	MPLLB_CHECK(mpllb_fracn2);
-	MPLLB_CHECK(mpllb_sscen);
-	MPLLB_CHECK(mpllb_sscstep);
-
-	/*
-	 * ref_control is handled by the hardware/firemware and never
-	 * programmed by the software, but the proper values are supplied
-	 * in the bspec for verification purposes.
-	 */
-	MPLLB_CHECK(ref_control);
-
-#undef MPLLB_CHECK
-}
-
 static void
 intel_modeset_verify_crtc(struct intel_crtc *crtc,
 			  struct intel_atomic_state *state,
@@ -6639,7 +6595,7 @@ intel_modeset_verify_crtc(struct intel_crtc *crtc,
 	verify_connector_state(state, crtc);
 	verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
 	intel_shared_dpll_state_verify(crtc, old_crtc_state, new_crtc_state);
-	verify_mpllb_state(state, new_crtc_state);
+	intel_mpllb_state_verify(state, new_crtc_state);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index b48f42f1832a9..0bdbedc67d7d3 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -813,3 +813,46 @@ int intel_snps_phy_check_hdmi_link_rate(int clock)
 
 	return MODE_CLOCK_RANGE;
 }
+
+void intel_mpllb_state_verify(struct intel_atomic_state *state,
+			      struct intel_crtc_state *new_crtc_state)
+{
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	struct intel_mpllb_state mpllb_hw_state = { 0 };
+	struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state;
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+	struct intel_encoder *encoder;
+
+	if (!IS_DG2(i915))
+		return;
+
+	if (!new_crtc_state->hw.active)
+		return;
+
+	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
+	intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state);
+
+#define MPLLB_CHECK(__name)						\
+	I915_STATE_WARN(mpllb_sw_state->__name != mpllb_hw_state.__name,	\
+			"[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \
+			crtc->base.base.id, crtc->base.name,		\
+			__stringify(__name),				\
+			mpllb_sw_state->__name, mpllb_hw_state.__name)
+
+	MPLLB_CHECK(mpllb_cp);
+	MPLLB_CHECK(mpllb_div);
+	MPLLB_CHECK(mpllb_div2);
+	MPLLB_CHECK(mpllb_fracn1);
+	MPLLB_CHECK(mpllb_fracn2);
+	MPLLB_CHECK(mpllb_sscen);
+	MPLLB_CHECK(mpllb_sscstep);
+
+	/*
+	 * ref_control is handled by the hardware/firemware and never
+	 * programmed by the software, but the proper values are supplied
+	 * in the bspec for verification purposes.
+	 */
+	MPLLB_CHECK(ref_control);
+
+#undef MPLLB_CHECK
+}
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h b/drivers/gpu/drm/i915/display/intel_snps_phy.h
index 11dcd6deb0704..557ef820bc0b3 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h
@@ -9,8 +9,9 @@
 #include <linux/types.h>
 
 struct drm_i915_private;
-struct intel_encoder;
+struct intel_atomic_state;
 struct intel_crtc_state;
+struct intel_encoder;
 struct intel_mpllb_state;
 enum phy;
 
@@ -31,5 +32,7 @@ int intel_mpllb_calc_port_clock(struct intel_encoder *encoder,
 int intel_snps_phy_check_hdmi_link_rate(int clock);
 void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
 				      const struct intel_crtc_state *crtc_state);
+void intel_mpllb_state_verify(struct intel_atomic_state *state,
+			      struct intel_crtc_state *new_crtc_state);
 
 #endif /* __INTEL_SNPS_PHY_H__ */
-- 
GitLab


From df17ff62b626554c6048bf435a87c5fe1981e8a8 Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Thu, 16 Jun 2022 12:48:15 +0300
Subject: [PATCH 0745/1731] drm/i915/display: split out modeset verification
 code
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add new file intel_modeset_verify.c for high level modeset verification
code to declutter intel_display.h. The new file is supposed to be about
crtc/encoder/connector verification; the state verification for very
specific functionality such as plls or wm should be placed next to the
code it verifies.

Fix some minor checkpatch issues while at it.

v2: Rebase

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/b9b47c14316a9edb772a8b8f934eabe7e928dd76.1655372759.git.jani.nikula@intel.com
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/intel_display.c  | 243 +----------------
 drivers/gpu/drm/i915/display/intel_display.h  |   9 +
 .../drm/i915/display/intel_modeset_verify.c   | 245 ++++++++++++++++++
 .../drm/i915/display/intel_modeset_verify.h   |  21 ++
 5 files changed, 284 insertions(+), 235 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_verify.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_verify.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5a52f014f0dde..c9dcb533f1bcc 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -232,6 +232,7 @@ i915-y += \
 	display/intel_hdcp.o \
 	display/intel_hotplug.o \
 	display/intel_lpe_audio.o \
+	display/intel_modeset_verify.o \
 	display/intel_overlay.o \
 	display/intel_pch_display.o \
 	display/intel_pch_refclk.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1679dd83d5d1e..c7a7599657932 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -99,6 +99,7 @@
 #include "intel_frontbuffer.h"
 #include "intel_hdcp.h"
 #include "intel_hotplug.h"
+#include "intel_modeset_verify.h"
 #include "intel_overlay.h"
 #include "intel_panel.h"
 #include "intel_pch_display.h"
@@ -2529,45 +2530,6 @@ void intel_encoder_destroy(struct drm_encoder *encoder)
 	kfree(intel_encoder);
 }
 
-/* Cross check the actual hw state with our own modeset state tracking (and it's
- * internal consistency). */
-static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
-					 struct drm_connector_state *conn_state)
-{
-	struct intel_connector *connector = to_intel_connector(conn_state->connector);
-	struct drm_i915_private *i915 = to_i915(connector->base.dev);
-
-	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
-		    connector->base.base.id, connector->base.name);
-
-	if (connector->get_hw_state(connector)) {
-		struct intel_encoder *encoder = intel_attached_encoder(connector);
-
-		I915_STATE_WARN(!crtc_state,
-			 "connector enabled without attached crtc\n");
-
-		if (!crtc_state)
-			return;
-
-		I915_STATE_WARN(!crtc_state->hw.active,
-				"connector is active, but attached crtc isn't\n");
-
-		if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
-			return;
-
-		I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
-			"atomic encoder doesn't match attached encoder\n");
-
-		I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
-			"attached encoder crtc differs from connector crtc\n");
-	} else {
-		I915_STATE_WARN(crtc_state && crtc_state->hw.active,
-				"attached crtc is active, but connector isn't\n");
-		I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
-			"best encoder set without crtc!\n");
-	}
-}
-
 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
 {
 	const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2709,8 +2671,8 @@ static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state
 	intel_crtc_compute_pixel_rate(crtc_state);
 }
 
-static void intel_encoder_get_config(struct intel_encoder *encoder,
-				     struct intel_crtc_state *crtc_state)
+void intel_encoder_get_config(struct intel_encoder *encoder,
+			      struct intel_crtc_state *crtc_state)
 {
 	encoder->get_config(encoder, crtc_state);
 
@@ -4251,7 +4213,7 @@ out:
 	return active;
 }
 
-static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
+bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
@@ -5230,9 +5192,9 @@ static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
 			    DRM_RECT_ARG(&plane_state->uapi.dst));
 }
 
-static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
-				   struct intel_atomic_state *state,
-				   const char *context)
+void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
+			    struct intel_atomic_state *state,
+			    const char *context)
 {
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -5982,7 +5944,7 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
 	return false;
 }
 
-static bool
+bool
 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 			  const struct intel_crtc_state *pipe_config,
 			  bool fastset)
@@ -6405,170 +6367,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	return ret;
 }
 
-static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
-					   const struct intel_crtc_state *pipe_config)
-{
-	if (pipe_config->has_pch_encoder) {
-		int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
-							    &pipe_config->fdi_m_n);
-		int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
-
-		/*
-		 * FDI already provided one idea for the dotclock.
-		 * Yell if the encoder disagrees.
-		 */
-		drm_WARN(&dev_priv->drm,
-			 !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
-			 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
-			 fdi_dotclock, dotclock);
-	}
-}
-
-static void
-verify_connector_state(struct intel_atomic_state *state,
-		       struct intel_crtc *crtc)
-{
-	struct drm_connector *connector;
-	struct drm_connector_state *new_conn_state;
-	int i;
-
-	for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
-		struct drm_encoder *encoder = connector->encoder;
-		struct intel_crtc_state *crtc_state = NULL;
-
-		if (new_conn_state->crtc != &crtc->base)
-			continue;
-
-		if (crtc)
-			crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
-
-		intel_connector_verify_state(crtc_state, new_conn_state);
-
-		I915_STATE_WARN(new_conn_state->best_encoder != encoder,
-		     "connector's atomic encoder doesn't match legacy encoder\n");
-	}
-}
-
-static void
-verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
-{
-	struct intel_encoder *encoder;
-	struct drm_connector *connector;
-	struct drm_connector_state *old_conn_state, *new_conn_state;
-	int i;
-
-	for_each_intel_encoder(&dev_priv->drm, encoder) {
-		bool enabled = false, found = false;
-		enum pipe pipe;
-
-		drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",
-			    encoder->base.base.id,
-			    encoder->base.name);
-
-		for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
-						   new_conn_state, i) {
-			if (old_conn_state->best_encoder == &encoder->base)
-				found = true;
-
-			if (new_conn_state->best_encoder != &encoder->base)
-				continue;
-			found = enabled = true;
-
-			I915_STATE_WARN(new_conn_state->crtc !=
-					encoder->base.crtc,
-			     "connector's crtc doesn't match encoder crtc\n");
-		}
-
-		if (!found)
-			continue;
-
-		I915_STATE_WARN(!!encoder->base.crtc != enabled,
-		     "encoder's enabled state mismatch "
-		     "(expected %i, found %i)\n",
-		     !!encoder->base.crtc, enabled);
-
-		if (!encoder->base.crtc) {
-			bool active;
-
-			active = encoder->get_hw_state(encoder, &pipe);
-			I915_STATE_WARN(active,
-			     "encoder detached but still enabled on pipe %c.\n",
-			     pipe_name(pipe));
-		}
-	}
-}
-
-static void
-verify_crtc_state(struct intel_crtc *crtc,
-		  struct intel_crtc_state *old_crtc_state,
-		  struct intel_crtc_state *new_crtc_state)
-{
-	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_encoder *encoder;
-	struct intel_crtc_state *pipe_config = old_crtc_state;
-	struct drm_atomic_state *state = old_crtc_state->uapi.state;
-	struct intel_crtc *master_crtc;
-
-	__drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
-	intel_crtc_free_hw_state(old_crtc_state);
-	intel_crtc_state_reset(old_crtc_state, crtc);
-	old_crtc_state->uapi.state = state;
-
-	drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
-		    crtc->base.name);
-
-	pipe_config->hw.enable = new_crtc_state->hw.enable;
-
-	intel_crtc_get_pipe_config(pipe_config);
-
-	/* we keep both pipes enabled on 830 */
-	if (IS_I830(dev_priv) && pipe_config->hw.active)
-		pipe_config->hw.active = new_crtc_state->hw.active;
-
-	I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active,
-			"crtc active state doesn't match with hw state "
-			"(expected %i, found %i)\n",
-			new_crtc_state->hw.active, pipe_config->hw.active);
-
-	I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
-			"transitional active state does not match atomic hw state "
-			"(expected %i, found %i)\n",
-			new_crtc_state->hw.active, crtc->active);
-
-	master_crtc = intel_master_crtc(new_crtc_state);
-
-	for_each_encoder_on_crtc(dev, &master_crtc->base, encoder) {
-		enum pipe pipe;
-		bool active;
-
-		active = encoder->get_hw_state(encoder, &pipe);
-		I915_STATE_WARN(active != new_crtc_state->hw.active,
-				"[ENCODER:%i] active %i with crtc active %i\n",
-				encoder->base.base.id, active,
-				new_crtc_state->hw.active);
-
-		I915_STATE_WARN(active && master_crtc->pipe != pipe,
-				"Encoder connected to wrong pipe %c\n",
-				pipe_name(pipe));
-
-		if (active)
-			intel_encoder_get_config(encoder, pipe_config);
-	}
-
-	if (!new_crtc_state->hw.active)
-		return;
-
-	intel_pipe_config_sanity_check(dev_priv, pipe_config);
-
-	if (!intel_pipe_config_compare(new_crtc_state,
-				       pipe_config, false)) {
-		I915_STATE_WARN(1, "pipe state doesn't match!\n");
-		intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
-		intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
-	}
-}
-
 static void
 intel_verify_planes(struct intel_atomic_state *state)
 {
@@ -6582,31 +6380,6 @@ intel_verify_planes(struct intel_atomic_state *state)
 			     plane_state->uapi.visible);
 }
 
-static void
-intel_modeset_verify_crtc(struct intel_crtc *crtc,
-			  struct intel_atomic_state *state,
-			  struct intel_crtc_state *old_crtc_state,
-			  struct intel_crtc_state *new_crtc_state)
-{
-	if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
-		return;
-
-	intel_wm_state_verify(crtc, new_crtc_state);
-	verify_connector_state(state, crtc);
-	verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
-	intel_shared_dpll_state_verify(crtc, old_crtc_state, new_crtc_state);
-	intel_mpllb_state_verify(state, new_crtc_state);
-}
-
-static void
-intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
-			      struct intel_atomic_state *state)
-{
-	verify_encoder_state(dev_priv, state);
-	verify_connector_state(state, NULL);
-	intel_shared_dpll_verify_disabled(dev_priv);
-}
-
 int intel_modeset_all_pipes(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 7af6b5a413dc0..70410eeb19c8f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -559,6 +559,13 @@ bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state);
 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state);
 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state);
 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state);
+bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
+bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
+			       const struct intel_crtc_state *pipe_config,
+			       bool fastset);
+void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
+			    struct intel_atomic_state *state,
+			    const char *context);
 
 void intel_plane_destroy(struct drm_plane *plane);
 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
@@ -583,6 +590,8 @@ int intel_display_suspend(struct drm_device *dev);
 void intel_encoder_destroy(struct drm_encoder *encoder);
 struct drm_display_mode *
 intel_encoder_current_mode(struct intel_encoder *encoder);
+void intel_encoder_get_config(struct intel_encoder *encoder,
+			      struct intel_crtc_state *crtc_state);
 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy);
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
new file mode 100644
index 0000000000000..1655c903e2f05
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -0,0 +1,245 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ *
+ * High level crtc/connector/encoder modeset state verification.
+ */
+
+#include <drm/drm_atomic_state_helper.h>
+
+#include "i915_drv.h"
+#include "intel_atomic.h"
+#include "intel_crtc.h"
+#include "intel_display.h"
+#include "intel_display_types.h"
+#include "intel_fdi.h"
+#include "intel_modeset_verify.h"
+#include "intel_pm.h"
+#include "intel_snps_phy.h"
+
+/*
+ * Cross check the actual hw state with our own modeset state tracking (and its
+ * internal consistency).
+ */
+static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
+					 struct drm_connector_state *conn_state)
+{
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
+	struct drm_i915_private *i915 = to_i915(connector->base.dev);
+
+	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
+		    connector->base.base.id, connector->base.name);
+
+	if (connector->get_hw_state(connector)) {
+		struct intel_encoder *encoder = intel_attached_encoder(connector);
+
+		I915_STATE_WARN(!crtc_state,
+				"connector enabled without attached crtc\n");
+
+		if (!crtc_state)
+			return;
+
+		I915_STATE_WARN(!crtc_state->hw.active,
+				"connector is active, but attached crtc isn't\n");
+
+		if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
+			return;
+
+		I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
+				"atomic encoder doesn't match attached encoder\n");
+
+		I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
+				"attached encoder crtc differs from connector crtc\n");
+	} else {
+		I915_STATE_WARN(crtc_state && crtc_state->hw.active,
+				"attached crtc is active, but connector isn't\n");
+		I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
+				"best encoder set without crtc!\n");
+	}
+}
+
+static void
+verify_connector_state(struct intel_atomic_state *state,
+		       struct intel_crtc *crtc)
+{
+	struct drm_connector *connector;
+	struct drm_connector_state *new_conn_state;
+	int i;
+
+	for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
+		struct drm_encoder *encoder = connector->encoder;
+		struct intel_crtc_state *crtc_state = NULL;
+
+		if (new_conn_state->crtc != &crtc->base)
+			continue;
+
+		if (crtc)
+			crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+
+		intel_connector_verify_state(crtc_state, new_conn_state);
+
+		I915_STATE_WARN(new_conn_state->best_encoder != encoder,
+				"connector's atomic encoder doesn't match legacy encoder\n");
+	}
+}
+
+static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
+					   const struct intel_crtc_state *pipe_config)
+{
+	if (pipe_config->has_pch_encoder) {
+		int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
+							    &pipe_config->fdi_m_n);
+		int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
+
+		/*
+		 * FDI already provided one idea for the dotclock.
+		 * Yell if the encoder disagrees.
+		 */
+		drm_WARN(&dev_priv->drm,
+			 !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
+			 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
+			 fdi_dotclock, dotclock);
+	}
+}
+
+static void
+verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
+{
+	struct intel_encoder *encoder;
+	struct drm_connector *connector;
+	struct drm_connector_state *old_conn_state, *new_conn_state;
+	int i;
+
+	for_each_intel_encoder(&dev_priv->drm, encoder) {
+		bool enabled = false, found = false;
+		enum pipe pipe;
+
+		drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",
+			    encoder->base.base.id,
+			    encoder->base.name);
+
+		for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
+						   new_conn_state, i) {
+			if (old_conn_state->best_encoder == &encoder->base)
+				found = true;
+
+			if (new_conn_state->best_encoder != &encoder->base)
+				continue;
+
+			found = true;
+			enabled = true;
+
+			I915_STATE_WARN(new_conn_state->crtc !=
+					encoder->base.crtc,
+					"connector's crtc doesn't match encoder crtc\n");
+		}
+
+		if (!found)
+			continue;
+
+		I915_STATE_WARN(!!encoder->base.crtc != enabled,
+				"encoder's enabled state mismatch (expected %i, found %i)\n",
+				!!encoder->base.crtc, enabled);
+
+		if (!encoder->base.crtc) {
+			bool active;
+
+			active = encoder->get_hw_state(encoder, &pipe);
+			I915_STATE_WARN(active,
+					"encoder detached but still enabled on pipe %c.\n",
+					pipe_name(pipe));
+		}
+	}
+}
+
+static void
+verify_crtc_state(struct intel_crtc *crtc,
+		  struct intel_crtc_state *old_crtc_state,
+		  struct intel_crtc_state *new_crtc_state)
+{
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_encoder *encoder;
+	struct intel_crtc_state *pipe_config = old_crtc_state;
+	struct drm_atomic_state *state = old_crtc_state->uapi.state;
+	struct intel_crtc *master_crtc;
+
+	__drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
+	intel_crtc_free_hw_state(old_crtc_state);
+	intel_crtc_state_reset(old_crtc_state, crtc);
+	old_crtc_state->uapi.state = state;
+
+	drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
+		    crtc->base.name);
+
+	pipe_config->hw.enable = new_crtc_state->hw.enable;
+
+	intel_crtc_get_pipe_config(pipe_config);
+
+	/* we keep both pipes enabled on 830 */
+	if (IS_I830(dev_priv) && pipe_config->hw.active)
+		pipe_config->hw.active = new_crtc_state->hw.active;
+
+	I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active,
+			"crtc active state doesn't match with hw state (expected %i, found %i)\n",
+			new_crtc_state->hw.active, pipe_config->hw.active);
+
+	I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
+			"transitional active state does not match atomic hw state (expected %i, found %i)\n",
+			new_crtc_state->hw.active, crtc->active);
+
+	master_crtc = intel_master_crtc(new_crtc_state);
+
+	for_each_encoder_on_crtc(dev, &master_crtc->base, encoder) {
+		enum pipe pipe;
+		bool active;
+
+		active = encoder->get_hw_state(encoder, &pipe);
+		I915_STATE_WARN(active != new_crtc_state->hw.active,
+				"[ENCODER:%i] active %i with crtc active %i\n",
+				encoder->base.base.id, active,
+				new_crtc_state->hw.active);
+
+		I915_STATE_WARN(active && master_crtc->pipe != pipe,
+				"Encoder connected to wrong pipe %c\n",
+				pipe_name(pipe));
+
+		if (active)
+			intel_encoder_get_config(encoder, pipe_config);
+	}
+
+	if (!new_crtc_state->hw.active)
+		return;
+
+	intel_pipe_config_sanity_check(dev_priv, pipe_config);
+
+	if (!intel_pipe_config_compare(new_crtc_state,
+				       pipe_config, false)) {
+		I915_STATE_WARN(1, "pipe state doesn't match!\n");
+		intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
+		intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
+	}
+}
+
+void intel_modeset_verify_crtc(struct intel_crtc *crtc,
+			       struct intel_atomic_state *state,
+			       struct intel_crtc_state *old_crtc_state,
+			       struct intel_crtc_state *new_crtc_state)
+{
+	if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
+		return;
+
+	intel_wm_state_verify(crtc, new_crtc_state);
+	verify_connector_state(state, crtc);
+	verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
+	intel_shared_dpll_state_verify(crtc, old_crtc_state, new_crtc_state);
+	intel_mpllb_state_verify(state, new_crtc_state);
+}
+
+void intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
+				   struct intel_atomic_state *state)
+{
+	verify_encoder_state(dev_priv, state);
+	verify_connector_state(state, NULL);
+	intel_shared_dpll_verify_disabled(dev_priv);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.h b/drivers/gpu/drm/i915/display/intel_modeset_verify.h
new file mode 100644
index 0000000000000..2d6fbe4f7846d
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_MODESET_VERIFY_H__
+#define __INTEL_MODESET_VERIFY_H__
+
+struct drm_i915_private;
+struct intel_atomic_state;
+struct intel_crtc;
+struct intel_crtc_state;
+
+void intel_modeset_verify_crtc(struct intel_crtc *crtc,
+			       struct intel_atomic_state *state,
+			       struct intel_crtc_state *old_crtc_state,
+			       struct intel_crtc_state *new_crtc_state);
+void intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
+				   struct intel_atomic_state *state);
+
+#endif /* __INTEL_MODESET_VERIFY_H__ */
-- 
GitLab


From 3e29d3b318533ad031396a40322e0ae1aaece943 Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Thu, 16 Jun 2022 12:48:16 +0300
Subject: [PATCH 0746/1731] drm/i915/display: split out crtc state dump to a
 separate file
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Declutter intel_display.c by splitting out crtc state dumping to a
separate file.

v2: intel_pipe_config_dump -> intel_crtc_state_dump

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/f72a5626473692910263671af91e02251ed87eea.1655372759.git.jani.nikula@intel.com
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 .../drm/i915/display/intel_crtc_state_dump.c  | 314 +++++++++++++++++
 .../drm/i915/display/intel_crtc_state_dump.h  |  16 +
 drivers/gpu/drm/i915/display/intel_display.c  | 315 +-----------------
 drivers/gpu/drm/i915/display/intel_display.h  |   3 -
 .../drm/i915/display/intel_modeset_verify.c   |   5 +-
 6 files changed, 340 insertions(+), 314 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_crtc_state_dump.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c9dcb533f1bcc..ea25322c64e07 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -210,6 +210,7 @@ i915-y += \
 	display/intel_combo_phy.o \
 	display/intel_connector.o \
 	display/intel_crtc.o \
+	display/intel_crtc_state_dump.o \
 	display/intel_cursor.o \
 	display/intel_display.o \
 	display/intel_display_power.o \
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
new file mode 100644
index 0000000000000..188509837926f
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -0,0 +1,314 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_crtc_state_dump.h"
+#include "intel_display_types.h"
+#include "intel_hdmi.h"
+#include "intel_vrr.h"
+
+static void intel_dump_crtc_timings(struct drm_i915_private *i915,
+				    const struct drm_display_mode *mode)
+{
+	drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
+		    "type: 0x%x flags: 0x%x\n",
+		    mode->crtc_clock,
+		    mode->crtc_hdisplay, mode->crtc_hsync_start,
+		    mode->crtc_hsync_end, mode->crtc_htotal,
+		    mode->crtc_vdisplay, mode->crtc_vsync_start,
+		    mode->crtc_vsync_end, mode->crtc_vtotal,
+		    mode->type, mode->flags);
+}
+
+static void
+intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
+		      const char *id, unsigned int lane_count,
+		      const struct intel_link_m_n *m_n)
+{
+	struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
+
+	drm_dbg_kms(&i915->drm,
+		    "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",
+		    id, lane_count,
+		    m_n->data_m, m_n->data_n,
+		    m_n->link_m, m_n->link_n, m_n->tu);
+}
+
+static void
+intel_dump_infoframe(struct drm_i915_private *dev_priv,
+		     const union hdmi_infoframe *frame)
+{
+	if (!drm_debug_enabled(DRM_UT_KMS))
+		return;
+
+	hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
+}
+
+static void
+intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
+		      const struct drm_dp_vsc_sdp *vsc)
+{
+	if (!drm_debug_enabled(DRM_UT_KMS))
+		return;
+
+	drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
+}
+
+#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
+
+static const char * const output_type_str[] = {
+	OUTPUT_TYPE(UNUSED),
+	OUTPUT_TYPE(ANALOG),
+	OUTPUT_TYPE(DVO),
+	OUTPUT_TYPE(SDVO),
+	OUTPUT_TYPE(LVDS),
+	OUTPUT_TYPE(TVOUT),
+	OUTPUT_TYPE(HDMI),
+	OUTPUT_TYPE(DP),
+	OUTPUT_TYPE(EDP),
+	OUTPUT_TYPE(DSI),
+	OUTPUT_TYPE(DDI),
+	OUTPUT_TYPE(DP_MST),
+};
+
+#undef OUTPUT_TYPE
+
+static void snprintf_output_types(char *buf, size_t len,
+				  unsigned int output_types)
+{
+	char *str = buf;
+	int i;
+
+	str[0] = '\0';
+
+	for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
+		int r;
+
+		if ((output_types & BIT(i)) == 0)
+			continue;
+
+		r = snprintf(str, len, "%s%s",
+			     str != buf ? "," : "", output_type_str[i]);
+		if (r >= len)
+			break;
+		str += r;
+		len -= r;
+
+		output_types &= ~BIT(i);
+	}
+
+	WARN_ON_ONCE(output_types != 0);
+}
+
+static const char * const output_format_str[] = {
+	[INTEL_OUTPUT_FORMAT_RGB] = "RGB",
+	[INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
+	[INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
+};
+
+static const char *output_formats(enum intel_output_format format)
+{
+	if (format >= ARRAY_SIZE(output_format_str))
+		return "invalid";
+	return output_format_str[format];
+}
+
+static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
+{
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+	struct drm_i915_private *i915 = to_i915(plane->base.dev);
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+
+	if (!fb) {
+		drm_dbg_kms(&i915->drm,
+			    "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
+			    plane->base.base.id, plane->base.name,
+			    str_yes_no(plane_state->uapi.visible));
+		return;
+	}
+
+	drm_dbg_kms(&i915->drm,
+		    "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n",
+		    plane->base.base.id, plane->base.name,
+		    fb->base.id, fb->width, fb->height, &fb->format->format,
+		    fb->modifier, str_yes_no(plane_state->uapi.visible));
+	drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
+		    plane_state->hw.rotation, plane_state->scaler_id);
+	if (plane_state->uapi.visible)
+		drm_dbg_kms(&i915->drm,
+			    "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
+			    DRM_RECT_FP_ARG(&plane_state->uapi.src),
+			    DRM_RECT_ARG(&plane_state->uapi.dst));
+}
+
+void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
+			   struct intel_atomic_state *state,
+			   const char *context)
+{
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct intel_plane_state *plane_state;
+	struct intel_plane *plane;
+	char buf[64];
+	int i;
+
+	drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
+		    crtc->base.base.id, crtc->base.name,
+		    str_yes_no(pipe_config->hw.enable), context);
+
+	if (!pipe_config->hw.enable)
+		goto dump_planes;
+
+	snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
+	drm_dbg_kms(&dev_priv->drm,
+		    "active: %s, output_types: %s (0x%x), output format: %s\n",
+		    str_yes_no(pipe_config->hw.active),
+		    buf, pipe_config->output_types,
+		    output_formats(pipe_config->output_format));
+
+	drm_dbg_kms(&dev_priv->drm,
+		    "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
+		    transcoder_name(pipe_config->cpu_transcoder),
+		    pipe_config->pipe_bpp, pipe_config->dither);
+
+	drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
+		    transcoder_name(pipe_config->mst_master_transcoder));
+
+	drm_dbg_kms(&dev_priv->drm,
+		    "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
+		    transcoder_name(pipe_config->master_transcoder),
+		    pipe_config->sync_mode_slaves_mask);
+
+	drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s, pipes: 0x%x\n",
+		    intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" :
+		    intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no",
+		    pipe_config->bigjoiner_pipes);
+
+	drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n",
+		    str_enabled_disabled(pipe_config->splitter.enable),
+		    pipe_config->splitter.link_count,
+		    pipe_config->splitter.pixel_overlap);
+
+	if (pipe_config->has_pch_encoder)
+		intel_dump_m_n_config(pipe_config, "fdi",
+				      pipe_config->fdi_lanes,
+				      &pipe_config->fdi_m_n);
+
+	if (intel_crtc_has_dp_encoder(pipe_config)) {
+		intel_dump_m_n_config(pipe_config, "dp m_n",
+				      pipe_config->lane_count,
+				      &pipe_config->dp_m_n);
+		intel_dump_m_n_config(pipe_config, "dp m2_n2",
+				      pipe_config->lane_count,
+				      &pipe_config->dp_m2_n2);
+	}
+
+	drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n",
+		    pipe_config->framestart_delay, pipe_config->msa_timing_delay);
+
+	drm_dbg_kms(&dev_priv->drm,
+		    "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
+		    pipe_config->has_audio, pipe_config->has_infoframe,
+		    pipe_config->infoframes.enable);
+
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
+		drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
+			    pipe_config->infoframes.gcp);
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
+		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
+		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
+		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
+		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
+		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
+		intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
+
+	drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
+		    str_yes_no(pipe_config->vrr.enable),
+		    pipe_config->vrr.vmin, pipe_config->vrr.vmax,
+		    pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
+		    pipe_config->vrr.flipline,
+		    intel_vrr_vmin_vblank_start(pipe_config),
+		    intel_vrr_vmax_vblank_start(pipe_config));
+
+	drm_dbg_kms(&dev_priv->drm, "requested mode: " DRM_MODE_FMT "\n",
+		    DRM_MODE_ARG(&pipe_config->hw.mode));
+	drm_dbg_kms(&dev_priv->drm, "adjusted mode: " DRM_MODE_FMT "\n",
+		    DRM_MODE_ARG(&pipe_config->hw.adjusted_mode));
+	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
+	drm_dbg_kms(&dev_priv->drm, "pipe mode: " DRM_MODE_FMT "\n",
+		    DRM_MODE_ARG(&pipe_config->hw.pipe_mode));
+	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
+	drm_dbg_kms(&dev_priv->drm,
+		    "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n",
+		    pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src),
+		    pipe_config->pixel_rate);
+
+	drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
+		    pipe_config->linetime, pipe_config->ips_linetime);
+
+	if (DISPLAY_VER(dev_priv) >= 9)
+		drm_dbg_kms(&dev_priv->drm,
+			    "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
+			    crtc->num_scalers,
+			    pipe_config->scaler_state.scaler_users,
+			    pipe_config->scaler_state.scaler_id);
+
+	if (HAS_GMCH(dev_priv))
+		drm_dbg_kms(&dev_priv->drm,
+			    "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
+			    pipe_config->gmch_pfit.control,
+			    pipe_config->gmch_pfit.pgm_ratios,
+			    pipe_config->gmch_pfit.lvds_border_bits);
+	else
+		drm_dbg_kms(&dev_priv->drm,
+			    "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
+			    DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
+			    str_enabled_disabled(pipe_config->pch_pfit.enabled),
+			    str_yes_no(pipe_config->pch_pfit.force_thru));
+
+	drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n",
+		    pipe_config->ips_enabled, pipe_config->double_wide,
+		    pipe_config->has_drrs);
+
+	intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
+
+	if (IS_CHERRYVIEW(dev_priv))
+		drm_dbg_kms(&dev_priv->drm,
+			    "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
+			    pipe_config->cgm_mode, pipe_config->gamma_mode,
+			    pipe_config->gamma_enable, pipe_config->csc_enable);
+	else
+		drm_dbg_kms(&dev_priv->drm,
+			    "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
+			    pipe_config->csc_mode, pipe_config->gamma_mode,
+			    pipe_config->gamma_enable, pipe_config->csc_enable);
+
+	drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
+		    pipe_config->hw.degamma_lut ?
+		    drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
+		    pipe_config->hw.gamma_lut ?
+		    drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
+
+dump_planes:
+	if (!state)
+		return;
+
+	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+		if (plane->pipe == crtc->pipe)
+			intel_dump_plane_state(plane_state);
+	}
+}
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
new file mode 100644
index 0000000000000..9399c35b7e5ed
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_CRTC_STATE_DUMP_H__
+#define __INTEL_CRTC_STATE_DUMP_H__
+
+struct intel_crtc_state;
+struct intel_atomic_state;
+
+void intel_crtc_state_dump(const struct intel_crtc_state *crtc_state,
+			   struct intel_atomic_state *state,
+			   const char *context);
+
+#endif /* __INTEL_CRTC_STATE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c7a7599657932..2945b498601c8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -87,6 +87,7 @@
 #include "intel_cdclk.h"
 #include "intel_color.h"
 #include "intel_crtc.h"
+#include "intel_crtc_state_dump.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_dmc.h"
@@ -5058,310 +5059,6 @@ compute_baseline_pipe_bpp(struct intel_atomic_state *state,
 	return 0;
 }
 
-static void intel_dump_crtc_timings(struct drm_i915_private *i915,
-				    const struct drm_display_mode *mode)
-{
-	drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
-		    "type: 0x%x flags: 0x%x\n",
-		    mode->crtc_clock,
-		    mode->crtc_hdisplay, mode->crtc_hsync_start,
-		    mode->crtc_hsync_end, mode->crtc_htotal,
-		    mode->crtc_vdisplay, mode->crtc_vsync_start,
-		    mode->crtc_vsync_end, mode->crtc_vtotal,
-		    mode->type, mode->flags);
-}
-
-static void
-intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
-		      const char *id, unsigned int lane_count,
-		      const struct intel_link_m_n *m_n)
-{
-	struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
-
-	drm_dbg_kms(&i915->drm,
-		    "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",
-		    id, lane_count,
-		    m_n->data_m, m_n->data_n,
-		    m_n->link_m, m_n->link_n, m_n->tu);
-}
-
-static void
-intel_dump_infoframe(struct drm_i915_private *dev_priv,
-		     const union hdmi_infoframe *frame)
-{
-	if (!drm_debug_enabled(DRM_UT_KMS))
-		return;
-
-	hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
-}
-
-static void
-intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
-		      const struct drm_dp_vsc_sdp *vsc)
-{
-	if (!drm_debug_enabled(DRM_UT_KMS))
-		return;
-
-	drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
-}
-
-#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
-
-static const char * const output_type_str[] = {
-	OUTPUT_TYPE(UNUSED),
-	OUTPUT_TYPE(ANALOG),
-	OUTPUT_TYPE(DVO),
-	OUTPUT_TYPE(SDVO),
-	OUTPUT_TYPE(LVDS),
-	OUTPUT_TYPE(TVOUT),
-	OUTPUT_TYPE(HDMI),
-	OUTPUT_TYPE(DP),
-	OUTPUT_TYPE(EDP),
-	OUTPUT_TYPE(DSI),
-	OUTPUT_TYPE(DDI),
-	OUTPUT_TYPE(DP_MST),
-};
-
-#undef OUTPUT_TYPE
-
-static void snprintf_output_types(char *buf, size_t len,
-				  unsigned int output_types)
-{
-	char *str = buf;
-	int i;
-
-	str[0] = '\0';
-
-	for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
-		int r;
-
-		if ((output_types & BIT(i)) == 0)
-			continue;
-
-		r = snprintf(str, len, "%s%s",
-			     str != buf ? "," : "", output_type_str[i]);
-		if (r >= len)
-			break;
-		str += r;
-		len -= r;
-
-		output_types &= ~BIT(i);
-	}
-
-	WARN_ON_ONCE(output_types != 0);
-}
-
-static const char * const output_format_str[] = {
-	[INTEL_OUTPUT_FORMAT_RGB] = "RGB",
-	[INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
-	[INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
-};
-
-static const char *output_formats(enum intel_output_format format)
-{
-	if (format >= ARRAY_SIZE(output_format_str))
-		return "invalid";
-	return output_format_str[format];
-}
-
-static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
-{
-	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
-	struct drm_i915_private *i915 = to_i915(plane->base.dev);
-	const struct drm_framebuffer *fb = plane_state->hw.fb;
-
-	if (!fb) {
-		drm_dbg_kms(&i915->drm,
-			    "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
-			    plane->base.base.id, plane->base.name,
-			    str_yes_no(plane_state->uapi.visible));
-		return;
-	}
-
-	drm_dbg_kms(&i915->drm,
-		    "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n",
-		    plane->base.base.id, plane->base.name,
-		    fb->base.id, fb->width, fb->height, &fb->format->format,
-		    fb->modifier, str_yes_no(plane_state->uapi.visible));
-	drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
-		    plane_state->hw.rotation, plane_state->scaler_id);
-	if (plane_state->uapi.visible)
-		drm_dbg_kms(&i915->drm,
-			    "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
-			    DRM_RECT_FP_ARG(&plane_state->uapi.src),
-			    DRM_RECT_ARG(&plane_state->uapi.dst));
-}
-
-void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
-			    struct intel_atomic_state *state,
-			    const char *context)
-{
-	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	const struct intel_plane_state *plane_state;
-	struct intel_plane *plane;
-	char buf[64];
-	int i;
-
-	drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
-		    crtc->base.base.id, crtc->base.name,
-		    str_yes_no(pipe_config->hw.enable), context);
-
-	if (!pipe_config->hw.enable)
-		goto dump_planes;
-
-	snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
-	drm_dbg_kms(&dev_priv->drm,
-		    "active: %s, output_types: %s (0x%x), output format: %s\n",
-		    str_yes_no(pipe_config->hw.active),
-		    buf, pipe_config->output_types,
-		    output_formats(pipe_config->output_format));
-
-	drm_dbg_kms(&dev_priv->drm,
-		    "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
-		    transcoder_name(pipe_config->cpu_transcoder),
-		    pipe_config->pipe_bpp, pipe_config->dither);
-
-	drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
-		    transcoder_name(pipe_config->mst_master_transcoder));
-
-	drm_dbg_kms(&dev_priv->drm,
-		    "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
-		    transcoder_name(pipe_config->master_transcoder),
-		    pipe_config->sync_mode_slaves_mask);
-
-	drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s, pipes: 0x%x\n",
-		    intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" :
-		    intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no",
-		    pipe_config->bigjoiner_pipes);
-
-	drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n",
-		    str_enabled_disabled(pipe_config->splitter.enable),
-		    pipe_config->splitter.link_count,
-		    pipe_config->splitter.pixel_overlap);
-
-	if (pipe_config->has_pch_encoder)
-		intel_dump_m_n_config(pipe_config, "fdi",
-				      pipe_config->fdi_lanes,
-				      &pipe_config->fdi_m_n);
-
-	if (intel_crtc_has_dp_encoder(pipe_config)) {
-		intel_dump_m_n_config(pipe_config, "dp m_n",
-				      pipe_config->lane_count,
-				      &pipe_config->dp_m_n);
-		intel_dump_m_n_config(pipe_config, "dp m2_n2",
-				      pipe_config->lane_count,
-				      &pipe_config->dp_m2_n2);
-	}
-
-	drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n",
-		    pipe_config->framestart_delay, pipe_config->msa_timing_delay);
-
-	drm_dbg_kms(&dev_priv->drm,
-		    "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
-		    pipe_config->has_audio, pipe_config->has_infoframe,
-		    pipe_config->infoframes.enable);
-
-	if (pipe_config->infoframes.enable &
-	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
-		drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
-			    pipe_config->infoframes.gcp);
-	if (pipe_config->infoframes.enable &
-	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
-		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
-	if (pipe_config->infoframes.enable &
-	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
-		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
-	if (pipe_config->infoframes.enable &
-	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
-		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
-	if (pipe_config->infoframes.enable &
-	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
-		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
-	if (pipe_config->infoframes.enable &
-	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
-		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
-	if (pipe_config->infoframes.enable &
-	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
-		intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
-
-	drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
-		    str_yes_no(pipe_config->vrr.enable),
-		    pipe_config->vrr.vmin, pipe_config->vrr.vmax,
-		    pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
-		    pipe_config->vrr.flipline,
-		    intel_vrr_vmin_vblank_start(pipe_config),
-		    intel_vrr_vmax_vblank_start(pipe_config));
-
-	drm_dbg_kms(&dev_priv->drm, "requested mode: " DRM_MODE_FMT "\n",
-		    DRM_MODE_ARG(&pipe_config->hw.mode));
-	drm_dbg_kms(&dev_priv->drm, "adjusted mode: " DRM_MODE_FMT "\n",
-		    DRM_MODE_ARG(&pipe_config->hw.adjusted_mode));
-	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
-	drm_dbg_kms(&dev_priv->drm, "pipe mode: " DRM_MODE_FMT "\n",
-		    DRM_MODE_ARG(&pipe_config->hw.pipe_mode));
-	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
-	drm_dbg_kms(&dev_priv->drm,
-		    "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n",
-		    pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src),
-		    pipe_config->pixel_rate);
-
-	drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
-		    pipe_config->linetime, pipe_config->ips_linetime);
-
-	if (DISPLAY_VER(dev_priv) >= 9)
-		drm_dbg_kms(&dev_priv->drm,
-			    "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
-			    crtc->num_scalers,
-			    pipe_config->scaler_state.scaler_users,
-			    pipe_config->scaler_state.scaler_id);
-
-	if (HAS_GMCH(dev_priv))
-		drm_dbg_kms(&dev_priv->drm,
-			    "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
-			    pipe_config->gmch_pfit.control,
-			    pipe_config->gmch_pfit.pgm_ratios,
-			    pipe_config->gmch_pfit.lvds_border_bits);
-	else
-		drm_dbg_kms(&dev_priv->drm,
-			    "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
-			    DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
-			    str_enabled_disabled(pipe_config->pch_pfit.enabled),
-			    str_yes_no(pipe_config->pch_pfit.force_thru));
-
-	drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n",
-		    pipe_config->ips_enabled, pipe_config->double_wide,
-		    pipe_config->has_drrs);
-
-	intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
-
-	if (IS_CHERRYVIEW(dev_priv))
-		drm_dbg_kms(&dev_priv->drm,
-			    "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
-			    pipe_config->cgm_mode, pipe_config->gamma_mode,
-			    pipe_config->gamma_enable, pipe_config->csc_enable);
-	else
-		drm_dbg_kms(&dev_priv->drm,
-			    "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
-			    pipe_config->csc_mode, pipe_config->gamma_mode,
-			    pipe_config->gamma_enable, pipe_config->csc_enable);
-
-	drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
-		    pipe_config->hw.degamma_lut ?
-		    drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
-		    pipe_config->hw.gamma_lut ?
-		    drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
-
-dump_planes:
-	if (!state)
-		return;
-
-	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
-		if (plane->pipe == crtc->pipe)
-			intel_dump_plane_state(plane_state);
-	}
-}
-
 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
 {
 	struct drm_device *dev = state->base.dev;
@@ -7392,9 +7089,9 @@ static int intel_atomic_check(struct drm_device *dev,
 		    !new_crtc_state->update_pipe)
 			continue;
 
-		intel_dump_pipe_config(new_crtc_state, state,
-				       intel_crtc_needs_modeset(new_crtc_state) ?
-				       "[modeset]" : "[fastset]");
+		intel_crtc_state_dump(new_crtc_state, state,
+				      intel_crtc_needs_modeset(new_crtc_state) ?
+				      "[modeset]" : "[fastset]");
 	}
 
 	return 0;
@@ -7409,7 +7106,7 @@ static int intel_atomic_check(struct drm_device *dev,
 	 */
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i)
-		intel_dump_pipe_config(new_crtc_state, state, "[failed]");
+		intel_crtc_state_dump(new_crtc_state, state, "[failed]");
 
 	return ret;
 }
@@ -9898,7 +9595,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
 			to_intel_crtc_state(crtc->base.state);
 
 		intel_sanitize_crtc(crtc, ctx);
-		intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
+		intel_crtc_state_dump(crtc_state, NULL, "[setup_hw_state]");
 	}
 
 	intel_modeset_update_connector_atomic_state(dev);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 70410eeb19c8f..2feb8ae5d5d48 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -563,9 +563,6 @@ bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
 bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 			       const struct intel_crtc_state *pipe_config,
 			       bool fastset);
-void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
-			    struct intel_atomic_state *state,
-			    const char *context);
 
 void intel_plane_destroy(struct drm_plane *plane);
 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index 1655c903e2f05..0e2ed07264591 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -10,6 +10,7 @@
 #include "i915_drv.h"
 #include "intel_atomic.h"
 #include "intel_crtc.h"
+#include "intel_crtc_state_dump.h"
 #include "intel_display.h"
 #include "intel_display_types.h"
 #include "intel_fdi.h"
@@ -216,8 +217,8 @@ verify_crtc_state(struct intel_crtc *crtc,
 	if (!intel_pipe_config_compare(new_crtc_state,
 				       pipe_config, false)) {
 		I915_STATE_WARN(1, "pipe state doesn't match!\n");
-		intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
-		intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
+		intel_crtc_state_dump(pipe_config, NULL, "[hw state]");
+		intel_crtc_state_dump(new_crtc_state, NULL, "[sw state]");
 	}
 }
 
-- 
GitLab


From ac1b49be7fa8cddcc194ce66aa453e2b2cff5831 Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Thu, 16 Jun 2022 12:48:17 +0300
Subject: [PATCH 0747/1731] drm/i915/display: change who adds [] around crtc
 state dump context string
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add the brackets [] around crtc state dump context string in
intel_crtc_state_dump() so the callers don't have to.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/c7d671279fb7d99eaf882bcb88c5c1d653755fb1.1655372759.git.jani.nikula@intel.com
---
 drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 2 +-
 drivers/gpu/drm/i915/display/intel_display.c         | 6 +++---
 drivers/gpu/drm/i915/display/intel_modeset_verify.c  | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 188509837926f..35c6277211991 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -154,7 +154,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 	char buf[64];
 	int i;
 
-	drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
+	drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s [%s]\n",
 		    crtc->base.base.id, crtc->base.name,
 		    str_yes_no(pipe_config->hw.enable), context);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2945b498601c8..44bfc1729b40d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7091,7 +7091,7 @@ static int intel_atomic_check(struct drm_device *dev,
 
 		intel_crtc_state_dump(new_crtc_state, state,
 				      intel_crtc_needs_modeset(new_crtc_state) ?
-				      "[modeset]" : "[fastset]");
+				      "modeset" : "fastset");
 	}
 
 	return 0;
@@ -7106,7 +7106,7 @@ static int intel_atomic_check(struct drm_device *dev,
 	 */
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i)
-		intel_crtc_state_dump(new_crtc_state, state, "[failed]");
+		intel_crtc_state_dump(new_crtc_state, state, "failed");
 
 	return ret;
 }
@@ -9595,7 +9595,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
 			to_intel_crtc_state(crtc->base.state);
 
 		intel_sanitize_crtc(crtc, ctx);
-		intel_crtc_state_dump(crtc_state, NULL, "[setup_hw_state]");
+		intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state");
 	}
 
 	intel_modeset_update_connector_atomic_state(dev);
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index 0e2ed07264591..a91586d77cb64 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -217,8 +217,8 @@ verify_crtc_state(struct intel_crtc *crtc,
 	if (!intel_pipe_config_compare(new_crtc_state,
 				       pipe_config, false)) {
 		I915_STATE_WARN(1, "pipe state doesn't match!\n");
-		intel_crtc_state_dump(pipe_config, NULL, "[hw state]");
-		intel_crtc_state_dump(new_crtc_state, NULL, "[sw state]");
+		intel_crtc_state_dump(pipe_config, NULL, "hw state");
+		intel_crtc_state_dump(new_crtc_state, NULL, "sw state");
 	}
 }
 
-- 
GitLab


From 319ff09312934b08b532e605042dd59f41b74458 Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Thu, 16 Jun 2022 12:48:18 +0300
Subject: [PATCH 0748/1731] drm/i915/display: rename dev_priv -> i915 in crtc
 state dump
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Rename dev_priv to i915 in crtc state dumping code.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/3c1dafd45757d2de2e3f8404674168f2b1241170.1655372759.git.jani.nikula@intel.com
---
 .../drm/i915/display/intel_crtc_state_dump.c  | 80 +++++++++----------
 1 file changed, 40 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 35c6277211991..4ca6e9493ff2f 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -37,23 +37,23 @@ intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
 }
 
 static void
-intel_dump_infoframe(struct drm_i915_private *dev_priv,
+intel_dump_infoframe(struct drm_i915_private *i915,
 		     const union hdmi_infoframe *frame)
 {
 	if (!drm_debug_enabled(DRM_UT_KMS))
 		return;
 
-	hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
+	hdmi_infoframe_log(KERN_DEBUG, i915->drm.dev, frame);
 }
 
 static void
-intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
+intel_dump_dp_vsc_sdp(struct drm_i915_private *i915,
 		      const struct drm_dp_vsc_sdp *vsc)
 {
 	if (!drm_debug_enabled(DRM_UT_KMS))
 		return;
 
-	drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
+	drm_dp_vsc_sdp_log(KERN_DEBUG, i915->drm.dev, vsc);
 }
 
 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
@@ -148,13 +148,13 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 			   const char *context)
 {
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	const struct intel_plane_state *plane_state;
 	struct intel_plane *plane;
 	char buf[64];
 	int i;
 
-	drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s [%s]\n",
+	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] enable: %s [%s]\n",
 		    crtc->base.base.id, crtc->base.name,
 		    str_yes_no(pipe_config->hw.enable), context);
 
@@ -162,31 +162,31 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 		goto dump_planes;
 
 	snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
-	drm_dbg_kms(&dev_priv->drm,
+	drm_dbg_kms(&i915->drm,
 		    "active: %s, output_types: %s (0x%x), output format: %s\n",
 		    str_yes_no(pipe_config->hw.active),
 		    buf, pipe_config->output_types,
 		    output_formats(pipe_config->output_format));
 
-	drm_dbg_kms(&dev_priv->drm,
+	drm_dbg_kms(&i915->drm,
 		    "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
 		    transcoder_name(pipe_config->cpu_transcoder),
 		    pipe_config->pipe_bpp, pipe_config->dither);
 
-	drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
+	drm_dbg_kms(&i915->drm, "MST master transcoder: %s\n",
 		    transcoder_name(pipe_config->mst_master_transcoder));
 
-	drm_dbg_kms(&dev_priv->drm,
+	drm_dbg_kms(&i915->drm,
 		    "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
 		    transcoder_name(pipe_config->master_transcoder),
 		    pipe_config->sync_mode_slaves_mask);
 
-	drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s, pipes: 0x%x\n",
+	drm_dbg_kms(&i915->drm, "bigjoiner: %s, pipes: 0x%x\n",
 		    intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" :
 		    intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no",
 		    pipe_config->bigjoiner_pipes);
 
-	drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n",
+	drm_dbg_kms(&i915->drm, "splitter: %s, link count %d, overlap %d\n",
 		    str_enabled_disabled(pipe_config->splitter.enable),
 		    pipe_config->splitter.link_count,
 		    pipe_config->splitter.pixel_overlap);
@@ -205,38 +205,38 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 				      &pipe_config->dp_m2_n2);
 	}
 
-	drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n",
+	drm_dbg_kms(&i915->drm, "framestart delay: %d, MSA timing delay: %d\n",
 		    pipe_config->framestart_delay, pipe_config->msa_timing_delay);
 
-	drm_dbg_kms(&dev_priv->drm,
+	drm_dbg_kms(&i915->drm,
 		    "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
 		    pipe_config->has_audio, pipe_config->has_infoframe,
 		    pipe_config->infoframes.enable);
 
 	if (pipe_config->infoframes.enable &
 	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
-		drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
+		drm_dbg_kms(&i915->drm, "GCP: 0x%x\n",
 			    pipe_config->infoframes.gcp);
 	if (pipe_config->infoframes.enable &
 	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
-		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
+		intel_dump_infoframe(i915, &pipe_config->infoframes.avi);
 	if (pipe_config->infoframes.enable &
 	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
-		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
+		intel_dump_infoframe(i915, &pipe_config->infoframes.spd);
 	if (pipe_config->infoframes.enable &
 	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
-		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
+		intel_dump_infoframe(i915, &pipe_config->infoframes.hdmi);
 	if (pipe_config->infoframes.enable &
 	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
-		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
+		intel_dump_infoframe(i915, &pipe_config->infoframes.drm);
 	if (pipe_config->infoframes.enable &
 	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
-		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
+		intel_dump_infoframe(i915, &pipe_config->infoframes.drm);
 	if (pipe_config->infoframes.enable &
 	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
-		intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
+		intel_dump_dp_vsc_sdp(i915, &pipe_config->infoframes.vsc);
 
-	drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
+	drm_dbg_kms(&i915->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
 		    str_yes_no(pipe_config->vrr.enable),
 		    pipe_config->vrr.vmin, pipe_config->vrr.vmax,
 		    pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
@@ -244,60 +244,60 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 		    intel_vrr_vmin_vblank_start(pipe_config),
 		    intel_vrr_vmax_vblank_start(pipe_config));
 
-	drm_dbg_kms(&dev_priv->drm, "requested mode: " DRM_MODE_FMT "\n",
+	drm_dbg_kms(&i915->drm, "requested mode: " DRM_MODE_FMT "\n",
 		    DRM_MODE_ARG(&pipe_config->hw.mode));
-	drm_dbg_kms(&dev_priv->drm, "adjusted mode: " DRM_MODE_FMT "\n",
+	drm_dbg_kms(&i915->drm, "adjusted mode: " DRM_MODE_FMT "\n",
 		    DRM_MODE_ARG(&pipe_config->hw.adjusted_mode));
-	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
-	drm_dbg_kms(&dev_priv->drm, "pipe mode: " DRM_MODE_FMT "\n",
+	intel_dump_crtc_timings(i915, &pipe_config->hw.adjusted_mode);
+	drm_dbg_kms(&i915->drm, "pipe mode: " DRM_MODE_FMT "\n",
 		    DRM_MODE_ARG(&pipe_config->hw.pipe_mode));
-	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
-	drm_dbg_kms(&dev_priv->drm,
+	intel_dump_crtc_timings(i915, &pipe_config->hw.pipe_mode);
+	drm_dbg_kms(&i915->drm,
 		    "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n",
 		    pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src),
 		    pipe_config->pixel_rate);
 
-	drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
+	drm_dbg_kms(&i915->drm, "linetime: %d, ips linetime: %d\n",
 		    pipe_config->linetime, pipe_config->ips_linetime);
 
-	if (DISPLAY_VER(dev_priv) >= 9)
-		drm_dbg_kms(&dev_priv->drm,
+	if (DISPLAY_VER(i915) >= 9)
+		drm_dbg_kms(&i915->drm,
 			    "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
 			    crtc->num_scalers,
 			    pipe_config->scaler_state.scaler_users,
 			    pipe_config->scaler_state.scaler_id);
 
-	if (HAS_GMCH(dev_priv))
-		drm_dbg_kms(&dev_priv->drm,
+	if (HAS_GMCH(i915))
+		drm_dbg_kms(&i915->drm,
 			    "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
 			    pipe_config->gmch_pfit.control,
 			    pipe_config->gmch_pfit.pgm_ratios,
 			    pipe_config->gmch_pfit.lvds_border_bits);
 	else
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(&i915->drm,
 			    "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
 			    DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
 			    str_enabled_disabled(pipe_config->pch_pfit.enabled),
 			    str_yes_no(pipe_config->pch_pfit.force_thru));
 
-	drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n",
+	drm_dbg_kms(&i915->drm, "ips: %i, double wide: %i, drrs: %i\n",
 		    pipe_config->ips_enabled, pipe_config->double_wide,
 		    pipe_config->has_drrs);
 
-	intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
+	intel_dpll_dump_hw_state(i915, &pipe_config->dpll_hw_state);
 
-	if (IS_CHERRYVIEW(dev_priv))
-		drm_dbg_kms(&dev_priv->drm,
+	if (IS_CHERRYVIEW(i915))
+		drm_dbg_kms(&i915->drm,
 			    "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
 			    pipe_config->cgm_mode, pipe_config->gamma_mode,
 			    pipe_config->gamma_enable, pipe_config->csc_enable);
 	else
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(&i915->drm,
 			    "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
 			    pipe_config->csc_mode, pipe_config->gamma_mode,
 			    pipe_config->gamma_enable, pipe_config->csc_enable);
 
-	drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
+	drm_dbg_kms(&i915->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
 		    pipe_config->hw.degamma_lut ?
 		    drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
 		    pipe_config->hw.gamma_lut ?
-- 
GitLab


From c5dc92006d50fb55a916755206cbac1022373134 Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Thu, 16 Jun 2022 12:48:20 +0300
Subject: [PATCH 0749/1731] drm/i915/display: some struct drm_i915_private
 *i915 conversions
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Prefer struct drm_i915_private *i915 over struct drm_device or dev_priv.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1bb84c4fffde5025ddc411148d529381a587e1e1.1655372759.git.jani.nikula@intel.com
---
 drivers/gpu/drm/i915/display/intel_display.c | 60 ++++++++++----------
 1 file changed, 30 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 44bfc1729b40d..4a3799203729e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -832,7 +832,7 @@ intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
 }
 
 static int
-__intel_display_resume(struct drm_device *dev,
+__intel_display_resume(struct drm_i915_private *i915,
 		       struct drm_atomic_state *state,
 		       struct drm_modeset_acquire_ctx *ctx)
 {
@@ -840,8 +840,8 @@ __intel_display_resume(struct drm_device *dev,
 	struct drm_crtc *crtc;
 	int i, ret;
 
-	intel_modeset_setup_hw_state(dev, ctx);
-	intel_vga_redisable(to_i915(dev));
+	intel_modeset_setup_hw_state(&i915->drm, ctx);
+	intel_vga_redisable(i915);
 
 	if (!state)
 		return 0;
@@ -861,12 +861,13 @@ __intel_display_resume(struct drm_device *dev,
 	}
 
 	/* ignore any reset values/BIOS leftovers in the WM registers */
-	if (!HAS_GMCH(to_i915(dev)))
+	if (!HAS_GMCH(i915))
 		to_intel_atomic_state(state)->skip_intermediate_wm = true;
 
 	ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
 
-	drm_WARN_ON(dev, ret == -EDEADLK);
+	drm_WARN_ON(&i915->drm, ret == -EDEADLK);
+
 	return ret;
 }
 
@@ -939,56 +940,55 @@ void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
 	state->acquire_ctx = ctx;
 }
 
-void intel_display_finish_reset(struct drm_i915_private *dev_priv)
+void intel_display_finish_reset(struct drm_i915_private *i915)
 {
-	struct drm_device *dev = &dev_priv->drm;
-	struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
+	struct drm_modeset_acquire_ctx *ctx = &i915->reset_ctx;
 	struct drm_atomic_state *state;
 	int ret;
 
-	if (!HAS_DISPLAY(dev_priv))
+	if (!HAS_DISPLAY(i915))
 		return;
 
 	/* reset doesn't touch the display */
-	if (!test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags))
+	if (!test_bit(I915_RESET_MODESET, &to_gt(i915)->reset.flags))
 		return;
 
-	state = fetch_and_zero(&dev_priv->modeset_restore_state);
+	state = fetch_and_zero(&i915->modeset_restore_state);
 	if (!state)
 		goto unlock;
 
 	/* reset doesn't touch the display */
-	if (!gpu_reset_clobbers_display(dev_priv)) {
+	if (!gpu_reset_clobbers_display(i915)) {
 		/* for testing only restore the display */
-		ret = __intel_display_resume(dev, state, ctx);
+		ret = __intel_display_resume(i915, state, ctx);
 		if (ret)
-			drm_err(&dev_priv->drm,
+			drm_err(&i915->drm,
 				"Restoring old state failed with %i\n", ret);
 	} else {
 		/*
 		 * The display has been reset as well,
 		 * so need a full re-initialization.
 		 */
-		intel_pps_unlock_regs_wa(dev_priv);
-		intel_modeset_init_hw(dev_priv);
-		intel_init_clock_gating(dev_priv);
-		intel_hpd_init(dev_priv);
+		intel_pps_unlock_regs_wa(i915);
+		intel_modeset_init_hw(i915);
+		intel_init_clock_gating(i915);
+		intel_hpd_init(i915);
 
-		ret = __intel_display_resume(dev, state, ctx);
+		ret = __intel_display_resume(i915, state, ctx);
 		if (ret)
-			drm_err(&dev_priv->drm,
+			drm_err(&i915->drm,
 				"Restoring old state failed with %i\n", ret);
 
-		intel_hpd_poll_disable(dev_priv);
+		intel_hpd_poll_disable(i915);
 	}
 
 	drm_atomic_state_put(state);
 unlock:
 	drm_modeset_drop_locks(ctx);
 	drm_modeset_acquire_fini(ctx);
-	mutex_unlock(&dev->mode_config.mutex);
+	mutex_unlock(&i915->drm.mode_config.mutex);
 
-	clear_bit_unlock(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags);
+	clear_bit_unlock(I915_RESET_MODESET, &to_gt(i915)->reset.flags);
 }
 
 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
@@ -9632,15 +9632,15 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
 
 void intel_display_resume(struct drm_device *dev)
 {
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct drm_atomic_state *state = dev_priv->modeset_restore_state;
+	struct drm_i915_private *i915 = to_i915(dev);
+	struct drm_atomic_state *state = i915->modeset_restore_state;
 	struct drm_modeset_acquire_ctx ctx;
 	int ret;
 
-	if (!HAS_DISPLAY(dev_priv))
+	if (!HAS_DISPLAY(i915))
 		return;
 
-	dev_priv->modeset_restore_state = NULL;
+	i915->modeset_restore_state = NULL;
 	if (state)
 		state->acquire_ctx = &ctx;
 
@@ -9655,14 +9655,14 @@ void intel_display_resume(struct drm_device *dev)
 	}
 
 	if (!ret)
-		ret = __intel_display_resume(dev, state, &ctx);
+		ret = __intel_display_resume(i915, state, &ctx);
 
-	intel_enable_ipc(dev_priv);
+	intel_enable_ipc(i915);
 	drm_modeset_drop_locks(&ctx);
 	drm_modeset_acquire_fini(&ctx);
 
 	if (ret)
-		drm_err(&dev_priv->drm,
+		drm_err(&i915->drm,
 			"Restoring old state failed with %i\n", ret);
 	if (state)
 		drm_atomic_state_put(state);
-- 
GitLab


From cc26c2661fefea215f41edb665193324a5f99021 Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Thu, 16 Jun 2022 00:34:34 -0700
Subject: [PATCH 0750/1731] net: fix data-race in dev_isalive()

dev_isalive() is called under RTNL or dev_base_lock protection.

This means that changes to dev->reg_state should be done with both locks held.

syzbot reported:

BUG: KCSAN: data-race in register_netdevice / type_show

write to 0xffff888144ecf518 of 1 bytes by task 20886 on cpu 0:
register_netdevice+0xb9f/0xdf0 net/core/dev.c:10050
lapbeth_new_device drivers/net/wan/lapbether.c:414 [inline]
lapbeth_device_event+0x4a0/0x6c0 drivers/net/wan/lapbether.c:456
notifier_call_chain kernel/notifier.c:87 [inline]
raw_notifier_call_chain+0x53/0xb0 kernel/notifier.c:455
__dev_notify_flags+0x1d6/0x3a0
dev_change_flags+0xa2/0xc0 net/core/dev.c:8607
do_setlink+0x778/0x2230 net/core/rtnetlink.c:2780
__rtnl_newlink net/core/rtnetlink.c:3546 [inline]
rtnl_newlink+0x114c/0x16a0 net/core/rtnetlink.c:3593
rtnetlink_rcv_msg+0x811/0x8c0 net/core/rtnetlink.c:6089
netlink_rcv_skb+0x13e/0x240 net/netlink/af_netlink.c:2501
rtnetlink_rcv+0x18/0x20 net/core/rtnetlink.c:6107
netlink_unicast_kernel net/netlink/af_netlink.c:1319 [inline]
netlink_unicast+0x58a/0x660 net/netlink/af_netlink.c:1345
netlink_sendmsg+0x661/0x750 net/netlink/af_netlink.c:1921
sock_sendmsg_nosec net/socket.c:714 [inline]
sock_sendmsg net/socket.c:734 [inline]
__sys_sendto+0x21e/0x2c0 net/socket.c:2119
__do_sys_sendto net/socket.c:2131 [inline]
__se_sys_sendto net/socket.c:2127 [inline]
__x64_sys_sendto+0x74/0x90 net/socket.c:2127
do_syscall_x64 arch/x86/entry/common.c:50 [inline]
do_syscall_64+0x2b/0x70 arch/x86/entry/common.c:80
entry_SYSCALL_64_after_hwframe+0x46/0xb0

read to 0xffff888144ecf518 of 1 bytes by task 20423 on cpu 1:
dev_isalive net/core/net-sysfs.c:38 [inline]
netdev_show net/core/net-sysfs.c:50 [inline]
type_show+0x24/0x90 net/core/net-sysfs.c:112
dev_attr_show+0x35/0x90 drivers/base/core.c:2095
sysfs_kf_seq_show+0x175/0x240 fs/sysfs/file.c:59
kernfs_seq_show+0x75/0x80 fs/kernfs/file.c:162
seq_read_iter+0x2c3/0x8e0 fs/seq_file.c:230
kernfs_fop_read_iter+0xd1/0x2f0 fs/kernfs/file.c:235
call_read_iter include/linux/fs.h:2052 [inline]
new_sync_read fs/read_write.c:401 [inline]
vfs_read+0x5a5/0x6a0 fs/read_write.c:482
ksys_read+0xe8/0x1a0 fs/read_write.c:620
__do_sys_read fs/read_write.c:630 [inline]
__se_sys_read fs/read_write.c:628 [inline]
__x64_sys_read+0x3e/0x50 fs/read_write.c:628
do_syscall_x64 arch/x86/entry/common.c:50 [inline]
do_syscall_64+0x2b/0x70 arch/x86/entry/common.c:80
entry_SYSCALL_64_after_hwframe+0x46/0xb0

value changed: 0x00 -> 0x01

Reported by Kernel Concurrency Sanitizer on:
CPU: 1 PID: 20423 Comm: udevd Tainted: G W 5.19.0-rc2-syzkaller-dirty #0
Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011

Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Signed-off-by: Eric Dumazet <edumazet@google.com>
Reported-by: syzbot <syzkaller@googlegroups.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/core/dev.c       | 25 +++++++++++++++----------
 net/core/net-sysfs.c |  1 +
 2 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/net/core/dev.c b/net/core/dev.c
index 08ce317fcec89..8e6f229612066 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -397,16 +397,18 @@ static void list_netdevice(struct net_device *dev)
 /* Device list removal
  * caller must respect a RCU grace period before freeing/reusing dev
  */
-static void unlist_netdevice(struct net_device *dev)
+static void unlist_netdevice(struct net_device *dev, bool lock)
 {
 	ASSERT_RTNL();
 
 	/* Unlink dev from the device chain */
-	write_lock(&dev_base_lock);
+	if (lock)
+		write_lock(&dev_base_lock);
 	list_del_rcu(&dev->dev_list);
 	netdev_name_node_del(dev->name_node);
 	hlist_del_rcu(&dev->index_hlist);
-	write_unlock(&dev_base_lock);
+	if (lock)
+		write_unlock(&dev_base_lock);
 
 	dev_base_seq_inc(dev_net(dev));
 }
@@ -10043,11 +10045,11 @@ int register_netdevice(struct net_device *dev)
 		goto err_uninit;
 
 	ret = netdev_register_kobject(dev);
-	if (ret) {
-		dev->reg_state = NETREG_UNREGISTERED;
+	write_lock(&dev_base_lock);
+	dev->reg_state = ret ? NETREG_UNREGISTERED : NETREG_REGISTERED;
+	write_unlock(&dev_base_lock);
+	if (ret)
 		goto err_uninit;
-	}
-	dev->reg_state = NETREG_REGISTERED;
 
 	__netdev_update_features(dev);
 
@@ -10329,7 +10331,9 @@ void netdev_run_todo(void)
 			continue;
 		}
 
+		write_lock(&dev_base_lock);
 		dev->reg_state = NETREG_UNREGISTERED;
+		write_unlock(&dev_base_lock);
 		linkwatch_forget_dev(dev);
 	}
 
@@ -10810,9 +10814,10 @@ void unregister_netdevice_many(struct list_head *head)
 
 	list_for_each_entry(dev, head, unreg_list) {
 		/* And unlink it from device chain. */
-		unlist_netdevice(dev);
-
+		write_lock(&dev_base_lock);
+		unlist_netdevice(dev, false);
 		dev->reg_state = NETREG_UNREGISTERING;
+		write_unlock(&dev_base_lock);
 	}
 	flush_all_backlogs();
 
@@ -10959,7 +10964,7 @@ int __dev_change_net_namespace(struct net_device *dev, struct net *net,
 	dev_close(dev);
 
 	/* And unlink it from device chain */
-	unlist_netdevice(dev);
+	unlist_netdevice(dev, true);
 
 	synchronize_net();
 
diff --git a/net/core/net-sysfs.c b/net/core/net-sysfs.c
index e319e242dddf0..a3642569fe535 100644
--- a/net/core/net-sysfs.c
+++ b/net/core/net-sysfs.c
@@ -33,6 +33,7 @@ static const char fmt_dec[] = "%d\n";
 static const char fmt_ulong[] = "%lu\n";
 static const char fmt_u64[] = "%llu\n";
 
+/* Caller holds RTNL or dev_base_lock */
 static inline int dev_isalive(const struct net_device *dev)
 {
 	return dev->reg_state <= NETREG_REGISTERED;
-- 
GitLab


From e66e257a5d8368d9c0ba13d4630f474436533e8b Mon Sep 17 00:00:00 2001
From: Jay Vosburgh <jay.vosburgh@canonical.com>
Date: Thu, 16 Jun 2022 12:26:30 -0700
Subject: [PATCH 0751/1731] veth: Add updating of trans_start

Since commit 21a75f0915dd ("bonding: Fix ARP monitor validation"),
the bonding ARP / ND link monitors depend on the trans_start time to
determine link availability.  NETIF_F_LLTX drivers must update trans_start
directly, which veth does not do.  This prevents use of the ARP or ND link
monitors with veth interfaces in a bond.

	Resolve this by having veth_xmit update the trans_start time.

Reported-by: Jonathan Toppins <jtoppins@redhat.com>
Tested-by: Jonathan Toppins <jtoppins@redhat.com>
Signed-off-by: Jay Vosburgh <jay.vosburgh@canonical.com>
Fixes: 21a75f0915dd ("bonding: Fix ARP monitor validation")
Link: https://lore.kernel.org/netdev/b2fd4147-8f50-bebd-963a-1a3e8d1d9715@redhat.com/
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/veth.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/veth.c b/drivers/net/veth.c
index 466da01ba2e3e..2cb833b3006a7 100644
--- a/drivers/net/veth.c
+++ b/drivers/net/veth.c
@@ -312,6 +312,7 @@ static bool veth_skb_is_eligible_for_gro(const struct net_device *dev,
 static netdev_tx_t veth_xmit(struct sk_buff *skb, struct net_device *dev)
 {
 	struct veth_priv *rcv_priv, *priv = netdev_priv(dev);
+	struct netdev_queue *queue = NULL;
 	struct veth_rq *rq = NULL;
 	struct net_device *rcv;
 	int length = skb->len;
@@ -329,6 +330,7 @@ static netdev_tx_t veth_xmit(struct sk_buff *skb, struct net_device *dev)
 	rxq = skb_get_queue_mapping(skb);
 	if (rxq < rcv->real_num_rx_queues) {
 		rq = &rcv_priv->rq[rxq];
+		queue = netdev_get_tx_queue(dev, rxq);
 
 		/* The napi pointer is available when an XDP program is
 		 * attached or when GRO is enabled
@@ -340,6 +342,8 @@ static netdev_tx_t veth_xmit(struct sk_buff *skb, struct net_device *dev)
 
 	skb_tx_timestamp(skb);
 	if (likely(veth_forward_skb(rcv, skb, rq, use_napi) == NET_RX_SUCCESS)) {
+		if (queue)
+			txq_trans_cond_update(queue);
 		if (!use_napi)
 			dev_lstats_add(dev, length);
 	} else {
-- 
GitLab


From 911600bf5a5e84bfda4d33ee32acc75ecf6159f0 Mon Sep 17 00:00:00 2001
From: Hoang Le <hoang.h.le@dektech.com.au>
Date: Fri, 17 Jun 2022 08:45:51 +0700
Subject: [PATCH 0752/1731] tipc: fix use-after-free Read in tipc_named_reinit

syzbot found the following issue on:
==================================================================
BUG: KASAN: use-after-free in tipc_named_reinit+0x94f/0x9b0
net/tipc/name_distr.c:413
Read of size 8 at addr ffff88805299a000 by task kworker/1:9/23764

CPU: 1 PID: 23764 Comm: kworker/1:9 Not tainted
5.18.0-rc4-syzkaller-00878-g17d49e6e8012 #0
Hardware name: Google Compute Engine/Google Compute Engine,
BIOS Google 01/01/2011
Workqueue: events tipc_net_finalize_work
Call Trace:
 <TASK>
 __dump_stack lib/dump_stack.c:88 [inline]
 dump_stack_lvl+0xcd/0x134 lib/dump_stack.c:106
 print_address_description.constprop.0.cold+0xeb/0x495
mm/kasan/report.c:313
 print_report mm/kasan/report.c:429 [inline]
 kasan_report.cold+0xf4/0x1c6 mm/kasan/report.c:491
 tipc_named_reinit+0x94f/0x9b0 net/tipc/name_distr.c:413
 tipc_net_finalize+0x234/0x3d0 net/tipc/net.c:138
 process_one_work+0x996/0x1610 kernel/workqueue.c:2289
 worker_thread+0x665/0x1080 kernel/workqueue.c:2436
 kthread+0x2e9/0x3a0 kernel/kthread.c:376
 ret_from_fork+0x1f/0x30 arch/x86/entry/entry_64.S:298
 </TASK>
[...]
==================================================================

In the commit
d966ddcc3821 ("tipc: fix a deadlock when flushing scheduled work"),
the cancel_work_sync() function just to make sure ONLY the work
tipc_net_finalize_work() is executing/pending on any CPU completed before
tipc namespace is destroyed through tipc_exit_net(). But this function
is not guaranteed the work is the last queued. So, the destroyed instance
may be accessed in the work which will try to enqueue later.

In order to completely fix, we re-order the calling of cancel_work_sync()
to make sure the work tipc_net_finalize_work() was last queued and it
must be completed by calling cancel_work_sync().

Reported-by: syzbot+47af19f3307fc9c5c82e@syzkaller.appspotmail.com
Fixes: d966ddcc3821 ("tipc: fix a deadlock when flushing scheduled work")
Acked-by: Jon Maloy <jmaloy@redhat.com>
Signed-off-by: Ying Xue <ying.xue@windriver.com>
Signed-off-by: Hoang Le <hoang.h.le@dektech.com.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/tipc/core.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/net/tipc/core.c b/net/tipc/core.c
index 3f4542e0f0650..434e70eabe081 100644
--- a/net/tipc/core.c
+++ b/net/tipc/core.c
@@ -109,10 +109,9 @@ static void __net_exit tipc_exit_net(struct net *net)
 	struct tipc_net *tn = tipc_net(net);
 
 	tipc_detach_loopback(net);
+	tipc_net_stop(net);
 	/* Make sure the tipc_net_finalize_work() finished */
 	cancel_work_sync(&tn->work);
-	tipc_net_stop(net);
-
 	tipc_bcast_stop(net);
 	tipc_nametbl_stop(net);
 	tipc_sk_rht_destroy(net);
-- 
GitLab


From 2b04495e21cdb9b45c28c6aeb2da560184de20a3 Mon Sep 17 00:00:00 2001
From: Xu Jia <xujia39@huawei.com>
Date: Fri, 17 Jun 2022 17:31:06 +0800
Subject: [PATCH 0753/1731] hamradio: 6pack: fix array-index-out-of-bounds in
 decode_std_command()

Hulk Robot reports incorrect sp->rx_count_cooked value in decode_std_command().
This should be caused by the subtracting from sp->rx_count_cooked before.
It seems that sp->rx_count_cooked value is changed to 0, which bypassed the
previous judgment.

The situation is shown below:

         (Thread 1)			|  (Thread 2)
decode_std_command()		| resync_tnc()
...					|
if (rest == 2)			|
	sp->rx_count_cooked -= 2;	|
else if (rest == 3)			| ...
					| sp->rx_count_cooked = 0;
	sp->rx_count_cooked -= 1;	|
for (i = 0; i < sp->rx_count_cooked; i++) // report error
	checksum += sp->cooked_buf[i];

sp->rx_count_cooked is a shared variable but is not protected by a lock.
The same applies to sp->rx_count. This patch adds a lock to fix the bug.

The fail log is shown below:
=======================================================================
UBSAN: array-index-out-of-bounds in drivers/net/hamradio/6pack.c:925:31
index 400 is out of range for type 'unsigned char [400]'
CPU: 3 PID: 7433 Comm: kworker/u10:1 Not tainted 5.18.0-rc5-00163-g4b97bac0756a #2
Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org 04/01/2014
Workqueue: events_unbound flush_to_ldisc
Call Trace:
 <TASK>
 dump_stack_lvl+0xcd/0x134
 ubsan_epilogue+0xb/0x50
 __ubsan_handle_out_of_bounds.cold+0x62/0x6c
 sixpack_receive_buf+0xfda/0x1330
 tty_ldisc_receive_buf+0x13e/0x180
 tty_port_default_receive_buf+0x6d/0xa0
 flush_to_ldisc+0x213/0x3f0
 process_one_work+0x98f/0x1620
 worker_thread+0x665/0x1080
 kthread+0x2e9/0x3a0
 ret_from_fork+0x1f/0x30
 ...

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Xu Jia <xujia39@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/hamradio/6pack.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/net/hamradio/6pack.c b/drivers/net/hamradio/6pack.c
index 45c3c4a1101b7..9fb5675242207 100644
--- a/drivers/net/hamradio/6pack.c
+++ b/drivers/net/hamradio/6pack.c
@@ -99,6 +99,7 @@ struct sixpack {
 
 	unsigned int		rx_count;
 	unsigned int		rx_count_cooked;
+	spinlock_t		rxlock;
 
 	int			mtu;		/* Our mtu (to spot changes!) */
 	int			buffsize;       /* Max buffers sizes */
@@ -565,6 +566,7 @@ static int sixpack_open(struct tty_struct *tty)
 	sp->dev = dev;
 
 	spin_lock_init(&sp->lock);
+	spin_lock_init(&sp->rxlock);
 	refcount_set(&sp->refcnt, 1);
 	init_completion(&sp->dead);
 
@@ -913,6 +915,7 @@ static void decode_std_command(struct sixpack *sp, unsigned char cmd)
 			sp->led_state = 0x60;
 			/* fill trailing bytes with zeroes */
 			sp->tty->ops->write(sp->tty, &sp->led_state, 1);
+			spin_lock_bh(&sp->rxlock);
 			rest = sp->rx_count;
 			if (rest != 0)
 				 for (i = rest; i <= 3; i++)
@@ -930,6 +933,7 @@ static void decode_std_command(struct sixpack *sp, unsigned char cmd)
 				sp_bump(sp, 0);
 			}
 			sp->rx_count_cooked = 0;
+			spin_unlock_bh(&sp->rxlock);
 		}
 		break;
 	case SIXP_TX_URUN: printk(KERN_DEBUG "6pack: TX underrun\n");
@@ -959,8 +963,11 @@ sixpack_decode(struct sixpack *sp, const unsigned char *pre_rbuff, int count)
 			decode_prio_command(sp, inbyte);
 		else if ((inbyte & SIXP_STD_CMD_MASK) != 0)
 			decode_std_command(sp, inbyte);
-		else if ((sp->status & SIXP_RX_DCD_MASK) == SIXP_RX_DCD_MASK)
+		else if ((sp->status & SIXP_RX_DCD_MASK) == SIXP_RX_DCD_MASK) {
+			spin_lock_bh(&sp->rxlock);
 			decode_data(sp, inbyte);
+			spin_unlock_bh(&sp->rxlock);
+		}
 	}
 }
 
-- 
GitLab


From b4a028c4d031c27704ad73b1195ca69a1206941e Mon Sep 17 00:00:00 2001
From: Riccardo Paolo Bestetti <pbl@bestov.io>
Date: Fri, 17 Jun 2022 10:54:35 +0200
Subject: [PATCH 0754/1731] ipv4: ping: fix bind address validity check
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Commit 8ff978b8b222 ("ipv4/raw: support binding to nonlocal addresses")
introduced a helper function to fold duplicated validity checks of bind
addresses into inet_addr_valid_or_nonlocal(). However, this caused an
unintended regression in ping_check_bind_addr(), which previously would
reject binding to multicast and broadcast addresses, but now these are
both incorrectly allowed as reported in [1].

This patch restores the original check. A simple reordering is done to
improve readability and make it evident that multicast and broadcast
addresses should not be allowed. Also, add an early exit for INADDR_ANY
which replaces lost behavior added by commit 0ce779a9f501 ("net: Avoid
unnecessary inet_addr_type() call when addr is INADDR_ANY").

Furthermore, this patch introduces regression selftests to catch these
specific cases.

[1] https://lore.kernel.org/netdev/CANP3RGdkAcDyAZoT1h8Gtuu0saq+eOrrTiWbxnOs+5zn+cpyKg@mail.gmail.com/

Fixes: 8ff978b8b222 ("ipv4/raw: support binding to nonlocal addresses")
Cc: Miaohe Lin <linmiaohe@huawei.com>
Reported-by: Maciej Żenczykowski <maze@google.com>
Signed-off-by: Carlos Llamas <cmllamas@google.com>
Signed-off-by: Riccardo Paolo Bestetti <pbl@bestov.io>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/ipv4/ping.c                           | 10 ++++---
 tools/testing/selftests/net/fcnal-test.sh | 33 +++++++++++++++++++++++
 2 files changed, 40 insertions(+), 3 deletions(-)

diff --git a/net/ipv4/ping.c b/net/ipv4/ping.c
index 1a43ca73f94d6..3c6101def7d6b 100644
--- a/net/ipv4/ping.c
+++ b/net/ipv4/ping.c
@@ -319,12 +319,16 @@ static int ping_check_bind_addr(struct sock *sk, struct inet_sock *isk,
 		pr_debug("ping_check_bind_addr(sk=%p,addr=%pI4,port=%d)\n",
 			 sk, &addr->sin_addr.s_addr, ntohs(addr->sin_port));
 
+		if (addr->sin_addr.s_addr == htonl(INADDR_ANY))
+			return 0;
+
 		tb_id = l3mdev_fib_table_by_index(net, sk->sk_bound_dev_if) ? : tb_id;
 		chk_addr_ret = inet_addr_type_table(net, addr->sin_addr.s_addr, tb_id);
 
-		if (!inet_addr_valid_or_nonlocal(net, inet_sk(sk),
-					         addr->sin_addr.s_addr,
-	                                         chk_addr_ret))
+		if (chk_addr_ret == RTN_MULTICAST ||
+		    chk_addr_ret == RTN_BROADCAST ||
+		    (chk_addr_ret != RTN_LOCAL &&
+		     !inet_can_nonlocal_bind(net, isk)))
 			return -EADDRNOTAVAIL;
 
 #if IS_ENABLED(CONFIG_IPV6)
diff --git a/tools/testing/selftests/net/fcnal-test.sh b/tools/testing/selftests/net/fcnal-test.sh
index 54701c8b0cd70..75223b63e3c88 100755
--- a/tools/testing/selftests/net/fcnal-test.sh
+++ b/tools/testing/selftests/net/fcnal-test.sh
@@ -70,6 +70,10 @@ NSB_LO_IP6=2001:db8:2::2
 NL_IP=172.17.1.1
 NL_IP6=2001:db8:4::1
 
+# multicast and broadcast addresses
+MCAST_IP=224.0.0.1
+BCAST_IP=255.255.255.255
+
 MD5_PW=abc123
 MD5_WRONG_PW=abc1234
 
@@ -308,6 +312,9 @@ addr2str()
 	127.0.0.1) echo "loopback";;
 	::1) echo "IPv6 loopback";;
 
+	${BCAST_IP}) echo "broadcast";;
+	${MCAST_IP}) echo "multicast";;
+
 	${NSA_IP})	echo "ns-A IP";;
 	${NSA_IP6})	echo "ns-A IPv6";;
 	${NSA_LO_IP})	echo "ns-A loopback IP";;
@@ -1800,6 +1807,19 @@ ipv4_addr_bind_novrf()
 	run_cmd nettest -s -R -P icmp -f -l ${a} -I ${NSA_DEV} -b
 	log_test_addr ${a} $? 0 "Raw socket bind to nonlocal address after device bind"
 
+	#
+	# check that ICMP sockets cannot bind to broadcast and multicast addresses
+	#
+	a=${BCAST_IP}
+	log_start
+	run_cmd nettest -s -R -P icmp -l ${a} -b
+	log_test_addr ${a} $? 1 "ICMP socket bind to broadcast address"
+
+	a=${MCAST_IP}
+	log_start
+	run_cmd nettest -s -R -P icmp -f -l ${a} -b
+	log_test_addr ${a} $? 1 "ICMP socket bind to multicast address"
+
 	#
 	# tcp sockets
 	#
@@ -1857,6 +1877,19 @@ ipv4_addr_bind_vrf()
 	run_cmd nettest -s -R -P icmp -f -l ${a} -I ${VRF} -b
 	log_test_addr ${a} $? 0 "Raw socket bind to nonlocal address after VRF bind"
 
+	#
+	# check that ICMP sockets cannot bind to broadcast and multicast addresses
+	#
+	a=${BCAST_IP}
+	log_start
+	run_cmd nettest -s -R -P icmp -l ${a} -I ${VRF} -b
+	log_test_addr ${a} $? 1 "ICMP socket bind to broadcast address after VRF bind"
+
+	a=${MCAST_IP}
+	log_start
+	run_cmd nettest -s -R -P icmp -f -l ${a} -I ${VRF} -b
+	log_test_addr ${a} $? 1 "ICMP socket bind to multicast address after VRF bind"
+
 	#
 	# tcp sockets
 	#
-- 
GitLab


From 6436c770f120a9ffeb4e791650467f30f1d062d1 Mon Sep 17 00:00:00 2001
From: Jens Axboe <axboe@kernel.dk>
Date: Fri, 17 Jun 2022 06:24:26 -0600
Subject: [PATCH 0755/1731] io_uring: recycle provided buffer if we punt to
 io-wq

io_arm_poll_handler() will recycle the buffer appropriately if we end
up arming poll (or if we're ready to retry), but not for the io-wq case
if we have attempted poll first.

Explicitly recycle the buffer to avoid both hanging on to it too long,
but also to avoid multiple reads grabbing the same one. This can happen
for ring mapped buffers, since it hasn't necessarily been committed.

Fixes: c7fb19428d67 ("io_uring: add support for ring mapped supplied buffers")
Link: https://github.com/axboe/liburing/issues/605
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index 95a1a78d799a1..d3ee4fc532faf 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -8690,6 +8690,7 @@ static void io_queue_async(struct io_kiocb *req, int ret)
 		 * Queued up for async execution, worker will release
 		 * submit reference when the iocb is actually submitted.
 		 */
+		io_kbuf_recycle(req, 0);
 		io_queue_iowq(req, NULL);
 		break;
 	case IO_APOLL_OK:
-- 
GitLab


From e83031564137cf37e07c2d10ad468046ff48a0cf Mon Sep 17 00:00:00 2001
From: Nathan Chancellor <nathan@kernel.org>
Date: Wed, 18 May 2022 11:45:29 -0700
Subject: [PATCH 0756/1731] riscv: Fix ALT_THEAD_PMA's asm parameters

After commit a35707c3d850 ("riscv: add memory-type errata for T-Head"),
builds with LLVM's integrated assembler fail like:

  In file included from arch/riscv/kernel/asm-offsets.c:10:
  In file included from ./include/linux/mm.h:29:
  In file included from ./include/linux/pgtable.h:6:
  In file included from ./arch/riscv/include/asm/pgtable.h:114:
  ./arch/riscv/include/asm/pgtable-64.h:210:2: error: invalid input constraint '0' in asm
          ALT_THEAD_PMA(prot_val);
          ^
  ./arch/riscv/include/asm/errata_list.h:88:4: note: expanded from macro 'ALT_THEAD_PMA'
          : "0"(_val),                                                    \
            ^

This was reported upstream to LLVM where Jessica pointed out a couple of
issues with the existing implementation of ALT_THEAD_PMA:

* t3 is modified but not listed in the clobbers list.

* "+r"(_val) marks _val as both an input and output of the asm but then
  "0"(_val) marks _val as an input matching constraint, which does not
  make much sense in this situation, as %1 is not actually used in the
  asm and matching constraints are designed to be used for different
  inputs that need to use the same register.

Drop the matching contraint and shift all the operands by one, as %1 is
unused, and mark t3 as clobbered. This resolves the build error and goes
not cause any problems with GNU as.

Fixes: a35707c3d850 ("riscv: add memory-type errata for T-Head")
Link: https://github.com/ClangBuiltLinux/linux/issues/1641
Link: https://github.com/llvm/llvm-project/issues/55514
Link: https://gcc.gnu.org/onlinedocs/gcc/Simple-Constraints.html
Suggested-by: Jessica Clarke <jrtc27@jrtc27.com>
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20220518184529.454008-1-nathan@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 arch/riscv/include/asm/errata_list.h | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 9e2888dbb5b13..416ead0f9a655 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -75,20 +75,20 @@ asm volatile(ALTERNATIVE(						\
 	"nop\n\t"							\
 	"nop\n\t"							\
 	"nop",								\
-	"li      t3, %2\n\t"						\
-	"slli    t3, t3, %4\n\t"					\
+	"li      t3, %1\n\t"						\
+	"slli    t3, t3, %3\n\t"					\
 	"and     t3, %0, t3\n\t"					\
 	"bne     t3, zero, 2f\n\t"					\
-	"li      t3, %3\n\t"						\
-	"slli    t3, t3, %4\n\t"					\
+	"li      t3, %2\n\t"						\
+	"slli    t3, t3, %3\n\t"					\
 	"or      %0, %0, t3\n\t"					\
 	"2:",  THEAD_VENDOR_ID,						\
 		ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT)		\
 	: "+r"(_val)							\
-	: "0"(_val),							\
-	  "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT),		\
+	: "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT),		\
 	  "I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT),			\
-	  "I"(ALT_THEAD_PBMT_SHIFT))
+	  "I"(ALT_THEAD_PBMT_SHIFT)					\
+	: "t3")
 #else
 #define ALT_THEAD_PMA(_val)
 #endif
-- 
GitLab


From 50e34d78815e474d410f342fbe783b18192ca518 Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Tue, 14 Jun 2022 09:48:24 +0200
Subject: [PATCH 0757/1731] block: disable the elevator int del_gendisk

The elevator is only used for file system requests, which are stopped in
del_gendisk.  Move disabling the elevator and freeing the scheduler tags
to the end of del_gendisk instead of doing that work in disk_release and
blk_cleanup_queue to avoid a use after free on q->tag_set from
disk_release as the tag_set might not be alive at that point.

Move the blk_qos_exit call as well, as it just depends on the elevator
exit and would be the only reason to keep the not exactly cheap queue
freeze in disk_release.

Fixes: e155b0c238b2 ("blk-mq: Use shared tags for shared sbitmap support")
Reported-by: syzbot+3e3f419f4a7816471838@syzkaller.appspotmail.com
Signed-off-by: Christoph Hellwig <hch@lst.de>
Tested-by: syzbot+3e3f419f4a7816471838@syzkaller.appspotmail.com
Link: https://lore.kernel.org/r/20220614074827.458955-2-hch@lst.de
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 block/blk-core.c | 13 -------------
 block/genhd.c    | 39 +++++++++++----------------------------
 2 files changed, 11 insertions(+), 41 deletions(-)

diff --git a/block/blk-core.c b/block/blk-core.c
index 06ff5bbfe8f66..27fb1357ad4b8 100644
--- a/block/blk-core.c
+++ b/block/blk-core.c
@@ -322,19 +322,6 @@ void blk_cleanup_queue(struct request_queue *q)
 		blk_mq_exit_queue(q);
 	}
 
-	/*
-	 * In theory, request pool of sched_tags belongs to request queue.
-	 * However, the current implementation requires tag_set for freeing
-	 * requests, so free the pool now.
-	 *
-	 * Queue has become frozen, there can't be any in-queue requests, so
-	 * it is safe to free requests now.
-	 */
-	mutex_lock(&q->sysfs_lock);
-	if (q->elevator)
-		blk_mq_sched_free_rqs(q);
-	mutex_unlock(&q->sysfs_lock);
-
 	/* @q is and will stay empty, shutdown and put */
 	blk_put_queue(q);
 }
diff --git a/block/genhd.c b/block/genhd.c
index 27205ae47d593..e0675772178b0 100644
--- a/block/genhd.c
+++ b/block/genhd.c
@@ -652,6 +652,17 @@ void del_gendisk(struct gendisk *disk)
 
 	blk_sync_queue(q);
 	blk_flush_integrity();
+	blk_mq_cancel_work_sync(q);
+
+	blk_mq_quiesce_queue(q);
+	if (q->elevator) {
+		mutex_lock(&q->sysfs_lock);
+		elevator_exit(q);
+		mutex_unlock(&q->sysfs_lock);
+	}
+	rq_qos_exit(q);
+	blk_mq_unquiesce_queue(q);
+
 	/*
 	 * Allow using passthrough request again after the queue is torn down.
 	 */
@@ -1120,31 +1131,6 @@ static const struct attribute_group *disk_attr_groups[] = {
 	NULL
 };
 
-static void disk_release_mq(struct request_queue *q)
-{
-	blk_mq_cancel_work_sync(q);
-
-	/*
-	 * There can't be any non non-passthrough bios in flight here, but
-	 * requests stay around longer, including passthrough ones so we
-	 * still need to freeze the queue here.
-	 */
-	blk_mq_freeze_queue(q);
-
-	/*
-	 * Since the I/O scheduler exit code may access cgroup information,
-	 * perform I/O scheduler exit before disassociating from the block
-	 * cgroup controller.
-	 */
-	if (q->elevator) {
-		mutex_lock(&q->sysfs_lock);
-		elevator_exit(q);
-		mutex_unlock(&q->sysfs_lock);
-	}
-	rq_qos_exit(q);
-	__blk_mq_unfreeze_queue(q, true);
-}
-
 /**
  * disk_release - releases all allocated resources of the gendisk
  * @dev: the device representing this disk
@@ -1166,9 +1152,6 @@ static void disk_release(struct device *dev)
 	might_sleep();
 	WARN_ON_ONCE(disk_live(disk));
 
-	if (queue_is_mq(disk->queue))
-		disk_release_mq(disk->queue);
-
 	blkcg_exit_queue(disk->queue);
 
 	disk_release_events(disk);
-- 
GitLab


From 5cf9c91ba927119fc6606b938b1895bb2459d3bc Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Tue, 14 Jun 2022 09:48:25 +0200
Subject: [PATCH 0758/1731] block: serialize all debugfs operations using
 q->debugfs_mutex

Various places like I/O schedulers or the QOS infrastructure try to
register debugfs files on demans, which can race with creating and
removing the main queue debugfs directory.  Use the existing
debugfs_mutex to serialize all debugfs operations that rely on
q->debugfs_dir or the directories hanging off it.

To make the teardown code a little simpler declare all debugfs dentry
pointers and not just the main one uncoditionally in blkdev.h.

Move debugfs_mutex next to the dentries that it protects and document
what it is used for.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Link: https://lore.kernel.org/r/20220614074827.458955-3-hch@lst.de
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 block/blk-mq-debugfs.c  | 25 ++++++++++++++++++++-----
 block/blk-mq-debugfs.h  |  5 -----
 block/blk-mq-sched.c    | 11 +++++++++++
 block/blk-rq-qos.c      |  2 ++
 block/blk-rq-qos.h      |  7 ++++++-
 block/blk-sysfs.c       | 20 +++++++++-----------
 include/linux/blkdev.h  |  8 ++++----
 kernel/trace/blktrace.c |  3 ---
 8 files changed, 52 insertions(+), 29 deletions(-)

diff --git a/block/blk-mq-debugfs.c b/block/blk-mq-debugfs.c
index 7e4136a60e1cc..f0fcfe1387cbc 100644
--- a/block/blk-mq-debugfs.c
+++ b/block/blk-mq-debugfs.c
@@ -711,11 +711,6 @@ void blk_mq_debugfs_register(struct request_queue *q)
 	}
 }
 
-void blk_mq_debugfs_unregister(struct request_queue *q)
-{
-	q->sched_debugfs_dir = NULL;
-}
-
 static void blk_mq_debugfs_register_ctx(struct blk_mq_hw_ctx *hctx,
 					struct blk_mq_ctx *ctx)
 {
@@ -746,6 +741,8 @@ void blk_mq_debugfs_register_hctx(struct request_queue *q,
 
 void blk_mq_debugfs_unregister_hctx(struct blk_mq_hw_ctx *hctx)
 {
+	if (!hctx->queue->debugfs_dir)
+		return;
 	debugfs_remove_recursive(hctx->debugfs_dir);
 	hctx->sched_debugfs_dir = NULL;
 	hctx->debugfs_dir = NULL;
@@ -773,6 +770,8 @@ void blk_mq_debugfs_register_sched(struct request_queue *q)
 {
 	struct elevator_type *e = q->elevator->type;
 
+	lockdep_assert_held(&q->debugfs_mutex);
+
 	/*
 	 * If the parent directory has not been created yet, return, we will be
 	 * called again later on and the directory/files will be created then.
@@ -790,6 +789,8 @@ void blk_mq_debugfs_register_sched(struct request_queue *q)
 
 void blk_mq_debugfs_unregister_sched(struct request_queue *q)
 {
+	lockdep_assert_held(&q->debugfs_mutex);
+
 	debugfs_remove_recursive(q->sched_debugfs_dir);
 	q->sched_debugfs_dir = NULL;
 }
@@ -811,6 +812,10 @@ static const char *rq_qos_id_to_name(enum rq_qos_id id)
 
 void blk_mq_debugfs_unregister_rqos(struct rq_qos *rqos)
 {
+	lockdep_assert_held(&rqos->q->debugfs_mutex);
+
+	if (!rqos->q->debugfs_dir)
+		return;
 	debugfs_remove_recursive(rqos->debugfs_dir);
 	rqos->debugfs_dir = NULL;
 }
@@ -820,6 +825,8 @@ void blk_mq_debugfs_register_rqos(struct rq_qos *rqos)
 	struct request_queue *q = rqos->q;
 	const char *dir_name = rq_qos_id_to_name(rqos->id);
 
+	lockdep_assert_held(&q->debugfs_mutex);
+
 	if (rqos->debugfs_dir || !rqos->ops->debugfs_attrs)
 		return;
 
@@ -835,6 +842,8 @@ void blk_mq_debugfs_register_rqos(struct rq_qos *rqos)
 
 void blk_mq_debugfs_unregister_queue_rqos(struct request_queue *q)
 {
+	lockdep_assert_held(&q->debugfs_mutex);
+
 	debugfs_remove_recursive(q->rqos_debugfs_dir);
 	q->rqos_debugfs_dir = NULL;
 }
@@ -844,6 +853,8 @@ void blk_mq_debugfs_register_sched_hctx(struct request_queue *q,
 {
 	struct elevator_type *e = q->elevator->type;
 
+	lockdep_assert_held(&q->debugfs_mutex);
+
 	/*
 	 * If the parent debugfs directory has not been created yet, return;
 	 * We will be called again later on with appropriate parent debugfs
@@ -863,6 +874,10 @@ void blk_mq_debugfs_register_sched_hctx(struct request_queue *q,
 
 void blk_mq_debugfs_unregister_sched_hctx(struct blk_mq_hw_ctx *hctx)
 {
+	lockdep_assert_held(&hctx->queue->debugfs_mutex);
+
+	if (!hctx->queue->debugfs_dir)
+		return;
 	debugfs_remove_recursive(hctx->sched_debugfs_dir);
 	hctx->sched_debugfs_dir = NULL;
 }
diff --git a/block/blk-mq-debugfs.h b/block/blk-mq-debugfs.h
index 69918f4170d69..771d458328788 100644
--- a/block/blk-mq-debugfs.h
+++ b/block/blk-mq-debugfs.h
@@ -21,7 +21,6 @@ int __blk_mq_debugfs_rq_show(struct seq_file *m, struct request *rq);
 int blk_mq_debugfs_rq_show(struct seq_file *m, void *v);
 
 void blk_mq_debugfs_register(struct request_queue *q);
-void blk_mq_debugfs_unregister(struct request_queue *q);
 void blk_mq_debugfs_register_hctx(struct request_queue *q,
 				  struct blk_mq_hw_ctx *hctx);
 void blk_mq_debugfs_unregister_hctx(struct blk_mq_hw_ctx *hctx);
@@ -42,10 +41,6 @@ static inline void blk_mq_debugfs_register(struct request_queue *q)
 {
 }
 
-static inline void blk_mq_debugfs_unregister(struct request_queue *q)
-{
-}
-
 static inline void blk_mq_debugfs_register_hctx(struct request_queue *q,
 						struct blk_mq_hw_ctx *hctx)
 {
diff --git a/block/blk-mq-sched.c b/block/blk-mq-sched.c
index eb3c65a213625..a4f7c101b53b2 100644
--- a/block/blk-mq-sched.c
+++ b/block/blk-mq-sched.c
@@ -594,7 +594,9 @@ int blk_mq_init_sched(struct request_queue *q, struct elevator_type *e)
 	if (ret)
 		goto err_free_map_and_rqs;
 
+	mutex_lock(&q->debugfs_mutex);
 	blk_mq_debugfs_register_sched(q);
+	mutex_unlock(&q->debugfs_mutex);
 
 	queue_for_each_hw_ctx(q, hctx, i) {
 		if (e->ops.init_hctx) {
@@ -607,7 +609,9 @@ int blk_mq_init_sched(struct request_queue *q, struct elevator_type *e)
 				return ret;
 			}
 		}
+		mutex_lock(&q->debugfs_mutex);
 		blk_mq_debugfs_register_sched_hctx(q, hctx);
+		mutex_unlock(&q->debugfs_mutex);
 	}
 
 	return 0;
@@ -648,14 +652,21 @@ void blk_mq_exit_sched(struct request_queue *q, struct elevator_queue *e)
 	unsigned int flags = 0;
 
 	queue_for_each_hw_ctx(q, hctx, i) {
+		mutex_lock(&q->debugfs_mutex);
 		blk_mq_debugfs_unregister_sched_hctx(hctx);
+		mutex_unlock(&q->debugfs_mutex);
+
 		if (e->type->ops.exit_hctx && hctx->sched_data) {
 			e->type->ops.exit_hctx(hctx, i);
 			hctx->sched_data = NULL;
 		}
 		flags = hctx->flags;
 	}
+
+	mutex_lock(&q->debugfs_mutex);
 	blk_mq_debugfs_unregister_sched(q);
+	mutex_unlock(&q->debugfs_mutex);
+
 	if (e->type->ops.exit_sched)
 		e->type->ops.exit_sched(e);
 	blk_mq_sched_tags_teardown(q, flags);
diff --git a/block/blk-rq-qos.c b/block/blk-rq-qos.c
index e83af7bc75919..249a6f05dd3bd 100644
--- a/block/blk-rq-qos.c
+++ b/block/blk-rq-qos.c
@@ -294,7 +294,9 @@ void rq_qos_wait(struct rq_wait *rqw, void *private_data,
 
 void rq_qos_exit(struct request_queue *q)
 {
+	mutex_lock(&q->debugfs_mutex);
 	blk_mq_debugfs_unregister_queue_rqos(q);
+	mutex_unlock(&q->debugfs_mutex);
 
 	while (q->rq_qos) {
 		struct rq_qos *rqos = q->rq_qos;
diff --git a/block/blk-rq-qos.h b/block/blk-rq-qos.h
index 68267007da1c6..0e46052b018a4 100644
--- a/block/blk-rq-qos.h
+++ b/block/blk-rq-qos.h
@@ -104,8 +104,11 @@ static inline void rq_qos_add(struct request_queue *q, struct rq_qos *rqos)
 
 	blk_mq_unfreeze_queue(q);
 
-	if (rqos->ops->debugfs_attrs)
+	if (rqos->ops->debugfs_attrs) {
+		mutex_lock(&q->debugfs_mutex);
 		blk_mq_debugfs_register_rqos(rqos);
+		mutex_unlock(&q->debugfs_mutex);
+	}
 }
 
 static inline void rq_qos_del(struct request_queue *q, struct rq_qos *rqos)
@@ -129,7 +132,9 @@ static inline void rq_qos_del(struct request_queue *q, struct rq_qos *rqos)
 
 	blk_mq_unfreeze_queue(q);
 
+	mutex_lock(&q->debugfs_mutex);
 	blk_mq_debugfs_unregister_rqos(rqos);
+	mutex_unlock(&q->debugfs_mutex);
 }
 
 typedef bool (acquire_inflight_cb_t)(struct rq_wait *rqw, void *private_data);
diff --git a/block/blk-sysfs.c b/block/blk-sysfs.c
index 88bd41d4cb593..6e4801b217a79 100644
--- a/block/blk-sysfs.c
+++ b/block/blk-sysfs.c
@@ -779,14 +779,13 @@ static void blk_release_queue(struct kobject *kobj)
 	if (queue_is_mq(q))
 		blk_mq_release(q);
 
-	blk_trace_shutdown(q);
 	mutex_lock(&q->debugfs_mutex);
+	blk_trace_shutdown(q);
 	debugfs_remove_recursive(q->debugfs_dir);
+	q->debugfs_dir = NULL;
+	q->sched_debugfs_dir = NULL;
 	mutex_unlock(&q->debugfs_mutex);
 
-	if (queue_is_mq(q))
-		blk_mq_debugfs_unregister(q);
-
 	bioset_exit(&q->bio_split);
 
 	if (blk_queue_has_srcu(q))
@@ -836,17 +835,16 @@ int blk_register_queue(struct gendisk *disk)
 		goto unlock;
 	}
 
+	if (queue_is_mq(q))
+		__blk_mq_register_dev(dev, q);
+	mutex_lock(&q->sysfs_lock);
+
 	mutex_lock(&q->debugfs_mutex);
 	q->debugfs_dir = debugfs_create_dir(kobject_name(q->kobj.parent),
 					    blk_debugfs_root);
-	mutex_unlock(&q->debugfs_mutex);
-
-	if (queue_is_mq(q)) {
-		__blk_mq_register_dev(dev, q);
+	if (queue_is_mq(q))
 		blk_mq_debugfs_register(q);
-	}
-
-	mutex_lock(&q->sysfs_lock);
+	mutex_unlock(&q->debugfs_mutex);
 
 	ret = disk_register_independent_access_ranges(disk, NULL);
 	if (ret)
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index bb6e3c31b3b7b..73c886eba8e19 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -482,7 +482,6 @@ struct request_queue {
 #endif /* CONFIG_BLK_DEV_ZONED */
 
 	int			node;
-	struct mutex		debugfs_mutex;
 #ifdef CONFIG_BLK_DEV_IO_TRACE
 	struct blk_trace __rcu	*blk_trace;
 #endif
@@ -526,11 +525,12 @@ struct request_queue {
 	struct bio_set		bio_split;
 
 	struct dentry		*debugfs_dir;
-
-#ifdef CONFIG_BLK_DEBUG_FS
 	struct dentry		*sched_debugfs_dir;
 	struct dentry		*rqos_debugfs_dir;
-#endif
+	/*
+	 * Serializes all debugfs metadata operations using the above dentries.
+	 */
+	struct mutex		debugfs_mutex;
 
 	bool			mq_sysfs_init_done;
 
diff --git a/kernel/trace/blktrace.c b/kernel/trace/blktrace.c
index 10a32b0f2deb6..fe04c6f96ca5d 100644
--- a/kernel/trace/blktrace.c
+++ b/kernel/trace/blktrace.c
@@ -770,14 +770,11 @@ int blk_trace_ioctl(struct block_device *bdev, unsigned cmd, char __user *arg)
  **/
 void blk_trace_shutdown(struct request_queue *q)
 {
-	mutex_lock(&q->debugfs_mutex);
 	if (rcu_dereference_protected(q->blk_trace,
 				      lockdep_is_held(&q->debugfs_mutex))) {
 		__blk_trace_startstop(q, 0);
 		__blk_trace_remove(q);
 	}
-
-	mutex_unlock(&q->debugfs_mutex);
 }
 
 #ifdef CONFIG_BLK_CGROUP
-- 
GitLab


From 99d055b4fd4bbb309c6cdb51a0d420669f777944 Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Tue, 14 Jun 2022 09:48:26 +0200
Subject: [PATCH 0759/1731] block: remove per-disk debugfs files in
 blk_unregister_queue

The block debugfs files are created in blk_register_queue, which is
called by add_disk and use a naming scheme based on the disk_name.
After del_gendisk returns that name can be reused and thus we must not
leave these debugfs files around, otherwise the kernel is unhappy
and spews messages like:

	Directory XXXXX with parent 'block' already present!

and the newly created devices will not have working debugfs files.

Move the unregistration to blk_unregister_queue instead (which matches
the sysfs unregistration) to make sure the debugfs life time rules match
those of the disk name.

As part of the move also make sure the whole debugfs unregistration is
inside a single debugfs_mutex critical section.

Note that this breaks blktests block/002, which checks that the debugfs
directory has not been removed while blktests is running, but that
particular check should simply be removed from the test case.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Link: https://lore.kernel.org/r/20220614074827.458955-4-hch@lst.de
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 block/blk-mq-debugfs.c |  8 --------
 block/blk-mq-debugfs.h |  5 -----
 block/blk-rq-qos.c     |  4 ----
 block/blk-sysfs.c      | 16 ++++++++--------
 4 files changed, 8 insertions(+), 25 deletions(-)

diff --git a/block/blk-mq-debugfs.c b/block/blk-mq-debugfs.c
index f0fcfe1387cbc..4d1ce9ef43187 100644
--- a/block/blk-mq-debugfs.c
+++ b/block/blk-mq-debugfs.c
@@ -840,14 +840,6 @@ void blk_mq_debugfs_register_rqos(struct rq_qos *rqos)
 	debugfs_create_files(rqos->debugfs_dir, rqos, rqos->ops->debugfs_attrs);
 }
 
-void blk_mq_debugfs_unregister_queue_rqos(struct request_queue *q)
-{
-	lockdep_assert_held(&q->debugfs_mutex);
-
-	debugfs_remove_recursive(q->rqos_debugfs_dir);
-	q->rqos_debugfs_dir = NULL;
-}
-
 void blk_mq_debugfs_register_sched_hctx(struct request_queue *q,
 					struct blk_mq_hw_ctx *hctx)
 {
diff --git a/block/blk-mq-debugfs.h b/block/blk-mq-debugfs.h
index 771d458328788..9c7d4b6117d41 100644
--- a/block/blk-mq-debugfs.h
+++ b/block/blk-mq-debugfs.h
@@ -35,7 +35,6 @@ void blk_mq_debugfs_unregister_sched_hctx(struct blk_mq_hw_ctx *hctx);
 
 void blk_mq_debugfs_register_rqos(struct rq_qos *rqos);
 void blk_mq_debugfs_unregister_rqos(struct rq_qos *rqos);
-void blk_mq_debugfs_unregister_queue_rqos(struct request_queue *q);
 #else
 static inline void blk_mq_debugfs_register(struct request_queue *q)
 {
@@ -82,10 +81,6 @@ static inline void blk_mq_debugfs_register_rqos(struct rq_qos *rqos)
 static inline void blk_mq_debugfs_unregister_rqos(struct rq_qos *rqos)
 {
 }
-
-static inline void blk_mq_debugfs_unregister_queue_rqos(struct request_queue *q)
-{
-}
 #endif
 
 #ifdef CONFIG_BLK_DEBUG_FS_ZONED
diff --git a/block/blk-rq-qos.c b/block/blk-rq-qos.c
index 249a6f05dd3bd..d3a75693adbf4 100644
--- a/block/blk-rq-qos.c
+++ b/block/blk-rq-qos.c
@@ -294,10 +294,6 @@ void rq_qos_wait(struct rq_wait *rqw, void *private_data,
 
 void rq_qos_exit(struct request_queue *q)
 {
-	mutex_lock(&q->debugfs_mutex);
-	blk_mq_debugfs_unregister_queue_rqos(q);
-	mutex_unlock(&q->debugfs_mutex);
-
 	while (q->rq_qos) {
 		struct rq_qos *rqos = q->rq_qos;
 		q->rq_qos = rqos->next;
diff --git a/block/blk-sysfs.c b/block/blk-sysfs.c
index 6e4801b217a79..9b905e9443e49 100644
--- a/block/blk-sysfs.c
+++ b/block/blk-sysfs.c
@@ -779,13 +779,6 @@ static void blk_release_queue(struct kobject *kobj)
 	if (queue_is_mq(q))
 		blk_mq_release(q);
 
-	mutex_lock(&q->debugfs_mutex);
-	blk_trace_shutdown(q);
-	debugfs_remove_recursive(q->debugfs_dir);
-	q->debugfs_dir = NULL;
-	q->sched_debugfs_dir = NULL;
-	mutex_unlock(&q->debugfs_mutex);
-
 	bioset_exit(&q->bio_split);
 
 	if (blk_queue_has_srcu(q))
@@ -946,8 +939,15 @@ void blk_unregister_queue(struct gendisk *disk)
 	/* Now that we've deleted all child objects, we can delete the queue. */
 	kobject_uevent(&q->kobj, KOBJ_REMOVE);
 	kobject_del(&q->kobj);
-
 	mutex_unlock(&q->sysfs_dir_lock);
 
+	mutex_lock(&q->debugfs_mutex);
+	blk_trace_shutdown(q);
+	debugfs_remove_recursive(q->debugfs_dir);
+	q->debugfs_dir = NULL;
+	q->sched_debugfs_dir = NULL;
+	q->rqos_debugfs_dir = NULL;
+	mutex_unlock(&q->debugfs_mutex);
+
 	kobject_put(&disk_to_dev(disk)->kobj);
 }
-- 
GitLab


From a09b314005f3a0956ebf56e01b3b80339df577cc Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Tue, 14 Jun 2022 09:48:27 +0200
Subject: [PATCH 0760/1731] block: freeze the queue earlier in del_gendisk

Freeze the queue earlier in del_gendisk so that the state does not
change while we remove debugfs and sysfs files.

Ming mentioned that being able to observer request in debugfs might
be useful while the queue is being frozen in del_gendisk, which is
made possible by this change.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Link: https://lore.kernel.org/r/20220614074827.458955-5-hch@lst.de
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 block/genhd.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/block/genhd.c b/block/genhd.c
index e0675772178b0..278227ba1d531 100644
--- a/block/genhd.c
+++ b/block/genhd.c
@@ -623,6 +623,7 @@ void del_gendisk(struct gendisk *disk)
 	 * Prevent new I/O from crossing bio_queue_enter().
 	 */
 	blk_queue_start_drain(q);
+	blk_mq_freeze_queue_wait(q);
 
 	if (!(disk->flags & GENHD_FL_HIDDEN)) {
 		sysfs_remove_link(&disk_to_dev(disk)->kobj, "bdi");
@@ -646,8 +647,6 @@ void del_gendisk(struct gendisk *disk)
 	pm_runtime_set_memalloc_noio(disk_to_dev(disk), false);
 	device_del(disk_to_dev(disk));
 
-	blk_mq_freeze_queue_wait(q);
-
 	blk_throtl_cancel_bios(disk->queue);
 
 	blk_sync_queue(q);
-- 
GitLab


From b672332ef9161f8cada005aaa9b333a19e496f07 Mon Sep 17 00:00:00 2001
From: Youling Tang <tangyouling@loongson.cn>
Date: Mon, 13 Jun 2022 18:54:12 +0800
Subject: [PATCH 0761/1731] LoongArch: vmlinux.lds.S: Add missing ELF_DETAILS

Commit c604abc3f6e ("vmlinux.lds.h: Split ELF_DETAILS from STABS_DEBUG")
splits ELF_DETAILS from STABS_DEBUG, resulting in missing ELF_DETAILS
information in LoongArch architecture, so add it.

Fixes: c604abc3f6e ("vmlinux.lds.h: Split ELF_DETAILS from STABS_DEBUG")
Signed-off-by: Youling Tang <tangyouling@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 arch/loongarch/kernel/vmlinux.lds.S | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/loongarch/kernel/vmlinux.lds.S b/arch/loongarch/kernel/vmlinux.lds.S
index 9d508158fe1a6..78311a6101a3e 100644
--- a/arch/loongarch/kernel/vmlinux.lds.S
+++ b/arch/loongarch/kernel/vmlinux.lds.S
@@ -101,6 +101,7 @@ SECTIONS
 
 	STABS_DEBUG
 	DWARF_DEBUG
+	ELF_DETAILS
 
 	.gptab.sdata : {
 		*(.gptab.data)
-- 
GitLab


From a667e4d3d0b021e13faad19f59cc49b706ae3d16 Mon Sep 17 00:00:00 2001
From: Yanteng Si <siyanteng@loongson.cn>
Date: Fri, 17 Jun 2022 20:47:54 +0800
Subject: [PATCH 0762/1731] docs/LoongArch: Fix notes rendering by using reST
 directives

Notes are better expressed with reST admonitions.

Fixes: 0ea8ce61cb2c ("Documentation: LoongArch: Add basic documentations")
Reviewed-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Yanteng Si <siyanteng@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 Documentation/loongarch/introduction.rst   | 15 +++++++++------
 Documentation/loongarch/irq-chip-model.rst | 22 +++++++++++++---------
 2 files changed, 22 insertions(+), 15 deletions(-)

diff --git a/Documentation/loongarch/introduction.rst b/Documentation/loongarch/introduction.rst
index 2bf40ad370dfa..216b3f390e806 100644
--- a/Documentation/loongarch/introduction.rst
+++ b/Documentation/loongarch/introduction.rst
@@ -45,10 +45,12 @@ Name              Alias           Usage               Preserved
 ``$r23``-``$r31`` ``$s0``-``$s8`` Static registers    Yes
 ================= =============== =================== ============
 
-Note: The register ``$r21`` is reserved in the ELF psABI, but used by the Linux
-kernel for storing the percpu base address. It normally has no ABI name, but is
-called ``$u0`` in the kernel. You may also see ``$v0`` or ``$v1`` in some old code,
-however they are deprecated aliases of ``$a0`` and ``$a1`` respectively.
+.. Note::
+    The register ``$r21`` is reserved in the ELF psABI, but used by the Linux
+    kernel for storing the percpu base address. It normally has no ABI name,
+    but is called ``$u0`` in the kernel. You may also see ``$v0`` or ``$v1``
+    in some old code,however they are deprecated aliases of ``$a0`` and ``$a1``
+    respectively.
 
 FPRs
 ----
@@ -69,8 +71,9 @@ Name              Alias              Usage               Preserved
 ``$f24``-``$f31`` ``$fs0``-``$fs7``  Static registers    Yes
 ================= ================== =================== ============
 
-Note: You may see ``$fv0`` or ``$fv1`` in some old code, however they are deprecated
-aliases of ``$fa0`` and ``$fa1`` respectively.
+.. Note::
+    You may see ``$fv0`` or ``$fv1`` in some old code, however they are
+    deprecated aliases of ``$fa0`` and ``$fa1`` respectively.
 
 VRs
 ----
diff --git a/Documentation/loongarch/irq-chip-model.rst b/Documentation/loongarch/irq-chip-model.rst
index 8d88f7ab2e5e9..7988f41923639 100644
--- a/Documentation/loongarch/irq-chip-model.rst
+++ b/Documentation/loongarch/irq-chip-model.rst
@@ -145,12 +145,16 @@ Documentation of Loongson's LS7A chipset:
 
   https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (in English)
 
-Note: CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described
-in Section 7.4 of "LoongArch Reference Manual, Vol 1"; LIOINTC is "Legacy I/O
-Interrupts" described in Section 11.1 of "Loongson 3A5000 Processor Reference
-Manual"; EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of
-"Loongson 3A5000 Processor Reference Manual"; HTVECINTC is "HyperTransport
-Interrupts" described in Section 14.3 of "Loongson 3A5000 Processor Reference
-Manual"; PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
-"Loongson 7A1000 Bridge User Manual"; PCH-LPC is "LPC Interrupts" described in
-Section 24.3 of "Loongson 7A1000 Bridge User Manual".
+.. Note::
+    - CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described
+      in Section 7.4 of "LoongArch Reference Manual, Vol 1";
+    - LIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of
+      "Loongson 3A5000 Processor Reference Manual";
+    - EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of
+      "Loongson 3A5000 Processor Reference Manual";
+    - HTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of
+      "Loongson 3A5000 Processor Reference Manual";
+    - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
+      "Loongson 7A1000 Bridge User Manual";
+    - PCH-LPC is "LPC Interrupts" described in Section 24.3 of
+      "Loongson 7A1000 Bridge User Manual".
-- 
GitLab


From 03dfb4a3abc4cc497850e6968b59005485592369 Mon Sep 17 00:00:00 2001
From: Yanteng Si <siyanteng@loongson.cn>
Date: Fri, 17 Jun 2022 20:47:55 +0800
Subject: [PATCH 0763/1731] docs/zh_CN/LoongArch: Fix notes rendering by using
 reST directives

Notes are better expressed with reST admonitions.

Fixes: f23b22599f8e ("Documentation/zh_CN: Add basic LoongArch documentations")
Reviewed-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Yanteng Si <siyanteng@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 .../translations/zh_CN/loongarch/introduction.rst  | 14 ++++++++------
 .../zh_CN/loongarch/irq-chip-model.rst             | 14 ++++++++------
 2 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/Documentation/translations/zh_CN/loongarch/introduction.rst b/Documentation/translations/zh_CN/loongarch/introduction.rst
index e31a1a928c484..11686ee0caeb1 100644
--- a/Documentation/translations/zh_CN/loongarch/introduction.rst
+++ b/Documentation/translations/zh_CN/loongarch/introduction.rst
@@ -46,10 +46,11 @@ LA64中每个寄存器为64位宽。 ``$r0`` 的内容总是固定为0，而其
 ``$r23``-``$r31`` ``$s0``-``$s8`` 静态寄存器          是
 ================= =============== =================== ==========
 
-注意：``$r21``寄存器在ELF psABI中保留未使用，但是在Linux内核用于保存每CPU
-变量基地址。该寄存器没有ABI命名，不过在内核中称为``$u0``。在一些遗留代码
-中有时可能见到``$v0``和``$v1``，它们是``$a0``和``$a1``的别名，属于已经废弃
-的用法。
+.. note::
+    注意： ``$r21`` 寄存器在ELF psABI中保留未使用，但是在Linux内核用于保
+    存每CPU变量基地址。该寄存器没有ABI命名，不过在内核中称为 ``$u0`` 。在
+    一些遗留代码中有时可能见到 ``$v0`` 和 ``$v1`` ，它们是 ``$a0`` 和
+    ``$a1`` 的别名，属于已经废弃的用法。
 
 浮点寄存器
 ----------
@@ -68,8 +69,9 @@ LA64中每个寄存器为64位宽。 ``$r0`` 的内容总是固定为0，而其
 ``$f24``-``$f31`` ``$fs0``-``$fs7``  静态寄存器          是
 ================= ================== =================== ==========
 
-注意：在一些遗留代码中有时可能见到 ``$v0`` 和 ``$v1`` ，它们是 ``$a0``
-和 ``$a1`` 的别名，属于已经废弃的用法。
+.. note::
+    注意：在一些遗留代码中有时可能见到 ``$v0`` 和 ``$v1`` ，它们是
+    ``$a0`` 和 ``$a1`` 的别名，属于已经废弃的用法。
 
 
 向量寄存器
diff --git a/Documentation/translations/zh_CN/loongarch/irq-chip-model.rst b/Documentation/translations/zh_CN/loongarch/irq-chip-model.rst
index 2a4c3ad38be4a..fb5d23b49ed55 100644
--- a/Documentation/translations/zh_CN/loongarch/irq-chip-model.rst
+++ b/Documentation/translations/zh_CN/loongarch/irq-chip-model.rst
@@ -147,9 +147,11 @@ PCH-LPC::
 
   https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (英文版)
 
-注：CPUINTC即《龙芯架构参考手册卷一》第7.4节所描述的CSR.ECFG/CSR.ESTAT寄存器及其中断
-控制逻辑；LIOINTC即《龙芯3A5000处理器使用手册》第11.1节所描述的“传统I/O中断”；EIOINTC
-即《龙芯3A5000处理器使用手册》第11.2节所描述的“扩展I/O中断”；HTVECINTC即《龙芯3A5000
-处理器使用手册》第14.3节所描述的“HyperTransport中断”；PCH-PIC/PCH-MSI即《龙芯7A1000桥
-片用户手册》第5章所描述的“中断控制器”；PCH-LPC即《龙芯7A1000桥片用户手册》第24.3节所
-描述的“LPC中断”。
+.. note::
+    - CPUINTC：即《龙芯架构参考手册卷一》第7.4节所描述的CSR.ECFG/CSR.ESTAT寄存器及其
+      中断控制逻辑；
+    - LIOINTC：即《龙芯3A5000处理器使用手册》第11.1节所描述的“传统I/O中断”；
+    - EIOINTC：即《龙芯3A5000处理器使用手册》第11.2节所描述的“扩展I/O中断”；
+    - HTVECINTC：即《龙芯3A5000处理器使用手册》第14.3节所描述的“HyperTransport中断”；
+    - PCH-PIC/PCH-MSI：即《龙芯7A1000桥片用户手册》第5章所描述的“中断控制器”；
+    - PCH-LPC：即《龙芯7A1000桥片用户手册》第24.3节所描述的“LPC中断”。
-- 
GitLab


From d49951219b0249d3eff49e4f02e0de82357bc8a0 Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Fri, 17 Jun 2022 07:30:28 -0600
Subject: [PATCH 0764/1731] ALSA: hda/realtek: Add quirk for Clevo PD70PNT

Fixes speaker output and headset detection on Clevo PD70PNT.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20220617133028.50568-1-tcrawford@system76.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/pci/hda/patch_realtek.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index b937f63d0d09e..ff9a09a670ed9 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -2634,6 +2634,7 @@ static const struct snd_pci_quirk alc882_fixup_tbl[] = {
 	SND_PCI_QUIRK(0x1558, 0x67e1, "Clevo PB71[DE][CDF]", ALC1220_FIXUP_CLEVO_PB51ED_PINS),
 	SND_PCI_QUIRK(0x1558, 0x67e5, "Clevo PC70D[PRS](?:-D|-G)?", ALC1220_FIXUP_CLEVO_PB51ED_PINS),
 	SND_PCI_QUIRK(0x1558, 0x67f1, "Clevo PC70H[PRS]", ALC1220_FIXUP_CLEVO_PB51ED_PINS),
+	SND_PCI_QUIRK(0x1558, 0x67f5, "Clevo PD70PN[NRT]", ALC1220_FIXUP_CLEVO_PB51ED_PINS),
 	SND_PCI_QUIRK(0x1558, 0x70d1, "Clevo PC70[ER][CDF]", ALC1220_FIXUP_CLEVO_PB51ED_PINS),
 	SND_PCI_QUIRK(0x1558, 0x7714, "Clevo X170SM", ALC1220_FIXUP_CLEVO_PB51ED_PINS),
 	SND_PCI_QUIRK(0x1558, 0x7715, "Clevo X170KM-G", ALC1220_FIXUP_CLEVO_PB51ED),
-- 
GitLab


From e7858254f9af9ad4f1570d781666e3af4c298a88 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Tue, 14 Jun 2022 17:10:18 -0700
Subject: [PATCH 0765/1731] drm/i915/gt: Move multicast register handling to a
 dedicated file

Handling of multicast/replicated registers is spread across intel_gt.c
and intel_uncore.c today.  As multicast handling and the related
steering logic gets more complicated with the addition of new platforms
and new rules it makes sense to centralize it all in one place.

For now the existing functions have been moved to the new .c/.h as-is.
Function renames and updates to operate in a more consistent manner will
be done in subsequent patches.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: Harish Chegondi <harish.chegondi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220615001019.1821989-2-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/Makefile               |   1 +
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c  |   1 +
 drivers/gpu/drm/i915/gt/intel_engine_cs.c   |   3 +-
 drivers/gpu/drm/i915/gt/intel_gt.c          | 297 +------------
 drivers/gpu/drm/i915/gt/intel_gt.h          |  15 -
 drivers/gpu/drm/i915/gt/intel_gt_debugfs.c  |   1 +
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c      | 448 ++++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_gt_mcr.h      |  37 ++
 drivers/gpu/drm/i915/gt/intel_region_lmem.c |   1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c |   1 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c  |   1 +
 drivers/gpu/drm/i915/i915_drv.h             |   2 -
 drivers/gpu/drm/i915/intel_uncore.c         | 112 -----
 drivers/gpu/drm/i915/intel_uncore.h         |   8 -
 14 files changed, 495 insertions(+), 433 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_mcr.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_mcr.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d2b18f03a33ce..08f5d0d6e83a7 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -103,6 +103,7 @@ gt-y += \
 	gt/intel_gt_debugfs.o \
 	gt/intel_gt_engines_debugfs.o \
 	gt/intel_gt_irq.o \
+	gt/intel_gt_mcr.o \
 	gt/intel_gt_pm.o \
 	gt/intel_gt_pm_debugfs.o \
 	gt/intel_gt_pm_irq.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 47b5e0e342abd..da30503d3ca22 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -13,6 +13,7 @@
 #include "gem/i915_gem_lmem.h"
 #include "gem/i915_gem_region.h"
 #include "gt/intel_gt.h"
+#include "gt/intel_gt_mcr.h"
 #include "gt/intel_region_lmem.h"
 #include "i915_drv.h"
 #include "i915_gem_stolen.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f0acf8518a515..244af1bdb7db7 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -21,8 +21,9 @@
 #include "intel_engine_user.h"
 #include "intel_execlists_submission.h"
 #include "intel_gt.h"
-#include "intel_gt_requests.h"
+#include "intel_gt_mcr.h"
 #include "intel_gt_pm.h"
+#include "intel_gt_requests.h"
 #include "intel_lrc.h"
 #include "intel_lrc_reg.h"
 #include "intel_reset.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index f33290358c518..be9877c4b4969 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -17,6 +17,7 @@
 #include "intel_gt_clock_utils.h"
 #include "intel_gt_debugfs.h"
 #include "intel_gt_gmch.h"
+#include "intel_gt_mcr.h"
 #include "intel_gt_pm.h"
 #include "intel_gt_regs.h"
 #include "intel_gt_requests.h"
@@ -102,107 +103,13 @@ int intel_gt_assign_ggtt(struct intel_gt *gt)
 	return gt->ggtt ? 0 : -ENOMEM;
 }
 
-static const char * const intel_steering_types[] = {
-	"L3BANK",
-	"MSLICE",
-	"LNCF",
-	"INSTANCE 0",
-};
-
-static const struct intel_mmio_range icl_l3bank_steering_table[] = {
-	{ 0x00B100, 0x00B3FF },
-	{},
-};
-
-static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = {
-	{ 0x004000, 0x004AFF },
-	{ 0x00C800, 0x00CFFF },
-	{ 0x00DD00, 0x00DDFF },
-	{ 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
-	{},
-};
-
-static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = {
-	{ 0x00B000, 0x00B0FF },
-	{ 0x00D800, 0x00D8FF },
-	{},
-};
-
-static const struct intel_mmio_range dg2_lncf_steering_table[] = {
-	{ 0x00B000, 0x00B0FF },
-	{ 0x00D880, 0x00D8FF },
-	{},
-};
-
-/*
- * We have several types of MCR registers on PVC where steering to (0,0)
- * will always provide us with a non-terminated value.  We'll stick them
- * all in the same table for simplicity.
- */
-static const struct intel_mmio_range pvc_instance0_steering_table[] = {
-	{ 0x004000, 0x004AFF },		/* HALF-BSLICE */
-	{ 0x008800, 0x00887F },		/* CC */
-	{ 0x008A80, 0x008AFF },		/* TILEPSMI */
-	{ 0x00B000, 0x00B0FF },		/* HALF-BSLICE */
-	{ 0x00B100, 0x00B3FF },		/* L3BANK */
-	{ 0x00C800, 0x00CFFF },		/* HALF-BSLICE */
-	{ 0x00D800, 0x00D8FF },		/* HALF-BSLICE */
-	{ 0x00DD00, 0x00DDFF },		/* BSLICE */
-	{ 0x00E900, 0x00E9FF },		/* HALF-BSLICE */
-	{ 0x00EC00, 0x00EEFF },		/* HALF-BSLICE */
-	{ 0x00F000, 0x00FFFF },		/* HALF-BSLICE */
-	{ 0x024180, 0x0241FF },		/* HALF-BSLICE */
-	{},
-};
-
 int intel_gt_init_mmio(struct intel_gt *gt)
 {
-	struct drm_i915_private *i915 = gt->i915;
-
 	intel_gt_init_clock_frequency(gt);
 
 	intel_uc_init_mmio(&gt->uc);
 	intel_sseu_info_init(gt);
-
-	/*
-	 * An mslice is unavailable only if both the meml3 for the slice is
-	 * disabled *and* all of the DSS in the slice (quadrant) are disabled.
-	 */
-	if (HAS_MSLICE_STEERING(i915)) {
-		gt->info.mslice_mask =
-			intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
-							  GEN_DSS_PER_MSLICE);
-		gt->info.mslice_mask |=
-			(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
-			 GEN12_MEML3_EN_MASK);
-
-		if (!gt->info.mslice_mask) /* should be impossible! */
-			drm_warn(&i915->drm, "mslice mask all zero!\n");
-	}
-
-	if (IS_PONTEVECCHIO(i915)) {
-		gt->steering_table[INSTANCE0] = pvc_instance0_steering_table;
-	} else if (IS_DG2(i915)) {
-		gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
-		gt->steering_table[LNCF] = dg2_lncf_steering_table;
-	} else if (IS_XEHPSDV(i915)) {
-		gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
-		gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;
-	} else if (GRAPHICS_VER(i915) >= 11 &&
-		   GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {
-		gt->steering_table[L3BANK] = icl_l3bank_steering_table;
-		gt->info.l3bank_mask =
-			~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
-			GEN10_L3BANK_MASK;
-		if (!gt->info.l3bank_mask) /* should be impossible! */
-			drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
-	} else if (GRAPHICS_VER(i915) >= 11) {
-		/*
-		 * We expect all modern platforms to have at least some
-		 * type of steering that needs to be initialized.
-		 */
-		MISSING_CASE(INTEL_INFO(i915)->platform);
-	}
+	intel_gt_mcr_init(gt);
 
 	return intel_engines_init_mmio(gt);
 }
@@ -864,206 +771,6 @@ void intel_gt_driver_late_release_all(struct drm_i915_private *i915)
 	}
 }
 
-/**
- * intel_gt_reg_needs_read_steering - determine whether a register read
- *     requires explicit steering
- * @gt: GT structure
- * @reg: the register to check steering requirements for
- * @type: type of multicast steering to check
- *
- * Determines whether @reg needs explicit steering of a specific type for
- * reads.
- *
- * Returns false if @reg does not belong to a register range of the given
- * steering type, or if the default (subslice-based) steering IDs are suitable
- * for @type steering too.
- */
-static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt,
-					     i915_reg_t reg,
-					     enum intel_steering_type type)
-{
-	const u32 offset = i915_mmio_reg_offset(reg);
-	const struct intel_mmio_range *entry;
-
-	if (likely(!intel_gt_needs_read_steering(gt, type)))
-		return false;
-
-	for (entry = gt->steering_table[type]; entry->end; entry++) {
-		if (offset >= entry->start && offset <= entry->end)
-			return true;
-	}
-
-	return false;
-}
-
-/**
- * intel_gt_get_valid_steering - determines valid IDs for a class of MCR steering
- * @gt: GT structure
- * @type: multicast register type
- * @sliceid: Slice ID returned
- * @subsliceid: Subslice ID returned
- *
- * Determines sliceid and subsliceid values that will steer reads
- * of a specific multicast register class to a valid value.
- */
-static void intel_gt_get_valid_steering(struct intel_gt *gt,
-					enum intel_steering_type type,
-					u8 *sliceid, u8 *subsliceid)
-{
-	switch (type) {
-	case L3BANK:
-		*sliceid = 0;		/* unused */
-		*subsliceid = __ffs(gt->info.l3bank_mask);
-		break;
-	case MSLICE:
-		GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915));
-		*sliceid = __ffs(gt->info.mslice_mask);
-		*subsliceid = 0;	/* unused */
-		break;
-	case LNCF:
-		/*
-		 * An LNCF is always present if its mslice is present, so we
-		 * can safely just steer to LNCF 0 in all cases.
-		 */
-		GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915));
-		*sliceid = __ffs(gt->info.mslice_mask) << 1;
-		*subsliceid = 0;	/* unused */
-		break;
-	case INSTANCE0:
-		/*
-		 * There are a lot of MCR types for which instance (0, 0)
-		 * will always provide a non-terminated value.
-		 */
-		*sliceid = 0;
-		*subsliceid = 0;
-		break;
-	default:
-		MISSING_CASE(type);
-		*sliceid = 0;
-		*subsliceid = 0;
-	}
-}
-
-/**
- * intel_gt_read_register_fw - reads a GT register with support for multicast
- * @gt: GT structure
- * @reg: register to read
- *
- * This function will read a GT register.  If the register is a multicast
- * register, the read will be steered to a valid instance (i.e., one that
- * isn't fused off or powered down by power gating).
- *
- * Returns the value from a valid instance of @reg.
- */
-u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg)
-{
-	int type;
-	u8 sliceid, subsliceid;
-
-	for (type = 0; type < NUM_STEERING_TYPES; type++) {
-		if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
-			intel_gt_get_valid_steering(gt, type, &sliceid,
-						    &subsliceid);
-			return intel_uncore_read_with_mcr_steering_fw(gt->uncore,
-								      reg,
-								      sliceid,
-								      subsliceid);
-		}
-	}
-
-	return intel_uncore_read_fw(gt->uncore, reg);
-}
-
-/**
- * intel_gt_get_valid_steering_for_reg - get a valid steering for a register
- * @gt: GT structure
- * @reg: register for which the steering is required
- * @sliceid: return variable for slice steering
- * @subsliceid: return variable for subslice steering
- *
- * This function returns a slice/subslice pair that is guaranteed to work for
- * read steering of the given register. Note that a value will be returned even
- * if the register is not replicated and therefore does not actually require
- * steering.
- */
-void intel_gt_get_valid_steering_for_reg(struct intel_gt *gt, i915_reg_t reg,
-					 u8 *sliceid, u8 *subsliceid)
-{
-	int type;
-
-	for (type = 0; type < NUM_STEERING_TYPES; type++) {
-		if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
-			intel_gt_get_valid_steering(gt, type, sliceid,
-						    subsliceid);
-			return;
-		}
-	}
-
-	*sliceid = gt->default_steering.groupid;
-	*subsliceid = gt->default_steering.instanceid;
-}
-
-u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg)
-{
-	int type;
-	u8 sliceid, subsliceid;
-
-	for (type = 0; type < NUM_STEERING_TYPES; type++) {
-		if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
-			intel_gt_get_valid_steering(gt, type, &sliceid,
-						    &subsliceid);
-			return intel_uncore_read_with_mcr_steering(gt->uncore,
-								   reg,
-								   sliceid,
-								   subsliceid);
-		}
-	}
-
-	return intel_uncore_read(gt->uncore, reg);
-}
-
-static void report_steering_type(struct drm_printer *p,
-				 struct intel_gt *gt,
-				 enum intel_steering_type type,
-				 bool dump_table)
-{
-	const struct intel_mmio_range *entry;
-	u8 slice, subslice;
-
-	BUILD_BUG_ON(ARRAY_SIZE(intel_steering_types) != NUM_STEERING_TYPES);
-
-	if (!gt->steering_table[type]) {
-		drm_printf(p, "%s steering: uses default steering\n",
-			   intel_steering_types[type]);
-		return;
-	}
-
-	intel_gt_get_valid_steering(gt, type, &slice, &subslice);
-	drm_printf(p, "%s steering: sliceid=0x%x, subsliceid=0x%x\n",
-		   intel_steering_types[type], slice, subslice);
-
-	if (!dump_table)
-		return;
-
-	for (entry = gt->steering_table[type]; entry->end; entry++)
-		drm_printf(p, "\t0x%06x - 0x%06x\n", entry->start, entry->end);
-}
-
-void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
-			      bool dump_table)
-{
-	drm_printf(p, "Default steering: sliceid=0x%x, subsliceid=0x%x\n",
-		   gt->default_steering.groupid,
-		   gt->default_steering.instanceid);
-
-	if (IS_PONTEVECCHIO(gt->i915)) {
-		report_steering_type(p, gt, INSTANCE0, dump_table);
-	} else if (HAS_MSLICE_STEERING(gt->i915)) {
-		report_steering_type(p, gt, MSLICE, dump_table);
-		report_steering_type(p, gt, LNCF, dump_table);
-	}
-}
-
 static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
 {
 	int ret;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 44c6cb63ccbc8..61d30d5c7e90f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -93,21 +93,6 @@ static inline bool intel_gt_is_wedged(const struct intel_gt *gt)
 	return unlikely(test_bit(I915_WEDGED, &gt->reset.flags));
 }
 
-static inline bool intel_gt_needs_read_steering(struct intel_gt *gt,
-						enum intel_steering_type type)
-{
-	return gt->steering_table[type];
-}
-
-void intel_gt_get_valid_steering_for_reg(struct intel_gt *gt, i915_reg_t reg,
-					 u8 *sliceid, u8 *subsliceid);
-
-u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg);
-u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg);
-
-void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
-			      bool dump_table);
-
 int intel_gt_probe_all(struct drm_i915_private *i915);
 int intel_gt_tiles_init(struct drm_i915_private *i915);
 void intel_gt_release_all(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
index d886fdc2c694b..ea07f2bb846f6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
@@ -9,6 +9,7 @@
 #include "intel_gt.h"
 #include "intel_gt_debugfs.h"
 #include "intel_gt_engines_debugfs.h"
+#include "intel_gt_mcr.h"
 #include "intel_gt_pm_debugfs.h"
 #include "intel_sseu_debugfs.h"
 #include "pxp/intel_pxp_debugfs.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
new file mode 100644
index 0000000000000..1279a1fe1001a
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -0,0 +1,448 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include "i915_drv.h"
+
+#include "intel_gt_mcr.h"
+#include "intel_gt_regs.h"
+
+/**
+ * DOC: GT Multicast/Replicated (MCR) Register Support
+ *
+ * Some GT registers are designed as "multicast" or "replicated" registers:
+ * multiple instances of the same register share a single MMIO offset.  MCR
+ * registers are generally used when the hardware needs to potentially track
+ * independent values of a register per hardware unit (e.g., per-subslice,
+ * per-L3bank, etc.).  The specific types of replication that exist vary
+ * per-platform.
+ *
+ * MMIO accesses to MCR registers are controlled according to the settings
+ * programmed in the platform's MCR_SELECTOR register(s).  MMIO writes to MCR
+ * registers can be done in either a (i.e., a single write updates all
+ * instances of the register to the same value) or unicast (a write updates only
+ * one specific instance).  Reads of MCR registers always operate in a unicast
+ * manner regardless of how the multicast/unicast bit is set in MCR_SELECTOR.
+ * Selection of a specific MCR instance for unicast operations is referred to
+ * as "steering."
+ *
+ * If MCR register operations are steered toward a hardware unit that is
+ * fused off or currently powered down due to power gating, the MMIO operation
+ * is "terminated" by the hardware.  Terminated read operations will return a
+ * value of zero and terminated unicast write operations will be silently
+ * ignored.
+ */
+
+#define HAS_MSLICE_STEERING(dev_priv)	(INTEL_INFO(dev_priv)->has_mslice_steering)
+
+static const char * const intel_steering_types[] = {
+	"L3BANK",
+	"MSLICE",
+	"LNCF",
+	"INSTANCE 0",
+};
+
+static const struct intel_mmio_range icl_l3bank_steering_table[] = {
+	{ 0x00B100, 0x00B3FF },
+	{},
+};
+
+static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = {
+	{ 0x004000, 0x004AFF },
+	{ 0x00C800, 0x00CFFF },
+	{ 0x00DD00, 0x00DDFF },
+	{ 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
+	{},
+};
+
+static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = {
+	{ 0x00B000, 0x00B0FF },
+	{ 0x00D800, 0x00D8FF },
+	{},
+};
+
+static const struct intel_mmio_range dg2_lncf_steering_table[] = {
+	{ 0x00B000, 0x00B0FF },
+	{ 0x00D880, 0x00D8FF },
+	{},
+};
+
+/*
+ * We have several types of MCR registers on PVC where steering to (0,0)
+ * will always provide us with a non-terminated value.  We'll stick them
+ * all in the same table for simplicity.
+ */
+static const struct intel_mmio_range pvc_instance0_steering_table[] = {
+	{ 0x004000, 0x004AFF },		/* HALF-BSLICE */
+	{ 0x008800, 0x00887F },		/* CC */
+	{ 0x008A80, 0x008AFF },		/* TILEPSMI */
+	{ 0x00B000, 0x00B0FF },		/* HALF-BSLICE */
+	{ 0x00B100, 0x00B3FF },		/* L3BANK */
+	{ 0x00C800, 0x00CFFF },		/* HALF-BSLICE */
+	{ 0x00D800, 0x00D8FF },		/* HALF-BSLICE */
+	{ 0x00DD00, 0x00DDFF },		/* BSLICE */
+	{ 0x00E900, 0x00E9FF },		/* HALF-BSLICE */
+	{ 0x00EC00, 0x00EEFF },		/* HALF-BSLICE */
+	{ 0x00F000, 0x00FFFF },		/* HALF-BSLICE */
+	{ 0x024180, 0x0241FF },		/* HALF-BSLICE */
+	{},
+};
+
+void intel_gt_mcr_init(struct intel_gt *gt)
+{
+	struct drm_i915_private *i915 = gt->i915;
+
+	/*
+	 * An mslice is unavailable only if both the meml3 for the slice is
+	 * disabled *and* all of the DSS in the slice (quadrant) are disabled.
+	 */
+	if (HAS_MSLICE_STEERING(i915)) {
+		gt->info.mslice_mask =
+			intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
+							  GEN_DSS_PER_MSLICE);
+		gt->info.mslice_mask |=
+			(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
+			 GEN12_MEML3_EN_MASK);
+
+		if (!gt->info.mslice_mask) /* should be impossible! */
+			drm_warn(&i915->drm, "mslice mask all zero!\n");
+	}
+
+	if (IS_PONTEVECCHIO(i915)) {
+		gt->steering_table[INSTANCE0] = pvc_instance0_steering_table;
+	} else if (IS_DG2(i915)) {
+		gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
+		gt->steering_table[LNCF] = dg2_lncf_steering_table;
+	} else if (IS_XEHPSDV(i915)) {
+		gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
+		gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;
+	} else if (GRAPHICS_VER(i915) >= 11 &&
+		   GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {
+		gt->steering_table[L3BANK] = icl_l3bank_steering_table;
+		gt->info.l3bank_mask =
+			~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
+			GEN10_L3BANK_MASK;
+		if (!gt->info.l3bank_mask) /* should be impossible! */
+			drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
+	} else if (GRAPHICS_VER(i915) >= 11) {
+		/*
+		 * We expect all modern platforms to have at least some
+		 * type of steering that needs to be initialized.
+		 */
+		MISSING_CASE(INTEL_INFO(i915)->platform);
+	}
+}
+
+/**
+ * uncore_rw_with_mcr_steering_fw - Access a register after programming
+ *				    the MCR selector register.
+ * @uncore: pointer to struct intel_uncore
+ * @reg: register being accessed
+ * @rw_flag: FW_REG_READ for read access or FW_REG_WRITE for write access
+ * @slice: slice number (ignored for multi-cast write)
+ * @subslice: sub-slice number (ignored for multi-cast write)
+ * @value: register value to be written (ignored for read)
+ *
+ * Return: 0 for write access. register value for read access.
+ *
+ * Caller needs to make sure the relevant forcewake wells are up.
+ */
+static u32 uncore_rw_with_mcr_steering_fw(struct intel_uncore *uncore,
+					  i915_reg_t reg, u8 rw_flag,
+					  int slice, int subslice, u32 value)
+{
+	u32 mcr_mask, mcr_ss, mcr, old_mcr, val = 0;
+
+	lockdep_assert_held(&uncore->lock);
+
+	if (GRAPHICS_VER(uncore->i915) >= 11) {
+		mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
+		mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
+
+		/*
+		 * Wa_22013088509
+		 *
+		 * The setting of the multicast/unicast bit usually wouldn't
+		 * matter for read operations (which always return the value
+		 * from a single register instance regardless of how that bit
+		 * is set), but some platforms have a workaround requiring us
+		 * to remain in multicast mode for reads.  There's no real
+		 * downside to this, so we'll just go ahead and do so on all
+		 * platforms; we'll only clear the multicast bit from the mask
+		 * when exlicitly doing a write operation.
+		 */
+		if (rw_flag == FW_REG_WRITE)
+			mcr_mask |= GEN11_MCR_MULTICAST;
+	} else {
+		mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
+		mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+	}
+
+	old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
+
+	mcr &= ~mcr_mask;
+	mcr |= mcr_ss;
+	intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
+
+	if (rw_flag == FW_REG_READ)
+		val = intel_uncore_read_fw(uncore, reg);
+	else
+		intel_uncore_write_fw(uncore, reg, value);
+
+	mcr &= ~mcr_mask;
+	mcr |= old_mcr & mcr_mask;
+
+	intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
+
+	return val;
+}
+
+static u32 uncore_rw_with_mcr_steering(struct intel_uncore *uncore,
+				       i915_reg_t reg, u8 rw_flag,
+				       int slice, int subslice,
+				       u32 value)
+{
+	enum forcewake_domains fw_domains;
+	u32 val;
+
+	fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
+						    rw_flag);
+	fw_domains |= intel_uncore_forcewake_for_reg(uncore,
+						     GEN8_MCR_SELECTOR,
+						     FW_REG_READ | FW_REG_WRITE);
+
+	spin_lock_irq(&uncore->lock);
+	intel_uncore_forcewake_get__locked(uncore, fw_domains);
+
+	val = uncore_rw_with_mcr_steering_fw(uncore, reg, rw_flag,
+					     slice, subslice, value);
+
+	intel_uncore_forcewake_put__locked(uncore, fw_domains);
+	spin_unlock_irq(&uncore->lock);
+
+	return val;
+}
+
+u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore,
+					   i915_reg_t reg, int slice, int subslice)
+{
+	return uncore_rw_with_mcr_steering_fw(uncore, reg, FW_REG_READ,
+					      slice, subslice, 0);
+}
+
+u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore,
+					i915_reg_t reg, int slice, int subslice)
+{
+	return uncore_rw_with_mcr_steering(uncore, reg, FW_REG_READ,
+					   slice, subslice, 0);
+}
+
+void intel_uncore_write_with_mcr_steering(struct intel_uncore *uncore,
+					  i915_reg_t reg, u32 value,
+					  int slice, int subslice)
+{
+	uncore_rw_with_mcr_steering(uncore, reg, FW_REG_WRITE,
+				    slice, subslice, value);
+}
+
+/**
+ * intel_gt_reg_needs_read_steering - determine whether a register read
+ *     requires explicit steering
+ * @gt: GT structure
+ * @reg: the register to check steering requirements for
+ * @type: type of multicast steering to check
+ *
+ * Determines whether @reg needs explicit steering of a specific type for
+ * reads.
+ *
+ * Returns false if @reg does not belong to a register range of the given
+ * steering type, or if the default (subslice-based) steering IDs are suitable
+ * for @type steering too.
+ */
+static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt,
+					     i915_reg_t reg,
+					     enum intel_steering_type type)
+{
+	const u32 offset = i915_mmio_reg_offset(reg);
+	const struct intel_mmio_range *entry;
+
+	if (likely(!intel_gt_needs_read_steering(gt, type)))
+		return false;
+
+	for (entry = gt->steering_table[type]; entry->end; entry++) {
+		if (offset >= entry->start && offset <= entry->end)
+			return true;
+	}
+
+	return false;
+}
+
+/**
+ * intel_gt_get_valid_steering - determines valid IDs for a class of MCR steering
+ * @gt: GT structure
+ * @type: multicast register type
+ * @sliceid: Slice ID returned
+ * @subsliceid: Subslice ID returned
+ *
+ * Determines sliceid and subsliceid values that will steer reads
+ * of a specific multicast register class to a valid value.
+ */
+static void intel_gt_get_valid_steering(struct intel_gt *gt,
+					enum intel_steering_type type,
+					u8 *sliceid, u8 *subsliceid)
+{
+	switch (type) {
+	case L3BANK:
+		*sliceid = 0;		/* unused */
+		*subsliceid = __ffs(gt->info.l3bank_mask);
+		break;
+	case MSLICE:
+		GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915));
+		*sliceid = __ffs(gt->info.mslice_mask);
+		*subsliceid = 0;	/* unused */
+		break;
+	case LNCF:
+		/*
+		 * An LNCF is always present if its mslice is present, so we
+		 * can safely just steer to LNCF 0 in all cases.
+		 */
+		GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915));
+		*sliceid = __ffs(gt->info.mslice_mask) << 1;
+		*subsliceid = 0;	/* unused */
+		break;
+	case INSTANCE0:
+		/*
+		 * There are a lot of MCR types for which instance (0, 0)
+		 * will always provide a non-terminated value.
+		 */
+		*sliceid = 0;
+		*subsliceid = 0;
+		break;
+	default:
+		MISSING_CASE(type);
+		*sliceid = 0;
+		*subsliceid = 0;
+	}
+}
+
+/**
+ * intel_gt_get_valid_steering_for_reg - get a valid steering for a register
+ * @gt: GT structure
+ * @reg: register for which the steering is required
+ * @sliceid: return variable for slice steering
+ * @subsliceid: return variable for subslice steering
+ *
+ * This function returns a slice/subslice pair that is guaranteed to work for
+ * read steering of the given register. Note that a value will be returned even
+ * if the register is not replicated and therefore does not actually require
+ * steering.
+ */
+void intel_gt_get_valid_steering_for_reg(struct intel_gt *gt, i915_reg_t reg,
+					 u8 *sliceid, u8 *subsliceid)
+{
+	int type;
+
+	for (type = 0; type < NUM_STEERING_TYPES; type++) {
+		if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
+			intel_gt_get_valid_steering(gt, type, sliceid,
+						    subsliceid);
+			return;
+		}
+	}
+
+	*sliceid = gt->default_steering.groupid;
+	*subsliceid = gt->default_steering.instanceid;
+}
+
+/**
+ * intel_gt_read_register_fw - reads a GT register with support for multicast
+ * @gt: GT structure
+ * @reg: register to read
+ *
+ * This function will read a GT register.  If the register is a multicast
+ * register, the read will be steered to a valid instance (i.e., one that
+ * isn't fused off or powered down by power gating).
+ *
+ * Returns the value from a valid instance of @reg.
+ */
+u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg)
+{
+	int type;
+	u8 sliceid, subsliceid;
+
+	for (type = 0; type < NUM_STEERING_TYPES; type++) {
+		if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
+			intel_gt_get_valid_steering(gt, type, &sliceid,
+						    &subsliceid);
+			return intel_uncore_read_with_mcr_steering_fw(gt->uncore,
+								      reg,
+								      sliceid,
+								      subsliceid);
+		}
+	}
+
+	return intel_uncore_read_fw(gt->uncore, reg);
+}
+
+u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg)
+{
+	int type;
+	u8 sliceid, subsliceid;
+
+	for (type = 0; type < NUM_STEERING_TYPES; type++) {
+		if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
+			intel_gt_get_valid_steering(gt, type, &sliceid,
+						    &subsliceid);
+			return intel_uncore_read_with_mcr_steering(gt->uncore,
+								   reg,
+								   sliceid,
+								   subsliceid);
+		}
+	}
+
+	return intel_uncore_read(gt->uncore, reg);
+}
+
+static void report_steering_type(struct drm_printer *p,
+				 struct intel_gt *gt,
+				 enum intel_steering_type type,
+				 bool dump_table)
+{
+	const struct intel_mmio_range *entry;
+	u8 slice, subslice;
+
+	BUILD_BUG_ON(ARRAY_SIZE(intel_steering_types) != NUM_STEERING_TYPES);
+
+	if (!gt->steering_table[type]) {
+		drm_printf(p, "%s steering: uses default steering\n",
+			   intel_steering_types[type]);
+		return;
+	}
+
+	intel_gt_get_valid_steering(gt, type, &slice, &subslice);
+	drm_printf(p, "%s steering: sliceid=0x%x, subsliceid=0x%x\n",
+		   intel_steering_types[type], slice, subslice);
+
+	if (!dump_table)
+		return;
+
+	for (entry = gt->steering_table[type]; entry->end; entry++)
+		drm_printf(p, "\t0x%06x - 0x%06x\n", entry->start, entry->end);
+}
+
+void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
+			      bool dump_table)
+{
+	drm_printf(p, "Default steering: sliceid=0x%x, subsliceid=0x%x\n",
+		   gt->default_steering.groupid,
+		   gt->default_steering.instanceid);
+
+	if (IS_PONTEVECCHIO(gt->i915)) {
+		report_steering_type(p, gt, INSTANCE0, dump_table);
+	} else if (HAS_MSLICE_STEERING(gt->i915)) {
+		report_steering_type(p, gt, MSLICE, dump_table);
+		report_steering_type(p, gt, LNCF, dump_table);
+	}
+}
+
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
new file mode 100644
index 0000000000000..b570c1571243d
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_GT_MCR__
+#define __INTEL_GT_MCR__
+
+#include "intel_gt_types.h"
+
+void intel_gt_mcr_init(struct intel_gt *gt);
+
+u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore,
+					   i915_reg_t reg,
+					   int slice, int subslice);
+u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore,
+					i915_reg_t reg,	int slice, int subslice);
+void intel_uncore_write_with_mcr_steering(struct intel_uncore *uncore,
+					  i915_reg_t reg, u32 value,
+					  int slice, int subslice);
+
+u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg);
+u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg);
+
+static inline bool intel_gt_needs_read_steering(struct intel_gt *gt,
+						enum intel_steering_type type)
+{
+	return gt->steering_table[type];
+}
+
+void intel_gt_get_valid_steering_for_reg(struct intel_gt *gt, i915_reg_t reg,
+					 u8 *sliceid, u8 *subsliceid);
+
+void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
+			      bool dump_table);
+
+#endif /* __INTEL_GT_MCR__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index e9c12e0d6f59f..1f4e7237a924c 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -12,6 +12,7 @@
 #include "gem/i915_gem_region.h"
 #include "gem/i915_gem_ttm.h"
 #include "gt/intel_gt.h"
+#include "gt/intel_gt_mcr.h"
 #include "gt/intel_gt_regs.h"
 
 static int
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index c4af51144216a..e4913aefac97d 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -9,6 +9,7 @@
 #include "intel_engine_regs.h"
 #include "intel_gpu_commands.h"
 #include "intel_gt.h"
+#include "intel_gt_mcr.h"
 #include "intel_gt_regs.h"
 #include "intel_ring.h"
 #include "intel_workarounds.h"
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index bb197610fd5b0..dea138d78111b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -7,6 +7,7 @@
 
 #include "gt/intel_engine_regs.h"
 #include "gt/intel_gt.h"
+#include "gt/intel_gt_mcr.h"
 #include "gt/intel_gt_regs.h"
 #include "gt/intel_lrc.h"
 #include "gt/shmem_utils.h"
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 59cd888209fe1..80d73222b125f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1346,8 +1346,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
 
-#define HAS_MSLICE_STEERING(dev_priv)	(INTEL_INFO(dev_priv)->has_mslice_steering)
-
 /*
  * Set this flag, when platform requires 64K GTT page sizes or larger for
  * device local memory access.
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 33304eb987e46..a852c471d1b38 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2644,118 +2644,6 @@ intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
 	return fw_domains;
 }
 
-/**
- * uncore_rw_with_mcr_steering_fw - Access a register after programming
- *				    the MCR selector register.
- * @uncore: pointer to struct intel_uncore
- * @reg: register being accessed
- * @rw_flag: FW_REG_READ for read access or FW_REG_WRITE for write access
- * @slice: slice number (ignored for multi-cast write)
- * @subslice: sub-slice number (ignored for multi-cast write)
- * @value: register value to be written (ignored for read)
- *
- * Return: 0 for write access. register value for read access.
- *
- * Caller needs to make sure the relevant forcewake wells are up.
- */
-static u32 uncore_rw_with_mcr_steering_fw(struct intel_uncore *uncore,
-					  i915_reg_t reg, u8 rw_flag,
-					  int slice, int subslice, u32 value)
-{
-	u32 mcr_mask, mcr_ss, mcr, old_mcr, val = 0;
-
-	lockdep_assert_held(&uncore->lock);
-
-	if (GRAPHICS_VER(uncore->i915) >= 11) {
-		mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
-		mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
-
-		/*
-		 * Wa_22013088509
-		 *
-		 * The setting of the multicast/unicast bit usually wouldn't
-		 * matter for read operations (which always return the value
-		 * from a single register instance regardless of how that bit
-		 * is set), but some platforms have a workaround requiring us
-		 * to remain in multicast mode for reads.  There's no real
-		 * downside to this, so we'll just go ahead and do so on all
-		 * platforms; we'll only clear the multicast bit from the mask
-		 * when exlicitly doing a write operation.
-		 */
-		if (rw_flag == FW_REG_WRITE)
-			mcr_mask |= GEN11_MCR_MULTICAST;
-	} else {
-		mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
-		mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
-	}
-
-	old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
-
-	mcr &= ~mcr_mask;
-	mcr |= mcr_ss;
-	intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
-
-	if (rw_flag == FW_REG_READ)
-		val = intel_uncore_read_fw(uncore, reg);
-	else
-		intel_uncore_write_fw(uncore, reg, value);
-
-	mcr &= ~mcr_mask;
-	mcr |= old_mcr & mcr_mask;
-
-	intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
-
-	return val;
-}
-
-static u32 uncore_rw_with_mcr_steering(struct intel_uncore *uncore,
-				       i915_reg_t reg, u8 rw_flag,
-				       int slice, int subslice,
-				       u32 value)
-{
-	enum forcewake_domains fw_domains;
-	u32 val;
-
-	fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
-						    rw_flag);
-	fw_domains |= intel_uncore_forcewake_for_reg(uncore,
-						     GEN8_MCR_SELECTOR,
-						     FW_REG_READ | FW_REG_WRITE);
-
-	spin_lock_irq(&uncore->lock);
-	intel_uncore_forcewake_get__locked(uncore, fw_domains);
-
-	val = uncore_rw_with_mcr_steering_fw(uncore, reg, rw_flag,
-					     slice, subslice, value);
-
-	intel_uncore_forcewake_put__locked(uncore, fw_domains);
-	spin_unlock_irq(&uncore->lock);
-
-	return val;
-}
-
-u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore,
-					   i915_reg_t reg, int slice, int subslice)
-{
-	return uncore_rw_with_mcr_steering_fw(uncore, reg, FW_REG_READ,
-					      slice, subslice, 0);
-}
-
-u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore,
-					i915_reg_t reg, int slice, int subslice)
-{
-	return uncore_rw_with_mcr_steering(uncore, reg, FW_REG_READ,
-					   slice, subslice, 0);
-}
-
-void intel_uncore_write_with_mcr_steering(struct intel_uncore *uncore,
-					  i915_reg_t reg, u32 value,
-					  int slice, int subslice)
-{
-	uncore_rw_with_mcr_steering(uncore, reg, FW_REG_WRITE,
-				    slice, subslice, value);
-}
-
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 #include "selftests/mock_uncore.c"
 #include "selftests/intel_uncore.c"
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 52fe3d89dd2b8..b1fa912a65e75 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -210,14 +210,6 @@ intel_uncore_has_fifo(const struct intel_uncore *uncore)
 	return uncore->flags & UNCORE_HAS_FIFO;
 }
 
-u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore,
-					   i915_reg_t reg,
-					   int slice, int subslice);
-u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore,
-					i915_reg_t reg,	int slice, int subslice);
-void intel_uncore_write_with_mcr_steering(struct intel_uncore *uncore,
-					  i915_reg_t reg, u32 value,
-					  int slice, int subslice);
 void
 intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug);
 void intel_uncore_init_early(struct intel_uncore *uncore,
-- 
GitLab


From 3fe6c7f53eaa62e3700d8ae076e9c42a1d855242 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Tue, 14 Jun 2022 17:10:19 -0700
Subject: [PATCH 0766/1731] drm/i915/gt: Cleanup interface for MCR operations

Let's replace the assortment of intel_gt_* and intel_uncore_* functions
that operate on MCR registers with a cleaner set of interfaces:

  * intel_gt_mcr_read -- unicast read from specific instance
  * intel_gt_mcr_read_any[_fw] -- unicast read from any non-terminated
    instance
  * intel_gt_mcr_unicast_write -- unicast write to specific instance
  * intel_gt_mcr_multicast_write[_fw] -- multicast write to all instances

We'll also replace the historic "slice" and "subslice" terminology with
"group" and "instance" to match the documentation for more recent
platforms; these days MCR steering applies to more types of replication
than just slice/subslice.

v2:
 - Reference the new kerneldoc from i915.rst.  (Jani)
 - Tweak the wording of the documentation for a couple functions to
   clarify the difference between "_fw" and non-"_fw" forms.

v3:
 - s/read/write/ to fix copy-paste mistake in a couple comments.
   (Harish)

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: Harish Chegondi <harish.chegondi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220615001019.1821989-3-matthew.d.roper@intel.com
---
 Documentation/gpu/i915.rst                  |  12 +
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c  |   2 +-
 drivers/gpu/drm/i915/gt/intel_engine_cs.c   |  33 ++-
 drivers/gpu/drm/i915/gt/intel_gt_debugfs.c  |   2 +-
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c      | 239 ++++++++++++--------
 drivers/gpu/drm/i915/gt/intel_gt_mcr.h      |  43 ++--
 drivers/gpu/drm/i915/gt/intel_region_lmem.c |   4 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c |   8 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c  |   2 +-
 9 files changed, 200 insertions(+), 145 deletions(-)

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 54060cd6c4194..4e59db1cfb00e 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -246,6 +246,18 @@ Display State Buffer
 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
    :internal:
 
+GT Programming
+==============
+
+Multicast/Replicated (MCR) Registers
+------------------------------------
+
+.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+   :doc: GT Multicast/Replicated (MCR) Register Support
+
+.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+   :internal:
+
 Memory Management and Command Submission
 ========================================
 
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index da30503d3ca22..fa54823d12192 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -835,7 +835,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
 	} else {
 		resource_size_t lmem_range;
 
-		lmem_range = intel_gt_read_register(&i915->gt0, XEHPSDV_TILE0_ADDR_RANGE) & 0xFFFF;
+		lmem_range = intel_gt_mcr_read_any(&i915->gt0, XEHPSDV_TILE0_ADDR_RANGE) & 0xFFFF;
 		lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT;
 		lmem_size *= SZ_1G;
 	}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 244af1bdb7db7..136cc44c3deb8 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1428,14 +1428,6 @@ void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
 	ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
 }
 
-static u32
-read_subslice_reg(const struct intel_engine_cs *engine,
-		  int slice, int subslice, i915_reg_t reg)
-{
-	return intel_uncore_read_with_mcr_steering(engine->uncore, reg,
-						   slice, subslice);
-}
-
 /* NB: please notice the memset */
 void intel_engine_get_instdone(const struct intel_engine_cs *engine,
 			       struct intel_instdone *instdone)
@@ -1469,28 +1461,33 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
 		if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
 			for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice, subslice) {
 				instdone->sampler[slice][subslice] =
-					read_subslice_reg(engine, slice, subslice,
-							  GEN7_SAMPLER_INSTDONE);
+					intel_gt_mcr_read(engine->gt,
+							  GEN7_SAMPLER_INSTDONE,
+							  slice, subslice);
 				instdone->row[slice][subslice] =
-					read_subslice_reg(engine, slice, subslice,
-							  GEN7_ROW_INSTDONE);
+					intel_gt_mcr_read(engine->gt,
+							  GEN7_ROW_INSTDONE,
+							  slice, subslice);
 			}
 		} else {
 			for_each_instdone_slice_subslice(i915, sseu, slice, subslice) {
 				instdone->sampler[slice][subslice] =
-					read_subslice_reg(engine, slice, subslice,
-							  GEN7_SAMPLER_INSTDONE);
+					intel_gt_mcr_read(engine->gt,
+							  GEN7_SAMPLER_INSTDONE,
+							  slice, subslice);
 				instdone->row[slice][subslice] =
-					read_subslice_reg(engine, slice, subslice,
-							  GEN7_ROW_INSTDONE);
+					intel_gt_mcr_read(engine->gt,
+							  GEN7_ROW_INSTDONE,
+							  slice, subslice);
 			}
 		}
 
 		if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
 			for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice, subslice)
 				instdone->geom_svg[slice][subslice] =
-					read_subslice_reg(engine, slice, subslice,
-							  XEHPG_INSTDONE_GEOM_SVG);
+					intel_gt_mcr_read(engine->gt,
+							  XEHPG_INSTDONE_GEOM_SVG,
+							  slice, subslice);
 		}
 	} else if (GRAPHICS_VER(i915) >= 7) {
 		instdone->instdone =
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
index ea07f2bb846f6..dd53641f36372 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
@@ -65,7 +65,7 @@ static int steering_show(struct seq_file *m, void *data)
 	struct drm_printer p = drm_seq_file_printer(m);
 	struct intel_gt *gt = m->private;
 
-	intel_gt_report_steering(&p, gt, true);
+	intel_gt_mcr_report_steering(&p, gt, true);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 1279a1fe1001a..777025d5bd665 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -134,23 +134,22 @@ void intel_gt_mcr_init(struct intel_gt *gt)
 	}
 }
 
-/**
- * uncore_rw_with_mcr_steering_fw - Access a register after programming
- *				    the MCR selector register.
+/*
+ * rw_with_mcr_steering_fw - Access a register with specific MCR steering
  * @uncore: pointer to struct intel_uncore
  * @reg: register being accessed
  * @rw_flag: FW_REG_READ for read access or FW_REG_WRITE for write access
- * @slice: slice number (ignored for multi-cast write)
- * @subslice: sub-slice number (ignored for multi-cast write)
+ * @group: group number (documented as "sliceid" on older platforms)
+ * @instance: instance number (documented as "subsliceid" on older platforms)
  * @value: register value to be written (ignored for read)
  *
  * Return: 0 for write access. register value for read access.
  *
  * Caller needs to make sure the relevant forcewake wells are up.
  */
-static u32 uncore_rw_with_mcr_steering_fw(struct intel_uncore *uncore,
-					  i915_reg_t reg, u8 rw_flag,
-					  int slice, int subslice, u32 value)
+static u32 rw_with_mcr_steering_fw(struct intel_uncore *uncore,
+				   i915_reg_t reg, u8 rw_flag,
+				   int group, int instance, u32 value)
 {
 	u32 mcr_mask, mcr_ss, mcr, old_mcr, val = 0;
 
@@ -158,7 +157,7 @@ static u32 uncore_rw_with_mcr_steering_fw(struct intel_uncore *uncore,
 
 	if (GRAPHICS_VER(uncore->i915) >= 11) {
 		mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
-		mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
+		mcr_ss = GEN11_MCR_SLICE(group) | GEN11_MCR_SUBSLICE(instance);
 
 		/*
 		 * Wa_22013088509
@@ -176,7 +175,7 @@ static u32 uncore_rw_with_mcr_steering_fw(struct intel_uncore *uncore,
 			mcr_mask |= GEN11_MCR_MULTICAST;
 	} else {
 		mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
-		mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+		mcr_ss = GEN8_MCR_SLICE(group) | GEN8_MCR_SUBSLICE(instance);
 	}
 
 	old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
@@ -198,10 +197,10 @@ static u32 uncore_rw_with_mcr_steering_fw(struct intel_uncore *uncore,
 	return val;
 }
 
-static u32 uncore_rw_with_mcr_steering(struct intel_uncore *uncore,
-				       i915_reg_t reg, u8 rw_flag,
-				       int slice, int subslice,
-				       u32 value)
+static u32 rw_with_mcr_steering(struct intel_uncore *uncore,
+				i915_reg_t reg, u8 rw_flag,
+				int group, int instance,
+				u32 value)
 {
 	enum forcewake_domains fw_domains;
 	u32 val;
@@ -215,8 +214,7 @@ static u32 uncore_rw_with_mcr_steering(struct intel_uncore *uncore,
 	spin_lock_irq(&uncore->lock);
 	intel_uncore_forcewake_get__locked(uncore, fw_domains);
 
-	val = uncore_rw_with_mcr_steering_fw(uncore, reg, rw_flag,
-					     slice, subslice, value);
+	val = rw_with_mcr_steering_fw(uncore, reg, rw_flag, group, instance, value);
 
 	intel_uncore_forcewake_put__locked(uncore, fw_domains);
 	spin_unlock_irq(&uncore->lock);
@@ -224,31 +222,73 @@ static u32 uncore_rw_with_mcr_steering(struct intel_uncore *uncore,
 	return val;
 }
 
-u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore,
-					   i915_reg_t reg, int slice, int subslice)
+/**
+ * intel_gt_mcr_read - read a specific instance of an MCR register
+ * @gt: GT structure
+ * @reg: the MCR register to read
+ * @group: the MCR group
+ * @instance: the MCR instance
+ *
+ * Returns the value read from an MCR register after steering toward a specific
+ * group/instance.
+ */
+u32 intel_gt_mcr_read(struct intel_gt *gt,
+		      i915_reg_t reg,
+		      int group, int instance)
 {
-	return uncore_rw_with_mcr_steering_fw(uncore, reg, FW_REG_READ,
-					      slice, subslice, 0);
+	return rw_with_mcr_steering(gt->uncore, reg, FW_REG_READ, group, instance, 0);
 }
 
-u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore,
-					i915_reg_t reg, int slice, int subslice)
+/**
+ * intel_gt_mcr_unicast_write - write a specific instance of an MCR register
+ * @gt: GT structure
+ * @reg: the MCR register to write
+ * @value: value to write
+ * @group: the MCR group
+ * @instance: the MCR instance
+ *
+ * Write an MCR register in unicast mode after steering toward a specific
+ * group/instance.
+ */
+void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_reg_t reg, u32 value,
+				int group, int instance)
 {
-	return uncore_rw_with_mcr_steering(uncore, reg, FW_REG_READ,
-					   slice, subslice, 0);
+	rw_with_mcr_steering(gt->uncore, reg, FW_REG_WRITE, group, instance, value);
 }
 
-void intel_uncore_write_with_mcr_steering(struct intel_uncore *uncore,
-					  i915_reg_t reg, u32 value,
-					  int slice, int subslice)
+/**
+ * intel_gt_mcr_multicast_write - write a value to all instances of an MCR register
+ * @gt: GT structure
+ * @reg: the MCR register to write
+ * @value: value to write
+ *
+ * Write an MCR register in multicast mode to update all instances.
+ */
+void intel_gt_mcr_multicast_write(struct intel_gt *gt,
+				i915_reg_t reg, u32 value)
 {
-	uncore_rw_with_mcr_steering(uncore, reg, FW_REG_WRITE,
-				    slice, subslice, value);
+	intel_uncore_write(gt->uncore, reg, value);
 }
 
 /**
- * intel_gt_reg_needs_read_steering - determine whether a register read
- *     requires explicit steering
+ * intel_gt_mcr_multicast_write_fw - write a value to all instances of an MCR register
+ * @gt: GT structure
+ * @reg: the MCR register to write
+ * @value: value to write
+ *
+ * Write an MCR register in multicast mode to update all instances.  This
+ * function assumes the caller is already holding any necessary forcewake
+ * domains; use intel_gt_mcr_multicast_write() in cases where forcewake should
+ * be obtained automatically.
+ */
+void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_reg_t reg, u32 value)
+{
+	intel_uncore_write_fw(gt->uncore, reg, value);
+}
+
+/*
+ * reg_needs_read_steering - determine whether a register read requires
+ *     explicit steering
  * @gt: GT structure
  * @reg: the register to check steering requirements for
  * @type: type of multicast steering to check
@@ -260,14 +300,14 @@ void intel_uncore_write_with_mcr_steering(struct intel_uncore *uncore,
  * steering type, or if the default (subslice-based) steering IDs are suitable
  * for @type steering too.
  */
-static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt,
-					     i915_reg_t reg,
-					     enum intel_steering_type type)
+static bool reg_needs_read_steering(struct intel_gt *gt,
+				    i915_reg_t reg,
+				    enum intel_steering_type type)
 {
 	const u32 offset = i915_mmio_reg_offset(reg);
 	const struct intel_mmio_range *entry;
 
-	if (likely(!intel_gt_needs_read_steering(gt, type)))
+	if (likely(!gt->steering_table[type]))
 		return false;
 
 	for (entry = gt->steering_table[type]; entry->end; entry++) {
@@ -278,29 +318,29 @@ static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt,
 	return false;
 }
 
-/**
- * intel_gt_get_valid_steering - determines valid IDs for a class of MCR steering
+/*
+ * get_nonterminated_steering - determines valid IDs for a class of MCR steering
  * @gt: GT structure
  * @type: multicast register type
- * @sliceid: Slice ID returned
- * @subsliceid: Subslice ID returned
+ * @group: Group ID returned
+ * @instance: Instance ID returned
  *
- * Determines sliceid and subsliceid values that will steer reads
- * of a specific multicast register class to a valid value.
+ * Determines group and instance values that will steer reads of the specified
+ * MCR class to a non-terminated instance.
  */
-static void intel_gt_get_valid_steering(struct intel_gt *gt,
-					enum intel_steering_type type,
-					u8 *sliceid, u8 *subsliceid)
+static void get_nonterminated_steering(struct intel_gt *gt,
+				       enum intel_steering_type type,
+				       u8 *group, u8 *instance)
 {
 	switch (type) {
 	case L3BANK:
-		*sliceid = 0;		/* unused */
-		*subsliceid = __ffs(gt->info.l3bank_mask);
+		*group = 0;		/* unused */
+		*instance = __ffs(gt->info.l3bank_mask);
 		break;
 	case MSLICE:
 		GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915));
-		*sliceid = __ffs(gt->info.mslice_mask);
-		*subsliceid = 0;	/* unused */
+		*group = __ffs(gt->info.mslice_mask);
+		*instance = 0;	/* unused */
 		break;
 	case LNCF:
 		/*
@@ -308,96 +348,105 @@ static void intel_gt_get_valid_steering(struct intel_gt *gt,
 		 * can safely just steer to LNCF 0 in all cases.
 		 */
 		GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915));
-		*sliceid = __ffs(gt->info.mslice_mask) << 1;
-		*subsliceid = 0;	/* unused */
+		*group = __ffs(gt->info.mslice_mask) << 1;
+		*instance = 0;	/* unused */
 		break;
 	case INSTANCE0:
 		/*
 		 * There are a lot of MCR types for which instance (0, 0)
 		 * will always provide a non-terminated value.
 		 */
-		*sliceid = 0;
-		*subsliceid = 0;
+		*group = 0;
+		*instance = 0;
 		break;
 	default:
 		MISSING_CASE(type);
-		*sliceid = 0;
-		*subsliceid = 0;
+		*group = 0;
+		*instance = 0;
 	}
 }
 
 /**
- * intel_gt_get_valid_steering_for_reg - get a valid steering for a register
+ * intel_gt_mcr_get_nonterminated_steering - find group/instance values that
+ *    will steer a register to a non-terminated instance
  * @gt: GT structure
  * @reg: register for which the steering is required
- * @sliceid: return variable for slice steering
- * @subsliceid: return variable for subslice steering
+ * @group: return variable for group steering
+ * @instance: return variable for instance steering
  *
- * This function returns a slice/subslice pair that is guaranteed to work for
+ * This function returns a group/instance pair that is guaranteed to work for
  * read steering of the given register. Note that a value will be returned even
  * if the register is not replicated and therefore does not actually require
  * steering.
  */
-void intel_gt_get_valid_steering_for_reg(struct intel_gt *gt, i915_reg_t reg,
-					 u8 *sliceid, u8 *subsliceid)
+void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt,
+					     i915_reg_t reg,
+					     u8 *group, u8 *instance)
 {
 	int type;
 
 	for (type = 0; type < NUM_STEERING_TYPES; type++) {
-		if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
-			intel_gt_get_valid_steering(gt, type, sliceid,
-						    subsliceid);
+		if (reg_needs_read_steering(gt, reg, type)) {
+			get_nonterminated_steering(gt, type, group, instance);
 			return;
 		}
 	}
 
-	*sliceid = gt->default_steering.groupid;
-	*subsliceid = gt->default_steering.instanceid;
+	*group = gt->default_steering.groupid;
+	*instance = gt->default_steering.instanceid;
 }
 
 /**
- * intel_gt_read_register_fw - reads a GT register with support for multicast
+ * intel_gt_mcr_read_any_fw - reads one instance of an MCR register
  * @gt: GT structure
  * @reg: register to read
  *
- * This function will read a GT register.  If the register is a multicast
- * register, the read will be steered to a valid instance (i.e., one that
- * isn't fused off or powered down by power gating).
+ * Reads a GT MCR register.  The read will be steered to a non-terminated
+ * instance (i.e., one that isn't fused off or powered down by power gating).
+ * This function assumes the caller is already holding any necessary forcewake
+ * domains; use intel_gt_mcr_read_any() in cases where forcewake should be
+ * obtained automatically.
  *
- * Returns the value from a valid instance of @reg.
+ * Returns the value from a non-terminated instance of @reg.
  */
-u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg)
+u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_reg_t reg)
 {
 	int type;
-	u8 sliceid, subsliceid;
+	u8 group, instance;
 
 	for (type = 0; type < NUM_STEERING_TYPES; type++) {
-		if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
-			intel_gt_get_valid_steering(gt, type, &sliceid,
-						    &subsliceid);
-			return intel_uncore_read_with_mcr_steering_fw(gt->uncore,
-								      reg,
-								      sliceid,
-								      subsliceid);
+		if (reg_needs_read_steering(gt, reg, type)) {
+			get_nonterminated_steering(gt, type, &group, &instance);
+			return rw_with_mcr_steering_fw(gt->uncore, reg,
+						       FW_REG_READ,
+						       group, instance, 0);
 		}
 	}
 
 	return intel_uncore_read_fw(gt->uncore, reg);
 }
 
-u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg)
+/**
+ * intel_gt_mcr_read_any - reads one instance of an MCR register
+ * @gt: GT structure
+ * @reg: register to read
+ *
+ * Reads a GT MCR register.  The read will be steered to a non-terminated
+ * instance (i.e., one that isn't fused off or powered down by power gating).
+ *
+ * Returns the value from a non-terminated instance of @reg.
+ */
+u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_reg_t reg)
 {
 	int type;
-	u8 sliceid, subsliceid;
+	u8 group, instance;
 
 	for (type = 0; type < NUM_STEERING_TYPES; type++) {
-		if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
-			intel_gt_get_valid_steering(gt, type, &sliceid,
-						    &subsliceid);
-			return intel_uncore_read_with_mcr_steering(gt->uncore,
-								   reg,
-								   sliceid,
-								   subsliceid);
+		if (reg_needs_read_steering(gt, reg, type)) {
+			get_nonterminated_steering(gt, type, &group, &instance);
+			return rw_with_mcr_steering(gt->uncore, reg,
+						    FW_REG_READ,
+						    group, instance, 0);
 		}
 	}
 
@@ -410,7 +459,7 @@ static void report_steering_type(struct drm_printer *p,
 				 bool dump_table)
 {
 	const struct intel_mmio_range *entry;
-	u8 slice, subslice;
+	u8 group, instance;
 
 	BUILD_BUG_ON(ARRAY_SIZE(intel_steering_types) != NUM_STEERING_TYPES);
 
@@ -420,9 +469,9 @@ static void report_steering_type(struct drm_printer *p,
 		return;
 	}
 
-	intel_gt_get_valid_steering(gt, type, &slice, &subslice);
-	drm_printf(p, "%s steering: sliceid=0x%x, subsliceid=0x%x\n",
-		   intel_steering_types[type], slice, subslice);
+	get_nonterminated_steering(gt, type, &group, &instance);
+	drm_printf(p, "%s steering: group=0x%x, instance=0x%x\n",
+		   intel_steering_types[type], group, instance);
 
 	if (!dump_table)
 		return;
@@ -431,10 +480,10 @@ static void report_steering_type(struct drm_printer *p,
 		drm_printf(p, "\t0x%06x - 0x%06x\n", entry->start, entry->end);
 }
 
-void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
-			      bool dump_table)
+void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt,
+				  bool dump_table)
 {
-	drm_printf(p, "Default steering: sliceid=0x%x, subsliceid=0x%x\n",
+	drm_printf(p, "Default steering: group=0x%x, instance=0x%x\n",
 		   gt->default_steering.groupid,
 		   gt->default_steering.instanceid);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
index b570c1571243d..506b0cbc8db35 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
@@ -10,28 +10,25 @@
 
 void intel_gt_mcr_init(struct intel_gt *gt);
 
-u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore,
-					   i915_reg_t reg,
-					   int slice, int subslice);
-u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore,
-					i915_reg_t reg,	int slice, int subslice);
-void intel_uncore_write_with_mcr_steering(struct intel_uncore *uncore,
-					  i915_reg_t reg, u32 value,
-					  int slice, int subslice);
-
-u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg);
-u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg);
-
-static inline bool intel_gt_needs_read_steering(struct intel_gt *gt,
-						enum intel_steering_type type)
-{
-	return gt->steering_table[type];
-}
-
-void intel_gt_get_valid_steering_for_reg(struct intel_gt *gt, i915_reg_t reg,
-					 u8 *sliceid, u8 *subsliceid);
-
-void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
-			      bool dump_table);
+u32 intel_gt_mcr_read(struct intel_gt *gt,
+		      i915_reg_t reg,
+		      int group, int instance);
+u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_reg_t reg);
+u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_reg_t reg);
+
+void intel_gt_mcr_unicast_write(struct intel_gt *gt,
+				i915_reg_t reg, u32 value,
+				int group, int instance);
+void intel_gt_mcr_multicast_write(struct intel_gt *gt,
+				  i915_reg_t reg, u32 value);
+void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt,
+				     i915_reg_t reg, u32 value);
+
+void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt,
+					     i915_reg_t reg,
+					     u8 *group, u8 *instance);
+
+void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt,
+				  bool dump_table);
 
 #endif /* __INTEL_GT_MCR__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 1f4e7237a924c..2ff4480470207 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -105,11 +105,11 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
 		resource_size_t lmem_range;
 		u64 tile_stolen, flat_ccs_base;
 
-		lmem_range = intel_gt_read_register(&i915->gt0, XEHPSDV_TILE0_ADDR_RANGE) & 0xFFFF;
+		lmem_range = intel_gt_mcr_read_any(&i915->gt0, XEHPSDV_TILE0_ADDR_RANGE) & 0xFFFF;
 		lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT;
 		lmem_size *= SZ_1G;
 
-		flat_ccs_base = intel_gt_read_register(gt, XEHPSDV_FLAT_CCS_BASE_ADDR);
+		flat_ccs_base = intel_gt_mcr_read_any(gt, XEHPSDV_FLAT_CCS_BASE_ADDR);
 		flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT) * SZ_64K;
 
 		/* FIXME: Remove this when we have small-bar enabled */
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e4913aefac97d..3213c593a55f4 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1083,7 +1083,7 @@ static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal,
 	gt->default_steering.instanceid = subslice;
 
 	if (drm_debug_enabled(DRM_UT_DRIVER))
-		intel_gt_report_steering(&p, gt, false);
+		intel_gt_mcr_report_steering(&p, gt, false);
 }
 
 static void
@@ -1624,13 +1624,13 @@ wa_list_apply(struct intel_gt *gt, const struct i915_wa_list *wal)
 		u32 val, old = 0;
 
 		/* open-coded rmw due to steering */
-		old = wa->clr ? intel_gt_read_register_fw(gt, wa->reg) : 0;
+		old = wa->clr ? intel_gt_mcr_read_any_fw(gt, wa->reg) : 0;
 		val = (old & ~wa->clr) | wa->set;
 		if (val != old || !wa->clr)
 			intel_uncore_write_fw(uncore, wa->reg, val);
 
 		if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
-			wa_verify(wa, intel_gt_read_register_fw(gt, wa->reg),
+			wa_verify(wa, intel_gt_mcr_read_any_fw(gt, wa->reg),
 				  wal->name, "application");
 	}
 
@@ -1661,7 +1661,7 @@ static bool wa_list_verify(struct intel_gt *gt,
 
 	for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
 		ok &= wa_verify(wa,
-				intel_gt_read_register_fw(gt, wa->reg),
+				intel_gt_mcr_read_any_fw(gt, wa->reg),
 				wal->name, from);
 
 	intel_uncore_forcewake_put__locked(uncore, fw);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index dea138d78111b..ba7541f3ca610 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -314,7 +314,7 @@ static long __must_check guc_mmio_reg_add(struct intel_gt *gt,
 	 * tracking, it is easier to just program the default steering for all
 	 * regs that don't need a non-default one.
 	 */
-	intel_gt_get_valid_steering_for_reg(gt, reg, &group, &inst);
+	intel_gt_mcr_get_nonterminated_steering(gt, reg, &group, &inst);
 	entry.flags |= GUC_REGSET_STEERING(group, inst);
 
 	slot = __mmio_reg_add(regset, &entry);
-- 
GitLab


From c50f11c6196f45c92ca48b16a5071615d4ae0572 Mon Sep 17 00:00:00 2001
From: Will Deacon <will@kernel.org>
Date: Fri, 10 Jun 2022 16:12:27 +0100
Subject: [PATCH 0767/1731] arm64: mm: Don't invalidate FROM_DEVICE buffers at
 start of DMA transfer

Invalidating the buffer memory in arch_sync_dma_for_device() for
FROM_DEVICE transfers

When using the streaming DMA API to map a buffer prior to inbound
non-coherent DMA (i.e. DMA_FROM_DEVICE), we invalidate any dirty CPU
cachelines so that they will not be written back during the transfer and
corrupt the buffer contents written by the DMA. This, however, poses two
potential problems:

  (1) If the DMA transfer does not write to every byte in the buffer,
      then the unwritten bytes will contain stale data once the transfer
      has completed.

  (2) If the buffer has a virtual alias in userspace, then stale data
      may be visible via this alias during the period between performing
      the cache invalidation and the DMA writes landing in memory.

Address both of these issues by cleaning (aka writing-back) the dirty
lines in arch_sync_dma_for_device(DMA_FROM_DEVICE) instead of discarding
them using invalidation.

Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20220606152150.GA31568@willie-the-truck
Signed-off-by: Will Deacon <will@kernel.org>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20220610151228.4562-2-will@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/mm/cache.S | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
index 0ea6cc25dc663..21c907987080f 100644
--- a/arch/arm64/mm/cache.S
+++ b/arch/arm64/mm/cache.S
@@ -218,8 +218,6 @@ SYM_FUNC_ALIAS(__dma_flush_area, __pi___dma_flush_area)
  */
 SYM_FUNC_START(__pi___dma_map_area)
 	add	x1, x0, x1
-	cmp	w2, #DMA_FROM_DEVICE
-	b.eq	__pi_dcache_inval_poc
 	b	__pi_dcache_clean_poc
 SYM_FUNC_END(__pi___dma_map_area)
 SYM_FUNC_ALIAS(__dma_map_area, __pi___dma_map_area)
-- 
GitLab


From a2b36ffbf5b6ec301e61249c8b09e610bc80772f Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sun, 12 Jun 2022 16:43:25 +0200
Subject: [PATCH 0768/1731] x86/PCI: Revert "x86/PCI: Clip only host bridge
 windows for E820 regions"

This reverts commit 4c5e242d3e93.

Prior to 4c5e242d3e93 ("x86/PCI: Clip only host bridge windows for E820
regions"), E820 regions did not affect PCI host bridge windows.  We only
looked at E820 regions and avoided them when allocating new MMIO space.
If firmware PCI bridge window and BAR assignments used E820 regions, we
left them alone.

After 4c5e242d3e93, we removed E820 regions from the PCI host bridge
windows before looking at BARs, so firmware assignments in E820 regions
looked like errors, and we moved things around to fit in the space left
(if any) after removing the E820 regions.  This unnecessary BAR
reassignment broke several machines.

Guilherme reported that Steam Deck fails to boot after 4c5e242d3e93.  We
clipped the window that contained most 32-bit BARs:

  BIOS-e820: [mem 0x00000000a0000000-0x00000000a00fffff] reserved
  acpi PNP0A08:00: clipped [mem 0x80000000-0xf7ffffff window] to [mem 0xa0100000-0xf7ffffff window] for e820 entry [mem 0xa0000000-0xa00fffff]

which forced us to reassign all those BARs, for example, this NVMe BAR:

  pci 0000:00:01.2: PCI bridge to [bus 01]
  pci 0000:00:01.2:   bridge window [mem 0x80600000-0x806fffff]
  pci 0000:01:00.0: BAR 0: [mem 0x80600000-0x80603fff 64bit]
  pci 0000:00:01.2: can't claim window [mem 0x80600000-0x806fffff]: no compatible bridge window
  pci 0000:01:00.0: can't claim BAR 0 [mem 0x80600000-0x80603fff 64bit]: no compatible bridge window

  pci 0000:00:01.2: bridge window: assigned [mem 0xa0100000-0xa01fffff]
  pci 0000:01:00.0: BAR 0: assigned [mem 0xa0100000-0xa0103fff 64bit]

All the reassignments were successful, so the devices should have been
functional at the new addresses, but some were not.

Andy reported a similar failure on an Intel MID platform.  Benjamin
reported a similar failure on a VMWare Fusion VM.

Note: this is not a clean revert; this revert keeps the later change to
make the clipping dependent on a new pci_use_e820 bool, moving the checking
of this bool to arch_remove_reservations().

[bhelgaas: commit log, add more reporters and testers]
BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=216109
Reported-by: Guilherme G. Piccoli <gpiccoli@igalia.com>
Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reported-by: Benjamin Coddington <bcodding@redhat.com>
Reported-by: Jongman Heo <jongman.heo@gmail.com>
Fixes: 4c5e242d3e93 ("x86/PCI: Clip only host bridge windows for E820 regions")
Link: https://lore.kernel.org/r/20220612144325.85366-1-hdegoede@redhat.com
Tested-by: Guilherme G. Piccoli <gpiccoli@igalia.com>
Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Benjamin Coddington <bcodding@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
 arch/x86/include/asm/e820/api.h |  5 -----
 arch/x86/include/asm/pci_x86.h  |  8 ++++++++
 arch/x86/kernel/resource.c      | 14 +++++++++-----
 arch/x86/pci/acpi.c             |  8 +-------
 4 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/arch/x86/include/asm/e820/api.h b/arch/x86/include/asm/e820/api.h
index 5a39ed59b6db7..e8f58ddd06d97 100644
--- a/arch/x86/include/asm/e820/api.h
+++ b/arch/x86/include/asm/e820/api.h
@@ -4,9 +4,6 @@
 
 #include <asm/e820/types.h>
 
-struct device;
-struct resource;
-
 extern struct e820_table *e820_table;
 extern struct e820_table *e820_table_kexec;
 extern struct e820_table *e820_table_firmware;
@@ -46,8 +43,6 @@ extern void e820__register_nosave_regions(unsigned long limit_pfn);
 
 extern int  e820__get_entry_type(u64 start, u64 end);
 
-extern void remove_e820_regions(struct device *dev, struct resource *avail);
-
 /*
  * Returns true iff the specified range [start,end) is completely contained inside
  * the ISA region.
diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h
index f52a886d35cf8..70533fdcbf02c 100644
--- a/arch/x86/include/asm/pci_x86.h
+++ b/arch/x86/include/asm/pci_x86.h
@@ -69,6 +69,8 @@ void pcibios_scan_specific_bus(int busn);
 
 /* pci-irq.c */
 
+struct pci_dev;
+
 struct irq_info {
 	u8 bus, devfn;			/* Bus, device and function */
 	struct {
@@ -246,3 +248,9 @@ static inline void mmio_config_writel(void __iomem *pos, u32 val)
 # define x86_default_pci_init_irq	NULL
 # define x86_default_pci_fixup_irqs	NULL
 #endif
+
+#if defined(CONFIG_PCI) && defined(CONFIG_ACPI)
+extern bool pci_use_e820;
+#else
+#define pci_use_e820 false
+#endif
diff --git a/arch/x86/kernel/resource.c b/arch/x86/kernel/resource.c
index db2b350a37b77..bba1abd05bfeb 100644
--- a/arch/x86/kernel/resource.c
+++ b/arch/x86/kernel/resource.c
@@ -1,7 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0
-#include <linux/dev_printk.h>
 #include <linux/ioport.h>
+#include <linux/printk.h>
 #include <asm/e820/api.h>
+#include <asm/pci_x86.h>
 
 static void resource_clip(struct resource *res, resource_size_t start,
 			  resource_size_t end)
@@ -24,14 +25,14 @@ static void resource_clip(struct resource *res, resource_size_t start,
 		res->start = end + 1;
 }
 
-void remove_e820_regions(struct device *dev, struct resource *avail)
+static void remove_e820_regions(struct resource *avail)
 {
 	int i;
 	struct e820_entry *entry;
 	u64 e820_start, e820_end;
 	struct resource orig = *avail;
 
-	if (!(avail->flags & IORESOURCE_MEM))
+	if (!pci_use_e820)
 		return;
 
 	for (i = 0; i < e820_table->nr_entries; i++) {
@@ -41,7 +42,7 @@ void remove_e820_regions(struct device *dev, struct resource *avail)
 
 		resource_clip(avail, e820_start, e820_end);
 		if (orig.start != avail->start || orig.end != avail->end) {
-			dev_info(dev, "clipped %pR to %pR for e820 entry [mem %#010Lx-%#010Lx]\n",
+			pr_info("clipped %pR to %pR for e820 entry [mem %#010Lx-%#010Lx]\n",
 				 &orig, avail, e820_start, e820_end);
 			orig = *avail;
 		}
@@ -55,6 +56,9 @@ void arch_remove_reservations(struct resource *avail)
 	 * the low 1MB unconditionally, as this area is needed for some ISA
 	 * cards requiring a memory range, e.g. the i82365 PCMCIA controller.
 	 */
-	if (avail->flags & IORESOURCE_MEM)
+	if (avail->flags & IORESOURCE_MEM) {
 		resource_clip(avail, BIOS_ROM_BASE, BIOS_ROM_END);
+
+		remove_e820_regions(avail);
+	}
 }
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index a4f43054bc79c..2f82480fd4305 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -8,7 +8,6 @@
 #include <linux/pci-acpi.h>
 #include <asm/numa.h>
 #include <asm/pci_x86.h>
-#include <asm/e820/api.h>
 
 struct pci_root_info {
 	struct acpi_pci_root_info common;
@@ -20,7 +19,7 @@ struct pci_root_info {
 #endif
 };
 
-static bool pci_use_e820 = true;
+bool pci_use_e820 = true;
 static bool pci_use_crs = true;
 static bool pci_ignore_seg;
 
@@ -387,11 +386,6 @@ static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci)
 
 	status = acpi_pci_probe_root_resources(ci);
 
-	if (pci_use_e820) {
-		resource_list_for_each_entry(entry, &ci->resources)
-			remove_e820_regions(&device->dev, entry->res);
-	}
-
 	if (pci_use_crs) {
 		resource_list_for_each_entry_safe(entry, tmp, &ci->resources)
 			if (resource_is_pcicfg_ioport(entry->res))
-- 
GitLab


From 63ce81d1c40459e2d9d28f90e2a3e3863e2f63d4 Mon Sep 17 00:00:00 2001
From: Daniel Borkmann <daniel@iogearbox.net>
Date: Fri, 17 Jun 2022 21:42:33 +0200
Subject: [PATCH 0769/1731] bpf, docs: Update some of the JIT/maintenance
 entries

Various minor updates around some of the BPF-related entries:

JITs for ARM32/NFP/SPARC/X86-32 haven't seen updates in quite a while, thus
for now, mark them as 'Odd Fixes' until they become more actively developed.

JITs for POWERPC/S390 are in good shape and receive active development and
review, thus bump to 'Supported' similar as we have with X86-64/ARM64.

JITs for MIPS/RISC-V are in similar good shape as the ones mentioned above,
but looked after mostly in spare time, thus leave for now in 'Maintained' state.

Add Michael to PPC JIT given he's picking up the patches there, so it better
reflects today's state.

Also, I haven't done much reviewing around BPF sockmap/kTLS after John and I
did the big rework back in the days to integrate sockmap with kTLS.

These days, most of this is taken care by John, Jakub {Sitnicki,Kicinski} and
others in the community, so remove myself from these two.

Lastly, move all BPF-related entries into one place, that is, move the sockmap
one over near rest of BPF.

Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Andrii Nakryiko <andrii@kernel.org>
Acked-by: Alexei Starovoitov <ast@kernel.org>
Acked-by: John Fastabend <john.fastabend@gmail.com>
Link: https://lore.kernel.org/r/f9b8a63a0b48dc764bd4c50f87632889f5813f69.1655494758.git.daniel@iogearbox.net
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
---
 MAINTAINERS | 41 ++++++++++++++++++++---------------------
 1 file changed, 20 insertions(+), 21 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 96158b337b407..795f7e40230cf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3662,7 +3662,7 @@ BPF JIT for ARM
 M:	Shubham Bansal <illusionist.neo@gmail.com>
 L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
-S:	Maintained
+S:	Odd Fixes
 F:	arch/arm/net/
 
 BPF JIT for ARM64
@@ -3686,14 +3686,15 @@ BPF JIT for NFP NICs
 M:	Jakub Kicinski <kuba@kernel.org>
 L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
-S:	Supported
+S:	Odd Fixes
 F:	drivers/net/ethernet/netronome/nfp/bpf/
 
 BPF JIT for POWERPC (32-BIT AND 64-BIT)
 M:	Naveen N. Rao <naveen.n.rao@linux.ibm.com>
+M:	Michael Ellerman <mpe@ellerman.id.au>
 L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
-S:	Maintained
+S:	Supported
 F:	arch/powerpc/net/
 
 BPF JIT for RISC-V (32-bit)
@@ -3719,7 +3720,7 @@ M:	Heiko Carstens <hca@linux.ibm.com>
 M:	Vasily Gorbik <gor@linux.ibm.com>
 L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
-S:	Maintained
+S:	Supported
 F:	arch/s390/net/
 X:	arch/s390/net/pnet.c
 
@@ -3727,14 +3728,14 @@ BPF JIT for SPARC (32-BIT AND 64-BIT)
 M:	David S. Miller <davem@davemloft.net>
 L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
-S:	Maintained
+S:	Odd Fixes
 F:	arch/sparc/net/
 
 BPF JIT for X86 32-BIT
 M:	Wang YanQing <udknight@gmail.com>
 L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
-S:	Maintained
+S:	Odd Fixes
 F:	arch/x86/net/bpf_jit_comp32.c
 
 BPF JIT for X86 64-BIT
@@ -3757,6 +3758,19 @@ F:	include/linux/bpf_lsm.h
 F:	kernel/bpf/bpf_lsm.c
 F:	security/bpf/
 
+BPF L7 FRAMEWORK
+M:	John Fastabend <john.fastabend@gmail.com>
+M:	Jakub Sitnicki <jakub@cloudflare.com>
+L:	netdev@vger.kernel.org
+L:	bpf@vger.kernel.org
+S:	Maintained
+F:	include/linux/skmsg.h
+F:	net/core/skmsg.c
+F:	net/core/sock_map.c
+F:	net/ipv4/tcp_bpf.c
+F:	net/ipv4/udp_bpf.c
+F:	net/unix/unix_bpf.c
+
 BPFTOOL
 M:	Quentin Monnet <quentin@isovalent.com>
 L:	bpf@vger.kernel.org
@@ -11095,20 +11109,6 @@ S:	Maintained
 F:	include/net/l3mdev.h
 F:	net/l3mdev
 
-L7 BPF FRAMEWORK
-M:	John Fastabend <john.fastabend@gmail.com>
-M:	Daniel Borkmann <daniel@iogearbox.net>
-M:	Jakub Sitnicki <jakub@cloudflare.com>
-L:	netdev@vger.kernel.org
-L:	bpf@vger.kernel.org
-S:	Maintained
-F:	include/linux/skmsg.h
-F:	net/core/skmsg.c
-F:	net/core/sock_map.c
-F:	net/ipv4/tcp_bpf.c
-F:	net/ipv4/udp_bpf.c
-F:	net/unix/unix_bpf.c
-
 LANDLOCK SECURITY MODULE
 M:	Mickaël Salaün <mic@digikod.net>
 L:	linux-security-module@vger.kernel.org
@@ -13950,7 +13950,6 @@ F:	net/ipv6/tcp*.c
 NETWORKING [TLS]
 M:	Boris Pismenny <borisp@nvidia.com>
 M:	John Fastabend <john.fastabend@gmail.com>
-M:	Daniel Borkmann <daniel@iogearbox.net>
 M:	Jakub Kicinski <kuba@kernel.org>
 L:	netdev@vger.kernel.org
 S:	Maintained
-- 
GitLab


From c88dbbcd88c233cb759ec857b57864c5bfcea26a Mon Sep 17 00:00:00 2001
From: "Masami Hiramatsu (Google)" <mhiramat@kernel.org>
Date: Wed, 8 Jun 2022 01:11:02 +0900
Subject: [PATCH 0770/1731] fprobe, samples: Add use_trace option and show
 hit/missed counter

Add use_trace option to use trace_printk() instead of pr_info()
so that the handler doesn't involve the RCU operations.
And show the hit and missed counter so that the user can check
how many times the probe handler hit and missed.

Signed-off-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Link: https://lore.kernel.org/bpf/165461826247.280167.11939123218334322352.stgit@devnote2
---
 samples/fprobe/fprobe_example.c | 29 +++++++++++++++++++++++++----
 1 file changed, 25 insertions(+), 4 deletions(-)

diff --git a/samples/fprobe/fprobe_example.c b/samples/fprobe/fprobe_example.c
index 24d3cf1091407..01ee6c8c83829 100644
--- a/samples/fprobe/fprobe_example.c
+++ b/samples/fprobe/fprobe_example.c
@@ -21,6 +21,7 @@
 #define BACKTRACE_DEPTH 16
 #define MAX_SYMBOL_LEN 4096
 struct fprobe sample_probe;
+static unsigned long nhit;
 
 static char symbol[MAX_SYMBOL_LEN] = "kernel_clone";
 module_param_string(symbol, symbol, sizeof(symbol), 0644);
@@ -28,6 +29,8 @@ static char nosymbol[MAX_SYMBOL_LEN] = "";
 module_param_string(nosymbol, nosymbol, sizeof(nosymbol), 0644);
 static bool stackdump = true;
 module_param(stackdump, bool, 0644);
+static bool use_trace = false;
+module_param(use_trace, bool, 0644);
 
 static void show_backtrace(void)
 {
@@ -40,7 +43,15 @@ static void show_backtrace(void)
 
 static void sample_entry_handler(struct fprobe *fp, unsigned long ip, struct pt_regs *regs)
 {
-	pr_info("Enter <%pS> ip = 0x%p\n", (void *)ip, (void *)ip);
+	if (use_trace)
+		/*
+		 * This is just an example, no kernel code should call
+		 * trace_printk() except when actively debugging.
+		 */
+		trace_printk("Enter <%pS> ip = 0x%p\n", (void *)ip, (void *)ip);
+	else
+		pr_info("Enter <%pS> ip = 0x%p\n", (void *)ip, (void *)ip);
+	nhit++;
 	if (stackdump)
 		show_backtrace();
 }
@@ -49,8 +60,17 @@ static void sample_exit_handler(struct fprobe *fp, unsigned long ip, struct pt_r
 {
 	unsigned long rip = instruction_pointer(regs);
 
-	pr_info("Return from <%pS> ip = 0x%p to rip = 0x%p (%pS)\n",
-		(void *)ip, (void *)ip, (void *)rip, (void *)rip);
+	if (use_trace)
+		/*
+		 * This is just an example, no kernel code should call
+		 * trace_printk() except when actively debugging.
+		 */
+		trace_printk("Return from <%pS> ip = 0x%p to rip = 0x%p (%pS)\n",
+			(void *)ip, (void *)ip, (void *)rip, (void *)rip);
+	else
+		pr_info("Return from <%pS> ip = 0x%p to rip = 0x%p (%pS)\n",
+			(void *)ip, (void *)ip, (void *)rip, (void *)rip);
+	nhit++;
 	if (stackdump)
 		show_backtrace();
 }
@@ -112,7 +132,8 @@ static void __exit fprobe_exit(void)
 {
 	unregister_fprobe(&sample_probe);
 
-	pr_info("fprobe at %s unregistered\n", symbol);
+	pr_info("fprobe at %s unregistered. %ld times hit, %ld times missed\n",
+		symbol, nhit, sample_probe.nmissed);
 }
 
 module_init(fprobe_init)
-- 
GitLab


From c0f3bb4054ef036e5f67e27f2e3cad9e6512cf00 Mon Sep 17 00:00:00 2001
From: "Masami Hiramatsu (Google)" <mhiramat@kernel.org>
Date: Wed, 8 Jun 2022 01:11:12 +0900
Subject: [PATCH 0771/1731] rethook: Reject getting a rethook if RCU is not
 watching

Since the rethook_recycle() will involve the call_rcu() for reclaiming
the rethook_instance, the rethook must be set up at the RCU available
context (non idle). This rethook_recycle() in the rethook trampoline
handler is inevitable, thus the RCU available check must be done before
setting the rethook trampoline.

This adds a rcu_is_watching() check in the rethook_try_get() so that
it will return NULL if it is called when !rcu_is_watching().

Fixes: 54ecbe6f1ed5 ("rethook: Add a generic return hook")
Signed-off-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Steven Rostedt (Google) <rostedt@goodmis.org>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Link: https://lore.kernel.org/bpf/165461827269.280167.7379263615545598958.stgit@devnote2
---
 kernel/trace/rethook.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/kernel/trace/rethook.c b/kernel/trace/rethook.c
index b56833700d23f..c69d82273ce78 100644
--- a/kernel/trace/rethook.c
+++ b/kernel/trace/rethook.c
@@ -154,6 +154,15 @@ struct rethook_node *rethook_try_get(struct rethook *rh)
 	if (unlikely(!handler))
 		return NULL;
 
+	/*
+	 * This expects the caller will set up a rethook on a function entry.
+	 * When the function returns, the rethook will eventually be reclaimed
+	 * or released in the rethook_recycle() with call_rcu().
+	 * This means the caller must be run in the RCU-availabe context.
+	 */
+	if (unlikely(!rcu_is_watching()))
+		return NULL;
+
 	fn = freelist_try_get(&rh->pool);
 	if (!fn)
 		return NULL;
-- 
GitLab


From 394e771684f7a2cd4e154647bff50084c31bc7cf Mon Sep 17 00:00:00 2001
From: Florian Westphal <fw@strlen.de>
Date: Wed, 15 Jun 2022 15:36:54 +0200
Subject: [PATCH 0772/1731] netfilter: cttimeout: fix slab-out-of-bounds read
 typo in cttimeout_net_exit

syzbot reports:
  BUG: KASAN: slab-out-of-bounds in __list_del_entry_valid+0xcc/0xf0 lib/list_debug.c:42
  [..]
  list_del include/linux/list.h:148 [inline]
  cttimeout_net_exit+0x211/0x540 net/netfilter/nfnetlink_cttimeout.c:617

Problem is the wrong name of the list member, so container_of() result is wrong.

Reported-by: <syzbot+92968395eedbdbd3617d@syzkaller.appspotmail.com>
Fixes: 78222bacfca9 ("netfilter: cttimeout: decouple unlink and free on netns destruction")
Signed-off-by: Florian Westphal <fw@strlen.de>
---
 net/netfilter/nfnetlink_cttimeout.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/net/netfilter/nfnetlink_cttimeout.c b/net/netfilter/nfnetlink_cttimeout.c
index af15102bc696f..f466af4f85317 100644
--- a/net/netfilter/nfnetlink_cttimeout.c
+++ b/net/netfilter/nfnetlink_cttimeout.c
@@ -614,7 +614,7 @@ static void __net_exit cttimeout_net_exit(struct net *net)
 
 	nf_ct_untimeout(net, NULL);
 
-	list_for_each_entry_safe(cur, tmp, &pernet->nfct_timeout_freelist, head) {
+	list_for_each_entry_safe(cur, tmp, &pernet->nfct_timeout_freelist, free_head) {
 		list_del(&cur->free_head);
 
 		if (refcount_dec_and_test(&cur->refcnt))
-- 
GitLab


From cc72b72073ac982a954d3b43519ca1c28f03c27c Mon Sep 17 00:00:00 2001
From: "Masami Hiramatsu (Google)" <mhiramat@kernel.org>
Date: Sat, 28 May 2022 00:55:39 +0900
Subject: [PATCH 0773/1731] tracing/kprobes: Check whether get_kretprobe()
 returns NULL in kretprobe_dispatcher()

There is a small chance that get_kretprobe(ri) returns NULL in
kretprobe_dispatcher() when another CPU unregisters the kretprobe
right after __kretprobe_trampoline_handler().

To avoid this issue, kretprobe_dispatcher() checks the get_kretprobe()
return value again. And if it is NULL, it returns soon because that
kretprobe is under unregistering process.

This issue has been introduced when the kretprobe is decoupled
from the struct kretprobe_instance by commit d741bf41d7c7
("kprobes: Remove kretprobe hash"). Before that commit, the
struct kretprob_instance::rp directly points the kretprobe
and it is never be NULL.

Link: https://lkml.kernel.org/r/165366693881.797669.16926184644089588731.stgit@devnote2

Reported-by: Yonghong Song <yhs@fb.com>
Fixes: d741bf41d7c7 ("kprobes: Remove kretprobe hash")
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: bpf <bpf@vger.kernel.org>
Cc: Kernel Team <kernel-team@fb.com>
Cc: stable@vger.kernel.org
Signed-off-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>
---
 kernel/trace/trace_kprobe.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/kernel/trace/trace_kprobe.c b/kernel/trace/trace_kprobe.c
index 93507330462c1..a245ea673715d 100644
--- a/kernel/trace/trace_kprobe.c
+++ b/kernel/trace/trace_kprobe.c
@@ -1718,8 +1718,17 @@ static int
 kretprobe_dispatcher(struct kretprobe_instance *ri, struct pt_regs *regs)
 {
 	struct kretprobe *rp = get_kretprobe(ri);
-	struct trace_kprobe *tk = container_of(rp, struct trace_kprobe, rp);
+	struct trace_kprobe *tk;
+
+	/*
+	 * There is a small chance that get_kretprobe(ri) returns NULL when
+	 * the kretprobe is unregister on another CPU between kretprobe's
+	 * trampoline_handler and this function.
+	 */
+	if (unlikely(!rp))
+		return 0;
 
+	tk = container_of(rp, struct trace_kprobe, rp);
 	raw_cpu_inc(*tk->nhit);
 
 	if (trace_probe_test_flag(&tk->tp, TP_FLAG_TRACE))
-- 
GitLab


From b9b6d4c925604b70d007feb4c77b8cc4c038d2da Mon Sep 17 00:00:00 2001
From: Stefan Wahren <stefan.wahren@i2se.com>
Date: Wed, 15 Jun 2022 23:05:34 +0200
Subject: [PATCH 0774/1731] ARM: dts: bcm2711-rpi-400: Fix GPIO line names

The GPIO expander line names has been fixed in the vendor tree last year,
so upstream these changes.

Fixes: 1c701accecf2 ("ARM: dts: Add Raspberry Pi 400 support")
Reported-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 arch/arm/boot/dts/bcm2711-rpi-400.dts | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/bcm2711-rpi-400.dts b/arch/arm/boot/dts/bcm2711-rpi-400.dts
index f4d2fc20397c7..c53d9eb0b8027 100644
--- a/arch/arm/boot/dts/bcm2711-rpi-400.dts
+++ b/arch/arm/boot/dts/bcm2711-rpi-400.dts
@@ -28,12 +28,12 @@
 &expgpio {
 	gpio-line-names = "BT_ON",
 			  "WL_ON",
-			  "",
+			  "PWR_LED_OFF",
 			  "GLOBAL_RESET",
 			  "VDD_SD_IO_SEL",
-			  "CAM_GPIO",
+			  "GLOBAL_SHUTDOWN",
 			  "SD_PWR_ON",
-			  "SD_OC_N";
+			  "SHUTDOWN_REQUEST";
 };
 
 &genet_mdio {
-- 
GitLab


From 1e7769653b06b56b7ea7d56911d2d5b2957750cd Mon Sep 17 00:00:00 2001
From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Date: Tue, 14 Jun 2022 15:01:35 +0300
Subject: [PATCH 0775/1731] x86/tdx: Handle load_unaligned_zeropad() page-cross
 to a shared page

load_unaligned_zeropad() can lead to unwanted loads across page boundaries.
The unwanted loads are typically harmless. But, they might be made to
totally unrelated or even unmapped memory. load_unaligned_zeropad()
relies on exception fixup (#PF, #GP and now #VE) to recover from these
unwanted loads.

In TDX guests, the second page can be shared page and a VMM may configure
it to trigger #VE.

The kernel assumes that #VE on a shared page is an MMIO access and tries to
decode instruction to handle it. In case of load_unaligned_zeropad() it
may result in confusion as it is not MMIO access.

Fix it by detecting split page MMIO accesses and failing them.
load_unaligned_zeropad() will recover using exception fixups.

The issue was discovered by analysis and reproduced artificially. It was
not triggered during testing.

[ dhansen: fix up changelogs and comments for grammar and clarity,
	   plus incorporate Kirill's off-by-one fix]

Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Link: https://lkml.kernel.org/r/20220614120135.14812-4-kirill.shutemov@linux.intel.com
---
 arch/x86/coco/tdx/tdx.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c
index c8d44f4632838..928dcf7a20d98 100644
--- a/arch/x86/coco/tdx/tdx.c
+++ b/arch/x86/coco/tdx/tdx.c
@@ -333,8 +333,8 @@ static bool mmio_write(int size, unsigned long addr, unsigned long val)
 
 static int handle_mmio(struct pt_regs *regs, struct ve_info *ve)
 {
+	unsigned long *reg, val, vaddr;
 	char buffer[MAX_INSN_SIZE];
-	unsigned long *reg, val;
 	struct insn insn = {};
 	enum mmio_type mmio;
 	int size, extend_size;
@@ -360,6 +360,19 @@ static int handle_mmio(struct pt_regs *regs, struct ve_info *ve)
 			return -EINVAL;
 	}
 
+	/*
+	 * Reject EPT violation #VEs that split pages.
+	 *
+	 * MMIO accesses are supposed to be naturally aligned and therefore
+	 * never cross page boundaries. Seeing split page accesses indicates
+	 * a bug or a load_unaligned_zeropad() that stepped into an MMIO page.
+	 *
+	 * load_unaligned_zeropad() will recover using exception fixups.
+	 */
+	vaddr = (unsigned long)insn_get_addr_ref(&insn, regs);
+	if (vaddr / PAGE_SIZE != (vaddr + size - 1) / PAGE_SIZE)
+		return -EFAULT;
+
 	/* Handle writes first */
 	switch (mmio) {
 	case MMIO_WRITE:
-- 
GitLab


From f4b0d318097e45cbac5e14976f8bb56aa2cef504 Mon Sep 17 00:00:00 2001
From: sunliming <sunliming@kylinos.cn>
Date: Thu, 2 Jun 2022 22:06:13 +0800
Subject: [PATCH 0776/1731] tracing: Simplify conditional compilation code in
 tracing_set_tracer()

Two conditional compilation directives "#ifdef CONFIG_TRACER_MAX_TRACE"
are used consecutively, and no other code in between. Simplify conditional
the compilation code and only use one "#ifdef CONFIG_TRACER_MAX_TRACE".

Link: https://lkml.kernel.org/r/20220602140613.545069-1-sunliming@kylinos.cn

Signed-off-by: sunliming <sunliming@kylinos.cn>
Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>
---
 kernel/trace/trace.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
index 2c95992e2c710..a8cfac0611bc3 100644
--- a/kernel/trace/trace.c
+++ b/kernel/trace/trace.c
@@ -6424,9 +6424,7 @@ int tracing_set_tracer(struct trace_array *tr, const char *buf)
 		synchronize_rcu();
 		free_snapshot(tr);
 	}
-#endif
 
-#ifdef CONFIG_TRACER_MAX_TRACE
 	if (t->use_max_tr && !had_max_tr) {
 		ret = tracing_alloc_snapshot_instance(tr);
 		if (ret < 0)
-- 
GitLab


From 93a8c044b9a3711d594702daea9fbe2292c73a42 Mon Sep 17 00:00:00 2001
From: Xiang wangx <wangxiang@cdjrlc.com>
Date: Sun, 5 Jun 2022 17:27:29 +0800
Subject: [PATCH 0777/1731] tracefs: Fix syntax errors in comments

Delete the redundant word 'to'.

Link: https://lkml.kernel.org/r/20220605092729.13010-1-wangxiang@cdjrlc.com

Signed-off-by: Xiang wangx <wangxiang@cdjrlc.com>
Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>
---
 fs/tracefs/inode.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/tracefs/inode.c b/fs/tracefs/inode.c
index de7252715b125..81d26abf486fa 100644
--- a/fs/tracefs/inode.c
+++ b/fs/tracefs/inode.c
@@ -553,7 +553,7 @@ struct dentry *tracefs_create_dir(const char *name, struct dentry *parent)
  *
  * Only one instances directory is allowed.
  *
- * The instances directory is special as it allows for mkdir and rmdir to
+ * The instances directory is special as it allows for mkdir and rmdir
  * to be done by userspace. When a mkdir or rmdir is performed, the inode
  * locks are released and the methods passed in (@mkdir and @rmdir) are
  * called without locks and with the name of the directory being created
-- 
GitLab


From 12c3e0c92fd7cb3d3b698d84fdde7dccb6ba8822 Mon Sep 17 00:00:00 2001
From: Gautam Menghani <gautammenghani201@gmail.com>
Date: Sun, 12 Jun 2022 07:42:32 -0700
Subject: [PATCH 0778/1731] tracing/uprobes: Remove unwanted initialization in
 __trace_uprobe_create()

Remove the unwanted initialization of variable 'ret'. This fixes the clang
scan warning: Value stored to 'ret' is never read [deadcode.DeadStores]

Link: https://lkml.kernel.org/r/20220612144232.145209-1-gautammenghani201@gmail.com

Signed-off-by: Gautam Menghani <gautammenghani201@gmail.com>
Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>
---
 kernel/trace/trace_uprobe.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/kernel/trace/trace_uprobe.c b/kernel/trace/trace_uprobe.c
index 9711589273cd5..c3dc4f859a6bc 100644
--- a/kernel/trace/trace_uprobe.c
+++ b/kernel/trace/trace_uprobe.c
@@ -546,7 +546,6 @@ static int __trace_uprobe_create(int argc, const char **argv)
 	bool is_return = false;
 	int i, ret;
 
-	ret = 0;
 	ref_ctr_offset = 0;
 
 	switch (argv[0][0]) {
-- 
GitLab


From 6cf06c17e94f26c290fd3370a5c36514ae15ac43 Mon Sep 17 00:00:00 2001
From: Michael Ellerman <mpe@ellerman.id.au>
Date: Thu, 16 Jun 2022 18:41:49 +1000
Subject: [PATCH 0779/1731] powerpc/mm: Move CMA reservations after
 initmem_init()

After commit 11ac3e87ce09 ("mm: cma: use pageblock_order as the single
alignment") there is an error at boot about the KVM CMA reservation
failing, eg:

  kvm_cma_reserve: reserving 6553 MiB for global area
  cma: Failed to reserve 6553 MiB

That makes it impossible to start KVM guests using the hash MMU with
more than 2G of memory, because the VM is unable to allocate a large
enough region for the hash page table, eg:

  $ qemu-system-ppc64 -enable-kvm -M pseries -m 4G ...
  qemu-system-ppc64: Failed to allocate KVM HPT of order 25: Cannot allocate memory

Aneesh pointed out that this happens because when kvm_cma_reserve() is
called, pageblock_order has not been initialised yet, and is still zero,
causing the checks in cma_init_reserved_mem() against
CMA_MIN_ALIGNMENT_PAGES to fail.

Fix it by moving the call to kvm_cma_reserve() after initmem_init(). The
pageblock_order is initialised in sparse_init() which is called from
initmem_init().

Also move the hugetlb CMA reservation.

Fixes: 11ac3e87ce09 ("mm: cma: use pageblock_order as the single alignment")
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Reviewed-by: Zi Yan <ziy@nvidia.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220616120033.1976732-1-mpe@ellerman.id.au
---
 arch/powerpc/kernel/setup-common.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
index eb0077b302e24..1a02629ec70b0 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -935,12 +935,6 @@ void __init setup_arch(char **cmdline_p)
 	/* Print various info about the machine that has been gathered so far. */
 	print_system_info();
 
-	/* Reserve large chunks of memory for use by CMA for KVM. */
-	kvm_cma_reserve();
-
-	/*  Reserve large chunks of memory for us by CMA for hugetlb */
-	gigantic_hugetlb_cma_reserve();
-
 	klp_init_thread_info(&init_task);
 
 	setup_initial_init_mm(_stext, _etext, _edata, _end);
@@ -955,6 +949,13 @@ void __init setup_arch(char **cmdline_p)
 
 	initmem_init();
 
+	/*
+	 * Reserve large chunks of memory for use by CMA for KVM and hugetlb. These must
+	 * be called after initmem_init(), so that pageblock_order is initialised.
+	 */
+	kvm_cma_reserve();
+	gigantic_hugetlb_cma_reserve();
+
 	early_memtest(min_low_pfn << PAGE_SHIFT, max_low_pfn << PAGE_SHIFT);
 
 	if (ppc_md.setup_arch)
-- 
GitLab


From 20a9689b3607456d92c6fb764501f6a95950b098 Mon Sep 17 00:00:00 2001
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
Date: Sat, 11 Jun 2022 17:10:13 +0200
Subject: [PATCH 0780/1731] powerpc/microwatt: wire up rng during setup_arch()

The platform's RNG must be available before random_init() in order to be
useful for initial seeding, which in turn means that it needs to be
called from setup_arch(), rather than from an init call. Fortunately,
each platform already has a setup_arch function pointer, which means
it's easy to wire this up. This commit also removes some noisy log
messages that don't add much.

Fixes: c25769fddaec ("powerpc/microwatt: Add support for hardware random number generator")
Cc: stable@vger.kernel.org # v5.14+
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220611151015.548325-2-Jason@zx2c4.com
---
 arch/powerpc/platforms/microwatt/microwatt.h |  7 +++++++
 arch/powerpc/platforms/microwatt/rng.c       | 10 +++-------
 arch/powerpc/platforms/microwatt/setup.c     |  8 ++++++++
 3 files changed, 18 insertions(+), 7 deletions(-)
 create mode 100644 arch/powerpc/platforms/microwatt/microwatt.h

diff --git a/arch/powerpc/platforms/microwatt/microwatt.h b/arch/powerpc/platforms/microwatt/microwatt.h
new file mode 100644
index 0000000000000..335417e95e66f
--- /dev/null
+++ b/arch/powerpc/platforms/microwatt/microwatt.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _MICROWATT_H
+#define _MICROWATT_H
+
+void microwatt_rng_init(void);
+
+#endif /* _MICROWATT_H */
diff --git a/arch/powerpc/platforms/microwatt/rng.c b/arch/powerpc/platforms/microwatt/rng.c
index 7bc4d1cbfaf04..8ece87d005c86 100644
--- a/arch/powerpc/platforms/microwatt/rng.c
+++ b/arch/powerpc/platforms/microwatt/rng.c
@@ -11,6 +11,7 @@
 #include <asm/archrandom.h>
 #include <asm/cputable.h>
 #include <asm/machdep.h>
+#include "microwatt.h"
 
 #define DARN_ERR 0xFFFFFFFFFFFFFFFFul
 
@@ -29,7 +30,7 @@ static int microwatt_get_random_darn(unsigned long *v)
 	return 1;
 }
 
-static __init int rng_init(void)
+void __init microwatt_rng_init(void)
 {
 	unsigned long val;
 	int i;
@@ -37,12 +38,7 @@ static __init int rng_init(void)
 	for (i = 0; i < 10; i++) {
 		if (microwatt_get_random_darn(&val)) {
 			ppc_md.get_random_seed = microwatt_get_random_darn;
-			return 0;
+			return;
 		}
 	}
-
-	pr_warn("Unable to use DARN for get_random_seed()\n");
-
-	return -EIO;
 }
-machine_subsys_initcall(, rng_init);
diff --git a/arch/powerpc/platforms/microwatt/setup.c b/arch/powerpc/platforms/microwatt/setup.c
index 0b02603bdb747..6b32539395a48 100644
--- a/arch/powerpc/platforms/microwatt/setup.c
+++ b/arch/powerpc/platforms/microwatt/setup.c
@@ -16,6 +16,8 @@
 #include <asm/xics.h>
 #include <asm/udbg.h>
 
+#include "microwatt.h"
+
 static void __init microwatt_init_IRQ(void)
 {
 	xics_init();
@@ -32,10 +34,16 @@ static int __init microwatt_populate(void)
 }
 machine_arch_initcall(microwatt, microwatt_populate);
 
+static void __init microwatt_setup_arch(void)
+{
+	microwatt_rng_init();
+}
+
 define_machine(microwatt) {
 	.name			= "microwatt",
 	.probe			= microwatt_probe,
 	.init_IRQ		= microwatt_init_IRQ,
+	.setup_arch		= microwatt_setup_arch,
 	.progress		= udbg_progress,
 	.calibrate_decr		= generic_calibrate_decr,
 };
-- 
GitLab


From e561e472a3d441753bd012333b057f48fef1045b Mon Sep 17 00:00:00 2001
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
Date: Sat, 11 Jun 2022 17:10:15 +0200
Subject: [PATCH 0781/1731] powerpc/pseries: wire up rng during setup_arch()

The platform's RNG must be available before random_init() in order to be
useful for initial seeding, which in turn means that it needs to be
called from setup_arch(), rather than from an init call. Fortunately,
each platform already has a setup_arch function pointer, which means
it's easy to wire this up. This commit also removes some noisy log
messages that don't add much.

Fixes: a489043f4626 ("powerpc/pseries: Implement arch_get_random_long() based on H_RANDOM")
Cc: stable@vger.kernel.org # v3.13+
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220611151015.548325-4-Jason@zx2c4.com
---
 arch/powerpc/platforms/pseries/pseries.h |  2 ++
 arch/powerpc/platforms/pseries/rng.c     | 11 +++--------
 arch/powerpc/platforms/pseries/setup.c   |  1 +
 3 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/arch/powerpc/platforms/pseries/pseries.h b/arch/powerpc/platforms/pseries/pseries.h
index f5c916c839c98..1d75b7742ef00 100644
--- a/arch/powerpc/platforms/pseries/pseries.h
+++ b/arch/powerpc/platforms/pseries/pseries.h
@@ -122,4 +122,6 @@ void pseries_lpar_read_hblkrm_characteristics(void);
 static inline void pseries_lpar_read_hblkrm_characteristics(void) { }
 #endif
 
+void pseries_rng_init(void);
+
 #endif /* _PSERIES_PSERIES_H */
diff --git a/arch/powerpc/platforms/pseries/rng.c b/arch/powerpc/platforms/pseries/rng.c
index 6268545947b83..6ddfdeaace9ef 100644
--- a/arch/powerpc/platforms/pseries/rng.c
+++ b/arch/powerpc/platforms/pseries/rng.c
@@ -10,6 +10,7 @@
 #include <asm/archrandom.h>
 #include <asm/machdep.h>
 #include <asm/plpar_wrappers.h>
+#include "pseries.h"
 
 
 static int pseries_get_random_long(unsigned long *v)
@@ -24,19 +25,13 @@ static int pseries_get_random_long(unsigned long *v)
 	return 0;
 }
 
-static __init int rng_init(void)
+void __init pseries_rng_init(void)
 {
 	struct device_node *dn;
 
 	dn = of_find_compatible_node(NULL, NULL, "ibm,random");
 	if (!dn)
-		return -ENODEV;
-
-	pr_info("Registering arch random hook.\n");
-
+		return;
 	ppc_md.get_random_seed = pseries_get_random_long;
-
 	of_node_put(dn);
-	return 0;
 }
-machine_subsys_initcall(pseries, rng_init);
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index afb074269b42b..ee4f1db495159 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -839,6 +839,7 @@ static void __init pSeries_setup_arch(void)
 	}
 
 	ppc_md.pcibios_root_bridge_prepare = pseries_root_bridge_prepare;
+	pseries_rng_init();
 }
 
 static void pseries_panic(char *str)
-- 
GitLab


From ec6d0dde71d760aa60316f8d1c9a1b0d99213529 Mon Sep 17 00:00:00 2001
From: "Naveen N. Rao" <naveen.n.rao@linux.vnet.ibm.com>
Date: Thu, 9 Jun 2022 16:03:28 +0530
Subject: [PATCH 0782/1731] powerpc: Enable execve syscall exit tracepoint

On execve[at], we are zero'ing out most of the thread register state
including gpr[0], which contains the syscall number. Due to this, we
fail to trigger the syscall exit tracepoint properly. Fix this by
retaining gpr[0] in the thread register state.

Before this patch:
  # tail /sys/kernel/debug/tracing/trace
	       cat-123     [000] .....    61.449351: sys_execve(filename:
  7fffa6b23448, argv: 7fffa6b233e0, envp: 7fffa6b233f8)
	       cat-124     [000] .....    62.428481: sys_execve(filename:
  7fffa6b23448, argv: 7fffa6b233e0, envp: 7fffa6b233f8)
	      echo-125     [000] .....    65.813702: sys_execve(filename:
  7fffa6b23378, argv: 7fffa6b233a0, envp: 7fffa6b233b0)
	      echo-125     [000] .....    65.822214: sys_execveat(fd: 0,
  filename: 1009ac48, argv: 7ffff65d0c98, envp: 7ffff65d0ca8, flags: 0)

After this patch:
  # tail /sys/kernel/debug/tracing/trace
	       cat-127     [000] .....   100.416262: sys_execve(filename:
  7fffa41b3448, argv: 7fffa41b33e0, envp: 7fffa41b33f8)
	       cat-127     [000] .....   100.418203: sys_execve -> 0x0
	      echo-128     [000] .....   103.873968: sys_execve(filename:
  7fffa41b3378, argv: 7fffa41b33a0, envp: 7fffa41b33b0)
	      echo-128     [000] .....   103.875102: sys_execve -> 0x0
	      echo-128     [000] .....   103.882097: sys_execveat(fd: 0,
  filename: 1009ac48, argv: 7fffd10d2148, envp: 7fffd10d2158, flags: 0)
	      echo-128     [000] .....   103.883225: sys_execveat -> 0x0

Cc: stable@vger.kernel.org
Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Tested-by: Sumit Dubey2 <Sumit.Dubey2@ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220609103328.41306-1-naveen.n.rao@linux.vnet.ibm.com
---
 arch/powerpc/kernel/process.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index ee04338096214..0fbda89cd1bb5 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -1855,7 +1855,7 @@ void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
 		tm_reclaim_current(0);
 #endif
 
-	memset(regs->gpr, 0, sizeof(regs->gpr));
+	memset(&regs->gpr[1], 0, sizeof(regs->gpr) - sizeof(regs->gpr[0]));
 	regs->ctr = 0;
 	regs->link = 0;
 	regs->xer = 0;
-- 
GitLab


From 7bc08056a6dabc3a1442216daf527edf61ac24b6 Mon Sep 17 00:00:00 2001
From: Andrew Donnellan <ajd@linux.ibm.com>
Date: Tue, 14 Jun 2022 23:49:52 +1000
Subject: [PATCH 0783/1731] powerpc/rtas: Allow ibm,platform-dump RTAS call
 with null buffer address

Add a special case to block_rtas_call() to allow the ibm,platform-dump RTAS
call through the RTAS filter if the buffer address is 0.

According to PAPR, ibm,platform-dump is called with a null buffer address
to notify the platform firmware that processing of a particular dump is
finished.

Without this, on a pseries machine with CONFIG_PPC_RTAS_FILTER enabled, an
application such as rtas_errd that is attempting to retrieve a dump will
encounter an error at the end of the retrieval process.

Fixes: bd59380c5ba4 ("powerpc/rtas: Restrict RTAS requests from userspace")
Cc: stable@vger.kernel.org
Reported-by: Sathvika Vasireddy <sathvika@linux.ibm.com>
Signed-off-by: Andrew Donnellan <ajd@linux.ibm.com>
Reviewed-by: Tyrel Datwyler <tyreld@linux.ibm.com>
Reviewed-by: Nathan Lynch <nathanl@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220614134952.156010-1-ajd@linux.ibm.com
---
 arch/powerpc/kernel/rtas.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c
index a6fce3106e02b..6931339722948 100644
--- a/arch/powerpc/kernel/rtas.c
+++ b/arch/powerpc/kernel/rtas.c
@@ -1071,7 +1071,7 @@ static struct rtas_filter rtas_filters[] __ro_after_init = {
 	{ "get-time-of-day", -1, -1, -1, -1, -1 },
 	{ "ibm,get-vpd", -1, 0, -1, 1, 2 },
 	{ "ibm,lpar-perftools", -1, 2, 3, -1, -1 },
-	{ "ibm,platform-dump", -1, 4, 5, -1, -1 },
+	{ "ibm,platform-dump", -1, 4, 5, -1, -1 },		/* Special cased */
 	{ "ibm,read-slot-reset-state", -1, -1, -1, -1, -1 },
 	{ "ibm,scan-log-dump", -1, 0, 1, -1, -1 },
 	{ "ibm,set-dynamic-indicator", -1, 2, -1, -1, -1 },
@@ -1120,6 +1120,15 @@ static bool block_rtas_call(int token, int nargs,
 				size = 1;
 
 			end = base + size - 1;
+
+			/*
+			 * Special case for ibm,platform-dump - NULL buffer
+			 * address is used to indicate end of dump processing
+			 */
+			if (!strcmp(f->name, "ibm,platform-dump") &&
+			    base == 0)
+				return false;
+
 			if (!in_rmo_buf(base, end))
 				goto err;
 		}
-- 
GitLab


From 856216b70a41ff3f8c866b627546afa01567b389 Mon Sep 17 00:00:00 2001
From: Matt Ranostay <mranostay@ti.com>
Date: Fri, 17 Jun 2022 08:13:04 -0700
Subject: [PATCH 0784/1731] arm64: dts: ti: k3-j721s2: Fix overlapping GICD
 memory region

GICD region was overlapping with GICR causing the latter to not map
successfully, and in turn the gic-v3 driver would fail to initialize.

This issue was hidden till commit 2b2cd74a06c3 ("irqchip/gic-v3: Claim
iomem resources") replaced of_iomap() calls with of_io_request_and_map()
that internally called request_mem_region().

Respective console output before this patchset:

[    0.000000] GICv3: /bus@100000/interrupt-controller@1800000: couldn't map region 0

Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC")
Cc: linux-stable@vger.kernel.org
Cc: Marc Zyngier <maz@kernel.org>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20220617151304.446607-1-mranostay@ti.com
---
 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index be7f39299894e..19966f72c5b38 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -33,7 +33,7 @@
 		ranges;
 		#interrupt-cells = <3>;
 		interrupt-controller;
-		reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
+		reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */
 		      <0x00 0x01900000 0x00 0x100000>, /* GICR */
 		      <0x00 0x6f000000 0x00 0x2000>,   /* GICC */
 		      <0x00 0x6f010000 0x00 0x1000>,   /* GICH */
-- 
GitLab


From 0c0af88f3f318e73237f7fadd02d0bf2b6c996bb Mon Sep 17 00:00:00 2001
From: Aswath Govindraju <a-govindraju@ti.com>
Date: Thu, 12 May 2022 12:18:58 +0530
Subject: [PATCH 0785/1731] arm64: dts: ti: k3-am64-main: Remove support for
 HS400 speed mode
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

AM64 SoC, does not support HS400 and HS200 is the maximum supported speed
mode[1]. Therefore, fix the device tree node to reflect the same.

[1] - https://www.ti.com/lit/ds/symlink/am6442.pdf
      (SPRSP56C – JANUARY 2021 – REVISED FEBRUARY 2022)

Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20220512064859.32059-1-a-govindraju@ti.com
---
 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index f64b368c6c371..cdb530597c5eb 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -456,13 +456,11 @@
 		clock-names = "clk_ahb", "clk_xin";
 		mmc-ddr-1_8v;
 		mmc-hs200-1_8v;
-		mmc-hs400-1_8v;
 		ti,trm-icp = <0x2>;
 		ti,otap-del-sel-legacy = <0x0>;
 		ti,otap-del-sel-mmc-hs = <0x0>;
 		ti,otap-del-sel-ddr52 = <0x6>;
 		ti,otap-del-sel-hs200 = <0x7>;
-		ti,otap-del-sel-hs400 = <0x4>;
 	};
 
 	sdhci1: mmc@fa00000 {
-- 
GitLab


From 3f6a57ee8544ec3982f8a3cbcbf4aea7d47eb9ec Mon Sep 17 00:00:00 2001
From: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Thu, 16 Jun 2022 16:13:20 +0200
Subject: [PATCH 0786/1731] igb: fix a use-after-free issue in
 igb_clean_tx_ring

Fix the following use-after-free bug in igb_clean_tx_ring routine when
the NIC is running in XDP mode. The issue can be triggered redirecting
traffic into the igb NIC and then closing the device while the traffic
is flowing.

[   73.322719] CPU: 1 PID: 487 Comm: xdp_redirect Not tainted 5.18.3-apu2 #9
[   73.330639] Hardware name: PC Engines APU2/APU2, BIOS 4.0.7 02/28/2017
[   73.337434] RIP: 0010:refcount_warn_saturate+0xa7/0xf0
[   73.362283] RSP: 0018:ffffc9000081f798 EFLAGS: 00010282
[   73.367761] RAX: 0000000000000000 RBX: ffffc90000420f80 RCX: 0000000000000000
[   73.375200] RDX: ffff88811ad22d00 RSI: ffff88811ad171e0 RDI: ffff88811ad171e0
[   73.382590] RBP: 0000000000000900 R08: ffffffff82298f28 R09: 0000000000000058
[   73.390008] R10: 0000000000000219 R11: ffffffff82280f40 R12: 0000000000000090
[   73.397356] R13: ffff888102343a40 R14: ffff88810359e0e4 R15: 0000000000000000
[   73.404806] FS:  00007ff38d31d740(0000) GS:ffff88811ad00000(0000) knlGS:0000000000000000
[   73.413129] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[   73.419096] CR2: 000055cff35f13f8 CR3: 0000000106391000 CR4: 00000000000406e0
[   73.426565] Call Trace:
[   73.429087]  <TASK>
[   73.431314]  igb_clean_tx_ring+0x43/0x140 [igb]
[   73.436002]  igb_down+0x1d7/0x220 [igb]
[   73.439974]  __igb_close+0x3c/0x120 [igb]
[   73.444118]  igb_xdp+0x10c/0x150 [igb]
[   73.447983]  ? igb_pci_sriov_configure+0x70/0x70 [igb]
[   73.453362]  dev_xdp_install+0xda/0x110
[   73.457371]  dev_xdp_attach+0x1da/0x550
[   73.461369]  do_setlink+0xfd0/0x10f0
[   73.465166]  ? __nla_validate_parse+0x89/0xc70
[   73.469714]  rtnl_setlink+0x11a/0x1e0
[   73.473547]  rtnetlink_rcv_msg+0x145/0x3d0
[   73.477709]  ? rtnl_calcit.isra.0+0x130/0x130
[   73.482258]  netlink_rcv_skb+0x8d/0x110
[   73.486229]  netlink_unicast+0x230/0x340
[   73.490317]  netlink_sendmsg+0x215/0x470
[   73.494395]  __sys_sendto+0x179/0x190
[   73.498268]  ? move_addr_to_user+0x37/0x70
[   73.502547]  ? __sys_getsockname+0x84/0xe0
[   73.506853]  ? netlink_setsockopt+0x1c1/0x4a0
[   73.511349]  ? __sys_setsockopt+0xc8/0x1d0
[   73.515636]  __x64_sys_sendto+0x20/0x30
[   73.519603]  do_syscall_64+0x3b/0x80
[   73.523399]  entry_SYSCALL_64_after_hwframe+0x44/0xae
[   73.528712] RIP: 0033:0x7ff38d41f20c
[   73.551866] RSP: 002b:00007fff3b945a68 EFLAGS: 00000246 ORIG_RAX: 000000000000002c
[   73.559640] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007ff38d41f20c
[   73.567066] RDX: 0000000000000034 RSI: 00007fff3b945b30 RDI: 0000000000000003
[   73.574457] RBP: 0000000000000003 R08: 0000000000000000 R09: 0000000000000000
[   73.581852] R10: 0000000000000000 R11: 0000000000000246 R12: 00007fff3b945ab0
[   73.589179] R13: 0000000000000000 R14: 0000000000000003 R15: 00007fff3b945b30
[   73.596545]  </TASK>
[   73.598842] ---[ end trace 0000000000000000 ]---

Fixes: 9cbc948b5a20c ("igb: add XDP support")
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Reviewed-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Acked-by: Jesper Dangaard Brouer <brouer@redhat.com>
Link: https://lore.kernel.org/r/e5c01d549dc37bff18e46aeabd6fb28a7bcf84be.1655388571.git.lorenzo@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/ethernet/intel/igb/igb_main.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c
index 68be2976f539f..1c26bec7d6fa7 100644
--- a/drivers/net/ethernet/intel/igb/igb_main.c
+++ b/drivers/net/ethernet/intel/igb/igb_main.c
@@ -4819,8 +4819,11 @@ static void igb_clean_tx_ring(struct igb_ring *tx_ring)
 	while (i != tx_ring->next_to_use) {
 		union e1000_adv_tx_desc *eop_desc, *tx_desc;
 
-		/* Free all the Tx ring sk_buffs */
-		dev_kfree_skb_any(tx_buffer->skb);
+		/* Free all the Tx ring sk_buffs or xdp frames */
+		if (tx_buffer->type == IGB_TYPE_SKB)
+			dev_kfree_skb_any(tx_buffer->skb);
+		else
+			xdp_return_frame(tx_buffer->xdpf);
 
 		/* unmap skb header data */
 		dma_unmap_single(tx_ring->dev,
-- 
GitLab


From 7a9214f3d88cfdb099f3896e102a306b316d8707 Mon Sep 17 00:00:00 2001
From: Jay Vosburgh <jay.vosburgh@canonical.com>
Date: Thu, 16 Jun 2022 12:32:40 -0700
Subject: [PATCH 0787/1731] bonding: ARP monitor spams NETDEV_NOTIFY_PEERS
 notifiers

The bonding ARP monitor fails to decrement send_peer_notif, the
number of peer notifications (gratuitous ARP or ND) to be sent. This
results in a continuous series of notifications.

Correct this by decrementing the counter for each notification.

Reported-by: Jonathan Toppins <jtoppins@redhat.com>
Signed-off-by: Jay Vosburgh <jay.vosburgh@canonical.com>
Fixes: b0929915e035 ("bonding: Fix RTNL: assertion failed at net/core/rtnetlink.c for ab arp monitor")
Link: https://lore.kernel.org/netdev/b2fd4147-8f50-bebd-963a-1a3e8d1d9715@redhat.com/
Tested-by: Jonathan Toppins <jtoppins@redhat.com>
Reviewed-by: Jonathan Toppins <jtoppins@redhat.com>
Link: https://lore.kernel.org/r/9400.1655407960@famine
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/bonding/bond_main.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
index f85372adf0426..6ba4c83fe5fc0 100644
--- a/drivers/net/bonding/bond_main.c
+++ b/drivers/net/bonding/bond_main.c
@@ -3684,9 +3684,11 @@ re_arm:
 		if (!rtnl_trylock())
 			return;
 
-		if (should_notify_peers)
+		if (should_notify_peers) {
+			bond->send_peer_notif--;
 			call_netdevice_notifiers(NETDEV_NOTIFY_PEERS,
 						 bond->dev);
+		}
 		if (should_notify_rtnl) {
 			bond_slave_state_notify(bond);
 			bond_slave_link_notify(bond);
-- 
GitLab


From a3bb7b63813f674fb62bac321cdd897cc62de094 Mon Sep 17 00:00:00 2001
From: Ivan Vecera <ivecera@redhat.com>
Date: Thu, 16 Jun 2022 18:08:55 +0200
Subject: [PATCH 0788/1731] ethtool: Fix get module eeprom fallback

Function fallback_set_params() checks if the module type returned
by a driver is ETH_MODULE_SFF_8079 and in this case it assumes
that buffer returns a concatenated content of page  A0h and A2h.
The check is wrong because the correct type is ETH_MODULE_SFF_8472.

Fixes: 96d971e307cc ("ethtool: Add fallback to get_module_eeprom from netlink command")
Signed-off-by: Ivan Vecera <ivecera@redhat.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Link: https://lore.kernel.org/r/20220616160856.3623273-1-ivecera@redhat.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/ethtool/eeprom.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/net/ethtool/eeprom.c b/net/ethtool/eeprom.c
index 7e6b37a54add3..1c94bb8ea03f2 100644
--- a/net/ethtool/eeprom.c
+++ b/net/ethtool/eeprom.c
@@ -36,7 +36,7 @@ static int fallback_set_params(struct eeprom_req_info *request,
 	if (request->page)
 		offset = request->page * ETH_MODULE_EEPROM_PAGE_LEN + offset;
 
-	if (modinfo->type == ETH_MODULE_SFF_8079 &&
+	if (modinfo->type == ETH_MODULE_SFF_8472 &&
 	    request->i2c_address == 0x51)
 		offset += ETH_MODULE_EEPROM_PAGE_LEN * 2;
 
-- 
GitLab


From a2b1a5d40bd12b44322c2ccd40bb0ec1699708b6 Mon Sep 17 00:00:00 2001
From: Peilin Ye <peilin.ye@bytedance.com>
Date: Thu, 16 Jun 2022 16:43:36 -0700
Subject: [PATCH 0789/1731] net/sched: sch_netem: Fix arithmetic in
 netem_dump() for 32-bit platforms

As reported by Yuming, currently tc always show a latency of UINT_MAX
for netem Qdisc's on 32-bit platforms:

    $ tc qdisc add dev dummy0 root netem latency 100ms
    $ tc qdisc show dev dummy0
    qdisc netem 8001: root refcnt 2 limit 1000 delay 275s  275s
                                               ^^^^^^^^^^^^^^^^

Let us take a closer look at netem_dump():

        qopt.latency = min_t(psched_tdiff_t, PSCHED_NS2TICKS(q->latency,
                             UINT_MAX);

qopt.latency is __u32, psched_tdiff_t is signed long,
(psched_tdiff_t)(UINT_MAX) is negative for 32-bit platforms, so
qopt.latency is always UINT_MAX.

Fix it by using psched_time_t (u64) instead.

Note: confusingly, users have two ways to specify 'latency':

  1. normally, via '__u32 latency' in struct tc_netem_qopt;
  2. via the TCA_NETEM_LATENCY64 attribute, which is s64.

For the second case, theoretically 'latency' could be negative.  This
patch ignores that corner case, since it is broken (i.e. assigning a
negative s64 to __u32) anyways, and should be handled separately.

Thanks Ted Lin for the analysis [1] .

[1] https://github.com/raspberrypi/linux/issues/3512

Reported-by: Yuming Chen <chenyuming.junnan@bytedance.com>
Fixes: 112f9cb65643 ("netem: convert to qdisc_watchdog_schedule_ns")
Reviewed-by: Cong Wang <cong.wang@bytedance.com>
Signed-off-by: Peilin Ye <peilin.ye@bytedance.com>
Acked-by: Stephen Hemminger <stephen@networkplumber.org>
Link: https://lore.kernel.org/r/20220616234336.2443-1-yepeilin.cs@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/sched/sch_netem.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/net/sched/sch_netem.c b/net/sched/sch_netem.c
index ed4ccef5d6a82..5449ed114e406 100644
--- a/net/sched/sch_netem.c
+++ b/net/sched/sch_netem.c
@@ -1146,9 +1146,9 @@ static int netem_dump(struct Qdisc *sch, struct sk_buff *skb)
 	struct tc_netem_rate rate;
 	struct tc_netem_slot slot;
 
-	qopt.latency = min_t(psched_tdiff_t, PSCHED_NS2TICKS(q->latency),
+	qopt.latency = min_t(psched_time_t, PSCHED_NS2TICKS(q->latency),
 			     UINT_MAX);
-	qopt.jitter = min_t(psched_tdiff_t, PSCHED_NS2TICKS(q->jitter),
+	qopt.jitter = min_t(psched_time_t, PSCHED_NS2TICKS(q->jitter),
 			    UINT_MAX);
 	qopt.limit = q->limit;
 	qopt.loss = q->loss;
-- 
GitLab


From 3c7a52217a8c1e674a9e15b71a7239d71a4d9cfd Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Sat, 18 Jun 2022 09:11:18 -0700
Subject: [PATCH 0790/1731] drm/msm: Drop update_fences()

I noticed while looking at some traces, that we could miss calls to
msm_update_fence(), as the irq could have raced with retire_submits()
which could have already popped the last submit on a ring out of the
queue of in-flight submits.  But walking the list of submits in the
irq handler isn't really needed, as dma_fence_is_signaled() will dtrt.
So lets just drop it entirely.

v2: use spin_lock_irqsave/restore as we are no longer protected by the
    spin_lock_irqsave/restore() in update_fences()

Reported-by: Steev Klimaszewski <steev@kali.org>
Fixes: 95d1deb02a9c ("drm/msm/gem: Add fenced vma unpin")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Patchwork: https://patchwork.freedesktop.org/patch/490136/
Link: https://lore.kernel.org/r/20220618161120.3451993-1-robdclark@gmail.com
---
 drivers/gpu/drm/msm/msm_fence.c |  8 +++++---
 drivers/gpu/drm/msm/msm_gpu.c   | 22 ++--------------------
 2 files changed, 7 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_fence.c b/drivers/gpu/drm/msm/msm_fence.c
index 3df255402a33c..38e3323bc2324 100644
--- a/drivers/gpu/drm/msm/msm_fence.c
+++ b/drivers/gpu/drm/msm/msm_fence.c
@@ -46,12 +46,14 @@ bool msm_fence_completed(struct msm_fence_context *fctx, uint32_t fence)
 		(int32_t)(*fctx->fenceptr - fence) >= 0;
 }
 
-/* called from workqueue */
+/* called from irq handler and workqueue (in recover path) */
 void msm_update_fence(struct msm_fence_context *fctx, uint32_t fence)
 {
-	spin_lock(&fctx->spinlock);
+	unsigned long flags;
+
+	spin_lock_irqsave(&fctx->spinlock, flags);
 	fctx->completed_fence = max(fence, fctx->completed_fence);
-	spin_unlock(&fctx->spinlock);
+	spin_unlock_irqrestore(&fctx->spinlock, flags);
 }
 
 struct msm_fence {
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 244511f850444..cedc88cf80838 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -164,24 +164,6 @@ int msm_gpu_hw_init(struct msm_gpu *gpu)
 	return ret;
 }
 
-static void update_fences(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
-		uint32_t fence)
-{
-	struct msm_gem_submit *submit;
-	unsigned long flags;
-
-	spin_lock_irqsave(&ring->submit_lock, flags);
-	list_for_each_entry(submit, &ring->submits, node) {
-		if (fence_after(submit->seqno, fence))
-			break;
-
-		msm_update_fence(submit->ring->fctx,
-			submit->hw_fence->seqno);
-		dma_fence_signal(submit->hw_fence);
-	}
-	spin_unlock_irqrestore(&ring->submit_lock, flags);
-}
-
 #ifdef CONFIG_DEV_COREDUMP
 static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset,
 		size_t count, void *data, size_t datalen)
@@ -438,7 +420,7 @@ static void recover_worker(struct kthread_work *work)
 		if (ring == cur_ring)
 			fence++;
 
-		update_fences(gpu, ring, fence);
+		msm_update_fence(ring->fctx, fence);
 	}
 
 	if (msm_gpu_active(gpu)) {
@@ -736,7 +718,7 @@ void msm_gpu_retire(struct msm_gpu *gpu)
 	int i;
 
 	for (i = 0; i < gpu->nr_rings; i++)
-		update_fences(gpu, gpu->rb[i], gpu->rb[i]->memptrs->fence);
+		msm_update_fence(gpu->rb[i]->fctx, gpu->rb[i]->memptrs->fence);
 
 	kthread_queue_work(gpu->worker, &gpu->retire_work);
 	update_sw_cntrs(gpu);
-- 
GitLab


From c8af219d18502c52319df8d4e3dcfe29a3ca31ab Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Sat, 18 Jun 2022 09:11:19 -0700
Subject: [PATCH 0791/1731] drm/msm: Don't overwrite hw fence in hw_init

Prior to the last commit, this could result in setting the GPU
written fence value back to an older value, if we had missed
updating completed_fence prior to suspend.  This was mostly
harmless as the GPU would eventually overwrite it again with
the correct value.  But we should just not do this.  Instead
just leave a sanity check that the fence looks plausible (in
case the GPU scribbled on memory).

Reported-by: Steev Klimaszewski <steev@kali.org>
Fixes: 95d1deb02a9c ("drm/msm/gem: Add fenced vma unpin")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Patchwork: https://patchwork.freedesktop.org/patch/490138/
Link: https://lore.kernel.org/r/20220618161120.3451993-2-robdclark@gmail.com
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 11 ++++++++---
 drivers/gpu/drm/msm/msm_gpu.c           |  2 +-
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index f944b69e2a258..efe9840e28fad 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -498,10 +498,15 @@ int adreno_hw_init(struct msm_gpu *gpu)
 
 		ring->cur = ring->start;
 		ring->next = ring->start;
-
-		/* reset completed fence seqno: */
-		ring->memptrs->fence = ring->fctx->completed_fence;
 		ring->memptrs->rptr = 0;
+
+		/* Detect and clean up an impossible fence, ie. if GPU managed
+		 * to scribble something invalid, we don't want that to confuse
+		 * us into mistakingly believing that submits have completed.
+		 */
+		if (fence_before(ring->fctx->last_fence, ring->memptrs->fence)) {
+			ring->memptrs->fence = ring->fctx->last_fence;
+		}
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index cedc88cf80838..c8cd9bfa3eebd 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -418,7 +418,7 @@ static void recover_worker(struct kthread_work *work)
 		 * one more to clear the faulting submit
 		 */
 		if (ring == cur_ring)
-			fence++;
+			ring->memptrs->fence = ++fence;
 
 		msm_update_fence(ring->fctx, fence);
 	}
-- 
GitLab


From b9cc4598607cb7f7eae5c75fc1e3209cd52ff5e0 Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Tue, 7 Jun 2022 15:08:38 +0400
Subject: [PATCH 0792/1731] drm/msm/mdp4: Fix refcount leak in
 mdp4_modeset_init_intf

of_graph_get_remote_node() returns remote device node pointer with
refcount incremented, we should use of_node_put() on it
when not need anymore.
Add missing of_node_put() to avoid refcount leak.

Fixes: 86418f90a4c1 ("drm: convert drivers to use of_graph_get_remote_node")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/488473/
Link: https://lore.kernel.org/r/20220607110841.53889-1-linmq006@gmail.com
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
index fb48c8c19ec3a..17cb1fc783795 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
@@ -216,6 +216,7 @@ static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms,
 		encoder = mdp4_lcdc_encoder_init(dev, panel_node);
 		if (IS_ERR(encoder)) {
 			DRM_DEV_ERROR(dev->dev, "failed to construct LCDC encoder\n");
+			of_node_put(panel_node);
 			return PTR_ERR(encoder);
 		}
 
@@ -225,6 +226,7 @@ static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms,
 		connector = mdp4_lvds_connector_init(dev, panel_node, encoder);
 		if (IS_ERR(connector)) {
 			DRM_DEV_ERROR(dev->dev, "failed to initialize LVDS connector\n");
+			of_node_put(panel_node);
 			return PTR_ERR(connector);
 		}
 
-- 
GitLab


From d80c3ba0ac247791a4ed7a0cd865a64906c8906a Mon Sep 17 00:00:00 2001
From: Kuogee Hsieh <quic_khsieh@quicinc.com>
Date: Mon, 6 Jun 2022 10:55:39 -0700
Subject: [PATCH 0793/1731] drm/msm/dp: check core_initialized before disable
 interrupts at dp_display_unbind()

During msm initialize phase, dp_display_unbind() will be called to undo
initializations had been done by dp_display_bind() previously if there is
error happen at msm_drm_bind. In this case, core_initialized flag had to
be check to make sure clocks is on before update DP controller register
to disable HPD interrupts. Otherwise system will crash due to below NOC
fatal error.

QTISECLIB [01f01a7ad]CNOC2 ERROR: ERRLOG0_LOW = 0x00061007
QTISECLIB [01f01a7ad]GEM_NOC ERROR: ERRLOG0_LOW = 0x00001007
QTISECLIB [01f0371a0]CNOC2 ERROR: ERRLOG0_HIGH = 0x00000003
QTISECLIB [01f055297]GEM_NOC ERROR: ERRLOG0_HIGH = 0x00000003
QTISECLIB [01f072beb]CNOC2 ERROR: ERRLOG1_LOW = 0x00000024
QTISECLIB [01f0914b8]GEM_NOC ERROR: ERRLOG1_LOW = 0x00000042
QTISECLIB [01f0ae639]CNOC2 ERROR: ERRLOG1_HIGH = 0x00004002
QTISECLIB [01f0cc73f]GEM_NOC ERROR: ERRLOG1_HIGH = 0x00004002
QTISECLIB [01f0ea092]CNOC2 ERROR: ERRLOG2_LOW = 0x0009020c
QTISECLIB [01f10895f]GEM_NOC ERROR: ERRLOG2_LOW = 0x0ae9020c
QTISECLIB [01f125ae1]CNOC2 ERROR: ERRLOG2_HIGH = 0x00000000
QTISECLIB [01f143be7]GEM_NOC ERROR: ERRLOG2_HIGH = 0x00000000
QTISECLIB [01f16153a]CNOC2 ERROR: ERRLOG3_LOW = 0x00000000
QTISECLIB [01f17fe07]GEM_NOC ERROR: ERRLOG3_LOW = 0x00000000
QTISECLIB [01f19cf89]CNOC2 ERROR: ERRLOG3_HIGH = 0x00000000
QTISECLIB [01f1bb08e]GEM_NOC ERROR: ERRLOG3_HIGH = 0x00000000
QTISECLIB [01f1d8a31]CNOC2 ERROR: SBM1 FAULTINSTATUS0_LOW = 0x00000002
QTISECLIB [01f1f72a4]GEM_NOC ERROR: SBM0 FAULTINSTATUS0_LOW = 0x00000001
QTISECLIB [01f21a217]CNOC3 ERROR: ERRLOG0_LOW = 0x00000006
QTISECLIB [01f23dfd3]NOC error fatal

changes in v2:
-- drop the first patch (drm/msm: enable msm irq after all initializations are done successfully at msm_drm_init()) since the problem had been fixed by other patch

Fixes: 570d3e5d28db ("drm/msm/dp: stop event kernel thread when DP unbind")
Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/488387/
Link: https://lore.kernel.org/r/1654538139-7450-1-git-send-email-quic_khsieh@quicinc.com
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/dp/dp_display.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index da5c03a8cc4c7..2b72639767405 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -309,7 +309,8 @@ static void dp_display_unbind(struct device *dev, struct device *master,
 	struct msm_drm_private *priv = dev_get_drvdata(master);
 
 	/* disable all HPD interrupts */
-	dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_INT_MASK, false);
+	if (dp->core_initialized)
+		dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_INT_MASK, false);
 
 	kthread_stop(dp->ev_tsk);
 
-- 
GitLab


From 2211e34a9d57973993b644c4a2c76086cb6ce7fd Mon Sep 17 00:00:00 2001
From: Abhinav Kumar <quic_abhinavk@quicinc.com>
Date: Thu, 16 Jun 2022 12:26:46 -0700
Subject: [PATCH 0794/1731] drm/msm/dpu: limit wb modes based on
 max_mixer_width

As explained in [1], using max_linewidth to limit the modes
does not seem to remove 4K modes on chipsets such as
sm8250 where the max_linewidth actually supports 4k.

This would have been alright if dual SSPP support was
present but otherwise fails the per SSPP bandwidth check.

The ideal way to implement this would be to filter out
the modes which will exceed the bandwidth check by computing
it.

But this would be an exhaustive solution till we have
dual SSPP support.

Let's instead use max_mixer_width to limit the modes.

max_mixer_width still remains 2560 on sm8250 so even if
the max_linewidth is 4096, the only way 4k modes could have
been supported is to have source split enabled on the SSPP.

Since source split support is not enabled yet in DPU driver,
enforce max_mixer_width as the upper limit on the modes.

[1] https://patchwork.freedesktop.org/patch/489662/

Fixes: e67dcecda06f ("drm/msm/dpu: limit writeback modes according to max_linewidth")
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/489893/
Link: https://lore.kernel.org/r/1655407606-21760-1-git-send-email-quic_abhinavk@quicinc.com
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c
index 399115e4e217f..2fd787079f9b0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c
@@ -11,7 +11,14 @@ static int dpu_wb_conn_get_modes(struct drm_connector *connector)
 	struct msm_drm_private *priv = dev->dev_private;
 	struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
 
-	return drm_add_modes_noedid(connector, dpu_kms->catalog->caps->max_linewidth,
+	/*
+	 * We should ideally be limiting the modes only to the maxlinewidth but
+	 * on some chipsets this will allow even 4k modes to be added which will
+	 * fail the per SSPP bandwidth checks. So, till we have dual-SSPP support
+	 * and source split support added lets limit the modes based on max_mixer_width
+	 * as 4K modes can then be supported.
+	 */
+	return drm_add_modes_noedid(connector, dpu_kms->catalog->caps->max_mixer_width,
 			dev->mode_config.max_height);
 }
 
-- 
GitLab


From a6e2af64a79afa7f1b29375b5231e840a84bb845 Mon Sep 17 00:00:00 2001
From: Kuogee Hsieh <quic_khsieh@quicinc.com>
Date: Thu, 16 Jun 2022 13:26:40 -0700
Subject: [PATCH 0795/1731] drm/msm/dp: force link training for display
 resolution change

Display resolution change is implemented through drm modeset. Older
modeset (resolution) has to be disabled first before newer modeset
(resolution) can be enabled. Display disable will turn off both
pixel clock and main link clock so that main link have to be
re-trained during display enable to have new video stream flow
again. At current implementation, display enable function manually
kicks up irq_hpd_handle which will read panel link status and start
link training if link status is not in sync state.

However, there is rare case that a particular panel links status keep
staying in sync for some period of time after main link had been shut
down previously at display disabled. In this case, main link retraining
will not be executed by irq_hdp_handle(). Hence video stream of newer
display resolution will fail to be transmitted to panel due to main
link is not in sync between host and panel.

This patch will bypass irq_hpd_handle() in favor of directly call
dp_ctrl_on_stream() to always perform link training in regardless of
main link status. So that no unexpected exception resolution change
failure cases will happen. Also this implementation are more efficient
than manual kicking off irq_hpd_handle function.

Changes in v2:
-- set force_link_train flag on DP only (is_edp == false)

Changes in v3:
-- revise commit  text
-- add Fixes tag

Changes in v4:
-- revise commit  text

Changes in v5:
-- fix spelling at commit text

Changes in v6:
-- split dp_ctrl_on_stream() for phy test case
-- revise commit text for modeset

Changes in v7:
-- drop 0 assignment at local variable (ret = 0)

Changes in v8:
-- add patch to remove pixel_rate from dp_ctrl

Changes in v9:
-- forward declare dp_ctrl_on_stream_phy_test_report()

Fixes: 62671d2ef24b ("drm/msm/dp: fixes wrong connection state caused by failure of link train")
Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/489895/
Link: https://lore.kernel.org/r/1655411200-7255-1-git-send-email-quic_khsieh@quicinc.com
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/dp/dp_ctrl.c    | 33 ++++++++++++++++++++++-------
 drivers/gpu/drm/msm/dp/dp_ctrl.h    |  2 +-
 drivers/gpu/drm/msm/dp/dp_display.c | 13 ++++++------
 3 files changed, 32 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index f3e333eff32db..f18588aecea2c 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -1533,6 +1533,8 @@ end:
 	return ret;
 }
 
+static int dp_ctrl_on_stream_phy_test_report(struct dp_ctrl *dp_ctrl);
+
 static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl)
 {
 	int ret = 0;
@@ -1556,7 +1558,7 @@ static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl)
 
 	ret = dp_ctrl_on_link(&ctrl->dp_ctrl);
 	if (!ret)
-		ret = dp_ctrl_on_stream(&ctrl->dp_ctrl);
+		ret = dp_ctrl_on_stream_phy_test_report(&ctrl->dp_ctrl);
 	else
 		DRM_ERROR("failed to enable DP link controller\n");
 
@@ -1812,7 +1814,27 @@ static int dp_ctrl_link_retrain(struct dp_ctrl_private *ctrl)
 	return dp_ctrl_setup_main_link(ctrl, &training_step);
 }
 
-int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl)
+static int dp_ctrl_on_stream_phy_test_report(struct dp_ctrl *dp_ctrl)
+{
+	int ret;
+	struct dp_ctrl_private *ctrl;
+
+	ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
+
+	ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
+
+	ret = dp_ctrl_enable_stream_clocks(ctrl);
+	if (ret) {
+		DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
+		return ret;
+	}
+
+	dp_ctrl_send_phy_test_pattern(ctrl);
+
+	return 0;
+}
+
+int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train)
 {
 	int ret = 0;
 	bool mainlink_ready = false;
@@ -1848,12 +1870,7 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl)
 		goto end;
 	}
 
-	if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
-		dp_ctrl_send_phy_test_pattern(ctrl);
-		return 0;
-	}
-
-	if (!dp_ctrl_channel_eq_ok(ctrl))
+	if (force_link_train || !dp_ctrl_channel_eq_ok(ctrl))
 		dp_ctrl_link_retrain(ctrl);
 
 	/* stop txing train pattern to end link training */
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h
index 0745fde01b45d..b563e2e3bfe5d 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.h
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h
@@ -21,7 +21,7 @@ struct dp_ctrl {
 };
 
 int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl);
-int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl);
+int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train);
 int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl);
 int dp_ctrl_off_link(struct dp_ctrl *dp_ctrl);
 int dp_ctrl_off(struct dp_ctrl *dp_ctrl);
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index 2b72639767405..a6117926a2742 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -873,7 +873,7 @@ static int dp_display_enable(struct dp_display_private *dp, u32 data)
 		return 0;
 	}
 
-	rc = dp_ctrl_on_stream(dp->ctrl);
+	rc = dp_ctrl_on_stream(dp->ctrl, data);
 	if (!rc)
 		dp_display->power_on = true;
 
@@ -1660,6 +1660,7 @@ void dp_bridge_enable(struct drm_bridge *drm_bridge)
 	int rc = 0;
 	struct dp_display_private *dp_display;
 	u32 state;
+	bool force_link_train = false;
 
 	dp_display = container_of(dp, struct dp_display_private, dp_display);
 	if (!dp_display->dp_mode.drm_mode.clock) {
@@ -1694,10 +1695,12 @@ void dp_bridge_enable(struct drm_bridge *drm_bridge)
 
 	state =  dp_display->hpd_state;
 
-	if (state == ST_DISPLAY_OFF)
+	if (state == ST_DISPLAY_OFF) {
 		dp_display_host_phy_init(dp_display);
+		force_link_train = true;
+	}
 
-	dp_display_enable(dp_display, 0);
+	dp_display_enable(dp_display, force_link_train);
 
 	rc = dp_display_post_enable(dp);
 	if (rc) {
@@ -1706,10 +1709,6 @@ void dp_bridge_enable(struct drm_bridge *drm_bridge)
 		dp_display_unprepare(dp);
 	}
 
-	/* manual kick off plug event to train link */
-	if (state == ST_DISPLAY_OFF)
-		dp_add_event(dp_display, EV_IRQ_HPD_INT, 0, 0);
-
 	/* completed connection */
 	dp_display->hpd_state = ST_CONNECTED;
 
-- 
GitLab


From 5d24968f5b7e00bae564b1646c3b9e0e3750aabe Mon Sep 17 00:00:00 2001
From: Shyam Prasad N <sprasad@microsoft.com>
Date: Tue, 14 Jun 2022 11:47:24 +0000
Subject: [PATCH 0796/1731] cifs: when a channel is not found for server, log
 its connection id

cifs_ses_get_chan_index gets the index for a given server pointer.
When a match is not found, we warn about a possible bug.
However, printing details about the non-matching server could be
more useful to debug here.

Signed-off-by: Shyam Prasad N <sprasad@microsoft.com>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/sess.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/fs/cifs/sess.c b/fs/cifs/sess.c
index 0bece97547d4b..d417de354d9d7 100644
--- a/fs/cifs/sess.c
+++ b/fs/cifs/sess.c
@@ -81,6 +81,9 @@ cifs_ses_get_chan_index(struct cifs_ses *ses,
 	}
 
 	/* If we didn't find the channel, it is likely a bug */
+	if (server)
+		cifs_dbg(VFS, "unable to get chan index for server: 0x%llx",
+			 server->conn_id);
 	WARN_ON(1);
 	return 0;
 }
-- 
GitLab


From a0117dc956429f2ede17b323046e1968d1849150 Mon Sep 17 00:00:00 2001
From: Liang He <windhl@126.com>
Date: Fri, 17 Jun 2022 20:44:32 +0800
Subject: [PATCH 0797/1731] xtensa: Fix refcount leak bug in time.c

In calibrate_ccount(), of_find_compatible_node() will return a node
pointer with refcount incremented. We should use of_node_put() when
it is not used anymore.

Cc: stable@vger.kernel.org
Signed-off-by: Liang He <windhl@126.com>
Message-Id: <20220617124432.4049006-1-windhl@126.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
 arch/xtensa/kernel/time.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/xtensa/kernel/time.c b/arch/xtensa/kernel/time.c
index e8ceb15286081..16b8a6273772c 100644
--- a/arch/xtensa/kernel/time.c
+++ b/arch/xtensa/kernel/time.c
@@ -154,6 +154,7 @@ static void __init calibrate_ccount(void)
 	cpu = of_find_compatible_node(NULL, NULL, "cdns,xtensa-cpu");
 	if (cpu) {
 		clk = of_clk_get(cpu, 0);
+		of_node_put(cpu);
 		if (!IS_ERR(clk)) {
 			ccount_freq = clk_get_rate(clk);
 			return;
-- 
GitLab


From 173940b3ae40114d4179c251a98ee039dc9cd5b3 Mon Sep 17 00:00:00 2001
From: Liang He <windhl@126.com>
Date: Fri, 17 Jun 2022 19:53:23 +0800
Subject: [PATCH 0798/1731] xtensa: xtfpga: Fix refcount leak bug in setup

In machine_setup(), of_find_compatible_node() will return a node
pointer with refcount incremented. We should use of_node_put() when
it is not used anymore.

Cc: stable@vger.kernel.org
Signed-off-by: Liang He <windhl@126.com>
Message-Id: <20220617115323.4046905-1-windhl@126.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
 arch/xtensa/platforms/xtfpga/setup.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/xtensa/platforms/xtfpga/setup.c b/arch/xtensa/platforms/xtfpga/setup.c
index 538e6748e85a7..c79c1d09ea863 100644
--- a/arch/xtensa/platforms/xtfpga/setup.c
+++ b/arch/xtensa/platforms/xtfpga/setup.c
@@ -133,6 +133,7 @@ static int __init machine_setup(void)
 
 	if ((eth = of_find_compatible_node(eth, NULL, "opencores,ethoc")))
 		update_local_mac(eth);
+	of_node_put(eth);
 	return 0;
 }
 arch_initcall(machine_setup);
-- 
GitLab


From 9b6641dd95a0c441b277dd72ba22fed8d61f76ad Mon Sep 17 00:00:00 2001
From: Ye Bin <yebin10@huawei.com>
Date: Wed, 25 May 2022 09:29:04 +0800
Subject: [PATCH 0799/1731] ext4: fix super block checksum incorrect after
 mount
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

We got issue as follows:
[home]# mount  /dev/sda  test
EXT4-fs (sda): warning: mounting fs with errors, running e2fsck is recommended
[home]# dmesg
EXT4-fs (sda): warning: mounting fs with errors, running e2fsck is recommended
EXT4-fs (sda): Errors on filesystem, clearing orphan list.
EXT4-fs (sda): recovery complete
EXT4-fs (sda): mounted filesystem with ordered data mode. Quota mode: none.
[home]# debugfs /dev/sda
debugfs 1.46.5 (30-Dec-2021)
Checksum errors in superblock!  Retrying...

Reason is ext4_orphan_cleanup will reset ‘s_last_orphan’ but not update
super block checksum.

To solve above issue, defer update super block checksum after
ext4_orphan_cleanup.

Signed-off-by: Ye Bin <yebin10@huawei.com>
Cc: stable@kernel.org
Reviewed-by: Jan Kara <jack@suse.cz>
Reviewed-by: Ritesh Harjani <ritesh.list@gmail.com>
Link: https://lore.kernel.org/r/20220525012904.1604737-1-yebin10@huawei.com
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
---
 fs/ext4/super.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/fs/ext4/super.c b/fs/ext4/super.c
index b2ecae8adbfc0..13d562d112355 100644
--- a/fs/ext4/super.c
+++ b/fs/ext4/super.c
@@ -5302,14 +5302,6 @@ no_journal:
 		err = percpu_counter_init(&sbi->s_freeinodes_counter, freei,
 					  GFP_KERNEL);
 	}
-	/*
-	 * Update the checksum after updating free space/inode
-	 * counters.  Otherwise the superblock can have an incorrect
-	 * checksum in the buffer cache until it is written out and
-	 * e2fsprogs programs trying to open a file system immediately
-	 * after it is mounted can fail.
-	 */
-	ext4_superblock_csum_set(sb);
 	if (!err)
 		err = percpu_counter_init(&sbi->s_dirs_counter,
 					  ext4_count_dirs(sb), GFP_KERNEL);
@@ -5367,6 +5359,14 @@ no_journal:
 	EXT4_SB(sb)->s_mount_state |= EXT4_ORPHAN_FS;
 	ext4_orphan_cleanup(sb, es);
 	EXT4_SB(sb)->s_mount_state &= ~EXT4_ORPHAN_FS;
+	/*
+	 * Update the checksum after updating free space/inode counters and
+	 * ext4_orphan_cleanup. Otherwise the superblock can have an incorrect
+	 * checksum in the buffer cache until it is written out and
+	 * e2fsprogs programs trying to open a file system immediately
+	 * after it is mounted can fail.
+	 */
+	ext4_superblock_csum_set(sb);
 	if (needs_recovery) {
 		ext4_msg(sb, KERN_INFO, "recovery complete");
 		err = ext4_mark_recovery_complete(sb, es);
-- 
GitLab


From 4efd9f0d120c55b08852ee5605dbb02a77089a5d Mon Sep 17 00:00:00 2001
From: Shuqi Zhang <zhangshuqi3@huawei.com>
Date: Wed, 25 May 2022 11:01:20 +0800
Subject: [PATCH 0800/1731] ext4: use kmemdup() to replace kmalloc + memcpy

Replace kmalloc + memcpy with kmemdup()

Signed-off-by: Shuqi Zhang <zhangshuqi3@huawei.com>
Reviewed-by: Ritesh Harjani <ritesh.list@gmail.com>
Link: https://lore.kernel.org/r/20220525030120.803330-1-zhangshuqi3@huawei.com
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
---
 fs/ext4/xattr.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/fs/ext4/xattr.c b/fs/ext4/xattr.c
index 0423253490986..564e28a1aa942 100644
--- a/fs/ext4/xattr.c
+++ b/fs/ext4/xattr.c
@@ -1895,11 +1895,10 @@ ext4_xattr_block_set(handle_t *handle, struct inode *inode,
 
 			unlock_buffer(bs->bh);
 			ea_bdebug(bs->bh, "cloning");
-			s->base = kmalloc(bs->bh->b_size, GFP_NOFS);
+			s->base = kmemdup(BHDR(bs->bh), bs->bh->b_size, GFP_NOFS);
 			error = -ENOMEM;
 			if (s->base == NULL)
 				goto cleanup;
-			memcpy(s->base, BHDR(bs->bh), bs->bh->b_size);
 			s->first = ENTRY(header(s->base)+1);
 			header(s->base)->h_refcount = cpu_to_le32(1);
 			s->here = ENTRY(s->base + offset);
-- 
GitLab


From 85456054e10b0247920b00422d27365e689d9f4a Mon Sep 17 00:00:00 2001
From: Eric Biggers <ebiggers@google.com>
Date: Wed, 25 May 2022 21:04:12 -0700
Subject: [PATCH 0801/1731] ext4: fix up test_dummy_encryption handling for new
 mount API

Since ext4 was converted to the new mount API, the test_dummy_encryption
mount option isn't being handled entirely correctly, because the needed
fscrypt_set_test_dummy_encryption() helper function combines
parsing/checking/applying into one function.  That doesn't work well
with the new mount API, which split these into separate steps.

This was sort of okay anyway, due to the parsing logic that was copied
from fscrypt_set_test_dummy_encryption() into ext4_parse_param(),
combined with an additional check in ext4_check_test_dummy_encryption().
However, these overlooked the case of changing the value of
test_dummy_encryption on remount, which isn't allowed but ext4 wasn't
detecting until ext4_apply_options() when it's too late to fail.
Another bug is that if test_dummy_encryption was specified multiple
times with an argument, memory was leaked.

Fix this up properly by using the new helper functions that allow
splitting up the parse/check/apply steps for test_dummy_encryption.

Fixes: cebe85d570cf ("ext4: switch to the new mount api")
Signed-off-by: Eric Biggers <ebiggers@google.com>
Link: https://lore.kernel.org/r/20220526040412.173025-1-ebiggers@kernel.org
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
---
 fs/ext4/super.c | 134 +++++++++++++++++++++++++-----------------------
 1 file changed, 71 insertions(+), 63 deletions(-)

diff --git a/fs/ext4/super.c b/fs/ext4/super.c
index 13d562d112355..845f2f8aee5f9 100644
--- a/fs/ext4/super.c
+++ b/fs/ext4/super.c
@@ -87,7 +87,7 @@ static struct inode *ext4_get_journal_inode(struct super_block *sb,
 static int ext4_validate_options(struct fs_context *fc);
 static int ext4_check_opt_consistency(struct fs_context *fc,
 				      struct super_block *sb);
-static int ext4_apply_options(struct fs_context *fc, struct super_block *sb);
+static void ext4_apply_options(struct fs_context *fc, struct super_block *sb);
 static int ext4_parse_param(struct fs_context *fc, struct fs_parameter *param);
 static int ext4_get_tree(struct fs_context *fc);
 static int ext4_reconfigure(struct fs_context *fc);
@@ -1870,31 +1870,12 @@ ext4_sb_read_encoding(const struct ext4_super_block *es)
 }
 #endif
 
-static int ext4_set_test_dummy_encryption(struct super_block *sb, char *arg)
-{
-#ifdef CONFIG_FS_ENCRYPTION
-	struct ext4_sb_info *sbi = EXT4_SB(sb);
-	int err;
-
-	err = fscrypt_set_test_dummy_encryption(sb, arg,
-						&sbi->s_dummy_enc_policy);
-	if (err) {
-		ext4_msg(sb, KERN_WARNING,
-			 "Error while setting test dummy encryption [%d]", err);
-		return err;
-	}
-	ext4_msg(sb, KERN_WARNING, "Test dummy encryption mode enabled");
-#endif
-	return 0;
-}
-
 #define EXT4_SPEC_JQUOTA			(1 <<  0)
 #define EXT4_SPEC_JQFMT				(1 <<  1)
 #define EXT4_SPEC_DATAJ				(1 <<  2)
 #define EXT4_SPEC_SB_BLOCK			(1 <<  3)
 #define EXT4_SPEC_JOURNAL_DEV			(1 <<  4)
 #define EXT4_SPEC_JOURNAL_IOPRIO		(1 <<  5)
-#define EXT4_SPEC_DUMMY_ENCRYPTION		(1 <<  6)
 #define EXT4_SPEC_s_want_extra_isize		(1 <<  7)
 #define EXT4_SPEC_s_max_batch_time		(1 <<  8)
 #define EXT4_SPEC_s_min_batch_time		(1 <<  9)
@@ -1911,7 +1892,7 @@ static int ext4_set_test_dummy_encryption(struct super_block *sb, char *arg)
 
 struct ext4_fs_context {
 	char		*s_qf_names[EXT4_MAXQUOTAS];
-	char		*test_dummy_enc_arg;
+	struct fscrypt_dummy_policy dummy_enc_policy;
 	int		s_jquota_fmt;	/* Format of quota to use */
 #ifdef CONFIG_EXT4_DEBUG
 	int s_fc_debug_max_replay;
@@ -1953,7 +1934,7 @@ static void ext4_fc_free(struct fs_context *fc)
 	for (i = 0; i < EXT4_MAXQUOTAS; i++)
 		kfree(ctx->s_qf_names[i]);
 
-	kfree(ctx->test_dummy_enc_arg);
+	fscrypt_free_dummy_policy(&ctx->dummy_enc_policy);
 	kfree(ctx);
 }
 
@@ -2029,6 +2010,29 @@ static int unnote_qf_name(struct fs_context *fc, int qtype)
 }
 #endif
 
+static int ext4_parse_test_dummy_encryption(const struct fs_parameter *param,
+					    struct ext4_fs_context *ctx)
+{
+	int err;
+
+	if (!IS_ENABLED(CONFIG_FS_ENCRYPTION)) {
+		ext4_msg(NULL, KERN_WARNING,
+			 "test_dummy_encryption option not supported");
+		return -EINVAL;
+	}
+	err = fscrypt_parse_test_dummy_encryption(param,
+						  &ctx->dummy_enc_policy);
+	if (err == -EINVAL) {
+		ext4_msg(NULL, KERN_WARNING,
+			 "Value of option \"%s\" is unrecognized", param->key);
+	} else if (err == -EEXIST) {
+		ext4_msg(NULL, KERN_WARNING,
+			 "Conflicting test_dummy_encryption options");
+		return -EINVAL;
+	}
+	return err;
+}
+
 #define EXT4_SET_CTX(name)						\
 static inline void ctx_set_##name(struct ext4_fs_context *ctx,		\
 				  unsigned long flag)			\
@@ -2291,29 +2295,7 @@ static int ext4_parse_param(struct fs_context *fc, struct fs_parameter *param)
 		ctx->spec |= EXT4_SPEC_JOURNAL_IOPRIO;
 		return 0;
 	case Opt_test_dummy_encryption:
-#ifdef CONFIG_FS_ENCRYPTION
-		if (param->type == fs_value_is_flag) {
-			ctx->spec |= EXT4_SPEC_DUMMY_ENCRYPTION;
-			ctx->test_dummy_enc_arg = NULL;
-			return 0;
-		}
-		if (*param->string &&
-		    !(!strcmp(param->string, "v1") ||
-		      !strcmp(param->string, "v2"))) {
-			ext4_msg(NULL, KERN_WARNING,
-				 "Value of option \"%s\" is unrecognized",
-				 param->key);
-			return -EINVAL;
-		}
-		ctx->spec |= EXT4_SPEC_DUMMY_ENCRYPTION;
-		ctx->test_dummy_enc_arg = kmemdup_nul(param->string, param->size,
-						      GFP_KERNEL);
-		return 0;
-#else
-		ext4_msg(NULL, KERN_WARNING,
-			 "test_dummy_encryption option not supported");
-		return -EINVAL;
-#endif
+		return ext4_parse_test_dummy_encryption(param, ctx);
 	case Opt_dax:
 	case Opt_dax_type:
 #ifdef CONFIG_FS_DAX
@@ -2504,7 +2486,8 @@ parse_failed:
 	if (s_ctx->spec & EXT4_SPEC_JOURNAL_IOPRIO)
 		m_ctx->journal_ioprio = s_ctx->journal_ioprio;
 
-	ret = ext4_apply_options(fc, sb);
+	ext4_apply_options(fc, sb);
+	ret = 0;
 
 out_free:
 	if (fc) {
@@ -2673,11 +2656,11 @@ err_jquota_specified:
 static int ext4_check_test_dummy_encryption(const struct fs_context *fc,
 					    struct super_block *sb)
 {
-#ifdef CONFIG_FS_ENCRYPTION
 	const struct ext4_fs_context *ctx = fc->fs_private;
 	const struct ext4_sb_info *sbi = EXT4_SB(sb);
+	int err;
 
-	if (!(ctx->spec & EXT4_SPEC_DUMMY_ENCRYPTION))
+	if (!fscrypt_is_dummy_policy_set(&ctx->dummy_enc_policy))
 		return 0;
 
 	if (!ext4_has_feature_encrypt(sb)) {
@@ -2691,14 +2674,46 @@ static int ext4_check_test_dummy_encryption(const struct fs_context *fc,
 	 * needed to allow it to be set or changed during remount.  We do allow
 	 * it to be specified during remount, but only if there is no change.
 	 */
-	if (fc->purpose == FS_CONTEXT_FOR_RECONFIGURE &&
-	    !sbi->s_dummy_enc_policy.policy) {
+	if (fc->purpose == FS_CONTEXT_FOR_RECONFIGURE) {
+		if (fscrypt_dummy_policies_equal(&sbi->s_dummy_enc_policy,
+						 &ctx->dummy_enc_policy))
+			return 0;
 		ext4_msg(NULL, KERN_WARNING,
-			 "Can't set test_dummy_encryption on remount");
+			 "Can't set or change test_dummy_encryption on remount");
 		return -EINVAL;
 	}
-#endif /* CONFIG_FS_ENCRYPTION */
-	return 0;
+	/* Also make sure s_mount_opts didn't contain a conflicting value. */
+	if (fscrypt_is_dummy_policy_set(&sbi->s_dummy_enc_policy)) {
+		if (fscrypt_dummy_policies_equal(&sbi->s_dummy_enc_policy,
+						 &ctx->dummy_enc_policy))
+			return 0;
+		ext4_msg(NULL, KERN_WARNING,
+			 "Conflicting test_dummy_encryption options");
+		return -EINVAL;
+	}
+	/*
+	 * fscrypt_add_test_dummy_key() technically changes the super_block, so
+	 * technically it should be delayed until ext4_apply_options() like the
+	 * other changes.  But since we never get here for remounts (see above),
+	 * and this is the last chance to report errors, we do it here.
+	 */
+	err = fscrypt_add_test_dummy_key(sb, &ctx->dummy_enc_policy);
+	if (err)
+		ext4_msg(NULL, KERN_WARNING,
+			 "Error adding test dummy encryption key [%d]", err);
+	return err;
+}
+
+static void ext4_apply_test_dummy_encryption(struct ext4_fs_context *ctx,
+					     struct super_block *sb)
+{
+	if (!fscrypt_is_dummy_policy_set(&ctx->dummy_enc_policy) ||
+	    /* if already set, it was already verified to be the same */
+	    fscrypt_is_dummy_policy_set(&EXT4_SB(sb)->s_dummy_enc_policy))
+		return;
+	EXT4_SB(sb)->s_dummy_enc_policy = ctx->dummy_enc_policy;
+	memset(&ctx->dummy_enc_policy, 0, sizeof(ctx->dummy_enc_policy));
+	ext4_msg(sb, KERN_WARNING, "Test dummy encryption mode enabled");
 }
 
 static int ext4_check_opt_consistency(struct fs_context *fc,
@@ -2785,11 +2800,10 @@ fail_dax_change_remount:
 	return ext4_check_quota_consistency(fc, sb);
 }
 
-static int ext4_apply_options(struct fs_context *fc, struct super_block *sb)
+static void ext4_apply_options(struct fs_context *fc, struct super_block *sb)
 {
 	struct ext4_fs_context *ctx = fc->fs_private;
 	struct ext4_sb_info *sbi = fc->s_fs_info;
-	int ret = 0;
 
 	sbi->s_mount_opt &= ~ctx->mask_s_mount_opt;
 	sbi->s_mount_opt |= ctx->vals_s_mount_opt;
@@ -2825,11 +2839,7 @@ static int ext4_apply_options(struct fs_context *fc, struct super_block *sb)
 #endif
 
 	ext4_apply_quota_options(fc, sb);
-
-	if (ctx->spec & EXT4_SPEC_DUMMY_ENCRYPTION)
-		ret = ext4_set_test_dummy_encryption(sb, ctx->test_dummy_enc_arg);
-
-	return ret;
+	ext4_apply_test_dummy_encryption(ctx, sb);
 }
 
 
@@ -4552,9 +4562,7 @@ static int __ext4_fill_super(struct fs_context *fc, struct super_block *sb)
 	if (err < 0)
 		goto failed_mount;
 
-	err = ext4_apply_options(fc, sb);
-	if (err < 0)
-		goto failed_mount;
+	ext4_apply_options(fc, sb);
 
 #if IS_ENABLED(CONFIG_UNICODE)
 	if (ext4_has_feature_casefold(sb) && !sb->s_encoding) {
-- 
GitLab


From a08f789d2ab5242c07e716baf9a835725046be89 Mon Sep 17 00:00:00 2001
From: Baokun Li <libaokun1@huawei.com>
Date: Sat, 28 May 2022 19:00:15 +0800
Subject: [PATCH 0802/1731] ext4: fix bug_on ext4_mb_use_inode_pa

Hulk Robot reported a BUG_ON:
==================================================================
kernel BUG at fs/ext4/mballoc.c:3211!
[...]
RIP: 0010:ext4_mb_mark_diskspace_used.cold+0x85/0x136f
[...]
Call Trace:
 ext4_mb_new_blocks+0x9df/0x5d30
 ext4_ext_map_blocks+0x1803/0x4d80
 ext4_map_blocks+0x3a4/0x1a10
 ext4_writepages+0x126d/0x2c30
 do_writepages+0x7f/0x1b0
 __filemap_fdatawrite_range+0x285/0x3b0
 file_write_and_wait_range+0xb1/0x140
 ext4_sync_file+0x1aa/0xca0
 vfs_fsync_range+0xfb/0x260
 do_fsync+0x48/0xa0
[...]
==================================================================

Above issue may happen as follows:
-------------------------------------
do_fsync
 vfs_fsync_range
  ext4_sync_file
   file_write_and_wait_range
    __filemap_fdatawrite_range
     do_writepages
      ext4_writepages
       mpage_map_and_submit_extent
        mpage_map_one_extent
         ext4_map_blocks
          ext4_mb_new_blocks
           ext4_mb_normalize_request
            >>> start + size <= ac->ac_o_ex.fe_logical
           ext4_mb_regular_allocator
            ext4_mb_simple_scan_group
             ext4_mb_use_best_found
              ext4_mb_new_preallocation
               ext4_mb_new_inode_pa
                ext4_mb_use_inode_pa
                 >>> set ac->ac_b_ex.fe_len <= 0
           ext4_mb_mark_diskspace_used
            >>> BUG_ON(ac->ac_b_ex.fe_len <= 0);

we can easily reproduce this problem with the following commands:
	`fallocate -l100M disk`
	`mkfs.ext4 -b 1024 -g 256 disk`
	`mount disk /mnt`
	`fsstress -d /mnt -l 0 -n 1000 -p 1`

The size must be smaller than or equal to EXT4_BLOCKS_PER_GROUP.
Therefore, "start + size <= ac->ac_o_ex.fe_logical" may occur
when the size is truncated. So start should be the start position of
the group where ac_o_ex.fe_logical is located after alignment.
In addition, when the value of fe_logical or EXT4_BLOCKS_PER_GROUP
is very large, the value calculated by start_off is more accurate.

Cc: stable@kernel.org
Fixes: cd648b8a8fd5 ("ext4: trim allocation requests to group size")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Baokun Li <libaokun1@huawei.com>
Reviewed-by: Ritesh Harjani <ritesh.list@gmail.com>
Link: https://lore.kernel.org/r/20220528110017.354175-2-libaokun1@huawei.com
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
---
 fs/ext4/mballoc.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c
index 9f12f29bc3468..4d3740fdff90f 100644
--- a/fs/ext4/mballoc.c
+++ b/fs/ext4/mballoc.c
@@ -4104,6 +4104,15 @@ ext4_mb_normalize_request(struct ext4_allocation_context *ac,
 	size = size >> bsbits;
 	start = start_off >> bsbits;
 
+	/*
+	 * For tiny groups (smaller than 8MB) the chosen allocation
+	 * alignment may be larger than group size. Make sure the
+	 * alignment does not move allocation to a different group which
+	 * makes mballoc fail assertions later.
+	 */
+	start = max(start, rounddown(ac->ac_o_ex.fe_logical,
+			(ext4_lblk_t)EXT4_BLOCKS_PER_GROUP(ac->ac_sb)));
+
 	/* don't cover already allocated blocks in selected range */
 	if (ar->pleft && start <= ar->lleft) {
 		size -= ar->lleft + 1 - start;
-- 
GitLab


From cf4ff938b47fc5c00b0ccce53a3b50eca9b32281 Mon Sep 17 00:00:00 2001
From: Baokun Li <libaokun1@huawei.com>
Date: Sat, 28 May 2022 19:00:16 +0800
Subject: [PATCH 0803/1731] ext4: correct the judgment of BUG in
 ext4_mb_normalize_request

ext4_mb_normalize_request() can move logical start of allocated blocks
to reduce fragmentation and better utilize preallocation. However logical
block requested as a start of allocation (ac->ac_o_ex.fe_logical) should
always be covered by allocated blocks so we should check that by
modifying and to or in the assertion.

Signed-off-by: Baokun Li <libaokun1@huawei.com>
Reviewed-by: Ritesh Harjani <ritesh.list@gmail.com>
Link: https://lore.kernel.org/r/20220528110017.354175-3-libaokun1@huawei.com
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
---
 fs/ext4/mballoc.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c
index 4d3740fdff90f..9e06334771a39 100644
--- a/fs/ext4/mballoc.c
+++ b/fs/ext4/mballoc.c
@@ -4185,7 +4185,22 @@ ext4_mb_normalize_request(struct ext4_allocation_context *ac,
 	}
 	rcu_read_unlock();
 
-	if (start + size <= ac->ac_o_ex.fe_logical &&
+	/*
+	 * In this function "start" and "size" are normalized for better
+	 * alignment and length such that we could preallocate more blocks.
+	 * This normalization is done such that original request of
+	 * ac->ac_o_ex.fe_logical & fe_len should always lie within "start" and
+	 * "size" boundaries.
+	 * (Note fe_len can be relaxed since FS block allocation API does not
+	 * provide gurantee on number of contiguous blocks allocation since that
+	 * depends upon free space left, etc).
+	 * In case of inode pa, later we use the allocated blocks
+	 * [pa_start + fe_logical - pa_lstart, fe_len/size] from the preallocated
+	 * range of goal/best blocks [start, size] to put it at the
+	 * ac_o_ex.fe_logical extent of this inode.
+	 * (See ext4_mb_use_inode_pa() for more details)
+	 */
+	if (start + size <= ac->ac_o_ex.fe_logical ||
 			start > ac->ac_o_ex.fe_logical) {
 		ext4_msg(ac->ac_sb, KERN_ERR,
 			 "start %lu, size %lu, fe_logical %lu",
-- 
GitLab


From bc75a6eb856cb1507fa907bf6c1eda91b3fef52f Mon Sep 17 00:00:00 2001
From: Ding Xiang <dingxiang@cmss.chinamobile.com>
Date: Mon, 30 May 2022 18:00:47 +0800
Subject: [PATCH 0804/1731] ext4: make variable "count" signed

Since dx_make_map() may return -EFSCORRUPTED now, so change "count" to
be a signed integer so we can correctly check for an error code returned
by dx_make_map().

Fixes: 46c116b920eb ("ext4: verify dir block before splitting it")
Cc: stable@kernel.org
Signed-off-by: Ding Xiang <dingxiang@cmss.chinamobile.com>
Link: https://lore.kernel.org/r/20220530100047.537598-1-dingxiang@cmss.chinamobile.com
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
---
 fs/ext4/namei.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/fs/ext4/namei.c b/fs/ext4/namei.c
index 47d0ca4c795b6..db4ba99d1cebe 100644
--- a/fs/ext4/namei.c
+++ b/fs/ext4/namei.c
@@ -1929,7 +1929,8 @@ static struct ext4_dir_entry_2 *do_split(handle_t *handle, struct inode *dir,
 			struct dx_hash_info *hinfo)
 {
 	unsigned blocksize = dir->i_sb->s_blocksize;
-	unsigned count, continued;
+	unsigned continued;
+	int count;
 	struct buffer_head *bh2;
 	ext4_lblk_t newblock;
 	u32 hash2;
-- 
GitLab


From b55c3cd102a6f48b90e61c44f7f3dda8c290c694 Mon Sep 17 00:00:00 2001
From: Zhang Yi <yi.zhang@huawei.com>
Date: Wed, 1 Jun 2022 17:27:17 +0800
Subject: [PATCH 0805/1731] ext4: add reserved GDT blocks check

We capture a NULL pointer issue when resizing a corrupt ext4 image which
is freshly clear resize_inode feature (not run e2fsck). It could be
simply reproduced by following steps. The problem is because of the
resize_inode feature was cleared, and it will convert the filesystem to
meta_bg mode in ext4_resize_fs(), but the es->s_reserved_gdt_blocks was
not reduced to zero, so could we mistakenly call reserve_backup_gdb()
and passing an uninitialized resize_inode to it when adding new group
descriptors.

 mkfs.ext4 /dev/sda 3G
 tune2fs -O ^resize_inode /dev/sda #forget to run requested e2fsck
 mount /dev/sda /mnt
 resize2fs /dev/sda 8G

 ========
 BUG: kernel NULL pointer dereference, address: 0000000000000028
 CPU: 19 PID: 3243 Comm: resize2fs Not tainted 5.18.0-rc7-00001-gfde086c5ebfd #748
 ...
 RIP: 0010:ext4_flex_group_add+0xe08/0x2570
 ...
 Call Trace:
  <TASK>
  ext4_resize_fs+0xbec/0x1660
  __ext4_ioctl+0x1749/0x24e0
  ext4_ioctl+0x12/0x20
  __x64_sys_ioctl+0xa6/0x110
  do_syscall_64+0x3b/0x90
  entry_SYSCALL_64_after_hwframe+0x44/0xae
 RIP: 0033:0x7f2dd739617b
 ========

The fix is simple, add a check in ext4_resize_begin() to make sure that
the es->s_reserved_gdt_blocks is zero when the resize_inode feature is
disabled.

Cc: stable@kernel.org
Signed-off-by: Zhang Yi <yi.zhang@huawei.com>
Reviewed-by: Ritesh Harjani <ritesh.list@gmail.com>
Reviewed-by: Jan Kara <jack@suse.cz>
Link: https://lore.kernel.org/r/20220601092717.763694-1-yi.zhang@huawei.com
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
---
 fs/ext4/resize.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/fs/ext4/resize.c b/fs/ext4/resize.c
index 90a941d20dfff..8b70a47012931 100644
--- a/fs/ext4/resize.c
+++ b/fs/ext4/resize.c
@@ -53,6 +53,16 @@ int ext4_resize_begin(struct super_block *sb)
 	if (!capable(CAP_SYS_RESOURCE))
 		return -EPERM;
 
+	/*
+	 * If the reserved GDT blocks is non-zero, the resize_inode feature
+	 * should always be set.
+	 */
+	if (EXT4_SB(sb)->s_es->s_reserved_gdt_blocks &&
+	    !ext4_has_feature_resize_inode(sb)) {
+		ext4_error(sb, "resize_inode disabled but reserved GDT blocks non-zero");
+		return -EFSCORRUPTED;
+	}
+
 	/*
 	 * If we are not using the primary superblock/GDT copy don't resize,
          * because the user tools have no way of handling this.  Probably a
-- 
GitLab


From 1f3ddff3755915a2b38de92d53508594de432d3d Mon Sep 17 00:00:00 2001
From: Xiang wangx <wangxiang@cdjrlc.com>
Date: Sun, 5 Jun 2022 17:15:03 +0800
Subject: [PATCH 0806/1731] ext4: fix a doubled word "need" in a comment

Signed-off-by: Xiang wangx <wangxiang@cdjrlc.com>
Link: https://lore.kernel.org/r/20220605091503.12513-1-wangxiang@cdjrlc.com
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
---
 fs/ext4/migrate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/ext4/migrate.c b/fs/ext4/migrate.c
index 7a5353a8cfd7b..42f590518b4ce 100644
--- a/fs/ext4/migrate.c
+++ b/fs/ext4/migrate.c
@@ -438,7 +438,7 @@ int ext4_ext_migrate(struct inode *inode)
 
 	/*
 	 * Worst case we can touch the allocation bitmaps and a block
-	 * group descriptor block.  We do need need to worry about
+	 * group descriptor block.  We do need to worry about
 	 * credits for modifying the quota inode.
 	 */
 	handle = ext4_journal_start(inode, EXT4_HT_MIGRATE,
-- 
GitLab


From a1016ba9f908d3d00b9483e2d9d5840ba744f122 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <festevam@denx.de>
Date: Tue, 7 Jun 2022 13:46:40 -0300
Subject: [PATCH 0807/1731] ARM: dts: imx7d-smegw01: Fix the SDIO description

usdhc2 is connected to a Wifi chip that is powered by a 3.3V supply.

Pass the "no-1-8-v" property to guarantee that no communication is
made at 1.8V.

While at it, also remove the unnecessary properties: "cap-sd-highspeed",
"sd-uhs-ddr50", and "mmc-ddr-1_8v".

Fixes: 9ac0ae97e349 ("ARM: dts: imx7d-smegw01: Add support for i.MX7D SMEGW01 board")
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 arch/arm/boot/dts/imx7d-smegw01.dts | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/imx7d-smegw01.dts b/arch/arm/boot/dts/imx7d-smegw01.dts
index c6b32064a0096..21b509c43393e 100644
--- a/arch/arm/boot/dts/imx7d-smegw01.dts
+++ b/arch/arm/boot/dts/imx7d-smegw01.dts
@@ -216,10 +216,8 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc2>;
 	bus-width = <4>;
+	no-1-8-v;
 	non-removable;
-	cap-sd-highspeed;
-	sd-uhs-ddr50;
-	mmc-ddr-1_8v;
 	vmmc-supply = <&reg_wifi>;
 	enable-sdio-wakeup;
 	status = "okay";
-- 
GitLab


From 8fc74d18639a2402ca52b177e990428e26ea881f Mon Sep 17 00:00:00 2001
From: Wentao_Liang <Wentao_Liang_g@163.com>
Date: Sun, 19 Jun 2022 22:14:54 +0800
Subject: [PATCH 0808/1731] drivers/net/ethernet/neterion/vxge: Fix a
 use-after-free bug in vxge-main.c
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The pointer vdev points to a memory region adjacent to a net_device
structure ndev, which is a field of hldev. At line 4740, the invocation
to vxge_device_unregister unregisters device hldev, and it also releases
the memory region pointed by vdev->bar0. At line 4743, the freed memory
region is referenced (i.e., iounmap(vdev->bar0)), resulting in a
use-after-free vulnerability. We can fix the bug by calling iounmap
before vxge_device_unregister.

4721.      static void vxge_remove(struct pci_dev *pdev)
4722.      {
4723.             struct __vxge_hw_device *hldev;
4724.             struct vxgedev *vdev;
…
4731.             vdev = netdev_priv(hldev->ndev);
…
4740.             vxge_device_unregister(hldev);
4741.             /* Do not call pci_disable_sriov here, as it
						will break child devices */
4742.             vxge_hw_device_terminate(hldev);
4743.             iounmap(vdev->bar0);
…
4749              vxge_debug_init(vdev->level_trace, "%s:%d
								Device unregistered",
4750                            __func__, __LINE__);
4751              vxge_debug_entryexit(vdev->level_trace, "%s:%d
								Exiting...", __func__,
4752                          __LINE__);
4753.      }

This is the screenshot when the vulnerability is triggered by using
KASAN. We can see that there is a use-after-free reported by KASAN.

/***************************start**************************/

root@kernel:~# echo 1 > /sys/bus/pci/devices/0000:00:03.0/remove
[  178.296316] vxge_remove
[  182.057081]
 ==================================================================
[  182.057548] BUG: KASAN: use-after-free in vxge_remove+0xe0/0x15c
[  182.057760] Read of size 8 at addr ffff888006c76598 by task bash/119
[  182.057983]
[  182.058747] CPU: 0 PID: 119 Comm: bash Not tainted 5.18.0 #5
[  182.058919] Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS
rel-1.13.0-0-gf21b5a4aeb02-prebuilt.qemu.org 04/01/2014
[  182.059463] Call Trace:
[  182.059726]  <TASK>
[  182.060017]  dump_stack_lvl+0x34/0x44
[  182.060316]  print_report.cold+0xb2/0x6b7
[  182.060401]  ? kfree+0x89/0x290
[  182.060478]  ? vxge_remove+0xe0/0x15c
[  182.060545]  kasan_report+0xa9/0x120
[  182.060629]  ? vxge_remove+0xe0/0x15c
[  182.060706]  vxge_remove+0xe0/0x15c
[  182.060793]  pci_device_remove+0x5d/0xe0
[  182.060968]  device_release_driver_internal+0xf1/0x180
[  182.061063]  pci_stop_bus_device+0xae/0xe0
[  182.061150]  pci_stop_and_remove_bus_device_locked+0x11/0x20
[  182.061236]  remove_store+0xc6/0xe0
[  182.061297]  ? subordinate_bus_number_show+0xc0/0xc0
[  182.061359]  ? __mutex_lock_slowpath+0x10/0x10
[  182.061438]  ? sysfs_kf_write+0x6d/0xa0
[  182.061525]  kernfs_fop_write_iter+0x1b0/0x260
[  182.061610]  ? sysfs_kf_bin_read+0xf0/0xf0
[  182.061695]  new_sync_write+0x209/0x310
[  182.061789]  ? new_sync_read+0x310/0x310
[  182.061865]  ? cgroup_rstat_updated+0x5c/0x170
[  182.061937]  ? preempt_count_sub+0xf/0xb0
[  182.061995]  ? pick_next_entity+0x13a/0x220
[  182.062063]  ? __inode_security_revalidate+0x44/0x80
[  182.062155]  ? security_file_permission+0x46/0x2a0
[  182.062230]  vfs_write+0x33f/0x3e0
[  182.062303]  ksys_write+0xb4/0x150
[  182.062369]  ? __ia32_sys_read+0x40/0x40
[  182.062451]  do_syscall_64+0x3b/0x90
[  182.062531]  entry_SYSCALL_64_after_hwframe+0x46/0xb0
[  182.062894] RIP: 0033:0x7f3f37d17274
[  182.063558] Code: 00 f7 d8 64 89 02 48 c7 c0 ff ff ff ff eb b3 0f 1f
80 00 00 00 00 48 8d 05 89 54 0d 00 8b 00 85 c0 75 13 b8 01 00 00 00 0f
05 <48> 3d 00 f0 ff ff 77 54 c3 0f 1f 00 41 54 49 89 d4 55 48 89 f5 53
[  182.063797] RSP: 002b:00007ffd5ba9e178 EFLAGS: 00000246
ORIG_RAX: 0000000000000001
[  182.064117] RAX: ffffffffffffffda RBX: 0000000000000002
RCX: 00007f3f37d17274
[  182.064219] RDX: 0000000000000002 RSI: 000055bbec327180
RDI: 0000000000000001
[  182.064315] RBP: 000055bbec327180 R08: 000000000000000a
R09: 00007f3f37de7cf0
[  182.064414] R10: 000000000000000a R11: 0000000000000246
R12: 00007f3f37de8760
[  182.064513] R13: 0000000000000002 R14: 00007f3f37de3760
R15: 0000000000000002
[  182.064691]  </TASK>
[  182.064916]
[  182.065224] The buggy address belongs to the physical page:
[  182.065804] page:00000000ef31e4f4 refcount:0 mapcount:0
mapping:0000000000000000 index:0x0 pfn:0x6c76
[  182.067419] flags: 0x100000000000000(node=0|zone=1)
[  182.068997] raw: 0100000000000000 0000000000000000
ffffea00001b1d88 0000000000000000
[  182.069118] raw: 0000000000000000 0000000000000000
00000000ffffffff 0000000000000000
[  182.069294] page dumped because: kasan: bad access detected
[  182.069331]
[  182.069360] Memory state around the buggy address:
[  182.070006]  ffff888006c76480: ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff
[  182.070136]  ffff888006c76500: ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff
[  182.070230] >ffff888006c76580: ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff
[  182.070305]                             ^
[  182.070456]  ffff888006c76600: ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff
[  182.070505]  ffff888006c76680: ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff
[  182.070606]
==================================================================
[  182.071374] Disabling lock debugging due to kernel taint

/*****************************end*****************************/

After fixing the bug as done in the patch, we can find KASAN do not report
 the bug and the device(00:03.0) has been successfully removed.

/*****************************start***************************/

root@kernel:~# echo 1 > /sys/bus/pci/devices/0000:00:03.0/remove
root@kernel:~#

/******************************end****************************/

Signed-off-by: Wentao_Liang <Wentao_Liang_g@163.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/neterion/vxge/vxge-main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/neterion/vxge/vxge-main.c b/drivers/net/ethernet/neterion/vxge/vxge-main.c
index fa5d4ddf429b6..092fd0ae58314 100644
--- a/drivers/net/ethernet/neterion/vxge/vxge-main.c
+++ b/drivers/net/ethernet/neterion/vxge/vxge-main.c
@@ -4736,10 +4736,10 @@ static void vxge_remove(struct pci_dev *pdev)
 	for (i = 0; i < vdev->no_of_vpath; i++)
 		vxge_free_mac_add_list(&vdev->vpaths[i]);
 
+	iounmap(vdev->bar0);
 	vxge_device_unregister(hldev);
 	/* Do not call pci_disable_sriov here, as it will break child devices */
 	vxge_hw_device_terminate(hldev);
-	iounmap(vdev->bar0);
 	pci_release_region(pdev, 0);
 	pci_disable_device(pdev);
 	driver_config->config_dev_cnt--;
-- 
GitLab


From 9926de7315be3d606cc011a305ad9adb9e8e14c9 Mon Sep 17 00:00:00 2001
From: Oleksij Rempel <o.rempel@pengutronix.de>
Date: Sat, 18 Jun 2022 14:23:33 +0200
Subject: [PATCH 0809/1731] net: phy: at803x: fix NULL pointer dereference on
 AR9331 PHY

Latest kernel will explode on the PHY interrupt config, since it depends
now on allocated priv. So, run probe to allocate priv to fix it.

 ar9331_switch ethernet.1:10 lan0 (uninitialized): PHY [!ahb!ethernet@1a000000!mdio!switch@10:00] driver [Qualcomm Atheros AR9331 built-in PHY] (irq=13)
 CPU 0 Unable to handle kernel paging request at virtual address 0000000a, epc == 8050e8a8, ra == 80504b34
         ...
 Call Trace:
 [<8050e8a8>] at803x_config_intr+0x5c/0xd0
 [<80504b34>] phy_request_interrupt+0xa8/0xd0
 [<8050289c>] phylink_bringup_phy+0x2d8/0x3ac
 [<80502b68>] phylink_fwnode_phy_connect+0x118/0x130
 [<8074d8ec>] dsa_slave_create+0x270/0x420
 [<80743b04>] dsa_port_setup+0x12c/0x148
 [<8074580c>] dsa_register_switch+0xaf0/0xcc0
 [<80511344>] ar9331_sw_probe+0x370/0x388
 [<8050cb78>] mdio_probe+0x44/0x70
 [<804df300>] really_probe+0x200/0x424
 [<804df7b4>] __driver_probe_device+0x290/0x298
 [<804df810>] driver_probe_device+0x54/0xe4
 [<804dfd50>] __device_attach_driver+0xe4/0x130
 [<804dcb00>] bus_for_each_drv+0xb4/0xd8
 [<804dfac4>] __device_attach+0x104/0x1a4
 [<804ddd24>] bus_probe_device+0x48/0xc4
 [<804deb44>] deferred_probe_work_func+0xf0/0x10c
 [<800a0ffc>] process_one_work+0x314/0x4d4
 [<800a17fc>] worker_thread+0x2a4/0x354
 [<800a9a54>] kthread+0x134/0x13c
 [<8006306c>] ret_from_kernel_thread+0x14/0x1c

Same Issue would affect some other PHYs (QCA8081, QCA9561), so fix it
too.

Fixes: 3265f4218878 ("net: phy: at803x: add fiber support")
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/phy/at803x.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index 6a467e7817a6a..59fe356942b51 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -2072,6 +2072,8 @@ static struct phy_driver at803x_driver[] = {
 	/* ATHEROS AR9331 */
 	PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
 	.name			= "Qualcomm Atheros AR9331 built-in PHY",
+	.probe			= at803x_probe,
+	.remove			= at803x_remove,
 	.suspend		= at803x_suspend,
 	.resume			= at803x_resume,
 	.flags			= PHY_POLL_CABLE_TEST,
@@ -2087,6 +2089,8 @@ static struct phy_driver at803x_driver[] = {
 	/* Qualcomm Atheros QCA9561 */
 	PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
 	.name			= "Qualcomm Atheros QCA9561 built-in PHY",
+	.probe			= at803x_probe,
+	.remove			= at803x_remove,
 	.suspend		= at803x_suspend,
 	.resume			= at803x_resume,
 	.flags			= PHY_POLL_CABLE_TEST,
@@ -2151,6 +2155,8 @@ static struct phy_driver at803x_driver[] = {
 	PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
 	.name			= "Qualcomm QCA8081",
 	.flags			= PHY_POLL_CABLE_TEST,
+	.probe			= at803x_probe,
+	.remove			= at803x_remove,
 	.config_intr		= at803x_config_intr,
 	.handle_interrupt	= at803x_handle_interrupt,
 	.get_tunable		= at803x_get_tunable,
-- 
GitLab


From ca5dabcff1df6bc8c413922b5fa63cc602858803 Mon Sep 17 00:00:00 2001
From: Christophe Leroy <christophe.leroy@csgroup.eu>
Date: Fri, 10 Jun 2022 17:43:43 +0200
Subject: [PATCH 0810/1731] powerpc/prom_init: Fix build failure with
 GCC_PLUGIN_STRUCTLEAK_BYREF_ALL and KASAN

When CONFIG_KASAN is selected, we expect prom_init to use __memset()
because it is too early to use memset().

But with CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL, the compiler adds calls
to memset() to clear objects on stack, hence the following failure:

	  PROMCHK arch/powerpc/kernel/prom_init_check
	Error: External symbol 'memset' referenced from prom_init.c
	make[2]: *** [arch/powerpc/kernel/Makefile:204 : arch/powerpc/kernel/prom_init_check] Erreur 1

prom_find_machine_type() is called from prom_init() and is called only
once, so lets put compat[] in BSS instead of stack to avoid that.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/3802811f7cf94f730be44688539c01bba3a3b5c0.1654875808.git.christophe.leroy@csgroup.eu
---
 arch/powerpc/kernel/prom_init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 04694ec423f66..13d6cb1888350 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -2302,7 +2302,7 @@ static void __init prom_init_stdout(void)
 
 static int __init prom_find_machine_type(void)
 {
-	char compat[256];
+	static char compat[256] __prombss;
 	int len, i = 0;
 #ifdef CONFIG_PPC64
 	phandle rtas;
-- 
GitLab


From 1d98cdf7fa2bc6e8063c0a692a1c091d8ebe3a75 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Mon, 6 Jun 2022 17:08:51 -0700
Subject: [PATCH 0811/1731] perf unwind: Fix uninitialized variable

The 'ret' variable may be uninitialized on error goto paths.

Fixes: dc2cf4ca866f5715 ("perf unwind: Fix segbase for ld.lld linked objects")
Reported-by: Sedat Dilek <sedat.dilek@gmail.com>
Reviewed-by: Fangrui Song <maskray@google.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Sedat Dilek <sedat.dilek@gmail.com> # LLVM-14 (x86-64)
Cc: Fangrui Song <maskray@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: llvm@lists.linux.dev
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sebastian Ullrich <sebasti@nullri.ch>
Link: https://lore.kernel.org/r/20220607000851.39798-1-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/unwind-libunwind-local.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/perf/util/unwind-libunwind-local.c b/tools/perf/util/unwind-libunwind-local.c
index 37622699c91ac..6e5b8cce47bf4 100644
--- a/tools/perf/util/unwind-libunwind-local.c
+++ b/tools/perf/util/unwind-libunwind-local.c
@@ -174,7 +174,7 @@ static int elf_section_address_and_offset(int fd, const char *name, u64 *address
 	Elf *elf;
 	GElf_Ehdr ehdr;
 	GElf_Shdr shdr;
-	int ret;
+	int ret = -1;
 
 	elf = elf_begin(fd, PERF_ELF_C_READ_MMAP, NULL);
 	if (elf == NULL)
-- 
GitLab


From ec906102e5b7d3393cfe83e606b48cf0c1fcb122 Mon Sep 17 00:00:00 2001
From: Thomas Richter <tmricht@linux.ibm.com>
Date: Fri, 3 Jun 2022 13:30:34 +0200
Subject: [PATCH 0812/1731] perf test: Fix "perf stat CSV output linter" test
 on s390

perf test -F 83 ("perf stat CSV output linter") fails on s390.

Reason is the wrong number of fields for certain CPU core/die/socket
related output.

On x84_64 the output of command:

  # ./perf stat -x, -A -a --no-merge true
  CPU0,1.50,msec,cpu-clock,1502781,100.00,1.052,CPUs utilized
  CPU1,1.48,msec,cpu-clock,1476113,100.00,1.034,CPUs utilized
  ...

results in 8 fields with 7 comma separators.

On s390 the output of command:

  #  ./perf stat -x, -A -a --no-merge -- true
  0.95,msec,cpu-clock,949800,100.00,1.060,CPUs utilized
  ...

results in 7 fields with 6 comma separators. Therefore this tests
fails on s390. Similar issues exist for per-die and per-socket output
which is not supported on s390.

I have rewritten the python program to count commas in each output line
into a bash function to achieve the same result. I hope this makes it a
bit easier.

Output before:

  # ./perf test -F 83
  83: perf stat CSV output linter  :
  Checking CSV output: no args [Success]
  Checking CSV output: system wide [Success]
  Checking CSV output: system wide Checking CSV output: \
	  system wide no aggregation 6.92,msec,cpu-clock,\
	  6918131,100.00,6.972,CPUs utilized
  ...
  RuntimeError: wrong number of fields. expected 7 in \
	  6.92,msec,cpu-clock,6918131,100.00,6.972,CPUs utilized

  FAILED!
  #

Output after:

  # ./perf test -F 83
  83: perf stat CSV output linter             :
  Checking CSV output: no args [Success]
  Checking CSV output: system wide [Success]
  Checking CSV output: system wide Checking CSV output:\
	  system wide no aggregation [Success]
  Checking CSV output: interval [Success]
  Checking CSV output: event [Success]
  Checking CSV output: per core [Success]
  Checking CSV output: per thread [Success]
  Checking CSV output: per die [Success]
  Checking CSV output: per node [Success]
  Checking CSV output: per socket [Success]
  Ok
  #

Committer notes:

Continues to work on x86_64

  $ perf test lint
   89: perf stat CSV output linter                                     : Ok
  $ perf test -v lint
  Couldn't bump rlimit(MEMLOCK), failures may take place when creating BPF maps, etc
   89: perf stat CSV output linter                                     :
  --- start ---
  test child forked, pid 53133
  Checking CSV output: no args [Success]
  Checking CSV output: system wide [Skip] paranoid and not root
  Checking CSV output: system wide [Skip] paranoid and not root
  Checking CSV output: interval [Success]
  Checking CSV output: event [Success]
  Checking CSV output: per core [Skip] paranoid and not root
  Checking CSV output: per thread [Skip] paranoid and not root
  Checking CSV output: per die [Skip] paranoid and not root
  Checking CSV output: per node [Skip] paranoid and not root
  Checking CSV output: per socket [Skip] paranoid and not root
  test child finished with 0
  ---- end ----
  perf stat CSV output linter: Ok
  $

Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
Acked-by: Ian Rogers <irogers@google.com>
Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Claire Jensen <cjense@google.com>
Cc: Heiko Carstens <hca@linux.ibm.com>
Cc: Sumanth Korikkar <sumanthk@linux.ibm.com>
Cc: Sven Schnelle <svens@linux.ibm.com>
Cc: Vasily Gorbik <gor@linux.ibm.com>
Cc: linux390-list@tuxmaker.boeblingen.de.ibm.com
Link: https://lore.kernel.org/r/20220603113034.2009728-1-tmricht@linux.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../tests/shell/lib/perf_csv_output_lint.py   | 48 -------------
 tools/perf/tests/shell/stat+csv_output.sh     | 69 ++++++++++++-------
 2 files changed, 45 insertions(+), 72 deletions(-)
 delete mode 100644 tools/perf/tests/shell/lib/perf_csv_output_lint.py

diff --git a/tools/perf/tests/shell/lib/perf_csv_output_lint.py b/tools/perf/tests/shell/lib/perf_csv_output_lint.py
deleted file mode 100644
index 714f283cfb1b3..0000000000000
--- a/tools/perf/tests/shell/lib/perf_csv_output_lint.py
+++ /dev/null
@@ -1,48 +0,0 @@
-#!/usr/bin/python
-# SPDX-License-Identifier: GPL-2.0
-
-import argparse
-import sys
-
-# Basic sanity check of perf CSV output as specified in the man page.
-# Currently just checks the number of fields per line in output.
-
-ap = argparse.ArgumentParser()
-ap.add_argument('--no-args', action='store_true')
-ap.add_argument('--interval', action='store_true')
-ap.add_argument('--system-wide-no-aggr', action='store_true')
-ap.add_argument('--system-wide', action='store_true')
-ap.add_argument('--event', action='store_true')
-ap.add_argument('--per-core', action='store_true')
-ap.add_argument('--per-thread', action='store_true')
-ap.add_argument('--per-die', action='store_true')
-ap.add_argument('--per-node', action='store_true')
-ap.add_argument('--per-socket', action='store_true')
-ap.add_argument('--separator', default=',', nargs='?')
-args = ap.parse_args()
-
-Lines = sys.stdin.readlines()
-
-def check_csv_output(exp):
-  for line in Lines:
-    if 'failed' not in line:
-      count = line.count(args.separator)
-      if count != exp:
-        sys.stdout.write(''.join(Lines))
-        raise RuntimeError(f'wrong number of fields. expected {exp} in {line}')
-
-try:
-  if args.no_args or args.system_wide or args.event:
-    expected_items = 6
-  elif args.interval or args.per_thread or args.system_wide_no_aggr:
-    expected_items = 7
-  elif args.per_core or args.per_socket or args.per_node or args.per_die:
-    expected_items = 8
-  else:
-    ap.print_help()
-    raise RuntimeError('No checking option specified')
-  check_csv_output(expected_items)
-
-except:
-  sys.stdout.write('Test failed for input: ' + ''.join(Lines))
-  raise
diff --git a/tools/perf/tests/shell/stat+csv_output.sh b/tools/perf/tests/shell/stat+csv_output.sh
index 983220ef3cb4e..38c26f3ef4c15 100755
--- a/tools/perf/tests/shell/stat+csv_output.sh
+++ b/tools/perf/tests/shell/stat+csv_output.sh
@@ -6,20 +6,41 @@
 
 set -e
 
-pythonchecker=$(dirname $0)/lib/perf_csv_output_lint.py
-if [ "x$PYTHON" == "x" ]
-then
-	if which python3 > /dev/null
-	then
-		PYTHON=python3
-	elif which python > /dev/null
-	then
-		PYTHON=python
-	else
-		echo Skipping test, python not detected please set environment variable PYTHON.
-		exit 2
-	fi
-fi
+function commachecker()
+{
+	local -i cnt=0 exp=0
+
+	case "$1"
+	in "--no-args")		exp=6
+	;; "--system-wide")	exp=6
+	;; "--event")		exp=6
+	;; "--interval")	exp=7
+	;; "--per-thread")	exp=7
+	;; "--system-wide-no-aggr")	exp=7
+				[ $(uname -m) = "s390x" ] && exp=6
+	;; "--per-core")	exp=8
+	;; "--per-socket")	exp=8
+	;; "--per-node")	exp=8
+	;; "--per-die")		exp=8
+	esac
+
+	while read line
+	do
+		# Check for lines beginning with Failed
+		x=${line:0:6}
+		[ "$x" = "Failed" ] && continue
+
+		# Count the number of commas
+		x=$(echo $line | tr -d -c ',')
+		cnt="${#x}"
+		# echo $line $cnt
+		[ "$cnt" -ne "$exp" ] && {
+			echo "wrong number of fields. expected $exp in $line" 1>&2
+			exit 1;
+		}
+	done
+	return 0
+}
 
 # Return true if perf_event_paranoid is > $1 and not running as root.
 function ParanoidAndNotRoot()
@@ -30,7 +51,7 @@ function ParanoidAndNotRoot()
 check_no_args()
 {
 	echo -n "Checking CSV output: no args "
-	perf stat -x, true 2>&1 | $PYTHON $pythonchecker --no-args
+	perf stat -x, true 2>&1 | commachecker --no-args
 	echo "[Success]"
 }
 
@@ -42,7 +63,7 @@ check_system_wide()
 		echo "[Skip] paranoid and not root"
 		return
 	fi
-	perf stat -x, -a true 2>&1 | $PYTHON $pythonchecker --system-wide
+	perf stat -x, -a true 2>&1 | commachecker --system-wide
 	echo "[Success]"
 }
 
@@ -55,14 +76,14 @@ check_system_wide_no_aggr()
 		return
 	fi
 	echo -n "Checking CSV output: system wide no aggregation "
-	perf stat -x, -A -a --no-merge true 2>&1 | $PYTHON $pythonchecker --system-wide-no-aggr
+	perf stat -x, -A -a --no-merge true 2>&1 | commachecker --system-wide-no-aggr
 	echo "[Success]"
 }
 
 check_interval()
 {
 	echo -n "Checking CSV output: interval "
-	perf stat -x, -I 1000 true 2>&1 | $PYTHON $pythonchecker --interval
+	perf stat -x, -I 1000 true 2>&1 | commachecker --interval
 	echo "[Success]"
 }
 
@@ -70,7 +91,7 @@ check_interval()
 check_event()
 {
 	echo -n "Checking CSV output: event "
-	perf stat -x, -e cpu-clock true 2>&1 | $PYTHON $pythonchecker --event
+	perf stat -x, -e cpu-clock true 2>&1 | commachecker --event
 	echo "[Success]"
 }
 
@@ -82,7 +103,7 @@ check_per_core()
 		echo "[Skip] paranoid and not root"
 		return
 	fi
-	perf stat -x, --per-core -a true 2>&1 | $PYTHON $pythonchecker --per-core
+	perf stat -x, --per-core -a true 2>&1 | commachecker --per-core
 	echo "[Success]"
 }
 
@@ -94,7 +115,7 @@ check_per_thread()
 		echo "[Skip] paranoid and not root"
 		return
 	fi
-	perf stat -x, --per-thread -a true 2>&1 | $PYTHON $pythonchecker --per-thread
+	perf stat -x, --per-thread -a true 2>&1 | commachecker --per-thread
 	echo "[Success]"
 }
 
@@ -106,7 +127,7 @@ check_per_die()
 		echo "[Skip] paranoid and not root"
 		return
 	fi
-	perf stat -x, --per-die -a true 2>&1 | $PYTHON $pythonchecker --per-die
+	perf stat -x, --per-die -a true 2>&1 | commachecker --per-die
 	echo "[Success]"
 }
 
@@ -118,7 +139,7 @@ check_per_node()
 		echo "[Skip] paranoid and not root"
 		return
 	fi
-	perf stat -x, --per-node -a true 2>&1 | $PYTHON $pythonchecker --per-node
+	perf stat -x, --per-node -a true 2>&1 | commachecker --per-node
 	echo "[Success]"
 }
 
@@ -130,7 +151,7 @@ check_per_socket()
 		echo "[Skip] paranoid and not root"
 		return
 	fi
-	perf stat -x, --per-socket -a true 2>&1 | $PYTHON $pythonchecker --per-socket
+	perf stat -x, --per-socket -a true 2>&1 | commachecker --per-socket
 	echo "[Success]"
 }
 
-- 
GitLab


From 94725994cfd768b9ee1bd06f15c252694b1e9b89 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 8 Jun 2022 22:23:52 -0700
Subject: [PATCH 0813/1731] libperf evsel: Open shouldn't leak fd on failure

If perf_event_open() fails the fd is opened but it is only freed by
closing (not by delete).

Typically when an open fails you don't call close and so this results in
a memory leak. To avoid this, add a close when open fails.

Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-By: Kajol Jain <kjain@linux.ibm.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Stephane Eranian <eranian@google.com>
Link: https://lore.kernel.org/r/20220609052355.1300162-2-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/lib/perf/evsel.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/tools/lib/perf/evsel.c b/tools/lib/perf/evsel.c
index c1d58673f6efa..952f3520d5c26 100644
--- a/tools/lib/perf/evsel.c
+++ b/tools/lib/perf/evsel.c
@@ -149,23 +149,30 @@ int perf_evsel__open(struct perf_evsel *evsel, struct perf_cpu_map *cpus,
 			int fd, group_fd, *evsel_fd;
 
 			evsel_fd = FD(evsel, idx, thread);
-			if (evsel_fd == NULL)
-				return -EINVAL;
+			if (evsel_fd == NULL) {
+				err = -EINVAL;
+				goto out;
+			}
 
 			err = get_group_fd(evsel, idx, thread, &group_fd);
 			if (err < 0)
-				return err;
+				goto out;
 
 			fd = sys_perf_event_open(&evsel->attr,
 						 threads->map[thread].pid,
 						 cpu, group_fd, 0);
 
-			if (fd < 0)
-				return -errno;
+			if (fd < 0) {
+				err = -errno;
+				goto out;
+			}
 
 			*evsel_fd = fd;
 		}
 	}
+out:
+	if (err)
+		perf_evsel__close(evsel);
 
 	return err;
 }
-- 
GitLab


From cc2145526c9889e3dbddc210c21bc3a080b2a29f Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Fri, 10 Jun 2022 11:02:47 -0700
Subject: [PATCH 0814/1731] perf test: Fix variable length array undefined
 behavior in bp_account

Fix:

  tests/bp_account.c:154:9: runtime error: variable length array bound evaluates to non-positive value 0

by switching from a variable length to an allocated array.

Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Link: https://lore.kernel.org/r/20220610180247.444798-1-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/tests/bp_account.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/tools/perf/tests/bp_account.c b/tools/perf/tests/bp_account.c
index d1ebb5561e5b3..6f921db33cf90 100644
--- a/tools/perf/tests/bp_account.c
+++ b/tools/perf/tests/bp_account.c
@@ -151,11 +151,21 @@ static int detect_ioctl(void)
 static int detect_share(int wp_cnt, int bp_cnt)
 {
 	struct perf_event_attr attr;
-	int i, fd[wp_cnt + bp_cnt], ret;
+	int i, *fd = NULL, ret = -1;
+
+	if (wp_cnt + bp_cnt == 0)
+		return 0;
+
+	fd = malloc(sizeof(int) * (wp_cnt + bp_cnt));
+	if (!fd)
+		return -1;
 
 	for (i = 0; i < wp_cnt; i++) {
 		fd[i] = wp_event((void *)&the_var, &attr);
-		TEST_ASSERT_VAL("failed to create wp\n", fd[i] != -1);
+		if (fd[i] == -1) {
+			pr_err("failed to create wp\n");
+			goto out;
+		}
 	}
 
 	for (; i < (bp_cnt + wp_cnt); i++) {
@@ -166,9 +176,11 @@ static int detect_share(int wp_cnt, int bp_cnt)
 
 	ret = i != (bp_cnt + wp_cnt);
 
+out:
 	while (i--)
 		close(fd[i]);
 
+	free(fd);
 	return ret;
 }
 
-- 
GitLab


From 67e7d771580e9f365e75e1cc3690401526cfbb29 Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Sat, 19 Jun 2021 10:09:08 -0300
Subject: [PATCH 0815/1731] perf beauty: Update copy of linux/socket.h with the
 kernel sources

To pick the changes in:

  f94fd25cb0aaf77f ("tcp: pass back data left in socket after receive")

That don't result in any changes in the tables generated from that
header.

This silences this perf build warning:

  Warning: Kernel ABI header at 'tools/perf/trace/beauty/include/linux/socket.h' differs from latest version at 'include/linux/socket.h'
  diff -u tools/perf/trace/beauty/include/linux/socket.h include/linux/socket.h

Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Jens Axboe <axboe@kernel.dk>
Link: https://lore.kernel.org/all/YqORj9d58AiGYl8b@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/trace/beauty/include/linux/socket.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/tools/perf/trace/beauty/include/linux/socket.h b/tools/perf/trace/beauty/include/linux/socket.h
index 6f85f5d957efe..17311ad9f9af2 100644
--- a/tools/perf/trace/beauty/include/linux/socket.h
+++ b/tools/perf/trace/beauty/include/linux/socket.h
@@ -50,6 +50,9 @@ struct linger {
 struct msghdr {
 	void		*msg_name;	/* ptr to socket address structure */
 	int		msg_namelen;	/* size of socket address structure */
+
+	int		msg_inq;	/* output, data left in socket */
+
 	struct iov_iter	msg_iter;	/* data */
 
 	/*
@@ -62,8 +65,9 @@ struct msghdr {
 		void __user	*msg_control_user;
 	};
 	bool		msg_control_is_user : 1;
-	__kernel_size_t	msg_controllen;	/* ancillary data buffer length */
+	bool		msg_get_inq : 1;/* return INQ after receive */
 	unsigned int	msg_flags;	/* flags on received message */
+	__kernel_size_t	msg_controllen;	/* ancillary data buffer length */
 	struct kiocb	*msg_iocb;	/* ptr to iocb for async requests */
 };
 
@@ -434,6 +438,7 @@ extern struct file *do_accept(struct file *file, unsigned file_flags,
 extern int __sys_accept4(int fd, struct sockaddr __user *upeer_sockaddr,
 			 int __user *upeer_addrlen, int flags);
 extern int __sys_socket(int family, int type, int protocol);
+extern struct file *__sys_socket_file(int family, int type, int protocol);
 extern int __sys_bind(int fd, struct sockaddr __user *umyaddr, int addrlen);
 extern int __sys_connect_file(struct file *file, struct sockaddr_storage *addr,
 			      int addrlen, int file_flags);
-- 
GitLab


From 72dcae8efd42699bbfd55e1ef187310c4e2e5dcb Mon Sep 17 00:00:00 2001
From: Michael Petlan <mpetlan@redhat.com>
Date: Tue, 14 Jun 2022 12:52:07 +0200
Subject: [PATCH 0816/1731] perf test: Record only user callchains on the
 "Check Arm64 callgraphs are complete in fp mode" test

The testcase 'Check Arm64 callgraphs are complete in fp mode' wants to
see the following output:

    610 leaf
    62f parent
    648 main

However, without excluding kernel callchains, the output might look like:

	ffffc2ff40ef1b5c arch_local_irq_enable
	ffffc2ff419d032c __schedule
	ffffc2ff419d06c0 schedule
	ffffc2ff40e4da30 do_notify_resume
	ffffc2ff40e421b0 work_pending
	             610 leaf
	             62f parent
	             648 main

Adding '--user-callchains' leaves only the wanted symbols in the chain.

Fixes: cd6382d82752737e ("perf test arm64: Test unwinding using fame-pointer (fp) mode")
Suggested-by: German Gomez <german.gomez@arm.com>
Reviewed-by: German Gomez <german.gomez@arm.com>
Reviewed-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Michael Petlan <mpetlan@redhat.com>
Cc: German Gomez <german.gomez@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Link: https://lore.kernel.org/r/20220614105207.26223-1-mpetlan@redhat.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/tests/shell/test_arm_callgraph_fp.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/perf/tests/shell/test_arm_callgraph_fp.sh b/tools/perf/tests/shell/test_arm_callgraph_fp.sh
index 6ffbb27afabac..ec108d45d3c61 100755
--- a/tools/perf/tests/shell/test_arm_callgraph_fp.sh
+++ b/tools/perf/tests/shell/test_arm_callgraph_fp.sh
@@ -43,7 +43,7 @@ CFLAGS="-g -O0 -fno-inline -fno-omit-frame-pointer"
 cc $CFLAGS $TEST_PROGRAM_SOURCE -o $TEST_PROGRAM || exit 1
 
 # Add a 1 second delay to skip samples that are not in the leaf() function
-perf record -o $PERF_DATA --call-graph fp -e cycles//u -D 1000 -- $TEST_PROGRAM 2> /dev/null &
+perf record -o $PERF_DATA --call-graph fp -e cycles//u -D 1000 --user-callchains -- $TEST_PROGRAM 2> /dev/null &
 PID=$!
 
 echo " + Recording (PID=$PID)..."
-- 
GitLab


From b236371421df57b93fc49c4b9d0e53bd1aab2b2e Mon Sep 17 00:00:00 2001
From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Date: Fri, 10 Jun 2022 19:29:39 +0530
Subject: [PATCH 0817/1731] perf test topology: Use !strncmp(right platform) to
 fix guest PPC comparision check

commit cfd7092c31aed728 ("perf test session topology: Fix test to skip
the test in guest environment") added check to skip the testcase if the
socket_id can't be fetched from topology info.

But the condition check uses strncmp which should be changed to !strncmp
and to correctly match platform.

Fix this condition check.

Fixes: cfd7092c31aed728 ("perf test session topology: Fix test to skip the test in guest environment")
Reported-by: Thomas Richter <tmricht@linux.ibm.com>
Signed-off-by: Athira Jajeev <atrajeev@linux.vnet.ibm.com>
Acked-by: Ian Rogers <irogers@google.com>
Cc: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Cc: Disha Goel <disgoel@linux.vnet.ibm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: linuxppc-dev@lists.ozlabs.org
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Nageswara R Sastry <rnsastry@linux.ibm.com>
Link: https://lore.kernel.org/r/20220610135939.63361-1-atrajeev@linux.vnet.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/tests/topology.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/perf/tests/topology.c b/tools/perf/tests/topology.c
index d23a9e322ff52..0b4f61b6cc6b8 100644
--- a/tools/perf/tests/topology.c
+++ b/tools/perf/tests/topology.c
@@ -115,7 +115,7 @@ static int check_cpu_topology(char *path, struct perf_cpu_map *map)
 	 * physical_package_id will be set to -1. Hence skip this
 	 * test if physical_package_id returns -1 for cpu from perf_cpu_map.
 	 */
-	if (strncmp(session->header.env.arch, "powerpc", 7)) {
+	if (!strncmp(session->header.env.arch, "ppc64le", 7)) {
 		if (cpu__get_socket_id(perf_cpu_map__cpu(map, 0)) == -1)
 			return TEST_SKIP;
 	}
-- 
GitLab


From e5287e6dd3b07e28e6bca5e33a3813a5e83bbc4c Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Thu, 26 May 2022 19:06:53 -0700
Subject: [PATCH 0818/1731] perf expr: Allow exponents on floating point values

Pass the optional exponent component through to strtod that already
supports it. We already have exponents in ScaleUnit and so this adds
uniformity.

Reported-by: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Reviewed-By: Kajol Jain <kjain@linux.ibm.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Richter <tmricht@linux.ibm.com>
Link: https://lore.kernel.org/r/20220527020653.4160884-1-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/tests/expr.c | 2 ++
 tools/perf/util/expr.l  | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/tools/perf/tests/expr.c b/tools/perf/tests/expr.c
index d54c5371c6a6e..5c0032fe93ae0 100644
--- a/tools/perf/tests/expr.c
+++ b/tools/perf/tests/expr.c
@@ -97,6 +97,8 @@ static int test__expr(struct test_suite *t __maybe_unused, int subtest __maybe_u
 	ret |= test(ctx, "2.2 > 2.2", 0);
 	ret |= test(ctx, "2.2 < 1.1", 0);
 	ret |= test(ctx, "1.1 > 2.2", 0);
+	ret |= test(ctx, "1.1e10 < 1.1e100", 1);
+	ret |= test(ctx, "1.1e2 > 1.1e-2", 1);
 
 	if (ret) {
 		expr__ctx_free(ctx);
diff --git a/tools/perf/util/expr.l b/tools/perf/util/expr.l
index 0a13eb20c8147..4dc8edbfd9cea 100644
--- a/tools/perf/util/expr.l
+++ b/tools/perf/util/expr.l
@@ -91,7 +91,7 @@ static int literal(yyscan_t scanner)
 }
 %}
 
-number		([0-9]+\.?[0-9]*|[0-9]*\.?[0-9]+)
+number		([0-9]+\.?[0-9]*|[0-9]*\.?[0-9]+)(e-?[0-9]+)?
 
 sch		[-,=]
 spec		\\{sch}
-- 
GitLab


From 51ba539f5bdb5a8cc7b1dedd5e73ac54564a7602 Mon Sep 17 00:00:00 2001
From: Leo Yan <leo.yan@linaro.org>
Date: Tue, 17 May 2022 02:03:25 +0000
Subject: [PATCH 0819/1731] perf arm-spe: Don't set data source if it's not a
 memory operation

Except for memory load and store operations, ARM SPE records also can
support other operation types, bug when set the data source field the
current code assumes a record is a either load operation or store
operation, this leads to wrongly synthesize memory samples.

This patch strictly checks the record operation type, it only sets data
source only for the operation types ARM_SPE_LD and ARM_SPE_ST,
otherwise, returns zero for data source.  Therefore, we can synthesize
memory samples only when data source is a non-zero value, the function
arm_spe__is_memory_event() is useless and removed.

Fixes: e55ed3423c1bb29f ("perf arm-spe: Synthesize memory event")
Reviewed-by: Ali Saidi <alisaidi@amazon.com>
Reviewed-by: German Gomez <german.gomez@arm.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Tested-by: Ali Saidi <alisaidi@amazon.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: alisaidi@amazon.com
Cc: Andrew Kilroy <andrew.kilroy@arm.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Li Huafei <lihuafei1@huawei.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Nick Forrington <nick.forrington@arm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Link: http://lore.kernel.org/lkml/20220517020326.18580-5-alisaidi@amazon.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/arm-spe.c | 22 ++++++++--------------
 1 file changed, 8 insertions(+), 14 deletions(-)

diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c
index 1a80151baed96..d040406f3314c 100644
--- a/tools/perf/util/arm-spe.c
+++ b/tools/perf/util/arm-spe.c
@@ -387,26 +387,16 @@ static int arm_spe__synth_instruction_sample(struct arm_spe_queue *speq,
 	return arm_spe_deliver_synth_event(spe, speq, event, &sample);
 }
 
-#define SPE_MEM_TYPE	(ARM_SPE_L1D_ACCESS | ARM_SPE_L1D_MISS | \
-			 ARM_SPE_LLC_ACCESS | ARM_SPE_LLC_MISS | \
-			 ARM_SPE_REMOTE_ACCESS)
-
-static bool arm_spe__is_memory_event(enum arm_spe_sample_type type)
-{
-	if (type & SPE_MEM_TYPE)
-		return true;
-
-	return false;
-}
-
 static u64 arm_spe__synth_data_source(const struct arm_spe_record *record)
 {
 	union perf_mem_data_src	data_src = { 0 };
 
 	if (record->op == ARM_SPE_LD)
 		data_src.mem_op = PERF_MEM_OP_LOAD;
-	else
+	else if (record->op == ARM_SPE_ST)
 		data_src.mem_op = PERF_MEM_OP_STORE;
+	else
+		return 0;
 
 	if (record->type & (ARM_SPE_LLC_ACCESS | ARM_SPE_LLC_MISS)) {
 		data_src.mem_lvl = PERF_MEM_LVL_L3;
@@ -510,7 +500,11 @@ static int arm_spe_sample(struct arm_spe_queue *speq)
 			return err;
 	}
 
-	if (spe->sample_memory && arm_spe__is_memory_event(record->type)) {
+	/*
+	 * When data_src is zero it means the record is not a memory operation,
+	 * skip to synthesize memory sample for this case.
+	 */
+	if (spe->sample_memory && data_src) {
 		err = arm_spe__synth_mem_sample(speq, spe->memory_id, data_src);
 		if (err)
 			return err;
-- 
GitLab


From 2e323f360a7b635a4df6faea616b80c188e68991 Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Fri, 10 Sep 2021 11:46:54 -0300
Subject: [PATCH 0820/1731] tools headers UAPI: Sync x86's asm/kvm.h with the
 kernel sources

To pick the changes in:

  f1a9761fbb00639c ("KVM: x86: Allow userspace to opt out of hypercall patching")

That just rebuilds kvm-stat.c on x86, no change in functionality.

This silences these perf build warning:

  Warning: Kernel ABI header at 'tools/arch/x86/include/uapi/asm/kvm.h' differs from latest version at 'arch/x86/include/uapi/asm/kvm.h'
  diff -u tools/arch/x86/include/uapi/asm/kvm.h arch/x86/include/uapi/asm/kvm.h

Cc: Oliver Upton <oupton@google.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Link: https://lore.kernel.org/lkml/Yq8qgiMwRcl9ds+f@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/arch/x86/include/uapi/asm/kvm.h | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/tools/arch/x86/include/uapi/asm/kvm.h b/tools/arch/x86/include/uapi/asm/kvm.h
index bf6e96011dfed..21614807a2cbb 100644
--- a/tools/arch/x86/include/uapi/asm/kvm.h
+++ b/tools/arch/x86/include/uapi/asm/kvm.h
@@ -428,11 +428,12 @@ struct kvm_sync_regs {
 	struct kvm_vcpu_events events;
 };
 
-#define KVM_X86_QUIRK_LINT0_REENABLED	   (1 << 0)
-#define KVM_X86_QUIRK_CD_NW_CLEARED	   (1 << 1)
-#define KVM_X86_QUIRK_LAPIC_MMIO_HOLE	   (1 << 2)
-#define KVM_X86_QUIRK_OUT_7E_INC_RIP	   (1 << 3)
-#define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT (1 << 4)
+#define KVM_X86_QUIRK_LINT0_REENABLED		(1 << 0)
+#define KVM_X86_QUIRK_CD_NW_CLEARED		(1 << 1)
+#define KVM_X86_QUIRK_LAPIC_MMIO_HOLE		(1 << 2)
+#define KVM_X86_QUIRK_OUT_7E_INC_RIP		(1 << 3)
+#define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT	(1 << 4)
+#define KVM_X86_QUIRK_FIX_HYPERCALL_INSN	(1 << 5)
 
 #define KVM_STATE_NESTED_FORMAT_VMX	0
 #define KVM_STATE_NESTED_FORMAT_SVM	1
-- 
GitLab


From 37402d5d061ba914a12d16ee8dda6d6964b4819d Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Sat, 9 Apr 2022 11:48:15 -0300
Subject: [PATCH 0821/1731] tools headers arm64: Sync arm64's cputype.h with
 the kernel sources

To get the changes in:

  cae889302ebf5a9b ("KVM: arm64: vgic-v3: List M1 Pro/Max as requiring the SEIS workaround")

That addresses this perf build warning:

  Warning: Kernel ABI header at 'tools/arch/arm64/include/asm/cputype.h' differs from latest version at 'arch/arm64/include/asm/cputype.h'
  diff -u tools/arch/arm64/include/asm/cputype.h arch/arm64/include/asm/cputype.h

Cc: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/lkml/Yq8w7p4omYKNwOij@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/arch/arm64/include/asm/cputype.h | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/tools/arch/arm64/include/asm/cputype.h b/tools/arch/arm64/include/asm/cputype.h
index e09d6908a21d3..8aa0d276a6362 100644
--- a/tools/arch/arm64/include/asm/cputype.h
+++ b/tools/arch/arm64/include/asm/cputype.h
@@ -36,7 +36,7 @@
 #define MIDR_VARIANT(midr)	\
 	(((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
 #define MIDR_IMPLEMENTOR_SHIFT	24
-#define MIDR_IMPLEMENTOR_MASK	(0xff << MIDR_IMPLEMENTOR_SHIFT)
+#define MIDR_IMPLEMENTOR_MASK	(0xffU << MIDR_IMPLEMENTOR_SHIFT)
 #define MIDR_IMPLEMENTOR(midr)	\
 	(((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
 
@@ -118,6 +118,10 @@
 
 #define APPLE_CPU_PART_M1_ICESTORM	0x022
 #define APPLE_CPU_PART_M1_FIRESTORM	0x023
+#define APPLE_CPU_PART_M1_ICESTORM_PRO	0x024
+#define APPLE_CPU_PART_M1_FIRESTORM_PRO	0x025
+#define APPLE_CPU_PART_M1_ICESTORM_MAX	0x028
+#define APPLE_CPU_PART_M1_FIRESTORM_MAX	0x029
 
 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
@@ -164,6 +168,10 @@
 #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
 #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
 #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
+#define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)
+#define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO)
+#define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX)
+#define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX)
 
 /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
 #define MIDR_FUJITSU_ERRATUM_010001		MIDR_FUJITSU_A64FX
@@ -172,7 +180,7 @@
 
 #ifndef __ASSEMBLY__
 
-#include "sysreg.h"
+#include <asm/sysreg.h>
 
 #define read_cpuid(reg)			read_sysreg_s(SYS_ ## reg)
 
-- 
GitLab


From c788ef61ef2ae51dc9cbd589e118f827585c156f Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Fri, 17 Jun 2022 18:39:57 -0700
Subject: [PATCH 0822/1731] perf metrics: Ensure at least 1 id per metric

We may have no events for a metric evaluated to a constant. In such a
case ensure a tool event is at least evaluated for metric parsing and
displaying.

Fixes: 8586d2744ff3065e ("perf metrics: Don't add all tool events for sharing")
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220618013957.999321-1-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/metricgroup.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c
index ee8fcfa115e50..8f7baeabc5cf6 100644
--- a/tools/perf/util/metricgroup.c
+++ b/tools/perf/util/metricgroup.c
@@ -1372,6 +1372,7 @@ static int parse_ids(bool metric_no_merge, struct perf_pmu *fake_pmu,
 
 	*out_evlist = NULL;
 	if (!metric_no_merge || hashmap__size(ids->ids) == 0) {
+		bool added_event = false;
 		int i;
 		/*
 		 * We may fail to share events between metrics because a tool
@@ -1393,8 +1394,16 @@ static int parse_ids(bool metric_no_merge, struct perf_pmu *fake_pmu,
 				if (!tmp)
 					return -ENOMEM;
 				ids__insert(ids->ids, tmp);
+				added_event = true;
 			}
 		}
+		if (!added_event && hashmap__size(ids->ids) == 0) {
+			char *tmp = strdup("duration_time");
+
+			if (!tmp)
+				return -ENOMEM;
+			ids__insert(ids->ids, tmp);
+		}
 	}
 	ret = metricgroup__build_event_string(&events, ids, modifier,
 					      has_constraint);
-- 
GitLab


From 140cd9ec8fdddc0e2d1684e6b69bcd05efbc9549 Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Thu, 11 Feb 2021 12:50:52 -0300
Subject: [PATCH 0823/1731] tools headers UAPI: Sync linux/prctl.h with the
 kernel sources

To pick the changes in:

  9e4ab6c891094720 ("arm64/sme: Implement vector length configuration prctl()s")

That don't result in any changes in tooling:

  $ tools/perf/trace/beauty/prctl_option.sh > before
  $ cp include/uapi/linux/prctl.h tools/include/uapi/linux/prctl.h
  $ tools/perf/trace/beauty/prctl_option.sh > after
  $ diff -u before after
  $

Just silences this perf tools build warning:

  Warning: Kernel ABI header at 'tools/include/uapi/linux/prctl.h' differs from latest version at 'include/uapi/linux/prctl.h'
  diff -u tools/include/uapi/linux/prctl.h include/uapi/linux/prctl.h

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mark Brown <broonie@kernel.org>
Link: http://lore.kernel.org/lkml/Yq81we+XFOqlBWyu@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/include/uapi/linux/prctl.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/tools/include/uapi/linux/prctl.h b/tools/include/uapi/linux/prctl.h
index e998764f02625..a5e06dcbba136 100644
--- a/tools/include/uapi/linux/prctl.h
+++ b/tools/include/uapi/linux/prctl.h
@@ -272,6 +272,15 @@ struct prctl_mm_map {
 # define PR_SCHED_CORE_SCOPE_THREAD_GROUP	1
 # define PR_SCHED_CORE_SCOPE_PROCESS_GROUP	2
 
+/* arm64 Scalable Matrix Extension controls */
+/* Flag values must be in sync with SVE versions */
+#define PR_SME_SET_VL			63	/* set task vector length */
+# define PR_SME_SET_VL_ONEXEC		(1 << 18) /* defer effect until exec */
+#define PR_SME_GET_VL			64	/* get task vector length */
+/* Bits common to PR_SME_SET_VL and PR_SME_GET_VL */
+# define PR_SME_VL_LEN_MASK		0xffff
+# define PR_SME_VL_INHERIT		(1 << 17) /* inherit across exec */
+
 #define PR_SET_VMA		0x53564d41
 # define PR_SET_VMA_ANON_NAME		0
 
-- 
GitLab


From be33d52ef5b4bdfec04cfdad39368c343bac97a3 Mon Sep 17 00:00:00 2001
From: Maya Matuszczyk <maccraft123mc@gmail.com>
Date: Sun, 19 Jun 2022 13:19:52 +0200
Subject: [PATCH 0824/1731] drm: panel-orientation-quirks: Add quirk for Aya
 Neo Next

The device is identified by "NEXT" in board name, however there are
different versions of it, "Next Advance" and "Next Pro", that have
different DMI board names.
Due to a production error a batch or two have their board names prefixed
by "AYANEO", this makes it 6 different DMI board names. To save some
space in final kernel image DMI_MATCH is used instead of
DMI_EXACT_MATCH.

Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220619111952.8487-1-maccraft123mc@gmail.com
---
 drivers/gpu/drm/drm_panel_orientation_quirks.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c b/drivers/gpu/drm/drm_panel_orientation_quirks.c
index 4e853acfd1e8a..df87ba99a87c0 100644
--- a/drivers/gpu/drm/drm_panel_orientation_quirks.c
+++ b/drivers/gpu/drm/drm_panel_orientation_quirks.c
@@ -152,6 +152,12 @@ static const struct dmi_system_id orientation_data[] = {
 		  DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "AYA NEO 2021"),
 		},
 		.driver_data = (void *)&lcd800x1280_rightside_up,
+	}, {	/* AYA NEO NEXT */
+		.matches = {
+		  DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AYANEO"),
+		  DMI_MATCH(DMI_BOARD_NAME, "NEXT"),
+		},
+		.driver_data = (void *)&lcd800x1280_rightside_up,
 	}, {	/* Chuwi HiBook (CWI514) */
 		.matches = {
 			DMI_MATCH(DMI_BOARD_VENDOR, "Hampoo"),
-- 
GitLab


From 6f6bd7591945c679b7f595119ea997b19f5794db Mon Sep 17 00:00:00 2001
From: Antoniu Miclaus <antoniu.miclaus@analog.com>
Date: Wed, 11 May 2022 12:00:06 +0300
Subject: [PATCH 0825/1731] iio: freq: admv1014: Fix warning about dubious x &
 !y and improve readability

The warning comes from __BF_FIELD_CHECK()
specifically

BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?		\
		 ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
		 _pfx "value too large for the field"); \

The code was using !(enum value) which is not particularly easy to follow
so replace that with explicit matching and use of ? 0 : 1; or ? 1 : 0;
to improve readability.

Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
Link: https://lore.kernel.org/r/20220511090006.90502-1-antoniu.miclaus@analog.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/frequency/admv1014.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/frequency/admv1014.c b/drivers/iio/frequency/admv1014.c
index a7994f8e6b9ba..1aac5665b5de3 100644
--- a/drivers/iio/frequency/admv1014.c
+++ b/drivers/iio/frequency/admv1014.c
@@ -700,8 +700,10 @@ static int admv1014_init(struct admv1014_state *st)
 			 ADMV1014_DET_EN_MSK;
 
 	enable_reg = FIELD_PREP(ADMV1014_P1DB_COMPENSATION_MSK, st->p1db_comp ? 3 : 0) |
-		     FIELD_PREP(ADMV1014_IF_AMP_PD_MSK, !(st->input_mode)) |
-		     FIELD_PREP(ADMV1014_BB_AMP_PD_MSK, st->input_mode) |
+		     FIELD_PREP(ADMV1014_IF_AMP_PD_MSK,
+				(st->input_mode == ADMV1014_IF_MODE) ? 0 : 1) |
+		     FIELD_PREP(ADMV1014_BB_AMP_PD_MSK,
+				(st->input_mode == ADMV1014_IF_MODE) ? 1 : 0) |
 		     FIELD_PREP(ADMV1014_DET_EN_MSK, st->det_en);
 
 	return __admv1014_spi_update_bits(st, ADMV1014_REG_ENABLE, enable_reg_msk, enable_reg);
-- 
GitLab


From b2f5ad97645e1deb5ca9bcb7090084b92cae35d2 Mon Sep 17 00:00:00 2001
From: Zheyu Ma <zheyuma97@gmail.com>
Date: Tue, 10 May 2022 17:24:31 +0800
Subject: [PATCH 0826/1731] iio: gyro: mpu3050: Fix the error handling in
 mpu3050_power_up()

The driver should disable regulators when fails at regmap_update_bits().

Signed-off-by: Zheyu Ma <zheyuma97@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Cc: <Stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20220510092431.1711284-1-zheyuma97@gmail.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/gyro/mpu3050-core.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/iio/gyro/mpu3050-core.c b/drivers/iio/gyro/mpu3050-core.c
index ea387efab62d2..f4c2f4cb48349 100644
--- a/drivers/iio/gyro/mpu3050-core.c
+++ b/drivers/iio/gyro/mpu3050-core.c
@@ -874,6 +874,7 @@ static int mpu3050_power_up(struct mpu3050 *mpu3050)
 	ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
 				 MPU3050_PWR_MGM_SLEEP, 0);
 	if (ret) {
+		regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
 		dev_err(mpu3050->dev, "error setting power mode\n");
 		return ret;
 	}
-- 
GitLab


From 78601726d4a59a291acc5a52da1d3a0a6831e4e8 Mon Sep 17 00:00:00 2001
From: Vincent Whitchurch <vincent.whitchurch@axis.com>
Date: Thu, 19 May 2022 11:19:25 +0200
Subject: [PATCH 0827/1731] iio: trigger: sysfs: fix use-after-free on remove

Ensure that the irq_work has completed before the trigger is freed.

 ==================================================================
 BUG: KASAN: use-after-free in irq_work_run_list
 Read of size 8 at addr 0000000064702248 by task python3/25

 Call Trace:
  irq_work_run_list
  irq_work_tick
  update_process_times
  tick_sched_handle
  tick_sched_timer
  __hrtimer_run_queues
  hrtimer_interrupt

 Allocated by task 25:
  kmem_cache_alloc_trace
  iio_sysfs_trig_add
  dev_attr_store
  sysfs_kf_write
  kernfs_fop_write_iter
  new_sync_write
  vfs_write
  ksys_write
  sys_write

 Freed by task 25:
  kfree
  iio_sysfs_trig_remove
  dev_attr_store
  sysfs_kf_write
  kernfs_fop_write_iter
  new_sync_write
  vfs_write
  ksys_write
  sys_write

 ==================================================================

Fixes: f38bc926d022 ("staging:iio:sysfs-trigger: Use irq_work to properly active trigger")
Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com>
Reviewed-by: Lars-Peter Clausen <lars@metafoo.de>
Link: https://lore.kernel.org/r/20220519091925.1053897-1-vincent.whitchurch@axis.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/trigger/iio-trig-sysfs.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/iio/trigger/iio-trig-sysfs.c b/drivers/iio/trigger/iio-trig-sysfs.c
index 2a4b75897910f..3d911c24b2650 100644
--- a/drivers/iio/trigger/iio-trig-sysfs.c
+++ b/drivers/iio/trigger/iio-trig-sysfs.c
@@ -191,6 +191,7 @@ static int iio_sysfs_trigger_remove(int id)
 	}
 
 	iio_trigger_unregister(t->trig);
+	irq_work_sync(&t->work);
 	iio_trigger_free(t->trig);
 
 	list_del(&t->l);
-- 
GitLab


From d836715f588ea15f905f607c27bc693587058db4 Mon Sep 17 00:00:00 2001
From: Jialin Zhang <zhangjialin11@huawei.com>
Date: Tue, 17 May 2022 11:35:26 +0800
Subject: [PATCH 0828/1731] iio: adc: rzg2l_adc: add missing
 fwnode_handle_put() in rzg2l_adc_parse_properties()

fwnode_handle_put() should be used when terminating
device_for_each_child_node() iteration with break or return to prevent
stale device node references from being left behind.

Fixes: d484c21bacfa ("iio: adc: Add driver for Renesas RZ/G2L A/D converter")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Jialin Zhang <zhangjialin11@huawei.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20220517033526.2035735-1-zhangjialin11@huawei.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/rzg2l_adc.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c
index 7585144b9715b..5b09a93fdf34f 100644
--- a/drivers/iio/adc/rzg2l_adc.c
+++ b/drivers/iio/adc/rzg2l_adc.c
@@ -334,11 +334,15 @@ static int rzg2l_adc_parse_properties(struct platform_device *pdev, struct rzg2l
 	i = 0;
 	device_for_each_child_node(&pdev->dev, fwnode) {
 		ret = fwnode_property_read_u32(fwnode, "reg", &channel);
-		if (ret)
+		if (ret) {
+			fwnode_handle_put(fwnode);
 			return ret;
+		}
 
-		if (channel >= RZG2L_ADC_MAX_CHANNELS)
+		if (channel >= RZG2L_ADC_MAX_CHANNELS) {
+			fwnode_handle_put(fwnode);
 			return -EINVAL;
+		}
 
 		chan_array[i].type = IIO_VOLTAGE;
 		chan_array[i].indexed = 1;
-- 
GitLab


From 47dcf770abc793f347a65a24c24d550c936f08b0 Mon Sep 17 00:00:00 2001
From: Jialin Zhang <zhangjialin11@huawei.com>
Date: Tue, 17 May 2022 11:30:20 +0800
Subject: [PATCH 0829/1731] iio: adc: ti-ads131e08: add missing
 fwnode_handle_put() in ads131e08_alloc_channels()

fwnode_handle_put() should be used when terminating
device_for_each_child_node() iteration with break or return to prevent
stale device node references from being left behind.

Fixes: d935eddd2799 ("iio: adc: Add driver for Texas Instruments ADS131E0x ADC family")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Jialin Zhang <zhangjialin11@huawei.com>
Link: https://lore.kernel.org/r/20220517033020.2033324-1-zhangjialin11@huawei.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/ti-ads131e08.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/iio/adc/ti-ads131e08.c b/drivers/iio/adc/ti-ads131e08.c
index 0c2025a225750..80a09817c1194 100644
--- a/drivers/iio/adc/ti-ads131e08.c
+++ b/drivers/iio/adc/ti-ads131e08.c
@@ -739,7 +739,7 @@ static int ads131e08_alloc_channels(struct iio_dev *indio_dev)
 	device_for_each_child_node(dev, node) {
 		ret = fwnode_property_read_u32(node, "reg", &channel);
 		if (ret)
-			return ret;
+			goto err_child_out;
 
 		ret = fwnode_property_read_u32(node, "ti,gain", &tmp);
 		if (ret) {
@@ -747,7 +747,7 @@ static int ads131e08_alloc_channels(struct iio_dev *indio_dev)
 		} else {
 			ret = ads131e08_pga_gain_to_field_value(st, tmp);
 			if (ret < 0)
-				return ret;
+				goto err_child_out;
 
 			channel_config[i].pga_gain = tmp;
 		}
@@ -758,7 +758,7 @@ static int ads131e08_alloc_channels(struct iio_dev *indio_dev)
 		} else {
 			ret = ads131e08_validate_channel_mux(st, tmp);
 			if (ret)
-				return ret;
+				goto err_child_out;
 
 			channel_config[i].mux = tmp;
 		}
@@ -784,6 +784,10 @@ static int ads131e08_alloc_channels(struct iio_dev *indio_dev)
 	st->channel_config = channel_config;
 
 	return 0;
+
+err_child_out:
+	fwnode_handle_put(node);
+	return ret;
 }
 
 static void ads131e08_regulator_disable(void *data)
-- 
GitLab


From d2214cca4d3eadc74eac9e30301ec7cad5355f00 Mon Sep 17 00:00:00 2001
From: Yannick Brosseau <yannick.brosseau@gmail.com>
Date: Mon, 16 May 2022 16:39:38 -0400
Subject: [PATCH 0830/1731] iio: adc: stm32: Fix ADCs iteration in irq handler

The irq handler was only checking the mask for the first ADCs in the case of the
F4 and H7 generation, since it was iterating up to the num_irq value. This patch add
the maximum number of ADC in the common register, which map to the number of entries of
eoc_msk and ovr_msk in stm32_adc_common_regs. This allow the handler to check all ADCs in
that module.

Tested on a STM32F429NIH6.

Fixes: 695e2f5c289b ("iio: adc: stm32-adc: fix a regression when using dma and irq")
Signed-off-by: Yannick Brosseau <yannick.brosseau@gmail.com>
Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Link: https://lore.kernel.org/r/20220516203939.3498673-2-yannick.brosseau@gmail.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/stm32-adc-core.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c
index 1426562321575..bb04deeb7992a 100644
--- a/drivers/iio/adc/stm32-adc-core.c
+++ b/drivers/iio/adc/stm32-adc-core.c
@@ -64,6 +64,7 @@ struct stm32_adc_priv;
  * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet)
  * @has_syscfg: SYSCFG capability flags
  * @num_irqs:	number of interrupt lines
+ * @num_adcs:   maximum number of ADC instances in the common registers
  */
 struct stm32_adc_priv_cfg {
 	const struct stm32_adc_common_regs *regs;
@@ -71,6 +72,7 @@ struct stm32_adc_priv_cfg {
 	u32 max_clk_rate_hz;
 	unsigned int has_syscfg;
 	unsigned int num_irqs;
+	unsigned int num_adcs;
 };
 
 /**
@@ -352,7 +354,7 @@ static void stm32_adc_irq_handler(struct irq_desc *desc)
 	 * before invoking the interrupt handler (e.g. call ISR only for
 	 * IRQ-enabled ADCs).
 	 */
-	for (i = 0; i < priv->cfg->num_irqs; i++) {
+	for (i = 0; i < priv->cfg->num_adcs; i++) {
 		if ((status & priv->cfg->regs->eoc_msk[i] &&
 		     stm32_adc_eoc_enabled(priv, i)) ||
 		     (status & priv->cfg->regs->ovr_msk[i]))
@@ -792,6 +794,7 @@ static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
 	.clk_sel = stm32f4_adc_clk_sel,
 	.max_clk_rate_hz = 36000000,
 	.num_irqs = 1,
+	.num_adcs = 3,
 };
 
 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
@@ -800,6 +803,7 @@ static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
 	.max_clk_rate_hz = 36000000,
 	.has_syscfg = HAS_VBOOSTER,
 	.num_irqs = 1,
+	.num_adcs = 2,
 };
 
 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
@@ -808,6 +812,7 @@ static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
 	.max_clk_rate_hz = 40000000,
 	.has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD,
 	.num_irqs = 2,
+	.num_adcs = 2,
 };
 
 static const struct of_device_id stm32_adc_of_match[] = {
-- 
GitLab


From 99bded02dae5e1e2312813506c41dc8db2fb656c Mon Sep 17 00:00:00 2001
From: Yannick Brosseau <yannick.brosseau@gmail.com>
Date: Mon, 16 May 2022 16:39:39 -0400
Subject: [PATCH 0831/1731] iio: adc: stm32: Fix IRQs on STM32F4 by removing
 custom spurious IRQs message

The check for spurious IRQs introduced in 695e2f5c289bb assumed that the bits
in the control and status registers are aligned. This is true for the H7 and MP1
version, but not the F4. The interrupt was then never handled on the F4.

Instead of increasing the complexity of the comparison and check each bit specifically,
we remove this check completely and rely on the generic handler for spurious IRQs.

Fixes: 695e2f5c289b ("iio: adc: stm32-adc: fix a regression when using dma and irq")
Signed-off-by: Yannick Brosseau <yannick.brosseau@gmail.com>
Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Link: https://lore.kernel.org/r/20220516203939.3498673-3-yannick.brosseau@gmail.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/stm32-adc.c | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c
index a68ecbda6480b..8c5f05f593aba 100644
--- a/drivers/iio/adc/stm32-adc.c
+++ b/drivers/iio/adc/stm32-adc.c
@@ -1407,7 +1407,6 @@ static irqreturn_t stm32_adc_threaded_isr(int irq, void *data)
 	struct stm32_adc *adc = iio_priv(indio_dev);
 	const struct stm32_adc_regspec *regs = adc->cfg->regs;
 	u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);
-	u32 mask = stm32_adc_readl(adc, regs->ier_eoc.reg);
 
 	/* Check ovr status right now, as ovr mask should be already disabled */
 	if (status & regs->isr_ovr.mask) {
@@ -1422,11 +1421,6 @@ static irqreturn_t stm32_adc_threaded_isr(int irq, void *data)
 		return IRQ_HANDLED;
 	}
 
-	if (!(status & mask))
-		dev_err_ratelimited(&indio_dev->dev,
-				    "Unexpected IRQ: IER=0x%08x, ISR=0x%08x\n",
-				    mask, status);
-
 	return IRQ_NONE;
 }
 
@@ -1436,10 +1430,6 @@ static irqreturn_t stm32_adc_isr(int irq, void *data)
 	struct stm32_adc *adc = iio_priv(indio_dev);
 	const struct stm32_adc_regspec *regs = adc->cfg->regs;
 	u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);
-	u32 mask = stm32_adc_readl(adc, regs->ier_eoc.reg);
-
-	if (!(status & mask))
-		return IRQ_WAKE_THREAD;
 
 	if (status & regs->isr_ovr.mask) {
 		/*
-- 
GitLab


From 8a2b6b5687984a010ed094b4f436a2f091987758 Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Mon, 16 May 2022 11:52:02 +0400
Subject: [PATCH 0832/1731] iio: adc: aspeed: Fix refcount leak in
 aspeed_adc_set_trim_data

of_find_node_by_name() returns a node pointer with refcount
incremented, we should use of_node_put() on it when done.
Add missing of_node_put() to avoid refcount leak.

Fixes: d0a4c17b4073 ("iio: adc: aspeed: Get and set trimming data.")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Link: https://lore.kernel.org/r/20220516075206.34580-1-linmq006@gmail.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/aspeed_adc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c
index 0793d2474cdcf..9341e0e0eb556 100644
--- a/drivers/iio/adc/aspeed_adc.c
+++ b/drivers/iio/adc/aspeed_adc.c
@@ -186,6 +186,7 @@ static int aspeed_adc_set_trim_data(struct iio_dev *indio_dev)
 		return -EOPNOTSUPP;
 	}
 	scu = syscon_node_to_regmap(syscon);
+	of_node_put(syscon);
 	if (IS_ERR(scu)) {
 		dev_warn(data->dev, "Failed to get syscon regmap\n");
 		return -EOPNOTSUPP;
-- 
GitLab


From 9decacd8b3a432316d61c4366f302e63384cb08d Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Tue, 24 May 2022 09:54:48 +0200
Subject: [PATCH 0833/1731] iio: afe: rescale: Fix boolean logic bug

When introducing support for processed channels I needed
to invert the expression:

  if (!iio_channel_has_info(schan, IIO_CHAN_INFO_RAW) ||
      !iio_channel_has_info(schan, IIO_CHAN_INFO_SCALE))
        dev_err(dev, "source channel does not support raw/scale\n");

To the inverse, meaning detect when we can usse raw+scale
rather than when we can not. This was the result:

  if (iio_channel_has_info(schan, IIO_CHAN_INFO_RAW) ||
      iio_channel_has_info(schan, IIO_CHAN_INFO_SCALE))
       dev_info(dev, "using raw+scale source channel\n");

Ooops. Spot the error. Yep old George Boole came up and bit me.
That should be an &&.

The current code "mostly works" because we have not run into
systems supporting only raw but not scale or only scale but not
raw, and I doubt there are few using the rescaler on anything
such, but let's fix the logic.

Cc: Liam Beguin <liambeguin@gmail.com>
Cc: stable@vger.kernel.org
Fixes: 53ebee949980 ("iio: afe: iio-rescale: Support processed channels")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Liam Beguin <liambeguin@gmail.com>
Acked-by: Peter Rosin <peda@axentia.se>
Link: https://lore.kernel.org/r/20220524075448.140238-1-linus.walleij@linaro.org
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/afe/iio-rescale.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/afe/iio-rescale.c b/drivers/iio/afe/iio-rescale.c
index 7e511293d6d12..dc426e1484f0d 100644
--- a/drivers/iio/afe/iio-rescale.c
+++ b/drivers/iio/afe/iio-rescale.c
@@ -278,7 +278,7 @@ static int rescale_configure_channel(struct device *dev,
 	chan->ext_info = rescale->ext_info;
 	chan->type = rescale->cfg->type;
 
-	if (iio_channel_has_info(schan, IIO_CHAN_INFO_RAW) ||
+	if (iio_channel_has_info(schan, IIO_CHAN_INFO_RAW) &&
 	    iio_channel_has_info(schan, IIO_CHAN_INFO_SCALE)) {
 		dev_info(dev, "using raw+scale source channel\n");
 	} else if (iio_channel_has_info(schan, IIO_CHAN_INFO_PROCESSED)) {
-- 
GitLab


From e5f3205b04d7f95a2ef43bce4b454a7f264d6923 Mon Sep 17 00:00:00 2001
From: Dmitry Rokosov <DDRokosov@sberdevices.ru>
Date: Tue, 24 May 2022 18:14:39 +0000
Subject: [PATCH 0834/1731] iio:accel:bma180: rearrange iio trigger get and
 register

IIO trigger interface function iio_trigger_get() should be called after
iio_trigger_register() (or its devm analogue) strictly, because of
iio_trigger_get() acquires module refcnt based on the trigger->owner
pointer, which is initialized inside iio_trigger_register() to
THIS_MODULE.
If this call order is wrong, the next iio_trigger_put() (from sysfs
callback or "delete module" path) will dereference "default" module
refcnt, which is incorrect behaviour.

Fixes: 0668a4e4d297 ("iio: accel: bma180: Fix indio_dev->trig assignment")
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220524181150.9240-2-ddrokosov@sberdevices.ru
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/accel/bma180.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/iio/accel/bma180.c b/drivers/iio/accel/bma180.c
index 4f73bc827eecb..9c9e985786670 100644
--- a/drivers/iio/accel/bma180.c
+++ b/drivers/iio/accel/bma180.c
@@ -1006,11 +1006,12 @@ static int bma180_probe(struct i2c_client *client,
 
 		data->trig->ops = &bma180_trigger_ops;
 		iio_trigger_set_drvdata(data->trig, indio_dev);
-		indio_dev->trig = iio_trigger_get(data->trig);
 
 		ret = iio_trigger_register(data->trig);
 		if (ret)
 			goto err_trigger_free;
+
+		indio_dev->trig = iio_trigger_get(data->trig);
 	}
 
 	ret = iio_triggered_buffer_setup(indio_dev, NULL,
-- 
GitLab


From ed302925d708f2f97ae5e9fd6c56c16bb34f6629 Mon Sep 17 00:00:00 2001
From: Dmitry Rokosov <DDRokosov@sberdevices.ru>
Date: Tue, 24 May 2022 18:14:42 +0000
Subject: [PATCH 0835/1731] iio:accel:kxcjk-1013: rearrange iio trigger get and
 register

IIO trigger interface function iio_trigger_get() should be called after
iio_trigger_register() (or its devm analogue) strictly, because of
iio_trigger_get() acquires module refcnt based on the trigger->owner
pointer, which is initialized inside iio_trigger_register() to
THIS_MODULE.
If this call order is wrong, the next iio_trigger_put() (from sysfs
callback or "delete module" path) will dereference "default" module
refcnt, which is incorrect behaviour.

Fixes: c1288b833881 ("iio: accel: kxcjk-1013: Increment ref counter for indio_dev->trig")
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220524181150.9240-3-ddrokosov@sberdevices.ru
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/accel/kxcjk-1013.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/accel/kxcjk-1013.c b/drivers/iio/accel/kxcjk-1013.c
index ac74cdcd2bc8c..748b35c2f0c37 100644
--- a/drivers/iio/accel/kxcjk-1013.c
+++ b/drivers/iio/accel/kxcjk-1013.c
@@ -1554,12 +1554,12 @@ static int kxcjk1013_probe(struct i2c_client *client,
 
 		data->dready_trig->ops = &kxcjk1013_trigger_ops;
 		iio_trigger_set_drvdata(data->dready_trig, indio_dev);
-		indio_dev->trig = data->dready_trig;
-		iio_trigger_get(indio_dev->trig);
 		ret = iio_trigger_register(data->dready_trig);
 		if (ret)
 			goto err_poweroff;
 
+		indio_dev->trig = iio_trigger_get(data->dready_trig);
+
 		data->motion_trig->ops = &kxcjk1013_trigger_ops;
 		iio_trigger_set_drvdata(data->motion_trig, indio_dev);
 		ret = iio_trigger_register(data->motion_trig);
-- 
GitLab


From 9354c224c9b4f55847a0de3e968cba2ebf15af3b Mon Sep 17 00:00:00 2001
From: Dmitry Rokosov <DDRokosov@sberdevices.ru>
Date: Tue, 24 May 2022 18:14:43 +0000
Subject: [PATCH 0836/1731] iio:accel:mxc4005: rearrange iio trigger get and
 register

IIO trigger interface function iio_trigger_get() should be called after
iio_trigger_register() (or its devm analogue) strictly, because of
iio_trigger_get() acquires module refcnt based on the trigger->owner
pointer, which is initialized inside iio_trigger_register() to
THIS_MODULE.
If this call order is wrong, the next iio_trigger_put() (from sysfs
callback or "delete module" path) will dereference "default" module
refcnt, which is incorrect behaviour.

Fixes: 47196620c82f ("iio: mxc4005: add data ready trigger for mxc4005")
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220524181150.9240-4-ddrokosov@sberdevices.ru
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/accel/mxc4005.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/accel/mxc4005.c b/drivers/iio/accel/mxc4005.c
index b3afbf0649152..df600d2917c0a 100644
--- a/drivers/iio/accel/mxc4005.c
+++ b/drivers/iio/accel/mxc4005.c
@@ -456,8 +456,6 @@ static int mxc4005_probe(struct i2c_client *client,
 
 		data->dready_trig->ops = &mxc4005_trigger_ops;
 		iio_trigger_set_drvdata(data->dready_trig, indio_dev);
-		indio_dev->trig = data->dready_trig;
-		iio_trigger_get(indio_dev->trig);
 		ret = devm_iio_trigger_register(&client->dev,
 						data->dready_trig);
 		if (ret) {
@@ -465,6 +463,8 @@ static int mxc4005_probe(struct i2c_client *client,
 				"failed to register trigger\n");
 			return ret;
 		}
+
+		indio_dev->trig = iio_trigger_get(data->dready_trig);
 	}
 
 	return devm_iio_device_register(&client->dev, indio_dev);
-- 
GitLab


From d710359c0b445e8c03e24f19ae2fb79ce7282260 Mon Sep 17 00:00:00 2001
From: Dmitry Rokosov <DDRokosov@sberdevices.ru>
Date: Tue, 24 May 2022 18:14:45 +0000
Subject: [PATCH 0837/1731] iio:chemical:ccs811: rearrange iio trigger get and
 register

IIO trigger interface function iio_trigger_get() should be called after
iio_trigger_register() (or its devm analogue) strictly, because of
iio_trigger_get() acquires module refcnt based on the trigger->owner
pointer, which is initialized inside iio_trigger_register() to
THIS_MODULE.
If this call order is wrong, the next iio_trigger_put() (from sysfs
callback or "delete module" path) will dereference "default" module
refcnt, which is incorrect behaviour.

Fixes: f1f065d7ac30 ("iio: chemical: ccs811: Add support for data ready trigger")
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220524181150.9240-5-ddrokosov@sberdevices.ru
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/chemical/ccs811.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/chemical/ccs811.c b/drivers/iio/chemical/ccs811.c
index 847194fa1e464..80ef1aa9aae3b 100644
--- a/drivers/iio/chemical/ccs811.c
+++ b/drivers/iio/chemical/ccs811.c
@@ -499,11 +499,11 @@ static int ccs811_probe(struct i2c_client *client,
 
 		data->drdy_trig->ops = &ccs811_trigger_ops;
 		iio_trigger_set_drvdata(data->drdy_trig, indio_dev);
-		indio_dev->trig = data->drdy_trig;
-		iio_trigger_get(indio_dev->trig);
 		ret = iio_trigger_register(data->drdy_trig);
 		if (ret)
 			goto err_poweroff;
+
+		indio_dev->trig = iio_trigger_get(data->drdy_trig);
 	}
 
 	ret = iio_triggered_buffer_setup(indio_dev, NULL,
-- 
GitLab


From 10b9c2c33ac706face458feab8965f11743c98c0 Mon Sep 17 00:00:00 2001
From: Dmitry Rokosov <DDRokosov@sberdevices.ru>
Date: Tue, 24 May 2022 18:14:46 +0000
Subject: [PATCH 0838/1731] iio:humidity:hts221: rearrange iio trigger get and
 register

IIO trigger interface function iio_trigger_get() should be called after
iio_trigger_register() (or its devm analogue) strictly, because of
iio_trigger_get() acquires module refcnt based on the trigger->owner
pointer, which is initialized inside iio_trigger_register() to
THIS_MODULE.
If this call order is wrong, the next iio_trigger_put() (from sysfs
callback or "delete module" path) will dereference "default" module
refcnt, which is incorrect behaviour.

Fixes: e4a70e3e7d84 ("iio: humidity: add support to hts221 rh/temp combo device")
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220524181150.9240-6-ddrokosov@sberdevices.ru
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/humidity/hts221_buffer.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/iio/humidity/hts221_buffer.c b/drivers/iio/humidity/hts221_buffer.c
index f29692b9d2db0..66b32413cf5e2 100644
--- a/drivers/iio/humidity/hts221_buffer.c
+++ b/drivers/iio/humidity/hts221_buffer.c
@@ -135,9 +135,12 @@ int hts221_allocate_trigger(struct iio_dev *iio_dev)
 
 	iio_trigger_set_drvdata(hw->trig, iio_dev);
 	hw->trig->ops = &hts221_trigger_ops;
+
+	err = devm_iio_trigger_register(hw->dev, hw->trig);
+
 	iio_dev->trig = iio_trigger_get(hw->trig);
 
-	return devm_iio_trigger_register(hw->dev, hw->trig);
+	return err;
 }
 
 static int hts221_buffer_preenable(struct iio_dev *iio_dev)
-- 
GitLab


From 7a2f6f61e8ee016b75e1b1dd62fbd03e6d6db37d Mon Sep 17 00:00:00 2001
From: Liam Beguin <liambeguin@gmail.com>
Date: Wed, 1 Jun 2022 10:21:38 -0400
Subject: [PATCH 0839/1731] iio: test: fix missing MODULE_LICENSE for
 IIO_RESCALE=m

When IIO_RESCALE_KUNIT_TEST=y and IIO_RESCALE=m,
drivers/iio/afe/iio-rescale.o is built twice causing the
MODULE_LICENSE() to be lost, as shown by:

  ERROR: modpost: missing MODULE_LICENSE() in drivers/iio/afe/iio-rescale.o

Rework the build configuration to have the dependency specified in the
Kconfig.

Reported-by: Randy Dunlap <rdunlap@infradead.org>
Fixes: 8e74a48d17d5 ("iio: test: add basic tests for the iio-rescale driver")
Signed-off-by: Liam Beguin <liambeguin@gmail.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Tested-by: Randy Dunlap <rdunlap@infradead.org>
Reviewed-by: Masahiro Yamada <masahiroy@kernel.org>
Link: https://lore.kernel.org/r/20220601142138.3331278-1-liambeguin@gmail.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/test/Kconfig  | 2 +-
 drivers/iio/test/Makefile | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/test/Kconfig b/drivers/iio/test/Kconfig
index 56ca0ad7e77a2..4c66c3f18c345 100644
--- a/drivers/iio/test/Kconfig
+++ b/drivers/iio/test/Kconfig
@@ -6,7 +6,7 @@
 # Keep in alphabetical order
 config IIO_RESCALE_KUNIT_TEST
 	bool "Test IIO rescale conversion functions"
-	depends on KUNIT=y && !IIO_RESCALE
+	depends on KUNIT=y && IIO_RESCALE=y
 	default KUNIT_ALL_TESTS
 	help
 	  If you want to run tests on the iio-rescale code say Y here.
diff --git a/drivers/iio/test/Makefile b/drivers/iio/test/Makefile
index f15ae0a6394f7..880360f8d02c2 100644
--- a/drivers/iio/test/Makefile
+++ b/drivers/iio/test/Makefile
@@ -4,6 +4,6 @@
 #
 
 # Keep in alphabetical order
-obj-$(CONFIG_IIO_RESCALE_KUNIT_TEST) += iio-test-rescale.o ../afe/iio-rescale.o
+obj-$(CONFIG_IIO_RESCALE_KUNIT_TEST) += iio-test-rescale.o
 obj-$(CONFIG_IIO_TEST_FORMAT) += iio-test-format.o
 CFLAGS_iio-test-format.o += $(DISABLE_STRUCTLEAK_PLUGIN)
-- 
GitLab


From ada7b0c0dedafd7d059115adf49e48acba3153a8 Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Tue, 24 May 2022 11:45:17 +0400
Subject: [PATCH 0840/1731] iio: adc: adi-axi-adc: Fix refcount leak in
 adi_axi_adc_attach_client

of_parse_phandle() returns a node pointer with refcount
incremented, we should use of_node_put() on it when not need anymore.
Add missing of_node_put() to avoid refcount leak.

Fixes: ef04070692a2 ("iio: adc: adi-axi-adc: add support for AXI ADC IP core")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Link: https://lore.kernel.org/r/20220524074517.45268-1-linmq006@gmail.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/adi-axi-adc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c
index a73e3c2d212fa..a9e655e69eaa2 100644
--- a/drivers/iio/adc/adi-axi-adc.c
+++ b/drivers/iio/adc/adi-axi-adc.c
@@ -322,16 +322,19 @@ static struct adi_axi_adc_client *adi_axi_adc_attach_client(struct device *dev)
 
 		if (!try_module_get(cl->dev->driver->owner)) {
 			mutex_unlock(&registered_clients_lock);
+			of_node_put(cln);
 			return ERR_PTR(-ENODEV);
 		}
 
 		get_device(cl->dev);
 		cl->info = info;
 		mutex_unlock(&registered_clients_lock);
+		of_node_put(cln);
 		return cl;
 	}
 
 	mutex_unlock(&registered_clients_lock);
+	of_node_put(cln);
 
 	return ERR_PTR(-EPROBE_DEFER);
 }
-- 
GitLab


From f1a633b15cd5371a2a83f02c513984e51132dd68 Mon Sep 17 00:00:00 2001
From: Baruch Siach <baruch@tkos.co.il>
Date: Mon, 30 May 2022 11:50:26 +0300
Subject: [PATCH 0841/1731] iio: adc: vf610: fix conversion mode sysfs node
 name

The documentation missed the "in_" prefix for this IIO_SHARED_BY_DIR
entry.

Fixes: bf04c1a367e3 ("iio: adc: vf610: implement configurable conversion modes")
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Acked-by: Haibo Chen <haibo.chen@nxp.com>
Link: https://lore.kernel.org/r/560dc93fafe5ef7e9a409885fd20b6beac3973d8.1653900626.git.baruch@tkos.co.il
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 Documentation/ABI/testing/sysfs-bus-iio-vf610 | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/ABI/testing/sysfs-bus-iio-vf610 b/Documentation/ABI/testing/sysfs-bus-iio-vf610
index 308a6756d3bf3..491ead8044888 100644
--- a/Documentation/ABI/testing/sysfs-bus-iio-vf610
+++ b/Documentation/ABI/testing/sysfs-bus-iio-vf610
@@ -1,4 +1,4 @@
-What:		/sys/bus/iio/devices/iio:deviceX/conversion_mode
+What:		/sys/bus/iio/devices/iio:deviceX/in_conversion_mode
 KernelVersion:	4.2
 Contact:	linux-iio@vger.kernel.org
 Description:
-- 
GitLab


From 106b391e1b859100a3f38f0ad874236e9be06bde Mon Sep 17 00:00:00 2001
From: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
Date: Thu, 9 Jun 2022 12:23:01 +0200
Subject: [PATCH 0842/1731] iio: imu: inv_icm42600: Fix broken icm42600 (chip
 id 0 value)

The 0 value used for INV_CHIP_ICM42600 was not working since the
match in i2c/spi was checking against NULL value.

To keep this check, add a first INV_CHIP_INVALID 0 value as safe
guard.

Fixes: 31c24c1e93c3 ("iio: imu: inv_icm42600: add core of new inv_icm42600 driver")
Signed-off-by: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
Link: https://lore.kernel.org/r/20220609102301.4794-1-jmaneyrol@invensense.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/imu/inv_icm42600/inv_icm42600.h      | 1 +
 drivers/iio/imu/inv_icm42600/inv_icm42600_core.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600.h b/drivers/iio/imu/inv_icm42600/inv_icm42600.h
index c0f5059b13b31..995a9dc06521d 100644
--- a/drivers/iio/imu/inv_icm42600/inv_icm42600.h
+++ b/drivers/iio/imu/inv_icm42600/inv_icm42600.h
@@ -17,6 +17,7 @@
 #include "inv_icm42600_buffer.h"
 
 enum inv_icm42600_chip {
+	INV_CHIP_INVALID,
 	INV_CHIP_ICM42600,
 	INV_CHIP_ICM42602,
 	INV_CHIP_ICM42605,
diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c b/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c
index 86858da9cc38f..ca85fccc98393 100644
--- a/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c
+++ b/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c
@@ -565,7 +565,7 @@ int inv_icm42600_core_probe(struct regmap *regmap, int chip, int irq,
 	bool open_drain;
 	int ret;
 
-	if (chip < 0 || chip >= INV_CHIP_NB) {
+	if (chip <= INV_CHIP_INVALID || chip >= INV_CHIP_NB) {
 		dev_err(dev, "invalid chip = %d\n", chip);
 		return -ENODEV;
 	}
-- 
GitLab


From bc05f30fc24705cd023f38659303376eaa5767df Mon Sep 17 00:00:00 2001
From: Olivier Moysan <olivier.moysan@foss.st.com>
Date: Thu, 9 Jun 2022 11:58:56 +0200
Subject: [PATCH 0843/1731] iio: adc: stm32: fix vrefint wrong calibration
 value handling

If the vrefint calibration is zero, the vrefint channel output value
cannot be computed. Currently, in such case, the raw conversion value
is returned, which is not relevant.
Do not expose the vrefint channel when the output value cannot be
computed, instead.

Fixes: 0e346b2cfa85 ("iio: adc: stm32-adc: add vrefint calibration support")
Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Link: https://lore.kernel.org/r/20220609095856.376961-1-olivier.moysan@foss.st.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/stm32-adc.c | 27 +++++++++++++++++----------
 1 file changed, 17 insertions(+), 10 deletions(-)

diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c
index 8c5f05f593aba..11ef873d64532 100644
--- a/drivers/iio/adc/stm32-adc.c
+++ b/drivers/iio/adc/stm32-adc.c
@@ -1365,7 +1365,7 @@ static int stm32_adc_read_raw(struct iio_dev *indio_dev,
 		else
 			ret = -EINVAL;
 
-		if (mask == IIO_CHAN_INFO_PROCESSED && adc->vrefint.vrefint_cal)
+		if (mask == IIO_CHAN_INFO_PROCESSED)
 			*val = STM32_ADC_VREFINT_VOLTAGE * adc->vrefint.vrefint_cal / *val;
 
 		iio_device_release_direct_mode(indio_dev);
@@ -1969,10 +1969,10 @@ static int stm32_adc_populate_int_ch(struct iio_dev *indio_dev, const char *ch_n
 
 	for (i = 0; i < STM32_ADC_INT_CH_NB; i++) {
 		if (!strncmp(stm32_adc_ic[i].name, ch_name, STM32_ADC_CH_SZ)) {
-			adc->int_ch[i] = chan;
-
-			if (stm32_adc_ic[i].idx != STM32_ADC_INT_CH_VREFINT)
-				continue;
+			if (stm32_adc_ic[i].idx != STM32_ADC_INT_CH_VREFINT) {
+				adc->int_ch[i] = chan;
+				break;
+			}
 
 			/* Get calibration data for vrefint channel */
 			ret = nvmem_cell_read_u16(&indio_dev->dev, "vrefint", &vrefint);
@@ -1980,10 +1980,15 @@ static int stm32_adc_populate_int_ch(struct iio_dev *indio_dev, const char *ch_n
 				return dev_err_probe(indio_dev->dev.parent, ret,
 						     "nvmem access error\n");
 			}
-			if (ret == -ENOENT)
-				dev_dbg(&indio_dev->dev, "vrefint calibration not found\n");
-			else
-				adc->vrefint.vrefint_cal = vrefint;
+			if (ret == -ENOENT) {
+				dev_dbg(&indio_dev->dev, "vrefint calibration not found. Skip vrefint channel\n");
+				return ret;
+			} else if (!vrefint) {
+				dev_dbg(&indio_dev->dev, "Null vrefint calibration value. Skip vrefint channel\n");
+				return -ENOENT;
+			}
+			adc->int_ch[i] = chan;
+			adc->vrefint.vrefint_cal = vrefint;
 		}
 	}
 
@@ -2020,7 +2025,9 @@ static int stm32_adc_generic_chan_init(struct iio_dev *indio_dev,
 			}
 			strncpy(adc->chan_name[val], name, STM32_ADC_CH_SZ);
 			ret = stm32_adc_populate_int_ch(indio_dev, name, val);
-			if (ret)
+			if (ret == -ENOENT)
+				continue;
+			else if (ret)
 				goto err;
 		} else if (ret != -EINVAL) {
 			dev_err(&indio_dev->dev, "Invalid label %d\n", ret);
-- 
GitLab


From 990539486e7e311fb5dab1bf4d85d1a8973ae644 Mon Sep 17 00:00:00 2001
From: Olivier Moysan <olivier.moysan@foss.st.com>
Date: Thu, 9 Jun 2022 11:52:34 +0200
Subject: [PATCH 0844/1731] iio: adc: stm32: fix maximum clock rate for
 stm32mp15x

Change maximum STM32 ADC input clock rate to 36MHz, as specified
in STM32MP15x datasheets.

Fixes: d58c67d1d851 ("iio: adc: stm32-adc: add support for STM32MP1")
Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Link: https://lore.kernel.org/r/20220609095234.375925-1-olivier.moysan@foss.st.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/stm32-adc-core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c
index bb04deeb7992a..3efb8c404ccc3 100644
--- a/drivers/iio/adc/stm32-adc-core.c
+++ b/drivers/iio/adc/stm32-adc-core.c
@@ -809,7 +809,7 @@ static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
 	.regs = &stm32h7_adc_common_regs,
 	.clk_sel = stm32h7_adc_clk_sel,
-	.max_clk_rate_hz = 40000000,
+	.max_clk_rate_hz = 36000000,
 	.has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD,
 	.num_irqs = 2,
 	.num_adcs = 2,
-- 
GitLab


From bf745142cc0a3e1723f9207fb0c073c88464b7b4 Mon Sep 17 00:00:00 2001
From: Haibo Chen <haibo.chen@nxp.com>
Date: Wed, 15 Jun 2022 19:31:58 +0800
Subject: [PATCH 0845/1731] iio: accel: mma8452: ignore the return value of
 reset operation

On fxls8471, after set the reset bit, the device will reset immediately,
will not give ACK. So ignore the return value of this reset operation,
let the following code logic to check whether the reset operation works.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Fixes: ecabae713196 ("iio: mma8452: Initialise before activating")
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/1655292718-14287-1-git-send-email-haibo.chen@nxp.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/accel/mma8452.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/iio/accel/mma8452.c b/drivers/iio/accel/mma8452.c
index 4156d216c640a..f4f835274d751 100644
--- a/drivers/iio/accel/mma8452.c
+++ b/drivers/iio/accel/mma8452.c
@@ -1510,10 +1510,14 @@ static int mma8452_reset(struct i2c_client *client)
 	int i;
 	int ret;
 
-	ret = i2c_smbus_write_byte_data(client,	MMA8452_CTRL_REG2,
+	/*
+	 * Find on fxls8471, after config reset bit, it reset immediately,
+	 * and will not give ACK, so here do not check the return value.
+	 * The following code will read the reset register, and check whether
+	 * this reset works.
+	 */
+	i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
 					MMA8452_CTRL_REG2_RST);
-	if (ret < 0)
-		return ret;
 
 	for (i = 0; i < 10; i++) {
 		usleep_range(100, 200);
-- 
GitLab


From 70171ed6dc53d2f580166d47f5b66cf51a6d0092 Mon Sep 17 00:00:00 2001
From: Aashish Sharma <shraash@google.com>
Date: Mon, 13 Jun 2022 16:22:24 -0700
Subject: [PATCH 0846/1731] iio:proximity:sx9324: Check ret value of
 device_property_read_u32_array()

0-day reports:

drivers/iio/proximity/sx9324.c:868:3: warning: Value stored
to 'ret' is never read [clang-analyzer-deadcode.DeadStores]

Put an if condition to break out of switch if ret is non-zero.

Signed-off-by: Aashish Sharma <shraash@google.com>
Fixes: a8ee3b32f5da ("iio:proximity:sx9324: Add dt_binding support")
Reported-by: kernel test robot <lkp@intel.com>
[swboyd@chromium.org: Reword commit subject, add fixes tag]
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Link: https://lore.kernel.org/r/20220613232224.2466278-1-swboyd@chromium.org
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/proximity/sx9324.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/iio/proximity/sx9324.c b/drivers/iio/proximity/sx9324.c
index 70c37f664f6da..63fbcaa4cac81 100644
--- a/drivers/iio/proximity/sx9324.c
+++ b/drivers/iio/proximity/sx9324.c
@@ -885,6 +885,9 @@ sx9324_get_default_reg(struct device *dev, int idx,
 			break;
 		ret = device_property_read_u32_array(dev, prop, pin_defs,
 						     ARRAY_SIZE(pin_defs));
+		if (ret)
+			break;
+
 		for (pin = 0; pin < SX9324_NUM_PINS; pin++)
 			raw |= (pin_defs[pin] << (2 * pin)) &
 			       SX9324_REG_AFE_PH0_PIN_MASK(pin);
-- 
GitLab


From a111daf0c53ae91e71fd2bfe7497862d14132e3e Mon Sep 17 00:00:00 2001
From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sun, 19 Jun 2022 15:06:47 -0500
Subject: [PATCH 0847/1731] Linux 5.19-rc3

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 1a6678d817bd1..513c1fbf7888b 100644
--- a/Makefile
+++ b/Makefile
@@ -2,7 +2,7 @@
 VERSION = 5
 PATCHLEVEL = 19
 SUBLEVEL = 0
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
 NAME = Superb Owl
 
 # *DOCUMENTATION*
-- 
GitLab


From 534d2eaf1970274150596fdd2bf552721e65d6b2 Mon Sep 17 00:00:00 2001
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
Date: Thu, 16 Jun 2022 02:03:12 +0200
Subject: [PATCH 0848/1731] random: schedule mix_interrupt_randomness() less
 often

It used to be that mix_interrupt_randomness() would credit 1 bit each
time it ran, and so add_interrupt_randomness() would schedule mix() to
run every 64 interrupts, a fairly arbitrary number, but nonetheless
considered to be a decent enough conservative estimate.

Since e3e33fc2ea7f ("random: do not use input pool from hard IRQs"),
mix() is now able to credit multiple bits, depending on the number of
calls to add(). This was done for reasons separate from this commit, but
it has the nice side effect of enabling this patch to schedule mix()
less often.

Currently the rules are:
a) Credit 1 bit for every 64 calls to add().
b) Schedule mix() once a second that add() is called.
c) Schedule mix() once every 64 calls to add().

Rules (a) and (c) no longer need to be coupled. It's still important to
have _some_ value in (c), so that we don't "over-saturate" the fast
pool, but the once per second we get from rule (b) is a plenty enough
baseline. So, by increasing the 64 in rule (c) to something larger, we
avoid calling queue_work_on() as frequently during irq storms.

This commit changes that 64 in rule (c) to be 1024, which means we
schedule mix() 16 times less often. And it does *not* need to change the
64 in rule (a).

Fixes: 58340f8e952b ("random: defer fast pool mixing to worker")
Cc: stable@vger.kernel.org
Cc: Dominik Brodowski <linux@dominikbrodowski.net>
Acked-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
---
 drivers/char/random.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/char/random.c b/drivers/char/random.c
index 655e327d425ec..d0e4c89c4fcb2 100644
--- a/drivers/char/random.c
+++ b/drivers/char/random.c
@@ -1009,7 +1009,7 @@ void add_interrupt_randomness(int irq)
 	if (new_count & MIX_INFLIGHT)
 		return;
 
-	if (new_count < 64 && !time_is_before_jiffies(fast_pool->last + HZ))
+	if (new_count < 1024 && !time_is_before_jiffies(fast_pool->last + HZ))
 		return;
 
 	if (unlikely(!fast_pool->mix.func))
-- 
GitLab


From c01d4d0a82b71857be7449380338bc53dde2da92 Mon Sep 17 00:00:00 2001
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
Date: Thu, 16 Jun 2022 15:00:51 +0200
Subject: [PATCH 0849/1731] random: quiet urandom warning ratelimit suppression
 message

random.c ratelimits how much it warns about uninitialized urandom reads
using __ratelimit(). When the RNG is finally initialized, it prints the
number of missed messages due to ratelimiting.

It has been this way since that functionality was introduced back in
2018. Recently, cc1e127bfa95 ("random: remove ratelimiting for in-kernel
unseeded randomness") put a bit more stress on the urandom ratelimiting,
which teased out a bug in the implementation.

Specifically, when under pressure, __ratelimit() will print its own
message and reset the count back to 0, making the final message at the
end less useful. Secondly, it does so as a pr_warn(), which apparently
is undesirable for people's CI.

Fortunately, __ratelimit() has the RATELIMIT_MSG_ON_RELEASE flag exactly
for this purpose, so we set the flag.

Fixes: 4e00b339e264 ("random: rate limit unseeded randomness warnings")
Cc: stable@vger.kernel.org
Reported-by: Jon Hunter <jonathanh@nvidia.com>
Reported-by: Ron Economos <re@w6rz.net>
Tested-by: Ron Economos <re@w6rz.net>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
---
 drivers/char/random.c           |  2 +-
 include/linux/ratelimit_types.h | 12 ++++++++----
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/char/random.c b/drivers/char/random.c
index d0e4c89c4fcb2..07a022e240573 100644
--- a/drivers/char/random.c
+++ b/drivers/char/random.c
@@ -87,7 +87,7 @@ static struct fasync_struct *fasync;
 
 /* Control how we warn userspace. */
 static struct ratelimit_state urandom_warning =
-	RATELIMIT_STATE_INIT("warn_urandom_randomness", HZ, 3);
+	RATELIMIT_STATE_INIT_FLAGS("urandom_warning", HZ, 3, RATELIMIT_MSG_ON_RELEASE);
 static int ratelimit_disable __read_mostly =
 	IS_ENABLED(CONFIG_WARN_ALL_UNSEEDED_RANDOM);
 module_param_named(ratelimit_disable, ratelimit_disable, int, 0644);
diff --git a/include/linux/ratelimit_types.h b/include/linux/ratelimit_types.h
index c21c7f8103e2b..002266693e506 100644
--- a/include/linux/ratelimit_types.h
+++ b/include/linux/ratelimit_types.h
@@ -23,12 +23,16 @@ struct ratelimit_state {
 	unsigned long	flags;
 };
 
-#define RATELIMIT_STATE_INIT(name, interval_init, burst_init) {		\
-		.lock		= __RAW_SPIN_LOCK_UNLOCKED(name.lock),	\
-		.interval	= interval_init,			\
-		.burst		= burst_init,				\
+#define RATELIMIT_STATE_INIT_FLAGS(name, interval_init, burst_init, flags_init) { \
+		.lock		= __RAW_SPIN_LOCK_UNLOCKED(name.lock),		  \
+		.interval	= interval_init,				  \
+		.burst		= burst_init,					  \
+		.flags		= flags_init,					  \
 	}
 
+#define RATELIMIT_STATE_INIT(name, interval_init, burst_init) \
+	RATELIMIT_STATE_INIT_FLAGS(name, interval_init, burst_init, 0)
+
 #define RATELIMIT_STATE_INIT_DISABLED					\
 	RATELIMIT_STATE_INIT(ratelimit_state, 0, DEFAULT_RATELIMIT_BURST)
 
-- 
GitLab


From 4cde00d50707c2ef6647b9b96b2cb40b6eb24397 Mon Sep 17 00:00:00 2001
From: Jaegeuk Kim <jaegeuk@kernel.org>
Date: Tue, 31 May 2022 18:27:09 -0700
Subject: [PATCH 0850/1731] f2fs: attach inline_data after setting compression

This fixes the below corruption.

[345393.335389] F2FS-fs (vdb): sanity_check_inode: inode (ino=6d0, mode=33206) should not have inline_data, run fsck to fix

Cc: <stable@vger.kernel.org>
Fixes: 677a82b44ebf ("f2fs: fix to do sanity check for inline inode")
Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
---
 fs/f2fs/namei.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/fs/f2fs/namei.c b/fs/f2fs/namei.c
index c549acb52ac47..bf00d5057abb8 100644
--- a/fs/f2fs/namei.c
+++ b/fs/f2fs/namei.c
@@ -89,8 +89,6 @@ static struct inode *f2fs_new_inode(struct user_namespace *mnt_userns,
 	if (test_opt(sbi, INLINE_XATTR))
 		set_inode_flag(inode, FI_INLINE_XATTR);
 
-	if (test_opt(sbi, INLINE_DATA) && f2fs_may_inline_data(inode))
-		set_inode_flag(inode, FI_INLINE_DATA);
 	if (f2fs_may_inline_dentry(inode))
 		set_inode_flag(inode, FI_INLINE_DENTRY);
 
@@ -107,10 +105,6 @@ static struct inode *f2fs_new_inode(struct user_namespace *mnt_userns,
 
 	f2fs_init_extent_tree(inode, NULL);
 
-	stat_inc_inline_xattr(inode);
-	stat_inc_inline_inode(inode);
-	stat_inc_inline_dir(inode);
-
 	F2FS_I(inode)->i_flags =
 		f2fs_mask_flags(mode, F2FS_I(dir)->i_flags & F2FS_FL_INHERITED);
 
@@ -127,6 +121,14 @@ static struct inode *f2fs_new_inode(struct user_namespace *mnt_userns,
 			set_compress_context(inode);
 	}
 
+	/* Should enable inline_data after compression set */
+	if (test_opt(sbi, INLINE_DATA) && f2fs_may_inline_data(inode))
+		set_inode_flag(inode, FI_INLINE_DATA);
+
+	stat_inc_inline_xattr(inode);
+	stat_inc_inline_inode(inode);
+	stat_inc_inline_dir(inode);
+
 	f2fs_set_inode_flags(inode);
 
 	trace_f2fs_new_inode(inode, 0);
@@ -325,6 +327,9 @@ static void set_compress_inode(struct f2fs_sb_info *sbi, struct inode *inode,
 		if (!is_extension_exist(name, ext[i], false))
 			continue;
 
+		/* Do not use inline_data with compression */
+		stat_dec_inline_inode(inode);
+		clear_inode_flag(inode, FI_INLINE_DATA);
 		set_compress_context(inode);
 		return;
 	}
-- 
GitLab


From 61803e984307c767a96d85f3b61ca50e1705fc67 Mon Sep 17 00:00:00 2001
From: Daeho Jeong <daehojeong@google.com>
Date: Fri, 10 Jun 2022 11:32:40 -0700
Subject: [PATCH 0851/1731] f2fs: fix iostat related lock protection

Made iostat related locks safe to be called from irq context again.

Cc: <stable@vger.kernel.org>
Fixes: a1e09b03e6f5 ("f2fs: use iomap for direct I/O")
Signed-off-by: Daeho Jeong <daehojeong@google.com>
Reviewed-by: Stanley Chu <stanley.chu@mediatek.com>
Tested-by: Eddie Huang <eddie.huang@mediatek.com>
Reviewed-by: Chao Yu <chao@kernel.org>
Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
---
 fs/f2fs/iostat.c | 31 ++++++++++++++++++-------------
 1 file changed, 18 insertions(+), 13 deletions(-)

diff --git a/fs/f2fs/iostat.c b/fs/f2fs/iostat.c
index be599f31d3c48..d84c5f6cc09d7 100644
--- a/fs/f2fs/iostat.c
+++ b/fs/f2fs/iostat.c
@@ -91,8 +91,9 @@ static inline void __record_iostat_latency(struct f2fs_sb_info *sbi)
 	unsigned int cnt;
 	struct f2fs_iostat_latency iostat_lat[MAX_IO_TYPE][NR_PAGE_TYPE];
 	struct iostat_lat_info *io_lat = sbi->iostat_io_lat;
+	unsigned long flags;
 
-	spin_lock_bh(&sbi->iostat_lat_lock);
+	spin_lock_irqsave(&sbi->iostat_lat_lock, flags);
 	for (idx = 0; idx < MAX_IO_TYPE; idx++) {
 		for (io = 0; io < NR_PAGE_TYPE; io++) {
 			cnt = io_lat->bio_cnt[idx][io];
@@ -106,7 +107,7 @@ static inline void __record_iostat_latency(struct f2fs_sb_info *sbi)
 			io_lat->bio_cnt[idx][io] = 0;
 		}
 	}
-	spin_unlock_bh(&sbi->iostat_lat_lock);
+	spin_unlock_irqrestore(&sbi->iostat_lat_lock, flags);
 
 	trace_f2fs_iostat_latency(sbi, iostat_lat);
 }
@@ -115,14 +116,15 @@ static inline void f2fs_record_iostat(struct f2fs_sb_info *sbi)
 {
 	unsigned long long iostat_diff[NR_IO_TYPE];
 	int i;
+	unsigned long flags;
 
 	if (time_is_after_jiffies(sbi->iostat_next_period))
 		return;
 
 	/* Need double check under the lock */
-	spin_lock_bh(&sbi->iostat_lock);
+	spin_lock_irqsave(&sbi->iostat_lock, flags);
 	if (time_is_after_jiffies(sbi->iostat_next_period)) {
-		spin_unlock_bh(&sbi->iostat_lock);
+		spin_unlock_irqrestore(&sbi->iostat_lock, flags);
 		return;
 	}
 	sbi->iostat_next_period = jiffies +
@@ -133,7 +135,7 @@ static inline void f2fs_record_iostat(struct f2fs_sb_info *sbi)
 				sbi->prev_rw_iostat[i];
 		sbi->prev_rw_iostat[i] = sbi->rw_iostat[i];
 	}
-	spin_unlock_bh(&sbi->iostat_lock);
+	spin_unlock_irqrestore(&sbi->iostat_lock, flags);
 
 	trace_f2fs_iostat(sbi, iostat_diff);
 
@@ -145,25 +147,27 @@ void f2fs_reset_iostat(struct f2fs_sb_info *sbi)
 	struct iostat_lat_info *io_lat = sbi->iostat_io_lat;
 	int i;
 
-	spin_lock_bh(&sbi->iostat_lock);
+	spin_lock_irq(&sbi->iostat_lock);
 	for (i = 0; i < NR_IO_TYPE; i++) {
 		sbi->rw_iostat[i] = 0;
 		sbi->prev_rw_iostat[i] = 0;
 	}
-	spin_unlock_bh(&sbi->iostat_lock);
+	spin_unlock_irq(&sbi->iostat_lock);
 
-	spin_lock_bh(&sbi->iostat_lat_lock);
+	spin_lock_irq(&sbi->iostat_lat_lock);
 	memset(io_lat, 0, sizeof(struct iostat_lat_info));
-	spin_unlock_bh(&sbi->iostat_lat_lock);
+	spin_unlock_irq(&sbi->iostat_lat_lock);
 }
 
 void f2fs_update_iostat(struct f2fs_sb_info *sbi,
 			enum iostat_type type, unsigned long long io_bytes)
 {
+	unsigned long flags;
+
 	if (!sbi->iostat_enable)
 		return;
 
-	spin_lock_bh(&sbi->iostat_lock);
+	spin_lock_irqsave(&sbi->iostat_lock, flags);
 	sbi->rw_iostat[type] += io_bytes;
 
 	if (type == APP_BUFFERED_IO || type == APP_DIRECT_IO)
@@ -172,7 +176,7 @@ void f2fs_update_iostat(struct f2fs_sb_info *sbi,
 	if (type == APP_BUFFERED_READ_IO || type == APP_DIRECT_READ_IO)
 		sbi->rw_iostat[APP_READ_IO] += io_bytes;
 
-	spin_unlock_bh(&sbi->iostat_lock);
+	spin_unlock_irqrestore(&sbi->iostat_lock, flags);
 
 	f2fs_record_iostat(sbi);
 }
@@ -185,6 +189,7 @@ static inline void __update_iostat_latency(struct bio_iostat_ctx *iostat_ctx,
 	struct f2fs_sb_info *sbi = iostat_ctx->sbi;
 	struct iostat_lat_info *io_lat = sbi->iostat_io_lat;
 	int idx;
+	unsigned long flags;
 
 	if (!sbi->iostat_enable)
 		return;
@@ -202,12 +207,12 @@ static inline void __update_iostat_latency(struct bio_iostat_ctx *iostat_ctx,
 			idx = WRITE_ASYNC_IO;
 	}
 
-	spin_lock_bh(&sbi->iostat_lat_lock);
+	spin_lock_irqsave(&sbi->iostat_lat_lock, flags);
 	io_lat->sum_lat[idx][iotype] += ts_diff;
 	io_lat->bio_cnt[idx][iotype]++;
 	if (ts_diff > io_lat->peak_lat[idx][iotype])
 		io_lat->peak_lat[idx][iotype] = ts_diff;
-	spin_unlock_bh(&sbi->iostat_lat_lock);
+	spin_unlock_irqrestore(&sbi->iostat_lat_lock, flags);
 }
 
 void iostat_update_and_unbind_ctx(struct bio *bio, int rw)
-- 
GitLab


From 28438794aba47a27e922857d27b31b74e8559143 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <masahiroy@kernel.org>
Date: Sat, 11 Jun 2022 03:32:30 +0900
Subject: [PATCH 0852/1731] modpost: fix section mismatch check for exported
 init/exit sections

Since commit f02e8a6596b7 ("module: Sort exported symbols"),
EXPORT_SYMBOL* is placed in the individual section ___ksymtab(_gpl)+<sym>
(3 leading underscores instead of 2).

Since then, modpost cannot detect the bad combination of EXPORT_SYMBOL
and __init/__exit.

Fix the .fromsec field.

Fixes: f02e8a6596b7 ("module: Sort exported symbols")
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
---
 scripts/mod/modpost.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/mod/modpost.c b/scripts/mod/modpost.c
index 29d5a841e2150..620dc8c4c8140 100644
--- a/scripts/mod/modpost.c
+++ b/scripts/mod/modpost.c
@@ -980,7 +980,7 @@ static const struct sectioncheck sectioncheck[] = {
 },
 /* Do not export init/exit functions or data */
 {
-	.fromsec = { "__ksymtab*", NULL },
+	.fromsec = { "___ksymtab*", NULL },
 	.bad_tosec = { INIT_SECTIONS, EXIT_SECTIONS, NULL },
 	.mismatch = EXPORT_TO_INIT_EXIT,
 	.symbol_white_list = { DEFAULT_SYMBOL_WHITE_LIST, NULL },
-- 
GitLab


From 291810be4227564403807e663f3ec8d3b3d6ba34 Mon Sep 17 00:00:00 2001
From: Nick Desaulniers <ndesaulniers@google.com>
Date: Fri, 17 Jun 2022 09:58:17 -0700
Subject: [PATCH 0853/1731] Documentation/llvm: Update Supported Arch table

While watching Michael's new talk on Clang-built-Linux, I noticed the
arch table in our docs that he refers to is outdated.

Add hexagon and User Mode.  Bump MIPS and RISCV to LLVM=1.  PowerPC is
almost LLVM=1 capable; ppc64le works, but ppc64 (big endian) and ppc32
still need more work.

Link: https://youtu.be/W4zdEDpvR5c?t=399
Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
Reviewed-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
---
 Documentation/kbuild/llvm.rst | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/kbuild/llvm.rst b/Documentation/kbuild/llvm.rst
index b854bb4131647..6b2bac8e9ce08 100644
--- a/Documentation/kbuild/llvm.rst
+++ b/Documentation/kbuild/llvm.rst
@@ -129,18 +129,24 @@ yet. Bug reports are always welcome at the issue tracker below!
    * - arm64
      - Supported
      - ``LLVM=1``
+   * - hexagon
+     - Maintained
+     - ``LLVM=1``
    * - mips
      - Maintained
-     - ``CC=clang``
+     - ``LLVM=1``
    * - powerpc
      - Maintained
      - ``CC=clang``
    * - riscv
      - Maintained
-     - ``CC=clang``
+     - ``LLVM=1``
    * - s390
      - Maintained
      - ``CC=clang``
+   * - um (User Mode)
+     - Maintained
+     - ``LLVM=1``
    * - x86
      - Supported
      - ``LLVM=1``
-- 
GitLab


From 9243fc4cd28c8bdddd7fe0abd5bbec3c4fdf5052 Mon Sep 17 00:00:00 2001
From: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Date: Fri, 3 Jun 2022 14:35:29 +0900
Subject: [PATCH 0854/1731] block: remove queue from struct
 blk_independent_access_range

The request queue pointer in struct blk_independent_access_range is
unused. Remove it.

Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Fixes: 41e46b3c2aa2 ("block: Fix potential deadlock in blk_ia_range_sysfs_show()")
Reviewed-by: Christoph Hellwig <hch@lst.de>
Link: https://lore.kernel.org/r/20220603053529.76405-1-damien.lemoal@opensource.wdc.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 block/blk-ia-ranges.c  | 1 -
 include/linux/blkdev.h | 1 -
 2 files changed, 2 deletions(-)

diff --git a/block/blk-ia-ranges.c b/block/blk-ia-ranges.c
index 56ed48d2954e6..47c89e65b57fa 100644
--- a/block/blk-ia-ranges.c
+++ b/block/blk-ia-ranges.c
@@ -144,7 +144,6 @@ int disk_register_independent_access_ranges(struct gendisk *disk,
 	}
 
 	for (i = 0; i < iars->nr_ia_ranges; i++) {
-		iars->ia_range[i].queue = q;
 		ret = kobject_init_and_add(&iars->ia_range[i].kobj,
 					   &blk_ia_range_ktype, &iars->kobj,
 					   "%d", i);
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index 73c886eba8e19..2f7b43444c5f8 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -342,7 +342,6 @@ static inline int blkdev_zone_mgmt_ioctl(struct block_device *bdev,
  */
 struct blk_independent_access_range {
 	struct kobject		kobj;
-	struct request_queue	*queue;
 	sector_t		sector;
 	sector_t		nr_sectors;
 };
-- 
GitLab


From 9882d63bea14c8b3ed2c9360b9ab9f0e2f64ae2b Mon Sep 17 00:00:00 2001
From: Takashi Iwai <tiwai@suse.de>
Date: Mon, 20 Jun 2022 09:34:40 +0200
Subject: [PATCH 0855/1731] ALSA: memalloc: Drop x86-specific hack for WC
 allocations

The recent report for a crash on Haswell machines implied that the
x86-specific (rather hackish) implementation for write-cache memory
buffer allocation in ALSA core is buggy with the recent kernel in some
corner cases.  This patch drops the x86-specific implementation and
uses the standard dma_alloc_wc() & co generically for avoiding the bug
and also for simplification.

BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=216112
Cc: <stable@vger.kernel.org> # v5.18+
Link: https://lore.kernel.org/r/20220620073440.7514-1-tiwai@suse.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/core/memalloc.c | 23 +----------------------
 1 file changed, 1 insertion(+), 22 deletions(-)

diff --git a/sound/core/memalloc.c b/sound/core/memalloc.c
index 15dc7160ba34e..8cfdaee779050 100644
--- a/sound/core/memalloc.c
+++ b/sound/core/memalloc.c
@@ -431,33 +431,17 @@ static const struct snd_malloc_ops snd_dma_iram_ops = {
  */
 static void *snd_dma_dev_alloc(struct snd_dma_buffer *dmab, size_t size)
 {
-	void *p;
-
-	p = dma_alloc_coherent(dmab->dev.dev, size, &dmab->addr, DEFAULT_GFP);
-#ifdef CONFIG_X86
-	if (p && dmab->dev.type == SNDRV_DMA_TYPE_DEV_WC)
-		set_memory_wc((unsigned long)p, PAGE_ALIGN(size) >> PAGE_SHIFT);
-#endif
-	return p;
+	return dma_alloc_coherent(dmab->dev.dev, size, &dmab->addr, DEFAULT_GFP);
 }
 
 static void snd_dma_dev_free(struct snd_dma_buffer *dmab)
 {
-#ifdef CONFIG_X86
-	if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_WC)
-		set_memory_wb((unsigned long)dmab->area,
-			      PAGE_ALIGN(dmab->bytes) >> PAGE_SHIFT);
-#endif
 	dma_free_coherent(dmab->dev.dev, dmab->bytes, dmab->area, dmab->addr);
 }
 
 static int snd_dma_dev_mmap(struct snd_dma_buffer *dmab,
 			    struct vm_area_struct *area)
 {
-#ifdef CONFIG_X86
-	if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_WC)
-		area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
-#endif
 	return dma_mmap_coherent(dmab->dev.dev, area,
 				 dmab->area, dmab->addr, dmab->bytes);
 }
@@ -471,10 +455,6 @@ static const struct snd_malloc_ops snd_dma_dev_ops = {
 /*
  * Write-combined pages
  */
-#ifdef CONFIG_X86
-/* On x86, share the same ops as the standard dev ops */
-#define snd_dma_wc_ops	snd_dma_dev_ops
-#else /* CONFIG_X86 */
 static void *snd_dma_wc_alloc(struct snd_dma_buffer *dmab, size_t size)
 {
 	return dma_alloc_wc(dmab->dev.dev, size, &dmab->addr, DEFAULT_GFP);
@@ -497,7 +477,6 @@ static const struct snd_malloc_ops snd_dma_wc_ops = {
 	.free = snd_dma_wc_free,
 	.mmap = snd_dma_wc_mmap,
 };
-#endif /* CONFIG_X86 */
 
 #ifdef CONFIG_SND_DMA_SGBUF
 static void *snd_dma_sg_fallback_alloc(struct snd_dma_buffer *dmab, size_t size);
-- 
GitLab


From 2ef6efa79fecd5e3457b324155d35524d95f2b6b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= <thomas.hellstrom@linux.intel.com>
Date: Fri, 17 Jun 2022 17:28:55 +0200
Subject: [PATCH 0856/1731] drm/i915: Improve on suspend / resume time with
 VT-d enabled
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When DMAR / VT-d is enabled, the display engine uses overfetching,
presumably to deal with the increased latency. To avoid display engine
errors and DMAR faults, as a workaround the GGTT is populated with scatch
PTEs when VT-d is enabled. However starting with gen10, Write-combined
writing of scratch PTES is no longer possible and as a result, populating
the full GGTT with scratch PTEs like on resume becomes very slow as
uncached access is needed.

Therefore, on integrated GPUs utilize the fact that the PTEs are stored in
stolen memory which retain content across S3 suspend. Don't clear the PTEs
on suspend and resume. This improves on resume time with around 100 ms.
While 100+ms might appear like a short time it's 10% to 20% of total resume
time and important in some applications.

One notable exception is Intel Rapid Start Technology which may cause
stolen memory to be lost across what the OS percieves as S3 suspend.
If IRST is enabled or if we can't detect whether IRST is enabled, retain
the old workaround, clearing and re-instating PTEs.

As an additional measure, if we detect that the last ggtt pte was lost
during suspend, print a warning and re-populate the GGTT ptes

On discrete GPUs, the display engine scans out from LMEM which isn't
subject to DMAR, and presumably the workaround is therefore not needed,
but that needs to be verified and disabling the workaround for dGPU,
if possible, will be deferred to a follow-up patch.

v2:
- Rely on retained ptes to also speed up suspend and resume re-binding.
- Re-build GGTT ptes if Intel rst is enabled.
v3:
- Re-build GGTT ptes also if we can't detect whether Intel rst is enabled,
  and if the guard page PTE and end of GGTT was lost.
v4:
- Fix some kerneldoc issues (Matthew Auld), rebase.

Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220617152856.249295-1-thomas.hellstrom@linux.intel.com
---
 drivers/gpu/drm/i915/gt/intel_ggtt.c | 56 +++++++++++++++++++++++++---
 drivers/gpu/drm/i915/gt/intel_gtt.h  | 24 ++++++++++++
 drivers/gpu/drm/i915/i915_driver.c   | 16 ++++++++
 3 files changed, 90 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index e6b2eb122ad7e..0849a6f66309f 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -22,6 +22,13 @@
 #include "intel_gtt.h"
 #include "gen8_ppgtt.h"
 
+static inline bool suspend_retains_ptes(struct i915_address_space *vm)
+{
+	return GRAPHICS_VER(vm->i915) >= 8 &&
+		!HAS_LMEM(vm->i915) &&
+		vm->is_ggtt;
+}
+
 static void i915_ggtt_color_adjust(const struct drm_mm_node *node,
 				   unsigned long color,
 				   u64 *start,
@@ -93,6 +100,23 @@ int i915_ggtt_init_hw(struct drm_i915_private *i915)
 	return 0;
 }
 
+/*
+ * Return the value of the last GGTT pte cast to an u64, if
+ * the system is supposed to retain ptes across resume. 0 otherwise.
+ */
+static u64 read_last_pte(struct i915_address_space *vm)
+{
+	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+	gen8_pte_t __iomem *ptep;
+
+	if (!suspend_retains_ptes(vm))
+		return 0;
+
+	GEM_BUG_ON(GRAPHICS_VER(vm->i915) < 8);
+	ptep = (typeof(ptep))ggtt->gsm + (ggtt_total_entries(ggtt) - 1);
+	return readq(ptep);
+}
+
 /**
  * i915_ggtt_suspend_vm - Suspend the memory mappings for a GGTT or DPT VM
  * @vm: The VM to suspend the mappings for
@@ -156,7 +180,10 @@ retry:
 		i915_gem_object_unlock(obj);
 	}
 
-	vm->clear_range(vm, 0, vm->total);
+	if (!suspend_retains_ptes(vm))
+		vm->clear_range(vm, 0, vm->total);
+	else
+		i915_vm_to_ggtt(vm)->probed_pte = read_last_pte(vm);
 
 	vm->skip_pte_rewrite = save_skip_rewrite;
 
@@ -299,6 +326,8 @@ static int init_ggtt(struct i915_ggtt *ggtt)
 	struct drm_mm_node *entry;
 	int ret;
 
+	ggtt->pte_lost = true;
+
 	/*
 	 * GuC requires all resources that we're sharing with it to be placed in
 	 * non-WOPCM memory. If GuC is not present or not in use we still need a
@@ -675,11 +704,20 @@ bool i915_ggtt_resume_vm(struct i915_address_space *vm)
 {
 	struct i915_vma *vma;
 	bool write_domain_objs = false;
+	bool retained_ptes;
 
 	drm_WARN_ON(&vm->i915->drm, !vm->is_ggtt && !vm->is_dpt);
 
-	/* First fill our portion of the GTT with scratch pages */
-	vm->clear_range(vm, 0, vm->total);
+	/*
+	 * First fill our portion of the GTT with scratch pages if
+	 * they were not retained across suspend.
+	 */
+	retained_ptes = suspend_retains_ptes(vm) &&
+		!i915_vm_to_ggtt(vm)->pte_lost &&
+		!GEM_WARN_ON(i915_vm_to_ggtt(vm)->probed_pte != read_last_pte(vm));
+
+	if (!retained_ptes)
+		vm->clear_range(vm, 0, vm->total);
 
 	/* clflush objects bound into the GGTT and rebind them. */
 	list_for_each_entry(vma, &vm->bound_list, vm_link) {
@@ -688,9 +726,10 @@ bool i915_ggtt_resume_vm(struct i915_address_space *vm)
 			atomic_read(&vma->flags) & I915_VMA_BIND_MASK;
 
 		GEM_BUG_ON(!was_bound);
-		vma->ops->bind_vma(vm, NULL, vma->resource,
-				   obj ? obj->cache_level : 0,
-				   was_bound);
+		if (!retained_ptes)
+			vma->ops->bind_vma(vm, NULL, vma->resource,
+					   obj ? obj->cache_level : 0,
+					   was_bound);
 		if (obj) { /* only used during resume => exclusive access */
 			write_domain_objs |= fetch_and_zero(&obj->write_domain);
 			obj->read_domains |= I915_GEM_DOMAIN_GTT;
@@ -718,3 +757,8 @@ void i915_ggtt_resume(struct i915_ggtt *ggtt)
 
 	intel_ggtt_restore_fences(ggtt);
 }
+
+void i915_ggtt_mark_pte_lost(struct drm_i915_private *i915, bool val)
+{
+	to_gt(i915)->ggtt->pte_lost = val;
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index a40d928b38884..128b31476938f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -345,6 +345,19 @@ struct i915_ggtt {
 
 	bool do_idle_maps;
 
+	/**
+	 * @pte_lost: Are ptes lost on resume?
+	 *
+	 * Whether the system was recently restored from hibernate and
+	 * thus may have lost pte content.
+	 */
+	bool pte_lost;
+
+	/**
+	 * @probed_pte: Probed pte value on suspend. Re-checked on resume.
+	 */
+	u64 probed_pte;
+
 	int mtrr;
 
 	/** Bit 6 swizzling required for X tiling */
@@ -581,6 +594,17 @@ bool i915_ggtt_resume_vm(struct i915_address_space *vm);
 void i915_ggtt_suspend(struct i915_ggtt *gtt);
 void i915_ggtt_resume(struct i915_ggtt *ggtt);
 
+/**
+ * i915_ggtt_mark_pte_lost - Mark ggtt ptes as lost or clear such a marking
+ * @i915 The device private.
+ * @val whether the ptes should be marked as lost.
+ *
+ * In some cases pte content is retained across suspend, but typically lost
+ * across hibernate. Typically they should be marked as lost on
+ * hibernation restore and such marking cleared on suspend.
+ */
+void i915_ggtt_mark_pte_lost(struct drm_i915_private *i915, bool val);
+
 void
 fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count);
 
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index d26dcca7e654a..0e224761d0ed8 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -100,6 +100,9 @@
 #include "intel_region_ttm.h"
 #include "vlv_suspend.h"
 
+/* Intel Rapid Start Technology ACPI device name */
+static const char irst_name[] = "INT3392";
+
 static const struct drm_driver i915_drm_driver;
 
 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
@@ -1441,6 +1444,8 @@ static int i915_pm_suspend(struct device *kdev)
 		return -ENODEV;
 	}
 
+	i915_ggtt_mark_pte_lost(i915, false);
+
 	if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
 		return 0;
 
@@ -1493,6 +1498,14 @@ static int i915_pm_resume(struct device *kdev)
 	if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
 		return 0;
 
+	/*
+	 * If IRST is enabled, or if we can't detect whether it's enabled,
+	 * then we must assume we lost the GGTT page table entries, since
+	 * they are not retained if IRST decided to enter S4.
+	 */
+	if (!IS_ENABLED(CONFIG_ACPI) || acpi_dev_present(irst_name, NULL, -1))
+		i915_ggtt_mark_pte_lost(i915, true);
+
 	return i915_drm_resume(&i915->drm);
 }
 
@@ -1552,6 +1565,9 @@ static int i915_pm_restore_early(struct device *kdev)
 
 static int i915_pm_restore(struct device *kdev)
 {
+	struct drm_i915_private *i915 = kdev_to_i915(kdev);
+
+	i915_ggtt_mark_pte_lost(i915, true);
 	return i915_pm_resume(kdev);
 }
 
-- 
GitLab


From 313c502fa3b3494159cb8f18d4a6444d06c5c9a5 Mon Sep 17 00:00:00 2001
From: Riccardo Paolo Bestetti <pbl@bestov.io>
Date: Sun, 19 Jun 2022 18:27:35 +0200
Subject: [PATCH 0857/1731] ipv4: fix bind address validity regression tests

Commit 8ff978b8b222 ("ipv4/raw: support binding to nonlocal addresses")
introduces support for binding to nonlocal addresses, as well as some
basic test coverage for some of the related cases.

Commit b4a028c4d031 ("ipv4: ping: fix bind address validity check")
fixes a regression which incorrectly removed some checks for bind
address validation. In addition, it introduces regression tests for
those specific checks. However, those regression tests are defective, in
that they perform the tests using an incorrect combination of bind
flags. As a result, those tests fail when they should succeed.

This commit introduces additional regression tests for nonlocal binding
and fixes the defective regression tests. It also introduces new
set_sysctl calls for the ipv4_bind test group, as to perform the ICMP
binding tests it is necessary to allow ICMP socket creation by setting
the net.ipv4.ping_group_range knob.

Fixes: b4a028c4d031 ("ipv4: ping: fix bind address validity check")
Reported-by: Riccardo Paolo Bestetti <pbl@bestov.io>
Signed-off-by: Riccardo Paolo Bestetti <pbl@bestov.io>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 tools/testing/selftests/net/fcnal-test.sh | 36 +++++++++++++++++------
 1 file changed, 27 insertions(+), 9 deletions(-)

diff --git a/tools/testing/selftests/net/fcnal-test.sh b/tools/testing/selftests/net/fcnal-test.sh
index 75223b63e3c88..03b586760164a 100755
--- a/tools/testing/selftests/net/fcnal-test.sh
+++ b/tools/testing/selftests/net/fcnal-test.sh
@@ -1800,24 +1800,32 @@ ipv4_addr_bind_novrf()
 	done
 
 	#
-	# raw socket with nonlocal bind
+	# tests for nonlocal bind
 	#
 	a=${NL_IP}
 	log_start
-	run_cmd nettest -s -R -P icmp -f -l ${a} -I ${NSA_DEV} -b
-	log_test_addr ${a} $? 0 "Raw socket bind to nonlocal address after device bind"
+	run_cmd nettest -s -R -f -l ${a} -b
+	log_test_addr ${a} $? 0 "Raw socket bind to nonlocal address"
+
+	log_start
+	run_cmd nettest -s -f -l ${a} -b
+	log_test_addr ${a} $? 0 "TCP socket bind to nonlocal address"
+
+	log_start
+	run_cmd nettest -s -D -P icmp -f -l ${a} -b
+	log_test_addr ${a} $? 0 "ICMP socket bind to nonlocal address"
 
 	#
 	# check that ICMP sockets cannot bind to broadcast and multicast addresses
 	#
 	a=${BCAST_IP}
 	log_start
-	run_cmd nettest -s -R -P icmp -l ${a} -b
+	run_cmd nettest -s -D -P icmp -l ${a} -b
 	log_test_addr ${a} $? 1 "ICMP socket bind to broadcast address"
 
 	a=${MCAST_IP}
 	log_start
-	run_cmd nettest -s -R -P icmp -f -l ${a} -b
+	run_cmd nettest -s -D -P icmp -l ${a} -b
 	log_test_addr ${a} $? 1 "ICMP socket bind to multicast address"
 
 	#
@@ -1870,24 +1878,32 @@ ipv4_addr_bind_vrf()
 	log_test_addr ${a} $? 1 "Raw socket bind to out of scope address after VRF bind"
 
 	#
-	# raw socket with nonlocal bind
+	# tests for nonlocal bind
 	#
 	a=${NL_IP}
 	log_start
-	run_cmd nettest -s -R -P icmp -f -l ${a} -I ${VRF} -b
+	run_cmd nettest -s -R -f -l ${a} -I ${VRF} -b
 	log_test_addr ${a} $? 0 "Raw socket bind to nonlocal address after VRF bind"
 
+	log_start
+	run_cmd nettest -s -f -l ${a} -I ${VRF} -b
+	log_test_addr ${a} $? 0 "TCP socket bind to nonlocal address after VRF bind"
+
+	log_start
+	run_cmd nettest -s -D -P icmp -f -l ${a} -I ${VRF} -b
+	log_test_addr ${a} $? 0 "ICMP socket bind to nonlocal address after VRF bind"
+
 	#
 	# check that ICMP sockets cannot bind to broadcast and multicast addresses
 	#
 	a=${BCAST_IP}
 	log_start
-	run_cmd nettest -s -R -P icmp -l ${a} -I ${VRF} -b
+	run_cmd nettest -s -D -P icmp -l ${a} -I ${VRF} -b
 	log_test_addr ${a} $? 1 "ICMP socket bind to broadcast address after VRF bind"
 
 	a=${MCAST_IP}
 	log_start
-	run_cmd nettest -s -R -P icmp -f -l ${a} -I ${VRF} -b
+	run_cmd nettest -s -D -P icmp -l ${a} -I ${VRF} -b
 	log_test_addr ${a} $? 1 "ICMP socket bind to multicast address after VRF bind"
 
 	#
@@ -1922,10 +1938,12 @@ ipv4_addr_bind()
 
 	log_subsection "No VRF"
 	setup
+	set_sysctl net.ipv4.ping_group_range='0 2147483647' 2>/dev/null
 	ipv4_addr_bind_novrf
 
 	log_subsection "With VRF"
 	setup "yes"
+	set_sysctl net.ipv4.ping_group_range='0 2147483647' 2>/dev/null
 	ipv4_addr_bind_vrf
 }
 
-- 
GitLab


From 301bd140ed0b24f0da660874c7e8a47dad8c8222 Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Mon, 20 Jun 2022 01:35:06 -0700
Subject: [PATCH 0858/1731] erspan: do not assume transport header is always
 set

Rewrite tests in ip6erspan_tunnel_xmit() and
erspan_fb_xmit() to not assume transport header is set.

syzbot reported:

WARNING: CPU: 0 PID: 1350 at include/linux/skbuff.h:2911 skb_transport_header include/linux/skbuff.h:2911 [inline]
WARNING: CPU: 0 PID: 1350 at include/linux/skbuff.h:2911 ip6erspan_tunnel_xmit+0x15af/0x2eb0 net/ipv6/ip6_gre.c:963
Modules linked in:
CPU: 0 PID: 1350 Comm: aoe_tx0 Not tainted 5.19.0-rc2-syzkaller-00160-g274295c6e53f #0
Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS 1.14.0-2 04/01/2014
RIP: 0010:skb_transport_header include/linux/skbuff.h:2911 [inline]
RIP: 0010:ip6erspan_tunnel_xmit+0x15af/0x2eb0 net/ipv6/ip6_gre.c:963
Code: 0f 47 f0 40 88 b5 7f fe ff ff e8 8c 16 4b f9 89 de bf ff ff ff ff e8 a0 12 4b f9 66 83 fb ff 0f 85 1d f1 ff ff e8 71 16 4b f9 <0f> 0b e9 43 f0 ff ff e8 65 16 4b f9 48 8d 85 30 ff ff ff ba 60 00
RSP: 0018:ffffc90005daf910 EFLAGS: 00010293
RAX: 0000000000000000 RBX: 000000000000ffff RCX: 0000000000000000
RDX: ffff88801f032100 RSI: ffffffff882e8d3f RDI: 0000000000000003
RBP: ffffc90005dafab8 R08: 0000000000000003 R09: 000000000000ffff
R10: 000000000000ffff R11: 0000000000000000 R12: ffff888024f21d40
R13: 000000000000a288 R14: 00000000000000b0 R15: ffff888025a2e000
FS: 0000000000000000(0000) GS:ffff88802c800000(0000) knlGS:0000000000000000
CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 0000001b2e425000 CR3: 000000006d099000 CR4: 0000000000152ef0
Call Trace:
<TASK>
__netdev_start_xmit include/linux/netdevice.h:4805 [inline]
netdev_start_xmit include/linux/netdevice.h:4819 [inline]
xmit_one net/core/dev.c:3588 [inline]
dev_hard_start_xmit+0x188/0x880 net/core/dev.c:3604
sch_direct_xmit+0x19f/0xbe0 net/sched/sch_generic.c:342
__dev_xmit_skb net/core/dev.c:3815 [inline]
__dev_queue_xmit+0x14a1/0x3900 net/core/dev.c:4219
dev_queue_xmit include/linux/netdevice.h:2994 [inline]
tx+0x6a/0xc0 drivers/block/aoe/aoenet.c:63
kthread+0x1e7/0x3b0 drivers/block/aoe/aoecmd.c:1229
kthread+0x2e9/0x3a0 kernel/kthread.c:376
ret_from_fork+0x1f/0x30 arch/x86/entry/entry_64.S:302
</TASK>

Fixes: d5db21a3e697 ("erspan: auto detect truncated ipv6 packets.")
Reported-by: syzbot <syzkaller@googlegroups.com>
Signed-off-by: Eric Dumazet <edumazet@google.com>
Cc: William Tu <u9012063@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/ipv4/ip_gre.c  | 15 ++++++++++-----
 net/ipv6/ip6_gre.c | 15 ++++++++++-----
 2 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/net/ipv4/ip_gre.c b/net/ipv4/ip_gre.c
index 3b9cd487075af..5c58e21f724e9 100644
--- a/net/ipv4/ip_gre.c
+++ b/net/ipv4/ip_gre.c
@@ -524,7 +524,6 @@ static void erspan_fb_xmit(struct sk_buff *skb, struct net_device *dev)
 	int tunnel_hlen;
 	int version;
 	int nhoff;
-	int thoff;
 
 	tun_info = skb_tunnel_info(skb);
 	if (unlikely(!tun_info || !(tun_info->mode & IP_TUNNEL_INFO_TX) ||
@@ -558,10 +557,16 @@ static void erspan_fb_xmit(struct sk_buff *skb, struct net_device *dev)
 	    (ntohs(ip_hdr(skb)->tot_len) > skb->len - nhoff))
 		truncate = true;
 
-	thoff = skb_transport_header(skb) - skb_mac_header(skb);
-	if (skb->protocol == htons(ETH_P_IPV6) &&
-	    (ntohs(ipv6_hdr(skb)->payload_len) > skb->len - thoff))
-		truncate = true;
+	if (skb->protocol == htons(ETH_P_IPV6)) {
+		int thoff;
+
+		if (skb_transport_header_was_set(skb))
+			thoff = skb_transport_header(skb) - skb_mac_header(skb);
+		else
+			thoff = nhoff + sizeof(struct ipv6hdr);
+		if (ntohs(ipv6_hdr(skb)->payload_len) > skb->len - thoff)
+			truncate = true;
+	}
 
 	if (version == 1) {
 		erspan_build_header(skb, ntohl(tunnel_id_to_key32(key->tun_id)),
diff --git a/net/ipv6/ip6_gre.c b/net/ipv6/ip6_gre.c
index 4e37f7c299004..a9051df0625dc 100644
--- a/net/ipv6/ip6_gre.c
+++ b/net/ipv6/ip6_gre.c
@@ -939,7 +939,6 @@ static netdev_tx_t ip6erspan_tunnel_xmit(struct sk_buff *skb,
 	__be16 proto;
 	__u32 mtu;
 	int nhoff;
-	int thoff;
 
 	if (!pskb_inet_may_pull(skb))
 		goto tx_err;
@@ -960,10 +959,16 @@ static netdev_tx_t ip6erspan_tunnel_xmit(struct sk_buff *skb,
 	    (ntohs(ip_hdr(skb)->tot_len) > skb->len - nhoff))
 		truncate = true;
 
-	thoff = skb_transport_header(skb) - skb_mac_header(skb);
-	if (skb->protocol == htons(ETH_P_IPV6) &&
-	    (ntohs(ipv6_hdr(skb)->payload_len) > skb->len - thoff))
-		truncate = true;
+	if (skb->protocol == htons(ETH_P_IPV6)) {
+		int thoff;
+
+		if (skb_transport_header_was_set(skb))
+			thoff = skb_transport_header(skb) - skb_mac_header(skb);
+		else
+			thoff = nhoff + sizeof(struct ipv6hdr);
+		if (ntohs(ipv6_hdr(skb)->payload_len) > skb->len - thoff)
+			truncate = true;
+	}
 
 	if (skb_cow_head(skb, dev->needed_headroom ?: t->hlen))
 		goto tx_err;
-- 
GitLab


From 69135c572d1f84261a6de2a1268513a7e71753e2 Mon Sep 17 00:00:00 2001
From: Ziyang Xuan <william.xuanziyang@huawei.com>
Date: Mon, 20 Jun 2022 12:35:08 +0800
Subject: [PATCH 0859/1731] net/tls: fix tls_sk_proto_close executed repeatedly

After setting the sock ktls, update ctx->sk_proto to sock->sk_prot by
tls_update(), so now ctx->sk_proto->close is tls_sk_proto_close(). When
close the sock, tls_sk_proto_close() is called for sock->sk_prot->close
is tls_sk_proto_close(). But ctx->sk_proto->close() will be executed later
in tls_sk_proto_close(). Thus tls_sk_proto_close() executed repeatedly
occurred. That will trigger the following bug.

=================================================================
KASAN: null-ptr-deref in range [0x0000000000000010-0x0000000000000017]
RIP: 0010:tls_sk_proto_close+0xd8/0xaf0 net/tls/tls_main.c:306
Call Trace:
 <TASK>
 tls_sk_proto_close+0x356/0xaf0 net/tls/tls_main.c:329
 inet_release+0x12e/0x280 net/ipv4/af_inet.c:428
 __sock_release+0xcd/0x280 net/socket.c:650
 sock_close+0x18/0x20 net/socket.c:1365

Updating a proto which is same with sock->sk_prot is incorrect. Add proto
and sock->sk_prot equality check at the head of tls_update() to fix it.

Fixes: 95fa145479fb ("bpf: sockmap/tls, close can race with map free")
Reported-by: syzbot+29c3c12f3214b85ad081@syzkaller.appspotmail.com
Signed-off-by: Ziyang Xuan <william.xuanziyang@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/tls/tls_main.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/net/tls/tls_main.c b/net/tls/tls_main.c
index da176411c1b5f..46bd5f26338bf 100644
--- a/net/tls/tls_main.c
+++ b/net/tls/tls_main.c
@@ -921,6 +921,9 @@ static void tls_update(struct sock *sk, struct proto *p,
 {
 	struct tls_context *ctx;
 
+	if (sk->sk_prot == p)
+		return;
+
 	ctx = tls_get_ctx(sk);
 	if (likely(ctx)) {
 		ctx->sk_write_space = write_space;
-- 
GitLab


From 63b8ea5e4f1a87dea4d3114293fc8e96a8f193d7 Mon Sep 17 00:00:00 2001
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
Date: Mon, 20 Jun 2022 11:03:48 +0200
Subject: [PATCH 0860/1731] random: update comment from copy_to_user() ->
 copy_to_iter()

This comment wasn't updated when we moved from read() to read_iter(), so
this patch makes the trivial fix.

Fixes: 1b388e7765f2 ("random: convert to using fops->read_iter()")
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
---
 drivers/char/random.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/char/random.c b/drivers/char/random.c
index 07a022e240573..e3dd1dd3dd226 100644
--- a/drivers/char/random.c
+++ b/drivers/char/random.c
@@ -408,7 +408,7 @@ static ssize_t get_random_bytes_user(struct iov_iter *iter)
 
 	/*
 	 * Immediately overwrite the ChaCha key at index 4 with random
-	 * bytes, in case userspace causes copy_to_user() below to sleep
+	 * bytes, in case userspace causes copy_to_iter() below to sleep
 	 * forever, so that we still retain forward secrecy in that case.
 	 */
 	crng_make_state(chacha_state, (u8 *)&chacha_state[4], CHACHA_KEY_SIZE);
-- 
GitLab


From 754f04cac362417b157e30d5dc4046b5ec92060c Mon Sep 17 00:00:00 2001
From: Cristian Marussi <cristian.marussi@arm.com>
Date: Thu, 16 Jun 2022 18:03:47 +0100
Subject: [PATCH 0861/1731] firmware: arm_scmi: Relax CLOCK_DESCRIBE_RATES
 out-of-spec checks

A reply to CLOCK_DESCRIBE_RATES issued against a non rate-discrete clock
should be composed of a triplet of rates descriptors (min/max/step)
returned all in one reply message.

This is not always the case when dealing with some SCMI server deployed in
the wild: relax such constraint while maintaining memory safety by checking
carefully the returned payload size.

While at that cleanup a stale debug printout.

Link: https://lore.kernel.org/r/20220616170347.2800771-1-cristian.marussi@arm.com
Fixes: 7bc7caafe6b1 ("firmware: arm_scmi: Use common iterators in the clock protocol")
Tested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Cristian Marussi <cristian.marussi@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
 drivers/firmware/arm_scmi/clock.c     | 26 +++++++++++++++++++++++++-
 drivers/firmware/arm_scmi/driver.c    |  1 +
 drivers/firmware/arm_scmi/protocols.h |  3 +++
 3 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/firmware/arm_scmi/clock.c b/drivers/firmware/arm_scmi/clock.c
index c7a83f6e38e5a..3ed7ae0d6781e 100644
--- a/drivers/firmware/arm_scmi/clock.c
+++ b/drivers/firmware/arm_scmi/clock.c
@@ -194,6 +194,7 @@ static int rate_cmp_func(const void *_r1, const void *_r2)
 }
 
 struct scmi_clk_ipriv {
+	struct device *dev;
 	u32 clk_id;
 	struct scmi_clock_info *clk;
 };
@@ -223,6 +224,29 @@ iter_clk_describe_update_state(struct scmi_iterator_state *st,
 	st->num_returned = NUM_RETURNED(flags);
 	p->clk->rate_discrete = RATE_DISCRETE(flags);
 
+	/* Warn about out of spec replies ... */
+	if (!p->clk->rate_discrete &&
+	    (st->num_returned != 3 || st->num_remaining != 0)) {
+		dev_warn(p->dev,
+			 "Out-of-spec CLOCK_DESCRIBE_RATES reply for %s - returned:%d remaining:%d rx_len:%zd\n",
+			 p->clk->name, st->num_returned, st->num_remaining,
+			 st->rx_len);
+
+		/*
+		 * A known quirk: a triplet is returned but num_returned != 3
+		 * Check for a safe payload size and fix.
+		 */
+		if (st->num_returned != 3 && st->num_remaining == 0 &&
+		    st->rx_len == sizeof(*r) + sizeof(__le32) * 2 * 3) {
+			st->num_returned = 3;
+			st->num_remaining = 0;
+		} else {
+			dev_err(p->dev,
+				"Cannot fix out-of-spec reply !\n");
+			return -EPROTO;
+		}
+	}
+
 	return 0;
 }
 
@@ -255,7 +279,6 @@ iter_clk_describe_process_response(const struct scmi_protocol_handle *ph,
 
 		*rate = RATE_TO_U64(r->rate[st->loop_idx]);
 		p->clk->list.num_rates++;
-		//XXX dev_dbg(ph->dev, "Rate %llu Hz\n", *rate);
 	}
 
 	return ret;
@@ -275,6 +298,7 @@ scmi_clock_describe_rates_get(const struct scmi_protocol_handle *ph, u32 clk_id,
 	struct scmi_clk_ipriv cpriv = {
 		.clk_id = clk_id,
 		.clk = clk,
+		.dev = ph->dev,
 	};
 
 	iter = ph->hops->iter_response_init(ph, &ops, SCMI_MAX_NUM_RATES,
diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c
index c1922bd650ae2..8b7ac6663d57d 100644
--- a/drivers/firmware/arm_scmi/driver.c
+++ b/drivers/firmware/arm_scmi/driver.c
@@ -1223,6 +1223,7 @@ static int scmi_iterator_run(void *iter)
 		if (ret)
 			break;
 
+		st->rx_len = i->t->rx.len;
 		ret = iops->update_state(st, i->resp, i->priv);
 		if (ret)
 			break;
diff --git a/drivers/firmware/arm_scmi/protocols.h b/drivers/firmware/arm_scmi/protocols.h
index c679f3fb8718b..51c31379f9b3e 100644
--- a/drivers/firmware/arm_scmi/protocols.h
+++ b/drivers/firmware/arm_scmi/protocols.h
@@ -179,6 +179,8 @@ struct scmi_protocol_handle {
  * @max_resources: Maximum acceptable number of items, configured by the caller
  *		   depending on the underlying resources that it is querying.
  * @loop_idx: The iterator loop index in the current multi-part reply.
+ * @rx_len: Size in bytes of the currenly processed message; it can be used by
+ *	    the user of the iterator to verify a reply size.
  * @priv: Optional pointer to some additional state-related private data setup
  *	  by the caller during the iterations.
  */
@@ -188,6 +190,7 @@ struct scmi_iterator_state {
 	unsigned int num_remaining;
 	unsigned int max_resources;
 	unsigned int loop_idx;
+	size_t rx_len;
 	void *priv;
 };
 
-- 
GitLab


From a2d9b75b19dc8863f0845ffb401d33b2286d0aa1 Mon Sep 17 00:00:00 2001
From: Max Filippov <jcmvbkbc@gmail.com>
Date: Mon, 20 Jun 2022 02:45:10 -0700
Subject: [PATCH 0862/1731] xtensa: change '.bss' to '.section .bss'

For some reason (ancient assembler?) the following build error is
reported by the kisskb:

  kisskb/src/arch/xtensa/kernel/entry.S: Error: unknown pseudo-op: `.bss':
  => 2176

Change abbreviated '.bss' to the full '.section .bss, "aw"' to fix this
error.

Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
 arch/xtensa/kernel/entry.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S
index e3eae648ba2e9..ab30bcb462903 100644
--- a/arch/xtensa/kernel/entry.S
+++ b/arch/xtensa/kernel/entry.S
@@ -2173,7 +2173,7 @@ ENDPROC(ret_from_kernel_thread)
 
 #ifdef CONFIG_HIBERNATION
 
-	.bss
+	.section	.bss, "aw"
 	.align	4
 .Lsaved_regs:
 #if defined(__XTENSA_WINDOWED_ABI__)
-- 
GitLab


From 13bd259b64bb58ae130923ada42ebc19bf3f2fa2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Mon, 13 Jun 2022 23:14:39 +0300
Subject: [PATCH 0863/1731] drm/i915: Implement w/a 22010492432 for adl-s
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

adl-s needs the combo PLL DCO fraction w/a as well.
Gets us slightly more accurate clock out of the PLL.

Cc: stable@vger.kernel.org
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220613201439.23341-1-ville.syrjala@linux.intel.com
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
(cherry picked from commit d36bdd77b9e6aa7f5cb7b0f11ebbab8e5febf10b)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 22f55574a35c5..88c2f38aa870c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2396,7 +2396,7 @@ static void icl_wrpll_params_populate(struct skl_wrpll_params *params,
 }
 
 /*
- * Display WA #22010492432: ehl, tgl, adl-p
+ * Display WA #22010492432: ehl, tgl, adl-s, adl-p
  * Program half of the nominal DCO divider fraction value.
  */
 static bool
@@ -2404,7 +2404,7 @@ ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
 {
 	return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
 		 IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
-		 IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&
+		 IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) &&
 		 i915->dpll.ref_clks.nssc == 38400;
 }
 
-- 
GitLab


From 3828296ad6242c25d2679d32a377b8e07c6b08c0 Mon Sep 17 00:00:00 2001
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date: Thu, 16 Jun 2022 15:00:56 +0100
Subject: [PATCH 0864/1731] drm/i915/fdinfo: Don't show engine classes not
 present

Stop displaying engine classes with no engines - it is not a huge problem
if they are shown, since the values will correctly be all zeroes, but it
does count as misleading.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Fixes: 055634e4b62f ("drm/i915: Expose client engine utilisation via fdinfo")
Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220616140056.559074-1-tvrtko.ursulin@linux.intel.com
(cherry picked from commit 9f1b1d0b2242171b2891a0398def233801601c14)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_drm_client.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drm_client.c b/drivers/gpu/drm/i915/i915_drm_client.c
index 18d38cb59923d..b09d1d3865740 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.c
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -116,8 +116,9 @@ show_client_class(struct seq_file *m,
 		total += busy_add(ctx, class);
 	rcu_read_unlock();
 
-	seq_printf(m, "drm-engine-%s:\t%llu ns\n",
-		   uabi_class_names[class], total);
+	if (capacity)
+		seq_printf(m, "drm-engine-%s:\t%llu ns\n",
+			   uabi_class_names[class], total);
 
 	if (capacity > 1)
 		seq_printf(m, "drm-engine-capacity-%s:\t%u\n",
-- 
GitLab


From 342fc0c3b345525da21112bd0478a0dc741598ea Mon Sep 17 00:00:00 2001
From: Carlo Lobrano <c.lobrano@gmail.com>
Date: Tue, 14 Jun 2022 09:56:23 +0200
Subject: [PATCH 0865/1731] USB: serial: option: add Telit LE910Cx 0x1250
 composition

Add support for the following Telit LE910Cx composition:

0x1250: rmnet, tty, tty, tty, tty

Reviewed-by: Daniele Palmas <dnlplm@gmail.com>
Signed-off-by: Carlo Lobrano <c.lobrano@gmail.com>
Link: https://lore.kernel.org/r/20220614075623.2392607-1-c.lobrano@gmail.com
Cc: stable@vger.kernel.org
Signed-off-by: Johan Hovold <johan@kernel.org>
---
 drivers/usb/serial/option.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
index ed1e50d83ccab..222b1e3d45a6f 100644
--- a/drivers/usb/serial/option.c
+++ b/drivers/usb/serial/option.c
@@ -1279,6 +1279,7 @@ static const struct usb_device_id option_ids[] = {
 	  .driver_info = NCTRL(0) | RSVD(1) | RSVD(2) },
 	{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1231, 0xff),	/* Telit LE910Cx (RNDIS) */
 	  .driver_info = NCTRL(2) | RSVD(3) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(TELIT_VENDOR_ID, 0x1250, 0xff, 0x00, 0x00) },	/* Telit LE910Cx (rmnet) */
 	{ USB_DEVICE(TELIT_VENDOR_ID, 0x1260),
 	  .driver_info = NCTRL(0) | RSVD(1) | RSVD(2) },
 	{ USB_DEVICE(TELIT_VENDOR_ID, 0x1261),
-- 
GitLab


From 419bc8f681a0dc63588cee693b6d45e7caa6006c Mon Sep 17 00:00:00 2001
From: Jon Lin <jon.lin@rock-chips.com>
Date: Fri, 17 Jun 2022 20:42:51 +0800
Subject: [PATCH 0866/1731] spi: rockchip: Unmask IRQ at the final to avoid
 preemption

Avoid pio_write process is preempted, resulting in abnormal state.

Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Jon <jon.lin@rock-chips.com>
Link: https://lore.kernel.org/r/20220617124251.5051-1-jon.lin@rock-chips.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 drivers/spi/spi-rockchip.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index a08215eb9e148..79242dc5272de 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -381,15 +381,18 @@ static int rockchip_spi_prepare_irq(struct rockchip_spi *rs,
 	rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
 	rs->rx_left = xfer->len / rs->n_bytes;
 
-	if (rs->cs_inactive)
-		writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
-	else
-		writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
+	writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
+
 	spi_enable_chip(rs, true);
 
 	if (rs->tx_left)
 		rockchip_spi_pio_writer(rs);
 
+	if (rs->cs_inactive)
+		writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
+	else
+		writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
+
 	/* 1 means the transfer is in progress */
 	return 1;
 }
-- 
GitLab


From 5faa0bc69102f3a4c605581564c367be5eb94dfa Mon Sep 17 00:00:00 2001
From: Takashi Iwai <tiwai@suse.de>
Date: Mon, 20 Jun 2022 12:40:07 +0200
Subject: [PATCH 0867/1731] ALSA: hda/conexant: Fix missing beep setup

Currently the Conexant codec driver sets up the beep NID after calling
snd_hda_gen_parse_auto_config().  It turned out that this results in
the insufficient setup for the beep control, as the generic parser
handles the fake path in snd_hda_gen_parse_auto_config() only if the
beep_nid is set up beforehand.

For dealing with the beep widget properly, call cx_auto_parse_beep()
before snd_hda_gen_parse_auto_config() call.

Fixes: 51e19ca5f755 ("ALSA: hda/conexant - Clean up beep code")
Cc: <stable@vger.kernel.org>
Link: https://bugzilla.kernel.org/show_bug.cgi?id=216152
Link: https://lore.kernel.org/r/20220620104008.1994-1-tiwai@suse.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/pci/hda/patch_conexant.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/pci/hda/patch_conexant.c b/sound/pci/hda/patch_conexant.c
index 1248d1a51cf01..3e541a4c04233 100644
--- a/sound/pci/hda/patch_conexant.c
+++ b/sound/pci/hda/patch_conexant.c
@@ -1079,11 +1079,11 @@ static int patch_conexant_auto(struct hda_codec *codec)
 	if (err < 0)
 		goto error;
 
-	err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg);
+	err = cx_auto_parse_beep(codec);
 	if (err < 0)
 		goto error;
 
-	err = cx_auto_parse_beep(codec);
+	err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg);
 	if (err < 0)
 		goto error;
 
-- 
GitLab


From c7807b27d510e5aa53c8a120cfc02c33c24ebb5f Mon Sep 17 00:00:00 2001
From: Takashi Iwai <tiwai@suse.de>
Date: Mon, 20 Jun 2022 12:40:08 +0200
Subject: [PATCH 0868/1731] ALSA: hda/via: Fix missing beep setup

Like the previous fix for Conexant codec, the beep_nid has to be set
up before calling snd_hda_gen_parse_auto_config(); otherwise it'd miss
the path setup.

Fix the call order for addressing the missing beep setup.

Fixes: 0e8f9862493a ("ALSA: hda/via - Simplify control management")
Cc: <stable@vger.kernel.org>
Link: https://bugzilla.kernel.org/show_bug.cgi?id=216152
Link: https://lore.kernel.org/r/20220620104008.1994-2-tiwai@suse.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/pci/hda/patch_via.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/pci/hda/patch_via.c b/sound/pci/hda/patch_via.c
index a05304f340df5..aea7fae2ca4b2 100644
--- a/sound/pci/hda/patch_via.c
+++ b/sound/pci/hda/patch_via.c
@@ -518,11 +518,11 @@ static int via_parse_auto_config(struct hda_codec *codec)
 	if (err < 0)
 		return err;
 
-	err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg);
+	err = auto_parse_beep(codec);
 	if (err < 0)
 		return err;
 
-	err = auto_parse_beep(codec);
+	err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg);
 	if (err < 0)
 		return err;
 
-- 
GitLab


From fc378794a2f7a19cf26010dc33b89ba608d4c70f Mon Sep 17 00:00:00 2001
From: Xiang wangx <wangxiang@cdjrlc.com>
Date: Sun, 5 Jun 2022 16:59:13 +0800
Subject: [PATCH 0869/1731] video: fbdev: skeletonfb: Fix syntax errors in
 comments

Delete the redundant word 'its'.

Signed-off-by: Xiang wangx <wangxiang@cdjrlc.com>
Signed-off-by: Helge Deller <deller@gmx.de>
---
 drivers/video/fbdev/skeletonfb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/fbdev/skeletonfb.c b/drivers/video/fbdev/skeletonfb.c
index bcacfb6934fa9..3d4d78362edea 100644
--- a/drivers/video/fbdev/skeletonfb.c
+++ b/drivers/video/fbdev/skeletonfb.c
@@ -96,7 +96,7 @@ static const struct fb_fix_screeninfo xxxfb_fix = {
 
     /*
      * 	Modern graphical hardware not only supports pipelines but some 
-     *  also support multiple monitors where each display can have its  
+     *  also support multiple monitors where each display can have
      *  its own unique data. In this case each display could be  
      *  represented by a separate framebuffer device thus a separate 
      *  struct fb_info. Now the struct xxx_par represents the graphics
-- 
GitLab


From 25c9a15fb7bbfafb94dd3b4e3165c18b8e1bd039 Mon Sep 17 00:00:00 2001
From: Petr Cvek <petrcvekcz@gmail.com>
Date: Fri, 17 Jun 2022 15:38:04 +0200
Subject: [PATCH 0870/1731] video: fbdev: intelfb: Use aperture size from
 pci_resource_len

Aperture size for i9x5 variants is determined from PCI base address.

	if (pci_resource_start(pdev, 2) & 0x08000000)
		*aperture_size = MB(128);
	...

This condition is incorrect as 128 MiB address can have the address
set as 0x?8000000 or 0x?0000000. Also the code can be simplified to just
use pci_resource_len().

The true settings of the aperture size is in the MSAC register, which
could be used instead. However the value is used only as an info message,
so it doesn't matter.

Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Signed-off-by: Helge Deller <deller@gmx.de>
---
 drivers/video/fbdev/intelfb/intelfbhw.c | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/video/fbdev/intelfb/intelfbhw.c b/drivers/video/fbdev/intelfb/intelfbhw.c
index 57aff7450bce7..2086e06532ee5 100644
--- a/drivers/video/fbdev/intelfb/intelfbhw.c
+++ b/drivers/video/fbdev/intelfb/intelfbhw.c
@@ -201,13 +201,11 @@ int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
 	case PCI_DEVICE_ID_INTEL_945GME:
 	case PCI_DEVICE_ID_INTEL_965G:
 	case PCI_DEVICE_ID_INTEL_965GM:
-		/* 915, 945 and 965 chipsets support a 256MB aperture.
-		   Aperture size is determined by inspected the
-		   base address of the aperture. */
-		if (pci_resource_start(pdev, 2) & 0x08000000)
-			*aperture_size = MB(128);
-		else
-			*aperture_size = MB(256);
+		/*
+		 * 915, 945 and 965 chipsets support 64MB, 128MB or 256MB
+		 * aperture. Determine size from PCI resource length.
+		 */
+		*aperture_size = pci_resource_len(pdev, 2);
 		break;
 	default:
 		if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
-- 
GitLab


From d36a869e0d0e56439365ed6d836480c480470e88 Mon Sep 17 00:00:00 2001
From: Petr Cvek <petrcvekcz@gmail.com>
Date: Fri, 17 Jun 2022 15:38:13 +0200
Subject: [PATCH 0871/1731] video: fbdev: intelfb: Initialize value of stolen
 size

Variable stolen_size can be left uninitialized in a code path with
INTEL_855_GMCH_GMS_DISABLED. Fix this by initializing the variable to 0.

Also fix indentation of function arguments.

Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Signed-off-by: Helge Deller <deller@gmx.de>
---
 drivers/video/fbdev/intelfb/intelfbdrv.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/video/fbdev/intelfb/intelfbdrv.c b/drivers/video/fbdev/intelfb/intelfbdrv.c
index a9579964eaba8..5647fca8c49a2 100644
--- a/drivers/video/fbdev/intelfb/intelfbdrv.c
+++ b/drivers/video/fbdev/intelfb/intelfbdrv.c
@@ -472,7 +472,7 @@ static int intelfb_pci_register(struct pci_dev *pdev,
 	struct fb_info *info;
 	struct intelfb_info *dinfo;
 	int i, err, dvo;
-	int aperture_size, stolen_size;
+	int aperture_size, stolen_size = 0;
 	struct agp_kern_info gtt_info;
 	int agp_memtype;
 	const char *s;
@@ -571,7 +571,7 @@ static int intelfb_pci_register(struct pci_dev *pdev,
 		return -ENODEV;
 	}
 
-	if (intelfbhw_get_memory(pdev, &aperture_size,&stolen_size)) {
+	if (intelfbhw_get_memory(pdev, &aperture_size, &stolen_size)) {
 		cleanup(dinfo);
 		return -ENODEV;
 	}
-- 
GitLab


From e146a096217e335f4e297a4fbba7ce6c722a1115 Mon Sep 17 00:00:00 2001
From: Bjorn Helgaas <bhelgaas@google.com>
Date: Tue, 7 Jun 2022 18:11:11 -0500
Subject: [PATCH 0872/1731] video: fbdev: cirrusfb: Remove useless reference to
 PCI power management

PCI-specific power management (pci_driver.suspend and pci_driver.resume) is
deprecated.  The cirrusfb driver has never implemented power management at
all, but if it ever does, it should use the generic power management
framework, not the PCI-specific hooks.

Remove the commented-out references to the PCI-specific power management
hooks.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Helge Deller <deller@gmx.de>
---
 drivers/video/fbdev/cirrusfb.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/video/fbdev/cirrusfb.c b/drivers/video/fbdev/cirrusfb.c
index 3d47c347b8970..51e072c03e1c6 100644
--- a/drivers/video/fbdev/cirrusfb.c
+++ b/drivers/video/fbdev/cirrusfb.c
@@ -2184,12 +2184,6 @@ static struct pci_driver cirrusfb_pci_driver = {
 	.id_table	= cirrusfb_pci_table,
 	.probe		= cirrusfb_pci_register,
 	.remove		= cirrusfb_pci_unregister,
-#ifdef CONFIG_PM
-#if 0
-	.suspend	= cirrusfb_pci_suspend,
-	.resume		= cirrusfb_pci_resume,
-#endif
-#endif
 };
 #endif /* CONFIG_PCI */
 
-- 
GitLab


From 267173cbf4a6b37599e644098c756e7e4b771fe9 Mon Sep 17 00:00:00 2001
From: Bjorn Helgaas <bhelgaas@google.com>
Date: Tue, 7 Jun 2022 18:11:12 -0500
Subject: [PATCH 0873/1731] video: fbdev: skeletonfb: Convert to generic power
 management

PCI-specific power management (pci_driver.suspend and pci_driver.resume) is
deprecated.  If drivers implement power management, they should use the
generic power management framework, not the PCI-specific hooks.

Convert the sample code to use the generic power management framework.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Helge Deller <deller@gmx.de>
---
 drivers/video/fbdev/skeletonfb.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/video/fbdev/skeletonfb.c b/drivers/video/fbdev/skeletonfb.c
index 3d4d78362edea..d119b1d08007f 100644
--- a/drivers/video/fbdev/skeletonfb.c
+++ b/drivers/video/fbdev/skeletonfb.c
@@ -838,9 +838,9 @@ static void xxxfb_remove(struct pci_dev *dev)
  *
  *      See Documentation/driver-api/pm/devices.rst for more information
  */
-static int xxxfb_suspend(struct pci_dev *dev, pm_message_t msg)
+static int xxxfb_suspend(struct device *dev)
 {
-	struct fb_info *info = pci_get_drvdata(dev);
+	struct fb_info *info = dev_get_drvdata(dev);
 	struct xxxfb_par *par = info->par;
 
 	/* suspend here */
@@ -853,9 +853,9 @@ static int xxxfb_suspend(struct pci_dev *dev, pm_message_t msg)
  *
  *      See Documentation/driver-api/pm/devices.rst for more information
  */
-static int xxxfb_resume(struct pci_dev *dev)
+static int xxxfb_resume(struct device *dev)
 {
-	struct fb_info *info = pci_get_drvdata(dev);
+	struct fb_info *info = dev_get_drvdata(dev);
 	struct xxxfb_par *par = info->par;
 
 	/* resume here */
@@ -873,14 +873,15 @@ static const struct pci_device_id xxxfb_id_table[] = {
 	{ 0, }
 };
 
+static SIMPLE_DEV_PM_OPS(xxxfb_pm_ops, xxxfb_suspend, xxxfb_resume);
+
 /* For PCI drivers */
 static struct pci_driver xxxfb_driver = {
 	.name =		"xxxfb",
 	.id_table =	xxxfb_id_table,
 	.probe =	xxxfb_probe,
 	.remove =	xxxfb_remove,
-	.suspend =      xxxfb_suspend, /* optional but recommended */
-	.resume =       xxxfb_resume,  /* optional but recommended */
+	.driver.pm =	xxxfb_pm_ops, /* optional but recommended */
 };
 
 MODULE_DEVICE_TABLE(pci, xxxfb_id_table);
-- 
GitLab


From 1bacd264d3c3a05de4afdd1712c9dd6ccebb9490 Mon Sep 17 00:00:00 2001
From: Jens Axboe <axboe@kernel.dk>
Date: Mon, 20 Jun 2022 06:39:27 -0600
Subject: [PATCH 0874/1731] io_uring: mark reissue requests with
 REQ_F_PARTIAL_IO

If we mark for reissue, we assume that the buffer will remain stable.
Hence if are using a provided buffer, we need to ensure that we stick
with it for the duration of that request.

This only affects block devices that use provided buffers, as those are
the only ones that get marked with REQ_F_REISSUE.

Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index d3ee4fc532faf..87c65a358678f 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -3437,7 +3437,7 @@ static bool __io_complete_rw_common(struct io_kiocb *req, long res)
 	if (unlikely(res != req->cqe.res)) {
 		if ((res == -EAGAIN || res == -EOPNOTSUPP) &&
 		    io_rw_should_reissue(req)) {
-			req->flags |= REQ_F_REISSUE;
+			req->flags |= REQ_F_REISSUE | REQ_F_PARTIAL_IO;
 			return true;
 		}
 		req_set_fail(req);
@@ -3487,7 +3487,7 @@ static void io_complete_rw_iopoll(struct kiocb *kiocb, long res)
 		kiocb_end_write(req);
 	if (unlikely(res != req->cqe.res)) {
 		if (res == -EAGAIN && io_rw_should_reissue(req)) {
-			req->flags |= REQ_F_REISSUE;
+			req->flags |= REQ_F_REISSUE | REQ_F_PARTIAL_IO;
 			return;
 		}
 		req->cqe.res = res;
-- 
GitLab


From 05b252cccb2e5c3f56119d25de684b4f810ba40a Mon Sep 17 00:00:00 2001
From: Gerd Hoffmann <kraxel@redhat.com>
Date: Mon, 20 Jun 2022 09:15:47 +0200
Subject: [PATCH 0875/1731] udmabuf: add back sanity check

Check vm_fault->pgoff before using it.  When we removed the warning, we
also removed the check.

Fixes: 7b26e4e2119d ("udmabuf: drop WARN_ON() check.")
Reported-by: zdi-disclosures@trendmicro.com
Suggested-by: Linus Torvalds <torvalds@linuxfoundation.org>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
---
 drivers/dma-buf/udmabuf.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/dma-buf/udmabuf.c b/drivers/dma-buf/udmabuf.c
index e7330684d3b82..9631f2fd2faf7 100644
--- a/drivers/dma-buf/udmabuf.c
+++ b/drivers/dma-buf/udmabuf.c
@@ -32,8 +32,11 @@ static vm_fault_t udmabuf_vm_fault(struct vm_fault *vmf)
 {
 	struct vm_area_struct *vma = vmf->vma;
 	struct udmabuf *ubuf = vma->vm_private_data;
+	pgoff_t pgoff = vmf->pgoff;
 
-	vmf->page = ubuf->pages[vmf->pgoff];
+	if (pgoff >= ubuf->pagecount)
+		return VM_FAULT_SIGBUS;
+	vmf->page = ubuf->pages[pgoff];
 	get_page(vmf->page);
 	return 0;
 }
-- 
GitLab


From ea50e2a1540fd94e6439a961daae595f65e574fb Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas <javierm@redhat.com>
Date: Thu, 16 Jun 2022 09:34:33 +0200
Subject: [PATCH 0876/1731] regmap: Re-introduce bulk read support check in
 regmap_bulk_read()

Support for drivers to define bulk read/write callbacks in regmap_config
was introduced by the commit d77e74561368 ("regmap: Add bulk read/write
callbacks into regmap_config"), but this commit wrongly dropped a check
in regmap_bulk_read() to determine whether bulk reads can be done or not.

Before that commit, it was checked if map->bus was set. Now has to check
if a map->read callback has been set.

Fixes: d77e74561368 ("regmap: Add bulk read/write callbacks into regmap_config")
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20220616073435.1988219-2-javierm@redhat.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 drivers/base/regmap/regmap.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c
index 2221d98638317..e5bb70374ffc4 100644
--- a/drivers/base/regmap/regmap.c
+++ b/drivers/base/regmap/regmap.c
@@ -3017,7 +3017,7 @@ int regmap_bulk_read(struct regmap *map, unsigned int reg, void *val,
 	if (val_count == 0)
 		return -EINVAL;
 
-	if (map->format.parse_inplace && (vol || map->cache_type == REGCACHE_NONE)) {
+	if (map->read && map->format.parse_inplace && (vol || map->cache_type == REGCACHE_NONE)) {
 		ret = regmap_raw_read(map, reg, val, val_bytes * val_count);
 		if (ret != 0)
 			return ret;
-- 
GitLab


From c42e99a3f93b4ca15720fdfd7aa8f6141dcc2a58 Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas <javierm@redhat.com>
Date: Thu, 16 Jun 2022 09:34:34 +0200
Subject: [PATCH 0877/1731] regmap: Make regmap_noinc_read() return -ENOTSUPP
 if map->read isn't set

Before adding support to define bulk read/write callbacks in regmap_config
by the commit d77e74561368 ("regmap: Add bulk read/write callbacks into
regmap_config"), the regmap_noinc_read() function returned an errno early
a map->bus->read callback wasn't set.

But that commit dropped the check and now a call to _regmap_raw_read() is
attempted even when bulk read operations are not supported. That function
checks for map->read anyways but there's no point to continue if the read
can't succeed.

Also is a fragile assumption to make so is better to make it fail earlier.

Fixes: d77e74561368 ("regmap: Add bulk read/write callbacks into regmap_config")
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20220616073435.1988219-3-javierm@redhat.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 drivers/base/regmap/regmap.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c
index e5bb70374ffc4..f37f80a521150 100644
--- a/drivers/base/regmap/regmap.c
+++ b/drivers/base/regmap/regmap.c
@@ -2904,6 +2904,9 @@ int regmap_noinc_read(struct regmap *map, unsigned int reg,
 	size_t read_len;
 	int ret;
 
+	if (!map->read)
+		return -ENOTSUPP;
+
 	if (val_len % map->format.val_bytes)
 		return -EINVAL;
 	if (!IS_ALIGNED(reg, map->reg_stride))
-- 
GitLab


From 2a166929bc0a3ae754365dabc455039fd1be82ca Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas <javierm@redhat.com>
Date: Thu, 16 Jun 2022 09:34:35 +0200
Subject: [PATCH 0878/1731] regmap: Wire up regmap_config provided bulk write
 in missed functions

There are some functions that were missed by commit d77e74561368 ("regmap:
Add bulk read/write callbacks into regmap_config") when support to define
bulk read/write callbacks in regmap_config was introduced.

The regmap_bulk_write() and regmap_noinc_write() functions weren't changed
to use the added map->write instead of the map->bus->write handler.

Also, the regmap_can_raw_write() was not modified to take map->write into
account. So will only return true if a bus with a .write callback is set.

Fixes: d77e74561368 ("regmap: Add bulk read/write callbacks into regmap_config")
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20220616073435.1988219-4-javierm@redhat.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 drivers/base/regmap/regmap.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c
index f37f80a521150..c3517ccc31591 100644
--- a/drivers/base/regmap/regmap.c
+++ b/drivers/base/regmap/regmap.c
@@ -1880,8 +1880,7 @@ static int _regmap_raw_write_impl(struct regmap *map, unsigned int reg,
  */
 bool regmap_can_raw_write(struct regmap *map)
 {
-	return map->bus && map->bus->write && map->format.format_val &&
-		map->format.format_reg;
+	return map->write && map->format.format_val && map->format.format_reg;
 }
 EXPORT_SYMBOL_GPL(regmap_can_raw_write);
 
@@ -2155,10 +2154,9 @@ int regmap_noinc_write(struct regmap *map, unsigned int reg,
 	size_t write_len;
 	int ret;
 
-	if (!map->bus)
-		return -EINVAL;
-	if (!map->bus->write)
+	if (!map->write)
 		return -ENOTSUPP;
+
 	if (val_len % map->format.val_bytes)
 		return -EINVAL;
 	if (!IS_ALIGNED(reg, map->reg_stride))
@@ -2278,7 +2276,7 @@ int regmap_bulk_write(struct regmap *map, unsigned int reg, const void *val,
 	 * Some devices don't support bulk write, for them we have a series of
 	 * single write operations.
 	 */
-	if (!map->bus || !map->format.parse_inplace) {
+	if (!map->write || !map->format.parse_inplace) {
 		map->lock(map->lock_arg);
 		for (i = 0; i < val_count; i++) {
 			unsigned int ival;
-- 
GitLab


From d5929835080a60f9119d024fa42f315913942f76 Mon Sep 17 00:00:00 2001
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
Date: Mon, 13 Jun 2022 12:22:41 +0200
Subject: [PATCH 0879/1731] drm/i915/display: Re-add check for low voltage sku
 for max dp source rate

This reverts commit 73867c8709b5 ("drm/i915/display: Remove check for
low voltage sku for max dp source rate"), which, on an i7-11850H iGPU
with a Thinkpad X1 Extreme Gen 4, attached to a LG LP160UQ1-SPB1
embedded panel, causes wild flickering glitching technicolor
pyrotechnics on resumption from suspend. The display shows strobing
colors in an utter disaster explosion of pantone, as though bombs were
dropped on the leprechauns at the base of the rainbow.

Rebooting the machine fixes the issue, presumably because the display is
initialized by firmware rather than by i915. Otherwise, the GPU appears
to work fine.

Bisection traced it back to this commit, which makes sense given the
issues.

Note: This re-opens, and puts back to the drawing board,
https://gitlab.freedesktop.org/drm/intel/-/issues/5272 which was fixed
by the regressing commit.

Fixes: 73867c8709b5 ("drm/i915/display: Remove check for low voltage sku for max dp source rate")
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6205
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Jani Saarinen <jani.saarinen@intel.com>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220613102241.9236-1-Jason@zx2c4.com
---
 drivers/gpu/drm/i915/display/intel_dp.c | 32 ++++++++++++++++++++++---
 1 file changed, 29 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 368bd4cdf2eeb..94ffbd7d807a4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -387,13 +387,23 @@ static int dg2_max_source_rate(struct intel_dp *intel_dp)
 	return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
 }
 
+static bool is_low_voltage_sku(struct drm_i915_private *i915, enum phy phy)
+{
+	u32 voltage;
+
+	voltage = intel_de_read(i915, ICL_PORT_COMP_DW3(phy)) & VOLTAGE_INFO_MASK;
+
+	return voltage == VOLTAGE_INFO_0_85V;
+}
+
 static int icl_max_source_rate(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 
-	if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
+	if (intel_phy_is_combo(dev_priv, phy) &&
+	    (is_low_voltage_sku(dev_priv, phy) || !intel_dp_is_edp(intel_dp)))
 		return 540000;
 
 	return 810000;
@@ -401,7 +411,23 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
 
 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 {
-	if (intel_dp_is_edp(intel_dp))
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
+
+	if (intel_dp_is_edp(intel_dp) || is_low_voltage_sku(dev_priv, phy))
+		return 540000;
+
+	return 810000;
+}
+
+static int dg1_max_source_rate(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
+
+	if (intel_phy_is_combo(i915, phy) && is_low_voltage_sku(i915, phy))
 		return 540000;
 
 	return 810000;
@@ -463,7 +489,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
 			max_rate = dg2_max_source_rate(intel_dp);
 		else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 			 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
-			max_rate = 810000;
+			max_rate = dg1_max_source_rate(intel_dp);
 		else if (IS_JSL_EHL(dev_priv))
 			max_rate = ehl_max_source_rate(intel_dp);
 		else
-- 
GitLab


From 2c7676b6b1f57713f55e738f803ecaf91dfc399f Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Fri, 17 Jun 2022 12:48:16 +0300
Subject: [PATCH 0880/1731] drm/i915/display: split out hw state readout and
 sanitize
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Split out the modeset hardware state readout and sanitize, or state
setup, to a separate file.

Do some drive-by checkpatch fixes while at it.

v2: Rebase

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220617094817.3466584-1-jani.nikula@intel.com
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/intel_display.c  | 739 +-----------------
 drivers/gpu/drm/i915/display/intel_display.h  |  12 +
 .../drm/i915/display/intel_modeset_setup.c    | 736 +++++++++++++++++
 .../drm/i915/display/intel_modeset_setup.h    |  15 +
 5 files changed, 778 insertions(+), 725 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_setup.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_setup.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index ea25322c64e07..f95c69b600ad6 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -234,6 +234,7 @@ i915-y += \
 	display/intel_hotplug.o \
 	display/intel_lpe_audio.o \
 	display/intel_modeset_verify.o \
+	display/intel_modeset_setup.o \
 	display/intel_overlay.o \
 	display/intel_pch_display.o \
 	display/intel_pch_refclk.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4a3799203729e..712f7c9afc451 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -101,6 +101,7 @@
 #include "intel_hdcp.h"
 #include "intel_hotplug.h"
 #include "intel_modeset_verify.h"
+#include "intel_modeset_setup.h"
 #include "intel_overlay.h"
 #include "intel_panel.h"
 #include "intel_pch_display.h"
@@ -130,8 +131,6 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
-static void intel_modeset_setup_hw_state(struct drm_device *dev,
-					 struct drm_modeset_acquire_ctx *ctx);
 
 /**
  * intel_update_watermarks - update FIFO watermark values based on current modes
@@ -166,7 +165,7 @@ static void intel_modeset_setup_hw_state(struct drm_device *dev,
  * We don't use the sprite, so we can ignore that.  And on Crestline we have
  * to set the non-SR watermarks to 8.
  */
-static void intel_update_watermarks(struct drm_i915_private *dev_priv)
+void intel_update_watermarks(struct drm_i915_private *dev_priv)
 {
 	if (dev_priv->wm_disp->update_wm)
 		dev_priv->wm_disp->update_wm(dev_priv);
@@ -733,10 +732,9 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 				 DRM_MODE_ROTATE_0);
 }
 
-static void
-intel_set_plane_visible(struct intel_crtc_state *crtc_state,
-			struct intel_plane_state *plane_state,
-			bool visible)
+void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
+			     struct intel_plane_state *plane_state,
+			     bool visible)
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 
@@ -748,7 +746,7 @@ intel_set_plane_visible(struct intel_crtc_state *crtc_state,
 		crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
 }
 
-static void fixup_plane_bitmasks(struct intel_crtc_state *crtc_state)
+void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	struct drm_plane *plane;
@@ -783,7 +781,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 		    crtc->base.base.id, crtc->base.name);
 
 	intel_set_plane_visible(crtc_state, plane_state, false);
-	fixup_plane_bitmasks(crtc_state);
+	intel_plane_fixup_bitmasks(crtc_state);
 	crtc_state->data_rate[plane->id] = 0;
 	crtc_state->data_rate_y[plane->id] = 0;
 	crtc_state->rel_data_rate[plane->id] = 0;
@@ -2209,9 +2207,8 @@ static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
 		set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
 }
 
-static void
-modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
-			       struct intel_power_domain_mask *old_domains)
+void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
+					  struct intel_power_domain_mask *old_domains)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2235,8 +2232,8 @@ modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
 					       domain);
 }
 
-static void modeset_put_crtc_power_domains(struct intel_crtc *crtc,
-					   struct intel_power_domain_mask *domains)
+void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
+					  struct intel_power_domain_mask *domains)
 {
 	intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
 					    &crtc->enabled_power_domains,
@@ -2416,89 +2413,6 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
 		i830_enable_pipe(dev_priv, pipe);
 }
 
-static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
-					struct drm_modeset_acquire_ctx *ctx)
-{
-	struct intel_encoder *encoder;
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	struct intel_bw_state *bw_state =
-		to_intel_bw_state(dev_priv->bw_obj.state);
-	struct intel_cdclk_state *cdclk_state =
-		to_intel_cdclk_state(dev_priv->cdclk.obj.state);
-	struct intel_dbuf_state *dbuf_state =
-		to_intel_dbuf_state(dev_priv->dbuf.obj.state);
-	struct intel_crtc_state *crtc_state =
-		to_intel_crtc_state(crtc->base.state);
-	struct intel_plane *plane;
-	struct drm_atomic_state *state;
-	struct intel_crtc_state *temp_crtc_state;
-	enum pipe pipe = crtc->pipe;
-	int ret;
-
-	if (!crtc_state->hw.active)
-		return;
-
-	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
-		const struct intel_plane_state *plane_state =
-			to_intel_plane_state(plane->base.state);
-
-		if (plane_state->uapi.visible)
-			intel_plane_disable_noatomic(crtc, plane);
-	}
-
-	state = drm_atomic_state_alloc(&dev_priv->drm);
-	if (!state) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "failed to disable [CRTC:%d:%s], out of memory",
-			    crtc->base.base.id, crtc->base.name);
-		return;
-	}
-
-	state->acquire_ctx = ctx;
-
-	/* Everything's already locked, -EDEADLK can't happen. */
-	temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
-	ret = drm_atomic_add_affected_connectors(state, &crtc->base);
-
-	drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
-
-	dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc);
-
-	drm_atomic_state_put(state);
-
-	drm_dbg_kms(&dev_priv->drm,
-		    "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
-		    crtc->base.base.id, crtc->base.name);
-
-	crtc->active = false;
-	crtc->base.enabled = false;
-
-	drm_WARN_ON(&dev_priv->drm,
-		    drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
-	crtc_state->uapi.active = false;
-	crtc_state->uapi.connector_mask = 0;
-	crtc_state->uapi.encoder_mask = 0;
-	intel_crtc_free_hw_state(crtc_state);
-	memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
-
-	for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
-		encoder->base.crtc = NULL;
-
-	intel_fbc_disable(crtc);
-	intel_update_watermarks(dev_priv);
-	intel_disable_shared_dpll(crtc_state);
-
-	intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains);
-
-	cdclk_state->min_cdclk[pipe] = 0;
-	cdclk_state->min_voltage_level[pipe] = 0;
-	cdclk_state->active_pipes &= ~BIT(pipe);
-
-	dbuf_state->active_pipes &= ~BIT(pipe);
-
-	bw_state->data_rate[pipe] = 0;
-	bw_state->num_active_planes[pipe] = 0;
-}
 
 /*
  * turn all crtc's off, but do not adjust state
@@ -4948,39 +4862,6 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 	return 0;
 }
 
-static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
-{
-	struct intel_connector *connector;
-	struct drm_connector_list_iter conn_iter;
-
-	drm_connector_list_iter_begin(dev, &conn_iter);
-	for_each_intel_connector_iter(connector, &conn_iter) {
-		struct drm_connector_state *conn_state = connector->base.state;
-		struct intel_encoder *encoder =
-			to_intel_encoder(connector->base.encoder);
-
-		if (conn_state->crtc)
-			drm_connector_put(&connector->base);
-
-		if (encoder) {
-			struct intel_crtc *crtc =
-				to_intel_crtc(encoder->base.crtc);
-			const struct intel_crtc_state *crtc_state =
-				to_intel_crtc_state(crtc->base.state);
-
-			conn_state->best_encoder = &encoder->base;
-			conn_state->crtc = &crtc->base;
-			conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
-
-			drm_connector_get(&connector->base);
-		} else {
-			conn_state->best_encoder = NULL;
-			conn_state->crtc = NULL;
-		}
-	}
-	drm_connector_list_iter_end(&conn_iter);
-}
-
 static int
 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
 		      struct intel_crtc_state *crtc_state)
@@ -5165,27 +5046,6 @@ intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
 	intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
 }
 
-static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
-{
-	if (intel_crtc_is_bigjoiner_slave(crtc_state))
-		return;
-
-	crtc_state->uapi.enable = crtc_state->hw.enable;
-	crtc_state->uapi.active = crtc_state->hw.active;
-	drm_WARN_ON(crtc_state->uapi.crtc->dev,
-		    drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
-
-	crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
-	crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
-
-	drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
-				  crtc_state->hw.degamma_lut);
-	drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
-				  crtc_state->hw.gamma_lut);
-	drm_property_replace_blob(&crtc_state->uapi.ctm,
-				  crtc_state->hw.ctm);
-}
-
 static void
 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state,
 				    struct intel_crtc *slave_crtc)
@@ -6115,8 +5975,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state)
 	return 0;
 }
 
-static void
-intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
+void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -7670,7 +7529,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 					    new_crtc_state, i) {
 		if (intel_crtc_needs_modeset(new_crtc_state) ||
 		    new_crtc_state->update_pipe) {
-			modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
+			intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
 		}
 	}
 
@@ -7770,7 +7629,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 		intel_post_plane_update(state, crtc);
 
-		modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
+		intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
 
 		intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
 
@@ -9060,576 +8919,6 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 	intel_de_posting_read(dev_priv, DPLL(pipe));
 }
 
-static void
-intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
-{
-	struct intel_crtc *crtc;
-
-	if (DISPLAY_VER(dev_priv) >= 4)
-		return;
-
-	for_each_intel_crtc(&dev_priv->drm, crtc) {
-		struct intel_plane *plane =
-			to_intel_plane(crtc->base.primary);
-		struct intel_crtc *plane_crtc;
-		enum pipe pipe;
-
-		if (!plane->get_hw_state(plane, &pipe))
-			continue;
-
-		if (pipe == crtc->pipe)
-			continue;
-
-		drm_dbg_kms(&dev_priv->drm,
-			    "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
-			    plane->base.base.id, plane->base.name);
-
-		plane_crtc = intel_crtc_for_pipe(dev_priv, pipe);
-		intel_plane_disable_noatomic(plane_crtc, plane);
-	}
-}
-
-static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
-{
-	struct drm_device *dev = crtc->base.dev;
-	struct intel_encoder *encoder;
-
-	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
-		return true;
-
-	return false;
-}
-
-static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
-{
-	struct drm_device *dev = encoder->base.dev;
-	struct intel_connector *connector;
-
-	for_each_connector_on_encoder(dev, &encoder->base, connector)
-		return connector;
-
-	return NULL;
-}
-
-static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-
-	if (!crtc_state->hw.active && !HAS_GMCH(i915))
-		return;
-
-	/*
-	 * We start out with underrun reporting disabled to avoid races.
-	 * For correct bookkeeping mark this on active crtcs.
-	 *
-	 * Also on gmch platforms we dont have any hardware bits to
-	 * disable the underrun reporting. Which means we need to start
-	 * out with underrun reporting disabled also on inactive pipes,
-	 * since otherwise we'll complain about the garbage we read when
-	 * e.g. coming up after runtime pm.
-	 *
-	 * No protection against concurrent access is required - at
-	 * worst a fifo underrun happens which also sets this to false.
-	 */
-	crtc->cpu_fifo_underrun_disabled = true;
-
-	/*
-	 * We track the PCH trancoder underrun reporting state
-	 * within the crtc. With crtc for pipe A housing the underrun
-	 * reporting state for PCH transcoder A, crtc for pipe B housing
-	 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
-	 * and marking underrun reporting as disabled for the non-existing
-	 * PCH transcoders B and C would prevent enabling the south
-	 * error interrupt (see cpt_can_enable_serr_int()).
-	 */
-	if (intel_has_pch_trancoder(i915, crtc->pipe))
-		crtc->pch_fifo_underrun_disabled = true;
-}
-
-static void intel_sanitize_crtc(struct intel_crtc *crtc,
-				struct drm_modeset_acquire_ctx *ctx)
-{
-	struct drm_device *dev = crtc->base.dev;
-	struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
-
-	if (crtc_state->hw.active) {
-		struct intel_plane *plane;
-
-		/* Disable everything but the primary plane */
-		for_each_intel_plane_on_crtc(dev, crtc, plane) {
-			const struct intel_plane_state *plane_state =
-				to_intel_plane_state(plane->base.state);
-
-			if (plane_state->uapi.visible &&
-			    plane->base.type != DRM_PLANE_TYPE_PRIMARY)
-				intel_plane_disable_noatomic(crtc, plane);
-		}
-
-		/* Disable any background color/etc. set by the BIOS */
-		intel_color_commit_noarm(crtc_state);
-		intel_color_commit_arm(crtc_state);
-	}
-
-	/* Adjust the state of the output pipe according to whether we
-	 * have active connectors/encoders. */
-	if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&
-	    !intel_crtc_is_bigjoiner_slave(crtc_state))
-		intel_crtc_disable_noatomic(crtc, ctx);
-}
-
-static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
-{
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
-
-	/*
-	 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
-	 * the hardware when a high res displays plugged in. DPLL P
-	 * divider is zero, and the pipe timings are bonkers. We'll
-	 * try to disable everything in that case.
-	 *
-	 * FIXME would be nice to be able to sanitize this state
-	 * without several WARNs, but for now let's take the easy
-	 * road.
-	 */
-	return IS_SANDYBRIDGE(dev_priv) &&
-		crtc_state->hw.active &&
-		crtc_state->shared_dpll &&
-		crtc_state->port_clock == 0;
-}
-
-static void intel_sanitize_encoder(struct intel_encoder *encoder)
-{
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_connector *connector;
-	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
-	struct intel_crtc_state *crtc_state = crtc ?
-		to_intel_crtc_state(crtc->base.state) : NULL;
-
-	/* We need to check both for a crtc link (meaning that the
-	 * encoder is active and trying to read from a pipe) and the
-	 * pipe itself being active. */
-	bool has_active_crtc = crtc_state &&
-		crtc_state->hw.active;
-
-	if (crtc_state && has_bogus_dpll_config(crtc_state)) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
-			    pipe_name(crtc->pipe));
-		has_active_crtc = false;
-	}
-
-	connector = intel_encoder_find_connector(encoder);
-	if (connector && !has_active_crtc) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
-			    encoder->base.base.id,
-			    encoder->base.name);
-
-		/* Connector is active, but has no active pipe. This is
-		 * fallout from our resume register restoring. Disable
-		 * the encoder manually again. */
-		if (crtc_state) {
-			struct drm_encoder *best_encoder;
-
-			drm_dbg_kms(&dev_priv->drm,
-				    "[ENCODER:%d:%s] manually disabled\n",
-				    encoder->base.base.id,
-				    encoder->base.name);
-
-			/* avoid oopsing in case the hooks consult best_encoder */
-			best_encoder = connector->base.state->best_encoder;
-			connector->base.state->best_encoder = &encoder->base;
-
-			/* FIXME NULL atomic state passed! */
-			if (encoder->disable)
-				encoder->disable(NULL, encoder, crtc_state,
-						 connector->base.state);
-			if (encoder->post_disable)
-				encoder->post_disable(NULL, encoder, crtc_state,
-						      connector->base.state);
-
-			connector->base.state->best_encoder = best_encoder;
-		}
-		encoder->base.crtc = NULL;
-
-		/* Inconsistent output/port/pipe state happens presumably due to
-		 * a bug in one of the get_hw_state functions. Or someplace else
-		 * in our code, like the register restore mess on resume. Clamp
-		 * things to off as a safer default. */
-
-		connector->base.dpms = DRM_MODE_DPMS_OFF;
-		connector->base.encoder = NULL;
-	}
-
-	/* notify opregion of the sanitized encoder state */
-	intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
-
-	if (HAS_DDI(dev_priv))
-		intel_ddi_sanitize_encoder_pll_mapping(encoder);
-}
-
-/* FIXME read out full plane state for all planes */
-static void readout_plane_state(struct drm_i915_private *dev_priv)
-{
-	struct intel_plane *plane;
-	struct intel_crtc *crtc;
-
-	for_each_intel_plane(&dev_priv->drm, plane) {
-		struct intel_plane_state *plane_state =
-			to_intel_plane_state(plane->base.state);
-		struct intel_crtc_state *crtc_state;
-		enum pipe pipe = PIPE_A;
-		bool visible;
-
-		visible = plane->get_hw_state(plane, &pipe);
-
-		crtc = intel_crtc_for_pipe(dev_priv, pipe);
-		crtc_state = to_intel_crtc_state(crtc->base.state);
-
-		intel_set_plane_visible(crtc_state, plane_state, visible);
-
-		drm_dbg_kms(&dev_priv->drm,
-			    "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
-			    plane->base.base.id, plane->base.name,
-			    str_enabled_disabled(visible), pipe_name(pipe));
-	}
-
-	for_each_intel_crtc(&dev_priv->drm, crtc) {
-		struct intel_crtc_state *crtc_state =
-			to_intel_crtc_state(crtc->base.state);
-
-		fixup_plane_bitmasks(crtc_state);
-	}
-}
-
-static void intel_modeset_readout_hw_state(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_cdclk_state *cdclk_state =
-		to_intel_cdclk_state(dev_priv->cdclk.obj.state);
-	struct intel_dbuf_state *dbuf_state =
-		to_intel_dbuf_state(dev_priv->dbuf.obj.state);
-	enum pipe pipe;
-	struct intel_crtc *crtc;
-	struct intel_encoder *encoder;
-	struct intel_connector *connector;
-	struct drm_connector_list_iter conn_iter;
-	u8 active_pipes = 0;
-
-	for_each_intel_crtc(dev, crtc) {
-		struct intel_crtc_state *crtc_state =
-			to_intel_crtc_state(crtc->base.state);
-
-		__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
-		intel_crtc_free_hw_state(crtc_state);
-		intel_crtc_state_reset(crtc_state, crtc);
-
-		intel_crtc_get_pipe_config(crtc_state);
-
-		crtc_state->hw.enable = crtc_state->hw.active;
-
-		crtc->base.enabled = crtc_state->hw.enable;
-		crtc->active = crtc_state->hw.active;
-
-		if (crtc_state->hw.active)
-			active_pipes |= BIT(crtc->pipe);
-
-		drm_dbg_kms(&dev_priv->drm,
-			    "[CRTC:%d:%s] hw state readout: %s\n",
-			    crtc->base.base.id, crtc->base.name,
-			    str_enabled_disabled(crtc_state->hw.active));
-	}
-
-	cdclk_state->active_pipes = dbuf_state->active_pipes = active_pipes;
-
-	readout_plane_state(dev_priv);
-
-	for_each_intel_encoder(dev, encoder) {
-		struct intel_crtc_state *crtc_state = NULL;
-
-		pipe = 0;
-
-		if (encoder->get_hw_state(encoder, &pipe)) {
-			crtc = intel_crtc_for_pipe(dev_priv, pipe);
-			crtc_state = to_intel_crtc_state(crtc->base.state);
-
-			encoder->base.crtc = &crtc->base;
-			intel_encoder_get_config(encoder, crtc_state);
-
-			/* read out to slave crtc as well for bigjoiner */
-			if (crtc_state->bigjoiner_pipes) {
-				struct intel_crtc *slave_crtc;
-
-				/* encoder should read be linked to bigjoiner master */
-				WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
-
-				for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc,
-								 intel_crtc_bigjoiner_slave_pipes(crtc_state)) {
-					struct intel_crtc_state *slave_crtc_state;
-
-					slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state);
-					intel_encoder_get_config(encoder, slave_crtc_state);
-				}
-			}
-		} else {
-			encoder->base.crtc = NULL;
-		}
-
-		if (encoder->sync_state)
-			encoder->sync_state(encoder, crtc_state);
-
-		drm_dbg_kms(&dev_priv->drm,
-			    "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
-			    encoder->base.base.id, encoder->base.name,
-			    str_enabled_disabled(encoder->base.crtc),
-			    pipe_name(pipe));
-	}
-
-	intel_dpll_readout_hw_state(dev_priv);
-
-	drm_connector_list_iter_begin(dev, &conn_iter);
-	for_each_intel_connector_iter(connector, &conn_iter) {
-		if (connector->get_hw_state(connector)) {
-			struct intel_crtc_state *crtc_state;
-			struct intel_crtc *crtc;
-
-			connector->base.dpms = DRM_MODE_DPMS_ON;
-
-			encoder = intel_attached_encoder(connector);
-			connector->base.encoder = &encoder->base;
-
-			crtc = to_intel_crtc(encoder->base.crtc);
-			crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
-
-			if (crtc_state && crtc_state->hw.active) {
-				/*
-				 * This has to be done during hardware readout
-				 * because anything calling .crtc_disable may
-				 * rely on the connector_mask being accurate.
-				 */
-				crtc_state->uapi.connector_mask |=
-					drm_connector_mask(&connector->base);
-				crtc_state->uapi.encoder_mask |=
-					drm_encoder_mask(&encoder->base);
-			}
-		} else {
-			connector->base.dpms = DRM_MODE_DPMS_OFF;
-			connector->base.encoder = NULL;
-		}
-		drm_dbg_kms(&dev_priv->drm,
-			    "[CONNECTOR:%d:%s] hw state readout: %s\n",
-			    connector->base.base.id, connector->base.name,
-			    str_enabled_disabled(connector->base.encoder));
-	}
-	drm_connector_list_iter_end(&conn_iter);
-
-	for_each_intel_crtc(dev, crtc) {
-		struct intel_bw_state *bw_state =
-			to_intel_bw_state(dev_priv->bw_obj.state);
-		struct intel_crtc_state *crtc_state =
-			to_intel_crtc_state(crtc->base.state);
-		struct intel_plane *plane;
-		int min_cdclk = 0;
-
-		if (crtc_state->hw.active) {
-			/*
-			 * The initial mode needs to be set in order to keep
-			 * the atomic core happy. It wants a valid mode if the
-			 * crtc's enabled, so we do the above call.
-			 *
-			 * But we don't set all the derived state fully, hence
-			 * set a flag to indicate that a full recalculation is
-			 * needed on the next commit.
-			 */
-			crtc_state->inherited = true;
-
-			intel_crtc_update_active_timings(crtc_state);
-
-			intel_crtc_copy_hw_to_uapi_state(crtc_state);
-		}
-
-		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
-			const struct intel_plane_state *plane_state =
-				to_intel_plane_state(plane->base.state);
-
-			/*
-			 * FIXME don't have the fb yet, so can't
-			 * use intel_plane_data_rate() :(
-			 */
-			if (plane_state->uapi.visible)
-				crtc_state->data_rate[plane->id] =
-					4 * crtc_state->pixel_rate;
-			/*
-			 * FIXME don't have the fb yet, so can't
-			 * use plane->min_cdclk() :(
-			 */
-			if (plane_state->uapi.visible && plane->min_cdclk) {
-				if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10)
-					crtc_state->min_cdclk[plane->id] =
-						DIV_ROUND_UP(crtc_state->pixel_rate, 2);
-				else
-					crtc_state->min_cdclk[plane->id] =
-						crtc_state->pixel_rate;
-			}
-			drm_dbg_kms(&dev_priv->drm,
-				    "[PLANE:%d:%s] min_cdclk %d kHz\n",
-				    plane->base.base.id, plane->base.name,
-				    crtc_state->min_cdclk[plane->id]);
-		}
-
-		if (crtc_state->hw.active) {
-			min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
-			if (drm_WARN_ON(dev, min_cdclk < 0))
-				min_cdclk = 0;
-		}
-
-		cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
-		cdclk_state->min_voltage_level[crtc->pipe] =
-			crtc_state->min_voltage_level;
-
-		intel_bw_crtc_update(bw_state, crtc_state);
-	}
-}
-
-static void
-get_encoder_power_domains(struct drm_i915_private *dev_priv)
-{
-	struct intel_encoder *encoder;
-
-	for_each_intel_encoder(&dev_priv->drm, encoder) {
-		struct intel_crtc_state *crtc_state;
-
-		if (!encoder->get_power_domains)
-			continue;
-
-		/*
-		 * MST-primary and inactive encoders don't have a crtc state
-		 * and neither of these require any power domain references.
-		 */
-		if (!encoder->base.crtc)
-			continue;
-
-		crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
-		encoder->get_power_domains(encoder, crtc_state);
-	}
-}
-
-static void intel_early_display_was(struct drm_i915_private *dev_priv)
-{
-	/*
-	 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl
-	 * Also known as Wa_14010480278.
-	 */
-	if (IS_DISPLAY_VER(dev_priv, 10, 12))
-		intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
-			       intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
-
-	if (IS_HASWELL(dev_priv)) {
-		/*
-		 * WaRsPkgCStateDisplayPMReq:hsw
-		 * System hang if this isn't done before disabling all planes!
-		 */
-		intel_de_write(dev_priv, CHICKEN_PAR1_1,
-			       intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
-	}
-
-	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) {
-		/* Display WA #1142:kbl,cfl,cml */
-		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
-			     KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
-		intel_de_rmw(dev_priv, CHICKEN_MISC_2,
-			     KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
-			     KBL_ARB_FILL_SPARE_14);
-	}
-}
-
-
-/* Scan out the current hw modeset state,
- * and sanitizes it to the current state
- */
-static void
-intel_modeset_setup_hw_state(struct drm_device *dev,
-			     struct drm_modeset_acquire_ctx *ctx)
-{
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_encoder *encoder;
-	struct intel_crtc *crtc;
-	intel_wakeref_t wakeref;
-
-	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
-
-	intel_early_display_was(dev_priv);
-	intel_modeset_readout_hw_state(dev);
-
-	/* HW state is read out, now we need to sanitize this mess. */
-	get_encoder_power_domains(dev_priv);
-
-	intel_pch_sanitize(dev_priv);
-
-	/*
-	 * intel_sanitize_plane_mapping() may need to do vblank
-	 * waits, so we need vblank interrupts restored beforehand.
-	 */
-	for_each_intel_crtc(&dev_priv->drm, crtc) {
-		struct intel_crtc_state *crtc_state =
-			to_intel_crtc_state(crtc->base.state);
-
-		intel_sanitize_fifo_underrun_reporting(crtc_state);
-
-		drm_crtc_vblank_reset(&crtc->base);
-
-		if (crtc_state->hw.active)
-			intel_crtc_vblank_on(crtc_state);
-	}
-
-	intel_fbc_sanitize(dev_priv);
-
-	intel_sanitize_plane_mapping(dev_priv);
-
-	for_each_intel_encoder(dev, encoder)
-		intel_sanitize_encoder(encoder);
-
-	for_each_intel_crtc(&dev_priv->drm, crtc) {
-		struct intel_crtc_state *crtc_state =
-			to_intel_crtc_state(crtc->base.state);
-
-		intel_sanitize_crtc(crtc, ctx);
-		intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state");
-	}
-
-	intel_modeset_update_connector_atomic_state(dev);
-
-	intel_dpll_sanitize_state(dev_priv);
-
-	if (IS_G4X(dev_priv)) {
-		g4x_wm_get_hw_state(dev_priv);
-		g4x_wm_sanitize(dev_priv);
-	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
-		vlv_wm_get_hw_state(dev_priv);
-		vlv_wm_sanitize(dev_priv);
-	} else if (DISPLAY_VER(dev_priv) >= 9) {
-		skl_wm_get_hw_state(dev_priv);
-		skl_wm_sanitize(dev_priv);
-	} else if (HAS_PCH_SPLIT(dev_priv)) {
-		ilk_wm_get_hw_state(dev_priv);
-	}
-
-	for_each_intel_crtc(dev, crtc) {
-		struct intel_crtc_state *crtc_state =
-			to_intel_crtc_state(crtc->base.state);
-		struct intel_power_domain_mask put_domains;
-
-		modeset_get_crtc_power_domains(crtc_state, &put_domains);
-		if (drm_WARN_ON(dev, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
-			modeset_put_crtc_power_domains(crtc, &put_domains);
-	}
-
-	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
-
-	intel_power_domains_sanitize_state(dev_priv);
-}
-
 void intel_display_resume(struct drm_device *dev)
 {
 	struct drm_i915_private *i915 = to_i915(dev);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 2feb8ae5d5d48..8610e17cc5934 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -56,6 +56,7 @@ struct intel_initial_plane_config;
 struct intel_load_detect_pipe;
 struct intel_plane;
 struct intel_plane_state;
+struct intel_power_domain_mask;
 struct intel_remapped_info;
 struct intel_rotation_info;
 struct pci_dev;
@@ -563,6 +564,7 @@ bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
 bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 			       const struct intel_crtc_state *pipe_config,
 			       bool fastset);
+void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state);
 
 void intel_plane_destroy(struct drm_plane *plane);
 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
@@ -659,10 +661,16 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
 			   const struct intel_crtc_state *crtc_state);
 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 				  struct intel_plane *plane);
+void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
+			     struct intel_plane_state *plane_state,
+			     bool visible);
+void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);
 
 void intel_display_driver_register(struct drm_i915_private *i915);
 void intel_display_driver_unregister(struct drm_i915_private *i915);
 
+void intel_update_watermarks(struct drm_i915_private *i915);
+
 /* modesetting */
 bool intel_modeset_probe_defer(struct pci_dev *pdev);
 void intel_modeset_init_hw(struct drm_i915_private *i915);
@@ -674,6 +682,10 @@ void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915);
 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915);
 void intel_display_resume(struct drm_device *dev);
 int intel_modeset_all_pipes(struct intel_atomic_state *state);
+void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
+					  struct intel_power_domain_mask *old_domains);
+void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
+					  struct intel_power_domain_mask *domains);
 
 /* modesetting asserts */
 void assert_transcoder(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
new file mode 100644
index 0000000000000..c340f33932462
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -0,0 +1,736 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ *
+ * Read out the current hardware modeset state, and sanitize it to the current
+ * state.
+ */
+
+#include <drm/drm_atomic_uapi.h>
+#include <drm/drm_atomic_state_helper.h>
+
+#include "i915_drv.h"
+#include "intel_atomic.h"
+#include "intel_bw.h"
+#include "intel_color.h"
+#include "intel_crtc.h"
+#include "intel_crtc_state_dump.h"
+#include "intel_ddi.h"
+#include "intel_de.h"
+#include "intel_display.h"
+#include "intel_display_power.h"
+#include "intel_display_types.h"
+#include "intel_modeset_setup.h"
+#include "intel_pch_display.h"
+#include "intel_pm.h"
+
+static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
+					struct drm_modeset_acquire_ctx *ctx)
+{
+	struct intel_encoder *encoder;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_bw_state *bw_state =
+		to_intel_bw_state(dev_priv->bw_obj.state);
+	struct intel_cdclk_state *cdclk_state =
+		to_intel_cdclk_state(dev_priv->cdclk.obj.state);
+	struct intel_dbuf_state *dbuf_state =
+		to_intel_dbuf_state(dev_priv->dbuf.obj.state);
+	struct intel_crtc_state *crtc_state =
+		to_intel_crtc_state(crtc->base.state);
+	struct intel_plane *plane;
+	struct drm_atomic_state *state;
+	struct intel_crtc_state *temp_crtc_state;
+	enum pipe pipe = crtc->pipe;
+	int ret;
+
+	if (!crtc_state->hw.active)
+		return;
+
+	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+		const struct intel_plane_state *plane_state =
+			to_intel_plane_state(plane->base.state);
+
+		if (plane_state->uapi.visible)
+			intel_plane_disable_noatomic(crtc, plane);
+	}
+
+	state = drm_atomic_state_alloc(&dev_priv->drm);
+	if (!state) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "failed to disable [CRTC:%d:%s], out of memory",
+			    crtc->base.base.id, crtc->base.name);
+		return;
+	}
+
+	state->acquire_ctx = ctx;
+
+	/* Everything's already locked, -EDEADLK can't happen. */
+	temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
+	ret = drm_atomic_add_affected_connectors(state, &crtc->base);
+
+	drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
+
+	dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc);
+
+	drm_atomic_state_put(state);
+
+	drm_dbg_kms(&dev_priv->drm,
+		    "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
+		    crtc->base.base.id, crtc->base.name);
+
+	crtc->active = false;
+	crtc->base.enabled = false;
+
+	drm_WARN_ON(&dev_priv->drm,
+		    drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
+	crtc_state->uapi.active = false;
+	crtc_state->uapi.connector_mask = 0;
+	crtc_state->uapi.encoder_mask = 0;
+	intel_crtc_free_hw_state(crtc_state);
+	memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
+
+	for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
+		encoder->base.crtc = NULL;
+
+	intel_fbc_disable(crtc);
+	intel_update_watermarks(dev_priv);
+	intel_disable_shared_dpll(crtc_state);
+
+	intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains);
+
+	cdclk_state->min_cdclk[pipe] = 0;
+	cdclk_state->min_voltage_level[pipe] = 0;
+	cdclk_state->active_pipes &= ~BIT(pipe);
+
+	dbuf_state->active_pipes &= ~BIT(pipe);
+
+	bw_state->data_rate[pipe] = 0;
+	bw_state->num_active_planes[pipe] = 0;
+}
+
+static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
+{
+	struct intel_connector *connector;
+	struct drm_connector_list_iter conn_iter;
+
+	drm_connector_list_iter_begin(dev, &conn_iter);
+	for_each_intel_connector_iter(connector, &conn_iter) {
+		struct drm_connector_state *conn_state = connector->base.state;
+		struct intel_encoder *encoder =
+			to_intel_encoder(connector->base.encoder);
+
+		if (conn_state->crtc)
+			drm_connector_put(&connector->base);
+
+		if (encoder) {
+			struct intel_crtc *crtc =
+				to_intel_crtc(encoder->base.crtc);
+			const struct intel_crtc_state *crtc_state =
+				to_intel_crtc_state(crtc->base.state);
+
+			conn_state->best_encoder = &encoder->base;
+			conn_state->crtc = &crtc->base;
+			conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
+
+			drm_connector_get(&connector->base);
+		} else {
+			conn_state->best_encoder = NULL;
+			conn_state->crtc = NULL;
+		}
+	}
+	drm_connector_list_iter_end(&conn_iter);
+}
+
+static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
+{
+	if (intel_crtc_is_bigjoiner_slave(crtc_state))
+		return;
+
+	crtc_state->uapi.enable = crtc_state->hw.enable;
+	crtc_state->uapi.active = crtc_state->hw.active;
+	drm_WARN_ON(crtc_state->uapi.crtc->dev,
+		    drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
+
+	crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
+	crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
+
+	drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
+				  crtc_state->hw.degamma_lut);
+	drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
+				  crtc_state->hw.gamma_lut);
+	drm_property_replace_blob(&crtc_state->uapi.ctm,
+				  crtc_state->hw.ctm);
+}
+
+static void
+intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
+{
+	struct intel_crtc *crtc;
+
+	if (DISPLAY_VER(dev_priv) >= 4)
+		return;
+
+	for_each_intel_crtc(&dev_priv->drm, crtc) {
+		struct intel_plane *plane =
+			to_intel_plane(crtc->base.primary);
+		struct intel_crtc *plane_crtc;
+		enum pipe pipe;
+
+		if (!plane->get_hw_state(plane, &pipe))
+			continue;
+
+		if (pipe == crtc->pipe)
+			continue;
+
+		drm_dbg_kms(&dev_priv->drm,
+			    "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
+			    plane->base.base.id, plane->base.name);
+
+		plane_crtc = intel_crtc_for_pipe(dev_priv, pipe);
+		intel_plane_disable_noatomic(plane_crtc, plane);
+	}
+}
+
+static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
+{
+	struct drm_device *dev = crtc->base.dev;
+	struct intel_encoder *encoder;
+
+	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
+		return true;
+
+	return false;
+}
+
+static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
+{
+	struct drm_device *dev = encoder->base.dev;
+	struct intel_connector *connector;
+
+	for_each_connector_on_encoder(dev, &encoder->base, connector)
+		return connector;
+
+	return NULL;
+}
+
+static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+	if (!crtc_state->hw.active && !HAS_GMCH(i915))
+		return;
+
+	/*
+	 * We start out with underrun reporting disabled to avoid races.
+	 * For correct bookkeeping mark this on active crtcs.
+	 *
+	 * Also on gmch platforms we dont have any hardware bits to
+	 * disable the underrun reporting. Which means we need to start
+	 * out with underrun reporting disabled also on inactive pipes,
+	 * since otherwise we'll complain about the garbage we read when
+	 * e.g. coming up after runtime pm.
+	 *
+	 * No protection against concurrent access is required - at
+	 * worst a fifo underrun happens which also sets this to false.
+	 */
+	crtc->cpu_fifo_underrun_disabled = true;
+
+	/*
+	 * We track the PCH trancoder underrun reporting state
+	 * within the crtc. With crtc for pipe A housing the underrun
+	 * reporting state for PCH transcoder A, crtc for pipe B housing
+	 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
+	 * and marking underrun reporting as disabled for the non-existing
+	 * PCH transcoders B and C would prevent enabling the south
+	 * error interrupt (see cpt_can_enable_serr_int()).
+	 */
+	if (intel_has_pch_trancoder(i915, crtc->pipe))
+		crtc->pch_fifo_underrun_disabled = true;
+}
+
+static void intel_sanitize_crtc(struct intel_crtc *crtc,
+				struct drm_modeset_acquire_ctx *ctx)
+{
+	struct drm_device *dev = crtc->base.dev;
+	struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
+
+	if (crtc_state->hw.active) {
+		struct intel_plane *plane;
+
+		/* Disable everything but the primary plane */
+		for_each_intel_plane_on_crtc(dev, crtc, plane) {
+			const struct intel_plane_state *plane_state =
+				to_intel_plane_state(plane->base.state);
+
+			if (plane_state->uapi.visible &&
+			    plane->base.type != DRM_PLANE_TYPE_PRIMARY)
+				intel_plane_disable_noatomic(crtc, plane);
+		}
+
+		/* Disable any background color/etc. set by the BIOS */
+		intel_color_commit_noarm(crtc_state);
+		intel_color_commit_arm(crtc_state);
+	}
+
+	/*
+	 * Adjust the state of the output pipe according to whether we have
+	 * active connectors/encoders.
+	 */
+	if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&
+	    !intel_crtc_is_bigjoiner_slave(crtc_state))
+		intel_crtc_disable_noatomic(crtc, ctx);
+}
+
+static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+
+	/*
+	 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
+	 * the hardware when a high res displays plugged in. DPLL P
+	 * divider is zero, and the pipe timings are bonkers. We'll
+	 * try to disable everything in that case.
+	 *
+	 * FIXME would be nice to be able to sanitize this state
+	 * without several WARNs, but for now let's take the easy
+	 * road.
+	 */
+	return IS_SANDYBRIDGE(dev_priv) &&
+		crtc_state->hw.active &&
+		crtc_state->shared_dpll &&
+		crtc_state->port_clock == 0;
+}
+
+static void intel_sanitize_encoder(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_connector *connector;
+	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
+	struct intel_crtc_state *crtc_state = crtc ?
+		to_intel_crtc_state(crtc->base.state) : NULL;
+
+	/*
+	 * We need to check both for a crtc link (meaning that the encoder is
+	 * active and trying to read from a pipe) and the pipe itself being
+	 * active.
+	 */
+	bool has_active_crtc = crtc_state &&
+		crtc_state->hw.active;
+
+	if (crtc_state && has_bogus_dpll_config(crtc_state)) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
+			    pipe_name(crtc->pipe));
+		has_active_crtc = false;
+	}
+
+	connector = intel_encoder_find_connector(encoder);
+	if (connector && !has_active_crtc) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
+			    encoder->base.base.id,
+			    encoder->base.name);
+
+		/*
+		 * Connector is active, but has no active pipe. This is fallout
+		 * from our resume register restoring. Disable the encoder
+		 * manually again.
+		 */
+		if (crtc_state) {
+			struct drm_encoder *best_encoder;
+
+			drm_dbg_kms(&dev_priv->drm,
+				    "[ENCODER:%d:%s] manually disabled\n",
+				    encoder->base.base.id,
+				    encoder->base.name);
+
+			/* avoid oopsing in case the hooks consult best_encoder */
+			best_encoder = connector->base.state->best_encoder;
+			connector->base.state->best_encoder = &encoder->base;
+
+			/* FIXME NULL atomic state passed! */
+			if (encoder->disable)
+				encoder->disable(NULL, encoder, crtc_state,
+						 connector->base.state);
+			if (encoder->post_disable)
+				encoder->post_disable(NULL, encoder, crtc_state,
+						      connector->base.state);
+
+			connector->base.state->best_encoder = best_encoder;
+		}
+		encoder->base.crtc = NULL;
+
+		/*
+		 * Inconsistent output/port/pipe state happens presumably due to
+		 * a bug in one of the get_hw_state functions. Or someplace else
+		 * in our code, like the register restore mess on resume. Clamp
+		 * things to off as a safer default.
+		 */
+		connector->base.dpms = DRM_MODE_DPMS_OFF;
+		connector->base.encoder = NULL;
+	}
+
+	/* notify opregion of the sanitized encoder state */
+	intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
+
+	if (HAS_DDI(dev_priv))
+		intel_ddi_sanitize_encoder_pll_mapping(encoder);
+}
+
+/* FIXME read out full plane state for all planes */
+static void readout_plane_state(struct drm_i915_private *dev_priv)
+{
+	struct intel_plane *plane;
+	struct intel_crtc *crtc;
+
+	for_each_intel_plane(&dev_priv->drm, plane) {
+		struct intel_plane_state *plane_state =
+			to_intel_plane_state(plane->base.state);
+		struct intel_crtc_state *crtc_state;
+		enum pipe pipe = PIPE_A;
+		bool visible;
+
+		visible = plane->get_hw_state(plane, &pipe);
+
+		crtc = intel_crtc_for_pipe(dev_priv, pipe);
+		crtc_state = to_intel_crtc_state(crtc->base.state);
+
+		intel_set_plane_visible(crtc_state, plane_state, visible);
+
+		drm_dbg_kms(&dev_priv->drm,
+			    "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
+			    plane->base.base.id, plane->base.name,
+			    str_enabled_disabled(visible), pipe_name(pipe));
+	}
+
+	for_each_intel_crtc(&dev_priv->drm, crtc) {
+		struct intel_crtc_state *crtc_state =
+			to_intel_crtc_state(crtc->base.state);
+
+		intel_plane_fixup_bitmasks(crtc_state);
+	}
+}
+
+static void intel_modeset_readout_hw_state(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_cdclk_state *cdclk_state =
+		to_intel_cdclk_state(dev_priv->cdclk.obj.state);
+	struct intel_dbuf_state *dbuf_state =
+		to_intel_dbuf_state(dev_priv->dbuf.obj.state);
+	enum pipe pipe;
+	struct intel_crtc *crtc;
+	struct intel_encoder *encoder;
+	struct intel_connector *connector;
+	struct drm_connector_list_iter conn_iter;
+	u8 active_pipes = 0;
+
+	for_each_intel_crtc(dev, crtc) {
+		struct intel_crtc_state *crtc_state =
+			to_intel_crtc_state(crtc->base.state);
+
+		__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
+		intel_crtc_free_hw_state(crtc_state);
+		intel_crtc_state_reset(crtc_state, crtc);
+
+		intel_crtc_get_pipe_config(crtc_state);
+
+		crtc_state->hw.enable = crtc_state->hw.active;
+
+		crtc->base.enabled = crtc_state->hw.enable;
+		crtc->active = crtc_state->hw.active;
+
+		if (crtc_state->hw.active)
+			active_pipes |= BIT(crtc->pipe);
+
+		drm_dbg_kms(&dev_priv->drm,
+			    "[CRTC:%d:%s] hw state readout: %s\n",
+			    crtc->base.base.id, crtc->base.name,
+			    str_enabled_disabled(crtc_state->hw.active));
+	}
+
+	cdclk_state->active_pipes = active_pipes;
+	dbuf_state->active_pipes = active_pipes;
+
+	readout_plane_state(dev_priv);
+
+	for_each_intel_encoder(dev, encoder) {
+		struct intel_crtc_state *crtc_state = NULL;
+
+		pipe = 0;
+
+		if (encoder->get_hw_state(encoder, &pipe)) {
+			crtc = intel_crtc_for_pipe(dev_priv, pipe);
+			crtc_state = to_intel_crtc_state(crtc->base.state);
+
+			encoder->base.crtc = &crtc->base;
+			intel_encoder_get_config(encoder, crtc_state);
+
+			/* read out to slave crtc as well for bigjoiner */
+			if (crtc_state->bigjoiner_pipes) {
+				struct intel_crtc *slave_crtc;
+
+				/* encoder should read be linked to bigjoiner master */
+				WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
+
+				for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc,
+								 intel_crtc_bigjoiner_slave_pipes(crtc_state)) {
+					struct intel_crtc_state *slave_crtc_state;
+
+					slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state);
+					intel_encoder_get_config(encoder, slave_crtc_state);
+				}
+			}
+		} else {
+			encoder->base.crtc = NULL;
+		}
+
+		if (encoder->sync_state)
+			encoder->sync_state(encoder, crtc_state);
+
+		drm_dbg_kms(&dev_priv->drm,
+			    "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
+			    encoder->base.base.id, encoder->base.name,
+			    str_enabled_disabled(encoder->base.crtc),
+			    pipe_name(pipe));
+	}
+
+	intel_dpll_readout_hw_state(dev_priv);
+
+	drm_connector_list_iter_begin(dev, &conn_iter);
+	for_each_intel_connector_iter(connector, &conn_iter) {
+		if (connector->get_hw_state(connector)) {
+			struct intel_crtc_state *crtc_state;
+			struct intel_crtc *crtc;
+
+			connector->base.dpms = DRM_MODE_DPMS_ON;
+
+			encoder = intel_attached_encoder(connector);
+			connector->base.encoder = &encoder->base;
+
+			crtc = to_intel_crtc(encoder->base.crtc);
+			crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
+
+			if (crtc_state && crtc_state->hw.active) {
+				/*
+				 * This has to be done during hardware readout
+				 * because anything calling .crtc_disable may
+				 * rely on the connector_mask being accurate.
+				 */
+				crtc_state->uapi.connector_mask |=
+					drm_connector_mask(&connector->base);
+				crtc_state->uapi.encoder_mask |=
+					drm_encoder_mask(&encoder->base);
+			}
+		} else {
+			connector->base.dpms = DRM_MODE_DPMS_OFF;
+			connector->base.encoder = NULL;
+		}
+		drm_dbg_kms(&dev_priv->drm,
+			    "[CONNECTOR:%d:%s] hw state readout: %s\n",
+			    connector->base.base.id, connector->base.name,
+			    str_enabled_disabled(connector->base.encoder));
+	}
+	drm_connector_list_iter_end(&conn_iter);
+
+	for_each_intel_crtc(dev, crtc) {
+		struct intel_bw_state *bw_state =
+			to_intel_bw_state(dev_priv->bw_obj.state);
+		struct intel_crtc_state *crtc_state =
+			to_intel_crtc_state(crtc->base.state);
+		struct intel_plane *plane;
+		int min_cdclk = 0;
+
+		if (crtc_state->hw.active) {
+			/*
+			 * The initial mode needs to be set in order to keep
+			 * the atomic core happy. It wants a valid mode if the
+			 * crtc's enabled, so we do the above call.
+			 *
+			 * But we don't set all the derived state fully, hence
+			 * set a flag to indicate that a full recalculation is
+			 * needed on the next commit.
+			 */
+			crtc_state->inherited = true;
+
+			intel_crtc_update_active_timings(crtc_state);
+
+			intel_crtc_copy_hw_to_uapi_state(crtc_state);
+		}
+
+		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+			const struct intel_plane_state *plane_state =
+				to_intel_plane_state(plane->base.state);
+
+			/*
+			 * FIXME don't have the fb yet, so can't
+			 * use intel_plane_data_rate() :(
+			 */
+			if (plane_state->uapi.visible)
+				crtc_state->data_rate[plane->id] =
+					4 * crtc_state->pixel_rate;
+			/*
+			 * FIXME don't have the fb yet, so can't
+			 * use plane->min_cdclk() :(
+			 */
+			if (plane_state->uapi.visible && plane->min_cdclk) {
+				if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10)
+					crtc_state->min_cdclk[plane->id] =
+						DIV_ROUND_UP(crtc_state->pixel_rate, 2);
+				else
+					crtc_state->min_cdclk[plane->id] =
+						crtc_state->pixel_rate;
+			}
+			drm_dbg_kms(&dev_priv->drm,
+				    "[PLANE:%d:%s] min_cdclk %d kHz\n",
+				    plane->base.base.id, plane->base.name,
+				    crtc_state->min_cdclk[plane->id]);
+		}
+
+		if (crtc_state->hw.active) {
+			min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
+			if (drm_WARN_ON(dev, min_cdclk < 0))
+				min_cdclk = 0;
+		}
+
+		cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
+		cdclk_state->min_voltage_level[crtc->pipe] =
+			crtc_state->min_voltage_level;
+
+		intel_bw_crtc_update(bw_state, crtc_state);
+	}
+}
+
+static void
+get_encoder_power_domains(struct drm_i915_private *dev_priv)
+{
+	struct intel_encoder *encoder;
+
+	for_each_intel_encoder(&dev_priv->drm, encoder) {
+		struct intel_crtc_state *crtc_state;
+
+		if (!encoder->get_power_domains)
+			continue;
+
+		/*
+		 * MST-primary and inactive encoders don't have a crtc state
+		 * and neither of these require any power domain references.
+		 */
+		if (!encoder->base.crtc)
+			continue;
+
+		crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
+		encoder->get_power_domains(encoder, crtc_state);
+	}
+}
+
+static void intel_early_display_was(struct drm_i915_private *dev_priv)
+{
+	/*
+	 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl
+	 * Also known as Wa_14010480278.
+	 */
+	if (IS_DISPLAY_VER(dev_priv, 10, 12))
+		intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
+			       intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
+
+	if (IS_HASWELL(dev_priv)) {
+		/*
+		 * WaRsPkgCStateDisplayPMReq:hsw
+		 * System hang if this isn't done before disabling all planes!
+		 */
+		intel_de_write(dev_priv, CHICKEN_PAR1_1,
+			       intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
+	}
+
+	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) {
+		/* Display WA #1142:kbl,cfl,cml */
+		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
+			     KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
+		intel_de_rmw(dev_priv, CHICKEN_MISC_2,
+			     KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
+			     KBL_ARB_FILL_SPARE_14);
+	}
+}
+
+void intel_modeset_setup_hw_state(struct drm_device *dev,
+				  struct drm_modeset_acquire_ctx *ctx)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_encoder *encoder;
+	struct intel_crtc *crtc;
+	intel_wakeref_t wakeref;
+
+	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
+
+	intel_early_display_was(dev_priv);
+	intel_modeset_readout_hw_state(dev);
+
+	/* HW state is read out, now we need to sanitize this mess. */
+	get_encoder_power_domains(dev_priv);
+
+	intel_pch_sanitize(dev_priv);
+
+	/*
+	 * intel_sanitize_plane_mapping() may need to do vblank
+	 * waits, so we need vblank interrupts restored beforehand.
+	 */
+	for_each_intel_crtc(&dev_priv->drm, crtc) {
+		struct intel_crtc_state *crtc_state =
+			to_intel_crtc_state(crtc->base.state);
+
+		intel_sanitize_fifo_underrun_reporting(crtc_state);
+
+		drm_crtc_vblank_reset(&crtc->base);
+
+		if (crtc_state->hw.active)
+			intel_crtc_vblank_on(crtc_state);
+	}
+
+	intel_fbc_sanitize(dev_priv);
+
+	intel_sanitize_plane_mapping(dev_priv);
+
+	for_each_intel_encoder(dev, encoder)
+		intel_sanitize_encoder(encoder);
+
+	for_each_intel_crtc(&dev_priv->drm, crtc) {
+		struct intel_crtc_state *crtc_state =
+			to_intel_crtc_state(crtc->base.state);
+
+		intel_sanitize_crtc(crtc, ctx);
+		intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state");
+	}
+
+	intel_modeset_update_connector_atomic_state(dev);
+
+	intel_dpll_sanitize_state(dev_priv);
+
+	if (IS_G4X(dev_priv)) {
+		g4x_wm_get_hw_state(dev_priv);
+		g4x_wm_sanitize(dev_priv);
+	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+		vlv_wm_get_hw_state(dev_priv);
+		vlv_wm_sanitize(dev_priv);
+	} else if (DISPLAY_VER(dev_priv) >= 9) {
+		skl_wm_get_hw_state(dev_priv);
+		skl_wm_sanitize(dev_priv);
+	} else if (HAS_PCH_SPLIT(dev_priv)) {
+		ilk_wm_get_hw_state(dev_priv);
+	}
+
+	for_each_intel_crtc(dev, crtc) {
+		struct intel_crtc_state *crtc_state =
+			to_intel_crtc_state(crtc->base.state);
+		struct intel_power_domain_mask put_domains;
+
+		intel_modeset_get_crtc_power_domains(crtc_state, &put_domains);
+		if (drm_WARN_ON(dev, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
+			intel_modeset_put_crtc_power_domains(crtc, &put_domains);
+	}
+
+	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
+
+	intel_power_domains_sanitize_state(dev_priv);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.h b/drivers/gpu/drm/i915/display/intel_modeset_setup.h
new file mode 100644
index 0000000000000..c29b34c6a7b00
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_MODESET_SETUP_H__
+#define __INTEL_MODESET_SETUP_H__
+
+struct drm_device;
+struct drm_modeset_acquire_ctx;
+
+void intel_modeset_setup_hw_state(struct drm_device *dev,
+				  struct drm_modeset_acquire_ctx *ctx);
+
+#endif /* __INTEL_MODESET_SETUP_H__ */
-- 
GitLab


From 47fa33cc54615161ec5192389e55f3b95274f56f Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Fri, 17 Jun 2022 12:48:17 +0300
Subject: [PATCH 0881/1731] drm/i915/display: convert modeset setup to struct
 drm_i915_private *i915
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Pass struct drm_i915_private * instead of struct drm_device *, and
rename dev_priv to i915.

v2: Rebase

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220617094817.3466584-2-jani.nikula@intel.com
---
 drivers/gpu/drm/i915/display/intel_display.c  |   4 +-
 .../drm/i915/display/intel_modeset_setup.c    | 194 +++++++++---------
 .../drm/i915/display/intel_modeset_setup.h    |   4 +-
 3 files changed, 100 insertions(+), 102 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 712f7c9afc451..8f29df6cca85d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -838,7 +838,7 @@ __intel_display_resume(struct drm_i915_private *i915,
 	struct drm_crtc *crtc;
 	int i, ret;
 
-	intel_modeset_setup_hw_state(&i915->drm, ctx);
+	intel_modeset_setup_hw_state(i915, ctx);
 	intel_vga_redisable(i915);
 
 	if (!state)
@@ -8766,7 +8766,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
 	intel_setup_outputs(i915);
 
 	drm_modeset_lock_all(dev);
-	intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
+	intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx);
 	intel_acpi_assign_connector_fwnodes(i915);
 	drm_modeset_unlock_all(dev);
 
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index c340f33932462..f0e04d3904c67 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -28,13 +28,13 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
 					struct drm_modeset_acquire_ctx *ctx)
 {
 	struct intel_encoder *encoder;
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	struct intel_bw_state *bw_state =
-		to_intel_bw_state(dev_priv->bw_obj.state);
+		to_intel_bw_state(i915->bw_obj.state);
 	struct intel_cdclk_state *cdclk_state =
-		to_intel_cdclk_state(dev_priv->cdclk.obj.state);
+		to_intel_cdclk_state(i915->cdclk.obj.state);
 	struct intel_dbuf_state *dbuf_state =
-		to_intel_dbuf_state(dev_priv->dbuf.obj.state);
+		to_intel_dbuf_state(i915->dbuf.obj.state);
 	struct intel_crtc_state *crtc_state =
 		to_intel_crtc_state(crtc->base.state);
 	struct intel_plane *plane;
@@ -46,7 +46,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
 	if (!crtc_state->hw.active)
 		return;
 
-	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+	for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
 		const struct intel_plane_state *plane_state =
 			to_intel_plane_state(plane->base.state);
 
@@ -54,9 +54,9 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
 			intel_plane_disable_noatomic(crtc, plane);
 	}
 
-	state = drm_atomic_state_alloc(&dev_priv->drm);
+	state = drm_atomic_state_alloc(&i915->drm);
 	if (!state) {
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(&i915->drm,
 			    "failed to disable [CRTC:%d:%s], out of memory",
 			    crtc->base.base.id, crtc->base.name);
 		return;
@@ -68,20 +68,20 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
 	temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
 	ret = drm_atomic_add_affected_connectors(state, &crtc->base);
 
-	drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
+	drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret);
 
-	dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc);
+	i915->display->crtc_disable(to_intel_atomic_state(state), crtc);
 
 	drm_atomic_state_put(state);
 
-	drm_dbg_kms(&dev_priv->drm,
+	drm_dbg_kms(&i915->drm,
 		    "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
 		    crtc->base.base.id, crtc->base.name);
 
 	crtc->active = false;
 	crtc->base.enabled = false;
 
-	drm_WARN_ON(&dev_priv->drm,
+	drm_WARN_ON(&i915->drm,
 		    drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
 	crtc_state->uapi.active = false;
 	crtc_state->uapi.connector_mask = 0;
@@ -89,14 +89,14 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
 	intel_crtc_free_hw_state(crtc_state);
 	memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
 
-	for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
+	for_each_encoder_on_crtc(&i915->drm, &crtc->base, encoder)
 		encoder->base.crtc = NULL;
 
 	intel_fbc_disable(crtc);
-	intel_update_watermarks(dev_priv);
+	intel_update_watermarks(i915);
 	intel_disable_shared_dpll(crtc_state);
 
-	intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains);
+	intel_display_power_put_all_in_set(i915, &crtc->enabled_power_domains);
 
 	cdclk_state->min_cdclk[pipe] = 0;
 	cdclk_state->min_voltage_level[pipe] = 0;
@@ -108,12 +108,12 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
 	bw_state->num_active_planes[pipe] = 0;
 }
 
-static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
+static void intel_modeset_update_connector_atomic_state(struct drm_i915_private *i915)
 {
 	struct intel_connector *connector;
 	struct drm_connector_list_iter conn_iter;
 
-	drm_connector_list_iter_begin(dev, &conn_iter);
+	drm_connector_list_iter_begin(&i915->drm, &conn_iter);
 	for_each_intel_connector_iter(connector, &conn_iter) {
 		struct drm_connector_state *conn_state = connector->base.state;
 		struct intel_encoder *encoder =
@@ -163,14 +163,14 @@ static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state
 }
 
 static void
-intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
+intel_sanitize_plane_mapping(struct drm_i915_private *i915)
 {
 	struct intel_crtc *crtc;
 
-	if (DISPLAY_VER(dev_priv) >= 4)
+	if (DISPLAY_VER(i915) >= 4)
 		return;
 
-	for_each_intel_crtc(&dev_priv->drm, crtc) {
+	for_each_intel_crtc(&i915->drm, crtc) {
 		struct intel_plane *plane =
 			to_intel_plane(crtc->base.primary);
 		struct intel_crtc *plane_crtc;
@@ -182,11 +182,11 @@ intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
 		if (pipe == crtc->pipe)
 			continue;
 
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(&i915->drm,
 			    "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
 			    plane->base.base.id, plane->base.name);
 
-		plane_crtc = intel_crtc_for_pipe(dev_priv, pipe);
+		plane_crtc = intel_crtc_for_pipe(i915, pipe);
 		intel_plane_disable_noatomic(plane_crtc, plane);
 	}
 }
@@ -252,14 +252,14 @@ static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state
 static void intel_sanitize_crtc(struct intel_crtc *crtc,
 				struct drm_modeset_acquire_ctx *ctx)
 {
-	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
 
 	if (crtc_state->hw.active) {
 		struct intel_plane *plane;
 
 		/* Disable everything but the primary plane */
-		for_each_intel_plane_on_crtc(dev, crtc, plane) {
+		for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
 			const struct intel_plane_state *plane_state =
 				to_intel_plane_state(plane->base.state);
 
@@ -284,7 +284,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
 
 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 
 	/*
 	 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
@@ -296,7 +296,7 @@ static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
 	 * without several WARNs, but for now let's take the easy
 	 * road.
 	 */
-	return IS_SANDYBRIDGE(dev_priv) &&
+	return IS_SANDYBRIDGE(i915) &&
 		crtc_state->hw.active &&
 		crtc_state->shared_dpll &&
 		crtc_state->port_clock == 0;
@@ -304,7 +304,7 @@ static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
 
 static void intel_sanitize_encoder(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	struct intel_connector *connector;
 	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 	struct intel_crtc_state *crtc_state = crtc ?
@@ -319,7 +319,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
 		crtc_state->hw.active;
 
 	if (crtc_state && has_bogus_dpll_config(crtc_state)) {
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(&i915->drm,
 			    "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
 			    pipe_name(crtc->pipe));
 		has_active_crtc = false;
@@ -327,7 +327,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
 
 	connector = intel_encoder_find_connector(encoder);
 	if (connector && !has_active_crtc) {
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(&i915->drm,
 			    "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
 			    encoder->base.base.id,
 			    encoder->base.name);
@@ -340,7 +340,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
 		if (crtc_state) {
 			struct drm_encoder *best_encoder;
 
-			drm_dbg_kms(&dev_priv->drm,
+			drm_dbg_kms(&i915->drm,
 				    "[ENCODER:%d:%s] manually disabled\n",
 				    encoder->base.base.id,
 				    encoder->base.name);
@@ -374,17 +374,17 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
 	/* notify opregion of the sanitized encoder state */
 	intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
 
-	if (HAS_DDI(dev_priv))
+	if (HAS_DDI(i915))
 		intel_ddi_sanitize_encoder_pll_mapping(encoder);
 }
 
 /* FIXME read out full plane state for all planes */
-static void readout_plane_state(struct drm_i915_private *dev_priv)
+static void readout_plane_state(struct drm_i915_private *i915)
 {
 	struct intel_plane *plane;
 	struct intel_crtc *crtc;
 
-	for_each_intel_plane(&dev_priv->drm, plane) {
+	for_each_intel_plane(&i915->drm, plane) {
 		struct intel_plane_state *plane_state =
 			to_intel_plane_state(plane->base.state);
 		struct intel_crtc_state *crtc_state;
@@ -393,18 +393,18 @@ static void readout_plane_state(struct drm_i915_private *dev_priv)
 
 		visible = plane->get_hw_state(plane, &pipe);
 
-		crtc = intel_crtc_for_pipe(dev_priv, pipe);
+		crtc = intel_crtc_for_pipe(i915, pipe);
 		crtc_state = to_intel_crtc_state(crtc->base.state);
 
 		intel_set_plane_visible(crtc_state, plane_state, visible);
 
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(&i915->drm,
 			    "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
 			    plane->base.base.id, plane->base.name,
 			    str_enabled_disabled(visible), pipe_name(pipe));
 	}
 
-	for_each_intel_crtc(&dev_priv->drm, crtc) {
+	for_each_intel_crtc(&i915->drm, crtc) {
 		struct intel_crtc_state *crtc_state =
 			to_intel_crtc_state(crtc->base.state);
 
@@ -412,13 +412,12 @@ static void readout_plane_state(struct drm_i915_private *dev_priv)
 	}
 }
 
-static void intel_modeset_readout_hw_state(struct drm_device *dev)
+static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
 {
-	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_cdclk_state *cdclk_state =
-		to_intel_cdclk_state(dev_priv->cdclk.obj.state);
+		to_intel_cdclk_state(i915->cdclk.obj.state);
 	struct intel_dbuf_state *dbuf_state =
-		to_intel_dbuf_state(dev_priv->dbuf.obj.state);
+		to_intel_dbuf_state(i915->dbuf.obj.state);
 	enum pipe pipe;
 	struct intel_crtc *crtc;
 	struct intel_encoder *encoder;
@@ -426,7 +425,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 	struct drm_connector_list_iter conn_iter;
 	u8 active_pipes = 0;
 
-	for_each_intel_crtc(dev, crtc) {
+	for_each_intel_crtc(&i915->drm, crtc) {
 		struct intel_crtc_state *crtc_state =
 			to_intel_crtc_state(crtc->base.state);
 
@@ -444,7 +443,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 		if (crtc_state->hw.active)
 			active_pipes |= BIT(crtc->pipe);
 
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(&i915->drm,
 			    "[CRTC:%d:%s] hw state readout: %s\n",
 			    crtc->base.base.id, crtc->base.name,
 			    str_enabled_disabled(crtc_state->hw.active));
@@ -453,15 +452,15 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 	cdclk_state->active_pipes = active_pipes;
 	dbuf_state->active_pipes = active_pipes;
 
-	readout_plane_state(dev_priv);
+	readout_plane_state(i915);
 
-	for_each_intel_encoder(dev, encoder) {
+	for_each_intel_encoder(&i915->drm, encoder) {
 		struct intel_crtc_state *crtc_state = NULL;
 
 		pipe = 0;
 
 		if (encoder->get_hw_state(encoder, &pipe)) {
-			crtc = intel_crtc_for_pipe(dev_priv, pipe);
+			crtc = intel_crtc_for_pipe(i915, pipe);
 			crtc_state = to_intel_crtc_state(crtc->base.state);
 
 			encoder->base.crtc = &crtc->base;
@@ -474,7 +473,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 				/* encoder should read be linked to bigjoiner master */
 				WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
 
-				for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc,
+				for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
 								 intel_crtc_bigjoiner_slave_pipes(crtc_state)) {
 					struct intel_crtc_state *slave_crtc_state;
 
@@ -489,16 +488,16 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 		if (encoder->sync_state)
 			encoder->sync_state(encoder, crtc_state);
 
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(&i915->drm,
 			    "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
 			    encoder->base.base.id, encoder->base.name,
 			    str_enabled_disabled(encoder->base.crtc),
 			    pipe_name(pipe));
 	}
 
-	intel_dpll_readout_hw_state(dev_priv);
+	intel_dpll_readout_hw_state(i915);
 
-	drm_connector_list_iter_begin(dev, &conn_iter);
+	drm_connector_list_iter_begin(&i915->drm, &conn_iter);
 	for_each_intel_connector_iter(connector, &conn_iter) {
 		if (connector->get_hw_state(connector)) {
 			struct intel_crtc_state *crtc_state;
@@ -527,16 +526,16 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 			connector->base.dpms = DRM_MODE_DPMS_OFF;
 			connector->base.encoder = NULL;
 		}
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(&i915->drm,
 			    "[CONNECTOR:%d:%s] hw state readout: %s\n",
 			    connector->base.base.id, connector->base.name,
 			    str_enabled_disabled(connector->base.encoder));
 	}
 	drm_connector_list_iter_end(&conn_iter);
 
-	for_each_intel_crtc(dev, crtc) {
+	for_each_intel_crtc(&i915->drm, crtc) {
 		struct intel_bw_state *bw_state =
-			to_intel_bw_state(dev_priv->bw_obj.state);
+			to_intel_bw_state(i915->bw_obj.state);
 		struct intel_crtc_state *crtc_state =
 			to_intel_crtc_state(crtc->base.state);
 		struct intel_plane *plane;
@@ -559,7 +558,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 			intel_crtc_copy_hw_to_uapi_state(crtc_state);
 		}
 
-		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+		for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
 			const struct intel_plane_state *plane_state =
 				to_intel_plane_state(plane->base.state);
 
@@ -575,14 +574,14 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 			 * use plane->min_cdclk() :(
 			 */
 			if (plane_state->uapi.visible && plane->min_cdclk) {
-				if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10)
+				if (crtc_state->double_wide || DISPLAY_VER(i915) >= 10)
 					crtc_state->min_cdclk[plane->id] =
 						DIV_ROUND_UP(crtc_state->pixel_rate, 2);
 				else
 					crtc_state->min_cdclk[plane->id] =
 						crtc_state->pixel_rate;
 			}
-			drm_dbg_kms(&dev_priv->drm,
+			drm_dbg_kms(&i915->drm,
 				    "[PLANE:%d:%s] min_cdclk %d kHz\n",
 				    plane->base.base.id, plane->base.name,
 				    crtc_state->min_cdclk[plane->id]);
@@ -590,7 +589,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 
 		if (crtc_state->hw.active) {
 			min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
-			if (drm_WARN_ON(dev, min_cdclk < 0))
+			if (drm_WARN_ON(&i915->drm, min_cdclk < 0))
 				min_cdclk = 0;
 		}
 
@@ -603,11 +602,11 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 }
 
 static void
-get_encoder_power_domains(struct drm_i915_private *dev_priv)
+get_encoder_power_domains(struct drm_i915_private *i915)
 {
 	struct intel_encoder *encoder;
 
-	for_each_intel_encoder(&dev_priv->drm, encoder) {
+	for_each_intel_encoder(&i915->drm, encoder) {
 		struct intel_crtc_state *crtc_state;
 
 		if (!encoder->get_power_domains)
@@ -625,58 +624,57 @@ get_encoder_power_domains(struct drm_i915_private *dev_priv)
 	}
 }
 
-static void intel_early_display_was(struct drm_i915_private *dev_priv)
+static void intel_early_display_was(struct drm_i915_private *i915)
 {
 	/*
 	 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl
 	 * Also known as Wa_14010480278.
 	 */
-	if (IS_DISPLAY_VER(dev_priv, 10, 12))
-		intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
-			       intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
+	if (IS_DISPLAY_VER(i915, 10, 12))
+		intel_de_write(i915, GEN9_CLKGATE_DIS_0,
+			       intel_de_read(i915, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
 
-	if (IS_HASWELL(dev_priv)) {
+	if (IS_HASWELL(i915)) {
 		/*
 		 * WaRsPkgCStateDisplayPMReq:hsw
 		 * System hang if this isn't done before disabling all planes!
 		 */
-		intel_de_write(dev_priv, CHICKEN_PAR1_1,
-			       intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
+		intel_de_write(i915, CHICKEN_PAR1_1,
+			       intel_de_read(i915, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
 	}
 
-	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) {
+	if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) {
 		/* Display WA #1142:kbl,cfl,cml */
-		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
+		intel_de_rmw(i915, CHICKEN_PAR1_1,
 			     KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
-		intel_de_rmw(dev_priv, CHICKEN_MISC_2,
+		intel_de_rmw(i915, CHICKEN_MISC_2,
 			     KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
 			     KBL_ARB_FILL_SPARE_14);
 	}
 }
 
-void intel_modeset_setup_hw_state(struct drm_device *dev,
+void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
 				  struct drm_modeset_acquire_ctx *ctx)
 {
-	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_encoder *encoder;
 	struct intel_crtc *crtc;
 	intel_wakeref_t wakeref;
 
-	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
+	wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT);
 
-	intel_early_display_was(dev_priv);
-	intel_modeset_readout_hw_state(dev);
+	intel_early_display_was(i915);
+	intel_modeset_readout_hw_state(i915);
 
 	/* HW state is read out, now we need to sanitize this mess. */
-	get_encoder_power_domains(dev_priv);
+	get_encoder_power_domains(i915);
 
-	intel_pch_sanitize(dev_priv);
+	intel_pch_sanitize(i915);
 
 	/*
 	 * intel_sanitize_plane_mapping() may need to do vblank
 	 * waits, so we need vblank interrupts restored beforehand.
 	 */
-	for_each_intel_crtc(&dev_priv->drm, crtc) {
+	for_each_intel_crtc(&i915->drm, crtc) {
 		struct intel_crtc_state *crtc_state =
 			to_intel_crtc_state(crtc->base.state);
 
@@ -688,14 +686,14 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
 			intel_crtc_vblank_on(crtc_state);
 	}
 
-	intel_fbc_sanitize(dev_priv);
+	intel_fbc_sanitize(i915);
 
-	intel_sanitize_plane_mapping(dev_priv);
+	intel_sanitize_plane_mapping(i915);
 
-	for_each_intel_encoder(dev, encoder)
+	for_each_intel_encoder(&i915->drm, encoder)
 		intel_sanitize_encoder(encoder);
 
-	for_each_intel_crtc(&dev_priv->drm, crtc) {
+	for_each_intel_crtc(&i915->drm, crtc) {
 		struct intel_crtc_state *crtc_state =
 			to_intel_crtc_state(crtc->base.state);
 
@@ -703,34 +701,34 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
 		intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state");
 	}
 
-	intel_modeset_update_connector_atomic_state(dev);
-
-	intel_dpll_sanitize_state(dev_priv);
-
-	if (IS_G4X(dev_priv)) {
-		g4x_wm_get_hw_state(dev_priv);
-		g4x_wm_sanitize(dev_priv);
-	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
-		vlv_wm_get_hw_state(dev_priv);
-		vlv_wm_sanitize(dev_priv);
-	} else if (DISPLAY_VER(dev_priv) >= 9) {
-		skl_wm_get_hw_state(dev_priv);
-		skl_wm_sanitize(dev_priv);
-	} else if (HAS_PCH_SPLIT(dev_priv)) {
-		ilk_wm_get_hw_state(dev_priv);
+	intel_modeset_update_connector_atomic_state(i915);
+
+	intel_dpll_sanitize_state(i915);
+
+	if (IS_G4X(i915)) {
+		g4x_wm_get_hw_state(i915);
+		g4x_wm_sanitize(i915);
+	} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
+		vlv_wm_get_hw_state(i915);
+		vlv_wm_sanitize(i915);
+	} else if (DISPLAY_VER(i915) >= 9) {
+		skl_wm_get_hw_state(i915);
+		skl_wm_sanitize(i915);
+	} else if (HAS_PCH_SPLIT(i915)) {
+		ilk_wm_get_hw_state(i915);
 	}
 
-	for_each_intel_crtc(dev, crtc) {
+	for_each_intel_crtc(&i915->drm, crtc) {
 		struct intel_crtc_state *crtc_state =
 			to_intel_crtc_state(crtc->base.state);
 		struct intel_power_domain_mask put_domains;
 
 		intel_modeset_get_crtc_power_domains(crtc_state, &put_domains);
-		if (drm_WARN_ON(dev, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
+		if (drm_WARN_ON(&i915->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
 			intel_modeset_put_crtc_power_domains(crtc, &put_domains);
 	}
 
-	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
+	intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
 
-	intel_power_domains_sanitize_state(dev_priv);
+	intel_power_domains_sanitize_state(i915);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.h b/drivers/gpu/drm/i915/display/intel_modeset_setup.h
index c29b34c6a7b00..3beff67b33d03 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.h
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.h
@@ -6,10 +6,10 @@
 #ifndef __INTEL_MODESET_SETUP_H__
 #define __INTEL_MODESET_SETUP_H__
 
-struct drm_device;
+struct drm_i915_private;
 struct drm_modeset_acquire_ctx;
 
-void intel_modeset_setup_hw_state(struct drm_device *dev,
+void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
 				  struct drm_modeset_acquire_ctx *ctx);
 
 #endif /* __INTEL_MODESET_SETUP_H__ */
-- 
GitLab


From c7b28f52f406bc89d15ca0ccbc47994f979f2fcd Mon Sep 17 00:00:00 2001
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
Date: Mon, 13 Jun 2022 12:22:41 +0200
Subject: [PATCH 0882/1731] drm/i915/display: Re-add check for low voltage sku
 for max dp source rate

This reverts commit 73867c8709b5 ("drm/i915/display: Remove check for
low voltage sku for max dp source rate"), which, on an i7-11850H iGPU
with a Thinkpad X1 Extreme Gen 4, attached to a LG LP160UQ1-SPB1
embedded panel, causes wild flickering glitching technicolor
pyrotechnics on resumption from suspend. The display shows strobing
colors in an utter disaster explosion of pantone, as though bombs were
dropped on the leprechauns at the base of the rainbow.

Rebooting the machine fixes the issue, presumably because the display is
initialized by firmware rather than by i915. Otherwise, the GPU appears
to work fine.

Bisection traced it back to this commit, which makes sense given the
issues.

Note: This re-opens, and puts back to the drawing board,
https://gitlab.freedesktop.org/drm/intel/-/issues/5272 which was fixed
by the regressing commit.

Fixes: 73867c8709b5 ("drm/i915/display: Remove check for low voltage sku for max dp source rate")
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6205
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Jani Saarinen <jani.saarinen@intel.com>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220613102241.9236-1-Jason@zx2c4.com
(cherry picked from commit d5929835080a60f9119d024fa42f315913942f76)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 32 ++++++++++++++++++++++---
 1 file changed, 29 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e4a79c11fd255..ff67899522cf7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -388,13 +388,23 @@ static int dg2_max_source_rate(struct intel_dp *intel_dp)
 	return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
 }
 
+static bool is_low_voltage_sku(struct drm_i915_private *i915, enum phy phy)
+{
+	u32 voltage;
+
+	voltage = intel_de_read(i915, ICL_PORT_COMP_DW3(phy)) & VOLTAGE_INFO_MASK;
+
+	return voltage == VOLTAGE_INFO_0_85V;
+}
+
 static int icl_max_source_rate(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 
-	if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
+	if (intel_phy_is_combo(dev_priv, phy) &&
+	    (is_low_voltage_sku(dev_priv, phy) || !intel_dp_is_edp(intel_dp)))
 		return 540000;
 
 	return 810000;
@@ -402,7 +412,23 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
 
 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 {
-	if (intel_dp_is_edp(intel_dp))
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
+
+	if (intel_dp_is_edp(intel_dp) || is_low_voltage_sku(dev_priv, phy))
+		return 540000;
+
+	return 810000;
+}
+
+static int dg1_max_source_rate(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
+
+	if (intel_phy_is_combo(i915, phy) && is_low_voltage_sku(i915, phy))
 		return 540000;
 
 	return 810000;
@@ -445,7 +471,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
 			max_rate = dg2_max_source_rate(intel_dp);
 		else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 			 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
-			max_rate = 810000;
+			max_rate = dg1_max_source_rate(intel_dp);
 		else if (IS_JSL_EHL(dev_priv))
 			max_rate = ehl_max_source_rate(intel_dp);
 		else
-- 
GitLab


From 6434cf630086eea2d091f122f5802582a05d9d1c Mon Sep 17 00:00:00 2001
From: Animesh Manna <animesh.manna@intel.com>
Date: Mon, 20 Jun 2022 12:21:38 +0530
Subject: [PATCH 0883/1731] drm/i915/bios: calculate panel type as per child
 device index in VBT
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Each LFP may have different panel type which is stored in LFP data
data block. Based on the child device index respective panel-type/
panel-type2 field will be used.

v1: Initial rfc verion.
v2: Based on review comments from Jani,
- Used panel-type instead addition panel-index variable.
- DEVICE_HANDLE_* name changed and placed before DEVICE_TYPE_*
macro.
v3:
- passing intel_bios_encoder_data as argument of
intel_bios_init_panel(). Passing NULL to indicate encoder is not
initialized yet for dsi as current focus is to enable dual EDP. [Jani]
v4:
- encoder->devdata used which is initialized before from vbt
structure. [Jani]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220620065138.5126-1-animesh.manna@intel.com
---
 drivers/gpu/drm/i915/display/icl_dsi.c        |  2 +-
 drivers/gpu/drm/i915/display/intel_bios.c     | 16 ++++++++++++++--
 drivers/gpu/drm/i915/display/intel_bios.h     |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  3 ++-
 drivers/gpu/drm/i915/display/intel_lvds.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_sdvo.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |  4 ++++
 drivers/gpu/drm/i915/display/vlv_dsi.c        |  2 +-
 8 files changed, 25 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 996bd3fdda6bd..712e371a2bf75 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -2049,7 +2049,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 	/* attach connector to encoder */
 	intel_connector_attach_encoder(intel_connector, encoder);
 
-	intel_bios_init_panel(dev_priv, &intel_connector->panel, NULL);
+	intel_bios_init_panel(dev_priv, &intel_connector->panel, NULL, NULL);
 
 	mutex_lock(&dev->mode_config.mutex);
 	intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 82eef3b1ca879..e89bc1d665f46 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -603,12 +603,14 @@ get_lfp_data_tail(const struct bdb_lvds_lfp_data *data,
 }
 
 static int opregion_get_panel_type(struct drm_i915_private *i915,
+				   const struct intel_bios_encoder_data *devdata,
 				   const struct edid *edid)
 {
 	return intel_opregion_get_panel_type(i915);
 }
 
 static int vbt_get_panel_type(struct drm_i915_private *i915,
+			      const struct intel_bios_encoder_data *devdata,
 			      const struct edid *edid)
 {
 	const struct bdb_lvds_options *lvds_options;
@@ -624,10 +626,16 @@ static int vbt_get_panel_type(struct drm_i915_private *i915,
 		return -1;
 	}
 
+	if (devdata && devdata->child.handle == DEVICE_HANDLE_LFP2)
+		return lvds_options->panel_type2;
+
+	drm_WARN_ON(&i915->drm, devdata && devdata->child.handle != DEVICE_HANDLE_LFP1);
+
 	return lvds_options->panel_type;
 }
 
 static int pnpid_get_panel_type(struct drm_i915_private *i915,
+				const struct intel_bios_encoder_data *devdata,
 				const struct edid *edid)
 {
 	const struct bdb_lvds_lfp_data *data;
@@ -674,6 +682,7 @@ static int pnpid_get_panel_type(struct drm_i915_private *i915,
 }
 
 static int fallback_get_panel_type(struct drm_i915_private *i915,
+				   const struct intel_bios_encoder_data *devdata,
 				   const struct edid *edid)
 {
 	return 0;
@@ -687,11 +696,13 @@ enum panel_type {
 };
 
 static int get_panel_type(struct drm_i915_private *i915,
+			  const struct intel_bios_encoder_data *devdata,
 			  const struct edid *edid)
 {
 	struct {
 		const char *name;
 		int (*get_panel_type)(struct drm_i915_private *i915,
+				      const struct intel_bios_encoder_data *devdata,
 				      const struct edid *edid);
 		int panel_type;
 	} panel_types[] = {
@@ -715,7 +726,7 @@ static int get_panel_type(struct drm_i915_private *i915,
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(panel_types); i++) {
-		panel_types[i].panel_type = panel_types[i].get_panel_type(i915, edid);
+		panel_types[i].panel_type = panel_types[i].get_panel_type(i915, devdata, edid);
 
 		drm_WARN_ON(&i915->drm, panel_types[i].panel_type > 0xf &&
 			    panel_types[i].panel_type != 0xff);
@@ -3126,11 +3137,12 @@ out:
 
 void intel_bios_init_panel(struct drm_i915_private *i915,
 			   struct intel_panel *panel,
+			   const struct intel_bios_encoder_data *devdata,
 			   const struct edid *edid)
 {
 	init_vbt_panel_defaults(panel);
 
-	panel->vbt.panel_type = get_panel_type(i915, edid);
+	panel->vbt.panel_type = get_panel_type(i915, devdata, edid);
 
 	parse_panel_options(i915, panel);
 	parse_generic_dtd(i915, panel);
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index b112200ae0a0b..e47582b0de0a1 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -234,6 +234,7 @@ struct mipi_pps_data {
 void intel_bios_init(struct drm_i915_private *dev_priv);
 void intel_bios_init_panel(struct drm_i915_private *dev_priv,
 			   struct intel_panel *panel,
+			   const struct intel_bios_encoder_data *devdata,
 			   const struct edid *edid);
 void intel_bios_fini_panel(struct intel_panel *panel);
 void intel_bios_driver_remove(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 94ffbd7d807a4..728a44263b5f1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5193,6 +5193,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 	struct drm_device *dev = &dev_priv->drm;
 	struct drm_connector *connector = &intel_connector->base;
 	struct drm_display_mode *fixed_mode;
+	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	bool has_dpcd;
 	enum pipe pipe = INVALID_PIPE;
 	struct edid *edid;
@@ -5250,7 +5251,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 	intel_connector->edid = edid;
 
 	intel_bios_init_panel(dev_priv, &intel_connector->panel,
-			      IS_ERR(edid) ? NULL : edid);
+			      encoder->devdata, IS_ERR(edid) ? NULL : edid);
 
 	intel_panel_add_edid_fixed_modes(intel_connector,
 					 intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE,
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index e55802b454613..730480ac3300d 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -967,7 +967,7 @@ void intel_lvds_init(struct drm_i915_private *dev_priv)
 	}
 	intel_connector->edid = edid;
 
-	intel_bios_init_panel(dev_priv, &intel_connector->panel,
+	intel_bios_init_panel(dev_priv, &intel_connector->panel, NULL,
 			      IS_ERR(edid) ? NULL : edid);
 
 	/* Try EDID first */
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 81f700517e894..30c752d02d7c2 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -2900,7 +2900,7 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
 	if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
 		goto err;
 
-	intel_bios_init_panel(i915, &intel_connector->panel, NULL);
+	intel_bios_init_panel(i915, &intel_connector->panel, NULL, NULL);
 
 	/*
 	 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 3766c09bd65d9..509b0a419c20a 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -182,6 +182,10 @@ struct bdb_general_features {
 #define GPIO_PIN_ADD_DDC	0x04 /* "ADDCARD DDC GPIO pins" */
 #define GPIO_PIN_ADD_DDC_I2C	0x06 /* "ADDCARD DDC/I2C GPIO pins" */
 
+/* Device handle */
+#define DEVICE_HANDLE_LFP1	0x0008
+#define DEVICE_HANDLE_LFP2	0x0080
+
 /* Pre 915 */
 #define DEVICE_TYPE_NONE	0x00
 #define DEVICE_TYPE_CRT		0x01
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index abda0888c8d41..b9b1fed998740 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -1926,7 +1926,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
 
 	intel_dsi->panel_power_off_time = ktime_get_boottime();
 
-	intel_bios_init_panel(dev_priv, &intel_connector->panel, NULL);
+	intel_bios_init_panel(dev_priv, &intel_connector->panel, NULL, NULL);
 
 	if (intel_connector->panel.vbt.dsi.config->dual_link)
 		intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
-- 
GitLab


From a09d2d00af53b43c6f11e6ab3cb58443c2cac8a7 Mon Sep 17 00:00:00 2001
From: Hyunwoo Kim <imv4bel@gmail.com>
Date: Mon, 20 Jun 2022 07:17:46 -0700
Subject: [PATCH 0884/1731] video: fbdev: pxa3xx-gcu: Fix integer overflow in
 pxa3xx_gcu_write

In pxa3xx_gcu_write, a count parameter of type size_t is passed to words of
type int.  Then, copy_from_user() may cause a heap overflow because it is used
as the third argument of copy_from_user().

Signed-off-by: Hyunwoo Kim <imv4bel@gmail.com>
Signed-off-by: Helge Deller <deller@gmx.de>
---
 drivers/video/fbdev/pxa3xx-gcu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/fbdev/pxa3xx-gcu.c b/drivers/video/fbdev/pxa3xx-gcu.c
index 043cc8f9ef1c7..c3cd1e1cc01b4 100644
--- a/drivers/video/fbdev/pxa3xx-gcu.c
+++ b/drivers/video/fbdev/pxa3xx-gcu.c
@@ -381,7 +381,7 @@ pxa3xx_gcu_write(struct file *file, const char *buff,
 	struct pxa3xx_gcu_batch	*buffer;
 	struct pxa3xx_gcu_priv *priv = to_pxa3xx_gcu_priv(file);
 
-	int words = count / 4;
+	size_t words = count / 4;
 
 	/* Does not need to be atomic. There's a lock in user space,
 	 * but anyhow, this is just for statistics. */
-- 
GitLab


From b5c525abe717f2f41684b8581c13347d50d5285a Mon Sep 17 00:00:00 2001
From: Yihao Han <hanyihao@vivo.com>
Date: Wed, 8 Jun 2022 04:43:25 -0700
Subject: [PATCH 0885/1731] video: fbdev: au1100fb: Drop unnecessary NULL ptr
 check

clk_disable() already checks the clk ptr using IS_ERR_OR_NULL(clk) and
clk_enable() checks the clk ptr using !clk, so there is no need to check clk
ptr again before calling them.

Signed-off-by: Yihao Han <hanyihao@vivo.com>
Signed-off-by: Helge Deller <deller@gmx.de>
---
 drivers/video/fbdev/au1100fb.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/video/fbdev/au1100fb.c b/drivers/video/fbdev/au1100fb.c
index 52f731a614821..519313b8bb004 100644
--- a/drivers/video/fbdev/au1100fb.c
+++ b/drivers/video/fbdev/au1100fb.c
@@ -560,8 +560,7 @@ int au1100fb_drv_suspend(struct platform_device *dev, pm_message_t state)
 	/* Blank the LCD */
 	au1100fb_fb_blank(VESA_POWERDOWN, &fbdev->info);
 
-	if (fbdev->lcdclk)
-		clk_disable(fbdev->lcdclk);
+	clk_disable(fbdev->lcdclk);
 
 	memcpy(&fbregs, fbdev->regs, sizeof(struct au1100fb_regs));
 
@@ -577,8 +576,7 @@ int au1100fb_drv_resume(struct platform_device *dev)
 
 	memcpy(fbdev->regs, &fbregs, sizeof(struct au1100fb_regs));
 
-	if (fbdev->lcdclk)
-		clk_enable(fbdev->lcdclk);
+	clk_enable(fbdev->lcdclk);
 
 	/* Unblank the LCD */
 	au1100fb_fb_blank(VESA_NO_BLANKING, &fbdev->info);
-- 
GitLab


From 5491424d17bdeb7b7852a59367858251783f8398 Mon Sep 17 00:00:00 2001
From: Yihao Han <hanyihao@vivo.com>
Date: Thu, 2 Jun 2022 02:42:18 -0700
Subject: [PATCH 0886/1731] video: fbdev: simplefb: Check before clk_put() not
 needed

clk_put() already checks the clk ptr using !clk and IS_ERR()
so there is no need to check it again before calling it.

Signed-off-by: Yihao Han <hanyihao@vivo.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Helge Deller <deller@gmx.de>
---
 drivers/video/fbdev/simplefb.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/video/fbdev/simplefb.c b/drivers/video/fbdev/simplefb.c
index 2c198561c338f..f96ce8801be49 100644
--- a/drivers/video/fbdev/simplefb.c
+++ b/drivers/video/fbdev/simplefb.c
@@ -237,8 +237,7 @@ static int simplefb_clocks_get(struct simplefb_par *par,
 		if (IS_ERR(clock)) {
 			if (PTR_ERR(clock) == -EPROBE_DEFER) {
 				while (--i >= 0) {
-					if (par->clks[i])
-						clk_put(par->clks[i]);
+					clk_put(par->clks[i]);
 				}
 				kfree(par->clks);
 				return -EPROBE_DEFER;
-- 
GitLab


From 5ccc944dce3df5fd2fd683a7df4fd49d1068eba2 Mon Sep 17 00:00:00 2001
From: "Matthew Wilcox (Oracle)" <willy@infradead.org>
Date: Fri, 10 Jun 2022 14:44:41 -0400
Subject: [PATCH 0887/1731] filemap: Correct the conditions for marking a folio
 as accessed

We had an off-by-one error which meant that we never marked the first page
in a read as accessed.  This was visible as a slowdown when re-reading
a file as pages were being evicted from cache too soon.  In reviewing
this code, we noticed a second bug where a multi-page folio would be
marked as accessed multiple times when doing reads that were less than
the size of the folio.

Abstract the comparison of whether two file positions are in the same
folio into a new function, fixing both of these bugs.

Reported-by: Yu Kuai <yukuai3@huawei.com>
Reviewed-by: Kent Overstreet <kent.overstreet@gmail.com>
Signed-off-by: Matthew Wilcox (Oracle) <willy@infradead.org>
---
 mm/filemap.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/mm/filemap.c b/mm/filemap.c
index ac3775c1ce4cd..5770688684492 100644
--- a/mm/filemap.c
+++ b/mm/filemap.c
@@ -2629,6 +2629,13 @@ err:
 	return err;
 }
 
+static inline bool pos_same_folio(loff_t pos1, loff_t pos2, struct folio *folio)
+{
+	unsigned int shift = folio_shift(folio);
+
+	return (pos1 >> shift == pos2 >> shift);
+}
+
 /**
  * filemap_read - Read data from the page cache.
  * @iocb: The iocb to read.
@@ -2700,11 +2707,11 @@ ssize_t filemap_read(struct kiocb *iocb, struct iov_iter *iter,
 		writably_mapped = mapping_writably_mapped(mapping);
 
 		/*
-		 * When a sequential read accesses a page several times, only
+		 * When a read accesses the same folio several times, only
 		 * mark it as accessed the first time.
 		 */
-		if (iocb->ki_pos >> PAGE_SHIFT !=
-		    ra->prev_pos >> PAGE_SHIFT)
+		if (!pos_same_folio(iocb->ki_pos, ra->prev_pos - 1,
+							fbatch.folios[0]))
 			folio_mark_accessed(fbatch.folios[0]);
 
 		for (i = 0; i < folio_batch_count(&fbatch); i++) {
-- 
GitLab


From cb995f4eeba9d268fd4b56c2423ad6c1d1ea1b82 Mon Sep 17 00:00:00 2001
From: "Matthew Wilcox (Oracle)" <willy@infradead.org>
Date: Fri, 17 Jun 2022 20:00:17 -0400
Subject: [PATCH 0888/1731] filemap: Handle sibling entries in
 filemap_get_read_batch()

If a read races with an invalidation followed by another read, it is
possible for a folio to be replaced with a higher-order folio.  If that
happens, we'll see a sibling entry for the new folio in the next iteration
of the loop.  This manifests as a NULL pointer dereference while holding
the RCU read lock.

Handle this by simply returning.  The next call will find the new folio
and handle it correctly.  The other ways of handling this rare race are
more complex and it's just not worth it.

Reported-by: Dave Chinner <david@fromorbit.com>
Reported-by: Brian Foster <bfoster@redhat.com>
Debugged-by: Brian Foster <bfoster@redhat.com>
Tested-by: Brian Foster <bfoster@redhat.com>
Reviewed-by: Brian Foster <bfoster@redhat.com>
Fixes: cbd59c48ae2b ("mm/filemap: use head pages in generic_file_buffered_read")
Cc: stable@vger.kernel.org
Signed-off-by: Matthew Wilcox (Oracle) <willy@infradead.org>
---
 mm/filemap.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/mm/filemap.c b/mm/filemap.c
index 5770688684492..ffdfbc8b0e3ca 100644
--- a/mm/filemap.c
+++ b/mm/filemap.c
@@ -2385,6 +2385,8 @@ static void filemap_get_read_batch(struct address_space *mapping,
 			continue;
 		if (xas.xa_index > max || xa_is_value(folio))
 			break;
+		if (xa_is_sibling(folio))
+			break;
 		if (!folio_try_get_rcu(folio))
 			goto retry;
 
-- 
GitLab


From 73130a7b1ac92c9f30e0a255951129f4851c5794 Mon Sep 17 00:00:00 2001
From: Steve French <stfrench@microsoft.com>
Date: Sat, 18 Jun 2022 17:24:23 -0500
Subject: [PATCH 0889/1731] smb3: fix empty netname context on secondary
 channels

Some servers do not allow null netname contexts, which would cause
multichannel to revert to single channel when mounting to some
servers (e.g. Azure xSMB).

Fixes: 4c14d7043fede ("cifs: populate empty hostnames for extra channels")
Reviewed-by: Shyam Prasad N <sprasad@microsoft.com>
Reviewed-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/smb2pdu.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/fs/cifs/smb2pdu.c b/fs/cifs/smb2pdu.c
index b515140bad8d2..5e8c4737b183a 100644
--- a/fs/cifs/smb2pdu.c
+++ b/fs/cifs/smb2pdu.c
@@ -570,16 +570,18 @@ assemble_neg_contexts(struct smb2_negotiate_req *req,
 	*total_len += ctxt_len;
 	pneg_ctxt += ctxt_len;
 
-	ctxt_len = build_netname_ctxt((struct smb2_netname_neg_context *)pneg_ctxt,
-					server->hostname);
-	*total_len += ctxt_len;
-	pneg_ctxt += ctxt_len;
-
 	build_posix_ctxt((struct smb2_posix_neg_context *)pneg_ctxt);
 	*total_len += sizeof(struct smb2_posix_neg_context);
 	pneg_ctxt += sizeof(struct smb2_posix_neg_context);
 
-	neg_context_count = 4;
+	if (server->hostname && (server->hostname[0] != 0)) {
+		ctxt_len = build_netname_ctxt((struct smb2_netname_neg_context *)pneg_ctxt,
+					server->hostname);
+		*total_len += ctxt_len;
+		pneg_ctxt += ctxt_len;
+		neg_context_count = 4;
+	} else /* second channels do not have a hostname */
+		neg_context_count = 3;
 
 	if (server->compress_algorithm) {
 		build_compression_ctxt((struct smb2_compression_capabilities_context *)
-- 
GitLab


From 372b2aee97028c75a6e12d205a2e5f0c8626efc6 Mon Sep 17 00:00:00 2001
From: Stephen Boyd <swboyd@chromium.org>
Date: Thu, 2 Jun 2022 12:06:21 -0700
Subject: [PATCH 0890/1731] arm64: dts: qcom: Remove duplicate sc7180-trogdor
 include on lazor/homestar

The sc7180-trogdor-{lazor,homestar}-*.dtsi files all include
sc7180-trogdor.dtsi and sc7180-trogdor-lazor.dtsi or
sc7180-trogdor-homestar.dtsi, so including it here in the
sc7180-trogdor-{lazor,homestar}.dtsi file means we have a duplicate
include after commit 19794489fa24 ("arm64: dts: qcom: Only include
sc7180.dtsi in sc7180-trogdor.dtsi"). We include the sc7180-trogdor.dtsi
file in a board like sc7180-trogdor-lazor-r1.dts so that we can include
the display bridge snippet (e.g. sc7180-trogdor-ti-sn65dsi86.dtsi)
instead of making ever increasing variants like
sc7180-trogdor-lazor-ti-sn65dsi86.dtsi.

Unfortunately, having the double include like this means the display
bridge's i2c bus is left disabled instead of enabled by the bridge
snippet. Any boards that use the i2c bus for the display bridge will
have the bus disabled when we include sc7180-trogdor.dtsi the second
time, which picks up the i2c status="disabled" line from sc7180.dtsi.
This leads to the display not turning on and black screens at boot on
lazor and homestar devices.

Fix this by dropping the include and making a note that the
sc7180-trogdor-{lazor,homestar}.dtsi file must be included after
sc7180-trogdor.dtsi

Reported-by: Douglas Anderson <dianders@chromium.org>
Cc: "Joseph S. Barrera III" <joebar@chromium.org>
Cc: Matthias Kaehlcke <mka@chromium.org>
Fixes: 19794489fa24 ("arm64: dts: qcom: Only include sc7180.dtsi in sc7180-trogdor.dtsi")
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220602190621.1646679-1-swboyd@chromium.org
---
 arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi    | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
index 9b3e3d13c1658..d1e2df5164eaa 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
@@ -5,7 +5,7 @@
  * Copyright 2021 Google LLC.
  */
 
-#include "sc7180-trogdor.dtsi"
+/* This file must be included after sc7180-trogdor.dtsi */
 
 / {
 	/* BOARD-SPECIFIC TOP LEVEL NODES */
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
index fe2369c29aad2..88f6a7d4d0203 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
@@ -5,7 +5,7 @@
  * Copyright 2020 Google LLC.
  */
 
-#include "sc7180-trogdor.dtsi"
+/* This file must be included after sc7180-trogdor.dtsi */
 
 &ap_sar_sensor {
 	semtech,cs0-ground;
-- 
GitLab


From 5d79d8af8dec58bf709b3124d09d9572edd9c617 Mon Sep 17 00:00:00 2001
From: Jie2x Zhou <jie2x.zhou@intel.com>
Date: Thu, 16 Jun 2022 15:40:46 +0800
Subject: [PATCH 0891/1731] selftests: netfilter: correct PKTGEN_SCRIPT_PATHS
 in nft_concat_range.sh

Before change:
make -C netfilter
 TEST: performance
   net,port                                                      [SKIP]
   perf not supported
   port,net                                                      [SKIP]
   perf not supported
   net6,port                                                     [SKIP]
   perf not supported
   port,proto                                                    [SKIP]
   perf not supported
   net6,port,mac                                                 [SKIP]
   perf not supported
   net6,port,mac,proto                                           [SKIP]
   perf not supported
   net,mac                                                       [SKIP]
   perf not supported

After change:
   net,mac                                                       [ OK ]
     baseline (drop from netdev hook):               2061098pps
     baseline hash (non-ranged entries):             1606741pps
     baseline rbtree (match on first field only):    1191607pps
     set with  1000 full, ranged entries:            1639119pps
ok 8 selftests: netfilter: nft_concat_range.sh

Fixes: 611973c1e06f ("selftests: netfilter: Introduce tests for sets with range concatenation")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Jie2x Zhou <jie2x.zhou@intel.com>
Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
---
 tools/testing/selftests/netfilter/nft_concat_range.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/testing/selftests/netfilter/nft_concat_range.sh b/tools/testing/selftests/netfilter/nft_concat_range.sh
index b35010cc7f6ae..a6991877e50cd 100755
--- a/tools/testing/selftests/netfilter/nft_concat_range.sh
+++ b/tools/testing/selftests/netfilter/nft_concat_range.sh
@@ -31,7 +31,7 @@ BUGS="flush_remove_add reload"
 
 # List of possible paths to pktgen script from kernel tree for performance tests
 PKTGEN_SCRIPT_PATHS="
-	../../../samples/pktgen/pktgen_bench_xmit_mode_netif_receive.sh
+	../../../../samples/pktgen/pktgen_bench_xmit_mode_netif_receive.sh
 	pktgen/pktgen_bench_xmit_mode_netif_receive.sh"
 
 # Definition of set types:
-- 
GitLab


From 574a5b85dc3b9ab672ff3fba0ee020f927960648 Mon Sep 17 00:00:00 2001
From: Florian Westphal <fw@strlen.de>
Date: Mon, 20 Jun 2022 16:17:30 +0200
Subject: [PATCH 0892/1731] netfilter: nf_dup_netdev: do not push mac header a
 second time

Eric reports skb_under_panic when using dup/fwd via bond+egress hook.
Before pushing mac header, we should make sure that we're called from
ingress to put back what was pulled earlier.

In egress case, the MAC header is already there; we should leave skb
alone.

While at it be more careful here: skb might have been altered and
headroom reduced, so add a skb_cow() before so that headroom is
increased if necessary.

nf_do_netdev_egress() assumes skb ownership (it normally ends with
a call to dev_queue_xmit), so we must free the packet on error.

Fixes: f87b9464d152 ("netfilter: nft_fwd_netdev: Support egress hook")
Reported-by: Eric Garver <eric@garver.life>
Signed-off-by: Florian Westphal <fw@strlen.de>
Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
---
 net/netfilter/nf_dup_netdev.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/net/netfilter/nf_dup_netdev.c b/net/netfilter/nf_dup_netdev.c
index 7873bd1389c36..13b7f6a660865 100644
--- a/net/netfilter/nf_dup_netdev.c
+++ b/net/netfilter/nf_dup_netdev.c
@@ -13,10 +13,16 @@
 #include <net/netfilter/nf_tables_offload.h>
 #include <net/netfilter/nf_dup_netdev.h>
 
-static void nf_do_netdev_egress(struct sk_buff *skb, struct net_device *dev)
+static void nf_do_netdev_egress(struct sk_buff *skb, struct net_device *dev,
+				enum nf_dev_hooks hook)
 {
-	if (skb_mac_header_was_set(skb))
+	if (hook == NF_NETDEV_INGRESS && skb_mac_header_was_set(skb)) {
+		if (skb_cow_head(skb, skb->mac_len)) {
+			kfree_skb(skb);
+			return;
+		}
 		skb_push(skb, skb->mac_len);
+	}
 
 	skb->dev = dev;
 	skb_clear_tstamp(skb);
@@ -33,7 +39,7 @@ void nf_fwd_netdev_egress(const struct nft_pktinfo *pkt, int oif)
 		return;
 	}
 
-	nf_do_netdev_egress(pkt->skb, dev);
+	nf_do_netdev_egress(pkt->skb, dev, nft_hook(pkt));
 }
 EXPORT_SYMBOL_GPL(nf_fwd_netdev_egress);
 
@@ -48,7 +54,7 @@ void nf_dup_netdev_egress(const struct nft_pktinfo *pkt, int oif)
 
 	skb = skb_clone(pkt->skb, GFP_ATOMIC);
 	if (skb)
-		nf_do_netdev_egress(skb, dev);
+		nf_do_netdev_egress(skb, dev, nft_hook(pkt));
 }
 EXPORT_SYMBOL_GPL(nf_dup_netdev_egress);
 
-- 
GitLab


From fcd53c51d03709bc429822086f1e9b3e88904284 Mon Sep 17 00:00:00 2001
From: Florian Westphal <fw@strlen.de>
Date: Mon, 20 Jun 2022 16:17:31 +0200
Subject: [PATCH 0893/1731] netfilter: nf_dup_netdev: add and use recursion
 counter

Now that the egress function can be called from egress hook, we need
to avoid recursive calls into the nf_tables traverser, else crash.

Fixes: f87b9464d152 ("netfilter: nft_fwd_netdev: Support egress hook")
Signed-off-by: Florian Westphal <fw@strlen.de>
Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
---
 net/netfilter/nf_dup_netdev.c | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/net/netfilter/nf_dup_netdev.c b/net/netfilter/nf_dup_netdev.c
index 13b7f6a660865..a8e2425e43b0d 100644
--- a/net/netfilter/nf_dup_netdev.c
+++ b/net/netfilter/nf_dup_netdev.c
@@ -13,20 +13,31 @@
 #include <net/netfilter/nf_tables_offload.h>
 #include <net/netfilter/nf_dup_netdev.h>
 
+#define NF_RECURSION_LIMIT	2
+
+static DEFINE_PER_CPU(u8, nf_dup_skb_recursion);
+
 static void nf_do_netdev_egress(struct sk_buff *skb, struct net_device *dev,
 				enum nf_dev_hooks hook)
 {
+	if (__this_cpu_read(nf_dup_skb_recursion) > NF_RECURSION_LIMIT)
+		goto err;
+
 	if (hook == NF_NETDEV_INGRESS && skb_mac_header_was_set(skb)) {
-		if (skb_cow_head(skb, skb->mac_len)) {
-			kfree_skb(skb);
-			return;
-		}
+		if (skb_cow_head(skb, skb->mac_len))
+			goto err;
+
 		skb_push(skb, skb->mac_len);
 	}
 
 	skb->dev = dev;
 	skb_clear_tstamp(skb);
+	__this_cpu_inc(nf_dup_skb_recursion);
 	dev_queue_xmit(skb);
+	__this_cpu_dec(nf_dup_skb_recursion);
+	return;
+err:
+	kfree_skb(skb);
 }
 
 void nf_fwd_netdev_egress(const struct nft_pktinfo *pkt, int oif)
-- 
GitLab


From dbab764ed5e987306480f827775876b99b81429e Mon Sep 17 00:00:00 2001
From: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Date: Mon, 13 Jun 2022 14:46:47 +0200
Subject: [PATCH 0894/1731] MAINTAINERS: add include/dt-bindings/usb to USB
 SUBSYSTEM

Maintainers of the directory Documentation/devicetree/bindings/usb
are also the maintainers of the corresponding directory
include/dt-bindings/usb.

Add the file entry for include/dt-bindings/usb to the appropriate
section in MAINTAINERS.

Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Link: https://lore.kernel.org/r/20220613124647.32019-1-lukas.bulwahn@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 3cf9842d9233c..f6c2182e7c389 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20714,6 +20714,7 @@ T:	git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git
 F:	Documentation/devicetree/bindings/usb/
 F:	Documentation/usb/
 F:	drivers/usb/
+F:	include/dt-bindings/usb/
 F:	include/linux/usb.h
 F:	include/linux/usb/
 
-- 
GitLab


From f2d8c2606825317b77db1f9ba0fc26ef26160b30 Mon Sep 17 00:00:00 2001
From: Alan Stern <stern@rowland.harvard.edu>
Date: Mon, 13 Jun 2022 10:17:03 -0400
Subject: [PATCH 0895/1731] usb: gadget: Fix non-unique driver names in
 raw-gadget driver

In a report for a separate bug (which has already been fixed by commit
5f0b5f4d50fa "usb: gadget: fix race when gadget driver register via
ioctl") in the raw-gadget driver, the syzbot console log included
error messages caused by attempted registration of a new driver with
the same name as an existing driver:

> kobject_add_internal failed for raw-gadget with -EEXIST, don't try to register things with the same name in the same directory.
> UDC core: USB Raw Gadget: driver registration failed: -17
> misc raw-gadget: fail, usb_gadget_register_driver returned -17

These errors arise because raw_gadget.c registers a separate UDC
driver for each of the UDC instances it creates, but these drivers all
have the same name: "raw-gadget".  Until recently this wasn't a
problem, but when the "gadget" bus was added and UDC drivers were
registered on this bus, it became possible for name conflicts to cause
the registrations to fail.  The reason is simply that the bus code in
the driver core uses the driver name as a sysfs directory name (e.g.,
/sys/bus/gadget/drivers/raw-gadget/), and you can't create two
directories with the same pathname.

To fix this problem, the driver names used by raw-gadget are made
distinct by appending a unique ID number: "raw-gadget.N", with a
different value of N for each driver instance.  And to avoid the
proliferation of error handling code in the raw_ioctl_init() routine,
the error return paths are refactored into the common pattern (goto
statements leading to cleanup code at the end of the routine).

Link: https://lore.kernel.org/all/0000000000008c664105dffae2eb@google.com/
Fixes: fc274c1e9973 "USB: gadget: Add a new bus for gadgets"
CC: Andrey Konovalov <andreyknvl@gmail.com>
CC: <stable@vger.kernel.org>
Reported-and-tested-by: syzbot+02b16343704b3af1667e@syzkaller.appspotmail.com
Reviewed-by: Andrey Konovalov <andreyknvl@gmail.com>
Acked-by: Hillf Danton <hdanton@sina.com>
Signed-off-by: Alan Stern <stern@rowland.harvard.edu>
Link: https://lore.kernel.org/r/YqdG32w+3h8c1s7z@rowland.harvard.edu
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/gadget/legacy/raw_gadget.c | 62 +++++++++++++++++++-------
 1 file changed, 46 insertions(+), 16 deletions(-)

diff --git a/drivers/usb/gadget/legacy/raw_gadget.c b/drivers/usb/gadget/legacy/raw_gadget.c
index 241740024c50b..5c8481cef35ff 100644
--- a/drivers/usb/gadget/legacy/raw_gadget.c
+++ b/drivers/usb/gadget/legacy/raw_gadget.c
@@ -11,6 +11,7 @@
 #include <linux/ctype.h>
 #include <linux/debugfs.h>
 #include <linux/delay.h>
+#include <linux/idr.h>
 #include <linux/kref.h>
 #include <linux/miscdevice.h>
 #include <linux/module.h>
@@ -36,6 +37,9 @@ MODULE_LICENSE("GPL");
 
 /*----------------------------------------------------------------------*/
 
+static DEFINE_IDA(driver_id_numbers);
+#define DRIVER_DRIVER_NAME_LENGTH_MAX	32
+
 #define RAW_EVENT_QUEUE_SIZE	16
 
 struct raw_event_queue {
@@ -161,6 +165,9 @@ struct raw_dev {
 	/* Reference to misc device: */
 	struct device			*dev;
 
+	/* Make driver names unique */
+	int				driver_id_number;
+
 	/* Protected by lock: */
 	enum dev_state			state;
 	bool				gadget_registered;
@@ -189,6 +196,7 @@ static struct raw_dev *dev_new(void)
 	spin_lock_init(&dev->lock);
 	init_completion(&dev->ep0_done);
 	raw_event_queue_init(&dev->queue);
+	dev->driver_id_number = -1;
 	return dev;
 }
 
@@ -199,6 +207,9 @@ static void dev_free(struct kref *kref)
 
 	kfree(dev->udc_name);
 	kfree(dev->driver.udc_name);
+	kfree(dev->driver.driver.name);
+	if (dev->driver_id_number >= 0)
+		ida_free(&driver_id_numbers, dev->driver_id_number);
 	if (dev->req) {
 		if (dev->ep0_urb_queued)
 			usb_ep_dequeue(dev->gadget->ep0, dev->req);
@@ -422,6 +433,7 @@ static int raw_ioctl_init(struct raw_dev *dev, unsigned long value)
 	struct usb_raw_init arg;
 	char *udc_driver_name;
 	char *udc_device_name;
+	char *driver_driver_name;
 	unsigned long flags;
 
 	if (copy_from_user(&arg, (void __user *)value, sizeof(arg)))
@@ -440,36 +452,44 @@ static int raw_ioctl_init(struct raw_dev *dev, unsigned long value)
 		return -EINVAL;
 	}
 
+	ret = ida_alloc(&driver_id_numbers, GFP_KERNEL);
+	if (ret < 0)
+		return ret;
+	dev->driver_id_number = ret;
+
+	driver_driver_name = kmalloc(DRIVER_DRIVER_NAME_LENGTH_MAX, GFP_KERNEL);
+	if (!driver_driver_name) {
+		ret = -ENOMEM;
+		goto out_free_driver_id_number;
+	}
+	snprintf(driver_driver_name, DRIVER_DRIVER_NAME_LENGTH_MAX,
+				DRIVER_NAME ".%d", dev->driver_id_number);
+
 	udc_driver_name = kmalloc(UDC_NAME_LENGTH_MAX, GFP_KERNEL);
-	if (!udc_driver_name)
-		return -ENOMEM;
+	if (!udc_driver_name) {
+		ret = -ENOMEM;
+		goto out_free_driver_driver_name;
+	}
 	ret = strscpy(udc_driver_name, &arg.driver_name[0],
 				UDC_NAME_LENGTH_MAX);
-	if (ret < 0) {
-		kfree(udc_driver_name);
-		return ret;
-	}
+	if (ret < 0)
+		goto out_free_udc_driver_name;
 	ret = 0;
 
 	udc_device_name = kmalloc(UDC_NAME_LENGTH_MAX, GFP_KERNEL);
 	if (!udc_device_name) {
-		kfree(udc_driver_name);
-		return -ENOMEM;
+		ret = -ENOMEM;
+		goto out_free_udc_driver_name;
 	}
 	ret = strscpy(udc_device_name, &arg.device_name[0],
 				UDC_NAME_LENGTH_MAX);
-	if (ret < 0) {
-		kfree(udc_driver_name);
-		kfree(udc_device_name);
-		return ret;
-	}
+	if (ret < 0)
+		goto out_free_udc_device_name;
 	ret = 0;
 
 	spin_lock_irqsave(&dev->lock, flags);
 	if (dev->state != STATE_DEV_OPENED) {
 		dev_dbg(dev->dev, "fail, device is not opened\n");
-		kfree(udc_driver_name);
-		kfree(udc_device_name);
 		ret = -EINVAL;
 		goto out_unlock;
 	}
@@ -484,14 +504,24 @@ static int raw_ioctl_init(struct raw_dev *dev, unsigned long value)
 	dev->driver.suspend = gadget_suspend;
 	dev->driver.resume = gadget_resume;
 	dev->driver.reset = gadget_reset;
-	dev->driver.driver.name = DRIVER_NAME;
+	dev->driver.driver.name = driver_driver_name;
 	dev->driver.udc_name = udc_device_name;
 	dev->driver.match_existing_only = 1;
 
 	dev->state = STATE_DEV_INITIALIZED;
+	spin_unlock_irqrestore(&dev->lock, flags);
+	return ret;
 
 out_unlock:
 	spin_unlock_irqrestore(&dev->lock, flags);
+out_free_udc_device_name:
+	kfree(udc_device_name);
+out_free_udc_driver_name:
+	kfree(udc_driver_name);
+out_free_driver_driver_name:
+	kfree(driver_driver_name);
+out_free_driver_id_number:
+	ida_free(&driver_id_numbers, dev->driver_id_number);
 	return ret;
 }
 
-- 
GitLab


From 36a38c53b4ee51b90566f8f44a613601eb31a10e Mon Sep 17 00:00:00 2001
From: Takashi Iwai <tiwai@suse.de>
Date: Tue, 21 Jun 2022 14:00:44 +0200
Subject: [PATCH 0896/1731] ALSA: hda: Fix discovery of i915 graphics PCI
 device

It's been reported that the recent fix for skipping the
component-binding with D-GPU caused a regression on some systems; it
resulted in the completely missing component binding with i915 GPU.

The problem was the use of pci_get_class() function.  It matches with
the full PCI class bits, while we want to match only partially the PCI
base class bits.  So, when a system has an i915 graphics device with
the PCI class 0380, it won't hit because we're looking for only the
PCI class 0300.

This patch fixes i915_gfx_present() to look up each PCI device and
match with PCI base class explicitly instead of pci_get_class().

Fixes: c9db8a30d9f0 ("ALSA: hda/i915 - skip acomp init if no matching display")
Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Tested-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Cc: <stable@vger.kernel.org>
Link: https://bugzilla.opensuse.org/show_bug.cgi?id=1200611
Link: https://lore.kernel.org/r/87bkunztec.wl-tiwai@suse.de
Link: https://lore.kernel.org/r/20220621120044.11573-1-tiwai@suse.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/hda/hdac_i915.c | 15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/sound/hda/hdac_i915.c b/sound/hda/hdac_i915.c
index 3f35972e1cf75..161a9711cd63e 100644
--- a/sound/hda/hdac_i915.c
+++ b/sound/hda/hdac_i915.c
@@ -119,21 +119,18 @@ static int i915_component_master_match(struct device *dev, int subcomponent,
 /* check whether Intel graphics is present and reachable */
 static int i915_gfx_present(struct pci_dev *hdac_pci)
 {
-	unsigned int class = PCI_BASE_CLASS_DISPLAY << 16;
 	struct pci_dev *display_dev = NULL;
-	bool match = false;
 
-	do {
-		display_dev = pci_get_class(class, display_dev);
-
-		if (display_dev && display_dev->vendor == PCI_VENDOR_ID_INTEL &&
+	for_each_pci_dev(display_dev) {
+		if (display_dev->vendor == PCI_VENDOR_ID_INTEL &&
+		    (display_dev->class >> 16) == PCI_BASE_CLASS_DISPLAY &&
 		    connectivity_check(display_dev, hdac_pci)) {
 			pci_dev_put(display_dev);
-			match = true;
+			return true;
 		}
-	} while (!match && display_dev);
+	}
 
-	return match;
+	return false;
 }
 
 /**
-- 
GitLab


From d4597898ba7b9d467b94a9aafd65ec408a75041f Mon Sep 17 00:00:00 2001
From: Filipe Manana <fdmanana@suse.com>
Date: Mon, 6 Jun 2022 10:41:17 +0100
Subject: [PATCH 0897/1731] btrfs: fix race between reflinking and ordered
 extent completion

While doing a reflink operation, if an ordered extent for a file range
that does not overlap with the source and destination ranges of the
reflink operation happens, we can end up having a failure in the reflink
operation and return -EINVAL to user space.

The following sequence of steps explains how this can happen:

1) We have the page at file offset 315392 dirty (under delalloc);

2) A reflink operation for this file starts, using the same file as both
   source and destination, the source range is [372736, 409600) (length of
   36864 bytes) and the destination range is [208896, 245760);

3) At btrfs_remap_file_range_prep(), we flush all delalloc in the source
   and destination ranges, and wait for any ordered extents in those range
   to complete;

4) Still at btrfs_remap_file_range_prep(), we then flush all delalloc in
   the inode, but we neither wait for it to complete nor any ordered
   extents to complete. This results in starting delalloc for the page at
   file offset 315392 and creating an ordered extent for that single page
   range;

5) We then move to btrfs_clone() and enter the loop to find file extent
   items to copy from the source range to destination range;

6) In the first iteration we end up at last file extent item stored in
   leaf A:

   (...)
   item 131 key (143616 108 315392) itemoff 5101 itemsize 53
            extent data disk bytenr 1903988736 nr 73728
            extent data offset 12288 nr 61440 ram 73728

   This represents the file range [315392, 376832), which overlaps with
   the source range to clone.

   @datal is set to 61440, key.offset is 315392 and @next_key_min_offset
   is therefore set to 376832 (315392 + 61440).

   @off (372736) is > key.offset (315392), so @new_key.offset is set to
   the value of @destoff (208896).

   @new_key.offset == @last_dest_end (208896) so @drop_start is set to
   208896 (@new_key.offset).

   @datal is adjusted to 4096, as @off is > @key.offset.

   So in this iteration we call btrfs_replace_file_extents() for the range
   [208896, 212991] (a single page, which is
   [@drop_start, @new_key.offset + @datal - 1]).

   @last_dest_end is set to 212992 (@new_key.offset + @datal =
   208896 + 4096 = 212992).

   Before the next iteration of the loop, @key.offset is set to the value
   376832, which is @next_key_min_offset;

7) On the second iteration btrfs_search_slot() leaves us again at leaf A,
   but this time pointing beyond the last slot of leaf A, as that's where
   a key with offset 376832 should be at if it existed. So end up calling
   btrfs_next_leaf();

8) btrfs_next_leaf() releases the path, but before it searches again the
   tree for the next key/leaf, the ordered extent for the single page
   range at file offset 315392 completes. That results in trimming the
   file extent item we processed before, adjusting its key offset from
   315392 to 319488, reducing its length from 61440 to 57344 and inserting
   a new file extent item for that single page range, with a key offset of
   315392 and a length of 4096.

   Leaf A now looks like:

     (...)
     item 132 key (143616 108 315392) itemoff 4995 itemsize 53
              extent data disk bytenr 1801666560 nr 4096
              extent data offset 0 nr 4096 ram 4096
     item 133 key (143616 108 319488) itemoff 4942 itemsize 53
              extent data disk bytenr 1903988736 nr 73728
              extent data offset 16384 nr 57344 ram 73728

9) When btrfs_next_leaf() returns, it gives us a path pointing to leaf A
   at slot 133, since it's the first key that follows what was the last
   key we saw (143616 108 315392). In fact it's the same item we processed
   before, but its key offset was changed, so it counts as a new key;

10) So now we have:

    @key.offset == 319488
    @datal == 57344

    @off (372736) is > key.offset (319488), so @new_key.offset is set to
    208896 (@destoff value).

    @new_key.offset (208896) != @last_dest_end (212992), so @drop_start
    is set to 212992 (@last_dest_end value).

    @datal is adjusted to 4096 because @off > @key.offset.

    So in this iteration we call btrfs_replace_file_extents() for the
    invalid range of [212992, 212991] (which is
    [@drop_start, @new_key.offset + @datal - 1]).

    This range is empty, the end offset is smaller than the start offset
    so btrfs_replace_file_extents() returns -EINVAL, which we end up
    returning to user space and fail the reflink operation.

    This all happens because the range of this file extent item was
    already processed in the previous iteration.

This scenario can be triggered very sporadically by fsx from fstests, for
example with test case generic/522.

So fix this by having btrfs_clone() skip file extent items that cover a
file range that we have already processed.

CC: stable@vger.kernel.org # 5.10+
Reviewed-by: Boris Burkov <boris@bur.io>
Signed-off-by: Filipe Manana <fdmanana@suse.com>
Signed-off-by: David Sterba <dsterba@suse.com>
---
 fs/btrfs/reflink.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/fs/btrfs/reflink.c b/fs/btrfs/reflink.c
index c39f8b3a5a4a4..912f4aa21a247 100644
--- a/fs/btrfs/reflink.c
+++ b/fs/btrfs/reflink.c
@@ -344,6 +344,7 @@ static int btrfs_clone(struct inode *src, struct inode *inode,
 	int ret;
 	const u64 len = olen_aligned;
 	u64 last_dest_end = destoff;
+	u64 prev_extent_end = off;
 
 	ret = -ENOMEM;
 	buf = kvmalloc(fs_info->nodesize, GFP_KERNEL);
@@ -363,7 +364,6 @@ static int btrfs_clone(struct inode *src, struct inode *inode,
 	key.offset = off;
 
 	while (1) {
-		u64 next_key_min_offset = key.offset + 1;
 		struct btrfs_file_extent_item *extent;
 		u64 extent_gen;
 		int type;
@@ -431,14 +431,21 @@ process_slot:
 		 * The first search might have left us at an extent item that
 		 * ends before our target range's start, can happen if we have
 		 * holes and NO_HOLES feature enabled.
+		 *
+		 * Subsequent searches may leave us on a file range we have
+		 * processed before - this happens due to a race with ordered
+		 * extent completion for a file range that is outside our source
+		 * range, but that range was part of a file extent item that
+		 * also covered a leading part of our source range.
 		 */
-		if (key.offset + datal <= off) {
+		if (key.offset + datal <= prev_extent_end) {
 			path->slots[0]++;
 			goto process_slot;
 		} else if (key.offset >= off + len) {
 			break;
 		}
-		next_key_min_offset = key.offset + datal;
+
+		prev_extent_end = key.offset + datal;
 		size = btrfs_item_size(leaf, slot);
 		read_extent_buffer(leaf, buf, btrfs_item_ptr_offset(leaf, slot),
 				   size);
@@ -550,7 +557,7 @@ process_slot:
 			break;
 
 		btrfs_release_path(path);
-		key.offset = next_key_min_offset;
+		key.offset = prev_extent_end;
 
 		if (fatal_signal_pending(current)) {
 			ret = -EINTR;
-- 
GitLab


From 983d8209c6803345c9958f4cc358d1155f93a099 Mon Sep 17 00:00:00 2001
From: Filipe Manana <fdmanana@suse.com>
Date: Mon, 6 Jun 2022 10:41:18 +0100
Subject: [PATCH 0898/1731] btrfs: add missing inode updates on each iteration
 when replacing extents

When replacing file extents, called during fallocate, hole punching,
clone and deduplication, we may not be able to replace/drop all the
target file extent items with a single transaction handle. We may get
-ENOSPC while doing it, in which case we release the transaction handle,
balance the dirty pages of the btree inode, flush delayed items and get
a new transaction handle to operate on what's left of the target range.

By dropping and replacing file extent items we have effectively modified
the inode, so we should bump its iversion and update its mtime/ctime
before we update the inode item. This is because if the transaction
we used for partially modifying the inode gets committed by someone after
we release it and before we finish the rest of the range, a power failure
happens, then after mounting the filesystem our inode has an outdated
iversion and mtime/ctime, corresponding to the values it had before we
changed it.

So add the missing iversion and mtime/ctime updates.

Reviewed-by: Boris Burkov <boris@bur.io>
Signed-off-by: Filipe Manana <fdmanana@suse.com>
Signed-off-by: David Sterba <dsterba@suse.com>
---
 fs/btrfs/ctree.h   |  2 ++
 fs/btrfs/file.c    | 19 +++++++++++++++++++
 fs/btrfs/inode.c   |  1 +
 fs/btrfs/reflink.c |  1 +
 4 files changed, 23 insertions(+)

diff --git a/fs/btrfs/ctree.h b/fs/btrfs/ctree.h
index 0e49b1a0c0716..415bf1823fb3a 100644
--- a/fs/btrfs/ctree.h
+++ b/fs/btrfs/ctree.h
@@ -1330,6 +1330,8 @@ struct btrfs_replace_extent_info {
 	 * existing extent into a file range.
 	 */
 	bool is_new_extent;
+	/* Indicate if we should update the inode's mtime and ctime. */
+	bool update_times;
 	/* Meaningful only if is_new_extent is true. */
 	int qgroup_reserved;
 	/*
diff --git a/fs/btrfs/file.c b/fs/btrfs/file.c
index 46c2baa8fdf54..8e7fb3e6f79c2 100644
--- a/fs/btrfs/file.c
+++ b/fs/btrfs/file.c
@@ -2802,6 +2802,25 @@ int btrfs_replace_file_extents(struct btrfs_inode *inode,
 			extent_info->file_offset += replace_len;
 		}
 
+		/*
+		 * We are releasing our handle on the transaction, balance the
+		 * dirty pages of the btree inode and flush delayed items, and
+		 * then get a new transaction handle, which may now point to a
+		 * new transaction in case someone else may have committed the
+		 * transaction we used to replace/drop file extent items. So
+		 * bump the inode's iversion and update mtime and ctime except
+		 * if we are called from a dedupe context. This is because a
+		 * power failure/crash may happen after the transaction is
+		 * committed and before we finish replacing/dropping all the
+		 * file extent items we need.
+		 */
+		inode_inc_iversion(&inode->vfs_inode);
+
+		if (!extent_info || extent_info->update_times) {
+			inode->vfs_inode.i_mtime = current_time(&inode->vfs_inode);
+			inode->vfs_inode.i_ctime = inode->vfs_inode.i_mtime;
+		}
+
 		ret = btrfs_update_inode(trans, root, inode);
 		if (ret)
 			break;
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index da13bd0d10f12..a642d34c13634 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -9897,6 +9897,7 @@ static struct btrfs_trans_handle *insert_prealloc_file_extent(
 	extent_info.file_offset = file_offset;
 	extent_info.extent_buf = (char *)&stack_fi;
 	extent_info.is_new_extent = true;
+	extent_info.update_times = true;
 	extent_info.qgroup_reserved = qgroup_released;
 	extent_info.insertions = 0;
 
diff --git a/fs/btrfs/reflink.c b/fs/btrfs/reflink.c
index 912f4aa21a247..a3549d587464a 100644
--- a/fs/btrfs/reflink.c
+++ b/fs/btrfs/reflink.c
@@ -496,6 +496,7 @@ process_slot:
 			clone_info.file_offset = new_key.offset;
 			clone_info.extent_buf = buf;
 			clone_info.is_new_extent = false;
+			clone_info.update_times = !no_time_update;
 			ret = btrfs_replace_file_extents(BTRFS_I(inode), path,
 					drop_start, new_key.offset + datal - 1,
 					&clone_info, &trans);
-- 
GitLab


From 650c9caba32a0167a018cca0fab32a2965d23513 Mon Sep 17 00:00:00 2001
From: Filipe Manana <fdmanana@suse.com>
Date: Mon, 6 Jun 2022 10:41:19 +0100
Subject: [PATCH 0899/1731] btrfs: do not BUG_ON() on failure to migrate space
 when replacing extents

At btrfs_replace_file_extents(), if we fail to migrate reserved metadata
space from the transaction block reserve into the local block reserve,
we trigger a BUG_ON(). This is because it should not be possible to have
a failure here, as we reserved more space when we started the transaction
than the space we want to migrate. However having a BUG_ON() is way too
drastic, we can perfectly handle the failure and return the error to the
caller. So just do that instead, and add a WARN_ON() to make it easier
to notice the failure if it ever happens (which is particularly useful
for fstests, and the warning will trigger a failure of a test case).

Reviewed-by: Boris Burkov <boris@bur.io>
Signed-off-by: Filipe Manana <fdmanana@suse.com>
Signed-off-by: David Sterba <dsterba@suse.com>
---
 fs/btrfs/file.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/fs/btrfs/file.c b/fs/btrfs/file.c
index 8e7fb3e6f79c2..dd30639ecac23 100644
--- a/fs/btrfs/file.c
+++ b/fs/btrfs/file.c
@@ -2718,7 +2718,8 @@ int btrfs_replace_file_extents(struct btrfs_inode *inode,
 
 	ret = btrfs_block_rsv_migrate(&fs_info->trans_block_rsv, rsv,
 				      min_size, false);
-	BUG_ON(ret);
+	if (WARN_ON(ret))
+		goto out_trans;
 	trans->block_rsv = rsv;
 
 	cur_offset = start;
@@ -2837,7 +2838,8 @@ int btrfs_replace_file_extents(struct btrfs_inode *inode,
 
 		ret = btrfs_block_rsv_migrate(&fs_info->trans_block_rsv,
 					      rsv, min_size, false);
-		BUG_ON(ret);	/* shouldn't happen */
+		if (WARN_ON(ret))
+			break;
 		trans->block_rsv = rsv;
 
 		cur_offset = drop_args.drop_end;
-- 
GitLab


From 343d8a30851c48a4ef0f5ef61d5e9fbd847a6883 Mon Sep 17 00:00:00 2001
From: Naohiro Aota <naohiro.aota@wdc.com>
Date: Tue, 7 Jun 2022 16:08:29 +0900
Subject: [PATCH 0900/1731] btrfs: zoned: prevent allocation from previous data
 relocation BG

After commit 5f0addf7b890 ("btrfs: zoned: use dedicated lock for data
relocation"), we observe IO errors on e.g, btrfs/232 like below.

  [09.0][T4038707] WARNING: CPU: 3 PID: 4038707 at fs/btrfs/extent-tree.c:2381 btrfs_cross_ref_exist+0xfc/0x120 [btrfs]
  <snip>
  [09.9][T4038707] Call Trace:
  [09.5][T4038707]  <TASK>
  [09.3][T4038707]  run_delalloc_nocow+0x7f1/0x11a0 [btrfs]
  [09.6][T4038707]  ? test_range_bit+0x174/0x320 [btrfs]
  [09.2][T4038707]  ? fallback_to_cow+0x980/0x980 [btrfs]
  [09.3][T4038707]  ? find_lock_delalloc_range+0x33e/0x3e0 [btrfs]
  [09.5][T4038707]  btrfs_run_delalloc_range+0x445/0x1320 [btrfs]
  [09.2][T4038707]  ? test_range_bit+0x320/0x320 [btrfs]
  [09.4][T4038707]  ? lock_downgrade+0x6a0/0x6a0
  [09.2][T4038707]  ? orc_find.part.0+0x1ed/0x300
  [09.5][T4038707]  ? __module_address.part.0+0x25/0x300
  [09.0][T4038707]  writepage_delalloc+0x159/0x310 [btrfs]
  <snip>
  [09.4][    C3] sd 10:0:1:0: [sde] tag#2620 FAILED Result: hostbyte=DID_OK driverbyte=DRIVER_OK cmd_age=0s
  [09.5][    C3] sd 10:0:1:0: [sde] tag#2620 Sense Key : Illegal Request [current]
  [09.9][    C3] sd 10:0:1:0: [sde] tag#2620 Add. Sense: Unaligned write command
  [09.5][    C3] sd 10:0:1:0: [sde] tag#2620 CDB: Write(16) 8a 00 00 00 00 00 02 f3 63 87 00 00 00 2c 00 00
  [09.4][    C3] critical target error, dev sde, sector 396041272 op 0x1:(WRITE) flags 0x800 phys_seg 3 prio class 0
  [09.9][    C3] BTRFS error (device dm-1): bdev /dev/mapper/dml_102_2 errs: wr 1, rd 0, flush 0, corrupt 0, gen 0

The IO errors occur when we allocate a regular extent in previous data
relocation block group.

On zoned btrfs, we use a dedicated block group to relocate a data
extent. Thus, we allocate relocating data extents (pre-alloc) only from
the dedicated block group and vice versa. Once the free space in the
dedicated block group gets tight, a relocating extent may not fit into
the block group. In that case, we need to switch the dedicated block
group to the next one. Then, the previous one is now freed up for
allocating a regular extent. The BG is already not enough to allocate
the relocating extent, but there is still room to allocate a smaller
extent. Now the problem happens. By allocating a regular extent while
nocow IOs for the relocation is still on-going, we will issue WRITE IOs
(for relocation) and ZONE APPEND IOs (for the regular writes) at the
same time. That mixed IOs confuses the write pointer and arises the
unaligned write errors.

This commit introduces a new bit 'zoned_data_reloc_ongoing' to the
btrfs_block_group. We set this bit before releasing the dedicated block
group, and no extent are allocated from a block group having this bit
set. This bit is similar to setting block_group->ro, but is different from
it by allowing nocow writes to start.

Once all the nocow IO for relocation is done (hooked from
btrfs_finish_ordered_io), we reset the bit to release the block group for
further allocation.

Fixes: c2707a255623 ("btrfs: zoned: add a dedicated data relocation block group")
CC: stable@vger.kernel.org # 5.16+
Signed-off-by: Naohiro Aota <naohiro.aota@wdc.com>
Reviewed-by: David Sterba <dsterba@suse.com>
Signed-off-by: David Sterba <dsterba@suse.com>
---
 fs/btrfs/block-group.h |  1 +
 fs/btrfs/extent-tree.c | 20 ++++++++++++++++++--
 fs/btrfs/inode.c       |  2 ++
 fs/btrfs/zoned.c       | 27 +++++++++++++++++++++++++++
 fs/btrfs/zoned.h       |  5 +++++
 5 files changed, 53 insertions(+), 2 deletions(-)

diff --git a/fs/btrfs/block-group.h b/fs/btrfs/block-group.h
index 3ac668ace50aa..35e0e860cc0bf 100644
--- a/fs/btrfs/block-group.h
+++ b/fs/btrfs/block-group.h
@@ -104,6 +104,7 @@ struct btrfs_block_group {
 	unsigned int relocating_repair:1;
 	unsigned int chunk_item_inserted:1;
 	unsigned int zone_is_active:1;
+	unsigned int zoned_data_reloc_ongoing:1;
 
 	int disk_cache_state;
 
diff --git a/fs/btrfs/extent-tree.c b/fs/btrfs/extent-tree.c
index fb367689d9d20..4515497d8a293 100644
--- a/fs/btrfs/extent-tree.c
+++ b/fs/btrfs/extent-tree.c
@@ -3832,7 +3832,7 @@ static int do_allocation_zoned(struct btrfs_block_group *block_group,
 	       block_group->start == fs_info->data_reloc_bg ||
 	       fs_info->data_reloc_bg == 0);
 
-	if (block_group->ro) {
+	if (block_group->ro || block_group->zoned_data_reloc_ongoing) {
 		ret = 1;
 		goto out;
 	}
@@ -3894,8 +3894,24 @@ static int do_allocation_zoned(struct btrfs_block_group *block_group,
 out:
 	if (ret && ffe_ctl->for_treelog)
 		fs_info->treelog_bg = 0;
-	if (ret && ffe_ctl->for_data_reloc)
+	if (ret && ffe_ctl->for_data_reloc &&
+	    fs_info->data_reloc_bg == block_group->start) {
+		/*
+		 * Do not allow further allocations from this block group.
+		 * Compared to increasing the ->ro, setting the
+		 * ->zoned_data_reloc_ongoing flag still allows nocow
+		 *  writers to come in. See btrfs_inc_nocow_writers().
+		 *
+		 * We need to disable an allocation to avoid an allocation of
+		 * regular (non-relocation data) extent. With mix of relocation
+		 * extents and regular extents, we can dispatch WRITE commands
+		 * (for relocation extents) and ZONE APPEND commands (for
+		 * regular extents) at the same time to the same zone, which
+		 * easily break the write pointer.
+		 */
+		block_group->zoned_data_reloc_ongoing = 1;
 		fs_info->data_reloc_bg = 0;
+	}
 	spin_unlock(&fs_info->relocation_bg_lock);
 	spin_unlock(&fs_info->treelog_bg_lock);
 	spin_unlock(&block_group->lock);
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index a642d34c13634..ba527da617327 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -3195,6 +3195,8 @@ static int btrfs_finish_ordered_io(struct btrfs_ordered_extent *ordered_extent)
 						ordered_extent->file_offset,
 						ordered_extent->file_offset +
 						logical_len);
+		btrfs_zoned_release_data_reloc_bg(fs_info, ordered_extent->disk_bytenr,
+						  ordered_extent->disk_num_bytes);
 	} else {
 		BUG_ON(root == fs_info->tree_root);
 		ret = insert_ordered_extent_file_extent(trans, ordered_extent);
diff --git a/fs/btrfs/zoned.c b/fs/btrfs/zoned.c
index 057babaa3e05c..8aec53528efab 100644
--- a/fs/btrfs/zoned.c
+++ b/fs/btrfs/zoned.c
@@ -2140,3 +2140,30 @@ bool btrfs_zoned_should_reclaim(struct btrfs_fs_info *fs_info)
 	factor = div64_u64(used * 100, total);
 	return factor >= fs_info->bg_reclaim_threshold;
 }
+
+void btrfs_zoned_release_data_reloc_bg(struct btrfs_fs_info *fs_info, u64 logical,
+				       u64 length)
+{
+	struct btrfs_block_group *block_group;
+
+	if (!btrfs_is_zoned(fs_info))
+		return;
+
+	block_group = btrfs_lookup_block_group(fs_info, logical);
+	/* It should be called on a previous data relocation block group. */
+	ASSERT(block_group && (block_group->flags & BTRFS_BLOCK_GROUP_DATA));
+
+	spin_lock(&block_group->lock);
+	if (!block_group->zoned_data_reloc_ongoing)
+		goto out;
+
+	/* All relocation extents are written. */
+	if (block_group->start + block_group->alloc_offset == logical + length) {
+		/* Now, release this block group for further allocations. */
+		block_group->zoned_data_reloc_ongoing = 0;
+	}
+
+out:
+	spin_unlock(&block_group->lock);
+	btrfs_put_block_group(block_group);
+}
diff --git a/fs/btrfs/zoned.h b/fs/btrfs/zoned.h
index bb1a189e11f90..6b2eec99162bf 100644
--- a/fs/btrfs/zoned.h
+++ b/fs/btrfs/zoned.h
@@ -77,6 +77,8 @@ void btrfs_schedule_zone_finish_bg(struct btrfs_block_group *bg,
 void btrfs_clear_data_reloc_bg(struct btrfs_block_group *bg);
 void btrfs_free_zone_cache(struct btrfs_fs_info *fs_info);
 bool btrfs_zoned_should_reclaim(struct btrfs_fs_info *fs_info);
+void btrfs_zoned_release_data_reloc_bg(struct btrfs_fs_info *fs_info, u64 logical,
+				       u64 length);
 #else /* CONFIG_BLK_DEV_ZONED */
 static inline int btrfs_get_dev_zone(struct btrfs_device *device, u64 pos,
 				     struct blk_zone *zone)
@@ -243,6 +245,9 @@ static inline bool btrfs_zoned_should_reclaim(struct btrfs_fs_info *fs_info)
 {
 	return false;
 }
+
+static inline void btrfs_zoned_release_data_reloc_bg(struct btrfs_fs_info *fs_info,
+						     u64 logical, u64 length) { }
 #endif
 
 static inline bool btrfs_dev_is_sequential(struct btrfs_device *device, u64 pos)
-- 
GitLab


From 19ab78ca86981e0e1e73036fb73a508731a7c078 Mon Sep 17 00:00:00 2001
From: Naohiro Aota <naohiro.aota@wdc.com>
Date: Tue, 7 Jun 2022 16:08:30 +0900
Subject: [PATCH 0901/1731] btrfs: zoned: fix critical section of relocation
 inode writeback

We use btrfs_zoned_data_reloc_{lock,unlock} to allow only one process to
write out to the relocation inode. That critical section must include all
the IO submission for the inode. However, flush_write_bio() in
extent_writepages() is out of the critical section, causing an IO
submission outside of the lock. This leads to an out of the order IO
submission and fail the relocation process.

Fix it by extending the critical section.

Fixes: 35156d852762 ("btrfs: zoned: only allow one process to add pages to a relocation inode")
CC: stable@vger.kernel.org # 5.16+
Reviewed-by: Johannes Thumshirn <johannes.thumshirn@wdc.com>
Signed-off-by: Naohiro Aota <naohiro.aota@wdc.com>
Signed-off-by: David Sterba <dsterba@suse.com>
---
 fs/btrfs/extent_io.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/fs/btrfs/extent_io.c b/fs/btrfs/extent_io.c
index 588c7c606a2c6..9c250b8cd548f 100644
--- a/fs/btrfs/extent_io.c
+++ b/fs/btrfs/extent_io.c
@@ -5240,13 +5240,14 @@ int extent_writepages(struct address_space *mapping,
 	 */
 	btrfs_zoned_data_reloc_lock(BTRFS_I(inode));
 	ret = extent_write_cache_pages(mapping, wbc, &epd);
-	btrfs_zoned_data_reloc_unlock(BTRFS_I(inode));
 	ASSERT(ret <= 0);
 	if (ret < 0) {
+		btrfs_zoned_data_reloc_unlock(BTRFS_I(inode));
 		end_write_bio(&epd, ret);
 		return ret;
 	}
 	flush_write_bio(&epd);
+	btrfs_zoned_data_reloc_unlock(BTRFS_I(inode));
 	return ret;
 }
 
-- 
GitLab


From 97e86631bccddfbbe0c13f9a9605cdef11d31296 Mon Sep 17 00:00:00 2001
From: Zygo Blaxell <ce3g8jdj@umail.furryterror.org>
Date: Wed, 8 Jun 2022 22:39:36 -0400
Subject: [PATCH 0902/1731] btrfs: don't set lock_owner when locking extent
 buffer for reading

In 196d59ab9ccc "btrfs: switch extent buffer tree lock to rw_semaphore"
the functions for tree read locking were rewritten, and in the process
the read lock functions started setting eb->lock_owner = current->pid.
Previously lock_owner was only set in tree write lock functions.

Read locks are shared, so they don't have exclusive ownership of the
underlying object, so setting lock_owner to any single value for a
read lock makes no sense.  It's mostly harmless because write locks
and read locks are mutually exclusive, and none of the existing code
in btrfs (btrfs_init_new_buffer and print_eb_refs_lock) cares what
nonsense is written in lock_owner when no writer is holding the lock.

KCSAN does care, and will complain about the data race incessantly.
Remove the assignments in the read lock functions because they're
useless noise.

Fixes: 196d59ab9ccc ("btrfs: switch extent buffer tree lock to rw_semaphore")
CC: stable@vger.kernel.org # 5.15+
Reviewed-by: Nikolay Borisov <nborisov@suse.com>
Reviewed-by: Filipe Manana <fdmanana@suse.com>
Signed-off-by: Zygo Blaxell <ce3g8jdj@umail.furryterror.org>
Signed-off-by: David Sterba <dsterba@suse.com>
---
 fs/btrfs/locking.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/fs/btrfs/locking.c b/fs/btrfs/locking.c
index 313d9d685adb7..33461b4f9c8b5 100644
--- a/fs/btrfs/locking.c
+++ b/fs/btrfs/locking.c
@@ -45,7 +45,6 @@ void __btrfs_tree_read_lock(struct extent_buffer *eb, enum btrfs_lock_nesting ne
 		start_ns = ktime_get_ns();
 
 	down_read_nested(&eb->lock, nest);
-	eb->lock_owner = current->pid;
 	trace_btrfs_tree_read_lock(eb, start_ns);
 }
 
@@ -62,7 +61,6 @@ void btrfs_tree_read_lock(struct extent_buffer *eb)
 int btrfs_try_tree_read_lock(struct extent_buffer *eb)
 {
 	if (down_read_trylock(&eb->lock)) {
-		eb->lock_owner = current->pid;
 		trace_btrfs_try_tree_read_lock(eb);
 		return 1;
 	}
@@ -90,7 +88,6 @@ int btrfs_try_tree_write_lock(struct extent_buffer *eb)
 void btrfs_tree_read_unlock(struct extent_buffer *eb)
 {
 	trace_btrfs_tree_read_unlock(eb);
-	eb->lock_owner = 0;
 	up_read(&eb->lock);
 }
 
-- 
GitLab


From bf7ba8ee759b7b7a34787ddd8dc3f190a3d7fa24 Mon Sep 17 00:00:00 2001
From: Josef Bacik <josef@toxicpanda.com>
Date: Mon, 13 Jun 2022 15:09:49 -0400
Subject: [PATCH 0903/1731] btrfs: fix deadlock with fsync+fiemap+transaction
 commit

We are hitting the following deadlock in production occasionally

Task 1		Task 2		Task 3		Task 4		Task 5
		fsync(A)
		 start trans
						start commit
				falloc(A)
				 lock 5m-10m
				 start trans
				  wait for commit
fiemap(A)
 lock 0-10m
  wait for 5m-10m
   (have 0-5m locked)

		 have btrfs_need_log_full_commit
		  !full_sync
		  wait_ordered_extents
								finish_ordered_io(A)
								lock 0-5m
								DEADLOCK

We have an existing dependency of file extent lock -> transaction.
However in fsync if we tried to do the fast logging, but then had to
fall back to committing the transaction, we will be forced to call
btrfs_wait_ordered_range() to make sure all of our extents are updated.

This creates a dependency of transaction -> file extent lock, because
btrfs_finish_ordered_io() will need to take the file extent lock in
order to run the ordered extents.

Fix this by stopping the transaction if we have to do the full commit
and we attempted to do the fast logging.  Then attach to the transaction
and commit it if we need to.

CC: stable@vger.kernel.org # 5.15+
Reviewed-by: Filipe Manana <fdmanana@suse.com>
Signed-off-by: Josef Bacik <josef@toxicpanda.com>
Signed-off-by: David Sterba <dsterba@suse.com>
---
 fs/btrfs/file.c | 67 ++++++++++++++++++++++++++++++++++++++-----------
 1 file changed, 52 insertions(+), 15 deletions(-)

diff --git a/fs/btrfs/file.c b/fs/btrfs/file.c
index dd30639ecac23..af2f2b71d2df7 100644
--- a/fs/btrfs/file.c
+++ b/fs/btrfs/file.c
@@ -2322,25 +2322,62 @@ int btrfs_sync_file(struct file *file, loff_t start, loff_t end, int datasync)
 	 */
 	btrfs_inode_unlock(inode, BTRFS_ILOCK_MMAP);
 
-	if (ret != BTRFS_NO_LOG_SYNC) {
+	if (ret == BTRFS_NO_LOG_SYNC) {
+		ret = btrfs_end_transaction(trans);
+		goto out;
+	}
+
+	/* We successfully logged the inode, attempt to sync the log. */
+	if (!ret) {
+		ret = btrfs_sync_log(trans, root, &ctx);
 		if (!ret) {
-			ret = btrfs_sync_log(trans, root, &ctx);
-			if (!ret) {
-				ret = btrfs_end_transaction(trans);
-				goto out;
-			}
-		}
-		if (!full_sync) {
-			ret = btrfs_wait_ordered_range(inode, start, len);
-			if (ret) {
-				btrfs_end_transaction(trans);
-				goto out;
-			}
+			ret = btrfs_end_transaction(trans);
+			goto out;
 		}
-		ret = btrfs_commit_transaction(trans);
-	} else {
+	}
+
+	/*
+	 * At this point we need to commit the transaction because we had
+	 * btrfs_need_log_full_commit() or some other error.
+	 *
+	 * If we didn't do a full sync we have to stop the trans handle, wait on
+	 * the ordered extents, start it again and commit the transaction.  If
+	 * we attempt to wait on the ordered extents here we could deadlock with
+	 * something like fallocate() that is holding the extent lock trying to
+	 * start a transaction while some other thread is trying to commit the
+	 * transaction while we (fsync) are currently holding the transaction
+	 * open.
+	 */
+	if (!full_sync) {
 		ret = btrfs_end_transaction(trans);
+		if (ret)
+			goto out;
+		ret = btrfs_wait_ordered_range(inode, start, len);
+		if (ret)
+			goto out;
+
+		/*
+		 * This is safe to use here because we're only interested in
+		 * making sure the transaction that had the ordered extents is
+		 * committed.  We aren't waiting on anything past this point,
+		 * we're purely getting the transaction and committing it.
+		 */
+		trans = btrfs_attach_transaction_barrier(root);
+		if (IS_ERR(trans)) {
+			ret = PTR_ERR(trans);
+
+			/*
+			 * We committed the transaction and there's no currently
+			 * running transaction, this means everything we care
+			 * about made it to disk and we are done.
+			 */
+			if (ret == -ENOENT)
+				ret = 0;
+			goto out;
+		}
 	}
+
+	ret = btrfs_commit_transaction(trans);
 out:
 	ASSERT(list_empty(&ctx.list));
 	err = file_check_and_advance_wb_err(file);
-- 
GitLab


From 037e127452b973f45b34c1e88a1af183e652e657 Mon Sep 17 00:00:00 2001
From: David Sterba <dsterba@suse.com>
Date: Tue, 14 Jun 2022 15:27:48 +0200
Subject: [PATCH 0904/1731] Documentation: update btrfs list of features and
 link to readthedocs.io

The btrfs documentation in kernel is only meant as a starting point, so
update the list of features and add link to btrfs.readthedocs.io page
that is most up-to-date. The wiki is still used but information is
migrated from there.

Signed-off-by: David Sterba <dsterba@suse.com>
---
 Documentation/filesystems/btrfs.rst | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/Documentation/filesystems/btrfs.rst b/Documentation/filesystems/btrfs.rst
index d0904f6028197..992eddb0e11b8 100644
--- a/Documentation/filesystems/btrfs.rst
+++ b/Documentation/filesystems/btrfs.rst
@@ -19,13 +19,23 @@ The main Btrfs features include:
     * Subvolumes (separate internal filesystem roots)
     * Object level mirroring and striping
     * Checksums on data and metadata (multiple algorithms available)
-    * Compression
+    * Compression (multiple algorithms available)
+    * Reflink, deduplication
+    * Scrub (on-line checksum verification)
+    * Hierarchical quota groups (subvolume and snapshot support)
     * Integrated multiple device support, with several raid algorithms
     * Offline filesystem check
-    * Efficient incremental backup and FS mirroring
+    * Efficient incremental backup and FS mirroring (send/receive)
+    * Trim/discard
     * Online filesystem defragmentation
+    * Swapfile support
+    * Zoned mode
+    * Read/write metadata verification
+    * Online resize (shrink, grow)
 
-For more information please refer to the wiki
+For more information please refer to the documentation site or wiki
+
+  https://btrfs.readthedocs.io
 
   https://btrfs.wiki.kernel.org
 
-- 
GitLab


From b60cac14bb3c88cff2a7088d9095b01a80938c41 Mon Sep 17 00:00:00 2001
From: Jens Axboe <axboe@kernel.dk>
Date: Tue, 21 Jun 2022 07:47:13 -0600
Subject: [PATCH 0905/1731] io_uring: fix merge error in checking send/recv
 addr2 flags

With the dropping of the IOPOLL checking in the per-opcode handlers,
we inadvertently left two checks in the recv/recvmsg and send/sendmsg
prep handlers for the same thing, and one of them includes addr2 which
holds the flags for these opcodes.

Fix it up and kill the redundant checks.

Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index 87c65a358678f..05508fe92b9cb 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -6077,8 +6077,6 @@ static int io_sendmsg_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe)
 
 	if (unlikely(sqe->file_index))
 		return -EINVAL;
-	if (unlikely(sqe->addr2 || sqe->file_index))
-		return -EINVAL;
 
 	sr->umsg = u64_to_user_ptr(READ_ONCE(sqe->addr));
 	sr->len = READ_ONCE(sqe->len);
@@ -6315,8 +6313,6 @@ static int io_recvmsg_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe)
 
 	if (unlikely(sqe->file_index))
 		return -EINVAL;
-	if (unlikely(sqe->addr2 || sqe->file_index))
-		return -EINVAL;
 
 	sr->umsg = u64_to_user_ptr(READ_ONCE(sqe->addr));
 	sr->len = READ_ONCE(sqe->len);
-- 
GitLab


From aacf2f9f382c91df73f33317e28a4c34c8038986 Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Tue, 21 Jun 2022 13:25:06 +0100
Subject: [PATCH 0906/1731] io_uring: fix req->apoll_events

apoll_events should be set once in the beginning of poll arming just as
poll->events and not change after. However, currently io_uring resets it
on each __io_poll_execute() for no clear reason. There is also a place
in __io_arm_poll_handler() where we add EPOLLONESHOT to downgrade a
multishot, but forget to do the same thing with ->apoll_events, which is
buggy.

Fixes: 81459350d581e ("io_uring: cache req->apoll->events in req->cflags")
Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
Reviewed-by: Hao Xu <howeyxu@tencent.com>
Link: https://lore.kernel.org/r/0aef40399ba75b1a4d2c2e85e6e8fd93c02fc6e4.1655814213.git.asml.silence@gmail.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index 05508fe92b9cb..dffa85d4dc7a0 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -6950,7 +6950,8 @@ static void io_apoll_task_func(struct io_kiocb *req, bool *locked)
 		io_req_complete_failed(req, ret);
 }
 
-static void __io_poll_execute(struct io_kiocb *req, int mask, __poll_t events)
+static void __io_poll_execute(struct io_kiocb *req, int mask,
+			      __poll_t __maybe_unused events)
 {
 	req->cqe.res = mask;
 	/*
@@ -6959,7 +6960,6 @@ static void __io_poll_execute(struct io_kiocb *req, int mask, __poll_t events)
 	 * CPU. We want to avoid pulling in req->apoll->events for that
 	 * case.
 	 */
-	req->apoll_events = events;
 	if (req->opcode == IORING_OP_POLL_ADD)
 		req->io_task_work.func = io_poll_task_func;
 	else
@@ -7110,6 +7110,8 @@ static int __io_arm_poll_handler(struct io_kiocb *req,
 	io_init_poll_iocb(poll, mask, io_poll_wake);
 	poll->file = req->file;
 
+	req->apoll_events = poll->events;
+
 	ipt->pt._key = mask;
 	ipt->req = req;
 	ipt->error = 0;
@@ -7140,8 +7142,10 @@ static int __io_arm_poll_handler(struct io_kiocb *req,
 
 	if (mask) {
 		/* can't multishot if failed, just queue the event we've got */
-		if (unlikely(ipt->error || !ipt->nr_entries))
+		if (unlikely(ipt->error || !ipt->nr_entries)) {
 			poll->events |= EPOLLONESHOT;
+			req->apoll_events |= EPOLLONESHOT;
+		}
 		__io_poll_execute(req, mask, poll->events);
 		return 0;
 	}
@@ -7388,7 +7392,7 @@ static int io_poll_add_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe
 		return -EINVAL;
 
 	io_req_set_refcount(req);
-	req->apoll_events = poll->events = io_poll_parse_events(sqe, flags);
+	poll->events = io_poll_parse_events(sqe, flags);
 	return 0;
 }
 
-- 
GitLab


From 0f074c1c95ea496dc91279b6c4b9845a337517fa Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Wed, 15 Jun 2022 15:54:02 +0200
Subject: [PATCH 0907/1731] dt-bindings: usb: ohci: Increase the number of PHYs

"make dtbs_check":

    arch/arm/boot/dts/r8a77470-iwg23s-sbc.dtb: usb@ee080000: phys: [[17, 0], [31]] is too long
	    From schema: Documentation/devicetree/bindings/usb/generic-ohci.yaml
    arch/arm/boot/dts/r8a77470-iwg23s-sbc.dtb: usb@ee0c0000: phys: [[17, 1], [33], [21, 0]] is too long
	    From schema: Documentation/devicetree/bindings/usb/generic-ohci.yaml

Some USB OHCI controllers (e.g. on the Renesas RZ/G1C SoC) have multiple
PHYs.  Increase the maximum number of PHYs to 3, which is sufficient for
now.

Fixes: 0499220d6dadafa5 ("dt-bindings: Add missing array size constraints")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/0112f9c8881513cb33bf7b66bc743dd08b35a2f5.1655301203.git.geert+renesas@glider.be
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 Documentation/devicetree/bindings/usb/generic-ohci.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
index e2ac846653161..bb6bbd5f129d4 100644
--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
@@ -103,7 +103,8 @@ properties:
       Overrides the detected port count
 
   phys:
-    maxItems: 1
+    minItems: 1
+    maxItems: 3
 
   phy-names:
     const: usb
-- 
GitLab


From 9faa1c8f92f33daad9db96944139de225cefa199 Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Wed, 15 Jun 2022 15:53:09 +0200
Subject: [PATCH 0908/1731] dt-bindings: usb: ehci: Increase the number of PHYs

"make dtbs_check":

    arch/arm/boot/dts/r8a77470-iwg23s-sbc.dtb: usb@ee080100: phys: [[17, 0], [31]] is too long
	    From schema: Documentation/devicetree/bindings/usb/generic-ehci.yaml
    arch/arm/boot/dts/r8a77470-iwg23s-sbc.dtb: usb@ee0c0100: phys: [[17, 1], [33], [21, 0]] is too long
	    From schema: Documentation/devicetree/bindings/usb/generic-ehci.yaml

Some USB EHCI controllers (e.g. on the Renesas RZ/G1C SoC) have multiple
PHYs.  Increase the maximum number of PHYs to 3, which is sufficient for
now.

Fixes: 0499220d6dadafa5 ("dt-bindings: Add missing array size constraints")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c5d19e2f9714f43effd90208798fc1936098078f.1655301043.git.geert+renesas@glider.be
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 Documentation/devicetree/bindings/usb/generic-ehci.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
index 0b4524b6409ec..1e84e1b7ab271 100644
--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
@@ -136,7 +136,8 @@ properties:
       Phandle of a companion.
 
   phys:
-    maxItems: 1
+    minItems: 1
+    maxItems: 3
 
   phy-names:
     const: usb
-- 
GitLab


From 96163f835e65f8c9897487fac965819f0651d671 Mon Sep 17 00:00:00 2001
From: Dan Vacura <w36195@motorola.com>
Date: Fri, 17 Jun 2022 11:31:53 -0500
Subject: [PATCH 0909/1731] usb: gadget: uvc: fix list double add in
 uvcg_video_pump

A panic can occur if the endpoint becomes disabled and the
uvcg_video_pump adds the request back to the req_free list after it has
already been queued to the endpoint. The endpoint complete will add the
request back to the req_free list. Invalidate the local request handle
once it's been queued.

<6>[  246.796704][T13726] configfs-gadget gadget: uvc: uvc_function_set_alt(1, 0)
<3>[  246.797078][   T26] list_add double add: new=ffffff878bee5c40, prev=ffffff878bee5c40, next=ffffff878b0f0a90.
<6>[  246.797213][   T26] ------------[ cut here ]------------
<2>[  246.797224][   T26] kernel BUG at lib/list_debug.c:31!
<6>[  246.807073][   T26] Call trace:
<6>[  246.807180][   T26]  uvcg_video_pump+0x364/0x38c
<6>[  246.807366][   T26]  process_one_work+0x2a4/0x544
<6>[  246.807394][   T26]  worker_thread+0x350/0x784
<6>[  246.807442][   T26]  kthread+0x2ac/0x320

Fixes: f9897ec0f6d3 ("usb: gadget: uvc: only pump video data if necessary")
Cc: stable@vger.kernel.org
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Dan Vacura <w36195@motorola.com>
Link: https://lore.kernel.org/r/20220617163154.16621-1-w36195@motorola.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/gadget/function/uvc_video.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/usb/gadget/function/uvc_video.c b/drivers/usb/gadget/function/uvc_video.c
index a9bb4553db847..d42bb3346745c 100644
--- a/drivers/usb/gadget/function/uvc_video.c
+++ b/drivers/usb/gadget/function/uvc_video.c
@@ -424,6 +424,9 @@ static void uvcg_video_pump(struct work_struct *work)
 			uvcg_queue_cancel(queue, 0);
 			break;
 		}
+
+		/* Endpoint now owns the request */
+		req = NULL;
 		video->req_int_count++;
 	}
 
-- 
GitLab


From 9ef165406308515dcf2e3f6e97b39a1c56d86db5 Mon Sep 17 00:00:00 2001
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Date: Mon, 20 Jun 2022 13:43:16 +0300
Subject: [PATCH 0910/1731] usb: typec: wcove: Drop wrong dependency to
 INTEL_SOC_PMIC

Intel SoC PMIC is a generic name for all PMICs that are used
on Intel platforms. In particular, INTEL_SOC_PMIC kernel configuration
option refers to Crystal Cove PMIC, which has never been a part
of any Intel Broxton hardware. Drop wrong dependency from Kconfig.

Note, the correct dependency is satisfied via ACPI PMIC OpRegion driver,
which the Type-C depends on.

Fixes: d2061f9cc32d ("usb: typec: add driver for Intel Whiskey Cove PMIC USB Type-C PHY")
Reported-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220620104316.57592-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/typec/tcpm/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/usb/typec/tcpm/Kconfig b/drivers/usb/typec/tcpm/Kconfig
index 557f392fe24da..073fd2ea5e0bb 100644
--- a/drivers/usb/typec/tcpm/Kconfig
+++ b/drivers/usb/typec/tcpm/Kconfig
@@ -56,7 +56,6 @@ config TYPEC_WCOVE
 	tristate "Intel WhiskeyCove PMIC USB Type-C PHY driver"
 	depends on ACPI
 	depends on MFD_INTEL_PMC_BXT
-	depends on INTEL_SOC_PMIC
 	depends on BXT_WC_PMIC_OPREGION
 	help
 	  This driver adds support for USB Type-C on Intel Broxton platforms
-- 
GitLab


From f9710c357e5bbf64d7ce45ba0bc75a52222491c1 Mon Sep 17 00:00:00 2001
From: Jason Andryuk <jandryuk@gmail.com>
Date: Wed, 1 Jun 2022 15:53:41 -0400
Subject: [PATCH 0911/1731] xen-blkfront: Handle NULL gendisk
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When a VBD is not fully created and then closed, the kernel can have a
NULL pointer dereference:

The reproducer is trivial:

[user@dom0 ~]$ sudo xl block-attach work backend=sys-usb vdev=xvdi target=/dev/sdz
[user@dom0 ~]$ xl block-list work
Vdev  BE  handle state evt-ch ring-ref BE-path
51712 0   241    4     -1     -1       /local/domain/0/backend/vbd/241/51712
51728 0   241    4     -1     -1       /local/domain/0/backend/vbd/241/51728
51744 0   241    4     -1     -1       /local/domain/0/backend/vbd/241/51744
51760 0   241    4     -1     -1       /local/domain/0/backend/vbd/241/51760
51840 3   241    3     -1     -1       /local/domain/3/backend/vbd/241/51840
                 ^ note state, the /dev/sdz doesn't exist in the backend

[user@dom0 ~]$ sudo xl block-detach work xvdi
[user@dom0 ~]$ xl block-list work
Vdev  BE  handle state evt-ch ring-ref BE-path
work is an invalid domain identifier

And its console has:

BUG: kernel NULL pointer dereference, address: 0000000000000050
PGD 80000000edebb067 P4D 80000000edebb067 PUD edec2067 PMD 0
Oops: 0000 [#1] PREEMPT SMP PTI
CPU: 1 PID: 52 Comm: xenwatch Not tainted 5.16.18-2.43.fc32.qubes.x86_64 #1
RIP: 0010:blk_mq_stop_hw_queues+0x5/0x40
Code: 00 48 83 e0 fd 83 c3 01 48 89 85 a8 00 00 00 41 39 5c 24 50 77 c0 5b 5d 41 5c 41 5d c3 c3 0f 1f 80 00 00 00 00 0f 1f 44 00 00 <8b> 47 50 85 c0 74 32 41 54 49 89 fc 55 53 31 db 49 8b 44 24 48 48
RSP: 0018:ffffc90000bcfe98 EFLAGS: 00010293
RAX: ffffffffc0008370 RBX: 0000000000000005 RCX: 0000000000000000
RDX: 0000000000000000 RSI: 0000000000000005 RDI: 0000000000000000
RBP: ffff88800775f000 R08: 0000000000000001 R09: ffff888006e620b8
R10: ffff888006e620b0 R11: f000000000000000 R12: ffff8880bff39000
R13: ffff8880bff39000 R14: 0000000000000000 R15: ffff88800604be00
FS:  0000000000000000(0000) GS:ffff8880f3300000(0000) knlGS:0000000000000000
CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 0000000000000050 CR3: 00000000e932e002 CR4: 00000000003706e0
Call Trace:
 <TASK>
 blkback_changed+0x95/0x137 [xen_blkfront]
 ? read_reply+0x160/0x160
 xenwatch_thread+0xc0/0x1a0
 ? do_wait_intr_irq+0xa0/0xa0
 kthread+0x16b/0x190
 ? set_kthread_struct+0x40/0x40
 ret_from_fork+0x22/0x30
 </TASK>
Modules linked in: snd_seq_dummy snd_hrtimer snd_seq snd_seq_device snd_timer snd soundcore ipt_REJECT nf_reject_ipv4 xt_state xt_conntrack nft_counter nft_chain_nat xt_MASQUERADE nf_nat nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 nft_compat nf_tables nfnetlink intel_rapl_msr intel_rapl_common crct10dif_pclmul crc32_pclmul crc32c_intel ghash_clmulni_intel xen_netfront pcspkr xen_scsiback target_core_mod xen_netback xen_privcmd xen_gntdev xen_gntalloc xen_blkback xen_evtchn ipmi_devintf ipmi_msghandler fuse bpf_preload ip_tables overlay xen_blkfront
CR2: 0000000000000050
---[ end trace 7bc9597fd06ae89d ]---
RIP: 0010:blk_mq_stop_hw_queues+0x5/0x40
Code: 00 48 83 e0 fd 83 c3 01 48 89 85 a8 00 00 00 41 39 5c 24 50 77 c0 5b 5d 41 5c 41 5d c3 c3 0f 1f 80 00 00 00 00 0f 1f 44 00 00 <8b> 47 50 85 c0 74 32 41 54 49 89 fc 55 53 31 db 49 8b 44 24 48 48
RSP: 0018:ffffc90000bcfe98 EFLAGS: 00010293
RAX: ffffffffc0008370 RBX: 0000000000000005 RCX: 0000000000000000
RDX: 0000000000000000 RSI: 0000000000000005 RDI: 0000000000000000
RBP: ffff88800775f000 R08: 0000000000000001 R09: ffff888006e620b8
R10: ffff888006e620b0 R11: f000000000000000 R12: ffff8880bff39000
R13: ffff8880bff39000 R14: 0000000000000000 R15: ffff88800604be00
FS:  0000000000000000(0000) GS:ffff8880f3300000(0000) knlGS:0000000000000000
CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 0000000000000050 CR3: 00000000e932e002 CR4: 00000000003706e0
Kernel panic - not syncing: Fatal exception
Kernel Offset: disabled

info->rq and info->gd are only set in blkfront_connect(), which is
called for state 4 (XenbusStateConnected).  Guard against using NULL
variables in blkfront_closing() to avoid the issue.

The rest of blkfront_closing looks okay.  If info->nr_rings is 0, then
for_each_rinfo won't do anything.

blkfront_remove also needs to check for non-NULL pointers before
cleaning up the gendisk and request queue.

Fixes: 05d69d950d9d "xen-blkfront: sanitize the removal state machine"
Reported-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
Signed-off-by: Jason Andryuk <jandryuk@gmail.com>
Reviewed-by: Juergen Gross <jgross@suse.com>
Link: https://lore.kernel.org/r/20220601195341.28581-1-jandryuk@gmail.com
Signed-off-by: Juergen Gross <jgross@suse.com>
---
 drivers/block/xen-blkfront.c | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/block/xen-blkfront.c b/drivers/block/xen-blkfront.c
index a88ce4426400e..33f04ef78984c 100644
--- a/drivers/block/xen-blkfront.c
+++ b/drivers/block/xen-blkfront.c
@@ -2114,9 +2114,11 @@ static void blkfront_closing(struct blkfront_info *info)
 		return;
 
 	/* No more blkif_request(). */
-	blk_mq_stop_hw_queues(info->rq);
-	blk_mark_disk_dead(info->gd);
-	set_capacity(info->gd, 0);
+	if (info->rq && info->gd) {
+		blk_mq_stop_hw_queues(info->rq);
+		blk_mark_disk_dead(info->gd);
+		set_capacity(info->gd, 0);
+	}
 
 	for_each_rinfo(info, rinfo, i) {
 		/* No more gnttab callback work. */
@@ -2457,16 +2459,19 @@ static int blkfront_remove(struct xenbus_device *xbdev)
 
 	dev_dbg(&xbdev->dev, "%s removed", xbdev->nodename);
 
-	del_gendisk(info->gd);
+	if (info->gd)
+		del_gendisk(info->gd);
 
 	mutex_lock(&blkfront_mutex);
 	list_del(&info->info_list);
 	mutex_unlock(&blkfront_mutex);
 
 	blkif_free(info, 0);
-	xlbd_release_minors(info->gd->first_minor, info->gd->minors);
-	blk_cleanup_disk(info->gd);
-	blk_mq_free_tag_set(&info->tag_set);
+	if (info->gd) {
+		xlbd_release_minors(info->gd->first_minor, info->gd->minors);
+		blk_cleanup_disk(info->gd);
+		blk_mq_free_tag_set(&info->tag_set);
+	}
 
 	kfree(info);
 	return 0;
-- 
GitLab


From ecb6237fa397b7b810d798ad19322eca466dbab1 Mon Sep 17 00:00:00 2001
From: Julien Grall <jgrall@amazon.com>
Date: Fri, 17 Jun 2022 11:30:37 +0100
Subject: [PATCH 0912/1731] x86/xen: Remove undefined behavior in
 setup_features()

1 << 31 is undefined. So switch to 1U << 31.

Fixes: 5ead97c84fa7 ("xen: Core Xen implementation")
Signed-off-by: Julien Grall <jgrall@amazon.com>
Reviewed-by: Juergen Gross <jgross@suse.com>
Link: https://lore.kernel.org/r/20220617103037.57828-1-julien@xen.org
Signed-off-by: Juergen Gross <jgross@suse.com>
---
 drivers/xen/features.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/xen/features.c b/drivers/xen/features.c
index 7b591443833c9..87f1828d40d5e 100644
--- a/drivers/xen/features.c
+++ b/drivers/xen/features.c
@@ -42,7 +42,7 @@ void xen_setup_features(void)
 		if (HYPERVISOR_xen_version(XENVER_get_features, &fi) < 0)
 			break;
 		for (j = 0; j < 32; j++)
-			xen_features[i * 32 + j] = !!(fi.submap & 1<<j);
+			xen_features[i * 32 + j] = !!(fi.submap & 1U << j);
 	}
 
 	if (xen_pv_domain()) {
-- 
GitLab


From ca6969013d13282b42cb5edcc13db731a08e0ad8 Mon Sep 17 00:00:00 2001
From: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>
Date: Mon, 9 May 2022 16:51:43 +0300
Subject: [PATCH 0913/1731] drm/xen: Add missing VM_DONTEXPAND flag in mmap
 callback

With Xen PV Display driver in use the "expected" VM_DONTEXPAND flag
is not set (neither explicitly nor implicitly), so the driver hits
the code path in drm_gem_mmap_obj() which triggers the WARNING.

Signed-off-by: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>
Reviewed-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
Link: https://lore.kernel.org/r/1652104303-5098-1-git-send-email-olekstysh@gmail.com
Signed-off-by: Juergen Gross <jgross@suse.com>
---
 drivers/gpu/drm/xen/xen_drm_front_gem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xen/xen_drm_front_gem.c b/drivers/gpu/drm/xen/xen_drm_front_gem.c
index 5a5bf4e5b7171..e31554d7139f1 100644
--- a/drivers/gpu/drm/xen/xen_drm_front_gem.c
+++ b/drivers/gpu/drm/xen/xen_drm_front_gem.c
@@ -71,7 +71,7 @@ static int xen_drm_front_gem_object_mmap(struct drm_gem_object *gem_obj,
 	 * the whole buffer.
 	 */
 	vma->vm_flags &= ~VM_PFNMAP;
-	vma->vm_flags |= VM_MIXEDMAP;
+	vma->vm_flags |= VM_MIXEDMAP | VM_DONTEXPAND;
 	vma->vm_pgoff = 0;
 
 	/*
-- 
GitLab


From c81aba8fde2aee4f5778ebab3a1d51bd2ef48e4c Mon Sep 17 00:00:00 2001
From: huhai <huhai@kylinos.cn>
Date: Fri, 10 Jun 2022 19:14:20 +0800
Subject: [PATCH 0914/1731] MIPS: Remove repetitive increase irq_err_count

commit 979934da9e7a ("[PATCH] mips: update IRQ handling for vr41xx") added
a function irq_dispatch, and it'll increase irq_err_count when the get_irq
callback returns a negative value, but increase irq_err_count in get_irq
was not removed.

And also, modpost complains once gpio-vr41xx drivers become modules.
  ERROR: modpost: "irq_err_count" [drivers/gpio/gpio-vr41xx.ko] undefined!

So it would be a good idea to remove repetitive increase irq_err_count in
get_irq callback.

Fixes: 27fdd325dace ("MIPS: Update VR41xx GPIO driver to use gpiolib")
Fixes: 979934da9e7a ("[PATCH] mips: update IRQ handling for vr41xx")
Reported-by: k2ci <kernel-bot@kylinos.cn>
Signed-off-by: huhai <huhai@kylinos.cn>
Signed-off-by: Genjian Zhang <zhanggenjian@kylinos.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
 arch/mips/vr41xx/common/icu.c | 2 --
 drivers/gpio/gpio-vr41xx.c    | 2 --
 2 files changed, 4 deletions(-)

diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c
index 7b7f25b4b057e..9240bcdbe74e4 100644
--- a/arch/mips/vr41xx/common/icu.c
+++ b/arch/mips/vr41xx/common/icu.c
@@ -640,8 +640,6 @@ static int icu_get_irq(unsigned int irq)
 
 	printk(KERN_ERR "spurious ICU interrupt: %04x,%04x\n", pend1, pend2);
 
-	atomic_inc(&irq_err_count);
-
 	return -1;
 }
 
diff --git a/drivers/gpio/gpio-vr41xx.c b/drivers/gpio/gpio-vr41xx.c
index 98cd715ccc33c..8d09b619c1669 100644
--- a/drivers/gpio/gpio-vr41xx.c
+++ b/drivers/gpio/gpio-vr41xx.c
@@ -217,8 +217,6 @@ static int giu_get_irq(unsigned int irq)
 	printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n",
 	       maskl, pendl, maskh, pendh);
 
-	atomic_inc(&irq_err_count);
-
 	return -EINVAL;
 }
 
-- 
GitLab


From 4becf6417bbdc293734a590fe4ed38437bbcea2c Mon Sep 17 00:00:00 2001
From: Liang He <windhl@126.com>
Date: Wed, 15 Jun 2022 22:11:23 +0800
Subject: [PATCH 0915/1731] arch: mips: generic: Add missing of_node_put() in
 board-ranchu.c

In ranchu_measure_hpt_freq(), of_find_compatible_node() will return
a node pointer with refcount incremented. We should use of_put_node()
when it is not used anymore.

Signed-off-by: Liang He <windhl@126.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
 arch/mips/generic/board-ranchu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/generic/board-ranchu.c b/arch/mips/generic/board-ranchu.c
index a89aaad59cb18..930c450418822 100644
--- a/arch/mips/generic/board-ranchu.c
+++ b/arch/mips/generic/board-ranchu.c
@@ -44,6 +44,7 @@ static __init unsigned int ranchu_measure_hpt_freq(void)
 		      __func__);
 
 	rtc_base = of_iomap(np, 0);
+	of_node_put(np);
 	if (!rtc_base)
 		panic("%s(): Failed to ioremap Goldfish RTC base!", __func__);
 
-- 
GitLab


From 608d94cb84c42585058d692f2fe5d327f8868cdb Mon Sep 17 00:00:00 2001
From: Liang He <windhl@126.com>
Date: Thu, 16 Jun 2022 22:27:56 +0800
Subject: [PATCH 0916/1731] mips: mti-malta: Fix refcount leak in malta-time.c

In update_gic_frequency_dt(), of_find_compatible_node() will return
a node pointer with refcount incremented. We should use of_node_put()
when it is not used anymore.

Signed-off-by: Liang He <windhl@126.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
 arch/mips/mti-malta/malta-time.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index bbf1e38e14319..2cb708cdf01a0 100644
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -214,6 +214,8 @@ static void update_gic_frequency_dt(void)
 
 	if (of_update_property(node, &gic_frequency_prop) < 0)
 		pr_err("error updating gic frequency property\n");
+
+	of_node_put(node);
 }
 
 #endif
-- 
GitLab


From 48ca54e39173d1ed4c4dc8cf045484014bb26eaf Mon Sep 17 00:00:00 2001
From: Liang He <windhl@126.com>
Date: Fri, 17 Jun 2022 11:39:29 +0800
Subject: [PATCH 0917/1731] mips: ralink: Fix refcount leak in of.c

In plat_of_remap_node(), plat_of_remap_node() will return a node
pointer with refcount incremented. We should use of_node_put()
when it is not used anymore.

Signed-off-by: Liang He <windhl@126.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
 arch/mips/ralink/of.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
index 587c7b9987697..ea8072acf8d94 100644
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
@@ -40,6 +40,8 @@ __iomem void *plat_of_remap_node(const char *node)
 	if (of_address_to_resource(np, 0, &res))
 		panic("Failed to get resource for %s", node);
 
+	of_node_put(np);
+
 	if (!request_mem_region(res.start,
 				resource_size(&res),
 				res.name))
-- 
GitLab


From 72a2af539fff975caadd9a4db3f99963569bd9c9 Mon Sep 17 00:00:00 2001
From: Liang He <windhl@126.com>
Date: Fri, 17 Jun 2022 20:19:58 +0800
Subject: [PATCH 0918/1731] mips: lantiq: falcon: Fix refcount leak bug in
 sysctrl

In ltq_soc_init(), of_find_compatible_node() will return a node pointer
with refcount incremented. We should use of_node_put() when it is not
used anymore.

Signed-off-by: Liang He <windhl@126.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
 arch/mips/lantiq/falcon/sysctrl.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
index 5204fc6d6d502..1187729d8cbb1 100644
--- a/arch/mips/lantiq/falcon/sysctrl.c
+++ b/arch/mips/lantiq/falcon/sysctrl.c
@@ -208,6 +208,12 @@ void __init ltq_soc_init(void)
 			of_address_to_resource(np_sysgpe, 0, &res_sys[2]))
 		panic("Failed to get core resources");
 
+	of_node_put(np_status);
+	of_node_put(np_ebu);
+	of_node_put(np_sys1);
+	of_node_put(np_syseth);
+	of_node_put(np_sysgpe);
+
 	if ((request_mem_region(res_status.start, resource_size(&res_status),
 				res_status.name) < 0) ||
 		(request_mem_region(res_ebu.start, resource_size(&res_ebu),
-- 
GitLab


From 76695592711ef1e215cc24ed3e1cd857d7fc3098 Mon Sep 17 00:00:00 2001
From: Liang He <windhl@126.com>
Date: Fri, 17 Jun 2022 20:25:05 +0800
Subject: [PATCH 0919/1731] mips: lantiq: xway: Fix refcount leak bug in
 sysctrl

In ltq_soc_init(), of_find_compatible_node() will return a node
pointer with refcount incremented. We should use of_node_put() when
it is not used anymore.

Signed-off-by: Liang He <windhl@126.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
 arch/mips/lantiq/xway/sysctrl.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 084f6caba5f23..d444a1b98a724 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -441,6 +441,10 @@ void __init ltq_soc_init(void)
 			of_address_to_resource(np_ebu, 0, &res_ebu))
 		panic("Failed to get core resources");
 
+	of_node_put(np_pmu);
+	of_node_put(np_cgu);
+	of_node_put(np_ebu);
+
 	if (!request_mem_region(res_pmu.start, resource_size(&res_pmu),
 				res_pmu.name) ||
 		!request_mem_region(res_cgu.start, resource_size(&res_cgu),
-- 
GitLab


From eb9e9bc4fa5fb489c92ec588b3fb35f042ba6d86 Mon Sep 17 00:00:00 2001
From: Liang He <windhl@126.com>
Date: Sun, 19 Jun 2022 12:54:27 +0800
Subject: [PATCH 0920/1731] mips/pic32/pic32mzda: Fix refcount leak bugs

of_find_matching_node(), of_find_compatible_node() and
of_find_node_by_path() will return node pointers with refcout
incremented. We should call of_node_put() when they are not
used anymore.

Signed-off-by: Liang He <windhl@126.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
 arch/mips/pic32/pic32mzda/init.c | 7 ++++++-
 arch/mips/pic32/pic32mzda/time.c | 3 +++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/mips/pic32/pic32mzda/init.c b/arch/mips/pic32/pic32mzda/init.c
index 129915616763a..d9c8c4e46aff9 100644
--- a/arch/mips/pic32/pic32mzda/init.c
+++ b/arch/mips/pic32/pic32mzda/init.c
@@ -98,13 +98,18 @@ static int __init pic32_of_prepare_platform_data(struct of_dev_auxdata *lookup)
 		np = of_find_compatible_node(NULL, NULL, lookup->compatible);
 		if (np) {
 			lookup->name = (char *)np->name;
-			if (lookup->phys_addr)
+			if (lookup->phys_addr) {
+				of_node_put(np);
 				continue;
+			}
 			if (!of_address_to_resource(np, 0, &res))
 				lookup->phys_addr = res.start;
+			of_node_put(np);
 		}
 	}
 
+	of_node_put(root);
+
 	return 0;
 }
 
diff --git a/arch/mips/pic32/pic32mzda/time.c b/arch/mips/pic32/pic32mzda/time.c
index 7174e9abbb1ba..777b515c52c8d 100644
--- a/arch/mips/pic32/pic32mzda/time.c
+++ b/arch/mips/pic32/pic32mzda/time.c
@@ -32,6 +32,9 @@ static unsigned int pic32_xlate_core_timer_irq(void)
 		goto default_map;
 
 	irq = irq_of_parse_and_map(node, 0);
+
+	of_node_put(node);
+
 	if (!irq)
 		goto default_map;
 
-- 
GitLab


From 60050ffe3d770dd1df5b641aa48f49d07a54bd84 Mon Sep 17 00:00:00 2001
From: David Howells <dhowells@redhat.com>
Date: Wed, 18 May 2022 23:48:09 +0100
Subject: [PATCH 0921/1731] certs: Move load_certificate_list() to be with the
 asymmetric keys code

Move load_certificate_list(), which loads a series of binary X.509
certificates from a blob and inserts them as keys into a keyring, to be
with the asymmetric keys code that it drives.

This makes it easier to add FIPS selftest code in which we need to load up
a private keyring for the tests to use.

Signed-off-by: David Howells <dhowells@redhat.com>
Reviewed-by: Simo Sorce <simo@redhat.com>
Reviewed-by: Herbert Xu <herbert@gondor.apana.org.au>
cc: keyrings@vger.kernel.org
cc: linux-crypto@vger.kernel.org
Link: https://lore.kernel.org/r/165515742145.1554877.13488098107542537203.stgit@warthog.procyon.org.uk/
---
 certs/Makefile                                         | 4 ++--
 certs/blacklist.c                                      | 8 ++++----
 certs/common.h                                         | 9 ---------
 certs/system_keyring.c                                 | 6 +++---
 crypto/asymmetric_keys/Makefile                        | 1 +
 certs/common.c => crypto/asymmetric_keys/x509_loader.c | 8 ++++----
 include/keys/asymmetric-type.h                         | 3 +++
 7 files changed, 17 insertions(+), 22 deletions(-)
 delete mode 100644 certs/common.h
 rename certs/common.c => crypto/asymmetric_keys/x509_loader.c (87%)

diff --git a/certs/Makefile b/certs/Makefile
index cb1a9da3fc581..3aac9f33ee22d 100644
--- a/certs/Makefile
+++ b/certs/Makefile
@@ -3,8 +3,8 @@
 # Makefile for the linux kernel signature checking certificates.
 #
 
-obj-$(CONFIG_SYSTEM_TRUSTED_KEYRING) += system_keyring.o system_certificates.o common.o
-obj-$(CONFIG_SYSTEM_BLACKLIST_KEYRING) += blacklist.o common.o
+obj-$(CONFIG_SYSTEM_TRUSTED_KEYRING) += system_keyring.o system_certificates.o
+obj-$(CONFIG_SYSTEM_BLACKLIST_KEYRING) += blacklist.o
 obj-$(CONFIG_SYSTEM_REVOCATION_LIST) += revocation_certificates.o
 ifneq ($(CONFIG_SYSTEM_BLACKLIST_HASH_LIST),)
 quiet_cmd_check_blacklist_hashes = CHECK   $(patsubst "%",%,$(2))
diff --git a/certs/blacklist.c b/certs/blacklist.c
index 25094ea736007..41f10601cc724 100644
--- a/certs/blacklist.c
+++ b/certs/blacklist.c
@@ -15,10 +15,9 @@
 #include <linux/err.h>
 #include <linux/seq_file.h>
 #include <linux/uidgid.h>
-#include <linux/verification.h>
+#include <keys/asymmetric-type.h>
 #include <keys/system_keyring.h>
 #include "blacklist.h"
-#include "common.h"
 
 /*
  * According to crypto/asymmetric_keys/x509_cert_parser.c:x509_note_pkey_algo(),
@@ -365,8 +364,9 @@ static __init int load_revocation_certificate_list(void)
 	if (revocation_certificate_list_size)
 		pr_notice("Loading compiled-in revocation X.509 certificates\n");
 
-	return load_certificate_list(revocation_certificate_list, revocation_certificate_list_size,
-				     blacklist_keyring);
+	return x509_load_certificate_list(revocation_certificate_list,
+					  revocation_certificate_list_size,
+					  blacklist_keyring);
 }
 late_initcall(load_revocation_certificate_list);
 #endif
diff --git a/certs/common.h b/certs/common.h
deleted file mode 100644
index abdb5795936b7..0000000000000
--- a/certs/common.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#ifndef _CERT_COMMON_H
-#define _CERT_COMMON_H
-
-int load_certificate_list(const u8 cert_list[], const unsigned long list_size,
-			  const struct key *keyring);
-
-#endif
diff --git a/certs/system_keyring.c b/certs/system_keyring.c
index 05b66ce9d1c9e..5042cc54fa5ec 100644
--- a/certs/system_keyring.c
+++ b/certs/system_keyring.c
@@ -16,7 +16,6 @@
 #include <keys/asymmetric-type.h>
 #include <keys/system_keyring.h>
 #include <crypto/pkcs7.h>
-#include "common.h"
 
 static struct key *builtin_trusted_keys;
 #ifdef CONFIG_SECONDARY_TRUSTED_KEYRING
@@ -183,7 +182,8 @@ __init int load_module_cert(struct key *keyring)
 
 	pr_notice("Loading compiled-in module X.509 certificates\n");
 
-	return load_certificate_list(system_certificate_list, module_cert_size, keyring);
+	return x509_load_certificate_list(system_certificate_list,
+					  module_cert_size, keyring);
 }
 
 /*
@@ -204,7 +204,7 @@ static __init int load_system_certificate_list(void)
 	size = system_certificate_list_size - module_cert_size;
 #endif
 
-	return load_certificate_list(p, size, builtin_trusted_keys);
+	return x509_load_certificate_list(p, size, builtin_trusted_keys);
 }
 late_initcall(load_system_certificate_list);
 
diff --git a/crypto/asymmetric_keys/Makefile b/crypto/asymmetric_keys/Makefile
index c38424f55b08d..0f190500dd872 100644
--- a/crypto/asymmetric_keys/Makefile
+++ b/crypto/asymmetric_keys/Makefile
@@ -20,6 +20,7 @@ x509_key_parser-y := \
 	x509.asn1.o \
 	x509_akid.asn1.o \
 	x509_cert_parser.o \
+	x509_loader.o \
 	x509_public_key.o
 
 $(obj)/x509_cert_parser.o: \
diff --git a/certs/common.c b/crypto/asymmetric_keys/x509_loader.c
similarity index 87%
rename from certs/common.c
rename to crypto/asymmetric_keys/x509_loader.c
index 16a220887a53e..1bc169dee22e0 100644
--- a/certs/common.c
+++ b/crypto/asymmetric_keys/x509_loader.c
@@ -2,11 +2,11 @@
 
 #include <linux/kernel.h>
 #include <linux/key.h>
-#include "common.h"
+#include <keys/asymmetric-type.h>
 
-int load_certificate_list(const u8 cert_list[],
-			  const unsigned long list_size,
-			  const struct key *keyring)
+int x509_load_certificate_list(const u8 cert_list[],
+			       const unsigned long list_size,
+			       const struct key *keyring)
 {
 	key_ref_t key;
 	const u8 *p, *end;
diff --git a/include/keys/asymmetric-type.h b/include/keys/asymmetric-type.h
index 6c5d4963e15bc..69a13e1e5b2e5 100644
--- a/include/keys/asymmetric-type.h
+++ b/include/keys/asymmetric-type.h
@@ -84,6 +84,9 @@ extern struct key *find_asymmetric_key(struct key *keyring,
 				       const struct asymmetric_key_id *id_2,
 				       bool partial);
 
+int x509_load_certificate_list(const u8 cert_list[], const unsigned long list_size,
+			       const struct key *keyring);
+
 /*
  * The payload is at the discretion of the subtype.
  */
-- 
GitLab


From 3cde3174eb910513d32a9ec8a9b95ea59be833df Mon Sep 17 00:00:00 2001
From: David Howells <dhowells@redhat.com>
Date: Wed, 18 May 2022 17:15:34 +0100
Subject: [PATCH 0922/1731] certs: Add FIPS selftests

Add some selftests for signature checking when FIPS mode is enabled.  These
need to be done before we start actually using the signature checking for
things and must panic the kernel upon failure.

Note that the tests must not check the blacklist lest this provide a way to
prevent a kernel from booting by installing a hash of a test key in the
appropriate UEFI table.

Reported-by: Simo Sorce <simo@redhat.com>
Signed-off-by: David Howells <dhowells@redhat.com>
Reviewed-by: Simo Sorce <simo@redhat.com>
Reviewed-by: Herbert Xu <herbert@gondor.apana.org.au>
cc: keyrings@vger.kernel.org
cc: linux-crypto@vger.kernel.org
Link: https://lore.kernel.org/r/165515742832.1554877.2073456606206090838.stgit@warthog.procyon.org.uk/
---
 crypto/asymmetric_keys/Kconfig           |  10 +
 crypto/asymmetric_keys/Makefile          |   1 +
 crypto/asymmetric_keys/selftest.c        | 224 +++++++++++++++++++++++
 crypto/asymmetric_keys/x509_parser.h     |   9 +
 crypto/asymmetric_keys/x509_public_key.c |   8 +-
 5 files changed, 251 insertions(+), 1 deletion(-)
 create mode 100644 crypto/asymmetric_keys/selftest.c

diff --git a/crypto/asymmetric_keys/Kconfig b/crypto/asymmetric_keys/Kconfig
index 460bc5d0a828c..3df3fe4ed95fa 100644
--- a/crypto/asymmetric_keys/Kconfig
+++ b/crypto/asymmetric_keys/Kconfig
@@ -75,4 +75,14 @@ config SIGNED_PE_FILE_VERIFICATION
 	  This option provides support for verifying the signature(s) on a
 	  signed PE binary.
 
+config FIPS_SIGNATURE_SELFTEST
+	bool "Run FIPS selftests on the X.509+PKCS7 signature verification"
+	help
+	  This option causes some selftests to be run on the signature
+	  verification code, using some built in data.  This is required
+	  for FIPS.
+	depends on KEYS
+	depends on ASYMMETRIC_KEY_TYPE
+	depends on PKCS7_MESSAGE_PARSER
+
 endif # ASYMMETRIC_KEY_TYPE
diff --git a/crypto/asymmetric_keys/Makefile b/crypto/asymmetric_keys/Makefile
index 0f190500dd872..0d1fa1b692c6b 100644
--- a/crypto/asymmetric_keys/Makefile
+++ b/crypto/asymmetric_keys/Makefile
@@ -22,6 +22,7 @@ x509_key_parser-y := \
 	x509_cert_parser.o \
 	x509_loader.o \
 	x509_public_key.o
+x509_key_parser-$(CONFIG_FIPS_SIGNATURE_SELFTEST) += selftest.o
 
 $(obj)/x509_cert_parser.o: \
 	$(obj)/x509.asn1.h \
diff --git a/crypto/asymmetric_keys/selftest.c b/crypto/asymmetric_keys/selftest.c
new file mode 100644
index 0000000000000..fa0bf7f242849
--- /dev/null
+++ b/crypto/asymmetric_keys/selftest.c
@@ -0,0 +1,224 @@
+/* Self-testing for signature checking.
+ *
+ * Copyright (C) 2022 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ */
+
+#include <linux/kernel.h>
+#include <linux/cred.h>
+#include <linux/key.h>
+#include <crypto/pkcs7.h>
+#include "x509_parser.h"
+
+struct certs_test {
+	const u8	*data;
+	size_t		data_len;
+	const u8	*pkcs7;
+	size_t		pkcs7_len;
+};
+
+/*
+ * Set of X.509 certificates to provide public keys for the tests.  These will
+ * be loaded into a temporary keyring for the duration of the testing.
+ */
+static const __initconst u8 certs_selftest_keys[] = {
+	"\x30\x82\x05\x55\x30\x82\x03\x3d\xa0\x03\x02\x01\x02\x02\x14\x73"
+	"\x98\xea\x98\x2d\xd0\x2e\xa8\xb1\xcf\x57\xc7\xf2\x97\xb3\xe6\x1a"
+	"\xfc\x8c\x0a\x30\x0d\x06\x09\x2a\x86\x48\x86\xf7\x0d\x01\x01\x0b"
+	"\x05\x00\x30\x34\x31\x32\x30\x30\x06\x03\x55\x04\x03\x0c\x29\x43"
+	"\x65\x72\x74\x69\x66\x69\x63\x61\x74\x65\x20\x76\x65\x72\x69\x66"
+	"\x69\x63\x61\x74\x69\x6f\x6e\x20\x73\x65\x6c\x66\x2d\x74\x65\x73"
+	"\x74\x69\x6e\x67\x20\x6b\x65\x79\x30\x20\x17\x0d\x32\x32\x30\x35"
+	"\x31\x38\x32\x32\x33\x32\x34\x31\x5a\x18\x0f\x32\x31\x32\x32\x30"
+	"\x34\x32\x34\x32\x32\x33\x32\x34\x31\x5a\x30\x34\x31\x32\x30\x30"
+	"\x06\x03\x55\x04\x03\x0c\x29\x43\x65\x72\x74\x69\x66\x69\x63\x61"
+	"\x74\x65\x20\x76\x65\x72\x69\x66\x69\x63\x61\x74\x69\x6f\x6e\x20"
+	"\x73\x65\x6c\x66\x2d\x74\x65\x73\x74\x69\x6e\x67\x20\x6b\x65\x79"
+	"\x30\x82\x02\x22\x30\x0d\x06\x09\x2a\x86\x48\x86\xf7\x0d\x01\x01"
+	"\x01\x05\x00\x03\x82\x02\x0f\x00\x30\x82\x02\x0a\x02\x82\x02\x01"
+	"\x00\xcc\xac\x49\xdd\x3b\xca\xb0\x15\x7e\x84\x6a\xb2\x0a\x69\x5f"
+	"\x1c\x0a\x61\x82\x3b\x4f\x2c\xa3\x95\x2c\x08\x58\x4b\xb1\x5d\x99"
+	"\xe0\xc3\xc1\x79\xc2\xb3\xeb\xc0\x1e\x6d\x3e\x54\x1d\xbd\xb7\x92"
+	"\x7b\x4d\xb5\x95\x58\xb2\x52\x2e\xc6\x24\x4b\x71\x63\x80\x32\x77"
+	"\xa7\x38\x5e\xdb\x72\xae\x6e\x0d\xec\xfb\xb6\x6d\x01\x7f\xe9\x55"
+	"\x66\xdf\xbf\x1d\x76\x78\x02\x31\xe8\xe5\x07\xf8\xb7\x82\x5c\x0d"
+	"\xd4\xbb\xfb\xa2\x59\x0d\x2e\x3a\x78\x95\x3a\x8b\x46\x06\x47\x44"
+	"\x46\xd7\xcd\x06\x6a\x41\x13\xe3\x19\xf6\xbb\x6e\x38\xf4\x83\x01"
+	"\xa3\xbf\x4a\x39\x4f\xd7\x0a\xe9\x38\xb3\xf5\x94\x14\x4e\xdd\xf7"
+	"\x43\xfd\x24\xb2\x49\x3c\xa5\xf7\x7a\x7c\xd4\x45\x3d\x97\x75\x68"
+	"\xf1\xed\x4c\x42\x0b\x70\xca\x85\xf3\xde\xe5\x88\x2c\xc5\xbe\xb6"
+	"\x97\x34\xba\x24\x02\xcd\x8b\x86\x9f\xa9\x73\xca\x73\xcf\x92\x81"
+	"\xee\x75\x55\xbb\x18\x67\x5c\xff\x3f\xb5\xdd\x33\x1b\x0c\xe9\x78"
+	"\xdb\x5c\xcf\xaa\x5c\x43\x42\xdf\x5e\xa9\x6d\xec\xd7\xd7\xff\xe6"
+	"\xa1\x3a\x92\x1a\xda\xae\xf6\x8c\x6f\x7b\xd5\xb4\x6e\x06\xe9\x8f"
+	"\xe8\xde\x09\x31\x89\xed\x0e\x11\xa1\xfa\x8a\xe9\xe9\x64\x59\x62"
+	"\x53\xda\xd1\x70\xbe\x11\xd4\x99\x97\x11\xcf\x99\xde\x0b\x9d\x94"
+	"\x7e\xaa\xb8\x52\xea\x37\xdb\x90\x7e\x35\xbd\xd9\xfe\x6d\x0a\x48"
+	"\x70\x28\xdd\xd5\x0d\x7f\x03\x80\x93\x14\x23\x8f\xb9\x22\xcd\x7c"
+	"\x29\xfe\xf1\x72\xb5\x5c\x0b\x12\xcf\x9c\x15\xf6\x11\x4c\x7a\x45"
+	"\x25\x8c\x45\x0a\x34\xac\x2d\x9a\x81\xca\x0b\x13\x22\xcd\xeb\x1a"
+	"\x38\x88\x18\x97\x96\x08\x81\xaa\xcc\x8f\x0f\x8a\x32\x7b\x76\x68"
+	"\x03\x68\x43\xbf\x11\xba\x55\x60\xfd\x80\x1c\x0d\x9b\x69\xb6\x09"
+	"\x72\xbc\x0f\x41\x2f\x07\x82\xc6\xe3\xb2\x13\x91\xc4\x6d\x14\x95"
+	"\x31\xbe\x19\xbd\xbc\xed\xe1\x4c\x74\xa2\xe0\x78\x0b\xbb\x94\xec"
+	"\x4c\x53\x3a\xa2\xb5\x84\x1d\x4b\x65\x7e\xdc\xf7\xdb\x36\x7d\xbe"
+	"\x9e\x3b\x36\x66\x42\x66\x76\x35\xbf\xbe\xf0\xc1\x3c\x7c\xe9\x42"
+	"\x5c\x24\x53\x03\x05\xa8\x67\x24\x50\x02\x75\xff\x24\x46\x3b\x35"
+	"\x89\x76\xe6\x70\xda\xc5\x51\x8c\x9a\xe5\x05\xb0\x0b\xd0\x2d\xd4"
+	"\x7d\x57\x75\x94\x6b\xf9\x0a\xad\x0e\x41\x00\x15\xd0\x4f\xc0\x7f"
+	"\x90\x2d\x18\x48\x8f\x28\xfe\x5d\xa7\xcd\x99\x9e\xbd\x02\x6c\x8a"
+	"\x31\xf3\x1c\xc7\x4b\xe6\x93\xcd\x42\xa2\xe4\x68\x10\x47\x9d\xfc"
+	"\x21\x02\x03\x01\x00\x01\xa3\x5d\x30\x5b\x30\x0c\x06\x03\x55\x1d"
+	"\x13\x01\x01\xff\x04\x02\x30\x00\x30\x0b\x06\x03\x55\x1d\x0f\x04"
+	"\x04\x03\x02\x07\x80\x30\x1d\x06\x03\x55\x1d\x0e\x04\x16\x04\x14"
+	"\xf5\x87\x03\xbb\x33\xce\x1b\x73\xee\x02\xec\xcd\xee\x5b\x88\x17"
+	"\x51\x8f\xe3\xdb\x30\x1f\x06\x03\x55\x1d\x23\x04\x18\x30\x16\x80"
+	"\x14\xf5\x87\x03\xbb\x33\xce\x1b\x73\xee\x02\xec\xcd\xee\x5b\x88"
+	"\x17\x51\x8f\xe3\xdb\x30\x0d\x06\x09\x2a\x86\x48\x86\xf7\x0d\x01"
+	"\x01\x0b\x05\x00\x03\x82\x02\x01\x00\xc0\x2e\x12\x41\x7b\x73\x85"
+	"\x16\xc8\xdb\x86\x79\xe8\xf5\xcd\x44\xf4\xc6\xe2\x81\x23\x5e\x47"
+	"\xcb\xab\x25\xf1\x1e\x58\x3e\x31\x7f\x78\xad\x85\xeb\xfe\x14\x88"
+	"\x60\xf7\x7f\xd2\x26\xa2\xf4\x98\x2a\xfd\xba\x05\x0c\x20\x33\x12"
+	"\xcc\x4d\x14\x61\x64\x81\x93\xd3\x33\xed\xc8\xff\xf1\x78\xcc\x5f"
+	"\x51\x9f\x09\xd7\xbe\x0d\x5c\x74\xfd\x9b\xdf\x52\x4a\xc9\xa8\x71"
+	"\x25\x33\x04\x10\x67\x36\xd0\xb3\x0b\xc9\xa1\x40\x72\xae\x41\x7b"
+	"\x68\xe6\xe4\x7b\xd0\x28\xf7\x6d\xe7\x3f\x50\xfc\x91\x7c\x91\x56"
+	"\xd4\xdf\xa6\xbb\xe8\x4d\x1b\x58\xaa\x28\xfa\xc1\x19\xeb\x11\x2f"
+	"\x24\x8b\x7c\xc5\xa9\x86\x26\xaa\x6e\xb7\x9b\xd5\xf8\x06\xfb\x02"
+	"\x52\x7b\x9c\x9e\xa1\xe0\x07\x8b\x5e\xe4\xb8\x55\x29\xf6\x48\x52"
+	"\x1c\x1b\x54\x2d\x46\xd8\xe5\x71\xb9\x60\xd1\x45\xb5\x92\x89\x8a"
+	"\x63\x58\x2a\xb3\xc6\xb2\x76\xe2\x3c\x82\x59\x04\xae\x5a\xc4\x99"
+	"\x7b\x2e\x4b\x46\x57\xb8\x29\x24\xb2\xfd\xee\x2c\x0d\xa4\x83\xfa"
+	"\x65\x2a\x07\x35\x8b\x97\xcf\xbd\x96\x2e\xd1\x7e\x6c\xc2\x1e\x87"
+	"\xb6\x6c\x76\x65\xb5\xb2\x62\xda\x8b\xe9\x73\xe3\xdb\x33\xdd\x13"
+	"\x3a\x17\x63\x6a\x76\xde\x8d\x8f\xe0\x47\x61\x28\x3a\x83\xff\x8f"
+	"\xe7\xc7\xe0\x4a\xa3\xe5\x07\xcf\xe9\x8c\x35\x35\x2e\xe7\x80\x66"
+	"\x31\xbf\x91\x58\x0a\xe1\x25\x3d\x38\xd3\xa4\xf0\x59\x34\x47\x07"
+	"\x62\x0f\xbe\x30\xdd\x81\x88\x58\xf0\x28\xb0\x96\xe5\x82\xf8\x05"
+	"\xb7\x13\x01\xbc\xfa\xc6\x1f\x86\x72\xcc\xf9\xee\x8e\xd9\xd6\x04"
+	"\x8c\x24\x6c\xbf\x0f\x5d\x37\x39\xcf\x45\xc1\x93\x3a\xd2\xed\x5c"
+	"\x58\x79\x74\x86\x62\x30\x7e\x8e\xbb\xdd\x7a\xa9\xed\xca\x40\xcb"
+	"\x62\x47\xf4\xb4\x9f\x52\x7f\x72\x63\xa8\xf0\x2b\xaf\x45\x2a\x48"
+	"\x19\x6d\xe3\xfb\xf9\x19\x66\x69\xc8\xcc\x62\x87\x6c\x53\x2b\x2d"
+	"\x6e\x90\x6c\x54\x3a\x82\x25\x41\xcb\x18\x6a\xa4\x22\xa8\xa1\xc4"
+	"\x47\xd7\x81\x00\x1c\x15\x51\x0f\x1a\xaf\xef\x9f\xa6\x61\x8c\xbd"
+	"\x6b\x8b\xed\xe6\xac\x0e\xb6\x3a\x4c\x92\xe6\x0f\x91\x0a\x0f\x71"
+	"\xc7\xa0\xb9\x0d\x3a\x17\x5a\x6f\x35\xc8\xe7\x50\x4f\x46\xe8\x70"
+	"\x60\x48\x06\x82\x8b\x66\x58\xe6\x73\x91\x9c\x12\x3d\x35\x8e\x46"
+	"\xad\x5a\xf5\xb3\xdb\x69\x21\x04\xfd\xd3\x1c\xdf\x94\x9d\x56\xb0"
+	"\x0a\xd1\x95\x76\x8d\xec\x9e\xdd\x0b\x15\x97\x64\xad\xe5\xf2\x62"
+	"\x02\xfc\x9e\x5f\x56\x42\x39\x05\xb3"
+};
+
+/*
+ * Signed data and detached signature blobs that form the verification tests.
+ */
+static const __initconst u8 certs_selftest_1_data[] = {
+	"\x54\x68\x69\x73\x20\x69\x73\x20\x73\x6f\x6d\x65\x20\x74\x65\x73"
+	"\x74\x20\x64\x61\x74\x61\x20\x75\x73\x65\x64\x20\x66\x6f\x72\x20"
+	"\x73\x65\x6c\x66\x2d\x74\x65\x73\x74\x69\x6e\x67\x20\x63\x65\x72"
+	"\x74\x69\x66\x69\x63\x61\x74\x65\x20\x76\x65\x72\x69\x66\x69\x63"
+	"\x61\x74\x69\x6f\x6e\x2e\x0a"
+};
+
+static const __initconst u8 certs_selftest_1_pkcs7[] = {
+	"\x30\x82\x02\xab\x06\x09\x2a\x86\x48\x86\xf7\x0d\x01\x07\x02\xa0"
+	"\x82\x02\x9c\x30\x82\x02\x98\x02\x01\x01\x31\x0d\x30\x0b\x06\x09"
+	"\x60\x86\x48\x01\x65\x03\x04\x02\x01\x30\x0b\x06\x09\x2a\x86\x48"
+	"\x86\xf7\x0d\x01\x07\x01\x31\x82\x02\x75\x30\x82\x02\x71\x02\x01"
+	"\x01\x30\x4c\x30\x34\x31\x32\x30\x30\x06\x03\x55\x04\x03\x0c\x29"
+	"\x43\x65\x72\x74\x69\x66\x69\x63\x61\x74\x65\x20\x76\x65\x72\x69"
+	"\x66\x69\x63\x61\x74\x69\x6f\x6e\x20\x73\x65\x6c\x66\x2d\x74\x65"
+	"\x73\x74\x69\x6e\x67\x20\x6b\x65\x79\x02\x14\x73\x98\xea\x98\x2d"
+	"\xd0\x2e\xa8\xb1\xcf\x57\xc7\xf2\x97\xb3\xe6\x1a\xfc\x8c\x0a\x30"
+	"\x0b\x06\x09\x60\x86\x48\x01\x65\x03\x04\x02\x01\x30\x0d\x06\x09"
+	"\x2a\x86\x48\x86\xf7\x0d\x01\x01\x01\x05\x00\x04\x82\x02\x00\xac"
+	"\xb0\xf2\x07\xd6\x99\x6d\xc0\xc0\xd9\x8d\x31\x0d\x7e\x04\xeb\xc3"
+	"\x88\x90\xc4\x58\x46\xd4\xe2\xa0\xa3\x25\xe3\x04\x50\x37\x85\x8c"
+	"\x91\xc6\xfc\xc5\xd4\x92\xfd\x05\xd8\xb8\xa3\xb8\xba\x89\x13\x00"
+	"\x88\x79\x99\x51\x6b\x5b\x28\x31\xc0\xb3\x1b\x7a\x68\x2c\x00\xdb"
+	"\x4b\x46\x11\xf3\xfa\x50\x8e\x19\x89\xa2\x4c\xda\x4c\x89\x01\x11"
+	"\x89\xee\xd3\xc8\xc1\xe7\xa7\xf6\xb2\xa2\xf8\x65\xb8\x35\x20\x33"
+	"\xba\x12\x62\xd5\xbd\xaa\x71\xe5\x5b\xc0\x6a\x32\xff\x6a\x2e\x23"
+	"\xef\x2b\xb6\x58\xb1\xfb\x5f\x82\x34\x40\x6d\x9f\xbc\x27\xac\x37"
+	"\x23\x99\xcf\x7d\x20\xb2\x39\x01\xc0\x12\xce\xd7\x5d\x2f\xb6\xab"
+	"\xb5\x56\x4f\xef\xf4\x72\x07\x58\x65\xa9\xeb\x1f\x75\x1c\x5f\x0c"
+	"\x88\xe0\xa4\xe2\xcd\x73\x2b\x9e\xb2\x05\x7e\x12\xf8\xd0\x66\x41"
+	"\xcc\x12\x63\xd4\xd6\xac\x9b\x1d\x14\x77\x8d\x1c\x57\xd5\x27\xc6"
+	"\x49\xa2\x41\x43\xf3\x59\x29\xe5\xcb\xd1\x75\xbc\x3a\x97\x2a\x72"
+	"\x22\x66\xc5\x3b\xc1\xba\xfc\x53\x18\x98\xe2\x21\x64\xc6\x52\x87"
+	"\x13\xd5\x7c\x42\xe8\xfb\x9c\x9a\x45\x32\xd5\xa5\x22\x62\x9d\xd4"
+	"\xcb\xa4\xfa\x77\xbb\x50\x24\x0b\x8b\x88\x99\x15\x56\xa9\x1e\x92"
+	"\xbf\x5d\x94\x77\xb6\xf1\x67\x01\x60\x06\x58\x5c\xdf\x18\x52\x79"
+	"\x37\x30\x93\x7d\x87\x04\xf1\xe0\x55\x59\x52\xf3\xc2\xb1\x1c\x5b"
+	"\x12\x7c\x49\x87\xfb\xf7\xed\xdd\x95\x71\xec\x4b\x1a\x85\x08\xb0"
+	"\xa0\x36\xc4\x7b\xab\x40\xe0\xf1\x98\xcc\xaf\x19\x40\x8f\x47\x6f"
+	"\xf0\x6c\x84\x29\x7f\x7f\x04\x46\xcb\x08\x0f\xe0\xc1\xc9\x70\x6e"
+	"\x95\x3b\xa4\xbc\x29\x2b\x53\x67\x45\x1b\x0d\xbc\x13\xa5\x76\x31"
+	"\xaf\xb9\xd0\xe0\x60\x12\xd2\xf4\xb7\x7c\x58\x7e\xf6\x2d\xbb\x24"
+	"\x14\x5a\x20\x24\xa8\x12\xdf\x25\xbd\x42\xce\x96\x7c\x2e\xba\x14"
+	"\x1b\x81\x9f\x18\x45\xa4\xc6\x70\x3e\x0e\xf0\xd3\x7b\x9c\x10\xbe"
+	"\xb8\x7a\x89\xc5\x9e\xd9\x97\xdf\xd7\xe7\xc6\x1d\xc0\x20\x6c\xb8"
+	"\x1e\x3a\x63\xb8\x39\x8e\x8e\x62\xd5\xd2\xb4\xcd\xff\x46\xfc\x8e"
+	"\xec\x07\x35\x0c\xff\xb0\x05\xe6\xf4\xe5\xfe\xa2\xe3\x0a\xe6\x36"
+	"\xa7\x4a\x7e\x62\x1d\xc4\x50\x39\x35\x4e\x28\xcb\x4a\xfb\x9d\xdb"
+	"\xdd\x23\xd6\x53\xb1\x74\x77\x12\xf7\x9c\xf0\x9a\x6b\xf7\xa9\x64"
+	"\x2d\x86\x21\x2a\xcf\xc6\x54\xf5\xc9\xad\xfa\xb5\x12\xb4\xf3\x51"
+	"\x77\x55\x3c\x6f\x0c\x32\xd3\x8c\x44\x39\x71\x25\xfe\x96\xd2"
+};
+
+/*
+ * List of tests to be run.
+ */
+#define TEST(data, pkcs7) { data, sizeof(data) - 1, pkcs7, sizeof(pkcs7) - 1 }
+static const struct certs_test certs_tests[] __initconst = {
+	TEST(certs_selftest_1_data, certs_selftest_1_pkcs7),
+};
+
+int __init fips_signature_selftest(void)
+{
+	struct key *keyring;
+	int ret, i;
+
+	pr_notice("Running certificate verification selftests\n");
+
+	keyring = keyring_alloc(".certs_selftest",
+				GLOBAL_ROOT_UID, GLOBAL_ROOT_GID, current_cred(),
+				(KEY_POS_ALL & ~KEY_POS_SETATTR) |
+				KEY_USR_VIEW | KEY_USR_READ |
+				KEY_USR_SEARCH,
+				KEY_ALLOC_NOT_IN_QUOTA,
+				NULL, NULL);
+	if (IS_ERR(keyring))
+		panic("Can't allocate certs selftest keyring: %ld\n",
+		      PTR_ERR(keyring));
+
+	ret = x509_load_certificate_list(certs_selftest_keys,
+					 sizeof(certs_selftest_keys) - 1, keyring);
+	if (ret < 0)
+		panic("Can't allocate certs selftest keyring: %d\n", ret);
+
+	for (i = 0; i < ARRAY_SIZE(certs_tests); i++) {
+		const struct certs_test *test = &certs_tests[i];
+		struct pkcs7_message *pkcs7;
+
+		pkcs7 = pkcs7_parse_message(test->pkcs7, test->pkcs7_len);
+		if (IS_ERR(pkcs7))
+			panic("Certs selftest %d: pkcs7_parse_message() = %d\n", i, ret);
+
+		pkcs7_supply_detached_data(pkcs7, test->data, test->data_len);
+
+		ret = pkcs7_verify(pkcs7, VERIFYING_MODULE_SIGNATURE);
+		if (ret < 0)
+			panic("Certs selftest %d: pkcs7_verify() = %d\n", i, ret);
+
+		ret = pkcs7_validate_trust(pkcs7, keyring);
+		if (ret < 0)
+			panic("Certs selftest %d: pkcs7_validate_trust() = %d\n", i, ret);
+
+		pkcs7_free_message(pkcs7);
+	}
+
+	key_put(keyring);
+	return 0;
+}
diff --git a/crypto/asymmetric_keys/x509_parser.h b/crypto/asymmetric_keys/x509_parser.h
index 97a886cbe01c3..a299c9c56f409 100644
--- a/crypto/asymmetric_keys/x509_parser.h
+++ b/crypto/asymmetric_keys/x509_parser.h
@@ -40,6 +40,15 @@ struct x509_certificate {
 	bool		blacklisted;
 };
 
+/*
+ * selftest.c
+ */
+#ifdef CONFIG_FIPS_SIGNATURE_SELFTEST
+extern int __init fips_signature_selftest(void);
+#else
+static inline int fips_signature_selftest(void) { return 0; }
+#endif
+
 /*
  * x509_cert_parser.c
  */
diff --git a/crypto/asymmetric_keys/x509_public_key.c b/crypto/asymmetric_keys/x509_public_key.c
index 77ed4e93ad56f..0b4943a4592b7 100644
--- a/crypto/asymmetric_keys/x509_public_key.c
+++ b/crypto/asymmetric_keys/x509_public_key.c
@@ -244,9 +244,15 @@ static struct asymmetric_key_parser x509_key_parser = {
 /*
  * Module stuff
  */
+extern int __init certs_selftest(void);
 static int __init x509_key_init(void)
 {
-	return register_asymmetric_key_parser(&x509_key_parser);
+	int ret;
+
+	ret = register_asymmetric_key_parser(&x509_key_parser);
+	if (ret < 0)
+		return ret;
+	return fips_signature_selftest();
 }
 
 static void __exit x509_key_exit(void)
-- 
GitLab


From db30dc1a5226eb74d52f748989e9a06451333678 Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Date: Fri, 17 Jun 2022 13:18:05 +0100
Subject: [PATCH 0923/1731] mips: dts: ingenic: Add TCU clock to x1000/x1830
 tcu device node

This clock is a gate for the TCU hardware block on these SoCs, but
it wasn't included in the device tree since the ingenic-tcu driver
erroneously did not request it.

Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
 arch/mips/boot/dts/ingenic/x1000.dtsi | 5 +++--
 arch/mips/boot/dts/ingenic/x1830.dtsi | 5 +++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
index b0a034b468bbb..42e69664efd93 100644
--- a/arch/mips/boot/dts/ingenic/x1000.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
@@ -111,8 +111,9 @@
 
 		clocks = <&cgu X1000_CLK_RTCLK>,
 			 <&cgu X1000_CLK_EXCLK>,
-			 <&cgu X1000_CLK_PCLK>;
-		clock-names = "rtc", "ext", "pclk";
+			 <&cgu X1000_CLK_PCLK>,
+			 <&cgu X1000_CLK_TCU>;
+		clock-names = "rtc", "ext", "pclk", "tcu";
 
 		interrupt-controller;
 		#interrupt-cells = <1>;
diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
index dbf21afaccb1a..65a5da71c1994 100644
--- a/arch/mips/boot/dts/ingenic/x1830.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
@@ -104,8 +104,9 @@
 
 		clocks = <&cgu X1830_CLK_RTCLK>,
 			 <&cgu X1830_CLK_EXCLK>,
-			 <&cgu X1830_CLK_PCLK>;
-		clock-names = "rtc", "ext", "pclk";
+			 <&cgu X1830_CLK_PCLK>,
+			 <&cgu X1830_CLK_TCU>;
+		clock-names = "rtc", "ext", "pclk", "tcu";
 
 		interrupt-controller;
 		#interrupt-cells = <1>;
-- 
GitLab


From 82c7863ed95d0914f02c7c8c011200a763bc6725 Mon Sep 17 00:00:00 2001
From: Jaegeuk Kim <jaegeuk@kernel.org>
Date: Sat, 18 Jun 2022 00:42:24 -0700
Subject: [PATCH 0924/1731] f2fs: do not count ENOENT for error case

Otherwise, we can get a wrong cp_error mark.

Cc: <stable@vger.kernel.org>
Fixes: a7b8618aa2f0 ("f2fs: avoid infinite loop to flush node pages")
Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
---
 fs/f2fs/node.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/fs/f2fs/node.c b/fs/f2fs/node.c
index 836c79a20afc6..cf6f7fc83c082 100644
--- a/fs/f2fs/node.c
+++ b/fs/f2fs/node.c
@@ -1450,7 +1450,9 @@ page_hit:
 out_err:
 	ClearPageUptodate(page);
 out_put_err:
-	f2fs_handle_page_eio(sbi, page->index, NODE);
+	/* ENOENT comes from read_node_page which is not an error. */
+	if (err != -ENOENT)
+		f2fs_handle_page_eio(sbi, page->index, NODE);
 	f2fs_put_page(page, 1);
 	return ERR_PTR(err);
 }
-- 
GitLab


From 34705a57e7df97d161324263c103c4d4d120dfe7 Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas <javierm@redhat.com>
Date: Fri, 10 Jun 2022 11:00:05 +0200
Subject: [PATCH 0925/1731] efi: sysfb_efi: remove unnecessary <asm/efi.h>
 include

Nothing defined in the header is used by drivers/firmware/efi/sysfb_efi.c
but also, including it can lead to build errors when built on arches that
don't have an asm/efi.h header file.

This can happen for example if a driver that is built when COMPILE_TEST is
enabled selects the SYSFB symbol, e.g. on powerpc with allyesconfig:

drivers/firmware/efi/sysfb_efi.c:29:10: fatal error: asm/efi.h: No such file or directory
   29 | #include <asm/efi.h>
      |          ^~~~~~~~~~~

Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
 drivers/firmware/efi/sysfb_efi.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/firmware/efi/sysfb_efi.c b/drivers/firmware/efi/sysfb_efi.c
index 4c7c9dd7733f9..7882d4b3f2be4 100644
--- a/drivers/firmware/efi/sysfb_efi.c
+++ b/drivers/firmware/efi/sysfb_efi.c
@@ -26,8 +26,6 @@
 #include <linux/sysfb.h>
 #include <video/vga.h>
 
-#include <asm/efi.h>
-
 enum {
 	OVERRIDE_NONE = 0x0,
 	OVERRIDE_BASE = 0x1,
-- 
GitLab


From aa6d1ed107eba26f49933216cffe797253914132 Mon Sep 17 00:00:00 2001
From: Evgeniy Baskov <baskov@ispras.ru>
Date: Thu, 9 Jun 2022 14:37:30 +0300
Subject: [PATCH 0926/1731] efi/x86: libstub: Fix typo in __efi64_argmap* name

The actual name of the DXE services function used
is set_memory_space_attributes(), not set_memory_space_descriptor().

Change EFI mixed mode helper macro name to match the function name.

Fixes: 31f1a0edff78 ("efi/x86: libstub: Make DXE calls mixed mode safe")
Signed-off-by: Evgeniy Baskov <baskov@ispras.ru>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
 arch/x86/include/asm/efi.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h
index 71943dce691ed..9636742a80f29 100644
--- a/arch/x86/include/asm/efi.h
+++ b/arch/x86/include/asm/efi.h
@@ -323,7 +323,7 @@ static inline u32 efi64_convert_status(efi_status_t status)
 #define __efi64_argmap_get_memory_space_descriptor(phys, desc) \
 	(__efi64_split(phys), (desc))
 
-#define __efi64_argmap_set_memory_space_descriptor(phys, size, flags) \
+#define __efi64_argmap_set_memory_space_attributes(phys, size, flags) \
 	(__efi64_split(phys), __efi64_split(size), __efi64_split(flags))
 
 /*
-- 
GitLab


From cb78d1b5efffe4cf97e16766329dd7358aed3deb Mon Sep 17 00:00:00 2001
From: David Howells <dhowells@redhat.com>
Date: Tue, 21 Jun 2022 15:59:57 +0100
Subject: [PATCH 0927/1731] afs: Fix dynamic root getattr

The recent patch to make afs_getattr consult the server didn't account
for the pseudo-inodes employed by the dynamic root-type afs superblock
not having a volume or a server to access, and thus an oops occurs if
such a directory is stat'd.

Fix this by checking to see if the vnode->volume pointer actually points
anywhere before following it in afs_getattr().

This can be tested by stat'ing a directory in /afs.  It may be
sufficient just to do "ls /afs" and the oops looks something like:

        BUG: kernel NULL pointer dereference, address: 0000000000000020
        ...
        RIP: 0010:afs_getattr+0x8b/0x14b
        ...
        Call Trace:
         <TASK>
         vfs_statx+0x79/0xf5
         vfs_fstatat+0x49/0x62

Fixes: 2aeb8c86d499 ("afs: Fix afs_getattr() to refetch file status if callback break occurred")
Reported-by: Marc Dionne <marc.dionne@auristor.com>
Signed-off-by: David Howells <dhowells@redhat.com>
Reviewed-by: Marc Dionne <marc.dionne@auristor.com>
Tested-by: Marc Dionne <marc.dionne@auristor.com>
cc: linux-afs@lists.infradead.org
Link: https://lore.kernel.org/r/165408450783.1031787.7941404776393751186.stgit@warthog.procyon.org.uk/
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
---
 fs/afs/inode.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/fs/afs/inode.c b/fs/afs/inode.c
index 89630acbc2cc5..64dab70d4a4f3 100644
--- a/fs/afs/inode.c
+++ b/fs/afs/inode.c
@@ -745,7 +745,8 @@ int afs_getattr(struct user_namespace *mnt_userns, const struct path *path,
 
 	_enter("{ ino=%lu v=%u }", inode->i_ino, inode->i_generation);
 
-	if (!(query_flags & AT_STATX_DONT_SYNC) &&
+	if (vnode->volume &&
+	    !(query_flags & AT_STATX_DONT_SYNC) &&
 	    !test_bit(AFS_VNODE_CB_PROMISED, &vnode->flags)) {
 		key = afs_request_key(vnode->volume->cell);
 		if (IS_ERR(key))
-- 
GitLab


From 2645672ffe21f0a1c139bfbc05ad30fd4e4f2583 Mon Sep 17 00:00:00 2001
From: Jens Axboe <axboe@kernel.dk>
Date: Tue, 21 Jun 2022 10:03:57 -0600
Subject: [PATCH 0928/1731] block: pop cached rq before potentially blocking
 rq_qos_throttle()

If rq_qos_throttle() ends up blocking, then we will have invalidated and
flushed our current plug. Since blk_mq_get_cached_request() hasn't
popped the cached request off the plug list just yet, we end holding a
pointer to a request that is no longer valid. This insta-crashes with
rq->mq_hctx being NULL in the validity checks just after.

Pop the request off the cached list before doing rq_qos_throttle() to
avoid using a potentially stale request.

Fixes: 0a5aa8d161d1 ("block: fix blk_mq_attempt_bio_merge and rq_qos_throttle protection")
Reported-by: Dylan Yudaken <dylany@fb.com>
Tested-by: Dylan Yudaken <dylany@fb.com>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 block/blk-mq.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/block/blk-mq.c b/block/blk-mq.c
index 33145ba52c960..93d9d60980fb5 100644
--- a/block/blk-mq.c
+++ b/block/blk-mq.c
@@ -2765,15 +2765,20 @@ static inline struct request *blk_mq_get_cached_request(struct request_queue *q,
 		return NULL;
 	}
 
-	rq_qos_throttle(q, *bio);
-
 	if (blk_mq_get_hctx_type((*bio)->bi_opf) != rq->mq_hctx->type)
 		return NULL;
 	if (op_is_flush(rq->cmd_flags) != op_is_flush((*bio)->bi_opf))
 		return NULL;
 
-	rq->cmd_flags = (*bio)->bi_opf;
+	/*
+	 * If any qos ->throttle() end up blocking, we will have flushed the
+	 * plug and hence killed the cached_rq list as well. Pop this entry
+	 * before we throttle.
+	 */
 	plug->cached_rq = rq_list_next(rq);
+	rq_qos_throttle(q, *bio);
+
+	rq->cmd_flags = (*bio)->bi_opf;
 	INIT_LIST_HEAD(&rq->queuelist);
 	return rq;
 }
-- 
GitLab


From 9ae6e8b1c9bbf6874163d1243e393137313762b7 Mon Sep 17 00:00:00 2001
From: Nikos Tsironis <ntsironis@arrikto.com>
Date: Tue, 21 Jun 2022 15:24:03 +0300
Subject: [PATCH 0929/1731] dm era: commit metadata in postsuspend after worker
 stops

During postsuspend dm-era does the following:

1. Archives the current era
2. Commits the metadata, as part of the RPC call for archiving the
   current era
3. Stops the worker

Until the worker stops, it might write to the metadata again. Moreover,
these writes are not flushed to disk immediately, but are cached by the
dm-bufio client, which writes them back asynchronously.

As a result, the committed metadata of a suspended dm-era device might
not be consistent with the in-core metadata.

In some cases, this can result in the corruption of the on-disk
metadata. Suppose the following sequence of events:

1. Load a new table, e.g. a snapshot-origin table, to a device with a
   dm-era table
2. Suspend the device
3. dm-era commits its metadata, but the worker does a few more metadata
   writes until it stops, as part of digesting an archived writeset
4. These writes are cached by the dm-bufio client
5. Load the dm-era table to another device.
6. The new instance of the dm-era target loads the committed, on-disk
   metadata, which don't include the extra writes done by the worker
   after the metadata commit.
7. Resume the new device
8. The new dm-era target instance starts using the metadata
9. Resume the original device
10. The destructor of the old dm-era target instance is called and
    destroys the dm-bufio client, which results in flushing the cached
    writes to disk
11. These writes might overwrite the writes done by the new dm-era
    instance, hence corrupting its metadata.

Fix this by committing the metadata after the worker stops running.

stop_worker uses flush_workqueue to flush the current work. However, the
work item may re-queue itself and flush_workqueue doesn't wait for
re-queued works to finish.

This could result in the worker changing the metadata after they have
been committed, or writing to the metadata concurrently with the commit
in the postsuspend thread.

Use drain_workqueue instead, which waits until the work and all
re-queued works finish.

Fixes: eec40579d8487 ("dm: add era target")
Cc: stable@vger.kernel.org # v3.15+
Signed-off-by: Nikos Tsironis <ntsironis@arrikto.com>
Signed-off-by: Mike Snitzer <snitzer@kernel.org>
---
 drivers/md/dm-era-target.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/md/dm-era-target.c b/drivers/md/dm-era-target.c
index 1f6bf152b3c74..e92c1afc3677f 100644
--- a/drivers/md/dm-era-target.c
+++ b/drivers/md/dm-era-target.c
@@ -1400,7 +1400,7 @@ static void start_worker(struct era *era)
 static void stop_worker(struct era *era)
 {
 	atomic_set(&era->suspended, 1);
-	flush_workqueue(era->wq);
+	drain_workqueue(era->wq);
 }
 
 /*----------------------------------------------------------------
@@ -1570,6 +1570,12 @@ static void era_postsuspend(struct dm_target *ti)
 	}
 
 	stop_worker(era);
+
+	r = metadata_commit(era->md);
+	if (r) {
+		DMERR("%s: metadata_commit failed", __func__);
+		/* FIXME: fail mode */
+	}
 }
 
 static int era_preresume(struct dm_target *ti)
-- 
GitLab


From 78ccef91234ba331c04d71f3ecb1377451d21056 Mon Sep 17 00:00:00 2001
From: Mike Snitzer <snitzer@kernel.org>
Date: Tue, 21 Jun 2022 13:37:06 -0400
Subject: [PATCH 0930/1731] dm: do not return early from dm_io_complete if
 BLK_STS_AGAIN without polling

Commit 5291984004edf ("dm: fix bio polling to handle possibile
BLK_STS_AGAIN") inadvertently introduced an early return from
dm_io_complete() without first queueing the bio to DM if BLK_STS_AGAIN
occurs and bio-polling is _not_ being used.

Fix this by only returning early from dm_io_complete() if the bio has
first been properly queued to DM. Otherwise, the bio will never finish
via bio_endio.

Fixes: 5291984004edf ("dm: fix bio polling to handle possibile BLK_STS_AGAIN")
Cc: stable@vger.kernel.org
Signed-off-by: Mike Snitzer <snitzer@kernel.org>
---
 drivers/md/dm.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/md/dm.c b/drivers/md/dm.c
index b6b25d319ef70..9ede55278eec4 100644
--- a/drivers/md/dm.c
+++ b/drivers/md/dm.c
@@ -939,9 +939,11 @@ static void dm_io_complete(struct dm_io *io)
 			if (io_error == BLK_STS_AGAIN) {
 				/* io_uring doesn't handle BLK_STS_AGAIN (yet) */
 				queue_io(md, bio);
+				return;
 			}
 		}
-		return;
+		if (io_error == BLK_STS_DM_REQUEUE)
+			return;
 	}
 
 	if (bio_is_flush_with_data(bio)) {
-- 
GitLab


From fc98eb494c4be6aed076c1ad21d46d5950415ca0 Mon Sep 17 00:00:00 2001
From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Date: Fri, 17 Jun 2022 14:20:32 -0700
Subject: [PATCH 0931/1731] drm/i915: Add global forcewake request to drpc

We have seen multiple RC6 issues where it is useful to know
which global forcewake bits are set. Add this to the 'drpc'
debugfs output.

v2: Review comments (Ashutosh)

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220617212032.34577-1-vinay.belgaumkar@intel.com
---
 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 90a4408650378..40bdd4cb629fe 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -100,14 +100,16 @@ static int vlv_drpc(struct seq_file *m)
 {
 	struct intel_gt *gt = m->private;
 	struct intel_uncore *uncore = gt->uncore;
-	u32 rcctl1, pw_status;
+	u32 rcctl1, pw_status, mt_fwake_req;
 
+	mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
 	pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS);
 	rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
 
 	seq_printf(m, "RC6 Enabled: %s\n",
 		   str_yes_no(rcctl1 & (GEN7_RC_CTL_TO_MODE |
 					GEN6_RC_CTL_EI_MODE(1))));
+	seq_printf(m, "Multi-threaded Forcewake Request: 0x%x\n", mt_fwake_req);
 	seq_printf(m, "Render Power Well: %s\n",
 		   (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
 	seq_printf(m, "Media Power Well: %s\n",
@@ -124,9 +126,10 @@ static int gen6_drpc(struct seq_file *m)
 	struct intel_gt *gt = m->private;
 	struct drm_i915_private *i915 = gt->i915;
 	struct intel_uncore *uncore = gt->uncore;
-	u32 gt_core_status, rcctl1, rc6vids = 0;
+	u32 gt_core_status, mt_fwake_req, rcctl1, rc6vids = 0;
 	u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
 
+	mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
 	gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
 
 	rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
@@ -178,6 +181,7 @@ static int gen6_drpc(struct seq_file *m)
 
 	seq_printf(m, "Core Power Down: %s\n",
 		   str_yes_no(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
+	seq_printf(m, "Multi-threaded Forcewake Request: 0x%x\n", mt_fwake_req);
 	if (GRAPHICS_VER(i915) >= 9) {
 		seq_printf(m, "Render Power Well: %s\n",
 			   (gen9_powergate_status &
-- 
GitLab


From d4ea6f6373ef56d1d795a24f1f5874f4a6019199 Mon Sep 17 00:00:00 2001
From: Marcin Szycik <marcin.szycik@linux.intel.com>
Date: Mon, 9 May 2022 21:01:18 +0200
Subject: [PATCH 0932/1731] ice: ignore protocol field in GTP offload

Commit 34a897758efe ("ice: Add support for inner etype in switchdev")
added the ability to match on inner ethertype. A side effect of that change
is that it is now impossible to add some filters for protocols which do not
contain inner ethtype field. tc requires the protocol field to be specified
when providing certain other options, e.g. src_ip. This is a problem in
case of GTP - when user wants to specify e.g. src_ip, they also need to
specify protocol in tc command (otherwise tc fails with: Illegal "src_ip").
Because GTP is a tunnel, the protocol field is treated as inner protocol.
GTP does not contain inner ethtype field and the filter cannot be added.

To fix this, ignore the ethertype field in case of GTP filters.

Fixes: 9a225f81f540 ("ice: Support GTP-U and GTP-C offload in switchdev")
Signed-off-by: Marcin Szycik <marcin.szycik@linux.intel.com>
Tested-by: Sandeep Penigalapati <sandeep.penigalapati@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
---
 drivers/net/ethernet/intel/ice/ice_tc_lib.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/intel/ice/ice_tc_lib.c b/drivers/net/ethernet/intel/ice/ice_tc_lib.c
index 0a0c55fb86993..b677c62a244ca 100644
--- a/drivers/net/ethernet/intel/ice/ice_tc_lib.c
+++ b/drivers/net/ethernet/intel/ice/ice_tc_lib.c
@@ -993,7 +993,9 @@ ice_parse_cls_flower(struct net_device *filter_dev, struct ice_vsi *vsi,
 		n_proto_key = ntohs(match.key->n_proto);
 		n_proto_mask = ntohs(match.mask->n_proto);
 
-		if (n_proto_key == ETH_P_ALL || n_proto_key == 0) {
+		if (n_proto_key == ETH_P_ALL || n_proto_key == 0 ||
+		    fltr->tunnel_type == TNL_GTPU ||
+		    fltr->tunnel_type == TNL_GTPC) {
 			n_proto_key = 0;
 			n_proto_mask = 0;
 		} else {
-- 
GitLab


From 202773260023b56e868d09d13d3a417028f1ff5b Mon Sep 17 00:00:00 2001
From: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Date: Fri, 17 Jun 2022 15:24:02 +0300
Subject: [PATCH 0933/1731] PM: hibernate: Use kernel_can_power_off()

Use new kernel_can_power_off() API instead of legacy pm_power_off global
variable to fix regressed hibernation to disk where machine no longer
powers off when it should because ACPI power driver transitioned to the
new sys-off based API and it doesn't use pm_power_off anymore.

Fixes: 98f30d0ecf79 ("ACPI: power: Switch to sys-off handler API")
Tested-by: Ken Moffat <zarniwhoop@ntlworld.com>
Reported-by: Ken Moffat <zarniwhhop@ntlworld.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 kernel/power/hibernate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/power/hibernate.c b/kernel/power/hibernate.c
index 20a66bf9f4659..89c71fce225dd 100644
--- a/kernel/power/hibernate.c
+++ b/kernel/power/hibernate.c
@@ -665,7 +665,7 @@ static void power_down(void)
 		hibernation_platform_enter();
 		fallthrough;
 	case HIBERNATION_SHUTDOWN:
-		if (pm_power_off)
+		if (kernel_can_power_off())
 			kernel_power_off();
 		break;
 	}
-- 
GitLab


From f6f0dab5efe4fcabe726f9218a0b3000fee0fa8a Mon Sep 17 00:00:00 2001
From: Ben Widawsky <ben.widawsky@intel.com>
Date: Fri, 20 May 2022 11:00:59 -0700
Subject: [PATCH 0934/1731] MAINTAINERS: Update Ben's email address

I'm leaving Intel. Update email address to korg and add .mailmap
entries. For now, I will be taking a reduced role in CXL development,
but I still plan to spend time working on it, and I can still serve as a
good substitute if needed for maintainer responsibilities (that may
change in the future).

Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://lore.kernel.org/r/20220520180059.632054-1-bwidawsk@kernel.org
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
 .mailmap    | 3 +++
 MAINTAINERS | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/.mailmap b/.mailmap
index 825fae8e6b7bd..ae8fa1af6b5e5 100644
--- a/.mailmap
+++ b/.mailmap
@@ -62,6 +62,9 @@ Bart Van Assche <bvanassche@acm.org> <bart.vanassche@sandisk.com>
 Bart Van Assche <bvanassche@acm.org> <bart.vanassche@wdc.com>
 Ben Gardner <bgardner@wabtec.com>
 Ben M Cahill <ben.m.cahill@intel.com>
+Ben Widawsky <bwidawsk@kernel.org> <ben@bwidawsk.net>
+Ben Widawsky <bwidawsk@kernel.org> <ben.widawsky@intel.com>
+Ben Widawsky <bwidawsk@kernel.org> <benjamin.widawsky@intel.com>
 Björn Steinbrink <B.Steinbrink@gmx.de>
 Björn Töpel <bjorn@kernel.org> <bjorn.topel@gmail.com>
 Björn Töpel <bjorn@kernel.org> <bjorn.topel@intel.com>
diff --git a/MAINTAINERS b/MAINTAINERS
index 3cf9842d9233c..54fa6e2059def 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5009,7 +5009,7 @@ COMPUTE EXPRESS LINK (CXL)
 M:	Alison Schofield <alison.schofield@intel.com>
 M:	Vishal Verma <vishal.l.verma@intel.com>
 M:	Ira Weiny <ira.weiny@intel.com>
-M:	Ben Widawsky <ben.widawsky@intel.com>
+M:	Ben Widawsky <bwidawsk@kernel.org>
 M:	Dan Williams <dan.j.williams@intel.com>
 L:	linux-cxl@vger.kernel.org
 S:	Maintained
-- 
GitLab


From 3578dc90013b1fa20da996cdadd8515802716132 Mon Sep 17 00:00:00 2001
From: Wojciech Drewek <wojciech.drewek@intel.com>
Date: Mon, 23 May 2022 11:41:55 +0200
Subject: [PATCH 0935/1731] ice: Fix switchdev rules book keeping

Adding two filters with same matching criteria ends up with
one rule in hardware with act = ICE_FWD_TO_VSI_LIST.
In order to remove them properly we have to keep the
information about vsi handle which is used in VSI bitmap
(ice_adv_fltr_mgmt_list_entry::vsi_list_info::vsi_map).

Fixes: 0d08a441fb1a ("ice: ndo_setup_tc implementation for PF")
Reported-by: Sridhar Samudrala <sridhar.samudrala@intel.com>
Signed-off-by: Wojciech Drewek <wojciech.drewek@intel.com>
Tested-by: Sandeep Penigalapati <sandeep.penigalapati@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
---
 drivers/net/ethernet/intel/ice/ice_tc_lib.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/ethernet/intel/ice/ice_tc_lib.c b/drivers/net/ethernet/intel/ice/ice_tc_lib.c
index b677c62a244ca..b803f2ab3cc76 100644
--- a/drivers/net/ethernet/intel/ice/ice_tc_lib.c
+++ b/drivers/net/ethernet/intel/ice/ice_tc_lib.c
@@ -524,6 +524,7 @@ ice_eswitch_add_tc_fltr(struct ice_vsi *vsi, struct ice_tc_flower_fltr *fltr)
 	 */
 	fltr->rid = rule_added.rid;
 	fltr->rule_id = rule_added.rule_id;
+	fltr->dest_id = rule_added.vsi_handle;
 
 exit:
 	kfree(list);
-- 
GitLab


From 3748d2185ac4c2c6f80989672253aad909ecaf95 Mon Sep 17 00:00:00 2001
From: Liang He <windhl@126.com>
Date: Tue, 21 Jun 2022 23:41:25 +0800
Subject: [PATCH 0936/1731] mips: lantiq: Add missing of_node_put() in irq.c

In icu_of_init(), of_find_compatible_node() will return a node
pointer with refcount incremented. We should use of_node_put()
when it is not used anymore.

Signed-off-by: Liang He <windhl@126.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
 arch/mips/lantiq/irq.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index b732495f138af..20622bf0a9b3d 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -408,6 +408,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
 		if (!ltq_eiu_membase)
 			panic("Failed to remap eiu memory");
 	}
+	of_node_put(eiu_node);
 
 	return 0;
 }
-- 
GitLab


From c3d184c83ff4b80167e34edfc3d21df424bf27ff Mon Sep 17 00:00:00 2001
From: Anatolii Gerasymenko <anatolii.gerasymenko@intel.com>
Date: Mon, 20 Jun 2022 09:47:05 +0200
Subject: [PATCH 0937/1731] ice: ethtool: advertise 1000M speeds properly

In current implementation ice_update_phy_type enables all link modes
for selected speed. This approach doesn't work for 1000M speeds,
because both copper (1000baseT) and optical (1000baseX) standards
cannot be enabled at once.

Fix this, by adding the function `ice_set_phy_type_from_speed()`
for 1000M speeds.

Fixes: 48cb27f2fd18 ("ice: Implement handlers for ethtool PHY/link operations")
Signed-off-by: Anatolii Gerasymenko <anatolii.gerasymenko@intel.com>
Tested-by: Gurucharan <gurucharanx.g@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
---
 drivers/net/ethernet/intel/ice/ice_ethtool.c | 39 +++++++++++++++++++-
 1 file changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/intel/ice/ice_ethtool.c b/drivers/net/ethernet/intel/ice/ice_ethtool.c
index 1e71b70f0e523..8078618ce1b61 100644
--- a/drivers/net/ethernet/intel/ice/ice_ethtool.c
+++ b/drivers/net/ethernet/intel/ice/ice_ethtool.c
@@ -2189,6 +2189,42 @@ ice_setup_autoneg(struct ice_port_info *p, struct ethtool_link_ksettings *ks,
 	return err;
 }
 
+/**
+ * ice_set_phy_type_from_speed - set phy_types based on speeds
+ * and advertised modes
+ * @ks: ethtool link ksettings struct
+ * @phy_type_low: pointer to the lower part of phy_type
+ * @phy_type_high: pointer to the higher part of phy_type
+ * @adv_link_speed: targeted link speeds bitmap
+ */
+static void
+ice_set_phy_type_from_speed(const struct ethtool_link_ksettings *ks,
+			    u64 *phy_type_low, u64 *phy_type_high,
+			    u16 adv_link_speed)
+{
+	/* Handle 1000M speed in a special way because ice_update_phy_type
+	 * enables all link modes, but having mixed copper and optical
+	 * standards is not supported.
+	 */
+	adv_link_speed &= ~ICE_AQ_LINK_SPEED_1000MB;
+
+	if (ethtool_link_ksettings_test_link_mode(ks, advertising,
+						  1000baseT_Full))
+		*phy_type_low |= ICE_PHY_TYPE_LOW_1000BASE_T |
+				 ICE_PHY_TYPE_LOW_1G_SGMII;
+
+	if (ethtool_link_ksettings_test_link_mode(ks, advertising,
+						  1000baseKX_Full))
+		*phy_type_low |= ICE_PHY_TYPE_LOW_1000BASE_KX;
+
+	if (ethtool_link_ksettings_test_link_mode(ks, advertising,
+						  1000baseX_Full))
+		*phy_type_low |= ICE_PHY_TYPE_LOW_1000BASE_SX |
+				 ICE_PHY_TYPE_LOW_1000BASE_LX;
+
+	ice_update_phy_type(phy_type_low, phy_type_high, adv_link_speed);
+}
+
 /**
  * ice_set_link_ksettings - Set Speed and Duplex
  * @netdev: network interface device structure
@@ -2320,7 +2356,8 @@ ice_set_link_ksettings(struct net_device *netdev,
 		adv_link_speed = curr_link_speed;
 
 	/* Convert the advertise link speeds to their corresponded PHY_TYPE */
-	ice_update_phy_type(&phy_type_low, &phy_type_high, adv_link_speed);
+	ice_set_phy_type_from_speed(ks, &phy_type_low, &phy_type_high,
+				    adv_link_speed);
 
 	if (!autoneg_changed && adv_link_speed == curr_link_speed) {
 		netdev_info(netdev, "Nothing changed, exiting without setting anything.\n");
-- 
GitLab


From db9a3a35d31ea337331f0e6e07e04bcd52642894 Mon Sep 17 00:00:00 2001
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: Thu, 9 Jun 2022 14:45:19 +0100
Subject: [PATCH 0938/1731] cxl: Fix cleanup of port devices on failure to
 probe driver.

The device is created, and then there is a check if a driver succesfully
bound to it. In event of failing the bind (e.g. failure in cxl_port_probe())
the device is left registered. When a bus rescan later occurs, fresh
devices are created leading to a multiple device representing the same
underlying hardware. Bad things may follow and at very least we have far too many
devices.

Fix by ensuring autoremove is registered if the device create succeeds,
but doesn't depend on sucessful binding to a driver.

Bug was observed as side effect of incorrect ownership in
[PATCH v9 6/9] cxl/port: Read CDAT table
but will result from any failure to in cxl_port_probe().

Fixes: 8dd2bc0f8e02 ("cxl/mem: Add the cxl_mem driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Link: https://lore.kernel.org/r/20220609134519.11668-1-Jonathan.Cameron@huawei.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
 drivers/cxl/mem.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
index c310f1fd3db02..a979d0b484d56 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/mem.c
@@ -29,6 +29,7 @@ static int create_endpoint(struct cxl_memdev *cxlmd,
 {
 	struct cxl_dev_state *cxlds = cxlmd->cxlds;
 	struct cxl_port *endpoint;
+	int rc;
 
 	endpoint = devm_cxl_add_port(&parent_port->dev, &cxlmd->dev,
 				     cxlds->component_reg_phys, parent_port);
@@ -37,13 +38,17 @@ static int create_endpoint(struct cxl_memdev *cxlmd,
 
 	dev_dbg(&cxlmd->dev, "add: %s\n", dev_name(&endpoint->dev));
 
+	rc = cxl_endpoint_autoremove(cxlmd, endpoint);
+	if (rc)
+		return rc;
+
 	if (!endpoint->dev.driver) {
 		dev_err(&cxlmd->dev, "%s failed probe\n",
 			dev_name(&endpoint->dev));
 		return -ENXIO;
 	}
 
-	return cxl_endpoint_autoremove(cxlmd, endpoint);
+	return 0;
 }
 
 static void enable_suspend(void *data)
-- 
GitLab


From 8ae3cebc1704b9a3ab8398dc7820c37183026bbc Mon Sep 17 00:00:00 2001
From: Ben Widawsky <ben.widawsky@intel.com>
Date: Fri, 4 Mar 2022 13:36:45 -0800
Subject: [PATCH 0939/1731] cxl/core: Use is_endpoint_decoder

Save some characters and directly check decoder type rather than port
type. There's no need to check if the port is an endpoint port since, by
this point, cxl_endpoint_decoder_alloc() has a specified type.

Reviewed by: Adam Manzanares <a.manzanares@samsung.com>
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
 drivers/cxl/core/hdm.c  | 2 +-
 drivers/cxl/core/port.c | 2 +-
 drivers/cxl/cxl.h       | 1 +
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index 0e89a7a932d40..bfc8ee876278c 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -197,7 +197,7 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
 	else
 		cxld->target_type = CXL_DECODER_ACCELERATOR;
 
-	if (is_cxl_endpoint(to_cxl_port(cxld->dev.parent)))
+	if (is_endpoint_decoder(&cxld->dev))
 		return 0;
 
 	target_list.value =
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index ea60abda65006..dbce99bdffabc 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -272,7 +272,7 @@ static const struct device_type cxl_decoder_root_type = {
 	.groups = cxl_decoder_root_attribute_groups,
 };
 
-static bool is_endpoint_decoder(struct device *dev)
+bool is_endpoint_decoder(struct device *dev)
 {
 	return dev->type == &cxl_decoder_endpoint_type;
 }
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 140dc3278cde1..6799b27c7db20 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -340,6 +340,7 @@ struct cxl_dport *cxl_find_dport_by_dev(struct cxl_port *port,
 
 struct cxl_decoder *to_cxl_decoder(struct device *dev);
 bool is_root_decoder(struct device *dev);
+bool is_endpoint_decoder(struct device *dev);
 bool is_cxl_decoder(struct device *dev);
 struct cxl_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
 					   unsigned int nr_targets);
-- 
GitLab


From 8a66487506161dbc1d22fd154d2de0244e232040 Mon Sep 17 00:00:00 2001
From: Alison Schofield <alison.schofield@intel.com>
Date: Fri, 25 Feb 2022 14:14:56 -0800
Subject: [PATCH 0940/1731] cxl/mbox: Use __le32 in get,set_lsa mailbox
 structures

CXL specification defines these as little endian.

Fixes: 60b8f17215de ("cxl/pmem: Translate NVDIMM label commands to CXL label commands")
Reported-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Link: https://lore.kernel.org/r/20220225221456.1025635-1-alison.schofield@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
 drivers/cxl/cxlmem.h | 8 ++++----
 drivers/cxl/pmem.c   | 6 +++---
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 60d10ee1e7fcd..7df0b053373a3 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -300,13 +300,13 @@ struct cxl_mbox_identify {
 } __packed;
 
 struct cxl_mbox_get_lsa {
-	u32 offset;
-	u32 length;
+	__le32 offset;
+	__le32 length;
 } __packed;
 
 struct cxl_mbox_set_lsa {
-	u32 offset;
-	u32 reserved;
+	__le32 offset;
+	__le32 reserved;
 	u8 data[];
 } __packed;
 
diff --git a/drivers/cxl/pmem.c b/drivers/cxl/pmem.c
index bbeef91e637e9..0aaa70b4e0f71 100644
--- a/drivers/cxl/pmem.c
+++ b/drivers/cxl/pmem.c
@@ -108,8 +108,8 @@ static int cxl_pmem_get_config_data(struct cxl_dev_state *cxlds,
 		return -EINVAL;
 
 	get_lsa = (struct cxl_mbox_get_lsa) {
-		.offset = cmd->in_offset,
-		.length = cmd->in_length,
+		.offset = cpu_to_le32(cmd->in_offset),
+		.length = cpu_to_le32(cmd->in_length),
 	};
 
 	rc = cxl_mbox_send_cmd(cxlds, CXL_MBOX_OP_GET_LSA, &get_lsa,
@@ -139,7 +139,7 @@ static int cxl_pmem_set_config_data(struct cxl_dev_state *cxlds,
 		return -ENOMEM;
 
 	*set_lsa = (struct cxl_mbox_set_lsa) {
-		.offset = cmd->in_offset,
+		.offset = cpu_to_le32(cmd->in_offset),
 	};
 	memcpy(set_lsa->data, cmd->in_buf, cmd->in_length);
 
-- 
GitLab


From 4ed49c954e35559cb4a34ba049a15f54ec7fccf6 Mon Sep 17 00:00:00 2001
From: Ruijing Dong <ruijing.dong@amd.com>
Date: Tue, 31 May 2022 14:18:25 -0400
Subject: [PATCH 0941/1731] drm/amdgpu/vcn: add unified queue ib test

- add unified queue headers
- add unified queue ib tests

Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 102 +++++++++++++++++++++++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |   1 +
 2 files changed, 100 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index aa7acfabf360b..e62ff7db4736b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -329,6 +329,18 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
 	return 0;
 }
 
+/* from vcn4 and above, only unified queue is used */
+bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring)
+{
+	struct amdgpu_device *adev = ring->adev;
+	bool ret = false;
+
+	if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0))
+		ret = true;
+
+	return ret;
+}
+
 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)
 {
 	bool ret = false;
@@ -718,19 +730,55 @@ error:
 	return r;
 }
 
+static uint32_t * amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib,
+					  uint32_t ib_pack_in_dw, bool enc)
+{
+	uint32_t *ib_checksum;
+
+	ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */
+	ib->ptr[ib->length_dw++] = 0x30000002;
+	ib_checksum = &ib->ptr[ib->length_dw++];
+	ib->ptr[ib->length_dw++] = ib_pack_in_dw;
+
+	ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */
+	ib->ptr[ib->length_dw++] = 0x30000001;
+	ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3;
+	ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t);
+
+	return ib_checksum;
+}
+
+static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum,
+				        uint32_t ib_pack_in_dw)
+{
+	uint32_t i;
+	uint32_t checksum = 0;
+
+	for (i = 0; i < ib_pack_in_dw; i++)
+		checksum += *(*ib_checksum + 2 + i);
+
+	**ib_checksum = checksum;
+}
+
 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
 				      struct amdgpu_ib *ib_msg,
 				      struct dma_fence **fence)
 {
 	struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
-	const unsigned int ib_size_dw = 64;
+	unsigned int ib_size_dw = 64;
 	struct amdgpu_device *adev = ring->adev;
 	struct dma_fence *f = NULL;
 	struct amdgpu_job *job;
 	struct amdgpu_ib *ib;
 	uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
+	bool sq = amdgpu_vcn_using_unified_queue(ring);
+	uint32_t *ib_checksum;
+	uint32_t ib_pack_in_dw;
 	int i, r;
 
+	if (sq)
+		ib_size_dw += 8;
+
 	r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4,
 				AMDGPU_IB_POOL_DIRECT, &job);
 	if (r)
@@ -739,6 +787,13 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
 	ib = &job->ibs[0];
 	ib->length_dw = 0;
 
+	/* single queue headers */
+	if (sq) {
+		ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t)
+			                     + 4 + 2; /* engine info + decoding ib in dw */
+		ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false);
+	}
+
 	ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
 	ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER);
 	decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]);
@@ -752,6 +807,9 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
 	for (i = ib->length_dw; i < ib_size_dw; ++i)
 		ib->ptr[i] = 0x0;
 
+	if (sq)
+		amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw);
+
 	r = amdgpu_job_submit_direct(job, ring, &f);
 	if (r)
 		goto err_free;
@@ -838,13 +896,18 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
 					 struct amdgpu_ib *ib_msg,
 					 struct dma_fence **fence)
 {
-	const unsigned ib_size_dw = 16;
+	unsigned ib_size_dw = 16;
 	struct amdgpu_job *job;
 	struct amdgpu_ib *ib;
 	struct dma_fence *f = NULL;
+	uint32_t *ib_checksum = NULL;
 	uint64_t addr;
+	bool sq = amdgpu_vcn_using_unified_queue(ring);
 	int i, r;
 
+	if (sq)
+		ib_size_dw += 8;
+
 	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
 					AMDGPU_IB_POOL_DIRECT, &job);
 	if (r)
@@ -854,6 +917,10 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
 	addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
 
 	ib->length_dw = 0;
+
+	if (sq)
+		ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
+
 	ib->ptr[ib->length_dw++] = 0x00000018;
 	ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 	ib->ptr[ib->length_dw++] = handle;
@@ -873,6 +940,9 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
 	for (i = ib->length_dw; i < ib_size_dw; ++i)
 		ib->ptr[i] = 0x0;
 
+	if (sq)
+		amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
+
 	r = amdgpu_job_submit_direct(job, ring, &f);
 	if (r)
 		goto err;
@@ -892,13 +962,18 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
 					  struct amdgpu_ib *ib_msg,
 					  struct dma_fence **fence)
 {
-	const unsigned ib_size_dw = 16;
+	unsigned ib_size_dw = 16;
 	struct amdgpu_job *job;
 	struct amdgpu_ib *ib;
 	struct dma_fence *f = NULL;
+	uint32_t *ib_checksum = NULL;
 	uint64_t addr;
+	bool sq = amdgpu_vcn_using_unified_queue(ring);
 	int i, r;
 
+	if (sq)
+		ib_size_dw += 8;
+
 	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
 					AMDGPU_IB_POOL_DIRECT, &job);
 	if (r)
@@ -908,6 +983,10 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
 	addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
 
 	ib->length_dw = 0;
+
+	if (sq)
+		ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
+
 	ib->ptr[ib->length_dw++] = 0x00000018;
 	ib->ptr[ib->length_dw++] = 0x00000001;
 	ib->ptr[ib->length_dw++] = handle;
@@ -927,6 +1006,9 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
 	for (i = ib->length_dw; i < ib_size_dw; ++i)
 		ib->ptr[i] = 0x0;
 
+	if (sq)
+		amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
+
 	r = amdgpu_job_submit_direct(job, ring, &f);
 	if (r)
 		goto err;
@@ -977,6 +1059,20 @@ error:
 	return r;
 }
 
+int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+{
+	long r;
+
+	r = amdgpu_vcn_enc_ring_test_ib(ring, timeout);
+	if (r)
+		goto error;
+
+	r =  amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout);
+
+error:
+	return r;
+}
+
 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring)
 {
 	switch(ring) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 6f90fcee0f9c9..60c608144480a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -364,6 +364,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring);
 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout);
+int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 
 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
-- 
GitLab


From bb4f196b47b6554ba89f02ec60246f0c643a4bf8 Mon Sep 17 00:00:00 2001
From: Ruijing Dong <ruijing.dong@amd.com>
Date: Tue, 31 May 2022 14:20:42 -0400
Subject: [PATCH 0942/1731] drm/amdgpu/vcn: support unified queue only in vcn4

- remove multiple queue support
- add unified queue related functions

Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 563 +++++++-------------------
 1 file changed, 140 insertions(+), 423 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 9119e966ffff1..d6f134ef9633d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -29,7 +29,6 @@
 #include "soc15d.h"
 #include "soc15_hw_ip.h"
 #include "vcn_v2_0.h"
-#include "vcn_sw_ring.h"
 
 #include "vcn/vcn_4_0_0_offset.h"
 #include "vcn/vcn_4_0_0_sh_mask.h"
@@ -45,15 +44,12 @@
 #define VCN_VID_SOC_ADDRESS_2_0							0x1fb00
 #define VCN1_VID_SOC_ADDRESS_3_0						0x48300
 
-bool unifiedQ_enabled = false;
-
 static int amdgpu_ih_clientid_vcns[] = {
 	SOC15_IH_CLIENTID_VCN,
 	SOC15_IH_CLIENTID_VCN1
 };
 
-static void vcn_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev);
-static void vcn_v4_0_set_enc_ring_funcs(struct amdgpu_device *adev);
+static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev);
 static int vcn_v4_0_set_powergating_state(void *handle,
         enum amd_powergating_state state);
@@ -71,36 +67,15 @@ static int vcn_v4_0_early_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	if (unifiedQ_enabled) {
-		adev->vcn.num_vcn_inst = 1;
-		adev->vcn.num_enc_rings = 1;
-	} else {
-		adev->vcn.num_enc_rings = 2;
-	}
-
-	if (!unifiedQ_enabled)
-		vcn_v4_0_set_dec_ring_funcs(adev);
+	/* re-use enc ring as unified ring */
+	adev->vcn.num_enc_rings = 1;
 
-	vcn_v4_0_set_enc_ring_funcs(adev);
+	vcn_v4_0_set_unified_ring_funcs(adev);
 	vcn_v4_0_set_irq_funcs(adev);
 
 	return 0;
 }
 
-static void amdgpu_vcn_setup_unified_queue_ucode(struct amdgpu_device *adev)
-{
-	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
-		const struct common_firmware_header *hdr;
-
-		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
-		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
-		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
-		adev->firmware.fw_size +=
-			ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
-		DRM_INFO("PSP loading VCN firmware\n");
-	}
-}
-
 /**
  * vcn_v4_0_sw_init - sw init for VCN block
  *
@@ -111,17 +86,14 @@ static void amdgpu_vcn_setup_unified_queue_ucode(struct amdgpu_device *adev)
 static int vcn_v4_0_sw_init(void *handle)
 {
 	struct amdgpu_ring *ring;
-	int i, j, r;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int i, r;
 
 	r = amdgpu_vcn_sw_init(adev);
 	if (r)
 		return r;
 
-	if (unifiedQ_enabled)
-		amdgpu_vcn_setup_unified_queue_ucode(adev);
-	else
-		amdgpu_vcn_setup_ucode(adev);
+	amdgpu_vcn_setup_ucode(adev);
 
 	r = amdgpu_vcn_resume(adev);
 	if (r)
@@ -129,81 +101,40 @@ static int vcn_v4_0_sw_init(void *handle)
 
 	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 		volatile struct amdgpu_vcn4_fw_shared *fw_shared;
+
 		if (adev->vcn.harvest_config & (1 << i))
 			continue;
-		/* VCN DEC TRAP */
+
+		atomic_set(&adev->vcn.inst[i].sched_score, 0);
+
+		/* VCN UNIFIED TRAP */
 		r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
-				VCN_4_0__SRCID__UVD_TRAP, &adev->vcn.inst[i].irq);
+				VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
 		if (r)
 			return r;
 
-		atomic_set(&adev->vcn.inst[i].sched_score, 0);
-		if (!unifiedQ_enabled) {
-			ring = &adev->vcn.inst[i].ring_dec;
-			ring->use_doorbell = true;
-
-			/* VCN4 doorbell layout
-			 * 1: VCN_JPEG_DB_CTRL UVD_JRBC_RB_WPTR; (jpeg)
-			 * 2: VCN_RB1_DB_CTRL  UVD_RB_WPTR; (decode/encode for unified queue)
-			 * 3: VCN_RB2_DB_CTRL  UVD_RB_WPTR2; (encode only for swqueue)
-			 * 4: VCN_RB3_DB_CTRL  UVD_RB_WPTR3; (Reserved)
-			 * 5: VCN_RB4_DB_CTRL  UVD_RB_WPTR4; (decode only for swqueue)
-			 */
-
-			ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1)
-						+ 5 + 8 * i;
-
-			sprintf(ring->name, "vcn_dec_%d", i);
-			r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
-					     AMDGPU_RING_PRIO_DEFAULT,
-					     &adev->vcn.inst[i].sched_score);
-			if (r)
-				return r;
-		}
-		for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
-			/* VCN ENC TRAP */
-			r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
-				j + VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
-			if (r)
-				return r;
-
-			ring = &adev->vcn.inst[i].ring_enc[j];
-			ring->use_doorbell = true;
-
-			ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i;
-
-			if (unifiedQ_enabled) {
-				sprintf(ring->name, "vcn_unified%d", i);
-				r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
-				     AMDGPU_RING_PRIO_DEFAULT, NULL);
-			} else {
-				enum amdgpu_ring_priority_level hw_prio;
+		ring = &adev->vcn.inst[i].ring_enc[0];
+		ring->use_doorbell = true;
+		ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i;
 
-				hw_prio = amdgpu_vcn_get_enc_ring_prio(j);
-				sprintf(ring->name, "vcn_enc_%d.%d", i, j);
-				r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
-					     hw_prio, &adev->vcn.inst[i].sched_score);
-			}
-			if (r)
-				return r;
-		}
+		sprintf(ring->name, "vcn_unified_%d", i);
 
-		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
-		fw_shared->present_flag_0 = 0;
+		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
+				  AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
+		if (r)
+			return r;
 
-		if (unifiedQ_enabled) {
-			fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
-			fw_shared->sq.is_enabled = 1;
-		}
+		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
+		fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
+		fw_shared->sq.is_enabled = 1;
 
 		if (amdgpu_vcnfw_log)
 			amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
 	}
 
-	if (!unifiedQ_enabled) {
-		if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
-			adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode;
-	}
+	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
+		adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode;
+
 	return 0;
 }
 
@@ -220,19 +151,19 @@ static int vcn_v4_0_sw_fini(void *handle)
 	int i, r, idx;
 
 	if (drm_dev_enter(&adev->ddev, &idx)) {
-                for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
-                        volatile struct amdgpu_vcn4_fw_shared *fw_shared;
+		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+			volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 
-                        if (adev->vcn.harvest_config & (1 << i))
-                                continue;
+			if (adev->vcn.harvest_config & (1 << i))
+				continue;
 
-                        fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
-                        fw_shared->present_flag_0 = 0;
-                        fw_shared->sq.is_enabled = 0;
-                }
+			fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
+			fw_shared->present_flag_0 = 0;
+			fw_shared->sq.is_enabled = 0;
+		}
 
-                drm_dev_exit(idx);
-        }
+		drm_dev_exit(idx);
+	}
 
 	r = amdgpu_vcn_suspend(adev);
 	if (r)
@@ -254,15 +185,13 @@ static int vcn_v4_0_hw_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	struct amdgpu_ring *ring;
-	int i, j, r;
+	int i, r;
 
 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 		if (adev->vcn.harvest_config & (1 << i))
 			continue;
-		if (unifiedQ_enabled)
-			ring = &adev->vcn.inst[i].ring_enc[0];
-		else
-			ring = &adev->vcn.inst[i].ring_dec;
+
+		ring = &adev->vcn.inst[i].ring_enc[0];
 
 		adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 				((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i);
@@ -270,13 +199,6 @@ static int vcn_v4_0_hw_init(void *handle)
 		r = amdgpu_ring_test_helper(ring);
 		if (r)
 			goto done;
-
-		for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
-			ring = &adev->vcn.inst[i].ring_enc[j];
-			r = amdgpu_ring_test_helper(ring);
-			if (r)
-				goto done;
-		}
 	}
 
 done:
@@ -464,7 +386,6 @@ static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
 		WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 			VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0),
 			AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
-
 	}
 
 	if (!indirect)
@@ -888,7 +809,6 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
 	volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
 	struct amdgpu_ring *ring;
 	uint32_t tmp;
-	int i;
 
 	/* disable register anti-hang mechanism */
 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,
@@ -974,74 +894,32 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
 			(uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
 				(uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
 
-	if (unifiedQ_enabled) {
-		ring = &adev->vcn.inst[inst_idx].ring_enc[0];
-		fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
-	} else
-		ring = &adev->vcn.inst[inst_idx].ring_dec;
-
-	WREG32_SOC15(VCN, inst_idx, regVCN_RB4_DB_CTRL,
-		ring->doorbell_index << VCN_RB4_DB_CTRL__OFFSET__SHIFT |
-		VCN_RB4_DB_CTRL__EN_MASK);
-
-	/* program the RB_BASE for ring buffer */
-	WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO4,
-		lower_32_bits(ring->gpu_addr));
-	WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI4,
-		upper_32_bits(ring->gpu_addr));
+	ring = &adev->vcn.inst[inst_idx].ring_enc[0];
 
-	WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE4, ring->ring_size / sizeof(uint32_t));
+	WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr);
+	WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+	WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4);
 
-	/* reseting ring, fw should not check RB ring */
 	tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
-	tmp &= ~(VCN_RB_ENABLE__RB4_EN_MASK);
+	tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
 	WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
+	fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
+	WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0);
+	WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0);
 
-	/* Initialize the ring buffer's read and write pointers */
-	tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR4);
-	WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR4, tmp);
-	ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR4);
+	tmp= RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
+	WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);
+	ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
 
 	tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
-	tmp |= VCN_RB_ENABLE__RB4_EN_MASK;
+	tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
 	WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
+	fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
 
-	WREG32_SOC15(VCN, inst_idx, regUVD_SCRATCH2, 0);
-
-	if (unifiedQ_enabled)
-		fw_shared->sq.queue_mode &= ~FW_QUEUE_RING_RESET;
-
-	for (i = 0; i < adev->vcn.num_enc_rings; i++) {
-		ring = &adev->vcn.inst[inst_idx].ring_enc[i];
-
-		if (i) {
-			ring = &adev->vcn.inst[inst_idx].ring_enc[1];
-
-			WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO2, ring->gpu_addr);
-			WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
-			WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE2, ring->ring_size / 4);
-			tmp= RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR2);
-			WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR2, tmp);
-			ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR2);
-
-			WREG32_SOC15(VCN, inst_idx, regVCN_RB2_DB_CTRL,
-				ring->doorbell_index << VCN_RB2_DB_CTRL__OFFSET__SHIFT |
-				VCN_RB2_DB_CTRL__EN_MASK);
-		} else {
-			ring = &adev->vcn.inst[inst_idx].ring_enc[0];
-
-			WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr);
-			WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
-			WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4);
-			tmp= RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
-			WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);
-			ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
+	WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL,
+			ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
+			VCN_RB1_DB_CTRL__EN_MASK);
 
-			WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL,
-				ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
-				VCN_RB1_DB_CTRL__EN_MASK);
-		}
-	}
 	return 0;
 }
 
@@ -1064,6 +942,8 @@ static int vcn_v4_0_start(struct amdgpu_device *adev)
 		amdgpu_dpm_enable_uvd(adev, true);
 
 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
+
 		if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
 			r = vcn_v4_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
 			continue;
@@ -1081,15 +961,15 @@ static int vcn_v4_0_start(struct amdgpu_device *adev)
 
 		/* enable VCPU clock */
 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
-			UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
+				UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
 
 		/* disable master interrupt */
 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,
-			~UVD_MASTINT_EN__VCPU_EN_MASK);
+				~UVD_MASTINT_EN__VCPU_EN_MASK);
 
 		/* enable LMI MC and UMC channels */
 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,
-			~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+				~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 
 		tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
 		tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
@@ -1099,10 +979,10 @@ static int vcn_v4_0_start(struct amdgpu_device *adev)
 		/* setup regUVD_LMI_CTRL */
 		tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);
 		WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |
-		UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
-		UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
-		UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
-		UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
+				UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
+				UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
+				UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
+				UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
 
 		/* setup regUVD_MPC_CNTL */
 		tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);
@@ -1112,37 +992,37 @@ static int vcn_v4_0_start(struct amdgpu_device *adev)
 
 		/* setup UVD_MPC_SET_MUXA0 */
 		WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,
-			((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
-			(0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
-			(0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
-			(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
+				((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
+				 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
+				 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
+				 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
 
 		/* setup UVD_MPC_SET_MUXB0 */
 		WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0,
-			((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
-			(0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
-			(0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
-			(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
+				((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
+				 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
+				 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
+				 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
 
 		/* setup UVD_MPC_SET_MUX */
 		WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,
-			((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
-			(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
-			(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
+				((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
+				 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
+				 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
 
 		vcn_v4_0_mc_resume(adev, i);
 
 		/* VCN global tiling registers */
 		WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
-			adev->gfx.config.gb_addr_config);
+				adev->gfx.config.gb_addr_config);
 
 		/* unblock VCPU register access */
 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,
-			~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+				~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
 
 		/* release VCPU reset to boot */
 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
-			~UVD_VCPU_CNTL__BLK_RST_MASK);
+				~UVD_VCPU_CNTL__BLK_RST_MASK);
 
 		for (j = 0; j < 10; ++j) {
 			uint32_t status;
@@ -1166,13 +1046,13 @@ static int vcn_v4_0_start(struct amdgpu_device *adev)
 				if (status & 2)
 					break;
 
-				dev_err(adev->dev, "VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i);
-					WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
-					UVD_VCPU_CNTL__BLK_RST_MASK,
-					~UVD_VCPU_CNTL__BLK_RST_MASK);
+				dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);
+				WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
+						UVD_VCPU_CNTL__BLK_RST_MASK,
+						~UVD_VCPU_CNTL__BLK_RST_MASK);
 				mdelay(10);
 				WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
-					~UVD_VCPU_CNTL__BLK_RST_MASK);
+						~UVD_VCPU_CNTL__BLK_RST_MASK);
 
 				mdelay(10);
 				r = -1;
@@ -1180,78 +1060,43 @@ static int vcn_v4_0_start(struct amdgpu_device *adev)
 		}
 
 		if (r) {
-			dev_err(adev->dev, "VCN[%d] decode not responding, giving up!!!\n", i);
+			dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i);
 			return r;
 		}
 
 		/* enable master interrupt */
 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),
-			UVD_MASTINT_EN__VCPU_EN_MASK,
-			~UVD_MASTINT_EN__VCPU_EN_MASK);
+				UVD_MASTINT_EN__VCPU_EN_MASK,
+				~UVD_MASTINT_EN__VCPU_EN_MASK);
 
 		/* clear the busy bit of VCN_STATUS */
 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
-			~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
-
-		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
-		if (unifiedQ_enabled) {
-			ring = &adev->vcn.inst[i].ring_enc[0];
-			fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
-		} else {
-			ring = &adev->vcn.inst[i].ring_dec;
+				~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
 
-			WREG32_SOC15(VCN, i, regVCN_RB4_DB_CTRL,
-				ring->doorbell_index << VCN_RB4_DB_CTRL__OFFSET__SHIFT |
-				VCN_RB4_DB_CTRL__EN_MASK);
-
-			/* program the RB_BASE for ring buffer */
-			WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO4,
-				lower_32_bits(ring->gpu_addr));
-			WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI4,
-				upper_32_bits(ring->gpu_addr));
-
-			WREG32_SOC15(VCN, i, regUVD_RB_SIZE4, ring->ring_size / sizeof(uint32_t));
-
-			/* resetting ring, fw should not check RB ring */
-			tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
-			tmp &= ~(VCN_RB_ENABLE__RB4_EN_MASK);
-			WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
+		ring = &adev->vcn.inst[i].ring_enc[0];
+		WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
+				ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
+				VCN_RB1_DB_CTRL__EN_MASK);
 
-			/* Initialize the ring buffer's read and write pointers */
-			tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR4);
-			WREG32_SOC15(VCN, i, regUVD_RB_WPTR4, tmp);
-			ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR4);
+		WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
+		WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+		WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
 
-			tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
-			tmp |= VCN_RB_ENABLE__RB4_EN_MASK;
-			WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
+		tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
+		tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
+		WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
+		fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
+		WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);
+		WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);
 
-			ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_RPTR4);
-		}
-		ring = &adev->vcn.inst[i].ring_enc[0];
-		WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
-			ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
-			VCN_RB1_DB_CTRL__EN_MASK);
 		tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
 		WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
 		ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);
-		WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
-		WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
-		WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
-		if (unifiedQ_enabled)
-			fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
-		else {
-			ring = &adev->vcn.inst[i].ring_enc[1];
-			WREG32_SOC15(VCN, i, regVCN_RB2_DB_CTRL,
-				ring->doorbell_index << VCN_RB2_DB_CTRL__OFFSET__SHIFT |
-				VCN_RB2_DB_CTRL__EN_MASK);
-			tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR2);
-			WREG32_SOC15(VCN, i, regUVD_RB_WPTR2, tmp);
-			ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR2);
-			WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO2, ring->gpu_addr);
-			WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
-			WREG32_SOC15(VCN, i, regUVD_RB_SIZE2, ring->ring_size / 4);
-		}
+
+		tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
+		tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
+		WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
+		fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
 	}
 
 	return 0;
@@ -1277,12 +1122,6 @@ static int vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
 	tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
 	SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);
 
-	tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR2);
-	SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
-
-	tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR4);
-	SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR4, tmp, 0xFFFFFFFF);
-
 	SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
 		UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
 
@@ -1301,10 +1140,14 @@ static int vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
  */
 static int vcn_v4_0_stop(struct amdgpu_device *adev)
 {
+	volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 	uint32_t tmp;
 	int i, r = 0;
 
 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
+		fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
+
 		if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
 			r = vcn_v4_0_stop_dpg_mode(adev, i);
 			continue;
@@ -1414,8 +1257,6 @@ static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,
 			/* unpause dpg, no need to wait */
 			reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
 			WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
-			SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1,
-				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
 		}
 		adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
 	}
@@ -1424,165 +1265,72 @@ static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,
 }
 
 /**
- * vcn_v4_0_dec_ring_get_rptr - get read pointer
+ * vcn_v4_0_unified_ring_get_rptr - get unified read pointer
  *
  * @ring: amdgpu_ring pointer
  *
- * Returns the current hardware read pointer
+ * Returns the current hardware unified read pointer
  */
-static uint64_t vcn_v4_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
+static uint64_t vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
-	return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR4);
+	if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
+		DRM_ERROR("wrong ring id is identified in %s", __func__);
+
+	return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);
 }
 
 /**
- * vcn_v4_0_dec_ring_get_wptr - get write pointer
+ * vcn_v4_0_unified_ring_get_wptr - get unified write pointer
  *
  * @ring: amdgpu_ring pointer
  *
- * Returns the current hardware write pointer
+ * Returns the current hardware unified write pointer
  */
-static uint64_t vcn_v4_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
+static uint64_t vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
+	if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
+		DRM_ERROR("wrong ring id is identified in %s", __func__);
+
 	if (ring->use_doorbell)
 		return *ring->wptr_cpu_addr;
 	else
-		return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR4);
+		return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);
 }
 
 /**
- * vcn_v4_0_dec_ring_set_wptr - set write pointer
+ * vcn_v4_0_unified_ring_set_wptr - set enc write pointer
  *
  * @ring: amdgpu_ring pointer
  *
- * Commits the write pointer to the hardware
+ * Commits the enc write pointer to the hardware
  */
-static void vcn_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
+static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
-	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
-		WREG32_SOC15(VCN, ring->me, regUVD_SCRATCH2,
-			lower_32_bits(ring->wptr));
-	}
+	if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
+		DRM_ERROR("wrong ring id is identified in %s", __func__);
 
 	if (ring->use_doorbell) {
 		*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
 		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 	} else {
-		WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR4, lower_32_bits(ring->wptr));
-	}
-}
-
-static const struct amdgpu_ring_funcs vcn_v4_0_dec_sw_ring_vm_funcs = {
-	.type = AMDGPU_RING_TYPE_VCN_DEC,
-	.align_mask = 0x3f,
-	.nop = VCN_DEC_SW_CMD_NO_OP,
-	.vmhub = AMDGPU_MMHUB_0,
-	.get_rptr = vcn_v4_0_dec_ring_get_rptr,
-	.get_wptr = vcn_v4_0_dec_ring_get_wptr,
-	.set_wptr = vcn_v4_0_dec_ring_set_wptr,
-	.emit_frame_size =
-		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
-		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
-		VCN_SW_RING_EMIT_FRAME_SIZE,
-	.emit_ib_size = 5, /* vcn_dec_sw_ring_emit_ib */
-	.emit_ib = vcn_dec_sw_ring_emit_ib,
-	.emit_fence = vcn_dec_sw_ring_emit_fence,
-	.emit_vm_flush = vcn_dec_sw_ring_emit_vm_flush,
-	.test_ring = amdgpu_vcn_dec_sw_ring_test_ring,
-	.test_ib = amdgpu_vcn_dec_sw_ring_test_ib,
-	.insert_nop = amdgpu_ring_insert_nop,
-	.insert_end = vcn_dec_sw_ring_insert_end,
-	.pad_ib = amdgpu_ring_generic_pad_ib,
-	.begin_use = amdgpu_vcn_ring_begin_use,
-	.end_use = amdgpu_vcn_ring_end_use,
-	.emit_wreg = vcn_dec_sw_ring_emit_wreg,
-	.emit_reg_wait = vcn_dec_sw_ring_emit_reg_wait,
-	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
-};
-
-/**
- * vcn_v4_0_enc_ring_get_rptr - get enc read pointer
- *
- * @ring: amdgpu_ring pointer
- *
- * Returns the current hardware enc read pointer
- */
-static uint64_t vcn_v4_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
-{
-	struct amdgpu_device *adev = ring->adev;
-
-	if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
-		return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);
-	else
-		return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR2);
-}
-
-/**
- * vcn_v4_0_enc_ring_get_wptr - get enc write pointer
- *
- * @ring: amdgpu_ring pointer
- *
- * Returns the current hardware enc write pointer
- */
-static uint64_t vcn_v4_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
-{
-	struct amdgpu_device *adev = ring->adev;
-
-	if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
-		if (ring->use_doorbell)
-			return *ring->wptr_cpu_addr;
-		else
-			return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);
-	} else {
-		if (ring->use_doorbell)
-			return *ring->wptr_cpu_addr;
-		else
-			return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR2);
-	}
-}
-
-/**
- * vcn_v4_0_enc_ring_set_wptr - set enc write pointer
- *
- * @ring: amdgpu_ring pointer
- *
- * Commits the enc write pointer to the hardware
- */
-static void vcn_v4_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
-{
-	struct amdgpu_device *adev = ring->adev;
-
-	if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
-		if (ring->use_doorbell) {
-			*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
-			WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
-		} else {
-			WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));
-		}
-	} else {
-		if (ring->use_doorbell) {
-			*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
-			WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
-		} else {
-			WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR2, lower_32_bits(ring->wptr));
-		}
+		WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));
 	}
 }
 
-static const struct amdgpu_ring_funcs vcn_v4_0_enc_ring_vm_funcs = {
+static const struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {
 	.type = AMDGPU_RING_TYPE_VCN_ENC,
 	.align_mask = 0x3f,
 	.nop = VCN_ENC_CMD_NO_OP,
 	.vmhub = AMDGPU_MMHUB_0,
-	.get_rptr = vcn_v4_0_enc_ring_get_rptr,
-	.get_wptr = vcn_v4_0_enc_ring_get_wptr,
-	.set_wptr = vcn_v4_0_enc_ring_set_wptr,
+	.get_rptr = vcn_v4_0_unified_ring_get_rptr,
+	.get_wptr = vcn_v4_0_unified_ring_get_wptr,
+	.set_wptr = vcn_v4_0_unified_ring_set_wptr,
 	.emit_frame_size =
 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
@@ -1594,7 +1342,7 @@ static const struct amdgpu_ring_funcs vcn_v4_0_enc_ring_vm_funcs = {
 	.emit_fence = vcn_v2_0_enc_ring_emit_fence,
 	.emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
 	.test_ring = amdgpu_vcn_enc_ring_test_ring,
-	.test_ib = amdgpu_vcn_enc_ring_test_ib,
+	.test_ib = amdgpu_vcn_unified_ring_test_ib,
 	.insert_nop = amdgpu_ring_insert_nop,
 	.insert_end = vcn_v2_0_enc_ring_insert_end,
 	.pad_ib = amdgpu_ring_generic_pad_ib,
@@ -1606,13 +1354,13 @@ static const struct amdgpu_ring_funcs vcn_v4_0_enc_ring_vm_funcs = {
 };
 
 /**
- * vcn_v4_0_set_dec_ring_funcs - set dec ring functions
+ * vcn_v4_0_set_unified_ring_funcs - set unified ring functions
  *
  * @adev: amdgpu_device pointer
  *
- * Set decode ring functions
+ * Set unified ring functions
  */
-static void vcn_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev)
+static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev)
 {
 	int i;
 
@@ -1620,32 +1368,10 @@ static void vcn_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev)
 		if (adev->vcn.harvest_config & (1 << i))
 			continue;
 
-		adev->vcn.inst[i].ring_dec.funcs = &vcn_v4_0_dec_sw_ring_vm_funcs;
-		adev->vcn.inst[i].ring_dec.me = i;
-		DRM_INFO("VCN(%d) decode software ring is enabled in VM mode\n", i);
-	}
-}
-
-/**
- * vcn_v4_0_set_enc_ring_funcs - set enc ring functions
- *
- * @adev: amdgpu_device pointer
- *
- * Set encode ring functions
- */
-static void vcn_v4_0_set_enc_ring_funcs(struct amdgpu_device *adev)
-{
-	int i, j;
-
-	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
-		if (adev->vcn.harvest_config & (1 << i))
-			continue;
+		adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_unified_ring_vm_funcs;
+		adev->vcn.inst[i].ring_enc[0].me = i;
 
-		for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
-			adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v4_0_enc_ring_vm_funcs;
-			adev->vcn.inst[i].ring_enc[j].me = i;
-		}
-		DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i);
+		DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i);
 	}
 }
 
@@ -1798,18 +1524,9 @@ static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_
 	DRM_DEBUG("IH: VCN TRAP\n");
 
 	switch (entry->src_id) {
-	case VCN_4_0__SRCID__UVD_TRAP:
-		if (!unifiedQ_enabled) {
-			amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);
-			break;
-		}
-		break;
 	case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
 		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
 		break;
-	case VCN_4_0__SRCID__UVD_ENC_LOW_LATENCY:
-		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
-		break;
 	default:
 		DRM_ERROR("Unhandled interrupt: %d %d\n",
 			  entry->src_id, entry->src_data[0]);
-- 
GitLab


From e751e4be1eec4d427d91583f31ce56ccb5286a27 Mon Sep 17 00:00:00 2001
From: Ruijing Dong <ruijing.dong@amd.com>
Date: Tue, 14 Jun 2022 22:42:54 -0400
Subject: [PATCH 0943/1731] drm/amdgpu/vcn: adjust unified queue code format
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Fixed some errors and warnings found by checkpatch.pl.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 12 ++++++------
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c   |  8 ++++----
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index e62ff7db4736b..fea4360233514 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -730,8 +730,8 @@ error:
 	return r;
 }
 
-static uint32_t * amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib,
-					  uint32_t ib_pack_in_dw, bool enc)
+static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib,
+						uint32_t ib_pack_in_dw, bool enc)
 {
 	uint32_t *ib_checksum;
 
@@ -749,7 +749,7 @@ static uint32_t * amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib,
 }
 
 static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum,
-				        uint32_t ib_pack_in_dw)
+						uint32_t ib_pack_in_dw)
 {
 	uint32_t i;
 	uint32_t checksum = 0;
@@ -790,7 +790,7 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
 	/* single queue headers */
 	if (sq) {
 		ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t)
-			                     + 4 + 2; /* engine info + decoding ib in dw */
+						+ 4 + 2; /* engine info + decoding ib in dw */
 		ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false);
 	}
 
@@ -896,7 +896,7 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
 					 struct amdgpu_ib *ib_msg,
 					 struct dma_fence **fence)
 {
-	unsigned ib_size_dw = 16;
+	unsigned int ib_size_dw = 16;
 	struct amdgpu_job *job;
 	struct amdgpu_ib *ib;
 	struct dma_fence *f = NULL;
@@ -962,7 +962,7 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
 					  struct amdgpu_ib *ib_msg,
 					  struct dma_fence **fence)
 {
-	unsigned ib_size_dw = 16;
+	unsigned int ib_size_dw = 16;
 	struct amdgpu_job *job;
 	struct amdgpu_ib *ib;
 	struct dma_fence *f = NULL;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index d6f134ef9633d..84ac2401895a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -120,7 +120,7 @@ static int vcn_v4_0_sw_init(void *handle)
 		sprintf(ring->name, "vcn_unified_%d", i);
 
 		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
-				  AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
+						AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
 		if (r)
 			return r;
 
@@ -907,7 +907,7 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
 	WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0);
 	WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0);
 
-	tmp= RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
+	tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
 	WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);
 	ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
 
@@ -1048,8 +1048,8 @@ static int vcn_v4_0_start(struct amdgpu_device *adev)
 
 				dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);
 				WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
-						UVD_VCPU_CNTL__BLK_RST_MASK,
-						~UVD_VCPU_CNTL__BLK_RST_MASK);
+							UVD_VCPU_CNTL__BLK_RST_MASK,
+							~UVD_VCPU_CNTL__BLK_RST_MASK);
 				mdelay(10);
 				WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
 						~UVD_VCPU_CNTL__BLK_RST_MASK);
-- 
GitLab


From b3e73cbf17a95a85e3a943d7500e9e477d6ab9c3 Mon Sep 17 00:00:00 2001
From: Graham Sider <Graham.Sider@amd.com>
Date: Wed, 18 May 2022 14:44:01 -0400
Subject: [PATCH 0944/1731] drm/amdgpu: Remove break for VMID loop TLB flush on
 MES

Loop through all VMIDs for gmc_v10_0_flush_gpu_tlb_pasid and
gmc_v11_0_flush_gpu_tlb_pasid (only if using MES for gmc_v10). This is
required for MES due to use_different_vmid_compute causing SDMA queues
to be assigned different VMIDs than compute for the same PASID.

Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 3 ++-
 drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 1 -
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 9077dfccaf3cf..25d5743ae91b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -456,7 +456,8 @@ static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 				gmc_v10_0_flush_gpu_tlb(adev, vmid,
 						AMDGPU_GFXHUB_0, flush_type);
 			}
-			break;
+			if (!adev->enable_mes)
+				break;
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 9c225553f5b53..ecf41d8a8c7e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -344,7 +344,6 @@ static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 				gmc_v11_0_flush_gpu_tlb(adev, vmid,
 						AMDGPU_GFXHUB_0, flush_type);
 			}
-			break;
 		}
 	}
 
-- 
GitLab


From 1f43b8903f3aae4a26a603c36f6d5dd25d6edb51 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Wed, 15 Jun 2022 12:02:08 -0400
Subject: [PATCH 0945/1731] drm/radeon: fix incorrrect SPDX-License-Identifiers
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

radeon is MIT.  This were incorrectly changed in
commit b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license")
and
commit d198b34f3855 (".gitignore: add SPDX License Identifier")
and:
commit ec8f24b7faaf ("treewide: Add SPDX license identifier - Makefile/Kconfig")

Fixes: d198b34f3855 (".gitignore: add SPDX License Identifier")
Fixes: ec8f24b7faaf ("treewide: Add SPDX license identifier - Makefile/Kconfig")
Fixes: b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license")
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2053
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/radeon/.gitignore | 2 +-
 drivers/gpu/drm/radeon/Kconfig    | 2 +-
 drivers/gpu/drm/radeon/Makefile   | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/radeon/.gitignore b/drivers/gpu/drm/radeon/.gitignore
index 9c1a941539836..d8777383a64aa 100644
--- a/drivers/gpu/drm/radeon/.gitignore
+++ b/drivers/gpu/drm/radeon/.gitignore
@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: GPL-2.0-only
+# SPDX-License-Identifier: MIT
 mkregtable
 *_reg_safe.h
 
diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig
index 6f60f4840cc58..52819e7f1fca1 100644
--- a/drivers/gpu/drm/radeon/Kconfig
+++ b/drivers/gpu/drm/radeon/Kconfig
@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: GPL-2.0-only
+# SPDX-License-Identifier: MIT
 config DRM_RADEON_USERPTR
 	bool "Always enable userptr support"
 	depends on DRM_RADEON
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index ea5380e24c3cc..e3ab3aca13967 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: GPL-2.0
+# SPDX-License-Identifier: MIT
 #
 # Makefile for the drm device driver.  This driver provides support for the
 # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
-- 
GitLab


From f7ba887f606b1895dabf718547cf7397924f0d3a Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Thu, 19 May 2022 10:21:08 -0400
Subject: [PATCH 0946/1731] drm/amdgpu: Adjust logic around GTT size (v3)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Certain GL unit tests for large textures can cause problems
with the OOM killer since there is no way to link this memory
to a process.  This was originally mitigated (but not necessarily
eliminated) by limiting the GTT size.  The problem is this limit
is often too low for many modern games so just make the limit 1/2
of system memory. The OOM accounting needs to be addressed, but
we shouldn't prevent common 3D applications from being usable
just to potentially mitigate that corner case.

Set default GTT size to max(3G, 1/2 of system ram) by default.

v2: drop previous logic and default to 3/4 of ram
v3: default to half of ram to align with ttm
v4: fix spelling in comment (Kent)

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1942
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index be6f76a30ac68..3b4c19412625d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1798,18 +1798,26 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
 	DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
 		 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
 
-	/* Compute GTT size, either bsaed on 3/4th the size of RAM size
+	/* Compute GTT size, either based on 1/2 the size of RAM size
 	 * or whatever the user passed on module init */
 	if (amdgpu_gtt_size == -1) {
 		struct sysinfo si;
 
 		si_meminfo(&si);
-		gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
-			       adev->gmc.mc_vram_size),
-			       ((uint64_t)si.totalram * si.mem_unit * 3/4));
-	}
-	else
+		/* Certain GL unit tests for large textures can cause problems
+		 * with the OOM killer since there is no way to link this memory
+		 * to a process.  This was originally mitigated (but not necessarily
+		 * eliminated) by limiting the GTT size.  The problem is this limit
+		 * is often too low for many modern games so just make the limit 1/2
+		 * of system memory which aligns with TTM. The OOM accounting needs
+		 * to be addressed, but we shouldn't prevent common 3D applications
+		 * from being usable just to potentially mitigate that corner case.
+		 */
+		gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
+			       (u64)si.totalram * si.mem_unit / 2);
+	} else {
 		gtt_size = (uint64_t)amdgpu_gtt_size << 20;
+	}
 
 	/* Initialize GTT memory pool */
 	r = amdgpu_gtt_mgr_init(adev, gtt_size);
-- 
GitLab


From 6626c5a4ea2ef1bba3e02f75f797523e168fe28e Mon Sep 17 00:00:00 2001
From: "Stanley.Yang" <Stanley.Yang@amd.com>
Date: Wed, 15 Jun 2022 23:34:53 +0800
Subject: [PATCH 0947/1731] drm/amdgpu/pm: adjust EccInfo_t struct

The EccInfo_t struct in driver_if.h is as below in official release
verion 68.55.0
 typedef struct {
   uint64_t mca_umc_status;
   uint64_t mca_umc_addr;

   uint16_t ce_count_lo_chip;
   uint16_t ce_count_hi_chip;

   uint32_t eccPadding;

   uint64_t mca_ceumc_addr;
 } EccInfo_t;
It's different from the debug version druing develop print correctable
error address, so adjust EccInfo_t struct.

Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h   | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h
index 6f92038470ecf..7a6075daa7b2f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h
@@ -521,12 +521,13 @@ typedef struct {
 typedef struct {
 	uint64_t mca_umc_status;
 	uint64_t mca_umc_addr;
-	uint64_t mca_ceumc_addr;
 
 	uint16_t ce_count_lo_chip;
 	uint16_t ce_count_hi_chip;
 
 	uint32_t eccPadding;
+
+	uint64_t mca_ceumc_addr;
 } EccInfo_V2_t;
 
 typedef struct {
-- 
GitLab


From 8748de873fedf4d55bdd99bbb738ee7ddf329792 Mon Sep 17 00:00:00 2001
From: Jack Xiao <Jack.Xiao@amd.com>
Date: Wed, 20 Apr 2022 13:08:28 +0800
Subject: [PATCH 0948/1731] drm/amdgpu/gmc11: avoid cpu accessing registers to
 flush VM

Due to gfxoff on, cpu accessing registers is not expected.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 51 +++++++++++++++++++++++++-
 1 file changed, 50 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index ecf41d8a8c7e7..e098b69d63212 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -259,6 +259,12 @@ static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 					uint32_t vmhub, uint32_t flush_type)
 {
+	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+	struct dma_fence *fence;
+	struct amdgpu_job *job;
+
+	int r;
+
 	if ((vmhub == AMDGPU_GFXHUB_0) && !adev->gfx.is_poweron)
 		return;
 
@@ -282,8 +288,51 @@ static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 	}
 
 	mutex_lock(&adev->mman.gtt_window_lock);
-	gmc_v11_0_flush_vm_hub(adev, vmid, vmhub, 0);
+
+	if (vmhub == AMDGPU_MMHUB_0) {
+		gmc_v11_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
+		mutex_unlock(&adev->mman.gtt_window_lock);
+		return;
+	}
+
+	BUG_ON(vmhub != AMDGPU_GFXHUB_0);
+
+	if (!adev->mman.buffer_funcs_enabled ||
+	    !adev->ib_pool_ready ||
+	    amdgpu_in_reset(adev) ||
+	    ring->sched.ready == false) {
+		gmc_v11_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
+		mutex_unlock(&adev->mman.gtt_window_lock);
+		return;
+	}
+
+	r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
+				     &job);
+	if (r)
+		goto error_alloc;
+
+	job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
+	job->vm_needs_flush = true;
+	job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
+	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
+	r = amdgpu_job_submit(job, &adev->mman.entity,
+			      AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
+	if (r)
+		goto error_submit;
+
+	mutex_unlock(&adev->mman.gtt_window_lock);
+
+	dma_fence_wait(fence, false);
+	dma_fence_put(fence);
+
+	return;
+
+error_submit:
+	amdgpu_job_free(job);
+
+error_alloc:
 	mutex_unlock(&adev->mman.gtt_window_lock);
+	DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
 	return;
 }
 
-- 
GitLab


From 51c45e450fc8529495bc85c2d8e309816cdcf959 Mon Sep 17 00:00:00 2001
From: Yang Wang <KevinYang.Wang@amd.com>
Date: Fri, 10 Jun 2022 11:48:04 +0800
Subject: [PATCH 0949/1731] drm/amd/pm: skip to set mp1 unload state in special
 case

set mp1 unload state will cause the SMC FW can't accept any SMU message,
skip to set mp1 unload state to avoid following case fail:
- runtime pm case.
- gpu reset case.

Fixes: 72aeb6ee0c78 ("drm/amd/pm: fix driver reload SMC firmware fail issue for smu13")
Signed-off-by: Yang Wang <KevinYang.Wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 3d269d1c27494..fd79b213fab48 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1415,12 +1415,13 @@ static int smu_disable_dpms(struct smu_context *smu)
 	switch (adev->ip_versions[MP1_HWIP][0]) {
 	case IP_VERSION(13, 0, 0):
 	case IP_VERSION(13, 0, 7):
-		ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD);
-		if (ret) {
-			dev_err(adev->dev, "Fail set mp1 state to UNLOAD!\n");
-			return ret;
+		if (!(adev->in_runpm || amdgpu_in_reset(adev))) {
+			ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD);
+			if (ret) {
+				dev_err(adev->dev, "Fail set mp1 state to UNLOAD!\n");
+				return ret;
+			}
 		}
-
 		return 0;
 	default:
 		break;
-- 
GitLab


From 1320d6c7b0deb7219701a55397e93e6c73d00366 Mon Sep 17 00:00:00 2001
From: Mario Limonciello <mario.limonciello@amd.com>
Date: Mon, 13 Jun 2022 23:53:52 -0500
Subject: [PATCH 0950/1731] drm/amd: Don't show warning on reading vbios values
 for SMU13 3.1

Some APUs with SMU13 are showing the following message:
`amdgpu 0000:63:00.0: amdgpu: Unexpected and unhandled version: 3.1`

This warning isn't relevant for smu info 3.1, as no bootup information
is present in the table.

Fixes: 593a54f18031 ("drm/amd/pm: correct the way for retrieving bootup clocks")
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index f18f9605e586e..0e59ab2192bf4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -731,6 +731,8 @@ int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
 			smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
 			smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
 			smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
+		} else if ((frev == 3) && (crev == 1)) {
+			return 0;
 		} else if ((frev == 4) && (crev == 0)) {
 			smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
 
-- 
GitLab


From 262236b4f5a7d2fe31ed31d34669a9ea4f1c3272 Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Thu, 16 Jun 2022 16:44:55 -0400
Subject: [PATCH 0951/1731] drm/amd/display: add missing reg defs for DCN3x
 HUBBUB

[Why&How]
The omitted register definition caused call traces like:

[    3.811215] WARNING: CPU: 7 PID: 794 at drivers/gpu/drm/amd/amdgpu/../display/dc/dc_helper.c:120 set_reg_field_values.constprop.0+0xc7/0xe0 [amdgpu]
[    3.811406] Modules linked in: amdgpu(+) drm_ttm_helper ttm iommu_v2 gpu_sched drm_kms_helper cfbfillrect syscopyarea cfbimgblt sysfillrect sysimgblt fb_sys_fops cfbcopyarea drm i2c_piix4 drm_panel_orientation_quirks
[    3.811419] CPU: 7 PID: 794 Comm: systemd-udevd Not tainted 5.16.0-kfd+ #132
[    3.811422] Hardware name: System manufacturer System Product Name/ROG STRIX B450-F GAMING, BIOS 3003 12/09/2019
[    3.811425] RIP: 0010:set_reg_field_values.constprop.0+0xc7/0xe0 [amdgpu]
[    3.811615] Code: 08 49 89 51 08 8b 08 48 8d 42 08 49 89 41 08 44 8b 02 48 8d 50 08 0f b6 c9 49 89 51 08 8b 00 45 85 c0 75 b3 0f 0b eb af 5d c3 <0f> 0b e9 48 ff ff ff 49 8b 51 08 eb d0 49 8b 41 08 eb d5 66 0f 1f
[    3.811619] RSP: 0018:ffffb8c1c04cf640 EFLAGS: 00010246
[    3.811621] RAX: 0000000000000000 RBX: ffff96f2100d8800 RCX: 0000000000000000
[    3.811623] RDX: 0000000000000000 RSI: 0000000000000001 RDI: ffffb8c1c04cf650
[    3.811625] RBP: ffffb8c1c04cf640 R08: 000000000000047f R09: ffffb8c1c04cf658
[    3.811627] R10: ffff96f5161ff000 R11: ffff96f5161ff000 R12: ffff96f204afb9c0
[    3.811629] R13: 0000000000000000 R14: ffff96f202b94c00 R15: ffffb8c1c04cf718
[    3.811631] FS:  00007fe07c2e2880(0000) GS:ffff96f5059c0000(0000) knlGS:0000000000000000
[    3.811634] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[    3.811636] CR2: 0000559634ab57b8 CR3: 0000000120674000 CR4: 00000000003506e0
[    3.811637] Call Trace:
[    3.811640]  <TASK>
[    3.811642]  generic_reg_update_ex+0x69/0x200 [amdgpu]
[    3.811831]  ? _printk+0x58/0x6f
[    3.811836]  dcn32_init_crb+0x18f/0x1b0 [amdgpu]
[    3.812031]  dcn32_init_hw+0x379/0x6a0 [amdgpu]
[    3.812223]  dc_hardware_init+0xba/0x100 [amdgpu]
[    3.812415]  amdgpu_dm_init.isra.0.cold+0x166/0x1867 [amdgpu]
[    3.812616]  ? dev_vprintk_emit+0x139/0x15d
[    3.812621]  ? dev_printk_emit+0x4e/0x65
[    3.812624]  dm_hw_init+0x12/0x30 [amdgpu]
[    3.812820]  amdgpu_device_init.cold+0x130d/0x178c [amdgpu]
[    3.813017]  ? pci_read_config_word+0x25/0x40
[    3.813021]  amdgpu_driver_load_kms+0x1a/0x130 [amdgpu]
[    3.813178]  amdgpu_pci_probe+0x130/0x330 [amdgpu]

Fixes: 4f29f9cf092b ("drm/amd: add register headers for DCN32/321")
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h          | 2 ++
 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h  | 2 ++
 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h | 3 +++
 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h  | 2 ++
 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h | 4 ++++
 5 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h
index 8d3ea8ee5b3b4..3bae6e558971b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h
@@ -65,6 +65,7 @@
 	SR(DCHUBBUB_DET3_CTRL),\
 	SR(DCHUBBUB_COMPBUF_CTRL),\
 	SR(COMPBUF_RESERVED_SPACE),\
+	SR(DCHUBBUB_DEBUG_CTRL_0),\
 	SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL),\
 	SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A),\
 	SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B),\
@@ -118,6 +119,7 @@
 	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, mask_sh), \
 	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, mask_sh), \
 	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, mask_sh),\
 	HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE, mask_sh),\
 	HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, mask_sh),\
 	HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE, mask_sh),\
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h
index 6f84ea5c006f9..14c29ce4c7b35 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h
@@ -1807,6 +1807,8 @@
 #define regDCHUBBUB_DET2_CTRL_BASE_IDX                                                                  2
 #define regDCHUBBUB_DET3_CTRL                                                                           0x04be
 #define regDCHUBBUB_DET3_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_DEBUG_CTRL_0                                                                        0x04c5
+#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                                               2
 #define regDCHUBBUB_MEM_PWR_MODE_CTRL                                                                   0x04c0
 #define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX                                                          2
 #define regCOMPBUF_MEM_PWR_CTRL_1                                                                       0x04c1
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h
index d42f91560bb95..0691e328d0f02 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h
@@ -6348,6 +6348,9 @@
 #define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B_MASK                                               0x00000FFFL
 #define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS_MASK                                                0x0FFF0000L
 
+//DCHUBBUB_DEBUG_CTRL_0
+#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT                                                               0x10
+#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK                                                                 0x07FF0000L
 
 // addressBlock: dcn_dc_dchubbubl_hubbub_vmrq_if_dispdec
 //DCN_VM_CONTEXT0_CNTL
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h
index e40a924c02cef..3bd8792fd7b35 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h
@@ -1817,6 +1817,8 @@
 #define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
 #define regCOMPBUF_RESERVED_SPACE                                                                       0x04c4
 #define regCOMPBUF_RESERVED_SPACE_BASE_IDX                                                              2
+#define regDCHUBBUB_DEBUG_CTRL_0                                                                        0x04c5
+#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                                               2
 
 
 // addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h
index 23faa628cd59e..e82dffc2b9b0b 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h
@@ -6350,6 +6350,10 @@
 #define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B_MASK                                               0x00000FFFL
 #define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS_MASK                                                0x0FFF0000L
 
+//DCHUBBUB_DEBUG_CTRL_0
+#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT                                                               0x10
+#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK                                                                 0x07FF0000L
+
 
 // addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec
 //DCN_VM_CONTEXT0_CNTL
-- 
GitLab


From 0081bc072837b66587904e6988aea1e0845b0294 Mon Sep 17 00:00:00 2001
From: Yifan Zhang <yifan1.zhang@amd.com>
Date: Mon, 20 Jun 2022 19:32:33 +0800
Subject: [PATCH 0952/1731] drm/amdgpu: add LSDMA block for LSDMA v6.0.1

This patch adds LSDMA ip block for LSDMA v6.0.1.

Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 11bbd76c581c6..37234c2998d73 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2333,6 +2333,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
 
 	switch (adev->ip_versions[LSDMA_HWIP][0]) {
 	case IP_VERSION(6, 0, 0):
+	case IP_VERSION(6, 0, 1):
 	case IP_VERSION(6, 0, 2):
 		adev->lsdma.funcs = &lsdma_v6_0_funcs;
 		break;
-- 
GitLab


From 5d763a9955f0fbf2681a2f1fa87c416056bd0c89 Mon Sep 17 00:00:00 2001
From: Cruise Hung <Cruise.Hung@amd.com>
Date: Mon, 6 Jun 2022 22:12:39 +0800
Subject: [PATCH 0953/1731] drm/amd/display: Remove compiler warning

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Cruise Hung <Cruise.Hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/include/fixed31_32.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h b/drivers/gpu/drm/amd/display/include/fixed31_32.h
index 22053d7ea6ced..ece97ae0e826c 100644
--- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
+++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
@@ -322,7 +322,7 @@ struct fixed31_32 dc_fixpt_sqr(struct fixed31_32 arg);
  */
 static inline struct fixed31_32 dc_fixpt_div_int(struct fixed31_32 arg1, long long arg2)
 {
-	return dc_fixpt_from_fraction(arg1.value, dc_fixpt_from_int(arg2).value);
+	return dc_fixpt_from_fraction(arg1.value, dc_fixpt_from_int((int)arg2).value);
 }
 
 /*
-- 
GitLab


From 4dd905fd9429626937107ca13770aa836c8a7e6e Mon Sep 17 00:00:00 2001
From: Mario Limonciello <mario.limonciello@amd.com>
Date: Wed, 15 Jun 2022 17:30:05 -0500
Subject: [PATCH 0954/1731] drm/amd: Revert "drm/amd/display: keep eDP Vdd on
 when eDP stream is already enabled"

A variety of Lenovo machines with Rembrandt APUs and OLED panels have
stopped showing the display at login.  This behavior clears up after
leaving it idle and moving the mouse or touching keyboard.

It was bisected to be caused by commit 559e2655220d ("drm/amd/display:
keep eDP Vdd on when eDP stream is already enabled").  Revert this commit
to fix the issue.

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2047
Reported-by: Aaron Ma <aaron.ma@canonical.com>
Fixes: 559e2655220d ("drm/amd/display: keep eDP Vdd on when eDP stream is already enabled")
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Tested-by: Mark Pearson <markpearson@lenovo.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../display/dc/dce110/dce110_hw_sequencer.c   | 24 ++-----------------
 1 file changed, 2 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index e7944c8811484..8662703f306c7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1776,29 +1776,9 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
 				break;
 			}
 		}
-
-		/*
-		 * TO-DO: So far the code logic below only addresses single eDP case.
-		 * For dual eDP case, there are a few things that need to be
-		 * implemented first:
-		 *
-		 * 1. Change the fastboot logic above, so eDP link[0 or 1]'s
-		 * stream[0 or 1] will all be checked.
-		 *
-		 * 2. Change keep_edp_vdd_on to an array, and maintain keep_edp_vdd_on
-		 * for each eDP.
-		 *
-		 * Once above 2 things are completed, we can then change the logic below
-		 * correspondingly, so dual eDP case will be fully covered.
-		 */
-
-		// We are trying to enable eDP, don't power down VDD if eDP stream is existing
-		if ((edp_stream_num == 1 && edp_streams[0] != NULL) || can_apply_edp_fast_boot) {
+		// We are trying to enable eDP, don't power down VDD
+		if (can_apply_edp_fast_boot)
 			keep_edp_vdd_on = true;
-			DC_LOG_EVENT_LINK_TRAINING("Keep eDP Vdd on\n");
-		} else {
-			DC_LOG_EVENT_LINK_TRAINING("No eDP stream enabled, turn eDP Vdd off\n");
-		}
 	}
 
 	// Check seamless boot support
-- 
GitLab


From 10a36226157035e84aaa58e1699a32b3de2755af Mon Sep 17 00:00:00 2001
From: Wayne Lin <Wayne.Lin@amd.com>
Date: Wed, 13 Apr 2022 15:52:48 +0800
Subject: [PATCH 0955/1731] drm/amd/display: Revert "drm/amd/display: Add flag
 to detect dpms force off during HPD"

This reverts commit 035f54969bb2c1a5ced52f43e4ef393e0c0f6bfa.

The reverted commit was trying to fix side effect brought by
commit 3c4d55c9b9be ("drm/amd/display: turn DPMS off on connector unplug")

However,
* This reverted commit will have mst case never call dm_set_dpms_off()
  which conflicts the idea of original commit 3c4d55c9b9be ("drm/amd/display: turn DPMS off on connector unplug")
  That's due to dm_crtc_state is always null since the input parameter
  aconnector is the root device (source) of mst topology.  It's not an
  end stream sink within the mst topology.
* Setting dpms off should be triggered by usermode. Besdies, it seems
  usermode does release relevant resource for mst & non-mst case when
  unplug connecotr now. Which means we no longer need both commits now:
  commit 3c4d55c9b9be ("drm/amd/display: turn DPMS off on connector unplug")
  commit 035f54969bb2 ("drm/amd/display: Add flag to detect dpms force off during HPD")

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Aurabindo Jayamohanan Pillai <Aurabindo.Pillai@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 19 ++++++-------------
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  2 --
 .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c    | 15 +++++----------
 3 files changed, 11 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 60fb99b747131..6c3288980e1e3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2583,7 +2583,7 @@ cleanup:
 	return;
 }
 
-static void dm_set_dpms_off(struct dc_link *link, struct dm_crtc_state *acrtc_state)
+static void dm_set_dpms_off(struct dc_link *link)
 {
 	struct dc_stream_state *stream_state;
 	struct amdgpu_dm_connector *aconnector = link->priv;
@@ -2604,7 +2604,6 @@ static void dm_set_dpms_off(struct dc_link *link, struct dm_crtc_state *acrtc_st
 	}
 
 	stream_update.stream = stream_state;
-	acrtc_state->force_dpms_off = true;
 	dc_commit_updates_for_stream(stream_state->ctx->dc, NULL, 0,
 				     stream_state, &stream_update,
 				     stream_state->ctx->dc->current_state);
@@ -3061,16 +3060,13 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
 	struct drm_device *dev = connector->dev;
 	enum dc_connection_type new_connection_type = dc_connection_none;
 	struct amdgpu_device *adev = drm_to_adev(dev);
+#ifdef CONFIG_DRM_AMD_DC_HDCP
 	struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
-	struct dm_crtc_state *dm_crtc_state = NULL;
+#endif
 
 	if (adev->dm.disable_hpd_irq)
 		return;
 
-	if (dm_con_state->base.state && dm_con_state->base.crtc)
-		dm_crtc_state = to_dm_crtc_state(drm_atomic_get_crtc_state(
-					dm_con_state->base.state,
-					dm_con_state->base.crtc));
 	/*
 	 * In case of failure or MST no need to update connector status or notify the OS
 	 * since (for MST case) MST does this in its own context.
@@ -3101,9 +3097,8 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
 
 	} else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
 		if (new_connection_type == dc_connection_none &&
-		    aconnector->dc_link->type == dc_connection_none &&
-		    dm_crtc_state)
-			dm_set_dpms_off(aconnector->dc_link, dm_crtc_state);
+		    aconnector->dc_link->type == dc_connection_none)
+			dm_set_dpms_off(aconnector->dc_link);
 
 		amdgpu_dm_update_connector_after_detect(aconnector);
 
@@ -6840,7 +6835,6 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
 	state->freesync_config = cur->freesync_config;
 	state->cm_has_degamma = cur->cm_has_degamma;
 	state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
-	state->force_dpms_off = cur->force_dpms_off;
 	state->mpo_requested = cur->mpo_requested;
 	/* TODO Duplicate dc_stream after objects are stream object is flattened */
 
@@ -9579,8 +9573,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 		 * and rely on sending it from software.
 		 */
 		if (acrtc_attach->base.state->event &&
-		    acrtc_state->active_planes > 0 &&
-		    !acrtc_state->force_dpms_off) {
+		    acrtc_state->active_planes > 0) {
 			drm_crtc_vblank_get(pcrtc);
 
 			spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index aa34c0068f410..2e351204cc2d9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -639,8 +639,6 @@ struct dm_crtc_state {
 
 	bool dsc_force_changed;
 	bool vrr_supported;
-
-	bool force_dpms_off;
 	struct mod_freesync_config freesync_config;
 	struct dc_info_packet vrr_infopacket;
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index fcafe07ed9087..a4191b2b4c653 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -448,7 +448,6 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
 	struct mod_hdcp_display *display = &hdcp_work[link_index].display;
 	struct mod_hdcp_link *link = &hdcp_work[link_index].link;
 	struct drm_connector_state *conn_state;
-	struct dc_sink *sink = NULL;
 	bool link_is_hdcp14 = false;
 
 	if (config->dpms_off) {
@@ -462,13 +461,8 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
 	display->index = aconnector->base.index;
 	display->state = MOD_HDCP_DISPLAY_ACTIVE;
 
-	if (aconnector->dc_sink)
-		sink = aconnector->dc_sink;
-	else if (aconnector->dc_em_sink)
-		sink = aconnector->dc_em_sink;
-
-	if (sink != NULL)
-		link->mode = mod_hdcp_signal_type_to_operation_mode(sink->sink_signal);
+	if (aconnector->dc_sink != NULL)
+		link->mode = mod_hdcp_signal_type_to_operation_mode(aconnector->dc_sink->sink_signal);
 
 	display->controller = CONTROLLER_ID_D0 + config->otg_inst;
 	display->dig_fe = config->dig_fe;
@@ -478,8 +472,9 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
 	link->link_enc_idx = config->link_enc_idx;
 	link->dio_output_id = config->dio_output_idx;
 	link->phy_idx = config->phy_idx;
-	if (sink)
-		link_is_hdcp14 = dc_link_is_hdcp14(aconnector->dc_link, sink->sink_signal);
+
+	link->hdcp_supported_informational = dc_link_is_hdcp14(aconnector->dc_link,
+			aconnector->dc_sink->sink_signal) ? 1 : 0;
 	link->hdcp_supported_informational = link_is_hdcp14;
 	link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw;
 	link->dp.assr_enabled = config->assr_enabled;
-- 
GitLab


From 052eaf6af846e59073a842e9b9517ba9d3f76d4a Mon Sep 17 00:00:00 2001
From: Wayne Lin <Wayne.Lin@amd.com>
Date: Wed, 13 Apr 2022 15:53:29 +0800
Subject: [PATCH 0956/1731] drm/amd/display: Revert "drm/amd/display: turn DPMS
 off on connector unplug"

This reverts commit 3c4d55c9b9becedd8d31a7c96783a364533713ab.

Revert the commit because:
- It's incomplete of the function dm_set_dpms_off() for mst case.  For
  stream sinks whithin the same mst topology, they share the same dc_link.
  dm_set_dpms_off() tries to update one mst stream only which is
  incomplete.
- Setting dpms off should be triggered by usermode. Besdies, it seems
  usermode does release relevant resource for mst & non-mst case when
  unplug connecotr now.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Aurabindo Jayamohanan Pillai <Aurabindo.Pillai@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 31 -------------------
 drivers/gpu/drm/amd/display/dc/core/dc.c      | 13 --------
 drivers/gpu/drm/amd/display/dc/dc_stream.h    |  1 -
 3 files changed, 45 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 6c3288980e1e3..986aeaf78ac05 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2583,33 +2583,6 @@ cleanup:
 	return;
 }
 
-static void dm_set_dpms_off(struct dc_link *link)
-{
-	struct dc_stream_state *stream_state;
-	struct amdgpu_dm_connector *aconnector = link->priv;
-	struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
-	struct dc_stream_update stream_update;
-	bool dpms_off = true;
-
-	memset(&stream_update, 0, sizeof(stream_update));
-	stream_update.dpms_off = &dpms_off;
-
-	mutex_lock(&adev->dm.dc_lock);
-	stream_state = dc_stream_find_from_link(link);
-
-	if (stream_state == NULL) {
-		DRM_DEBUG_DRIVER("Error finding stream state associated with link!\n");
-		mutex_unlock(&adev->dm.dc_lock);
-		return;
-	}
-
-	stream_update.stream = stream_state;
-	dc_commit_updates_for_stream(stream_state->ctx->dc, NULL, 0,
-				     stream_state, &stream_update,
-				     stream_state->ctx->dc->current_state);
-	mutex_unlock(&adev->dm.dc_lock);
-}
-
 static int dm_resume(void *handle)
 {
 	struct amdgpu_device *adev = handle;
@@ -3096,10 +3069,6 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
 			drm_kms_helper_connector_hotplug_event(connector);
 
 	} else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
-		if (new_connection_type == dc_connection_none &&
-		    aconnector->dc_link->type == dc_connection_none)
-			dm_set_dpms_off(aconnector->dc_link);
-
 		amdgpu_dm_update_connector_after_detect(aconnector);
 
 		drm_modeset_lock_all(dev);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 48a14a5bda563..146fd4b864b2a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3325,19 +3325,6 @@ struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
 	return NULL;
 }
 
-struct dc_stream_state *dc_stream_find_from_link(const struct dc_link *link)
-{
-	uint8_t i;
-	struct dc_context *ctx = link->ctx;
-
-	for (i = 0; i < ctx->dc->current_state->stream_count; i++) {
-		if (ctx->dc->current_state->streams[i]->link == link)
-			return ctx->dc->current_state->streams[i];
-	}
-
-	return NULL;
-}
-
 enum dc_irq_source dc_interrupt_to_irq_source(
 		struct dc *dc,
 		uint32_t src_id,
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 5a894c19b0ea9..6f79327e00355 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -351,7 +351,6 @@ void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream);
 
 uint8_t dc_get_current_stream_count(struct dc *dc);
 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
-struct dc_stream_state *dc_stream_find_from_link(const struct dc_link *link);
 
 /*
  * Return the current frame counter.
-- 
GitLab


From 84a8b3908285d007db49532fd4b51d4b183d1242 Mon Sep 17 00:00:00 2001
From: Wayne Lin <Wayne.Lin@amd.com>
Date: Tue, 12 Apr 2022 21:18:00 +0800
Subject: [PATCH 0957/1731] drm/amd/display: Release remote dc_sink under mst
 scenario

[Why]
Observe that we have several problems while releasing remote dc_sink
under mst cases.

- When unplug mst branch device from the source, we now try to free all
  remote dc_sinks in dm_helpers_dp_mst_stop_top_mgr(). However, there are
  bugs while we're releasing dc_sinks here. First of all,
  link->remote_sinks[] array get shuffled within
  dc_link_remove_remote_sink(). As the result, increasing the array index
  within the releasing loop is wrong. Secondly, it tries to call
  dc_sink_release() to release the dc_sink of the same aconnector every
  time in the loop. Which can't release dc_sink of all aconnector in the
  mst topology.
- There is no code path for us to release remote dc_sink for disconnected
  sst monitor which unplug event is notified by CSN sideband message. Which
  means we'll use stale dc_sink data to represent later on connected
  monitor. Also, has chance to break the maximum remote dc_sink number
  constraint.

[How]
Distinguish unplug event of mst scenario into 2 cases.

* Unplug sst/legacy stream sink off the mst topology
- Release related remote dc_sink in detec_ctx().

* Unplug mst branch device off the mst topology
- Release related remote dc_sink in early_unregister()

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Aurabindo Jayamohanan Pillai <Aurabindo.Pillai@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  5 +--
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 18 +---------
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 34 +++++++++++++++++--
 3 files changed, 35 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 986aeaf78ac05..9039c2fbabe2e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2201,7 +2201,8 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend)
 		} else {
 			ret = drm_dp_mst_topology_mgr_resume(mgr, true);
 			if (ret < 0) {
-				drm_dp_mst_topology_mgr_set_mst(mgr, false);
+				dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
+					aconnector->dc_link);
 				need_hotplug = true;
 			}
 		}
@@ -10606,7 +10607,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
 		 * added MST connectors not found in existing crtc_state in the chained mode
 		 * TODO: need to dig out the root cause of that
 		 */
-		if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
+		if (!aconnector)
 			goto skip_modeset;
 
 		if (modereset_required(new_crtc_state))
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 7c799ddc1d278..137645d40b72e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -451,7 +451,6 @@ bool dm_helpers_dp_mst_stop_top_mgr(
 		struct dc_link *link)
 {
 	struct amdgpu_dm_connector *aconnector = link->priv;
-	uint8_t i;
 
 	if (!aconnector) {
 		DRM_ERROR("Failed to find connector for link!");
@@ -463,22 +462,7 @@ bool dm_helpers_dp_mst_stop_top_mgr(
 
 	if (aconnector->mst_mgr.mst_state == true) {
 		drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
-
-		for (i = 0; i < MAX_SINKS_PER_LINK; i++) {
-			if (link->remote_sinks[i] == NULL)
-				continue;
-
-			if (link->remote_sinks[i]->sink_signal ==
-			    SIGNAL_TYPE_DISPLAY_PORT_MST) {
-				dc_link_remove_remote_sink(link, link->remote_sinks[i]);
-
-				if (aconnector->dc_sink) {
-					dc_sink_release(aconnector->dc_sink);
-					aconnector->dc_sink = NULL;
-					aconnector->dc_link->cur_link_settings.lane_count = 0;
-				}
-			}
-		}
+		link->cur_link_settings.lane_count = 0;
 	}
 
 	return false;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 7e246a798c8a4..26f733b2faa0d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -140,11 +140,28 @@ amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
 static void
 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
 {
-	struct amdgpu_dm_connector *amdgpu_dm_connector =
+	struct amdgpu_dm_connector *aconnector =
 		to_amdgpu_dm_connector(connector);
-	struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
+	struct drm_dp_mst_port *port = aconnector->port;
+	struct amdgpu_dm_connector *root = aconnector->mst_port;
+	struct dc_link *dc_link = aconnector->dc_link;
+	struct dc_sink *dc_sink = aconnector->dc_sink;
 
 	drm_dp_mst_connector_early_unregister(connector, port);
+
+	/*
+	 * Release dc_sink for connector which its attached port is
+	 * no longer in the mst topology
+	 */
+	drm_modeset_lock(&root->mst_mgr.base.lock, NULL);
+	if (dc_sink) {
+		if (dc_link->sink_count)
+			dc_link_remove_remote_sink(dc_link, dc_sink);
+
+		dc_sink_release(dc_sink);
+		aconnector->dc_sink = NULL;
+	}
+	drm_modeset_unlock(&root->mst_mgr.base.lock);
 }
 
 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
@@ -351,7 +368,7 @@ dm_dp_mst_detect(struct drm_connector *connector,
 		return connector_status_disconnected;
 
 	connection_status = drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
-				      aconnector->port);
+							aconnector->port);
 
 	if (port->pdt != DP_PEER_DEVICE_NONE && !port->dpcd_rev) {
 		uint8_t dpcd_rev;
@@ -385,6 +402,17 @@ dm_dp_mst_detect(struct drm_connector *connector,
 		port->dpcd_rev = 0;
 	}
 
+	/*
+	 * Release dc_sink for connector which unplug event is notified by CSN msg
+	 */
+	if (connection_status == connector_status_disconnected && aconnector->dc_sink) {
+		if (aconnector->dc_link->sink_count)
+			dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink);
+
+		dc_sink_release(aconnector->dc_sink);
+		aconnector->dc_sink = NULL;
+	}
+
 	return connection_status;
 }
 
-- 
GitLab


From 4d31819a3746b1f33a915546a4b1aa19374d1544 Mon Sep 17 00:00:00 2001
From: Wayne Lin <Wayne.Lin@amd.com>
Date: Tue, 31 May 2022 18:14:41 +0800
Subject: [PATCH 0958/1731] drm/amd/display: Take emulated dc_sink into account
 for HDCP

[Why]
While updating the config of hdcp, we use the sink_singal type of the
dc_sink to decide the HDCP operation mode. However, it doesn't consider
the case when the sink is a emulated one.

[How]
Take dc_em_sink into account while updating HDCP config.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Aurabindo Jayamohanan Pillai <Aurabindo.Pillai@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index a4191b2b4c653..d7c41c133e2c2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -448,6 +448,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
 	struct mod_hdcp_display *display = &hdcp_work[link_index].display;
 	struct mod_hdcp_link *link = &hdcp_work[link_index].link;
 	struct drm_connector_state *conn_state;
+	struct dc_sink *sink = NULL;
 	bool link_is_hdcp14 = false;
 
 	if (config->dpms_off) {
@@ -461,8 +462,13 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
 	display->index = aconnector->base.index;
 	display->state = MOD_HDCP_DISPLAY_ACTIVE;
 
-	if (aconnector->dc_sink != NULL)
-		link->mode = mod_hdcp_signal_type_to_operation_mode(aconnector->dc_sink->sink_signal);
+	if (aconnector->dc_sink)
+		sink = aconnector->dc_sink;
+	else if (aconnector->dc_em_sink)
+		sink = aconnector->dc_em_sink;
+
+	if (sink != NULL)
+		link->mode = mod_hdcp_signal_type_to_operation_mode(sink->sink_signal);
 
 	display->controller = CONTROLLER_ID_D0 + config->otg_inst;
 	display->dig_fe = config->dig_fe;
@@ -473,8 +479,8 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
 	link->dio_output_id = config->dio_output_idx;
 	link->phy_idx = config->phy_idx;
 
-	link->hdcp_supported_informational = dc_link_is_hdcp14(aconnector->dc_link,
-			aconnector->dc_sink->sink_signal) ? 1 : 0;
+	if (sink)
+		link_is_hdcp14 = dc_link_is_hdcp14(aconnector->dc_link, sink->sink_signal);
 	link->hdcp_supported_informational = link_is_hdcp14;
 	link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw;
 	link->dp.assr_enabled = config->assr_enabled;
-- 
GitLab


From ec457f8378901d673b841e81d289b0165286db7f Mon Sep 17 00:00:00 2001
From: Ian Chen <ian.chen@amd.com>
Date: Mon, 16 May 2022 15:35:34 +0800
Subject: [PATCH 0959/1731] drm/amd/display: Drop unnecessary detect link code

Delete unnecessary codes in detect_link_and_local_sink. We already have
correct stop logic in dc_link_detect.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Ian Chen <ian.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 199868925fe48..fac27b45230f1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1142,11 +1142,6 @@ static bool detect_link_and_local_sink(struct dc_link *link,
 					(link->dpcd_caps.dongle_type !=
 							DISPLAY_DONGLE_DP_HDMI_CONVERTER))
 				converter_disable_audio = true;
-
-			// link switch from MST to non-MST stop topology manager
-			if (pre_connection_type == dc_connection_mst_branch &&
-					link->type != dc_connection_mst_branch)
-				dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 			break;
 		}
 
-- 
GitLab


From f04d275d94e164d24516c32437c988a323018f63 Mon Sep 17 00:00:00 2001
From: hersen wu <hersenxs.wu@amd.com>
Date: Sun, 29 May 2022 12:12:32 -0400
Subject: [PATCH 0960/1731] drm/amd/display: add mst port output bw check

[Why]
when connect one 4k@144hz dp to dsc mst hub, 4k@144hz mode is in valid
mode list. but some mst hub port output bandwidth does not support
4k@144hz.

[How]
add mst port output bandwidth checks, include full_pbn, branch max
throughput mps.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Jerry Zuo <Jerry.Zuo@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  8 +++--
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  3 +-
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 36 +++++++++++++++++++
 .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |  4 +++
 4 files changed, 48 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 9039c2fbabe2e..b3ab2a3ea29c5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7260,7 +7260,11 @@ create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
 			break;
 		}
 
-		dc_result = dc_validate_stream(adev->dm.dc, stream);
+		if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
+			dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
+
+		if (dc_result == DC_OK)
+			dc_result = dc_validate_stream(adev->dm.dc, stream);
 
 		if (dc_result != DC_OK) {
 			DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
@@ -7560,7 +7564,7 @@ static void dm_encoder_helper_disable(struct drm_encoder *encoder)
 
 }
 
-static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth)
+int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
 {
 	switch (display_color_depth) {
 		case COLOR_DEPTH_666:
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 2e351204cc2d9..547fc15479778 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -583,7 +583,6 @@ struct amdgpu_dm_connector {
 	struct drm_dp_mst_port *port;
 	struct amdgpu_dm_connector *mst_port;
 	struct drm_dp_aux *dsc_aux;
-
 	/* TODO see if we can merge with ddc_bus or make a dm_connector */
 	struct amdgpu_i2c_adapter *i2c;
 
@@ -747,4 +746,6 @@ int dm_atomic_get_state(struct drm_atomic_state *state,
 struct amdgpu_dm_connector *
 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
 					     struct drm_crtc *crtc);
+
+int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth);
 #endif /* __AMDGPU_DM_H__ */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 26f733b2faa0d..f3ce37664143f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -1353,4 +1353,40 @@ clean_exit:
 
 	return (ret == 0);
 }
+
 #endif
+
+enum dc_status dm_dp_mst_is_port_support_mode(
+	struct amdgpu_dm_connector *aconnector,
+	struct dc_stream_state *stream)
+{
+	int bpp, pbn, branch_max_throughput_mps = 0;
+
+	/* check if mode could be supported within fUll_pbn */
+	bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
+	pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
+	if (pbn > aconnector->port->full_pbn)
+		return DC_FAIL_BANDWIDTH_VALIDATE;
+
+	/* check is mst dsc output bandwidth branch_overall_throughput_0_mps */
+	switch (stream->timing.pixel_encoding) {
+	case PIXEL_ENCODING_RGB:
+	case PIXEL_ENCODING_YCBCR444:
+		branch_max_throughput_mps =
+			aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps;
+		break;
+	case PIXEL_ENCODING_YCBCR422:
+	case PIXEL_ENCODING_YCBCR420:
+		branch_max_throughput_mps =
+			aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps;
+		break;
+	default:
+		break;
+	}
+
+	if (branch_max_throughput_mps != 0 &&
+		((stream->timing.pix_clk_100hz / 10) >  branch_max_throughput_mps * 1000))
+		return DC_FAIL_BANDWIDTH_VALIDATE;
+
+	return DC_OK;
+}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
index 2e13027d9b884..b92a7c5671aa2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
@@ -63,4 +63,8 @@ bool pre_validate_dsc(struct drm_atomic_state *state,
 		      struct dm_atomic_state **dm_state_ptr,
 		      struct dsc_mst_fairness_vars *vars);
 
+enum dc_status dm_dp_mst_is_port_support_mode(
+	struct amdgpu_dm_connector *aconnector,
+	struct dc_stream_state *stream);
+
 #endif
-- 
GitLab


From 06f2f7772dc7ff2e3734e654cb2d0b588076860d Mon Sep 17 00:00:00 2001
From: Sung Joon Kim <sungkim@amd.com>
Date: Tue, 7 Jun 2022 11:36:29 -0400
Subject: [PATCH 0961/1731] drm/amd/display: Fix eDP not light up on resume

[why]
Only on VG, if external display is disconnected during S3 suspend, the
internal panel doesn't light up on resume because we set the power state
using an unsupported DPCD register SET_POWER.  To check the register is
supported, we need to check SET_POWER_CAPABLE first which is
eDP-specific DPCD register field.

[how]
Check the SET_POWER_CAPABLE register field and decide the control of the
eDP power state based on the read register value.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Agustin Gutierrez <Agustin.Gutierrez@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c    | 6 +++++-
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 7 +++++++
 drivers/gpu/drm/amd/display/dc/dc.h              | 1 +
 3 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index fac27b45230f1..82b74ee5f0c36 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1104,9 +1104,13 @@ static bool detect_link_and_local_sink(struct dc_link *link,
 				dc_ctx->dce_version == DCN_VERSION_3_01 &&
 				link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 &&
 				memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580,
-					sizeof(link->dpcd_caps.branch_dev_name)) == 0)
+					sizeof(link->dpcd_caps.branch_dev_name)) == 0) {
 				dc->config.edp_no_power_sequencing = true;
 
+				if (!link->dpcd_caps.set_power_state_capable_edp)
+					link->wa_flags.dp_keep_receiver_powered = true;
+			}
+
 			sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 			sink_caps.signal = SIGNAL_TYPE_EDP;
 			break;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index f9c10d044da6a..fd95bd51988b2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -5832,6 +5832,7 @@ void detect_edp_sink_caps(struct dc_link *link)
 	uint32_t link_rate_in_khz;
 	enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
 	uint8_t backlight_adj_cap;
+	uint8_t general_edp_cap;
 
 	retrieve_link_cap(link);
 	link->dpcd_caps.edp_supported_link_rates_count = 0;
@@ -5870,6 +5871,12 @@ void detect_edp_sink_caps(struct dc_link *link)
 	link->dpcd_caps.dynamic_backlight_capable_edp =
 				(backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
 
+	core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_1,
+						&general_edp_cap, sizeof(general_edp_cap));
+
+	link->dpcd_caps.set_power_state_capable_edp =
+				(general_edp_cap & DP_EDP_SET_POWER_CAP) ? true:false;
+
 	dc_link_set_default_brightness_aux(link);
 
 	core_link_read_dpcd(link, DP_EDP_DPCD_REV,
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index ba57e03d3d9e9..51f5d75bf9e3e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1245,6 +1245,7 @@ struct dpcd_caps {
 	bool panel_mode_edp;
 	bool dpcd_display_control_capable;
 	bool ext_receiver_cap_field_present;
+	bool set_power_state_capable_edp;
 	bool dynamic_backlight_capable_edp;
 	union dpcd_fec_capability fec_cap;
 	struct dpcd_dsc_capabilities dsc_caps;
-- 
GitLab


From 3ab55e3a1ebc22c1e0b7c72261a8c9fe78a3a09a Mon Sep 17 00:00:00 2001
From: Sung Joon Kim <sungkim@amd.com>
Date: Tue, 7 Jun 2022 14:15:06 -0400
Subject: [PATCH 0962/1731] drm/amd/display: Turn off internal backlight when
 plugging external monitor

[why]
For VG, we want to turn off power/backlight of the intenral panel when
plugging in external monitor and going to "external monitor only" mode.

[how]
For turning off power of the internal panel, ignore the config flag whic
bypasses power sequencing for eDP panels.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index fd95bd51988b2..ef771471aa39e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -7275,8 +7275,7 @@ void dp_disable_link_phy(struct dc_link *link, const struct link_resource *link_
 			link->dc->hwss.edp_backlight_control(link, false);
 		if (link_hwss->ext.disable_dp_link_output)
 			link_hwss->ext.disable_dp_link_output(link, link_res, signal);
-		if (!link->dc->config.edp_no_power_sequencing)
-			link->dc->hwss.edp_power_control(link, false);
+		link->dc->hwss.edp_power_control(link, false);
 	} else {
 		if (dmcu != NULL && dmcu->funcs->lock_phy)
 			dmcu->funcs->lock_phy(dmcu);
-- 
GitLab


From 4b33b5ffcf68de3a43e7dddc91c5dc86e6ed8587 Mon Sep 17 00:00:00 2001
From: Saaem Rizvi <SyedSaaem.Rizvi@amd.com>
Date: Thu, 9 Jun 2022 15:34:43 -0400
Subject: [PATCH 0963/1731] drm/amd/display: Add SMU logging code

[WHY]
Logging for SMU response value after the wait allows us to know
immediately what the response value was. Makes it easier to debug should
the value be anything other than OK.

[HOW]
Using the the already available DC SMU logging functions.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Saaem Rizvi <SyedSaaem.Rizvi@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c  | 12 ++++++++++++
 .../drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c   | 12 ++++++++++++
 .../gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c |  8 ++++++++
 .../drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c   |  8 ++++++++
 .../drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c   |  8 ++++++++
 5 files changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
index 30c6f9cd717f3..4137394a6ace9 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
@@ -41,6 +41,12 @@
 #define FN(reg_name, field) \
 	FD(reg_name##__##field)
 
+#include "logger_types.h"
+#undef DC_LOGGER
+#define DC_LOGGER \
+	CTX->logger
+#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
+
 #define VBIOSSMC_MSG_TestMessage                  0x1
 #define VBIOSSMC_MSG_GetSmuVersion                0x2
 #define VBIOSSMC_MSG_PowerUpGfx                   0x3
@@ -97,6 +103,12 @@ static int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
 	result = rn_smu_wait_for_response(clk_mgr, 10, 200000);
 	ASSERT(result == VBIOSSMC_Result_OK);
 
+	smu_print("SMU response after wait: %d\n", result);
+
+	if (result == VBIOSSMC_Status_BUSY) {
+		return -1;
+	}
+
 	/* First clear response register */
 	REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
index 1cae01a91a69d..d8f03328558b4 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
@@ -41,6 +41,12 @@
 #define FN(reg_name, field) \
 	FD(reg_name##__##field)
 
+#include "logger_types.h"
+#undef DC_LOGGER
+#define DC_LOGGER \
+	CTX->logger
+#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
+
 #define VBIOSSMC_MSG_GetSmuVersion                0x2
 #define VBIOSSMC_MSG_SetDispclkFreq               0x4
 #define VBIOSSMC_MSG_SetDprefclkFreq              0x5
@@ -96,6 +102,12 @@ static int dcn301_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
 
 	result = dcn301_smu_wait_for_response(clk_mgr, 10, 200000);
 
+	smu_print("SMU response after wait: %d\n", result);
+
+	if (result == VBIOSSMC_Status_BUSY) {
+		return -1;
+	}
+
 	/* First clear response register */
 	REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
index c5d7d075026f3..6a17f7ed4d01e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
@@ -40,6 +40,12 @@
 #define FN(reg_name, field) \
 	FD(reg_name##__##field)
 
+#include "logger_types.h"
+#undef DC_LOGGER
+#define DC_LOGGER \
+	CTX->logger
+#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
+
 #define VBIOSSMC_MSG_TestMessage                  0x1
 #define VBIOSSMC_MSG_GetSmuVersion                0x2
 #define VBIOSSMC_MSG_PowerUpGfx                   0x3
@@ -104,6 +110,8 @@ static int dcn31_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
 	result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000);
 	ASSERT(result == VBIOSSMC_Result_OK);
 
+	smu_print("SMU response after wait: %d\n", result);
+
 	if (result == VBIOSSMC_Status_BUSY) {
 		return -1;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
index 2600313fea579..74a78fda62fb0 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
@@ -70,6 +70,12 @@ static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D
 #define REG_NBIO(reg_name) \
 	(NBIO_BASE.instance[0].segment[regBIF_BX_PF2_ ## reg_name ## _BASE_IDX] + regBIF_BX_PF2_ ## reg_name)
 
+#include "logger_types.h"
+#undef DC_LOGGER
+#define DC_LOGGER \
+	CTX->logger
+#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
+
 #define mmMP1_C2PMSG_3                            0x3B1050C
 
 #define VBIOSSMC_MSG_TestMessage                  0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
@@ -132,6 +138,8 @@ static int dcn315_smu_send_msg_with_param(
 	result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000);
 	ASSERT(result == VBIOSSMC_Result_OK);
 
+	smu_print("SMU response after wait: %d\n", result);
+
 	if (result == VBIOSSMC_Status_BUSY) {
 		return -1;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
index dceec4b960527..b2d1f24cfb804 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
@@ -58,6 +58,12 @@ static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E0000
 #define FN(reg_name, field) \
 	FD(reg_name##__##field)
 
+#include "logger_types.h"
+#undef DC_LOGGER
+#define DC_LOGGER \
+	CTX->logger
+#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
+
 #define VBIOSSMC_MSG_TestMessage                  0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
 #define VBIOSSMC_MSG_GetPmfwVersion               0x02 ///< Get PMFW version
 #define VBIOSSMC_MSG_Spare0                       0x03 ///< Spare0
@@ -120,6 +126,8 @@ static int dcn316_smu_send_msg_with_param(
 	result = dcn316_smu_wait_for_response(clk_mgr, 10, 200000);
 	ASSERT(result == VBIOSSMC_Result_OK);
 
+	smu_print("SMU response after wait: %d\n", result);
+
 	if (result == VBIOSSMC_Status_BUSY) {
 		return -1;
 	}
-- 
GitLab


From f173fbe5b042e1c87593e3b06e85cae0094dd867 Mon Sep 17 00:00:00 2001
From: Qingqing Zhuo <qingqing.zhuo@amd.com>
Date: Fri, 10 Jun 2022 10:43:53 -0400
Subject: [PATCH 0964/1731] drm/amd/display: Fix DC warning at driver load

[Why]
Wrong index was checked for dcfclk_mhz, causing false warning.

[How]
Fix the assertion index.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
index fb4ae800e9193..f4381725b2107 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
@@ -550,7 +550,7 @@ static void dcn315_clk_mgr_helper_populate_bw_params(
 		if (!bw_params->clk_table.entries[i].dtbclk_mhz)
 			bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
 	}
-	ASSERT(bw_params->clk_table.entries[i].dcfclk_mhz);
+	ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
 	bw_params->vram_type = bios_info->memory_type;
 	bw_params->num_channels = bios_info->ma_channel_number;
 	if (!bw_params->num_channels)
-- 
GitLab


From 98dd398aa3e021896adb7f2b1d0f6b2d3784610c Mon Sep 17 00:00:00 2001
From: "JinZe.Xu" <JinZe.Xu@amd.com>
Date: Tue, 21 Jul 2020 17:52:41 +0800
Subject: [PATCH 0965/1731] drm/amd/display: Change HDMI judgement condition.

[Why & How]
Use dc_is_hdmi_signal to determine signal type.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: JinZe.Xu <JinZe.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 82b74ee5f0c36..fb6ffcb0bc6bf 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -4374,7 +4374,7 @@ void core_link_enable_stream(
 			dp_set_dsc_enable(pipe_ctx, true);
 	}
 
-	if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
+	if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
 		core_link_set_avmute(pipe_ctx, false);
 	}
 }
-- 
GitLab


From f18368b686a86477a79bc240a3a1c655d88a2348 Mon Sep 17 00:00:00 2001
From: Wenjing Liu <wenjing.liu@amd.com>
Date: Tue, 6 Oct 2020 16:22:40 -0400
Subject: [PATCH 0966/1731] drm/amd/display: Enrich the log in MST payload
 update

[Why & How]
Enrich the log to provide more informatio in MST payload update.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index fb6ffcb0bc6bf..43b55bc6e2db4 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3831,11 +3831,14 @@ enum dc_status dc_link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw
 
 	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
 		DC_LOG_MST("stream_enc[%d]: %p      "
+				"stream[%d].hpo_dp_stream_enc: %p      "
 				"stream[%d].vcp_id: %d      "
 				"stream[%d].slot_count: %d\n",
 				i,
 				(void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
 				i,
+				(void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
+				i,
 				link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
 				i,
 				link->mst_stream_alloc_table.stream_allocations[i].slot_count);
@@ -3896,11 +3899,14 @@ enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t
 
 	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
 		DC_LOG_MST("stream_enc[%d]: %p      "
+				"stream[%d].hpo_dp_stream_enc: %p      "
 				"stream[%d].vcp_id: %d      "
 				"stream[%d].slot_count: %d\n",
 				i,
 				(void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
 				i,
+				(void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
+				i,
 				link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
 				i,
 				link->mst_stream_alloc_table.stream_allocations[i].slot_count);
-- 
GitLab


From 95133f41b090b09ba9163b4469cda1d5ee230cd3 Mon Sep 17 00:00:00 2001
From: George Shen <george.shen@amd.com>
Date: Wed, 6 Oct 2021 15:47:37 -0400
Subject: [PATCH 0967/1731] drm/amd/display: Fix in overriding DP drive
 settings

[Why & How]
Check always_match_dpcd_with_hw_lane_settings bit before
overriding the DP drive settings

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index ef771471aa39e..9f873d2cdcad4 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1674,8 +1674,9 @@ static void override_training_settings(
 			: POST_CURSOR2_DISABLED;
 	}
 
-	dp_hw_to_dpcd_lane_settings(lt_settings,
-			lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
+	if (lt_settings->always_match_dpcd_with_hw_lane_settings)
+		dp_hw_to_dpcd_lane_settings(lt_settings,
+				lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
 
 	/* Initialize training timings */
 	if (overrides->cr_pattern_time != NULL)
-- 
GitLab


From 2b96b036a6a5767b84f87edc2c0a1c70c91ebac0 Mon Sep 17 00:00:00 2001
From: Wenjing Liu <wenjing.liu@amd.com>
Date: Sat, 11 Sep 2021 23:06:31 -0400
Subject: [PATCH 0968/1731] drm/amd/display: rename lane_settings to
 hw_lane_settings

[why]
This is one of the major steps to decouple hw lane settings
from dpcd lane settings.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c  |  8 ++++----
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c       | 10 +++++-----
 drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c     | 10 +++++-----
 .../gpu/drm/amd/display/include/link_service_types.h   |  1 -
 4 files changed, 14 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index c7a592d68febf..4d5824edafaad 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -540,11 +540,11 @@ static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
 
 	/* apply phy settings from user */
 	for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) {
-		link_lane_settings.lane_settings[r].VOLTAGE_SWING =
+		link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING =
 				(enum dc_voltage_swing) (param[0]);
-		link_lane_settings.lane_settings[r].PRE_EMPHASIS =
+		link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS =
 				(enum dc_pre_emphasis) (param[1]);
-		link_lane_settings.lane_settings[r].POST_CURSOR2 =
+		link_lane_settings.hw_lane_settings[r].POST_CURSOR2 =
 				(enum dc_post_cursor2) (param[2]);
 	}
 
@@ -738,7 +738,7 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us
 	}
 
 	for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
-		link_training_settings.lane_settings[i] = link->cur_lane_setting[i];
+		link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i];
 
 	dc_link_set_test_pattern(
 		link,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 9f873d2cdcad4..dfee3ba8b2342 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1660,15 +1660,15 @@ static void override_training_settings(
 		lt_settings->always_match_dpcd_with_hw_lane_settings = false;
 	}
 	for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
-		lt_settings->lane_settings[lane].VOLTAGE_SWING =
+		lt_settings->hw_lane_settings[lane].VOLTAGE_SWING =
 			lt_settings->voltage_swing != NULL ?
 			*lt_settings->voltage_swing :
 			VOLTAGE_SWING_LEVEL0;
-		lt_settings->lane_settings[lane].PRE_EMPHASIS =
+		lt_settings->hw_lane_settings[lane].PRE_EMPHASIS =
 			lt_settings->pre_emphasis != NULL ?
 			*lt_settings->pre_emphasis
 			: PRE_EMPHASIS_DISABLED;
-		lt_settings->lane_settings[lane].POST_CURSOR2 =
+		lt_settings->hw_lane_settings[lane].POST_CURSOR2 =
 			lt_settings->post_cursor2 != NULL ?
 			*lt_settings->post_cursor2
 			: POST_CURSOR2_DISABLED;
@@ -1935,8 +1935,8 @@ static void print_status_message(
 				link_rate,
 				lt_settings->link_settings.lane_count,
 				lt_result,
-				lt_settings->lane_settings[0].VOLTAGE_SWING,
-				lt_settings->lane_settings[0].PRE_EMPHASIS,
+				lt_settings->hw_lane_settings[0].VOLTAGE_SWING,
+				lt_settings->hw_lane_settings[0].PRE_EMPHASIS,
 				lt_spread);
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
index 1b7a8774b0c90..a29ebd9dbbcd1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
@@ -177,13 +177,13 @@ static uint8_t dpia_build_set_config_data(enum dpia_set_config_type type,
 		break;
 	case DPIA_SET_CFG_SET_VSPE:
 		/* Assume all lanes have same drive settings. */
-		data.set_vspe.swing = lt_settings->lane_settings[0].VOLTAGE_SWING;
-		data.set_vspe.pre_emph = lt_settings->lane_settings[0].PRE_EMPHASIS;
+		data.set_vspe.swing = lt_settings->hw_lane_settings[0].VOLTAGE_SWING;
+		data.set_vspe.pre_emph = lt_settings->hw_lane_settings[0].PRE_EMPHASIS;
 		data.set_vspe.max_swing_reached =
-			lt_settings->lane_settings[0].VOLTAGE_SWING ==
+			lt_settings->hw_lane_settings[0].VOLTAGE_SWING ==
 			VOLTAGE_SWING_MAX_LEVEL ? 1 : 0;
 		data.set_vspe.max_pre_emph_reached =
-			lt_settings->lane_settings[0].PRE_EMPHASIS ==
+			lt_settings->hw_lane_settings[0].PRE_EMPHASIS ==
 			PRE_EMPHASIS_MAX_LEVEL ? 1 : 0;
 		break;
 	default:
@@ -405,7 +405,7 @@ static enum link_training_result dpia_training_cr_non_transparent(
 
 		/* Update VS/PE. */
 		dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
-				lt_settings->lane_settings,
+				lt_settings->hw_lane_settings,
 				lt_settings->dpcd_lane_settings);
 		retry_count++;
 	}
diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h
index 23f7d7354aaa5..79fabc51c991a 100644
--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
@@ -94,7 +94,6 @@ struct link_training_settings {
 	/* TODO: turn lane settings below into mandatory fields
 	 * as initial lane configuration
 	 */
-	struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
 	enum dc_voltage_swing *voltage_swing;
 	enum dc_pre_emphasis *pre_emphasis;
 	enum dc_post_cursor2 *post_cursor2;
-- 
GitLab


From 6bad8e4a0ec8a950d10d91cb1846f3ef3e1f4ae0 Mon Sep 17 00:00:00 2001
From: Aric Cyr <aric.cyr@amd.com>
Date: Sat, 2 Oct 2021 09:44:08 -0400
Subject: [PATCH 0969/1731] drm/amd/display: Change initializer to single brace

[Why & How]
Change struct initializer from multiple brace to single brace.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  4 +--
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  6 ++--
 .../drm/amd/display/dc/core/dc_link_dpia.c    | 28 +++++++++----------
 3 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 43b55bc6e2db4..fd053d6bdf735 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1528,7 +1528,7 @@ static bool dc_link_construct_legacy(struct dc_link *link,
 				     const struct link_init_data *init_params)
 {
 	uint8_t i;
-	struct ddc_service_init_data ddc_service_init_data = { { 0 } };
+	struct ddc_service_init_data ddc_service_init_data = { 0 };
 	struct dc_context *dc_ctx = init_params->ctx;
 	struct encoder_init_data enc_init_data = { 0 };
 	struct panel_cntl_init_data panel_cntl_init_data = { 0 };
@@ -1828,7 +1828,7 @@ create_fail:
 static bool dc_link_construct_dpia(struct dc_link *link,
 				   const struct link_init_data *init_params)
 {
-	struct ddc_service_init_data ddc_service_init_data = { { 0 } };
+	struct ddc_service_init_data ddc_service_init_data = { 0 };
 	struct dc_context *dc_ctx = init_params->ctx;
 
 	DC_LOGGER_INIT(dc_ctx->logger);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index dfee3ba8b2342..76efac8300a9f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -638,7 +638,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
 	uint32_t dpcd_base_lt_offset;
 
 	uint8_t dpcd_lt_buffer[5] = {0};
-	union dpcd_training_pattern dpcd_pattern = { 0 };
+	union dpcd_training_pattern dpcd_pattern = {0};
 	uint32_t size_in_bytes;
 	bool edp_workaround = false; /* TODO link_prop.INTERNAL */
 	dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
@@ -1369,7 +1369,7 @@ static enum link_training_result perform_clock_recovery_sequence(
 	enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 	union lane_align_status_updated dpcd_lane_status_updated;
-	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
+	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
 
 	retries_cr = 0;
 	retry_count = 0;
@@ -2164,7 +2164,7 @@ static enum link_training_result dp_perform_128b_132b_cds_done_sequence(
 	enum link_training_result result = LINK_TRAINING_SUCCESS;
 	union lane_align_status_updated dpcd_lane_status_updated = {0};
 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
-	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
+	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
 	uint32_t wait_time = 0;
 
 	/* initiate CDS done sequence */
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
index a29ebd9dbbcd1..03f7249df1ef9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
@@ -226,7 +226,7 @@ static enum dc_status dpcd_set_lt_pattern(struct dc_link *link,
 	enum dc_dp_training_pattern pattern,
 	uint32_t hop)
 {
-	union dpcd_training_pattern dpcd_pattern = { {0} };
+	union dpcd_training_pattern dpcd_pattern = {0};
 	uint32_t dpcd_tps_offset = DP_TRAINING_PATTERN_SET;
 	enum dc_status status;
 
@@ -287,9 +287,9 @@ static enum link_training_result dpia_training_cr_non_transparent(
 	/* From DP spec, CR read interval is always 100us. */
 	uint32_t wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
 	enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
-	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
-	union lane_align_status_updated dpcd_lane_status_updated = { {0} };
-	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
+	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
+	union lane_align_status_updated dpcd_lane_status_updated = {0};
+	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
 	uint8_t set_cfg_data;
 	enum dpia_set_config_ts ts;
 
@@ -445,9 +445,9 @@ static enum link_training_result dpia_training_cr_transparent(
 	uint32_t retry_count = 0;
 	uint32_t wait_time_microsec = lt_settings->cr_pattern_time;
 	enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
-	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
-	union lane_align_status_updated dpcd_lane_status_updated = { {0} };
-	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
+	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
+	union lane_align_status_updated dpcd_lane_status_updated = {0};
+	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
 
 	/* Cap of LINK_TRAINING_MAX_CR_RETRY attempts at clock recovery.
 	 * Fix inherited from perform_clock_recovery_sequence() -
@@ -599,9 +599,9 @@ static enum link_training_result dpia_training_eq_non_transparent(
 	enum dc_dp_training_pattern tr_pattern;
 	uint32_t wait_time_microsec;
 	enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
-	union lane_align_status_updated dpcd_lane_status_updated = { {0} };
-	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
-	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
+	union lane_align_status_updated dpcd_lane_status_updated = {0};
+	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
+	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
 	uint8_t set_cfg_data;
 	enum dpia_set_config_ts ts;
 
@@ -738,9 +738,9 @@ static enum link_training_result dpia_training_eq_transparent(
 	enum dc_dp_training_pattern tr_pattern = lt_settings->pattern_for_eq;
 	uint32_t wait_time_microsec;
 	enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
-	union lane_align_status_updated dpcd_lane_status_updated = { {0} };
-	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
-	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
+	union lane_align_status_updated dpcd_lane_status_updated = {0};
+	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
+	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
 
 	wait_time_microsec = dpia_get_eq_aux_rd_interval(link, lt_settings, DPRX);
 
@@ -827,7 +827,7 @@ static enum link_training_result dpia_training_eq_phase(
 /* End training of specified hop in display path. */
 static enum dc_status dpcd_clear_lt_pattern(struct dc_link *link, uint32_t hop)
 {
-	union dpcd_training_pattern dpcd_pattern = { {0} };
+	union dpcd_training_pattern dpcd_pattern = {0};
 	uint32_t dpcd_tps_offset = DP_TRAINING_PATTERN_SET;
 	enum dc_status status;
 
-- 
GitLab


From a3e731260b9325e2e87baf54f07619c6cb83931b Mon Sep 17 00:00:00 2001
From: George Shen <george.shen@amd.com>
Date: Thu, 7 Oct 2021 15:59:44 -0400
Subject: [PATCH 0970/1731] drm/amd/display: Fix typo in override_lane_settings

[Why]
The function currently skips overriding the drive
settings of the first lane.

[How]
Change for loop to start at 0 instead of 1.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 76efac8300a9f..972dbbcc36da2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -944,7 +944,7 @@ static void override_lane_settings(const struct link_training_settings *lt_setti
 
 		return;
 
-	for (lane = 1; lane < LANE_COUNT_DP_MAX; lane++) {
+	for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
 		if (lt_settings->voltage_swing)
 			lane_settings[lane].VOLTAGE_SWING = *lt_settings->voltage_swing;
 		if (lt_settings->pre_emphasis)
-- 
GitLab


From 0bbd1c7de319ca5a08359e5fc901a0317bf5c0d6 Mon Sep 17 00:00:00 2001
From: George Shen <George.Shen@amd.com>
Date: Mon, 31 Jan 2022 14:31:14 -0500
Subject: [PATCH 0971/1731] drm/amd/display: Handle downstream LTTPR with fixed
 VS sequence

[Why]
Several issues were discovered that caused link
training to fail when an LTTPR device is
connected downstream for the fixed VS sequence.

[How]
The following were added:
- workaround to configure AUX timeout
for fixed VS sequence
- additional delay before disabling
fixed VS intercept
- detection of fixed VS deadlock state and
performing DPCD sequence to recover

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: George Shen <George.Shen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 43 ++++++++++++++++---
 drivers/gpu/drm/amd/display/dc/dc.h           |  2 +
 .../drm/amd/display/dc/dcn31/dcn31_resource.c |  1 -
 3 files changed, 40 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 972dbbcc36da2..c993b428ca7ea 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2384,6 +2384,7 @@ static enum link_training_result dp_perform_fixed_vs_pe_training_sequence(
 			link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
 	const uint8_t vendor_lttpr_write_data_intercept_en[4] = {0x1, 0x55, 0x63, 0x0};
 	const uint8_t vendor_lttpr_write_data_intercept_dis[4] = {0x1, 0x55, 0x63, 0x68};
+	uint32_t pre_disable_intercept_delay_ms = link->dc->debug.fixed_vs_aux_delay_config_wa;
 	uint8_t vendor_lttpr_write_data_vs[4] = {0x1, 0x51, 0x63, 0x0};
 	uint8_t vendor_lttpr_write_data_pe[4] = {0x1, 0x52, 0x63, 0x0};
 	uint32_t vendor_lttpr_write_address = 0xF004F;
@@ -2406,6 +2407,10 @@ static enum link_training_result dp_perform_fixed_vs_pe_training_sequence(
 	if (offset != 0xFF) {
 		vendor_lttpr_write_address +=
 				((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
+
+		/* Certain display and cable configuration require extra delay */
+		if (offset > 2)
+			pre_disable_intercept_delay_ms = link->dc->debug.fixed_vs_aux_delay_config_wa * 2;
 	}
 
 	/* Vendor specific: Reset lane settings */
@@ -2485,6 +2490,7 @@ static enum link_training_result dp_perform_fixed_vs_pe_training_sequence(
 
 	/* Perform Clock Recovery Sequence */
 	if (status == LINK_TRAINING_SUCCESS) {
+		const uint8_t max_vendor_dpcd_retries = 10;
 		uint32_t retries_cr;
 		uint32_t retry_count;
 		uint32_t wait_time_microsec;
@@ -2492,6 +2498,8 @@ static enum link_training_result dp_perform_fixed_vs_pe_training_sequence(
 		union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 		union lane_align_status_updated dpcd_lane_status_updated;
 		union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
+		enum dc_status dpcd_status = DC_OK;
+		uint8_t i = 0;
 
 		retries_cr = 0;
 		retry_count = 0;
@@ -2522,11 +2530,23 @@ static enum link_training_result dp_perform_fixed_vs_pe_training_sequence(
 						lt_settings->pattern_for_cr,
 						0);
 				/* Vendor specific: Disable intercept */
-				core_link_write_dpcd(
-						link,
-						vendor_lttpr_write_address,
-						&vendor_lttpr_write_data_intercept_dis[0],
-						sizeof(vendor_lttpr_write_data_intercept_dis));
+				for (i = 0; i < max_vendor_dpcd_retries; i++) {
+					msleep(pre_disable_intercept_delay_ms);
+					dpcd_status = core_link_write_dpcd(
+							link,
+							vendor_lttpr_write_address,
+							&vendor_lttpr_write_data_intercept_dis[0],
+							sizeof(vendor_lttpr_write_data_intercept_dis));
+
+					if (dpcd_status == DC_OK)
+						break;
+
+					core_link_write_dpcd(
+							link,
+							vendor_lttpr_write_address,
+							&vendor_lttpr_write_data_intercept_en[0],
+							sizeof(vendor_lttpr_write_data_intercept_en));
+				}
 			} else {
 				vendor_lttpr_write_data_vs[3] = 0;
 				vendor_lttpr_write_data_pe[3] = 0;
@@ -5190,6 +5210,19 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
 	determine_lttpr_mode(link);
 
 	if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
+		if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
+				!link->dc->debug.disable_fixed_vs_aux_timeout_wa) {
+			/* Fixed VS workaround for AUX timeout */
+			const uint32_t fixed_vs_address = 0xF004F;
+			const uint8_t fixed_vs_data[4] = {0x1, 0x22, 0x63, 0xc};
+
+			core_link_write_dpcd(
+					link,
+					fixed_vs_address,
+					fixed_vs_data,
+					sizeof(fixed_vs_data));
+		}
+
 		/* By reading LTTPR capability, RX assumes that we will enable
 		 * LTTPR extended aux timeout if LTTPR is present.
 		 */
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 51f5d75bf9e3e..236a204d41adc 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -737,6 +737,8 @@ struct dc_debug_options {
 	bool enable_z9_disable_interface;
 	bool enable_sw_cntl_psr;
 	union dpia_debug_options dpia_debug;
+	bool disable_fixed_vs_aux_timeout_wa;
+	uint32_t fixed_vs_aux_delay_config_wa;
 	bool force_disable_subvp;
 	bool force_subvp_mclk_switch;
 	bool force_usr_allow;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index a67475251188f..1a67d04cc0178 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -890,7 +890,6 @@ static const struct dc_debug_options debug_defaults_drv = {
 	.disable_z10 = true,
 	.optimize_edp_link_rate = true,
 	.enable_sw_cntl_psr = true,
-	.apply_vendor_specific_lttpr_wa = true,
 	.enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
 	.dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE,
 };
-- 
GitLab


From 20cb72174ddcc86596286784416adb947195e45c Mon Sep 17 00:00:00 2001
From: George Shen <George.Shen@amd.com>
Date: Fri, 11 Feb 2022 14:13:01 -0500
Subject: [PATCH 0972/1731] drm/amd/display: Remove unused vendor specific w/a

[Why & How]
Old vendor specific w/a are no longer needed and unused. Clean up
codebase by removing them.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 133 +-----------------
 drivers/gpu/drm/amd/display/dc/dc.h           |   1 -
 2 files changed, 4 insertions(+), 130 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index c993b428ca7ea..76233db6876cc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -329,51 +329,6 @@ static uint8_t get_dpcd_link_rate(const struct dc_link_settings *link_settings)
 	return link_rate;
 }
 
-static void vendor_specific_lttpr_wa_one_start(struct dc_link *link)
-{
-	const uint8_t vendor_lttpr_write_data[4] = {0x1, 0x50, 0x63, 0xff};
-	const uint8_t offset = dp_convert_to_count(
-			link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
-	uint32_t vendor_lttpr_write_address = 0xF004F;
-
-	if (offset != 0xFF)
-		vendor_lttpr_write_address +=
-				((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
-
-	/* W/A for certain LTTPR to reset their lane settings, part one of two */
-	core_link_write_dpcd(
-			link,
-			vendor_lttpr_write_address,
-			&vendor_lttpr_write_data[0],
-			sizeof(vendor_lttpr_write_data));
-}
-
-static void vendor_specific_lttpr_wa_one_two(
-	struct dc_link *link,
-	const uint8_t rate)
-{
-	if (link->apply_vendor_specific_lttpr_link_rate_wa) {
-		uint8_t toggle_rate = 0x0;
-
-		if (rate == 0x6)
-			toggle_rate = 0xA;
-		else
-			toggle_rate = 0x6;
-
-		if (link->vendor_specific_lttpr_link_rate_wa == rate) {
-			/* W/A for certain LTTPR to reset internal state for link training */
-			core_link_write_dpcd(
-					link,
-					DP_LINK_BW_SET,
-					&toggle_rate,
-					1);
-		}
-
-		/* Store the last attempted link rate for this link */
-		link->vendor_specific_lttpr_link_rate_wa = rate;
-	}
-}
-
 static void dp_fixed_vs_pe_read_lane_adjust(
 	struct dc_link *link,
 	union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX])
@@ -423,51 +378,6 @@ static void dp_fixed_vs_pe_read_lane_adjust(
 	}
 }
 
-static void vendor_specific_lttpr_wa_four(
-	struct dc_link *link,
-	bool apply_wa)
-{
-	const uint8_t vendor_lttpr_write_data_one[4] = {0x1, 0x55, 0x63, 0x8};
-	const uint8_t vendor_lttpr_write_data_two[4] = {0x1, 0x55, 0x63, 0x0};
-	const uint8_t offset = dp_convert_to_count(
-			link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
-	uint32_t vendor_lttpr_write_address = 0xF004F;
-	uint8_t sink_status = 0;
-	uint8_t i;
-
-	if (offset != 0xFF)
-		vendor_lttpr_write_address +=
-				((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
-
-	/* W/A to pass through DPCD write of TPS=0 to DPRX */
-	if (apply_wa) {
-		core_link_write_dpcd(
-				link,
-				vendor_lttpr_write_address,
-				&vendor_lttpr_write_data_one[0],
-				sizeof(vendor_lttpr_write_data_one));
-	}
-
-	/* clear training pattern set */
-	dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
-
-	if (apply_wa) {
-		core_link_write_dpcd(
-				link,
-				vendor_lttpr_write_address,
-				&vendor_lttpr_write_data_two[0],
-				sizeof(vendor_lttpr_write_data_two));
-	}
-
-	/* poll for intra-hop disable */
-	for (i = 0; i < 10; i++) {
-		if ((core_link_read_dpcd(link, DP_SINK_STATUS, &sink_status, 1) == DC_OK) &&
-				(sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION) == 0)
-			break;
-		udelay(1000);
-	}
-}
-
 static void dp_fixed_vs_pe_set_retimer_lane_settings(
 	struct dc_link *link,
 	const union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX],
@@ -561,14 +471,6 @@ enum dc_status dpcd_set_link_settings(
 				&lt_settings->link_settings.link_rate_set, 1);
 	} else {
 		rate = get_dpcd_link_rate(&lt_settings->link_settings);
-		if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
-					(link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
-					link->lttpr_mode == LTTPR_MODE_TRANSPARENT)
-			vendor_specific_lttpr_wa_one_start(link);
-
-		if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
-					(link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN))
-			vendor_specific_lttpr_wa_one_two(link, rate);
 
 		status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 	}
@@ -1303,12 +1205,6 @@ static enum link_training_result perform_channel_equalization_sequence(
 					dp_translate_training_aux_read_interval(
 						link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
 
-		if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
-				(link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
-				link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
-			wait_time_microsec = 16000;
-		}
-
 		dp_wait_for_training_aux_rd_interval(
 				link,
 				wait_time_microsec);
@@ -1415,11 +1311,6 @@ static enum link_training_result perform_clock_recovery_sequence(
 		/* 3. wait receiver to lock-on*/
 		wait_time_microsec = lt_settings->cr_pattern_time;
 
-		if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
-				(link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN)) {
-			wait_time_microsec = 16000;
-		}
-
 		dp_wait_for_training_aux_rd_interval(
 				link,
 				wait_time_microsec);
@@ -2752,14 +2643,7 @@ enum link_training_result dc_link_dp_perform_link_training(
 			&lt_settings);
 
 	/* reset previous training states */
-	if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
-			(link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
-			link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
-		link->apply_vendor_specific_lttpr_link_rate_wa = true;
-		vendor_specific_lttpr_wa_four(link, true);
-	} else {
-		dpcd_exit_training_mode(link);
-	}
+	dpcd_exit_training_mode(link);
 
 	/* configure link prior to entering training mode */
 	dpcd_configure_lttpr_mode(link, &lt_settings);
@@ -2780,14 +2664,7 @@ enum link_training_result dc_link_dp_perform_link_training(
 		ASSERT(0);
 
 	/* exit training mode */
-	if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
-			(link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
-			link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
-		link->apply_vendor_specific_lttpr_link_rate_wa = false;
-		vendor_specific_lttpr_wa_four(link, (status != LINK_TRAINING_SUCCESS));
-	} else {
-		dpcd_exit_training_mode(link);
-	}
+	dpcd_exit_training_mode(link);
 
 	/* switch to video idle */
 	if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern)
@@ -4227,8 +4104,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
 			&dpcd_lane_adjustment[0].raw,
 			sizeof(dpcd_lane_adjustment));
 
-	if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
-			(link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
+	if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
 			link->lttpr_mode == LTTPR_MODE_TRANSPARENT)
 		dp_fixed_vs_pe_read_lane_adjust(
 				link,
@@ -6198,8 +6074,7 @@ bool dc_link_dp_set_test_pattern(
 	if (is_dp_phy_pattern(test_pattern)) {
 		/* Set DPCD Lane Settings before running test pattern */
 		if (p_link_settings != NULL) {
-			if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
-					(link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
+			if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
 					link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
 				dp_fixed_vs_pe_set_retimer_lane_settings(
 						link,
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 236a204d41adc..81e308d59a978 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -744,7 +744,6 @@ struct dc_debug_options {
 	bool force_usr_allow;
 	/* uses value at boot and disables switch */
 	bool disable_dtb_ref_clk_switch;
-	bool apply_vendor_specific_lttpr_wa;
 	bool extended_blank_optimization;
 	union aux_wake_wa_options aux_wake_wa;
 	uint8_t psr_power_use_phy_fsm;
-- 
GitLab


From 990cad0e4a9df4202cd482c192608caf6408e4b3 Mon Sep 17 00:00:00 2001
From: Wenjing Liu <wenjing.liu@amd.com>
Date: Fri, 25 Mar 2022 16:12:14 -0400
Subject: [PATCH 0973/1731] drm/amd/display: extract update stream allocation
 to link_hwss

[Why & How]
Extract update stream allocation table into link hwss as part of the
link hwss refactor work.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  | 10 +++++++---
 drivers/gpu/drm/amd/display/dc/inc/link_hwss.h |  6 +++---
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index fd053d6bdf735..1206a3dd746f9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3871,7 +3871,6 @@ enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t
 	struct fixed31_32 avg_time_slots_per_mtp;
 	struct fixed31_32 pbn;
 	struct fixed31_32 pbn_per_slot;
-	struct link_encoder *link_encoder = link->link_enc;
 	struct dp_mst_stream_allocation_table proposed_table = {0};
 	uint8_t i;
 	enum act_return_status ret;
@@ -3915,8 +3914,13 @@ enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t
 	ASSERT(proposed_table.stream_count > 0);
 
 	/* update mst stream allocation table hardware state */
-	link_encoder->funcs->update_mst_stream_allocation_table(
-			link_encoder,
+	if (link_hwss->ext.update_stream_allocation_table == NULL ||
+			dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
+		DC_LOG_ERROR("Failure: unknown encoding format\n");
+		return DC_ERROR_UNEXPECTED;
+	}
+
+	link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
 			&link->mst_stream_alloc_table);
 
 	/* poll for immediate branch device ACT handled */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
index e6c49ef8b5849..3482a877b6af5 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
@@ -62,9 +62,9 @@ struct link_hwss_ext {
 			const struct link_resource *link_res,
 			struct encoder_set_dp_phy_pattern_param *tp_params);
 	void (*set_dp_lane_settings)(struct dc_link *link,
-		const struct link_resource *link_res,
-		const struct dc_link_settings *link_settings,
-		const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
+			const struct link_resource *link_res,
+			const struct dc_link_settings *link_settings,
+			const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
 	void (*update_stream_allocation_table)(struct dc_link *link,
 			const struct link_resource *link_res,
 			const struct link_mst_stream_allocation_table *table);
-- 
GitLab


From a30e8c13e7affd6fe379c6bf213133b0f917d1bf Mon Sep 17 00:00:00 2001
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Date: Tue, 15 Jun 2021 15:11:31 -0400
Subject: [PATCH 0974/1731] drm/amd/display: Fix in dp link-training when
 updating payload allocation table

[Why & How]
Check if aux is not accessible before updating payload allocation table.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 76233db6876cc..4027f439a5a40 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -6823,6 +6823,13 @@ bool dpcd_write_128b_132b_sst_payload_allocation_table(
 		/// Leave req_slot_count = 0 if allocate is false.
 	}
 
+	proposed_table->stream_count = 1; /// Always 1 stream for SST
+	proposed_table->stream_allocations[0].slot_count = req_slot_count;
+	proposed_table->stream_allocations[0].vcp_id = vc_id;
+
+	if (link->aux_access_disabled)
+		return true;
+
 	/// Write DPCD 2C0 = 1 to start updating
 	update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1;
 	core_link_write_dpcd(
@@ -6890,10 +6897,6 @@ bool dpcd_write_128b_132b_sst_payload_allocation_table(
 		// TODO - DP2.0 Payload: Read and log the payload table from downstream branch
 	}
 
-	proposed_table->stream_count = 1; /// Always 1 stream for SST
-	proposed_table->stream_allocations[0].slot_count = req_slot_count;
-	proposed_table->stream_allocations[0].vcp_id = vc_id;
-
 	return result;
 }
 
@@ -6909,6 +6912,8 @@ bool dpcd_poll_for_allocation_change_trigger(struct dc_link *link)
 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 	union lane_align_status_updated lane_status_updated;
 
+	if (link->aux_access_disabled)
+		return true;
 	for (i = 0; i < act_retries; i++) {
 		get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated);
 
-- 
GitLab


From 074efb5cadcb3c9e40d536a730318bfab3384cad Mon Sep 17 00:00:00 2001
From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Date: Tue, 14 Jun 2022 09:04:53 -0400
Subject: [PATCH 0975/1731] drm/amd/display: Check minimum disp_clk and dpp_clk
 debug option

Our debug struct has the min_disp_clk_khz and min_dpp_clk_khz options,
which we ignore in the DCN32. This commit introduces those checks and
the necessary calculation.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Aurabindo Jayamohanan Pillai <Aurabindo.Pillai@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c  | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index ed70ae10bdb1f..b32880afb3fb3 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -265,6 +265,25 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
 			&clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
 			&num_levels);
 
+	if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {
+		unsigned int i;
+
+		for (i = 0; i < num_levels; i++)
+			if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
+					< khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))
+				clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
+					= khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);
+	}
+
+	if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {
+		unsigned int i;
+
+		for (i = 0; i < num_levels; i++)
+			if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
+					< khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))
+				clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
+					= khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);
+	}
 
 	/* Get UCLK, update bounding box */
 	clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
-- 
GitLab


From 04e6931a76e592e66e1014ffe4d13303ccac5d8b Mon Sep 17 00:00:00 2001
From: Alvin Lee <Alvin.Lee2@amd.com>
Date: Fri, 6 May 2022 15:57:09 -0400
Subject: [PATCH 0976/1731] drm/amd/display: Update DPPCLK programming sequence

[Description]
- When lowering DPPCLK, we want to program the DPP DTO before updating
the DPP refclk.
- Also update DPPCLK to the exact frequency that will be set after clock
divider has been programmed. This will prevent rounding errors when
making the request to PMFW (we need DPP DTO to match exactly with the
exact DPP refclk).

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c  | 25 ++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index b32880afb3fb3..bab85f3c9c675 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -325,6 +325,26 @@ static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
 	}
 }
 
+/* Since DPPCLK request to PMFW needs to be exact (due to DPP DTO programming),
+ * update DPPCLK to be the exact frequency that will be set after the DPPCLK
+ * divider is updated. This will prevent rounding issues that could cause DPP
+ * refclk and DPP DTO to not match up.
+ */
+static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks)
+{
+	int dpp_divider = 0;
+	int disp_divider = 0;
+
+	dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+			* clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz;
+	disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+			* clk_mgr->base.dentist_vco_freq_khz / new_clocks->dispclk_khz;
+
+	// Divide back the previous result to round up to the actual clock value that will be set from divider
+	new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
+	new_clocks->dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
+}
+
 static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 			struct dc_state *context,
 			bool safe_to_lower)
@@ -448,13 +468,14 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 		}
 	}
 
+	dcn32_update_dppclk_dispclk_freq(clk_mgr, new_clocks);
 	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
 		if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
 			dpp_clock_lowered = true;
 
 		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
 
-		if (clk_mgr->smu_present)
+		if (clk_mgr->smu_present && !dpp_clock_lowered)
 			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
 
 		update_dppclk = true;
@@ -488,6 +509,8 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 			/* if clock is being lowered, increase DTO before lowering refclk */
 			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 			dcn20_update_clocks_update_dentist(clk_mgr, context);
+			if (clk_mgr->smu_present)
+				dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
 		} else {
 			/* if clock is being raised, increase refclk before lowering DTO */
 			if (update_dppclk || update_dispclk)
-- 
GitLab


From a3a885878e74d3d81e4742f8dd84faa27c8863ad Mon Sep 17 00:00:00 2001
From: George Shen <george.shen@amd.com>
Date: Fri, 20 May 2022 11:55:10 -0400
Subject: [PATCH 0977/1731] drm/amd/display: Fix divide-by-zero in DPPCLK and
 DISPCLK calculation

[Why]
Certain use cases will pass in zero in the new_clocks parameter for all
clocks. This results in a divide-by-zero error when attempting to round
up the new clock.

When new_clocks are zero, no rounding is required, so we can skip it.

[How]
Guard the division calculation with a check to make sure clocks are not
zero.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c   | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index bab85f3c9c675..8ece88ddfb5bd 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -335,14 +335,16 @@ static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, s
 	int dpp_divider = 0;
 	int disp_divider = 0;
 
-	dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
-			* clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz;
-	disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
-			* clk_mgr->base.dentist_vco_freq_khz / new_clocks->dispclk_khz;
-
-	// Divide back the previous result to round up to the actual clock value that will be set from divider
-	new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
-	new_clocks->dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
+	if (new_clocks->dppclk_khz) {
+		dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+				* clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz;
+		new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
+	}
+	if (new_clocks->dispclk_khz > 0) {
+		disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+				* clk_mgr->base.dentist_vco_freq_khz / new_clocks->dispclk_khz;
+		new_clocks->dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
+	}
 }
 
 static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
-- 
GitLab


From 32e8ab05ed81c995b92f12b590c12ef951ca1129 Mon Sep 17 00:00:00 2001
From: Alvin Lee <Alvin.Lee2@amd.com>
Date: Wed, 25 May 2022 13:34:07 -0400
Subject: [PATCH 0978/1731] drm/amd/display: Update SW state correctly for FCLK

FCLK not supported for DCN321, but still need to update the software
state accordingly to prevent unneeded full updates in driver

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c    | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 8ece88ddfb5bd..90ba9576a6fb0 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -431,12 +431,12 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 						clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
 		}
 
-		if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 &&
-				should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) {
+		if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) &&
+				clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21) {
 			clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
 
 			/* To disable FCLK P-state switching, send FCLK_PSTATE_NOTSUPPORTED message to PMFW */
-			if (!clk_mgr_base->clks.fclk_p_state_change_support) {
+			if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && !clk_mgr_base->clks.fclk_p_state_change_support) {
 				/* Handle code for sending a message to PMFW that FCLK P-state change is not supported */
 				dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED);
 			}
-- 
GitLab


From 3e838f7ccf64b0e33a2f6d1c66158cc5ab04c86f Mon Sep 17 00:00:00 2001
From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Date: Tue, 14 Jun 2022 09:51:08 -0400
Subject: [PATCH 0979/1731] drm/amd/display: Get VCO frequency from registers

Add support to get VCO frequency from registers.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Aurabindo Jayamohanan Pillai <Aurabindo.Pillai@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c  | 94 ++++++++++++++++++-
 .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h   |  3 +
 2 files changed, 96 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 90ba9576a6fb0..e3abadeca0a6f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -531,6 +531,96 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 				clk_mgr_base->clks.dispclk_khz / 1000 / 7);
 }
 
+static uint32_t dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
+{
+		struct fixed31_32 pll_req;
+		uint32_t pll_req_reg = 0;
+
+		/* get FbMult value */
+		if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev))
+			pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
+		else
+			pll_req_reg = REG_READ(CLK1_CLK_PLL_REQ);
+
+		/* set up a fixed-point number
+		 * this works because the int part is on the right edge of the register
+		 * and the frac part is on the left edge
+		 */
+			pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
+		pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
+
+		/* multiply by REFCLK period */
+		pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
+
+		return dc_fixpt_floor(pll_req);
+}
+
+static void dcn32_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
+		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	uint32_t dprefclk_did = 0;
+	uint32_t dcfclk_did = 0;
+	uint32_t dtbclk_did = 0;
+	uint32_t dispclk_did = 0;
+	uint32_t dppclk_did = 0;
+	uint32_t target_div = 0;
+
+	if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
+		/* DFS Slice 0 is used for DISPCLK */
+		dispclk_did = REG_READ(CLK0_CLK0_DFS_CNTL);
+		/* DFS Slice 1 is used for DPPCLK */
+		dppclk_did = REG_READ(CLK0_CLK1_DFS_CNTL);
+		/* DFS Slice 2 is used for DPREFCLK */
+		dprefclk_did = REG_READ(CLK0_CLK2_DFS_CNTL);
+		/* DFS Slice 3 is used for DCFCLK */
+		dcfclk_did = REG_READ(CLK0_CLK3_DFS_CNTL);
+		/* DFS Slice 4 is used for DTBCLK */
+		dtbclk_did = REG_READ(CLK0_CLK4_DFS_CNTL);
+	} else {
+		/* DFS Slice 0 is used for DISPCLK */
+		dispclk_did = REG_READ(CLK1_CLK0_DFS_CNTL);
+		/* DFS Slice 1 is used for DPPCLK */
+		dppclk_did = REG_READ(CLK1_CLK1_DFS_CNTL);
+		/* DFS Slice 2 is used for DPREFCLK */
+		dprefclk_did = REG_READ(CLK1_CLK2_DFS_CNTL);
+		/* DFS Slice 3 is used for DCFCLK */
+		dcfclk_did = REG_READ(CLK1_CLK3_DFS_CNTL);
+		/* DFS Slice 4 is used for DTBCLK */
+		dtbclk_did = REG_READ(CLK1_CLK4_DFS_CNTL);
+	}
+
+	/* Convert DISPCLK DFS Slice DID to divider*/
+	target_div = dentist_get_divider_from_did(dispclk_did);
+	//Get dispclk in khz
+	regs_and_bypass->dispclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+			* clk_mgr->base.dentist_vco_freq_khz) / target_div;
+
+	/* Convert DISPCLK DFS Slice DID to divider*/
+	target_div = dentist_get_divider_from_did(dppclk_did);
+	//Get dppclk in khz
+	regs_and_bypass->dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+			* clk_mgr->base.dentist_vco_freq_khz) / target_div;
+
+	/* Convert DPREFCLK DFS Slice DID to divider*/
+	target_div = dentist_get_divider_from_did(dprefclk_did);
+	//Get dprefclk in khz
+	regs_and_bypass->dprefclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+			* clk_mgr->base.dentist_vco_freq_khz) / target_div;
+
+	/* Convert DCFCLK DFS Slice DID to divider*/
+	target_div = dentist_get_divider_from_did(dcfclk_did);
+	//Get dcfclk in khz
+	regs_and_bypass->dcfclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+			* clk_mgr->base.dentist_vco_freq_khz) / target_div;
+
+	/* Convert DTBCLK DFS Slice DID to divider*/
+	target_div = dentist_get_divider_from_did(dtbclk_did);
+	//Get dtbclk in khz
+	regs_and_bypass->dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+			* clk_mgr->base.dentist_vco_freq_khz) / target_div;
+}
+
 static void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)
 {
 	struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
@@ -680,6 +770,7 @@ static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base)
 static struct clk_mgr_funcs dcn32_funcs = {
 		.get_dp_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
 		.update_clocks = dcn32_update_clocks,
+		.dump_clk_registers = dcn32_dump_clk_registers,
 		.init_clocks = dcn32_init_clocks,
 		.notify_wm_ranges = dcn32_notify_wm_ranges,
 		.set_hard_min_memclk = dcn32_set_hard_min_memclk,
@@ -730,7 +821,8 @@ void dcn32_clk_mgr_construct(
 	}
 
 	/* integer part is now VCO frequency in kHz */
-	clk_mgr->base.dentist_vco_freq_khz = 4300000;//dcn32_get_vco_frequency_from_reg(clk_mgr);
+	clk_mgr->base.dentist_vco_freq_khz = dcn32_get_vco_frequency_from_reg(clk_mgr);
+
 	/* in case we don't get a value from the register, use default */
 	if (clk_mgr->base.dentist_vco_freq_khz == 0)
 		clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index 4dd461e6c14ba..9ae9439c8f7b2 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -245,6 +245,9 @@ struct clk_mgr_funcs {
 
 	void (*init_clocks)(struct clk_mgr *clk_mgr);
 
+	void (*dump_clk_registers)(struct clk_state_registers_and_bypass *regs_and_bypass,
+			struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info);
+
 	void (*enable_pme_wa) (struct clk_mgr *clk_mgr);
 	void (*get_clock)(struct clk_mgr *clk_mgr,
 			struct dc_state *context,
-- 
GitLab


From aeb73c608c5b7fa6fad6d98694323e7629e93cce Mon Sep 17 00:00:00 2001
From: Chaitanya Dhere <chaitanya.dhere@amd.com>
Date: Thu, 14 Apr 2022 13:24:11 -0400
Subject: [PATCH 0980/1731] drm/amd/display: Implement a pme workaround
 function

[Why]
For DCN32 we do not have a pme workaround function defined that sends a
BacoAudio message. Default code had uses the DCN30 function for pme
workaround. PMFW headers are inconsistent with their message ID
definitions which cause ID's to clash leading to inconsistent system
behaviour. There is a clash with FCLK message due to inconsitent PMFW
headers.

[How]
Implement a new BacoAudio function to workaround the problem of
inconsistent PMFW headers in order to avoid BacoAudio message clasing
with FCLK Enable message.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c  | 2 +-
 .../amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c  | 8 ++++++++
 .../amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h  | 1 +
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index e3abadeca0a6f..b31adf5238d0a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -757,7 +757,7 @@ static void dcn32_enable_pme_wa(struct clk_mgr *clk_mgr_base)
 	if (!clk_mgr->smu_present)
 		return;
 
-	dcn30_smu_set_pme_workaround(clk_mgr);
+	dcn32_smu_set_pme_workaround(clk_mgr);
 }
 
 static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
index d7c99e9179be5..67ed8bf4510b7 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
@@ -115,6 +115,14 @@ void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
 			DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL);
 }
 
+void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr)
+{
+	smu_print("SMU Set PME workaround\n");
+
+	dcn32_smu_send_msg_with_param(clk_mgr,
+		DALSMC_MSG_BacoAudioD3PME, 0, NULL);
+}
+
 /* Returns the actual frequency that was set in MHz, 0 on failure */
 unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
index 352435edbd79a..a68038a41972f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
@@ -39,6 +39,7 @@
 void
 dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable);
 void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
+void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);
 void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways);
 void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
 unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);
-- 
GitLab


From 2d7a1ef85d013699ef60068a9f37ab56ffb33c32 Mon Sep 17 00:00:00 2001
From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Date: Tue, 14 Jun 2022 10:11:47 -0400
Subject: [PATCH 0981/1731] drm/amd/display: Update hook dcn32_funcs

In DCN32 clk hook functions, we are using the wrong reference for
get_dp_ref_clk_frequency and missing the get_dtb_ref_clk_frequency
reference. This commit adds those references.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index b31adf5238d0a..113f93b3d3b27 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -768,7 +768,8 @@ static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base)
 
 
 static struct clk_mgr_funcs dcn32_funcs = {
-		.get_dp_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
+		.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
+		.get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
 		.update_clocks = dcn32_update_clocks,
 		.dump_clk_registers = dcn32_dump_clk_registers,
 		.init_clocks = dcn32_init_clocks,
-- 
GitLab


From 2b2db1f9dbfbc61116fec83a51d16fd0cf49b61b Mon Sep 17 00:00:00 2001
From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Date: Tue, 14 Jun 2022 10:18:27 -0400
Subject: [PATCH 0982/1731] drm/amd/display: Drop duplicate define

We already have DALSMC_MSG_TransferTableDram2Smu in the file dalsmc.h;
for this reason, we don't need this definition in the smu msg file.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c    | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
index 67ed8bf4510b7..3137b987f0a0f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
@@ -34,8 +34,6 @@
 #define mmDAL_ARG_REG  0x16273
 #define mmDAL_RESP_REG 0x16274
 
-#define DALSMC_MSG_TransferTableDram2Smu          0x8
-
 #define REG(reg_name) \
 	mm ## reg_name
 
-- 
GitLab


From dc597268225b2e39bca0bc0c5394e3e6266be2e3 Mon Sep 17 00:00:00 2001
From: Aric Cyr <aric.cyr@amd.com>
Date: Sun, 12 Jun 2022 20:06:32 -0400
Subject: [PATCH 0983/1731] drm/amd/display: 3.2.191

This DC patchset brings improvements in multiple areas. In summary, we
highlight:

- Remove unnecessary code;
- Small fixes (compilation warnings, typos, etc);
- Improvements in the DPMS code;
- Fix eDP issues
- Improvements in the MST code

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 81e308d59a978..8292f27c15162 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -47,7 +47,7 @@ struct aux_payload;
 struct set_config_cmd_payload;
 struct dmub_notification;
 
-#define DC_VER "3.2.190"
+#define DC_VER "3.2.191"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
GitLab


From 43af2220b3302bc04d72bdf07970ebc0fc46155b Mon Sep 17 00:00:00 2001
From: Joshua Ashton <joshua@froggi.es>
Date: Thu, 16 Jun 2022 01:21:27 +0000
Subject: [PATCH 0984/1731] amd/display/dc: Fix COLOR_ENCODING and COLOR_RANGE
 doing nothing for DCN20+

For DCN20 and above, the code that actually hooks up the provided
input_color_space got lost at some point.

Fixes COLOR_ENCODING and COLOR_RANGE doing nothing on DCN20+.
Tested using Steam Remote Play Together + gamescope.

Update other DCNs the same wasy DCN1.x was updates in
commit a1e07ba89d49 ("drm/amd/display: Use plane->color_space for dpp if specified")

Fixes: a1e07ba89d49 ("drm/amd/display: Use plane->color_space for dpp if specified")
Signed-off-by: Joshua Ashton <joshua@froggi.es>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c   | 3 +++
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c | 3 +++
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c   | 3 +++
 3 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
index 970b65efeac10..eaa7032f0f1a3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
@@ -212,6 +212,9 @@ static void dpp2_cnv_setup (
 		break;
 	}
 
+	/* Set default color space based on format if none is given. */
+	color_space = input_color_space ? input_color_space : color_space;
+
 	if (is_2bit == 1 && alpha_2bit_lut != NULL) {
 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
index 8b6505b7dca86..f50ab961bc174 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
@@ -153,6 +153,9 @@ static void dpp201_cnv_setup(
 		break;
 	}
 
+	/* Set default color space based on format if none is given. */
+	color_space = input_color_space ? input_color_space : color_space;
+
 	if (is_2bit == 1 && alpha_2bit_lut != NULL) {
 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
index 9cca59bf2ae0a..3c77949b81106 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
@@ -294,6 +294,9 @@ void dpp3_cnv_setup (
 		break;
 	}
 
+	/* Set default color space based on format if none is given. */
+	color_space = input_color_space ? input_color_space : color_space;
+
 	if (is_2bit == 1 && alpha_2bit_lut != NULL) {
 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
-- 
GitLab


From 83a3439ddb28e15afa66f52650cf3c1486ae6515 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Mon, 20 Jun 2022 11:43:35 +0200
Subject: [PATCH 0985/1731] drm/amdgpu: Drop CONFIG_BACKLIGHT_CLASS_DEVICE
 ifdefs

The DRM_AMDGPU Kconfig code contains:

	select BACKLIGHT_CLASS_DEVICE

So the condition these ifdefs test for is always true, drop them.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c          |  6 ------
 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h          |  4 ----
 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c    | 14 --------------
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 +--------------
 4 files changed, 1 insertion(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 98ac53ee6bb55..130060834b4e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -66,9 +66,7 @@ struct amdgpu_atif {
 	struct amdgpu_atif_notifications notifications;
 	struct amdgpu_atif_functions functions;
 	struct amdgpu_atif_notification_cfg notification_cfg;
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 	struct backlight_device *bd;
-#endif
 	struct amdgpu_dm_backlight_caps backlight_caps;
 };
 
@@ -436,7 +434,6 @@ static int amdgpu_atif_handler(struct amdgpu_device *adev,
 		DRM_DEBUG_DRIVER("ATIF: %d pending SBIOS requests\n", count);
 
 		if (req.pending & ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST) {
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 			if (atif->bd) {
 				DRM_DEBUG_DRIVER("Changing brightness to %d\n",
 						 req.backlight_level);
@@ -447,7 +444,6 @@ static int amdgpu_atif_handler(struct amdgpu_device *adev,
 				 */
 				backlight_device_set_brightness(atif->bd, req.backlight_level);
 			}
-#endif
 		}
 
 		if (req.pending & ATIF_DGPU_DISPLAY_EVENT) {
@@ -849,7 +845,6 @@ int amdgpu_acpi_init(struct amdgpu_device *adev)
 {
 	struct amdgpu_atif *atif = &amdgpu_acpi_priv.atif;
 
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 	if (atif->notifications.brightness_change) {
 		if (amdgpu_device_has_dc_support(adev)) {
 #if defined(CONFIG_DRM_AMD_DC)
@@ -876,7 +871,6 @@ int amdgpu_acpi_init(struct amdgpu_device *adev)
 			}
 		}
 	}
-#endif
 	adev->acpi_nb.notifier_call = amdgpu_acpi_event;
 	register_acpi_notifier(&adev->acpi_nb);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index f80b4838cea15..dbe2904e015b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -349,15 +349,11 @@ struct amdgpu_mode_info {
 
 #define AMDGPU_MAX_BL_LEVEL 0xFF
 
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
-
 struct amdgpu_backlight_privdata {
 	struct amdgpu_encoder *encoder;
 	uint8_t negative;
 };
 
-#endif
-
 struct amdgpu_atom_ss {
 	uint16_t percentage;
 	uint16_t percentage_divider;
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
index d4f5a584075d7..fa7421afb9a6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
@@ -118,8 +118,6 @@ amdgpu_atombios_encoder_set_backlight_level(struct amdgpu_encoder *amdgpu_encode
 	}
 }
 
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
-
 static u8 amdgpu_atombios_encoder_backlight_level(struct backlight_device *bd)
 {
 	u8 level;
@@ -251,18 +249,6 @@ amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder *amdgpu_encoder)
 	}
 }
 
-#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
-
-void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *encoder)
-{
-}
-
-void amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder *encoder)
-{
-}
-
-#endif
-
 bool amdgpu_atombios_encoder_is_digital(struct drm_encoder *encoder)
 {
 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b3ab2a3ea29c5..beadd75ab93d8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3862,9 +3862,6 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
 
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
-	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
-
 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
 					    int bl_idx)
 {
@@ -4068,7 +4065,6 @@ amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
 	else
 		DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
 }
-#endif
 
 static int initialize_plane(struct amdgpu_display_manager *dm,
 			    struct amdgpu_mode_info *mode_info, int plane_id,
@@ -4114,9 +4110,6 @@ static int initialize_plane(struct amdgpu_display_manager *dm,
 static void register_backlight_device(struct amdgpu_display_manager *dm,
 				      struct dc_link *link)
 {
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
-	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
-
 	if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
 	    link->type != dc_connection_none) {
 		/*
@@ -4132,7 +4125,6 @@ static void register_backlight_device(struct amdgpu_display_manager *dm,
 			dm->num_of_edps++;
 		}
 	}
-#endif
 }
 
 
@@ -7064,15 +7056,12 @@ static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
 	if (aconnector->mst_mgr.dev)
 		drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
 
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
-	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 	for (i = 0; i < dm->num_of_edps; i++) {
 		if ((link == dm->backlight_link[i]) && dm->backlight_dev[i]) {
 			backlight_device_unregister(dm->backlight_dev[i]);
 			dm->backlight_dev[i] = NULL;
 		}
 	}
-#endif
 
 	if (aconnector->dc_em_sink)
 		dc_sink_release(aconnector->dc_em_sink);
@@ -10155,15 +10144,13 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
 	/* Update audio instances for each connector. */
 	amdgpu_dm_commit_audio(dev, state);
 
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||		\
-	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 	/* restore the backlight level */
 	for (i = 0; i < dm->num_of_edps; i++) {
 		if (dm->backlight_dev[i] &&
 		    (dm->actual_brightness[i] != dm->brightness[i]))
 			amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
 	}
-#endif
+
 	/*
 	 * send vblank event on all events not handled in flip and
 	 * mark consumed event for drm_atomic_helper_commit_hw_done
-- 
GitLab


From efb4fd107cfd9748f777a4e9015d803d3c9db68b Mon Sep 17 00:00:00 2001
From: Yifan Zhang <yifan1.zhang@amd.com>
Date: Mon, 20 Jun 2022 16:24:58 +0800
Subject: [PATCH 0986/1731] drm/amdkfd: correct sdma queue number of sdma 6.0.1

sdma 6.0.1 has 8 queues instead of 2.

Fixes: 26776a7031c423 ("drm/amdkfd: add GC 11.0.1 KFD support")
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index bf42004577722..c8fee0dbfdcb9 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -75,7 +75,6 @@ static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd)
 	case IP_VERSION(5, 2, 3):/* YELLOW_CARP */
 	case IP_VERSION(5, 2, 6):/* GC 10.3.6 */
 	case IP_VERSION(5, 2, 7):/* GC 10.3.7 */
-	case IP_VERSION(6, 0, 1):
 		kfd->device_info.num_sdma_queues_per_engine = 2;
 		break;
 	case IP_VERSION(4, 2, 0):/* VEGA20 */
@@ -90,6 +89,7 @@ static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd)
 	case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */
 	case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */
 	case IP_VERSION(6, 0, 0):
+	case IP_VERSION(6, 0, 1):
 	case IP_VERSION(6, 0, 2):
 		kfd->device_info.num_sdma_queues_per_engine = 8;
 		break;
-- 
GitLab


From cb4b7a23ff85740ed9e0a3aa4c3c0195654a89d5 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Mon, 20 Jun 2022 11:43:36 +0200
Subject: [PATCH 0987/1731] drm/radeon: Drop CONFIG_BACKLIGHT_CLASS_DEVICE
 ifdefs

The DRM_RADEON Kconfig code contains:

	select BACKLIGHT_CLASS_DEVICE

So the condition these ifdefs test for is always true, drop them.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/radeon/atombios_encoders.c      | 14 --------------
 drivers/gpu/drm/radeon/radeon_acpi.c            |  2 --
 drivers/gpu/drm/radeon/radeon_legacy_encoders.c | 15 ---------------
 drivers/gpu/drm/radeon/radeon_mode.h            |  4 ----
 4 files changed, 35 deletions(-)

diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index 70bd84b7ef2b0..c93040e60d040 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -141,8 +141,6 @@ atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
 	}
 }
 
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
-
 static u8 radeon_atom_bl_level(struct backlight_device *bd)
 {
 	u8 level;
@@ -286,18 +284,6 @@ static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
 	}
 }
 
-#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
-
-void radeon_atom_backlight_init(struct radeon_encoder *encoder)
-{
-}
-
-static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
-{
-}
-
-#endif
-
 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 				   const struct drm_display_mode *mode,
 				   struct drm_display_mode *adjusted_mode)
diff --git a/drivers/gpu/drm/radeon/radeon_acpi.c b/drivers/gpu/drm/radeon/radeon_acpi.c
index 1baef7b493def..b603c0b770750 100644
--- a/drivers/gpu/drm/radeon/radeon_acpi.c
+++ b/drivers/gpu/drm/radeon/radeon_acpi.c
@@ -391,7 +391,6 @@ static int radeon_atif_handler(struct radeon_device *rdev,
 
 			radeon_set_backlight_level(rdev, enc, req.backlight_level);
 
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 			if (rdev->is_atom_bios) {
 				struct radeon_encoder_atom_dig *dig = enc->enc_priv;
 				backlight_force_update(dig->bl_dev,
@@ -401,7 +400,6 @@ static int radeon_atif_handler(struct radeon_device *rdev,
 				backlight_force_update(dig->bl_dev,
 						       BACKLIGHT_UPDATE_HOTKEY);
 			}
-#endif
 		}
 	}
 	if (req.pending & ATIF_DGPU_DISPLAY_EVENT) {
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index 7fdb77d48d6a3..1a66fb969ee75 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -318,8 +318,6 @@ radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 leve
 	radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode);
 }
 
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
-
 static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
 {
 	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
@@ -488,19 +486,6 @@ static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder)
 	}
 }
 
-#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
-
-void radeon_legacy_backlight_init(struct radeon_encoder *encoder)
-{
-}
-
-static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder)
-{
-}
-
-#endif
-
-
 static void radeon_lvds_enc_destroy(struct drm_encoder *encoder)
 {
 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 3485e7f142e94..b34cffc162e2c 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -281,15 +281,11 @@ struct radeon_mode_info {
 
 #define RADEON_MAX_BL_LEVEL 0xFF
 
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
-
 struct radeon_backlight_privdata {
 	struct radeon_encoder *encoder;
 	uint8_t negative;
 };
 
-#endif
-
 #define MAX_H_CODE_TIMING_LEN 32
 #define MAX_V_CODE_TIMING_LEN 32
 
-- 
GitLab


From 163d4cd26a18db7db68a98b4d1ca95d542ca72af Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Thu, 16 Jun 2022 16:52:01 -0400
Subject: [PATCH 0988/1731] drm/amdgpu: fix adev variable used in
 amdgpu_device_gpu_recover()

Use the correct adev variable for the drm_fb_helper in
amdgpu_device_gpu_recover().  Noticed by inspection.

Fixes: 087451f372bf ("drm/amdgpu: use generic fb helpers instead of setting up AMD own's.")
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index ea9a9d781d8c4..f2a4c268ac72b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5187,7 +5187,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
 		 */
 		amdgpu_unregister_gpu_instance(tmp_adev);
 
-		drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
+		drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true);
 
 		/* disable ras on ALL IPs */
 		if (!need_emergency_restart &&
-- 
GitLab


From fd6ae969cfa2b12c6082eb83bdfa648b15d9b3c7 Mon Sep 17 00:00:00 2001
From: Jiang Jian <jiangjian@cdjrlc.com>
Date: Tue, 21 Jun 2022 21:10:41 +0800
Subject: [PATCH 0989/1731] drm/amdgpu: vm - drop unexpected word "the" in the
 comments

there is an unexpected word "the" in the comments that need to be dropped

file: drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
line: 57
  * the kernel tells the the ring what VMID to use for that command
changed to
  * the kernel tells the ring what VMID to use for that command

Signed-off-by: Jiang Jian <jiangjian@cdjrlc.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index dc76d2b3ce52f..8530befb20513 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -54,7 +54,7 @@
  * (uncached system pages).
  * Each VM has an ID associated with it and there is a page table
  * associated with each VMID.  When executing a command buffer,
- * the kernel tells the the ring what VMID to use for that command
+ * the kernel tells the ring what VMID to use for that command
  * buffer.  VMIDs are allocated dynamically as commands are submitted.
  * The userspace drivers maintain their own address space and the kernel
  * sets up their pages tables accordingly when they submit their
-- 
GitLab


From c85c623ab406188da7969180e53c4b61e8a982e0 Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Tue, 21 Jun 2022 11:23:39 -0400
Subject: [PATCH 0990/1731] drm/amd/display: fix array index in DML
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

[Why&How]
When the a 3d array is used by indexing with only one dimension in an if
condition, the addresses get compared instead of the intended value stored in the
array. GCC 12.1 caught this error:

drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/dcn32/display_mode_vba_32.c: In function ‘DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation’:
drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/dcn32/display_mode_vba_32.c:1007:45: error: the comparison will always evaluate as ‘true’ for the address of ‘use_one_row_for_frame_flip’ will never be NULL [-Werror=address]
1007 | if (v->use_one_row_for_frame_flip[k]) {
| ^
In file included from ./drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/display_mode_lib.h:32,
from ./drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dc.h:45,
from drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/dcn32/display_mode_vba_32.c:30:
./drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/display_mode_vba.h:605:14: note: ‘use_one_row_for_frame_flip’ declared here
605 | bool use_one_row_for_frame_flip[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
|

Fix this by explicitly specifying the last two indices.

Fixes: dda4fb85e433 ("drm/amd/display: DML changes for DCN32/321")
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index b9f5bfa67791b..c920d71fbd560 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -994,7 +994,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 							+ mode_lib->vba.DPPPerPlane[k]
 									* (v->PDEAndMetaPTEBytesFrame[k]
 											+ v->MetaRowByte[k]);
-					if (v->use_one_row_for_frame_flip[k]) {
+					if (v->use_one_row_for_frame_flip[k][0][0]) {
 						mode_lib->vba.TotImmediateFlipBytes =
 								mode_lib->vba.TotImmediateFlipBytes
 										+ 2 * v->PixelPTEBytesPerRow[k];
-- 
GitLab


From eec53143b7fe1ccaace434e03b5959c9117bf9c5 Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Tue, 21 Jun 2022 11:23:40 -0400
Subject: [PATCH 0991/1731] drm/amd/display: fix incorrect comparison in DML
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

[Why&How]
GCC 12 catches the following incorrect comparison in the if arm

drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/dcn32/display_mode_vba_32.c: In function ‘dml32_ModeSupportAndSystemConfigurationFull’:
drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/dcn32/display_mode_vba_32.c:3740:33: error: the comparison will always evaluate as ‘true’ for the address of ‘USRRetrainingSupport’ will never be NULL [-Werror=address]
3740 | || &mode_lib->vba.USRRetrainingSupport[i][j])) {
| ^~
In file included from ./drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/display_mode_lib.h:32,
from ./drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dc.h:45,
from drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/dcn32/display_mode_vba_32.c:30:
./drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/display_mode_vba.h:1175:14: note: ‘USRRetrainingSupport’ declared here
1175 | bool USRRetrainingSupport[DC__VOLTAGE_STATES][2];
|

Fix this by remove preceding & so that value is compared instead of
address

Fixes: dda4fb85e433 ("drm/amd/display: DML changes for DCN32/321")
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index c920d71fbd560..510b7a81ee124 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -3725,7 +3725,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 				&& (!mode_lib->vba.FCLKChangeRequirementFinal || i == v->soc.num_states - 1
 				|| mode_lib->vba.FCLKChangeSupport[i][j] != dm_fclock_change_unsupported)
 				&& (!mode_lib->vba.USRRetrainingRequiredFinal
-				|| &mode_lib->vba.USRRetrainingSupport[i][j])) {
+				|| mode_lib->vba.USRRetrainingSupport[i][j])) {
 				mode_lib->vba.ModeSupport[i][j] = true;
 			} else {
 				mode_lib->vba.ModeSupport[i][j] = false;
-- 
GitLab


From a632b2a4c920ce5af29410fb091f7ee6d2e77dc6 Mon Sep 17 00:00:00 2001
From: Anatolii Gerasymenko <anatolii.gerasymenko@intel.com>
Date: Mon, 6 Jun 2022 09:01:21 +0200
Subject: [PATCH 0992/1731] ice: ethtool: Prohibit improper channel config for
 DCB

Do not allow setting less channels, than Traffic Classes there are
via ethtool. There must be at least one channel per Traffic Class.

If you set less channels, than Traffic Classes there are, then during
ice_vsi_rebuild there would be allocated only the requested amount
of tx/rx rings in ice_vsi_alloc_arrays. But later in ice_vsi_setup_q_map
there would be requested at least one channel per Traffic Class. This
results in setting num_rxq > alloc_rxq and num_txq > alloc_txq.
Later, there would be a NULL pointer dereference in
ice_vsi_map_rings_to_vectors, because we go beyond of rx_rings or
tx_rings arrays.

Change ice_set_channels() to return error if you try to allocate less
channels, than Traffic Classes there are.
Change ice_vsi_setup_q_map() and ice_vsi_setup_q_map_mqprio() to return
status code instead of void.
Add error handling for ice_vsi_setup_q_map() and
ice_vsi_setup_q_map_mqprio() in ice_vsi_init() and ice_vsi_cfg_tc().

[53753.889983] INFO: Flow control is disabled for this traffic class (0) on this vsi.
[53763.984862] BUG: unable to handle kernel NULL pointer dereference at 0000000000000028
[53763.992915] PGD 14b45f5067 P4D 0
[53763.996444] Oops: 0002 [#1] SMP NOPTI
[53764.000312] CPU: 12 PID: 30661 Comm: ethtool Kdump: loaded Tainted: GOE    --------- -  - 4.18.0-240.el8.x86_64 #1
[53764.011825] Hardware name: Intel Corporation WilsonCity/WilsonCity, BIOS WLYDCRB1.SYS.0020.P21.2012150710 12/15/2020
[53764.022584] RIP: 0010:ice_vsi_map_rings_to_vectors+0x7e/0x120 [ice]
[53764.029089] Code: 41 0d 0f b7 b7 12 05 00 00 0f b6 d0 44 29 de 44 0f b7 c6 44 01 c2 41 39 d0 7d 2d 4c 8b 47 28 44 0f b7 ce 83 c6 01 4f 8b 04 c8 <49> 89 48 28 4                           c 8b 89 b8 01 00 00 4d 89 08 4c 89 81 b8 01 00 00 44
[53764.048379] RSP: 0018:ff550dd88ea47b20 EFLAGS: 00010206
[53764.053884] RAX: 0000000000000002 RBX: 0000000000000004 RCX: ff385ea42fa4a018
[53764.061301] RDX: 0000000000000006 RSI: 0000000000000005 RDI: ff385e9baeedd018
[53764.068717] RBP: 0000000000000010 R08: 0000000000000000 R09: 0000000000000004
[53764.076133] R10: 0000000000000002 R11: 0000000000000004 R12: 0000000000000000
[53764.083553] R13: 0000000000000000 R14: ff385e658fdd9000 R15: ff385e9baeedd018
[53764.090976] FS:  000014872c5b5740(0000) GS:ff385e847f100000(0000) knlGS:0000000000000000
[53764.099362] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[53764.105409] CR2: 0000000000000028 CR3: 0000000a820fa002 CR4: 0000000000761ee0
[53764.112851] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[53764.120301] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
[53764.127747] PKRU: 55555554
[53764.130781] Call Trace:
[53764.133564]  ice_vsi_rebuild+0x611/0x870 [ice]
[53764.138341]  ice_vsi_recfg_qs+0x94/0x100 [ice]
[53764.143116]  ice_set_channels+0x1a8/0x3e0 [ice]
[53764.147975]  ethtool_set_channels+0x14e/0x240
[53764.152667]  dev_ethtool+0xd74/0x2a10
[53764.156665]  ? __mod_lruvec_state+0x44/0x110
[53764.161280]  ? __mod_lruvec_state+0x44/0x110
[53764.165893]  ? page_add_file_rmap+0x15/0x170
[53764.170518]  ? inet_ioctl+0xd1/0x220
[53764.174445]  ? netdev_run_todo+0x5e/0x290
[53764.178808]  dev_ioctl+0xb5/0x550
[53764.182485]  sock_do_ioctl+0xa0/0x140
[53764.186512]  sock_ioctl+0x1a8/0x300
[53764.190367]  ? selinux_file_ioctl+0x161/0x200
[53764.195090]  do_vfs_ioctl+0xa4/0x640
[53764.199035]  ksys_ioctl+0x60/0x90
[53764.202722]  __x64_sys_ioctl+0x16/0x20
[53764.206845]  do_syscall_64+0x5b/0x1a0
[53764.210887]  entry_SYSCALL_64_after_hwframe+0x65/0xca

Fixes: 87324e747fde ("ice: Implement ethtool ops for channels")
Signed-off-by: Anatolii Gerasymenko <anatolii.gerasymenko@intel.com>
Tested-by: Gurucharan <gurucharanx.g@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
---
 drivers/net/ethernet/intel/ice/ice_ethtool.c | 10 +++++
 drivers/net/ethernet/intel/ice/ice_lib.c     | 42 +++++++++++++++++---
 2 files changed, 47 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/intel/ice/ice_ethtool.c b/drivers/net/ethernet/intel/ice/ice_ethtool.c
index 8078618ce1b61..70335f6e85243 100644
--- a/drivers/net/ethernet/intel/ice/ice_ethtool.c
+++ b/drivers/net/ethernet/intel/ice/ice_ethtool.c
@@ -3507,6 +3507,16 @@ static int ice_set_channels(struct net_device *dev, struct ethtool_channels *ch)
 	new_rx = ch->combined_count + ch->rx_count;
 	new_tx = ch->combined_count + ch->tx_count;
 
+	if (new_rx < vsi->tc_cfg.numtc) {
+		netdev_err(dev, "Cannot set less Rx channels, than Traffic Classes you have (%u)\n",
+			   vsi->tc_cfg.numtc);
+		return -EINVAL;
+	}
+	if (new_tx < vsi->tc_cfg.numtc) {
+		netdev_err(dev, "Cannot set less Tx channels, than Traffic Classes you have (%u)\n",
+			   vsi->tc_cfg.numtc);
+		return -EINVAL;
+	}
 	if (new_rx > ice_get_max_rxq(pf)) {
 		netdev_err(dev, "Maximum allowed Rx channels is %d\n",
 			   ice_get_max_rxq(pf));
diff --git a/drivers/net/ethernet/intel/ice/ice_lib.c b/drivers/net/ethernet/intel/ice/ice_lib.c
index 454e01ae09b97..f7f9c973ec54d 100644
--- a/drivers/net/ethernet/intel/ice/ice_lib.c
+++ b/drivers/net/ethernet/intel/ice/ice_lib.c
@@ -909,7 +909,7 @@ static void ice_set_dflt_vsi_ctx(struct ice_hw *hw, struct ice_vsi_ctx *ctxt)
  * @vsi: the VSI being configured
  * @ctxt: VSI context structure
  */
-static void ice_vsi_setup_q_map(struct ice_vsi *vsi, struct ice_vsi_ctx *ctxt)
+static int ice_vsi_setup_q_map(struct ice_vsi *vsi, struct ice_vsi_ctx *ctxt)
 {
 	u16 offset = 0, qmap = 0, tx_count = 0, pow = 0;
 	u16 num_txq_per_tc, num_rxq_per_tc;
@@ -982,7 +982,18 @@ static void ice_vsi_setup_q_map(struct ice_vsi *vsi, struct ice_vsi_ctx *ctxt)
 	else
 		vsi->num_rxq = num_rxq_per_tc;
 
+	if (vsi->num_rxq > vsi->alloc_rxq) {
+		dev_err(ice_pf_to_dev(vsi->back), "Trying to use more Rx queues (%u), than were allocated (%u)!\n",
+			vsi->num_rxq, vsi->alloc_rxq);
+		return -EINVAL;
+	}
+
 	vsi->num_txq = tx_count;
+	if (vsi->num_txq > vsi->alloc_txq) {
+		dev_err(ice_pf_to_dev(vsi->back), "Trying to use more Tx queues (%u), than were allocated (%u)!\n",
+			vsi->num_txq, vsi->alloc_txq);
+		return -EINVAL;
+	}
 
 	if (vsi->type == ICE_VSI_VF && vsi->num_txq != vsi->num_rxq) {
 		dev_dbg(ice_pf_to_dev(vsi->back), "VF VSI should have same number of Tx and Rx queues. Hence making them equal\n");
@@ -1000,6 +1011,8 @@ static void ice_vsi_setup_q_map(struct ice_vsi *vsi, struct ice_vsi_ctx *ctxt)
 	 */
 	ctxt->info.q_mapping[0] = cpu_to_le16(vsi->rxq_map[0]);
 	ctxt->info.q_mapping[1] = cpu_to_le16(vsi->num_rxq);
+
+	return 0;
 }
 
 /**
@@ -1187,7 +1200,10 @@ static int ice_vsi_init(struct ice_vsi *vsi, bool init_vsi)
 	if (vsi->type == ICE_VSI_CHNL) {
 		ice_chnl_vsi_setup_q_map(vsi, ctxt);
 	} else {
-		ice_vsi_setup_q_map(vsi, ctxt);
+		ret = ice_vsi_setup_q_map(vsi, ctxt);
+		if (ret)
+			goto out;
+
 		if (!init_vsi) /* means VSI being updated */
 			/* must to indicate which section of VSI context are
 			 * being modified
@@ -3464,7 +3480,7 @@ void ice_vsi_cfg_netdev_tc(struct ice_vsi *vsi, u8 ena_tc)
  *
  * Prepares VSI tc_config to have queue configurations based on MQPRIO options.
  */
-static void
+static int
 ice_vsi_setup_q_map_mqprio(struct ice_vsi *vsi, struct ice_vsi_ctx *ctxt,
 			   u8 ena_tc)
 {
@@ -3513,7 +3529,18 @@ ice_vsi_setup_q_map_mqprio(struct ice_vsi *vsi, struct ice_vsi_ctx *ctxt,
 
 	/* Set actual Tx/Rx queue pairs */
 	vsi->num_txq = offset + qcount_tx;
+	if (vsi->num_txq > vsi->alloc_txq) {
+		dev_err(ice_pf_to_dev(vsi->back), "Trying to use more Tx queues (%u), than were allocated (%u)!\n",
+			vsi->num_txq, vsi->alloc_txq);
+		return -EINVAL;
+	}
+
 	vsi->num_rxq = offset + qcount_rx;
+	if (vsi->num_rxq > vsi->alloc_rxq) {
+		dev_err(ice_pf_to_dev(vsi->back), "Trying to use more Rx queues (%u), than were allocated (%u)!\n",
+			vsi->num_rxq, vsi->alloc_rxq);
+		return -EINVAL;
+	}
 
 	/* Setup queue TC[0].qmap for given VSI context */
 	ctxt->info.tc_mapping[0] = cpu_to_le16(qmap);
@@ -3531,6 +3558,8 @@ ice_vsi_setup_q_map_mqprio(struct ice_vsi *vsi, struct ice_vsi_ctx *ctxt,
 	dev_dbg(ice_pf_to_dev(vsi->back), "vsi->num_rxq = %d\n",  vsi->num_rxq);
 	dev_dbg(ice_pf_to_dev(vsi->back), "all_numtc %u, all_enatc: 0x%04x, tc_cfg.numtc %u\n",
 		vsi->all_numtc, vsi->all_enatc, vsi->tc_cfg.numtc);
+
+	return 0;
 }
 
 /**
@@ -3580,9 +3609,12 @@ int ice_vsi_cfg_tc(struct ice_vsi *vsi, u8 ena_tc)
 
 	if (vsi->type == ICE_VSI_PF &&
 	    test_bit(ICE_FLAG_TC_MQPRIO, pf->flags))
-		ice_vsi_setup_q_map_mqprio(vsi, ctx, ena_tc);
+		ret = ice_vsi_setup_q_map_mqprio(vsi, ctx, ena_tc);
 	else
-		ice_vsi_setup_q_map(vsi, ctx);
+		ret = ice_vsi_setup_q_map(vsi, ctx);
+
+	if (ret)
+		goto out;
 
 	/* must to indicate which section of VSI context are being modified */
 	ctx->info.valid_sections = cpu_to_le16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
-- 
GitLab


From c487a5ad48831afa6784b368ec40d0ee50f2fe1b Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Wed, 22 Jun 2022 00:00:35 +0100
Subject: [PATCH 0993/1731] io_uring: fail links when poll fails

Don't forget to cancel all linked requests of poll request when
__io_arm_poll_handler() failed.

Fixes: aa43477b04025 ("io_uring: poll rework")
Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
Link: https://lore.kernel.org/r/a78aad962460f9fdfe4aa4c0b62425c88f9415bc.1655852245.git.asml.silence@gmail.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index dffa85d4dc7a0..d5ea3c6167b55 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -7405,6 +7405,8 @@ static int io_poll_add(struct io_kiocb *req, unsigned int issue_flags)
 	ipt.pt._qproc = io_poll_queue_proc;
 
 	ret = __io_arm_poll_handler(req, &req->poll, &ipt, poll->events);
+	if (!ret && ipt.error)
+		req_set_fail(req);
 	ret = ret ?: ipt.error;
 	if (ret)
 		__io_req_complete(req, issue_flags, ret, 0);
-- 
GitLab


From 9d2ad2947a53abf5e5e6527a9eeed50a3a4cbc72 Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Wed, 22 Jun 2022 00:00:36 +0100
Subject: [PATCH 0994/1731] io_uring: fix wrong arm_poll error handling

Leaving ip.error set when a request was punted to task_work execution is
problematic, don't forget to clear it.

Fixes: aa43477b04025 ("io_uring: poll rework")
Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
Link: https://lore.kernel.org/r/a6c84ef4182c6962380aebe11b35bdcb25b0ccfb.1655852245.git.asml.silence@gmail.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index d5ea3c6167b55..cb719a53b8bd1 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -7145,6 +7145,7 @@ static int __io_arm_poll_handler(struct io_kiocb *req,
 		if (unlikely(ipt->error || !ipt->nr_entries)) {
 			poll->events |= EPOLLONESHOT;
 			req->apoll_events |= EPOLLONESHOT;
+			ipt->error = 0;
 		}
 		__io_poll_execute(req, mask, poll->events);
 		return 0;
-- 
GitLab


From c0737fa9a5a5cf5a053bcc983f72d58919b997c6 Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Wed, 22 Jun 2022 00:00:37 +0100
Subject: [PATCH 0995/1731] io_uring: fix double poll leak on repolling

We have re-polling for partial IO, so a request can be polled twice. If
it used two poll entries the first time then on the second
io_arm_poll_handler() it will find the old apoll entry and NULL
kmalloc()'ed second entry, i.e. apoll->double_poll, so leaking it.

Fixes: 10c873334feba ("io_uring: allow re-poll if we made progress")
Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
Link: https://lore.kernel.org/r/fee2452494222ecc7f1f88c8fb659baef971414a.1655852245.git.asml.silence@gmail.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index cb719a53b8bd1..5c95755619e2d 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -7208,6 +7208,7 @@ static int io_arm_poll_handler(struct io_kiocb *req, unsigned issue_flags)
 		mask |= EPOLLEXCLUSIVE;
 	if (req->flags & REQ_F_POLLED) {
 		apoll = req->apoll;
+		kfree(apoll->double_poll);
 	} else if (!(issue_flags & IO_URING_F_UNLOCKED) &&
 		   !list_empty(&ctx->apoll_cache)) {
 		apoll = list_first_entry(&ctx->apoll_cache, struct async_poll,
-- 
GitLab


From 2642cc6c3bbe0900ba15bab078fd15ad8baccbc5 Mon Sep 17 00:00:00 2001
From: Lukas Wunner <lukas@wunner.de>
Date: Mon, 20 Jun 2022 13:04:50 +0200
Subject: [PATCH 0996/1731] net: phy: smsc: Disable Energy Detect Power-Down in
 interrupt mode

Simon reports that if two LAN9514 USB adapters are directly connected
without an intermediate switch, the link fails to come up and link LEDs
remain dark.  The issue was introduced by commit 1ce8b37241ed ("usbnet:
smsc95xx: Forward PHY interrupts to PHY driver to avoid polling").

The PHY suffers from a known erratum wherein link detection becomes
unreliable if Energy Detect Power-Down is used.  In poll mode, the
driver works around the erratum by briefly disabling EDPD for 640 msec
to detect a neighbor, then re-enabling it to save power.

In interrupt mode, no interrupt is signaled if EDPD is used by both link
partners, so it must not be enabled at all.

We'll recoup the power savings by enabling SUSPEND1 mode on affected
LAN95xx chips in a forthcoming commit.

Fixes: 1ce8b37241ed ("usbnet: smsc95xx: Forward PHY interrupts to PHY driver to avoid polling")
Reported-by: Simon Han <z.han@kunbus.com>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Link: https://lore.kernel.org/r/439a3f3168c2f9d44b5fd9bb8d2b551711316be6.1655714438.git.lukas@wunner.de
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/phy/smsc.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
index 1b54684b68a07..96d3c40932d8c 100644
--- a/drivers/net/phy/smsc.c
+++ b/drivers/net/phy/smsc.c
@@ -110,7 +110,7 @@ static int smsc_phy_config_init(struct phy_device *phydev)
 	struct smsc_phy_priv *priv = phydev->priv;
 	int rc;
 
-	if (!priv->energy_enable)
+	if (!priv->energy_enable || phydev->irq != PHY_POLL)
 		return 0;
 
 	rc = phy_read(phydev, MII_LAN83C185_CTRL_STATUS);
@@ -210,6 +210,8 @@ static int lan95xx_config_aneg_ext(struct phy_device *phydev)
  * response on link pulses to detect presence of plugged Ethernet cable.
  * The Energy Detect Power-Down mode is enabled again in the end of procedure to
  * save approximately 220 mW of power if cable is unplugged.
+ * The workaround is only applicable to poll mode. Energy Detect Power-Down may
+ * not be used in interrupt mode lest link change detection becomes unreliable.
  */
 static int lan87xx_read_status(struct phy_device *phydev)
 {
@@ -217,7 +219,7 @@ static int lan87xx_read_status(struct phy_device *phydev)
 
 	int err = genphy_read_status(phydev);
 
-	if (!phydev->link && priv->energy_enable) {
+	if (!phydev->link && priv->energy_enable && phydev->irq == PHY_POLL) {
 		/* Disable EDPD to wake up PHY */
 		int rc = phy_read(phydev, MII_LAN83C185_CTRL_STATUS);
 		if (rc < 0)
-- 
GitLab


From 14d6a086f6b91238873d3363f840a91b3aa062de Mon Sep 17 00:00:00 2001
From: pengfuyuan <pengfuyuan@kylinos.cn>
Date: Thu, 16 Jun 2022 15:08:03 +0800
Subject: [PATCH 0997/1731] drm/i915: Fix spelling typo in comment

Fix spelling typo in comment.

Reported-by: k2ci <kernel-bot@kylinos.cn>
Signed-off-by: pengfuyuan <pengfuyuan@kylinos.cn>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/tencent_7B226C4A9BC2B5EEB37B70C188B5015D290A@qq.com
---
 drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
index 80ac0db1ae8ca..85518b28cd721 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
@@ -114,7 +114,7 @@ u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,
 	return i915_gem_fence_size(i915, size, tiling, stride);
 }
 
-/* Check pitch constriants for all chips & tiling formats */
+/* Check pitch constraints for all chips & tiling formats */
 static bool
 i915_tiling_ok(struct drm_i915_gem_object *obj,
 	       unsigned int tiling, unsigned int stride)
-- 
GitLab


From 7482a65664c16cc88eb84d2b545a1fed887378a1 Mon Sep 17 00:00:00 2001
From: katrinzhou <katrinzhou@tencent.com>
Date: Tue, 21 Jun 2022 13:49:26 +0100
Subject: [PATCH 0998/1731] drm/i915/gem: add missing else

Add missing else in set_proto_ctx_param() to fix coverity issue.

Addresses-Coverity: ("Unused value")
Fixes: d4433c7600f7 ("drm/i915/gem: Use the proto-context to handle create parameters (v5)")
Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: katrinzhou <katrinzhou@tencent.com>
[tursulin: fixup alignment]
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220621124926.615884-1-tvrtko.ursulin@linux.intel.com
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index e116f82fc37c6..dabdfe09f5e51 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -933,8 +933,9 @@ static int set_proto_ctx_param(struct drm_i915_file_private *fpriv,
 	case I915_CONTEXT_PARAM_PERSISTENCE:
 		if (args->size)
 			ret = -EINVAL;
-		ret = proto_context_set_persistence(fpriv->dev_priv, pc,
-						    args->value);
+		else
+			ret = proto_context_set_persistence(fpriv->dev_priv, pc,
+							    args->value);
 		break;
 
 	case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
-- 
GitLab


From ae60aac59a9ad8ab64a4b07de509a534a75b6bac Mon Sep 17 00:00:00 2001
From: Johan Hovold <johan@kernel.org>
Date: Tue, 21 Jun 2022 10:58:55 +0200
Subject: [PATCH 0999/1731] USB: serial: pl2303: add support for more HXN (G)
 types

Add support for further HXN (G) type devices (GT variant, GL variant, GS
variant and GR) and document the bcdDevice mapping.

Note that the TA and TB types use the same bcdDevice as some GT and GE
variants, respectively, but that the HX status request can be used to
determine which is which.

Also note that we currently do not distinguish between the various HXN
(G) types in the driver but that this may change eventually (e.g. when
adding GPIO support).

Reported-by: Charles Yeh <charlesyeh522@gmail.com>
Link: https://lore.kernel.org/r/YrF77b9DdeumUAee@hovoldconsulting.com
Cc: stable@vger.kernel.org	# 5.13
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Johan Hovold <johan@kernel.org>
---
 drivers/usb/serial/pl2303.c | 29 +++++++++++++++++------------
 1 file changed, 17 insertions(+), 12 deletions(-)

diff --git a/drivers/usb/serial/pl2303.c b/drivers/usb/serial/pl2303.c
index 3506c47e1eef0..40b1ab3d284dc 100644
--- a/drivers/usb/serial/pl2303.c
+++ b/drivers/usb/serial/pl2303.c
@@ -436,22 +436,27 @@ static int pl2303_detect_type(struct usb_serial *serial)
 		break;
 	case 0x200:
 		switch (bcdDevice) {
-		case 0x100:
+		case 0x100:	/* GC */
 		case 0x105:
+			return TYPE_HXN;
+		case 0x300:	/* GT / TA */
+			if (pl2303_supports_hx_status(serial))
+				return TYPE_TA;
+			fallthrough;
 		case 0x305:
+		case 0x400:	/* GL */
 		case 0x405:
+			return TYPE_HXN;
+		case 0x500:	/* GE / TB */
+			if (pl2303_supports_hx_status(serial))
+				return TYPE_TB;
+			fallthrough;
+		case 0x505:
+		case 0x600:	/* GS */
 		case 0x605:
-			/*
-			 * Assume it's an HXN-type if the device doesn't
-			 * support the old read request value.
-			 */
-			if (!pl2303_supports_hx_status(serial))
-				return TYPE_HXN;
-			break;
-		case 0x300:
-			return TYPE_TA;
-		case 0x500:
-			return TYPE_TB;
+		case 0x700:	/* GR */
+		case 0x705:
+			return TYPE_HXN;
 		}
 		break;
 	}
-- 
GitLab


From 33b29dbb39bcbd0a96e440646396bbf670b914fa Mon Sep 17 00:00:00 2001
From: Yonglin Tan <yonglin.tan@outlook.com>
Date: Tue, 21 Jun 2022 20:37:53 +0800
Subject: [PATCH 1000/1731] USB: serial: option: add Quectel EM05-G modem

The EM05-G modem has 2 USB configurations that are configurable via the AT
command AT+QCFG="usbnet",[ 0 | 2 ] which make the modem enumerate with
the following interfaces, respectively:

"RMNET"	: AT + DIAG + NMEA + Modem + QMI
"MBIM"	: MBIM + AT + DIAG + NMEA + Modem

The detailed description of the USB configuration for each mode as follows:

RMNET Mode
--------------
T:  Bus=01 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#= 21 Spd=480  MxCh= 0
D:  Ver= 2.00 Cls=ef(misc ) Sub=02 Prot=01 MxPS=64 #Cfgs=  1
P:  Vendor=2c7c ProdID=030a Rev= 3.18
S:  Manufacturer=Quectel
S:  Product=Quectel EM05-G
C:* #Ifs= 5 Cfg#= 1 Atr=a0 MxPwr=500mA
I:* If#= 3 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=ff Driver=option
E:  Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 4 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=83(I) Atr=03(Int.) MxPS=  10 Ivl=32ms
E:  Ad=82(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 2 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=85(I) Atr=03(Int.) MxPS=  10 Ivl=32ms
E:  Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 5 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=87(I) Atr=03(Int.) MxPS=  10 Ivl=32ms
E:  Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=04(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 6 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=(none)
E:  Ad=89(I) Atr=03(Int.) MxPS=   8 Ivl=32ms
E:  Ad=88(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=05(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms

MBIM Mode
--------------
T:  Bus=01 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#= 16 Spd=480  MxCh= 0
D:  Ver= 2.00 Cls=ef(misc ) Sub=02 Prot=01 MxPS=64 #Cfgs=  1
P:  Vendor=2c7c ProdID=030a Rev= 3.18
S:  Manufacturer=Quectel
S:  Product=Quectel EM05-G
C:* #Ifs= 6 Cfg#= 1 Atr=a0 MxPwr=500mA
A:  FirstIf#= 0 IfCount= 2 Cls=02(comm.) Sub=0e Prot=00
I:* If#= 3 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=ff Driver=option
E:  Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 4 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=83(I) Atr=03(Int.) MxPS=  10 Ivl=32ms
E:  Ad=82(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 2 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=85(I) Atr=03(Int.) MxPS=  10 Ivl=32ms
E:  Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 5 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=87(I) Atr=03(Int.) MxPS=  10 Ivl=32ms
E:  Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=04(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=0e Prot=00 Driver=cdc_mbim
E:  Ad=89(I) Atr=03(Int.) MxPS=  64 Ivl=32ms
I:  If#= 1 Alt= 0 #EPs= 0 Cls=0a(data ) Sub=00 Prot=02 Driver=cdc_mbim
I:* If#= 1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=02 Driver=cdc_mbim
E:  Ad=88(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=05(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms

Signed-off-by: Yonglin Tan <yonglin.tan@outlook.com>
Cc: stable@vger.kernel.org
Signed-off-by: Johan Hovold <johan@kernel.org>
---
 drivers/usb/serial/option.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
index 222b1e3d45a6f..61d34886c7066 100644
--- a/drivers/usb/serial/option.c
+++ b/drivers/usb/serial/option.c
@@ -252,6 +252,7 @@ static void option_instat_callback(struct urb *urb);
 #define QUECTEL_PRODUCT_EG95			0x0195
 #define QUECTEL_PRODUCT_BG96			0x0296
 #define QUECTEL_PRODUCT_EP06			0x0306
+#define QUECTEL_PRODUCT_EM05G			0x030a
 #define QUECTEL_PRODUCT_EM12			0x0512
 #define QUECTEL_PRODUCT_RM500Q			0x0800
 #define QUECTEL_PRODUCT_EC200S_CN		0x6002
@@ -1134,6 +1135,8 @@ static const struct usb_device_id option_ids[] = {
 	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EP06, 0xff, 0xff, 0xff),
 	  .driver_info = RSVD(1) | RSVD(2) | RSVD(3) | RSVD(4) | NUMEP2 },
 	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EP06, 0xff, 0, 0) },
+	{ USB_DEVICE_INTERFACE_CLASS(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM05G, 0xff),
+	  .driver_info = RSVD(6) | ZLP },
 	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM12, 0xff, 0xff, 0xff),
 	  .driver_info = RSVD(1) | RSVD(2) | RSVD(3) | RSVD(4) | NUMEP2 },
 	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM12, 0xff, 0, 0) },
-- 
GitLab


From 5f940e528da6bce52a86fbdf881b76f60240aeaf Mon Sep 17 00:00:00 2001
From: Saud Farooqui <farooqui_saud@hotmail.com>
Date: Thu, 9 Jun 2022 23:50:31 +0500
Subject: [PATCH 1001/1731] drm/vc4: hdmi: Fixed possible integer overflow

Multiplying ints and saving it in unsigned long long
could lead to integer overflow before being type casted to
unsigned long long.

Addresses-Coverity:  1505113: Unintentional integer overflow.

Signed-off-by: Saud Farooqui <farooqui_saud@hotmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/PA4P189MB1421E63C0FF3EBF234A80AB38BA79@PA4P189MB1421.EURP189.PROD.OUTLOOK.COM
---
 drivers/gpu/drm/vc4/vc4_hdmi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 823d812f49829..ce9d16666d91f 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1481,7 +1481,7 @@ vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
 				    unsigned int bpc,
 				    enum vc4_hdmi_output_format fmt)
 {
-	unsigned long long clock = mode->clock * 1000;
+	unsigned long long clock = mode->clock * 1000ULL;
 
 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 		clock = clock * 2;
-- 
GitLab


From f5aa16807aa4f99293044944590dde81364f434f Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@gmail.com>
Date: Mon, 20 Jun 2022 20:13:33 +0200
Subject: [PATCH 1002/1731] drm/sun4i: Add DMA mask and segment size

Kernel occasionally complains that there is mismatch in segment size
when trying to render HW decoded videos and rendering them directly with
sun4i DRM driver. Following message can be observed on H6 SoC:

[  184.298308] ------------[ cut here ]------------
[  184.298326] DMA-API: sun4i-drm display-engine: mapping sg segment longer than device claims to support [len=6144000] [max=65536]
[  184.298364] WARNING: CPU: 1 PID: 382 at kernel/dma/debug.c:1162 debug_dma_map_sg+0x2b0/0x350
[  184.322997] CPU: 1 PID: 382 Comm: ffmpeg Not tainted 5.19.0-rc1+ #1331
[  184.329533] Hardware name: Tanix TX6 (DT)
[  184.333544] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[  184.340512] pc : debug_dma_map_sg+0x2b0/0x350
[  184.344882] lr : debug_dma_map_sg+0x2b0/0x350
[  184.349250] sp : ffff800009f33a50
[  184.352567] x29: ffff800009f33a50 x28: 0000000000010000 x27: ffff000001b86c00
[  184.359725] x26: ffffffffffffffff x25: ffff000005d8cc80 x24: 0000000000000000
[  184.366879] x23: ffff80000939ab18 x22: 0000000000000001 x21: 0000000000000001
[  184.374031] x20: 0000000000000000 x19: ffff0000018a7410 x18: ffffffffffffffff
[  184.381186] x17: 0000000000000000 x16: 0000000000000000 x15: ffffffffffffffff
[  184.388338] x14: 0000000000000001 x13: ffff800009534e86 x12: 6f70707573206f74
[  184.395493] x11: 20736d69616c6320 x10: 000000000000000a x9 : 0000000000010000
[  184.402647] x8 : ffff8000093b6d40 x7 : ffff800009f33850 x6 : 000000000000000c
[  184.409800] x5 : ffff0000bf997940 x4 : 0000000000000000 x3 : 0000000000000027
[  184.416953] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff000003960e80
[  184.424106] Call trace:
[  184.426556]  debug_dma_map_sg+0x2b0/0x350
[  184.430580]  __dma_map_sg_attrs+0xa0/0x110
[  184.434687]  dma_map_sgtable+0x28/0x4c
[  184.438447]  vb2_dc_dmabuf_ops_map+0x60/0xcc
[  184.442729]  __map_dma_buf+0x2c/0xd4
[  184.446321]  dma_buf_map_attachment+0xa0/0x130
[  184.450777]  drm_gem_prime_import_dev+0x7c/0x18c
[  184.455410]  drm_gem_prime_fd_to_handle+0x1b8/0x214
[  184.460300]  drm_prime_fd_to_handle_ioctl+0x2c/0x40
[  184.465190]  drm_ioctl_kernel+0xc4/0x174
[  184.469123]  drm_ioctl+0x204/0x420
[  184.472534]  __arm64_sys_ioctl+0xac/0xf0
[  184.476474]  invoke_syscall+0x48/0x114
[  184.480240]  el0_svc_common.constprop.0+0x44/0xec
[  184.484956]  do_el0_svc+0x2c/0xc0
[  184.488283]  el0_svc+0x2c/0x84
[  184.491354]  el0t_64_sync_handler+0x11c/0x150
[  184.495723]  el0t_64_sync+0x18c/0x190
[  184.499397] ---[ end trace 0000000000000000 ]---

Fix that by setting DMA mask and segment size.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20220620181333.650301-1-jernej.skrabec@gmail.com
---
 drivers/gpu/drm/sun4i/sun4i_drv.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 8841dba989ee4..6eb1aabdb1618 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -7,6 +7,7 @@
  */
 
 #include <linux/component.h>
+#include <linux/dma-mapping.h>
 #include <linux/kfifo.h>
 #include <linux/module.h>
 #include <linux/of_graph.h>
@@ -369,6 +370,13 @@ static int sun4i_drv_probe(struct platform_device *pdev)
 
 	INIT_KFIFO(list.fifo);
 
+	/*
+	 * DE2 and DE3 cores actually supports 40-bit addresses, but
+	 * driver does not.
+	 */
+	dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
+	dma_set_max_seg_size(&pdev->dev, UINT_MAX);
+
 	for (i = 0;; i++) {
 		struct device_node *pipeline = of_parse_phandle(np,
 								"allwinner,pipelines",
-- 
GitLab


From f3eac426657d985b97c92fa5f7ae1d43f04721f3 Mon Sep 17 00:00:00 2001
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
Date: Tue, 21 Jun 2022 16:08:49 +0200
Subject: [PATCH 1003/1731] powerpc/powernv: wire up rng during setup_arch

The platform's RNG must be available before random_init() in order to be
useful for initial seeding, which in turn means that it needs to be
called from setup_arch(), rather than from an init call.

Complicating things, however, is that POWER8 systems need some per-cpu
state and kmalloc, which isn't available at this stage. So we split
things up into an early phase and a later opportunistic phase. This
commit also removes some noisy log messages that don't add much.

Fixes: a4da0d50b2a0 ("powerpc: Implement arch_get_random_long/int() for powernv")
Cc: stable@vger.kernel.org # v3.13+
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
[mpe: Add of_node_put(), use pnv naming, minor change log editing]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220621140849.127227-1-Jason@zx2c4.com
---
 arch/powerpc/platforms/powernv/powernv.h |  2 +
 arch/powerpc/platforms/powernv/rng.c     | 52 ++++++++++++++++--------
 arch/powerpc/platforms/powernv/setup.c   |  2 +
 3 files changed, 40 insertions(+), 16 deletions(-)

diff --git a/arch/powerpc/platforms/powernv/powernv.h b/arch/powerpc/platforms/powernv/powernv.h
index e297bf4abfcb8..866efdc103fdd 100644
--- a/arch/powerpc/platforms/powernv/powernv.h
+++ b/arch/powerpc/platforms/powernv/powernv.h
@@ -42,4 +42,6 @@ ssize_t memcons_copy(struct memcons *mc, char *to, loff_t pos, size_t count);
 u32 __init memcons_get_size(struct memcons *mc);
 struct memcons *__init memcons_init(struct device_node *node, const char *mc_prop_name);
 
+void pnv_rng_init(void);
+
 #endif /* _POWERNV_H */
diff --git a/arch/powerpc/platforms/powernv/rng.c b/arch/powerpc/platforms/powernv/rng.c
index e3d44b36ae98f..463c78c52cc5d 100644
--- a/arch/powerpc/platforms/powernv/rng.c
+++ b/arch/powerpc/platforms/powernv/rng.c
@@ -17,6 +17,7 @@
 #include <asm/prom.h>
 #include <asm/machdep.h>
 #include <asm/smp.h>
+#include "powernv.h"
 
 #define DARN_ERR 0xFFFFFFFFFFFFFFFFul
 
@@ -28,7 +29,6 @@ struct powernv_rng {
 
 static DEFINE_PER_CPU(struct powernv_rng *, powernv_rng);
 
-
 int powernv_hwrng_present(void)
 {
 	struct powernv_rng *rng;
@@ -98,9 +98,6 @@ static int __init initialise_darn(void)
 			return 0;
 		}
 	}
-
-	pr_warn("Unable to use DARN for get_random_seed()\n");
-
 	return -EIO;
 }
 
@@ -163,32 +160,55 @@ static __init int rng_create(struct device_node *dn)
 
 	rng_init_per_cpu(rng, dn);
 
-	pr_info_once("Registering arch random hook.\n");
-
 	ppc_md.get_random_seed = powernv_get_random_long;
 
 	return 0;
 }
 
-static __init int rng_init(void)
+static int __init pnv_get_random_long_early(unsigned long *v)
 {
 	struct device_node *dn;
-	int rc;
+
+	if (!slab_is_available())
+		return 0;
+
+	if (cmpxchg(&ppc_md.get_random_seed, pnv_get_random_long_early,
+		    NULL) != pnv_get_random_long_early)
+		return 0;
 
 	for_each_compatible_node(dn, NULL, "ibm,power-rng") {
-		rc = rng_create(dn);
-		if (rc) {
-			pr_err("Failed creating rng for %pOF (%d).\n",
-				dn, rc);
+		if (rng_create(dn))
 			continue;
-		}
-
 		/* Create devices for hwrng driver */
 		of_platform_device_create(dn, NULL, NULL);
 	}
 
-	initialise_darn();
+	if (!ppc_md.get_random_seed)
+		return 0;
+	return ppc_md.get_random_seed(v);
+}
+
+void __init pnv_rng_init(void)
+{
+	struct device_node *dn;
 
+	/* Prefer darn over the rest. */
+	if (!initialise_darn())
+		return;
+
+	dn = of_find_compatible_node(NULL, NULL, "ibm,power-rng");
+	if (dn)
+		ppc_md.get_random_seed = pnv_get_random_long_early;
+
+	of_node_put(dn);
+}
+
+static int __init pnv_rng_late_init(void)
+{
+	unsigned long v;
+	/* In case it wasn't called during init for some other reason. */
+	if (ppc_md.get_random_seed == pnv_get_random_long_early)
+		pnv_get_random_long_early(&v);
 	return 0;
 }
-machine_subsys_initcall(powernv, rng_init);
+machine_subsys_initcall(powernv, pnv_rng_late_init);
diff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c
index 824c3ad7a0faf..dac545aa03082 100644
--- a/arch/powerpc/platforms/powernv/setup.c
+++ b/arch/powerpc/platforms/powernv/setup.c
@@ -203,6 +203,8 @@ static void __init pnv_setup_arch(void)
 	pnv_check_guarded_cores();
 
 	/* XXX PMCS */
+
+	pnv_rng_init();
 }
 
 static void __init pnv_init(void)
-- 
GitLab


From afd5cb3907eaf43e4ca88c162b92143551f0323e Mon Sep 17 00:00:00 2001
From: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Date: Fri, 10 Jun 2022 15:12:05 +0300
Subject: [PATCH 1004/1731] drm/i915: don't leak lmem mapping in vma_evict

Don't leak lmem mapping in vma_evict, move __i915_vma_iounmap outside
i915_vma_is_map_and_fenceable.

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220610121205.29645-3-juhapekka.heikkila@gmail.com
---
 drivers/gpu/drm/i915/i915_vma.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 0bffb70b3c5f5..d333c44169971 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1907,9 +1907,11 @@ struct dma_fence *__i915_vma_evict(struct i915_vma *vma, bool async)
 		/* release the fence reg _after_ flushing */
 		i915_vma_revoke_fence(vma);
 
-		__i915_vma_iounmap(vma);
 		clear_bit(I915_VMA_CAN_FENCE_BIT, __i915_vma_flags(vma));
 	}
+
+	__i915_vma_iounmap(vma);
+
 	GEM_BUG_ON(vma->fence);
 	GEM_BUG_ON(i915_vma_has_userfault(vma));
 
-- 
GitLab


From d976521a995a817007ae3f471ac22b93b1bd39f7 Mon Sep 17 00:00:00 2001
From: CQ Tang <cq.tang@intel.com>
Date: Fri, 10 Jun 2022 15:12:04 +0300
Subject: [PATCH 1005/1731] drm/i915: extend i915_vma_pin_iomap()

In the future display might try call this with a normal smem object,
which doesn't require PIN_MAPPABLE underneath in order to CPU map the
pages (unlike stolen).  Extend i915_vma_pin_iomap() to directly use
i915_gem_object_pin_map() for such cases.

This change was suggested by Chris P Wilson, that we pin
the smem with i915_gem_object_pin_map_unlocked().

v2 (jheikkil): Change i915_gem_object_pin_map_unlocked to
               i915_gem_object_pin_map

Signed-off-by: CQ Tang <cq.tang@intel.com>
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Cc: Chris Wilson <chris.p.wilson@intel.com>
Cc: Jari Tahvanainen <jari.tahvanainen@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
[mauld: tweak commit message, plus minor checkpatch fix]
Link: https://patchwork.freedesktop.org/patch/msgid/20220610121205.29645-2-juhapekka.heikkila@gmail.com
---
 drivers/gpu/drm/i915/i915_vma.c | 35 ++++++++++++++++++++++-----------
 1 file changed, 23 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index d333c44169971..5d5828b9a2426 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -551,13 +551,6 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
 	if (WARN_ON_ONCE(vma->obj->flags & I915_BO_ALLOC_GPU_ONLY))
 		return IOMEM_ERR_PTR(-EINVAL);
 
-	if (!i915_gem_object_is_lmem(vma->obj)) {
-		if (GEM_WARN_ON(!i915_vma_is_map_and_fenceable(vma))) {
-			err = -ENODEV;
-			goto err;
-		}
-	}
-
 	GEM_BUG_ON(!i915_vma_is_ggtt(vma));
 	GEM_BUG_ON(!i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND));
 	GEM_BUG_ON(i915_vma_verify_bind_complete(vma));
@@ -570,20 +563,33 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
 		 * of pages, that way we can also drop the
 		 * I915_BO_ALLOC_CONTIGUOUS when allocating the object.
 		 */
-		if (i915_gem_object_is_lmem(vma->obj))
+		if (i915_gem_object_is_lmem(vma->obj)) {
 			ptr = i915_gem_object_lmem_io_map(vma->obj, 0,
 							  vma->obj->base.size);
-		else
+		} else if (i915_vma_is_map_and_fenceable(vma)) {
 			ptr = io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->iomap,
 						vma->node.start,
 						vma->node.size);
+		} else {
+			ptr = (void __iomem *)
+				i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
+			if (IS_ERR(ptr)) {
+				err = PTR_ERR(ptr);
+				goto err;
+			}
+			ptr = page_pack_bits(ptr, 1);
+		}
+
 		if (ptr == NULL) {
 			err = -ENOMEM;
 			goto err;
 		}
 
 		if (unlikely(cmpxchg(&vma->iomap, NULL, ptr))) {
-			io_mapping_unmap(ptr);
+			if (page_unmask_bits(ptr))
+				__i915_gem_object_release_map(vma->obj);
+			else
+				io_mapping_unmap(ptr);
 			ptr = vma->iomap;
 		}
 	}
@@ -597,7 +603,7 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
 	i915_vma_set_ggtt_write(vma);
 
 	/* NB Access through the GTT requires the device to be awake. */
-	return ptr;
+	return page_mask_bits(ptr);
 
 err_unpin:
 	__i915_vma_unpin(vma);
@@ -615,6 +621,8 @@ void i915_vma_unpin_iomap(struct i915_vma *vma)
 {
 	GEM_BUG_ON(vma->iomap == NULL);
 
+	/* XXX We keep the mapping until __i915_vma_unbind()/evict() */
+
 	i915_vma_flush_writes(vma);
 
 	i915_vma_unpin_fence(vma);
@@ -1763,7 +1771,10 @@ static void __i915_vma_iounmap(struct i915_vma *vma)
 	if (vma->iomap == NULL)
 		return;
 
-	io_mapping_unmap(vma->iomap);
+	if (page_unmask_bits(vma->iomap))
+		__i915_gem_object_release_map(vma->obj);
+	else
+		io_mapping_unmap(vma->iomap);
 	vma->iomap = NULL;
 }
 
-- 
GitLab


From 0dc987b699ce4266450d407d6d79d41eab88c5d0 Mon Sep 17 00:00:00 2001
From: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Date: Fri, 10 Jun 2022 15:12:03 +0300
Subject: [PATCH 1006/1731] drm/i915/display: Add smem fallback allocation for
 dpt

Add fallback smem allocation for dpt if stolen memory
allocation failed.

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220610121205.29645-1-juhapekka.heikkila@gmail.com
---
 drivers/gpu/drm/i915/display/intel_dpt.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c b/drivers/gpu/drm/i915/display/intel_dpt.c
index fb0e7e79e0cda..ac587647e1f50 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -4,6 +4,7 @@
  */
 
 #include "gem/i915_gem_domain.h"
+#include "gem/i915_gem_internal.h"
 #include "gt/gen8_ppgtt.h"
 
 #include "i915_drv.h"
@@ -127,8 +128,12 @@ struct i915_vma *intel_dpt_pin(struct i915_address_space *vm)
 	struct i915_vma *vma;
 	void __iomem *iomem;
 	struct i915_gem_ww_ctx ww;
+	u64 pin_flags = 0;
 	int err;
 
+	if (i915_gem_object_is_stolen(dpt->obj))
+		pin_flags |= PIN_MAPPABLE;
+
 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
 	atomic_inc(&i915->gpu_error.pending_fb_pin);
 
@@ -138,7 +143,7 @@ struct i915_vma *intel_dpt_pin(struct i915_address_space *vm)
 			continue;
 
 		vma = i915_gem_object_ggtt_pin_ww(dpt->obj, &ww, NULL, 0, 4096,
-						  HAS_LMEM(i915) ? 0 : PIN_MAPPABLE);
+						  pin_flags);
 		if (IS_ERR(vma)) {
 			err = PTR_ERR(vma);
 			continue;
@@ -248,10 +253,13 @@ intel_dpt_create(struct intel_framebuffer *fb)
 
 	size = round_up(size * sizeof(gen8_pte_t), I915_GTT_PAGE_SIZE);
 
-	if (HAS_LMEM(i915))
-		dpt_obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_CONTIGUOUS);
-	else
+	dpt_obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_CONTIGUOUS);
+	if (IS_ERR(dpt_obj) && i915_ggtt_has_aperture(to_gt(i915)->ggtt))
 		dpt_obj = i915_gem_object_create_stolen(i915, size);
+	if (IS_ERR(dpt_obj) && !HAS_LMEM(i915)) {
+		drm_dbg_kms(&i915->drm, "Allocating dpt from smem\n");
+		dpt_obj = i915_gem_object_create_internal(i915, size);
+	}
 	if (IS_ERR(dpt_obj))
 		return ERR_CAST(dpt_obj);
 
-- 
GitLab


From 485037ae9a095491beb7f893c909a76cc4f9d1e7 Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Date: Mon, 20 Jun 2022 21:05:56 +0100
Subject: [PATCH 1007/1731] regmap-irq: Fix a bug in regmap_irq_enable() for
 type_in_mask chips

When enabling a type_in_mask irq, the type_buf contents must be
AND'd with the mask of the IRQ we're enabling to avoid enabling
other IRQs by accident, which can happen if several type_in_mask
irqs share a mask register.

Fixes: bc998a730367 ("regmap: irq: handle HW using separate rising/falling edge interrupts")
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Link: https://lore.kernel.org/r/20220620200644.1961936-2-aidanmacdonald.0x0@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 drivers/base/regmap/regmap-irq.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c
index 400c7412a7dcf..4f785bc7981cd 100644
--- a/drivers/base/regmap/regmap-irq.c
+++ b/drivers/base/regmap/regmap-irq.c
@@ -252,6 +252,7 @@ static void regmap_irq_enable(struct irq_data *data)
 	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 	struct regmap *map = d->map;
 	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
+	unsigned int reg = irq_data->reg_offset / map->reg_stride;
 	unsigned int mask, type;
 
 	type = irq_data->type.type_falling_val | irq_data->type.type_rising_val;
@@ -268,14 +269,14 @@ static void regmap_irq_enable(struct irq_data *data)
 	 * at the corresponding offset in regmap_irq_set_type().
 	 */
 	if (d->chip->type_in_mask && type)
-		mask = d->type_buf[irq_data->reg_offset / map->reg_stride];
+		mask = d->type_buf[reg] & irq_data->mask;
 	else
 		mask = irq_data->mask;
 
 	if (d->chip->clear_on_unmask)
 		d->clear_status = true;
 
-	d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~mask;
+	d->mask_buf[reg] &= ~mask;
 }
 
 static void regmap_irq_disable(struct irq_data *data)
-- 
GitLab


From 3f05010f243be06478a9b11cfce0ce994f5a0890 Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Date: Mon, 20 Jun 2022 21:05:57 +0100
Subject: [PATCH 1008/1731] regmap-irq: Fix offset/index mismatch in
 read_sub_irq_data()

We need to divide the sub-irq status register offset by register
stride to get an index for the status buffer to avoid an out of
bounds write when the register stride is greater than 1.

Fixes: a2d21848d921 ("regmap: regmap-irq: Add main status register support")
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Link: https://lore.kernel.org/r/20220620200644.1961936-3-aidanmacdonald.0x0@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 drivers/base/regmap/regmap-irq.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c
index 4f785bc7981cd..a6db605707b00 100644
--- a/drivers/base/regmap/regmap-irq.c
+++ b/drivers/base/regmap/regmap-irq.c
@@ -387,6 +387,7 @@ static inline int read_sub_irq_data(struct regmap_irq_chip_data *data,
 		subreg = &chip->sub_reg_offsets[b];
 		for (i = 0; i < subreg->num_regs; i++) {
 			unsigned int offset = subreg->offset[i];
+			unsigned int index = offset / map->reg_stride;
 
 			if (chip->not_fixed_stride)
 				ret = regmap_read(map,
@@ -395,7 +396,7 @@ static inline int read_sub_irq_data(struct regmap_irq_chip_data *data,
 			else
 				ret = regmap_read(map,
 						chip->status_base + offset,
-						&data->status_buf[offset]);
+						&data->status_buf[index]);
 
 			if (ret)
 				break;
-- 
GitLab


From 877fe9d49b74e5f84346f9df34e2c7f8086dbceb Mon Sep 17 00:00:00 2001
From: Jakub Kicinski <kuba@kernel.org>
Date: Mon, 20 Jun 2022 12:12:37 -0700
Subject: [PATCH 1009/1731] Revert "drivers/net/ethernet/neterion/vxge: Fix a
 use-after-free bug in vxge-main.c"

This reverts commit 8fc74d18639a2402ca52b177e990428e26ea881f.

BAR0 is the main (only?) register bank for this device. We most
obviously can't unmap it before the netdev is unregistered.
This was pointed out in review but the patch got reposted and
merged, anyway.

The author of the patch was only testing it with a QEMU model,
which I presume does not emulate enough for the netdev to be brought
up (author's replies are not visible in lore because they kept sending
their emails in HTML).

Link: https://lore.kernel.org/all/20220616085059.680dc215@kernel.org/
Fixes: 8fc74d18639a ("drivers/net/ethernet/neterion/vxge: Fix a use-after-free bug in vxge-main.c")
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/neterion/vxge/vxge-main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/neterion/vxge/vxge-main.c b/drivers/net/ethernet/neterion/vxge/vxge-main.c
index 092fd0ae58314..fa5d4ddf429b6 100644
--- a/drivers/net/ethernet/neterion/vxge/vxge-main.c
+++ b/drivers/net/ethernet/neterion/vxge/vxge-main.c
@@ -4736,10 +4736,10 @@ static void vxge_remove(struct pci_dev *pdev)
 	for (i = 0; i < vdev->no_of_vpath; i++)
 		vxge_free_mac_add_list(&vdev->vpaths[i]);
 
-	iounmap(vdev->bar0);
 	vxge_device_unregister(hldev);
 	/* Do not call pci_disable_sriov here, as it will break child devices */
 	vxge_hw_device_terminate(hldev);
+	iounmap(vdev->bar0);
 	pci_release_region(pdev, 0);
 	pci_disable_device(pdev);
 	driver_config->config_dev_cnt--;
-- 
GitLab


From 9f7d09fe23a0112c08d2326d9116fccb5a912660 Mon Sep 17 00:00:00 2001
From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Date: Fri, 17 Jun 2022 10:01:07 +0900
Subject: [PATCH 1010/1731] iommu/ipmmu-vmsa: Fix compatible for rcar-gen4

Fix compatible string for R-Car Gen4.

Fixes: ae684caf465b ("iommu/ipmmu-vmsa: Add support for R-Car Gen4")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20220617010107.3229784-1-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
---
 drivers/iommu/ipmmu-vmsa.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
index 8fdb84b3642bd..1d42084d02767 100644
--- a/drivers/iommu/ipmmu-vmsa.c
+++ b/drivers/iommu/ipmmu-vmsa.c
@@ -987,7 +987,7 @@ static const struct of_device_id ipmmu_of_ids[] = {
 		.compatible = "renesas,ipmmu-r8a779a0",
 		.data = &ipmmu_features_rcar_gen4,
 	}, {
-		.compatible = "renesas,rcar-gen4-ipmmu",
+		.compatible = "renesas,rcar-gen4-ipmmu-vmsa",
 		.data = &ipmmu_features_rcar_gen4,
 	}, {
 		/* Terminator */
-- 
GitLab


From 3026b5ca06fa872147f9726ca7c1f658bae71abf Mon Sep 17 00:00:00 2001
From: Dan Carpenter <dan.carpenter@oracle.com>
Date: Wed, 22 Jun 2022 15:25:15 +0300
Subject: [PATCH 1011/1731] drm/vc4: fix error code in vc4_check_tex_size()

The vc4_check_tex_size() function is supposed to return false on error
but this error path accidentally returns -ENODEV (which means true).

Fixes: 30f8c74ca9b7 ("drm/vc4: Warn if some v3d code is run on BCM2711")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/YrMKK89/viQiaiAg@kili
---
 drivers/gpu/drm/vc4/vc4_validate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/vc4/vc4_validate.c b/drivers/gpu/drm/vc4/vc4_validate.c
index 833eb623d545f..2feba55bcef7b 100644
--- a/drivers/gpu/drm/vc4/vc4_validate.c
+++ b/drivers/gpu/drm/vc4/vc4_validate.c
@@ -170,7 +170,7 @@ vc4_check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo,
 	uint32_t utile_h = utile_height(cpp);
 
 	if (WARN_ON_ONCE(vc4->is_vc5))
-		return -ENODEV;
+		return false;
 
 	/* The shaded vertex format stores signed 12.4 fixed point
 	 * (-2048,2047) offsets from the viewport center, so we should
-- 
GitLab


From 85016f66af8506cb601fd4f4fde23ed327a266be Mon Sep 17 00:00:00 2001
From: Saud Farooqui <farooqui_saud@hotmail.com>
Date: Wed, 22 Jun 2022 13:59:17 +0500
Subject: [PATCH 1012/1731] drm/sun4i: Return if frontend is not present

Added return statement in sun4i_layer_format_mod_supported()
in case frontend is not present.

Signed-off-by: Saud Farooqui <farooqui_saud@hotmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/PA4P189MB1421E93EF5F8E8E00E71B7878BB29@PA4P189MB1421.EURP189.PROD.OUTLOOK.COM
---
 drivers/gpu/drm/sun4i/sun4i_layer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c b/drivers/gpu/drm/sun4i/sun4i_layer.c
index 6d43080791a04..85fb9e800ddf7 100644
--- a/drivers/gpu/drm/sun4i/sun4i_layer.c
+++ b/drivers/gpu/drm/sun4i/sun4i_layer.c
@@ -117,7 +117,7 @@ static bool sun4i_layer_format_mod_supported(struct drm_plane *plane,
 	struct sun4i_layer *layer = plane_to_sun4i_layer(plane);
 
 	if (IS_ERR_OR_NULL(layer->backend->frontend))
-		sun4i_backend_format_is_supported(format, modifier);
+		return sun4i_backend_format_is_supported(format, modifier);
 
 	return sun4i_backend_format_is_supported(format, modifier) ||
 	       sun4i_frontend_format_is_supported(format, modifier);
-- 
GitLab


From bdc48fd571a7bb0aecb9d101d78b29a05f217c72 Mon Sep 17 00:00:00 2001
From: Jiang Jian <jiangjian@cdjrlc.com>
Date: Tue, 21 Jun 2022 14:49:04 +0800
Subject: [PATCH 1013/1731] video: fbdev: omapfb: Align '*' in comment

Consider '*' alignment in comments

Signed-off-by: Jiang Jian <jiangjian@cdjrlc.com>
Signed-off-by: Helge Deller <deller@gmx.de>
---
 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c b/drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c
index 6fbfeb01b3157..170463a7e1f49 100644
--- a/drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c
+++ b/drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c
@@ -143,7 +143,7 @@ int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,
 	/*
 	 * In OMAP5+, the HFBITCLK must be divided by 2 before issuing the
 	 * HDMI_PHYPWRCMD_LDOON command.
-	*/
+	 */
 	if (phy_feat->bist_ctrl)
 		REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11);
 
-- 
GitLab


From cb5177336ecb07fe1c6804306fe8efc827643c64 Mon Sep 17 00:00:00 2001
From: Jiang Jian <jiangjian@cdjrlc.com>
Date: Wed, 22 Jun 2022 02:55:38 +0800
Subject: [PATCH 1014/1731] video: fbdev: omap: Remove duplicate 'the' in
 comment

Signed-off-by: Jiang Jian <jiangjian@cdjrlc.com>
Signed-off-by: Helge Deller <deller@gmx.de>
---
 drivers/video/fbdev/omap/sossi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/fbdev/omap/sossi.c b/drivers/video/fbdev/omap/sossi.c
index c90eb8ca58af8..66aff6cd1df08 100644
--- a/drivers/video/fbdev/omap/sossi.c
+++ b/drivers/video/fbdev/omap/sossi.c
@@ -359,7 +359,7 @@ static void sossi_set_bits_per_cycle(int bpc)
 	int bus_pick_count, bus_pick_width;
 
 	/*
-	 * We set explicitly the the bus_pick_count as well, although
+	 * We set explicitly the bus_pick_count as well, although
 	 * with remapping/reordering disabled it will be calculated by HW
 	 * as (32 / bus_pick_width).
 	 */
-- 
GitLab


From 627ce0d68eb4b53e995b08089fa9da1e513ec5ba Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Wed, 22 Jun 2022 09:00:17 -0600
Subject: [PATCH 1015/1731] ALSA: hda/realtek: Add quirk for Clevo NS50PU

Fixes headset detection on Clevo NS50PU.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20220622150017.9897-1-tcrawford@system76.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/pci/hda/patch_realtek.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index ff9a09a670ed9..cee69fa7e246a 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -9211,6 +9211,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
 	SND_PCI_QUIRK(0x1558, 0x70f3, "Clevo NH77DPQ", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE),
 	SND_PCI_QUIRK(0x1558, 0x70f4, "Clevo NH77EPY", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE),
 	SND_PCI_QUIRK(0x1558, 0x70f6, "Clevo NH77DPQ-Y", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE),
+	SND_PCI_QUIRK(0x1558, 0x7716, "Clevo NS50PU", ALC256_FIXUP_SYSTEM76_MIC_NO_PRESENCE),
 	SND_PCI_QUIRK(0x1558, 0x8228, "Clevo NR40BU", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE),
 	SND_PCI_QUIRK(0x1558, 0x8520, "Clevo NH50D[CD]", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE),
 	SND_PCI_QUIRK(0x1558, 0x8521, "Clevo NH77D[CD]", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE),
-- 
GitLab


From 1e70212e031528918066a631c9fdccda93a1ffaa Mon Sep 17 00:00:00 2001
From: Kees Cook <keescook@chromium.org>
Date: Wed, 15 Jun 2022 22:23:12 -0700
Subject: [PATCH 1016/1731] hinic: Replace memcpy() with direct assignment

Under CONFIG_FORTIFY_SOURCE=y and CONFIG_UBSAN_BOUNDS=y, Clang is bugged
here for calculating the size of the destination buffer (0x10 instead of
0x14). This copy is a fixed size (sizeof(struct fw_section_info_st)), with
the source and dest being struct fw_section_info_st, so the memcpy should
be safe, assuming the index is within bounds, which is UBSAN_BOUNDS's
responsibility to figure out.

Avoid the whole thing and just do a direct assignment. This results in
no change to the executable code.

[This is a duplicate of commit 2c0ab32b73cf ("hinic: Replace memcpy()
 with direct assignment") which was applied to net-next.]

Cc: Nick Desaulniers <ndesaulniers@google.com>
Cc: Tom Rix <trix@redhat.com>
Cc: llvm@lists.linux.dev
Link: https://github.com/ClangBuiltLinux/linux/issues/1592
Signed-off-by: Kees Cook <keescook@chromium.org>
Reviewed-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Tested-by: Nathan Chancellor <nathan@kernel.org> # build
Link: https://lore.kernel.org/r/20220616052312.292861-1-keescook@chromium.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/ethernet/huawei/hinic/hinic_devlink.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/huawei/hinic/hinic_devlink.c b/drivers/net/ethernet/huawei/hinic/hinic_devlink.c
index 60ae8bfc5f69a..1749d26f4befc 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_devlink.c
+++ b/drivers/net/ethernet/huawei/hinic/hinic_devlink.c
@@ -43,9 +43,7 @@ static bool check_image_valid(struct hinic_devlink_priv *priv, const u8 *buf,
 
 	for (i = 0; i < fw_image->fw_info.fw_section_cnt; i++) {
 		len += fw_image->fw_section_info[i].fw_section_len;
-		memcpy(&host_image->image_section_info[i],
-		       &fw_image->fw_section_info[i],
-		       sizeof(struct fw_section_info_st));
+		host_image->image_section_info[i] = fw_image->fw_section_info[i];
 	}
 
 	if (len != fw_image->fw_len ||
-- 
GitLab


From f4f9b827d76d2fa23c2a2359b4e9fb417deec61a Mon Sep 17 00:00:00 2001
From: Philip Yang <Philip.Yang@amd.com>
Date: Wed, 15 Jun 2022 16:26:35 -0400
Subject: [PATCH 1017/1731] drm/amdkfd: Add queue to MES if it becomes active

We remove the user queue from MES scheduler to update queue properties.
If the queue becomes active after updating, add the user queue to MES
scheduler, to be able to handle command packet submission.

v2: don't break pqm_set_gws

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Graham Sider <Graham.Sider@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index e1797657b04c7..21aeb05b17dbe 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -811,7 +811,6 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q,
 	struct mqd_manager *mqd_mgr;
 	struct kfd_process_device *pdd;
 	bool prev_active = false;
-	bool add_queue = false;
 
 	dqm_lock(dqm);
 	pdd = kfd_get_process_device_data(q->device, q->process);
@@ -887,7 +886,7 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q,
 	if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
 		if (!dqm->dev->shared_resources.enable_mes)
 			retval = map_queues_cpsch(dqm);
-		else if (add_queue)
+		else if (q->properties.is_active)
 			retval = add_queue_mes(dqm, q, &pdd->qpd);
 	} else if (q->properties.is_active &&
 		 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
-- 
GitLab


From ab8529b0cdb271d9b222cbbddb2641f3fca5df8f Mon Sep 17 00:00:00 2001
From: Philip Yang <Philip.Yang@amd.com>
Date: Fri, 10 Jun 2022 20:15:29 -0400
Subject: [PATCH 1018/1731] drm/amdkfd: Free queue after unmap queue success

After queue unmap or remove from MES successfully, free queue sysfs
entries, doorbell and remove from queue list. Otherwise, application may
destroy queue again, cause below kernel warning or crash backtrace.

For outstanding queues, either application forget to destroy or failed
to destroy, kfd_process_notifier_release will remove queue sysfs
entries, kfd_process_wq_release will free queue doorbell.

v2: decrement_queue_count for MES queue

 refcount_t: underflow; use-after-free.
 WARNING: CPU: 7 PID: 3053 at lib/refcount.c:28
  Call Trace:
   kobject_put+0xd6/0x1a0
   kfd_procfs_del_queue+0x27/0x30 [amdgpu]
   pqm_destroy_queue+0xeb/0x240 [amdgpu]
   kfd_ioctl_destroy_queue+0x32/0x70 [amdgpu]
   kfd_ioctl+0x27d/0x500 [amdgpu]
   do_syscall_64+0x35/0x80

 WARNING: CPU: 2 PID: 3053 at drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager.c:400
  Call Trace:
   deallocate_doorbell.isra.0+0x39/0x40 [amdgpu]
   destroy_queue_cpsch+0xb3/0x270 [amdgpu]
   pqm_destroy_queue+0x108/0x240 [amdgpu]
   kfd_ioctl_destroy_queue+0x32/0x70 [amdgpu]
   kfd_ioctl+0x27d/0x500 [amdgpu]

 general protection fault, probably for non-canonical address
0xdead000000000108:
 Call Trace:
  pqm_destroy_queue+0xf0/0x200 [amdgpu]
  kfd_ioctl_destroy_queue+0x2f/0x60 [amdgpu]
  kfd_ioctl+0x19b/0x600 [amdgpu]

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Graham Sider <Graham.Sider@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../drm/amd/amdkfd/kfd_device_queue_manager.c | 28 +++++++++++--------
 .../amd/amdkfd/kfd_process_queue_manager.c    |  2 +-
 2 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 21aeb05b17dbe..213246a5b4e4f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1872,6 +1872,22 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm,
 
 	}
 
+	if (q->properties.is_active) {
+		if (!dqm->dev->shared_resources.enable_mes) {
+			retval = execute_queues_cpsch(dqm,
+						      KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
+			if (retval == -ETIME)
+				qpd->reset_wavefronts = true;
+		} else {
+			retval = remove_queue_mes(dqm, q, qpd);
+		}
+
+		if (retval)
+			goto failed_unmap_queue;
+
+		decrement_queue_count(dqm, qpd, q);
+	}
+
 	mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
 			q->properties.type)];
 
@@ -1885,17 +1901,6 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm,
 
 	list_del(&q->list);
 	qpd->queue_count--;
-	if (q->properties.is_active) {
-		if (!dqm->dev->shared_resources.enable_mes) {
-			decrement_queue_count(dqm, qpd, q);
-			retval = execute_queues_cpsch(dqm,
-						      KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
-			if (retval == -ETIME)
-				qpd->reset_wavefronts = true;
-		} else {
-			retval = remove_queue_mes(dqm, q, qpd);
-		}
-	}
 
 	/*
 	 * Unconditionally decrement this counter, regardless of the queue's
@@ -1912,6 +1917,7 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm,
 
 	return retval;
 
+failed_unmap_queue:
 failed_try_destroy_debugged_queue:
 
 	dqm_unlock(dqm);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index dc00484ff484c..99f2a64122016 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -419,7 +419,6 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid)
 	}
 
 	if (pqn->q) {
-		kfd_procfs_del_queue(pqn->q);
 		dqm = pqn->q->device->dqm;
 		retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q);
 		if (retval) {
@@ -439,6 +438,7 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid)
 		if (dev->shared_resources.enable_mes)
 			amdgpu_amdkfd_free_gtt_mem(dev->adev,
 						   pqn->q->gang_ctx_bo);
+		kfd_procfs_del_queue(pqn->q);
 		uninit_queue(pqn->q);
 	}
 
-- 
GitLab


From 543faf57ee0ef6feb1ef60122c0abb9097083ded Mon Sep 17 00:00:00 2001
From: Darren Powell <darren.powell@amd.com>
Date: Fri, 29 Apr 2022 21:20:52 -0400
Subject: [PATCH 1019/1731] amdgpu/pm: Fix incorrect variable for size of
 clocks array

 [v2]
No Changes, added RB
 [v1]
Size of pp_clock_levels_with_latency is PP_MAX_CLOCK_LEVELS, not MAX_NUM_CLOCKS.
Both are currently defined as 16, modifying in case one value is modified in future
Changed code in both arcturus and aldabaran.

Also removed unneeded var count, and used min_t function

Signed-off-by: Darren Powell <darren.powell@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c  | 9 +++++----
 drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 9 +++++----
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index bfabcd3c45aa2..445005571f76f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -573,12 +573,13 @@ static int arcturus_get_clk_table(struct smu_context *smu,
 			struct pp_clock_levels_with_latency *clocks,
 			struct smu_11_0_dpm_table *dpm_table)
 {
-	int i, count;
+	uint32_t i;
 
-	count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
-	clocks->num_levels = count;
+	clocks->num_levels = min_t(uint32_t,
+				   dpm_table->count,
+				   (uint32_t)PP_MAX_CLOCK_LEVELS);
 
-	for (i = 0; i < count; i++) {
+	for (i = 0; i < clocks->num_levels; i++) {
 		clocks->data[i].clocks_in_khz =
 			dpm_table->dpm_levels[i].value * 1000;
 		clocks->data[i].latency_in_us = 0;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index 1133edd34e4d0..cc96a5b11d51d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -555,12 +555,13 @@ static int aldebaran_get_clk_table(struct smu_context *smu,
 				   struct pp_clock_levels_with_latency *clocks,
 				   struct smu_13_0_dpm_table *dpm_table)
 {
-	int i, count;
+	uint32_t i;
 
-	count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
-	clocks->num_levels = count;
+	clocks->num_levels = min_t(uint32_t,
+				   dpm_table->count,
+				   (uint32_t)PP_MAX_CLOCK_LEVELS);
 
-	for (i = 0; i < count; i++) {
+	for (i = 0; i < clocks->num_levels; i++) {
 		clocks->data[i].clocks_in_khz =
 			dpm_table->dpm_levels[i].value * 1000;
 		clocks->data[i].latency_in_us = 0;
-- 
GitLab


From ceb180361e3851007547c55035cd1de03f108f75 Mon Sep 17 00:00:00 2001
From: Darren Powell <darren.powell@amd.com>
Date: Wed, 11 May 2022 01:07:04 -0400
Subject: [PATCH 1020/1731] amdgpu/pm: Fix possible array out-of-bounds if SCLK
 levels != 2

 [v2]
simplified fix after Lijo's feedback
 removed clocks.num_levels from calculation of loop count
   removed unsafe accesses to shim table freq_values
 retained corner case output only min,now if
   clocks.num_levels == 1 && now > min

 [v1]
added a check to populate and use SCLK shim table freq_values only
   if using dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL or
                         AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM
removed clocks.num_levels from calculation of shim table size
removed unsafe accesses to shim table freq_values
   output gfx_table values if using other dpm levels
added check for freq_match when using freq_values for when now == min_clk

== Test ==
LOGFILE=aldebaran-sclk.test.log
AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print $9}'`
HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}

lspci -nn | grep "VGA\|Display"  > $LOGFILE
FILES="pp_od_clk_voltage
pp_dpm_sclk"

for f in $FILES
do
  echo === $f === >> $LOGFILE
  cat $HWMON_DIR/device/$f >> $LOGFILE
done
cat $LOGFILE

Signed-off-by: Darren Powell <darren.powell@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c    | 34 +++++++------------
 1 file changed, 12 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index cc96a5b11d51d..619aee51b1238 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -746,7 +746,7 @@ static int aldebaran_print_clk_levels(struct smu_context *smu,
 	struct smu_13_0_dpm_table *single_dpm_table;
 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 	struct smu_13_0_dpm_context *dpm_context = NULL;
-	uint32_t display_levels;
+	int display_levels;
 	uint32_t freq_values[3] = {0};
 	uint32_t min_clk, max_clk;
 
@@ -778,7 +778,7 @@ static int aldebaran_print_clk_levels(struct smu_context *smu,
 			return ret;
 		}
 
-		display_levels = clocks.num_levels;
+		display_levels = (clocks.num_levels == 1) ? 1 : 2;
 
 		min_clk = pstate_table->gfxclk_pstate.curr.min;
 		max_clk = pstate_table->gfxclk_pstate.curr.max;
@@ -788,30 +788,20 @@ static int aldebaran_print_clk_levels(struct smu_context *smu,
 
 		/* fine-grained dpm has only 2 levels */
 		if (now > min_clk && now < max_clk) {
-			display_levels = clocks.num_levels + 1;
+			display_levels++;
 			freq_values[2] = max_clk;
 			freq_values[1] = now;
 		}
 
-		/*
-		 * For DPM disabled case, there will be only one clock level.
-		 * And it's safe to assume that is always the current clock.
-		 */
-		if (display_levels == clocks.num_levels) {
-			for (i = 0; i < clocks.num_levels; i++)
-				size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
-					freq_values[i],
-					(clocks.num_levels == 1) ?
-						"*" :
-						(aldebaran_freqs_in_same_level(
-							 freq_values[i], now) ?
-							 "*" :
-							 ""));
-		} else {
-			for (i = 0; i < display_levels; i++)
-				size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
-						freq_values[i], i == 1 ? "*" : "");
-		}
+		for (i = 0; i < display_levels; i++)
+			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
+				freq_values[i],
+				(display_levels == 1) ?
+					"*" :
+					(aldebaran_freqs_in_same_level(
+						 freq_values[i], now) ?
+						 "*" :
+						 ""));
 
 		break;
 
-- 
GitLab


From f12d07d6e9f22bbe65d158de1435ec515acfb50a Mon Sep 17 00:00:00 2001
From: Ruijing Dong <ruijing.dong@amd.com>
Date: Wed, 22 Jun 2022 10:10:11 -0400
Subject: [PATCH 1021/1731] drm/amdgpu/vcn: fix no previous prototype warning

Declare 'static', as the function is not intended to be used
outside of this translation unit.

Fixes: 4ed49c954e35 ("drm/amdgpu/vcn: add unified queue ib test")
Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index fea4360233514..1bfdfb9207acf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -330,7 +330,7 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
 }
 
 /* from vcn4 and above, only unified queue is used */
-bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring)
+static bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 	bool ret = false;
-- 
GitLab


From f15345a377c6ea9c7cc74f079616af8856aff37f Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Thu, 19 May 2022 10:21:08 -0400
Subject: [PATCH 1022/1731] drm/amdgpu: Adjust logic around GTT size (v3)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Certain GL unit tests for large textures can cause problems
with the OOM killer since there is no way to link this memory
to a process.  This was originally mitigated (but not necessarily
eliminated) by limiting the GTT size.  The problem is this limit
is often too low for many modern games so just make the limit 1/2
of system memory. The OOM accounting needs to be addressed, but
we shouldn't prevent common 3D applications from being usable
just to potentially mitigate that corner case.

Set default GTT size to max(3G, 1/2 of system ram) by default.

v2: drop previous logic and default to 3/4 of ram
v3: default to half of ram to align with ttm
v4: fix spelling in comment (Kent)

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1942
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index be6f76a30ac68..3b4c19412625d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1798,18 +1798,26 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
 	DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
 		 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
 
-	/* Compute GTT size, either bsaed on 3/4th the size of RAM size
+	/* Compute GTT size, either based on 1/2 the size of RAM size
 	 * or whatever the user passed on module init */
 	if (amdgpu_gtt_size == -1) {
 		struct sysinfo si;
 
 		si_meminfo(&si);
-		gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
-			       adev->gmc.mc_vram_size),
-			       ((uint64_t)si.totalram * si.mem_unit * 3/4));
-	}
-	else
+		/* Certain GL unit tests for large textures can cause problems
+		 * with the OOM killer since there is no way to link this memory
+		 * to a process.  This was originally mitigated (but not necessarily
+		 * eliminated) by limiting the GTT size.  The problem is this limit
+		 * is often too low for many modern games so just make the limit 1/2
+		 * of system memory which aligns with TTM. The OOM accounting needs
+		 * to be addressed, but we shouldn't prevent common 3D applications
+		 * from being usable just to potentially mitigate that corner case.
+		 */
+		gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
+			       (u64)si.totalram * si.mem_unit / 2);
+	} else {
 		gtt_size = (uint64_t)amdgpu_gtt_size << 20;
+	}
 
 	/* Initialize GTT memory pool */
 	r = amdgpu_gtt_mgr_init(adev, gtt_size);
-- 
GitLab


From 937e24b7f5595566a64e0f856ebab9147f2e4d1b Mon Sep 17 00:00:00 2001
From: Mario Limonciello <mario.limonciello@amd.com>
Date: Wed, 15 Jun 2022 17:30:05 -0500
Subject: [PATCH 1023/1731] drm/amd: Revert "drm/amd/display: keep eDP Vdd on
 when eDP stream is already enabled"

A variety of Lenovo machines with Rembrandt APUs and OLED panels have
stopped showing the display at login.  This behavior clears up after
leaving it idle and moving the mouse or touching keyboard.

It was bisected to be caused by commit 559e2655220d ("drm/amd/display:
keep eDP Vdd on when eDP stream is already enabled").  Revert this commit
to fix the issue.

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2047
Reported-by: Aaron Ma <aaron.ma@canonical.com>
Fixes: 559e2655220d ("drm/amd/display: keep eDP Vdd on when eDP stream is already enabled")
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Tested-by: Mark Pearson <markpearson@lenovo.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../display/dc/dce110/dce110_hw_sequencer.c   | 24 ++-----------------
 1 file changed, 2 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 7eff7811769d1..5f2afa5b48142 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1766,29 +1766,9 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
 				break;
 			}
 		}
-
-		/*
-		 * TO-DO: So far the code logic below only addresses single eDP case.
-		 * For dual eDP case, there are a few things that need to be
-		 * implemented first:
-		 *
-		 * 1. Change the fastboot logic above, so eDP link[0 or 1]'s
-		 * stream[0 or 1] will all be checked.
-		 *
-		 * 2. Change keep_edp_vdd_on to an array, and maintain keep_edp_vdd_on
-		 * for each eDP.
-		 *
-		 * Once above 2 things are completed, we can then change the logic below
-		 * correspondingly, so dual eDP case will be fully covered.
-		 */
-
-		// We are trying to enable eDP, don't power down VDD if eDP stream is existing
-		if ((edp_stream_num == 1 && edp_streams[0] != NULL) || can_apply_edp_fast_boot) {
+		// We are trying to enable eDP, don't power down VDD
+		if (can_apply_edp_fast_boot)
 			keep_edp_vdd_on = true;
-			DC_LOG_EVENT_LINK_TRAINING("Keep eDP Vdd on\n");
-		} else {
-			DC_LOG_EVENT_LINK_TRAINING("No eDP stream enabled, turn eDP Vdd off\n");
-		}
 	}
 
 	// Check seamless boot support
-- 
GitLab


From 235870f659687b48b12c28f9427e6ca39dcaa81e Mon Sep 17 00:00:00 2001
From: Qingqing Zhuo <qingqing.zhuo@amd.com>
Date: Fri, 10 Jun 2022 10:43:53 -0400
Subject: [PATCH 1024/1731] drm/amd/display: Fix DC warning at driver load

[Why]
Wrong index was checked for dcfclk_mhz, causing false warning.

[How]
Fix the assertion index.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 5.18.x
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
index fb4ae800e9193..f4381725b2107 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
@@ -550,7 +550,7 @@ static void dcn315_clk_mgr_helper_populate_bw_params(
 		if (!bw_params->clk_table.entries[i].dtbclk_mhz)
 			bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
 	}
-	ASSERT(bw_params->clk_table.entries[i].dcfclk_mhz);
+	ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
 	bw_params->vram_type = bios_info->memory_type;
 	bw_params->num_channels = bios_info->ma_channel_number;
 	if (!bw_params->num_channels)
-- 
GitLab


From 98b02e9f002b21944176774cf420c4d674f6201c Mon Sep 17 00:00:00 2001
From: George Shen <george.shen@amd.com>
Date: Thu, 7 Oct 2021 15:59:44 -0400
Subject: [PATCH 1025/1731] drm/amd/display: Fix typo in override_lane_settings

[Why]
The function currently skips overriding the drive
settings of the first lane.

[How]
Change for loop to start at 0 instead of 1.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index cbc47aecd00f5..d8eee89e63ce3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -944,7 +944,7 @@ static void override_lane_settings(const struct link_training_settings *lt_setti
 
 		return;
 
-	for (lane = 1; lane < LANE_COUNT_DP_MAX; lane++) {
+	for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
 		if (lt_settings->voltage_swing)
 			lane_settings[lane].VOLTAGE_SWING = *lt_settings->voltage_swing;
 		if (lt_settings->pre_emphasis)
-- 
GitLab


From e84131a88a8cdcd6fe9f234ed98e3f8ca049142b Mon Sep 17 00:00:00 2001
From: Joshua Ashton <joshua@froggi.es>
Date: Thu, 16 Jun 2022 01:21:27 +0000
Subject: [PATCH 1026/1731] amd/display/dc: Fix COLOR_ENCODING and COLOR_RANGE
 doing nothing for DCN20+

For DCN20 and above, the code that actually hooks up the provided
input_color_space got lost at some point.

Fixes COLOR_ENCODING and COLOR_RANGE doing nothing on DCN20+.
Tested using Steam Remote Play Together + gamescope.

Update other DCNs the same wasy DCN1.x was updates in
commit a1e07ba89d49 ("drm/amd/display: Use plane->color_space for dpp if specified")

Fixes: a1e07ba89d49 ("drm/amd/display: Use plane->color_space for dpp if specified")
Signed-off-by: Joshua Ashton <joshua@froggi.es>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c   | 3 +++
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c | 3 +++
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c   | 3 +++
 3 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
index 970b65efeac10..eaa7032f0f1a3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
@@ -212,6 +212,9 @@ static void dpp2_cnv_setup (
 		break;
 	}
 
+	/* Set default color space based on format if none is given. */
+	color_space = input_color_space ? input_color_space : color_space;
+
 	if (is_2bit == 1 && alpha_2bit_lut != NULL) {
 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
index 8b6505b7dca86..f50ab961bc174 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
@@ -153,6 +153,9 @@ static void dpp201_cnv_setup(
 		break;
 	}
 
+	/* Set default color space based on format if none is given. */
+	color_space = input_color_space ? input_color_space : color_space;
+
 	if (is_2bit == 1 && alpha_2bit_lut != NULL) {
 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
index ab3918c0a15b0..0dcc07531643f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
@@ -294,6 +294,9 @@ static void dpp3_cnv_setup (
 		break;
 	}
 
+	/* Set default color space based on format if none is given. */
+	color_space = input_color_space ? input_color_space : color_space;
+
 	if (is_2bit == 1 && alpha_2bit_lut != NULL) {
 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
-- 
GitLab


From 64e06652e348f0725368853688d3c15784549fd2 Mon Sep 17 00:00:00 2001
From: Lucas De Marchi <lucas.demarchi@intel.com>
Date: Fri, 17 Jun 2022 16:05:58 -0700
Subject: [PATCH 1027/1731] agp/intel: Rename intel-gtt symbols

Exporting the symbols like intel_gtt_* creates some confusion inside
i915 that has symbols named similarly. In an attempt to isolate
platforms needing intel-gtt.ko, commit 7a5c922377b4 ("drm/i915/gt: Split
intel-gtt functions by arch") moved way too much
inside gt/intel_gt_gmch.c, even the functions that don't callout to this
module. Rename the symbols to make the separation clear.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220617230559.2109427-1-lucas.demarchi@intel.com
---
 drivers/char/agp/intel-gtt.c            | 58 ++++++++++++-------------
 drivers/gpu/drm/i915/gt/intel_gt_gmch.c | 16 +++----
 include/drm/intel-gtt.h                 | 24 +++++-----
 3 files changed, 49 insertions(+), 49 deletions(-)

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 79a1b65527c2c..fe7e2105e7667 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -744,7 +744,7 @@ static void i830_write_entry(dma_addr_t addr, unsigned int entry,
 	writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
 }
 
-bool intel_enable_gtt(void)
+bool intel_gmch_enable_gtt(void)
 {
 	u8 __iomem *reg;
 
@@ -787,7 +787,7 @@ bool intel_enable_gtt(void)
 
 	return true;
 }
-EXPORT_SYMBOL(intel_enable_gtt);
+EXPORT_SYMBOL(intel_gmch_enable_gtt);
 
 static int i830_setup(void)
 {
@@ -821,8 +821,8 @@ static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
 
 static int intel_fake_agp_configure(void)
 {
-	if (!intel_enable_gtt())
-	    return -EIO;
+	if (!intel_gmch_enable_gtt())
+		return -EIO;
 
 	intel_private.clear_fake_agp = true;
 	agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
@@ -844,20 +844,20 @@ static bool i830_check_flags(unsigned int flags)
 	return false;
 }
 
-void intel_gtt_insert_page(dma_addr_t addr,
-			   unsigned int pg,
-			   unsigned int flags)
+void intel_gmch_gtt_insert_page(dma_addr_t addr,
+				unsigned int pg,
+				unsigned int flags)
 {
 	intel_private.driver->write_entry(addr, pg, flags);
 	readl(intel_private.gtt + pg);
 	if (intel_private.driver->chipset_flush)
 		intel_private.driver->chipset_flush();
 }
-EXPORT_SYMBOL(intel_gtt_insert_page);
+EXPORT_SYMBOL(intel_gmch_gtt_insert_page);
 
-void intel_gtt_insert_sg_entries(struct sg_table *st,
-				 unsigned int pg_start,
-				 unsigned int flags)
+void intel_gmch_gtt_insert_sg_entries(struct sg_table *st,
+				      unsigned int pg_start,
+				      unsigned int flags)
 {
 	struct scatterlist *sg;
 	unsigned int len, m;
@@ -879,13 +879,13 @@ void intel_gtt_insert_sg_entries(struct sg_table *st,
 	if (intel_private.driver->chipset_flush)
 		intel_private.driver->chipset_flush();
 }
-EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
+EXPORT_SYMBOL(intel_gmch_gtt_insert_sg_entries);
 
 #if IS_ENABLED(CONFIG_AGP_INTEL)
-static void intel_gtt_insert_pages(unsigned int first_entry,
-				   unsigned int num_entries,
-				   struct page **pages,
-				   unsigned int flags)
+static void intel_gmch_gtt_insert_pages(unsigned int first_entry,
+					unsigned int num_entries,
+					struct page **pages,
+					unsigned int flags)
 {
 	int i, j;
 
@@ -905,7 +905,7 @@ static int intel_fake_agp_insert_entries(struct agp_memory *mem,
 	if (intel_private.clear_fake_agp) {
 		int start = intel_private.stolen_size / PAGE_SIZE;
 		int end = intel_private.gtt_mappable_entries;
-		intel_gtt_clear_range(start, end - start);
+		intel_gmch_gtt_clear_range(start, end - start);
 		intel_private.clear_fake_agp = false;
 	}
 
@@ -934,12 +934,12 @@ static int intel_fake_agp_insert_entries(struct agp_memory *mem,
 		if (ret != 0)
 			return ret;
 
-		intel_gtt_insert_sg_entries(&st, pg_start, type);
+		intel_gmch_gtt_insert_sg_entries(&st, pg_start, type);
 		mem->sg_list = st.sgl;
 		mem->num_sg = st.nents;
 	} else
-		intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
-				       type);
+		intel_gmch_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
+					    type);
 
 out:
 	ret = 0;
@@ -949,7 +949,7 @@ out_err:
 }
 #endif
 
-void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
+void intel_gmch_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
 {
 	unsigned int i;
 
@@ -959,7 +959,7 @@ void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
 	}
 	wmb();
 }
-EXPORT_SYMBOL(intel_gtt_clear_range);
+EXPORT_SYMBOL(intel_gmch_gtt_clear_range);
 
 #if IS_ENABLED(CONFIG_AGP_INTEL)
 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
@@ -968,7 +968,7 @@ static int intel_fake_agp_remove_entries(struct agp_memory *mem,
 	if (mem->page_count == 0)
 		return 0;
 
-	intel_gtt_clear_range(pg_start, mem->page_count);
+	intel_gmch_gtt_clear_range(pg_start, mem->page_count);
 
 	if (intel_private.needs_dmar) {
 		intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
@@ -1431,22 +1431,22 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
 }
 EXPORT_SYMBOL(intel_gmch_probe);
 
-void intel_gtt_get(u64 *gtt_total,
-		   phys_addr_t *mappable_base,
-		   resource_size_t *mappable_end)
+void intel_gmch_gtt_get(u64 *gtt_total,
+			phys_addr_t *mappable_base,
+			resource_size_t *mappable_end)
 {
 	*gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT;
 	*mappable_base = intel_private.gma_bus_addr;
 	*mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT;
 }
-EXPORT_SYMBOL(intel_gtt_get);
+EXPORT_SYMBOL(intel_gmch_gtt_get);
 
-void intel_gtt_chipset_flush(void)
+void intel_gmch_gtt_flush(void)
 {
 	if (intel_private.driver->chipset_flush)
 		intel_private.driver->chipset_flush();
 }
-EXPORT_SYMBOL(intel_gtt_chipset_flush);
+EXPORT_SYMBOL(intel_gmch_gtt_flush);
 
 void intel_gmch_remove(void)
 {
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_gmch.c b/drivers/gpu/drm/i915/gt/intel_gt_gmch.c
index 18e488672d1b3..b1a6ff4c93774 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_gmch.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_gmch.c
@@ -134,7 +134,7 @@ static void gen5_ggtt_insert_page(struct i915_address_space *vm,
 	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 
-	intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
+	intel_gmch_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
 }
 
 static void gen6_ggtt_insert_page(struct i915_address_space *vm,
@@ -175,8 +175,8 @@ static void gen5_ggtt_insert_entries(struct i915_address_space *vm,
 	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 
-	intel_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> PAGE_SHIFT,
-				    flags);
+	intel_gmch_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> PAGE_SHIFT,
+					 flags);
 }
 
 /*
@@ -306,18 +306,18 @@ static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm,
 
 void intel_gt_gmch_gen5_chipset_flush(struct intel_gt *gt)
 {
-	intel_gtt_chipset_flush();
+	intel_gmch_gtt_flush();
 }
 
 static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
-	intel_gtt_chipset_flush();
+	intel_gmch_gtt_flush();
 }
 
 static void gen5_ggtt_clear_range(struct i915_address_space *vm,
 					 u64 start, u64 length)
 {
-	intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
+	intel_gmch_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
 }
 
 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
@@ -494,7 +494,7 @@ int intel_gt_gmch_gen5_probe(struct i915_ggtt *ggtt)
 		return -EIO;
 	}
 
-	intel_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
+	intel_gmch_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
 
 	ggtt->gmadr =
 		(struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
@@ -647,7 +647,7 @@ int intel_gt_gmch_gen8_probe(struct i915_ggtt *ggtt)
 
 int intel_gt_gmch_gen5_enable_hw(struct drm_i915_private *i915)
 {
-	if (GRAPHICS_VER(i915) < 6 && !intel_enable_gtt())
+	if (GRAPHICS_VER(i915) < 6 && !intel_gmch_enable_gtt())
 		return -EIO;
 
 	return 0;
diff --git a/include/drm/intel-gtt.h b/include/drm/intel-gtt.h
index 67530bfef129c..cb0d5b7200c7f 100644
--- a/include/drm/intel-gtt.h
+++ b/include/drm/intel-gtt.h
@@ -10,24 +10,24 @@ struct agp_bridge_data;
 struct pci_dev;
 struct sg_table;
 
-void intel_gtt_get(u64 *gtt_total,
-		   phys_addr_t *mappable_base,
-		   resource_size_t *mappable_end);
+void intel_gmch_gtt_get(u64 *gtt_total,
+			phys_addr_t *mappable_base,
+			resource_size_t *mappable_end);
 
 int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
 		     struct agp_bridge_data *bridge);
 void intel_gmch_remove(void);
 
-bool intel_enable_gtt(void);
+bool intel_gmch_enable_gtt(void);
 
-void intel_gtt_chipset_flush(void);
-void intel_gtt_insert_page(dma_addr_t addr,
-			   unsigned int pg,
-			   unsigned int flags);
-void intel_gtt_insert_sg_entries(struct sg_table *st,
-				 unsigned int pg_start,
-				 unsigned int flags);
-void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries);
+void intel_gmch_gtt_flush(void);
+void intel_gmch_gtt_insert_page(dma_addr_t addr,
+				unsigned int pg,
+				unsigned int flags);
+void intel_gmch_gtt_insert_sg_entries(struct sg_table *st,
+				      unsigned int pg_start,
+				      unsigned int flags);
+void intel_gmch_gtt_clear_range(unsigned int first_entry, unsigned int num_entries);
 
 /* Special gtt memory types */
 #define AGP_DCACHE_MEMORY	1
-- 
GitLab


From 9ce07d94c9f80e1b33f5f6bc2c5a27f6cc56a6dc Mon Sep 17 00:00:00 2001
From: Lucas De Marchi <lucas.demarchi@intel.com>
Date: Fri, 17 Jun 2022 16:05:59 -0700
Subject: [PATCH 1028/1731] drm/i915/gt: Re-do the intel-gtt split

Re-do what was attempted in commit 7a5c922377b4 ("drm/i915/gt: Split
intel-gtt functions by arch"). The goal of that commit was to split the
handlers for older hardware that depend on intel-gtt.ko so i915 can
be built for non-x86 archs, after some more patches. Other archs do not
need intel-gtt.ko.

Main issue with the previous approach: it moved all the hooks, including
the gen8, which is used by all platforms gen8 and newer.  Re-do the
split moving only the handlers for gen < 6, which are the only ones
calling out to the separate module.

While at it do some minor cleanups:
  - Rename the prefix s/gen5_/gmch_/ to be more accurate what platforms
    are covered by intel_ggtt_gmch.c
  - Remove dead code for gen12 out of needs_idle_maps()
  - Remove TODO comment leftover
  - Re-order if/else ladder in ggtt_probe_hw() to keep newest platforms
    first

v2: Add minor cleanups (Matt Roper)

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220617230559.2109427-2-lucas.demarchi@intel.com
---
 drivers/gpu/drm/i915/Makefile             |   2 +-
 drivers/gpu/drm/i915/gt/intel_ggtt.c      | 561 ++++++++++++++++++-
 drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c | 132 +++++
 drivers/gpu/drm/i915/gt/intel_ggtt_gmch.h |  27 +
 drivers/gpu/drm/i915/gt/intel_gt.c        |   5 +-
 drivers/gpu/drm/i915/gt/intel_gt.h        |   9 -
 drivers/gpu/drm/i915/gt/intel_gt_gmch.c   | 654 ----------------------
 drivers/gpu/drm/i915/gt/intel_gt_gmch.h   |  46 --
 drivers/gpu/drm/i915/gt/intel_gtt.h       |  12 +-
 9 files changed, 714 insertions(+), 734 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_ggtt_gmch.h
 delete mode 100644 drivers/gpu/drm/i915/gt/intel_gt_gmch.c
 delete mode 100644 drivers/gpu/drm/i915/gt/intel_gt_gmch.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 08f5d0d6e83a7..e776aded71c00 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -130,7 +130,7 @@ gt-y += \
 	gt/shmem_utils.o \
 	gt/sysfs_engines.o
 # x86 intel-gtt module support
-gt-$(CONFIG_X86) += gt/intel_gt_gmch.o
+gt-$(CONFIG_X86) += gt/intel_ggtt_gmch.o
 # autogenerated null render state
 gt-y += \
 	gt/gen6_renderstate.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 0849a6f66309f..ffff961803137 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -3,16 +3,18 @@
  * Copyright © 2020 Intel Corporation
  */
 
-#include <linux/types.h>
 #include <asm/set_memory.h>
 #include <asm/smp.h>
+#include <linux/types.h>
+#include <linux/stop_machine.h>
 
 #include <drm/i915_drm.h>
+#include <drm/intel-gtt.h>
 
 #include "gem/i915_gem_lmem.h"
 
+#include "intel_ggtt_gmch.h"
 #include "intel_gt.h"
-#include "intel_gt_gmch.h"
 #include "intel_gt_regs.h"
 #include "i915_drv.h"
 #include "i915_scatterlist.h"
@@ -208,7 +210,7 @@ void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
 	spin_unlock_irq(&uncore->lock);
 }
 
-void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
+static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
 	struct intel_uncore *uncore = ggtt->vm.gt->uncore;
 
@@ -245,11 +247,232 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
 	return pte;
 }
 
+static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
+{
+	writeq(pte, addr);
+}
+
+static void gen8_ggtt_insert_page(struct i915_address_space *vm,
+				  dma_addr_t addr,
+				  u64 offset,
+				  enum i915_cache_level level,
+				  u32 flags)
+{
+	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+	gen8_pte_t __iomem *pte =
+		(gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
+
+	gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags));
+
+	ggtt->invalidate(ggtt);
+}
+
+static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
+				     struct i915_vma_resource *vma_res,
+				     enum i915_cache_level level,
+				     u32 flags)
+{
+	const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags);
+	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+	gen8_pte_t __iomem *gte;
+	gen8_pte_t __iomem *end;
+	struct sgt_iter iter;
+	dma_addr_t addr;
+
+	/*
+	 * Note that we ignore PTE_READ_ONLY here. The caller must be careful
+	 * not to allow the user to override access to a read only page.
+	 */
+
+	gte = (gen8_pte_t __iomem *)ggtt->gsm;
+	gte += vma_res->start / I915_GTT_PAGE_SIZE;
+	end = gte + vma_res->node_size / I915_GTT_PAGE_SIZE;
+
+	for_each_sgt_daddr(addr, iter, vma_res->bi.pages)
+		gen8_set_pte(gte++, pte_encode | addr);
+	GEM_BUG_ON(gte > end);
+
+	/* Fill the allocated but "unused" space beyond the end of the buffer */
+	while (gte < end)
+		gen8_set_pte(gte++, vm->scratch[0]->encode);
+
+	/*
+	 * We want to flush the TLBs only after we're certain all the PTE
+	 * updates have finished.
+	 */
+	ggtt->invalidate(ggtt);
+}
+
+static void gen6_ggtt_insert_page(struct i915_address_space *vm,
+				  dma_addr_t addr,
+				  u64 offset,
+				  enum i915_cache_level level,
+				  u32 flags)
+{
+	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+	gen6_pte_t __iomem *pte =
+		(gen6_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
+
+	iowrite32(vm->pte_encode(addr, level, flags), pte);
+
+	ggtt->invalidate(ggtt);
+}
+
+/*
+ * Binds an object into the global gtt with the specified cache level.
+ * The object will be accessible to the GPU via commands whose operands
+ * reference offsets within the global GTT as well as accessible by the GPU
+ * through the GMADR mapped BAR (i915->mm.gtt->gtt).
+ */
+static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
+				     struct i915_vma_resource *vma_res,
+				     enum i915_cache_level level,
+				     u32 flags)
+{
+	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+	gen6_pte_t __iomem *gte;
+	gen6_pte_t __iomem *end;
+	struct sgt_iter iter;
+	dma_addr_t addr;
+
+	gte = (gen6_pte_t __iomem *)ggtt->gsm;
+	gte += vma_res->start / I915_GTT_PAGE_SIZE;
+	end = gte + vma_res->node_size / I915_GTT_PAGE_SIZE;
+
+	for_each_sgt_daddr(addr, iter, vma_res->bi.pages)
+		iowrite32(vm->pte_encode(addr, level, flags), gte++);
+	GEM_BUG_ON(gte > end);
+
+	/* Fill the allocated but "unused" space beyond the end of the buffer */
+	while (gte < end)
+		iowrite32(vm->scratch[0]->encode, gte++);
+
+	/*
+	 * We want to flush the TLBs only after we're certain all the PTE
+	 * updates have finished.
+	 */
+	ggtt->invalidate(ggtt);
+}
+
+static void nop_clear_range(struct i915_address_space *vm,
+			    u64 start, u64 length)
+{
+}
+
+static void gen8_ggtt_clear_range(struct i915_address_space *vm,
+				  u64 start, u64 length)
+{
+	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+	unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
+	unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
+	const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
+	gen8_pte_t __iomem *gtt_base =
+		(gen8_pte_t __iomem *)ggtt->gsm + first_entry;
+	const int max_entries = ggtt_total_entries(ggtt) - first_entry;
+	int i;
+
+	if (WARN(num_entries > max_entries,
+		 "First entry = %d; Num entries = %d (max=%d)\n",
+		 first_entry, num_entries, max_entries))
+		num_entries = max_entries;
+
+	for (i = 0; i < num_entries; i++)
+		gen8_set_pte(&gtt_base[i], scratch_pte);
+}
+
+static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
+{
+	/*
+	 * Make sure the internal GAM fifo has been cleared of all GTT
+	 * writes before exiting stop_machine(). This guarantees that
+	 * any aperture accesses waiting to start in another process
+	 * cannot back up behind the GTT writes causing a hang.
+	 * The register can be any arbitrary GAM register.
+	 */
+	intel_uncore_posting_read_fw(vm->gt->uncore, GFX_FLSH_CNTL_GEN6);
+}
+
+struct insert_page {
+	struct i915_address_space *vm;
+	dma_addr_t addr;
+	u64 offset;
+	enum i915_cache_level level;
+};
+
+static int bxt_vtd_ggtt_insert_page__cb(void *_arg)
+{
+	struct insert_page *arg = _arg;
+
+	gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset, arg->level, 0);
+	bxt_vtd_ggtt_wa(arg->vm);
+
+	return 0;
+}
+
+static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space *vm,
+					  dma_addr_t addr,
+					  u64 offset,
+					  enum i915_cache_level level,
+					  u32 unused)
+{
+	struct insert_page arg = { vm, addr, offset, level };
+
+	stop_machine(bxt_vtd_ggtt_insert_page__cb, &arg, NULL);
+}
+
+struct insert_entries {
+	struct i915_address_space *vm;
+	struct i915_vma_resource *vma_res;
+	enum i915_cache_level level;
+	u32 flags;
+};
+
+static int bxt_vtd_ggtt_insert_entries__cb(void *_arg)
+{
+	struct insert_entries *arg = _arg;
+
+	gen8_ggtt_insert_entries(arg->vm, arg->vma_res, arg->level, arg->flags);
+	bxt_vtd_ggtt_wa(arg->vm);
+
+	return 0;
+}
+
+static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm,
+					     struct i915_vma_resource *vma_res,
+					     enum i915_cache_level level,
+					     u32 flags)
+{
+	struct insert_entries arg = { vm, vma_res, level, flags };
+
+	stop_machine(bxt_vtd_ggtt_insert_entries__cb, &arg, NULL);
+}
+
+static void gen6_ggtt_clear_range(struct i915_address_space *vm,
+				  u64 start, u64 length)
+{
+	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+	unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
+	unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
+	gen6_pte_t scratch_pte, __iomem *gtt_base =
+		(gen6_pte_t __iomem *)ggtt->gsm + first_entry;
+	const int max_entries = ggtt_total_entries(ggtt) - first_entry;
+	int i;
+
+	if (WARN(num_entries > max_entries,
+		 "First entry = %d; Num entries = %d (max=%d)\n",
+		 first_entry, num_entries, max_entries))
+		num_entries = max_entries;
+
+	scratch_pte = vm->scratch[0]->encode;
+	for (i = 0; i < num_entries; i++)
+		iowrite32(scratch_pte, &gtt_base[i]);
+}
+
 void intel_ggtt_bind_vma(struct i915_address_space *vm,
-			  struct i915_vm_pt_stash *stash,
-			  struct i915_vma_resource *vma_res,
-			  enum i915_cache_level cache_level,
-			  u32 flags)
+			 struct i915_vm_pt_stash *stash,
+			 struct i915_vma_resource *vma_res,
+			 enum i915_cache_level cache_level,
+			 u32 flags)
 {
 	u32 pte_flags;
 
@@ -270,7 +493,7 @@ void intel_ggtt_bind_vma(struct i915_address_space *vm,
 }
 
 void intel_ggtt_unbind_vma(struct i915_address_space *vm,
-			    struct i915_vma_resource *vma_res)
+			   struct i915_vma_resource *vma_res)
 {
 	vm->clear_range(vm, vma_res->start, vma_res->vma_size);
 }
@@ -589,12 +812,316 @@ void i915_ggtt_driver_late_release(struct drm_i915_private *i915)
 	dma_resv_fini(&ggtt->vm._resv);
 }
 
-struct resource intel_pci_resource(struct pci_dev *pdev, int bar)
+static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
+{
+	snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
+	snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
+	return snb_gmch_ctl << 20;
+}
+
+static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
+{
+	bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
+	bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
+	if (bdw_gmch_ctl)
+		bdw_gmch_ctl = 1 << bdw_gmch_ctl;
+
+#ifdef CONFIG_X86_32
+	/* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * I915_GTT_PAGE_SIZE */
+	if (bdw_gmch_ctl > 4)
+		bdw_gmch_ctl = 4;
+#endif
+
+	return bdw_gmch_ctl << 20;
+}
+
+static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
+{
+	gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
+	gmch_ctrl &= SNB_GMCH_GGMS_MASK;
+
+	if (gmch_ctrl)
+		return 1 << (20 + gmch_ctrl);
+
+	return 0;
+}
+
+static unsigned int gen6_gttmmadr_size(struct drm_i915_private *i915)
+{
+	/*
+	 * GEN6: GTTMMADR size is 4MB and GTTADR starts at 2MB offset
+	 * GEN8: GTTMMADR size is 16MB and GTTADR starts at 8MB offset
+	 */
+	GEM_BUG_ON(GRAPHICS_VER(i915) < 6);
+	return (GRAPHICS_VER(i915) < 8) ? SZ_4M : SZ_16M;
+}
+
+static unsigned int gen6_gttadr_offset(struct drm_i915_private *i915)
+{
+	return gen6_gttmmadr_size(i915) / 2;
+}
+
+static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
+{
+	struct drm_i915_private *i915 = ggtt->vm.i915;
+	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+	phys_addr_t phys_addr;
+	u32 pte_flags;
+	int ret;
+
+	GEM_WARN_ON(pci_resource_len(pdev, 0) != gen6_gttmmadr_size(i915));
+	phys_addr = pci_resource_start(pdev, 0) + gen6_gttadr_offset(i915);
+
+	/*
+	 * On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range
+	 * will be dropped. For WC mappings in general we have 64 byte burst
+	 * writes when the WC buffer is flushed, so we can't use it, but have to
+	 * resort to an uncached mapping. The WC issue is easily caught by the
+	 * readback check when writing GTT PTE entries.
+	 */
+	if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 11)
+		ggtt->gsm = ioremap(phys_addr, size);
+	else
+		ggtt->gsm = ioremap_wc(phys_addr, size);
+	if (!ggtt->gsm) {
+		drm_err(&i915->drm, "Failed to map the ggtt page table\n");
+		return -ENOMEM;
+	}
+
+	kref_init(&ggtt->vm.resv_ref);
+	ret = setup_scratch_page(&ggtt->vm);
+	if (ret) {
+		drm_err(&i915->drm, "Scratch setup failed\n");
+		/* iounmap will also get called at remove, but meh */
+		iounmap(ggtt->gsm);
+		return ret;
+	}
+
+	pte_flags = 0;
+	if (i915_gem_object_is_lmem(ggtt->vm.scratch[0]))
+		pte_flags |= PTE_LM;
+
+	ggtt->vm.scratch[0]->encode =
+		ggtt->vm.pte_encode(px_dma(ggtt->vm.scratch[0]),
+				    I915_CACHE_NONE, pte_flags);
+
+	return 0;
+}
+
+static void gen6_gmch_remove(struct i915_address_space *vm)
+{
+	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+
+	iounmap(ggtt->gsm);
+	free_scratch(vm);
+}
+
+static struct resource pci_resource(struct pci_dev *pdev, int bar)
 {
 	return (struct resource)DEFINE_RES_MEM(pci_resource_start(pdev, bar),
 					       pci_resource_len(pdev, bar));
 }
 
+static int gen8_gmch_probe(struct i915_ggtt *ggtt)
+{
+	struct drm_i915_private *i915 = ggtt->vm.i915;
+	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+	unsigned int size;
+	u16 snb_gmch_ctl;
+
+	if (!HAS_LMEM(i915)) {
+		ggtt->gmadr = pci_resource(pdev, 2);
+		ggtt->mappable_end = resource_size(&ggtt->gmadr);
+	}
+
+	pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
+	if (IS_CHERRYVIEW(i915))
+		size = chv_get_total_gtt_size(snb_gmch_ctl);
+	else
+		size = gen8_get_total_gtt_size(snb_gmch_ctl);
+
+	ggtt->vm.alloc_pt_dma = alloc_pt_dma;
+	ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
+	ggtt->vm.lmem_pt_obj_flags = I915_BO_ALLOC_PM_EARLY;
+
+	ggtt->vm.total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
+	ggtt->vm.cleanup = gen6_gmch_remove;
+	ggtt->vm.insert_page = gen8_ggtt_insert_page;
+	ggtt->vm.clear_range = nop_clear_range;
+	if (intel_scanout_needs_vtd_wa(i915))
+		ggtt->vm.clear_range = gen8_ggtt_clear_range;
+
+	ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
+
+	/*
+	 * Serialize GTT updates with aperture access on BXT if VT-d is on,
+	 * and always on CHV.
+	 */
+	if (intel_vm_no_concurrent_access_wa(i915)) {
+		ggtt->vm.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
+		ggtt->vm.insert_page    = bxt_vtd_ggtt_insert_page__BKL;
+		ggtt->vm.bind_async_flags =
+			I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
+	}
+
+	ggtt->invalidate = gen8_ggtt_invalidate;
+
+	ggtt->vm.vma_ops.bind_vma    = intel_ggtt_bind_vma;
+	ggtt->vm.vma_ops.unbind_vma  = intel_ggtt_unbind_vma;
+
+	ggtt->vm.pte_encode = gen8_ggtt_pte_encode;
+
+	setup_private_pat(ggtt->vm.gt->uncore);
+
+	return ggtt_probe_common(ggtt, size);
+}
+
+static u64 snb_pte_encode(dma_addr_t addr,
+			  enum i915_cache_level level,
+			  u32 flags)
+{
+	gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
+
+	switch (level) {
+	case I915_CACHE_L3_LLC:
+	case I915_CACHE_LLC:
+		pte |= GEN6_PTE_CACHE_LLC;
+		break;
+	case I915_CACHE_NONE:
+		pte |= GEN6_PTE_UNCACHED;
+		break;
+	default:
+		MISSING_CASE(level);
+	}
+
+	return pte;
+}
+
+static u64 ivb_pte_encode(dma_addr_t addr,
+			  enum i915_cache_level level,
+			  u32 flags)
+{
+	gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
+
+	switch (level) {
+	case I915_CACHE_L3_LLC:
+		pte |= GEN7_PTE_CACHE_L3_LLC;
+		break;
+	case I915_CACHE_LLC:
+		pte |= GEN6_PTE_CACHE_LLC;
+		break;
+	case I915_CACHE_NONE:
+		pte |= GEN6_PTE_UNCACHED;
+		break;
+	default:
+		MISSING_CASE(level);
+	}
+
+	return pte;
+}
+
+static u64 byt_pte_encode(dma_addr_t addr,
+			  enum i915_cache_level level,
+			  u32 flags)
+{
+	gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
+
+	if (!(flags & PTE_READ_ONLY))
+		pte |= BYT_PTE_WRITEABLE;
+
+	if (level != I915_CACHE_NONE)
+		pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
+
+	return pte;
+}
+
+static u64 hsw_pte_encode(dma_addr_t addr,
+			  enum i915_cache_level level,
+			  u32 flags)
+{
+	gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
+
+	if (level != I915_CACHE_NONE)
+		pte |= HSW_WB_LLC_AGE3;
+
+	return pte;
+}
+
+static u64 iris_pte_encode(dma_addr_t addr,
+			   enum i915_cache_level level,
+			   u32 flags)
+{
+	gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
+
+	switch (level) {
+	case I915_CACHE_NONE:
+		break;
+	case I915_CACHE_WT:
+		pte |= HSW_WT_ELLC_LLC_AGE3;
+		break;
+	default:
+		pte |= HSW_WB_ELLC_LLC_AGE3;
+		break;
+	}
+
+	return pte;
+}
+
+static int gen6_gmch_probe(struct i915_ggtt *ggtt)
+{
+	struct drm_i915_private *i915 = ggtt->vm.i915;
+	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+	unsigned int size;
+	u16 snb_gmch_ctl;
+
+	ggtt->gmadr = pci_resource(pdev, 2);
+	ggtt->mappable_end = resource_size(&ggtt->gmadr);
+
+	/*
+	 * 64/512MB is the current min/max we actually know of, but this is
+	 * just a coarse sanity check.
+	 */
+	if (ggtt->mappable_end < (64 << 20) ||
+	    ggtt->mappable_end > (512 << 20)) {
+		drm_err(&i915->drm, "Unknown GMADR size (%pa)\n",
+			&ggtt->mappable_end);
+		return -ENXIO;
+	}
+
+	pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
+
+	size = gen6_get_total_gtt_size(snb_gmch_ctl);
+	ggtt->vm.total = (size / sizeof(gen6_pte_t)) * I915_GTT_PAGE_SIZE;
+
+	ggtt->vm.alloc_pt_dma = alloc_pt_dma;
+	ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
+
+	ggtt->vm.clear_range = nop_clear_range;
+	if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
+		ggtt->vm.clear_range = gen6_ggtt_clear_range;
+	ggtt->vm.insert_page = gen6_ggtt_insert_page;
+	ggtt->vm.insert_entries = gen6_ggtt_insert_entries;
+	ggtt->vm.cleanup = gen6_gmch_remove;
+
+	ggtt->invalidate = gen6_ggtt_invalidate;
+
+	if (HAS_EDRAM(i915))
+		ggtt->vm.pte_encode = iris_pte_encode;
+	else if (IS_HASWELL(i915))
+		ggtt->vm.pte_encode = hsw_pte_encode;
+	else if (IS_VALLEYVIEW(i915))
+		ggtt->vm.pte_encode = byt_pte_encode;
+	else if (GRAPHICS_VER(i915) >= 7)
+		ggtt->vm.pte_encode = ivb_pte_encode;
+	else
+		ggtt->vm.pte_encode = snb_pte_encode;
+
+	ggtt->vm.vma_ops.bind_vma    = intel_ggtt_bind_vma;
+	ggtt->vm.vma_ops.unbind_vma  = intel_ggtt_unbind_vma;
+
+	return ggtt_probe_common(ggtt, size);
+}
+
 static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
 {
 	struct drm_i915_private *i915 = gt->i915;
@@ -605,12 +1132,13 @@ static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
 	ggtt->vm.dma = i915->drm.dev;
 	dma_resv_init(&ggtt->vm._resv);
 
-	if (GRAPHICS_VER(i915) <= 5)
-		ret = intel_gt_gmch_gen5_probe(ggtt);
-	else if (GRAPHICS_VER(i915) < 8)
-		ret = intel_gt_gmch_gen6_probe(ggtt);
+	if (GRAPHICS_VER(i915) >= 8)
+		ret = gen8_gmch_probe(ggtt);
+	else if (GRAPHICS_VER(i915) >= 6)
+		ret = gen6_gmch_probe(ggtt);
 	else
-		ret = intel_gt_gmch_gen8_probe(ggtt);
+		ret = intel_ggtt_gmch_probe(ggtt);
+
 	if (ret) {
 		dma_resv_fini(&ggtt->vm._resv);
 		return ret;
@@ -664,7 +1192,10 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
 
 int i915_ggtt_enable_hw(struct drm_i915_private *i915)
 {
-	return intel_gt_gmch_gen5_enable_hw(i915);
+	if (GRAPHICS_VER(i915) < 6)
+		return intel_ggtt_gmch_enable_hw(i915);
+
+	return 0;
 }
 
 void i915_ggtt_enable_guc(struct i915_ggtt *ggtt)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c b/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c
new file mode 100644
index 0000000000000..4e2163a1aa469
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include "intel_ggtt_gmch.h"
+
+#include <drm/intel-gtt.h>
+#include <drm/i915_drm.h>
+
+#include <linux/agp_backend.h>
+
+#include "i915_drv.h"
+#include "i915_utils.h"
+#include "intel_gtt.h"
+#include "intel_gt_regs.h"
+#include "intel_gt.h"
+
+static void gmch_ggtt_insert_page(struct i915_address_space *vm,
+				  dma_addr_t addr,
+				  u64 offset,
+				  enum i915_cache_level cache_level,
+				  u32 unused)
+{
+	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
+		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
+
+	intel_gmch_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
+}
+
+static void gmch_ggtt_insert_entries(struct i915_address_space *vm,
+				     struct i915_vma_resource *vma_res,
+				     enum i915_cache_level cache_level,
+				     u32 unused)
+{
+	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
+		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
+
+	intel_gmch_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> PAGE_SHIFT,
+					 flags);
+}
+
+static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
+{
+	intel_gmch_gtt_flush();
+}
+
+static void gmch_ggtt_clear_range(struct i915_address_space *vm,
+				  u64 start, u64 length)
+{
+	intel_gmch_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
+}
+
+static void gmch_ggtt_remove(struct i915_address_space *vm)
+{
+	intel_gmch_remove();
+}
+
+/*
+ * Certain Gen5 chipsets require idling the GPU before unmapping anything from
+ * the GTT when VT-d is enabled.
+ */
+static bool needs_idle_maps(struct drm_i915_private *i915)
+{
+	/*
+	 * Query intel_iommu to see if we need the workaround. Presumably that
+	 * was loaded first.
+	 */
+	if (!i915_vtd_active(i915))
+		return false;
+
+	if (GRAPHICS_VER(i915) == 5 && IS_MOBILE(i915))
+		return true;
+
+	return false;
+}
+
+int intel_ggtt_gmch_probe(struct i915_ggtt *ggtt)
+{
+	struct drm_i915_private *i915 = ggtt->vm.i915;
+	phys_addr_t gmadr_base;
+	int ret;
+
+	ret = intel_gmch_probe(i915->bridge_dev, to_pci_dev(i915->drm.dev), NULL);
+	if (!ret) {
+		drm_err(&i915->drm, "failed to set up gmch\n");
+		return -EIO;
+	}
+
+	intel_gmch_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
+
+	ggtt->gmadr =
+		(struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
+
+	ggtt->vm.alloc_pt_dma = alloc_pt_dma;
+	ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
+
+	if (needs_idle_maps(i915)) {
+		drm_notice(&i915->drm,
+			   "Flushing DMA requests before IOMMU unmaps; performance may be degraded\n");
+		ggtt->do_idle_maps = true;
+	}
+
+	ggtt->vm.insert_page = gmch_ggtt_insert_page;
+	ggtt->vm.insert_entries = gmch_ggtt_insert_entries;
+	ggtt->vm.clear_range = gmch_ggtt_clear_range;
+	ggtt->vm.cleanup = gmch_ggtt_remove;
+
+	ggtt->invalidate = gmch_ggtt_invalidate;
+
+	ggtt->vm.vma_ops.bind_vma    = intel_ggtt_bind_vma;
+	ggtt->vm.vma_ops.unbind_vma  = intel_ggtt_unbind_vma;
+
+	if (unlikely(ggtt->do_idle_maps))
+		drm_notice(&i915->drm,
+			   "Applying Ironlake quirks for intel_iommu\n");
+
+	return 0;
+}
+
+int intel_ggtt_gmch_enable_hw(struct drm_i915_private *i915)
+{
+	if (!intel_gmch_enable_gtt())
+		return -EIO;
+
+	return 0;
+}
+
+void intel_ggtt_gmch_flush(void)
+{
+	intel_gmch_gtt_flush();
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.h b/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.h
new file mode 100644
index 0000000000000..370bf321b4e26
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_GGTT_GMCH_H__
+#define __INTEL_GGTT_GMCH_H__
+
+#include "intel_gtt.h"
+
+/* For x86 platforms */
+#if IS_ENABLED(CONFIG_X86)
+
+void intel_ggtt_gmch_flush(void);
+int intel_ggtt_gmch_enable_hw(struct drm_i915_private *i915);
+int intel_ggtt_gmch_probe(struct i915_ggtt *ggtt);
+
+/* Stubs for non-x86 platforms */
+#else
+
+static inline void intel_ggtt_gmch_flush(void) { }
+static inline int intel_ggtt_gmch_enable_hw(struct drm_i915_private *i915) { return -ENODEV; }
+static inline int intel_ggtt_gmch_probe(struct i915_ggtt *ggtt) { return -ENODEV; }
+
+#endif
+
+#endif /* __INTEL_GGTT_GMCH_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index be9877c4b4969..8da3314bb6bf6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -4,6 +4,7 @@
  */
 
 #include <drm/drm_managed.h>
+#include <drm/intel-gtt.h>
 
 #include "gem/i915_gem_internal.h"
 #include "gem/i915_gem_lmem.h"
@@ -12,11 +13,11 @@
 #include "i915_drv.h"
 #include "intel_context.h"
 #include "intel_engine_regs.h"
+#include "intel_ggtt_gmch.h"
 #include "intel_gt.h"
 #include "intel_gt_buffer_pool.h"
 #include "intel_gt_clock_utils.h"
 #include "intel_gt_debugfs.h"
-#include "intel_gt_gmch.h"
 #include "intel_gt_mcr.h"
 #include "intel_gt_pm.h"
 #include "intel_gt_regs.h"
@@ -387,7 +388,7 @@ void intel_gt_chipset_flush(struct intel_gt *gt)
 {
 	wmb();
 	if (GRAPHICS_VER(gt->i915) < 6)
-		intel_gt_gmch_gen5_chipset_flush(gt);
+		intel_ggtt_gmch_flush();
 }
 
 void intel_gt_driver_register(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 61d30d5c7e90f..82d6f248d8762 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -13,13 +13,6 @@
 struct drm_i915_private;
 struct drm_printer;
 
-struct insert_entries {
-	struct i915_address_space *vm;
-	struct i915_vma_resource *vma_res;
-	enum i915_cache_level level;
-	u32 flags;
-};
-
 #define GT_TRACE(gt, fmt, ...) do {					\
 	const struct intel_gt *gt__ __maybe_unused = (gt);		\
 	GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev),		\
@@ -110,6 +103,4 @@ void intel_gt_watchdog_work(struct work_struct *work);
 
 void intel_gt_invalidate_tlbs(struct intel_gt *gt);
 
-struct resource intel_pci_resource(struct pci_dev *pdev, int bar);
-
 #endif /* __INTEL_GT_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_gmch.c b/drivers/gpu/drm/i915/gt/intel_gt_gmch.c
deleted file mode 100644
index b1a6ff4c93774..0000000000000
--- a/drivers/gpu/drm/i915/gt/intel_gt_gmch.c
+++ /dev/null
@@ -1,654 +0,0 @@
-// SPDX-License-Identifier: MIT
-/*
- * Copyright © 2022 Intel Corporation
- */
-
-#include <drm/intel-gtt.h>
-#include <drm/i915_drm.h>
-
-#include <linux/agp_backend.h>
-#include <linux/stop_machine.h>
-
-#include "i915_drv.h"
-#include "intel_gt_gmch.h"
-#include "intel_gt_regs.h"
-#include "intel_gt.h"
-#include "i915_utils.h"
-
-#include "gen8_ppgtt.h"
-
-struct insert_page {
-	struct i915_address_space *vm;
-	dma_addr_t addr;
-	u64 offset;
-	enum i915_cache_level level;
-};
-
-static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
-{
-	writeq(pte, addr);
-}
-
-static void nop_clear_range(struct i915_address_space *vm,
-			    u64 start, u64 length)
-{
-}
-
-static u64 snb_pte_encode(dma_addr_t addr,
-			  enum i915_cache_level level,
-			  u32 flags)
-{
-	gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
-
-	switch (level) {
-	case I915_CACHE_L3_LLC:
-	case I915_CACHE_LLC:
-		pte |= GEN6_PTE_CACHE_LLC;
-		break;
-	case I915_CACHE_NONE:
-		pte |= GEN6_PTE_UNCACHED;
-		break;
-	default:
-		MISSING_CASE(level);
-	}
-
-	return pte;
-}
-
-static u64 ivb_pte_encode(dma_addr_t addr,
-			  enum i915_cache_level level,
-			  u32 flags)
-{
-	gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
-
-	switch (level) {
-	case I915_CACHE_L3_LLC:
-		pte |= GEN7_PTE_CACHE_L3_LLC;
-		break;
-	case I915_CACHE_LLC:
-		pte |= GEN6_PTE_CACHE_LLC;
-		break;
-	case I915_CACHE_NONE:
-		pte |= GEN6_PTE_UNCACHED;
-		break;
-	default:
-		MISSING_CASE(level);
-	}
-
-	return pte;
-}
-
-static u64 byt_pte_encode(dma_addr_t addr,
-			  enum i915_cache_level level,
-			  u32 flags)
-{
-	gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
-
-	if (!(flags & PTE_READ_ONLY))
-		pte |= BYT_PTE_WRITEABLE;
-
-	if (level != I915_CACHE_NONE)
-		pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
-
-	return pte;
-}
-
-static u64 hsw_pte_encode(dma_addr_t addr,
-			  enum i915_cache_level level,
-			  u32 flags)
-{
-	gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
-
-	if (level != I915_CACHE_NONE)
-		pte |= HSW_WB_LLC_AGE3;
-
-	return pte;
-}
-
-static u64 iris_pte_encode(dma_addr_t addr,
-			   enum i915_cache_level level,
-			   u32 flags)
-{
-	gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
-
-	switch (level) {
-	case I915_CACHE_NONE:
-		break;
-	case I915_CACHE_WT:
-		pte |= HSW_WT_ELLC_LLC_AGE3;
-		break;
-	default:
-		pte |= HSW_WB_ELLC_LLC_AGE3;
-		break;
-	}
-
-	return pte;
-}
-
-static void gen5_ggtt_insert_page(struct i915_address_space *vm,
-				  dma_addr_t addr,
-				  u64 offset,
-				  enum i915_cache_level cache_level,
-				  u32 unused)
-{
-	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
-		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
-
-	intel_gmch_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
-}
-
-static void gen6_ggtt_insert_page(struct i915_address_space *vm,
-				  dma_addr_t addr,
-				  u64 offset,
-				  enum i915_cache_level level,
-				  u32 flags)
-{
-	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
-	gen6_pte_t __iomem *pte =
-		(gen6_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
-
-	iowrite32(vm->pte_encode(addr, level, flags), pte);
-
-	ggtt->invalidate(ggtt);
-}
-
-static void gen8_ggtt_insert_page(struct i915_address_space *vm,
-				  dma_addr_t addr,
-				  u64 offset,
-				  enum i915_cache_level level,
-				  u32 flags)
-{
-	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
-	gen8_pte_t __iomem *pte =
-		(gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
-
-	gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags));
-
-	ggtt->invalidate(ggtt);
-}
-
-static void gen5_ggtt_insert_entries(struct i915_address_space *vm,
-				     struct i915_vma_resource *vma_res,
-				     enum i915_cache_level cache_level,
-				     u32 unused)
-{
-	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
-		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
-
-	intel_gmch_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> PAGE_SHIFT,
-					 flags);
-}
-
-/*
- * Binds an object into the global gtt with the specified cache level.
- * The object will be accessible to the GPU via commands whose operands
- * reference offsets within the global GTT as well as accessible by the GPU
- * through the GMADR mapped BAR (i915->mm.gtt->gtt).
- */
-static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
-				     struct i915_vma_resource *vma_res,
-				     enum i915_cache_level level,
-				     u32 flags)
-{
-	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
-	gen6_pte_t __iomem *gte;
-	gen6_pte_t __iomem *end;
-	struct sgt_iter iter;
-	dma_addr_t addr;
-
-	gte = (gen6_pte_t __iomem *)ggtt->gsm;
-	gte += vma_res->start / I915_GTT_PAGE_SIZE;
-	end = gte + vma_res->node_size / I915_GTT_PAGE_SIZE;
-
-	for_each_sgt_daddr(addr, iter, vma_res->bi.pages)
-		iowrite32(vm->pte_encode(addr, level, flags), gte++);
-	GEM_BUG_ON(gte > end);
-
-	/* Fill the allocated but "unused" space beyond the end of the buffer */
-	while (gte < end)
-		iowrite32(vm->scratch[0]->encode, gte++);
-
-	/*
-	 * We want to flush the TLBs only after we're certain all the PTE
-	 * updates have finished.
-	 */
-	ggtt->invalidate(ggtt);
-}
-
-static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
-				     struct i915_vma_resource *vma_res,
-				     enum i915_cache_level level,
-				     u32 flags)
-{
-	const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags);
-	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
-	gen8_pte_t __iomem *gte;
-	gen8_pte_t __iomem *end;
-	struct sgt_iter iter;
-	dma_addr_t addr;
-
-	/*
-	 * Note that we ignore PTE_READ_ONLY here. The caller must be careful
-	 * not to allow the user to override access to a read only page.
-	 */
-
-	gte = (gen8_pte_t __iomem *)ggtt->gsm;
-	gte += vma_res->start / I915_GTT_PAGE_SIZE;
-	end = gte + vma_res->node_size / I915_GTT_PAGE_SIZE;
-
-	for_each_sgt_daddr(addr, iter, vma_res->bi.pages)
-		gen8_set_pte(gte++, pte_encode | addr);
-	GEM_BUG_ON(gte > end);
-
-	/* Fill the allocated but "unused" space beyond the end of the buffer */
-	while (gte < end)
-		gen8_set_pte(gte++, vm->scratch[0]->encode);
-
-	/*
-	 * We want to flush the TLBs only after we're certain all the PTE
-	 * updates have finished.
-	 */
-	ggtt->invalidate(ggtt);
-}
-
-static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
-{
-	/*
-	 * Make sure the internal GAM fifo has been cleared of all GTT
-	 * writes before exiting stop_machine(). This guarantees that
-	 * any aperture accesses waiting to start in another process
-	 * cannot back up behind the GTT writes causing a hang.
-	 * The register can be any arbitrary GAM register.
-	 */
-	intel_uncore_posting_read_fw(vm->gt->uncore, GFX_FLSH_CNTL_GEN6);
-}
-
-static int bxt_vtd_ggtt_insert_page__cb(void *_arg)
-{
-	struct insert_page *arg = _arg;
-
-	gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset, arg->level, 0);
-	bxt_vtd_ggtt_wa(arg->vm);
-
-	return 0;
-}
-
-static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space *vm,
-					  dma_addr_t addr,
-					  u64 offset,
-					  enum i915_cache_level level,
-					  u32 unused)
-{
-	struct insert_page arg = { vm, addr, offset, level };
-
-	stop_machine(bxt_vtd_ggtt_insert_page__cb, &arg, NULL);
-}
-
-static int bxt_vtd_ggtt_insert_entries__cb(void *_arg)
-{
-	struct insert_entries *arg = _arg;
-
-	gen8_ggtt_insert_entries(arg->vm, arg->vma_res, arg->level, arg->flags);
-	bxt_vtd_ggtt_wa(arg->vm);
-
-	return 0;
-}
-
-static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm,
-					     struct i915_vma_resource *vma_res,
-					     enum i915_cache_level level,
-					     u32 flags)
-{
-	struct insert_entries arg = { vm, vma_res, level, flags };
-
-	stop_machine(bxt_vtd_ggtt_insert_entries__cb, &arg, NULL);
-}
-
-void intel_gt_gmch_gen5_chipset_flush(struct intel_gt *gt)
-{
-	intel_gmch_gtt_flush();
-}
-
-static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
-{
-	intel_gmch_gtt_flush();
-}
-
-static void gen5_ggtt_clear_range(struct i915_address_space *vm,
-					 u64 start, u64 length)
-{
-	intel_gmch_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
-}
-
-static void gen6_ggtt_clear_range(struct i915_address_space *vm,
-				  u64 start, u64 length)
-{
-	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
-	unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
-	unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
-	gen6_pte_t scratch_pte, __iomem *gtt_base =
-		(gen6_pte_t __iomem *)ggtt->gsm + first_entry;
-	const int max_entries = ggtt_total_entries(ggtt) - first_entry;
-	int i;
-
-	if (WARN(num_entries > max_entries,
-		 "First entry = %d; Num entries = %d (max=%d)\n",
-		 first_entry, num_entries, max_entries))
-		num_entries = max_entries;
-
-	scratch_pte = vm->scratch[0]->encode;
-	for (i = 0; i < num_entries; i++)
-		iowrite32(scratch_pte, &gtt_base[i]);
-}
-
-static void gen8_ggtt_clear_range(struct i915_address_space *vm,
-				  u64 start, u64 length)
-{
-	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
-	unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
-	unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
-	const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
-	gen8_pte_t __iomem *gtt_base =
-		(gen8_pte_t __iomem *)ggtt->gsm + first_entry;
-	const int max_entries = ggtt_total_entries(ggtt) - first_entry;
-	int i;
-
-	if (WARN(num_entries > max_entries,
-		 "First entry = %d; Num entries = %d (max=%d)\n",
-		 first_entry, num_entries, max_entries))
-		num_entries = max_entries;
-
-	for (i = 0; i < num_entries; i++)
-		gen8_set_pte(&gtt_base[i], scratch_pte);
-}
-
-static void gen5_gmch_remove(struct i915_address_space *vm)
-{
-	intel_gmch_remove();
-}
-
-static void gen6_gmch_remove(struct i915_address_space *vm)
-{
-	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
-
-	iounmap(ggtt->gsm);
-	free_scratch(vm);
-}
-
-/*
- * Certain Gen5 chipsets require idling the GPU before
- * unmapping anything from the GTT when VT-d is enabled.
- */
-static bool needs_idle_maps(struct drm_i915_private *i915)
-{
-	/*
-	 * Query intel_iommu to see if we need the workaround. Presumably that
-	 * was loaded first.
-	 */
-	if (!i915_vtd_active(i915))
-		return false;
-
-	if (GRAPHICS_VER(i915) == 5 && IS_MOBILE(i915))
-		return true;
-
-	if (GRAPHICS_VER(i915) == 12)
-		return true; /* XXX DMAR fault reason 7 */
-
-	return false;
-}
-
-static unsigned int gen6_gttmmadr_size(struct drm_i915_private *i915)
-{
-	/*
-	 * GEN6: GTTMMADR size is 4MB and GTTADR starts at 2MB offset
-	 * GEN8: GTTMMADR size is 16MB and GTTADR starts at 8MB offset
-	 */
-	GEM_BUG_ON(GRAPHICS_VER(i915) < 6);
-	return (GRAPHICS_VER(i915) < 8) ? SZ_4M : SZ_16M;
-}
-
-static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
-{
-	snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
-	snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
-	return snb_gmch_ctl << 20;
-}
-
-static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
-{
-	bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
-	bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
-	if (bdw_gmch_ctl)
-		bdw_gmch_ctl = 1 << bdw_gmch_ctl;
-
-#ifdef CONFIG_X86_32
-	/* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * I915_GTT_PAGE_SIZE */
-	if (bdw_gmch_ctl > 4)
-		bdw_gmch_ctl = 4;
-#endif
-
-	return bdw_gmch_ctl << 20;
-}
-
-static unsigned int gen6_gttadr_offset(struct drm_i915_private *i915)
-{
-	return gen6_gttmmadr_size(i915) / 2;
-}
-
-static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
-{
-	struct drm_i915_private *i915 = ggtt->vm.i915;
-	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
-	phys_addr_t phys_addr;
-	u32 pte_flags;
-	int ret;
-
-	GEM_WARN_ON(pci_resource_len(pdev, 0) != gen6_gttmmadr_size(i915));
-	phys_addr = pci_resource_start(pdev, 0) + gen6_gttadr_offset(i915);
-
-	/*
-	 * On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range
-	 * will be dropped. For WC mappings in general we have 64 byte burst
-	 * writes when the WC buffer is flushed, so we can't use it, but have to
-	 * resort to an uncached mapping. The WC issue is easily caught by the
-	 * readback check when writing GTT PTE entries.
-	 */
-	if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 11)
-		ggtt->gsm = ioremap(phys_addr, size);
-	else
-		ggtt->gsm = ioremap_wc(phys_addr, size);
-	if (!ggtt->gsm) {
-		drm_err(&i915->drm, "Failed to map the ggtt page table\n");
-		return -ENOMEM;
-	}
-
-	kref_init(&ggtt->vm.resv_ref);
-	ret = setup_scratch_page(&ggtt->vm);
-	if (ret) {
-		drm_err(&i915->drm, "Scratch setup failed\n");
-		/* iounmap will also get called at remove, but meh */
-		iounmap(ggtt->gsm);
-		return ret;
-	}
-
-	pte_flags = 0;
-	if (i915_gem_object_is_lmem(ggtt->vm.scratch[0]))
-		pte_flags |= PTE_LM;
-
-	ggtt->vm.scratch[0]->encode =
-		ggtt->vm.pte_encode(px_dma(ggtt->vm.scratch[0]),
-				    I915_CACHE_NONE, pte_flags);
-
-	return 0;
-}
-
-int intel_gt_gmch_gen5_probe(struct i915_ggtt *ggtt)
-{
-	struct drm_i915_private *i915 = ggtt->vm.i915;
-	phys_addr_t gmadr_base;
-	int ret;
-
-	ret = intel_gmch_probe(i915->bridge_dev, to_pci_dev(i915->drm.dev), NULL);
-	if (!ret) {
-		drm_err(&i915->drm, "failed to set up gmch\n");
-		return -EIO;
-	}
-
-	intel_gmch_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
-
-	ggtt->gmadr =
-		(struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
-
-	ggtt->vm.alloc_pt_dma = alloc_pt_dma;
-	ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
-
-	if (needs_idle_maps(i915)) {
-		drm_notice(&i915->drm,
-			   "Flushing DMA requests before IOMMU unmaps; performance may be degraded\n");
-		ggtt->do_idle_maps = true;
-	}
-
-	ggtt->vm.insert_page = gen5_ggtt_insert_page;
-	ggtt->vm.insert_entries = gen5_ggtt_insert_entries;
-	ggtt->vm.clear_range = gen5_ggtt_clear_range;
-	ggtt->vm.cleanup = gen5_gmch_remove;
-
-	ggtt->invalidate = gmch_ggtt_invalidate;
-
-	ggtt->vm.vma_ops.bind_vma    = intel_ggtt_bind_vma;
-	ggtt->vm.vma_ops.unbind_vma  = intel_ggtt_unbind_vma;
-
-	if (unlikely(ggtt->do_idle_maps))
-		drm_notice(&i915->drm,
-			   "Applying Ironlake quirks for intel_iommu\n");
-
-	return 0;
-}
-
-int intel_gt_gmch_gen6_probe(struct i915_ggtt *ggtt)
-{
-	struct drm_i915_private *i915 = ggtt->vm.i915;
-	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
-	unsigned int size;
-	u16 snb_gmch_ctl;
-
-	ggtt->gmadr = intel_pci_resource(pdev, 2);
-	ggtt->mappable_end = resource_size(&ggtt->gmadr);
-
-	/*
-	 * 64/512MB is the current min/max we actually know of, but this is
-	 * just a coarse sanity check.
-	 */
-	if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) {
-		drm_err(&i915->drm, "Unknown GMADR size (%pa)\n",
-			&ggtt->mappable_end);
-		return -ENXIO;
-	}
-
-	pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
-
-	size = gen6_get_total_gtt_size(snb_gmch_ctl);
-	ggtt->vm.total = (size / sizeof(gen6_pte_t)) * I915_GTT_PAGE_SIZE;
-
-	ggtt->vm.alloc_pt_dma = alloc_pt_dma;
-	ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
-
-	ggtt->vm.clear_range = nop_clear_range;
-	if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
-		ggtt->vm.clear_range = gen6_ggtt_clear_range;
-	ggtt->vm.insert_page = gen6_ggtt_insert_page;
-	ggtt->vm.insert_entries = gen6_ggtt_insert_entries;
-	ggtt->vm.cleanup = gen6_gmch_remove;
-
-	ggtt->invalidate = gen6_ggtt_invalidate;
-
-	if (HAS_EDRAM(i915))
-		ggtt->vm.pte_encode = iris_pte_encode;
-	else if (IS_HASWELL(i915))
-		ggtt->vm.pte_encode = hsw_pte_encode;
-	else if (IS_VALLEYVIEW(i915))
-		ggtt->vm.pte_encode = byt_pte_encode;
-	else if (GRAPHICS_VER(i915) >= 7)
-		ggtt->vm.pte_encode = ivb_pte_encode;
-	else
-		ggtt->vm.pte_encode = snb_pte_encode;
-
-	ggtt->vm.vma_ops.bind_vma    = intel_ggtt_bind_vma;
-	ggtt->vm.vma_ops.unbind_vma  = intel_ggtt_unbind_vma;
-
-	return ggtt_probe_common(ggtt, size);
-}
-
-static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
-{
-	gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
-	gmch_ctrl &= SNB_GMCH_GGMS_MASK;
-
-	if (gmch_ctrl)
-		return 1 << (20 + gmch_ctrl);
-
-	return 0;
-}
-
-int intel_gt_gmch_gen8_probe(struct i915_ggtt *ggtt)
-{
-	struct drm_i915_private *i915 = ggtt->vm.i915;
-	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
-	unsigned int size;
-	u16 snb_gmch_ctl;
-
-	/* TODO: We're not aware of mappable constraints on gen8 yet */
-	if (!HAS_LMEM(i915)) {
-		ggtt->gmadr = intel_pci_resource(pdev, 2);
-		ggtt->mappable_end = resource_size(&ggtt->gmadr);
-	}
-
-	pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
-	if (IS_CHERRYVIEW(i915))
-		size = chv_get_total_gtt_size(snb_gmch_ctl);
-	else
-		size = gen8_get_total_gtt_size(snb_gmch_ctl);
-
-	ggtt->vm.alloc_pt_dma = alloc_pt_dma;
-	ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
-	ggtt->vm.lmem_pt_obj_flags = I915_BO_ALLOC_PM_EARLY;
-
-	ggtt->vm.total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
-	ggtt->vm.cleanup = gen6_gmch_remove;
-	ggtt->vm.insert_page = gen8_ggtt_insert_page;
-	ggtt->vm.clear_range = nop_clear_range;
-	if (intel_scanout_needs_vtd_wa(i915))
-		ggtt->vm.clear_range = gen8_ggtt_clear_range;
-
-	ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
-
-	/*
-	 * Serialize GTT updates with aperture access on BXT if VT-d is on,
-	 * and always on CHV.
-	 */
-	if (intel_vm_no_concurrent_access_wa(i915)) {
-		ggtt->vm.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
-		ggtt->vm.insert_page    = bxt_vtd_ggtt_insert_page__BKL;
-		ggtt->vm.bind_async_flags =
-			I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
-	}
-
-	ggtt->invalidate = gen8_ggtt_invalidate;
-
-	ggtt->vm.vma_ops.bind_vma    = intel_ggtt_bind_vma;
-	ggtt->vm.vma_ops.unbind_vma  = intel_ggtt_unbind_vma;
-
-	ggtt->vm.pte_encode = gen8_ggtt_pte_encode;
-
-	setup_private_pat(ggtt->vm.gt->uncore);
-
-	return ggtt_probe_common(ggtt, size);
-}
-
-int intel_gt_gmch_gen5_enable_hw(struct drm_i915_private *i915)
-{
-	if (GRAPHICS_VER(i915) < 6 && !intel_gmch_enable_gtt())
-		return -EIO;
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_gmch.h b/drivers/gpu/drm/i915/gt/intel_gt_gmch.h
deleted file mode 100644
index 75ed55c1f30aa..0000000000000
--- a/drivers/gpu/drm/i915/gt/intel_gt_gmch.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright © 2022 Intel Corporation
- */
-
-#ifndef __INTEL_GT_GMCH_H__
-#define __INTEL_GT_GMCH_H__
-
-#include "intel_gtt.h"
-
-/* For x86 platforms */
-#if IS_ENABLED(CONFIG_X86)
-void intel_gt_gmch_gen5_chipset_flush(struct intel_gt *gt);
-int intel_gt_gmch_gen6_probe(struct i915_ggtt *ggtt);
-int intel_gt_gmch_gen8_probe(struct i915_ggtt *ggtt);
-int intel_gt_gmch_gen5_probe(struct i915_ggtt *ggtt);
-int intel_gt_gmch_gen5_enable_hw(struct drm_i915_private *i915);
-
-/* Stubs for non-x86 platforms */
-#else
-static inline void intel_gt_gmch_gen5_chipset_flush(struct intel_gt *gt)
-{
-}
-static inline int intel_gt_gmch_gen5_probe(struct i915_ggtt *ggtt)
-{
-	/* No HW should be probed for this case yet, return fail */
-	return -ENODEV;
-}
-static inline int intel_gt_gmch_gen6_probe(struct i915_ggtt *ggtt)
-{
-	/* No HW should be probed for this case yet, return fail */
-	return -ENODEV;
-}
-static inline int intel_gt_gmch_gen8_probe(struct i915_ggtt *ggtt)
-{
-	/* No HW should be probed for this case yet, return fail */
-	return -ENODEV;
-}
-static inline int intel_gt_gmch_gen5_enable_hw(struct drm_i915_private *i915)
-{
-	/* No HW should be enabled for this case yet, return fail */
-	return -ENODEV;
-}
-#endif
-
-#endif /* __INTEL_GT_GMCH_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 128b31476938f..29fd3a9e8b2e8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -561,14 +561,13 @@ i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n)
 
 void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
 		unsigned long lmem_pt_obj_flags);
-
 void intel_ggtt_bind_vma(struct i915_address_space *vm,
-			  struct i915_vm_pt_stash *stash,
-			  struct i915_vma_resource *vma_res,
-			  enum i915_cache_level cache_level,
-			  u32 flags);
+			 struct i915_vm_pt_stash *stash,
+			 struct i915_vma_resource *vma_res,
+			 enum i915_cache_level cache_level,
+			 u32 flags);
 void intel_ggtt_unbind_vma(struct i915_address_space *vm,
-			    struct i915_vma_resource *vma_res);
+			   struct i915_vma_resource *vma_res);
 
 int i915_ggtt_probe_hw(struct drm_i915_private *i915);
 int i915_ggtt_init_hw(struct drm_i915_private *i915);
@@ -651,7 +650,6 @@ release_pd_entry(struct i915_page_directory * const pd,
 		 struct i915_page_table * const pt,
 		 const struct drm_i915_gem_object * const scratch);
 void gen6_ggtt_invalidate(struct i915_ggtt *ggtt);
-void gen8_ggtt_invalidate(struct i915_ggtt *ggtt);
 
 void ppgtt_bind_vma(struct i915_address_space *vm,
 		    struct i915_vm_pt_stash *stash,
-- 
GitLab


From 13f28c2cf0701eaf3b251a57b46bca0fe17248ca Mon Sep 17 00:00:00 2001
From: Vadim Fedorenko <vadfed@fb.com>
Date: Wed, 22 Jun 2022 02:31:31 +0300
Subject: [PATCH 1029/1731] MAINTAINERS: Add a maintainer for OCP Time Card

I've been contributing and reviewing patches for ptp_ocp driver for
some time and I'm taking care of it's github mirror. On Jakub's
suggestion, I would like to step forward and become a maintainer for
this driver. This patch adds a dedicated entry to MAINTAINERS.

Signed-off-by: Vadim Fedorenko <vadfed@fb.com>
Acked-by: Jonathan Lemon <jonathan.lemon@gmail.com>
Link: https://lore.kernel.org/r/20220621233131.21240-1-vfedorenko@novek.ru
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 15a2341936ea5..d922601f02ae5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14868,6 +14868,7 @@ F:	include/dt-bindings/
 
 OPENCOMPUTE PTP CLOCK DRIVER
 M:	Jonathan Lemon <jonathan.lemon@gmail.com>
+M:	Vadim Fedorenko <vadfed@fb.com>
 L:	netdev@vger.kernel.org
 S:	Maintained
 F:	drivers/ptp/ptp_ocp.c
-- 
GitLab


From 9de74996a739bf0b7b5d8c260bd207ad6007442b Mon Sep 17 00:00:00 2001
From: Shyam Prasad N <sprasad@microsoft.com>
Date: Wed, 22 Jun 2022 12:36:36 -0500
Subject: [PATCH 1030/1731] smb3: use netname when available on secondary
 channels

Some servers do not allow null netname contexts, which would cause
multichannel to revert to single channel when mounting to some
servers (e.g. Azure xSMB). The previous patch fixed that by avoiding
incorrectly sending the netname context when there would be a null
hostname sent in the netname context, while this patch fixes the null
hostname for the secondary channel by using the hostname of the
primary channel for the secondary channel.

Fixes: 4c14d7043fede ("cifs: populate empty hostnames for extra channels")
Signed-off-by: Shyam Prasad N <sprasad@microsoft.com>
Reviewed-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/smb2pdu.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/fs/cifs/smb2pdu.c b/fs/cifs/smb2pdu.c
index 5e8c4737b183a..12b4dddaedb02 100644
--- a/fs/cifs/smb2pdu.c
+++ b/fs/cifs/smb2pdu.c
@@ -543,6 +543,7 @@ assemble_neg_contexts(struct smb2_negotiate_req *req,
 		      struct TCP_Server_Info *server, unsigned int *total_len)
 {
 	char *pneg_ctxt;
+	char *hostname = NULL;
 	unsigned int ctxt_len, neg_context_count;
 
 	if (*total_len > 200) {
@@ -574,9 +575,15 @@ assemble_neg_contexts(struct smb2_negotiate_req *req,
 	*total_len += sizeof(struct smb2_posix_neg_context);
 	pneg_ctxt += sizeof(struct smb2_posix_neg_context);
 
-	if (server->hostname && (server->hostname[0] != 0)) {
+	/*
+	 * secondary channels don't have the hostname field populated
+	 * use the hostname field in the primary channel instead
+	 */
+	hostname = CIFS_SERVER_IS_CHAN(server) ?
+		server->primary_server->hostname : server->hostname;
+	if (hostname && (hostname[0] != 0)) {
 		ctxt_len = build_netname_ctxt((struct smb2_netname_neg_context *)pneg_ctxt,
-					server->hostname);
+					      hostname);
 		*total_len += ctxt_len;
 		pneg_ctxt += ctxt_len;
 		neg_context_count = 4;
-- 
GitLab


From aa45dadd34e44fcd6a9df4b395bee5b5633b4cec Mon Sep 17 00:00:00 2001
From: Shyam Prasad N <sprasad@microsoft.com>
Date: Sat, 1 Jan 2022 12:50:21 +0000
Subject: [PATCH 1031/1731] cifs: change iface_list from array to sorted linked
 list

A server's published interface list can change over time, and needs
to be updated. We've storing iface_list as a simple array, which
makes it difficult to manipulate an existing list.

With this change, iface_list is modified into a linked list of
interfaces, which is kept sorted by speed.

Also added a reference counter for an iface entry, so that each
channel can maintain a backpointer to the iface and drop it
easily when needed.

Signed-off-by: Shyam Prasad N <sprasad@microsoft.com>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/cifs_debug.c |  12 +--
 fs/cifs/cifsglob.h   |  54 +++++++++++++-
 fs/cifs/connect.c    |   6 +-
 fs/cifs/misc.c       |   9 ++-
 fs/cifs/sess.c       |  78 ++++++++++----------
 fs/cifs/smb2ops.c    | 171 ++++++++++++++++++++++---------------------
 6 files changed, 201 insertions(+), 129 deletions(-)

diff --git a/fs/cifs/cifs_debug.c b/fs/cifs/cifs_debug.c
index 1dd995efd5b86..2cfbac8bb9650 100644
--- a/fs/cifs/cifs_debug.c
+++ b/fs/cifs/cifs_debug.c
@@ -162,6 +162,8 @@ cifs_dump_iface(struct seq_file *m, struct cifs_server_iface *iface)
 		seq_printf(m, "\t\tIPv4: %pI4\n", &ipv4->sin_addr);
 	else if (iface->sockaddr.ss_family == AF_INET6)
 		seq_printf(m, "\t\tIPv6: %pI6\n", &ipv6->sin6_addr);
+	if (!iface->is_active)
+		seq_puts(m, "\t\t[for-cleanup]\n");
 }
 
 static int cifs_debug_files_proc_show(struct seq_file *m, void *v)
@@ -221,6 +223,7 @@ static int cifs_debug_data_proc_show(struct seq_file *m, void *v)
 	struct TCP_Server_Info *server;
 	struct cifs_ses *ses;
 	struct cifs_tcon *tcon;
+	struct cifs_server_iface *iface;
 	int c, i, j;
 
 	seq_puts(m,
@@ -456,11 +459,10 @@ skip_rdma:
 			if (ses->iface_count)
 				seq_printf(m, "\n\n\tServer interfaces: %zu",
 					   ses->iface_count);
-			for (j = 0; j < ses->iface_count; j++) {
-				struct cifs_server_iface *iface;
-
-				iface = &ses->iface_list[j];
-				seq_printf(m, "\n\t%d)", j+1);
+			j = 0;
+			list_for_each_entry(iface, &ses->iface_list,
+						 iface_head) {
+				seq_printf(m, "\n\t%d)", ++j);
 				cifs_dump_iface(m, iface);
 				if (is_ses_using_iface(ses, iface))
 					seq_puts(m, "\t\t[CONNECTED]\n");
diff --git a/fs/cifs/cifsglob.h b/fs/cifs/cifsglob.h
index e7737166e5b86..7fc2addc95a3e 100644
--- a/fs/cifs/cifsglob.h
+++ b/fs/cifs/cifsglob.h
@@ -933,15 +933,67 @@ static inline void cifs_set_net_ns(struct TCP_Server_Info *srv, struct net *net)
 #endif
 
 struct cifs_server_iface {
+	struct list_head iface_head;
+	struct kref refcount;
 	size_t speed;
 	unsigned int rdma_capable : 1;
 	unsigned int rss_capable : 1;
+	unsigned int is_active : 1; /* unset if non existent */
 	struct sockaddr_storage sockaddr;
 };
 
+/* release iface when last ref is dropped */
+static inline void
+release_iface(struct kref *ref)
+{
+	struct cifs_server_iface *iface = container_of(ref,
+						       struct cifs_server_iface,
+						       refcount);
+	list_del_init(&iface->iface_head);
+	kfree(iface);
+}
+
+/*
+ * compare two interfaces a and b
+ * return 0 if everything matches.
+ * return 1 if a has higher link speed, or rdma capable, or rss capable
+ * return -1 otherwise.
+ */
+static inline int
+iface_cmp(struct cifs_server_iface *a, struct cifs_server_iface *b)
+{
+	int cmp_ret = 0;
+
+	WARN_ON(!a || !b);
+	if (a->speed == b->speed) {
+		if (a->rdma_capable == b->rdma_capable) {
+			if (a->rss_capable == b->rss_capable) {
+				cmp_ret = memcmp(&a->sockaddr, &b->sockaddr,
+						 sizeof(a->sockaddr));
+				if (!cmp_ret)
+					return 0;
+				else if (cmp_ret > 0)
+					return 1;
+				else
+					return -1;
+			} else if (a->rss_capable > b->rss_capable)
+				return 1;
+			else
+				return -1;
+		} else if (a->rdma_capable > b->rdma_capable)
+			return 1;
+		else
+			return -1;
+	} else if (a->speed > b->speed)
+		return 1;
+	else
+		return -1;
+}
+
 struct cifs_chan {
 	unsigned int in_reconnect : 1; /* if session setup in progress for this channel */
 	struct TCP_Server_Info *server;
+	struct cifs_server_iface *iface; /* interface in use */
 	__u8 signkey[SMB3_SIGN_KEY_SIZE];
 };
 
@@ -993,7 +1045,7 @@ struct cifs_ses {
 	 */
 	spinlock_t iface_lock;
 	/* ========= begin: protected by iface_lock ======== */
-	struct cifs_server_iface *iface_list;
+	struct list_head iface_list;
 	size_t iface_count;
 	unsigned long iface_last_update; /* jiffies */
 	/* ========= end: protected by iface_lock ======== */
diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
index 1849e34114878..248fe1805c172 100644
--- a/fs/cifs/connect.c
+++ b/fs/cifs/connect.c
@@ -1894,9 +1894,11 @@ void cifs_put_smb_ses(struct cifs_ses *ses)
 		int i;
 
 		for (i = 1; i < chan_count; i++) {
-			spin_unlock(&ses->chan_lock);
+			if (ses->chans[i].iface) {
+				kref_put(&ses->chans[i].iface->refcount, release_iface);
+				ses->chans[i].iface = NULL;
+			}
 			cifs_put_tcp_session(ses->chans[i].server, 0);
-			spin_lock(&ses->chan_lock);
 			ses->chans[i].server = NULL;
 		}
 	}
diff --git a/fs/cifs/misc.c b/fs/cifs/misc.c
index c69e1240d730b..0e84e6fcf8ab4 100644
--- a/fs/cifs/misc.c
+++ b/fs/cifs/misc.c
@@ -75,6 +75,7 @@ sesInfoAlloc(void)
 		INIT_LIST_HEAD(&ret_buf->tcon_list);
 		mutex_init(&ret_buf->session_mutex);
 		spin_lock_init(&ret_buf->iface_lock);
+		INIT_LIST_HEAD(&ret_buf->iface_list);
 		spin_lock_init(&ret_buf->chan_lock);
 	}
 	return ret_buf;
@@ -83,6 +84,8 @@ sesInfoAlloc(void)
 void
 sesInfoFree(struct cifs_ses *buf_to_free)
 {
+	struct cifs_server_iface *iface = NULL, *niface = NULL;
+
 	if (buf_to_free == NULL) {
 		cifs_dbg(FYI, "Null buffer passed to sesInfoFree\n");
 		return;
@@ -96,7 +99,11 @@ sesInfoFree(struct cifs_ses *buf_to_free)
 	kfree(buf_to_free->user_name);
 	kfree(buf_to_free->domainName);
 	kfree_sensitive(buf_to_free->auth_key.response);
-	kfree(buf_to_free->iface_list);
+	spin_lock(&buf_to_free->iface_lock);
+	list_for_each_entry_safe(iface, niface, &buf_to_free->iface_list,
+				 iface_head)
+		kref_put(&iface->refcount, release_iface);
+	spin_unlock(&buf_to_free->iface_lock);
 	kfree_sensitive(buf_to_free);
 }
 
diff --git a/fs/cifs/sess.c b/fs/cifs/sess.c
index d417de354d9d7..d7b6e5687df28 100644
--- a/fs/cifs/sess.c
+++ b/fs/cifs/sess.c
@@ -58,7 +58,7 @@ bool is_ses_using_iface(struct cifs_ses *ses, struct cifs_server_iface *iface)
 
 	spin_lock(&ses->chan_lock);
 	for (i = 0; i < ses->chan_count; i++) {
-		if (is_server_using_iface(ses->chans[i].server, iface)) {
+		if (ses->chans[i].iface == iface) {
 			spin_unlock(&ses->chan_lock);
 			return true;
 		}
@@ -151,11 +151,9 @@ int cifs_try_adding_channels(struct cifs_sb_info *cifs_sb, struct cifs_ses *ses)
 {
 	int old_chan_count, new_chan_count;
 	int left;
-	int i = 0;
 	int rc = 0;
 	int tries = 0;
-	struct cifs_server_iface *ifaces = NULL;
-	size_t iface_count;
+	struct cifs_server_iface *iface = NULL, *niface = NULL;
 
 	spin_lock(&ses->chan_lock);
 
@@ -184,33 +182,17 @@ int cifs_try_adding_channels(struct cifs_sb_info *cifs_sb, struct cifs_ses *ses)
 	}
 	spin_unlock(&ses->chan_lock);
 
-	/*
-	 * Make a copy of the iface list at the time and use that
-	 * instead so as to not hold the iface spinlock for opening
-	 * channels
-	 */
-	spin_lock(&ses->iface_lock);
-	iface_count = ses->iface_count;
-	if (iface_count <= 0) {
-		spin_unlock(&ses->iface_lock);
-		cifs_dbg(VFS, "no iface list available to open channels\n");
-		return 0;
-	}
-	ifaces = kmemdup(ses->iface_list, iface_count*sizeof(*ifaces),
-			 GFP_ATOMIC);
-	if (!ifaces) {
-		spin_unlock(&ses->iface_lock);
-		return 0;
-	}
-	spin_unlock(&ses->iface_lock);
-
 	/*
 	 * Keep connecting to same, fastest, iface for all channels as
 	 * long as its RSS. Try next fastest one if not RSS or channel
 	 * creation fails.
 	 */
+	spin_lock(&ses->iface_lock);
+	iface = list_first_entry(&ses->iface_list, struct cifs_server_iface,
+				 iface_head);
+	spin_unlock(&ses->iface_lock);
+
 	while (left > 0) {
-		struct cifs_server_iface *iface;
 
 		tries++;
 		if (tries > 3*ses->chan_max) {
@@ -219,27 +201,46 @@ int cifs_try_adding_channels(struct cifs_sb_info *cifs_sb, struct cifs_ses *ses)
 			break;
 		}
 
-		iface = &ifaces[i];
-		if (is_ses_using_iface(ses, iface) && !iface->rss_capable) {
-			i = (i+1) % iface_count;
-			continue;
+		spin_lock(&ses->iface_lock);
+		if (!ses->iface_count) {
+			spin_unlock(&ses->iface_lock);
+			break;
 		}
 
-		rc = cifs_ses_add_channel(cifs_sb, ses, iface);
-		if (rc) {
-			cifs_dbg(FYI, "failed to open extra channel on iface#%d rc=%d\n",
-				 i, rc);
-			i = (i+1) % iface_count;
-			continue;
+		list_for_each_entry_safe_from(iface, niface, &ses->iface_list,
+				    iface_head) {
+			/* skip ifaces that are unusable */
+			if (!iface->is_active ||
+			    (is_ses_using_iface(ses, iface) &&
+			     !iface->rss_capable)) {
+				continue;
+			}
+
+			/* take ref before unlock */
+			kref_get(&iface->refcount);
+
+			spin_unlock(&ses->iface_lock);
+			rc = cifs_ses_add_channel(cifs_sb, ses, iface);
+			spin_lock(&ses->iface_lock);
+
+			if (rc) {
+				cifs_dbg(VFS, "failed to open extra channel on iface:%pIS rc=%d\n",
+					 &iface->sockaddr,
+					 rc);
+				kref_put(&iface->refcount, release_iface);
+				continue;
+			}
+
+			cifs_dbg(FYI, "successfully opened new channel on iface:%pIS\n",
+				 &iface->sockaddr);
+			break;
 		}
+		spin_unlock(&ses->iface_lock);
 
-		cifs_dbg(FYI, "successfully opened new channel on iface#%d\n",
-			 i);
 		left--;
 		new_chan_count++;
 	}
 
-	kfree(ifaces);
 	return new_chan_count - old_chan_count;
 }
 
@@ -355,6 +356,7 @@ cifs_ses_add_channel(struct cifs_sb_info *cifs_sb, struct cifs_ses *ses,
 		spin_unlock(&ses->chan_lock);
 		goto out;
 	}
+	chan->iface = iface;
 	ses->chan_count++;
 	atomic_set(&ses->chan_seq, 0);
 
diff --git a/fs/cifs/smb2ops.c b/fs/cifs/smb2ops.c
index 8543cafdfd341..db4ccf1d235e9 100644
--- a/fs/cifs/smb2ops.c
+++ b/fs/cifs/smb2ops.c
@@ -512,73 +512,41 @@ smb3_negotiate_rsize(struct cifs_tcon *tcon, struct smb3_fs_context *ctx)
 static int
 parse_server_interfaces(struct network_interface_info_ioctl_rsp *buf,
 			size_t buf_len,
-			struct cifs_server_iface **iface_list,
-			size_t *iface_count)
+			struct cifs_ses *ses)
 {
 	struct network_interface_info_ioctl_rsp *p;
 	struct sockaddr_in *addr4;
 	struct sockaddr_in6 *addr6;
 	struct iface_info_ipv4 *p4;
 	struct iface_info_ipv6 *p6;
-	struct cifs_server_iface *info;
+	struct cifs_server_iface *info = NULL, *iface = NULL, *niface = NULL;
+	struct cifs_server_iface tmp_iface;
 	ssize_t bytes_left;
 	size_t next = 0;
 	int nb_iface = 0;
-	int rc = 0;
-
-	*iface_list = NULL;
-	*iface_count = 0;
-
-	/*
-	 * Fist pass: count and sanity check
-	 */
+	int rc = 0, ret = 0;
 
 	bytes_left = buf_len;
 	p = buf;
-	while (bytes_left >= sizeof(*p)) {
-		nb_iface++;
-		next = le32_to_cpu(p->Next);
-		if (!next) {
-			bytes_left -= sizeof(*p);
-			break;
-		}
-		p = (struct network_interface_info_ioctl_rsp *)((u8 *)p+next);
-		bytes_left -= next;
-	}
-
-	if (!nb_iface) {
-		cifs_dbg(VFS, "%s: malformed interface info\n", __func__);
-		rc = -EINVAL;
-		goto out;
-	}
-
-	/* Azure rounds the buffer size up 8, to a 16 byte boundary */
-	if ((bytes_left > 8) || p->Next)
-		cifs_dbg(VFS, "%s: incomplete interface info\n", __func__);
-
 
+	spin_lock(&ses->iface_lock);
 	/*
-	 * Second pass: extract info to internal structure
+	 * Go through iface_list and do kref_put to remove
+	 * any unused ifaces. ifaces in use will be removed
+	 * when the last user calls a kref_put on it
 	 */
-
-	*iface_list = kcalloc(nb_iface, sizeof(**iface_list), GFP_KERNEL);
-	if (!*iface_list) {
-		rc = -ENOMEM;
-		goto out;
+	list_for_each_entry_safe(iface, niface, &ses->iface_list,
+				 iface_head) {
+		iface->is_active = 0;
+		kref_put(&iface->refcount, release_iface);
 	}
+	spin_unlock(&ses->iface_lock);
 
-	info = *iface_list;
-	bytes_left = buf_len;
-	p = buf;
 	while (bytes_left >= sizeof(*p)) {
-		info->speed = le64_to_cpu(p->LinkSpeed);
-		info->rdma_capable = le32_to_cpu(p->Capability & RDMA_CAPABLE) ? 1 : 0;
-		info->rss_capable = le32_to_cpu(p->Capability & RSS_CAPABLE) ? 1 : 0;
-
-		cifs_dbg(FYI, "%s: adding iface %zu\n", __func__, *iface_count);
-		cifs_dbg(FYI, "%s: speed %zu bps\n", __func__, info->speed);
-		cifs_dbg(FYI, "%s: capabilities 0x%08x\n", __func__,
-			 le32_to_cpu(p->Capability));
+		memset(&tmp_iface, 0, sizeof(tmp_iface));
+		tmp_iface.speed = le64_to_cpu(p->LinkSpeed);
+		tmp_iface.rdma_capable = le32_to_cpu(p->Capability & RDMA_CAPABLE) ? 1 : 0;
+		tmp_iface.rss_capable = le32_to_cpu(p->Capability & RSS_CAPABLE) ? 1 : 0;
 
 		switch (p->Family) {
 		/*
@@ -587,7 +555,7 @@ parse_server_interfaces(struct network_interface_info_ioctl_rsp *buf,
 		 * conversion explicit in case either one changes.
 		 */
 		case INTERNETWORK:
-			addr4 = (struct sockaddr_in *)&info->sockaddr;
+			addr4 = (struct sockaddr_in *)&tmp_iface.sockaddr;
 			p4 = (struct iface_info_ipv4 *)p->Buffer;
 			addr4->sin_family = AF_INET;
 			memcpy(&addr4->sin_addr, &p4->IPv4Address, 4);
@@ -599,7 +567,7 @@ parse_server_interfaces(struct network_interface_info_ioctl_rsp *buf,
 				 &addr4->sin_addr);
 			break;
 		case INTERNETWORKV6:
-			addr6 =	(struct sockaddr_in6 *)&info->sockaddr;
+			addr6 =	(struct sockaddr_in6 *)&tmp_iface.sockaddr;
 			p6 = (struct iface_info_ipv6 *)p->Buffer;
 			addr6->sin6_family = AF_INET6;
 			memcpy(&addr6->sin6_addr, &p6->IPv6Address, 16);
@@ -619,36 +587,88 @@ parse_server_interfaces(struct network_interface_info_ioctl_rsp *buf,
 			goto next_iface;
 		}
 
-		(*iface_count)++;
-		info++;
+		/*
+		 * The iface_list is assumed to be sorted by speed.
+		 * Check if the new interface exists in that list.
+		 * NEVER change iface. it could be in use.
+		 * Add a new one instead
+		 */
+		spin_lock(&ses->iface_lock);
+		iface = niface = NULL;
+		list_for_each_entry_safe(iface, niface, &ses->iface_list,
+					 iface_head) {
+			ret = iface_cmp(iface, &tmp_iface);
+			if (!ret) {
+				/* just get a ref so that it doesn't get picked/freed */
+				iface->is_active = 1;
+				kref_get(&iface->refcount);
+				spin_unlock(&ses->iface_lock);
+				goto next_iface;
+			} else if (ret < 0) {
+				/* all remaining ifaces are slower */
+				kref_get(&iface->refcount);
+				break;
+			}
+		}
+		spin_unlock(&ses->iface_lock);
+
+		/* no match. insert the entry in the list */
+		info = kmalloc(sizeof(struct cifs_server_iface),
+			       GFP_KERNEL);
+		if (!info) {
+			rc = -ENOMEM;
+			goto out;
+		}
+		memcpy(info, &tmp_iface, sizeof(tmp_iface));
+
+		/* add this new entry to the list */
+		kref_init(&info->refcount);
+		info->is_active = 1;
+
+		cifs_dbg(FYI, "%s: adding iface %zu\n", __func__, ses->iface_count);
+		cifs_dbg(FYI, "%s: speed %zu bps\n", __func__, info->speed);
+		cifs_dbg(FYI, "%s: capabilities 0x%08x\n", __func__,
+			 le32_to_cpu(p->Capability));
+
+		spin_lock(&ses->iface_lock);
+		if (!list_entry_is_head(iface, &ses->iface_list, iface_head)) {
+			list_add_tail(&info->iface_head, &iface->iface_head);
+			kref_put(&iface->refcount, release_iface);
+		} else
+			list_add_tail(&info->iface_head, &ses->iface_list);
+		spin_unlock(&ses->iface_lock);
+
+		ses->iface_count++;
+		ses->iface_last_update = jiffies;
 next_iface:
+		nb_iface++;
 		next = le32_to_cpu(p->Next);
-		if (!next)
+		if (!next) {
+			bytes_left -= sizeof(*p);
 			break;
+		}
 		p = (struct network_interface_info_ioctl_rsp *)((u8 *)p+next);
 		bytes_left -= next;
 	}
 
-	if (!*iface_count) {
+	if (!nb_iface) {
+		cifs_dbg(VFS, "%s: malformed interface info\n", __func__);
 		rc = -EINVAL;
 		goto out;
 	}
 
-out:
-	if (rc) {
-		kfree(*iface_list);
-		*iface_count = 0;
-		*iface_list = NULL;
-	}
-	return rc;
-}
+	/* Azure rounds the buffer size up 8, to a 16 byte boundary */
+	if ((bytes_left > 8) || p->Next)
+		cifs_dbg(VFS, "%s: incomplete interface info\n", __func__);
 
-static int compare_iface(const void *ia, const void *ib)
-{
-	const struct cifs_server_iface *a = (struct cifs_server_iface *)ia;
-	const struct cifs_server_iface *b = (struct cifs_server_iface *)ib;
 
-	return a->speed == b->speed ? 0 : (a->speed > b->speed ? -1 : 1);
+	if (!ses->iface_count) {
+		rc = -EINVAL;
+		goto out;
+	}
+
+out:
+	return rc;
 }
 
 static int
@@ -657,8 +677,6 @@ SMB3_request_interfaces(const unsigned int xid, struct cifs_tcon *tcon)
 	int rc;
 	unsigned int ret_data_len = 0;
 	struct network_interface_info_ioctl_rsp *out_buf = NULL;
-	struct cifs_server_iface *iface_list;
-	size_t iface_count;
 	struct cifs_ses *ses = tcon->ses;
 
 	rc = SMB2_ioctl(xid, tcon, NO_FILE_ID, NO_FILE_ID,
@@ -674,21 +692,10 @@ SMB3_request_interfaces(const unsigned int xid, struct cifs_tcon *tcon)
 		goto out;
 	}
 
-	rc = parse_server_interfaces(out_buf, ret_data_len,
-				     &iface_list, &iface_count);
+	rc = parse_server_interfaces(out_buf, ret_data_len, ses);
 	if (rc)
 		goto out;
 
-	/* sort interfaces from fastest to slowest */
-	sort(iface_list, iface_count, sizeof(*iface_list), compare_iface, NULL);
-
-	spin_lock(&ses->iface_lock);
-	kfree(ses->iface_list);
-	ses->iface_list = iface_list;
-	ses->iface_count = iface_count;
-	ses->iface_last_update = jiffies;
-	spin_unlock(&ses->iface_lock);
-
 out:
 	kfree(out_buf);
 	return rc;
-- 
GitLab


From b54034a73baf9fe31fb3f218c17bd5308a27a1ca Mon Sep 17 00:00:00 2001
From: Shyam Prasad N <sprasad@microsoft.com>
Date: Mon, 3 Jan 2022 08:47:30 +0000
Subject: [PATCH 1032/1731] cifs: during reconnect, update interface if
 necessary

Going forward, the plan is to periodically query the server
for it's interfaces (when multichannel is enabled).

This change allows checking for inactive interfaces during
reconnect, and reconnect to a new interface if necessary.

Signed-off-by: Shyam Prasad N <sprasad@microsoft.com>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/cifsproto.h |  5 +++
 fs/cifs/connect.c   |  4 +++
 fs/cifs/sess.c      | 79 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 88 insertions(+)

diff --git a/fs/cifs/cifsproto.h b/fs/cifs/cifsproto.h
index 3b7366ec03c76..00c4a8aa26497 100644
--- a/fs/cifs/cifsproto.h
+++ b/fs/cifs/cifsproto.h
@@ -636,6 +636,11 @@ cifs_chan_clear_need_reconnect(struct cifs_ses *ses,
 bool
 cifs_chan_needs_reconnect(struct cifs_ses *ses,
 			  struct TCP_Server_Info *server);
+bool
+cifs_chan_is_iface_active(struct cifs_ses *ses,
+			  struct TCP_Server_Info *server);
+int
+cifs_chan_update_iface(struct cifs_ses *ses, struct TCP_Server_Info *server);
 
 void extract_unc_hostname(const char *unc, const char **h, size_t *len);
 int copy_path_name(char *dst, const char *src);
diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
index 248fe1805c172..d8aae257649fa 100644
--- a/fs/cifs/connect.c
+++ b/fs/cifs/connect.c
@@ -232,6 +232,10 @@ cifs_mark_tcp_ses_conns_for_reconnect(struct TCP_Server_Info *server,
 
 	spin_lock(&cifs_tcp_ses_lock);
 	list_for_each_entry(ses, &pserver->smb_ses_list, smb_ses_list) {
+		/* check if iface is still active */
+		if (!cifs_chan_is_iface_active(ses, server))
+			cifs_chan_update_iface(ses, server);
+
 		spin_lock(&ses->chan_lock);
 		if (!mark_smb_session && cifs_chan_needs_reconnect(ses, server))
 			goto next_session;
diff --git a/fs/cifs/sess.c b/fs/cifs/sess.c
index d7b6e5687df28..7c26ee70c8b01 100644
--- a/fs/cifs/sess.c
+++ b/fs/cifs/sess.c
@@ -146,6 +146,16 @@ cifs_chan_needs_reconnect(struct cifs_ses *ses,
 	return CIFS_CHAN_NEEDS_RECONNECT(ses, chan_index);
 }
 
+bool
+cifs_chan_is_iface_active(struct cifs_ses *ses,
+			  struct TCP_Server_Info *server)
+{
+	unsigned int chan_index = cifs_ses_get_chan_index(ses, server);
+
+	return ses->chans[chan_index].iface &&
+		ses->chans[chan_index].iface->is_active;
+}
+
 /* returns number of channels added */
 int cifs_try_adding_channels(struct cifs_sb_info *cifs_sb, struct cifs_ses *ses)
 {
@@ -244,6 +254,75 @@ int cifs_try_adding_channels(struct cifs_sb_info *cifs_sb, struct cifs_ses *ses)
 	return new_chan_count - old_chan_count;
 }
 
+/*
+ * update the iface for the channel if necessary.
+ * will return 0 when iface is updated. 1 otherwise
+ * Must be called with chan_lock held.
+ */
+int
+cifs_chan_update_iface(struct cifs_ses *ses, struct TCP_Server_Info *server)
+{
+	unsigned int chan_index = cifs_ses_get_chan_index(ses, server);
+	struct cifs_server_iface *iface = NULL;
+	struct cifs_server_iface *old_iface = NULL;
+	int rc = 0;
+
+	/* primary channel. This can never go away */
+	if (!chan_index)
+		return 0;
+
+	if (ses->chans[chan_index].iface) {
+		old_iface = ses->chans[chan_index].iface;
+		if (old_iface->is_active)
+			return 1;
+	}
+
+	spin_lock(&ses->iface_lock);
+
+	/* then look for a new one */
+	list_for_each_entry(iface, &ses->iface_list, iface_head) {
+		if (!iface->is_active ||
+		    (is_ses_using_iface(ses, iface) &&
+		     !iface->rss_capable)) {
+			continue;
+		}
+		kref_get(&iface->refcount);
+	}
+
+	if (!list_entry_is_head(iface, &ses->iface_list, iface_head)) {
+		rc = 1;
+		iface = NULL;
+		cifs_dbg(FYI, "unable to find a suitable iface\n");
+	}
+
+	ses->chans[chan_index].iface = iface;
+
+	/* now drop the ref to the current iface */
+	if (old_iface && iface) {
+		kref_put(&old_iface->refcount, release_iface);
+		cifs_dbg(FYI, "replacing iface: %pIS with %pIS\n",
+			 &old_iface->sockaddr,
+			 &iface->sockaddr);
+	} else if (old_iface) {
+		kref_put(&old_iface->refcount, release_iface);
+		cifs_dbg(FYI, "releasing ref to iface: %pIS\n",
+			 &old_iface->sockaddr);
+	} else {
+		WARN_ON(!iface);
+		cifs_dbg(FYI, "adding new iface: %pIS\n", &iface->sockaddr);
+	}
+
+	spin_unlock(&ses->iface_lock);
+
+	/* No iface is found. if secondary chan, drop connection */
+	if (!iface && CIFS_SERVER_IS_CHAN(server)) {
+		cifs_put_tcp_session(server, false);
+		ses->chans[chan_index].server = NULL;
+	}
+
+	return rc;
+}
+
 /*
  * If server is a channel of ses, return the corresponding enclosing
  * cifs_chan otherwise return NULL.
-- 
GitLab


From 6e1c1c08cdf3d7d7b8c571c0f032a283af6ca024 Mon Sep 17 00:00:00 2001
From: Shyam Prasad N <sprasad@microsoft.com>
Date: Mon, 6 Jun 2022 09:17:56 +0000
Subject: [PATCH 1033/1731] cifs: periodically query network interfaces from
 server

Currently, we only query the server for network interfaces
information at the time of mount, and never afterwards.
This can be a problem, especially for services like Azure,
where the IP address of the channel endpoints can change
over time.

With this change, we schedule a 600s polling of this info
from the server for each tree connect.

An alternative for periodic polling was to do this only at
the time of reconnect. But this could delay the reconnect
time slightly. Also, there are some challenges w.r.t how
we have cifs_reconnect implemented today.

Signed-off-by: Shyam Prasad N <sprasad@microsoft.com>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/cifsglob.h  |  4 ++++
 fs/cifs/cifsproto.h |  2 ++
 fs/cifs/connect.c   | 28 ++++++++++++++++++++++++++++
 fs/cifs/smb2ops.c   |  2 +-
 4 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/fs/cifs/cifsglob.h b/fs/cifs/cifsglob.h
index 7fc2addc95a3e..a643c84ff1e93 100644
--- a/fs/cifs/cifsglob.h
+++ b/fs/cifs/cifsglob.h
@@ -80,6 +80,9 @@
 #define SMB_DNS_RESOLVE_INTERVAL_MIN     120
 #define SMB_DNS_RESOLVE_INTERVAL_DEFAULT 600
 
+/* smb multichannel query server interfaces interval in seconds */
+#define SMB_INTERFACE_POLL_INTERVAL	600
+
 /* maximum number of PDUs in one compound */
 #define MAX_COMPOUND 5
 
@@ -1255,6 +1258,7 @@ struct cifs_tcon {
 #ifdef CONFIG_CIFS_DFS_UPCALL
 	struct list_head ulist; /* cache update list */
 #endif
+	struct delayed_work	query_interfaces; /* query interfaces workqueue job */
 };
 
 /*
diff --git a/fs/cifs/cifsproto.h b/fs/cifs/cifsproto.h
index 00c4a8aa26497..d59aebefa71cd 100644
--- a/fs/cifs/cifsproto.h
+++ b/fs/cifs/cifsproto.h
@@ -641,6 +641,8 @@ cifs_chan_is_iface_active(struct cifs_ses *ses,
 			  struct TCP_Server_Info *server);
 int
 cifs_chan_update_iface(struct cifs_ses *ses, struct TCP_Server_Info *server);
+int
+SMB3_request_interfaces(const unsigned int xid, struct cifs_tcon *tcon);
 
 void extract_unc_hostname(const char *unc, const char **h, size_t *len);
 int copy_path_name(char *dst, const char *src);
diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
index d8aae257649fa..e666d2643edeb 100644
--- a/fs/cifs/connect.c
+++ b/fs/cifs/connect.c
@@ -145,6 +145,25 @@ requeue_resolve:
 	return rc;
 }
 
+static void smb2_query_server_interfaces(struct work_struct *work)
+{
+	int rc;
+	struct cifs_tcon *tcon = container_of(work,
+					struct cifs_tcon,
+					query_interfaces.work);
+
+	/*
+	 * query server network interfaces, in case they change
+	 */
+	rc = SMB3_request_interfaces(0, tcon);
+	if (rc) {
+		cifs_dbg(FYI, "%s: failed to query server interfaces: %d\n",
+				__func__, rc);
+	}
+
+	queue_delayed_work(cifsiod_wq, &tcon->query_interfaces,
+			   (SMB_INTERFACE_POLL_INTERVAL * HZ));
+}
 
 static void cifs_resolve_server(struct work_struct *work)
 {
@@ -2276,6 +2295,9 @@ cifs_put_tcon(struct cifs_tcon *tcon)
 	list_del_init(&tcon->tcon_list);
 	spin_unlock(&cifs_tcp_ses_lock);
 
+	/* cancel polling of interfaces */
+	cancel_delayed_work_sync(&tcon->query_interfaces);
+
 	if (tcon->use_witness) {
 		int rc;
 
@@ -2513,6 +2535,12 @@ cifs_get_tcon(struct cifs_ses *ses, struct smb3_fs_context *ctx)
 	tcon->local_lease = ctx->local_lease;
 	INIT_LIST_HEAD(&tcon->pending_opens);
 
+	/* schedule query interfaces poll */
+	INIT_DELAYED_WORK(&tcon->query_interfaces,
+			  smb2_query_server_interfaces);
+	queue_delayed_work(cifsiod_wq, &tcon->query_interfaces,
+			   (SMB_INTERFACE_POLL_INTERVAL * HZ));
+
 	spin_lock(&cifs_tcp_ses_lock);
 	list_add(&tcon->tcon_list, &ses->tcon_list);
 	spin_unlock(&cifs_tcp_ses_lock);
diff --git a/fs/cifs/smb2ops.c b/fs/cifs/smb2ops.c
index db4ccf1d235e9..8802995b2d3d6 100644
--- a/fs/cifs/smb2ops.c
+++ b/fs/cifs/smb2ops.c
@@ -671,7 +671,7 @@ out:
 	return rc;
 }
 
-static int
+int
 SMB3_request_interfaces(const unsigned int xid, struct cifs_tcon *tcon)
 {
 	int rc;
-- 
GitLab


From 386228c694bf1e7a7688e44412cb33500b0ac585 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Tue, 21 Jun 2022 17:11:22 +0200
Subject: [PATCH 1034/1731] net: dsa: qca8k: reset cpu port on MTU change

It was discovered that the Documentation lacks of a fundamental detail
on how to correctly change the MAX_FRAME_SIZE of the switch.

In fact if the MAX_FRAME_SIZE is changed while the cpu port is on, the
switch panics and cease to send any packet. This cause the mgmt ethernet
system to not receive any packet (the slow fallback still works) and
makes the device not reachable. To recover from this a switch reset is
required.

To correctly handle this, turn off the cpu ports before changing the
MAX_FRAME_SIZE and turn on again after the value is applied.

Fixes: f58d2598cf70 ("net: dsa: qca8k: implement the port MTU callbacks")
Cc: stable@vger.kernel.org
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20220621151122.10220-1-ansuelsmth@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/dsa/qca8k.c | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 2727d3169c252..1cbb05b0323f0 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -2334,6 +2334,7 @@ static int
 qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
 {
 	struct qca8k_priv *priv = ds->priv;
+	int ret;
 
 	/* We have only have a general MTU setting.
 	 * DSA always set the CPU port's MTU to the largest MTU of the slave
@@ -2344,8 +2345,27 @@ qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
 	if (!dsa_is_cpu_port(ds, port))
 		return 0;
 
+	/* To change the MAX_FRAME_SIZE the cpu ports must be off or
+	 * the switch panics.
+	 * Turn off both cpu ports before applying the new value to prevent
+	 * this.
+	 */
+	if (priv->port_enabled_map & BIT(0))
+		qca8k_port_set_status(priv, 0, 0);
+
+	if (priv->port_enabled_map & BIT(6))
+		qca8k_port_set_status(priv, 6, 0);
+
 	/* Include L2 header / FCS length */
-	return qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, new_mtu + ETH_HLEN + ETH_FCS_LEN);
+	ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, new_mtu + ETH_HLEN + ETH_FCS_LEN);
+
+	if (priv->port_enabled_map & BIT(0))
+		qca8k_port_set_status(priv, 0, 1);
+
+	if (priv->port_enabled_map & BIT(6))
+		qca8k_port_set_status(priv, 6, 1);
+
+	return ret;
 }
 
 static int
-- 
GitLab


From 85467f7da18992311deafdbf32a8d163cb1e98d7 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Tue, 21 Jun 2022 17:16:33 +0200
Subject: [PATCH 1035/1731] net: dsa: qca8k: reduce mgmt ethernet timeout

The current mgmt ethernet timeout is set to 100ms. This value is too
big and would slow down any mdio command in case the mgmt ethernet
packet have some problems on the receiving part.
Reduce it to just 5ms to handle case when some operation are done on the
master port that would cause the mgmt ethernet to not work temporarily.

Fixes: 5950c7c0a68c ("net: dsa: qca8k: add support for mgmt read/write in Ethernet packet")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20220621151633.11741-1-ansuelsmth@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/dsa/qca8k.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index 04408e11402a9..ec58d0e80a70f 100644
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -15,7 +15,7 @@
 
 #define QCA8K_ETHERNET_MDIO_PRIORITY			7
 #define QCA8K_ETHERNET_PHY_PRIORITY			6
-#define QCA8K_ETHERNET_TIMEOUT				100
+#define QCA8K_ETHERNET_TIMEOUT				5
 
 #define QCA8K_NUM_PORTS					7
 #define QCA8K_NUM_CPU_PORTS				2
-- 
GitLab


From 4e0effd9007ea0be31f7488611eb3824b4541554 Mon Sep 17 00:00:00 2001
From: Kai-Heng Feng <kai.heng.feng@canonical.com>
Date: Tue, 21 Jun 2022 15:10:56 -0700
Subject: [PATCH 1036/1731] igb: Make DMA faster when CPU is active on the PCIe
 link

Intel I210 on some Intel Alder Lake platforms can only achieve ~750Mbps
Tx speed via iperf. The RR2DCDELAY shows around 0x2xxx DMA delay, which
will be significantly lower when 1) ASPM is disabled or 2) SoC package
c-state stays above PC3. When the RR2DCDELAY is around 0x1xxx the Tx
speed can reach to ~950Mbps.

According to the I210 datasheet "8.26.1 PCIe Misc. Register - PCIEMISC",
"DMA Idle Indication" doesn't seem to tie to DMA coalesce anymore, so
set it to 1b for "DMA is considered idle when there is no Rx or Tx AND
when there are no TLPs indicating that CPU is active detected on the
PCIe link (such as the host executes CSR or Configuration register read
or write operation)" and performing Tx should also fall under "active
CPU on PCIe link" case.

In addition to that, commit b6e0c419f040 ("igb: Move DMA Coalescing init
code to separate function.") seems to wrongly changed from enabling
E1000_PCIEMISC_LX_DECISION to disabling it, also fix that.

Fixes: b6e0c419f040 ("igb: Move DMA Coalescing init code to separate function.")
Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Tested-by: Gurucharan <gurucharanx.g@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Link: https://lore.kernel.org/r/20220621221056.604304-1-anthony.l.nguyen@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/ethernet/intel/igb/igb_main.c | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c
index 1c26bec7d6fa7..c5f04c40284bf 100644
--- a/drivers/net/ethernet/intel/igb/igb_main.c
+++ b/drivers/net/ethernet/intel/igb/igb_main.c
@@ -9901,11 +9901,10 @@ static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
 	struct e1000_hw *hw = &adapter->hw;
 	u32 dmac_thr;
 	u16 hwm;
+	u32 reg;
 
 	if (hw->mac.type > e1000_82580) {
 		if (adapter->flags & IGB_FLAG_DMAC) {
-			u32 reg;
-
 			/* force threshold to 0. */
 			wr32(E1000_DMCTXTH, 0);
 
@@ -9938,7 +9937,6 @@ static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
 			/* Disable BMC-to-OS Watchdog Enable */
 			if (hw->mac.type != e1000_i354)
 				reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
-
 			wr32(E1000_DMACR, reg);
 
 			/* no lower threshold to disable
@@ -9955,12 +9953,12 @@ static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
 			 */
 			wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
 			     (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
+		}
 
-			/* make low power state decision controlled
-			 * by DMA coal
-			 */
+		if (hw->mac.type >= e1000_i210 ||
+		    (adapter->flags & IGB_FLAG_DMAC)) {
 			reg = rd32(E1000_PCIEMISC);
-			reg &= ~E1000_PCIEMISC_LX_DECISION;
+			reg |= E1000_PCIEMISC_LX_DECISION;
 			wr32(E1000_PCIEMISC, reg);
 		} /* endif adapter->dmac is not disabled */
 	} else if (hw->mac.type == e1000_82580) {
-- 
GitLab


From 8af52fe9fd3bf5e7478da99193c0632276e1dfce Mon Sep 17 00:00:00 2001
From: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Date: Tue, 21 Jun 2022 13:48:44 +0200
Subject: [PATCH 1037/1731] virtio_net: fix xdp_rxq_info bug after
 suspend/resume

The following sequence currently causes a driver bug warning
when using virtio_net:

  # ip link set eth0 up
  # echo mem > /sys/power/state (or e.g. # rtcwake -s 10 -m mem)
  <resume>
  # ip link set eth0 down

  Missing register, driver bug
  WARNING: CPU: 0 PID: 375 at net/core/xdp.c:138 xdp_rxq_info_unreg+0x58/0x60
  Call trace:
   xdp_rxq_info_unreg+0x58/0x60
   virtnet_close+0x58/0xac
   __dev_close_many+0xac/0x140
   __dev_change_flags+0xd8/0x210
   dev_change_flags+0x24/0x64
   do_setlink+0x230/0xdd0
   ...

This happens because virtnet_freeze() frees the receive_queue
completely (including struct xdp_rxq_info) but does not call
xdp_rxq_info_unreg(). Similarly, virtnet_restore() sets up the
receive_queue again but does not call xdp_rxq_info_reg().

Actually, parts of virtnet_freeze_down() and virtnet_restore_up()
are almost identical to virtnet_close() and virtnet_open(): only
the calls to xdp_rxq_info_(un)reg() are missing. This means that
we can fix this easily and avoid such problems in the future by
just calling virtnet_close()/open() from the freeze/restore handlers.

Aside from adding the missing xdp_rxq_info calls the only difference
is that the refill work is only cancelled if netif_running(). However,
this should not make any functional difference since the refill work
should only be active if the network interface is actually up.

Fixes: 754b8a21a96d ("virtio_net: setup xdp_rxq_info")
Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Acked-by: Jesper Dangaard Brouer <brouer@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Link: https://lore.kernel.org/r/20220621114845.3650258-1-stephan.gerhold@kernkonzept.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/virtio_net.c | 25 ++++++-------------------
 1 file changed, 6 insertions(+), 19 deletions(-)

diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c
index db05b5e930bed..969a67970e71c 100644
--- a/drivers/net/virtio_net.c
+++ b/drivers/net/virtio_net.c
@@ -2768,7 +2768,6 @@ static const struct ethtool_ops virtnet_ethtool_ops = {
 static void virtnet_freeze_down(struct virtio_device *vdev)
 {
 	struct virtnet_info *vi = vdev->priv;
-	int i;
 
 	/* Make sure no work handler is accessing the device */
 	flush_work(&vi->config_work);
@@ -2776,14 +2775,8 @@ static void virtnet_freeze_down(struct virtio_device *vdev)
 	netif_tx_lock_bh(vi->dev);
 	netif_device_detach(vi->dev);
 	netif_tx_unlock_bh(vi->dev);
-	cancel_delayed_work_sync(&vi->refill);
-
-	if (netif_running(vi->dev)) {
-		for (i = 0; i < vi->max_queue_pairs; i++) {
-			napi_disable(&vi->rq[i].napi);
-			virtnet_napi_tx_disable(&vi->sq[i].napi);
-		}
-	}
+	if (netif_running(vi->dev))
+		virtnet_close(vi->dev);
 }
 
 static int init_vqs(struct virtnet_info *vi);
@@ -2791,7 +2784,7 @@ static int init_vqs(struct virtnet_info *vi);
 static int virtnet_restore_up(struct virtio_device *vdev)
 {
 	struct virtnet_info *vi = vdev->priv;
-	int err, i;
+	int err;
 
 	err = init_vqs(vi);
 	if (err)
@@ -2800,15 +2793,9 @@ static int virtnet_restore_up(struct virtio_device *vdev)
 	virtio_device_ready(vdev);
 
 	if (netif_running(vi->dev)) {
-		for (i = 0; i < vi->curr_queue_pairs; i++)
-			if (!try_fill_recv(vi, &vi->rq[i], GFP_KERNEL))
-				schedule_delayed_work(&vi->refill, 0);
-
-		for (i = 0; i < vi->max_queue_pairs; i++) {
-			virtnet_napi_enable(vi->rq[i].vq, &vi->rq[i].napi);
-			virtnet_napi_tx_enable(vi, vi->sq[i].vq,
-					       &vi->sq[i].napi);
-		}
+		err = virtnet_open(vi->dev);
+		if (err)
+			return err;
 	}
 
 	netif_tx_lock_bh(vi->dev);
-- 
GitLab


From 1b205d948fbb06a7613d87dcea0ff5fd8a08ed91 Mon Sep 17 00:00:00 2001
From: Jakub Kicinski <kuba@kernel.org>
Date: Mon, 20 Jun 2022 12:13:52 -0700
Subject: [PATCH 1038/1731] Revert "net/tls: fix tls_sk_proto_close executed
 repeatedly"

This reverts commit 69135c572d1f84261a6de2a1268513a7e71753e2.

This commit was just papering over the issue, ULP should not
get ->update() called with its own sk_prot. Each ULP would
need to add this check.

Fixes: 69135c572d1f ("net/tls: fix tls_sk_proto_close executed repeatedly")
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Reviewed-by: John Fastabend <john.fastabend@gmail.com>
Link: https://lore.kernel.org/r/20220620191353.1184629-1-kuba@kernel.org
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
 net/tls/tls_main.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/net/tls/tls_main.c b/net/tls/tls_main.c
index 46bd5f26338bf..da176411c1b5f 100644
--- a/net/tls/tls_main.c
+++ b/net/tls/tls_main.c
@@ -921,9 +921,6 @@ static void tls_update(struct sock *sk, struct proto *p,
 {
 	struct tls_context *ctx;
 
-	if (sk->sk_prot == p)
-		return;
-
 	ctx = tls_get_ctx(sk);
 	if (likely(ctx)) {
 		ctx->sk_write_space = write_space;
-- 
GitLab


From e34a07c0ae3906f97eb18df50902e2a01c1015b6 Mon Sep 17 00:00:00 2001
From: Jakub Kicinski <kuba@kernel.org>
Date: Mon, 20 Jun 2022 12:13:53 -0700
Subject: [PATCH 1039/1731] sock: redo the psock vs ULP protection check

Commit 8a59f9d1e3d4 ("sock: Introduce sk->sk_prot->psock_update_sk_prot()")
has moved the inet_csk_has_ulp(sk) check from sk_psock_init() to
the new tcp_bpf_update_proto() function. I'm guessing that this
was done to allow creating psocks for non-inet sockets.

Unfortunately the destruction path for psock includes the ULP
unwind, so we need to fail the sk_psock_init() itself.
Otherwise if ULP is already present we'll notice that later,
and call tcp_update_ulp() with the sk_proto of the ULP
itself, which will most likely result in the ULP looping
its callbacks.

Fixes: 8a59f9d1e3d4 ("sock: Introduce sk->sk_prot->psock_update_sk_prot()")
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Reviewed-by: John Fastabend <john.fastabend@gmail.com>
Reviewed-by: Jakub Sitnicki <jakub@cloudflare.com>
Tested-by: Jakub Sitnicki <jakub@cloudflare.com>
Link: https://lore.kernel.org/r/20220620191353.1184629-2-kuba@kernel.org
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
 include/net/inet_sock.h | 5 +++++
 net/core/skmsg.c        | 5 +++++
 net/ipv4/tcp_bpf.c      | 3 ---
 net/tls/tls_main.c      | 2 ++
 4 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/include/net/inet_sock.h b/include/net/inet_sock.h
index c1b5dcd6597c6..daead5fb389ae 100644
--- a/include/net/inet_sock.h
+++ b/include/net/inet_sock.h
@@ -253,6 +253,11 @@ struct inet_sock {
 #define IP_CMSG_CHECKSUM	BIT(7)
 #define IP_CMSG_RECVFRAGSIZE	BIT(8)
 
+static inline bool sk_is_inet(struct sock *sk)
+{
+	return sk->sk_family == AF_INET || sk->sk_family == AF_INET6;
+}
+
 /**
  * sk_to_full_sk - Access to a full socket
  * @sk: pointer to a socket
diff --git a/net/core/skmsg.c b/net/core/skmsg.c
index 22b983ade0e7d..b0fcd0200e84a 100644
--- a/net/core/skmsg.c
+++ b/net/core/skmsg.c
@@ -699,6 +699,11 @@ struct sk_psock *sk_psock_init(struct sock *sk, int node)
 
 	write_lock_bh(&sk->sk_callback_lock);
 
+	if (sk_is_inet(sk) && inet_csk_has_ulp(sk)) {
+		psock = ERR_PTR(-EINVAL);
+		goto out;
+	}
+
 	if (sk->sk_user_data) {
 		psock = ERR_PTR(-EBUSY);
 		goto out;
diff --git a/net/ipv4/tcp_bpf.c b/net/ipv4/tcp_bpf.c
index be3947e70fec5..0d3f68bb51c05 100644
--- a/net/ipv4/tcp_bpf.c
+++ b/net/ipv4/tcp_bpf.c
@@ -611,9 +611,6 @@ int tcp_bpf_update_proto(struct sock *sk, struct sk_psock *psock, bool restore)
 		return 0;
 	}
 
-	if (inet_csk_has_ulp(sk))
-		return -EINVAL;
-
 	if (sk->sk_family == AF_INET6) {
 		if (tcp_bpf_assert_proto_ops(psock->sk_proto))
 			return -EINVAL;
diff --git a/net/tls/tls_main.c b/net/tls/tls_main.c
index da176411c1b5f..2ffede463e4a5 100644
--- a/net/tls/tls_main.c
+++ b/net/tls/tls_main.c
@@ -921,6 +921,8 @@ static void tls_update(struct sock *sk, struct proto *p,
 {
 	struct tls_context *ctx;
 
+	WARN_ON_ONCE(sk->sk_prot == p);
+
 	ctx = tls_get_ctx(sk);
 	if (likely(ctx)) {
 		ctx->sk_write_space = write_space;
-- 
GitLab


From 12378a5a75e33f34f8586706eb61cca9e6d4690c Mon Sep 17 00:00:00 2001
From: Rosemarie O'Riorden <roriorden@redhat.com>
Date: Tue, 21 Jun 2022 16:48:45 -0400
Subject: [PATCH 1040/1731] net: openvswitch: fix parsing of nw_proto for IPv6
 fragments

When a packet enters the OVS datapath and does not match any existing
flows installed in the kernel flow cache, the packet will be sent to
userspace to be parsed, and a new flow will be created. The kernel and
OVS rely on each other to parse packet fields in the same way so that
packets will be handled properly.

As per the design document linked below, OVS expects all later IPv6
fragments to have nw_proto=44 in the flow key, so they can be correctly
matched on OpenFlow rules. OpenFlow controllers create pipelines based
on this design.

This behavior was changed by the commit in the Fixes tag so that
nw_proto equals the next_header field of the last extension header.
However, there is no counterpart for this change in OVS userspace,
meaning that this field is parsed differently between OVS and the
kernel. This is a problem because OVS creates actions based on what is
parsed in userspace, but the kernel-provided flow key is used as a match
criteria, as described in Documentation/networking/openvswitch.rst. This
leads to issues such as packets incorrectly matching on a flow and thus
the wrong list of actions being applied to the packet. Such changes in
packet parsing cannot be implemented without breaking the userspace.

The offending commit is partially reverted to restore the expected
behavior.

The change technically made sense and there is a good reason that it was
implemented, but it does not comply with the original design of OVS.
If in the future someone wants to implement such a change, then it must
be user-configurable and disabled by default to preserve backwards
compatibility with existing OVS versions.

Cc: stable@vger.kernel.org
Fixes: fa642f08839b ("openvswitch: Derive IP protocol number for IPv6 later frags")
Link: https://docs.openvswitch.org/en/latest/topics/design/#fragments
Signed-off-by: Rosemarie O'Riorden <roriorden@redhat.com>
Acked-by: Eelco Chaudron <echaudro@redhat.com>
Link: https://lore.kernel.org/r/20220621204845.9721-1-roriorden@redhat.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
 net/openvswitch/flow.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/net/openvswitch/flow.c b/net/openvswitch/flow.c
index 372bf54a0ca9e..e20d1a9734175 100644
--- a/net/openvswitch/flow.c
+++ b/net/openvswitch/flow.c
@@ -407,7 +407,7 @@ static int parse_ipv6hdr(struct sk_buff *skb, struct sw_flow_key *key)
 	if (flags & IP6_FH_F_FRAG) {
 		if (frag_off) {
 			key->ip.frag = OVS_FRAG_TYPE_LATER;
-			key->ip.proto = nexthdr;
+			key->ip.proto = NEXTHDR_FRAGMENT;
 			return 0;
 		}
 		key->ip.frag = OVS_FRAG_TYPE_FIRST;
-- 
GitLab


From 15b694e96c31807d8515aacfa687a1e8a4fbbadc Mon Sep 17 00:00:00 2001
From: Macpaul Lin <macpaul.lin@mediatek.com>
Date: Thu, 23 Jun 2022 16:56:44 +0800
Subject: [PATCH 1041/1731] USB: serial: option: add Quectel RM500K module
 support

Add usb product id of the Quectel RM500K module.

RM500K provides 2 mandatory interfaces to Linux host after enumeration.
 - /dev/ttyUSB5: this is a serial interface for control path. User needs
   to write AT commands to this device node to query status, set APN,
   set PIN code, and enable/disable the data connection to 5G network.
 - ethX: this is the data path provided as a RNDIS devices. After the
   data connection has been established, Linux host can access 5G data
   network via this interface.

"RNDIS": RNDIS + ADB + AT (/dev/ttyUSB5) + MODEM COMs

usb-devices output for 0x7001:
T:  Bus=05 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#=  3 Spd=480 MxCh= 0
D:  Ver= 2.10 Cls=ef(misc ) Sub=02 Prot=01 MxPS=64 #Cfgs=  1
P:  Vendor=2c7c ProdID=7001 Rev=00.01
S:  Manufacturer=MediaTek Inc.
S:  Product=USB DATA CARD
S:  SerialNumber=869206050009672
C:  #Ifs=10 Cfg#= 1 Atr=a0 MxPwr=500mA
I:  If#= 0 Alt= 0 #EPs= 1 Cls=02(commc) Sub=02 Prot=ff Driver=rndis_host
E:  Ad=82(I) Atr=03(Int.) MxPS=  64 Ivl=125us
I:  If#= 1 Alt= 0 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver=rndis_host
E:  Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:  If#= 2 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=83(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:  If#= 3 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:  If#= 4 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=04(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=85(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:  If#= 5 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=42 Prot=01 Driver=(none)
E:  Ad=05(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:  If#= 6 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=06(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=87(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:  If#= 7 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=07(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=88(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:  If#= 8 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=08(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=89(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:  If#= 9 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=09(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=8a(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms

Co-developed-by: Ballon Shi <ballon.shi@quectel.com>
Signed-off-by: Ballon Shi <ballon.shi@quectel.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Cc: stable@vger.kernel.org
Signed-off-by: Johan Hovold <johan@kernel.org>
---
 drivers/usb/serial/option.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
index 61d34886c7066..de59fa919540a 100644
--- a/drivers/usb/serial/option.c
+++ b/drivers/usb/serial/option.c
@@ -257,6 +257,7 @@ static void option_instat_callback(struct urb *urb);
 #define QUECTEL_PRODUCT_RM500Q			0x0800
 #define QUECTEL_PRODUCT_EC200S_CN		0x6002
 #define QUECTEL_PRODUCT_EC200T			0x6026
+#define QUECTEL_PRODUCT_RM500K			0x7001
 
 #define CMOTECH_VENDOR_ID			0x16d8
 #define CMOTECH_PRODUCT_6001			0x6001
@@ -1150,6 +1151,7 @@ static const struct usb_device_id option_ids[] = {
 	  .driver_info = ZLP },
 	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200S_CN, 0xff, 0, 0) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200T, 0xff, 0, 0) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RM500K, 0xff, 0x00, 0x00) },
 
 	{ USB_DEVICE(CMOTECH_VENDOR_ID, CMOTECH_PRODUCT_6001) },
 	{ USB_DEVICE(CMOTECH_VENDOR_ID, CMOTECH_PRODUCT_CMU_300) },
-- 
GitLab


From 41f38043f884c66af4114a7109cf540d6222f450 Mon Sep 17 00:00:00 2001
From: Leo Savernik <l.savernik@aon.at>
Date: Wed, 22 Jun 2022 12:19:21 +0200
Subject: [PATCH 1042/1731] nvme: add a bogus subsystem NQN quirk for Micron
 MTFDKBA2T0TFH

The Micron MTFDKBA2T0TFH device reports the same subsysem NQN for
all devices.  Add a quick to ignore it.

Signed-off-by: Leo Savernik <l.savernik@aon.at>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/host/pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index c7012e85d035d..1871d216e1f15 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -3474,6 +3474,8 @@ static const struct pci_device_id nvme_id_table[] = {
 	{ PCI_DEVICE(0x1cc1, 0x8201),   /* ADATA SX8200PNP 512GB */
 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS |
 				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
+	 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
+		.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
 	{ PCI_DEVICE(0x1c5c, 0x1504),   /* SK Hynix PC400 */
 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
 	{ PCI_DEVICE(0x1c5c, 0x174a),   /* SK Hynix P31 SSD */
-- 
GitLab


From 23c9cd56007e90b2c2317c5eab6ab12921b4314a Mon Sep 17 00:00:00 2001
From: Joel Granados <j.granados@samsung.com>
Date: Tue, 21 Jun 2022 09:05:00 +0200
Subject: [PATCH 1043/1731] nvme: fix the CRIMS and CRWMS definitions to match
 the spec

Adjust the values of NVME_CAP_CRMS_CRIMS and NVME_CAP_CRMS_CRWMS masks as
they are different from the ones in TP4084 - Time-to-ready.

Fixes: 354201c53e61 ("nvme: add support for TP4084 - Time-to-Ready Enhancements").
Signed-off-by: Joel Granados <j.granados@samsung.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Sagi Grimberg <sagi@grimberg.me>
Reviewed-by: Chaitanya Kulkarni <kch@nvidia.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 include/linux/nvme.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/linux/nvme.h b/include/linux/nvme.h
index 29ec3e3481ff6..e3934003f2397 100644
--- a/include/linux/nvme.h
+++ b/include/linux/nvme.h
@@ -233,8 +233,8 @@ enum {
 };
 
 enum {
-	NVME_CAP_CRMS_CRIMS	= 1ULL << 59,
-	NVME_CAP_CRMS_CRWMS	= 1ULL << 60,
+	NVME_CAP_CRMS_CRWMS	= 1ULL << 59,
+	NVME_CAP_CRMS_CRIMS	= 1ULL << 60,
 };
 
 struct nvme_id_power_state {
-- 
GitLab


From e6487833182a8a0187f0292aca542fc163ccd03e Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Fri, 17 Jun 2022 10:29:42 +0200
Subject: [PATCH 1044/1731] nvme: move the Samsung X5 quirk entry to the core
 quirks

This device shares the PCI ID with the Samsung 970 Evo Plus that
does not need or want the quirks.  Move the the quirk entry to the
core table based on the model number instead.

Fixes: bc360b0b1611 ("nvme-pci: add quirks for Samsung X5 SSDs")
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Pankaj Raghav <p.raghav@samsung.com>
---
 drivers/nvme/host/core.c | 14 ++++++++++++++
 drivers/nvme/host/pci.c  |  4 ----
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c
index 3ab2cfd254a44..b3d9c29aba1e6 100644
--- a/drivers/nvme/host/core.c
+++ b/drivers/nvme/host/core.c
@@ -2546,6 +2546,20 @@ static const struct nvme_core_quirk_entry core_quirks[] = {
 		.vid = 0x1e0f,
 		.mn = "KCD6XVUL6T40",
 		.quirks = NVME_QUIRK_NO_APST,
+	},
+	{
+		/*
+		 * The external Samsung X5 SSD fails initialization without a
+		 * delay before checking if it is ready and has a whole set of
+		 * other problems.  To make this even more interesting, it
+		 * shares the PCI ID with internal Samsung 970 Evo Plus that
+		 * does not need or want these quirks.
+		 */
+		.vid = 0x144d,
+		.mn = "Samsung Portable SSD X5",
+		.quirks = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
+			  NVME_QUIRK_NO_DEEPEST_PS |
+			  NVME_QUIRK_IGNORE_DEV_SUBNQN,
 	}
 };
 
diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 1871d216e1f15..d7b24ee172859 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -3526,10 +3526,6 @@ static const struct pci_device_id nvme_id_table[] = {
 				NVME_QUIRK_128_BYTES_SQES |
 				NVME_QUIRK_SHARED_TAGS |
 				NVME_QUIRK_SKIP_CID_GEN },
-	{ PCI_DEVICE(0x144d, 0xa808),   /* Samsung X5 */
-		.driver_data =  NVME_QUIRK_DELAY_BEFORE_CHK_RDY|
-				NVME_QUIRK_NO_DEEPEST_PS |
-				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
 	{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
 	{ 0, }
 };
-- 
GitLab


From 3be4562584bba603f33863a00c1c32eecf772ee6 Mon Sep 17 00:00:00 2001
From: Dexuan Cui <decui@microsoft.com>
Date: Wed, 22 Jun 2022 12:14:24 -0700
Subject: [PATCH 1045/1731] dma-direct: use the correct size for
 dma_set_encrypted()

The third parameter of dma_set_encrypted() is a size in bytes rather than
the number of pages.

Fixes: 4d0564785bb0 ("dma-direct: factor out dma_set_{de,en}crypted helpers")
Signed-off-by: Dexuan Cui <decui@microsoft.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 kernel/dma/direct.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c
index e978f36e6be86..8d0b68a170422 100644
--- a/kernel/dma/direct.c
+++ b/kernel/dma/direct.c
@@ -357,7 +357,7 @@ void dma_direct_free(struct device *dev, size_t size,
 	} else {
 		if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_CLEAR_UNCACHED))
 			arch_dma_clear_uncached(cpu_addr, size);
-		if (dma_set_encrypted(dev, cpu_addr, 1 << page_order))
+		if (dma_set_encrypted(dev, cpu_addr, size))
 			return;
 	}
 
@@ -392,7 +392,6 @@ void dma_direct_free_pages(struct device *dev, size_t size,
 		struct page *page, dma_addr_t dma_addr,
 		enum dma_data_direction dir)
 {
-	unsigned int page_order = get_order(size);
 	void *vaddr = page_address(page);
 
 	/* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
@@ -400,7 +399,7 @@ void dma_direct_free_pages(struct device *dev, size_t size,
 	    dma_free_from_pool(dev, vaddr, size))
 		return;
 
-	if (dma_set_encrypted(dev, vaddr, 1 << page_order))
+	if (dma_set_encrypted(dev, vaddr, size))
 		return;
 	__dma_direct_free_pages(dev, page, size);
 }
-- 
GitLab


From dbe97cff7dd9f0f75c524afdd55ad46be3d15295 Mon Sep 17 00:00:00 2001
From: Demi Marie Obenour <demi@invisiblethingslab.com>
Date: Tue, 21 Jun 2022 22:27:26 -0400
Subject: [PATCH 1046/1731] xen/gntdev: Avoid blocking in unmap_grant_pages()

unmap_grant_pages() currently waits for the pages to no longer be used.
In https://github.com/QubesOS/qubes-issues/issues/7481, this lead to a
deadlock against i915: i915 was waiting for gntdev's MMU notifier to
finish, while gntdev was waiting for i915 to free its pages.  I also
believe this is responsible for various deadlocks I have experienced in
the past.

Avoid these problems by making unmap_grant_pages async.  This requires
making it return void, as any errors will not be available when the
function returns.  Fortunately, the only use of the return value is a
WARN_ON(), which can be replaced by a WARN_ON when the error is
detected.  Additionally, a failed call will not prevent further calls
from being made, but this is harmless.

Because unmap_grant_pages is now async, the grant handle will be sent to
INVALID_GRANT_HANDLE too late to prevent multiple unmaps of the same
handle.  Instead, a separate bool array is allocated for this purpose.
This wastes memory, but stuffing this information in padding bytes is
too fragile.  Furthermore, it is necessary to grab a reference to the
map before making the asynchronous call, and release the reference when
the call returns.

It is also necessary to guard against reentrancy in gntdev_map_put(),
and to handle the case where userspace tries to map a mapping whose
contents have not all been freed yet.

Fixes: 745282256c75 ("xen/gntdev: safely unmap grants in case they are still in use")
Cc: stable@vger.kernel.org
Signed-off-by: Demi Marie Obenour <demi@invisiblethingslab.com>
Reviewed-by: Juergen Gross <jgross@suse.com>
Link: https://lore.kernel.org/r/20220622022726.2538-1-demi@invisiblethingslab.com
Signed-off-by: Juergen Gross <jgross@suse.com>
---
 drivers/xen/gntdev-common.h |   7 ++
 drivers/xen/gntdev.c        | 157 ++++++++++++++++++++++++------------
 2 files changed, 113 insertions(+), 51 deletions(-)

diff --git a/drivers/xen/gntdev-common.h b/drivers/xen/gntdev-common.h
index 20d7d059dadb5..40ef379c28ab0 100644
--- a/drivers/xen/gntdev-common.h
+++ b/drivers/xen/gntdev-common.h
@@ -16,6 +16,7 @@
 #include <linux/mmu_notifier.h>
 #include <linux/types.h>
 #include <xen/interface/event_channel.h>
+#include <xen/grant_table.h>
 
 struct gntdev_dmabuf_priv;
 
@@ -56,6 +57,7 @@ struct gntdev_grant_map {
 	struct gnttab_unmap_grant_ref *unmap_ops;
 	struct gnttab_map_grant_ref   *kmap_ops;
 	struct gnttab_unmap_grant_ref *kunmap_ops;
+	bool *being_removed;
 	struct page **pages;
 	unsigned long pages_vm_start;
 
@@ -73,6 +75,11 @@ struct gntdev_grant_map {
 	/* Needed to avoid allocation in gnttab_dma_free_pages(). */
 	xen_pfn_t *frames;
 #endif
+
+	/* Number of live grants */
+	atomic_t live_grants;
+	/* Needed to avoid allocation in __unmap_grant_pages */
+	struct gntab_unmap_queue_data unmap_data;
 };
 
 struct gntdev_grant_map *gntdev_alloc_map(struct gntdev_priv *priv, int count,
diff --git a/drivers/xen/gntdev.c b/drivers/xen/gntdev.c
index 59ffea8000791..4b56c39f766d4 100644
--- a/drivers/xen/gntdev.c
+++ b/drivers/xen/gntdev.c
@@ -35,6 +35,7 @@
 #include <linux/slab.h>
 #include <linux/highmem.h>
 #include <linux/refcount.h>
+#include <linux/workqueue.h>
 
 #include <xen/xen.h>
 #include <xen/grant_table.h>
@@ -60,10 +61,11 @@ module_param(limit, uint, 0644);
 MODULE_PARM_DESC(limit,
 	"Maximum number of grants that may be mapped by one mapping request");
 
+/* True in PV mode, false otherwise */
 static int use_ptemod;
 
-static int unmap_grant_pages(struct gntdev_grant_map *map,
-			     int offset, int pages);
+static void unmap_grant_pages(struct gntdev_grant_map *map,
+			      int offset, int pages);
 
 static struct miscdevice gntdev_miscdev;
 
@@ -120,6 +122,7 @@ static void gntdev_free_map(struct gntdev_grant_map *map)
 	kvfree(map->unmap_ops);
 	kvfree(map->kmap_ops);
 	kvfree(map->kunmap_ops);
+	kvfree(map->being_removed);
 	kfree(map);
 }
 
@@ -140,10 +143,13 @@ struct gntdev_grant_map *gntdev_alloc_map(struct gntdev_priv *priv, int count,
 	add->unmap_ops = kvmalloc_array(count, sizeof(add->unmap_ops[0]),
 					GFP_KERNEL);
 	add->pages     = kvcalloc(count, sizeof(add->pages[0]), GFP_KERNEL);
+	add->being_removed =
+		kvcalloc(count, sizeof(add->being_removed[0]), GFP_KERNEL);
 	if (NULL == add->grants    ||
 	    NULL == add->map_ops   ||
 	    NULL == add->unmap_ops ||
-	    NULL == add->pages)
+	    NULL == add->pages     ||
+	    NULL == add->being_removed)
 		goto err;
 	if (use_ptemod) {
 		add->kmap_ops   = kvmalloc_array(count, sizeof(add->kmap_ops[0]),
@@ -250,9 +256,36 @@ void gntdev_put_map(struct gntdev_priv *priv, struct gntdev_grant_map *map)
 	if (!refcount_dec_and_test(&map->users))
 		return;
 
-	if (map->pages && !use_ptemod)
+	if (map->pages && !use_ptemod) {
+		/*
+		 * Increment the reference count.  This ensures that the
+		 * subsequent call to unmap_grant_pages() will not wind up
+		 * re-entering itself.  It *can* wind up calling
+		 * gntdev_put_map() recursively, but such calls will be with a
+		 * reference count greater than 1, so they will return before
+		 * this code is reached.  The recursion depth is thus limited to
+		 * 1.  Do NOT use refcount_inc() here, as it will detect that
+		 * the reference count is zero and WARN().
+		 */
+		refcount_set(&map->users, 1);
+
+		/*
+		 * Unmap the grants.  This may or may not be asynchronous, so it
+		 * is possible that the reference count is 1 on return, but it
+		 * could also be greater than 1.
+		 */
 		unmap_grant_pages(map, 0, map->count);
 
+		/* Check if the memory now needs to be freed */
+		if (!refcount_dec_and_test(&map->users))
+			return;
+
+		/*
+		 * All pages have been returned to the hypervisor, so free the
+		 * map.
+		 */
+	}
+
 	if (map->notify.flags & UNMAP_NOTIFY_SEND_EVENT) {
 		notify_remote_via_evtchn(map->notify.event);
 		evtchn_put(map->notify.event);
@@ -283,6 +316,7 @@ static int find_grant_ptes(pte_t *pte, unsigned long addr, void *data)
 
 int gntdev_map_grant_pages(struct gntdev_grant_map *map)
 {
+	size_t alloced = 0;
 	int i, err = 0;
 
 	if (!use_ptemod) {
@@ -331,97 +365,116 @@ int gntdev_map_grant_pages(struct gntdev_grant_map *map)
 			map->count);
 
 	for (i = 0; i < map->count; i++) {
-		if (map->map_ops[i].status == GNTST_okay)
+		if (map->map_ops[i].status == GNTST_okay) {
 			map->unmap_ops[i].handle = map->map_ops[i].handle;
-		else if (!err)
+			if (!use_ptemod)
+				alloced++;
+		} else if (!err)
 			err = -EINVAL;
 
 		if (map->flags & GNTMAP_device_map)
 			map->unmap_ops[i].dev_bus_addr = map->map_ops[i].dev_bus_addr;
 
 		if (use_ptemod) {
-			if (map->kmap_ops[i].status == GNTST_okay)
+			if (map->kmap_ops[i].status == GNTST_okay) {
+				if (map->map_ops[i].status == GNTST_okay)
+					alloced++;
 				map->kunmap_ops[i].handle = map->kmap_ops[i].handle;
-			else if (!err)
+			} else if (!err)
 				err = -EINVAL;
 		}
 	}
+	atomic_add(alloced, &map->live_grants);
 	return err;
 }
 
-static int __unmap_grant_pages(struct gntdev_grant_map *map, int offset,
-			       int pages)
+static void __unmap_grant_pages_done(int result,
+		struct gntab_unmap_queue_data *data)
 {
-	int i, err = 0;
-	struct gntab_unmap_queue_data unmap_data;
-
-	if (map->notify.flags & UNMAP_NOTIFY_CLEAR_BYTE) {
-		int pgno = (map->notify.addr >> PAGE_SHIFT);
-		if (pgno >= offset && pgno < offset + pages) {
-			/* No need for kmap, pages are in lowmem */
-			uint8_t *tmp = pfn_to_kaddr(page_to_pfn(map->pages[pgno]));
-			tmp[map->notify.addr & (PAGE_SIZE-1)] = 0;
-			map->notify.flags &= ~UNMAP_NOTIFY_CLEAR_BYTE;
-		}
-	}
-
-	unmap_data.unmap_ops = map->unmap_ops + offset;
-	unmap_data.kunmap_ops = use_ptemod ? map->kunmap_ops + offset : NULL;
-	unmap_data.pages = map->pages + offset;
-	unmap_data.count = pages;
-
-	err = gnttab_unmap_refs_sync(&unmap_data);
-	if (err)
-		return err;
+	unsigned int i;
+	struct gntdev_grant_map *map = data->data;
+	unsigned int offset = data->unmap_ops - map->unmap_ops;
 
-	for (i = 0; i < pages; i++) {
-		if (map->unmap_ops[offset+i].status)
-			err = -EINVAL;
+	for (i = 0; i < data->count; i++) {
+		WARN_ON(map->unmap_ops[offset+i].status);
 		pr_debug("unmap handle=%d st=%d\n",
 			map->unmap_ops[offset+i].handle,
 			map->unmap_ops[offset+i].status);
 		map->unmap_ops[offset+i].handle = INVALID_GRANT_HANDLE;
 		if (use_ptemod) {
-			if (map->kunmap_ops[offset+i].status)
-				err = -EINVAL;
+			WARN_ON(map->kunmap_ops[offset+i].status);
 			pr_debug("kunmap handle=%u st=%d\n",
 				 map->kunmap_ops[offset+i].handle,
 				 map->kunmap_ops[offset+i].status);
 			map->kunmap_ops[offset+i].handle = INVALID_GRANT_HANDLE;
 		}
 	}
-	return err;
+	/*
+	 * Decrease the live-grant counter.  This must happen after the loop to
+	 * prevent premature reuse of the grants by gnttab_mmap().
+	 */
+	atomic_sub(data->count, &map->live_grants);
+
+	/* Release reference taken by __unmap_grant_pages */
+	gntdev_put_map(NULL, map);
+}
+
+static void __unmap_grant_pages(struct gntdev_grant_map *map, int offset,
+			       int pages)
+{
+	if (map->notify.flags & UNMAP_NOTIFY_CLEAR_BYTE) {
+		int pgno = (map->notify.addr >> PAGE_SHIFT);
+
+		if (pgno >= offset && pgno < offset + pages) {
+			/* No need for kmap, pages are in lowmem */
+			uint8_t *tmp = pfn_to_kaddr(page_to_pfn(map->pages[pgno]));
+
+			tmp[map->notify.addr & (PAGE_SIZE-1)] = 0;
+			map->notify.flags &= ~UNMAP_NOTIFY_CLEAR_BYTE;
+		}
+	}
+
+	map->unmap_data.unmap_ops = map->unmap_ops + offset;
+	map->unmap_data.kunmap_ops = use_ptemod ? map->kunmap_ops + offset : NULL;
+	map->unmap_data.pages = map->pages + offset;
+	map->unmap_data.count = pages;
+	map->unmap_data.done = __unmap_grant_pages_done;
+	map->unmap_data.data = map;
+	refcount_inc(&map->users); /* to keep map alive during async call below */
+
+	gnttab_unmap_refs_async(&map->unmap_data);
 }
 
-static int unmap_grant_pages(struct gntdev_grant_map *map, int offset,
-			     int pages)
+static void unmap_grant_pages(struct gntdev_grant_map *map, int offset,
+			      int pages)
 {
-	int range, err = 0;
+	int range;
+
+	if (atomic_read(&map->live_grants) == 0)
+		return; /* Nothing to do */
 
 	pr_debug("unmap %d+%d [%d+%d]\n", map->index, map->count, offset, pages);
 
 	/* It is possible the requested range will have a "hole" where we
 	 * already unmapped some of the grants. Only unmap valid ranges.
 	 */
-	while (pages && !err) {
-		while (pages &&
-		       map->unmap_ops[offset].handle == INVALID_GRANT_HANDLE) {
+	while (pages) {
+		while (pages && map->being_removed[offset]) {
 			offset++;
 			pages--;
 		}
 		range = 0;
 		while (range < pages) {
-			if (map->unmap_ops[offset + range].handle ==
-			    INVALID_GRANT_HANDLE)
+			if (map->being_removed[offset + range])
 				break;
+			map->being_removed[offset + range] = true;
 			range++;
 		}
-		err = __unmap_grant_pages(map, offset, range);
+		if (range)
+			__unmap_grant_pages(map, offset, range);
 		offset += range;
 		pages -= range;
 	}
-
-	return err;
 }
 
 /* ------------------------------------------------------------------ */
@@ -473,7 +526,6 @@ static bool gntdev_invalidate(struct mmu_interval_notifier *mn,
 	struct gntdev_grant_map *map =
 		container_of(mn, struct gntdev_grant_map, notifier);
 	unsigned long mstart, mend;
-	int err;
 
 	if (!mmu_notifier_range_blockable(range))
 		return false;
@@ -494,10 +546,9 @@ static bool gntdev_invalidate(struct mmu_interval_notifier *mn,
 			map->index, map->count,
 			map->vma->vm_start, map->vma->vm_end,
 			range->start, range->end, mstart, mend);
-	err = unmap_grant_pages(map,
+	unmap_grant_pages(map,
 				(mstart - map->vma->vm_start) >> PAGE_SHIFT,
 				(mend - mstart) >> PAGE_SHIFT);
-	WARN_ON(err);
 
 	return true;
 }
@@ -985,6 +1036,10 @@ static int gntdev_mmap(struct file *flip, struct vm_area_struct *vma)
 		goto unlock_out;
 	if (use_ptemod && map->vma)
 		goto unlock_out;
+	if (atomic_read(&map->live_grants)) {
+		err = -EAGAIN;
+		goto unlock_out;
+	}
 	refcount_inc(&map->users);
 
 	vma->vm_ops = &gntdev_vmops;
-- 
GitLab


From ca2a3343d69741dae4df2dbb954fb806d9a835de Mon Sep 17 00:00:00 2001
From: Li Nan <linan122@huawei.com>
Date: Thu, 23 Jun 2022 15:41:00 +0800
Subject: [PATCH 1047/1731] block: remove WARN_ON() from bd_link_disk_holder

Since commit 83cbce957446("block: add error handling for device_add_disk /
add_disk"), bdev->bd_holder_dir can not be empty now, so remove WARN_ON()
from bd_link_disk_holder.

Signed-off-by: Li Nan <linan122@huawei.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Link: https://lore.kernel.org/r/20220623074100.2251301-1-linan122@huawei.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 block/holder.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/block/holder.c b/block/holder.c
index 8d750281a1cd9..5283bc804cc14 100644
--- a/block/holder.c
+++ b/block/holder.c
@@ -79,10 +79,6 @@ int bd_link_disk_holder(struct block_device *bdev, struct gendisk *disk)
 
 	WARN_ON_ONCE(!bdev->bd_holder);
 
-	/* FIXME: remove the following once add_disk() handles errors */
-	if (WARN_ON(!bdev->bd_holder_dir))
-		goto out_unlock;
-
 	holder = bd_find_holder_disk(bdev, disk);
 	if (holder) {
 		holder->refcnt++;
-- 
GitLab


From 9e2f6498efbbc880d7caa7935839e682b64fe5a6 Mon Sep 17 00:00:00 2001
From: Raghavendra Rao Ananta <rananta@google.com>
Date: Wed, 15 Jun 2022 18:57:06 +0000
Subject: [PATCH 1048/1731] selftests: KVM: Handle compiler optimizations in
 ucall

The selftests, when built with newer versions of clang, is found
to have over optimized guests' ucall() function, and eliminating
the stores for uc.cmd (perhaps due to no immediate readers). This
resulted in the userspace side always reading a value of '0', and
causing multiple test failures.

As a result, prevent the compiler from optimizing the stores in
ucall() with WRITE_ONCE().

Suggested-by: Ricardo Koller <ricarkol@google.com>
Suggested-by: Reiji Watanabe <reijiw@google.com>
Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
Message-Id: <20220615185706.1099208-1-rananta@google.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/lib/aarch64/ucall.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/tools/testing/selftests/kvm/lib/aarch64/ucall.c b/tools/testing/selftests/kvm/lib/aarch64/ucall.c
index e0b0164e9af85..be1d9728c4cea 100644
--- a/tools/testing/selftests/kvm/lib/aarch64/ucall.c
+++ b/tools/testing/selftests/kvm/lib/aarch64/ucall.c
@@ -73,20 +73,19 @@ void ucall_uninit(struct kvm_vm *vm)
 
 void ucall(uint64_t cmd, int nargs, ...)
 {
-	struct ucall uc = {
-		.cmd = cmd,
-	};
+	struct ucall uc = {};
 	va_list va;
 	int i;
 
+	WRITE_ONCE(uc.cmd, cmd);
 	nargs = nargs <= UCALL_MAX_ARGS ? nargs : UCALL_MAX_ARGS;
 
 	va_start(va, nargs);
 	for (i = 0; i < nargs; ++i)
-		uc.args[i] = va_arg(va, uint64_t);
+		WRITE_ONCE(uc.args[i], va_arg(va, uint64_t));
 	va_end(va);
 
-	*ucall_exit_mmio_addr = (vm_vaddr_t)&uc;
+	WRITE_ONCE(*ucall_exit_mmio_addr, (vm_vaddr_t)&uc);
 }
 
 uint64_t get_ucall(struct kvm_vm *vm, uint32_t vcpu_id, struct ucall *uc)
-- 
GitLab


From a808925075fb750804a60ff0710614466c396db4 Mon Sep 17 00:00:00 2001
From: Hongyu Xie <xy521521@gmail.com>
Date: Thu, 23 Jun 2022 14:19:42 +0300
Subject: [PATCH 1049/1731] xhci: Keep interrupt disabled in initialization
 until host is running.

irq is disabled in xhci_quiesce(called by xhci_halt, with bit:2 cleared
in USBCMD register), but xhci_run(called by usb_add_hcd) re-enable it.
It's possible that you will receive thousands of interrupt requests
after initialization for 2.0 roothub. And you will get a lot of
warning like, "xHCI dying, ignoring interrupt. Shouldn't IRQs be
disabled?". This amount of interrupt requests will cause the entire
system to freeze.
This problem was first found on a device with ASM2142 host controller
on it.

[tidy up old code while moving it, reword header -Mathias]

Cc: stable@kernel.org
Signed-off-by: Hongyu Xie <xiehongyu1@kylinos.cn>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Link: https://lore.kernel.org/r/20220623111945.1557702-2-mathias.nyman@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/host/xhci.c | 35 ++++++++++++++++++++++-------------
 1 file changed, 22 insertions(+), 13 deletions(-)

diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 9ac56e9ffc645..cb99bed5f755e 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -611,15 +611,37 @@ static int xhci_init(struct usb_hcd *hcd)
 
 static int xhci_run_finished(struct xhci_hcd *xhci)
 {
+	unsigned long	flags;
+	u32		temp;
+
+	/*
+	 * Enable interrupts before starting the host (xhci 4.2 and 5.5.2).
+	 * Protect the short window before host is running with a lock
+	 */
+	spin_lock_irqsave(&xhci->lock, flags);
+
+	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable interrupts");
+	temp = readl(&xhci->op_regs->command);
+	temp |= (CMD_EIE);
+	writel(temp, &xhci->op_regs->command);
+
+	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable primary interrupter");
+	temp = readl(&xhci->ir_set->irq_pending);
+	writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
+
 	if (xhci_start(xhci)) {
 		xhci_halt(xhci);
+		spin_unlock_irqrestore(&xhci->lock, flags);
 		return -ENODEV;
 	}
+
 	xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
 
 	if (xhci->quirks & XHCI_NEC_HOST)
 		xhci_ring_cmd_db(xhci);
 
+	spin_unlock_irqrestore(&xhci->lock, flags);
+
 	return 0;
 }
 
@@ -668,19 +690,6 @@ int xhci_run(struct usb_hcd *hcd)
 	temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
 	writel(temp, &xhci->ir_set->irq_control);
 
-	/* Set the HCD state before we enable the irqs */
-	temp = readl(&xhci->op_regs->command);
-	temp |= (CMD_EIE);
-	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
-			"// Enable interrupts, cmd = 0x%x.", temp);
-	writel(temp, &xhci->op_regs->command);
-
-	temp = readl(&xhci->ir_set->irq_pending);
-	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
-			"// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
-			xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
-	writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
-
 	if (xhci->quirks & XHCI_NEC_HOST) {
 		struct xhci_command *command;
 
-- 
GitLab


From 83810f84ecf11dfc5a9414a8b762c3501b328185 Mon Sep 17 00:00:00 2001
From: Mathias Nyman <mathias.nyman@linux.intel.com>
Date: Thu, 23 Jun 2022 14:19:43 +0300
Subject: [PATCH 1050/1731] xhci: turn off port power in shutdown

If ports are not turned off in shutdown then runtime suspended
self-powered USB devices may survive in U3 link state over S5.

During subsequent boot, if firmware sends an IPC command to program
the port in DISCONNECT state, it will time out, causing significant
delay in the boot time.

Turning off roothub port power is also recommended in xhci
specification 4.19.4 "Port Power" in the additional note.

Cc: stable@vger.kernel.org
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Link: https://lore.kernel.org/r/20220623111945.1557702-3-mathias.nyman@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/host/xhci-hub.c |  2 +-
 drivers/usb/host/xhci.c     | 15 +++++++++++++--
 drivers/usb/host/xhci.h     |  2 ++
 3 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
index c54f2bc23d3f8..0fdc014c94011 100644
--- a/drivers/usb/host/xhci-hub.c
+++ b/drivers/usb/host/xhci-hub.c
@@ -652,7 +652,7 @@ struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
  * It will release and re-aquire the lock while calling ACPI
  * method.
  */
-static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
+void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
 				u16 index, bool on, unsigned long *flags)
 	__must_hold(&xhci->lock)
 {
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index cb99bed5f755e..65858f6074377 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -791,6 +791,8 @@ static void xhci_stop(struct usb_hcd *hcd)
 void xhci_shutdown(struct usb_hcd *hcd)
 {
 	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+	unsigned long flags;
+	int i;
 
 	if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
 		usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
@@ -806,12 +808,21 @@ void xhci_shutdown(struct usb_hcd *hcd)
 		del_timer_sync(&xhci->shared_hcd->rh_timer);
 	}
 
-	spin_lock_irq(&xhci->lock);
+	spin_lock_irqsave(&xhci->lock, flags);
 	xhci_halt(xhci);
+
+	/* Power off USB2 ports*/
+	for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
+		xhci_set_port_power(xhci, xhci->main_hcd, i, false, &flags);
+
+	/* Power off USB3 ports*/
+	for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
+		xhci_set_port_power(xhci, xhci->shared_hcd, i, false, &flags);
+
 	/* Workaround for spurious wakeups at shutdown with HSW */
 	if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 		xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
-	spin_unlock_irq(&xhci->lock);
+	spin_unlock_irqrestore(&xhci->lock, flags);
 
 	xhci_cleanup_msix(xhci);
 
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 0bd76c94a4b15..28aaf031f9a8b 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -2196,6 +2196,8 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
+void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd, u16 index,
+			 bool on, unsigned long *flags);
 
 void xhci_hc_died(struct xhci_hcd *xhci);
 
-- 
GitLab


From 7516da47a349e74de623243a27f9b8a91446bf4f Mon Sep 17 00:00:00 2001
From: Tanveer Alam <tanveer1.alam@intel.com>
Date: Thu, 23 Jun 2022 14:19:44 +0300
Subject: [PATCH 1051/1731] xhci-pci: Allow host runtime PM as default for
 Intel Raptor Lake xHCI

In the same way as Intel Alder Lake TCSS (Type-C Subsystem) the Raptor
Lake TCSS xHCI needs to be runtime suspended whenever possible to
allow the TCSS hardware block to enter D3cold and thus save energy.

Cc: stable@kernel.org
Signed-off-by: Tanveer Alam <tanveer1.alam@intel.com>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Link: https://lore.kernel.org/r/20220623111945.1557702-4-mathias.nyman@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/host/xhci-pci.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index fac9492a8bda0..d66ea276ccec2 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -61,6 +61,7 @@
 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI		0x461e
 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_XHCI		0x464e
 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI	0x51ed
+#define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_XHCI		0xa71e
 
 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI			0x1639
 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4			0x43b9
@@ -269,7 +270,8 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
 	     pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI ||
 	     pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI ||
 	     pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_XHCI ||
-	     pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI))
+	     pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI ||
+	     pdev->device == PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_XHCI))
 		xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 
 	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
-- 
GitLab


From 8ffdc53a60049f3930afe161dc51c67959c8d83d Mon Sep 17 00:00:00 2001
From: Utkarsh Patel <utkarsh.h.patel@intel.com>
Date: Thu, 23 Jun 2022 14:19:45 +0300
Subject: [PATCH 1052/1731] xhci-pci: Allow host runtime PM as default for
 Intel Meteor Lake xHCI

Meteor Lake TCSS(Type-C Subsystem) xHCI needs to be runtime suspended
whenever possible to allow the TCSS hardware block to enter D3cold and
thus save energy.

Cc: stable@kernel.org
Signed-off-by: Utkarsh Patel <utkarsh.h.patel@intel.com>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Link: https://lore.kernel.org/r/20220623111945.1557702-5-mathias.nyman@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/host/xhci-pci.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index d66ea276ccec2..dce6c0ec8d340 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -62,6 +62,7 @@
 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_XHCI		0x464e
 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI	0x51ed
 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_XHCI		0xa71e
+#define PCI_DEVICE_ID_INTEL_METEOR_LAKE_XHCI		0x7ec0
 
 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI			0x1639
 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4			0x43b9
@@ -271,7 +272,8 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
 	     pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI ||
 	     pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_XHCI ||
 	     pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI ||
-	     pdev->device == PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_XHCI))
+	     pdev->device == PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_XHCI ||
+	     pdev->device == PCI_DEVICE_ID_INTEL_METEOR_LAKE_XHCI))
 		xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 
 	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
-- 
GitLab


From 9ca766eaea2e87b8b773bff04ee56c055cb76d4e Mon Sep 17 00:00:00 2001
From: Dan Carpenter <dan.carpenter@oracle.com>
Date: Thu, 23 Jun 2022 11:29:48 +0300
Subject: [PATCH 1053/1731] gpio: winbond: Fix error code in winbond_gpio_get()

This error path returns 1, but it should instead propagate the negative
error code from winbond_sio_enter().

Fixes: a0d65009411c ("gpio: winbond: Add driver")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
---
 drivers/gpio/gpio-winbond.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpio/gpio-winbond.c b/drivers/gpio/gpio-winbond.c
index 7f8f5b02e31d5..4b61d975cc0ec 100644
--- a/drivers/gpio/gpio-winbond.c
+++ b/drivers/gpio/gpio-winbond.c
@@ -385,12 +385,13 @@ static int winbond_gpio_get(struct gpio_chip *gc, unsigned int offset)
 	unsigned long *base = gpiochip_get_data(gc);
 	const struct winbond_gpio_info *info;
 	bool val;
+	int ret;
 
 	winbond_gpio_get_info(&offset, &info);
 
-	val = winbond_sio_enter(*base);
-	if (val)
-		return val;
+	ret = winbond_sio_enter(*base);
+	if (ret)
+		return ret;
 
 	winbond_sio_select_logical(*base, info->dev);
 
-- 
GitLab


From e70b64a3f28b9f54602ae3e706b1dc1338de3df7 Mon Sep 17 00:00:00 2001
From: Dylan Yudaken <dylany@fb.com>
Date: Thu, 23 Jun 2022 01:37:43 -0700
Subject: [PATCH 1054/1731] io_uring: move io_uring_get_opcode out of TP_printk

The TP_printk macro's are not supposed to use custom code ([1]) or else
tools such as perf cannot use these events.

Convert the opcode string representation to use the __string wiring that
the event framework provides ([2]).

[1]: https://lwn.net/Articles/379903/
[2]: https://lwn.net/Articles/381064/

Fixes: 033b87d24f72 ("io_uring: use the text representation of ops in trace")
Signed-off-by: Dylan Yudaken <dylany@fb.com>
Link: https://lore.kernel.org/r/20220623083743.2648321-1-dylany@fb.com
[axboe: fixup spurious removal of sq_thread assignment]
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 include/trace/events/io_uring.h | 42 +++++++++++++++++++++++++++------
 1 file changed, 35 insertions(+), 7 deletions(-)

diff --git a/include/trace/events/io_uring.h b/include/trace/events/io_uring.h
index 66fcc5a1a5b1c..aa2f951b07cdf 100644
--- a/include/trace/events/io_uring.h
+++ b/include/trace/events/io_uring.h
@@ -158,6 +158,8 @@ TRACE_EVENT(io_uring_queue_async_work,
 		__field(  unsigned int,			flags		)
 		__field(  struct io_wq_work *,		work		)
 		__field(  int,				rw		)
+
+		__string( op_str, io_uring_get_opcode(opcode)	)
 	),
 
 	TP_fast_assign(
@@ -168,11 +170,13 @@ TRACE_EVENT(io_uring_queue_async_work,
 		__entry->opcode		= opcode;
 		__entry->work		= work;
 		__entry->rw		= rw;
+
+		__assign_str(op_str, io_uring_get_opcode(opcode));
 	),
 
 	TP_printk("ring %p, request %p, user_data 0x%llx, opcode %s, flags 0x%x, %s queue, work %p",
 		__entry->ctx, __entry->req, __entry->user_data,
-		io_uring_get_opcode(__entry->opcode),
+		__get_str(op_str),
 		__entry->flags, __entry->rw ? "hashed" : "normal", __entry->work)
 );
 
@@ -198,6 +202,8 @@ TRACE_EVENT(io_uring_defer,
 		__field(  void *,		req	)
 		__field(  unsigned long long,	data	)
 		__field(  u8,			opcode	)
+
+		__string( op_str, io_uring_get_opcode(opcode) )
 	),
 
 	TP_fast_assign(
@@ -205,11 +211,13 @@ TRACE_EVENT(io_uring_defer,
 		__entry->req	= req;
 		__entry->data	= user_data;
 		__entry->opcode	= opcode;
+
+		__assign_str(op_str, io_uring_get_opcode(opcode));
 	),
 
 	TP_printk("ring %p, request %p, user_data 0x%llx, opcode %s",
 		__entry->ctx, __entry->req, __entry->data,
-		io_uring_get_opcode(__entry->opcode))
+		__get_str(op_str))
 );
 
 /**
@@ -298,6 +306,8 @@ TRACE_EVENT(io_uring_fail_link,
 		__field(  unsigned long long,	user_data	)
 		__field(  u8,			opcode		)
 		__field(  void *,		link		)
+
+		__string( op_str, io_uring_get_opcode(opcode) )
 	),
 
 	TP_fast_assign(
@@ -306,11 +316,13 @@ TRACE_EVENT(io_uring_fail_link,
 		__entry->user_data	= user_data;
 		__entry->opcode		= opcode;
 		__entry->link		= link;
+
+		__assign_str(op_str, io_uring_get_opcode(opcode));
 	),
 
 	TP_printk("ring %p, request %p, user_data 0x%llx, opcode %s, link %p",
 		__entry->ctx, __entry->req, __entry->user_data,
-		io_uring_get_opcode(__entry->opcode), __entry->link)
+		__get_str(op_str), __entry->link)
 );
 
 /**
@@ -390,6 +402,8 @@ TRACE_EVENT(io_uring_submit_sqe,
 		__field(  u32,			flags		)
 		__field(  bool,			force_nonblock	)
 		__field(  bool,			sq_thread	)
+
+		__string( op_str, io_uring_get_opcode(opcode) )
 	),
 
 	TP_fast_assign(
@@ -400,11 +414,13 @@ TRACE_EVENT(io_uring_submit_sqe,
 		__entry->flags		= flags;
 		__entry->force_nonblock	= force_nonblock;
 		__entry->sq_thread	= sq_thread;
+
+		__assign_str(op_str, io_uring_get_opcode(opcode));
 	),
 
 	TP_printk("ring %p, req %p, user_data 0x%llx, opcode %s, flags 0x%x, "
 		  "non block %d, sq_thread %d", __entry->ctx, __entry->req,
-		  __entry->user_data, io_uring_get_opcode(__entry->opcode),
+		  __entry->user_data, __get_str(op_str),
 		  __entry->flags, __entry->force_nonblock, __entry->sq_thread)
 );
 
@@ -435,6 +451,8 @@ TRACE_EVENT(io_uring_poll_arm,
 		__field(  u8,			opcode		)
 		__field(  int,			mask		)
 		__field(  int,			events		)
+
+		__string( op_str, io_uring_get_opcode(opcode) )
 	),
 
 	TP_fast_assign(
@@ -444,11 +462,13 @@ TRACE_EVENT(io_uring_poll_arm,
 		__entry->opcode		= opcode;
 		__entry->mask		= mask;
 		__entry->events		= events;
+
+		__assign_str(op_str, io_uring_get_opcode(opcode));
 	),
 
 	TP_printk("ring %p, req %p, user_data 0x%llx, opcode %s, mask 0x%x, events 0x%x",
 		  __entry->ctx, __entry->req, __entry->user_data,
-		  io_uring_get_opcode(__entry->opcode),
+		  __get_str(op_str),
 		  __entry->mask, __entry->events)
 );
 
@@ -474,6 +494,8 @@ TRACE_EVENT(io_uring_task_add,
 		__field(  unsigned long long,	user_data	)
 		__field(  u8,			opcode		)
 		__field(  int,			mask		)
+
+		__string( op_str, io_uring_get_opcode(opcode) )
 	),
 
 	TP_fast_assign(
@@ -482,11 +504,13 @@ TRACE_EVENT(io_uring_task_add,
 		__entry->user_data	= user_data;
 		__entry->opcode		= opcode;
 		__entry->mask		= mask;
+
+		__assign_str(op_str, io_uring_get_opcode(opcode));
 	),
 
 	TP_printk("ring %p, req %p, user_data 0x%llx, opcode %s, mask %x",
 		__entry->ctx, __entry->req, __entry->user_data,
-		io_uring_get_opcode(__entry->opcode),
+		__get_str(op_str),
 		__entry->mask)
 );
 
@@ -523,6 +547,8 @@ TRACE_EVENT(io_uring_req_failed,
 		__field( u64,			pad1		)
 		__field( u64,			addr3		)
 		__field( int,			error		)
+
+		__string( op_str, io_uring_get_opcode(sqe->opcode) )
 	),
 
 	TP_fast_assign(
@@ -542,6 +568,8 @@ TRACE_EVENT(io_uring_req_failed,
 		__entry->pad1		= sqe->__pad2[0];
 		__entry->addr3		= sqe->addr3;
 		__entry->error		= error;
+
+		__assign_str(op_str, io_uring_get_opcode(sqe->opcode));
 	),
 
 	TP_printk("ring %p, req %p, user_data 0x%llx, "
@@ -550,7 +578,7 @@ TRACE_EVENT(io_uring_req_failed,
 		  "personality=%d, file_index=%d, pad=0x%llx, addr3=%llx, "
 		  "error=%d",
 		  __entry->ctx, __entry->req, __entry->user_data,
-		  io_uring_get_opcode(__entry->opcode),
+		  __get_str(op_str),
 		  __entry->flags, __entry->ioprio,
 		  (unsigned long long)__entry->off,
 		  (unsigned long long) __entry->addr, __entry->len,
-- 
GitLab


From c1c2a15c2b5379ea8e44dcdcc298e3de42076ba0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Tue, 21 Jun 2022 08:40:36 +0200
Subject: [PATCH 1055/1731] gpio: grgpio: Fix device removing
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

If a platform device's remove callback returns non-zero, the device core
emits a warning and still removes the device and calls the devm cleanup
callbacks.

So it's not save to not unregister the gpiochip because on the next request
to a GPIO the driver accesses kfree()'d memory. Also if an IRQ triggers,
the freed memory is accessed.

Instead rely on the GPIO framework to ensure that after gpiochip_remove()
all GPIOs are freed and so the corresponding IRQs are unmapped.

This is a preparation for making platform remove callbacks return void.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
---
 drivers/gpio/gpio-grgpio.c | 14 +-------------
 1 file changed, 1 insertion(+), 13 deletions(-)

diff --git a/drivers/gpio/gpio-grgpio.c b/drivers/gpio/gpio-grgpio.c
index df563616f943f..bea0e32c195d4 100644
--- a/drivers/gpio/gpio-grgpio.c
+++ b/drivers/gpio/gpio-grgpio.c
@@ -434,25 +434,13 @@ static int grgpio_probe(struct platform_device *ofdev)
 static int grgpio_remove(struct platform_device *ofdev)
 {
 	struct grgpio_priv *priv = platform_get_drvdata(ofdev);
-	int i;
-	int ret = 0;
-
-	if (priv->domain) {
-		for (i = 0; i < GRGPIO_MAX_NGPIO; i++) {
-			if (priv->uirqs[i].refcnt != 0) {
-				ret = -EBUSY;
-				goto out;
-			}
-		}
-	}
 
 	gpiochip_remove(&priv->gc);
 
 	if (priv->domain)
 		irq_domain_remove(priv->domain);
 
-out:
-	return ret;
+	return 0;
 }
 
 static const struct of_device_id grgpio_match[] = {
-- 
GitLab


From 373269ae6f90bbbe945abde4c0811a991a27901a Mon Sep 17 00:00:00 2001
From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Date: Wed, 22 Jun 2022 15:11:04 +0100
Subject: [PATCH 1056/1731] drm/i915/selftests: Increase timeout for
 live_parallel_switch

With GuC submission, it takes a little bit longer switching contexts
among all available engines simultaneously, when running
live_parallel_switch subtest. Increase the timeout.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5885
Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220622141104.334432-1-matthew.auld@intel.com
---
 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 93a67422ca3b1..c6ad67b90e8af 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -212,7 +212,7 @@ static int __live_parallel_switch1(void *data)
 
 			i915_request_add(rq);
 		}
-		if (i915_request_wait(rq, 0, HZ / 5) < 0)
+		if (i915_request_wait(rq, 0, HZ) < 0)
 			err = -ETIME;
 		i915_request_put(rq);
 		if (err)
-- 
GitLab


From cc02e6e21aa5f2ac0defe8c15e5a9d024da6e73d Mon Sep 17 00:00:00 2001
From: Alexander Gordeev <agordeev@linux.ibm.com>
Date: Fri, 10 Jun 2022 11:04:36 +0200
Subject: [PATCH 1057/1731] s390/crash: add missing iterator advance in
 copy_oldmem_page()

In case old memory was successfully copied the passed iterator
should be advanced as well. Currently copy_oldmem_page() is
always called with single-segment iterator. Should that ever
change - copy_oldmem_user and copy_oldmem_kernel() functions
would need a rework to deal with multi-segment iterators.

Fixes: 5d8de293c224 ("vmcore: convert copy_oldmem_page() to take an iov_iter")
Reviewed-by: Alexander Egorenkov <egorenar@linux.ibm.com>
Tested-by: Alexander Egorenkov <egorenar@linux.ibm.com>
Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
---
 arch/s390/kernel/crash_dump.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/s390/kernel/crash_dump.c b/arch/s390/kernel/crash_dump.c
index a2c1c55daec03..2534a31d25502 100644
--- a/arch/s390/kernel/crash_dump.c
+++ b/arch/s390/kernel/crash_dump.c
@@ -219,6 +219,11 @@ ssize_t copy_oldmem_page(struct iov_iter *iter, unsigned long pfn, size_t csize,
 	unsigned long src;
 	int rc;
 
+	if (!(iter_is_iovec(iter) || iov_iter_is_kvec(iter)))
+		return -EINVAL;
+	/* Multi-segment iterators are not supported */
+	if (iter->nr_segs > 1)
+		return -EINVAL;
 	if (!csize)
 		return 0;
 	src = pfn_to_phys(pfn) + offset;
@@ -228,6 +233,8 @@ ssize_t copy_oldmem_page(struct iov_iter *iter, unsigned long pfn, size_t csize,
 		rc = copy_oldmem_user(iter->iov->iov_base, src, csize);
 	else
 		rc = copy_oldmem_kernel(iter->kvec->iov_base, src, csize);
+	if (!rc)
+		iov_iter_advance(iter, csize);
 	return rc;
 }
 
-- 
GitLab


From af2debd58bd769e38f538143f0d332e15d753396 Mon Sep 17 00:00:00 2001
From: Alexander Gordeev <agordeev@linux.ibm.com>
Date: Thu, 9 Jun 2022 21:32:39 +0200
Subject: [PATCH 1058/1731] s390/crash: make copy_oldmem_page() return number
 of bytes copied

Callback copy_oldmem_page() returns either error code or zero.
Instead, it should return the error code or number of bytes copied.

Fixes: df9694c7975f ("s390/dump: streamline oldmem copy functions")
Reviewed-by: Alexander Egorenkov <egorenar@linux.ibm.com>
Tested-by: Alexander Egorenkov <egorenar@linux.ibm.com>
Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
---
 arch/s390/kernel/crash_dump.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/s390/kernel/crash_dump.c b/arch/s390/kernel/crash_dump.c
index 2534a31d25502..28124d0fa1d5e 100644
--- a/arch/s390/kernel/crash_dump.c
+++ b/arch/s390/kernel/crash_dump.c
@@ -233,9 +233,10 @@ ssize_t copy_oldmem_page(struct iov_iter *iter, unsigned long pfn, size_t csize,
 		rc = copy_oldmem_user(iter->iov->iov_base, src, csize);
 	else
 		rc = copy_oldmem_kernel(iter->kvec->iov_base, src, csize);
-	if (!rc)
-		iov_iter_advance(iter, csize);
-	return rc;
+	if (rc < 0)
+		return rc;
+	iov_iter_advance(iter, csize);
+	return csize;
 }
 
 /*
-- 
GitLab


From be857b7f77d130dbbd47c91fc35198b040f35865 Mon Sep 17 00:00:00 2001
From: Thomas Richter <tmricht@linux.ibm.com>
Date: Fri, 10 Jun 2022 15:19:00 +0200
Subject: [PATCH 1059/1731] s390/cpumf: Handle events cycles and instructions
 identical

Events CPU_CYCLES and INSTRUCTIONS can be submitted with two different
perf_event attribute::type values:
 - PERF_TYPE_HARDWARE: when invoked via perf tool predefined events name
   cycles or cpu-cycles or instructions.
 - pmu->type: when invoked via perf tool event name cpu_cf/CPU_CYLCES/ or
   cpu_cf/INSTRUCTIONS/. This invocation also selects the PMU to which
   the event belongs.
Handle both type of invocations identical for events CPU_CYLCES and
INSTRUCTIONS. They address the same hardware.
The result is different when event modifier exclude_kernel is also set.
Invocation with event modifier for user space event counting fails.

Output before:

 # perf stat -e cpum_cf/cpu_cycles/u -- true

 Performance counter stats for 'true':

   <not supported>      cpum_cf/cpu_cycles/u

       0.000761033 seconds time elapsed

       0.000076000 seconds user
       0.000725000 seconds sys

 #

Output after:
 # perf stat -e cpum_cf/cpu_cycles/u -- true

 Performance counter stats for 'true':

           349,613      cpum_cf/cpu_cycles/u

       0.000844143 seconds time elapsed

       0.000079000 seconds user
       0.000800000 seconds sys
 #

Fixes: 6a82e23f45fe ("s390/cpumf: Adjust registration of s390 PMU device drivers")
Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
Acked-by: Sumanth Korikkar <sumanthk@linux.ibm.com>
[agordeev@linux.ibm.com corrected commit ID of Fixes commit]
Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
---
 arch/s390/kernel/perf_cpum_cf.c | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/arch/s390/kernel/perf_cpum_cf.c b/arch/s390/kernel/perf_cpum_cf.c
index 483ab5e10164d..f7dd3c849e68c 100644
--- a/arch/s390/kernel/perf_cpum_cf.c
+++ b/arch/s390/kernel/perf_cpum_cf.c
@@ -516,6 +516,26 @@ static int __hw_perf_event_init(struct perf_event *event, unsigned int type)
 	return err;
 }
 
+/* Events CPU_CYLCES and INSTRUCTIONS can be submitted with two different
+ * attribute::type values:
+ * - PERF_TYPE_HARDWARE:
+ * - pmu->type:
+ * Handle both type of invocations identical. They address the same hardware.
+ * The result is different when event modifiers exclude_kernel and/or
+ * exclude_user are also set.
+ */
+static int cpumf_pmu_event_type(struct perf_event *event)
+{
+	u64 ev = event->attr.config;
+
+	if (cpumf_generic_events_basic[PERF_COUNT_HW_CPU_CYCLES] == ev ||
+	    cpumf_generic_events_basic[PERF_COUNT_HW_INSTRUCTIONS] == ev ||
+	    cpumf_generic_events_user[PERF_COUNT_HW_CPU_CYCLES] == ev ||
+	    cpumf_generic_events_user[PERF_COUNT_HW_INSTRUCTIONS] == ev)
+		return PERF_TYPE_HARDWARE;
+	return PERF_TYPE_RAW;
+}
+
 static int cpumf_pmu_event_init(struct perf_event *event)
 {
 	unsigned int type = event->attr.type;
@@ -525,7 +545,7 @@ static int cpumf_pmu_event_init(struct perf_event *event)
 		err = __hw_perf_event_init(event, type);
 	else if (event->pmu->type == type)
 		/* Registered as unknown PMU */
-		err = __hw_perf_event_init(event, PERF_TYPE_RAW);
+		err = __hw_perf_event_init(event, cpumf_pmu_event_type(event));
 	else
 		return -ENOENT;
 
-- 
GitLab


From 541a496644512ebed429b33f19a3fadfb19c6ee7 Mon Sep 17 00:00:00 2001
From: Thomas Richter <tmricht@linux.ibm.com>
Date: Tue, 14 Jun 2022 12:40:46 +0200
Subject: [PATCH 1060/1731] s390/pai: Prevent invalid event number for
 pai_crypto PMU

The pai_crypto PMU has to check the event number. It has to be in
the supported range. This is not the case, the lower limit is not
checked. Fix this and obey the lower limit.

Fixes: 39d62336f5c1 ("s390/pai: add support for cryptography counters")

Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
Suggested-by: Sumanth Korikkar <sumanthk@linux.ibm.com>
Reviewed-by: Sumanth Korikkar <sumanthk@linux.ibm.com>
Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
---
 arch/s390/kernel/perf_pai_crypto.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/s390/kernel/perf_pai_crypto.c b/arch/s390/kernel/perf_pai_crypto.c
index 8c1545946d85e..188c6cf09c7a2 100644
--- a/arch/s390/kernel/perf_pai_crypto.c
+++ b/arch/s390/kernel/perf_pai_crypto.c
@@ -193,8 +193,9 @@ static int paicrypt_event_init(struct perf_event *event)
 	/* PAI crypto PMU registered as PERF_TYPE_RAW, check event type */
 	if (a->type != PERF_TYPE_RAW && event->pmu->type != a->type)
 		return -ENOENT;
-	/* PAI crypto event must be valid */
-	if (a->config > PAI_CRYPTO_BASE + paicrypt_cnt)
+	/* PAI crypto event must be in valid range */
+	if (a->config < PAI_CRYPTO_BASE ||
+	    a->config > PAI_CRYPTO_BASE + paicrypt_cnt)
 		return -EINVAL;
 	/* Allow only CPU wide operation, no process context for now. */
 	if (event->hw.target || event->cpu == -1)
-- 
GitLab


From 21e876448792af2dd5261338907c72bdf37fa056 Mon Sep 17 00:00:00 2001
From: Thomas Richter <tmricht@linux.ibm.com>
Date: Wed, 15 Jun 2022 14:02:07 +0200
Subject: [PATCH 1061/1731] s390/pai: Fix multiple concurrent event
 installation

Two different events such as pai_crypto/KM_AES_128/ and
pai_crypto/KM_AES_192/ can be installed multiple times on the same CPU
and the events are executed concurrently:

  # perf stat -e pai_crypto/KM_AES_128/  -C0 -a -- sleep 5 &
  # sleep 2
  # perf stat -e pai_crypto/KM_AES_192/ -C0 -a -- true

This results in the first event being installed two times with two seconds
delay. The kernel does install the second event after the first
event has been deleted and re-added, as can be seen in the traces:

 13:48:47.600350  paicrypt_start event 0x1007 (event KM_AES_128)
 13:48:49.599359  paicrypt_stop event 0x1007  (event KM_AES_128)
 13:48:49.599198  paicrypt_start event 0x1007
 13:48:49.599199  paicrypt_start event 0x1008
 13:48:49.599921  paicrypt_event_destroy event 0x1008
 13:48:52.601507  paicrypt_event_destroy event 0x1007

This is caused by functions event_sched_in() and event_sched_out() which
call the PMU's add() and start() functions on schedule_in and the PMU's
stop() and del() functions on schedule_out. This is correct for events
attached to processes.  The pai_crypto events are system-wide events
and not attached to processes.

Since the kernel common code can not be changed easily, fix this issue
and do not reset the event count value to zero each time the event is
added and started. Instead use a flag and zero the event count value
only when called immediately after the event has been initialized.
Therefore only the first invocation of the the event's add() function
initializes the event count value to zero. The following invocations
of the event's add() function leave the current event count value
untouched.

Fixes: 39d62336f5c1 ("s390/pai: add support for cryptography counters")

Reported-by: Sumanth Korikkar <sumanthk@linux.ibm.com>
Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
Acked-by: Sumanth Korikkar <sumanthk@linux.ibm.com>
Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
---
 arch/s390/kernel/perf_pai_crypto.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/s390/kernel/perf_pai_crypto.c b/arch/s390/kernel/perf_pai_crypto.c
index 188c6cf09c7a2..b38b4ae01589b 100644
--- a/arch/s390/kernel/perf_pai_crypto.c
+++ b/arch/s390/kernel/perf_pai_crypto.c
@@ -209,6 +209,12 @@ static int paicrypt_event_init(struct perf_event *event)
 	if (rc)
 		return rc;
 
+	/* Event initialization sets last_tag to 0. When later on the events
+	 * are deleted and re-added, do not reset the event count value to zero.
+	 * Events are added, deleted and re-added when 2 or more events
+	 * are active at the same time.
+	 */
+	event->hw.last_tag = 0;
 	cpump->event = event;
 	event->destroy = paicrypt_event_destroy;
 
@@ -243,9 +249,12 @@ static void paicrypt_start(struct perf_event *event, int flags)
 {
 	u64 sum;
 
-	sum = paicrypt_getall(event);		/* Get current value */
-	local64_set(&event->hw.prev_count, sum);
-	local64_set(&event->count, 0);
+	if (!event->hw.last_tag) {
+		event->hw.last_tag = 1;
+		sum = paicrypt_getall(event);		/* Get current value */
+		local64_set(&event->count, 0);
+		local64_set(&event->hw.prev_count, sum);
+	}
 }
 
 static int paicrypt_add(struct perf_event *event, int flags)
-- 
GitLab


From b653db77350c7307a513b81856fe53e94cf42446 Mon Sep 17 00:00:00 2001
From: "Matthew Wilcox (Oracle)" <willy@infradead.org>
Date: Sun, 19 Jun 2022 10:37:32 -0400
Subject: [PATCH 1062/1731] mm: Clear page->private when splitting or migrating
 a page

In our efforts to remove uses of PG_private, we have found folios with
the private flag clear and folio->private not-NULL.  That is the root
cause behind 642d51fb0775 ("ceph: check folio PG_private bit instead
of folio->private").  It can also affect a few other filesystems that
haven't yet reported a problem.

compaction_alloc() can return a page with uninitialised page->private,
and rather than checking all the callers of migrate_pages(), just zero
page->private after calling get_new_page().  Similarly, the tail pages
from split_huge_page() may also have an uninitialised page->private.

Reported-by: Xiubo Li <xiubli@redhat.com>
Tested-by: Xiubo Li <xiubli@redhat.com>
Signed-off-by: Matthew Wilcox (Oracle) <willy@infradead.org>
---
 mm/huge_memory.c | 1 +
 mm/migrate.c     | 1 +
 2 files changed, 2 insertions(+)

diff --git a/mm/huge_memory.c b/mm/huge_memory.c
index f7248002dad98..834f288b37690 100644
--- a/mm/huge_memory.c
+++ b/mm/huge_memory.c
@@ -2377,6 +2377,7 @@ static void __split_huge_page_tail(struct page *head, int tail,
 			page_tail);
 	page_tail->mapping = head->mapping;
 	page_tail->index = head->index + tail;
+	page_tail->private = 0;
 
 	/* Page flags must be visible before we make the page non-compound. */
 	smp_wmb();
diff --git a/mm/migrate.c b/mm/migrate.c
index e51588e95f573..6c1ea61f39d80 100644
--- a/mm/migrate.c
+++ b/mm/migrate.c
@@ -1106,6 +1106,7 @@ static int unmap_and_move(new_page_t get_new_page,
 	if (!newpage)
 		return -ENOMEM;
 
+	newpage->private = 0;
 	rc = __unmap_and_move(page, newpage, force, mode);
 	if (rc == MIGRATEPAGE_SUCCESS)
 		set_page_owner_migrate_reason(newpage, reason);
-- 
GitLab


From 00fa15e0d56482e32d8ca1f51d76b0ee00afb16b Mon Sep 17 00:00:00 2001
From: Alistair Popple <apopple@nvidia.com>
Date: Mon, 20 Jun 2022 19:05:36 +1000
Subject: [PATCH 1063/1731] filemap: Fix serialization adding transparent huge
 pages to page cache

Commit 793917d997df ("mm/readahead: Add large folio readahead")
introduced support for using large folios for filebacked pages if the
filesystem supports it.

page_cache_ra_order() was introduced to allocate and add these large
folios to the page cache. However adding pages to the page cache should
be serialized against truncation and hole punching by taking
invalidate_lock. Not doing so can lead to data races resulting in stale
data getting added to the page cache and marked up-to-date. See commit
730633f0b7f9 ("mm: Protect operations adding pages to page cache with
invalidate_lock") for more details.

This issue was found by inspection but a testcase revealed it was
possible to observe in practice on XFS. Fix this by taking
invalidate_lock in page_cache_ra_order(), to mirror what is done for the
non-thp case in page_cache_ra_unbounded().

Signed-off-by: Alistair Popple <apopple@nvidia.com>
Fixes: 793917d997df ("mm/readahead: Add large folio readahead")
Reviewed-by: Jan Kara <jack@suse.cz>
Signed-off-by: Matthew Wilcox (Oracle) <willy@infradead.org>
---
 mm/readahead.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/mm/readahead.c b/mm/readahead.c
index 57a0151082543..fdcd28cbd92de 100644
--- a/mm/readahead.c
+++ b/mm/readahead.c
@@ -510,6 +510,7 @@ void page_cache_ra_order(struct readahead_control *ractl,
 			new_order--;
 	}
 
+	filemap_invalidate_lock_shared(mapping);
 	while (index <= limit) {
 		unsigned int order = new_order;
 
@@ -536,6 +537,7 @@ void page_cache_ra_order(struct readahead_control *ractl,
 	}
 
 	read_pages(ractl);
+	filemap_invalidate_unlock_shared(mapping);
 
 	/*
 	 * If there were already pages in the page cache, then we may have
-- 
GitLab


From 20fb0c8272bbb102d15bdd11aa64f828619dd7cc Mon Sep 17 00:00:00 2001
From: Petr Mladek <pmladek@suse.com>
Date: Thu, 23 Jun 2022 16:51:52 +0200
Subject: [PATCH 1064/1731] Revert "printk: Wait for the global console lock
 when the system is going down"

This reverts commit b87f02307d3cfbda768520f0687c51ca77e14fc3.

The testing of 5.19 release candidates revealed missing synchronization
between early and regular console functionality.

It would be possible to start the console kthreads later as a workaround.
But it is clear that console lock serialized console drivers between
each other. It opens a big area of possible problems that were not
considered by people involved in the development and review.

printk() is crucial for debugging kernel issues and console output is
very important part of it. The number of consoles is huge and a proper
review would take some time. As a result it need to be reverted for 5.19.

Link: https://lore.kernel.org/r/YrBdjVwBOVgLfHyb@alley
Signed-off-by: Petr Mladek <pmladek@suse.com>
Link: https://lore.kernel.org/r/20220623145157.21938-2-pmladek@suse.com
---
 include/linux/printk.h      |  5 -----
 kernel/panic.c              |  2 --
 kernel/printk/internal.h    |  2 --
 kernel/printk/printk.c      |  4 ----
 kernel/printk/printk_safe.c | 32 --------------------------------
 kernel/reboot.c             |  2 --
 6 files changed, 47 deletions(-)

diff --git a/include/linux/printk.h b/include/linux/printk.h
index c1e07c0652c7c..cd26aab0ab2a0 100644
--- a/include/linux/printk.h
+++ b/include/linux/printk.h
@@ -174,7 +174,6 @@ extern void printk_prefer_direct_enter(void);
 extern void printk_prefer_direct_exit(void);
 
 extern bool pr_flush(int timeout_ms, bool reset_on_progress);
-extern void try_block_console_kthreads(int timeout_ms);
 
 /*
  * Please don't use printk_ratelimit(), because it shares ratelimiting state
@@ -239,10 +238,6 @@ static inline bool pr_flush(int timeout_ms, bool reset_on_progress)
 	return true;
 }
 
-static inline void try_block_console_kthreads(int timeout_ms)
-{
-}
-
 static inline int printk_ratelimit(void)
 {
 	return 0;
diff --git a/kernel/panic.c b/kernel/panic.c
index fe73d18ecdf02..6737b23322753 100644
--- a/kernel/panic.c
+++ b/kernel/panic.c
@@ -273,7 +273,6 @@ void panic(const char *fmt, ...)
 		 * unfortunately means it may not be hardened to work in a
 		 * panic situation.
 		 */
-		try_block_console_kthreads(10000);
 		smp_send_stop();
 	} else {
 		/*
@@ -281,7 +280,6 @@ void panic(const char *fmt, ...)
 		 * kmsg_dump, we will need architecture dependent extra
 		 * works in addition to stopping other CPUs.
 		 */
-		try_block_console_kthreads(10000);
 		crash_smp_send_stop();
 	}
 
diff --git a/kernel/printk/internal.h b/kernel/printk/internal.h
index e7d8578860adf..d947ca6c84f99 100644
--- a/kernel/printk/internal.h
+++ b/kernel/printk/internal.h
@@ -20,8 +20,6 @@ enum printk_info_flags {
 	LOG_CONT	= 8,	/* text is a fragment of a continuation line */
 };
 
-extern bool block_console_kthreads;
-
 __printf(4, 0)
 int vprintk_store(int facility, int level,
 		  const struct dev_printk_info *dev_info,
diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c
index b095fb5f5f61b..45c6c2b0b1044 100644
--- a/kernel/printk/printk.c
+++ b/kernel/printk/printk.c
@@ -250,9 +250,6 @@ static atomic_t console_kthreads_active = ATOMIC_INIT(0);
 #define console_kthread_printing_exit() \
 	atomic_dec(&console_kthreads_active)
 
-/* Block console kthreads to avoid processing new messages. */
-bool block_console_kthreads;
-
 /*
  * Helper macros to handle lockdep when locking/unlocking console_sem. We use
  * macros instead of functions so that _RET_IP_ contains useful information.
@@ -3733,7 +3730,6 @@ static bool printer_should_wake(struct console *con, u64 seq)
 
 	if (con->blocked ||
 	    console_kthreads_atomically_blocked() ||
-	    block_console_kthreads ||
 	    system_state > SYSTEM_RUNNING ||
 	    oops_in_progress) {
 		return false;
diff --git a/kernel/printk/printk_safe.c b/kernel/printk/printk_safe.c
index caac4de1ea59a..ef0f9a2044da1 100644
--- a/kernel/printk/printk_safe.c
+++ b/kernel/printk/printk_safe.c
@@ -8,9 +8,7 @@
 #include <linux/smp.h>
 #include <linux/cpumask.h>
 #include <linux/printk.h>
-#include <linux/console.h>
 #include <linux/kprobes.h>
-#include <linux/delay.h>
 
 #include "internal.h"
 
@@ -52,33 +50,3 @@ asmlinkage int vprintk(const char *fmt, va_list args)
 	return vprintk_default(fmt, args);
 }
 EXPORT_SYMBOL(vprintk);
-
-/**
- * try_block_console_kthreads() - Try to block console kthreads and
- *	make the global console_lock() avaialble
- *
- * @timeout_ms:        The maximum time (in ms) to wait.
- *
- * Prevent console kthreads from starting processing new messages. Wait
- * until the global console_lock() become available.
- *
- * Context: Can be called in any context.
- */
-void try_block_console_kthreads(int timeout_ms)
-{
-	block_console_kthreads = true;
-
-	/* Do not wait when the console lock could not be safely taken. */
-	if (this_cpu_read(printk_context) || in_nmi())
-		return;
-
-	while (timeout_ms > 0) {
-		if (console_trylock()) {
-			console_unlock();
-			return;
-		}
-
-		udelay(1000);
-		timeout_ms -= 1;
-	}
-}
diff --git a/kernel/reboot.c b/kernel/reboot.c
index 3103636855020..4177645e74d6a 100644
--- a/kernel/reboot.c
+++ b/kernel/reboot.c
@@ -74,7 +74,6 @@ void kernel_restart_prepare(char *cmd)
 {
 	blocking_notifier_call_chain(&reboot_notifier_list, SYS_RESTART, cmd);
 	system_state = SYSTEM_RESTART;
-	try_block_console_kthreads(10000);
 	usermodehelper_disable();
 	device_shutdown();
 }
@@ -263,7 +262,6 @@ static void kernel_shutdown_prepare(enum system_states state)
 	blocking_notifier_call_chain(&reboot_notifier_list,
 		(state == SYSTEM_HALT) ? SYS_HALT : SYS_POWER_OFF, NULL);
 	system_state = state;
-	try_block_console_kthreads(10000);
 	usermodehelper_disable();
 	device_shutdown();
 }
-- 
GitLab


From 05c96b3713aa2a406d0c4ef0505bf80a6748fedb Mon Sep 17 00:00:00 2001
From: Petr Mladek <pmladek@suse.com>
Date: Thu, 23 Jun 2022 16:51:53 +0200
Subject: [PATCH 1065/1731] Revert "printk: Block console kthreads when direct
 printing will be required"

This reverts commit c3230283e2819a69dad2cf7a63143fde8bab8b5c.

The testing of 5.19 release candidates revealed missing synchronization
between early and regular console functionality.

It would be possible to start the console kthreads later as a workaround.
But it is clear that console lock serialized console drivers between
each other. It opens a big area of possible problems that were not
considered by people involved in the development and review.

printk() is crucial for debugging kernel issues and console output is
very important part of it. The number of consoles is huge and a proper
review would take some time. As a result it need to be reverted for 5.19.

Link: https://lore.kernel.org/r/YrBdjVwBOVgLfHyb@alley
Signed-off-by: Petr Mladek <pmladek@suse.com>
Link: https://lore.kernel.org/r/20220623145157.21938-3-pmladek@suse.com
---
 kernel/printk/printk.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c
index 45c6c2b0b1044..ea3dd55709e72 100644
--- a/kernel/printk/printk.c
+++ b/kernel/printk/printk.c
@@ -3729,9 +3729,7 @@ static bool printer_should_wake(struct console *con, u64 seq)
 		return true;
 
 	if (con->blocked ||
-	    console_kthreads_atomically_blocked() ||
-	    system_state > SYSTEM_RUNNING ||
-	    oops_in_progress) {
+	    console_kthreads_atomically_blocked()) {
 		return false;
 	}
 
-- 
GitLab


From 007eeab7e9f03a3108c300c03e11a6c151e430c9 Mon Sep 17 00:00:00 2001
From: Petr Mladek <pmladek@suse.com>
Date: Thu, 23 Jun 2022 16:51:54 +0200
Subject: [PATCH 1066/1731] Revert "printk: remove @console_locked"

This reverts commit ab406816fca009349b89cbde885daf68a8c77e33.

The testing of 5.19 release candidates revealed missing synchronization
between early and regular console functionality.

It would be possible to start the console kthreads later as a workaround.
But it is clear that console lock serialized console drivers between
each other. It opens a big area of possible problems that were not
considered by people involved in the development and review.

printk() is crucial for debugging kernel issues and console output is
very important part of it. The number of consoles is huge and a proper
review would take some time. As a result it need to be reverted for 5.19.

Link: https://lore.kernel.org/r/YrBdjVwBOVgLfHyb@alley
Signed-off-by: Petr Mladek <pmladek@suse.com>
Link: https://lore.kernel.org/r/20220623145157.21938-4-pmladek@suse.com
---
 kernel/printk/printk.c | 29 +++++++++++++++--------------
 1 file changed, 15 insertions(+), 14 deletions(-)

diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c
index ea3dd55709e72..dfd1a19b95d67 100644
--- a/kernel/printk/printk.c
+++ b/kernel/printk/printk.c
@@ -340,7 +340,15 @@ static void console_kthreads_unblock(void)
 	console_kthreads_blocked = false;
 }
 
-static int console_suspended;
+/*
+ * This is used for debugging the mess that is the VT code by
+ * keeping track if we have the console semaphore held. It's
+ * definitely not the perfect debug tool (we don't know if _WE_
+ * hold it and are racing, but it helps tracking those weird code
+ * paths in the console code where we end up in places I want
+ * locked without the console semaphore held).
+ */
+static int console_locked, console_suspended;
 
 /*
  *	Array of consoles built from command line options (console=)
@@ -2711,6 +2719,7 @@ void console_lock(void)
 	if (console_suspended)
 		return;
 	console_kthreads_block();
+	console_locked = 1;
 	console_may_schedule = 1;
 }
 EXPORT_SYMBOL(console_lock);
@@ -2735,26 +2744,15 @@ int console_trylock(void)
 		up_console_sem();
 		return 0;
 	}
+	console_locked = 1;
 	console_may_schedule = 0;
 	return 1;
 }
 EXPORT_SYMBOL(console_trylock);
 
-/*
- * This is used to help to make sure that certain paths within the VT code are
- * running with the console lock held. It is definitely not the perfect debug
- * tool (it is not known if the VT code is the task holding the console lock),
- * but it helps tracking those weird code paths in the console code such as
- * when the console is suspended: where the console is not locked but no
- * console printing may occur.
- *
- * Note: This returns true when the console is suspended but is not locked.
- *       This is intentional because the VT code must consider that situation
- *       the same as if the console was locked.
- */
 int is_console_locked(void)
 {
-	return (console_kthreads_blocked || atomic_read(&console_kthreads_active));
+	return (console_locked || atomic_read(&console_kthreads_active));
 }
 EXPORT_SYMBOL(is_console_locked);
 
@@ -2810,6 +2808,8 @@ static inline bool console_is_usable(struct console *con)
 
 static void __console_unlock(void)
 {
+	console_locked = 0;
+
 	/*
 	 * Depending on whether console_lock() or console_trylock() was used,
 	 * appropriately allow the kthread printers to continue.
@@ -3127,6 +3127,7 @@ void console_unblank(void)
 	} else
 		console_lock();
 
+	console_locked = 1;
 	console_may_schedule = 0;
 	for_each_console(c)
 		if ((c->flags & CON_ENABLED) && c->unblank)
-- 
GitLab


From 2d9ef940f89e0ab4fde7ba6f769d82f2a450c35a Mon Sep 17 00:00:00 2001
From: Petr Mladek <pmladek@suse.com>
Date: Thu, 23 Jun 2022 16:51:55 +0200
Subject: [PATCH 1067/1731] Revert "printk: extend console_lock for per-console
 locking"

This reverts commit 8e274732115f63c1d09136284431b3555bd5cc56.

The testing of 5.19 release candidates revealed missing synchronization
between early and regular console functionality.

It would be possible to start the console kthreads later as a workaround.
But it is clear that console lock serialized console drivers between
each other. It opens a big area of possible problems that were not
considered by people involved in the development and review.

printk() is crucial for debugging kernel issues and console output is
very important part of it. The number of consoles is huge and a proper
review would take some time. As a result it need to be reverted for 5.19.

Link: https://lore.kernel.org/r/YrBdjVwBOVgLfHyb@alley
Signed-off-by: Petr Mladek <pmladek@suse.com>
Link: https://lore.kernel.org/r/20220623145157.21938-5-pmladek@suse.com
---
 include/linux/console.h |  15 ---
 kernel/printk/printk.c  | 261 +++++++++-------------------------------
 2 files changed, 56 insertions(+), 220 deletions(-)

diff --git a/include/linux/console.h b/include/linux/console.h
index 143653090c480..9a251e70c090a 100644
--- a/include/linux/console.h
+++ b/include/linux/console.h
@@ -16,7 +16,6 @@
 
 #include <linux/atomic.h>
 #include <linux/types.h>
-#include <linux/mutex.h>
 
 struct vc_data;
 struct console_font_op;
@@ -155,20 +154,6 @@ struct console {
 	u64	seq;
 	unsigned long dropped;
 	struct task_struct *thread;
-	bool	blocked;
-
-	/*
-	 * The per-console lock is used by printing kthreads to synchronize
-	 * this console with callers of console_lock(). This is necessary in
-	 * order to allow printing kthreads to run in parallel to each other,
-	 * while each safely accessing the @blocked field and synchronizing
-	 * against direct printing via console_lock/console_unlock.
-	 *
-	 * Note: For synchronizing against direct printing via
-	 *       console_trylock/console_unlock, see the static global
-	 *       variable @console_kthreads_active.
-	 */
-	struct mutex lock;
 
 	void	*data;
 	struct	 console *next;
diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c
index dfd1a19b95d67..ae489dc685a1e 100644
--- a/kernel/printk/printk.c
+++ b/kernel/printk/printk.c
@@ -223,33 +223,6 @@ int devkmsg_sysctl_set_loglvl(struct ctl_table *table, int write,
 /* Number of registered extended console drivers. */
 static int nr_ext_console_drivers;
 
-/*
- * Used to synchronize printing kthreads against direct printing via
- * console_trylock/console_unlock.
- *
- * Values:
- * -1 = console kthreads atomically blocked (via global trylock)
- *  0 = no kthread printing, console not locked (via trylock)
- * >0 = kthread(s) actively printing
- *
- * Note: For synchronizing against direct printing via
- *       console_lock/console_unlock, see the @lock variable in
- *       struct console.
- */
-static atomic_t console_kthreads_active = ATOMIC_INIT(0);
-
-#define console_kthreads_atomic_tryblock() \
-	(atomic_cmpxchg(&console_kthreads_active, 0, -1) == 0)
-#define console_kthreads_atomic_unblock() \
-	atomic_cmpxchg(&console_kthreads_active, -1, 0)
-#define console_kthreads_atomically_blocked() \
-	(atomic_read(&console_kthreads_active) == -1)
-
-#define console_kthread_printing_tryenter() \
-	atomic_inc_unless_negative(&console_kthreads_active)
-#define console_kthread_printing_exit() \
-	atomic_dec(&console_kthreads_active)
-
 /*
  * Helper macros to handle lockdep when locking/unlocking console_sem. We use
  * macros instead of functions so that _RET_IP_ contains useful information.
@@ -297,49 +270,6 @@ static bool panic_in_progress(void)
 	return unlikely(atomic_read(&panic_cpu) != PANIC_CPU_INVALID);
 }
 
-/*
- * Tracks whether kthread printers are all blocked. A value of true implies
- * that the console is locked via console_lock() or the console is suspended.
- * Writing to this variable requires holding @console_sem.
- */
-static bool console_kthreads_blocked;
-
-/*
- * Block all kthread printers from a schedulable context.
- *
- * Requires holding @console_sem.
- */
-static void console_kthreads_block(void)
-{
-	struct console *con;
-
-	for_each_console(con) {
-		mutex_lock(&con->lock);
-		con->blocked = true;
-		mutex_unlock(&con->lock);
-	}
-
-	console_kthreads_blocked = true;
-}
-
-/*
- * Unblock all kthread printers from a schedulable context.
- *
- * Requires holding @console_sem.
- */
-static void console_kthreads_unblock(void)
-{
-	struct console *con;
-
-	for_each_console(con) {
-		mutex_lock(&con->lock);
-		con->blocked = false;
-		mutex_unlock(&con->lock);
-	}
-
-	console_kthreads_blocked = false;
-}
-
 /*
  * This is used for debugging the mess that is the VT code by
  * keeping track if we have the console semaphore held. It's
@@ -2673,6 +2603,13 @@ void resume_console(void)
 	down_console_sem();
 	console_suspended = 0;
 	console_unlock();
+
+	/*
+	 * While suspended, new records may have been added to the
+	 * ringbuffer. Wake up the kthread printers to print them.
+	 */
+	wake_up_klogd();
+
 	pr_flush(1000, true);
 }
 
@@ -2691,14 +2628,9 @@ static int console_cpu_notify(unsigned int cpu)
 		/* If trylock fails, someone else is doing the printing */
 		if (console_trylock())
 			console_unlock();
-		else {
-			/*
-			 * If a new CPU comes online, the conditions for
-			 * printer_should_wake() may have changed for some
-			 * kthread printer with !CON_ANYTIME.
-			 */
-			wake_up_klogd();
-		}
+
+		/* Wake kthread printers. Some may have become usable. */
+		wake_up_klogd();
 	}
 	return 0;
 }
@@ -2718,7 +2650,6 @@ void console_lock(void)
 	down_console_sem();
 	if (console_suspended)
 		return;
-	console_kthreads_block();
 	console_locked = 1;
 	console_may_schedule = 1;
 }
@@ -2740,10 +2671,6 @@ int console_trylock(void)
 		up_console_sem();
 		return 0;
 	}
-	if (!console_kthreads_atomic_tryblock()) {
-		up_console_sem();
-		return 0;
-	}
 	console_locked = 1;
 	console_may_schedule = 0;
 	return 1;
@@ -2752,7 +2679,7 @@ EXPORT_SYMBOL(console_trylock);
 
 int is_console_locked(void)
 {
-	return (console_locked || atomic_read(&console_kthreads_active));
+	return console_locked;
 }
 EXPORT_SYMBOL(is_console_locked);
 
@@ -2796,7 +2723,7 @@ static inline bool __console_is_usable(short flags)
  * Check if the given console is currently capable and allowed to print
  * records.
  *
- * Requires holding the console_lock.
+ * Requires the console_lock.
  */
 static inline bool console_is_usable(struct console *con)
 {
@@ -2809,22 +2736,6 @@ static inline bool console_is_usable(struct console *con)
 static void __console_unlock(void)
 {
 	console_locked = 0;
-
-	/*
-	 * Depending on whether console_lock() or console_trylock() was used,
-	 * appropriately allow the kthread printers to continue.
-	 */
-	if (console_kthreads_blocked)
-		console_kthreads_unblock();
-	else
-		console_kthreads_atomic_unblock();
-
-	/*
-	 * New records may have arrived while the console was locked.
-	 * Wake the kthread printers to print them.
-	 */
-	wake_up_klogd();
-
 	up_console_sem();
 }
 
@@ -2842,19 +2753,17 @@ static void __console_unlock(void)
  *
  * @handover will be set to true if a printk waiter has taken over the
  * console_lock, in which case the caller is no longer holding the
- * console_lock. Otherwise it is set to false. A NULL pointer may be provided
- * to disable allowing the console_lock to be taken over by a printk waiter.
+ * console_lock. Otherwise it is set to false.
  *
  * Returns false if the given console has no next record to print, otherwise
  * true.
  *
- * Requires the console_lock if @handover is non-NULL.
- * Requires con->lock otherwise.
+ * Requires the console_lock.
  */
-static bool __console_emit_next_record(struct console *con, char *text, char *ext_text,
-				       char *dropped_text, bool *handover)
+static bool console_emit_next_record(struct console *con, char *text, char *ext_text,
+				     char *dropped_text, bool *handover)
 {
-	static atomic_t panic_console_dropped = ATOMIC_INIT(0);
+	static int panic_console_dropped;
 	struct printk_info info;
 	struct printk_record r;
 	unsigned long flags;
@@ -2863,8 +2772,7 @@ static bool __console_emit_next_record(struct console *con, char *text, char *ex
 
 	prb_rec_init_rd(&r, &info, text, CONSOLE_LOG_MAX);
 
-	if (handover)
-		*handover = false;
+	*handover = false;
 
 	if (!prb_read_valid(prb, con->seq, &r))
 		return false;
@@ -2872,8 +2780,7 @@ static bool __console_emit_next_record(struct console *con, char *text, char *ex
 	if (con->seq != r.info->seq) {
 		con->dropped += r.info->seq - con->seq;
 		con->seq = r.info->seq;
-		if (panic_in_progress() &&
-		    atomic_fetch_inc_relaxed(&panic_console_dropped) > 10) {
+		if (panic_in_progress() && panic_console_dropped++ > 10) {
 			suppress_panic_printk = 1;
 			pr_warn_once("Too many dropped messages. Suppress messages on non-panic CPUs to prevent livelock.\n");
 		}
@@ -2895,61 +2802,31 @@ static bool __console_emit_next_record(struct console *con, char *text, char *ex
 		len = record_print_text(&r, console_msg_format & MSG_FORMAT_SYSLOG, printk_time);
 	}
 
-	if (handover) {
-		/*
-		 * While actively printing out messages, if another printk()
-		 * were to occur on another CPU, it may wait for this one to
-		 * finish. This task can not be preempted if there is a
-		 * waiter waiting to take over.
-		 *
-		 * Interrupts are disabled because the hand over to a waiter
-		 * must not be interrupted until the hand over is completed
-		 * (@console_waiter is cleared).
-		 */
-		printk_safe_enter_irqsave(flags);
-		console_lock_spinning_enable();
-
-		/* don't trace irqsoff print latency */
-		stop_critical_timings();
-	}
+	/*
+	 * While actively printing out messages, if another printk()
+	 * were to occur on another CPU, it may wait for this one to
+	 * finish. This task can not be preempted if there is a
+	 * waiter waiting to take over.
+	 *
+	 * Interrupts are disabled because the hand over to a waiter
+	 * must not be interrupted until the hand over is completed
+	 * (@console_waiter is cleared).
+	 */
+	printk_safe_enter_irqsave(flags);
+	console_lock_spinning_enable();
 
+	stop_critical_timings();	/* don't trace print latency */
 	call_console_driver(con, write_text, len, dropped_text);
+	start_critical_timings();
 
 	con->seq++;
 
-	if (handover) {
-		start_critical_timings();
-		*handover = console_lock_spinning_disable_and_check();
-		printk_safe_exit_irqrestore(flags);
-	}
+	*handover = console_lock_spinning_disable_and_check();
+	printk_safe_exit_irqrestore(flags);
 skip:
 	return true;
 }
 
-/*
- * Print a record for a given console, but allow another printk() caller to
- * take over the console_lock and continue printing.
- *
- * Requires the console_lock, but depending on @handover after the call, the
- * caller may no longer have the console_lock.
- *
- * See __console_emit_next_record() for argument and return details.
- */
-static bool console_emit_next_record_transferable(struct console *con, char *text, char *ext_text,
-						  char *dropped_text, bool *handover)
-{
-	/*
-	 * Handovers are only supported if threaded printers are atomically
-	 * blocked. The context taking over the console_lock may be atomic.
-	 */
-	if (!console_kthreads_atomically_blocked()) {
-		*handover = false;
-		handover = NULL;
-	}
-
-	return __console_emit_next_record(con, text, ext_text, dropped_text, handover);
-}
-
 /*
  * Print out all remaining records to all consoles.
  *
@@ -3001,11 +2878,13 @@ static bool console_flush_all(bool do_cond_resched, u64 *next_seq, bool *handove
 
 			if (con->flags & CON_EXTENDED) {
 				/* Extended consoles do not print "dropped messages". */
-				progress = console_emit_next_record_transferable(con, &text[0],
-								&ext_text[0], NULL, handover);
+				progress = console_emit_next_record(con, &text[0],
+								    &ext_text[0], NULL,
+								    handover);
 			} else {
-				progress = console_emit_next_record_transferable(con, &text[0],
-								NULL, &dropped_text[0], handover);
+				progress = console_emit_next_record(con, &text[0],
+								    NULL, &dropped_text[0],
+								    handover);
 			}
 			if (*handover)
 				return false;
@@ -3120,10 +2999,6 @@ void console_unblank(void)
 	if (oops_in_progress) {
 		if (down_trylock_console_sem() != 0)
 			return;
-		if (!console_kthreads_atomic_tryblock()) {
-			up_console_sem();
-			return;
-		}
 	} else
 		console_lock();
 
@@ -3206,6 +3081,10 @@ void console_start(struct console *console)
 	console_lock();
 	console->flags |= CON_ENABLED;
 	console_unlock();
+
+	/* Wake the newly enabled kthread printer. */
+	wake_up_klogd();
+
 	__pr_flush(console, 1000, true);
 }
 EXPORT_SYMBOL(console_start);
@@ -3407,8 +3286,6 @@ void register_console(struct console *newcon)
 
 	newcon->dropped = 0;
 	newcon->thread = NULL;
-	newcon->blocked = true;
-	mutex_init(&newcon->lock);
 
 	if (newcon->flags & CON_PRINTBUFFER) {
 		/* Get a consistent copy of @syslog_seq. */
@@ -3709,19 +3586,6 @@ static void printk_fallback_preferred_direct(void)
 	console_unlock();
 }
 
-/*
- * Print a record for a given console, not allowing another printk() caller
- * to take over. This is appropriate for contexts that do not have the
- * console_lock.
- *
- * See __console_emit_next_record() for argument and return details.
- */
-static bool console_emit_next_record(struct console *con, char *text, char *ext_text,
-				     char *dropped_text)
-{
-	return __console_emit_next_record(con, text, ext_text, dropped_text, NULL);
-}
-
 static bool printer_should_wake(struct console *con, u64 seq)
 {
 	short flags;
@@ -3729,10 +3593,8 @@ static bool printer_should_wake(struct console *con, u64 seq)
 	if (kthread_should_stop() || !printk_kthreads_available)
 		return true;
 
-	if (con->blocked ||
-	    console_kthreads_atomically_blocked()) {
+	if (console_suspended)
 		return false;
-	}
 
 	/*
 	 * This is an unsafe read from con->flags, but a false positive is
@@ -3753,6 +3615,7 @@ static int printk_kthread_func(void *data)
 	struct console *con = data;
 	char *dropped_text = NULL;
 	char *ext_text = NULL;
+	bool handover;
 	u64 seq = 0;
 	char *text;
 	int error;
@@ -3802,27 +3665,15 @@ static int printk_kthread_func(void *data)
 		if (error)
 			continue;
 
-		error = mutex_lock_interruptible(&con->lock);
-		if (error)
-			continue;
+		console_lock();
 
-		if (con->blocked ||
-		    !console_kthread_printing_tryenter()) {
-			/* Another context has locked the console_lock. */
-			mutex_unlock(&con->lock);
+		if (console_suspended) {
+			up_console_sem();
 			continue;
 		}
 
-		/*
-		 * Although this context has not locked the console_lock, it
-		 * is known that the console_lock is not locked and it is not
-		 * possible for any other context to lock the console_lock.
-		 * Therefore it is safe to read con->flags.
-		 */
-
-		if (!__console_is_usable(con->flags)) {
-			console_kthread_printing_exit();
-			mutex_unlock(&con->lock);
+		if (!console_is_usable(con)) {
+			__console_unlock();
 			continue;
 		}
 
@@ -3835,13 +3686,13 @@ static int printk_kthread_func(void *data)
 		 * which can conditionally invoke cond_resched().
 		 */
 		console_may_schedule = 0;
-		console_emit_next_record(con, text, ext_text, dropped_text);
+		console_emit_next_record(con, text, ext_text, dropped_text, &handover);
+		if (handover)
+			continue;
 
 		seq = con->seq;
 
-		console_kthread_printing_exit();
-
-		mutex_unlock(&con->lock);
+		__console_unlock();
 	}
 
 	con_printk(KERN_INFO, con, "printing thread stopped\n");
-- 
GitLab


From 5831788afb17b89c5b531fb60cbd798613ccbb63 Mon Sep 17 00:00:00 2001
From: Petr Mladek <pmladek@suse.com>
Date: Thu, 23 Jun 2022 16:51:56 +0200
Subject: [PATCH 1068/1731] Revert "printk: add kthread console printers"

This reverts commit 09c5ba0aa2fcfdadb17d045c3ee6f86d69270df7.

This reverts commit b87f02307d3cfbda768520f0687c51ca77e14fc3.

The testing of 5.19 release candidates revealed missing synchronization
between early and regular console functionality.

It would be possible to start the console kthreads later as a workaround.
But it is clear that console lock serialized console drivers between
each other. It opens a big area of possible problems that were not
considered by people involved in the development and review.

printk() is crucial for debugging kernel issues and console output is
very important part of it. The number of consoles is huge and a proper
review would take some time. As a result it need to be reverted for 5.19.

Link: https://lore.kernel.org/r/YrBdjVwBOVgLfHyb@alley
Signed-off-by: Petr Mladek <pmladek@suse.com>
Link: https://lore.kernel.org/r/20220623145157.21938-6-pmladek@suse.com
---
 include/linux/console.h |   2 -
 kernel/printk/printk.c  | 329 +++-------------------------------------
 2 files changed, 22 insertions(+), 309 deletions(-)

diff --git a/include/linux/console.h b/include/linux/console.h
index 9a251e70c090a..8c1686e2c2337 100644
--- a/include/linux/console.h
+++ b/include/linux/console.h
@@ -153,8 +153,6 @@ struct console {
 	uint	ospeed;
 	u64	seq;
 	unsigned long dropped;
-	struct task_struct *thread;
-
 	void	*data;
 	struct	 console *next;
 };
diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c
index ae489dc685a1e..5a6273e56b4e9 100644
--- a/kernel/printk/printk.c
+++ b/kernel/printk/printk.c
@@ -361,13 +361,6 @@ static int console_msg_format = MSG_FORMAT_DEFAULT;
 /* syslog_lock protects syslog_* variables and write access to clear_seq. */
 static DEFINE_MUTEX(syslog_lock);
 
-/*
- * A flag to signify if printk_activate_kthreads() has already started the
- * kthread printers. If true, any later registered consoles must start their
- * own kthread directly. The flag is write protected by the console_lock.
- */
-static bool printk_kthreads_available;
-
 #ifdef CONFIG_PRINTK
 static atomic_t printk_prefer_direct = ATOMIC_INIT(0);
 
@@ -397,39 +390,6 @@ void printk_prefer_direct_exit(void)
 	WARN_ON(atomic_dec_if_positive(&printk_prefer_direct) < 0);
 }
 
-/*
- * Calling printk() always wakes kthread printers so that they can
- * flush the new message to their respective consoles. Also, if direct
- * printing is allowed, printk() tries to flush the messages directly.
- *
- * Direct printing is allowed in situations when the kthreads
- * are not available or the system is in a problematic state.
- *
- * See the implementation about possible races.
- */
-static inline bool allow_direct_printing(void)
-{
-	/*
-	 * Checking kthread availability is a possible race because the
-	 * kthread printers can become permanently disabled during runtime.
-	 * However, doing that requires holding the console_lock, so any
-	 * pending messages will be direct printed by console_unlock().
-	 */
-	if (!printk_kthreads_available)
-		return true;
-
-	/*
-	 * Prefer direct printing when the system is in a problematic state.
-	 * The context that sets this state will always see the updated value.
-	 * The other contexts do not care. Anyway, direct printing is just a
-	 * best effort. The direct output is only possible when console_lock
-	 * is not already taken and no kthread printers are actively printing.
-	 */
-	return (system_state > SYSTEM_RUNNING ||
-		oops_in_progress ||
-		atomic_read(&printk_prefer_direct));
-}
-
 DECLARE_WAIT_QUEUE_HEAD(log_wait);
 /* All 3 protected by @syslog_lock. */
 /* the next printk record to read by syslog(READ) or /proc/kmsg */
@@ -2320,10 +2280,10 @@ asmlinkage int vprintk_emit(int facility, int level,
 	printed_len = vprintk_store(facility, level, dev_info, fmt, args);
 
 	/* If called from the scheduler, we can not call up(). */
-	if (!in_sched && allow_direct_printing()) {
+	if (!in_sched) {
 		/*
 		 * The caller may be holding system-critical or
-		 * timing-sensitive locks. Disable preemption during direct
+		 * timing-sensitive locks. Disable preemption during
 		 * printing of all remaining records to all consoles so that
 		 * this context can return as soon as possible. Hopefully
 		 * another printk() caller will take over the printing.
@@ -2366,8 +2326,6 @@ EXPORT_SYMBOL(_printk);
 
 static bool __pr_flush(struct console *con, int timeout_ms, bool reset_on_progress);
 
-static void printk_start_kthread(struct console *con);
-
 #else /* CONFIG_PRINTK */
 
 #define CONSOLE_LOG_MAX		0
@@ -2401,8 +2359,6 @@ static void call_console_driver(struct console *con, const char *text, size_t le
 }
 static bool suppress_message_printing(int level) { return false; }
 static bool __pr_flush(struct console *con, int timeout_ms, bool reset_on_progress) { return true; }
-static void printk_start_kthread(struct console *con) { }
-static bool allow_direct_printing(void) { return true; }
 
 #endif /* CONFIG_PRINTK */
 
@@ -2603,13 +2559,6 @@ void resume_console(void)
 	down_console_sem();
 	console_suspended = 0;
 	console_unlock();
-
-	/*
-	 * While suspended, new records may have been added to the
-	 * ringbuffer. Wake up the kthread printers to print them.
-	 */
-	wake_up_klogd();
-
 	pr_flush(1000, true);
 }
 
@@ -2628,9 +2577,6 @@ static int console_cpu_notify(unsigned int cpu)
 		/* If trylock fails, someone else is doing the printing */
 		if (console_trylock())
 			console_unlock();
-
-		/* Wake kthread printers. Some may have become usable. */
-		wake_up_klogd();
 	}
 	return 0;
 }
@@ -2702,9 +2648,18 @@ static bool abandon_console_lock_in_panic(void)
 	return atomic_read(&panic_cpu) != raw_smp_processor_id();
 }
 
-static inline bool __console_is_usable(short flags)
+/*
+ * Check if the given console is currently capable and allowed to print
+ * records.
+ *
+ * Requires the console_lock.
+ */
+static inline bool console_is_usable(struct console *con)
 {
-	if (!(flags & CON_ENABLED))
+	if (!(con->flags & CON_ENABLED))
+		return false;
+
+	if (!con->write)
 		return false;
 
 	/*
@@ -2713,26 +2668,12 @@ static inline bool __console_is_usable(short flags)
 	 * cope (CON_ANYTIME) don't call them until this CPU is officially up.
 	 */
 	if (!cpu_online(raw_smp_processor_id()) &&
-	    !(flags & CON_ANYTIME))
+	    !(con->flags & CON_ANYTIME))
 		return false;
 
 	return true;
 }
 
-/*
- * Check if the given console is currently capable and allowed to print
- * records.
- *
- * Requires the console_lock.
- */
-static inline bool console_is_usable(struct console *con)
-{
-	if (!con->write)
-		return false;
-
-	return __console_is_usable(con->flags);
-}
-
 static void __console_unlock(void)
 {
 	console_locked = 0;
@@ -2845,8 +2786,8 @@ skip:
  * were flushed to all usable consoles. A returned false informs the caller
  * that everything was not flushed (either there were no usable consoles or
  * another context has taken over printing or it is a panic situation and this
- * is not the panic CPU or direct printing is not preferred). Regardless the
- * reason, the caller should assume it is not useful to immediately try again.
+ * is not the panic CPU). Regardless the reason, the caller should assume it
+ * is not useful to immediately try again.
  *
  * Requires the console_lock.
  */
@@ -2863,10 +2804,6 @@ static bool console_flush_all(bool do_cond_resched, u64 *next_seq, bool *handove
 	*handover = false;
 
 	do {
-		/* Let the kthread printers do the work if they can. */
-		if (!allow_direct_printing())
-			return false;
-
 		any_progress = false;
 
 		for_each_console(con) {
@@ -3081,10 +3018,6 @@ void console_start(struct console *console)
 	console_lock();
 	console->flags |= CON_ENABLED;
 	console_unlock();
-
-	/* Wake the newly enabled kthread printer. */
-	wake_up_klogd();
-
 	__pr_flush(console, 1000, true);
 }
 EXPORT_SYMBOL(console_start);
@@ -3285,8 +3218,6 @@ void register_console(struct console *newcon)
 		nr_ext_console_drivers++;
 
 	newcon->dropped = 0;
-	newcon->thread = NULL;
-
 	if (newcon->flags & CON_PRINTBUFFER) {
 		/* Get a consistent copy of @syslog_seq. */
 		mutex_lock(&syslog_lock);
@@ -3296,10 +3227,6 @@ void register_console(struct console *newcon)
 		/* Begin with next message. */
 		newcon->seq = prb_next_seq(prb);
 	}
-
-	if (printk_kthreads_available)
-		printk_start_kthread(newcon);
-
 	console_unlock();
 	console_sysfs_notify();
 
@@ -3326,7 +3253,6 @@ EXPORT_SYMBOL(register_console);
 
 int unregister_console(struct console *console)
 {
-	struct task_struct *thd;
 	struct console *con;
 	int res;
 
@@ -3367,20 +3293,7 @@ int unregister_console(struct console *console)
 		console_drivers->flags |= CON_CONSDEV;
 
 	console->flags &= ~CON_ENABLED;
-
-	/*
-	 * console->thread can only be cleared under the console lock. But
-	 * stopping the thread must be done without the console lock. The
-	 * task that clears @thread is the task that stops the kthread.
-	 */
-	thd = console->thread;
-	console->thread = NULL;
-
 	console_unlock();
-
-	if (thd)
-		kthread_stop(thd);
-
 	console_sysfs_notify();
 
 	if (console->exit)
@@ -3476,20 +3389,6 @@ static int __init printk_late_init(void)
 }
 late_initcall(printk_late_init);
 
-static int __init printk_activate_kthreads(void)
-{
-	struct console *con;
-
-	console_lock();
-	printk_kthreads_available = true;
-	for_each_console(con)
-		printk_start_kthread(con);
-	console_unlock();
-
-	return 0;
-}
-early_initcall(printk_activate_kthreads);
-
 #if defined CONFIG_PRINTK
 /* If @con is specified, only wait for that console. Otherwise wait for all. */
 static bool __pr_flush(struct console *con, int timeout_ms, bool reset_on_progress)
@@ -3564,180 +3463,11 @@ bool pr_flush(int timeout_ms, bool reset_on_progress)
 }
 EXPORT_SYMBOL(pr_flush);
 
-static void __printk_fallback_preferred_direct(void)
-{
-	printk_prefer_direct_enter();
-	pr_err("falling back to preferred direct printing\n");
-	printk_kthreads_available = false;
-}
-
-/*
- * Enter preferred direct printing, but never exit. Mark console threads as
- * unavailable. The system is then forever in preferred direct printing and
- * any printing threads will exit.
- *
- * Must *not* be called under console_lock. Use
- * __printk_fallback_preferred_direct() if already holding console_lock.
- */
-static void printk_fallback_preferred_direct(void)
-{
-	console_lock();
-	__printk_fallback_preferred_direct();
-	console_unlock();
-}
-
-static bool printer_should_wake(struct console *con, u64 seq)
-{
-	short flags;
-
-	if (kthread_should_stop() || !printk_kthreads_available)
-		return true;
-
-	if (console_suspended)
-		return false;
-
-	/*
-	 * This is an unsafe read from con->flags, but a false positive is
-	 * not a problem. Worst case it would allow the printer to wake up
-	 * although it is disabled. But the printer will notice that when
-	 * attempting to print and instead go back to sleep.
-	 */
-	flags = data_race(READ_ONCE(con->flags));
-
-	if (!__console_is_usable(flags))
-		return false;
-
-	return prb_read_valid(prb, seq, NULL);
-}
-
-static int printk_kthread_func(void *data)
-{
-	struct console *con = data;
-	char *dropped_text = NULL;
-	char *ext_text = NULL;
-	bool handover;
-	u64 seq = 0;
-	char *text;
-	int error;
-
-	text = kmalloc(CONSOLE_LOG_MAX, GFP_KERNEL);
-	if (!text) {
-		con_printk(KERN_ERR, con, "failed to allocate text buffer\n");
-		printk_fallback_preferred_direct();
-		goto out;
-	}
-
-	if (con->flags & CON_EXTENDED) {
-		ext_text = kmalloc(CONSOLE_EXT_LOG_MAX, GFP_KERNEL);
-		if (!ext_text) {
-			con_printk(KERN_ERR, con, "failed to allocate ext_text buffer\n");
-			printk_fallback_preferred_direct();
-			goto out;
-		}
-	} else {
-		dropped_text = kmalloc(DROPPED_TEXT_MAX, GFP_KERNEL);
-		if (!dropped_text) {
-			con_printk(KERN_ERR, con, "failed to allocate dropped_text buffer\n");
-			printk_fallback_preferred_direct();
-			goto out;
-		}
-	}
-
-	con_printk(KERN_INFO, con, "printing thread started\n");
-
-	for (;;) {
-		/*
-		 * Guarantee this task is visible on the waitqueue before
-		 * checking the wake condition.
-		 *
-		 * The full memory barrier within set_current_state() of
-		 * prepare_to_wait_event() pairs with the full memory barrier
-		 * within wq_has_sleeper().
-		 *
-		 * This pairs with __wake_up_klogd:A.
-		 */
-		error = wait_event_interruptible(log_wait,
-				printer_should_wake(con, seq)); /* LMM(printk_kthread_func:A) */
-
-		if (kthread_should_stop() || !printk_kthreads_available)
-			break;
-
-		if (error)
-			continue;
-
-		console_lock();
-
-		if (console_suspended) {
-			up_console_sem();
-			continue;
-		}
-
-		if (!console_is_usable(con)) {
-			__console_unlock();
-			continue;
-		}
-
-		/*
-		 * Even though the printk kthread is always preemptible, it is
-		 * still not allowed to call cond_resched() from within
-		 * console drivers. The task may become non-preemptible in the
-		 * console driver call chain. For example, vt_console_print()
-		 * takes a spinlock and then can call into fbcon_redraw(),
-		 * which can conditionally invoke cond_resched().
-		 */
-		console_may_schedule = 0;
-		console_emit_next_record(con, text, ext_text, dropped_text, &handover);
-		if (handover)
-			continue;
-
-		seq = con->seq;
-
-		__console_unlock();
-	}
-
-	con_printk(KERN_INFO, con, "printing thread stopped\n");
-out:
-	kfree(dropped_text);
-	kfree(ext_text);
-	kfree(text);
-
-	console_lock();
-	/*
-	 * If this kthread is being stopped by another task, con->thread will
-	 * already be NULL. That is fine. The important thing is that it is
-	 * NULL after the kthread exits.
-	 */
-	con->thread = NULL;
-	console_unlock();
-
-	return 0;
-}
-
-/* Must be called under console_lock. */
-static void printk_start_kthread(struct console *con)
-{
-	/*
-	 * Do not start a kthread if there is no write() callback. The
-	 * kthreads assume the write() callback exists.
-	 */
-	if (!con->write)
-		return;
-
-	con->thread = kthread_run(printk_kthread_func, con,
-				  "pr/%s%d", con->name, con->index);
-	if (IS_ERR(con->thread)) {
-		con->thread = NULL;
-		con_printk(KERN_ERR, con, "unable to start printing thread\n");
-		__printk_fallback_preferred_direct();
-		return;
-	}
-}
-
 /*
  * Delayed printk version, for scheduler-internal messages:
  */
-#define PRINTK_PENDING_WAKEUP		0x01
-#define PRINTK_PENDING_DIRECT_OUTPUT	0x02
+#define PRINTK_PENDING_WAKEUP	0x01
+#define PRINTK_PENDING_OUTPUT	0x02
 
 static DEFINE_PER_CPU(int, printk_pending);
 
@@ -3745,14 +3475,10 @@ static void wake_up_klogd_work_func(struct irq_work *irq_work)
 {
 	int pending = this_cpu_xchg(printk_pending, 0);
 
-	if (pending & PRINTK_PENDING_DIRECT_OUTPUT) {
-		printk_prefer_direct_enter();
-
+	if (pending & PRINTK_PENDING_OUTPUT) {
 		/* If trylock fails, someone else is doing the printing */
 		if (console_trylock())
 			console_unlock();
-
-		printk_prefer_direct_exit();
 	}
 
 	if (pending & PRINTK_PENDING_WAKEUP)
@@ -3777,11 +3503,10 @@ static void __wake_up_klogd(int val)
 	 * prepare_to_wait_event(), which is called after ___wait_event() adds
 	 * the waiter but before it has checked the wait condition.
 	 *
-	 * This pairs with devkmsg_read:A, syslog_print:A, and
-	 * printk_kthread_func:A.
+	 * This pairs with devkmsg_read:A and syslog_print:A.
 	 */
 	if (wq_has_sleeper(&log_wait) || /* LMM(__wake_up_klogd:A) */
-	    (val & PRINTK_PENDING_DIRECT_OUTPUT)) {
+	    (val & PRINTK_PENDING_OUTPUT)) {
 		this_cpu_or(printk_pending, val);
 		irq_work_queue(this_cpu_ptr(&wake_up_klogd_work));
 	}
@@ -3799,17 +3524,7 @@ void defer_console_output(void)
 	 * New messages may have been added directly to the ringbuffer
 	 * using vprintk_store(), so wake any waiters as well.
 	 */
-	int val = PRINTK_PENDING_WAKEUP;
-
-	/*
-	 * Make sure that some context will print the messages when direct
-	 * printing is allowed. This happens in situations when the kthreads
-	 * may not be as reliable or perhaps unusable.
-	 */
-	if (allow_direct_printing())
-		val |= PRINTK_PENDING_DIRECT_OUTPUT;
-
-	__wake_up_klogd(val);
+	__wake_up_klogd(PRINTK_PENDING_WAKEUP | PRINTK_PENDING_OUTPUT);
 }
 
 void printk_trigger_flush(void)
-- 
GitLab


From 07a22b61946f0b80065b0ddcc703b715f84355f5 Mon Sep 17 00:00:00 2001
From: Petr Mladek <pmladek@suse.com>
Date: Thu, 23 Jun 2022 16:51:57 +0200
Subject: [PATCH 1069/1731] Revert "printk: add functions to prefer direct
 printing"

This reverts commit 2bb2b7b57f81255c13f4395ea911d6bdc70c9fe2.

The testing of 5.19 release candidates revealed missing synchronization
between early and regular console functionality.

It would be possible to start the console kthreads later as a workaround.
But it is clear that console lock serialized console drivers between
each other. It opens a big area of possible problems that were not
considered by people involved in the development and review.

printk() is crucial for debugging kernel issues and console output is
very important part of it. The number of consoles is huge and a proper
review would take some time. As a result it need to be reverted for 5.19.

Link: https://lore.kernel.org/r/YrBdjVwBOVgLfHyb@alley
Signed-off-by: Petr Mladek <pmladek@suse.com>
Link: https://lore.kernel.org/r/20220623145157.21938-7-pmladek@suse.com
---
 drivers/tty/sysrq.c     |  2 --
 include/linux/printk.h  | 11 -----------
 kernel/hung_task.c      | 11 +----------
 kernel/panic.c          |  4 ----
 kernel/printk/printk.c  | 28 ----------------------------
 kernel/rcu/tree_stall.h |  2 --
 kernel/reboot.c         | 14 +-------------
 kernel/watchdog.c       |  4 ----
 kernel/watchdog_hld.c   |  4 ----
 9 files changed, 2 insertions(+), 78 deletions(-)

diff --git a/drivers/tty/sysrq.c b/drivers/tty/sysrq.c
index 2884cd638d64b..bbfd004449b5b 100644
--- a/drivers/tty/sysrq.c
+++ b/drivers/tty/sysrq.c
@@ -578,7 +578,6 @@ void __handle_sysrq(int key, bool check_mask)
 
 	rcu_sysrq_start();
 	rcu_read_lock();
-	printk_prefer_direct_enter();
 	/*
 	 * Raise the apparent loglevel to maximum so that the sysrq header
 	 * is shown to provide the user with positive feedback.  We do not
@@ -620,7 +619,6 @@ void __handle_sysrq(int key, bool check_mask)
 		pr_cont("\n");
 		console_loglevel = orig_log_level;
 	}
-	printk_prefer_direct_exit();
 	rcu_read_unlock();
 	rcu_sysrq_end();
 
diff --git a/include/linux/printk.h b/include/linux/printk.h
index cd26aab0ab2a0..091fba7283e14 100644
--- a/include/linux/printk.h
+++ b/include/linux/printk.h
@@ -170,9 +170,6 @@ extern void __printk_safe_exit(void);
 #define printk_deferred_enter __printk_safe_enter
 #define printk_deferred_exit __printk_safe_exit
 
-extern void printk_prefer_direct_enter(void);
-extern void printk_prefer_direct_exit(void);
-
 extern bool pr_flush(int timeout_ms, bool reset_on_progress);
 
 /*
@@ -225,14 +222,6 @@ static inline void printk_deferred_exit(void)
 {
 }
 
-static inline void printk_prefer_direct_enter(void)
-{
-}
-
-static inline void printk_prefer_direct_exit(void)
-{
-}
-
 static inline bool pr_flush(int timeout_ms, bool reset_on_progress)
 {
 	return true;
diff --git a/kernel/hung_task.c b/kernel/hung_task.c
index 02a65d5543409..52501e5f76554 100644
--- a/kernel/hung_task.c
+++ b/kernel/hung_task.c
@@ -127,8 +127,6 @@ static void check_hung_task(struct task_struct *t, unsigned long timeout)
 	 * complain:
 	 */
 	if (sysctl_hung_task_warnings) {
-		printk_prefer_direct_enter();
-
 		if (sysctl_hung_task_warnings > 0)
 			sysctl_hung_task_warnings--;
 		pr_err("INFO: task %s:%d blocked for more than %ld seconds.\n",
@@ -144,8 +142,6 @@ static void check_hung_task(struct task_struct *t, unsigned long timeout)
 
 		if (sysctl_hung_task_all_cpu_backtrace)
 			hung_task_show_all_bt = true;
-
-		printk_prefer_direct_exit();
 	}
 
 	touch_nmi_watchdog();
@@ -208,17 +204,12 @@ static void check_hung_uninterruptible_tasks(unsigned long timeout)
 	}
  unlock:
 	rcu_read_unlock();
-	if (hung_task_show_lock) {
-		printk_prefer_direct_enter();
+	if (hung_task_show_lock)
 		debug_show_all_locks();
-		printk_prefer_direct_exit();
-	}
 
 	if (hung_task_show_all_bt) {
 		hung_task_show_all_bt = false;
-		printk_prefer_direct_enter();
 		trigger_all_cpu_backtrace();
-		printk_prefer_direct_exit();
 	}
 
 	if (hung_task_call_panic)
diff --git a/kernel/panic.c b/kernel/panic.c
index 6737b23322753..8355b19676f84 100644
--- a/kernel/panic.c
+++ b/kernel/panic.c
@@ -579,8 +579,6 @@ void __warn(const char *file, int line, void *caller, unsigned taint,
 {
 	disable_trace_on_warning();
 
-	printk_prefer_direct_enter();
-
 	if (file)
 		pr_warn("WARNING: CPU: %d PID: %d at %s:%d %pS\n",
 			raw_smp_processor_id(), current->pid, file, line,
@@ -610,8 +608,6 @@ void __warn(const char *file, int line, void *caller, unsigned taint,
 
 	/* Just a warning, don't kill lockdep. */
 	add_taint(taint, LOCKDEP_STILL_OK);
-
-	printk_prefer_direct_exit();
 }
 
 #ifndef __WARN_FLAGS
diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c
index 5a6273e56b4e9..b49c6ff6dca01 100644
--- a/kernel/printk/printk.c
+++ b/kernel/printk/printk.c
@@ -362,34 +362,6 @@ static int console_msg_format = MSG_FORMAT_DEFAULT;
 static DEFINE_MUTEX(syslog_lock);
 
 #ifdef CONFIG_PRINTK
-static atomic_t printk_prefer_direct = ATOMIC_INIT(0);
-
-/**
- * printk_prefer_direct_enter - cause printk() calls to attempt direct
- *                              printing to all enabled consoles
- *
- * Since it is not possible to call into the console printing code from any
- * context, there is no guarantee that direct printing will occur.
- *
- * This globally effects all printk() callers.
- *
- * Context: Any context.
- */
-void printk_prefer_direct_enter(void)
-{
-	atomic_inc(&printk_prefer_direct);
-}
-
-/**
- * printk_prefer_direct_exit - restore printk() behavior
- *
- * Context: Any context.
- */
-void printk_prefer_direct_exit(void)
-{
-	WARN_ON(atomic_dec_if_positive(&printk_prefer_direct) < 0);
-}
-
 DECLARE_WAIT_QUEUE_HEAD(log_wait);
 /* All 3 protected by @syslog_lock. */
 /* the next printk record to read by syslog(READ) or /proc/kmsg */
diff --git a/kernel/rcu/tree_stall.h b/kernel/rcu/tree_stall.h
index 4995c078cff98..a001e1e7a9926 100644
--- a/kernel/rcu/tree_stall.h
+++ b/kernel/rcu/tree_stall.h
@@ -647,7 +647,6 @@ static void print_cpu_stall(unsigned long gps)
 	 * See Documentation/RCU/stallwarn.rst for info on how to debug
 	 * RCU CPU stall warnings.
 	 */
-	printk_prefer_direct_enter();
 	trace_rcu_stall_warning(rcu_state.name, TPS("SelfDetected"));
 	pr_err("INFO: %s self-detected stall on CPU\n", rcu_state.name);
 	raw_spin_lock_irqsave_rcu_node(rdp->mynode, flags);
@@ -685,7 +684,6 @@ static void print_cpu_stall(unsigned long gps)
 	 */
 	set_tsk_need_resched(current);
 	set_preempt_need_resched();
-	printk_prefer_direct_exit();
 }
 
 static void check_cpu_stall(struct rcu_data *rdp)
diff --git a/kernel/reboot.c b/kernel/reboot.c
index 4177645e74d6a..6bcc5d6a6572b 100644
--- a/kernel/reboot.c
+++ b/kernel/reboot.c
@@ -447,11 +447,9 @@ static int __orderly_reboot(void)
 	ret = run_cmd(reboot_cmd);
 
 	if (ret) {
-		printk_prefer_direct_enter();
 		pr_warn("Failed to start orderly reboot: forcing the issue\n");
 		emergency_sync();
 		kernel_restart(NULL);
-		printk_prefer_direct_exit();
 	}
 
 	return ret;
@@ -464,7 +462,6 @@ static int __orderly_poweroff(bool force)
 	ret = run_cmd(poweroff_cmd);
 
 	if (ret && force) {
-		printk_prefer_direct_enter();
 		pr_warn("Failed to start orderly shutdown: forcing the issue\n");
 
 		/*
@@ -474,7 +471,6 @@ static int __orderly_poweroff(bool force)
 		 */
 		emergency_sync();
 		kernel_power_off();
-		printk_prefer_direct_exit();
 	}
 
 	return ret;
@@ -532,8 +528,6 @@ EXPORT_SYMBOL_GPL(orderly_reboot);
  */
 static void hw_failure_emergency_poweroff_func(struct work_struct *work)
 {
-	printk_prefer_direct_enter();
-
 	/*
 	 * We have reached here after the emergency shutdown waiting period has
 	 * expired. This means orderly_poweroff has not been able to shut off
@@ -550,8 +544,6 @@ static void hw_failure_emergency_poweroff_func(struct work_struct *work)
 	 */
 	pr_emerg("Hardware protection shutdown failed. Trying emergency restart\n");
 	emergency_restart();
-
-	printk_prefer_direct_exit();
 }
 
 static DECLARE_DELAYED_WORK(hw_failure_emergency_poweroff_work,
@@ -590,13 +582,11 @@ void hw_protection_shutdown(const char *reason, int ms_until_forced)
 {
 	static atomic_t allow_proceed = ATOMIC_INIT(1);
 
-	printk_prefer_direct_enter();
-
 	pr_emerg("HARDWARE PROTECTION shutdown (%s)\n", reason);
 
 	/* Shutdown should be initiated only once. */
 	if (!atomic_dec_and_test(&allow_proceed))
-		goto out;
+		return;
 
 	/*
 	 * Queue a backup emergency shutdown in the event of
@@ -604,8 +594,6 @@ void hw_protection_shutdown(const char *reason, int ms_until_forced)
 	 */
 	hw_failure_emergency_poweroff(ms_until_forced);
 	orderly_poweroff(true);
-out:
-	printk_prefer_direct_exit();
 }
 EXPORT_SYMBOL_GPL(hw_protection_shutdown);
 
diff --git a/kernel/watchdog.c b/kernel/watchdog.c
index 40024e03d4220..9166220457bcb 100644
--- a/kernel/watchdog.c
+++ b/kernel/watchdog.c
@@ -424,8 +424,6 @@ static enum hrtimer_restart watchdog_timer_fn(struct hrtimer *hrtimer)
 		/* Start period for the next softlockup warning. */
 		update_report_ts();
 
-		printk_prefer_direct_enter();
-
 		pr_emerg("BUG: soft lockup - CPU#%d stuck for %us! [%s:%d]\n",
 			smp_processor_id(), duration,
 			current->comm, task_pid_nr(current));
@@ -444,8 +442,6 @@ static enum hrtimer_restart watchdog_timer_fn(struct hrtimer *hrtimer)
 		add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK);
 		if (softlockup_panic)
 			panic("softlockup: hung tasks");
-
-		printk_prefer_direct_exit();
 	}
 
 	return HRTIMER_RESTART;
diff --git a/kernel/watchdog_hld.c b/kernel/watchdog_hld.c
index 701f35f0e2d44..247bf0b1582ca 100644
--- a/kernel/watchdog_hld.c
+++ b/kernel/watchdog_hld.c
@@ -135,8 +135,6 @@ static void watchdog_overflow_callback(struct perf_event *event,
 		if (__this_cpu_read(hard_watchdog_warn) == true)
 			return;
 
-		printk_prefer_direct_enter();
-
 		pr_emerg("Watchdog detected hard LOCKUP on cpu %d\n",
 			 this_cpu);
 		print_modules();
@@ -157,8 +155,6 @@ static void watchdog_overflow_callback(struct perf_event *event,
 		if (hardlockup_panic)
 			nmi_panic(regs, "Hard LOCKUP");
 
-		printk_prefer_direct_exit();
-
 		__this_cpu_write(hard_watchdog_warn, true);
 		return;
 	}
-- 
GitLab


From 6945b2141fc9429f30fd6df2bcdd657a7f309f2f Mon Sep 17 00:00:00 2001
From: Paolo Bonzini <pbonzini@redhat.com>
Date: Thu, 23 Jun 2022 07:15:17 -0400
Subject: [PATCH 1070/1731] MAINTAINERS: Reorganize KVM/x86 maintainership

For the last few years I have been the sole maintainer of KVM, albeit
getting serious help from all the people who have reviewed hundreds of
patches.  The volume of KVM x86 alone has gotten to the point where one
maintainer is not enough; especially if that maintainer is not doing it
full time and if they want to keep up with the evolution of ARM64 and
RISC-V at both the architecture and the hypervisor level.

So, this patch is the first step in restoring double maintainership
or even transitioning to the submaintainer model of other architectures.

The changes here were mostly proposed by Sean offlist and they are twofold:

- revisiting the set of KVM x86 reviewers.  It's important to have an
  an accurate list of people that are actively reviewing patches ("R"),
  as well as people that are able to act on bug reports ("M").  Otherwise,
  voids to be filled are not easily visible.  The proposal is to split
  KVM on Hyper-V, which is where Vitaly has been the main contributor
  for quite some time now; likewise for KVM paravirt support, which
  has been the main interest of Wanpeng and to which Vitaly has also
  contributed (e.g., for async page faults).  Jim and Joerg have not been
  particularly active (though Joerg has worked on guest support for AMD
  SEV); knowing them a bit, I can't imagine they would object to their
  removal or even be surprised, but please speak up if you do.

- promoting Sean to maintainer for KVM x86 host support.  While for
  now this changes little, let's treat it as a harbinger for future
  changes.  The plan is that I would keep the final integration testing
  for quite some time, and probably focus more on -rc work.  This will
  give me more time to clean up my ad hoc setup and moving towards a
  more public CI, with Sean focusing instead on next-release patches,
  and the testing up to where kvm-unit-tests and selftests pass.  In
  order to facilitate collaboration between Sean and myself, we'll
  also formalize a bit more the various branches of kvm.git.

Nothing is going to change with respect to handling pull requests to Linus
and from other architectures, as well as maintainance of the generic code
(which I expect and hope to be more important as architectures try to
share more code) and documentation.  However, it's not a coincidence
that my entry is now the last for x86, ready to be demoted to reviewer
if/when the right time comes.

Suggested-by: Sean Christopherson <seanjc@google.com>
Co-developed-by: Sean Christopherson <seanjc@google.com>
Cc: kvm@vger.kernel.org
Cc: Sean Christopherson <seanjc@google.com>
Cc: Vitaly Kuznetsov <vkuznets@redhat.com>
Cc: Wanpeng Li <wanpengli@tencent.com>
Cc: Jim Mattson <jmattson@google.com>
Cc: Joerg Roedel <joro@8bytes.org>
Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 MAINTAINERS | 41 ++++++++++++++++++++++++++++++++---------
 1 file changed, 32 insertions(+), 9 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 97014ae3e5ed2..bb7f42229d9e3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10897,28 +10897,51 @@ F:	tools/testing/selftests/kvm/*/s390x/
 F:	tools/testing/selftests/kvm/s390x/
 
 KERNEL VIRTUAL MACHINE FOR X86 (KVM/x86)
+M:	Sean Christopherson <seanjc@google.com>
 M:	Paolo Bonzini <pbonzini@redhat.com>
-R:	Sean Christopherson <seanjc@google.com>
-R:	Vitaly Kuznetsov <vkuznets@redhat.com>
-R:	Wanpeng Li <wanpengli@tencent.com>
-R:	Jim Mattson <jmattson@google.com>
-R:	Joerg Roedel <joro@8bytes.org>
 L:	kvm@vger.kernel.org
 S:	Supported
-W:	http://www.linux-kvm.org
 T:	git git://git.kernel.org/pub/scm/virt/kvm/kvm.git
 F:	arch/x86/include/asm/kvm*
-F:	arch/x86/include/asm/pvclock-abi.h
 F:	arch/x86/include/asm/svm.h
 F:	arch/x86/include/asm/vmx*.h
 F:	arch/x86/include/uapi/asm/kvm*
 F:	arch/x86/include/uapi/asm/svm.h
 F:	arch/x86/include/uapi/asm/vmx.h
-F:	arch/x86/kernel/kvm.c
-F:	arch/x86/kernel/kvmclock.c
 F:	arch/x86/kvm/
 F:	arch/x86/kvm/*/
 
+KVM PARAVIRT (KVM/paravirt)
+M:	Paolo Bonzini <pbonzini@redhat.com>
+R:	Wanpeng Li <wanpengli@tencent.com>
+R:	Vitaly Kuznetsov <vkuznets@redhat.com>
+L:	kvm@vger.kernel.org
+S:	Supported
+T:	git git://git.kernel.org/pub/scm/virt/kvm/kvm.git
+F:	arch/x86/kernel/kvm.c
+F:	arch/x86/kernel/kvmclock.c
+F:	arch/x86/include/asm/pvclock-abi.h
+F:	include/linux/kvm_para.h
+F:	include/uapi/linux/kvm_para.h
+F:	include/uapi/asm-generic/kvm_para.h
+F:	include/asm-generic/kvm_para.h
+F:	arch/um/include/asm/kvm_para.h
+F:	arch/x86/include/asm/kvm_para.h
+F:	arch/x86/include/uapi/asm/kvm_para.h
+
+KVM X86 HYPER-V (KVM/hyper-v)
+M:	Vitaly Kuznetsov <vkuznets@redhat.com>
+M:	Sean Christopherson <seanjc@google.com>
+M:	Paolo Bonzini <pbonzini@redhat.com>
+L:	kvm@vger.kernel.org
+S:	Supported
+T:	git git://git.kernel.org/pub/scm/virt/kvm/kvm.git
+F:	arch/x86/kvm/hyperv.*
+F:	arch/x86/kvm/kvm_onhyperv.*
+F:	arch/x86/kvm/svm/hyperv.*
+F:	arch/x86/kvm/svm/svm_onhyperv.*
+F:	arch/x86/kvm/vmx/evmcs.*
+
 KERNFS
 M:	Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 M:	Tejun Heo <tj@kernel.org>
-- 
GitLab


From 386e4fb6962b9f248a80f8870aea0870ca603e89 Mon Sep 17 00:00:00 2001
From: Jens Axboe <axboe@kernel.dk>
Date: Thu, 23 Jun 2022 11:06:43 -0600
Subject: [PATCH 1071/1731] io_uring: use original request task for inflight
 tracking

In prior kernels, we did file assignment always at prep time. This meant
that req->task == current. But after deferring that assignment and then
pushing the inflight tracking back in, we've got the inflight tracking
using current when it should in fact now be using req->task.

Fixup that error introduced by adding the inflight tracking back after
file assignments got modifed.

Fixes: 9cae36a094e7 ("io_uring: reinstate the inflight tracking")
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index 5c95755619e2d..5ff2cdb425bc4 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -1975,7 +1975,7 @@ static inline void io_req_track_inflight(struct io_kiocb *req)
 {
 	if (!(req->flags & REQ_F_INFLIGHT)) {
 		req->flags |= REQ_F_INFLIGHT;
-		atomic_inc(&current->io_uring->inflight_tracked);
+		atomic_inc(&req->task->io_uring->inflight_tracked);
 	}
 }
 
-- 
GitLab


From c28d76d360f9f7af1f910342bde27939873bc45e Mon Sep 17 00:00:00 2001
From: Stephen Boyd <swboyd@chromium.org>
Date: Tue, 21 Jun 2022 19:38:55 -0700
Subject: [PATCH 1072/1731] drm/msm/dpu: Increment vsync_cnt before waking up
 userspace

The 'vsync_cnt' is used to count the number of frames for a crtc.
Unfortunately, we increment the count after waking up userspace via
dpu_crtc_vblank_callback() calling drm_crtc_handle_vblank().
drm_crtc_handle_vblank() wakes up userspace processes that have called
drm_wait_vblank_ioctl(), and if that ioctl is expecting the count to
increase it won't.

Increment the count before calling into the drm APIs so that we don't
have to worry about ordering the increment with anything else in drm.
This fixes a software video decode test that fails to see frame counts
increase on Trogdor boards.

Cc: Mark Yacoub <markyacoub@chromium.org>
Cc: Jessica Zhang <quic_jesszhan@quicinc.com>
Fixes: 885455d6bf82 ("drm/msm: Change dpu_crtc_get_vblank_counter to use vsync count.")
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Jessica Zhang <quic_jesszhan@quicinc.com> # Trogdor (sc7180)
Patchwork: https://patchwork.freedesktop.org/patch/490531/
Link: https://lore.kernel.org/r/20220622023855.2970913-1-swboyd@chromium.org
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 3a462e327e0ed..a1b8c45929437 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1251,12 +1251,13 @@ static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
 	DPU_ATRACE_BEGIN("encoder_vblank_callback");
 	dpu_enc = to_dpu_encoder_virt(drm_enc);
 
+	atomic_inc(&phy_enc->vsync_cnt);
+
 	spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
 	if (dpu_enc->crtc)
 		dpu_crtc_vblank_callback(dpu_enc->crtc);
 	spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
 
-	atomic_inc(&phy_enc->vsync_cnt);
 	DPU_ATRACE_END("encoder_vblank_callback");
 }
 
-- 
GitLab


From 0769d0a7ae3c26c0f2210578f83b3d1b30391601 Mon Sep 17 00:00:00 2001
From: Kuogee Hsieh <quic_khsieh@quicinc.com>
Date: Wed, 22 Jun 2022 12:55:31 -0700
Subject: [PATCH 1073/1731] drm/msm/dp: reset drm_dev to NULL at
 dp_display_unbind()

During msm initialize phase, dp_display_unbind() will be called to undo
initializations had been done by dp_display_bind() previously if there is
error happen at msm_drm_bind. Under this kind of circumstance, drm_device
may not be populated completed which causes system crash at drm_dev_dbg().
This patch reset drm_dev to NULL so that following drm_dev_dbg() will not
refer to any internal fields of drm_device to prevent system from crashing.
Below are panic stack trace,

[   53.584904] Unable to handle kernel paging request at virtual address 0000000070018001
.
[   53.702212] Hardware name: Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+) (DT)
[   53.710445] pstate: 20400009 (nzCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[   53.717596] pc : string_nocheck+0x1c/0x64
[   53.721738] lr : string+0x54/0x60
[   53.725162] sp : ffffffc013d6b650
[   53.728590] pmr_save: 000000e0
[   53.731743] x29: ffffffc013d6b650 x28: 0000000000000002 x27: 0000000000ffffff
[   53.739083] x26: ffffffc013d6b710 x25: ffffffd07a066ae0 x24: ffffffd07a419f97
[   53.746420] x23: ffffffd07a419f99 x22: ffffff81fef360d4 x21: ffffff81fef364d4
[   53.753760] x20: ffffffc013d6b6f8 x19: ffffffd07a06683c x18: 0000000000000000
[   53.761093] x17: 4020386678302f30 x16: 00000000000000b0 x15: ffffffd0797523c8
[   53.768429] x14: 0000000000000004 x13: ffff0000ffffff00 x12: ffffffd07a066b2c
[   53.775780] x11: 0000000000000000 x10: 000000000000013c x9 : 0000000000000000
[   53.783117] x8 : ffffff81fef364d4 x7 : 0000000000000000 x6 : 0000000000000000
[   53.790445] x5 : 0000000000000000 x4 : ffff0a00ffffff04 x3 : ffff0a00ffffff04
[   53.797783] x2 : 0000000070018001 x1 : ffffffffffffffff x0 : ffffff81fef360d4
[   53.805136] Call trace:
[   53.807667]  string_nocheck+0x1c/0x64
[   53.811439]  string+0x54/0x60
[   53.814498]  vsnprintf+0x374/0x53c
[   53.818009]  pointer+0x3dc/0x40c
[   53.821340]  vsnprintf+0x398/0x53c
[   53.824854]  vscnprintf+0x3c/0x88
[   53.828274]  __trace_array_vprintk+0xcc/0x2d4
[   53.832768]  trace_array_printk+0x8c/0xb4
[   53.836900]  drm_trace_printf+0x74/0x9c
[   53.840875]  drm_dev_dbg+0xfc/0x1b8
[   53.844480]  dp_pm_suspend+0x70/0xf8
[   53.848164]  dpm_run_callback+0x60/0x1a0
[   53.852222]  __device_suspend+0x304/0x3f4
[   53.856363]  dpm_suspend+0xf8/0x3a8
[   53.859959]  dpm_suspend_start+0x8c/0xc0

Fixes: 570d3e5d28db ("drm/msm/dp: stop event kernel thread when DP unbind")
Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/490756/
Link: https://lore.kernel.org/r/1655927731-22396-1-git-send-email-quic_khsieh@quicinc.com
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
---
 drivers/gpu/drm/msm/dp/dp_display.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index a6117926a2742..dcd80c8a794c3 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -316,6 +316,8 @@ static void dp_display_unbind(struct device *dev, struct device *master,
 
 	dp_power_client_deinit(dp->power);
 	dp_aux_unregister(dp->aux);
+	dp->drm_dev = NULL;
+	dp->aux->drm_dev = NULL;
 	priv->dp[dp->id] = NULL;
 }
 
-- 
GitLab


From eb174bd875ae504cdc1b5b209da288fffb1e5128 Mon Sep 17 00:00:00 2001
From: sunliming <sunliming@kylinos.cn>
Date: Thu, 23 Jun 2022 09:27:07 +0800
Subject: [PATCH 1074/1731] drm/msm/dpu: Fix variable dereferenced before check

Fixes the following smatch warning:

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c:261
dpu_encoder_phys_wb_atomic_check() warn: variable dereferenced before check 'conn_state'

Fixes: d7d0e73f7de3 ("drm/msm/dpu: introduce the dpu_encoder_phys_* for writeback")
Signed-off-by: sunliming <sunliming@kylinos.cn>
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/490850/
Link: https://lore.kernel.org/r/20220623012707.453972-1-sunliming@kylinos.cn
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 59da348ff3396..0ec809ab06e72 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -252,11 +252,6 @@ static int dpu_encoder_phys_wb_atomic_check(
 	DPU_DEBUG("[atomic_check:%d, \"%s\",%d,%d]\n",
 			phys_enc->wb_idx, mode->name, mode->hdisplay, mode->vdisplay);
 
-	if (!conn_state->writeback_job || !conn_state->writeback_job->fb)
-		return 0;
-
-	fb = conn_state->writeback_job->fb;
-
 	if (!conn_state || !conn_state->connector) {
 		DPU_ERROR("invalid connector state\n");
 		return -EINVAL;
@@ -267,6 +262,11 @@ static int dpu_encoder_phys_wb_atomic_check(
 		return -EINVAL;
 	}
 
+	if (!conn_state->writeback_job || !conn_state->writeback_job->fb)
+		return 0;
+
+	fb = conn_state->writeback_job->fb;
+
 	DPU_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id,
 			fb->width, fb->height);
 
-- 
GitLab


From 61b6e2e5321da281ab3c0c04e1962b3d000f6248 Mon Sep 17 00:00:00 2001
From: Ming Lei <ming.lei@redhat.com>
Date: Thu, 23 Jun 2022 21:20:05 +0800
Subject: [PATCH 1075/1731] dm: fix BLK_STS_DM_REQUEUE handling when dm_io
 represents split bio

Commit 7dd76d1feec7 ("dm: improve bio splitting and associated IO
accounting") removed using cloned bio when dm io splitting is needed.
Using bio_trim()+bio_inc_remaining() rather than bio_split()+bio_chain()
causes multiple dm_io instances to share the same original bio, and it
works fine if IOs are completed successfully.

But a regression was caused for the case when BLK_STS_DM_REQUEUE is
returned from any one of DM's cloned bios (whose dm_io share the same
orig_bio). In this BLK_STS_DM_REQUEUE case only the mapped subset of
the original bio for the current exact dm_io needs to be re-submitted.
However, since the original bio is shared among all dm_io instances,
the ->orig_bio actually only represents the last dm_io instance, so
requeue can't work as expected. Also when more than one dm_io is
requeued, the same original bio is requeued from all dm_io's
completion handler, then race is caused.

Fix this issue by still allocating one clone bio for completing io
only, then io accounting can rely on ->orig_bio being unmodified. This
is needed because the dm_io's sector_offset and sectors members are
recorded relative to an unmodified ->orig_bio.

In the future, we can go back to using bio_trim()+bio_inc_remaining()
for dm's io splitting but then delay needing a bio clone only when
handling BLK_STS_DM_REQUEUE, but that approach is a bit complicated
(so it needs a development cycle):
1) bio clone needs to be done in task context
2) a block interface for unwinding bio is required

Fixes: 7dd76d1feec7 ("dm: improve bio splitting and associated IO accounting")
Reported-by: Benjamin Marzinski <bmarzins@redhat.com>
Signed-off-by: Ming Lei <ming.lei@redhat.com>
Signed-off-by: Mike Snitzer <snitzer@kernel.org>
---
 drivers/md/dm-core.h |  1 +
 drivers/md/dm.c      | 11 +++++++----
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/md/dm-core.h b/drivers/md/dm-core.h
index 54c0473a51dde..c954ff91870e7 100644
--- a/drivers/md/dm-core.h
+++ b/drivers/md/dm-core.h
@@ -272,6 +272,7 @@ struct dm_io {
 	atomic_t io_count;
 	struct mapped_device *md;
 
+	struct bio *split_bio;
 	/* The three fields represent mapped part of original bio */
 	struct bio *orig_bio;
 	unsigned int sector_offset; /* offset to end of orig_bio */
diff --git a/drivers/md/dm.c b/drivers/md/dm.c
index 9ede55278eec4..2b75f1ef7386b 100644
--- a/drivers/md/dm.c
+++ b/drivers/md/dm.c
@@ -594,6 +594,7 @@ static struct dm_io *alloc_io(struct mapped_device *md, struct bio *bio)
 	atomic_set(&io->io_count, 2);
 	this_cpu_inc(*md->pending_io);
 	io->orig_bio = bio;
+	io->split_bio = NULL;
 	io->md = md;
 	spin_lock_init(&io->lock);
 	io->start_time = jiffies;
@@ -887,7 +888,7 @@ static void dm_io_complete(struct dm_io *io)
 {
 	blk_status_t io_error;
 	struct mapped_device *md = io->md;
-	struct bio *bio = io->orig_bio;
+	struct bio *bio = io->split_bio ? io->split_bio : io->orig_bio;
 
 	if (io->status == BLK_STS_DM_REQUEUE) {
 		unsigned long flags;
@@ -1693,9 +1694,11 @@ static void dm_split_and_process_bio(struct mapped_device *md,
 	 * Remainder must be passed to submit_bio_noacct() so it gets handled
 	 * *after* bios already submitted have been completely processed.
 	 */
-	bio_trim(bio, io->sectors, ci.sector_count);
-	trace_block_split(bio, bio->bi_iter.bi_sector);
-	bio_inc_remaining(bio);
+	WARN_ON_ONCE(!dm_io_flagged(io, DM_IO_WAS_SPLIT));
+	io->split_bio = bio_split(bio, io->sectors, GFP_NOIO,
+				  &md->queue->bio_split);
+	bio_chain(io->split_bio, bio);
+	trace_block_split(io->split_bio, bio->bi_iter.bi_sector);
 	submit_bio_noacct(bio);
 out:
 	/*
-- 
GitLab


From 90736eb3232d208ee048493f371075e4272e0944 Mon Sep 17 00:00:00 2001
From: Mikulas Patocka <mpatocka@redhat.com>
Date: Thu, 23 Jun 2022 14:53:25 -0400
Subject: [PATCH 1076/1731] dm mirror log: clear log bits up to BITS_PER_LONG
 boundary

Commit 85e123c27d5c ("dm mirror log: round up region bitmap size to
BITS_PER_LONG") introduced a regression on 64-bit architectures in the
lvm testsuite tests: lvcreate-mirror, mirror-names and vgsplit-operation.

If the device is shrunk, we need to clear log bits beyond the end of the
device. The code clears bits up to a 32-bit boundary and then calculates
lc->sync_count by summing set bits up to a 64-bit boundary (the commit
changed that; previously, this boundary was 32-bit too). So, it was using
some non-zeroed bits in the calculation and this caused misbehavior.

Fix this regression by clearing bits up to BITS_PER_LONG boundary.

Fixes: 85e123c27d5c ("dm mirror log: round up region bitmap size to BITS_PER_LONG")
Cc: stable@vger.kernel.org
Reported-by: Benjamin Marzinski <bmarzins@redhat.com>
Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Signed-off-by: Mike Snitzer <snitzer@kernel.org>
---
 drivers/md/dm-log.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/md/dm-log.c b/drivers/md/dm-log.c
index 2dda05aada231..0c6620e7b7bf6 100644
--- a/drivers/md/dm-log.c
+++ b/drivers/md/dm-log.c
@@ -615,7 +615,7 @@ static int disk_resume(struct dm_dirty_log *log)
 			log_clear_bit(lc, lc->clean_bits, i);
 
 	/* clear any old bits -- device has shrunk */
-	for (i = lc->region_count; i % (sizeof(*lc->clean_bits) << BYTE_SHIFT); i++)
+	for (i = lc->region_count; i % BITS_PER_LONG; i++)
 		log_clear_bit(lc, lc->clean_bits, i);
 
 	/* copy clean across to sync */
-- 
GitLab


From b376471fb47d4905e72fe73e9eeed228f8f2f230 Mon Sep 17 00:00:00 2001
From: Jinzhou Su <Jinzhou.Su@amd.com>
Date: Thu, 23 Jun 2022 11:15:09 +0800
Subject: [PATCH 1077/1731] cpufreq: amd-pstate: Add resume and suspend
 callbacks

When system resumes from S3, the CPPC enable register will be
cleared and reset to 0.

So enable the CPPC interface by writing 1 to this register on
system resume and disable it during system suspend.

Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
[ rjw: Subject and changelog edits ]
Cc: All applicable <stable@vger.kernel.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 drivers/cpufreq/amd-pstate.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index 7be38bc6a673b..9ac75c1cde9c2 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -566,6 +566,28 @@ static int amd_pstate_cpu_exit(struct cpufreq_policy *policy)
 	return 0;
 }
 
+static int amd_pstate_cpu_resume(struct cpufreq_policy *policy)
+{
+	int ret;
+
+	ret = amd_pstate_enable(true);
+	if (ret)
+		pr_err("failed to enable amd-pstate during resume, return %d\n", ret);
+
+	return ret;
+}
+
+static int amd_pstate_cpu_suspend(struct cpufreq_policy *policy)
+{
+	int ret;
+
+	ret = amd_pstate_enable(false);
+	if (ret)
+		pr_err("failed to disable amd-pstate during suspend, return %d\n", ret);
+
+	return ret;
+}
+
 /* Sysfs attributes */
 
 /*
@@ -636,6 +658,8 @@ static struct cpufreq_driver amd_pstate_driver = {
 	.target		= amd_pstate_target,
 	.init		= amd_pstate_cpu_init,
 	.exit		= amd_pstate_cpu_exit,
+	.suspend	= amd_pstate_cpu_suspend,
+	.resume		= amd_pstate_cpu_resume,
 	.set_boost	= amd_pstate_set_boost,
 	.name		= "amd-pstate",
 	.attr           = amd_pstate_attr,
-- 
GitLab


From c7e1c443584ddd7facffca00e9e23b0d084e5bb3 Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiyks@gmail.com>
Date: Mon, 6 Jun 2022 13:44:24 +0900
Subject: [PATCH 1078/1731] gpio: Fix kernel-doc comments to nested union

Commit 48ec13d36d3f ("gpio: Properly document parent data union")
is supposed to have fixed a warning from "make htmldocs" regarding
kernel-doc comments to union members.  However, the same warning
still remains [1].

Fix the issue by following the example found in section "Nested
structs/unions" of Documentation/doc-guide/kernel-doc.rst.

Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Fixes: 48ec13d36d3f ("gpio: Properly document parent data union")
Link: https://lore.kernel.org/r/20220606093302.21febee3@canb.auug.org.au/ [1]
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Bartosz Golaszewski <brgl@bgdev.pl>
Cc: Joey Gouly <joey.gouly@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Tested-by: Stephen Rothwell <sfr@canb.auug.org.au>
Reviewed-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
---
 include/linux/gpio/driver.h | 29 ++++++++++++++++-------------
 1 file changed, 16 insertions(+), 13 deletions(-)

diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h
index b1e0f1f8ee2e7..54c3c6506503f 100644
--- a/include/linux/gpio/driver.h
+++ b/include/linux/gpio/driver.h
@@ -167,21 +167,24 @@ struct gpio_irq_chip {
 	 */
 	irq_flow_handler_t parent_handler;
 
-	/**
-	 * @parent_handler_data:
-	 *
-	 * If @per_parent_data is false, @parent_handler_data is a single
-	 * pointer used as the data associated with every parent interrupt.
-	 *
-	 * @parent_handler_data_array:
-	 *
-	 * If @per_parent_data is true, @parent_handler_data_array is
-	 * an array of @num_parents pointers, and is used to associate
-	 * different data for each parent. This cannot be NULL if
-	 * @per_parent_data is true.
-	 */
 	union {
+		/**
+		 * @parent_handler_data:
+		 *
+		 * If @per_parent_data is false, @parent_handler_data is a
+		 * single pointer used as the data associated with every
+		 * parent interrupt.
+		 */
 		void *parent_handler_data;
+
+		/**
+		 * @parent_handler_data_array:
+		 *
+		 * If @per_parent_data is true, @parent_handler_data_array is
+		 * an array of @num_parents pointers, and is used to associate
+		 * different data for each parent. This cannot be NULL if
+		 * @per_parent_data is true.
+		 */
 		void **parent_handler_data_array;
 	};
 
-- 
GitLab


From 421f5410965dbc65b7bf7d2b2323203920ad370c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com>
Date: Fri, 17 Jun 2022 12:06:29 -0700
Subject: [PATCH 1079/1731] drm/i915: Call i915_gem_suspend() only after
 display is turned off
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When the last reference of a gem object is removed it is added to the
mm.free_list list and mm.free_work is queued to actually free the
object.

So gem objects that had their last reference removed by display during
drm_atomic_helper_shutdown() are added to mm.free_list what could
cause that mm.free_work is executed at the same time as
intel_runtime_pm_driver_release() causing raw-wakerefs warning.

So here only calling i915_gem_suspend() and by consequence
i915_gem_drain_freed_objects() only after display is down making
sure all display gem objecs are freed when
intel_runtime_pm_driver_release() is executed.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220617190629.355356-1-jose.souza@intel.com
---
 drivers/gpu/drm/i915/i915_driver.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 419e237f9ea40..be95f3d0c3d03 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1049,8 +1049,6 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
 	intel_runtime_pm_disable(&i915->runtime_pm);
 	intel_power_domains_disable(i915);
 
-	i915_gem_suspend(i915);
-
 	if (HAS_DISPLAY(i915)) {
 		drm_kms_helper_poll_disable(&i915->drm);
 
@@ -1067,6 +1065,8 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
 
 	intel_dmc_ucode_suspend(i915);
 
+	i915_gem_suspend(i915);
+
 	/*
 	 * The only requirement is to reboot with display DC states disabled,
 	 * for now leaving all display power wells in the INIT power domain
-- 
GitLab


From 7cf2b0f9611b9971d663e1fc3206eeda3b902922 Mon Sep 17 00:00:00 2001
From: Dave Chinner <dchinner@redhat.com>
Date: Thu, 16 Jun 2022 07:44:31 -0700
Subject: [PATCH 1080/1731] xfs: bound maximum wait time for inodegc work

Currently inodegc work can sit queued on the per-cpu queue until
the workqueue is either flushed of the queue reaches a depth that
triggers work queuing (and later throttling). This means that we
could queue work that waits for a long time for some other event to
trigger flushing.

Hence instead of just queueing work at a specific depth, use a
delayed work that queues the work at a bound time. We can still
schedule the work immediately at a given depth, but we no long need
to worry about leaving a number of items on the list that won't get
processed until external events prevail.

Signed-off-by: Dave Chinner <dchinner@redhat.com>
Reviewed-by: Darrick J. Wong <djwong@kernel.org>
Signed-off-by: Darrick J. Wong <djwong@kernel.org>
---
 fs/xfs/xfs_icache.c | 36 ++++++++++++++++++++++--------------
 fs/xfs/xfs_mount.h  |  2 +-
 fs/xfs/xfs_super.c  |  2 +-
 3 files changed, 24 insertions(+), 16 deletions(-)

diff --git a/fs/xfs/xfs_icache.c b/fs/xfs/xfs_icache.c
index 5269354b1b69d..786702273621a 100644
--- a/fs/xfs/xfs_icache.c
+++ b/fs/xfs/xfs_icache.c
@@ -440,7 +440,7 @@ xfs_inodegc_queue_all(
 	for_each_online_cpu(cpu) {
 		gc = per_cpu_ptr(mp->m_inodegc, cpu);
 		if (!llist_empty(&gc->list))
-			queue_work_on(cpu, mp->m_inodegc_wq, &gc->work);
+			mod_delayed_work_on(cpu, mp->m_inodegc_wq, &gc->work, 0);
 	}
 }
 
@@ -1841,8 +1841,8 @@ void
 xfs_inodegc_worker(
 	struct work_struct	*work)
 {
-	struct xfs_inodegc	*gc = container_of(work, struct xfs_inodegc,
-							work);
+	struct xfs_inodegc	*gc = container_of(to_delayed_work(work),
+						struct xfs_inodegc, work);
 	struct llist_node	*node = llist_del_all(&gc->list);
 	struct xfs_inode	*ip, *n;
 
@@ -2014,6 +2014,7 @@ xfs_inodegc_queue(
 	struct xfs_inodegc	*gc;
 	int			items;
 	unsigned int		shrinker_hits;
+	unsigned long		queue_delay = 1;
 
 	trace_xfs_inode_set_need_inactive(ip);
 	spin_lock(&ip->i_flags_lock);
@@ -2025,19 +2026,26 @@ xfs_inodegc_queue(
 	items = READ_ONCE(gc->items);
 	WRITE_ONCE(gc->items, items + 1);
 	shrinker_hits = READ_ONCE(gc->shrinker_hits);
-	put_cpu_ptr(gc);
 
-	if (!xfs_is_inodegc_enabled(mp))
+	/*
+	 * We queue the work while holding the current CPU so that the work
+	 * is scheduled to run on this CPU.
+	 */
+	if (!xfs_is_inodegc_enabled(mp)) {
+		put_cpu_ptr(gc);
 		return;
-
-	if (xfs_inodegc_want_queue_work(ip, items)) {
-		trace_xfs_inodegc_queue(mp, __return_address);
-		queue_work(mp->m_inodegc_wq, &gc->work);
 	}
 
+	if (xfs_inodegc_want_queue_work(ip, items))
+		queue_delay = 0;
+
+	trace_xfs_inodegc_queue(mp, __return_address);
+	mod_delayed_work(mp->m_inodegc_wq, &gc->work, queue_delay);
+	put_cpu_ptr(gc);
+
 	if (xfs_inodegc_want_flush_work(ip, items, shrinker_hits)) {
 		trace_xfs_inodegc_throttle(mp, __return_address);
-		flush_work(&gc->work);
+		flush_delayed_work(&gc->work);
 	}
 }
 
@@ -2054,7 +2062,7 @@ xfs_inodegc_cpu_dead(
 	unsigned int		count = 0;
 
 	dead_gc = per_cpu_ptr(mp->m_inodegc, dead_cpu);
-	cancel_work_sync(&dead_gc->work);
+	cancel_delayed_work_sync(&dead_gc->work);
 
 	if (llist_empty(&dead_gc->list))
 		return;
@@ -2073,12 +2081,12 @@ xfs_inodegc_cpu_dead(
 	llist_add_batch(first, last, &gc->list);
 	count += READ_ONCE(gc->items);
 	WRITE_ONCE(gc->items, count);
-	put_cpu_ptr(gc);
 
 	if (xfs_is_inodegc_enabled(mp)) {
 		trace_xfs_inodegc_queue(mp, __return_address);
-		queue_work(mp->m_inodegc_wq, &gc->work);
+		mod_delayed_work(mp->m_inodegc_wq, &gc->work, 0);
 	}
+	put_cpu_ptr(gc);
 }
 
 /*
@@ -2173,7 +2181,7 @@ xfs_inodegc_shrinker_scan(
 			unsigned int	h = READ_ONCE(gc->shrinker_hits);
 
 			WRITE_ONCE(gc->shrinker_hits, h + 1);
-			queue_work_on(cpu, mp->m_inodegc_wq, &gc->work);
+			mod_delayed_work_on(cpu, mp->m_inodegc_wq, &gc->work, 0);
 			no_items = false;
 		}
 	}
diff --git a/fs/xfs/xfs_mount.h b/fs/xfs/xfs_mount.h
index ba5d42abf66e0..d2eaebd85abfa 100644
--- a/fs/xfs/xfs_mount.h
+++ b/fs/xfs/xfs_mount.h
@@ -61,7 +61,7 @@ struct xfs_error_cfg {
  */
 struct xfs_inodegc {
 	struct llist_head	list;
-	struct work_struct	work;
+	struct delayed_work	work;
 
 	/* approximate count of inodes in the list */
 	unsigned int		items;
diff --git a/fs/xfs/xfs_super.c b/fs/xfs/xfs_super.c
index ed18160e6181c..90d9c419ecc51 100644
--- a/fs/xfs/xfs_super.c
+++ b/fs/xfs/xfs_super.c
@@ -1074,7 +1074,7 @@ xfs_inodegc_init_percpu(
 		gc = per_cpu_ptr(mp->m_inodegc, cpu);
 		init_llist_head(&gc->list);
 		gc->items = 0;
-		INIT_WORK(&gc->work, xfs_inodegc_worker);
+		INIT_DELAYED_WORK(&gc->work, xfs_inodegc_worker);
 	}
 	return 0;
 }
-- 
GitLab


From 5e672cd69f0a534a445df4372141fd0d1d00901d Mon Sep 17 00:00:00 2001
From: Dave Chinner <dchinner@redhat.com>
Date: Thu, 16 Jun 2022 07:44:32 -0700
Subject: [PATCH 1081/1731] xfs: introduce xfs_inodegc_push()

The current blocking mechanism for pushing the inodegc queue out to
disk can result in systems becoming unusable when there is a long
running inodegc operation. This is because the statfs()
implementation currently issues a blocking flush of the inodegc
queue and a significant number of common system utilities will call
statfs() to discover something about the underlying filesystem.

This can result in userspace operations getting stuck on inodegc
progress, and when trying to remove a heavily reflinked file on slow
storage with a full journal, this can result in delays measuring in
hours.

Avoid this problem by adding "push" function that expedites the
flushing of the inodegc queue, but doesn't wait for it to complete.

Convert xfs_fs_statfs() and xfs_qm_scall_getquota() to use this
mechanism so they don't block but still ensure that queued
operations are expedited.

Fixes: ab23a7768739 ("xfs: per-cpu deferred inode inactivation queues")
Reported-by: Chris Dunlop <chris@onthe.net.au>
Signed-off-by: Dave Chinner <dchinner@redhat.com>
[djwong: fix _getquota_next to use _inodegc_push too]
Reviewed-by: Darrick J. Wong <djwong@kernel.org>
Signed-off-by: Darrick J. Wong <djwong@kernel.org>
---
 fs/xfs/xfs_icache.c      | 20 +++++++++++++++-----
 fs/xfs/xfs_icache.h      |  1 +
 fs/xfs/xfs_qm_syscalls.c |  9 ++++++---
 fs/xfs/xfs_super.c       |  7 +++++--
 fs/xfs/xfs_trace.h       |  1 +
 5 files changed, 28 insertions(+), 10 deletions(-)

diff --git a/fs/xfs/xfs_icache.c b/fs/xfs/xfs_icache.c
index 786702273621a..2609825d53eed 100644
--- a/fs/xfs/xfs_icache.c
+++ b/fs/xfs/xfs_icache.c
@@ -1862,19 +1862,29 @@ xfs_inodegc_worker(
 }
 
 /*
- * Force all currently queued inode inactivation work to run immediately and
- * wait for the work to finish.
+ * Expedite all pending inodegc work to run immediately. This does not wait for
+ * completion of the work.
  */
 void
-xfs_inodegc_flush(
+xfs_inodegc_push(
 	struct xfs_mount	*mp)
 {
 	if (!xfs_is_inodegc_enabled(mp))
 		return;
+	trace_xfs_inodegc_push(mp, __return_address);
+	xfs_inodegc_queue_all(mp);
+}
 
+/*
+ * Force all currently queued inode inactivation work to run immediately and
+ * wait for the work to finish.
+ */
+void
+xfs_inodegc_flush(
+	struct xfs_mount	*mp)
+{
+	xfs_inodegc_push(mp);
 	trace_xfs_inodegc_flush(mp, __return_address);
-
-	xfs_inodegc_queue_all(mp);
 	flush_workqueue(mp->m_inodegc_wq);
 }
 
diff --git a/fs/xfs/xfs_icache.h b/fs/xfs/xfs_icache.h
index 2e4cfddf8b8ed..6cd180721659b 100644
--- a/fs/xfs/xfs_icache.h
+++ b/fs/xfs/xfs_icache.h
@@ -76,6 +76,7 @@ void xfs_blockgc_stop(struct xfs_mount *mp);
 void xfs_blockgc_start(struct xfs_mount *mp);
 
 void xfs_inodegc_worker(struct work_struct *work);
+void xfs_inodegc_push(struct xfs_mount *mp);
 void xfs_inodegc_flush(struct xfs_mount *mp);
 void xfs_inodegc_stop(struct xfs_mount *mp);
 void xfs_inodegc_start(struct xfs_mount *mp);
diff --git a/fs/xfs/xfs_qm_syscalls.c b/fs/xfs/xfs_qm_syscalls.c
index 74ac9ca9e119d..392cb39cc10c8 100644
--- a/fs/xfs/xfs_qm_syscalls.c
+++ b/fs/xfs/xfs_qm_syscalls.c
@@ -454,9 +454,12 @@ xfs_qm_scall_getquota(
 	struct xfs_dquot	*dqp;
 	int			error;
 
-	/* Flush inodegc work at the start of a quota reporting scan. */
+	/*
+	 * Expedite pending inodegc work at the start of a quota reporting
+	 * scan but don't block waiting for it to complete.
+	 */
 	if (id == 0)
-		xfs_inodegc_flush(mp);
+		xfs_inodegc_push(mp);
 
 	/*
 	 * Try to get the dquot. We don't want it allocated on disk, so don't
@@ -498,7 +501,7 @@ xfs_qm_scall_getquota_next(
 
 	/* Flush inodegc work at the start of a quota reporting scan. */
 	if (*id == 0)
-		xfs_inodegc_flush(mp);
+		xfs_inodegc_push(mp);
 
 	error = xfs_qm_dqget_next(mp, *id, type, &dqp);
 	if (error)
diff --git a/fs/xfs/xfs_super.c b/fs/xfs/xfs_super.c
index 90d9c419ecc51..aa977c7ea370b 100644
--- a/fs/xfs/xfs_super.c
+++ b/fs/xfs/xfs_super.c
@@ -797,8 +797,11 @@ xfs_fs_statfs(
 	xfs_extlen_t		lsize;
 	int64_t			ffree;
 
-	/* Wait for whatever inactivations are in progress. */
-	xfs_inodegc_flush(mp);
+	/*
+	 * Expedite background inodegc but don't wait. We do not want to block
+	 * here waiting hours for a billion extent file to be truncated.
+	 */
+	xfs_inodegc_push(mp);
 
 	statp->f_type = XFS_SUPER_MAGIC;
 	statp->f_namelen = MAXNAMELEN - 1;
diff --git a/fs/xfs/xfs_trace.h b/fs/xfs/xfs_trace.h
index d32026585c1be..0fa1b7a2918c9 100644
--- a/fs/xfs/xfs_trace.h
+++ b/fs/xfs/xfs_trace.h
@@ -240,6 +240,7 @@ DEFINE_EVENT(xfs_fs_class, name,					\
 	TP_PROTO(struct xfs_mount *mp, void *caller_ip), \
 	TP_ARGS(mp, caller_ip))
 DEFINE_FS_EVENT(xfs_inodegc_flush);
+DEFINE_FS_EVENT(xfs_inodegc_push);
 DEFINE_FS_EVENT(xfs_inodegc_start);
 DEFINE_FS_EVENT(xfs_inodegc_stop);
 DEFINE_FS_EVENT(xfs_inodegc_queue);
-- 
GitLab


From b0d473185ba887c798ed0cd6f5abf4075363baa4 Mon Sep 17 00:00:00 2001
From: Stefan Wahren <stefan.wahren@i2se.com>
Date: Fri, 17 Jun 2022 12:38:09 +0200
Subject: [PATCH 1082/1731] gpio: mxs: Fix header comment

This driver is about MXS GPIO support. MXC is a different platform.

Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
---
 drivers/gpio/gpio-mxs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c
index c5166cd47c9cd..7f59e5d936c2e 100644
--- a/drivers/gpio/gpio-mxs.c
+++ b/drivers/gpio/gpio-mxs.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 //
-// MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
+// MXS GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
 // Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 //
 // Based on code from Freescale,
-- 
GitLab


From 3d313f09f31490cec9d5251b59adeb6542c944cc Mon Sep 17 00:00:00 2001
From: Carlos Llamas <cmllamas@google.com>
Date: Tue, 21 Jun 2022 20:39:21 +0000
Subject: [PATCH 1083/1731] drm/fourcc: fix integer type usage in uapi header
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Kernel uapi headers are supposed to use __[us]{8,16,32,64} types defined
by <linux/types.h> as opposed to 'uint32_t' and similar. See [1] for the
relevant discussion about this topic. In this particular case, the usage
of 'uint64_t' escaped headers_check as these macros are not being called
here. However, the following program triggers a compilation error:

  #include <drm/drm_fourcc.h>

  int main()
  {
  	unsigned long x = AMD_FMT_MOD_CLEAR(RB);
  	return 0;
  }

gcc error:
  drm.c:5:27: error: ‘uint64_t’ undeclared (first use in this function)
      5 |         unsigned long x = AMD_FMT_MOD_CLEAR(RB);
        |                           ^~~~~~~~~~~~~~~~~

This patch changes AMD_FMT_MOD_{SET,CLEAR} macros to use the correct
integer types, which fixes the above issue.

  [1] https://lkml.org/lkml/2019/6/5/18

Fixes: 8ba16d599374 ("drm/fourcc: Add AMD DRM modifiers.")
Signed-off-by: Carlos Llamas <cmllamas@google.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 include/uapi/drm/drm_fourcc.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 1d717c75e1717..65af4a724b671 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -1446,11 +1446,11 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
 #define AMD_FMT_MOD_PIPE_MASK 0x7
 
 #define AMD_FMT_MOD_SET(field, value) \
-	((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
+	((__u64)(value) << AMD_FMT_MOD_##field##_SHIFT)
 #define AMD_FMT_MOD_GET(field, value) \
 	(((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
 #define AMD_FMT_MOD_CLEAR(field) \
-	(~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
+	(~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
 
 #if defined(__cplusplus)
 }
-- 
GitLab


From fa3dab48defe1ae2f5a5fb56df5f5931fb3e45c8 Mon Sep 17 00:00:00 2001
From: Jiang Jian <jiangjian@cdjrlc.com>
Date: Wed, 22 Jun 2022 22:22:37 +0800
Subject: [PATCH 1084/1731] gpu/drm/radeon: Fix typo in comments

Remove the repeated word 'and' from comments

Signed-off-by: Jiang Jian <jiangjian@cdjrlc.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/radeon/r300_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/r300_reg.h b/drivers/gpu/drm/radeon/r300_reg.h
index 60d5413bafa10..9d341cff63ee7 100644
--- a/drivers/gpu/drm/radeon/r300_reg.h
+++ b/drivers/gpu/drm/radeon/r300_reg.h
@@ -1103,7 +1103,7 @@
  * The destination register index is in FPI1 (color) and FPI3 (alpha)
  * together with enable bits.
  * There are separate enable bits for writing into temporary registers
- * (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_*
+ * (DSTC_REG_* /DSTA_REG) and program output registers (DSTC_OUTPUT_*
  * /DSTA_OUTPUT). You can write to both at once, or not write at all (the
  * same index must be used for both).
  *
-- 
GitLab


From 508f748b03949143ccda614b900e3f7d842251e5 Mon Sep 17 00:00:00 2001
From: Ruili Ji <ruiliji2@amd.com>
Date: Wed, 22 Jun 2022 14:20:22 +0800
Subject: [PATCH 1085/1731] drm/amdgpu: To flush tlb for MMHUB of RAVEN series

amdgpu: [mmhub0] no-retry page fault (src_id:0 ring:40 vmid:8 pasid:32769, for process test_basic pid 3305 thread test_basic pid 3305)
amdgpu: in page starting at address 0x00007ff990003000 from IH client 0x12 (VMC)
amdgpu: VM_L2_PROTECTION_FAULT_STATUS:0x00840051
amdgpu: Faulty UTCL2 client ID: MP1 (0x0)
amdgpu: MORE_FAULTS: 0x1
amdgpu: WALKER_ERROR: 0x0
amdgpu: PERMISSION_FAULTS: 0x5
amdgpu: MAPPING_ERROR: 0x0
amdgpu: RW: 0x1

When memory is allocated by kfd, no one triggers the tlb flush for MMHUB0.
There is page fault from MMHUB0.

v2:fix indentation
v3:change subject and fix indentation

Signed-off-by: Ruili Ji <ruiliji2@amd.com>
Reviewed-by: Philip Yang <philip.yang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 513c57f839d81..44da025502aca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -727,7 +727,8 @@ int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 {
 	bool all_hub = false;
 
-	if (adev->family == AMDGPU_FAMILY_AI)
+	if (adev->family == AMDGPU_FAMILY_AI ||
+	    adev->family == AMDGPU_FAMILY_RV)
 		all_hub = true;
 
 	return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub);
-- 
GitLab


From ff83e6e7ab042e1f6f4345be1837d08c41b0a49d Mon Sep 17 00:00:00 2001
From: Graham Sider <Graham.Sider@amd.com>
Date: Fri, 3 Jun 2022 09:53:54 -0400
Subject: [PATCH 1086/1731] drm/amdgpu: Fetch MES scheduler/KIQ versions

Store MES scheduler and MES KIQ version numbers in amdgpu_mes for GFX11.

Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h |  3 +++
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c  | 12 ++++++++++++
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index 25590b301f25b..42f5a61dd2ec8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -65,6 +65,9 @@ struct amdgpu_mes {
 
 	spinlock_t                      queue_id_lock;
 
+	uint32_t			sched_version;
+	uint32_t			kiq_version;
+
 	uint32_t                        total_max_queue;
 	uint32_t                        doorbell_id_offset;
 	uint32_t                        max_doorbell_slices;
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 7eee004cf3ce3..ead1860744d89 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -858,6 +858,18 @@ static int mes_v11_0_queue_init(struct amdgpu_device *adev,
 		mes_v11_0_queue_init_register(ring);
 	}
 
+	/* get MES scheduler/KIQ versions */
+	mutex_lock(&adev->srbm_mutex);
+	soc21_grbm_select(adev, 3, pipe, 0, 0);
+
+	if (pipe == AMDGPU_MES_SCHED_PIPE)
+		adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
+	else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
+		adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
+
+	soc21_grbm_select(adev, 0, 0, 0, 0);
+	mutex_unlock(&adev->srbm_mutex);
+
 	return 0;
 }
 
-- 
GitLab


From e77a541f5dea0a2ff9d6a40dcda9b284e1e736fe Mon Sep 17 00:00:00 2001
From: Graham Sider <Graham.Sider@amd.com>
Date: Wed, 11 May 2022 12:33:35 -0400
Subject: [PATCH 1087/1731] drm/amdkfd: Enable GFX11 usermode queue
 oversubscription
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Starting with GFX11, MES requires wptr BOs to be GTT allocated/mapped to
GART for usermode queues in order to support oversubscription. In the
case that work is submitted to an unmapped queue, MES must have a GART
wptr address to determine whether the queue should be mapped.

This change is accompanied with changes in MES and is applicable for
MES_API_VERSION >= 2.

v3:
- Use amdgpu_vm_bo_lookup_mapping for wptr_bo mapping lookup
- Move wptr_bo refcount increment to amdgpu_amdkfd_map_gtt_bo_to_gart
- Remove list_del_init from amdgpu_amdkfd_map_gtt_bo_to_gart
- Cleanup/fix create_queue wptr_bo error handling
v4:
- Add MES version shift/mask defines to amdgpu_mes.h
- Change version check from MES_VERSION to MES_API_VERSION
- Add check in kfd_ioctl_create_queue before wptr bo pin/GART map to
ensure bo is a single page.

Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h    |  2 +
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 48 +++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h       |  7 +++
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c      | 45 ++++++++++++++++-
 .../drm/amd/amdkfd/kfd_device_queue_manager.c |  9 +++-
 .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c  |  2 +
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h         |  3 ++
 .../amd/amdkfd/kfd_process_queue_manager.c    | 17 +++++--
 8 files changed, 125 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 648c031942e92..b25b41f502138 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -286,6 +286,8 @@ int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
 					     void **kptr, uint64_t *size);
 void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem);
 
+int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo);
+
 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,
 					    struct dma_fence **ef);
 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 8805bd1eed372..f3f9912fc51aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -2113,6 +2113,54 @@ int amdgpu_amdkfd_gpuvm_sync_memory(
 	return ret;
 }
 
+/**
+ * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference count
+ * @adev: Device to which allocated BO belongs
+ * @bo: Buffer object to be mapped
+ *
+ * Before return, bo reference count is incremented. To release the reference and unpin/
+ * unmap the BO, call amdgpu_amdkfd_free_gtt_mem.
+ */
+int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo)
+{
+	int ret;
+
+	ret = amdgpu_bo_reserve(bo, true);
+	if (ret) {
+		pr_err("Failed to reserve bo. ret %d\n", ret);
+		goto err_reserve_bo_failed;
+	}
+
+	ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
+	if (ret) {
+		pr_err("Failed to pin bo. ret %d\n", ret);
+		goto err_pin_bo_failed;
+	}
+
+	ret = amdgpu_ttm_alloc_gart(&bo->tbo);
+	if (ret) {
+		pr_err("Failed to bind bo to GART. ret %d\n", ret);
+		goto err_map_bo_gart_failed;
+	}
+
+	amdgpu_amdkfd_remove_eviction_fence(
+		bo, bo->kfd_bo->process_info->eviction_fence);
+
+	amdgpu_bo_unreserve(bo);
+
+	bo = amdgpu_bo_ref(bo);
+
+	return 0;
+
+err_map_bo_gart_failed:
+	amdgpu_bo_unpin(bo);
+err_pin_bo_failed:
+	amdgpu_bo_unreserve(bo);
+err_reserve_bo_failed:
+
+	return ret;
+}
+
 /** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Map a GTT BO for kernel CPU access
  *
  * @mem: Buffer object to be mapped for CPU access
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index 42f5a61dd2ec8..9c11219e925fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -33,6 +33,13 @@
 #define AMDGPU_MES_MAX_GFX_PIPES            2
 #define AMDGPU_MES_MAX_SDMA_PIPES           2
 
+#define AMDGPU_MES_API_VERSION_SHIFT	12
+#define AMDGPU_MES_FEAT_VERSION_SHIFT	24
+
+#define AMDGPU_MES_VERSION_MASK		0x00000fff
+#define AMDGPU_MES_API_VERSION_MASK	0x00fff000
+#define AMDGPU_MES_FEAT_VERSION_MASK	0xff000000
+
 enum amdgpu_mes_priority_level {
 	AMDGPU_MES_PRIORITY_LEVEL_LOW       = 0,
 	AMDGPU_MES_PRIORITY_LEVEL_NORMAL    = 1,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 3bcf9bf29acbb..d07588230ed60 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -299,6 +299,7 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
 	struct kfd_process_device *pdd;
 	struct queue_properties q_properties;
 	uint32_t doorbell_offset_in_process = 0;
+	struct amdgpu_bo *wptr_bo = NULL;
 
 	memset(&q_properties, 0, sizeof(struct queue_properties));
 
@@ -326,12 +327,49 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
 		goto err_bind_process;
 	}
 
+	/* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work
+	 * on unmapped queues for usermode queue oversubscription (no aggregated doorbell)
+	 */
+	if (dev->shared_resources.enable_mes &&
+			((dev->adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK)
+			>> AMDGPU_MES_API_VERSION_SHIFT) >= 2) {
+		struct amdgpu_bo_va_mapping *wptr_mapping;
+		struct amdgpu_vm *wptr_vm;
+
+		wptr_vm = drm_priv_to_vm(pdd->drm_priv);
+		err = amdgpu_bo_reserve(wptr_vm->root.bo, false);
+		if (err)
+			goto err_wptr_map_gart;
+
+		wptr_mapping = amdgpu_vm_bo_lookup_mapping(
+				wptr_vm, args->write_pointer_address >> PAGE_SHIFT);
+		amdgpu_bo_unreserve(wptr_vm->root.bo);
+		if (!wptr_mapping) {
+			pr_err("Failed to lookup wptr bo\n");
+			err = -EINVAL;
+			goto err_wptr_map_gart;
+		}
+
+		wptr_bo = wptr_mapping->bo_va->base.bo;
+		if (wptr_bo->tbo.base.size > PAGE_SIZE) {
+			pr_err("Requested GART mapping for wptr bo larger than one page\n");
+			err = -EINVAL;
+			goto err_wptr_map_gart;
+		}
+
+		err = amdgpu_amdkfd_map_gtt_bo_to_gart(dev->adev, wptr_bo);
+		if (err) {
+			pr_err("Failed to map wptr bo to GART\n");
+			goto err_wptr_map_gart;
+		}
+	}
+
 	pr_debug("Creating queue for PASID 0x%x on gpu 0x%x\n",
 			p->pasid,
 			dev->id);
 
-	err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id, NULL, NULL, NULL,
-			&doorbell_offset_in_process);
+	err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id, wptr_bo,
+			NULL, NULL, NULL, &doorbell_offset_in_process);
 	if (err != 0)
 		goto err_create_queue;
 
@@ -363,6 +401,9 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
 	return 0;
 
 err_create_queue:
+	if (wptr_bo)
+		amdgpu_amdkfd_free_gtt_mem(dev->adev, wptr_bo);
+err_wptr_map_gart:
 err_bind_process:
 err_pdd:
 	mutex_unlock(&p->mutex);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 213246a5b4e4f..299927a4959b1 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -177,6 +177,7 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q,
 	struct kfd_process_device *pdd = qpd_to_pdd(qpd);
 	struct mes_add_queue_input queue_input;
 	int r, queue_type;
+	uint64_t wptr_addr_off;
 
 	if (dqm->is_hws_hang)
 		return -EIO;
@@ -196,7 +197,13 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q,
 					AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
 	queue_input.doorbell_offset = q->properties.doorbell_off;
 	queue_input.mqd_addr = q->gart_mqd_addr;
-	queue_input.wptr_addr = (uint64_t)q->properties.write_ptr;
+
+	if (q->wptr_bo) {
+		wptr_addr_off = (uint64_t)q->properties.write_ptr - (uint64_t)q->wptr_bo->kfd_bo->va;
+		queue_input.wptr_addr = ((uint64_t)q->wptr_bo->tbo.resource->start << PAGE_SHIFT) + wptr_addr_off;
+	} else
+		queue_input.wptr_addr = (uint64_t)q->properties.write_ptr;
+
 	queue_input.paging = false;
 	queue_input.tba_addr = qpd->tba_addr;
 	queue_input.tma_addr = qpd->tma_addr;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
index 4e0387f591beb..b8e14c2cc2956 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
@@ -377,6 +377,8 @@ static void update_mqd_sdma(struct mqd_manager *mm, void *mqd,
 	m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
 	m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
 	m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
+	m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
+	m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
 	m->sdmax_rlcx_doorbell_offset =
 		q->doorbell_off << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT;
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 2585d6e61d422..4c4bbd493caae 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -571,6 +571,8 @@ struct queue {
 	void *gang_ctx_bo;
 	uint64_t gang_ctx_gpu_addr;
 	void *gang_ctx_cpu_ptr;
+
+	struct amdgpu_bo *wptr_bo;
 };
 
 enum KFD_MQD_TYPE {
@@ -1206,6 +1208,7 @@ int pqm_create_queue(struct process_queue_manager *pqm,
 			    struct file *f,
 			    struct queue_properties *properties,
 			    unsigned int *qid,
+			    struct amdgpu_bo *wptr_bo,
 			    const struct kfd_criu_queue_priv_data *q_data,
 			    const void *restore_mqd,
 			    const void *restore_ctl_stack,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index 99f2a64122016..a46e2a37b4a65 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -180,7 +180,8 @@ void pqm_uninit(struct process_queue_manager *pqm)
 static int init_user_queue(struct process_queue_manager *pqm,
 				struct kfd_dev *dev, struct queue **q,
 				struct queue_properties *q_properties,
-				struct file *f, unsigned int qid)
+				struct file *f, struct amdgpu_bo *wptr_bo,
+				unsigned int qid)
 {
 	int retval;
 
@@ -210,6 +211,7 @@ static int init_user_queue(struct process_queue_manager *pqm,
 			goto cleanup;
 		}
 		memset((*q)->gang_ctx_cpu_ptr, 0, AMDGPU_MES_GANG_CTX_SIZE);
+		(*q)->wptr_bo = wptr_bo;
 	}
 
 	pr_debug("PQM After init queue");
@@ -226,6 +228,7 @@ int pqm_create_queue(struct process_queue_manager *pqm,
 			    struct file *f,
 			    struct queue_properties *properties,
 			    unsigned int *qid,
+			    struct amdgpu_bo *wptr_bo,
 			    const struct kfd_criu_queue_priv_data *q_data,
 			    const void *restore_mqd,
 			    const void *restore_ctl_stack,
@@ -288,7 +291,7 @@ int pqm_create_queue(struct process_queue_manager *pqm,
 		 * allocate_sdma_queue() in create_queue() has the
 		 * corresponding check logic.
 		 */
-		retval = init_user_queue(pqm, dev, &q, properties, f, *qid);
+		retval = init_user_queue(pqm, dev, &q, properties, f, wptr_bo, *qid);
 		if (retval != 0)
 			goto err_create_queue;
 		pqn->q = q;
@@ -309,7 +312,7 @@ int pqm_create_queue(struct process_queue_manager *pqm,
 			goto err_create_queue;
 		}
 
-		retval = init_user_queue(pqm, dev, &q, properties, f, *qid);
+		retval = init_user_queue(pqm, dev, &q, properties, f, wptr_bo, *qid);
 		if (retval != 0)
 			goto err_create_queue;
 		pqn->q = q;
@@ -435,9 +438,13 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid)
 			pdd->qpd.num_gws = 0;
 		}
 
-		if (dev->shared_resources.enable_mes)
+		if (dev->shared_resources.enable_mes) {
 			amdgpu_amdkfd_free_gtt_mem(dev->adev,
 						   pqn->q->gang_ctx_bo);
+			if (pqn->q->wptr_bo)
+				amdgpu_amdkfd_free_gtt_mem(dev->adev, pqn->q->wptr_bo);
+
+		}
 		kfd_procfs_del_queue(pqn->q);
 		uninit_queue(pqn->q);
 	}
@@ -844,7 +851,7 @@ int kfd_criu_restore_queue(struct kfd_process *p,
 
 	print_queue_properties(&qp);
 
-	ret = pqm_create_queue(&p->pqm, pdd->dev, NULL, &qp, &queue_id, q_data, mqd, ctl_stack,
+	ret = pqm_create_queue(&p->pqm, pdd->dev, NULL, &qp, &queue_id, NULL, q_data, mqd, ctl_stack,
 				NULL);
 	if (ret) {
 		pr_err("Failed to create new queue err:%d\n", ret);
-- 
GitLab


From a957995618a8afe3efa2b5746c0a954bbd450882 Mon Sep 17 00:00:00 2001
From: Graham Sider <Graham.Sider@amd.com>
Date: Thu, 28 Apr 2022 10:16:16 -0400
Subject: [PATCH 1088/1731] drm/amdgpu: Update mes_v11_api_def.h

Update MES API to support oversubscription without aggregated doorbell
for usermode queues.

v2: Change oversubscription_no_aggregated_en to is_kfd_process (align
with MES)

Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c               | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h               | 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c                | 2 ++
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 ++
 drivers/gpu/drm/amd/include/mes_v11_api_def.h         | 4 +++-
 5 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 69a70a0aaed93..521e35d93d677 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -677,6 +677,7 @@ int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id,
 	queue_input.wptr_addr = qprops->wptr_gpu_addr;
 	queue_input.queue_type = qprops->queue_type;
 	queue_input.paging = qprops->paging;
+	queue_input.is_kfd_process = 0;
 
 	r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input);
 	if (r) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index 9c11219e925fe..85ebb5fdba0b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -214,6 +214,7 @@ struct mes_add_queue_input {
 	uint32_t        gws_size;
 	uint64_t	tba_addr;
 	uint64_t	tma_addr;
+	uint32_t	is_kfd_process;
 };
 
 struct mes_remove_queue_input {
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index ead1860744d89..7dfc6ea21397b 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -165,6 +165,7 @@ static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes,
 	mes_add_queue_pkt.gws_size = input->gws_size;
 	mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
 	mes_add_queue_pkt.tma_addr = input->tma_addr;
+	mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
 
 	mes_add_queue_pkt.api_status.api_completion_fence_addr =
 		mes->ring.fence_drv.gpu_addr;
@@ -312,6 +313,7 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
 	mes_set_hw_res_pkt.disable_reset = 1;
 	mes_set_hw_res_pkt.disable_mes_log = 1;
 	mes_set_hw_res_pkt.use_different_vmid_compute = 1;
+	mes_set_hw_res_pkt.oversubscription_timer = 50;
 
 	mes_set_hw_res_pkt.api_status.api_completion_fence_addr =
 		mes->ring.fence_drv.gpu_addr;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 299927a4959b1..74a1f8a6f53f3 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -204,6 +204,8 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q,
 	} else
 		queue_input.wptr_addr = (uint64_t)q->properties.write_ptr;
 
+	queue_input.is_kfd_process = 1;
+
 	queue_input.paging = false;
 	queue_input.tba_addr = qpd->tba_addr;
 	queue_input.tma_addr = qpd->tma_addr;
diff --git a/drivers/gpu/drm/amd/include/mes_v11_api_def.h b/drivers/gpu/drm/amd/include/mes_v11_api_def.h
index f9d02d7bdf776..fa1b9e0d299a5 100644
--- a/drivers/gpu/drm/amd/include/mes_v11_api_def.h
+++ b/drivers/gpu/drm/amd/include/mes_v11_api_def.h
@@ -226,6 +226,7 @@ union MESAPI_SET_HW_RESOURCES {
 			};
 			uint32_t	uint32_t_all;
 		};
+		uint32_t	oversubscription_timer;
 	};
 
 	uint32_t	max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
@@ -265,7 +266,8 @@ union MESAPI__ADD_QUEUE {
 			uint32_t is_gang_suspended	: 1;
 			uint32_t is_tmz_queue		: 1;
 			uint32_t map_kiq_utility_queue  : 1;
-			uint32_t reserved		: 23;
+			uint32_t is_kfd_process		: 1;
+			uint32_t reserved		: 22;
 		};
 		struct MES_API_STATUS		api_status;
 		uint64_t                        tma_addr;
-- 
GitLab


From 10a9035c36d00586ad4bdb838f8800be951db8d2 Mon Sep 17 00:00:00 2001
From: Nathan Chancellor <nathan@kernel.org>
Date: Thu, 23 Jun 2022 08:30:01 -0700
Subject: [PATCH 1089/1731] drm/amd/display: Fix indentation in
 dcn32_get_vco_frequency_from_reg()

Clang warns:

  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c:549:4: warning: misleading indentation; statement is not part of the previous 'else' [-Wmisleading-indentation]
                          pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
                          ^
  drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c:542:3: note: previous statement is here
                  else
                  ^
  1 warning generated.

Indent this statement to the left, as it was clearly intended to be
called unconditionally, which will fix the warning.

Link: https://github.com/ClangBuiltLinux/linux/issues/1655
Fixes: 3e838f7ccf64 ("drm/amd/display: Get VCO frequency from registers")
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 113f93b3d3b27..4e8059f200075 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -546,7 +546,7 @@ static uint32_t dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mg
 		 * this works because the int part is on the right edge of the register
 		 * and the frac part is on the left edge
 		 */
-			pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
+		pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
 		pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
 
 		/* multiply by REFCLK period */
-- 
GitLab


From 50ef0cacc43c5b01d5d1d65f08af33513b07e2c7 Mon Sep 17 00:00:00 2001
From: Jiang Jian <jiangjian@cdjrlc.com>
Date: Thu, 23 Jun 2022 18:14:48 +0800
Subject: [PATCH 1090/1731] drm/amdgpu: drop unexpected word 'for' in comments

there is an unexpected word 'for' in the comments that need to be dropped

file - drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
line - 245

 * position and also advance the position for for Vega10

changed to:

 * position and also advance the position for Vega10

Signed-off-by: Jiang Jian <jiangjian@cdjrlc.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index 3df146579ad9c..1d5af50331e41 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -242,7 +242,7 @@ restart_ih:
  * @entry: IV entry
  *
  * Decodes the interrupt vector at the current rptr
- * position and also advance the position for for Vega10
+ * position and also advance the position for Vega10
  * and later GPUs.
  */
 void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev,
-- 
GitLab


From f64e6e0b6afe047cb0d34a5369597fe0d188e94d Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Mon, 20 Jun 2022 18:29:39 -0400
Subject: [PATCH 1091/1731] Revert "drm/amdgpu/display: set
 vblank_disable_immediate for DC"

This reverts commit 92020e81ddbeac351ea4a19bcf01743f32b9c800.

This causes stuttering and timeouts with DMCUB for some users
so revert it until we understand why and safely enable it
to save power.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1887
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c           | 1 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ---
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index b4cf8717f554e..89011bae7588e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -320,6 +320,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
 	if (!amdgpu_device_has_dc_support(adev)) {
 		if (!adev->enable_virtual_display)
 			/* Disable vblank IRQs aggressively for power-saving */
+			/* XXX: can this be enabled for DC? */
 			adev_to_drm(adev)->vblank_disable_immediate = true;
 
 		r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index beadd75ab93d8..2f7982fd70822 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4251,9 +4251,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 		}
 	}
 
-	/* Disable vblank IRQs aggressively for power-saving. */
-	adev_to_drm(adev)->vblank_disable_immediate = true;
-
 	/* loops over all connectors on the board */
 	for (i = 0; i < link_cnt; i++) {
 		struct dc_link *link = NULL;
-- 
GitLab


From 5027605aedec363b3209c17d382efe5e29211594 Mon Sep 17 00:00:00 2001
From: Colin Ian King <colin.i.king@gmail.com>
Date: Thu, 23 Jun 2022 13:14:18 -0400
Subject: [PATCH 1092/1731] drm/amdkfd: Fix spelling mistake "mechanim" ->
 "mechanism"

There is a spelling mistake in a pr_debug message. Fix it.

Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index f3f9912fc51aa..0036c9e405afd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -914,7 +914,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
 			ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]);
 			if (ret)
 				goto unwind;
-			pr_debug("Employ DMABUF mechanim to enable peer GPU access\n");
+			pr_debug("Employ DMABUF mechanism to enable peer GPU access\n");
 		} else {
 			WARN_ONCE(true, "Handling invalid ATTACH request");
 			ret = -EINVAL;
-- 
GitLab


From 7fc494f9cf8ec7497d4aab26a3b19deceab0fe31 Mon Sep 17 00:00:00 2001
From: Colin Ian King <colin.i.king@gmail.com>
Date: Thu, 23 Jun 2022 13:19:04 -0400
Subject: [PATCH 1093/1731] drm/amdgpu/display: Fix spelling mistake
 "supporing" -> "supporting"

There is a spelling mistake in a dml_print message. Fix it.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 510b7a81ee124..5bb6f4d8bf287 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -1098,7 +1098,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 				if (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required && v->ImmediateFlipSupportedForPipe[k] == false) {
 					v->ImmediateFlipSupported = false;
 #ifdef __DML_VBA_DEBUG__
-					dml_print("DML::%s: Pipe %0d not supporing iflip\n", __func__, k);
+					dml_print("DML::%s: Pipe %0d not supporting iflip\n", __func__, k);
 #endif
 				}
 			}
-- 
GitLab


From 366e817e83e4d795fe3f6e7379bfe79d49cac89b Mon Sep 17 00:00:00 2001
From: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Mon, 20 Jun 2022 02:37:20 +0200
Subject: [PATCH 1094/1731] Revert "drm/amd/display: ignore modifiers when
 checking for format support"

This reverts commit 5089c4a8ebea3c3ad9eedf038dad7098ebc06131.

This breaks validation and enumeration of display capable modifiers.

The early return true means the rest of the validation code never gets
executed, and we need that to enumerate the right modifiers to userspace
for the format.

The modifiers that are in the initial list generated for a plane are the
superset for all formats and we need the proper checks in this function
to filter some of them out for formats with which they're invalid to be
used.

Furthermore, the safety contract here is that we validate the incoming
modifiers to ensure the kernel can handle them and the display hardware
can handle them. This includes e.g. rejecting multi-plane images with DCC.

Note that the legacy swizzle mechanism allows encoding more swizzles, and
at fb creation time we convert them to modifiers and reject those with
no corresponding modifiers. If we are seeing rejections I'm happy to
help define modifiers that correspond to those, or if absolutely needed
implement a fallback path to allow for less strict validation of the
legacy path.

However, I'd like to revert this patch, since any of these is going to
be a significant rework of the patch, and I'd rather not the regression
gets into a release or forgotten in the meantime.

Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 53 +++----------------
 1 file changed, 7 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 2f7982fd70822..9195d6a8a51f6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4890,7 +4890,8 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane,
 {
 	struct amdgpu_device *adev = drm_to_adev(plane->dev);
 	const struct drm_format_info *info = drm_format_info(format);
-	struct hw_asic_id asic_id = adev->dm.dc->ctx->asic_id;
+	int i;
+
 	enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3;
 
 	if (!info)
@@ -4906,53 +4907,13 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane,
 		return true;
 	}
 
-	/* check if swizzle mode is supported by this version of DCN */
-	switch (asic_id.chip_family) {
-		case FAMILY_SI:
-		case FAMILY_CI:
-		case FAMILY_KV:
-		case FAMILY_CZ:
-		case FAMILY_VI:
-			/* asics before AI does not have modifier support */
-			return false;
-			break;
-		case FAMILY_AI:
-		case FAMILY_RV:
-		case FAMILY_NV:
-		case FAMILY_VGH:
-		case FAMILY_YELLOW_CARP:
-		case AMDGPU_FAMILY_GC_10_3_6:
-		case AMDGPU_FAMILY_GC_10_3_7:
-			switch (AMD_FMT_MOD_GET(TILE, modifier)) {
-				case AMD_FMT_MOD_TILE_GFX9_64K_R_X:
-				case AMD_FMT_MOD_TILE_GFX9_64K_D_X:
-				case AMD_FMT_MOD_TILE_GFX9_64K_S_X:
-				case AMD_FMT_MOD_TILE_GFX9_64K_D:
-					return true;
-					break;
-				default:
-					return false;
-					break;
-			}
-			break;
-		case AMDGPU_FAMILY_GC_11_0_0:
-			switch (AMD_FMT_MOD_GET(TILE, modifier)) {
-				case AMD_FMT_MOD_TILE_GFX11_256K_R_X:
-				case AMD_FMT_MOD_TILE_GFX9_64K_R_X:
-				case AMD_FMT_MOD_TILE_GFX9_64K_D_X:
-				case AMD_FMT_MOD_TILE_GFX9_64K_S_X:
-				case AMD_FMT_MOD_TILE_GFX9_64K_D:
-					return true;
-					break;
-				default:
-					return false;
-					break;
-			}
-			break;
-		default:
-			ASSERT(0); /* Unknown asic */
+	/* Check that the modifier is on the list of the plane's supported modifiers. */
+	for (i = 0; i < plane->modifier_count; i++) {
+		if (modifier == plane->modifiers[i])
 			break;
 	}
+	if (i == plane->modifier_count)
+		return false;
 
 	/*
 	 * For D swizzle the canonical modifier depends on the bpp, so check
-- 
GitLab


From f50974eee5c4a5de1e4f1a3d873099f170df25f8 Mon Sep 17 00:00:00 2001
From: Dan Williams <dan.j.williams@intel.com>
Date: Thu, 23 Jun 2022 13:02:31 -0700
Subject: [PATCH 1095/1731] memregion: Fix memregion_free() fallback definition

In the CONFIG_MEMREGION=n case, memregion_free() is meant to be a static
inline. 0day reports:

    In file included from drivers/cxl/core/port.c:4:
    include/linux/memregion.h:19:6: warning: no previous prototype for
    function 'memregion_free' [-Wmissing-prototypes]

Mark memregion_free() static.

Fixes: 33dd70752cd7 ("lib: Uplevel the pmem "region" ida to a global allocator")
Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://lore.kernel.org/r/165601455171.4042645.3350844271068713515.stgit@dwillia2-xfh
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
 include/linux/memregion.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/memregion.h b/include/linux/memregion.h
index e11595256cac0..c04c4fd2e2091 100644
--- a/include/linux/memregion.h
+++ b/include/linux/memregion.h
@@ -16,7 +16,7 @@ static inline int memregion_alloc(gfp_t gfp)
 {
 	return -ENOMEM;
 }
-void memregion_free(int id)
+static inline void memregion_free(int id)
 {
 }
 #endif
-- 
GitLab


From 19fc5bb93c6bbdce8292b4d7eed04e2fa118d2fe Mon Sep 17 00:00:00 2001
From: Nathan Lynch <nathanl@linux.ibm.com>
Date: Thu, 23 Jun 2022 13:25:09 -0500
Subject: [PATCH 1096/1731] powerpc/xive/spapr: correct bitmap allocation size
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

kasan detects access beyond the end of the xibm->bitmap allocation:

BUG: KASAN: slab-out-of-bounds in _find_first_zero_bit+0x40/0x140
Read of size 8 at addr c00000001d1d0118 by task swapper/0/1

CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.19.0-rc2-00001-g90df023b36dd #28
Call Trace:
[c00000001d98f770] [c0000000012baab8] dump_stack_lvl+0xac/0x108 (unreliable)
[c00000001d98f7b0] [c00000000068faac] print_report+0x37c/0x710
[c00000001d98f880] [c0000000006902c0] kasan_report+0x110/0x354
[c00000001d98f950] [c000000000692324] __asan_load8+0xa4/0xe0
[c00000001d98f970] [c0000000011c6ed0] _find_first_zero_bit+0x40/0x140
[c00000001d98f9b0] [c0000000000dbfbc] xive_spapr_get_ipi+0xcc/0x260
[c00000001d98fa70] [c0000000000d6d28] xive_setup_cpu_ipi+0x1e8/0x450
[c00000001d98fb30] [c000000004032a20] pSeries_smp_probe+0x5c/0x118
[c00000001d98fb60] [c000000004018b44] smp_prepare_cpus+0x944/0x9ac
[c00000001d98fc90] [c000000004009f9c] kernel_init_freeable+0x2d4/0x640
[c00000001d98fd90] [c0000000000131e8] kernel_init+0x28/0x1d0
[c00000001d98fe10] [c00000000000cd54] ret_from_kernel_thread+0x5c/0x64

Allocated by task 0:
 kasan_save_stack+0x34/0x70
 __kasan_kmalloc+0xb4/0xf0
 __kmalloc+0x268/0x540
 xive_spapr_init+0x4d0/0x77c
 pseries_init_irq+0x40/0x27c
 init_IRQ+0x44/0x84
 start_kernel+0x2a4/0x538
 start_here_common+0x1c/0x20

The buggy address belongs to the object at c00000001d1d0118
 which belongs to the cache kmalloc-8 of size 8
The buggy address is located 0 bytes inside of
 8-byte region [c00000001d1d0118, c00000001d1d0120)

The buggy address belongs to the physical page:
page:c00c000000074740 refcount:1 mapcount:0 mapping:0000000000000000 index:0xc00000001d1d0558 pfn:0x1d1d
flags: 0x7ffff000000200(slab|node=0|zone=0|lastcpupid=0x7ffff)
raw: 007ffff000000200 c00000001d0003c8 c00000001d0003c8 c00000001d010480
raw: c00000001d1d0558 0000000001e1000a 00000001ffffffff 0000000000000000
page dumped because: kasan: bad access detected

Memory state around the buggy address:
 c00000001d1d0000: fc 00 fc fc fc fc fc fc fc fc fc fc fc fc fc fc
 c00000001d1d0080: fc fc 00 fc fc fc fc fc fc fc fc fc fc fc fc fc
>c00000001d1d0100: fc fc fc 02 fc fc fc fc fc fc fc fc fc fc fc fc
                            ^
 c00000001d1d0180: fc fc fc fc 04 fc fc fc fc fc fc fc fc fc fc fc
 c00000001d1d0200: fc fc fc fc fc 04 fc fc fc fc fc fc fc fc fc fc

This happens because the allocation uses the wrong unit (bits) when it
should pass (BITS_TO_LONGS(count) * sizeof(long)) or equivalent. With small
numbers of bits, the allocated object can be smaller than sizeof(long),
which results in invalid accesses.

Use bitmap_zalloc() to allocate and initialize the irq bitmap, paired with
bitmap_free() for consistency.

Signed-off-by: Nathan Lynch <nathanl@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220623182509.3985625-1-nathanl@linux.ibm.com
---
 arch/powerpc/sysdev/xive/spapr.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/sysdev/xive/spapr.c b/arch/powerpc/sysdev/xive/spapr.c
index 7d5128676e830..d02911e78cfc1 100644
--- a/arch/powerpc/sysdev/xive/spapr.c
+++ b/arch/powerpc/sysdev/xive/spapr.c
@@ -15,6 +15,7 @@
 #include <linux/of_fdt.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
+#include <linux/bitmap.h>
 #include <linux/cpumask.h>
 #include <linux/mm.h>
 #include <linux/delay.h>
@@ -57,7 +58,7 @@ static int __init xive_irq_bitmap_add(int base, int count)
 	spin_lock_init(&xibm->lock);
 	xibm->base = base;
 	xibm->count = count;
-	xibm->bitmap = kzalloc(xibm->count, GFP_KERNEL);
+	xibm->bitmap = bitmap_zalloc(xibm->count, GFP_KERNEL);
 	if (!xibm->bitmap) {
 		kfree(xibm);
 		return -ENOMEM;
@@ -75,7 +76,7 @@ static void xive_irq_bitmap_remove_all(void)
 
 	list_for_each_entry_safe(xibm, tmp, &xive_irq_bitmaps, list) {
 		list_del(&xibm->list);
-		kfree(xibm->bitmap);
+		bitmap_free(xibm->bitmap);
 		kfree(xibm);
 	}
 }
-- 
GitLab


From 986481618023e18e187646b0fff05a3c337531cb Mon Sep 17 00:00:00 2001
From: Christophe Leroy <christophe.leroy@csgroup.eu>
Date: Thu, 23 Jun 2022 10:56:17 +0200
Subject: [PATCH 1097/1731] powerpc/book3e: Fix PUD allocation size in
 map_kernel_page()

Commit 2fb4706057bc ("powerpc: add support for folded p4d page tables")
erroneously changed PUD setup to a mix of PMD and PUD. Fix it.

While at it, use PTE_TABLE_SIZE instead of PAGE_SIZE for PTE tables
in order to avoid any confusion.

Fixes: 2fb4706057bc ("powerpc: add support for folded p4d page tables")
Cc: stable@vger.kernel.org # v5.8+
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Acked-by: Mike Rapoport <rppt@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/95ddfd6176d53e6c85e13bd1c358359daa56775f.1655974558.git.christophe.leroy@csgroup.eu
---
 arch/powerpc/mm/nohash/book3e_pgtable.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/mm/nohash/book3e_pgtable.c b/arch/powerpc/mm/nohash/book3e_pgtable.c
index 7d4368d055a68..b80fc4a91a534 100644
--- a/arch/powerpc/mm/nohash/book3e_pgtable.c
+++ b/arch/powerpc/mm/nohash/book3e_pgtable.c
@@ -96,8 +96,8 @@ int __ref map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot)
 		pgdp = pgd_offset_k(ea);
 		p4dp = p4d_offset(pgdp, ea);
 		if (p4d_none(*p4dp)) {
-			pmdp = early_alloc_pgtable(PMD_TABLE_SIZE);
-			p4d_populate(&init_mm, p4dp, pmdp);
+			pudp = early_alloc_pgtable(PUD_TABLE_SIZE);
+			p4d_populate(&init_mm, p4dp, pudp);
 		}
 		pudp = pud_offset(p4dp, ea);
 		if (pud_none(*pudp)) {
@@ -106,7 +106,7 @@ int __ref map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot)
 		}
 		pmdp = pmd_offset(pudp, ea);
 		if (!pmd_present(*pmdp)) {
-			ptep = early_alloc_pgtable(PAGE_SIZE);
+			ptep = early_alloc_pgtable(PTE_TABLE_SIZE);
 			pmd_populate_kernel(&init_mm, pmdp, ptep);
 		}
 		ptep = pte_offset_kernel(pmdp, ea);
-- 
GitLab


From 16d584d2fc8f4ea36203af45a76becd7093586f1 Mon Sep 17 00:00:00 2001
From: Liang He <windhl@126.com>
Date: Wed, 22 Jun 2022 12:06:21 +0800
Subject: [PATCH 1098/1731] net/dsa/hirschmann: Add missing of_node_get() in
 hellcreek_led_setup()

of_find_node_by_name() will decrease the refcount of its first arg and
we need a of_node_get() to keep refcount balance.

Fixes: 7d9ee2e8ff15 ("net: dsa: hellcreek: Add PTP status LEDs")
Signed-off-by: Liang He <windhl@126.com>
Link: https://lore.kernel.org/r/20220622040621.4094304-1-windhl@126.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/dsa/hirschmann/hellcreek_ptp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/dsa/hirschmann/hellcreek_ptp.c b/drivers/net/dsa/hirschmann/hellcreek_ptp.c
index 2572c6087bb5a..b28baab6d56a1 100644
--- a/drivers/net/dsa/hirschmann/hellcreek_ptp.c
+++ b/drivers/net/dsa/hirschmann/hellcreek_ptp.c
@@ -300,6 +300,7 @@ static int hellcreek_led_setup(struct hellcreek *hellcreek)
 	const char *label, *state;
 	int ret = -EINVAL;
 
+	of_node_get(hellcreek->dev->of_node);
 	leds = of_find_node_by_name(hellcreek->dev->of_node, "leds");
 	if (!leds) {
 		dev_err(hellcreek->dev, "No LEDs specified in device tree!\n");
-- 
GitLab


From 7c97bc0128b2eecc703106112679a69d446d1a12 Mon Sep 17 00:00:00 2001
From: Doug Berger <opendmb@gmail.com>
Date: Wed, 22 Jun 2022 20:02:04 -0700
Subject: [PATCH 1099/1731] net: dsa: bcm_sf2: force pause link settings

The pause settings reported by the PHY should also be applied to the GMII port
status override otherwise the switch will not generate pause frames towards the
link partner despite the advertisement saying otherwise.

Fixes: 246d7f773c13 ("net: dsa: add Broadcom SF2 switch driver")
Signed-off-by: Doug Berger <opendmb@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20220623030204.1966851-1-f.fainelli@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/dsa/bcm_sf2.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c
index 87e81c636339f..be0edfa093d04 100644
--- a/drivers/net/dsa/bcm_sf2.c
+++ b/drivers/net/dsa/bcm_sf2.c
@@ -878,6 +878,11 @@ static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
 		if (duplex == DUPLEX_FULL)
 			reg |= DUPLX_MODE;
 
+		if (tx_pause)
+			reg |= TXFLOW_CNTL;
+		if (rx_pause)
+			reg |= RXFLOW_CNTL;
+
 		core_writel(priv, reg, offset);
 	}
 
-- 
GitLab


From 6886da5f49e6d86aad76807a93f3eef5e4f01b10 Mon Sep 17 00:00:00 2001
From: Liam Howlett <liam.howlett@oracle.com>
Date: Fri, 24 Jun 2022 01:17:58 +0000
Subject: [PATCH 1100/1731] powerpc/prom_init: Fix kernel config grep

When searching for config options, use the KCONFIG_CONFIG shell variable
so that builds using non-standard config locations work.

Fixes: 26deb04342e3 ("powerpc: prepare string/mem functions for KASAN")
Cc: stable@vger.kernel.org # v5.2+
Signed-off-by: Liam R. Howlett <Liam.Howlett@oracle.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220624011745.4060795-1-Liam.Howlett@oracle.com
---
 arch/powerpc/kernel/prom_init_check.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/kernel/prom_init_check.sh b/arch/powerpc/kernel/prom_init_check.sh
index b183ab9c5107c..dfa5f729f774d 100644
--- a/arch/powerpc/kernel/prom_init_check.sh
+++ b/arch/powerpc/kernel/prom_init_check.sh
@@ -13,7 +13,7 @@
 # If you really need to reference something from prom_init.o add
 # it to the list below:
 
-grep "^CONFIG_KASAN=y$" .config >/dev/null
+grep "^CONFIG_KASAN=y$" ${KCONFIG_CONFIG} >/dev/null
 if [ $? -eq 0 ]
 then
 	MEM_FUNCS="__memcpy __memset"
-- 
GitLab


From ad887a507d7386de09a532c5d303ed659eba2cfb Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Wed, 22 Jun 2022 13:54:16 +0200
Subject: [PATCH 1101/1731] net/ncsi: use proper "mellanox" DT vendor prefix

"mlx" Devicetree vendor prefix is not documented and instead "mellanox"
should be used.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220622115416.7400-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/ncsi/ncsi-manage.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/net/ncsi/ncsi-manage.c b/net/ncsi/ncsi-manage.c
index 78814417d753f..80713febfac6d 100644
--- a/net/ncsi/ncsi-manage.c
+++ b/net/ncsi/ncsi-manage.c
@@ -1803,7 +1803,8 @@ struct ncsi_dev *ncsi_register_dev(struct net_device *dev,
 	pdev = to_platform_device(dev->dev.parent);
 	if (pdev) {
 		np = pdev->dev.of_node;
-		if (np && of_get_property(np, "mlx,multi-host", NULL))
+		if (np && (of_get_property(np, "mellanox,multi-host", NULL) ||
+			   of_get_property(np, "mlx,multi-host", NULL)))
 			ndp->mlx_multi_host = true;
 	}
 
-- 
GitLab


From 1228b34c8d0ecf6de18c4c95d22f60cc8607c50a Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Wed, 22 Jun 2022 15:02:20 +0000
Subject: [PATCH 1102/1731] net: clear msg_get_inq in __sys_recvfrom() and
 __copy_msghdr_from_user()

syzbot reported uninit-value in tcp_recvmsg() [1]

Issue here is that msg->msg_get_inq should have been cleared,
otherwise tcp_recvmsg() might read garbage and perform
more work than needed, or have undefined behavior.

Given CONFIG_INIT_STACK_ALL_ZERO=y is probably going to be
the default soon, I chose to change __sys_recvfrom() to clear
all fields but msghdr.addr which might be not NULL.

For __copy_msghdr_from_user(), I added an explicit clear
of kmsg->msg_get_inq.

[1]
BUG: KMSAN: uninit-value in tcp_recvmsg+0x6cf/0xb60 net/ipv4/tcp.c:2557
tcp_recvmsg+0x6cf/0xb60 net/ipv4/tcp.c:2557
inet_recvmsg+0x13a/0x5a0 net/ipv4/af_inet.c:850
sock_recvmsg_nosec net/socket.c:995 [inline]
sock_recvmsg net/socket.c:1013 [inline]
__sys_recvfrom+0x696/0x900 net/socket.c:2176
__do_sys_recvfrom net/socket.c:2194 [inline]
__se_sys_recvfrom net/socket.c:2190 [inline]
__x64_sys_recvfrom+0x122/0x1c0 net/socket.c:2190
do_syscall_x64 arch/x86/entry/common.c:50 [inline]
do_syscall_64+0x3d/0xb0 arch/x86/entry/common.c:80
entry_SYSCALL_64_after_hwframe+0x46/0xb0

Local variable msg created at:
__sys_recvfrom+0x81/0x900 net/socket.c:2154
__do_sys_recvfrom net/socket.c:2194 [inline]
__se_sys_recvfrom net/socket.c:2190 [inline]
__x64_sys_recvfrom+0x122/0x1c0 net/socket.c:2190

CPU: 0 PID: 3493 Comm: syz-executor170 Not tainted 5.19.0-rc3-syzkaller-30868-g4b28366af7d9 #0
Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011

Fixes: f94fd25cb0aa ("tcp: pass back data left in socket after receive")
Reported-by: syzbot <syzkaller@googlegroups.com>
Signed-off-by: Eric Dumazet <edumazet@google.com>
Reviewed-by: Jens Axboe <axboe@kernel.dk>
Tested-by: Alexander Potapenko<glider@google.com>
Link: https://lore.kernel.org/r/20220622150220.1091182-1-edumazet@google.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/socket.c | 16 ++++++----------
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/net/socket.c b/net/socket.c
index 2bc8773d9dc5e..96300cdc06251 100644
--- a/net/socket.c
+++ b/net/socket.c
@@ -2149,10 +2149,13 @@ SYSCALL_DEFINE4(send, int, fd, void __user *, buff, size_t, len,
 int __sys_recvfrom(int fd, void __user *ubuf, size_t size, unsigned int flags,
 		   struct sockaddr __user *addr, int __user *addr_len)
 {
+	struct sockaddr_storage address;
+	struct msghdr msg = {
+		/* Save some cycles and don't copy the address if not needed */
+		.msg_name = addr ? (struct sockaddr *)&address : NULL,
+	};
 	struct socket *sock;
 	struct iovec iov;
-	struct msghdr msg;
-	struct sockaddr_storage address;
 	int err, err2;
 	int fput_needed;
 
@@ -2163,14 +2166,6 @@ int __sys_recvfrom(int fd, void __user *ubuf, size_t size, unsigned int flags,
 	if (!sock)
 		goto out;
 
-	msg.msg_control = NULL;
-	msg.msg_controllen = 0;
-	/* Save some cycles and don't copy the address if not needed */
-	msg.msg_name = addr ? (struct sockaddr *)&address : NULL;
-	/* We assume all kernel code knows the size of sockaddr_storage */
-	msg.msg_namelen = 0;
-	msg.msg_iocb = NULL;
-	msg.msg_flags = 0;
 	if (sock->file->f_flags & O_NONBLOCK)
 		flags |= MSG_DONTWAIT;
 	err = sock_recvmsg(sock, &msg, flags);
@@ -2375,6 +2370,7 @@ int __copy_msghdr_from_user(struct msghdr *kmsg,
 		return -EFAULT;
 
 	kmsg->msg_control_is_user = true;
+	kmsg->msg_get_inq = 0;
 	kmsg->msg_control_user = msg.msg_control;
 	kmsg->msg_controllen = msg.msg_controllen;
 	kmsg->msg_flags = msg.msg_flags;
-- 
GitLab


From b968080808f7f28b89aa495b7402ba48eb17ee93 Mon Sep 17 00:00:00 2001
From: Dimitris Michailidis <d.michailidis@fungible.com>
Date: Wed, 22 Jun 2022 17:02:34 -0700
Subject: [PATCH 1103/1731] selftests/net: pass ipv6_args to udpgso_bench's
 IPv6 TCP test

udpgso_bench.sh has been running its IPv6 TCP test with IPv4 arguments
since its initial conmit. Looks like a typo.

Fixes: 3a687bef148d ("selftests: udp gso benchmark")
Cc: willemb@google.com
Signed-off-by: Dimitris Michailidis <dmichail@fungible.com>
Acked-by: Willem de Bruijn <willemb@google.com>
Link: https://lore.kernel.org/r/20220623000234.61774-1-dmichail@fungible.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 tools/testing/selftests/net/udpgso_bench.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/testing/selftests/net/udpgso_bench.sh b/tools/testing/selftests/net/udpgso_bench.sh
index 80b5d352702e5..dc932fd653634 100755
--- a/tools/testing/selftests/net/udpgso_bench.sh
+++ b/tools/testing/selftests/net/udpgso_bench.sh
@@ -120,7 +120,7 @@ run_all() {
 	run_udp "${ipv4_args}"
 
 	echo "ipv6"
-	run_tcp "${ipv4_args}"
+	run_tcp "${ipv6_args}"
 	run_udp "${ipv6_args}"
 }
 
-- 
GitLab


From 745bbc0995c25917dfafb645b8efb29813ef9e0b Mon Sep 17 00:00:00 2001
From: Hyunchul Lee <hyc.lee@gmail.com>
Date: Tue, 14 Jun 2022 08:25:50 +0900
Subject: [PATCH 1104/1731] ksmbd: remove duplicate flag set in smb2_write

The writethrough flag is set again if is_rdma_channel is false.

Signed-off-by: Hyunchul Lee <hyc.lee@gmail.com>
Acked-by: Namjae Jeon <linkinjeon@kernel.org>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/ksmbd/smb2pdu.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/fs/ksmbd/smb2pdu.c b/fs/ksmbd/smb2pdu.c
index e6f4ccc12f494..e359308678935 100644
--- a/fs/ksmbd/smb2pdu.c
+++ b/fs/ksmbd/smb2pdu.c
@@ -6490,6 +6490,7 @@ int smb2_write(struct ksmbd_work *work)
 		goto out;
 	}
 
+	ksmbd_debug(SMB, "flags %u\n", le32_to_cpu(req->Flags));
 	if (le32_to_cpu(req->Flags) & SMB2_WRITEFLAG_WRITE_THROUGH)
 		writethrough = true;
 
@@ -6505,10 +6506,6 @@ int smb2_write(struct ksmbd_work *work)
 		data_buf = (char *)(((char *)&req->hdr.ProtocolId) +
 				    le16_to_cpu(req->DataOffset));
 
-		ksmbd_debug(SMB, "flags %u\n", le32_to_cpu(req->Flags));
-		if (le32_to_cpu(req->Flags) & SMB2_WRITEFLAG_WRITE_THROUGH)
-			writethrough = true;
-
 		ksmbd_debug(SMB, "filename %pd, offset %lld, len %zu\n",
 			    fp->filp->f_path.dentry, offset, length);
 		err = ksmbd_vfs_write(work, fp, data_buf, length, &offset,
-- 
GitLab


From 18e39fb960e6a908ac5230b57e3d0d6c25232368 Mon Sep 17 00:00:00 2001
From: Namjae Jeon <linkinjeon@kernel.org>
Date: Sun, 19 Jun 2022 22:35:48 +0900
Subject: [PATCH 1105/1731] ksmbd: set the range of bytes to zero without
 extending file size in FSCTL_ZERO_DATA

generic/091, 263 test failed since commit f66f8b94e7f2 ("cifs: when
extending a file with falloc we should make files not-sparse").
FSCTL_ZERO_DATA sets the range of bytes to zero without extending file
size. The VFS_FALLOCATE_FL_KEEP_SIZE flag should be used even on
non-sparse files.

Cc: stable@vger.kernel.org
Reviewed-by: Hyunchul Lee <hyc.lee@gmail.com>
Signed-off-by: Namjae Jeon <linkinjeon@kernel.org>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/ksmbd/vfs.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/fs/ksmbd/vfs.c b/fs/ksmbd/vfs.c
index dcdd07c6efffd..f194bf764f9f0 100644
--- a/fs/ksmbd/vfs.c
+++ b/fs/ksmbd/vfs.c
@@ -1015,7 +1015,9 @@ int ksmbd_vfs_zero_data(struct ksmbd_work *work, struct ksmbd_file *fp,
 				     FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE,
 				     off, len);
 
-	return vfs_fallocate(fp->filp, FALLOC_FL_ZERO_RANGE, off, len);
+	return vfs_fallocate(fp->filp,
+			     FALLOC_FL_ZERO_RANGE | FALLOC_FL_KEEP_SIZE,
+			     off, len);
 }
 
 int ksmbd_vfs_fqar_lseek(struct ksmbd_file *fp, loff_t start, loff_t length,
-- 
GitLab


From b5e5f9dfc915ff05b41dff56181e1dae101712bd Mon Sep 17 00:00:00 2001
From: Namjae Jeon <linkinjeon@kernel.org>
Date: Sun, 19 Jun 2022 22:37:17 +0900
Subject: [PATCH 1106/1731] ksmbd: check invalid FileOffset and BeyondFinalZero
 in FSCTL_ZERO_DATA

FileOffset should not be greater than BeyondFinalZero in FSCTL_ZERO_DATA.
And don't call ksmbd_vfs_zero_data() if length is zero.

Cc: stable@vger.kernel.org
Reviewed-by: Hyunchul Lee <hyc.lee@gmail.com>
Signed-off-by: Namjae Jeon <linkinjeon@kernel.org>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/ksmbd/smb2pdu.c | 27 +++++++++++++++++----------
 1 file changed, 17 insertions(+), 10 deletions(-)

diff --git a/fs/ksmbd/smb2pdu.c b/fs/ksmbd/smb2pdu.c
index e359308678935..94ab1dcd80e7b 100644
--- a/fs/ksmbd/smb2pdu.c
+++ b/fs/ksmbd/smb2pdu.c
@@ -7700,7 +7700,7 @@ int smb2_ioctl(struct ksmbd_work *work)
 	{
 		struct file_zero_data_information *zero_data;
 		struct ksmbd_file *fp;
-		loff_t off, len;
+		loff_t off, len, bfz;
 
 		if (!test_tree_conn_flag(work->tcon, KSMBD_TREE_CONN_FLAG_WRITABLE)) {
 			ksmbd_debug(SMB,
@@ -7717,19 +7717,26 @@ int smb2_ioctl(struct ksmbd_work *work)
 		zero_data =
 			(struct file_zero_data_information *)&req->Buffer[0];
 
-		fp = ksmbd_lookup_fd_fast(work, id);
-		if (!fp) {
-			ret = -ENOENT;
+		off = le64_to_cpu(zero_data->FileOffset);
+		bfz = le64_to_cpu(zero_data->BeyondFinalZero);
+		if (off > bfz) {
+			ret = -EINVAL;
 			goto out;
 		}
 
-		off = le64_to_cpu(zero_data->FileOffset);
-		len = le64_to_cpu(zero_data->BeyondFinalZero) - off;
+		len = bfz - off;
+		if (len) {
+			fp = ksmbd_lookup_fd_fast(work, id);
+			if (!fp) {
+				ret = -ENOENT;
+				goto out;
+			}
 
-		ret = ksmbd_vfs_zero_data(work, fp, off, len);
-		ksmbd_fd_put(work, fp);
-		if (ret < 0)
-			goto out;
+			ret = ksmbd_vfs_zero_data(work, fp, off, len);
+			ksmbd_fd_put(work, fp);
+			if (ret < 0)
+				goto out;
+		}
 		break;
 	}
 	case FSCTL_QUERY_ALLOCATED_RANGES:
-- 
GitLab


From 40f2f3e94178d45e4ee6078effba2dfc76f6f5ba Mon Sep 17 00:00:00 2001
From: Eli Cohen <elic@nvidia.com>
Date: Mon, 13 Jun 2022 10:59:57 +0300
Subject: [PATCH 1107/1731] vdpa/mlx5: Update Control VQ callback information

The control VQ specific information is stored in the dedicated struct
mlx5_control_vq. When the callback is updated through
mlx5_vdpa_set_vq_cb(), make sure to update the control VQ struct.

Fixes: 5262912ef3cf ("vdpa/mlx5: Add support for control VQ and MAC setting")
Signed-off-by: Eli Cohen <elic@nvidia.com>
Message-Id: <20220613075958.511064-1-elic@nvidia.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com)
---
 drivers/vdpa/mlx5/net/mlx5_vnet.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c
index 1b6d46b86f810..789c078ff1afc 100644
--- a/drivers/vdpa/mlx5/net/mlx5_vnet.c
+++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c
@@ -1962,6 +1962,8 @@ static void mlx5_vdpa_set_vq_cb(struct vdpa_device *vdev, u16 idx, struct vdpa_c
 	struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev);
 
 	ndev->event_cbs[idx] = *cb;
+	if (is_ctrl_vq_idx(mvdev, idx))
+		mvdev->cvq.event_cb = *cb;
 }
 
 static void mlx5_cvq_notify(struct vringh *vring)
-- 
GitLab


From ace9252446ec615cd79a5f77d90edb25c0b9d024 Mon Sep 17 00:00:00 2001
From: Eli Cohen <elic@nvidia.com>
Date: Mon, 13 Jun 2022 10:59:58 +0300
Subject: [PATCH 1108/1731] vdpa/mlx5: Initialize CVQ vringh only once
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Currently, CVQ vringh is initialized inside setup_virtqueues() which is
called every time a memory update is done. This is undesirable since it
resets all the context of the vring, including the available and used
indices.

Move the initialization to mlx5_vdpa_set_status() when
VIRTIO_CONFIG_S_DRIVER_OK is set.

Signed-off-by: Eli Cohen <elic@nvidia.com>
Message-Id: <20220613075958.511064-2-elic@nvidia.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
---
 drivers/vdpa/mlx5/net/mlx5_vnet.c | 31 ++++++++++++++++++++-----------
 1 file changed, 20 insertions(+), 11 deletions(-)

diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c
index 789c078ff1afc..e85c1d71f4ed2 100644
--- a/drivers/vdpa/mlx5/net/mlx5_vnet.c
+++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c
@@ -2176,7 +2176,6 @@ static int verify_driver_features(struct mlx5_vdpa_dev *mvdev, u64 features)
 static int setup_virtqueues(struct mlx5_vdpa_dev *mvdev)
 {
 	struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev);
-	struct mlx5_control_vq *cvq = &mvdev->cvq;
 	int err;
 	int i;
 
@@ -2186,16 +2185,6 @@ static int setup_virtqueues(struct mlx5_vdpa_dev *mvdev)
 			goto err_vq;
 	}
 
-	if (mvdev->actual_features & BIT_ULL(VIRTIO_NET_F_CTRL_VQ)) {
-		err = vringh_init_iotlb(&cvq->vring, mvdev->actual_features,
-					MLX5_CVQ_MAX_ENT, false,
-					(struct vring_desc *)(uintptr_t)cvq->desc_addr,
-					(struct vring_avail *)(uintptr_t)cvq->driver_addr,
-					(struct vring_used *)(uintptr_t)cvq->device_addr);
-		if (err)
-			goto err_vq;
-	}
-
 	return 0;
 
 err_vq:
@@ -2468,6 +2457,21 @@ static void clear_vqs_ready(struct mlx5_vdpa_net *ndev)
 	ndev->mvdev.cvq.ready = false;
 }
 
+static int setup_cvq_vring(struct mlx5_vdpa_dev *mvdev)
+{
+	struct mlx5_control_vq *cvq = &mvdev->cvq;
+	int err = 0;
+
+	if (mvdev->actual_features & BIT_ULL(VIRTIO_NET_F_CTRL_VQ))
+		err = vringh_init_iotlb(&cvq->vring, mvdev->actual_features,
+					MLX5_CVQ_MAX_ENT, false,
+					(struct vring_desc *)(uintptr_t)cvq->desc_addr,
+					(struct vring_avail *)(uintptr_t)cvq->driver_addr,
+					(struct vring_used *)(uintptr_t)cvq->device_addr);
+
+	return err;
+}
+
 static void mlx5_vdpa_set_status(struct vdpa_device *vdev, u8 status)
 {
 	struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev);
@@ -2480,6 +2484,11 @@ static void mlx5_vdpa_set_status(struct vdpa_device *vdev, u8 status)
 
 	if ((status ^ ndev->mvdev.status) & VIRTIO_CONFIG_S_DRIVER_OK) {
 		if (status & VIRTIO_CONFIG_S_DRIVER_OK) {
+			err = setup_cvq_vring(mvdev);
+			if (err) {
+				mlx5_vdpa_warn(mvdev, "failed to setup control VQ vring\n");
+				goto err_setup;
+			}
 			err = setup_driver(mvdev);
 			if (err) {
 				mlx5_vdpa_warn(mvdev, "failed to setup driver\n");
-- 
GitLab


From 0e0348ac3f0a6e6606f1aa5acb1803ada913aa3d Mon Sep 17 00:00:00 2001
From: Parav Pandit <parav@nvidia.com>
Date: Mon, 13 Jun 2022 22:52:23 +0300
Subject: [PATCH 1109/1731] vduse: Tie vduse mgmtdev and its device

vduse devices are not backed by any real devices such as PCI. Hence it
doesn't have any parent device linked to it.

Kernel driver model in [1] suggests to avoid an empty device
release callback.

Hence tie the mgmtdevice object's life cycle to an allocate dummy struct
device instead of static one.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/core-api/kobject.rst?h=v5.18-rc7#n284

Signed-off-by: Parav Pandit <parav@nvidia.com>
Message-Id: <20220613195223.473966-1-parav@nvidia.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Xie Yongji <xieyongji@bytedance.com>
Acked-by: Jason Wang <jasowang@redhat.com>
---
 drivers/vdpa/vdpa_user/vduse_dev.c | 60 ++++++++++++++++++------------
 1 file changed, 37 insertions(+), 23 deletions(-)

diff --git a/drivers/vdpa/vdpa_user/vduse_dev.c b/drivers/vdpa/vdpa_user/vduse_dev.c
index 776ad7496f534..3bc27de58f46b 100644
--- a/drivers/vdpa/vdpa_user/vduse_dev.c
+++ b/drivers/vdpa/vdpa_user/vduse_dev.c
@@ -1476,16 +1476,12 @@ static char *vduse_devnode(struct device *dev, umode_t *mode)
 	return kasprintf(GFP_KERNEL, "vduse/%s", dev_name(dev));
 }
 
-static void vduse_mgmtdev_release(struct device *dev)
-{
-}
-
-static struct device vduse_mgmtdev = {
-	.init_name = "vduse",
-	.release = vduse_mgmtdev_release,
+struct vduse_mgmt_dev {
+	struct vdpa_mgmt_dev mgmt_dev;
+	struct device dev;
 };
 
-static struct vdpa_mgmt_dev mgmt_dev;
+static struct vduse_mgmt_dev *vduse_mgmt;
 
 static int vduse_dev_init_vdpa(struct vduse_dev *dev, const char *name)
 {
@@ -1510,7 +1506,7 @@ static int vduse_dev_init_vdpa(struct vduse_dev *dev, const char *name)
 	}
 	set_dma_ops(&vdev->vdpa.dev, &vduse_dev_dma_ops);
 	vdev->vdpa.dma_dev = &vdev->vdpa.dev;
-	vdev->vdpa.mdev = &mgmt_dev;
+	vdev->vdpa.mdev = &vduse_mgmt->mgmt_dev;
 
 	return 0;
 }
@@ -1556,34 +1552,52 @@ static struct virtio_device_id id_table[] = {
 	{ 0 },
 };
 
-static struct vdpa_mgmt_dev mgmt_dev = {
-	.device = &vduse_mgmtdev,
-	.id_table = id_table,
-	.ops = &vdpa_dev_mgmtdev_ops,
-};
+static void vduse_mgmtdev_release(struct device *dev)
+{
+	struct vduse_mgmt_dev *mgmt_dev;
+
+	mgmt_dev = container_of(dev, struct vduse_mgmt_dev, dev);
+	kfree(mgmt_dev);
+}
 
 static int vduse_mgmtdev_init(void)
 {
 	int ret;
 
-	ret = device_register(&vduse_mgmtdev);
-	if (ret)
+	vduse_mgmt = kzalloc(sizeof(*vduse_mgmt), GFP_KERNEL);
+	if (!vduse_mgmt)
+		return -ENOMEM;
+
+	ret = dev_set_name(&vduse_mgmt->dev, "vduse");
+	if (ret) {
+		kfree(vduse_mgmt);
 		return ret;
+	}
 
-	ret = vdpa_mgmtdev_register(&mgmt_dev);
+	vduse_mgmt->dev.release = vduse_mgmtdev_release;
+
+	ret = device_register(&vduse_mgmt->dev);
 	if (ret)
-		goto err;
+		goto dev_reg_err;
 
-	return 0;
-err:
-	device_unregister(&vduse_mgmtdev);
+	vduse_mgmt->mgmt_dev.id_table = id_table;
+	vduse_mgmt->mgmt_dev.ops = &vdpa_dev_mgmtdev_ops;
+	vduse_mgmt->mgmt_dev.device = &vduse_mgmt->dev;
+	ret = vdpa_mgmtdev_register(&vduse_mgmt->mgmt_dev);
+	if (ret)
+		device_unregister(&vduse_mgmt->dev);
+
+	return ret;
+
+dev_reg_err:
+	put_device(&vduse_mgmt->dev);
 	return ret;
 }
 
 static void vduse_mgmtdev_exit(void)
 {
-	vdpa_mgmtdev_unregister(&mgmt_dev);
-	device_unregister(&vduse_mgmtdev);
+	vdpa_mgmtdev_unregister(&vduse_mgmt->mgmt_dev);
+	device_unregister(&vduse_mgmt->dev);
 }
 
 static int vduse_init(void)
-- 
GitLab


From a7722890fdfb2aaeb6b02d68bb0f1e411e58d539 Mon Sep 17 00:00:00 2001
From: "huangjie.albert" <huangjie.albert@bytedance.com>
Date: Fri, 17 Jun 2022 10:04:11 +0800
Subject: [PATCH 1110/1731] virtio_ring : keep used_wrap_counter in
 vq->last_used_idx
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

the used_wrap_counter and the vq->last_used_idx may get
out of sync if they are separate assignment，and interrupt
might use an incorrect value to check for the used index.

for example:OOB access
ksoftirqd may consume the packet and it will call:
virtnet_poll
	-->virtnet_receive
		-->virtqueue_get_buf_ctx
			-->virtqueue_get_buf_ctx_packed
and in virtqueue_get_buf_ctx_packed:

vq->last_used_idx += vq->packed.desc_state[id].num;
if (unlikely(vq->last_used_idx >= vq->packed.vring.num)) {
         vq->last_used_idx -= vq->packed.vring.num;
         vq->packed.used_wrap_counter ^= 1;
}

if at the same time, there comes a vring interrupt，in vring_interrupt:
we will call:
vring_interrupt
	-->more_used
		-->more_used_packed
			-->is_used_desc_packed
in is_used_desc_packed, the last_used_idx maybe >= vq->packed.vring.num.
so this could case a memory out of bounds bug.

this patch is to keep the used_wrap_counter in vq->last_used_idx
so we can get the correct value to check for used index in interrupt.

v3->v4:
- use READ_ONCE/WRITE_ONCE to get/set vq->last_used_idx

v2->v3:
- add inline function to get used_wrap_counter and last_used
- when use vq->last_used_idx, only read once
  if vq->last_used_idx is read twice, the values can be inconsistent.
- use last_used_idx & ~(-(1 << VRING_PACKED_EVENT_F_WRAP_CTR))
  to get the all bits below VRING_PACKED_EVENT_F_WRAP_CTR

v1->v2:
- reuse the VRING_PACKED_EVENT_F_WRAP_CTR
- Remove parameter judgment in is_used_desc_packed,
because it can't be illegal

Signed-off-by: huangjie.albert <huangjie.albert@bytedance.com>
Message-Id: <20220617020411.80367-1-huangjie.albert@bytedance.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 drivers/virtio/virtio_ring.c | 75 ++++++++++++++++++++++--------------
 1 file changed, 47 insertions(+), 28 deletions(-)

diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c
index 13a7348cedfff..ef30465dd39cb 100644
--- a/drivers/virtio/virtio_ring.c
+++ b/drivers/virtio/virtio_ring.c
@@ -111,7 +111,12 @@ struct vring_virtqueue {
 	/* Number we've added since last sync. */
 	unsigned int num_added;
 
-	/* Last used index we've seen. */
+	/* Last used index  we've seen.
+	 * for split ring, it just contains last used index
+	 * for packed ring:
+	 * bits up to VRING_PACKED_EVENT_F_WRAP_CTR include the last used index.
+	 * bits from VRING_PACKED_EVENT_F_WRAP_CTR include the used wrap counter.
+	 */
 	u16 last_used_idx;
 
 	/* Hint for event idx: already triggered no need to disable. */
@@ -154,9 +159,6 @@ struct vring_virtqueue {
 			/* Driver ring wrap counter. */
 			bool avail_wrap_counter;
 
-			/* Device ring wrap counter. */
-			bool used_wrap_counter;
-
 			/* Avail used flags. */
 			u16 avail_used_flags;
 
@@ -973,6 +975,15 @@ static struct virtqueue *vring_create_virtqueue_split(
 /*
  * Packed ring specific functions - *_packed().
  */
+static inline bool packed_used_wrap_counter(u16 last_used_idx)
+{
+	return !!(last_used_idx & (1 << VRING_PACKED_EVENT_F_WRAP_CTR));
+}
+
+static inline u16 packed_last_used(u16 last_used_idx)
+{
+	return last_used_idx & ~(-(1 << VRING_PACKED_EVENT_F_WRAP_CTR));
+}
 
 static void vring_unmap_extra_packed(const struct vring_virtqueue *vq,
 				     struct vring_desc_extra *extra)
@@ -1406,8 +1417,14 @@ static inline bool is_used_desc_packed(const struct vring_virtqueue *vq,
 
 static inline bool more_used_packed(const struct vring_virtqueue *vq)
 {
-	return is_used_desc_packed(vq, vq->last_used_idx,
-			vq->packed.used_wrap_counter);
+	u16 last_used;
+	u16 last_used_idx;
+	bool used_wrap_counter;
+
+	last_used_idx = READ_ONCE(vq->last_used_idx);
+	last_used = packed_last_used(last_used_idx);
+	used_wrap_counter = packed_used_wrap_counter(last_used_idx);
+	return is_used_desc_packed(vq, last_used, used_wrap_counter);
 }
 
 static void *virtqueue_get_buf_ctx_packed(struct virtqueue *_vq,
@@ -1415,7 +1432,8 @@ static void *virtqueue_get_buf_ctx_packed(struct virtqueue *_vq,
 					  void **ctx)
 {
 	struct vring_virtqueue *vq = to_vvq(_vq);
-	u16 last_used, id;
+	u16 last_used, id, last_used_idx;
+	bool used_wrap_counter;
 	void *ret;
 
 	START_USE(vq);
@@ -1434,7 +1452,9 @@ static void *virtqueue_get_buf_ctx_packed(struct virtqueue *_vq,
 	/* Only get used elements after they have been exposed by host. */
 	virtio_rmb(vq->weak_barriers);
 
-	last_used = vq->last_used_idx;
+	last_used_idx = READ_ONCE(vq->last_used_idx);
+	used_wrap_counter = packed_used_wrap_counter(last_used_idx);
+	last_used = packed_last_used(last_used_idx);
 	id = le16_to_cpu(vq->packed.vring.desc[last_used].id);
 	*len = le32_to_cpu(vq->packed.vring.desc[last_used].len);
 
@@ -1451,12 +1471,15 @@ static void *virtqueue_get_buf_ctx_packed(struct virtqueue *_vq,
 	ret = vq->packed.desc_state[id].data;
 	detach_buf_packed(vq, id, ctx);
 
-	vq->last_used_idx += vq->packed.desc_state[id].num;
-	if (unlikely(vq->last_used_idx >= vq->packed.vring.num)) {
-		vq->last_used_idx -= vq->packed.vring.num;
-		vq->packed.used_wrap_counter ^= 1;
+	last_used += vq->packed.desc_state[id].num;
+	if (unlikely(last_used >= vq->packed.vring.num)) {
+		last_used -= vq->packed.vring.num;
+		used_wrap_counter ^= 1;
 	}
 
+	last_used = (last_used | (used_wrap_counter << VRING_PACKED_EVENT_F_WRAP_CTR));
+	WRITE_ONCE(vq->last_used_idx, last_used);
+
 	/*
 	 * If we expect an interrupt for the next entry, tell host
 	 * by writing event index and flush out the write before
@@ -1465,9 +1488,7 @@ static void *virtqueue_get_buf_ctx_packed(struct virtqueue *_vq,
 	if (vq->packed.event_flags_shadow == VRING_PACKED_EVENT_FLAG_DESC)
 		virtio_store_mb(vq->weak_barriers,
 				&vq->packed.vring.driver->off_wrap,
-				cpu_to_le16(vq->last_used_idx |
-					(vq->packed.used_wrap_counter <<
-					 VRING_PACKED_EVENT_F_WRAP_CTR)));
+				cpu_to_le16(vq->last_used_idx));
 
 	LAST_ADD_TIME_INVALID(vq);
 
@@ -1499,9 +1520,7 @@ static unsigned int virtqueue_enable_cb_prepare_packed(struct virtqueue *_vq)
 
 	if (vq->event) {
 		vq->packed.vring.driver->off_wrap =
-			cpu_to_le16(vq->last_used_idx |
-				(vq->packed.used_wrap_counter <<
-				 VRING_PACKED_EVENT_F_WRAP_CTR));
+			cpu_to_le16(vq->last_used_idx);
 		/*
 		 * We need to update event offset and event wrap
 		 * counter first before updating event flags.
@@ -1518,8 +1537,7 @@ static unsigned int virtqueue_enable_cb_prepare_packed(struct virtqueue *_vq)
 	}
 
 	END_USE(vq);
-	return vq->last_used_idx | ((u16)vq->packed.used_wrap_counter <<
-			VRING_PACKED_EVENT_F_WRAP_CTR);
+	return vq->last_used_idx;
 }
 
 static bool virtqueue_poll_packed(struct virtqueue *_vq, u16 off_wrap)
@@ -1537,7 +1555,7 @@ static bool virtqueue_poll_packed(struct virtqueue *_vq, u16 off_wrap)
 static bool virtqueue_enable_cb_delayed_packed(struct virtqueue *_vq)
 {
 	struct vring_virtqueue *vq = to_vvq(_vq);
-	u16 used_idx, wrap_counter;
+	u16 used_idx, wrap_counter, last_used_idx;
 	u16 bufs;
 
 	START_USE(vq);
@@ -1550,9 +1568,10 @@ static bool virtqueue_enable_cb_delayed_packed(struct virtqueue *_vq)
 	if (vq->event) {
 		/* TODO: tune this threshold */
 		bufs = (vq->packed.vring.num - vq->vq.num_free) * 3 / 4;
-		wrap_counter = vq->packed.used_wrap_counter;
+		last_used_idx = READ_ONCE(vq->last_used_idx);
+		wrap_counter = packed_used_wrap_counter(last_used_idx);
 
-		used_idx = vq->last_used_idx + bufs;
+		used_idx = packed_last_used(last_used_idx) + bufs;
 		if (used_idx >= vq->packed.vring.num) {
 			used_idx -= vq->packed.vring.num;
 			wrap_counter ^= 1;
@@ -1582,9 +1601,10 @@ static bool virtqueue_enable_cb_delayed_packed(struct virtqueue *_vq)
 	 */
 	virtio_mb(vq->weak_barriers);
 
-	if (is_used_desc_packed(vq,
-				vq->last_used_idx,
-				vq->packed.used_wrap_counter)) {
+	last_used_idx = READ_ONCE(vq->last_used_idx);
+	wrap_counter = packed_used_wrap_counter(last_used_idx);
+	used_idx = packed_last_used(last_used_idx);
+	if (is_used_desc_packed(vq, used_idx, wrap_counter)) {
 		END_USE(vq);
 		return false;
 	}
@@ -1689,7 +1709,7 @@ static struct virtqueue *vring_create_virtqueue_packed(
 	vq->notify = notify;
 	vq->weak_barriers = weak_barriers;
 	vq->broken = true;
-	vq->last_used_idx = 0;
+	vq->last_used_idx = 0 | (1 << VRING_PACKED_EVENT_F_WRAP_CTR);
 	vq->event_triggered = false;
 	vq->num_added = 0;
 	vq->packed_ring = true;
@@ -1720,7 +1740,6 @@ static struct virtqueue *vring_create_virtqueue_packed(
 
 	vq->packed.next_avail_idx = 0;
 	vq->packed.avail_wrap_counter = 1;
-	vq->packed.used_wrap_counter = 1;
 	vq->packed.event_flags_shadow = 0;
 	vq->packed.avail_used_flags = 1 << VRING_PACKED_DESC_F_AVAIL;
 
-- 
GitLab


From 03d9571706942fa653a4975709820596d13563c7 Mon Sep 17 00:00:00 2001
From: Bo Liu <liubo03@inspur.com>
Date: Fri, 17 Jun 2022 01:59:52 -0400
Subject: [PATCH 1111/1731] virtio: Remove unnecessary variable assignments

In function vp_modern_probe(), "pci_dev" is initialized with the
value of "mdev->pci_dev", so assigning "pci_dev" to "mdev->pci_dev"
is unnecessary since they store the same value.

Signed-off-by: Bo Liu <liubo03@inspur.com>
Message-Id: <20220617055952.5364-1-liubo03@inspur.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
---
 drivers/virtio/virtio_pci_modern_dev.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/virtio/virtio_pci_modern_dev.c b/drivers/virtio/virtio_pci_modern_dev.c
index b790f30b2b566..fa2a9445bb18c 100644
--- a/drivers/virtio/virtio_pci_modern_dev.c
+++ b/drivers/virtio/virtio_pci_modern_dev.c
@@ -220,8 +220,6 @@ int vp_modern_probe(struct virtio_pci_modern_device *mdev)
 
 	check_offsets();
 
-	mdev->pci_dev = pci_dev;
-
 	/* We only own devices >= 0x1000 and <= 0x107f: leave the rest. */
 	if (pci_dev->device < 0x1000 || pci_dev->device > 0x107f)
 		return -ENODEV;
-- 
GitLab


From c346dae4f3fbce51bbd4f2ec5e8c6f9b91e93163 Mon Sep 17 00:00:00 2001
From: Jason Wang <jasowang@redhat.com>
Date: Wed, 22 Jun 2022 09:29:40 +0800
Subject: [PATCH 1112/1731] virtio: disable notification hardening by default

We try to harden virtio device notifications in 8b4ec69d7e09 ("virtio:
harden vring IRQ"). It works with the assumption that the driver or
core can properly call virtio_device_ready() at the right
place. Unfortunately, this seems to be not true and uncover various
bugs of the existing drivers, mainly the issue of using
virtio_device_ready() incorrectly.

So let's add a Kconfig option and disable it by default. It gives
us time to fix the drivers and then we can consider re-enabling it.

Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20220622012940.21441-1-jasowang@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
---
 drivers/s390/virtio/virtio_ccw.c |  9 ++++++++-
 drivers/virtio/Kconfig           | 13 +++++++++++++
 drivers/virtio/virtio.c          |  2 ++
 drivers/virtio/virtio_ring.c     | 12 ++++++++++++
 include/linux/virtio_config.h    |  2 ++
 5 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/s390/virtio/virtio_ccw.c b/drivers/s390/virtio/virtio_ccw.c
index 97e51c34e6cfb..161d3b141f0d3 100644
--- a/drivers/s390/virtio/virtio_ccw.c
+++ b/drivers/s390/virtio/virtio_ccw.c
@@ -1136,8 +1136,13 @@ static void virtio_ccw_int_handler(struct ccw_device *cdev,
 			vcdev->err = -EIO;
 	}
 	virtio_ccw_check_activity(vcdev, activity);
-	/* Interrupts are disabled here */
+#ifdef CONFIG_VIRTIO_HARDEN_NOTIFICATION
+	/*
+	 * Paired with virtio_ccw_synchronize_cbs() and interrupts are
+	 * disabled here.
+	 */
 	read_lock(&vcdev->irq_lock);
+#endif
 	for_each_set_bit(i, indicators(vcdev),
 			 sizeof(*indicators(vcdev)) * BITS_PER_BYTE) {
 		/* The bit clear must happen before the vring kick. */
@@ -1146,7 +1151,9 @@ static void virtio_ccw_int_handler(struct ccw_device *cdev,
 		vq = virtio_ccw_vq_by_ind(vcdev, i);
 		vring_interrupt(0, vq);
 	}
+#ifdef CONFIG_VIRTIO_HARDEN_NOTIFICATION
 	read_unlock(&vcdev->irq_lock);
+#endif
 	if (test_bit(0, indicators2(vcdev))) {
 		virtio_config_changed(&vcdev->vdev);
 		clear_bit(0, indicators2(vcdev));
diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig
index a6dc8b5846fe7..e1556d2a355ae 100644
--- a/drivers/virtio/Kconfig
+++ b/drivers/virtio/Kconfig
@@ -29,6 +29,19 @@ menuconfig VIRTIO_MENU
 
 if VIRTIO_MENU
 
+config VIRTIO_HARDEN_NOTIFICATION
+        bool "Harden virtio notification"
+        help
+          Enable this to harden the device notifications and suppress
+          those that happen at a time where notifications are illegal.
+
+          Experimental: Note that several drivers still have bugs that
+          may cause crashes or hangs when correct handling of
+          notifications is enforced; depending on the subset of
+          drivers and devices you use, this may or may not work.
+
+          If unsure, say N.
+
 config VIRTIO_PCI
 	tristate "PCI driver for virtio devices"
 	depends on PCI
diff --git a/drivers/virtio/virtio.c b/drivers/virtio/virtio.c
index 6bace84ae37ec..7deeed30d1f3a 100644
--- a/drivers/virtio/virtio.c
+++ b/drivers/virtio/virtio.c
@@ -219,6 +219,7 @@ static int virtio_features_ok(struct virtio_device *dev)
  * */
 void virtio_reset_device(struct virtio_device *dev)
 {
+#ifdef CONFIG_VIRTIO_HARDEN_NOTIFICATION
 	/*
 	 * The below virtio_synchronize_cbs() guarantees that any
 	 * interrupt for this line arriving after
@@ -227,6 +228,7 @@ void virtio_reset_device(struct virtio_device *dev)
 	 */
 	virtio_break_device(dev);
 	virtio_synchronize_cbs(dev);
+#endif
 
 	dev->config->reset(dev);
 }
diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c
index ef30465dd39cb..96731cdef422a 100644
--- a/drivers/virtio/virtio_ring.c
+++ b/drivers/virtio/virtio_ring.c
@@ -1708,7 +1708,11 @@ static struct virtqueue *vring_create_virtqueue_packed(
 	vq->we_own_ring = true;
 	vq->notify = notify;
 	vq->weak_barriers = weak_barriers;
+#ifdef CONFIG_VIRTIO_HARDEN_NOTIFICATION
 	vq->broken = true;
+#else
+	vq->broken = false;
+#endif
 	vq->last_used_idx = 0 | (1 << VRING_PACKED_EVENT_F_WRAP_CTR);
 	vq->event_triggered = false;
 	vq->num_added = 0;
@@ -2154,9 +2158,13 @@ irqreturn_t vring_interrupt(int irq, void *_vq)
 	}
 
 	if (unlikely(vq->broken)) {
+#ifdef CONFIG_VIRTIO_HARDEN_NOTIFICATION
 		dev_warn_once(&vq->vq.vdev->dev,
 			      "virtio vring IRQ raised before DRIVER_OK");
 		return IRQ_NONE;
+#else
+		return IRQ_HANDLED;
+#endif
 	}
 
 	/* Just a hint for performance: so it's ok that this can be racy! */
@@ -2199,7 +2207,11 @@ struct virtqueue *__vring_new_virtqueue(unsigned int index,
 	vq->we_own_ring = false;
 	vq->notify = notify;
 	vq->weak_barriers = weak_barriers;
+#ifdef CONFIG_VIRTIO_HARDEN_NOTIFICATION
 	vq->broken = true;
+#else
+	vq->broken = false;
+#endif
 	vq->last_used_idx = 0;
 	vq->event_triggered = false;
 	vq->num_added = 0;
diff --git a/include/linux/virtio_config.h b/include/linux/virtio_config.h
index 49c7c32815f15..b47c2e7ed0ee8 100644
--- a/include/linux/virtio_config.h
+++ b/include/linux/virtio_config.h
@@ -257,6 +257,7 @@ void virtio_device_ready(struct virtio_device *dev)
 
 	WARN_ON(status & VIRTIO_CONFIG_S_DRIVER_OK);
 
+#ifdef CONFIG_VIRTIO_HARDEN_NOTIFICATION
 	/*
 	 * The virtio_synchronize_cbs() makes sure vring_interrupt()
 	 * will see the driver specific setup if it sees vq->broken
@@ -264,6 +265,7 @@ void virtio_device_ready(struct virtio_device *dev)
 	 */
 	virtio_synchronize_cbs(dev);
 	__virtio_unbreak_device(dev);
+#endif
 	/*
 	 * The transport should ensure the visibility of vq->broken
 	 * before setting DRIVER_OK. See the comments for the transport
-- 
GitLab


From ebdec859faa8cfbfef9f6c1f83d79dd6c8f4ab8c Mon Sep 17 00:00:00 2001
From: Mingwei Zhang <mizhang@google.com>
Date: Thu, 23 Jun 2022 17:18:58 +0000
Subject: [PATCH 1113/1731] KVM: x86/svm: add __GFP_ACCOUNT to
 __sev_dbg_{en,de}crypt_user()

Adding the accounting flag when allocating pages within the SEV function,
since these memory pages should belong to individual VM.

No functional change intended.

Signed-off-by: Mingwei Zhang <mizhang@google.com>
Message-Id: <20220623171858.2083637-1-mizhang@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/svm/sev.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c
index 51fd985cf21dd..e2c7fada0b3da 100644
--- a/arch/x86/kvm/svm/sev.c
+++ b/arch/x86/kvm/svm/sev.c
@@ -844,7 +844,7 @@ static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
 
 	/* If source buffer is not aligned then use an intermediate buffer */
 	if (!IS_ALIGNED((unsigned long)vaddr, 16)) {
-		src_tpage = alloc_page(GFP_KERNEL);
+		src_tpage = alloc_page(GFP_KERNEL_ACCOUNT);
 		if (!src_tpage)
 			return -ENOMEM;
 
@@ -865,7 +865,7 @@ static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
 	if (!IS_ALIGNED((unsigned long)dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
 		int dst_offset;
 
-		dst_tpage = alloc_page(GFP_KERNEL);
+		dst_tpage = alloc_page(GFP_KERNEL_ACCOUNT);
 		if (!dst_tpage) {
 			ret = -ENOMEM;
 			goto e_free;
-- 
GitLab


From 6defa24d3b12bbd418bc8526dea1cbc605265c06 Mon Sep 17 00:00:00 2001
From: Peter Gonda <pgonda@google.com>
Date: Thu, 23 Jun 2022 10:34:06 -0700
Subject: [PATCH 1114/1731] KVM: SEV: Init target VMCBs in sev_migrate_from

The target VMCBs during an intra-host migration need to correctly setup
for running SEV and SEV-ES guests. Add sev_init_vmcb() function and make
sev_es_init_vmcb() static. sev_init_vmcb() uses the now private function
to init SEV-ES guests VMCBs when needed.

Fixes: 0b020f5af092 ("KVM: SEV: Add support for SEV-ES intra host migration")
Fixes: b56639318bb2 ("KVM: SEV: Add support for SEV intra host migration")
Signed-off-by: Peter Gonda <pgonda@google.com>
Cc: Marc Orr <marcorr@google.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Sean Christopherson <seanjc@google.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: kvm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Message-Id: <20220623173406.744645-1-pgonda@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/svm/sev.c | 68 ++++++++++++++++++++++++++++--------------
 arch/x86/kvm/svm/svm.c | 11 ++-----
 arch/x86/kvm/svm/svm.h |  2 +-
 3 files changed, 48 insertions(+), 33 deletions(-)

diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c
index e2c7fada0b3da..0c240ed04f96c 100644
--- a/arch/x86/kvm/svm/sev.c
+++ b/arch/x86/kvm/svm/sev.c
@@ -1665,19 +1665,24 @@ static void sev_migrate_from(struct kvm *dst_kvm, struct kvm *src_kvm)
 {
 	struct kvm_sev_info *dst = &to_kvm_svm(dst_kvm)->sev_info;
 	struct kvm_sev_info *src = &to_kvm_svm(src_kvm)->sev_info;
+	struct kvm_vcpu *dst_vcpu, *src_vcpu;
+	struct vcpu_svm *dst_svm, *src_svm;
 	struct kvm_sev_info *mirror;
+	unsigned long i;
 
 	dst->active = true;
 	dst->asid = src->asid;
 	dst->handle = src->handle;
 	dst->pages_locked = src->pages_locked;
 	dst->enc_context_owner = src->enc_context_owner;
+	dst->es_active = src->es_active;
 
 	src->asid = 0;
 	src->active = false;
 	src->handle = 0;
 	src->pages_locked = 0;
 	src->enc_context_owner = NULL;
+	src->es_active = false;
 
 	list_cut_before(&dst->regions_list, &src->regions_list, &src->regions_list);
 
@@ -1704,26 +1709,21 @@ static void sev_migrate_from(struct kvm *dst_kvm, struct kvm *src_kvm)
 		list_del(&src->mirror_entry);
 		list_add_tail(&dst->mirror_entry, &owner_sev_info->mirror_vms);
 	}
-}
 
-static int sev_es_migrate_from(struct kvm *dst, struct kvm *src)
-{
-	unsigned long i;
-	struct kvm_vcpu *dst_vcpu, *src_vcpu;
-	struct vcpu_svm *dst_svm, *src_svm;
+	kvm_for_each_vcpu(i, dst_vcpu, dst_kvm) {
+		dst_svm = to_svm(dst_vcpu);
 
-	if (atomic_read(&src->online_vcpus) != atomic_read(&dst->online_vcpus))
-		return -EINVAL;
+		sev_init_vmcb(dst_svm);
 
-	kvm_for_each_vcpu(i, src_vcpu, src) {
-		if (!src_vcpu->arch.guest_state_protected)
-			return -EINVAL;
-	}
+		if (!dst->es_active)
+			continue;
 
-	kvm_for_each_vcpu(i, src_vcpu, src) {
+		/*
+		 * Note, the source is not required to have the same number of
+		 * vCPUs as the destination when migrating a vanilla SEV VM.
+		 */
+		src_vcpu = kvm_get_vcpu(dst_kvm, i);
 		src_svm = to_svm(src_vcpu);
-		dst_vcpu = kvm_get_vcpu(dst, i);
-		dst_svm = to_svm(dst_vcpu);
 
 		/*
 		 * Transfer VMSA and GHCB state to the destination.  Nullify and
@@ -1740,8 +1740,23 @@ static int sev_es_migrate_from(struct kvm *dst, struct kvm *src)
 		src_svm->vmcb->control.vmsa_pa = INVALID_PAGE;
 		src_vcpu->arch.guest_state_protected = false;
 	}
-	to_kvm_svm(src)->sev_info.es_active = false;
-	to_kvm_svm(dst)->sev_info.es_active = true;
+}
+
+static int sev_check_source_vcpus(struct kvm *dst, struct kvm *src)
+{
+	struct kvm_vcpu *src_vcpu;
+	unsigned long i;
+
+	if (!sev_es_guest(src))
+		return 0;
+
+	if (atomic_read(&src->online_vcpus) != atomic_read(&dst->online_vcpus))
+		return -EINVAL;
+
+	kvm_for_each_vcpu(i, src_vcpu, src) {
+		if (!src_vcpu->arch.guest_state_protected)
+			return -EINVAL;
+	}
 
 	return 0;
 }
@@ -1789,11 +1804,9 @@ int sev_vm_move_enc_context_from(struct kvm *kvm, unsigned int source_fd)
 	if (ret)
 		goto out_dst_vcpu;
 
-	if (sev_es_guest(source_kvm)) {
-		ret = sev_es_migrate_from(kvm, source_kvm);
-		if (ret)
-			goto out_source_vcpu;
-	}
+	ret = sev_check_source_vcpus(kvm, source_kvm);
+	if (ret)
+		goto out_source_vcpu;
 
 	sev_migrate_from(kvm, source_kvm);
 	kvm_vm_dead(source_kvm);
@@ -2914,7 +2927,7 @@ int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in)
 				    count, in);
 }
 
-void sev_es_init_vmcb(struct vcpu_svm *svm)
+static void sev_es_init_vmcb(struct vcpu_svm *svm)
 {
 	struct kvm_vcpu *vcpu = &svm->vcpu;
 
@@ -2967,6 +2980,15 @@ void sev_es_init_vmcb(struct vcpu_svm *svm)
 	}
 }
 
+void sev_init_vmcb(struct vcpu_svm *svm)
+{
+	svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
+	clr_exception_intercept(svm, UD_VECTOR);
+
+	if (sev_es_guest(svm->vcpu.kvm))
+		sev_es_init_vmcb(svm);
+}
+
 void sev_es_vcpu_reset(struct vcpu_svm *svm)
 {
 	/*
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 87da90360bc76..44bbf25dfeb95 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -1212,15 +1212,8 @@ static void init_vmcb(struct kvm_vcpu *vcpu)
 		svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
 	}
 
-	if (sev_guest(vcpu->kvm)) {
-		svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
-		clr_exception_intercept(svm, UD_VECTOR);
-
-		if (sev_es_guest(vcpu->kvm)) {
-			/* Perform SEV-ES specific VMCB updates */
-			sev_es_init_vmcb(svm);
-		}
-	}
+	if (sev_guest(vcpu->kvm))
+		sev_init_vmcb(svm);
 
 	svm_hv_init_vmcb(vmcb);
 	init_vmcb_after_set_cpuid(vcpu);
diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h
index 1bddd336a27e0..9223ac100ef57 100644
--- a/arch/x86/kvm/svm/svm.h
+++ b/arch/x86/kvm/svm/svm.h
@@ -649,10 +649,10 @@ void __init sev_set_cpu_caps(void);
 void __init sev_hardware_setup(void);
 void sev_hardware_unsetup(void);
 int sev_cpu_init(struct svm_cpu_data *sd);
+void sev_init_vmcb(struct vcpu_svm *svm);
 void sev_free_vcpu(struct kvm_vcpu *vcpu);
 int sev_handle_vmgexit(struct kvm_vcpu *vcpu);
 int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in);
-void sev_es_init_vmcb(struct vcpu_svm *svm);
 void sev_es_vcpu_reset(struct vcpu_svm *svm);
 void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector);
 void sev_es_prepare_switch_to_guest(struct sev_es_save_area *hostsa);
-- 
GitLab


From 87d044096ea62f1f230e8c4679ee8abf03266f64 Mon Sep 17 00:00:00 2001
From: Tom Lendacky <thomas.lendacky@amd.com>
Date: Mon, 13 Jun 2022 14:16:27 -0500
Subject: [PATCH 1115/1731] crypto: ccp - Fix device IRQ counting by using
 platform_irq_count()

The ccp driver loops through the platform device resources array to get
the IRQ count for the device. With commit a1a2b7125e10 ("of/platform: Drop
static setup of IRQ resource from DT core"), the IRQ resources are no
longer stored in the platform device resource array. As a result, the IRQ
count is now always zero. This causes the driver to issue a second call to
platform_get_irq(), which fails if the IRQ count is really 1, causing the
loading of the driver to fail.

Replace looping through the resources array to count the number of IRQs
with a call to platform_irq_count().

Fixes: a1a2b7125e10 ("of/platform: Drop static setup of IRQ resource from DT core")
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
---
 drivers/crypto/ccp/sp-platform.c | 12 ++----------
 1 file changed, 2 insertions(+), 10 deletions(-)

diff --git a/drivers/crypto/ccp/sp-platform.c b/drivers/crypto/ccp/sp-platform.c
index 9dba52fbee997..7d79a8744f9a6 100644
--- a/drivers/crypto/ccp/sp-platform.c
+++ b/drivers/crypto/ccp/sp-platform.c
@@ -85,17 +85,9 @@ static int sp_get_irqs(struct sp_device *sp)
 	struct sp_platform *sp_platform = sp->dev_specific;
 	struct device *dev = sp->dev;
 	struct platform_device *pdev = to_platform_device(dev);
-	unsigned int i, count;
 	int ret;
 
-	for (i = 0, count = 0; i < pdev->num_resources; i++) {
-		struct resource *res = &pdev->resource[i];
-
-		if (resource_type(res) == IORESOURCE_IRQ)
-			count++;
-	}
-
-	sp_platform->irq_count = count;
+	sp_platform->irq_count = platform_irq_count(pdev);
 
 	ret = platform_get_irq(pdev, 0);
 	if (ret < 0) {
@@ -104,7 +96,7 @@ static int sp_get_irqs(struct sp_device *sp)
 	}
 
 	sp->psp_irq = ret;
-	if (count == 1) {
+	if (sp_platform->irq_count == 1) {
 		sp->ccp_irq = ret;
 	} else {
 		ret = platform_get_irq(pdev, 1);
-- 
GitLab


From ae8b1631561a3634cc09d0c62bbdd938eade05ec Mon Sep 17 00:00:00 2001
From: Takashi Iwai <tiwai@suse.de>
Date: Fri, 24 Jun 2022 12:11:32 +0200
Subject: [PATCH 1116/1731] ALSA: usb-audio: Workarounds for Behringer UMC
 204/404 HD

Both Behringer UMC 202 HD and 404 HD need explicit quirks to enable
the implicit feedback mode and start the playback stream primarily.
The former seems fixing the stuttering and the latter is required for
a playback-only case.

Note that the "clock source 41 is not valid" error message still
appears even after this fix, but it should be only once at probe.
The reason of the error is still unknown, but this seems to be mostly
harmless as it's a one-off error and the driver retires the clock
setup and it succeeds afterwards.

BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=215934
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20220624101132.14528-1-tiwai@suse.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/usb/quirks.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c
index e8468f9b007d1..12ce69b04f634 100644
--- a/sound/usb/quirks.c
+++ b/sound/usb/quirks.c
@@ -1842,6 +1842,10 @@ static const struct usb_audio_quirk_flags_table quirk_flags_table[] = {
 		   QUIRK_FLAG_SHARE_MEDIA_DEVICE | QUIRK_FLAG_ALIGN_TRANSFER),
 	DEVICE_FLG(0x1395, 0x740a, /* Sennheiser DECT */
 		   QUIRK_FLAG_GET_SAMPLE_RATE),
+	DEVICE_FLG(0x1397, 0x0508, /* Behringer UMC204HD */
+		   QUIRK_FLAG_PLAYBACK_FIRST | QUIRK_FLAG_GENERIC_IMPLICIT_FB),
+	DEVICE_FLG(0x1397, 0x0509, /* Behringer UMC404HD */
+		   QUIRK_FLAG_PLAYBACK_FIRST | QUIRK_FLAG_GENERIC_IMPLICIT_FB),
 	DEVICE_FLG(0x13e5, 0x0001, /* Serato Phono */
 		   QUIRK_FLAG_IGNORE_CTL_ERROR),
 	DEVICE_FLG(0x154e, 0x1002, /* Denon DCD-1500RE */
-- 
GitLab


From 90bc2af24638659da56397ff835f3c95a948f991 Mon Sep 17 00:00:00 2001
From: Alan Stern <stern@rowland.harvard.edu>
Date: Wed, 22 Jun 2022 10:46:31 -0400
Subject: [PATCH 1117/1731] USB: gadget: Fix double-free bug in raw_gadget
 driver

Re-reading a recently merged fix to the raw_gadget driver showed that
it inadvertently introduced a double-free bug in a failure pathway.
If raw_ioctl_init() encounters an error after the driver ID number has
been allocated, it deallocates the ID number before returning.  But
when dev_free() runs later on, it will then try to deallocate the ID
number a second time.

Closely related to this issue is another error in the recent fix: The
ID number is stored in the raw_dev structure before the code checks to
see whether the structure has already been initialized, in which case
the new ID number would overwrite the earlier value.

The solution to both bugs is to keep the new ID number in a local
variable, and store it in the raw_dev structure only after the check
for prior initialization.  No errors can occur after that point, so
the double-free will never happen.

Fixes: f2d8c2606825 ("usb: gadget: Fix non-unique driver names in raw-gadget driver")
CC: Andrey Konovalov <andreyknvl@gmail.com>
CC: <stable@vger.kernel.org>
Signed-off-by: Alan Stern <stern@rowland.harvard.edu>
Link: https://lore.kernel.org/r/YrMrRw5AyIZghN0v@rowland.harvard.edu
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/gadget/legacy/raw_gadget.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/usb/gadget/legacy/raw_gadget.c b/drivers/usb/gadget/legacy/raw_gadget.c
index 5c8481cef35ff..2acece16b8900 100644
--- a/drivers/usb/gadget/legacy/raw_gadget.c
+++ b/drivers/usb/gadget/legacy/raw_gadget.c
@@ -430,6 +430,7 @@ out_put:
 static int raw_ioctl_init(struct raw_dev *dev, unsigned long value)
 {
 	int ret = 0;
+	int driver_id_number;
 	struct usb_raw_init arg;
 	char *udc_driver_name;
 	char *udc_device_name;
@@ -452,10 +453,9 @@ static int raw_ioctl_init(struct raw_dev *dev, unsigned long value)
 		return -EINVAL;
 	}
 
-	ret = ida_alloc(&driver_id_numbers, GFP_KERNEL);
-	if (ret < 0)
-		return ret;
-	dev->driver_id_number = ret;
+	driver_id_number = ida_alloc(&driver_id_numbers, GFP_KERNEL);
+	if (driver_id_number < 0)
+		return driver_id_number;
 
 	driver_driver_name = kmalloc(DRIVER_DRIVER_NAME_LENGTH_MAX, GFP_KERNEL);
 	if (!driver_driver_name) {
@@ -463,7 +463,7 @@ static int raw_ioctl_init(struct raw_dev *dev, unsigned long value)
 		goto out_free_driver_id_number;
 	}
 	snprintf(driver_driver_name, DRIVER_DRIVER_NAME_LENGTH_MAX,
-				DRIVER_NAME ".%d", dev->driver_id_number);
+				DRIVER_NAME ".%d", driver_id_number);
 
 	udc_driver_name = kmalloc(UDC_NAME_LENGTH_MAX, GFP_KERNEL);
 	if (!udc_driver_name) {
@@ -507,6 +507,7 @@ static int raw_ioctl_init(struct raw_dev *dev, unsigned long value)
 	dev->driver.driver.name = driver_driver_name;
 	dev->driver.udc_name = udc_device_name;
 	dev->driver.match_existing_only = 1;
+	dev->driver_id_number = driver_id_number;
 
 	dev->state = STATE_DEV_INITIALIZED;
 	spin_unlock_irqrestore(&dev->lock, flags);
@@ -521,7 +522,7 @@ out_free_udc_driver_name:
 out_free_driver_driver_name:
 	kfree(driver_driver_name);
 out_free_driver_id_number:
-	ida_free(&driver_id_numbers, dev->driver_id_number);
+	ida_free(&driver_id_numbers, driver_id_number);
 	return ret;
 }
 
-- 
GitLab


From b24346a240b36cfc4df194d145463874985aa29b Mon Sep 17 00:00:00 2001
From: Xu Yang <xu.yang_2@nxp.com>
Date: Thu, 23 Jun 2022 11:02:42 +0800
Subject: [PATCH 1118/1731] usb: chipidea: udc: check request status before
 setting device address

The complete() function may be called even though request is not
completed. In this case, it's necessary to check request status so
as not to set device address wrongly.

Fixes: 10775eb17bee ("usb: chipidea: udc: update gadget states according to ch9")
cc: <stable@vger.kernel.org>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Link: https://lore.kernel.org/r/20220623030242.41796-1-xu.yang_2@nxp.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/chipidea/udc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
index dc6c96e04bcfe..3b8bf6daf7d0f 100644
--- a/drivers/usb/chipidea/udc.c
+++ b/drivers/usb/chipidea/udc.c
@@ -1048,6 +1048,9 @@ isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
 	struct ci_hdrc *ci = req->context;
 	unsigned long flags;
 
+	if (req->status < 0)
+		return;
+
 	if (ci->setaddr) {
 		hw_usb_set_address(ci, ci->address);
 		ci->setaddr = false;
-- 
GitLab


From c242507c1b895646b4a25060df13b6214805759f Mon Sep 17 00:00:00 2001
From: Joerg Roedel <jroedel@suse.de>
Date: Fri, 24 Jun 2022 14:51:39 +0200
Subject: [PATCH 1119/1731] MAINTAINERS: Add new IOMMU development mailing list

The IOMMU mailing list will move from lists.linux-foundation.org to
lists.linux.dev. The hard switch of the archive will happen on July
5th, but add the new list now already so that people start using the
list when sending patches. After July 5th the old list will disappear.

Cc: stable@vger.kernel.org
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Link: https://lore.kernel.org/r/20220624125139.412-1-joro@8bytes.org
Signed-off-by: Joerg Roedel <jroedel@suse.de>
---
 MAINTAINERS | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 3cf9842d9233c..36d1bc9998158 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -427,6 +427,7 @@ ACPI VIOT DRIVER
 M:	Jean-Philippe Brucker <jean-philippe@linaro.org>
 L:	linux-acpi@vger.kernel.org
 L:	iommu@lists.linux-foundation.org
+L:	iommu@lists.linux.dev
 S:	Maintained
 F:	drivers/acpi/viot.c
 F:	include/linux/acpi_viot.h
@@ -960,6 +961,7 @@ AMD IOMMU (AMD-VI)
 M:	Joerg Roedel <joro@8bytes.org>
 R:	Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
 L:	iommu@lists.linux-foundation.org
+L:	iommu@lists.linux.dev
 S:	Maintained
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
 F:	drivers/iommu/amd/
@@ -5962,6 +5964,7 @@ M:	Christoph Hellwig <hch@lst.de>
 M:	Marek Szyprowski <m.szyprowski@samsung.com>
 R:	Robin Murphy <robin.murphy@arm.com>
 L:	iommu@lists.linux-foundation.org
+L:	iommu@lists.linux.dev
 S:	Supported
 W:	http://git.infradead.org/users/hch/dma-mapping.git
 T:	git git://git.infradead.org/users/hch/dma-mapping.git
@@ -5974,6 +5977,7 @@ F:	kernel/dma/
 DMA MAPPING BENCHMARK
 M:	Xiang Chen <chenxiang66@hisilicon.com>
 L:	iommu@lists.linux-foundation.org
+L:	iommu@lists.linux.dev
 F:	kernel/dma/map_benchmark.c
 F:	tools/testing/selftests/dma/
 
@@ -7558,6 +7562,7 @@ F:	drivers/gpu/drm/exynos/exynos_dp*
 EXYNOS SYSMMU (IOMMU) driver
 M:	Marek Szyprowski <m.szyprowski@samsung.com>
 L:	iommu@lists.linux-foundation.org
+L:	iommu@lists.linux.dev
 S:	Maintained
 F:	drivers/iommu/exynos-iommu.c
 
@@ -9977,6 +9982,7 @@ INTEL IOMMU (VT-d)
 M:	David Woodhouse <dwmw2@infradead.org>
 M:	Lu Baolu <baolu.lu@linux.intel.com>
 L:	iommu@lists.linux-foundation.org
+L:	iommu@lists.linux.dev
 S:	Supported
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
 F:	drivers/iommu/intel/
@@ -10356,6 +10362,7 @@ IOMMU DRIVERS
 M:	Joerg Roedel <joro@8bytes.org>
 M:	Will Deacon <will@kernel.org>
 L:	iommu@lists.linux-foundation.org
+L:	iommu@lists.linux.dev
 S:	Maintained
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
 F:	Documentation/devicetree/bindings/iommu/
@@ -12504,6 +12511,7 @@ F:	drivers/i2c/busses/i2c-mt65xx.c
 MEDIATEK IOMMU DRIVER
 M:	Yong Wu <yong.wu@mediatek.com>
 L:	iommu@lists.linux-foundation.org
+L:	iommu@lists.linux.dev
 L:	linux-mediatek@lists.infradead.org (moderated for non-subscribers)
 S:	Supported
 F:	Documentation/devicetree/bindings/iommu/mediatek*
@@ -16545,6 +16553,7 @@ F:	drivers/i2c/busses/i2c-qcom-cci.c
 QUALCOMM IOMMU
 M:	Rob Clark <robdclark@gmail.com>
 L:	iommu@lists.linux-foundation.org
+L:	iommu@lists.linux.dev
 L:	linux-arm-msm@vger.kernel.org
 S:	Maintained
 F:	drivers/iommu/arm/arm-smmu/qcom_iommu.c
@@ -19170,6 +19179,7 @@ F:	arch/x86/boot/video*
 SWIOTLB SUBSYSTEM
 M:	Christoph Hellwig <hch@infradead.org>
 L:	iommu@lists.linux-foundation.org
+L:	iommu@lists.linux.dev
 S:	Supported
 W:	http://git.infradead.org/users/hch/dma-mapping.git
 T:	git git://git.infradead.org/users/hch/dma-mapping.git
@@ -21844,6 +21854,7 @@ M:	Juergen Gross <jgross@suse.com>
 M:	Stefano Stabellini <sstabellini@kernel.org>
 L:	xen-devel@lists.xenproject.org (moderated for non-subscribers)
 L:	iommu@lists.linux-foundation.org
+L:	iommu@lists.linux.dev
 S:	Supported
 F:	arch/x86/xen/*swiotlb*
 F:	drivers/xen/*swiotlb*
-- 
GitLab


From 8da33fd11c05b7c64ef6456970f2fce61851806e Mon Sep 17 00:00:00 2001
From: Shyam Prasad N <sprasad@microsoft.com>
Date: Fri, 24 Jun 2022 09:43:59 +0000
Subject: [PATCH 1120/1731] cifs: avoid deadlocks while updating iface

We use cifs_tcp_ses_lock to protect a lot of things.
Not only does it protect the lists of connections, sessions,
tree connects, open file lists, etc., we also use it to
protect some fields in each of it's entries.

In this case, cifs_mark_ses_for_reconnect takes the
cifs_tcp_ses_lock to traverse the lists, and then calls
cifs_update_iface. However, that can end up calling
cifs_put_tcp_session, which picks up the same lock again.

Avoid this by taking a ref for the session, drop the lock,
and then call update iface.

Also, in cifs_update_iface, avoid nested locking of iface_lock
and chan_lock, as much as possible. When unavoidable, we need
to pick iface_lock first.

Signed-off-by: Shyam Prasad N <sprasad@microsoft.com>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/connect.c | 15 ++++++++++++---
 fs/cifs/sess.c    | 33 +++++++++++++++++++++------------
 2 files changed, 33 insertions(+), 15 deletions(-)

diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
index e666d2643edeb..8d56325915d0f 100644
--- a/fs/cifs/connect.c
+++ b/fs/cifs/connect.c
@@ -236,7 +236,7 @@ cifs_mark_tcp_ses_conns_for_reconnect(struct TCP_Server_Info *server,
 				      bool mark_smb_session)
 {
 	struct TCP_Server_Info *pserver;
-	struct cifs_ses *ses;
+	struct cifs_ses *ses, *nses;
 	struct cifs_tcon *tcon;
 
 	/*
@@ -250,10 +250,19 @@ cifs_mark_tcp_ses_conns_for_reconnect(struct TCP_Server_Info *server,
 
 
 	spin_lock(&cifs_tcp_ses_lock);
-	list_for_each_entry(ses, &pserver->smb_ses_list, smb_ses_list) {
+	list_for_each_entry_safe(ses, nses, &pserver->smb_ses_list, smb_ses_list) {
 		/* check if iface is still active */
-		if (!cifs_chan_is_iface_active(ses, server))
+		if (!cifs_chan_is_iface_active(ses, server)) {
+			/*
+			 * HACK: drop the lock before calling
+			 * cifs_chan_update_iface to avoid deadlock
+			 */
+			ses->ses_count++;
+			spin_unlock(&cifs_tcp_ses_lock);
 			cifs_chan_update_iface(ses, server);
+			spin_lock(&cifs_tcp_ses_lock);
+			ses->ses_count--;
+		}
 
 		spin_lock(&ses->chan_lock);
 		if (!mark_smb_session && cifs_chan_needs_reconnect(ses, server))
diff --git a/fs/cifs/sess.c b/fs/cifs/sess.c
index 7c26ee70c8b01..b85718f32b531 100644
--- a/fs/cifs/sess.c
+++ b/fs/cifs/sess.c
@@ -256,29 +256,34 @@ int cifs_try_adding_channels(struct cifs_sb_info *cifs_sb, struct cifs_ses *ses)
 
 /*
  * update the iface for the channel if necessary.
- * will return 0 when iface is updated. 1 otherwise
+ * will return 0 when iface is updated, 1 if removed, 2 otherwise
  * Must be called with chan_lock held.
  */
 int
 cifs_chan_update_iface(struct cifs_ses *ses, struct TCP_Server_Info *server)
 {
-	unsigned int chan_index = cifs_ses_get_chan_index(ses, server);
+	unsigned int chan_index;
 	struct cifs_server_iface *iface = NULL;
 	struct cifs_server_iface *old_iface = NULL;
 	int rc = 0;
 
-	/* primary channel. This can never go away */
-	if (!chan_index)
+	spin_lock(&ses->chan_lock);
+	chan_index = cifs_ses_get_chan_index(ses, server);
+	if (!chan_index) {
+		spin_unlock(&ses->chan_lock);
 		return 0;
+	}
 
 	if (ses->chans[chan_index].iface) {
 		old_iface = ses->chans[chan_index].iface;
-		if (old_iface->is_active)
+		if (old_iface->is_active) {
+			spin_unlock(&ses->chan_lock);
 			return 1;
+		}
 	}
+	spin_unlock(&ses->chan_lock);
 
 	spin_lock(&ses->iface_lock);
-
 	/* then look for a new one */
 	list_for_each_entry(iface, &ses->iface_list, iface_head) {
 		if (!iface->is_active ||
@@ -295,8 +300,6 @@ cifs_chan_update_iface(struct cifs_ses *ses, struct TCP_Server_Info *server)
 		cifs_dbg(FYI, "unable to find a suitable iface\n");
 	}
 
-	ses->chans[chan_index].iface = iface;
-
 	/* now drop the ref to the current iface */
 	if (old_iface && iface) {
 		kref_put(&old_iface->refcount, release_iface);
@@ -311,14 +314,20 @@ cifs_chan_update_iface(struct cifs_ses *ses, struct TCP_Server_Info *server)
 		WARN_ON(!iface);
 		cifs_dbg(FYI, "adding new iface: %pIS\n", &iface->sockaddr);
 	}
-
 	spin_unlock(&ses->iface_lock);
 
+	spin_lock(&ses->chan_lock);
+	chan_index = cifs_ses_get_chan_index(ses, server);
+	ses->chans[chan_index].iface = iface;
+
 	/* No iface is found. if secondary chan, drop connection */
-	if (!iface && CIFS_SERVER_IS_CHAN(server)) {
-		cifs_put_tcp_session(server, false);
+	if (!iface && CIFS_SERVER_IS_CHAN(server))
 		ses->chans[chan_index].server = NULL;
-	}
+
+	spin_unlock(&ses->chan_lock);
+
+	if (!iface && CIFS_SERVER_IS_CHAN(server))
+		cifs_put_tcp_session(server, false);
 
 	return rc;
 }
-- 
GitLab


From 17b1362d49191625440ca2c195959ce0b37ec296 Mon Sep 17 00:00:00 2001
From: Thara Gopinath <thara.gopinath@linaro.org>
Date: Fri, 7 Jan 2022 09:51:54 -0500
Subject: [PATCH 1121/1731] MAINTAINERS: Update email address

Update my email address in the MAINTAINERS file as  the current
one will stop functioning in a while.

Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 MAINTAINERS | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 192ba251e987c..ffa52d4bdfc50 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16489,7 +16489,7 @@ F:	Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
 F:	drivers/cpufreq/qcom-cpufreq-nvmem.c
 
 QUALCOMM CRYPTO DRIVERS
-M:	Thara Gopinath <thara.gopinath@linaro.org>
+M:	Thara Gopinath <thara.gopinath@gmail.com>
 L:	linux-crypto@vger.kernel.org
 L:	linux-arm-msm@vger.kernel.org
 S:	Maintained
@@ -16599,7 +16599,7 @@ F:	include/linux/if_rmnet.h
 
 QUALCOMM TSENS THERMAL DRIVER
 M:	Amit Kucheria <amitk@kernel.org>
-M:	Thara Gopinath <thara.gopinath@linaro.org>
+M:	Thara Gopinath <thara.gopinath@gmail.com>
 L:	linux-pm@vger.kernel.org
 L:	linux-arm-msm@vger.kernel.org
 S:	Maintained
-- 
GitLab


From 1ba904b6b16e08de5aed7c1349838d9cd0d178c5 Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Sun, 5 Jun 2022 11:58:41 +0400
Subject: [PATCH 1122/1731] ARM: cns3xxx: Fix refcount leak in cns3xxx_init

of_find_compatible_node() returns a node pointer with refcount
incremented, we should use of_node_put() on it when done.
Add missing of_node_put() to avoid refcount leak.

Fixes: 415f59142d9d ("ARM: cns3xxx: initial DT support")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Acked-by: Krzysztof Halasa <khalasa@piap.pl>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/mach-cns3xxx/core.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index e4f4b20b83a2d..3fc4ec830e3a3 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -372,6 +372,7 @@ static void __init cns3xxx_init(void)
 		/* De-Asscer SATA Reset */
 		cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
 	}
+	of_node_put(dn);
 
 	dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci");
 	if (of_device_is_available(dn)) {
@@ -385,6 +386,7 @@ static void __init cns3xxx_init(void)
 		cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
 		cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
 	}
+	of_node_put(dn);
 
 	pm_power_off = cns3xxx_power_off;
 
-- 
GitLab


From 2c629dd2d14fd7f64a553f809eda6d0b3a4f615a Mon Sep 17 00:00:00 2001
From: Liang He <windhl@126.com>
Date: Thu, 16 Jun 2022 17:30:27 +0800
Subject: [PATCH 1123/1731] arm: mach-spear: Add missing of_node_put() in
 time.c

In spear_setup_of_timer(), of_find_matching_node() will return a
node pointer with refcount incrementd. We should use of_node_put()
in each fail path or when it is not used anymore.

Signed-off-by: Liang He <windhl@126.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Link: https://lore.kernel.org/r/20220616093027.3984903-1-windhl@126.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/mach-spear/time.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-spear/time.c b/arch/arm/mach-spear/time.c
index d1fdb6066f7bb..c7c17c0f936cf 100644
--- a/arch/arm/mach-spear/time.c
+++ b/arch/arm/mach-spear/time.c
@@ -218,13 +218,13 @@ void __init spear_setup_of_timer(void)
 	irq = irq_of_parse_and_map(np, 0);
 	if (!irq) {
 		pr_err("%s: No irq passed for timer via DT\n", __func__);
-		return;
+		goto err_put_np;
 	}
 
 	gpt_base = of_iomap(np, 0);
 	if (!gpt_base) {
 		pr_err("%s: of iomap failed\n", __func__);
-		return;
+		goto err_put_np;
 	}
 
 	gpt_clk = clk_get_sys("gpt0", NULL);
@@ -239,6 +239,8 @@ void __init spear_setup_of_timer(void)
 		goto err_prepare_enable_clk;
 	}
 
+	of_node_put(np);
+
 	spear_clockevent_init(irq);
 	spear_clocksource_init();
 
@@ -248,4 +250,6 @@ err_prepare_enable_clk:
 	clk_put(gpt_clk);
 err_iomap:
 	iounmap(gpt_base);
+err_put_np:
+	of_node_put(np);
 }
-- 
GitLab


From ac63716da3070f8cb6baaba3a058a0c7f22aeb5b Mon Sep 17 00:00:00 2001
From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Date: Mon, 6 Jun 2022 15:37:46 -0500
Subject: [PATCH 1124/1731] ASoC: Realtek/Maxim SoundWire codecs: disable
 pm_runtime on remove

When binding/unbinding codec drivers, the following warnings are
thrown:

[ 107.266879] rt715-sdca sdw:3:025d:0714:01: Unbalanced pm_runtime_enable!
[  306.879700] rt711-sdca sdw:0:025d:0711:01: Unbalanced pm_runtime_enable!

Add a remove callback for all Realtek/Maxim SoundWire codecs and remove this
warning.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20220606203752.144159-2-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/max98373-sdw.c   | 12 +++++++++++-
 sound/soc/codecs/rt1308-sdw.c     | 11 +++++++++++
 sound/soc/codecs/rt1316-sdw.c     | 11 +++++++++++
 sound/soc/codecs/rt5682-sdw.c     |  5 ++++-
 sound/soc/codecs/rt700-sdw.c      |  6 +++++-
 sound/soc/codecs/rt711-sdca-sdw.c |  6 +++++-
 sound/soc/codecs/rt711-sdw.c      |  6 +++++-
 sound/soc/codecs/rt715-sdca-sdw.c | 12 ++++++++++++
 sound/soc/codecs/rt715-sdw.c      | 12 ++++++++++++
 9 files changed, 76 insertions(+), 5 deletions(-)

diff --git a/sound/soc/codecs/max98373-sdw.c b/sound/soc/codecs/max98373-sdw.c
index f47e956d4f55a..97b64477dde67 100644
--- a/sound/soc/codecs/max98373-sdw.c
+++ b/sound/soc/codecs/max98373-sdw.c
@@ -862,6 +862,16 @@ static int max98373_sdw_probe(struct sdw_slave *slave,
 	return max98373_init(slave, regmap);
 }
 
+static int max98373_sdw_remove(struct sdw_slave *slave)
+{
+	struct max98373_priv *max98373 = dev_get_drvdata(&slave->dev);
+
+	if (max98373->first_hw_init)
+		pm_runtime_disable(&slave->dev);
+
+	return 0;
+}
+
 #if defined(CONFIG_OF)
 static const struct of_device_id max98373_of_match[] = {
 	{ .compatible = "maxim,max98373", },
@@ -893,7 +903,7 @@ static struct sdw_driver max98373_sdw_driver = {
 		.pm = &max98373_pm,
 	},
 	.probe = max98373_sdw_probe,
-	.remove = NULL,
+	.remove = max98373_sdw_remove,
 	.ops = &max98373_slave_ops,
 	.id_table = max98373_id,
 };
diff --git a/sound/soc/codecs/rt1308-sdw.c b/sound/soc/codecs/rt1308-sdw.c
index 1c11b42dd76e0..72f673f278eec 100644
--- a/sound/soc/codecs/rt1308-sdw.c
+++ b/sound/soc/codecs/rt1308-sdw.c
@@ -691,6 +691,16 @@ static int rt1308_sdw_probe(struct sdw_slave *slave,
 	return 0;
 }
 
+static int rt1308_sdw_remove(struct sdw_slave *slave)
+{
+	struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev);
+
+	if (rt1308->first_hw_init)
+		pm_runtime_disable(&slave->dev);
+
+	return 0;
+}
+
 static const struct sdw_device_id rt1308_id[] = {
 	SDW_SLAVE_ENTRY_EXT(0x025d, 0x1308, 0x2, 0, 0),
 	{},
@@ -750,6 +760,7 @@ static struct sdw_driver rt1308_sdw_driver = {
 		.pm = &rt1308_pm,
 	},
 	.probe = rt1308_sdw_probe,
+	.remove = rt1308_sdw_remove,
 	.ops = &rt1308_slave_ops,
 	.id_table = rt1308_id,
 };
diff --git a/sound/soc/codecs/rt1316-sdw.c b/sound/soc/codecs/rt1316-sdw.c
index 60baa9ff19070..2d6b5f9d4d770 100644
--- a/sound/soc/codecs/rt1316-sdw.c
+++ b/sound/soc/codecs/rt1316-sdw.c
@@ -676,6 +676,16 @@ static int rt1316_sdw_probe(struct sdw_slave *slave,
 	return rt1316_sdw_init(&slave->dev, regmap, slave);
 }
 
+static int rt1316_sdw_remove(struct sdw_slave *slave)
+{
+	struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(&slave->dev);
+
+	if (rt1316->first_hw_init)
+		pm_runtime_disable(&slave->dev);
+
+	return 0;
+}
+
 static const struct sdw_device_id rt1316_id[] = {
 	SDW_SLAVE_ENTRY_EXT(0x025d, 0x1316, 0x3, 0x1, 0),
 	{},
@@ -735,6 +745,7 @@ static struct sdw_driver rt1316_sdw_driver = {
 		.pm = &rt1316_pm,
 	},
 	.probe = rt1316_sdw_probe,
+	.remove = rt1316_sdw_remove,
 	.ops = &rt1316_slave_ops,
 	.id_table = rt1316_id,
 };
diff --git a/sound/soc/codecs/rt5682-sdw.c b/sound/soc/codecs/rt5682-sdw.c
index 248257a2e4e0f..f04e18c32489d 100644
--- a/sound/soc/codecs/rt5682-sdw.c
+++ b/sound/soc/codecs/rt5682-sdw.c
@@ -719,9 +719,12 @@ static int rt5682_sdw_remove(struct sdw_slave *slave)
 {
 	struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
 
-	if (rt5682 && rt5682->hw_init)
+	if (rt5682->hw_init)
 		cancel_delayed_work_sync(&rt5682->jack_detect_work);
 
+	if (rt5682->first_hw_init)
+		pm_runtime_disable(&slave->dev);
+
 	return 0;
 }
 
diff --git a/sound/soc/codecs/rt700-sdw.c b/sound/soc/codecs/rt700-sdw.c
index bda5948996642..f7439e40ca8b5 100644
--- a/sound/soc/codecs/rt700-sdw.c
+++ b/sound/soc/codecs/rt700-sdw.c
@@ -13,6 +13,7 @@
 #include <linux/soundwire/sdw_type.h>
 #include <linux/soundwire/sdw_registers.h>
 #include <linux/module.h>
+#include <linux/pm_runtime.h>
 #include <linux/regmap.h>
 #include <sound/soc.h>
 #include "rt700.h"
@@ -463,11 +464,14 @@ static int rt700_sdw_remove(struct sdw_slave *slave)
 {
 	struct rt700_priv *rt700 = dev_get_drvdata(&slave->dev);
 
-	if (rt700 && rt700->hw_init) {
+	if (rt700->hw_init) {
 		cancel_delayed_work_sync(&rt700->jack_detect_work);
 		cancel_delayed_work_sync(&rt700->jack_btn_check_work);
 	}
 
+	if (rt700->first_hw_init)
+		pm_runtime_disable(&slave->dev);
+
 	return 0;
 }
 
diff --git a/sound/soc/codecs/rt711-sdca-sdw.c b/sound/soc/codecs/rt711-sdca-sdw.c
index aaf5af153d3fe..c722a2b0041f7 100644
--- a/sound/soc/codecs/rt711-sdca-sdw.c
+++ b/sound/soc/codecs/rt711-sdca-sdw.c
@@ -11,6 +11,7 @@
 #include <linux/mod_devicetable.h>
 #include <linux/soundwire/sdw_registers.h>
 #include <linux/module.h>
+#include <linux/pm_runtime.h>
 
 #include "rt711-sdca.h"
 #include "rt711-sdca-sdw.h"
@@ -364,11 +365,14 @@ static int rt711_sdca_sdw_remove(struct sdw_slave *slave)
 {
 	struct rt711_sdca_priv *rt711 = dev_get_drvdata(&slave->dev);
 
-	if (rt711 && rt711->hw_init) {
+	if (rt711->hw_init) {
 		cancel_delayed_work_sync(&rt711->jack_detect_work);
 		cancel_delayed_work_sync(&rt711->jack_btn_check_work);
 	}
 
+	if (rt711->first_hw_init)
+		pm_runtime_disable(&slave->dev);
+
 	return 0;
 }
 
diff --git a/sound/soc/codecs/rt711-sdw.c b/sound/soc/codecs/rt711-sdw.c
index bda2cc9439c98..f49c94baa37c6 100644
--- a/sound/soc/codecs/rt711-sdw.c
+++ b/sound/soc/codecs/rt711-sdw.c
@@ -13,6 +13,7 @@
 #include <linux/soundwire/sdw_type.h>
 #include <linux/soundwire/sdw_registers.h>
 #include <linux/module.h>
+#include <linux/pm_runtime.h>
 #include <linux/regmap.h>
 #include <sound/soc.h>
 #include "rt711.h"
@@ -464,12 +465,15 @@ static int rt711_sdw_remove(struct sdw_slave *slave)
 {
 	struct rt711_priv *rt711 = dev_get_drvdata(&slave->dev);
 
-	if (rt711 && rt711->hw_init) {
+	if (rt711->hw_init) {
 		cancel_delayed_work_sync(&rt711->jack_detect_work);
 		cancel_delayed_work_sync(&rt711->jack_btn_check_work);
 		cancel_work_sync(&rt711->calibration_work);
 	}
 
+	if (rt711->first_hw_init)
+		pm_runtime_disable(&slave->dev);
+
 	return 0;
 }
 
diff --git a/sound/soc/codecs/rt715-sdca-sdw.c b/sound/soc/codecs/rt715-sdca-sdw.c
index 0ecd2948f7aa7..13e731d166753 100644
--- a/sound/soc/codecs/rt715-sdca-sdw.c
+++ b/sound/soc/codecs/rt715-sdca-sdw.c
@@ -13,6 +13,7 @@
 #include <linux/soundwire/sdw_type.h>
 #include <linux/soundwire/sdw_registers.h>
 #include <linux/module.h>
+#include <linux/pm_runtime.h>
 #include <linux/regmap.h>
 #include <sound/soc.h>
 #include "rt715-sdca.h"
@@ -193,6 +194,16 @@ static int rt715_sdca_sdw_probe(struct sdw_slave *slave,
 	return rt715_sdca_init(&slave->dev, mbq_regmap, regmap, slave);
 }
 
+static int rt715_sdca_sdw_remove(struct sdw_slave *slave)
+{
+	struct rt715_sdca_priv *rt715 = dev_get_drvdata(&slave->dev);
+
+	if (rt715->first_hw_init)
+		pm_runtime_disable(&slave->dev);
+
+	return 0;
+}
+
 static const struct sdw_device_id rt715_sdca_id[] = {
 	SDW_SLAVE_ENTRY_EXT(0x025d, 0x715, 0x3, 0x1, 0),
 	SDW_SLAVE_ENTRY_EXT(0x025d, 0x714, 0x3, 0x1, 0),
@@ -267,6 +278,7 @@ static struct sdw_driver rt715_sdw_driver = {
 		.pm = &rt715_pm,
 	},
 	.probe = rt715_sdca_sdw_probe,
+	.remove = rt715_sdca_sdw_remove,
 	.ops = &rt715_sdca_slave_ops,
 	.id_table = rt715_sdca_id,
 };
diff --git a/sound/soc/codecs/rt715-sdw.c b/sound/soc/codecs/rt715-sdw.c
index a7b21b03c08bb..b047bf87a100c 100644
--- a/sound/soc/codecs/rt715-sdw.c
+++ b/sound/soc/codecs/rt715-sdw.c
@@ -14,6 +14,7 @@
 #include <linux/soundwire/sdw_type.h>
 #include <linux/soundwire/sdw_registers.h>
 #include <linux/module.h>
+#include <linux/pm_runtime.h>
 #include <linux/of.h>
 #include <linux/regmap.h>
 #include <sound/soc.h>
@@ -514,6 +515,16 @@ static int rt715_sdw_probe(struct sdw_slave *slave,
 	return 0;
 }
 
+static int rt715_sdw_remove(struct sdw_slave *slave)
+{
+	struct rt715_priv *rt715 = dev_get_drvdata(&slave->dev);
+
+	if (rt715->first_hw_init)
+		pm_runtime_disable(&slave->dev);
+
+	return 0;
+}
+
 static const struct sdw_device_id rt715_id[] = {
 	SDW_SLAVE_ENTRY_EXT(0x025d, 0x714, 0x2, 0, 0),
 	SDW_SLAVE_ENTRY_EXT(0x025d, 0x715, 0x2, 0, 0),
@@ -575,6 +586,7 @@ static struct sdw_driver rt715_sdw_driver = {
 		   .pm = &rt715_pm,
 		   },
 	.probe = rt715_sdw_probe,
+	.remove = rt715_sdw_remove,
 	.ops = &rt715_slave_ops,
 	.id_table = rt715_id,
 };
-- 
GitLab


From ed0a7fb29c9fd4f53eeb37d1fe2354df7a038047 Mon Sep 17 00:00:00 2001
From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Date: Mon, 6 Jun 2022 15:37:47 -0500
Subject: [PATCH 1125/1731] ASoC: rt711-sdca-sdw: fix calibrate mutex
 initialization

In codec driver bind/unbind test, the following warning is thrown:

DEBUG_LOCKS_WARN_ON(lock->magic != lock)
...
[  699.182495]  rt711_sdca_jack_init+0x1b/0x1d0 [snd_soc_rt711_sdca]
[  699.182498]  rt711_sdca_set_jack_detect+0x3b/0x90 [snd_soc_rt711_sdca]
[  699.182500]  snd_soc_component_set_jack+0x24/0x50 [snd_soc_core]

A quick check in the code shows that the 'calibrate_mutex' used by
this driver are not initialized at probe time. Moving the
initialization to the probe removes the issue.

BugLink: https://github.com/thesofproject/linux/issues/3644
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20220606203752.144159-3-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/rt711-sdca-sdw.c | 3 +++
 sound/soc/codecs/rt711-sdca.c     | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/sound/soc/codecs/rt711-sdca-sdw.c b/sound/soc/codecs/rt711-sdca-sdw.c
index c722a2b0041f7..a085b2f530aa1 100644
--- a/sound/soc/codecs/rt711-sdca-sdw.c
+++ b/sound/soc/codecs/rt711-sdca-sdw.c
@@ -373,6 +373,9 @@ static int rt711_sdca_sdw_remove(struct sdw_slave *slave)
 	if (rt711->first_hw_init)
 		pm_runtime_disable(&slave->dev);
 
+	mutex_destroy(&rt711->calibrate_mutex);
+	mutex_destroy(&rt711->disable_irq_lock);
+
 	return 0;
 }
 
diff --git a/sound/soc/codecs/rt711-sdca.c b/sound/soc/codecs/rt711-sdca.c
index 57629c18db384..af73bcb4560a3 100644
--- a/sound/soc/codecs/rt711-sdca.c
+++ b/sound/soc/codecs/rt711-sdca.c
@@ -1412,6 +1412,7 @@ int rt711_sdca_init(struct device *dev, struct regmap *regmap,
 	rt711->regmap = regmap;
 	rt711->mbq_regmap = mbq_regmap;
 
+	mutex_init(&rt711->calibrate_mutex);
 	mutex_init(&rt711->disable_irq_lock);
 
 	/*
@@ -1550,7 +1551,6 @@ int rt711_sdca_io_init(struct device *dev, struct sdw_slave *slave)
 			rt711_sdca_jack_detect_handler);
 		INIT_DELAYED_WORK(&rt711->jack_btn_check_work,
 			rt711_sdca_btn_check_handler);
-		mutex_init(&rt711->calibrate_mutex);
 	}
 
 	/* calibration */
-- 
GitLab


From fe154c4ff376bc31041c6441958a08243df09c99 Mon Sep 17 00:00:00 2001
From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Date: Mon, 6 Jun 2022 15:37:48 -0500
Subject: [PATCH 1126/1731] ASoC: Intel: sof_sdw: handle errors on card
 registration

If the card registration fails, typically because of deferred probes,
the device properties added for headset codecs are not removed, which
leads to kernel oopses in driver bind/unbind tests.

We already clean-up the device properties when the card is removed,
this code can be moved as a helper and called upon card registration
errors.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20220606203752.144159-4-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/boards/sof_sdw.c | 51 ++++++++++++++++++--------------
 1 file changed, 29 insertions(+), 22 deletions(-)

diff --git a/sound/soc/intel/boards/sof_sdw.c b/sound/soc/intel/boards/sof_sdw.c
index 1f00679b42409..ad826ad82d51a 100644
--- a/sound/soc/intel/boards/sof_sdw.c
+++ b/sound/soc/intel/boards/sof_sdw.c
@@ -1398,6 +1398,33 @@ static struct snd_soc_card card_sof_sdw = {
 	.late_probe = sof_sdw_card_late_probe,
 };
 
+static void mc_dailink_exit_loop(struct snd_soc_card *card)
+{
+	struct snd_soc_dai_link *link;
+	int ret;
+	int i, j;
+
+	for (i = 0; i < ARRAY_SIZE(codec_info_list); i++) {
+		if (!codec_info_list[i].exit)
+			continue;
+		/*
+		 * We don't need to call .exit function if there is no matched
+		 * dai link found.
+		 */
+		for_each_card_prelinks(card, j, link) {
+			if (!strcmp(link->codecs[0].dai_name,
+				    codec_info_list[i].dai_name)) {
+				ret = codec_info_list[i].exit(card, link);
+				if (ret)
+					dev_warn(card->dev,
+						 "codec exit failed %d\n",
+						 ret);
+				break;
+			}
+		}
+	}
+}
+
 static int mc_probe(struct platform_device *pdev)
 {
 	struct snd_soc_card *card = &card_sof_sdw;
@@ -1462,6 +1489,7 @@ static int mc_probe(struct platform_device *pdev)
 	ret = devm_snd_soc_register_card(&pdev->dev, card);
 	if (ret) {
 		dev_err(card->dev, "snd_soc_register_card failed %d\n", ret);
+		mc_dailink_exit_loop(card);
 		return ret;
 	}
 
@@ -1473,29 +1501,8 @@ static int mc_probe(struct platform_device *pdev)
 static int mc_remove(struct platform_device *pdev)
 {
 	struct snd_soc_card *card = platform_get_drvdata(pdev);
-	struct snd_soc_dai_link *link;
-	int ret;
-	int i, j;
 
-	for (i = 0; i < ARRAY_SIZE(codec_info_list); i++) {
-		if (!codec_info_list[i].exit)
-			continue;
-		/*
-		 * We don't need to call .exit function if there is no matched
-		 * dai link found.
-		 */
-		for_each_card_prelinks(card, j, link) {
-			if (!strcmp(link->codecs[0].dai_name,
-				    codec_info_list[i].dai_name)) {
-				ret = codec_info_list[i].exit(card, link);
-				if (ret)
-					dev_warn(&pdev->dev,
-						 "codec exit failed %d\n",
-						 ret);
-				break;
-			}
-		}
-	}
+	mc_dailink_exit_loop(card);
 
 	return 0;
 }
-- 
GitLab


From 08bb5dc6ce02374169213cea772b1c297eaf32d5 Mon Sep 17 00:00:00 2001
From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Date: Mon, 6 Jun 2022 15:37:49 -0500
Subject: [PATCH 1127/1731] ASoC: rt711: fix calibrate mutex initialization

Follow the same flow as rt711-sdca and initialize all mutexes at probe
time.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20220606203752.144159-5-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/rt711-sdw.c | 3 +++
 sound/soc/codecs/rt711.c     | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/sound/soc/codecs/rt711-sdw.c b/sound/soc/codecs/rt711-sdw.c
index f49c94baa37c6..4fe68bcf2a7c2 100644
--- a/sound/soc/codecs/rt711-sdw.c
+++ b/sound/soc/codecs/rt711-sdw.c
@@ -474,6 +474,9 @@ static int rt711_sdw_remove(struct sdw_slave *slave)
 	if (rt711->first_hw_init)
 		pm_runtime_disable(&slave->dev);
 
+	mutex_destroy(&rt711->calibrate_mutex);
+	mutex_destroy(&rt711->disable_irq_lock);
+
 	return 0;
 }
 
diff --git a/sound/soc/codecs/rt711.c b/sound/soc/codecs/rt711.c
index 9838fb4d5b9c0..1e35ba433a7e7 100644
--- a/sound/soc/codecs/rt711.c
+++ b/sound/soc/codecs/rt711.c
@@ -1204,6 +1204,7 @@ int rt711_init(struct device *dev, struct regmap *sdw_regmap,
 	rt711->sdw_regmap = sdw_regmap;
 	rt711->regmap = regmap;
 
+	mutex_init(&rt711->calibrate_mutex);
 	mutex_init(&rt711->disable_irq_lock);
 
 	/*
@@ -1318,7 +1319,6 @@ int rt711_io_init(struct device *dev, struct sdw_slave *slave)
 			rt711_jack_detect_handler);
 		INIT_DELAYED_WORK(&rt711->jack_btn_check_work,
 			rt711_btn_check_handler);
-		mutex_init(&rt711->calibrate_mutex);
 		INIT_WORK(&rt711->calibration_work, rt711_calibration_work);
 		schedule_work(&rt711->calibration_work);
 	}
-- 
GitLab


From 0484271ab0ce50649329fa9dc23c50853c5b26a4 Mon Sep 17 00:00:00 2001
From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Date: Mon, 6 Jun 2022 15:37:50 -0500
Subject: [PATCH 1128/1731] ASoC: rt7*-sdw: harden jack_detect_handler

Realtek headset codec drivers typically check if the card is
instantiated before proceeding with the jack detection.

The rt700, rt711 and rt711-sdca are however missing a check on the
card pointer, which can lead to NULL dereferences encountered in
driver bind/unbind tests.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20220606203752.144159-6-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/rt700.c      | 2 +-
 sound/soc/codecs/rt711-sdca.c | 2 +-
 sound/soc/codecs/rt711.c      | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/sound/soc/codecs/rt700.c b/sound/soc/codecs/rt700.c
index af32295fa9b93..4a99d5f4706fd 100644
--- a/sound/soc/codecs/rt700.c
+++ b/sound/soc/codecs/rt700.c
@@ -162,7 +162,7 @@ static void rt700_jack_detect_handler(struct work_struct *work)
 	if (!rt700->hs_jack)
 		return;
 
-	if (!rt700->component->card->instantiated)
+	if (!rt700->component->card || !rt700->component->card->instantiated)
 		return;
 
 	reg = RT700_VERB_GET_PIN_SENSE | RT700_HP_OUT;
diff --git a/sound/soc/codecs/rt711-sdca.c b/sound/soc/codecs/rt711-sdca.c
index af73bcb4560a3..93b36f05cb567 100644
--- a/sound/soc/codecs/rt711-sdca.c
+++ b/sound/soc/codecs/rt711-sdca.c
@@ -294,7 +294,7 @@ static void rt711_sdca_jack_detect_handler(struct work_struct *work)
 	if (!rt711->hs_jack)
 		return;
 
-	if (!rt711->component->card->instantiated)
+	if (!rt711->component->card || !rt711->component->card->instantiated)
 		return;
 
 	/* SDW_SCP_SDCA_INT_SDCA_0 is used for jack detection */
diff --git a/sound/soc/codecs/rt711.c b/sound/soc/codecs/rt711.c
index 1e35ba433a7e7..2f445b27305a4 100644
--- a/sound/soc/codecs/rt711.c
+++ b/sound/soc/codecs/rt711.c
@@ -242,7 +242,7 @@ static void rt711_jack_detect_handler(struct work_struct *work)
 	if (!rt711->hs_jack)
 		return;
 
-	if (!rt711->component->card->instantiated)
+	if (!rt711->component->card || !rt711->component->card->instantiated)
 		return;
 
 	if (pm_runtime_status_suspended(rt711->slave->dev.parent)) {
-- 
GitLab


From ba98d7d8b60ba410aa03834f6aa48fd3b2e68478 Mon Sep 17 00:00:00 2001
From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Date: Mon, 6 Jun 2022 15:37:51 -0500
Subject: [PATCH 1129/1731] ASoC: codecs: rt700/rt711/rt711-sdca: initialize
 workqueues in probe

The workqueues are initialized in the io_init functions, which isn't
quite right. In some tests, this leads to warnings throw from
__queue_delayed_work()

WARN_ON_FUNCTION_MISMATCH(timer->function, delayed_work_timer_fn);

Move all the initializations to the probe functions.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20220606203752.144159-7-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/rt700.c      | 12 +++++-------
 sound/soc/codecs/rt711-sdca.c | 10 +++-------
 sound/soc/codecs/rt711.c      | 12 +++++-------
 3 files changed, 13 insertions(+), 21 deletions(-)

diff --git a/sound/soc/codecs/rt700.c b/sound/soc/codecs/rt700.c
index 4a99d5f4706fd..7a6cf3434591a 100644
--- a/sound/soc/codecs/rt700.c
+++ b/sound/soc/codecs/rt700.c
@@ -1115,6 +1115,11 @@ int rt700_init(struct device *dev, struct regmap *sdw_regmap,
 
 	mutex_init(&rt700->disable_irq_lock);
 
+	INIT_DELAYED_WORK(&rt700->jack_detect_work,
+			  rt700_jack_detect_handler);
+	INIT_DELAYED_WORK(&rt700->jack_btn_check_work,
+			  rt700_btn_check_handler);
+
 	/*
 	 * Mark hw_init to false
 	 * HW init will be performed when device reports present
@@ -1209,13 +1214,6 @@ int rt700_io_init(struct device *dev, struct sdw_slave *slave)
 	/* Finish Initial Settings, set power to D3 */
 	regmap_write(rt700->regmap, RT700_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
 
-	if (!rt700->first_hw_init) {
-		INIT_DELAYED_WORK(&rt700->jack_detect_work,
-			rt700_jack_detect_handler);
-		INIT_DELAYED_WORK(&rt700->jack_btn_check_work,
-			rt700_btn_check_handler);
-	}
-
 	/*
 	 * if set_jack callback occurred early than io_init,
 	 * we set up the jack detection function now
diff --git a/sound/soc/codecs/rt711-sdca.c b/sound/soc/codecs/rt711-sdca.c
index 93b36f05cb567..2b3b77577d1fd 100644
--- a/sound/soc/codecs/rt711-sdca.c
+++ b/sound/soc/codecs/rt711-sdca.c
@@ -1415,6 +1415,9 @@ int rt711_sdca_init(struct device *dev, struct regmap *regmap,
 	mutex_init(&rt711->calibrate_mutex);
 	mutex_init(&rt711->disable_irq_lock);
 
+	INIT_DELAYED_WORK(&rt711->jack_detect_work, rt711_sdca_jack_detect_handler);
+	INIT_DELAYED_WORK(&rt711->jack_btn_check_work, rt711_sdca_btn_check_handler);
+
 	/*
 	 * Mark hw_init to false
 	 * HW init will be performed when device reports present
@@ -1546,13 +1549,6 @@ int rt711_sdca_io_init(struct device *dev, struct sdw_slave *slave)
 	rt711_sdca_index_update_bits(rt711, RT711_VENDOR_HDA_CTL,
 		RT711_PUSH_BTN_INT_CTL0, 0x20, 0x00);
 
-	if (!rt711->first_hw_init) {
-		INIT_DELAYED_WORK(&rt711->jack_detect_work,
-			rt711_sdca_jack_detect_handler);
-		INIT_DELAYED_WORK(&rt711->jack_btn_check_work,
-			rt711_sdca_btn_check_handler);
-	}
-
 	/* calibration */
 	ret = rt711_sdca_calibration(rt711);
 	if (ret < 0)
diff --git a/sound/soc/codecs/rt711.c b/sound/soc/codecs/rt711.c
index 2f445b27305a4..5709a6bbe8fc5 100644
--- a/sound/soc/codecs/rt711.c
+++ b/sound/soc/codecs/rt711.c
@@ -1207,6 +1207,10 @@ int rt711_init(struct device *dev, struct regmap *sdw_regmap,
 	mutex_init(&rt711->calibrate_mutex);
 	mutex_init(&rt711->disable_irq_lock);
 
+	INIT_DELAYED_WORK(&rt711->jack_detect_work, rt711_jack_detect_handler);
+	INIT_DELAYED_WORK(&rt711->jack_btn_check_work, rt711_btn_check_handler);
+	INIT_WORK(&rt711->calibration_work, rt711_calibration_work);
+
 	/*
 	 * Mark hw_init to false
 	 * HW init will be performed when device reports present
@@ -1314,14 +1318,8 @@ int rt711_io_init(struct device *dev, struct sdw_slave *slave)
 
 	if (rt711->first_hw_init)
 		rt711_calibration(rt711);
-	else {
-		INIT_DELAYED_WORK(&rt711->jack_detect_work,
-			rt711_jack_detect_handler);
-		INIT_DELAYED_WORK(&rt711->jack_btn_check_work,
-			rt711_btn_check_handler);
-		INIT_WORK(&rt711->calibration_work, rt711_calibration_work);
+	else
 		schedule_work(&rt711->calibration_work);
-	}
 
 	/*
 	 * if set_jack callback occurred early than io_init,
-- 
GitLab


From 40737057b48f1b4db67b0d766b95c87ba8fc5e03 Mon Sep 17 00:00:00 2001
From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Date: Mon, 6 Jun 2022 15:37:52 -0500
Subject: [PATCH 1130/1731] ASoC: codecs: rt700/rt711/rt711-sdca: resume
 bus/codec in .set_jack_detect

The .set_jack_detect() codec component callback is invoked during card
registration, which happens when the machine driver is probed.

The issue is that this callback can race with the bus suspend/resume,
and IO timeouts can happen. This can be reproduced very easily if the
machine driver is 'blacklisted' and manually probed after the bus
suspends. The bus and codec need to be re-initialized using pm_runtime
helpers.

Previous contributions tried to make sure accesses to the bus during
the .set_jack_detect() component callback only happen when the bus is
active. This was done by changing the regcache status on a component
remove. This is however a layering violation, the regcache status
should only be modified on device probe, suspend and resume. The
component probe/remove should not modify how the device regcache is
handled. This solution also didn't handle all the possible race
conditions, and the RT700 headset codec was not handled.

This patch tries to resume the codec device before handling the jack
initializations. In case the codec has not yet been initialized,
pm_runtime may not be enabled yet, so we don't squelch the -EACCES
error code and only stop the jack information. When the codec reports
as attached, the jack initialization will proceed as usual.

BugLink: https://github.com/thesofproject/linux/issues/3643
Fixes: 7ad4d237e7c4a ('ASoC: rt711-sdca: Add RT711 SDCA vendor-specific driver')
Fixes: 899b12542b089 ('ASoC: rt711: add snd_soc_component remove callback')
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20220606203752.144159-8-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/rt700.c      | 16 +++++++++++++---
 sound/soc/codecs/rt711-sdca.c | 26 ++++++++++++++------------
 sound/soc/codecs/rt711.c      | 24 +++++++++++++-----------
 3 files changed, 40 insertions(+), 26 deletions(-)

diff --git a/sound/soc/codecs/rt700.c b/sound/soc/codecs/rt700.c
index 7a6cf3434591a..9bceeeb830b15 100644
--- a/sound/soc/codecs/rt700.c
+++ b/sound/soc/codecs/rt700.c
@@ -315,17 +315,27 @@ static int rt700_set_jack_detect(struct snd_soc_component *component,
 	struct snd_soc_jack *hs_jack, void *data)
 {
 	struct rt700_priv *rt700 = snd_soc_component_get_drvdata(component);
+	int ret;
 
 	rt700->hs_jack = hs_jack;
 
-	if (!rt700->hw_init) {
-		dev_dbg(&rt700->slave->dev,
-			"%s hw_init not ready yet\n", __func__);
+	ret = pm_runtime_resume_and_get(component->dev);
+	if (ret < 0) {
+		if (ret != -EACCES) {
+			dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret);
+			return ret;
+		}
+
+		/* pm_runtime not enabled yet */
+		dev_dbg(component->dev,	"%s: skipping jack init for now\n", __func__);
 		return 0;
 	}
 
 	rt700_jack_init(rt700);
 
+	pm_runtime_mark_last_busy(component->dev);
+	pm_runtime_put_autosuspend(component->dev);
+
 	return 0;
 }
 
diff --git a/sound/soc/codecs/rt711-sdca.c b/sound/soc/codecs/rt711-sdca.c
index 2b3b77577d1fd..dfe3c9299ebde 100644
--- a/sound/soc/codecs/rt711-sdca.c
+++ b/sound/soc/codecs/rt711-sdca.c
@@ -487,16 +487,27 @@ static int rt711_sdca_set_jack_detect(struct snd_soc_component *component,
 	struct snd_soc_jack *hs_jack, void *data)
 {
 	struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
+	int ret;
 
 	rt711->hs_jack = hs_jack;
 
-	if (!rt711->hw_init) {
-		dev_dbg(&rt711->slave->dev,
-			"%s hw_init not ready yet\n", __func__);
+	ret = pm_runtime_resume_and_get(component->dev);
+	if (ret < 0) {
+		if (ret != -EACCES) {
+			dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret);
+			return ret;
+		}
+
+		/* pm_runtime not enabled yet */
+		dev_dbg(component->dev,	"%s: skipping jack init for now\n", __func__);
 		return 0;
 	}
 
 	rt711_sdca_jack_init(rt711);
+
+	pm_runtime_mark_last_busy(component->dev);
+	pm_runtime_put_autosuspend(component->dev);
+
 	return 0;
 }
 
@@ -1190,14 +1201,6 @@ static int rt711_sdca_probe(struct snd_soc_component *component)
 	return 0;
 }
 
-static void rt711_sdca_remove(struct snd_soc_component *component)
-{
-	struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
-
-	regcache_cache_only(rt711->regmap, true);
-	regcache_cache_only(rt711->mbq_regmap, true);
-}
-
 static const struct snd_soc_component_driver soc_sdca_dev_rt711 = {
 	.probe = rt711_sdca_probe,
 	.controls = rt711_sdca_snd_controls,
@@ -1207,7 +1210,6 @@ static const struct snd_soc_component_driver soc_sdca_dev_rt711 = {
 	.dapm_routes = rt711_sdca_audio_map,
 	.num_dapm_routes = ARRAY_SIZE(rt711_sdca_audio_map),
 	.set_jack = rt711_sdca_set_jack_detect,
-	.remove = rt711_sdca_remove,
 	.endianness = 1,
 };
 
diff --git a/sound/soc/codecs/rt711.c b/sound/soc/codecs/rt711.c
index 5709a6bbe8fc5..9df800abfc2d8 100644
--- a/sound/soc/codecs/rt711.c
+++ b/sound/soc/codecs/rt711.c
@@ -457,17 +457,27 @@ static int rt711_set_jack_detect(struct snd_soc_component *component,
 	struct snd_soc_jack *hs_jack, void *data)
 {
 	struct rt711_priv *rt711 = snd_soc_component_get_drvdata(component);
+	int ret;
 
 	rt711->hs_jack = hs_jack;
 
-	if (!rt711->hw_init) {
-		dev_dbg(&rt711->slave->dev,
-			"%s hw_init not ready yet\n", __func__);
+	ret = pm_runtime_resume_and_get(component->dev);
+	if (ret < 0) {
+		if (ret != -EACCES) {
+			dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret);
+			return ret;
+		}
+
+		/* pm_runtime not enabled yet */
+		dev_dbg(component->dev,	"%s: skipping jack init for now\n", __func__);
 		return 0;
 	}
 
 	rt711_jack_init(rt711);
 
+	pm_runtime_mark_last_busy(component->dev);
+	pm_runtime_put_autosuspend(component->dev);
+
 	return 0;
 }
 
@@ -932,13 +942,6 @@ static int rt711_probe(struct snd_soc_component *component)
 	return 0;
 }
 
-static void rt711_remove(struct snd_soc_component *component)
-{
-	struct rt711_priv *rt711 = snd_soc_component_get_drvdata(component);
-
-	regcache_cache_only(rt711->regmap, true);
-}
-
 static const struct snd_soc_component_driver soc_codec_dev_rt711 = {
 	.probe = rt711_probe,
 	.set_bias_level = rt711_set_bias_level,
@@ -949,7 +952,6 @@ static const struct snd_soc_component_driver soc_codec_dev_rt711 = {
 	.dapm_routes = rt711_audio_map,
 	.num_dapm_routes = ARRAY_SIZE(rt711_audio_map),
 	.set_jack = rt711_set_jack_detect,
-	.remove = rt711_remove,
 	.endianness = 1,
 };
 
-- 
GitLab


From ed0073bd0fccec459b526918be70bf9dc551581a Mon Sep 17 00:00:00 2001
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Date: Wed, 8 Jun 2022 02:09:16 +0000
Subject: [PATCH 1131/1731] ASoC: ak4613: cares Simple-Audio-Card case for TDM

Renesas is the only user of ak4613 on upstream for now, and
commit f28dbaa958fbd8 ("ASoC: ak4613: add TDM256 support")
added TDM256 support. Renesas tested part of it, because of
board connection.

It was assuming ak4613 is probed via Audio-Graph-Card, but it
might be probed via Simple-Audio-Card either.
It will indicates WARNING in such case. This patch fixup it.

Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/87h74v29f7.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/ak4613.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/sound/soc/codecs/ak4613.c b/sound/soc/codecs/ak4613.c
index 55e773f921228..93606e5afd8f1 100644
--- a/sound/soc/codecs/ak4613.c
+++ b/sound/soc/codecs/ak4613.c
@@ -868,10 +868,12 @@ static void ak4613_parse_of(struct ak4613_priv *priv,
 
 	/*
 	 * connected STDI
+	 * TDM support is assuming it is probed via Audio-Graph-Card style here.
+	 * Default is SDTIx1 if it was probed via Simple-Audio-Card for now.
 	 */
 	sdti_num = of_graph_get_endpoint_count(np);
-	if (WARN_ON((sdti_num > 3) || (sdti_num < 1)))
-		return;
+	if ((sdti_num >= SDTx_MAX) || (sdti_num < 1))
+		sdti_num = 1;
 
 	AK4613_CONFIG_SDTI_set(priv, sdti_num);
 }
-- 
GitLab


From 08f8a93198e300dff9649bbae424cd805d313326 Mon Sep 17 00:00:00 2001
From: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Date: Thu, 9 Jun 2022 11:59:47 +0300
Subject: [PATCH 1132/1731] ASoC: SOF: Intel: hda-dsp: Expose
 hda_dsp_core_power_up()

The hda_dsp_core_power_up() needs to be exposed so that it can be used in
hda-loader.c to correct the boot flow.
The first step must not unstall the core, it should only power up the
core(s).

Add sanity check for the core_mask while exposing it to be safe.

Complements: 2a68ff846164 ("ASoC: SOF: Intel: hda: Revisit IMR boot sequence")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20220609085949.29062-2-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/sof/intel/hda-dsp.c | 10 +++++++++-
 sound/soc/sof/intel/hda.h     |  1 +
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/sound/soc/sof/intel/hda-dsp.c b/sound/soc/sof/intel/hda-dsp.c
index 000ea906670cb..e24eea725acb4 100644
--- a/sound/soc/sof/intel/hda-dsp.c
+++ b/sound/soc/sof/intel/hda-dsp.c
@@ -181,12 +181,20 @@ int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask)
  * Power Management.
  */
 
-static int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask)
+int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask)
 {
+	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
+	const struct sof_intel_dsp_desc *chip = hda->desc;
 	unsigned int cpa;
 	u32 adspcs;
 	int ret;
 
+	/* restrict core_mask to host managed cores mask */
+	core_mask &= chip->host_managed_cores_mask;
+	/* return if core_mask is not valid */
+	if (!core_mask)
+		return 0;
+
 	/* update bits */
 	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
 				HDA_DSP_ADSPCS_SPA_MASK(core_mask),
diff --git a/sound/soc/sof/intel/hda.h b/sound/soc/sof/intel/hda.h
index 3e0f7b0c586a2..0f57ef5d9b8e9 100644
--- a/sound/soc/sof/intel/hda.h
+++ b/sound/soc/sof/intel/hda.h
@@ -497,6 +497,7 @@ struct sof_intel_hda_stream {
  */
 int hda_dsp_probe(struct snd_sof_dev *sdev);
 int hda_dsp_remove(struct snd_sof_dev *sdev);
+int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
-- 
GitLab


From c31691e0d126ec5d60d2b6b03f699c11b613b219 Mon Sep 17 00:00:00 2001
From: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Date: Thu, 9 Jun 2022 11:59:48 +0300
Subject: [PATCH 1133/1731] ASoC: SOF: Intel: hda-loader: Make sure that the fw
 load sequence is followed

The hda_dsp_enable_core() is powering up _and_ unstall the core in one
call while the first step of the firmware loading  must not unstall the
core.
The core can be unstalled only after the set cpb_cfp and the configuration
of the IPC register for the ROM_CONTROL message.

Complements: 2a68ff846164 ("ASoC: SOF: Intel: hda: Revisit IMR boot sequence")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20220609085949.29062-3-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/sof/intel/hda-loader.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/sof/intel/hda-loader.c b/sound/soc/sof/intel/hda-loader.c
index 64290125d7cd8..103e62bcfa82d 100644
--- a/sound/soc/sof/intel/hda-loader.c
+++ b/sound/soc/sof/intel/hda-loader.c
@@ -110,7 +110,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
 	int ret;
 
 	/* step 1: power up corex */
-	ret = hda_dsp_enable_core(sdev, chip->host_managed_cores_mask);
+	ret = hda_dsp_core_power_up(sdev, chip->host_managed_cores_mask);
 	if (ret < 0) {
 		if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
 			dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n");
-- 
GitLab


From bbfef046c6613404c01aeb9e9928bebb78dd327a Mon Sep 17 00:00:00 2001
From: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Date: Thu, 9 Jun 2022 11:59:49 +0300
Subject: [PATCH 1134/1731] ASoC: SOF: Intel: hda-loader: Clarify the
 cl_dsp_init() flow

Update the comment for the cl_dsp_init() to clarify what is done by the
function and use the chip->init_core_mask instead of BIT(0) when
unstalling/running the init core.

Complements: 2a68ff846164 ("ASoC: SOF: Intel: hda: Revisit IMR boot sequence")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20220609085949.29062-4-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/sof/intel/hda-loader.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/sound/soc/sof/intel/hda-loader.c b/sound/soc/sof/intel/hda-loader.c
index 103e62bcfa82d..d3ec5996a9a3d 100644
--- a/sound/soc/sof/intel/hda-loader.c
+++ b/sound/soc/sof/intel/hda-loader.c
@@ -95,9 +95,9 @@ out_put:
 }
 
 /*
- * first boot sequence has some extra steps. core 0 waits for power
- * status on core 1, so power up core 1 also momentarily, keep it in
- * reset/stall and then turn it off
+ * first boot sequence has some extra steps.
+ * power on all host managed cores and only unstall/run the boot core to boot the
+ * DSP then turn off all non boot cores (if any) is powered on.
  */
 static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
 {
@@ -127,7 +127,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
 	snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr);
 
 	/* step 3: unset core 0 reset state & unstall/run core 0 */
-	ret = hda_dsp_core_run(sdev, BIT(0));
+	ret = hda_dsp_core_run(sdev, chip->init_core_mask);
 	if (ret < 0) {
 		if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
 			dev_err(sdev->dev,
-- 
GitLab


From c2d1aec3f5da2475aa13a487d329823b7d27d499 Mon Sep 17 00:00:00 2001
From: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Date: Fri, 10 Jun 2022 11:47:35 +0300
Subject: [PATCH 1135/1731] ASoC: SOF: ipc3-topology: Move and correct size
 checks in sof_ipc3_control_load_bytes()

Move the size checks prior to allocating memory as these checks do not need
the data to be allocated and in case of an error we would not need to free
the allocation.

The max size must not be less than the size of
struct sof_ipc_ctrl_data + struct sof_abi_hdr as the ABI header needs to
be present under all circumstances.
The check was incorrectly used or between the two size checks.

Fixes: b5cee8feb1d4 ("ASoC: SOF: topology: Make control parsing IPC agnostic")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20220610084735.19397-1-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/sof/ipc3-topology.c | 23 +++++++++++------------
 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/sound/soc/sof/ipc3-topology.c b/sound/soc/sof/ipc3-topology.c
index 043554d7cb4a6..10740c55294dc 100644
--- a/sound/soc/sof/ipc3-topology.c
+++ b/sound/soc/sof/ipc3-topology.c
@@ -1577,24 +1577,23 @@ static int sof_ipc3_control_load_bytes(struct snd_sof_dev *sdev, struct snd_sof_
 	struct sof_ipc_ctrl_data *cdata;
 	int ret;
 
-	scontrol->ipc_control_data = kzalloc(scontrol->max_size, GFP_KERNEL);
-	if (!scontrol->ipc_control_data)
-		return -ENOMEM;
-
-	if (scontrol->max_size < sizeof(*cdata) ||
-	    scontrol->max_size < sizeof(struct sof_abi_hdr)) {
-		ret = -EINVAL;
-		goto err;
+	if (scontrol->max_size < (sizeof(*cdata) + sizeof(struct sof_abi_hdr))) {
+		dev_err(sdev->dev, "%s: insufficient size for a bytes control: %zu.\n",
+			__func__, scontrol->max_size);
+		return -EINVAL;
 	}
 
-	/* init the get/put bytes data */
 	if (scontrol->priv_size > scontrol->max_size - sizeof(*cdata)) {
-		dev_err(sdev->dev, "err: bytes data size %zu exceeds max %zu.\n",
+		dev_err(sdev->dev,
+			"%s: bytes data size %zu exceeds max %zu.\n", __func__,
 			scontrol->priv_size, scontrol->max_size - sizeof(*cdata));
-		ret = -EINVAL;
-		goto err;
+		return -EINVAL;
 	}
 
+	scontrol->ipc_control_data = kzalloc(scontrol->max_size, GFP_KERNEL);
+	if (!scontrol->ipc_control_data)
+		return -ENOMEM;
+
 	scontrol->size = sizeof(struct sof_ipc_ctrl_data) + scontrol->priv_size;
 
 	cdata = scontrol->ipc_control_data;
-- 
GitLab


From af2d146a8041c67efdd620c9463973ce0650b7b7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Amadeusz=20S=C5=82awi=C5=84ski?=
 <amadeuszx.slawinski@linux.intel.com>
Date: Fri, 10 Jun 2022 14:42:57 +0200
Subject: [PATCH 1136/1731] ASoC: Intel: avs: Fix parsing UUIDs in topology
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Use correct type for parsing UUIDs, this eliminates warning present,
when compiling with W=1.

Fixes: 34ae2cd53673 ("ASoC: Intel: avs: Add topology parsing infrastructure")
Reported-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Amadeusz Sławiński <amadeuszx.slawinski@linux.intel.com>
Reviewed-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20220610124257.4160658-1-amadeuszx.slawinski@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/avs/topology.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/soc/intel/avs/topology.c b/sound/soc/intel/avs/topology.c
index 0d11cc8aab0bd..6a06fe387d13b 100644
--- a/sound/soc/intel/avs/topology.c
+++ b/sound/soc/intel/avs/topology.c
@@ -128,10 +128,10 @@ struct avs_tplg_token_parser {
 static int
 avs_parse_uuid_token(struct snd_soc_component *comp, void *elem, void *object, u32 offset)
 {
-	struct snd_soc_tplg_vendor_value_elem *tuple = elem;
+	struct snd_soc_tplg_vendor_uuid_elem *tuple = elem;
 	guid_t *val = (guid_t *)((u8 *)object + offset);
 
-	guid_copy((guid_t *)val, (const guid_t *)&tuple->value);
+	guid_copy((guid_t *)val, (const guid_t *)&tuple->uuid);
 
 	return 0;
 }
-- 
GitLab


From 12abc4d10d5502e4f3d8f1c6f9e8245747a44708 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Amadeusz=20S=C5=82awi=C5=84ski?=
 <amadeuszx.slawinski@linux.intel.com>
Date: Fri, 10 Jun 2022 14:44:20 +0200
Subject: [PATCH 1137/1731] ASoC: Remove unused hw_write_t type
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Commit 81da8a0b7975 ("ASoC: remove codec hw_write/control_data") removed
use of hw_write_t in struct snd_soc_codec, but it left type definition.
Fully clean it up.

Fixes: 81da8a0b7975 ("ASoC: remove codec hw_write/control_data")
Signed-off-by: Amadeusz Sławiński <amadeuszx.slawinski@linux.intel.com>
Reviewed-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20220610124420.4160986-1-amadeuszx.slawinski@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 include/sound/soc.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/include/sound/soc.h b/include/sound/soc.h
index f20f5f890794a..b276dcb5d4e8b 100644
--- a/include/sound/soc.h
+++ b/include/sound/soc.h
@@ -408,8 +408,6 @@ struct snd_soc_jack_pin;
 
 struct snd_soc_jack_gpio;
 
-typedef int (*hw_write_t)(void *,const char* ,int);
-
 enum snd_soc_pcm_subclass {
 	SND_SOC_PCM_CLASS_PCM	= 0,
 	SND_SOC_PCM_CLASS_BE	= 1,
-- 
GitLab


From 58136d93d4e2c1207a5e4f3044815cd40b1d95fd Mon Sep 17 00:00:00 2001
From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Date: Fri, 10 Jun 2022 15:48:18 +0100
Subject: [PATCH 1138/1731] ASoC: qdsp6: q6apm-dai: unprepare stream if its
 already prepared

prepare callback can be called multiple times, so unprepare the stream
if its already prepared.

Without this DSP is not happy to setting the params on a already
prepared graph.

Fixes: 9b4fe0f1cd79 ("ASoC: qdsp6: audioreach: add q6apm-dai support")
Reported-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220610144818.511797-1-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/qcom/qdsp6/q6apm-dai.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/sound/soc/qcom/qdsp6/q6apm-dai.c b/sound/soc/qcom/qdsp6/q6apm-dai.c
index 19c4a90ec1ea9..ee59ef36b85a6 100644
--- a/sound/soc/qcom/qdsp6/q6apm-dai.c
+++ b/sound/soc/qcom/qdsp6/q6apm-dai.c
@@ -147,6 +147,12 @@ static int q6apm_dai_prepare(struct snd_soc_component *component,
 	cfg.num_channels = runtime->channels;
 	cfg.bit_width = prtd->bits_per_sample;
 
+	if (prtd->state) {
+		/* clear the previous setup if any  */
+		q6apm_graph_stop(prtd->graph);
+		q6apm_unmap_memory_regions(prtd->graph, substream->stream);
+	}
+
 	prtd->pcm_count = snd_pcm_lib_period_bytes(substream);
 	prtd->pos = 0;
 	/* rate and channels are sent to audio driver */
-- 
GitLab


From be6dd72edb216f20fc80e426ece9fe9b8aabf033 Mon Sep 17 00:00:00 2001
From: Yassine Oudjana <y.oudjana@protonmail.com>
Date: Mon, 6 Jun 2022 19:22:26 +0400
Subject: [PATCH 1139/1731] ASoC: wcd9335: Remove RX channel from old list
 before adding it to a new one

Currently in slim_rx_mux_put, an RX channel gets added to a new list
even if it is already in one. This can mess up links and make either
it, the new list head, or both, get linked to the wrong entries.
This can cause an entry to link to itself which in turn ends up
making list_for_each_entry in other functions loop infinitely.
To avoid issues, always remove the RX channel from any list it's in
before adding it to a new list.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Link: https://lore.kernel.org/r/20220606152226.149164-1-y.oudjana@protonmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/wcd9335.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/sound/soc/codecs/wcd9335.c b/sound/soc/codecs/wcd9335.c
index 617a36a89dfed..597420679505b 100644
--- a/sound/soc/codecs/wcd9335.c
+++ b/sound/soc/codecs/wcd9335.c
@@ -1289,9 +1289,12 @@ static int slim_rx_mux_put(struct snd_kcontrol *kc,
 
 	wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0];
 
+	/* Remove channel from any list it's in before adding it to a new one */
+	list_del_init(&wcd->rx_chs[port_id].list);
+
 	switch (wcd->rx_port_value[port_id]) {
 	case 0:
-		list_del_init(&wcd->rx_chs[port_id].list);
+		/* Channel already removed from lists. Nothing to do here */
 		break;
 	case 1:
 		list_add_tail(&wcd->rx_chs[port_id].list,
-- 
GitLab


From a7786cbae4b2732815da98efa39df96746b5bd0d Mon Sep 17 00:00:00 2001
From: Mark Brown <broonie@kernel.org>
Date: Fri, 3 Jun 2022 14:46:09 +0200
Subject: [PATCH 1140/1731] ASoC: wcd9335: Fix spurious event generation

The slimbus mux put operation unconditionally reports a change in value
which means that spurious events are generated. Fix this by exiting early
in that case.

Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220603124609.4024666-1-broonie@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/wcd9335.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/sound/soc/codecs/wcd9335.c b/sound/soc/codecs/wcd9335.c
index 597420679505b..d9f1352006881 100644
--- a/sound/soc/codecs/wcd9335.c
+++ b/sound/soc/codecs/wcd9335.c
@@ -1287,6 +1287,9 @@ static int slim_rx_mux_put(struct snd_kcontrol *kc,
 	struct snd_soc_dapm_update *update = NULL;
 	u32 port_id = w->shift;
 
+	if (wcd->rx_port_value[port_id] == ucontrol->value.enumerated.item[0])
+		return 0;
+
 	wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0];
 
 	/* Remove channel from any list it's in before adding it to a new one */
-- 
GitLab


From 10e7ff0047921e32b919ecee7be706dd33c107f8 Mon Sep 17 00:00:00 2001
From: Mark Brown <broonie@kernel.org>
Date: Fri, 3 Jun 2022 14:25:26 +0200
Subject: [PATCH 1141/1731] ASoC: wcd938x: Fix event generation for some
 controls

Currently wcd938x_*_put() unconditionally report that the value of the
control changed, resulting in spurious events being generated. Return 0 in
that case instead as we should. There is still an issue in the compander
control which is a bit more complex.

Signed-off-by: Mark Brown <broonie@kernel.org>
Reported-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/r/20220603122526.3914942-1-broonie@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/wcd938x.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/sound/soc/codecs/wcd938x.c b/sound/soc/codecs/wcd938x.c
index c1b61b997f696..781ae569be290 100644
--- a/sound/soc/codecs/wcd938x.c
+++ b/sound/soc/codecs/wcd938x.c
@@ -2519,6 +2519,9 @@ static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 	int path = e->shift_l;
 
+	if (wcd938x->tx_mode[path] == ucontrol->value.enumerated.item[0])
+		return 0;
+
 	wcd938x->tx_mode[path] = ucontrol->value.enumerated.item[0];
 
 	return 1;
@@ -2541,6 +2544,9 @@ static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 	struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
 
+	if (wcd938x->hph_mode == ucontrol->value.enumerated.item[0])
+		return 0;
+
 	wcd938x->hph_mode = ucontrol->value.enumerated.item[0];
 
 	return 1;
@@ -2632,6 +2638,9 @@ static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 	struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
 
+	if (wcd938x->ldoh == ucontrol->value.integer.value[0])
+		return 0;
+
 	wcd938x->ldoh = ucontrol->value.integer.value[0];
 
 	return 1;
@@ -2654,6 +2663,9 @@ static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 	struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
 
+	if (wcd938x->bcs_dis == ucontrol->value.integer.value[0])
+		return 0;
+
 	wcd938x->bcs_dis = ucontrol->value.integer.value[0];
 
 	return 1;
-- 
GitLab


From a7d9391dc3d570aed87ed764db95b16760c898e4 Mon Sep 17 00:00:00 2001
From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Date: Fri, 10 Jun 2022 16:43:13 -0500
Subject: [PATCH 1142/1731] MAINTAINERS: update ASoC/Intel/SOF maintainers
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Keyon Jie was a key contributor to the Intel ASoC and SOF Intel
drivers, but he's moved on to a different role within Intel. We wish
him all the best in his new endeavors.

Bard Liao, Kai Vehmanen, Ranjani Sridharan and Peter Ujfalusi have
been involved in the Intel multi-maintainer team, it's time to update
the MAINTAINERS entry to reflect their contributions and clarify their
role.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://lore.kernel.org/r/20220610214313.42903-1-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 MAINTAINERS | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index a6d3bd9d2a8d0..440f3d7c93b9e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9803,7 +9803,10 @@ INTEL ASoC DRIVERS
 M:	Cezary Rojewski <cezary.rojewski@intel.com>
 M:	Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
 M:	Liam Girdwood <liam.r.girdwood@linux.intel.com>
-M:	Jie Yang <yang.jie@linux.intel.com>
+M:	Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
+M:	Bard Liao <yung-chuan.liao@linux.intel.com>
+M:	Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
+M:	Kai Vehmanen <kai.vehmanen@linux.intel.com>
 L:	alsa-devel@alsa-project.org (moderated for non-subscribers)
 S:	Supported
 F:	sound/soc/intel/
@@ -18670,8 +18673,10 @@ F:	sound/soc/
 SOUND - SOUND OPEN FIRMWARE (SOF) DRIVERS
 M:	Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
 M:	Liam Girdwood <lgirdwood@gmail.com>
+M:	Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
+M:	Bard Liao <yung-chuan.liao@linux.intel.com>
 M:	Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
-M:	Kai Vehmanen <kai.vehmanen@linux.intel.com>
+R:	Kai Vehmanen <kai.vehmanen@linux.intel.com>
 M:	Daniel Baluta <daniel.baluta@nxp.com>
 L:	sound-open-firmware@alsa-project.org (moderated for non-subscribers)
 S:	Supported
-- 
GitLab


From 4e07479eab8a044cc9542414ccb4aeb8eb033bde Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sun, 12 Jun 2022 17:56:52 +0200
Subject: [PATCH 1143/1731] ASoC: Intel: bytcr_wm5102: Fix GPIO related
 probe-ordering problem

The "wlf,spkvdd-ena" GPIO needed by the bytcr_wm5102 driver
is made available through a gpio-lookup table.

This gpio-lookup table is registered by drivers/mfd/arizona-spi.c, which
may get probed after the bytcr_wm5102 driver.

If the gpio-lookup table has not registered yet then the gpiod_get()
will return -ENOENT. Treat -ENOENT as -EPROBE_DEFER to still keep
things working in this case.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20220612155652.107310-1-hdegoede@redhat.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/boards/bytcr_wm5102.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/sound/soc/intel/boards/bytcr_wm5102.c b/sound/soc/intel/boards/bytcr_wm5102.c
index 00384c6fbcaa5..330c0ace16387 100644
--- a/sound/soc/intel/boards/bytcr_wm5102.c
+++ b/sound/soc/intel/boards/bytcr_wm5102.c
@@ -421,8 +421,17 @@ static int snd_byt_wm5102_mc_probe(struct platform_device *pdev)
 	priv->spkvdd_en_gpio = gpiod_get(codec_dev, "wlf,spkvdd-ena", GPIOD_OUT_LOW);
 	put_device(codec_dev);
 
-	if (IS_ERR(priv->spkvdd_en_gpio))
-		return dev_err_probe(dev, PTR_ERR(priv->spkvdd_en_gpio), "getting spkvdd-GPIO\n");
+	if (IS_ERR(priv->spkvdd_en_gpio)) {
+		ret = PTR_ERR(priv->spkvdd_en_gpio);
+		/*
+		 * The spkvdd gpio-lookup is registered by: drivers/mfd/arizona-spi.c,
+		 * so -ENOENT means that arizona-spi hasn't probed yet.
+		 */
+		if (ret == -ENOENT)
+			ret = -EPROBE_DEFER;
+
+		return dev_err_probe(dev, ret, "getting spkvdd-GPIO\n");
+	}
 
 	/* override platform name, if required */
 	byt_wm5102_card.dev = dev;
-- 
GitLab


From 427eb3e1ed530792231bc5bbee6dec99fc57aeb7 Mon Sep 17 00:00:00 2001
From: Dan Carpenter <dan.carpenter@oracle.com>
Date: Wed, 15 Jun 2022 11:19:44 +0300
Subject: [PATCH 1144/1731] ASoC: SOF: mediatek: Fix error code in probe

This should return PTR_ERR() instead of IS_ERR().

Fixes: e0100bfd383c ("ASoC: SOF: mediatek: Add mt8186 ipc support")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/YqmWIK8sTj578OJP@kili
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/sof/mediatek/mt8186/mt8186.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/sof/mediatek/mt8186/mt8186.c b/sound/soc/sof/mediatek/mt8186/mt8186.c
index 3333a0634e29d..e006532caf2f0 100644
--- a/sound/soc/sof/mediatek/mt8186/mt8186.c
+++ b/sound/soc/sof/mediatek/mt8186/mt8186.c
@@ -392,7 +392,7 @@ static int mt8186_dsp_probe(struct snd_sof_dev *sdev)
 						      PLATFORM_DEVID_NONE,
 						      pdev, sizeof(*pdev));
 	if (IS_ERR(priv->ipc_dev)) {
-		ret = IS_ERR(priv->ipc_dev);
+		ret = PTR_ERR(priv->ipc_dev);
 		dev_err(sdev->dev, "failed to create mtk-adsp-ipc device\n");
 		goto err_adsp_off;
 	}
-- 
GitLab


From ca7ab1dcf58dfce5bc851bf7e50fd94822c24665 Mon Sep 17 00:00:00 2001
From: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Date: Thu, 16 Jun 2022 15:19:53 -0500
Subject: [PATCH 1145/1731] ASoC: SOF: Intel: hda: Fix compressed stream
 position tracking

Commit 288fad2f71fa ("ASoC: SOF: Intel: hda: add quirks for HDAudio DMA position information")
modified the PCM path only, but left the compressed data patch using an
obsolete option.
Move the functionality in a helper that can be called for both PCM and
compressed data.

Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Fixes: 288fad2f71fa ("ASoC: SOF: Intel: hda: add quirks for HDAudio DMA position information")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20220616201953.130876-1-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/sof/intel/hda-pcm.c    | 74 +------------------------
 sound/soc/sof/intel/hda-stream.c | 94 ++++++++++++++++++++++++++++++--
 sound/soc/sof/intel/hda.h        |  3 +
 3 files changed, 94 insertions(+), 77 deletions(-)

diff --git a/sound/soc/sof/intel/hda-pcm.c b/sound/soc/sof/intel/hda-pcm.c
index dc1f743730c0d..6888e0a4665d2 100644
--- a/sound/soc/sof/intel/hda-pcm.c
+++ b/sound/soc/sof/intel/hda-pcm.c
@@ -192,79 +192,7 @@ snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
 		goto found;
 	}
 
-	switch (sof_hda_position_quirk) {
-	case SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY:
-		/*
-		 * This legacy code, inherited from the Skylake driver,
-		 * mixes DPIB registers and DPIB DDR updates and
-		 * does not seem to follow any known hardware recommendations.
-		 * It's not clear e.g. why there is a different flow
-		 * for capture and playback, the only information that matters is
-		 * what traffic class is used, and on all SOF-enabled platforms
-		 * only VC0 is supported so the work-around was likely not necessary
-		 * and quite possibly wrong.
-		 */
-
-		/* DPIB/posbuf position mode:
-		 * For Playback, Use DPIB register from HDA space which
-		 * reflects the actual data transferred.
-		 * For Capture, Use the position buffer for pointer, as DPIB
-		 * is not accurate enough, its update may be completed
-		 * earlier than the data written to DDR.
-		 */
-		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
-			pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
-					       AZX_REG_VS_SDXDPIB_XBASE +
-					       (AZX_REG_VS_SDXDPIB_XINTERVAL *
-						hstream->index));
-		} else {
-			/*
-			 * For capture stream, we need more workaround to fix the
-			 * position incorrect issue:
-			 *
-			 * 1. Wait at least 20us before reading position buffer after
-			 * the interrupt generated(IOC), to make sure position update
-			 * happens on frame boundary i.e. 20.833uSec for 48KHz.
-			 * 2. Perform a dummy Read to DPIB register to flush DMA
-			 * position value.
-			 * 3. Read the DMA Position from posbuf. Now the readback
-			 * value should be >= period boundary.
-			 */
-			usleep_range(20, 21);
-			snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
-					 AZX_REG_VS_SDXDPIB_XBASE +
-					 (AZX_REG_VS_SDXDPIB_XINTERVAL *
-					  hstream->index));
-			pos = snd_hdac_stream_get_pos_posbuf(hstream);
-		}
-		break;
-	case SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS:
-		/*
-		 * In case VC1 traffic is disabled this is the recommended option
-		 */
-		pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
-				       AZX_REG_VS_SDXDPIB_XBASE +
-				       (AZX_REG_VS_SDXDPIB_XINTERVAL *
-					hstream->index));
-		break;
-	case SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE:
-		/*
-		 * This is the recommended option when VC1 is enabled.
-		 * While this isn't needed for SOF platforms it's added for
-		 * consistency and debug.
-		 */
-		pos = snd_hdac_stream_get_pos_posbuf(hstream);
-		break;
-	default:
-		dev_err_once(sdev->dev, "hda_position_quirk value %d not supported\n",
-			     sof_hda_position_quirk);
-		pos = 0;
-		break;
-	}
-
-	if (pos >= hstream->bufsize)
-		pos = 0;
-
+	pos = hda_dsp_stream_get_position(hstream, substream->stream, true);
 found:
 	pos = bytes_to_frames(substream->runtime, pos);
 
diff --git a/sound/soc/sof/intel/hda-stream.c b/sound/soc/sof/intel/hda-stream.c
index daeb64c495e40..d95ae17e81cc4 100644
--- a/sound/soc/sof/intel/hda-stream.c
+++ b/sound/soc/sof/intel/hda-stream.c
@@ -707,12 +707,13 @@ bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev)
 }
 
 static void
-hda_dsp_set_bytes_transferred(struct hdac_stream *hstream, u64 buffer_size)
+hda_dsp_compr_bytes_transferred(struct hdac_stream *hstream, int direction)
 {
+	u64 buffer_size = hstream->bufsize;
 	u64 prev_pos, pos, num_bytes;
 
 	div64_u64_rem(hstream->curr_pos, buffer_size, &prev_pos);
-	pos = snd_hdac_stream_get_pos_posbuf(hstream);
+	pos = hda_dsp_stream_get_position(hstream, direction, false);
 
 	if (pos < prev_pos)
 		num_bytes = (buffer_size - prev_pos) +  pos;
@@ -748,8 +749,7 @@ static bool hda_dsp_stream_check(struct hdac_bus *bus, u32 status)
 			if (s->substream && sof_hda->no_ipc_position) {
 				snd_sof_pcm_period_elapsed(s->substream);
 			} else if (s->cstream) {
-				hda_dsp_set_bytes_transferred(s,
-					s->cstream->runtime->buffer_size);
+				hda_dsp_compr_bytes_transferred(s, s->cstream->direction);
 				snd_compr_fragment_elapsed(s->cstream);
 			}
 		}
@@ -1009,3 +1009,89 @@ void hda_dsp_stream_free(struct snd_sof_dev *sdev)
 		devm_kfree(sdev->dev, hda_stream);
 	}
 }
+
+snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream,
+					      int direction, bool can_sleep)
+{
+	struct hdac_ext_stream *hext_stream = stream_to_hdac_ext_stream(hstream);
+	struct sof_intel_hda_stream *hda_stream = hstream_to_sof_hda_stream(hext_stream);
+	struct snd_sof_dev *sdev = hda_stream->sdev;
+	snd_pcm_uframes_t pos;
+
+	switch (sof_hda_position_quirk) {
+	case SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY:
+		/*
+		 * This legacy code, inherited from the Skylake driver,
+		 * mixes DPIB registers and DPIB DDR updates and
+		 * does not seem to follow any known hardware recommendations.
+		 * It's not clear e.g. why there is a different flow
+		 * for capture and playback, the only information that matters is
+		 * what traffic class is used, and on all SOF-enabled platforms
+		 * only VC0 is supported so the work-around was likely not necessary
+		 * and quite possibly wrong.
+		 */
+
+		/* DPIB/posbuf position mode:
+		 * For Playback, Use DPIB register from HDA space which
+		 * reflects the actual data transferred.
+		 * For Capture, Use the position buffer for pointer, as DPIB
+		 * is not accurate enough, its update may be completed
+		 * earlier than the data written to DDR.
+		 */
+		if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
+			pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
+					       AZX_REG_VS_SDXDPIB_XBASE +
+					       (AZX_REG_VS_SDXDPIB_XINTERVAL *
+						hstream->index));
+		} else {
+			/*
+			 * For capture stream, we need more workaround to fix the
+			 * position incorrect issue:
+			 *
+			 * 1. Wait at least 20us before reading position buffer after
+			 * the interrupt generated(IOC), to make sure position update
+			 * happens on frame boundary i.e. 20.833uSec for 48KHz.
+			 * 2. Perform a dummy Read to DPIB register to flush DMA
+			 * position value.
+			 * 3. Read the DMA Position from posbuf. Now the readback
+			 * value should be >= period boundary.
+			 */
+			if (can_sleep)
+				usleep_range(20, 21);
+
+			snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
+					 AZX_REG_VS_SDXDPIB_XBASE +
+					 (AZX_REG_VS_SDXDPIB_XINTERVAL *
+					  hstream->index));
+			pos = snd_hdac_stream_get_pos_posbuf(hstream);
+		}
+		break;
+	case SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS:
+		/*
+		 * In case VC1 traffic is disabled this is the recommended option
+		 */
+		pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
+				       AZX_REG_VS_SDXDPIB_XBASE +
+				       (AZX_REG_VS_SDXDPIB_XINTERVAL *
+					hstream->index));
+		break;
+	case SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE:
+		/*
+		 * This is the recommended option when VC1 is enabled.
+		 * While this isn't needed for SOF platforms it's added for
+		 * consistency and debug.
+		 */
+		pos = snd_hdac_stream_get_pos_posbuf(hstream);
+		break;
+	default:
+		dev_err_once(sdev->dev, "hda_position_quirk value %d not supported\n",
+			     sof_hda_position_quirk);
+		pos = 0;
+		break;
+	}
+
+	if (pos >= hstream->bufsize)
+		pos = 0;
+
+	return pos;
+}
diff --git a/sound/soc/sof/intel/hda.h b/sound/soc/sof/intel/hda.h
index 0f57ef5d9b8e9..06476ffe96d73 100644
--- a/sound/soc/sof/intel/hda.h
+++ b/sound/soc/sof/intel/hda.h
@@ -565,6 +565,9 @@ int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
 bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev);
 bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev);
 
+snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream,
+					      int direction, bool can_sleep);
+
 struct hdac_ext_stream *
 	hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags);
 int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
-- 
GitLab


From a933084558c61cac8c902d2474b39444d87fba46 Mon Sep 17 00:00:00 2001
From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Date: Thu, 16 Jun 2022 15:18:16 -0500
Subject: [PATCH 1146/1731] ASoC: SOF: pm: add explicit behavior for ACPI S1
 and S2
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The existing code only deals with S0 and S3, let's start adding S1 and S2.

No functional change.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://lore.kernel.org/r/20220616201818.130802-2-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/sof/pm.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/sound/soc/sof/pm.c b/sound/soc/sof/pm.c
index 18eb327a57f03..239f39a5166a4 100644
--- a/sound/soc/sof/pm.c
+++ b/sound/soc/sof/pm.c
@@ -335,8 +335,18 @@ int snd_sof_prepare(struct device *dev)
 		return 0;
 
 #if defined(CONFIG_ACPI)
-	if (acpi_target_system_state() == ACPI_STATE_S0)
+	switch (acpi_target_system_state()) {
+	case ACPI_STATE_S0:
 		sdev->system_suspend_target = SOF_SUSPEND_S0IX;
+		break;
+	case ACPI_STATE_S1:
+	case ACPI_STATE_S2:
+	case ACPI_STATE_S3:
+		sdev->system_suspend_target = SOF_SUSPEND_S3;
+		break;
+	default:
+		break;
+	}
 #endif
 
 	return 0;
-- 
GitLab


From 9d2d462713384538477703e68577b05131c7d97d Mon Sep 17 00:00:00 2001
From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Date: Thu, 16 Jun 2022 15:18:17 -0500
Subject: [PATCH 1147/1731] ASoC: SOF: pm: add definitions for S4 and S5 states
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

We currently don't have a means to differentiate between S3, S4 and
S5. Add definitions so that we have select different code paths
depending on the target state in follow-up patches.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://lore.kernel.org/r/20220616201818.130802-3-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/sof/pm.c       | 9 +++++++++
 sound/soc/sof/sof-priv.h | 2 ++
 2 files changed, 11 insertions(+)

diff --git a/sound/soc/sof/pm.c b/sound/soc/sof/pm.c
index 239f39a5166a4..df740be645e84 100644
--- a/sound/soc/sof/pm.c
+++ b/sound/soc/sof/pm.c
@@ -23,6 +23,9 @@ static u32 snd_sof_dsp_power_target(struct snd_sof_dev *sdev)
 	u32 target_dsp_state;
 
 	switch (sdev->system_suspend_target) {
+	case SOF_SUSPEND_S5:
+	case SOF_SUSPEND_S4:
+		/* DSP should be in D3 if the system is suspending to S3+ */
 	case SOF_SUSPEND_S3:
 		/* DSP should be in D3 if the system is suspending to S3 */
 		target_dsp_state = SOF_DSP_PM_D3;
@@ -344,6 +347,12 @@ int snd_sof_prepare(struct device *dev)
 	case ACPI_STATE_S3:
 		sdev->system_suspend_target = SOF_SUSPEND_S3;
 		break;
+	case ACPI_STATE_S4:
+		sdev->system_suspend_target = SOF_SUSPEND_S4;
+		break;
+	case ACPI_STATE_S5:
+		sdev->system_suspend_target = SOF_SUSPEND_S5;
+		break;
 	default:
 		break;
 	}
diff --git a/sound/soc/sof/sof-priv.h b/sound/soc/sof/sof-priv.h
index 9d7f53ff9c70e..f0f3d72c0da73 100644
--- a/sound/soc/sof/sof-priv.h
+++ b/sound/soc/sof/sof-priv.h
@@ -85,6 +85,8 @@ enum sof_system_suspend_state {
 	SOF_SUSPEND_NONE = 0,
 	SOF_SUSPEND_S0IX,
 	SOF_SUSPEND_S3,
+	SOF_SUSPEND_S4,
+	SOF_SUSPEND_S5,
 };
 
 enum sof_dfsentry_type {
-- 
GitLab


From 391153522d186f19a008d824bb3a05950351ce6c Mon Sep 17 00:00:00 2001
From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Date: Thu, 16 Jun 2022 15:18:18 -0500
Subject: [PATCH 1148/1731] ASoC: SOF: Intel: disable IMR boot when resuming
 from ACPI S4 and S5 states
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The IMR was assumed to be preserved when suspending to S4 and S5
states, but community reports invalidate that assumption, the hardware
seems to be powered off and the IMR memory content cleared.

Make sure regular boot with firmware download is used for S4 and S5.

BugLink: https://github.com/thesofproject/sof/issues/5892
Fixes: 5fb5f51185126 ("ASoC: SOF: Intel: hda-loader: add IMR restore support")
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://lore.kernel.org/r/20220616201818.130802-4-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/sof/intel/hda-loader.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/sound/soc/sof/intel/hda-loader.c b/sound/soc/sof/intel/hda-loader.c
index d3ec5996a9a3d..145d483bd129f 100644
--- a/sound/soc/sof/intel/hda-loader.c
+++ b/sound/soc/sof/intel/hda-loader.c
@@ -389,7 +389,8 @@ int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev)
 	struct snd_dma_buffer dmab;
 	int ret, ret1, i;
 
-	if (hda->imrboot_supported && !sdev->first_boot) {
+	if (sdev->system_suspend_target < SOF_SUSPEND_S4 &&
+	    hda->imrboot_supported && !sdev->first_boot) {
 		dev_dbg(sdev->dev, "IMR restore supported, booting from IMR directly\n");
 		hda->boot_iteration = 0;
 		ret = hda_dsp_boot_imr(sdev);
-- 
GitLab


From a5450aba737dae3ee1a64b282e609d8375d6700c Mon Sep 17 00:00:00 2001
From: Judy Hsiao <judyhsiao@chromium.org>
Date: Wed, 15 Jun 2022 04:56:43 +0000
Subject: [PATCH 1149/1731] ASoC: rockchip: i2s: switch BCLK to GPIO

We discoverd that the state of BCLK on, LRCLK off and SD_MODE on
may cause the speaker melting issue. Removing LRCLK while BCLK
is present can cause unexpected output behavior including a large
DC output voltage as described in the Max98357a datasheet.

In order to:
  1. prevent BCLK from turning on by other component.
  2. keep BCLK and LRCLK being present at the same time

This patch switches BCLK to GPIO func before LRCLK output, and
configures BCLK func back during LRCLK is output.

Without this fix, BCLK is turned on 11 ms earlier than LRCK by the
da7219.
With this fix, BCLK is turned on only 0.4 ms earlier than LRCK by
the rockchip codec.

Signed-off-by: Judy Hsiao <judyhsiao@chromium.org>
Link: https://lore.kernel.org/r/20220615045643.3137287-1-judyhsiao@chromium.org
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/rockchip/rockchip_i2s.c | 160 ++++++++++++++++++++++++------
 1 file changed, 129 insertions(+), 31 deletions(-)

diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c
index 4ce5d25793875..99a128a666fbb 100644
--- a/sound/soc/rockchip/rockchip_i2s.c
+++ b/sound/soc/rockchip/rockchip_i2s.c
@@ -13,6 +13,7 @@
 #include <linux/of_gpio.h>
 #include <linux/of_device.h>
 #include <linux/clk.h>
+#include <linux/pinctrl/consumer.h>
 #include <linux/pm_runtime.h>
 #include <linux/regmap.h>
 #include <linux/spinlock.h>
@@ -54,8 +55,40 @@ struct rk_i2s_dev {
 	const struct rk_i2s_pins *pins;
 	unsigned int bclk_ratio;
 	spinlock_t lock; /* tx/rx lock */
+	struct pinctrl *pinctrl;
+	struct pinctrl_state *bclk_on;
+	struct pinctrl_state *bclk_off;
 };
 
+static int i2s_pinctrl_select_bclk_on(struct rk_i2s_dev *i2s)
+{
+	int ret = 0;
+
+	if (!IS_ERR(i2s->pinctrl) && !IS_ERR_OR_NULL(i2s->bclk_on))
+		ret = pinctrl_select_state(i2s->pinctrl,
+				     i2s->bclk_on);
+
+	if (ret)
+		dev_err(i2s->dev, "bclk enable failed %d\n", ret);
+
+	return ret;
+}
+
+static int i2s_pinctrl_select_bclk_off(struct rk_i2s_dev *i2s)
+{
+
+	int ret = 0;
+
+	if (!IS_ERR(i2s->pinctrl) && !IS_ERR_OR_NULL(i2s->bclk_off))
+		ret = pinctrl_select_state(i2s->pinctrl,
+				     i2s->bclk_off);
+
+	if (ret)
+		dev_err(i2s->dev, "bclk disable failed %d\n", ret);
+
+	return ret;
+}
+
 static int i2s_runtime_suspend(struct device *dev)
 {
 	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
@@ -92,38 +125,49 @@ static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
 	return snd_soc_dai_get_drvdata(dai);
 }
 
-static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
+static int rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
 {
 	unsigned int val = 0;
 	int retry = 10;
+	int ret = 0;
 
 	spin_lock(&i2s->lock);
 	if (on) {
-		regmap_update_bits(i2s->regmap, I2S_DMACR,
-				   I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
+		ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
+				I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
+		if (ret < 0)
+			goto end;
 
-		regmap_update_bits(i2s->regmap, I2S_XFER,
-				   I2S_XFER_TXS_START | I2S_XFER_RXS_START,
-				   I2S_XFER_TXS_START | I2S_XFER_RXS_START);
+		ret = regmap_update_bits(i2s->regmap, I2S_XFER,
+				I2S_XFER_TXS_START | I2S_XFER_RXS_START,
+				I2S_XFER_TXS_START | I2S_XFER_RXS_START);
+		if (ret < 0)
+			goto end;
 
 		i2s->tx_start = true;
 	} else {
 		i2s->tx_start = false;
 
-		regmap_update_bits(i2s->regmap, I2S_DMACR,
-				   I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
+		ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
+				I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
+		if (ret < 0)
+			goto end;
 
 		if (!i2s->rx_start) {
-			regmap_update_bits(i2s->regmap, I2S_XFER,
-					   I2S_XFER_TXS_START |
-					   I2S_XFER_RXS_START,
-					   I2S_XFER_TXS_STOP |
-					   I2S_XFER_RXS_STOP);
+			ret = regmap_update_bits(i2s->regmap, I2S_XFER,
+					I2S_XFER_TXS_START |
+					I2S_XFER_RXS_START,
+					I2S_XFER_TXS_STOP |
+					I2S_XFER_RXS_STOP);
+			if (ret < 0)
+				goto end;
 
 			udelay(150);
-			regmap_update_bits(i2s->regmap, I2S_CLR,
-					   I2S_CLR_TXC | I2S_CLR_RXC,
-					   I2S_CLR_TXC | I2S_CLR_RXC);
+			ret = regmap_update_bits(i2s->regmap, I2S_CLR,
+					I2S_CLR_TXC | I2S_CLR_RXC,
+					I2S_CLR_TXC | I2S_CLR_RXC);
+			if (ret < 0)
+				goto end;
 
 			regmap_read(i2s->regmap, I2S_CLR, &val);
 
@@ -138,44 +182,57 @@ static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
 			}
 		}
 	}
+end:
 	spin_unlock(&i2s->lock);
+	if (ret < 0)
+		dev_err(i2s->dev, "lrclk update failed\n");
+
+	return ret;
 }
 
-static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
+static int rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
 {
 	unsigned int val = 0;
 	int retry = 10;
+	int ret = 0;
 
 	spin_lock(&i2s->lock);
 	if (on) {
-		regmap_update_bits(i2s->regmap, I2S_DMACR,
+		ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
 				   I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
+		if (ret < 0)
+			goto end;
 
-		regmap_update_bits(i2s->regmap, I2S_XFER,
+		ret = regmap_update_bits(i2s->regmap, I2S_XFER,
 				   I2S_XFER_TXS_START | I2S_XFER_RXS_START,
 				   I2S_XFER_TXS_START | I2S_XFER_RXS_START);
+		if (ret < 0)
+			goto end;
 
 		i2s->rx_start = true;
 	} else {
 		i2s->rx_start = false;
 
-		regmap_update_bits(i2s->regmap, I2S_DMACR,
+		ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
 				   I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
+		if (ret < 0)
+			goto end;
 
 		if (!i2s->tx_start) {
-			regmap_update_bits(i2s->regmap, I2S_XFER,
+			ret = regmap_update_bits(i2s->regmap, I2S_XFER,
 					   I2S_XFER_TXS_START |
 					   I2S_XFER_RXS_START,
 					   I2S_XFER_TXS_STOP |
 					   I2S_XFER_RXS_STOP);
-
+			if (ret < 0)
+				goto end;
 			udelay(150);
-			regmap_update_bits(i2s->regmap, I2S_CLR,
+			ret = regmap_update_bits(i2s->regmap, I2S_CLR,
 					   I2S_CLR_TXC | I2S_CLR_RXC,
 					   I2S_CLR_TXC | I2S_CLR_RXC);
-
+			if (ret < 0)
+				goto end;
 			regmap_read(i2s->regmap, I2S_CLR, &val);
-
 			/* Should wait for clear operation to finish */
 			while (val) {
 				regmap_read(i2s->regmap, I2S_CLR, &val);
@@ -187,7 +244,12 @@ static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
 			}
 		}
 	}
+end:
 	spin_unlock(&i2s->lock);
+	if (ret < 0)
+		dev_err(i2s->dev, "lrclk update failed\n");
+
+	return ret;
 }
 
 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
@@ -425,17 +487,26 @@ static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
 	case SNDRV_PCM_TRIGGER_RESUME:
 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
-			rockchip_snd_rxctrl(i2s, 1);
+			ret = rockchip_snd_rxctrl(i2s, 1);
 		else
-			rockchip_snd_txctrl(i2s, 1);
+			ret = rockchip_snd_txctrl(i2s, 1);
+		/* Do not turn on bclk if lrclk open fails. */
+		if (ret < 0)
+			return ret;
+		i2s_pinctrl_select_bclk_on(i2s);
 		break;
 	case SNDRV_PCM_TRIGGER_SUSPEND:
 	case SNDRV_PCM_TRIGGER_STOP:
 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
-		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
-			rockchip_snd_rxctrl(i2s, 0);
-		else
-			rockchip_snd_txctrl(i2s, 0);
+		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+			if (!i2s->tx_start)
+				i2s_pinctrl_select_bclk_off(i2s);
+			ret = rockchip_snd_rxctrl(i2s, 0);
+		} else {
+			if (!i2s->rx_start)
+				i2s_pinctrl_select_bclk_off(i2s);
+			ret = rockchip_snd_txctrl(i2s, 0);
+		}
 		break;
 	default:
 		ret = -EINVAL;
@@ -736,6 +807,33 @@ static int rockchip_i2s_probe(struct platform_device *pdev)
 	}
 
 	i2s->bclk_ratio = 64;
+	i2s->pinctrl = devm_pinctrl_get(&pdev->dev);
+	if (IS_ERR(i2s->pinctrl))
+		dev_err(&pdev->dev, "failed to find i2s pinctrl\n");
+
+	i2s->bclk_on = pinctrl_lookup_state(i2s->pinctrl,
+				   "bclk_on");
+	if (IS_ERR_OR_NULL(i2s->bclk_on))
+		dev_err(&pdev->dev, "failed to find i2s default state\n");
+	else
+		dev_dbg(&pdev->dev, "find i2s bclk state\n");
+
+	i2s->bclk_off = pinctrl_lookup_state(i2s->pinctrl,
+				  "bclk_off");
+	if (IS_ERR_OR_NULL(i2s->bclk_off))
+		dev_err(&pdev->dev, "failed to find i2s gpio state\n");
+	else
+		dev_dbg(&pdev->dev, "find i2s bclk_off state\n");
+
+	i2s_pinctrl_select_bclk_off(i2s);
+
+	i2s->playback_dma_data.addr = res->start + I2S_TXDR;
+	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+	i2s->playback_dma_data.maxburst = 4;
+
+	i2s->capture_dma_data.addr = res->start + I2S_RXDR;
+	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+	i2s->capture_dma_data.maxburst = 4;
 
 	dev_set_drvdata(&pdev->dev, i2s);
 
-- 
GitLab


From f2c2f31f00ce48d96dec28b9f8d70f73213ed4af Mon Sep 17 00:00:00 2001
From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Date: Fri, 17 Jun 2022 14:02:30 -0700
Subject: [PATCH 1150/1731] MAINTAINERS: update ASoC Qualcomm maintainer
 email-id

Update Banajit's email address from codeaurora.org to quicinc.com, as
codeaurora.org is not in use anymore.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220617210230.7685-1-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 440f3d7c93b9e..171fa31606960 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16247,7 +16247,7 @@ F:	drivers/crypto/qat/
 
 QCOM AUDIO (ASoC) DRIVERS
 M:	Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
-M:	Banajit Goswami <bgoswami@codeaurora.org>
+M:	Banajit Goswami <bgoswami@quicinc.com>
 L:	alsa-devel@alsa-project.org (moderated for non-subscribers)
 S:	Supported
 F:	sound/soc/codecs/lpass-va-macro.c
-- 
GitLab


From 9896c029f0df628c6cb108253d09b1d61f1d4a88 Mon Sep 17 00:00:00 2001
From: Charles Keepax <ckeepax@opensource.cirrus.com>
Date: Tue, 21 Jun 2022 11:20:38 +0100
Subject: [PATCH 1151/1731] ASoC: wm_adsp: Fix event for preloader

The preloader controls on ADSP should return a value of 1 if the
preloader value was changed, update to correct this.

Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20220621102041.1713504-1-ckeepax@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/wm_adsp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/codecs/wm_adsp.c b/sound/soc/codecs/wm_adsp.c
index 6d7fd88243aa8..a7784ac15dde6 100644
--- a/sound/soc/codecs/wm_adsp.c
+++ b/sound/soc/codecs/wm_adsp.c
@@ -997,7 +997,7 @@ int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol,
 		snd_soc_dapm_sync(dapm);
 	}
 
-	return 0;
+	return 1;
 }
 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put);
 
-- 
GitLab


From 0bc0ae9a5938d512fd5d44f11c9c04892dcf4961 Mon Sep 17 00:00:00 2001
From: Charles Keepax <ckeepax@opensource.cirrus.com>
Date: Tue, 21 Jun 2022 11:20:39 +0100
Subject: [PATCH 1152/1731] ASoC: wm5110: Fix DRE control

The DRE controls on wm5110 should return a value of 1 if the DRE state
is actually changed, update to fix this.

Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20220621102041.1713504-2-ckeepax@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/wm5110.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/sound/soc/codecs/wm5110.c b/sound/soc/codecs/wm5110.c
index 4973ba1ed7791..4ab7a672f8de8 100644
--- a/sound/soc/codecs/wm5110.c
+++ b/sound/soc/codecs/wm5110.c
@@ -413,6 +413,7 @@ static int wm5110_put_dre(struct snd_kcontrol *kcontrol,
 	unsigned int rnew = (!!ucontrol->value.integer.value[1]) << mc->rshift;
 	unsigned int lold, rold;
 	unsigned int lena, rena;
+	bool change = false;
 	int ret;
 
 	snd_soc_dapm_mutex_lock(dapm);
@@ -440,8 +441,8 @@ static int wm5110_put_dre(struct snd_kcontrol *kcontrol,
 		goto err;
 	}
 
-	ret = regmap_update_bits(arizona->regmap, ARIZONA_DRE_ENABLE,
-				 mask, lnew | rnew);
+	ret = regmap_update_bits_check(arizona->regmap, ARIZONA_DRE_ENABLE,
+				       mask, lnew | rnew, &change);
 	if (ret) {
 		dev_err(arizona->dev, "Failed to set DRE: %d\n", ret);
 		goto err;
@@ -454,6 +455,9 @@ static int wm5110_put_dre(struct snd_kcontrol *kcontrol,
 	if (!rnew && rold)
 		wm5110_clear_pga_volume(arizona, mc->rshift);
 
+	if (change)
+		ret = 1;
+
 err:
 	snd_soc_dapm_mutex_unlock(dapm);
 
-- 
GitLab


From c6a5f22f9b4fd5f21414be690ce34046d9712f05 Mon Sep 17 00:00:00 2001
From: Charles Keepax <ckeepax@opensource.cirrus.com>
Date: Tue, 21 Jun 2022 11:20:40 +0100
Subject: [PATCH 1153/1731] ASoC: cs35l41: Correct some control names

Various boolean controls on cs35l41 are missing the required "Switch" in
the name, add these.

Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20220621102041.1713504-3-ckeepax@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/cs35l41.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/sound/soc/codecs/cs35l41.c b/sound/soc/codecs/cs35l41.c
index 3e68a07a3c8e0..71ab2a5d1c559 100644
--- a/sound/soc/codecs/cs35l41.c
+++ b/sound/soc/codecs/cs35l41.c
@@ -333,7 +333,7 @@ static const struct snd_kcontrol_new cs35l41_aud_controls[] = {
 	SOC_SINGLE("HW Noise Gate Enable", CS35L41_NG_CFG, 8, 63, 0),
 	SOC_SINGLE("HW Noise Gate Delay", CS35L41_NG_CFG, 4, 7, 0),
 	SOC_SINGLE("HW Noise Gate Threshold", CS35L41_NG_CFG, 0, 7, 0),
-	SOC_SINGLE("Aux Noise Gate CH1 Enable",
+	SOC_SINGLE("Aux Noise Gate CH1 Switch",
 		   CS35L41_MIXER_NGATE_CH1_CFG, 16, 1, 0),
 	SOC_SINGLE("Aux Noise Gate CH1 Entry Delay",
 		   CS35L41_MIXER_NGATE_CH1_CFG, 8, 15, 0),
@@ -341,15 +341,15 @@ static const struct snd_kcontrol_new cs35l41_aud_controls[] = {
 		   CS35L41_MIXER_NGATE_CH1_CFG, 0, 7, 0),
 	SOC_SINGLE("Aux Noise Gate CH2 Entry Delay",
 		   CS35L41_MIXER_NGATE_CH2_CFG, 8, 15, 0),
-	SOC_SINGLE("Aux Noise Gate CH2 Enable",
+	SOC_SINGLE("Aux Noise Gate CH2 Switch",
 		   CS35L41_MIXER_NGATE_CH2_CFG, 16, 1, 0),
 	SOC_SINGLE("Aux Noise Gate CH2 Threshold",
 		   CS35L41_MIXER_NGATE_CH2_CFG, 0, 7, 0),
-	SOC_SINGLE("SCLK Force", CS35L41_SP_FORMAT, CS35L41_SCLK_FRC_SHIFT, 1, 0),
-	SOC_SINGLE("LRCLK Force", CS35L41_SP_FORMAT, CS35L41_LRCLK_FRC_SHIFT, 1, 0),
-	SOC_SINGLE("Invert Class D", CS35L41_AMP_DIG_VOL_CTRL,
+	SOC_SINGLE("SCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_SCLK_FRC_SHIFT, 1, 0),
+	SOC_SINGLE("LRCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_LRCLK_FRC_SHIFT, 1, 0),
+	SOC_SINGLE("Invert Class D Switch", CS35L41_AMP_DIG_VOL_CTRL,
 		   CS35L41_AMP_INV_PCM_SHIFT, 1, 0),
-	SOC_SINGLE("Amp Gain ZC", CS35L41_AMP_GAIN_CTRL,
+	SOC_SINGLE("Amp Gain ZC Switch", CS35L41_AMP_GAIN_CTRL,
 		   CS35L41_AMP_GAIN_ZC_SHIFT, 1, 0),
 	WM_ADSP2_PRELOAD_SWITCH("DSP1", 1),
 	WM_ADSP_FW_CONTROL("DSP1", 0),
-- 
GitLab


From 1df793d479bef546569fc2e409ff8bb3f0fb8e99 Mon Sep 17 00:00:00 2001
From: Shuming Fan <shumingf@realtek.com>
Date: Tue, 21 Jun 2022 17:07:19 +0800
Subject: [PATCH 1154/1731] ASoC: rt711-sdca: fix kernel NULL pointer
 dereference when IO error

The initial settings will be written before the codec probe function.
But, the rt711->component doesn't be assigned yet.
If IO error happened during initial settings operations, it will cause the kernel panic.
This patch changed component->dev to slave->dev to fix this issue.

Signed-off-by: Shuming Fan <shumingf@realtek.com>
Link: https://lore.kernel.org/r/20220621090719.30558-1-shumingf@realtek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/rt711-sdca.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/soc/codecs/rt711-sdca.c b/sound/soc/codecs/rt711-sdca.c
index dfe3c9299ebde..5ad53bbc85284 100644
--- a/sound/soc/codecs/rt711-sdca.c
+++ b/sound/soc/codecs/rt711-sdca.c
@@ -34,7 +34,7 @@ static int rt711_sdca_index_write(struct rt711_sdca_priv *rt711,
 
 	ret = regmap_write(regmap, addr, value);
 	if (ret < 0)
-		dev_err(rt711->component->dev,
+		dev_err(&rt711->slave->dev,
 			"Failed to set private value: %06x <= %04x ret=%d\n",
 			addr, value, ret);
 
@@ -50,7 +50,7 @@ static int rt711_sdca_index_read(struct rt711_sdca_priv *rt711,
 
 	ret = regmap_read(regmap, addr, value);
 	if (ret < 0)
-		dev_err(rt711->component->dev,
+		dev_err(&rt711->slave->dev,
 			"Failed to get private value: %06x => %04x ret=%d\n",
 			addr, *value, ret);
 
-- 
GitLab


From 11d7a12f7f50baa5af9090b131c9b03af59503e7 Mon Sep 17 00:00:00 2001
From: Charles Keepax <ckeepax@opensource.cirrus.com>
Date: Thu, 23 Jun 2022 11:51:15 +0100
Subject: [PATCH 1155/1731] ASoC: dapm: Initialise kcontrol data for mux/demux
 controls

DAPM keeps a copy of the current value of mux/demux controls,
however this value is only initialised in the case of autodisable
controls. This leads to false notification events when first
modifying a DAPM kcontrol that has a non-zero default.

Autodisable controls are left as they are, since they already
initialise the value, and there would be more work required to
support autodisable muxes where the first option isn't disabled
and/or that isn't the default.

Technically this issue could affect mixer/switch elements as well,
although not on any of the devices I am currently running. There
is also a little more work to do to address the issue there due to
that side supporting stereo controls, so that has not been tackled
in this patch.

Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20220623105120.1981154-1-ckeepax@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/soc-dapm.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c
index 869c76506b669..a8e842e02cdc2 100644
--- a/sound/soc/soc-dapm.c
+++ b/sound/soc/soc-dapm.c
@@ -62,6 +62,8 @@ struct snd_soc_dapm_widget *
 snd_soc_dapm_new_control_unlocked(struct snd_soc_dapm_context *dapm,
 			 const struct snd_soc_dapm_widget *widget);
 
+static unsigned int soc_dapm_read(struct snd_soc_dapm_context *dapm, int reg);
+
 /* dapm power sequences - make this per codec in the future */
 static int dapm_up_seq[] = {
 	[snd_soc_dapm_pre] = 1,
@@ -442,6 +444,9 @@ static int dapm_kcontrol_data_alloc(struct snd_soc_dapm_widget *widget,
 
 			snd_soc_dapm_add_path(widget->dapm, data->widget,
 					      widget, NULL, NULL);
+		} else if (e->reg != SND_SOC_NOPM) {
+			data->value = soc_dapm_read(widget->dapm, e->reg) &
+				      (e->mask << e->shift_l);
 		}
 		break;
 	default:
-- 
GitLab


From 46b0d050c8c7df6dfb2c376aaa149bf2cfc5ca3e Mon Sep 17 00:00:00 2001
From: Charles Keepax <ckeepax@opensource.cirrus.com>
Date: Thu, 23 Jun 2022 11:51:16 +0100
Subject: [PATCH 1156/1731] ASoC: cs35l41: Add ASP TX3/4 source to register
 patch

The mixer controls for ASP TX3/4 are set to values that are not included
in their enumeration control. This will cause spurious event
notifications when the controls are first changed, as the register value
changes whilst the actual visible enumeration value does not. Use the
register patch to set them to a known value, zero, which equates to zero
fill, thereby avoiding the spurious notifications.

Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20220623105120.1981154-2-ckeepax@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/cs35l41-lib.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/sound/soc/codecs/cs35l41-lib.c b/sound/soc/codecs/cs35l41-lib.c
index 6d3070ea9e06d..198cfe54a46fc 100644
--- a/sound/soc/codecs/cs35l41-lib.c
+++ b/sound/soc/codecs/cs35l41-lib.c
@@ -37,8 +37,8 @@ static const struct reg_default cs35l41_reg[] = {
 	{ CS35L41_DAC_PCM1_SRC,			0x00000008 },
 	{ CS35L41_ASP_TX1_SRC,			0x00000018 },
 	{ CS35L41_ASP_TX2_SRC,			0x00000019 },
-	{ CS35L41_ASP_TX3_SRC,			0x00000020 },
-	{ CS35L41_ASP_TX4_SRC,			0x00000021 },
+	{ CS35L41_ASP_TX3_SRC,			0x00000000 },
+	{ CS35L41_ASP_TX4_SRC,			0x00000000 },
 	{ CS35L41_DSP1_RX1_SRC,			0x00000008 },
 	{ CS35L41_DSP1_RX2_SRC,			0x00000009 },
 	{ CS35L41_DSP1_RX3_SRC,			0x00000018 },
@@ -644,6 +644,8 @@ static const struct reg_sequence cs35l41_reva0_errata_patch[] = {
 	{ CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
 	{ CS35L41_PWR_CTRL2,		 0x00000000 },
 	{ CS35L41_AMP_GAIN_CTRL,	 0x00000000 },
+	{ CS35L41_ASP_TX3_SRC,		 0x00000000 },
+	{ CS35L41_ASP_TX4_SRC,		 0x00000000 },
 };
 
 static const struct reg_sequence cs35l41_revb0_errata_patch[] = {
@@ -655,6 +657,8 @@ static const struct reg_sequence cs35l41_revb0_errata_patch[] = {
 	{ CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
 	{ CS35L41_PWR_CTRL2,		 0x00000000 },
 	{ CS35L41_AMP_GAIN_CTRL,	 0x00000000 },
+	{ CS35L41_ASP_TX3_SRC,		 0x00000000 },
+	{ CS35L41_ASP_TX4_SRC,		 0x00000000 },
 };
 
 static const struct reg_sequence cs35l41_revb2_errata_patch[] = {
@@ -666,6 +670,8 @@ static const struct reg_sequence cs35l41_revb2_errata_patch[] = {
 	{ CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
 	{ CS35L41_PWR_CTRL2,		 0x00000000 },
 	{ CS35L41_AMP_GAIN_CTRL,	 0x00000000 },
+	{ CS35L41_ASP_TX3_SRC,		 0x00000000 },
+	{ CS35L41_ASP_TX4_SRC,		 0x00000000 },
 };
 
 static const struct reg_sequence cs35l41_fs_errata_patch[] = {
-- 
GitLab


From 7f103af4a10f375b9b346b4d0b730f6a66b8c451 Mon Sep 17 00:00:00 2001
From: Charles Keepax <ckeepax@opensource.cirrus.com>
Date: Thu, 23 Jun 2022 11:51:17 +0100
Subject: [PATCH 1157/1731] ASoC: cs47l15: Fix event generation for low power
 mux control

cs47l15_in1_adc_put always returns zero regardless of if the control
value was updated. This results in missing notifications to user-space
of the control change. Update the handling to return 1 when the value is
changed.

Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20220623105120.1981154-3-ckeepax@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/cs47l15.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/sound/soc/codecs/cs47l15.c b/sound/soc/codecs/cs47l15.c
index 391fd7da331fd..1c7d52bef8935 100644
--- a/sound/soc/codecs/cs47l15.c
+++ b/sound/soc/codecs/cs47l15.c
@@ -122,6 +122,9 @@ static int cs47l15_in1_adc_put(struct snd_kcontrol *kcontrol,
 		snd_soc_kcontrol_component(kcontrol);
 	struct cs47l15 *cs47l15 = snd_soc_component_get_drvdata(component);
 
+	if (!!ucontrol->value.integer.value[0] == cs47l15->in1_lp_mode)
+		return 0;
+
 	switch (ucontrol->value.integer.value[0]) {
 	case 0:
 		/* Set IN1 to normal mode */
@@ -150,7 +153,7 @@ static int cs47l15_in1_adc_put(struct snd_kcontrol *kcontrol,
 		break;
 	}
 
-	return 0;
+	return 1;
 }
 
 static const struct snd_kcontrol_new cs47l15_snd_controls[] = {
-- 
GitLab


From e3cabbef3db8269207a6b8808f510137669f8deb Mon Sep 17 00:00:00 2001
From: Charles Keepax <ckeepax@opensource.cirrus.com>
Date: Thu, 23 Jun 2022 11:51:18 +0100
Subject: [PATCH 1158/1731] ASoC: madera: Fix event generation for OUT1 demux

madera_out1_demux_put returns the value of
snd_soc_dapm_mux_update_power, which returns a 1 if a path was found for
the kcontrol. This is obviously different to the expected return a 1 if
the control was updated value. This results in spurious notifications to
user-space. Update the handling to only return a 1 when the value is
changed.

Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20220623105120.1981154-4-ckeepax@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/madera.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/sound/soc/codecs/madera.c b/sound/soc/codecs/madera.c
index 272041c6236a9..8095a87117cf8 100644
--- a/sound/soc/codecs/madera.c
+++ b/sound/soc/codecs/madera.c
@@ -618,7 +618,13 @@ int madera_out1_demux_put(struct snd_kcontrol *kcontrol,
 end:
 	snd_soc_dapm_mutex_unlock(dapm);
 
-	return snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL);
+	ret = snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL);
+	if (ret < 0) {
+		dev_err(madera->dev, "Failed to update demux power state: %d\n", ret);
+		return ret;
+	}
+
+	return change;
 }
 EXPORT_SYMBOL_GPL(madera_out1_demux_put);
 
-- 
GitLab


From 980555e95f7cabdc9c80a07107622b097ba23703 Mon Sep 17 00:00:00 2001
From: Charles Keepax <ckeepax@opensource.cirrus.com>
Date: Thu, 23 Jun 2022 11:51:19 +0100
Subject: [PATCH 1159/1731] ASoC: madera: Fix event generation for rate
 controls

madera_adsp_rate_put always returns zero regardless of if the control
value was updated. This results in missing notifications to user-space
of the control change. Update the handling to return 1 when the
value is changed.

Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20220623105120.1981154-5-ckeepax@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/madera.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/sound/soc/codecs/madera.c b/sound/soc/codecs/madera.c
index 8095a87117cf8..b9f19fbd29114 100644
--- a/sound/soc/codecs/madera.c
+++ b/sound/soc/codecs/madera.c
@@ -899,7 +899,7 @@ static int madera_adsp_rate_put(struct snd_kcontrol *kcontrol,
 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 	const int adsp_num = e->shift_l;
 	const unsigned int item = ucontrol->value.enumerated.item[0];
-	int ret;
+	int ret = 0;
 
 	if (item >= e->items)
 		return -EINVAL;
@@ -916,10 +916,10 @@ static int madera_adsp_rate_put(struct snd_kcontrol *kcontrol,
 			 "Cannot change '%s' while in use by active audio paths\n",
 			 kcontrol->id.name);
 		ret = -EBUSY;
-	} else {
+	} else if (priv->adsp_rate_cache[adsp_num] != e->values[item]) {
 		/* Volatile register so defer until the codec is powered up */
 		priv->adsp_rate_cache[adsp_num] = e->values[item];
-		ret = 0;
+		ret = 1;
 	}
 
 	mutex_unlock(&priv->rate_lock);
-- 
GitLab


From 7f058112873e86ca760f2d2b0e1ccc2ab111f418 Mon Sep 17 00:00:00 2001
From: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Date: Fri, 24 Jun 2022 16:35:11 +0930
Subject: [PATCH 1160/1731] ARM: dts: aspeed: nuvia: rename vendor nuvia to
 qcom

Nuvia has been acquired by Qualcomm and the vendor name 'nuvia' will
not be used anymore so rename aspeed-bmc-nuvia-dc-scm.dts to
aspeed-bmc-qcom-dc-scm-v1.dts and change 'nuvia' to 'qcom' as its vendor
name in the file.

Fixes: 7b46aa7c008d ("ARM: dts: aspeed: Add Nuvia DC-SCM BMC")
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220523175640.60155-1-quic_jaehyoo@quicinc.com
Link: https://lore.kernel.org/r/20220624070511.4070659-1-joel@jms.id.au'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/boot/dts/Makefile                                    | 2 +-
 ...eed-bmc-nuvia-dc-scm.dts => aspeed-bmc-qcom-dc-scm-v1.dts} | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)
 rename arch/arm/boot/dts/{aspeed-bmc-nuvia-dc-scm.dts => aspeed-bmc-qcom-dc-scm-v1.dts} (97%)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 184899808ee73..5112f493f4946 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1586,7 +1586,6 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
 	aspeed-bmc-lenovo-hr630.dtb \
 	aspeed-bmc-lenovo-hr855xg2.dtb \
 	aspeed-bmc-microsoft-olympus.dtb \
-	aspeed-bmc-nuvia-dc-scm.dtb \
 	aspeed-bmc-opp-lanyang.dtb \
 	aspeed-bmc-opp-mihawk.dtb \
 	aspeed-bmc-opp-mowgli.dtb \
@@ -1599,6 +1598,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
 	aspeed-bmc-opp-witherspoon.dtb \
 	aspeed-bmc-opp-zaius.dtb \
 	aspeed-bmc-portwell-neptune.dtb \
+	aspeed-bmc-qcom-dc-scm-v1.dtb \
 	aspeed-bmc-quanta-q71l.dtb \
 	aspeed-bmc-quanta-s6q.dtb \
 	aspeed-bmc-supermicro-x11spi.dtb \
diff --git a/arch/arm/boot/dts/aspeed-bmc-nuvia-dc-scm.dts b/arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts
similarity index 97%
rename from arch/arm/boot/dts/aspeed-bmc-nuvia-dc-scm.dts
rename to arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts
index f4a97cfb0f238..259ef3f54c5cc 100644
--- a/arch/arm/boot/dts/aspeed-bmc-nuvia-dc-scm.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts
@@ -6,8 +6,8 @@
 #include "aspeed-g6.dtsi"
 
 / {
-	model = "Nuvia DC-SCM BMC";
-	compatible = "nuvia,dc-scm-bmc", "aspeed,ast2600";
+	model = "Qualcomm DC-SCM V1 BMC";
+	compatible = "qcom,dc-scm-v1-bmc", "aspeed,ast2600";
 
 	aliases {
 		serial4 = &uart5;
-- 
GitLab


From de9b3d9616078f1d1d0d51b01cdafa101733f935 Mon Sep 17 00:00:00 2001
From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Date: Fri, 11 Mar 2022 00:19:34 +0200
Subject: [PATCH 1161/1731] arm64: dts: qcom: sm8450: fix interconnects
 property of UFS node

All interconnect device tree nodes on sm8450 are 2-cells, however in
UFS node they are handled as 1-cells, fix it.

Fixes: aa2d0bf04a3c ("arm64: dts: qcom: sm8450: add interconnect nodes")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220310221934.1560729-1-vladimir.zapolskiy@linaro.org
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 7d08fad763717..b2accf9960948 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -3037,8 +3037,8 @@
 
 			iommus = <&apps_smmu 0xe0 0x0>;
 
-			interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
-					<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
+			interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
+					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
 			interconnect-names = "ufs-ddr", "cpu-ufs";
 			clock-names =
 				"core_clk",
-- 
GitLab


From 935336c191040809bf5739654ea337c13fe8f9af Mon Sep 17 00:00:00 2001
From: Jakub Sitnicki <jakub@cloudflare.com>
Date: Thu, 23 Jun 2022 11:12:31 +0200
Subject: [PATCH 1162/1731] selftests/bpf: Test sockmap update when socket has
 ULP

Cover the scenario when we cannot insert a socket into the sockmap, because
it has it is using ULP. Failed insert should not have any effect on the ULP
state. This is a regression test.

Signed-off-by: Jakub Sitnicki <jakub@cloudflare.com>
Link: https://lore.kernel.org/r/20220623091231.417138-1-jakub@cloudflare.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 .../selftests/bpf/prog_tests/sockmap_ktls.c   | 84 +++++++++++++++++--
 1 file changed, 75 insertions(+), 9 deletions(-)

diff --git a/tools/testing/selftests/bpf/prog_tests/sockmap_ktls.c b/tools/testing/selftests/bpf/prog_tests/sockmap_ktls.c
index af293ea1542ce..e172d89e92e19 100644
--- a/tools/testing/selftests/bpf/prog_tests/sockmap_ktls.c
+++ b/tools/testing/selftests/bpf/prog_tests/sockmap_ktls.c
@@ -4,6 +4,7 @@
  * Tests for sockmap/sockhash holding kTLS sockets.
  */
 
+#include <netinet/tcp.h>
 #include "test_progs.h"
 
 #define MAX_TEST_NAME 80
@@ -92,9 +93,78 @@ close_srv:
 	close(srv);
 }
 
+static void test_sockmap_ktls_update_fails_when_sock_has_ulp(int family, int map)
+{
+	struct sockaddr_storage addr = {};
+	socklen_t len = sizeof(addr);
+	struct sockaddr_in6 *v6;
+	struct sockaddr_in *v4;
+	int err, s, zero = 0;
+
+	switch (family) {
+	case AF_INET:
+		v4 = (struct sockaddr_in *)&addr;
+		v4->sin_family = AF_INET;
+		break;
+	case AF_INET6:
+		v6 = (struct sockaddr_in6 *)&addr;
+		v6->sin6_family = AF_INET6;
+		break;
+	default:
+		PRINT_FAIL("unsupported socket family %d", family);
+		return;
+	}
+
+	s = socket(family, SOCK_STREAM, 0);
+	if (!ASSERT_GE(s, 0, "socket"))
+		return;
+
+	err = bind(s, (struct sockaddr *)&addr, len);
+	if (!ASSERT_OK(err, "bind"))
+		goto close;
+
+	err = getsockname(s, (struct sockaddr *)&addr, &len);
+	if (!ASSERT_OK(err, "getsockname"))
+		goto close;
+
+	err = connect(s, (struct sockaddr *)&addr, len);
+	if (!ASSERT_OK(err, "connect"))
+		goto close;
+
+	/* save sk->sk_prot and set it to tls_prots */
+	err = setsockopt(s, IPPROTO_TCP, TCP_ULP, "tls", strlen("tls"));
+	if (!ASSERT_OK(err, "setsockopt(TCP_ULP)"))
+		goto close;
+
+	/* sockmap update should not affect saved sk_prot */
+	err = bpf_map_update_elem(map, &zero, &s, BPF_ANY);
+	if (!ASSERT_ERR(err, "sockmap update elem"))
+		goto close;
+
+	/* call sk->sk_prot->setsockopt to dispatch to saved sk_prot */
+	err = setsockopt(s, IPPROTO_TCP, TCP_NODELAY, &zero, sizeof(zero));
+	ASSERT_OK(err, "setsockopt(TCP_NODELAY)");
+
+close:
+	close(s);
+}
+
+static const char *fmt_test_name(const char *subtest_name, int family,
+				 enum bpf_map_type map_type)
+{
+	const char *map_type_str = BPF_MAP_TYPE_SOCKMAP ? "SOCKMAP" : "SOCKHASH";
+	const char *family_str = AF_INET ? "IPv4" : "IPv6";
+	static char test_name[MAX_TEST_NAME];
+
+	snprintf(test_name, MAX_TEST_NAME,
+		 "sockmap_ktls %s %s %s",
+		 subtest_name, family_str, map_type_str);
+
+	return test_name;
+}
+
 static void run_tests(int family, enum bpf_map_type map_type)
 {
-	char test_name[MAX_TEST_NAME];
 	int map;
 
 	map = bpf_map_create(map_type, NULL, sizeof(int), sizeof(int), 1, NULL);
@@ -103,14 +173,10 @@ static void run_tests(int family, enum bpf_map_type map_type)
 		return;
 	}
 
-	snprintf(test_name, MAX_TEST_NAME,
-		 "sockmap_ktls disconnect_after_delete %s %s",
-		 family == AF_INET ? "IPv4" : "IPv6",
-		 map_type == BPF_MAP_TYPE_SOCKMAP ? "SOCKMAP" : "SOCKHASH");
-	if (!test__start_subtest(test_name))
-		return;
-
-	test_sockmap_ktls_disconnect_after_delete(family, map);
+	if (test__start_subtest(fmt_test_name("disconnect_after_delete", family, map_type)))
+		test_sockmap_ktls_disconnect_after_delete(family, map);
+	if (test__start_subtest(fmt_test_name("update_fails_when_sock_has_ulp", family, map_type)))
+		test_sockmap_ktls_update_fails_when_sock_has_ulp(family, map);
 
 	close(map);
 }
-- 
GitLab


From af3a6d1018f02c6dc8388f1f3785a559c7ab5961 Mon Sep 17 00:00:00 2001
From: Paulo Alcantara <pc@cjr.nz>
Date: Fri, 24 Jun 2022 15:01:43 -0300
Subject: [PATCH 1163/1731] cifs: update cifs_ses::ip_addr after failover

cifs_ses::ip_addr wasn't being updated in cifs_session_setup() when
reconnecting SMB sessions thus returning wrong value in
/proc/fs/cifs/DebugData.

Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Cc: stable@kernel.org
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/connect.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
index 8d56325915d0f..fa29c9aae24bc 100644
--- a/fs/cifs/connect.c
+++ b/fs/cifs/connect.c
@@ -4025,10 +4025,16 @@ cifs_setup_session(const unsigned int xid, struct cifs_ses *ses,
 		   struct nls_table *nls_info)
 {
 	int rc = -ENOSYS;
+	struct sockaddr_in6 *addr6 = (struct sockaddr_in6 *)&server->dstaddr;
+	struct sockaddr_in *addr = (struct sockaddr_in *)&server->dstaddr;
 	bool is_binding = false;
 
-
 	spin_lock(&cifs_tcp_ses_lock);
+	if (server->dstaddr.ss_family == AF_INET6)
+		scnprintf(ses->ip_addr, sizeof(ses->ip_addr), "%pI6", &addr6->sin6_addr);
+	else
+		scnprintf(ses->ip_addr, sizeof(ses->ip_addr), "%pI4", &addr->sin_addr);
+
 	if (ses->ses_status != SES_GOOD &&
 	    ses->ses_status != SES_NEW &&
 	    ses->ses_status != SES_NEED_RECON) {
-- 
GitLab


From ef9102004a87cb3f8b26e000a095a261fc0467d3 Mon Sep 17 00:00:00 2001
From: Chris Ye <chris.ye@intel.com>
Date: Tue, 31 May 2022 17:09:54 -0700
Subject: [PATCH 1164/1731] nvdimm: Fix badblocks clear off-by-one error

nvdimm_clear_badblocks_region() validates badblock clearing requests
against the span of the region, however it compares the inclusive
badblock request range to the exclusive region range. Fix up the
off-by-one error.

Fixes: 23f498448362 ("libnvdimm: rework region badblocks clearing")
Cc: <stable@vger.kernel.org>
Signed-off-by: Chris Ye <chris.ye@intel.com>
Reviewed-by: Vishal Verma <vishal.l.verma@intel.com>
Link: https://lore.kernel.org/r/165404219489.2445897.9792886413715690399.stgit@dwillia2-xfh
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
 drivers/nvdimm/bus.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/nvdimm/bus.c b/drivers/nvdimm/bus.c
index a4fc17db707c9..b38d0355b0ac3 100644
--- a/drivers/nvdimm/bus.c
+++ b/drivers/nvdimm/bus.c
@@ -176,8 +176,8 @@ static int nvdimm_clear_badblocks_region(struct device *dev, void *data)
 	ndr_end = nd_region->ndr_start + nd_region->ndr_size - 1;
 
 	/* make sure we are in the region */
-	if (ctx->phys < nd_region->ndr_start
-			|| (ctx->phys + ctx->cleared) > ndr_end)
+	if (ctx->phys < nd_region->ndr_start ||
+	    (ctx->phys + ctx->cleared - 1) > ndr_end)
 		return 0;
 
 	sector = (ctx->phys - nd_region->ndr_start) / 512;
-- 
GitLab


From 2990f223ffa7bb25422956b9f79f9176a5b38346 Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Tue, 21 Jun 2022 09:25:44 +0400
Subject: [PATCH 1165/1731] RDMA/cm: Fix memory leak in ib_cm_insert_listen

cm_alloc_id_priv() allocates resource for the cm_id_priv. When
cm_init_listen() fails it doesn't free it, leading to memory leak.

Add the missing error unwind.

Fixes: 98f67156a80f ("RDMA/cm: Simplify establishing a listen cm_id")
Link: https://lore.kernel.org/r/20220621052546.4821-1-linmq006@gmail.com
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
---
 drivers/infiniband/core/cm.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/infiniband/core/cm.c b/drivers/infiniband/core/cm.c
index 1c107d6d03b99..b985e0d9bc05e 100644
--- a/drivers/infiniband/core/cm.c
+++ b/drivers/infiniband/core/cm.c
@@ -1252,8 +1252,10 @@ struct ib_cm_id *ib_cm_insert_listen(struct ib_device *device,
 		return ERR_CAST(cm_id_priv);
 
 	err = cm_init_listen(cm_id_priv, service_id, 0);
-	if (err)
+	if (err) {
+		ib_destroy_cm_id(&cm_id_priv->id);
 		return ERR_PTR(err);
+	}
 
 	spin_lock_irq(&cm_id_priv->lock);
 	listen_id_priv = cm_insert_listen(cm_id_priv, cm_handler);
-- 
GitLab


From 179a93f74b29d0f37871d7afe826292cda90f113 Mon Sep 17 00:00:00 2001
From: "Masami Hiramatsu (Google)" <mhiramat@kernel.org>
Date: Fri, 24 Jun 2022 07:31:35 +0900
Subject: [PATCH 1166/1731] fprobe, samples: Add module parameter descriptions

Add module parameter descriptions for the fprobe_example module.

Signed-off-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
Signed-off-by: Andrii Nakryiko <andrii@kernel.org>
Link: https://lore.kernel.org/bpf/165602349520.56016.1314423560740428008.stgit@devnote2
---
 samples/fprobe/fprobe_example.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/samples/fprobe/fprobe_example.c b/samples/fprobe/fprobe_example.c
index 01ee6c8c83829..18b1e5c4b4315 100644
--- a/samples/fprobe/fprobe_example.c
+++ b/samples/fprobe/fprobe_example.c
@@ -25,12 +25,19 @@ static unsigned long nhit;
 
 static char symbol[MAX_SYMBOL_LEN] = "kernel_clone";
 module_param_string(symbol, symbol, sizeof(symbol), 0644);
+MODULE_PARM_DESC(symbol, "Probed symbol(s), given by comma separated symbols or a wildcard pattern.");
+
 static char nosymbol[MAX_SYMBOL_LEN] = "";
 module_param_string(nosymbol, nosymbol, sizeof(nosymbol), 0644);
+MODULE_PARM_DESC(nosymbol, "Not-probed symbols, given by a wildcard pattern.");
+
 static bool stackdump = true;
 module_param(stackdump, bool, 0644);
+MODULE_PARM_DESC(stackdump, "Enable stackdump.");
+
 static bool use_trace = false;
 module_param(use_trace, bool, 0644);
+MODULE_PARM_DESC(use_trace, "Use trace_printk instead of printk. This is only for debugging.");
 
 static void show_backtrace(void)
 {
-- 
GitLab


From 6f0012e35160cd08a53e46e3b3bbf724b92dfe68 Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Thu, 23 Jun 2022 05:04:36 +0000
Subject: [PATCH 1167/1731] tcp: add a missing nf_reset_ct() in 3WHS handling

When the third packet of 3WHS connection establishment
contains payload, it is added into socket receive queue
without the XFRM check and the drop of connection tracking
context.

This means that if the data is left unread in the socket
receive queue, conntrack module can not be unloaded.

As most applications usually reads the incoming data
immediately after accept(), bug has been hiding for
quite a long time.

Commit 68822bdf76f1 ("net: generalize skb freeing
deferral to per-cpu lists") exposed this bug because
even if the application reads this data, the skb
with nfct state could stay in a per-cpu cache for
an arbitrary time, if said cpu no longer process RX softirqs.

Many thanks to Ilya Maximets for reporting this issue,
and for testing various patches:
https://lore.kernel.org/netdev/20220619003919.394622-1-i.maximets@ovn.org/

Note that I also added a missing xfrm4_policy_check() call,
although this is probably not a big issue, as the SYN
packet should have been dropped earlier.

Fixes: b59c270104f0 ("[NETFILTER]: Keep conntrack reference until IPsec policy checks are done")
Reported-by: Ilya Maximets <i.maximets@ovn.org>
Signed-off-by: Eric Dumazet <edumazet@google.com>
Cc: Florian Westphal <fw@strlen.de>
Cc: Pablo Neira Ayuso <pablo@netfilter.org>
Cc: Steffen Klassert <steffen.klassert@secunet.com>
Tested-by: Ilya Maximets <i.maximets@ovn.org>
Reviewed-by: Ilya Maximets <i.maximets@ovn.org>
Link: https://lore.kernel.org/r/20220623050436.1290307-1-edumazet@google.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/ipv4/tcp_ipv4.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/net/ipv4/tcp_ipv4.c b/net/ipv4/tcp_ipv4.c
index fe8f23b95d32c..da5a3c44c4fb7 100644
--- a/net/ipv4/tcp_ipv4.c
+++ b/net/ipv4/tcp_ipv4.c
@@ -1964,7 +1964,10 @@ process:
 		struct sock *nsk;
 
 		sk = req->rsk_listener;
-		drop_reason = tcp_inbound_md5_hash(sk, skb,
+		if (!xfrm4_policy_check(sk, XFRM_POLICY_IN, skb))
+			drop_reason = SKB_DROP_REASON_XFRM_POLICY;
+		else
+			drop_reason = tcp_inbound_md5_hash(sk, skb,
 						   &iph->saddr, &iph->daddr,
 						   AF_INET, dif, sdif);
 		if (unlikely(drop_reason)) {
@@ -2016,6 +2019,7 @@ process:
 			}
 			goto discard_and_relse;
 		}
+		nf_reset_ct(skb);
 		if (nsk == sk) {
 			reqsk_put(req);
 			tcp_v4_restore_cb(skb);
-- 
GitLab


From 3b9bc84d311104906d2b4995a9a02d7b7ddab2db Mon Sep 17 00:00:00 2001
From: Jakub Kicinski <kuba@kernel.org>
Date: Wed, 22 Jun 2022 21:20:39 -0700
Subject: [PATCH 1168/1731] net: tun: unlink NAPI from device on destruction

Syzbot found a race between tun file and device destruction.
NAPIs live in struct tun_file which can get destroyed before
the netdev so we have to del them explicitly. The current
code is missing deleting the NAPI if the queue was detached
first.

Fixes: 943170998b20 ("tun: enable NAPI for TUN/TAP driver")
Reported-by: syzbot+b75c138e9286ac742647@syzkaller.appspotmail.com
Link: https://lore.kernel.org/r/20220623042039.2274708-1-kuba@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/tun.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/tun.c b/drivers/net/tun.c
index 87a635aac0084..7fd0288c37898 100644
--- a/drivers/net/tun.c
+++ b/drivers/net/tun.c
@@ -727,6 +727,7 @@ static void tun_detach_all(struct net_device *dev)
 		sock_put(&tfile->sk);
 	}
 	list_for_each_entry_safe(tfile, tmp, &tun->disabled, next) {
+		tun_napi_del(tfile);
 		tun_enable_queue(tfile);
 		tun_queue_purge(tfile);
 		xdp_rxq_info_unreg(&tfile->xdp_rxq);
-- 
GitLab


From c96614eeab663646f57f67aa591e015abd8bd0ba Mon Sep 17 00:00:00 2001
From: Enguerrand de Ribaucourt <enguerrand.de-ribaucourt@savoirfairelinux.com>
Date: Thu, 23 Jun 2022 15:46:44 +0200
Subject: [PATCH 1169/1731] net: dp83822: disable false carrier interrupt

When unplugging an Ethernet cable, false carrier events were produced by
the PHY at a very high rate. Once the false carrier counter full, an
interrupt was triggered every few clock cycles until the cable was
replugged. This resulted in approximately 10k/s interrupts.

Since the false carrier counter (FCSCR) is never used, we can safely
disable this interrupt.

In addition to improving performance, this also solved MDIO read
timeouts I was randomly encountering with an i.MX8 fec MAC because of
the interrupt flood. The interrupt count and MDIO timeout fix were
tested on a v5.4.110 kernel.

Fixes: 87461f7a58ab ("net: phy: DP83822 initial driver submission")
Signed-off-by: Enguerrand de Ribaucourt <enguerrand.de-ribaucourt@savoirfairelinux.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/phy/dp83822.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c
index e6ad3a494d32c..95ef507053a66 100644
--- a/drivers/net/phy/dp83822.c
+++ b/drivers/net/phy/dp83822.c
@@ -230,7 +230,6 @@ static int dp83822_config_intr(struct phy_device *phydev)
 			return misr_status;
 
 		misr_status |= (DP83822_RX_ERR_HF_INT_EN |
-				DP83822_FALSE_CARRIER_HF_INT_EN |
 				DP83822_LINK_STAT_INT_EN |
 				DP83822_ENERGY_DET_INT_EN |
 				DP83822_LINK_QUAL_INT_EN);
-- 
GitLab


From 0e597e2affb90d6ea48df6890d882924acf71e19 Mon Sep 17 00:00:00 2001
From: Enguerrand de Ribaucourt <enguerrand.de-ribaucourt@savoirfairelinux.com>
Date: Thu, 23 Jun 2022 15:46:45 +0200
Subject: [PATCH 1170/1731] net: dp83822: disable rx error interrupt

Some RX errors, notably when disconnecting the cable, increase the RCSR
register. Once half full (0x7fff), an interrupt flood is generated. I
measured ~3k/s interrupts even after the RX errors transfer was
stopped.

Since we don't read and clear the RCSR register, we should disable this
interrupt.

Fixes: 87461f7a58ab ("net: phy: DP83822 initial driver submission")
Signed-off-by: Enguerrand de Ribaucourt <enguerrand.de-ribaucourt@savoirfairelinux.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/phy/dp83822.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c
index 95ef507053a66..8549e0e356c9b 100644
--- a/drivers/net/phy/dp83822.c
+++ b/drivers/net/phy/dp83822.c
@@ -229,8 +229,7 @@ static int dp83822_config_intr(struct phy_device *phydev)
 		if (misr_status < 0)
 			return misr_status;
 
-		misr_status |= (DP83822_RX_ERR_HF_INT_EN |
-				DP83822_LINK_STAT_INT_EN |
+		misr_status |= (DP83822_LINK_STAT_INT_EN |
 				DP83822_ENERGY_DET_INT_EN |
 				DP83822_LINK_QUAL_INT_EN);
 
-- 
GitLab


From 3b89b511ea0c705cc418440e2abf9d692a556d84 Mon Sep 17 00:00:00 2001
From: Dan Carpenter <dan.carpenter@oracle.com>
Date: Thu, 23 Jun 2022 16:32:32 +0300
Subject: [PATCH 1171/1731] net: fix IFF_TX_SKB_NO_LINEAR definition

The "1<<31" shift has a sign extension bug so IFF_TX_SKB_NO_LINEAR is
0xffffffff80000000 instead of 0x0000000080000000.

Fixes: c2ff53d8049f ("net: Add priv_flags for allow tx skb without linear")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Link: https://lore.kernel.org/r/YrRrcGttfEVnf85Q@kili
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 include/linux/netdevice.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index f615a66c89e98..2563d30736e9a 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -1671,7 +1671,7 @@ enum netdev_priv_flags {
 	IFF_FAILOVER_SLAVE		= 1<<28,
 	IFF_L3MDEV_RX_HANDLER		= 1<<29,
 	IFF_LIVE_RENAME_OK		= 1<<30,
-	IFF_TX_SKB_NO_LINEAR		= 1<<31,
+	IFF_TX_SKB_NO_LINEAR		= BIT_ULL(31),
 	IFF_CHANGE_PROTO_DOWN		= BIT_ULL(32),
 };
 
-- 
GitLab


From 501dcbe495c0484a8f7954f1b24d2002dc6cb2d2 Mon Sep 17 00:00:00 2001
From: Huacai Chen <chenhuacai@loongson.cn>
Date: Wed, 22 Jun 2022 21:56:16 +0800
Subject: [PATCH 1172/1731] LoongArch: Fix the !THP build

Fix the !THP build by making pmd_pfn() available in all configurations.
Because pmd_pfn() is used in mm/page_vma_mapped.c whether or not THP is
configured.

Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 arch/loongarch/include/asm/pgtable.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/loongarch/include/asm/pgtable.h b/arch/loongarch/include/asm/pgtable.h
index 5dc84d8f18d60..d9e86cfa53e22 100644
--- a/arch/loongarch/include/asm/pgtable.h
+++ b/arch/loongarch/include/asm/pgtable.h
@@ -426,6 +426,11 @@ static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
 
 #define kern_addr_valid(addr)	(1)
 
+static inline unsigned long pmd_pfn(pmd_t pmd)
+{
+	return (pmd_val(pmd) & _PFN_MASK) >> _PFN_SHIFT;
+}
+
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 
 /* We don't have hardware dirty/accessed bits, generic_pmdp_establish is fine.*/
@@ -497,11 +502,6 @@ static inline pmd_t pmd_mkyoung(pmd_t pmd)
 	return pmd;
 }
 
-static inline unsigned long pmd_pfn(pmd_t pmd)
-{
-	return (pmd_val(pmd) & _PFN_MASK) >> _PFN_SHIFT;
-}
-
 static inline struct page *pmd_page(pmd_t pmd)
 {
 	if (pmd_trans_huge(pmd))
-- 
GitLab


From 92264f2dae7324f3189d22c0a0f0cb4e5d30d617 Mon Sep 17 00:00:00 2001
From: Huacai Chen <chenhuacai@loongson.cn>
Date: Sat, 25 Jun 2022 16:55:41 +0800
Subject: [PATCH 1173/1731] LoongArch: Fix the _stext symbol address

_stext means the start of .text section (see __is_kernel_text()), but we
put its definition in .ref.text by mistake. Fix it by defining it in the
vmlinux.lds.S.

Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 arch/loongarch/kernel/head.S        | 2 --
 arch/loongarch/kernel/vmlinux.lds.S | 1 +
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/loongarch/kernel/head.S b/arch/loongarch/kernel/head.S
index e596dfcd924b3..d01e62dd414f2 100644
--- a/arch/loongarch/kernel/head.S
+++ b/arch/loongarch/kernel/head.S
@@ -14,8 +14,6 @@
 
 	__REF
 
-SYM_ENTRY(_stext, SYM_L_GLOBAL, SYM_A_NONE)
-
 SYM_CODE_START(kernel_entry)			# kernel entry point
 
 	/* Config direct window and set PG */
diff --git a/arch/loongarch/kernel/vmlinux.lds.S b/arch/loongarch/kernel/vmlinux.lds.S
index 78311a6101a3e..69c76f26c1c57 100644
--- a/arch/loongarch/kernel/vmlinux.lds.S
+++ b/arch/loongarch/kernel/vmlinux.lds.S
@@ -37,6 +37,7 @@ SECTIONS
 	HEAD_TEXT_SECTION
 
 	. = ALIGN(PECOFF_SEGMENT_ALIGN);
+	_stext = .;
 	.text : {
 		TEXT_TEXT
 		SCHED_TEXT
-- 
GitLab


From bab1c299f3945ffe7934c05f3c50377ca4b291b4 Mon Sep 17 00:00:00 2001
From: Huacai Chen <chenhuacai@loongson.cn>
Date: Thu, 23 Jun 2022 09:55:42 +0800
Subject: [PATCH 1174/1731] LoongArch: Fix sleeping in atomic context in
 setup_tlb_handler()

Since setup_tlb_handler() is executed in atomic context, we should use
GFP_ATOMIC instead of GFP_KERNEL to alloc pages. Otherwise we will get
a "sleeping in atomic context" error:

[    0.013118] BUG: sleeping function called from invalid context at mm/page_alloc.c:5158
[    0.013126] in_atomic(): 1, irqs_disabled(): 1, non_block: 0, pid: 0, name: swapper/1
[    0.013131] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 5.19-rc3+ #1008 1a223086d14d07967cc427f15d52139422271360
[    0.013136] Hardware name: Loongson Loongson-3A5000-7A1000-1w-V0.1-CRB/Loongson-LS3A5000-7A1000-1w-EVB-V1.21, BIOS Loongson-UDK2018-V2.0.04082-beta7 04/27
[    0.013140] Stack : 90000000015fc990 9000000100493c18 9000000000df3370 9000000100490000
[    0.013151]         9000000100493b50 0000000000000000 9000000100493b58 9000000001417ef0
[    0.013160]         900000000199e54e 0000000000000040 9000000100493c18 90000000015f7a98
[    0.013168]         ffffffffffffffff 6de72f8b42179d1e 9000000100403b80 90000000015f7890
[    0.013176]         0000000000000001 00000000fffff175 9000000000eb9860 9000000001530b4b
[    0.013184]         9000000000e99e60 0000000000000013 0000000006ecc000 0000000000000001
[    0.013193]         90000000015f7a98 9000000001417ef0 0000000000000004 0000000000000000
[    0.013201]         0000000000000cc0 0000000000000000 0000000000000001 90000000015fc990
[    0.013209]         9000000000217e74 9000000001603b6b 9000000000208640 0000000000000000
[    0.013217]         00000000000000b0 0000000000000004 0000000000000000 0000000000070000
[    0.013225]         ...
[    0.013229] Call Trace:
[    0.013230] [<9000000000208640>] show_stack+0x4c/0x14c
[    0.013240] [<9000000000df3370>] dump_stack_lvl+0x70/0xac
[    0.013246] [<9000000000270c8c>] ___might_sleep+0x104/0x124
[    0.013253] [<9000000000477e84>] __alloc_pages+0x240/0x464
[    0.013260] [<9000000000214214>] setup_tlb_handler+0x104/0x1e8
[    0.013265] [<9000000000214324>] tlb_init+0x2c/0x3c
[    0.013270] [<9000000000208b74>] per_cpu_trap_init+0xec/0x108
[    0.013275] [<9000000000202850>] cpu_probe+0x400/0x8a4
[    0.013279] [<900000000020d160>] start_secondary+0x5c/0x3d4

Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 arch/loongarch/mm/tlb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/loongarch/mm/tlb.c b/arch/loongarch/mm/tlb.c
index e272f8ac57d16..6d050973241cf 100644
--- a/arch/loongarch/mm/tlb.c
+++ b/arch/loongarch/mm/tlb.c
@@ -281,7 +281,7 @@ void setup_tlb_handler(int cpu)
 		if (pcpu_handlers[cpu])
 			return;
 
-		page = alloc_pages_node(cpu_to_node(cpu), GFP_KERNEL, get_order(vec_sz));
+		page = alloc_pages_node(cpu_to_node(cpu), GFP_ATOMIC, get_order(vec_sz));
 		if (!page)
 			return;
 
-- 
GitLab


From 26808cebf14cdf1d835ae256188ece116d2ab377 Mon Sep 17 00:00:00 2001
From: Huacai Chen <chenhuacai@loongson.cn>
Date: Thu, 23 Jun 2022 16:11:54 +0800
Subject: [PATCH 1175/1731] LoongArch: Fix EENTRY/MERRENTRY setting in
 setup_tlb_handler()

setup_tlb_handler() is expected to set per-cpu exception handlers, but
it only set the TLBRENTRY successfully because of copy & paste errors,
so fix it.

Reviewed-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 arch/loongarch/mm/tlb.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/loongarch/mm/tlb.c b/arch/loongarch/mm/tlb.c
index 6d050973241cf..9818ce11546bc 100644
--- a/arch/loongarch/mm/tlb.c
+++ b/arch/loongarch/mm/tlb.c
@@ -286,10 +286,11 @@ void setup_tlb_handler(int cpu)
 			return;
 
 		addr = page_address(page);
-		pcpu_handlers[cpu] = virt_to_phys(addr);
+		pcpu_handlers[cpu] = (unsigned long)addr;
 		memcpy((void *)addr, (void *)eentry, vec_sz);
 		local_flush_icache_range((unsigned long)addr, (unsigned long)addr + vec_sz);
-		csr_write64(pcpu_handlers[cpu], LOONGARCH_CSR_TLBRENTRY);
+		csr_write64(pcpu_handlers[cpu], LOONGARCH_CSR_EENTRY);
+		csr_write64(pcpu_handlers[cpu], LOONGARCH_CSR_MERRENTRY);
 		csr_write64(pcpu_handlers[cpu] + 80*VECSIZE, LOONGARCH_CSR_TLBRENTRY);
 	}
 #endif
-- 
GitLab


From ad82eef3cebf8cd4f67e20b902e6d02e679e2ef1 Mon Sep 17 00:00:00 2001
From: Tiezhu Yang <yangtiezhu@loongson.cn>
Date: Sat, 18 Jun 2022 12:50:31 +0800
Subject: [PATCH 1176/1731] LoongArch: Fix wrong fpu version

According to the configuration information accessible by the CPUCFG
instruction in LoongArch Reference Manual [1], FP_ver is stored in
bit [5: 3] of CPUCFG2, the current code to get fpu version is wrong,
use CPUCFG2_FPVERS to fix it.

[1] https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html

Fixes: 628c3bb40e9a ("LoongArch: Add boot and setup routines")
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 arch/loongarch/kernel/cpu-probe.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-probe.c
index 6c87ea36b2573..529ab8f44ec6d 100644
--- a/arch/loongarch/kernel/cpu-probe.c
+++ b/arch/loongarch/kernel/cpu-probe.c
@@ -263,7 +263,7 @@ void cpu_probe(void)
 
 	c->cputype	= CPU_UNKNOWN;
 	c->processor_id = read_cpucfg(LOONGARCH_CPUCFG0);
-	c->fpu_vers	= (read_cpucfg(LOONGARCH_CPUCFG2) >> 3) & 0x3;
+	c->fpu_vers     = (read_cpucfg(LOONGARCH_CPUCFG2) & CPUCFG2_FPVERS) >> 3;
 
 	c->fpu_csr0	= FPU_CSR_RN;
 	c->fpu_mask	= FPU_CSR_RSVD;
-- 
GitLab


From ea18d434781105ce61ff3ef7f74c9e51812f0580 Mon Sep 17 00:00:00 2001
From: Tiezhu Yang <yangtiezhu@loongson.cn>
Date: Sat, 18 Jun 2022 16:39:11 +0800
Subject: [PATCH 1177/1731] LoongArch: Make compute_return_era() return void

compute_return_era() always returns 0, make it return void,
and then no need to check its return value for its callers.

Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 arch/loongarch/include/asm/branch.h | 3 +--
 arch/loongarch/kernel/traps.c       | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/loongarch/include/asm/branch.h b/arch/loongarch/include/asm/branch.h
index 3f33c89f35b48..9a133e4c068e2 100644
--- a/arch/loongarch/include/asm/branch.h
+++ b/arch/loongarch/include/asm/branch.h
@@ -12,10 +12,9 @@ static inline unsigned long exception_era(struct pt_regs *regs)
 	return regs->csr_era;
 }
 
-static inline int compute_return_era(struct pt_regs *regs)
+static inline void compute_return_era(struct pt_regs *regs)
 {
 	regs->csr_era += 4;
-	return 0;
 }
 
 #endif /* _ASM_BRANCH_H */
diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index e4060f84a2216..1bf58c65e2bf0 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -475,8 +475,7 @@ asmlinkage void noinstr do_ri(struct pt_regs *regs)
 
 	die_if_kernel("Reserved instruction in kernel code", regs);
 
-	if (unlikely(compute_return_era(regs) < 0))
-		goto out;
+	compute_return_era(regs);
 
 	if (unlikely(get_user(opcode, era) < 0)) {
 		status = SIGSEGV;
-- 
GitLab


From fbb564a557809466c171b95f8d593a0972450ff2 Mon Sep 17 00:00:00 2001
From: wuchi <wuchi.zero@gmail.com>
Date: Sun, 5 Jun 2022 22:58:35 +0800
Subject: [PATCH 1178/1731] lib/sbitmap: Fix invalid loop in
 __sbitmap_queue_get_batch()

1. Getting next index before continue branch.
2. Checking free bits when setting the target bits. Otherwise,
it may reuse the busying bits.

Signed-off-by: wuchi <wuchi.zero@gmail.com>
Reviewed-by: Martin Wilck <mwilck@suse.com>
Link: https://lore.kernel.org/r/20220605145835.26916-1-wuchi.zero@gmail.com
Fixes: 9672b0d43782 ("sbitmap: add __sbitmap_queue_get_batch()")
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 lib/sbitmap.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/lib/sbitmap.c b/lib/sbitmap.c
index ae4fd4de9ebe7..29eb0484215af 100644
--- a/lib/sbitmap.c
+++ b/lib/sbitmap.c
@@ -528,7 +528,7 @@ unsigned long __sbitmap_queue_get_batch(struct sbitmap_queue *sbq, int nr_tags,
 
 		sbitmap_deferred_clear(map);
 		if (map->word == (1UL << (map_depth - 1)) - 1)
-			continue;
+			goto next;
 
 		nr = find_first_zero_bit(&map->word, map_depth);
 		if (nr + nr_tags <= map_depth) {
@@ -539,6 +539,8 @@ unsigned long __sbitmap_queue_get_batch(struct sbitmap_queue *sbq, int nr_tags,
 			get_mask = ((1UL << map_tags) - 1) << nr;
 			do {
 				val = READ_ONCE(map->word);
+				if ((val & ~get_mask) != val)
+					goto next;
 				ret = atomic_long_cmpxchg(ptr, val, get_mask | val);
 			} while (ret != val);
 			get_mask = (get_mask & ~ret) >> nr;
@@ -549,6 +551,7 @@ unsigned long __sbitmap_queue_get_batch(struct sbitmap_queue *sbq, int nr_tags,
 				return get_mask;
 			}
 		}
+next:
 		/* Jump to next index. */
 		if (++index >= sb->map_nr)
 			index = 0;
-- 
GitLab


From 47bf59c4755930f616dd90c8c6a85f40a6d347ea Mon Sep 17 00:00:00 2001
From: Konrad Dybcio <konrad.dybcio@somainline.org>
Date: Sun, 1 May 2022 20:40:16 +0200
Subject: [PATCH 1179/1731] arm64: dts: qcom: msm8994: Fix CPU6/7 reg values

CPU6 and CPU7 were mistakengly pointing to CPU5 reg. Fix it.

Fixes: 02d8091bbca0 ("arm64: dts: qcom: msm8994: Add a proper CPU map")
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220501184016.64138-1-konrad.dybcio@somainline.org
---
 arch/arm64/boot/dts/qcom/msm8994.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
index 0318d42c57364..1ac2913b182cc 100644
--- a/arch/arm64/boot/dts/qcom/msm8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
@@ -100,7 +100,7 @@
 		CPU6: cpu@102 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a57";
-			reg = <0x0 0x101>;
+			reg = <0x0 0x102>;
 			enable-method = "psci";
 			next-level-cache = <&L2_1>;
 		};
@@ -108,7 +108,7 @@
 		CPU7: cpu@103 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a57";
-			reg = <0x0 0x101>;
+			reg = <0x0 0x103>;
 			enable-method = "psci";
 			next-level-cache = <&L2_1>;
 		};
-- 
GitLab


From fc8b0b9b630df6de7415f527fe27c0c441b5dc70 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Mon, 2 May 2022 22:26:04 +0300
Subject: [PATCH 1180/1731] arm64: dts: qcom: sm8450 add ITS device tree node

Add device tree node corresponding to the ITS part of GICv3.

Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220502192604.272686-1-dmitry.baryshkov@linaro.org
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index b2accf9960948..b87756bf1ce44 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -2853,6 +2853,16 @@
 			reg = <0x0 0x17100000 0x0 0x10000>,     /* GICD */
 			      <0x0 0x17180000 0x0 0x200000>;    /* GICR * 8 */
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			gic_its: msi-controller@17140000 {
+				compatible = "arm,gic-v3-its";
+				reg = <0x0 0x17140000 0x0 0x20000>;
+				msi-controller;
+				#msi-cells = <1>;
+			};
 		};
 
 		timer@17420000 {
-- 
GitLab


From 53632ba87d9f302a8d97a11ec2f4f4eec7bb75ea Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <masahiroy@kernel.org>
Date: Fri, 24 Jun 2022 04:11:47 +0900
Subject: [PATCH 1181/1731] kbuild: link vmlinux only once for
 CONFIG_TRIM_UNUSED_KSYMS (2nd attempt)

If CONFIG_TRIM_UNUSED_KSYMS is enabled and the kernel is built from
a pristine state, the vmlinux is linked twice.

Commit 3fdc7d3fe4c0 ("kbuild: link vmlinux only once for
CONFIG_TRIM_UNUSED_KSYMS") explains why this happens, but it did not fix
the issue at all.

Now I realized I had applied a wrong patch.

In v1 patch [1], the autoksyms_recursive target correctly recurses to
"$(MAKE) -f $(srctree)/Makefile autoksyms_recursive".

In v2 patch [2], I accidentally dropped the diff line, and it recurses to
"$(MAKE) -f $(srctree)/Makefile vmlinux".

Restore the code I intended in v1.

[1]: https://lore.kernel.org/linux-kbuild/1521045861-22418-8-git-send-email-yamada.masahiro@socionext.com/
[2]: https://lore.kernel.org/linux-kbuild/1521166725-24157-8-git-send-email-yamada.masahiro@socionext.com/

Fixes: 3fdc7d3fe4c0 ("kbuild: link vmlinux only once for CONFIG_TRIM_UNUSED_KSYMS")
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Tested-by: Sami Tolvanen <samitolvanen@google.com>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 513c1fbf7888b..a3ff166c50354 100644
--- a/Makefile
+++ b/Makefile
@@ -1141,7 +1141,7 @@ KBUILD_MODULES := 1
 
 autoksyms_recursive: descend modules.order
 	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/adjust_autoksyms.sh \
-	  "$(MAKE) -f $(srctree)/Makefile vmlinux"
+	  "$(MAKE) -f $(srctree)/Makefile autoksyms_recursive"
 endif
 
 autoksyms_h := $(if $(CONFIG_TRIM_UNUSED_KSYMS), include/generated/autoksyms.h)
-- 
GitLab


From ff139766764675b9df12bcbc8928a02149b7ba95 Mon Sep 17 00:00:00 2001
From: Sami Tolvanen <samitolvanen@google.com>
Date: Thu, 16 Jun 2022 19:57:59 +0000
Subject: [PATCH 1182/1731] kbuild: Ignore __this_module in gen_autoksyms.sh

Module object files can contain an undefined reference to __this_module,
which isn't resolved until we link the final .ko. The kernel doesn't
export this symbol, so ignore it in gen_autoksyms.sh.

Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
Tested-by: Steve Muckle <smuckle@google.com>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Tested-by: Ramji Jiyani <ramjiyani@google.com>
---
 scripts/gen_autoksyms.sh | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/scripts/gen_autoksyms.sh b/scripts/gen_autoksyms.sh
index faacf70621221..653fadbad302f 100755
--- a/scripts/gen_autoksyms.sh
+++ b/scripts/gen_autoksyms.sh
@@ -56,4 +56,7 @@ EOT
 # point addresses.
 sed -e 's/^\.//' |
 sort -u |
+# Ignore __this_module. It's not an exported symbol, and will be resolved
+# when the final .ko's are linked.
+grep -v '^__this_module$' |
 sed -e 's/\(.*\)/#define __KSYM_\1 1/' >> "$output_file"
-- 
GitLab


From d16c5c7c925658ea94689dfe4469441f7fd59f00 Mon Sep 17 00:00:00 2001
From: Jiang Jian <jiangjian@cdjrlc.com>
Date: Tue, 21 Jun 2022 14:38:23 +0800
Subject: [PATCH 1183/1731] parisc: align '*' in comment in math-emu code

Signed-off-by: Jiang Jian <jiangjian@cdjrlc.com>
Reviewed-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Helge Deller <deller@gmx.de>
---
 arch/parisc/math-emu/decode_exc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/parisc/math-emu/decode_exc.c b/arch/parisc/math-emu/decode_exc.c
index 494ca41df05d0..d41ddb3430b5b 100644
--- a/arch/parisc/math-emu/decode_exc.c
+++ b/arch/parisc/math-emu/decode_exc.c
@@ -102,7 +102,7 @@ decode_fpu(unsigned int Fpu_register[], unsigned int trap_counts[])
      * that happen.  Want to keep this overhead low, but still provide
      * some information to the customer.  All exits from this routine
      * need to restore Fpu_register[0]
-    */
+     */
 
     bflags=(Fpu_register[0] & 0xf8000000);
     Fpu_register[0] &= 0x07ffffff;
-- 
GitLab


From 067baa9a37b32b95fdeabccde4b0cb6a2cf95f96 Mon Sep 17 00:00:00 2001
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
Date: Sat, 25 Jun 2022 13:01:08 +0200
Subject: [PATCH 1184/1731] ksmbd: use vfs_llseek instead of dereferencing NULL

By not checking whether llseek is NULL, this might jump to NULL. Also,
it doesn't check FMODE_LSEEK. Fix this by using vfs_llseek(), which
always does the right thing.

Fixes: f44158485826 ("cifsd: add file operations")
Cc: stable@vger.kernel.org
Cc: linux-cifs@vger.kernel.org
Cc: Ronnie Sahlberg <lsahlber@redhat.com>
Cc: Hyunchul Lee <hyc.lee@gmail.com>
Cc: Sergey Senozhatsky <sergey.senozhatsky@gmail.com>
Reviewed-by: Namjae Jeon <linkinjeon@kernel.org>
Acked-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/ksmbd/vfs.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fs/ksmbd/vfs.c b/fs/ksmbd/vfs.c
index f194bf764f9f0..5d185564aef6b 100644
--- a/fs/ksmbd/vfs.c
+++ b/fs/ksmbd/vfs.c
@@ -1048,7 +1048,7 @@ int ksmbd_vfs_fqar_lseek(struct ksmbd_file *fp, loff_t start, loff_t length,
 	*out_count = 0;
 	end = start + length;
 	while (start < end && *out_count < in_count) {
-		extent_start = f->f_op->llseek(f, start, SEEK_DATA);
+		extent_start = vfs_llseek(f, start, SEEK_DATA);
 		if (extent_start < 0) {
 			if (extent_start != -ENXIO)
 				ret = (int)extent_start;
@@ -1058,7 +1058,7 @@ int ksmbd_vfs_fqar_lseek(struct ksmbd_file *fp, loff_t start, loff_t length,
 		if (extent_start >= end)
 			break;
 
-		extent_end = f->f_op->llseek(f, extent_start, SEEK_HOLE);
+		extent_end = vfs_llseek(f, extent_start, SEEK_HOLE);
 		if (extent_end < 0) {
 			if (extent_end != -ENXIO)
 				ret = (int)extent_end;
-- 
GitLab


From 3ba500dee327e0261e728edec8a4f2f563d2760c Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Tue, 31 May 2022 15:47:35 +0300
Subject: [PATCH 1185/1731] arm64: dts: qcom: sdm845: use dispcc AHB clock for
 mdss node

It was noticed that on sdm845 after an MDSS suspend/resume cycle the
driver can not read HW_REV registers properly (they will return 0
instead). Chaning the "iface" clock from <&gcc GCC_DISP_AHB_CLK> to
<&dispcc DISP_CC_MDSS_AHB_CLK> fixes the issue.

Fixes: 08c2a076d18f ("arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220531124735.1165582-1-dmitry.baryshkov@linaro.org
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 0692ae0e60a42..038538c8c6141 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -4244,7 +4244,7 @@
 
 			power-domains = <&dispcc MDSS_GDSC>;
 
-			clocks = <&gcc GCC_DISP_AHB_CLK>,
+			clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 				 <&dispcc DISP_CC_MDSS_MDP_CLK>;
 			clock-names = "iface", "core";
 
-- 
GitLab


From d640974d1c4ee510fcc8f05f0ddaaf9d17b47643 Mon Sep 17 00:00:00 2001
From: Konrad Dybcio <konrad.dybcio@somainline.org>
Date: Mon, 23 May 2022 23:03:04 +0200
Subject: [PATCH 1186/1731] MAINTAINERS: Add myself as a reviewer for Qualcomm
 ARM/64 support

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220523210304.19125-1-konrad.dybcio@somainline.org
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index a6d3bd9d2a8d0..524c1c434ed86 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2537,6 +2537,7 @@ W:	http://www.armlinux.org.uk/
 ARM/QUALCOMM SUPPORT
 M:	Andy Gross <agross@kernel.org>
 M:	Bjorn Andersson <bjorn.andersson@linaro.org>
+R:	Konrad Dybcio <konrad.dybcio@somainline.org>
 L:	linux-arm-msm@vger.kernel.org
 S:	Maintained
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git
-- 
GitLab


From e9ed22e6e5010997a2f922eef61ca797d0a2a246 Mon Sep 17 00:00:00 2001
From: John David Anglin <dave.anglin@bell.net>
Date: Sat, 18 Jun 2022 15:14:34 +0000
Subject: [PATCH 1187/1731] parisc: Fix flush_anon_page on PA8800/PA8900

Anonymous pages are allocated with the shared mappings colouring,
SHM_COLOUR. Since the alias boundary on machines with PA8800 and
PA8900 processors is unknown, flush_user_cache_page() might not
flush all mappings of a shared anonymous page. Flushing the whole
data cache flushes all mappings.

This won't fix all coherency issues with shared mappings but it
seems to work well in practice.  I haven't seen any random memory
faults in almost a month on a rp3440 running as a debian buildd
machine.

There is a small preformance hit.

Signed-off-by: John David Anglin <dave.anglin@bell.net>
Signed-off-by: Helge Deller <deller@gmx.de>
Cc: stable@vger.kernel.org   # v5.18+
---
 arch/parisc/kernel/cache.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index c8a11fcecf4c6..a9bc578e4c52e 100644
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -722,7 +722,10 @@ void flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned lon
 		return;
 
 	if (parisc_requires_coherency()) {
-		flush_user_cache_page(vma, vmaddr);
+		if (vma->vm_flags & VM_SHARED)
+			flush_data_cache();
+		else
+			flush_user_cache_page(vma, vmaddr);
 		return;
 	}
 
-- 
GitLab


From 0a1355db36718178becd2bfe728a023933d73123 Mon Sep 17 00:00:00 2001
From: Helge Deller <deller@gmx.de>
Date: Sun, 26 Jun 2022 11:50:43 +0200
Subject: [PATCH 1188/1731] parisc: Enable ARCH_HAS_STRICT_MODULE_RWX

Fix a boot crash on a c8000 machine as reported by Dave.  Basically it changes
patch_map() to return an alias mapping to the to-be-patched code in order to
prevent writing to write-protected memory.

Signed-off-by: Helge Deller <deller@gmx.de>
Suggested-by: John David Anglin <dave.anglin@bell.net>
Cc: stable@vger.kernel.org   # v5.2+
Link: https://lore.kernel.org/all/e8ec39e8-25f8-e6b4-b7ed-4cb23efc756e@bell.net/
---
 arch/parisc/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index 5f2448dc5a2b2..fa400055b2d50 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -10,6 +10,7 @@ config PARISC
 	select ARCH_WANT_FRAME_POINTERS
 	select ARCH_HAS_ELF_RANDOMIZE
 	select ARCH_HAS_STRICT_KERNEL_RWX
+	select ARCH_HAS_STRICT_MODULE_RWX
 	select ARCH_HAS_UBSAN_SANITIZE_ALL
 	select ARCH_HAS_PTE_SPECIAL
 	select ARCH_NO_SG_CHAIN
-- 
GitLab


From 342cb0d80613719c5e5ac30619e54b9a3fd83625 Mon Sep 17 00:00:00 2001
From: Adrian Hunter <adrian.hunter@intel.com>
Date: Mon, 20 Jun 2022 13:39:04 +0300
Subject: [PATCH 1189/1731] perf inject: Fix missing free in copy_kcore_dir()

Free string allocated by asprintf().

Fixes: d8fc08550929bb84 ("perf inject: Keep a copy of kcore_dir")
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Link: https://lore.kernel.org/r/20220620103904.7960-1-adrian.hunter@intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/builtin-inject.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/tools/perf/builtin-inject.c b/tools/perf/builtin-inject.c
index a75bf11585b5c..063f74f5b8db5 100644
--- a/tools/perf/builtin-inject.c
+++ b/tools/perf/builtin-inject.c
@@ -891,7 +891,9 @@ static int copy_kcore_dir(struct perf_inject *inject)
 	if (ret < 0)
 		return ret;
 	pr_debug("%s\n", cmd);
-	return system(cmd);
+	ret = system(cmd);
+	free(cmd);
+	return ret;
 }
 
 static int output_fd(struct perf_inject *inject)
-- 
GitLab


From 0fdd435cb4f873b5602913db4f2ba497a5443daf Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Sat, 13 Nov 2021 11:08:31 -0300
Subject: [PATCH 1190/1731] tools headers UAPI: Sync drm/i915_drm.h with the
 kernel sources

To pick up the changes in:

  ecf8eca51f33dbfd ("drm/i915/xehp: Add compute engine ABI")
  991b4de3275728fd ("drm/i915/uapi: Add kerneldoc for engine class enum")
  c94fde8f516610b0 ("drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES")
  1c671ad753dbbf5f ("drm/i915/doc: Link query items to their uapi structs")
  a2e5402691e23269 ("drm/i915/doc: Convert perf UAPI comments to kerneldoc")
  462ac1cdf4d7acf1 ("drm/i915/doc: Convert drm_i915_query_topology_info comment to kerneldoc")
  034d47b25b2ce627 ("drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB")
  78e1fb3112c0ac44 ("drm/i915/uapi: Add query for hwconfig blob")

That don't add any new ioctl, so no changes in tooling.

This silences this perf build warning:

  Warning: Kernel ABI header at 'tools/include/uapi/drm/i915_drm.h' differs from latest version at 'include/uapi/drm/i915_drm.h'
  diff -u tools/include/uapi/drm/i915_drm.h include/uapi/drm/i915_drm.h

Cc: John Harrison <John.C.Harrison@intel.com>
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://lore.kernel.org/lkml/YrDi4ALYjv9Mdocq@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/include/uapi/drm/i915_drm.h | 353 +++++++++++++++++++++++-------
 1 file changed, 272 insertions(+), 81 deletions(-)

diff --git a/tools/include/uapi/drm/i915_drm.h b/tools/include/uapi/drm/i915_drm.h
index 05c3642aaece4..a2def7b270097 100644
--- a/tools/include/uapi/drm/i915_drm.h
+++ b/tools/include/uapi/drm/i915_drm.h
@@ -154,25 +154,77 @@ enum i915_mocs_table_index {
 	I915_MOCS_CACHED,
 };
 
-/*
+/**
+ * enum drm_i915_gem_engine_class - uapi engine type enumeration
+ *
  * Different engines serve different roles, and there may be more than one
- * engine serving each role. enum drm_i915_gem_engine_class provides a
- * classification of the role of the engine, which may be used when requesting
- * operations to be performed on a certain subset of engines, or for providing
- * information about that group.
+ * engine serving each role.  This enum provides a classification of the role
+ * of the engine, which may be used when requesting operations to be performed
+ * on a certain subset of engines, or for providing information about that
+ * group.
  */
 enum drm_i915_gem_engine_class {
+	/**
+	 * @I915_ENGINE_CLASS_RENDER:
+	 *
+	 * Render engines support instructions used for 3D, Compute (GPGPU),
+	 * and programmable media workloads.  These instructions fetch data and
+	 * dispatch individual work items to threads that operate in parallel.
+	 * The threads run small programs (called "kernels" or "shaders") on
+	 * the GPU's execution units (EUs).
+	 */
 	I915_ENGINE_CLASS_RENDER	= 0,
+
+	/**
+	 * @I915_ENGINE_CLASS_COPY:
+	 *
+	 * Copy engines (also referred to as "blitters") support instructions
+	 * that move blocks of data from one location in memory to another,
+	 * or that fill a specified location of memory with fixed data.
+	 * Copy engines can perform pre-defined logical or bitwise operations
+	 * on the source, destination, or pattern data.
+	 */
 	I915_ENGINE_CLASS_COPY		= 1,
+
+	/**
+	 * @I915_ENGINE_CLASS_VIDEO:
+	 *
+	 * Video engines (also referred to as "bit stream decode" (BSD) or
+	 * "vdbox") support instructions that perform fixed-function media
+	 * decode and encode.
+	 */
 	I915_ENGINE_CLASS_VIDEO		= 2,
+
+	/**
+	 * @I915_ENGINE_CLASS_VIDEO_ENHANCE:
+	 *
+	 * Video enhancement engines (also referred to as "vebox") support
+	 * instructions related to image enhancement.
+	 */
 	I915_ENGINE_CLASS_VIDEO_ENHANCE	= 3,
 
-	/* should be kept compact */
+	/**
+	 * @I915_ENGINE_CLASS_COMPUTE:
+	 *
+	 * Compute engines support a subset of the instructions available
+	 * on render engines:  compute engines support Compute (GPGPU) and
+	 * programmable media workloads, but do not support the 3D pipeline.
+	 */
+	I915_ENGINE_CLASS_COMPUTE	= 4,
+
+	/* Values in this enum should be kept compact. */
 
+	/**
+	 * @I915_ENGINE_CLASS_INVALID:
+	 *
+	 * Placeholder value to represent an invalid engine class assignment.
+	 */
 	I915_ENGINE_CLASS_INVALID	= -1
 };
 
-/*
+/**
+ * struct i915_engine_class_instance - Engine class/instance identifier
+ *
  * There may be more than one engine fulfilling any role within the system.
  * Each engine of a class is given a unique instance number and therefore
  * any engine can be specified by its class:instance tuplet. APIs that allow
@@ -180,10 +232,21 @@ enum drm_i915_gem_engine_class {
  * for this identification.
  */
 struct i915_engine_class_instance {
-	__u16 engine_class; /* see enum drm_i915_gem_engine_class */
-	__u16 engine_instance;
+	/**
+	 * @engine_class:
+	 *
+	 * Engine class from enum drm_i915_gem_engine_class
+	 */
+	__u16 engine_class;
 #define I915_ENGINE_CLASS_INVALID_NONE -1
 #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
+
+	/**
+	 * @engine_instance:
+	 *
+	 * Engine instance.
+	 */
+	__u16 engine_instance;
 };
 
 /**
@@ -2657,24 +2720,65 @@ enum drm_i915_perf_record_type {
 	DRM_I915_PERF_RECORD_MAX /* non-ABI */
 };
 
-/*
+/**
+ * struct drm_i915_perf_oa_config
+ *
  * Structure to upload perf dynamic configuration into the kernel.
  */
 struct drm_i915_perf_oa_config {
-	/** String formatted like "%08x-%04x-%04x-%04x-%012x" */
+	/**
+	 * @uuid:
+	 *
+	 * String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x"
+	 */
 	char uuid[36];
 
+	/**
+	 * @n_mux_regs:
+	 *
+	 * Number of mux regs in &mux_regs_ptr.
+	 */
 	__u32 n_mux_regs;
+
+	/**
+	 * @n_boolean_regs:
+	 *
+	 * Number of boolean regs in &boolean_regs_ptr.
+	 */
 	__u32 n_boolean_regs;
+
+	/**
+	 * @n_flex_regs:
+	 *
+	 * Number of flex regs in &flex_regs_ptr.
+	 */
 	__u32 n_flex_regs;
 
-	/*
-	 * These fields are pointers to tuples of u32 values (register address,
-	 * value). For example the expected length of the buffer pointed by
-	 * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
+	/**
+	 * @mux_regs_ptr:
+	 *
+	 * Pointer to tuples of u32 values (register address, value) for mux
+	 * registers.  Expected length of buffer is (2 * sizeof(u32) *
+	 * &n_mux_regs).
 	 */
 	__u64 mux_regs_ptr;
+
+	/**
+	 * @boolean_regs_ptr:
+	 *
+	 * Pointer to tuples of u32 values (register address, value) for mux
+	 * registers.  Expected length of buffer is (2 * sizeof(u32) *
+	 * &n_boolean_regs).
+	 */
 	__u64 boolean_regs_ptr;
+
+	/**
+	 * @flex_regs_ptr:
+	 *
+	 * Pointer to tuples of u32 values (register address, value) for mux
+	 * registers.  Expected length of buffer is (2 * sizeof(u32) *
+	 * &n_flex_regs).
+	 */
 	__u64 flex_regs_ptr;
 };
 
@@ -2685,12 +2789,24 @@ struct drm_i915_perf_oa_config {
  * @data_ptr is also depends on the specific @query_id.
  */
 struct drm_i915_query_item {
-	/** @query_id: The id for this query */
+	/**
+	 * @query_id:
+	 *
+	 * The id for this query.  Currently accepted query IDs are:
+	 *  - %DRM_I915_QUERY_TOPOLOGY_INFO (see struct drm_i915_query_topology_info)
+	 *  - %DRM_I915_QUERY_ENGINE_INFO (see struct drm_i915_engine_info)
+	 *  - %DRM_I915_QUERY_PERF_CONFIG (see struct drm_i915_query_perf_config)
+	 *  - %DRM_I915_QUERY_MEMORY_REGIONS (see struct drm_i915_query_memory_regions)
+	 *  - %DRM_I915_QUERY_HWCONFIG_BLOB (see `GuC HWCONFIG blob uAPI`)
+	 *  - %DRM_I915_QUERY_GEOMETRY_SUBSLICES (see struct drm_i915_query_topology_info)
+	 */
 	__u64 query_id;
-#define DRM_I915_QUERY_TOPOLOGY_INFO    1
-#define DRM_I915_QUERY_ENGINE_INFO	2
-#define DRM_I915_QUERY_PERF_CONFIG      3
-#define DRM_I915_QUERY_MEMORY_REGIONS   4
+#define DRM_I915_QUERY_TOPOLOGY_INFO		1
+#define DRM_I915_QUERY_ENGINE_INFO		2
+#define DRM_I915_QUERY_PERF_CONFIG		3
+#define DRM_I915_QUERY_MEMORY_REGIONS		4
+#define DRM_I915_QUERY_HWCONFIG_BLOB		5
+#define DRM_I915_QUERY_GEOMETRY_SUBSLICES	6
 /* Must be kept compact -- no holes and well documented */
 
 	/**
@@ -2706,14 +2822,17 @@ struct drm_i915_query_item {
 	/**
 	 * @flags:
 	 *
-	 * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
+	 * When &query_id == %DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
 	 *
-	 * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
+	 * When &query_id == %DRM_I915_QUERY_PERF_CONFIG, must be one of the
 	 * following:
 	 *
-	 *	- DRM_I915_QUERY_PERF_CONFIG_LIST
-	 *      - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
-	 *      - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
+	 *	- %DRM_I915_QUERY_PERF_CONFIG_LIST
+	 *      - %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
+	 *      - %DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
+	 *
+	 * When &query_id == %DRM_I915_QUERY_GEOMETRY_SUBSLICES must contain
+	 * a struct i915_engine_class_instance that references a render engine.
 	 */
 	__u32 flags;
 #define DRM_I915_QUERY_PERF_CONFIG_LIST          1
@@ -2771,66 +2890,112 @@ struct drm_i915_query {
 	__u64 items_ptr;
 };
 
-/*
- * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
- *
- * data: contains the 3 pieces of information :
- *
- * - the slice mask with one bit per slice telling whether a slice is
- *   available. The availability of slice X can be queried with the following
- *   formula :
- *
- *           (data[X / 8] >> (X % 8)) & 1
- *
- * - the subslice mask for each slice with one bit per subslice telling
- *   whether a subslice is available. Gen12 has dual-subslices, which are
- *   similar to two gen11 subslices. For gen12, this array represents dual-
- *   subslices. The availability of subslice Y in slice X can be queried
- *   with the following formula :
- *
- *           (data[subslice_offset +
- *                 X * subslice_stride +
- *                 Y / 8] >> (Y % 8)) & 1
- *
- * - the EU mask for each subslice in each slice with one bit per EU telling
- *   whether an EU is available. The availability of EU Z in subslice Y in
- *   slice X can be queried with the following formula :
+/**
+ * struct drm_i915_query_topology_info
  *
- *           (data[eu_offset +
- *                 (X * max_subslices + Y) * eu_stride +
- *                 Z / 8] >> (Z % 8)) & 1
+ * Describes slice/subslice/EU information queried by
+ * %DRM_I915_QUERY_TOPOLOGY_INFO
  */
 struct drm_i915_query_topology_info {
-	/*
+	/**
+	 * @flags:
+	 *
 	 * Unused for now. Must be cleared to zero.
 	 */
 	__u16 flags;
 
+	/**
+	 * @max_slices:
+	 *
+	 * The number of bits used to express the slice mask.
+	 */
 	__u16 max_slices;
+
+	/**
+	 * @max_subslices:
+	 *
+	 * The number of bits used to express the subslice mask.
+	 */
 	__u16 max_subslices;
+
+	/**
+	 * @max_eus_per_subslice:
+	 *
+	 * The number of bits in the EU mask that correspond to a single
+	 * subslice's EUs.
+	 */
 	__u16 max_eus_per_subslice;
 
-	/*
+	/**
+	 * @subslice_offset:
+	 *
 	 * Offset in data[] at which the subslice masks are stored.
 	 */
 	__u16 subslice_offset;
 
-	/*
+	/**
+	 * @subslice_stride:
+	 *
 	 * Stride at which each of the subslice masks for each slice are
 	 * stored.
 	 */
 	__u16 subslice_stride;
 
-	/*
+	/**
+	 * @eu_offset:
+	 *
 	 * Offset in data[] at which the EU masks are stored.
 	 */
 	__u16 eu_offset;
 
-	/*
+	/**
+	 * @eu_stride:
+	 *
 	 * Stride at which each of the EU masks for each subslice are stored.
 	 */
 	__u16 eu_stride;
 
+	/**
+	 * @data:
+	 *
+	 * Contains 3 pieces of information :
+	 *
+	 * - The slice mask with one bit per slice telling whether a slice is
+	 *   available. The availability of slice X can be queried with the
+	 *   following formula :
+	 *
+	 *   .. code:: c
+	 *
+	 *      (data[X / 8] >> (X % 8)) & 1
+	 *
+	 *   Starting with Xe_HP platforms, Intel hardware no longer has
+	 *   traditional slices so i915 will always report a single slice
+	 *   (hardcoded slicemask = 0x1) which contains all of the platform's
+	 *   subslices.  I.e., the mask here does not reflect any of the newer
+	 *   hardware concepts such as "gslices" or "cslices" since userspace
+	 *   is capable of inferring those from the subslice mask.
+	 *
+	 * - The subslice mask for each slice with one bit per subslice telling
+	 *   whether a subslice is available.  Starting with Gen12 we use the
+	 *   term "subslice" to refer to what the hardware documentation
+	 *   describes as a "dual-subslices."  The availability of subslice Y
+	 *   in slice X can be queried with the following formula :
+	 *
+	 *   .. code:: c
+	 *
+	 *      (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1
+	 *
+	 * - The EU mask for each subslice in each slice, with one bit per EU
+	 *   telling whether an EU is available. The availability of EU Z in
+	 *   subslice Y in slice X can be queried with the following formula :
+	 *
+	 *   .. code:: c
+	 *
+	 *      (data[eu_offset +
+	 *            (X * max_subslices + Y) * eu_stride +
+	 *            Z / 8
+	 *       ] >> (Z % 8)) & 1
+	 */
 	__u8 data[];
 };
 
@@ -2951,52 +3116,68 @@ struct drm_i915_query_engine_info {
 	struct drm_i915_engine_info engines[];
 };
 
-/*
- * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
+/**
+ * struct drm_i915_query_perf_config
+ *
+ * Data written by the kernel with query %DRM_I915_QUERY_PERF_CONFIG and
+ * %DRM_I915_QUERY_GEOMETRY_SUBSLICES.
  */
 struct drm_i915_query_perf_config {
 	union {
-		/*
-		 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
-		 * this fields to the number of configurations available.
+		/**
+		 * @n_configs:
+		 *
+		 * When &drm_i915_query_item.flags ==
+		 * %DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets this fields to
+		 * the number of configurations available.
 		 */
 		__u64 n_configs;
 
-		/*
-		 * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
-		 * i915 will use the value in this field as configuration
-		 * identifier to decide what data to write into config_ptr.
+		/**
+		 * @config:
+		 *
+		 * When &drm_i915_query_item.flags ==
+		 * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID, i915 will use the
+		 * value in this field as configuration identifier to decide
+		 * what data to write into config_ptr.
 		 */
 		__u64 config;
 
-		/*
-		 * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
-		 * i915 will use the value in this field as configuration
-		 * identifier to decide what data to write into config_ptr.
+		/**
+		 * @uuid:
+		 *
+		 * When &drm_i915_query_item.flags ==
+		 * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID, i915 will use the
+		 * value in this field as configuration identifier to decide
+		 * what data to write into config_ptr.
 		 *
 		 * String formatted like "%08x-%04x-%04x-%04x-%012x"
 		 */
 		char uuid[36];
 	};
 
-	/*
+	/**
+	 * @flags:
+	 *
 	 * Unused for now. Must be cleared to zero.
 	 */
 	__u32 flags;
 
-	/*
-	 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
-	 * write an array of __u64 of configuration identifiers.
+	/**
+	 * @data:
 	 *
-	 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
-	 * write a struct drm_i915_perf_oa_config. If the following fields of
-	 * drm_i915_perf_oa_config are set not set to 0, i915 will write into
-	 * the associated pointers the values of submitted when the
+	 * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_LIST,
+	 * i915 will write an array of __u64 of configuration identifiers.
+	 *
+	 * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_DATA,
+	 * i915 will write a struct drm_i915_perf_oa_config. If the following
+	 * fields of struct drm_i915_perf_oa_config are not set to 0, i915 will
+	 * write into the associated pointers the values of submitted when the
 	 * configuration was created :
 	 *
-	 *         - n_mux_regs
-	 *         - n_boolean_regs
-	 *         - n_flex_regs
+	 *  - &drm_i915_perf_oa_config.n_mux_regs
+	 *  - &drm_i915_perf_oa_config.n_boolean_regs
+	 *  - &drm_i915_perf_oa_config.n_flex_regs
 	 */
 	__u8 data[];
 };
@@ -3134,6 +3315,16 @@ struct drm_i915_query_memory_regions {
 	struct drm_i915_memory_region_info regions[];
 };
 
+/**
+ * DOC: GuC HWCONFIG blob uAPI
+ *
+ * The GuC produces a blob with information about the current device.
+ * i915 reads this blob from GuC and makes it available via this uAPI.
+ *
+ * The format and meaning of the blob content are documented in the
+ * Programmer's Reference Manual.
+ */
+
 /**
  * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added
  * extension support using struct i915_user_extension.
-- 
GitLab


From 4b3f7644ae84bcf785cc88d35327227cb2fb6b82 Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Thu, 1 Jul 2021 13:39:15 -0300
Subject: [PATCH 1191/1731] tools headers cpufeatures: Sync with the kernel
 sources

To pick the changes from:

  d6d0c7f681fda1d0 ("x86/cpufeatures: Add PerfMonV2 feature bit")
  296d5a17e793956f ("KVM: SEV-ES: Use V_TSC_AUX if available instead of RDTSC/MSR_TSC_AUX intercepts")
  f30903394eb62316 ("x86/cpufeatures: Add virtual TSC_AUX feature bit")
  8ad7e8f696951f19 ("x86/fpu/xsave: Support XSAVEC in the kernel")
  59bd54a84d15e933 ("x86/tdx: Detect running as a TDX guest in early boot")
  a77d41ac3a0f41c8 ("x86/cpufeatures: Add AMD Fam19h Branch Sampling feature")

This only causes these perf files to be rebuilt:

  CC       /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o
  CC       /tmp/build/perf/bench/mem-memset-x86-64-asm.o

And addresses this perf build warning:

  Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h'
  diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h
  Warning: Kernel ABI header at 'tools/arch/x86/include/asm/disabled-features.h' differs from latest version at 'arch/x86/include/asm/disabled-features.h'
  diff -u tools/arch/x86/include/asm/disabled-features.h arch/x86/include/asm/disabled-features.h

Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Babu Moger <babu.moger@amd.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/lkml/YrDkgmwhLv+nKeOo@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/arch/x86/include/asm/cpufeatures.h       | 7 +++++--
 tools/arch/x86/include/asm/disabled-features.h | 8 +++++++-
 2 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index e17de69faa543..03acc823838a7 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -201,7 +201,7 @@
 #define X86_FEATURE_INVPCID_SINGLE	( 7*32+ 7) /* Effectively INVPCID && CR4.PCIDE=1 */
 #define X86_FEATURE_HW_PSTATE		( 7*32+ 8) /* AMD HW-PState */
 #define X86_FEATURE_PROC_FEEDBACK	( 7*32+ 9) /* AMD ProcFeedbackInterface */
-/* FREE!                                ( 7*32+10) */
+#define X86_FEATURE_XCOMPACTED		( 7*32+10) /* "" Use compacted XSTATE (XSAVES or XSAVEC) */
 #define X86_FEATURE_PTI			( 7*32+11) /* Kernel Page Table Isolation enabled */
 #define X86_FEATURE_RETPOLINE		( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
 #define X86_FEATURE_RETPOLINE_LFENCE	( 7*32+13) /* "" Use LFENCE for Spectre variant 2 */
@@ -211,7 +211,7 @@
 #define X86_FEATURE_SSBD		( 7*32+17) /* Speculative Store Bypass Disable */
 #define X86_FEATURE_MBA			( 7*32+18) /* Memory Bandwidth Allocation */
 #define X86_FEATURE_RSB_CTXSW		( 7*32+19) /* "" Fill RSB on context switches */
-/* FREE!                                ( 7*32+20) */
+#define X86_FEATURE_PERFMON_V2		( 7*32+20) /* AMD Performance Monitoring Version 2 */
 #define X86_FEATURE_USE_IBPB		( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */
 #define X86_FEATURE_USE_IBRS_FW		( 7*32+22) /* "" Use IBRS during runtime firmware calls */
 #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE	( 7*32+23) /* "" Disable Speculative Store Bypass. */
@@ -238,6 +238,7 @@
 #define X86_FEATURE_VMW_VMMCALL		( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */
 #define X86_FEATURE_PVUNLOCK		( 8*32+20) /* "" PV unlock function */
 #define X86_FEATURE_VCPUPREEMPT		( 8*32+21) /* "" PV vcpu_is_preempted function */
+#define X86_FEATURE_TDX_GUEST		( 8*32+22) /* Intel Trust Domain Extensions Guest */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
 #define X86_FEATURE_FSGSBASE		( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
@@ -315,6 +316,7 @@
 #define X86_FEATURE_VIRT_SSBD		(13*32+25) /* Virtualized Speculative Store Bypass Disable */
 #define X86_FEATURE_AMD_SSB_NO		(13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
 #define X86_FEATURE_CPPC		(13*32+27) /* Collaborative Processor Performance Control */
+#define X86_FEATURE_BRS			(13*32+31) /* Branch Sampling available */
 
 /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
 #define X86_FEATURE_DTHERM		(14*32+ 0) /* Digital Thermal Sensor */
@@ -405,6 +407,7 @@
 #define X86_FEATURE_SEV			(19*32+ 1) /* AMD Secure Encrypted Virtualization */
 #define X86_FEATURE_VM_PAGE_FLUSH	(19*32+ 2) /* "" VM Page Flush MSR is supported */
 #define X86_FEATURE_SEV_ES		(19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */
+#define X86_FEATURE_V_TSC_AUX		(19*32+ 9) /* "" Virtual TSC_AUX */
 #define X86_FEATURE_SME_COHERENT	(19*32+10) /* "" AMD hardware-enforced cache coherency */
 
 /*
diff --git a/tools/arch/x86/include/asm/disabled-features.h b/tools/arch/x86/include/asm/disabled-features.h
index 1ae0fab7d902b..36369e76cc631 100644
--- a/tools/arch/x86/include/asm/disabled-features.h
+++ b/tools/arch/x86/include/asm/disabled-features.h
@@ -62,6 +62,12 @@
 # define DISABLE_SGX	(1 << (X86_FEATURE_SGX & 31))
 #endif
 
+#ifdef CONFIG_INTEL_TDX_GUEST
+# define DISABLE_TDX_GUEST	0
+#else
+# define DISABLE_TDX_GUEST	(1 << (X86_FEATURE_TDX_GUEST & 31))
+#endif
+
 /*
  * Make sure to add features to the correct mask
  */
@@ -73,7 +79,7 @@
 #define DISABLED_MASK5	0
 #define DISABLED_MASK6	0
 #define DISABLED_MASK7	(DISABLE_PTI)
-#define DISABLED_MASK8	0
+#define DISABLED_MASK8	(DISABLE_TDX_GUEST)
 #define DISABLED_MASK9	(DISABLE_SGX)
 #define DISABLED_MASK10	0
 #define DISABLED_MASK11	0
-- 
GitLab


From ab66fdace8581ef3b4e7cf5381a168ed4058d779 Mon Sep 17 00:00:00 2001
From: Adrian Hunter <adrian.hunter@intel.com>
Date: Tue, 21 Jun 2022 15:51:44 +0300
Subject: [PATCH 1192/1731] perf build-id: Fix caching files with a wrong build
 ID

Build ID events associate a file name with a build ID.  However, when
using perf inject, there is no guarantee that the file on the current
machine at the current time has that build ID. Fix by comparing the
build IDs and skip adding to the cache if they are different.

Example:

  $ echo "int main() {return 0;}" > prog.c
  $ gcc -o prog prog.c
  $ perf record --buildid-all ./prog
  [ perf record: Woken up 1 times to write data ]
  [ perf record: Captured and wrote 0.019 MB perf.data ]
  $ file-buildid() { file $1 | awk -F= '{print $2}' | awk -F, '{print $1}' ; }
  $ file-buildid prog
  444ad9be165d8058a48ce2ffb4e9f55854a3293e
  $ file-buildid ~/.debug/$(pwd)/prog/444ad9be165d8058a48ce2ffb4e9f55854a3293e/elf
  444ad9be165d8058a48ce2ffb4e9f55854a3293e
  $ echo "int main() {return 1;}" > prog.c
  $ gcc -o prog prog.c
  $ file-buildid prog
  885524d5aaa24008a3e2b06caa3ea95d013c0fc5

Before:

  $ perf buildid-cache --purge $(pwd)/prog
  $ perf inject -i perf.data -o junk
  $ file-buildid ~/.debug/$(pwd)/prog/444ad9be165d8058a48ce2ffb4e9f55854a3293e/elf
  885524d5aaa24008a3e2b06caa3ea95d013c0fc5
  $

After:

  $ perf buildid-cache --purge $(pwd)/prog
  $ perf inject -i perf.data -o junk
  $ file-buildid ~/.debug/$(pwd)/prog/444ad9be165d8058a48ce2ffb4e9f55854a3293e/elf

  $

Fixes: 454c407ec17a0c63 ("perf: add perf-inject builtin")
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Tom Zanussi <tzanussi@gmail.com>
Link: https://lore.kernel.org/r/20220621125144.5623-1-adrian.hunter@intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/build-id.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/tools/perf/util/build-id.c b/tools/perf/util/build-id.c
index 82f3d46bea70e..328668f38c69d 100644
--- a/tools/perf/util/build-id.c
+++ b/tools/perf/util/build-id.c
@@ -872,6 +872,30 @@ out_free:
 	return err;
 }
 
+static int filename__read_build_id_ns(const char *filename,
+				      struct build_id *bid,
+				      struct nsinfo *nsi)
+{
+	struct nscookie nsc;
+	int ret;
+
+	nsinfo__mountns_enter(nsi, &nsc);
+	ret = filename__read_build_id(filename, bid);
+	nsinfo__mountns_exit(&nsc);
+
+	return ret;
+}
+
+static bool dso__build_id_mismatch(struct dso *dso, const char *name)
+{
+	struct build_id bid;
+
+	if (filename__read_build_id_ns(name, &bid, dso->nsinfo) < 0)
+		return false;
+
+	return !dso__build_id_equal(dso, &bid);
+}
+
 static int dso__cache_build_id(struct dso *dso, struct machine *machine,
 			       void *priv __maybe_unused)
 {
@@ -886,6 +910,10 @@ static int dso__cache_build_id(struct dso *dso, struct machine *machine,
 		is_kallsyms = true;
 		name = machine->mmap_name;
 	}
+
+	if (!is_kallsyms && dso__build_id_mismatch(dso, name))
+		return 0;
+
 	return build_id_cache__add_b(&dso->bid, name, dso->nsinfo,
 				     is_kallsyms, is_vdso);
 }
-- 
GitLab


From 3713e2494b6ab98f0476bb575b22323775f7d77a Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Tue, 21 Jun 2022 12:34:37 -0300
Subject: [PATCH 1193/1731] perf trace beauty: Fix generation of errno id->str
 table on ALT Linux

For some reason using:

         cat <<EoFuncBegin
  static const char *errno_to_name__$arch(int err)
  {
         switch (err) {
  EoFuncBegin

In tools/perf/trace/beauty/arch_errno_names.sh isn't working on ALT
Linux sisyphus (development version), which could be some distro
specific glitch, so just get this done in an alternative way that works
everywhere while giving notice to the people working on that distro to
try and figure our what really took place.

Cc: Gleb Fotengauer-Malinovskiy <glebfm@altlinux.org>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/trace/beauty/arch_errno_names.sh | 14 ++------------
 1 file changed, 2 insertions(+), 12 deletions(-)

diff --git a/tools/perf/trace/beauty/arch_errno_names.sh b/tools/perf/trace/beauty/arch_errno_names.sh
index 2c5f72fa81087..37c53bac5f56e 100755
--- a/tools/perf/trace/beauty/arch_errno_names.sh
+++ b/tools/perf/trace/beauty/arch_errno_names.sh
@@ -33,23 +33,13 @@ create_errno_lookup_func()
 	local arch=$(arch_string "$1")
 	local nr name
 
-	cat <<EoFuncBegin
-static const char *errno_to_name__$arch(int err)
-{
-	switch (err) {
-EoFuncBegin
+	printf "static const char *errno_to_name__%s(int err)\n{\n\tswitch (err) {\n" $arch
 
 	while read name nr; do
 		printf '\tcase %d: return "%s";\n' $nr $name
 	done
 
-	cat <<EoFuncEnd
-	default:
-		return "(unknown)";
-	}
-}
-
-EoFuncEnd
+	printf '\tdefault: return "(unknown)";\n\t}\n}\n'
 }
 
 process_arch()
-- 
GitLab


From 37ed2cddcbf1b52b03b9b2344c752ed867fa3539 Mon Sep 17 00:00:00 2001
From: Raul Silvera <rsilvera@google.com>
Date: Tue, 21 Jun 2022 15:27:25 +0000
Subject: [PATCH 1194/1731] perf inject: Adjust output data offset for backward
 compatibility

When 'perf inject' creates a new file, it reuses the data offset from
the input file. If there has been a change on the size of the header, as
happened in v5.12 -> v5.13, the new offsets will be wrong, resulting in
a corrupted output file.

This change adds the function perf_session__data_offset to compute the
data offset based on the current header size, and uses that instead of
the offset from the original input file.

Signed-off-by: Raul Silvera <rsilvera@google.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Athira Jajeev <atrajeev@linux.vnet.ibm.com>
Cc: Colin Ian King <colin.king@intel.com>
Cc: Dave Marchevsky <davemarchevsky@fb.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20220621152725.2668041-1-rsilvera@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/builtin-inject.c |  2 +-
 tools/perf/util/header.c    | 14 ++++++++++++++
 tools/perf/util/header.h    |  2 ++
 3 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/tools/perf/builtin-inject.c b/tools/perf/builtin-inject.c
index 063f74f5b8db5..54d4e508a0920 100644
--- a/tools/perf/builtin-inject.c
+++ b/tools/perf/builtin-inject.c
@@ -918,7 +918,7 @@ static int __cmd_inject(struct perf_inject *inject)
 		inject->tool.tracing_data = perf_event__repipe_tracing_data;
 	}
 
-	output_data_offset = session->header.data_offset;
+	output_data_offset = perf_session__data_offset(session->evlist);
 
 	if (inject->build_id_all) {
 		inject->tool.mmap	  = perf_event__repipe_buildid_mmap;
diff --git a/tools/perf/util/header.c b/tools/perf/util/header.c
index 53332da100e83..6ad629db63b7d 100644
--- a/tools/perf/util/header.c
+++ b/tools/perf/util/header.c
@@ -3686,6 +3686,20 @@ int perf_session__write_header(struct perf_session *session,
 	return perf_session__do_write_header(session, evlist, fd, at_exit, NULL);
 }
 
+size_t perf_session__data_offset(const struct evlist *evlist)
+{
+	struct evsel *evsel;
+	size_t data_offset;
+
+	data_offset = sizeof(struct perf_file_header);
+	evlist__for_each_entry(evlist, evsel) {
+		data_offset += evsel->core.ids * sizeof(u64);
+	}
+	data_offset += evlist->core.nr_entries * sizeof(struct perf_file_attr);
+
+	return data_offset;
+}
+
 int perf_session__inject_header(struct perf_session *session,
 				struct evlist *evlist,
 				int fd,
diff --git a/tools/perf/util/header.h b/tools/perf/util/header.h
index 08563c1f1bffe..56916dabce7be 100644
--- a/tools/perf/util/header.h
+++ b/tools/perf/util/header.h
@@ -136,6 +136,8 @@ int perf_session__inject_header(struct perf_session *session,
 				int fd,
 				struct feat_copier *fc);
 
+size_t perf_session__data_offset(const struct evlist *evlist);
+
 void perf_header__set_feat(struct perf_header *header, int feat);
 void perf_header__clear_feat(struct perf_header *header, int feat);
 bool perf_header__has_feat(const struct perf_header *header, int feat);
-- 
GitLab


From 448ce0e6ea93ae99e0b36055e5f5a3f723fe3665 Mon Sep 17 00:00:00 2001
From: Gang Li <ligang.bdlg@bytedance.com>
Date: Wed, 22 Jun 2022 11:00:37 +0800
Subject: [PATCH 1195/1731] perf stat: Enable ignore_missing_thread

perf already support ignore_missing_thread for -p, but not yet
applied to `perf stat -p <pid>`. This patch enables ignore_missing_thread
for `perf stat -p <pid>`.

Committer notes:

And here is a refresher about the 'ignore_missing_thread' knob, from a
previous patch using it:

  ca8000684ec4e66f ("perf evsel: Enable ignore_missing_thread for pid option")

  ---
    While monitoring a multithread process with pid option, perf sometimes
    may return sys_perf_event_open failure with 3(No such process) if any of
    the process's threads die before we open the event. However, we want
    perf continue monitoring the remaining threads and do not exit with
    error.
  ---

Signed-off-by: Gang Li <ligang.bdlg@bytedance.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20220622030037.15005-1-ligang.bdlg@bytedance.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/builtin-stat.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c
index 4ce87a8eb7d7e..d2ecd4d296243 100644
--- a/tools/perf/builtin-stat.c
+++ b/tools/perf/builtin-stat.c
@@ -2586,6 +2586,8 @@ int cmd_stat(int argc, const char **argv)
 	if (evlist__initialize_ctlfd(evsel_list, stat_config.ctl_fd, stat_config.ctl_fd_ack))
 		goto out;
 
+	/* Enable ignoring missing threads when -p option is defined. */
+	evlist__first(evsel_list)->ignore_missing_thread = target.pid;
 	status = 0;
 	for (run_idx = 0; forever || run_idx < stat_config.run_count; run_idx++) {
 		if (stat_config.run_count != 1 && verbose > 0)
-- 
GitLab


From e2213a2dc63e1b2941728a9a938c2196548e980f Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Tue, 14 Apr 2020 09:12:55 -0300
Subject: [PATCH 1196/1731] tools include UAPI: Sync linux/vhost.h with the
 kernel sources

To get the changes in:

  84d7c8fd3aade2fe ("vhost-vdpa: introduce uAPI to set group ASID")
  2d1fcb7758e49fd9 ("vhost-vdpa: uAPI to get virtqueue group id")
  a0c95f201170bd55 ("vhost-vdpa: introduce uAPI to get the number of address spaces")
  3ace88bd37436abc ("vhost-vdpa: introduce uAPI to get the number of virtqueue groups")
  175d493c3c3e09a3 ("vhost: move the backend feature bits to vhost_types.h")

Silencing this perf build warning:

  Warning: Kernel ABI header at 'tools/include/uapi/linux/vhost.h' differs from latest version at 'include/uapi/linux/vhost.h'
  diff -u tools/include/uapi/linux/vhost.h include/uapi/linux/vhost.h

To pick up these changes and support them:

  $ tools/perf/trace/beauty/vhost_virtio_ioctl.sh > before
  $ cp include/uapi/linux/vhost.h tools/include/uapi/linux/vhost.h
  $ tools/perf/trace/beauty/vhost_virtio_ioctl.sh > after
  $ diff -u before after
  --- before	2022-06-26 12:04:35.982003781 -0300
  +++ after	2022-06-26 12:04:43.819972476 -0300
  @@ -28,6 +28,7 @@
   	[0x74] = "VDPA_SET_CONFIG",
   	[0x75] = "VDPA_SET_VRING_ENABLE",
   	[0x77] = "VDPA_SET_CONFIG_CALL",
  +	[0x7C] = "VDPA_SET_GROUP_ASID",
   };
   static const char *vhost_virtio_ioctl_read_cmds[] = {
   	[0x00] = "GET_FEATURES",
  @@ -39,5 +40,8 @@
   	[0x76] = "VDPA_GET_VRING_NUM",
   	[0x78] = "VDPA_GET_IOVA_RANGE",
   	[0x79] = "VDPA_GET_CONFIG_SIZE",
  +	[0x7A] = "VDPA_GET_AS_NUM",
  +	[0x7B] = "VDPA_GET_VRING_GROUP",
   	[0x80] = "VDPA_GET_VQS_COUNT",
  +	[0x81] = "VDPA_GET_GROUP_NUM",
   };
  $

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Gautam Dawar <gautam.dawar@xilinx.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/lkml/Yrh3xMYbfeAD0MFL@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/include/uapi/linux/vhost.h | 26 ++++++++++++++++++++------
 1 file changed, 20 insertions(+), 6 deletions(-)

diff --git a/tools/include/uapi/linux/vhost.h b/tools/include/uapi/linux/vhost.h
index 5d99e7c242a25..cab645d4a6455 100644
--- a/tools/include/uapi/linux/vhost.h
+++ b/tools/include/uapi/linux/vhost.h
@@ -89,11 +89,6 @@
 
 /* Set or get vhost backend capability */
 
-/* Use message type V2 */
-#define VHOST_BACKEND_F_IOTLB_MSG_V2 0x1
-/* IOTLB can accept batching hints */
-#define VHOST_BACKEND_F_IOTLB_BATCH  0x2
-
 #define VHOST_SET_BACKEND_FEATURES _IOW(VHOST_VIRTIO, 0x25, __u64)
 #define VHOST_GET_BACKEND_FEATURES _IOR(VHOST_VIRTIO, 0x26, __u64)
 
@@ -150,11 +145,30 @@
 /* Get the valid iova range */
 #define VHOST_VDPA_GET_IOVA_RANGE	_IOR(VHOST_VIRTIO, 0x78, \
 					     struct vhost_vdpa_iova_range)
-
 /* Get the config size */
 #define VHOST_VDPA_GET_CONFIG_SIZE	_IOR(VHOST_VIRTIO, 0x79, __u32)
 
 /* Get the count of all virtqueues */
 #define VHOST_VDPA_GET_VQS_COUNT	_IOR(VHOST_VIRTIO, 0x80, __u32)
 
+/* Get the number of virtqueue groups. */
+#define VHOST_VDPA_GET_GROUP_NUM	_IOR(VHOST_VIRTIO, 0x81, __u32)
+
+/* Get the number of address spaces. */
+#define VHOST_VDPA_GET_AS_NUM		_IOR(VHOST_VIRTIO, 0x7A, unsigned int)
+
+/* Get the group for a virtqueue: read index, write group in num,
+ * The virtqueue index is stored in the index field of
+ * vhost_vring_state. The group for this specific virtqueue is
+ * returned via num field of vhost_vring_state.
+ */
+#define VHOST_VDPA_GET_VRING_GROUP	_IOWR(VHOST_VIRTIO, 0x7B,	\
+					      struct vhost_vring_state)
+/* Set the ASID for a virtqueue group. The group index is stored in
+ * the index field of vhost_vring_state, the ASID associated with this
+ * group is stored at num field of vhost_vring_state.
+ */
+#define VHOST_VDPA_SET_GROUP_ASID	_IOW(VHOST_VIRTIO, 0x7C, \
+					     struct vhost_vring_state)
+
 #endif
-- 
GitLab


From f8d866194082e703c86751cceb07f6243cde96d2 Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Mon, 21 Dec 2020 20:04:45 -0300
Subject: [PATCH 1197/1731] tools headers UAPI: Synch KVM's svm.h header with
 the kernel

To pick up the changes from:

  d5af44dde5461d12 ("x86/sev: Provide support for SNP guest request NAEs")
  0afb6b660a6b58cb ("x86/sev: Use SEV-SNP AP creation to start secondary CPUs")
  dc3f3d2474b80eae ("x86/mm: Validate memory when changing the C-bit")
  cbd3d4f7c4e5a93e ("x86/sev: Check SEV-SNP features support")

That gets these new SVM exit reasons:

+       { SVM_VMGEXIT_PSC,              "vmgexit_page_state_change" }, \
+       { SVM_VMGEXIT_GUEST_REQUEST,    "vmgexit_guest_request" }, \
+       { SVM_VMGEXIT_EXT_GUEST_REQUEST, "vmgexit_ext_guest_request" }, \
+       { SVM_VMGEXIT_AP_CREATION,      "vmgexit_ap_creation" }, \
+       { SVM_VMGEXIT_HV_FEATURES,      "vmgexit_hypervisor_feature" }, \

Addressing this perf build warning:

  Warning: Kernel ABI header at 'tools/arch/x86/include/uapi/asm/svm.h' differs from latest version at 'arch/x86/include/uapi/asm/svm.h'
  diff -u tools/arch/x86/include/uapi/asm/svm.h arch/x86/include/uapi/asm/svm.h

This causes these changes:

  CC      /tmp/build/perf-urgent/arch/x86/util/kvm-stat.o
  LD      /tmp/build/perf-urgent/arch/x86/util/perf-in.o
  LD      /tmp/build/perf-urgent/arch/x86/perf-in.o
  LD      /tmp/build/perf-urgent/arch/perf-in.o
  LD      /tmp/build/perf-urgent/perf-in.o
  LINK    /tmp/build/perf-urgent/perf

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/arch/x86/include/uapi/asm/svm.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/tools/arch/x86/include/uapi/asm/svm.h b/tools/arch/x86/include/uapi/asm/svm.h
index efa969325ede5..f69c168391aa5 100644
--- a/tools/arch/x86/include/uapi/asm/svm.h
+++ b/tools/arch/x86/include/uapi/asm/svm.h
@@ -108,6 +108,14 @@
 #define SVM_VMGEXIT_AP_JUMP_TABLE		0x80000005
 #define SVM_VMGEXIT_SET_AP_JUMP_TABLE		0
 #define SVM_VMGEXIT_GET_AP_JUMP_TABLE		1
+#define SVM_VMGEXIT_PSC				0x80000010
+#define SVM_VMGEXIT_GUEST_REQUEST		0x80000011
+#define SVM_VMGEXIT_EXT_GUEST_REQUEST		0x80000012
+#define SVM_VMGEXIT_AP_CREATION			0x80000013
+#define SVM_VMGEXIT_AP_CREATE_ON_INIT		0
+#define SVM_VMGEXIT_AP_CREATE			1
+#define SVM_VMGEXIT_AP_DESTROY			2
+#define SVM_VMGEXIT_HV_FEATURES			0x8000fffd
 #define SVM_VMGEXIT_UNSUPPORTED_EVENT		0x8000ffff
 
 /* Exit code reserved for hypervisor/software use */
@@ -218,6 +226,11 @@
 	{ SVM_VMGEXIT_NMI_COMPLETE,	"vmgexit_nmi_complete" }, \
 	{ SVM_VMGEXIT_AP_HLT_LOOP,	"vmgexit_ap_hlt_loop" }, \
 	{ SVM_VMGEXIT_AP_JUMP_TABLE,	"vmgexit_ap_jump_table" }, \
+	{ SVM_VMGEXIT_PSC,		"vmgexit_page_state_change" }, \
+	{ SVM_VMGEXIT_GUEST_REQUEST,	"vmgexit_guest_request" }, \
+	{ SVM_VMGEXIT_EXT_GUEST_REQUEST, "vmgexit_ext_guest_request" }, \
+	{ SVM_VMGEXIT_AP_CREATION,	"vmgexit_ap_creation" }, \
+	{ SVM_VMGEXIT_HV_FEATURES,	"vmgexit_hypervisor_feature" }, \
 	{ SVM_EXIT_ERR,         "invalid_guest_state" }
 
 
-- 
GitLab


From 03c765b0e3b4cb5063276b086c76f7a612856a9a Mon Sep 17 00:00:00 2001
From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sun, 26 Jun 2022 14:22:10 -0700
Subject: [PATCH 1198/1731] Linux 5.19-rc4

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index a3ff166c50354..8973b285ce6c7 100644
--- a/Makefile
+++ b/Makefile
@@ -2,7 +2,7 @@
 VERSION = 5
 PATCHLEVEL = 19
 SUBLEVEL = 0
-EXTRAVERSION = -rc3
+EXTRAVERSION = -rc4
 NAME = Superb Owl
 
 # *DOCUMENTATION*
-- 
GitLab


From ca76a761ea2497a250988fd67f12fd93524e611e Mon Sep 17 00:00:00 2001
From: Kaixu Xia <kaixuxia@tencent.com>
Date: Sun, 19 Jun 2022 14:53:42 -0700
Subject: [PATCH 1199/1731] xfs: factor out the common lock flags assert

There are similar lock flags assert in xfs_ilock(), xfs_ilock_nowait(),
xfs_iunlock(), thus we can factor it out into a helper that is clear.

Signed-off-by: Kaixu Xia <kaixuxia@tencent.com>
Reviewed-by: Dave Chinner <dchinner@redhat.com>
Reviewed-by: Darrick J. Wong <djwong@kernel.org>
Signed-off-by: Darrick J. Wong <djwong@kernel.org>
---
 fs/xfs/xfs_inode.c | 60 ++++++++++++++++++----------------------------
 1 file changed, 23 insertions(+), 37 deletions(-)

diff --git a/fs/xfs/xfs_inode.c b/fs/xfs/xfs_inode.c
index 52d6f2c7d58b3..8b8bac7eba8cf 100644
--- a/fs/xfs/xfs_inode.c
+++ b/fs/xfs/xfs_inode.c
@@ -131,6 +131,26 @@ xfs_ilock_attr_map_shared(
 	return lock_mode;
 }
 
+/*
+ * You can't set both SHARED and EXCL for the same lock,
+ * and only XFS_IOLOCK_SHARED, XFS_IOLOCK_EXCL, XFS_MMAPLOCK_SHARED,
+ * XFS_MMAPLOCK_EXCL, XFS_ILOCK_SHARED, XFS_ILOCK_EXCL are valid values
+ * to set in lock_flags.
+ */
+static inline void
+xfs_lock_flags_assert(
+	uint		lock_flags)
+{
+	ASSERT((lock_flags & (XFS_IOLOCK_SHARED | XFS_IOLOCK_EXCL)) !=
+		(XFS_IOLOCK_SHARED | XFS_IOLOCK_EXCL));
+	ASSERT((lock_flags & (XFS_MMAPLOCK_SHARED | XFS_MMAPLOCK_EXCL)) !=
+		(XFS_MMAPLOCK_SHARED | XFS_MMAPLOCK_EXCL));
+	ASSERT((lock_flags & (XFS_ILOCK_SHARED | XFS_ILOCK_EXCL)) !=
+		(XFS_ILOCK_SHARED | XFS_ILOCK_EXCL));
+	ASSERT((lock_flags & ~(XFS_LOCK_MASK | XFS_LOCK_SUBCLASS_MASK)) == 0);
+	ASSERT(lock_flags != 0);
+}
+
 /*
  * In addition to i_rwsem in the VFS inode, the xfs inode contains 2
  * multi-reader locks: invalidate_lock and the i_lock.  This routine allows
@@ -168,18 +188,7 @@ xfs_ilock(
 {
 	trace_xfs_ilock(ip, lock_flags, _RET_IP_);
 
-	/*
-	 * You can't set both SHARED and EXCL for the same lock,
-	 * and only XFS_IOLOCK_SHARED, XFS_IOLOCK_EXCL, XFS_ILOCK_SHARED,
-	 * and XFS_ILOCK_EXCL are valid values to set in lock_flags.
-	 */
-	ASSERT((lock_flags & (XFS_IOLOCK_SHARED | XFS_IOLOCK_EXCL)) !=
-	       (XFS_IOLOCK_SHARED | XFS_IOLOCK_EXCL));
-	ASSERT((lock_flags & (XFS_MMAPLOCK_SHARED | XFS_MMAPLOCK_EXCL)) !=
-	       (XFS_MMAPLOCK_SHARED | XFS_MMAPLOCK_EXCL));
-	ASSERT((lock_flags & (XFS_ILOCK_SHARED | XFS_ILOCK_EXCL)) !=
-	       (XFS_ILOCK_SHARED | XFS_ILOCK_EXCL));
-	ASSERT((lock_flags & ~(XFS_LOCK_MASK | XFS_LOCK_SUBCLASS_MASK)) == 0);
+	xfs_lock_flags_assert(lock_flags);
 
 	if (lock_flags & XFS_IOLOCK_EXCL) {
 		down_write_nested(&VFS_I(ip)->i_rwsem,
@@ -222,18 +231,7 @@ xfs_ilock_nowait(
 {
 	trace_xfs_ilock_nowait(ip, lock_flags, _RET_IP_);
 
-	/*
-	 * You can't set both SHARED and EXCL for the same lock,
-	 * and only XFS_IOLOCK_SHARED, XFS_IOLOCK_EXCL, XFS_ILOCK_SHARED,
-	 * and XFS_ILOCK_EXCL are valid values to set in lock_flags.
-	 */
-	ASSERT((lock_flags & (XFS_IOLOCK_SHARED | XFS_IOLOCK_EXCL)) !=
-	       (XFS_IOLOCK_SHARED | XFS_IOLOCK_EXCL));
-	ASSERT((lock_flags & (XFS_MMAPLOCK_SHARED | XFS_MMAPLOCK_EXCL)) !=
-	       (XFS_MMAPLOCK_SHARED | XFS_MMAPLOCK_EXCL));
-	ASSERT((lock_flags & (XFS_ILOCK_SHARED | XFS_ILOCK_EXCL)) !=
-	       (XFS_ILOCK_SHARED | XFS_ILOCK_EXCL));
-	ASSERT((lock_flags & ~(XFS_LOCK_MASK | XFS_LOCK_SUBCLASS_MASK)) == 0);
+	xfs_lock_flags_assert(lock_flags);
 
 	if (lock_flags & XFS_IOLOCK_EXCL) {
 		if (!down_write_trylock(&VFS_I(ip)->i_rwsem))
@@ -291,19 +289,7 @@ xfs_iunlock(
 	xfs_inode_t		*ip,
 	uint			lock_flags)
 {
-	/*
-	 * You can't set both SHARED and EXCL for the same lock,
-	 * and only XFS_IOLOCK_SHARED, XFS_IOLOCK_EXCL, XFS_ILOCK_SHARED,
-	 * and XFS_ILOCK_EXCL are valid values to set in lock_flags.
-	 */
-	ASSERT((lock_flags & (XFS_IOLOCK_SHARED | XFS_IOLOCK_EXCL)) !=
-	       (XFS_IOLOCK_SHARED | XFS_IOLOCK_EXCL));
-	ASSERT((lock_flags & (XFS_MMAPLOCK_SHARED | XFS_MMAPLOCK_EXCL)) !=
-	       (XFS_MMAPLOCK_SHARED | XFS_MMAPLOCK_EXCL));
-	ASSERT((lock_flags & (XFS_ILOCK_SHARED | XFS_ILOCK_EXCL)) !=
-	       (XFS_ILOCK_SHARED | XFS_ILOCK_EXCL));
-	ASSERT((lock_flags & ~(XFS_LOCK_MASK | XFS_LOCK_SUBCLASS_MASK)) == 0);
-	ASSERT(lock_flags != 0);
+	xfs_lock_flags_assert(lock_flags);
 
 	if (lock_flags & XFS_IOLOCK_EXCL)
 		up_write(&VFS_I(ip)->i_rwsem);
-- 
GitLab


From 82af88063961da9425924d9aec3fb67a4ebade3e Mon Sep 17 00:00:00 2001
From: Kaixu Xia <kaixuxia@tencent.com>
Date: Sun, 19 Jun 2022 14:53:43 -0700
Subject: [PATCH 1200/1731] xfs: use invalidate_lock to check the state of
 mmap_lock

We should use invalidate_lock and XFS_MMAPLOCK_SHARED to check the state
of mmap_lock rw_semaphore in xfs_isilocked(), rather than i_rwsem and
XFS_IOLOCK_SHARED.

Fixes: 2433480a7e1d ("xfs: Convert to use invalidate_lock")
Signed-off-by: Kaixu Xia <kaixuxia@tencent.com>
Reviewed-by: Dave Chinner <dchinner@redhat.com>
Reviewed-by: Darrick J. Wong <djwong@kernel.org>
Signed-off-by: Darrick J. Wong <djwong@kernel.org>
---
 fs/xfs/xfs_inode.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fs/xfs/xfs_inode.c b/fs/xfs/xfs_inode.c
index 8b8bac7eba8cf..3e1c62ffa4f76 100644
--- a/fs/xfs/xfs_inode.c
+++ b/fs/xfs/xfs_inode.c
@@ -365,8 +365,8 @@ xfs_isilocked(
 	}
 
 	if (lock_flags & (XFS_MMAPLOCK_EXCL|XFS_MMAPLOCK_SHARED)) {
-		return __xfs_rwsem_islocked(&VFS_I(ip)->i_rwsem,
-				(lock_flags & XFS_IOLOCK_SHARED));
+		return __xfs_rwsem_islocked(&VFS_I(ip)->i_mapping->invalidate_lock,
+				(lock_flags & XFS_MMAPLOCK_SHARED));
 	}
 
 	if (lock_flags & (XFS_IOLOCK_EXCL | XFS_IOLOCK_SHARED)) {
-- 
GitLab


From b822ea17fd15659b92cb86c48d018c9e43d0fd98 Mon Sep 17 00:00:00 2001
From: "Darrick J. Wong" <djwong@kernel.org>
Date: Wed, 22 Jun 2022 16:57:07 -0700
Subject: [PATCH 1201/1731] xfs: always free xattri_leaf_bp when cancelling a
 deferred op

While running the following fstest with logged xattrs DISabled, I
noticed the following:

# FSSTRESS_AVOID="-z -f unlink=1 -f rmdir=1 -f creat=2 -f mkdir=2 -f
getfattr=3 -f listfattr=3 -f attr_remove=4 -f removefattr=4 -f
setfattr=20 -f attr_set=60" ./check generic/475

INFO: task u9:1:40 blocked for more than 61 seconds.
      Tainted: G           O      5.19.0-rc2-djwx #rc2
"echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
task:u9:1            state:D stack:12872 pid:   40 ppid:     2 flags:0x00004000
Workqueue: xfs-cil/dm-0 xlog_cil_push_work [xfs]
Call Trace:
 <TASK>
 __schedule+0x2db/0x1110
 schedule+0x58/0xc0
 schedule_timeout+0x115/0x160
 __down_common+0x126/0x210
 down+0x54/0x70
 xfs_buf_lock+0x2d/0xe0 [xfs 0532c1cb1d67dd81d15cb79ac6e415c8dec58f73]
 xfs_buf_item_unpin+0x227/0x3a0 [xfs 0532c1cb1d67dd81d15cb79ac6e415c8dec58f73]
 xfs_trans_committed_bulk+0x18e/0x320 [xfs 0532c1cb1d67dd81d15cb79ac6e415c8dec58f73]
 xlog_cil_committed+0x2ea/0x360 [xfs 0532c1cb1d67dd81d15cb79ac6e415c8dec58f73]
 xlog_cil_push_work+0x60f/0x690 [xfs 0532c1cb1d67dd81d15cb79ac6e415c8dec58f73]
 process_one_work+0x1df/0x3c0
 worker_thread+0x53/0x3b0
 kthread+0xea/0x110
 ret_from_fork+0x1f/0x30
 </TASK>

This appears to be the result of shortform_to_leaf creating a new leaf
buffer as part of adding an xattr to a file.  The new leaf buffer is
held and attached to the xfs_attr_intent structure, but then the
filesystem shuts down.  Instead of the usual path (which adds the attr
to the held leaf buffer which releases the hold), we instead cancel the
entire deferred operation.

Unfortunately, xfs_attr_cancel_item doesn't release any attached leaf
buffers, so we leak the locked buffer.  The CIL cannot do anything
about that, and hangs.  Fix this by teaching it to release leaf buffers,
and make XFS a little more careful about not leaving a dangling
reference.

The prologue of xfs_attri_item_recover is (in this author's opinion) a
little hard to figure out, so I'll clean that up in the next patch.

Signed-off-by: Darrick J. Wong <djwong@kernel.org>
Reviewed-by: Dave Chinner <dchinner@redhat.com>
---
 fs/xfs/xfs_attr_item.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/fs/xfs/xfs_attr_item.c b/fs/xfs/xfs_attr_item.c
index 135d441334773..4f37fb251fe7a 100644
--- a/fs/xfs/xfs_attr_item.c
+++ b/fs/xfs/xfs_attr_item.c
@@ -455,6 +455,8 @@ static inline void
 xfs_attr_free_item(
 	struct xfs_attr_intent		*attr)
 {
+	ASSERT(attr->xattri_leaf_bp == NULL);
+
 	if (attr->xattri_da_state)
 		xfs_da_state_free(attr->xattri_da_state);
 	xfs_attri_log_nameval_put(attr->xattri_nameval);
@@ -509,6 +511,10 @@ xfs_attr_cancel_item(
 	struct xfs_attr_intent		*attr;
 
 	attr = container_of(item, struct xfs_attr_intent, xattri_list);
+	if (attr->xattri_leaf_bp) {
+		xfs_buf_relse(attr->xattri_leaf_bp);
+		attr->xattri_leaf_bp = NULL;
+	}
 	xfs_attr_free_item(attr);
 }
 
@@ -670,9 +676,21 @@ xfs_attri_item_recover(
 	error = xfs_defer_ops_capture_and_commit(tp, capture_list);
 
 out_unlock:
-	if (attr->xattri_leaf_bp)
+	if (attr->xattri_leaf_bp) {
 		xfs_buf_relse(attr->xattri_leaf_bp);
 
+		/*
+		 * If there's more work to do to complete the attr intent, the
+		 * defer capture structure will have taken its own reference to
+		 * the attr leaf buffer and will give that to the continuation
+		 * transaction.  The attr intent struct drives the continuation
+		 * work, so release our refcount on the attr leaf buffer but
+		 * retain the pointer in the intent structure.
+		 */
+		if (ret != -EAGAIN)
+			attr->xattri_leaf_bp = NULL;
+	}
+
 	xfs_iunlock(ip, XFS_ILOCK_EXCL);
 	xfs_irele(ip);
 out:
-- 
GitLab


From f94e08b602d45ec8ea69fb0aa1c85b712a6a4558 Mon Sep 17 00:00:00 2001
From: "Darrick J. Wong" <djwong@kernel.org>
Date: Thu, 23 Jun 2022 09:26:38 -0700
Subject: [PATCH 1202/1731] xfs: clean up the end of xfs_attri_item_recover

The end of this function could use some cleanup -- the EAGAIN
conditionals make it harder to figure out what's going on with the
disposal of xattri_leaf_bp, and the dual error/ret variables aren't
needed.  Turn the EAGAIN case into a separate block documenting all the
subtleties of recovering in the middle of an xattr update chain, which
makes the rest of the prologue much simpler.

Signed-off-by: Darrick J. Wong <djwong@kernel.org>
Reviewed-by: Dave Chinner <dchinner@redhat.com>
---
 fs/xfs/xfs_attr_item.c | 45 ++++++++++++++++++++++++------------------
 1 file changed, 26 insertions(+), 19 deletions(-)

diff --git a/fs/xfs/xfs_attr_item.c b/fs/xfs/xfs_attr_item.c
index 4f37fb251fe7a..6ee905a09eb24 100644
--- a/fs/xfs/xfs_attr_item.c
+++ b/fs/xfs/xfs_attr_item.c
@@ -582,7 +582,7 @@ xfs_attri_item_recover(
 	struct xfs_trans_res		tres;
 	struct xfs_attri_log_format	*attrp;
 	struct xfs_attri_log_nameval	*nv = attrip->attri_nameval;
-	int				error, ret = 0;
+	int				error;
 	int				total;
 	int				local;
 	struct xfs_attrd_log_item	*done_item = NULL;
@@ -661,13 +661,31 @@ xfs_attri_item_recover(
 	xfs_ilock(ip, XFS_ILOCK_EXCL);
 	xfs_trans_ijoin(tp, ip, 0);
 
-	ret = xfs_xattri_finish_update(attr, done_item);
-	if (ret == -EAGAIN) {
-		/* There's more work to do, so add it to this transaction */
+	error = xfs_xattri_finish_update(attr, done_item);
+	if (error == -EAGAIN) {
+		/*
+		 * There's more work to do, so add the intent item to this
+		 * transaction so that we can continue it later.
+		 */
 		xfs_defer_add(tp, XFS_DEFER_OPS_TYPE_ATTR, &attr->xattri_list);
-	} else
-		error = ret;
+		error = xfs_defer_ops_capture_and_commit(tp, capture_list);
+		if (error)
+			goto out_unlock;
+
+		/*
+		 * The defer capture structure took its own reference to the
+		 * attr leaf buffer and will give that to the continuation
+		 * transaction.  The attr intent struct drives the continuation
+		 * work, so release our refcount on the attr leaf buffer but
+		 * retain the pointer in the intent structure.
+		 */
+		if (attr->xattri_leaf_bp)
+			xfs_buf_relse(attr->xattri_leaf_bp);
 
+		xfs_iunlock(ip, XFS_ILOCK_EXCL);
+		xfs_irele(ip);
+		return 0;
+	}
 	if (error) {
 		xfs_trans_cancel(tp);
 		goto out_unlock;
@@ -678,24 +696,13 @@ xfs_attri_item_recover(
 out_unlock:
 	if (attr->xattri_leaf_bp) {
 		xfs_buf_relse(attr->xattri_leaf_bp);
-
-		/*
-		 * If there's more work to do to complete the attr intent, the
-		 * defer capture structure will have taken its own reference to
-		 * the attr leaf buffer and will give that to the continuation
-		 * transaction.  The attr intent struct drives the continuation
-		 * work, so release our refcount on the attr leaf buffer but
-		 * retain the pointer in the intent structure.
-		 */
-		if (ret != -EAGAIN)
-			attr->xattri_leaf_bp = NULL;
+		attr->xattri_leaf_bp = NULL;
 	}
 
 	xfs_iunlock(ip, XFS_ILOCK_EXCL);
 	xfs_irele(ip);
 out:
-	if (ret != -EAGAIN)
-		xfs_attr_free_item(attr);
+	xfs_attr_free_item(attr);
 	return error;
 }
 
-- 
GitLab


From 3fdd4ef444f99d25f524e68777d210d453757698 Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Mon, 20 Jun 2022 11:20:44 +0800
Subject: [PATCH 1203/1731] arm64: dts: imx8mp: correct clock of pgc_ispdwp

The deprecated DIV clk is previously part of the ISP composite clk, but
there is still one child clk(IMX8MP_CLK_MEDIA_ISP_ROOT) sourcing from
IMX8MP_CLK_MEDIA_ISP( previously IMX8MP_CLK_MEDIA_ISP_DIV)

So IMX8MP_CLK_MEDIA_ISP_ROOT should be used, not IMX8MP_CLK_MEDIA_ISP_DIV.

Fixes: 9d89189d5227 ("arm64: dts: imx8mp: Add MEDIAMIX power domains")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index d9542dfff83fb..410d0d5e6f1e5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -595,7 +595,7 @@
 					pgc_ispdwp: power-domain@18 {
 						#power-domain-cells = <0>;
 						reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
-						clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>;
+						clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
 					};
 				};
 			};
-- 
GitLab


From d63eae6747eb8b3192e89712f6553c6aa162f872 Mon Sep 17 00:00:00 2001
From: Gayatri Kammela <gayatri.kammela@linux.intel.com>
Date: Tue, 14 Jun 2022 17:27:51 -0700
Subject: [PATCH 1204/1731] platform/x86: intel/pmc: Add Alder Lake N support
 to PMC core driver

Add Alder Lake N (ADL-N) to the list of the platforms that Intel's
PMC core driver supports. Alder Lake N reuses all the TigerLake PCH IPs.

Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: David E. Box <david.e.box@linux.intel.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@linux.intel.com>
Reviewed-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
Link: https://lore.kernel.org/r/20220615002751.3371730-1-gayatri.kammela@linux.intel.com
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 drivers/platform/x86/intel/pmc/core.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
index 40183bda7894a..a1fe1e0dcf4a5 100644
--- a/drivers/platform/x86/intel/pmc/core.c
+++ b/drivers/platform/x86/intel/pmc/core.c
@@ -1911,6 +1911,7 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = {
 	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,	&icl_reg_map),
 	X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE,		&tgl_reg_map),
 	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,		&tgl_reg_map),
+	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,		&tgl_reg_map),
 	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,		&adl_reg_map),
 	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,        &tgl_reg_map),
 	{}
-- 
GitLab


From 79e90ca02d7d45898c52fd8523cd4a2a304e409c Mon Sep 17 00:00:00 2001
From: Dan Carpenter <dan.carpenter@oracle.com>
Date: Wed, 15 Jun 2022 11:11:07 +0300
Subject: [PATCH 1205/1731] platform/mellanox: nvsw-sn2201: fix error code in
 nvsw_sn2201_create_static_devices()

This should return PTR_ERR() instead of IS_ERR().  Also "dev->client"
has been set to NULL by this point so it returns 0/success so preserve
the error code earlier.

Fixes: 662f24826f95 ("platform/mellanox: Add support for new SN2201 system")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Michael Shych <michaelsh@nvidia.com>
Link: https://lore.kernel.org/r/YqmUGwmPK7cPolk/@kili
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 drivers/platform/mellanox/nvsw-sn2201.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/platform/mellanox/nvsw-sn2201.c b/drivers/platform/mellanox/nvsw-sn2201.c
index 2923daf63b75d..7b9c107c17ce6 100644
--- a/drivers/platform/mellanox/nvsw-sn2201.c
+++ b/drivers/platform/mellanox/nvsw-sn2201.c
@@ -890,6 +890,7 @@ nvsw_sn2201_create_static_devices(struct nvsw_sn2201 *nvsw_sn2201,
 				  int size)
 {
 	struct mlxreg_hotplug_device *dev = devs;
+	int ret;
 	int i;
 
 	/* Create I2C static devices. */
@@ -901,6 +902,7 @@ nvsw_sn2201_create_static_devices(struct nvsw_sn2201 *nvsw_sn2201,
 				dev->nr, dev->brdinfo->addr);
 
 			dev->adapter = NULL;
+			ret = PTR_ERR(dev->client);
 			goto fail_create_static_devices;
 		}
 	}
@@ -914,7 +916,7 @@ fail_create_static_devices:
 		dev->client = NULL;
 		dev->adapter = NULL;
 	}
-	return IS_ERR(dev->client);
+	return ret;
 }
 
 static void nvsw_sn2201_destroy_static_devices(struct nvsw_sn2201 *nvsw_sn2201,
-- 
GitLab


From d2f33f0c3ad7b0d5262d9b986f1353265fad7a08 Mon Sep 17 00:00:00 2001
From: Jean Delvare <jdelvare@suse.de>
Date: Tue, 21 Jun 2022 15:55:11 +0200
Subject: [PATCH 1206/1731] platform/x86: thinkpad_acpi: Fix a memory leak of
 EFCH MMIO resource

Unlike release_mem_region(), a call to release_resource() does not
free the resource, so it has to be freed explicitly to avoid a memory
leak.

Signed-off-by: Jean Delvare <jdelvare@suse.de>
Fixes: 455cd867b85b ("platform/x86: thinkpad_acpi: Add a s2idle resume quirk for a number of laptops")
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Henrique de Moraes Holschuh <hmh@hmh.eng.br>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Mark Gross <markgross@kernel.org>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20220621155511.5b266395@endymion.delvare
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 drivers/platform/x86/thinkpad_acpi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/platform/x86/thinkpad_acpi.c b/drivers/platform/x86/thinkpad_acpi.c
index e6cb4a14cdd47..aa6ffeaa39329 100644
--- a/drivers/platform/x86/thinkpad_acpi.c
+++ b/drivers/platform/x86/thinkpad_acpi.c
@@ -4529,6 +4529,7 @@ static void thinkpad_acpi_amd_s2idle_restore(void)
 	iounmap(addr);
 cleanup_resource:
 	release_resource(res);
+	kfree(res);
 }
 
 static struct acpi_s2idle_dev_ops thinkpad_acpi_s2idle_dev_ops = {
-- 
GitLab


From b10ef5f2ddb3a5a22ac0936c8d91a50ac5e55e77 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <festevam@denx.de>
Date: Tue, 21 Jun 2022 13:45:05 -0300
Subject: [PATCH 1207/1731] ARM: mxs_defconfig: Enable the framebuffer

Currently, when booting Linux on a imx28-evk board there is
no display activity.

Enable CONFIG_FB which is nowadays required for CONFIG_DRM_PANEL_LVDS,
CONFIG_DRM_PANEL_SIMPLE, CONFIG_DRM_PANEL_SEIKO_43WVF1G,
CONFIG_FB_MODE_HELPERS, CONFIG_BACKLIGHT_PWM, CONFIG_BACKLIGHT_GPIO,
CONFIG_FRAMEBUFFER_CONSOLE, CONFIG_LOGO, CONFIG_FONTS, CONFIG_FONT_8x8
and CONFIG_FONT_8x16.

Based on commit c54467482ffd ("ARM: imx_v6_v7_defconfig: enable fb").

Fixes: f611b1e7624c ("drm: Avoid circular dependencies for CONFIG_FB")
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 arch/arm/configs/mxs_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index ca32446b187f5..f53086ddc48b0 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -93,6 +93,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_DRM=y
 CONFIG_DRM_PANEL_SEIKO_43WVF1G=y
 CONFIG_DRM_MXSFB=y
+CONFIG_FB=y
 CONFIG_FB_MODE_HELPERS=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
-- 
GitLab


From 01785f1f156511c4f285786b4192245d4f476bf1 Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Wed, 22 Jun 2022 14:13:57 +0800
Subject: [PATCH 1208/1731] arm64: dts: imx8mp-evk: correct mmc pad settings

According to RM bit layout, BIT3 and BIT0 are reserved.
  8  7   6   5   4   3  2 1  0
 PE HYS PUE ODE FSEL X  DSE  X

Not set reserved bit.

Fixes: 9e847693c6f3 ("arm64: dts: freescale: Add i.MX8MP EVK board support")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 4c3ac4214a2cd..f31cf778890d8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -500,7 +500,7 @@
 
 	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41
+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
 		>;
 	};
 
@@ -525,7 +525,7 @@
 			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
 			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
 			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
-			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0
 		>;
 	};
 
@@ -537,7 +537,7 @@
 			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4
 			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4
 			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4
-			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
 		>;
 	};
 
@@ -549,7 +549,7 @@
 			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6
 			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6
 			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6
-			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
 		>;
 	};
 
-- 
GitLab


From 2d4fb72b681205eed4553d8802632bd3270be3ba Mon Sep 17 00:00:00 2001
From: Sherry Sun <sherry.sun@nxp.com>
Date: Wed, 22 Jun 2022 14:13:58 +0800
Subject: [PATCH 1209/1731] arm64: dts: imx8mp-evk: correct the uart2 pinctl
 value

According to the IOMUXC_SW_PAD_CTL_PAD_UART2_RXD/TXD register define in
imx8mp RM, bit0 and bit3 are reserved, and the uart2 rx/tx pin should
enable the pull up, so need to set bit8 to 1. The original pinctl value
0x49 is incorrect and needs to be changed to 0x140, same as uart1 and
uart3.

Fixes: 9e847693c6f3 ("arm64: dts: freescale: Add i.MX8MP EVK board support")
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index f31cf778890d8..4ba31fc5d0a5c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -506,8 +506,8 @@
 
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
-			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x49
-			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x49
+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140
 		>;
 	};
 
-- 
GitLab


From b838582ab8d5fb11b2c0275056a9f34e1d94fece Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Wed, 22 Jun 2022 14:13:59 +0800
Subject: [PATCH 1210/1731] arm64: dts: imx8mp-evk: correct gpio-led pad
 settings

0x19 is not a valid setting. According to RM bit layout,
BIT3 and BIT0 are reserved.
  8  7   6   5   4   3  2 1  0
 PE HYS PUE ODE FSEL X  DSE  X

Correct setting with PE PUE set, DSE set to 0.

Fixes: 50d336b12f34 ("arm64: dts: imx8mp-evk: Add GPIO LED support")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 4ba31fc5d0a5c..4ff75c4cbddc8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -461,7 +461,7 @@
 
 	pinctrl_gpio_led: gpioledgrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x19
+			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x140
 		>;
 	};
 
-- 
GitLab


From e2c00820a99c55c9bb40642d5818a904a1e0d664 Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Wed, 22 Jun 2022 14:14:00 +0800
Subject: [PATCH 1211/1731] arm64: dts: imx8mp-evk: correct vbus pad settings

0x19 is not a valid setting. According to RM bit layout, BIT3 and BIT0
are reserved.
  8  7   6   5   4   3  2 1  0
 PE HYS PUE ODE FSEL X  DSE  X

Not set reserved bit.

Fixes: 43da4f92a611 ("arm64: dts: imx8mp-evk: enable usb1 as host mode")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 4ff75c4cbddc8..a28ce8af61bdd 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -513,7 +513,7 @@
 
 	pinctrl_usb1_vbus: usb1grp {
 		fsl,pins = <
-			MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR	0x19
+			MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR	0x10
 		>;
 	};
 
-- 
GitLab


From e6e1bc0ec9e8ad212fa46d8878a6e17cd31fdf7b Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Wed, 22 Jun 2022 14:14:01 +0800
Subject: [PATCH 1212/1731] arm64: dts: imx8mp-evk: correct eqos pad settings

According to RM bit layout, BIT3 and BIT0 are reserved.
 8  7   6   5   4   3  2 1  0
PE HYS PUE ODE FSEL X  DSE  X

Although function is not broken, we should not set reserved bit.

Fixes: dc6d5dc89bad ("arm64: dts: imx8mp-evk: enable EQOS ethernet")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 30 ++++++++++----------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index a28ce8af61bdd..454856bd4f564 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -395,21 +395,21 @@
 &iomuxc {
 	pinctrl_eqos: eqosgrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3
-			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3
-			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91
-			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91
-			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91
-			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91
-			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
-			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91
-			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f
-			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f
-			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f
-			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f
-			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f
-			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
-			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22				0x19
+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2
+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2
+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90
+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90
+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90
+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90
+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x90
+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x16
+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x16
+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x16
+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x16
+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x16
+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22				0x10
 		>;
 	};
 
-- 
GitLab


From 95587ecfcf25e1b9e7810ed91df084d823ee8023 Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Wed, 22 Jun 2022 14:14:02 +0800
Subject: [PATCH 1213/1731] arm64: dts: imx8mp-evk: correct vbus pad settings

According to RM bit layout, BIT3 and BIT0 are reserved.
  8  7   6   5   4   3  2 1  0
 PE HYS PUE ODE FSEL X  DSE  X

Not set reserved bit.

Fixes: 9e847693c6f3 ("arm64: dts: freescale: Add i.MX8MP EVK board support")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 30 ++++++++++----------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 454856bd4f564..c244a5cd1ac02 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -415,21 +415,21 @@
 
 	pinctrl_fec: fecgrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
-			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
-			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
-			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
-			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
-			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
-			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
-			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
-			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
-			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
-			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
-			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
-			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
-			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
-			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x19
+			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x2
+			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x2
+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x90
+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x90
+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x90
+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x90
+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x90
+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90
+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x16
+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x16
+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x16
+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x16
+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x16
+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x16
+			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x10
 		>;
 	};
 
-- 
GitLab


From 8c214b78e149dc7209e38a031292fe21d7017561 Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Wed, 22 Jun 2022 14:14:03 +0800
Subject: [PATCH 1214/1731] arm64: dts: imx8mp-evk: correct I2C5 pad settings

According to RM bit layout, BIT3 and BIT0 are reserved.
 8  7   6   5   4   3  2 1  0
PE HYS PUE ODE FSEL X  DSE  X

Although function is not broken, we should not set reserved bit.

Fixes: 8134822db08d ("arm64: dts: imx8mp-evk: add support for I2C5")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index c244a5cd1ac02..b2fd0af5d1e1f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -481,8 +481,8 @@
 
 	pinctrl_i2c5: i2c5grp {
 		fsl,pins = <
-			MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA         0x400001c3
-			MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL         0x400001c3
+			MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA         0x400001c2
+			MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL         0x400001c2
 		>;
 	};
 
-- 
GitLab


From 05a7f43478e890513d571f36660bfedc1482a588 Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Wed, 22 Jun 2022 14:14:04 +0800
Subject: [PATCH 1215/1731] arm64: dts: imx8mp-evk: correct I2C1 pad settings

According to RM bit layout, BIT3 and BIT0 are reserved.
 8  7   6   5   4   3  2 1  0
PE HYS PUE ODE FSEL X  DSE  X

Although function is not broken, we should not set reserved bit.

Fixes: 5497bc2a2bff ("arm64: dts: imx8mp-evk: Add PMIC device")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index b2fd0af5d1e1f..fb858a6eb0e58 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -467,8 +467,8 @@
 
 	pinctrl_i2c1: i2c1grp {
 		fsl,pins = <
-			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c3
-			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c3
+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2
+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2
 		>;
 	};
 
-- 
GitLab


From 0836de513ebaae5f03014641eac996290d67493d Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Wed, 22 Jun 2022 14:14:05 +0800
Subject: [PATCH 1216/1731] arm64: dts: imx8mp-evk: correct I2C3 pad settings

According to RM bit layout, BIT3 and BIT0 are reserved.
 8  7   6   5   4   3  2 1  0
PE HYS PUE ODE FSEL X  DSE  X

Although function is not broken, we should not set reserved bit.

Fixes: 5e4a67ff7f69 ("arm64: dts: imx8mp-evk: Add i2c3 support")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index fb858a6eb0e58..9a4de739e6a2a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -474,8 +474,8 @@
 
 	pinctrl_i2c3: i2c3grp {
 		fsl,pins = <
-			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c3
-			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c3
+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2
+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2
 		>;
 	};
 
-- 
GitLab


From 843af59e577021bd9c975b7a17c237394f26b929 Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Wed, 22 Jun 2022 14:14:06 +0800
Subject: [PATCH 1217/1731] arm64: dts: imx8mp-venice-gw74xx: correct pad
 settings

According to RM bit layout, BIT3 and BIT0 are reserved.
  8  7   6   5   4   3  2 1  0
 PE HYS PUE ODE FSEL X  DSE  X

Should not set reserved bit.

Fixes: 7899eb6cb15d ("arm64: dts: imx: Add i.MX8M Plus Gateworks gw7400 dts support")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 .../dts/freescale/imx8mp-venice-gw74xx.dts    | 116 +++++++++---------
 1 file changed, 58 insertions(+), 58 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
index 101d311476034..521215520a0f4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
@@ -622,15 +622,15 @@
 
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09	0x40000041 /* DIO0 */
-			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11	0x40000041 /* DIO1 */
-			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14	0x40000041 /* M2SKT_OFF# */
-			MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17	0x40000159 /* PCIE1_WDIS# */
-			MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18	0x40000159 /* PCIE2_WDIS# */
-			MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14	0x40000159 /* PCIE3_WDIS# */
-			MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06	0x40000041 /* M2SKT_RST# */
-			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18	0x40000159 /* M2SKT_WDIS# */
-			MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00	0x40000159 /* M2SKT_GDIS# */
+			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09	0x40000040 /* DIO0 */
+			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11	0x40000040 /* DIO1 */
+			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14	0x40000040 /* M2SKT_OFF# */
+			MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17	0x40000150 /* PCIE1_WDIS# */
+			MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18	0x40000150 /* PCIE2_WDIS# */
+			MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14	0x40000150 /* PCIE3_WDIS# */
+			MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06	0x40000040 /* M2SKT_RST# */
+			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18	0x40000150 /* M2SKT_WDIS# */
+			MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00	0x40000150 /* M2SKT_GDIS# */
 			MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01	0x40000104 /* UART_TERM */
 			MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31	0x40000104 /* UART_RS485 */
 			MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00	0x40000104 /* UART_HALF */
@@ -639,47 +639,47 @@
 
 	pinctrl_accel: accelgrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07	0x159
+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07	0x150
 		>;
 	};
 
 	pinctrl_eqos: eqosgrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3
-			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3
-			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x91
-			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x91
-			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x91
-			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x91
-			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
-			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x91
-			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x1f
-			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x1f
-			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x1f
-			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x1f
-			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x1f
-			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
-			MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30		0x141 /* RST# */
-			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0x159 /* IRQ# */
+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2
+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2
+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x90
+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x90
+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x90
+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x90
+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90
+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x16
+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x16
+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x16
+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x16
+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x16
+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
+			MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30		0x140 /* RST# */
+			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0x150 /* IRQ# */
 		>;
 	};
 
 	pinctrl_fec: fecgrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
-			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
-			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
-			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
-			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
-			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
-			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
-			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
-			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
-			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
-			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
-			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
-			MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN	0x141
-			MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT	0x141
+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x90
+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x90
+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x90
+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x90
+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x90
+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90
+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x16
+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x16
+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x16
+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x16
+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x16
+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x16
+			MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN	0x140
+			MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT	0x140
 		>;
 	};
 
@@ -692,61 +692,61 @@
 
 	pinctrl_gsc: gscgrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20	0x159
+			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20	0x150
 		>;
 	};
 
 	pinctrl_i2c1: i2c1grp {
 		fsl,pins = <
-			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c3
-			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c3
+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2
+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2
 		>;
 	};
 
 	pinctrl_i2c2: i2c2grp {
 		fsl,pins = <
-			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c3
-			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c3
+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2
+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2
 		>;
 	};
 
 	pinctrl_i2c3: i2c3grp {
 		fsl,pins = <
-			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c3
-			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c3
+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2
+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2
 		>;
 	};
 
 	pinctrl_i2c4: i2c4grp {
 		fsl,pins = <
-			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL		0x400001c3
-			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA		0x400001c3
+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL		0x400001c2
+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA		0x400001c2
 		>;
 	};
 
 	pinctrl_ksz: kszgrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x159 /* IRQ# */
-			MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02	0x141 /* RST# */
+			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x150 /* IRQ# */
+			MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02	0x140 /* RST# */
 		>;
 	};
 
 	pinctrl_gpio_leds: ledgrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15	0x19
-			MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16	0x19
+			MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15	0x10
+			MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16	0x10
 		>;
 	};
 
 	pinctrl_pmic: pmicgrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07	0x141
+			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07	0x140
 		>;
 	};
 
 	pinctrl_pps: ppsgrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12	0x141
+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12	0x140
 		>;
 	};
 
@@ -758,13 +758,13 @@
 
 	pinctrl_reg_usb2: regusb2grp {
 		fsl,pins = <
-			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06	0x141
+			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06	0x140
 		>;
 	};
 
 	pinctrl_reg_wifi: regwifigrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09	0x119
+			MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09	0x110
 		>;
 	};
 
@@ -811,7 +811,7 @@
 
 	pinctrl_uart3_gpio: uart3gpiogrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08	0x119
+			MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08	0x110
 		>;
 	};
 
-- 
GitLab


From e266c155bd88e95f9b86379d6b0add6ac6e5452e Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Wed, 22 Jun 2022 14:14:07 +0800
Subject: [PATCH 1218/1731] arm64: dts: imx8mp-phyboard-pollux-rdk: correct
 uart pad settings

BIT3 and BIT0 are reserved bits, should not touch.

Fixes: 846f752866bd ("arm64: dts: imx8mp-phyboard-pollux-rdk: Change debug UART")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
index 984a6b9ded8d7..e340769548972 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
@@ -156,8 +156,8 @@
 
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
-			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x49
-			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x49
+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x40
+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x40
 		>;
 	};
 
-- 
GitLab


From bae4de618efe1c41d34aa2e6cef8b08e46256667 Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Wed, 22 Jun 2022 14:14:08 +0800
Subject: [PATCH 1219/1731] arm64: dts: imx8mp-phyboard-pollux-rdk: correct
 eqos pad settings

BIT3 and BIT0 are reserved bits, should not touch.

Fixes: 6f96852619d5 ("arm64: dts: freescale: Add support EQOS MAC on phyBOARD-Pollux-i.MX8MP")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 .../freescale/imx8mp-phyboard-pollux-rdk.dts  | 28 +++++++++----------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
index e340769548972..cefd3d36f93f3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
@@ -116,20 +116,20 @@
 &iomuxc {
 	pinctrl_eqos: eqosgrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC			0x3
-			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO			0x3
-			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x91
-			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x91
-			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x91
-			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x91
-			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
-			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x91
-			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x1f
-			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x1f
-			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x1f
-			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x1f
-			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x1f
-			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC			0x2
+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO			0x2
+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x90
+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x90
+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x90
+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x90
+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90
+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x16
+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x16
+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x16
+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x16
+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x16
+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
 			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20			0x10
 		>;
 	};
-- 
GitLab


From 242d8ee9111171a6e68249aaff62643c513be6ec Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Wed, 22 Jun 2022 14:14:09 +0800
Subject: [PATCH 1220/1731] arm64: dts: imx8mp-phyboard-pollux-rdk: correct
 i2c2 & mmc settings

BIT3 and BIT0 are reserved bits, should not touch.

Fixes: 88f7f6bcca37 ("arm64: dts: freescale: Add support for phyBOARD-Pollux-i.MX8MP")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
index cefd3d36f93f3..6aa720bafe289 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
@@ -136,21 +136,21 @@
 
 	pinctrl_i2c2: i2c2grp {
 		fsl,pins = <
-			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c3
-			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c3
+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2
+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2
 		>;
 	};
 
 	pinctrl_i2c2_gpio: i2c2gpiogrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x1e3
-			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x1e3
+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x1e2
+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x1e2
 		>;
 	};
 
 	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41
+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
 		>;
 	};
 
@@ -175,7 +175,7 @@
 			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
 			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
 			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
-			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0
 		>;
 	};
 
@@ -187,7 +187,7 @@
 			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4
 			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4
 			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4
-			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0
 		>;
 	};
 
@@ -199,7 +199,7 @@
 			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6
 			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6
 			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6
-			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0
 		>;
 	};
 };
-- 
GitLab


From 8630354f42bef90f51e003a7ce62b69aceb735ca Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Wed, 22 Jun 2022 14:14:10 +0800
Subject: [PATCH 1221/1731] arm64: dts: imx8mp-icore-mx8mp-edim2.2: correct pad
 settings

BIT3 and BIT0 are reserved bits, should not touch.

Fixes: aec8ad34f7f2 ("arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
 .../freescale/imx8mp-icore-mx8mp-edimm2.2.dts | 40 +++++++++----------
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts
index 70a701a624a67..dd703b6a5e17c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts
@@ -110,28 +110,28 @@
 &iomuxc {
 	pinctrl_eqos: eqosgrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3
-			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3
-			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91
-			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91
-			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91
-			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91
-			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
-			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91
-			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f
-			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f
-			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f
-			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f
-			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f
-			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
-			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07				0x19
+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2
+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2
+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90
+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90
+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90
+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90
+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x90
+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x16
+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x16
+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x16
+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x16
+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x16
+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
+			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07				0x10
 		>;
 	};
 
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
-			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x49
-			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x49
+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x40
+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x40
 		>;
 	};
 
@@ -151,7 +151,7 @@
 			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
 			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
 			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
-			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0
 		>;
 	};
 
@@ -163,13 +163,13 @@
 
 	pinctrl_reg_usb1: regusb1grp {
 		fsl,pins = <
-			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14	0x19
+			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14	0x10
 		>;
 	};
 
 	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41
+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
 		>;
 	};
 };
-- 
GitLab


From cd4c1e65a32afd003b08ad4aafe1e4d3e4e8e61b Mon Sep 17 00:00:00 2001
From: Andrei Lalaev <andrey.lalaev@gmail.com>
Date: Wed, 25 May 2022 22:04:25 +0300
Subject: [PATCH 1222/1731] pinctrl: sunxi: sunxi_pconf_set: use correct offset

Some Allwinner SoCs have 2 pinctrls (PIO and R_PIO).
Previous implementation used absolute pin numbering and it was incorrect
for R_PIO pinctrl.
It's necessary to take into account the base pin number.

Fixes: 90be64e27621 ("pinctrl: sunxi: implement pin_config_set")
Signed-off-by: Andrei Lalaev <andrey.lalaev@gmail.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220525190423.410609-1-andrey.lalaev@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index d9327d7d56eea..dd928402af997 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -544,6 +544,8 @@ static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 	int i;
 
+	pin -= pctl->desc->pin_base;
+
 	for (i = 0; i < num_configs; i++) {
 		enum pin_config_param param;
 		unsigned long flags;
-- 
GitLab


From 853a7614880231747040cada91d2b8d2e995c51a Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Fri, 24 Jun 2022 15:30:20 +0000
Subject: [PATCH 1223/1731] tunnels: do not assume mac header is set in
 skb_tunnel_check_pmtu()

Recently added debug in commit f9aefd6b2aa3 ("net: warn if mac header
was not set") caught a bug in skb_tunnel_check_pmtu(), as shown
in this syzbot report [1].

In ndo_start_xmit() paths, there is really no need to use skb->mac_header,
because skb->data is supposed to point at it.

[1] WARNING: CPU: 1 PID: 8604 at include/linux/skbuff.h:2784 skb_mac_header_len include/linux/skbuff.h:2784 [inline]
WARNING: CPU: 1 PID: 8604 at include/linux/skbuff.h:2784 skb_tunnel_check_pmtu+0x5de/0x2f90 net/ipv4/ip_tunnel_core.c:413
Modules linked in:
CPU: 1 PID: 8604 Comm: syz-executor.3 Not tainted 5.19.0-rc2-syzkaller-00443-g8720bd951b8e #0
Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011
RIP: 0010:skb_mac_header_len include/linux/skbuff.h:2784 [inline]
RIP: 0010:skb_tunnel_check_pmtu+0x5de/0x2f90 net/ipv4/ip_tunnel_core.c:413
Code: 00 00 00 00 fc ff df 4c 89 fa 48 c1 ea 03 80 3c 02 00 0f 84 b9 fe ff ff 4c 89 ff e8 7c 0f d7 f9 e9 ac fe ff ff e8 c2 13 8a f9 <0f> 0b e9 28 fc ff ff e8 b6 13 8a f9 48 8b 54 24 70 48 b8 00 00 00
RSP: 0018:ffffc90002e4f520 EFLAGS: 00010212
RAX: 0000000000000324 RBX: ffff88804d5fd500 RCX: ffffc90005b52000
RDX: 0000000000040000 RSI: ffffffff87f05e3e RDI: 0000000000000003
RBP: ffffc90002e4f650 R08: 0000000000000003 R09: 000000000000ffff
R10: 000000000000ffff R11: 0000000000000000 R12: 000000000000ffff
R13: 0000000000000000 R14: 000000000000ffcd R15: 000000000000001f
FS: 00007f3babba9700(0000) GS:ffff8880b9b00000(0000) knlGS:0000000000000000
CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 0000000020000080 CR3: 0000000075319000 CR4: 00000000003506e0
DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
Call Trace:
<TASK>
geneve_xmit_skb drivers/net/geneve.c:927 [inline]
geneve_xmit+0xcf8/0x35d0 drivers/net/geneve.c:1107
__netdev_start_xmit include/linux/netdevice.h:4805 [inline]
netdev_start_xmit include/linux/netdevice.h:4819 [inline]
__dev_direct_xmit+0x500/0x730 net/core/dev.c:4309
dev_direct_xmit include/linux/netdevice.h:3007 [inline]
packet_direct_xmit+0x1b8/0x2c0 net/packet/af_packet.c:282
packet_snd net/packet/af_packet.c:3073 [inline]
packet_sendmsg+0x21f4/0x55d0 net/packet/af_packet.c:3104
sock_sendmsg_nosec net/socket.c:714 [inline]
sock_sendmsg+0xcf/0x120 net/socket.c:734
____sys_sendmsg+0x6eb/0x810 net/socket.c:2489
___sys_sendmsg+0xf3/0x170 net/socket.c:2543
__sys_sendmsg net/socket.c:2572 [inline]
__do_sys_sendmsg net/socket.c:2581 [inline]
__se_sys_sendmsg net/socket.c:2579 [inline]
__x64_sys_sendmsg+0x132/0x220 net/socket.c:2579
do_syscall_x64 arch/x86/entry/common.c:50 [inline]
do_syscall_64+0x35/0xb0 arch/x86/entry/common.c:80
entry_SYSCALL_64_after_hwframe+0x46/0xb0
RIP: 0033:0x7f3baaa89109
Code: ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 c7 c1 b8 ff ff ff f7 d8 64 89 01 48
RSP: 002b:00007f3babba9168 EFLAGS: 00000246 ORIG_RAX: 000000000000002e
RAX: ffffffffffffffda RBX: 00007f3baab9bf60 RCX: 00007f3baaa89109
RDX: 0000000000000000 RSI: 0000000020000a00 RDI: 0000000000000003
RBP: 00007f3baaae305d R08: 0000000000000000 R09: 0000000000000000
R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000000
R13: 00007ffe74f2543f R14: 00007f3babba9300 R15: 0000000000022000
</TASK>

Fixes: 4cb47a8644cc ("tunnels: PMTU discovery support for directly bridged IP packets")
Reported-by: syzbot <syzkaller@googlegroups.com>
Signed-off-by: Eric Dumazet <edumazet@google.com>
Cc: Stefano Brivio <sbrivio@redhat.com>
Reviewed-by: Stefano Brivio <sbrivio@redhat.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/ipv4/ip_tunnel_core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/net/ipv4/ip_tunnel_core.c b/net/ipv4/ip_tunnel_core.c
index 6b2dc7b2b6127..cc1caab4a6549 100644
--- a/net/ipv4/ip_tunnel_core.c
+++ b/net/ipv4/ip_tunnel_core.c
@@ -410,7 +410,7 @@ int skb_tunnel_check_pmtu(struct sk_buff *skb, struct dst_entry *encap_dst,
 	u32 mtu = dst_mtu(encap_dst) - headroom;
 
 	if ((skb_is_gso(skb) && skb_gso_validate_network_len(skb, mtu)) ||
-	    (!skb_is_gso(skb) && (skb->len - skb_mac_header_len(skb)) <= mtu))
+	    (!skb_is_gso(skb) && (skb->len - skb_network_offset(skb)) <= mtu))
 		return 0;
 
 	skb_dst_update_pmtu_no_confirm(skb, mtu);
-- 
GitLab


From cb8092d70a6f5f01ec1490fce4d35efed3ed996c Mon Sep 17 00:00:00 2001
From: Xin Long <lucien.xin@gmail.com>
Date: Fri, 24 Jun 2022 12:24:31 -0400
Subject: [PATCH 1224/1731] tipc: move bc link creation back to
 tipc_node_create

Shuang Li reported a NULL pointer dereference crash:

  [] BUG: kernel NULL pointer dereference, address: 0000000000000068
  [] RIP: 0010:tipc_link_is_up+0x5/0x10 [tipc]
  [] Call Trace:
  []  <IRQ>
  []  tipc_bcast_rcv+0xa2/0x190 [tipc]
  []  tipc_node_bc_rcv+0x8b/0x200 [tipc]
  []  tipc_rcv+0x3af/0x5b0 [tipc]
  []  tipc_udp_recv+0xc7/0x1e0 [tipc]

It was caused by the 'l' passed into tipc_bcast_rcv() is NULL. When it
creates a node in tipc_node_check_dest(), after inserting the new node
into hashtable in tipc_node_create(), it creates the bc link. However,
there is a gap between this insert and bc link creation, a bc packet
may come in and get the node from the hashtable then try to dereference
its bc link, which is NULL.

This patch is to fix it by moving the bc link creation before inserting
into the hashtable.

Note that for a preliminary node becoming "real", the bc link creation
should also be called before it's rehashed, as we don't create it for
preliminary nodes.

Fixes: 4cbf8ac2fe5a ("tipc: enable creating a "preliminary" node")
Reported-by: Shuang Li <shuali@redhat.com>
Signed-off-by: Xin Long <lucien.xin@gmail.com>
Acked-by: Jon Maloy <jmaloy@redhat.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/tipc/node.c | 41 ++++++++++++++++++++++-------------------
 1 file changed, 22 insertions(+), 19 deletions(-)

diff --git a/net/tipc/node.c b/net/tipc/node.c
index 6ef95ce565bd3..b48d97cbbe29c 100644
--- a/net/tipc/node.c
+++ b/net/tipc/node.c
@@ -472,8 +472,8 @@ struct tipc_node *tipc_node_create(struct net *net, u32 addr, u8 *peer_id,
 				   bool preliminary)
 {
 	struct tipc_net *tn = net_generic(net, tipc_net_id);
+	struct tipc_link *l, *snd_l = tipc_bc_sndlink(net);
 	struct tipc_node *n, *temp_node;
-	struct tipc_link *l;
 	unsigned long intv;
 	int bearer_id;
 	int i;
@@ -488,6 +488,16 @@ struct tipc_node *tipc_node_create(struct net *net, u32 addr, u8 *peer_id,
 			goto exit;
 		/* A preliminary node becomes "real" now, refresh its data */
 		tipc_node_write_lock(n);
+		if (!tipc_link_bc_create(net, tipc_own_addr(net), addr, peer_id, U16_MAX,
+					 tipc_link_min_win(snd_l), tipc_link_max_win(snd_l),
+					 n->capabilities, &n->bc_entry.inputq1,
+					 &n->bc_entry.namedq, snd_l, &n->bc_entry.link)) {
+			pr_warn("Broadcast rcv link refresh failed, no memory\n");
+			tipc_node_write_unlock_fast(n);
+			tipc_node_put(n);
+			n = NULL;
+			goto exit;
+		}
 		n->preliminary = false;
 		n->addr = addr;
 		hlist_del_rcu(&n->hash);
@@ -567,7 +577,16 @@ update:
 	n->signature = INVALID_NODE_SIG;
 	n->active_links[0] = INVALID_BEARER_ID;
 	n->active_links[1] = INVALID_BEARER_ID;
-	n->bc_entry.link = NULL;
+	if (!preliminary &&
+	    !tipc_link_bc_create(net, tipc_own_addr(net), addr, peer_id, U16_MAX,
+				 tipc_link_min_win(snd_l), tipc_link_max_win(snd_l),
+				 n->capabilities, &n->bc_entry.inputq1,
+				 &n->bc_entry.namedq, snd_l, &n->bc_entry.link)) {
+		pr_warn("Broadcast rcv link creation failed, no memory\n");
+		kfree(n);
+		n = NULL;
+		goto exit;
+	}
 	tipc_node_get(n);
 	timer_setup(&n->timer, tipc_node_timeout, 0);
 	/* Start a slow timer anyway, crypto needs it */
@@ -1155,7 +1174,7 @@ void tipc_node_check_dest(struct net *net, u32 addr,
 			  bool *respond, bool *dupl_addr)
 {
 	struct tipc_node *n;
-	struct tipc_link *l, *snd_l;
+	struct tipc_link *l;
 	struct tipc_link_entry *le;
 	bool addr_match = false;
 	bool sign_match = false;
@@ -1175,22 +1194,6 @@ void tipc_node_check_dest(struct net *net, u32 addr,
 		return;
 
 	tipc_node_write_lock(n);
-	if (unlikely(!n->bc_entry.link)) {
-		snd_l = tipc_bc_sndlink(net);
-		if (!tipc_link_bc_create(net, tipc_own_addr(net),
-					 addr, peer_id, U16_MAX,
-					 tipc_link_min_win(snd_l),
-					 tipc_link_max_win(snd_l),
-					 n->capabilities,
-					 &n->bc_entry.inputq1,
-					 &n->bc_entry.namedq, snd_l,
-					 &n->bc_entry.link)) {
-			pr_warn("Broadcast rcv link creation failed, no mem\n");
-			tipc_node_write_unlock_fast(n);
-			tipc_node_put(n);
-			return;
-		}
-	}
 
 	le = &n->links[b->identity];
 
-- 
GitLab


From 75c8f430d8596cf16634337fec8aec50e7b0feed Mon Sep 17 00:00:00 2001
From: Vincent Guittot <vincent.guittot@linaro.org>
Date: Fri, 24 Jun 2022 09:45:49 +0200
Subject: [PATCH 1225/1731] firmware: arm_scmi: Fix response size warning for
 OPTEE transport

Some protocols check the response size with the expected value but optee
shared memory doesn't return such size whereas it is available in the
optee output buffer.

As an example, the base protocol compares the response size with the
expected result when requesting the list of protocol which triggers a
warning with optee shared memory:

arm-scmi firmware:scmi0: Malformed reply - real_sz:116  calc_sz:4  (loop_num_ret:4)

Save the output buffer length and use it when fetching the answer.

Link: https://lore.kernel.org/r/20220624074549.3298-1-vincent.guittot@linaro.org
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Cristian Marussi <cristian.marussi@arm.com>
Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
 drivers/firmware/arm_scmi/optee.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/firmware/arm_scmi/optee.c b/drivers/firmware/arm_scmi/optee.c
index b503c22cfd326..8abace56b9588 100644
--- a/drivers/firmware/arm_scmi/optee.c
+++ b/drivers/firmware/arm_scmi/optee.c
@@ -117,6 +117,7 @@ struct scmi_optee_channel {
 	u32 channel_id;
 	u32 tee_session;
 	u32 caps;
+	u32 rx_len;
 	struct mutex mu;
 	struct scmi_chan_info *cinfo;
 	union {
@@ -302,6 +303,9 @@ static int invoke_process_msg_channel(struct scmi_optee_channel *channel, size_t
 		return -EIO;
 	}
 
+	/* Save response size */
+	channel->rx_len = param[2].u.memref.size;
+
 	return 0;
 }
 
@@ -353,6 +357,7 @@ static int setup_dynamic_shmem(struct device *dev, struct scmi_optee_channel *ch
 	shbuf = tee_shm_get_va(channel->tee_shm, 0);
 	memset(shbuf, 0, msg_size);
 	channel->req.msg = shbuf;
+	channel->rx_len = msg_size;
 
 	return 0;
 }
@@ -508,7 +513,7 @@ static void scmi_optee_fetch_response(struct scmi_chan_info *cinfo,
 	struct scmi_optee_channel *channel = cinfo->transport_info;
 
 	if (channel->tee_shm)
-		msg_fetch_response(channel->req.msg, SCMI_OPTEE_MAX_MSG_SIZE, xfer);
+		msg_fetch_response(channel->req.msg, channel->rx_len, xfer);
 	else
 		shmem_fetch_response(channel->req.shmem, xfer);
 }
-- 
GitLab


From 138c2fca6f408f397ea8fbbbf33203f244d96e01 Mon Sep 17 00:00:00 2001
From: Anshuman Gupta <anshuman.gupta@intel.com>
Date: Thu, 16 Jun 2022 17:52:49 +0530
Subject: [PATCH 1226/1731] drm/i915/dgfx: Disable d3cold at gfx root port

Currently i915 disables d3cold for i915 pci dev.
This blocks D3 for i915 gfx pci upstream bridge (VSP).
Let's disable d3cold at gfx root port to make sure that
i915 gfx VSP can transition to D3 to save some power.

We don't need to disable/enable d3cold in rpm, s2idle
suspend/resume handlers. Disabling/Enabling d3cold at
gfx root port in probe/remove phase is sufficient.

Fixes: 1a085e23411d ("drm/i915: Disable D3Cold in s2idle and runtime pm")
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Reviewed-by: Badal Nilawar <badal.nilawar@intel.com>
Acked-by:: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220616122249.5007-1-anshuman.gupta@intel.com
---
 drivers/gpu/drm/i915/i915_driver.c | 34 +++++++++++++-----------------
 1 file changed, 15 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index be95f3d0c3d03..9d0187ee4c7e2 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -535,6 +535,7 @@ mask_err:
 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 {
 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+	struct pci_dev *root_pdev;
 	int ret;
 
 	if (i915_inject_probe_failure(dev_priv))
@@ -646,6 +647,15 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 
 	intel_bw_init_hw(dev_priv);
 
+	/*
+	 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
+	 * This should be totally removed when we handle the pci states properly
+	 * on runtime PM and on s2idle cases.
+	 */
+	root_pdev = pcie_find_root_port(pdev);
+	if (root_pdev)
+		pci_d3cold_disable(root_pdev);
+
 	return 0;
 
 err_msi:
@@ -669,11 +679,16 @@ err_perf:
 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
 {
 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+	struct pci_dev *root_pdev;
 
 	i915_perf_fini(dev_priv);
 
 	if (pdev->msi_enabled)
 		pci_disable_msi(pdev);
+
+	root_pdev = pcie_find_root_port(pdev);
+	if (root_pdev)
+		pci_d3cold_enable(root_pdev);
 }
 
 /**
@@ -1191,14 +1206,6 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
 		goto out;
 	}
 
-	/*
-	 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
-	 * This should be totally removed when we handle the pci states properly
-	 * on runtime PM and on s2idle cases.
-	 */
-	if (suspend_to_idle(dev_priv))
-		pci_d3cold_disable(pdev);
-
 	pci_disable_device(pdev);
 	/*
 	 * During hibernation on some platforms the BIOS may try to access
@@ -1363,8 +1370,6 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
 	pci_set_master(pdev);
 
-	pci_d3cold_enable(pdev);
-
 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
 	ret = vlv_resume_prepare(dev_priv, false);
@@ -1541,7 +1546,6 @@ static int intel_runtime_suspend(struct device *kdev)
 {
 	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
 	struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
-	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 	int ret;
 
 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
@@ -1587,12 +1591,6 @@ static int intel_runtime_suspend(struct device *kdev)
 		drm_err(&dev_priv->drm,
 			"Unclaimed access detected prior to suspending\n");
 
-	/*
-	 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
-	 * This should be totally removed when we handle the pci states properly
-	 * on runtime PM and on s2idle cases.
-	 */
-	pci_d3cold_disable(pdev);
 	rpm->suspended = true;
 
 	/*
@@ -1631,7 +1629,6 @@ static int intel_runtime_resume(struct device *kdev)
 {
 	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
 	struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
-	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 	int ret;
 
 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
@@ -1644,7 +1641,6 @@ static int intel_runtime_resume(struct device *kdev)
 
 	intel_opregion_notify_adapter(dev_priv, PCI_D0);
 	rpm->suspended = false;
-	pci_d3cold_enable(pdev);
 	if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
 		drm_dbg(&dev_priv->drm,
 			"Unclaimed access during suspend, bios?\n");
-- 
GitLab


From 563aaf4a928def2d36d1b3de0a4b515e2477b4da Mon Sep 17 00:00:00 2001
From: Matthew Auld <matthew.auld@intel.com>
Date: Wed, 22 Jun 2022 16:59:19 +0100
Subject: [PATCH 1227/1731] drm/i915: tweak the ordering in
 cpu_write_needs_clflush
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

For imported dma-buf objects we leave the object as cache_coherent = 0
across all platforms, which is reasonable given that have no clue what
the memory underneath is, and its not like the driver can ever manually
clflush the pages anyway (like with i915_gem_clflush_object) for such
objects. However on discrete we choose to treat cache_dirty = true as a
programmer error, leading to a warning. The simplest fix looks to be to
just change the ordering in cpu_write_needs_clflush to prevent ever
setting cache_dirty for dma-buf objects on discrete.

Fixes: d028a7690d87 ("drm/i915/dmabuf: Fix prime_mmap to work when using LMEM")
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5266
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220622155919.355081-1-matthew.auld@intel.com
---
 drivers/gpu/drm/i915/gem/i915_gem_domain.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 3e5d6057b3ef9..1674b0c5802bf 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -35,12 +35,12 @@ bool i915_gem_cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
 	if (obj->cache_dirty)
 		return false;
 
-	if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE))
-		return true;
-
 	if (IS_DGFX(i915))
 		return false;
 
+	if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE))
+		return true;
+
 	/* Currently in use by HW (display engine)? Keep flushed. */
 	return i915_gem_object_is_framebuffer(obj);
 }
-- 
GitLab


From 50c0ada627f56c92f5953a8bf9158b045ad026a1 Mon Sep 17 00:00:00 2001
From: Jason Wang <jasowang@redhat.com>
Date: Fri, 17 Jun 2022 15:29:49 +0800
Subject: [PATCH 1228/1731] virtio-net: fix race between ndo_open() and
 virtio_device_ready()

We currently call virtio_device_ready() after netdev
registration. Since ndo_open() can be called immediately
after register_netdev, this means there exists a race between
ndo_open() and virtio_device_ready(): the driver may start to use the
device before DRIVER_OK which violates the spec.

Fix this by switching to use register_netdevice() and protect the
virtio_device_ready() with rtnl_lock() to make sure ndo_open() can
only be called after virtio_device_ready().

Fixes: 4baf1e33d0842 ("virtio_net: enable VQs early")
Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20220617072949.30734-1-jasowang@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 drivers/net/virtio_net.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c
index db05b5e930bed..8a5810bcb839a 100644
--- a/drivers/net/virtio_net.c
+++ b/drivers/net/virtio_net.c
@@ -3655,14 +3655,20 @@ static int virtnet_probe(struct virtio_device *vdev)
 	if (vi->has_rss || vi->has_rss_hash_report)
 		virtnet_init_default_rss(vi);
 
-	err = register_netdev(dev);
+	/* serialize netdev register + virtio_device_ready() with ndo_open() */
+	rtnl_lock();
+
+	err = register_netdevice(dev);
 	if (err) {
 		pr_debug("virtio_net: registering device failed\n");
+		rtnl_unlock();
 		goto free_failover;
 	}
 
 	virtio_device_ready(vdev);
 
+	rtnl_unlock();
+
 	err = virtnet_cpu_notif_add(vi);
 	if (err) {
 		pr_debug("virtio_net: registering cpu notifier failed\n");
-- 
GitLab


From 11a37eb66812ce6a06b79223ad530eb0e1d7294d Mon Sep 17 00:00:00 2001
From: Jason Wang <jasowang@redhat.com>
Date: Mon, 20 Jun 2022 13:11:14 +0800
Subject: [PATCH 1229/1731] caif_virtio: fix race between virtio_device_ready()
 and ndo_open()

We currently depend on probe() calling virtio_device_ready() -
which happens after netdev
registration. Since ndo_open() can be called immediately
after register_netdev, this means there exists a race between
ndo_open() and virtio_device_ready(): the driver may start to use the
device (e.g. TX) before DRIVER_OK which violates the spec.

Fix this by switching to use register_netdevice() and protect the
virtio_device_ready() with rtnl_lock() to make sure ndo_open() can
only be called after virtio_device_ready().

Fixes: 0d2e1a2926b18 ("caif_virtio: Introduce caif over virtio")
Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20220620051115.3142-3-jasowang@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 drivers/net/caif/caif_virtio.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/net/caif/caif_virtio.c b/drivers/net/caif/caif_virtio.c
index 5458f57177a0a..0b0f234b0b508 100644
--- a/drivers/net/caif/caif_virtio.c
+++ b/drivers/net/caif/caif_virtio.c
@@ -722,13 +722,21 @@ static int cfv_probe(struct virtio_device *vdev)
 	/* Carrier is off until netdevice is opened */
 	netif_carrier_off(netdev);
 
+	/* serialize netdev register + virtio_device_ready() with ndo_open() */
+	rtnl_lock();
+
 	/* register Netdev */
-	err = register_netdev(netdev);
+	err = register_netdevice(netdev);
 	if (err) {
+		rtnl_unlock();
 		dev_err(&vdev->dev, "Unable to register netdev (%d)\n", err);
 		goto err;
 	}
 
+	virtio_device_ready(vdev);
+
+	rtnl_unlock();
+
 	debugfs_init(cfv);
 
 	return 0;
-- 
GitLab


From ed7ac37fde33ccd84e4bd2b9363c191f925364c7 Mon Sep 17 00:00:00 2001
From: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Date: Tue, 21 Jun 2022 13:06:20 +0200
Subject: [PATCH 1230/1731] virtio_mmio: Add missing PM calls to freeze/restore

Most virtio drivers provide freeze/restore callbacks to finish up
device usage before suspend and to reinitialize the virtio device after
resume. However, these callbacks are currently only called when using
virtio_pci. virtio_mmio does not have any PM ops defined.

This causes problems for example after suspend to disk (hibernation),
since the virtio devices might lose their state after the VMM is
restarted. Calling virtio_device_freeze()/restore() ensures that
the virtio devices are re-initialized correctly.

Fix this by implementing the dev_pm_ops for virtio_mmio,
similar to virtio_pci_common.

Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Message-Id: <20220621110621.3638025-2-stephan.gerhold@kernkonzept.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 drivers/virtio/virtio_mmio.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c
index c9bec3813e949..980dffd695865 100644
--- a/drivers/virtio/virtio_mmio.c
+++ b/drivers/virtio/virtio_mmio.c
@@ -62,6 +62,7 @@
 #include <linux/list.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/pm.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <linux/virtio.h>
@@ -556,6 +557,25 @@ static const struct virtio_config_ops virtio_mmio_config_ops = {
 	.synchronize_cbs = vm_synchronize_cbs,
 };
 
+#ifdef CONFIG_PM_SLEEP
+static int virtio_mmio_freeze(struct device *dev)
+{
+	struct virtio_mmio_device *vm_dev = dev_get_drvdata(dev);
+
+	return virtio_device_freeze(&vm_dev->vdev);
+}
+
+static int virtio_mmio_restore(struct device *dev)
+{
+	struct virtio_mmio_device *vm_dev = dev_get_drvdata(dev);
+
+	return virtio_device_restore(&vm_dev->vdev);
+}
+
+static const struct dev_pm_ops virtio_mmio_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(virtio_mmio_freeze, virtio_mmio_restore)
+};
+#endif
 
 static void virtio_mmio_release_dev(struct device *_d)
 {
@@ -799,6 +819,9 @@ static struct platform_driver virtio_mmio_driver = {
 		.name	= "virtio-mmio",
 		.of_match_table	= virtio_mmio_match,
 		.acpi_match_table = ACPI_PTR(virtio_mmio_acpi_match),
+#ifdef CONFIG_PM_SLEEP
+		.pm	= &virtio_mmio_pm_ops,
+#endif
 	},
 };
 
-- 
GitLab


From e0c2ce8217955537dd5434baeba061f209797119 Mon Sep 17 00:00:00 2001
From: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Date: Tue, 21 Jun 2022 13:06:21 +0200
Subject: [PATCH 1231/1731] virtio_mmio: Restore guest page size on resume

Virtio devices might lose their state when the VMM is restarted
after a suspend to disk (hibernation) cycle. This means that the
guest page size register must be restored for the virtio_mmio legacy
interface, since otherwise the virtio queues are not functional.

This is particularly problematic for QEMU that currently still defaults
to using the legacy interface for virtio_mmio. Write the guest page
size register again in virtio_mmio_restore() to make legacy virtio_mmio
devices work correctly after hibernation.

Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Message-Id: <20220621110621.3638025-3-stephan.gerhold@kernkonzept.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 drivers/virtio/virtio_mmio.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c
index 980dffd695865..083ff1eb743d3 100644
--- a/drivers/virtio/virtio_mmio.c
+++ b/drivers/virtio/virtio_mmio.c
@@ -569,6 +569,9 @@ static int virtio_mmio_restore(struct device *dev)
 {
 	struct virtio_mmio_device *vm_dev = dev_get_drvdata(dev);
 
+	if (vm_dev->version == 1)
+		writel(PAGE_SIZE, vm_dev->base + VIRTIO_MMIO_GUEST_PAGE_SIZE);
+
 	return virtio_device_restore(&vm_dev->vdev);
 }
 
-- 
GitLab


From 037d4305569aacaa018a617771dccbb81cc60257 Mon Sep 17 00:00:00 2001
From: Stefano Garzarella <sgarzare@redhat.com>
Date: Wed, 22 Jun 2022 17:14:07 +0200
Subject: [PATCH 1232/1731] vhost-vdpa: call vhost_vdpa_cleanup during the
 release
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Before commit 3d5698793897 ("vhost-vdpa: introduce asid based IOTLB")
we call vhost_vdpa_iotlb_free() during the release to clean all regions
mapped in the iotlb.

That commit removed vhost_vdpa_iotlb_free() and added vhost_vdpa_cleanup()
to do some cleanup, including deleting all mappings, but we forgot to call
it in vhost_vdpa_release().

This causes that if an application does not remove all mappings explicitly
(or it crashes), the mappings remain in the iotlb and subsequent
applications may fail if they map the same addresses.

Calling vhost_vdpa_cleanup() also fixes a memory leak since we are not
freeing `v->vdev.vqs` during the release from the same commit.

Since vhost_vdpa_cleanup() calls vhost_dev_cleanup() we can remove its
call from vhost_vdpa_release().

Fixes: 3d5698793897 ("vhost-vdpa: introduce asid based IOTLB")
Cc: gautam.dawar@xilinx.com
Signed-off-by: Stefano Garzarella <sgarzare@redhat.com>
Message-Id: <20220622151407.51232-1-sgarzare@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Tested-by: Eugenio Pérez <eperezma@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
---
 drivers/vhost/vdpa.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/vhost/vdpa.c b/drivers/vhost/vdpa.c
index 5ad2596c6e8a1..23dcbfdfa13b1 100644
--- a/drivers/vhost/vdpa.c
+++ b/drivers/vhost/vdpa.c
@@ -1209,7 +1209,7 @@ static int vhost_vdpa_release(struct inode *inode, struct file *filep)
 	vhost_dev_stop(&v->vdev);
 	vhost_vdpa_free_domain(v);
 	vhost_vdpa_config_put(v);
-	vhost_dev_cleanup(&v->vdev);
+	vhost_vdpa_cleanup(v);
 	mutex_unlock(&d->mutex);
 
 	atomic_dec(&v->opened);
-- 
GitLab


From c7cc29aaebf9eaa543b4c70801e0ecef1101b3c8 Mon Sep 17 00:00:00 2001
From: Deming Wang <wangdeming@inspur.com>
Date: Wed, 22 Jun 2022 15:23:06 -0400
Subject: [PATCH 1233/1731] virtio_ring: make vring_create_virtqueue_split
 prettier

Add some spaces to vring_alloc_queue(make it look prettier).

Signed-off-by: Deming Wang <wangdeming@inspur.com>
Message-Id: <20220622192306.4371-1-wangdeming@inspur.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 drivers/virtio/virtio_ring.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c
index 96731cdef422a..643ca779fcc63 100644
--- a/drivers/virtio/virtio_ring.c
+++ b/drivers/virtio/virtio_ring.c
@@ -935,7 +935,7 @@ static struct virtqueue *vring_create_virtqueue_split(
 	for (; num && vring_size(num, vring_align) > PAGE_SIZE; num /= 2) {
 		queue = vring_alloc_queue(vdev, vring_size(num, vring_align),
 					  &dma_addr,
-					  GFP_KERNEL|__GFP_NOWARN|__GFP_ZERO);
+					  GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
 		if (queue)
 			break;
 		if (!may_reduce_num)
-- 
GitLab


From 5f701324c0fb6f9f5aaac3f8d1575321375f6d8f Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime@cerno.tech>
Date: Wed, 22 Jun 2022 10:02:43 +0200
Subject: [PATCH 1234/1731] drm/vc4: perfmon: Fix variable dereferenced before
 check
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Commit 30f8c74ca9b7 ("drm/vc4: Warn if some v3d code is run on BCM2711")
introduced a check in vc4_perfmon_get() that dereferences a pointer before
we checked whether that pointer is valid or not.

Let's rework that function a bit to do things in the proper order.

Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Fixes: 30f8c74ca9b7 ("drm/vc4: Warn if some v3d code is run on BCM2711")
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Reviewed-by: José Expósito <jose.exposito89@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220622080243.22119-1-maxime@cerno.tech
---
 drivers/gpu/drm/vc4/vc4_perfmon.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_perfmon.c b/drivers/gpu/drm/vc4/vc4_perfmon.c
index c7f5adb6bcf8b..79a74184d7328 100644
--- a/drivers/gpu/drm/vc4/vc4_perfmon.c
+++ b/drivers/gpu/drm/vc4/vc4_perfmon.c
@@ -17,13 +17,16 @@
 
 void vc4_perfmon_get(struct vc4_perfmon *perfmon)
 {
-	struct vc4_dev *vc4 = perfmon->dev;
+	struct vc4_dev *vc4;
 
+	if (!perfmon)
+		return;
+
+	vc4 = perfmon->dev;
 	if (WARN_ON_ONCE(vc4->is_vc5))
 		return;
 
-	if (perfmon)
-		refcount_inc(&perfmon->refcnt);
+	refcount_inc(&perfmon->refcnt);
 }
 
 void vc4_perfmon_put(struct vc4_perfmon *perfmon)
-- 
GitLab


From e201c9630b374e394b7cadcc4d3679371cf98388 Mon Sep 17 00:00:00 2001
From: "Nancy.Lin" <nancy.lin@mediatek.com>
Date: Mon, 20 Jun 2022 17:19:17 +0800
Subject: [PATCH 1235/1731] dt-bindings: display: mediatek: add vdosys1 RDMA
 definition for mt8195

Add vdosys1 RDMA definition.

Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220620091930.27797-2-nancy.lin@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 .../display/mediatek/mediatek,mdp-rdma.yaml   | 88 +++++++++++++++++++
 1 file changed, 88 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
new file mode 100644
index 0000000000000..dd12e2ff685c2
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MDP RDMA
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description:
+  The MediaTek MDP RDMA stands for Read Direct Memory Access.
+  It provides real time data to the back-end panel driver, such as DSI,
+  DPI and DP_INTF.
+  It contains one line buffer to store the sufficient pixel data.
+  RDMA device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+
+properties:
+  compatible:
+    const: mediatek,mt8195-vdo1-rdma
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: RDMA Clock
+
+  iommus:
+    maxItems: 1
+
+  mediatek,gce-client-reg:
+    description:
+      The register of display function block to be set by gce. There are 4 arguments,
+      such as gce node, subsys id, offset and register size. The subsys id that is
+      mapping to the register of display function blocks is defined in the gce header
+      include/dt-bindings/gce/<chip>-gce.h of each chips.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      items:
+        - description: phandle of GCE
+        - description: GCE subsys id
+        - description: register offset
+        - description: register size
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - clocks
+  - iommus
+  - mediatek,gce-client-reg
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/mt8195-clk.h>
+    #include <dt-bindings/power/mt8195-power.h>
+    #include <dt-bindings/gce/mt8195-gce.h>
+    #include <dt-bindings/memory/mt8195-memory-port.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        rdma@1c104000 {
+            compatible = "mediatek,mt8195-vdo1-rdma";
+            reg = <0 0x1c104000 0 0x1000>;
+            interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+            clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+            power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+            iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+            mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
+        };
+    };
-- 
GitLab


From a27a1e35f5c87463ba7c12d5b7d7cbafbefc9213 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Thu, 23 Jun 2022 13:59:14 +0200
Subject: [PATCH 1236/1731] platform/x86: ideapad-laptop: Add allow_v4_dytc
 module parameter

Add an allow_v4_dytc module parameter to allow users to easily test if
DYTC version 4 platform-profiles work on their laptop.

Fixes: 599482c58ebd ("platform/x86: ideapad-laptop: Add platform support for Ideapad 5 Pro 16ACH6-82L5")
Link: https://bugzilla.kernel.org/show_bug.cgi?id=213297
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20220623115914.103001-1-hdegoede@redhat.com
---
 drivers/platform/x86/ideapad-laptop.c | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/platform/x86/ideapad-laptop.c b/drivers/platform/x86/ideapad-laptop.c
index 3ccb7b71dfb12..71f4b59eed4bd 100644
--- a/drivers/platform/x86/ideapad-laptop.c
+++ b/drivers/platform/x86/ideapad-laptop.c
@@ -152,6 +152,10 @@ static bool no_bt_rfkill;
 module_param(no_bt_rfkill, bool, 0444);
 MODULE_PARM_DESC(no_bt_rfkill, "No rfkill for bluetooth.");
 
+static bool allow_v4_dytc;
+module_param(allow_v4_dytc, bool, 0444);
+MODULE_PARM_DESC(allow_v4_dytc, "Enable DYTC version 4 platform-profile support.");
+
 /*
  * ACPI Helpers
  */
@@ -901,13 +905,16 @@ static int ideapad_dytc_profile_init(struct ideapad_private *priv)
 
 	dytc_version = (output >> DYTC_QUERY_REV_BIT) & 0xF;
 
-	if (dytc_version < 5) {
-		if (dytc_version < 4 || !dmi_check_system(ideapad_dytc_v4_allow_table)) {
-			dev_info(&priv->platform_device->dev,
-				 "DYTC_VERSION is less than 4 or is not allowed: %d\n",
-				 dytc_version);
-			return -ENODEV;
-		}
+	if (dytc_version < 4) {
+		dev_info(&priv->platform_device->dev, "DYTC_VERSION < 4 is not supported\n");
+		return -ENODEV;
+	}
+
+	if (dytc_version < 5 &&
+	    !(allow_v4_dytc || dmi_check_system(ideapad_dytc_v4_allow_table))) {
+		dev_info(&priv->platform_device->dev,
+			 "DYTC_VERSION 4 support may not work. Pass ideapad_laptop.allow_v4_dytc=Y on the kernel commandline to enable\n");
+		return -ENODEV;
 	}
 
 	priv->dytc = kzalloc(sizeof(*priv->dytc), GFP_KERNEL);
-- 
GitLab


From 8853e8ce9b576e0a3aad8381e19a117964d445fa Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Mon, 27 Jun 2022 15:08:50 +0200
Subject: [PATCH 1237/1731] platform/x86: ideapad-laptop: Add Ideapad 5 15ITL05
 to ideapad_dytc_v4_allow_table[]

The Ideapad 5 15ITL05 uses DYTC version 4 for platform-profile
control. This has been tested successfully with the ideapad-laptop
DYTC version 5 code; Add the Ideapad 5 15ITL05 to the
ideapad_dytc_v4_allow_table[].

Fixes: 599482c58ebd ("platform/x86: ideapad-laptop: Add platform support for Ideapad 5 Pro 16ACH6-82L5")
Link: https://bugzilla.kernel.org/show_bug.cgi?id=213297
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20220627130850.313537-1-hdegoede@redhat.com
---
 drivers/platform/x86/ideapad-laptop.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/platform/x86/ideapad-laptop.c b/drivers/platform/x86/ideapad-laptop.c
index 71f4b59eed4bd..abd0c81d62c40 100644
--- a/drivers/platform/x86/ideapad-laptop.c
+++ b/drivers/platform/x86/ideapad-laptop.c
@@ -875,12 +875,18 @@ static void dytc_profile_refresh(struct ideapad_private *priv)
 static const struct dmi_system_id ideapad_dytc_v4_allow_table[] = {
 	{
 		/* Ideapad 5 Pro 16ACH6 */
-		.ident = "LENOVO 82L5",
 		.matches = {
 			DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
 			DMI_MATCH(DMI_PRODUCT_NAME, "82L5")
 		}
 	},
+	{
+		/* Ideapad 5 15ITL05 */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
+			DMI_MATCH(DMI_PRODUCT_VERSION, "IdeaPad 5 15ITL05")
+		}
+	},
 	{}
 };
 
-- 
GitLab


From 19e506b317497a8c2b3ec2f12314d355d2f00ad0 Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Tue, 21 Jun 2022 15:22:26 +0200
Subject: [PATCH 1238/1731] eeprom: at25: Rework buggy read splitting

The recent change to split reads into chunks has several problems:
  1. If an SPI controller has no transfer size limit, max_chunk is
     SIZE_MAX, and num_msgs becomes zero, causing no data to be read
     into the buffer, and exposing the original contents of the buffer
     to userspace,
  2. If the requested read size is not a multiple of the maximum
     transfer size, the last transfer reads too much data, overflowing
     the buffer,
  3. The loop logic differs from the write case.

Fix the above by:
  1. Keeping track of the number of bytes that are still to be
     transferred, instead of precalculating the number of messages and
     keeping track of the number of bytes tranfered,
  2. Calculating the transfer size of each individual message, taking
     into account the number of bytes left,
  3. Switching from a "while"-loop to a "do-while"-loop, and renaming
     "msg_count" to "segment".

While at it, drop the superfluous cast from "unsigned int" to "unsigned
int", also from at25_ee_write(), where it was probably copied from.

Fixes: 0a35780c755ccec0 ("eeprom: at25: Split reads into chunks and cap write size")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/7ae260778d2c08986348ea48ce02ef148100e088.1655817534.git.geert+renesas@glider.be
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/misc/eeprom/at25.c | 26 ++++++++++++--------------
 1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/drivers/misc/eeprom/at25.c b/drivers/misc/eeprom/at25.c
index c9c56fd194c13..bdffc6543f6f8 100644
--- a/drivers/misc/eeprom/at25.c
+++ b/drivers/misc/eeprom/at25.c
@@ -80,10 +80,9 @@ static int at25_ee_read(void *priv, unsigned int offset,
 	struct at25_data *at25 = priv;
 	char *buf = val;
 	size_t max_chunk = spi_max_transfer_size(at25->spi);
-	size_t num_msgs = DIV_ROUND_UP(count, max_chunk);
-	size_t nr_bytes = 0;
-	unsigned int msg_offset;
-	size_t msg_count;
+	unsigned int msg_offset = offset;
+	size_t bytes_left = count;
+	size_t segment;
 	u8			*cp;
 	ssize_t			status;
 	struct spi_transfer	t[2];
@@ -97,9 +96,8 @@ static int at25_ee_read(void *priv, unsigned int offset,
 	if (unlikely(!count))
 		return -EINVAL;
 
-	msg_offset = (unsigned int)offset;
-	msg_count = min(count, max_chunk);
-	while (num_msgs) {
+	do {
+		segment = min(bytes_left, max_chunk);
 		cp = at25->command;
 
 		instr = AT25_READ;
@@ -131,8 +129,8 @@ static int at25_ee_read(void *priv, unsigned int offset,
 		t[0].len = at25->addrlen + 1;
 		spi_message_add_tail(&t[0], &m);
 
-		t[1].rx_buf = buf + nr_bytes;
-		t[1].len = msg_count;
+		t[1].rx_buf = buf;
+		t[1].len = segment;
 		spi_message_add_tail(&t[1], &m);
 
 		status = spi_sync(at25->spi, &m);
@@ -142,10 +140,10 @@ static int at25_ee_read(void *priv, unsigned int offset,
 		if (status)
 			return status;
 
-		--num_msgs;
-		msg_offset += msg_count;
-		nr_bytes += msg_count;
-	}
+		msg_offset += segment;
+		buf += segment;
+		bytes_left -= segment;
+	} while (bytes_left > 0);
 
 	dev_dbg(&at25->spi->dev, "read %zu bytes at %d\n",
 		count, offset);
@@ -229,7 +227,7 @@ static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count)
 	do {
 		unsigned long	timeout, retries;
 		unsigned	segment;
-		unsigned	offset = (unsigned) off;
+		unsigned	offset = off;
 		u8		*cp = bounce;
 		int		sr;
 		u8		instr;
-- 
GitLab


From f8946e2b6bb2a0efd450cc054f6b5b45a1f5c7d3 Mon Sep 17 00:00:00 2001
From: "Nancy.Lin" <nancy.lin@mediatek.com>
Date: Mon, 20 Jun 2022 17:19:19 +0800
Subject: [PATCH 1239/1731] drm/mediatek: Add display MDP RDMA support for
 MT8195

Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
the ovl_adaptor component.

Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220620091930.27797-4-nancy.lin@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/Makefile       |   3 +-
 drivers/gpu/drm/mediatek/mtk_disp_drv.h |   7 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.h  |   1 +
 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 315 ++++++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h |  20 ++
 6 files changed, 346 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index a38e88e82d123..6e604a933ed08 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_aal.o \
 		  mtk_drm_gem.o \
 		  mtk_drm_plane.o \
 		  mtk_dsi.o \
-		  mtk_dpi.o
+		  mtk_dpi.o \
+		  mtk_mdp_rdma.o
 
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
 
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index f13a6f5d512aa..2cd1c660ace36 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -8,6 +8,7 @@
 
 #include <linux/soc/mediatek/mtk-cmdq.h>
 #include "mtk_drm_plane.h"
+#include "mtk_mdp_rdma.h"
 
 int mtk_aal_clk_enable(struct device *dev);
 void mtk_aal_clk_disable(struct device *dev);
@@ -110,4 +111,10 @@ void mtk_rdma_unregister_vblank_cb(struct device *dev);
 void mtk_rdma_enable_vblank(struct device *dev);
 void mtk_rdma_disable_vblank(struct device *dev);
 
+int mtk_mdp_rdma_clk_enable(struct device *dev);
+void mtk_mdp_rdma_clk_disable(struct device *dev);
+void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
+			 struct cmdq_pkt *cmdq_pkt);
 #endif
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 42e27ca423a22..13a1bbe7ead7f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -875,6 +875,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_dpi_driver,
 	&mtk_drm_platform_driver,
 	&mtk_dsi_driver,
+	&mtk_mdp_rdma_driver,
 };
 
 static int __init mtk_drm_init(void)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 9fc922b1684f5..7b37b5cf96295 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -61,5 +61,6 @@ extern struct platform_driver mtk_disp_ovl_driver;
 extern struct platform_driver mtk_disp_rdma_driver;
 extern struct platform_driver mtk_dpi_driver;
 extern struct platform_driver mtk_dsi_driver;
+extern struct platform_driver mtk_mdp_rdma_driver;
 
 #endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
new file mode 100644
index 0000000000000..eecfa98ff52e8
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
@@ -0,0 +1,315 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_disp_drv.h"
+#include "mtk_drm_drv.h"
+#include "mtk_mdp_rdma.h"
+
+#define MDP_RDMA_EN			0x000
+#define FLD_ROT_ENABLE				BIT(0)
+#define MDP_RDMA_RESET			0x008
+#define MDP_RDMA_CON			0x020
+#define FLD_OUTPUT_10B				BIT(5)
+#define FLD_SIMPLE_MODE				BIT(4)
+#define MDP_RDMA_GMCIF_CON		0x028
+#define FLD_COMMAND_DIV				BIT(0)
+#define FLD_EXT_PREULTRA_EN			BIT(3)
+#define FLD_RD_REQ_TYPE				GENMASK(7, 4)
+#define VAL_RD_REQ_TYPE_BURST_8_ACCESS		7
+#define FLD_ULTRA_EN				GENMASK(13, 12)
+#define VAL_ULTRA_EN_ENABLE			1
+#define FLD_PRE_ULTRA_EN			GENMASK(17, 16)
+#define VAL_PRE_ULTRA_EN_ENABLE			1
+#define FLD_EXT_ULTRA_EN			BIT(18)
+#define MDP_RDMA_SRC_CON		0x030
+#define FLD_OUTPUT_ARGB				BIT(25)
+#define FLD_BIT_NUMBER				GENMASK(19, 18)
+#define FLD_SWAP				BIT(14)
+#define FLD_UNIFORM_CONFIG			BIT(17)
+#define RDMA_INPUT_10BIT			BIT(18)
+#define FLD_SRC_FORMAT				GENMASK(3, 0)
+#define MDP_RDMA_COMP_CON		0x038
+#define FLD_AFBC_EN				BIT(22)
+#define FLD_AFBC_YUV_TRANSFORM			BIT(21)
+#define FLD_UFBDC_EN				BIT(12)
+#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE	0x060
+#define FLD_MF_BKGD_WB				GENMASK(22, 0)
+#define MDP_RDMA_MF_SRC_SIZE		0x070
+#define FLD_MF_SRC_H				GENMASK(30, 16)
+#define FLD_MF_SRC_W				GENMASK(14, 0)
+#define MDP_RDMA_MF_CLIP_SIZE		0x078
+#define FLD_MF_CLIP_H				GENMASK(30, 16)
+#define FLD_MF_CLIP_W				GENMASK(14, 0)
+#define MDP_RDMA_SRC_OFFSET_0		0x118
+#define FLD_SRC_OFFSET_0			GENMASK(31, 0)
+#define MDP_RDMA_TRANSFORM_0		0x200
+#define FLD_INT_MATRIX_SEL			GENMASK(27, 23)
+#define FLD_TRANS_EN				BIT(16)
+#define MDP_RDMA_SRC_BASE_0		0xf00
+#define FLD_SRC_BASE_0				GENMASK(31, 0)
+
+#define RDMA_CSC_FULL709_TO_RGB			5
+#define RDMA_CSC_BT601_TO_RGB			6
+
+enum rdma_format {
+	RDMA_INPUT_FORMAT_RGB565 = 0,
+	RDMA_INPUT_FORMAT_RGB888 = 1,
+	RDMA_INPUT_FORMAT_RGBA8888 = 2,
+	RDMA_INPUT_FORMAT_ARGB8888 = 3,
+	RDMA_INPUT_FORMAT_UYVY = 4,
+	RDMA_INPUT_FORMAT_YUY2 = 5,
+	RDMA_INPUT_FORMAT_Y8 = 7,
+	RDMA_INPUT_FORMAT_YV12 = 8,
+	RDMA_INPUT_FORMAT_UYVY_3PL = 9,
+	RDMA_INPUT_FORMAT_NV12 = 12,
+	RDMA_INPUT_FORMAT_UYVY_2PL = 13,
+	RDMA_INPUT_FORMAT_Y410 = 14
+};
+
+struct mtk_mdp_rdma {
+	void __iomem		*regs;
+	struct clk		*clk;
+	struct cmdq_client_reg	cmdq_reg;
+};
+
+static unsigned int rdma_fmt_convert(unsigned int fmt)
+{
+	switch (fmt) {
+	default:
+	case DRM_FORMAT_RGB565:
+		return RDMA_INPUT_FORMAT_RGB565;
+	case DRM_FORMAT_BGR565:
+		return RDMA_INPUT_FORMAT_RGB565 | FLD_SWAP;
+	case DRM_FORMAT_RGB888:
+		return RDMA_INPUT_FORMAT_RGB888;
+	case DRM_FORMAT_BGR888:
+		return RDMA_INPUT_FORMAT_RGB888 | FLD_SWAP;
+	case DRM_FORMAT_RGBX8888:
+	case DRM_FORMAT_RGBA8888:
+		return RDMA_INPUT_FORMAT_ARGB8888;
+	case DRM_FORMAT_BGRX8888:
+	case DRM_FORMAT_BGRA8888:
+		return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP;
+	case DRM_FORMAT_XRGB8888:
+	case DRM_FORMAT_ARGB8888:
+		return RDMA_INPUT_FORMAT_RGBA8888;
+	case DRM_FORMAT_XBGR8888:
+	case DRM_FORMAT_ABGR8888:
+		return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP;
+	case DRM_FORMAT_ABGR2101010:
+		return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP | RDMA_INPUT_10BIT;
+	case DRM_FORMAT_ARGB2101010:
+		return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
+	case DRM_FORMAT_RGBA1010102:
+		return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP | RDMA_INPUT_10BIT;
+	case DRM_FORMAT_BGRA1010102:
+		return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
+	case DRM_FORMAT_UYVY:
+		return RDMA_INPUT_FORMAT_UYVY;
+	case DRM_FORMAT_YUYV:
+		return RDMA_INPUT_FORMAT_YUY2;
+	}
+}
+
+static unsigned int rdma_color_convert(unsigned int color_encoding)
+{
+	switch (color_encoding) {
+	default:
+	case DRM_COLOR_YCBCR_BT709:
+		return RDMA_CSC_FULL709_TO_RGB;
+	case DRM_COLOR_YCBCR_BT601:
+		return RDMA_CSC_BT601_TO_RGB;
+	}
+}
+
+static void mtk_mdp_rdma_fifo_config(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
+
+	mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | VAL_PRE_ULTRA_EN_ENABLE << 16 |
+			   VAL_ULTRA_EN_ENABLE << 12 | VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 |
+			   FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV, &priv->cmdq_reg,
+			   priv->regs, MDP_RDMA_GMCIF_CON, FLD_EXT_ULTRA_EN |
+			   FLD_PRE_ULTRA_EN | FLD_ULTRA_EN | FLD_RD_REQ_TYPE |
+			   FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV);
+}
+
+void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
+
+	mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg,
+			   priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE);
+}
+
+void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
+
+	mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,
+			   priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE);
+	mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);
+	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);
+}
+
+void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
+			 struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
+	const struct drm_format_info *fmt_info = drm_format_info(cfg->fmt);
+	bool csc_enable = fmt_info->is_yuv ? true : false;
+	unsigned int src_pitch_y = cfg->pitch;
+	unsigned int offset_y = 0;
+
+	mtk_mdp_rdma_fifo_config(dev, cmdq_pkt);
+
+	mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv->cmdq_reg, priv->regs,
+			   MDP_RDMA_SRC_CON, FLD_UNIFORM_CONFIG);
+	mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), &priv->cmdq_reg, priv->regs,
+			   MDP_RDMA_SRC_CON, FLD_SWAP | FLD_SRC_FORMAT | FLD_BIT_NUMBER);
+
+	if (!csc_enable && fmt_info->has_alpha)
+		mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB, &priv->cmdq_reg,
+				   priv->regs, MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB);
+	else
+		mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+				   MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB);
+
+	mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg, priv->regs,
+			   MDP_RDMA_SRC_BASE_0, FLD_SRC_BASE_0);
+
+	mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg, priv->regs,
+			   MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, FLD_MF_BKGD_WB);
+
+	mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_COMP_CON,
+			   FLD_AFBC_YUV_TRANSFORM | FLD_UFBDC_EN | FLD_AFBC_EN);
+	mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_10B, &priv->cmdq_reg, priv->regs,
+			   MDP_RDMA_CON, FLD_OUTPUT_10B);
+	mtk_ddp_write_mask(cmdq_pkt, FLD_SIMPLE_MODE, &priv->cmdq_reg, priv->regs,
+			   MDP_RDMA_CON, FLD_SIMPLE_MODE);
+	if (csc_enable)
+		mtk_ddp_write_mask(cmdq_pkt, rdma_color_convert(cfg->color_encoding) << 23,
+				   &priv->cmdq_reg, priv->regs, MDP_RDMA_TRANSFORM_0,
+				   FLD_INT_MATRIX_SEL);
+	mtk_ddp_write_mask(cmdq_pkt, csc_enable << 16, &priv->cmdq_reg, priv->regs,
+			   MDP_RDMA_TRANSFORM_0, FLD_TRANS_EN);
+
+	offset_y  = cfg->x_left * fmt_info->cpp[0] + cfg->y_top * src_pitch_y;
+
+	mtk_ddp_write_mask(cmdq_pkt, offset_y, &priv->cmdq_reg, priv->regs,
+			   MDP_RDMA_SRC_OFFSET_0, FLD_SRC_OFFSET_0);
+	mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,
+			   MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_W);
+	mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,
+			   MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_H);
+	mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,
+			   MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_W);
+	mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,
+			   MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_H);
+}
+
+int mtk_mdp_rdma_clk_enable(struct device *dev)
+{
+	struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
+
+	clk_prepare_enable(rdma->clk);
+	return 0;
+}
+
+void mtk_mdp_rdma_clk_disable(struct device *dev)
+{
+	struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
+
+	clk_disable_unprepare(rdma->clk);
+}
+
+static int mtk_mdp_rdma_bind(struct device *dev, struct device *master,
+			     void *data)
+{
+	return 0;
+}
+
+static void mtk_mdp_rdma_unbind(struct device *dev, struct device *master,
+				void *data)
+{
+}
+
+static const struct component_ops mtk_mdp_rdma_component_ops = {
+	.bind	= mtk_mdp_rdma_bind,
+	.unbind = mtk_mdp_rdma_unbind,
+};
+
+static int mtk_mdp_rdma_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct mtk_mdp_rdma *priv;
+	int ret = 0;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->regs)) {
+		dev_err(dev, "failed to ioremap rdma\n");
+		return PTR_ERR(priv->regs);
+	}
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(dev, "failed to get rdma clk\n");
+		return PTR_ERR(priv->clk);
+	}
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+	if (ret)
+		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+	platform_set_drvdata(pdev, priv);
+
+	pm_runtime_enable(dev);
+
+	ret = component_add(dev, &mtk_mdp_rdma_component_ops);
+	if (ret != 0) {
+		pm_runtime_disable(dev);
+		dev_err(dev, "Failed to add component: %d\n", ret);
+	}
+	return ret;
+}
+
+static int mtk_mdp_rdma_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &mtk_mdp_rdma_component_ops);
+	pm_runtime_disable(&pdev->dev);
+	return 0;
+}
+
+static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] = {
+	{ .compatible = "mediatek,mt8195-vdo1-rdma", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, mtk_mdp_rdma_driver_dt_match);
+
+struct platform_driver mtk_mdp_rdma_driver = {
+	.probe = mtk_mdp_rdma_probe,
+	.remove = mtk_mdp_rdma_remove,
+	.driver = {
+		.name = "mediatek-mdp-rdma",
+		.owner = THIS_MODULE,
+		.of_match_table = mtk_mdp_rdma_driver_dt_match,
+	},
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
new file mode 100644
index 0000000000000..9943ee3aac31e
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_MDP_RDMA_H__
+#define __MTK_MDP_RDMA_H__
+
+struct mtk_mdp_rdma_cfg {
+	unsigned int	pitch;
+	unsigned int	addr0;
+	unsigned int	width;
+	unsigned int	height;
+	unsigned int	x_left;
+	unsigned int	y_top;
+	int		fmt;
+	int		color_encoding;
+};
+
+#endif // __MTK_MDP_RDMA_H__
-- 
GitLab


From 7e4727f74520dd4038acb4f29f3d4195890094fa Mon Sep 17 00:00:00 2001
From: "Nancy.Lin" <nancy.lin@mediatek.com>
Date: Mon, 20 Jun 2022 17:19:20 +0800
Subject: [PATCH 1240/1731] drm/mediatek: Add display merge advance config API
 for MT8195

Add merge new advance config API. The original merge API is
mtk_ddp_comp_funcs function prototype. The API interface parameters
cannot be modified, so add a new config API for extension. This is
the preparation for ovl_adaptor merge control.

Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220620091930.27797-5-nancy.lin@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_disp_drv.h   |  3 ++
 drivers/gpu/drm/mediatek/mtk_disp_merge.c | 52 ++++++++++++++++++++---
 2 files changed, 48 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 2cd1c660ace36..e847e90f436d7 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -63,6 +63,9 @@ void mtk_merge_config(struct device *dev, unsigned int width,
 		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
 void mtk_merge_start(struct device *dev);
 void mtk_merge_stop(struct device *dev);
+void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,
+			      unsigned int h, unsigned int vrefresh, unsigned int bpc,
+			      struct cmdq_pkt *cmdq_pkt);
 
 void mtk_ovl_bgclr_in_on(struct device *dev);
 void mtk_ovl_bgclr_in_off(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
index 45face6381531..40da0555416d9 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -17,6 +17,7 @@
 #define DISP_REG_MERGE_CTRL		0x000
 #define MERGE_EN				1
 #define DISP_REG_MERGE_CFG_0		0x010
+#define DISP_REG_MERGE_CFG_1		0x014
 #define DISP_REG_MERGE_CFG_4		0x020
 #define DISP_REG_MERGE_CFG_10		0x038
 /* no swap */
@@ -25,9 +26,12 @@
 #define DISP_REG_MERGE_CFG_12		0x040
 #define CFG_10_10_1PI_2PO_BUF_MODE		6
 #define CFG_10_10_2PI_2PO_BUF_MODE		8
+#define CFG_11_10_1PI_2PO_MERGE			18
 #define FLD_CFG_MERGE_MODE			GENMASK(4, 0)
 #define DISP_REG_MERGE_CFG_24		0x070
 #define DISP_REG_MERGE_CFG_25		0x074
+#define DISP_REG_MERGE_CFG_26		0x078
+#define DISP_REG_MERGE_CFG_27		0x07c
 #define DISP_REG_MERGE_CFG_36		0x0a0
 #define ULTRA_EN				BIT(0)
 #define PREULTRA_EN				BIT(4)
@@ -98,12 +102,19 @@ static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
 void mtk_merge_config(struct device *dev, unsigned int w,
 		      unsigned int h, unsigned int vrefresh,
 		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	mtk_merge_advance_config(dev, w, 0, h, vrefresh, bpc, cmdq_pkt);
+}
+
+void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,
+			      unsigned int h, unsigned int vrefresh, unsigned int bpc,
+			      struct cmdq_pkt *cmdq_pkt)
 {
 	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
 	unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
 
-	if (!h || !w) {
-		dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
+	if (!h || !l_w) {
+		dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, l_w, h);
 		return;
 	}
 
@@ -112,14 +123,41 @@ void mtk_merge_config(struct device *dev, unsigned int w,
 		mode = CFG_10_10_2PI_2PO_BUF_MODE;
 	}
 
-	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+	if (r_w)
+		mode = CFG_11_10_1PI_2PO_MERGE;
+
+	mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
 		      DISP_REG_MERGE_CFG_0);
-	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+	mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_1);
+	mtk_ddp_write(cmdq_pkt, h << 16 | (l_w + r_w), &priv->cmdq_reg, priv->regs,
 		      DISP_REG_MERGE_CFG_4);
-	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+	/*
+	 * DISP_REG_MERGE_CFG_24 is merge SRAM0 w/h
+	 * DISP_REG_MERGE_CFG_25 is merge SRAM1 w/h.
+	 * If r_w > 0, the merge is in merge mode (input0 and input1 merge together),
+	 * the input0 goes to SRAM0, and input1 goes to SRAM1.
+	 * If r_w = 0, the merge is in buffer mode, the input goes through SRAM0 and
+	 * then to SRAM1. Both SRAM0 and SRAM1 are set to the same size.
+	 */
+	mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
 		      DISP_REG_MERGE_CFG_24);
-	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
-		      DISP_REG_MERGE_CFG_25);
+	if (r_w)
+		mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
+			      DISP_REG_MERGE_CFG_25);
+	else
+		mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
+			      DISP_REG_MERGE_CFG_25);
+
+	/*
+	 * DISP_REG_MERGE_CFG_26 and DISP_REG_MERGE_CFG_27 is only used in LR merge.
+	 * Only take effect when the merge is setting to merge mode.
+	 */
+	mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_26);
+	mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_27);
+
 	mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
 			   DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
 	mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
-- 
GitLab


From d2ae586f0e207ab418263018fd2e3cec2322179f Mon Sep 17 00:00:00 2001
From: "Nancy.Lin" <nancy.lin@mediatek.com>
Date: Mon, 20 Jun 2022 17:19:21 +0800
Subject: [PATCH 1241/1731] drm/mediatek: Add display merge start/stop API for
 cmdq support

Add merge start/stop API for cmdq support. The ovl_adaptor merges
are configured with each drm plane update. Need to enable/disable
merge with cmdq making sure all the settings taken effect in the
same vblank.

Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220620091930.27797-6-nancy.lin@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_disp_drv.h   |  2 ++
 drivers/gpu/drm/mediatek/mtk_disp_merge.c | 18 +++++++++++++++---
 2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index e847e90f436d7..33e61a136bbc5 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -66,6 +66,8 @@ void mtk_merge_stop(struct device *dev);
 void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,
 			      unsigned int h, unsigned int vrefresh, unsigned int bpc,
 			      struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_start_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt);
 
 void mtk_ovl_bgclr_in_on(struct device *dev);
 void mtk_ovl_bgclr_in_off(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
index 40da0555416d9..c7af5ccab9166 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -67,17 +67,29 @@ struct mtk_disp_merge {
 };
 
 void mtk_merge_start(struct device *dev)
+{
+	mtk_merge_start_cmdq(dev, NULL);
+}
+
+void mtk_merge_stop(struct device *dev)
+{
+	mtk_merge_stop_cmdq(dev, NULL);
+}
+
+void mtk_merge_start_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt)
 {
 	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
 
-	writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
+	mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CTRL);
 }
 
-void mtk_merge_stop(struct device *dev)
+void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt)
 {
 	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
 
-	writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CTRL);
 }
 
 static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
-- 
GitLab


From 8a9ffb8c857c2c99403bd6483a5a005fed5c0773 Mon Sep 17 00:00:00 2001
From: Alexey Khoroshilov <khoroshilov@ispras.ru>
Date: Sat, 25 Jun 2022 23:52:43 +0300
Subject: [PATCH 1242/1731] NFSD: restore EINVAL error translation in
 nfsd_commit()

commit 555dbf1a9aac ("nfsd: Replace use of rwsem with errseq_t")
incidentally broke translation of -EINVAL to nfserr_notsupp.
The patch restores that.

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru>
Fixes: 555dbf1a9aac ("nfsd: Replace use of rwsem with errseq_t")
Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
---
 fs/nfsd/vfs.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/fs/nfsd/vfs.c b/fs/nfsd/vfs.c
index 840e3af63a6f1..1b09d7293bc54 100644
--- a/fs/nfsd/vfs.c
+++ b/fs/nfsd/vfs.c
@@ -1173,6 +1173,7 @@ nfsd_commit(struct svc_rqst *rqstp, struct svc_fh *fhp, u64 offset,
 			nfsd_copy_write_verifier(verf, nn);
 			err2 = filemap_check_wb_err(nf->nf_file->f_mapping,
 						    since);
+			err = nfserrno(err2);
 			break;
 		case -EINVAL:
 			err = nfserr_notsupp;
@@ -1180,8 +1181,8 @@ nfsd_commit(struct svc_rqst *rqstp, struct svc_fh *fhp, u64 offset,
 		default:
 			nfsd_reset_write_verifier(nn);
 			trace_nfsd_writeverf_reset(nn, rqstp, err2);
+			err = nfserrno(err2);
 		}
-		err = nfserrno(err2);
 	} else
 		nfsd_copy_write_verifier(verf, nn);
 
-- 
GitLab


From a5b51d1dd95fd3a103b35fe0235ee6c35cf32c29 Mon Sep 17 00:00:00 2001
From: "Nancy.Lin" <nancy.lin@mediatek.com>
Date: Mon, 20 Jun 2022 17:19:22 +0800
Subject: [PATCH 1243/1731] drm/mediatek: Add display merge mute/unmute support
 for MT8195

Add merge mute/unmute setting for MT8195.
MT8195 Vdosys1 merge1~merge4 support HW mute function.

Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220620091930.27797-7-nancy.lin@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_disp_merge.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
index c7af5ccab9166..2e13d2fb429e7 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -58,12 +58,15 @@
 #define FLD_PREULTRA_TH_LOW			GENMASK(15, 0)
 #define FLD_PREULTRA_TH_HIGH			GENMASK(31, 16)
 
+#define DISP_REG_MERGE_MUTE_0		0xf00
+
 struct mtk_disp_merge {
 	void __iomem			*regs;
 	struct clk			*clk;
 	struct clk			*async_clk;
 	struct cmdq_client_reg		cmdq_reg;
 	bool				fifo_en;
+	bool				mute_support;
 };
 
 void mtk_merge_start(struct device *dev)
@@ -80,6 +83,10 @@ void mtk_merge_start_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt)
 {
 	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
 
+	if (priv->mute_support)
+		mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs,
+			      DISP_REG_MERGE_MUTE_0);
+
 	mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,
 		      DISP_REG_MERGE_CTRL);
 }
@@ -88,6 +95,10 @@ void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt)
 {
 	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
 
+	if (priv->mute_support)
+		mtk_ddp_write(cmdq_pkt, 0x1, &priv->cmdq_reg, priv->regs,
+			      DISP_REG_MERGE_MUTE_0);
+
 	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
 		      DISP_REG_MERGE_CTRL);
 }
@@ -262,6 +273,8 @@ static int mtk_disp_merge_probe(struct platform_device *pdev)
 	priv->fifo_en = of_property_read_bool(dev->of_node,
 					      "mediatek,merge-fifo-en");
 
+	priv->mute_support = of_property_read_bool(dev->of_node,
+						   "mediatek,merge-mute");
 	platform_set_drvdata(pdev, priv);
 
 	ret = component_add(dev, &mtk_disp_merge_component_ops);
-- 
GitLab


From aaf94f7c3ae6b86135ada5bdb01bce5242b27175 Mon Sep 17 00:00:00 2001
From: "Nancy.Lin" <nancy.lin@mediatek.com>
Date: Mon, 20 Jun 2022 17:19:23 +0800
Subject: [PATCH 1244/1731] drm/mediatek: Add display merge async reset control

Add merge async reset control in mtk_merge_stop. Async hw doesn't do self
reset on each sof signal(start of frame), so need to reset the async to
clear the hw status for the next merge start.

Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220620091930.27797-8-nancy.lin@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_disp_merge.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
index 2e13d2fb429e7..6428b6203ffe8 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -8,6 +8,7 @@
 #include <linux/of_device.h>
 #include <linux/of_irq.h>
 #include <linux/platform_device.h>
+#include <linux/reset.h>
 #include <linux/soc/mediatek/mtk-cmdq.h>
 
 #include "mtk_drm_ddp_comp.h"
@@ -67,6 +68,7 @@ struct mtk_disp_merge {
 	struct cmdq_client_reg		cmdq_reg;
 	bool				fifo_en;
 	bool				mute_support;
+	struct reset_control		*reset_ctl;
 };
 
 void mtk_merge_start(struct device *dev)
@@ -101,6 +103,9 @@ void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt)
 
 	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
 		      DISP_REG_MERGE_CTRL);
+
+	if (priv->async_clk)
+		reset_control_reset(priv->reset_ctl);
 }
 
 static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
@@ -264,6 +269,12 @@ static int mtk_disp_merge_probe(struct platform_device *pdev)
 		return PTR_ERR(priv->async_clk);
 	}
 
+	if (priv->async_clk) {
+		priv->reset_ctl = devm_reset_control_get_optional_exclusive(dev, NULL);
+		if (IS_ERR(priv->reset_ctl))
+			return PTR_ERR(priv->reset_ctl);
+	}
+
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
 	if (ret)
-- 
GitLab


From 5621416b11f4147585751fdaf714a06ffe2f57b6 Mon Sep 17 00:00:00 2001
From: "Nancy.Lin" <nancy.lin@mediatek.com>
Date: Mon, 20 Jun 2022 17:19:25 +0800
Subject: [PATCH 1245/1731] drm/mediatek: Add mediatek-drm plane color encoding
 info

Add plane color encoding information for color space conversion.
It's a preparation for adding support for mt8195 ovl_adaptor mdp_rdma
csc control.

Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220620091930.27797-10-nancy.lin@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_drm_plane.c | 1 +
 drivers/gpu/drm/mediatek/mtk_drm_plane.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
index e5fae4ec23370..39cb9a80d9766 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
@@ -138,6 +138,7 @@ static void mtk_plane_update_new_state(struct drm_plane_state *new_state,
 	mtk_plane_state->pending.width = drm_rect_width(&new_state->dst);
 	mtk_plane_state->pending.height = drm_rect_height(&new_state->dst);
 	mtk_plane_state->pending.rotation = new_state->rotation;
+	mtk_plane_state->pending.color_encoding = new_state->color_encoding;
 }
 
 static void mtk_plane_atomic_async_update(struct drm_plane *plane,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.h b/drivers/gpu/drm/mediatek/mtk_drm_plane.h
index d454bece95356..2d5ec66e3df1b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_plane.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.h
@@ -24,6 +24,7 @@ struct mtk_plane_pending_state {
 	bool				dirty;
 	bool				async_dirty;
 	bool				async_config;
+	enum drm_color_encoding		color_encoding;
 };
 
 struct mtk_plane_state {
-- 
GitLab


From 8524bb67145d8a2b495fabcd4b5643010ea43353 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Fri, 24 Jun 2022 14:03:27 -0700
Subject: [PATCH 1246/1731] drm/i915: Correct duplicated/misplaced GT register
 definitions

XEHPSDV_FLAT_CCS_BASE_ADDR, GEN8_L3_LRA_1_GPGPU, and MMCD_MISC_CTRL were
duplicated between i915_reg.h and intel_gt_regs.h.  These are all GT
registers, so we should drop the copy from i915_reg.h.

XEHPSDV_TILE0_ADDR_RANGE was defined in i915_reg.h, but really belongs
in intel_gt_regs.h.  Move it.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220624210328.308630-1-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c |  1 +
 drivers/gpu/drm/i915/gt/intel_gt_regs.h    |  3 +++
 drivers/gpu/drm/i915/i915_reg.h            | 17 -----------------
 3 files changed, 4 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index fa54823d12192..e63de9c065969 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -14,6 +14,7 @@
 #include "gem/i915_gem_region.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_mcr.h"
+#include "gt/intel_gt_regs.h"
 #include "gt/intel_region_lmem.h"
 #include "i915_drv.h"
 #include "i915_gem_stolen.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 07ef111947b8c..61815b6e87dee 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -324,6 +324,9 @@
 
 #define GEN12_PAT_INDEX(index)			_MMIO(0x4800 + (index) * 4)
 
+#define XEHPSDV_TILE0_ADDR_RANGE		_MMIO(0x4900)
+#define   XEHPSDV_TILE_LMEM_RANGE_SHIFT		8
+
 #define XEHPSDV_FLAT_CCS_BASE_ADDR		_MMIO(0x4910)
 #define   XEHPSDV_CCS_BASE_SHIFT		8
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 213f02d58fc8e..3ad7a2b5f47f2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8496,23 +8496,6 @@ enum skl_power_gate {
 #define   SGGI_DIS			REG_BIT(15)
 #define   SGR_DIS			REG_BIT(13)
 
-#define XEHPSDV_TILE0_ADDR_RANGE	_MMIO(0x4900)
-#define   XEHPSDV_TILE_LMEM_RANGE_SHIFT  8
-
-#define XEHPSDV_FLAT_CCS_BASE_ADDR	_MMIO(0x4910)
-#define   XEHPSDV_CCS_BASE_SHIFT	8
-
-/* gamt regs */
-#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
-#define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
-#define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV  0x5FF101FF /* max/min for LRA1/2 */
-#define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL  0x67F1427F /*    "        " */
-#define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT  0x5FF101FF /*    "        " */
-
-#define MMCD_MISC_CTRL		_MMIO(0x4ddc) /* skl+ */
-#define  MMCD_PCLA		(1 << 31)
-#define  MMCD_HOTSPOT_EN	(1 << 27)
-
 #define _ICL_PHY_MISC_A		0x64C00
 #define _ICL_PHY_MISC_B		0x64C04
 #define _DG2_PHY_MISC_TC1	0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
-- 
GitLab


From 7d8097073caa334ed6187a964645335324231e01 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Fri, 24 Jun 2022 14:03:28 -0700
Subject: [PATCH 1247/1731] drm/i915: Prefer "XEHP_" prefix for registers

We've been introducing new registers with a mix of "XEHP_"
(architecture) and "XEHPSDV_" (platform) prefixes.  For consistency,
let's settle on "XEHP_" as the preferred form.

XEHPSDV_RP_STATE_CAP stays with its current name since that's truly a
platform-specific register and not something that applies to the Xe_HP
architecture as a whole.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Caz Yokoyama <caz@caztech.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220624210328.308630-2-matthew.d.roper@intel.com
---
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c  | 4 ++--
 drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 8 ++++----
 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 4 ++--
 drivers/gpu/drm/i915/gt/intel_region_lmem.c | 8 ++++----
 drivers/gpu/drm/i915/i915_reg.h             | 6 +++---
 5 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index e63de9c065969..166d0a4b9e8c0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -836,8 +836,8 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
 	} else {
 		resource_size_t lmem_range;
 
-		lmem_range = intel_gt_mcr_read_any(&i915->gt0, XEHPSDV_TILE0_ADDR_RANGE) & 0xFFFF;
-		lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT;
+		lmem_range = intel_gt_mcr_read_any(&i915->gt0, XEHP_TILE0_ADDR_RANGE) & 0xFFFF;
+		lmem_size = lmem_range >> XEHP_TILE_LMEM_RANGE_SHIFT;
 		lmem_size *= SZ_1G;
 	}
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 61815b6e87dee..37c1095d8603b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -324,11 +324,11 @@
 
 #define GEN12_PAT_INDEX(index)			_MMIO(0x4800 + (index) * 4)
 
-#define XEHPSDV_TILE0_ADDR_RANGE		_MMIO(0x4900)
-#define   XEHPSDV_TILE_LMEM_RANGE_SHIFT		8
+#define XEHP_TILE0_ADDR_RANGE			_MMIO(0x4900)
+#define   XEHP_TILE_LMEM_RANGE_SHIFT		8
 
-#define XEHPSDV_FLAT_CCS_BASE_ADDR		_MMIO(0x4910)
-#define   XEHPSDV_CCS_BASE_SHIFT		8
+#define XEHP_FLAT_CCS_BASE_ADDR			_MMIO(0x4910)
+#define   XEHP_CCS_BASE_SHIFT			8
 
 #define GAMTARBMODE				_MMIO(0x4a08)
 #define   ARB_MODE_BWGTLB_DISABLE		(1 << 9)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index ae8a8f725f011..73a8b46e02344 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -679,7 +679,7 @@ static ssize_t media_RP0_freq_mhz_show(struct device *dev,
 	u32 val;
 	int err;
 
-	err = snb_pcode_read_p(gt->uncore, XEHPSDV_PCODE_FREQUENCY_CONFIG,
+	err = snb_pcode_read_p(gt->uncore, XEHP_PCODE_FREQUENCY_CONFIG,
 			       PCODE_MBOX_FC_SC_READ_FUSED_P0,
 			       PCODE_MBOX_DOMAIN_MEDIAFF, &val);
 
@@ -700,7 +700,7 @@ static ssize_t media_RPn_freq_mhz_show(struct device *dev,
 	u32 val;
 	int err;
 
-	err = snb_pcode_read_p(gt->uncore, XEHPSDV_PCODE_FREQUENCY_CONFIG,
+	err = snb_pcode_read_p(gt->uncore, XEHP_PCODE_FREQUENCY_CONFIG,
 			       PCODE_MBOX_FC_SC_READ_FUSED_PN,
 			       PCODE_MBOX_DOMAIN_MEDIAFF, &val);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 2ff4480470207..d09b996a97594 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -105,12 +105,12 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
 		resource_size_t lmem_range;
 		u64 tile_stolen, flat_ccs_base;
 
-		lmem_range = intel_gt_mcr_read_any(&i915->gt0, XEHPSDV_TILE0_ADDR_RANGE) & 0xFFFF;
-		lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT;
+		lmem_range = intel_gt_mcr_read_any(&i915->gt0, XEHP_TILE0_ADDR_RANGE) & 0xFFFF;
+		lmem_size = lmem_range >> XEHP_TILE_LMEM_RANGE_SHIFT;
 		lmem_size *= SZ_1G;
 
-		flat_ccs_base = intel_gt_mcr_read_any(gt, XEHPSDV_FLAT_CCS_BASE_ADDR);
-		flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT) * SZ_64K;
+		flat_ccs_base = intel_gt_mcr_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
+		flat_ccs_base = (flat_ccs_base >> XEHP_CCS_BASE_SHIFT) * SZ_64K;
 
 		/* FIXME: Remove this when we have small-bar enabled */
 		if (pci_resource_len(pdev, 2) < lmem_size) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3ad7a2b5f47f2..63f1f04b21a7f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6767,12 +6767,12 @@
 #define     DG1_UNCORE_GET_INIT_STATUS		0x0
 #define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
-#define   XEHPSDV_PCODE_FREQUENCY_CONFIG		0x6e	/* xehpsdv, pvc */
-/* XEHPSDV_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
+#define   XEHP_PCODE_FREQUENCY_CONFIG		0x6e	/* xehpsdv, pvc */
+/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
 #define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
 #define     PCODE_MBOX_FC_SC_READ_FUSED_PN	0x1
 /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
-/*   XEHPSDV_PCODE_FREQUENCY_CONFIG param2 */
+/*   XEHP_PCODE_FREQUENCY_CONFIG param2 */
 #define     PCODE_MBOX_DOMAIN_NONE		0x0
 #define     PCODE_MBOX_DOMAIN_MEDIAFF		0x3
 #define GEN6_PCODE_DATA				_MMIO(0x138128)
-- 
GitLab


From 9efdd519d001ee3e761f6ff80d5eb123387421c1 Mon Sep 17 00:00:00 2001
From: katrinzhou <katrinzhou@tencent.com>
Date: Tue, 21 Jun 2022 13:49:26 +0100
Subject: [PATCH 1248/1731] drm/i915/gem: add missing else

Add missing else in set_proto_ctx_param() to fix coverity issue.

Addresses-Coverity: ("Unused value")
Fixes: d4433c7600f7 ("drm/i915/gem: Use the proto-context to handle create parameters (v5)")
Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: katrinzhou <katrinzhou@tencent.com>
[tursulin: fixup alignment]
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220621124926.615884-1-tvrtko.ursulin@linux.intel.com
(cherry picked from commit 7482a65664c16cc88eb84d2b545a1fed887378a1)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ab4c5ab28e4d9..321af109d484f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -933,8 +933,9 @@ static int set_proto_ctx_param(struct drm_i915_file_private *fpriv,
 	case I915_CONTEXT_PARAM_PERSISTENCE:
 		if (args->size)
 			ret = -EINVAL;
-		ret = proto_context_set_persistence(fpriv->dev_priv, pc,
-						    args->value);
+		else
+			ret = proto_context_set_persistence(fpriv->dev_priv, pc,
+							    args->value);
 		break;
 
 	case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
-- 
GitLab


From 7d23a80dc9720a378707edc03a7275d5a372355f Mon Sep 17 00:00:00 2001
From: Anshuman Gupta <anshuman.gupta@intel.com>
Date: Thu, 16 Jun 2022 17:52:49 +0530
Subject: [PATCH 1249/1731] drm/i915/dgfx: Disable d3cold at gfx root port

Currently i915 disables d3cold for i915 pci dev.
This blocks D3 for i915 gfx pci upstream bridge (VSP).
Let's disable d3cold at gfx root port to make sure that
i915 gfx VSP can transition to D3 to save some power.

We don't need to disable/enable d3cold in rpm, s2idle
suspend/resume handlers. Disabling/Enabling d3cold at
gfx root port in probe/remove phase is sufficient.

Fixes: 1a085e23411d ("drm/i915: Disable D3Cold in s2idle and runtime pm")
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Reviewed-by: Badal Nilawar <badal.nilawar@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220616122249.5007-1-anshuman.gupta@intel.com
(cherry picked from commit 138c2fca6f408f397ea8fbbbf33203f244d96e01)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_driver.c | 34 +++++++++++++-----------------
 1 file changed, 15 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 90b0ce5051aff..1041b5340465f 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -530,6 +530,7 @@ mask_err:
 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 {
 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+	struct pci_dev *root_pdev;
 	int ret;
 
 	if (i915_inject_probe_failure(dev_priv))
@@ -641,6 +642,15 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 
 	intel_bw_init_hw(dev_priv);
 
+	/*
+	 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
+	 * This should be totally removed when we handle the pci states properly
+	 * on runtime PM and on s2idle cases.
+	 */
+	root_pdev = pcie_find_root_port(pdev);
+	if (root_pdev)
+		pci_d3cold_disable(root_pdev);
+
 	return 0;
 
 err_msi:
@@ -664,11 +674,16 @@ err_perf:
 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
 {
 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+	struct pci_dev *root_pdev;
 
 	i915_perf_fini(dev_priv);
 
 	if (pdev->msi_enabled)
 		pci_disable_msi(pdev);
+
+	root_pdev = pcie_find_root_port(pdev);
+	if (root_pdev)
+		pci_d3cold_enable(root_pdev);
 }
 
 /**
@@ -1193,14 +1208,6 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
 		goto out;
 	}
 
-	/*
-	 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
-	 * This should be totally removed when we handle the pci states properly
-	 * on runtime PM and on s2idle cases.
-	 */
-	if (suspend_to_idle(dev_priv))
-		pci_d3cold_disable(pdev);
-
 	pci_disable_device(pdev);
 	/*
 	 * During hibernation on some platforms the BIOS may try to access
@@ -1365,8 +1372,6 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
 	pci_set_master(pdev);
 
-	pci_d3cold_enable(pdev);
-
 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
 	ret = vlv_resume_prepare(dev_priv, false);
@@ -1543,7 +1548,6 @@ static int intel_runtime_suspend(struct device *kdev)
 {
 	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
 	struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
-	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 	int ret;
 
 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
@@ -1589,12 +1593,6 @@ static int intel_runtime_suspend(struct device *kdev)
 		drm_err(&dev_priv->drm,
 			"Unclaimed access detected prior to suspending\n");
 
-	/*
-	 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
-	 * This should be totally removed when we handle the pci states properly
-	 * on runtime PM and on s2idle cases.
-	 */
-	pci_d3cold_disable(pdev);
 	rpm->suspended = true;
 
 	/*
@@ -1633,7 +1631,6 @@ static int intel_runtime_resume(struct device *kdev)
 {
 	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
 	struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
-	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 	int ret;
 
 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
@@ -1646,7 +1643,6 @@ static int intel_runtime_resume(struct device *kdev)
 
 	intel_opregion_notify_adapter(dev_priv, PCI_D0);
 	rpm->suspended = false;
-	pci_d3cold_enable(pdev);
 	if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
 		drm_dbg(&dev_priv->drm,
 			"Unclaimed access during suspend, bios?\n");
-- 
GitLab


From 79538490fd7ade244dba400923e792519a2bdfea Mon Sep 17 00:00:00 2001
From: Matthew Auld <matthew.auld@intel.com>
Date: Wed, 22 Jun 2022 16:59:19 +0100
Subject: [PATCH 1250/1731] drm/i915: tweak the ordering in
 cpu_write_needs_clflush
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

For imported dma-buf objects we leave the object as cache_coherent = 0
across all platforms, which is reasonable given that have no clue what
the memory underneath is, and its not like the driver can ever manually
clflush the pages anyway (like with i915_gem_clflush_object) for such
objects. However on discrete we choose to treat cache_dirty = true as a
programmer error, leading to a warning. The simplest fix looks to be to
just change the ordering in cpu_write_needs_clflush to prevent ever
setting cache_dirty for dma-buf objects on discrete.

Fixes: d028a7690d87 ("drm/i915/dmabuf: Fix prime_mmap to work when using LMEM")
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5266
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220622155919.355081-1-matthew.auld@intel.com
(cherry picked from commit 563aaf4a928def2d36d1b3de0a4b515e2477b4da)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_domain.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 3e5d6057b3ef9..1674b0c5802bf 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -35,12 +35,12 @@ bool i915_gem_cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
 	if (obj->cache_dirty)
 		return false;
 
-	if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE))
-		return true;
-
 	if (IS_DGFX(i915))
 		return false;
 
+	if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE))
+		return true;
+
 	/* Currently in use by HW (display engine)? Keep flushed. */
 	return i915_gem_object_is_framebuffer(obj);
 }
-- 
GitLab


From 3cdcdc34f35eb4616f7e5954cbdcd3390da8eae4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Wed, 13 Apr 2022 22:26:07 +0300
Subject: [PATCH 1251/1731] drm/i915: Eliminate PIPECONF RMWs from
 .color_commit()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Eliminate the PIPECONF RMWs from .comit_commit() so
that we can finally declare the whole vblank evade part
(and the noarm() part) of the pipe commit free of register
reads. Or at least I hope that's the last read...

Only the i9xx/ilk codepaths need this for now, but let's
add the same thing for hsw+ just in case we want to start
calling that during fastsets at some point (eg. to change
dithering settings/etc.).

Should open up the way to start experimenting with
different DSB usage approaches for pipe commits.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220413192607.27533-1-ville.syrjala@linux.intel.com
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c   | 21 ++++----------
 drivers/gpu/drm/i915/display/intel_display.c | 30 ++++++++++++++------
 drivers/gpu/drm/i915/display/intel_display.h |  2 ++
 3 files changed, 29 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index a27ce874a9e86..4350595640de8 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -505,30 +505,19 @@ static void ilk_color_commit_noarm(const struct intel_crtc_state *crtc_state)
 
 static void i9xx_color_commit_arm(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum pipe pipe = crtc->pipe;
-	u32 val;
-
-	val = intel_de_read(dev_priv, PIPECONF(pipe));
-	val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX;
-	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
-	intel_de_write(dev_priv, PIPECONF(pipe), val);
+	/* update PIPECONF GAMMA_MODE */
+	i9xx_set_pipeconf(crtc_state);
 }
 
 static void ilk_color_commit_arm(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum pipe pipe = crtc->pipe;
-	u32 val;
 
-	val = intel_de_read(dev_priv, PIPECONF(pipe));
-	val &= ~PIPECONF_GAMMA_MODE_MASK_ILK;
-	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
-	intel_de_write(dev_priv, PIPECONF(pipe), val);
+	/* update PIPECONF GAMMA_MODE */
+	ilk_set_pipeconf(crtc_state);
 
-	intel_de_write_fw(dev_priv, PIPE_CSC_MODE(pipe),
+	intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe),
 			  crtc_state->csc_mode);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8f29df6cca85d..6a0a0cb064950 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -126,8 +126,6 @@
 
 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
-static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
-static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
@@ -3015,14 +3013,18 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
 	intel_bigjoiner_adjust_pipe_src(pipe_config);
 }
 
-static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
+void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 pipeconf = 0;
 
-	/* we keep both pipes enabled on 830 */
-	if (IS_I830(dev_priv))
+	/*
+	 * - We keep both pipes enabled on 830
+	 * - During modeset the pipe is still disabled and must remain so
+	 * - During fastset the pipe is already enabled and must remain so
+	 */
+	if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state))
 		pipeconf |= PIPECONF_ENABLE;
 
 	if (crtc_state->double_wide)
@@ -3335,14 +3337,19 @@ out:
 	return ret;
 }
 
-static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
+void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
-	u32 val;
+	u32 val = 0;
 
-	val = 0;
+	/*
+	 * - During modeset the pipe is still disabled and must remain so
+	 * - During fastset the pipe is already enabled and must remain so
+	 */
+	if (!intel_crtc_needs_modeset(crtc_state))
+		val |= PIPECONF_ENABLE;
 
 	switch (crtc_state->pipe_bpp) {
 	default:
@@ -3401,6 +3408,13 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	u32 val = 0;
 
+	/*
+	 * - During modeset the pipe is still disabled and must remain so
+	 * - During fastset the pipe is already enabled and must remain so
+	 */
+	if (!intel_crtc_needs_modeset(crtc_state))
+		val |= PIPECONF_ENABLE;
+
 	if (IS_HASWELL(dev_priv) && crtc_state->dither)
 		val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 8610e17cc5934..9724a873c0b93 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -567,6 +567,8 @@ bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state);
 
 void intel_plane_destroy(struct drm_plane *plane);
+void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
+void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);
 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
-- 
GitLab


From 04155815dbb8320ecd17dd54e85c9a5ae5d63bb9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Thu, 23 Jun 2022 16:08:52 +0300
Subject: [PATCH 1252/1731] drm/i915: Move dbuf details to INTEL_INFO->display
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

DBUF is a display thing, so move it into the display
portion of the device info.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220623130900.26078-2-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.h   |  2 +-
 .../gpu/drm/i915/display/intel_display_power.c |  2 +-
 drivers/gpu/drm/i915/i915_pci.c                | 18 +++++++++---------
 drivers/gpu/drm/i915/intel_device_info.h       |  9 +++++----
 drivers/gpu/drm/i915/intel_pm.c                |  8 ++++----
 5 files changed, 20 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 9724a873c0b93..fa53710362395 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -193,7 +193,7 @@ enum plane_id {
 
 #define for_each_dbuf_slice(__dev_priv, __slice) \
 	for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
-		for_each_if(INTEL_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
+		for_each_if(INTEL_INFO(__dev_priv)->display.dbuf.slice_mask & BIT(__slice))
 
 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
 	for_each_dbuf_slice((__dev_priv), (__slice)) \
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index fb17439bd4f8a..a9cb27f1c964a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1038,7 +1038,7 @@ void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
 			     u8 req_slices)
 {
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
-	u8 slice_mask = INTEL_INFO(dev_priv)->dbuf.slice_mask;
+	u8 slice_mask = INTEL_INFO(dev_priv)->display.dbuf.slice_mask;
 	enum dbuf_slice slice;
 
 	drm_WARN(&dev_priv->drm, req_slices & ~slice_mask,
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1e5c40f36798f..b6b7d8eb5b577 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -649,8 +649,8 @@ static const struct intel_device_info chv_info = {
 	.display.has_ipc = 1, \
 	.display.has_psr = 1, \
 	.display.has_psr_hw_tracking = 1, \
-	.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
-	.dbuf.slice_mask = BIT(DBUF_S1)
+	.display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
+	.display.dbuf.slice_mask = BIT(DBUF_S1)
 
 #define SKL_PLATFORM \
 	GEN9_FEATURES, \
@@ -685,7 +685,7 @@ static const struct intel_device_info skl_gt4_info = {
 #define GEN9_LP_FEATURES \
 	GEN(9), \
 	.is_lp = 1, \
-	.dbuf.slice_mask = BIT(DBUF_S1), \
+	.display.dbuf.slice_mask = BIT(DBUF_S1), \
 	.display.has_hotplug = 1, \
 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
@@ -722,14 +722,14 @@ static const struct intel_device_info skl_gt4_info = {
 static const struct intel_device_info bxt_info = {
 	GEN9_LP_FEATURES,
 	PLATFORM(INTEL_BROXTON),
-	.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
+	.display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
 };
 
 static const struct intel_device_info glk_info = {
 	GEN9_LP_FEATURES,
 	PLATFORM(INTEL_GEMINILAKE),
 	.display.ver = 10,
-	.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
+	.display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
 	GLK_COLORS,
 };
 
@@ -819,8 +819,8 @@ static const struct intel_device_info cml_gt2_info = {
 	}, \
 	GEN(11), \
 	ICL_COLORS, \
-	.dbuf.size = 2048, \
-	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
+	.display.dbuf.size = 2048, \
+	.display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
 	.display.has_dsc = 1, \
 	.has_coherent_ggtt = false, \
 	.has_logical_ring_elsq = 1
@@ -942,8 +942,8 @@ static const struct intel_device_info adl_s_info = {
 		   .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |		\
 					DRM_COLOR_LUT_EQUAL_CHANNELS,		\
 	},									\
-	.dbuf.size = 4096,							\
-	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |		\
+	.display.dbuf.size = 4096,						\
+	.display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |	\
 		BIT(DBUF_S4),							\
 	.display.has_ddi = 1,							\
 	.display.has_dmc = 1,							\
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index eb3a37808e1dd..f14183d54c69d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -225,15 +225,16 @@ struct intel_device_info {
 		u8 fbc_mask;
 		u8 abox_mask;
 
+		struct {
+			u16 size; /* in blocks */
+			u8 slice_mask;
+		} dbuf;
+
 #define DEFINE_FLAG(name) u8 name:1
 		DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
 #undef DEFINE_FLAG
 	} display;
 
-	struct {
-		u16 size; /* in blocks */
-		u8 slice_mask;
-	} dbuf;
 
 	/* Register offsets for the various display pipes and transcoders */
 	int pipe_offsets[I915_MAX_TRANSCODERS];
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 25069751bd6c7..7b5fbede79739 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4100,8 +4100,8 @@ static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry,
 
 static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv)
 {
-	return INTEL_INFO(dev_priv)->dbuf.size /
-		hweight8(INTEL_INFO(dev_priv)->dbuf.slice_mask);
+	return INTEL_INFO(dev_priv)->display.dbuf.size /
+		hweight8(INTEL_INFO(dev_priv)->display.dbuf.slice_mask);
 }
 
 static void
@@ -4120,7 +4120,7 @@ skl_ddb_entry_for_slices(struct drm_i915_private *dev_priv, u8 slice_mask,
 	ddb->end = fls(slice_mask) * slice_size;
 
 	WARN_ON(ddb->start >= ddb->end);
-	WARN_ON(ddb->end > INTEL_INFO(dev_priv)->dbuf.size);
+	WARN_ON(ddb->end > INTEL_INFO(dev_priv)->display.dbuf.size);
 }
 
 static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask)
@@ -6095,7 +6095,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
 			    "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
 			    old_dbuf_state->enabled_slices,
 			    new_dbuf_state->enabled_slices,
-			    INTEL_INFO(dev_priv)->dbuf.slice_mask,
+			    INTEL_INFO(dev_priv)->display.dbuf.slice_mask,
 			    str_yes_no(old_dbuf_state->joined_mbus),
 			    str_yes_no(new_dbuf_state->joined_mbus));
 	}
-- 
GitLab


From 4ce7e51dc712f8a006ce6abcc49f788c79287c03 Mon Sep 17 00:00:00 2001
From: Bo Liu <liubo03@inspur.com>
Date: Thu, 16 Jun 2022 01:50:52 -0400
Subject: [PATCH 1253/1731] firmware: arm_scmi: Remove usage of the deprecated
 ida_simple_xxx API

Replace the deprecated ida_simple_{get,remove} with ida_{alloc,free}.

Link: https://lore.kernel.org/r/20220616055052.4559-1-liubo03@inspur.com
Signed-off-by: Bo Liu <liubo03@inspur.com>
[sudeep.holla: Replace ida_alloc_min with ida_alloc as suggested by Cristian]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
 drivers/firmware/arm_scmi/bus.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/firmware/arm_scmi/bus.c b/drivers/firmware/arm_scmi/bus.c
index f6fe723ab869e..d4e23101448ae 100644
--- a/drivers/firmware/arm_scmi/bus.c
+++ b/drivers/firmware/arm_scmi/bus.c
@@ -181,7 +181,7 @@ scmi_device_create(struct device_node *np, struct device *parent, int protocol,
 		return NULL;
 	}
 
-	id = ida_simple_get(&scmi_bus_id, 1, 0, GFP_KERNEL);
+	id = ida_alloc_min(&scmi_bus_id, 1, GFP_KERNEL);
 	if (id < 0) {
 		kfree_const(scmi_dev->name);
 		kfree(scmi_dev);
@@ -204,7 +204,7 @@ scmi_device_create(struct device_node *np, struct device *parent, int protocol,
 put_dev:
 	kfree_const(scmi_dev->name);
 	put_device(&scmi_dev->dev);
-	ida_simple_remove(&scmi_bus_id, id);
+	ida_free(&scmi_bus_id, id);
 	return NULL;
 }
 
@@ -212,7 +212,7 @@ void scmi_device_destroy(struct scmi_device *scmi_dev)
 {
 	kfree_const(scmi_dev->name);
 	scmi_handle_put(scmi_dev->handle);
-	ida_simple_remove(&scmi_bus_id, scmi_dev->id);
+	ida_free(&scmi_bus_id, scmi_dev->id);
 	device_unregister(&scmi_dev->dev);
 }
 
-- 
GitLab


From 12d74553726675b5c991251f349422a24c575e56 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Thu, 23 Jun 2022 16:08:53 +0300
Subject: [PATCH 1254/1731] drm/i915: Move pipe_offsets[] & co. to
 INTEL_INFO->display
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The display register offsets are display stuff so stick
into the display portion of the device info.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220623130900.26078-3-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c          | 44 ++++++++++++------------
 drivers/gpu/drm/i915/i915_reg.h          | 18 +++++-----
 drivers/gpu/drm/i915/intel_device_info.h | 10 +++---
 3 files changed, 36 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b6b7d8eb5b577..b7379d671657a 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -38,43 +38,43 @@
 	.display.ver = (x)
 
 #define I845_PIPE_OFFSETS \
-	.pipe_offsets = { \
+	.display.pipe_offsets = { \
 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
 	}, \
-	.trans_offsets = { \
+	.display.trans_offsets = { \
 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 	}
 
 #define I9XX_PIPE_OFFSETS \
-	.pipe_offsets = { \
+	.display.pipe_offsets = { \
 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
 		[TRANSCODER_B] = PIPE_B_OFFSET, \
 	}, \
-	.trans_offsets = { \
+	.display.trans_offsets = { \
 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 	}
 
 #define IVB_PIPE_OFFSETS \
-	.pipe_offsets = { \
+	.display.pipe_offsets = { \
 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
 		[TRANSCODER_B] = PIPE_B_OFFSET, \
 		[TRANSCODER_C] = PIPE_C_OFFSET, \
 	}, \
-	.trans_offsets = { \
+	.display.trans_offsets = { \
 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 	}
 
 #define HSW_PIPE_OFFSETS \
-	.pipe_offsets = { \
+	.display.pipe_offsets = { \
 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
 		[TRANSCODER_B] = PIPE_B_OFFSET, \
 		[TRANSCODER_C] = PIPE_C_OFFSET, \
 		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
 	}, \
-	.trans_offsets = { \
+	.display.trans_offsets = { \
 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
@@ -82,44 +82,44 @@
 	}
 
 #define CHV_PIPE_OFFSETS \
-	.pipe_offsets = { \
+	.display.pipe_offsets = { \
 		[TRANSCODER_A] = PIPE_A_OFFSET, \
 		[TRANSCODER_B] = PIPE_B_OFFSET, \
 		[TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
 	}, \
-	.trans_offsets = { \
+	.display.trans_offsets = { \
 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 		[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
 	}
 
 #define I845_CURSOR_OFFSETS \
-	.cursor_offsets = { \
+	.display.cursor_offsets = { \
 		[PIPE_A] = CURSOR_A_OFFSET, \
 	}
 
 #define I9XX_CURSOR_OFFSETS \
-	.cursor_offsets = { \
+	.display.cursor_offsets = { \
 		[PIPE_A] = CURSOR_A_OFFSET, \
 		[PIPE_B] = CURSOR_B_OFFSET, \
 	}
 
 #define CHV_CURSOR_OFFSETS \
-	.cursor_offsets = { \
+	.display.cursor_offsets = { \
 		[PIPE_A] = CURSOR_A_OFFSET, \
 		[PIPE_B] = CURSOR_B_OFFSET, \
 		[PIPE_C] = CHV_CURSOR_C_OFFSET, \
 	}
 
 #define IVB_CURSOR_OFFSETS \
-	.cursor_offsets = { \
+	.display.cursor_offsets = { \
 		[PIPE_A] = CURSOR_A_OFFSET, \
 		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
 		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
 	}
 
 #define TGL_CURSOR_OFFSETS \
-	.cursor_offsets = { \
+	.display.cursor_offsets = { \
 		[PIPE_A] = CURSOR_A_OFFSET, \
 		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
 		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
@@ -801,7 +801,7 @@ static const struct intel_device_info cml_gt2_info = {
 	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
-	.pipe_offsets = { \
+	.display.pipe_offsets = { \
 		[TRANSCODER_A] = PIPE_A_OFFSET, \
 		[TRANSCODER_B] = PIPE_B_OFFSET, \
 		[TRANSCODER_C] = PIPE_C_OFFSET, \
@@ -809,7 +809,7 @@ static const struct intel_device_info cml_gt2_info = {
 		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 	}, \
-	.trans_offsets = { \
+	.display.trans_offsets = { \
 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
@@ -854,7 +854,7 @@ static const struct intel_device_info jsl_info = {
 	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
 		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
-	.pipe_offsets = { \
+	.display.pipe_offsets = { \
 		[TRANSCODER_A] = PIPE_A_OFFSET, \
 		[TRANSCODER_B] = PIPE_B_OFFSET, \
 		[TRANSCODER_C] = PIPE_C_OFFSET, \
@@ -862,7 +862,7 @@ static const struct intel_device_info jsl_info = {
 		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 	}, \
-	.trans_offsets = { \
+	.display.trans_offsets = { \
 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
@@ -929,7 +929,7 @@ static const struct intel_device_info adl_s_info = {
 };
 
 #define XE_LPD_CURSOR_OFFSETS \
-	.cursor_offsets = { \
+	.display.cursor_offsets = { \
 		[PIPE_A] = CURSOR_A_OFFSET, \
 		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
 		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
@@ -958,7 +958,7 @@ static const struct intel_device_info adl_s_info = {
 	.display.has_psr = 1,							\
 	.display.ver = 13,							\
 	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),	\
-	.pipe_offsets = {							\
+	.display.pipe_offsets = {						\
 		[TRANSCODER_A] = PIPE_A_OFFSET,					\
 		[TRANSCODER_B] = PIPE_B_OFFSET,					\
 		[TRANSCODER_C] = PIPE_C_OFFSET,					\
@@ -966,7 +966,7 @@ static const struct intel_device_info adl_s_info = {
 		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,				\
 		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,				\
 	},									\
-	.trans_offsets = {							\
+	.display.trans_offsets = {						\
 		[TRANSCODER_A] = TRANSCODER_A_OFFSET,				\
 		[TRANSCODER_B] = TRANSCODER_B_OFFSET,				\
 		[TRANSCODER_C] = TRANSCODER_C_OFFSET,				\
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cc608e264e23e..e59d0b0123c96 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -161,16 +161,16 @@
  * Device info offset array based helpers for groups of registers with unevenly
  * spaced base offsets.
  */
-#define _MMIO_PIPE2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
-					      INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
-					      DISPLAY_MMIO_BASE(dev_priv))
-#define _TRANS2(tran, reg)		(INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \
-					 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
-					 DISPLAY_MMIO_BASE(dev_priv))
+#define _MMIO_PIPE2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \
+					      INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \
+					      DISPLAY_MMIO_BASE(dev_priv) + (reg))
+#define _TRANS2(tran, reg)		(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \
+					 INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
+					 DISPLAY_MMIO_BASE(dev_priv) + (reg))
 #define _MMIO_TRANS2(tran, reg)		_MMIO(_TRANS2(tran, reg))
-#define _CURSOR2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
-					      INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
-					      DISPLAY_MMIO_BASE(dev_priv))
+#define _CURSOR2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
+					      INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \
+					      DISPLAY_MMIO_BASE(dev_priv) + (reg))
 
 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
 #define _MASKED_FIELD(mask, value) ({					   \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index f14183d54c69d..ab439875da300 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -233,13 +233,13 @@ struct intel_device_info {
 #define DEFINE_FLAG(name) u8 name:1
 		DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
 #undef DEFINE_FLAG
-	} display;
 
+		/* Register offsets for the various display pipes and transcoders */
+		int pipe_offsets[I915_MAX_TRANSCODERS];
+		int trans_offsets[I915_MAX_TRANSCODERS];
+		int cursor_offsets[I915_MAX_PIPES];
+	} display;
 
-	/* Register offsets for the various display pipes and transcoders */
-	int pipe_offsets[I915_MAX_TRANSCODERS];
-	int trans_offsets[I915_MAX_TRANSCODERS];
-	int cursor_offsets[I915_MAX_PIPES];
 
 	struct color_luts {
 		u32 degamma_lut_size;
-- 
GitLab


From c92df6aa397b5a37cf06004a219b4fdf26234dd6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Thu, 23 Jun 2022 16:08:54 +0300
Subject: [PATCH 1255/1731] drm/i915: Move display_mmio_offset under
 INTEL_INFO->display
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The display register offsets are display stuff so stick
into the display portion of the device info.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220623130900.26078-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c          | 4 ++--
 drivers/gpu/drm/i915/i915_reg.h          | 2 +-
 drivers/gpu/drm/i915/intel_device_info.h | 5 +++--
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b7379d671657a..a2d3b61f0246b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -529,7 +529,7 @@ static const struct intel_device_info vlv_info = {
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
-	.display_mmio_offset = VLV_DISPLAY_BASE,
+	.display.mmio_offset = VLV_DISPLAY_BASE,
 	I9XX_PIPE_OFFSETS,
 	I9XX_CURSOR_OFFSETS,
 	I965_COLORS,
@@ -627,7 +627,7 @@ static const struct intel_device_info chv_info = {
 	.has_reset_engine = 1,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
-	.display_mmio_offset = VLV_DISPLAY_BASE,
+	.display.mmio_offset = VLV_DISPLAY_BASE,
 	CHV_PIPE_OFFSETS,
 	CHV_CURSOR_OFFSETS,
 	CHV_COLORS,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e59d0b0123c96..76c47f699e708 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -115,7 +115,7 @@
  *  #define GEN8_BAR                    _MMIO(0xb888)
  */
 
-#define DISPLAY_MMIO_BASE(dev_priv)	(INTEL_INFO(dev_priv)->display_mmio_offset)
+#define DISPLAY_MMIO_BASE(dev_priv)	(INTEL_INFO(dev_priv)->display.mmio_offset)
 
 /*
  * Given the first two numbers __a and __b of arbitrarily many evenly spaced
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index ab439875da300..f55a1643ae04d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -208,8 +208,6 @@ struct intel_device_info {
 
 	u32 memory_regions; /* regions supported by the HW */
 
-	u32 display_mmio_offset;
-
 	u8 gt; /* GT number, 0 if undefined */
 
 #define DEFINE_FLAG(name) u8 name:1
@@ -234,6 +232,9 @@ struct intel_device_info {
 		DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
 #undef DEFINE_FLAG
 
+		/* Global register offset for the display engine */
+		u32 mmio_offset;
+
 		/* Register offsets for the various display pipes and transcoders */
 		int pipe_offsets[I915_MAX_TRANSCODERS];
 		int trans_offsets[I915_MAX_TRANSCODERS];
-- 
GitLab


From 5ba584ec1101cd63081ba7c228849acef962f6b9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Thu, 23 Jun 2022 16:08:55 +0300
Subject: [PATCH 1256/1731] drm/i915: Make pipe_offsets[] & co. u32
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Using a signed type for the register offsets doesn't really
make sense. Switch to u32.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220623130900.26078-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_device_info.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index f55a1643ae04d..7e50c778c78ed 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -236,9 +236,9 @@ struct intel_device_info {
 		u32 mmio_offset;
 
 		/* Register offsets for the various display pipes and transcoders */
-		int pipe_offsets[I915_MAX_TRANSCODERS];
-		int trans_offsets[I915_MAX_TRANSCODERS];
-		int cursor_offsets[I915_MAX_PIPES];
+		u32 pipe_offsets[I915_MAX_TRANSCODERS];
+		u32 trans_offsets[I915_MAX_TRANSCODERS];
+		u32 cursor_offsets[I915_MAX_PIPES];
 	} display;
 
 
-- 
GitLab


From d5a680548eddca0e2e01fb84b85c1f7687355e21 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Thu, 23 Jun 2022 16:08:56 +0300
Subject: [PATCH 1257/1731] drm/i915: s/_CURSOR2/_MMIO_CURSOR2//
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The other similar macros have the _MMIO prefix, so give
it also to _CURSOR2.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220623130900.26078-6-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 76c47f699e708..b8c254d8d6b63 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -168,7 +168,7 @@
 					 INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
 					 DISPLAY_MMIO_BASE(dev_priv) + (reg))
 #define _MMIO_TRANS2(tran, reg)		_MMIO(_TRANS2(tran, reg))
-#define _CURSOR2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
+#define _MMIO_CURSOR2(pipe, reg)	_MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
 					      INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \
 					      DISPLAY_MMIO_BASE(dev_priv) + (reg))
 
@@ -4304,12 +4304,12 @@
 #define _CURBBASE_IVB		0x71084
 #define _CURBPOS_IVB		0x71088
 
-#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
-#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
-#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
-#define CURSIZE(pipe) _CURSOR2(pipe, _CURASIZE)
-#define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
-#define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
+#define CURCNTR(pipe) _MMIO_CURSOR2(pipe, _CURACNTR)
+#define CURBASE(pipe) _MMIO_CURSOR2(pipe, _CURABASE)
+#define CURPOS(pipe) _MMIO_CURSOR2(pipe, _CURAPOS)
+#define CURSIZE(pipe) _MMIO_CURSOR2(pipe, _CURASIZE)
+#define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(pipe, _CUR_FBC_CTL_A)
+#define CURSURFLIVE(pipe) _MMIO_CURSOR2(pipe, _CURASURFLIVE)
 
 #define CURSOR_A_OFFSET 0x70080
 #define CURSOR_B_OFFSET 0x700c0
-- 
GitLab


From 2e25ae522164e8586520ef20bddbb41c97b0057a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Thu, 23 Jun 2022 16:08:57 +0300
Subject: [PATCH 1258/1731] drm/i915: Use _MMIO_TRANS2() where appropriate
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Stop hand rolling _MMIO_TRANS2() and just use the real thing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220623130900.26078-7-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 19 +++++++++----------
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b8c254d8d6b63..3f0ad77c083a2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -164,10 +164,9 @@
 #define _MMIO_PIPE2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \
 					      INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \
 					      DISPLAY_MMIO_BASE(dev_priv) + (reg))
-#define _TRANS2(tran, reg)		(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \
-					 INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
-					 DISPLAY_MMIO_BASE(dev_priv) + (reg))
-#define _MMIO_TRANS2(tran, reg)		_MMIO(_TRANS2(tran, reg))
+#define _MMIO_TRANS2(tran, reg)		_MMIO(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \
+					      INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
+					      DISPLAY_MMIO_BASE(dev_priv) + (reg))
 #define _MMIO_CURSOR2(pipe, reg)	_MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
 					      INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \
 					      DISPLAY_MMIO_BASE(dev_priv) + (reg))
@@ -2147,7 +2146,7 @@
  */
 #define _SRD_CTL_A				0x60800
 #define _SRD_CTL_EDP				0x6f800
-#define EDP_PSR_CTL(tran)			_MMIO(_TRANS2(tran, _SRD_CTL_A))
+#define EDP_PSR_CTL(tran)			_MMIO_TRANS2(tran, _SRD_CTL_A)
 #define   EDP_PSR_ENABLE			(1 << 31)
 #define   BDW_PSR_SINGLE_FRAME			(1 << 30)
 #define   EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK	(1 << 29) /* SW can't modify */
@@ -2193,11 +2192,11 @@
 
 #define _SRD_AUX_DATA_A				0x60814
 #define _SRD_AUX_DATA_EDP			0x6f814
-#define EDP_PSR_AUX_DATA(tran, i)		_MMIO(_TRANS2(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */
+#define EDP_PSR_AUX_DATA(tran, i)		_MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) + 4) /* 5 registers */
 
 #define _SRD_STATUS_A				0x60840
 #define _SRD_STATUS_EDP				0x6f840
-#define EDP_PSR_STATUS(tran)			_MMIO(_TRANS2(tran, _SRD_STATUS_A))
+#define EDP_PSR_STATUS(tran)			_MMIO_TRANS2(tran, _SRD_STATUS_A)
 #define   EDP_PSR_STATUS_STATE_MASK		(7 << 29)
 #define   EDP_PSR_STATUS_STATE_SHIFT		29
 #define   EDP_PSR_STATUS_STATE_IDLE		(0 << 29)
@@ -2224,13 +2223,13 @@
 
 #define _SRD_PERF_CNT_A			0x60844
 #define _SRD_PERF_CNT_EDP		0x6f844
-#define EDP_PSR_PERF_CNT(tran)		_MMIO(_TRANS2(tran, _SRD_PERF_CNT_A))
+#define EDP_PSR_PERF_CNT(tran)		_MMIO_TRANS2(tran, _SRD_PERF_CNT_A)
 #define   EDP_PSR_PERF_CNT_MASK		0xffffff
 
 /* PSR_MASK on SKL+ */
 #define _SRD_DEBUG_A				0x60860
 #define _SRD_DEBUG_EDP				0x6f860
-#define EDP_PSR_DEBUG(tran)			_MMIO(_TRANS2(tran, _SRD_DEBUG_A))
+#define EDP_PSR_DEBUG(tran)			_MMIO_TRANS2(tran, _SRD_DEBUG_A)
 #define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1 << 28)
 #define   EDP_PSR_DEBUG_MASK_LPSP              (1 << 27)
 #define   EDP_PSR_DEBUG_MASK_MEMUP             (1 << 26)
@@ -2305,7 +2304,7 @@
 
 #define _PSR2_SU_STATUS_A		0x60914
 #define _PSR2_SU_STATUS_EDP		0x6f914
-#define _PSR2_SU_STATUS(tran, index)	_MMIO(_TRANS2(tran, _PSR2_SU_STATUS_A) + (index) * 4)
+#define _PSR2_SU_STATUS(tran, index)	_MMIO_TRANS2(tran, _PSR2_SU_STATUS_A + (index) * 4)
 #define PSR2_SU_STATUS(tran, frame)	(_PSR2_SU_STATUS(tran, (frame) / 3))
 #define PSR2_SU_STATUS_SHIFT(frame)	(((frame) % 3) * 10)
 #define PSR2_SU_STATUS_MASK(frame)	(0x3ff << PSR2_SU_STATUS_SHIFT(frame))
-- 
GitLab


From e97f91e8d39f8f5cff071d847c2d192904e35d0b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Thu, 23 Jun 2022 16:08:58 +0300
Subject: [PATCH 1259/1731] drm/i915: Use _MMIO_PIPE2() where appropriate
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Stop hand rolling _MMIO_TRANS2() and just use the real thing.
Note that this register isn't even used atm, hence why this
builds despite the _PIPE2() macro not actually existing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220623130900.26078-8-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3f0ad77c083a2..d38939a775ce8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4383,7 +4383,7 @@
 #define DSPLINOFF(plane)	DSPADDR(plane)
 #define DSPOFFSET(plane)	_MMIO_PIPE2(plane, _DSPAOFFSET)
 #define DSPSURFLIVE(plane)	_MMIO_PIPE2(plane, _DSPASURFLIVE)
-#define DSPGAMC(plane, i)	_MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
+#define DSPGAMC(plane, i)	_MMIO_PIPE2(plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
 
 /* CHV pipe B blender and primary plane */
 #define _CHV_BLEND_A		0x60a00
-- 
GitLab


From 95be40c875fc848d99f231e77b341e7ab5d8125d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Thu, 23 Jun 2022 16:08:59 +0300
Subject: [PATCH 1260/1731] drm/i915: Get rid of XE_LPD_CURSOR_OFFSETS
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

XE_LPD_CURSOR_OFFSETS is a duplicate of TGL_CURSOR_OFFSETS.
Just use the latter.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220623130900.26078-9-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 10 +---------
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a2d3b61f0246b..1d2ace9217837 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -928,14 +928,6 @@ static const struct intel_device_info adl_s_info = {
 	.dma_mask_size = 39,
 };
 
-#define XE_LPD_CURSOR_OFFSETS \
-	.display.cursor_offsets = { \
-		[PIPE_A] = CURSOR_A_OFFSET, \
-		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
-		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
-		[PIPE_D] = TGL_CURSOR_D_OFFSET, \
-	}
-
 #define XE_LPD_FEATURES \
 	.display.abox_mask = GENMASK(1, 0),					\
 	.color = { .degamma_lut_size = 128, .gamma_lut_size = 1024,		\
@@ -974,7 +966,7 @@ static const struct intel_device_info adl_s_info = {
 		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,			\
 		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,			\
 	},									\
-	XE_LPD_CURSOR_OFFSETS
+	TGL_CURSOR_OFFSETS
 
 static const struct intel_device_info adl_p_info = {
 	GEN12_FEATURES,
-- 
GitLab


From f7fb92cd2e39357f14846d69ae0e1d8692371f82 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Thu, 23 Jun 2022 16:09:00 +0300
Subject: [PATCH 1261/1731] drm/i915: Move the color stuff under
 INTEL_INFO->display
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The LUTs are a display feature so move the details into
the display portion of the device info.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220623130900.26078-10-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 28 ++++++++--------
 drivers/gpu/drm/i915/i915_pci.c            | 38 ++++++++++++----------
 drivers/gpu/drm/i915/intel_device_info.h   | 15 ++++-----
 3 files changed, 42 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 4350595640de8..9583d17e858d9 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -841,7 +841,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
-	int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
 	const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
 
 	/*
@@ -883,7 +883,7 @@ static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_stat
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
-	int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
 
 	/*
 	 * When setting the auto-increment bit, the hardware seems to
@@ -1335,10 +1335,10 @@ static int check_luts(const struct intel_crtc_state *crtc_state)
 		return -EINVAL;
 	}
 
-	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
-	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
-	degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;
-	gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;
+	degamma_length = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
+	gamma_length = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
+	degamma_tests = INTEL_INFO(dev_priv)->display.color.degamma_lut_tests;
+	gamma_tests = INTEL_INFO(dev_priv)->display.color.gamma_lut_tests;
 
 	if (check_lut_size(degamma_lut, degamma_length) ||
 	    check_lut_size(gamma_lut, gamma_length))
@@ -1874,7 +1874,7 @@ static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
 static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
@@ -1917,7 +1917,7 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
 static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
@@ -1978,7 +1978,7 @@ static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
 static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
@@ -2029,7 +2029,7 @@ static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc,
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int i, hw_lut_size = ivb_lut_10_size(prec_index);
-	int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	int lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
@@ -2082,7 +2082,7 @@ static struct drm_property_blob *
 icl_read_lut_multi_segment(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
@@ -2219,7 +2219,7 @@ static const struct intel_color_funcs ilk_color_funcs = {
 void intel_color_init(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	bool has_ctm = INTEL_INFO(dev_priv)->color.degamma_lut_size != 0;
+	bool has_ctm = INTEL_INFO(dev_priv)->display.color.degamma_lut_size != 0;
 
 	drm_mode_crtc_set_gamma_size(&crtc->base, 256);
 
@@ -2250,7 +2250,7 @@ void intel_color_init(struct intel_crtc *crtc)
 	}
 
 	drm_crtc_enable_color_mgmt(&crtc->base,
-				   INTEL_INFO(dev_priv)->color.degamma_lut_size,
+				   INTEL_INFO(dev_priv)->display.color.degamma_lut_size,
 				   has_ctm,
-				   INTEL_INFO(dev_priv)->color.gamma_lut_size);
+				   INTEL_INFO(dev_priv)->display.color.gamma_lut_size);
 }
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1d2ace9217837..04346929d009d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -127,30 +127,33 @@
 	}
 
 #define I9XX_COLORS \
-	.color = { .gamma_lut_size = 256 }
+	.display.color = { .gamma_lut_size = 256 }
 #define I965_COLORS \
-	.color = { .gamma_lut_size = 129, \
+	.display.color = { .gamma_lut_size = 129, \
 		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 	}
 #define ILK_COLORS \
-	.color = { .gamma_lut_size = 1024 }
+	.display.color = { .gamma_lut_size = 1024 }
 #define IVB_COLORS \
-	.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
+	.display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
 #define CHV_COLORS \
-	.color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
-		   .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
-		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
+	.display.color = { \
+		.degamma_lut_size = 65, .gamma_lut_size = 257, \
+		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
+		.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 	}
 #define GLK_COLORS \
-	.color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
-		   .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
-					DRM_COLOR_LUT_EQUAL_CHANNELS, \
+	.display.color = { \
+		.degamma_lut_size = 33, .gamma_lut_size = 1024, \
+		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
+				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
 	}
 #define ICL_COLORS \
-	.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145, \
-		   .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
-					DRM_COLOR_LUT_EQUAL_CHANNELS, \
-		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
+	.display.color = { \
+		.degamma_lut_size = 33, .gamma_lut_size = 262145, \
+		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
+				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
+		.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 	}
 
 /* Keep in gen based order, and chronological order within a gen */
@@ -930,9 +933,10 @@ static const struct intel_device_info adl_s_info = {
 
 #define XE_LPD_FEATURES \
 	.display.abox_mask = GENMASK(1, 0),					\
-	.color = { .degamma_lut_size = 128, .gamma_lut_size = 1024,		\
-		   .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |		\
-					DRM_COLOR_LUT_EQUAL_CHANNELS,		\
+	.display.color = {							\
+		.degamma_lut_size = 128, .gamma_lut_size = 1024,		\
+		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |		\
+				     DRM_COLOR_LUT_EQUAL_CHANNELS,		\
 	},									\
 	.display.dbuf.size = 4096,						\
 	.display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |	\
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 7e50c778c78ed..b259a3dbbe0e6 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -239,15 +239,14 @@ struct intel_device_info {
 		u32 pipe_offsets[I915_MAX_TRANSCODERS];
 		u32 trans_offsets[I915_MAX_TRANSCODERS];
 		u32 cursor_offsets[I915_MAX_PIPES];
-	} display;
-
 
-	struct color_luts {
-		u32 degamma_lut_size;
-		u32 gamma_lut_size;
-		u32 degamma_lut_tests;
-		u32 gamma_lut_tests;
-	} color;
+		struct {
+			u32 degamma_lut_size;
+			u32 gamma_lut_size;
+			u32 degamma_lut_tests;
+			u32 gamma_lut_tests;
+		} color;
+	} display;
 };
 
 struct intel_runtime_info {
-- 
GitLab


From 05907f10e235680cc7fb196810e4ad3215d5e648 Mon Sep 17 00:00:00 2001
From: Pablo Neira Ayuso <pablo@netfilter.org>
Date: Tue, 21 Jun 2022 14:01:41 +0200
Subject: [PATCH 1262/1731] netfilter: nft_dynset: restore set element counter
 when failing to update

This patch fixes a race condition.

nft_rhash_update() might fail for two reasons:

- Element already exists in the hashtable.
- Another packet won race to insert an entry in the hashtable.

In both cases, new() has already bumped the counter via atomic_add_unless(),
therefore, decrement the set element counter.

Fixes: 22fe54d5fefc ("netfilter: nf_tables: add support for dynamic set updates")
Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
---
 net/netfilter/nft_set_hash.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/net/netfilter/nft_set_hash.c b/net/netfilter/nft_set_hash.c
index df40314de21f5..76de6c8d98655 100644
--- a/net/netfilter/nft_set_hash.c
+++ b/net/netfilter/nft_set_hash.c
@@ -143,6 +143,7 @@ static bool nft_rhash_update(struct nft_set *set, const u32 *key,
 	/* Another cpu may race to insert the element with the same key */
 	if (prev) {
 		nft_set_elem_destroy(set, he, true);
+		atomic_dec(&set->nelems);
 		he = prev;
 	}
 
@@ -152,6 +153,7 @@ out:
 
 err2:
 	nft_set_elem_destroy(set, he, true);
+	atomic_dec(&set->nelems);
 err1:
 	return false;
 }
-- 
GitLab


From e34b9ed96ce3b06c79bf884009b16961ca478f87 Mon Sep 17 00:00:00 2001
From: Florian Westphal <fw@strlen.de>
Date: Wed, 22 Jun 2022 16:43:57 +0200
Subject: [PATCH 1263/1731] netfilter: nf_tables: avoid skb access on nf_stolen

When verdict is NF_STOLEN, the skb might have been freed.

When tracing is enabled, this can result in a use-after-free:
1. access to skb->nf_trace
2. access to skb->mark
3. computation of trace id
4. dump of packet payload

To avoid 1, keep a cached copy of skb->nf_trace in the
trace state struct.
Refresh this copy whenever verdict is != STOLEN.

Avoid 2 by skipping skb->mark access if verdict is STOLEN.

3 is avoided by precomputing the trace id.

Only dump the packet when verdict is not "STOLEN".

Reported-by: Pablo Neira Ayuso <pablo@netfilter.org>
Signed-off-by: Florian Westphal <fw@strlen.de>
Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
---
 include/net/netfilter/nf_tables.h | 16 ++++++-----
 net/netfilter/nf_tables_core.c    | 24 ++++++++++++++---
 net/netfilter/nf_tables_trace.c   | 44 +++++++++++++++++--------------
 3 files changed, 55 insertions(+), 29 deletions(-)

diff --git a/include/net/netfilter/nf_tables.h b/include/net/netfilter/nf_tables.h
index 279ae0fff7adb..5c4e5a96a984f 100644
--- a/include/net/netfilter/nf_tables.h
+++ b/include/net/netfilter/nf_tables.h
@@ -1338,24 +1338,28 @@ void nft_unregister_flowtable_type(struct nf_flowtable_type *type);
 /**
  *	struct nft_traceinfo - nft tracing information and state
  *
+ *	@trace: other struct members are initialised
+ *	@nf_trace: copy of skb->nf_trace before rule evaluation
+ *	@type: event type (enum nft_trace_types)
+ *	@skbid: hash of skb to be used as trace id
+ *	@packet_dumped: packet headers sent in a previous traceinfo message
  *	@pkt: pktinfo currently processed
  *	@basechain: base chain currently processed
  *	@chain: chain currently processed
  *	@rule:  rule that was evaluated
  *	@verdict: verdict given by rule
- *	@type: event type (enum nft_trace_types)
- *	@packet_dumped: packet headers sent in a previous traceinfo message
- *	@trace: other struct members are initialised
  */
 struct nft_traceinfo {
+	bool				trace;
+	bool				nf_trace;
+	bool				packet_dumped;
+	enum nft_trace_types		type:8;
+	u32				skbid;
 	const struct nft_pktinfo	*pkt;
 	const struct nft_base_chain	*basechain;
 	const struct nft_chain		*chain;
 	const struct nft_rule_dp	*rule;
 	const struct nft_verdict	*verdict;
-	enum nft_trace_types		type;
-	bool				packet_dumped;
-	bool				trace;
 };
 
 void nft_trace_init(struct nft_traceinfo *info, const struct nft_pktinfo *pkt,
diff --git a/net/netfilter/nf_tables_core.c b/net/netfilter/nf_tables_core.c
index 53f40e4738557..3ddce24ac76dd 100644
--- a/net/netfilter/nf_tables_core.c
+++ b/net/netfilter/nf_tables_core.c
@@ -25,9 +25,7 @@ static noinline void __nft_trace_packet(struct nft_traceinfo *info,
 					const struct nft_chain *chain,
 					enum nft_trace_types type)
 {
-	const struct nft_pktinfo *pkt = info->pkt;
-
-	if (!info->trace || !pkt->skb->nf_trace)
+	if (!info->trace || !info->nf_trace)
 		return;
 
 	info->chain = chain;
@@ -42,11 +40,24 @@ static inline void nft_trace_packet(struct nft_traceinfo *info,
 				    enum nft_trace_types type)
 {
 	if (static_branch_unlikely(&nft_trace_enabled)) {
+		const struct nft_pktinfo *pkt = info->pkt;
+
+		info->nf_trace = pkt->skb->nf_trace;
 		info->rule = rule;
 		__nft_trace_packet(info, chain, type);
 	}
 }
 
+static inline void nft_trace_copy_nftrace(struct nft_traceinfo *info)
+{
+	if (static_branch_unlikely(&nft_trace_enabled)) {
+		const struct nft_pktinfo *pkt = info->pkt;
+
+		if (info->trace)
+			info->nf_trace = pkt->skb->nf_trace;
+	}
+}
+
 static void nft_bitwise_fast_eval(const struct nft_expr *expr,
 				  struct nft_regs *regs)
 {
@@ -85,6 +96,7 @@ static noinline void __nft_trace_verdict(struct nft_traceinfo *info,
 					 const struct nft_chain *chain,
 					 const struct nft_regs *regs)
 {
+	const struct nft_pktinfo *pkt = info->pkt;
 	enum nft_trace_types type;
 
 	switch (regs->verdict.code) {
@@ -92,8 +104,13 @@ static noinline void __nft_trace_verdict(struct nft_traceinfo *info,
 	case NFT_RETURN:
 		type = NFT_TRACETYPE_RETURN;
 		break;
+	case NF_STOLEN:
+		type = NFT_TRACETYPE_RULE;
+		/* can't access skb->nf_trace; use copy */
+		break;
 	default:
 		type = NFT_TRACETYPE_RULE;
+		info->nf_trace = pkt->skb->nf_trace;
 		break;
 	}
 
@@ -254,6 +271,7 @@ next_rule:
 		switch (regs.verdict.code) {
 		case NFT_BREAK:
 			regs.verdict.code = NFT_CONTINUE;
+			nft_trace_copy_nftrace(&info);
 			continue;
 		case NFT_CONTINUE:
 			nft_trace_packet(&info, chain, rule,
diff --git a/net/netfilter/nf_tables_trace.c b/net/netfilter/nf_tables_trace.c
index 5041725423c2d..1163ba9c14011 100644
--- a/net/netfilter/nf_tables_trace.c
+++ b/net/netfilter/nf_tables_trace.c
@@ -7,7 +7,7 @@
 #include <linux/module.h>
 #include <linux/static_key.h>
 #include <linux/hash.h>
-#include <linux/jhash.h>
+#include <linux/siphash.h>
 #include <linux/if_vlan.h>
 #include <linux/init.h>
 #include <linux/skbuff.h>
@@ -25,22 +25,6 @@
 DEFINE_STATIC_KEY_FALSE(nft_trace_enabled);
 EXPORT_SYMBOL_GPL(nft_trace_enabled);
 
-static int trace_fill_id(struct sk_buff *nlskb, struct sk_buff *skb)
-{
-	__be32 id;
-
-	/* using skb address as ID results in a limited number of
-	 * values (and quick reuse).
-	 *
-	 * So we attempt to use as many skb members that will not
-	 * change while skb is with netfilter.
-	 */
-	id = (__be32)jhash_2words(hash32_ptr(skb), skb_get_hash(skb),
-				  skb->skb_iif);
-
-	return nla_put_be32(nlskb, NFTA_TRACE_ID, id);
-}
-
 static int trace_fill_header(struct sk_buff *nlskb, u16 type,
 			     const struct sk_buff *skb,
 			     int off, unsigned int len)
@@ -186,6 +170,7 @@ void nft_trace_notify(struct nft_traceinfo *info)
 	struct nlmsghdr *nlh;
 	struct sk_buff *skb;
 	unsigned int size;
+	u32 mark = 0;
 	u16 event;
 
 	if (!nfnetlink_has_listeners(nft_net(pkt), NFNLGRP_NFTRACE))
@@ -229,7 +214,7 @@ void nft_trace_notify(struct nft_traceinfo *info)
 	if (nla_put_be32(skb, NFTA_TRACE_TYPE, htonl(info->type)))
 		goto nla_put_failure;
 
-	if (trace_fill_id(skb, pkt->skb))
+	if (nla_put_u32(skb, NFTA_TRACE_ID, info->skbid))
 		goto nla_put_failure;
 
 	if (nla_put_string(skb, NFTA_TRACE_CHAIN, info->chain->name))
@@ -249,16 +234,24 @@ void nft_trace_notify(struct nft_traceinfo *info)
 	case NFT_TRACETYPE_RULE:
 		if (nft_verdict_dump(skb, NFTA_TRACE_VERDICT, info->verdict))
 			goto nla_put_failure;
+
+		/* pkt->skb undefined iff NF_STOLEN, disable dump */
+		if (info->verdict->code == NF_STOLEN)
+			info->packet_dumped = true;
+		else
+			mark = pkt->skb->mark;
+
 		break;
 	case NFT_TRACETYPE_POLICY:
+		mark = pkt->skb->mark;
+
 		if (nla_put_be32(skb, NFTA_TRACE_POLICY,
 				 htonl(info->basechain->policy)))
 			goto nla_put_failure;
 		break;
 	}
 
-	if (pkt->skb->mark &&
-	    nla_put_be32(skb, NFTA_TRACE_MARK, htonl(pkt->skb->mark)))
+	if (mark && nla_put_be32(skb, NFTA_TRACE_MARK, htonl(mark)))
 		goto nla_put_failure;
 
 	if (!info->packet_dumped) {
@@ -283,9 +276,20 @@ void nft_trace_init(struct nft_traceinfo *info, const struct nft_pktinfo *pkt,
 		    const struct nft_verdict *verdict,
 		    const struct nft_chain *chain)
 {
+	static siphash_key_t trace_key __read_mostly;
+	struct sk_buff *skb = pkt->skb;
+
 	info->basechain = nft_base_chain(chain);
 	info->trace = true;
+	info->nf_trace = pkt->skb->nf_trace;
 	info->packet_dumped = false;
 	info->pkt = pkt;
 	info->verdict = verdict;
+
+	net_get_random_once(&trace_key, sizeof(trace_key));
+
+	info->skbid = (u32)siphash_3u32(hash32_ptr(skb),
+					skb_get_hash(skb),
+					skb->skb_iif,
+					&trace_key);
 }
-- 
GitLab


From c2577862eeb0be94f151f2f1fff662b028061b00 Mon Sep 17 00:00:00 2001
From: Florian Westphal <fw@strlen.de>
Date: Tue, 21 Jun 2022 18:26:03 +0200
Subject: [PATCH 1264/1731] netfilter: br_netfilter: do not skip all hooks with
 0 priority

When br_netfilter module is loaded, skbs may be diverted to the
ipv4/ipv6 hooks, just like as if we were routing.

Unfortunately, bridge filter hooks with priority 0 may be skipped
in this case.

Example:
1. an nftables bridge ruleset is loaded, with a prerouting
   hook that has priority 0.
2. interface is added to the bridge.
3. no tcp packet is ever seen by the bridge prerouting hook.
4. flush the ruleset
5. load the bridge ruleset again.
6. tcp packets are processed as expected.

After 1) the only registered hook is the bridge prerouting hook, but its
not called yet because the bridge hasn't been brought up yet.

After 2), hook order is:
   0 br_nf_pre_routing // br_netfilter internal hook
   0 chain bridge f prerouting // nftables bridge ruleset

The packet is diverted to br_nf_pre_routing.
If call-iptables is off, the nftables bridge ruleset is called as expected.

But if its enabled, br_nf_hook_thresh() will skip it because it assumes
that all 0-priority hooks had been called previously in bridge context.

To avoid this, check for the br_nf_pre_routing hook itself, we need to
resume directly after it, even if this hook has a priority of 0.

Unfortunately, this still results in different packet flow.
With this fix, the eval order after in 3) is:
1. br_nf_pre_routing
2. ip(6)tables (if enabled)
3. nftables bridge

but after 5 its the much saner:
1. nftables bridge
2. br_nf_pre_routing
3. ip(6)tables (if enabled)

Unfortunately I don't see a solution here:
It would be possible to move br_nf_pre_routing to a higher priority
so that it will be called later in the pipeline, but this also impacts
ebtables evaluation order, and would still result in this very ordering
problem for all nftables-bridge hooks with the same priority as the
br_nf_pre_routing one.

Searching back through the git history I don't think this has
ever behaved in any other way, hence, no fixes-tag.

Reported-by: Radim Hrazdil <rhrazdil@redhat.com>
Signed-off-by: Florian Westphal <fw@strlen.de>
Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
---
 net/bridge/br_netfilter_hooks.c | 21 ++++++++++++++++++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/net/bridge/br_netfilter_hooks.c b/net/bridge/br_netfilter_hooks.c
index 4fd882686b04d..ff47790366497 100644
--- a/net/bridge/br_netfilter_hooks.c
+++ b/net/bridge/br_netfilter_hooks.c
@@ -1012,9 +1012,24 @@ int br_nf_hook_thresh(unsigned int hook, struct net *net,
 		return okfn(net, sk, skb);
 
 	ops = nf_hook_entries_get_hook_ops(e);
-	for (i = 0; i < e->num_hook_entries &&
-	      ops[i]->priority <= NF_BR_PRI_BRNF; i++)
-		;
+	for (i = 0; i < e->num_hook_entries; i++) {
+		/* These hooks have already been called */
+		if (ops[i]->priority < NF_BR_PRI_BRNF)
+			continue;
+
+		/* These hooks have not been called yet, run them. */
+		if (ops[i]->priority > NF_BR_PRI_BRNF)
+			break;
+
+		/* take a closer look at NF_BR_PRI_BRNF. */
+		if (ops[i]->hook == br_nf_pre_routing) {
+			/* This hook diverted the skb to this function,
+			 * hooks after this have not been run yet.
+			 */
+			i++;
+			break;
+		}
+	}
 
 	nf_hook_state_init(&state, hook, NFPROTO_BRIDGE, indev, outdev,
 			   sk, net, okfn);
-- 
GitLab


From 2390095113e98fc52fffe35c5206d30d9efe3f78 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <masahiroy@kernel.org>
Date: Mon, 27 Jun 2022 12:22:09 +0900
Subject: [PATCH 1265/1731] tick/nohz: unexport __init-annotated
 tick_nohz_full_setup()

EXPORT_SYMBOL and __init is a bad combination because the .init.text
section is freed up after the initialization. Hence, modules cannot
use symbols annotated __init. The access to a freed symbol may end up
with kernel panic.

modpost used to detect it, but it had been broken for a decade.

Commit 28438794aba4 ("modpost: fix section mismatch check for exported
init/exit sections") fixed it so modpost started to warn it again, then
this showed up:

    MODPOST vmlinux.symvers
  WARNING: modpost: vmlinux.o(___ksymtab_gpl+tick_nohz_full_setup+0x0): Section mismatch in reference from the variable __ksymtab_tick_nohz_full_setup to the function .init.text:tick_nohz_full_setup()
  The symbol tick_nohz_full_setup is exported and annotated __init
  Fix this by removing the __init annotation of tick_nohz_full_setup or drop the export.

Drop the export because tick_nohz_full_setup() is only called from the
built-in code in kernel/sched/isolation.c.

Fixes: ae9e557b5be2 ("time: Export tick start/stop functions for rcutorture")
Reported-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Tested-by: Paul E. McKenney <paulmck@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
---
 kernel/time/tick-sched.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c
index 58a11f859ac79..30049580cd628 100644
--- a/kernel/time/tick-sched.c
+++ b/kernel/time/tick-sched.c
@@ -526,7 +526,6 @@ void __init tick_nohz_full_setup(cpumask_var_t cpumask)
 	cpumask_copy(tick_nohz_full_mask, cpumask);
 	tick_nohz_full_running = true;
 }
-EXPORT_SYMBOL_GPL(tick_nohz_full_setup);
 
 static int tick_nohz_cpu_down(unsigned int cpu)
 {
-- 
GitLab


From 7307e91bfcd0e3f123aab01b30557f93923b6d73 Mon Sep 17 00:00:00 2001
From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Date: Wed, 15 Jun 2022 00:13:46 +0530
Subject: [PATCH 1266/1731] drm/i915: Do not access rq->engine without a
 reference

In i915_fence_get_driver_name(), user may not hold a
reference to rq->engine. Hence do not access it. Instead,
store required device private pointer in 'rq->i915' and use it.

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Suggested-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220614184348.23746-2-ramalingam.c@intel.com
---
 drivers/gpu/drm/i915/i915_request.c | 3 ++-
 drivers/gpu/drm/i915/i915_request.h | 2 ++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index c3937640b1199..667dda7668cb1 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -60,7 +60,7 @@ static struct kmem_cache *slab_execute_cbs;
 
 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
 {
-	return dev_name(to_request(fence)->engine->i915->drm.dev);
+	return dev_name(to_request(fence)->i915->drm.dev);
 }
 
 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
@@ -937,6 +937,7 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp)
 	rq->engine = ce->engine;
 	rq->ring = ce->ring;
 	rq->execution_mask = ce->engine->mask;
+	rq->i915 = ce->engine->i915;
 
 	ret = intel_timeline_get_seqno(tl, rq, &seqno);
 	if (ret)
diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h
index 28b1f9db54875..47041ec68df89 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -196,6 +196,8 @@ struct i915_request {
 	struct dma_fence fence;
 	spinlock_t lock;
 
+	struct drm_i915_private *i915;
+
 	/**
 	 * Context and ring buffer related to this request
 	 * Contexts are refcounted, so when this request is associated with a
-- 
GitLab


From bcb9aa45d5a0e11ef91245330c53cde214d15e8d Mon Sep 17 00:00:00 2001
From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Date: Wed, 15 Jun 2022 00:13:47 +0530
Subject: [PATCH 1267/1731] Revert "drm/i915: Hold reference to intel_context
 over life of i915_request"

This reverts commit 1e98d8c52ed5dfbaf273c4423c636525c2ce59e7.

The problem with this patch is that it makes i915_request to hold a
reference to intel_context, which in turn holds a reference on the VM.
This strong back referencing can lead to reference loops which leads
to resource leak.

An example is the upcoming VM_BIND work which requires VM to hold
a reference to some shared VM specific BO. But this BO's dma-resv
fences holds reference to the i915_request thus leading to reference
loop.

v2:
  Do not use reserved requests for virtual engines

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Suggested-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Mathew Brost <matthew.brost@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220614184348.23746-3-ramalingam.c@intel.com
---
 drivers/gpu/drm/i915/i915_request.c | 52 ++++++++++++++++++-----------
 1 file changed, 32 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index 667dda7668cb1..62fad16a55e84 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -134,17 +134,42 @@ static void i915_fence_release(struct dma_fence *fence)
 	i915_sw_fence_fini(&rq->semaphore);
 
 	/*
-	 * Keep one request on each engine for reserved use under mempressure,
+	 * Keep one request on each engine for reserved use under mempressure
 	 * do not use with virtual engines as this really is only needed for
 	 * kernel contexts.
+	 *
+	 * We do not hold a reference to the engine here and so have to be
+	 * very careful in what rq->engine we poke. The virtual engine is
+	 * referenced via the rq->context and we released that ref during
+	 * i915_request_retire(), ergo we must not dereference a virtual
+	 * engine here. Not that we would want to, as the only consumer of
+	 * the reserved engine->request_pool is the power management parking,
+	 * which must-not-fail, and that is only run on the physical engines.
+	 *
+	 * Since the request must have been executed to be have completed,
+	 * we know that it will have been processed by the HW and will
+	 * not be unsubmitted again, so rq->engine and rq->execution_mask
+	 * at this point is stable. rq->execution_mask will be a single
+	 * bit if the last and _only_ engine it could execution on was a
+	 * physical engine, if it's multiple bits then it started on and
+	 * could still be on a virtual engine. Thus if the mask is not a
+	 * power-of-two we assume that rq->engine may still be a virtual
+	 * engine and so a dangling invalid pointer that we cannot dereference
+	 *
+	 * For example, consider the flow of a bonded request through a virtual
+	 * engine. The request is created with a wide engine mask (all engines
+	 * that we might execute on). On processing the bond, the request mask
+	 * is reduced to one or more engines. If the request is subsequently
+	 * bound to a single engine, it will then be constrained to only
+	 * execute on that engine and never returned to the virtual engine
+	 * after timeslicing away, see __unwind_incomplete_requests(). Thus we
+	 * know that if the rq->execution_mask is a single bit, rq->engine
+	 * can be a physical engine with the exact corresponding mask.
 	 */
 	if (!intel_engine_is_virtual(rq->engine) &&
-	    !cmpxchg(&rq->engine->request_pool, NULL, rq)) {
-		intel_context_put(rq->context);
+	    is_power_of_2(rq->execution_mask) &&
+	    !cmpxchg(&rq->engine->request_pool, NULL, rq))
 		return;
-	}
-
-	intel_context_put(rq->context);
 
 	kmem_cache_free(slab_requests, rq);
 }
@@ -921,19 +946,7 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp)
 		}
 	}
 
-	/*
-	 * Hold a reference to the intel_context over life of an i915_request.
-	 * Without this an i915_request can exist after the context has been
-	 * destroyed (e.g. request retired, context closed, but user space holds
-	 * a reference to the request from an out fence). In the case of GuC
-	 * submission + virtual engine, the engine that the request references
-	 * is also destroyed which can trigger bad pointer dref in fence ops
-	 * (e.g. i915_fence_get_driver_name). We could likely change these
-	 * functions to avoid touching the engine but let's just be safe and
-	 * hold the intel_context reference. In execlist mode the request always
-	 * eventually points to a physical engine so this isn't an issue.
-	 */
-	rq->context = intel_context_get(ce);
+	rq->context = ce;
 	rq->engine = ce->engine;
 	rq->ring = ce->ring;
 	rq->execution_mask = ce->engine->mask;
@@ -1009,7 +1022,6 @@ err_unwind:
 	GEM_BUG_ON(!list_empty(&rq->sched.waiters_list));
 
 err_free:
-	intel_context_put(ce);
 	kmem_cache_free(slab_requests, rq);
 err_unreserve:
 	intel_context_unpin(ce);
-- 
GitLab


From 59bcdb564b3bac3e86cc274e5dec05d4647ce47f Mon Sep 17 00:00:00 2001
From: Alan Previn <alan.previn.teres.alexis@intel.com>
Date: Wed, 22 Jun 2022 19:31:57 -0700
Subject: [PATCH 1268/1731] drm/i915/guc: Don't update engine busyness stats
 too frequently

Using two different types of workoads, it was observed that
guc_update_engine_gt_clks was being called too frequently and/or
causing a CPU-to-lmem bandwidth hit over PCIE. Details on
the workloads and numbers are in the notes below.

Background: At the moment, guc_update_engine_gt_clks can be invoked
via one of 3 ways. #1 and #2 are infrequent under normal operating
conditions:
     1.When a predefined "ping_delay" timer expires so that GuC-
       busyness can sample the GTPM clock counter to ensure it
       doesn't miss a wrap-around of the 32-bits of the HW counter.
       (The ping_delay is calculated based on 1/8th the time taken
       for the counter go from 0x0 to 0xffffffff based on the
       GT frequency. This comes to about once every 28 seconds at a
       GT frequency of 19.2Mhz).
     2.In preparation for a gt reset.
     3.In response to __gt_park events (as the gt power management
       puts the gt into a lower power state when there is no work
       being done).

Root-cause: For both the workloads described farther below, it was
observed that when user space calls IOCTLs that unparks the
gt momentarily and repeats such calls many times in quick succession,
it triggers calling guc_update_engine_gt_clks as many times. However,
the primary purpose of guc_update_engine_gt_clks is to ensure we don't
miss the wraparound while the counter is ticking. Thus, the solution
is to ensure we skip that check if gt_park is calling this function
earlier than necessary.

Solution: Snapshot jiffies when we do actually update the busyness
stats. Then get the new jiffies every time intel_guc_busyness_park
is called and bail if we are being called too soon. Use half of the
ping_delay as a safe threshold.

NOTE1: Workload1: IGTs' gem_create was modified to create a file handle,
allocate memory with sizes that range from a min of 4K to the max supported
(in power of two step-sizes). Its maps, modifies and reads back the
memory. Allocations and modification is repeated until total memory
allocation reaches the max. Then the file handle is closed. With this
workload, guc_update_engine_gt_clks was called over 188 thousand times
in the span of 15 seconds while this test ran three times. With this patch,
the number of calls reduced to 14.

NOTE2: Workload2: 30 transcode sessions are created in quick succession.
While these sessions are created, pcm-iio tool was used to measure I/O
read operation bandwidth consumption sampled at 100 milisecond intervals
over the course of 20 seconds. The total bandwidth consumed over 20 seconds
without this patch was measured at average at 311KBps per sample. With this
patch, the number went down to about 175Kbps which is about a 43% savings.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220623023157.211650-2-alan.previn.teres.alexis@intel.com
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.h            |  8 ++++++++
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 13 +++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 966e69a8b1c12..d0d99f178f2d4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -230,6 +230,14 @@ struct intel_guc {
 		 * @shift: Right shift value for the gpm timestamp
 		 */
 		u32 shift;
+
+		/**
+		 * @last_stat_jiffies: jiffies at last actual stats collection time
+		 * We use this timestamp to ensure we don't oversample the
+		 * stats because runtime power management events can trigger
+		 * stats collection at much higher rates than required.
+		 */
+		unsigned long last_stat_jiffies;
 	} timestamp;
 
 #ifdef CONFIG_DRM_I915_SELFTEST
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index e62ea35513ea9..c9f167b809107 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1314,6 +1314,8 @@ static void __update_guc_busyness_stats(struct intel_guc *guc)
 	unsigned long flags;
 	ktime_t unused;
 
+	guc->timestamp.last_stat_jiffies = jiffies;
+
 	spin_lock_irqsave(&guc->timestamp.lock, flags);
 
 	guc_update_pm_timestamp(guc, &unused);
@@ -1386,6 +1388,17 @@ void intel_guc_busyness_park(struct intel_gt *gt)
 		return;
 
 	cancel_delayed_work(&guc->timestamp.work);
+
+	/*
+	 * Before parking, we should sample engine busyness stats if we need to.
+	 * We can skip it if we are less than half a ping from the last time we
+	 * sampled the busyness stats.
+	 */
+	if (guc->timestamp.last_stat_jiffies &&
+	    !time_after(jiffies, guc->timestamp.last_stat_jiffies +
+			(guc->timestamp.ping_delay / 2)))
+		return;
+
 	__update_guc_busyness_stats(guc);
 }
 
-- 
GitLab


From 0667429ce68e0b08f9f1fec8fd0b1f57228f605e Mon Sep 17 00:00:00 2001
From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Date: Tue, 21 Jun 2022 12:21:05 -0700
Subject: [PATCH 1269/1731] drm/i915/reset: Add additional steps for
 Wa_22011802037 for execlist backend

For execlists backend, current implementation of Wa_22011802037 is to
stop the CS before doing a reset of the engine. This WA was further
extended to wait for any pending MI FORCE WAKEUPs before issuing a
reset. Add the extended steps in the execlist path of reset.

In addition, extend the WA to gen11.

v2: (Tvrtko)
- Clarify comments, commit message, fix typos
- Use IS_GRAPHICS_VER for gen 11/12 checks

v3: (Daneile)
- Drop changes to intel_ring_submission since WA does not apply to it
- Log an error if MSG IDLE is not defined for an engine

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Fixes: f6aa0d713c88 ("drm/i915: Add Wa_22011802037 force cs halt")
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220621192105.2100585-1-umesh.nerlige.ramappa@intel.com
---
 drivers/gpu/drm/i915/gt/intel_engine.h        |  2 +
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     | 88 ++++++++++++++++++-
 .../drm/i915/gt/intel_execlists_submission.c  |  7 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  4 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 81 ++---------------
 5 files changed, 103 insertions(+), 79 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 1431f1e9dbee7..04e435bce79bd 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -201,6 +201,8 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine);
 int intel_engine_stop_cs(struct intel_engine_cs *engine);
 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
 
+void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine);
+
 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask);
 
 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 136cc44c3deb8..283870c659911 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1376,10 +1376,10 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
 	intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
 
 	/*
-	 * Wa_22011802037 : gen12, Prior to doing a reset, ensure CS is
+	 * Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is
 	 * stopped, set ring stop bit and prefetch disable bit to halt CS
 	 */
-	if (GRAPHICS_VER(engine->i915) == 12)
+	if (IS_GRAPHICS_VER(engine->i915, 11, 12))
 		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
 				      _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
 
@@ -1402,6 +1402,18 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine)
 		return -ENODEV;
 
 	ENGINE_TRACE(engine, "\n");
+	/*
+	 * TODO: Find out why occasionally stopping the CS times out. Seen
+	 * especially with gem_eio tests.
+	 *
+	 * Occasionally trying to stop the cs times out, but does not adversely
+	 * affect functionality. The timeout is set as a config parameter that
+	 * defaults to 100ms. In most cases the follow up operation is to wait
+	 * for pending MI_FORCE_WAKES. The assumption is that this timeout is
+	 * sufficient for any pending MI_FORCEWAKEs to complete. Once root
+	 * caused, the caller must check and handle the return from this
+	 * function.
+	 */
 	if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
 		ENGINE_TRACE(engine,
 			     "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n",
@@ -1428,6 +1440,78 @@ void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
 	ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
 }
 
+static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
+{
+	static const i915_reg_t _reg[I915_NUM_ENGINES] = {
+		[RCS0] = MSG_IDLE_CS,
+		[BCS0] = MSG_IDLE_BCS,
+		[VCS0] = MSG_IDLE_VCS0,
+		[VCS1] = MSG_IDLE_VCS1,
+		[VCS2] = MSG_IDLE_VCS2,
+		[VCS3] = MSG_IDLE_VCS3,
+		[VCS4] = MSG_IDLE_VCS4,
+		[VCS5] = MSG_IDLE_VCS5,
+		[VCS6] = MSG_IDLE_VCS6,
+		[VCS7] = MSG_IDLE_VCS7,
+		[VECS0] = MSG_IDLE_VECS0,
+		[VECS1] = MSG_IDLE_VECS1,
+		[VECS2] = MSG_IDLE_VECS2,
+		[VECS3] = MSG_IDLE_VECS3,
+		[CCS0] = MSG_IDLE_CS,
+		[CCS1] = MSG_IDLE_CS,
+		[CCS2] = MSG_IDLE_CS,
+		[CCS3] = MSG_IDLE_CS,
+	};
+	u32 val;
+
+	if (!_reg[engine->id].reg) {
+		drm_err(&engine->i915->drm,
+			"MSG IDLE undefined for engine id %u\n", engine->id);
+		return 0;
+	}
+
+	val = intel_uncore_read(engine->uncore, _reg[engine->id]);
+
+	/* bits[29:25] & bits[13:9] >> shift */
+	return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
+}
+
+static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
+{
+	int ret;
+
+	/* Ensure GPM receives fw up/down after CS is stopped */
+	udelay(1);
+
+	/* Wait for forcewake request to complete in GPM */
+	ret =  __intel_wait_for_register_fw(gt->uncore,
+					    GEN9_PWRGT_DOMAIN_STATUS,
+					    fw_mask, fw_mask, 5000, 0, NULL);
+
+	/* Ensure CS receives fw ack from GPM */
+	udelay(1);
+
+	if (ret)
+		GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);
+}
+
+/*
+ * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
+ * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
+ * pending status is indicated by bits[13:9] (masked by bits[29:25]) in the
+ * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
+ * are concerned only with the gt reset here, we use a logical OR of pending
+ * forcewakeups from all reset domains and then wait for them to complete by
+ * querying PWRGT_DOMAIN_STATUS.
+ */
+void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine)
+{
+	u32 fw_pending = __cs_pending_mi_force_wakes(engine);
+
+	if (fw_pending)
+		__gpm_wait_for_fw_complete(engine->gt, fw_pending);
+}
+
 /* NB: please notice the memset */
 void intel_engine_get_instdone(const struct intel_engine_cs *engine,
 			       struct intel_instdone *instdone)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 98f1c7258cc08..aab240ea1d25b 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2968,6 +2968,13 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
 	ring_set_paused(engine, 1);
 	intel_engine_stop_cs(engine);
 
+	/*
+	 * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
+	 * to wait for any pending mi force wakeups
+	 */
+	if (IS_GRAPHICS_VER(engine->i915, 11, 12))
+		intel_engine_wait_for_pending_mi_fw(engine);
+
 	engine->execlists.reset_ccid = active_ccid(engine);
 }
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 35887cb532019..2706a8c650900 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -310,8 +310,8 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
 	if (IS_DG2(gt->i915))
 		flags |= GUC_WA_DUAL_QUEUE;
 
-	/* Wa_22011802037: graphics version 12 */
-	if (GRAPHICS_VER(gt->i915) == 12)
+	/* Wa_22011802037: graphics version 11/12 */
+	if (IS_GRAPHICS_VER(gt->i915, 11, 12))
 		flags |= GUC_WA_PRE_PARSER;
 
 	/* Wa_16011777198:dg2 */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index c9f167b809107..40f726c61e951 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1540,87 +1540,18 @@ static void guc_reset_state(struct intel_context *ce, u32 head, bool scrub)
 	lrc_update_regs(ce, engine, head);
 }
 
-static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
-{
-	static const i915_reg_t _reg[I915_NUM_ENGINES] = {
-		[RCS0] = MSG_IDLE_CS,
-		[BCS0] = MSG_IDLE_BCS,
-		[VCS0] = MSG_IDLE_VCS0,
-		[VCS1] = MSG_IDLE_VCS1,
-		[VCS2] = MSG_IDLE_VCS2,
-		[VCS3] = MSG_IDLE_VCS3,
-		[VCS4] = MSG_IDLE_VCS4,
-		[VCS5] = MSG_IDLE_VCS5,
-		[VCS6] = MSG_IDLE_VCS6,
-		[VCS7] = MSG_IDLE_VCS7,
-		[VECS0] = MSG_IDLE_VECS0,
-		[VECS1] = MSG_IDLE_VECS1,
-		[VECS2] = MSG_IDLE_VECS2,
-		[VECS3] = MSG_IDLE_VECS3,
-		[CCS0] = MSG_IDLE_CS,
-		[CCS1] = MSG_IDLE_CS,
-		[CCS2] = MSG_IDLE_CS,
-		[CCS3] = MSG_IDLE_CS,
-	};
-	u32 val;
-
-	if (!_reg[engine->id].reg)
-		return 0;
-
-	val = intel_uncore_read(engine->uncore, _reg[engine->id]);
-
-	/* bits[29:25] & bits[13:9] >> shift */
-	return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
-}
-
-static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
-{
-	int ret;
-
-	/* Ensure GPM receives fw up/down after CS is stopped */
-	udelay(1);
-
-	/* Wait for forcewake request to complete in GPM */
-	ret =  __intel_wait_for_register_fw(gt->uncore,
-					    GEN9_PWRGT_DOMAIN_STATUS,
-					    fw_mask, fw_mask, 5000, 0, NULL);
-
-	/* Ensure CS receives fw ack from GPM */
-	udelay(1);
-
-	if (ret)
-		GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);
-}
-
-/*
- * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
- * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
- * pending status is indicated by bits[13:9] (masked by bits[ 29:25]) in the
- * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
- * are concerned only with the gt reset here, we use a logical OR of pending
- * forcewakeups from all reset domains and then wait for them to complete by
- * querying PWRGT_DOMAIN_STATUS.
- */
 static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
 {
-	u32 fw_pending;
-
-	if (GRAPHICS_VER(engine->i915) != 12)
+	if (!IS_GRAPHICS_VER(engine->i915, 11, 12))
 		return;
 
-	/*
-	 * Wa_22011802037
-	 * TODO: Occasionally trying to stop the cs times out, but does not
-	 * adversely affect functionality. The timeout is set as a config
-	 * parameter that defaults to 100ms. Assuming that this timeout is
-	 * sufficient for any pending MI_FORCEWAKEs to complete, ignore the
-	 * timeout returned here until it is root caused.
-	 */
 	intel_engine_stop_cs(engine);
 
-	fw_pending = __cs_pending_mi_force_wakes(engine);
-	if (fw_pending)
-		__gpm_wait_for_fw_complete(engine->gt, fw_pending);
+	/*
+	 * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
+	 * to wait for any pending mi force wakeups
+	 */
+	intel_engine_wait_for_pending_mi_fw(engine);
 }
 
 static void guc_reset_nop(struct intel_engine_cs *engine)
-- 
GitLab


From 96b80fcd2705fc50ebe1f7f3ce204e861b3099ab Mon Sep 17 00:00:00 2001
From: Helge Deller <deller@gmx.de>
Date: Mon, 27 Jun 2022 01:39:11 +0200
Subject: [PATCH 1270/1731] parisc/unaligned: Fix emulate_ldw() breakage

The commit e8aa7b17fe41 broke the 32-bit load-word unalignment exception
handler because it calculated the wrong amount of bits by which the value
should be shifted. This patch fixes it.

Signed-off-by: Helge Deller <deller@gmx.de>
Fixes: e8aa7b17fe41 ("parisc/unaligned: Rewrite inline assembly of emulate_ldw()")
Cc: stable@vger.kernel.org   # v5.18
---
 arch/parisc/kernel/unaligned.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/parisc/kernel/unaligned.c b/arch/parisc/kernel/unaligned.c
index ed1e88a74dc42..bac581b5ecfc5 100644
--- a/arch/parisc/kernel/unaligned.c
+++ b/arch/parisc/kernel/unaligned.c
@@ -146,7 +146,7 @@ static int emulate_ldw(struct pt_regs *regs, int toreg, int flop)
 "	depw	%%r0,31,2,%4\n"
 "1:	ldw	0(%%sr1,%4),%0\n"
 "2:	ldw	4(%%sr1,%4),%3\n"
-"	subi	32,%4,%2\n"
+"	subi	32,%2,%2\n"
 "	mtctl	%2,11\n"
 "	vshd	%0,%3,%0\n"
 "3:	\n"
-- 
GitLab


From 08de214138cdea438a0dfcb10d355a6650c6017c Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Fri, 24 Jun 2022 11:45:28 -0700
Subject: [PATCH 1271/1731] drm/msm/gem: Fix error return on fence id alloc
 fail

This was a typo, we didn't actually want to return zero.

Fixes: a61acbbe9cf8 ("drm/msm: Track "seqno" fences by idr")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/491145/
Link: https://lore.kernel.org/r/20220624184528.4036837-1-robdclark@gmail.com
---
 drivers/gpu/drm/msm/msm_gem_submit.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c
index 286124008445d..6b6feae1f7b62 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -928,7 +928,7 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
 						    INT_MAX, GFP_KERNEL);
 	}
 	if (submit->fence_id < 0) {
-		ret = submit->fence_id = 0;
+		ret = submit->fence_id;
 		submit->fence_id = 0;
 	}
 
-- 
GitLab


From 5fb779558f1c97e2bf2794cb59553e569c38e2f9 Mon Sep 17 00:00:00 2001
From: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Date: Mon, 27 Jun 2022 15:59:38 +0200
Subject: [PATCH 1272/1731] arm64: dts: qcom: msm8992-*: Fix vdd_lvs1_2-supply
 typo

"make dtbs_check" complains about the missing "-supply" suffix for
vdd_lvs1_2 which is clearly a typo, originally introduced in the
msm8994-smd-rpm.dtsi file and apparently later copied to
msm8992-xiaomi-libra.dts:

msm8992-lg-bullhead-rev-10/101.dtb: pm8994-regulators: 'vdd_lvs1_2'
does not match any of the regexes:
  '.*-supply$', '^((s|l|lvs|5vs)[0-9]*)|(boost-bypass)|(bob)$', 'pinctrl-[0-9]+'
From schema: regulator/qcom,smd-rpm-regulator.yaml

msm8992-xiaomi-libra.dtb: pm8994-regulators: 'vdd_lvs1_2'
does not match any of the regexes:
  '.*-supply$', '^((s|l|lvs|5vs)[0-9]*)|(boost-bypass)|(bob)$', 'pinctrl-[0-9]+'
From schema: regulator/qcom,smd-rpm-regulator.yaml

Reported-by: Rob Herring <robh@kernel.org>
Cc: Konrad Dybcio <konrad.dybcio@somainline.org>
Fixes: f3b2c99e73be ("arm64: dts: Enable onboard SDHCI on msm8992")
Fixes: 0f5cdb31e850 ("arm64: dts: qcom: Add Xiaomi Libra (Mi 4C) device tree")
Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220627135938.2901871-1-stephan.gerhold@kernkonzept.com
---
 arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi
index 3b0cc85d66742..71e373b11de9d 100644
--- a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi
@@ -74,7 +74,7 @@
 		vdd_l17_29-supply = <&vph_pwr>;
 		vdd_l20_21-supply = <&vph_pwr>;
 		vdd_l25-supply = <&pm8994_s5>;
-		vdd_lvs1_2 = <&pm8994_s4>;
+		vdd_lvs1_2-supply = <&pm8994_s4>;
 
 		/* S1, S2, S6 and S12 are managed by RPMPD */
 
diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
index 7748b745a5df5..afa91ca9a3dcd 100644
--- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
+++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
@@ -171,7 +171,7 @@
 		vdd_l17_29-supply = <&vph_pwr>;
 		vdd_l20_21-supply = <&vph_pwr>;
 		vdd_l25-supply = <&pm8994_s5>;
-		vdd_lvs1_2 = <&pm8994_s4>;
+		vdd_lvs1_2-supply = <&pm8994_s4>;
 
 		/* S1, S2, S6 and S12 are managed by RPMPD */
 
-- 
GitLab


From 58eaa6b3fb636072a4f19e6b6c76bbf564e95b95 Mon Sep 17 00:00:00 2001
From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Date: Wed, 22 Jun 2022 17:32:25 -0700
Subject: [PATCH 1273/1731] drm/i915/guc/slpc: Use non-blocking H2G for
 waitboost

SLPC min/max frequency updates require H2G calls. We are seeing
timeouts when GuC channel is backed up and it is unable to respond
in a timely fashion causing warnings and affecting CI.

This is seen when waitboosting happens during a stress test.
this patch updates the waitboost path to use a non-blocking
H2G call instead, which returns as soon as the message is
successfully transmitted.

v2: Use drm_notice to report any errors that might occur while
sending the waitboost H2G request (Tvrtko)
v3: Add drm_notice inside force_min_freq (Ashutosh)

Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220623003225.23301-1-vinay.belgaumkar@intel.com
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 42 +++++++++++++++++----
 1 file changed, 35 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 2df31af70d638..ec9c4ca0f615b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -98,6 +98,30 @@ static u32 slpc_get_state(struct intel_guc_slpc *slpc)
 	return data->header.global_state;
 }
 
+static int guc_action_slpc_set_param_nb(struct intel_guc *guc, u8 id, u32 value)
+{
+	u32 request[] = {
+		GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
+		SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2),
+		id,
+		value,
+	};
+	int ret;
+
+	ret = intel_guc_send_nb(guc, request, ARRAY_SIZE(request), 0);
+
+	return ret > 0 ? -EPROTO : ret;
+}
+
+static int slpc_set_param_nb(struct intel_guc_slpc *slpc, u8 id, u32 value)
+{
+	struct intel_guc *guc = slpc_to_guc(slpc);
+
+	GEM_BUG_ON(id >= SLPC_MAX_PARAM);
+
+	return guc_action_slpc_set_param_nb(guc, id, value);
+}
+
 static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
 {
 	u32 request[] = {
@@ -208,12 +232,14 @@ static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq)
 	 */
 
 	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
-		ret = slpc_set_param(slpc,
-				     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
-				     freq);
+		/* Non-blocking request will avoid stalls */
+		ret = slpc_set_param_nb(slpc,
+					SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+					freq);
 		if (ret)
-			i915_probe_error(i915, "Unable to force min freq to %u: %d",
-					 freq, ret);
+			drm_notice(&i915->drm,
+				   "Failed to send set_param for min freq(%d): (%d)\n",
+				   freq, ret);
 	}
 
 	return ret;
@@ -222,6 +248,7 @@ static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq)
 static void slpc_boost_work(struct work_struct *work)
 {
 	struct intel_guc_slpc *slpc = container_of(work, typeof(*slpc), boost_work);
+	int err;
 
 	/*
 	 * Raise min freq to boost. It's possible that
@@ -231,8 +258,9 @@ static void slpc_boost_work(struct work_struct *work)
 	 */
 	mutex_lock(&slpc->lock);
 	if (atomic_read(&slpc->num_waiters)) {
-		slpc_force_min_freq(slpc, slpc->boost_freq);
-		slpc->num_boosts++;
+		err = slpc_force_min_freq(slpc, slpc->boost_freq);
+		if (!err)
+			slpc->num_boosts++;
 	}
 	mutex_unlock(&slpc->lock);
 }
-- 
GitLab


From 332bd0778775d0cf105c4b9e03e460b590749916 Mon Sep 17 00:00:00 2001
From: Heinz Mauelshagen <heinzm@redhat.com>
Date: Tue, 28 Jun 2022 00:37:22 +0200
Subject: [PATCH 1274/1731] dm raid: fix accesses beyond end of raid member
 array

On dm-raid table load (using raid_ctr), dm-raid allocates an array
rs->devs[rs->raid_disks] for the raid device members. rs->raid_disks
is defined by the number of raid metadata and image tupples passed
into the target's constructor.

In the case of RAID layout changes being requested, that number can be
different from the current number of members for existing raid sets as
defined in their superblocks. Example RAID layout changes include:
- raid1 legs being added/removed
- raid4/5/6/10 number of stripes changed (stripe reshaping)
- takeover to higher raid level (e.g. raid5 -> raid6)

When accessing array members, rs->raid_disks must be used in control
loops instead of the potentially larger value in rs->md.raid_disks.
Otherwise it will cause memory access beyond the end of the rs->devs
array.

Fix this by changing code that is prone to out-of-bounds access.
Also fix validate_raid_redundancy() to validate all devices that are
added. Also, use braces to help clean up raid_iterate_devices().

The out-of-bounds memory accesses was discovered using KASAN.

This commit was verified to pass all LVM2 RAID tests (with KASAN
enabled).

Cc: stable@vger.kernel.org
Signed-off-by: Heinz Mauelshagen <heinzm@redhat.com>
Signed-off-by: Mike Snitzer <snitzer@kernel.org>
---
 drivers/md/dm-raid.c | 34 ++++++++++++++++++----------------
 1 file changed, 18 insertions(+), 16 deletions(-)

diff --git a/drivers/md/dm-raid.c b/drivers/md/dm-raid.c
index 9526ccbedafba..80c9f7134e9b9 100644
--- a/drivers/md/dm-raid.c
+++ b/drivers/md/dm-raid.c
@@ -1001,12 +1001,13 @@ static int validate_region_size(struct raid_set *rs, unsigned long region_size)
 static int validate_raid_redundancy(struct raid_set *rs)
 {
 	unsigned int i, rebuild_cnt = 0;
-	unsigned int rebuilds_per_group = 0, copies;
+	unsigned int rebuilds_per_group = 0, copies, raid_disks;
 	unsigned int group_size, last_group_start;
 
-	for (i = 0; i < rs->md.raid_disks; i++)
-		if (!test_bit(In_sync, &rs->dev[i].rdev.flags) ||
-		    !rs->dev[i].rdev.sb_page)
+	for (i = 0; i < rs->raid_disks; i++)
+		if (!test_bit(FirstUse, &rs->dev[i].rdev.flags) &&
+		    ((!test_bit(In_sync, &rs->dev[i].rdev.flags) ||
+		      !rs->dev[i].rdev.sb_page)))
 			rebuild_cnt++;
 
 	switch (rs->md.level) {
@@ -1046,8 +1047,9 @@ static int validate_raid_redundancy(struct raid_set *rs)
 		 *	    A	 A    B	   B	C
 		 *	    C	 D    D	   E	E
 		 */
+		raid_disks = min(rs->raid_disks, rs->md.raid_disks);
 		if (__is_raid10_near(rs->md.new_layout)) {
-			for (i = 0; i < rs->md.raid_disks; i++) {
+			for (i = 0; i < raid_disks; i++) {
 				if (!(i % copies))
 					rebuilds_per_group = 0;
 				if ((!rs->dev[i].rdev.sb_page ||
@@ -1070,10 +1072,10 @@ static int validate_raid_redundancy(struct raid_set *rs)
 		 * results in the need to treat the last (potentially larger)
 		 * set differently.
 		 */
-		group_size = (rs->md.raid_disks / copies);
-		last_group_start = (rs->md.raid_disks / group_size) - 1;
+		group_size = (raid_disks / copies);
+		last_group_start = (raid_disks / group_size) - 1;
 		last_group_start *= group_size;
-		for (i = 0; i < rs->md.raid_disks; i++) {
+		for (i = 0; i < raid_disks; i++) {
 			if (!(i % copies) && !(i > last_group_start))
 				rebuilds_per_group = 0;
 			if ((!rs->dev[i].rdev.sb_page ||
@@ -1588,7 +1590,7 @@ static sector_t __rdev_sectors(struct raid_set *rs)
 {
 	int i;
 
-	for (i = 0; i < rs->md.raid_disks; i++) {
+	for (i = 0; i < rs->raid_disks; i++) {
 		struct md_rdev *rdev = &rs->dev[i].rdev;
 
 		if (!test_bit(Journal, &rdev->flags) &&
@@ -3766,13 +3768,13 @@ static int raid_iterate_devices(struct dm_target *ti,
 	unsigned int i;
 	int r = 0;
 
-	for (i = 0; !r && i < rs->md.raid_disks; i++)
-		if (rs->dev[i].data_dev)
-			r = fn(ti,
-				 rs->dev[i].data_dev,
-				 0, /* No offset on data devs */
-				 rs->md.dev_sectors,
-				 data);
+	for (i = 0; !r && i < rs->raid_disks; i++) {
+		if (rs->dev[i].data_dev) {
+			r = fn(ti, rs->dev[i].data_dev,
+			       0, /* No offset on data devs */
+			       rs->md.dev_sectors, data);
+		}
+	}
 
 	return r;
 }
-- 
GitLab


From fce54ed027577517df1e74b7d54dc2b1bd536887 Mon Sep 17 00:00:00 2001
From: John Garry <john.garry@huawei.com>
Date: Thu, 23 Jun 2022 20:41:59 +0800
Subject: [PATCH 1275/1731] scsi: hisi_sas: Limit max hw sectors for v3 HW

If the controller is behind an IOMMU then the IOMMU IOVA caching range can
affect performance, as discussed in [0].

Limit the max HW sectors to not exceed this limit. We need to hardcode the
value until a proper DMA mapping API is available.

[0] https://lore.kernel.org/linux-iommu/20210129092120.1482-1-thunder.leizhen@huawei.com/

Link: https://lore.kernel.org/r/1655988119-223714-1-git-send-email-john.garry@huawei.com
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
---
 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 7d819fc0395e4..eb86afb21aabb 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -2782,6 +2782,7 @@ static int slave_configure_v3_hw(struct scsi_device *sdev)
 	struct hisi_hba *hisi_hba = shost_priv(shost);
 	struct device *dev = hisi_hba->dev;
 	int ret = sas_slave_configure(sdev);
+	unsigned int max_sectors;
 
 	if (ret)
 		return ret;
@@ -2799,6 +2800,12 @@ static int slave_configure_v3_hw(struct scsi_device *sdev)
 		}
 	}
 
+	/* Set according to IOMMU IOVA caching limit */
+	max_sectors = min_t(size_t, queue_max_hw_sectors(sdev->request_queue),
+			    (PAGE_SIZE * 32) >> SECTOR_SHIFT);
+
+	blk_queue_max_hw_sectors(sdev->request_queue, max_sectors);
+
 	return 0;
 }
 
-- 
GitLab


From a8fc8cb5692aebb9c6f7afd4265366d25dcd1d01 Mon Sep 17 00:00:00 2001
From: Jakub Kicinski <kuba@kernel.org>
Date: Wed, 22 Jun 2022 21:21:05 -0700
Subject: [PATCH 1276/1731] net: tun: stop NAPI when detaching queues

While looking at a syzbot report I noticed the NAPI only gets
disabled before it's deleted. I think that user can detach
the queue before destroying the device and the NAPI will never
be stopped.

Fixes: 943170998b20 ("tun: enable NAPI for TUN/TAP driver")
Acked-by: Petar Penkov <ppenkov@aviatrix.com>
Link: https://lore.kernel.org/r/20220623042105.2274812-1-kuba@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/tun.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/net/tun.c b/drivers/net/tun.c
index 7fd0288c37898..e2eb35887394e 100644
--- a/drivers/net/tun.c
+++ b/drivers/net/tun.c
@@ -273,6 +273,12 @@ static void tun_napi_init(struct tun_struct *tun, struct tun_file *tfile,
 	}
 }
 
+static void tun_napi_enable(struct tun_file *tfile)
+{
+	if (tfile->napi_enabled)
+		napi_enable(&tfile->napi);
+}
+
 static void tun_napi_disable(struct tun_file *tfile)
 {
 	if (tfile->napi_enabled)
@@ -653,8 +659,10 @@ static void __tun_detach(struct tun_file *tfile, bool clean)
 		if (clean) {
 			RCU_INIT_POINTER(tfile->tun, NULL);
 			sock_put(&tfile->sk);
-		} else
+		} else {
 			tun_disable_queue(tun, tfile);
+			tun_napi_disable(tfile);
+		}
 
 		synchronize_net();
 		tun_flow_delete_by_queue(tun, tun->numqueues + 1);
@@ -808,6 +816,7 @@ static int tun_attach(struct tun_struct *tun, struct file *file,
 
 	if (tfile->detached) {
 		tun_enable_queue(tfile);
+		tun_napi_enable(tfile);
 	} else {
 		sock_hold(&tfile->sk);
 		tun_napi_init(tun, tfile, napi, napi_frags);
-- 
GitLab


From 8ee9d82cd0a45e7d050ade598c9f33032a0f2891 Mon Sep 17 00:00:00 2001
From: Tong Zhang <ztong0001@gmail.com>
Date: Sun, 26 Jun 2022 21:33:48 -0700
Subject: [PATCH 1277/1731] epic100: fix use after free on rmmod

epic_close() calls epic_rx() and uses dma buffer, but in epic_remove_one()
we already freed the dma buffer. To fix this issue, reorder function calls
like in the .probe function.

BUG: KASAN: use-after-free in epic_rx+0xa6/0x7e0 [epic100]
Call Trace:
 epic_rx+0xa6/0x7e0 [epic100]
 epic_close+0xec/0x2f0 [epic100]
 unregister_netdev+0x18/0x20
 epic_remove_one+0xaa/0xf0 [epic100]

Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Reported-by: Yilun Wu <yiluwu@cs.stonybrook.edu>
Signed-off-by: Tong Zhang <ztong0001@gmail.com>
Reviewed-by: Francois Romieu <romieu@fr.zoreil.com>
Link: https://lore.kernel.org/r/20220627043351.25615-1-ztong0001@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/ethernet/smsc/epic100.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/smsc/epic100.c b/drivers/net/ethernet/smsc/epic100.c
index a0654e88444cf..0329caf63279c 100644
--- a/drivers/net/ethernet/smsc/epic100.c
+++ b/drivers/net/ethernet/smsc/epic100.c
@@ -1515,14 +1515,14 @@ static void epic_remove_one(struct pci_dev *pdev)
 	struct net_device *dev = pci_get_drvdata(pdev);
 	struct epic_private *ep = netdev_priv(dev);
 
+	unregister_netdev(dev);
 	dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, ep->tx_ring,
 			  ep->tx_ring_dma);
 	dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, ep->rx_ring,
 			  ep->rx_ring_dma);
-	unregister_netdev(dev);
 	pci_iounmap(pdev, ep->ioaddr);
-	pci_release_regions(pdev);
 	free_netdev(dev);
+	pci_release_regions(pdev);
 	pci_disable_device(pdev);
 	/* pci_power_off(pdev, -1); */
 }
-- 
GitLab


From 76b39b94382f9e0a639e1c70c3253de248cc4c83 Mon Sep 17 00:00:00 2001
From: Victor Nogueira <victor@mojatatu.com>
Date: Thu, 23 Jun 2022 11:07:41 -0300
Subject: [PATCH 1278/1731] net/sched: act_api: Notify user space if any
 actions were flushed before error

If during an action flush operation one of the actions is still being
referenced, the flush operation is aborted and the kernel returns to
user space with an error. However, if the kernel was able to flush, for
example, 3 actions and failed on the fourth, the kernel will not notify
user space that it deleted 3 actions before failing.

This patch fixes that behaviour by notifying user space of how many
actions were deleted before flush failed and by setting extack with a
message describing what happened.

Fixes: 55334a5db5cd ("net_sched: act: refuse to remove bound action outside")
Signed-off-by: Victor Nogueira <victor@mojatatu.com>
Acked-by: Jamal Hadi Salim <jhs@mojatatu.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/sched/act_api.c | 22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/net/sched/act_api.c b/net/sched/act_api.c
index da9733da9868f..817065aa28331 100644
--- a/net/sched/act_api.c
+++ b/net/sched/act_api.c
@@ -588,7 +588,8 @@ static int tcf_idr_release_unsafe(struct tc_action *p)
 }
 
 static int tcf_del_walker(struct tcf_idrinfo *idrinfo, struct sk_buff *skb,
-			  const struct tc_action_ops *ops)
+			  const struct tc_action_ops *ops,
+			  struct netlink_ext_ack *extack)
 {
 	struct nlattr *nest;
 	int n_i = 0;
@@ -604,20 +605,25 @@ static int tcf_del_walker(struct tcf_idrinfo *idrinfo, struct sk_buff *skb,
 	if (nla_put_string(skb, TCA_KIND, ops->kind))
 		goto nla_put_failure;
 
+	ret = 0;
 	mutex_lock(&idrinfo->lock);
 	idr_for_each_entry_ul(idr, p, tmp, id) {
 		if (IS_ERR(p))
 			continue;
 		ret = tcf_idr_release_unsafe(p);
-		if (ret == ACT_P_DELETED) {
+		if (ret == ACT_P_DELETED)
 			module_put(ops->owner);
-			n_i++;
-		} else if (ret < 0) {
-			mutex_unlock(&idrinfo->lock);
-			goto nla_put_failure;
-		}
+		else if (ret < 0)
+			break;
+		n_i++;
 	}
 	mutex_unlock(&idrinfo->lock);
+	if (ret < 0) {
+		if (n_i)
+			NL_SET_ERR_MSG(extack, "Unable to flush all TC actions");
+		else
+			goto nla_put_failure;
+	}
 
 	ret = nla_put_u32(skb, TCA_FCNT, n_i);
 	if (ret)
@@ -638,7 +644,7 @@ int tcf_generic_walker(struct tc_action_net *tn, struct sk_buff *skb,
 	struct tcf_idrinfo *idrinfo = tn->idrinfo;
 
 	if (type == RTM_DELACTION) {
-		return tcf_del_walker(idrinfo, skb, ops);
+		return tcf_del_walker(idrinfo, skb, ops, extack);
 	} else if (type == RTM_GETACTION) {
 		return tcf_dump_walker(idrinfo, skb, cb);
 	} else {
-- 
GitLab


From 88153e29c1e0f3ace8c831b06f6cea9503f16cec Mon Sep 17 00:00:00 2001
From: Victor Nogueira <victor@mojatatu.com>
Date: Thu, 23 Jun 2022 11:07:42 -0300
Subject: [PATCH 1279/1731] selftests: tc-testing: Add testcases to test new
 flush behaviour

Add tdc test cases to verify new flush behaviour is correct, which do
the following:

- Try to flush only one action which is being referenced by a filter
- Try to flush three actions where the last one (index 3) is being
  referenced by a filter

Signed-off-by: Victor Nogueira <victor@mojatatu.com>
Acked-by: Jamal Hadi Salim <jhs@mojatatu.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 .../tc-testing/tc-tests/actions/gact.json     | 77 +++++++++++++++++++
 1 file changed, 77 insertions(+)

diff --git a/tools/testing/selftests/tc-testing/tc-tests/actions/gact.json b/tools/testing/selftests/tc-testing/tc-tests/actions/gact.json
index b24494c6f5465..c652e8c1157dc 100644
--- a/tools/testing/selftests/tc-testing/tc-tests/actions/gact.json
+++ b/tools/testing/selftests/tc-testing/tc-tests/actions/gact.json
@@ -609,5 +609,82 @@
         "teardown": [
             "$TC actions flush action gact"
         ]
+    },
+    {
+        "id": "7f52",
+        "name": "Try to flush action which is referenced by filter",
+        "category": [
+            "actions",
+            "gact"
+        ],
+        "plugins": {
+            "requires": "nsPlugin"
+        },
+        "setup": [
+            [
+                "$TC actions flush action gact",
+                0,
+                1,
+                255
+            ],
+            "$TC qdisc add dev $DEV1 ingress",
+            "$TC actions add action pass index 1",
+            "$TC filter add dev $DEV1 protocol all ingress prio 1 handle 0x1234 matchall action gact index 1"
+        ],
+        "cmdUnderTest": "$TC actions flush action gact",
+        "expExitCode": "1",
+        "verifyCmd": "$TC actions ls action gact",
+        "matchPattern": "total acts 1.*action order [0-9]*: gact action pass.*index 1 ref 2 bind 1",
+        "matchCount": "1",
+        "teardown": [
+            "$TC qdisc del dev $DEV1 ingress",
+            [
+                "sleep 1; $TC actions flush action gact",
+                0,
+                1
+            ]
+        ]
+    },
+    {
+        "id": "ae1e",
+        "name": "Try to flush actions when last one is referenced by filter",
+        "category": [
+            "actions",
+            "gact"
+        ],
+        "plugins": {
+            "requires": "nsPlugin"
+        },
+        "setup": [
+            [
+                "$TC actions flush action gact",
+                0,
+                1,
+                255
+            ],
+            "$TC qdisc add dev $DEV1 ingress",
+	    [
+                "$TC actions add action pass index 1",
+		0,
+		1,
+		255
+	    ],
+            "$TC actions add action reclassify index 2",
+            "$TC actions add action drop index 3",
+            "$TC filter add dev $DEV1 protocol all ingress prio 1 handle 0x1234 matchall action gact index 3"
+        ],
+        "cmdUnderTest": "$TC actions flush action gact",
+        "expExitCode": "0",
+        "verifyCmd": "$TC actions ls action gact",
+        "matchPattern": "total acts 1.*action order [0-9]*: gact action drop.*index 3 ref 2 bind 1",
+        "matchCount": "1",
+        "teardown": [
+            "$TC qdisc del dev $DEV1 ingress",
+            [
+                "sleep 1; $TC actions flush action gact",
+                0,
+                1
+            ]
+        ]
     }
 ]
-- 
GitLab


From 4bbfed9112ca9da88ac83d5ffe62c988f7169e9f Mon Sep 17 00:00:00 2001
From: Shreenidhi Shedi <sshedi@vmware.com>
Date: Sun, 26 Jun 2022 18:59:47 +0530
Subject: [PATCH 1280/1731] octeon_ep: use bitwise AND

This should be bitwise operator not logical.

Fixes: 862cd659a6fb ("octeon_ep: Add driver framework and device initialization")
Signed-off-by: Shreenidhi Shedi <sshedi@vmware.com>
Link: https://lore.kernel.org/r/20220626132947.3992423-1-sshedi@vmware.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
index cc51149790ff6..3d5d39a52fe64 100644
--- a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
+++ b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
@@ -52,7 +52,7 @@
 
 #define    CN93_SDP_EPF_RINFO_SRN(val)           ((val) & 0xFF)
 #define    CN93_SDP_EPF_RINFO_RPVF(val)          (((val) >> 32) & 0xF)
-#define    CN93_SDP_EPF_RINFO_NVFS(val)          (((val) >> 48) && 0xFF)
+#define    CN93_SDP_EPF_RINFO_NVFS(val)          (((val) >> 48) & 0xFF)
 
 /* SDP Function select */
 #define    CN93_SDP_FUNC_SEL_EPF_BIT_POS         8
-- 
GitLab


From 6b9f1d46fdada756294d2d5f04df613478386d34 Mon Sep 17 00:00:00 2001
From: Michael Walle <michael@walle.cc>
Date: Sun, 26 Jun 2022 22:00:39 +0200
Subject: [PATCH 1281/1731] MAINTAINERS: nfc: drop Charles Gorand from NXP-NCI

Mails to Charles get an auto reply, that he is no longer working at
Eff'Innov technologies. Drop the entry and mark the driver as orphaned.

Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220626200039.4062784-1-michael@walle.cc
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 MAINTAINERS | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 6cc8258577225..6a288d59ff79c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14350,9 +14350,8 @@ F:	Documentation/devicetree/bindings/sound/nxp,tfa989x.yaml
 F:	sound/soc/codecs/tfa989x.c
 
 NXP-NCI NFC DRIVER
-R:	Charles Gorand <charles.gorand@effinnov.com>
 L:	linux-nfc@lists.01.org (subscribers-only)
-S:	Supported
+S:	Orphan
 F:	Documentation/devicetree/bindings/net/nfc/nxp,nci.yaml
 F:	drivers/nfc/nxp-nci
 
-- 
GitLab


From 805206e66fab4ba1e0ebd19402006d62cd1d4902 Mon Sep 17 00:00:00 2001
From: Oleksij Rempel <o.rempel@pengutronix.de>
Date: Fri, 24 Jun 2022 09:51:38 +0200
Subject: [PATCH 1282/1731] net: asix: fix "can't send until first packet is
 send" issue

If cable is attached after probe sequence, the usbnet framework would
not automatically start processing RX packets except at least one
packet was transmitted.

On systems with any kind of address auto configuration this issue was
not detected, because some packets are send immediately after link state
is changed to "running".

With this patch we will notify usbnet about link status change provided by the
PHYlib.

Fixes: e532a096be0e ("net: usb: asix: ax88772: add phylib support")
Reported-by: Anton Lundin <glance@acc.umu.se>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Tested-by: Anton Lundin <glance@acc.umu.se>
Link: https://lore.kernel.org/r/20220624075139.3139300-1-o.rempel@pengutronix.de
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/usb/asix_common.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/usb/asix_common.c b/drivers/net/usb/asix_common.c
index 632fa6c1d5e30..b4a1b7abcfc97 100644
--- a/drivers/net/usb/asix_common.c
+++ b/drivers/net/usb/asix_common.c
@@ -431,6 +431,7 @@ void asix_adjust_link(struct net_device *netdev)
 
 	asix_write_medium_mode(dev, mode, 0);
 	phy_print_status(phydev);
+	usbnet_link_change(dev, phydev->link, 0);
 }
 
 int asix_write_gpio(struct usbnet *dev, u16 value, int sleep, int in_pm)
-- 
GitLab


From ce95ab775f8d8e89a038c0e5611a7381a2ef8e43 Mon Sep 17 00:00:00 2001
From: Oleksij Rempel <o.rempel@pengutronix.de>
Date: Fri, 24 Jun 2022 09:51:39 +0200
Subject: [PATCH 1283/1731] net: usb: asix: do not force pause frames support

We should respect link partner capabilities and not force flow control
support on every link. Even more, in current state the MAC driver do not
advertises pause support so we should not keep flow control enabled at
all.

Fixes: e532a096be0e ("net: usb: asix: ax88772: add phylib support")
Reported-by: Anton Lundin <glance@acc.umu.se>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Tested-by: Anton Lundin <glance@acc.umu.se>
Link: https://lore.kernel.org/r/20220624075139.3139300-2-o.rempel@pengutronix.de
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/usb/asix.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/net/usb/asix.h b/drivers/net/usb/asix.h
index 2c81236c6c7c6..45d3cc5cc355e 100644
--- a/drivers/net/usb/asix.h
+++ b/drivers/net/usb/asix.h
@@ -126,8 +126,7 @@
 	 AX_MEDIUM_RE)
 
 #define AX88772_MEDIUM_DEFAULT	\
-	(AX_MEDIUM_FD | AX_MEDIUM_RFC | \
-	 AX_MEDIUM_TFC | AX_MEDIUM_PS | \
+	(AX_MEDIUM_FD | AX_MEDIUM_PS | \
 	 AX_MEDIUM_AC | AX_MEDIUM_RE)
 
 /* AX88772 & AX88178 RX_CTL values */
-- 
GitLab


From 3b0dc529f56b5f2328244130683210be98f16f7f Mon Sep 17 00:00:00 2001
From: Nicolas Dichtel <nicolas.dichtel@6wind.com>
Date: Thu, 23 Jun 2022 14:00:15 +0200
Subject: [PATCH 1284/1731] ipv6: take care of disable_policy when restoring
 routes

When routes corresponding to addresses are restored by
fixup_permanent_addr(), the dst_nopolicy parameter was not set.
The typical use case is a user that configures an address on a down
interface and then put this interface up.

Let's take care of this flag in addrconf_f6i_alloc(), so that every callers
benefit ont it.

CC: stable@kernel.org
CC: David Forster <dforster@brocade.com>
Fixes: df789fe75206 ("ipv6: Provide ipv6 version of "disable_policy" sysctl")
Reported-by: Siwar Zitouni <siwar.zitouni@6wind.com>
Signed-off-by: Nicolas Dichtel <nicolas.dichtel@6wind.com>
Reviewed-by: David Ahern <dsahern@kernel.org>
Link: https://lore.kernel.org/r/20220623120015.32640-1-nicolas.dichtel@6wind.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/ipv6/addrconf.c | 4 ----
 net/ipv6/route.c    | 9 ++++++++-
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c
index 1b1932502e9e7..5864cbc30db69 100644
--- a/net/ipv6/addrconf.c
+++ b/net/ipv6/addrconf.c
@@ -1109,10 +1109,6 @@ ipv6_add_addr(struct inet6_dev *idev, struct ifa6_config *cfg,
 		goto out;
 	}
 
-	if (net->ipv6.devconf_all->disable_policy ||
-	    idev->cnf.disable_policy)
-		f6i->dst_nopolicy = true;
-
 	neigh_parms_data_state_setall(idev->nd_parms);
 
 	ifa->addr = *cfg->pfx;
diff --git a/net/ipv6/route.c b/net/ipv6/route.c
index d25dc83bac627..828355710c57b 100644
--- a/net/ipv6/route.c
+++ b/net/ipv6/route.c
@@ -4569,8 +4569,15 @@ struct fib6_info *addrconf_f6i_alloc(struct net *net,
 	}
 
 	f6i = ip6_route_info_create(&cfg, gfp_flags, NULL);
-	if (!IS_ERR(f6i))
+	if (!IS_ERR(f6i)) {
 		f6i->dst_nocount = true;
+
+		if (!anycast &&
+		    (net->ipv6.devconf_all->disable_policy ||
+		     idev->cnf.disable_policy))
+			f6i->dst_nopolicy = true;
+	}
+
 	return f6i;
 }
 
-- 
GitLab


From 4ff5a9b6d95f3524bf6d27147df497eb21968300 Mon Sep 17 00:00:00 2001
From: Liang He <windhl@126.com>
Date: Wed, 15 Jun 2022 17:48:07 +0800
Subject: [PATCH 1285/1731] drivers: cpufreq: Add missing of_node_put() in
 qoriq-cpufreq.c

In qoriq_cpufreq_probe(), of_find_matching_node() will return a
node pointer with refcount incremented. We should use of_node_put()
when it is not used anymore.

Fixes: 157f527639da ("cpufreq: qoriq: convert to a platform driver")
[ Viresh: Fixed Author's name in commit log ]
Signed-off-by: Liang He <windhl@126.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
 drivers/cpufreq/qoriq-cpufreq.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
index 6b6b20da2bcfc..573b417e14833 100644
--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
@@ -275,6 +275,7 @@ static int qoriq_cpufreq_probe(struct platform_device *pdev)
 
 	np = of_find_matching_node(NULL, qoriq_cpufreq_blacklist);
 	if (np) {
+		of_node_put(np);
 		dev_info(&pdev->dev, "Disabling due to erratum A-008083");
 		return -ENODEV;
 	}
-- 
GitLab


From 668a7a12ded7077d4fd7ad1305667e559907e5bb Mon Sep 17 00:00:00 2001
From: Stephen Boyd <swboyd@chromium.org>
Date: Thu, 16 Jun 2022 15:45:31 -0700
Subject: [PATCH 1286/1731] cpufreq: qcom-hw: Don't do lmh things without a
 throttle interrupt

Offlining cpu6 and cpu7 and then onlining cpu6 hangs on
sc7180-trogdor-lazor because the throttle interrupt doesn't exist.
Similarly, things go sideways when suspend/resume runs. That's because
the qcom_cpufreq_hw_cpu_online() and qcom_cpufreq_hw_lmh_exit()
functions are calling genirq APIs with an interrupt value of '-6', i.e.
-ENXIO, and that isn't good.

Check the value of the throttle interrupt like we already do in other
functions in this file and bail out early from lmh code to fix the hang.

Reported-by: Rob Clark <robdclark@chromium.org>
Cc: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: a1eb080a0447 ("cpufreq: qcom-hw: provide online/offline operations")
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
 drivers/cpufreq/qcom-cpufreq-hw.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c
index 0253731d6d25d..36c79580fba25 100644
--- a/drivers/cpufreq/qcom-cpufreq-hw.c
+++ b/drivers/cpufreq/qcom-cpufreq-hw.c
@@ -442,6 +442,9 @@ static int qcom_cpufreq_hw_cpu_online(struct cpufreq_policy *policy)
 	struct platform_device *pdev = cpufreq_get_driver_data();
 	int ret;
 
+	if (data->throttle_irq <= 0)
+		return 0;
+
 	ret = irq_set_affinity_hint(data->throttle_irq, policy->cpus);
 	if (ret)
 		dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
@@ -469,6 +472,9 @@ static int qcom_cpufreq_hw_cpu_offline(struct cpufreq_policy *policy)
 
 static void qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data *data)
 {
+	if (data->throttle_irq <= 0)
+		return;
+
 	free_irq(data->throttle_irq, data);
 }
 
-- 
GitLab


From ccd7567d4b6cf187fdfa55f003a9e461ee629e36 Mon Sep 17 00:00:00 2001
From: Liang He <windhl@126.com>
Date: Sat, 18 Jun 2022 10:25:45 +0800
Subject: [PATCH 1287/1731] cpufreq: pmac32-cpufreq: Fix refcount leak bug

In pmac_cpufreq_init_MacRISC3(), we need to add corresponding
of_node_put() for the three node pointers whose refcount have
been incremented by of_find_node_by_name().

Signed-off-by: Liang He <windhl@126.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
 drivers/cpufreq/pmac32-cpufreq.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/cpufreq/pmac32-cpufreq.c b/drivers/cpufreq/pmac32-cpufreq.c
index 20f64a8b0a354..4b8ee2014da6d 100644
--- a/drivers/cpufreq/pmac32-cpufreq.c
+++ b/drivers/cpufreq/pmac32-cpufreq.c
@@ -470,6 +470,10 @@ static int pmac_cpufreq_init_MacRISC3(struct device_node *cpunode)
 	if (slew_done_gpio_np)
 		slew_done_gpio = read_gpio(slew_done_gpio_np);
 
+	of_node_put(volt_gpio_np);
+	of_node_put(freq_gpio_np);
+	of_node_put(slew_done_gpio_np);
+
 	/* If we use the frequency GPIOs, calculate the min/max speeds based
 	 * on the bus frequencies
 	 */
-- 
GitLab


From be4b61ec45b3efe5e9077525fc92d544305eb2a6 Mon Sep 17 00:00:00 2001
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Date: Fri, 17 Jun 2022 13:09:26 +0200
Subject: [PATCH 1288/1731] cpufreq: Add MT8186 to cpufreq-dt-platdev blocklist

This SoC shall use the mediatek-cpufreq driver, or the system will
crash upon any clock scaling request: add it to the cpufreq-dt-platdev
blocklist.

Fixes: 39b360102f3a ("cpufreq: mediatek: Add support for MT8186")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
 drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 96de1536e1cbf..2c96de3f2d83c 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -127,6 +127,7 @@ static const struct of_device_id blocklist[] __initconst = {
 	{ .compatible = "mediatek,mt8173", },
 	{ .compatible = "mediatek,mt8176", },
 	{ .compatible = "mediatek,mt8183", },
+	{ .compatible = "mediatek,mt8186", },
 	{ .compatible = "mediatek,mt8365", },
 	{ .compatible = "mediatek,mt8516", },
 
-- 
GitLab


From 8520501346ed8d1c4a6dfa751cb57328a9c843f1 Mon Sep 17 00:00:00 2001
From: Stafford Horne <shorne@gmail.com>
Date: Wed, 15 Jun 2022 08:54:26 +0900
Subject: [PATCH 1289/1731] irqchip: or1k-pic: Undefine mask_ack for level
 triggered hardware

The mask_ack operation clears the interrupt by writing to the PICSR
register.  This we don't want for level triggered interrupt because
it does not actually clear the interrupt on the source hardware.

This was causing issues in qemu with multi core setups where
interrupts would continue to fire even though they had been cleared in
PICSR.

Just remove the mask_ack operation.

Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 drivers/irqchip/irq-or1k-pic.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/irqchip/irq-or1k-pic.c b/drivers/irqchip/irq-or1k-pic.c
index 49b47e7876448..f289ccd952914 100644
--- a/drivers/irqchip/irq-or1k-pic.c
+++ b/drivers/irqchip/irq-or1k-pic.c
@@ -66,7 +66,6 @@ static struct or1k_pic_dev or1k_pic_level = {
 		.name = "or1k-PIC-level",
 		.irq_unmask = or1k_pic_unmask,
 		.irq_mask = or1k_pic_mask,
-		.irq_mask_ack = or1k_pic_mask_ack,
 	},
 	.handle = handle_level_irq,
 	.flags = IRQ_LEVEL | IRQ_NOPROBE,
-- 
GitLab


From 48bddb89d59eec27c3305d179b1832d5292e285d Mon Sep 17 00:00:00 2001
From: Xiang wangx <wangxiang@cdjrlc.com>
Date: Thu, 2 Jun 2022 16:53:50 +0800
Subject: [PATCH 1290/1731] openrisc: unwinder: Fix grammar issue in comment

Delete the redundant word 'the'.

Signed-off-by: Xiang wangx <wangxiang@cdjrlc.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/kernel/unwinder.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/openrisc/kernel/unwinder.c b/arch/openrisc/kernel/unwinder.c
index 8ae15c2c18459..c6ad6f867a6a8 100644
--- a/arch/openrisc/kernel/unwinder.c
+++ b/arch/openrisc/kernel/unwinder.c
@@ -25,7 +25,7 @@ struct or1k_frameinfo {
 /*
  * Verify a frameinfo structure.  The return address should be a valid text
  * address.  The frame pointer may be null if its the last frame, otherwise
- * the frame pointer should point to a location in the stack after the the
+ * the frame pointer should point to a location in the stack after the
  * top of the next frame up.
  */
 static inline int or1k_frameinfo_valid(struct or1k_frameinfo *frameinfo)
-- 
GitLab


From 8698e3bab4dd7968666e84e111d0bfd17c040e77 Mon Sep 17 00:00:00 2001
From: Amir Goldstein <amir73il@gmail.com>
Date: Mon, 27 Jun 2022 20:47:19 +0300
Subject: [PATCH 1291/1731] fanotify: refine the validation checks on non-dir
 inode mask

Commit ceaf69f8eadc ("fanotify: do not allow setting dirent events in
mask of non-dir") added restrictions about setting dirent events in the
mask of a non-dir inode mark, which does not make any sense.

For backward compatibility, these restictions were added only to new
(v5.17+) APIs.

It also does not make any sense to set the flags FAN_EVENT_ON_CHILD or
FAN_ONDIR in the mask of a non-dir inode.  Add these flags to the
dir-only restriction of the new APIs as well.

Move the check of the dir-only flags for new APIs into the helper
fanotify_events_supported(), which is only called for FAN_MARK_ADD,
because there is no need to error on an attempt to remove the dir-only
flags from non-dir inode.

Fixes: ceaf69f8eadc ("fanotify: do not allow setting dirent events in mask of non-dir")
Link: https://lore.kernel.org/linux-fsdevel/20220627113224.kr2725conevh53u4@quack3.lan/
Link: https://lore.kernel.org/r/20220627174719.2838175-1-amir73il@gmail.com
Signed-off-by: Amir Goldstein <amir73il@gmail.com>
Signed-off-by: Jan Kara <jack@suse.cz>
---
 fs/notify/fanotify/fanotify_user.c | 34 +++++++++++++++++-------------
 include/linux/fanotify.h           |  4 ++++
 2 files changed, 23 insertions(+), 15 deletions(-)

diff --git a/fs/notify/fanotify/fanotify_user.c b/fs/notify/fanotify/fanotify_user.c
index c2255b440df9f..b08ce0d821a7f 100644
--- a/fs/notify/fanotify/fanotify_user.c
+++ b/fs/notify/fanotify/fanotify_user.c
@@ -1513,8 +1513,15 @@ static int fanotify_test_fid(struct dentry *dentry)
 	return 0;
 }
 
-static int fanotify_events_supported(struct path *path, __u64 mask)
+static int fanotify_events_supported(struct fsnotify_group *group,
+				     struct path *path, __u64 mask,
+				     unsigned int flags)
 {
+	unsigned int mark_type = flags & FANOTIFY_MARK_TYPE_BITS;
+	/* Strict validation of events in non-dir inode mask with v5.17+ APIs */
+	bool strict_dir_events = FAN_GROUP_FLAG(group, FAN_REPORT_TARGET_FID) ||
+				 (mask & FAN_RENAME);
+
 	/*
 	 * Some filesystems such as 'proc' acquire unusual locks when opening
 	 * files. For them fanotify permission events have high chances of
@@ -1526,6 +1533,16 @@ static int fanotify_events_supported(struct path *path, __u64 mask)
 	if (mask & FANOTIFY_PERM_EVENTS &&
 	    path->mnt->mnt_sb->s_type->fs_flags & FS_DISALLOW_NOTIFY_PERM)
 		return -EINVAL;
+
+	/*
+	 * We shouldn't have allowed setting dirent events and the directory
+	 * flags FAN_ONDIR and FAN_EVENT_ON_CHILD in mask of non-dir inode,
+	 * but because we always allowed it, error only when using new APIs.
+	 */
+	if (strict_dir_events && mark_type == FAN_MARK_INODE &&
+	    !d_is_dir(path->dentry) && (mask & FANOTIFY_DIRONLY_EVENT_BITS))
+		return -ENOTDIR;
+
 	return 0;
 }
 
@@ -1672,7 +1689,7 @@ static int do_fanotify_mark(int fanotify_fd, unsigned int flags, __u64 mask,
 		goto fput_and_out;
 
 	if (flags & FAN_MARK_ADD) {
-		ret = fanotify_events_supported(&path, mask);
+		ret = fanotify_events_supported(group, &path, mask, flags);
 		if (ret)
 			goto path_put_and_out;
 	}
@@ -1695,19 +1712,6 @@ static int do_fanotify_mark(int fanotify_fd, unsigned int flags, __u64 mask,
 	else
 		mnt = path.mnt;
 
-	/*
-	 * FAN_RENAME is not allowed on non-dir (for now).
-	 * We shouldn't have allowed setting any dirent events in mask of
-	 * non-dir, but because we always allowed it, error only if group
-	 * was initialized with the new flag FAN_REPORT_TARGET_FID.
-	 */
-	ret = -ENOTDIR;
-	if (inode && !S_ISDIR(inode->i_mode) &&
-	    ((mask & FAN_RENAME) ||
-	     ((mask & FANOTIFY_DIRENT_EVENTS) &&
-	      FAN_GROUP_FLAG(group, FAN_REPORT_TARGET_FID))))
-		goto path_put_and_out;
-
 	/* Mask out FAN_EVENT_ON_CHILD flag for sb/mount/non-dir marks */
 	if (mnt || !S_ISDIR(inode->i_mode)) {
 		mask &= ~FAN_EVENT_ON_CHILD;
diff --git a/include/linux/fanotify.h b/include/linux/fanotify.h
index edc28555814ca..e517dbcf74ed2 100644
--- a/include/linux/fanotify.h
+++ b/include/linux/fanotify.h
@@ -111,6 +111,10 @@
 					 FANOTIFY_PERM_EVENTS | \
 					 FAN_Q_OVERFLOW | FAN_ONDIR)
 
+/* Events and flags relevant only for directories */
+#define FANOTIFY_DIRONLY_EVENT_BITS	(FANOTIFY_DIRENT_EVENTS | \
+					 FAN_EVENT_ON_CHILD | FAN_ONDIR)
+
 #define ALL_FANOTIFY_EVENT_BITS		(FANOTIFY_OUTGOING_EVENTS | \
 					 FANOTIFY_EVENT_FLAGS)
 
-- 
GitLab


From ddc980da8043779119acaca106c6d9b445c9b65b Mon Sep 17 00:00:00 2001
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Date: Mon, 23 May 2022 12:24:19 +0300
Subject: [PATCH 1292/1731] ARM: at91: pm: use proper compatible for sama5d2's
 rtc

Use proper compatible strings for SAMA5D2's RTC IPs. This is necessary
for configuring wakeup sources for ULP1 PM mode.

Fixes: d7484f5c6b3b ("ARM: at91: pm: configure wakeup sources for ULP1 mode")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220523092421.317345-2-claudiu.beznea@microchip.com
---
 arch/arm/mach-at91/pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index b1a43d7bc56ce..4d62f686bd1eb 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -202,7 +202,7 @@ static const struct wakeup_source_info ws_info[] = {
 
 static const struct of_device_id sama5d2_ws_ids[] = {
 	{ .compatible = "atmel,sama5d2-gem",		.data = &ws_info[0] },
-	{ .compatible = "atmel,at91rm9200-rtc",		.data = &ws_info[1] },
+	{ .compatible = "atmel,sama5d2-rtc",		.data = &ws_info[1] },
 	{ .compatible = "atmel,sama5d3-udc",		.data = &ws_info[2] },
 	{ .compatible = "atmel,at91rm9200-ohci",	.data = &ws_info[2] },
 	{ .compatible = "usb-ohci",			.data = &ws_info[2] },
-- 
GitLab


From 641522665dbb25ce117c78746df1aad8b58c80e5 Mon Sep 17 00:00:00 2001
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Date: Mon, 23 May 2022 12:24:20 +0300
Subject: [PATCH 1293/1731] ARM: at91: pm: use proper compatibles for sam9x60's
 rtc and rtt

Use proper compatible strings for SAM9X60's RTC and RTT IPs. These are
necessary for configuring wakeup sources for ULP1 PM mode.

Fixes: eaedc0d379da ("ARM: at91: pm: add ULP1 support for SAM9X60")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220523092421.317345-3-claudiu.beznea@microchip.com
---
 arch/arm/mach-at91/pm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 4d62f686bd1eb..f017b2d1b11eb 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -213,12 +213,12 @@ static const struct of_device_id sama5d2_ws_ids[] = {
 };
 
 static const struct of_device_id sam9x60_ws_ids[] = {
-	{ .compatible = "atmel,at91sam9x5-rtc",		.data = &ws_info[1] },
+	{ .compatible = "microchip,sam9x60-rtc",	.data = &ws_info[1] },
 	{ .compatible = "atmel,at91rm9200-ohci",	.data = &ws_info[2] },
 	{ .compatible = "usb-ohci",			.data = &ws_info[2] },
 	{ .compatible = "atmel,at91sam9g45-ehci",	.data = &ws_info[2] },
 	{ .compatible = "usb-ehci",			.data = &ws_info[2] },
-	{ .compatible = "atmel,at91sam9260-rtt",	.data = &ws_info[4] },
+	{ .compatible = "microchip,sam9x60-rtt",	.data = &ws_info[4] },
 	{ .compatible = "cdns,sam9x60-macb",		.data = &ws_info[5] },
 	{ /* sentinel */ }
 };
-- 
GitLab


From 1c40169b35ad58906814d53a517ac92db3d20d5f Mon Sep 17 00:00:00 2001
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Date: Mon, 23 May 2022 12:24:21 +0300
Subject: [PATCH 1294/1731] ARM: at91: pm: use proper compatibles for sama7g5's
 rtc and rtt

Use proper compatible strings for SAMA7G5's RTC and RTT IPs. These are
necessary for configuring wakeup sources for ULP1 PM mode.

Fixes: 6501330f9f5e ("ARM: at91: pm: add pm support for SAMA7G5")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220523092421.317345-4-claudiu.beznea@microchip.com
---
 arch/arm/mach-at91/pm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index f017b2d1b11eb..826fd56d2a179 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -224,13 +224,13 @@ static const struct of_device_id sam9x60_ws_ids[] = {
 };
 
 static const struct of_device_id sama7g5_ws_ids[] = {
-	{ .compatible = "atmel,at91sam9x5-rtc",		.data = &ws_info[1] },
+	{ .compatible = "microchip,sama7g5-rtc",	.data = &ws_info[1] },
 	{ .compatible = "microchip,sama7g5-ohci",	.data = &ws_info[2] },
 	{ .compatible = "usb-ohci",			.data = &ws_info[2] },
 	{ .compatible = "atmel,at91sam9g45-ehci",	.data = &ws_info[2] },
 	{ .compatible = "usb-ehci",			.data = &ws_info[2] },
 	{ .compatible = "microchip,sama7g5-sdhci",	.data = &ws_info[3] },
-	{ .compatible = "atmel,at91sam9260-rtt",	.data = &ws_info[4] },
+	{ .compatible = "microchip,sama7g5-rtt",	.data = &ws_info[4] },
 	{ /* sentinel */ }
 };
 
-- 
GitLab


From f2cbbc3f926316ccf8ef9363d8a60c1110afc1c7 Mon Sep 17 00:00:00 2001
From: Eugen Hristev <eugen.hristev@microchip.com>
Date: Tue, 7 Jun 2022 12:04:54 +0300
Subject: [PATCH 1295/1731] ARM: dts: at91: sam9x60ek: fix eeprom compatible
 and size

The board has a microchip 24aa025e48 eeprom, which is a 2 Kbits memory,
so it's compatible with at24c02 not at24c32.
Also the size property is wrong, it's not 128 bytes, but 256 bytes.
Thus removing and leaving it to the default (256).

Fixes: 1e5f532c27371 ("ARM: dts: at91: sam9x60: add device tree for soc and board")
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220607090455.80433-1-eugen.hristev@microchip.com
---
 arch/arm/boot/dts/at91-sam9x60ek.dts | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts
index 7719ea3d4933c..81ccb0636a009 100644
--- a/arch/arm/boot/dts/at91-sam9x60ek.dts
+++ b/arch/arm/boot/dts/at91-sam9x60ek.dts
@@ -233,10 +233,9 @@
 		status = "okay";
 
 		eeprom@53 {
-			compatible = "atmel,24c32";
+			compatible = "atmel,24c02";
 			reg = <0x53>;
 			pagesize = <16>;
-			size = <128>;
 			status = "okay";
 		};
 	};
-- 
GitLab


From 416ce193d73a734ded6d09fe141017b38af1c567 Mon Sep 17 00:00:00 2001
From: Eugen Hristev <eugen.hristev@microchip.com>
Date: Tue, 7 Jun 2022 12:04:55 +0300
Subject: [PATCH 1296/1731] ARM: dts: at91: sama5d2_icp: fix eeprom compatibles

The eeprom memories on the board are microchip 24aa025e48, which are 2 Kbits
and are compatible with at24c02 not at24c32.

Fixes: 68a95ef72cefe ("ARM: dts: at91: sama5d2-icp: add SAMA5D2-ICP")
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220607090455.80433-2-eugen.hristev@microchip.com
---
 arch/arm/boot/dts/at91-sama5d2_icp.dts | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts
index 806eb1d911d7c..164201a8fbf2d 100644
--- a/arch/arm/boot/dts/at91-sama5d2_icp.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts
@@ -329,21 +329,21 @@
 	status = "okay";
 
 	eeprom@50 {
-		compatible = "atmel,24c32";
+		compatible = "atmel,24c02";
 		reg = <0x50>;
 		pagesize = <16>;
 		status = "okay";
 	};
 
 	eeprom@52 {
-		compatible = "atmel,24c32";
+		compatible = "atmel,24c02";
 		reg = <0x52>;
 		pagesize = <16>;
 		status = "disabled";
 	};
 
 	eeprom@53 {
-		compatible = "atmel,24c32";
+		compatible = "atmel,24c02";
 		reg = <0x53>;
 		pagesize = <16>;
 		status = "disabled";
-- 
GitLab


From 35074df65a8d8c5328a83e2eea948f7bbc8e6e08 Mon Sep 17 00:00:00 2001
From: Mihai Sain <mihai.sain@microchip.com>
Date: Thu, 16 Jun 2022 11:13:44 +0300
Subject: [PATCH 1297/1731] ARM: at91: fix soc detection for SAM9X60 SiPs

Fix SoC detection for SAM9X60 SiPs:
SAM9X60D5M
SAM9X60D1G
SAM9X60D6K

Fixes: af3a10513cd6 ("drivers: soc: atmel: add per soc id and version match masks")
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220616081344.1978664-1-claudiu.beznea@microchip.com
---
 drivers/soc/atmel/soc.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c
index b2d365ae02823..dae8a2e0f7455 100644
--- a/drivers/soc/atmel/soc.c
+++ b/drivers/soc/atmel/soc.c
@@ -91,14 +91,14 @@ static const struct at91_soc socs[] __initconst = {
 	AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 		 AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
 		 "sam9x60", "sam9x60"),
-	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D5M_EXID_MATCH,
-		 AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
+	AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
+		 AT91_CIDR_VERSION_MASK, SAM9X60_D5M_EXID_MATCH,
 		 "sam9x60 64MiB DDR2 SiP", "sam9x60"),
-	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D1G_EXID_MATCH,
-		 AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
+	AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
+		 AT91_CIDR_VERSION_MASK, SAM9X60_D1G_EXID_MATCH,
 		 "sam9x60 128MiB DDR2 SiP", "sam9x60"),
-	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D6K_EXID_MATCH,
-		 AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
+	AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
+		 AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH,
 		 "sam9x60 8MiB SDRAM SiP", "sam9x60"),
 #endif
 #ifdef CONFIG_SOC_SAMA5
-- 
GitLab


From 91d60e259c0f58c855f88f3fe5b7909aec563525 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <festevam@denx.de>
Date: Wed, 22 Jun 2022 08:48:10 -0300
Subject: [PATCH 1298/1731] ARM: at91: pm: Mark at91_pm_secure_init as __init

at91_pm_secure_init() is used inside sama5d2_pm_init(), which has
the __init notation.

Pass the __init notation to at91_pm_secure_init() as well to fix the
following section mismatch warning:

WARNING: modpost: vmlinux.o(.text.unlikely+0x2138): Section mismatch in reference from the function at91_pm_secure_init() to the (unknown reference) .init.rodata:(unknown)

Fixes: f2f5cf78a333 ("ARM: at91: pm: add support for sama5d2 secure suspend")
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220622114810.1186330-1-festevam@gmail.com
---
 arch/arm/mach-at91/pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 826fd56d2a179..df6d673e83d56 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -1079,7 +1079,7 @@ securam_fail:
 	return ret;
 }
 
-static void at91_pm_secure_init(void)
+static void __init at91_pm_secure_init(void)
 {
 	int suspend_mode;
 	struct arm_smccc_res res;
-- 
GitLab


From 9569ff1a188fe48b46eb1ac2ae4543c271e0d4c2 Mon Sep 17 00:00:00 2001
From: Dan Carpenter <dan.carpenter@oracle.com>
Date: Fri, 24 Jun 2022 09:39:24 +0300
Subject: [PATCH 1299/1731] drm/i915: Fix error code in
 icl_compute_combo_phy_dpll()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This function is supposed to return zero or negative error codes but it
accidentally returns true on failure.

Fixes: 92a020747d6c ("drm/i915: Split shared dpll .get_dplls() into compute and get phases")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YrVcHArNMTGCSy+9@kili
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index ddae7e42ac46d..118598c9a8092 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3184,7 +3184,7 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
 	struct icl_port_dpll *port_dpll =
 		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
 	struct skl_wrpll_params pll_params = {};
-	bool ret;
+	int ret;
 
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
-- 
GitLab


From cea9ed611e85d36a05db52b6457bf584b7d969e2 Mon Sep 17 00:00:00 2001
From: Hangyu Hua <hbh25y@gmail.com>
Date: Fri, 24 Jun 2022 06:04:06 -0700
Subject: [PATCH 1300/1731] drm/i915: fix a possible refcount leak in
 intel_dp_add_mst_connector()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

If drm_connector_init fails, intel_connector_free will be called to take
care of proper free. So it is necessary to drop the refcount of port
before intel_connector_free.

Fixes: 091a4f91942a ("drm/i915: Handle drm-layer errors in intel_dp_add_mst_connector")
Signed-off-by: Hangyu Hua <hbh25y@gmail.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220624130406.17996-1-jose.souza@intel.com
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 061b277e5ce78..14d2a64193b2d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -839,6 +839,7 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
 	ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs,
 				 DRM_MODE_CONNECTOR_DisplayPort);
 	if (ret) {
+		drm_dp_mst_put_port_malloc(port);
 		intel_connector_free(intel_connector);
 		return NULL;
 	}
-- 
GitLab


From fbc24ebc65507feb9728dc38197f90486148dda0 Mon Sep 17 00:00:00 2001
From: Jacky Bai <ping.bai@nxp.com>
Date: Mon, 13 Jun 2022 11:18:54 +0800
Subject: [PATCH 1301/1731] pinctrl: imx: Add the zero base flag for imx93

On i.MX93, the pin mux reg offset is from 0x0,
so need to add the 'ZERO_OFFSET_VALID' flag to make
sure the pin at mux offset 0 can be found.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Link: https://lore.kernel.org/r/20220613031854.1571357-1-ping.bai@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 drivers/pinctrl/freescale/pinctrl-imx93.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/freescale/pinctrl-imx93.c b/drivers/pinctrl/freescale/pinctrl-imx93.c
index c0630f69e9954..417e41b37a6fd 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx93.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx93.c
@@ -239,6 +239,7 @@ static const struct pinctrl_pin_desc imx93_pinctrl_pads[] = {
 static const struct imx_pinctrl_soc_info imx93_pinctrl_info = {
 	.pins = imx93_pinctrl_pads,
 	.npins = ARRAY_SIZE(imx93_pinctrl_pads),
+	.flags = ZERO_OFFSET_VALID,
 	.gpr_compatible = "fsl,imx93-iomuxc-gpr",
 };
 
-- 
GitLab


From ab84db251c04d38b8dc7ee86e13d4050bedb1c88 Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Mon, 27 Jun 2022 10:28:13 +0000
Subject: [PATCH 1302/1731] net: bonding: fix possible NULL deref in rlb code

syzbot has two reports involving the same root cause.

bond_alb_initialize() must not set bond->alb_info.rlb_enabled
if a memory allocation error is detected.

Report 1:

general protection fault, probably for non-canonical address 0xdffffc0000000002: 0000 [#1] PREEMPT SMP KASAN
KASAN: null-ptr-deref in range [0x0000000000000010-0x0000000000000017]
CPU: 0 PID: 12276 Comm: kworker/u4:10 Not tainted 5.19.0-rc3-syzkaller-00132-g3b89b511ea0c #0
Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011
Workqueue: netns cleanup_net
RIP: 0010:rlb_clear_slave+0x10e/0x690 drivers/net/bonding/bond_alb.c:393
Code: 8e fc 83 fb ff 0f 84 74 02 00 00 e8 cc 2a 8e fc 48 8b 44 24 08 89 dd 48 c1 e5 06 4c 8d 34 28 49 8d 7e 14 48 89 f8 48 c1 e8 03 <42> 0f b6 14 20 48 89 f8 83 e0 07 83 c0 03 38 d0 7c 08 84 d2 0f 85
RSP: 0018:ffffc90018a8f678 EFLAGS: 00010203
RAX: 0000000000000002 RBX: 0000000000000000 RCX: 0000000000000000
RDX: ffff88803375bb00 RSI: ffffffff84ec4ac4 RDI: 0000000000000014
RBP: 0000000000000000 R08: 0000000000000005 R09: 00000000ffffffff
R10: 0000000000000000 R11: 0000000000000000 R12: dffffc0000000000
R13: ffff8880ac889000 R14: 0000000000000000 R15: ffff88815a668c80
FS: 0000000000000000(0000) GS:ffff8880b9a00000(0000) knlGS:0000000000000000
CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 00005597077e10b0 CR3: 0000000026668000 CR4: 00000000003506f0
DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
Call Trace:
<TASK>
bond_alb_deinit_slave+0x43c/0x6b0 drivers/net/bonding/bond_alb.c:1663
__bond_release_one.cold+0x383/0xd53 drivers/net/bonding/bond_main.c:2370
bond_slave_netdev_event drivers/net/bonding/bond_main.c:3778 [inline]
bond_netdev_event+0x993/0xad0 drivers/net/bonding/bond_main.c:3889
notifier_call_chain+0xb5/0x200 kernel/notifier.c:87
call_netdevice_notifiers_info+0xb5/0x130 net/core/dev.c:1945
call_netdevice_notifiers_extack net/core/dev.c:1983 [inline]
call_netdevice_notifiers net/core/dev.c:1997 [inline]
unregister_netdevice_many+0x948/0x18b0 net/core/dev.c:10839
default_device_exit_batch+0x449/0x590 net/core/dev.c:11333
ops_exit_list+0x125/0x170 net/core/net_namespace.c:167
cleanup_net+0x4ea/0xb00 net/core/net_namespace.c:594
process_one_work+0x996/0x1610 kernel/workqueue.c:2289
worker_thread+0x665/0x1080 kernel/workqueue.c:2436
kthread+0x2e9/0x3a0 kernel/kthread.c:376
ret_from_fork+0x1f/0x30 arch/x86/entry/entry_64.S:302
</TASK>

Report 2:

general protection fault, probably for non-canonical address 0xdffffc0000000006: 0000 [#1] PREEMPT SMP KASAN
KASAN: null-ptr-deref in range [0x0000000000000030-0x0000000000000037]
CPU: 1 PID: 5206 Comm: syz-executor.1 Not tainted 5.18.0-syzkaller-12108-g58f9d52ff689 #0
Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011
RIP: 0010:rlb_req_update_slave_clients+0x109/0x2f0 drivers/net/bonding/bond_alb.c:502
Code: 5d 18 8f fc 41 80 3e 00 0f 85 a5 01 00 00 89 d8 48 c1 e0 06 49 03 84 24 68 01 00 00 48 8d 78 30 49 89 c7 48 89 fa 48 c1 ea 03 <80> 3c 2a 00 0f 85 98 01 00 00 4d 39 6f 30 75 83 e8 22 18 8f fc 49
RSP: 0018:ffffc9000300ee80 EFLAGS: 00010206
RAX: 0000000000000000 RBX: 0000000000000000 RCX: ffffc90016c11000
RDX: 0000000000000006 RSI: ffffffff84eb6bf3 RDI: 0000000000000030
RBP: dffffc0000000000 R08: 0000000000000005 R09: 00000000ffffffff
R10: 0000000000000000 R11: 0000000000000000 R12: ffff888027c80c80
R13: ffff88807d7ff800 R14: ffffed1004f901bd R15: 0000000000000000
FS:  00007f6f46c58700(0000) GS:ffff8880b9b00000(0000) knlGS:0000000000000000
CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 0000000020010000 CR3: 00000000516cc000 CR4: 00000000003506e0
DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
Call Trace:
 <TASK>
 alb_fasten_mac_swap+0x886/0xa80 drivers/net/bonding/bond_alb.c:1070
 bond_alb_handle_active_change+0x624/0x1050 drivers/net/bonding/bond_alb.c:1765
 bond_change_active_slave+0xfa1/0x29b0 drivers/net/bonding/bond_main.c:1173
 bond_select_active_slave+0x23f/0xa50 drivers/net/bonding/bond_main.c:1253
 bond_enslave+0x3b34/0x53b0 drivers/net/bonding/bond_main.c:2159
 do_set_master+0x1c8/0x220 net/core/rtnetlink.c:2577
 rtnl_newlink_create net/core/rtnetlink.c:3380 [inline]
 __rtnl_newlink+0x13ac/0x17e0 net/core/rtnetlink.c:3580
 rtnl_newlink+0x64/0xa0 net/core/rtnetlink.c:3593
 rtnetlink_rcv_msg+0x43a/0xc90 net/core/rtnetlink.c:6089
 netlink_rcv_skb+0x153/0x420 net/netlink/af_netlink.c:2501
 netlink_unicast_kernel net/netlink/af_netlink.c:1319 [inline]
 netlink_unicast+0x543/0x7f0 net/netlink/af_netlink.c:1345
 netlink_sendmsg+0x917/0xe10 net/netlink/af_netlink.c:1921
 sock_sendmsg_nosec net/socket.c:714 [inline]
 sock_sendmsg+0xcf/0x120 net/socket.c:734
 ____sys_sendmsg+0x6eb/0x810 net/socket.c:2492
 ___sys_sendmsg+0xf3/0x170 net/socket.c:2546
 __sys_sendmsg net/socket.c:2575 [inline]
 __do_sys_sendmsg net/socket.c:2584 [inline]
 __se_sys_sendmsg net/socket.c:2582 [inline]
 __x64_sys_sendmsg+0x132/0x220 net/socket.c:2582
 do_syscall_x64 arch/x86/entry/common.c:50 [inline]
 do_syscall_64+0x35/0xb0 arch/x86/entry/common.c:80
 entry_SYSCALL_64_after_hwframe+0x46/0xb0
RIP: 0033:0x7f6f45a89109
Code: ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 c7 c1 b8 ff ff ff f7 d8 64 89 01 48
RSP: 002b:00007f6f46c58168 EFLAGS: 00000246 ORIG_RAX: 000000000000002e
RAX: ffffffffffffffda RBX: 00007f6f45b9c030 RCX: 00007f6f45a89109
RDX: 0000000000000000 RSI: 0000000020000080 RDI: 0000000000000006
RBP: 00007f6f45ae308d R08: 0000000000000000 R09: 0000000000000000
R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000000
R13: 00007ffed99029af R14: 00007f6f46c58300 R15: 0000000000022000
 </TASK>

Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Reported-by: syzbot <syzkaller@googlegroups.com>
Signed-off-by: Eric Dumazet <edumazet@google.com>
Cc: Jay Vosburgh <j.vosburgh@gmail.com>
Cc: Veaceslav Falico <vfalico@gmail.com>
Cc: Andy Gospodarek <andy@greyhouse.net>
Acked-by: Jay Vosburgh <jay.vosburgh@canonical.com>
Link: https://lore.kernel.org/r/20220627102813.126264-1-edumazet@google.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
 drivers/net/bonding/bond_alb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/bonding/bond_alb.c b/drivers/net/bonding/bond_alb.c
index 303c8d32d451e..007d43e46dcb0 100644
--- a/drivers/net/bonding/bond_alb.c
+++ b/drivers/net/bonding/bond_alb.c
@@ -1302,12 +1302,12 @@ int bond_alb_initialize(struct bonding *bond, int rlb_enabled)
 		return res;
 
 	if (rlb_enabled) {
-		bond->alb_info.rlb_enabled = 1;
 		res = rlb_initialize(bond);
 		if (res) {
 			tlb_deinitialize(bond);
 			return res;
 		}
+		bond->alb_info.rlb_enabled = 1;
 	} else {
 		bond->alb_info.rlb_enabled = 0;
 	}
-- 
GitLab


From 0fe3dbbefb74a8575f61d7801b08dbc50523d60d Mon Sep 17 00:00:00 2001
From: Tao Liu <thomas.liu@ucloud.cn>
Date: Mon, 27 Jun 2022 22:00:04 +0800
Subject: [PATCH 1303/1731] linux/dim: Fix divide by 0 in RDMA DIM

Fix a divide 0 error in rdma_dim_stats_compare() when prev->cpe_ratio ==
0.

CallTrace:
  Hardware name: H3C R4900 G3/RS33M2C9S, BIOS 2.00.37P21 03/12/2020
  task: ffff880194b78000 task.stack: ffffc90006714000
  RIP: 0010:backport_rdma_dim+0x10e/0x240 [mlx_compat]
  RSP: 0018:ffff880c10e83ec0 EFLAGS: 00010202
  RAX: 0000000000002710 RBX: ffff88096cd7f780 RCX: 0000000000000064
  RDX: 0000000000000000 RSI: 0000000000000002 RDI: 0000000000000001
  RBP: 0000000000000001 R08: 0000000000000000 R09: 0000000000000000
  R10: 0000000000000000 R11: 0000000000000000 R12: 000000001d7c6c09
  R13: ffff88096cd7f780 R14: ffff880b174fe800 R15: 0000000000000000
  FS:  0000000000000000(0000) GS:ffff880c10e80000(0000)
  knlGS:0000000000000000
  CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
  CR2: 00000000a0965b00 CR3: 000000000200a003 CR4: 00000000007606e0
  DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
  DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
  PKRU: 55555554
  Call Trace:
   <IRQ>
   ib_poll_handler+0x43/0x80 [ib_core]
   irq_poll_softirq+0xae/0x110
   __do_softirq+0xd1/0x28c
   irq_exit+0xde/0xf0
   do_IRQ+0x54/0xe0
   common_interrupt+0x8f/0x8f
   </IRQ>
   ? cpuidle_enter_state+0xd9/0x2a0
   ? cpuidle_enter_state+0xc7/0x2a0
   ? do_idle+0x170/0x1d0
   ? cpu_startup_entry+0x6f/0x80
   ? start_secondary+0x1b9/0x210
   ? secondary_startup_64+0xa5/0xb0
  Code: 0f 87 e1 00 00 00 8b 4c 24 14 44 8b 43 14 89 c8 4d 63 c8 44 29 c0 99 31 d0 29 d0 31 d2 48 98 48 8d 04 80 48 8d 04 80 48 c1 e0 02 <49> f7 f1 48 83 f8 0a 0f 86 c1 00 00 00 44 39 c1 7f 10 48 89 df
  RIP: backport_rdma_dim+0x10e/0x240 [mlx_compat] RSP: ffff880c10e83ec0

Fixes: f4915455dcf0 ("linux/dim: Implement RDMA adaptive moderation (DIM)")
Link: https://lore.kernel.org/r/20220627140004.3099-1-thomas.liu@ucloud.cn
Signed-off-by: Tao Liu <thomas.liu@ucloud.cn>
Reviewed-by: Max Gurtovoy <mgurtovoy@nvidia.com>
Acked-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
---
 include/linux/dim.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/dim.h b/include/linux/dim.h
index b698266d00356..6c5733981563e 100644
--- a/include/linux/dim.h
+++ b/include/linux/dim.h
@@ -21,7 +21,7 @@
  * We consider 10% difference as significant.
  */
 #define IS_SIGNIFICANT_DIFF(val, ref) \
-	(((100UL * abs((val) - (ref))) / (ref)) > 10)
+	((ref) && (((100UL * abs((val) - (ref))) / (ref)) > 10))
 
 /*
  * Calculate the gap between two values.
-- 
GitLab


From a1d4ef1adf8bbd302067534ead671a94759687ed Mon Sep 17 00:00:00 2001
From: Fabien Dessenne <fabien.dessenne@foss.st.com>
Date: Mon, 27 Jun 2022 16:23:50 +0200
Subject: [PATCH 1304/1731] pinctrl: stm32: fix optional IRQ support to gpios

To act as an interrupt controller, a gpio bank relies on the
"interrupt-parent" of the pin controller.
When this optional "interrupt-parent" misses, do not create any IRQ domain.

This fixes a "NULL pointer in stm32_gpio_domain_alloc()" kernel crash when
the interrupt-parent = <exti> property is not declared in the Device Tree.

Fixes: 0eb9f683336d ("pinctrl: Add IRQ support to STM32 gpios")
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Link: https://lore.kernel.org/r/20220627142350.742973-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 drivers/pinctrl/stm32/pinctrl-stm32.c | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 57a33fb0f2d7d..14bcca73238ae 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -1338,16 +1338,18 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode
 	bank->secure_control = pctl->match_data->secure_control;
 	spin_lock_init(&bank->lock);
 
-	/* create irq hierarchical domain */
-	bank->fwnode = fwnode;
+	if (pctl->domain) {
+		/* create irq hierarchical domain */
+		bank->fwnode = fwnode;
 
-	bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
-					STM32_GPIO_IRQ_LINE, bank->fwnode,
-					&stm32_gpio_domain_ops, bank);
+		bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,
+							   bank->fwnode, &stm32_gpio_domain_ops,
+							   bank);
 
-	if (!bank->domain) {
-		err = -ENODEV;
-		goto err_clk;
+		if (!bank->domain) {
+			err = -ENODEV;
+			goto err_clk;
+		}
 	}
 
 	err = gpiochip_add_data(&bank->gpio_chip, bank);
@@ -1510,6 +1512,8 @@ int stm32_pctl_probe(struct platform_device *pdev)
 	pctl->domain = stm32_pctrl_get_irq_domain(pdev);
 	if (IS_ERR(pctl->domain))
 		return PTR_ERR(pctl->domain);
+	if (!pctl->domain)
+		dev_warn(dev, "pinctrl without interrupt support\n");
 
 	/* hwspinlock is optional */
 	hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
-- 
GitLab


From d6838ec44b4513280a3f43fcc402e246d543fb53 Mon Sep 17 00:00:00 2001
From: Namhyung Kim <namhyung@kernel.org>
Date: Fri, 24 Jun 2022 16:13:08 -0700
Subject: [PATCH 1305/1731] perf offcpu: Fix build failure on old kernels

Old kernels have a 'struct task_struct' which contains a "state" field
and newer kernels have "__state" instead.

While the get_task_state() in the BPF code handles that in some way, it
assumed the current kernel has the new definition and it caused a build
error on old kernels.

We should not assume anything and access them carefully.  Do not use
'task struct' directly access it instead using new and old definitions
in a row.

Fixes: edc41a1099c2d08c ("perf record: Enable off-cpu analysis with BPF")
Reported-by: Ian Rogers <irogers@google.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Cc: Blake Jones <blakejones@google.com>
Cc: Hao Luo <haoluo@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Milian Wolff <milian.wolff@kdab.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Song Liu <songliubraving@fb.com>
Cc: bpf@vger.kernel.org
Link: http://lore.kernel.org/lkml/20220624231313.367909-2-namhyung@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/bpf_skel/off_cpu.bpf.c | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/tools/perf/util/bpf_skel/off_cpu.bpf.c b/tools/perf/util/bpf_skel/off_cpu.bpf.c
index 792ae2847080c..cc6d7fd55118c 100644
--- a/tools/perf/util/bpf_skel/off_cpu.bpf.c
+++ b/tools/perf/util/bpf_skel/off_cpu.bpf.c
@@ -71,6 +71,11 @@ struct {
 	__uint(max_entries, 1);
 } cgroup_filter SEC(".maps");
 
+/* new kernel task_struct definition */
+struct task_struct___new {
+	long __state;
+} __attribute__((preserve_access_index));
+
 /* old kernel task_struct definition */
 struct task_struct___old {
 	long state;
@@ -93,14 +98,17 @@ const volatile bool uses_cgroup_v1 = false;
  */
 static inline int get_task_state(struct task_struct *t)
 {
-	if (bpf_core_field_exists(t->__state))
-		return BPF_CORE_READ(t, __state);
+	/* recast pointer to capture new type for compiler */
+	struct task_struct___new *t_new = (void *)t;
 
-	/* recast pointer to capture task_struct___old type for compiler */
-	struct task_struct___old *t_old = (void *)t;
+	if (bpf_core_field_exists(t_new->__state)) {
+		return BPF_CORE_READ(t_new, __state);
+	} else {
+		/* recast pointer to capture old type for compiler */
+		struct task_struct___old *t_old = (void *)t;
 
-	/* now use old "state" name of the field */
-	return BPF_CORE_READ(t_old, state);
+		return BPF_CORE_READ(t_old, state);
+	}
 }
 
 static inline __u64 get_cgroup_id(struct task_struct *t)
-- 
GitLab


From 49c692b7dfc9b6c06a1dc11359a8780575b16d4a Mon Sep 17 00:00:00 2001
From: Namhyung Kim <namhyung@kernel.org>
Date: Fri, 24 Jun 2022 16:13:09 -0700
Subject: [PATCH 1306/1731] perf offcpu: Accept allowed sample types only

As offcpu-time event is synthesized at the end, it could not get the
all the sample info.  Define OFFCPU_SAMPLE_TYPES for allowed ones and
mask out others in evsel__config() to prevent parse errors.

Because perf sample parsing assumes a specific ordering with the
sample types, setting unsupported one would make it fail to read
data like perf record -d/--data.

Fixes: edc41a1099c2d08c ("perf record: Enable off-cpu analysis with BPF")
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Cc: Blake Jones <blakejones@google.com>
Cc: Hao Luo <haoluo@google.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Milian Wolff <milian.wolff@kdab.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Song Liu <songliubraving@fb.com>
Cc: bpf@vger.kernel.org
Link: http://lore.kernel.org/lkml/20220624231313.367909-3-namhyung@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/bpf_off_cpu.c | 7 ++++++-
 tools/perf/util/evsel.c       | 9 +++++++++
 tools/perf/util/off_cpu.h     | 9 +++++++++
 3 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/tools/perf/util/bpf_off_cpu.c b/tools/perf/util/bpf_off_cpu.c
index b73e84a022648..f289b77135980 100644
--- a/tools/perf/util/bpf_off_cpu.c
+++ b/tools/perf/util/bpf_off_cpu.c
@@ -265,6 +265,12 @@ int off_cpu_write(struct perf_session *session)
 
 	sample_type = evsel->core.attr.sample_type;
 
+	if (sample_type & ~OFFCPU_SAMPLE_TYPES) {
+		pr_err("not supported sample type: %llx\n",
+		       (unsigned long long)sample_type);
+		return -1;
+	}
+
 	if (sample_type & (PERF_SAMPLE_ID | PERF_SAMPLE_IDENTIFIER)) {
 		if (evsel->core.id)
 			sid = evsel->core.id[0];
@@ -319,7 +325,6 @@ int off_cpu_write(struct perf_session *session)
 		}
 		if (sample_type & PERF_SAMPLE_CGROUP)
 			data.array[n++] = key.cgroup_id;
-		/* TODO: handle more sample types */
 
 		size = n * sizeof(u64);
 		data.hdr.size = size;
diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
index ce499c5da8d7b..094b0a9c0bc0f 100644
--- a/tools/perf/util/evsel.c
+++ b/tools/perf/util/evsel.c
@@ -48,6 +48,7 @@
 #include "util.h"
 #include "hashmap.h"
 #include "pmu-hybrid.h"
+#include "off_cpu.h"
 #include "../perf-sys.h"
 #include "util/parse-branch-options.h"
 #include <internal/xyarray.h>
@@ -1102,6 +1103,11 @@ static void evsel__set_default_freq_period(struct record_opts *opts,
 	}
 }
 
+static bool evsel__is_offcpu_event(struct evsel *evsel)
+{
+	return evsel__is_bpf_output(evsel) && !strcmp(evsel->name, OFFCPU_EVENT);
+}
+
 /*
  * The enable_on_exec/disabled value strategy:
  *
@@ -1366,6 +1372,9 @@ void evsel__config(struct evsel *evsel, struct record_opts *opts,
 	 */
 	if (evsel__is_dummy_event(evsel))
 		evsel__reset_sample_bit(evsel, BRANCH_STACK);
+
+	if (evsel__is_offcpu_event(evsel))
+		evsel->core.attr.sample_type &= OFFCPU_SAMPLE_TYPES;
 }
 
 int evsel__set_filter(struct evsel *evsel, const char *filter)
diff --git a/tools/perf/util/off_cpu.h b/tools/perf/util/off_cpu.h
index 548008f74d420..2dd67c60f2119 100644
--- a/tools/perf/util/off_cpu.h
+++ b/tools/perf/util/off_cpu.h
@@ -1,6 +1,8 @@
 #ifndef PERF_UTIL_OFF_CPU_H
 #define PERF_UTIL_OFF_CPU_H
 
+#include <linux/perf_event.h>
+
 struct evlist;
 struct target;
 struct perf_session;
@@ -8,6 +10,13 @@ struct record_opts;
 
 #define OFFCPU_EVENT  "offcpu-time"
 
+#define OFFCPU_SAMPLE_TYPES  (PERF_SAMPLE_IDENTIFIER | PERF_SAMPLE_IP | \
+			      PERF_SAMPLE_TID | PERF_SAMPLE_TIME | \
+			      PERF_SAMPLE_ID | PERF_SAMPLE_CPU | \
+			      PERF_SAMPLE_PERIOD | PERF_SAMPLE_CALLCHAIN | \
+			      PERF_SAMPLE_CGROUP)
+
+
 #ifdef HAVE_BPF_SKEL
 int off_cpu_prepare(struct evlist *evlist, struct target *target,
 		    struct record_opts *opts);
-- 
GitLab


From 117c49505b5918388157321c68c6e5a58b67f649 Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Mon, 21 Dec 2020 12:53:44 -0300
Subject: [PATCH 1307/1731] tools kvm headers arm64: Update KVM headers from
 the kernel sources

To pick the changes from:

  2cde51f1e10f2600 ("KVM: arm64: Hide KVM_REG_ARM_*_BMAP_BIT_COUNT from userspace")
  b22216e1a617ca55 ("KVM: arm64: Add vendor hypervisor firmware register")
  428fd6788d4d0e0d ("KVM: arm64: Add standard hypervisor firmware register")
  05714cab7d63b189 ("KVM: arm64: Setup a framework for hypercall bitmap firmware registers")
  18f3976fdb5da2ba ("KVM: arm64: uapi: Add kvm_debug_exit_arch.hsr_high")
  a5905d6af492ee6a ("KVM: arm64: Allow SMCCC_ARCH_WORKAROUND_3 to be discovered and migrated")

That don't causes any changes in tooling (when built on x86), only
addresses this perf build warning:

  Warning: Kernel ABI header at 'tools/arch/arm64/include/uapi/asm/kvm.h' differs from latest version at 'arch/arm64/include/uapi/asm/kvm.h'
  diff -u tools/arch/arm64/include/uapi/asm/kvm.h arch/arm64/include/uapi/asm/kvm.h

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexandru Elisei <alexandru.elisei@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ian Rogers <irogers@google.com>
Cc: James Morse <james.morse@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Raghavendra Rao Ananta <rananta@google.com>
Link: https://lore.kernel.org/lkml/YrsWcDQyJC+xsfmm@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/arch/arm64/include/uapi/asm/kvm.h | 36 +++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/tools/arch/arm64/include/uapi/asm/kvm.h b/tools/arch/arm64/include/uapi/asm/kvm.h
index c1b6ddc02d2ff..3bb134355874c 100644
--- a/tools/arch/arm64/include/uapi/asm/kvm.h
+++ b/tools/arch/arm64/include/uapi/asm/kvm.h
@@ -139,8 +139,10 @@ struct kvm_guest_debug_arch {
 	__u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS];
 };
 
+#define KVM_DEBUG_ARCH_HSR_HIGH_VALID	(1 << 0)
 struct kvm_debug_exit_arch {
 	__u32 hsr;
+	__u32 hsr_high;	/* ESR_EL2[61:32] */
 	__u64 far;	/* used for watchpoints */
 };
 
@@ -332,6 +334,40 @@ struct kvm_arm_copy_mte_tags {
 #define KVM_ARM64_SVE_VLS_WORDS	\
 	((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1)
 
+/* Bitmap feature firmware registers */
+#define KVM_REG_ARM_FW_FEAT_BMAP		(0x0016 << KVM_REG_ARM_COPROC_SHIFT)
+#define KVM_REG_ARM_FW_FEAT_BMAP_REG(r)		(KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
+						KVM_REG_ARM_FW_FEAT_BMAP |	\
+						((r) & 0xffff))
+
+#define KVM_REG_ARM_STD_BMAP			KVM_REG_ARM_FW_FEAT_BMAP_REG(0)
+
+enum {
+	KVM_REG_ARM_STD_BIT_TRNG_V1_0	= 0,
+#ifdef __KERNEL__
+	KVM_REG_ARM_STD_BMAP_BIT_COUNT,
+#endif
+};
+
+#define KVM_REG_ARM_STD_HYP_BMAP		KVM_REG_ARM_FW_FEAT_BMAP_REG(1)
+
+enum {
+	KVM_REG_ARM_STD_HYP_BIT_PV_TIME	= 0,
+#ifdef __KERNEL__
+	KVM_REG_ARM_STD_HYP_BMAP_BIT_COUNT,
+#endif
+};
+
+#define KVM_REG_ARM_VENDOR_HYP_BMAP		KVM_REG_ARM_FW_FEAT_BMAP_REG(2)
+
+enum {
+	KVM_REG_ARM_VENDOR_HYP_BIT_FUNC_FEAT	= 0,
+	KVM_REG_ARM_VENDOR_HYP_BIT_PTP		= 1,
+#ifdef __KERNEL__
+	KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_COUNT,
+#endif
+};
+
 /* Device Control API: ARM VGIC */
 #define KVM_DEV_ARM_VGIC_GRP_ADDR	0
 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS	1
-- 
GitLab


From 579d6c6d77a7b55d74db8a506d5fc0c77fb1a5e1 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Mon, 13 Jun 2022 18:47:14 -0700
Subject: [PATCH 1308/1731] perf bpf: 8 byte align bpil data

bpil data is accessed assuming 64-bit alignment resulting in undefined
behavior as the data is just byte aligned. With an -fsanitize=undefined
build the following errors are observed:

  $ sudo perf record -a sleep 1
  util/bpf-event.c:310:22: runtime error: load of misaligned address 0x55f61084520f for type '__u64', which requires 8 byte alignment
  0x55f61084520f: note: pointer points here
   a8 fe ff ff 3c  51 d3 c0 ff ff ff ff 04  84 d3 c0 ff ff ff ff d8  aa d3 c0 ff ff ff ff a4  c0 d3 c0
               ^
  util/bpf-event.c:311:20: runtime error: load of misaligned address 0x55f61084522f for type '__u32', which requires 4 byte alignment
  0x55f61084522f: note: pointer points here
   ff ff ff ff c7  17 00 00 f1 02 00 00 1f  04 00 00 58 04 00 00 00  00 00 00 0f 00 00 00 63  02 00 00
               ^
  util/bpf-event.c:198:33: runtime error: member access within misaligned address 0x55f61084523f for type 'const struct bpf_func_info', which requires 4 byte alignment
  0x55f61084523f: note: pointer points here
   58 04 00 00 00  00 00 00 0f 00 00 00 63  02 00 00 3b 00 00 00 ab  02 00 00 44 00 00 00 14  03 00 00

Correct this by rouding up the data sizes and aligning the pointers.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Andrii Nakryiko <andrii@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexei Starovoitov <ast@kernel.org>
Cc: Daniel Borkmann <daniel@iogearbox.net>
Cc: Dave Marchevsky <davemarchevsky@fb.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Fastabend <john.fastabend@gmail.com>
Cc: KP Singh <kpsingh@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Martin KaFai Lau <kafai@fb.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Quentin Monnet <quentin@isovalent.com>
Cc: Song Liu <songliubraving@fb.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Yonghong Song <yhs@fb.com>
Cc: bpf@vger.kernel.org
Cc: netdev@vger.kernel.org
Link: https://lore.kernel.org/r/20220614014714.1407239-1-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/bpf-utils.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/tools/perf/util/bpf-utils.c b/tools/perf/util/bpf-utils.c
index e271e05e51bce..80b1d2b3729ba 100644
--- a/tools/perf/util/bpf-utils.c
+++ b/tools/perf/util/bpf-utils.c
@@ -149,11 +149,10 @@ get_bpf_prog_info_linear(int fd, __u64 arrays)
 		count = bpf_prog_info_read_offset_u32(&info, desc->count_offset);
 		size  = bpf_prog_info_read_offset_u32(&info, desc->size_offset);
 
-		data_len += count * size;
+		data_len += roundup(count * size, sizeof(__u64));
 	}
 
 	/* step 3: allocate continuous memory */
-	data_len = roundup(data_len, sizeof(__u64));
 	info_linear = malloc(sizeof(struct perf_bpil) + data_len);
 	if (!info_linear)
 		return ERR_PTR(-ENOMEM);
@@ -180,7 +179,7 @@ get_bpf_prog_info_linear(int fd, __u64 arrays)
 		bpf_prog_info_set_offset_u64(&info_linear->info,
 					     desc->array_offset,
 					     ptr_to_u64(ptr));
-		ptr += count * size;
+		ptr += roundup(count * size, sizeof(__u64));
 	}
 
 	/* step 5: call syscall again to get required arrays */
-- 
GitLab


From 01cf387b1c7f60527c91627528370f463bcb84f3 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Wed, 22 Jun 2022 10:36:58 -0400
Subject: [PATCH 1309/1731] drm/amdgpu/display: reduce stack size in
 dml32_ModeSupportAndSystemConfigurationFull()

Move more stack variable in to dummy vars structure on the heap.

Fixes stack frame size errors:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In function 'dml32_ModeSupportAndSystemConfigurationFull':
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:3833:1: error: the frame size of 2720 bytes is larger than 2048 bytes [-Werror=frame-larger-than=]
 3833 | } // ModeSupportAndSystemConfigurationFull
      | ^

Fixes: dda4fb85e433 ("drm/amd/display: DML changes for DCN32/321")
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Rodrigo Siqueira Jordao <Rodrigo.Siqueira@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../dc/dml/dcn32/display_mode_vba_32.c        | 77 ++++++++-----------
 .../drm/amd/display/dc/dml/display_mode_vba.h |  3 +-
 2 files changed, 36 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 5bb6f4d8bf287..7d536c2f4477c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -1660,8 +1660,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 
 void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
 {
-	bool dummy_boolean[2];
-	unsigned int dummy_integer[1];
+	unsigned int dummy_integer[4];
 	bool MPCCombineMethodAsNeededForPStateChangeAndVoltage;
 	bool MPCCombineMethodAsPossible;
 	enum odm_combine_mode dummy_odm_mode[DC__NUM_DPP__MAX];
@@ -1973,10 +1972,10 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[5], /* Long            DETBufferSizeInKByte[]  */
 			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[6], /* Long            DETBufferSizeY[]  */
 			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[7], /* Long            DETBufferSizeC[]  */
-			&dummy_boolean[0], /* bool           *UnboundedRequestEnabled  */
-			&dummy_integer[0], /* Long           *CompressedBufferSizeInkByte  */
+			&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_boolean_array[0][0], /* bool           *UnboundedRequestEnabled  */
+			&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[0][0], /* Long           *CompressedBufferSizeInkByte  */
 			mode_lib->vba.SingleDPPViewportSizeSupportPerSurface,/* bool ViewportSizeSupportPerSurface[] */
-			&dummy_boolean[1]); /* bool           *ViewportSizeSupport */
+			&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_boolean_array[1][0]); /* bool           *ViewportSizeSupport */
 
 	MPCCombineMethodAsNeededForPStateChangeAndVoltage = false;
 	MPCCombineMethodAsPossible = false;
@@ -2506,7 +2505,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 	//
 	for (i = 0; i < (int) v->soc.num_states; ++i) {
 		for (j = 0; j <= 1; ++j) {
-			bool dummy_boolean_array[1][DC__NUM_DPP__MAX];
 			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
 				mode_lib->vba.RequiredDPPCLKThisState[k] = mode_lib->vba.RequiredDPPCLK[i][j][k];
 				mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k];
@@ -2570,7 +2568,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 					mode_lib->vba.DETBufferSizeCThisState,
 					&mode_lib->vba.UnboundedRequestEnabledThisState,
 					&mode_lib->vba.CompressedBufferSizeInkByteThisState,
-					dummy_boolean_array[0],
+					v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_boolean_array[0],
 					&mode_lib->vba.ViewportSizeSupport[i][j]);
 
 			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
@@ -2708,9 +2706,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 			}
 
 			{
-				bool dummy_boolean_array[2][DC__NUM_DPP__MAX];
-				unsigned int dummy_integer_array[22][DC__NUM_DPP__MAX];
-
 				dml32_CalculateVMRowAndSwath(
 						mode_lib->vba.NumberOfActiveSurfaces,
 						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters,
@@ -2733,32 +2728,32 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 						/* Output */
 						mode_lib->vba.PTEBufferSizeNotExceededPerState,
 						mode_lib->vba.DCCMetaBufferSizeNotExceededPerState,
-						dummy_integer_array[0],
-						dummy_integer_array[1],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[0],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[1],
 						mode_lib->vba.dpte_row_height,
 						mode_lib->vba.dpte_row_height_chroma,
-						dummy_integer_array[2],
-						dummy_integer_array[3],
-						dummy_integer_array[4],
-						dummy_integer_array[5],
-						dummy_integer_array[6],
-						dummy_integer_array[7],
-						dummy_integer_array[8],
-						dummy_integer_array[9],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[2],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[3],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[4],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[5],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[6],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[7],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[8],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[9],
 						mode_lib->vba.meta_row_height,
 						mode_lib->vba.meta_row_height_chroma,
-						dummy_integer_array[10],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[10],
 						mode_lib->vba.dpte_group_bytes,
-						dummy_integer_array[11],
-						dummy_integer_array[12],
-						dummy_integer_array[13],
-						dummy_integer_array[14],
-						dummy_integer_array[15],
-						dummy_integer_array[16],
-						dummy_integer_array[17],
-						dummy_integer_array[18],
-						dummy_integer_array[19],
-						dummy_integer_array[20],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[11],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[12],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[13],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[14],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[15],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[16],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[17],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[18],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[19],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[20],
 						mode_lib->vba.PrefetchLinesYThisState,
 						mode_lib->vba.PrefetchLinesCThisState,
 						mode_lib->vba.PrefillY,
@@ -2772,9 +2767,9 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 						mode_lib->vba.MetaRowBytesThisState,
 						mode_lib->vba.use_one_row_for_frame_this_state,
 						mode_lib->vba.use_one_row_for_frame_flip_this_state,
-						dummy_boolean_array[0], // Boolean UsesMALLForStaticScreen[]
-						dummy_boolean_array[1], // Boolean PTE_BUFFER_MODE[]
-						dummy_integer_array[21]); // Long BIGK_FRAGMENT_SIZE[]
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_boolean_array[0], // Boolean UsesMALLForStaticScreen[]
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_boolean_array[1], // Boolean PTE_BUFFER_MODE[]
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[21]); // Long BIGK_FRAGMENT_SIZE[]
 			}
 
 			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
@@ -3197,7 +3192,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 
 				for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
 					DmlPipe myPipe;
-					unsigned int dummy_integer;
 
 					mode_lib->vba.TWait = dml32_CalculateTWait(
 							mode_lib->vba.PrefetchModePerState[i][j],
@@ -3294,7 +3288,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[0],         // double *Tdmdl_vm
 							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[1],         // double *Tdmdl
 							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[2],         // double *TSetup
-							&dummy_integer,         							    // unsigned int   *VUpdateOffsetPix
+							&dummy_integer[0],         							    // unsigned int   *VUpdateOffsetPix
 							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[3],         // unsigned int   *VUpdateWidthPix
 							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[4]);        // unsigned int   *VReadyOffsetPix
 				}
@@ -3323,7 +3317,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 				}
 
 				{
-					double dummy_single[2];
 					dml32_CalculatePrefetchBandwithSupport(
 							mode_lib->vba.NumberOfActiveSurfaces,
 							mode_lib->vba.ReturnBWPerState[i][j],
@@ -3346,8 +3339,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 							mode_lib->vba.UrgentBurstFactorCursorPre,
 
 							/* output */
-							&dummy_single[0],   // Single  *PrefetchBandwidth
-							&dummy_single[1],   // Single  *FractionOfUrgentBandwidth
+							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[0],   // Single  *PrefetchBandwidth
+							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[1],   // Single  *FractionOfUrgentBandwidth
 							&mode_lib->vba.PrefetchSupported[i][j]);
 				}
 
@@ -3457,7 +3450,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 					}
 
 					{
-						double dummy_single[2];
 						dml32_CalculateImmediateFlipBandwithSupport(mode_lib->vba.NumberOfActiveSurfaces,
 								mode_lib->vba.ReturnBWPerState[i][j],
 								mode_lib->vba.ImmediateFlipRequirement,
@@ -3480,8 +3472,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 								mode_lib->vba.UrgentBurstFactorCursorPre,
 
 								/* output */
-								&dummy_single[0], //  Single  *TotalBandwidth
-								&dummy_single[1], //  Single  *FractionOfUrgentBandwidth
+								&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[0], //  Single  *TotalBandwidth
+								&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[1], //  Single  *FractionOfUrgentBandwidth
 								&mode_lib->vba.ImmediateFlipSupportedForState[i][j]); // Boolean *ImmediateFlipBandwidthSupport
 					}
 
@@ -3534,7 +3526,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SMNLatency = mode_lib->vba.SMNLatency;
 
 			{
-				unsigned int dummy_integer[4];
 				dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
 						mode_lib->vba.USRRetrainingRequiredFinal,
 						mode_lib->vba.UsesMALLForPStateChange,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 9ad49ad38814f..10ff536ef2a4e 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -196,7 +196,7 @@ struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCal
 };
 
 struct dml32_ModeSupportAndSystemConfigurationFull {
-	unsigned int dummy_integer_array[8][DC__NUM_DPP__MAX];
+	unsigned int dummy_integer_array[22][DC__NUM_DPP__MAX];
 	double dummy_double_array[2][DC__NUM_DPP__MAX];
 	DmlPipe SurfParameters[DC__NUM_DPP__MAX];
 	double dummy_single[5];
@@ -207,6 +207,7 @@ struct dml32_ModeSupportAndSystemConfigurationFull {
 	double DSTYAfterScaler[DC__NUM_DPP__MAX];
 	double DSTXAfterScaler[DC__NUM_DPP__MAX];
 	double MaxTotalVActiveRDBandwidth;
+	bool dummy_boolean_array[2][DC__NUM_DPP__MAX];
 };
 
 struct dummy_vars {
-- 
GitLab


From d7f0c8aff01340c2bed48f1e712a7f17c31b3db9 Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Thu, 3 Mar 2022 14:39:22 +0800
Subject: [PATCH 1310/1731] drm/amdgpu: update GFX11 cs settings

Update GFX11 cs related settings.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/clearstate_gfx11.h | 307 +++++++++---------
 1 file changed, 158 insertions(+), 149 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/clearstate_gfx11.h b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx11.h
index f3852b59b1d67..a8b29d33c4648 100644
--- a/drivers/gpu/drm/amd/amdgpu/clearstate_gfx11.h
+++ b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx11.h
@@ -39,7 +39,7 @@ static const unsigned int gfx11_SECT_CONTEXT_def_1[] =
     0x00000000, // DB_DEPTH_CLEAR
     0x00000000, // PA_SC_SCREEN_SCISSOR_TL
     0x40004000, // PA_SC_SCREEN_SCISSOR_BR
-    0x00000000, // DB_DFSM_CONTROL
+    0, // HOLE
     0x00000000, // DB_RESERVED_REG_2
     0x00000000, // DB_Z_INFO
     0x00000000, // DB_STENCIL_INFO
@@ -50,7 +50,7 @@ static const unsigned int gfx11_SECT_CONTEXT_def_1[] =
     0x00000000, // DB_RESERVED_REG_1
     0x00000000, // DB_RESERVED_REG_3
     0x00000000, // DB_SPI_VRS_CENTER_LOCATION
-    0x00000000, // DB_VRS_OVERRIDE_CNTL
+    0, // HOLE
     0x00000000, // DB_Z_READ_BASE_HI
     0x00000000, // DB_STENCIL_READ_BASE_HI
     0x00000000, // DB_Z_WRITE_BASE_HI
@@ -270,29 +270,29 @@ static const unsigned int gfx11_SECT_CONTEXT_def_2[] =
     0x00000000, // PA_SC_FSR_EN
     0x00000000, // PA_SC_FSR_FBW_RECURSIONS_X
     0x00000000, // PA_SC_FSR_FBW_RECURSIONS_Y
-    0x00000000, // PA_SC_VRS_RATE_FEEDBACK_VIEW
+    0, // HOLE
     0x00000000, // PA_SC_VRS_OVERRIDE_CNTL
     0x00000000, // PA_SC_VRS_RATE_FEEDBACK_BASE
     0x00000000, // PA_SC_VRS_RATE_FEEDBACK_BASE_EXT
     0x00000000, // PA_SC_VRS_RATE_FEEDBACK_SIZE_XY
     0x00000000, // PA_SC_BINNER_OUTPUT_TIMEOUT_CNTL
-    0, // HOLE
+    0x00000000, // PA_SC_VRS_RATE_CACHE_CNTL
     0, // HOLE
     0, // HOLE
     0x00000000, // PA_SC_VRS_RATE_BASE
     0x00000000, // PA_SC_VRS_RATE_BASE_EXT
     0x00000000, // PA_SC_VRS_RATE_SIZE_XY
-    0x00000000, // PA_SC_VRS_RATE_VIEW
-    0xffffffff, // VGT_MAX_VTX_INDX
-    0x00000000, // VGT_MIN_VTX_INDX
-    0x00000000, // VGT_INDX_OFFSET
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // VGT_MULTI_PRIM_IB_RESET_INDX
     0x00550055, // CB_RMI_GL2_CACHE_CONTROL
     0x00000000, // CB_BLEND_RED
     0x00000000, // CB_BLEND_GREEN
     0x00000000, // CB_BLEND_BLUE
     0x00000000, // CB_BLEND_ALPHA
-    0x00000000, // CB_DCC_CONTROL
+    0x00000000, // CB_FDCC_CONTROL
     0x00000000, // CB_COVERAGE_OUT_CONTROL
     0x00000000, // DB_STENCIL_CONTROL
     0x01000000, // DB_STENCILREFMASK
@@ -470,8 +470,8 @@ static const unsigned int gfx11_SECT_CONTEXT_def_2[] =
     0x00000000, // SPI_BARYC_CNTL
     0, // HOLE
     0x00000000, // SPI_TMPRING_SIZE
-    0, // HOLE
-    0, // HOLE
+    0x00000000, // SPI_GFX_SCRATCH_BASE_LO
+    0x00000000, // SPI_GFX_SCRATCH_BASE_HI
     0, // HOLE
     0, // HOLE
     0, // HOLE
@@ -545,7 +545,7 @@ static const unsigned int gfx11_SECT_CONTEXT_def_4[] =
     0x00000000, // PA_STEREO_CNTL
     0x00000000, // PA_STATE_STEREO_X
     0x00000000, // PA_CL_VRS_CNTL
-    0x00000000, // PA_SIDEBAND_REQUEST_DELAYS
+    0, // HOLE
     0, // HOLE
     0, // HOLE
     0, // HOLE
@@ -658,30 +658,30 @@ static const unsigned int gfx11_SECT_CONTEXT_def_4[] =
     0x00000000, // PA_SU_POINT_MINMAX
     0x00000000, // PA_SU_LINE_CNTL
     0x00000000, // PA_SC_LINE_STIPPLE
-    0x00000000, // VGT_OUTPUT_PATH_CNTL
-    0x00000000, // VGT_HOS_CNTL
+    0, // HOLE
+    0, // HOLE
     0x00000000, // VGT_HOS_MAX_TESS_LEVEL
     0x00000000, // VGT_HOS_MIN_TESS_LEVEL
-    0x00000000, // VGT_HOS_REUSE_DEPTH
-    0x00000000, // VGT_GROUP_PRIM_TYPE
-    0x00000000, // VGT_GROUP_FIRST_DECR
-    0x00000000, // VGT_GROUP_DECR
-    0x00000000, // VGT_GROUP_VECT_0_CNTL
-    0x00000000, // VGT_GROUP_VECT_1_CNTL
-    0x00000000, // VGT_GROUP_VECT_0_FMT_CNTL
-    0x00000000, // VGT_GROUP_VECT_1_FMT_CNTL
-    0x00000000, // VGT_GS_MODE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // VGT_GS_ONCHIP_CNTL
     0x00000000, // PA_SC_MODE_CNTL_0
     0x00000000, // PA_SC_MODE_CNTL_1
     0x00000000, // VGT_ENHANCE
-    0x00000100, // VGT_GS_PER_ES
-    0x00000080, // VGT_ES_PER_GS
-    0x00000002, // VGT_GS_PER_VS
-    0x00000000, // VGT_GSVS_RING_OFFSET_1
-    0x00000000, // VGT_GSVS_RING_OFFSET_2
-    0x00000000, // VGT_GSVS_RING_OFFSET_3
-    0x00000000, // VGT_GS_OUT_PRIM_TYPE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // IA_ENHANCE
 };
 static const unsigned int gfx11_SECT_CONTEXT_def_5[] =
@@ -695,37 +695,36 @@ static const unsigned int gfx11_SECT_CONTEXT_def_6[] =
 };
 static const unsigned int gfx11_SECT_CONTEXT_def_7[] =
 {
-    0x00000000, // VGT_MULTI_PRIM_IB_RESET_EN
     0x00000000, // VGT_DRAW_PAYLOAD_CNTL
     0, // HOLE
-    0x00000000, // VGT_INSTANCE_STEP_RATE_0
-    0x00000000, // VGT_INSTANCE_STEP_RATE_1
-    0x000000ff, // IA_MULTI_VGT_PARAM
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // VGT_ESGS_RING_ITEMSIZE
-    0x00000000, // VGT_GSVS_RING_ITEMSIZE
+    0, // HOLE
     0x00000000, // VGT_REUSE_OFF
-    0x00000000, // VGT_VTX_CNT_EN
+    0, // HOLE
     0x00000000, // DB_HTILE_SURFACE
     0x00000000, // DB_SRESULTS_COMPARE_STATE0
     0x00000000, // DB_SRESULTS_COMPARE_STATE1
     0x00000000, // DB_PRELOAD_CONTROL
     0, // HOLE
-    0x00000000, // VGT_STRMOUT_BUFFER_SIZE_0
-    0x00000000, // VGT_STRMOUT_VTX_STRIDE_0
     0, // HOLE
-    0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_0
-    0x00000000, // VGT_STRMOUT_BUFFER_SIZE_1
-    0x00000000, // VGT_STRMOUT_VTX_STRIDE_1
     0, // HOLE
-    0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_1
-    0x00000000, // VGT_STRMOUT_BUFFER_SIZE_2
-    0x00000000, // VGT_STRMOUT_VTX_STRIDE_2
     0, // HOLE
-    0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_2
-    0x00000000, // VGT_STRMOUT_BUFFER_SIZE_3
-    0x00000000, // VGT_STRMOUT_VTX_STRIDE_3
     0, // HOLE
-    0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_3
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
     0, // HOLE
     0, // HOLE
     0, // HOLE
@@ -745,10 +744,10 @@ static const unsigned int gfx11_SECT_CONTEXT_def_7[] =
     0x00000000, // VGT_TESS_DISTRIBUTION
     0x00000000, // VGT_SHADER_STAGES_EN
     0x00000000, // VGT_LS_HS_CONFIG
-    0x00000000, // VGT_GS_VERT_ITEMSIZE
-    0x00000000, // VGT_GS_VERT_ITEMSIZE_1
-    0x00000000, // VGT_GS_VERT_ITEMSIZE_2
-    0x00000000, // VGT_GS_VERT_ITEMSIZE_3
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // VGT_TF_PARAM
     0x00000000, // DB_ALPHA_TO_MASK
     0, // HOLE
@@ -759,11 +758,22 @@ static const unsigned int gfx11_SECT_CONTEXT_def_7[] =
     0x00000000, // PA_SU_POLY_OFFSET_BACK_SCALE
     0x00000000, // PA_SU_POLY_OFFSET_BACK_OFFSET
     0x00000000, // VGT_GS_INSTANCE_CNT
-    0x00000000, // VGT_STRMOUT_CONFIG
-    0x00000000, // VGT_STRMOUT_BUFFER_CONFIG
-};
-static const unsigned int gfx11_SECT_CONTEXT_def_8[] =
-{
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // PA_SC_CENTROID_PRIORITY_0
     0x00000000, // PA_SC_CENTROID_PRIORITY_1
     0x00001000, // PA_SC_LINE_CNTL
@@ -797,126 +807,126 @@ static const unsigned int gfx11_SECT_CONTEXT_def_8[] =
     0x00100000, // PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
     0x00000000, // PA_SC_NGG_MODE_CNTL
     0x00000000, // PA_SC_BINNER_CNTL_2
-    0x0000001e, // VGT_VERTEX_REUSE_BLOCK_CNTL
-    0x00000020, // VGT_OUT_DEALLOC_CNTL
+    0, // HOLE
+    0, // HOLE
     0x00000000, // CB_COLOR0_BASE
-    0x00000000, // CB_COLOR0_PITCH
-    0x00000000, // CB_COLOR0_SLICE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // CB_COLOR0_VIEW
     0x00000000, // CB_COLOR0_INFO
     0x00000000, // CB_COLOR0_ATTRIB
-    0x00000000, // CB_COLOR0_DCC_CONTROL
-    0x00000000, // CB_COLOR0_CMASK
-    0x00000000, // CB_COLOR0_CMASK_SLICE
-    0x00000000, // CB_COLOR0_FMASK
-    0x00000000, // CB_COLOR0_FMASK_SLICE
-    0x00000000, // CB_COLOR0_CLEAR_WORD0
-    0x00000000, // CB_COLOR0_CLEAR_WORD1
+    0x00000000, // CB_COLOR0_FDCC_CONTROL
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // CB_COLOR0_DCC_BASE
     0, // HOLE
     0x00000000, // CB_COLOR1_BASE
-    0x00000000, // CB_COLOR1_PITCH
-    0x00000000, // CB_COLOR1_SLICE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // CB_COLOR1_VIEW
     0x00000000, // CB_COLOR1_INFO
     0x00000000, // CB_COLOR1_ATTRIB
-    0x00000000, // CB_COLOR1_DCC_CONTROL
-    0x00000000, // CB_COLOR1_CMASK
-    0x00000000, // CB_COLOR1_CMASK_SLICE
-    0x00000000, // CB_COLOR1_FMASK
-    0x00000000, // CB_COLOR1_FMASK_SLICE
-    0x00000000, // CB_COLOR1_CLEAR_WORD0
-    0x00000000, // CB_COLOR1_CLEAR_WORD1
+    0x00000000, // CB_COLOR1_FDCC_CONTROL
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // CB_COLOR1_DCC_BASE
     0, // HOLE
     0x00000000, // CB_COLOR2_BASE
-    0x00000000, // CB_COLOR2_PITCH
-    0x00000000, // CB_COLOR2_SLICE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // CB_COLOR2_VIEW
     0x00000000, // CB_COLOR2_INFO
     0x00000000, // CB_COLOR2_ATTRIB
-    0x00000000, // CB_COLOR2_DCC_CONTROL
-    0x00000000, // CB_COLOR2_CMASK
-    0x00000000, // CB_COLOR2_CMASK_SLICE
-    0x00000000, // CB_COLOR2_FMASK
-    0x00000000, // CB_COLOR2_FMASK_SLICE
-    0x00000000, // CB_COLOR2_CLEAR_WORD0
-    0x00000000, // CB_COLOR2_CLEAR_WORD1
+    0x00000000, // CB_COLOR2_FDCC_CONTROL
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // CB_COLOR2_DCC_BASE
     0, // HOLE
     0x00000000, // CB_COLOR3_BASE
-    0x00000000, // CB_COLOR3_PITCH
-    0x00000000, // CB_COLOR3_SLICE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // CB_COLOR3_VIEW
     0x00000000, // CB_COLOR3_INFO
     0x00000000, // CB_COLOR3_ATTRIB
-    0x00000000, // CB_COLOR3_DCC_CONTROL
-    0x00000000, // CB_COLOR3_CMASK
-    0x00000000, // CB_COLOR3_CMASK_SLICE
-    0x00000000, // CB_COLOR3_FMASK
-    0x00000000, // CB_COLOR3_FMASK_SLICE
-    0x00000000, // CB_COLOR3_CLEAR_WORD0
-    0x00000000, // CB_COLOR3_CLEAR_WORD1
+    0x00000000, // CB_COLOR3_FDCC_CONTROL
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // CB_COLOR3_DCC_BASE
     0, // HOLE
     0x00000000, // CB_COLOR4_BASE
-    0x00000000, // CB_COLOR4_PITCH
-    0x00000000, // CB_COLOR4_SLICE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // CB_COLOR4_VIEW
     0x00000000, // CB_COLOR4_INFO
     0x00000000, // CB_COLOR4_ATTRIB
-    0x00000000, // CB_COLOR4_DCC_CONTROL
-    0x00000000, // CB_COLOR4_CMASK
-    0x00000000, // CB_COLOR4_CMASK_SLICE
-    0x00000000, // CB_COLOR4_FMASK
-    0x00000000, // CB_COLOR4_FMASK_SLICE
-    0x00000000, // CB_COLOR4_CLEAR_WORD0
-    0x00000000, // CB_COLOR4_CLEAR_WORD1
+    0x00000000, // CB_COLOR4_FDCC_CONTROL
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // CB_COLOR4_DCC_BASE
     0, // HOLE
     0x00000000, // CB_COLOR5_BASE
-    0x00000000, // CB_COLOR5_PITCH
-    0x00000000, // CB_COLOR5_SLICE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // CB_COLOR5_VIEW
     0x00000000, // CB_COLOR5_INFO
     0x00000000, // CB_COLOR5_ATTRIB
-    0x00000000, // CB_COLOR5_DCC_CONTROL
-    0x00000000, // CB_COLOR5_CMASK
-    0x00000000, // CB_COLOR5_CMASK_SLICE
-    0x00000000, // CB_COLOR5_FMASK
-    0x00000000, // CB_COLOR5_FMASK_SLICE
-    0x00000000, // CB_COLOR5_CLEAR_WORD0
-    0x00000000, // CB_COLOR5_CLEAR_WORD1
+    0x00000000, // CB_COLOR5_FDCC_CONTROL
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // CB_COLOR5_DCC_BASE
     0, // HOLE
     0x00000000, // CB_COLOR6_BASE
-    0x00000000, // CB_COLOR6_PITCH
-    0x00000000, // CB_COLOR6_SLICE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // CB_COLOR6_VIEW
     0x00000000, // CB_COLOR6_INFO
     0x00000000, // CB_COLOR6_ATTRIB
-    0x00000000, // CB_COLOR6_DCC_CONTROL
-    0x00000000, // CB_COLOR6_CMASK
-    0x00000000, // CB_COLOR6_CMASK_SLICE
-    0x00000000, // CB_COLOR6_FMASK
-    0x00000000, // CB_COLOR6_FMASK_SLICE
-    0x00000000, // CB_COLOR6_CLEAR_WORD0
-    0x00000000, // CB_COLOR6_CLEAR_WORD1
+    0x00000000, // CB_COLOR6_FDCC_CONTROL
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // CB_COLOR6_DCC_BASE
     0, // HOLE
     0x00000000, // CB_COLOR7_BASE
-    0x00000000, // CB_COLOR7_PITCH
-    0x00000000, // CB_COLOR7_SLICE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // CB_COLOR7_VIEW
     0x00000000, // CB_COLOR7_INFO
     0x00000000, // CB_COLOR7_ATTRIB
-    0x00000000, // CB_COLOR7_DCC_CONTROL
-    0x00000000, // CB_COLOR7_CMASK
-    0x00000000, // CB_COLOR7_CMASK_SLICE
-    0x00000000, // CB_COLOR7_FMASK
-    0x00000000, // CB_COLOR7_FMASK_SLICE
-    0x00000000, // CB_COLOR7_CLEAR_WORD0
-    0x00000000, // CB_COLOR7_CLEAR_WORD1
+    0x00000000, // CB_COLOR7_FDCC_CONTROL
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // CB_COLOR7_DCC_BASE
     0, // HOLE
     0x00000000, // CB_COLOR0_BASE_EXT
@@ -927,22 +937,22 @@ static const unsigned int gfx11_SECT_CONTEXT_def_8[] =
     0x00000000, // CB_COLOR5_BASE_EXT
     0x00000000, // CB_COLOR6_BASE_EXT
     0x00000000, // CB_COLOR7_BASE_EXT
-    0x00000000, // CB_COLOR0_CMASK_BASE_EXT
-    0x00000000, // CB_COLOR1_CMASK_BASE_EXT
-    0x00000000, // CB_COLOR2_CMASK_BASE_EXT
-    0x00000000, // CB_COLOR3_CMASK_BASE_EXT
-    0x00000000, // CB_COLOR4_CMASK_BASE_EXT
-    0x00000000, // CB_COLOR5_CMASK_BASE_EXT
-    0x00000000, // CB_COLOR6_CMASK_BASE_EXT
-    0x00000000, // CB_COLOR7_CMASK_BASE_EXT
-    0x00000000, // CB_COLOR0_FMASK_BASE_EXT
-    0x00000000, // CB_COLOR1_FMASK_BASE_EXT
-    0x00000000, // CB_COLOR2_FMASK_BASE_EXT
-    0x00000000, // CB_COLOR3_FMASK_BASE_EXT
-    0x00000000, // CB_COLOR4_FMASK_BASE_EXT
-    0x00000000, // CB_COLOR5_FMASK_BASE_EXT
-    0x00000000, // CB_COLOR6_FMASK_BASE_EXT
-    0x00000000, // CB_COLOR7_FMASK_BASE_EXT
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
     0x00000000, // CB_COLOR0_DCC_BASE_EXT
     0x00000000, // CB_COLOR1_DCC_BASE_EXT
     0x00000000, // CB_COLOR2_DCC_BASE_EXT
@@ -976,8 +986,7 @@ static const struct cs_extent_def gfx11_SECT_CONTEXT_defs[] =
     {gfx11_SECT_CONTEXT_def_4, 0x0000a1ff, 158 },
     {gfx11_SECT_CONTEXT_def_5, 0x0000a2a0, 2 },
     {gfx11_SECT_CONTEXT_def_6, 0x0000a2a3, 1 },
-    {gfx11_SECT_CONTEXT_def_7, 0x0000a2a5, 66 },
-    {gfx11_SECT_CONTEXT_def_8, 0x0000a2f5, 203 },
+    {gfx11_SECT_CONTEXT_def_7, 0x0000a2a6, 282 },
     { 0, 0, 0 }
 };
 static const struct cs_section_def gfx11_cs_data[] = {
-- 
GitLab


From 1d3182006cf6eea26d0cd752f8042c3cae43139b Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Tue, 14 Jun 2022 15:21:48 +0800
Subject: [PATCH 1311/1731] drm/amd/pm: enable VR0 HOT support for SMU 13.0.0

Enable VR0 Hot support for SMU 13.0.0.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 6fb2b072a730e..ce2fa04e3926a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -308,6 +308,8 @@ smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu,
 
 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_UCLK_BIT);
 
+	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT);
+
 	return 0;
 }
 
-- 
GitLab


From ca0cb8959f7b84742c3dd612f5b044788cddfcc7 Mon Sep 17 00:00:00 2001
From: Chandan Vurdigere Nataraj <chandan.vurdigerenataraj@amd.com>
Date: Thu, 23 Jun 2022 12:48:49 +0530
Subject: [PATCH 1312/1731] drm/amd/display : Log DP link training failure
 reason

[Why]
Existing logs doesn't print DP LT failure reason

[How]
Update the existing log with DP LT failure reason

Signed-off-by: Chandan Vurdigere Nataraj <chandan.vurdigerenataraj@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 4027f439a5a40..c8355acd36722 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2786,9 +2786,9 @@ bool perform_link_training_with_retries(
 				break;
 		}
 
-		DC_LOG_WARNING("%s: Link(%d) training attempt %u of %d failed @ rate(%d) x lane(%d)\n",
+		DC_LOG_WARNING("%s: Link(%d) training attempt %u of %d failed @ rate(%d) x lane(%d) : fail reason:(%d)\n",
 			__func__, link->link_index, (unsigned int)j + 1, attempts, cur_link_settings.link_rate,
-			cur_link_settings.lane_count);
+			cur_link_settings.lane_count, status);
 
 		dp_disable_link_phy(link, &pipe_ctx->link_res, signal);
 
-- 
GitLab


From fe4e9ff9873758ad07e6f7b3088ae3a9dd3ff1b3 Mon Sep 17 00:00:00 2001
From: Jack Xiao <Jack.Xiao@amd.com>
Date: Thu, 2 Jun 2022 16:37:56 +0800
Subject: [PATCH 1313/1731] drm/amdgpu: add mc wptr addr support for mes

MES requires mc wptr address for usermode queues.
Export bo gart address for mc wptr address.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c               | 10 ++++++++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h               |  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h           |  1 +
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c                |  8 +++++++-
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c |  6 +++---
 5 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 521e35d93d677..0c9cb493a85c3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -675,6 +675,7 @@ int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id,
 	queue_input.doorbell_offset = qprops->doorbell_off;
 	queue_input.mqd_addr = queue->mqd_gpu_addr;
 	queue_input.wptr_addr = qprops->wptr_gpu_addr;
+	queue_input.wptr_mc_addr = qprops->wptr_mc_addr;
 	queue_input.queue_type = qprops->queue_type;
 	queue_input.paging = qprops->paging;
 	queue_input.is_kfd_process = 0;
@@ -802,6 +803,8 @@ amdgpu_mes_ring_to_queue_props(struct amdgpu_device *adev,
 	props->hqd_base_gpu_addr = ring->gpu_addr;
 	props->rptr_gpu_addr = ring->rptr_gpu_addr;
 	props->wptr_gpu_addr = ring->wptr_gpu_addr;
+	props->wptr_mc_addr =
+		ring->mes_ctx->meta_data_mc_addr + ring->wptr_offs;
 	props->queue_size = ring->ring_size;
 	props->eop_gpu_addr = ring->eop_gpu_addr;
 	props->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL;
@@ -962,7 +965,8 @@ int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev,
 	r = amdgpu_bo_create_kernel(adev,
 			    sizeof(struct amdgpu_mes_ctx_meta_data),
 			    PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
-			    &ctx_data->meta_data_obj, NULL,
+			    &ctx_data->meta_data_obj,
+			    &ctx_data->meta_data_mc_addr,
 			    &ctx_data->meta_data_ptr);
 	if (!ctx_data->meta_data_obj)
 		return -ENOMEM;
@@ -976,7 +980,9 @@ int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev,
 void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data)
 {
 	if (ctx_data->meta_data_obj)
-		amdgpu_bo_free_kernel(&ctx_data->meta_data_obj, NULL, NULL);
+		amdgpu_bo_free_kernel(&ctx_data->meta_data_obj,
+				      &ctx_data->meta_data_mc_addr,
+				      &ctx_data->meta_data_ptr);
 }
 
 int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index 85ebb5fdba0b5..074418c63e4b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -176,6 +176,7 @@ struct amdgpu_mes_queue_properties {
 	uint64_t                hqd_base_gpu_addr;
 	uint64_t                rptr_gpu_addr;
 	uint64_t                wptr_gpu_addr;
+	uint64_t                wptr_mc_addr;
 	uint32_t                queue_size;
 	uint64_t                eop_gpu_addr;
 	uint32_t                hqd_pipe_priority;
@@ -208,6 +209,7 @@ struct mes_add_queue_input {
 	uint32_t	doorbell_offset;
 	uint64_t	mqd_addr;
 	uint64_t	wptr_addr;
+	uint64_t	wptr_mc_addr;
 	uint32_t	queue_type;
 	uint32_t	paging;
 	uint32_t        gws_base;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h
index c000f656aae5e..912a5be2ece6c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h
@@ -107,6 +107,7 @@ struct amdgpu_mes_ctx_meta_data {
 struct amdgpu_mes_ctx_data {
 	struct amdgpu_bo	*meta_data_obj;
 	uint64_t                meta_data_gpu_addr;
+	uint64_t                meta_data_mc_addr;
 	struct amdgpu_bo_va	*meta_data_va;
 	void                    *meta_data_ptr;
 	uint32_t                gang_ids[AMDGPU_HW_IP_DMA+1];
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 7dfc6ea21397b..89b99dc827a6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -156,7 +156,13 @@ static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes,
 		input->gang_global_priority_level;
 	mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
 	mes_add_queue_pkt.mqd_addr = input->mqd_addr;
-	mes_add_queue_pkt.wptr_addr = input->wptr_addr;
+
+	if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >>
+			AMDGPU_MES_API_VERSION_SHIFT) >= 2)
+		mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr;
+	else
+		mes_add_queue_pkt.wptr_addr = input->wptr_addr;
+
 	mes_add_queue_pkt.queue_type =
 		convert_to_mes_queue_type(input->queue_type);
 	mes_add_queue_pkt.paging = input->paging;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 74a1f8a6f53f3..21e451acfa598 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -197,12 +197,12 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q,
 					AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
 	queue_input.doorbell_offset = q->properties.doorbell_off;
 	queue_input.mqd_addr = q->gart_mqd_addr;
+	queue_input.wptr_addr = (uint64_t)q->properties.write_ptr;
 
 	if (q->wptr_bo) {
 		wptr_addr_off = (uint64_t)q->properties.write_ptr - (uint64_t)q->wptr_bo->kfd_bo->va;
-		queue_input.wptr_addr = ((uint64_t)q->wptr_bo->tbo.resource->start << PAGE_SHIFT) + wptr_addr_off;
-	} else
-		queue_input.wptr_addr = (uint64_t)q->properties.write_ptr;
+		queue_input.wptr_mc_addr = ((uint64_t)q->wptr_bo->tbo.resource->start << PAGE_SHIFT) + wptr_addr_off;
+	}
 
 	queue_input.is_kfd_process = 1;
 
-- 
GitLab


From 5c4904ac34b76eb58abc15a52603ee59bf8be85d Mon Sep 17 00:00:00 2001
From: Leslie Shi <Yuliang.Shi@amd.com>
Date: Mon, 27 Jun 2022 12:52:17 +0800
Subject: [PATCH 1314/1731] drm/amdgpu: Remove useless
 amdgpu_display_freesync_ioctl() declaration

Signed-off-by: Leslie Shi <Yuliang.Shi@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
index 7b6d83e2b13ca..560352f7c3177 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
@@ -35,8 +35,6 @@
 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
 
-int amdgpu_display_freesync_ioctl(struct drm_device *dev, void *data,
-				  struct drm_file *filp);
 void amdgpu_display_update_priority(struct amdgpu_device *adev);
 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
 					  uint64_t bo_flags);
-- 
GitLab


From dd70748eda3f63217d5284f48651239a9721245e Mon Sep 17 00:00:00 2001
From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Date: Mon, 20 Jun 2022 13:08:52 -0400
Subject: [PATCH 1315/1731] drm/amdgpu: Add put fence in
 amdgpu_fence_driver_clear_job_fences
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This function should drop the fence refcount when it extracts the
fence from the fence array, just as it's done in amdgpu_fence_process.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 957437a5558c1..a9ae3beaa1d3d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -595,8 +595,10 @@ void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring)
 	for (i = 0; i <= ring->fence_drv.num_fences_mask; i++) {
 		ptr = &ring->fence_drv.fences[i];
 		old = rcu_dereference_protected(*ptr, 1);
-		if (old && old->ops == &amdgpu_job_fence_ops)
+		if (old && old->ops == &amdgpu_job_fence_ops) {
 			RCU_INIT_POINTER(*ptr, NULL);
+			dma_fence_put(old);
+		}
 	}
 }
 
-- 
GitLab


From 9e225fb9e636b31b97e9d35324c2f9e43ee0aab4 Mon Sep 17 00:00:00 2001
From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Date: Sat, 18 Jun 2022 00:28:50 -0400
Subject: [PATCH 1316/1731] drm/amdgpu: Prevent race between late signaled
 fences and GPU reset.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Problem:
After we start handling timed out jobs we assume there fences won't be
signaled but we cannot be sure and sometimes they fire late. We need
to prevent concurrent accesses to fence array from
amdgpu_fence_driver_clear_job_fences during GPU reset and amdgpu_fence_process
from a late EOP interrupt.

Fix:
Before accessing fence array in GPU disable EOP interrupt and flush
all pending interrupt handlers for amdgpu device's interrupt line.

v2: Switch from irq_get/put to full enable/disable_irq for amdgpu

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  4 ++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c  | 18 ++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h   |  1 +
 3 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index f2a4c268ac72b..9d2395ab4f70b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4606,6 +4606,8 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
 		amdgpu_virt_fini_data_exchange(adev);
 	}
 
+	amdgpu_fence_driver_isr_toggle(adev, true);
+
 	/* block all schedulers and reset given job's ring */
 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 		struct amdgpu_ring *ring = adev->rings[i];
@@ -4621,6 +4623,8 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
 		amdgpu_fence_driver_force_completion(ring);
 	}
 
+	amdgpu_fence_driver_isr_toggle(adev, false);
+
 	if (job && job->vm)
 		drm_sched_increase_karma(&job->base);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index a9ae3beaa1d3d..c1d04ea3c67f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -532,6 +532,24 @@ void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev)
 	}
 }
 
+/* Will either stop and flush handlers for amdgpu interrupt or reanble it */
+void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop)
+{
+	int i;
+
+	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
+		struct amdgpu_ring *ring = adev->rings[i];
+
+		if (!ring || !ring->fence_drv.initialized || !ring->fence_drv.irq_src)
+			continue;
+
+		if (stop)
+			disable_irq(adev->irq.irq);
+		else
+			enable_irq(adev->irq.irq);
+	}
+}
+
 void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev)
 {
 	unsigned int i, j;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 7d89a52091c0e..82c178a9033af 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -143,6 +143,7 @@ signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
 				      uint32_t wait_seq,
 				      signed long timeout);
 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
+void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop);
 
 /*
  * Rings.
-- 
GitLab


From 45ecaea738830b9d521c93520c8f201359dcbd95 Mon Sep 17 00:00:00 2001
From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Date: Mon, 20 Jun 2022 16:39:47 -0400
Subject: [PATCH 1317/1731] drm/sched: Partial revert of 'drm/sched: Keep
 s_fence->parent pointer'
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Problem:
This patch caused negative refcount as described in [1] because
for that case parent fence did not signal by the time of drm_sched_stop and hence
kept in pending list the assumption was they will not signal and
so fence was put to account for the s_fence->parent refcount but for
amdgpu which has embedded HW fence (always same parent fence)
drm_sched_fence_release_scheduled was always called and would
still drop the count for parent fence once more. For jobs that
never signaled this imbalance was masked by refcount bug in
amdgpu_fence_driver_clear_job_fences that would not drop
refcount on the fences that were removed from fence drive
fences array (against prevois insertion into the array in
get in amdgpu_fence_emit).

Fix:
Revert this patch and by setting s_job->s_fence->parent to NULL
as before prevent the extra refcount drop in amdgpu when
drm_sched_fence_release_scheduled is called on job release.

Also - align behaviour in drm_sched_resubmit_jobs_ext with that of
drm_sched_main when submitting jobs - take a refcount for the
new parent fence pointer and drop refcount for original kref_init
for new HW fence creation (or fake new HW fence in amdgpu - see next patch).

[1] - https://lore.kernel.org/all/731b7ff1-3cc9-e314-df2a-7c51b76d4db0@amd.com/t/#r00c728fcc069b1276642c325bfa9d82bf8fa21a3

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Tested-by: Yiqing Yao <yiqing.yao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/scheduler/sched_main.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c
index 76fd2904c7c63..68317d3a7a277 100644
--- a/drivers/gpu/drm/scheduler/sched_main.c
+++ b/drivers/gpu/drm/scheduler/sched_main.c
@@ -419,6 +419,8 @@ void drm_sched_stop(struct drm_gpu_scheduler *sched, struct drm_sched_job *bad)
 		if (s_job->s_fence->parent &&
 		    dma_fence_remove_callback(s_job->s_fence->parent,
 					      &s_job->cb)) {
+			dma_fence_put(s_job->s_fence->parent);
+			s_job->s_fence->parent = NULL;
 			atomic_dec(&sched->hw_rq_count);
 		} else {
 			/*
@@ -548,7 +550,6 @@ void drm_sched_resubmit_jobs_ext(struct drm_gpu_scheduler *sched, int max)
 		if (found_guilty && s_job->s_fence->scheduled.context == guilty_context)
 			dma_fence_set_error(&s_fence->finished, -ECANCELED);
 
-		dma_fence_put(s_job->s_fence->parent);
 		fence = sched->ops->run_job(s_job);
 		i++;
 
@@ -558,7 +559,11 @@ void drm_sched_resubmit_jobs_ext(struct drm_gpu_scheduler *sched, int max)
 
 			s_job->s_fence->parent = NULL;
 		} else {
-			s_job->s_fence->parent = fence;
+
+			s_job->s_fence->parent = dma_fence_get(fence);
+
+			/* Drop for orignal kref_init */
+			dma_fence_put(fence);
 		}
 	}
 }
@@ -955,6 +960,9 @@ static int drm_sched_main(void *param)
 
 		if (!IS_ERR_OR_NULL(fence)) {
 			s_fence->parent = dma_fence_get(fence);
+			/* Drop for original kref_init of the fence */
+			dma_fence_put(fence);
+
 			r = dma_fence_add_callback(fence, &sched_job->cb,
 						   drm_sched_job_done_cb);
 			if (r == -ENOENT)
@@ -962,7 +970,6 @@ static int drm_sched_main(void *param)
 			else if (r)
 				DRM_DEV_ERROR(sched->dev, "fence add callback failed (%d)\n",
 					  r);
-			dma_fence_put(fence);
 		} else {
 			if (IS_ERR(fence))
 				dma_fence_set_error(&s_fence->finished, PTR_ERR(fence));
-- 
GitLab


From 9ae55f030dc523fc4dc6069557e4a887ea815453 Mon Sep 17 00:00:00 2001
From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Date: Mon, 20 Jun 2022 17:33:55 -0400
Subject: [PATCH 1318/1731] drm/amdgpu: Follow up change to previous drm
 scheduler change.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Align refcount behaviour for amdgpu_job embedded HW fence with
classic pointer style HW fences by increasing refcount each
time emit is called so amdgpu code doesn't need to make workarounds
using amdgpu_job.job_run_counter to keep the HW fence refcount balanced.

Also since in the previous patch we resumed setting s_fence->parent to NULL
in drm_sched_stop switch to directly checking if job->hw_fence is
signaled to short circuit reset if already signed.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Tested-by: Yiqing Yao <yiqing.yao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c |  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 27 +++++++++++++++++-----
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c  |  7 +++++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c    |  4 ----
 4 files changed, 29 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 44da025502aca..567597469a8a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -684,6 +684,8 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,
 		goto err_ib_sched;
 	}
 
+	/* Drop the initial kref_init count (see drm_sched_main as example) */
+	dma_fence_put(f);
 	ret = dma_fence_wait(f, false);
 
 err_ib_sched:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9d2395ab4f70b..0a1c47ccd1ea7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5010,16 +5010,32 @@ static void amdgpu_device_recheck_guilty_jobs(
 
 		/* clear job's guilty and depend the folowing step to decide the real one */
 		drm_sched_reset_karma(s_job);
-		/* for the real bad job, it will be resubmitted twice, adding a dma_fence_get
-		 * to make sure fence is balanced */
-		dma_fence_get(s_job->s_fence->parent);
 		drm_sched_resubmit_jobs_ext(&ring->sched, 1);
 
+		if (!s_job->s_fence->parent) {
+			DRM_WARN("Failed to get a HW fence for job!");
+			continue;
+		}
+
 		ret = dma_fence_wait_timeout(s_job->s_fence->parent, false, ring->sched.timeout);
 		if (ret == 0) { /* timeout */
 			DRM_ERROR("Found the real bad job! ring:%s, job_id:%llx\n",
 						ring->sched.name, s_job->id);
 
+
+			amdgpu_fence_driver_isr_toggle(adev, true);
+
+			/* Clear this failed job from fence array */
+			amdgpu_fence_driver_clear_job_fences(ring);
+
+			amdgpu_fence_driver_isr_toggle(adev, false);
+
+			/* Since the job won't signal and we go for
+			 * another resubmit drop this parent pointer
+			 */
+			dma_fence_put(s_job->s_fence->parent);
+			s_job->s_fence->parent = NULL;
+
 			/* set guilty */
 			drm_sched_increase_karma(s_job);
 retry:
@@ -5048,7 +5064,6 @@ retry:
 
 		/* got the hw fence, signal finished fence */
 		atomic_dec(ring->sched.score);
-		dma_fence_put(s_job->s_fence->parent);
 		dma_fence_get(&s_job->s_fence->finished);
 		dma_fence_signal(&s_job->s_fence->finished);
 		dma_fence_put(&s_job->s_fence->finished);
@@ -5221,8 +5236,8 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
 	 *
 	 * job->base holds a reference to parent fence
 	 */
-	if (job && job->base.s_fence->parent &&
-	    dma_fence_is_signaled(job->base.s_fence->parent)) {
+	if (job && (job->hw_fence.ops != NULL) &&
+	    dma_fence_is_signaled(&job->hw_fence)) {
 		job_signaled = true;
 		dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
 		goto skip_hw_reset;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index c1d04ea3c67f3..39597ab807d10 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -164,11 +164,16 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, struct amd
 	if (job && job->job_run_counter) {
 		/* reinit seq for resubmitted jobs */
 		fence->seqno = seq;
+		/* TO be inline with external fence creation and other drivers */
+		dma_fence_get(fence);
 	} else {
-		if (job)
+		if (job) {
 			dma_fence_init(fence, &amdgpu_job_fence_ops,
 				       &ring->fence_drv.lock,
 				       adev->fence_context + ring->idx, seq);
+			/* Against remove in amdgpu_job_{free, free_cb} */
+			dma_fence_get(fence);
+		}
 		else
 			dma_fence_init(fence, &amdgpu_fence_ops,
 				       &ring->fence_drv.lock,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 26ede765eed89..22735790fe502 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -262,10 +262,6 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
 			DRM_ERROR("Error scheduling IBs (%d)\n", r);
 	}
 
-	if (!job->job_run_counter)
-		dma_fence_get(fence);
-	else if (finished->error < 0)
-		dma_fence_put(&job->hw_fence);
 	job->job_run_counter++;
 	amdgpu_job_free_resources(job);
 
-- 
GitLab


From 1c4dae3e4639540fb567e570cc56a3c292afb6fe Mon Sep 17 00:00:00 2001
From: Rahul Kumar <rahul.kumar1@amd.com>
Date: Tue, 28 Jun 2022 01:36:38 +0530
Subject: [PATCH 1319/1731] drm/amdgpu/display/dc: Fix null pointer exception

We observed hard hang due to NULL derefrence This issue is seen after
running system all the time after two or three days

struct dc *dc = plane_state->ctx->dc; Randomly in long run we found
plane_state or plane_state->ctx is found NULL which causes exception.

BUG: kernel NULL pointer dereference, address: 0000000000000000
PF: supervisor read access in kernel mode
PF: error_code(0x0000) - not-present page
PGD 1dc7f2067 P4D 1dc7f2067 PUD 222c75067 PMD 0
Oops: 0000 [#1] SMP NOPTI
CPU: 5 PID: 29855 Comm: kworker/u16:4 ...
...
Workqueue: events_unbound commit_work [drm_kms_helper]
RIP: 0010:dcn10_update_pending_status+0x1f/0xee [amdgpu]
Code: 41 5f c3 0f 1f 44 00 00 b0 01 c3 0f 1f 44 00 00 41 55 41 54 55 53 48 8b 1f 4c 8b af f8 00 00 00 48 8b 83 88 03 00 00 48 85 db <4c> 8b 20 0f 84 bf 00 00 00 48 89 fd 48 8b bf b8 00 00 00 48 8b 07
RSP: 0018:ffff942941997ab8 EFLAGS: 00010286
RAX: 0000000000000000 RBX: ffff8d7fd98d2000 RCX: 0000000000000000
RDX: 0000000000000000 RSI: ffff8d7e3e87c708 RDI: ffff8d7f2d8c0690
RBP: ffff8d7f2d8c0000 R08: ffff942941997a34 R09: 00000000ffffffff
R10: 0000000000005000 R11: 00000000000000f0 R12: ffff8d7f2d8c0690
R13: ffff8d8035a41680 R14: 00000000000186a0 R15: ffff8d7f2d8c1dd8
FS:  0000000000000000(0000) GS:ffff8d8037340000(0000) knlGS:0000000000000000
CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 0000000000000000 CR3: 0000000148030000 CR4: 00000000003406e0
Call Trace:
 dc_commit_state+0x6a2/0x7f0 [amdgpu]
 amdgpu_dm_atomic_commit_tail+0x460/0x19bb [amdgpu]

Tested-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index fff724e94eed0..aaa0bf321bce6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -3243,7 +3243,7 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 	struct timing_generator *tg = pipe_ctx->stream_res.tg;
 	bool flip_pending;
-	struct dc *dc = plane_state->ctx->dc;
+	struct dc *dc = pipe_ctx->stream->ctx->dc;
 
 	if (plane_state == NULL)
 		return;
-- 
GitLab


From 8c07f33ea096a1d25fcefa4e904ce50aa2358876 Mon Sep 17 00:00:00 2001
From: Philip Yang <Philip.Yang@amd.com>
Date: Mon, 27 Jun 2022 13:23:27 -0400
Subject: [PATCH 1320/1731] Revert "drm/amdkfd: Free queue after unmap queue
 success"

This reverts commit ab8529b0cdb271d9b222cbbddb2641f3fca5df8f.

This causes KFDTest KFDMemoryTest.MemoryRegister test failed on gfx9.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../drm/amd/amdkfd/kfd_device_queue_manager.c | 28 ++++++++-----------
 .../amd/amdkfd/kfd_process_queue_manager.c    |  2 +-
 2 files changed, 12 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 21e451acfa598..93a0b69954309 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1881,22 +1881,6 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm,
 
 	}
 
-	if (q->properties.is_active) {
-		if (!dqm->dev->shared_resources.enable_mes) {
-			retval = execute_queues_cpsch(dqm,
-						      KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
-			if (retval == -ETIME)
-				qpd->reset_wavefronts = true;
-		} else {
-			retval = remove_queue_mes(dqm, q, qpd);
-		}
-
-		if (retval)
-			goto failed_unmap_queue;
-
-		decrement_queue_count(dqm, qpd, q);
-	}
-
 	mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
 			q->properties.type)];
 
@@ -1910,6 +1894,17 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm,
 
 	list_del(&q->list);
 	qpd->queue_count--;
+	if (q->properties.is_active) {
+		if (!dqm->dev->shared_resources.enable_mes) {
+			decrement_queue_count(dqm, qpd, q);
+			retval = execute_queues_cpsch(dqm,
+						      KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
+			if (retval == -ETIME)
+				qpd->reset_wavefronts = true;
+		} else {
+			retval = remove_queue_mes(dqm, q, qpd);
+		}
+	}
 
 	/*
 	 * Unconditionally decrement this counter, regardless of the queue's
@@ -1926,7 +1921,6 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm,
 
 	return retval;
 
-failed_unmap_queue:
 failed_try_destroy_debugged_queue:
 
 	dqm_unlock(dqm);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index a46e2a37b4a65..c9c205df4a147 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -422,6 +422,7 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid)
 	}
 
 	if (pqn->q) {
+		kfd_procfs_del_queue(pqn->q);
 		dqm = pqn->q->device->dqm;
 		retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q);
 		if (retval) {
@@ -445,7 +446,6 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid)
 				amdgpu_amdkfd_free_gtt_mem(dev->adev, pqn->q->wptr_bo);
 
 		}
-		kfd_procfs_del_queue(pqn->q);
 		uninit_queue(pqn->q);
 	}
 
-- 
GitLab


From 32df6fe110c443763d6749a758f33a7117ec1270 Mon Sep 17 00:00:00 2001
From: Alexei Starovoitov <ast@kernel.org>
Date: Mon, 27 Jun 2022 20:22:55 +0200
Subject: [PATCH 1321/1731] bpf, docs: Better scale maintenance of BPF
 subsystem

The BPF subsystem consists of a large number of pieces. There is not a
single person that understands it all. Yet reviews are crucially important
for the BPF community to provide productive quality feedback to contributors
in a timely manner and therefore to ultimately expand the number of active
developers in the community.

So far, the BPF community had a two-stage review system, that is, a weekly
rotation among 7 developers (Alexei, Daniel, Andrii, Martin, Song, Yonghong,
John) as a first-level review of all inbound patches accompanied by a BPF CI
system which runs the in-tree BPF selftests to check for regressions for
every new patch, and then, a final check by Alexei, Daniel, Andrii to apply
the patches to either bpf or bpf-next trees.

This system worked well for the last ~3.5 years, but clearly reaches its
limits these days as it does not scale enough. Especially, as we also need
to allow enough room for every developer to contribute patches themselves,
integrate with their day to day job, and in particular avoid burnout. We
want to better scale both horizontally and vertically going forward.

On the horizontal scale, we are adding more developers (KP, Stan, Hao, Jiri)
to the overall core reviewer team, thus growing to 11 people in total. The
weekly rotation for the horizontal oncall reviewer is shortened to 1/2 week
(Mo - Wed and Thur - Fri). Instead of just patches, the coverage however
extends also generally to triage and reply to mailing list traffic (e.g. RFCs,
questions, etc).

On the vertical scale, there is clearly a need for deep expertise areas to
assign dedicated maintainer/reviewer teams that are responsible for code
reviews and help with design of individual building blocks. To some degree
we have been doing this implicitly, but the point is to formalize the teams
and commitment.

There is an overlap between areas and boundaries are intentionally grey. These
additional entries provide a guidance on who has to look at the patches. The
patch series which span multiple areas will be looked at by multiple people.
The vertical review with areas of deep expertise are bundled at the same time
with the horizontal side.

This patch cleans up a bit the BPF entries, adds mentioned developers to
the horizontal scale and creates new sub-entries with teams for developers
committing to the above outlined vertical scale. Also, pw.git tools we use
for BPF tree maintenance have been updated with a new pw-schedule script to
semi-automate vertical oncall review rotation.

Signed-off-by: Andrii Nakryiko <andrii@kernel.org>
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Martin KaFai Lau <martin.lau@linux.dev>
Acked-by: Song Liu <song@kernel.org>
Acked-by: Yonghong Song <yhs@fb.com>
Acked-by: Mykola Lysenko <mykolal@fb.com>
Acked-by: John Fastabend <john.fastabend@gmail.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Acked-by: KP Singh <kpsingh@kernel.org>
Acked-by: Stanislav Fomichev <sdf@google.com>
Acked-by: Hao Luo <haoluo@google.com>
Acked-by: Quentin Monnet <quentin@isovalent.com>
Link: https://git.kernel.org/pub/scm/linux/kernel/git/dborkman/pw.git
Link: https://lore.kernel.org/bpf/5bdc73e7f5a087299589944fa074563cdf2c2c1a.1656353995.git.daniel@iogearbox.net
---
 MAINTAINERS | 115 +++++++++++++++++++++++++++++++++++++++++++---------
 1 file changed, 95 insertions(+), 20 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 15a2341936ea5..ade0a42411e4b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3614,16 +3614,18 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml
 F:	drivers/iio/accel/bma400*
 
-BPF (Safe dynamic programs and tools)
+BPF [GENERAL] (Safe Dynamic Programs and Tools)
 M:	Alexei Starovoitov <ast@kernel.org>
 M:	Daniel Borkmann <daniel@iogearbox.net>
 M:	Andrii Nakryiko <andrii@kernel.org>
-R:	Martin KaFai Lau <kafai@fb.com>
-R:	Song Liu <songliubraving@fb.com>
+R:	Martin KaFai Lau <martin.lau@linux.dev>
+R:	Song Liu <song@kernel.org>
 R:	Yonghong Song <yhs@fb.com>
 R:	John Fastabend <john.fastabend@gmail.com>
 R:	KP Singh <kpsingh@kernel.org>
-L:	netdev@vger.kernel.org
+R:	Stanislav Fomichev <sdf@google.com>
+R:	Hao Luo <haoluo@google.com>
+R:	Jiri Olsa <jolsa@kernel.org>
 L:	bpf@vger.kernel.org
 S:	Supported
 W:	https://bpf.io/
@@ -3655,12 +3657,9 @@ F:	scripts/pahole-version.sh
 F:	tools/bpf/
 F:	tools/lib/bpf/
 F:	tools/testing/selftests/bpf/
-N:	bpf
-K:	bpf
 
 BPF JIT for ARM
 M:	Shubham Bansal <illusionist.neo@gmail.com>
-L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
 S:	Odd Fixes
 F:	arch/arm/net/
@@ -3669,7 +3668,6 @@ BPF JIT for ARM64
 M:	Daniel Borkmann <daniel@iogearbox.net>
 M:	Alexei Starovoitov <ast@kernel.org>
 M:	Zi Shen Lim <zlim.lnx@gmail.com>
-L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
 S:	Supported
 F:	arch/arm64/net/
@@ -3677,14 +3675,12 @@ F:	arch/arm64/net/
 BPF JIT for MIPS (32-BIT AND 64-BIT)
 M:	Johan Almbladh <johan.almbladh@anyfinetworks.com>
 M:	Paul Burton <paulburton@kernel.org>
-L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
 S:	Maintained
 F:	arch/mips/net/
 
 BPF JIT for NFP NICs
 M:	Jakub Kicinski <kuba@kernel.org>
-L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
 S:	Odd Fixes
 F:	drivers/net/ethernet/netronome/nfp/bpf/
@@ -3692,7 +3688,6 @@ F:	drivers/net/ethernet/netronome/nfp/bpf/
 BPF JIT for POWERPC (32-BIT AND 64-BIT)
 M:	Naveen N. Rao <naveen.n.rao@linux.ibm.com>
 M:	Michael Ellerman <mpe@ellerman.id.au>
-L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
 S:	Supported
 F:	arch/powerpc/net/
@@ -3700,7 +3695,6 @@ F:	arch/powerpc/net/
 BPF JIT for RISC-V (32-bit)
 M:	Luke Nelson <luke.r.nels@gmail.com>
 M:	Xi Wang <xi.wang@gmail.com>
-L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
 S:	Maintained
 F:	arch/riscv/net/
@@ -3708,7 +3702,6 @@ X:	arch/riscv/net/bpf_jit_comp64.c
 
 BPF JIT for RISC-V (64-bit)
 M:	Björn Töpel <bjorn@kernel.org>
-L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
 S:	Maintained
 F:	arch/riscv/net/
@@ -3718,7 +3711,6 @@ BPF JIT for S390
 M:	Ilya Leoshkevich <iii@linux.ibm.com>
 M:	Heiko Carstens <hca@linux.ibm.com>
 M:	Vasily Gorbik <gor@linux.ibm.com>
-L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
 S:	Supported
 F:	arch/s390/net/
@@ -3726,14 +3718,12 @@ X:	arch/s390/net/pnet.c
 
 BPF JIT for SPARC (32-BIT AND 64-BIT)
 M:	David S. Miller <davem@davemloft.net>
-L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
 S:	Odd Fixes
 F:	arch/sparc/net/
 
 BPF JIT for X86 32-BIT
 M:	Wang YanQing <udknight@gmail.com>
-L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
 S:	Odd Fixes
 F:	arch/x86/net/bpf_jit_comp32.c
@@ -3741,13 +3731,60 @@ F:	arch/x86/net/bpf_jit_comp32.c
 BPF JIT for X86 64-BIT
 M:	Alexei Starovoitov <ast@kernel.org>
 M:	Daniel Borkmann <daniel@iogearbox.net>
-L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
 S:	Supported
 F:	arch/x86/net/
 X:	arch/x86/net/bpf_jit_comp32.c
 
-BPF LSM (Security Audit and Enforcement using BPF)
+BPF [CORE]
+M:	Alexei Starovoitov <ast@kernel.org>
+M:	Daniel Borkmann <daniel@iogearbox.net>
+R:	John Fastabend <john.fastabend@gmail.com>
+L:	bpf@vger.kernel.org
+S:	Maintained
+F:	kernel/bpf/verifier.c
+F:	kernel/bpf/tnum.c
+F:	kernel/bpf/core.c
+F:	kernel/bpf/syscall.c
+F:	kernel/bpf/dispatcher.c
+F:	kernel/bpf/trampoline.c
+F:	include/linux/bpf*
+F:	include/linux/filter.h
+
+BPF [BTF]
+M:	Martin KaFai Lau <martin.lau@linux.dev>
+L:	bpf@vger.kernel.org
+S:	Maintained
+F:	kernel/bpf/btf.c
+F:	include/linux/btf*
+
+BPF [TRACING]
+M:	Song Liu <song@kernel.org>
+R:	Jiri Olsa <jolsa@kernel.org>
+L:	bpf@vger.kernel.org
+S:	Maintained
+F:	kernel/trace/bpf_trace.c
+F:	kernel/bpf/stackmap.c
+
+BPF [NETWORKING] (tc BPF, sock_addr)
+M:	Martin KaFai Lau <martin.lau@linux.dev>
+M:	Daniel Borkmann <daniel@iogearbox.net>
+R:	John Fastabend <john.fastabend@gmail.com>
+L:	bpf@vger.kernel.org
+L:	netdev@vger.kernel.org
+S:	Maintained
+F:	net/core/filter.c
+F:	net/sched/act_bpf.c
+F:	net/sched/cls_bpf.c
+
+BPF [NETWORKING] (struct_ops, reuseport)
+M:	Martin KaFai Lau <martin.lau@linux.dev>
+L:	bpf@vger.kernel.org
+L:	netdev@vger.kernel.org
+S:	Maintained
+F:	kernel/bpf/bpf_struct*
+
+BPF [SECURITY & LSM] (Security Audit and Enforcement using BPF)
 M:	KP Singh <kpsingh@kernel.org>
 R:	Florent Revest <revest@chromium.org>
 R:	Brendan Jackman <jackmanb@chromium.org>
@@ -3758,7 +3795,27 @@ F:	include/linux/bpf_lsm.h
 F:	kernel/bpf/bpf_lsm.c
 F:	security/bpf/
 
-BPF L7 FRAMEWORK
+BPF [STORAGE & CGROUPS]
+M:	Martin KaFai Lau <martin.lau@linux.dev>
+L:	bpf@vger.kernel.org
+S:	Maintained
+F:	kernel/bpf/cgroup.c
+F:	kernel/bpf/*storage.c
+F:	kernel/bpf/bpf_lru*
+
+BPF [RINGBUF]
+M:	Andrii Nakryiko <andrii@kernel.org>
+L:	bpf@vger.kernel.org
+S:	Maintained
+F:	kernel/bpf/ringbuf.c
+
+BPF [ITERATOR]
+M:	Yonghong Song <yhs@fb.com>
+L:	bpf@vger.kernel.org
+S:	Maintained
+F:	kernel/bpf/*iter.c
+
+BPF [L7 FRAMEWORK] (sockmap)
 M:	John Fastabend <john.fastabend@gmail.com>
 M:	Jakub Sitnicki <jakub@cloudflare.com>
 L:	netdev@vger.kernel.org
@@ -3771,13 +3828,31 @@ F:	net/ipv4/tcp_bpf.c
 F:	net/ipv4/udp_bpf.c
 F:	net/unix/unix_bpf.c
 
-BPFTOOL
+BPF [LIBRARY] (libbpf)
+M:	Andrii Nakryiko <andrii@kernel.org>
+L:	bpf@vger.kernel.org
+S:	Maintained
+F:	tools/lib/bpf/
+
+BPF [TOOLING] (bpftool)
 M:	Quentin Monnet <quentin@isovalent.com>
 L:	bpf@vger.kernel.org
 S:	Maintained
 F:	kernel/bpf/disasm.*
 F:	tools/bpf/bpftool/
 
+BPF [SELFTESTS] (Test Runners & Infrastructure)
+M:	Andrii Nakryiko <andrii@kernel.org>
+R:	Mykola Lysenko <mykolal@fb.com>
+L:	bpf@vger.kernel.org
+S:	Maintained
+F:	tools/testing/selftests/bpf/
+
+BPF [MISC]
+L:	bpf@vger.kernel.org
+S:	Odd Fixes
+K:	(?:\b|_)bpf(?:\b|_)
+
 BROADCOM B44 10/100 ETHERNET DRIVER
 M:	Michael Chan <michael.chan@broadcom.com>
 L:	netdev@vger.kernel.org
-- 
GitLab


From 7fe718fb8f3f543da1f04ca08bf652dd2afb55f8 Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Sun, 9 May 2021 09:39:02 -0300
Subject: [PATCH 1322/1731] tools headers UAPI: Sync linux/kvm.h with the
 kernel sources

To pick the changes in:

  bfbab44568779e16 ("KVM: arm64: Implement PSCI SYSTEM_SUSPEND")
  7b33a09d036ffd9a ("KVM: arm64: Add support for userspace to suspend a vCPU")
  ffbb61d09fc56c85 ("KVM: x86: Accept KVM_[GS]ET_TSC_KHZ as a VM ioctl.")
  661a20fab7d156cf ("KVM: x86/xen: Advertise and document KVM_XEN_HVM_CONFIG_EVTCHN_SEND")
  fde0451be8fb3208 ("KVM: x86/xen: Support per-vCPU event channel upcall via local APIC")
  28d1629f751c4a5f ("KVM: x86/xen: Kernel acceleration for XENVER_version")
  536395260582be74 ("KVM: x86/xen: handle PV timers oneshot mode")
  942c2490c23f2800 ("KVM: x86/xen: Add KVM_XEN_VCPU_ATTR_TYPE_VCPU_ID")
  2fd6df2f2b47d430 ("KVM: x86/xen: intercept EVTCHNOP_send from guests")
  35025735a79eaa89 ("KVM: x86/xen: Support direct injection of event channel events")

That automatically adds support for this new ioctl:

  $ tools/perf/trace/beauty/kvm_ioctl.sh > before
  $ cp include/uapi/linux/kvm.h tools/include/uapi/linux/kvm.h
  $ tools/perf/trace/beauty/kvm_ioctl.sh > after
  $ diff -u before after
  --- before	2022-06-28 12:13:07.281150509 -0300
  +++ after	2022-06-28 12:13:16.423392896 -0300
  @@ -98,6 +98,7 @@
   	[0xcc] = "GET_SREGS2",
   	[0xcd] = "SET_SREGS2",
   	[0xce] = "GET_STATS_FD",
  +	[0xd0] = "XEN_HVM_EVTCHN_SEND",
   	[0xe0] = "CREATE_DEVICE",
   	[0xe1] = "SET_DEVICE_ATTR",
   	[0xe2] = "GET_DEVICE_ATTR",
  $

This silences these perf build warning:

  Warning: Kernel ABI header at 'tools/include/uapi/linux/kvm.h' differs from latest version at 'include/uapi/linux/kvm.h'
  diff -u tools/include/uapi/linux/kvm.h include/uapi/linux/kvm.h

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: David Woodhouse <dwmw@amazon.co.uk>
Cc: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Joao Martins <joao.m.martins@oracle.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Oliver Upton <oupton@google.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Link: http://lore.kernel.org/lkml/Yrs4RE+qfgTaWdAt@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/include/uapi/linux/kvm.h | 54 ++++++++++++++++++++++++++++++++--
 1 file changed, 52 insertions(+), 2 deletions(-)

diff --git a/tools/include/uapi/linux/kvm.h b/tools/include/uapi/linux/kvm.h
index 6a184d260c7f2..5088bd9f19228 100644
--- a/tools/include/uapi/linux/kvm.h
+++ b/tools/include/uapi/linux/kvm.h
@@ -444,6 +444,9 @@ struct kvm_run {
 #define KVM_SYSTEM_EVENT_SHUTDOWN       1
 #define KVM_SYSTEM_EVENT_RESET          2
 #define KVM_SYSTEM_EVENT_CRASH          3
+#define KVM_SYSTEM_EVENT_WAKEUP         4
+#define KVM_SYSTEM_EVENT_SUSPEND        5
+#define KVM_SYSTEM_EVENT_SEV_TERM       6
 			__u32 type;
 			__u32 ndata;
 			union {
@@ -646,6 +649,7 @@ struct kvm_vapic_addr {
 #define KVM_MP_STATE_OPERATING         7
 #define KVM_MP_STATE_LOAD              8
 #define KVM_MP_STATE_AP_RESET_HOLD     9
+#define KVM_MP_STATE_SUSPENDED         10
 
 struct kvm_mp_state {
 	__u32 mp_state;
@@ -1150,8 +1154,9 @@ struct kvm_ppc_resize_hpt {
 #define KVM_CAP_S390_MEM_OP_EXTENSION 211
 #define KVM_CAP_PMU_CAPABILITY 212
 #define KVM_CAP_DISABLE_QUIRKS2 213
-/* #define KVM_CAP_VM_TSC_CONTROL 214 */
+#define KVM_CAP_VM_TSC_CONTROL 214
 #define KVM_CAP_SYSTEM_EVENT_DATA 215
+#define KVM_CAP_ARM_SYSTEM_SUSPEND 216
 
 #ifdef KVM_CAP_IRQ_ROUTING
 
@@ -1240,6 +1245,7 @@ struct kvm_x86_mce {
 #define KVM_XEN_HVM_CONFIG_SHARED_INFO		(1 << 2)
 #define KVM_XEN_HVM_CONFIG_RUNSTATE		(1 << 3)
 #define KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL	(1 << 4)
+#define KVM_XEN_HVM_CONFIG_EVTCHN_SEND		(1 << 5)
 
 struct kvm_xen_hvm_config {
 	__u32 flags;
@@ -1478,7 +1484,8 @@ struct kvm_s390_ucas_mapping {
 #define KVM_SET_PIT2              _IOW(KVMIO,  0xa0, struct kvm_pit_state2)
 /* Available with KVM_CAP_PPC_GET_PVINFO */
 #define KVM_PPC_GET_PVINFO	  _IOW(KVMIO,  0xa1, struct kvm_ppc_pvinfo)
-/* Available with KVM_CAP_TSC_CONTROL */
+/* Available with KVM_CAP_TSC_CONTROL for a vCPU, or with
+*  KVM_CAP_VM_TSC_CONTROL to set defaults for a VM */
 #define KVM_SET_TSC_KHZ           _IO(KVMIO,  0xa2)
 #define KVM_GET_TSC_KHZ           _IO(KVMIO,  0xa3)
 /* Available with KVM_CAP_PCI_2_3 */
@@ -1694,6 +1701,32 @@ struct kvm_xen_hvm_attr {
 		struct {
 			__u64 gfn;
 		} shared_info;
+		struct {
+			__u32 send_port;
+			__u32 type; /* EVTCHNSTAT_ipi / EVTCHNSTAT_interdomain */
+			__u32 flags;
+#define KVM_XEN_EVTCHN_DEASSIGN		(1 << 0)
+#define KVM_XEN_EVTCHN_UPDATE		(1 << 1)
+#define KVM_XEN_EVTCHN_RESET		(1 << 2)
+			/*
+			 * Events sent by the guest are either looped back to
+			 * the guest itself (potentially on a different port#)
+			 * or signalled via an eventfd.
+			 */
+			union {
+				struct {
+					__u32 port;
+					__u32 vcpu;
+					__u32 priority;
+				} port;
+				struct {
+					__u32 port; /* Zero for eventfd */
+					__s32 fd;
+				} eventfd;
+				__u32 padding[4];
+			} deliver;
+		} evtchn;
+		__u32 xen_version;
 		__u64 pad[8];
 	} u;
 };
@@ -1702,11 +1735,17 @@ struct kvm_xen_hvm_attr {
 #define KVM_XEN_ATTR_TYPE_LONG_MODE		0x0
 #define KVM_XEN_ATTR_TYPE_SHARED_INFO		0x1
 #define KVM_XEN_ATTR_TYPE_UPCALL_VECTOR		0x2
+/* Available with KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_EVTCHN_SEND */
+#define KVM_XEN_ATTR_TYPE_EVTCHN		0x3
+#define KVM_XEN_ATTR_TYPE_XEN_VERSION		0x4
 
 /* Per-vCPU Xen attributes */
 #define KVM_XEN_VCPU_GET_ATTR	_IOWR(KVMIO, 0xca, struct kvm_xen_vcpu_attr)
 #define KVM_XEN_VCPU_SET_ATTR	_IOW(KVMIO,  0xcb, struct kvm_xen_vcpu_attr)
 
+/* Available with KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_EVTCHN_SEND */
+#define KVM_XEN_HVM_EVTCHN_SEND	_IOW(KVMIO,  0xd0, struct kvm_irq_routing_xen_evtchn)
+
 #define KVM_GET_SREGS2             _IOR(KVMIO,  0xcc, struct kvm_sregs2)
 #define KVM_SET_SREGS2             _IOW(KVMIO,  0xcd, struct kvm_sregs2)
 
@@ -1724,6 +1763,13 @@ struct kvm_xen_vcpu_attr {
 			__u64 time_blocked;
 			__u64 time_offline;
 		} runstate;
+		__u32 vcpu_id;
+		struct {
+			__u32 port;
+			__u32 priority;
+			__u64 expires_ns;
+		} timer;
+		__u8 vector;
 	} u;
 };
 
@@ -1734,6 +1780,10 @@ struct kvm_xen_vcpu_attr {
 #define KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_CURRENT	0x3
 #define KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_DATA	0x4
 #define KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_ADJUST	0x5
+/* Available with KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_EVTCHN_SEND */
+#define KVM_XEN_VCPU_ATTR_TYPE_VCPU_ID		0x6
+#define KVM_XEN_VCPU_ATTR_TYPE_TIMER		0x7
+#define KVM_XEN_VCPU_ATTR_TYPE_UPCALL_VECTOR	0x8
 
 /* Secure Encrypted Virtualization command */
 enum sev_cmd_id {
-- 
GitLab


From 3a0cf7ab8df3878a7e2f3d29275b785cf4e7afb6 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Fri, 24 Jun 2022 13:23:34 +0200
Subject: [PATCH 1323/1731] ACPI: video: Change how we determine if brightness
 key-presses are handled

Some systems have an ACPI video bus but not ACPI video devices with
backlight capability. On these devices brightness key-presses are
(logically) not reported through the ACPI video bus.

Change how acpi_video_handles_brightness_key_presses() determines if
brightness key-presses are handled by the ACPI video driver to avoid
vendor specific drivers/platform/x86 drivers filtering out their
brightness key-presses even though they are the only ones reporting
these presses.

Fixes: ed83c9171829 ("platform/x86: panasonic-laptop: Resolve hotkey double trigger bug")
Reported-and-tested-by: Stefan Seyfried <seife+kernel@b1-systems.com>
Reported-and-tested-by: Kenneth Chan <kenneth.t.chan@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220624112340.10130-2-hdegoede@redhat.com
---
 drivers/acpi/acpi_video.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/acpi/acpi_video.c b/drivers/acpi/acpi_video.c
index e07782b1fbb68..43177c20ce4f6 100644
--- a/drivers/acpi/acpi_video.c
+++ b/drivers/acpi/acpi_video.c
@@ -73,6 +73,7 @@ module_param(device_id_scheme, bool, 0444);
 static int only_lcd = -1;
 module_param(only_lcd, int, 0444);
 
+static bool has_backlight;
 static int register_count;
 static DEFINE_MUTEX(register_count_mutex);
 static DEFINE_MUTEX(video_list_lock);
@@ -1222,6 +1223,9 @@ acpi_video_bus_get_one_device(struct acpi_device *device,
 	acpi_video_device_bind(video, data);
 	acpi_video_device_find_cap(data);
 
+	if (data->cap._BCM && data->cap._BCL)
+		has_backlight = true;
+
 	mutex_lock(&video->device_list_lock);
 	list_add_tail(&data->entry, &video->video_device_list);
 	mutex_unlock(&video->device_list_lock);
@@ -2249,6 +2253,7 @@ void acpi_video_unregister(void)
 	if (register_count) {
 		acpi_bus_unregister_driver(&acpi_video_bus);
 		register_count = 0;
+		has_backlight = false;
 	}
 	mutex_unlock(&register_count_mutex);
 }
@@ -2270,13 +2275,7 @@ void acpi_video_unregister_backlight(void)
 
 bool acpi_video_handles_brightness_key_presses(void)
 {
-	bool have_video_busses;
-
-	mutex_lock(&video_list_lock);
-	have_video_busses = !list_empty(&video_bus_head);
-	mutex_unlock(&video_list_lock);
-
-	return have_video_busses &&
+	return has_backlight &&
 	       (report_key_events & REPORT_BRIGHTNESS_KEY_EVENTS);
 }
 EXPORT_SYMBOL(acpi_video_handles_brightness_key_presses);
-- 
GitLab


From 65a3e6c8d3f7c346813a05f3d76fc46b640d76d6 Mon Sep 17 00:00:00 2001
From: Stefan Seyfried <seife+kernel@b1-systems.com>
Date: Fri, 24 Jun 2022 13:23:35 +0200
Subject: [PATCH 1324/1731] platform/x86: panasonic-laptop: de-obfuscate button
 codes

In the definition of panasonic_keymap[] the key codes are given in
decimal, later checks are done with hexadecimal values, which does
not help in understanding the code.
Additionally use two helper variables to shorten the code and make
the logic more obvious.

Fixes: ed83c9171829 ("platform/x86: panasonic-laptop: Resolve hotkey double trigger bug")
Signed-off-by: Stefan Seyfried <seife+kernel@b1-systems.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220624112340.10130-3-hdegoede@redhat.com
---
 drivers/platform/x86/panasonic-laptop.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/platform/x86/panasonic-laptop.c b/drivers/platform/x86/panasonic-laptop.c
index 37850d07987d8..ca6137f4000fd 100644
--- a/drivers/platform/x86/panasonic-laptop.c
+++ b/drivers/platform/x86/panasonic-laptop.c
@@ -762,6 +762,8 @@ static void acpi_pcc_generate_keyinput(struct pcc_acpi *pcc)
 	struct input_dev *hotk_input_dev = pcc->input_dev;
 	int rc;
 	unsigned long long result;
+	unsigned int key;
+	unsigned int updown;
 
 	rc = acpi_evaluate_integer(pcc->handle, METHOD_HKEY_QUERY,
 				   NULL, &result);
@@ -770,18 +772,22 @@ static void acpi_pcc_generate_keyinput(struct pcc_acpi *pcc)
 		return;
 	}
 
+	key = result & 0xf;
+	updown = result & 0x80; /* 0x80 == key down; 0x00 = key up */
+
 	/* hack: some firmware sends no key down for sleep / hibernate */
-	if ((result & 0xf) == 0x7 || (result & 0xf) == 0xa) {
-		if (result & 0x80)
+	if (key == 7 || key == 10) {
+		if (updown)
 			sleep_keydown_seen = 1;
 		if (!sleep_keydown_seen)
 			sparse_keymap_report_event(hotk_input_dev,
-					result & 0xf, 0x80, false);
+					key, 0x80, false);
 	}
 
-	if ((result & 0xf) == 0x7 || (result & 0xf) == 0x9 || (result & 0xf) == 0xa) {
+	/* for the magic values, see panasonic_keymap[] above */
+	if (key == 7 || key == 9 || key == 10) {
 		if (!sparse_keymap_report_event(hotk_input_dev,
-						result & 0xf, result & 0x80, false))
+						key, updown, false))
 			pr_err("Unknown hotkey event: 0x%04llx\n", result);
 	}
 }
-- 
GitLab


From fe4326c8d18dc8a54affdc9ab269ad92dafef659 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Fri, 24 Jun 2022 13:23:36 +0200
Subject: [PATCH 1325/1731] platform/x86: panasonic-laptop: sort includes
 alphabetically

Sort includes alphabetically, small cleanup patch in preparation of
further changes.

Fixes: ed83c9171829 ("platform/x86: panasonic-laptop: Resolve hotkey double trigger bug")
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220624112340.10130-4-hdegoede@redhat.com
---
 drivers/platform/x86/panasonic-laptop.c | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/platform/x86/panasonic-laptop.c b/drivers/platform/x86/panasonic-laptop.c
index ca6137f4000fd..26e31ac09dc6a 100644
--- a/drivers/platform/x86/panasonic-laptop.c
+++ b/drivers/platform/x86/panasonic-laptop.c
@@ -119,20 +119,19 @@
  *		- v0.1  start from toshiba_acpi driver written by John Belmonte
  */
 
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/types.h>
+#include <linux/acpi.h>
 #include <linux/backlight.h>
 #include <linux/ctype.h>
-#include <linux/seq_file.h>
-#include <linux/uaccess.h>
-#include <linux/slab.h>
-#include <linux/acpi.h>
+#include <linux/init.h>
 #include <linux/input.h>
 #include <linux/input/sparse-keymap.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/platform_device.h>
-
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/uaccess.h>
 
 MODULE_AUTHOR("Hiroshi Miura <miura@da-cha.org>");
 MODULE_AUTHOR("David Bronaugh <dbronaugh@linuxboxen.org>");
-- 
GitLab


From 83a5ddc3dc561c40d948b85553514aaba99123d8 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Fri, 24 Jun 2022 13:23:37 +0200
Subject: [PATCH 1326/1731] platform/x86: panasonic-laptop: revert "Resolve
 hotkey double trigger bug"

In hindsight blindly throwing away most of the key-press events is not
a good idea. So revert commit ed83c9171829 ("platform/x86:
panasonic-laptop: Resolve hotkey double trigger bug").

Fixes: ed83c9171829 ("platform/x86: panasonic-laptop: Resolve hotkey double trigger bug")
Reported-and-tested-by: Stefan Seyfried <seife+kernel@b1-systems.com>
Reported-and-tested-by: Kenneth Chan <kenneth.t.chan@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220624112340.10130-5-hdegoede@redhat.com
---
 drivers/platform/x86/panasonic-laptop.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/platform/x86/panasonic-laptop.c b/drivers/platform/x86/panasonic-laptop.c
index 26e31ac09dc6a..2e6531dd15f95 100644
--- a/drivers/platform/x86/panasonic-laptop.c
+++ b/drivers/platform/x86/panasonic-laptop.c
@@ -783,12 +783,8 @@ static void acpi_pcc_generate_keyinput(struct pcc_acpi *pcc)
 					key, 0x80, false);
 	}
 
-	/* for the magic values, see panasonic_keymap[] above */
-	if (key == 7 || key == 9 || key == 10) {
-		if (!sparse_keymap_report_event(hotk_input_dev,
-						key, updown, false))
-			pr_err("Unknown hotkey event: 0x%04llx\n", result);
-	}
+	if (!sparse_keymap_report_event(hotk_input_dev, key, updown, false))
+		pr_err("Unknown hotkey event: 0x%04llx\n", result);
 }
 
 static void acpi_pcc_hotkey_notify(struct acpi_device *device, u32 event)
-- 
GitLab


From 1f2c9de83a50447a2d7166f6273ab0c0e97cd68e Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Fri, 24 Jun 2022 13:23:38 +0200
Subject: [PATCH 1327/1731] platform/x86: panasonic-laptop: don't report
 duplicate brightness key-presses

The brightness key-presses might also get reported by the ACPI video bus,
check for this and in this case don't report the presses to avoid reporting
2 presses for a single key-press.

Fixes: ed83c9171829 ("platform/x86: panasonic-laptop: Resolve hotkey double trigger bug")
Reported-and-tested-by: Stefan Seyfried <seife+kernel@b1-systems.com>
Reported-and-tested-by: Kenneth Chan <kenneth.t.chan@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220624112340.10130-6-hdegoede@redhat.com
---
 drivers/platform/x86/Kconfig            | 1 +
 drivers/platform/x86/panasonic-laptop.c | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index f08ad85683cb0..b59063f831044 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -945,6 +945,7 @@ config PANASONIC_LAPTOP
 	tristate "Panasonic Laptop Extras"
 	depends on INPUT && ACPI
 	depends on BACKLIGHT_CLASS_DEVICE
+	depends on ACPI_VIDEO=n || ACPI_VIDEO
 	select INPUT_SPARSEKMAP
 	help
 	  This driver adds support for access to backlight control and hotkeys
diff --git a/drivers/platform/x86/panasonic-laptop.c b/drivers/platform/x86/panasonic-laptop.c
index 2e6531dd15f95..d65e6c2372ca6 100644
--- a/drivers/platform/x86/panasonic-laptop.c
+++ b/drivers/platform/x86/panasonic-laptop.c
@@ -132,6 +132,7 @@
 #include <linux/slab.h>
 #include <linux/types.h>
 #include <linux/uaccess.h>
+#include <acpi/video.h>
 
 MODULE_AUTHOR("Hiroshi Miura <miura@da-cha.org>");
 MODULE_AUTHOR("David Bronaugh <dbronaugh@linuxboxen.org>");
@@ -783,6 +784,13 @@ static void acpi_pcc_generate_keyinput(struct pcc_acpi *pcc)
 					key, 0x80, false);
 	}
 
+	/*
+	 * Don't report brightness key-presses if they are also reported
+	 * by the ACPI video bus.
+	 */
+	if ((key == 1 || key == 2) && acpi_video_handles_brightness_key_presses())
+		return;
+
 	if (!sparse_keymap_report_event(hotk_input_dev, key, updown, false))
 		pr_err("Unknown hotkey event: 0x%04llx\n", result);
 }
-- 
GitLab


From aacb455dfe01b7a24a792a2fbe7a04112ce8321d Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Fri, 24 Jun 2022 13:23:39 +0200
Subject: [PATCH 1328/1731] platform/x86: panasonic-laptop: filter out
 duplicate volume up/down/mute keypresses

On some Panasonic models the volume up/down/mute keypresses get
reported both through the Panasonic ACPI HKEY interface as well as
through the atkbd device.

Filter out the atkbd scan-codes for these to avoid reporting presses
twice.

Note normally we would leave the filtering of these to userspace by mapping
the scan-codes to KEY_UNKNOWN through /lib/udev/hwdb.d/60-keyboard.hwdb.
However in this case that would cause regressions since we were filtering
the Panasonic ACPI HKEY events before, so filter these in the kernel.

Fixes: ed83c9171829 ("platform/x86: panasonic-laptop: Resolve hotkey double trigger bug")
Reported-and-tested-by: Stefan Seyfried <seife+kernel@b1-systems.com>
Reported-and-tested-by: Kenneth Chan <kenneth.t.chan@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220624112340.10130-7-hdegoede@redhat.com
---
 drivers/platform/x86/Kconfig            |  1 +
 drivers/platform/x86/panasonic-laptop.c | 41 +++++++++++++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index b59063f831044..bc4013e950ed5 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -946,6 +946,7 @@ config PANASONIC_LAPTOP
 	depends on INPUT && ACPI
 	depends on BACKLIGHT_CLASS_DEVICE
 	depends on ACPI_VIDEO=n || ACPI_VIDEO
+	depends on SERIO_I8042 || SERIO_I8042 = n
 	select INPUT_SPARSEKMAP
 	help
 	  This driver adds support for access to backlight control and hotkeys
diff --git a/drivers/platform/x86/panasonic-laptop.c b/drivers/platform/x86/panasonic-laptop.c
index d65e6c2372ca6..615e39cbbbf19 100644
--- a/drivers/platform/x86/panasonic-laptop.c
+++ b/drivers/platform/x86/panasonic-laptop.c
@@ -122,6 +122,7 @@
 #include <linux/acpi.h>
 #include <linux/backlight.h>
 #include <linux/ctype.h>
+#include <linux/i8042.h>
 #include <linux/init.h>
 #include <linux/input.h>
 #include <linux/input/sparse-keymap.h>
@@ -129,6 +130,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/seq_file.h>
+#include <linux/serio.h>
 #include <linux/slab.h>
 #include <linux/types.h>
 #include <linux/uaccess.h>
@@ -241,6 +243,42 @@ struct pcc_acpi {
 	struct platform_device	*platform;
 };
 
+/*
+ * On some Panasonic models the volume up / down / mute keys send duplicate
+ * keypress events over the PS/2 kbd interface, filter these out.
+ */
+static bool panasonic_i8042_filter(unsigned char data, unsigned char str,
+				   struct serio *port)
+{
+	static bool extended;
+
+	if (str & I8042_STR_AUXDATA)
+		return false;
+
+	if (data == 0xe0) {
+		extended = true;
+		return true;
+	} else if (extended) {
+		extended = false;
+
+		switch (data & 0x7f) {
+		case 0x20: /* e0 20 / e0 a0, Volume Mute press / release */
+		case 0x2e: /* e0 2e / e0 ae, Volume Down press / release */
+		case 0x30: /* e0 30 / e0 b0, Volume Up press / release */
+			return true;
+		default:
+			/*
+			 * Report the previously filtered e0 before continuing
+			 * with the next non-filtered byte.
+			 */
+			serio_interrupt(port, 0xe0, 0);
+			return false;
+		}
+	}
+
+	return false;
+}
+
 /* method access functions */
 static int acpi_pcc_write_sset(struct pcc_acpi *pcc, int func, int val)
 {
@@ -1006,6 +1044,7 @@ static int acpi_pcc_hotkey_add(struct acpi_device *device)
 		pcc->platform = NULL;
 	}
 
+	i8042_install_filter(panasonic_i8042_filter);
 	return 0;
 
 out_platform:
@@ -1029,6 +1068,8 @@ static int acpi_pcc_hotkey_remove(struct acpi_device *device)
 	if (!device || !pcc)
 		return -EINVAL;
 
+	i8042_remove_filter(panasonic_i8042_filter);
+
 	if (pcc->platform) {
 		device_remove_file(&pcc->platform->dev, &dev_attr_cdpower);
 		platform_device_unregister(pcc->platform);
-- 
GitLab


From 42504af775361ca2330a2bfde496a5ebc5655c86 Mon Sep 17 00:00:00 2001
From: Mark Pearson <markpearson@lenovo.com>
Date: Fri, 3 Jun 2022 13:02:09 -0400
Subject: [PATCH 1329/1731] platform/x86: thinkpad-acpi: profile capabilities
 as integer

Currently the active mode (PSC/MMC) is stored in an enum and queried
throughout the driver.

Other driver changes will enumerate additional submodes that are relevant
to be tracked, so instead track PSC/MMC in a single integer variable.

Co-developed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Mark Pearson <markpearson@lenovo.com>
Link: https://lore.kernel.org/r/20220603170212.164963-1-markpearson@lenovo.com
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 drivers/platform/x86/thinkpad_acpi.c | 45 +++++++++++-----------------
 1 file changed, 18 insertions(+), 27 deletions(-)

diff --git a/drivers/platform/x86/thinkpad_acpi.c b/drivers/platform/x86/thinkpad_acpi.c
index aa6ffeaa39329..b4d6a356b7462 100644
--- a/drivers/platform/x86/thinkpad_acpi.c
+++ b/drivers/platform/x86/thinkpad_acpi.c
@@ -10300,21 +10300,15 @@ static struct ibm_struct proxsensor_driver_data = {
 #define DYTC_DISABLE_CQL DYTC_SET_COMMAND(DYTC_FUNCTION_CQL, DYTC_MODE_MMC_BALANCE, 0)
 #define DYTC_ENABLE_CQL DYTC_SET_COMMAND(DYTC_FUNCTION_CQL, DYTC_MODE_MMC_BALANCE, 1)
 
-enum dytc_profile_funcmode {
-	DYTC_FUNCMODE_NONE = 0,
-	DYTC_FUNCMODE_MMC,
-	DYTC_FUNCMODE_PSC,
-};
-
-static enum dytc_profile_funcmode dytc_profile_available;
 static enum platform_profile_option dytc_current_profile;
 static atomic_t dytc_ignore_event = ATOMIC_INIT(0);
 static DEFINE_MUTEX(dytc_mutex);
+static int dytc_capabilities;
 static bool dytc_mmc_get_available;
 
 static int convert_dytc_to_profile(int dytcmode, enum platform_profile_option *profile)
 {
-	if (dytc_profile_available == DYTC_FUNCMODE_MMC) {
+	if (dytc_capabilities & BIT(DYTC_FC_MMC)) {
 		switch (dytcmode) {
 		case DYTC_MODE_MMC_LOWPOWER:
 			*profile = PLATFORM_PROFILE_LOW_POWER;
@@ -10331,7 +10325,7 @@ static int convert_dytc_to_profile(int dytcmode, enum platform_profile_option *p
 		}
 		return 0;
 	}
-	if (dytc_profile_available == DYTC_FUNCMODE_PSC) {
+	if (dytc_capabilities & BIT(DYTC_FC_PSC)) {
 		switch (dytcmode) {
 		case DYTC_MODE_PSC_LOWPOWER:
 			*profile = PLATFORM_PROFILE_LOW_POWER;
@@ -10353,21 +10347,21 @@ static int convert_profile_to_dytc(enum platform_profile_option profile, int *pe
 {
 	switch (profile) {
 	case PLATFORM_PROFILE_LOW_POWER:
-		if (dytc_profile_available == DYTC_FUNCMODE_MMC)
+		if (dytc_capabilities & BIT(DYTC_FC_MMC))
 			*perfmode = DYTC_MODE_MMC_LOWPOWER;
-		else if (dytc_profile_available == DYTC_FUNCMODE_PSC)
+		else if (dytc_capabilities & BIT(DYTC_FC_PSC))
 			*perfmode = DYTC_MODE_PSC_LOWPOWER;
 		break;
 	case PLATFORM_PROFILE_BALANCED:
-		if (dytc_profile_available == DYTC_FUNCMODE_MMC)
+		if (dytc_capabilities & BIT(DYTC_FC_MMC))
 			*perfmode = DYTC_MODE_MMC_BALANCE;
-		else if (dytc_profile_available == DYTC_FUNCMODE_PSC)
+		else if (dytc_capabilities & BIT(DYTC_FC_PSC))
 			*perfmode = DYTC_MODE_PSC_BALANCE;
 		break;
 	case PLATFORM_PROFILE_PERFORMANCE:
-		if (dytc_profile_available == DYTC_FUNCMODE_MMC)
+		if (dytc_capabilities & BIT(DYTC_FC_MMC))
 			*perfmode = DYTC_MODE_MMC_PERFORM;
-		else if (dytc_profile_available == DYTC_FUNCMODE_PSC)
+		else if (dytc_capabilities & BIT(DYTC_FC_PSC))
 			*perfmode = DYTC_MODE_PSC_PERFORM;
 		break;
 	default: /* Unknown profile */
@@ -10446,7 +10440,7 @@ static int dytc_profile_set(struct platform_profile_handler *pprof,
 	if (err)
 		goto unlock;
 
-	if (dytc_profile_available == DYTC_FUNCMODE_MMC) {
+	if (dytc_capabilities & BIT(DYTC_FC_MMC)) {
 		if (profile == PLATFORM_PROFILE_BALANCED) {
 			/*
 			 * To get back to balanced mode we need to issue a reset command.
@@ -10465,7 +10459,7 @@ static int dytc_profile_set(struct platform_profile_handler *pprof,
 				goto unlock;
 		}
 	}
-	if (dytc_profile_available == DYTC_FUNCMODE_PSC) {
+	if (dytc_capabilities & BIT(DYTC_FC_PSC)) {
 		err = dytc_command(DYTC_SET_COMMAND(DYTC_FUNCTION_PSC, perfmode, 1), &output);
 		if (err)
 			goto unlock;
@@ -10484,12 +10478,12 @@ static void dytc_profile_refresh(void)
 	int perfmode;
 
 	mutex_lock(&dytc_mutex);
-	if (dytc_profile_available == DYTC_FUNCMODE_MMC) {
+	if (dytc_capabilities & BIT(DYTC_FC_MMC)) {
 		if (dytc_mmc_get_available)
 			err = dytc_command(DYTC_CMD_MMC_GET, &output);
 		else
 			err = dytc_cql_command(DYTC_CMD_GET, &output);
-	} else if (dytc_profile_available == DYTC_FUNCMODE_PSC)
+	} else if (dytc_capabilities & BIT(DYTC_FC_PSC))
 		err = dytc_command(DYTC_CMD_GET, &output);
 
 	mutex_unlock(&dytc_mutex);
@@ -10518,7 +10512,6 @@ static int tpacpi_dytc_profile_init(struct ibm_init_struct *iibm)
 	set_bit(PLATFORM_PROFILE_BALANCED, dytc_profile.choices);
 	set_bit(PLATFORM_PROFILE_PERFORMANCE, dytc_profile.choices);
 
-	dytc_profile_available = DYTC_FUNCMODE_NONE;
 	err = dytc_command(DYTC_CMD_QUERY, &output);
 	if (err)
 		return err;
@@ -10531,13 +10524,12 @@ static int tpacpi_dytc_profile_init(struct ibm_init_struct *iibm)
 		return -ENODEV;
 
 	/* Check what capabilities are supported */
-	err = dytc_command(DYTC_CMD_FUNC_CAP, &output);
+	err = dytc_command(DYTC_CMD_FUNC_CAP, &dytc_capabilities);
 	if (err)
 		return err;
 
-	if (output & BIT(DYTC_FC_MMC)) { /* MMC MODE */
-		dytc_profile_available = DYTC_FUNCMODE_MMC;
-
+	if (dytc_capabilities & BIT(DYTC_FC_MMC)) { /* MMC MODE */
+		pr_debug("MMC is supported\n");
 		/*
 		 * Check if MMC_GET functionality available
 		 * Version > 6 and return success from MMC_GET command
@@ -10548,8 +10540,8 @@ static int tpacpi_dytc_profile_init(struct ibm_init_struct *iibm)
 			if (!err && ((output & DYTC_ERR_MASK) == DYTC_ERR_SUCCESS))
 				dytc_mmc_get_available = true;
 		}
-	} else if (output & BIT(DYTC_FC_PSC)) { /* PSC MODE */
-		dytc_profile_available = DYTC_FUNCMODE_PSC;
+	} else if (dytc_capabilities & BIT(DYTC_FC_PSC)) { /* PSC MODE */
+		pr_debug("PSC is supported\n");
 	} else {
 		dbg_printk(TPACPI_DBG_INIT, "No DYTC support available\n");
 		return -ENODEV;
@@ -10575,7 +10567,6 @@ static int tpacpi_dytc_profile_init(struct ibm_init_struct *iibm)
 
 static void dytc_profile_exit(void)
 {
-	dytc_profile_available = DYTC_FUNCMODE_NONE;
 	platform_profile_remove();
 }
 
-- 
GitLab


From bce6243f767f7da88aa4674d5d678f9f156eaba9 Mon Sep 17 00:00:00 2001
From: Mark Pearson <markpearson@lenovo.com>
Date: Mon, 27 Jun 2022 14:14:49 -0400
Subject: [PATCH 1330/1731] platform/x86: thinkpad_acpi: do not use PSC mode on
 Intel platforms

PSC platform profile mode is only supported on Linux for AMD platforms.

Some older Intel platforms (e.g T490) are advertising it's capability
as Windows uses it - but on Linux we should only be using MMC profile
for Intel systems.

Add a check to prevent it being enabled incorrectly.

Signed-off-by: Mark Pearson <markpearson@lenovo.com>
Link: https://lore.kernel.org/r/20220627181449.3537-1-markpearson@lenovo.com
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 drivers/platform/x86/thinkpad_acpi.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/platform/x86/thinkpad_acpi.c b/drivers/platform/x86/thinkpad_acpi.c
index b4d6a356b7462..a8b3830515285 100644
--- a/drivers/platform/x86/thinkpad_acpi.c
+++ b/drivers/platform/x86/thinkpad_acpi.c
@@ -10541,6 +10541,11 @@ static int tpacpi_dytc_profile_init(struct ibm_init_struct *iibm)
 				dytc_mmc_get_available = true;
 		}
 	} else if (dytc_capabilities & BIT(DYTC_FC_PSC)) { /* PSC MODE */
+		/* Support for this only works on AMD platforms */
+		if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
+			dbg_printk(TPACPI_DBG_INIT, "PSC not support on Intel platforms\n");
+			return -ENODEV;
+		}
 		pr_debug("PSC is supported\n");
 	} else {
 		dbg_printk(TPACPI_DBG_INIT, "No DYTC support available\n");
-- 
GitLab


From 9ab762a84b8094540c18a170e5ddd6488632c456 Mon Sep 17 00:00:00 2001
From: Kai-Heng Feng <kai.heng.feng@canonical.com>
Date: Tue, 28 Jun 2022 20:37:26 +0800
Subject: [PATCH 1331/1731] platform/x86: hp-wmi: Ignore Sanitization Mode
 event

After system resume the hp-wmi driver may complain:
[ 702.620180] hp_wmi: Unknown event_id - 23 - 0x0

According to HP it means 'Sanitization Mode' and it's harmless to just
ignore the event.

Cc: Jorge Lopez <jorge.lopez2@hp.com>
Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Link: https://lore.kernel.org/r/20220628123726.250062-1-kai.heng.feng@canonical.com
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 drivers/platform/x86/hp-wmi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/platform/x86/hp-wmi.c b/drivers/platform/x86/hp-wmi.c
index 0d8cb22e30df9..bc7020e9df9e8 100644
--- a/drivers/platform/x86/hp-wmi.c
+++ b/drivers/platform/x86/hp-wmi.c
@@ -89,6 +89,7 @@ enum hp_wmi_event_ids {
 	HPWMI_BACKLIT_KB_BRIGHTNESS	= 0x0D,
 	HPWMI_PEAKSHIFT_PERIOD		= 0x0F,
 	HPWMI_BATTERY_CHARGE_PERIOD	= 0x10,
+	HPWMI_SANITIZATION_MODE		= 0x17,
 };
 
 /*
@@ -853,6 +854,8 @@ static void hp_wmi_notify(u32 value, void *context)
 		break;
 	case HPWMI_BATTERY_CHARGE_PERIOD:
 		break;
+	case HPWMI_SANITIZATION_MODE:
+		break;
 	default:
 		pr_info("Unknown event_id - %d - 0x%x\n", event_id, event_data);
 		break;
-- 
GitLab


From 512d1999b8e94a5d43fba3afc73e774849674742 Mon Sep 17 00:00:00 2001
From: Ivan Malov <ivan.malov@oktetlabs.ru>
Date: Tue, 28 Jun 2022 12:18:48 +0300
Subject: [PATCH 1332/1731] xsk: Clear page contiguity bit when unmapping pool

When a XSK pool gets mapped, xp_check_dma_contiguity() adds bit 0x1
to pages' DMA addresses that go in ascending order and at 4K stride.

The problem is that the bit does not get cleared before doing unmap.
As a result, a lot of warnings from iommu_dma_unmap_page() are seen
in dmesg, which indicates that lookups by iommu_iova_to_phys() fail.

Fixes: 2b43470add8c ("xsk: Introduce AF_XDP buffer allocation API")
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Magnus Karlsson <magnus.karlsson@intel.com>
Link: https://lore.kernel.org/bpf/20220628091848.534803-1-ivan.malov@oktetlabs.ru
---
 net/xdp/xsk_buff_pool.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/net/xdp/xsk_buff_pool.c b/net/xdp/xsk_buff_pool.c
index 87bdd71c7bb66..f70112176b7c1 100644
--- a/net/xdp/xsk_buff_pool.c
+++ b/net/xdp/xsk_buff_pool.c
@@ -332,6 +332,7 @@ static void __xp_dma_unmap(struct xsk_dma_map *dma_map, unsigned long attrs)
 	for (i = 0; i < dma_map->dma_pages_cnt; i++) {
 		dma = &dma_map->dma_pages[i];
 		if (*dma) {
+			*dma &= ~XSK_NEXT_PG_CONTIG_MASK;
 			dma_unmap_page_attrs(dma_map->dev, *dma, PAGE_SIZE,
 					     DMA_BIDIRECTIONAL, attrs);
 			*dma = 0;
-- 
GitLab


From a4ab14e1d8fe83cc1ed8910b788117ec2ed25179 Mon Sep 17 00:00:00 2001
From: John Hubbard <jhubbard@nvidia.com>
Date: Mon, 27 Jun 2022 18:23:53 -0700
Subject: [PATCH 1333/1731] gen_compile_commands: handle multiple lines per
 .mod file

scripts/clang-tools/gen_compile_commands.py incorrectly assumes that
each .mod file only contains one line. That assumption was correct when
the script was originally created, but commit 9413e7640564 ("kbuild:
split the second line of *.mod into *.usyms") changed the .mod file
format so that there is one entry per line, and potentially many lines.

The problem can be reproduced by using Kbuild to generate
compile_commands.json, like this:

    make CC=clang compile_commands.json

In many cases, the problem might be overlooked because many subsystems
only have one line anyway. However, in some subsystems (Nouveau, with
762 entries, is a notable example) it results in skipping most of the
subsystem.

Fix this by fully processing each .mod file.

Fixes: 9413e7640564 ("kbuild: split the second line of *.mod into *.usyms")
Signed-off-by: John Hubbard <jhubbard@nvidia.com>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
---
 scripts/clang-tools/gen_compile_commands.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/scripts/clang-tools/gen_compile_commands.py b/scripts/clang-tools/gen_compile_commands.py
index 1d1bde1fd45eb..47da25b3ba7d2 100755
--- a/scripts/clang-tools/gen_compile_commands.py
+++ b/scripts/clang-tools/gen_compile_commands.py
@@ -157,10 +157,10 @@ def cmdfiles_for_modorder(modorder):
             if ext != '.ko':
                 sys.exit('{}: module path must end with .ko'.format(ko))
             mod = base + '.mod'
-	    # The first line of *.mod lists the objects that compose the module.
+            # Read from *.mod, to get a list of objects that compose the module.
             with open(mod) as m:
-                for obj in m.readline().split():
-                    yield to_cmdfile(obj)
+                for mod_line in m:
+                    yield to_cmdfile(mod_line.rstrip())
 
 
 def process_line(root_directory, command_prefix, file_path):
-- 
GitLab


From 0c1f78a49af721490a5ad70b73e8b4d382465dae Mon Sep 17 00:00:00 2001
From: Paolo Abeni <pabeni@redhat.com>
Date: Mon, 27 Jun 2022 18:02:35 -0700
Subject: [PATCH 1334/1731] mptcp: fix error mibs accounting

The current accounting for MP_FAIL and FASTCLOSE is not very
accurate: both can be increased even when the related option is
not really sent. Move the accounting into the correct place.

Fixes: eb7f33654dc1 ("mptcp: add the mibs for MP_FAIL")
Fixes: 1e75629cb964 ("mptcp: add the mibs for MP_FASTCLOSE")
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/mptcp/options.c | 5 +++--
 net/mptcp/pm.c      | 1 -
 net/mptcp/subflow.c | 4 +---
 3 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/net/mptcp/options.c b/net/mptcp/options.c
index be3b918a6d15e..2a6351d55a7d9 100644
--- a/net/mptcp/options.c
+++ b/net/mptcp/options.c
@@ -765,6 +765,7 @@ static noinline bool mptcp_established_options_rst(struct sock *sk, struct sk_bu
 	opts->suboptions |= OPTION_MPTCP_RST;
 	opts->reset_transient = subflow->reset_transient;
 	opts->reset_reason = subflow->reset_reason;
+	MPTCP_INC_STATS(sock_net(sk), MPTCP_MIB_MPRSTTX);
 
 	return true;
 }
@@ -788,6 +789,7 @@ static bool mptcp_established_options_fastclose(struct sock *sk,
 	opts->rcvr_key = msk->remote_key;
 
 	pr_debug("FASTCLOSE key=%llu", opts->rcvr_key);
+	MPTCP_INC_STATS(sock_net(sk), MPTCP_MIB_MPFASTCLOSETX);
 	return true;
 }
 
@@ -809,6 +811,7 @@ static bool mptcp_established_options_mp_fail(struct sock *sk,
 	opts->fail_seq = subflow->map_seq;
 
 	pr_debug("MP_FAIL fail_seq=%llu", opts->fail_seq);
+	MPTCP_INC_STATS(sock_net(sk), MPTCP_MIB_MPFAILTX);
 
 	return true;
 }
@@ -833,13 +836,11 @@ bool mptcp_established_options(struct sock *sk, struct sk_buff *skb,
 		    mptcp_established_options_mp_fail(sk, &opt_size, remaining, opts)) {
 			*size += opt_size;
 			remaining -= opt_size;
-			MPTCP_INC_STATS(sock_net(sk), MPTCP_MIB_MPFASTCLOSETX);
 		}
 		/* MP_RST can be used with MP_FASTCLOSE and MP_FAIL if there is room */
 		if (mptcp_established_options_rst(sk, skb, &opt_size, remaining, opts)) {
 			*size += opt_size;
 			remaining -= opt_size;
-			MPTCP_INC_STATS(sock_net(sk), MPTCP_MIB_MPRSTTX);
 		}
 		return true;
 	}
diff --git a/net/mptcp/pm.c b/net/mptcp/pm.c
index 59a85220edc9c..91a62b598de4f 100644
--- a/net/mptcp/pm.c
+++ b/net/mptcp/pm.c
@@ -310,7 +310,6 @@ void mptcp_pm_mp_fail_received(struct sock *sk, u64 fail_seq)
 		pr_debug("send MP_FAIL response and infinite map");
 
 		subflow->send_mp_fail = 1;
-		MPTCP_INC_STATS(sock_net(sk), MPTCP_MIB_MPFAILTX);
 		subflow->send_infinite_map = 1;
 	} else if (!sock_flag(sk, SOCK_DEAD)) {
 		pr_debug("MP_FAIL response received");
diff --git a/net/mptcp/subflow.c b/net/mptcp/subflow.c
index 8841e8cd9ad8d..50ad19adc0037 100644
--- a/net/mptcp/subflow.c
+++ b/net/mptcp/subflow.c
@@ -958,10 +958,8 @@ static enum mapping_status validate_data_csum(struct sock *ssk, struct sk_buff *
 				 subflow->map_data_csum);
 	if (unlikely(csum)) {
 		MPTCP_INC_STATS(sock_net(ssk), MPTCP_MIB_DATACSUMERR);
-		if (subflow->mp_join || subflow->valid_csum_seen) {
+		if (subflow->mp_join || subflow->valid_csum_seen)
 			subflow->send_mp_fail = 1;
-			MPTCP_INC_STATS(sock_net(ssk), MPTCP_MIB_MPFAILTX);
-		}
 		return subflow->mp_join ? MAPPING_INVALID : MAPPING_DUMMY;
 	}
 
-- 
GitLab


From 31bf11de146c3f8892093ff39f8f9b3069d6a852 Mon Sep 17 00:00:00 2001
From: Paolo Abeni <pabeni@redhat.com>
Date: Mon, 27 Jun 2022 18:02:36 -0700
Subject: [PATCH 1335/1731] mptcp: introduce MAPPING_BAD_CSUM

This allow moving a couple of conditional out of the fast path,
making the code more easy to follow and will simplify the next
patch.

Fixes: ae66fb2ba6c3 ("mptcp: Do TCP fallback on early DSS checksum failure")
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/mptcp/subflow.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/net/mptcp/subflow.c b/net/mptcp/subflow.c
index 50ad19adc0037..42a7c18a1c245 100644
--- a/net/mptcp/subflow.c
+++ b/net/mptcp/subflow.c
@@ -843,7 +843,8 @@ enum mapping_status {
 	MAPPING_INVALID,
 	MAPPING_EMPTY,
 	MAPPING_DATA_FIN,
-	MAPPING_DUMMY
+	MAPPING_DUMMY,
+	MAPPING_BAD_CSUM
 };
 
 static void dbg_bad_map(struct mptcp_subflow_context *subflow, u32 ssn)
@@ -958,9 +959,7 @@ static enum mapping_status validate_data_csum(struct sock *ssk, struct sk_buff *
 				 subflow->map_data_csum);
 	if (unlikely(csum)) {
 		MPTCP_INC_STATS(sock_net(ssk), MPTCP_MIB_DATACSUMERR);
-		if (subflow->mp_join || subflow->valid_csum_seen)
-			subflow->send_mp_fail = 1;
-		return subflow->mp_join ? MAPPING_INVALID : MAPPING_DUMMY;
+		return MAPPING_BAD_CSUM;
 	}
 
 	subflow->valid_csum_seen = 1;
@@ -1182,10 +1181,8 @@ static bool subflow_check_data_avail(struct sock *ssk)
 
 		status = get_mapping_status(ssk, msk);
 		trace_subflow_check_data_avail(status, skb_peek(&ssk->sk_receive_queue));
-		if (unlikely(status == MAPPING_INVALID))
-			goto fallback;
-
-		if (unlikely(status == MAPPING_DUMMY))
+		if (unlikely(status == MAPPING_INVALID || status == MAPPING_DUMMY ||
+			     status == MAPPING_BAD_CSUM))
 			goto fallback;
 
 		if (status != MAPPING_OK)
@@ -1227,7 +1224,10 @@ no_data:
 fallback:
 	if (!__mptcp_check_fallback(msk)) {
 		/* RFC 8684 section 3.7. */
-		if (subflow->send_mp_fail) {
+		if (status == MAPPING_BAD_CSUM &&
+		    (subflow->mp_join || subflow->valid_csum_seen)) {
+			subflow->send_mp_fail = 1;
+
 			if (!READ_ONCE(msk->allow_infinite_fallback)) {
 				ssk->sk_err = EBADMSG;
 				tcp_set_state(ssk, TCP_CLOSE);
-- 
GitLab


From 76a13b315709b5b65a7b65caf9ede9a8a38d8930 Mon Sep 17 00:00:00 2001
From: Geliang Tang <geliang.tang@suse.com>
Date: Mon, 27 Jun 2022 18:02:37 -0700
Subject: [PATCH 1336/1731] mptcp: invoke MP_FAIL response when needed

mptcp_mp_fail_no_response shouldn't be invoked on each worker run, it
should be invoked only when MP_FAIL response timeout occurs.

This patch refactors the MP_FAIL response logic.

It leverages the fact that only the MPC/first subflow can gracefully
fail to avoid unneeded subflows traversal: the failing subflow can
be only msk->first.

A new 'fail_tout' field is added to the subflow context to record the
MP_FAIL response timeout and use such field to reliably share the
timeout timer between the MP_FAIL event and the MPTCP socket close
timeout.

Finally, a new ack is generated to send out MP_FAIL notification as soon
as we hit the relevant condition, instead of waiting a possibly unbound
time for the next data packet.

Closes: https://github.com/multipath-tcp/mptcp_net-next/issues/281
Fixes: d9fb797046c5 ("mptcp: Do not traverse the subflow connection list without lock")
Co-developed-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Geliang Tang <geliang.tang@suse.com>
Signed-off-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/mptcp/pm.c       |  9 +++---
 net/mptcp/protocol.c | 77 +++++++++++++++++++++++++++-----------------
 net/mptcp/protocol.h |  3 +-
 net/mptcp/subflow.c  | 38 ++++++++++++++++------
 4 files changed, 82 insertions(+), 45 deletions(-)

diff --git a/net/mptcp/pm.c b/net/mptcp/pm.c
index 91a62b598de4f..45e2a48397b95 100644
--- a/net/mptcp/pm.c
+++ b/net/mptcp/pm.c
@@ -299,22 +299,21 @@ void mptcp_pm_mp_fail_received(struct sock *sk, u64 fail_seq)
 {
 	struct mptcp_subflow_context *subflow = mptcp_subflow_ctx(sk);
 	struct mptcp_sock *msk = mptcp_sk(subflow->conn);
-	struct sock *s = (struct sock *)msk;
 
 	pr_debug("fail_seq=%llu", fail_seq);
 
 	if (!READ_ONCE(msk->allow_infinite_fallback))
 		return;
 
-	if (!READ_ONCE(subflow->mp_fail_response_expect)) {
+	if (!subflow->fail_tout) {
 		pr_debug("send MP_FAIL response and infinite map");
 
 		subflow->send_mp_fail = 1;
 		subflow->send_infinite_map = 1;
-	} else if (!sock_flag(sk, SOCK_DEAD)) {
+		tcp_send_ack(sk);
+	} else {
 		pr_debug("MP_FAIL response received");
-
-		sk_stop_timer(s, &s->sk_timer);
+		WRITE_ONCE(subflow->fail_tout, 0);
 	}
 }
 
diff --git a/net/mptcp/protocol.c b/net/mptcp/protocol.c
index 17e13396024ad..e6fcb61443dd6 100644
--- a/net/mptcp/protocol.c
+++ b/net/mptcp/protocol.c
@@ -500,7 +500,7 @@ static void mptcp_set_timeout(struct sock *sk)
 	__mptcp_set_timeout(sk, tout);
 }
 
-static bool tcp_can_send_ack(const struct sock *ssk)
+static inline bool tcp_can_send_ack(const struct sock *ssk)
 {
 	return !((1 << inet_sk_state_load(ssk)) &
 	       (TCPF_SYN_SENT | TCPF_SYN_RECV | TCPF_TIME_WAIT | TCPF_CLOSE | TCPF_LISTEN));
@@ -2175,21 +2175,6 @@ static void mptcp_retransmit_timer(struct timer_list *t)
 	sock_put(sk);
 }
 
-static struct mptcp_subflow_context *
-mp_fail_response_expect_subflow(struct mptcp_sock *msk)
-{
-	struct mptcp_subflow_context *subflow, *ret = NULL;
-
-	mptcp_for_each_subflow(msk, subflow) {
-		if (READ_ONCE(subflow->mp_fail_response_expect)) {
-			ret = subflow;
-			break;
-		}
-	}
-
-	return ret;
-}
-
 static void mptcp_timeout_timer(struct timer_list *t)
 {
 	struct sock *sk = from_timer(sk, t, sk_timer);
@@ -2518,27 +2503,50 @@ reset_timer:
 		mptcp_reset_timer(sk);
 }
 
+/* schedule the timeout timer for the relevant event: either close timeout
+ * or mp_fail timeout. The close timeout takes precedence on the mp_fail one
+ */
+void mptcp_reset_timeout(struct mptcp_sock *msk, unsigned long fail_tout)
+{
+	struct sock *sk = (struct sock *)msk;
+	unsigned long timeout, close_timeout;
+
+	if (!fail_tout && !sock_flag(sk, SOCK_DEAD))
+		return;
+
+	close_timeout = inet_csk(sk)->icsk_mtup.probe_timestamp - tcp_jiffies32 + jiffies + TCP_TIMEWAIT_LEN;
+
+	/* the close timeout takes precedence on the fail one, and here at least one of
+	 * them is active
+	 */
+	timeout = sock_flag(sk, SOCK_DEAD) ? close_timeout : fail_tout;
+
+	sk_reset_timer(sk, &sk->sk_timer, timeout);
+}
+
 static void mptcp_mp_fail_no_response(struct mptcp_sock *msk)
 {
-	struct mptcp_subflow_context *subflow;
-	struct sock *ssk;
+	struct sock *ssk = msk->first;
 	bool slow;
 
-	subflow = mp_fail_response_expect_subflow(msk);
-	if (subflow) {
-		pr_debug("MP_FAIL doesn't respond, reset the subflow");
+	if (!ssk)
+		return;
 
-		ssk = mptcp_subflow_tcp_sock(subflow);
-		slow = lock_sock_fast(ssk);
-		mptcp_subflow_reset(ssk);
-		unlock_sock_fast(ssk, slow);
-	}
+	pr_debug("MP_FAIL doesn't respond, reset the subflow");
+
+	slow = lock_sock_fast(ssk);
+	mptcp_subflow_reset(ssk);
+	WRITE_ONCE(mptcp_subflow_ctx(ssk)->fail_tout, 0);
+	unlock_sock_fast(ssk, slow);
+
+	mptcp_reset_timeout(msk, 0);
 }
 
 static void mptcp_worker(struct work_struct *work)
 {
 	struct mptcp_sock *msk = container_of(work, struct mptcp_sock, work);
 	struct sock *sk = &msk->sk.icsk_inet.sk;
+	unsigned long fail_tout;
 	int state;
 
 	lock_sock(sk);
@@ -2575,7 +2583,9 @@ static void mptcp_worker(struct work_struct *work)
 	if (test_and_clear_bit(MPTCP_WORK_RTX, &msk->flags))
 		__mptcp_retrans(sk);
 
-	mptcp_mp_fail_no_response(msk);
+	fail_tout = msk->first ? READ_ONCE(mptcp_subflow_ctx(msk->first)->fail_tout) : 0;
+	if (fail_tout && time_after(jiffies, fail_tout))
+		mptcp_mp_fail_no_response(msk);
 
 unlock:
 	release_sock(sk);
@@ -2822,6 +2832,7 @@ static void __mptcp_destroy_sock(struct sock *sk)
 static void mptcp_close(struct sock *sk, long timeout)
 {
 	struct mptcp_subflow_context *subflow;
+	struct mptcp_sock *msk = mptcp_sk(sk);
 	bool do_cancel_work = false;
 
 	lock_sock(sk);
@@ -2840,10 +2851,16 @@ static void mptcp_close(struct sock *sk, long timeout)
 cleanup:
 	/* orphan all the subflows */
 	inet_csk(sk)->icsk_mtup.probe_timestamp = tcp_jiffies32;
-	mptcp_for_each_subflow(mptcp_sk(sk), subflow) {
+	mptcp_for_each_subflow(msk, subflow) {
 		struct sock *ssk = mptcp_subflow_tcp_sock(subflow);
 		bool slow = lock_sock_fast_nested(ssk);
 
+		/* since the close timeout takes precedence on the fail one,
+		 * cancel the latter
+		 */
+		if (ssk == msk->first)
+			subflow->fail_tout = 0;
+
 		sock_orphan(ssk);
 		unlock_sock_fast(ssk, slow);
 	}
@@ -2852,13 +2869,13 @@ cleanup:
 	sock_hold(sk);
 	pr_debug("msk=%p state=%d", sk, sk->sk_state);
 	if (mptcp_sk(sk)->token)
-		mptcp_event(MPTCP_EVENT_CLOSED, mptcp_sk(sk), NULL, GFP_KERNEL);
+		mptcp_event(MPTCP_EVENT_CLOSED, msk, NULL, GFP_KERNEL);
 
 	if (sk->sk_state == TCP_CLOSE) {
 		__mptcp_destroy_sock(sk);
 		do_cancel_work = true;
 	} else {
-		sk_reset_timer(sk, &sk->sk_timer, jiffies + TCP_TIMEWAIT_LEN);
+		mptcp_reset_timeout(msk, 0);
 	}
 	release_sock(sk);
 	if (do_cancel_work)
diff --git a/net/mptcp/protocol.h b/net/mptcp/protocol.h
index 200f89f6d62f6..1d2d717118725 100644
--- a/net/mptcp/protocol.h
+++ b/net/mptcp/protocol.h
@@ -468,7 +468,6 @@ struct mptcp_subflow_context {
 		local_id_valid : 1, /* local_id is correctly initialized */
 		valid_csum_seen : 1;        /* at least one csum validated */
 	enum mptcp_data_avail data_avail;
-	bool	mp_fail_response_expect;
 	u32	remote_nonce;
 	u64	thmac;
 	u32	local_nonce;
@@ -482,6 +481,7 @@ struct mptcp_subflow_context {
 	u8	stale_count;
 
 	long	delegated_status;
+	unsigned long	fail_tout;
 
 	);
 
@@ -662,6 +662,7 @@ void mptcp_get_options(const struct sk_buff *skb,
 
 void mptcp_finish_connect(struct sock *sk);
 void __mptcp_set_connected(struct sock *sk);
+void mptcp_reset_timeout(struct mptcp_sock *msk, unsigned long fail_tout);
 static inline bool mptcp_is_fully_established(struct sock *sk)
 {
 	return inet_sk_state_load(sk) == TCP_ESTABLISHED &&
diff --git a/net/mptcp/subflow.c b/net/mptcp/subflow.c
index 42a7c18a1c245..8dfea6a8a82f6 100644
--- a/net/mptcp/subflow.c
+++ b/net/mptcp/subflow.c
@@ -971,7 +971,6 @@ static enum mapping_status get_mapping_status(struct sock *ssk,
 {
 	struct mptcp_subflow_context *subflow = mptcp_subflow_ctx(ssk);
 	bool csum_reqd = READ_ONCE(msk->csum_enabled);
-	struct sock *sk = (struct sock *)msk;
 	struct mptcp_ext *mpext;
 	struct sk_buff *skb;
 	u16 data_len;
@@ -1013,9 +1012,6 @@ static enum mapping_status get_mapping_status(struct sock *ssk,
 		pr_debug("infinite mapping received");
 		MPTCP_INC_STATS(sock_net(ssk), MPTCP_MIB_INFINITEMAPRX);
 		subflow->map_data_len = 0;
-		if (!sock_flag(ssk, SOCK_DEAD))
-			sk_stop_timer(sk, &sk->sk_timer);
-
 		return MAPPING_INVALID;
 	}
 
@@ -1162,6 +1158,33 @@ static bool subflow_can_fallback(struct mptcp_subflow_context *subflow)
 		return !subflow->fully_established;
 }
 
+static void mptcp_subflow_fail(struct mptcp_sock *msk, struct sock *ssk)
+{
+	struct mptcp_subflow_context *subflow = mptcp_subflow_ctx(ssk);
+	unsigned long fail_tout;
+
+	/* greceful failure can happen only on the MPC subflow */
+	if (WARN_ON_ONCE(ssk != READ_ONCE(msk->first)))
+		return;
+
+	/* since the close timeout take precedence on the fail one,
+	 * no need to start the latter when the first is already set
+	 */
+	if (sock_flag((struct sock *)msk, SOCK_DEAD))
+		return;
+
+	/* we don't need extreme accuracy here, use a zero fail_tout as special
+	 * value meaning no fail timeout at all;
+	 */
+	fail_tout = jiffies + TCP_RTO_MAX;
+	if (!fail_tout)
+		fail_tout = 1;
+	WRITE_ONCE(subflow->fail_tout, fail_tout);
+	tcp_send_ack(ssk);
+
+	mptcp_reset_timeout(msk, subflow->fail_tout);
+}
+
 static bool subflow_check_data_avail(struct sock *ssk)
 {
 	struct mptcp_subflow_context *subflow = mptcp_subflow_ctx(ssk);
@@ -1236,11 +1259,8 @@ fallback:
 				tcp_send_active_reset(ssk, GFP_ATOMIC);
 				while ((skb = skb_peek(&ssk->sk_receive_queue)))
 					sk_eat_skb(ssk, skb);
-			} else if (!sock_flag(ssk, SOCK_DEAD)) {
-				WRITE_ONCE(subflow->mp_fail_response_expect, true);
-				sk_reset_timer((struct sock *)msk,
-					       &((struct sock *)msk)->sk_timer,
-					       jiffies + TCP_RTO_MAX);
+			} else {
+				mptcp_subflow_fail(msk, ssk);
 			}
 			WRITE_ONCE(subflow->data_avail, MPTCP_SUBFLOW_NODATA);
 			return true;
-- 
GitLab


From d51991e2e31477853e5b9c1005ac617707077286 Mon Sep 17 00:00:00 2001
From: Paolo Abeni <pabeni@redhat.com>
Date: Mon, 27 Jun 2022 18:02:38 -0700
Subject: [PATCH 1337/1731] mptcp: fix shutdown vs fallback race

If the MPTCP socket shutdown happens before a fallback
to TCP, and all the pending data have been already spooled,
we never close the TCP connection.

Address the issue explicitly checking for critical condition
at fallback time.

Fixes: 1e39e5a32ad7 ("mptcp: infinite mapping sending")
Fixes: 0348c690ed37 ("mptcp: add the fallback check")
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/mptcp/options.c  |  2 +-
 net/mptcp/protocol.c |  2 +-
 net/mptcp/protocol.h | 19 ++++++++++++++++---
 net/mptcp/subflow.c  |  2 +-
 4 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/net/mptcp/options.c b/net/mptcp/options.c
index 2a6351d55a7d9..aead331866a0c 100644
--- a/net/mptcp/options.c
+++ b/net/mptcp/options.c
@@ -967,7 +967,7 @@ static bool check_fully_established(struct mptcp_sock *msk, struct sock *ssk,
 			goto reset;
 		subflow->mp_capable = 0;
 		pr_fallback(msk);
-		__mptcp_do_fallback(msk);
+		mptcp_do_fallback(ssk);
 		return false;
 	}
 
diff --git a/net/mptcp/protocol.c b/net/mptcp/protocol.c
index e6fcb61443dd6..e63bc2bb7fff0 100644
--- a/net/mptcp/protocol.c
+++ b/net/mptcp/protocol.c
@@ -1245,7 +1245,7 @@ static void mptcp_update_infinite_map(struct mptcp_sock *msk,
 	MPTCP_INC_STATS(sock_net(ssk), MPTCP_MIB_INFINITEMAPTX);
 	mptcp_subflow_ctx(ssk)->send_infinite_map = 0;
 	pr_fallback(msk);
-	__mptcp_do_fallback(msk);
+	mptcp_do_fallback(ssk);
 }
 
 static int mptcp_sendmsg_frag(struct sock *sk, struct sock *ssk,
diff --git a/net/mptcp/protocol.h b/net/mptcp/protocol.h
index 1d2d717118725..9860179bfd5ed 100644
--- a/net/mptcp/protocol.h
+++ b/net/mptcp/protocol.h
@@ -927,12 +927,25 @@ static inline void __mptcp_do_fallback(struct mptcp_sock *msk)
 	set_bit(MPTCP_FALLBACK_DONE, &msk->flags);
 }
 
-static inline void mptcp_do_fallback(struct sock *sk)
+static inline void mptcp_do_fallback(struct sock *ssk)
 {
-	struct mptcp_subflow_context *subflow = mptcp_subflow_ctx(sk);
-	struct mptcp_sock *msk = mptcp_sk(subflow->conn);
+	struct mptcp_subflow_context *subflow = mptcp_subflow_ctx(ssk);
+	struct sock *sk = subflow->conn;
+	struct mptcp_sock *msk;
 
+	msk = mptcp_sk(sk);
 	__mptcp_do_fallback(msk);
+	if (READ_ONCE(msk->snd_data_fin_enable) && !(ssk->sk_shutdown & SEND_SHUTDOWN)) {
+		gfp_t saved_allocation = ssk->sk_allocation;
+
+		/* we are in a atomic (BH) scope, override ssk default for data
+		 * fin allocation
+		 */
+		ssk->sk_allocation = GFP_ATOMIC;
+		ssk->sk_shutdown |= SEND_SHUTDOWN;
+		tcp_shutdown(ssk, SEND_SHUTDOWN);
+		ssk->sk_allocation = saved_allocation;
+	}
 }
 
 #define pr_fallback(a) pr_debug("%s:fallback to TCP (msk=%p)", __func__, a)
diff --git a/net/mptcp/subflow.c b/net/mptcp/subflow.c
index 8dfea6a8a82f6..b34b96fb742f9 100644
--- a/net/mptcp/subflow.c
+++ b/net/mptcp/subflow.c
@@ -1279,7 +1279,7 @@ fallback:
 			return false;
 		}
 
-		__mptcp_do_fallback(msk);
+		mptcp_do_fallback(ssk);
 	}
 
 	skb = skb_peek(&ssk->sk_receive_queue);
-- 
GitLab


From f745a3ebdfb9041d3a55e66eb345895cd8ecc90c Mon Sep 17 00:00:00 2001
From: Paolo Abeni <pabeni@redhat.com>
Date: Mon, 27 Jun 2022 18:02:39 -0700
Subject: [PATCH 1338/1731] mptcp: consistent map handling on failure

When the MPTCP receive path reach a non fatal fall-back condition, e.g.
when the MPC sockets must fall-back to TCP, the existing code is a little
self-inconsistent: it reports that new data is available - return true -
but sets the MPC flag to the opposite value.

As the consequence read operations in some exceptional scenario may block
unexpectedly.

Address the issue setting the correct MPC read status. Additionally avoid
some code duplication in the fatal fall-back scenario.

Fixes: 9c81be0dbc89 ("mptcp: add MP_FAIL response support")
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/mptcp/subflow.c | 19 +++++++++----------
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/net/mptcp/subflow.c b/net/mptcp/subflow.c
index b34b96fb742f9..03862103665d6 100644
--- a/net/mptcp/subflow.c
+++ b/net/mptcp/subflow.c
@@ -1252,17 +1252,12 @@ fallback:
 			subflow->send_mp_fail = 1;
 
 			if (!READ_ONCE(msk->allow_infinite_fallback)) {
-				ssk->sk_err = EBADMSG;
-				tcp_set_state(ssk, TCP_CLOSE);
 				subflow->reset_transient = 0;
 				subflow->reset_reason = MPTCP_RST_EMIDDLEBOX;
-				tcp_send_active_reset(ssk, GFP_ATOMIC);
-				while ((skb = skb_peek(&ssk->sk_receive_queue)))
-					sk_eat_skb(ssk, skb);
-			} else {
-				mptcp_subflow_fail(msk, ssk);
+				goto reset;
 			}
-			WRITE_ONCE(subflow->data_avail, MPTCP_SUBFLOW_NODATA);
+			mptcp_subflow_fail(msk, ssk);
+			WRITE_ONCE(subflow->data_avail, MPTCP_SUBFLOW_DATA_AVAIL);
 			return true;
 		}
 
@@ -1270,10 +1265,14 @@ fallback:
 			/* fatal protocol error, close the socket.
 			 * subflow_error_report() will introduce the appropriate barriers
 			 */
-			ssk->sk_err = EBADMSG;
-			tcp_set_state(ssk, TCP_CLOSE);
 			subflow->reset_transient = 0;
 			subflow->reset_reason = MPTCP_RST_EMPTCP;
+
+reset:
+			ssk->sk_err = EBADMSG;
+			tcp_set_state(ssk, TCP_CLOSE);
+			while ((skb = skb_peek(&ssk->sk_receive_queue)))
+				sk_eat_skb(ssk, skb);
 			tcp_send_active_reset(ssk, GFP_ATOMIC);
 			WRITE_ONCE(subflow->data_avail, MPTCP_SUBFLOW_NODATA);
 			return false;
-- 
GitLab


From 6aeed9045071f2252ff4e98fc13d1e304f33e5b0 Mon Sep 17 00:00:00 2001
From: Paolo Abeni <pabeni@redhat.com>
Date: Mon, 27 Jun 2022 18:02:40 -0700
Subject: [PATCH 1339/1731] mptcp: fix race on unaccepted mptcp sockets

When the listener socket owning the relevant request is closed,
it frees the unaccepted subflows and that causes later deletion
of the paired MPTCP sockets.

The mptcp socket's worker can run in the time interval between such delete
operations. When that happens, any access to msk->first will cause an UaF
access, as the subflow cleanup did not cleared such field in the mptcp
socket.

Address the issue explicitly traversing the listener socket accept
queue at close time and performing the needed cleanup on the pending
msk.

Note that the locking is a bit tricky, as we need to acquire the msk
socket lock, while still owning the subflow socket one.

Fixes: 86e39e04482b ("mptcp: keep track of local endpoint still available for each msk")
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/mptcp/protocol.c |  5 +++++
 net/mptcp/protocol.h |  2 ++
 net/mptcp/subflow.c  | 52 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 59 insertions(+)

diff --git a/net/mptcp/protocol.c b/net/mptcp/protocol.c
index e63bc2bb7fff0..e475212f2618b 100644
--- a/net/mptcp/protocol.c
+++ b/net/mptcp/protocol.c
@@ -2331,6 +2331,11 @@ static void __mptcp_close_ssk(struct sock *sk, struct sock *ssk,
 		kfree_rcu(subflow, rcu);
 	} else {
 		/* otherwise tcp will dispose of the ssk and subflow ctx */
+		if (ssk->sk_state == TCP_LISTEN) {
+			tcp_set_state(ssk, TCP_CLOSE);
+			mptcp_subflow_queue_clean(ssk);
+			inet_csk_listen_stop(ssk);
+		}
 		__tcp_close(ssk, 0);
 
 		/* close acquired an extra ref */
diff --git a/net/mptcp/protocol.h b/net/mptcp/protocol.h
index 9860179bfd5ed..c14d70c036d0e 100644
--- a/net/mptcp/protocol.h
+++ b/net/mptcp/protocol.h
@@ -306,6 +306,7 @@ struct mptcp_sock {
 
 	u32 setsockopt_seq;
 	char		ca_name[TCP_CA_NAME_MAX];
+	struct mptcp_sock	*dl_next;
 };
 
 #define mptcp_data_lock(sk) spin_lock_bh(&(sk)->sk_lock.slock)
@@ -608,6 +609,7 @@ void mptcp_close_ssk(struct sock *sk, struct sock *ssk,
 		     struct mptcp_subflow_context *subflow);
 void mptcp_subflow_send_ack(struct sock *ssk);
 void mptcp_subflow_reset(struct sock *ssk);
+void mptcp_subflow_queue_clean(struct sock *ssk);
 void mptcp_sock_graft(struct sock *sk, struct socket *parent);
 struct socket *__mptcp_nmpc_socket(const struct mptcp_sock *msk);
 
diff --git a/net/mptcp/subflow.c b/net/mptcp/subflow.c
index 03862103665d6..63e8892ec807d 100644
--- a/net/mptcp/subflow.c
+++ b/net/mptcp/subflow.c
@@ -1723,6 +1723,58 @@ static void subflow_state_change(struct sock *sk)
 	}
 }
 
+void mptcp_subflow_queue_clean(struct sock *listener_ssk)
+{
+	struct request_sock_queue *queue = &inet_csk(listener_ssk)->icsk_accept_queue;
+	struct mptcp_sock *msk, *next, *head = NULL;
+	struct request_sock *req;
+
+	/* build a list of all unaccepted mptcp sockets */
+	spin_lock_bh(&queue->rskq_lock);
+	for (req = queue->rskq_accept_head; req; req = req->dl_next) {
+		struct mptcp_subflow_context *subflow;
+		struct sock *ssk = req->sk;
+		struct mptcp_sock *msk;
+
+		if (!sk_is_mptcp(ssk))
+			continue;
+
+		subflow = mptcp_subflow_ctx(ssk);
+		if (!subflow || !subflow->conn)
+			continue;
+
+		/* skip if already in list */
+		msk = mptcp_sk(subflow->conn);
+		if (msk->dl_next || msk == head)
+			continue;
+
+		msk->dl_next = head;
+		head = msk;
+	}
+	spin_unlock_bh(&queue->rskq_lock);
+	if (!head)
+		return;
+
+	/* can't acquire the msk socket lock under the subflow one,
+	 * or will cause ABBA deadlock
+	 */
+	release_sock(listener_ssk);
+
+	for (msk = head; msk; msk = next) {
+		struct sock *sk = (struct sock *)msk;
+		bool slow;
+
+		slow = lock_sock_fast_nested(sk);
+		next = msk->dl_next;
+		msk->first = NULL;
+		msk->dl_next = NULL;
+		unlock_sock_fast(sk, slow);
+	}
+
+	/* we are still under the listener msk socket lock */
+	lock_sock_nested(listener_ssk, SINGLE_DEPTH_NESTING);
+}
+
 static int subflow_ulp_init(struct sock *sk)
 {
 	struct inet_connection_sock *icsk = inet_csk(sk);
-- 
GitLab


From 42fb6cddec3b306c9f6ef136b6438e0de1836431 Mon Sep 17 00:00:00 2001
From: Paolo Abeni <pabeni@redhat.com>
Date: Mon, 27 Jun 2022 18:02:41 -0700
Subject: [PATCH 1340/1731] selftests: mptcp: more stable diag tests

The mentioned test-case still use an hard-coded-len sleep to
wait for a relative large number of connection to be established.

On very slow VM and with debug build such timeout could be exceeded,
causing failures in our CI.

Address the issue polling for the expected condition several times,
up to an unreasonable high amount of time. On reasonably fast system
the self-tests will be faster then before, on very slow one we will
still catch the correct condition.

Fixes: df62f2ec3df6 ("selftests/mptcp: add diag interface tests")
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 tools/testing/selftests/net/mptcp/diag.sh | 48 +++++++++++++++++++----
 1 file changed, 40 insertions(+), 8 deletions(-)

diff --git a/tools/testing/selftests/net/mptcp/diag.sh b/tools/testing/selftests/net/mptcp/diag.sh
index 9dd43d7d957b9..515859a5168bc 100755
--- a/tools/testing/selftests/net/mptcp/diag.sh
+++ b/tools/testing/selftests/net/mptcp/diag.sh
@@ -61,6 +61,39 @@ chk_msk_nr()
 	__chk_nr "grep -c token:" $*
 }
 
+wait_msk_nr()
+{
+	local condition="grep -c token:"
+	local expected=$1
+	local timeout=20
+	local msg nr
+	local max=0
+	local i=0
+
+	shift 1
+	msg=$*
+
+	while [ $i -lt $timeout ]; do
+		nr=$(ss -inmHMN $ns | $condition)
+		[ $nr == $expected ] && break;
+		[ $nr -gt $max ] && max=$nr
+		i=$((i + 1))
+		sleep 1
+	done
+
+	printf "%-50s" "$msg"
+	if [ $i -ge $timeout ]; then
+		echo "[ fail ] timeout while expecting $expected max $max last $nr"
+		ret=$test_cnt
+	elif [ $nr != $expected ]; then
+		echo "[ fail ] expected $expected found $nr"
+		ret=$test_cnt
+	else
+		echo "[  ok  ]"
+	fi
+	test_cnt=$((test_cnt+1))
+}
+
 chk_msk_fallback_nr()
 {
 		__chk_nr "grep -c fallback" $*
@@ -146,7 +179,7 @@ ip -n $ns link set dev lo up
 echo "a" | \
 	timeout ${timeout_test} \
 		ip netns exec $ns \
-			./mptcp_connect -p 10000 -l -t ${timeout_poll} \
+			./mptcp_connect -p 10000 -l -t ${timeout_poll} -w 20 \
 				0.0.0.0 >/dev/null &
 wait_local_port_listen $ns 10000
 chk_msk_nr 0 "no msk on netns creation"
@@ -155,7 +188,7 @@ chk_msk_listen 10000
 echo "b" | \
 	timeout ${timeout_test} \
 		ip netns exec $ns \
-			./mptcp_connect -p 10000 -r 0 -t ${timeout_poll} \
+			./mptcp_connect -p 10000 -r 0 -t ${timeout_poll} -w 20 \
 				127.0.0.1 >/dev/null &
 wait_connected $ns 10000
 chk_msk_nr 2 "after MPC handshake "
@@ -167,13 +200,13 @@ flush_pids
 echo "a" | \
 	timeout ${timeout_test} \
 		ip netns exec $ns \
-			./mptcp_connect -p 10001 -l -s TCP -t ${timeout_poll} \
+			./mptcp_connect -p 10001 -l -s TCP -t ${timeout_poll} -w 20 \
 				0.0.0.0 >/dev/null &
 wait_local_port_listen $ns 10001
 echo "b" | \
 	timeout ${timeout_test} \
 		ip netns exec $ns \
-			./mptcp_connect -p 10001 -r 0 -t ${timeout_poll} \
+			./mptcp_connect -p 10001 -r 0 -t ${timeout_poll} -w 20 \
 				127.0.0.1 >/dev/null &
 wait_connected $ns 10001
 chk_msk_fallback_nr 1 "check fallback"
@@ -184,7 +217,7 @@ for I in `seq 1 $NR_CLIENTS`; do
 	echo "a" | \
 		timeout ${timeout_test} \
 			ip netns exec $ns \
-				./mptcp_connect -p $((I+10001)) -l -w 10 \
+				./mptcp_connect -p $((I+10001)) -l -w 20 \
 					-t ${timeout_poll} 0.0.0.0 >/dev/null &
 done
 wait_local_port_listen $ns $((NR_CLIENTS + 10001))
@@ -193,12 +226,11 @@ for I in `seq 1 $NR_CLIENTS`; do
 	echo "b" | \
 		timeout ${timeout_test} \
 			ip netns exec $ns \
-				./mptcp_connect -p $((I+10001)) -w 10 \
+				./mptcp_connect -p $((I+10001)) -w 20 \
 					-t ${timeout_poll} 127.0.0.1 >/dev/null &
 done
-sleep 1.5
 
-chk_msk_nr $((NR_CLIENTS*2)) "many msk socket present"
+wait_msk_nr $((NR_CLIENTS*2)) "many msk socket present"
 flush_pids
 
 exit $ret
-- 
GitLab


From 06e445f740c1a0fe5d16b3dff8a4ef18e124e54e Mon Sep 17 00:00:00 2001
From: Ossama Othman <ossama.othman@intel.com>
Date: Mon, 27 Jun 2022 18:02:42 -0700
Subject: [PATCH 1341/1731] mptcp: fix conflict with <netinet/in.h>

Including <linux/mptcp.h> before the C library <netinet/in.h> header
causes symbol redefinition errors at compile-time due to duplicate
declarations and definitions in the <linux/in.h> header included by
<linux/mptcp.h>.

Explicitly include <netinet/in.h> before <linux/in.h> in
<linux/mptcp.h> when __KERNEL__ is not defined so that the C library
compatibility logic in <linux/libc-compat.h> is enabled when including
<linux/mptcp.h> in user space code.

Fixes: c11c5906bc0a ("mptcp: add MPTCP_SUBFLOW_ADDRS getsockopt support")
Signed-off-by: Ossama Othman <ossama.othman@intel.com>
Signed-off-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 include/uapi/linux/mptcp.h | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/include/uapi/linux/mptcp.h b/include/uapi/linux/mptcp.h
index 9219635899042..dfe19bf13f4c8 100644
--- a/include/uapi/linux/mptcp.h
+++ b/include/uapi/linux/mptcp.h
@@ -2,16 +2,17 @@
 #ifndef _UAPI_MPTCP_H
 #define _UAPI_MPTCP_H
 
+#ifndef __KERNEL__
+#include <netinet/in.h>		/* for sockaddr_in and sockaddr_in6	*/
+#include <sys/socket.h>		/* for struct sockaddr			*/
+#endif
+
 #include <linux/const.h>
 #include <linux/types.h>
 #include <linux/in.h>		/* for sockaddr_in			*/
 #include <linux/in6.h>		/* for sockaddr_in6			*/
 #include <linux/socket.h>	/* for sockaddr_storage and sa_family	*/
 
-#ifndef __KERNEL__
-#include <sys/socket.h>		/* for struct sockaddr			*/
-#endif
-
 #define MPTCP_SUBFLOW_FLAG_MCAP_REM		_BITUL(0)
 #define MPTCP_SUBFLOW_FLAG_MCAP_LOC		_BITUL(1)
 #define MPTCP_SUBFLOW_FLAG_JOIN_REM		_BITUL(2)
-- 
GitLab


From fd37c2ecb21f7aee04ccca5f561469f07d00063c Mon Sep 17 00:00:00 2001
From: Mat Martineau <mathew.j.martineau@linux.intel.com>
Date: Mon, 27 Jun 2022 18:02:43 -0700
Subject: [PATCH 1342/1731] selftests: mptcp: Initialize variables to quiet gcc
 12 warnings

In a few MPTCP selftest tools, gcc 12 complains that the 'sock' variable
might be used uninitialized. This is a false positive because the only
code path that could lead to uninitialized access is where getaddrinfo()
fails, but the local xgetaddrinfo() wrapper exits if such a failure
occurs.

Initialize the 'sock' variable anyway to allow the tools to build with
gcc 12.

Fixes: 048d19d444be ("mptcp: add basic kselftest for mptcp")
Acked-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 tools/testing/selftests/net/mptcp/mptcp_connect.c | 2 +-
 tools/testing/selftests/net/mptcp/mptcp_inq.c     | 2 +-
 tools/testing/selftests/net/mptcp/mptcp_sockopt.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/tools/testing/selftests/net/mptcp/mptcp_connect.c b/tools/testing/selftests/net/mptcp/mptcp_connect.c
index 8628aa61b7634..e2ea6c126c99f 100644
--- a/tools/testing/selftests/net/mptcp/mptcp_connect.c
+++ b/tools/testing/selftests/net/mptcp/mptcp_connect.c
@@ -265,7 +265,7 @@ static void sock_test_tcpulp(int sock, int proto, unsigned int line)
 static int sock_listen_mptcp(const char * const listenaddr,
 			     const char * const port)
 {
-	int sock;
+	int sock = -1;
 	struct addrinfo hints = {
 		.ai_protocol = IPPROTO_TCP,
 		.ai_socktype = SOCK_STREAM,
diff --git a/tools/testing/selftests/net/mptcp/mptcp_inq.c b/tools/testing/selftests/net/mptcp/mptcp_inq.c
index 29f75e2a11168..8672d898f8cda 100644
--- a/tools/testing/selftests/net/mptcp/mptcp_inq.c
+++ b/tools/testing/selftests/net/mptcp/mptcp_inq.c
@@ -88,7 +88,7 @@ static void xgetaddrinfo(const char *node, const char *service,
 static int sock_listen_mptcp(const char * const listenaddr,
 			     const char * const port)
 {
-	int sock;
+	int sock = -1;
 	struct addrinfo hints = {
 		.ai_protocol = IPPROTO_TCP,
 		.ai_socktype = SOCK_STREAM,
diff --git a/tools/testing/selftests/net/mptcp/mptcp_sockopt.c b/tools/testing/selftests/net/mptcp/mptcp_sockopt.c
index ac9a4d9c17646..ae61f39556ca8 100644
--- a/tools/testing/selftests/net/mptcp/mptcp_sockopt.c
+++ b/tools/testing/selftests/net/mptcp/mptcp_sockopt.c
@@ -136,7 +136,7 @@ static void xgetaddrinfo(const char *node, const char *service,
 static int sock_listen_mptcp(const char * const listenaddr,
 			     const char * const port)
 {
-	int sock;
+	int sock = -1;
 	struct addrinfo hints = {
 		.ai_protocol = IPPROTO_TCP,
 		.ai_socktype = SOCK_STREAM,
-- 
GitLab


From adabdd8f6acabc0c3fdbba2e7f5a2edd9c5ef22d Mon Sep 17 00:00:00 2001
From: katrinzhou <katrinzhou@tencent.com>
Date: Tue, 28 Jun 2022 11:50:30 +0800
Subject: [PATCH 1343/1731] ipv6/sit: fix ipip6_tunnel_get_prl return value

When kcalloc fails, ipip6_tunnel_get_prl() should return -ENOMEM.
Move the position of label "out" to return correctly.

Addresses-Coverity: ("Unused value")
Fixes: 300aaeeaab5f ("[IPV6] SIT: Add SIOCGETPRL ioctl to get/dump PRL.")
Signed-off-by: katrinzhou <katrinzhou@tencent.com>
Reviewed-by: Eric Dumazet<edumazet@google.com>
Reviewed-by: David Ahern <dsahern@kernel.org>
Link: https://lore.kernel.org/r/20220628035030.1039171-1-zys.zljxml@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/ipv6/sit.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/net/ipv6/sit.c b/net/ipv6/sit.c
index c0b138c209925..6bcd5e419a083 100644
--- a/net/ipv6/sit.c
+++ b/net/ipv6/sit.c
@@ -323,8 +323,6 @@ static int ipip6_tunnel_get_prl(struct net_device *dev, struct ip_tunnel_prl __u
 		kcalloc(cmax, sizeof(*kp), GFP_KERNEL_ACCOUNT | __GFP_NOWARN) :
 		NULL;
 
-	rcu_read_lock();
-
 	ca = min(t->prl_count, cmax);
 
 	if (!kp) {
@@ -341,7 +339,7 @@ static int ipip6_tunnel_get_prl(struct net_device *dev, struct ip_tunnel_prl __u
 		}
 	}
 
-	c = 0;
+	rcu_read_lock();
 	for_each_prl_rcu(t->prl) {
 		if (c >= cmax)
 			break;
@@ -353,7 +351,7 @@ static int ipip6_tunnel_get_prl(struct net_device *dev, struct ip_tunnel_prl __u
 		if (kprl.addr != htonl(INADDR_ANY))
 			break;
 	}
-out:
+
 	rcu_read_unlock();
 
 	len = sizeof(*kp) * c;
@@ -362,7 +360,7 @@ out:
 		ret = -EFAULT;
 
 	kfree(kp);
-
+out:
 	return ret;
 }
 
-- 
GitLab


From 53ad46169fe2996fe1b623ba6c9c4fa33847876f Mon Sep 17 00:00:00 2001
From: YueHaibing <yuehaibing@huawei.com>
Date: Tue, 28 Jun 2022 11:31:34 +0800
Subject: [PATCH 1344/1731] net: ipv6: unexport __init-annotated
 seg6_hmac_net_init()

As of commit 5801f064e351 ("net: ipv6: unexport __init-annotated seg6_hmac_init()"),
EXPORT_SYMBOL and __init is a bad combination because the .init.text
section is freed up after the initialization. Hence, modules cannot
use symbols annotated __init. The access to a freed symbol may end up
with kernel panic.

This remove the EXPORT_SYMBOL to fix modpost warning:

WARNING: modpost: vmlinux.o(___ksymtab+seg6_hmac_net_init+0x0): Section mismatch in reference from the variable __ksymtab_seg6_hmac_net_init to the function .init.text:seg6_hmac_net_init()
The symbol seg6_hmac_net_init is exported and annotated __init
Fix this by removing the __init annotation of seg6_hmac_net_init or drop the export.

Fixes: bf355b8d2c30 ("ipv6: sr: add core files for SR HMAC support")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lore.kernel.org/r/20220628033134.21088-1-yuehaibing@huawei.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/ipv6/seg6_hmac.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/net/ipv6/seg6_hmac.c b/net/ipv6/seg6_hmac.c
index 6de01185cc68f..d43c50a7310d6 100644
--- a/net/ipv6/seg6_hmac.c
+++ b/net/ipv6/seg6_hmac.c
@@ -406,7 +406,6 @@ int __net_init seg6_hmac_net_init(struct net *net)
 
 	return rhashtable_init(&sdata->hmac_infos, &rht_params);
 }
-EXPORT_SYMBOL(seg6_hmac_net_init);
 
 void seg6_hmac_exit(void)
 {
-- 
GitLab


From 5a478a653b4cca148d5c89832f007ec0809d7e6d Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Mon, 27 Jun 2022 14:40:48 +0200
Subject: [PATCH 1345/1731] nfc: nfcmrvl: Fix irq_of_parse_and_map() return
 value

The irq_of_parse_and_map() returns 0 on failure, not a negative ERRNO.

Reported-by: Lv Ruyi <lv.ruyi@zte.com.cn>
Fixes: caf6e49bf6d0 ("NFC: nfcmrvl: add spi driver")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220627124048.296253-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/nfc/nfcmrvl/i2c.c | 6 +++---
 drivers/nfc/nfcmrvl/spi.c | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/nfc/nfcmrvl/i2c.c b/drivers/nfc/nfcmrvl/i2c.c
index ceef81d93ac99..01329b91d59d5 100644
--- a/drivers/nfc/nfcmrvl/i2c.c
+++ b/drivers/nfc/nfcmrvl/i2c.c
@@ -167,9 +167,9 @@ static int nfcmrvl_i2c_parse_dt(struct device_node *node,
 		pdata->irq_polarity = IRQF_TRIGGER_RISING;
 
 	ret = irq_of_parse_and_map(node, 0);
-	if (ret < 0) {
-		pr_err("Unable to get irq, error: %d\n", ret);
-		return ret;
+	if (!ret) {
+		pr_err("Unable to get irq\n");
+		return -EINVAL;
 	}
 	pdata->irq = ret;
 
diff --git a/drivers/nfc/nfcmrvl/spi.c b/drivers/nfc/nfcmrvl/spi.c
index a38e2fcdfd39f..ad3359a4942c7 100644
--- a/drivers/nfc/nfcmrvl/spi.c
+++ b/drivers/nfc/nfcmrvl/spi.c
@@ -115,9 +115,9 @@ static int nfcmrvl_spi_parse_dt(struct device_node *node,
 	}
 
 	ret = irq_of_parse_and_map(node, 0);
-	if (ret < 0) {
-		pr_err("Unable to get irq, error: %d\n", ret);
-		return ret;
+	if (!ret) {
+		pr_err("Unable to get irq\n");
+		return -EINVAL;
 	}
 	pdata->irq = ret;
 
-- 
GitLab


From e35f5718903b093be4b1d3833aa8a32f864a3ef1 Mon Sep 17 00:00:00 2001
From: Vishal Verma <vishal.l.verma@intel.com>
Date: Tue, 28 Jun 2022 16:01:09 -0600
Subject: [PATCH 1346/1731] cxl/mbox: Fix missing variable payload checks in
 cmd size validation

The conversion of command sizes to unsigned missed a couple of checks
against variable size payloads during command validation, which made all
variable payload commands unconditionally fail. Add the checks back using
the new CXL_VARIABLE_PAYLOAD scheme.

Fixes: 26f89535a5bb ("cxl/mbox: Use type __u32 for mailbox payload sizes")
Cc: <stable@vger.kernel.org>
Cc: Ira Weiny <ira.weiny@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Alison Schofield <alison.schofield@intel.com>
Reported-by: Abhi Cs <abhi.cs@intel.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
Link: https://lore.kernel.org/r/20220628220109.633564-1-vishal.l.verma@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
 drivers/cxl/core/mbox.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
index 54f434733b562..cbf23beebebef 100644
--- a/drivers/cxl/core/mbox.c
+++ b/drivers/cxl/core/mbox.c
@@ -355,11 +355,13 @@ static int cxl_to_mem_cmd(struct cxl_mem_command *mem_cmd,
 		return -EBUSY;
 
 	/* Check the input buffer is the expected size */
-	if (info->size_in != send_cmd->in.size)
+	if ((info->size_in != CXL_VARIABLE_PAYLOAD) &&
+	    (info->size_in != send_cmd->in.size))
 		return -ENOMEM;
 
 	/* Check the output buffer is at least large enough */
-	if (send_cmd->out.size < info->size_out)
+	if ((info->size_out != CXL_VARIABLE_PAYLOAD) &&
+	    (send_cmd->out.size < info->size_out))
 		return -ENOMEM;
 
 	*mem_cmd = (struct cxl_mem_command) {
-- 
GitLab


From 9e121040e54abef9ed5542e5fdfa87911cd96204 Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas <javierm@redhat.com>
Date: Tue, 7 Jun 2022 20:23:34 +0200
Subject: [PATCH 1347/1731] firmware: sysfb: Make sysfb_create_simplefb()
 return a pdev pointer

This function just returned 0 on success or an errno code on error, but it
could be useful for sysfb_init() callers to have a pointer to the device.

Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20220607182338.344270-2-javierm@redhat.com
---
 drivers/firmware/sysfb.c          |  4 ++--
 drivers/firmware/sysfb_simplefb.c | 16 ++++++++--------
 include/linux/sysfb.h             | 10 +++++-----
 3 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/firmware/sysfb.c b/drivers/firmware/sysfb.c
index 2bfbb05f7d896..b032f40a92de0 100644
--- a/drivers/firmware/sysfb.c
+++ b/drivers/firmware/sysfb.c
@@ -46,8 +46,8 @@ static __init int sysfb_init(void)
 	/* try to create a simple-framebuffer device */
 	compatible = sysfb_parse_mode(si, &mode);
 	if (compatible) {
-		ret = sysfb_create_simplefb(si, &mode);
-		if (!ret)
+		pd = sysfb_create_simplefb(si, &mode);
+		if (!IS_ERR(pd))
 			return 0;
 	}
 
diff --git a/drivers/firmware/sysfb_simplefb.c b/drivers/firmware/sysfb_simplefb.c
index bda8712bfd8c5..a353e27f83f54 100644
--- a/drivers/firmware/sysfb_simplefb.c
+++ b/drivers/firmware/sysfb_simplefb.c
@@ -57,8 +57,8 @@ __init bool sysfb_parse_mode(const struct screen_info *si,
 	return false;
 }
 
-__init int sysfb_create_simplefb(const struct screen_info *si,
-				 const struct simplefb_platform_data *mode)
+__init struct platform_device *sysfb_create_simplefb(const struct screen_info *si,
+						     const struct simplefb_platform_data *mode)
 {
 	struct platform_device *pd;
 	struct resource res;
@@ -76,7 +76,7 @@ __init int sysfb_create_simplefb(const struct screen_info *si,
 		base |= (u64)si->ext_lfb_base << 32;
 	if (!base || (u64)(resource_size_t)base != base) {
 		printk(KERN_DEBUG "sysfb: inaccessible VRAM base\n");
-		return -EINVAL;
+		return ERR_PTR(-EINVAL);
 	}
 
 	/*
@@ -93,7 +93,7 @@ __init int sysfb_create_simplefb(const struct screen_info *si,
 	length = mode->height * mode->stride;
 	if (length > size) {
 		printk(KERN_WARNING "sysfb: VRAM smaller than advertised\n");
-		return -EINVAL;
+		return ERR_PTR(-EINVAL);
 	}
 	length = PAGE_ALIGN(length);
 
@@ -104,11 +104,11 @@ __init int sysfb_create_simplefb(const struct screen_info *si,
 	res.start = base;
 	res.end = res.start + length - 1;
 	if (res.end <= res.start)
-		return -EINVAL;
+		return ERR_PTR(-EINVAL);
 
 	pd = platform_device_alloc("simple-framebuffer", 0);
 	if (!pd)
-		return -ENOMEM;
+		return ERR_PTR(-ENOMEM);
 
 	sysfb_apply_efi_quirks(pd);
 
@@ -124,10 +124,10 @@ __init int sysfb_create_simplefb(const struct screen_info *si,
 	if (ret)
 		goto err_put_device;
 
-	return 0;
+	return pd;
 
 err_put_device:
 	platform_device_put(pd);
 
-	return ret;
+	return ERR_PTR(ret);
 }
diff --git a/include/linux/sysfb.h b/include/linux/sysfb.h
index b0dcfa26d07bd..708152e9037bf 100644
--- a/include/linux/sysfb.h
+++ b/include/linux/sysfb.h
@@ -72,8 +72,8 @@ static inline void sysfb_apply_efi_quirks(struct platform_device *pd)
 
 bool sysfb_parse_mode(const struct screen_info *si,
 		      struct simplefb_platform_data *mode);
-int sysfb_create_simplefb(const struct screen_info *si,
-			  const struct simplefb_platform_data *mode);
+struct platform_device *sysfb_create_simplefb(const struct screen_info *si,
+					      const struct simplefb_platform_data *mode);
 
 #else /* CONFIG_SYSFB_SIMPLE */
 
@@ -83,10 +83,10 @@ static inline bool sysfb_parse_mode(const struct screen_info *si,
 	return false;
 }
 
-static inline int sysfb_create_simplefb(const struct screen_info *si,
-					 const struct simplefb_platform_data *mode)
+static inline struct platform_device *sysfb_create_simplefb(const struct screen_info *si,
+							    const struct simplefb_platform_data *mode)
 {
-	return -EINVAL;
+	return ERR_PTR(-EINVAL);
 }
 
 #endif /* CONFIG_SYSFB_SIMPLE */
-- 
GitLab


From bde376e9de3c0bc55eedc8956b0f114c05531595 Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas <javierm@redhat.com>
Date: Tue, 7 Jun 2022 20:23:35 +0200
Subject: [PATCH 1348/1731] firmware: sysfb: Add sysfb_disable() helper
 function

This can be used by subsystems to unregister a platform device registered
by sysfb and also to disable future platform device registration in sysfb.

Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20220607182338.344270-3-javierm@redhat.com
---
 .../driver-api/firmware/other_interfaces.rst  |  6 +++
 drivers/firmware/sysfb.c                      | 54 ++++++++++++++++---
 include/linux/sysfb.h                         | 12 +++++
 3 files changed, 66 insertions(+), 6 deletions(-)

diff --git a/Documentation/driver-api/firmware/other_interfaces.rst b/Documentation/driver-api/firmware/other_interfaces.rst
index b81794e0cfbb9..06ac89adaafba 100644
--- a/Documentation/driver-api/firmware/other_interfaces.rst
+++ b/Documentation/driver-api/firmware/other_interfaces.rst
@@ -13,6 +13,12 @@ EDD Interfaces
 .. kernel-doc:: drivers/firmware/edd.c
    :internal:
 
+Generic System Framebuffers Interface
+-------------------------------------
+
+.. kernel-doc:: drivers/firmware/sysfb.c
+   :export:
+
 Intel Stratix10 SoC Service Layer
 ---------------------------------
 Some features of the Intel Stratix10 SoC require a level of privilege
diff --git a/drivers/firmware/sysfb.c b/drivers/firmware/sysfb.c
index b032f40a92de0..1f276f108cc93 100644
--- a/drivers/firmware/sysfb.c
+++ b/drivers/firmware/sysfb.c
@@ -34,21 +34,59 @@
 #include <linux/screen_info.h>
 #include <linux/sysfb.h>
 
+static struct platform_device *pd;
+static DEFINE_MUTEX(disable_lock);
+static bool disabled;
+
+static bool sysfb_unregister(void)
+{
+	if (IS_ERR_OR_NULL(pd))
+		return false;
+
+	platform_device_unregister(pd);
+	pd = NULL;
+
+	return true;
+}
+
+/**
+ * sysfb_disable() - disable the Generic System Framebuffers support
+ *
+ * This disables the registration of system framebuffer devices that match the
+ * generic drivers that make use of the system framebuffer set up by firmware.
+ *
+ * It also unregisters a device if this was already registered by sysfb_init().
+ *
+ * Context: The function can sleep. A @disable_lock mutex is acquired to serialize
+ *          against sysfb_init(), that registers a system framebuffer device.
+ */
+void sysfb_disable(void)
+{
+	mutex_lock(&disable_lock);
+	sysfb_unregister();
+	disabled = true;
+	mutex_unlock(&disable_lock);
+}
+EXPORT_SYMBOL_GPL(sysfb_disable);
+
 static __init int sysfb_init(void)
 {
 	struct screen_info *si = &screen_info;
 	struct simplefb_platform_data mode;
-	struct platform_device *pd;
 	const char *name;
 	bool compatible;
-	int ret;
+	int ret = 0;
+
+	mutex_lock(&disable_lock);
+	if (disabled)
+		goto unlock_mutex;
 
 	/* try to create a simple-framebuffer device */
 	compatible = sysfb_parse_mode(si, &mode);
 	if (compatible) {
 		pd = sysfb_create_simplefb(si, &mode);
 		if (!IS_ERR(pd))
-			return 0;
+			goto unlock_mutex;
 	}
 
 	/* if the FB is incompatible, create a legacy framebuffer device */
@@ -60,8 +98,10 @@ static __init int sysfb_init(void)
 		name = "platform-framebuffer";
 
 	pd = platform_device_alloc(name, 0);
-	if (!pd)
-		return -ENOMEM;
+	if (!pd) {
+		ret = -ENOMEM;
+		goto unlock_mutex;
+	}
 
 	sysfb_apply_efi_quirks(pd);
 
@@ -73,9 +113,11 @@ static __init int sysfb_init(void)
 	if (ret)
 		goto err;
 
-	return 0;
+	goto unlock_mutex;
 err:
 	platform_device_put(pd);
+unlock_mutex:
+	mutex_unlock(&disable_lock);
 	return ret;
 }
 
diff --git a/include/linux/sysfb.h b/include/linux/sysfb.h
index 708152e9037bf..8ba8b5be55675 100644
--- a/include/linux/sysfb.h
+++ b/include/linux/sysfb.h
@@ -55,6 +55,18 @@ struct efifb_dmi_info {
 	int flags;
 };
 
+#ifdef CONFIG_SYSFB
+
+void sysfb_disable(void);
+
+#else /* CONFIG_SYSFB */
+
+static inline void sysfb_disable(void)
+{
+}
+
+#endif /* CONFIG_SYSFB */
+
 #ifdef CONFIG_EFI
 
 extern struct efifb_dmi_info efifb_dmi_list[];
-- 
GitLab


From ee7a69aa38d87a3bbced7b8245c732c05ed0c6ec Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas <javierm@redhat.com>
Date: Tue, 7 Jun 2022 20:23:36 +0200
Subject: [PATCH 1349/1731] fbdev: Disable sysfb device registration when
 removing conflicting FBs

The platform devices registered by sysfb match with firmware-based DRM or
fbdev drivers, that are used to have early graphics using a framebuffer
provided by the system firmware.

DRM or fbdev drivers later are probed and remove conflicting framebuffers,
leading to these platform devices for generic drivers to be unregistered.

But the current solution has a race, since the sysfb_init() function could
be called after a DRM or fbdev driver is probed and request to unregister
the devices for drivers with conflicting framebuffes.

To prevent this, disable any future sysfb platform device registration by
calling sysfb_disable(), if a driver requests to remove the conflicting
framebuffers.

Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20220607182338.344270-4-javierm@redhat.com
---
 drivers/video/fbdev/core/fbmem.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/video/fbdev/core/fbmem.c b/drivers/video/fbdev/core/fbmem.c
index afa2863670f34..8afc4538558cd 100644
--- a/drivers/video/fbdev/core/fbmem.c
+++ b/drivers/video/fbdev/core/fbmem.c
@@ -19,6 +19,7 @@
 #include <linux/kernel.h>
 #include <linux/major.h>
 #include <linux/slab.h>
+#include <linux/sysfb.h>
 #include <linux/mm.h>
 #include <linux/mman.h>
 #include <linux/vt.h>
@@ -1752,6 +1753,17 @@ int remove_conflicting_framebuffers(struct apertures_struct *a,
 		do_free = true;
 	}
 
+	/*
+	 * If a driver asked to unregister a platform device registered by
+	 * sysfb, then can be assumed that this is a driver for a display
+	 * that is set up by the system firmware and has a generic driver.
+	 *
+	 * Drivers for devices that don't have a generic driver will never
+	 * ask for this, so let's assume that a real driver for the display
+	 * was already probed and prevent sysfb to register devices later.
+	 */
+	sysfb_disable();
+
 	mutex_lock(&registration_lock);
 	do_remove_conflicting_framebuffers(a, name, primary);
 	mutex_unlock(&registration_lock);
-- 
GitLab


From a06968563775181690125091f470a8655742dcbf Mon Sep 17 00:00:00 2001
From: Nirmoy Das <nirmoy.das@intel.com>
Date: Fri, 24 Jun 2022 13:08:21 +0200
Subject: [PATCH 1350/1731] drm/i915: Fix a lockdep warning at error capture

For some platfroms we use stop_machine version of
gen8_ggtt_insert_page/gen8_ggtt_insert_entries to avoid a
concurrent GGTT access bug but this causes a circular locking
dependency warning:

  Possible unsafe locking scenario:
        CPU0                    CPU1
        ----                    ----
   lock(&ggtt->error_mutex);
                                lock(dma_fence_map);
                                lock(&ggtt->error_mutex);
   lock(cpu_hotplug_lock);

Fix this by calling gen8_ggtt_insert_page/gen8_ggtt_insert_entries
directly at error capture which is concurrent GGTT access safe because
reset path make sure of that.

v2: Fix rebase conflict and added a comment.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5595
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220624110821.29190-1-nirmoy.das@intel.com
---
 drivers/gpu/drm/i915/gt/intel_ggtt.c     | 10 ++++++++++
 drivers/gpu/drm/i915/gt/intel_gtt.h      |  9 +++++++++
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c |  5 ++++-
 drivers/gpu/drm/i915/i915_gpu_error.c    |  8 ++++++--
 4 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index ffff961803137..15a915bb4088e 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -960,6 +960,16 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 	if (intel_vm_no_concurrent_access_wa(i915)) {
 		ggtt->vm.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
 		ggtt->vm.insert_page    = bxt_vtd_ggtt_insert_page__BKL;
+
+		/*
+		 * Calling stop_machine() version of GGTT update function
+		 * at error capture/reset path will raise lockdep warning.
+		 * Allow calling gen8_ggtt_insert_* directly at reset path
+		 * which is safe from parallel GGTT updates.
+		 */
+		ggtt->vm.raw_insert_page = gen8_ggtt_insert_page;
+		ggtt->vm.raw_insert_entries = gen8_ggtt_insert_entries;
+
 		ggtt->vm.bind_async_flags =
 			I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
 	}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 29fd3a9e8b2e8..e639434e97fdb 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -306,6 +306,15 @@ struct i915_address_space {
 			       struct i915_vma_resource *vma_res,
 			       enum i915_cache_level cache_level,
 			       u32 flags);
+	void (*raw_insert_page)(struct i915_address_space *vm,
+				dma_addr_t addr,
+				u64 offset,
+				enum i915_cache_level cache_level,
+				u32 flags);
+	void (*raw_insert_entries)(struct i915_address_space *vm,
+				   struct i915_vma_resource *vma_res,
+				   enum i915_cache_level cache_level,
+				   u32 flags);
 	void (*cleanup)(struct i915_address_space *vm);
 
 	void (*foreach)(struct i915_address_space *vm,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index d2c5c9367cc4f..c06e83872c34d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -493,7 +493,10 @@ static void uc_fw_bind_ggtt(struct intel_uc_fw *uc_fw)
 	if (i915_gem_object_is_lmem(obj))
 		pte_flags |= PTE_LM;
 
-	ggtt->vm.insert_entries(&ggtt->vm, dummy, I915_CACHE_NONE, pte_flags);
+	if (ggtt->vm.raw_insert_entries)
+		ggtt->vm.raw_insert_entries(&ggtt->vm, dummy, I915_CACHE_NONE, pte_flags);
+	else
+		ggtt->vm.insert_entries(&ggtt->vm, dummy, I915_CACHE_NONE, pte_flags);
 }
 
 static void uc_fw_unbind_ggtt(struct intel_uc_fw *uc_fw)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index bff8a111424a2..f9b1969ed7ed2 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1104,8 +1104,12 @@ i915_vma_coredump_create(const struct intel_gt *gt,
 
 		for_each_sgt_daddr(dma, iter, vma_res->bi.pages) {
 			mutex_lock(&ggtt->error_mutex);
-			ggtt->vm.insert_page(&ggtt->vm, dma, slot,
-					     I915_CACHE_NONE, 0);
+			if (ggtt->vm.raw_insert_page)
+				ggtt->vm.raw_insert_page(&ggtt->vm, dma, slot,
+							 I915_CACHE_NONE, 0);
+			else
+				ggtt->vm.insert_page(&ggtt->vm, dma, slot,
+						     I915_CACHE_NONE, 0);
 			mb();
 
 			s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
-- 
GitLab


From b21bd5a4b130f8370861478d2880985daace5913 Mon Sep 17 00:00:00 2001
From: "Naveen N. Rao" <naveen.n.rao@linux.vnet.ibm.com>
Date: Tue, 28 Jun 2022 00:41:19 +0530
Subject: [PATCH 1351/1731] powerpc/bpf: Fix use of user_pt_regs in uapi
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Trying to build a .c file that includes <linux/bpf_perf_event.h>:
  $ cat test_bpf_headers.c
  #include <linux/bpf_perf_event.h>

throws the below error:
  /usr/include/linux/bpf_perf_event.h:14:28: error: field ‘regs’ has incomplete type
     14 |         bpf_user_pt_regs_t regs;
	|                            ^~~~

This is because we typedef bpf_user_pt_regs_t to 'struct user_pt_regs'
in arch/powerpc/include/uaps/asm/bpf_perf_event.h, but 'struct
user_pt_regs' is not exposed to userspace.

Powerpc has both pt_regs and user_pt_regs structures. However, unlike
arm64 and s390, we expose user_pt_regs to userspace as just 'pt_regs'.
As such, we should typedef bpf_user_pt_regs_t to 'struct pt_regs' for
userspace.

Within the kernel though, we want to typedef bpf_user_pt_regs_t to
'struct user_pt_regs'.

Remove arch/powerpc/include/uapi/asm/bpf_perf_event.h so that the
uapi/asm-generic version of the header is exposed to userspace.
Introduce arch/powerpc/include/asm/bpf_perf_event.h so that we can
typedef bpf_user_pt_regs_t to 'struct user_pt_regs' for use within the
kernel.

Note that this was not showing up with the bpf selftest build since
tools/include/uapi/asm/bpf_perf_event.h didn't include the powerpc
variant.

Fixes: a6460b03f945ee ("powerpc/bpf: Fix broken uapi for BPF_PROG_TYPE_PERF_EVENT")
Cc: stable@vger.kernel.org # v4.20+
Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
[mpe: Use typical naming for header include guard]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220627191119.142867-1-naveen.n.rao@linux.vnet.ibm.com
---
 arch/powerpc/include/asm/bpf_perf_event.h      | 9 +++++++++
 arch/powerpc/include/uapi/asm/bpf_perf_event.h | 9 ---------
 2 files changed, 9 insertions(+), 9 deletions(-)
 create mode 100644 arch/powerpc/include/asm/bpf_perf_event.h
 delete mode 100644 arch/powerpc/include/uapi/asm/bpf_perf_event.h

diff --git a/arch/powerpc/include/asm/bpf_perf_event.h b/arch/powerpc/include/asm/bpf_perf_event.h
new file mode 100644
index 0000000000000..e8a7b4ffb58c2
--- /dev/null
+++ b/arch/powerpc/include/asm/bpf_perf_event.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_POWERPC_BPF_PERF_EVENT_H
+#define _ASM_POWERPC_BPF_PERF_EVENT_H
+
+#include <asm/ptrace.h>
+
+typedef struct user_pt_regs bpf_user_pt_regs_t;
+
+#endif /* _ASM_POWERPC_BPF_PERF_EVENT_H */
diff --git a/arch/powerpc/include/uapi/asm/bpf_perf_event.h b/arch/powerpc/include/uapi/asm/bpf_perf_event.h
deleted file mode 100644
index 5e1e648aeec4c..0000000000000
--- a/arch/powerpc/include/uapi/asm/bpf_perf_event.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI__ASM_BPF_PERF_EVENT_H__
-#define _UAPI__ASM_BPF_PERF_EVENT_H__
-
-#include <asm/ptrace.h>
-
-typedef struct user_pt_regs bpf_user_pt_regs_t;
-
-#endif /* _UAPI__ASM_BPF_PERF_EVENT_H__ */
-- 
GitLab


From ac790d09885d36143076e7e02825c541e8eee899 Mon Sep 17 00:00:00 2001
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
Date: Wed, 29 Jun 2022 10:39:25 +0530
Subject: [PATCH 1352/1731] powerpc/memhotplug: Add add_pages override for PPC

With commit ffa0b64e3be5 ("powerpc: Fix virt_addr_valid() for 64-bit Book3E & 32-bit")
the kernel now validate the addr against high_memory value. This results
in the below BUG_ON with dax pfns.

[  635.798741][T26531] kernel BUG at mm/page_alloc.c:5521!
1:mon> e
cpu 0x1: Vector: 700 (Program Check) at [c000000007287630]
    pc: c00000000055ed48: free_pages.part.0+0x48/0x110
    lr: c00000000053ca70: tlb_finish_mmu+0x80/0xd0
    sp: c0000000072878d0
   msr: 800000000282b033
  current = 0xc00000000afabe00
  paca    = 0xc00000037ffff300   irqmask: 0x03   irq_happened: 0x05
    pid   = 26531, comm = 50-landscape-sy
kernel BUG at :5521!
Linux version 5.19.0-rc3-14659-g4ec05be7c2e1 (kvaneesh@ltc-boston8) (gcc (Ubuntu 9.4.0-1ubuntu1~20.04.1) 9.4.0, GNU ld (GNU Binutils for Ubuntu) 2.34) #625 SMP Thu Jun 23 00:35:43 CDT 2022
1:mon> t
[link register   ] c00000000053ca70 tlb_finish_mmu+0x80/0xd0
[c0000000072878d0] c00000000053ca54 tlb_finish_mmu+0x64/0xd0 (unreliable)
[c000000007287900] c000000000539424 exit_mmap+0xe4/0x2a0
[c0000000072879e0] c00000000019fc1c mmput+0xcc/0x210
[c000000007287a20] c000000000629230 begin_new_exec+0x5e0/0xf40
[c000000007287ae0] c00000000070b3cc load_elf_binary+0x3ac/0x1e00
[c000000007287c10] c000000000627af0 bprm_execve+0x3b0/0xaf0
[c000000007287cd0] c000000000628414 do_execveat_common.isra.0+0x1e4/0x310
[c000000007287d80] c00000000062858c sys_execve+0x4c/0x60
[c000000007287db0] c00000000002c1b0 system_call_exception+0x160/0x2c0
[c000000007287e10] c00000000000c53c system_call_common+0xec/0x250

The fix is to make sure we update high_memory on memory hotplug.
This is similar to what x86 does in commit 3072e413e305 ("mm/memory_hotplug: introduce add_pages")

Fixes: ffa0b64e3be5 ("powerpc: Fix virt_addr_valid() for 64-bit Book3E & 32-bit")
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Reviewed-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220629050925.31447-1-aneesh.kumar@linux.ibm.com
---
 arch/powerpc/Kconfig  |  4 ++++
 arch/powerpc/mm/mem.c | 33 ++++++++++++++++++++++++++++++++-
 2 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index c2ce2e60c8f0f..7aa12e88c5800 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -358,6 +358,10 @@ config ARCH_SUSPEND_NONZERO_CPU
 	def_bool y
 	depends on PPC_POWERNV || PPC_PSERIES
 
+config ARCH_HAS_ADD_PAGES
+	def_bool y
+	depends on ARCH_ENABLE_MEMORY_HOTPLUG
+
 config PPC_DCR_NATIVE
 	bool
 
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 52b77684acda7..a97128a488177 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -105,6 +105,37 @@ void __ref arch_remove_linear_mapping(u64 start, u64 size)
 	vm_unmap_aliases();
 }
 
+/*
+ * After memory hotplug the variables max_pfn, max_low_pfn and high_memory need
+ * updating.
+ */
+static void update_end_of_memory_vars(u64 start, u64 size)
+{
+	unsigned long end_pfn = PFN_UP(start + size);
+
+	if (end_pfn > max_pfn) {
+		max_pfn = end_pfn;
+		max_low_pfn = end_pfn;
+		high_memory = (void *)__va(max_pfn * PAGE_SIZE - 1) + 1;
+	}
+}
+
+int __ref add_pages(int nid, unsigned long start_pfn, unsigned long nr_pages,
+		    struct mhp_params *params)
+{
+	int ret;
+
+	ret = __add_pages(nid, start_pfn, nr_pages, params);
+	if (ret)
+		return ret;
+
+	/* update max_pfn, max_low_pfn and high_memory */
+	update_end_of_memory_vars(start_pfn << PAGE_SHIFT,
+				  nr_pages << PAGE_SHIFT);
+
+	return ret;
+}
+
 int __ref arch_add_memory(int nid, u64 start, u64 size,
 			  struct mhp_params *params)
 {
@@ -115,7 +146,7 @@ int __ref arch_add_memory(int nid, u64 start, u64 size,
 	rc = arch_create_linear_mapping(nid, start, size, params);
 	if (rc)
 		return rc;
-	rc = __add_pages(nid, start_pfn, nr_pages, params);
+	rc = add_pages(nid, start_pfn, nr_pages, params);
 	if (rc)
 		arch_remove_linear_mapping(start, size);
 	return rc;
-- 
GitLab


From 00aff3590fc0a73bddd3b743863c14e76fd35c0c Mon Sep 17 00:00:00 2001
From: Hangyu Hua <hbh25y@gmail.com>
Date: Wed, 29 Jun 2022 14:34:18 +0800
Subject: [PATCH 1353/1731] net: tipc: fix possible refcount leak in
 tipc_sk_create()

Free sk in case tipc_sk_insert() fails.

Signed-off-by: Hangyu Hua <hbh25y@gmail.com>
Reviewed-by: Tung Nguyen <tung.q.nguyen@dektech.com.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/tipc/socket.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/net/tipc/socket.c b/net/tipc/socket.c
index 17f8c523e33b0..43509c7e90fc2 100644
--- a/net/tipc/socket.c
+++ b/net/tipc/socket.c
@@ -502,6 +502,7 @@ static int tipc_sk_create(struct net *net, struct socket *sock,
 	sock_init_data(sock, sk);
 	tipc_set_sk_state(sk, TIPC_OPEN);
 	if (tipc_sk_insert(tsk)) {
+		sk_free(sk);
 		pr_warn("Socket create failed; port number exhausted\n");
 		return -EINVAL;
 	}
-- 
GitLab


From eddd95b9423946aaacb55cac6a9b2cea8ab944fc Mon Sep 17 00:00:00 2001
From: Michael Walle <michael@walle.cc>
Date: Mon, 27 Jun 2022 19:06:42 +0200
Subject: [PATCH 1354/1731] NFC: nxp-nci: Don't issue a zero length
 i2c_master_read()

There are packets which doesn't have a payload. In that case, the second
i2c_master_read() will have a zero length. But because the NFC
controller doesn't have any data left, it will NACK the I2C read and
-ENXIO will be returned. In case there is no payload, just skip the
second i2c master read.

Fixes: 6be88670fc59 ("NFC: nxp-nci_i2c: Add I2C support to NXP NCI driver")
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/nfc/nxp-nci/i2c.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/nfc/nxp-nci/i2c.c b/drivers/nfc/nxp-nci/i2c.c
index 7e451c10985df..e8f3b35afbee4 100644
--- a/drivers/nfc/nxp-nci/i2c.c
+++ b/drivers/nfc/nxp-nci/i2c.c
@@ -162,6 +162,9 @@ static int nxp_nci_i2c_nci_read(struct nxp_nci_i2c_phy *phy,
 
 	skb_put_data(*skb, (void *)&header, NCI_CTRL_HDR_SIZE);
 
+	if (!header.plen)
+		return 0;
+
 	r = i2c_master_recv(client, skb_put(*skb, header.plen), header.plen);
 	if (r != header.plen) {
 		nfc_err(&client->dev,
-- 
GitLab


From 9577fc5fdc8b07b891709af6453545db405e24ad Mon Sep 17 00:00:00 2001
From: Michael Walle <michael@walle.cc>
Date: Mon, 27 Jun 2022 19:06:43 +0200
Subject: [PATCH 1355/1731] NFC: nxp-nci: don't print header length mismatch on
 i2c error

Don't print a misleading header length mismatch error if the i2c call
returns an error. Instead just return the error code without any error
message.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/nfc/nxp-nci/i2c.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/nfc/nxp-nci/i2c.c b/drivers/nfc/nxp-nci/i2c.c
index e8f3b35afbee4..ae2ba08d8ac3f 100644
--- a/drivers/nfc/nxp-nci/i2c.c
+++ b/drivers/nfc/nxp-nci/i2c.c
@@ -122,7 +122,9 @@ static int nxp_nci_i2c_fw_read(struct nxp_nci_i2c_phy *phy,
 	skb_put_data(*skb, &header, NXP_NCI_FW_HDR_LEN);
 
 	r = i2c_master_recv(client, skb_put(*skb, frame_len), frame_len);
-	if (r != frame_len) {
+	if (r < 0) {
+		goto fw_read_exit_free_skb;
+	} else if (r != frame_len) {
 		nfc_err(&client->dev,
 			"Invalid frame length: %u (expected %zu)\n",
 			r, frame_len);
@@ -166,7 +168,9 @@ static int nxp_nci_i2c_nci_read(struct nxp_nci_i2c_phy *phy,
 		return 0;
 
 	r = i2c_master_recv(client, skb_put(*skb, header.plen), header.plen);
-	if (r != header.plen) {
+	if (r < 0) {
+		goto nci_read_exit_free_skb;
+	} else if (r != header.plen) {
 		nfc_err(&client->dev,
 			"Invalid frame payload length: %u (expected %u)\n",
 			r, header.plen);
-- 
GitLab


From ed0691cf55140ce0f3fb100225645d902cce904b Mon Sep 17 00:00:00 2001
From: Sagi Grimberg <sagi@grimberg.me>
Date: Fri, 24 Jun 2022 00:49:53 +0300
Subject: [PATCH 1356/1731] nvmet-tcp: fix regression in data_digest
 calculation

Data digest calculation iterates over command mapped iovec. However
since commit bac04454ef9f we unmap the iovec before we handle the data
digest, and since commit 69b85e1f1d1d we clear nr_mapped when we unmap
the iov.

Instead of open-coding the command iov traversal, simply call
crypto_ahash_digest with the command sg that is already allocated (we
already do that for the send path). Rename nvmet_tcp_send_ddgst to
nvmet_tcp_calc_ddgst and call it from send and recv paths.

Fixes: 69b85e1f1d1d ("nvmet-tcp: add an helper to free the cmd buffers")
Fixes: bac04454ef9f ("nvmet-tcp: fix kmap leak when data digest in use")
Signed-off-by: Sagi Grimberg <sagi@grimberg.me>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/target/tcp.c | 23 +++--------------------
 1 file changed, 3 insertions(+), 20 deletions(-)

diff --git a/drivers/nvme/target/tcp.c b/drivers/nvme/target/tcp.c
index 2793554e622ee..0a9542599ad1c 100644
--- a/drivers/nvme/target/tcp.c
+++ b/drivers/nvme/target/tcp.c
@@ -405,7 +405,7 @@ err:
 	return NVME_SC_INTERNAL;
 }
 
-static void nvmet_tcp_send_ddgst(struct ahash_request *hash,
+static void nvmet_tcp_calc_ddgst(struct ahash_request *hash,
 		struct nvmet_tcp_cmd *cmd)
 {
 	ahash_request_set_crypt(hash, cmd->req.sg,
@@ -413,23 +413,6 @@ static void nvmet_tcp_send_ddgst(struct ahash_request *hash,
 	crypto_ahash_digest(hash);
 }
 
-static void nvmet_tcp_recv_ddgst(struct ahash_request *hash,
-		struct nvmet_tcp_cmd *cmd)
-{
-	struct scatterlist sg;
-	struct kvec *iov;
-	int i;
-
-	crypto_ahash_init(hash);
-	for (i = 0, iov = cmd->iov; i < cmd->nr_mapped; i++, iov++) {
-		sg_init_one(&sg, iov->iov_base, iov->iov_len);
-		ahash_request_set_crypt(hash, &sg, NULL, iov->iov_len);
-		crypto_ahash_update(hash);
-	}
-	ahash_request_set_crypt(hash, NULL, (void *)&cmd->exp_ddgst, 0);
-	crypto_ahash_final(hash);
-}
-
 static void nvmet_setup_c2h_data_pdu(struct nvmet_tcp_cmd *cmd)
 {
 	struct nvme_tcp_data_pdu *pdu = cmd->data_pdu;
@@ -454,7 +437,7 @@ static void nvmet_setup_c2h_data_pdu(struct nvmet_tcp_cmd *cmd)
 
 	if (queue->data_digest) {
 		pdu->hdr.flags |= NVME_TCP_F_DDGST;
-		nvmet_tcp_send_ddgst(queue->snd_hash, cmd);
+		nvmet_tcp_calc_ddgst(queue->snd_hash, cmd);
 	}
 
 	if (cmd->queue->hdr_digest) {
@@ -1137,7 +1120,7 @@ static void nvmet_tcp_prep_recv_ddgst(struct nvmet_tcp_cmd *cmd)
 {
 	struct nvmet_tcp_queue *queue = cmd->queue;
 
-	nvmet_tcp_recv_ddgst(queue->rcv_hash, cmd);
+	nvmet_tcp_calc_ddgst(queue->rcv_hash, cmd);
 	queue->offset = 0;
 	queue->left = NVME_TCP_DIGEST_LENGTH;
 	queue->rcv_state = NVMET_TCP_RECV_DDGST;
-- 
GitLab


From 41d07df7de841bfbc32725ce21d933ad358f2844 Mon Sep 17 00:00:00 2001
From: Sagi Grimberg <sagi@grimberg.me>
Date: Sun, 26 Jun 2022 12:24:51 +0300
Subject: [PATCH 1357/1731] nvme-tcp: always fail a request when sending it
 failed

queue stoppage and inflight requests cancellation is fully fenced from
io_work and thus failing a request from this context. Hence we don't
need to try to guess from the socket retcode if this failure is because
the queue is about to be torn down or not.

We are perfectly safe to just fail it, the request will not be cancelled
later on.

This solves possible very long shutdown delays when the users issues a
'nvme disconnect-all'

Reported-by: Daniel Wagner <dwagner@suse.de>
Signed-off-by: Sagi Grimberg <sagi@grimberg.me>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/host/tcp.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/nvme/host/tcp.c b/drivers/nvme/host/tcp.c
index bb67538d241b6..009c2cf3f1068 100644
--- a/drivers/nvme/host/tcp.c
+++ b/drivers/nvme/host/tcp.c
@@ -1180,8 +1180,7 @@ done:
 	} else if (ret < 0) {
 		dev_err(queue->ctrl->ctrl.device,
 			"failed to send request %d\n", ret);
-		if (ret != -EPIPE && ret != -ECONNRESET)
-			nvme_tcp_fail_request(queue->request);
+		nvme_tcp_fail_request(queue->request);
 		nvme_tcp_done_send_req(queue);
 	}
 	return ret;
-- 
GitLab


From 1629de0e0373e04d68e88e6d9d3071fbf70b7ea8 Mon Sep 17 00:00:00 2001
From: Pablo Greco <pgreco@centosproject.org>
Date: Sat, 25 Jun 2022 09:15:02 -0300
Subject: [PATCH 1358/1731] nvme-pci: add NVME_QUIRK_BOGUS_NID for ADATA XPG
 SX6000LNP (AKA SPECTRIX S40G)

ADATA XPG SPECTRIX S40G drives report bogus eui64 values that appear to
be the same across drives in one system. Quirk them out so they are
not marked as "non globally unique" duplicates.

Before:
[    2.258919] nvme nvme1: pci function 0000:06:00.0
[    2.264898] nvme nvme2: pci function 0000:05:00.0
[    2.323235] nvme nvme1: failed to set APST feature (2)
[    2.326153] nvme nvme2: failed to set APST feature (2)
[    2.333935] nvme nvme1: allocated 64 MiB host memory buffer.
[    2.336492] nvme nvme2: allocated 64 MiB host memory buffer.
[    2.339611] nvme nvme1: 7/0/0 default/read/poll queues
[    2.341805] nvme nvme2: 7/0/0 default/read/poll queues
[    2.346114]  nvme1n1: p1
[    2.347197] nvme nvme2: globally duplicate IDs for nsid 1
After:
[    2.427715] nvme nvme1: pci function 0000:06:00.0
[    2.427771] nvme nvme2: pci function 0000:05:00.0
[    2.488154] nvme nvme2: failed to set APST feature (2)
[    2.489895] nvme nvme1: failed to set APST feature (2)
[    2.498773] nvme nvme2: allocated 64 MiB host memory buffer.
[    2.500587] nvme nvme1: allocated 64 MiB host memory buffer.
[    2.504113] nvme nvme2: 7/0/0 default/read/poll queues
[    2.507026] nvme nvme1: 7/0/0 default/read/poll queues
[    2.509467] nvme nvme2: Ignoring bogus Namespace Identifiers
[    2.512804] nvme nvme1: Ignoring bogus Namespace Identifiers
[    2.513698]  nvme1n1: p1

Signed-off-by: Pablo Greco <pgreco@centosproject.org>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Chaitanya Kulkarni <kch@nvidia.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/host/pci.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index d7b24ee172859..c9ebe60724980 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -3470,7 +3470,8 @@ static const struct pci_device_id nvme_id_table[] = {
 		.driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
 				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
 	{ PCI_DEVICE(0x10ec, 0x5762),   /* ADATA SX6000LNP */
-		.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
+		.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
+				NVME_QUIRK_BOGUS_NID, },
 	{ PCI_DEVICE(0x1cc1, 0x8201),   /* ADATA SX8200PNP 512GB */
 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS |
 				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
-- 
GitLab


From f7f70f4aa09dc43d7455c060143e86a017c30548 Mon Sep 17 00:00:00 2001
From: Ruozhu Li <liruozhu@huawei.com>
Date: Thu, 23 Jun 2022 14:45:39 +0800
Subject: [PATCH 1359/1731] nvme: fix regression when disconnect a recovering
 ctrl

We encountered a problem that the disconnect command hangs.
After analyzing the log and stack, we found that the triggering
process is as follows:
CPU0                          CPU1
                                nvme_rdma_error_recovery_work
                                  nvme_rdma_teardown_io_queues
nvme_do_delete_ctrl                 nvme_stop_queues
  nvme_remove_namespaces
  --clear ctrl->namespaces
                                    nvme_start_queues
                                    --no ns in ctrl->namespaces
    nvme_ns_remove                  return(because ctrl is deleting)
      blk_freeze_queue
        blk_mq_freeze_queue_wait
        --wait for ns to unquiesce to clean infligt IO, hang forever

This problem was not found in older kernels because we will flush
err work in nvme_stop_ctrl before nvme_remove_namespaces.It does not
seem to be modified for functional reasons, the patch can be revert
to solve the problem.

Revert commit 794a4cb3d2f7 ("nvme: remove the .stop_ctrl callout")

Signed-off-by: Ruozhu Li <liruozhu@huawei.com>
Reviewed-by: Sagi Grimberg <sagi@grimberg.me>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/host/core.c |  2 ++
 drivers/nvme/host/nvme.h |  1 +
 drivers/nvme/host/rdma.c | 12 +++++++++---
 drivers/nvme/host/tcp.c  | 10 +++++++---
 4 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c
index b3d9c29aba1e6..ec6ac298d8de2 100644
--- a/drivers/nvme/host/core.c
+++ b/drivers/nvme/host/core.c
@@ -4595,6 +4595,8 @@ void nvme_stop_ctrl(struct nvme_ctrl *ctrl)
 	nvme_stop_failfast_work(ctrl);
 	flush_work(&ctrl->async_event_work);
 	cancel_work_sync(&ctrl->fw_act_work);
+	if (ctrl->ops->stop_ctrl)
+		ctrl->ops->stop_ctrl(ctrl);
 }
 EXPORT_SYMBOL_GPL(nvme_stop_ctrl);
 
diff --git a/drivers/nvme/host/nvme.h b/drivers/nvme/host/nvme.h
index 0da94b233feda..5558f88121579 100644
--- a/drivers/nvme/host/nvme.h
+++ b/drivers/nvme/host/nvme.h
@@ -502,6 +502,7 @@ struct nvme_ctrl_ops {
 	void (*free_ctrl)(struct nvme_ctrl *ctrl);
 	void (*submit_async_event)(struct nvme_ctrl *ctrl);
 	void (*delete_ctrl)(struct nvme_ctrl *ctrl);
+	void (*stop_ctrl)(struct nvme_ctrl *ctrl);
 	int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size);
 	void (*print_device_info)(struct nvme_ctrl *ctrl);
 };
diff --git a/drivers/nvme/host/rdma.c b/drivers/nvme/host/rdma.c
index f2a5e1ea508a7..46c2dcf72f7ea 100644
--- a/drivers/nvme/host/rdma.c
+++ b/drivers/nvme/host/rdma.c
@@ -1048,6 +1048,14 @@ static void nvme_rdma_teardown_io_queues(struct nvme_rdma_ctrl *ctrl,
 	}
 }
 
+static void nvme_rdma_stop_ctrl(struct nvme_ctrl *nctrl)
+{
+	struct nvme_rdma_ctrl *ctrl = to_rdma_ctrl(nctrl);
+
+	cancel_work_sync(&ctrl->err_work);
+	cancel_delayed_work_sync(&ctrl->reconnect_work);
+}
+
 static void nvme_rdma_free_ctrl(struct nvme_ctrl *nctrl)
 {
 	struct nvme_rdma_ctrl *ctrl = to_rdma_ctrl(nctrl);
@@ -2252,9 +2260,6 @@ static const struct blk_mq_ops nvme_rdma_admin_mq_ops = {
 
 static void nvme_rdma_shutdown_ctrl(struct nvme_rdma_ctrl *ctrl, bool shutdown)
 {
-	cancel_work_sync(&ctrl->err_work);
-	cancel_delayed_work_sync(&ctrl->reconnect_work);
-
 	nvme_rdma_teardown_io_queues(ctrl, shutdown);
 	nvme_stop_admin_queue(&ctrl->ctrl);
 	if (shutdown)
@@ -2304,6 +2309,7 @@ static const struct nvme_ctrl_ops nvme_rdma_ctrl_ops = {
 	.submit_async_event	= nvme_rdma_submit_async_event,
 	.delete_ctrl		= nvme_rdma_delete_ctrl,
 	.get_address		= nvmf_get_address,
+	.stop_ctrl		= nvme_rdma_stop_ctrl,
 };
 
 /*
diff --git a/drivers/nvme/host/tcp.c b/drivers/nvme/host/tcp.c
index 009c2cf3f1068..7a9e6ffa23429 100644
--- a/drivers/nvme/host/tcp.c
+++ b/drivers/nvme/host/tcp.c
@@ -2193,9 +2193,6 @@ static void nvme_tcp_error_recovery_work(struct work_struct *work)
 
 static void nvme_tcp_teardown_ctrl(struct nvme_ctrl *ctrl, bool shutdown)
 {
-	cancel_work_sync(&to_tcp_ctrl(ctrl)->err_work);
-	cancel_delayed_work_sync(&to_tcp_ctrl(ctrl)->connect_work);
-
 	nvme_tcp_teardown_io_queues(ctrl, shutdown);
 	nvme_stop_admin_queue(ctrl);
 	if (shutdown)
@@ -2235,6 +2232,12 @@ out_fail:
 	nvme_tcp_reconnect_or_remove(ctrl);
 }
 
+static void nvme_tcp_stop_ctrl(struct nvme_ctrl *ctrl)
+{
+	cancel_work_sync(&to_tcp_ctrl(ctrl)->err_work);
+	cancel_delayed_work_sync(&to_tcp_ctrl(ctrl)->connect_work);
+}
+
 static void nvme_tcp_free_ctrl(struct nvme_ctrl *nctrl)
 {
 	struct nvme_tcp_ctrl *ctrl = to_tcp_ctrl(nctrl);
@@ -2556,6 +2559,7 @@ static const struct nvme_ctrl_ops nvme_tcp_ctrl_ops = {
 	.submit_async_event	= nvme_tcp_submit_async_event,
 	.delete_ctrl		= nvme_tcp_delete_ctrl,
 	.get_address		= nvmf_get_address,
+	.stop_ctrl		= nvme_tcp_stop_ctrl,
 };
 
 static bool
-- 
GitLab


From 7be3bd8856fba99f8b25b9c223250e42292c312e Mon Sep 17 00:00:00 2001
From: "Darrick J. Wong" <djwong@kernel.org>
Date: Fri, 24 Jun 2022 15:01:28 -0700
Subject: [PATCH 1360/1731] xfs: empty xattr leaf header blocks are not
 corruption

TLDR: Revert commit 51e6104fdb95 ("xfs: detect empty attr leaf blocks in
xfs_attr3_leaf_verify") because it was wrong.

Every now and then we get a corruption report from the kernel or
xfs_repair about empty leaf blocks in the extended attribute structure.
We've long thought that these shouldn't be possible, but prior to 5.18
one would shake loose in the recoveryloop fstests about once a month.

A new addition to the xattr leaf block verifier in 5.19-rc1 makes this
happen every 7 minutes on my testing cloud.  I added a ton of logging to
detect any time we set the header count on an xattr leaf block to zero.
This produced the following dmesg output on generic/388:

XFS (sda4): ino 0x21fcbaf leaf 0x129bf78 hdcount==0!
Call Trace:
 <TASK>
 dump_stack_lvl+0x34/0x44
 xfs_attr3_leaf_create+0x187/0x230
 xfs_attr_shortform_to_leaf+0xd1/0x2f0
 xfs_attr_set_iter+0x73e/0xa90
 xfs_xattri_finish_update+0x45/0x80
 xfs_attr_finish_item+0x1b/0xd0
 xfs_defer_finish_noroll+0x19c/0x770
 __xfs_trans_commit+0x153/0x3e0
 xfs_attr_set+0x36b/0x740
 xfs_xattr_set+0x89/0xd0
 __vfs_setxattr+0x67/0x80
 __vfs_setxattr_noperm+0x6e/0x120
 vfs_setxattr+0x97/0x180
 setxattr+0x88/0xa0
 path_setxattr+0xc3/0xe0
 __x64_sys_setxattr+0x27/0x30
 do_syscall_64+0x35/0x80
 entry_SYSCALL_64_after_hwframe+0x46/0xb0

So now we know that someone is creating empty xattr leaf blocks as part
of converting a sf xattr structure into a leaf xattr structure.  The
conversion routine logs any existing sf attributes in the same
transaction that creates the leaf block, so we know this is a setxattr
to a file that has no attributes at all.

Next, g/388 calls the shutdown ioctl and cycles the mount to trigger log
recovery.  I also augmented buffer item recovery to call ->verify_struct
on any attr leaf blocks and complain if it finds a failure:

XFS (sda4): Unmounting Filesystem
XFS (sda4): Mounting V5 Filesystem
XFS (sda4): Starting recovery (logdev: internal)
XFS (sda4): xattr leaf daddr 0x129bf78 hdrcount == 0!
Call Trace:
 <TASK>
 dump_stack_lvl+0x34/0x44
 xfs_attr3_leaf_verify+0x3b8/0x420
 xlog_recover_buf_commit_pass2+0x60a/0x6c0
 xlog_recover_items_pass2+0x4e/0xc0
 xlog_recover_commit_trans+0x33c/0x350
 xlog_recovery_process_trans+0xa5/0xe0
 xlog_recover_process_data+0x8d/0x140
 xlog_do_recovery_pass+0x19b/0x720
 xlog_do_log_recovery+0x62/0xc0
 xlog_do_recover+0x33/0x1d0
 xlog_recover+0xda/0x190
 xfs_log_mount+0x14c/0x360
 xfs_mountfs+0x517/0xa60
 xfs_fs_fill_super+0x6bc/0x950
 get_tree_bdev+0x175/0x280
 vfs_get_tree+0x1a/0x80
 path_mount+0x6f5/0xaa0
 __x64_sys_mount+0x103/0x140
 do_syscall_64+0x35/0x80
 entry_SYSCALL_64_after_hwframe+0x46/0xb0
RIP: 0033:0x7fc61e241eae

And a moment later, the _delwri_submit of the recovered buffers trips
the same verifier and recovery fails:

XFS (sda4): Metadata corruption detected at xfs_attr3_leaf_verify+0x393/0x420 [xfs], xfs_attr3_leaf block 0x129bf78
XFS (sda4): Unmount and run xfs_repair
XFS (sda4): First 128 bytes of corrupted metadata buffer:
00000000: 00 00 00 00 00 00 00 00 3b ee 00 00 00 00 00 00  ........;.......
00000010: 00 00 00 00 01 29 bf 78 00 00 00 00 00 00 00 00  .....).x........
00000020: a5 1b d0 02 b2 9a 49 df 8e 9c fb 8d f8 31 3e 9d  ......I......1>.
00000030: 00 00 00 00 02 1f cb af 00 00 00 00 10 00 00 00  ................
00000040: 00 50 0f b0 00 00 00 00 00 00 00 00 00 00 00 00  .P..............
00000050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
00000060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
00000070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
XFS (sda4): Corruption of in-memory data (0x8) detected at _xfs_buf_ioapply+0x37f/0x3b0 [xfs] (fs/xfs/xfs_buf.c:1518).  Shutting down filesystem.
XFS (sda4): Please unmount the filesystem and rectify the problem(s)
XFS (sda4): log mount/recovery failed: error -117
XFS (sda4): log mount failed

I think I see what's going on here -- setxattr is racing with something
that shuts down the filesystem:

Thread 1				Thread 2
--------				--------
xfs_attr_sf_addname
xfs_attr_shortform_to_leaf
<create empty leaf>
xfs_trans_bhold(leaf)
xattri_dela_state = XFS_DAS_LEAF_ADD
<roll transaction>
					<flush log>
					<shut down filesystem>
xfs_trans_bhold_release(leaf)
<discover fs is dead, bail>

Thread 3
--------
<cycle mount, start recovery>
xlog_recover_buf_commit_pass2
xlog_recover_do_reg_buffer
<replay empty leaf buffer from recovered buf item>
xfs_buf_delwri_queue(leaf)
xfs_buf_delwri_submit
_xfs_buf_ioapply(leaf)
xfs_attr3_leaf_write_verify
<trip over empty leaf buffer>
<fail recovery>

As you can see, the bhold keeps the leaf buffer locked and thus prevents
the *AIL* from tripping over the ichdr.count==0 check in the write
verifier.  Unfortunately, it doesn't prevent the log from getting
flushed to disk, which sets up log recovery to fail.

So.  It's clear that the kernel has always had the ability to persist
attr leaf blocks with ichdr.count==0, which means that it's part of the
ondisk format now.

Unfortunately, this check has been added and removed multiple times
throughout history.  It first appeared in[1] kernel 3.10 as part of the
early V5 format patches.  The check was later discovered to break log
recovery and hence disabled[2] during log recovery in kernel 4.10.
Simultaneously, the check was added[3] to xfs_repair 4.9.0 to try to
weed out the empty leaf blocks.  This was still not correct because log
recovery would recover an empty attr leaf block successfully only for
regular xattr operations to trip over the empty block during of the
block during regular operation.  Therefore, the check was removed
entirely[4] in kernel 5.7 but removal of the xfs_repair check was
forgotten.  The continued complaints from xfs_repair lead to us
mistakenly re-adding[5] the verifier check for kernel 5.19.  Remove it
once again.

[1] 517c22207b04 ("xfs: add CRCs to attr leaf blocks")
[2] 2e1d23370e75 ("xfs: ignore leaf attr ichdr.count in verifier
                   during log replay")
[3] f7140161 ("xfs_repair: junk leaf attribute if count == 0")
[4] f28cef9e4dac ("xfs: don't fail verifier on empty attr3 leaf
                   block")
[5] 51e6104fdb95 ("xfs: detect empty attr leaf blocks in
                   xfs_attr3_leaf_verify")

Looking at the rest of the xattr code, it seems that files with empty
leaf blocks behave as expected -- listxattr reports no attributes;
getxattr on any xattr returns nothing as expected; removexattr does
nothing; and setxattr can add attributes just fine.

Original-bug: 517c22207b04 ("xfs: add CRCs to attr leaf blocks")
Still-not-fixed-by: 2e1d23370e75 ("xfs: ignore leaf attr ichdr.count in verifier during log replay")
Removed-in: f28cef9e4dac ("xfs: don't fail verifier on empty attr3 leaf block")
Fixes: 51e6104fdb95 ("xfs: detect empty attr leaf blocks in xfs_attr3_leaf_verify")
Signed-off-by: Darrick J. Wong <djwong@kernel.org>
Reviewed-by: Dave Chinner <dchinner@redhat.com>
---
 fs/xfs/libxfs/xfs_attr_leaf.c | 26 +++++++++++++++++---------
 1 file changed, 17 insertions(+), 9 deletions(-)

diff --git a/fs/xfs/libxfs/xfs_attr_leaf.c b/fs/xfs/libxfs/xfs_attr_leaf.c
index 37e7c33f62839..f6629960e17b3 100644
--- a/fs/xfs/libxfs/xfs_attr_leaf.c
+++ b/fs/xfs/libxfs/xfs_attr_leaf.c
@@ -289,6 +289,23 @@ xfs_attr3_leaf_verify_entry(
 	return NULL;
 }
 
+/*
+ * Validate an attribute leaf block.
+ *
+ * Empty leaf blocks can occur under the following circumstances:
+ *
+ * 1. setxattr adds a new extended attribute to a file;
+ * 2. The file has zero existing attributes;
+ * 3. The attribute is too large to fit in the attribute fork;
+ * 4. The attribute is small enough to fit in a leaf block;
+ * 5. A log flush occurs after committing the transaction that creates
+ *    the (empty) leaf block; and
+ * 6. The filesystem goes down after the log flush but before the new
+ *    attribute can be committed to the leaf block.
+ *
+ * Hence we need to ensure that we don't fail the validation purely
+ * because the leaf is empty.
+ */
 static xfs_failaddr_t
 xfs_attr3_leaf_verify(
 	struct xfs_buf			*bp)
@@ -310,15 +327,6 @@ xfs_attr3_leaf_verify(
 	if (fa)
 		return fa;
 
-	/*
-	 * Empty leaf blocks should never occur;  they imply the existence of a
-	 * software bug that needs fixing. xfs_repair also flags them as a
-	 * corruption that needs fixing, so we should never let these go to
-	 * disk.
-	 */
-	if (ichdr.count == 0)
-		return __this_address;
-
 	/*
 	 * firstused is the block offset of the first name info structure.
 	 * Make sure it doesn't go off the block or crash into the header.
-- 
GitLab


From e53bcffad0326c1ef4b4baec4262b5343e420c44 Mon Sep 17 00:00:00 2001
From: "Darrick J. Wong" <djwong@kernel.org>
Date: Sat, 25 Jun 2022 10:01:20 -0700
Subject: [PATCH 1361/1731] xfs: don't hold xattr leaf buffers across
 transaction rolls

Now that we've established (again!) that empty xattr leaf buffers are
ok, we no longer need to bhold them to transactions when we're creating
new leaf blocks.  Get rid of the entire mechanism, which should simplify
the xattr code quite a bit.

The original justification for using bhold here was to prevent the AIL
from trying to write the empty leaf block into the fs during the brief
time that we release the buffer lock.  The reason for /that/ was to
prevent recovery from tripping over the empty ondisk block.

Reviewed-by: Dave Chinner <dchinner@redhat.com>
Signed-off-by: Darrick J. Wong <djwong@kernel.org>
---
 fs/xfs/libxfs/xfs_attr.c      | 38 +++++++++--------------------------
 fs/xfs/libxfs/xfs_attr.h      |  5 -----
 fs/xfs/libxfs/xfs_attr_leaf.c |  9 ++-------
 fs/xfs/libxfs/xfs_attr_leaf.h |  3 +--
 fs/xfs/xfs_attr_item.c        | 22 --------------------
 5 files changed, 12 insertions(+), 65 deletions(-)

diff --git a/fs/xfs/libxfs/xfs_attr.c b/fs/xfs/libxfs/xfs_attr.c
index 1824f61621a24..224649a76cbbb 100644
--- a/fs/xfs/libxfs/xfs_attr.c
+++ b/fs/xfs/libxfs/xfs_attr.c
@@ -50,7 +50,7 @@ STATIC int xfs_attr_shortform_addname(xfs_da_args_t *args);
 STATIC int xfs_attr_leaf_get(xfs_da_args_t *args);
 STATIC int xfs_attr_leaf_removename(xfs_da_args_t *args);
 STATIC int xfs_attr_leaf_hasname(struct xfs_da_args *args, struct xfs_buf **bp);
-STATIC int xfs_attr_leaf_try_add(struct xfs_da_args *args, struct xfs_buf *bp);
+STATIC int xfs_attr_leaf_try_add(struct xfs_da_args *args);
 
 /*
  * Internal routines when attribute list is more than one block.
@@ -393,16 +393,10 @@ xfs_attr_sf_addname(
 	 * It won't fit in the shortform, transform to a leaf block.  GROT:
 	 * another possible req'mt for a double-split btree op.
 	 */
-	error = xfs_attr_shortform_to_leaf(args, &attr->xattri_leaf_bp);
+	error = xfs_attr_shortform_to_leaf(args);
 	if (error)
 		return error;
 
-	/*
-	 * Prevent the leaf buffer from being unlocked so that a concurrent AIL
-	 * push cannot grab the half-baked leaf buffer and run into problems
-	 * with the write verifier.
-	 */
-	xfs_trans_bhold(args->trans, attr->xattri_leaf_bp);
 	attr->xattri_dela_state = XFS_DAS_LEAF_ADD;
 out:
 	trace_xfs_attr_sf_addname_return(attr->xattri_dela_state, args->dp);
@@ -447,11 +441,9 @@ xfs_attr_leaf_addname(
 
 	/*
 	 * Use the leaf buffer we may already hold locked as a result of
-	 * a sf-to-leaf conversion. The held buffer is no longer valid
-	 * after this call, regardless of the result.
+	 * a sf-to-leaf conversion.
 	 */
-	error = xfs_attr_leaf_try_add(args, attr->xattri_leaf_bp);
-	attr->xattri_leaf_bp = NULL;
+	error = xfs_attr_leaf_try_add(args);
 
 	if (error == -ENOSPC) {
 		error = xfs_attr3_leaf_to_node(args);
@@ -497,8 +489,6 @@ xfs_attr_node_addname(
 	struct xfs_da_args	*args = attr->xattri_da_args;
 	int			error;
 
-	ASSERT(!attr->xattri_leaf_bp);
-
 	error = xfs_attr_node_addname_find_attr(attr);
 	if (error)
 		return error;
@@ -1215,24 +1205,14 @@ xfs_attr_restore_rmt_blk(
  */
 STATIC int
 xfs_attr_leaf_try_add(
-	struct xfs_da_args	*args,
-	struct xfs_buf		*bp)
+	struct xfs_da_args	*args)
 {
+	struct xfs_buf		*bp;
 	int			error;
 
-	/*
-	 * If the caller provided a buffer to us, it is locked and held in
-	 * the transaction because it just did a shortform to leaf conversion.
-	 * Hence we don't need to read it again. Otherwise read in the leaf
-	 * buffer.
-	 */
-	if (bp) {
-		xfs_trans_bhold_release(args->trans, bp);
-	} else {
-		error = xfs_attr3_leaf_read(args->trans, args->dp, 0, &bp);
-		if (error)
-			return error;
-	}
+	error = xfs_attr3_leaf_read(args->trans, args->dp, 0, &bp);
+	if (error)
+		return error;
 
 	/*
 	 * Look up the xattr name to set the insertion point for the new xattr.
diff --git a/fs/xfs/libxfs/xfs_attr.h b/fs/xfs/libxfs/xfs_attr.h
index b4a2fc77017e0..dfb47fa63c6d5 100644
--- a/fs/xfs/libxfs/xfs_attr.h
+++ b/fs/xfs/libxfs/xfs_attr.h
@@ -515,11 +515,6 @@ struct xfs_attr_intent {
 	 */
 	struct xfs_attri_log_nameval	*xattri_nameval;
 
-	/*
-	 * Used by xfs_attr_set to hold a leaf buffer across a transaction roll
-	 */
-	struct xfs_buf			*xattri_leaf_bp;
-
 	/* Used to keep track of current state of delayed operation */
 	enum xfs_delattr_state		xattri_dela_state;
 
diff --git a/fs/xfs/libxfs/xfs_attr_leaf.c b/fs/xfs/libxfs/xfs_attr_leaf.c
index f6629960e17b3..8f47396f8dd23 100644
--- a/fs/xfs/libxfs/xfs_attr_leaf.c
+++ b/fs/xfs/libxfs/xfs_attr_leaf.c
@@ -930,14 +930,10 @@ xfs_attr_shortform_getvalue(
 	return -ENOATTR;
 }
 
-/*
- * Convert from using the shortform to the leaf.  On success, return the
- * buffer so that we can keep it locked until we're totally done with it.
- */
+/* Convert from using the shortform to the leaf format. */
 int
 xfs_attr_shortform_to_leaf(
-	struct xfs_da_args		*args,
-	struct xfs_buf			**leaf_bp)
+	struct xfs_da_args		*args)
 {
 	struct xfs_inode		*dp;
 	struct xfs_attr_shortform	*sf;
@@ -999,7 +995,6 @@ xfs_attr_shortform_to_leaf(
 		sfe = xfs_attr_sf_nextentry(sfe);
 	}
 	error = 0;
-	*leaf_bp = bp;
 out:
 	kmem_free(tmpbuffer);
 	return error;
diff --git a/fs/xfs/libxfs/xfs_attr_leaf.h b/fs/xfs/libxfs/xfs_attr_leaf.h
index efa757f1e912c..368f4d9fa1d59 100644
--- a/fs/xfs/libxfs/xfs_attr_leaf.h
+++ b/fs/xfs/libxfs/xfs_attr_leaf.h
@@ -49,8 +49,7 @@ void	xfs_attr_shortform_create(struct xfs_da_args *args);
 void	xfs_attr_shortform_add(struct xfs_da_args *args, int forkoff);
 int	xfs_attr_shortform_lookup(struct xfs_da_args *args);
 int	xfs_attr_shortform_getvalue(struct xfs_da_args *args);
-int	xfs_attr_shortform_to_leaf(struct xfs_da_args *args,
-			struct xfs_buf **leaf_bp);
+int	xfs_attr_shortform_to_leaf(struct xfs_da_args *args);
 int	xfs_attr_sf_removename(struct xfs_da_args *args);
 int	xfs_attr_sf_findname(struct xfs_da_args *args,
 			     struct xfs_attr_sf_entry **sfep,
diff --git a/fs/xfs/xfs_attr_item.c b/fs/xfs/xfs_attr_item.c
index 6ee905a09eb24..5077a7ad56460 100644
--- a/fs/xfs/xfs_attr_item.c
+++ b/fs/xfs/xfs_attr_item.c
@@ -455,8 +455,6 @@ static inline void
 xfs_attr_free_item(
 	struct xfs_attr_intent		*attr)
 {
-	ASSERT(attr->xattri_leaf_bp == NULL);
-
 	if (attr->xattri_da_state)
 		xfs_da_state_free(attr->xattri_da_state);
 	xfs_attri_log_nameval_put(attr->xattri_nameval);
@@ -511,10 +509,6 @@ xfs_attr_cancel_item(
 	struct xfs_attr_intent		*attr;
 
 	attr = container_of(item, struct xfs_attr_intent, xattri_list);
-	if (attr->xattri_leaf_bp) {
-		xfs_buf_relse(attr->xattri_leaf_bp);
-		attr->xattri_leaf_bp = NULL;
-	}
 	xfs_attr_free_item(attr);
 }
 
@@ -672,16 +666,6 @@ xfs_attri_item_recover(
 		if (error)
 			goto out_unlock;
 
-		/*
-		 * The defer capture structure took its own reference to the
-		 * attr leaf buffer and will give that to the continuation
-		 * transaction.  The attr intent struct drives the continuation
-		 * work, so release our refcount on the attr leaf buffer but
-		 * retain the pointer in the intent structure.
-		 */
-		if (attr->xattri_leaf_bp)
-			xfs_buf_relse(attr->xattri_leaf_bp);
-
 		xfs_iunlock(ip, XFS_ILOCK_EXCL);
 		xfs_irele(ip);
 		return 0;
@@ -692,13 +676,7 @@ xfs_attri_item_recover(
 	}
 
 	error = xfs_defer_ops_capture_and_commit(tp, capture_list);
-
 out_unlock:
-	if (attr->xattri_leaf_bp) {
-		xfs_buf_relse(attr->xattri_leaf_bp);
-		attr->xattri_leaf_bp = NULL;
-	}
-
 	xfs_iunlock(ip, XFS_ILOCK_EXCL);
 	xfs_irele(ip);
 out:
-- 
GitLab


From 8944c6fb8add384154b784a90ceca88a51a8c364 Mon Sep 17 00:00:00 2001
From: "Darrick J. Wong" <djwong@kernel.org>
Date: Sat, 25 Jun 2022 10:47:45 -0700
Subject: [PATCH 1362/1731] xfs: dont treat rt extents beyond EOF as eofblocks
 to be cleared

On a system with a realtime volume and a 28k realtime extent,
generic/491 fails because the test opens a file on a frozen filesystem
and closing it causes xfs_release -> xfs_can_free_eofblocks to
mistakenly think that the the blocks of the realtime extent beyond EOF
are posteof blocks to be freed.  Realtime extents cannot be partially
unmapped, so this is pointless.  Worse yet, this triggers posteof
cleanup, which stalls on a transaction allocation, which is why the test
fails.

Teach the predicate to account for realtime extents properly.

Reviewed-by: Dave Chinner <dchinner@redhat.com>
Signed-off-by: Darrick J. Wong <djwong@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
---
 fs/xfs/xfs_bmap_util.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/fs/xfs/xfs_bmap_util.c b/fs/xfs/xfs_bmap_util.c
index 52be58372c632..85e1a26c92e87 100644
--- a/fs/xfs/xfs_bmap_util.c
+++ b/fs/xfs/xfs_bmap_util.c
@@ -686,6 +686,8 @@ xfs_can_free_eofblocks(
 	 * forever.
 	 */
 	end_fsb = XFS_B_TO_FSB(mp, (xfs_ufsize_t)XFS_ISIZE(ip));
+	if (XFS_IS_REALTIME_INODE(ip) && mp->m_sb.sb_rextsize > 1)
+		end_fsb = roundup_64(end_fsb, mp->m_sb.sb_rextsize);
 	last_fsb = XFS_B_TO_FSB(mp, mp->m_super->s_maxbytes);
 	if (last_fsb <= end_fsb)
 		return false;
-- 
GitLab


From 8692969e9164c15474b356b9898e5b9b21a85643 Mon Sep 17 00:00:00 2001
From: Jeff Layton <jlayton@kernel.org>
Date: Mon, 6 Jun 2022 19:31:42 -0400
Subject: [PATCH 1363/1731] ceph: wait on async create before checking caps for
 syncfs

Currently, we'll call ceph_check_caps, but if we're still waiting
on the reply, we'll end up spinning around on the same inode in
flush_dirty_session_caps. Wait for the async create reply before
flushing caps.

Cc: stable@vger.kernel.org
URL: https://tracker.ceph.com/issues/55823
Fixes: fbed7045f552 ("ceph: wait for async create reply before sending any cap messages")
Signed-off-by: Jeff Layton <jlayton@kernel.org>
Reviewed-by: Xiubo Li <xiubli@redhat.com>
Signed-off-by: Ilya Dryomov <idryomov@gmail.com>
---
 fs/ceph/caps.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fs/ceph/caps.c b/fs/ceph/caps.c
index 38c930384d417..ac8fd5e7f5405 100644
--- a/fs/ceph/caps.c
+++ b/fs/ceph/caps.c
@@ -4377,6 +4377,7 @@ static void flush_dirty_session_caps(struct ceph_mds_session *s)
 		ihold(inode);
 		dout("flush_dirty_caps %llx.%llx\n", ceph_vinop(inode));
 		spin_unlock(&mdsc->cap_dirty_lock);
+		ceph_wait_on_async_create(inode);
 		ceph_check_caps(ci, CHECK_CAPS_FLUSH, NULL);
 		iput(inode);
 		spin_lock(&mdsc->cap_dirty_lock);
-- 
GitLab


From bbba251577b27422ebe173e1bd006424d6a8cfb3 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Thu, 16 Jun 2022 16:52:01 -0400
Subject: [PATCH 1364/1731] drm/amdgpu: fix adev variable used in
 amdgpu_device_gpu_recover()

Use the correct adev variable for the drm_fb_helper in
amdgpu_device_gpu_recover().  Noticed by inspection.

Fixes: 087451f372bf ("drm/amdgpu: use generic fb helpers instead of setting up AMD own's.")
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 625424f3082b6..58df107e3beba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5164,7 +5164,7 @@ int amdgpu_device_gpu_recover_imp(struct amdgpu_device *adev,
 		 */
 		amdgpu_unregister_gpu_instance(tmp_adev);
 
-		drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
+		drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true);
 
 		/* disable ras on ALL IPs */
 		if (!need_emergency_restart &&
-- 
GitLab


From 20b8264394b33adb1640a485a62a84bc1388b6a3 Mon Sep 17 00:00:00 2001
From: Carlos Llamas <cmllamas@google.com>
Date: Tue, 21 Jun 2022 20:39:21 +0000
Subject: [PATCH 1365/1731] drm/fourcc: fix integer type usage in uapi header
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Kernel uapi headers are supposed to use __[us]{8,16,32,64} types defined
by <linux/types.h> as opposed to 'uint32_t' and similar. See [1] for the
relevant discussion about this topic. In this particular case, the usage
of 'uint64_t' escaped headers_check as these macros are not being called
here. However, the following program triggers a compilation error:

  #include <drm/drm_fourcc.h>

  int main()
  {
  	unsigned long x = AMD_FMT_MOD_CLEAR(RB);
  	return 0;
  }

gcc error:
  drm.c:5:27: error: ‘uint64_t’ undeclared (first use in this function)
      5 |         unsigned long x = AMD_FMT_MOD_CLEAR(RB);
        |                           ^~~~~~~~~~~~~~~~~

This patch changes AMD_FMT_MOD_{SET,CLEAR} macros to use the correct
integer types, which fixes the above issue.

  [1] https://lkml.org/lkml/2019/6/5/18

Fixes: 8ba16d599374 ("drm/fourcc: Add AMD DRM modifiers.")
Signed-off-by: Carlos Llamas <cmllamas@google.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 include/uapi/drm/drm_fourcc.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index f1972154a5940..0980678d502dc 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -1444,11 +1444,11 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
 #define AMD_FMT_MOD_PIPE_MASK 0x7
 
 #define AMD_FMT_MOD_SET(field, value) \
-	((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
+	((__u64)(value) << AMD_FMT_MOD_##field##_SHIFT)
 #define AMD_FMT_MOD_GET(field, value) \
 	(((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
 #define AMD_FMT_MOD_CLEAR(field) \
-	(~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
+	(~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
 
 #if defined(__cplusplus)
 }
-- 
GitLab


From 5cb0e3fb2c54eabfb3f932a1574bff1774946bc0 Mon Sep 17 00:00:00 2001
From: Ruili Ji <ruiliji2@amd.com>
Date: Wed, 22 Jun 2022 14:20:22 +0800
Subject: [PATCH 1366/1731] drm/amdgpu: To flush tlb for MMHUB of RAVEN series

amdgpu: [mmhub0] no-retry page fault (src_id:0 ring:40 vmid:8 pasid:32769, for process test_basic pid 3305 thread test_basic pid 3305)
amdgpu: in page starting at address 0x00007ff990003000 from IH client 0x12 (VMC)
amdgpu: VM_L2_PROTECTION_FAULT_STATUS:0x00840051
amdgpu: Faulty UTCL2 client ID: MP1 (0x0)
amdgpu: MORE_FAULTS: 0x1
amdgpu: WALKER_ERROR: 0x0
amdgpu: PERMISSION_FAULTS: 0x5
amdgpu: MAPPING_ERROR: 0x0
amdgpu: RW: 0x1

When memory is allocated by kfd, no one triggers the tlb flush for MMHUB0.
There is page fault from MMHUB0.

v2:fix indentation
v3:change subject and fix indentation

Signed-off-by: Ruili Ji <ruiliji2@amd.com>
Reviewed-by: Philip Yang <philip.yang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 1f8161cd507f0..3b1c675aba346 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -714,7 +714,8 @@ int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 {
 	bool all_hub = false;
 
-	if (adev->family == AMDGPU_FAMILY_AI)
+	if (adev->family == AMDGPU_FAMILY_AI ||
+	    adev->family == AMDGPU_FAMILY_RV)
 		all_hub = true;
 
 	return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub);
-- 
GitLab


From a775e4e4941bf2f326aa36c58f67bd6c96cac717 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Mon, 20 Jun 2022 18:29:39 -0400
Subject: [PATCH 1367/1731] Revert "drm/amdgpu/display: set
 vblank_disable_immediate for DC"

This reverts commit 92020e81ddbeac351ea4a19bcf01743f32b9c800.

This causes stuttering and timeouts with DMCUB for some users
so revert it until we understand why and safely enable it
to save power.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1887
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c           | 1 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ---
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index b4cf8717f554e..89011bae7588e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -320,6 +320,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
 	if (!amdgpu_device_has_dc_support(adev)) {
 		if (!adev->enable_virtual_display)
 			/* Disable vblank IRQs aggressively for power-saving */
+			/* XXX: can this be enabled for DC? */
 			adev_to_drm(adev)->vblank_disable_immediate = true;
 
 		r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 39b425d83bb1a..9dd2e0601ea8c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4259,9 +4259,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 		}
 	}
 
-	/* Disable vblank IRQs aggressively for power-saving. */
-	adev_to_drm(adev)->vblank_disable_immediate = true;
-
 	/* loops over all connectors on the board */
 	for (i = 0; i < link_cnt; i++) {
 		struct dc_link *link = NULL;
-- 
GitLab


From 8ad59b397f86a4d8014966fdc0552095a0c4fb2b Mon Sep 17 00:00:00 2001
From: Jean Delvare <jdelvare@suse.de>
Date: Wed, 22 Jun 2022 08:37:43 +0200
Subject: [PATCH 1368/1731] i2c: piix4: Fix a memory leak in the EFCH MMIO
 support

The recently added support for EFCH MMIO regions introduced a memory
leak in that code path. The leak is caused by the fact that
release_resource() merely removes the resource from the tree but does
not free its memory. We need to call release_mem_region() instead,
which does free the memory. As a nice side effect, this brings back
some symmetry between the legacy and MMIO paths.

Signed-off-by: Jean Delvare <jdelvare@suse.de>
Reported-by: Yi Zhang <yi.zhang@redhat.com>
Tested-by: Yi Zhang <yi.zhang@redhat.com>
Reviewed-by: Terry Bowman <terry.bowman@amd.com>
Tested-by: Terry Bowman <Terry.Bowman@amd.com>
Fixes: 7c148722d074 ("i2c: piix4: Add EFCH MMIO support to region request and release")
Signed-off-by: Wolfram Sang <wsa@kernel.org>
---
 drivers/i2c/busses/i2c-piix4.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c
index ac8e7d60672a1..39cb1b7bb8656 100644
--- a/drivers/i2c/busses/i2c-piix4.c
+++ b/drivers/i2c/busses/i2c-piix4.c
@@ -161,7 +161,6 @@ static const char *piix4_aux_port_name_sb800 = " port 1";
 
 struct sb800_mmio_cfg {
 	void __iomem *addr;
-	struct resource *res;
 	bool use_mmio;
 };
 
@@ -179,13 +178,11 @@ static int piix4_sb800_region_request(struct device *dev,
 				      struct sb800_mmio_cfg *mmio_cfg)
 {
 	if (mmio_cfg->use_mmio) {
-		struct resource *res;
 		void __iomem *addr;
 
-		res = request_mem_region_muxed(SB800_PIIX4_FCH_PM_ADDR,
-					       SB800_PIIX4_FCH_PM_SIZE,
-					       "sb800_piix4_smb");
-		if (!res) {
+		if (!request_mem_region_muxed(SB800_PIIX4_FCH_PM_ADDR,
+					      SB800_PIIX4_FCH_PM_SIZE,
+					      "sb800_piix4_smb")) {
 			dev_err(dev,
 				"SMBus base address memory region 0x%x already in use.\n",
 				SB800_PIIX4_FCH_PM_ADDR);
@@ -195,12 +192,12 @@ static int piix4_sb800_region_request(struct device *dev,
 		addr = ioremap(SB800_PIIX4_FCH_PM_ADDR,
 			       SB800_PIIX4_FCH_PM_SIZE);
 		if (!addr) {
-			release_resource(res);
+			release_mem_region(SB800_PIIX4_FCH_PM_ADDR,
+					   SB800_PIIX4_FCH_PM_SIZE);
 			dev_err(dev, "SMBus base address mapping failed.\n");
 			return -ENOMEM;
 		}
 
-		mmio_cfg->res = res;
 		mmio_cfg->addr = addr;
 
 		return 0;
@@ -222,7 +219,8 @@ static void piix4_sb800_region_release(struct device *dev,
 {
 	if (mmio_cfg->use_mmio) {
 		iounmap(mmio_cfg->addr);
-		release_resource(mmio_cfg->res);
+		release_mem_region(SB800_PIIX4_FCH_PM_ADDR,
+				   SB800_PIIX4_FCH_PM_SIZE);
 		return;
 	}
 
-- 
GitLab


From 57e00b40033a376de3f3cf0bb9bf7590d2dd679d Mon Sep 17 00:00:00 2001
From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
Date: Tue, 14 Jun 2022 13:06:59 +0200
Subject: [PATCH 1369/1731] PM / devfreq: Fix kernel panic with cpu based
 scaling to passive gov

The cpufreq passive register notifier can PROBE_DEFER and the devfreq
struct is freed and then reallocaed on probe retry.
The current logic assume that the code can't PROBE_DEFER so the devfreq
struct in the this variable in devfreq_passive_data is assumed to be
(if already set) always correct.
This cause kernel panic as the code try to access the wrong address.
To correctly handle this, update the this variable in
devfreq_passive_data to the devfreq reallocated struct.

Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor")
Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 drivers/devfreq/governor_passive.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_passive.c
index 72c67979ebe11..091a69e1f4877 100644
--- a/drivers/devfreq/governor_passive.c
+++ b/drivers/devfreq/governor_passive.c
@@ -407,8 +407,7 @@ static int devfreq_passive_event_handler(struct devfreq *devfreq,
 	if (!p_data)
 		return -EINVAL;
 
-	if (!p_data->this)
-		p_data->this = devfreq;
+	p_data->this = devfreq;
 
 	switch (event) {
 	case DEVFREQ_GOV_START:
-- 
GitLab


From e52b045fe07d7874474665c843befa7521853234 Mon Sep 17 00:00:00 2001
From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
Date: Wed, 15 Jun 2022 01:09:50 +0200
Subject: [PATCH 1370/1731] PM / devfreq: Mute warning on governor PROBE_DEFER

Don't print warning when a governor PROBE_DEFER as it's not a real
GOV_START fail.

Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor")
Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 drivers/devfreq/devfreq.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index 01474daf45483..80a1235ef8fb7 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -932,8 +932,9 @@ struct devfreq *devfreq_add_device(struct device *dev,
 	err = devfreq->governor->event_handler(devfreq, DEVFREQ_GOV_START,
 						NULL);
 	if (err) {
-		dev_err(dev, "%s: Unable to start governor for the device\n",
-			__func__);
+		dev_err_probe(dev, err,
+			"%s: Unable to start governor for the device\n",
+			 __func__);
 		goto err_init;
 	}
 	create_sysfs_files(devfreq, devfreq->governor);
-- 
GitLab


From 0cca7e8dcfa9e6fe7ba697e534a732571f1689d0 Mon Sep 17 00:00:00 2001
From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
Date: Wed, 15 Jun 2022 01:09:47 +0200
Subject: [PATCH 1371/1731] PM / devfreq: Fix cpufreq passive unregister
 erroring on PROBE_DEFER

With the passive governor, the cpu based scaling can PROBE_DEFER due to
the fact that CPU policy are not ready.
The cpufreq passive unregister notifier is called both from the
GOV_START errors and for the GOV_STOP and assume the notifier is
successfully registred every time. With GOV_START failing it's wrong to
loop over each possible CPU since the register path has failed for
some CPU policy not ready. Change the logic and unregister the notifer
based on the current allocated parent_cpu_data list to correctly handle
errors and the governor unregister path.

Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor")
Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 drivers/devfreq/governor_passive.c | 39 +++++++++++++-----------------
 1 file changed, 17 insertions(+), 22 deletions(-)

diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_passive.c
index 091a69e1f4877..a35b39ac656cd 100644
--- a/drivers/devfreq/governor_passive.c
+++ b/drivers/devfreq/governor_passive.c
@@ -34,6 +34,20 @@ get_parent_cpu_data(struct devfreq_passive_data *p_data,
 	return NULL;
 }
 
+static void delete_parent_cpu_data(struct devfreq_passive_data *p_data)
+{
+	struct devfreq_cpu_data *parent_cpu_data, *tmp;
+
+	list_for_each_entry_safe(parent_cpu_data, tmp, &p_data->cpu_data_list, node) {
+		list_del(&parent_cpu_data->node);
+
+		if (parent_cpu_data->opp_table)
+			dev_pm_opp_put_opp_table(parent_cpu_data->opp_table);
+
+		kfree(parent_cpu_data);
+	}
+}
+
 static unsigned long get_target_freq_by_required_opp(struct device *p_dev,
 						struct opp_table *p_opp_table,
 						struct opp_table *opp_table,
@@ -222,8 +236,7 @@ static int cpufreq_passive_unregister_notifier(struct devfreq *devfreq)
 {
 	struct devfreq_passive_data *p_data
 			= (struct devfreq_passive_data *)devfreq->data;
-	struct devfreq_cpu_data *parent_cpu_data;
-	int cpu, ret = 0;
+	int ret;
 
 	if (p_data->nb.notifier_call) {
 		ret = cpufreq_unregister_notifier(&p_data->nb,
@@ -232,27 +245,9 @@ static int cpufreq_passive_unregister_notifier(struct devfreq *devfreq)
 			return ret;
 	}
 
-	for_each_possible_cpu(cpu) {
-		struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
-		if (!policy) {
-			ret = -EINVAL;
-			continue;
-		}
-
-		parent_cpu_data = get_parent_cpu_data(p_data, policy);
-		if (!parent_cpu_data) {
-			cpufreq_cpu_put(policy);
-			continue;
-		}
-
-		list_del(&parent_cpu_data->node);
-		if (parent_cpu_data->opp_table)
-			dev_pm_opp_put_opp_table(parent_cpu_data->opp_table);
-		kfree(parent_cpu_data);
-		cpufreq_cpu_put(policy);
-	}
+	delete_parent_cpu_data(p_data);
 
-	return ret;
+	return 0;
 }
 
 static int cpufreq_passive_register_notifier(struct devfreq *devfreq)
-- 
GitLab


From 20e6c3cc90c0a86dba659dd9e7d60b429d88746d Mon Sep 17 00:00:00 2001
From: Yicong Yang <yangyicong@hisilicon.com>
Date: Fri, 10 Jun 2022 15:54:28 +0800
Subject: [PATCH 1372/1731] PM / devfreq: passive: Use HZ_PER_KHZ macro in
 units.h

HZ macros has been centralized in units.h since [1]. Use it to avoid
duplicated definition.

[1] commit e2c77032fcbe ("units: add the HZ macros")

Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 drivers/devfreq/governor_passive.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_passive.c
index a35b39ac656cd..69e06725d92b6 100644
--- a/drivers/devfreq/governor_passive.c
+++ b/drivers/devfreq/governor_passive.c
@@ -14,10 +14,9 @@
 #include <linux/slab.h>
 #include <linux/device.h>
 #include <linux/devfreq.h>
+#include <linux/units.h>
 #include "governor.h"
 
-#define HZ_PER_KHZ	1000
-
 static struct devfreq_cpu_data *
 get_parent_cpu_data(struct devfreq_passive_data *p_data,
 		    struct cpufreq_policy *policy)
-- 
GitLab


From f44b799603a9b5d2e375b0b2d54dd0b791eddfc2 Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Thu, 26 May 2022 12:28:56 +0400
Subject: [PATCH 1373/1731] PM / devfreq: exynos-ppmu: Fix refcount leak in
 of_get_devfreq_events

of_get_child_by_name() returns a node pointer with refcount
incremented, we should use of_node_put() on it when done.
This function only calls of_node_put() in normal path,
missing it in error paths.
Add missing of_node_put() to avoid refcount leak.

Fixes: f262f28c1470 ("PM / devfreq: event: Add devfreq_event class")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 drivers/devfreq/event/exynos-ppmu.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/devfreq/event/exynos-ppmu.c b/drivers/devfreq/event/exynos-ppmu.c
index 9b849d7811167..a443e7c42dafa 100644
--- a/drivers/devfreq/event/exynos-ppmu.c
+++ b/drivers/devfreq/event/exynos-ppmu.c
@@ -519,15 +519,19 @@ static int of_get_devfreq_events(struct device_node *np,
 
 	count = of_get_child_count(events_np);
 	desc = devm_kcalloc(dev, count, sizeof(*desc), GFP_KERNEL);
-	if (!desc)
+	if (!desc) {
+		of_node_put(events_np);
 		return -ENOMEM;
+	}
 	info->num_events = count;
 
 	of_id = of_match_device(exynos_ppmu_id_match, dev);
 	if (of_id)
 		info->ppmu_type = (enum exynos_ppmu_type)of_id->data;
-	else
+	else {
+		of_node_put(events_np);
 		return -EINVAL;
+	}
 
 	j = 0;
 	for_each_child_of_node(events_np, node) {
-- 
GitLab


From b5d281f6c16dd432b618bdfd36ddba1a58d5b603 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Mon, 20 Jun 2022 00:03:51 +0200
Subject: [PATCH 1374/1731] PM / devfreq: Rework freq_table to be local to
 devfreq struct

On a devfreq PROBE_DEFER, the freq_table in the driver profile struct,
is never reset and may be leaved in an undefined state.

This comes from the fact that we store the freq_table in the driver
profile struct that is commonly defined as static and not reset on
PROBE_DEFER.
We currently skip the reinit of the freq_table if we found
it's already defined since a driver may declare his own freq_table.

This logic is flawed in the case devfreq core generate a freq_table, set
it in the profile struct and then PROBE_DEFER, freeing the freq_table.
In this case devfreq will found a NOT NULL freq_table that has been
freed, skip the freq_table generation and probe the driver based on the
wrong table.

To fix this and correctly handle PROBE_DEFER, use a local freq_table and
max_state in the devfreq struct and never modify the freq_table present
in the profile struct if it does provide it.

Fixes: 0ec09ac2cebe ("PM / devfreq: Set the freq_table of devfreq device")
Cc: stable@vger.kernel.org
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 drivers/devfreq/devfreq.c          | 71 ++++++++++++++----------------
 drivers/devfreq/governor_passive.c | 14 +++---
 include/linux/devfreq.h            |  5 +++
 3 files changed, 46 insertions(+), 44 deletions(-)

diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index 80a1235ef8fb7..9602141bb8ec4 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -123,7 +123,7 @@ void devfreq_get_freq_range(struct devfreq *devfreq,
 			    unsigned long *min_freq,
 			    unsigned long *max_freq)
 {
-	unsigned long *freq_table = devfreq->profile->freq_table;
+	unsigned long *freq_table = devfreq->freq_table;
 	s32 qos_min_freq, qos_max_freq;
 
 	lockdep_assert_held(&devfreq->lock);
@@ -133,11 +133,11 @@ void devfreq_get_freq_range(struct devfreq *devfreq,
 	 * The devfreq drivers can initialize this in either ascending or
 	 * descending order and devfreq core supports both.
 	 */
-	if (freq_table[0] < freq_table[devfreq->profile->max_state - 1]) {
+	if (freq_table[0] < freq_table[devfreq->max_state - 1]) {
 		*min_freq = freq_table[0];
-		*max_freq = freq_table[devfreq->profile->max_state - 1];
+		*max_freq = freq_table[devfreq->max_state - 1];
 	} else {
-		*min_freq = freq_table[devfreq->profile->max_state - 1];
+		*min_freq = freq_table[devfreq->max_state - 1];
 		*max_freq = freq_table[0];
 	}
 
@@ -169,8 +169,8 @@ static int devfreq_get_freq_level(struct devfreq *devfreq, unsigned long freq)
 {
 	int lev;
 
-	for (lev = 0; lev < devfreq->profile->max_state; lev++)
-		if (freq == devfreq->profile->freq_table[lev])
+	for (lev = 0; lev < devfreq->max_state; lev++)
+		if (freq == devfreq->freq_table[lev])
 			return lev;
 
 	return -EINVAL;
@@ -178,7 +178,6 @@ static int devfreq_get_freq_level(struct devfreq *devfreq, unsigned long freq)
 
 static int set_freq_table(struct devfreq *devfreq)
 {
-	struct devfreq_dev_profile *profile = devfreq->profile;
 	struct dev_pm_opp *opp;
 	unsigned long freq;
 	int i, count;
@@ -188,25 +187,22 @@ static int set_freq_table(struct devfreq *devfreq)
 	if (count <= 0)
 		return -EINVAL;
 
-	profile->max_state = count;
-	profile->freq_table = devm_kcalloc(devfreq->dev.parent,
-					profile->max_state,
-					sizeof(*profile->freq_table),
-					GFP_KERNEL);
-	if (!profile->freq_table) {
-		profile->max_state = 0;
+	devfreq->max_state = count;
+	devfreq->freq_table = devm_kcalloc(devfreq->dev.parent,
+					   devfreq->max_state,
+					   sizeof(*devfreq->freq_table),
+					   GFP_KERNEL);
+	if (!devfreq->freq_table)
 		return -ENOMEM;
-	}
 
-	for (i = 0, freq = 0; i < profile->max_state; i++, freq++) {
+	for (i = 0, freq = 0; i < devfreq->max_state; i++, freq++) {
 		opp = dev_pm_opp_find_freq_ceil(devfreq->dev.parent, &freq);
 		if (IS_ERR(opp)) {
-			devm_kfree(devfreq->dev.parent, profile->freq_table);
-			profile->max_state = 0;
+			devm_kfree(devfreq->dev.parent, devfreq->freq_table);
 			return PTR_ERR(opp);
 		}
 		dev_pm_opp_put(opp);
-		profile->freq_table[i] = freq;
+		devfreq->freq_table[i] = freq;
 	}
 
 	return 0;
@@ -246,7 +242,7 @@ int devfreq_update_status(struct devfreq *devfreq, unsigned long freq)
 
 	if (lev != prev_lev) {
 		devfreq->stats.trans_table[
-			(prev_lev * devfreq->profile->max_state) + lev]++;
+			(prev_lev * devfreq->max_state) + lev]++;
 		devfreq->stats.total_trans++;
 	}
 
@@ -835,6 +831,9 @@ struct devfreq *devfreq_add_device(struct device *dev,
 		if (err < 0)
 			goto err_dev;
 		mutex_lock(&devfreq->lock);
+	} else {
+		devfreq->freq_table = devfreq->profile->freq_table;
+		devfreq->max_state = devfreq->profile->max_state;
 	}
 
 	devfreq->scaling_min_freq = find_available_min_freq(devfreq);
@@ -870,8 +869,8 @@ struct devfreq *devfreq_add_device(struct device *dev,
 
 	devfreq->stats.trans_table = devm_kzalloc(&devfreq->dev,
 			array3_size(sizeof(unsigned int),
-				    devfreq->profile->max_state,
-				    devfreq->profile->max_state),
+				    devfreq->max_state,
+				    devfreq->max_state),
 			GFP_KERNEL);
 	if (!devfreq->stats.trans_table) {
 		mutex_unlock(&devfreq->lock);
@@ -880,7 +879,7 @@ struct devfreq *devfreq_add_device(struct device *dev,
 	}
 
 	devfreq->stats.time_in_state = devm_kcalloc(&devfreq->dev,
-			devfreq->profile->max_state,
+			devfreq->max_state,
 			sizeof(*devfreq->stats.time_in_state),
 			GFP_KERNEL);
 	if (!devfreq->stats.time_in_state) {
@@ -1666,9 +1665,9 @@ static ssize_t available_frequencies_show(struct device *d,
 
 	mutex_lock(&df->lock);
 
-	for (i = 0; i < df->profile->max_state; i++)
+	for (i = 0; i < df->max_state; i++)
 		count += scnprintf(&buf[count], (PAGE_SIZE - count - 2),
-				"%lu ", df->profile->freq_table[i]);
+				"%lu ", df->freq_table[i]);
 
 	mutex_unlock(&df->lock);
 	/* Truncate the trailing space */
@@ -1691,7 +1690,7 @@ static ssize_t trans_stat_show(struct device *dev,
 
 	if (!df->profile)
 		return -EINVAL;
-	max_state = df->profile->max_state;
+	max_state = df->max_state;
 
 	if (max_state == 0)
 		return sprintf(buf, "Not Supported.\n");
@@ -1708,19 +1707,17 @@ static ssize_t trans_stat_show(struct device *dev,
 	len += sprintf(buf + len, "           :");
 	for (i = 0; i < max_state; i++)
 		len += sprintf(buf + len, "%10lu",
-				df->profile->freq_table[i]);
+				df->freq_table[i]);
 
 	len += sprintf(buf + len, "   time(ms)\n");
 
 	for (i = 0; i < max_state; i++) {
-		if (df->profile->freq_table[i]
-					== df->previous_freq) {
+		if (df->freq_table[i] == df->previous_freq)
 			len += sprintf(buf + len, "*");
-		} else {
+		else
 			len += sprintf(buf + len, " ");
-		}
-		len += sprintf(buf + len, "%10lu:",
-				df->profile->freq_table[i]);
+
+		len += sprintf(buf + len, "%10lu:", df->freq_table[i]);
 		for (j = 0; j < max_state; j++)
 			len += sprintf(buf + len, "%10u",
 				df->stats.trans_table[(i * max_state) + j]);
@@ -1744,7 +1741,7 @@ static ssize_t trans_stat_store(struct device *dev,
 	if (!df->profile)
 		return -EINVAL;
 
-	if (df->profile->max_state == 0)
+	if (df->max_state == 0)
 		return count;
 
 	err = kstrtoint(buf, 10, &value);
@@ -1752,11 +1749,11 @@ static ssize_t trans_stat_store(struct device *dev,
 		return -EINVAL;
 
 	mutex_lock(&df->lock);
-	memset(df->stats.time_in_state, 0, (df->profile->max_state *
+	memset(df->stats.time_in_state, 0, (df->max_state *
 					sizeof(*df->stats.time_in_state)));
 	memset(df->stats.trans_table, 0, array3_size(sizeof(unsigned int),
-					df->profile->max_state,
-					df->profile->max_state));
+					df->max_state,
+					df->max_state));
 	df->stats.total_trans = 0;
 	df->stats.last_update = get_jiffies_64();
 	mutex_unlock(&df->lock);
diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_passive.c
index 69e06725d92b6..406ef79c0c461 100644
--- a/drivers/devfreq/governor_passive.c
+++ b/drivers/devfreq/governor_passive.c
@@ -144,18 +144,18 @@ static int get_target_freq_with_devfreq(struct devfreq *devfreq,
 		goto out;
 
 	/* Use interpolation if required opps is not available */
-	for (i = 0; i < parent_devfreq->profile->max_state; i++)
-		if (parent_devfreq->profile->freq_table[i] == *freq)
+	for (i = 0; i < parent_devfreq->max_state; i++)
+		if (parent_devfreq->freq_table[i] == *freq)
 			break;
 
-	if (i == parent_devfreq->profile->max_state)
+	if (i == parent_devfreq->max_state)
 		return -EINVAL;
 
-	if (i < devfreq->profile->max_state) {
-		child_freq = devfreq->profile->freq_table[i];
+	if (i < devfreq->max_state) {
+		child_freq = devfreq->freq_table[i];
 	} else {
-		count = devfreq->profile->max_state;
-		child_freq = devfreq->profile->freq_table[count - 1];
+		count = devfreq->max_state;
+		child_freq = devfreq->freq_table[count - 1];
 	}
 
 out:
diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h
index dc10bee75a729..34aab4dd336c8 100644
--- a/include/linux/devfreq.h
+++ b/include/linux/devfreq.h
@@ -148,6 +148,8 @@ struct devfreq_stats {
  *		reevaluate operable frequencies. Devfreq users may use
  *		devfreq.nb to the corresponding register notifier call chain.
  * @work:	delayed work for load monitoring.
+ * @freq_table:		current frequency table used by the devfreq driver.
+ * @max_state:		count of entry present in the frequency table.
  * @previous_freq:	previously configured frequency value.
  * @last_status:	devfreq user device info, performance statistics
  * @data:	Private data of the governor. The devfreq framework does not
@@ -185,6 +187,9 @@ struct devfreq {
 	struct notifier_block nb;
 	struct delayed_work work;
 
+	unsigned long *freq_table;
+	unsigned int max_state;
+
 	unsigned long previous_freq;
 	struct devfreq_dev_status last_status;
 
-- 
GitLab


From 82c66d2bbbeda9e493487e7413769087a0b46250 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Mon, 20 Jun 2022 00:29:39 +0200
Subject: [PATCH 1375/1731] PM / devfreq: Fix kernel warning with cpufreq
 passive register fail

Remove cpufreq_passive_unregister_notifier from
cpufreq_passive_register_notifier in case of error as devfreq core
already call unregister on GOV_START fail.

This fix the kernel always printing a WARN on governor PROBE_DEFER as
cpufreq_passive_unregister_notifier is called two times and return
error on the second call as the cpufreq is already unregistered.

Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 drivers/devfreq/governor_passive.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_passive.c
index 406ef79c0c461..bce487cc8f3eb 100644
--- a/drivers/devfreq/governor_passive.c
+++ b/drivers/devfreq/governor_passive.c
@@ -330,7 +330,6 @@ err_free_cpu_data:
 err_put_policy:
 	cpufreq_cpu_put(policy);
 err:
-	WARN_ON(cpufreq_passive_unregister_notifier(devfreq));
 
 	return ret;
 }
-- 
GitLab


From f08fe6fcbe13f83558ecccc4acaf5af3dce71a1f Mon Sep 17 00:00:00 2001
From: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Date: Tue, 28 Jun 2022 07:34:11 +0200
Subject: [PATCH 1376/1731] PM / devfreq: passive: revert an editing accident
 in SPDX-License line

Commit 26984d9d581e ("PM / devfreq: passive: Keep cpufreq_policy for
possible cpus") reworked governor_passive.c, and accidently added a
tab in the first line, i.e., the SPDX-License-Identifier line.

The checkpatch script warns with the SPDX_LICENSE_TAG warning, and hence
pointed this issue out while investigating checkpatch warnings.

Revert this editing accident. No functional change.

Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 drivers/devfreq/governor_passive.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_passive.c
index bce487cc8f3eb..953cf9a1e9f7f 100644
--- a/drivers/devfreq/governor_passive.c
+++ b/drivers/devfreq/governor_passive.c
@@ -1,4 +1,4 @@
-	// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * linux/drivers/devfreq/governor_passive.c
  *
-- 
GitLab


From 1bbb2809040a1f9c7c53c9f06c21aa83275ed27b Mon Sep 17 00:00:00 2001
From: Eddie James <eajames@linux.ibm.com>
Date: Tue, 28 Jun 2022 15:30:29 -0500
Subject: [PATCH 1377/1731] hwmon: (occ) Prevent power cap command overwriting
 poll response

Currently, the response to the power cap command overwrites the
first eight bytes of the poll response, since the commands use
the same buffer. This means that user's get the wrong data between
the time of sending the power cap and the next poll response update.
Fix this by specifying a different buffer for the power cap command
response.

Fixes: 5b5513b88002 ("hwmon: Add On-Chip Controller (OCC) hwmon driver")
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Link: https://lore.kernel.org/r/20220628203029.51747-1-eajames@linux.ibm.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
---
 drivers/hwmon/occ/common.c |  5 +++--
 drivers/hwmon/occ/common.h |  3 ++-
 drivers/hwmon/occ/p8_i2c.c | 13 +++++++------
 drivers/hwmon/occ/p9_sbe.c |  7 +++----
 4 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/hwmon/occ/common.c b/drivers/hwmon/occ/common.c
index ea070b91e5b98..157b73a3da29f 100644
--- a/drivers/hwmon/occ/common.c
+++ b/drivers/hwmon/occ/common.c
@@ -145,7 +145,7 @@ static int occ_poll(struct occ *occ)
 	cmd[6] = 0;			/* checksum lsb */
 
 	/* mutex should already be locked if necessary */
-	rc = occ->send_cmd(occ, cmd, sizeof(cmd));
+	rc = occ->send_cmd(occ, cmd, sizeof(cmd), &occ->resp, sizeof(occ->resp));
 	if (rc) {
 		occ->last_error = rc;
 		if (occ->error_count++ > OCC_ERROR_COUNT_THRESHOLD)
@@ -182,6 +182,7 @@ static int occ_set_user_power_cap(struct occ *occ, u16 user_power_cap)
 {
 	int rc;
 	u8 cmd[8];
+	u8 resp[8];
 	__be16 user_power_cap_be = cpu_to_be16(user_power_cap);
 
 	cmd[0] = 0;	/* sequence number */
@@ -198,7 +199,7 @@ static int occ_set_user_power_cap(struct occ *occ, u16 user_power_cap)
 	if (rc)
 		return rc;
 
-	rc = occ->send_cmd(occ, cmd, sizeof(cmd));
+	rc = occ->send_cmd(occ, cmd, sizeof(cmd), resp, sizeof(resp));
 
 	mutex_unlock(&occ->lock);
 
diff --git a/drivers/hwmon/occ/common.h b/drivers/hwmon/occ/common.h
index 64d5ec7e169b0..7ac4b2febce65 100644
--- a/drivers/hwmon/occ/common.h
+++ b/drivers/hwmon/occ/common.h
@@ -96,7 +96,8 @@ struct occ {
 
 	int powr_sample_time_us;	/* average power sample time */
 	u8 poll_cmd_data;		/* to perform OCC poll command */
-	int (*send_cmd)(struct occ *occ, u8 *cmd, size_t len);
+	int (*send_cmd)(struct occ *occ, u8 *cmd, size_t len, void *resp,
+			size_t resp_len);
 
 	unsigned long next_update;
 	struct mutex lock;		/* lock OCC access */
diff --git a/drivers/hwmon/occ/p8_i2c.c b/drivers/hwmon/occ/p8_i2c.c
index da39ea28df312..b221be1f35f31 100644
--- a/drivers/hwmon/occ/p8_i2c.c
+++ b/drivers/hwmon/occ/p8_i2c.c
@@ -111,7 +111,8 @@ static int p8_i2c_occ_putscom_be(struct i2c_client *client, u32 address,
 				      be32_to_cpu(data1));
 }
 
-static int p8_i2c_occ_send_cmd(struct occ *occ, u8 *cmd, size_t len)
+static int p8_i2c_occ_send_cmd(struct occ *occ, u8 *cmd, size_t len,
+			       void *resp, size_t resp_len)
 {
 	int i, rc;
 	unsigned long start;
@@ -120,7 +121,7 @@ static int p8_i2c_occ_send_cmd(struct occ *occ, u8 *cmd, size_t len)
 	const long wait_time = msecs_to_jiffies(OCC_CMD_IN_PRG_WAIT_MS);
 	struct p8_i2c_occ *ctx = to_p8_i2c_occ(occ);
 	struct i2c_client *client = ctx->client;
-	struct occ_response *resp = &occ->resp;
+	struct occ_response *or = (struct occ_response *)resp;
 
 	start = jiffies;
 
@@ -151,7 +152,7 @@ static int p8_i2c_occ_send_cmd(struct occ *occ, u8 *cmd, size_t len)
 			return rc;
 
 		/* wait for OCC */
-		if (resp->return_status == OCC_RESP_CMD_IN_PRG) {
+		if (or->return_status == OCC_RESP_CMD_IN_PRG) {
 			rc = -EALREADY;
 
 			if (time_after(jiffies, start + timeout))
@@ -163,7 +164,7 @@ static int p8_i2c_occ_send_cmd(struct occ *occ, u8 *cmd, size_t len)
 	} while (rc);
 
 	/* check the OCC response */
-	switch (resp->return_status) {
+	switch (or->return_status) {
 	case OCC_RESP_CMD_IN_PRG:
 		rc = -ETIMEDOUT;
 		break;
@@ -192,8 +193,8 @@ static int p8_i2c_occ_send_cmd(struct occ *occ, u8 *cmd, size_t len)
 	if (rc < 0)
 		return rc;
 
-	data_length = get_unaligned_be16(&resp->data_length);
-	if (data_length > OCC_RESP_DATA_BYTES)
+	data_length = get_unaligned_be16(&or->data_length);
+	if ((data_length + 7) > resp_len)
 		return -EMSGSIZE;
 
 	/* fetch the rest of the response data */
diff --git a/drivers/hwmon/occ/p9_sbe.c b/drivers/hwmon/occ/p9_sbe.c
index 42fc7b97bb34b..a91937e28e12b 100644
--- a/drivers/hwmon/occ/p9_sbe.c
+++ b/drivers/hwmon/occ/p9_sbe.c
@@ -78,11 +78,10 @@ done:
 	return notify;
 }
 
-static int p9_sbe_occ_send_cmd(struct occ *occ, u8 *cmd, size_t len)
+static int p9_sbe_occ_send_cmd(struct occ *occ, u8 *cmd, size_t len,
+			       void *resp, size_t resp_len)
 {
-	struct occ_response *resp = &occ->resp;
 	struct p9_sbe_occ *ctx = to_p9_sbe_occ(occ);
-	size_t resp_len = sizeof(*resp);
 	int rc;
 
 	rc = fsi_occ_submit(ctx->sbe, cmd, len, resp, &resp_len);
@@ -96,7 +95,7 @@ static int p9_sbe_occ_send_cmd(struct occ *occ, u8 *cmd, size_t len)
 		return rc;
 	}
 
-	switch (resp->return_status) {
+	switch (((struct occ_response *)resp)->return_status) {
 	case OCC_RESP_CMD_IN_PRG:
 		rc = -ETIMEDOUT;
 		break;
-- 
GitLab


From f0aa153b6ce8018a052d9c05dc1b8483ac3a0f1a Mon Sep 17 00:00:00 2001
From: Jiang Jian <jiangjian@cdjrlc.com>
Date: Wed, 22 Jun 2022 14:32:31 +0800
Subject: [PATCH 1378/1731] hwmon: (pmbus/ucd9200) fix typos in comments

Drop the redundant word 'the' in the comments following
    /*
     * Set PHASE registers on all pages to 0xff to ensure that phase
     * specific commands will apply to all phases of a given page (rail).
     * This only affects the READ_IOUT and READ_TEMPERATURE2 registers.
     * READ_IOUT will return the sum of currents of all phases of a rail,
     * and READ_TEMPERATURE2 will return the maximum temperature detected
     * for the [the - DROP] phases of the rail.
     */

Signed-off-by: Jiang Jian <jiangjian@cdjrlc.com>
Link: https://lore.kernel.org/r/20220622063231.20612-1-jiangjian@cdjrlc.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
---
 drivers/hwmon/pmbus/ucd9200.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/hwmon/pmbus/ucd9200.c b/drivers/hwmon/pmbus/ucd9200.c
index 6bc3273e31e72..3ad375a76f3ec 100644
--- a/drivers/hwmon/pmbus/ucd9200.c
+++ b/drivers/hwmon/pmbus/ucd9200.c
@@ -148,7 +148,7 @@ static int ucd9200_probe(struct i2c_client *client)
 	 * This only affects the READ_IOUT and READ_TEMPERATURE2 registers.
 	 * READ_IOUT will return the sum of currents of all phases of a rail,
 	 * and READ_TEMPERATURE2 will return the maximum temperature detected
-	 * for the the phases of the rail.
+	 * for the phases of the rail.
 	 */
 	for (i = 0; i < info->pages; i++) {
 		/*
-- 
GitLab


From 0b58162e1207db5052d1fadd5a16eeb90720d765 Mon Sep 17 00:00:00 2001
From: "Souptick Joarder (HPE)" <jrdr.linux@gmail.com>
Date: Sat, 25 Jun 2022 07:11:57 +0530
Subject: [PATCH 1379/1731] drm/amd/display: Removed unused variable ret

Kernel test robot throws below warning ->

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:
In function 'dc_link_reduce_mst_payload':
   drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:3782:32:
warning: variable 'ret' set but not used [-Wunused-but-set-variable]
    3782 |         enum act_return_status ret;

Removed the unused ret variable.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Souptick Joarder (HPE) <jrdr.linux@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 1206a3dd746f9..518a63f454428 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3783,7 +3783,6 @@ enum dc_status dc_link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw
 	struct fixed31_32 pbn_per_slot;
 	struct dp_mst_stream_allocation_table proposed_table = {0};
 	uint8_t i;
-	enum act_return_status ret;
 	const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
 	DC_LOGGER_INIT(link->ctx->logger);
 
@@ -3857,7 +3856,7 @@ enum dc_status dc_link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw
 			&link->mst_stream_alloc_table);
 
 	/* poll for immediate branch device ACT handled */
-	ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
+	dm_helpers_dp_mst_poll_for_allocation_change_trigger(
 			stream->ctx,
 			stream);
 
-- 
GitLab


From d193b12b2fa6dc316e3ee8871b4ec05992bcb7b1 Mon Sep 17 00:00:00 2001
From: Kent Russell <kent.russell@amd.com>
Date: Tue, 28 Jun 2022 10:40:59 -0400
Subject: [PATCH 1380/1731] drm/amdgpu: Fix typos in amdgpu_stop_pending_resets

Change amdggpu to amdgpu and pedning to pending

Signed-off-by: Kent Russell <kent.russell@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 0a1c47ccd1ea7..41f68b3427f24 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5076,7 +5076,7 @@ retry:
 	}
 }
 
-static inline void amdggpu_device_stop_pedning_resets(struct amdgpu_device *adev)
+static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev)
 {
 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 
@@ -5257,7 +5257,7 @@ retry:	/* Rest of adevs pre asic reset from XGMI hive. */
 		 * Drop all pending non scheduler resets. Scheduler resets
 		 * were already dropped during drm_sched_stop
 		 */
-		amdggpu_device_stop_pedning_resets(tmp_adev);
+		amdgpu_device_stop_pending_resets(tmp_adev);
 	}
 
 	tmp_vram_lost_counter = atomic_read(&((adev)->vram_lost_counter));
-- 
GitLab


From 7bb97c5a39ecebc8ff5db1491fe4e7a8129f93d5 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Thu, 23 Jun 2022 12:34:18 -0400
Subject: [PATCH 1381/1731] drm/amdgpu/display: drop set but unused variable

No longer used so drop it.

Fixes: ec457f837890 ("drm/amd/display: Drop unnecessary detect link code")
Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 518a63f454428..335ca5b14fa7d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1022,7 +1022,6 @@ static bool detect_link_and_local_sink(struct dc_link *link,
 	struct dc_sink *prev_sink = NULL;
 	struct dpcd_caps prev_dpcd_caps;
 	enum dc_connection_type new_connection_type = dc_connection_none;
-	enum dc_connection_type pre_connection_type = dc_connection_none;
 	const uint32_t post_oui_delay = 30; // 30ms
 
 	DC_LOGGER_INIT(link->ctx->logger);
@@ -1059,7 +1058,6 @@ static bool detect_link_and_local_sink(struct dc_link *link,
 
 	link_disconnect_sink(link);
 	if (new_connection_type != dc_connection_none) {
-		pre_connection_type = link->type;
 		link->type = new_connection_type;
 		link->link_state_valid = false;
 
-- 
GitLab


From 70f1fcbc83582419fd753701c5abe674e05db785 Mon Sep 17 00:00:00 2001
From: Tom Rix <trix@redhat.com>
Date: Sun, 26 Jun 2022 10:20:53 -0400
Subject: [PATCH 1382/1731] drm/amd/display: Remove unused globals FORCE_RATE
 and FORCE_LANE_COUNT

sparse reports
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:3885:6: warning: symbol 'FORCE_RATE' was not declared. Should it be static?
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:3886:10: warning: symbol 'FORCE_LANE_COUNT' was not declared. Should it be static?

Neither of thse variables is used in dc_link_dp.c.  Reviewing the commit listed in
the fixes tag shows neither was used in the original patch.  So remove them.

Fixes: 265280b99822 ("drm/amd/display: add CLKMGR changes for DCN32/321")
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Tom Rix <trix@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index c8355acd36722..b2295bc086097 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3882,9 +3882,6 @@ static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_
 	return true;
 }
 
-bool FORCE_RATE = false;
-uint32_t FORCE_LANE_COUNT = 0;
-
 void decide_link_settings(struct dc_stream_state *stream,
 	struct dc_link_settings *link_setting)
 {
-- 
GitLab


From 01752681f1ee5febc9dd2da23f5dc0289ea125a6 Mon Sep 17 00:00:00 2001
From: Tom Rix <trix@redhat.com>
Date: Sun, 26 Jun 2022 10:46:15 -0400
Subject: [PATCH 1383/1731] drm/amd/display: change to_dal_irq_source_dnc32()
 storage class specifier to static

sparse reports
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn32/irq_service_dcn32.c:39:20: warning: symbol 'to_dal_irq_source_dcn32' was not declared. Should it be static?

to_dal_irq_source_dnc32() is only referenced in irq_service_dnc32.c, so change its
storage class specifier to static.

Fixes: 0efd4374f6b4 ("drm/amd/display: add dcn32 IRQ changes")
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Tom Rix <trix@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
index 3a213ca2f0771..b1012fa1977b5 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
@@ -36,7 +36,7 @@
 
 #define DCN_BASE__INST0_SEG2                       0x000034C0
 
-enum dc_irq_source to_dal_irq_source_dcn32(
+static enum dc_irq_source to_dal_irq_source_dcn32(
 		struct irq_service *irq_service,
 		uint32_t src_id,
 		uint32_t ext_id)
-- 
GitLab


From 2639d3e44f9c15b3f29f79943ed58f769faeaef2 Mon Sep 17 00:00:00 2001
From: Mauro Carvalho Chehab <mchehab@kernel.org>
Date: Tue, 28 Jun 2022 10:46:13 +0100
Subject: [PATCH 1384/1731] drm/amdgpu/amdgpu_dm: fix kernel-doc markups

There are 4 undocumented fields at struct amdgpu_display_manager.

Add documentation for them, fixing those warnings:

	drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:544: warning: Function parameter or member 'dmub_outbox_params' not described in 'amdgpu_display_manager'
	drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:544: warning: Function parameter or member 'num_of_edps' not described in 'amdgpu_display_manager'
	drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:544: warning: Function parameter or member 'disable_hpd_irq' not described in 'amdgpu_display_manager'
	drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:544: warning: Function parameter or member 'dmub_aux_transfer_done' not described in 'amdgpu_display_manager'
	drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:544: warning: Function parameter or member 'delayed_hpd_wq' not described in 'amdgpu_display_manager'

Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 547fc15479778..73755b304299c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -242,6 +242,13 @@ struct hpd_rx_irq_offload_work {
  * @force_timing_sync: set via debugfs. When set, indicates that all connected
  *		       displays will be forced to synchronize.
  * @dmcub_trace_event_en: enable dmcub trace events
+ * @dmub_outbox_params: DMUB Outbox parameters
+ * @num_of_edps: number of backlight eDPs
+ * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the
+ *		     driver when true
+ * @dmub_aux_transfer_done: struct completion used to indicate when DMUB
+ * 			    transfers are done
+ * @delayed_hpd_wq: work queue used to delay DMUB HPD work
  */
 struct amdgpu_display_manager {
 
-- 
GitLab


From 46d44516aa6e142fd70287e829e3bbad0d2ed35b Mon Sep 17 00:00:00 2001
From: Mauro Carvalho Chehab <mchehab@kernel.org>
Date: Tue, 28 Jun 2022 10:46:15 +0100
Subject: [PATCH 1385/1731] drm/amd/amd_shared.h: Add missing doc for
 PP_GFX_DCS_MASK

This symbol is missing documentation:

	drivers/gpu/drm/amd/include/amd_shared.h:224: warning: Enum value 'PP_GFX_DCS_MASK' not described in enum 'PP_FEATURE_MASK'

Document it.

Fixes: 680602d6c2d6 ("drm/amd/pm: enable DCS")
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/include/amd_shared.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index bcdf7453a4039..2e02a6fc17176 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -193,6 +193,7 @@ enum amd_powergating_state {
  * @PP_ACG_MASK: Adaptive clock generator.
  * @PP_STUTTER_MODE: Stutter mode.
  * @PP_AVFS_MASK: Adaptive voltage and frequency scaling.
+ * @PP_GFX_DCS_MASK: GFX Async DCS.
  *
  * To override these settings on boot, append amdgpu.ppfeaturemask=<mask> to
  * the kernel's command line parameters. This is usually done through a system's
-- 
GitLab


From 7268f0a9e842c52fa73b9f5afc1bebcf9f7d48b7 Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Tue, 28 Jun 2022 15:07:16 -0400
Subject: [PATCH 1386/1731] drm/amd: Load TA firmware for DCN321/DCN32

[Why&How]
TA firmware is needed to enable HDCP.

Changes in v2:

Load separate firmware for PSP 13.0.0

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index 9e1ef81933ff0..30386d34d0d64 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -39,7 +39,9 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
+MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
+MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
 
 /* For large FW files the time to complete can be very long */
 #define USBC_PD_POLLING_LIMIT_S 240
@@ -103,6 +105,10 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
 	case IP_VERSION(13, 0, 0):
 	case IP_VERSION(13, 0, 7):
 		err = psp_init_sos_microcode(psp, chip_name);
+		if (err)
+			return err;
+		/* It's not necessary to load ras ta on Guest side */
+		err = psp_init_ta_microcode(psp, chip_name);
 		if (err)
 			return err;
 		break;
-- 
GitLab


From ff15cea338d2c78e0086d55c8a9dd637a5dd3ccc Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Date: Tue, 28 Jun 2022 16:25:28 -0400
Subject: [PATCH 1387/1731] drm/amd/display: expose additional modifier for
 DCN32/321

[Why&How]
Some userspace expect a backwards compatible modifier on DCN32/321. For
hardware with num_pipes more than 16, we expose the most efficient
modifier first. As a fall back method, we need to expose slightly inefficient
modifier AMD_FMT_MOD_TILE_GFX9_64K_R_X after the best option.

Also set the number of packers to fixed value as required per hardware
documentation. This value is cached during hardware initialization and
can be read through the base driver.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  3 +-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 66 ++++++++++---------
 2 files changed, 36 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 8ef489fad7076..97fff4727724e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -744,8 +744,7 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 			switch (version) {
 			case AMD_FMT_MOD_TILE_VER_GFX11:
 				pipe_xor_bits = min(block_size_bits - 8, pipes);
-				packers = min(block_size_bits - 8 - pipe_xor_bits,
-						ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
+				packers = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);
 				break;
 			case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
 				pipe_xor_bits = min(block_size_bits - 8, pipes);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 9195d6a8a51f6..1bd65b41ba4d9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5203,6 +5203,7 @@ add_gfx11_modifiers(struct amdgpu_device *adev,
 	int num_pkrs = 0;
 	int pkrs = 0;
 	u32 gb_addr_config;
+	u8 i = 0;
 	unsigned swizzle_r_x;
 	uint64_t modifier_r_x;
 	uint64_t modifier_dcc_best;
@@ -5218,37 +5219,40 @@ add_gfx11_modifiers(struct amdgpu_device *adev,
 	num_pipes = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PIPES);
 	pipe_xor_bits = ilog2(num_pipes);
 
-	/* R_X swizzle modes are the best for rendering and DCC requires them. */
-	swizzle_r_x = num_pipes > 16 ? AMD_FMT_MOD_TILE_GFX11_256K_R_X :
-                                              AMD_FMT_MOD_TILE_GFX9_64K_R_X;
-
-	modifier_r_x = AMD_FMT_MOD |
-		AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
-		AMD_FMT_MOD_SET(TILE, swizzle_r_x) |
-		AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
-		AMD_FMT_MOD_SET(PACKERS, pkrs);
-
-	/* DCC_CONSTANT_ENCODE is not set because it can't vary with gfx11 (it's implied to be 1). */
-	modifier_dcc_best = modifier_r_x |
-		AMD_FMT_MOD_SET(DCC, 1) |
-		AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 0) |
-		AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
-		AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B);
-
-	/* DCC settings for 4K and greater resolutions. (required by display hw) */
-	modifier_dcc_4k = modifier_r_x |
-			AMD_FMT_MOD_SET(DCC, 1) |
-			AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
-			AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
-			AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B);
-
-	add_modifier(mods, size, capacity, modifier_dcc_best);
-	add_modifier(mods, size, capacity, modifier_dcc_4k);
-
-	add_modifier(mods, size, capacity, modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1));
-	add_modifier(mods, size, capacity, modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1));
-
-	add_modifier(mods, size, capacity, modifier_r_x);
+	for (i = 0; i < 2; i++) {
+		/* Insert the best one first. */
+		/* R_X swizzle modes are the best for rendering and DCC requires them. */
+		if (num_pipes > 16)
+			swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX11_256K_R_X : AMD_FMT_MOD_TILE_GFX9_64K_R_X;
+		else
+			swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX9_64K_R_X : AMD_FMT_MOD_TILE_GFX11_256K_R_X;
+
+		modifier_r_x = AMD_FMT_MOD |
+			       AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
+			       AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+			       AMD_FMT_MOD_SET(TILE, swizzle_r_x) |
+			       AMD_FMT_MOD_SET(PACKERS, pkrs);
+
+		/* DCC_CONSTANT_ENCODE is not set because it can't vary with gfx11 (it's implied to be 1). */
+		modifier_dcc_best = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) |
+				    AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 0) |
+				    AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
+				    AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B);
+
+		/* DCC settings for 4K and greater resolutions. (required by display hw) */
+		modifier_dcc_4k = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) |
+				  AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
+				  AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
+				  AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B);
+
+		add_modifier(mods, size, capacity, modifier_dcc_best);
+		add_modifier(mods, size, capacity, modifier_dcc_4k);
+
+		add_modifier(mods, size, capacity, modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1));
+		add_modifier(mods, size, capacity, modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1));
+
+		add_modifier(mods, size, capacity, modifier_r_x);
+	}
 
 	add_modifier(mods, size, capacity, AMD_FMT_MOD |
              AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
-- 
GitLab


From c5cb2cdf23ceefd9ef319d6c0d6ac294dfe356b6 Mon Sep 17 00:00:00 2001
From: Chandan Vurdigere Nataraj <chandan.vurdigerenataraj@amd.com>
Date: Sun, 26 Jun 2022 15:41:44 +0530
Subject: [PATCH 1388/1731] drm/amd/display: Re-org and cleanup the redundant
 code

[Why]
Redundant if-else cases for repeater and non-repeater checks

[How]
Without changing the core logic, rearranged the code by removing
redundant checks

Signed-off-by: Chandan Vurdigere Nataraj <chandan.vurdigerenataraj@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index b2295bc086097..1982ec0b55d4b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -913,19 +913,10 @@ enum dc_status dp_get_lane_status_and_lane_adjust(
 			offset,
 			lane01_status_address, dpcd_buf[0],
 			lane01_status_address + 1, dpcd_buf[1]);
-	} else {
-		DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
-			__func__,
-			lane01_status_address, dpcd_buf[0],
-			lane01_status_address + 1, dpcd_buf[1]);
-	}
-	lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
 
-	if (is_repeater(link, offset))
 		lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
 				((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 
-	if (is_repeater(link, offset)) {
 		DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 				" 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 					__func__,
@@ -935,6 +926,13 @@ enum dc_status dp_get_lane_status_and_lane_adjust(
 					lane01_adjust_address + 1,
 					dpcd_buf[lane_adjust_offset + 1]);
 	} else {
+		DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
+			__func__,
+			lane01_status_address, dpcd_buf[0],
+			lane01_status_address + 1, dpcd_buf[1]);
+
+		lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
+
 		DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 			__func__,
 			lane01_adjust_address,
-- 
GitLab


From 32788beb103f7f71e0192dce701f387070914651 Mon Sep 17 00:00:00 2001
From: John Garry <john.garry@huawei.com>
Date: Wed, 29 Jun 2022 17:18:44 +0800
Subject: [PATCH 1389/1731] ata: pata_cs5535: Fix W=1 warnings
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

x86_64 allmodconfig build with W=1 gives these warnings:

drivers/ata/pata_cs5535.c: In function ‘cs5535_set_piomode’:
drivers/ata/pata_cs5535.c:93:11: error: variable ‘dummy’ set but not
used [-Werror=unused-but-set-variable]
  u32 reg, dummy;
           ^~~~~
drivers/ata/pata_cs5535.c: In function ‘cs5535_set_dmamode’:
drivers/ata/pata_cs5535.c:132:11: error: variable ‘dummy’ set but not
used [-Werror=unused-but-set-variable]
  u32 reg, dummy;
           ^~~~~
cc1: all warnings being treated as errors

Mark variables 'dummy' as "maybe unused" as they are only ever written
in rdmsr() calls.

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
---
 drivers/ata/pata_cs5535.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/pata_cs5535.c b/drivers/ata/pata_cs5535.c
index 6725931f3c35f..c2c3238ff84bf 100644
--- a/drivers/ata/pata_cs5535.c
+++ b/drivers/ata/pata_cs5535.c
@@ -90,7 +90,7 @@ static void cs5535_set_piomode(struct ata_port *ap, struct ata_device *adev)
 	static const u16 pio_cmd_timings[5] = {
 		0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131
 	};
-	u32 reg, dummy;
+	u32 reg, __maybe_unused dummy;
 	struct ata_device *pair = ata_dev_pair(adev);
 
 	int mode = adev->pio_mode - XFER_PIO_0;
@@ -129,7 +129,7 @@ static void cs5535_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 	static const u32 mwdma_timings[3] = {
 		0x7F0FFFF3, 0x7F035352, 0x7F024241
 	};
-	u32 reg, dummy;
+	u32 reg, __maybe_unused dummy;
 	int mode = adev->dma_mode;
 
 	rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
-- 
GitLab


From 1ebc2cec0b7dd8dad0812449110803bd875ac816 Mon Sep 17 00:00:00 2001
From: Mikulas Patocka <mpatocka@redhat.com>
Date: Wed, 29 Jun 2022 13:40:01 -0400
Subject: [PATCH 1390/1731] dm raid: fix KASAN warning in raid5_remove_disk

There's a KASAN warning in raid5_remove_disk when running the LVM
testsuite. We fix this warning by verifying that the "number" variable is
within limits.

Cc: stable@vger.kernel.org
Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Signed-off-by: Mike Snitzer <snitzer@kernel.org>
---
 drivers/md/raid5.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
index 5d09256d7f818..ba289411f26f7 100644
--- a/drivers/md/raid5.c
+++ b/drivers/md/raid5.c
@@ -7933,7 +7933,7 @@ static int raid5_remove_disk(struct mddev *mddev, struct md_rdev *rdev)
 	int err = 0;
 	int number = rdev->raid_disk;
 	struct md_rdev __rcu **rdevp;
-	struct disk_info *p = conf->disks + number;
+	struct disk_info *p;
 	struct md_rdev *tmp;
 
 	print_raid5_conf(conf);
@@ -7952,6 +7952,9 @@ static int raid5_remove_disk(struct mddev *mddev, struct md_rdev *rdev)
 		log_exit(conf);
 		return 0;
 	}
+	if (unlikely(number >= conf->pool_size))
+		return 0;
+	p = conf->disks + number;
 	if (rdev == rcu_access_pointer(p->rdev))
 		rdevp = &p->rdev;
 	else if (rdev == rcu_access_pointer(p->replacement))
-- 
GitLab


From 617b365872a247480e9dcd50a32c8d1806b21861 Mon Sep 17 00:00:00 2001
From: Mikulas Patocka <mpatocka@redhat.com>
Date: Wed, 29 Jun 2022 13:40:57 -0400
Subject: [PATCH 1391/1731] dm raid: fix KASAN warning in raid5_add_disks

There's a KASAN warning in raid5_add_disk when running the LVM testsuite.
The warning happens in the test
lvconvert-raid-reshape-linear_to_raid6-single-type.sh. We fix the warning
by verifying that rdev->saved_raid_disk is within limits.

Cc: stable@vger.kernel.org
Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Signed-off-by: Mike Snitzer <snitzer@kernel.org>
---
 drivers/md/raid5.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
index ba289411f26f7..20e53b167f81f 100644
--- a/drivers/md/raid5.c
+++ b/drivers/md/raid5.c
@@ -8065,6 +8065,7 @@ static int raid5_add_disk(struct mddev *mddev, struct md_rdev *rdev)
 	 */
 	if (rdev->saved_raid_disk >= 0 &&
 	    rdev->saved_raid_disk >= first &&
+	    rdev->saved_raid_disk <= last &&
 	    conf->disks[rdev->saved_raid_disk].rdev == NULL)
 		first = rdev->saved_raid_disk;
 
-- 
GitLab


From 6e9c65f71eddef88f14b7210bbf30e6ce2409b87 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Thu, 23 Jun 2022 12:37:40 -0400
Subject: [PATCH 1392/1731] drm/amdgpu: fix documentation warning

Fixes this issue:
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:5094: warning: expecting prototype for amdgpu_device_gpu_recover_imp(). Prototype was for amdgpu_device_gpu_recover() instead

Fixes: cf727044144d ("drm/amdgpu: Rename amdgpu_device_gpu_recover_imp back to amdgpu_device_gpu_recover")
Reviewed-by: Kent Russell <kent.russell@amd.com>
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 41f68b3427f24..64f37713b270c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5098,7 +5098,7 @@ static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev)
 
 
 /**
- * amdgpu_device_gpu_recover_imp - reset the asic and recover scheduler
+ * amdgpu_device_gpu_recover - reset the asic and recover scheduler
  *
  * @adev: amdgpu_device pointer
  * @job: which job trigger hang
-- 
GitLab


From 7b92aa9e613508cbaa29dd35bf27db4c35628b10 Mon Sep 17 00:00:00 2001
From: Coleman Dietsch <dietschc@csp.edu>
Date: Tue, 28 Jun 2022 12:47:44 -0500
Subject: [PATCH 1393/1731] selftests net: fix kselftest net fatal error

The incorrect path is causing the following error when trying to run net
kselftests:

In file included from bpf/nat6to4.c:43:
../../../lib/bpf/bpf_helpers.h:11:10: fatal error: 'bpf_helper_defs.h' file not found
         ^~~~~~~~~~~~~~~~~~~
1 error generated.

Fixes: cf67838c4422 ("selftests net: fix bpf build error")
Signed-off-by: Coleman Dietsch <dietschc@csp.edu>
Link: https://lore.kernel.org/r/20220628174744.7908-1-dietschc@csp.edu
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 tools/testing/selftests/net/bpf/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/testing/selftests/net/bpf/Makefile b/tools/testing/selftests/net/bpf/Makefile
index 8a69c91fcca07..8ccaf8732eb22 100644
--- a/tools/testing/selftests/net/bpf/Makefile
+++ b/tools/testing/selftests/net/bpf/Makefile
@@ -2,7 +2,7 @@
 
 CLANG ?= clang
 CCINCLUDE += -I../../bpf
-CCINCLUDE += -I../../../lib
+CCINCLUDE += -I../../../../lib
 CCINCLUDE += -I../../../../../usr/include/
 
 TEST_CUSTOM_PROGS = $(OUTPUT)/bpf/nat6to4.o
-- 
GitLab


From e65af5403e462ccd7dff6a045a886c64da598c2e Mon Sep 17 00:00:00 2001
From: Oliver Neukum <oneukum@suse.com>
Date: Tue, 28 Jun 2022 11:35:17 +0200
Subject: [PATCH 1394/1731] usbnet: fix memory allocation in helpers

usbnet provides some helper functions that are also used in
the context of reset() operations. During a reset the other
drivers on a device are unable to operate. As that can be block
drivers, a driver for another interface cannot use paging
in its memory allocations without risking a deadlock.
Use GFP_NOIO in the helpers.

Fixes: 877bd862f32b8 ("usbnet: introduce usbnet 3 command helpers")
Signed-off-by: Oliver Neukum <oneukum@suse.com>
Link: https://lore.kernel.org/r/20220628093517.7469-1-oneukum@suse.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/usb/usbnet.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/usb/usbnet.c b/drivers/net/usb/usbnet.c
index 1cb6dab3e2d04..e2135ab87a6ed 100644
--- a/drivers/net/usb/usbnet.c
+++ b/drivers/net/usb/usbnet.c
@@ -2004,7 +2004,7 @@ static int __usbnet_read_cmd(struct usbnet *dev, u8 cmd, u8 reqtype,
 		   cmd, reqtype, value, index, size);
 
 	if (size) {
-		buf = kmalloc(size, GFP_KERNEL);
+		buf = kmalloc(size, GFP_NOIO);
 		if (!buf)
 			goto out;
 	}
@@ -2036,7 +2036,7 @@ static int __usbnet_write_cmd(struct usbnet *dev, u8 cmd, u8 reqtype,
 		   cmd, reqtype, value, index, size);
 
 	if (data) {
-		buf = kmemdup(data, size, GFP_KERNEL);
+		buf = kmemdup(data, size, GFP_NOIO);
 		if (!buf)
 			goto out;
 	} else {
-- 
GitLab


From 1758bde2e4aa5ff188d53e7d9d388bbb7e12eebb Mon Sep 17 00:00:00 2001
From: Lukas Wunner <lukas@wunner.de>
Date: Tue, 28 Jun 2022 12:15:08 +0200
Subject: [PATCH 1395/1731] net: phy: Don't trigger state machine while in
 suspend

Upon system sleep, mdio_bus_phy_suspend() stops the phy_state_machine(),
but subsequent interrupts may retrigger it:

They may have been left enabled to facilitate wakeup and are not
quiesced until the ->suspend_noirq() phase.  Unwanted interrupts may
hence occur between mdio_bus_phy_suspend() and dpm_suspend_noirq(),
as well as between dpm_resume_noirq() and mdio_bus_phy_resume().

Retriggering the phy_state_machine() through an interrupt is not only
undesirable for the reason given in mdio_bus_phy_suspend() (freezing it
midway with phydev->lock held), but also because the PHY may be
inaccessible after it's suspended:  Accesses to USB-attached PHYs are
blocked once usb_suspend_both() clears the can_submit flag and PHYs on
PCI network cards may become inaccessible upon suspend as well.

Amend phy_interrupt() to avoid triggering the state machine if the PHY
is suspended.  Signal wakeup instead if the attached net_device or its
parent has been configured as a wakeup source.  (Those conditions are
identical to mdio_bus_phy_may_suspend().)  Postpone handling of the
interrupt until the PHY has resumed.

Before stopping the phy_state_machine() in mdio_bus_phy_suspend(),
wait for a concurrent phy_interrupt() to run to completion.  That is
necessary because phy_interrupt() may have checked the PHY's suspend
status before the system sleep transition commenced and it may thus
retrigger the state machine after it was stopped.

Likewise, after re-enabling interrupt handling in mdio_bus_phy_resume(),
wait for a concurrent phy_interrupt() to complete to ensure that
interrupts which it postponed are properly rerun.

The issue was exposed by commit 1ce8b37241ed ("usbnet: smsc95xx: Forward
PHY interrupts to PHY driver to avoid polling"), but has existed since
forever.

Fixes: 541cd3ee00a4 ("phylib: Fix deadlock on resume")
Link: https://lore.kernel.org/netdev/a5315a8a-32c2-962f-f696-de9a26d30091@samsung.com/
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: stable@vger.kernel.org # v2.6.33+
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/b7f386d04e9b5b0e2738f0125743e30676f309ef.1656410895.git.lukas@wunner.de
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/phy/phy.c        | 23 +++++++++++++++++++++++
 drivers/net/phy/phy_device.c | 23 +++++++++++++++++++++++
 include/linux/phy.h          |  6 ++++++
 3 files changed, 52 insertions(+)

diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index ef62f357b76d9..8d3ee3a6495b4 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -31,6 +31,7 @@
 #include <linux/io.h>
 #include <linux/uaccess.h>
 #include <linux/atomic.h>
+#include <linux/suspend.h>
 #include <net/netlink.h>
 #include <net/genetlink.h>
 #include <net/sock.h>
@@ -976,6 +977,28 @@ static irqreturn_t phy_interrupt(int irq, void *phy_dat)
 	struct phy_driver *drv = phydev->drv;
 	irqreturn_t ret;
 
+	/* Wakeup interrupts may occur during a system sleep transition.
+	 * Postpone handling until the PHY has resumed.
+	 */
+	if (IS_ENABLED(CONFIG_PM_SLEEP) && phydev->irq_suspended) {
+		struct net_device *netdev = phydev->attached_dev;
+
+		if (netdev) {
+			struct device *parent = netdev->dev.parent;
+
+			if (netdev->wol_enabled)
+				pm_system_wakeup();
+			else if (device_may_wakeup(&netdev->dev))
+				pm_wakeup_dev_event(&netdev->dev, 0, true);
+			else if (parent && device_may_wakeup(parent))
+				pm_wakeup_dev_event(parent, 0, true);
+		}
+
+		phydev->irq_rerun = 1;
+		disable_irq_nosync(irq);
+		return IRQ_HANDLED;
+	}
+
 	mutex_lock(&phydev->lock);
 	ret = drv->handle_interrupt(phydev);
 	mutex_unlock(&phydev->lock);
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index 431a8719c6359..46acddd865a78 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -278,6 +278,15 @@ static __maybe_unused int mdio_bus_phy_suspend(struct device *dev)
 	if (phydev->mac_managed_pm)
 		return 0;
 
+	/* Wakeup interrupts may occur during the system sleep transition when
+	 * the PHY is inaccessible. Set flag to postpone handling until the PHY
+	 * has resumed. Wait for concurrent interrupt handler to complete.
+	 */
+	if (phy_interrupt_is_valid(phydev)) {
+		phydev->irq_suspended = 1;
+		synchronize_irq(phydev->irq);
+	}
+
 	/* We must stop the state machine manually, otherwise it stops out of
 	 * control, possibly with the phydev->lock held. Upon resume, netdev
 	 * may call phy routines that try to grab the same lock, and that may
@@ -315,6 +324,20 @@ static __maybe_unused int mdio_bus_phy_resume(struct device *dev)
 	if (ret < 0)
 		return ret;
 no_resume:
+	if (phy_interrupt_is_valid(phydev)) {
+		phydev->irq_suspended = 0;
+		synchronize_irq(phydev->irq);
+
+		/* Rerun interrupts which were postponed by phy_interrupt()
+		 * because they occurred during the system sleep transition.
+		 */
+		if (phydev->irq_rerun) {
+			phydev->irq_rerun = 0;
+			enable_irq(phydev->irq);
+			irq_wake_thread(phydev->irq, phydev);
+		}
+	}
+
 	if (phydev->attached_dev && phydev->adjust_link)
 		phy_start_machine(phydev);
 
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 508f1149665b8..b09f7d36cff2a 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -572,6 +572,10 @@ struct macsec_ops;
  * @mdix_ctrl: User setting of crossover
  * @pma_extable: Cached value of PMA/PMD Extended Abilities Register
  * @interrupts: Flag interrupts have been enabled
+ * @irq_suspended: Flag indicating PHY is suspended and therefore interrupt
+ *                 handling shall be postponed until PHY has resumed
+ * @irq_rerun: Flag indicating interrupts occurred while PHY was suspended,
+ *             requiring a rerun of the interrupt handler after resume
  * @interface: enum phy_interface_t value
  * @skb: Netlink message for cable diagnostics
  * @nest: Netlink nest used for cable diagnostics
@@ -626,6 +630,8 @@ struct phy_device {
 
 	/* Interrupts are enabled */
 	unsigned interrupts:1;
+	unsigned irq_suspended:1;
+	unsigned irq_rerun:1;
 
 	enum phy_state state;
 
-- 
GitLab


From fa152f626b24ec2ca3489100d8c5c0a0bce4e2ef Mon Sep 17 00:00:00 2001
From: Oleksij Rempel <o.rempel@pengutronix.de>
Date: Tue, 28 Jun 2022 13:43:49 +0200
Subject: [PATCH 1396/1731] net: phy: ax88772a: fix lost pause advertisement
 configuration

In case of asix_ax88772a_link_change_notify() workaround, we run soft
reset which will automatically clear MII_ADVERTISE configuration. The
PHYlib framework do not know about changed configuration state of the
PHY, so we need use phy_init_hw() to reinit PHY configuration.

Fixes: dde258469257 ("net: usb/phy: asix: add support for ax88772A/C PHYs")
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20220628114349.3929928-1-o.rempel@pengutronix.de
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/phy/ax88796b.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/net/phy/ax88796b.c b/drivers/net/phy/ax88796b.c
index 4578963375055..0f1e617a26c91 100644
--- a/drivers/net/phy/ax88796b.c
+++ b/drivers/net/phy/ax88796b.c
@@ -88,8 +88,10 @@ static void asix_ax88772a_link_change_notify(struct phy_device *phydev)
 	/* Reset PHY, otherwise MII_LPA will provide outdated information.
 	 * This issue is reproducible only with some link partner PHYs
 	 */
-	if (phydev->state == PHY_NOLINK && phydev->drv->soft_reset)
-		phydev->drv->soft_reset(phydev);
+	if (phydev->state == PHY_NOLINK) {
+		phy_init_hw(phydev);
+		phy_start_aneg(phydev);
+	}
 }
 
 static struct phy_driver asix_driver[] = {
-- 
GitLab


From 4e43e64d0f1332fcc503babad4dc31aead7131ca Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Tue, 28 Jun 2022 12:12:48 +0000
Subject: [PATCH 1397/1731] ipv6: fix lockdep splat in in6_dump_addrs()

As reported by syzbot, we should not use rcu_dereference()
when rcu_read_lock() is not held.

WARNING: suspicious RCU usage
5.19.0-rc2-syzkaller #0 Not tainted

net/ipv6/addrconf.c:5175 suspicious rcu_dereference_check() usage!

other info that might help us debug this:

rcu_scheduler_active = 2, debug_locks = 1
1 lock held by syz-executor326/3617:
 #0: ffffffff8d5848e8 (rtnl_mutex){+.+.}-{3:3}, at: netlink_dump+0xae/0xc20 net/netlink/af_netlink.c:2223

stack backtrace:
CPU: 0 PID: 3617 Comm: syz-executor326 Not tainted 5.19.0-rc2-syzkaller #0
Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011
Call Trace:
 <TASK>
 __dump_stack lib/dump_stack.c:88 [inline]
 dump_stack_lvl+0xcd/0x134 lib/dump_stack.c:106
 in6_dump_addrs+0x12d1/0x1790 net/ipv6/addrconf.c:5175
 inet6_dump_addr+0x9c1/0xb50 net/ipv6/addrconf.c:5300
 netlink_dump+0x541/0xc20 net/netlink/af_netlink.c:2275
 __netlink_dump_start+0x647/0x900 net/netlink/af_netlink.c:2380
 netlink_dump_start include/linux/netlink.h:245 [inline]
 rtnetlink_rcv_msg+0x73e/0xc90 net/core/rtnetlink.c:6046
 netlink_rcv_skb+0x153/0x420 net/netlink/af_netlink.c:2501
 netlink_unicast_kernel net/netlink/af_netlink.c:1319 [inline]
 netlink_unicast+0x543/0x7f0 net/netlink/af_netlink.c:1345
 netlink_sendmsg+0x917/0xe10 net/netlink/af_netlink.c:1921
 sock_sendmsg_nosec net/socket.c:714 [inline]
 sock_sendmsg+0xcf/0x120 net/socket.c:734
 ____sys_sendmsg+0x6eb/0x810 net/socket.c:2492
 ___sys_sendmsg+0xf3/0x170 net/socket.c:2546
 __sys_sendmsg net/socket.c:2575 [inline]
 __do_sys_sendmsg net/socket.c:2584 [inline]
 __se_sys_sendmsg net/socket.c:2582 [inline]
 __x64_sys_sendmsg+0x132/0x220 net/socket.c:2582
 do_syscall_x64 arch/x86/entry/common.c:50 [inline]
 do_syscall_64+0x35/0xb0 arch/x86/entry/common.c:80
 entry_SYSCALL_64_after_hwframe+0x46/0xb0

Fixes: 88e2ca308094 ("mld: convert ifmcaddr6 to RCU")
Reported-by: syzbot <syzkaller@googlegroups.com>
Signed-off-by: Eric Dumazet <edumazet@google.com>
Cc: Taehee Yoo <ap420073@gmail.com>
Link: https://lore.kernel.org/r/20220628121248.858695-1-edumazet@google.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/ipv6/addrconf.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c
index 5864cbc30db69..49cc6587dd771 100644
--- a/net/ipv6/addrconf.c
+++ b/net/ipv6/addrconf.c
@@ -5168,9 +5168,9 @@ next:
 		fillargs->event = RTM_GETMULTICAST;
 
 		/* multicast address */
-		for (ifmca = rcu_dereference(idev->mc_list);
+		for (ifmca = rtnl_dereference(idev->mc_list);
 		     ifmca;
-		     ifmca = rcu_dereference(ifmca->next), ip_idx++) {
+		     ifmca = rtnl_dereference(ifmca->next), ip_idx++) {
 			if (ip_idx < s_ip_idx)
 				continue;
 			err = inet6_fill_ifmcaddr(skb, ifmca, fillargs);
-- 
GitLab


From 050133e1aa2cb49bb17be847d48a4431598ef562 Mon Sep 17 00:00:00 2001
From: Yevhen Orlov <yevhen.orlov@plvision.eu>
Date: Wed, 29 Jun 2022 04:29:14 +0300
Subject: [PATCH 1398/1731] net: bonding: fix use-after-free after 802.3ad
 slave unbind

commit 0622cab0341c ("bonding: fix 802.3ad aggregator reselection"),
resolve case, when there is several aggregation groups in the same bond.
bond_3ad_unbind_slave will invalidate (clear) aggregator when
__agg_active_ports return zero. So, ad_clear_agg can be executed even, when
num_of_ports!=0. Than bond_3ad_unbind_slave can be executed again for,
previously cleared aggregator. NOTE: at this time bond_3ad_unbind_slave
will not update slave ports list, because lag_ports==NULL. So, here we
got slave ports, pointing to freed aggregator memory.

Fix with checking actual number of ports in group (as was before
commit 0622cab0341c ("bonding: fix 802.3ad aggregator reselection") ),
before ad_clear_agg().

The KASAN logs are as follows:

[  767.617392] ==================================================================
[  767.630776] BUG: KASAN: use-after-free in bond_3ad_state_machine_handler+0x13dc/0x1470
[  767.638764] Read of size 2 at addr ffff00011ba9d430 by task kworker/u8:7/767
[  767.647361] CPU: 3 PID: 767 Comm: kworker/u8:7 Tainted: G           O 5.15.11 #15
[  767.655329] Hardware name: DNI AmazonGo1 A7040 board (DT)
[  767.660760] Workqueue: lacp_1 bond_3ad_state_machine_handler
[  767.666468] Call trace:
[  767.668930]  dump_backtrace+0x0/0x2d0
[  767.672625]  show_stack+0x24/0x30
[  767.675965]  dump_stack_lvl+0x68/0x84
[  767.679659]  print_address_description.constprop.0+0x74/0x2b8
[  767.685451]  kasan_report+0x1f0/0x260
[  767.689148]  __asan_load2+0x94/0xd0
[  767.692667]  bond_3ad_state_machine_handler+0x13dc/0x1470

Fixes: 0622cab0341c ("bonding: fix 802.3ad aggregator reselection")
Co-developed-by: Maksym Glubokiy <maksym.glubokiy@plvision.eu>
Signed-off-by: Maksym Glubokiy <maksym.glubokiy@plvision.eu>
Signed-off-by: Yevhen Orlov <yevhen.orlov@plvision.eu>
Acked-by: Jay Vosburgh <jay.vosburgh@canonical.com>
Link: https://lore.kernel.org/r/20220629012914.361-1-yevhen.orlov@plvision.eu
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/bonding/bond_3ad.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/bonding/bond_3ad.c b/drivers/net/bonding/bond_3ad.c
index a86b1f71762ea..d7fb33c078e81 100644
--- a/drivers/net/bonding/bond_3ad.c
+++ b/drivers/net/bonding/bond_3ad.c
@@ -2228,7 +2228,8 @@ void bond_3ad_unbind_slave(struct slave *slave)
 				temp_aggregator->num_of_ports--;
 				if (__agg_active_ports(temp_aggregator) == 0) {
 					select_new_active_agg = temp_aggregator->is_active;
-					ad_clear_agg(temp_aggregator);
+					if (temp_aggregator->num_of_ports == 0)
+						ad_clear_agg(temp_aggregator);
 					if (select_new_active_agg) {
 						slave_info(bond->dev, slave->dev, "Removing an active aggregator\n");
 						/* select new active aggregator */
-- 
GitLab


From 34ad61514c4c3657df21a058f9961c3bb2f84ff2 Mon Sep 17 00:00:00 2001
From: Alan Adamson <alan.adamson@oracle.com>
Date: Mon, 27 Jun 2022 16:25:43 -0700
Subject: [PATCH 1399/1731] nvmet: add a clear_ids attribute for passthru
 targets

If the clear_ids attribute is set to true, the EUI/GUID/UUID is cleared
for the passthru target.  By default, loop targets will set clear_ids to
true.

This resolves an issue where a connect to a passthru target fails when
using a trtype of 'loop' because EUI/GUID/UUID is not unique.

Fixes: 2079f41ec6ff ("nvme: check that EUI/GUID/UUID are globally unique")
Signed-off-by: Alan Adamson <alan.adamson@oracle.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Chaitanya Kulkarni <kch@nvidia.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/target/configfs.c | 20 +++++++++++++
 drivers/nvme/target/core.c     |  6 ++++
 drivers/nvme/target/nvmet.h    |  1 +
 drivers/nvme/target/passthru.c | 55 ++++++++++++++++++++++++++++++++++
 4 files changed, 82 insertions(+)

diff --git a/drivers/nvme/target/configfs.c b/drivers/nvme/target/configfs.c
index e44b2988759ec..ff77c3d2354fa 100644
--- a/drivers/nvme/target/configfs.c
+++ b/drivers/nvme/target/configfs.c
@@ -773,11 +773,31 @@ static ssize_t nvmet_passthru_io_timeout_store(struct config_item *item,
 }
 CONFIGFS_ATTR(nvmet_passthru_, io_timeout);
 
+static ssize_t nvmet_passthru_clear_ids_show(struct config_item *item,
+		char *page)
+{
+	return sprintf(page, "%u\n", to_subsys(item->ci_parent)->clear_ids);
+}
+
+static ssize_t nvmet_passthru_clear_ids_store(struct config_item *item,
+		const char *page, size_t count)
+{
+	struct nvmet_subsys *subsys = to_subsys(item->ci_parent);
+	unsigned int clear_ids;
+
+	if (kstrtouint(page, 0, &clear_ids))
+		return -EINVAL;
+	subsys->clear_ids = clear_ids;
+	return count;
+}
+CONFIGFS_ATTR(nvmet_passthru_, clear_ids);
+
 static struct configfs_attribute *nvmet_passthru_attrs[] = {
 	&nvmet_passthru_attr_device_path,
 	&nvmet_passthru_attr_enable,
 	&nvmet_passthru_attr_admin_timeout,
 	&nvmet_passthru_attr_io_timeout,
+	&nvmet_passthru_attr_clear_ids,
 	NULL,
 };
 
diff --git a/drivers/nvme/target/core.c b/drivers/nvme/target/core.c
index 90e75324dae05..c27660a660d9a 100644
--- a/drivers/nvme/target/core.c
+++ b/drivers/nvme/target/core.c
@@ -1374,6 +1374,12 @@ u16 nvmet_alloc_ctrl(const char *subsysnqn, const char *hostnqn,
 	ctrl->port = req->port;
 	ctrl->ops = req->ops;
 
+#ifdef CONFIG_NVME_TARGET_PASSTHRU
+	/* By default, set loop targets to clear IDS by default */
+	if (ctrl->port->disc_addr.trtype == NVMF_TRTYPE_LOOP)
+		subsys->clear_ids = 1;
+#endif
+
 	INIT_WORK(&ctrl->async_event_work, nvmet_async_event_work);
 	INIT_LIST_HEAD(&ctrl->async_events);
 	INIT_RADIX_TREE(&ctrl->p2p_ns_map, GFP_KERNEL);
diff --git a/drivers/nvme/target/nvmet.h b/drivers/nvme/target/nvmet.h
index 69818752a33a5..2b3e5719f24e4 100644
--- a/drivers/nvme/target/nvmet.h
+++ b/drivers/nvme/target/nvmet.h
@@ -249,6 +249,7 @@ struct nvmet_subsys {
 	struct config_group	passthru_group;
 	unsigned int		admin_timeout;
 	unsigned int		io_timeout;
+	unsigned int		clear_ids;
 #endif /* CONFIG_NVME_TARGET_PASSTHRU */
 
 #ifdef CONFIG_BLK_DEV_ZONED
diff --git a/drivers/nvme/target/passthru.c b/drivers/nvme/target/passthru.c
index b1f7efab39180..6f39a29828b12 100644
--- a/drivers/nvme/target/passthru.c
+++ b/drivers/nvme/target/passthru.c
@@ -30,6 +30,53 @@ void nvmet_passthrough_override_cap(struct nvmet_ctrl *ctrl)
 		ctrl->cap &= ~(1ULL << 43);
 }
 
+static u16 nvmet_passthru_override_id_descs(struct nvmet_req *req)
+{
+	struct nvmet_ctrl *ctrl = req->sq->ctrl;
+	u16 status = NVME_SC_SUCCESS;
+	int pos, len;
+	bool csi_seen = false;
+	void *data;
+	u8 csi;
+
+	if (!ctrl->subsys->clear_ids)
+		return status;
+
+	data = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
+	if (!data)
+		return NVME_SC_INTERNAL;
+
+	status = nvmet_copy_from_sgl(req, 0, data, NVME_IDENTIFY_DATA_SIZE);
+	if (status)
+		goto out_free;
+
+	for (pos = 0; pos < NVME_IDENTIFY_DATA_SIZE; pos += len) {
+		struct nvme_ns_id_desc *cur = data + pos;
+
+		if (cur->nidl == 0)
+			break;
+		if (cur->nidt == NVME_NIDT_CSI) {
+			memcpy(&csi, cur + 1, NVME_NIDT_CSI_LEN);
+			csi_seen = true;
+			break;
+		}
+		len = sizeof(struct nvme_ns_id_desc) + cur->nidl;
+	}
+
+	memset(data, 0, NVME_IDENTIFY_DATA_SIZE);
+	if (csi_seen) {
+		struct nvme_ns_id_desc *cur = data;
+
+		cur->nidt = NVME_NIDT_CSI;
+		cur->nidl = NVME_NIDT_CSI_LEN;
+		memcpy(cur + 1, &csi, NVME_NIDT_CSI_LEN);
+	}
+	status = nvmet_copy_to_sgl(req, 0, data, NVME_IDENTIFY_DATA_SIZE);
+out_free:
+	kfree(data);
+	return status;
+}
+
 static u16 nvmet_passthru_override_id_ctrl(struct nvmet_req *req)
 {
 	struct nvmet_ctrl *ctrl = req->sq->ctrl;
@@ -152,6 +199,11 @@ static u16 nvmet_passthru_override_id_ns(struct nvmet_req *req)
 	 */
 	id->mc = 0;
 
+	if (req->sq->ctrl->subsys->clear_ids) {
+		memset(id->nguid, 0, NVME_NIDT_NGUID_LEN);
+		memset(id->eui64, 0, NVME_NIDT_EUI64_LEN);
+	}
+
 	status = nvmet_copy_to_sgl(req, 0, id, sizeof(*id));
 
 out_free:
@@ -176,6 +228,9 @@ static void nvmet_passthru_execute_cmd_work(struct work_struct *w)
 		case NVME_ID_CNS_NS:
 			nvmet_passthru_override_id_ns(req);
 			break;
+		case NVME_ID_CNS_NS_DESC_LIST:
+			nvmet_passthru_override_id_descs(req);
+			break;
 		}
 	} else if (status < 0)
 		status = NVME_SC_INTERNAL;
-- 
GitLab


From e1c70d79346356bb1ede3f79436df80917845ab9 Mon Sep 17 00:00:00 2001
From: Lamarque Vieira Souza <lamarque@petrosoftdesign.com>
Date: Wed, 29 Jun 2022 21:30:53 -0300
Subject: [PATCH 1400/1731] nvme-pci: add NVME_QUIRK_BOGUS_NID for ADATA
 IM2P33F8ABR1
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

ADATA IM2P33F8ABR1 reports bogus eui64 values that appear to be the same
across all drives. Quirk them out so they are not marked as "non globally
unique" duplicates.

Co-developed-by: Felipe de Jesus Araujo da Conceição <felipe.conceicao@petrosoftdesign.com>
Signed-off-by: Felipe de Jesus Araujo da Conceição <felipe.conceicao@petrosoftdesign.com>
Signed-off-by: Lamarque V. Souza <lamarque.souza@petrosoftdesign.com>

Cc: stable@vger.kernel.org
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/host/pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index c9ebe60724980..e7af2234e53b9 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -3469,6 +3469,8 @@ static const struct pci_device_id nvme_id_table[] = {
 	{ PCI_DEVICE(0x1b4b, 0x1092),	/* Lexar 256 GB SSD */
 		.driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
 				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
+	{ PCI_DEVICE(0x1cc1, 0x33f8),   /* ADATA IM2P33F8ABR1 1 TB */
+		.driver_data = NVME_QUIRK_BOGUS_NID, },
 	{ PCI_DEVICE(0x10ec, 0x5762),   /* ADATA SX6000LNP */
 		.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
 				NVME_QUIRK_BOGUS_NID, },
-- 
GitLab


From f8ebb3ac881b17712e1d5967c97ab1806b16d3d6 Mon Sep 17 00:00:00 2001
From: Jose Alonso <joalonsof@gmail.com>
Date: Tue, 28 Jun 2022 12:13:02 -0300
Subject: [PATCH 1401/1731] net: usb: ax88179_178a: Fix packet receiving

This patch corrects packet receiving in ax88179_rx_fixup.

- problem observed:
  ifconfig shows allways a lot of 'RX Errors' while packets
  are received normally.

  This occurs because ax88179_rx_fixup does not recognise properly
  the usb urb received.
  The packets are normally processed and at the end, the code exits
  with 'return 0', generating RX Errors.
  (pkt_cnt==-2 and ptk_hdr over field rx_hdr trying to identify
   another packet there)

  This is a usb urb received by "tcpdump -i usbmon2 -X" on a
  little-endian CPU:
  0x0000:  eeee f8e3 3b19 87a0 94de 80e3 daac 0800
           ^         packet 1 start (pkt_len = 0x05ec)
           ^^^^      IP alignment pseudo header
                ^    ethernet packet start
           last byte ethernet packet   v
           padding (8-bytes aligned)     vvvv vvvv
  0x05e0:  c92d d444 1420 8a69 83dd 272f e82b 9811
  0x05f0:  eeee f8e3 3b19 87a0 94de 80e3 daac 0800
  ...      ^ packet 2
  0x0be0:  eeee f8e3 3b19 87a0 94de 80e3 daac 0800
  ...
  0x1130:  9d41 9171 8a38 0ec5 eeee f8e3 3b19 87a0
  ...
  0x1720:  8cfc 15ff 5e4c e85c eeee f8e3 3b19 87a0
  ...
  0x1d10:  ecfa 2a3a 19ab c78c eeee f8e3 3b19 87a0
  ...
  0x2070:  eeee f8e3 3b19 87a0 94de 80e3 daac 0800
  ...      ^ packet 7
  0x2120:  7c88 4ca5 5c57 7dcc 0d34 7577 f778 7e0a
  0x2130:  f032 e093 7489 0740 3008 ec05 0000 0080
                               ====1==== ====2====
           hdr_off             ^
           pkt_len = 0x05ec         ^^^^
           AX_RXHDR_*=0x00830  ^^^^   ^
           pkt_len = 0                        ^^^^
           AX_RXHDR_DROP_ERR=0x80000000  ^^^^   ^
  0x2140:  3008 ec05 0000 0080 3008 5805 0000 0080
  0x2150:  3008 ec05 0000 0080 3008 ec05 0000 0080
  0x2160:  3008 5803 0000 0080 3008 c800 0000 0080
           ===11==== ===12==== ===13==== ===14====
  0x2170:  0000 0000 0e00 3821
                     ^^^^ ^^^^ rx_hdr
                     ^^^^      pkt_cnt=14
                          ^^^^ hdr_off=0x2138
           ^^^^ ^^^^           padding

  The dump shows that pkt_cnt is the number of entrys in the
  per-packet metadata. It is "2 * packet count".
  Each packet have two entrys. The first have a valid
  value (pkt_len and AX_RXHDR_*) and the second have a
  dummy-header 0x80000000 (pkt_len=0 with AX_RXHDR_DROP_ERR).
  Why exists dummy-header for each packet?!?
  My guess is that this was done probably to align the
  entry for each packet to 64-bits and maintain compatibility
  with old firmware.
  There is also a padding (0x00000000) before the rx_hdr to
  align the end of rx_hdr to 64-bit.
  Note that packets have a alignment of 64-bits (8-bytes).

  This patch assumes that the dummy-header and the last
  padding are optional. So it preserves semantics and
  recognises the same valid packets as the current code.

  This patch was made using only the dumpfile information and
  tested with only one device:
  0b95:1790 ASIX Electronics Corp. AX88179 Gigabit Ethernet

Fixes: 57bc3d3ae8c1 ("net: usb: ax88179_178a: Fix out-of-bounds accesses in RX fixup")
Fixes: e2ca90c276e1 ("ax88179_178a: ASIX AX88179_178A USB 3.0/2.0 to gigabit ethernet adapter driver")
Signed-off-by: Jose Alonso <joalonsof@gmail.com>
Acked-by: Paolo Abeni <pabeni@redhat.com>
Link: https://lore.kernel.org/r/d6970bb04bf67598af4d316eaeb1792040b18cfd.camel@gmail.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
 drivers/net/usb/ax88179_178a.c | 101 +++++++++++++++++++++++++--------
 1 file changed, 76 insertions(+), 25 deletions(-)

diff --git a/drivers/net/usb/ax88179_178a.c b/drivers/net/usb/ax88179_178a.c
index 4704ed6f00efe..ac2d400d1d6cd 100644
--- a/drivers/net/usb/ax88179_178a.c
+++ b/drivers/net/usb/ax88179_178a.c
@@ -1472,6 +1472,42 @@ static int ax88179_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
 	 * are bundled into this buffer and where we can find an array of
 	 * per-packet metadata (which contains elements encoded into u16).
 	 */
+
+	/* SKB contents for current firmware:
+	 *   <packet 1> <padding>
+	 *   ...
+	 *   <packet N> <padding>
+	 *   <per-packet metadata entry 1> <dummy header>
+	 *   ...
+	 *   <per-packet metadata entry N> <dummy header>
+	 *   <padding2> <rx_hdr>
+	 *
+	 * where:
+	 *   <packet N> contains pkt_len bytes:
+	 *		2 bytes of IP alignment pseudo header
+	 *		packet received
+	 *   <per-packet metadata entry N> contains 4 bytes:
+	 *		pkt_len and fields AX_RXHDR_*
+	 *   <padding>	0-7 bytes to terminate at
+	 *		8 bytes boundary (64-bit).
+	 *   <padding2> 4 bytes to make rx_hdr terminate at
+	 *		8 bytes boundary (64-bit)
+	 *   <dummy-header> contains 4 bytes:
+	 *		pkt_len=0 and AX_RXHDR_DROP_ERR
+	 *   <rx-hdr>	contains 4 bytes:
+	 *		pkt_cnt and hdr_off (offset of
+	 *		  <per-packet metadata entry 1>)
+	 *
+	 * pkt_cnt is number of entrys in the per-packet metadata.
+	 * In current firmware there is 2 entrys per packet.
+	 * The first points to the packet and the
+	 *  second is a dummy header.
+	 * This was done probably to align fields in 64-bit and
+	 *  maintain compatibility with old firmware.
+	 * This code assumes that <dummy header> and <padding2> are
+	 *  optional.
+	 */
+
 	if (skb->len < 4)
 		return 0;
 	skb_trim(skb, skb->len - 4);
@@ -1485,51 +1521,66 @@ static int ax88179_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
 	/* Make sure that the bounds of the metadata array are inside the SKB
 	 * (and in front of the counter at the end).
 	 */
-	if (pkt_cnt * 2 + hdr_off > skb->len)
+	if (pkt_cnt * 4 + hdr_off > skb->len)
 		return 0;
 	pkt_hdr = (u32 *)(skb->data + hdr_off);
 
 	/* Packets must not overlap the metadata array */
 	skb_trim(skb, hdr_off);
 
-	for (; ; pkt_cnt--, pkt_hdr++) {
+	for (; pkt_cnt > 0; pkt_cnt--, pkt_hdr++) {
+		u16 pkt_len_plus_padd;
 		u16 pkt_len;
 
 		le32_to_cpus(pkt_hdr);
 		pkt_len = (*pkt_hdr >> 16) & 0x1fff;
+		pkt_len_plus_padd = (pkt_len + 7) & 0xfff8;
 
-		if (pkt_len > skb->len)
+		/* Skip dummy header used for alignment
+		 */
+		if (pkt_len == 0)
+			continue;
+
+		if (pkt_len_plus_padd > skb->len)
 			return 0;
 
 		/* Check CRC or runt packet */
-		if (((*pkt_hdr & (AX_RXHDR_CRC_ERR | AX_RXHDR_DROP_ERR)) == 0) &&
-		    pkt_len >= 2 + ETH_HLEN) {
-			bool last = (pkt_cnt == 0);
-
-			if (last) {
-				ax_skb = skb;
-			} else {
-				ax_skb = skb_clone(skb, GFP_ATOMIC);
-				if (!ax_skb)
-					return 0;
-			}
-			ax_skb->len = pkt_len;
-			/* Skip IP alignment pseudo header */
-			skb_pull(ax_skb, 2);
-			skb_set_tail_pointer(ax_skb, ax_skb->len);
-			ax_skb->truesize = pkt_len + sizeof(struct sk_buff);
-			ax88179_rx_checksum(ax_skb, pkt_hdr);
+		if ((*pkt_hdr & (AX_RXHDR_CRC_ERR | AX_RXHDR_DROP_ERR)) ||
+		    pkt_len < 2 + ETH_HLEN) {
+			dev->net->stats.rx_errors++;
+			skb_pull(skb, pkt_len_plus_padd);
+			continue;
+		}
 
-			if (last)
-				return 1;
+		/* last packet */
+		if (pkt_len_plus_padd == skb->len) {
+			skb_trim(skb, pkt_len);
 
-			usbnet_skb_return(dev, ax_skb);
+			/* Skip IP alignment pseudo header */
+			skb_pull(skb, 2);
+
+			skb->truesize = SKB_TRUESIZE(pkt_len_plus_padd);
+			ax88179_rx_checksum(skb, pkt_hdr);
+			return 1;
 		}
 
-		/* Trim this packet away from the SKB */
-		if (!skb_pull(skb, (pkt_len + 7) & 0xFFF8))
+		ax_skb = skb_clone(skb, GFP_ATOMIC);
+		if (!ax_skb)
 			return 0;
+		skb_trim(ax_skb, pkt_len);
+
+		/* Skip IP alignment pseudo header */
+		skb_pull(ax_skb, 2);
+
+		skb->truesize = pkt_len_plus_padd +
+				SKB_DATA_ALIGN(sizeof(struct sk_buff));
+		ax88179_rx_checksum(ax_skb, pkt_hdr);
+		usbnet_skb_return(dev, ax_skb);
+
+		skb_pull(skb, pkt_len_plus_padd);
 	}
+
+	return 0;
 }
 
 static struct sk_buff *
-- 
GitLab


From 9cc02ede696272c5271a401e4f27c262359bc2f6 Mon Sep 17 00:00:00 2001
From: Duoming Zhou <duoming@zju.edu.cn>
Date: Wed, 29 Jun 2022 08:26:40 +0800
Subject: [PATCH 1402/1731] net: rose: fix UAF bugs caused by timer handler

There are UAF bugs in rose_heartbeat_expiry(), rose_timer_expiry()
and rose_idletimer_expiry(). The root cause is that del_timer()
could not stop the timer handler that is running and the refcount
of sock is not managed properly.

One of the UAF bugs is shown below:

    (thread 1)          |        (thread 2)
                        |  rose_bind
                        |  rose_connect
                        |    rose_start_heartbeat
rose_release            |    (wait a time)
  case ROSE_STATE_0     |
  rose_destroy_socket   |  rose_heartbeat_expiry
    rose_stop_heartbeat |
    sock_put(sk)        |    ...
  sock_put(sk) // FREE  |
                        |    bh_lock_sock(sk) // USE

The sock is deallocated by sock_put() in rose_release() and
then used by bh_lock_sock() in rose_heartbeat_expiry().

Although rose_destroy_socket() calls rose_stop_heartbeat(),
it could not stop the timer that is running.

The KASAN report triggered by POC is shown below:

BUG: KASAN: use-after-free in _raw_spin_lock+0x5a/0x110
Write of size 4 at addr ffff88800ae59098 by task swapper/3/0
...
Call Trace:
 <IRQ>
 dump_stack_lvl+0xbf/0xee
 print_address_description+0x7b/0x440
 print_report+0x101/0x230
 ? irq_work_single+0xbb/0x140
 ? _raw_spin_lock+0x5a/0x110
 kasan_report+0xed/0x120
 ? _raw_spin_lock+0x5a/0x110
 kasan_check_range+0x2bd/0x2e0
 _raw_spin_lock+0x5a/0x110
 rose_heartbeat_expiry+0x39/0x370
 ? rose_start_heartbeat+0xb0/0xb0
 call_timer_fn+0x2d/0x1c0
 ? rose_start_heartbeat+0xb0/0xb0
 expire_timers+0x1f3/0x320
 __run_timers+0x3ff/0x4d0
 run_timer_softirq+0x41/0x80
 __do_softirq+0x233/0x544
 irq_exit_rcu+0x41/0xa0
 sysvec_apic_timer_interrupt+0x8c/0xb0
 </IRQ>
 <TASK>
 asm_sysvec_apic_timer_interrupt+0x1b/0x20
RIP: 0010:default_idle+0xb/0x10
RSP: 0018:ffffc9000012fea0 EFLAGS: 00000202
RAX: 000000000000bcae RBX: ffff888006660f00 RCX: 000000000000bcae
RDX: 0000000000000001 RSI: ffffffff843a11c0 RDI: ffffffff843a1180
RBP: dffffc0000000000 R08: dffffc0000000000 R09: ffffed100da36d46
R10: dfffe9100da36d47 R11: ffffffff83cf0950 R12: 0000000000000000
R13: 1ffff11000ccc1e0 R14: ffffffff8542af28 R15: dffffc0000000000
...
Allocated by task 146:
 __kasan_kmalloc+0xc4/0xf0
 sk_prot_alloc+0xdd/0x1a0
 sk_alloc+0x2d/0x4e0
 rose_create+0x7b/0x330
 __sock_create+0x2dd/0x640
 __sys_socket+0xc7/0x270
 __x64_sys_socket+0x71/0x80
 do_syscall_64+0x43/0x90
 entry_SYSCALL_64_after_hwframe+0x46/0xb0

Freed by task 152:
 kasan_set_track+0x4c/0x70
 kasan_set_free_info+0x1f/0x40
 ____kasan_slab_free+0x124/0x190
 kfree+0xd3/0x270
 __sk_destruct+0x314/0x460
 rose_release+0x2fa/0x3b0
 sock_close+0xcb/0x230
 __fput+0x2d9/0x650
 task_work_run+0xd6/0x160
 exit_to_user_mode_loop+0xc7/0xd0
 exit_to_user_mode_prepare+0x4e/0x80
 syscall_exit_to_user_mode+0x20/0x40
 do_syscall_64+0x4f/0x90
 entry_SYSCALL_64_after_hwframe+0x46/0xb0

This patch adds refcount of sock when we use functions
such as rose_start_heartbeat() and so on to start timer,
and decreases the refcount of sock when timer is finished
or deleted by functions such as rose_stop_heartbeat()
and so on. As a result, the UAF bugs could be mitigated.

Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Signed-off-by: Duoming Zhou <duoming@zju.edu.cn>
Tested-by: Duoming Zhou <duoming@zju.edu.cn>
Link: https://lore.kernel.org/r/20220629002640.5693-1-duoming@zju.edu.cn
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
 net/rose/rose_timer.c | 34 +++++++++++++++++++---------------
 1 file changed, 19 insertions(+), 15 deletions(-)

diff --git a/net/rose/rose_timer.c b/net/rose/rose_timer.c
index b3138fc2e552e..f06ddbed3fed6 100644
--- a/net/rose/rose_timer.c
+++ b/net/rose/rose_timer.c
@@ -31,89 +31,89 @@ static void rose_idletimer_expiry(struct timer_list *);
 
 void rose_start_heartbeat(struct sock *sk)
 {
-	del_timer(&sk->sk_timer);
+	sk_stop_timer(sk, &sk->sk_timer);
 
 	sk->sk_timer.function = rose_heartbeat_expiry;
 	sk->sk_timer.expires  = jiffies + 5 * HZ;
 
-	add_timer(&sk->sk_timer);
+	sk_reset_timer(sk, &sk->sk_timer, sk->sk_timer.expires);
 }
 
 void rose_start_t1timer(struct sock *sk)
 {
 	struct rose_sock *rose = rose_sk(sk);
 
-	del_timer(&rose->timer);
+	sk_stop_timer(sk, &rose->timer);
 
 	rose->timer.function = rose_timer_expiry;
 	rose->timer.expires  = jiffies + rose->t1;
 
-	add_timer(&rose->timer);
+	sk_reset_timer(sk, &rose->timer, rose->timer.expires);
 }
 
 void rose_start_t2timer(struct sock *sk)
 {
 	struct rose_sock *rose = rose_sk(sk);
 
-	del_timer(&rose->timer);
+	sk_stop_timer(sk, &rose->timer);
 
 	rose->timer.function = rose_timer_expiry;
 	rose->timer.expires  = jiffies + rose->t2;
 
-	add_timer(&rose->timer);
+	sk_reset_timer(sk, &rose->timer, rose->timer.expires);
 }
 
 void rose_start_t3timer(struct sock *sk)
 {
 	struct rose_sock *rose = rose_sk(sk);
 
-	del_timer(&rose->timer);
+	sk_stop_timer(sk, &rose->timer);
 
 	rose->timer.function = rose_timer_expiry;
 	rose->timer.expires  = jiffies + rose->t3;
 
-	add_timer(&rose->timer);
+	sk_reset_timer(sk, &rose->timer, rose->timer.expires);
 }
 
 void rose_start_hbtimer(struct sock *sk)
 {
 	struct rose_sock *rose = rose_sk(sk);
 
-	del_timer(&rose->timer);
+	sk_stop_timer(sk, &rose->timer);
 
 	rose->timer.function = rose_timer_expiry;
 	rose->timer.expires  = jiffies + rose->hb;
 
-	add_timer(&rose->timer);
+	sk_reset_timer(sk, &rose->timer, rose->timer.expires);
 }
 
 void rose_start_idletimer(struct sock *sk)
 {
 	struct rose_sock *rose = rose_sk(sk);
 
-	del_timer(&rose->idletimer);
+	sk_stop_timer(sk, &rose->idletimer);
 
 	if (rose->idle > 0) {
 		rose->idletimer.function = rose_idletimer_expiry;
 		rose->idletimer.expires  = jiffies + rose->idle;
 
-		add_timer(&rose->idletimer);
+		sk_reset_timer(sk, &rose->idletimer, rose->idletimer.expires);
 	}
 }
 
 void rose_stop_heartbeat(struct sock *sk)
 {
-	del_timer(&sk->sk_timer);
+	sk_stop_timer(sk, &sk->sk_timer);
 }
 
 void rose_stop_timer(struct sock *sk)
 {
-	del_timer(&rose_sk(sk)->timer);
+	sk_stop_timer(sk, &rose_sk(sk)->timer);
 }
 
 void rose_stop_idletimer(struct sock *sk)
 {
-	del_timer(&rose_sk(sk)->idletimer);
+	sk_stop_timer(sk, &rose_sk(sk)->idletimer);
 }
 
 static void rose_heartbeat_expiry(struct timer_list *t)
@@ -130,6 +130,7 @@ static void rose_heartbeat_expiry(struct timer_list *t)
 		    (sk->sk_state == TCP_LISTEN && sock_flag(sk, SOCK_DEAD))) {
 			bh_unlock_sock(sk);
 			rose_destroy_socket(sk);
+			sock_put(sk);
 			return;
 		}
 		break;
@@ -152,6 +153,7 @@ static void rose_heartbeat_expiry(struct timer_list *t)
 
 	rose_start_heartbeat(sk);
 	bh_unlock_sock(sk);
+	sock_put(sk);
 }
 
 static void rose_timer_expiry(struct timer_list *t)
@@ -181,6 +183,7 @@ static void rose_timer_expiry(struct timer_list *t)
 		break;
 	}
 	bh_unlock_sock(sk);
+	sock_put(sk);
 }
 
 static void rose_idletimer_expiry(struct timer_list *t)
@@ -205,4 +208,5 @@ static void rose_idletimer_expiry(struct timer_list *t)
 		sock_set_flag(sk, SOCK_DEAD);
 	}
 	bh_unlock_sock(sk);
+	sock_put(sk);
 }
-- 
GitLab


From 665030fd0c1ed9f505932e6e73e7a2c788787a0a Mon Sep 17 00:00:00 2001
From: Petr Machata <petrm@nvidia.com>
Date: Wed, 29 Jun 2022 10:02:05 +0300
Subject: [PATCH 1403/1731] mlxsw: spectrum_router: Fix rollback in tunnel next
 hop init

In mlxsw_sp_nexthop6_init(), a next hop is always added to the router
linked list, and mlxsw_sp_nexthop_type_init() is invoked afterwards. When
that function results in an error, the next hop will not have been removed
from the linked list. As the error is propagated upwards and the caller
frees the next hop object, the linked list ends up holding an invalid
object.

A similar issue comes up with mlxsw_sp_nexthop4_init(), where rollback
block does exist, however does not include the linked list removal.

Both IPv6 and IPv4 next hops have a similar issue with next-hop counter
rollbacks. As these were introduced in the same patchset as the next hop
linked list, include the cleanup in this patch.

Fixes: dbe4598c1e92 ("mlxsw: spectrum_router: Keep nexthops in a linked list")
Fixes: a5390278a5eb ("mlxsw: spectrum: Add support for setting counters on nexthops")
Signed-off-by: Petr Machata <petrm@nvidia.com>
Reviewed-by: Amit Cohen <amcohen@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Link: https://lore.kernel.org/r/20220629070205.803952-1-idosch@nvidia.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
 .../net/ethernet/mellanox/mlxsw/spectrum_router.c  | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c
index 9dbb573d53eaf..0d8a0068e4ca1 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c
@@ -4415,6 +4415,8 @@ static int mlxsw_sp_nexthop4_init(struct mlxsw_sp *mlxsw_sp,
 	return 0;
 
 err_nexthop_neigh_init:
+	list_del(&nh->router_list_node);
+	mlxsw_sp_nexthop_counter_free(mlxsw_sp, nh);
 	mlxsw_sp_nexthop_remove(mlxsw_sp, nh);
 	return err;
 }
@@ -6740,6 +6742,7 @@ static int mlxsw_sp_nexthop6_init(struct mlxsw_sp *mlxsw_sp,
 				  const struct fib6_info *rt)
 {
 	struct net_device *dev = rt->fib6_nh->fib_nh_dev;
+	int err;
 
 	nh->nhgi = nh_grp->nhgi;
 	nh->nh_weight = rt->fib6_nh->fib_nh_weight;
@@ -6755,7 +6758,16 @@ static int mlxsw_sp_nexthop6_init(struct mlxsw_sp *mlxsw_sp,
 		return 0;
 	nh->ifindex = dev->ifindex;
 
-	return mlxsw_sp_nexthop_type_init(mlxsw_sp, nh, dev);
+	err = mlxsw_sp_nexthop_type_init(mlxsw_sp, nh, dev);
+	if (err)
+		goto err_nexthop_type_init;
+
+	return 0;
+
+err_nexthop_type_init:
+	list_del(&nh->router_list_node);
+	mlxsw_sp_nexthop_counter_free(mlxsw_sp, nh);
+	return err;
 }
 
 static void mlxsw_sp_nexthop6_fini(struct mlxsw_sp *mlxsw_sp,
-- 
GitLab


From 0a18d802d65cf662644fd1d369c86d84a5630652 Mon Sep 17 00:00:00 2001
From: Jianglei Nie <niejianglei2021@163.com>
Date: Wed, 29 Jun 2022 15:55:50 +0800
Subject: [PATCH 1404/1731] net: sfp: fix memory leak in sfp_probe()

sfp_probe() allocates a memory chunk from sfp with sfp_alloc(). When
devm_add_action() fails, sfp is not freed, which leads to a memory leak.

We should use devm_add_action_or_reset() instead of devm_add_action().

Signed-off-by: Jianglei Nie <niejianglei2021@163.com>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://lore.kernel.org/r/20220629075550.2152003-1-niejianglei2021@163.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
 drivers/net/phy/sfp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/phy/sfp.c b/drivers/net/phy/sfp.c
index 9a5d5a10560fb..e7b0e12cc75bf 100644
--- a/drivers/net/phy/sfp.c
+++ b/drivers/net/phy/sfp.c
@@ -2516,7 +2516,7 @@ static int sfp_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, sfp);
 
-	err = devm_add_action(sfp->dev, sfp_cleanup, sfp);
+	err = devm_add_action_or_reset(sfp->dev, sfp_cleanup, sfp);
 	if (err < 0)
 		return err;
 
-- 
GitLab


From e61f294c7e8da94bb1c9d66f2cdcebfa2dc535a2 Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Tue, 21 Jun 2022 15:37:32 +0300
Subject: [PATCH 1405/1731] drm/i915/bios: debug log ddi port info after
 parsing
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The ddc pin and aux channel sanitization may disable DVI/HDMI and DP,
respectively, of ports parsed earlier, in "last one wins" fashion. With
parsing and printing interleaved, we'll end up logging support first and
disabling later anyway.

Now that we've split ddi port info parsing and printing, take it further
by doing the printing in a separate loop, fixing the logging.

Note that this also changes the logging order from VBT child device
order to port number order.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220621123732.1118437-1-jani.nikula@intel.com
---
 drivers/gpu/drm/i915/display/intel_bios.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index e89bc1d665f46..7f3fd32ea74de 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2668,8 +2668,6 @@ static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
 
 	sanitize_device_type(devdata, port);
 
-	print_ddi_port(devdata, port);
-
 	if (intel_bios_encoder_supports_dvi(devdata))
 		sanitize_ddc_pin(devdata, port);
 
@@ -2687,12 +2685,18 @@ static bool has_ddi_port_info(struct drm_i915_private *i915)
 static void parse_ddi_ports(struct drm_i915_private *i915)
 {
 	struct intel_bios_encoder_data *devdata;
+	enum port port;
 
 	if (!has_ddi_port_info(i915))
 		return;
 
 	list_for_each_entry(devdata, &i915->vbt.display_devices, node)
 		parse_ddi_port(devdata);
+
+	for_each_port(port) {
+		if (i915->vbt.ports[port])
+			print_ddi_port(i915->vbt.ports[port], port);
+	}
 }
 
 static void
-- 
GitLab


From 0f36d074aeb51a20508a65861d1518dbc231a1fc Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Tue, 28 Jun 2022 17:10:05 +0300
Subject: [PATCH 1406/1731] drm/i915: use DISPLAY_VER() instead of accessing
 match_info directly
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

We've just set up device info in i915_driver_create() so we can use
DISPLAY_VER() intead of looking at match_info directly.

Semantically we want to check the display version instead of the
graphics version, and for the earlier platforms they are always the
same.

v2: Use DISPLAY_VER() instead of GRAPHICS_VER() (Ville)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220628141005.226252-1-jani.nikula@intel.com
---
 drivers/gpu/drm/i915/i915_driver.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 9d0187ee4c7e2..2bd45e51d3b02 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -833,8 +833,6 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
  */
 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 {
-	const struct intel_device_info *match_info =
-		(struct intel_device_info *)ent->driver_data;
 	struct drm_i915_private *i915;
 	int ret;
 
@@ -843,7 +841,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 		return PTR_ERR(i915);
 
 	/* Disable nuclear pageflip by default on pre-ILK */
-	if (!i915->params.nuclear_pageflip && match_info->graphics.ver < 5)
+	if (!i915->params.nuclear_pageflip && DISPLAY_VER(i915) < 5)
 		i915->drm.driver_features &= ~DRIVER_ATOMIC;
 
 	ret = pci_enable_device(pdev);
-- 
GitLab


From 25deecb21c18ee29e3be8ac6177b2a9504c33d2d Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <masahiroy@kernel.org>
Date: Tue, 14 Jun 2022 02:09:00 +0900
Subject: [PATCH 1407/1731] s390: remove unneeded 'select BUILD_BIN2C'

Since commit 4c0f032d4963 ("s390/purgatory: Omit use of bin2c"),
s390 builds the purgatory without using bin2c.

Remove 'select BUILD_BIN2C' to avoid the unneeded build of bin2c.

Fixes: 4c0f032d4963 ("s390/purgatory: Omit use of bin2c")
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Link: https://lore.kernel.org/r/20220613170902.1775211-1-masahiroy@kernel.org
Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
---
 arch/s390/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index 91c0b80a8bf04..8cd9e56c629ba 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -484,7 +484,6 @@ config KEXEC
 config KEXEC_FILE
 	bool "kexec file based system call"
 	select KEXEC_CORE
-	select BUILD_BIN2C
 	depends on CRYPTO
 	depends on CRYPTO_SHA256
 	depends on CRYPTO_SHA256_S390
-- 
GitLab


From b9a56c113f907b19b91dc5c2383b0169831e15a4 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <masahiroy@kernel.org>
Date: Tue, 14 Jun 2022 02:09:01 +0900
Subject: [PATCH 1408/1731] s390/purgatory: hard-code obj-y in Makefile

The purgatory/ directory is entirely guarded in arch/s390/Kbuild.
CONFIG_ARCH_HAS_KEXEC_PURGATORY is bool type.

$(CONFIG_ARCH_HAS_KEXEC_PURGATORY) is always 'y' when Kbuild visits
this Makefile for building.

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Link: https://lore.kernel.org/r/20220613170902.1775211-2-masahiroy@kernel.org
Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
---
 arch/s390/purgatory/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/s390/purgatory/Makefile b/arch/s390/purgatory/Makefile
index 360ada80d20c3..3e2c17ba04def 100644
--- a/arch/s390/purgatory/Makefile
+++ b/arch/s390/purgatory/Makefile
@@ -51,4 +51,4 @@ $(obj)/purgatory.ro: $(obj)/purgatory $(obj)/purgatory.chk FORCE
 $(obj)/kexec-purgatory.o: $(obj)/kexec-purgatory.S $(obj)/purgatory.ro FORCE
 	$(call if_changed_rule,as_o_S)
 
-obj-$(CONFIG_ARCH_HAS_KEXEC_PURGATORY) += kexec-purgatory.o
+obj-y += kexec-purgatory.o
-- 
GitLab


From 20159e287a031bd6a28429675ccc66b06372fa3c Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <masahiroy@kernel.org>
Date: Tue, 14 Jun 2022 02:09:02 +0900
Subject: [PATCH 1409/1731] s390/purgatory: remove duplicated build rule of
 kexec-purgatory.o

This is equivalent to the pattern rule in scripts/Makefile.build.

Having the dependency on $(obj)/purgatory.ro is enough.

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Link: https://lore.kernel.org/r/20220613170902.1775211-3-masahiroy@kernel.org
Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
---
 arch/s390/purgatory/Makefile | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/s390/purgatory/Makefile b/arch/s390/purgatory/Makefile
index 3e2c17ba04def..d237bc6841cb8 100644
--- a/arch/s390/purgatory/Makefile
+++ b/arch/s390/purgatory/Makefile
@@ -48,7 +48,6 @@ OBJCOPYFLAGS_purgatory.ro += --remove-section='.note.*'
 $(obj)/purgatory.ro: $(obj)/purgatory $(obj)/purgatory.chk FORCE
 		$(call if_changed,objcopy)
 
-$(obj)/kexec-purgatory.o: $(obj)/kexec-purgatory.S $(obj)/purgatory.ro FORCE
-	$(call if_changed_rule,as_o_S)
+$(obj)/kexec-purgatory.o: $(obj)/purgatory.ro
 
 obj-y += kexec-purgatory.o
-- 
GitLab


From 29c1ac230e6056b26846c66881802b581a78ad72 Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Thu, 30 Jun 2022 13:25:57 +0100
Subject: [PATCH 1410/1731] io_uring: keep sendrecv flags in ioprio

We waste a u64 SQE field for flags even though we don't need as many
bits and it can be used for something more useful later. Store io_uring
specific send/recv flags in sqe->ioprio instead of ->addr2.

Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
Fixes: 0455d4ccec54 ("io_uring: add POLL_FIRST support for send/sendmsg and recv/recvmsg")
[axboe: change comment in io_uring.h as well]
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c                 | 12 ++++++++----
 include/uapi/linux/io_uring.h |  2 +-
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index 5ff2cdb425bc4..aeb042ba5cc53 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -1183,6 +1183,7 @@ static const struct io_op_def io_op_defs[] = {
 		.unbound_nonreg_file	= 1,
 		.pollout		= 1,
 		.needs_async_setup	= 1,
+		.ioprio			= 1,
 		.async_size		= sizeof(struct io_async_msghdr),
 	},
 	[IORING_OP_RECVMSG] = {
@@ -1191,6 +1192,7 @@ static const struct io_op_def io_op_defs[] = {
 		.pollin			= 1,
 		.buffer_select		= 1,
 		.needs_async_setup	= 1,
+		.ioprio			= 1,
 		.async_size		= sizeof(struct io_async_msghdr),
 	},
 	[IORING_OP_TIMEOUT] = {
@@ -1266,6 +1268,7 @@ static const struct io_op_def io_op_defs[] = {
 		.unbound_nonreg_file	= 1,
 		.pollout		= 1,
 		.audit_skip		= 1,
+		.ioprio			= 1,
 	},
 	[IORING_OP_RECV] = {
 		.needs_file		= 1,
@@ -1273,6 +1276,7 @@ static const struct io_op_def io_op_defs[] = {
 		.pollin			= 1,
 		.buffer_select		= 1,
 		.audit_skip		= 1,
+		.ioprio			= 1,
 	},
 	[IORING_OP_OPENAT2] = {
 	},
@@ -6075,12 +6079,12 @@ static int io_sendmsg_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe)
 {
 	struct io_sr_msg *sr = &req->sr_msg;
 
-	if (unlikely(sqe->file_index))
+	if (unlikely(sqe->file_index || sqe->addr2))
 		return -EINVAL;
 
 	sr->umsg = u64_to_user_ptr(READ_ONCE(sqe->addr));
 	sr->len = READ_ONCE(sqe->len);
-	sr->flags = READ_ONCE(sqe->addr2);
+	sr->flags = READ_ONCE(sqe->ioprio);
 	if (sr->flags & ~IORING_RECVSEND_POLL_FIRST)
 		return -EINVAL;
 	sr->msg_flags = READ_ONCE(sqe->msg_flags) | MSG_NOSIGNAL;
@@ -6311,12 +6315,12 @@ static int io_recvmsg_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe)
 {
 	struct io_sr_msg *sr = &req->sr_msg;
 
-	if (unlikely(sqe->file_index))
+	if (unlikely(sqe->file_index || sqe->addr2))
 		return -EINVAL;
 
 	sr->umsg = u64_to_user_ptr(READ_ONCE(sqe->addr));
 	sr->len = READ_ONCE(sqe->len);
-	sr->flags = READ_ONCE(sqe->addr2);
+	sr->flags = READ_ONCE(sqe->ioprio);
 	if (sr->flags & ~IORING_RECVSEND_POLL_FIRST)
 		return -EINVAL;
 	sr->msg_flags = READ_ONCE(sqe->msg_flags) | MSG_NOSIGNAL;
diff --git a/include/uapi/linux/io_uring.h b/include/uapi/linux/io_uring.h
index 53e7dae92e42e..f10b59d6693e3 100644
--- a/include/uapi/linux/io_uring.h
+++ b/include/uapi/linux/io_uring.h
@@ -244,7 +244,7 @@ enum io_uring_op {
 #define IORING_ASYNC_CANCEL_ANY	(1U << 2)
 
 /*
- * send/sendmsg and recv/recvmsg flags (sqe->addr2)
+ * send/sendmsg and recv/recvmsg flags (sqe->ioprio)
  *
  * IORING_RECVSEND_POLL_FIRST	If set, instead of first attempting to send
  *				or receive and arm poll if that yields an
-- 
GitLab


From 87a7d5350c67aca513dc0a80f696d5583430d594 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com>
Date: Wed, 29 Jun 2022 06:47:21 -0700
Subject: [PATCH 1411/1731] drm/i915: Drain freed object after suspend display
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Display is turned off by i915_drm_suspend() during the suspend
procedure, removing the last reference of some gem objects that were
used by display.

The issue is that those objects are only actually freed when
mm.free_work executed and that can happen very late in the suspend
process causing issues.
So here draining all freed objects released by display fixing suspend
issues.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220629134721.48375-1-jose.souza@intel.com
---
 drivers/gpu/drm/i915/i915_driver.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 2bd45e51d3b02..a67f20710978e 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1163,6 +1163,8 @@ static int i915_drm_suspend(struct drm_device *dev)
 
 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
+	i915_gem_drain_freed_objects(dev_priv);
+
 	return 0;
 }
 
-- 
GitLab


From 09007af2b627f0f195c6c53c4829b285cc3990ec Mon Sep 17 00:00:00 2001
From: Dylan Yudaken <dylany@fb.com>
Date: Thu, 30 Jun 2022 06:20:06 -0700
Subject: [PATCH 1412/1731] io_uring: fix provided buffer import

io_import_iovec uses the s pointer, but this was changed immediately
after the iovec was re-imported and so it was imported into the wrong
place.

Change the ordering.

Fixes: 2be2eb02e2f5 ("io_uring: ensure reads re-import for selected buffers")
Signed-off-by: Dylan Yudaken <dylany@fb.com>
Link: https://lore.kernel.org/r/20220630132006.2825668-1-dylany@fb.com
[axboe: ensure we don't half-import as well]
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index aeb042ba5cc53..0d491ad15b66a 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -4318,18 +4318,19 @@ static int io_read(struct io_kiocb *req, unsigned int issue_flags)
 		if (unlikely(ret < 0))
 			return ret;
 	} else {
+		rw = req->async_data;
+		s = &rw->s;
+
 		/*
 		 * Safe and required to re-import if we're using provided
 		 * buffers, as we dropped the selected one before retry.
 		 */
-		if (req->flags & REQ_F_BUFFER_SELECT) {
+		if (io_do_buffer_select(req)) {
 			ret = io_import_iovec(READ, req, &iovec, s, issue_flags);
 			if (unlikely(ret < 0))
 				return ret;
 		}
 
-		rw = req->async_data;
-		s = &rw->s;
 		/*
 		 * We come here from an earlier attempt, restore our state to
 		 * match in case it doesn't. It's cheap enough that we don't
-- 
GitLab


From e4f74400308cb8abde5fdc9cad609c2aba32110c Mon Sep 17 00:00:00 2001
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
Date: Sat, 11 Jun 2022 00:20:23 +0200
Subject: [PATCH 1413/1731] s390/archrandom: simplify back to earlier design
 and initialize earlier

s390x appears to present two RNG interfaces:
- a "TRNG" that gathers entropy using some hardware function; and
- a "DRBG" that takes in a seed and expands it.

Previously, the TRNG was wired up to arch_get_random_{long,int}(), but
it was observed that this was being called really frequently, resulting
in high overhead. So it was changed to be wired up to arch_get_random_
seed_{long,int}(), which was a reasonable decision. Later on, the DRBG
was then wired up to arch_get_random_{long,int}(), with a complicated
buffer filling thread, to control overhead and rate.

Fortunately, none of the performance issues matter much now. The RNG
always attempts to use arch_get_random_seed_{long,int}() first, which
means a complicated implementation of arch_get_random_{long,int}() isn't
really valuable or useful to have around. And it's only used when
reseeding, which means it won't hit the high throughput complications
that were faced before.

So this commit returns to an earlier design of just calling the TRNG in
arch_get_random_seed_{long,int}(), and returning false in arch_get_
random_{long,int}().

Part of what makes the simplification possible is that the RNG now seeds
itself using the TRNG at bootup. But this only works if the TRNG is
detected early in boot, before random_init() is called. So this commit
also causes that check to happen in setup_arch().

Cc: stable@vger.kernel.org
Cc: Harald Freudenberger <freude@linux.ibm.com>
Cc: Ingo Franzki <ifranzki@linux.ibm.com>
Cc: Juergen Christ <jchrist@linux.ibm.com>
Cc: Heiko Carstens <hca@linux.ibm.com>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Link: https://lore.kernel.org/r/20220610222023.378448-1-Jason@zx2c4.com
Reviewed-by: Harald Freudenberger <freude@linux.ibm.com>
Acked-by: Heiko Carstens <hca@linux.ibm.com>
Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
---
 arch/s390/crypto/arch_random.c     | 217 -----------------------------
 arch/s390/include/asm/archrandom.h |  14 +-
 arch/s390/kernel/setup.c           |   5 +
 3 files changed, 12 insertions(+), 224 deletions(-)

diff --git a/arch/s390/crypto/arch_random.c b/arch/s390/crypto/arch_random.c
index 56007c763902a..1f2d40993c4d2 100644
--- a/arch/s390/crypto/arch_random.c
+++ b/arch/s390/crypto/arch_random.c
@@ -4,232 +4,15 @@
  *
  * Copyright IBM Corp. 2017, 2020
  * Author(s): Harald Freudenberger
- *
- * The s390_arch_random_generate() function may be called from random.c
- * in interrupt context. So this implementation does the best to be very
- * fast. There is a buffer of random data which is asynchronously checked
- * and filled by a workqueue thread.
- * If there are enough bytes in the buffer the s390_arch_random_generate()
- * just delivers these bytes. Otherwise false is returned until the
- * worker thread refills the buffer.
- * The worker fills the rng buffer by pulling fresh entropy from the
- * high quality (but slow) true hardware random generator. This entropy
- * is then spread over the buffer with an pseudo random generator PRNG.
- * As the arch_get_random_seed_long() fetches 8 bytes and the calling
- * function add_interrupt_randomness() counts this as 1 bit entropy the
- * distribution needs to make sure there is in fact 1 bit entropy contained
- * in 8 bytes of the buffer. The current values pull 32 byte entropy
- * and scatter this into a 2048 byte buffer. So 8 byte in the buffer
- * will contain 1 bit of entropy.
- * The worker thread is rescheduled based on the charge level of the
- * buffer but at least with 500 ms delay to avoid too much CPU consumption.
- * So the max. amount of rng data delivered via arch_get_random_seed is
- * limited to 4k bytes per second.
  */
 
 #include <linux/kernel.h>
 #include <linux/atomic.h>
 #include <linux/random.h>
-#include <linux/slab.h>
 #include <linux/static_key.h>
-#include <linux/workqueue.h>
-#include <linux/moduleparam.h>
 #include <asm/cpacf.h>
 
 DEFINE_STATIC_KEY_FALSE(s390_arch_random_available);
 
 atomic64_t s390_arch_random_counter = ATOMIC64_INIT(0);
 EXPORT_SYMBOL(s390_arch_random_counter);
-
-#define ARCH_REFILL_TICKS (HZ/2)
-#define ARCH_PRNG_SEED_SIZE 32
-#define ARCH_RNG_BUF_SIZE 2048
-
-static DEFINE_SPINLOCK(arch_rng_lock);
-static u8 *arch_rng_buf;
-static unsigned int arch_rng_buf_idx;
-
-static void arch_rng_refill_buffer(struct work_struct *);
-static DECLARE_DELAYED_WORK(arch_rng_work, arch_rng_refill_buffer);
-
-bool s390_arch_random_generate(u8 *buf, unsigned int nbytes)
-{
-	/* max hunk is ARCH_RNG_BUF_SIZE */
-	if (nbytes > ARCH_RNG_BUF_SIZE)
-		return false;
-
-	/* lock rng buffer */
-	if (!spin_trylock(&arch_rng_lock))
-		return false;
-
-	/* try to resolve the requested amount of bytes from the buffer */
-	arch_rng_buf_idx -= nbytes;
-	if (arch_rng_buf_idx < ARCH_RNG_BUF_SIZE) {
-		memcpy(buf, arch_rng_buf + arch_rng_buf_idx, nbytes);
-		atomic64_add(nbytes, &s390_arch_random_counter);
-		spin_unlock(&arch_rng_lock);
-		return true;
-	}
-
-	/* not enough bytes in rng buffer, refill is done asynchronously */
-	spin_unlock(&arch_rng_lock);
-
-	return false;
-}
-EXPORT_SYMBOL(s390_arch_random_generate);
-
-static void arch_rng_refill_buffer(struct work_struct *unused)
-{
-	unsigned int delay = ARCH_REFILL_TICKS;
-
-	spin_lock(&arch_rng_lock);
-	if (arch_rng_buf_idx > ARCH_RNG_BUF_SIZE) {
-		/* buffer is exhausted and needs refill */
-		u8 seed[ARCH_PRNG_SEED_SIZE];
-		u8 prng_wa[240];
-		/* fetch ARCH_PRNG_SEED_SIZE bytes of entropy */
-		cpacf_trng(NULL, 0, seed, sizeof(seed));
-		/* blow this entropy up to ARCH_RNG_BUF_SIZE with PRNG */
-		memset(prng_wa, 0, sizeof(prng_wa));
-		cpacf_prno(CPACF_PRNO_SHA512_DRNG_SEED,
-			   &prng_wa, NULL, 0, seed, sizeof(seed));
-		cpacf_prno(CPACF_PRNO_SHA512_DRNG_GEN,
-			   &prng_wa, arch_rng_buf, ARCH_RNG_BUF_SIZE, NULL, 0);
-		arch_rng_buf_idx = ARCH_RNG_BUF_SIZE;
-	}
-	delay += (ARCH_REFILL_TICKS * arch_rng_buf_idx) / ARCH_RNG_BUF_SIZE;
-	spin_unlock(&arch_rng_lock);
-
-	/* kick next check */
-	queue_delayed_work(system_long_wq, &arch_rng_work, delay);
-}
-
-/*
- * Here follows the implementation of s390_arch_get_random_long().
- *
- * The random longs to be pulled by arch_get_random_long() are
- * prepared in an 4K buffer which is filled from the NIST 800-90
- * compliant s390 drbg. By default the random long buffer is refilled
- * 256 times before the drbg itself needs a reseed. The reseed of the
- * drbg is done with 32 bytes fetched from the high quality (but slow)
- * trng which is assumed to deliver 100% entropy. So the 32 * 8 = 256
- * bits of entropy are spread over 256 * 4KB = 1MB serving 131072
- * arch_get_random_long() invocations before reseeded.
- *
- * How often the 4K random long buffer is refilled with the drbg
- * before the drbg is reseeded can be adjusted. There is a module
- * parameter 's390_arch_rnd_long_drbg_reseed' accessible via
- *   /sys/module/arch_random/parameters/rndlong_drbg_reseed
- * or as kernel command line parameter
- *   arch_random.rndlong_drbg_reseed=<value>
- * This parameter tells how often the drbg fills the 4K buffer before
- * it is re-seeded by fresh entropy from the trng.
- * A value of 16 results in reseeding the drbg at every 16 * 4 KB = 64
- * KB with 32 bytes of fresh entropy pulled from the trng. So a value
- * of 16 would result in 256 bits entropy per 64 KB.
- * A value of 256 results in 1MB of drbg output before a reseed of the
- * drbg is done. So this would spread the 256 bits of entropy among 1MB.
- * Setting this parameter to 0 forces the reseed to take place every
- * time the 4K buffer is depleted, so the entropy rises to 256 bits
- * entropy per 4K or 0.5 bit entropy per arch_get_random_long().  With
- * setting this parameter to negative values all this effort is
- * disabled, arch_get_random long() returns false and thus indicating
- * that the arch_get_random_long() feature is disabled at all.
- */
-
-static unsigned long rndlong_buf[512];
-static DEFINE_SPINLOCK(rndlong_lock);
-static int rndlong_buf_index;
-
-static int rndlong_drbg_reseed = 256;
-module_param_named(rndlong_drbg_reseed, rndlong_drbg_reseed, int, 0600);
-MODULE_PARM_DESC(rndlong_drbg_reseed, "s390 arch_get_random_long() drbg reseed");
-
-static inline void refill_rndlong_buf(void)
-{
-	static u8 prng_ws[240];
-	static int drbg_counter;
-
-	if (--drbg_counter < 0) {
-		/* need to re-seed the drbg */
-		u8 seed[32];
-
-		/* fetch seed from trng */
-		cpacf_trng(NULL, 0, seed, sizeof(seed));
-		/* seed drbg */
-		memset(prng_ws, 0, sizeof(prng_ws));
-		cpacf_prno(CPACF_PRNO_SHA512_DRNG_SEED,
-			   &prng_ws, NULL, 0, seed, sizeof(seed));
-		/* re-init counter for drbg */
-		drbg_counter = rndlong_drbg_reseed;
-	}
-
-	/* fill the arch_get_random_long buffer from drbg */
-	cpacf_prno(CPACF_PRNO_SHA512_DRNG_GEN, &prng_ws,
-		   (u8 *) rndlong_buf, sizeof(rndlong_buf),
-		   NULL, 0);
-}
-
-bool s390_arch_get_random_long(unsigned long *v)
-{
-	bool rc = false;
-	unsigned long flags;
-
-	/* arch_get_random_long() disabled ? */
-	if (rndlong_drbg_reseed < 0)
-		return false;
-
-	/* try to lock the random long lock */
-	if (!spin_trylock_irqsave(&rndlong_lock, flags))
-		return false;
-
-	if (--rndlong_buf_index >= 0) {
-		/* deliver next long value from the buffer */
-		*v = rndlong_buf[rndlong_buf_index];
-		rc = true;
-		goto out;
-	}
-
-	/* buffer is depleted and needs refill */
-	if (in_interrupt()) {
-		/* delay refill in interrupt context to next caller */
-		rndlong_buf_index = 0;
-		goto out;
-	}
-
-	/* refill random long buffer */
-	refill_rndlong_buf();
-	rndlong_buf_index = ARRAY_SIZE(rndlong_buf);
-
-	/* and provide one random long */
-	*v = rndlong_buf[--rndlong_buf_index];
-	rc = true;
-
-out:
-	spin_unlock_irqrestore(&rndlong_lock, flags);
-	return rc;
-}
-EXPORT_SYMBOL(s390_arch_get_random_long);
-
-static int __init s390_arch_random_init(void)
-{
-	/* all the needed PRNO subfunctions available ? */
-	if (cpacf_query_func(CPACF_PRNO, CPACF_PRNO_TRNG) &&
-	    cpacf_query_func(CPACF_PRNO, CPACF_PRNO_SHA512_DRNG_GEN)) {
-
-		/* alloc arch random working buffer */
-		arch_rng_buf = kmalloc(ARCH_RNG_BUF_SIZE, GFP_KERNEL);
-		if (!arch_rng_buf)
-			return -ENOMEM;
-
-		/* kick worker queue job to fill the random buffer */
-		queue_delayed_work(system_long_wq,
-				   &arch_rng_work, ARCH_REFILL_TICKS);
-
-		/* enable arch random to the outside world */
-		static_branch_enable(&s390_arch_random_available);
-	}
-
-	return 0;
-}
-arch_initcall(s390_arch_random_init);
diff --git a/arch/s390/include/asm/archrandom.h b/arch/s390/include/asm/archrandom.h
index 5dc712fde3c7f..2c6e1c6ecbe78 100644
--- a/arch/s390/include/asm/archrandom.h
+++ b/arch/s390/include/asm/archrandom.h
@@ -15,17 +15,13 @@
 
 #include <linux/static_key.h>
 #include <linux/atomic.h>
+#include <asm/cpacf.h>
 
 DECLARE_STATIC_KEY_FALSE(s390_arch_random_available);
 extern atomic64_t s390_arch_random_counter;
 
-bool s390_arch_get_random_long(unsigned long *v);
-bool s390_arch_random_generate(u8 *buf, unsigned int nbytes);
-
 static inline bool __must_check arch_get_random_long(unsigned long *v)
 {
-	if (static_branch_likely(&s390_arch_random_available))
-		return s390_arch_get_random_long(v);
 	return false;
 }
 
@@ -37,7 +33,9 @@ static inline bool __must_check arch_get_random_int(unsigned int *v)
 static inline bool __must_check arch_get_random_seed_long(unsigned long *v)
 {
 	if (static_branch_likely(&s390_arch_random_available)) {
-		return s390_arch_random_generate((u8 *)v, sizeof(*v));
+		cpacf_trng(NULL, 0, (u8 *)v, sizeof(*v));
+		atomic64_add(sizeof(*v), &s390_arch_random_counter);
+		return true;
 	}
 	return false;
 }
@@ -45,7 +43,9 @@ static inline bool __must_check arch_get_random_seed_long(unsigned long *v)
 static inline bool __must_check arch_get_random_seed_int(unsigned int *v)
 {
 	if (static_branch_likely(&s390_arch_random_available)) {
-		return s390_arch_random_generate((u8 *)v, sizeof(*v));
+		cpacf_trng(NULL, 0, (u8 *)v, sizeof(*v));
+		atomic64_add(sizeof(*v), &s390_arch_random_counter);
+		return true;
 	}
 	return false;
 }
diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c
index 8d91eccc09632..0a37f5de28631 100644
--- a/arch/s390/kernel/setup.c
+++ b/arch/s390/kernel/setup.c
@@ -875,6 +875,11 @@ static void __init setup_randomness(void)
 	if (stsi(vmms, 3, 2, 2) == 0 && vmms->count)
 		add_device_randomness(&vmms->vm, sizeof(vmms->vm[0]) * vmms->count);
 	memblock_free(vmms, PAGE_SIZE);
+
+#ifdef CONFIG_ARCH_RANDOM
+	if (cpacf_query_func(CPACF_PRNO, CPACF_PRNO_TRNG))
+		static_branch_enable(&s390_arch_random_available);
+#endif
 }
 
 /*
-- 
GitLab


From d608f45ed3cfd411a409cec93fa64232181752ff Mon Sep 17 00:00:00 2001
From: Jiang Jian <jiangjian@cdjrlc.com>
Date: Wed, 22 Jun 2022 22:27:13 +0800
Subject: [PATCH 1414/1731] s390/sclp: Fix typo in comments

Remove the repeated word 'and' from comments

Signed-off-by: Jiang Jian <jiangjian@cdjrlc.com>
Reviewed-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/20220622142713.14187-1-jiangjian@cdjrlc.com
Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
---
 drivers/s390/char/sclp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/s390/char/sclp.c b/drivers/s390/char/sclp.c
index cb24917619589..ae1d6ee382a50 100644
--- a/drivers/s390/char/sclp.c
+++ b/drivers/s390/char/sclp.c
@@ -60,7 +60,7 @@ static LIST_HEAD(sclp_reg_list);
 /* List of queued requests. */
 static LIST_HEAD(sclp_req_queue);
 
-/* Data for read and and init requests. */
+/* Data for read and init requests. */
 static struct sclp_req sclp_read_req;
 static struct sclp_req sclp_init_req;
 static void *sclp_read_sccb;
-- 
GitLab


From d7d488f41b41a1b7a1df3c74f2f65eb4585f5d55 Mon Sep 17 00:00:00 2001
From: Zhang Jiaming <jiaming@nfschina.com>
Date: Thu, 23 Jun 2022 14:05:43 +0800
Subject: [PATCH 1415/1731] s390/qdio: Fix spelling mistake

Change 'defineable' to 'definable'.
Change 'paramater' to 'parameter'.

Signed-off-by: Zhang Jiaming <jiaming@nfschina.com>
Reviewed-by: Benjamin Block <bblock@linux.ibm.com>
Link: https://lore.kernel.org/r/20220623060543.12870-1-jiaming@nfschina.com
Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
---
 arch/s390/include/asm/qdio.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h
index 54ae2dc65e3b2..2f983e0b95e09 100644
--- a/arch/s390/include/asm/qdio.h
+++ b/arch/s390/include/asm/qdio.h
@@ -133,9 +133,9 @@ struct slibe {
  * @sb_count: number of storage blocks
  * @sba: storage block element addresses
  * @dcount: size of storage block elements
- * @user0: user defineable value
- * @res4: reserved paramater
- * @user1: user defineable value
+ * @user0: user definable value
+ * @res4: reserved parameter
+ * @user1: user definable value
  */
 struct qaob {
 	u64 res0[6];
-- 
GitLab


From 62f46fc7b8c639bc97cc9c69e063c40970b6e14c Mon Sep 17 00:00:00 2001
From: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Date: Fri, 6 May 2022 19:20:09 +0530
Subject: [PATCH 1416/1731] thermal: intel_tcc_cooling: Add TCC cooling support
 for RaptorLake

Add RaptorLake to the list of processor models supported by the Intel
TCC cooling driver.

Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
[ rjw: Subject edits, new changelog ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 drivers/thermal/intel/intel_tcc_cooling.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/thermal/intel/intel_tcc_cooling.c b/drivers/thermal/intel/intel_tcc_cooling.c
index cd80c7db40730..a9596e7562ea6 100644
--- a/drivers/thermal/intel/intel_tcc_cooling.c
+++ b/drivers/thermal/intel/intel_tcc_cooling.c
@@ -81,6 +81,7 @@ static const struct x86_cpu_id tcc_ids[] __initconst = {
 	X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, NULL),
 	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, NULL),
 	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, NULL),
+	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, NULL),
 	{}
 };
 
-- 
GitLab


From 9c5de246c1dbe785268fc2e83c88624b92e4ec93 Mon Sep 17 00:00:00 2001
From: Casper Andersson <casper.casan@gmail.com>
Date: Thu, 30 Jun 2022 14:22:26 +0200
Subject: [PATCH 1417/1731] net: sparx5: mdb add/del handle non-sparx5 devices

When adding/deleting mdb entries on other net_devices, eg., tap
interfaces, it should not crash.

Fixes: 3bacfccdcb2d ("net: sparx5: Add mdb handlers")
Signed-off-by: Casper Andersson <casper.casan@gmail.com>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Link: https://lore.kernel.org/r/20220630122226.316812-1-casper.casan@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c b/drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
index 3429660cd2e5d..5edc8b7176c82 100644
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
@@ -396,6 +396,9 @@ static int sparx5_handle_port_mdb_add(struct net_device *dev,
 	u32 mact_entry;
 	int res, err;
 
+	if (!sparx5_netdevice_check(dev))
+		return -EOPNOTSUPP;
+
 	if (netif_is_bridge_master(v->obj.orig_dev)) {
 		sparx5_mact_learn(spx5, PGID_CPU, v->addr, v->vid);
 		return 0;
@@ -466,6 +469,9 @@ static int sparx5_handle_port_mdb_del(struct net_device *dev,
 	u32 mact_entry, res, pgid_entry[3];
 	int err;
 
+	if (!sparx5_netdevice_check(dev))
+		return -EOPNOTSUPP;
+
 	if (netif_is_bridge_master(v->obj.orig_dev)) {
 		sparx5_mact_forget(spx5, v->addr, v->vid);
 		return 0;
-- 
GitLab


From ff1fa2081d173b01cebe2fbf0a2d0f1cee9ce4b5 Mon Sep 17 00:00:00 2001
From: Jakub Kicinski <kuba@kernel.org>
Date: Wed, 29 Jun 2022 11:19:10 -0700
Subject: [PATCH 1418/1731] net: tun: avoid disabling NAPI twice

Eric reports that syzbot made short work out of my speculative
fix. Indeed when queue gets detached its tfile->tun remains,
so we would try to stop NAPI twice with a detach(), close()
sequence.

Alternative fix would be to move tun_napi_disable() to
tun_detach_all() and let the NAPI run after the queue
has been detached.

Fixes: a8fc8cb5692a ("net: tun: stop NAPI when detaching queues")
Reported-by: syzbot <syzkaller@googlegroups.com>
Reported-by: Eric Dumazet <edumazet@google.com>
Reviewed-by: Eric Dumazet <edumazet@google.com>
Link: https://lore.kernel.org/r/20220629181911.372047-1-kuba@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/tun.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/tun.c b/drivers/net/tun.c
index e2eb35887394e..259b2b84b2b39 100644
--- a/drivers/net/tun.c
+++ b/drivers/net/tun.c
@@ -640,7 +640,8 @@ static void __tun_detach(struct tun_file *tfile, bool clean)
 	tun = rtnl_dereference(tfile->tun);
 
 	if (tun && clean) {
-		tun_napi_disable(tfile);
+		if (!tfile->detached)
+			tun_napi_disable(tfile);
 		tun_napi_del(tfile);
 	}
 
-- 
GitLab


From 839b92fede7ba308f1a475aa00fea55f63b7fccf Mon Sep 17 00:00:00 2001
From: Jakub Kicinski <kuba@kernel.org>
Date: Wed, 29 Jun 2022 11:19:11 -0700
Subject: [PATCH 1419/1731] selftest: tun: add test for NAPI dismantle

Being lazy does not pay, add the test for various
ordering of tun queue close / detach / destroy.

Link: https://lore.kernel.org/r/20220629181911.372047-2-kuba@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 tools/testing/selftests/net/Makefile |   2 +-
 tools/testing/selftests/net/tun.c    | 162 +++++++++++++++++++++++++++
 2 files changed, 163 insertions(+), 1 deletion(-)
 create mode 100644 tools/testing/selftests/net/tun.c

diff --git a/tools/testing/selftests/net/Makefile b/tools/testing/selftests/net/Makefile
index 7ea54af554909..ddad703ace348 100644
--- a/tools/testing/selftests/net/Makefile
+++ b/tools/testing/selftests/net/Makefile
@@ -54,7 +54,7 @@ TEST_GEN_FILES += ipsec
 TEST_GEN_FILES += ioam6_parser
 TEST_GEN_FILES += gro
 TEST_GEN_PROGS = reuseport_bpf reuseport_bpf_cpu reuseport_bpf_numa
-TEST_GEN_PROGS += reuseport_dualstack reuseaddr_conflict tls
+TEST_GEN_PROGS += reuseport_dualstack reuseaddr_conflict tls tun
 TEST_GEN_FILES += toeplitz
 TEST_GEN_FILES += cmsg_sender
 TEST_GEN_FILES += stress_reuseport_listen
diff --git a/tools/testing/selftests/net/tun.c b/tools/testing/selftests/net/tun.c
new file mode 100644
index 0000000000000..fa83918b62d1b
--- /dev/null
+++ b/tools/testing/selftests/net/tun.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#define _GNU_SOURCE
+
+#include <errno.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <linux/if.h>
+#include <linux/if_tun.h>
+#include <linux/netlink.h>
+#include <linux/rtnetlink.h>
+#include <sys/ioctl.h>
+#include <sys/socket.h>
+
+#include "../kselftest_harness.h"
+
+static int tun_attach(int fd, char *dev)
+{
+	struct ifreq ifr;
+
+	memset(&ifr, 0, sizeof(ifr));
+	strcpy(ifr.ifr_name, dev);
+	ifr.ifr_flags = IFF_ATTACH_QUEUE;
+
+	return ioctl(fd, TUNSETQUEUE, (void *) &ifr);
+}
+
+static int tun_detach(int fd, char *dev)
+{
+	struct ifreq ifr;
+
+	memset(&ifr, 0, sizeof(ifr));
+	strcpy(ifr.ifr_name, dev);
+	ifr.ifr_flags = IFF_DETACH_QUEUE;
+
+	return ioctl(fd, TUNSETQUEUE, (void *) &ifr);
+}
+
+static int tun_alloc(char *dev)
+{
+	struct ifreq ifr;
+	int fd, err;
+
+	fd = open("/dev/net/tun", O_RDWR);
+	if (fd < 0) {
+		fprintf(stderr, "can't open tun: %s\n", strerror(errno));
+		return fd;
+	}
+
+	memset(&ifr, 0, sizeof(ifr));
+	strcpy(ifr.ifr_name, dev);
+	ifr.ifr_flags = IFF_TAP | IFF_NAPI | IFF_MULTI_QUEUE;
+
+	err = ioctl(fd, TUNSETIFF, (void *) &ifr);
+	if (err < 0) {
+		fprintf(stderr, "can't TUNSETIFF: %s\n", strerror(errno));
+		close(fd);
+		return err;
+	}
+	strcpy(dev, ifr.ifr_name);
+	return fd;
+}
+
+static int tun_delete(char *dev)
+{
+	struct {
+		struct nlmsghdr  nh;
+		struct ifinfomsg ifm;
+		unsigned char    data[64];
+	} req;
+	struct rtattr *rta;
+	int ret, rtnl;
+
+	rtnl = socket(AF_NETLINK, SOCK_DGRAM, NETLINK_ROUTE);
+	if (rtnl < 0) {
+		fprintf(stderr, "can't open rtnl: %s\n", strerror(errno));
+		return 1;
+	}
+
+	memset(&req, 0, sizeof(req));
+	req.nh.nlmsg_len = NLMSG_ALIGN(NLMSG_LENGTH(sizeof(req.ifm)));
+	req.nh.nlmsg_flags = NLM_F_REQUEST;
+	req.nh.nlmsg_type = RTM_DELLINK;
+
+	req.ifm.ifi_family = AF_UNSPEC;
+
+	rta = (struct rtattr *)(((char *)&req) + NLMSG_ALIGN(req.nh.nlmsg_len));
+	rta->rta_type = IFLA_IFNAME;
+	rta->rta_len = RTA_LENGTH(IFNAMSIZ);
+	req.nh.nlmsg_len += rta->rta_len;
+	memcpy(RTA_DATA(rta), dev, IFNAMSIZ);
+
+	ret = send(rtnl, &req, req.nh.nlmsg_len, 0);
+	if (ret < 0)
+		fprintf(stderr, "can't send: %s\n", strerror(errno));
+	ret = (unsigned int)ret != req.nh.nlmsg_len;
+
+	close(rtnl);
+	return ret;
+}
+
+FIXTURE(tun)
+{
+	char ifname[IFNAMSIZ];
+	int fd, fd2;
+};
+
+FIXTURE_SETUP(tun)
+{
+	memset(self->ifname, 0, sizeof(self->ifname));
+
+	self->fd = tun_alloc(self->ifname);
+	ASSERT_GE(self->fd, 0);
+
+	self->fd2 = tun_alloc(self->ifname);
+	ASSERT_GE(self->fd2, 0);
+}
+
+FIXTURE_TEARDOWN(tun)
+{
+	if (self->fd >= 0)
+		close(self->fd);
+	if (self->fd2 >= 0)
+		close(self->fd2);
+}
+
+TEST_F(tun, delete_detach_close) {
+	EXPECT_EQ(tun_delete(self->ifname), 0);
+	EXPECT_EQ(tun_detach(self->fd, self->ifname), -1);
+	EXPECT_EQ(errno, 22);
+}
+
+TEST_F(tun, detach_delete_close) {
+	EXPECT_EQ(tun_detach(self->fd, self->ifname), 0);
+	EXPECT_EQ(tun_delete(self->ifname), 0);
+}
+
+TEST_F(tun, detach_close_delete) {
+	EXPECT_EQ(tun_detach(self->fd, self->ifname), 0);
+	close(self->fd);
+	self->fd = -1;
+	EXPECT_EQ(tun_delete(self->ifname), 0);
+}
+
+TEST_F(tun, reattach_delete_close) {
+	EXPECT_EQ(tun_detach(self->fd, self->ifname), 0);
+	EXPECT_EQ(tun_attach(self->fd, self->ifname), 0);
+	EXPECT_EQ(tun_delete(self->ifname), 0);
+}
+
+TEST_F(tun, reattach_close_delete) {
+	EXPECT_EQ(tun_detach(self->fd, self->ifname), 0);
+	EXPECT_EQ(tun_attach(self->fd, self->ifname), 0);
+	close(self->fd);
+	self->fd = -1;
+	EXPECT_EQ(tun_delete(self->ifname), 0);
+}
+
+TEST_HARNESS_MAIN
-- 
GitLab


From 58bf4db695287c4bb2a5fc9fc12c78fdd4c36894 Mon Sep 17 00:00:00 2001
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Date: Wed, 29 Jun 2022 21:30:07 +0300
Subject: [PATCH 1420/1731] net: dsa: felix: fix race between reading PSFP
 stats and port stats

Both PSFP stats and the port stats read by ocelot_check_stats_work() are
indirectly read through the same mechanism - write to STAT_CFG:STAT_VIEW,
read from SYS:STAT:CNT[n].

It's just that for port stats, we write STAT_VIEW with the index of the
port, and for PSFP stats, we write STAT_VIEW with the filter index.

So if we allow them to run concurrently, ocelot_check_stats_work() may
change the view from vsc9959_psfp_counters_get(), and vice versa.

Fixes: 7d4b564d6add ("net: dsa: felix: support psfp filter on vsc9959")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Link: https://lore.kernel.org/r/20220629183007.3808130-1-vladimir.oltean@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/dsa/ocelot/felix_vsc9959.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/dsa/ocelot/felix_vsc9959.c b/drivers/net/dsa/ocelot/felix_vsc9959.c
index 570d0204b7bef..9c27b9b0128db 100644
--- a/drivers/net/dsa/ocelot/felix_vsc9959.c
+++ b/drivers/net/dsa/ocelot/felix_vsc9959.c
@@ -1886,6 +1886,8 @@ static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot,
 static void vsc9959_psfp_counters_get(struct ocelot *ocelot, u32 index,
 				      struct felix_stream_filter_counters *counters)
 {
+	mutex_lock(&ocelot->stats_lock);
+
 	ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(index),
 		   SYS_STAT_CFG_STAT_VIEW_M,
 		   SYS_STAT_CFG);
@@ -1900,6 +1902,8 @@ static void vsc9959_psfp_counters_get(struct ocelot *ocelot, u32 index,
 		     SYS_STAT_CFG_STAT_VIEW(index) |
 		     SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10),
 		     SYS_STAT_CFG);
+
+	mutex_unlock(&ocelot->stats_lock);
 }
 
 static int vsc9959_psfp_filter_add(struct ocelot *ocelot, int port,
-- 
GitLab


From 90d5fd317c745a80019ed7f12a1933ce6116e0e4 Mon Sep 17 00:00:00 2001
From: Jack Xiao <Jack.Xiao@amd.com>
Date: Mon, 6 Jun 2022 17:30:34 +0800
Subject: [PATCH 1421/1731] drm/amdgpu/mes11: update mes interface for acessing
 registers

Update MES firmware api for accessing registers.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/include/mes_v11_api_def.h | 37 +++++++++++++------
 1 file changed, 26 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/mes_v11_api_def.h b/drivers/gpu/drm/amd/include/mes_v11_api_def.h
index fa1b9e0d299a5..1d37ec2cd7377 100644
--- a/drivers/gpu/drm/amd/include/mes_v11_api_def.h
+++ b/drivers/gpu/drm/amd/include/mes_v11_api_def.h
@@ -508,27 +508,40 @@ union MESAPI__SET_DEBUG_VMID {
 };
 
 enum MESAPI_MISC_OPCODE {
-	MESAPI_MISC__MODIFY_REG,
+	MESAPI_MISC__WRITE_REG,
 	MESAPI_MISC__INV_GART,
 	MESAPI_MISC__QUERY_STATUS,
+	MESAPI_MISC__READ_REG,
+	MESAPI_MISC__WAIT_REG_MEM,
 	MESAPI_MISC__MAX,
 };
 
-enum MODIFY_REG_SUBCODE {
-	MODIFY_REG__OVERWRITE,
-	MODIFY_REG__RMW_OR,
-	MODIFY_REG__RMW_AND,
-	MODIFY_REG__MAX,
-};
-
 enum { MISC_DATA_MAX_SIZE_IN_DWORDS = 20 };
 
-struct MODIFY_REG {
-	enum MODIFY_REG_SUBCODE   subcode;
+struct WRITE_REG {
 	uint32_t                  reg_offset;
 	uint32_t                  reg_value;
 };
 
+struct READ_REG {
+	uint32_t                  reg_offset;
+	uint64_t                  buffer_addr;
+};
+
+enum WRM_OPERATION {
+	WRM_OPERATION__WAIT_REG_MEM,
+	WRM_OPERATION__WR_WAIT_WR_REG,
+	WRM_OPERATION__MAX,
+};
+
+struct WAIT_REG_MEM {
+	enum WRM_OPERATION         op;
+	uint32_t                   reference;
+	uint32_t                   mask;
+	uint32_t                   reg_offset1;
+	uint32_t                   reg_offset2;
+};
+
 struct INV_GART {
 	uint64_t                  inv_range_va_start;
 	uint64_t                  inv_range_size;
@@ -545,9 +558,11 @@ union MESAPI__MISC {
 		struct MES_API_STATUS	api_status;
 
 		union {
-			struct		MODIFY_REG modify_reg;
+			struct		WRITE_REG write_reg;
 			struct		INV_GART inv_gart;
 			struct		QUERY_STATUS query_status;
+			struct		READ_REG read_reg;
+			struct          WAIT_REG_MEM wait_reg_mem;
 			uint32_t	data[MISC_DATA_MAX_SIZE_IN_DWORDS];
 		};
 	};
-- 
GitLab


From 6a4a1f6054318cd3590562668798304b4351ef36 Mon Sep 17 00:00:00 2001
From: Jack Xiao <Jack.Xiao@amd.com>
Date: Thu, 16 Jun 2022 21:23:45 +0800
Subject: [PATCH 1422/1731] drm/amdgpu: add common interface for mes misc op

Add common interface for mes misc op, including accessing register
interface.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 46 +++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index 074418c63e4b4..3cec87e023b3d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -119,6 +119,10 @@ struct amdgpu_mes {
 	uint32_t			query_status_fence_offs;
 	uint64_t			query_status_fence_gpu_addr;
 	uint64_t			*query_status_fence_ptr;
+	uint32_t                        read_val_offs;
+	uint64_t			read_val_gpu_addr;
+	uint32_t			*read_val_ptr;
+
 	uint32_t			saved_flags;
 
 	/* initialize kiq pipe */
@@ -246,6 +250,36 @@ struct mes_resume_gang_input {
 	uint64_t	gang_context_addr;
 };
 
+enum mes_misc_opcode {
+	MES_MISC_OP_WRITE_REG,
+	MES_MISC_OP_READ_REG,
+	MES_MISC_OP_WRM_REG_WAIT,
+	MES_MISC_OP_WRM_REG_WR_WAIT,
+};
+
+struct mes_misc_op_input {
+	enum mes_misc_opcode op;
+
+	union {
+		struct {
+			uint32_t                  reg_offset;
+			uint64_t                  buffer_addr;
+		} read_reg;
+
+		struct {
+			uint32_t                  reg_offset;
+			uint32_t                  reg_value;
+		} write_reg;
+
+		struct {
+			uint32_t                   ref;
+			uint32_t                   mask;
+			uint32_t                   reg0;
+			uint32_t                   reg1;
+		} wrm_reg;
+	};
+};
+
 struct amdgpu_mes_funcs {
 	int (*add_hw_queue)(struct amdgpu_mes *mes,
 			    struct mes_add_queue_input *input);
@@ -261,6 +295,9 @@ struct amdgpu_mes_funcs {
 
 	int (*resume_gang)(struct amdgpu_mes *mes,
 			   struct mes_resume_gang_input *input);
+
+	int (*misc_op)(struct amdgpu_mes *mes,
+		       struct mes_misc_op_input *input);
 };
 
 #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev))
@@ -293,6 +330,15 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,
 				  enum amdgpu_unmap_queues_action action,
 				  u64 gpu_addr, u64 seq);
 
+uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg);
+int amdgpu_mes_wreg(struct amdgpu_device *adev,
+		    uint32_t reg, uint32_t val);
+int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg,
+			uint32_t val, uint32_t mask);
+int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,
+				  uint32_t reg0, uint32_t reg1,
+				  uint32_t ref, uint32_t mask);
+
 int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,
 			int queue_type, int idx,
 			struct amdgpu_mes_ctx_data *ctx_data,
-- 
GitLab


From cff35798fad565b5f8bbf4ef84ac698270dcaf64 Mon Sep 17 00:00:00 2001
From: Jonathan Kim <jonathan.kim@amd.com>
Date: Sun, 26 Jun 2022 21:35:10 -0400
Subject: [PATCH 1423/1731] drm/amdkfd: fix cu mask for asics with wgps

GFX10 and up have work group processors (WGP) and WGP mode is the native
compile mode.

KFD and ROCr have no visibility into whether a dispatch is operating
in CU or WGP mode.

Enforce CU masking to be pairwise continguous in enablement and
round robin distribute CUs across the SEs in a pairwise manner to
assume WGP mode at all times.

Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c      | 12 +++++++-----
 .../drm/amd/amdkfd/kfd_process_queue_manager.c    | 15 +++++++++++++++
 2 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
index 49a283be6b574..623ccd227b7de 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
@@ -100,7 +100,9 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
 {
 	struct kfd_cu_info cu_info;
 	uint32_t cu_per_sh[KFD_MAX_NUM_SE][KFD_MAX_NUM_SH_PER_SE] = {0};
-	int i, se, sh, cu, cu_bitmap_sh_mul;
+	bool wgp_mode_req = KFD_GC_VERSION(mm->dev) >= IP_VERSION(10, 0, 0);
+	uint32_t en_mask = wgp_mode_req ? 0x3 : 0x1;
+	int i, se, sh, cu, cu_bitmap_sh_mul, inc = wgp_mode_req ? 2 : 1;
 
 	amdgpu_amdkfd_get_cu_info(mm->dev->adev, &cu_info);
 
@@ -167,13 +169,13 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
 		se_mask[i] = 0;
 
 	i = 0;
-	for (cu = 0; cu < 16; cu++) {
+	for (cu = 0; cu < 16; cu += inc) {
 		for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++) {
 			for (se = 0; se < cu_info.num_shader_engines; se++) {
 				if (cu_per_sh[se][sh] > cu) {
-					if (cu_mask[i / 32] & (1 << (i % 32)))
-						se_mask[se] |= 1 << (cu + sh * 16);
-					i++;
+					if (cu_mask[i / 32] & (en_mask << (i % 32)))
+						se_mask[se] |= en_mask << (cu + sh * 16);
+					i += inc;
 					if (i == cu_mask_count)
 						return;
 				}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index c9c205df4a147..6e3e7f54381b3 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -498,6 +498,21 @@ int pqm_update_mqd(struct process_queue_manager *pqm,
 		return -EFAULT;
 	}
 
+	/* ASICs that have WGPs must enforce pairwise enabled mask checks. */
+	if (minfo && minfo->update_flag == UPDATE_FLAG_CU_MASK && minfo->cu_mask.ptr &&
+			KFD_GC_VERSION(pqn->q->device) >= IP_VERSION(10, 0, 0)) {
+		int i;
+
+		for (i = 0; i < minfo->cu_mask.count; i += 2) {
+			uint32_t cu_pair = (minfo->cu_mask.ptr[i / 32] >> (i % 32)) & 0x3;
+
+			if (cu_pair && cu_pair != 0x3) {
+				pr_debug("CUs must be adjacent pairwise enabled.\n");
+				return -EINVAL;
+			}
+		}
+	}
+
 	retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm,
 							pqn->q, minfo);
 	if (retval != 0)
-- 
GitLab


From 7d4705b33cb84bfbba04de153d4f5e83041ac393 Mon Sep 17 00:00:00 2001
From: Jack Xiao <Jack.Xiao@amd.com>
Date: Thu, 16 Jun 2022 21:49:29 +0800
Subject: [PATCH 1424/1731] drm/amdgpu/mes11: add mes11 misc op

Add misc op commands in mes11.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 53 ++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 89b99dc827a6a..72d6017964c8a 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -274,6 +274,58 @@ static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes)
 			&mes_status_pkt, sizeof(mes_status_pkt));
 }
 
+static int mes_v11_0_misc_op(struct amdgpu_mes *mes,
+			     struct mes_misc_op_input *input)
+{
+	union MESAPI__MISC misc_pkt;
+
+	memset(&misc_pkt, 0, sizeof(misc_pkt));
+
+	misc_pkt.header.type = MES_API_TYPE_SCHEDULER;
+	misc_pkt.header.opcode = MES_SCH_API_MISC;
+	misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
+
+	switch (input->op) {
+	case MES_MISC_OP_READ_REG:
+		misc_pkt.opcode = MESAPI_MISC__READ_REG;
+		misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;
+		misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr;
+		break;
+	case MES_MISC_OP_WRITE_REG:
+		misc_pkt.opcode = MESAPI_MISC__WRITE_REG;
+		misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;
+		misc_pkt.write_reg.reg_value = input->write_reg.reg_value;
+		break;
+	case MES_MISC_OP_WRM_REG_WAIT:
+		misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
+		misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;
+		misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
+		misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
+		misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
+		misc_pkt.wait_reg_mem.reg_offset2 = 0;
+		break;
+	case MES_MISC_OP_WRM_REG_WR_WAIT:
+		misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
+		misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;
+		misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
+		misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
+		misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
+		misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;
+		break;
+	default:
+		DRM_ERROR("unsupported misc op (%d) \n", input->op);
+		return -EINVAL;
+	}
+
+	misc_pkt.api_status.api_completion_fence_addr =
+		mes->ring.fence_drv.gpu_addr;
+	misc_pkt.api_status.api_completion_fence_value =
+		++mes->ring.fence_drv.sync_seq;
+
+	return mes_v11_0_submit_pkt_and_poll_completion(mes,
+			&misc_pkt, sizeof(misc_pkt));
+}
+
 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
 {
 	int i;
@@ -336,6 +388,7 @@ static const struct amdgpu_mes_funcs mes_v11_0_funcs = {
 	.unmap_legacy_queue = mes_v11_0_unmap_legacy_queue,
 	.suspend_gang = mes_v11_0_suspend_gang,
 	.resume_gang = mes_v11_0_resume_gang,
+	.misc_op = mes_v11_0_misc_op,
 };
 
 static int mes_v11_0_init_microcode(struct amdgpu_device *adev,
-- 
GitLab


From adc0e6ab0df390907228abb76c6bf82382089af1 Mon Sep 17 00:00:00 2001
From: Jack Xiao <Jack.Xiao@amd.com>
Date: Thu, 16 Jun 2022 21:23:01 +0800
Subject: [PATCH 1425/1731] drm/amdgpu/mes: add mes register access interface

Add mes register access routines:
1. read register
2. write register
3. wait register
4. write and wait register

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 132 +++++++++++++++++++++++-
 1 file changed, 131 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 0c9cb493a85c3..bffde4aa6fe7d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -189,15 +189,29 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
 
 	r = amdgpu_device_wb_get(adev, &adev->mes.query_status_fence_offs);
 	if (r) {
+		amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
 		dev_err(adev->dev,
 			"(%d) query_status_fence_offs wb alloc failed\n", r);
-		return r;
+		goto error_ids;
 	}
 	adev->mes.query_status_fence_gpu_addr =
 		adev->wb.gpu_addr + (adev->mes.query_status_fence_offs * 4);
 	adev->mes.query_status_fence_ptr =
 		(uint64_t *)&adev->wb.wb[adev->mes.query_status_fence_offs];
 
+	r = amdgpu_device_wb_get(adev, &adev->mes.read_val_offs);
+	if (r) {
+		amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
+		amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
+		dev_err(adev->dev,
+			"(%d) read_val_offs alloc failed\n", r);
+		goto error_ids;
+	}
+	adev->mes.read_val_gpu_addr =
+		adev->wb.gpu_addr + (adev->mes.read_val_offs * 4);
+	adev->mes.read_val_ptr =
+		(uint32_t *)&adev->wb.wb[adev->mes.read_val_offs];
+
 	r = amdgpu_mes_doorbell_init(adev);
 	if (r)
 		goto error;
@@ -206,6 +220,8 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
 
 error:
 	amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
+	amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
+	amdgpu_device_wb_free(adev, adev->mes.read_val_offs);
 error_ids:
 	idr_destroy(&adev->mes.pasid_idr);
 	idr_destroy(&adev->mes.gang_id_idr);
@@ -218,6 +234,8 @@ error_ids:
 void amdgpu_mes_fini(struct amdgpu_device *adev)
 {
 	amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
+	amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
+	amdgpu_device_wb_free(adev, adev->mes.read_val_offs);
 
 	idr_destroy(&adev->mes.pasid_idr);
 	idr_destroy(&adev->mes.gang_id_idr);
@@ -794,6 +812,118 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,
 	return r;
 }
 
+uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg)
+{
+	struct mes_misc_op_input op_input;
+	int r, val = 0;
+
+	amdgpu_mes_lock(&adev->mes);
+
+	op_input.op = MES_MISC_OP_READ_REG;
+	op_input.read_reg.reg_offset = reg;
+	op_input.read_reg.buffer_addr = adev->mes.read_val_gpu_addr;
+
+	if (!adev->mes.funcs->misc_op) {
+		DRM_ERROR("mes rreg is not supported!\n");
+		goto error;
+	}
+
+	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
+	if (r)
+		DRM_ERROR("failed to read reg (0x%x)\n", reg);
+	else
+		val = *(adev->mes.read_val_ptr);
+
+error:
+	amdgpu_mes_unlock(&adev->mes);
+	return val;
+}
+
+int amdgpu_mes_wreg(struct amdgpu_device *adev,
+		    uint32_t reg, uint32_t val)
+{
+	struct mes_misc_op_input op_input;
+	int r;
+
+	amdgpu_mes_lock(&adev->mes);
+
+	op_input.op = MES_MISC_OP_WRITE_REG;
+	op_input.write_reg.reg_offset = reg;
+	op_input.write_reg.reg_value = val;
+
+	if (!adev->mes.funcs->misc_op) {
+		DRM_ERROR("mes wreg is not supported!\n");
+		r = -EINVAL;
+		goto error;
+	}
+
+	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
+	if (r)
+		DRM_ERROR("failed to write reg (0x%x)\n", reg);
+
+error:
+	amdgpu_mes_unlock(&adev->mes);
+	return r;
+}
+
+int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,
+				  uint32_t reg0, uint32_t reg1,
+				  uint32_t ref, uint32_t mask)
+{
+	struct mes_misc_op_input op_input;
+	int r;
+
+	amdgpu_mes_lock(&adev->mes);
+
+	op_input.op = MES_MISC_OP_WRM_REG_WR_WAIT;
+	op_input.wrm_reg.reg0 = reg0;
+	op_input.wrm_reg.reg1 = reg1;
+	op_input.wrm_reg.ref = ref;
+	op_input.wrm_reg.mask = mask;
+
+	if (!adev->mes.funcs->misc_op) {
+		DRM_ERROR("mes reg_write_reg_wait is not supported!\n");
+		r = -EINVAL;
+		goto error;
+	}
+
+	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
+	if (r)
+		DRM_ERROR("failed to reg_write_reg_wait\n");
+
+error:
+	amdgpu_mes_unlock(&adev->mes);
+	return r;
+}
+
+int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg,
+			uint32_t val, uint32_t mask)
+{
+	struct mes_misc_op_input op_input;
+	int r;
+
+	amdgpu_mes_lock(&adev->mes);
+
+	op_input.op = MES_MISC_OP_WRM_REG_WAIT;
+	op_input.wrm_reg.reg0 = reg;
+	op_input.wrm_reg.ref = val;
+	op_input.wrm_reg.mask = mask;
+
+	if (!adev->mes.funcs->misc_op) {
+		DRM_ERROR("mes reg wait is not supported!\n");
+		r = -EINVAL;
+		goto error;
+	}
+
+	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
+	if (r)
+		DRM_ERROR("failed to reg_write_reg_wait\n");
+
+error:
+	amdgpu_mes_unlock(&adev->mes);
+	return r;
+}
+
 static void
 amdgpu_mes_ring_to_queue_props(struct amdgpu_device *adev,
 			       struct amdgpu_ring *ring,
-- 
GitLab


From cf6067290034b9ebbe4c39733b1a4acc94876c26 Mon Sep 17 00:00:00 2001
From: Jack Xiao <Jack.Xiao@amd.com>
Date: Thu, 16 Jun 2022 21:34:24 +0800
Subject: [PATCH 1426/1731] drm/amdgpu: enable mes to access registers v2

Enable mes to access registers.

v2: squash mes sched ring enablement flag

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c  | 8 ++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 6 ++++++
 drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c   | 2 +-
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c   | 1 +
 4 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index b697353e5a7ae..222d3d7ea0767 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -699,6 +699,9 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
 	if (amdgpu_device_skip_hw_access(adev))
 		return 0;
 
+	if (adev->mes.ring.sched.ready)
+		return amdgpu_mes_rreg(adev, reg);
+
 	BUG_ON(!ring->funcs->emit_rreg);
 
 	spin_lock_irqsave(&kiq->ring_lock, flags);
@@ -766,6 +769,11 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 	if (amdgpu_device_skip_hw_access(adev))
 		return;
 
+	if (adev->mes.ring.sched.ready) {
+		amdgpu_mes_wreg(adev, reg, v);
+		return;
+	}
+
 	spin_lock_irqsave(&kiq->ring_lock, flags);
 	amdgpu_ring_alloc(ring, 32);
 	amdgpu_ring_emit_wreg(ring, reg, v);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index a8ecf04389b32..9be57389301b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -76,6 +76,12 @@ void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
 	unsigned long flags;
 	uint32_t seq;
 
+	if (adev->mes.ring.sched.ready) {
+		amdgpu_mes_reg_write_reg_wait(adev, reg0, reg1,
+					      ref, mask);
+		return;
+	}
+
 	spin_lock_irqsave(&kiq->ring_lock, flags);
 	amdgpu_ring_alloc(ring, 32);
 	amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index e098b69d63212..d4e9c6790c2c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -274,7 +274,7 @@ static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 	/* For SRIOV run time, driver shouldn't access the register through MMIO
 	 * Directly use kiq to do the vm invalidation instead
 	 */
-	if (adev->gfx.kiq.ring.sched.ready && !adev->enable_mes &&
+	if ((adev->gfx.kiq.ring.sched.ready || adev->mes.ring.sched.ready) &&
 	    (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
 		struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
 		const unsigned eng = 17;
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 72d6017964c8a..5bdc2babb070b 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -1193,6 +1193,7 @@ static int mes_v11_0_hw_init(void *handle)
 	 * with MES enabled.
 	 */
 	adev->gfx.kiq.ring.sched.ready = false;
+	adev->mes.ring.sched.ready = true;
 
 	return 0;
 
-- 
GitLab


From 395ece6f14124c2245e4b7fe74932514f999faa1 Mon Sep 17 00:00:00 2001
From: Jack Xiao <Jack.Xiao@amd.com>
Date: Tue, 28 Jun 2022 12:28:43 +0800
Subject: [PATCH 1427/1731] Revert "drm/amdgpu/gmc11: avoid cpu accessing
 registers to flush VM"

This reverts commit 8748de873fedf4d55bdd99bbb738ee7ddf329792
since drv enabled mes to access registers.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 51 +-------------------------
 1 file changed, 1 insertion(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index d4e9c6790c2c7..edbdc0b934ea4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -259,12 +259,6 @@ static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 					uint32_t vmhub, uint32_t flush_type)
 {
-	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
-	struct dma_fence *fence;
-	struct amdgpu_job *job;
-
-	int r;
-
 	if ((vmhub == AMDGPU_GFXHUB_0) && !adev->gfx.is_poweron)
 		return;
 
@@ -288,51 +282,8 @@ static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 	}
 
 	mutex_lock(&adev->mman.gtt_window_lock);
-
-	if (vmhub == AMDGPU_MMHUB_0) {
-		gmc_v11_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
-		mutex_unlock(&adev->mman.gtt_window_lock);
-		return;
-	}
-
-	BUG_ON(vmhub != AMDGPU_GFXHUB_0);
-
-	if (!adev->mman.buffer_funcs_enabled ||
-	    !adev->ib_pool_ready ||
-	    amdgpu_in_reset(adev) ||
-	    ring->sched.ready == false) {
-		gmc_v11_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
-		mutex_unlock(&adev->mman.gtt_window_lock);
-		return;
-	}
-
-	r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
-				     &job);
-	if (r)
-		goto error_alloc;
-
-	job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
-	job->vm_needs_flush = true;
-	job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
-	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
-	r = amdgpu_job_submit(job, &adev->mman.entity,
-			      AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
-	if (r)
-		goto error_submit;
-
-	mutex_unlock(&adev->mman.gtt_window_lock);
-
-	dma_fence_wait(fence, false);
-	dma_fence_put(fence);
-
-	return;
-
-error_submit:
-	amdgpu_job_free(job);
-
-error_alloc:
+	gmc_v11_0_flush_vm_hub(adev, vmid, vmhub, 0);
 	mutex_unlock(&adev->mman.gtt_window_lock);
-	DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
 	return;
 }
 
-- 
GitLab


From d7cfea332cca483ccd3970ed4de73ed892643e51 Mon Sep 17 00:00:00 2001
From: Philip Yang <Philip.Yang@amd.com>
Date: Thu, 20 Jan 2022 15:06:30 -0500
Subject: [PATCH 1428/1731] drm/amdkfd: Add KFD SMI event IDs and triggers

Define new system management interface event IDs for migration, GPU
recoverable page fault, user queues eviction, restore and unmap from
GPU events and corresponding event triggers, those will be implemented
in the following patches.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 include/uapi/linux/kfd_ioctl.h | 37 ++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index 231eb010b823e..280edda46faf7 100644
--- a/include/uapi/linux/kfd_ioctl.h
+++ b/include/uapi/linux/kfd_ioctl.h
@@ -470,6 +470,43 @@ enum kfd_smi_event {
 	KFD_SMI_EVENT_THERMAL_THROTTLE = 2,
 	KFD_SMI_EVENT_GPU_PRE_RESET = 3,
 	KFD_SMI_EVENT_GPU_POST_RESET = 4,
+	KFD_SMI_EVENT_MIGRATE_START = 5,
+	KFD_SMI_EVENT_MIGRATE_END = 6,
+	KFD_SMI_EVENT_PAGE_FAULT_START = 7,
+	KFD_SMI_EVENT_PAGE_FAULT_END = 8,
+	KFD_SMI_EVENT_QUEUE_EVICTION = 9,
+	KFD_SMI_EVENT_QUEUE_RESTORE = 10,
+	KFD_SMI_EVENT_UNMAP_FROM_GPU = 11,
+
+	/*
+	 * max event number, as a flag bit to get events from all processes,
+	 * this requires super user permission, otherwise will not be able to
+	 * receive event from any process. Without this flag to receive events
+	 * from same process.
+	 */
+	KFD_SMI_EVENT_ALL_PROCESS = 64
+};
+
+enum KFD_MIGRATE_TRIGGERS {
+	KFD_MIGRATE_TRIGGER_PREFETCH,
+	KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU,
+	KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU,
+	KFD_MIGRATE_TRIGGER_TTM_EVICTION
+};
+
+enum KFD_QUEUE_EVICTION_TRIGGERS {
+	KFD_QUEUE_EVICTION_TRIGGER_SVM,
+	KFD_QUEUE_EVICTION_TRIGGER_USERPTR,
+	KFD_QUEUE_EVICTION_TRIGGER_TTM,
+	KFD_QUEUE_EVICTION_TRIGGER_SUSPEND,
+	KFD_QUEUE_EVICTION_CRIU_CHECKPOINT,
+	KFD_QUEUE_EVICTION_CRIU_RESTORE
+};
+
+enum KFD_SVM_UNMAP_TRIGGERS {
+	KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY,
+	KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY_MIGRATE,
+	KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU
 };
 
 #define KFD_SMI_EVENT_MASK_FROM_INDEX(i) (1ULL << ((i) - 1))
-- 
GitLab


From 163a5a58437062ce4dbef2aab6de4d784043bcf5 Mon Sep 17 00:00:00 2001
From: Philip Yang <Philip.Yang@amd.com>
Date: Thu, 13 Jan 2022 18:59:02 -0500
Subject: [PATCH 1429/1731] drm/amdkfd: Enable per process SMI event

Process receive event from same process by default. Add a flag to be
able to receive event from all processes, this requires super user
permission.

Event using pid 0 to send the event to all processes, to keep the
default behavior of existing SMI events.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 37 +++++++++++++++------
 1 file changed, 26 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
index f2e1d506ba211..55ed026435e27 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
@@ -38,6 +38,8 @@ struct kfd_smi_client {
 	uint64_t events;
 	struct kfd_dev *dev;
 	spinlock_t lock;
+	pid_t pid;
+	bool suser;
 };
 
 #define MAX_KFIFO_SIZE	1024
@@ -151,16 +153,27 @@ static int kfd_smi_ev_release(struct inode *inode, struct file *filep)
 	return 0;
 }
 
-static void add_event_to_kfifo(struct kfd_dev *dev, unsigned int smi_event,
-			      char *event_msg, int len)
+static bool kfd_smi_ev_enabled(pid_t pid, struct kfd_smi_client *client,
+			       unsigned int event)
+{
+	uint64_t all = KFD_SMI_EVENT_MASK_FROM_INDEX(KFD_SMI_EVENT_ALL_PROCESS);
+	uint64_t events = READ_ONCE(client->events);
+
+	if (pid && client->pid != pid && !(client->suser && (events & all)))
+		return false;
+
+	return events & KFD_SMI_EVENT_MASK_FROM_INDEX(event);
+}
+
+static void add_event_to_kfifo(pid_t pid, struct kfd_dev *dev,
+			       unsigned int smi_event, char *event_msg, int len)
 {
 	struct kfd_smi_client *client;
 
 	rcu_read_lock();
 
 	list_for_each_entry_rcu(client, &dev->smi_clients, list) {
-		if (!(READ_ONCE(client->events) &
-				KFD_SMI_EVENT_MASK_FROM_INDEX(smi_event)))
+		if (!kfd_smi_ev_enabled(pid, client, smi_event))
 			continue;
 		spin_lock(&client->lock);
 		if (kfifo_avail(&client->fifo) >= len) {
@@ -176,9 +189,9 @@ static void add_event_to_kfifo(struct kfd_dev *dev, unsigned int smi_event,
 	rcu_read_unlock();
 }
 
-__printf(3, 4)
-static void kfd_smi_event_add(struct kfd_dev *dev, unsigned int event,
-			      char *fmt, ...)
+__printf(4, 5)
+static void kfd_smi_event_add(pid_t pid, struct kfd_dev *dev,
+			      unsigned int event, char *fmt, ...)
 {
 	char fifo_in[KFD_SMI_EVENT_MSG_SIZE];
 	int len;
@@ -193,7 +206,7 @@ static void kfd_smi_event_add(struct kfd_dev *dev, unsigned int event,
 	len += vsnprintf(fifo_in + len, sizeof(fifo_in) - len, fmt, args);
 	va_end(args);
 
-	add_event_to_kfifo(dev, event, fifo_in, len);
+	add_event_to_kfifo(pid, dev, event, fifo_in, len);
 }
 
 void kfd_smi_event_update_gpu_reset(struct kfd_dev *dev, bool post_reset)
@@ -206,13 +219,13 @@ void kfd_smi_event_update_gpu_reset(struct kfd_dev *dev, bool post_reset)
 		event = KFD_SMI_EVENT_GPU_PRE_RESET;
 		++(dev->reset_seq_num);
 	}
-	kfd_smi_event_add(dev, event, "%x\n", dev->reset_seq_num);
+	kfd_smi_event_add(0, dev, event, "%x\n", dev->reset_seq_num);
 }
 
 void kfd_smi_event_update_thermal_throttling(struct kfd_dev *dev,
 					     uint64_t throttle_bitmask)
 {
-	kfd_smi_event_add(dev, KFD_SMI_EVENT_THERMAL_THROTTLE, "%llx:%llx\n",
+	kfd_smi_event_add(0, dev, KFD_SMI_EVENT_THERMAL_THROTTLE, "%llx:%llx\n",
 			  throttle_bitmask,
 			  amdgpu_dpm_get_thermal_throttling_counter(dev->adev));
 }
@@ -227,7 +240,7 @@ void kfd_smi_event_update_vmfault(struct kfd_dev *dev, uint16_t pasid)
 	if (!task_info.pid)
 		return;
 
-	kfd_smi_event_add(dev, KFD_SMI_EVENT_VMFAULT, "%x:%s\n",
+	kfd_smi_event_add(0, dev, KFD_SMI_EVENT_VMFAULT, "%x:%s\n",
 			  task_info.pid, task_info.task_name);
 }
 
@@ -251,6 +264,8 @@ int kfd_smi_event_open(struct kfd_dev *dev, uint32_t *fd)
 	spin_lock_init(&client->lock);
 	client->events = 0;
 	client->dev = dev;
+	client->pid = current->tgid;
+	client->suser = capable(CAP_SYS_ADMIN);
 
 	spin_lock(&dev->smi_lock);
 	list_add_rcu(&client->list, &dev->smi_clients);
-- 
GitLab


From e0f1e65b836c42741288a367eab565167a408b59 Mon Sep 17 00:00:00 2001
From: Philip Yang <Philip.Yang@amd.com>
Date: Thu, 13 Jan 2022 19:22:54 -0500
Subject: [PATCH 1430/1731] drm/amdkfd: Add GPU recoverable fault SMI event

Use ktime_get_boottime_ns() as timestamp to correlate with other
APIs. Output timestamp when GPU recoverable fault starts and ends to
recover the fault, if migration happened or only GPU page table is
updated to recover, fault address, if read or write fault.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 17 +++++++++++++++++
 drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h |  6 +++++-
 drivers/gpu/drm/amd/amdkfd/kfd_svm.c        | 19 ++++++++++++++-----
 drivers/gpu/drm/amd/amdkfd/kfd_svm.h        |  2 +-
 4 files changed, 37 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
index 55ed026435e27..b7e68283925f6 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
@@ -244,6 +244,23 @@ void kfd_smi_event_update_vmfault(struct kfd_dev *dev, uint16_t pasid)
 			  task_info.pid, task_info.task_name);
 }
 
+void kfd_smi_event_page_fault_start(struct kfd_dev *dev, pid_t pid,
+				    unsigned long address, bool write_fault,
+				    ktime_t ts)
+{
+	kfd_smi_event_add(pid, dev, KFD_SMI_EVENT_PAGE_FAULT_START,
+			  "%lld -%d @%lx(%x) %c\n", ktime_to_ns(ts), pid,
+			  address, dev->id, write_fault ? 'W' : 'R');
+}
+
+void kfd_smi_event_page_fault_end(struct kfd_dev *dev, pid_t pid,
+				  unsigned long address, bool migration)
+{
+	kfd_smi_event_add(pid, dev, KFD_SMI_EVENT_PAGE_FAULT_END,
+			  "%lld -%d @%lx(%x) %c\n", ktime_get_boottime_ns(),
+			  pid, address, dev->id, migration ? 'M' : 'U');
+}
+
 int kfd_smi_event_open(struct kfd_dev *dev, uint32_t *fd)
 {
 	struct kfd_smi_client *client;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h
index dfe101c211666..7903718cd9eb8 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h
@@ -29,5 +29,9 @@ void kfd_smi_event_update_vmfault(struct kfd_dev *dev, uint16_t pasid);
 void kfd_smi_event_update_thermal_throttling(struct kfd_dev *dev,
 					     uint64_t throttle_bitmask);
 void kfd_smi_event_update_gpu_reset(struct kfd_dev *dev, bool post_reset);
-
+void kfd_smi_event_page_fault_start(struct kfd_dev *dev, pid_t pid,
+				    unsigned long address, bool write_fault,
+				    ktime_t ts);
+void kfd_smi_event_page_fault_end(struct kfd_dev *dev, pid_t pid,
+				  unsigned long address, bool migration);
 #endif
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 7b332246eda3e..a3c7dd411b772 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -32,6 +32,7 @@
 #include "kfd_priv.h"
 #include "kfd_svm.h"
 #include "kfd_migrate.h"
+#include "kfd_smi_events.h"
 
 #ifdef dev_fmt
 #undef dev_fmt
@@ -43,7 +44,7 @@
 /* Long enough to ensure no retry fault comes after svm range is restored and
  * page table is updated.
  */
-#define AMDGPU_SVM_RANGE_RETRY_FAULT_PENDING	2000
+#define AMDGPU_SVM_RANGE_RETRY_FAULT_PENDING	(2UL * NSEC_PER_MSEC)
 
 struct criu_svm_metadata {
 	struct list_head list;
@@ -1617,7 +1618,7 @@ unreserve_out:
 	svm_range_unreserve_bos(&ctx);
 
 	if (!r)
-		prange->validate_timestamp = ktime_to_us(ktime_get());
+		prange->validate_timestamp = ktime_get_boottime();
 
 	return r;
 }
@@ -2694,11 +2695,12 @@ svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid,
 	struct svm_range_list *svms;
 	struct svm_range *prange;
 	struct kfd_process *p;
-	uint64_t timestamp;
+	ktime_t timestamp = ktime_get_boottime();
 	int32_t best_loc;
 	int32_t gpuidx = MAX_GPU_INSTANCE;
 	bool write_locked = false;
 	struct vm_area_struct *vma;
+	bool migration = false;
 	int r = 0;
 
 	if (!KFD_IS_SVM_API_SUPPORTED(adev->kfd.dev)) {
@@ -2775,9 +2777,9 @@ retry_write_locked:
 		goto out_unlock_range;
 	}
 
-	timestamp = ktime_to_us(ktime_get()) - prange->validate_timestamp;
 	/* skip duplicate vm fault on different pages of same range */
-	if (timestamp < AMDGPU_SVM_RANGE_RETRY_FAULT_PENDING) {
+	if (ktime_before(timestamp, ktime_add_ns(prange->validate_timestamp,
+				AMDGPU_SVM_RANGE_RETRY_FAULT_PENDING))) {
 		pr_debug("svms 0x%p [0x%lx %lx] already restored\n",
 			 svms, prange->start, prange->last);
 		r = 0;
@@ -2813,7 +2815,11 @@ retry_write_locked:
 		 svms, prange->start, prange->last, best_loc,
 		 prange->actual_loc);
 
+	kfd_smi_event_page_fault_start(adev->kfd.dev, p->lead_thread->pid, addr,
+				       write_fault, timestamp);
+
 	if (prange->actual_loc != best_loc) {
+		migration = true;
 		if (best_loc) {
 			r = svm_migrate_to_vram(prange, best_loc, mm);
 			if (r) {
@@ -2842,6 +2848,9 @@ retry_write_locked:
 		pr_debug("failed %d to map svms 0x%p [0x%lx 0x%lx] to gpus\n",
 			 r, svms, prange->start, prange->last);
 
+	kfd_smi_event_page_fault_end(adev->kfd.dev, p->lead_thread->pid, addr,
+				     migration);
+
 out_unlock_range:
 	mutex_unlock(&prange->migrate_mutex);
 out_unlock_svms:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h
index 2d54147b4ddaa..eab7f6d3b13ca 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h
@@ -125,7 +125,7 @@ struct svm_range {
 	uint32_t			actual_loc;
 	uint8_t				granularity;
 	atomic_t			invalid;
-	uint64_t			validate_timestamp;
+	ktime_t				validate_timestamp;
 	struct mmu_interval_notifier	notifier;
 	struct svm_work_list_item	work_item;
 	struct list_head		deferred_list;
-- 
GitLab


From acac270d09828edda2d530d255ee75ceb87583ec Mon Sep 17 00:00:00 2001
From: Philip Yang <Philip.Yang@amd.com>
Date: Thu, 13 Jan 2022 19:28:13 -0500
Subject: [PATCH 1431/1731] drm/amdkfd: Add migration SMI event

For migration start and end event, output timestamp when migration
starts, ends, svm range address and size, GPU id of migration source and
destination and svm range attributes,

Migration trigger could be prefetch, CPU or GPU page fault and TTM
eviction.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_migrate.c    | 53 ++++++++++++++++-----
 drivers/gpu/drm/amd/amdkfd/kfd_migrate.h    |  5 +-
 drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 22 +++++++++
 drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h |  8 ++++
 drivers/gpu/drm/amd/amdkfd/kfd_svm.c        | 16 ++++---
 5 files changed, 83 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index e44376c2ecdcd..eecb262270e21 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -33,6 +33,7 @@
 #include "kfd_priv.h"
 #include "kfd_svm.h"
 #include "kfd_migrate.h"
+#include "kfd_smi_events.h"
 
 #ifdef dev_fmt
 #undef dev_fmt
@@ -402,8 +403,9 @@ out:
 static long
 svm_migrate_vma_to_vram(struct amdgpu_device *adev, struct svm_range *prange,
 			struct vm_area_struct *vma, uint64_t start,
-			uint64_t end)
+			uint64_t end, uint32_t trigger)
 {
+	struct kfd_process *p = container_of(prange->svms, struct kfd_process, svms);
 	uint64_t npages = (end - start) >> PAGE_SHIFT;
 	struct kfd_process_device *pdd;
 	struct dma_fence *mfence = NULL;
@@ -430,6 +432,11 @@ svm_migrate_vma_to_vram(struct amdgpu_device *adev, struct svm_range *prange,
 	migrate.dst = migrate.src + npages;
 	scratch = (dma_addr_t *)(migrate.dst + npages);
 
+	kfd_smi_event_migration_start(adev->kfd.dev, p->lead_thread->pid,
+				      start >> PAGE_SHIFT, end >> PAGE_SHIFT,
+				      0, adev->kfd.dev->id, prange->prefetch_loc,
+				      prange->preferred_loc, trigger);
+
 	r = migrate_vma_setup(&migrate);
 	if (r) {
 		dev_err(adev->dev, "%s: vma setup fail %d range [0x%lx 0x%lx]\n",
@@ -458,6 +465,10 @@ svm_migrate_vma_to_vram(struct amdgpu_device *adev, struct svm_range *prange,
 	svm_migrate_copy_done(adev, mfence);
 	migrate_vma_finalize(&migrate);
 
+	kfd_smi_event_migration_end(adev->kfd.dev, p->lead_thread->pid,
+				    start >> PAGE_SHIFT, end >> PAGE_SHIFT,
+				    0, adev->kfd.dev->id, trigger);
+
 	svm_range_dma_unmap(adev->dev, scratch, 0, npages);
 	svm_range_free_dma_mappings(prange);
 
@@ -479,6 +490,7 @@ out:
  * @prange: range structure
  * @best_loc: the device to migrate to
  * @mm: the process mm structure
+ * @trigger: reason of migration
  *
  * Context: Process context, caller hold mmap read lock, svms lock, prange lock
  *
@@ -487,7 +499,7 @@ out:
  */
 static int
 svm_migrate_ram_to_vram(struct svm_range *prange, uint32_t best_loc,
-			struct mm_struct *mm)
+			struct mm_struct *mm, uint32_t trigger)
 {
 	unsigned long addr, start, end;
 	struct vm_area_struct *vma;
@@ -524,7 +536,7 @@ svm_migrate_ram_to_vram(struct svm_range *prange, uint32_t best_loc,
 			break;
 
 		next = min(vma->vm_end, end);
-		r = svm_migrate_vma_to_vram(adev, prange, vma, addr, next);
+		r = svm_migrate_vma_to_vram(adev, prange, vma, addr, next, trigger);
 		if (r < 0) {
 			pr_debug("failed %ld to migrate\n", r);
 			break;
@@ -655,8 +667,10 @@ out_oom:
  */
 static long
 svm_migrate_vma_to_ram(struct amdgpu_device *adev, struct svm_range *prange,
-		       struct vm_area_struct *vma, uint64_t start, uint64_t end)
+		       struct vm_area_struct *vma, uint64_t start, uint64_t end,
+		       uint32_t trigger)
 {
+	struct kfd_process *p = container_of(prange->svms, struct kfd_process, svms);
 	uint64_t npages = (end - start) >> PAGE_SHIFT;
 	unsigned long upages = npages;
 	unsigned long cpages = 0;
@@ -685,6 +699,11 @@ svm_migrate_vma_to_ram(struct amdgpu_device *adev, struct svm_range *prange,
 	migrate.dst = migrate.src + npages;
 	scratch = (dma_addr_t *)(migrate.dst + npages);
 
+	kfd_smi_event_migration_start(adev->kfd.dev, p->lead_thread->pid,
+				      start >> PAGE_SHIFT, end >> PAGE_SHIFT,
+				      adev->kfd.dev->id, 0, prange->prefetch_loc,
+				      prange->preferred_loc, trigger);
+
 	r = migrate_vma_setup(&migrate);
 	if (r) {
 		dev_err(adev->dev, "%s: vma setup fail %d range [0x%lx 0x%lx]\n",
@@ -715,6 +734,11 @@ svm_migrate_vma_to_ram(struct amdgpu_device *adev, struct svm_range *prange,
 
 	svm_migrate_copy_done(adev, mfence);
 	migrate_vma_finalize(&migrate);
+
+	kfd_smi_event_migration_end(adev->kfd.dev, p->lead_thread->pid,
+				    start >> PAGE_SHIFT, end >> PAGE_SHIFT,
+				    adev->kfd.dev->id, 0, trigger);
+
 	svm_range_dma_unmap(adev->dev, scratch, 0, npages);
 
 out_free:
@@ -732,13 +756,15 @@ out:
  * svm_migrate_vram_to_ram - migrate svm range from device to system
  * @prange: range structure
  * @mm: process mm, use current->mm if NULL
+ * @trigger: reason of migration
  *
  * Context: Process context, caller hold mmap read lock, prange->migrate_mutex
  *
  * Return:
  * 0 - OK, otherwise error code
  */
-int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm)
+int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm,
+			    uint32_t trigger)
 {
 	struct amdgpu_device *adev;
 	struct vm_area_struct *vma;
@@ -779,7 +805,7 @@ int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm)
 		}
 
 		next = min(vma->vm_end, end);
-		r = svm_migrate_vma_to_ram(adev, prange, vma, addr, next);
+		r = svm_migrate_vma_to_ram(adev, prange, vma, addr, next, trigger);
 		if (r < 0) {
 			pr_debug("failed %ld to migrate prange %p\n", r, prange);
 			break;
@@ -802,6 +828,7 @@ int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm)
  * @prange: range structure
  * @best_loc: the device to migrate to
  * @mm: process mm, use current->mm if NULL
+ * @trigger: reason of migration
  *
  * Context: Process context, caller hold mmap read lock, svms lock, prange lock
  *
@@ -810,7 +837,7 @@ int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm)
  */
 static int
 svm_migrate_vram_to_vram(struct svm_range *prange, uint32_t best_loc,
-			 struct mm_struct *mm)
+			 struct mm_struct *mm, uint32_t trigger)
 {
 	int r, retries = 3;
 
@@ -822,7 +849,7 @@ svm_migrate_vram_to_vram(struct svm_range *prange, uint32_t best_loc,
 	pr_debug("from gpu 0x%x to gpu 0x%x\n", prange->actual_loc, best_loc);
 
 	do {
-		r = svm_migrate_vram_to_ram(prange, mm);
+		r = svm_migrate_vram_to_ram(prange, mm, trigger);
 		if (r)
 			return r;
 	} while (prange->actual_loc && --retries);
@@ -830,17 +857,17 @@ svm_migrate_vram_to_vram(struct svm_range *prange, uint32_t best_loc,
 	if (prange->actual_loc)
 		return -EDEADLK;
 
-	return svm_migrate_ram_to_vram(prange, best_loc, mm);
+	return svm_migrate_ram_to_vram(prange, best_loc, mm, trigger);
 }
 
 int
 svm_migrate_to_vram(struct svm_range *prange, uint32_t best_loc,
-		    struct mm_struct *mm)
+		    struct mm_struct *mm, uint32_t trigger)
 {
 	if  (!prange->actual_loc)
-		return svm_migrate_ram_to_vram(prange, best_loc, mm);
+		return svm_migrate_ram_to_vram(prange, best_loc, mm, trigger);
 	else
-		return svm_migrate_vram_to_vram(prange, best_loc, mm);
+		return svm_migrate_vram_to_vram(prange, best_loc, mm, trigger);
 
 }
 
@@ -909,7 +936,7 @@ static vm_fault_t svm_migrate_to_ram(struct vm_fault *vmf)
 		goto out_unlock_prange;
 	}
 
-	r = svm_migrate_vram_to_ram(prange, mm);
+	r = svm_migrate_vram_to_ram(prange, mm, KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU);
 	if (r)
 		pr_debug("failed %d migrate 0x%p [0x%lx 0x%lx] to ram\n", r,
 			 prange, prange->start, prange->last);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h
index 2f5b3394c9ed9..b3f0754b32faa 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h
@@ -41,8 +41,9 @@ enum MIGRATION_COPY_DIR {
 };
 
 int svm_migrate_to_vram(struct svm_range *prange,  uint32_t best_loc,
-			struct mm_struct *mm);
-int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm);
+			struct mm_struct *mm, uint32_t trigger);
+int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm,
+			    uint32_t trigger);
 unsigned long
 svm_migrate_addr_to_pfn(struct amdgpu_device *adev, unsigned long addr);
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
index b7e68283925f6..ec4d278c2a471 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
@@ -261,6 +261,28 @@ void kfd_smi_event_page_fault_end(struct kfd_dev *dev, pid_t pid,
 			  pid, address, dev->id, migration ? 'M' : 'U');
 }
 
+void kfd_smi_event_migration_start(struct kfd_dev *dev, pid_t pid,
+				   unsigned long start, unsigned long end,
+				   uint32_t from, uint32_t to,
+				   uint32_t prefetch_loc, uint32_t preferred_loc,
+				   uint32_t trigger)
+{
+	kfd_smi_event_add(pid, dev, KFD_SMI_EVENT_MIGRATE_START,
+			  "%lld -%d @%lx(%lx) %x->%x %x:%x %d\n",
+			  ktime_get_boottime_ns(), pid, start, end - start,
+			  from, to, prefetch_loc, preferred_loc, trigger);
+}
+
+void kfd_smi_event_migration_end(struct kfd_dev *dev, pid_t pid,
+				 unsigned long start, unsigned long end,
+				 uint32_t from, uint32_t to, uint32_t trigger)
+{
+	kfd_smi_event_add(pid, dev, KFD_SMI_EVENT_MIGRATE_END,
+			  "%lld -%d @%lx(%lx) %x->%x %d\n",
+			  ktime_get_boottime_ns(), pid, start, end - start,
+			  from, to, trigger);
+}
+
 int kfd_smi_event_open(struct kfd_dev *dev, uint32_t *fd)
 {
 	struct kfd_smi_client *client;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h
index 7903718cd9eb8..ec5d74a2fef44 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h
@@ -34,4 +34,12 @@ void kfd_smi_event_page_fault_start(struct kfd_dev *dev, pid_t pid,
 				    ktime_t ts);
 void kfd_smi_event_page_fault_end(struct kfd_dev *dev, pid_t pid,
 				  unsigned long address, bool migration);
+void kfd_smi_event_migration_start(struct kfd_dev *dev, pid_t pid,
+			     unsigned long start, unsigned long end,
+			     uint32_t from, uint32_t to,
+			     uint32_t prefetch_loc, uint32_t preferred_loc,
+			     uint32_t trigger);
+void kfd_smi_event_migration_end(struct kfd_dev *dev, pid_t pid,
+			     unsigned long start, unsigned long end,
+			     uint32_t from, uint32_t to, uint32_t trigger);
 #endif
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index a3c7dd411b772..e8ded7a02bcb1 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -2821,7 +2821,8 @@ retry_write_locked:
 	if (prange->actual_loc != best_loc) {
 		migration = true;
 		if (best_loc) {
-			r = svm_migrate_to_vram(prange, best_loc, mm);
+			r = svm_migrate_to_vram(prange, best_loc, mm,
+					KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU);
 			if (r) {
 				pr_debug("svm_migrate_to_vram failed (%d) at %llx, falling back to system memory\n",
 					 r, addr);
@@ -2829,12 +2830,14 @@ retry_write_locked:
 				 * VRAM failed
 				 */
 				if (prange->actual_loc)
-					r = svm_migrate_vram_to_ram(prange, mm);
+					r = svm_migrate_vram_to_ram(prange, mm,
+					   KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU);
 				else
 					r = 0;
 			}
 		} else {
-			r = svm_migrate_vram_to_ram(prange, mm);
+			r = svm_migrate_vram_to_ram(prange, mm,
+					KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU);
 		}
 		if (r) {
 			pr_debug("failed %d to migrate svms %p [0x%lx 0x%lx]\n",
@@ -3157,12 +3160,12 @@ svm_range_trigger_migration(struct mm_struct *mm, struct svm_range *prange,
 		return 0;
 
 	if (!best_loc) {
-		r = svm_migrate_vram_to_ram(prange, mm);
+		r = svm_migrate_vram_to_ram(prange, mm, KFD_MIGRATE_TRIGGER_PREFETCH);
 		*migrated = !r;
 		return r;
 	}
 
-	r = svm_migrate_to_vram(prange, best_loc, mm);
+	r = svm_migrate_to_vram(prange, best_loc, mm, KFD_MIGRATE_TRIGGER_PREFETCH);
 	*migrated = !r;
 
 	return r;
@@ -3220,7 +3223,8 @@ static void svm_range_evict_svm_bo_worker(struct work_struct *work)
 		mutex_lock(&prange->migrate_mutex);
 		do {
 			r = svm_migrate_vram_to_ram(prange,
-						svm_bo->eviction_fence->mm);
+						svm_bo->eviction_fence->mm,
+						KFD_MIGRATE_TRIGGER_TTM_EVICTION);
 		} while (!r && prange->actual_loc && --retries);
 
 		if (!r && prange->actual_loc)
-- 
GitLab


From c7f21978fa6aafaf7ad37155c7d3a217dc3d16b0 Mon Sep 17 00:00:00 2001
From: Philip Yang <Philip.Yang@amd.com>
Date: Thu, 13 Jan 2022 21:24:20 -0500
Subject: [PATCH 1432/1731] drm/amdkfd: Add user queue eviction restore SMI
 event

Output user queue eviction and restore event. User queue eviction may be
triggered by svm or userptr MMU notifier, TTM eviction, device suspend
and CRIU checkpoint and restore.

User queue restore may be rescheduled if eviction happens again while
restore.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h    |  2 +-
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 12 ++++---
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c      |  4 +--
 drivers/gpu/drm/amd/amdkfd/kfd_device.c       |  4 +--
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h         |  2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_process.c      | 15 ++++++--
 drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c   | 35 +++++++++++++++++++
 drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h   |  4 +++
 drivers/gpu/drm/amd/amdkfd/kfd_svm.c          |  6 ++--
 9 files changed, 69 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index b25b41f502138..73bf8b5f2aa9a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -336,7 +336,7 @@ void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
 }
 #endif
 /* KGD2KFD callbacks */
-int kgd2kfd_quiesce_mm(struct mm_struct *mm);
+int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger);
 int kgd2kfd_resume_mm(struct mm_struct *mm);
 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
 						struct dma_fence *fence);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 0036c9e405afd..2fcc6e079769e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -32,6 +32,7 @@
 #include "amdgpu_dma_buf.h"
 #include <uapi/linux/kfd_ioctl.h>
 #include "amdgpu_xgmi.h"
+#include "kfd_smi_events.h"
 
 /* Userptr restore delay, just long enough to allow consecutive VM
  * changes to accumulate
@@ -2346,7 +2347,7 @@ int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem,
 	evicted_bos = atomic_inc_return(&process_info->evicted_bos);
 	if (evicted_bos == 1) {
 		/* First eviction, stop the queues */
-		r = kgd2kfd_quiesce_mm(mm);
+		r = kgd2kfd_quiesce_mm(mm, KFD_QUEUE_EVICTION_TRIGGER_USERPTR);
 		if (r)
 			pr_err("Failed to quiesce KFD\n");
 		schedule_delayed_work(&process_info->restore_userptr_work,
@@ -2620,13 +2621,16 @@ static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
 
 unlock_out:
 	mutex_unlock(&process_info->lock);
-	mmput(mm);
-	put_task_struct(usertask);
 
 	/* If validation failed, reschedule another attempt */
-	if (evicted_bos)
+	if (evicted_bos) {
 		schedule_delayed_work(&process_info->restore_userptr_work,
 			msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
+
+		kfd_smi_event_queue_restore_rescheduled(mm);
+	}
+	mmput(mm);
+	put_task_struct(usertask);
 }
 
 /** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index d07588230ed60..2b3d8bc8f0aae 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -2434,7 +2434,7 @@ static int criu_restore(struct file *filep,
 	 * Set the process to evicted state to avoid running any new queues before all the memory
 	 * mappings are ready.
 	 */
-	ret = kfd_process_evict_queues(p);
+	ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_RESTORE);
 	if (ret)
 		goto exit_unlock;
 
@@ -2553,7 +2553,7 @@ static int criu_process_info(struct file *filep,
 		goto err_unlock;
 	}
 
-	ret = kfd_process_evict_queues(p);
+	ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT);
 	if (ret)
 		goto err_unlock;
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index c8fee0dbfdcb9..6ec0e9f0927d9 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -837,7 +837,7 @@ void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
 	spin_unlock_irqrestore(&kfd->interrupt_lock, flags);
 }
 
-int kgd2kfd_quiesce_mm(struct mm_struct *mm)
+int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger)
 {
 	struct kfd_process *p;
 	int r;
@@ -851,7 +851,7 @@ int kgd2kfd_quiesce_mm(struct mm_struct *mm)
 		return -ESRCH;
 
 	WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
-	r = kfd_process_evict_queues(p);
+	r = kfd_process_evict_queues(p, trigger);
 
 	kfd_unref_process(p);
 	return r;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 4c4bbd493caae..d03a3b9c9c5d6 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -947,7 +947,7 @@ static inline struct kfd_process_device *kfd_process_device_from_gpuidx(
 }
 
 void kfd_unref_process(struct kfd_process *p);
-int kfd_process_evict_queues(struct kfd_process *p);
+int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger);
 int kfd_process_restore_queues(struct kfd_process *p);
 void kfd_suspend_all_processes(void);
 int kfd_resume_all_processes(void);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index a13e60d48b735..fc38a4d81420d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -43,6 +43,7 @@ struct mm_struct;
 #include "kfd_device_queue_manager.h"
 #include "kfd_iommu.h"
 #include "kfd_svm.h"
+#include "kfd_smi_events.h"
 
 /*
  * List of struct kfd_process (field kfd_process).
@@ -1736,7 +1737,7 @@ struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm)
  * Eviction is reference-counted per process-device. This means multiple
  * evictions from different sources can be nested safely.
  */
-int kfd_process_evict_queues(struct kfd_process *p)
+int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger)
 {
 	int r = 0;
 	int i;
@@ -1745,6 +1746,9 @@ int kfd_process_evict_queues(struct kfd_process *p)
 	for (i = 0; i < p->n_pdds; i++) {
 		struct kfd_process_device *pdd = p->pdds[i];
 
+		kfd_smi_event_queue_eviction(pdd->dev, p->lead_thread->pid,
+					     trigger);
+
 		r = pdd->dev->dqm->ops.evict_process_queues(pdd->dev->dqm,
 							    &pdd->qpd);
 		/* evict return -EIO if HWS is hang or asic is resetting, in this case
@@ -1769,6 +1773,9 @@ fail:
 
 		if (n_evicted == 0)
 			break;
+
+		kfd_smi_event_queue_restore(pdd->dev, p->lead_thread->pid);
+
 		if (pdd->dev->dqm->ops.restore_process_queues(pdd->dev->dqm,
 							      &pdd->qpd))
 			pr_err("Failed to restore queues\n");
@@ -1788,6 +1795,8 @@ int kfd_process_restore_queues(struct kfd_process *p)
 	for (i = 0; i < p->n_pdds; i++) {
 		struct kfd_process_device *pdd = p->pdds[i];
 
+		kfd_smi_event_queue_restore(pdd->dev, p->lead_thread->pid);
+
 		r = pdd->dev->dqm->ops.restore_process_queues(pdd->dev->dqm,
 							      &pdd->qpd);
 		if (r) {
@@ -1849,7 +1858,7 @@ static void evict_process_worker(struct work_struct *work)
 	flush_delayed_work(&p->restore_work);
 
 	pr_debug("Started evicting pasid 0x%x\n", p->pasid);
-	ret = kfd_process_evict_queues(p);
+	ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_TRIGGER_TTM);
 	if (!ret) {
 		dma_fence_signal(p->ef);
 		dma_fence_put(p->ef);
@@ -1916,7 +1925,7 @@ void kfd_suspend_all_processes(void)
 		cancel_delayed_work_sync(&p->eviction_work);
 		cancel_delayed_work_sync(&p->restore_work);
 
-		if (kfd_process_evict_queues(p))
+		if (kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_TRIGGER_SUSPEND))
 			pr_err("Failed to suspend process 0x%x\n", p->pasid);
 		dma_fence_signal(p->ef);
 		dma_fence_put(p->ef);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
index ec4d278c2a471..3917c38204d09 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
@@ -283,6 +283,41 @@ void kfd_smi_event_migration_end(struct kfd_dev *dev, pid_t pid,
 			  from, to, trigger);
 }
 
+void kfd_smi_event_queue_eviction(struct kfd_dev *dev, pid_t pid,
+				  uint32_t trigger)
+{
+	kfd_smi_event_add(pid, dev, KFD_SMI_EVENT_QUEUE_EVICTION,
+			  "%lld -%d %x %d\n", ktime_get_boottime_ns(), pid,
+			  dev->id, trigger);
+}
+
+void kfd_smi_event_queue_restore(struct kfd_dev *dev, pid_t pid)
+{
+	kfd_smi_event_add(pid, dev, KFD_SMI_EVENT_QUEUE_RESTORE,
+			  "%lld -%d %x\n", ktime_get_boottime_ns(), pid,
+			  dev->id);
+}
+
+void kfd_smi_event_queue_restore_rescheduled(struct mm_struct *mm)
+{
+	struct kfd_process *p;
+	int i;
+
+	p = kfd_lookup_process_by_mm(mm);
+	if (!p)
+		return;
+
+	for (i = 0; i < p->n_pdds; i++) {
+		struct kfd_process_device *pdd = p->pdds[i];
+
+		kfd_smi_event_add(p->lead_thread->pid, pdd->dev,
+				  KFD_SMI_EVENT_QUEUE_RESTORE,
+				  "%lld -%d %x %c\n", ktime_get_boottime_ns(),
+				  p->lead_thread->pid, pdd->dev->id, 'R');
+	}
+	kfd_unref_process(p);
+}
+
 int kfd_smi_event_open(struct kfd_dev *dev, uint32_t *fd)
 {
 	struct kfd_smi_client *client;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h
index ec5d74a2fef44..b23292637239a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h
@@ -42,4 +42,8 @@ void kfd_smi_event_migration_start(struct kfd_dev *dev, pid_t pid,
 void kfd_smi_event_migration_end(struct kfd_dev *dev, pid_t pid,
 			     unsigned long start, unsigned long end,
 			     uint32_t from, uint32_t to, uint32_t trigger);
+void kfd_smi_event_queue_eviction(struct kfd_dev *dev, pid_t pid,
+				  uint32_t trigger);
+void kfd_smi_event_queue_restore(struct kfd_dev *dev, pid_t pid);
+void kfd_smi_event_queue_restore_rescheduled(struct mm_struct *mm);
 #endif
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index e8ded7a02bcb1..8bfb7b99e45d9 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -1730,14 +1730,16 @@ out_reschedule:
 	mutex_unlock(&svms->lock);
 	mmap_write_unlock(mm);
 	mutex_unlock(&process_info->lock);
-	mmput(mm);
 
 	/* If validation failed, reschedule another attempt */
 	if (evicted_ranges) {
 		pr_debug("reschedule to restore svm range\n");
 		schedule_delayed_work(&svms->restore_work,
 			msecs_to_jiffies(AMDGPU_SVM_RANGE_RESTORE_DELAY_MS));
+
+		kfd_smi_event_queue_restore_rescheduled(mm);
 	}
+	mmput(mm);
 }
 
 /**
@@ -1793,7 +1795,7 @@ svm_range_evict(struct svm_range *prange, struct mm_struct *mm,
 			 prange->svms, prange->start, prange->last);
 
 		/* First eviction, stop the queues */
-		r = kgd2kfd_quiesce_mm(mm);
+		r = kgd2kfd_quiesce_mm(mm, KFD_QUEUE_EVICTION_TRIGGER_SVM);
 		if (r)
 			pr_debug("failed to quiesce KFD\n");
 
-- 
GitLab


From 46ae2af9a8aa168cbad69f21bb1426771339ac9a Mon Sep 17 00:00:00 2001
From: Philip Yang <Philip.Yang@amd.com>
Date: Thu, 20 Jan 2022 16:43:42 -0500
Subject: [PATCH 1433/1731] drm/amdkfd: Add unmap from GPU SMI event

SVM range unmapped from GPUs when range is unmapped from CPU, or with
xnack on from MMU notifier when range is evicted or migrated.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c |  9 ++++++++
 drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h |  3 +++
 drivers/gpu/drm/amd/amdkfd/kfd_svm.c        | 25 +++++++++++++++------
 3 files changed, 30 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
index 3917c38204d09..e5896b7a16dd1 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
@@ -318,6 +318,15 @@ void kfd_smi_event_queue_restore_rescheduled(struct mm_struct *mm)
 	kfd_unref_process(p);
 }
 
+void kfd_smi_event_unmap_from_gpu(struct kfd_dev *dev, pid_t pid,
+				  unsigned long address, unsigned long last,
+				  uint32_t trigger)
+{
+	kfd_smi_event_add(pid, dev, KFD_SMI_EVENT_UNMAP_FROM_GPU,
+			  "%lld -%d @%lx(%lx) %x %d\n", ktime_get_boottime_ns(),
+			  pid, address, last - address + 1, dev->id, trigger);
+}
+
 int kfd_smi_event_open(struct kfd_dev *dev, uint32_t *fd)
 {
 	struct kfd_smi_client *client;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h
index b23292637239a..76fe4e0ec2d23 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h
@@ -46,4 +46,7 @@ void kfd_smi_event_queue_eviction(struct kfd_dev *dev, pid_t pid,
 				  uint32_t trigger);
 void kfd_smi_event_queue_restore(struct kfd_dev *dev, pid_t pid);
 void kfd_smi_event_queue_restore_rescheduled(struct mm_struct *mm);
+void kfd_smi_event_unmap_from_gpu(struct kfd_dev *dev, pid_t pid,
+				  unsigned long address, unsigned long last,
+				  uint32_t trigger);
 #endif
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 8bfb7b99e45d9..fd89951c29fe9 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -1200,7 +1200,7 @@ svm_range_unmap_from_gpu(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 
 static int
 svm_range_unmap_from_gpus(struct svm_range *prange, unsigned long start,
-			  unsigned long last)
+			  unsigned long last, uint32_t trigger)
 {
 	DECLARE_BITMAP(bitmap, MAX_GPU_INSTANCE);
 	struct kfd_process_device *pdd;
@@ -1232,6 +1232,9 @@ svm_range_unmap_from_gpus(struct svm_range *prange, unsigned long start,
 			return -EINVAL;
 		}
 
+		kfd_smi_event_unmap_from_gpu(pdd->dev, p->lead_thread->pid,
+					     start, last, trigger);
+
 		r = svm_range_unmap_from_gpu(pdd->dev->adev,
 					     drm_priv_to_vm(pdd->drm_priv),
 					     start, last, &fence);
@@ -1759,7 +1762,8 @@ out_reschedule:
  */
 static int
 svm_range_evict(struct svm_range *prange, struct mm_struct *mm,
-		unsigned long start, unsigned long last)
+		unsigned long start, unsigned long last,
+		enum mmu_notifier_event event)
 {
 	struct svm_range_list *svms = prange->svms;
 	struct svm_range *pchild;
@@ -1804,6 +1808,12 @@ svm_range_evict(struct svm_range *prange, struct mm_struct *mm,
 			msecs_to_jiffies(AMDGPU_SVM_RANGE_RESTORE_DELAY_MS));
 	} else {
 		unsigned long s, l;
+		uint32_t trigger;
+
+		if (event == MMU_NOTIFY_MIGRATE)
+			trigger = KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY_MIGRATE;
+		else
+			trigger = KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY;
 
 		pr_debug("invalidate unmap svms 0x%p [0x%lx 0x%lx] from GPUs\n",
 			 prange->svms, start, last);
@@ -1812,13 +1822,13 @@ svm_range_evict(struct svm_range *prange, struct mm_struct *mm,
 			s = max(start, pchild->start);
 			l = min(last, pchild->last);
 			if (l >= s)
-				svm_range_unmap_from_gpus(pchild, s, l);
+				svm_range_unmap_from_gpus(pchild, s, l, trigger);
 			mutex_unlock(&pchild->lock);
 		}
 		s = max(start, prange->start);
 		l = min(last, prange->last);
 		if (l >= s)
-			svm_range_unmap_from_gpus(prange, s, l);
+			svm_range_unmap_from_gpus(prange, s, l, trigger);
 	}
 
 	return r;
@@ -2232,6 +2242,7 @@ static void
 svm_range_unmap_from_cpu(struct mm_struct *mm, struct svm_range *prange,
 			 unsigned long start, unsigned long last)
 {
+	uint32_t trigger = KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU;
 	struct svm_range_list *svms;
 	struct svm_range *pchild;
 	struct kfd_process *p;
@@ -2259,14 +2270,14 @@ svm_range_unmap_from_cpu(struct mm_struct *mm, struct svm_range *prange,
 		s = max(start, pchild->start);
 		l = min(last, pchild->last);
 		if (l >= s)
-			svm_range_unmap_from_gpus(pchild, s, l);
+			svm_range_unmap_from_gpus(pchild, s, l, trigger);
 		svm_range_unmap_split(mm, prange, pchild, start, last);
 		mutex_unlock(&pchild->lock);
 	}
 	s = max(start, prange->start);
 	l = min(last, prange->last);
 	if (l >= s)
-		svm_range_unmap_from_gpus(prange, s, l);
+		svm_range_unmap_from_gpus(prange, s, l, trigger);
 	svm_range_unmap_split(mm, prange, prange, start, last);
 
 	if (unmap_parent)
@@ -2333,7 +2344,7 @@ svm_range_cpu_invalidate_pagetables(struct mmu_interval_notifier *mni,
 		svm_range_unmap_from_cpu(mni->mm, prange, start, last);
 		break;
 	default:
-		svm_range_evict(prange, mni->mm, start, last);
+		svm_range_evict(prange, mni->mm, start, last, range->event);
 		break;
 	}
 
-- 
GitLab


From 414e9f520e897818302a6b1729aa2dad8cc928ca Mon Sep 17 00:00:00 2001
From: Philip Yang <Philip.Yang@amd.com>
Date: Fri, 8 Apr 2022 10:25:11 -0400
Subject: [PATCH 1434/1731] drm/amdkfd: Asynchronously free smi_client

The synchronize_rcu may take several ms, which noticeably slows down
applications close SMI event handle. Use call_rcu to free client->fifo
and client asynchronously and eliminate the synchronize_rcu call in the
user thread.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
index e5896b7a16dd1..0472b56de2457 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
@@ -38,6 +38,7 @@ struct kfd_smi_client {
 	uint64_t events;
 	struct kfd_dev *dev;
 	spinlock_t lock;
+	struct rcu_head rcu;
 	pid_t pid;
 	bool suser;
 };
@@ -137,6 +138,14 @@ static ssize_t kfd_smi_ev_write(struct file *filep, const char __user *user,
 	return sizeof(events);
 }
 
+static void kfd_smi_ev_client_free(struct rcu_head *p)
+{
+	struct kfd_smi_client *ev = container_of(p, struct kfd_smi_client, rcu);
+
+	kfifo_free(&ev->fifo);
+	kfree(ev);
+}
+
 static int kfd_smi_ev_release(struct inode *inode, struct file *filep)
 {
 	struct kfd_smi_client *client = filep->private_data;
@@ -146,10 +155,7 @@ static int kfd_smi_ev_release(struct inode *inode, struct file *filep)
 	list_del_rcu(&client->list);
 	spin_unlock(&dev->smi_lock);
 
-	synchronize_rcu();
-	kfifo_free(&client->fifo);
-	kfree(client);
-
+	call_rcu(&client->rcu, kfd_smi_ev_client_free);
 	return 0;
 }
 
-- 
GitLab


From 3db7f894549a54dd6f8dfb7fe213ede83249bb94 Mon Sep 17 00:00:00 2001
From: Philip Yang <Philip.Yang@amd.com>
Date: Wed, 19 Jan 2022 12:57:26 -0500
Subject: [PATCH 1435/1731] drm/amdkfd: Bump KFD API version for SMI profiling
 event

Indicate SMI profiling events available.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 include/uapi/linux/kfd_ioctl.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index 280edda46faf7..d993a0d50994b 100644
--- a/include/uapi/linux/kfd_ioctl.h
+++ b/include/uapi/linux/kfd_ioctl.h
@@ -35,9 +35,10 @@
  * - 1.7 - Checkpoint Restore (CRIU) API
  * - 1.8 - CRIU - Support for SDMA transfers with GTT BOs
  * - 1.9 - Add available memory ioctl
+ * - 1.10 - Add SMI profiler event log
  */
 #define KFD_IOCTL_MAJOR_VERSION 1
-#define KFD_IOCTL_MINOR_VERSION 9
+#define KFD_IOCTL_MINOR_VERSION 10
 
 struct kfd_ioctl_get_version_args {
 	__u32 major_version;	/* from KFD */
-- 
GitLab


From 1adb1563e7b7ec659379a18e607e8bc3522d8a78 Mon Sep 17 00:00:00 2001
From: Lukasz Cieplicki <lukaszx.cieplicki@intel.com>
Date: Tue, 31 May 2022 12:54:20 +0200
Subject: [PATCH 1436/1731] i40e: Fix dropped jumbo frames statistics

Dropped packets caused by too large frames were not included in
dropped RX packets statistics.
Issue was caused by not reading the GL_RXERR1 register. That register
stores count of packet which was have been dropped due to too large
size.

Fix it by reading GL_RXERR1 register for each interface.

Repro steps:
Send a packet larger than the set MTU to SUT
Observe rx statists: ethtool -S <interface> | grep rx | grep -v ": 0"

Fixes: 41a9e55c89be ("i40e: add missing VSI statistics")
Signed-off-by: Lukasz Cieplicki <lukaszx.cieplicki@intel.com>
Signed-off-by: Jedrzej Jagielski <jedrzej.jagielski@intel.com>
Tested-by: Gurucharan <gurucharanx.g@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
---
 drivers/net/ethernet/intel/i40e/i40e.h        | 16 ++++
 drivers/net/ethernet/intel/i40e/i40e_main.c   | 73 +++++++++++++++++++
 .../net/ethernet/intel/i40e/i40e_register.h   | 13 ++++
 drivers/net/ethernet/intel/i40e/i40e_type.h   |  1 +
 4 files changed, 103 insertions(+)

diff --git a/drivers/net/ethernet/intel/i40e/i40e.h b/drivers/net/ethernet/intel/i40e/i40e.h
index 18558a0193531..407fe8f340a06 100644
--- a/drivers/net/ethernet/intel/i40e/i40e.h
+++ b/drivers/net/ethernet/intel/i40e/i40e.h
@@ -37,6 +37,7 @@
 #include <net/tc_act/tc_mirred.h>
 #include <net/udp_tunnel.h>
 #include <net/xdp_sock.h>
+#include <linux/bitfield.h>
 #include "i40e_type.h"
 #include "i40e_prototype.h"
 #include <linux/net/intel/i40e_client.h>
@@ -1092,6 +1093,21 @@ static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
 			  (u32)(val & 0xFFFFFFFFULL));
 }
 
+/**
+ * i40e_get_pf_count - get PCI PF count.
+ * @hw: pointer to a hw.
+ *
+ * Reports the function number of the highest PCI physical
+ * function plus 1 as it is loaded from the NVM.
+ *
+ * Return: PCI PF count.
+ **/
+static inline u32 i40e_get_pf_count(struct i40e_hw *hw)
+{
+	return FIELD_GET(I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK,
+			 rd32(hw, I40E_GLGEN_PCIFCNCNT));
+}
+
 /* needed by i40e_ethtool.c */
 int i40e_up(struct i40e_vsi *vsi);
 void i40e_down(struct i40e_vsi *vsi);
diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c
index 72576bb3e94d4..aa786fd559511 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_main.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_main.c
@@ -550,6 +550,47 @@ void i40e_pf_reset_stats(struct i40e_pf *pf)
 	pf->hw_csum_rx_error = 0;
 }
 
+/**
+ * i40e_compute_pci_to_hw_id - compute index form PCI function.
+ * @vsi: ptr to the VSI to read from.
+ * @hw: ptr to the hardware info.
+ **/
+static u32 i40e_compute_pci_to_hw_id(struct i40e_vsi *vsi, struct i40e_hw *hw)
+{
+	int pf_count = i40e_get_pf_count(hw);
+
+	if (vsi->type == I40E_VSI_SRIOV)
+		return (hw->port * BIT(7)) / pf_count + vsi->vf_id;
+
+	return hw->port + BIT(7);
+}
+
+/**
+ * i40e_stat_update64 - read and update a 64 bit stat from the chip.
+ * @hw: ptr to the hardware info.
+ * @hireg: the high 32 bit reg to read.
+ * @loreg: the low 32 bit reg to read.
+ * @offset_loaded: has the initial offset been loaded yet.
+ * @offset: ptr to current offset value.
+ * @stat: ptr to the stat.
+ *
+ * Since the device stats are not reset at PFReset, they will not
+ * be zeroed when the driver starts.  We'll save the first values read
+ * and use them as offsets to be subtracted from the raw values in order
+ * to report stats that count from zero.
+ **/
+static void i40e_stat_update64(struct i40e_hw *hw, u32 hireg, u32 loreg,
+			       bool offset_loaded, u64 *offset, u64 *stat)
+{
+	u64 new_data;
+
+	new_data = rd64(hw, loreg);
+
+	if (!offset_loaded || new_data < *offset)
+		*offset = new_data;
+	*stat = new_data - *offset;
+}
+
 /**
  * i40e_stat_update48 - read and update a 48 bit stat from the chip
  * @hw: ptr to the hardware info
@@ -621,6 +662,34 @@ static void i40e_stat_update_and_clear32(struct i40e_hw *hw, u32 reg, u64 *stat)
 	*stat += new_data;
 }
 
+/**
+ * i40e_stats_update_rx_discards - update rx_discards.
+ * @vsi: ptr to the VSI to be updated.
+ * @hw: ptr to the hardware info.
+ * @stat_idx: VSI's stat_counter_idx.
+ * @offset_loaded: ptr to the VSI's stat_offsets_loaded.
+ * @stat_offset: ptr to stat_offset to store first read of specific register.
+ * @stat: ptr to VSI's stat to be updated.
+ **/
+static void
+i40e_stats_update_rx_discards(struct i40e_vsi *vsi, struct i40e_hw *hw,
+			      int stat_idx, bool offset_loaded,
+			      struct i40e_eth_stats *stat_offset,
+			      struct i40e_eth_stats *stat)
+{
+	u64 rx_rdpc, rx_rxerr;
+
+	i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx), offset_loaded,
+			   &stat_offset->rx_discards, &rx_rdpc);
+	i40e_stat_update64(hw,
+			   I40E_GL_RXERR1H(i40e_compute_pci_to_hw_id(vsi, hw)),
+			   I40E_GL_RXERR1L(i40e_compute_pci_to_hw_id(vsi, hw)),
+			   offset_loaded, &stat_offset->rx_discards_other,
+			   &rx_rxerr);
+
+	stat->rx_discards = rx_rdpc + rx_rxerr;
+}
+
 /**
  * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
  * @vsi: the VSI to be updated
@@ -680,6 +749,10 @@ void i40e_update_eth_stats(struct i40e_vsi *vsi)
 			   I40E_GLV_BPTCL(stat_idx),
 			   vsi->stat_offsets_loaded,
 			   &oes->tx_broadcast, &es->tx_broadcast);
+
+	i40e_stats_update_rx_discards(vsi, hw, stat_idx,
+				      vsi->stat_offsets_loaded, oes, es);
+
 	vsi->stat_offsets_loaded = true;
 }
 
diff --git a/drivers/net/ethernet/intel/i40e/i40e_register.h b/drivers/net/ethernet/intel/i40e/i40e_register.h
index 1908eed4fa5ee..7339003aa17cd 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_register.h
+++ b/drivers/net/ethernet/intel/i40e/i40e_register.h
@@ -211,6 +211,11 @@
 #define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0
 #define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16
 #define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT)
+#define I40E_GLGEN_PCIFCNCNT                0x001C0AB4 /* Reset: PCIR */
+#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0
+#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK  I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT)
+#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT 16
+#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK  I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT)
 #define I40E_GLGEN_RSTAT 0x000B8188 /* Reset: POR */
 #define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT 0
 #define I40E_GLGEN_RSTAT_DEVSTATE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_DEVSTATE_SHIFT)
@@ -643,6 +648,14 @@
 #define I40E_VFQF_HKEY1_MAX_INDEX 12
 #define I40E_VFQF_HLUT1(_i, _VF) (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: CORER */
 #define I40E_VFQF_HLUT1_MAX_INDEX 15
+#define I40E_GL_RXERR1H(_i)             (0x00318004 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
+#define I40E_GL_RXERR1H_MAX_INDEX       143
+#define I40E_GL_RXERR1H_RXERR1H_SHIFT   0
+#define I40E_GL_RXERR1H_RXERR1H_MASK    I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1H_RXERR1H_SHIFT)
+#define I40E_GL_RXERR1L(_i)             (0x00318000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
+#define I40E_GL_RXERR1L_MAX_INDEX       143
+#define I40E_GL_RXERR1L_RXERR1L_SHIFT   0
+#define I40E_GL_RXERR1L_RXERR1L_MASK    I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1L_RXERR1L_SHIFT)
 #define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
diff --git a/drivers/net/ethernet/intel/i40e/i40e_type.h b/drivers/net/ethernet/intel/i40e/i40e_type.h
index 36a4ca1ffb1a9..7b3f30beb757a 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_type.h
+++ b/drivers/net/ethernet/intel/i40e/i40e_type.h
@@ -1172,6 +1172,7 @@ struct i40e_eth_stats {
 	u64 tx_broadcast;		/* bptc */
 	u64 tx_discards;		/* tdpc */
 	u64 tx_errors;			/* tepc */
+	u64 rx_discards_other;          /* rxerr1 */
 };
 
 /* Statistics collected per VEB per TC */
-- 
GitLab


From fed0d9f13266a22ce1fc9a97521ef9cdc6271a23 Mon Sep 17 00:00:00 2001
From: Norbert Zulinski <norbertx.zulinski@intel.com>
Date: Wed, 8 Jun 2022 11:10:56 +0200
Subject: [PATCH 1437/1731] i40e: Fix VF's MAC Address change on VM

Clear VF MAC from parent PF and remove VF filter from VSI when both
conditions are true:
-VIRTCHNL_VF_OFFLOAD_USO is not used
-VM MAC was not set from PF level

It affects older version of IAVF and it allow them to change MAC
Address on VM, newer IAVF won't change their behaviour.

Previously it wasn't possible to change VF's MAC Address on VM
because there is flag on IAVF driver that won't allow to
change MAC Address if this address is given from PF driver.

Fixes: 155f0ac2c96b ("iavf: allow permanent MAC address to change")
Signed-off-by: Norbert Zulinski <norbertx.zulinski@intel.com>
Signed-off-by: Jan Sokolowski <jan.sokolowski@intel.com>
Tested-by: Konrad Jankowski <konrad0.jankowski@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
---
 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
index 033ea71763e3d..86b0f21287dc8 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
@@ -2147,6 +2147,10 @@ static int i40e_vc_get_vf_resources_msg(struct i40e_vf *vf, u8 *msg)
 		/* VFs only use TC 0 */
 		vfres->vsi_res[0].qset_handle
 					  = le16_to_cpu(vsi->info.qs_handle[0]);
+		if (!(vf->driver_caps & VIRTCHNL_VF_OFFLOAD_USO) && !vf->pf_set_mac) {
+			i40e_del_mac_filter(vsi, vf->default_lan_addr.addr);
+			eth_zero_addr(vf->default_lan_addr.addr);
+		}
 		ether_addr_copy(vfres->vsi_res[0].default_mac_addr,
 				vf->default_lan_addr.addr);
 	}
-- 
GitLab


From 080abad71e99d2becf38c978572982130b927a28 Mon Sep 17 00:00:00 2001
From: NeilBrown <neilb@suse.de>
Date: Thu, 23 Jun 2022 14:47:34 +1000
Subject: [PATCH 1438/1731] NFS: restore module put when manager exits.

Commit f49169c97fce ("NFSD: Remove svc_serv_ops::svo_module") removed
calls to module_put_and_kthread_exit() from threads that acted as SUNRPC
servers and had a related svc_serv_ops structure.  This was correct.

It ALSO removed the module_put_and_kthread_exit() call from
nfs4_run_state_manager() which is NOT a SUNRPC service.

Consequently every time the NFSv4 state manager runs the module count
increments and won't be decremented.  So the nfsv4 module cannot be
unloaded.

So restore the module_put_and_kthread_exit() call.

Fixes: f49169c97fce ("NFSD: Remove svc_serv_ops::svo_module")
Signed-off-by: NeilBrown <neilb@suse.de>
Signed-off-by: Anna Schumaker <Anna.Schumaker@Netapp.com>
---
 fs/nfs/nfs4state.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fs/nfs/nfs4state.c b/fs/nfs/nfs4state.c
index 2540b35ec1870..9bab3e9c702a4 100644
--- a/fs/nfs/nfs4state.c
+++ b/fs/nfs/nfs4state.c
@@ -2753,5 +2753,6 @@ again:
 		goto again;
 
 	nfs_put_client(clp);
+	module_put_and_kthread_exit(0);
 	return 0;
 }
-- 
GitLab


From 4f40a5b5544618b096d1611a18219dd91fd57f80 Mon Sep 17 00:00:00 2001
From: Scott Mayhew <smayhew@redhat.com>
Date: Mon, 27 Jun 2022 17:31:29 -0400
Subject: [PATCH 1439/1731] NFSv4: Add an fattr allocation to
 _nfs4_discover_trunking()

This was missed in c3ed222745d9 ("NFSv4: Fix free of uninitialized
nfs4_label on referral lookup.") and causes a panic when mounting
with '-o trunkdiscovery':

PID: 1604   TASK: ffff93dac3520000  CPU: 3   COMMAND: "mount.nfs"
 #0 [ffffb79140f738f8] machine_kexec at ffffffffaec64bee
 #1 [ffffb79140f73950] __crash_kexec at ffffffffaeda67fd
 #2 [ffffb79140f73a18] crash_kexec at ffffffffaeda76ed
 #3 [ffffb79140f73a30] oops_end at ffffffffaec2658d
 #4 [ffffb79140f73a50] general_protection at ffffffffaf60111e
    [exception RIP: nfs_fattr_init+0x5]
    RIP: ffffffffc0c18265  RSP: ffffb79140f73b08  RFLAGS: 00010246
    RAX: 0000000000000000  RBX: ffff93dac304a800  RCX: 0000000000000000
    RDX: ffffb79140f73bb0  RSI: ffff93dadc8cbb40  RDI: d03ee11cfaf6bd50
    RBP: ffffb79140f73be8   R8: ffffffffc0691560   R9: 0000000000000006
    R10: ffff93db3ffd3df8  R11: 0000000000000000  R12: ffff93dac4040000
    R13: ffff93dac2848e00  R14: ffffb79140f73b60  R15: ffffb79140f73b30
    ORIG_RAX: ffffffffffffffff  CS: 0010  SS: 0018
 #5 [ffffb79140f73b08] _nfs41_proc_get_locations at ffffffffc0c73d53 [nfsv4]
 #6 [ffffb79140f73bf0] nfs4_proc_get_locations at ffffffffc0c83e90 [nfsv4]
 #7 [ffffb79140f73c60] nfs4_discover_trunking at ffffffffc0c83fb7 [nfsv4]
 #8 [ffffb79140f73cd8] nfs_probe_fsinfo at ffffffffc0c0f95f [nfs]
 #9 [ffffb79140f73da0] nfs_probe_server at ffffffffc0c1026a [nfs]
    RIP: 00007f6254fce26e  RSP: 00007ffc69496ac8  RFLAGS: 00000246
    RAX: ffffffffffffffda  RBX: 0000000000000000  RCX: 00007f6254fce26e
    RDX: 00005600220a82a0  RSI: 00005600220a64d0  RDI: 00005600220a6520
    RBP: 00007ffc69496c50   R8: 00005600220a8710   R9: 003035322e323231
    R10: 0000000000000000  R11: 0000000000000246  R12: 00007ffc69496c50
    R13: 00005600220a8440  R14: 0000000000000010  R15: 0000560020650ef9
    ORIG_RAX: 00000000000000a5  CS: 0033  SS: 002b

Fixes: c3ed222745d9 ("NFSv4: Fix free of uninitialized nfs4_label on referral lookup.")
Signed-off-by: Scott Mayhew <smayhew@redhat.com>
Signed-off-by: Anna Schumaker <Anna.Schumaker@Netapp.com>
---
 fs/nfs/nfs4proc.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/fs/nfs/nfs4proc.c b/fs/nfs/nfs4proc.c
index c0fdcf8c00329..bb0e84a46d61a 100644
--- a/fs/nfs/nfs4proc.c
+++ b/fs/nfs/nfs4proc.c
@@ -4012,22 +4012,29 @@ static int _nfs4_discover_trunking(struct nfs_server *server,
 	}
 
 	page = alloc_page(GFP_KERNEL);
+	if (!page)
+		return -ENOMEM;
 	locations = kmalloc(sizeof(struct nfs4_fs_locations), GFP_KERNEL);
-	if (page == NULL || locations == NULL)
-		goto out;
+	if (!locations)
+		goto out_free;
+	locations->fattr = nfs_alloc_fattr();
+	if (!locations->fattr)
+		goto out_free_2;
 
 	status = nfs4_proc_get_locations(server, fhandle, locations, page,
 					 cred);
 	if (status)
-		goto out;
+		goto out_free_3;
 
 	for (i = 0; i < locations->nlocations; i++)
 		test_fs_location_for_trunking(&locations->locations[i], clp,
 					      server);
-out:
-	if (page)
-		__free_page(page);
+out_free_3:
+	kfree(locations->fattr);
+out_free_2:
 	kfree(locations);
+out_free:
+	__free_page(page);
 	return status;
 }
 
-- 
GitLab


From a23dd544debcda4ee4a549ec7de59e85c3c8345c Mon Sep 17 00:00:00 2001
From: Chuck Lever <chuck.lever@oracle.com>
Date: Thu, 30 Jun 2022 16:48:18 -0400
Subject: [PATCH 1440/1731] SUNRPC: Fix READ_PLUS crasher

Looks like there are still cases when "space_left - frag1bytes" can
legitimately exceed PAGE_SIZE. Ensure that xdr->end always remains
within the current encode buffer.

Reported-by: Bruce Fields <bfields@fieldses.org>
Reported-by: Zorro Lang <zlang@redhat.com>
Link: https://bugzilla.kernel.org/show_bug.cgi?id=216151
Fixes: 6c254bf3b637 ("SUNRPC: Fix the calculation of xdr->end in xdr_get_next_encode_buffer()")
Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
---
 net/sunrpc/xdr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/net/sunrpc/xdr.c b/net/sunrpc/xdr.c
index f87a2d8f23a72..5d2b3e6979fb9 100644
--- a/net/sunrpc/xdr.c
+++ b/net/sunrpc/xdr.c
@@ -984,7 +984,7 @@ static noinline __be32 *xdr_get_next_encode_buffer(struct xdr_stream *xdr,
 	p = page_address(*xdr->page_ptr);
 	xdr->p = p + frag2bytes;
 	space_left = xdr->buf->buflen - xdr->buf->len;
-	if (space_left - nbytes >= PAGE_SIZE)
+	if (space_left - frag1bytes >= PAGE_SIZE)
 		xdr->end = p + PAGE_SIZE;
 	else
 		xdr->end = p + space_left - frag1bytes;
-- 
GitLab


From 868f9f2f8e004bfe0d3935b1976f625b2924893b Mon Sep 17 00:00:00 2001
From: Amir Goldstein <amir73il@gmail.com>
Date: Thu, 30 Jun 2022 22:58:49 +0300
Subject: [PATCH 1441/1731] vfs: fix copy_file_range() regression in cross-fs
 copies

A regression has been reported by Nicolas Boichat, found while using the
copy_file_range syscall to copy a tracefs file.

Before commit 5dae222a5ff0 ("vfs: allow copy_file_range to copy across
devices") the kernel would return -EXDEV to userspace when trying to
copy a file across different filesystems.  After this commit, the
syscall doesn't fail anymore and instead returns zero (zero bytes
copied), as this file's content is generated on-the-fly and thus reports
a size of zero.

Another regression has been reported by He Zhe - the assertion of
WARN_ON_ONCE(ret == -EOPNOTSUPP) can be triggered from userspace when
copying from a sysfs file whose read operation may return -EOPNOTSUPP.

Since we do not have test coverage for copy_file_range() between any two
types of filesystems, the best way to avoid these sort of issues in the
future is for the kernel to be more picky about filesystems that are
allowed to do copy_file_range().

This patch restores some cross-filesystem copy restrictions that existed
prior to commit 5dae222a5ff0 ("vfs: allow copy_file_range to copy across
devices"), namely, cross-sb copy is not allowed for filesystems that do
not implement ->copy_file_range().

Filesystems that do implement ->copy_file_range() have full control of
the result - if this method returns an error, the error is returned to
the user.  Before this change this was only true for fs that did not
implement the ->remap_file_range() operation (i.e.  nfsv3).

Filesystems that do not implement ->copy_file_range() still fall-back to
the generic_copy_file_range() implementation when the copy is within the
same sb.  This helps the kernel can maintain a more consistent story
about which filesystems support copy_file_range().

nfsd and ksmbd servers are modified to fall-back to the
generic_copy_file_range() implementation in case vfs_copy_file_range()
fails with -EOPNOTSUPP or -EXDEV, which preserves behavior of
server-side-copy.

fall-back to generic_copy_file_range() is not implemented for the smb
operation FSCTL_DUPLICATE_EXTENTS_TO_FILE, which is arguably a correct
change of behavior.

Fixes: 5dae222a5ff0 ("vfs: allow copy_file_range to copy across devices")
Link: https://lore.kernel.org/linux-fsdevel/20210212044405.4120619-1-drinkcat@chromium.org/
Link: https://lore.kernel.org/linux-fsdevel/CANMq1KDZuxir2LM5jOTm0xx+BnvW=ZmpsG47CyHFJwnw7zSX6Q@mail.gmail.com/
Link: https://lore.kernel.org/linux-fsdevel/20210126135012.1.If45b7cdc3ff707bc1efa17f5366057d60603c45f@changeid/
Link: https://lore.kernel.org/linux-fsdevel/20210630161320.29006-1-lhenriques@suse.de/
Reported-by: Nicolas Boichat <drinkcat@chromium.org>
Reported-by: kernel test robot <oliver.sang@intel.com>
Signed-off-by: Luis Henriques <lhenriques@suse.de>
Fixes: 64bf5ff58dff ("vfs: no fallback for ->copy_file_range")
Link: https://lore.kernel.org/linux-fsdevel/20f17f64-88cb-4e80-07c1-85cb96c83619@windriver.com/
Reported-by: He Zhe <zhe.he@windriver.com>
Tested-by: Namjae Jeon <linkinjeon@kernel.org>
Tested-by: Luis Henriques <lhenriques@suse.de>
Signed-off-by: Amir Goldstein <amir73il@gmail.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
---
 fs/ksmbd/smb2pdu.c | 16 ++++++++--
 fs/ksmbd/vfs.c     |  4 +++
 fs/nfsd/vfs.c      |  8 ++++-
 fs/read_write.c    | 77 ++++++++++++++++++++++++++--------------------
 4 files changed, 68 insertions(+), 37 deletions(-)

diff --git a/fs/ksmbd/smb2pdu.c b/fs/ksmbd/smb2pdu.c
index 94ab1dcd80e7b..353f047e783ca 100644
--- a/fs/ksmbd/smb2pdu.c
+++ b/fs/ksmbd/smb2pdu.c
@@ -7810,14 +7810,24 @@ int smb2_ioctl(struct ksmbd_work *work)
 		src_off = le64_to_cpu(dup_ext->SourceFileOffset);
 		dst_off = le64_to_cpu(dup_ext->TargetFileOffset);
 		length = le64_to_cpu(dup_ext->ByteCount);
-		cloned = vfs_clone_file_range(fp_in->filp, src_off, fp_out->filp,
-					      dst_off, length, 0);
+		/*
+		 * XXX: It is not clear if FSCTL_DUPLICATE_EXTENTS_TO_FILE
+		 * should fall back to vfs_copy_file_range().  This could be
+		 * beneficial when re-exporting nfs/smb mount, but note that
+		 * this can result in partial copy that returns an error status.
+		 * If/when FSCTL_DUPLICATE_EXTENTS_TO_FILE_EX is implemented,
+		 * fall back to vfs_copy_file_range(), should be avoided when
+		 * the flag DUPLICATE_EXTENTS_DATA_EX_SOURCE_ATOMIC is set.
+		 */
+		cloned = vfs_clone_file_range(fp_in->filp, src_off,
+					      fp_out->filp, dst_off, length, 0);
 		if (cloned == -EXDEV || cloned == -EOPNOTSUPP) {
 			ret = -EOPNOTSUPP;
 			goto dup_ext_out;
 		} else if (cloned != length) {
 			cloned = vfs_copy_file_range(fp_in->filp, src_off,
-						     fp_out->filp, dst_off, length, 0);
+						     fp_out->filp, dst_off,
+						     length, 0);
 			if (cloned != length) {
 				if (cloned < 0)
 					ret = cloned;
diff --git a/fs/ksmbd/vfs.c b/fs/ksmbd/vfs.c
index 5d185564aef6b..05efcdf7a4a73 100644
--- a/fs/ksmbd/vfs.c
+++ b/fs/ksmbd/vfs.c
@@ -1779,6 +1779,10 @@ int ksmbd_vfs_copy_file_ranges(struct ksmbd_work *work,
 
 		ret = vfs_copy_file_range(src_fp->filp, src_off,
 					  dst_fp->filp, dst_off, len, 0);
+		if (ret == -EOPNOTSUPP || ret == -EXDEV)
+			ret = generic_copy_file_range(src_fp->filp, src_off,
+						      dst_fp->filp, dst_off,
+						      len, 0);
 		if (ret < 0)
 			return ret;
 
diff --git a/fs/nfsd/vfs.c b/fs/nfsd/vfs.c
index 840e3af63a6f1..b764213bcc553 100644
--- a/fs/nfsd/vfs.c
+++ b/fs/nfsd/vfs.c
@@ -577,6 +577,7 @@ out_err:
 ssize_t nfsd_copy_file_range(struct file *src, u64 src_pos, struct file *dst,
 			     u64 dst_pos, u64 count)
 {
+	ssize_t ret;
 
 	/*
 	 * Limit copy to 4MB to prevent indefinitely blocking an nfsd
@@ -587,7 +588,12 @@ ssize_t nfsd_copy_file_range(struct file *src, u64 src_pos, struct file *dst,
 	 * limit like this and pipeline multiple COPY requests.
 	 */
 	count = min_t(u64, count, 1 << 22);
-	return vfs_copy_file_range(src, src_pos, dst, dst_pos, count, 0);
+	ret = vfs_copy_file_range(src, src_pos, dst, dst_pos, count, 0);
+
+	if (ret == -EOPNOTSUPP || ret == -EXDEV)
+		ret = generic_copy_file_range(src, src_pos, dst, dst_pos,
+					      count, 0);
+	return ret;
 }
 
 __be32 nfsd4_vfs_fallocate(struct svc_rqst *rqstp, struct svc_fh *fhp,
diff --git a/fs/read_write.c b/fs/read_write.c
index b1b1cdfee9d39..e0777eefd8465 100644
--- a/fs/read_write.c
+++ b/fs/read_write.c
@@ -1397,28 +1397,6 @@ ssize_t generic_copy_file_range(struct file *file_in, loff_t pos_in,
 }
 EXPORT_SYMBOL(generic_copy_file_range);
 
-static ssize_t do_copy_file_range(struct file *file_in, loff_t pos_in,
-				  struct file *file_out, loff_t pos_out,
-				  size_t len, unsigned int flags)
-{
-	/*
-	 * Although we now allow filesystems to handle cross sb copy, passing
-	 * a file of the wrong filesystem type to filesystem driver can result
-	 * in an attempt to dereference the wrong type of ->private_data, so
-	 * avoid doing that until we really have a good reason.  NFS defines
-	 * several different file_system_type structures, but they all end up
-	 * using the same ->copy_file_range() function pointer.
-	 */
-	if (file_out->f_op->copy_file_range &&
-	    file_out->f_op->copy_file_range == file_in->f_op->copy_file_range)
-		return file_out->f_op->copy_file_range(file_in, pos_in,
-						       file_out, pos_out,
-						       len, flags);
-
-	return generic_copy_file_range(file_in, pos_in, file_out, pos_out, len,
-				       flags);
-}
-
 /*
  * Performs necessary checks before doing a file copy
  *
@@ -1440,6 +1418,24 @@ static int generic_copy_file_checks(struct file *file_in, loff_t pos_in,
 	if (ret)
 		return ret;
 
+	/*
+	 * We allow some filesystems to handle cross sb copy, but passing
+	 * a file of the wrong filesystem type to filesystem driver can result
+	 * in an attempt to dereference the wrong type of ->private_data, so
+	 * avoid doing that until we really have a good reason.
+	 *
+	 * nfs and cifs define several different file_system_type structures
+	 * and several different sets of file_operations, but they all end up
+	 * using the same ->copy_file_range() function pointer.
+	 */
+	if (file_out->f_op->copy_file_range) {
+		if (file_in->f_op->copy_file_range !=
+		    file_out->f_op->copy_file_range)
+			return -EXDEV;
+	} else if (file_inode(file_in)->i_sb != file_inode(file_out)->i_sb) {
+		return -EXDEV;
+	}
+
 	/* Don't touch certain kinds of inodes */
 	if (IS_IMMUTABLE(inode_out))
 		return -EPERM;
@@ -1505,26 +1501,41 @@ ssize_t vfs_copy_file_range(struct file *file_in, loff_t pos_in,
 	file_start_write(file_out);
 
 	/*
-	 * Try cloning first, this is supported by more file systems, and
-	 * more efficient if both clone and copy are supported (e.g. NFS).
+	 * Cloning is supported by more file systems, so we implement copy on
+	 * same sb using clone, but for filesystems where both clone and copy
+	 * are supported (e.g. nfs,cifs), we only call the copy method.
 	 */
+	if (file_out->f_op->copy_file_range) {
+		ret = file_out->f_op->copy_file_range(file_in, pos_in,
+						      file_out, pos_out,
+						      len, flags);
+		goto done;
+	}
+
 	if (file_in->f_op->remap_file_range &&
 	    file_inode(file_in)->i_sb == file_inode(file_out)->i_sb) {
-		loff_t cloned;
-
-		cloned = file_in->f_op->remap_file_range(file_in, pos_in,
+		ret = file_in->f_op->remap_file_range(file_in, pos_in,
 				file_out, pos_out,
 				min_t(loff_t, MAX_RW_COUNT, len),
 				REMAP_FILE_CAN_SHORTEN);
-		if (cloned > 0) {
-			ret = cloned;
+		if (ret > 0)
 			goto done;
-		}
 	}
 
-	ret = do_copy_file_range(file_in, pos_in, file_out, pos_out, len,
-				flags);
-	WARN_ON_ONCE(ret == -EOPNOTSUPP);
+	/*
+	 * We can get here for same sb copy of filesystems that do not implement
+	 * ->copy_file_range() in case filesystem does not support clone or in
+	 * case filesystem supports clone but rejected the clone request (e.g.
+	 * because it was not block aligned).
+	 *
+	 * In both cases, fall back to kernel copy so we are able to maintain a
+	 * consistent story about which filesystems support copy_file_range()
+	 * and which filesystems do not, that will allow userspace tools to
+	 * make consistent desicions w.r.t using copy_file_range().
+	 */
+	ret = generic_copy_file_range(file_in, pos_in, file_out, pos_out, len,
+				      flags);
+
 done:
 	if (ret > 0) {
 		fsnotify_access(file_in);
-- 
GitLab


From 0d8928a94ba18205cc7b41793af333e6731e9d76 Mon Sep 17 00:00:00 2001
From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Date: Thu, 30 Jun 2022 14:46:18 -0400
Subject: [PATCH 1442/1731] drm/amd/display: Fix __umoddi3 undefined for 32 bit
 compilation

While we tried to build amdgpu on i386, we got this error:

ERROR: modpost: "__umoddi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!

This commit fixes this issue by replacing the standard module operator
with div_u64_rem.

Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Randy Dunlap <rdunlap@infradead.org>
Fixes: d3dfceb58de5 ("drm/amd/display: Add dependant changes for DCN32/321")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Tested-by: Randy Dunlap <rdunlap@infradead.org> # build-tested
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index a10ec59191941..790aa2b3952cc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -208,12 +208,14 @@ static uint32_t dcn32_cache_lines_for_surface(struct dc *dc, uint32_t surface_si
 	uint32_t num_cached_bytes = 0;
 	uint32_t remaining_size = 0;
 	uint32_t cache_line_size = dc->caps.cache_line_size;
+	uint32_t remainder = 0;
 
 	/* 1. Calculate surface size minus the number of bytes stored
 	 * in the first cache line (all bytes in first cache line might
 	 * not be fully used).
 	 */
-	num_cached_bytes = cache_line_size - (start_address % cache_line_size);
+	div_u64_rem(start_address, cache_line_size, &remainder);
+	num_cached_bytes = cache_line_size - remainder;
 	remaining_size = surface_size - num_cached_bytes;
 
 	/* 2. Calculate number of cache lines that will be fully used with
-- 
GitLab


From 071ebbb0d4826ce7c47953b955a522f503dcedfb Mon Sep 17 00:00:00 2001
From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Date: Thu, 30 Jun 2022 14:46:19 -0400
Subject: [PATCH 1443/1731] drm/amd/display: Fix __floatunsidf undefined for 32
 bit compilation

When we tried to compile DCN32/321 for 32-bit architecture, we got this
error message:

ERROR: modpost: "__floatunsidf" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!

This was caused because we were trying to assign an unsigned int to a
double value which causes issues for 32-bit architecture. This issue can
be fixed by changing the value type.

Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Randy Dunlap <rdunlap@infradead.org>
Fixes: 265280b99822 ("drm/amd/display: add CLKMGR changes for DCN32/321")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Tested-by: Randy Dunlap <rdunlap@infradead.org> # build-tested
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index 9ae9439c8f7b2..5d2b028e5dadf 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -208,7 +208,7 @@ struct wm_table {
 
 struct dummy_pstate_entry {
 	unsigned int dram_speed_mts;
-	unsigned int dummy_pstate_latency_us;
+	double dummy_pstate_latency_us;
 };
 
 struct clk_bw_params {
-- 
GitLab


From 202804b9705ce26788c443a54aec47eae20f4596 Mon Sep 17 00:00:00 2001
From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Date: Thu, 30 Jun 2022 14:46:20 -0400
Subject: [PATCH 1444/1731] drm/amd/display: Fix __muldf3 undefined for 32 bit
 compilation

Sometimes when trying to enable some feature, we have to define some
values with educated guesses, but we mark those values as TBD, which
means "To Be Determined". However, the correct way to approach it is by
loading that information from the firmware. Anyway, some of the values
that we were experimenting with caused this issue:

ERROR: modpost: "__muldf3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!

This commit fixes this issue by removing the division by two since it is
harmless in this case.

Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Randy Dunlap <rdunlap@infradead.org>
Fixes: 265280b99822 ("drm/amd/display: add CLKMGR changes for DCN32/321")
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Tested-by: Randy Dunlap <rdunlap@infradead.org> # build-tested
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 4e8059f200075..b49a4e34d39be 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -213,8 +213,8 @@ static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us;
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us = fclk_change_latency_us;
-	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2; // TBD
-	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us / 2; // TBD
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us; // TBD
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; // TBD
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;
-- 
GitLab


From 780f97cec866e1ec6967c66c2a1f68b8aa1e3f23 Mon Sep 17 00:00:00 2001
From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Date: Thu, 30 Jun 2022 14:46:21 -0400
Subject: [PATCH 1445/1731] drm/amd/display: Fix __nedf2 undefined for 32 bit
 compilation

When we tried to compile DCN32/321 for 32-bit architecture, we got this
error message:

ERROR: modpost: "__nedf2" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!

This commit fixes this issue by rewriting a small part of the
dcn32_build_wm_range_table.

Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Randy Dunlap <rdunlap@infradead.org>
Fixes: 265280b99822 ("drm/amd/display: add CLKMGR changes for DCN32/321")
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Tested-by: Randy Dunlap <rdunlap@infradead.org> # build-tested
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c  | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index b49a4e34d39be..1edb5aab8990f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -155,10 +155,14 @@ static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
 	uint16_t min_uclk_mhz			= clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
 	uint16_t min_dcfclk_mhz			= clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
 	uint16_t setb_min_uclk_mhz		= min_uclk_mhz;
-	uint16_t setb_min_dcfclk_mhz	= min_dcfclk_mhz;
+	uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;
+
 	/* For Set B ranges use min clocks state 2 when available, and report those to PM FW */
-	if (clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz)
-		setb_min_dcfclk_mhz = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;
+	if (dcfclk_mhz_for_the_second_state)
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state;
+	else
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
+
 	if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz)
 		setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz;
 
@@ -181,7 +185,6 @@ static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
-	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = setb_min_dcfclk_mhz;
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = setb_min_uclk_mhz;
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;
-- 
GitLab


From c5da61cf5bab30059f22ea368702c445ee87171a Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Mon, 27 Jun 2022 16:35:43 -0400
Subject: [PATCH 1446/1731] drm/amdgpu/display: add missing FP_START/END checks
 dcn32_clk_mgr.c

Properly handle FP code in dcn32_clk_mgr.c.

Fixes: 265280b99822 ("drm/amd/display: add CLKMGR changes for DCN32/321")
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 1edb5aab8990f..c0989a04d025d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -291,8 +291,10 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
 	/* Get UCLK, update bounding box */
 	clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
 
+	DC_FP_START();
 	/* WM range table */
 	dcn32_build_wm_range_table(clk_mgr);
+	DC_FP_END();
 }
 
 static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
@@ -727,9 +729,11 @@ static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
 			&num_levels);
 	clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
 
+	DC_FP_START();
 	/* Refresh bounding box */
 	clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
 			clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
+	DC_FP_END();
 }
 
 static bool dcn32_are_clock_states_equal(struct dc_clocks *a,
-- 
GitLab


From 2f446ffe9d737e9a844b97887919c4fda18246e7 Mon Sep 17 00:00:00 2001
From: Roger Pau Monne <roger.pau@citrix.com>
Date: Fri, 1 Jul 2022 08:23:54 +0200
Subject: [PATCH 1447/1731] xen/blkfront: fix leaking data in shared pages
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When allocating pages to be used for shared communication with the
backend always zero them, this avoids leaking unintended data present
on the pages.

This is CVE-2022-26365, part of XSA-403.

Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Juergen Gross <jgross@suse.com>
---
 drivers/block/xen-blkfront.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/block/xen-blkfront.c b/drivers/block/xen-blkfront.c
index 33f04ef78984c..4b3bef6ace68f 100644
--- a/drivers/block/xen-blkfront.c
+++ b/drivers/block/xen-blkfront.c
@@ -311,7 +311,7 @@ static int fill_grant_buffer(struct blkfront_ring_info *rinfo, int num)
 			goto out_of_memory;
 
 		if (info->feature_persistent) {
-			granted_page = alloc_page(GFP_NOIO);
+			granted_page = alloc_page(GFP_NOIO | __GFP_ZERO);
 			if (!granted_page) {
 				kfree(gnt_list_entry);
 				goto out_of_memory;
@@ -2183,7 +2183,8 @@ static int blkfront_setup_indirect(struct blkfront_ring_info *rinfo)
 
 		BUG_ON(!list_empty(&rinfo->indirect_pages));
 		for (i = 0; i < num; i++) {
-			struct page *indirect_page = alloc_page(GFP_KERNEL);
+			struct page *indirect_page = alloc_page(GFP_KERNEL |
+								__GFP_ZERO);
 			if (!indirect_page)
 				goto out_of_memory;
 			list_add(&indirect_page->lru, &rinfo->indirect_pages);
-- 
GitLab


From eb7f8e28420372787933eec079735c35034bda7d Mon Sep 17 00:00:00 2001
From: Shuah Khan <skhan@linuxfoundation.org>
Date: Thu, 30 Jun 2022 20:32:55 -0600
Subject: [PATCH 1448/1731] misc: rtsx_usb: fix use of dma mapped buffer for
 usb bulk transfer

rtsx_usb driver allocates coherent dma buffer for urb transfers.
This buffer is passed to usb_bulk_msg() and usb core tries to
map already mapped buffer running into a dma mapping error.

xhci_hcd 0000:01:00.0: rejecting DMA map of vmalloc memory
WARNING: CPU: 1 PID: 279 at include/linux/dma-mapping.h:326 usb_ hcd_map_urb_for_dma+0x7d6/0x820

...

xhci_map_urb_for_dma+0x291/0x4e0
usb_hcd_submit_urb+0x199/0x12b0
...
usb_submit_urb+0x3b8/0x9e0
usb_start_wait_urb+0xe3/0x2d0
usb_bulk_msg+0x115/0x240
rtsx_usb_transfer_data+0x185/0x1a8 [rtsx_usb]
rtsx_usb_send_cmd+0xbb/0x123 [rtsx_usb]
rtsx_usb_write_register+0x12c/0x143 [rtsx_usb]
rtsx_usb_probe+0x226/0x4b2 [rtsx_usb]

Fix it to use kmalloc() to get DMA-able memory region instead.

Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
Cc: stable <stable@kernel.org>
Link: https://lore.kernel.org/r/667d627d502e1ba9ff4f9b94966df3299d2d3c0d.1656642167.git.skhan@linuxfoundation.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/misc/cardreader/rtsx_usb.c | 13 +++++++------
 include/linux/rtsx_usb.h           |  1 -
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/misc/cardreader/rtsx_usb.c b/drivers/misc/cardreader/rtsx_usb.c
index 1ef9b61077c44..e147cc8ab0fdf 100644
--- a/drivers/misc/cardreader/rtsx_usb.c
+++ b/drivers/misc/cardreader/rtsx_usb.c
@@ -631,8 +631,7 @@ static int rtsx_usb_probe(struct usb_interface *intf,
 
 	ucr->pusb_dev = usb_dev;
 
-	ucr->iobuf = usb_alloc_coherent(ucr->pusb_dev, IOBUF_SIZE,
-			GFP_KERNEL, &ucr->iobuf_dma);
+	ucr->iobuf = kmalloc(IOBUF_SIZE, GFP_KERNEL);
 	if (!ucr->iobuf)
 		return -ENOMEM;
 
@@ -668,8 +667,9 @@ static int rtsx_usb_probe(struct usb_interface *intf,
 
 out_init_fail:
 	usb_set_intfdata(ucr->pusb_intf, NULL);
-	usb_free_coherent(ucr->pusb_dev, IOBUF_SIZE, ucr->iobuf,
-			ucr->iobuf_dma);
+	kfree(ucr->iobuf);
+	ucr->iobuf = NULL;
+	ucr->cmd_buf = ucr->rsp_buf = NULL;
 	return ret;
 }
 
@@ -682,8 +682,9 @@ static void rtsx_usb_disconnect(struct usb_interface *intf)
 	mfd_remove_devices(&intf->dev);
 
 	usb_set_intfdata(ucr->pusb_intf, NULL);
-	usb_free_coherent(ucr->pusb_dev, IOBUF_SIZE, ucr->iobuf,
-			ucr->iobuf_dma);
+	kfree(ucr->iobuf);
+	ucr->iobuf = NULL;
+	ucr->cmd_buf = ucr->rsp_buf = NULL;
 }
 
 #ifdef CONFIG_PM
diff --git a/include/linux/rtsx_usb.h b/include/linux/rtsx_usb.h
index 159729cffd8e1..a07f7341ebc25 100644
--- a/include/linux/rtsx_usb.h
+++ b/include/linux/rtsx_usb.h
@@ -55,7 +55,6 @@ struct rtsx_ucr {
 	struct usb_interface	*pusb_intf;
 	struct usb_sg_request	current_sg;
 	unsigned char		*iobuf;
-	dma_addr_t		iobuf_dma;
 
 	struct timer_list	sg_timer;
 	struct mutex		dev_mutex;
-- 
GitLab


From 3776c78559853fd151be7c41e369fd076fb679d5 Mon Sep 17 00:00:00 2001
From: Shuah Khan <skhan@linuxfoundation.org>
Date: Thu, 30 Jun 2022 20:32:56 -0600
Subject: [PATCH 1449/1731] misc: rtsx_usb: use separate command and response
 buffers

rtsx_usb uses same buffer for command and response. There could
be a potential conflict using the same buffer for both especially
if retries and timeouts are involved.

Use separate command and response buffers to avoid conflicts.

Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
Cc: stable <stable@kernel.org>
Link: https://lore.kernel.org/r/07e3721804ff07aaab9ef5b39a5691d0718b9ade.1656642167.git.skhan@linuxfoundation.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/misc/cardreader/rtsx_usb.c | 26 +++++++++++++++++---------
 include/linux/rtsx_usb.h           |  1 -
 2 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/drivers/misc/cardreader/rtsx_usb.c b/drivers/misc/cardreader/rtsx_usb.c
index e147cc8ab0fdf..4e21080525094 100644
--- a/drivers/misc/cardreader/rtsx_usb.c
+++ b/drivers/misc/cardreader/rtsx_usb.c
@@ -631,15 +631,18 @@ static int rtsx_usb_probe(struct usb_interface *intf,
 
 	ucr->pusb_dev = usb_dev;
 
-	ucr->iobuf = kmalloc(IOBUF_SIZE, GFP_KERNEL);
-	if (!ucr->iobuf)
+	ucr->cmd_buf = kmalloc(IOBUF_SIZE, GFP_KERNEL);
+	if (!ucr->cmd_buf)
 		return -ENOMEM;
 
+	ucr->rsp_buf = kmalloc(IOBUF_SIZE, GFP_KERNEL);
+	if (!ucr->rsp_buf)
+		goto out_free_cmd_buf;
+
 	usb_set_intfdata(intf, ucr);
 
 	ucr->vendor_id = id->idVendor;
 	ucr->product_id = id->idProduct;
-	ucr->cmd_buf = ucr->rsp_buf = ucr->iobuf;
 
 	mutex_init(&ucr->dev_mutex);
 
@@ -667,9 +670,11 @@ static int rtsx_usb_probe(struct usb_interface *intf,
 
 out_init_fail:
 	usb_set_intfdata(ucr->pusb_intf, NULL);
-	kfree(ucr->iobuf);
-	ucr->iobuf = NULL;
-	ucr->cmd_buf = ucr->rsp_buf = NULL;
+	kfree(ucr->rsp_buf);
+	ucr->rsp_buf = NULL;
+out_free_cmd_buf:
+	kfree(ucr->cmd_buf);
+	ucr->cmd_buf = NULL;
 	return ret;
 }
 
@@ -682,9 +687,12 @@ static void rtsx_usb_disconnect(struct usb_interface *intf)
 	mfd_remove_devices(&intf->dev);
 
 	usb_set_intfdata(ucr->pusb_intf, NULL);
-	kfree(ucr->iobuf);
-	ucr->iobuf = NULL;
-	ucr->cmd_buf = ucr->rsp_buf = NULL;
+
+	kfree(ucr->cmd_buf);
+	ucr->cmd_buf = NULL;
+
+	kfree(ucr->rsp_buf);
+	ucr->rsp_buf = NULL;
 }
 
 #ifdef CONFIG_PM
diff --git a/include/linux/rtsx_usb.h b/include/linux/rtsx_usb.h
index a07f7341ebc25..3247ed8e9ff0f 100644
--- a/include/linux/rtsx_usb.h
+++ b/include/linux/rtsx_usb.h
@@ -54,7 +54,6 @@ struct rtsx_ucr {
 	struct usb_device	*pusb_dev;
 	struct usb_interface	*pusb_intf;
 	struct usb_sg_request	current_sg;
-	unsigned char		*iobuf;
 
 	struct timer_list	sg_timer;
 	struct mutex		dev_mutex;
-- 
GitLab


From ee6c6e7342471d468096a16bee9f89b5a6c1e39d Mon Sep 17 00:00:00 2001
From: Davidlohr Bueso <dave@stgolabs.net>
Date: Wed, 29 Jun 2022 09:52:25 -0700
Subject: [PATCH 1450/1731] staging/wlan-ng: get the correct struct hfa384x in
 work callback

hfa384x_usbctlx_completion_task() is bogusly using the reaper BH when
in fact this is the completion_bh. This was reflected when trying
to acquire the hw->ctlxq.lock and getting a failed lockdep class
initialized to it.

Fixes: 9442e81d7e7c ("staging/wlan-ng, prism2usb: replace completion_bh tasklet with work")
Reported-by: syzbot+ce3408364c4a234dd90c@syzkaller.appspotmail.com
Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Link: https://lore.kernel.org/r/20220629165225.3436822-1-dave@stgolabs.net
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/staging/wlan-ng/hfa384x_usb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/wlan-ng/hfa384x_usb.c b/drivers/staging/wlan-ng/hfa384x_usb.c
index 33844526c7977..02fdef7a16c87 100644
--- a/drivers/staging/wlan-ng/hfa384x_usb.c
+++ b/drivers/staging/wlan-ng/hfa384x_usb.c
@@ -2632,7 +2632,7 @@ static void hfa384x_usbctlx_reaper_task(struct work_struct *work)
  */
 static void hfa384x_usbctlx_completion_task(struct work_struct *work)
 {
-	struct hfa384x *hw = container_of(work, struct hfa384x, reaper_bh);
+	struct hfa384x *hw = container_of(work, struct hfa384x, completion_bh);
 	struct hfa384x_usbctlx *ctlx, *temp;
 	unsigned long flags;
 
-- 
GitLab


From 307c8de2b02344805ebead3440d8feed28f2f010 Mon Sep 17 00:00:00 2001
From: Roger Pau Monne <roger.pau@citrix.com>
Date: Wed, 6 Apr 2022 17:38:04 +0200
Subject: [PATCH 1451/1731] xen/netfront: fix leaking data in shared pages
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When allocating pages to be used for shared communication with the
backend always zero them, this avoids leaking unintended data present
on the pages.

This is CVE-2022-33740, part of XSA-403.

Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Juergen Gross <jgross@suse.com>
---
 drivers/net/xen-netfront.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/xen-netfront.c b/drivers/net/xen-netfront.c
index 8c0b9546d5a2d..e3165139629d5 100644
--- a/drivers/net/xen-netfront.c
+++ b/drivers/net/xen-netfront.c
@@ -271,7 +271,8 @@ static struct sk_buff *xennet_alloc_one_rx_buffer(struct netfront_queue *queue)
 	if (unlikely(!skb))
 		return NULL;
 
-	page = page_pool_dev_alloc_pages(queue->page_pool);
+	page = page_pool_alloc_pages(queue->page_pool,
+				     GFP_ATOMIC | __GFP_NOWARN | __GFP_ZERO);
 	if (unlikely(!page)) {
 		kfree_skb(skb);
 		return NULL;
-- 
GitLab


From 4491001c2e0fa69efbb748c96ec96b100a5cdb7e Mon Sep 17 00:00:00 2001
From: Roger Pau Monne <roger.pau@citrix.com>
Date: Thu, 7 Apr 2022 12:20:06 +0200
Subject: [PATCH 1452/1731] xen/netfront: force data bouncing when backend is
 untrusted
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Bounce all data on the skbs to be transmitted into zeroed pages if the
backend is untrusted. This avoids leaking data present in the pages
shared with the backend but not part of the skb fragments.  This
requires introducing a new helper in order to allocate skbs with a
size multiple of XEN_PAGE_SIZE so we don't leak contiguous data on the
granted pages.

Reporting whether the backend is to be trusted can be done using a
module parameter, or from the xenstore frontend path as set by the
toolstack when adding the device.

This is CVE-2022-33741, part of XSA-403.

Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Juergen Gross <jgross@suse.com>
---
 drivers/net/xen-netfront.c | 49 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 47 insertions(+), 2 deletions(-)

diff --git a/drivers/net/xen-netfront.c b/drivers/net/xen-netfront.c
index e3165139629d5..87f6df77bfbfd 100644
--- a/drivers/net/xen-netfront.c
+++ b/drivers/net/xen-netfront.c
@@ -66,6 +66,10 @@ module_param_named(max_queues, xennet_max_queues, uint, 0644);
 MODULE_PARM_DESC(max_queues,
 		 "Maximum number of queues per virtual interface");
 
+static bool __read_mostly xennet_trusted = true;
+module_param_named(trusted, xennet_trusted, bool, 0644);
+MODULE_PARM_DESC(trusted, "Is the backend trusted");
+
 #define XENNET_TIMEOUT  (5 * HZ)
 
 static const struct ethtool_ops xennet_ethtool_ops;
@@ -173,6 +177,9 @@ struct netfront_info {
 	/* Is device behaving sane? */
 	bool broken;
 
+	/* Should skbs be bounced into a zeroed buffer? */
+	bool bounce;
+
 	atomic_t rx_gso_checksum_fixup;
 };
 
@@ -666,6 +673,33 @@ static int xennet_xdp_xmit(struct net_device *dev, int n,
 	return nxmit;
 }
 
+struct sk_buff *bounce_skb(const struct sk_buff *skb)
+{
+	unsigned int headerlen = skb_headroom(skb);
+	/* Align size to allocate full pages and avoid contiguous data leaks */
+	unsigned int size = ALIGN(skb_end_offset(skb) + skb->data_len,
+				  XEN_PAGE_SIZE);
+	struct sk_buff *n = alloc_skb(size, GFP_ATOMIC | __GFP_ZERO);
+
+	if (!n)
+		return NULL;
+
+	if (!IS_ALIGNED((uintptr_t)n->head, XEN_PAGE_SIZE)) {
+		WARN_ONCE(1, "misaligned skb allocated\n");
+		kfree_skb(n);
+		return NULL;
+	}
+
+	/* Set the data pointer */
+	skb_reserve(n, headerlen);
+	/* Set the tail pointer and length */
+	skb_put(n, skb->len);
+
+	BUG_ON(skb_copy_bits(skb, -headerlen, n->head, headerlen + skb->len));
+
+	skb_copy_header(n, skb);
+	return n;
+}
 
 #define MAX_XEN_SKB_FRAGS (65536 / XEN_PAGE_SIZE + 1)
 
@@ -719,9 +753,13 @@ static netdev_tx_t xennet_start_xmit(struct sk_buff *skb, struct net_device *dev
 
 	/* The first req should be at least ETH_HLEN size or the packet will be
 	 * dropped by netback.
+	 *
+	 * If the backend is not trusted bounce all data to zeroed pages to
+	 * avoid exposing contiguous data on the granted page not belonging to
+	 * the skb.
 	 */
-	if (unlikely(PAGE_SIZE - offset < ETH_HLEN)) {
-		nskb = skb_copy(skb, GFP_ATOMIC);
+	if (np->bounce || unlikely(PAGE_SIZE - offset < ETH_HLEN)) {
+		nskb = bounce_skb(skb);
 		if (!nskb)
 			goto drop;
 		dev_consume_skb_any(skb);
@@ -2215,6 +2253,10 @@ static int talk_to_netback(struct xenbus_device *dev,
 
 	info->netdev->irq = 0;
 
+	/* Check if backend is trusted. */
+	info->bounce = !xennet_trusted ||
+		       !xenbus_read_unsigned(dev->nodename, "trusted", 1);
+
 	/* Check if backend supports multiple queues */
 	max_queues = xenbus_read_unsigned(info->xbdev->otherend,
 					  "multi-queue-max-queues", 1);
@@ -2382,6 +2424,9 @@ static int xennet_connect(struct net_device *dev)
 		return err;
 	if (np->netback_has_xdp_headroom)
 		pr_info("backend supports XDP headroom\n");
+	if (np->bounce)
+		dev_info(&np->xbdev->dev,
+			 "bouncing transmitted data to zeroed pages\n");
 
 	/* talk_to_netback() sets the correct number of queues */
 	num_queues = dev->real_num_tx_queues;
-- 
GitLab


From 2400617da7eebf9167d71a46122828bc479d64c9 Mon Sep 17 00:00:00 2001
From: Roger Pau Monne <roger.pau@citrix.com>
Date: Thu, 7 Apr 2022 13:04:24 +0200
Subject: [PATCH 1453/1731] xen/blkfront: force data bouncing when backend is
 untrusted
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Split the current bounce buffering logic used with persistent grants
into it's own option, and allow enabling it independently of
persistent grants.  This allows to reuse the same code paths to
perform the bounce buffering required to avoid leaking contiguous data
in shared pages not part of the request fragments.

Reporting whether the backend is to be trusted can be done using a
module parameter, or from the xenstore frontend path as set by the
toolstack when adding the device.

This is CVE-2022-33742, part of XSA-403.

Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Juergen Gross <jgross@suse.com>
---
 drivers/block/xen-blkfront.c | 49 +++++++++++++++++++++++++-----------
 1 file changed, 34 insertions(+), 15 deletions(-)

diff --git a/drivers/block/xen-blkfront.c b/drivers/block/xen-blkfront.c
index 4b3bef6ace68f..3646c0cae672a 100644
--- a/drivers/block/xen-blkfront.c
+++ b/drivers/block/xen-blkfront.c
@@ -152,6 +152,10 @@ static unsigned int xen_blkif_max_ring_order;
 module_param_named(max_ring_page_order, xen_blkif_max_ring_order, int, 0444);
 MODULE_PARM_DESC(max_ring_page_order, "Maximum order of pages to be used for the shared ring");
 
+static bool __read_mostly xen_blkif_trusted = true;
+module_param_named(trusted, xen_blkif_trusted, bool, 0644);
+MODULE_PARM_DESC(trusted, "Is the backend trusted");
+
 #define BLK_RING_SIZE(info)	\
 	__CONST_RING_SIZE(blkif, XEN_PAGE_SIZE * (info)->nr_ring_pages)
 
@@ -210,6 +214,7 @@ struct blkfront_info
 	unsigned int feature_discard:1;
 	unsigned int feature_secdiscard:1;
 	unsigned int feature_persistent:1;
+	unsigned int bounce:1;
 	unsigned int discard_granularity;
 	unsigned int discard_alignment;
 	/* Number of 4KB segments handled */
@@ -310,7 +315,7 @@ static int fill_grant_buffer(struct blkfront_ring_info *rinfo, int num)
 		if (!gnt_list_entry)
 			goto out_of_memory;
 
-		if (info->feature_persistent) {
+		if (info->bounce) {
 			granted_page = alloc_page(GFP_NOIO | __GFP_ZERO);
 			if (!granted_page) {
 				kfree(gnt_list_entry);
@@ -330,7 +335,7 @@ out_of_memory:
 	list_for_each_entry_safe(gnt_list_entry, n,
 	                         &rinfo->grants, node) {
 		list_del(&gnt_list_entry->node);
-		if (info->feature_persistent)
+		if (info->bounce)
 			__free_page(gnt_list_entry->page);
 		kfree(gnt_list_entry);
 		i--;
@@ -376,7 +381,7 @@ static struct grant *get_grant(grant_ref_t *gref_head,
 	/* Assign a gref to this page */
 	gnt_list_entry->gref = gnttab_claim_grant_reference(gref_head);
 	BUG_ON(gnt_list_entry->gref == -ENOSPC);
-	if (info->feature_persistent)
+	if (info->bounce)
 		grant_foreign_access(gnt_list_entry, info);
 	else {
 		/* Grant access to the GFN passed by the caller */
@@ -400,7 +405,7 @@ static struct grant *get_indirect_grant(grant_ref_t *gref_head,
 	/* Assign a gref to this page */
 	gnt_list_entry->gref = gnttab_claim_grant_reference(gref_head);
 	BUG_ON(gnt_list_entry->gref == -ENOSPC);
-	if (!info->feature_persistent) {
+	if (!info->bounce) {
 		struct page *indirect_page;
 
 		/* Fetch a pre-allocated page to use for indirect grefs */
@@ -703,7 +708,7 @@ static int blkif_queue_rw_req(struct request *req, struct blkfront_ring_info *ri
 		.grant_idx = 0,
 		.segments = NULL,
 		.rinfo = rinfo,
-		.need_copy = rq_data_dir(req) && info->feature_persistent,
+		.need_copy = rq_data_dir(req) && info->bounce,
 	};
 
 	/*
@@ -981,11 +986,12 @@ static void xlvbd_flush(struct blkfront_info *info)
 {
 	blk_queue_write_cache(info->rq, info->feature_flush ? true : false,
 			      info->feature_fua ? true : false);
-	pr_info("blkfront: %s: %s %s %s %s %s\n",
+	pr_info("blkfront: %s: %s %s %s %s %s %s %s\n",
 		info->gd->disk_name, flush_info(info),
 		"persistent grants:", info->feature_persistent ?
 		"enabled;" : "disabled;", "indirect descriptors:",
-		info->max_indirect_segments ? "enabled;" : "disabled;");
+		info->max_indirect_segments ? "enabled;" : "disabled;",
+		"bounce buffer:", info->bounce ? "enabled" : "disabled;");
 }
 
 static int xen_translate_vdev(int vdevice, int *minor, unsigned int *offset)
@@ -1207,7 +1213,7 @@ static void blkif_free_ring(struct blkfront_ring_info *rinfo)
 	if (!list_empty(&rinfo->indirect_pages)) {
 		struct page *indirect_page, *n;
 
-		BUG_ON(info->feature_persistent);
+		BUG_ON(info->bounce);
 		list_for_each_entry_safe(indirect_page, n, &rinfo->indirect_pages, lru) {
 			list_del(&indirect_page->lru);
 			__free_page(indirect_page);
@@ -1224,7 +1230,7 @@ static void blkif_free_ring(struct blkfront_ring_info *rinfo)
 							  NULL);
 				rinfo->persistent_gnts_c--;
 			}
-			if (info->feature_persistent)
+			if (info->bounce)
 				__free_page(persistent_gnt->page);
 			kfree(persistent_gnt);
 		}
@@ -1245,7 +1251,7 @@ static void blkif_free_ring(struct blkfront_ring_info *rinfo)
 		for (j = 0; j < segs; j++) {
 			persistent_gnt = rinfo->shadow[i].grants_used[j];
 			gnttab_end_foreign_access(persistent_gnt->gref, NULL);
-			if (info->feature_persistent)
+			if (info->bounce)
 				__free_page(persistent_gnt->page);
 			kfree(persistent_gnt);
 		}
@@ -1428,7 +1434,7 @@ static int blkif_completion(unsigned long *id,
 	data.s = s;
 	num_sg = s->num_sg;
 
-	if (bret->operation == BLKIF_OP_READ && info->feature_persistent) {
+	if (bret->operation == BLKIF_OP_READ && info->bounce) {
 		for_each_sg(s->sg, sg, num_sg, i) {
 			BUG_ON(sg->offset + sg->length > PAGE_SIZE);
 
@@ -1487,7 +1493,7 @@ static int blkif_completion(unsigned long *id,
 				 * Add the used indirect page back to the list of
 				 * available pages for indirect grefs.
 				 */
-				if (!info->feature_persistent) {
+				if (!info->bounce) {
 					indirect_page = s->indirect_grants[i]->page;
 					list_add(&indirect_page->lru, &rinfo->indirect_pages);
 				}
@@ -1764,6 +1770,10 @@ static int talk_to_blkback(struct xenbus_device *dev,
 	if (!info)
 		return -ENODEV;
 
+	/* Check if backend is trusted. */
+	info->bounce = !xen_blkif_trusted ||
+		       !xenbus_read_unsigned(dev->nodename, "trusted", 1);
+
 	max_page_order = xenbus_read_unsigned(info->xbdev->otherend,
 					      "max-ring-page-order", 0);
 	ring_page_order = min(xen_blkif_max_ring_order, max_page_order);
@@ -2173,10 +2183,10 @@ static int blkfront_setup_indirect(struct blkfront_ring_info *rinfo)
 	if (err)
 		goto out_of_memory;
 
-	if (!info->feature_persistent && info->max_indirect_segments) {
+	if (!info->bounce && info->max_indirect_segments) {
 		/*
-		 * We are using indirect descriptors but not persistent
-		 * grants, we need to allocate a set of pages that can be
+		 * We are using indirect descriptors but don't have a bounce
+		 * buffer, we need to allocate a set of pages that can be
 		 * used for mapping indirect grefs
 		 */
 		int num = INDIRECT_GREFS(grants) * BLK_RING_SIZE(info);
@@ -2277,6 +2287,8 @@ static void blkfront_gather_backend_features(struct blkfront_info *info)
 		info->feature_persistent =
 			!!xenbus_read_unsigned(info->xbdev->otherend,
 					       "feature-persistent", 0);
+	if (info->feature_persistent)
+		info->bounce = true;
 
 	indirect_segments = xenbus_read_unsigned(info->xbdev->otherend,
 					"feature-max-indirect-segments", 0);
@@ -2548,6 +2560,13 @@ static void blkfront_delay_work(struct work_struct *work)
 	struct blkfront_info *info;
 	bool need_schedule_work = false;
 
+	/*
+	 * Note that when using bounce buffers but not persistent grants
+	 * there's no need to run blkfront_delay_work because grants are
+	 * revoked in blkif_completion or else an error is reported and the
+	 * connection is closed.
+	 */
+
 	mutex_lock(&blkfront_mutex);
 
 	list_for_each_entry(info, &info_list, info_list) {
-- 
GitLab


From f63c2c2032c2e3caad9add3b82cc6e91c376fd26 Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Fri, 1 Jul 2022 08:56:52 +0200
Subject: [PATCH 1454/1731] xen-netfront: restore __skb_queue_tail()
 positioning in xennet_get_responses()

The commit referenced below moved the invocation past the "next" label,
without any explanation. In fact this allows misbehaving backends undue
control over the domain the frontend runs in, as earlier detected errors
require the skb to not be freed (it may be retained for later processing
via xennet_move_rx_slot(), or it may simply be unsafe to have it freed).

This is CVE-2022-33743 / XSA-405.

Fixes: 6c5aa6fc4def ("xen networking: add basic XDP support for xen-netfront")
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Juergen Gross <jgross@suse.com>
---
 drivers/net/xen-netfront.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/xen-netfront.c b/drivers/net/xen-netfront.c
index 87f6df77bfbfd..2409007f1fd96 100644
--- a/drivers/net/xen-netfront.c
+++ b/drivers/net/xen-netfront.c
@@ -1092,8 +1092,10 @@ static int xennet_get_responses(struct netfront_queue *queue,
 			}
 		}
 		rcu_read_unlock();
-next:
+
 		__skb_queue_tail(list, skb);
+
+next:
 		if (!(rx->flags & XEN_NETRXF_more_data))
 			break;
 
-- 
GitLab


From b75cd218274e01d026dc5240e86fdeb44bbed0c8 Mon Sep 17 00:00:00 2001
From: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>
Date: Fri, 1 Jul 2022 08:57:44 +0200
Subject: [PATCH 1455/1731] xen/arm: Fix race in RB-tree based P2M accounting

During the PV driver life cycle the mappings are added to
the RB-tree by set_foreign_p2m_mapping(), which is called from
gnttab_map_refs() and are removed by clear_foreign_p2m_mapping()
which is called from gnttab_unmap_refs(). As both functions end
up calling __set_phys_to_machine_multi() which updates the RB-tree,
this function can be called concurrently.

There is already a "p2m_lock" to protect against concurrent accesses,
but the problem is that the first read of "phys_to_mach.rb_node"
in __set_phys_to_machine_multi() is not covered by it, so this might
lead to the incorrect mappings update (removing in our case) in RB-tree.

In my environment the related issue happens rarely and only when
PV net backend is running, the xen_add_phys_to_mach_entry() claims
that it cannot add new pfn <-> mfn mapping to the tree since it is
already exists which results in a failure when mapping foreign pages.

But there might be other bad consequences related to the non-protected
root reads such use-after-free, etc.

While at it, also fix the similar usage in __pfn_to_mfn(), so
initialize "struct rb_node *n" with the "p2m_lock" held in both
functions to avoid possible bad consequences.

This is CVE-2022-33744 / XSA-406.

Signed-off-by: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Signed-off-by: Juergen Gross <jgross@suse.com>
---
 arch/arm/xen/p2m.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/xen/p2m.c b/arch/arm/xen/p2m.c
index 84a1cea1f43b9..309648c17f486 100644
--- a/arch/arm/xen/p2m.c
+++ b/arch/arm/xen/p2m.c
@@ -63,11 +63,12 @@ out:
 
 unsigned long __pfn_to_mfn(unsigned long pfn)
 {
-	struct rb_node *n = phys_to_mach.rb_node;
+	struct rb_node *n;
 	struct xen_p2m_entry *entry;
 	unsigned long irqflags;
 
 	read_lock_irqsave(&p2m_lock, irqflags);
+	n = phys_to_mach.rb_node;
 	while (n) {
 		entry = rb_entry(n, struct xen_p2m_entry, rbnode_phys);
 		if (entry->pfn <= pfn &&
@@ -152,10 +153,11 @@ bool __set_phys_to_machine_multi(unsigned long pfn,
 	int rc;
 	unsigned long irqflags;
 	struct xen_p2m_entry *p2m_entry;
-	struct rb_node *n = phys_to_mach.rb_node;
+	struct rb_node *n;
 
 	if (mfn == INVALID_P2M_ENTRY) {
 		write_lock_irqsave(&p2m_lock, irqflags);
+		n = phys_to_mach.rb_node;
 		while (n) {
 			p2m_entry = rb_entry(n, struct xen_p2m_entry, rbnode_phys);
 			if (p2m_entry->pfn <= pfn &&
-- 
GitLab


From 96e8fc5818686d4a1591bb6907e7fdb64ef29884 Mon Sep 17 00:00:00 2001
From: Juergen Gross <jgross@suse.com>
Date: Thu, 30 Jun 2022 09:14:39 +0200
Subject: [PATCH 1456/1731] x86/xen: Use clear_bss() for Xen PV guests

Instead of clearing the bss area in assembly code, use the clear_bss()
function.

This requires to pass the start_info address as parameter to
xen_start_kernel() in order to avoid the xen_start_info being zeroed
again.

Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Link: https://lore.kernel.org/r/20220630071441.28576-2-jgross@suse.com
---
 arch/x86/include/asm/setup.h |  3 +++
 arch/x86/kernel/head64.c     |  2 +-
 arch/x86/xen/enlighten_pv.c  |  8 ++++++--
 arch/x86/xen/xen-head.S      | 10 +---------
 4 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h
index f8b9ee97a8913..f37cbff7354c4 100644
--- a/arch/x86/include/asm/setup.h
+++ b/arch/x86/include/asm/setup.h
@@ -120,6 +120,9 @@ void *extend_brk(size_t size, size_t align);
 	static char __brk_##name[size]
 
 extern void probe_roms(void);
+
+void clear_bss(void);
+
 #ifdef __i386__
 
 asmlinkage void __init i386_start_kernel(void);
diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
index bd4a34100ed0c..e7e233209a8ca 100644
--- a/arch/x86/kernel/head64.c
+++ b/arch/x86/kernel/head64.c
@@ -426,7 +426,7 @@ void __init do_early_exception(struct pt_regs *regs, int trapnr)
 
 /* Don't add a printk in there. printk relies on the PDA which is not initialized 
    yet. */
-static void __init clear_bss(void)
+void __init clear_bss(void)
 {
 	memset(__bss_start, 0,
 	       (unsigned long) __bss_stop - (unsigned long) __bss_start);
diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c
index e3297b15701c6..70fb2ea85e907 100644
--- a/arch/x86/xen/enlighten_pv.c
+++ b/arch/x86/xen/enlighten_pv.c
@@ -1183,15 +1183,19 @@ static void __init xen_domu_set_legacy_features(void)
 extern void early_xen_iret_patch(void);
 
 /* First C function to be called on Xen boot */
-asmlinkage __visible void __init xen_start_kernel(void)
+asmlinkage __visible void __init xen_start_kernel(struct start_info *si)
 {
 	struct physdev_set_iopl set_iopl;
 	unsigned long initrd_start = 0;
 	int rc;
 
-	if (!xen_start_info)
+	if (!si)
 		return;
 
+	clear_bss();
+
+	xen_start_info = si;
+
 	__text_gen_insn(&early_xen_iret_patch,
 			JMP32_INSN_OPCODE, &early_xen_iret_patch, &xen_iret,
 			JMP32_INSN_SIZE);
diff --git a/arch/x86/xen/xen-head.S b/arch/x86/xen/xen-head.S
index 3a2cd93bf0590..13af6fe453e3f 100644
--- a/arch/x86/xen/xen-head.S
+++ b/arch/x86/xen/xen-head.S
@@ -48,15 +48,6 @@ SYM_CODE_START(startup_xen)
 	ANNOTATE_NOENDBR
 	cld
 
-	/* Clear .bss */
-	xor %eax,%eax
-	mov $__bss_start, %rdi
-	mov $__bss_stop, %rcx
-	sub %rdi, %rcx
-	shr $3, %rcx
-	rep stosq
-
-	mov %rsi, xen_start_info
 	mov initial_stack(%rip), %rsp
 
 	/* Set up %gs.
@@ -71,6 +62,7 @@ SYM_CODE_START(startup_xen)
 	cdq
 	wrmsr
 
+	mov	%rsi, %rdi
 	call xen_start_kernel
 SYM_CODE_END(startup_xen)
 	__FINIT
-- 
GitLab


From 38fa5479b41376dc9d7f57e71c83514285a25ca0 Mon Sep 17 00:00:00 2001
From: Juergen Gross <jgross@suse.com>
Date: Thu, 30 Jun 2022 09:14:40 +0200
Subject: [PATCH 1457/1731] x86: Clear .brk area at early boot

The .brk section has the same properties as .bss: it is an alloc-only
section and should be cleared before being used.

Not doing so is especially a problem for Xen PV guests, as the
hypervisor will validate page tables (check for writable page tables
and hypervisor private bits) before accepting them to be used.

Make sure .brk is initially zero by letting clear_bss() clear the brk
area, too.

Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20220630071441.28576-3-jgross@suse.com
---
 arch/x86/kernel/head64.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
index e7e233209a8ca..6a3cfaf6b72ad 100644
--- a/arch/x86/kernel/head64.c
+++ b/arch/x86/kernel/head64.c
@@ -430,6 +430,8 @@ void __init clear_bss(void)
 {
 	memset(__bss_start, 0,
 	       (unsigned long) __bss_stop - (unsigned long) __bss_start);
+	memset(__brk_base, 0,
+	       (unsigned long) __brk_limit - (unsigned long) __brk_base);
 }
 
 static unsigned long get_cmd_line_ptr(void)
-- 
GitLab


From 7e09ac27f43b382f5fe9bb7c7f4c465ece1f8a23 Mon Sep 17 00:00:00 2001
From: Juergen Gross <jgross@suse.com>
Date: Thu, 30 Jun 2022 09:14:41 +0200
Subject: [PATCH 1458/1731] x86: Fix .brk attribute in linker script

Commit in Fixes added the "NOLOAD" attribute to the .brk section as a
"failsafe" measure.

Unfortunately, this leads to the linker no longer covering the .brk
section in a program header, resulting in the kernel loader not knowing
that the memory for the .brk section must be reserved.

This has led to crashes when loading the kernel as PV dom0 under Xen,
but other scenarios could be hit by the same problem (e.g. in case an
uncompressed kernel is used and the initrd is placed directly behind
it).

So drop the "NOLOAD" attribute. This has been verified to correctly
cover the .brk section by a program header of the resulting ELF file.

Fixes: e32683c6f7d2 ("x86/mm: Fix RESERVE_BRK() for older binutils")
Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Josh Poimboeuf <jpoimboe@kernel.org>
Link: https://lore.kernel.org/r/20220630071441.28576-4-jgross@suse.com
---
 arch/x86/kernel/vmlinux.lds.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S
index 81aba718ecd56..9487ce8c13eeb 100644
--- a/arch/x86/kernel/vmlinux.lds.S
+++ b/arch/x86/kernel/vmlinux.lds.S
@@ -385,7 +385,7 @@ SECTIONS
 	__end_of_kernel_reserve = .;
 
 	. = ALIGN(PAGE_SIZE);
-	.brk (NOLOAD) : AT(ADDR(.brk) - LOAD_OFFSET) {
+	.brk : AT(ADDR(.brk) - LOAD_OFFSET) {
 		__brk_base = .;
 		. += 64 * 1024;		/* 64k alignment slop space */
 		*(.bss..brk)		/* areas brk users have reserved */
-- 
GitLab


From 0ac9c3dd0d6fe293cd5044cfad10bec27d171e4e Mon Sep 17 00:00:00 2001
From: Caleb Connolly <caleb.connolly@linaro.org>
Date: Wed, 29 Jun 2022 15:06:00 +0100
Subject: [PATCH 1459/1731] dmaengine: qcom: bam_dma: fix runtime PM underflow

Commit dbad41e7bb5f ("dmaengine: qcom: bam_dma: check if the runtime pm enabled")
caused unbalanced pm_runtime_get/put() calls when the bam is
controlled remotely. This commit reverts it and just enables pm_runtime
in all cases, the clk_* functions already just nop when the clock is NULL.

Also clean up a bit by removing unnecessary bamclk null checks.

Suggested-by: Stephan Gerhold <stephan@gerhold.net>
Fixes: dbad41e7bb5f ("dmaengine: qcom: bam_dma: check if the runtime pm enabled")
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20220629140559.118537-1-caleb.connolly@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/dma/qcom/bam_dma.c | 39 +++++++++++---------------------------
 1 file changed, 11 insertions(+), 28 deletions(-)

diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c
index 87f6ca1541cff..2ff787df513e6 100644
--- a/drivers/dma/qcom/bam_dma.c
+++ b/drivers/dma/qcom/bam_dma.c
@@ -558,14 +558,6 @@ static int bam_alloc_chan(struct dma_chan *chan)
 	return 0;
 }
 
-static int bam_pm_runtime_get_sync(struct device *dev)
-{
-	if (pm_runtime_enabled(dev))
-		return pm_runtime_get_sync(dev);
-
-	return 0;
-}
-
 /**
  * bam_free_chan - Frees dma resources associated with specific channel
  * @chan: specified channel
@@ -581,7 +573,7 @@ static void bam_free_chan(struct dma_chan *chan)
 	unsigned long flags;
 	int ret;
 
-	ret = bam_pm_runtime_get_sync(bdev->dev);
+	ret = pm_runtime_get_sync(bdev->dev);
 	if (ret < 0)
 		return;
 
@@ -784,7 +776,7 @@ static int bam_pause(struct dma_chan *chan)
 	unsigned long flag;
 	int ret;
 
-	ret = bam_pm_runtime_get_sync(bdev->dev);
+	ret = pm_runtime_get_sync(bdev->dev);
 	if (ret < 0)
 		return ret;
 
@@ -810,7 +802,7 @@ static int bam_resume(struct dma_chan *chan)
 	unsigned long flag;
 	int ret;
 
-	ret = bam_pm_runtime_get_sync(bdev->dev);
+	ret = pm_runtime_get_sync(bdev->dev);
 	if (ret < 0)
 		return ret;
 
@@ -919,7 +911,7 @@ static irqreturn_t bam_dma_irq(int irq, void *data)
 	if (srcs & P_IRQ)
 		tasklet_schedule(&bdev->task);
 
-	ret = bam_pm_runtime_get_sync(bdev->dev);
+	ret = pm_runtime_get_sync(bdev->dev);
 	if (ret < 0)
 		return IRQ_NONE;
 
@@ -1037,7 +1029,7 @@ static void bam_start_dma(struct bam_chan *bchan)
 	if (!vd)
 		return;
 
-	ret = bam_pm_runtime_get_sync(bdev->dev);
+	ret = pm_runtime_get_sync(bdev->dev);
 	if (ret < 0)
 		return;
 
@@ -1374,11 +1366,6 @@ static int bam_dma_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_unregister_dma;
 
-	if (!bdev->bamclk) {
-		pm_runtime_disable(&pdev->dev);
-		return 0;
-	}
-
 	pm_runtime_irq_safe(&pdev->dev);
 	pm_runtime_set_autosuspend_delay(&pdev->dev, BAM_DMA_AUTOSUSPEND_DELAY);
 	pm_runtime_use_autosuspend(&pdev->dev);
@@ -1462,10 +1449,8 @@ static int __maybe_unused bam_dma_suspend(struct device *dev)
 {
 	struct bam_device *bdev = dev_get_drvdata(dev);
 
-	if (bdev->bamclk) {
-		pm_runtime_force_suspend(dev);
-		clk_unprepare(bdev->bamclk);
-	}
+	pm_runtime_force_suspend(dev);
+	clk_unprepare(bdev->bamclk);
 
 	return 0;
 }
@@ -1475,13 +1460,11 @@ static int __maybe_unused bam_dma_resume(struct device *dev)
 	struct bam_device *bdev = dev_get_drvdata(dev);
 	int ret;
 
-	if (bdev->bamclk) {
-		ret = clk_prepare(bdev->bamclk);
-		if (ret)
-			return ret;
+	ret = clk_prepare(bdev->bamclk);
+	if (ret)
+		return ret;
 
-		pm_runtime_force_resume(dev);
-	}
+	pm_runtime_force_resume(dev);
 
 	return 0;
 }
-- 
GitLab


From 44c4237cf3436bda2b185ff728123651ad133f69 Mon Sep 17 00:00:00 2001
From: Dave Jiang <dave.jiang@intel.com>
Date: Tue, 28 Jun 2022 16:00:56 -0700
Subject: [PATCH 1460/1731] dmaengine: idxd: force wq context cleanup on device
 disable path

Testing shown that when a wq mode is setup to be dedicated and then torn
down and reconfigured to shared, the wq configured end up being dedicated
anyays. The root cause is when idxd_device_wqs_clear_state() gets called
during idxd_driver removal, idxd_wq_disable_cleanup() does not get called
vs when the wq driver is removed first. The check of wq state being
"enabled" causes the cleanup to be bypassed. However, idxd_driver->remove()
releases all wq drivers. So the wqs goes to "disabled" state and will never
be "enabled". By that point, the driver has no idea if the wq was
previously configured or clean. So force call idxd_wq_disable_cleanup() on
all wqs always to make sure everything gets cleaned up.

Reported-by: Tony Zhu <tony.zhu@intel.com>
Tested-by: Tony Zhu <tony.zhu@intel.com>
Fixes: 0dcfe41e9a4c ("dmanegine: idxd: cleanup all device related bits after disabling device")
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Co-developed-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Link: https://lore.kernel.org/r/20220628230056.2527816-1-fenghua.yu@intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/dma/idxd/device.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/dma/idxd/device.c b/drivers/dma/idxd/device.c
index ff0ea60051f0c..5a8cc52c1abfd 100644
--- a/drivers/dma/idxd/device.c
+++ b/drivers/dma/idxd/device.c
@@ -716,10 +716,7 @@ static void idxd_device_wqs_clear_state(struct idxd_device *idxd)
 		struct idxd_wq *wq = idxd->wqs[i];
 
 		mutex_lock(&wq->wq_lock);
-		if (wq->state == IDXD_WQ_ENABLED) {
-			idxd_wq_disable_cleanup(wq);
-			wq->state = IDXD_WQ_DISABLED;
-		}
+		idxd_wq_disable_cleanup(wq);
 		idxd_wq_device_reset_cleanup(wq);
 		mutex_unlock(&wq->wq_lock);
 	}
-- 
GitLab


From 49db68d45bdcad06e28a420d5d911e4178389666 Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <kernel@esmil.dk>
Date: Mon, 27 Jun 2022 11:09:39 +0200
Subject: [PATCH 1461/1731] dmaengine: dw-axi-dmac: Fix RMW on channel suspend
 register

When the DMA is configured for more than 8 channels the bits controlling
suspend moves to another register. However when adding support for this
the new register would be completely overwritten in one case and
overwritten with values from the old register in another case.

Found by comparing the parallel implementation of more than 8 channel
support for the StarFive JH7100 SoC by Samin.

Fixes: 824351668a41 ("dmaengine: dw-axi-dmac: support DMAX_NUM_CHANNELS > 8")
Co-developed-by: Samin Guo <samin.guo@starfivetech.com>
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Link: https://lore.kernel.org/r/20220627090939.1775717-1-emil.renner.berthing@canonical.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index e9c9bcb1f5c20..c741da02b67e9 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -1164,8 +1164,9 @@ static int dma_chan_pause(struct dma_chan *dchan)
 			BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT;
 		axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
 	} else {
-		val = BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT |
-		      BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT;
+		val = axi_dma_ioread32(chan->chip, DMAC_CHSUSPREG);
+		val |= BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT |
+			BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT;
 		axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val);
 	}
 
@@ -1190,12 +1191,13 @@ static inline void axi_chan_resume(struct axi_dma_chan *chan)
 {
 	u32 val;
 
-	val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
 	if (chan->chip->dw->hdata->reg_map_8_channels) {
+		val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
 		val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT);
 		val |=  (BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT);
 		axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
 	} else {
+		val = axi_dma_ioread32(chan->chip, DMAC_CHSUSPREG);
 		val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT);
 		val |=  (BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT);
 		axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val);
-- 
GitLab


From 8dfeee9dc52cb979cf520f6b345e7baa6b29ecb4 Mon Sep 17 00:00:00 2001
From: Li kunyu <kunyu@nfschina.com>
Date: Fri, 1 Jul 2022 14:47:23 +0800
Subject: [PATCH 1462/1731] net: usb: Fix typo in code

Remove the repeated ';' from code.

Signed-off-by: Li kunyu <kunyu@nfschina.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/usb/catc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/usb/catc.c b/drivers/net/usb/catc.c
index e7fe9c0f63a9f..1a376ed45d7ac 100644
--- a/drivers/net/usb/catc.c
+++ b/drivers/net/usb/catc.c
@@ -781,7 +781,7 @@ static int catc_probe(struct usb_interface *intf, const struct usb_device_id *id
 			intf->altsetting->desc.bInterfaceNumber, 1)) {
 		dev_err(dev, "Can't set altsetting 1.\n");
 		ret = -EIO;
-		goto fail_mem;;
+		goto fail_mem;
 	}
 
 	netdev = alloc_etherdev(sizeof(struct catc));
-- 
GitLab


From 620f83b8326ce9706b1118334f0257ae028ce045 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Sun, 26 Jun 2022 09:43:15 +0200
Subject: [PATCH 1463/1731] soc: ixp4xx/npe: Fix unused match warning

The kernel test robot found this inconsistency:

  drivers/soc/ixp4xx/ixp4xx-npe.c:737:34: warning:
  'ixp4xx_npe_of_match' defined but not used [-Wunused-const-variable=]
     737 | static const struct of_device_id ixp4xx_npe_of_match[] = {

This is because the match is enclosed in the of_match_ptr()
which compiles into NULL when OF is disabled and this
is unnecessary.

Fix it by dropping of_match_ptr() around the match.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20220626074315.61209-1-linus.walleij@linaro.org'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 drivers/soc/ixp4xx/ixp4xx-npe.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/ixp4xx/ixp4xx-npe.c b/drivers/soc/ixp4xx/ixp4xx-npe.c
index 613935cb6a488..58240e320c132 100644
--- a/drivers/soc/ixp4xx/ixp4xx-npe.c
+++ b/drivers/soc/ixp4xx/ixp4xx-npe.c
@@ -758,7 +758,7 @@ static const struct of_device_id ixp4xx_npe_of_match[] = {
 static struct platform_driver ixp4xx_npe_driver = {
 	.driver = {
 		.name           = "ixp4xx-npe",
-		.of_match_table = of_match_ptr(ixp4xx_npe_of_match),
+		.of_match_table = ixp4xx_npe_of_match,
 	},
 	.probe = ixp4xx_npe_probe,
 	.remove = ixp4xx_npe_remove,
-- 
GitLab


From fd31000d58f41588fa10128278efdab8474f5ce8 Mon Sep 17 00:00:00 2001
From: Jamie Iles <jamie@jamieiles.com>
Date: Thu, 30 Jun 2022 12:10:08 +0100
Subject: [PATCH 1464/1731] irqchip/xilinx: Add explicit dependency on
 OF_ADDRESS

Commit b84dc7f0e364 ("irqchip/xilinx: Remove microblaze+zynq
dependency") relaxed the dependencies on the Xilinx interrupt controller
to be OF only, but some OF architectures (s390 for example) do not
support OF_ADDRESS and so a build of the driver will result in undefined
references to of_iomap/iounmap and friends.

Fixes: b84dc7f0e364 ("irqchip/xilinx: Remove microblaze+zynq dependency")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220630111008.3838307-1-jamie@jamieiles.com
---
 drivers/irqchip/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 1f23a6be7d882..bbb11cb8b0f73 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -298,7 +298,7 @@ config XTENSA_MX
 
 config XILINX_INTC
 	bool "Xilinx Interrupt Controller IP"
-	depends on OF
+	depends on OF_ADDRESS
 	select IRQ_DOMAIN
 	help
 	  Support for the Xilinx Interrupt Controller IP core.
-- 
GitLab


From 1357d2a65601bc0afb221672d5a8f1649063a141 Mon Sep 17 00:00:00 2001
From: Wei Yongjun <weiyongjun1@huawei.com>
Date: Sat, 18 Jun 2022 07:28:24 +0000
Subject: [PATCH 1465/1731] irqchip/apple-aic: Make symbol 'use_fast_ipi'
 static

The sparse tool complains as follows:

drivers/irqchip/irq-apple-aic.c:231:1: warning:
 symbol 'use_fast_ipi' was not declared. Should it be static?

This symbol is not used outside of irq-apple-aic.c, so marks it static.

Fixes: 2cf68211664a ("irqchip/apple-aic: Add Fast IPI support")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Reviewed-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220618072824.562350-1-weiyongjun1@huawei.com
---
 drivers/irqchip/irq-apple-aic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-aic.c
index 5ac83185ff479..1c2813ad8bbe2 100644
--- a/drivers/irqchip/irq-apple-aic.c
+++ b/drivers/irqchip/irq-apple-aic.c
@@ -228,7 +228,7 @@
 #define AIC_TMR_EL02_PHYS	AIC_TMR_GUEST_PHYS
 #define AIC_TMR_EL02_VIRT	AIC_TMR_GUEST_VIRT
 
-DEFINE_STATIC_KEY_TRUE(use_fast_ipi);
+static DEFINE_STATIC_KEY_TRUE(use_fast_ipi);
 
 struct aic_info {
 	int version;
-- 
GitLab


From 7561cea5dbb97fecb952548a0fb74fb105bf4664 Mon Sep 17 00:00:00 2001
From: "Darrick J. Wong" <djwong@kernel.org>
Date: Fri, 1 Jul 2022 09:08:33 -0700
Subject: [PATCH 1466/1731] xfs: prevent a UAF when log IO errors race with
 unmount

KASAN reported the following use after free bug when running
generic/475:

 XFS (dm-0): Mounting V5 Filesystem
 XFS (dm-0): Starting recovery (logdev: internal)
 XFS (dm-0): Ending recovery (logdev: internal)
 Buffer I/O error on dev dm-0, logical block 20639616, async page read
 Buffer I/O error on dev dm-0, logical block 20639617, async page read
 XFS (dm-0): log I/O error -5
 XFS (dm-0): Filesystem has been shut down due to log error (0x2).
 XFS (dm-0): Unmounting Filesystem
 XFS (dm-0): Please unmount the filesystem and rectify the problem(s).
 ==================================================================
 BUG: KASAN: use-after-free in do_raw_spin_lock+0x246/0x270
 Read of size 4 at addr ffff888109dd84c4 by task 3:1H/136

 CPU: 3 PID: 136 Comm: 3:1H Not tainted 5.19.0-rc4-xfsx #rc4 8e53ab5ad0fddeb31cee5e7063ff9c361915a9c4
 Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS 1.15.0-1 04/01/2014
 Workqueue: xfs-log/dm-0 xlog_ioend_work [xfs]
 Call Trace:
  <TASK>
  dump_stack_lvl+0x34/0x44
  print_report.cold+0x2b8/0x661
  ? do_raw_spin_lock+0x246/0x270
  kasan_report+0xab/0x120
  ? do_raw_spin_lock+0x246/0x270
  do_raw_spin_lock+0x246/0x270
  ? rwlock_bug.part.0+0x90/0x90
  xlog_force_shutdown+0xf6/0x370 [xfs 4ad76ae0d6add7e8183a553e624c31e9ed567318]
  xlog_ioend_work+0x100/0x190 [xfs 4ad76ae0d6add7e8183a553e624c31e9ed567318]
  process_one_work+0x672/0x1040
  worker_thread+0x59b/0xec0
  ? __kthread_parkme+0xc6/0x1f0
  ? process_one_work+0x1040/0x1040
  ? process_one_work+0x1040/0x1040
  kthread+0x29e/0x340
  ? kthread_complete_and_exit+0x20/0x20
  ret_from_fork+0x1f/0x30
  </TASK>

 Allocated by task 154099:
  kasan_save_stack+0x1e/0x40
  __kasan_kmalloc+0x81/0xa0
  kmem_alloc+0x8d/0x2e0 [xfs]
  xlog_cil_init+0x1f/0x540 [xfs]
  xlog_alloc_log+0xd1e/0x1260 [xfs]
  xfs_log_mount+0xba/0x640 [xfs]
  xfs_mountfs+0xf2b/0x1d00 [xfs]
  xfs_fs_fill_super+0x10af/0x1910 [xfs]
  get_tree_bdev+0x383/0x670
  vfs_get_tree+0x7d/0x240
  path_mount+0xdb7/0x1890
  __x64_sys_mount+0x1fa/0x270
  do_syscall_64+0x2b/0x80
  entry_SYSCALL_64_after_hwframe+0x46/0xb0

 Freed by task 154151:
  kasan_save_stack+0x1e/0x40
  kasan_set_track+0x21/0x30
  kasan_set_free_info+0x20/0x30
  ____kasan_slab_free+0x110/0x190
  slab_free_freelist_hook+0xab/0x180
  kfree+0xbc/0x310
  xlog_dealloc_log+0x1b/0x2b0 [xfs]
  xfs_unmountfs+0x119/0x200 [xfs]
  xfs_fs_put_super+0x6e/0x2e0 [xfs]
  generic_shutdown_super+0x12b/0x3a0
  kill_block_super+0x95/0xd0
  deactivate_locked_super+0x80/0x130
  cleanup_mnt+0x329/0x4d0
  task_work_run+0xc5/0x160
  exit_to_user_mode_prepare+0xd4/0xe0
  syscall_exit_to_user_mode+0x1d/0x40
  entry_SYSCALL_64_after_hwframe+0x46/0xb0

This appears to be a race between the unmount process, which frees the
CIL and waits for in-flight iclog IO; and the iclog IO completion.  When
generic/475 runs, it starts fsstress in the background, waits a few
seconds, and substitutes a dm-error device to simulate a disk falling
out of a machine.  If the fsstress encounters EIO on a pure data write,
it will exit but the filesystem will still be online.

The next thing the test does is unmount the filesystem, which tries to
clean the log, free the CIL, and wait for iclog IO completion.  If an
iclog was being written when the dm-error switch occurred, it can race
with log unmounting as follows:

Thread 1				Thread 2

					xfs_log_unmount
					xfs_log_clean
					xfs_log_quiesce
xlog_ioend_work
<observe error>
xlog_force_shutdown
test_and_set_bit(XLOG_IOERROR)
					xfs_log_force
					<log is shut down, nop>
					xfs_log_umount_write
					<log is shut down, nop>
					xlog_dealloc_log
					xlog_cil_destroy
					<wait for iclogs>
spin_lock(&log->l_cilp->xc_push_lock)
<KABOOM>

Therefore, free the CIL after waiting for the iclogs to complete.  I
/think/ this race has existed for quite a few years now, though I don't
remember the ~2014 era logging code well enough to know if it was a real
threat then or if the actual race was exposed only more recently.

Fixes: ac983517ec59 ("xfs: don't sleep in xlog_cil_force_lsn on shutdown")
Signed-off-by: Darrick J. Wong <djwong@kernel.org>
Reviewed-by: Dave Chinner <dchinner@redhat.com>
---
 fs/xfs/xfs_log.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/fs/xfs/xfs_log.c b/fs/xfs/xfs_log.c
index 1e972f884a812..ae904b21e9cc7 100644
--- a/fs/xfs/xfs_log.c
+++ b/fs/xfs/xfs_log.c
@@ -2092,8 +2092,6 @@ xlog_dealloc_log(
 	xlog_in_core_t	*iclog, *next_iclog;
 	int		i;
 
-	xlog_cil_destroy(log);
-
 	/*
 	 * Cycle all the iclogbuf locks to make sure all log IO completion
 	 * is done before we tear down these buffers.
@@ -2105,6 +2103,13 @@ xlog_dealloc_log(
 		iclog = iclog->ic_next;
 	}
 
+	/*
+	 * Destroy the CIL after waiting for iclog IO completion because an
+	 * iclog EIO error will try to shut down the log, which accesses the
+	 * CIL to wake up the waiters.
+	 */
+	xlog_cil_destroy(log);
+
 	iclog = log->l_iclog;
 	for (i = 0; i < log->l_iclog_bufs; i++) {
 		next_iclog = iclog->ic_next;
-- 
GitLab


From 09f7b80fac3e588b282ad26aabd7336d7d293efd Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: Fri, 17 Jun 2022 13:50:42 +0200
Subject: [PATCH 1467/1731] dmaengine: imx-sdma: only restart cyclic channel
 when enabled

An interrupt for a channel might be pending even after struct
dma_device::device_terminate_all has been called. In that case the
recently introduced warning message "restart cyclic channel..." triggers
and the channel will be restarted. This is not desired as the channel
has just been stopped. Only restart the channel when we still have a
descriptor set for it (which will be set to NULL in
sdma_terminate_all()).

Fixes: 5b215c28b9235 ("dmaengine: imx-sdma: restart cyclic channel if needed")
Cc: stable@vger.kernel.org
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20220617115042.4004062-1-s.hauer@pengutronix.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/dma/imx-sdma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 900cafdaf3594..f37a276f519e6 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -891,7 +891,7 @@ static void sdma_update_channel_loop(struct sdma_channel *sdmac)
 	 * SDMA stops cyclic channel when DMA request triggers a channel and no SDMA
 	 * owned buffer is available (i.e. BD_DONE was set too late).
 	 */
-	if (!is_sdma_channel_enabled(sdmac->sdma, sdmac->channel)) {
+	if (sdmac->desc && !is_sdma_channel_enabled(sdmac->sdma, sdmac->channel)) {
 		dev_warn(sdmac->sdma->dev, "restart cyclic channel %d\n", sdmac->channel);
 		sdma_enable_channel(sdmac->sdma, sdmac->channel);
 	}
-- 
GitLab


From 410982303772993a86bb7a9cfa7ece34522b2636 Mon Sep 17 00:00:00 2001
From: Will Deacon <will@kernel.org>
Date: Wed, 29 Jun 2022 10:53:49 +0100
Subject: [PATCH 1468/1731] arm64: hugetlb: Restore TLB invalidation for BBM on
 contiguous ptes

Commit fb396bb459c1 ("arm64/hugetlb: Drop TLB flush from get_clear_flush()")
removed TLB invalidation from get_clear_flush() [now get_clear_contig()]
on the basis that the core TLB invalidation code is aware of hugetlb
mappings backed by contiguous page-table entries and will cover the
correct virtual address range.

However, this change also resulted in the TLB invalidation being removed
from the "break" step in the break-before-make (BBM) sequence used
internally by huge_ptep_set_{access_flags,wrprotect}(), therefore
making the BBM sequence unsafe irrespective of later invalidation.

Although the architecture is desperately unclear about how exactly
contiguous ptes should be updated in a live page-table, restore TLB
invalidation to our BBM sequence under the assumption that BBM is the
right thing to be doing in the first place.

Fixes: fb396bb459c1 ("arm64/hugetlb: Drop TLB flush from get_clear_flush()")
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Steve Capper <steve.capper@arm.com>
Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Mike Kravetz <mike.kravetz@oracle.com>
Cc: Marc Zyngier <maz@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/20220629095349.25748-1-will@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/mm/hugetlbpage.c | 30 +++++++++++++++++++++---------
 1 file changed, 21 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c
index e2a5ec9fdc0db..3618ef3f6d818 100644
--- a/arch/arm64/mm/hugetlbpage.c
+++ b/arch/arm64/mm/hugetlbpage.c
@@ -214,6 +214,19 @@ static pte_t get_clear_contig(struct mm_struct *mm,
 	return orig_pte;
 }
 
+static pte_t get_clear_contig_flush(struct mm_struct *mm,
+				    unsigned long addr,
+				    pte_t *ptep,
+				    unsigned long pgsize,
+				    unsigned long ncontig)
+{
+	pte_t orig_pte = get_clear_contig(mm, addr, ptep, pgsize, ncontig);
+	struct vm_area_struct vma = TLB_FLUSH_VMA(mm, 0);
+
+	flush_tlb_range(&vma, addr, addr + (pgsize * ncontig));
+	return orig_pte;
+}
+
 /*
  * Changing some bits of contiguous entries requires us to follow a
  * Break-Before-Make approach, breaking the whole contiguous set
@@ -447,19 +460,20 @@ int huge_ptep_set_access_flags(struct vm_area_struct *vma,
 	int ncontig, i;
 	size_t pgsize = 0;
 	unsigned long pfn = pte_pfn(pte), dpfn;
+	struct mm_struct *mm = vma->vm_mm;
 	pgprot_t hugeprot;
 	pte_t orig_pte;
 
 	if (!pte_cont(pte))
 		return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
 
-	ncontig = find_num_contig(vma->vm_mm, addr, ptep, &pgsize);
+	ncontig = find_num_contig(mm, addr, ptep, &pgsize);
 	dpfn = pgsize >> PAGE_SHIFT;
 
 	if (!__cont_access_flags_changed(ptep, pte, ncontig))
 		return 0;
 
-	orig_pte = get_clear_contig(vma->vm_mm, addr, ptep, pgsize, ncontig);
+	orig_pte = get_clear_contig_flush(mm, addr, ptep, pgsize, ncontig);
 
 	/* Make sure we don't lose the dirty or young state */
 	if (pte_dirty(orig_pte))
@@ -470,7 +484,7 @@ int huge_ptep_set_access_flags(struct vm_area_struct *vma,
 
 	hugeprot = pte_pgprot(pte);
 	for (i = 0; i < ncontig; i++, ptep++, addr += pgsize, pfn += dpfn)
-		set_pte_at(vma->vm_mm, addr, ptep, pfn_pte(pfn, hugeprot));
+		set_pte_at(mm, addr, ptep, pfn_pte(pfn, hugeprot));
 
 	return 1;
 }
@@ -492,7 +506,7 @@ void huge_ptep_set_wrprotect(struct mm_struct *mm,
 	ncontig = find_num_contig(mm, addr, ptep, &pgsize);
 	dpfn = pgsize >> PAGE_SHIFT;
 
-	pte = get_clear_contig(mm, addr, ptep, pgsize, ncontig);
+	pte = get_clear_contig_flush(mm, addr, ptep, pgsize, ncontig);
 	pte = pte_wrprotect(pte);
 
 	hugeprot = pte_pgprot(pte);
@@ -505,17 +519,15 @@ void huge_ptep_set_wrprotect(struct mm_struct *mm,
 pte_t huge_ptep_clear_flush(struct vm_area_struct *vma,
 			    unsigned long addr, pte_t *ptep)
 {
+	struct mm_struct *mm = vma->vm_mm;
 	size_t pgsize;
 	int ncontig;
-	pte_t orig_pte;
 
 	if (!pte_cont(READ_ONCE(*ptep)))
 		return ptep_clear_flush(vma, addr, ptep);
 
-	ncontig = find_num_contig(vma->vm_mm, addr, ptep, &pgsize);
-	orig_pte = get_clear_contig(vma->vm_mm, addr, ptep, pgsize, ncontig);
-	flush_tlb_range(vma, addr, addr + pgsize * ncontig);
-	return orig_pte;
+	ncontig = find_num_contig(mm, addr, ptep, &pgsize);
+	return get_clear_contig_flush(mm, addr, ptep, pgsize, ncontig);
 }
 
 static int __init hugetlbpage_init(void)
-- 
GitLab


From d0e51022a025ca5350fafb8e413a6fe5d4baf833 Mon Sep 17 00:00:00 2001
From: Yang Yingliang <yangyingliang@huawei.com>
Date: Fri, 1 Jul 2022 15:41:53 +0800
Subject: [PATCH 1469/1731] hwmon: (ibmaem) don't call platform_device_del() if
 platform_device_add() fails

If platform_device_add() fails, it no need to call platform_device_del(), split
platform_device_unregister() into platform_device_del/put(), so platform_device_put()
can be called separately.

Fixes: 8808a793f052 ("ibmaem: new driver for power/energy/temp meters in IBM System X hardware")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Link: https://lore.kernel.org/r/20220701074153.4021556-1-yangyingliang@huawei.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
---
 drivers/hwmon/ibmaem.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/hwmon/ibmaem.c b/drivers/hwmon/ibmaem.c
index 5c4cf742f5ae7..157e232aace0c 100644
--- a/drivers/hwmon/ibmaem.c
+++ b/drivers/hwmon/ibmaem.c
@@ -550,7 +550,7 @@ static int aem_init_aem1_inst(struct aem_ipmi_data *probe, u8 module_handle)
 
 	res = platform_device_add(data->pdev);
 	if (res)
-		goto ipmi_err;
+		goto dev_add_err;
 
 	platform_set_drvdata(data->pdev, data);
 
@@ -598,7 +598,9 @@ hwmon_reg_err:
 	ipmi_destroy_user(data->ipmi.user);
 ipmi_err:
 	platform_set_drvdata(data->pdev, NULL);
-	platform_device_unregister(data->pdev);
+	platform_device_del(data->pdev);
+dev_add_err:
+	platform_device_put(data->pdev);
 dev_err:
 	ida_free(&aem_ida, data->id);
 id_err:
@@ -690,7 +692,7 @@ static int aem_init_aem2_inst(struct aem_ipmi_data *probe,
 
 	res = platform_device_add(data->pdev);
 	if (res)
-		goto ipmi_err;
+		goto dev_add_err;
 
 	platform_set_drvdata(data->pdev, data);
 
@@ -738,7 +740,9 @@ hwmon_reg_err:
 	ipmi_destroy_user(data->ipmi.user);
 ipmi_err:
 	platform_set_drvdata(data->pdev, NULL);
-	platform_device_unregister(data->pdev);
+	platform_device_del(data->pdev);
+dev_add_err:
+	platform_device_put(data->pdev);
 dev_err:
 	ida_free(&aem_ida, data->id);
 id_err:
-- 
GitLab


From 07358194badf73e267289b40b761f5dc56928eab Mon Sep 17 00:00:00 2001
From: "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>
Date: Mon, 27 Jun 2022 20:42:18 +0200
Subject: [PATCH 1470/1731] PM: runtime: Redefine pm_runtime_release_supplier()

Instead of passing an extra bool argument to pm_runtime_release_supplier(),
make its callers take care of triggering a runtime-suspend of the
supplier device as needed.

No expected functional impact.

Suggested-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: 5.1+ <stable@vger.kernel.org> # 5.1+
---
 drivers/base/core.c          |  3 ++-
 drivers/base/power/runtime.c | 20 +++++++++-----------
 include/linux/pm_runtime.h   |  5 ++---
 3 files changed, 13 insertions(+), 15 deletions(-)

diff --git a/drivers/base/core.c b/drivers/base/core.c
index 7cd789c4985d4..58aa49527d3ae 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -486,7 +486,8 @@ static void device_link_release_fn(struct work_struct *work)
 	/* Ensure that all references to the link object have been dropped. */
 	device_link_synchronize_removal();
 
-	pm_runtime_release_supplier(link, true);
+	pm_runtime_release_supplier(link);
+	pm_request_idle(link->supplier);
 
 	put_device(link->consumer);
 	put_device(link->supplier);
diff --git a/drivers/base/power/runtime.c b/drivers/base/power/runtime.c
index 676dc72d912d1..23cc4c377d77e 100644
--- a/drivers/base/power/runtime.c
+++ b/drivers/base/power/runtime.c
@@ -308,13 +308,10 @@ static int rpm_get_suppliers(struct device *dev)
 /**
  * pm_runtime_release_supplier - Drop references to device link's supplier.
  * @link: Target device link.
- * @check_idle: Whether or not to check if the supplier device is idle.
  *
- * Drop all runtime PM references associated with @link to its supplier device
- * and if @check_idle is set, check if that device is idle (and so it can be
- * suspended).
+ * Drop all runtime PM references associated with @link to its supplier device.
  */
-void pm_runtime_release_supplier(struct device_link *link, bool check_idle)
+void pm_runtime_release_supplier(struct device_link *link)
 {
 	struct device *supplier = link->supplier;
 
@@ -327,9 +324,6 @@ void pm_runtime_release_supplier(struct device_link *link, bool check_idle)
 	while (refcount_dec_not_one(&link->rpm_active) &&
 	       atomic_read(&supplier->power.usage_count) > 0)
 		pm_runtime_put_noidle(supplier);
-
-	if (check_idle)
-		pm_request_idle(supplier);
 }
 
 static void __rpm_put_suppliers(struct device *dev, bool try_to_suspend)
@@ -337,8 +331,11 @@ static void __rpm_put_suppliers(struct device *dev, bool try_to_suspend)
 	struct device_link *link;
 
 	list_for_each_entry_rcu(link, &dev->links.suppliers, c_node,
-				device_links_read_lock_held())
-		pm_runtime_release_supplier(link, try_to_suspend);
+				device_links_read_lock_held()) {
+		pm_runtime_release_supplier(link);
+		if (try_to_suspend)
+			pm_request_idle(link->supplier);
+	}
 }
 
 static void rpm_put_suppliers(struct device *dev)
@@ -1838,7 +1835,8 @@ void pm_runtime_drop_link(struct device_link *link)
 		return;
 
 	pm_runtime_drop_link_count(link->consumer);
-	pm_runtime_release_supplier(link, true);
+	pm_runtime_release_supplier(link);
+	pm_request_idle(link->supplier);
 }
 
 static bool pm_runtime_need_not_resume(struct device *dev)
diff --git a/include/linux/pm_runtime.h b/include/linux/pm_runtime.h
index 9e4d056967c66..0a41b2dcccad5 100644
--- a/include/linux/pm_runtime.h
+++ b/include/linux/pm_runtime.h
@@ -88,7 +88,7 @@ extern void pm_runtime_get_suppliers(struct device *dev);
 extern void pm_runtime_put_suppliers(struct device *dev);
 extern void pm_runtime_new_link(struct device *dev);
 extern void pm_runtime_drop_link(struct device_link *link);
-extern void pm_runtime_release_supplier(struct device_link *link, bool check_idle);
+extern void pm_runtime_release_supplier(struct device_link *link);
 
 extern int devm_pm_runtime_enable(struct device *dev);
 
@@ -314,8 +314,7 @@ static inline void pm_runtime_get_suppliers(struct device *dev) {}
 static inline void pm_runtime_put_suppliers(struct device *dev) {}
 static inline void pm_runtime_new_link(struct device *dev) {}
 static inline void pm_runtime_drop_link(struct device_link *link) {}
-static inline void pm_runtime_release_supplier(struct device_link *link,
-					       bool check_idle) {}
+static inline void pm_runtime_release_supplier(struct device_link *link) {}
 
 #endif /* !CONFIG_PM */
 
-- 
GitLab


From 887371066039011144b4a94af97d9328df6869a2 Mon Sep 17 00:00:00 2001
From: "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>
Date: Thu, 30 Jun 2022 21:16:41 +0200
Subject: [PATCH 1471/1731] PM: runtime: Fix supplier device management during
 consumer probe

Because pm_runtime_get_suppliers() bumps up the rpm_active counter
of each device link to a supplier of the given device in addition
to bumping up the supplier's PM-runtime usage counter, a runtime
suspend of the consumer device may case the latter to go down to 0
when pm_runtime_put_suppliers() is running on a remote CPU.  If that
happens after pm_runtime_put_suppliers() has released power.lock for
the consumer device, and a runtime resume of that device takes place
immediately after it, before pm_runtime_put() is called for the
supplier, that pm_runtime_put() call may cause the supplier to be
suspended even though the consumer is active.

To prevent that from happening, modify pm_runtime_get_suppliers() to
call pm_runtime_get_sync() for the given device's suppliers without
touching the rpm_active counters of the involved device links
Accordingly, modify pm_runtime_put_suppliers() to call pm_runtime_put()
for the given device's suppliers without looking at the rpm_active
counters of the device links at hand.  [This is analogous to what
happened before commit 4c06c4e6cf63 ("driver core: Fix possible
supplier PM-usage counter imbalance").]

Since pm_runtime_get_suppliers() sets supplier_preactivated for each
device link where the supplier's PM-runtime usage counter has been
incremented and pm_runtime_put_suppliers() calls pm_runtime_put() for
the suppliers whose device links have supplier_preactivated set, the
PM-runtime usage counter is balanced for each supplier and this is
independent of the runtime suspend and resume of the consumer device.

However, in case a device link with DL_FLAG_PM_RUNTIME set is dropped
during the consumer device probe, so pm_runtime_get_suppliers() bumps
up the supplier's PM-runtime usage counter, but it cannot be dropped by
pm_runtime_put_suppliers(), make device_link_release_fn() take care of
that.

Fixes: 4c06c4e6cf63 ("driver core: Fix possible supplier PM-usage counter imbalance")
Reported-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Cc: 5.1+ <stable@vger.kernel.org> # 5.1+
---
 drivers/base/core.c          | 10 ++++++++++
 drivers/base/power/runtime.c | 14 +-------------
 2 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/drivers/base/core.c b/drivers/base/core.c
index 58aa49527d3ae..460d6f163e41b 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -487,6 +487,16 @@ static void device_link_release_fn(struct work_struct *work)
 	device_link_synchronize_removal();
 
 	pm_runtime_release_supplier(link);
+	/*
+	 * If supplier_preactivated is set, the link has been dropped between
+	 * the pm_runtime_get_suppliers() and pm_runtime_put_suppliers() calls
+	 * in __driver_probe_device().  In that case, drop the supplier's
+	 * PM-runtime usage counter to remove the reference taken by
+	 * pm_runtime_get_suppliers().
+	 */
+	if (link->supplier_preactivated)
+		pm_runtime_put_noidle(link->supplier);
+
 	pm_request_idle(link->supplier);
 
 	put_device(link->consumer);
diff --git a/drivers/base/power/runtime.c b/drivers/base/power/runtime.c
index 23cc4c377d77e..949907e2e2423 100644
--- a/drivers/base/power/runtime.c
+++ b/drivers/base/power/runtime.c
@@ -1768,7 +1768,6 @@ void pm_runtime_get_suppliers(struct device *dev)
 		if (link->flags & DL_FLAG_PM_RUNTIME) {
 			link->supplier_preactivated = true;
 			pm_runtime_get_sync(link->supplier);
-			refcount_inc(&link->rpm_active);
 		}
 
 	device_links_read_unlock(idx);
@@ -1788,19 +1787,8 @@ void pm_runtime_put_suppliers(struct device *dev)
 	list_for_each_entry_rcu(link, &dev->links.suppliers, c_node,
 				device_links_read_lock_held())
 		if (link->supplier_preactivated) {
-			bool put;
-
 			link->supplier_preactivated = false;
-
-			spin_lock_irq(&dev->power.lock);
-
-			put = pm_runtime_status_suspended(dev) &&
-			      refcount_dec_not_one(&link->rpm_active);
-
-			spin_unlock_irq(&dev->power.lock);
-
-			if (put)
-				pm_runtime_put(link->supplier);
+			pm_runtime_put(link->supplier);
 		}
 
 	device_links_read_unlock(idx);
-- 
GitLab


From a12ca6277eca6aeeccf66e840c23a2b520e24c8f Mon Sep 17 00:00:00 2001
From: Daniel Borkmann <daniel@iogearbox.net>
Date: Fri, 1 Jul 2022 14:47:24 +0200
Subject: [PATCH 1472/1731] bpf: Fix incorrect verifier simulation around
 jmp32's jeq/jne

Kuee reported a quirk in the jmp32's jeq/jne simulation, namely that the
register value does not match expectations for the fall-through path. For
example:

Before fix:

  0: R1=ctx(off=0,imm=0) R10=fp0
  0: (b7) r2 = 0                        ; R2_w=P0
  1: (b7) r6 = 563                      ; R6_w=P563
  2: (87) r2 = -r2                      ; R2_w=Pscalar()
  3: (87) r2 = -r2                      ; R2_w=Pscalar()
  4: (4c) w2 |= w6                      ; R2_w=Pscalar(umin=563,umax=4294967295,var_off=(0x233; 0xfffffdcc),s32_min=-2147483085) R6_w=P563
  5: (56) if w2 != 0x8 goto pc+1        ; R2_w=P571  <--- [*]
  6: (95) exit
  R0 !read_ok

After fix:

  0: R1=ctx(off=0,imm=0) R10=fp0
  0: (b7) r2 = 0                        ; R2_w=P0
  1: (b7) r6 = 563                      ; R6_w=P563
  2: (87) r2 = -r2                      ; R2_w=Pscalar()
  3: (87) r2 = -r2                      ; R2_w=Pscalar()
  4: (4c) w2 |= w6                      ; R2_w=Pscalar(umin=563,umax=4294967295,var_off=(0x233; 0xfffffdcc),s32_min=-2147483085) R6_w=P563
  5: (56) if w2 != 0x8 goto pc+1        ; R2_w=P8  <--- [*]
  6: (95) exit
  R0 !read_ok

As can be seen on line 5 for the branch fall-through path in R2 [*] is that
given condition w2 != 0x8 is false, verifier should conclude that r2 = 8 as
upper 32 bit are known to be zero. However, verifier incorrectly concludes
that r2 = 571 which is far off.

The problem is it only marks false{true}_reg as known in the switch for JE/NE
case, but at the end of the function, it uses {false,true}_{64,32}off to
update {false,true}_reg->var_off and they still hold the prior value of
{false,true}_reg->var_off before it got marked as known. The subsequent
__reg_combine_32_into_64() then propagates this old var_off and derives new
bounds. The information between min/max bounds on {false,true}_reg from
setting the register to known const combined with the {false,true}_reg->var_off
based on the old information then derives wrong register data.

Fix it by detangling the BPF_JEQ/BPF_JNE cases and updating relevant
{false,true}_{64,32}off tnums along with the register marking to known
constant.

Fixes: 3f50f132d840 ("bpf: Verifier, do explicit ALU32 bounds tracking")
Reported-by: Kuee K1r0a <liulin063@gmail.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Signed-off-by: Andrii Nakryiko <andrii@kernel.org>
Acked-by: John Fastabend <john.fastabend@gmail.com>
Link: https://lore.kernel.org/bpf/20220701124727.11153-1-daniel@iogearbox.net
---
 kernel/bpf/verifier.c | 41 ++++++++++++++++++++++++-----------------
 1 file changed, 24 insertions(+), 17 deletions(-)

diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c
index aedac2ac02b92..ec164b3c0fa2f 100644
--- a/kernel/bpf/verifier.c
+++ b/kernel/bpf/verifier.c
@@ -9577,26 +9577,33 @@ static void reg_set_min_max(struct bpf_reg_state *true_reg,
 		return;
 
 	switch (opcode) {
+	/* JEQ/JNE comparison doesn't change the register equivalence.
+	 *
+	 * r1 = r2;
+	 * if (r1 == 42) goto label;
+	 * ...
+	 * label: // here both r1 and r2 are known to be 42.
+	 *
+	 * Hence when marking register as known preserve it's ID.
+	 */
 	case BPF_JEQ:
+		if (is_jmp32) {
+			__mark_reg32_known(true_reg, val32);
+			true_32off = tnum_subreg(true_reg->var_off);
+		} else {
+			___mark_reg_known(true_reg, val);
+			true_64off = true_reg->var_off;
+		}
+		break;
 	case BPF_JNE:
-	{
-		struct bpf_reg_state *reg =
-			opcode == BPF_JEQ ? true_reg : false_reg;
-
-		/* JEQ/JNE comparison doesn't change the register equivalence.
-		 * r1 = r2;
-		 * if (r1 == 42) goto label;
-		 * ...
-		 * label: // here both r1 and r2 are known to be 42.
-		 *
-		 * Hence when marking register as known preserve it's ID.
-		 */
-		if (is_jmp32)
-			__mark_reg32_known(reg, val32);
-		else
-			___mark_reg_known(reg, val);
+		if (is_jmp32) {
+			__mark_reg32_known(false_reg, val32);
+			false_32off = tnum_subreg(false_reg->var_off);
+		} else {
+			___mark_reg_known(false_reg, val);
+			false_64off = false_reg->var_off;
+		}
 		break;
-	}
 	case BPF_JSET:
 		if (is_jmp32) {
 			false_32off = tnum_and(false_32off, tnum_const(~val32));
-- 
GitLab


From 3844d153a41adea718202c10ae91dc96b37453b5 Mon Sep 17 00:00:00 2001
From: Daniel Borkmann <daniel@iogearbox.net>
Date: Fri, 1 Jul 2022 14:47:25 +0200
Subject: [PATCH 1473/1731] bpf: Fix insufficient bounds propagation from
 adjust_scalar_min_max_vals

Kuee reported a corner case where the tnum becomes constant after the call
to __reg_bound_offset(), but the register's bounds are not, that is, its
min bounds are still not equal to the register's max bounds.

This in turn allows to leak pointers through turning a pointer register as
is into an unknown scalar via adjust_ptr_min_max_vals().

Before:

  func#0 @0
  0: R1=ctx(off=0,imm=0,umax=0,var_off=(0x0; 0x0)) R10=fp(off=0,imm=0,umax=0,var_off=(0x0; 0x0))
  0: (b7) r0 = 1                        ; R0_w=scalar(imm=1,umin=1,umax=1,var_off=(0x1; 0x0))
  1: (b7) r3 = 0                        ; R3_w=scalar(imm=0,umax=0,var_off=(0x0; 0x0))
  2: (87) r3 = -r3                      ; R3_w=scalar()
  3: (87) r3 = -r3                      ; R3_w=scalar()
  4: (47) r3 |= 32767                   ; R3_w=scalar(smin=-9223372036854743041,umin=32767,var_off=(0x7fff; 0xffffffffffff8000),s32_min=-2147450881)
  5: (75) if r3 s>= 0x0 goto pc+1       ; R3_w=scalar(umin=9223372036854808575,var_off=(0x8000000000007fff; 0x7fffffffffff8000),s32_min=-2147450881,u32_min=32767)
  6: (95) exit

  from 5 to 7: R0=scalar(imm=1,umin=1,umax=1,var_off=(0x1; 0x0)) R1=ctx(off=0,imm=0,umax=0,var_off=(0x0; 0x0)) R3=scalar(umin=32767,umax=9223372036854775807,var_off=(0x7fff; 0x7fffffffffff8000),s32_min=-2147450881) R10=fp(off=0,imm=0,umax=0,var_off=(0x0; 0x0))
  7: (d5) if r3 s<= 0x8000 goto pc+1    ; R3=scalar(umin=32769,umax=9223372036854775807,var_off=(0x7fff; 0x7fffffffffff8000),s32_min=-2147450881,u32_min=32767)
  8: (95) exit

  from 7 to 9: R0=scalar(imm=1,umin=1,umax=1,var_off=(0x1; 0x0)) R1=ctx(off=0,imm=0,umax=0,var_off=(0x0; 0x0)) R3=scalar(umin=32767,umax=32768,var_off=(0x7fff; 0x8000)) R10=fp(off=0,imm=0,umax=0,var_off=(0x0; 0x0))
  9: (07) r3 += -32767                  ; R3_w=scalar(imm=0,umax=1,var_off=(0x0; 0x0))  <--- [*]
  10: (95) exit

What can be seen here is that R3=scalar(umin=32767,umax=32768,var_off=(0x7fff;
0x8000)) after the operation R3 += -32767 results in a 'malformed' constant, that
is, R3_w=scalar(imm=0,umax=1,var_off=(0x0; 0x0)). Intersecting with var_off has
not been done at that point via __update_reg_bounds(), which would have improved
the umax to be equal to umin.

Refactor the tnum <> min/max bounds information flow into a reg_bounds_sync()
helper and use it consistently everywhere. After the fix, bounds have been
corrected to R3_w=scalar(imm=0,umax=0,var_off=(0x0; 0x0)) and thus the register
is regarded as a 'proper' constant scalar of 0.

After:

  func#0 @0
  0: R1=ctx(off=0,imm=0,umax=0,var_off=(0x0; 0x0)) R10=fp(off=0,imm=0,umax=0,var_off=(0x0; 0x0))
  0: (b7) r0 = 1                        ; R0_w=scalar(imm=1,umin=1,umax=1,var_off=(0x1; 0x0))
  1: (b7) r3 = 0                        ; R3_w=scalar(imm=0,umax=0,var_off=(0x0; 0x0))
  2: (87) r3 = -r3                      ; R3_w=scalar()
  3: (87) r3 = -r3                      ; R3_w=scalar()
  4: (47) r3 |= 32767                   ; R3_w=scalar(smin=-9223372036854743041,umin=32767,var_off=(0x7fff; 0xffffffffffff8000),s32_min=-2147450881)
  5: (75) if r3 s>= 0x0 goto pc+1       ; R3_w=scalar(umin=9223372036854808575,var_off=(0x8000000000007fff; 0x7fffffffffff8000),s32_min=-2147450881,u32_min=32767)
  6: (95) exit

  from 5 to 7: R0=scalar(imm=1,umin=1,umax=1,var_off=(0x1; 0x0)) R1=ctx(off=0,imm=0,umax=0,var_off=(0x0; 0x0)) R3=scalar(umin=32767,umax=9223372036854775807,var_off=(0x7fff; 0x7fffffffffff8000),s32_min=-2147450881) R10=fp(off=0,imm=0,umax=0,var_off=(0x0; 0x0))
  7: (d5) if r3 s<= 0x8000 goto pc+1    ; R3=scalar(umin=32769,umax=9223372036854775807,var_off=(0x7fff; 0x7fffffffffff8000),s32_min=-2147450881,u32_min=32767)
  8: (95) exit

  from 7 to 9: R0=scalar(imm=1,umin=1,umax=1,var_off=(0x1; 0x0)) R1=ctx(off=0,imm=0,umax=0,var_off=(0x0; 0x0)) R3=scalar(umin=32767,umax=32768,var_off=(0x7fff; 0x8000)) R10=fp(off=0,imm=0,umax=0,var_off=(0x0; 0x0))
  9: (07) r3 += -32767                  ; R3_w=scalar(imm=0,umax=0,var_off=(0x0; 0x0))  <--- [*]
  10: (95) exit

Fixes: b03c9f9fdc37 ("bpf/verifier: track signed and unsigned min/max values")
Reported-by: Kuee K1r0a <liulin063@gmail.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Signed-off-by: Andrii Nakryiko <andrii@kernel.org>
Acked-by: John Fastabend <john.fastabend@gmail.com>
Link: https://lore.kernel.org/bpf/20220701124727.11153-2-daniel@iogearbox.net
---
 kernel/bpf/verifier.c | 72 ++++++++++++++-----------------------------
 1 file changed, 23 insertions(+), 49 deletions(-)

diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c
index ec164b3c0fa2f..0efbac0fd1264 100644
--- a/kernel/bpf/verifier.c
+++ b/kernel/bpf/verifier.c
@@ -1562,6 +1562,21 @@ static void __reg_bound_offset(struct bpf_reg_state *reg)
 	reg->var_off = tnum_or(tnum_clear_subreg(var64_off), var32_off);
 }
 
+static void reg_bounds_sync(struct bpf_reg_state *reg)
+{
+	/* We might have learned new bounds from the var_off. */
+	__update_reg_bounds(reg);
+	/* We might have learned something about the sign bit. */
+	__reg_deduce_bounds(reg);
+	/* We might have learned some bits from the bounds. */
+	__reg_bound_offset(reg);
+	/* Intersecting with the old var_off might have improved our bounds
+	 * slightly, e.g. if umax was 0x7f...f and var_off was (0; 0xf...fc),
+	 * then new var_off is (0; 0x7f...fc) which improves our umax.
+	 */
+	__update_reg_bounds(reg);
+}
+
 static bool __reg32_bound_s64(s32 a)
 {
 	return a >= 0 && a <= S32_MAX;
@@ -1603,16 +1618,8 @@ static void __reg_combine_32_into_64(struct bpf_reg_state *reg)
 		 * so they do not impact tnum bounds calculation.
 		 */
 		__mark_reg64_unbounded(reg);
-		__update_reg_bounds(reg);
 	}
-
-	/* Intersecting with the old var_off might have improved our bounds
-	 * slightly.  e.g. if umax was 0x7f...f and var_off was (0; 0xf...fc),
-	 * then new var_off is (0; 0x7f...fc) which improves our umax.
-	 */
-	__reg_deduce_bounds(reg);
-	__reg_bound_offset(reg);
-	__update_reg_bounds(reg);
+	reg_bounds_sync(reg);
 }
 
 static bool __reg64_bound_s32(s64 a)
@@ -1628,7 +1635,6 @@ static bool __reg64_bound_u32(u64 a)
 static void __reg_combine_64_into_32(struct bpf_reg_state *reg)
 {
 	__mark_reg32_unbounded(reg);
-
 	if (__reg64_bound_s32(reg->smin_value) && __reg64_bound_s32(reg->smax_value)) {
 		reg->s32_min_value = (s32)reg->smin_value;
 		reg->s32_max_value = (s32)reg->smax_value;
@@ -1637,14 +1643,7 @@ static void __reg_combine_64_into_32(struct bpf_reg_state *reg)
 		reg->u32_min_value = (u32)reg->umin_value;
 		reg->u32_max_value = (u32)reg->umax_value;
 	}
-
-	/* Intersecting with the old var_off might have improved our bounds
-	 * slightly.  e.g. if umax was 0x7f...f and var_off was (0; 0xf...fc),
-	 * then new var_off is (0; 0x7f...fc) which improves our umax.
-	 */
-	__reg_deduce_bounds(reg);
-	__reg_bound_offset(reg);
-	__update_reg_bounds(reg);
+	reg_bounds_sync(reg);
 }
 
 /* Mark a register as having a completely unknown (scalar) value. */
@@ -6943,9 +6942,7 @@ static void do_refine_retval_range(struct bpf_reg_state *regs, int ret_type,
 	ret_reg->s32_max_value = meta->msize_max_value;
 	ret_reg->smin_value = -MAX_ERRNO;
 	ret_reg->s32_min_value = -MAX_ERRNO;
-	__reg_deduce_bounds(ret_reg);
-	__reg_bound_offset(ret_reg);
-	__update_reg_bounds(ret_reg);
+	reg_bounds_sync(ret_reg);
 }
 
 static int
@@ -8202,11 +8199,7 @@ static int adjust_ptr_min_max_vals(struct bpf_verifier_env *env,
 
 	if (!check_reg_sane_offset(env, dst_reg, ptr_reg->type))
 		return -EINVAL;
-
-	__update_reg_bounds(dst_reg);
-	__reg_deduce_bounds(dst_reg);
-	__reg_bound_offset(dst_reg);
-
+	reg_bounds_sync(dst_reg);
 	if (sanitize_check_bounds(env, insn, dst_reg) < 0)
 		return -EACCES;
 	if (sanitize_needed(opcode)) {
@@ -8944,10 +8937,7 @@ static int adjust_scalar_min_max_vals(struct bpf_verifier_env *env,
 	/* ALU32 ops are zero extended into 64bit register */
 	if (alu32)
 		zext_32_to_64(dst_reg);
-
-	__update_reg_bounds(dst_reg);
-	__reg_deduce_bounds(dst_reg);
-	__reg_bound_offset(dst_reg);
+	reg_bounds_sync(dst_reg);
 	return 0;
 }
 
@@ -9136,10 +9126,7 @@ static int check_alu_op(struct bpf_verifier_env *env, struct bpf_insn *insn)
 							 insn->dst_reg);
 				}
 				zext_32_to_64(dst_reg);
-
-				__update_reg_bounds(dst_reg);
-				__reg_deduce_bounds(dst_reg);
-				__reg_bound_offset(dst_reg);
+				reg_bounds_sync(dst_reg);
 			}
 		} else {
 			/* case: R = imm
@@ -9742,21 +9729,8 @@ static void __reg_combine_min_max(struct bpf_reg_state *src_reg,
 							dst_reg->smax_value);
 	src_reg->var_off = dst_reg->var_off = tnum_intersect(src_reg->var_off,
 							     dst_reg->var_off);
-	/* We might have learned new bounds from the var_off. */
-	__update_reg_bounds(src_reg);
-	__update_reg_bounds(dst_reg);
-	/* We might have learned something about the sign bit. */
-	__reg_deduce_bounds(src_reg);
-	__reg_deduce_bounds(dst_reg);
-	/* We might have learned some bits from the bounds. */
-	__reg_bound_offset(src_reg);
-	__reg_bound_offset(dst_reg);
-	/* Intersecting with the old var_off might have improved our bounds
-	 * slightly.  e.g. if umax was 0x7f...f and var_off was (0; 0xf...fc),
-	 * then new var_off is (0; 0x7f...fc) which improves our umax.
-	 */
-	__update_reg_bounds(src_reg);
-	__update_reg_bounds(dst_reg);
+	reg_bounds_sync(src_reg);
+	reg_bounds_sync(dst_reg);
 }
 
 static void reg_combine_min_max(struct bpf_reg_state *true_src,
-- 
GitLab


From 73c4936f916de73fa3faec204a4deb37c25e18c1 Mon Sep 17 00:00:00 2001
From: Daniel Borkmann <daniel@iogearbox.net>
Date: Fri, 1 Jul 2022 14:47:26 +0200
Subject: [PATCH 1474/1731] bpf, selftests: Add verifier test case for
 imm=0,umin=0,umax=1 scalar

Add a test case to trigger the constant scalar issue which leaves the
register in scalar(imm=0,umin=0,umax=1,var_off=(0x0; 0x0)) state. Make
use of dead code elimination, so that we can see the verifier bailing
out on unfixed kernels. For the condition, we use jle given it checks
on umax bound.

Before:

  # ./test_verifier 743
  #743/p jump & dead code elimination FAIL
  Failed to load prog 'Permission denied'!
  R4 !read_ok
  verification time 11 usec
  stack depth 0
  processed 13 insns (limit 1000000) max_states_per_insn 0 total_states 1 peak_states 1 mark_read 1
  Summary: 0 PASSED, 0 SKIPPED, 1 FAILED

After:

  # ./test_verifier 743
  #743/p jump & dead code elimination OK
  Summary: 1 PASSED, 0 SKIPPED, 0 FAILED

Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Signed-off-by: Andrii Nakryiko <andrii@kernel.org>
Link: https://lore.kernel.org/bpf/20220701124727.11153-3-daniel@iogearbox.net
---
 tools/testing/selftests/bpf/verifier/jump.c | 22 +++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/tools/testing/selftests/bpf/verifier/jump.c b/tools/testing/selftests/bpf/verifier/jump.c
index 6f951d1ff0a44..497fe17d2eaf6 100644
--- a/tools/testing/selftests/bpf/verifier/jump.c
+++ b/tools/testing/selftests/bpf/verifier/jump.c
@@ -373,3 +373,25 @@
 	.result = ACCEPT,
 	.retval = 3,
 },
+{
+	"jump & dead code elimination",
+	.insns = {
+	BPF_MOV64_IMM(BPF_REG_0, 1),
+	BPF_MOV64_IMM(BPF_REG_3, 0),
+	BPF_ALU64_IMM(BPF_NEG, BPF_REG_3, 0),
+	BPF_ALU64_IMM(BPF_NEG, BPF_REG_3, 0),
+	BPF_ALU64_IMM(BPF_OR, BPF_REG_3, 32767),
+	BPF_JMP_IMM(BPF_JSGE, BPF_REG_3, 0, 1),
+	BPF_EXIT_INSN(),
+	BPF_JMP_IMM(BPF_JSLE, BPF_REG_3, 0x8000, 1),
+	BPF_EXIT_INSN(),
+	BPF_ALU64_IMM(BPF_ADD, BPF_REG_3, -32767),
+	BPF_MOV64_IMM(BPF_REG_0, 2),
+	BPF_JMP_IMM(BPF_JLE, BPF_REG_3, 0, 1),
+	BPF_MOV64_REG(BPF_REG_0, BPF_REG_4),
+	BPF_EXIT_INSN(),
+	},
+	.prog_type = BPF_PROG_TYPE_SCHED_CLS,
+	.result = ACCEPT,
+	.retval = 2,
+},
-- 
GitLab


From a49b8ce7306cf8031361a6a4f7f6bc7a775a39c8 Mon Sep 17 00:00:00 2001
From: Daniel Borkmann <daniel@iogearbox.net>
Date: Fri, 1 Jul 2022 14:47:27 +0200
Subject: [PATCH 1475/1731] bpf, selftests: Add verifier test case for jmp32's
 jeq/jne

Add a test case to trigger the verifier's incorrect conclusion in the
case of jmp32's jeq/jne. Also here, make use of dead code elimination,
so that we can see the verifier bailing out on unfixed kernels.

Before:

  # ./test_verifier 724
  #724/p jeq32/jne32: bounds checking FAIL
  Failed to load prog 'Permission denied'!
  R4 !read_ok
  verification time 8 usec
  stack depth 0
  processed 8 insns (limit 1000000) max_states_per_insn 0 total_states 1 peak_states 1 mark_read 0
  Summary: 0 PASSED, 0 SKIPPED, 1 FAILED

After:

  # ./test_verifier 724
  #724/p jeq32/jne32: bounds checking OK
  Summary: 1 PASSED, 0 SKIPPED, 0 FAILED

Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Signed-off-by: Andrii Nakryiko <andrii@kernel.org>
Link: https://lore.kernel.org/bpf/20220701124727.11153-4-daniel@iogearbox.net
---
 tools/testing/selftests/bpf/verifier/jmp32.c | 21 ++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/tools/testing/selftests/bpf/verifier/jmp32.c b/tools/testing/selftests/bpf/verifier/jmp32.c
index 6ddc418fdfafa..1a27a62105543 100644
--- a/tools/testing/selftests/bpf/verifier/jmp32.c
+++ b/tools/testing/selftests/bpf/verifier/jmp32.c
@@ -864,3 +864,24 @@
 	.result = ACCEPT,
 	.flags = F_NEEDS_EFFICIENT_UNALIGNED_ACCESS,
 },
+{
+	"jeq32/jne32: bounds checking",
+	.insns = {
+	BPF_MOV64_IMM(BPF_REG_6, 563),
+	BPF_MOV64_IMM(BPF_REG_2, 0),
+	BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
+	BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
+	BPF_ALU32_REG(BPF_OR, BPF_REG_2, BPF_REG_6),
+	BPF_JMP32_IMM(BPF_JNE, BPF_REG_2, 8, 5),
+	BPF_JMP_IMM(BPF_JSGE, BPF_REG_2, 500, 2),
+	BPF_MOV64_IMM(BPF_REG_0, 2),
+	BPF_EXIT_INSN(),
+	BPF_MOV64_REG(BPF_REG_0, BPF_REG_4),
+	BPF_EXIT_INSN(),
+	BPF_MOV64_IMM(BPF_REG_0, 1),
+	BPF_EXIT_INSN(),
+	},
+	.prog_type = BPF_PROG_TYPE_SCHED_CLS,
+	.result = ACCEPT,
+	.retval = 1,
+},
-- 
GitLab


From 3461b040a90d723c93c9d1c7c11e3464f5cadc0e Mon Sep 17 00:00:00 2001
From: Tom Rix <trix@redhat.com>
Date: Fri, 1 Jul 2022 16:32:36 -0400
Subject: [PATCH 1476/1731] drm/i915/display: clean up comments

spelling changes
resoluition -> resolution
dont        -> don't
commmit     -> commit
Invalidade  -> Invalidate

Signed-off-by: Tom Rix <trix@redhat.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220701203236.1871668-1-trix@redhat.com
---
 drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 7d61c55184e51..e6a870641cd25 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -555,7 +555,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 		/*
 		 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default
 		 * values from BSpec. In order to setting an optimal power
-		 * consumption, lower than 4k resoluition mode needs to decrese
+		 * consumption, lower than 4k resolution mode needs to decrease
 		 * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution
 		 * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE.
 		 */
@@ -959,7 +959,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 	int psr_setup_time;
 
 	/*
-	 * Current PSR panels dont work reliably with VRR enabled
+	 * Current PSR panels don't work reliably with VRR enabled
 	 * So if VRR is enabled, do not enable PSR.
 	 */
 	if (crtc_state->vrr.enable)
@@ -1664,7 +1664,7 @@ static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *c
  *
  * Plane scaling and rotation is not supported by selective fetch and both
  * properties can change without a modeset, so need to be check at every
- * atomic commmit.
+ * atomic commit.
  */
 static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state)
 {
@@ -2203,7 +2203,7 @@ static void _psr_invalidate_handle(struct intel_dp *intel_dp)
 }
 
 /**
- * intel_psr_invalidate - Invalidade PSR
+ * intel_psr_invalidate - Invalidate PSR
  * @dev_priv: i915 device
  * @frontbuffer_bits: frontbuffer plane tracking bits
  * @origin: which operation caused the invalidate
-- 
GitLab


From d28b25a62a47a8c8aa19bd543863aab6717e68c9 Mon Sep 17 00:00:00 2001
From: Hangbin Liu <liuhangbin@gmail.com>
Date: Thu, 30 Jun 2022 14:22:28 +0800
Subject: [PATCH 1477/1731] selftests/net: fix section name when using
 xdp_dummy.o

Since commit 8fffa0e3451a ("selftests/bpf: Normalize XDP section names in
selftests") the xdp_dummy.o's section name has changed to xdp. But some
tests are still using "section xdp_dummy", which make the tests failed.
Fix them by updating to the new section name.

Fixes: 8fffa0e3451a ("selftests/bpf: Normalize XDP section names in selftests")
Signed-off-by: Hangbin Liu <liuhangbin@gmail.com>
Acked-by: Andrii Nakryiko <andrii@kernel.org>
Link: https://lore.kernel.org/r/20220630062228.3453016-1-liuhangbin@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 tools/testing/selftests/net/udpgro.sh         | 2 +-
 tools/testing/selftests/net/udpgro_bench.sh   | 2 +-
 tools/testing/selftests/net/udpgro_frglist.sh | 2 +-
 tools/testing/selftests/net/udpgro_fwd.sh     | 2 +-
 tools/testing/selftests/net/veth.sh           | 6 +++---
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/tools/testing/selftests/net/udpgro.sh b/tools/testing/selftests/net/udpgro.sh
index f8a19f548ae9d..ebbd0b2824327 100755
--- a/tools/testing/selftests/net/udpgro.sh
+++ b/tools/testing/selftests/net/udpgro.sh
@@ -34,7 +34,7 @@ cfg_veth() {
 	ip -netns "${PEER_NS}" addr add dev veth1 192.168.1.1/24
 	ip -netns "${PEER_NS}" addr add dev veth1 2001:db8::1/64 nodad
 	ip -netns "${PEER_NS}" link set dev veth1 up
-	ip -n "${PEER_NS}" link set veth1 xdp object ../bpf/xdp_dummy.o section xdp_dummy
+	ip -n "${PEER_NS}" link set veth1 xdp object ../bpf/xdp_dummy.o section xdp
 }
 
 run_one() {
diff --git a/tools/testing/selftests/net/udpgro_bench.sh b/tools/testing/selftests/net/udpgro_bench.sh
index 820bc50f6b687..fad2d1a71cac3 100755
--- a/tools/testing/selftests/net/udpgro_bench.sh
+++ b/tools/testing/selftests/net/udpgro_bench.sh
@@ -34,7 +34,7 @@ run_one() {
 	ip -netns "${PEER_NS}" addr add dev veth1 2001:db8::1/64 nodad
 	ip -netns "${PEER_NS}" link set dev veth1 up
 
-	ip -n "${PEER_NS}" link set veth1 xdp object ../bpf/xdp_dummy.o section xdp_dummy
+	ip -n "${PEER_NS}" link set veth1 xdp object ../bpf/xdp_dummy.o section xdp
 	ip netns exec "${PEER_NS}" ./udpgso_bench_rx ${rx_args} -r &
 	ip netns exec "${PEER_NS}" ./udpgso_bench_rx -t ${rx_args} -r &
 
diff --git a/tools/testing/selftests/net/udpgro_frglist.sh b/tools/testing/selftests/net/udpgro_frglist.sh
index 807b74c8fd80f..832c738cc3c29 100755
--- a/tools/testing/selftests/net/udpgro_frglist.sh
+++ b/tools/testing/selftests/net/udpgro_frglist.sh
@@ -36,7 +36,7 @@ run_one() {
 	ip netns exec "${PEER_NS}" ethtool -K veth1 rx-gro-list on
 
 
-	ip -n "${PEER_NS}" link set veth1 xdp object ../bpf/xdp_dummy.o section xdp_dummy
+	ip -n "${PEER_NS}" link set veth1 xdp object ../bpf/xdp_dummy.o section xdp
 	tc -n "${PEER_NS}" qdisc add dev veth1 clsact
 	tc -n "${PEER_NS}" filter add dev veth1 ingress prio 4 protocol ipv6 bpf object-file ../bpf/nat6to4.o section schedcls/ingress6/nat_6  direct-action
 	tc -n "${PEER_NS}" filter add dev veth1 egress prio 4 protocol ip bpf object-file ../bpf/nat6to4.o section schedcls/egress4/snat4 direct-action
diff --git a/tools/testing/selftests/net/udpgro_fwd.sh b/tools/testing/selftests/net/udpgro_fwd.sh
index 6f05e06f67613..1bcd82e1f662e 100755
--- a/tools/testing/selftests/net/udpgro_fwd.sh
+++ b/tools/testing/selftests/net/udpgro_fwd.sh
@@ -46,7 +46,7 @@ create_ns() {
 		ip -n $BASE$ns addr add dev veth$ns $BM_NET_V4$ns/24
 		ip -n $BASE$ns addr add dev veth$ns $BM_NET_V6$ns/64 nodad
 	done
-	ip -n $NS_DST link set veth$DST xdp object ../bpf/xdp_dummy.o section xdp_dummy 2>/dev/null
+	ip -n $NS_DST link set veth$DST xdp object ../bpf/xdp_dummy.o section xdp 2>/dev/null
 }
 
 create_vxlan_endpoint() {
diff --git a/tools/testing/selftests/net/veth.sh b/tools/testing/selftests/net/veth.sh
index 19eac3e44c065..430895d1a2b63 100755
--- a/tools/testing/selftests/net/veth.sh
+++ b/tools/testing/selftests/net/veth.sh
@@ -289,14 +289,14 @@ if [ $CPUS -gt 1 ]; then
 	ip netns exec $NS_SRC ethtool -L veth$SRC rx 1 tx 2 2>/dev/null
 	printf "%-60s" "bad setting: XDP with RX nr less than TX"
 	ip -n $NS_DST link set dev veth$DST xdp object ../bpf/xdp_dummy.o \
-		section xdp_dummy 2>/dev/null &&\
+		section xdp 2>/dev/null &&\
 		echo "fail - set operation successful ?!?" || echo " ok "
 
 	# the following tests will run with multiple channels active
 	ip netns exec $NS_SRC ethtool -L veth$SRC rx 2
 	ip netns exec $NS_DST ethtool -L veth$DST rx 2
 	ip -n $NS_DST link set dev veth$DST xdp object ../bpf/xdp_dummy.o \
-		section xdp_dummy 2>/dev/null
+		section xdp 2>/dev/null
 	printf "%-60s" "bad setting: reducing RX nr below peer TX with XDP set"
 	ip netns exec $NS_DST ethtool -L veth$DST rx 1 2>/dev/null &&\
 		echo "fail - set operation successful ?!?" || echo " ok "
@@ -311,7 +311,7 @@ if [ $CPUS -gt 2 ]; then
 	chk_channels "setting invalid channels nr" $DST 2 2
 fi
 
-ip -n $NS_DST link set dev veth$DST xdp object ../bpf/xdp_dummy.o section xdp_dummy 2>/dev/null
+ip -n $NS_DST link set dev veth$DST xdp object ../bpf/xdp_dummy.o section xdp 2>/dev/null
 chk_gro_flag "with xdp attached - gro flag" $DST on
 chk_gro_flag "        - peer gro flag" $SRC off
 chk_tso_flag "        - tso flag" $SRC off
-- 
GitLab


From 5eb502b2e1ae1ab052cdf6bdd7615217e8517360 Mon Sep 17 00:00:00 2001
From: Ivan Babrou <ivan@cloudflare.com>
Date: Fri, 1 Jul 2022 11:20:46 -0700
Subject: [PATCH 1478/1731] perf unwind: Fix unitialized 'offset' variable on
 aarch64

Commit dc2cf4ca866f5715 ("perf unwind: Fix segbase for ld.lld linked
objects") uncovered the following issue on aarch64:

    util/unwind-libunwind-local.c: In function 'find_proc_info':
    util/unwind-libunwind-local.c:386:28: error: 'offset' may be used uninitialized in this function [-Werror=maybe-uninitialized]
    386 |                         if (ofs > 0) {
        |                            ^
    util/unwind-libunwind-local.c:199:22: note: 'offset' was declared here
    199 |         u64 address, offset;
        |                      ^~~~~~
    util/unwind-libunwind-local.c:371:20: error: 'offset' may be used uninitialized in this function [-Werror=maybe-uninitialized]
    371 |                 if (ofs <= 0) {
        |                    ^
    util/unwind-libunwind-local.c:199:22: note: 'offset' was declared here
    199 |         u64 address, offset;
        |                      ^~~~~~
    util/unwind-libunwind-local.c:363:20: error: 'offset' may be used uninitialized in this function [-Werror=maybe-uninitialized]
    363 |                 if (ofs <= 0) {
        |                    ^
    util/unwind-libunwind-local.c:199:22: note: 'offset' was declared here
    199 |         u64 address, offset;
        |                      ^~~~~~
    In file included from util/libunwind/arm64.c:37:

Fixes: dc2cf4ca866f5715 ("perf unwind: Fix segbase for ld.lld linked objects")
Signed-off-by: Ivan Babrou <ivan@cloudflare.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Fangrui Song <maskray@google.com>
Cc: Ian Rogers <irogers@google.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: kernel-team@cloudflare.com
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lore.kernel.org/lkml/20220701182046.12589-1-ivan@cloudflare.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/unwind-libunwind-local.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/perf/util/unwind-libunwind-local.c b/tools/perf/util/unwind-libunwind-local.c
index 6e5b8cce47bf4..81b6bd6e1536a 100644
--- a/tools/perf/util/unwind-libunwind-local.c
+++ b/tools/perf/util/unwind-libunwind-local.c
@@ -197,7 +197,7 @@ out_err:
 #ifndef NO_LIBUNWIND_DEBUG_FRAME
 static u64 elf_section_offset(int fd, const char *name)
 {
-	u64 address, offset;
+	u64 address, offset = 0;
 
 	if (elf_section_address_and_offset(fd, name, &address, &offset))
 		return 0;
-- 
GitLab


From 363afa3aef24f5e08df6a539f5dc3aae4cddcc1a Mon Sep 17 00:00:00 2001
From: Namhyung Kim <namhyung@kernel.org>
Date: Fri, 1 Jul 2022 13:54:57 -0700
Subject: [PATCH 1479/1731] perf synthetic-events: Don't sort the task scan
 result from /proc

It should not sort the result as procfs already returns a proper
ordering of tasks.  Actually sorting the order caused problems that it
doesn't guararantee to process the main thread first.

Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Acked-by: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lore.kernel.org/lkml/20220701205458.985106-1-namhyung@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/synthetic-events.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/perf/util/synthetic-events.c b/tools/perf/util/synthetic-events.c
index 27acdc5e57236..a068f42833c35 100644
--- a/tools/perf/util/synthetic-events.c
+++ b/tools/perf/util/synthetic-events.c
@@ -754,7 +754,7 @@ static int __event__synthesize_thread(union perf_event *comm_event,
 	snprintf(filename, sizeof(filename), "%s/proc/%d/task",
 		 machine->root_dir, pid);
 
-	n = scandir(filename, &dirent, filter_task, alphasort);
+	n = scandir(filename, &dirent, filter_task, NULL);
 	if (n < 0)
 		return n;
 
@@ -987,7 +987,7 @@ int perf_event__synthesize_threads(struct perf_tool *tool,
 		return 0;
 
 	snprintf(proc_path, sizeof(proc_path), "%s/proc", machine->root_dir);
-	n = scandir(proc_path, &dirent, filter_task, alphasort);
+	n = scandir(proc_path, &dirent, filter_task, NULL);
 	if (n < 0)
 		return err;
 
-- 
GitLab


From ff898552fb32d255517fb0676f9fa500664c484d Mon Sep 17 00:00:00 2001
From: Namhyung Kim <namhyung@kernel.org>
Date: Fri, 1 Jul 2022 13:54:58 -0700
Subject: [PATCH 1480/1731] perf synthetic-events: Ignore dead threads during
 event synthesis

When it synthesize various task events, it scans the list of task
first and then accesses later.  There's a window threads can die
between the two and proc entries may not be available.

Instead of bailing out, we can ignore that thread and move on.

Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Acked-by: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lore.kernel.org/lkml/20220701205458.985106-2-namhyung@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/synthetic-events.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/tools/perf/util/synthetic-events.c b/tools/perf/util/synthetic-events.c
index a068f42833c35..84d17bd4efaed 100644
--- a/tools/perf/util/synthetic-events.c
+++ b/tools/perf/util/synthetic-events.c
@@ -767,11 +767,12 @@ static int __event__synthesize_thread(union perf_event *comm_event,
 		if (*end)
 			continue;
 
-		rc = -1;
+		/* some threads may exit just after scan, ignore it */
 		if (perf_event__prepare_comm(comm_event, pid, _pid, machine,
 					     &tgid, &ppid, &kernel_thread) != 0)
-			break;
+			continue;
 
+		rc = -1;
 		if (perf_event__synthesize_fork(tool, fork_event, _pid, tgid,
 						ppid, process, machine) < 0)
 			break;
-- 
GitLab


From 2cd37c2e72449a7add6da1183d20a6247d6db111 Mon Sep 17 00:00:00 2001
From: Shuah Khan <skhan@linuxfoundation.org>
Date: Fri, 1 Jul 2022 10:53:52 -0600
Subject: [PATCH 1481/1731] misc: rtsx_usb: set return value in rsp_buf alloc
 err path

Set return value in rsp_buf alloc error path before going to
error handling.

drivers/misc/cardreader/rtsx_usb.c:639:6: warning: variable 'ret' is used uninitialized whenever 'if' condition is true [-Wsometimes-uninitialized]
           if (!ucr->rsp_buf)
               ^~~~~~~~~~~~~
   drivers/misc/cardreader/rtsx_usb.c:678:9: note: uninitialized use occurs here
           return ret;
                  ^~~
   drivers/misc/cardreader/rtsx_usb.c:639:2: note: remove the 'if' if its condition is always false
           if (!ucr->rsp_buf)
           ^~~~~~~~~~~~~~~~~~
   drivers/misc/cardreader/rtsx_usb.c:622:9: note: initialize the variable 'ret' to silence this warning
           int ret;
                  ^
                   = 0

Fixes: 3776c7855985 ("misc: rtsx_usb: use separate command and response buffers")
Reported-by: kernel test robot <lkp@intel.com>
Cc: stable <stable@kernel.org>
Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
Link: https://lore.kernel.org/r/20220701165352.15687-1-skhan@linuxfoundation.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/misc/cardreader/rtsx_usb.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/misc/cardreader/rtsx_usb.c b/drivers/misc/cardreader/rtsx_usb.c
index 4e21080525094..f150d8769f198 100644
--- a/drivers/misc/cardreader/rtsx_usb.c
+++ b/drivers/misc/cardreader/rtsx_usb.c
@@ -636,8 +636,10 @@ static int rtsx_usb_probe(struct usb_interface *intf,
 		return -ENOMEM;
 
 	ucr->rsp_buf = kmalloc(IOBUF_SIZE, GFP_KERNEL);
-	if (!ucr->rsp_buf)
+	if (!ucr->rsp_buf) {
+		ret = -ENOMEM;
 		goto out_free_cmd_buf;
+	}
 
 	usb_set_intfdata(intf, ucr);
 
-- 
GitLab


From 3d5a2a396f19874b02196268a567a529ad5c7448 Mon Sep 17 00:00:00 2001
From: Karsten Graul <kgraul@linux.ibm.com>
Date: Fri, 1 Jul 2022 20:41:43 +0200
Subject: [PATCH 1482/1731] MAINTAINERS: add Wenjia as SMC maintainer

Add Wenjia as maintainer for Shared Memory Communications (SMC)
Sockets.

Acked-by: Wenjia Zhang <wenjia@linux.ibm.com>
Acked-by: Alexandra Winter <wintera@linux.ibm.com>
Signed-off-by: Karsten Graul <kgraul@linux.ibm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index e41bee2952bd9..ffb682773404e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -18179,6 +18179,7 @@ F:	drivers/misc/sgi-xp/
 
 SHARED MEMORY COMMUNICATIONS (SMC) SOCKETS
 M:	Karsten Graul <kgraul@linux.ibm.com>
+M:	Wenjia Zhang <wenjia@linux.ibm.com>
 L:	linux-s390@vger.kernel.org
 S:	Supported
 W:	http://www.ibm.com/developerworks/linux/linux390/
-- 
GitLab


From aa78fa905b4431c432071a878da99c2b37fc0e79 Mon Sep 17 00:00:00 2001
From: Helge Deller <deller@gmx.de>
Date: Fri, 1 Jul 2022 09:00:41 +0200
Subject: [PATCH 1483/1731] parisc: Fix vDSO signal breakage on 32-bit kernel

Addition of vDSO support for parisc in kernel v5.18 suddenly broke glibc
signal testcases on a 32-bit kernel.

The trampoline code (sigtramp.S) which is mapped into userspace includes
an offset to the context data on the stack, which is used by gdb and
glibc to get access to registers.

In a 32-bit kernel we used by mistake the offset into the compat context
(which is valid on a 64-bit kernel only) instead of the offset into the
"native" 32-bit context.

Reported-by: John David Anglin <dave.anglin@bell.net>
Tested-by: John David Anglin <dave.anglin@bell.net>
Fixes: 	df24e1783e6e ("parisc: Add vDSO support")
CC: stable@vger.kernel.org # 5.18
Signed-off-by: Helge Deller <deller@gmx.de>
---
 arch/parisc/kernel/asm-offsets.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/parisc/kernel/asm-offsets.c b/arch/parisc/kernel/asm-offsets.c
index 2673d57eeb008..94652e13c2603 100644
--- a/arch/parisc/kernel/asm-offsets.c
+++ b/arch/parisc/kernel/asm-offsets.c
@@ -224,8 +224,13 @@ int main(void)
 	BLANK();
 	DEFINE(ASM_SIGFRAME_SIZE, PARISC_RT_SIGFRAME_SIZE);
 	DEFINE(SIGFRAME_CONTEXT_REGS, offsetof(struct rt_sigframe, uc.uc_mcontext) - PARISC_RT_SIGFRAME_SIZE);
+#ifdef CONFIG_64BIT
 	DEFINE(ASM_SIGFRAME_SIZE32, PARISC_RT_SIGFRAME_SIZE32);
 	DEFINE(SIGFRAME_CONTEXT_REGS32, offsetof(struct compat_rt_sigframe, uc.uc_mcontext) - PARISC_RT_SIGFRAME_SIZE32);
+#else
+	DEFINE(ASM_SIGFRAME_SIZE32, PARISC_RT_SIGFRAME_SIZE);
+	DEFINE(SIGFRAME_CONTEXT_REGS32, offsetof(struct rt_sigframe, uc.uc_mcontext) - PARISC_RT_SIGFRAME_SIZE);
+#endif
 	BLANK();
 	DEFINE(ICACHE_BASE, offsetof(struct pdc_cache_info, ic_base));
 	DEFINE(ICACHE_STRIDE, offsetof(struct pdc_cache_info, ic_stride));
-- 
GitLab


From 7e6bc1f6cabcd30aba0b11219d8e01b952eacbb6 Mon Sep 17 00:00:00 2001
From: Pablo Neira Ayuso <pablo@netfilter.org>
Date: Sat, 2 Jul 2022 04:16:30 +0200
Subject: [PATCH 1484/1731] netfilter: nf_tables: stricter validation of
 element data

Make sure element data type and length do not mismatch the one specified
by the set declaration.

Fixes: 7d7402642eaf ("netfilter: nf_tables: variable sized set element keys / data")
Reported-by: Hugues ANGUELKOV <hanguelkov@randorisec.fr>
Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
---
 net/netfilter/nf_tables_api.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c
index 51144fc66889b..d6b59beab3a98 100644
--- a/net/netfilter/nf_tables_api.c
+++ b/net/netfilter/nf_tables_api.c
@@ -5213,13 +5213,20 @@ static int nft_setelem_parse_data(struct nft_ctx *ctx, struct nft_set *set,
 				  struct nft_data *data,
 				  struct nlattr *attr)
 {
+	u32 dtype;
 	int err;
 
 	err = nft_data_init(ctx, data, NFT_DATA_VALUE_MAXLEN, desc, attr);
 	if (err < 0)
 		return err;
 
-	if (desc->type != NFT_DATA_VERDICT && desc->len != set->dlen) {
+	if (set->dtype == NFT_DATA_VERDICT)
+		dtype = NFT_DATA_VERDICT;
+	else
+		dtype = NFT_DATA_VALUE;
+
+	if (dtype != desc->type ||
+	    set->dlen != desc->len) {
 		nft_data_release(data, desc->type);
 		return -EINVAL;
 	}
-- 
GitLab


From 9827a0e6e23bf43003cd3d5b7fb11baf59a35e1e Mon Sep 17 00:00:00 2001
From: Pablo Neira Ayuso <pablo@netfilter.org>
Date: Sat, 2 Jul 2022 04:16:31 +0200
Subject: [PATCH 1485/1731] netfilter: nft_set_pipapo: release elements in
 clone from abort path

New elements that reside in the clone are not released in case that the
transaction is aborted.

[16302.231754] ------------[ cut here ]------------
[16302.231756] WARNING: CPU: 0 PID: 100509 at net/netfilter/nf_tables_api.c:1864 nf_tables_chain_destroy+0x26/0x127 [nf_tables]
[...]
[16302.231882] CPU: 0 PID: 100509 Comm: nft Tainted: G        W         5.19.0-rc3+ #155
[...]
[16302.231887] RIP: 0010:nf_tables_chain_destroy+0x26/0x127 [nf_tables]
[16302.231899] Code: f3 fe ff ff 41 55 41 54 55 53 48 8b 6f 10 48 89 fb 48 c7 c7 82 96 d9 a0 8b 55 50 48 8b 75 58 e8 de f5 92 e0 83 7d 50 00 74 09 <0f> 0b 5b 5d 41 5c 41 5d c3 4c 8b 65 00 48 8b 7d 08 49 39 fc 74 05
[...]
[16302.231917] Call Trace:
[16302.231919]  <TASK>
[16302.231921]  __nf_tables_abort.cold+0x23/0x28 [nf_tables]
[16302.231934]  nf_tables_abort+0x30/0x50 [nf_tables]
[16302.231946]  nfnetlink_rcv_batch+0x41a/0x840 [nfnetlink]
[16302.231952]  ? __nla_validate_parse+0x48/0x190
[16302.231959]  nfnetlink_rcv+0x110/0x129 [nfnetlink]
[16302.231963]  netlink_unicast+0x211/0x340
[16302.231969]  netlink_sendmsg+0x21e/0x460

Add nft_set_pipapo_match_destroy() helper function to release the
elements in the lookup tables.

Stefano Brivio says: "We additionally look for elements pointers in the
cloned matching data if priv->dirty is set, because that means that
cloned data might point to additional elements we did not commit to the
working copy yet (such as the abort path case, but perhaps not limited
to it)."

Fixes: 3c4287f62044 ("nf_tables: Add set type for arbitrary concatenation of ranges")
Reviewed-by: Stefano Brivio <sbrivio@redhat.com>
Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
---
 net/netfilter/nft_set_pipapo.c | 48 +++++++++++++++++++++++-----------
 1 file changed, 33 insertions(+), 15 deletions(-)

diff --git a/net/netfilter/nft_set_pipapo.c b/net/netfilter/nft_set_pipapo.c
index 2c8051d8cca69..4f9299b9dcddc 100644
--- a/net/netfilter/nft_set_pipapo.c
+++ b/net/netfilter/nft_set_pipapo.c
@@ -2124,6 +2124,32 @@ out_scratch:
 	return err;
 }
 
+/**
+ * nft_set_pipapo_match_destroy() - Destroy elements from key mapping array
+ * @set:	nftables API set representation
+ * @m:		matching data pointing to key mapping array
+ */
+static void nft_set_pipapo_match_destroy(const struct nft_set *set,
+					 struct nft_pipapo_match *m)
+{
+	struct nft_pipapo_field *f;
+	int i, r;
+
+	for (i = 0, f = m->f; i < m->field_count - 1; i++, f++)
+		;
+
+	for (r = 0; r < f->rules; r++) {
+		struct nft_pipapo_elem *e;
+
+		if (r < f->rules - 1 && f->mt[r + 1].e == f->mt[r].e)
+			continue;
+
+		e = f->mt[r].e;
+
+		nft_set_elem_destroy(set, e, true);
+	}
+}
+
 /**
  * nft_pipapo_destroy() - Free private data for set and all committed elements
  * @set:	nftables API set representation
@@ -2132,26 +2158,13 @@ static void nft_pipapo_destroy(const struct nft_set *set)
 {
 	struct nft_pipapo *priv = nft_set_priv(set);
 	struct nft_pipapo_match *m;
-	struct nft_pipapo_field *f;
-	int i, r, cpu;
+	int cpu;
 
 	m = rcu_dereference_protected(priv->match, true);
 	if (m) {
 		rcu_barrier();
 
-		for (i = 0, f = m->f; i < m->field_count - 1; i++, f++)
-			;
-
-		for (r = 0; r < f->rules; r++) {
-			struct nft_pipapo_elem *e;
-
-			if (r < f->rules - 1 && f->mt[r + 1].e == f->mt[r].e)
-				continue;
-
-			e = f->mt[r].e;
-
-			nft_set_elem_destroy(set, e, true);
-		}
+		nft_set_pipapo_match_destroy(set, m);
 
 #ifdef NFT_PIPAPO_ALIGN
 		free_percpu(m->scratch_aligned);
@@ -2165,6 +2178,11 @@ static void nft_pipapo_destroy(const struct nft_set *set)
 	}
 
 	if (priv->clone) {
+		m = priv->clone;
+
+		if (priv->dirty)
+			nft_set_pipapo_match_destroy(set, m);
+
 #ifdef NFT_PIPAPO_ALIGN
 		free_percpu(priv->clone->scratch_aligned);
 #endif
-- 
GitLab


From 2545e12da4281f859c7b41b9681db15668e7f44d Mon Sep 17 00:00:00 2001
From: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Date: Fri, 1 Jul 2022 17:05:42 +0800
Subject: [PATCH 1486/1731] drm/mediatek: Remove mt8192 display rdma compatible
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The compatible “mediatek,mt8192-disp-rdma” is being used for reading
the data into DMA for back-end panel driver in mt8192 but there is
no difference between mt8183 and mt8192 in rdma driver.

Remove compatible “mediatek,mt8192-disp-rdma” from the driver and
should use “mediatek,mt8183-disp-rdma” as fallback in 8192 DTS
according to the mediatek,rdma.yaml.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220701090547.21429-2-allen-kh.cheng@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ------
 drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 2 --
 2 files changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index a000bba04e015..3b1905359b245 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -368,10 +368,6 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
 	.fifo_size = 5 * SZ_1K,
 };
 
-static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
-	.fifo_size = 5 * SZ_1K,
-};
-
 static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
 	.fifo_size = 1920,
 };
@@ -383,8 +379,6 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	  .data = &mt8173_rdma_driver_data},
 	{ .compatible = "mediatek,mt8183-disp-rdma",
 	  .data = &mt8183_rdma_driver_data},
-	{ .compatible = "mediatek,mt8192-disp-rdma",
-	  .data = &mt8192_rdma_driver_data},
 	{ .compatible = "mediatek,mt8195-disp-rdma",
 	  .data = &mt8195_rdma_driver_data},
 	{},
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 13a1bbe7ead7f..0551e1a8c941e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -617,8 +617,6 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8183-disp-rdma",
 	  .data = (void *)MTK_DISP_RDMA },
-	{ .compatible = "mediatek,mt8192-disp-rdma",
-	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8195-disp-rdma",
 	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8173-disp-ufoe",
-- 
GitLab


From 4a557a5d1a6145ea586dc9b17a9b4e5190c9c017 Mon Sep 17 00:00:00 2001
From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Thu, 30 Jun 2022 09:34:10 -0700
Subject: [PATCH 1487/1731] sparse: introduce conditional lock acquire function
 attribute

The kernel tends to try to avoid conditional locking semantics because
it makes it harder to think about and statically check locking rules,
but we do have a few fundamental locking primitives that take locks
conditionally - most obviously the 'trylock' functions.

That has always been a problem for 'sparse' checking for locking
imbalance, and we've had a special '__cond_lock()' macro that we've used
to let sparse know how the locking works:

    # define __cond_lock(x,c)        ((c) ? ({ __acquire(x); 1; }) : 0)

so that you can then use this to tell sparse that (for example) the
spinlock trylock macro ends up acquiring the lock when it succeeds, but
not when it fails:

    #define raw_spin_trylock(lock)  __cond_lock(lock, _raw_spin_trylock(lock))

and then sparse can follow along the locking rules when you have code like

        if (!spin_trylock(&dentry->d_lock))
                return LRU_SKIP;
	.. sparse sees that the lock is held here..
        spin_unlock(&dentry->d_lock);

and sparse ends up happy about the lock contexts.

However, this '__cond_lock()' use does result in very ugly header files,
and requires you to basically wrap the real function with that macro
that uses '__cond_lock'.  Which has made PeterZ NAK things that try to
fix sparse warnings over the years [1].

To solve this, there is now a very experimental patch to sparse that
basically does the exact same thing as '__cond_lock()' did, but using a
function attribute instead.  That seems to make PeterZ happy [2].

Note that this does not replace existing use of '__cond_lock()', but
only exposes the new proposed attribute and uses it for the previously
unannotated 'refcount_dec_and_lock()' family of functions.

For existing sparse installations, this will make no difference (a
negative output context was ignored), but if you have the experimental
sparse patch it will make sparse now understand code that uses those
functions, the same way '__cond_lock()' makes sparse understand the very
similar 'atomic_dec_and_lock()' uses that have the old '__cond_lock()'
annotations.

Note that in some cases this will silence existing context imbalance
warnings.  But in other cases it may end up exposing new sparse warnings
for code that sparse just didn't see the locking for at all before.

This is a trial, in other words.  I'd expect that if it ends up being
successful, and new sparse releases end up having this new attribute,
we'll migrate the old-style '__cond_lock()' users to use the new-style
'__cond_acquires' function attribute.

The actual experimental sparse patch was posted in [3].

Link: https://lore.kernel.org/all/20130930134434.GC12926@twins.programming.kicks-ass.net/ [1]
Link: https://lore.kernel.org/all/Yr60tWxN4P568x3W@worktop.programming.kicks-ass.net/ [2]
Link: https://lore.kernel.org/all/CAHk-=wjZfO9hGqJ2_hGQG3U_XzSh9_XaXze=HgPdvJbgrvASfA@mail.gmail.com/ [3]
Acked-by: Peter Zijlstra <peterz@infradead.org>
Cc: Alexander Aring <aahringo@redhat.com>
Cc: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
---
 include/linux/compiler_types.h | 2 ++
 include/linux/refcount.h       | 6 +++---
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/include/linux/compiler_types.h b/include/linux/compiler_types.h
index d08dfcb0ac687..4f2a819fd60a3 100644
--- a/include/linux/compiler_types.h
+++ b/include/linux/compiler_types.h
@@ -24,6 +24,7 @@ static inline void __chk_io_ptr(const volatile void __iomem *ptr) { }
 /* context/locking */
 # define __must_hold(x)	__attribute__((context(x,1,1)))
 # define __acquires(x)	__attribute__((context(x,0,1)))
+# define __cond_acquires(x) __attribute__((context(x,0,-1)))
 # define __releases(x)	__attribute__((context(x,1,0)))
 # define __acquire(x)	__context__(x,1)
 # define __release(x)	__context__(x,-1)
@@ -50,6 +51,7 @@ static inline void __chk_io_ptr(const volatile void __iomem *ptr) { }
 /* context/locking */
 # define __must_hold(x)
 # define __acquires(x)
+# define __cond_acquires(x)
 # define __releases(x)
 # define __acquire(x)	(void)0
 # define __release(x)	(void)0
diff --git a/include/linux/refcount.h b/include/linux/refcount.h
index b8a6e387f8f94..a62fcca974861 100644
--- a/include/linux/refcount.h
+++ b/include/linux/refcount.h
@@ -361,9 +361,9 @@ static inline void refcount_dec(refcount_t *r)
 
 extern __must_check bool refcount_dec_if_one(refcount_t *r);
 extern __must_check bool refcount_dec_not_one(refcount_t *r);
-extern __must_check bool refcount_dec_and_mutex_lock(refcount_t *r, struct mutex *lock);
-extern __must_check bool refcount_dec_and_lock(refcount_t *r, spinlock_t *lock);
+extern __must_check bool refcount_dec_and_mutex_lock(refcount_t *r, struct mutex *lock) __cond_acquires(lock);
+extern __must_check bool refcount_dec_and_lock(refcount_t *r, spinlock_t *lock) __cond_acquires(lock);
 extern __must_check bool refcount_dec_and_lock_irqsave(refcount_t *r,
 						       spinlock_t *lock,
-						       unsigned long *flags);
+						       unsigned long *flags) __cond_acquires(lock);
 #endif /* _LINUX_REFCOUNT_H */
-- 
GitLab


From b8d5109f50969ead9d49c3e8bd78ec1f82e548e3 Mon Sep 17 00:00:00 2001
From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sun, 3 Jul 2022 14:40:28 -0700
Subject: [PATCH 1488/1731] lockref: remove unused 'lockref_get_or_lock()'
 function

Looking at the conditional lock acquire functions in the kernel due to
the new sparse support (see commit 4a557a5d1a61 "sparse: introduce
conditional lock acquire function attribute"), it became obvious that
the lockref code has a couple of them, but they don't match the usual
naming convention for the other ones, and their return value logic is
also reversed.

In the other very similar places, the naming pattern is '*_and_lock()'
(eg 'atomic_put_and_lock()' and 'refcount_dec_and_lock()'), and the
function returns true when the lock is taken.

The lockref code is superficially very similar to the refcount code,
only with the special "atomic wrt the embedded lock" semantics.  But
instead of the '*_and_lock()' naming it uses '*_or_lock()'.

And instead of returning true in case it took the lock, it returns true
if it *didn't* take the lock.

Now, arguably the reflock code is quite logical: it really is a "either
decrement _or_ lock" kind of situation - and the return value is about
whether the operation succeeded without any special care needed.

So despite the similarities, the differences do make some sense, and
maybe it's not worth trying to unify the different conditional locking
primitives in this area.

But while looking at this all, it did become obvious that the
'lockref_get_or_lock()' function hasn't actually had any users for
almost a decade.

The only user it ever had was the shortlived 'd_rcu_to_refcount()'
function, and it got removed and replaced with 'lockref_get_not_dead()'
back in 2013 in commits 0d98439ea3c6 ("vfs: use lockred 'dead' flag to
mark unrecoverably dead dentries") and e5c832d55588 ("vfs: fix dentry
RCU to refcounting possibly sleeping dput()")

In fact, that single use was removed less than a week after the whole
function was introduced in commit b3abd80250c1 ("lockref: add
'lockref_get_or_lock() helper") so this function has been around for a
decade, but only had a user for six days.

Let's just put this mis-designed and unused function out of its misery.

We can think about the naming and semantic oddities of the remaining
'lockref_put_or_lock()' later, but at least that function has users.

And while the naming is different and the return value doesn't match,
that function matches the whole '{atomic,refcount}_dec_and_test()'
pattern much better (ie the magic happens when the count goes down to
zero, not when it is incremented from zero).

Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
---
 include/linux/lockref.h |  1 -
 lib/lockref.c           | 25 -------------------------
 2 files changed, 26 deletions(-)

diff --git a/include/linux/lockref.h b/include/linux/lockref.h
index 99f17cc8e1630..c3a1f78bc884d 100644
--- a/include/linux/lockref.h
+++ b/include/linux/lockref.h
@@ -38,7 +38,6 @@ extern void lockref_get(struct lockref *);
 extern int lockref_put_return(struct lockref *);
 extern int lockref_get_not_zero(struct lockref *);
 extern int lockref_put_not_zero(struct lockref *);
-extern int lockref_get_or_lock(struct lockref *);
 extern int lockref_put_or_lock(struct lockref *);
 
 extern void lockref_mark_dead(struct lockref *);
diff --git a/lib/lockref.c b/lib/lockref.c
index c6f0b183b937b..45e93ece8ba0d 100644
--- a/lib/lockref.c
+++ b/lib/lockref.c
@@ -110,31 +110,6 @@ int lockref_put_not_zero(struct lockref *lockref)
 }
 EXPORT_SYMBOL(lockref_put_not_zero);
 
-/**
- * lockref_get_or_lock - Increments count unless the count is 0 or dead
- * @lockref: pointer to lockref structure
- * Return: 1 if count updated successfully or 0 if count was zero
- * and we got the lock instead.
- */
-int lockref_get_or_lock(struct lockref *lockref)
-{
-	CMPXCHG_LOOP(
-		new.count++;
-		if (old.count <= 0)
-			break;
-	,
-		return 1;
-	);
-
-	spin_lock(&lockref->lock);
-	if (lockref->count <= 0)
-		return 0;
-	lockref->count++;
-	spin_unlock(&lockref->lock);
-	return 1;
-}
-EXPORT_SYMBOL(lockref_get_or_lock);
-
 /**
  * lockref_put_return - Decrement reference count if possible
  * @lockref: pointer to lockref structure
-- 
GitLab


From 88084a3df1672e131ddc1b4e39eeacfd39864acf Mon Sep 17 00:00:00 2001
From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sun, 3 Jul 2022 15:39:28 -0700
Subject: [PATCH 1489/1731] Linux 5.19-rc5

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 8973b285ce6c7..990d2ee79186c 100644
--- a/Makefile
+++ b/Makefile
@@ -2,7 +2,7 @@
 VERSION = 5
 PATCHLEVEL = 19
 SUBLEVEL = 0
-EXTRAVERSION = -rc4
+EXTRAVERSION = -rc5
 NAME = Superb Owl
 
 # *DOCUMENTATION*
-- 
GitLab


From a34b42f8690ce2b8360971ca5b886786ee1781af Mon Sep 17 00:00:00 2001
From: Etienne Carriere <etienne.carriere@linaro.org>
Date: Fri, 24 Jun 2022 11:00:55 +0200
Subject: [PATCH 1490/1731] ARM: dts: stm32: fix pwr regulators references to
 use scmi

Fixes stm32mp15*-scmi DTS files introduced in [1] to also access PWR
regulators through SCMI service. This is needed since enabling secure
only access to RCC clock and reset controllers also enables secure
access only on PWR voltage regulators reg11, reg18 and usb33 hence
these must also be accessed through SCMI Voltage Domain protocol.
This change applies on commit [2] that already corrects issues from
commit [1].

Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Link: [1] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-7-alexandre.torgue@foss.st.com
Link: [2] https://lore.kernel.org/linux-arm-kernel/20220613071920.5463-1-alexandre.torgue@foss.st.com
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
---
 arch/arm/boot/dts/stm32mp15-scmi.dtsi      | 52 ++++++++++++++++++++++
 arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts |  1 +
 arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts |  1 +
 3 files changed, 54 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/stm32mp15-scmi.dtsi
index e90cf3acd0b31..d2afb66674798 100644
--- a/arch/arm/boot/dts/stm32mp15-scmi.dtsi
+++ b/arch/arm/boot/dts/stm32mp15-scmi.dtsi
@@ -27,6 +27,37 @@
 				reg = <0x16>;
 				#reset-cells = <1>;
 			};
+
+			scmi_voltd: protocol@17 {
+				reg = <0x17>;
+
+				scmi_reguls: regulators {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					scmi_reg11: reg11@0 {
+						reg = <0>;
+						regulator-name = "reg11";
+						regulator-min-microvolt = <1100000>;
+						regulator-max-microvolt = <1100000>;
+					};
+
+					scmi_reg18: reg18@1 {
+						voltd-name = "reg18";
+						reg = <1>;
+						regulator-name = "reg18";
+						regulator-min-microvolt = <1800000>;
+						regulator-max-microvolt = <1800000>;
+					};
+
+					scmi_usb33: usb33@2 {
+						reg = <2>;
+						regulator-name = "usb33";
+						regulator-min-microvolt = <3300000>;
+						regulator-max-microvolt = <3300000>;
+					};
+				};
+			};
 		};
 	};
 
@@ -45,3 +76,24 @@
 		};
 	};
 };
+
+&reg11 {
+	status = "disabled";
+};
+
+&reg18 {
+	status = "disabled";
+};
+
+&usb33 {
+	status = "disabled";
+};
+
+&usbotg_hs {
+	usb33d-supply = <&scmi_usb33>;
+};
+
+&usbphyc {
+	vdda1v1-supply = <&scmi_reg11>;
+	vdda1v8-supply = <&scmi_reg18>;
+};
diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts
index 03226a5969046..97e4f94b0a24e 100644
--- a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts
+++ b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts
@@ -35,6 +35,7 @@
 };
 
 &dsi {
+	phy-dsi-supply = <&scmi_reg18>;
 	clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
 };
 
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts
index 7842384ddbe45..3b9dd6f4ccc96 100644
--- a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts
@@ -36,6 +36,7 @@
 };
 
 &dsi {
+	phy-dsi-supply = <&scmi_reg18>;
 	clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
 };
 
-- 
GitLab


From 78ece8cce1ba0c3f3e5a7c6c1b914b3794f04c44 Mon Sep 17 00:00:00 2001
From: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Date: Fri, 24 Jun 2022 11:27:13 +0200
Subject: [PATCH 1491/1731] ARM: dts: stm32: use the correct clock source for
 CEC on stm32mp151

The peripheral clock of CEC is not LSE but CEC.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
---
 arch/arm/boot/dts/stm32mp151.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi
index 7fdc324b3cf95..c50f38f539f25 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -565,7 +565,7 @@
 			compatible = "st,stm32-cec";
 			reg = <0x40016000 0x400>;
 			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc CEC_K>, <&clk_lse>;
+			clocks = <&rcc CEC_K>, <&rcc CEC>;
 			clock-names = "cec", "hdmi-cec";
 			status = "disabled";
 		};
-- 
GitLab


From cfd7ea394cd3b70ba4d9d87ee7b88e37459036b0 Mon Sep 17 00:00:00 2001
From: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Date: Fri, 24 Jun 2022 11:27:14 +0200
Subject: [PATCH 1492/1731] ARM: dts: stm32: DSI should use LSE SCMI clock on
 DK1/ED1 STM32 board

LSE clock is provided by SCMI.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
---
 arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts | 4 ++++
 arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts
index 36371d6ed6604..e539cc80bef81 100644
--- a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts
+++ b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts
@@ -29,6 +29,10 @@
 	clocks = <&scmi_clk CK_SCMI_MPU>;
 };
 
+&dsi {
+	clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
+};
+
 &gpioz {
 	clocks = <&scmi_clk CK_SCMI_GPIOZ>;
 };
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts
index c1a79272c0688..9cf0a44d2f47e 100644
--- a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts
@@ -34,6 +34,10 @@
 	resets = <&scmi_reset RST_SCMI_CRYP1>;
 };
 
+&dsi {
+	clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
+};
+
 &gpioz {
 	clocks = <&scmi_clk CK_SCMI_GPIOZ>;
 };
-- 
GitLab


From bf74181e75c93a1b2b000ebf3c8b4c8c17cd59da Mon Sep 17 00:00:00 2001
From: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Date: Fri, 24 Jun 2022 11:27:15 +0200
Subject: [PATCH 1493/1731] ARM: dts: stm32: delete fixed clock node on
 STM32MP15-SCMI

Delete the node fixed clock managed by secure world with SCMI.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
---
 arch/arm/boot/dts/stm32mp15-scmi.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/stm32mp15-scmi.dtsi
index d2afb66674798..543f24c2f4f6b 100644
--- a/arch/arm/boot/dts/stm32mp15-scmi.dtsi
+++ b/arch/arm/boot/dts/stm32mp15-scmi.dtsi
@@ -97,3 +97,9 @@
 	vdda1v1-supply = <&scmi_reg11>;
 	vdda1v8-supply = <&scmi_reg18>;
 };
+
+/delete-node/ &clk_hse;
+/delete-node/ &clk_hsi;
+/delete-node/ &clk_lse;
+/delete-node/ &clk_lsi;
+/delete-node/ &clk_csi;
-- 
GitLab


From 1d0c1aadf1fd9f3de95d1532b3651e8634546e71 Mon Sep 17 00:00:00 2001
From: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Date: Tue, 21 Jun 2022 10:45:09 +0200
Subject: [PATCH 1494/1731] ARM: dts: stm32: add missing usbh clock and fix clk
 order on stm32mp15

The USBH composed of EHCI and OHCI controllers needs the PHY clock to be
initialized first, before enabling (gating) them. The reverse is also
required when going to suspend.
So, add USBPHY clock as 1st entry in both controllers, so the USBPHY PLL
gets enabled 1st upon controller init. Upon suspend/resume, this also makes
the clock to be disabled/re-enabled in the correct order.
This fixes some IRQ storm conditions seen when going to low-power, due to
PHY PLL being disabled before all clocks are cleanly gated.

Fixes: 949a0c0dec85 ("ARM: dts: stm32: add USB Host (USBH) support to stm32mp157c")
Fixes: db7be2cb87ae ("ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151")
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
---
 arch/arm/boot/dts/stm32mp151.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi
index c50f38f539f25..e04dda5ddd954 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -1474,7 +1474,7 @@
 		usbh_ohci: usb@5800c000 {
 			compatible = "generic-ohci";
 			reg = <0x5800c000 0x1000>;
-			clocks = <&rcc USBH>, <&usbphyc>;
+			clocks = <&usbphyc>, <&rcc USBH>;
 			resets = <&rcc USBH_R>;
 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
@@ -1483,7 +1483,7 @@
 		usbh_ehci: usb@5800d000 {
 			compatible = "generic-ehci";
 			reg = <0x5800d000 0x1000>;
-			clocks = <&rcc USBH>;
+			clocks = <&usbphyc>, <&rcc USBH>;
 			resets = <&rcc USBH_R>;
 			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 			companion = <&usbh_ohci>;
-- 
GitLab


From f1b4e32aca0811aa011c76e5d6cf2fa19224b386 Mon Sep 17 00:00:00 2001
From: Oliver Hartkopp <socketcan@hartkopp.net>
Date: Fri, 20 May 2022 20:32:39 +0200
Subject: [PATCH 1495/1731] can: bcm: use call_rcu() instead of costly
 synchronize_rcu()

In commit d5f9023fa61e ("can: bcm: delay release of struct bcm_op
after synchronize_rcu()") Thadeu Lima de Souza Cascardo introduced two
synchronize_rcu() calls in bcm_release() (only once at socket close)
and in bcm_delete_rx_op() (called on removal of each single bcm_op).

Unfortunately this slow removal of the bcm_op's affects user space
applications like cansniffer where the modification of a filter
removes 2048 bcm_op's which blocks the cansniffer application for
40(!) seconds.

In commit 181d4447905d ("can: gw: use call_rcu() instead of costly
synchronize_rcu()") Eric Dumazet replaced the synchronize_rcu() calls
with several call_rcu()'s to safely remove the data structures after
the removal of CAN ID subscriptions with can_rx_unregister() calls.

This patch adopts Erics approach for the can-bcm which should be
applicable since the removal of tasklet_kill() in bcm_remove_op() and
the introduction of the HRTIMER_MODE_SOFT timer handling in Linux 5.4.

Fixes: d5f9023fa61e ("can: bcm: delay release of struct bcm_op after synchronize_rcu()") # >= 5.4
Link: https://lore.kernel.org/all/20220520183239.19111-1-socketcan@hartkopp.net
Cc: stable@vger.kernel.org
Cc: Eric Dumazet <edumazet@google.com>
Cc: Norbert Slusarek <nslusarek@gmx.net>
Cc: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
Signed-off-by: Oliver Hartkopp <socketcan@hartkopp.net>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
 net/can/bcm.c | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/net/can/bcm.c b/net/can/bcm.c
index 65ee1b784a30f..e60161bec850a 100644
--- a/net/can/bcm.c
+++ b/net/can/bcm.c
@@ -100,6 +100,7 @@ static inline u64 get_u64(const struct canfd_frame *cp, int offset)
 
 struct bcm_op {
 	struct list_head list;
+	struct rcu_head rcu;
 	int ifindex;
 	canid_t can_id;
 	u32 flags;
@@ -718,10 +719,9 @@ static struct bcm_op *bcm_find_op(struct list_head *ops,
 	return NULL;
 }
 
-static void bcm_remove_op(struct bcm_op *op)
+static void bcm_free_op_rcu(struct rcu_head *rcu_head)
 {
-	hrtimer_cancel(&op->timer);
-	hrtimer_cancel(&op->thrtimer);
+	struct bcm_op *op = container_of(rcu_head, struct bcm_op, rcu);
 
 	if ((op->frames) && (op->frames != &op->sframe))
 		kfree(op->frames);
@@ -732,6 +732,14 @@ static void bcm_remove_op(struct bcm_op *op)
 	kfree(op);
 }
 
+static void bcm_remove_op(struct bcm_op *op)
+{
+	hrtimer_cancel(&op->timer);
+	hrtimer_cancel(&op->thrtimer);
+
+	call_rcu(&op->rcu, bcm_free_op_rcu);
+}
+
 static void bcm_rx_unreg(struct net_device *dev, struct bcm_op *op)
 {
 	if (op->rx_reg_dev == dev) {
@@ -757,6 +765,9 @@ static int bcm_delete_rx_op(struct list_head *ops, struct bcm_msg_head *mh,
 		if ((op->can_id == mh->can_id) && (op->ifindex == ifindex) &&
 		    (op->flags & CAN_FD_FRAME) == (mh->flags & CAN_FD_FRAME)) {
 
+			/* disable automatic timer on frame reception */
+			op->flags |= RX_NO_AUTOTIMER;
+
 			/*
 			 * Don't care if we're bound or not (due to netdev
 			 * problems) can_rx_unregister() is always a save
@@ -785,7 +796,6 @@ static int bcm_delete_rx_op(struct list_head *ops, struct bcm_msg_head *mh,
 						  bcm_rx_handler, op);
 
 			list_del(&op->list);
-			synchronize_rcu();
 			bcm_remove_op(op);
 			return 1; /* done */
 		}
-- 
GitLab


From 02514a067fad6df27c4b21c316c1af93066af06e Mon Sep 17 00:00:00 2001
From: Jakub Kicinski <kuba@kernel.org>
Date: Fri, 1 Jul 2022 20:12:07 -0700
Subject: [PATCH 1496/1731] docs: netdev: document that patch series length
 limit

We had been asking people to avoid massive patch series but it does
not appear in the FAQ.

Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 Documentation/process/maintainer-netdev.rst | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/Documentation/process/maintainer-netdev.rst b/Documentation/process/maintainer-netdev.rst
index c456b5225d664..79a10d05031e4 100644
--- a/Documentation/process/maintainer-netdev.rst
+++ b/Documentation/process/maintainer-netdev.rst
@@ -136,6 +136,20 @@ it to the maintainer to figure out what is the most recent and current
 version that should be applied. If there is any doubt, the maintainer
 will reply and ask what should be done.
 
+How do I divide my work into patches?
+-------------------------------------
+
+Put yourself in the shoes of the reviewer. Each patch is read separately
+and therefore should constitute a comprehensible step towards your stated
+goal.
+
+Avoid sending series longer than 15 patches. Larger series takes longer
+to review as reviewers will defer looking at it until they find a large
+chunk of time. A small series can be reviewed in a short time, so Maintainers
+just do it. As a result, a sequence of smaller series gets merged quicker and
+with better review coverage. Re-posting large series also increases the mailing
+list traffic.
+
 I made changes to only a few patches in a patch series should I resend only those changed?
 ------------------------------------------------------------------------------------------
 No, please resend the entire patch series and make sure you do number your
-- 
GitLab


From a24875641143fce726529e6d550b313c53eb5821 Mon Sep 17 00:00:00 2001
From: Jakub Kicinski <kuba@kernel.org>
Date: Fri, 1 Jul 2022 20:12:08 -0700
Subject: [PATCH 1497/1731] docs: netdev: document reverse xmas tree

Similarly to the 15 patch rule the reverse xmas tree is not
documented.

Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 Documentation/process/maintainer-netdev.rst | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/process/maintainer-netdev.rst b/Documentation/process/maintainer-netdev.rst
index 79a10d05031e4..8a9dae7a05247 100644
--- a/Documentation/process/maintainer-netdev.rst
+++ b/Documentation/process/maintainer-netdev.rst
@@ -197,6 +197,19 @@ it is requested that you make it look like this::
    * another line of text
    */
 
+What is "reverse xmas tree"?
+----------------------------
+
+Netdev has a convention for ordering local variables in functions.
+Order the variable declaration lines longest to shortest, e.g.::
+
+  struct scatterlist *sg;
+  struct sk_buff *skb;
+  int err, i;
+
+If there are dependencies between the variables preventing the ordering
+move the initialization out of line.
+
 I am working in existing code which uses non-standard formatting. Which formatting should I use?
 ------------------------------------------------------------------------------------------------
 Make your code follow the most recent guidelines, so that eventually all code
-- 
GitLab


From 5d407ca7389261c002c49068e4a11ed3bff0fc8e Mon Sep 17 00:00:00 2001
From: Jakub Kicinski <kuba@kernel.org>
Date: Fri, 1 Jul 2022 20:12:09 -0700
Subject: [PATCH 1498/1731] docs: netdev: add a cheat sheet for the rules

Summarize the rules we see broken most often and which may
be less familiar to kernel devs who are used to working outside
of netdev.

Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 Documentation/process/maintainer-netdev.rst | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/Documentation/process/maintainer-netdev.rst b/Documentation/process/maintainer-netdev.rst
index 8a9dae7a05247..d140070815955 100644
--- a/Documentation/process/maintainer-netdev.rst
+++ b/Documentation/process/maintainer-netdev.rst
@@ -6,6 +6,15 @@
 netdev FAQ
 ==========
 
+tl;dr
+-----
+
+ - designate your patch to a tree - ``[PATCH net]`` or ``[PATCH net-next]``
+ - for fixes the ``Fixes:`` tag is required, regardless of the tree
+ - don't post large series (> 15 patches), break them up
+ - don't repost your patches within one 24h period
+ - reverse xmas tree
+
 What is netdev?
 ---------------
 It is a mailing list for all network-related Linux stuff.  This
-- 
GitLab


From c6da4590fe819dfe28a4f8037a8dc1e056542fb4 Mon Sep 17 00:00:00 2001
From: Srinivas Neeli <srinivas.neeli@xilinx.com>
Date: Thu, 9 Jun 2022 13:54:32 +0530
Subject: [PATCH 1499/1731] Revert "can: xilinx_can: Limit CANFD brp to 2"

This reverts commit 05ca14fdb6fe65614e0652d03e44b02748d25af7.

On early silicon engineering samples observed bit shrinking issue when
we use brp as 1. Hence updated brp_min as 2. As in production silicon
this issue is fixed, so reverting the patch.

Link: https://lore.kernel.org/all/20220609082433.1191060-2-srinivas.neeli@xilinx.com
Signed-off-by: Srinivas Neeli <srinivas.neeli@xilinx.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
 drivers/net/can/xilinx_can.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c
index 8a3b7b103ca48..e179d311aa288 100644
--- a/drivers/net/can/xilinx_can.c
+++ b/drivers/net/can/xilinx_can.c
@@ -258,7 +258,7 @@ static const struct can_bittiming_const xcan_bittiming_const_canfd2 = {
 	.tseg2_min = 1,
 	.tseg2_max = 128,
 	.sjw_max = 128,
-	.brp_min = 2,
+	.brp_min = 1,
 	.brp_max = 256,
 	.brp_inc = 1,
 };
@@ -271,7 +271,7 @@ static const struct can_bittiming_const xcan_data_bittiming_const_canfd2 = {
 	.tseg2_min = 1,
 	.tseg2_max = 16,
 	.sjw_max = 16,
-	.brp_min = 2,
+	.brp_min = 1,
 	.brp_max = 256,
 	.brp_inc = 1,
 };
-- 
GitLab


From 374e11f1bde91545674233459e5a0416ba842b69 Mon Sep 17 00:00:00 2001
From: Duy Nguyen <duy.nguyen.rh@renesas.com>
Date: Mon, 4 Jul 2022 16:46:11 +0900
Subject: [PATCH 1500/1731] can: rcar_canfd: Fix data transmission failed on
 R-Car V3U

On R-Car V3U, this driver should use suitable register offset instead of
other SoCs' one. Otherwise, data transmission failed on R-Car V3U.

Fixes: 45721c406dcf ("can: rcar_canfd: Add support for r8a779a0 SoC")
Link: https://lore.kernel.org/all/20220704074611.957191-1-yoshihiro.shimoda.uh@renesas.com
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
 drivers/net/can/rcar/rcar_canfd.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
index 40a11445d021e..ba42cef10a532 100644
--- a/drivers/net/can/rcar/rcar_canfd.c
+++ b/drivers/net/can/rcar/rcar_canfd.c
@@ -1332,7 +1332,10 @@ static void rcar_canfd_set_bittiming(struct net_device *dev)
 		cfg = (RCANFD_DCFG_DTSEG1(gpriv, tseg1) | RCANFD_DCFG_DBRP(brp) |
 		       RCANFD_DCFG_DSJW(sjw) | RCANFD_DCFG_DTSEG2(gpriv, tseg2));
 
-		rcar_canfd_write(priv->base, RCANFD_F_DCFG(ch), cfg);
+		if (is_v3u(gpriv))
+			rcar_canfd_write(priv->base, RCANFD_V3U_DCFG(ch), cfg);
+		else
+			rcar_canfd_write(priv->base, RCANFD_F_DCFG(ch), cfg);
 		netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
 			   brp, sjw, tseg1, tseg2);
 	} else {
-- 
GitLab


From 2bda24ef95c0311ab93bda00db40486acf30bd0a Mon Sep 17 00:00:00 2001
From: Rhett Aultman <rhett.aultman@samsara.com>
Date: Sun, 3 Jul 2022 19:33:06 +0200
Subject: [PATCH 1501/1731] can: gs_usb: gs_usb_open/close(): fix memory leak

The gs_usb driver appears to suffer from a malady common to many USB
CAN adapter drivers in that it performs usb_alloc_coherent() to
allocate a number of USB request blocks (URBs) for RX, and then later
relies on usb_kill_anchored_urbs() to free them, but this doesn't
actually free them. As a result, this may be leaking DMA memory that's
been used by the driver.

This commit is an adaptation of the techniques found in the esd_usb2
driver where a similar design pattern led to a memory leak. It
explicitly frees the RX URBs and their DMA memory via a call to
usb_free_coherent(). Since the RX URBs were allocated in the
gs_can_open(), we remove them in gs_can_close() rather than in the
disconnect function as was done in esd_usb2.

For more information, see the 928150fad41b ("can: esd_usb2: fix memory
leak").

Link: https://lore.kernel.org/all/alpine.DEB.2.22.394.2206031547001.1630869@thelappy
Fixes: d08e973a77d1 ("can: gs_usb: Added support for the GS_USB CAN devices")
Cc: stable@vger.kernel.org
Signed-off-by: Rhett Aultman <rhett.aultman@samsara.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
 drivers/net/can/usb/gs_usb.c | 23 +++++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/net/can/usb/gs_usb.c b/drivers/net/can/usb/gs_usb.c
index b29ba9138866b..d3a658b444b5f 100644
--- a/drivers/net/can/usb/gs_usb.c
+++ b/drivers/net/can/usb/gs_usb.c
@@ -268,6 +268,8 @@ struct gs_can {
 
 	struct usb_anchor tx_submitted;
 	atomic_t active_tx_urbs;
+	void *rxbuf[GS_MAX_RX_URBS];
+	dma_addr_t rxbuf_dma[GS_MAX_RX_URBS];
 };
 
 /* usb interface struct */
@@ -742,6 +744,7 @@ static int gs_can_open(struct net_device *netdev)
 		for (i = 0; i < GS_MAX_RX_URBS; i++) {
 			struct urb *urb;
 			u8 *buf;
+			dma_addr_t buf_dma;
 
 			/* alloc rx urb */
 			urb = usb_alloc_urb(0, GFP_KERNEL);
@@ -752,7 +755,7 @@ static int gs_can_open(struct net_device *netdev)
 			buf = usb_alloc_coherent(dev->udev,
 						 dev->parent->hf_size_rx,
 						 GFP_KERNEL,
-						 &urb->transfer_dma);
+						 &buf_dma);
 			if (!buf) {
 				netdev_err(netdev,
 					   "No memory left for USB buffer\n");
@@ -760,6 +763,8 @@ static int gs_can_open(struct net_device *netdev)
 				return -ENOMEM;
 			}
 
+			urb->transfer_dma = buf_dma;
+
 			/* fill, anchor, and submit rx urb */
 			usb_fill_bulk_urb(urb,
 					  dev->udev,
@@ -781,10 +786,17 @@ static int gs_can_open(struct net_device *netdev)
 					   "usb_submit failed (err=%d)\n", rc);
 
 				usb_unanchor_urb(urb);
+				usb_free_coherent(dev->udev,
+						  sizeof(struct gs_host_frame),
+						  buf,
+						  buf_dma);
 				usb_free_urb(urb);
 				break;
 			}
 
+			dev->rxbuf[i] = buf;
+			dev->rxbuf_dma[i] = buf_dma;
+
 			/* Drop reference,
 			 * USB core will take care of freeing it
 			 */
@@ -842,13 +854,20 @@ static int gs_can_close(struct net_device *netdev)
 	int rc;
 	struct gs_can *dev = netdev_priv(netdev);
 	struct gs_usb *parent = dev->parent;
+	unsigned int i;
 
 	netif_stop_queue(netdev);
 
 	/* Stop polling */
 	parent->active_channels--;
-	if (!parent->active_channels)
+	if (!parent->active_channels) {
 		usb_kill_anchored_urbs(&parent->rx_submitted);
+		for (i = 0; i < GS_MAX_RX_URBS; i++)
+			usb_free_coherent(dev->udev,
+					  sizeof(struct gs_host_frame),
+					  dev->rxbuf[i],
+					  dev->rxbuf_dma[i]);
+	}
 
 	/* Stop sending URBs */
 	usb_kill_anchored_urbs(&dev->tx_submitted);
-- 
GitLab


From 562fed945ea482833667f85496eeda766d511386 Mon Sep 17 00:00:00 2001
From: Liang He <windhl@126.com>
Date: Sun, 19 Jun 2022 15:02:57 +0800
Subject: [PATCH 1502/1731] can: grcan: grcan_probe(): remove extra
 of_node_get()

In grcan_probe(), of_find_node_by_path() has already increased the
refcount. There is no need to call of_node_get() again, so remove it.

Link: https://lore.kernel.org/all/20220619070257.4067022-1-windhl@126.com
Fixes: 1e93ed26acf0 ("can: grcan: grcan_probe(): fix broken system id check for errata workaround needs")
Cc: stable@vger.kernel.org # v5.18
Cc: Andreas Larsson <andreas@gaisler.com>
Signed-off-by: Liang He <windhl@126.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
 drivers/net/can/grcan.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/net/can/grcan.c b/drivers/net/can/grcan.c
index 76df4807d3666..4c47c1055eff9 100644
--- a/drivers/net/can/grcan.c
+++ b/drivers/net/can/grcan.c
@@ -1646,7 +1646,6 @@ static int grcan_probe(struct platform_device *ofdev)
 	 */
 	sysid_parent = of_find_node_by_path("/ambapp0");
 	if (sysid_parent) {
-		of_node_get(sysid_parent);
 		err = of_property_read_u32(sysid_parent, "systemid", &sysid);
 		if (!err && ((sysid & GRLIB_VERSION_MASK) >=
 			     GRCAN_TXBUG_SAFE_GRLIB_VERSION))
-- 
GitLab


From 5b12933de4e76ec164031c18ce8e0904abf530d7 Mon Sep 17 00:00:00 2001
From: Marc Kleine-Budde <mkl@pengutronix.de>
Date: Mon, 23 May 2022 17:18:33 +0200
Subject: [PATCH 1503/1731] can: m_can: m_can_chip_config(): actually enable
 internal timestamping

In commit df06fd678260 ("can: m_can: m_can_chip_config(): enable and
configure internal timestamps") the timestamping in the m_can core
should be enabled. In peripheral mode, the RX'ed CAN frames, TX
compete frames and error events are sorted by the timestamp.

The above mentioned commit however forgot to enable the timestamping.
Add the missing bits to enable the timestamp counter to the write of
the Timestamp Counter Configuration register.

Link: https://lore.kernel.org/all/20220612212708.4081756-1-mkl@pengutronix.de
Fixes: df06fd678260 ("can: m_can: m_can_chip_config(): enable and configure internal timestamps")
Cc: <stable@vger.kernel.org> # 5.13
Cc: Torin Cooper-Bennun <torin@maxiluxsystems.com>
Reviewed-by: Chandrasekar Ramakrishnan <rcsekar@samsung.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
 drivers/net/can/m_can/m_can.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c
index 5d0c82d8b9a9f..03a22d493cf6b 100644
--- a/drivers/net/can/m_can/m_can.c
+++ b/drivers/net/can/m_can/m_can.c
@@ -1351,7 +1351,9 @@ static void m_can_chip_config(struct net_device *dev)
 	/* enable internal timestamp generation, with a prescalar of 16. The
 	 * prescalar is applied to the nominal bit timing
 	 */
-	m_can_write(cdev, M_CAN_TSCC, FIELD_PREP(TSCC_TCP_MASK, 0xf));
+	m_can_write(cdev, M_CAN_TSCC,
+		    FIELD_PREP(TSCC_TCP_MASK, 0xf) |
+		    FIELD_PREP(TSCC_TSS_MASK, TSCC_TSS_INTERNAL));
 
 	m_can_config_endisable(cdev, false);
 
-- 
GitLab


From 4c3333693f07313f5f0145a922f14a7d3c0f4f21 Mon Sep 17 00:00:00 2001
From: Marc Kleine-Budde <mkl@pengutronix.de>
Date: Mon, 30 May 2022 19:30:28 +0200
Subject: [PATCH 1504/1731] can: m_can: m_can_{read_fifo,echo_tx_event}():
 shift timestamp to full 32 bits

In commit 1be37d3b0414 ("can: m_can: fix periph RX path: use
rx-offload to ensure skbs are sent from softirq context") the RX path
for peripheral devices was switched to RX-offload.

Received CAN frames are pushed to RX-offload together with a
timestamp. RX-offload is designed to handle overflows of the timestamp
correctly, if 32 bit timestamps are provided.

The timestamps of m_can core are only 16 bits wide. So this patch
shifts them to full 32 bit before passing them to RX-offload.

Link: https://lore.kernel.org/all/20220612211410.4081390-1-mkl@pengutronix.de
Fixes: 1be37d3b0414 ("can: m_can: fix periph RX path: use rx-offload to ensure skbs are sent from softirq context")
Cc: <stable@vger.kernel.org> # 5.13
Cc: Torin Cooper-Bennun <torin@maxiluxsystems.com>
Reviewed-by: Chandrasekar Ramakrishnan <rcsekar@samsung.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
 drivers/net/can/m_can/m_can.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c
index 03a22d493cf6b..7931f9c71ef31 100644
--- a/drivers/net/can/m_can/m_can.c
+++ b/drivers/net/can/m_can/m_can.c
@@ -529,7 +529,7 @@ static int m_can_read_fifo(struct net_device *dev, u32 rxfs)
 	/* acknowledge rx fifo 0 */
 	m_can_write(cdev, M_CAN_RXF0A, fgi);
 
-	timestamp = FIELD_GET(RX_BUF_RXTS_MASK, fifo_header.dlc);
+	timestamp = FIELD_GET(RX_BUF_RXTS_MASK, fifo_header.dlc) << 16;
 
 	m_can_receive_skb(cdev, skb, timestamp);
 
@@ -1030,7 +1030,7 @@ static int m_can_echo_tx_event(struct net_device *dev)
 		}
 
 		msg_mark = FIELD_GET(TX_EVENT_MM_MASK, txe);
-		timestamp = FIELD_GET(TX_EVENT_TXTS_MASK, txe);
+		timestamp = FIELD_GET(TX_EVENT_TXTS_MASK, txe) << 16;
 
 		/* ack txe element */
 		m_can_write(cdev, M_CAN_TXEFA, FIELD_PREP(TXEFA_EFAI_MASK,
-- 
GitLab


From 1b18f09d31cfa7148df15a7d5c5e0e86f105f7d1 Mon Sep 17 00:00:00 2001
From: Rick Lindsley <ricklind@us.ibm.com>
Date: Sat, 2 Jul 2022 03:37:12 -0700
Subject: [PATCH 1505/1731] ibmvnic: Properly dispose of all skbs during a
 failover.

During a reset, there may have been transmits in flight that are no
longer valid and cannot be fulfilled.  Resetting and clearing the
queues is insufficient; each skb also needs to be explicitly freed
so that upper levels are not left waiting for confirmation of a
transmit that will never happen.  If this happens frequently enough,
the apparent backlog will cause TCP to begin "congestion control"
unnecessarily, culminating in permanently decreased throughput.

Fixes: d7c0ef36bde03 ("ibmvnic: Free and re-allocate scrqs when tx/rx scrqs change")
Tested-by: Nick Child <nnac123@linux.ibm.com>
Reviewed-by: Brian King <brking@linux.vnet.ibm.com>
Signed-off-by: Rick Lindsley <ricklind@us.ibm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/ibm/ibmvnic.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/net/ethernet/ibm/ibmvnic.c b/drivers/net/ethernet/ibm/ibmvnic.c
index 7e7fe5bdf1f8c..5ab7c0f81e9af 100644
--- a/drivers/net/ethernet/ibm/ibmvnic.c
+++ b/drivers/net/ethernet/ibm/ibmvnic.c
@@ -5981,6 +5981,15 @@ static int ibmvnic_reset_init(struct ibmvnic_adapter *adapter, bool reset)
 			release_sub_crqs(adapter, 0);
 			rc = init_sub_crqs(adapter);
 		} else {
+			/* no need to reinitialize completely, but we do
+			 * need to clean up transmits that were in flight
+			 * when we processed the reset.  Failure to do so
+			 * will confound the upper layer, usually TCP, by
+			 * creating the illusion of transmits that are
+			 * awaiting completion.
+			 */
+			clean_tx_pools(adapter);
+
 			rc = reset_sub_crq_queues(adapter);
 		}
 	} else {
-- 
GitLab


From 49f274c72357d2d74cba70b172cf369768909707 Mon Sep 17 00:00:00 2001
From: Jimmy Assarsson <extja@kvaser.com>
Date: Fri, 3 Jun 2022 10:38:18 +0200
Subject: [PATCH 1506/1731] can: kvaser_usb: replace run-time checks with
 struct kvaser_usb_driver_info

Unify and move compile-time known information into new struct
kvaser_usb_driver_info, in favor of run-time checks.

All Kvaser USBcanII supports listen-only mode and error counter
reporting.

Link: https://lore.kernel.org/all/20220603083820.800246-2-extja@kvaser.com
Suggested-by: Marc Kleine-Budde <mkl@pengutronix.de>
Cc: stable@vger.kernel.org
Signed-off-by: Jimmy Assarsson <extja@kvaser.com>
[mkl: move struct kvaser_usb_driver_info into kvaser_usb_core.c]
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
 drivers/net/can/usb/kvaser_usb/kvaser_usb.h   |  22 +-
 .../net/can/usb/kvaser_usb/kvaser_usb_core.c  | 274 ++++++++++--------
 .../net/can/usb/kvaser_usb/kvaser_usb_leaf.c  |  24 +-
 3 files changed, 172 insertions(+), 148 deletions(-)

diff --git a/drivers/net/can/usb/kvaser_usb/kvaser_usb.h b/drivers/net/can/usb/kvaser_usb/kvaser_usb.h
index 3a49257f9fa65..39d5bfd70ff42 100644
--- a/drivers/net/can/usb/kvaser_usb/kvaser_usb.h
+++ b/drivers/net/can/usb/kvaser_usb/kvaser_usb.h
@@ -35,9 +35,9 @@
 #define KVASER_USB_RX_BUFFER_SIZE		3072
 #define KVASER_USB_MAX_NET_DEVICES		5
 
-/* USB devices features */
-#define KVASER_USB_HAS_SILENT_MODE		BIT(0)
-#define KVASER_USB_HAS_TXRX_ERRORS		BIT(1)
+/* Kvaser USB device quirks */
+#define KVASER_USB_QUIRK_HAS_SILENT_MODE	BIT(0)
+#define KVASER_USB_QUIRK_HAS_TXRX_ERRORS	BIT(1)
 
 /* Device capabilities */
 #define KVASER_USB_CAP_BERR_CAP			0x01
@@ -65,12 +65,7 @@ struct kvaser_usb_dev_card_data_hydra {
 struct kvaser_usb_dev_card_data {
 	u32 ctrlmode_supported;
 	u32 capabilities;
-	union {
-		struct {
-			enum kvaser_usb_leaf_family family;
-		} leaf;
-		struct kvaser_usb_dev_card_data_hydra hydra;
-	};
+	struct kvaser_usb_dev_card_data_hydra hydra;
 };
 
 /* Context for an outstanding, not yet ACKed, transmission */
@@ -83,7 +78,7 @@ struct kvaser_usb {
 	struct usb_device *udev;
 	struct usb_interface *intf;
 	struct kvaser_usb_net_priv *nets[KVASER_USB_MAX_NET_DEVICES];
-	const struct kvaser_usb_dev_ops *ops;
+	const struct kvaser_usb_driver_info *driver_info;
 	const struct kvaser_usb_dev_cfg *cfg;
 
 	struct usb_endpoint_descriptor *bulk_in, *bulk_out;
@@ -165,6 +160,12 @@ struct kvaser_usb_dev_ops {
 				  u16 transid);
 };
 
+struct kvaser_usb_driver_info {
+	u32 quirks;
+	enum kvaser_usb_leaf_family family;
+	const struct kvaser_usb_dev_ops *ops;
+};
+
 struct kvaser_usb_dev_cfg {
 	const struct can_clock clock;
 	const unsigned int timestamp_freq;
@@ -184,4 +185,5 @@ int kvaser_usb_send_cmd_async(struct kvaser_usb_net_priv *priv, void *cmd,
 			      int len);
 
 int kvaser_usb_can_rx_over_error(struct net_device *netdev);
+
 #endif /* KVASER_USB_H */
diff --git a/drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c b/drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c
index e67658b53d02f..d5b293e673d86 100644
--- a/drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c
+++ b/drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c
@@ -61,8 +61,6 @@
 #define USB_USBCAN_R_V2_PRODUCT_ID		294
 #define USB_LEAF_LIGHT_R_V2_PRODUCT_ID		295
 #define USB_LEAF_LIGHT_HS_V2_OEM2_PRODUCT_ID	296
-#define USB_LEAF_PRODUCT_ID_END \
-	USB_LEAF_LIGHT_HS_V2_OEM2_PRODUCT_ID
 
 /* Kvaser USBCan-II devices product ids */
 #define USB_USBCAN_REVB_PRODUCT_ID		2
@@ -89,116 +87,144 @@
 #define USB_USBCAN_PRO_4HS_PRODUCT_ID		276
 #define USB_HYBRID_CANLIN_PRODUCT_ID		277
 #define USB_HYBRID_PRO_CANLIN_PRODUCT_ID	278
-#define USB_HYDRA_PRODUCT_ID_END \
-	USB_HYBRID_PRO_CANLIN_PRODUCT_ID
 
-static inline bool kvaser_is_leaf(const struct usb_device_id *id)
-{
-	return (id->idProduct >= USB_LEAF_DEVEL_PRODUCT_ID &&
-		id->idProduct <= USB_CAN_R_PRODUCT_ID) ||
-		(id->idProduct >= USB_LEAF_LITE_V2_PRODUCT_ID &&
-		 id->idProduct <= USB_LEAF_PRODUCT_ID_END);
-}
+static const struct kvaser_usb_driver_info kvaser_usb_driver_info_hydra = {
+	.quirks = 0,
+	.ops = &kvaser_usb_hydra_dev_ops,
+};
 
-static inline bool kvaser_is_usbcan(const struct usb_device_id *id)
-{
-	return id->idProduct >= USB_USBCAN_REVB_PRODUCT_ID &&
-	       id->idProduct <= USB_MEMORATOR_PRODUCT_ID;
-}
+static const struct kvaser_usb_driver_info kvaser_usb_driver_info_usbcan = {
+	.quirks = KVASER_USB_QUIRK_HAS_TXRX_ERRORS |
+		  KVASER_USB_QUIRK_HAS_SILENT_MODE,
+	.family = KVASER_USBCAN,
+	.ops = &kvaser_usb_leaf_dev_ops,
+};
 
-static inline bool kvaser_is_hydra(const struct usb_device_id *id)
-{
-	return id->idProduct >= USB_BLACKBIRD_V2_PRODUCT_ID &&
-	       id->idProduct <= USB_HYDRA_PRODUCT_ID_END;
-}
+static const struct kvaser_usb_driver_info kvaser_usb_driver_info_leaf = {
+	.quirks = 0,
+	.family = KVASER_LEAF,
+	.ops = &kvaser_usb_leaf_dev_ops,
+};
+
+static const struct kvaser_usb_driver_info kvaser_usb_driver_info_leaf_err = {
+	.quirks = KVASER_USB_QUIRK_HAS_TXRX_ERRORS,
+	.family = KVASER_LEAF,
+	.ops = &kvaser_usb_leaf_dev_ops,
+};
+
+static const struct kvaser_usb_driver_info kvaser_usb_driver_info_leaf_err_listen = {
+	.quirks = KVASER_USB_QUIRK_HAS_TXRX_ERRORS |
+		  KVASER_USB_QUIRK_HAS_SILENT_MODE,
+	.family = KVASER_LEAF,
+	.ops = &kvaser_usb_leaf_dev_ops,
+};
 
 static const struct usb_device_id kvaser_usb_table[] = {
 	/* Leaf USB product IDs */
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_DEVEL_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_LITE_PRODUCT_ID) },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_DEVEL_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_LITE_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_PRO_PRODUCT_ID),
-		.driver_info = KVASER_USB_HAS_TXRX_ERRORS |
-			       KVASER_USB_HAS_SILENT_MODE },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf_err_listen },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_SPRO_PRODUCT_ID),
-		.driver_info = KVASER_USB_HAS_TXRX_ERRORS |
-			       KVASER_USB_HAS_SILENT_MODE },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf_err_listen },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_PRO_LS_PRODUCT_ID),
-		.driver_info = KVASER_USB_HAS_TXRX_ERRORS |
-			       KVASER_USB_HAS_SILENT_MODE },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf_err_listen },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_PRO_SWC_PRODUCT_ID),
-		.driver_info = KVASER_USB_HAS_TXRX_ERRORS |
-			       KVASER_USB_HAS_SILENT_MODE },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf_err_listen },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_PRO_LIN_PRODUCT_ID),
-		.driver_info = KVASER_USB_HAS_TXRX_ERRORS |
-			       KVASER_USB_HAS_SILENT_MODE },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf_err_listen },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_SPRO_LS_PRODUCT_ID),
-		.driver_info = KVASER_USB_HAS_TXRX_ERRORS |
-			       KVASER_USB_HAS_SILENT_MODE },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf_err_listen },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_SPRO_SWC_PRODUCT_ID),
-		.driver_info = KVASER_USB_HAS_TXRX_ERRORS |
-			       KVASER_USB_HAS_SILENT_MODE },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf_err_listen },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_MEMO2_DEVEL_PRODUCT_ID),
-		.driver_info = KVASER_USB_HAS_TXRX_ERRORS |
-			       KVASER_USB_HAS_SILENT_MODE },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf_err_listen },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_MEMO2_HSHS_PRODUCT_ID),
-		.driver_info = KVASER_USB_HAS_TXRX_ERRORS |
-			       KVASER_USB_HAS_SILENT_MODE },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf_err_listen },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_UPRO_HSHS_PRODUCT_ID),
-		.driver_info = KVASER_USB_HAS_TXRX_ERRORS },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_LITE_GI_PRODUCT_ID) },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf_err },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_LITE_GI_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_PRO_OBDII_PRODUCT_ID),
-		.driver_info = KVASER_USB_HAS_TXRX_ERRORS |
-			       KVASER_USB_HAS_SILENT_MODE },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf_err_listen },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_MEMO2_HSLS_PRODUCT_ID),
-		.driver_info = KVASER_USB_HAS_TXRX_ERRORS },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf_err },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_LITE_CH_PRODUCT_ID),
-		.driver_info = KVASER_USB_HAS_TXRX_ERRORS },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf_err },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_BLACKBIRD_SPRO_PRODUCT_ID),
-		.driver_info = KVASER_USB_HAS_TXRX_ERRORS },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf_err },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_OEM_MERCURY_PRODUCT_ID),
-		.driver_info = KVASER_USB_HAS_TXRX_ERRORS },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf_err },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_OEM_LEAF_PRODUCT_ID),
-		.driver_info = KVASER_USB_HAS_TXRX_ERRORS },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf_err },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_CAN_R_PRODUCT_ID),
-		.driver_info = KVASER_USB_HAS_TXRX_ERRORS },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_LITE_V2_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_MINI_PCIE_HS_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_LIGHT_HS_V2_OEM_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_USBCAN_LIGHT_2HS_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_MINI_PCIE_2HS_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_USBCAN_R_V2_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_LIGHT_R_V2_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_LIGHT_HS_V2_OEM2_PRODUCT_ID) },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf_err },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_LITE_V2_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_MINI_PCIE_HS_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_LIGHT_HS_V2_OEM_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_USBCAN_LIGHT_2HS_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_MINI_PCIE_2HS_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_USBCAN_R_V2_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_LIGHT_R_V2_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_LIGHT_HS_V2_OEM2_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf },
 
 	/* USBCANII USB product IDs */
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_USBCAN2_PRODUCT_ID),
-		.driver_info = KVASER_USB_HAS_TXRX_ERRORS },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_usbcan },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_USBCAN_REVB_PRODUCT_ID),
-		.driver_info = KVASER_USB_HAS_TXRX_ERRORS },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_usbcan },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_MEMORATOR_PRODUCT_ID),
-		.driver_info = KVASER_USB_HAS_TXRX_ERRORS },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_usbcan },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_VCI2_PRODUCT_ID),
-		.driver_info = KVASER_USB_HAS_TXRX_ERRORS },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_usbcan },
 
 	/* Minihydra USB product IDs */
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_BLACKBIRD_V2_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_MEMO_PRO_5HS_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_USBCAN_PRO_5HS_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_USBCAN_LIGHT_4HS_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_PRO_HS_V2_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_USBCAN_PRO_2HS_V2_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_MEMO_2HS_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_MEMO_PRO_2HS_V2_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_HYBRID_2CANLIN_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_ATI_USBCAN_PRO_2HS_V2_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_ATI_MEMO_PRO_2HS_V2_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_HYBRID_PRO_2CANLIN_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_U100_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_U100P_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_U100S_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_USBCAN_PRO_4HS_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_HYBRID_CANLIN_PRODUCT_ID) },
-	{ USB_DEVICE(KVASER_VENDOR_ID, USB_HYBRID_PRO_CANLIN_PRODUCT_ID) },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_BLACKBIRD_V2_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_hydra },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_MEMO_PRO_5HS_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_hydra },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_USBCAN_PRO_5HS_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_hydra },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_USBCAN_LIGHT_4HS_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_hydra },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_PRO_HS_V2_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_hydra },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_USBCAN_PRO_2HS_V2_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_hydra },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_MEMO_2HS_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_hydra },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_MEMO_PRO_2HS_V2_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_hydra },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_HYBRID_2CANLIN_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_hydra },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_ATI_USBCAN_PRO_2HS_V2_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_hydra },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_ATI_MEMO_PRO_2HS_V2_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_hydra },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_HYBRID_PRO_2CANLIN_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_hydra },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_U100_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_hydra },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_U100P_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_hydra },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_U100S_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_hydra },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_USBCAN_PRO_4HS_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_hydra },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_HYBRID_CANLIN_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_hydra },
+	{ USB_DEVICE(KVASER_VENDOR_ID, USB_HYBRID_PRO_CANLIN_PRODUCT_ID),
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_hydra },
 	{ }
 };
 MODULE_DEVICE_TABLE(usb, kvaser_usb_table);
@@ -285,6 +311,7 @@ int kvaser_usb_can_rx_over_error(struct net_device *netdev)
 static void kvaser_usb_read_bulk_callback(struct urb *urb)
 {
 	struct kvaser_usb *dev = urb->context;
+	const struct kvaser_usb_dev_ops *ops = dev->driver_info->ops;
 	int err;
 	unsigned int i;
 
@@ -301,8 +328,8 @@ static void kvaser_usb_read_bulk_callback(struct urb *urb)
 		goto resubmit_urb;
 	}
 
-	dev->ops->dev_read_bulk_callback(dev, urb->transfer_buffer,
-					 urb->actual_length);
+	ops->dev_read_bulk_callback(dev, urb->transfer_buffer,
+				    urb->actual_length);
 
 resubmit_urb:
 	usb_fill_bulk_urb(urb, dev->udev,
@@ -396,6 +423,7 @@ static int kvaser_usb_open(struct net_device *netdev)
 {
 	struct kvaser_usb_net_priv *priv = netdev_priv(netdev);
 	struct kvaser_usb *dev = priv->dev;
+	const struct kvaser_usb_dev_ops *ops = dev->driver_info->ops;
 	int err;
 
 	err = open_candev(netdev);
@@ -406,11 +434,11 @@ static int kvaser_usb_open(struct net_device *netdev)
 	if (err)
 		goto error;
 
-	err = dev->ops->dev_set_opt_mode(priv);
+	err = ops->dev_set_opt_mode(priv);
 	if (err)
 		goto error;
 
-	err = dev->ops->dev_start_chip(priv);
+	err = ops->dev_start_chip(priv);
 	if (err) {
 		netdev_warn(netdev, "Cannot start device, error %d\n", err);
 		goto error;
@@ -467,22 +495,23 @@ static int kvaser_usb_close(struct net_device *netdev)
 {
 	struct kvaser_usb_net_priv *priv = netdev_priv(netdev);
 	struct kvaser_usb *dev = priv->dev;
+	const struct kvaser_usb_dev_ops *ops = dev->driver_info->ops;
 	int err;
 
 	netif_stop_queue(netdev);
 
-	err = dev->ops->dev_flush_queue(priv);
+	err = ops->dev_flush_queue(priv);
 	if (err)
 		netdev_warn(netdev, "Cannot flush queue, error %d\n", err);
 
-	if (dev->ops->dev_reset_chip) {
-		err = dev->ops->dev_reset_chip(dev, priv->channel);
+	if (ops->dev_reset_chip) {
+		err = ops->dev_reset_chip(dev, priv->channel);
 		if (err)
 			netdev_warn(netdev, "Cannot reset card, error %d\n",
 				    err);
 	}
 
-	err = dev->ops->dev_stop_chip(priv);
+	err = ops->dev_stop_chip(priv);
 	if (err)
 		netdev_warn(netdev, "Cannot stop device, error %d\n", err);
 
@@ -521,6 +550,7 @@ static netdev_tx_t kvaser_usb_start_xmit(struct sk_buff *skb,
 {
 	struct kvaser_usb_net_priv *priv = netdev_priv(netdev);
 	struct kvaser_usb *dev = priv->dev;
+	const struct kvaser_usb_dev_ops *ops = dev->driver_info->ops;
 	struct net_device_stats *stats = &netdev->stats;
 	struct kvaser_usb_tx_urb_context *context = NULL;
 	struct urb *urb;
@@ -563,8 +593,7 @@ static netdev_tx_t kvaser_usb_start_xmit(struct sk_buff *skb,
 		goto freeurb;
 	}
 
-	buf = dev->ops->dev_frame_to_cmd(priv, skb, &cmd_len,
-					 context->echo_index);
+	buf = ops->dev_frame_to_cmd(priv, skb, &cmd_len, context->echo_index);
 	if (!buf) {
 		stats->tx_dropped++;
 		dev_kfree_skb(skb);
@@ -648,15 +677,16 @@ static void kvaser_usb_remove_interfaces(struct kvaser_usb *dev)
 	}
 }
 
-static int kvaser_usb_init_one(struct kvaser_usb *dev,
-			       const struct usb_device_id *id, int channel)
+static int kvaser_usb_init_one(struct kvaser_usb *dev, int channel)
 {
 	struct net_device *netdev;
 	struct kvaser_usb_net_priv *priv;
+	const struct kvaser_usb_driver_info *driver_info = dev->driver_info;
+	const struct kvaser_usb_dev_ops *ops = driver_info->ops;
 	int err;
 
-	if (dev->ops->dev_reset_chip) {
-		err = dev->ops->dev_reset_chip(dev, channel);
+	if (ops->dev_reset_chip) {
+		err = ops->dev_reset_chip(dev, channel);
 		if (err)
 			return err;
 	}
@@ -685,20 +715,19 @@ static int kvaser_usb_init_one(struct kvaser_usb *dev,
 	priv->can.state = CAN_STATE_STOPPED;
 	priv->can.clock.freq = dev->cfg->clock.freq;
 	priv->can.bittiming_const = dev->cfg->bittiming_const;
-	priv->can.do_set_bittiming = dev->ops->dev_set_bittiming;
-	priv->can.do_set_mode = dev->ops->dev_set_mode;
-	if ((id->driver_info & KVASER_USB_HAS_TXRX_ERRORS) ||
+	priv->can.do_set_bittiming = ops->dev_set_bittiming;
+	priv->can.do_set_mode = ops->dev_set_mode;
+	if ((driver_info->quirks & KVASER_USB_QUIRK_HAS_TXRX_ERRORS) ||
 	    (priv->dev->card_data.capabilities & KVASER_USB_CAP_BERR_CAP))
-		priv->can.do_get_berr_counter = dev->ops->dev_get_berr_counter;
-	if (id->driver_info & KVASER_USB_HAS_SILENT_MODE)
+		priv->can.do_get_berr_counter = ops->dev_get_berr_counter;
+	if (driver_info->quirks & KVASER_USB_QUIRK_HAS_SILENT_MODE)
 		priv->can.ctrlmode_supported |= CAN_CTRLMODE_LISTENONLY;
 
 	priv->can.ctrlmode_supported |= dev->card_data.ctrlmode_supported;
 
 	if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) {
 		priv->can.data_bittiming_const = dev->cfg->data_bittiming_const;
-		priv->can.do_set_data_bittiming =
-					dev->ops->dev_set_data_bittiming;
+		priv->can.do_set_data_bittiming = ops->dev_set_data_bittiming;
 	}
 
 	netdev->flags |= IFF_ECHO;
@@ -729,29 +758,22 @@ static int kvaser_usb_probe(struct usb_interface *intf,
 	struct kvaser_usb *dev;
 	int err;
 	int i;
+	const struct kvaser_usb_driver_info *driver_info;
+	const struct kvaser_usb_dev_ops *ops;
+
+	driver_info = (const struct kvaser_usb_driver_info *)id->driver_info;
+	if (!driver_info)
+		return -ENODEV;
 
 	dev = devm_kzalloc(&intf->dev, sizeof(*dev), GFP_KERNEL);
 	if (!dev)
 		return -ENOMEM;
 
-	if (kvaser_is_leaf(id)) {
-		dev->card_data.leaf.family = KVASER_LEAF;
-		dev->ops = &kvaser_usb_leaf_dev_ops;
-	} else if (kvaser_is_usbcan(id)) {
-		dev->card_data.leaf.family = KVASER_USBCAN;
-		dev->ops = &kvaser_usb_leaf_dev_ops;
-	} else if (kvaser_is_hydra(id)) {
-		dev->ops = &kvaser_usb_hydra_dev_ops;
-	} else {
-		dev_err(&intf->dev,
-			"Product ID (%d) is not a supported Kvaser USB device\n",
-			id->idProduct);
-		return -ENODEV;
-	}
-
 	dev->intf = intf;
+	dev->driver_info = driver_info;
+	ops = driver_info->ops;
 
-	err = dev->ops->dev_setup_endpoints(dev);
+	err = ops->dev_setup_endpoints(dev);
 	if (err) {
 		dev_err(&intf->dev, "Cannot get usb endpoint(s)");
 		return err;
@@ -765,22 +787,22 @@ static int kvaser_usb_probe(struct usb_interface *intf,
 
 	dev->card_data.ctrlmode_supported = 0;
 	dev->card_data.capabilities = 0;
-	err = dev->ops->dev_init_card(dev);
+	err = ops->dev_init_card(dev);
 	if (err) {
 		dev_err(&intf->dev,
 			"Failed to initialize card, error %d\n", err);
 		return err;
 	}
 
-	err = dev->ops->dev_get_software_info(dev);
+	err = ops->dev_get_software_info(dev);
 	if (err) {
 		dev_err(&intf->dev,
 			"Cannot get software info, error %d\n", err);
 		return err;
 	}
 
-	if (dev->ops->dev_get_software_details) {
-		err = dev->ops->dev_get_software_details(dev);
+	if (ops->dev_get_software_details) {
+		err = ops->dev_get_software_details(dev);
 		if (err) {
 			dev_err(&intf->dev,
 				"Cannot get software details, error %d\n", err);
@@ -798,14 +820,14 @@ static int kvaser_usb_probe(struct usb_interface *intf,
 
 	dev_dbg(&intf->dev, "Max outstanding tx = %d URBs\n", dev->max_tx_urbs);
 
-	err = dev->ops->dev_get_card_info(dev);
+	err = ops->dev_get_card_info(dev);
 	if (err) {
 		dev_err(&intf->dev, "Cannot get card info, error %d\n", err);
 		return err;
 	}
 
-	if (dev->ops->dev_get_capabilities) {
-		err = dev->ops->dev_get_capabilities(dev);
+	if (ops->dev_get_capabilities) {
+		err = ops->dev_get_capabilities(dev);
 		if (err) {
 			dev_err(&intf->dev,
 				"Cannot get capabilities, error %d\n", err);
@@ -815,7 +837,7 @@ static int kvaser_usb_probe(struct usb_interface *intf,
 	}
 
 	for (i = 0; i < dev->nchannels; i++) {
-		err = kvaser_usb_init_one(dev, id, i);
+		err = kvaser_usb_init_one(dev, i);
 		if (err) {
 			kvaser_usb_remove_interfaces(dev);
 			return err;
diff --git a/drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c b/drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c
index c805b999c5436..5cf940ba3f7f1 100644
--- a/drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c
+++ b/drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c
@@ -404,7 +404,7 @@ kvaser_usb_leaf_frame_to_cmd(const struct kvaser_usb_net_priv *priv,
 				      sizeof(struct kvaser_cmd_tx_can);
 		cmd->u.tx_can.channel = priv->channel;
 
-		switch (dev->card_data.leaf.family) {
+		switch (dev->driver_info->family) {
 		case KVASER_LEAF:
 			cmd_tx_can_flags = &cmd->u.tx_can.leaf.flags;
 			break;
@@ -550,7 +550,7 @@ static int kvaser_usb_leaf_get_software_info_inner(struct kvaser_usb *dev)
 	if (err)
 		return err;
 
-	switch (dev->card_data.leaf.family) {
+	switch (dev->driver_info->family) {
 	case KVASER_LEAF:
 		kvaser_usb_leaf_get_software_info_leaf(dev, &cmd.u.leaf.softinfo);
 		break;
@@ -597,7 +597,7 @@ static int kvaser_usb_leaf_get_card_info(struct kvaser_usb *dev)
 
 	dev->nchannels = cmd.u.cardinfo.nchannels;
 	if (dev->nchannels > KVASER_USB_MAX_NET_DEVICES ||
-	    (dev->card_data.leaf.family == KVASER_USBCAN &&
+	    (dev->driver_info->family == KVASER_USBCAN &&
 	     dev->nchannels > MAX_USBCAN_NET_DEVICES))
 		return -EINVAL;
 
@@ -730,7 +730,7 @@ kvaser_usb_leaf_rx_error_update_can_state(struct kvaser_usb_net_priv *priv,
 	    new_state < CAN_STATE_BUS_OFF)
 		priv->can.can_stats.restarts++;
 
-	switch (dev->card_data.leaf.family) {
+	switch (dev->driver_info->family) {
 	case KVASER_LEAF:
 		if (es->leaf.error_factor) {
 			priv->can.can_stats.bus_error++;
@@ -809,7 +809,7 @@ static void kvaser_usb_leaf_rx_error(const struct kvaser_usb *dev,
 		}
 	}
 
-	switch (dev->card_data.leaf.family) {
+	switch (dev->driver_info->family) {
 	case KVASER_LEAF:
 		if (es->leaf.error_factor) {
 			cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
@@ -999,7 +999,7 @@ static void kvaser_usb_leaf_rx_can_msg(const struct kvaser_usb *dev,
 	stats = &priv->netdev->stats;
 
 	if ((cmd->u.rx_can_header.flag & MSG_FLAG_ERROR_FRAME) &&
-	    (dev->card_data.leaf.family == KVASER_LEAF &&
+	    (dev->driver_info->family == KVASER_LEAF &&
 	     cmd->id == CMD_LEAF_LOG_MESSAGE)) {
 		kvaser_usb_leaf_leaf_rx_error(dev, cmd);
 		return;
@@ -1015,7 +1015,7 @@ static void kvaser_usb_leaf_rx_can_msg(const struct kvaser_usb *dev,
 		return;
 	}
 
-	switch (dev->card_data.leaf.family) {
+	switch (dev->driver_info->family) {
 	case KVASER_LEAF:
 		rx_data = cmd->u.leaf.rx_can.data;
 		break;
@@ -1030,7 +1030,7 @@ static void kvaser_usb_leaf_rx_can_msg(const struct kvaser_usb *dev,
 		return;
 	}
 
-	if (dev->card_data.leaf.family == KVASER_LEAF && cmd->id ==
+	if (dev->driver_info->family == KVASER_LEAF && cmd->id ==
 	    CMD_LEAF_LOG_MESSAGE) {
 		cf->can_id = le32_to_cpu(cmd->u.leaf.log_message.id);
 		if (cf->can_id & KVASER_EXTENDED_FRAME)
@@ -1128,14 +1128,14 @@ static void kvaser_usb_leaf_handle_command(const struct kvaser_usb *dev,
 		break;
 
 	case CMD_LEAF_LOG_MESSAGE:
-		if (dev->card_data.leaf.family != KVASER_LEAF)
+		if (dev->driver_info->family != KVASER_LEAF)
 			goto warn;
 		kvaser_usb_leaf_rx_can_msg(dev, cmd);
 		break;
 
 	case CMD_CHIP_STATE_EVENT:
 	case CMD_CAN_ERROR_EVENT:
-		if (dev->card_data.leaf.family == KVASER_LEAF)
+		if (dev->driver_info->family == KVASER_LEAF)
 			kvaser_usb_leaf_leaf_rx_error(dev, cmd);
 		else
 			kvaser_usb_leaf_usbcan_rx_error(dev, cmd);
@@ -1147,12 +1147,12 @@ static void kvaser_usb_leaf_handle_command(const struct kvaser_usb *dev,
 
 	/* Ignored commands */
 	case CMD_USBCAN_CLOCK_OVERFLOW_EVENT:
-		if (dev->card_data.leaf.family != KVASER_USBCAN)
+		if (dev->driver_info->family != KVASER_USBCAN)
 			goto warn;
 		break;
 
 	case CMD_FLUSH_QUEUE_REPLY:
-		if (dev->card_data.leaf.family != KVASER_LEAF)
+		if (dev->driver_info->family != KVASER_LEAF)
 			goto warn;
 		break;
 
-- 
GitLab


From e6c80e601053ffdac5709f11ff3ec1e19ed05f7b Mon Sep 17 00:00:00 2001
From: Jimmy Assarsson <extja@kvaser.com>
Date: Fri, 3 Jun 2022 10:38:19 +0200
Subject: [PATCH 1507/1731] can: kvaser_usb: kvaser_usb_leaf: fix CAN clock
 frequency regression

The firmware of M32C based Leaf devices expects bittiming parameters
calculated for 16MHz clock. Since we use the actual clock frequency of
the device, the device may end up with wrong bittiming parameters,
depending on user requested parameters.

This regression affects M32C based Leaf devices with non-16MHz clock.

Fixes: fb12797ab1fe ("can: kvaser_usb: get CAN clock frequency from device")
Link: https://lore.kernel.org/all/20220603083820.800246-3-extja@kvaser.com
Cc: stable@vger.kernel.org
Signed-off-by: Jimmy Assarsson <extja@kvaser.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
 drivers/net/can/usb/kvaser_usb/kvaser_usb.h   |  1 +
 .../net/can/usb/kvaser_usb/kvaser_usb_core.c  | 33 ++++++++++++-------
 .../net/can/usb/kvaser_usb/kvaser_usb_leaf.c  | 25 +++++++++-----
 3 files changed, 38 insertions(+), 21 deletions(-)

diff --git a/drivers/net/can/usb/kvaser_usb/kvaser_usb.h b/drivers/net/can/usb/kvaser_usb/kvaser_usb.h
index 39d5bfd70ff42..c1f66cef2c3f7 100644
--- a/drivers/net/can/usb/kvaser_usb/kvaser_usb.h
+++ b/drivers/net/can/usb/kvaser_usb/kvaser_usb.h
@@ -38,6 +38,7 @@
 /* Kvaser USB device quirks */
 #define KVASER_USB_QUIRK_HAS_SILENT_MODE	BIT(0)
 #define KVASER_USB_QUIRK_HAS_TXRX_ERRORS	BIT(1)
+#define KVASER_USB_QUIRK_IGNORE_CLK_FREQ	BIT(2)
 
 /* Device capabilities */
 #define KVASER_USB_CAP_BERR_CAP			0x01
diff --git a/drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c b/drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c
index d5b293e673d86..f211bfcb1d97e 100644
--- a/drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c
+++ b/drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c
@@ -101,26 +101,33 @@ static const struct kvaser_usb_driver_info kvaser_usb_driver_info_usbcan = {
 };
 
 static const struct kvaser_usb_driver_info kvaser_usb_driver_info_leaf = {
-	.quirks = 0,
+	.quirks = KVASER_USB_QUIRK_IGNORE_CLK_FREQ,
 	.family = KVASER_LEAF,
 	.ops = &kvaser_usb_leaf_dev_ops,
 };
 
 static const struct kvaser_usb_driver_info kvaser_usb_driver_info_leaf_err = {
-	.quirks = KVASER_USB_QUIRK_HAS_TXRX_ERRORS,
+	.quirks = KVASER_USB_QUIRK_HAS_TXRX_ERRORS |
+		  KVASER_USB_QUIRK_IGNORE_CLK_FREQ,
 	.family = KVASER_LEAF,
 	.ops = &kvaser_usb_leaf_dev_ops,
 };
 
 static const struct kvaser_usb_driver_info kvaser_usb_driver_info_leaf_err_listen = {
 	.quirks = KVASER_USB_QUIRK_HAS_TXRX_ERRORS |
-		  KVASER_USB_QUIRK_HAS_SILENT_MODE,
+		  KVASER_USB_QUIRK_HAS_SILENT_MODE |
+		  KVASER_USB_QUIRK_IGNORE_CLK_FREQ,
 	.family = KVASER_LEAF,
 	.ops = &kvaser_usb_leaf_dev_ops,
 };
 
+static const struct kvaser_usb_driver_info kvaser_usb_driver_info_leafimx = {
+	.quirks = 0,
+	.ops = &kvaser_usb_leaf_dev_ops,
+};
+
 static const struct usb_device_id kvaser_usb_table[] = {
-	/* Leaf USB product IDs */
+	/* Leaf M32C USB product IDs */
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_DEVEL_PRODUCT_ID),
 		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_LITE_PRODUCT_ID),
@@ -161,22 +168,24 @@ static const struct usb_device_id kvaser_usb_table[] = {
 		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf_err },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_CAN_R_PRODUCT_ID),
 		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf_err },
+
+	/* Leaf i.MX28 USB product IDs */
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_LITE_V2_PRODUCT_ID),
-		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leafimx },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_MINI_PCIE_HS_PRODUCT_ID),
-		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leafimx },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_LIGHT_HS_V2_OEM_PRODUCT_ID),
-		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leafimx },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_USBCAN_LIGHT_2HS_PRODUCT_ID),
-		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leafimx },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_MINI_PCIE_2HS_PRODUCT_ID),
-		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leafimx },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_USBCAN_R_V2_PRODUCT_ID),
-		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leafimx },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_LIGHT_R_V2_PRODUCT_ID),
-		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leafimx },
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_LIGHT_HS_V2_OEM2_PRODUCT_ID),
-		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leaf },
+		.driver_info = (kernel_ulong_t)&kvaser_usb_driver_info_leafimx },
 
 	/* USBCANII USB product IDs */
 	{ USB_DEVICE(KVASER_VENDOR_ID, USB_USBCAN2_PRODUCT_ID),
diff --git a/drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c b/drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c
index 5cf940ba3f7f1..957144cee4149 100644
--- a/drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c
+++ b/drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c
@@ -524,16 +524,23 @@ static void kvaser_usb_leaf_get_software_info_leaf(struct kvaser_usb *dev,
 	dev->fw_version = le32_to_cpu(softinfo->fw_version);
 	dev->max_tx_urbs = le16_to_cpu(softinfo->max_outstanding_tx);
 
-	switch (sw_options & KVASER_USB_LEAF_SWOPTION_FREQ_MASK) {
-	case KVASER_USB_LEAF_SWOPTION_FREQ_16_MHZ_CLK:
+	if (dev->driver_info->quirks & KVASER_USB_QUIRK_IGNORE_CLK_FREQ) {
+		/* Firmware expects bittiming parameters calculated for 16MHz
+		 * clock, regardless of the actual clock
+		 */
 		dev->cfg = &kvaser_usb_leaf_dev_cfg_16mhz;
-		break;
-	case KVASER_USB_LEAF_SWOPTION_FREQ_24_MHZ_CLK:
-		dev->cfg = &kvaser_usb_leaf_dev_cfg_24mhz;
-		break;
-	case KVASER_USB_LEAF_SWOPTION_FREQ_32_MHZ_CLK:
-		dev->cfg = &kvaser_usb_leaf_dev_cfg_32mhz;
-		break;
+	} else {
+		switch (sw_options & KVASER_USB_LEAF_SWOPTION_FREQ_MASK) {
+		case KVASER_USB_LEAF_SWOPTION_FREQ_16_MHZ_CLK:
+			dev->cfg = &kvaser_usb_leaf_dev_cfg_16mhz;
+			break;
+		case KVASER_USB_LEAF_SWOPTION_FREQ_24_MHZ_CLK:
+			dev->cfg = &kvaser_usb_leaf_dev_cfg_24mhz;
+			break;
+		case KVASER_USB_LEAF_SWOPTION_FREQ_32_MHZ_CLK:
+			dev->cfg = &kvaser_usb_leaf_dev_cfg_32mhz;
+			break;
+		}
 	}
 }
 
-- 
GitLab


From b3b6df2c56d80b8c6740433cff5f016668b8de70 Mon Sep 17 00:00:00 2001
From: Jimmy Assarsson <extja@kvaser.com>
Date: Fri, 3 Jun 2022 10:38:20 +0200
Subject: [PATCH 1508/1731] can: kvaser_usb: kvaser_usb_leaf: fix bittiming
 limits

Use correct bittiming limits depending on device. For devices based on
USBcanII, Leaf M32C or Leaf i.MX28.

Fixes: 080f40a6fa28 ("can: kvaser_usb: Add support for Kvaser CAN/USB devices")
Fixes: b4f20130af23 ("can: kvaser_usb: add support for Kvaser Leaf v2 and usb mini PCIe")
Fixes: f5d4abea3ce0 ("can: kvaser_usb: Add support for the USBcan-II family")
Link: https://lore.kernel.org/all/20220603083820.800246-4-extja@kvaser.com
Cc: stable@vger.kernel.org
Signed-off-by: Jimmy Assarsson <extja@kvaser.com>
[mkl: remove stray netlink.h include]
[mkl: keep struct can_bittiming_const kvaser_usb_flexc_bittiming_const in kvaser_usb_hydra.c]
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
 drivers/net/can/usb/kvaser_usb/kvaser_usb.h   |  2 +
 .../net/can/usb/kvaser_usb/kvaser_usb_hydra.c |  4 +-
 .../net/can/usb/kvaser_usb/kvaser_usb_leaf.c  | 76 +++++++++++--------
 3 files changed, 47 insertions(+), 35 deletions(-)

diff --git a/drivers/net/can/usb/kvaser_usb/kvaser_usb.h b/drivers/net/can/usb/kvaser_usb/kvaser_usb.h
index c1f66cef2c3f7..eefcbe3aadce7 100644
--- a/drivers/net/can/usb/kvaser_usb/kvaser_usb.h
+++ b/drivers/net/can/usb/kvaser_usb/kvaser_usb.h
@@ -187,4 +187,6 @@ int kvaser_usb_send_cmd_async(struct kvaser_usb_net_priv *priv, void *cmd,
 
 int kvaser_usb_can_rx_over_error(struct net_device *netdev);
 
+extern const struct can_bittiming_const kvaser_usb_flexc_bittiming_const;
+
 #endif /* KVASER_USB_H */
diff --git a/drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c b/drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c
index a26823c5b62ad..5d70844ac0300 100644
--- a/drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c
+++ b/drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c
@@ -375,7 +375,7 @@ static const struct can_bittiming_const kvaser_usb_hydra_kcan_bittiming_c = {
 	.brp_inc = 1,
 };
 
-static const struct can_bittiming_const kvaser_usb_hydra_flexc_bittiming_c = {
+const struct can_bittiming_const kvaser_usb_flexc_bittiming_const = {
 	.name = "kvaser_usb_flex",
 	.tseg1_min = 4,
 	.tseg1_max = 16,
@@ -2052,7 +2052,7 @@ static const struct kvaser_usb_dev_cfg kvaser_usb_hydra_dev_cfg_flexc = {
 		.freq = 24 * MEGA /* Hz */,
 	},
 	.timestamp_freq = 1,
-	.bittiming_const = &kvaser_usb_hydra_flexc_bittiming_c,
+	.bittiming_const = &kvaser_usb_flexc_bittiming_const,
 };
 
 static const struct kvaser_usb_dev_cfg kvaser_usb_hydra_dev_cfg_rt = {
diff --git a/drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c b/drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c
index 957144cee4149..cc809ecd1e622 100644
--- a/drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c
+++ b/drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c
@@ -101,16 +101,6 @@
 #define USBCAN_ERROR_STATE_RX_ERROR	BIT(1)
 #define USBCAN_ERROR_STATE_BUSERROR	BIT(2)
 
-/* bittiming parameters */
-#define KVASER_USB_TSEG1_MIN		1
-#define KVASER_USB_TSEG1_MAX		16
-#define KVASER_USB_TSEG2_MIN		1
-#define KVASER_USB_TSEG2_MAX		8
-#define KVASER_USB_SJW_MAX		4
-#define KVASER_USB_BRP_MIN		1
-#define KVASER_USB_BRP_MAX		64
-#define KVASER_USB_BRP_INC		1
-
 /* ctrl modes */
 #define KVASER_CTRL_MODE_NORMAL		1
 #define KVASER_CTRL_MODE_SILENT		2
@@ -343,48 +333,68 @@ struct kvaser_usb_err_summary {
 	};
 };
 
-static const struct can_bittiming_const kvaser_usb_leaf_bittiming_const = {
-	.name = "kvaser_usb",
-	.tseg1_min = KVASER_USB_TSEG1_MIN,
-	.tseg1_max = KVASER_USB_TSEG1_MAX,
-	.tseg2_min = KVASER_USB_TSEG2_MIN,
-	.tseg2_max = KVASER_USB_TSEG2_MAX,
-	.sjw_max = KVASER_USB_SJW_MAX,
-	.brp_min = KVASER_USB_BRP_MIN,
-	.brp_max = KVASER_USB_BRP_MAX,
-	.brp_inc = KVASER_USB_BRP_INC,
+static const struct can_bittiming_const kvaser_usb_leaf_m16c_bittiming_const = {
+	.name = "kvaser_usb_ucii",
+	.tseg1_min = 4,
+	.tseg1_max = 16,
+	.tseg2_min = 2,
+	.tseg2_max = 8,
+	.sjw_max = 4,
+	.brp_min = 1,
+	.brp_max = 16,
+	.brp_inc = 1,
+};
+
+static const struct can_bittiming_const kvaser_usb_leaf_m32c_bittiming_const = {
+	.name = "kvaser_usb_leaf",
+	.tseg1_min = 3,
+	.tseg1_max = 16,
+	.tseg2_min = 2,
+	.tseg2_max = 8,
+	.sjw_max = 4,
+	.brp_min = 2,
+	.brp_max = 128,
+	.brp_inc = 2,
 };
 
-static const struct kvaser_usb_dev_cfg kvaser_usb_leaf_dev_cfg_8mhz = {
+static const struct kvaser_usb_dev_cfg kvaser_usb_leaf_usbcan_dev_cfg = {
 	.clock = {
 		.freq = 8 * MEGA /* Hz */,
 	},
 	.timestamp_freq = 1,
-	.bittiming_const = &kvaser_usb_leaf_bittiming_const,
+	.bittiming_const = &kvaser_usb_leaf_m16c_bittiming_const,
+};
+
+static const struct kvaser_usb_dev_cfg kvaser_usb_leaf_m32c_dev_cfg = {
+	.clock = {
+		.freq = 16 * MEGA /* Hz */,
+	},
+	.timestamp_freq = 1,
+	.bittiming_const = &kvaser_usb_leaf_m32c_bittiming_const,
 };
 
-static const struct kvaser_usb_dev_cfg kvaser_usb_leaf_dev_cfg_16mhz = {
+static const struct kvaser_usb_dev_cfg kvaser_usb_leaf_imx_dev_cfg_16mhz = {
 	.clock = {
 		.freq = 16 * MEGA /* Hz */,
 	},
 	.timestamp_freq = 1,
-	.bittiming_const = &kvaser_usb_leaf_bittiming_const,
+	.bittiming_const = &kvaser_usb_flexc_bittiming_const,
 };
 
-static const struct kvaser_usb_dev_cfg kvaser_usb_leaf_dev_cfg_24mhz = {
+static const struct kvaser_usb_dev_cfg kvaser_usb_leaf_imx_dev_cfg_24mhz = {
 	.clock = {
 		.freq = 24 * MEGA /* Hz */,
 	},
 	.timestamp_freq = 1,
-	.bittiming_const = &kvaser_usb_leaf_bittiming_const,
+	.bittiming_const = &kvaser_usb_flexc_bittiming_const,
 };
 
-static const struct kvaser_usb_dev_cfg kvaser_usb_leaf_dev_cfg_32mhz = {
+static const struct kvaser_usb_dev_cfg kvaser_usb_leaf_imx_dev_cfg_32mhz = {
 	.clock = {
 		.freq = 32 * MEGA /* Hz */,
 	},
 	.timestamp_freq = 1,
-	.bittiming_const = &kvaser_usb_leaf_bittiming_const,
+	.bittiming_const = &kvaser_usb_flexc_bittiming_const,
 };
 
 static void *
@@ -528,17 +538,17 @@ static void kvaser_usb_leaf_get_software_info_leaf(struct kvaser_usb *dev,
 		/* Firmware expects bittiming parameters calculated for 16MHz
 		 * clock, regardless of the actual clock
 		 */
-		dev->cfg = &kvaser_usb_leaf_dev_cfg_16mhz;
+		dev->cfg = &kvaser_usb_leaf_m32c_dev_cfg;
 	} else {
 		switch (sw_options & KVASER_USB_LEAF_SWOPTION_FREQ_MASK) {
 		case KVASER_USB_LEAF_SWOPTION_FREQ_16_MHZ_CLK:
-			dev->cfg = &kvaser_usb_leaf_dev_cfg_16mhz;
+			dev->cfg = &kvaser_usb_leaf_imx_dev_cfg_16mhz;
 			break;
 		case KVASER_USB_LEAF_SWOPTION_FREQ_24_MHZ_CLK:
-			dev->cfg = &kvaser_usb_leaf_dev_cfg_24mhz;
+			dev->cfg = &kvaser_usb_leaf_imx_dev_cfg_24mhz;
 			break;
 		case KVASER_USB_LEAF_SWOPTION_FREQ_32_MHZ_CLK:
-			dev->cfg = &kvaser_usb_leaf_dev_cfg_32mhz;
+			dev->cfg = &kvaser_usb_leaf_imx_dev_cfg_32mhz;
 			break;
 		}
 	}
@@ -565,7 +575,7 @@ static int kvaser_usb_leaf_get_software_info_inner(struct kvaser_usb *dev)
 		dev->fw_version = le32_to_cpu(cmd.u.usbcan.softinfo.fw_version);
 		dev->max_tx_urbs =
 			le16_to_cpu(cmd.u.usbcan.softinfo.max_outstanding_tx);
-		dev->cfg = &kvaser_usb_leaf_dev_cfg_8mhz;
+		dev->cfg = &kvaser_usb_leaf_usbcan_dev_cfg;
 		break;
 	}
 
-- 
GitLab


From 406cc9cdb3e8d644b15e8028948f091b82abdbca Mon Sep 17 00:00:00 2001
From: Thomas Kopp <thomas.kopp@microchip.com>
Date: Tue, 21 Dec 2021 22:24:52 +0000
Subject: [PATCH 1509/1731] can: mcp251xfd: mcp251xfd_regmap_crc_read():
 improve workaround handling for mcp2517fd

The mcp251xfd compatible chips have an erratum ([1], [2]), where the
received CRC doesn't match the calculated CRC. In commit
c7eb923c3caf ("can: mcp251xfd: mcp251xfd_regmap_crc_read(): work
around broken CRC on TBC register") the following workaround was
implementierend.

- If a CRC read error on the TBC register is detected and the first
  byte is 0x00 or 0x80, the most significant bit of the first byte is
  flipped and the CRC is calculated again.
- If the CRC now matches, the _original_ data is passed to the reader.
  For now we assume transferred data was OK.

Measurements on the mcp2517fd show that the workaround is applicable
not only of the lowest byte is 0x00 or 0x80, but also if 3 least
significant bits are set.

Update check on 1st data byte and workaround description accordingly.

[1] mcp2517fd: DS80000792C: "Incorrect CRC for certain READ_CRC commands"
[2] mcp2518fd: DS80000789C: "Incorrect CRC for certain READ_CRC commands"

Link: https://lore.kernel.org/all/DM4PR11MB53901D49578FE265B239E55AFB7C9@DM4PR11MB5390.namprd11.prod.outlook.com
Fixes: c7eb923c3caf ("can: mcp251xfd: mcp251xfd_regmap_crc_read(): work around broken CRC on TBC register")
Cc: stable@vger.kernel.org
Reported-by: Pavel Modilaynen <pavel.modilaynen@volvocars.com>
Signed-off-by: Thomas Kopp <thomas.kopp@microchip.com>
[mkl: split into 2 patches, update patch description and documentation]
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
 drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c b/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c
index 217510c12af55..211edd9ef0c98 100644
--- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c
+++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c
@@ -334,10 +334,12 @@ mcp251xfd_regmap_crc_read(void *context,
 		 * register. It increments once per SYS clock tick,
 		 * which is 20 or 40 MHz.
 		 *
-		 * Observation shows that if the lowest byte (which is
-		 * transferred first on the SPI bus) of that register
-		 * is 0x00 or 0x80 the calculated CRC doesn't always
-		 * match the transferred one.
+		 * Observation on the mcp2518fd shows that if the
+		 * lowest byte (which is transferred first on the SPI
+		 * bus) of that register is 0x00 or 0x80 the
+		 * calculated CRC doesn't always match the transferred
+		 * one. On the mcp2517fd this problem is not limited
+		 * to the first byte being 0x00 or 0x80.
 		 *
 		 * If the highest bit in the lowest byte is flipped
 		 * the transferred CRC matches the calculated one. We
@@ -346,7 +348,8 @@ mcp251xfd_regmap_crc_read(void *context,
 		 * correct.
 		 */
 		if (reg == MCP251XFD_REG_TBC &&
-		    (buf_rx->data[0] == 0x0 || buf_rx->data[0] == 0x80)) {
+		    ((buf_rx->data[0] & 0xf8) == 0x0 ||
+		     (buf_rx->data[0] & 0xf8) == 0x80)) {
 			/* Flip highest bit in lowest byte of le32 */
 			buf_rx->data[0] ^= 0x80;
 
-- 
GitLab


From e3d4ee7d5f7f5256dfe89219afcc7a2d553b731f Mon Sep 17 00:00:00 2001
From: Thomas Kopp <thomas.kopp@microchip.com>
Date: Tue, 21 Dec 2021 22:24:52 +0000
Subject: [PATCH 1510/1731] can: mcp251xfd: mcp251xfd_regmap_crc_read(): update
 workaround broken CRC on TBC register

The mcp251xfd compatible chips have an erratum ([1], [2]), where the
received CRC doesn't match the calculated CRC. In commit
c7eb923c3caf ("can: mcp251xfd: mcp251xfd_regmap_crc_read(): work
around broken CRC on TBC register") the following workaround was
implementierend.

- If a CRC read error on the TBC register is detected and the first
  byte is 0x00 or 0x80, the most significant bit of the first byte is
  flipped and the CRC is calculated again.
- If the CRC now matches, the _original_ data is passed to the reader.
  For now we assume transferred data was OK.

New investigations and simulations indicate that the CRC send by the
device is calculated on correct data, and the data is incorrectly
received by the SPI host controller.

Use flipped instead of original data and update workaround description
in mcp251xfd_regmap_crc_read().

[1] mcp2517fd: DS80000792C: "Incorrect CRC for certain READ_CRC commands"
[2] mcp2518fd: DS80000789C: "Incorrect CRC for certain READ_CRC commands"

Link: https://lore.kernel.org/all/DM4PR11MB53901D49578FE265B239E55AFB7C9@DM4PR11MB5390.namprd11.prod.outlook.com
Fixes: c7eb923c3caf ("can: mcp251xfd: mcp251xfd_regmap_crc_read(): work around broken CRC on TBC register")
Cc: stable@vger.kernel.org
Signed-off-by: Thomas Kopp <thomas.kopp@microchip.com>
[mkl: split into 2 patches, update patch description and documentation]
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
 drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c b/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c
index 211edd9ef0c98..92b7bc7f14b9e 100644
--- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c
+++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c
@@ -343,9 +343,8 @@ mcp251xfd_regmap_crc_read(void *context,
 		 *
 		 * If the highest bit in the lowest byte is flipped
 		 * the transferred CRC matches the calculated one. We
-		 * assume for now the CRC calculation in the chip
-		 * works on wrong data and the transferred data is
-		 * correct.
+		 * assume for now the CRC operates on the correct
+		 * data.
 		 */
 		if (reg == MCP251XFD_REG_TBC &&
 		    ((buf_rx->data[0] & 0xf8) == 0x0 ||
@@ -359,10 +358,8 @@ mcp251xfd_regmap_crc_read(void *context,
 								  val_len);
 			if (!err) {
 				/* If CRC is now correct, assume
-				 * transferred data was OK, flip bit
-				 * back to original value.
+				 * flipped data is OK.
 				 */
-				buf_rx->data[0] ^= 0x80;
 				goto out;
 			}
 		}
-- 
GitLab


From d5a972f561a003e302e4267340c57e8fbd096fa4 Mon Sep 17 00:00:00 2001
From: Marc Kleine-Budde <mkl@pengutronix.de>
Date: Mon, 6 Jun 2022 14:46:18 +0200
Subject: [PATCH 1511/1731] can: mcp251xfd: mcp251xfd_stop(): add missing
 hrtimer_cancel()

In commit 169d00a25658 ("can: mcp251xfd: add TX IRQ coalescing
support") software based TX coalescing was added to the driver. The
key idea is to keep the TX complete IRQ disabled for some time after
processing it and re-enable later by a hrtimer. When bringing the
interface down, this timer has to be stopped.

Add the missing hrtimer_cancel() of the tx_irq_time hrtimer to
mcp251xfd_stop().

Link: https://lore.kernel.org/all/20220620143942.891811-1-mkl@pengutronix.de
Fixes: 169d00a25658 ("can: mcp251xfd: add TX IRQ coalescing support")
Cc: stable@vger.kernel.org # v5.18
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
 drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c b/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c
index b212523902168..34b160024ce3b 100644
--- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c
+++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c
@@ -1650,6 +1650,7 @@ static int mcp251xfd_stop(struct net_device *ndev)
 	netif_stop_queue(ndev);
 	set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
 	hrtimer_cancel(&priv->rx_irq_timer);
+	hrtimer_cancel(&priv->tx_irq_timer);
 	mcp251xfd_chip_interrupts_disable(priv);
 	free_irq(ndev->irq, priv);
 	can_rx_offload_disable(&priv->offload);
-- 
GitLab


From 0ff32bfa0e794ccc3601de7158b522bf736fa63c Mon Sep 17 00:00:00 2001
From: Marc Kleine-Budde <mkl@pengutronix.de>
Date: Thu, 16 Jun 2022 11:38:00 +0200
Subject: [PATCH 1512/1731] can: mcp251xfd: mcp251xfd_register_get_dev_id():
 use correct length to read dev_id

The device ID register is 32 bits wide. The driver uses incorrectly
the size of a pointer to a u32 to calculate the length of the SPI
transfer. This results in a read of 2 registers on 64 bit platforms.
This is no problem on the Linux side, as the RX buffer of the SPI
transfer is large enough. In the mpc251xfd chip this results in the
read of an undocumented register. So far no problems were observed.

Fix the length of the SPI transfer to read the device ID register
only.

Link: https://lore.kernel.org/all/20220616094914.244440-1-mkl@pengutronix.de
Fixes: 55e5b97f003e ("can: mcp25xxfd: add driver for Microchip MCP25xxFD SPI CAN")
Reported-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
 drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c b/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c
index 34b160024ce3b..3160881e89d9e 100644
--- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c
+++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c
@@ -1778,7 +1778,7 @@ mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv *priv, u32 *dev_id,
 	xfer[0].len = sizeof(buf_tx->cmd);
 	xfer[0].speed_hz = priv->spi_max_speed_hz_slow;
 	xfer[1].rx_buf = buf_rx->data;
-	xfer[1].len = sizeof(dev_id);
+	xfer[1].len = sizeof(*dev_id);
 	xfer[1].speed_hz = priv->spi_max_speed_hz_fast;
 
 	mcp251xfd_spi_cmd_read_nocrc(&buf_tx->cmd, MCP251XFD_REG_DEVID);
-- 
GitLab


From 1c0e78a287e3493e22bde8553d02f3b89177eaf7 Mon Sep 17 00:00:00 2001
From: Marc Kleine-Budde <mkl@pengutronix.de>
Date: Mon, 20 Jun 2022 11:49:24 +0200
Subject: [PATCH 1513/1731] can: mcp251xfd: mcp251xfd_register_get_dev_id():
 fix endianness conversion

In mcp251xfd_register_get_dev_id() the device ID register is read with
handcrafted SPI transfers. As all registers, this register is in
little endian. Further it is not naturally aligned in struct
mcp251xfd_map_buf_nocrc::data. However after the transfer the register
content is converted from big endian to CPU endianness not taking care
of being unaligned.

Fix the conversion by converting from little endian to CPU endianness
taking the unaligned source into account.

Side note: So far the register content is 0x0 on all mcp251xfd
compatible chips, and is only used for an informative printk.

Link: https://lore.kernel.org/all/20220627092859.809042-1-mkl@pengutronix.de
Fixes: 55e5b97f003e ("can: mcp25xxfd: add driver for Microchip MCP25xxFD SPI CAN")
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
 drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c b/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c
index 3160881e89d9e..9b47b07162fe5 100644
--- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c
+++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c
@@ -12,6 +12,7 @@
 // Copyright (c) 2019 Martin Sperl <kernel@martin.sperl.org>
 //
 
+#include <asm/unaligned.h>
 #include <linux/bitfield.h>
 #include <linux/clk.h>
 #include <linux/device.h>
@@ -1787,7 +1788,7 @@ mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv *priv, u32 *dev_id,
 	if (err)
 		goto out_kfree_buf_tx;
 
-	*dev_id = be32_to_cpup((__be32 *)buf_rx->data);
+	*dev_id = get_unaligned_le32(buf_rx->data);
 	*effective_speed_hz_slow = xfer[0].effective_speed_hz;
 	*effective_speed_hz_fast = xfer[1].effective_speed_hz;
 
-- 
GitLab


From 887502826549caa7e4215fd9e628f48f14c0825a Mon Sep 17 00:00:00 2001
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
Date: Thu, 30 Jun 2022 14:16:54 +0200
Subject: [PATCH 1514/1731] powerpc/powernv: delay rng platform device creation
 until later in boot

The platform device for the rng must be created much later in boot.
Otherwise it tries to connect to a parent that doesn't yet exist,
resulting in this splat:

  [    0.000478] kobject: '(null)' ((____ptrval____)): is not initialized, yet kobject_get() is being called.
  [    0.002925] [c000000002a0fb30] [c00000000073b0bc] kobject_get+0x8c/0x100 (unreliable)
  [    0.003071] [c000000002a0fba0] [c00000000087e464] device_add+0xf4/0xb00
  [    0.003194] [c000000002a0fc80] [c000000000a7f6e4] of_device_add+0x64/0x80
  [    0.003321] [c000000002a0fcb0] [c000000000a800d0] of_platform_device_create_pdata+0xd0/0x1b0
  [    0.003476] [c000000002a0fd00] [c00000000201fa44] pnv_get_random_long_early+0x240/0x2e4
  [    0.003623] [c000000002a0fe20] [c000000002060c38] random_init+0xc0/0x214

This patch fixes the issue by doing the platform device creation inside
of machine_subsys_initcall.

Fixes: f3eac426657d ("powerpc/powernv: wire up rng during setup_arch")
Cc: stable@vger.kernel.org
Reported-by: Sachin Sant <sachinp@linux.ibm.com>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Tested-by: Sachin Sant <sachinp@linux.ibm.com>
[mpe: Change "of node" to "platform device" in change log]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220630121654.1939181-1-Jason@zx2c4.com
---
 arch/powerpc/platforms/powernv/rng.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/platforms/powernv/rng.c b/arch/powerpc/platforms/powernv/rng.c
index 463c78c52cc5d..3805ad13b8f3d 100644
--- a/arch/powerpc/platforms/powernv/rng.c
+++ b/arch/powerpc/platforms/powernv/rng.c
@@ -176,12 +176,8 @@ static int __init pnv_get_random_long_early(unsigned long *v)
 		    NULL) != pnv_get_random_long_early)
 		return 0;
 
-	for_each_compatible_node(dn, NULL, "ibm,power-rng") {
-		if (rng_create(dn))
-			continue;
-		/* Create devices for hwrng driver */
-		of_platform_device_create(dn, NULL, NULL);
-	}
+	for_each_compatible_node(dn, NULL, "ibm,power-rng")
+		rng_create(dn);
 
 	if (!ppc_md.get_random_seed)
 		return 0;
@@ -205,10 +201,18 @@ void __init pnv_rng_init(void)
 
 static int __init pnv_rng_late_init(void)
 {
+	struct device_node *dn;
 	unsigned long v;
+
 	/* In case it wasn't called during init for some other reason. */
 	if (ppc_md.get_random_seed == pnv_get_random_long_early)
 		pnv_get_random_long_early(&v);
+
+	if (ppc_md.get_random_seed == powernv_get_random_long) {
+		for_each_compatible_node(dn, NULL, "ibm,power-rng")
+			of_platform_device_create(dn, NULL, NULL);
+	}
+
 	return 0;
 }
 machine_subsys_initcall(powernv, pnv_rng_late_init);
-- 
GitLab


From 6e2c9105e0b743c92a157389d40f00b81bdd09fe Mon Sep 17 00:00:00 2001
From: John Veness <john-linux@pelago.org.uk>
Date: Fri, 24 Jun 2022 15:07:57 +0100
Subject: [PATCH 1515/1731] ALSA: usb-audio: Add quirks for MacroSilicon
 MS2100/MS2106 devices

Treat the claimed 96kHz 1ch in the descriptors as 48kHz 2ch, so that
the audio stream doesn't sound mono. Also fix initial stream
alignment, so that left and right channels are in the correct order.

Signed-off-by: John Veness <john-linux@pelago.org.uk>
Link: https://lore.kernel.org/r/20220624140757.28758-1-john-linux@pelago.org.uk
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/usb/quirks-table.h | 48 ++++++++++++++++++++++++++++++++++++++++
 sound/usb/quirks.c       |  3 +++
 2 files changed, 51 insertions(+)

diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h
index 4f56e1784932a..853da162fd18c 100644
--- a/sound/usb/quirks-table.h
+++ b/sound/usb/quirks-table.h
@@ -3802,6 +3802,54 @@ YAMAHA_DEVICE(0x7010, "UB99"),
 	}
 },
 
+/*
+ * MacroSilicon MS2100/MS2106 based AV capture cards
+ *
+ * These claim 96kHz 1ch in the descriptors, but are actually 48kHz 2ch.
+ * They also need QUIRK_FLAG_ALIGN_TRANSFER, which makes one wonder if
+ * they pretend to be 96kHz mono as a workaround for stereo being broken
+ * by that...
+ *
+ * They also have an issue with initial stream alignment that causes the
+ * channels to be swapped and out of phase, which is dealt with in quirks.c.
+ */
+{
+	USB_AUDIO_DEVICE(0x534d, 0x0021),
+	.driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) {
+		.vendor_name = "MacroSilicon",
+		.product_name = "MS210x",
+		.ifnum = QUIRK_ANY_INTERFACE,
+		.type = QUIRK_COMPOSITE,
+		.data = &(const struct snd_usb_audio_quirk[]) {
+			{
+				.ifnum = 2,
+				.type = QUIRK_AUDIO_STANDARD_MIXER,
+			},
+			{
+				.ifnum = 3,
+				.type = QUIRK_AUDIO_FIXED_ENDPOINT,
+				.data = &(const struct audioformat) {
+					.formats = SNDRV_PCM_FMTBIT_S16_LE,
+					.channels = 2,
+					.iface = 3,
+					.altsetting = 1,
+					.altset_idx = 1,
+					.attributes = 0,
+					.endpoint = 0x82,
+					.ep_attr = USB_ENDPOINT_XFER_ISOC |
+						USB_ENDPOINT_SYNC_ASYNC,
+					.rates = SNDRV_PCM_RATE_CONTINUOUS,
+					.rate_min = 48000,
+					.rate_max = 48000,
+				}
+			},
+			{
+				.ifnum = -1
+			}
+		}
+	}
+},
+
 /*
  * MacroSilicon MS2109 based HDMI capture cards
  *
diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c
index 12ce69b04f634..a7bcae0a2c75b 100644
--- a/sound/usb/quirks.c
+++ b/sound/usb/quirks.c
@@ -1478,6 +1478,7 @@ void snd_usb_set_format_quirk(struct snd_usb_substream *subs,
 	case USB_ID(0x041e, 0x3f19): /* E-Mu 0204 USB */
 		set_format_emu_quirk(subs, fmt);
 		break;
+	case USB_ID(0x534d, 0x0021): /* MacroSilicon MS2100/MS2106 */
 	case USB_ID(0x534d, 0x2109): /* MacroSilicon MS2109 */
 		subs->stream_offset_adj = 2;
 		break;
@@ -1908,6 +1909,8 @@ static const struct usb_audio_quirk_flags_table quirk_flags_table[] = {
 		   QUIRK_FLAG_IGNORE_CTL_ERROR),
 	DEVICE_FLG(0x413c, 0xa506, /* Dell AE515 sound bar */
 		   QUIRK_FLAG_GET_SAMPLE_RATE),
+	DEVICE_FLG(0x534d, 0x0021, /* MacroSilicon MS2100/MS2106 */
+		   QUIRK_FLAG_ALIGN_TRANSFER),
 	DEVICE_FLG(0x534d, 0x2109, /* MacroSilicon MS2109 */
 		   QUIRK_FLAG_ALIGN_TRANSFER),
 	DEVICE_FLG(0x1224, 0x2a25, /* Jieli Technology USB PHY 2.0 */
-- 
GitLab


From 11bea26929a1a3a9dd1a287b60c2f471701bf706 Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Fri, 24 Jun 2022 08:41:09 -0600
Subject: [PATCH 1516/1731] ALSA: hda/realtek: Add quirk for Clevo L140PU

Fixes headset detection on Clevo L140PU.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20220624144109.3957-1-tcrawford@system76.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/pci/hda/patch_realtek.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index cee69fa7e246a..007dd8b5e1f2f 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -9212,6 +9212,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
 	SND_PCI_QUIRK(0x1558, 0x70f4, "Clevo NH77EPY", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE),
 	SND_PCI_QUIRK(0x1558, 0x70f6, "Clevo NH77DPQ-Y", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE),
 	SND_PCI_QUIRK(0x1558, 0x7716, "Clevo NS50PU", ALC256_FIXUP_SYSTEM76_MIC_NO_PRESENCE),
+	SND_PCI_QUIRK(0x1558, 0x7718, "Clevo L140PU", ALC256_FIXUP_SYSTEM76_MIC_NO_PRESENCE),
 	SND_PCI_QUIRK(0x1558, 0x8228, "Clevo NR40BU", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE),
 	SND_PCI_QUIRK(0x1558, 0x8520, "Clevo NH50D[CD]", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE),
 	SND_PCI_QUIRK(0x1558, 0x8521, "Clevo NH77D[CD]", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE),
-- 
GitLab


From 4fb7c24f69c48fdc02ea7858dbd5a60ff08bf7e5 Mon Sep 17 00:00:00 2001
From: Egor Vorontsov <sdoregor@sdore.me>
Date: Mon, 27 Jun 2022 13:00:34 +0300
Subject: [PATCH 1517/1731] ALSA: usb-audio: Add quirk for Fiero SC-01

Fiero SC-01 is a USB sound card with two mono inputs and a single
stereo output. The inputs are composed into a single stereo stream.

The device uses a vendor-provided driver on Windows and does not work
at all without it. The driver mostly provides ASIO functionality, but
also alters the way the sound card is queried for sample rates and
clocks.

ALSA queries those failing with an EPIPE (same as Windows 10 does).
Presumably, the vendor-provided driver does not query it at all, simply
matching by VID:PID. Thus, I consider this a buggy firmware and adhere
to a set of fixed endpoint quirks instead.

The soundcard has an internal clock. Implicit feedback mode is required
for the playback.

I have updated my device to v1.1.0 from a Windows 10 VM using a vendor-
provided binary prior to the development, hoping for it to just begin
working. The device provides no obvious way to downgrade the firmware,
and regardless, there's no binary available for v1.0.0 anyway.

Thus, I will be getting another unit to extend the patch with support
for that. Expected to be a simple copy-paste of the existing one,
though.

There were no previous reports of that device in context of Linux
anywhere. Other issues have been reported though, but that's out of the
scope.

Signed-off-by: Egor Vorontsov <sdoregor@sdore.me>
Link: https://lore.kernel.org/r/20220627100041.2861494-1-sdoregor@sdore.me
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/usb/quirks-table.h | 68 ++++++++++++++++++++++++++++++++++++++++
 sound/usb/quirks.c       |  2 ++
 2 files changed, 70 insertions(+)

diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h
index 853da162fd18c..7067d314fecd4 100644
--- a/sound/usb/quirks-table.h
+++ b/sound/usb/quirks-table.h
@@ -4167,6 +4167,74 @@ YAMAHA_DEVICE(0x7010, "UB99"),
 		}
 	}
 },
+{
+	/*
+	 * Fiero SC-01 (firmware v1.1.0)
+	 */
+	USB_DEVICE(0x2b53, 0x0031),
+	.driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) {
+		.vendor_name = "Fiero",
+		.product_name = "SC-01",
+		.ifnum = QUIRK_ANY_INTERFACE,
+		.type = QUIRK_COMPOSITE,
+		.data = &(const struct snd_usb_audio_quirk[]) {
+			{
+				.ifnum = 0,
+				.type = QUIRK_AUDIO_STANDARD_INTERFACE
+			},
+			/* Playback */
+			{
+				.ifnum = 1,
+				.type = QUIRK_AUDIO_FIXED_ENDPOINT,
+				.data = &(const struct audioformat) {
+					.formats = SNDRV_PCM_FMTBIT_S32_LE,
+					.channels = 2,
+					.fmt_bits = 24,
+					.iface = 1,
+					.altsetting = 1,
+					.altset_idx = 1,
+					.endpoint = 0x01,
+					.ep_attr = USB_ENDPOINT_XFER_ISOC |
+						   USB_ENDPOINT_SYNC_ASYNC,
+					.rates = SNDRV_PCM_RATE_48000 |
+						 SNDRV_PCM_RATE_96000,
+					.rate_min = 48000,
+					.rate_max = 96000,
+					.nr_rates = 2,
+					.rate_table = (unsigned int[]) { 48000, 96000 },
+					.clock = 0x29
+				}
+			},
+			/* Capture */
+			{
+				.ifnum = 2,
+				.type = QUIRK_AUDIO_FIXED_ENDPOINT,
+				.data = &(const struct audioformat) {
+					.formats = SNDRV_PCM_FMTBIT_S32_LE,
+					.channels = 2,
+					.fmt_bits = 24,
+					.iface = 2,
+					.altsetting = 1,
+					.altset_idx = 1,
+					.endpoint = 0x82,
+					.ep_attr = USB_ENDPOINT_XFER_ISOC |
+						   USB_ENDPOINT_SYNC_ASYNC |
+						   USB_ENDPOINT_USAGE_IMPLICIT_FB,
+					.rates = SNDRV_PCM_RATE_48000 |
+						 SNDRV_PCM_RATE_96000,
+					.rate_min = 48000,
+					.rate_max = 96000,
+					.nr_rates = 2,
+					.rate_table = (unsigned int[]) { 48000, 96000 },
+					.clock = 0x29
+				}
+			},
+			{
+				.ifnum = -1
+			}
+		}
+	}
+},
 
 #undef USB_DEVICE_VENDOR_SPEC
 #undef USB_AUDIO_DEVICE
diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c
index a7bcae0a2c75b..51138350f03c5 100644
--- a/sound/usb/quirks.c
+++ b/sound/usb/quirks.c
@@ -1915,6 +1915,8 @@ static const struct usb_audio_quirk_flags_table quirk_flags_table[] = {
 		   QUIRK_FLAG_ALIGN_TRANSFER),
 	DEVICE_FLG(0x1224, 0x2a25, /* Jieli Technology USB PHY 2.0 */
 		   QUIRK_FLAG_GET_SAMPLE_RATE),
+	DEVICE_FLG(0x2b53, 0x0031, /* Fiero SC-01 (firmware v1.1.0) */
+		   QUIRK_FLAG_GENERIC_IMPLICIT_FB),
 
 	/* Vendor matches */
 	VENDOR_FLG(0x045e, /* MS Lifecam */
-- 
GitLab


From 2307a0e1ca0b5c1337b37ac6302f96e017ebac3c Mon Sep 17 00:00:00 2001
From: Egor Vorontsov <sdoregor@sdore.me>
Date: Mon, 27 Jun 2022 13:00:35 +0300
Subject: [PATCH 1518/1731] ALSA: usb-audio: Add quirk for Fiero SC-01 (fw
 v1.0.0)

The patch applies the same quirks used for SC-01 at firmware v1.1.0 to
the ones running v1.0.0, with respect to hard-coded sample rates.

I got two more units and successfully tested the patch series with both
firmwares.

The support is now complete (not accounting ASIO).

Signed-off-by: Egor Vorontsov <sdoregor@sdore.me>
Link: https://lore.kernel.org/r/20220627100041.2861494-2-sdoregor@sdore.me
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/usb/quirks-table.h | 132 +++++++++++++++++++++++++++++++++++++++
 sound/usb/quirks.c       |   4 ++
 2 files changed, 136 insertions(+)

diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h
index 7067d314fecd4..f93201a830b5a 100644
--- a/sound/usb/quirks-table.h
+++ b/sound/usb/quirks-table.h
@@ -4167,6 +4167,138 @@ YAMAHA_DEVICE(0x7010, "UB99"),
 		}
 	}
 },
+{
+	/*
+	 * Fiero SC-01 (firmware v1.0.0 @ 48 kHz)
+	 */
+	USB_DEVICE(0x2b53, 0x0023),
+	.driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) {
+		.vendor_name = "Fiero",
+		.product_name = "SC-01",
+		.ifnum = QUIRK_ANY_INTERFACE,
+		.type = QUIRK_COMPOSITE,
+		.data = &(const struct snd_usb_audio_quirk[]) {
+			{
+				.ifnum = 0,
+				.type = QUIRK_AUDIO_STANDARD_INTERFACE
+			},
+			/* Playback */
+			{
+				.ifnum = 1,
+				.type = QUIRK_AUDIO_FIXED_ENDPOINT,
+				.data = &(const struct audioformat) {
+					.formats = SNDRV_PCM_FMTBIT_S32_LE,
+					.channels = 2,
+					.fmt_bits = 24,
+					.iface = 1,
+					.altsetting = 1,
+					.altset_idx = 1,
+					.endpoint = 0x01,
+					.ep_attr = USB_ENDPOINT_XFER_ISOC |
+						   USB_ENDPOINT_SYNC_ASYNC,
+					.rates = SNDRV_PCM_RATE_48000,
+					.rate_min = 48000,
+					.rate_max = 48000,
+					.nr_rates = 1,
+					.rate_table = (unsigned int[]) { 48000 },
+					.clock = 0x29
+				}
+			},
+			/* Capture */
+			{
+				.ifnum = 2,
+				.type = QUIRK_AUDIO_FIXED_ENDPOINT,
+				.data = &(const struct audioformat) {
+					.formats = SNDRV_PCM_FMTBIT_S32_LE,
+					.channels = 2,
+					.fmt_bits = 24,
+					.iface = 2,
+					.altsetting = 1,
+					.altset_idx = 1,
+					.endpoint = 0x82,
+					.ep_attr = USB_ENDPOINT_XFER_ISOC |
+						   USB_ENDPOINT_SYNC_ASYNC |
+						   USB_ENDPOINT_USAGE_IMPLICIT_FB,
+					.rates = SNDRV_PCM_RATE_48000,
+					.rate_min = 48000,
+					.rate_max = 48000,
+					.nr_rates = 1,
+					.rate_table = (unsigned int[]) { 48000 },
+					.clock = 0x29
+				}
+			},
+			{
+				.ifnum = -1
+			}
+		}
+	}
+},
+{
+	/*
+	 * Fiero SC-01 (firmware v1.0.0 @ 96 kHz)
+	 */
+	USB_DEVICE(0x2b53, 0x0024),
+	.driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) {
+		.vendor_name = "Fiero",
+		.product_name = "SC-01",
+		.ifnum = QUIRK_ANY_INTERFACE,
+		.type = QUIRK_COMPOSITE,
+		.data = &(const struct snd_usb_audio_quirk[]) {
+			{
+				.ifnum = 0,
+				.type = QUIRK_AUDIO_STANDARD_INTERFACE
+			},
+			/* Playback */
+			{
+				.ifnum = 1,
+				.type = QUIRK_AUDIO_FIXED_ENDPOINT,
+				.data = &(const struct audioformat) {
+					.formats = SNDRV_PCM_FMTBIT_S32_LE,
+					.channels = 2,
+					.fmt_bits = 24,
+					.iface = 1,
+					.altsetting = 1,
+					.altset_idx = 1,
+					.endpoint = 0x01,
+					.ep_attr = USB_ENDPOINT_XFER_ISOC |
+						   USB_ENDPOINT_SYNC_ASYNC,
+					.rates = SNDRV_PCM_RATE_96000,
+					.rate_min = 96000,
+					.rate_max = 96000,
+					.nr_rates = 1,
+					.rate_table = (unsigned int[]) { 96000 },
+					.clock = 0x29
+				}
+			},
+			/* Capture */
+			{
+				.ifnum = 2,
+				.type = QUIRK_AUDIO_FIXED_ENDPOINT,
+				.data = &(const struct audioformat) {
+					.formats = SNDRV_PCM_FMTBIT_S32_LE,
+					.channels = 2,
+					.fmt_bits = 24,
+					.iface = 2,
+					.altsetting = 1,
+					.altset_idx = 1,
+					.endpoint = 0x82,
+					.ep_attr = USB_ENDPOINT_XFER_ISOC |
+						   USB_ENDPOINT_SYNC_ASYNC |
+						   USB_ENDPOINT_USAGE_IMPLICIT_FB,
+					.rates = SNDRV_PCM_RATE_96000,
+					.rate_min = 96000,
+					.rate_max = 96000,
+					.nr_rates = 1,
+					.rate_table = (unsigned int[]) { 96000 },
+					.clock = 0x29
+				}
+			},
+			{
+				.ifnum = -1
+			}
+		}
+	}
+},
 {
 	/*
 	 * Fiero SC-01 (firmware v1.1.0)
diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c
index 51138350f03c5..968d90caeefa0 100644
--- a/sound/usb/quirks.c
+++ b/sound/usb/quirks.c
@@ -1915,6 +1915,10 @@ static const struct usb_audio_quirk_flags_table quirk_flags_table[] = {
 		   QUIRK_FLAG_ALIGN_TRANSFER),
 	DEVICE_FLG(0x1224, 0x2a25, /* Jieli Technology USB PHY 2.0 */
 		   QUIRK_FLAG_GET_SAMPLE_RATE),
+	DEVICE_FLG(0x2b53, 0x0023, /* Fiero SC-01 (firmware v1.0.0 @ 48 kHz) */
+		   QUIRK_FLAG_GENERIC_IMPLICIT_FB),
+	DEVICE_FLG(0x2b53, 0x0024, /* Fiero SC-01 (firmware v1.0.0 @ 96 kHz) */
+		   QUIRK_FLAG_GENERIC_IMPLICIT_FB),
 	DEVICE_FLG(0x2b53, 0x0031, /* Fiero SC-01 (firmware v1.1.0) */
 		   QUIRK_FLAG_GENERIC_IMPLICIT_FB),
 
-- 
GitLab


From 0ec29ccf94eb4c32570555a882575eca9eec6467 Mon Sep 17 00:00:00 2001
From: Bill Wendling <morbo@google.com>
Date: Mon, 21 Mar 2022 10:49:12 -0700
Subject: [PATCH 1519/1731] soc: qcom: smem: use correct format characters

When compiling with -Wformat, clang emits the following warnings:

drivers/soc/qcom/smem.c:847:41: warning: format specifies type 'unsigned
short' but the argument has type 'unsigned int' [-Wformat]
                        dev_err(smem->dev, "bad host %hu\n", remote_host);
                                                     ~~~     ^~~~~~~~~~~
                                                     %u
./include/linux/dev_printk.h:144:65: note: expanded from macro 'dev_err'
        dev_printk_index_wrap(_dev_err, KERN_ERR, dev, dev_fmt(fmt), ##__VA_ARGS__)
                                                               ~~~     ^~~~~~~~~~~
./include/linux/dev_printk.h:110:23: note: expanded from macro 'dev_printk_index_wrap'
                _p_func(dev, fmt, ##__VA_ARGS__);                       \
                             ~~~    ^~~~~~~~~~~
drivers/soc/qcom/smem.c:852:47: warning: format specifies type 'unsigned
short' but the argument has type 'unsigned int' [-Wformat]
                        dev_err(smem->dev, "duplicate host %hu\n", remote_host);
                                                           ~~~     ^~~~~~~~~~~
                                                           %u
./include/linux/dev_printk.h:144:65: note: expanded from macro 'dev_err'
        dev_printk_index_wrap(_dev_err, KERN_ERR, dev, dev_fmt(fmt), ##__VA_ARGS__)
                                                               ~~~     ^~~~~~~~~~~
./include/linux/dev_printk.h:110:23: note: expanded from macro 'dev_printk_index_wrap'
                _p_func(dev, fmt, ##__VA_ARGS__);                       \
                             ~~~    ^~~~~~~~~~~

The types of these arguments are unconditionally defined, so this patch
updates the format character to the correct one and change type of
remote_host to "u16" to match with other types.

Signed-off-by: Bill Wendling <morbo@google.com>
Tested-by: Justin Stitt <jstitt007@gmail.com>
Reviewed-by: Justin Stitt <jstitt007@gmail.com>
Link: https://github.com/ClangBuiltLinux/linux/issues/378
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 drivers/soc/qcom/smem.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c
index 3e95835653eaa..4f163d62942c1 100644
--- a/drivers/soc/qcom/smem.c
+++ b/drivers/soc/qcom/smem.c
@@ -926,7 +926,7 @@ qcom_smem_enumerate_partitions(struct qcom_smem *smem, u16 local_host)
 	struct smem_partition_header *header;
 	struct smem_ptable_entry *entry;
 	struct smem_ptable *ptable;
-	unsigned int remote_host;
+	u16 remote_host;
 	u16 host0, host1;
 	int i;
 
@@ -951,12 +951,12 @@ qcom_smem_enumerate_partitions(struct qcom_smem *smem, u16 local_host)
 			continue;
 
 		if (remote_host >= SMEM_HOST_COUNT) {
-			dev_err(smem->dev, "bad host %hu\n", remote_host);
+			dev_err(smem->dev, "bad host %u\n", remote_host);
 			return -EINVAL;
 		}
 
 		if (smem->partitions[remote_host].virt_base) {
-			dev_err(smem->dev, "duplicate host %hu\n", remote_host);
+			dev_err(smem->dev, "duplicate host %u\n", remote_host);
 			return -EINVAL;
 		}
 
-- 
GitLab


From 0f15d785ff2d59884f6271bb4ba4522596f218c7 Mon Sep 17 00:00:00 2001
From: Hsin-Yi Wang <hsinyi@chromium.org>
Date: Thu, 30 Jun 2022 03:05:46 +0800
Subject: [PATCH 1520/1731] drm/mediatek: Ensure bridge disable happends before
 suspend

Make sure bridge_disable will be called before suspend by calling
drm_mode_config_helper_suspend() in .prepare callback.

Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220629190545.478113-1-hsinyi@chromium.org/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 0551e1a8c941e..e659dc84d7e51 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -826,8 +826,7 @@ static int mtk_drm_remove(struct platform_device *pdev)
 	return 0;
 }
 
-#ifdef CONFIG_PM_SLEEP
-static int mtk_drm_sys_suspend(struct device *dev)
+static int mtk_drm_sys_prepare(struct device *dev)
 {
 	struct mtk_drm_private *private = dev_get_drvdata(dev);
 	struct drm_device *drm = private->drm;
@@ -838,20 +837,21 @@ static int mtk_drm_sys_suspend(struct device *dev)
 	return ret;
 }
 
-static int mtk_drm_sys_resume(struct device *dev)
+static void mtk_drm_sys_complete(struct device *dev)
 {
 	struct mtk_drm_private *private = dev_get_drvdata(dev);
 	struct drm_device *drm = private->drm;
 	int ret;
 
 	ret = drm_mode_config_helper_resume(drm);
-
-	return ret;
+	if (ret)
+		dev_err(dev, "Failed to resume\n");
 }
-#endif
 
-static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
-			 mtk_drm_sys_resume);
+static const struct dev_pm_ops mtk_drm_pm_ops = {
+	.prepare = mtk_drm_sys_prepare,
+	.complete = mtk_drm_sys_complete,
+};
 
 static struct platform_driver mtk_drm_platform_driver = {
 	.probe	= mtk_drm_probe,
-- 
GitLab


From e32895fc7fdfd61be26a4fef12b0f012ce578756 Mon Sep 17 00:00:00 2001
From: Markus Schneider-Pargmann <msp@baylibre.com>
Date: Fri, 1 Jul 2022 11:58:30 +0800
Subject: [PATCH 1521/1731] dt-bindings: display: mediatek: dpi: Add DP_INTF
 compatible

DP_INTF is similar to DPI but does not have the exact same feature set
or register layouts.

DP_INTF is the sink of the display pipeline that is connected to the
DisplayPort controller and encoder unit. It takes the same clocks as
DPI.

Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220701035845.16458-2-rex-bc.chen@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 .../bindings/display/mediatek/mediatek,dpi.yaml       | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
index 77ee1b9239912..8e526a4b134e3 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -4,16 +4,16 @@
 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: mediatek DPI Controller Device Tree Bindings
+title: mediatek DPI and DP_INTF Controller
 
 maintainers:
   - CK Hu <ck.hu@mediatek.com>
   - Jitao shi <jitao.shi@mediatek.com>
 
 description: |
-  The Mediatek DPI function block is a sink of the display subsystem and
-  provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
-  output bus.
+  The Mediatek DPI and DP_INTF function blocks are a sink of the display
+  subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
+  parallel output bus.
 
 properties:
   compatible:
@@ -24,6 +24,7 @@ properties:
       - mediatek,mt8183-dpi
       - mediatek,mt8186-dpi
       - mediatek,mt8192-dpi
+      - mediatek,mt8195-dp-intf
 
   reg:
     maxItems: 1
@@ -55,7 +56,7 @@ properties:
     $ref: /schemas/graph.yaml#/properties/port
     description:
       Output port node. This port should be connected to the input port of an
-      attached HDMI or LVDS encoder chip.
+      attached HDMI, LVDS or DisplayPort encoder chip.
 
 required:
   - compatible
-- 
GitLab


From f294c89fbc3806d8c292a9ff9385acadb0f19233 Mon Sep 17 00:00:00 2001
From: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Date: Fri, 1 Jul 2022 11:58:31 +0800
Subject: [PATCH 1522/1731] dt-bindings: display: mediatek: dpi: Revise
 mediatek strings to correct format

Strings replacement:
- s/mediatek/MediaTek/ in title.
- s/Mediatek/MediaTek/ in description.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220701035845.16458-3-rex-bc.chen@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml    | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
index 8e526a4b134e3..5bb23e97cf332 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -4,14 +4,14 @@
 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: mediatek DPI and DP_INTF Controller
+title: MediaTek DPI and DP_INTF Controller
 
 maintainers:
   - CK Hu <ck.hu@mediatek.com>
   - Jitao shi <jitao.shi@mediatek.com>
 
 description: |
-  The Mediatek DPI and DP_INTF function blocks are a sink of the display
+  The MediaTek DPI and DP_INTF function blocks are a sink of the display
   subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
   parallel output bus.
 
-- 
GitLab


From 0bf0cb60116a4f8f44136d03ed8a47ea32f02f8e Mon Sep 17 00:00:00 2001
From: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Date: Fri, 1 Jul 2022 11:58:32 +0800
Subject: [PATCH 1523/1731] drm/mediatek: dpi: Add kernel document for struct
 mtk_dpi_conf

This driver will support dp_intf and there are many configs between dpi
and dp_intf. Therefore, we will add many configs in "struct mtk_dpi_conf".
To let this structure more readable, we add this kernel doc.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220701035845.16458-4-rex-bc.chen@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index e61cd67b978ff..f66a121ba0c90 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -118,6 +118,15 @@ struct mtk_dpi_yc_limit {
 	u16 c_bottom;
 };
 
+/**
+ * struct mtk_dpi_conf - Configuration of mediatek dpi.
+ * @cal_factor: Callback function to calculate factor value.
+ * @reg_h_fre_con: Register address of frequency control.
+ * @max_clock_khz: Max clock frequency supported for this SoCs in khz units.
+ * @edge_sel_en: Enable of edge selection.
+ * @output_fmts: Array of supported output formats.
+ * @num_output_fmts: Quantity of supported output formats.
+ */
 struct mtk_dpi_conf {
 	unsigned int (*cal_factor)(int clock);
 	u32 reg_h_fre_con;
-- 
GitLab


From c9ed0713b3c35fc45677707ba47f432cad95da56 Mon Sep 17 00:00:00 2001
From: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Date: Fri, 1 Jul 2022 11:58:33 +0800
Subject: [PATCH 1524/1731] drm/mediatek: dpi: Remove output format of YUV

DPI is not support output format as YUV, but there is the setting of
configuring output YUV. Therefore, remove them in this patch.

Fixes: 9e629c17aa8d ("drm/mediatek: Add DPI sub driver")
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220701035845.16458-5-rex-bc.chen@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 31 ++++++------------------------
 1 file changed, 6 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index f66a121ba0c90..3473ee18ad976 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -54,13 +54,7 @@ enum mtk_dpi_out_channel_swap {
 };
 
 enum mtk_dpi_out_color_format {
-	MTK_DPI_COLOR_FORMAT_RGB,
-	MTK_DPI_COLOR_FORMAT_RGB_FULL,
-	MTK_DPI_COLOR_FORMAT_YCBCR_444,
-	MTK_DPI_COLOR_FORMAT_YCBCR_422,
-	MTK_DPI_COLOR_FORMAT_XV_YCC,
-	MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL,
-	MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL
+	MTK_DPI_COLOR_FORMAT_RGB
 };
 
 struct mtk_dpi {
@@ -373,24 +367,11 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
 					enum mtk_dpi_out_color_format format)
 {
-	if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_444) ||
-	    (format == MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) {
-		mtk_dpi_config_yuv422_enable(dpi, false);
-		mtk_dpi_config_csc_enable(dpi, true);
-		mtk_dpi_config_swap_input(dpi, false);
-		mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR);
-	} else if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_422) ||
-		   (format == MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) {
-		mtk_dpi_config_yuv422_enable(dpi, true);
-		mtk_dpi_config_csc_enable(dpi, true);
-		mtk_dpi_config_swap_input(dpi, true);
-		mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB);
-	} else {
-		mtk_dpi_config_yuv422_enable(dpi, false);
-		mtk_dpi_config_csc_enable(dpi, false);
-		mtk_dpi_config_swap_input(dpi, false);
-		mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB);
-	}
+	/* only support RGB888 */
+	mtk_dpi_config_yuv422_enable(dpi, false);
+	mtk_dpi_config_csc_enable(dpi, false);
+	mtk_dpi_config_swap_input(dpi, false);
+	mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB);
 }
 
 static void mtk_dpi_dual_edge(struct mtk_dpi *dpi)
-- 
GitLab


From aed61ef6beb911cc043af0f2f291167663995065 Mon Sep 17 00:00:00 2001
From: Guillaume Ranquet <granquet@baylibre.com>
Date: Fri, 1 Jul 2022 11:58:44 +0800
Subject: [PATCH 1525/1731] drm/mediatek: dpi: Only enable dpi after the bridge
 is enabled

Enabling the dpi too early causes glitches on screen.

Move the call to mtk_dpi_enable() at the end of the bridge_enable
callback to ensure everything is setup properly before enabling dpi.

Fixes: 9e629c17aa8d ("drm/mediatek: Add DPI sub driver")
Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220701035845.16458-16-rex-bc.chen@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 3473ee18ad976..06af0af31e9bc 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -426,7 +426,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
 	if (dpi->pinctrl && dpi->pins_dpi)
 		pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi);
 
-	mtk_dpi_enable(dpi);
 	return 0;
 
 err_pixel:
@@ -648,6 +647,7 @@ static void mtk_dpi_bridge_enable(struct drm_bridge *bridge)
 
 	mtk_dpi_power_on(dpi);
 	mtk_dpi_set_display_mode(dpi, &dpi->mode);
+	mtk_dpi_enable(dpi);
 }
 
 static enum drm_mode_status
-- 
GitLab


From 4393c74a88cdbf36d8ccc315af09eae1bbe47ae2 Mon Sep 17 00:00:00 2001
From: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Date: Fri, 1 Jul 2022 11:58:34 +0800
Subject: [PATCH 1526/1731] drm/mediatek: dpi: Add support for quantization
 range

For RGB colorimetry, CTA-861 support both limited and full range data
when receiving video with RGB color space.
We use drm_default_rgb_quant_range() to determine the correct setting.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220701035845.16458-6-rex-bc.chen@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 34 ++++++++++++++++++------------
 1 file changed, 21 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 06af0af31e9bc..d0e0152456d10 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -238,16 +238,30 @@ static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height)
 	mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK);
 }
 
-static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi,
-					 struct mtk_dpi_yc_limit *limit)
+static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi)
 {
-	mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT,
+	struct mtk_dpi_yc_limit limit;
+
+	if (drm_default_rgb_quant_range(&dpi->mode) ==
+	    HDMI_QUANTIZATION_RANGE_LIMITED) {
+		limit.y_bottom = 0x10;
+		limit.y_top = 0xfe0;
+		limit.c_bottom = 0x10;
+		limit.c_top = 0xfe0;
+	} else {
+		limit.y_bottom = 0;
+		limit.y_top = 0xfff;
+		limit.c_bottom = 0;
+		limit.c_top = 0xfff;
+	}
+
+	mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_bottom << Y_LIMINT_BOT,
 		     Y_LIMINT_BOT_MASK);
-	mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP,
+	mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_top << Y_LIMINT_TOP,
 		     Y_LIMINT_TOP_MASK);
-	mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_bottom << C_LIMIT_BOT,
+	mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_bottom << C_LIMIT_BOT,
 		     C_LIMIT_BOT_MASK);
-	mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_top << C_LIMIT_TOP,
+	mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_top << C_LIMIT_TOP,
 		     C_LIMIT_TOP_MASK);
 }
 
@@ -438,7 +452,6 @@ err_refcount:
 static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 				    struct drm_display_mode *mode)
 {
-	struct mtk_dpi_yc_limit limit;
 	struct mtk_dpi_polarities dpi_pol;
 	struct mtk_dpi_sync_param hsync;
 	struct mtk_dpi_sync_param vsync_lodd = { 0 };
@@ -473,11 +486,6 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	dev_dbg(dpi->dev, "Got  PLL %lu Hz, pixel clock %lu Hz\n",
 		pll_rate, vm.pixelclock);
 
-	limit.c_bottom = 0x0010;
-	limit.c_top = 0x0FE0;
-	limit.y_bottom = 0x0010;
-	limit.y_top = 0x0FE0;
-
 	dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING;
 	dpi_pol.de_pol = MTK_DPI_POLARITY_RISING;
 	dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ?
@@ -525,7 +533,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	else
 		mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive);
 
-	mtk_dpi_config_channel_limit(dpi, &limit);
+	mtk_dpi_config_channel_limit(dpi);
 	mtk_dpi_config_bit_num(dpi, dpi->bit_num);
 	mtk_dpi_config_channel_swap(dpi, dpi->channel_swap);
 	mtk_dpi_config_yc_map(dpi, dpi->yc_map);
-- 
GitLab


From cf060519e48e7ca9844325d73bc3225182ac6223 Mon Sep 17 00:00:00 2001
From: Guillaume Ranquet <granquet@baylibre.com>
Date: Fri, 1 Jul 2022 11:58:35 +0800
Subject: [PATCH 1527/1731] drm/mediatek: dpi: Implement a CK/DE pol toggle in
 SoC config

Dp_intf does not support CK/DE polarity because the polarity information
is not used for eDP and DP while dp_intf is only for eDP and DP.
Therefore, we add a bit of flexibility to support SoCs without CK/DE pol
support.

Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220701035845.16458-7-rex-bc.chen@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 23 ++++++++++++++++++-----
 1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index d0e0152456d10..9b17507fe5d43 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -120,6 +120,7 @@ struct mtk_dpi_yc_limit {
  * @edge_sel_en: Enable of edge selection.
  * @output_fmts: Array of supported output formats.
  * @num_output_fmts: Quantity of supported output formats.
+ * @is_ck_de_pol: Support CK/DE polarity.
  */
 struct mtk_dpi_conf {
 	unsigned int (*cal_factor)(int clock);
@@ -128,6 +129,7 @@ struct mtk_dpi_conf {
 	bool edge_sel_en;
 	const u32 *output_fmts;
 	u32 num_output_fmts;
+	bool is_ck_de_pol;
 };
 
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -213,13 +215,20 @@ static void mtk_dpi_config_pol(struct mtk_dpi *dpi,
 			       struct mtk_dpi_polarities *dpi_pol)
 {
 	unsigned int pol;
+	unsigned int mask;
 
-	pol = (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ? 0 : CK_POL) |
-	      (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ? 0 : DE_POL) |
-	      (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) |
+	mask = HSYNC_POL | VSYNC_POL;
+	pol = (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) |
 	      (dpi_pol->vsync_pol == MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL);
-	mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol,
-		     CK_POL | DE_POL | HSYNC_POL | VSYNC_POL);
+	if (dpi->conf->is_ck_de_pol) {
+		mask |= CK_POL | DE_POL;
+		pol |= (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ?
+			0 : CK_POL) |
+		       (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ?
+			0 : DE_POL);
+	}
+
+	mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, mask);
 }
 
 static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d)
@@ -794,6 +803,7 @@ static const struct mtk_dpi_conf mt8173_conf = {
 	.max_clock_khz = 300000,
 	.output_fmts = mt8173_output_fmts,
 	.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
+	.is_ck_de_pol = true,
 };
 
 static const struct mtk_dpi_conf mt2701_conf = {
@@ -803,6 +813,7 @@ static const struct mtk_dpi_conf mt2701_conf = {
 	.max_clock_khz = 150000,
 	.output_fmts = mt8173_output_fmts,
 	.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
+	.is_ck_de_pol = true,
 };
 
 static const struct mtk_dpi_conf mt8183_conf = {
@@ -811,6 +822,7 @@ static const struct mtk_dpi_conf mt8183_conf = {
 	.max_clock_khz = 100000,
 	.output_fmts = mt8183_output_fmts,
 	.num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
+	.is_ck_de_pol = true,
 };
 
 static const struct mtk_dpi_conf mt8192_conf = {
@@ -819,6 +831,7 @@ static const struct mtk_dpi_conf mt8192_conf = {
 	.max_clock_khz = 150000,
 	.output_fmts = mt8183_output_fmts,
 	.num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
+	.is_ck_de_pol = true,
 };
 
 static int mtk_dpi_probe(struct platform_device *pdev)
-- 
GitLab


From 3145095fae25de45b029746730f5249823ba059c Mon Sep 17 00:00:00 2001
From: Guillaume Ranquet <granquet@baylibre.com>
Date: Fri, 1 Jul 2022 11:58:36 +0800
Subject: [PATCH 1528/1731] drm/mediatek: dpi: Implement a swap_input toggle in
 SoC config

The hardware design of dp_intf does not support input swap, so we add
a bit of flexibility to support SoCs without swap_input support.
We also add a warning message if the hardware is not supported and it
needs to swap input.

Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220701035845.16458-8-rex-bc.chen@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 9b17507fe5d43..0f7f566860792 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -121,6 +121,7 @@ struct mtk_dpi_yc_limit {
  * @output_fmts: Array of supported output formats.
  * @num_output_fmts: Quantity of supported output formats.
  * @is_ck_de_pol: Support CK/DE polarity.
+ * @swap_input_support: Support input swap function.
  */
 struct mtk_dpi_conf {
 	unsigned int (*cal_factor)(int clock);
@@ -130,6 +131,7 @@ struct mtk_dpi_conf {
 	const u32 *output_fmts;
 	u32 num_output_fmts;
 	bool is_ck_de_pol;
+	bool swap_input_support;
 };
 
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -393,7 +395,8 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
 	/* only support RGB888 */
 	mtk_dpi_config_yuv422_enable(dpi, false);
 	mtk_dpi_config_csc_enable(dpi, false);
-	mtk_dpi_config_swap_input(dpi, false);
+	if (dpi->conf->swap_input_support)
+		mtk_dpi_config_swap_input(dpi, false);
 	mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB);
 }
 
@@ -804,6 +807,7 @@ static const struct mtk_dpi_conf mt8173_conf = {
 	.output_fmts = mt8173_output_fmts,
 	.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
 	.is_ck_de_pol = true,
+	.swap_input_support = true,
 };
 
 static const struct mtk_dpi_conf mt2701_conf = {
@@ -814,6 +818,7 @@ static const struct mtk_dpi_conf mt2701_conf = {
 	.output_fmts = mt8173_output_fmts,
 	.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
 	.is_ck_de_pol = true,
+	.swap_input_support = true,
 };
 
 static const struct mtk_dpi_conf mt8183_conf = {
@@ -823,6 +828,7 @@ static const struct mtk_dpi_conf mt8183_conf = {
 	.output_fmts = mt8183_output_fmts,
 	.num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
 	.is_ck_de_pol = true,
+	.swap_input_support = true,
 };
 
 static const struct mtk_dpi_conf mt8192_conf = {
@@ -832,6 +838,7 @@ static const struct mtk_dpi_conf mt8192_conf = {
 	.output_fmts = mt8183_output_fmts,
 	.num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
 	.is_ck_de_pol = true,
+	.swap_input_support = true,
 };
 
 static int mtk_dpi_probe(struct platform_device *pdev)
-- 
GitLab


From a519e22bcfd4ddfed0524946124b6fe1fd27a954 Mon Sep 17 00:00:00 2001
From: Guillaume Ranquet <granquet@baylibre.com>
Date: Fri, 1 Jul 2022 11:58:37 +0800
Subject: [PATCH 1529/1731] drm/mediatek: dpi: Move dimension mask to SoC
 config

Add flexibility by moving the dimension mask to the SoC config

Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220701035845.16458-9-rex-bc.chen@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 27 +++++++++++++++++----------
 1 file changed, 17 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 0f7f566860792..cbb211cc017bf 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -122,6 +122,8 @@ struct mtk_dpi_yc_limit {
  * @num_output_fmts: Quantity of supported output formats.
  * @is_ck_de_pol: Support CK/DE polarity.
  * @swap_input_support: Support input swap function.
+ * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH
+ *		    (no shift).
  */
 struct mtk_dpi_conf {
 	unsigned int (*cal_factor)(int clock);
@@ -132,6 +134,7 @@ struct mtk_dpi_conf {
 	u32 num_output_fmts;
 	bool is_ck_de_pol;
 	bool swap_input_support;
+	u32 dimension_mask;
 };
 
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -160,30 +163,30 @@ static void mtk_dpi_disable(struct mtk_dpi *dpi)
 static void mtk_dpi_config_hsync(struct mtk_dpi *dpi,
 				 struct mtk_dpi_sync_param *sync)
 {
-	mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH,
-		     sync->sync_width << HPW, HPW_MASK);
-	mtk_dpi_mask(dpi, DPI_TGEN_HPORCH,
-		     sync->back_porch << HBP, HBP_MASK);
+	mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, sync->sync_width << HPW,
+		     dpi->conf->dimension_mask << HPW);
+	mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->back_porch << HBP,
+		     dpi->conf->dimension_mask << HBP);
 	mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP,
-		     HFP_MASK);
+		     dpi->conf->dimension_mask << HFP);
 }
 
 static void mtk_dpi_config_vsync(struct mtk_dpi *dpi,
 				 struct mtk_dpi_sync_param *sync,
 				 u32 width_addr, u32 porch_addr)
 {
-	mtk_dpi_mask(dpi, width_addr,
-		     sync->sync_width << VSYNC_WIDTH_SHIFT,
-		     VSYNC_WIDTH_MASK);
 	mtk_dpi_mask(dpi, width_addr,
 		     sync->shift_half_line << VSYNC_HALF_LINE_SHIFT,
 		     VSYNC_HALF_LINE_MASK);
+	mtk_dpi_mask(dpi, width_addr,
+		     sync->sync_width << VSYNC_WIDTH_SHIFT,
+		     dpi->conf->dimension_mask << VSYNC_WIDTH_SHIFT);
 	mtk_dpi_mask(dpi, porch_addr,
 		     sync->back_porch << VSYNC_BACK_PORCH_SHIFT,
-		     VSYNC_BACK_PORCH_MASK);
+		     dpi->conf->dimension_mask << VSYNC_BACK_PORCH_SHIFT);
 	mtk_dpi_mask(dpi, porch_addr,
 		     sync->front_porch << VSYNC_FRONT_PORCH_SHIFT,
-		     VSYNC_FRONT_PORCH_MASK);
+		     dpi->conf->dimension_mask << VSYNC_FRONT_PORCH_SHIFT);
 }
 
 static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi,
@@ -808,6 +811,7 @@ static const struct mtk_dpi_conf mt8173_conf = {
 	.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
 	.is_ck_de_pol = true,
 	.swap_input_support = true,
+	.dimension_mask = HPW_MASK,
 };
 
 static const struct mtk_dpi_conf mt2701_conf = {
@@ -819,6 +823,7 @@ static const struct mtk_dpi_conf mt2701_conf = {
 	.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
 	.is_ck_de_pol = true,
 	.swap_input_support = true,
+	.dimension_mask = HPW_MASK,
 };
 
 static const struct mtk_dpi_conf mt8183_conf = {
@@ -829,6 +834,7 @@ static const struct mtk_dpi_conf mt8183_conf = {
 	.num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
 	.is_ck_de_pol = true,
 	.swap_input_support = true,
+	.dimension_mask = HPW_MASK,
 };
 
 static const struct mtk_dpi_conf mt8192_conf = {
@@ -839,6 +845,7 @@ static const struct mtk_dpi_conf mt8192_conf = {
 	.num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
 	.is_ck_de_pol = true,
 	.swap_input_support = true,
+	.dimension_mask = HPW_MASK,
 };
 
 static int mtk_dpi_probe(struct platform_device *pdev)
-- 
GitLab


From e373924d7eb1db0d0f46de9db270b0ee88f857c7 Mon Sep 17 00:00:00 2001
From: Guillaume Ranquet <granquet@baylibre.com>
Date: Fri, 1 Jul 2022 11:58:38 +0800
Subject: [PATCH 1530/1731] drm/mediatek: dpi: Move hvsize_mask to SoC config

Add flexibility by moving the hvsize mask to SoC specific config.

Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220701035845.16458-10-rex-bc.chen@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index cbb211cc017bf..9d1f8a00e5aee 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -124,6 +124,7 @@ struct mtk_dpi_yc_limit {
  * @swap_input_support: Support input swap function.
  * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH
  *		    (no shift).
+ * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift).
  */
 struct mtk_dpi_conf {
 	unsigned int (*cal_factor)(int clock);
@@ -135,6 +136,7 @@ struct mtk_dpi_conf {
 	bool is_ck_de_pol;
 	bool swap_input_support;
 	u32 dimension_mask;
+	u32 hvsize_mask;
 };
 
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -248,8 +250,10 @@ static void mtk_dpi_config_interface(struct mtk_dpi *dpi, bool inter)
 
 static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height)
 {
-	mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, HSIZE_MASK);
-	mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK);
+	mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE,
+		     dpi->conf->hvsize_mask << HSIZE);
+	mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE,
+		     dpi->conf->hvsize_mask << VSIZE);
 }
 
 static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi)
@@ -812,6 +816,7 @@ static const struct mtk_dpi_conf mt8173_conf = {
 	.is_ck_de_pol = true,
 	.swap_input_support = true,
 	.dimension_mask = HPW_MASK,
+	.hvsize_mask = HSIZE_MASK,
 };
 
 static const struct mtk_dpi_conf mt2701_conf = {
@@ -824,6 +829,7 @@ static const struct mtk_dpi_conf mt2701_conf = {
 	.is_ck_de_pol = true,
 	.swap_input_support = true,
 	.dimension_mask = HPW_MASK,
+	.hvsize_mask = HSIZE_MASK,
 };
 
 static const struct mtk_dpi_conf mt8183_conf = {
@@ -835,6 +841,7 @@ static const struct mtk_dpi_conf mt8183_conf = {
 	.is_ck_de_pol = true,
 	.swap_input_support = true,
 	.dimension_mask = HPW_MASK,
+	.hvsize_mask = HSIZE_MASK,
 };
 
 static const struct mtk_dpi_conf mt8192_conf = {
@@ -846,6 +853,7 @@ static const struct mtk_dpi_conf mt8192_conf = {
 	.is_ck_de_pol = true,
 	.swap_input_support = true,
 	.dimension_mask = HPW_MASK,
+	.hvsize_mask = HSIZE_MASK,
 };
 
 static int mtk_dpi_probe(struct platform_device *pdev)
-- 
GitLab


From 48fb81a2717d732448c08d34484ae18cd9f73769 Mon Sep 17 00:00:00 2001
From: Guillaume Ranquet <granquet@baylibre.com>
Date: Fri, 1 Jul 2022 11:58:39 +0800
Subject: [PATCH 1531/1731] drm/mediatek: dpi: Move swap_shift to SoC config

Add flexibility by moving the swap shift value to SoC specific config.

Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220701035845.16458-11-rex-bc.chen@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 9d1f8a00e5aee..669e324d44d06 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -125,6 +125,7 @@ struct mtk_dpi_yc_limit {
  * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH
  *		    (no shift).
  * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift).
+ * @channel_swap_shift: Shift value of channel swap.
  */
 struct mtk_dpi_conf {
 	unsigned int (*cal_factor)(int clock);
@@ -137,6 +138,7 @@ struct mtk_dpi_conf {
 	bool swap_input_support;
 	u32 dimension_mask;
 	u32 hvsize_mask;
+	u32 channel_swap_shift;
 };
 
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -367,7 +369,9 @@ static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi,
 		break;
 	}
 
-	mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, CH_SWAP_MASK);
+	mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING,
+		     val << dpi->conf->channel_swap_shift,
+		     CH_SWAP_MASK << dpi->conf->channel_swap_shift);
 }
 
 static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable)
@@ -817,6 +821,7 @@ static const struct mtk_dpi_conf mt8173_conf = {
 	.swap_input_support = true,
 	.dimension_mask = HPW_MASK,
 	.hvsize_mask = HSIZE_MASK,
+	.channel_swap_shift = CH_SWAP,
 };
 
 static const struct mtk_dpi_conf mt2701_conf = {
@@ -830,6 +835,7 @@ static const struct mtk_dpi_conf mt2701_conf = {
 	.swap_input_support = true,
 	.dimension_mask = HPW_MASK,
 	.hvsize_mask = HSIZE_MASK,
+	.channel_swap_shift = CH_SWAP,
 };
 
 static const struct mtk_dpi_conf mt8183_conf = {
@@ -842,6 +848,7 @@ static const struct mtk_dpi_conf mt8183_conf = {
 	.swap_input_support = true,
 	.dimension_mask = HPW_MASK,
 	.hvsize_mask = HSIZE_MASK,
+	.channel_swap_shift = CH_SWAP,
 };
 
 static const struct mtk_dpi_conf mt8192_conf = {
@@ -854,6 +861,7 @@ static const struct mtk_dpi_conf mt8192_conf = {
 	.swap_input_support = true,
 	.dimension_mask = HPW_MASK,
 	.hvsize_mask = HSIZE_MASK,
+	.channel_swap_shift = CH_SWAP,
 };
 
 static int mtk_dpi_probe(struct platform_device *pdev)
-- 
GitLab


From 4e28119bd52beda1643f885a01db2ac404878755 Mon Sep 17 00:00:00 2001
From: Guillaume Ranquet <granquet@baylibre.com>
Date: Fri, 1 Jul 2022 11:58:40 +0800
Subject: [PATCH 1532/1731] drm/mediatek: dpi: Move the yuv422_en_bit to SoC
 config

Add flexibility by moving the yuv422 en bit to SoC specific config

Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220701035845.16458-12-rex-bc.chen@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 669e324d44d06..940da6594030f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -126,6 +126,7 @@ struct mtk_dpi_yc_limit {
  *		    (no shift).
  * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift).
  * @channel_swap_shift: Shift value of channel swap.
+ * @yuv422_en_bit: Enable bit of yuv422.
  */
 struct mtk_dpi_conf {
 	unsigned int (*cal_factor)(int clock);
@@ -139,6 +140,7 @@ struct mtk_dpi_conf {
 	u32 dimension_mask;
 	u32 hvsize_mask;
 	u32 channel_swap_shift;
+	u32 yuv422_en_bit;
 };
 
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -376,7 +378,8 @@ static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi,
 
 static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable)
 {
-	mtk_dpi_mask(dpi, DPI_CON, enable ? YUV422_EN : 0, YUV422_EN);
+	mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->yuv422_en_bit : 0,
+		     dpi->conf->yuv422_en_bit);
 }
 
 static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable)
@@ -822,6 +825,7 @@ static const struct mtk_dpi_conf mt8173_conf = {
 	.dimension_mask = HPW_MASK,
 	.hvsize_mask = HSIZE_MASK,
 	.channel_swap_shift = CH_SWAP,
+	.yuv422_en_bit = YUV422_EN,
 };
 
 static const struct mtk_dpi_conf mt2701_conf = {
@@ -836,6 +840,7 @@ static const struct mtk_dpi_conf mt2701_conf = {
 	.dimension_mask = HPW_MASK,
 	.hvsize_mask = HSIZE_MASK,
 	.channel_swap_shift = CH_SWAP,
+	.yuv422_en_bit = YUV422_EN,
 };
 
 static const struct mtk_dpi_conf mt8183_conf = {
@@ -849,6 +854,7 @@ static const struct mtk_dpi_conf mt8183_conf = {
 	.dimension_mask = HPW_MASK,
 	.hvsize_mask = HSIZE_MASK,
 	.channel_swap_shift = CH_SWAP,
+	.yuv422_en_bit = YUV422_EN,
 };
 
 static const struct mtk_dpi_conf mt8192_conf = {
@@ -862,6 +868,7 @@ static const struct mtk_dpi_conf mt8192_conf = {
 	.dimension_mask = HPW_MASK,
 	.hvsize_mask = HSIZE_MASK,
 	.channel_swap_shift = CH_SWAP,
+	.yuv422_en_bit = YUV422_EN,
 };
 
 static int mtk_dpi_probe(struct platform_device *pdev)
-- 
GitLab


From 091e5e004e697a758358195bb774d3d3cd12414f Mon Sep 17 00:00:00 2001
From: Guillaume Ranquet <granquet@baylibre.com>
Date: Fri, 1 Jul 2022 11:58:41 +0800
Subject: [PATCH 1533/1731] drm/mediatek: dpi: Move the csc_enable bit to SoC
 config

Add flexibility by moving the csc_enable bit to SoC specific config

Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220701035845.16458-13-rex-bc.chen@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 940da6594030f..ea8d866e67bc5 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -127,6 +127,7 @@ struct mtk_dpi_yc_limit {
  * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift).
  * @channel_swap_shift: Shift value of channel swap.
  * @yuv422_en_bit: Enable bit of yuv422.
+ * @csc_enable_bit: Enable bit of CSC.
  */
 struct mtk_dpi_conf {
 	unsigned int (*cal_factor)(int clock);
@@ -141,6 +142,7 @@ struct mtk_dpi_conf {
 	u32 hvsize_mask;
 	u32 channel_swap_shift;
 	u32 yuv422_en_bit;
+	u32 csc_enable_bit;
 };
 
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -384,7 +386,8 @@ static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable)
 
 static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable)
 {
-	mtk_dpi_mask(dpi, DPI_CON, enable ? CSC_ENABLE : 0, CSC_ENABLE);
+	mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->csc_enable_bit : 0,
+		     dpi->conf->csc_enable_bit);
 }
 
 static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
@@ -826,6 +829,7 @@ static const struct mtk_dpi_conf mt8173_conf = {
 	.hvsize_mask = HSIZE_MASK,
 	.channel_swap_shift = CH_SWAP,
 	.yuv422_en_bit = YUV422_EN,
+	.csc_enable_bit = CSC_ENABLE,
 };
 
 static const struct mtk_dpi_conf mt2701_conf = {
@@ -841,6 +845,7 @@ static const struct mtk_dpi_conf mt2701_conf = {
 	.hvsize_mask = HSIZE_MASK,
 	.channel_swap_shift = CH_SWAP,
 	.yuv422_en_bit = YUV422_EN,
+	.csc_enable_bit = CSC_ENABLE,
 };
 
 static const struct mtk_dpi_conf mt8183_conf = {
@@ -855,6 +860,7 @@ static const struct mtk_dpi_conf mt8183_conf = {
 	.hvsize_mask = HSIZE_MASK,
 	.channel_swap_shift = CH_SWAP,
 	.yuv422_en_bit = YUV422_EN,
+	.csc_enable_bit = CSC_ENABLE,
 };
 
 static const struct mtk_dpi_conf mt8192_conf = {
@@ -869,6 +875,7 @@ static const struct mtk_dpi_conf mt8192_conf = {
 	.hvsize_mask = HSIZE_MASK,
 	.channel_swap_shift = CH_SWAP,
 	.yuv422_en_bit = YUV422_EN,
+	.csc_enable_bit = CSC_ENABLE,
 };
 
 static int mtk_dpi_probe(struct platform_device *pdev)
-- 
GitLab


From 51e4d60e6ba50cc53150885549318c3470d44e3c Mon Sep 17 00:00:00 2001
From: Abhinav Kumar <quic_abhinavk@quicinc.com>
Date: Tue, 10 May 2022 16:54:39 -0700
Subject: [PATCH 1534/1731] drm/msm/dpu: add writeback support for sc7180

Add writeback support for sc7180 devices. This has been
validated on sc7180 chromebook using IGT writeback test
suite.

localhost /usr/local/libexec/igt-gpu-tools # ./kms_writeback
Starting subtest: writeback-pixel-formats
Subtest writeback-pixel-formats: SUCCESS (0.001s)
Starting subtest: writeback-invalid-parameters
Subtest writeback-invalid-parameters: SUCCESS (0.004s)
Starting subtest: writeback-fb-id
Subtest writeback-fb-id: SUCCESS (0.009s)
Starting subtest: writeback-check-output
Subtest writeback-check-output: SUCCESS (0.203s)

Adding this will increase IGT coverage on chromebooks and also
allow using writeback functionality for other use-cases as
necessary.

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/485787/
Link: https://lore.kernel.org/r/20220510235439.31916-1-quic_abhinavk@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 400ebceb56bb6..210becd2a9b70 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1803,6 +1803,8 @@ static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.pingpong = sc7180_pp,
 		.intf_count = ARRAY_SIZE(sc7180_intf),
 		.intf = sc7180_intf,
+		.wb_count = ARRAY_SIZE(sm8250_wb),
+		.wb = sm8250_wb,
 		.vbif_count = ARRAY_SIZE(sdm845_vbif),
 		.vbif = sdm845_vbif,
 		.reg_dma_count = 1,
-- 
GitLab


From 2d8a4edb672dbd997ee1d82eb13b08def29b4329 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 2 Jun 2022 23:24:41 +0300
Subject: [PATCH 1535/1731] drm/msm/dpu: use feature bit for LM combined alpha
 check

Rather than checking hwversion, follow the usual patter and add special
bit to the lm->features to check whether the LM has combined or separate
alpha registers. While we are at it, rename
dpu_hw_lm_setup_blend_config_sdm845() to
dpu_hw_lm_setup_blend_config_combined_alpha().

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/488155/
Link: https://lore.kernel.org/r/20220602202447.1755115-2-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c    | 19 +++++++++++--------
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |  2 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c     |  6 +++---
 3 files changed, 16 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 210becd2a9b70..9309e2b8a41c9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -50,11 +50,14 @@
 #define DMA_CURSOR_MSM8998_MASK \
 	(DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR))
 
-#define MIXER_SDM845_MASK \
+#define MIXER_MSM8998_MASK \
 	(BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
 
+#define MIXER_SDM845_MASK \
+	(BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
+
 #define MIXER_SC7180_MASK \
-	(BIT(DPU_DIM_LAYER))
+	(BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
 
 #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER)
 
@@ -936,17 +939,17 @@ static const struct dpu_lm_sub_blks msm8998_lm_sblk = {
 };
 
 static const struct dpu_lm_cfg msm8998_lm[] = {
-	LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
+	LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK,
 		&msm8998_lm_sblk, PINGPONG_0, LM_2, DSPP_0),
-	LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
+	LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK,
 		&msm8998_lm_sblk, PINGPONG_1, LM_5, DSPP_1),
-	LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
+	LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK,
 		&msm8998_lm_sblk, PINGPONG_2, LM_0, 0),
-	LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
+	LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK,
 		&msm8998_lm_sblk, PINGPONG_MAX, 0, 0),
-	LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
+	LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK,
 		&msm8998_lm_sblk, PINGPONG_MAX, 0, 0),
-	LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
+	LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK,
 		&msm8998_lm_sblk, PINGPONG_3, LM_1, 0),
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 8cb6d1f25bf90..80bc09b1f1b36 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -145,6 +145,7 @@ enum {
  * @DPU_MIXER_SOURCESPLIT     Layer mixer supports source-split configuration
  * @DPU_MIXER_GC              Gamma correction block
  * @DPU_DIM_LAYER             Layer mixer supports dim layer
+ * @DPU_MIXER_COMBINED_ALPHA  Layer mixer has combined alpha register
  * @DPU_MIXER_MAX             maximum value
  */
 enum {
@@ -152,6 +153,7 @@ enum {
 	DPU_MIXER_SOURCESPLIT,
 	DPU_MIXER_GC,
 	DPU_DIM_LAYER,
+	DPU_MIXER_COMBINED_ALPHA,
 	DPU_MIXER_MAX
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index 462f5082099e6..25d2eba28e717 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -148,7 +148,7 @@ static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value)
 	return 0;
 }
 
-static void dpu_hw_lm_setup_blend_config_sdm845(struct dpu_hw_mixer *ctx,
+static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer *ctx,
 	u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)
 {
 	struct dpu_hw_blk_reg_map *c = &ctx->hw;
@@ -204,8 +204,8 @@ static void _setup_mixer_ops(const struct dpu_mdss_cfg *m,
 		unsigned long features)
 {
 	ops->setup_mixer_out = dpu_hw_lm_setup_out;
-	if (m->hwversion >= DPU_HW_VER_400)
-		ops->setup_blend_config = dpu_hw_lm_setup_blend_config_sdm845;
+	if (test_bit(DPU_MIXER_COMBINED_ALPHA, &features))
+		ops->setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha;
 	else
 		ops->setup_blend_config = dpu_hw_lm_setup_blend_config;
 	ops->setup_alpha_out = dpu_hw_lm_setup_color3;
-- 
GitLab


From c87443150a982727dbd1f57bc91649864b471ab2 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 2 Jun 2022 23:24:42 +0300
Subject: [PATCH 1536/1731] drm/msm/dpu: move VBIF_XINL_QOS_LVL_REMAP size to
 hw_catalog

Rather than detecting VBIF_XINL_QOS_LVL_REMAP_000 based on the
hwversion, push the offset to the hw_catalog.

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/488156/
Link: https://lore.kernel.org/r/20220602202447.1755115-3-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c    | 4 ++--
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 9309e2b8a41c9..6647cdedbd75c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1339,6 +1339,7 @@ static const struct dpu_vbif_cfg msm8998_vbif[] = {
 	.default_ot_wr_limit = 32,
 	.features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM),
 	.xin_halt_timeout = 0x4000,
+	.qos_rp_remap_size = 0x20,
 	.dynamic_ot_rd_tbl = {
 		.count = ARRAY_SIZE(msm8998_ot_rdwr_cfg),
 		.cfg = msm8998_ot_rdwr_cfg,
@@ -1366,6 +1367,7 @@ static const struct dpu_vbif_cfg sdm845_vbif[] = {
 	.base = 0, .len = 0x1040,
 	.features = BIT(DPU_VBIF_QOS_REMAP),
 	.xin_halt_timeout = 0x4000,
+	.qos_rp_remap_size = 0x40,
 	.qos_rt_tbl = {
 		.npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
 		.priority_lvl = sdm845_rt_pri_lvl,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 80bc09b1f1b36..f70de97f492aa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -709,6 +709,7 @@ struct dpu_vbif_qos_tbl {
  * @ot_rd_limit        default OT read limit
  * @ot_wr_limit        default OT write limit
  * @xin_halt_timeout   maximum time (in usec) for xin to halt
+ * @qos_rp_remap_size  size of VBIF_XINL_QOS_RP_REMAP register space
  * @dynamic_ot_rd_tbl  dynamic OT read configuration table
  * @dynamic_ot_wr_tbl  dynamic OT write configuration table
  * @qos_rt_tbl         real-time QoS priority table
@@ -721,6 +722,7 @@ struct dpu_vbif_cfg {
 	u32 default_ot_rd_limit;
 	u32 default_ot_wr_limit;
 	u32 xin_halt_timeout;
+	u32 qos_rp_remap_size;
 	struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl;
 	struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl;
 	struct dpu_vbif_qos_tbl qos_rt_tbl;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
index b757054e1c23f..046854c3fbed0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
@@ -30,7 +30,7 @@
 #define VBIF_XIN_HALT_CTRL0		0x0200
 #define VBIF_XIN_HALT_CTRL1		0x0204
 #define VBIF_XINL_QOS_RP_REMAP_000	0x0550
-#define VBIF_XINL_QOS_LVL_REMAP_000(v)	(v < DPU_HW_VER_400 ? 0x570 : 0x0590)
+#define VBIF_XINL_QOS_LVL_REMAP_000(vbif)	(VBIF_XINL_QOS_RP_REMAP_000 + (vbif)->cap->qos_rp_remap_size)
 
 static void dpu_hw_clear_errors(struct dpu_hw_vbif *vbif,
 		u32 *pnd_errors, u32 *src_errors)
@@ -163,7 +163,7 @@ static void dpu_hw_set_qos_remap(struct dpu_hw_vbif *vbif,
 
 	c = &vbif->hw;
 
-	reg_lvl = VBIF_XINL_QOS_LVL_REMAP_000(c->hwversion);
+	reg_lvl = VBIF_XINL_QOS_LVL_REMAP_000(vbif);
 	reg_high = ((xin_id & 0x8) >> 3) * 4 + (level * 8);
 	reg_shift = (xin_id & 0x7) * 4;
 
-- 
GitLab


From 129ae533fabfbbbfe59aabf6a26cce2cfeccbf23 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 2 Jun 2022 23:24:43 +0300
Subject: [PATCH 1537/1731] drm/msm/dpu: remove hwversion field from data
 structures

The driver should not depend on hw revision for detecting features.
Instead it should use features from the hw catalog. Drop the hwversion
field from struct dpu_mdss_cfg and struct dpu_hw_blk_reg_map.

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/488160/
Link: https://lore.kernel.org/r/20220602202447.1755115-4-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c    | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    | 2 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c        | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c        | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c       | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c       | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c         | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c    | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c   | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c       | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c        | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h       | 2 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c       | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c         | 1 -
 15 files changed, 17 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 6647cdedbd75c..61271d9013a11 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -2004,7 +2004,6 @@ struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev)
 	for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) {
 		if (cfg_handler[i].hw_rev == hw_rev) {
 			cfg_handler[i].cfg_init(dpu_cfg);
-			dpu_cfg->hwversion = hw_rev;
 			return dpu_cfg;
 		}
 	}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index f70de97f492aa..4225f58d8f977 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -826,8 +826,6 @@ struct dpu_perf_cfg {
  * @mdss_irqs:         Bitmap with the irqs supported by the target
  */
 struct dpu_mdss_cfg {
-	u32 hwversion;
-
 	const struct dpu_caps *caps;
 
 	u32 mdp_count;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index c33e7ef611a6c..7d416bf4ae916 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -61,7 +61,6 @@ static const struct dpu_ctl_cfg *_ctl_offset(enum dpu_ctl ctl,
 			b->base_off = addr;
 			b->blk_off = m->ctl[i].base;
 			b->length = m->ctl[i].len;
-			b->hwversion = m->hwversion;
 			b->log_mask = DPU_DBG_MASK_CTL;
 			return &m->ctl[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
index 4ad8991fc7d9d..6f20d6b6dddd0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
@@ -169,7 +169,6 @@ static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc,
 			b->base_off = addr;
 			b->blk_off = m->dsc[i].base;
 			b->length = m->dsc[i].len;
-			b->hwversion = m->hwversion;
 			b->log_mask = DPU_DBG_MASK_DSC;
 			return &m->dsc[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
index 355894a3b48c3..3e63bf4fa64e5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
@@ -83,7 +83,6 @@ static const struct dpu_dspp_cfg *_dspp_offset(enum dpu_dspp dspp,
 			b->base_off = addr;
 			b->blk_off = m->dspp[i].base;
 			b->length = m->dspp[i].len;
-			b->hwversion = m->hwversion;
 			b->log_mask = DPU_DBG_MASK_DSPP;
 			return &m->dspp[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index 61284e6c313da..01bb2d84c3a05 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -403,7 +403,6 @@ static void __intr_offset(struct dpu_mdss_cfg *m,
 {
 	hw->base_off = addr;
 	hw->blk_off = m->mdp[0].base;
-	hw->hwversion = m->hwversion;
 }
 
 struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 3f4d2c6e1b452..b2ca8d19fdd79 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -80,7 +80,6 @@ static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf,
 			b->base_off = addr;
 			b->blk_off = m->intf[i].base;
 			b->length = m->intf[i].len;
-			b->hwversion = m->hwversion;
 			b->log_mask = DPU_DBG_MASK_INTF;
 			return &m->intf[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index 25d2eba28e717..b41993269d091 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -46,7 +46,6 @@ static const struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer,
 			b->base_off = addr;
 			b->blk_off = m->mixer[i].base;
 			b->length = m->mixer[i].len;
-			b->hwversion = m->hwversion;
 			b->log_mask = DPU_DBG_MASK_LM;
 			return &m->mixer[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
index c06d595d5df0f..b053d68d38da2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
@@ -26,7 +26,6 @@ static const struct dpu_merge_3d_cfg *_merge_3d_offset(enum dpu_merge_3d idx,
 			b->base_off = addr;
 			b->blk_off = m->merge_3d[i].base;
 			b->length = m->merge_3d[i].len;
-			b->hwversion = m->hwversion;
 			b->log_mask = DPU_DBG_MASK_PINGPONG;
 			return &m->merge_3d[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
index 47c6ab6caf953..6538e195cfe94 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
@@ -54,7 +54,6 @@ static const struct dpu_pingpong_cfg *_pingpong_offset(enum dpu_pingpong pp,
 			b->base_off = addr;
 			b->blk_off = m->pingpong[i].base;
 			b->length = m->pingpong[i].len;
-			b->hwversion = m->hwversion;
 			b->log_mask = DPU_DBG_MASK_PINGPONG;
 			return &m->pingpong[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 0a0864dff7837..ab7f1a4cc578f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -772,7 +772,6 @@ static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp,
 				b->base_off = addr;
 				b->blk_off = catalog->sspp[i].base;
 				b->length = catalog->sspp[i].len;
-				b->hwversion = catalog->hwversion;
 				b->log_mask = DPU_DBG_MASK_SSPP;
 				return &catalog->sspp[i];
 			}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
index ab3ef162b6668..12d3b00672754 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
@@ -288,7 +288,6 @@ static const struct dpu_mdp_cfg *_top_offset(enum dpu_mdp mdp,
 			b->base_off = addr;
 			b->blk_off = m->mdp[i].base;
 			b->length = m->mdp[i].len;
-			b->hwversion = m->hwversion;
 			b->log_mask = DPU_DBG_MASK_TOP;
 			return &m->mdp[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index e4a65eb4f7690..550b2e2b3e348 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -21,14 +21,12 @@
  * @blk_off:      pipe offset relative to mdss offset
  * @length        length of register block offset
  * @xin_id        xin id
- * @hwversion     mdss hw version number
  */
 struct dpu_hw_blk_reg_map {
 	void __iomem *base_off;
 	u32 blk_off;
 	u32 length;
 	u32 xin_id;
-	u32 hwversion;
 	u32 log_mask;
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
index 046854c3fbed0..789ecc531b43a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
@@ -223,7 +223,6 @@ static const struct dpu_vbif_cfg *_top_offset(enum dpu_vbif vbif,
 			b->base_off = addr;
 			b->blk_off = m->vbif[i].base;
 			b->length = m->vbif[i].len;
-			b->hwversion = m->hwversion;
 			b->log_mask = DPU_DBG_MASK_VBIF;
 			return &m->vbif[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
index bcccce292937d..084439fdd3a0d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
@@ -63,7 +63,6 @@ static const struct dpu_wb_cfg *_wb_offset(enum dpu_wb wb,
 			b->base_off = addr;
 			b->blk_off = m->wb[i].base;
 			b->length = m->wb[i].len;
-			b->hwversion = m->hwversion;
 			return &m->wb[i];
 		}
 	}
-- 
GitLab


From 477db4feea03e6b93071d2152efac761b8cab22d Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 2 Jun 2022 23:24:44 +0300
Subject: [PATCH 1538/1731] drm/msm/dpu: change catalog->perf to be a const
 pointer

Change dpu_mdss_cfg::perf to be a const pointer rather than embedding
the dpu_perf_cfg struct into the struct dpu_mdss_cfg.

Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/488158/
Link: https://lore.kernel.org/r/20220602202447.1755115-5-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 20 +++++++++----------
 .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c   | 10 +++++-----
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c    | 16 +++++++--------
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c     | 18 ++++++++---------
 5 files changed, 33 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index a7492dd6ed654..31767d0f73537 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -53,7 +53,7 @@ static u64 _dpu_core_perf_calc_bw(struct dpu_kms *kms,
 		crtc_plane_bw += pstate->plane_fetch_bw;
 	}
 
-	bw_factor = kms->catalog->perf.bw_inefficiency_factor;
+	bw_factor = kms->catalog->perf->bw_inefficiency_factor;
 	if (bw_factor) {
 		crtc_plane_bw *= bw_factor;
 		do_div(crtc_plane_bw, 100);
@@ -90,7 +90,7 @@ static u64 _dpu_core_perf_calc_clk(struct dpu_kms *kms,
 		crtc_clk = max(pstate->plane_clk, crtc_clk);
 	}
 
-	clk_factor = kms->catalog->perf.clk_inefficiency_factor;
+	clk_factor = kms->catalog->perf->clk_inefficiency_factor;
 	if (clk_factor) {
 		crtc_clk *= clk_factor;
 		do_div(crtc_clk, 100);
@@ -128,7 +128,7 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
 		perf->core_clk_rate = kms->perf.fix_core_clk_rate;
 	} else {
 		perf->bw_ctl = _dpu_core_perf_calc_bw(kms, crtc);
-		perf->max_per_pipe_ib = kms->catalog->perf.min_dram_ib;
+		perf->max_per_pipe_ib = kms->catalog->perf->min_dram_ib;
 		perf->core_clk_rate = _dpu_core_perf_calc_clk(kms, crtc, state);
 	}
 
@@ -189,7 +189,7 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
 		bw = DIV_ROUND_UP_ULL(bw_sum_of_intfs, 1000);
 		DRM_DEBUG_ATOMIC("calculated bandwidth=%uk\n", bw);
 
-		threshold = kms->catalog->perf.max_bw_high;
+		threshold = kms->catalog->perf->max_bw_high;
 
 		DRM_DEBUG_ATOMIC("final threshold bw limit = %d\n", threshold);
 
@@ -413,7 +413,7 @@ static ssize_t _dpu_core_perf_mode_write(struct file *file,
 		    const char __user *user_buf, size_t count, loff_t *ppos)
 {
 	struct dpu_core_perf *perf = file->private_data;
-	struct dpu_perf_cfg *cfg = &perf->catalog->perf;
+	const struct dpu_perf_cfg *cfg = perf->catalog->perf;
 	u32 perf_mode = 0;
 	int ret;
 
@@ -480,15 +480,15 @@ int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent)
 	debugfs_create_u32("enable_bw_release", 0600, entry,
 			(u32 *)&perf->enable_bw_release);
 	debugfs_create_u32("threshold_low", 0600, entry,
-			(u32 *)&catalog->perf.max_bw_low);
+			(u32 *)&catalog->perf->max_bw_low);
 	debugfs_create_u32("threshold_high", 0600, entry,
-			(u32 *)&catalog->perf.max_bw_high);
+			(u32 *)&catalog->perf->max_bw_high);
 	debugfs_create_u32("min_core_ib", 0600, entry,
-			(u32 *)&catalog->perf.min_core_ib);
+			(u32 *)&catalog->perf->min_core_ib);
 	debugfs_create_u32("min_llcc_ib", 0600, entry,
-			(u32 *)&catalog->perf.min_llcc_ib);
+			(u32 *)&catalog->perf->min_llcc_ib);
 	debugfs_create_u32("min_dram_ib", 0600, entry,
-			(u32 *)&catalog->perf.min_dram_ib);
+			(u32 *)&catalog->perf->min_dram_ib);
 	debugfs_create_file("perf_mode", 0600, entry,
 			(u32 *)perf, &dpu_core_perf_mode_fops);
 	debugfs_create_u64("fix_core_clk_rate", 0600, entry,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 0ec809ab06e72..0793ab213670d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -104,7 +104,7 @@ static void dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc)
 	struct dpu_hw_wb *hw_wb;
 	struct dpu_hw_wb_qos_cfg qos_cfg;
 	struct dpu_mdss_cfg *catalog;
-	struct dpu_qos_lut_tbl *qos_lut_tb;
+	const struct dpu_qos_lut_tbl *qos_lut_tb;
 
 	if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {
 		DPU_ERROR("invalid parameter(s)\n");
@@ -118,11 +118,11 @@ static void dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc)
 	memset(&qos_cfg, 0, sizeof(struct dpu_hw_wb_qos_cfg));
 	qos_cfg.danger_safe_en = true;
 	qos_cfg.danger_lut =
-		catalog->perf.danger_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
+		catalog->perf->danger_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
 
-	qos_cfg.safe_lut = catalog->perf.safe_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
+	qos_cfg.safe_lut = catalog->perf->safe_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
 
-	qos_lut_tb = &catalog->perf.qos_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
+	qos_lut_tb = &catalog->perf->qos_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
 	qos_cfg.creq_lut = _dpu_hw_get_qos_lut(qos_lut_tb, 0);
 
 	if (hw_wb->ops.setup_qos_lut)
@@ -166,7 +166,7 @@ static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc,
 	if (hw_wb->ops.setup_cdp) {
 		memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg));
 
-		cdp_cfg.enable = phys_enc->dpu_kms->catalog->perf.cdp_cfg
+		cdp_cfg.enable = phys_enc->dpu_kms->catalog->perf->cdp_cfg
 				[DPU_PERF_CDP_USAGE_NRT].wr_enable;
 		cdp_cfg.ubwc_meta_enable =
 				DPU_FORMAT_IS_UBWC(wb_cfg->dest.format);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 61271d9013a11..8d19bb190aaef 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1750,7 +1750,7 @@ static void msm8998_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.vbif_count = ARRAY_SIZE(msm8998_vbif),
 		.vbif = msm8998_vbif,
 		.reg_dma_count = 0,
-		.perf = msm8998_perf_data,
+		.perf = &msm8998_perf_data,
 		.mdss_irqs = IRQ_SM8250_MASK,
 	};
 }
@@ -1781,7 +1781,7 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.vbif = sdm845_vbif,
 		.reg_dma_count = 1,
 		.dma_cfg = sdm845_regdma,
-		.perf = sdm845_perf_data,
+		.perf = &sdm845_perf_data,
 		.mdss_irqs = IRQ_SDM845_MASK,
 	};
 }
@@ -1814,7 +1814,7 @@ static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.vbif = sdm845_vbif,
 		.reg_dma_count = 1,
 		.dma_cfg = sdm845_regdma,
-		.perf = sc7180_perf_data,
+		.perf = &sc7180_perf_data,
 		.mdss_irqs = IRQ_SC7180_MASK,
 	};
 }
@@ -1847,7 +1847,7 @@ static void sm8150_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.vbif = sdm845_vbif,
 		.reg_dma_count = 1,
 		.dma_cfg = sm8150_regdma,
-		.perf = sm8150_perf_data,
+		.perf = &sm8150_perf_data,
 		.mdss_irqs = IRQ_SDM845_MASK,
 	};
 }
@@ -1878,7 +1878,7 @@ static void sc8180x_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.vbif = sdm845_vbif,
 		.reg_dma_count = 1,
 		.dma_cfg = sm8150_regdma,
-		.perf = sc8180x_perf_data,
+		.perf = &sc8180x_perf_data,
 		.mdss_irqs = IRQ_SC8180X_MASK,
 	};
 }
@@ -1913,7 +1913,7 @@ static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.wb = sm8250_wb,
 		.reg_dma_count = 1,
 		.dma_cfg = sm8250_regdma,
-		.perf = sm8250_perf_data,
+		.perf = &sm8250_perf_data,
 		.mdss_irqs = IRQ_SM8250_MASK,
 	};
 }
@@ -1936,7 +1936,7 @@ static void sc7280_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.intf = sc7280_intf,
 		.vbif_count = ARRAY_SIZE(sdm845_vbif),
 		.vbif = sdm845_vbif,
-		.perf = sc7280_perf_data,
+		.perf = &sc7280_perf_data,
 		.mdss_irqs = IRQ_SC7280_MASK,
 	};
 }
@@ -1968,7 +1968,7 @@ static void qcm2290_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.vbif = sdm845_vbif,
 		.reg_dma_count = 1,
 		.dma_cfg = sdm845_regdma,
-		.perf = qcm2290_perf_data,
+		.perf = &qcm2290_perf_data,
 		.mdss_irqs = IRQ_SC7180_MASK,
 	};
 }
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 4225f58d8f977..64ed96b2fa3d0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -868,7 +868,7 @@ struct dpu_mdss_cfg {
 
 	/* Add additional block data structures here */
 
-	struct dpu_perf_cfg perf;
+	const struct dpu_perf_cfg *perf;
 	const struct dpu_format_extended *dma_formats;
 	const struct dpu_format_extended *cursor_formats;
 	const struct dpu_format_extended *vig_formats;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 5b5aef2493900..b887f45596f3c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -160,7 +160,7 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane,
 	vbp = mode->vtotal - mode->vsync_end;
 	vpw = mode->vsync_end - mode->vsync_start;
 	vfp = mode->vsync_start - mode->vdisplay;
-	hw_latency_lines =  dpu_kms->catalog->perf.min_prefill_lines;
+	hw_latency_lines =  dpu_kms->catalog->perf->min_prefill_lines;
 	scale_factor = src_height > dst_height ?
 		mult_frac(src_height, 1, dst_height) : 1;
 
@@ -309,7 +309,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
 	}
 
 	qos_lut = _dpu_hw_get_qos_lut(
-			&pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl);
+			&pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl);
 
 	trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0,
 			(fmt) ? fmt->base.pixel_format : 0,
@@ -336,9 +336,9 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
 	u32 danger_lut, safe_lut;
 
 	if (!pdpu->is_rt_pipe) {
-		danger_lut = pdpu->catalog->perf.danger_lut_tbl
+		danger_lut = pdpu->catalog->perf->danger_lut_tbl
 				[DPU_QOS_LUT_USAGE_NRT];
-		safe_lut = pdpu->catalog->perf.safe_lut_tbl
+		safe_lut = pdpu->catalog->perf->safe_lut_tbl
 				[DPU_QOS_LUT_USAGE_NRT];
 	} else {
 		fmt = dpu_get_dpu_format_ext(
@@ -346,14 +346,14 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
 				fb->modifier);
 
 		if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) {
-			danger_lut = pdpu->catalog->perf.danger_lut_tbl
+			danger_lut = pdpu->catalog->perf->danger_lut_tbl
 					[DPU_QOS_LUT_USAGE_LINEAR];
-			safe_lut = pdpu->catalog->perf.safe_lut_tbl
+			safe_lut = pdpu->catalog->perf->safe_lut_tbl
 					[DPU_QOS_LUT_USAGE_LINEAR];
 		} else {
-			danger_lut = pdpu->catalog->perf.danger_lut_tbl
+			danger_lut = pdpu->catalog->perf->danger_lut_tbl
 					[DPU_QOS_LUT_USAGE_MACROTILE];
-			safe_lut = pdpu->catalog->perf.safe_lut_tbl
+			safe_lut = pdpu->catalog->perf->safe_lut_tbl
 					[DPU_QOS_LUT_USAGE_MACROTILE];
 		}
 	}
@@ -1225,7 +1225,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
 
 			memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg));
 
-			cdp_cfg.enable = pdpu->catalog->perf.cdp_cfg
+			cdp_cfg.enable = pdpu->catalog->perf->cdp_cfg
 					[DPU_PERF_CDP_USAGE_RT].rd_enable;
 			cdp_cfg.ubwc_meta_enable =
 					DPU_FORMAT_IS_UBWC(fmt);
-- 
GitLab


From 481d5dbb93ae5083e20bcf973d8b6696ee54be86 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 2 Jun 2022 23:24:45 +0300
Subject: [PATCH 1539/1731] drm/msm/dpu: change catalog->dma_cfg to be a const
 pointer

Change dpu_mdss_cfg::dma_cfg to be a const pointer rather than embedding
the dpu_reg_dma_cfg struct into the struct dpu_mdss_cfg.

Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/488162/
Link: https://lore.kernel.org/r/20220602202447.1755115-6-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 12 ++++++------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 8d19bb190aaef..0578e0c560d34 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1780,7 +1780,7 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.vbif_count = ARRAY_SIZE(sdm845_vbif),
 		.vbif = sdm845_vbif,
 		.reg_dma_count = 1,
-		.dma_cfg = sdm845_regdma,
+		.dma_cfg = &sdm845_regdma,
 		.perf = &sdm845_perf_data,
 		.mdss_irqs = IRQ_SDM845_MASK,
 	};
@@ -1813,7 +1813,7 @@ static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.vbif_count = ARRAY_SIZE(sdm845_vbif),
 		.vbif = sdm845_vbif,
 		.reg_dma_count = 1,
-		.dma_cfg = sdm845_regdma,
+		.dma_cfg = &sdm845_regdma,
 		.perf = &sc7180_perf_data,
 		.mdss_irqs = IRQ_SC7180_MASK,
 	};
@@ -1846,7 +1846,7 @@ static void sm8150_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.vbif_count = ARRAY_SIZE(sdm845_vbif),
 		.vbif = sdm845_vbif,
 		.reg_dma_count = 1,
-		.dma_cfg = sm8150_regdma,
+		.dma_cfg = &sm8150_regdma,
 		.perf = &sm8150_perf_data,
 		.mdss_irqs = IRQ_SDM845_MASK,
 	};
@@ -1877,7 +1877,7 @@ static void sc8180x_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.vbif_count = ARRAY_SIZE(sdm845_vbif),
 		.vbif = sdm845_vbif,
 		.reg_dma_count = 1,
-		.dma_cfg = sm8150_regdma,
+		.dma_cfg = &sm8150_regdma,
 		.perf = &sc8180x_perf_data,
 		.mdss_irqs = IRQ_SC8180X_MASK,
 	};
@@ -1912,7 +1912,7 @@ static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.wb_count = ARRAY_SIZE(sm8250_wb),
 		.wb = sm8250_wb,
 		.reg_dma_count = 1,
-		.dma_cfg = sm8250_regdma,
+		.dma_cfg = &sm8250_regdma,
 		.perf = &sm8250_perf_data,
 		.mdss_irqs = IRQ_SM8250_MASK,
 	};
@@ -1967,7 +1967,7 @@ static void qcm2290_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.vbif_count = ARRAY_SIZE(sdm845_vbif),
 		.vbif = sdm845_vbif,
 		.reg_dma_count = 1,
-		.dma_cfg = sdm845_regdma,
+		.dma_cfg = &sdm845_regdma,
 		.perf = &qcm2290_perf_data,
 		.mdss_irqs = IRQ_SC7180_MASK,
 	};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 64ed96b2fa3d0..60b403ac9f0fa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -859,7 +859,7 @@ struct dpu_mdss_cfg {
 	const struct dpu_wb_cfg *wb;
 
 	u32 reg_dma_count;
-	struct dpu_reg_dma_cfg dma_cfg;
+	const struct dpu_reg_dma_cfg *dma_cfg;
 
 	u32 ad_count;
 
-- 
GitLab


From 3208496720a180985b35ec7ccad8334ce885d3a8 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 2 Jun 2022 23:24:46 +0300
Subject: [PATCH 1540/1731] drm/msm/dpu: constify struct dpu_mdss_cfg

Mark struct dpu_mdss_cfg instance as a const pointer. This is mostly a
preparation for the next patch.

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/488164/
Link: https://lore.kernel.org/r/20220602202447.1755115-7-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c       |  4 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h       |  4 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c         |  4 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c      | 11 +++--------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h      |  9 ++-------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c          |  4 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h          |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c   |  4 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h   |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c         |  4 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h         |  4 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c             |  8 +++-----
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h             |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c           |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c              |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h              |  2 +-
 17 files changed, 29 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 31767d0f73537..1d9d83d7b99ed 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -468,7 +468,7 @@ static const struct file_operations dpu_core_perf_mode_fops = {
 int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent)
 {
 	struct dpu_core_perf *perf = &dpu_kms->perf;
-	struct dpu_mdss_cfg *catalog = perf->catalog;
+	const struct dpu_mdss_cfg *catalog = perf->catalog;
 	struct dentry *entry;
 
 	entry = debugfs_create_dir("core_perf", parent);
@@ -517,7 +517,7 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf)
 
 int dpu_core_perf_init(struct dpu_core_perf *perf,
 		struct drm_device *dev,
-		struct dpu_mdss_cfg *catalog,
+		const struct dpu_mdss_cfg *catalog,
 		struct clk *core_clk)
 {
 	perf->dev = dev;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
index 8dfcc6db71766..e3795995e1454 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
@@ -68,7 +68,7 @@ struct dpu_core_perf_tune {
 struct dpu_core_perf {
 	struct drm_device *dev;
 	struct dentry *debugfs_root;
-	struct dpu_mdss_cfg *catalog;
+	const struct dpu_mdss_cfg *catalog;
 	struct clk *core_clk;
 	u64 core_clk_rate;
 	u64 max_core_clk_rate;
@@ -119,7 +119,7 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf);
  */
 int dpu_core_perf_init(struct dpu_core_perf *perf,
 		struct drm_device *dev,
-		struct dpu_mdss_cfg *catalog,
+		const struct dpu_mdss_cfg *catalog,
 		struct clk *core_clk);
 
 struct dpu_kms;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index a1b8c45929437..5e88ddd0f4fe5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1205,7 +1205,7 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
 	mutex_unlock(&dpu_enc->enc_lock);
 }
 
-static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog,
+static enum dpu_intf dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog,
 		enum dpu_intf_type type, u32 controller_id)
 {
 	int i = 0;
@@ -1222,7 +1222,7 @@ static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog,
 	return INTF_MAX;
 }
 
-static enum dpu_wb dpu_encoder_get_wb(struct dpu_mdss_cfg *catalog,
+static enum dpu_wb dpu_encoder_get_wb(const struct dpu_mdss_cfg *catalog,
 		enum dpu_intf_type type, u32 controller_id)
 {
 	int i = 0;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 0793ab213670d..2ba9e64445b4c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -103,7 +103,7 @@ static void dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc)
 {
 	struct dpu_hw_wb *hw_wb;
 	struct dpu_hw_wb_qos_cfg qos_cfg;
-	struct dpu_mdss_cfg *catalog;
+	const struct dpu_mdss_cfg *catalog;
 	const struct dpu_qos_lut_tbl *qos_lut_tb;
 
 	if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 0578e0c560d34..535337a9e74fc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1987,17 +1987,12 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
 	{ .hw_rev = DPU_HW_VER_720, .cfg_init = sc7280_cfg_init},
 };
 
-void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg)
-{
-	kfree(dpu_cfg);
-}
-
-struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev)
+const struct dpu_mdss_cfg *dpu_hw_catalog_init(struct device *dev, u32 hw_rev)
 {
 	int i;
 	struct dpu_mdss_cfg *dpu_cfg;
 
-	dpu_cfg = kzalloc(sizeof(*dpu_cfg), GFP_KERNEL);
+	dpu_cfg = devm_kzalloc(dev, sizeof(*dpu_cfg), GFP_KERNEL);
 	if (!dpu_cfg)
 		return ERR_PTR(-ENOMEM);
 
@@ -2009,7 +2004,7 @@ struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev)
 	}
 
 	DPU_ERROR("unsupported chipset id:%X\n", hw_rev);
-	dpu_hw_catalog_deinit(dpu_cfg);
+
 	return ERR_PTR(-ENODEV);
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 60b403ac9f0fa..c317fa27daa09 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -884,16 +884,11 @@ struct dpu_mdss_hw_cfg_handler {
 /**
  * dpu_hw_catalog_init - dpu hardware catalog init API retrieves
  * hardcoded target specific catalog information in config structure
+ * @dev:          DPU device
  * @hw_rev:       caller needs provide the hardware revision.
  *
  * Return: dpu config structure
  */
-struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev);
-
-/**
- * dpu_hw_catalog_deinit - dpu hardware catalog cleanup
- * @dpu_cfg:      pointer returned from init function
- */
-void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg);
+const struct dpu_mdss_cfg *dpu_hw_catalog_init(struct device *dev, u32 hw_rev);
 
 #endif /* _DPU_HW_CATALOG_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
index 6f20d6b6dddd0..184a1b27b13d5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
@@ -158,7 +158,7 @@ static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc,
 }
 
 static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc,
-				       struct dpu_mdss_cfg *m,
+				       const struct dpu_mdss_cfg *m,
 				       void __iomem *addr,
 				       struct dpu_hw_blk_reg_map *b)
 {
@@ -186,7 +186,7 @@ static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops,
 };
 
 struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,
-				   struct dpu_mdss_cfg *m)
+				   const struct dpu_mdss_cfg *m)
 {
 	struct dpu_hw_dsc *c;
 	struct dpu_dsc_cfg *cfg;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
index b39ee4ed32f74..45e4118f1fa27 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
@@ -64,7 +64,7 @@ struct dpu_hw_dsc {
  * Returns: Error code or allocated dpu_hw_dsc context
  */
 struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,
-				   struct dpu_mdss_cfg *m);
+				   const struct dpu_mdss_cfg *m);
 
 /**
  * dpu_hw_dsc_destroy - destroys dsc driver context
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index 01bb2d84c3a05..d83503ea2419a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -398,7 +398,7 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
 	return intr_status;
 }
 
-static void __intr_offset(struct dpu_mdss_cfg *m,
+static void __intr_offset(const struct dpu_mdss_cfg *m,
 		void __iomem *addr, struct dpu_hw_blk_reg_map *hw)
 {
 	hw->base_off = addr;
@@ -406,7 +406,7 @@ static void __intr_offset(struct dpu_mdss_cfg *m,
 }
 
 struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
-		struct dpu_mdss_cfg *m)
+		const struct dpu_mdss_cfg *m)
 {
 	struct dpu_hw_intr *intr;
 	int nirq = MDP_INTR_MAX * 32;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index 4154c5e2b4ae6..46443955443c4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -67,7 +67,7 @@ struct dpu_hw_intr {
  * @m :   pointer to mdss catalog data
  */
 struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
-		struct dpu_mdss_cfg *m);
+		const struct dpu_mdss_cfg *m);
 
 /**
  * dpu_hw_intr_destroy(): Cleanup interrutps hw object
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index ab7f1a4cc578f..da4c7e4f304b4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -761,7 +761,7 @@ int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct dpu_kms *kms,
 
 static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp,
 		void __iomem *addr,
-		struct dpu_mdss_cfg *catalog,
+		const struct dpu_mdss_cfg *catalog,
 		struct dpu_hw_blk_reg_map *b)
 {
 	int i;
@@ -782,7 +782,7 @@ static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp,
 }
 
 struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
-		void __iomem *addr, struct dpu_mdss_cfg *catalog,
+		void __iomem *addr, const struct dpu_mdss_cfg *catalog,
 		bool is_virtual_pipe)
 {
 	struct dpu_hw_pipe *hw_pipe;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index a81e16657d615..7f7338fcddeb6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -360,7 +360,7 @@ struct dpu_hw_sspp_ops {
 struct dpu_hw_pipe {
 	struct dpu_hw_blk base;
 	struct dpu_hw_blk_reg_map hw;
-	struct dpu_mdss_cfg *catalog;
+	const struct dpu_mdss_cfg *catalog;
 	const struct dpu_mdp_cfg *mdp;
 
 	/* Pipe */
@@ -381,7 +381,7 @@ struct dpu_kms;
  * @is_virtual_pipe: is this pipe virtual pipe
  */
 struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
-		void __iomem *addr, struct dpu_mdss_cfg *catalog,
+		void __iomem *addr, const struct dpu_mdss_cfg *catalog,
 		bool is_virtual_pipe);
 
 /**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index e23e2552e8020..324f01b924334 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -745,7 +745,7 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
 	unsigned int num_encoders;
 
 	struct msm_drm_private *priv;
-	struct dpu_mdss_cfg *catalog;
+	const struct dpu_mdss_cfg *catalog;
 
 	int primary_planes_idx = 0, cursor_planes_idx = 0, i, ret;
 	int max_crtc_count;
@@ -842,8 +842,6 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
 		dpu_rm_destroy(&dpu_kms->rm);
 	dpu_kms->rm_init = false;
 
-	if (dpu_kms->catalog)
-		dpu_hw_catalog_deinit(dpu_kms->catalog);
 	dpu_kms->catalog = NULL;
 
 	if (dpu_kms->vbif[VBIF_NRT])
@@ -905,7 +903,7 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k
 {
 	int i;
 	struct dpu_kms *dpu_kms;
-	struct dpu_mdss_cfg *cat;
+	const struct dpu_mdss_cfg *cat;
 	struct dpu_hw_mdp *top;
 
 	dpu_kms = to_dpu_kms(kms);
@@ -1095,7 +1093,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
 
 	pr_info("dpu hardware revision:0x%x\n", dpu_kms->core_rev);
 
-	dpu_kms->catalog = dpu_hw_catalog_init(dpu_kms->core_rev);
+	dpu_kms->catalog = dpu_hw_catalog_init(dev->dev, dpu_kms->core_rev);
 	if (IS_ERR_OR_NULL(dpu_kms->catalog)) {
 		rc = PTR_ERR(dpu_kms->catalog);
 		if (!dpu_kms->catalog)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index 832a0769f2e77..ed80ed6784eee 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -69,7 +69,7 @@ struct dpu_kms {
 	struct msm_kms base;
 	struct drm_device *dev;
 	int core_rev;
-	struct dpu_mdss_cfg *catalog;
+	const struct dpu_mdss_cfg *catalog;
 
 	/* io/register spaces: */
 	void __iomem *mmio, *vbif[VBIF_MAX], *reg_dma;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index b887f45596f3c..7899418c5ca34 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -106,7 +106,7 @@ struct dpu_plane {
 	bool is_rt_pipe;
 	bool is_virtual;
 	struct list_head mplane_list;
-	struct dpu_mdss_cfg *catalog;
+	const struct dpu_mdss_cfg *catalog;
 };
 
 static const uint64_t supported_format_modifiers[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 06f03e7081bc7..73b3442e74679 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -95,7 +95,7 @@ int dpu_rm_destroy(struct dpu_rm *rm)
 }
 
 int dpu_rm_init(struct dpu_rm *rm,
-		struct dpu_mdss_cfg *cat,
+		const struct dpu_mdss_cfg *cat,
 		void __iomem *mmio)
 {
 	int rc, i;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 2f34a31d8d0df..59de72b381f96 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -42,7 +42,7 @@ struct dpu_rm {
  * @Return: 0 on Success otherwise -ERROR
  */
 int dpu_rm_init(struct dpu_rm *rm,
-		struct dpu_mdss_cfg *cat,
+		const struct dpu_mdss_cfg *cat,
 		void __iomem *mmio);
 
 /**
-- 
GitLab


From de7d480f5e8ca6eace02a725abdadb9ea13294ef Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 2 Jun 2022 23:24:47 +0300
Subject: [PATCH 1541/1731] drm/msm/dpu: make dpu hardware catalog static const

Replace superfluous cfg_init functions, which just assign a static
config to the struct dpu_mdss_cfg, with static instances of struct
dpu_mdss_cfg.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/488166/
Link: https://lore.kernel.org/r/20220602202447.1755115-8-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c    | 479 ++++++++----------
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |   5 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c       |   2 +-
 3 files changed, 215 insertions(+), 271 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 535337a9e74fc..de4291936cb22 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1722,285 +1722,230 @@ static const struct dpu_perf_cfg qcm2290_perf_data = {
 	.bw_inefficiency_factor = 120,
 };
 /*************************************************************
- * Hardware catalog init
+ * Hardware catalog
  *************************************************************/
 
-/*
- * msm8998_cfg_init(): populate sdm845 dpu sub-blocks reg offsets
- * and instance counts.
- */
-static void msm8998_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
-{
-	*dpu_cfg = (struct dpu_mdss_cfg){
-		.caps = &msm8998_dpu_caps,
-		.mdp_count = ARRAY_SIZE(msm8998_mdp),
-		.mdp = msm8998_mdp,
-		.ctl_count = ARRAY_SIZE(msm8998_ctl),
-		.ctl = msm8998_ctl,
-		.sspp_count = ARRAY_SIZE(msm8998_sspp),
-		.sspp = msm8998_sspp,
-		.mixer_count = ARRAY_SIZE(msm8998_lm),
-		.mixer = msm8998_lm,
-		.dspp_count = ARRAY_SIZE(msm8998_dspp),
-		.dspp = msm8998_dspp,
-		.pingpong_count = ARRAY_SIZE(sdm845_pp),
-		.pingpong = sdm845_pp,
-		.intf_count = ARRAY_SIZE(msm8998_intf),
-		.intf = msm8998_intf,
-		.vbif_count = ARRAY_SIZE(msm8998_vbif),
-		.vbif = msm8998_vbif,
-		.reg_dma_count = 0,
-		.perf = &msm8998_perf_data,
-		.mdss_irqs = IRQ_SM8250_MASK,
-	};
-}
-
-/*
- * sdm845_cfg_init(): populate sdm845 dpu sub-blocks reg offsets
- * and instance counts.
- */
-static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
-{
-	*dpu_cfg = (struct dpu_mdss_cfg){
-		.caps = &sdm845_dpu_caps,
-		.mdp_count = ARRAY_SIZE(sdm845_mdp),
-		.mdp = sdm845_mdp,
-		.ctl_count = ARRAY_SIZE(sdm845_ctl),
-		.ctl = sdm845_ctl,
-		.sspp_count = ARRAY_SIZE(sdm845_sspp),
-		.sspp = sdm845_sspp,
-		.mixer_count = ARRAY_SIZE(sdm845_lm),
-		.mixer = sdm845_lm,
-		.pingpong_count = ARRAY_SIZE(sdm845_pp),
-		.pingpong = sdm845_pp,
-		.dsc_count = ARRAY_SIZE(sdm845_dsc),
-		.dsc = sdm845_dsc,
-		.intf_count = ARRAY_SIZE(sdm845_intf),
-		.intf = sdm845_intf,
-		.vbif_count = ARRAY_SIZE(sdm845_vbif),
-		.vbif = sdm845_vbif,
-		.reg_dma_count = 1,
-		.dma_cfg = &sdm845_regdma,
-		.perf = &sdm845_perf_data,
-		.mdss_irqs = IRQ_SDM845_MASK,
-	};
-}
-
-/*
- * sc7180_cfg_init(): populate sc7180 dpu sub-blocks reg offsets
- * and instance counts.
- */
-static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
-{
-	*dpu_cfg = (struct dpu_mdss_cfg){
-		.caps = &sc7180_dpu_caps,
-		.mdp_count = ARRAY_SIZE(sc7180_mdp),
-		.mdp = sc7180_mdp,
-		.ctl_count = ARRAY_SIZE(sc7180_ctl),
-		.ctl = sc7180_ctl,
-		.sspp_count = ARRAY_SIZE(sc7180_sspp),
-		.sspp = sc7180_sspp,
-		.mixer_count = ARRAY_SIZE(sc7180_lm),
-		.mixer = sc7180_lm,
-		.dspp_count = ARRAY_SIZE(sc7180_dspp),
-		.dspp = sc7180_dspp,
-		.pingpong_count = ARRAY_SIZE(sc7180_pp),
-		.pingpong = sc7180_pp,
-		.intf_count = ARRAY_SIZE(sc7180_intf),
-		.intf = sc7180_intf,
-		.wb_count = ARRAY_SIZE(sm8250_wb),
-		.wb = sm8250_wb,
-		.vbif_count = ARRAY_SIZE(sdm845_vbif),
-		.vbif = sdm845_vbif,
-		.reg_dma_count = 1,
-		.dma_cfg = &sdm845_regdma,
-		.perf = &sc7180_perf_data,
-		.mdss_irqs = IRQ_SC7180_MASK,
-	};
-}
-
-/*
- * sm8150_cfg_init(): populate sm8150 dpu sub-blocks reg offsets
- * and instance counts.
- */
-static void sm8150_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
-{
-	*dpu_cfg = (struct dpu_mdss_cfg){
-		.caps = &sm8150_dpu_caps,
-		.mdp_count = ARRAY_SIZE(sdm845_mdp),
-		.mdp = sdm845_mdp,
-		.ctl_count = ARRAY_SIZE(sm8150_ctl),
-		.ctl = sm8150_ctl,
-		.sspp_count = ARRAY_SIZE(sdm845_sspp),
-		.sspp = sdm845_sspp,
-		.mixer_count = ARRAY_SIZE(sm8150_lm),
-		.mixer = sm8150_lm,
-		.dspp_count = ARRAY_SIZE(sm8150_dspp),
-		.dspp = sm8150_dspp,
-		.pingpong_count = ARRAY_SIZE(sm8150_pp),
-		.pingpong = sm8150_pp,
-		.merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
-		.merge_3d = sm8150_merge_3d,
-		.intf_count = ARRAY_SIZE(sm8150_intf),
-		.intf = sm8150_intf,
-		.vbif_count = ARRAY_SIZE(sdm845_vbif),
-		.vbif = sdm845_vbif,
-		.reg_dma_count = 1,
-		.dma_cfg = &sm8150_regdma,
-		.perf = &sm8150_perf_data,
-		.mdss_irqs = IRQ_SDM845_MASK,
-	};
-}
-
-/*
- * sc8180x_cfg_init(): populate sc8180 dpu sub-blocks reg offsets
- * and instance counts.
- */
-static void sc8180x_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
-{
-	*dpu_cfg = (struct dpu_mdss_cfg){
-		.caps = &sc8180x_dpu_caps,
-		.mdp_count = ARRAY_SIZE(sc8180x_mdp),
-		.mdp = sc8180x_mdp,
-		.ctl_count = ARRAY_SIZE(sm8150_ctl),
-		.ctl = sm8150_ctl,
-		.sspp_count = ARRAY_SIZE(sdm845_sspp),
-		.sspp = sdm845_sspp,
-		.mixer_count = ARRAY_SIZE(sm8150_lm),
-		.mixer = sm8150_lm,
-		.pingpong_count = ARRAY_SIZE(sm8150_pp),
-		.pingpong = sm8150_pp,
-		.merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
-		.merge_3d = sm8150_merge_3d,
-		.intf_count = ARRAY_SIZE(sc8180x_intf),
-		.intf = sc8180x_intf,
-		.vbif_count = ARRAY_SIZE(sdm845_vbif),
-		.vbif = sdm845_vbif,
-		.reg_dma_count = 1,
-		.dma_cfg = &sm8150_regdma,
-		.perf = &sc8180x_perf_data,
-		.mdss_irqs = IRQ_SC8180X_MASK,
-	};
-}
-
-/*
- * sm8250_cfg_init(): populate sm8250 dpu sub-blocks reg offsets
- * and instance counts.
- */
-static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
-{
-	*dpu_cfg = (struct dpu_mdss_cfg){
-		.caps = &sm8250_dpu_caps,
-		.mdp_count = ARRAY_SIZE(sm8250_mdp),
-		.mdp = sm8250_mdp,
-		.ctl_count = ARRAY_SIZE(sm8150_ctl),
-		.ctl = sm8150_ctl,
-		.sspp_count = ARRAY_SIZE(sm8250_sspp),
-		.sspp = sm8250_sspp,
-		.mixer_count = ARRAY_SIZE(sm8150_lm),
-		.mixer = sm8150_lm,
-		.dspp_count = ARRAY_SIZE(sm8150_dspp),
-		.dspp = sm8150_dspp,
-		.pingpong_count = ARRAY_SIZE(sm8150_pp),
-		.pingpong = sm8150_pp,
-		.merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
-		.merge_3d = sm8150_merge_3d,
-		.intf_count = ARRAY_SIZE(sm8150_intf),
-		.intf = sm8150_intf,
-		.vbif_count = ARRAY_SIZE(sdm845_vbif),
-		.vbif = sdm845_vbif,
-		.wb_count = ARRAY_SIZE(sm8250_wb),
-		.wb = sm8250_wb,
-		.reg_dma_count = 1,
-		.dma_cfg = &sm8250_regdma,
-		.perf = &sm8250_perf_data,
-		.mdss_irqs = IRQ_SM8250_MASK,
-	};
-}
-
-static void sc7280_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
-{
-	*dpu_cfg = (struct dpu_mdss_cfg){
-		.caps = &sc7280_dpu_caps,
-		.mdp_count = ARRAY_SIZE(sc7280_mdp),
-		.mdp = sc7280_mdp,
-		.ctl_count = ARRAY_SIZE(sc7280_ctl),
-		.ctl = sc7280_ctl,
-		.sspp_count = ARRAY_SIZE(sc7280_sspp),
-		.sspp = sc7280_sspp,
-		.mixer_count = ARRAY_SIZE(sc7280_lm),
-		.mixer = sc7280_lm,
-		.pingpong_count = ARRAY_SIZE(sc7280_pp),
-		.pingpong = sc7280_pp,
-		.intf_count = ARRAY_SIZE(sc7280_intf),
-		.intf = sc7280_intf,
-		.vbif_count = ARRAY_SIZE(sdm845_vbif),
-		.vbif = sdm845_vbif,
-		.perf = &sc7280_perf_data,
-		.mdss_irqs = IRQ_SC7280_MASK,
-	};
-}
-
-
-/*
- * qcm2290_cfg_init(): populate qcm2290 dpu sub-blocks reg offsets
- * and instance counts.
- */
-static void qcm2290_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
-{
-	*dpu_cfg = (struct dpu_mdss_cfg){
-		.caps = &qcm2290_dpu_caps,
-		.mdp_count = ARRAY_SIZE(qcm2290_mdp),
-		.mdp = qcm2290_mdp,
-		.ctl_count = ARRAY_SIZE(qcm2290_ctl),
-		.ctl = qcm2290_ctl,
-		.sspp_count = ARRAY_SIZE(qcm2290_sspp),
-		.sspp = qcm2290_sspp,
-		.mixer_count = ARRAY_SIZE(qcm2290_lm),
-		.mixer = qcm2290_lm,
-		.dspp_count = ARRAY_SIZE(qcm2290_dspp),
-		.dspp = qcm2290_dspp,
-		.pingpong_count = ARRAY_SIZE(qcm2290_pp),
-		.pingpong = qcm2290_pp,
-		.intf_count = ARRAY_SIZE(qcm2290_intf),
-		.intf = qcm2290_intf,
-		.vbif_count = ARRAY_SIZE(sdm845_vbif),
-		.vbif = sdm845_vbif,
-		.reg_dma_count = 1,
-		.dma_cfg = &sdm845_regdma,
-		.perf = &qcm2290_perf_data,
-		.mdss_irqs = IRQ_SC7180_MASK,
-	};
-}
+static const struct dpu_mdss_cfg msm8998_dpu_cfg = {
+	.caps = &msm8998_dpu_caps,
+	.mdp_count = ARRAY_SIZE(msm8998_mdp),
+	.mdp = msm8998_mdp,
+	.ctl_count = ARRAY_SIZE(msm8998_ctl),
+	.ctl = msm8998_ctl,
+	.sspp_count = ARRAY_SIZE(msm8998_sspp),
+	.sspp = msm8998_sspp,
+	.mixer_count = ARRAY_SIZE(msm8998_lm),
+	.mixer = msm8998_lm,
+	.dspp_count = ARRAY_SIZE(msm8998_dspp),
+	.dspp = msm8998_dspp,
+	.pingpong_count = ARRAY_SIZE(sdm845_pp),
+	.pingpong = sdm845_pp,
+	.intf_count = ARRAY_SIZE(msm8998_intf),
+	.intf = msm8998_intf,
+	.vbif_count = ARRAY_SIZE(msm8998_vbif),
+	.vbif = msm8998_vbif,
+	.reg_dma_count = 0,
+	.perf = &msm8998_perf_data,
+	.mdss_irqs = IRQ_SM8250_MASK,
+};
+
+static const struct dpu_mdss_cfg sdm845_dpu_cfg = {
+	.caps = &sdm845_dpu_caps,
+	.mdp_count = ARRAY_SIZE(sdm845_mdp),
+	.mdp = sdm845_mdp,
+	.ctl_count = ARRAY_SIZE(sdm845_ctl),
+	.ctl = sdm845_ctl,
+	.sspp_count = ARRAY_SIZE(sdm845_sspp),
+	.sspp = sdm845_sspp,
+	.mixer_count = ARRAY_SIZE(sdm845_lm),
+	.mixer = sdm845_lm,
+	.pingpong_count = ARRAY_SIZE(sdm845_pp),
+	.pingpong = sdm845_pp,
+	.dsc_count = ARRAY_SIZE(sdm845_dsc),
+	.dsc = sdm845_dsc,
+	.intf_count = ARRAY_SIZE(sdm845_intf),
+	.intf = sdm845_intf,
+	.vbif_count = ARRAY_SIZE(sdm845_vbif),
+	.vbif = sdm845_vbif,
+	.reg_dma_count = 1,
+	.dma_cfg = &sdm845_regdma,
+	.perf = &sdm845_perf_data,
+	.mdss_irqs = IRQ_SDM845_MASK,
+};
+
+static const struct dpu_mdss_cfg sc7180_dpu_cfg = {
+	.caps = &sc7180_dpu_caps,
+	.mdp_count = ARRAY_SIZE(sc7180_mdp),
+	.mdp = sc7180_mdp,
+	.ctl_count = ARRAY_SIZE(sc7180_ctl),
+	.ctl = sc7180_ctl,
+	.sspp_count = ARRAY_SIZE(sc7180_sspp),
+	.sspp = sc7180_sspp,
+	.mixer_count = ARRAY_SIZE(sc7180_lm),
+	.mixer = sc7180_lm,
+	.dspp_count = ARRAY_SIZE(sc7180_dspp),
+	.dspp = sc7180_dspp,
+	.pingpong_count = ARRAY_SIZE(sc7180_pp),
+	.pingpong = sc7180_pp,
+	.intf_count = ARRAY_SIZE(sc7180_intf),
+	.intf = sc7180_intf,
+	.wb_count = ARRAY_SIZE(sm8250_wb),
+	.wb = sm8250_wb,
+	.vbif_count = ARRAY_SIZE(sdm845_vbif),
+	.vbif = sdm845_vbif,
+	.reg_dma_count = 1,
+	.dma_cfg = &sdm845_regdma,
+	.perf = &sc7180_perf_data,
+	.mdss_irqs = IRQ_SC7180_MASK,
+};
+
+static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
+	.caps = &sm8150_dpu_caps,
+	.mdp_count = ARRAY_SIZE(sdm845_mdp),
+	.mdp = sdm845_mdp,
+	.ctl_count = ARRAY_SIZE(sm8150_ctl),
+	.ctl = sm8150_ctl,
+	.sspp_count = ARRAY_SIZE(sdm845_sspp),
+	.sspp = sdm845_sspp,
+	.mixer_count = ARRAY_SIZE(sm8150_lm),
+	.mixer = sm8150_lm,
+	.dspp_count = ARRAY_SIZE(sm8150_dspp),
+	.dspp = sm8150_dspp,
+	.pingpong_count = ARRAY_SIZE(sm8150_pp),
+	.pingpong = sm8150_pp,
+	.merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
+	.merge_3d = sm8150_merge_3d,
+	.intf_count = ARRAY_SIZE(sm8150_intf),
+	.intf = sm8150_intf,
+	.vbif_count = ARRAY_SIZE(sdm845_vbif),
+	.vbif = sdm845_vbif,
+	.reg_dma_count = 1,
+	.dma_cfg = &sm8150_regdma,
+	.perf = &sm8150_perf_data,
+	.mdss_irqs = IRQ_SDM845_MASK,
+};
+
+static const struct dpu_mdss_cfg sc8180x_dpu_cfg = {
+	.caps = &sc8180x_dpu_caps,
+	.mdp_count = ARRAY_SIZE(sc8180x_mdp),
+	.mdp = sc8180x_mdp,
+	.ctl_count = ARRAY_SIZE(sm8150_ctl),
+	.ctl = sm8150_ctl,
+	.sspp_count = ARRAY_SIZE(sdm845_sspp),
+	.sspp = sdm845_sspp,
+	.mixer_count = ARRAY_SIZE(sm8150_lm),
+	.mixer = sm8150_lm,
+	.pingpong_count = ARRAY_SIZE(sm8150_pp),
+	.pingpong = sm8150_pp,
+	.merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
+	.merge_3d = sm8150_merge_3d,
+	.intf_count = ARRAY_SIZE(sc8180x_intf),
+	.intf = sc8180x_intf,
+	.vbif_count = ARRAY_SIZE(sdm845_vbif),
+	.vbif = sdm845_vbif,
+	.reg_dma_count = 1,
+	.dma_cfg = &sm8150_regdma,
+	.perf = &sc8180x_perf_data,
+	.mdss_irqs = IRQ_SC8180X_MASK,
+};
+
+static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
+	.caps = &sm8250_dpu_caps,
+	.mdp_count = ARRAY_SIZE(sm8250_mdp),
+	.mdp = sm8250_mdp,
+	.ctl_count = ARRAY_SIZE(sm8150_ctl),
+	.ctl = sm8150_ctl,
+	.sspp_count = ARRAY_SIZE(sm8250_sspp),
+	.sspp = sm8250_sspp,
+	.mixer_count = ARRAY_SIZE(sm8150_lm),
+	.mixer = sm8150_lm,
+	.dspp_count = ARRAY_SIZE(sm8150_dspp),
+	.dspp = sm8150_dspp,
+	.pingpong_count = ARRAY_SIZE(sm8150_pp),
+	.pingpong = sm8150_pp,
+	.merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
+	.merge_3d = sm8150_merge_3d,
+	.intf_count = ARRAY_SIZE(sm8150_intf),
+	.intf = sm8150_intf,
+	.vbif_count = ARRAY_SIZE(sdm845_vbif),
+	.vbif = sdm845_vbif,
+	.wb_count = ARRAY_SIZE(sm8250_wb),
+	.wb = sm8250_wb,
+	.reg_dma_count = 1,
+	.dma_cfg = &sm8250_regdma,
+	.perf = &sm8250_perf_data,
+	.mdss_irqs = IRQ_SM8250_MASK,
+};
+
+static const struct dpu_mdss_cfg sc7280_dpu_cfg = {
+	.caps = &sc7280_dpu_caps,
+	.mdp_count = ARRAY_SIZE(sc7280_mdp),
+	.mdp = sc7280_mdp,
+	.ctl_count = ARRAY_SIZE(sc7280_ctl),
+	.ctl = sc7280_ctl,
+	.sspp_count = ARRAY_SIZE(sc7280_sspp),
+	.sspp = sc7280_sspp,
+	.mixer_count = ARRAY_SIZE(sc7280_lm),
+	.mixer = sc7280_lm,
+	.pingpong_count = ARRAY_SIZE(sc7280_pp),
+	.pingpong = sc7280_pp,
+	.intf_count = ARRAY_SIZE(sc7280_intf),
+	.intf = sc7280_intf,
+	.vbif_count = ARRAY_SIZE(sdm845_vbif),
+	.vbif = sdm845_vbif,
+	.perf = &sc7280_perf_data,
+	.mdss_irqs = IRQ_SC7280_MASK,
+};
+
+static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
+	.caps = &qcm2290_dpu_caps,
+	.mdp_count = ARRAY_SIZE(qcm2290_mdp),
+	.mdp = qcm2290_mdp,
+	.ctl_count = ARRAY_SIZE(qcm2290_ctl),
+	.ctl = qcm2290_ctl,
+	.sspp_count = ARRAY_SIZE(qcm2290_sspp),
+	.sspp = qcm2290_sspp,
+	.mixer_count = ARRAY_SIZE(qcm2290_lm),
+	.mixer = qcm2290_lm,
+	.dspp_count = ARRAY_SIZE(qcm2290_dspp),
+	.dspp = qcm2290_dspp,
+	.pingpong_count = ARRAY_SIZE(qcm2290_pp),
+	.pingpong = qcm2290_pp,
+	.intf_count = ARRAY_SIZE(qcm2290_intf),
+	.intf = qcm2290_intf,
+	.vbif_count = ARRAY_SIZE(sdm845_vbif),
+	.vbif = sdm845_vbif,
+	.reg_dma_count = 1,
+	.dma_cfg = &sdm845_regdma,
+	.perf = &qcm2290_perf_data,
+	.mdss_irqs = IRQ_SC7180_MASK,
+};
 
 static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
-	{ .hw_rev = DPU_HW_VER_300, .cfg_init = msm8998_cfg_init},
-	{ .hw_rev = DPU_HW_VER_301, .cfg_init = msm8998_cfg_init},
-	{ .hw_rev = DPU_HW_VER_400, .cfg_init = sdm845_cfg_init},
-	{ .hw_rev = DPU_HW_VER_401, .cfg_init = sdm845_cfg_init},
-	{ .hw_rev = DPU_HW_VER_500, .cfg_init = sm8150_cfg_init},
-	{ .hw_rev = DPU_HW_VER_501, .cfg_init = sm8150_cfg_init},
-	{ .hw_rev = DPU_HW_VER_510, .cfg_init = sc8180x_cfg_init},
-	{ .hw_rev = DPU_HW_VER_600, .cfg_init = sm8250_cfg_init},
-	{ .hw_rev = DPU_HW_VER_620, .cfg_init = sc7180_cfg_init},
-	{ .hw_rev = DPU_HW_VER_650, .cfg_init = qcm2290_cfg_init},
-	{ .hw_rev = DPU_HW_VER_720, .cfg_init = sc7280_cfg_init},
-};
-
-const struct dpu_mdss_cfg *dpu_hw_catalog_init(struct device *dev, u32 hw_rev)
+	{ .hw_rev = DPU_HW_VER_300, .dpu_cfg = &msm8998_dpu_cfg},
+	{ .hw_rev = DPU_HW_VER_301, .dpu_cfg = &msm8998_dpu_cfg},
+	{ .hw_rev = DPU_HW_VER_400, .dpu_cfg = &sdm845_dpu_cfg},
+	{ .hw_rev = DPU_HW_VER_401, .dpu_cfg = &sdm845_dpu_cfg},
+	{ .hw_rev = DPU_HW_VER_500, .dpu_cfg = &sm8150_dpu_cfg},
+	{ .hw_rev = DPU_HW_VER_501, .dpu_cfg = &sm8150_dpu_cfg},
+	{ .hw_rev = DPU_HW_VER_510, .dpu_cfg = &sc8180x_dpu_cfg},
+	{ .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg},
+	{ .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg},
+	{ .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
+	{ .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
+};
+
+const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev)
 {
 	int i;
 	struct dpu_mdss_cfg *dpu_cfg;
 
-	dpu_cfg = devm_kzalloc(dev, sizeof(*dpu_cfg), GFP_KERNEL);
+	dpu_cfg = kzalloc(sizeof(*dpu_cfg), GFP_KERNEL);
 	if (!dpu_cfg)
 		return ERR_PTR(-ENOMEM);
 
 	for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) {
-		if (cfg_handler[i].hw_rev == hw_rev) {
-			cfg_handler[i].cfg_init(dpu_cfg);
-			return dpu_cfg;
-		}
+		if (cfg_handler[i].hw_rev == hw_rev)
+			return cfg_handler[i].dpu_cfg;
 	}
 
 	DPU_ERROR("unsupported chipset id:%X\n", hw_rev);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index c317fa27daa09..71fe4c505f5b2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -878,17 +878,16 @@ struct dpu_mdss_cfg {
 
 struct dpu_mdss_hw_cfg_handler {
 	u32 hw_rev;
-	void (*cfg_init)(struct dpu_mdss_cfg *dpu_cfg);
+	const struct dpu_mdss_cfg *dpu_cfg;
 };
 
 /**
  * dpu_hw_catalog_init - dpu hardware catalog init API retrieves
  * hardcoded target specific catalog information in config structure
- * @dev:          DPU device
  * @hw_rev:       caller needs provide the hardware revision.
  *
  * Return: dpu config structure
  */
-const struct dpu_mdss_cfg *dpu_hw_catalog_init(struct device *dev, u32 hw_rev);
+const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev);
 
 #endif /* _DPU_HW_CATALOG_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 324f01b924334..1b3781f276d16 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1093,7 +1093,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
 
 	pr_info("dpu hardware revision:0x%x\n", dpu_kms->core_rev);
 
-	dpu_kms->catalog = dpu_hw_catalog_init(dev->dev, dpu_kms->core_rev);
+	dpu_kms->catalog = dpu_hw_catalog_init(dpu_kms->core_rev);
 	if (IS_ERR_OR_NULL(dpu_kms->catalog)) {
 		rc = PTR_ERR(dpu_kms->catalog);
 		if (!dpu_kms->catalog)
-- 
GitLab


From b1ed585a16da8ad3ee426309d684a7a4a919ae56 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Sat, 7 May 2022 14:59:41 +0300
Subject: [PATCH 1542/1731] drm/msm/dpu: dont_use IS_ERR_OR_NULL for encoder
 phys backends

The functions dpu_encoder_phys_foo_init() can not return NULL. Replace
corresponding IS_ERR_OR_NULL() checks with just IS_ERR().

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/485452/
Link: https://lore.kernel.org/r/20220507115942.1705872-1-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 5e88ddd0f4fe5..d14415b58e5b8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2142,10 +2142,10 @@ static int dpu_encoder_virt_add_phys_encs(
 	if (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE) {
 		enc = dpu_encoder_phys_vid_init(params);
 
-		if (IS_ERR_OR_NULL(enc)) {
+		if (IS_ERR(enc)) {
 			DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
 				PTR_ERR(enc));
-			return enc == NULL ? -EINVAL : PTR_ERR(enc);
+			return PTR_ERR(enc);
 		}
 
 		dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
@@ -2155,10 +2155,10 @@ static int dpu_encoder_virt_add_phys_encs(
 	if (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) {
 		enc = dpu_encoder_phys_cmd_init(params);
 
-		if (IS_ERR_OR_NULL(enc)) {
+		if (IS_ERR(enc)) {
 			DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n",
 				PTR_ERR(enc));
-			return enc == NULL ? -EINVAL : PTR_ERR(enc);
+			return PTR_ERR(enc);
 		}
 
 		dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
@@ -2168,10 +2168,10 @@ static int dpu_encoder_virt_add_phys_encs(
 	if (disp_info->intf_type == DRM_MODE_ENCODER_VIRTUAL) {
 		enc = dpu_encoder_phys_wb_init(params);
 
-		if (IS_ERR_OR_NULL(enc)) {
+		if (IS_ERR(enc)) {
 			DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n",
 					PTR_ERR(enc));
-			return enc == NULL ? -EINVAL : PTR_ERR(enc);
+			return PTR_ERR(enc);
 		}
 
 		dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
-- 
GitLab


From b6529e33761f8c2f482d0f7e37e4d7a054cc1d9f Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Sat, 7 May 2022 14:59:42 +0300
Subject: [PATCH 1543/1731] drm/msm/dpu: drop enum msm_display_caps

After the commit c46f0d69039c ("drm/msm: remove unused hotplug and edid
macros from msm_drv.h") the msm_display_caps enum contains two bits
describing whether the encoder should work in video or command mode.
Drop the enum and replace capabilities field in struct msm_display_info
with boolean is_cmd_mode field.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/485454/
Link: https://lore.kernel.org/r/20220507115942.1705872-2-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 31 +++++++++------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h |  4 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c     |  5 +---
 drivers/gpu/drm/msm/msm_drv.h               | 10 -------
 4 files changed, 16 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index d14415b58e5b8..5ccaf35929a0e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -634,7 +634,7 @@ static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
 	}
 
 	if (hw_mdptop->ops.setup_vsync_source &&
-			disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) {
+			disp_info->is_cmd_mode) {
 		for (i = 0; i < dpu_enc->num_phys_encs; i++)
 			vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;
 
@@ -718,8 +718,7 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
 	}
 	dpu_enc = to_dpu_encoder_virt(drm_enc);
 	priv = drm_enc->dev->dev_private;
-	is_vid_mode = dpu_enc->disp_info.capabilities &
-						MSM_DISPLAY_CAP_VID_MODE;
+	is_vid_mode = !dpu_enc->disp_info.is_cmd_mode;
 
 	/*
 	 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
@@ -1603,7 +1602,7 @@ void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
 
 		/* update only for command mode primary ctl */
 		if ((phys == dpu_enc->cur_master) &&
-		   (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE)
+		    disp_info->is_cmd_mode
 		    && ctl->ops.trigger_pending)
 			ctl->ops.trigger_pending(ctl);
 	}
@@ -2139,20 +2138,19 @@ static int dpu_encoder_virt_add_phys_encs(
 		return -EINVAL;
 	}
 
-	if (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE) {
-		enc = dpu_encoder_phys_vid_init(params);
+
+	if (disp_info->intf_type == DRM_MODE_ENCODER_VIRTUAL) {
+		enc = dpu_encoder_phys_wb_init(params);
 
 		if (IS_ERR(enc)) {
-			DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
+			DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n",
 				PTR_ERR(enc));
 			return PTR_ERR(enc);
 		}
 
 		dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
 		++dpu_enc->num_phys_encs;
-	}
-
-	if (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) {
+	} else if (disp_info->is_cmd_mode) {
 		enc = dpu_encoder_phys_cmd_init(params);
 
 		if (IS_ERR(enc)) {
@@ -2163,14 +2161,12 @@ static int dpu_encoder_virt_add_phys_encs(
 
 		dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
 		++dpu_enc->num_phys_encs;
-	}
-
-	if (disp_info->intf_type == DRM_MODE_ENCODER_VIRTUAL) {
-		enc = dpu_encoder_phys_wb_init(params);
+	} else {
+		enc = dpu_encoder_phys_vid_init(params);
 
 		if (IS_ERR(enc)) {
-			DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n",
-					PTR_ERR(enc));
+			DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
+				PTR_ERR(enc));
 			return PTR_ERR(enc);
 		}
 
@@ -2230,8 +2226,7 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
 
 	DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
 
-	if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
-	    (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE))
+	if (disp_info->intf_type != DRM_MODE_ENCODER_VIRTUAL)
 		dpu_enc->idle_pc_supported =
 				dpu_kms->catalog->caps->has_idle_pc;
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 781d41c91994c..861870ac8ae70 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -21,19 +21,19 @@
 /**
  * struct msm_display_info - defines display properties
  * @intf_type:          DRM_MODE_ENCODER_ type
- * @capabilities:       Bitmask of display flags
  * @num_of_h_tiles:     Number of horizontal tiles in case of split interface
  * @h_tile_instance:    Controller instance used per tile. Number of elements is
  *                      based on num_of_h_tiles
+ * @is_cmd_mode		Boolean to indicate if the CMD mode is requested
  * @is_te_using_watchdog_timer:  Boolean to indicate watchdog TE is
  *				 used instead of panel TE in cmd mode panels
  * @dsc:		DSC configuration data for DSC-enabled displays
  */
 struct msm_display_info {
 	int intf_type;
-	uint32_t capabilities;
 	uint32_t num_of_h_tiles;
 	uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
+	bool is_cmd_mode;
 	bool is_te_using_watchdog_timer;
 	struct msm_display_dsc_config *dsc;
 };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 1b3781f276d16..a2d71f0c96af2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -582,9 +582,7 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
 		}
 
 		info.h_tile_instance[info.num_of_h_tiles++] = i;
-		info.capabilities = msm_dsi_is_cmd_mode(priv->dsi[i]) ?
-			MSM_DISPLAY_CAP_CMD_MODE :
-			MSM_DISPLAY_CAP_VID_MODE;
+		info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]);
 
 		info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
 
@@ -637,7 +635,6 @@ static int _dpu_kms_initialize_displayport(struct drm_device *dev,
 
 		info.num_of_h_tiles = 1;
 		info.h_tile_instance[0] = i;
-		info.capabilities = MSM_DISPLAY_CAP_VID_MODE;
 		info.intf_type = encoder->encoder_type;
 		rc = dpu_encoder_setup(dev, encoder, &info);
 		if (rc) {
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 099a67d10c3a7..ae49e56ac0268 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -61,16 +61,6 @@ enum msm_dp_controller {
 #define MSM_GPU_MAX_RINGS 4
 #define MAX_H_TILES_PER_DISPLAY 2
 
-/**
- * enum msm_display_caps - features/capabilities supported by displays
- * @MSM_DISPLAY_CAP_VID_MODE:           Video or "active" mode supported
- * @MSM_DISPLAY_CAP_CMD_MODE:           Command mode supported
- */
-enum msm_display_caps {
-	MSM_DISPLAY_CAP_VID_MODE	= BIT(0),
-	MSM_DISPLAY_CAP_CMD_MODE	= BIT(1),
-};
-
 /**
  * enum msm_event_wait - type of HW events to wait for
  * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
-- 
GitLab


From b4a624acabe99f2ea912e895529b8b37d1fa909d Mon Sep 17 00:00:00 2001
From: Abhinav Kumar <quic_abhinavk@quicinc.com>
Date: Thu, 16 Jun 2022 12:01:22 -0700
Subject: [PATCH 1544/1731] drm/msm/dpu: move intf and wb assignment to
 dpu_encoder_setup_display()

intf and wb resources are not dependent on the rm global
state so need not be allocated during dpu_encoder_virt_atomic_mode_set().

Move the allocation of intf and wb resources to dpu_encoder_setup_display()
so that we can utilize the hw caps even during atomic_check() phase.

Since dpu_encoder_setup_display() already has protection against
setting invalid intf_idx and wb_idx, these checks can now
be dropped as well.

changes in v2:
	- add phys->hw_intf and phys->hw_wb checks back

changes in v3:
	- correct the Fixes tag

Fixes: e02a559a720f ("drm/msm/dpu: make changes to dpu_encoder to support virtual encoder")
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/489885/
Link: https://lore.kernel.org/r/1655406084-17407-1-git-send-email-quic_abhinavk@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 36 ++++++++++-----------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 5ccaf35929a0e..d61874b069c32 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1047,24 +1047,6 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
 		phys->hw_pp = dpu_enc->hw_pp[i];
 		phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
 
-		if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX)
-			phys->hw_intf = dpu_rm_get_intf(&dpu_kms->rm, phys->intf_idx);
-
-		if (phys->wb_idx >= WB_0 && phys->wb_idx < WB_MAX)
-			phys->hw_wb = dpu_rm_get_wb(&dpu_kms->rm, phys->wb_idx);
-
-		if (!phys->hw_intf && !phys->hw_wb) {
-			DPU_ERROR_ENC(dpu_enc,
-				      "no intf or wb block assigned at idx: %d\n", i);
-			return;
-		}
-
-		if (phys->hw_intf && phys->hw_wb) {
-			DPU_ERROR_ENC(dpu_enc,
-					"invalid phys both intf and wb block at idx: %d\n", i);
-			return;
-		}
-
 		phys->cached_mode = crtc_state->adjusted_mode;
 		if (phys->ops.atomic_mode_set)
 			phys->ops.atomic_mode_set(phys, crtc_state, conn_state);
@@ -2289,7 +2271,25 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 		atomic_set(&phys->vsync_cnt, 0);
 		atomic_set(&phys->underrun_cnt, 0);
+
+		if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX)
+			phys->hw_intf = dpu_rm_get_intf(&dpu_kms->rm, phys->intf_idx);
+
+		if (phys->wb_idx >= WB_0 && phys->wb_idx < WB_MAX)
+			phys->hw_wb = dpu_rm_get_wb(&dpu_kms->rm, phys->wb_idx);
+
+		if (!phys->hw_intf && !phys->hw_wb) {
+			DPU_ERROR_ENC(dpu_enc, "no intf or wb block assigned at idx: %d\n", i);
+			ret = -EINVAL;
+		}
+
+		if (phys->hw_intf && phys->hw_wb) {
+			DPU_ERROR_ENC(dpu_enc,
+					"invalid phys both intf and wb block at idx: %d\n", i);
+			ret = -EINVAL;
+		}
 	}
+
 	mutex_unlock(&dpu_enc->enc_lock);
 
 	return ret;
-- 
GitLab


From a370cc392e075de5a4b7f3fb27cdeec0d70b5893 Mon Sep 17 00:00:00 2001
From: Abhinav Kumar <quic_abhinavk@quicinc.com>
Date: Thu, 16 Jun 2022 12:01:23 -0700
Subject: [PATCH 1545/1731] drm/msm/dpu: fix maxlinewidth for writeback block

Writeback block for sm8250 was using the default maxlinewidth
of 2048. But this is not right as it supports upto 4096.

This should have no effect on most resolutions as we are
still limiting upto maxlinewidth of SSPP for adding the modes.

Fix the maxlinewidth for writeback block on sm8250.

changes in v3:
	- correct the Fixes tag

Fixes: 53324b99bd7b ("drm/msm/dpu: add writeback blocks to the sm8250 DPU catalog")
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/489887/
Link: https://lore.kernel.org/r/1655406084-17407-2-git-send-email-quic_abhinavk@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index de4291936cb22..c7d46cd8c35e1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1288,7 +1288,7 @@ static const struct dpu_intf_cfg qcm2290_intf[] = {
  * Writeback blocks config
  *************************************************************/
 #define WB_BLK(_name, _id, _base, _features, _clk_ctrl, \
-		__xin_id, vbif_id, _reg, _wb_done_bit) \
+		__xin_id, vbif_id, _reg, _max_linewidth, _wb_done_bit) \
 	{ \
 	.name = _name, .id = _id, \
 	.base = _base, .len = 0x2c8, \
@@ -1298,13 +1298,13 @@ static const struct dpu_intf_cfg qcm2290_intf[] = {
 	.clk_ctrl = _clk_ctrl, \
 	.xin_id = __xin_id, \
 	.vbif_idx = vbif_id, \
-	.maxlinewidth = DEFAULT_DPU_LINE_WIDTH, \
+	.maxlinewidth = _max_linewidth, \
 	.intr_wb_done = DPU_IRQ_IDX(_reg, _wb_done_bit) \
 	}
 
 static const struct dpu_wb_cfg sm8250_wb[] = {
 	WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,
-			VBIF_RT, MDP_SSPP_TOP0_INTR, 4),
+			VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4),
 };
 
 /*************************************************************
-- 
GitLab


From 4edea8d305873336a626c5f4ce17cb8751059054 Mon Sep 17 00:00:00 2001
From: Abhinav Kumar <quic_abhinavk@quicinc.com>
Date: Thu, 16 Jun 2022 12:01:24 -0700
Subject: [PATCH 1546/1731] drm/msm/dpu: remove hard-coded linewidth limit for
 writeback

Remove the hard-coded limit for writeback and lets start using
the one from catalog instead.

changes in v3:
	- correct the Fixes tag

Fixes: d7d0e73f7de3 ("drm/msm/dpu: introduce the dpu_encoder_phys_* for writeback")
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/489888/
Link: https://lore.kernel.org/r/1655406084-17407-3-git-send-email-quic_abhinavk@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 2ba9e64445b4c..d301070cd4a1e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -20,8 +20,6 @@
 #include "dpu_crtc.h"
 #include "disp/msm_disp_snapshot.h"
 
-#define DEFAULT_MAX_WRITEBACK_WIDTH 2048
-
 #define to_dpu_encoder_phys_wb(x) \
 	container_of(x, struct dpu_encoder_phys_wb, base)
 
@@ -278,9 +276,9 @@ static int dpu_encoder_phys_wb_atomic_check(
 		DPU_ERROR("invalid fb h=%d, mode h=%d\n", fb->height,
 				  mode->vdisplay);
 		return -EINVAL;
-	} else if (fb->width > DEFAULT_MAX_WRITEBACK_WIDTH) {
+	} else if (fb->width > phys_enc->hw_wb->caps->maxlinewidth) {
 		DPU_ERROR("invalid fb w=%d, maxlinewidth=%u\n",
-				  fb->width, DEFAULT_MAX_WRITEBACK_WIDTH);
+				  fb->width, phys_enc->hw_wb->caps->maxlinewidth);
 		return -EINVAL;
 	}
 
-- 
GitLab


From 58fc5d186db44cc33bbd9622eff18a15a995a08b Mon Sep 17 00:00:00 2001
From: Jessica Zhang <quic_jesszhan@quicinc.com>
Date: Wed, 22 Jun 2022 10:18:32 -0700
Subject: [PATCH 1547/1731] drm/msm/dpu: Move LM CRC code into separate method

Move layer mixer-specific section of dpu_crtc_get_crc() into a separate
helper method. This way, we can make it easier to get CRCs from other HW
blocks by adding other get_crc helper methods.

Changes since V1:
- Move common bitmasks to dpu_hw_util.h
- Move common CRC methods to dpu_hw_util.c
- Update copyrights
- Change crcs array to a dynamically allocated array and added it as a
  member of crtc_state

Changes since V2:
- Put changes for hw_util into a separate commit
- Revert crcs array to a static array
- Add else case for set_crc_source to return EINVAL if no valid source
  is selected
- Add DPU_CRTC_MAX_CRC_ENTRIES macro

Changes since V3:
- Move crcs array into dpu_crtc_get_lm_crc
- Remove comment about crcs array in dpu_crtc_state struct
- Revert `lm` rename
- Remove DPU_CRTC_MAX_CRC_ENTRIES macro
- Return EINVAL in dpu_crtc_get_crc if no valid CRC source is set

Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/490735/
Link: https://lore.kernel.org/r/20220622171835.7558-2-quic_jesszhan@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 65 +++++++++++++++---------
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |  2 +
 2 files changed, 43 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index b56f777dbd0ea..b57140c3671a2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
  * Copyright (C) 2013 Red Hat
  * Author: Rob Clark <robdclark@gmail.com>
@@ -99,17 +100,32 @@ static int dpu_crtc_verify_crc_source(struct drm_crtc *crtc,
 	return 0;
 }
 
+static void dpu_crtc_setup_lm_misr(struct dpu_crtc_state *crtc_state)
+{
+	struct dpu_crtc_mixer *m;
+	int i;
+
+	for (i = 0; i < crtc_state->num_mixers; ++i) {
+		m = &crtc_state->mixers[i];
+
+		if (!m->hw_lm || !m->hw_lm->ops.setup_misr)
+			continue;
+
+		/* Calculate MISR over 1 frame */
+		m->hw_lm->ops.setup_misr(m->hw_lm, true, 1);
+	}
+}
+
 static int dpu_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
 {
 	enum dpu_crtc_crc_source source = dpu_crtc_parse_crc_source(src_name);
 	enum dpu_crtc_crc_source current_source;
 	struct dpu_crtc_state *crtc_state;
 	struct drm_device *drm_dev = crtc->dev;
-	struct dpu_crtc_mixer *m;
 
 	bool was_enabled;
 	bool enable = false;
-	int i, ret = 0;
+	int ret = 0;
 
 	if (source < 0) {
 		DRM_DEBUG_DRIVER("Invalid CRC source %s for CRTC%d\n", src_name, crtc->index);
@@ -146,16 +162,10 @@ static int dpu_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
 
 	crtc_state->crc_frame_skip_count = 0;
 
-	for (i = 0; i < crtc_state->num_mixers; ++i) {
-		m = &crtc_state->mixers[i];
-
-		if (!m->hw_lm || !m->hw_lm->ops.setup_misr)
-			continue;
-
-		/* Calculate MISR over 1 frame */
-		m->hw_lm->ops.setup_misr(m->hw_lm, true, 1);
-	}
-
+	if (source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER)
+		dpu_crtc_setup_lm_misr(crtc_state);
+	else
+		ret = -EINVAL;
 
 cleanup:
 	drm_modeset_unlock(&crtc->mutex);
@@ -174,26 +184,17 @@ static u32 dpu_crtc_get_vblank_counter(struct drm_crtc *crtc)
 	return dpu_encoder_get_vsync_count(encoder);
 }
 
-
-static int dpu_crtc_get_crc(struct drm_crtc *crtc)
+static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc,
+		struct dpu_crtc_state *crtc_state)
 {
-	struct dpu_crtc_state *crtc_state;
 	struct dpu_crtc_mixer *m;
 	u32 crcs[CRTC_DUAL_MIXERS];
 
-	int i = 0;
 	int rc = 0;
-
-	crtc_state = to_dpu_crtc_state(crtc->state);
+	int i;
 
 	BUILD_BUG_ON(ARRAY_SIZE(crcs) != ARRAY_SIZE(crtc_state->mixers));
 
-	/* Skip first 2 frames in case of "uncooked" CRCs */
-	if (crtc_state->crc_frame_skip_count < 2) {
-		crtc_state->crc_frame_skip_count++;
-		return 0;
-	}
-
 	for (i = 0; i < crtc_state->num_mixers; ++i) {
 
 		m = &crtc_state->mixers[i];
@@ -214,6 +215,22 @@ static int dpu_crtc_get_crc(struct drm_crtc *crtc)
 			drm_crtc_accurate_vblank_count(crtc), crcs);
 }
 
+static int dpu_crtc_get_crc(struct drm_crtc *crtc)
+{
+	struct dpu_crtc_state *crtc_state = to_dpu_crtc_state(crtc->state);
+
+	/* Skip first 2 frames in case of "uncooked" CRCs */
+	if (crtc_state->crc_frame_skip_count < 2) {
+		crtc_state->crc_frame_skip_count++;
+		return 0;
+	}
+
+	if (crtc_state->crc_source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER)
+		return dpu_crtc_get_lm_crc(crtc, crtc_state);
+
+	return -EINVAL;
+}
+
 static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc,
 					   bool in_vblank_irq,
 					   int *vpos, int *hpos,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index b8785c394fcc6..20df23fe74ed8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -201,6 +201,8 @@ struct dpu_crtc {
  * @mixers        : List of active mixers
  * @num_ctls      : Number of ctl paths in use
  * @hw_ctls       : List of active ctl paths
+ * @crc_source    : CRC source
+ * @crc_frame_skip_count: Number of frames skipped before getting CRC
  */
 struct dpu_crtc_state {
 	struct drm_crtc_state base;
-- 
GitLab


From d9e0f7a6631baf8b5abb2e7364101f05a5b4e7cb Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 17 Feb 2022 08:55:26 +0300
Subject: [PATCH 1548/1731] drm/msm/dp: "inline"
 dp_ctrl_set_clock_rate("ctrl_link")

"ctrl_link" is the clock from DP_CTRL_PM module. The result of setting
the rate for it would be a call to dev_pm_opp_set_rate(). Instead of
saving the rate inside struct dss_module_power, call the
devm_pm_opp_set_rate() directly.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/474712/
Link: https://lore.kernel.org/r/20220217055529.499829-3-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/dp/dp_ctrl.c  |  7 +++++--
 drivers/gpu/drm/msm/dp/dp_power.c | 33 +------------------------------
 2 files changed, 6 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 703249384e7c7..4a9e4f0e9972f 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -1349,12 +1349,11 @@ static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl)
 	opts_dp->lanes = ctrl->link->link_params.num_lanes;
 	opts_dp->link_rate = ctrl->link->link_params.rate / 100;
 	opts_dp->ssc = drm_dp_max_downspread(dpcd);
-	dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link",
-					ctrl->link->link_params.rate * 1000);
 
 	phy_configure(phy, &dp_io->phy_opts);
 	phy_power_on(phy);
 
+	dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000);
 	ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true);
 	if (ret)
 		DRM_ERROR("Unable to start link clocks. ret=%d\n", ret);
@@ -1462,6 +1461,7 @@ static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl)
 	 * link clock might have been adjusted as part of the
 	 * link maintenance.
 	 */
+	dev_pm_opp_set_rate(ctrl->dev, 0);
 	ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
 	if (ret) {
 		DRM_ERROR("Failed to disable clocks. ret=%d\n", ret);
@@ -1493,6 +1493,7 @@ static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl)
 
 	dp_catalog_ctrl_reset(ctrl->catalog);
 
+	dev_pm_opp_set_rate(ctrl->dev, 0);
 	ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
 	if (ret) {
 		DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
@@ -1929,6 +1930,7 @@ int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl)
 		}
 	}
 
+	dev_pm_opp_set_rate(ctrl->dev, 0);
 	ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
 	if (ret) {
 		DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
@@ -1997,6 +1999,7 @@ int dp_ctrl_off(struct dp_ctrl *dp_ctrl)
 	if (ret)
 		DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret);
 
+	dev_pm_opp_set_rate(ctrl->dev, 0);
 	ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
 	if (ret) {
 		DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
diff --git a/drivers/gpu/drm/msm/dp/dp_power.c b/drivers/gpu/drm/msm/dp/dp_power.c
index d9e011775ad88..ccb7c42c862cc 100644
--- a/drivers/gpu/drm/msm/dp/dp_power.c
+++ b/drivers/gpu/drm/msm/dp/dp_power.c
@@ -151,44 +151,13 @@ static int dp_power_clk_deinit(struct dp_power_private *power)
 	return 0;
 }
 
-static int dp_power_clk_set_link_rate(struct dp_power_private *power,
-			struct dss_clk *clk_arry, int num_clk, int enable)
-{
-	u32 rate;
-	int i, rc = 0;
-
-	for (i = 0; i < num_clk; i++) {
-		if (clk_arry[i].clk) {
-			if (clk_arry[i].type == DSS_CLK_PCLK) {
-				if (enable)
-					rate = clk_arry[i].rate;
-				else
-					rate = 0;
-
-				rc = dev_pm_opp_set_rate(power->dev, rate);
-				if (rc)
-					break;
-			}
-
-		}
-	}
-	return rc;
-}
-
 static int dp_power_clk_set_rate(struct dp_power_private *power,
 		enum dp_pm_type module, bool enable)
 {
 	int rc = 0;
 	struct dss_module_power *mp = &power->parser->mp[module];
 
-	if (module == DP_CTRL_PM) {
-		rc = dp_power_clk_set_link_rate(power, mp->clk_config, mp->num_clk, enable);
-		if (rc) {
-			DRM_ERROR("failed to set link clks rate\n");
-			return rc;
-		}
-	} else {
-
+	if (module != DP_CTRL_PM) {
 		if (enable) {
 			rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
 			if (rc) {
-- 
GitLab


From 26345e0117234c89e9d581c63aa25f10e6b50517 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 17 Feb 2022 08:55:27 +0300
Subject: [PATCH 1549/1731] drm/msm/dp: set stream_pixel rate directly

The only clock for which we set the rate is the "stream_pixel". Rather
than storing the rate and then setting it by looping over all the
clocks, set the clock rate directly.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/474714/
Link: https://lore.kernel.org/r/20220217055529.499829-4-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/dp/dp_clk_util.c | 33 ----------------------------
 drivers/gpu/drm/msm/dp/dp_clk_util.h |  9 --------
 drivers/gpu/drm/msm/dp/dp_ctrl.c     |  2 +-
 drivers/gpu/drm/msm/dp/dp_parser.c   |  7 ------
 drivers/gpu/drm/msm/dp/dp_power.c    | 10 ---------
 5 files changed, 1 insertion(+), 60 deletions(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_clk_util.c b/drivers/gpu/drm/msm/dp/dp_clk_util.c
index 44a4fc59ff31b..85abed31c68b2 100644
--- a/drivers/gpu/drm/msm/dp/dp_clk_util.c
+++ b/drivers/gpu/drm/msm/dp/dp_clk_util.c
@@ -51,39 +51,6 @@ error:
 	return rc;
 }
 
-int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk)
-{
-	int i, rc = 0;
-
-	for (i = 0; i < num_clk; i++) {
-		if (clk_arry[i].clk) {
-			if (clk_arry[i].type != DSS_CLK_AHB) {
-				DEV_DBG("%pS->%s: '%s' rate %ld\n",
-					__builtin_return_address(0), __func__,
-					clk_arry[i].clk_name,
-					clk_arry[i].rate);
-				rc = clk_set_rate(clk_arry[i].clk,
-					clk_arry[i].rate);
-				if (rc) {
-					DEV_ERR("%pS->%s: %s failed. rc=%d\n",
-						__builtin_return_address(0),
-						__func__,
-						clk_arry[i].clk_name, rc);
-					break;
-				}
-			}
-		} else {
-			DEV_ERR("%pS->%s: '%s' is not available\n",
-				__builtin_return_address(0), __func__,
-				clk_arry[i].clk_name);
-			rc = -EPERM;
-			break;
-		}
-	}
-
-	return rc;
-}
-
 int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable)
 {
 	int i, rc = 0;
diff --git a/drivers/gpu/drm/msm/dp/dp_clk_util.h b/drivers/gpu/drm/msm/dp/dp_clk_util.h
index 067bf87f3d972..c3d59b5017a93 100644
--- a/drivers/gpu/drm/msm/dp/dp_clk_util.h
+++ b/drivers/gpu/drm/msm/dp/dp_clk_util.h
@@ -13,17 +13,9 @@
 #define DEV_WARN(fmt, args...)  pr_warn(fmt, ##args)
 #define DEV_ERR(fmt, args...)   pr_err(fmt, ##args)
 
-enum dss_clk_type {
-	DSS_CLK_AHB, /* no set rate. rate controlled through rpm */
-	DSS_CLK_PCLK,
-};
-
 struct dss_clk {
 	struct clk *clk; /* clk handle */
 	char clk_name[32];
-	enum dss_clk_type type;
-	unsigned long rate;
-	unsigned long max_rate;
 };
 
 struct dss_module_power {
@@ -33,6 +25,5 @@ struct dss_module_power {
 
 int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk);
 void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk);
-int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk);
 int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable);
 #endif /* __DP_CLK_UTIL_H__ */
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 4a9e4f0e9972f..748339617ad44 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -1332,7 +1332,7 @@ static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl,
 						rate, name);
 
 	if (num)
-		cfg->rate = rate;
+		clk_set_rate(cfg->clk, rate);
 	else
 		DRM_ERROR("%s clock doesn't exit to set rate %lu\n",
 				name, rate);
diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c
index 8f9fed9fdafc4..fc3d88c05f942 100644
--- a/drivers/gpu/drm/msm/dp/dp_parser.c
+++ b/drivers/gpu/drm/msm/dp/dp_parser.c
@@ -237,14 +237,12 @@ static int dp_parser_clock(struct dp_parser *parser)
 			struct dss_clk *clk =
 				&core_power->clk_config[core_clk_index];
 			strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
-			clk->type = DSS_CLK_AHB;
 			core_clk_index++;
 		} else if (dp_parser_check_prefix("stream", clk_name) &&
 				stream_clk_index < stream_clk_count) {
 			struct dss_clk *clk =
 				&stream_power->clk_config[stream_clk_index];
 			strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
-			clk->type = DSS_CLK_PCLK;
 			stream_clk_index++;
 		} else if (dp_parser_check_prefix("ctrl", clk_name) &&
 			   ctrl_clk_index < ctrl_clk_count) {
@@ -252,11 +250,6 @@ static int dp_parser_clock(struct dp_parser *parser)
 				&ctrl_power->clk_config[ctrl_clk_index];
 			strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
 			ctrl_clk_index++;
-			if (dp_parser_check_prefix("ctrl_link", clk_name) ||
-			    dp_parser_check_prefix("stream_pixel", clk_name))
-				clk->type = DSS_CLK_PCLK;
-			else
-				clk->type = DSS_CLK_AHB;
 		}
 	}
 
diff --git a/drivers/gpu/drm/msm/dp/dp_power.c b/drivers/gpu/drm/msm/dp/dp_power.c
index ccb7c42c862cc..ffb84edb0f981 100644
--- a/drivers/gpu/drm/msm/dp/dp_power.c
+++ b/drivers/gpu/drm/msm/dp/dp_power.c
@@ -157,16 +157,6 @@ static int dp_power_clk_set_rate(struct dp_power_private *power,
 	int rc = 0;
 	struct dss_module_power *mp = &power->parser->mp[module];
 
-	if (module != DP_CTRL_PM) {
-		if (enable) {
-			rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
-			if (rc) {
-				DRM_ERROR("failed to set clks rate\n");
-				return rc;
-			}
-		}
-	}
-
 	rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);
 	if (rc) {
 		DRM_ERROR("failed to %d clks, err: %d\n", enable, rc);
-- 
GitLab


From 7b37523fb1d1b2afe64d5fbd16a1ea72596e3663 Mon Sep 17 00:00:00 2001
From: Jessica Zhang <quic_jesszhan@quicinc.com>
Date: Wed, 22 Jun 2022 10:18:33 -0700
Subject: [PATCH 1550/1731] drm/msm/dpu: Move MISR methods to dpu_hw_util

Move layer mixer specific MISR methods to generalized helper methods.
This will make it easier to add CRC support for other blocks in the
future.

Changes since V2:
- Reordered parameters so that offsets are after hw_blk_reg_map
- Fixed mismatched whitespace in bitmask definitions

Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/490732/
Link: https://lore.kernel.org/r/20220622171835.7558-3-quic_jesszhan@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c   | 42 ++----------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 49 ++++++++++++++++++++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 16 +++++++
 3 files changed, 67 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index b41993269d091..f1d237057ed91 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  */
 
@@ -27,11 +28,6 @@
 
 #define LM_MISR_CTRL                     0x310
 #define LM_MISR_SIGNATURE                0x314
-#define LM_MISR_FRAME_COUNT_MASK         0xFF
-#define LM_MISR_CTRL_ENABLE              BIT(8)
-#define LM_MISR_CTRL_STATUS              BIT(9)
-#define LM_MISR_CTRL_STATUS_CLEAR        BIT(10)
-#define LM_MISR_CTRL_FREE_RUN_MASK     BIT(31)
 
 
 static const struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer,
@@ -107,44 +103,12 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx,
 
 static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count)
 {
-	struct dpu_hw_blk_reg_map *c = &ctx->hw;
-	u32 config = 0;
-
-	DPU_REG_WRITE(c, LM_MISR_CTRL, LM_MISR_CTRL_STATUS_CLEAR);
-
-	/* Clear old MISR value (in case it's read before a new value is calculated)*/
-	wmb();
-
-	if (enable) {
-		config = (frame_count & LM_MISR_FRAME_COUNT_MASK) |
-			LM_MISR_CTRL_ENABLE | LM_MISR_CTRL_FREE_RUN_MASK;
-
-		DPU_REG_WRITE(c, LM_MISR_CTRL, config);
-	} else {
-		DPU_REG_WRITE(c, LM_MISR_CTRL, 0);
-	}
-
+	dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, enable, frame_count);
 }
 
 static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value)
 {
-	struct dpu_hw_blk_reg_map *c = &ctx->hw;
-	u32 ctrl = 0;
-
-	if (!misr_value)
-		return -EINVAL;
-
-	ctrl = DPU_REG_READ(c, LM_MISR_CTRL);
-
-	if (!(ctrl & LM_MISR_CTRL_ENABLE))
-		return -ENODATA;
-
-	if (!(ctrl & LM_MISR_CTRL_STATUS))
-		return -EINVAL;
-
-	*misr_value = DPU_REG_READ(c, LM_MISR_SIGNATURE);
-
-	return 0;
+	return dpu_hw_collect_misr(&ctx->hw, LM_MISR_CTRL, LM_MISR_SIGNATURE, misr_value);
 }
 
 static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer *ctx,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
index 512316f25a517..a679757159e92 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
  */
 #define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
 
@@ -447,3 +449,48 @@ u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
 
 	return 0;
 }
+
+void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
+		u32 misr_ctrl_offset,
+		bool enable, u32 frame_count)
+{
+	u32 config = 0;
+
+	DPU_REG_WRITE(c, misr_ctrl_offset, MISR_CTRL_STATUS_CLEAR);
+
+	/* Clear old MISR value (in case it's read before a new value is calculated)*/
+	wmb();
+
+	if (enable) {
+		config = (frame_count & MISR_FRAME_COUNT_MASK) |
+			MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK;
+
+		DPU_REG_WRITE(c, misr_ctrl_offset, config);
+	} else {
+		DPU_REG_WRITE(c, misr_ctrl_offset, 0);
+	}
+
+}
+
+int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
+		u32 misr_ctrl_offset,
+		u32 misr_signature_offset,
+		u32 *misr_value)
+{
+	u32 ctrl = 0;
+
+	if (!misr_value)
+		return -EINVAL;
+
+	ctrl = DPU_REG_READ(c, misr_ctrl_offset);
+
+	if (!(ctrl & MISR_CTRL_ENABLE))
+		return -ENODATA;
+
+	if (!(ctrl & MISR_CTRL_STATUS))
+		return -EINVAL;
+
+	*misr_value = DPU_REG_READ(c, misr_signature_offset);
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index 550b2e2b3e348..ca74474d546b8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  */
 
@@ -12,6 +13,11 @@
 #include "dpu_hw_catalog.h"
 
 #define REG_MASK(n)                     ((BIT(n)) - 1)
+#define MISR_FRAME_COUNT_MASK           0xFF
+#define MISR_CTRL_ENABLE                BIT(8)
+#define MISR_CTRL_STATUS                BIT(9)
+#define MISR_CTRL_STATUS_CLEAR          BIT(10)
+#define MISR_CTRL_FREE_RUN_MASK         BIT(31)
 
 /*
  * This is the common struct maintained by each sub block
@@ -341,4 +347,14 @@ void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map  *c,
 u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
 		u32 total_fl);
 
+void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
+		u32 misr_ctrl_offset,
+		bool enable,
+		u32 frame_count);
+
+int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
+		u32 misr_ctrl_offset,
+		u32 misr_signature_offset,
+		u32 *misr_value);
+
 #endif /* _DPU_HW_UTIL_H */
-- 
GitLab


From fc18ea9818cdf2767f007d108d07a5b47083d67f Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 17 Feb 2022 08:55:28 +0300
Subject: [PATCH 1551/1731] drm/msm/dp: inline dp_power_clk_set_rate()

Inline the dp_power_clk_set_rate() function, replacing it with the call
to msm_dss_enable_clk().

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/474719/
Link: https://lore.kernel.org/r/20220217055529.499829-5-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/dp/dp_power.c | 22 +++++-----------------
 1 file changed, 5 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_power.c b/drivers/gpu/drm/msm/dp/dp_power.c
index ffb84edb0f981..9dadcb6793dd9 100644
--- a/drivers/gpu/drm/msm/dp/dp_power.c
+++ b/drivers/gpu/drm/msm/dp/dp_power.c
@@ -151,21 +151,6 @@ static int dp_power_clk_deinit(struct dp_power_private *power)
 	return 0;
 }
 
-static int dp_power_clk_set_rate(struct dp_power_private *power,
-		enum dp_pm_type module, bool enable)
-{
-	int rc = 0;
-	struct dss_module_power *mp = &power->parser->mp[module];
-
-	rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);
-	if (rc) {
-		DRM_ERROR("failed to %d clks, err: %d\n", enable, rc);
-		return rc;
-	}
-
-	return 0;
-}
-
 int dp_power_clk_status(struct dp_power *dp_power, enum dp_pm_type pm_type)
 {
 	struct dp_power_private *power;
@@ -193,6 +178,7 @@ int dp_power_clk_enable(struct dp_power *dp_power,
 {
 	int rc = 0;
 	struct dp_power_private *power;
+	struct dss_module_power *mp;
 
 	power = container_of(dp_power, struct dp_power_private, dp_power);
 
@@ -225,8 +211,9 @@ int dp_power_clk_enable(struct dp_power *dp_power,
 		if ((pm_type == DP_CTRL_PM) && (!dp_power->core_clks_on)) {
 			drm_dbg_dp(power->drm_dev,
 					"Enable core clks before link clks\n");
+			mp = &power->parser->mp[DP_CORE_PM];
 
-			rc = dp_power_clk_set_rate(power, DP_CORE_PM, enable);
+			rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);
 			if (rc) {
 				DRM_ERROR("fail to enable clks: %s. err=%d\n",
 					dp_parser_pm_name(DP_CORE_PM), rc);
@@ -236,7 +223,8 @@ int dp_power_clk_enable(struct dp_power *dp_power,
 		}
 	}
 
-	rc = dp_power_clk_set_rate(power, pm_type, enable);
+	mp = &power->parser->mp[pm_type];
+	rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);
 	if (rc) {
 		DRM_ERROR("failed to '%s' clks for: %s. err=%d\n",
 			enable ? "enable" : "disable",
-- 
GitLab


From 91143873a05db2ae606128c9e246745a721c60b9 Mon Sep 17 00:00:00 2001
From: Jessica Zhang <quic_jesszhan@quicinc.com>
Date: Wed, 22 Jun 2022 10:18:34 -0700
Subject: [PATCH 1552/1731] drm/msm/dpu: Add MISR register support for
 interface

Add support for setting MISR registers within the interface

Changes since V1:
- Replaced dpu_hw_intf collect_misr and setup_misr implementations with
  calls to dpu_hw_utils helper methods

Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/490730/
Link: https://lore.kernel.org/r/20220622171835.7558-4-quic_jesszhan@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 19 ++++++++++++++++++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h |  8 +++++++-
 2 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index b2ca8d19fdd79..90613f797ff58 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
  */
 
 #include "dpu_hwio.h"
@@ -67,6 +69,9 @@
 #define INTF_CFG2_DATABUS_WIDEN	BIT(0)
 #define INTF_CFG2_DATA_HCTL_EN	BIT(4)
 
+#define INTF_MISR_CTRL			0x180
+#define INTF_MISR_SIGNATURE		0x184
+
 static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf,
 		const struct dpu_mdss_cfg *m,
 		void __iomem *addr,
@@ -318,6 +323,16 @@ static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf)
 	return DPU_REG_READ(c, INTF_LINE_COUNT);
 }
 
+static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf, bool enable, u32 frame_count)
+{
+	dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, enable, frame_count);
+}
+
+static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value)
+{
+	return dpu_hw_collect_misr(&intf->hw, INTF_MISR_CTRL, INTF_MISR_SIGNATURE, misr_value);
+}
+
 static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
 		unsigned long cap)
 {
@@ -328,6 +343,8 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
 	ops->get_line_count = dpu_hw_intf_get_line_count;
 	if (cap & BIT(DPU_INTF_INPUT_CTRL))
 		ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk;
+	ops->setup_misr = dpu_hw_intf_setup_misr;
+	ops->collect_misr = dpu_hw_intf_collect_misr;
 }
 
 struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index 7b2d96ac61e85..8d0e7b5092602 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _DPU_HW_INTF_H
@@ -57,6 +59,8 @@ struct intf_status {
  * @ get_line_count: reads current vertical line counter
  * @bind_pingpong_blk: enable/disable the connection with pingpong which will
  *                     feed pixels to this interface
+ * @setup_misr: enable/disable MISR
+ * @collect_misr: read MISR signature
  */
 struct dpu_hw_intf_ops {
 	void (*setup_timing_gen)(struct dpu_hw_intf *intf,
@@ -77,6 +81,8 @@ struct dpu_hw_intf_ops {
 	void (*bind_pingpong_blk)(struct dpu_hw_intf *intf,
 			bool enable,
 			const enum dpu_pingpong pp);
+	void (*setup_misr)(struct dpu_hw_intf *intf, bool enable, u32 frame_count);
+	int (*collect_misr)(struct dpu_hw_intf *intf, u32 *misr_value);
 };
 
 struct dpu_hw_intf {
-- 
GitLab


From 50b1131e067496b1cdd6e52d48f1aea94eccecaf Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 17 Feb 2022 08:55:29 +0300
Subject: [PATCH 1553/1731] drm/msm/dp: rewrite dss_module_power to use bulk
 clock functions

In order to simplify DP code, drop hand-coded loops over clock arrays,
replacing them with clk_bulk_* functions.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/474717/
Link: https://lore.kernel.org/r/20220217055529.499829-6-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/Makefile         |  1 -
 drivers/gpu/drm/msm/dp/dp_clk_util.c | 87 ----------------------------
 drivers/gpu/drm/msm/dp/dp_clk_util.h | 29 ----------
 drivers/gpu/drm/msm/dp/dp_ctrl.c     |  4 +-
 drivers/gpu/drm/msm/dp/dp_parser.c   | 36 +++++-------
 drivers/gpu/drm/msm/dp/dp_parser.h   |  6 +-
 drivers/gpu/drm/msm/dp/dp_power.c    | 45 ++++----------
 7 files changed, 34 insertions(+), 174 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/dp/dp_clk_util.c
 delete mode 100644 drivers/gpu/drm/msm/dp/dp_clk_util.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 66395ee0862a6..7274c41228ed9 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -119,7 +119,6 @@ msm-$(CONFIG_DRM_MSM_GPU_STATE)	+= adreno/a6xx_gpu_state.o
 
 msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
 	dp/dp_catalog.o \
-	dp/dp_clk_util.o \
 	dp/dp_ctrl.o \
 	dp/dp_display.o \
 	dp/dp_drm.o \
diff --git a/drivers/gpu/drm/msm/dp/dp_clk_util.c b/drivers/gpu/drm/msm/dp/dp_clk_util.c
deleted file mode 100644
index 85abed31c68b2..0000000000000
--- a/drivers/gpu/drm/msm/dp/dp_clk_util.c
+++ /dev/null
@@ -1,87 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2012-2015, 2017-2018, The Linux Foundation.
- * All rights reserved.
- */
-
-#include <linux/clk.h>
-#include <linux/clk/clk-conf.h>
-#include <linux/err.h>
-#include <linux/delay.h>
-#include <linux/of.h>
-
-#include <drm/drm_print.h>
-
-#include "dp_clk_util.h"
-
-void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk)
-{
-	int i;
-
-	for (i = num_clk - 1; i >= 0; i--) {
-		if (clk_arry[i].clk)
-			clk_put(clk_arry[i].clk);
-		clk_arry[i].clk = NULL;
-	}
-}
-
-int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk)
-{
-	int i, rc = 0;
-
-	for (i = 0; i < num_clk; i++) {
-		clk_arry[i].clk = clk_get(dev, clk_arry[i].clk_name);
-		rc = PTR_ERR_OR_ZERO(clk_arry[i].clk);
-		if (rc) {
-			DEV_ERR("%pS->%s: '%s' get failed. rc=%d\n",
-				__builtin_return_address(0), __func__,
-				clk_arry[i].clk_name, rc);
-			goto error;
-		}
-	}
-
-	return rc;
-
-error:
-	for (i--; i >= 0; i--) {
-		if (clk_arry[i].clk)
-			clk_put(clk_arry[i].clk);
-		clk_arry[i].clk = NULL;
-	}
-
-	return rc;
-}
-
-int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable)
-{
-	int i, rc = 0;
-
-	if (enable) {
-		for (i = 0; i < num_clk; i++) {
-			DEV_DBG("%pS->%s: enable '%s'\n",
-				__builtin_return_address(0), __func__,
-				clk_arry[i].clk_name);
-			rc = clk_prepare_enable(clk_arry[i].clk);
-			if (rc)
-				DEV_ERR("%pS->%s: %s en fail. rc=%d\n",
-					__builtin_return_address(0),
-					__func__,
-					clk_arry[i].clk_name, rc);
-
-			if (rc && i) {
-				msm_dss_enable_clk(&clk_arry[i - 1],
-					i - 1, false);
-				break;
-			}
-		}
-	} else {
-		for (i = num_clk - 1; i >= 0; i--) {
-			DEV_DBG("%pS->%s: disable '%s'\n",
-				__builtin_return_address(0), __func__,
-				clk_arry[i].clk_name);
-
-			clk_disable_unprepare(clk_arry[i].clk);
-		}
-	}
-
-	return rc;
-}
diff --git a/drivers/gpu/drm/msm/dp/dp_clk_util.h b/drivers/gpu/drm/msm/dp/dp_clk_util.h
deleted file mode 100644
index c3d59b5017a93..0000000000000
--- a/drivers/gpu/drm/msm/dp/dp_clk_util.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved.
- */
-
-#ifndef __DP_CLK_UTIL_H__
-#define __DP_CLK_UTIL_H__
-
-#include <linux/platform_device.h>
-#include <linux/types.h>
-
-#define DEV_DBG(fmt, args...)   pr_debug(fmt, ##args)
-#define DEV_INFO(fmt, args...)  pr_info(fmt, ##args)
-#define DEV_WARN(fmt, args...)  pr_warn(fmt, ##args)
-#define DEV_ERR(fmt, args...)   pr_err(fmt, ##args)
-
-struct dss_clk {
-	struct clk *clk; /* clk handle */
-	char clk_name[32];
-};
-
-struct dss_module_power {
-	unsigned int num_clk;
-	struct dss_clk *clk_config;
-};
-
-int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk);
-void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk);
-int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable);
-#endif /* __DP_CLK_UTIL_H__ */
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 748339617ad44..ab6aa13b1639a 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -1321,9 +1321,9 @@ static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl,
 			enum dp_pm_type module, char *name, unsigned long rate)
 {
 	u32 num = ctrl->parser->mp[module].num_clk;
-	struct dss_clk *cfg = ctrl->parser->mp[module].clk_config;
+	struct clk_bulk_data *cfg = ctrl->parser->mp[module].clocks;
 
-	while (num && strcmp(cfg->clk_name, name)) {
+	while (num && strcmp(cfg->id, name)) {
 		num--;
 		cfg++;
 	}
diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c
index fc3d88c05f942..29107f108a783 100644
--- a/drivers/gpu/drm/msm/dp/dp_parser.c
+++ b/drivers/gpu/drm/msm/dp/dp_parser.c
@@ -162,11 +162,11 @@ static int dp_parser_init_clk_data(struct dp_parser *parser)
 	}
 
 	core_power->num_clk = core_clk_count;
-	core_power->clk_config = devm_kzalloc(dev,
-			sizeof(struct dss_clk) * core_power->num_clk,
+	core_power->clocks = devm_kcalloc(dev,
+			core_power->num_clk, sizeof(struct clk_bulk_data),
 			GFP_KERNEL);
-	if (!core_power->clk_config)
-		return -EINVAL;
+	if (!core_power->clocks)
+		return -ENOMEM;
 
 	/* Initialize the CTRL power module */
 	if (ctrl_clk_count == 0) {
@@ -175,12 +175,12 @@ static int dp_parser_init_clk_data(struct dp_parser *parser)
 	}
 
 	ctrl_power->num_clk = ctrl_clk_count;
-	ctrl_power->clk_config = devm_kzalloc(dev,
-			sizeof(struct dss_clk) * ctrl_power->num_clk,
+	ctrl_power->clocks = devm_kcalloc(dev,
+			ctrl_power->num_clk, sizeof(struct clk_bulk_data),
 			GFP_KERNEL);
-	if (!ctrl_power->clk_config) {
+	if (!ctrl_power->clocks) {
 		ctrl_power->num_clk = 0;
-		return -EINVAL;
+		return -ENOMEM;
 	}
 
 	/* Initialize the STREAM power module */
@@ -190,12 +190,12 @@ static int dp_parser_init_clk_data(struct dp_parser *parser)
 	}
 
 	stream_power->num_clk = stream_clk_count;
-	stream_power->clk_config = devm_kzalloc(dev,
-			sizeof(struct dss_clk) * stream_power->num_clk,
+	stream_power->clocks = devm_kcalloc(dev,
+			stream_power->num_clk, sizeof(struct clk_bulk_data),
 			GFP_KERNEL);
-	if (!stream_power->clk_config) {
+	if (!stream_power->clocks) {
 		stream_power->num_clk = 0;
-		return -EINVAL;
+		return -ENOMEM;
 	}
 
 	return 0;
@@ -234,21 +234,15 @@ static int dp_parser_clock(struct dp_parser *parser)
 		}
 		if (dp_parser_check_prefix("core", clk_name) &&
 				core_clk_index < core_clk_count) {
-			struct dss_clk *clk =
-				&core_power->clk_config[core_clk_index];
-			strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
+			core_power->clocks[core_clk_index].id = devm_kstrdup(dev, clk_name, GFP_KERNEL);
 			core_clk_index++;
 		} else if (dp_parser_check_prefix("stream", clk_name) &&
 				stream_clk_index < stream_clk_count) {
-			struct dss_clk *clk =
-				&stream_power->clk_config[stream_clk_index];
-			strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
+			stream_power->clocks[stream_clk_index].id = devm_kstrdup(dev, clk_name, GFP_KERNEL);
 			stream_clk_index++;
 		} else if (dp_parser_check_prefix("ctrl", clk_name) &&
 			   ctrl_clk_index < ctrl_clk_count) {
-			struct dss_clk *clk =
-				&ctrl_power->clk_config[ctrl_clk_index];
-			strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
+			ctrl_power->clocks[ctrl_clk_index].id = devm_kstrdup(dev, clk_name, GFP_KERNEL);
 			ctrl_clk_index++;
 		}
 	}
diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h
index 3a4d7972c0697..9abddc6d50c06 100644
--- a/drivers/gpu/drm/msm/dp/dp_parser.h
+++ b/drivers/gpu/drm/msm/dp/dp_parser.h
@@ -10,7 +10,6 @@
 #include <linux/phy/phy.h>
 #include <linux/phy/phy-dp.h>
 
-#include "dp_clk_util.h"
 #include "msm_drv.h"
 
 #define DP_LABEL "MDSS DP DISPLAY"
@@ -106,6 +105,11 @@ struct dp_regulator_cfg {
 	struct dp_reg_entry regs[DP_DEV_REGULATOR_MAX];
 };
 
+struct dss_module_power {
+	unsigned int num_clk;
+	struct clk_bulk_data *clocks;
+};
+
 /**
  * struct dp_parser - DP parser's data exposed to clients
  *
diff --git a/drivers/gpu/drm/msm/dp/dp_power.c b/drivers/gpu/drm/msm/dp/dp_power.c
index 9dadcb6793dd9..b415b35c2b8cc 100644
--- a/drivers/gpu/drm/msm/dp/dp_power.c
+++ b/drivers/gpu/drm/msm/dp/dp_power.c
@@ -106,51 +106,30 @@ static int dp_power_clk_init(struct dp_power_private *power)
 	ctrl = &power->parser->mp[DP_CTRL_PM];
 	stream = &power->parser->mp[DP_STREAM_PM];
 
-	rc = msm_dss_get_clk(dev, core->clk_config, core->num_clk);
+	rc = devm_clk_bulk_get(dev, core->num_clk, core->clocks);
 	if (rc) {
 		DRM_ERROR("failed to get %s clk. err=%d\n",
 			dp_parser_pm_name(DP_CORE_PM), rc);
 		return rc;
 	}
 
-	rc = msm_dss_get_clk(dev, ctrl->clk_config, ctrl->num_clk);
+	rc = devm_clk_bulk_get(dev, ctrl->num_clk, ctrl->clocks);
 	if (rc) {
 		DRM_ERROR("failed to get %s clk. err=%d\n",
 			dp_parser_pm_name(DP_CTRL_PM), rc);
-		msm_dss_put_clk(core->clk_config, core->num_clk);
 		return -ENODEV;
 	}
 
-	rc = msm_dss_get_clk(dev, stream->clk_config, stream->num_clk);
+	rc = devm_clk_bulk_get(dev, stream->num_clk, stream->clocks);
 	if (rc) {
 		DRM_ERROR("failed to get %s clk. err=%d\n",
 			dp_parser_pm_name(DP_CTRL_PM), rc);
-		msm_dss_put_clk(core->clk_config, core->num_clk);
 		return -ENODEV;
 	}
 
 	return 0;
 }
 
-static int dp_power_clk_deinit(struct dp_power_private *power)
-{
-	struct dss_module_power *core, *ctrl, *stream;
-
-	core = &power->parser->mp[DP_CORE_PM];
-	ctrl = &power->parser->mp[DP_CTRL_PM];
-	stream = &power->parser->mp[DP_STREAM_PM];
-
-	if (!core || !ctrl || !stream) {
-		DRM_ERROR("invalid power_data\n");
-		return -EINVAL;
-	}
-
-	msm_dss_put_clk(ctrl->clk_config, ctrl->num_clk);
-	msm_dss_put_clk(core->clk_config, core->num_clk);
-	msm_dss_put_clk(stream->clk_config, stream->num_clk);
-	return 0;
-}
-
 int dp_power_clk_status(struct dp_power *dp_power, enum dp_pm_type pm_type)
 {
 	struct dp_power_private *power;
@@ -213,7 +192,7 @@ int dp_power_clk_enable(struct dp_power *dp_power,
 					"Enable core clks before link clks\n");
 			mp = &power->parser->mp[DP_CORE_PM];
 
-			rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);
+			rc = clk_bulk_prepare_enable(mp->num_clk, mp->clocks);
 			if (rc) {
 				DRM_ERROR("fail to enable clks: %s. err=%d\n",
 					dp_parser_pm_name(DP_CORE_PM), rc);
@@ -224,12 +203,14 @@ int dp_power_clk_enable(struct dp_power *dp_power,
 	}
 
 	mp = &power->parser->mp[pm_type];
-	rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);
-	if (rc) {
-		DRM_ERROR("failed to '%s' clks for: %s. err=%d\n",
-			enable ? "enable" : "disable",
-			dp_parser_pm_name(pm_type), rc);
-		return rc;
+	if (enable) {
+		rc = clk_bulk_prepare_enable(mp->num_clk, mp->clocks);
+		if (rc) {
+			DRM_ERROR("failed to enable clks, err: %d\n", rc);
+			return rc;
+		}
+	} else {
+		clk_bulk_disable_unprepare(mp->num_clk, mp->clocks);
 	}
 
 	if (pm_type == DP_CORE_PM)
@@ -294,9 +275,7 @@ void dp_power_client_deinit(struct dp_power *dp_power)
 
 	power = container_of(dp_power, struct dp_power_private, dp_power);
 
-	dp_power_clk_deinit(power);
 	pm_runtime_disable(&power->pdev->dev);
-
 }
 
 int dp_power_init(struct dp_power *dp_power, bool flip)
-- 
GitLab


From b16650478635f06600bd6bc3cc04f09a5c3888af Mon Sep 17 00:00:00 2001
From: Jessica Zhang <quic_jesszhan@quicinc.com>
Date: Wed, 22 Jun 2022 10:18:35 -0700
Subject: [PATCH 1554/1731] drm/msm/dpu: Add interface support for CRC debugfs

Add support for writing CRC values for the interface block to
the debugfs by calling the necessary MISR setup/collect methods.

Changes since V1:
- Set values_cnt to only include phys with backing hw_intf
- Loop over all drm_encs connected to crtc

Changes since V2:
- Remove vblank.h inclusion
- Change `pos + i` to `pos + entries`
- Initialize values_cnt to 0 for encoder
- Change DPU_CRTC_CRC_SOURCE_INTF to DPU_CRTC_CRC_SOURCE_ENCODER (and
  "intf" to "enc")
- Change dpu_encoder_get_num_phys to dpu_encoder_get_num_hw_intfs
- Add checks for setup_misr and collect_misr in
  dpu_encoder_get_num_hw_intfs

Changes since V3:
- Remove extra whitespace
- Change "enc" to "encoder"
- Move crcs array to dpu_crtc_get_encoder_crc
- Rename dpu_encoder_get_num_hw_intfs to dpu_encoder_get_crc_values_cnt

Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/490736/
Link: https://lore.kernel.org/r/20220622171835.7558-5-quic_jesszhan@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c    | 46 ++++++++++++++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h    |  3 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 64 +++++++++++++++++++++
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 22 +++++++
 4 files changed, 134 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index b57140c3671a2..4dd0ce09ca743 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -79,6 +79,8 @@ static enum dpu_crtc_crc_source dpu_crtc_parse_crc_source(const char *src_name)
 	if (!strcmp(src_name, "auto") ||
 	    !strcmp(src_name, "lm"))
 		return DPU_CRTC_CRC_SOURCE_LAYER_MIXER;
+	if (!strcmp(src_name, "encoder"))
+		return DPU_CRTC_CRC_SOURCE_ENCODER;
 
 	return DPU_CRTC_CRC_SOURCE_INVALID;
 }
@@ -94,8 +96,16 @@ static int dpu_crtc_verify_crc_source(struct drm_crtc *crtc,
 		return -EINVAL;
 	}
 
-	if (source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER)
+	if (source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER) {
 		*values_cnt = crtc_state->num_mixers;
+	} else if (source == DPU_CRTC_CRC_SOURCE_ENCODER) {
+		struct drm_encoder *drm_enc;
+
+		*values_cnt = 0;
+
+		drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask)
+			*values_cnt += dpu_encoder_get_crc_values_cnt(drm_enc);
+	}
 
 	return 0;
 }
@@ -116,6 +126,14 @@ static void dpu_crtc_setup_lm_misr(struct dpu_crtc_state *crtc_state)
 	}
 }
 
+static void dpu_crtc_setup_encoder_misr(struct drm_crtc *crtc)
+{
+	struct drm_encoder *drm_enc;
+
+	drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask)
+		dpu_encoder_setup_misr(drm_enc);
+}
+
 static int dpu_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
 {
 	enum dpu_crtc_crc_source source = dpu_crtc_parse_crc_source(src_name);
@@ -164,6 +182,8 @@ static int dpu_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
 
 	if (source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER)
 		dpu_crtc_setup_lm_misr(crtc_state);
+	else if (source == DPU_CRTC_CRC_SOURCE_ENCODER)
+		dpu_crtc_setup_encoder_misr(crtc);
 	else
 		ret = -EINVAL;
 
@@ -215,6 +235,28 @@ static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc,
 			drm_crtc_accurate_vblank_count(crtc), crcs);
 }
 
+static int dpu_crtc_get_encoder_crc(struct drm_crtc *crtc)
+{
+	struct drm_encoder *drm_enc;
+	int rc, pos = 0;
+	u32 crcs[INTF_MAX];
+
+	drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask) {
+		rc = dpu_encoder_get_crc(drm_enc, crcs, pos);
+		if (rc < 0) {
+			if (rc != -ENODATA)
+				DRM_DEBUG_DRIVER("MISR read failed\n");
+
+			return rc;
+		}
+
+		pos += rc;
+	}
+
+	return drm_crtc_add_crc_entry(crtc, true,
+			drm_crtc_accurate_vblank_count(crtc), crcs);
+}
+
 static int dpu_crtc_get_crc(struct drm_crtc *crtc)
 {
 	struct dpu_crtc_state *crtc_state = to_dpu_crtc_state(crtc->state);
@@ -227,6 +269,8 @@ static int dpu_crtc_get_crc(struct drm_crtc *crtc)
 
 	if (crtc_state->crc_source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER)
 		return dpu_crtc_get_lm_crc(crtc, crtc_state);
+	else if (crtc_state->crc_source == DPU_CRTC_CRC_SOURCE_ENCODER)
+		return dpu_crtc_get_encoder_crc(crtc);
 
 	return -EINVAL;
 }
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 20df23fe74ed8..af03277a3e5aa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2015-2021 The Linux Foundation. All rights reserved.
  * Copyright (C) 2013 Red Hat
  * Author: Rob Clark <robdclark@gmail.com>
@@ -73,11 +74,13 @@ struct dpu_crtc_smmu_state_data {
  * enum dpu_crtc_crc_source: CRC source
  * @DPU_CRTC_CRC_SOURCE_NONE: no source set
  * @DPU_CRTC_CRC_SOURCE_LAYER_MIXER: CRC in layer mixer
+ * @DPU_CRTC_CRC_SOURCE_ENCODER: CRC in encoder
  * @DPU_CRTC_CRC_SOURCE_INVALID: Invalid source
  */
 enum dpu_crtc_crc_source {
 	DPU_CRTC_CRC_SOURCE_NONE = 0,
 	DPU_CRTC_CRC_SOURCE_LAYER_MIXER,
+	DPU_CRTC_CRC_SOURCE_ENCODER,
 	DPU_CRTC_CRC_SOURCE_MAX,
 	DPU_CRTC_CRC_SOURCE_INVALID = -1
 };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index d61874b069c32..f435baa500f8f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -225,6 +225,70 @@ bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc)
 	return dpu_enc->wide_bus_en;
 }
 
+int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc)
+{
+	struct dpu_encoder_virt *dpu_enc;
+	int i, num_intf = 0;
+
+	dpu_enc = to_dpu_encoder_virt(drm_enc);
+
+	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
+		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
+
+		if (phys->hw_intf && phys->hw_intf->ops.setup_misr
+				&& phys->hw_intf->ops.collect_misr)
+			num_intf++;
+	}
+
+	return num_intf;
+}
+
+void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc)
+{
+	struct dpu_encoder_virt *dpu_enc;
+
+	int i;
+
+	dpu_enc = to_dpu_encoder_virt(drm_enc);
+
+	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
+		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
+
+		if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr)
+			continue;
+
+		phys->hw_intf->ops.setup_misr(phys->hw_intf, true, 1);
+	}
+}
+
+int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos)
+{
+	struct dpu_encoder_virt *dpu_enc;
+
+	int i, rc = 0, entries_added = 0;
+
+	if (!drm_enc->crtc) {
+		DRM_ERROR("no crtc found for encoder %d\n", drm_enc->index);
+		return -EINVAL;
+	}
+
+	dpu_enc = to_dpu_encoder_virt(drm_enc);
+
+	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
+		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
+
+		if (!phys->hw_intf || !phys->hw_intf->ops.collect_misr)
+			continue;
+
+		rc = phys->hw_intf->ops.collect_misr(phys->hw_intf, &crcs[pos + entries_added]);
+		if (rc)
+			return rc;
+		entries_added++;
+	}
+
+	return entries_added;
+}
+
 static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc)
 {
 	struct dpu_hw_dither_cfg dither_cfg = { 0 };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 861870ac8ae70..d4d1ecd416e39 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
  * Copyright (C) 2013 Red Hat
  * Author: Rob Clark <robdclark@gmail.com>
@@ -174,6 +175,27 @@ int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc);
 
 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc);
 
+/**
+ * dpu_encoder_get_crc_values_cnt - get number of physical encoders contained
+ *	in virtual encoder that can collect CRC values
+ * @drm_enc:    Pointer to previously created drm encoder structure
+ * Returns:     Number of physical encoders for given drm encoder
+ */
+int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc);
+
+/**
+ * dpu_encoder_setup_misr - enable misr calculations
+ * @drm_enc:    Pointer to previously created drm encoder structure
+ */
+void dpu_encoder_setup_misr(const struct drm_encoder *drm_encoder);
+
+/**
+ * dpu_encoder_get_crc - get the crc value from interface blocks
+ * @drm_enc:    Pointer to previously created drm encoder structure
+ * Returns:     0 on success, error otherwise
+ */
+int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos);
+
 /**
  * dpu_encoder_use_dsc_merge - returns true if the encoder uses DSC merge topology.
  * @drm_enc:    Pointer to previously created drm encoder structure
-- 
GitLab


From ce557eaf52ab03c376bb1a29b17e9abd04f9be26 Mon Sep 17 00:00:00 2001
From: Douglas Anderson <dianders@chromium.org>
Date: Mon, 25 Apr 2022 14:06:42 -0700
Subject: [PATCH 1555/1731] dt-bindings: msm/dp: List supplies in the bindings

We're supposed to list the supplies in the dt bindings but there are
none in the DP controller bindings. Looking at the Linux driver and
existing device trees, we can see that two supplies are expected:
- vdda-0p9-supply
- vdda-1p2-supply

Let's list them both in the bindings. Note that the datasheet for
sc7280 doesn't describe these supplies very verbosely. For the 0p9
supply, for instance, it says "Power for eDP 0.9 V circuits". This
this is obvious from the property name, we don't bother cluttering the
bindings with a description.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/483373/
Link: https://lore.kernel.org/r/20220425140619.1.Ibfde5a26a7182c4b478d570c23d2649823ac2cce@changeid
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../devicetree/bindings/display/msm/dp-controller.yaml      | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index cd05cfd765362..dba31108db513 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -76,6 +76,9 @@ properties:
   "#sound-dai-cells":
     const: 0
 
+  vdda-0p9-supply: true
+  vdda-1p2-supply: true
+
   ports:
     $ref: /schemas/graph.yaml#/properties/ports
     properties:
@@ -137,6 +140,9 @@ examples:
 
         power-domains = <&rpmhpd SC7180_CX>;
 
+        vdda-0p9-supply = <&vdda_usb_ss_dp_core>;
+        vdda-1p2-supply = <&vdda_usb_ss_dp_1p2>;
+
         ports {
             #address-cells = <1>;
             #size-cells = <0>;
-- 
GitLab


From 2709935b4a9e5b2b97288b391da9fe5aab24c280 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Sat, 25 Jun 2022 03:30:28 +0300
Subject: [PATCH 1556/1731] drm/msm/dpu: simplify and unify
 dpu_encoder_get_intf and dpu_encoder_get_wb

Remove extra nestting level from the dpu_encoder_get_intf(), replacing it
with the explicit return in case the INTF_WB was passed to the function.

While we are at it, also change dpu_encoder_get_wb() to also use
explicit return rather than the goto.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/491189/
Link: https://lore.kernel.org/r/20220625003028.383259-1-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index f435baa500f8f..c682d4e02d1bc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1255,12 +1255,13 @@ static enum dpu_intf dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog,
 {
 	int i = 0;
 
-	if (type != INTF_WB) {
-		for (i = 0; i < catalog->intf_count; i++) {
-			if (catalog->intf[i].type == type
-				&& catalog->intf[i].controller_id == controller_id) {
-				return catalog->intf[i].id;
-			}
+	if (type == INTF_WB)
+		return INTF_MAX;
+
+	for (i = 0; i < catalog->intf_count; i++) {
+		if (catalog->intf[i].type == type
+		    && catalog->intf[i].controller_id == controller_id) {
+			return catalog->intf[i].id;
 		}
 	}
 
@@ -1273,14 +1274,13 @@ static enum dpu_wb dpu_encoder_get_wb(const struct dpu_mdss_cfg *catalog,
 	int i = 0;
 
 	if (type != INTF_WB)
-		goto end;
+		return WB_MAX;
 
 	for (i = 0; i < catalog->wb_count; i++) {
 		if (catalog->wb[i].id == controller_id)
 			return catalog->wb[i].id;
 	}
 
-end:
 	return WB_MAX;
 }
 
-- 
GitLab


From 01161a5c0ea6d21da8f59001ffeb95aed4e35526 Mon Sep 17 00:00:00 2001
From: Kuogee Hsieh <quic_khsieh@quicinc.com>
Date: Fri, 3 Jun 2022 13:09:39 -0700
Subject: [PATCH 1557/1731] dt-bindings: msm: update maintainers list with
 proper id

Use quic id instead of codeaurora id in maintainers list
for display devicetree bindings.

Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/488296/
Link: https://lore.kernel.org/r/1654286979-11072-1-git-send-email-quic_khsieh@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../devicetree/bindings/display/msm/dp-controller.yaml          | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index dba31108db513..94bc6e1b64518 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: MSM Display Port Controller
 
 maintainers:
-  - Kuogee Hsieh <khsieh@codeaurora.org>
+  - Kuogee Hsieh <quic_khsieh@quicinc.com>
 
 description: |
   Device tree bindings for DisplayPort host controller for MSM targets
-- 
GitLab


From 3bcecf2b6d06f71ce3392cc5f5a2d8cd52bd72a1 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Wed, 15 Jun 2022 14:59:20 +0300
Subject: [PATCH 1558/1731] drm/msm/dp: make dp_bridge_mode_valid() more
 precise

Make dp_connector_mode_valid() return precise MODE_CLOCK_HIGH rather
than generic MODE_BAD in case the mode clock is higher than
DP_MAX_PIXEL_CLK_KHZ (675 MHz).

Reviewed-by: Kuogee Hsieh<quic_khsieh@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/489554/
Link: https://lore.kernel.org/r/20220615115920.6768-1-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/dp/dp_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index 239c8e3f2fbdc..c234295ce94b6 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -992,7 +992,7 @@ enum drm_mode_status dp_bridge_mode_valid(struct drm_bridge *bridge,
 		return MODE_OK;
 
 	if (mode->clock > DP_MAX_PIXEL_CLK_KHZ)
-		return MODE_BAD;
+		return MODE_CLOCK_HIGH;
 
 	dp_display = container_of(dp, struct dp_display_private, dp_display);
 	link_info = &dp_display->panel->link_info;
-- 
GitLab


From efc7617086bf3ce5a782fcc926947d73788316c5 Mon Sep 17 00:00:00 2001
From: Stephen Boyd <swboyd@chromium.org>
Date: Fri, 24 Jun 2022 17:28:11 -0700
Subject: [PATCH 1559/1731] drm/msm/dp: Remove encoder pointer from struct
 msm_dp

We don't need to stash the encoder here. Instead we can simply pass it
around as an argument.

Cc: Kuogee Hsieh <quic_khsieh@quicinc.com>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/491187/
Link: https://lore.kernel.org/r/20220625002811.3225344-1-swboyd@chromium.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/dp/dp_display.c | 4 +---
 drivers/gpu/drm/msm/dp/dp_display.h | 1 -
 drivers/gpu/drm/msm/dp/dp_drm.c     | 8 ++++----
 drivers/gpu/drm/msm/dp/dp_drm.h     | 2 +-
 4 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index c234295ce94b6..859353fec26d0 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -1624,8 +1624,6 @@ int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
 		return ret;
 	}
 
-	dp_display->encoder = encoder;
-
 	ret = dp_display_get_next_bridge(dp_display);
 	if (ret)
 		return ret;
@@ -1641,7 +1639,7 @@ int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
 
 	priv->bridges[priv->num_bridges++] = dp_display->bridge;
 
-	dp_display->connector = dp_drm_connector_init(dp_display);
+	dp_display->connector = dp_drm_connector_init(dp_display, encoder);
 	if (IS_ERR(dp_display->connector)) {
 		ret = PTR_ERR(dp_display->connector);
 		DRM_DEV_ERROR(dev->dev,
diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h
index 4f9fe4d7610b3..dcedf021f7fe1 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.h
+++ b/drivers/gpu/drm/msm/dp/dp_display.h
@@ -15,7 +15,6 @@ struct msm_dp {
 	struct device *codec_dev;
 	struct drm_bridge *bridge;
 	struct drm_connector *connector;
-	struct drm_encoder *encoder;
 	struct drm_bridge *next_bridge;
 	bool is_connected;
 	bool audio_enabled;
diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c
index 62d58b9c46472..6df25f7662e79 100644
--- a/drivers/gpu/drm/msm/dp/dp_drm.c
+++ b/drivers/gpu/drm/msm/dp/dp_drm.c
@@ -116,7 +116,7 @@ struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device *
 	}
 
 	if (dp_display->next_bridge) {
-		rc = drm_bridge_attach(dp_display->encoder,
+		rc = drm_bridge_attach(encoder,
 					dp_display->next_bridge, bridge,
 					DRM_BRIDGE_ATTACH_NO_CONNECTOR);
 		if (rc < 0) {
@@ -130,15 +130,15 @@ struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device *
 }
 
 /* connector initialization */
-struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display)
+struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display, struct drm_encoder *encoder)
 {
 	struct drm_connector *connector = NULL;
 
-	connector = drm_bridge_connector_init(dp_display->drm_dev, dp_display->encoder);
+	connector = drm_bridge_connector_init(dp_display->drm_dev, encoder);
 	if (IS_ERR(connector))
 		return connector;
 
-	drm_connector_attach_encoder(connector, dp_display->encoder);
+	drm_connector_attach_encoder(connector, encoder);
 
 	return connector;
 }
diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_drm.h
index f4b1ed1e24f7b..82035dbb05789 100644
--- a/drivers/gpu/drm/msm/dp/dp_drm.h
+++ b/drivers/gpu/drm/msm/dp/dp_drm.h
@@ -19,7 +19,7 @@ struct msm_dp_bridge {
 
 #define to_dp_bridge(x)     container_of((x), struct msm_dp_bridge, bridge)
 
-struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display);
+struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display, struct drm_encoder *encoder);
 struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device *dev,
 			struct drm_encoder *encoder);
 
-- 
GitLab


From a18a44e9262d5c7f7fbccbc9458df64d69185d41 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 9 Jun 2022 14:31:48 +0300
Subject: [PATCH 1560/1731] drm/msm/hdmi: fill the pwr_regs bulk regulators

Conversion to use bulk regulator API omitted filling the pwr_regs with
proper regulator IDs. This was left unnoticed, since none of my testing
platforms has used the pwr_regs. Fix this by propagating regulator ids
properly.

Fixes: 31b3b1f5e352 ("drm/msm/hdmi: use bulk regulator API")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/488847/
Link: https://lore.kernel.org/r/20220609113148.3149194-1-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/hdmi/hdmi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index cf24e68864ba0..73070ec1a9361 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -180,6 +180,9 @@ static struct hdmi *msm_hdmi_init(struct platform_device *pdev)
 		goto fail;
 	}
 
+	for (i = 0; i < config->pwr_reg_cnt; i++)
+		hdmi->pwr_regs[i].supply = config->pwr_reg_names[i];
+
 	ret = devm_regulator_bulk_get(&pdev->dev, config->pwr_reg_cnt, hdmi->pwr_regs);
 	if (ret) {
 		DRM_DEV_ERROR(&pdev->dev, "failed to get pwr regulator: %d\n", ret);
-- 
GitLab


From 4f0718bfa47266de90f9e5eec8545ba20939c872 Mon Sep 17 00:00:00 2001
From: Vladimir Lypak <vladimir.lypak@gmail.com>
Date: Sat, 11 Jun 2022 00:02:57 +0200
Subject: [PATCH 1561/1731] drm/msm/dsi: Use single function for reset

There is currently two function for performing reset: dsi_sw_reset and
dsi_sw_reset_restore. Only difference between those is that latter one
assumes that DSI controller is enabled. In contrary former one assumes
that controller is disabled and executed during power-on. However this
assumtion is not true mobile devices which have boot splash set up by
boot-loader.

This patch removes dsi_sw_reset_restore and makes dsi_sw_reset disable
DSI controller during reset sequence if it's enabled.

Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/489152/
Link: https://lore.kernel.org/r/20220610220259.220622-1-luca@z3ntu.xyz
[DB: fixed the typo in the commit message]
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/dsi/dsi_host.c | 48 +++++++++++++-----------------
 1 file changed, 21 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index a95d5df52653c..bab2634ebd11c 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -1080,12 +1080,32 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
 
 static void dsi_sw_reset(struct msm_dsi_host *msm_host)
 {
+	u32 ctrl;
+
+	ctrl = dsi_read(msm_host, REG_DSI_CTRL);
+
+	if (ctrl & DSI_CTRL_ENABLE) {
+		dsi_write(msm_host, REG_DSI_CTRL, ctrl & ~DSI_CTRL_ENABLE);
+		/*
+		 * dsi controller need to be disabled before
+		 * clocks turned on
+		 */
+		wmb();
+	}
+
 	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
 	wmb(); /* clocks need to be enabled before reset */
 
+	/* dsi controller can only be reset while clocks are running */
 	dsi_write(msm_host, REG_DSI_RESET, 1);
 	msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */
 	dsi_write(msm_host, REG_DSI_RESET, 0);
+	wmb(); /* controller out of reset */
+
+	if (ctrl & DSI_CTRL_ENABLE) {
+		dsi_write(msm_host, REG_DSI_CTRL, ctrl);
+		wmb();	/* make sure dsi controller enabled again */
+	}
 }
 
 static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
@@ -1478,32 +1498,6 @@ static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
 	return len;
 }
 
-static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host)
-{
-	u32 data0, data1;
-
-	data0 = dsi_read(msm_host, REG_DSI_CTRL);
-	data1 = data0;
-	data1 &= ~DSI_CTRL_ENABLE;
-	dsi_write(msm_host, REG_DSI_CTRL, data1);
-	/*
-	 * dsi controller need to be disabled before
-	 * clocks turned on
-	 */
-	wmb();
-
-	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
-	wmb();	/* make sure clocks enabled */
-
-	/* dsi controller can only be reset while clocks are running */
-	dsi_write(msm_host, REG_DSI_RESET, 1);
-	msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */
-	dsi_write(msm_host, REG_DSI_RESET, 0);
-	wmb();	/* controller out of reset */
-	dsi_write(msm_host, REG_DSI_CTRL, data0);
-	wmb();	/* make sure dsi controller enabled again */
-}
-
 static void dsi_hpd_worker(struct work_struct *work)
 {
 	struct msm_dsi_host *msm_host =
@@ -1520,7 +1514,7 @@ static void dsi_err_worker(struct work_struct *work)
 
 	pr_err_ratelimited("%s: status=%x\n", __func__, status);
 	if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
-		dsi_sw_reset_restore(msm_host);
+		dsi_sw_reset(msm_host);
 
 	/* It is safe to clear here because error irq is disabled. */
 	msm_host->err_work_state = 0;
-- 
GitLab


From 94a9e05228c8624fbb08f4d8b2775dd0dc588f76 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Mon, 27 Jun 2022 19:54:13 +0300
Subject: [PATCH 1562/1731] drm/msm/dp: use ARRAY_SIZE for calculating
 num_descs

If for some reason the msm_dp_config::descs array starts from non-zero
index or contains the hole, setting the msm_dp_config::num_descs might
be not that obvious and error-prone. Use ARRAY_SIZE to set this field
rather than encoding the value manually.

Reported-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/491399/
Link: https://lore.kernel.org/r/20220627165413.657142-1-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/dp/dp_display.c | 46 +++++++++++++++++------------
 1 file changed, 27 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index 859353fec26d0..b36f8b69a2445 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -131,35 +131,43 @@ struct msm_dp_config {
 	size_t num_descs;
 };
 
+static const struct msm_dp_desc sc7180_dp_descs[] = {
+	[MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort },
+};
+
 static const struct msm_dp_config sc7180_dp_cfg = {
-	.descs = (const struct msm_dp_desc[]) {
-		[MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort },
-	},
-	.num_descs = 1,
+	.descs = sc7180_dp_descs,
+	.num_descs = ARRAY_SIZE(sc7180_dp_descs),
+};
+
+static const struct msm_dp_desc sc7280_dp_descs[] = {
+	[MSM_DP_CONTROLLER_0] =	{ .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true },
+	[MSM_DP_CONTROLLER_1] =	{ .io_start = 0x0aea0000, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true },
 };
 
 static const struct msm_dp_config sc7280_dp_cfg = {
-	.descs = (const struct msm_dp_desc[]) {
-		[MSM_DP_CONTROLLER_0] =	{ .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true },
-		[MSM_DP_CONTROLLER_1] =	{ .io_start = 0x0aea0000, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true },
-	},
-	.num_descs = 2,
+	.descs = sc7280_dp_descs,
+	.num_descs = ARRAY_SIZE(sc7280_dp_descs),
+};
+
+static const struct msm_dp_desc sc8180x_dp_descs[] = {
+	[MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort },
+	[MSM_DP_CONTROLLER_1] = { .io_start = 0x0ae98000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort },
+	[MSM_DP_CONTROLLER_2] = { .io_start = 0x0ae9a000, .connector_type = DRM_MODE_CONNECTOR_eDP },
 };
 
 static const struct msm_dp_config sc8180x_dp_cfg = {
-	.descs = (const struct msm_dp_desc[]) {
-		[MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort },
-		[MSM_DP_CONTROLLER_1] = { .io_start = 0x0ae98000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort },
-		[MSM_DP_CONTROLLER_2] = { .io_start = 0x0ae9a000, .connector_type = DRM_MODE_CONNECTOR_eDP },
-	},
-	.num_descs = 3,
+	.descs = sc8180x_dp_descs,
+	.num_descs = ARRAY_SIZE(sc8180x_dp_descs),
+};
+
+static const struct msm_dp_desc sm8350_dp_descs[] = {
+	[MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort },
 };
 
 static const struct msm_dp_config sm8350_dp_cfg = {
-	.descs = (const struct msm_dp_desc[]) {
-		[MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort },
-	},
-	.num_descs = 1,
+	.descs = sm8350_dp_descs,
+	.num_descs = ARRAY_SIZE(sm8350_dp_descs),
 };
 
 static const struct of_device_id dp_dt_match[] = {
-- 
GitLab


From 2f14bc38d88a47e79fc2d8bf5d4ced752db7e1fb Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 9 Jun 2022 15:23:37 +0300
Subject: [PATCH 1563/1731] dt-bindings: display/msm: hdmi: split and convert
 to yaml

Convert Qualcomm HDMI binding into HDMI TX and PHY yaml bindings.

Changes to schema:
HDMI:
 - fixed reg-names numbering to match 0..3 instead 0,1,3,4
 - dropped qcom,tx-ddc-* from example, they were not documented
 - make phy-names deprecated, drop it from the examples

PHY:
 - moved into phy/ directory
 - split into QMP and non-QMP PHY schemas

Co-developed-by: David Heidelberg <david@ixit.cz>
Signed-off-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/488850/
Link: https://lore.kernel.org/r/20220609122350.3157529-2-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../devicetree/bindings/display/msm/hdmi.txt  |  99 --------
 .../devicetree/bindings/display/msm/hdmi.yaml | 228 ++++++++++++++++++
 .../bindings/phy/qcom,hdmi-phy-other.yaml     | 104 ++++++++
 .../bindings/phy/qcom,hdmi-phy-qmp.yaml       |  85 +++++++
 4 files changed, 417 insertions(+), 99 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/display/msm/hdmi.txt
 create mode 100644 Documentation/devicetree/bindings/display/msm/hdmi.yaml
 create mode 100644 Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml
 create mode 100644 Documentation/devicetree/bindings/phy/qcom,hdmi-phy-qmp.yaml

diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.txt b/Documentation/devicetree/bindings/display/msm/hdmi.txt
deleted file mode 100644
index 5f90a40da51b2..0000000000000
--- a/Documentation/devicetree/bindings/display/msm/hdmi.txt
+++ /dev/null
@@ -1,99 +0,0 @@
-Qualcomm adreno/snapdragon hdmi output
-
-Required properties:
-- compatible: one of the following
-   * "qcom,hdmi-tx-8996"
-   * "qcom,hdmi-tx-8994"
-   * "qcom,hdmi-tx-8084"
-   * "qcom,hdmi-tx-8974"
-   * "qcom,hdmi-tx-8660"
-   * "qcom,hdmi-tx-8960"
-- reg: Physical base address and length of the controller's registers
-- reg-names: "core_physical"
-- interrupts: The interrupt signal from the hdmi block.
-- power-domains: Should be <&mmcc MDSS_GDSC>.
-- clocks: device clocks
-  See ../clocks/clock-bindings.txt for details.
-- core-vdda-supply: phandle to supply regulator
-- hdmi-mux-supply: phandle to mux regulator
-- phys: the phandle for the HDMI PHY device
-- phy-names: the name of the corresponding PHY device
-
-Optional properties:
-- hpd-gpios: hpd pin
-- qcom,hdmi-tx-mux-en-gpios: hdmi mux enable pin
-- qcom,hdmi-tx-mux-sel-gpios: hdmi mux select pin
-- qcom,hdmi-tx-mux-lpm-gpios: hdmi mux lpm pin
-- power-domains: reference to the power domain(s), if available.
-- pinctrl-names: the pin control state names; should contain "default"
-- pinctrl-0: the default pinctrl state (active)
-- pinctrl-1: the "sleep" pinctrl state
-
-HDMI PHY:
-Required properties:
-- compatible: Could be the following
-  * "qcom,hdmi-phy-8660"
-  * "qcom,hdmi-phy-8960"
-  * "qcom,hdmi-phy-8974"
-  * "qcom,hdmi-phy-8084"
-  * "qcom,hdmi-phy-8996"
-- #phy-cells: Number of cells in a PHY specifier; Should be 0.
-- reg: Physical base address and length of the registers of the PHY sub blocks.
-- reg-names: The names of register regions. The following regions are required:
-  * "hdmi_phy"
-  * "hdmi_pll"
-  For HDMI PHY on msm8996, these additional register regions are required:
-    * "hdmi_tx_l0"
-    * "hdmi_tx_l1"
-    * "hdmi_tx_l3"
-    * "hdmi_tx_l4"
-- power-domains: Should be <&mmcc MDSS_GDSC>.
-- clocks: device clocks
-  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- core-vdda-supply: phandle to vdda regulator device node
-
-Example:
-
-/ {
-	...
-
-	hdmi: hdmi@4a00000 {
-		compatible = "qcom,hdmi-tx-8960";
-		reg-names = "core_physical";
-		reg = <0x04a00000 0x2f0>;
-		interrupts = <GIC_SPI 79 0>;
-		power-domains = <&mmcc MDSS_GDSC>;
-		clock-names =
-		    "core",
-		    "master_iface",
-		    "slave_iface";
-		clocks =
-		    <&mmcc HDMI_APP_CLK>,
-		    <&mmcc HDMI_M_AHB_CLK>,
-		    <&mmcc HDMI_S_AHB_CLK>;
-		qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>;
-		qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>;
-		qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
-		core-vdda-supply = <&pm8921_hdmi_mvs>;
-		hdmi-mux-supply = <&ext_3p3v>;
-		pinctrl-names = "default", "sleep";
-		pinctrl-0 = <&hpd_active  &ddc_active  &cec_active>;
-		pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;
-
-		phys = <&hdmi_phy>;
-		phy-names = "hdmi_phy";
-	};
-
-	hdmi_phy: phy@4a00400 {
-		compatible = "qcom,hdmi-phy-8960";
-		reg-names = "hdmi_phy",
-			    "hdmi_pll";
-		reg = <0x4a00400 0x60>,
-		      <0x4a00500 0x100>;
-		#phy-cells = <0>;
-		power-domains = <&mmcc MDSS_GDSC>;
-		clock-names = "slave_iface";
-		clocks = <&mmcc HDMI_S_AHB_CLK>;
-		core-vdda-supply = <&pm8921_hdmi_mvs>;
-	};
-};
diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.yaml b/Documentation/devicetree/bindings/display/msm/hdmi.yaml
new file mode 100644
index 0000000000000..861678b2bf941
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/hdmi.yaml
@@ -0,0 +1,228 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/display/msm/hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Adreno/Snapdragon HDMI output
+
+maintainers:
+  - Rob Clark <robdclark@gmail.com>
+
+properties:
+  compatible:
+    enum:
+      - qcom,hdmi-tx-8084
+      - qcom,hdmi-tx-8660
+      - qcom,hdmi-tx-8960
+      - qcom,hdmi-tx-8974
+      - qcom,hdmi-tx-8994
+      - qcom,hdmi-tx-8996
+
+  clocks:
+    minItems: 1
+    maxItems: 5
+
+  clock-names:
+    minItems: 1
+    maxItems: 5
+
+  reg:
+    minItems: 1
+    maxItems: 3
+
+  reg-names:
+    minItems: 1
+    items:
+      - const: core_physical
+      - const: qfprom_physical
+      - const: hdcp_physical
+
+  interrupts:
+    maxItems: 1
+
+  phys:
+    maxItems: 1
+
+  phy-names:
+    enum:
+      - hdmi_phy
+      - hdmi-phy
+    deprecated: true
+
+  core-vdda-supply:
+    description: phandle to VDDA supply regulator
+
+  hdmi-mux-supply:
+    description: phandle to mux regulator
+
+  core-vcc-supply:
+    description: phandle to VCC supply regulator
+
+  hpd-gpios:
+    maxItems: 1
+    description: hpd pin
+
+  qcom,hdmi-tx-mux-en-gpios:
+    maxItems: 1
+    description: HDMI mux enable pin
+
+  qcom,hdmi-tx-mux-sel-gpios:
+    maxItems: 1
+    description: HDMI mux select pin
+
+  qcom,hdmi-tx-mux-lpm-gpios:
+    maxItems: 1
+    description: HDMI mux lpm pin
+
+  '#sound-dai-cells':
+    const: 1
+
+  ports:
+    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        description: |
+          Input endpoints of the controller.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        description: |
+          Output endpoints of the controller.
+
+    required:
+      - port@0
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - reg
+  - reg-names
+  - interrupts
+  - phys
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,hdmi-tx-8960
+              - qcom,hdmi-tx-8660
+    then:
+      properties:
+        clocks:
+          minItems: 3
+          maxItems: 3
+        clock-names:
+          items:
+            - const: core
+            - const: master_iface
+            - const: slave_iface
+        core-vcc-supplies: false
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,hdmi-tx-8974
+              - qcom,hdmi-tx-8084
+              - qcom,hdmi-tx-8994
+              - qcom,hdmi-tx-8996
+    then:
+      properties:
+        clocks:
+          minItems: 5
+        clock-names:
+          items:
+            - const: mdp_core
+            - const: iface
+            - const: core
+            - const: alt_iface
+            - const: extp
+        hdmi-mux-supplies: false
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    hdmi: hdmi@4a00000 {
+      compatible = "qcom,hdmi-tx-8960";
+      reg-names = "core_physical";
+      reg = <0x04a00000 0x2f0>;
+      interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+      clock-names = "core",
+                    "master_iface",
+                    "slave_iface";
+      clocks = <&clk 61>,
+               <&clk 72>,
+               <&clk 98>;
+      hpd-gpios = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
+      core-vdda-supply = <&pm8921_hdmi_mvs>;
+      hdmi-mux-supply = <&ext_3p3v>;
+      pinctrl-names = "default", "sleep";
+      pinctrl-0 = <&hpd_active  &ddc_active  &cec_active>;
+      pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;
+
+      phys = <&hdmi_phy>;
+    };
+  - |
+    #include <dt-bindings/clock/qcom,gcc-msm8996.h>
+    #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    hdmi@9a0000 {
+      compatible = "qcom,hdmi-tx-8996";
+      reg = <0x009a0000 0x50c>,
+            <0x00070000 0x6158>,
+            <0x009e0000 0xfff>;
+      reg-names = "core_physical",
+                  "qfprom_physical",
+                  "hdcp_physical";
+
+      interrupt-parent = <&mdss>;
+      interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+
+      clocks = <&mmcc MDSS_MDP_CLK>,
+               <&mmcc MDSS_AHB_CLK>,
+               <&mmcc MDSS_HDMI_CLK>,
+               <&mmcc MDSS_HDMI_AHB_CLK>,
+               <&mmcc MDSS_EXTPCLK_CLK>;
+      clock-names = "mdp_core",
+                    "iface",
+                    "core",
+                    "alt_iface",
+                    "extp";
+
+      phys = <&hdmi_phy>;
+      #sound-dai-cells = <1>;
+
+      pinctrl-names = "default", "sleep";
+      pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
+      pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;
+
+      core-vdda-supply = <&vreg_l12a_1p8>;
+      core-vcc-supply = <&vreg_s4a_1p8>;
+
+      ports {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        port@0 {
+          reg = <0>;
+          endpoint {
+            remote-endpoint = <&mdp5_intf3_out>;
+          };
+        };
+      };
+    };
+...
diff --git a/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml b/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml
new file mode 100644
index 0000000000000..fdb277edebebb
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-other.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Adreno/Snapdragon HDMI phy
+
+maintainers:
+  - Rob Clark <robdclark@gmail.com>
+
+properties:
+  compatible:
+    enum:
+      - qcom,hdmi-phy-8660
+      - qcom,hdmi-phy-8960
+      - qcom,hdmi-phy-8974
+      - qcom,hdmi-phy-8084
+
+  reg:
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: hdmi_phy
+      - const: hdmi_pll
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+  clock-names:
+    minItems: 1
+    maxItems: 2
+
+  power-domains:
+    maxItems: 1
+
+  core-vdda-supply:
+    description: phandle to VDDA supply regulator
+
+  vddio-supply:
+    description: phandle to VDD I/O supply regulator
+
+  '#phy-cells':
+    const: 0
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,hdmi-phy-8660
+              - qcom,hdmi-phy-8960
+    then:
+      properties:
+        clocks:
+          maxItems: 1
+        clock-names:
+          items:
+            - const: slave_iface
+        vddio-supply: false
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,hdmi-phy-8084
+              - qcom,hdmi-phy-8974
+    then:
+      properties:
+        clocks:
+          maxItems: 2
+        clock-names:
+          items:
+            - const: iface
+            - const: alt_iface
+
+required:
+  - compatible
+  - clocks
+  - reg
+  - reg-names
+  - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    hdmi_phy: phy@4a00400 {
+      compatible = "qcom,hdmi-phy-8960";
+      reg-names = "hdmi_phy",
+                  "hdmi_pll";
+      reg = <0x4a00400 0x60>,
+            <0x4a00500 0x100>;
+      #phy-cells = <0>;
+      power-domains = <&mmcc 1>;
+      clock-names = "slave_iface";
+      clocks = <&clk 21>;
+      core-vdda-supply = <&pm8921_hdmi_mvs>;
+    };
diff --git a/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-qmp.yaml b/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-qmp.yaml
new file mode 100644
index 0000000000000..eea2e02678edc
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-qmp.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-qmp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Adreno/Snapdragon QMP HDMI phy
+
+maintainers:
+  - Rob Clark <robdclark@gmail.com>
+
+properties:
+  compatible:
+    enum:
+      - qcom,hdmi-phy-8996
+
+  reg:
+    maxItems: 6
+
+  reg-names:
+    items:
+      - const: hdmi_pll
+      - const: hdmi_tx_l0
+      - const: hdmi_tx_l1
+      - const: hdmi_tx_l2
+      - const: hdmi_tx_l3
+      - const: hdmi_phy
+
+  clocks:
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: iface
+      - const: ref
+
+  power-domains:
+    maxItems: 1
+
+  vcca-supply:
+    description: phandle to VCCA supply regulator
+
+  vddio-supply:
+    description: phandle to VDD I/O supply regulator
+
+  '#phy-cells':
+    const: 0
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - reg
+  - reg-names
+  - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    hdmi-phy@9a0600 {
+      compatible = "qcom,hdmi-phy-8996";
+      reg = <0x009a0600 0x1c4>,
+            <0x009a0a00 0x124>,
+            <0x009a0c00 0x124>,
+            <0x009a0e00 0x124>,
+            <0x009a1000 0x124>,
+            <0x009a1200 0x0c8>;
+      reg-names = "hdmi_pll",
+                  "hdmi_tx_l0",
+                  "hdmi_tx_l1",
+                  "hdmi_tx_l2",
+                  "hdmi_tx_l3",
+                  "hdmi_phy";
+
+      clocks = <&mmcc 116>,
+               <&gcc 214>;
+      clock-names = "iface",
+                    "ref";
+      #phy-cells = <0>;
+
+      vddio-supply = <&vreg_l12a_1p8>;
+      vcca-supply = <&vreg_l28a_0p925>;
+    };
-- 
GitLab


From e3c5ce88e8f93b498e0632add6899afc31d89607 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 9 Jun 2022 15:23:38 +0300
Subject: [PATCH 1564/1731] dt-bindings: display/msm: hdmi: mark old GPIO
 properties as deprecated

Mark obsolete GPIO properties as deprecated. They are not used by
existing device trees. While we are at it, also drop them from the
schema example.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/488852/
Link: https://lore.kernel.org/r/20220609122350.3157529-3-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 Documentation/devicetree/bindings/display/msm/hdmi.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.yaml b/Documentation/devicetree/bindings/display/msm/hdmi.yaml
index 861678b2bf941..99b07abcd9607 100644
--- a/Documentation/devicetree/bindings/display/msm/hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/msm/hdmi.yaml
@@ -66,14 +66,17 @@ properties:
 
   qcom,hdmi-tx-mux-en-gpios:
     maxItems: 1
+    deprecated: true
     description: HDMI mux enable pin
 
   qcom,hdmi-tx-mux-sel-gpios:
     maxItems: 1
+    deprecated: true
     description: HDMI mux select pin
 
   qcom,hdmi-tx-mux-lpm-gpios:
     maxItems: 1
+    deprecated: true
     description: HDMI mux lpm pin
 
   '#sound-dai-cells':
-- 
GitLab


From 6c04d89a6138a3d398e893c6c1f7542b1ff406a3 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 9 Jun 2022 15:23:39 +0300
Subject: [PATCH 1565/1731] dt-bindings: display/msm: hdmi: mark
 hdmi-mux-supply as deprecated

hdmi-mux-supply is not used by the SoC's HDMI block, it is thought to
power up the external logic. Thus it should not be a part of HDMI
bindings, but it should be declared at some other device in the DT (like
HDMI mux, bridge, etc). Mark it as deprecated.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/488870/
Link: https://lore.kernel.org/r/20220609122350.3157529-4-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 Documentation/devicetree/bindings/display/msm/hdmi.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.yaml b/Documentation/devicetree/bindings/display/msm/hdmi.yaml
index 99b07abcd9607..47e97669821c3 100644
--- a/Documentation/devicetree/bindings/display/msm/hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/msm/hdmi.yaml
@@ -56,6 +56,7 @@ properties:
 
   hdmi-mux-supply:
     description: phandle to mux regulator
+    deprecated: true
 
   core-vcc-supply:
     description: phandle to VCC supply regulator
-- 
GitLab


From 7fbf025305e9f9f554ec5f0ac781035c7edd27a6 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 9 Jun 2022 15:23:41 +0300
Subject: [PATCH 1566/1731] drm/msm/hdmi: drop the hdmi-mux support

With the last (and only) in-kernel user of hdmi-mux regulator, drop it
from the HDMI driver.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/488855/
Link: https://lore.kernel.org/r/20220609122350.3157529-6-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/hdmi/hdmi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 73070ec1a9361..7267167d5ef1c 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -361,7 +361,7 @@ static const char *hpd_reg_names_none[] = {};
 
 static struct hdmi_platform_config hdmi_tx_8660_config;
 
-static const char *hpd_reg_names_8960[] = {"core-vdda", "hdmi-mux"};
+static const char *hpd_reg_names_8960[] = {"core-vdda"};
 static const char *hpd_clk_names_8960[] = {"core", "master_iface", "slave_iface"};
 
 static struct hdmi_platform_config hdmi_tx_8960_config = {
-- 
GitLab


From 68e674b13b17ed41aac2763d12ece6deaae8df58 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 9 Jun 2022 15:23:42 +0300
Subject: [PATCH 1567/1731] drm/msm/hdmi: drop unused GPIO support

The HDMI driver has code to configure extra GPIOs, which predates
pinctrl support. Nowadays all platforms should use pinctrl instead.
Neither of upstreamed Qualcomm platforms uses these properties, so it's
safe to drop them.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/488858/
Link: https://lore.kernel.org/r/20220609122350.3157529-7-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/hdmi/hdmi.c     | 66 +++++++----------------------
 drivers/gpu/drm/msm/hdmi/hdmi.h     | 13 +-----
 drivers/gpu/drm/msm/hdmi/hdmi_hpd.c | 62 ++-------------------------
 3 files changed, 21 insertions(+), 120 deletions(-)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 7267167d5ef1c..6d79f1b910a51 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -233,6 +233,20 @@ static struct hdmi *msm_hdmi_init(struct platform_device *pdev)
 		hdmi->pwr_clks[i] = clk;
 	}
 
+	hdmi->hpd_gpiod = devm_gpiod_get_optional(&pdev->dev, "hpd", GPIOD_IN);
+	/* This will catch e.g. -EPROBE_DEFER */
+	if (IS_ERR(hdmi->hpd_gpiod)) {
+		ret = PTR_ERR(hdmi->hpd_gpiod);
+		DRM_DEV_ERROR(&pdev->dev, "failed to get hpd gpio: (%d)\n", ret);
+		goto fail;
+	}
+
+	if (!hdmi->hpd_gpiod)
+		DBG("failed to get HPD gpio");
+
+	if (hdmi->hpd_gpiod)
+		gpiod_set_consumer_name(hdmi->hpd_gpiod, "HDMI_HPD");
+
 	pm_runtime_enable(&pdev->dev);
 
 	hdmi->workq = alloc_ordered_workqueue("msm_hdmi", 0);
@@ -409,20 +423,6 @@ static struct hdmi_platform_config hdmi_tx_8996_config = {
 		.hpd_freq      = hpd_clk_freq_8x74,
 };
 
-static const struct {
-	const char *name;
-	const bool output;
-	const int value;
-	const char *label;
-} msm_hdmi_gpio_pdata[] = {
-	{ "qcom,hdmi-tx-ddc-clk", true, 1, "HDMI_DDC_CLK" },
-	{ "qcom,hdmi-tx-ddc-data", true, 1, "HDMI_DDC_DATA" },
-	{ "qcom,hdmi-tx-hpd", false, 1, "HDMI_HPD" },
-	{ "qcom,hdmi-tx-mux-en", true, 1, "HDMI_MUX_EN" },
-	{ "qcom,hdmi-tx-mux-sel", true, 0, "HDMI_MUX_SEL" },
-	{ "qcom,hdmi-tx-mux-lpm", true, 1, "HDMI_MUX_LPM" },
-};
-
 /*
  * HDMI audio codec callbacks
  */
@@ -534,7 +534,7 @@ static int msm_hdmi_bind(struct device *dev, struct device *master, void *data)
 	struct hdmi_platform_config *hdmi_cfg;
 	struct hdmi *hdmi;
 	struct device_node *of_node = dev->of_node;
-	int i, err;
+	int err;
 
 	hdmi_cfg = (struct hdmi_platform_config *)
 			of_device_get_match_data(dev);
@@ -546,42 +546,6 @@ static int msm_hdmi_bind(struct device *dev, struct device *master, void *data)
 	hdmi_cfg->mmio_name     = "core_physical";
 	hdmi_cfg->qfprom_mmio_name = "qfprom_physical";
 
-	for (i = 0; i < HDMI_MAX_NUM_GPIO; i++) {
-		const char *name = msm_hdmi_gpio_pdata[i].name;
-		struct gpio_desc *gpiod;
-
-		/*
-		 * We are fetching the GPIO lines "as is" since the connector
-		 * code is enabling and disabling the lines. Until that point
-		 * the power-on default value will be kept.
-		 */
-		gpiod = devm_gpiod_get_optional(dev, name, GPIOD_ASIS);
-		/* This will catch e.g. -PROBE_DEFER */
-		if (IS_ERR(gpiod))
-			return PTR_ERR(gpiod);
-		if (!gpiod) {
-			/* Try a second time, stripping down the name */
-			char name3[32];
-
-			/*
-			 * Try again after stripping out the "qcom,hdmi-tx"
-			 * prefix. This is mainly to match "hpd-gpios" used
-			 * in the upstream bindings.
-			 */
-			if (sscanf(name, "qcom,hdmi-tx-%s", name3))
-				gpiod = devm_gpiod_get_optional(dev, name3, GPIOD_ASIS);
-			if (IS_ERR(gpiod))
-				return PTR_ERR(gpiod);
-			if (!gpiod)
-				DBG("failed to get gpio: %s", name);
-		}
-		hdmi_cfg->gpios[i].gpiod = gpiod;
-		if (gpiod)
-			gpiod_set_consumer_name(gpiod, msm_hdmi_gpio_pdata[i].label);
-		hdmi_cfg->gpios[i].output = msm_hdmi_gpio_pdata[i].output;
-		hdmi_cfg->gpios[i].value = msm_hdmi_gpio_pdata[i].value;
-	}
-
 	dev->platform_data = hdmi_cfg;
 
 	hdmi = msm_hdmi_init(to_platform_device(dev));
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index 736f348befb38..a6c88d157bc3a 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -19,17 +19,9 @@
 #include "msm_drv.h"
 #include "hdmi.xml.h"
 
-#define HDMI_MAX_NUM_GPIO	6
-
 struct hdmi_phy;
 struct hdmi_platform_config;
 
-struct hdmi_gpio_data {
-	struct gpio_desc *gpiod;
-	bool output;
-	int value;
-};
-
 struct hdmi_audio {
 	bool enabled;
 	struct hdmi_audio_infoframe infoframe;
@@ -61,6 +53,8 @@ struct hdmi {
 	struct clk **hpd_clks;
 	struct clk **pwr_clks;
 
+	struct gpio_desc *hpd_gpiod;
+
 	struct hdmi_phy *phy;
 	struct device *phy_dev;
 
@@ -109,9 +103,6 @@ struct hdmi_platform_config {
 	/* clks that need to be on for screen pwr (ie pixel clk): */
 	const char **pwr_clk_names;
 	int pwr_clk_cnt;
-
-	/* gpio's: */
-	struct hdmi_gpio_data gpios[HDMI_MAX_NUM_GPIO];
 };
 
 struct hdmi_bridge {
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
index 75605ddac7c4b..bfa827b479897 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
@@ -60,48 +60,6 @@ static void msm_hdmi_phy_reset(struct hdmi *hdmi)
 	}
 }
 
-static int gpio_config(struct hdmi *hdmi, bool on)
-{
-	const struct hdmi_platform_config *config = hdmi->config;
-	int i;
-
-	if (on) {
-		for (i = 0; i < HDMI_MAX_NUM_GPIO; i++) {
-			struct hdmi_gpio_data gpio = config->gpios[i];
-
-			if (gpio.gpiod) {
-				if (gpio.output) {
-					gpiod_direction_output(gpio.gpiod,
-							       gpio.value);
-				} else {
-					gpiod_direction_input(gpio.gpiod);
-					gpiod_set_value_cansleep(gpio.gpiod,
-								 gpio.value);
-				}
-			}
-		}
-
-		DBG("gpio on");
-	} else {
-		for (i = 0; i < HDMI_MAX_NUM_GPIO; i++) {
-			struct hdmi_gpio_data gpio = config->gpios[i];
-
-			if (!gpio.gpiod)
-				continue;
-
-			if (gpio.output) {
-				int value = gpio.value ? 0 : 1;
-
-				gpiod_set_value_cansleep(gpio.gpiod, value);
-			}
-		}
-
-		DBG("gpio off");
-	}
-
-	return 0;
-}
-
 static void enable_hpd_clocks(struct hdmi *hdmi, bool enable)
 {
 	const struct hdmi_platform_config *config = hdmi->config;
@@ -154,11 +112,8 @@ int msm_hdmi_hpd_enable(struct drm_bridge *bridge)
 		goto fail;
 	}
 
-	ret = gpio_config(hdmi, true);
-	if (ret) {
-		DRM_DEV_ERROR(dev, "failed to configure GPIOs: %d\n", ret);
-		goto fail;
-	}
+	if (hdmi->hpd_gpiod)
+		gpiod_set_value_cansleep(hdmi->hpd_gpiod, 1);
 
 	pm_runtime_get_sync(dev);
 	enable_hpd_clocks(hdmi, true);
@@ -207,10 +162,6 @@ void msm_hdmi_hpd_disable(struct hdmi_bridge *hdmi_bridge)
 	enable_hpd_clocks(hdmi, false);
 	pm_runtime_put(dev);
 
-	ret = gpio_config(hdmi, false);
-	if (ret)
-		dev_warn(dev, "failed to unconfigure GPIOs: %d\n", ret);
-
 	ret = pinctrl_pm_select_sleep_state(dev);
 	if (ret)
 		dev_warn(dev, "pinctrl state chg failed: %d\n", ret);
@@ -269,10 +220,7 @@ static enum drm_connector_status detect_reg(struct hdmi *hdmi)
 #define HPD_GPIO_INDEX	2
 static enum drm_connector_status detect_gpio(struct hdmi *hdmi)
 {
-	const struct hdmi_platform_config *config = hdmi->config;
-	struct hdmi_gpio_data hpd_gpio = config->gpios[HPD_GPIO_INDEX];
-
-	return gpiod_get_value(hpd_gpio.gpiod) ?
+	return gpiod_get_value(hdmi->hpd_gpiod) ?
 			connector_status_connected :
 			connector_status_disconnected;
 }
@@ -282,8 +230,6 @@ enum drm_connector_status msm_hdmi_bridge_detect(
 {
 	struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
 	struct hdmi *hdmi = hdmi_bridge->hdmi;
-	const struct hdmi_platform_config *config = hdmi->config;
-	struct hdmi_gpio_data hpd_gpio = config->gpios[HPD_GPIO_INDEX];
 	enum drm_connector_status stat_gpio, stat_reg;
 	int retry = 20;
 
@@ -291,7 +237,7 @@ enum drm_connector_status msm_hdmi_bridge_detect(
 	 * some platforms may not have hpd gpio. Rely only on the status
 	 * provided by REG_HDMI_HPD_INT_STATUS in this case.
 	 */
-	if (!hpd_gpio.gpiod)
+	if (!hdmi->hpd_gpiod)
 		return detect_reg(hdmi);
 
 	do {
-- 
GitLab


From 1f88301794595ff4c28a1f1befe690e8dbac72a2 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 9 Jun 2022 15:23:43 +0300
Subject: [PATCH 1568/1731] drm/msm/hdmi: enable core-vcc/core-vdda-supply for
 8996 platform

DB820c makes use of core-vcc-supply and core-vdda-supply, however the
driver code doesn't support these regulators. Enable them for HDMI on
8996 platform.

Fixes: 0afbe59edd3f ("drm/msm/hdmi: Add basic HDMI support for msm8996")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/488857/
Link: https://lore.kernel.org/r/20220609122350.3157529-8-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/hdmi/hdmi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 6d79f1b910a51..4ec55616a2e5f 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -416,7 +416,7 @@ static struct hdmi_platform_config hdmi_tx_8994_config = {
 };
 
 static struct hdmi_platform_config hdmi_tx_8996_config = {
-		HDMI_CFG(pwr_reg, none),
+		HDMI_CFG(pwr_reg, 8x74),
 		HDMI_CFG(hpd_reg, none),
 		HDMI_CFG(pwr_clk, 8x74),
 		HDMI_CFG(hpd_clk, 8x74),
-- 
GitLab


From 53d9118f7d39f9ae8dc0555d7ae2186b4cf783e3 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 9 Jun 2022 15:23:44 +0300
Subject: [PATCH 1569/1731] drm/msm/hdmi: drop empty 'none' regulator lists

Several platform configs use empty 'none' regulator arrays. They are not
necessary, as the code will use corresponding _cnt field and skip the
array completely. Drop them now.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/488861/
Link: https://lore.kernel.org/r/20220609122350.3157529-9-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/hdmi/hdmi.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 4ec55616a2e5f..8f0fd2795748a 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -370,9 +370,6 @@ fail:
 	.item ## _names = item ##_names_ ## entry, \
 	.item ## _cnt   = ARRAY_SIZE(item ## _names_ ## entry)
 
-static const char *pwr_reg_names_none[] = {};
-static const char *hpd_reg_names_none[] = {};
-
 static struct hdmi_platform_config hdmi_tx_8660_config;
 
 static const char *hpd_reg_names_8960[] = {"core-vdda"};
@@ -409,7 +406,6 @@ static struct hdmi_platform_config hdmi_tx_8084_config = {
 
 static struct hdmi_platform_config hdmi_tx_8994_config = {
 		HDMI_CFG(pwr_reg, 8x74),
-		HDMI_CFG(hpd_reg, none),
 		HDMI_CFG(pwr_clk, 8x74),
 		HDMI_CFG(hpd_clk, 8x74),
 		.hpd_freq      = hpd_clk_freq_8x74,
@@ -417,7 +413,6 @@ static struct hdmi_platform_config hdmi_tx_8994_config = {
 
 static struct hdmi_platform_config hdmi_tx_8996_config = {
 		HDMI_CFG(pwr_reg, 8x74),
-		HDMI_CFG(hpd_reg, none),
 		HDMI_CFG(pwr_clk, 8x74),
 		HDMI_CFG(hpd_clk, 8x74),
 		.hpd_freq      = hpd_clk_freq_8x74,
-- 
GitLab


From b45aff9688e7d0e2dc478b43125d6901849a16b6 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 9 Jun 2022 15:23:45 +0300
Subject: [PATCH 1570/1731] drm/msm/hdmi: drop hpd_regs usage on 8x74/8084

The MSM HDMI driver has support for hpd_regs on 8x74/8084: supply
regulators that are to be enabled for HPD to work. Currently these
regulators contain the hpd_gdsc, which was replaced by the power-domains
support and hpd-5v/hpd-5v-en, which are not used by the chip itself.
They power up the ESD bridge.
However it is a separate device which should be represented separately
in the device tree.
None of upstreamed devices support these properties. Thus drop support
for them from the HDMI driver.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/488860/
Link: https://lore.kernel.org/r/20220609122350.3157529-10-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/hdmi/hdmi.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 8f0fd2795748a..48cd6b9a75653 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -381,24 +381,19 @@ static struct hdmi_platform_config hdmi_tx_8960_config = {
 };
 
 static const char *pwr_reg_names_8x74[] = {"core-vdda", "core-vcc"};
-static const char *hpd_reg_names_8x74[] = {"hpd-gdsc", "hpd-5v"};
 static const char *pwr_clk_names_8x74[] = {"extp", "alt_iface"};
 static const char *hpd_clk_names_8x74[] = {"iface", "core", "mdp_core"};
 static unsigned long hpd_clk_freq_8x74[] = {0, 19200000, 0};
 
 static struct hdmi_platform_config hdmi_tx_8974_config = {
 		HDMI_CFG(pwr_reg, 8x74),
-		HDMI_CFG(hpd_reg, 8x74),
 		HDMI_CFG(pwr_clk, 8x74),
 		HDMI_CFG(hpd_clk, 8x74),
 		.hpd_freq      = hpd_clk_freq_8x74,
 };
 
-static const char *hpd_reg_names_8084[] = {"hpd-gdsc", "hpd-5v", "hpd-5v-en"};
-
 static struct hdmi_platform_config hdmi_tx_8084_config = {
 		HDMI_CFG(pwr_reg, 8x74),
-		HDMI_CFG(hpd_reg, 8084),
 		HDMI_CFG(pwr_clk, 8x74),
 		HDMI_CFG(hpd_clk, 8x74),
 		.hpd_freq      = hpd_clk_freq_8x74,
-- 
GitLab


From 9edaba8751ca4e218d06bfeb002ef27c34057e18 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 9 Jun 2022 15:23:46 +0300
Subject: [PATCH 1571/1731] drm/msm/hdmi: merge platform config for
 8974/8084/8994/8996

Since there is no more difference between the HDMI platform data
between MSM8974/APQ8084/MSM8994/MSM8996, merge these configs into a
single entry.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/488868/
Link: https://lore.kernel.org/r/20220609122350.3157529-11-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/hdmi/hdmi.c | 27 +++------------------------
 1 file changed, 3 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 48cd6b9a75653..0f1c63f685699 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -392,27 +392,6 @@ static struct hdmi_platform_config hdmi_tx_8974_config = {
 		.hpd_freq      = hpd_clk_freq_8x74,
 };
 
-static struct hdmi_platform_config hdmi_tx_8084_config = {
-		HDMI_CFG(pwr_reg, 8x74),
-		HDMI_CFG(pwr_clk, 8x74),
-		HDMI_CFG(hpd_clk, 8x74),
-		.hpd_freq      = hpd_clk_freq_8x74,
-};
-
-static struct hdmi_platform_config hdmi_tx_8994_config = {
-		HDMI_CFG(pwr_reg, 8x74),
-		HDMI_CFG(pwr_clk, 8x74),
-		HDMI_CFG(hpd_clk, 8x74),
-		.hpd_freq      = hpd_clk_freq_8x74,
-};
-
-static struct hdmi_platform_config hdmi_tx_8996_config = {
-		HDMI_CFG(pwr_reg, 8x74),
-		HDMI_CFG(pwr_clk, 8x74),
-		HDMI_CFG(hpd_clk, 8x74),
-		.hpd_freq      = hpd_clk_freq_8x74,
-};
-
 /*
  * HDMI audio codec callbacks
  */
@@ -583,9 +562,9 @@ static int msm_hdmi_dev_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id msm_hdmi_dt_match[] = {
-	{ .compatible = "qcom,hdmi-tx-8996", .data = &hdmi_tx_8996_config },
-	{ .compatible = "qcom,hdmi-tx-8994", .data = &hdmi_tx_8994_config },
-	{ .compatible = "qcom,hdmi-tx-8084", .data = &hdmi_tx_8084_config },
+	{ .compatible = "qcom,hdmi-tx-8996", .data = &hdmi_tx_8974_config },
+	{ .compatible = "qcom,hdmi-tx-8994", .data = &hdmi_tx_8974_config },
+	{ .compatible = "qcom,hdmi-tx-8084", .data = &hdmi_tx_8974_config },
 	{ .compatible = "qcom,hdmi-tx-8974", .data = &hdmi_tx_8974_config },
 	{ .compatible = "qcom,hdmi-tx-8960", .data = &hdmi_tx_8960_config },
 	{ .compatible = "qcom,hdmi-tx-8660", .data = &hdmi_tx_8660_config },
-- 
GitLab


From ac1c2787bb297ccc0ae4d6071b3b21103145fe98 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 9 Jun 2022 15:23:47 +0300
Subject: [PATCH 1572/1731] drm/msm/hdmi: reuse MSM8960's config for MSM8660

MSM8660 requires the same set of clocks and regulators as MSM8960. Reuse
MSM8960's config for the MSM8660 (8x60).

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/488864/
Link: https://lore.kernel.org/r/20220609122350.3157529-12-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/hdmi/hdmi.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 0f1c63f685699..6acc17e0efc14 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -370,8 +370,6 @@ fail:
 	.item ## _names = item ##_names_ ## entry, \
 	.item ## _cnt   = ARRAY_SIZE(item ## _names_ ## entry)
 
-static struct hdmi_platform_config hdmi_tx_8660_config;
-
 static const char *hpd_reg_names_8960[] = {"core-vdda"};
 static const char *hpd_clk_names_8960[] = {"core", "master_iface", "slave_iface"};
 
@@ -567,7 +565,7 @@ static const struct of_device_id msm_hdmi_dt_match[] = {
 	{ .compatible = "qcom,hdmi-tx-8084", .data = &hdmi_tx_8974_config },
 	{ .compatible = "qcom,hdmi-tx-8974", .data = &hdmi_tx_8974_config },
 	{ .compatible = "qcom,hdmi-tx-8960", .data = &hdmi_tx_8960_config },
-	{ .compatible = "qcom,hdmi-tx-8660", .data = &hdmi_tx_8660_config },
+	{ .compatible = "qcom,hdmi-tx-8660", .data = &hdmi_tx_8960_config },
 	{}
 };
 
-- 
GitLab


From 0f390c8ca0e18149ec77967cedf12aac8284b48d Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 9 Jun 2022 15:23:48 +0300
Subject: [PATCH 1573/1731] drm/msm/hdmi-phy: populate 8x60 HDMI PHY
 requirements

Declare that 8x60 HDMI PHY uses the core-vdda regulator and slave_iface
clock (this is the same config as is used by the 8960).

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/488863/
Link: https://lore.kernel.org/r/20220609122350.3157529-13-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c
index 95f2928cb2cb0..1d97640d8c24a 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c
@@ -122,8 +122,20 @@ static void hdmi_phy_8x60_powerdown(struct hdmi_phy *phy)
 		       HDMI_8x60_PHY_REG2_PD_DESER);
 }
 
+static const char * const hdmi_phy_8x60_reg_names[] = {
+	"core-vdda",
+};
+
+static const char * const hdmi_phy_8x60_clk_names[] = {
+	"slave_iface",
+};
+
 const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg = {
 	.type = MSM_HDMI_PHY_8x60,
 	.powerup = hdmi_phy_8x60_powerup,
 	.powerdown = hdmi_phy_8x60_powerdown,
+	.reg_names = hdmi_phy_8x60_reg_names,
+	.num_regs = ARRAY_SIZE(hdmi_phy_8x60_reg_names),
+	.clk_names = hdmi_phy_8x60_clk_names,
+	.num_clks = ARRAY_SIZE(hdmi_phy_8x60_clk_names),
 };
-- 
GitLab


From 089008b698f8c4a42e5e73b0a5628509b608b8da Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 16 Jun 2022 11:50:54 +0300
Subject: [PATCH 1574/1731] drm/msm/hdmi: drop empty bridge callbacks

Drop empty callbacks msm_hdmi_bridge_enable() and
msm_hdmi_bridge_disable().

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/489707/
Link: https://lore.kernel.org/r/20220616085054.432317-1-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
index 97c24010c4d10..d569f0c6cab7d 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
@@ -159,14 +159,6 @@ static void msm_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
 		msm_hdmi_hdcp_on(hdmi->hdcp_ctrl);
 }
 
-static void msm_hdmi_bridge_enable(struct drm_bridge *bridge)
-{
-}
-
-static void msm_hdmi_bridge_disable(struct drm_bridge *bridge)
-{
-}
-
 static void msm_hdmi_bridge_post_disable(struct drm_bridge *bridge)
 {
 	struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
@@ -306,8 +298,6 @@ static enum drm_mode_status msm_hdmi_bridge_mode_valid(struct drm_bridge *bridge
 
 static const struct drm_bridge_funcs msm_hdmi_bridge_funcs = {
 		.pre_enable = msm_hdmi_bridge_pre_enable,
-		.enable = msm_hdmi_bridge_enable,
-		.disable = msm_hdmi_bridge_disable,
 		.post_disable = msm_hdmi_bridge_post_disable,
 		.mode_set = msm_hdmi_bridge_mode_set,
 		.mode_valid = msm_hdmi_bridge_mode_valid,
-- 
GitLab


From a7977d5cd9dbf4c9e8706d9e254655ed422859f0 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 16 Jun 2022 11:50:57 +0300
Subject: [PATCH 1575/1731] drm/msm/hdmi: support attaching the "next" bridge

There might be a chain of bridges attached to the HDMI node
(including but not limited to the display-connector bridge). Add support
for attaching them right to the HDMI bridge chain.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/489709/
Link: https://lore.kernel.org/r/20220616085057.432353-1-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/hdmi/hdmi.c | 14 ++++++++++++++
 drivers/gpu/drm/msm/hdmi/hdmi.h |  2 ++
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 6acc17e0efc14..93fe61b869670 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -9,6 +9,7 @@
 #include <linux/of_gpio.h>
 
 #include <drm/drm_bridge_connector.h>
+#include <drm/drm_of.h>
 
 #include <sound/hdmi-codec.h>
 #include "hdmi.h"
@@ -133,6 +134,10 @@ static struct hdmi *msm_hdmi_init(struct platform_device *pdev)
 	hdmi->config = config;
 	spin_lock_init(&hdmi->reg_lock);
 
+	ret = drm_of_find_panel_or_bridge(pdev->dev.of_node, 1, 0, NULL, &hdmi->next_bridge);
+	if (ret && ret != -ENODEV)
+		goto fail;
+
 	hdmi->mmio = msm_ioremap(pdev, config->mmio_name);
 	if (IS_ERR(hdmi->mmio)) {
 		ret = PTR_ERR(hdmi->mmio);
@@ -308,6 +313,15 @@ int msm_hdmi_modeset_init(struct hdmi *hdmi,
 		goto fail;
 	}
 
+	if (hdmi->next_bridge) {
+		ret = drm_bridge_attach(hdmi->encoder, hdmi->next_bridge, hdmi->bridge,
+					DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+		if (ret) {
+			DRM_DEV_ERROR(dev->dev, "failed to attach next HDMI bridge: %d\n", ret);
+			goto fail;
+		}
+	}
+
 	hdmi->connector = drm_bridge_connector_init(hdmi->dev, encoder);
 	if (IS_ERR(hdmi->connector)) {
 		ret = PTR_ERR(hdmi->connector);
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index a6c88d157bc3a..04a74381aaf7c 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -62,6 +62,8 @@ struct hdmi {
 	struct drm_connector *connector;
 	struct drm_bridge *bridge;
 
+	struct drm_bridge *next_bridge;
+
 	/* the encoder we are hooked to (outside of hdmi block) */
 	struct drm_encoder *encoder;
 
-- 
GitLab


From a143890fefa5c519772cace8be27ca1bd1792e95 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 5 May 2022 16:50:07 +0300
Subject: [PATCH 1576/1731] drm/msm/mdp4: move iommu_domain_alloc() call close
 to its usage

Move iommu_domain_alloc() in front of adress space/IOMMU initialization.
This allows us to drop it from struct mdp4_cfg_platform which
remained from the pre-DT days.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/485049/
Link: https://lore.kernel.org/r/20220505135008.1351533-2-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 8 ++++----
 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h | 1 -
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
index 17cb1fc783795..b55b4a4067be9 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
@@ -390,6 +390,7 @@ static int mdp4_kms_init(struct drm_device *dev)
 	struct msm_drm_private *priv = dev->dev_private;
 	struct mdp4_kms *mdp4_kms;
 	struct msm_kms *kms = NULL;
+	struct iommu_domain *iommu;
 	struct msm_gem_address_space *aspace;
 	int irq, ret;
 	u32 major, minor;
@@ -497,9 +498,9 @@ static int mdp4_kms_init(struct drm_device *dev)
 	mdp4_disable(mdp4_kms);
 	mdelay(16);
 
-	if (config->iommu) {
-		struct msm_mmu *mmu = msm_iommu_new(&pdev->dev,
-			config->iommu);
+	iommu = iommu_domain_alloc(pdev->dev.bus);
+	if (iommu) {
+		struct msm_mmu *mmu = msm_iommu_new(&pdev->dev, iommu);
 
 		aspace  = msm_gem_address_space_create(mmu,
 			"mdp4", 0x1000, 0x100000000 - 0x1000);
@@ -559,7 +560,6 @@ static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev)
 
 	/* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */
 	config.max_clk = 266667000;
-	config.iommu = iommu_domain_alloc(&platform_bus_type);
 
 	return &config;
 }
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h
index e8ee92ab79566..7cc549b6a82b5 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h
@@ -44,7 +44,6 @@ struct mdp4_kms {
 
 /* platform config data (ie. from DT, or pdata) */
 struct mdp4_platform_config {
-	struct iommu_domain *iommu;
 	uint32_t max_clk;
 };
 
-- 
GitLab


From 97b10e15df73249a6e5dfe36d07322110748cf67 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 5 May 2022 16:50:08 +0300
Subject: [PATCH 1577/1731] drm/msm/mdp4: get rid of struct
 mdp4_platform_config

Struct mdp4_platform_config is a relict from the DT-conversion time.
Move the max_clk field to the mdp4_kms_init(), the place where it is
used and drop the struct mdp4_platform_config and the mdp4_get_config()
function.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/485050/
Link: https://lore.kernel.org/r/20220505135008.1351533-3-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 21 ++++++---------------
 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h |  5 -----
 2 files changed, 6 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
index b55b4a4067be9..964573d26d261 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
@@ -13,8 +13,6 @@
 #include "msm_mmu.h"
 #include "mdp4_kms.h"
 
-static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev);
-
 static int mdp4_hw_init(struct msm_kms *kms)
 {
 	struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
@@ -386,7 +384,6 @@ static void read_mdp_hw_revision(struct mdp4_kms *mdp4_kms,
 static int mdp4_kms_init(struct drm_device *dev)
 {
 	struct platform_device *pdev = to_platform_device(dev->dev);
-	struct mdp4_platform_config *config = mdp4_get_config(pdev);
 	struct msm_drm_private *priv = dev->dev_private;
 	struct mdp4_kms *mdp4_kms;
 	struct msm_kms *kms = NULL;
@@ -394,6 +391,10 @@ static int mdp4_kms_init(struct drm_device *dev)
 	struct msm_gem_address_space *aspace;
 	int irq, ret;
 	u32 major, minor;
+	unsigned long max_clk;
+
+	/* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */
+	max_clk = 266667000;
 
 	mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
 	if (!mdp4_kms) {
@@ -461,7 +462,7 @@ static int mdp4_kms_init(struct drm_device *dev)
 		goto fail;
 	}
 
-	clk_set_rate(mdp4_kms->clk, config->max_clk);
+	clk_set_rate(mdp4_kms->clk, max_clk);
 
 	read_mdp_hw_revision(mdp4_kms, &major, &minor);
 
@@ -481,7 +482,7 @@ static int mdp4_kms_init(struct drm_device *dev)
 			ret = PTR_ERR(mdp4_kms->lut_clk);
 			goto fail;
 		}
-		clk_set_rate(mdp4_kms->lut_clk, config->max_clk);
+		clk_set_rate(mdp4_kms->lut_clk, max_clk);
 	}
 
 	pm_runtime_enable(dev->dev);
@@ -554,16 +555,6 @@ fail:
 	return ret;
 }
 
-static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev)
-{
-	static struct mdp4_platform_config config = {};
-
-	/* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */
-	config.max_clk = 266667000;
-
-	return &config;
-}
-
 static const struct dev_pm_ops mdp4_pm_ops = {
 	.prepare = msm_pm_prepare,
 	.complete = msm_pm_complete,
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h
index 7cc549b6a82b5..01179e764a294 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h
@@ -42,11 +42,6 @@ struct mdp4_kms {
 };
 #define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)
 
-/* platform config data (ie. from DT, or pdata) */
-struct mdp4_platform_config {
-	uint32_t max_clk;
-};
-
 static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
 {
 	msm_writel(data, mdp4_kms->mmio + reg);
-- 
GitLab


From eeda2bc4fcd9f544b668efc6489ab165dc0d607e Mon Sep 17 00:00:00 2001
From: Vladimir Lypak <vladimir.lypak@gmail.com>
Date: Sat, 11 Jun 2022 00:53:02 +0200
Subject: [PATCH 1578/1731] drm/msm/mdp5: Add perf data for MDP v1.16

Add the perf data for the mdp found in msm8953.

Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/489153/
Link: https://lore.kernel.org/r/20220610225304.267508-1-luca@z3ntu.xyz
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
index 1bf9ff5dbabc9..b17f868ffca83 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
@@ -837,6 +837,11 @@ static const struct mdp5_cfg_hw msm8x53_config = {
 			[2] = INTF_DSI,
 		},
 	},
+	.perf = {
+		.ab_inefficiency = 100,
+		.ib_inefficiency = 200,
+		.clk_inefficiency = 105
+	},
 	.max_clk = 400000000,
 };
 
-- 
GitLab


From fca5ad26b7d8390f474d886a0778d4f9266c6662 Mon Sep 17 00:00:00 2001
From: Kalyan Thota <quic_kalyant@quicinc.com>
Date: Tue, 21 Jun 2022 02:06:26 -0700
Subject: [PATCH 1579/1731] drm/msm/disp/dpu1: add dspp support for sc7280

Add destination side post processing hw block support in sc7280.

This hwblock enablement is necessary to support color features
like CT Matix (Ex: Night Light feature)

Signed-off-by: Kalyan Thota <quic_kalyant@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/490382/
Link: https://lore.kernel.org/r/1655802387-15275-1-git-send-email-quic_kalyant@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index c7d46cd8c35e1..0239a811d5ecb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1015,7 +1015,7 @@ static const struct dpu_lm_cfg sm8150_lm[] = {
 
 static const struct dpu_lm_cfg sc7280_lm[] = {
 	LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
-		&sc7180_lm_sblk, PINGPONG_0, 0, 0),
+		&sc7180_lm_sblk, PINGPONG_0, 0, DSPP_0),
 	LM_BLK("lm_2", LM_2, 0x46000, MIXER_SC7180_MASK,
 		&sc7180_lm_sblk, PINGPONG_2, LM_3, 0),
 	LM_BLK("lm_3", LM_3, 0x47000, MIXER_SC7180_MASK,
@@ -1884,6 +1884,8 @@ static const struct dpu_mdss_cfg sc7280_dpu_cfg = {
 	.ctl = sc7280_ctl,
 	.sspp_count = ARRAY_SIZE(sc7280_sspp),
 	.sspp = sc7280_sspp,
+	.dspp_count = ARRAY_SIZE(sc7180_dspp),
+	.dspp = sc7180_dspp,
 	.mixer_count = ARRAY_SIZE(sc7280_lm),
 	.mixer = sc7280_lm,
 	.pingpong_count = ARRAY_SIZE(sc7280_pp),
-- 
GitLab


From 6867c9aff860b23ca5ffa6c427f0fbb7ccf3ac6b Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Mon, 13 Jun 2022 13:49:10 -0700
Subject: [PATCH 1580/1731] drm/msm: Make msm_gem_free_object() static

Misc small cleanup I noticed.  Not called from another object file since
commit 3c9edd9c85f5 ("drm/msm: Introduce GEM object funcs")

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/489362/
Link: https://lore.kernel.org/r/20220613204910.2651747-1-robdclark@gmail.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/msm_gem.c | 2 +-
 drivers/gpu/drm/msm/msm_gem.h | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 7f92231785a0e..5514aca98dd02 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -1004,7 +1004,7 @@ void msm_gem_describe_objects(struct list_head *list, struct seq_file *m)
 #endif
 
 /* don't call directly!  Use drm_gem_object_put() */
-void msm_gem_free_object(struct drm_gem_object *obj)
+static void msm_gem_free_object(struct drm_gem_object *obj)
 {
 	struct msm_gem_object *msm_obj = to_msm_bo(obj);
 	struct drm_device *dev = obj->dev;
diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h
index 6b7d5bb3b575f..d608339c1643a 100644
--- a/drivers/gpu/drm/msm/msm_gem.h
+++ b/drivers/gpu/drm/msm/msm_gem.h
@@ -175,7 +175,6 @@ void msm_gem_active_get(struct drm_gem_object *obj, struct msm_gpu *gpu);
 void msm_gem_active_put(struct drm_gem_object *obj);
 int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout);
 int msm_gem_cpu_fini(struct drm_gem_object *obj);
-void msm_gem_free_object(struct drm_gem_object *obj);
 int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
 		uint32_t size, uint32_t flags, uint32_t *handle, char *name);
 struct drm_gem_object *msm_gem_new(struct drm_device *dev,
-- 
GitLab


From 1981c35bf7533d70f295b184bbb638d280fe2f36 Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Thu, 9 Jun 2022 10:42:11 -0700
Subject: [PATCH 1581/1731] drm: Add DRM_GEM_FOPS

The DEFINE_DRM_GEM_FOPS() helper is a bit limiting if a driver wants to
provide additional file ops, like show_fdinfo().

v2: Split out DRM_GEM_FOPS instead of making DEFINE_DRM_GEM_FOPS
    varardic
v3: nits

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
Patchwork: https://patchwork.freedesktop.org/patch/488904/
Link: https://lore.kernel.org/r/20220609174213.2265938-1-robdclark@gmail.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 include/drm/drm_gem.h | 26 ++++++++++++++++++--------
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/include/drm/drm_gem.h b/include/drm/drm_gem.h
index 9d7c61a122dc4..87cffc9efa855 100644
--- a/include/drm/drm_gem.h
+++ b/include/drm/drm_gem.h
@@ -314,6 +314,23 @@ struct drm_gem_object {
 	const struct drm_gem_object_funcs *funcs;
 };
 
+/**
+ * DRM_GEM_FOPS - Default drm GEM file operations
+ *
+ * This macro provides a shorthand for setting the GEM file ops in the
+ * &file_operations structure.  If all you need are the default ops, use
+ * DEFINE_DRM_GEM_FOPS instead.
+ */
+#define DRM_GEM_FOPS \
+	.open		= drm_open,\
+	.release	= drm_release,\
+	.unlocked_ioctl	= drm_ioctl,\
+	.compat_ioctl	= drm_compat_ioctl,\
+	.poll		= drm_poll,\
+	.read		= drm_read,\
+	.llseek		= noop_llseek,\
+	.mmap		= drm_gem_mmap
+
 /**
  * DEFINE_DRM_GEM_FOPS() - macro to generate file operations for GEM drivers
  * @name: name for the generated structure
@@ -330,14 +347,7 @@ struct drm_gem_object {
 #define DEFINE_DRM_GEM_FOPS(name) \
 	static const struct file_operations name = {\
 		.owner		= THIS_MODULE,\
-		.open		= drm_open,\
-		.release	= drm_release,\
-		.unlocked_ioctl	= drm_ioctl,\
-		.compat_ioctl	= drm_compat_ioctl,\
-		.poll		= drm_poll,\
-		.read		= drm_read,\
-		.llseek		= noop_llseek,\
-		.mmap		= drm_gem_mmap,\
+		DRM_GEM_FOPS,\
 	}
 
 void drm_gem_object_release(struct drm_gem_object *obj);
-- 
GitLab


From cfebe3fd599634540960ec37e3a6c2eb8b5bed2f Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Thu, 9 Jun 2022 10:42:12 -0700
Subject: [PATCH 1582/1731] drm/msm: Expose client engine utilization via
 fdinfo

Similar to AMD commit
874442541133 ("drm/amdgpu: Add show_fdinfo() interface"), using the
infrastructure added in previous patches, we add basic client info
and GPU engine utilisation for msm.

Example output:

	# cat /proc/`pgrep glmark2`/fdinfo/6
	pos:	0
	flags:	02400002
	mnt_id:	21
	ino:	162
	drm-driver:	msm
	drm-client-id:	7
	drm-engine-gpu:	1734371319 ns
	drm-cycles-gpu:	1153645024
	drm-maxfreq-gpu:	800000000 Hz

See also: https://patchwork.freedesktop.org/patch/468505/

v2: Add dev-maxfreq-$engine and update drm-usage-stats.rst
v3: spelling and compiler warning

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Patchwork: https://patchwork.freedesktop.org/patch/488906/
Link: https://lore.kernel.org/r/20220609174213.2265938-2-robdclark@gmail.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 Documentation/gpu/drm-usage-stats.rst | 21 +++++++++++++++++++++
 drivers/gpu/drm/msm/msm_drv.c         | 19 ++++++++++++++++++-
 drivers/gpu/drm/msm/msm_gpu.c         | 21 +++++++++++++++++++--
 drivers/gpu/drm/msm/msm_gpu.h         | 19 +++++++++++++++++++
 4 files changed, 77 insertions(+), 3 deletions(-)

diff --git a/Documentation/gpu/drm-usage-stats.rst b/Documentation/gpu/drm-usage-stats.rst
index 6c9f166a8d6fa..92c5117368d7f 100644
--- a/Documentation/gpu/drm-usage-stats.rst
+++ b/Documentation/gpu/drm-usage-stats.rst
@@ -105,6 +105,27 @@ object belong to this client, in the respective memory region.
 Default unit shall be bytes with optional unit specifiers of 'KiB' or 'MiB'
 indicating kibi- or mebi-bytes.
 
+- drm-cycles-<str> <uint>
+
+Engine identifier string must be the same as the one specified in the
+drm-engine-<str> tag and shall contain the number of busy cycles for the given
+engine.
+
+Values are not required to be constantly monotonic if it makes the driver
+implementation easier, but are required to catch up with the previously reported
+larger value within a reasonable period. Upon observing a value lower than what
+was previously read, userspace is expected to stay with that larger previous
+value until a monotonic update is seen.
+
+- drm-maxfreq-<str> <uint> [Hz|MHz|KHz]
+
+Engine identifier string must be the same as the one specified in the
+drm-engine-<str> tag and shall contain the maximum frequency for the given
+engine.  Taken together with drm-cycles-<str>, this can be used to calculate
+percentage utilization of the engine, whereas drm-engine-<str> only reflects
+time active without considering what frequency the engine is operating as a
+percentage of it's maximum frequency.
+
 ===============================
 Driver specific implementations
 ===============================
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 14ab9a627d8b0..57a66093e6711 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -948,7 +948,24 @@ static const struct drm_ioctl_desc msm_ioctls[] = {
 	DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
 };
 
-DEFINE_DRM_GEM_FOPS(fops);
+static void msm_fop_show_fdinfo(struct seq_file *m, struct file *f)
+{
+	struct drm_file *file = f->private_data;
+	struct drm_device *dev = file->minor->dev;
+	struct msm_drm_private *priv = dev->dev_private;
+	struct drm_printer p = drm_seq_file_printer(m);
+
+	if (!priv->gpu)
+		return;
+
+	msm_gpu_show_fdinfo(priv->gpu, file->driver_priv, &p);
+}
+
+static const struct file_operations fops = {
+	.owner = THIS_MODULE,
+	DRM_GEM_FOPS,
+	.show_fdinfo = msm_fop_show_fdinfo,
+};
 
 static const struct drm_driver msm_driver = {
 	.driver_features    = DRIVER_GEM |
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index c8cd9bfa3eebd..484346daa05f3 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -4,6 +4,8 @@
  * Author: Rob Clark <robdclark@gmail.com>
  */
 
+#include "drm/drm_drv.h"
+
 #include "msm_gpu.h"
 #include "msm_gem.h"
 #include "msm_mmu.h"
@@ -146,6 +148,16 @@ int msm_gpu_pm_suspend(struct msm_gpu *gpu)
 	return 0;
 }
 
+void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_file_private *ctx,
+			 struct drm_printer *p)
+{
+	drm_printf(p, "drm-driver:\t%s\n", gpu->dev->driver->name);
+	drm_printf(p, "drm-client-id:\t%u\n", ctx->seqno);
+	drm_printf(p, "drm-engine-gpu:\t%llu ns\n", ctx->elapsed_ns);
+	drm_printf(p, "drm-cycles-gpu:\t%llu\n", ctx->cycles);
+	drm_printf(p, "drm-maxfreq-gpu:\t%u Hz\n", gpu->fast_rate);
+}
+
 int msm_gpu_hw_init(struct msm_gpu *gpu)
 {
 	int ret;
@@ -634,7 +646,7 @@ static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
 {
 	int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
 	volatile struct msm_gpu_submit_stats *stats;
-	u64 elapsed, clock = 0;
+	u64 elapsed, clock = 0, cycles;
 	unsigned long flags;
 
 	stats = &ring->memptrs->stats[index];
@@ -642,12 +654,17 @@ static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
 	elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000;
 	do_div(elapsed, 192);
 
+	cycles = stats->cpcycles_end - stats->cpcycles_start;
+
 	/* Calculate the clock frequency from the number of CP cycles */
 	if (elapsed) {
-		clock = (stats->cpcycles_end - stats->cpcycles_start) * 1000;
+		clock = cycles * 1000;
 		do_div(clock, elapsed);
 	}
 
+	submit->queue->ctx->elapsed_ns += elapsed;
+	submit->queue->ctx->cycles     += cycles;
+
 	trace_msm_gpu_submit_retired(submit, elapsed, clock,
 		stats->alwayson_start, stats->alwayson_end);
 
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 6def008830463..4911943ba53b2 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -361,6 +361,22 @@ struct msm_file_private {
 	/** cmdline: Overridden task cmdline, see MSM_PARAM_CMDLINE */
 	char *cmdline;
 
+	/**
+	 * elapsed:
+	 *
+	 * The total (cumulative) elapsed time GPU was busy with rendering
+	 * from this context in ns.
+	 */
+	uint64_t elapsed_ns;
+
+	/**
+	 * cycles:
+	 *
+	 * The total (cumulative) GPU cycles elapsed attributed to this
+	 * context.
+	 */
+	uint64_t cycles;
+
 	/**
 	 * entities:
 	 *
@@ -544,6 +560,9 @@ static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val)
 int msm_gpu_pm_suspend(struct msm_gpu *gpu);
 int msm_gpu_pm_resume(struct msm_gpu *gpu);
 
+void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_file_private *ctx,
+			 struct drm_printer *p);
+
 int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx);
 struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx,
 		u32 id);
-- 
GitLab


From 4400c3a1d48f7f7863ca65d24f99ad295b37726c Mon Sep 17 00:00:00 2001
From: Wan Jiabing <wanjiabing@vivo.com>
Date: Tue, 26 Apr 2022 21:21:26 +0800
Subject: [PATCH 1583/1731] drm/msm: Use div64_ul instead of do_div

Fix following coccicheck warning:
drivers/gpu/drm/msm/msm_gpu_devfreq.c:72:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead.

Use div64_ul instead of do_div to avoid a possible truncation.

Signed-off-by: Wan Jiabing <wanjiabing@vivo.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Patchwork: https://patchwork.freedesktop.org/patch/483499/
Link: https://lore.kernel.org/r/20220426132126.686447-1-wanjiabing@vivo.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/msm_gpu_devfreq.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c
index d2539ca78c296..c2ea978c89218 100644
--- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c
+++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c
@@ -69,7 +69,7 @@ static void get_raw_dev_status(struct msm_gpu *gpu,
 	df->time = time;
 
 	busy_time *= USEC_PER_SEC;
-	do_div(busy_time, sample_rate);
+	busy_time = div64_ul(busy_time, sample_rate);
 	if (WARN_ON(busy_time > ~0LU))
 		busy_time = ~0LU;
 
-- 
GitLab


From 2311720a0182756f175fbf4afc1fb76ac487b587 Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Wed, 15 Jun 2022 09:24:35 -0700
Subject: [PATCH 1584/1731] drm/msm: Fix fence rollover issue

And while we are at it, let's start the fence counter close to the
rollover point so that if issues slip in, they are more obvious.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Fixes: fde5de6cb461 ("drm/msm: move fence code to it's own file")
Fixes: 5f3aee4ceb5b ("drm/msm: Handle fence rollover")
Patchwork: https://patchwork.freedesktop.org/patch/489619/
Link: https://lore.kernel.org/r/20220615162435.3011793-1-robdclark@gmail.com
[DB: fixed the conflict while applying the patch]
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/msm_fence.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/msm_fence.c b/drivers/gpu/drm/msm/msm_fence.c
index 38e3323bc2324..a47e5837c528f 100644
--- a/drivers/gpu/drm/msm/msm_fence.c
+++ b/drivers/gpu/drm/msm/msm_fence.c
@@ -28,6 +28,14 @@ msm_fence_context_alloc(struct drm_device *dev, volatile uint32_t *fenceptr,
 	fctx->fenceptr = fenceptr;
 	spin_lock_init(&fctx->spinlock);
 
+	/*
+	 * Start out close to the 32b fence rollover point, so we can
+	 * catch bugs with fence comparisons.
+	 */
+	fctx->last_fence = 0xffffff00;
+	fctx->completed_fence = fctx->last_fence;
+	*fctx->fenceptr = fctx->last_fence;
+
 	return fctx;
 }
 
@@ -52,7 +60,8 @@ void msm_update_fence(struct msm_fence_context *fctx, uint32_t fence)
 	unsigned long flags;
 
 	spin_lock_irqsave(&fctx->spinlock, flags);
-	fctx->completed_fence = max(fence, fctx->completed_fence);
+	if (fence_after(fence, fctx->completed_fence))
+		fctx->completed_fence = fence;
 	spin_unlock_irqrestore(&fctx->spinlock, flags);
 }
 
-- 
GitLab


From b8e629b05f5d23f9649c901bef09fab8b0c2e4b9 Mon Sep 17 00:00:00 2001
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Date: Sun, 3 Jul 2022 10:36:24 +0300
Subject: [PATCH 1585/1731] selftests: forwarding: fix flood_unicast_test when
 h2 supports IFF_UNICAST_FLT

As mentioned in the blamed commit, flood_unicast_test() works by
checking the match count on a tc filter placed on the receiving
interface.

But the second host interface (host2_if) has no interest in receiving a
packet with MAC DA de:ad:be:ef:13:37, so its RX filter drops it even
before the ingress tc filter gets to be executed. So we will incorrectly
get the message "Packet was not flooded when should", when in fact, the
packet was flooded as expected but dropped due to an unrelated reason,
at some other layer on the receiving side.

Force h2 to accept this packet by temporarily placing it in promiscuous
mode. Alternatively we could either deliver to its MAC address or use
tcpdump_start, but this has the fewest complications.

This fixes the "flooding" test from bridge_vlan_aware.sh and
bridge_vlan_unaware.sh, which calls flood_test from the lib.

Fixes: 236dd50bf67a ("selftests: forwarding: Add a test for flooded traffic")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Tested-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
 tools/testing/selftests/net/forwarding/lib.sh | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tools/testing/selftests/net/forwarding/lib.sh b/tools/testing/selftests/net/forwarding/lib.sh
index 37ae49d478536..4e69497f021f3 100755
--- a/tools/testing/selftests/net/forwarding/lib.sh
+++ b/tools/testing/selftests/net/forwarding/lib.sh
@@ -1306,6 +1306,7 @@ flood_test_do()
 
 	# Add an ACL on `host2_if` which will tell us whether the packet
 	# was flooded to it or not.
+	ip link set $host2_if promisc on
 	tc qdisc add dev $host2_if ingress
 	tc filter add dev $host2_if ingress protocol ip pref 1 handle 101 \
 		flower dst_mac $mac action drop
@@ -1323,6 +1324,7 @@ flood_test_do()
 
 	tc filter del dev $host2_if ingress protocol ip pref 1 handle 101 flower
 	tc qdisc del dev $host2_if ingress
+	ip link set $host2_if promisc off
 
 	return $err
 }
-- 
GitLab


From 1a635d3e1c80626237fdae47a5545b6655d8d81c Mon Sep 17 00:00:00 2001
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Date: Sun, 3 Jul 2022 10:36:25 +0300
Subject: [PATCH 1586/1731] selftests: forwarding: fix learning_test when h1
 supports IFF_UNICAST_FLT

The first host interface has by default no interest in receiving packets
MAC DA de:ad:be:ef:13:37, so it might drop them before they hit the tc
filter and this might confuse the selftest.

Enable promiscuous mode such that the filter properly counts received
packets.

Fixes: d4deb01467ec ("selftests: forwarding: Add a test for FDB learning")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Tested-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
 tools/testing/selftests/net/forwarding/lib.sh | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tools/testing/selftests/net/forwarding/lib.sh b/tools/testing/selftests/net/forwarding/lib.sh
index 4e69497f021f3..26ba8b5d264a7 100755
--- a/tools/testing/selftests/net/forwarding/lib.sh
+++ b/tools/testing/selftests/net/forwarding/lib.sh
@@ -1240,6 +1240,7 @@ learning_test()
 	# FDB entry was installed.
 	bridge link set dev $br_port1 flood off
 
+	ip link set $host1_if promisc on
 	tc qdisc add dev $host1_if ingress
 	tc filter add dev $host1_if ingress protocol ip pref 1 handle 101 \
 		flower dst_mac $mac action drop
@@ -1289,6 +1290,7 @@ learning_test()
 
 	tc filter del dev $host1_if ingress protocol ip pref 1 handle 101 flower
 	tc qdisc del dev $host1_if ingress
+	ip link set $host1_if promisc off
 
 	bridge link set dev $br_port1 flood on
 
-- 
GitLab


From 83844aacab2015da1dba1df0cc61fc4b4c4e8076 Mon Sep 17 00:00:00 2001
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Date: Sun, 3 Jul 2022 10:36:26 +0300
Subject: [PATCH 1587/1731] selftests: forwarding: fix error message in
 learning_test

When packets are not received, they aren't received on $host1_if, so the
message talking about the second host not receiving them is incorrect.
Fix it.

Fixes: d4deb01467ec ("selftests: forwarding: Add a test for FDB learning")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
 tools/testing/selftests/net/forwarding/lib.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/testing/selftests/net/forwarding/lib.sh b/tools/testing/selftests/net/forwarding/lib.sh
index 26ba8b5d264a7..3ffb9d6c09504 100755
--- a/tools/testing/selftests/net/forwarding/lib.sh
+++ b/tools/testing/selftests/net/forwarding/lib.sh
@@ -1251,7 +1251,7 @@ learning_test()
 	tc -j -s filter show dev $host1_if ingress \
 		| jq -e ".[] | select(.options.handle == 101) \
 		| select(.options.actions[0].stats.packets == 1)" &> /dev/null
-	check_fail $? "Packet reached second host when should not"
+	check_fail $? "Packet reached first host when should not"
 
 	$MZ $host1_if -c 1 -p 64 -a $mac -t ip -q
 	sleep 1
-- 
GitLab


From 3770d92bd5237d686e49da7b2fb86f53ee6ed259 Mon Sep 17 00:00:00 2001
From: Michael Walle <michael@walle.cc>
Date: Thu, 26 May 2022 15:51:11 +0200
Subject: [PATCH 1588/1731] dmaengine: at_xdma: handle errors of
 at_xdmac_alloc_desc() correctly

It seems that it is valid to have less than the requested number of
descriptors. But what is not valid and leads to subsequent errors is to
have zero descriptors. In that case, abort the probing.

Fixes: e1f7c9eee707 ("dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver")
Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20220526135111.1470926-1-michael@walle.cc
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/dma/at_xdmac.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
index 3e9d726504e2e..7b3e6030f7b4b 100644
--- a/drivers/dma/at_xdmac.c
+++ b/drivers/dma/at_xdmac.c
@@ -1900,6 +1900,11 @@ static int at_xdmac_alloc_chan_resources(struct dma_chan *chan)
 	for (i = 0; i < init_nr_desc_per_channel; i++) {
 		desc = at_xdmac_alloc_desc(chan, GFP_KERNEL);
 		if (!desc) {
+			if (i == 0) {
+				dev_warn(chan2dev(chan),
+					 "can't allocate any descriptors\n");
+				return -EIO;
+			}
 			dev_warn(chan2dev(chan),
 				"only %d descriptors have been allocated\n", i);
 			break;
-- 
GitLab


From 8ffccd119a5908b240a26182be44c0ff3d1e3d85 Mon Sep 17 00:00:00 2001
From: Jerry Snitselaar <jsnitsel@redhat.com>
Date: Sat, 25 Jun 2022 22:16:48 -0700
Subject: [PATCH 1589/1731] dmaengine: idxd: Only call
 idxd_enable_system_pasid() if succeeded in enabling SVA feature

On a Sapphire Rapids system if boot without intel_iommu=on, the IDXD
driver will crash during probe in iommu_sva_bind_device().

[   21.423729] BUG: kernel NULL pointer dereference, address: 0000000000000038
[   21.445108] #PF: supervisor read access in kernel mode
[   21.450912] #PF: error_code(0x0000) - not-present page
[   21.456706] PGD 0
[   21.459047] Oops: 0000 [#1] PREEMPT SMP NOPTI
[   21.464004] CPU: 0 PID: 1420 Comm: kworker/0:3 Not tainted 5.19.0-0.rc3.27.eln120.x86_64 #1
[   21.464011] Hardware name: Intel Corporation EAGLESTREAM/EAGLESTREAM, BIOS EGSDCRB1.SYS.0067.D12.2110190954 10/19/2021
[   21.464015] Workqueue: events work_for_cpu_fn
[   21.464030] RIP: 0010:iommu_sva_bind_device+0x1d/0xe0
[   21.464046] Code: c3 cc 66 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 41 57 41 56 49 89 d6 41 55 41 54 55 53 48 83 ec 08 48 8b 87 d8 02 00 00 <48> 8b 40 38 48 8b 50 10 48 83 7a 70 00 48 89 14 24 0f 84 91 00 00
[   21.464050] RSP: 0018:ff7245d9096b7db8 EFLAGS: 00010296
[   21.464054] RAX: 0000000000000000 RBX: ff1eadeec8a51000 RCX: 0000000000000000
[   21.464058] RDX: ff7245d9096b7e24 RSI: 0000000000000000 RDI: ff1eadeec8a510d0
[   21.464060] RBP: ff1eadeec8a51000 R08: ffffffffb1a12300 R09: ff1eadffbfce25b4
[   21.464062] R10: ffffffffffffffff R11: 0000000000000038 R12: ffffffffc09f8000
[   21.464065] R13: ff1eadeec8a510d0 R14: ff7245d9096b7e24 R15: ff1eaddf54429000
[   21.464067] FS:  0000000000000000(0000) GS:ff1eadee7f600000(0000) knlGS:0000000000000000
[   21.464070] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[   21.464072] CR2: 0000000000000038 CR3: 00000008c0e10006 CR4: 0000000000771ef0
[   21.464074] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[   21.464076] DR3: 0000000000000000 DR6: 00000000fffe07f0 DR7: 0000000000000400
[   21.464078] PKRU: 55555554
[   21.464079] Call Trace:
[   21.464083]  <TASK>
[   21.464092]  idxd_pci_probe+0x259/0x1070 [idxd]
[   21.464121]  local_pci_probe+0x3e/0x80
[   21.464132]  work_for_cpu_fn+0x13/0x20
[   21.464136]  process_one_work+0x1c4/0x380
[   21.464143]  worker_thread+0x1ab/0x380
[   21.464147]  ? _raw_spin_lock_irqsave+0x23/0x50
[   21.464158]  ? process_one_work+0x380/0x380
[   21.464161]  kthread+0xe6/0x110
[   21.464168]  ? kthread_complete_and_exit+0x20/0x20
[   21.464172]  ret_from_fork+0x1f/0x30

iommu_sva_bind_device() requires SVA has been enabled successfully on
the IDXD device before it's called. Otherwise, iommu_sva_bind_device()
will access a NULL pointer. If Intel IOMMU is disabled, SVA cannot be
enabled and thus idxd_enable_system_pasid() and iommu_sva_bind_device()
should not be called.

Fixes: 42a1b73852c4 ("dmaengine: idxd: Separate user and kernel pasid enabling")
Cc: Vinod Koul <vkoul@kernel.org>
Cc: linux-kernel@vger.kernel.org
Cc: Dave Jiang <dave.jiang@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Link: https://lore.kernel.org/dmaengine/20220623170232.6whonfjuh3m5vcoy@cantor/
Signed-off-by: Jerry Snitselaar <jsnitsel@redhat.com>
Acked-by: Fenghua Yu <fenghua.yu@intel.com>
Link: https://lore.kernel.org/r/20220626051648.14249-1-jsnitsel@redhat.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/dma/idxd/init.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/dma/idxd/init.c b/drivers/dma/idxd/init.c
index 355fb3ef4cbfa..aa3478257ddb5 100644
--- a/drivers/dma/idxd/init.c
+++ b/drivers/dma/idxd/init.c
@@ -512,15 +512,16 @@ static int idxd_probe(struct idxd_device *idxd)
 	dev_dbg(dev, "IDXD reset complete\n");
 
 	if (IS_ENABLED(CONFIG_INTEL_IDXD_SVM) && sva) {
-		if (iommu_dev_enable_feature(dev, IOMMU_DEV_FEAT_SVA))
+		if (iommu_dev_enable_feature(dev, IOMMU_DEV_FEAT_SVA)) {
 			dev_warn(dev, "Unable to turn on user SVA feature.\n");
-		else
+		} else {
 			set_bit(IDXD_FLAG_USER_PASID_ENABLED, &idxd->flags);
 
-		if (idxd_enable_system_pasid(idxd))
-			dev_warn(dev, "No in-kernel DMA with PASID.\n");
-		else
-			set_bit(IDXD_FLAG_PASID_ENABLED, &idxd->flags);
+			if (idxd_enable_system_pasid(idxd))
+				dev_warn(dev, "No in-kernel DMA with PASID.\n");
+			else
+				set_bit(IDXD_FLAG_PASID_ENABLED, &idxd->flags);
+		}
 	} else if (!sva) {
 		dev_warn(dev, "User forced SVA off via module param.\n");
 	}
-- 
GitLab


From 8af3a0b23818af59971f538bf258c15e1033ea55 Mon Sep 17 00:00:00 2001
From: Leon Romanovsky <leonro@nvidia.com>
Date: Tue, 5 Jul 2022 13:21:14 +0300
Subject: [PATCH 1590/1731] gpio: vf610: fix compilation error
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Fix compilation error by explicitly adding the missing include.

drivers/gpio/gpio-vf610.c: In function ‘vf610_gpio_direction_input’:
drivers/gpio/gpio-vf610.c:120:9: error: implicit declaration of function ‘pinctrl_gpio_direction_input’; did you mean ‘vf610_gpio_direction_input’? [-Werror=implicit-function-declaration]
  120 |  return pinctrl_gpio_direction_input(chip->base + gpio);
      |         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
      |         vf610_gpio_direction_input

Fixes: 30a35c07d9e9 ("gpio: vf610: drop the SOC_VF610 dependency for GPIO_VF610")
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
---
 drivers/gpio/gpio-vf610.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpio/gpio-vf610.c b/drivers/gpio/gpio-vf610.c
index 23cddb265a0dc..9db42f6a20439 100644
--- a/drivers/gpio/gpio-vf610.c
+++ b/drivers/gpio/gpio-vf610.c
@@ -19,6 +19,7 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/of_irq.h>
+#include <linux/pinctrl/consumer.h>
 
 #define VF610_GPIO_PER_PORT		32
 
-- 
GitLab


From bf17455b9cbd4b10bf30d39c047307e1d774fb1a Mon Sep 17 00:00:00 2001
From: Yue Hu <huyue2@coolpad.com>
Date: Wed, 25 May 2022 10:32:22 +0800
Subject: [PATCH 1591/1731] fscache: Fix if condition in
 fscache_wait_on_volume_collision()

After waiting for the volume to complete the acquisition with timeout,
the if condition under which potential volume collision occurs should be
acquire the volume is still pending rather than not pending so that we
will continue to wait until the pending flag is cleared. Also, use the
existing test pending wrapper directly instead of test_bit().

Fixes: 62ab63352350 ("fscache: Implement volume registration")
Signed-off-by: Yue Hu <huyue2@coolpad.com>
Signed-off-by: David Howells <dhowells@redhat.com>
Reviewed-by: Gao Xiang <hsiangkao@linux.alibaba.com>
Reviewed-by: Jeffle Xu <jefflexu@linux.alibaba.com>
Reviewed-by: Jeff Layton <jlayton@kernel.org>
Link: https://listman.redhat.com/archives/linux-cachefs/2022-May/006918.html
---
 fs/fscache/volume.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fs/fscache/volume.c b/fs/fscache/volume.c
index f2aa7dbad7667..a058e0136bfeb 100644
--- a/fs/fscache/volume.c
+++ b/fs/fscache/volume.c
@@ -143,7 +143,7 @@ static void fscache_wait_on_volume_collision(struct fscache_volume *candidate,
 {
 	wait_var_event_timeout(&candidate->flags,
 			       !fscache_is_acquire_pending(candidate), 20 * HZ);
-	if (!fscache_is_acquire_pending(candidate)) {
+	if (fscache_is_acquire_pending(candidate)) {
 		pr_notice("Potential volume collision new=%08x old=%08x",
 			  candidate->debug_id, collidee_debug_id);
 		fscache_stat(&fscache_n_volumes_collision);
@@ -182,7 +182,7 @@ static bool fscache_hash_volume(struct fscache_volume *candidate)
 	hlist_bl_add_head(&candidate->hash_link, h);
 	hlist_bl_unlock(h);
 
-	if (test_bit(FSCACHE_VOLUME_ACQUIRE_PENDING, &candidate->flags))
+	if (fscache_is_acquire_pending(candidate))
 		fscache_wait_on_volume_collision(candidate, collidee_debug_id);
 	return true;
 
-- 
GitLab


From 5c4588aea6675b69e328d468c5b6be5127e19a79 Mon Sep 17 00:00:00 2001
From: Yue Hu <zbestahu@gmail.com>
Date: Wed, 25 May 2022 10:51:50 +0800
Subject: [PATCH 1592/1731] fscache: Introduce fscache_cookie_is_dropped()

FSCACHE_COOKIE_STATE_DROPPED will be read more than once, so let's add a
helper to avoid code duplication.

Signed-off-by: Yue Hu <huyue2@coolpad.com>
Signed-off-by: David Howells <dhowells@redhat.com>
Link: https://listman.redhat.com/archives/linux-cachefs/2022-May/006919.html
---
 fs/fscache/cookie.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/fs/fscache/cookie.c b/fs/fscache/cookie.c
index 9d3cf01117093..575a5ba07c0dd 100644
--- a/fs/fscache/cookie.c
+++ b/fs/fscache/cookie.c
@@ -372,17 +372,22 @@ nomem:
 	return NULL;
 }
 
+static inline bool fscache_cookie_is_dropped(struct fscache_cookie *cookie)
+{
+	return READ_ONCE(cookie->state) == FSCACHE_COOKIE_STATE_DROPPED;
+}
+
 static void fscache_wait_on_collision(struct fscache_cookie *candidate,
 				      struct fscache_cookie *wait_for)
 {
 	enum fscache_cookie_state *statep = &wait_for->state;
 
-	wait_var_event_timeout(statep, READ_ONCE(*statep) == FSCACHE_COOKIE_STATE_DROPPED,
+	wait_var_event_timeout(statep, fscache_cookie_is_dropped(wait_for),
 			       20 * HZ);
-	if (READ_ONCE(*statep) != FSCACHE_COOKIE_STATE_DROPPED) {
+	if (!fscache_cookie_is_dropped(wait_for)) {
 		pr_notice("Potential collision c=%08x old: c=%08x",
 			  candidate->debug_id, wait_for->debug_id);
-		wait_var_event(statep, READ_ONCE(*statep) == FSCACHE_COOKIE_STATE_DROPPED);
+		wait_var_event(statep, fscache_cookie_is_dropped(wait_for));
 	}
 }
 
-- 
GitLab


From 65aa5f6fd8a12e0a343aaf1815949a79a49e3f35 Mon Sep 17 00:00:00 2001
From: Jia Zhu <zhujia.zj@bytedance.com>
Date: Thu, 9 Jun 2022 16:54:10 +0800
Subject: [PATCH 1593/1731] cachefiles: narrow the scope of flushed requests
 when releasing fd

When an anonymous fd is released, only flush the requests
associated with it, rather than all of requests in xarray.

Fixes: 9032b6e8589f ("cachefiles: implement on-demand read")
Signed-off-by: Jia Zhu <zhujia.zj@bytedance.com>
Signed-off-by: David Howells <dhowells@redhat.com>
Reviewed-by: Jeffle Xu <jefflexu@linux.alibaba.com>
Reviewed-by: Gao Xiang <hsiangkao@linux.alibaba.com>
Link: https://listman.redhat.com/archives/linux-cachefs/2022-June/006937.html
---
 fs/cachefiles/ondemand.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/fs/cachefiles/ondemand.c b/fs/cachefiles/ondemand.c
index a41ae6efc5454..1fee702d55293 100644
--- a/fs/cachefiles/ondemand.c
+++ b/fs/cachefiles/ondemand.c
@@ -21,7 +21,8 @@ static int cachefiles_ondemand_fd_release(struct inode *inode,
 	 * anon_fd.
 	 */
 	xas_for_each(&xas, req, ULONG_MAX) {
-		if (req->msg.opcode == CACHEFILES_OP_READ) {
+		if (req->msg.object_id == object_id &&
+		    req->msg.opcode == CACHEFILES_OP_READ) {
 			req->error = -EIO;
 			complete(&req->done);
 			xas_store(&xas, NULL);
-- 
GitLab


From 85e4ea1049c70fb99de5c6057e835d151fb647da Mon Sep 17 00:00:00 2001
From: David Howells <dhowells@redhat.com>
Date: Wed, 20 Apr 2022 14:27:17 +0100
Subject: [PATCH 1594/1731] fscache: Fix invalidation/lookup race

If an NFS file is opened for writing and closed, fscache_invalidate() will
be asked to invalidate the file - however, if the cookie is in the
LOOKING_UP state (or the CREATING state), then request to invalidate
doesn't get recorded for fscache_cookie_state_machine() to do something
with.

Fix this by making __fscache_invalidate() set a flag if it sees the cookie
is in the LOOKING_UP state to indicate that we need to go to invalidation.
Note that this requires a count on the n_accesses counter for the state
machine, which that will release when it's done.

fscache_cookie_state_machine() then shifts to the INVALIDATING state if it
sees the flag.

Without this, an nfs file can get corrupted if it gets modified locally and
then read locally as the cache contents may not get updated.

Fixes: d24af13e2e23 ("fscache: Implement cookie invalidation")
Reported-by: Max Kellermann <mk@cm4all.com>
Signed-off-by: David Howells <dhowells@redhat.com>
Tested-by: Max Kellermann <mk@cm4all.com>
Link: https://lore.kernel.org/r/YlWWbpW5Foynjllo@rabbit.intern.cm-ag [1]
---
 fs/fscache/cookie.c     | 15 ++++++++++++++-
 include/linux/fscache.h |  1 +
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/fs/fscache/cookie.c b/fs/fscache/cookie.c
index 575a5ba07c0dd..74920826d8f67 100644
--- a/fs/fscache/cookie.c
+++ b/fs/fscache/cookie.c
@@ -522,7 +522,14 @@ static void fscache_perform_lookup(struct fscache_cookie *cookie)
 	}
 
 	fscache_see_cookie(cookie, fscache_cookie_see_active);
-	fscache_set_cookie_state(cookie, FSCACHE_COOKIE_STATE_ACTIVE);
+	spin_lock(&cookie->lock);
+	if (test_and_clear_bit(FSCACHE_COOKIE_DO_INVALIDATE, &cookie->flags))
+		__fscache_set_cookie_state(cookie,
+					   FSCACHE_COOKIE_STATE_INVALIDATING);
+	else
+		__fscache_set_cookie_state(cookie, FSCACHE_COOKIE_STATE_ACTIVE);
+	spin_unlock(&cookie->lock);
+	wake_up_cookie_state(cookie);
 	trace = fscache_access_lookup_cookie_end;
 
 out:
@@ -757,6 +764,9 @@ again_locked:
 			spin_lock(&cookie->lock);
 		}
 
+		if (test_and_clear_bit(FSCACHE_COOKIE_DO_INVALIDATE, &cookie->flags))
+			fscache_end_cookie_access(cookie, fscache_access_invalidate_cookie_end);
+
 		switch (state) {
 		case FSCACHE_COOKIE_STATE_RELINQUISHING:
 			fscache_see_cookie(cookie, fscache_cookie_see_relinquish);
@@ -1053,6 +1063,9 @@ void __fscache_invalidate(struct fscache_cookie *cookie,
 		return;
 
 	case FSCACHE_COOKIE_STATE_LOOKING_UP:
+		__fscache_begin_cookie_access(cookie, fscache_access_invalidate_cookie);
+		set_bit(FSCACHE_COOKIE_DO_INVALIDATE, &cookie->flags);
+		fallthrough;
 	case FSCACHE_COOKIE_STATE_CREATING:
 		spin_unlock(&cookie->lock);
 		_leave(" [look %x]", cookie->inval_counter);
diff --git a/include/linux/fscache.h b/include/linux/fscache.h
index 72585c9729a2c..b86265664879e 100644
--- a/include/linux/fscache.h
+++ b/include/linux/fscache.h
@@ -130,6 +130,7 @@ struct fscache_cookie {
 #define FSCACHE_COOKIE_DO_PREP_TO_WRITE	12		/* T if cookie needs write preparation */
 #define FSCACHE_COOKIE_HAVE_DATA	13		/* T if this cookie has data stored */
 #define FSCACHE_COOKIE_IS_HASHED	14		/* T if this cookie is hashed */
+#define FSCACHE_COOKIE_DO_INVALIDATE	15		/* T if cookie needs invalidation */
 
 	enum fscache_cookie_state	state;
 	u8				advice;		/* FSCACHE_ADV_* */
-- 
GitLab


From c5e58c4545a69677d078b4c813b5d10d3481be9c Mon Sep 17 00:00:00 2001
From: Takashi Iwai <tiwai@suse.de>
Date: Tue, 5 Jul 2022 17:23:36 +0200
Subject: [PATCH 1595/1731] ALSA: cs46xx: Fix missing snd_card_free() call at
 probe error

The previous cleanup with devres may lead to the incorrect release
orders at the probe error handling due to the devres's nature.  Until
we register the card, snd_card_free() has to be called at first for
releasing the stuff properly when the driver tries to manage and
release the stuff via card->private_free().

This patch fixes it by calling snd_card_free() manually on the error
from the probe callback.

Fixes: 5bff69b3645d ("ALSA: cs46xx: Allocate resources with device-managed APIs")
Cc: <stable@vger.kernel.org>
Reported-and-tested-by: Jan Engelhardt <jengelh@inai.de>
Link: https://lore.kernel.org/r/p2p1s96o-746-74p4-s95-61qo1p7782pn@vanv.qr
Link: https://lore.kernel.org/r/20220705152336.350-1-tiwai@suse.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/pci/cs46xx/cs46xx.c | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/sound/pci/cs46xx/cs46xx.c b/sound/pci/cs46xx/cs46xx.c
index bd60308769ff7..8634004a606b6 100644
--- a/sound/pci/cs46xx/cs46xx.c
+++ b/sound/pci/cs46xx/cs46xx.c
@@ -74,36 +74,36 @@ static int snd_card_cs46xx_probe(struct pci_dev *pci,
 	err = snd_cs46xx_create(card, pci,
 				external_amp[dev], thinkpad[dev]);
 	if (err < 0)
-		return err;
+		goto error;
 	card->private_data = chip;
 	chip->accept_valid = mmap_valid[dev];
 	err = snd_cs46xx_pcm(chip, 0);
 	if (err < 0)
-		return err;
+		goto error;
 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 	err = snd_cs46xx_pcm_rear(chip, 1);
 	if (err < 0)
-		return err;
+		goto error;
 	err = snd_cs46xx_pcm_iec958(chip, 2);
 	if (err < 0)
-		return err;
+		goto error;
 #endif
 	err = snd_cs46xx_mixer(chip, 2);
 	if (err < 0)
-		return err;
+		goto error;
 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 	if (chip->nr_ac97_codecs ==2) {
 		err = snd_cs46xx_pcm_center_lfe(chip, 3);
 		if (err < 0)
-			return err;
+			goto error;
 	}
 #endif
 	err = snd_cs46xx_midi(chip, 0);
 	if (err < 0)
-		return err;
+		goto error;
 	err = snd_cs46xx_start_dsp(chip);
 	if (err < 0)
-		return err;
+		goto error;
 
 	snd_cs46xx_gameport(chip);
 
@@ -117,11 +117,15 @@ static int snd_card_cs46xx_probe(struct pci_dev *pci,
 
 	err = snd_card_register(card);
 	if (err < 0)
-		return err;
+		goto error;
 
 	pci_set_drvdata(pci, card);
 	dev++;
 	return 0;
+
+ error:
+	snd_card_free(card);
+	return err;
 }
 
 static struct pci_driver cs46xx_driver = {
-- 
GitLab


From 7feec7430edddb87c24b0a86b08a03d0b496a755 Mon Sep 17 00:00:00 2001
From: Mario Limonciello <mario.limonciello@amd.com>
Date: Tue, 5 Jul 2022 13:29:14 -0500
Subject: [PATCH 1596/1731] ACPI: CPPC: Only probe for _CPC if CPPC v2 is acked

Previously the kernel used to ignore whether the firmware masked CPPC
or CPPCv2 and would just pretend that it worked.

When support for the USB4 bit in _OSC was introduced from commit
9e1f561afb ("ACPI: Execute platform _OSC also with query bit clear")
the kernel began to look at the return when the query bit was clear.

This caused regressions that were misdiagnosed and attempted to be solved
as part of commit 2ca8e6285250 ("Revert "ACPI: Pass the same capabilities
to the _OSC regardless of the query flag""). This caused a different
regression where non-Intel systems weren't able to negotiate _OSC
properly.

This was reverted in commit 2ca8e6285250 ("Revert "ACPI: Pass the same
capabilities to the _OSC regardless of the query flag"") and attempted to
be fixed by commit c42fa24b4475 ("ACPI: bus: Avoid using CPPC if not
supported by firmware") but the regression still returned.

These systems with the regression only load support for CPPC from an SSDT
dynamically when _OSC reports CPPC v2.  Avoid the problem by not letting
CPPC satisfy the requirement in `acpi_cppc_processor_probe`.

Reported-by: CUI Hao <cuihao.leo@gmail.com>
Reported-by: maxim.novozhilov@gmail.com
Reported-by: lethe.tree@protonmail.com
Reported-by: garystephenwright@gmail.com
Reported-by: galaxyking0419@gmail.com
Fixes: c42fa24b4475 ("ACPI: bus: Avoid using CPPC if not supported by firmware")
Fixes: 2ca8e6285250 ("Revert "ACPI Pass the same capabilities to the _OSC regardless of the query flag"")
Link: https://bugzilla.kernel.org/show_bug.cgi?id=213023
Link: https://bugzilla.redhat.com/show_bug.cgi?id=2075387
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Tested-by: CUI Hao <cuihao.leo@gmail.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 drivers/acpi/bus.c       | 11 +++++------
 drivers/acpi/cppc_acpi.c |  4 +++-
 include/linux/acpi.h     |  2 +-
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
index 86fa61a21826c..e2db1bdd9dd25 100644
--- a/drivers/acpi/bus.c
+++ b/drivers/acpi/bus.c
@@ -298,7 +298,7 @@ EXPORT_SYMBOL_GPL(osc_cpc_flexible_adr_space_confirmed);
 bool osc_sb_native_usb4_support_confirmed;
 EXPORT_SYMBOL_GPL(osc_sb_native_usb4_support_confirmed);
 
-bool osc_sb_cppc_not_supported;
+bool osc_sb_cppc2_support_acked;
 
 static u8 sb_uuid_str[] = "0811B06E-4A27-44F9-8D60-3CBBC22E7B48";
 static void acpi_bus_osc_negotiate_platform_control(void)
@@ -358,11 +358,6 @@ static void acpi_bus_osc_negotiate_platform_control(void)
 		return;
 	}
 
-#ifdef CONFIG_ACPI_CPPC_LIB
-	osc_sb_cppc_not_supported = !(capbuf_ret[OSC_SUPPORT_DWORD] &
-			(OSC_SB_CPC_SUPPORT | OSC_SB_CPCV2_SUPPORT));
-#endif
-
 	/*
 	 * Now run _OSC again with query flag clear and with the caps
 	 * supported by both the OS and the platform.
@@ -376,6 +371,10 @@ static void acpi_bus_osc_negotiate_platform_control(void)
 
 	capbuf_ret = context.ret.pointer;
 	if (context.ret.length > OSC_SUPPORT_DWORD) {
+#ifdef CONFIG_ACPI_CPPC_LIB
+		osc_sb_cppc2_support_acked = capbuf_ret[OSC_SUPPORT_DWORD] & OSC_SB_CPCV2_SUPPORT;
+#endif
+
 		osc_sb_apei_support_acked =
 			capbuf_ret[OSC_SUPPORT_DWORD] & OSC_SB_APEI_SUPPORT;
 		osc_pc_lpi_support_confirmed =
diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index 903528f7e187e..d64facbda0fb7 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -684,8 +684,10 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 	acpi_status status;
 	int ret = -ENODATA;
 
-	if (osc_sb_cppc_not_supported)
+	if (!osc_sb_cppc2_support_acked) {
+		pr_debug("CPPC v2 _OSC not acked\n");
 		return -ENODEV;
+	}
 
 	/* Parse the ACPI _CPC table for this CPU. */
 	status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 4f82a5bc6d987..44975c1bbe12f 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -584,7 +584,7 @@ acpi_status acpi_run_osc(acpi_handle handle, struct acpi_osc_context *context);
 extern bool osc_sb_apei_support_acked;
 extern bool osc_pc_lpi_support_confirmed;
 extern bool osc_sb_native_usb4_support_confirmed;
-extern bool osc_sb_cppc_not_supported;
+extern bool osc_sb_cppc2_support_acked;
 extern bool osc_cpc_flexible_adr_space_confirmed;
 
 /* USB4 Capabilities */
-- 
GitLab


From 8b356e536e69f3a4d6778ae9f0858a1beadabb1f Mon Sep 17 00:00:00 2001
From: Mario Limonciello <mario.limonciello@amd.com>
Date: Tue, 5 Jul 2022 13:29:15 -0500
Subject: [PATCH 1597/1731] ACPI: CPPC: Don't require _OSC if X86_FEATURE_CPPC
 is supported

commit 72f2ecb7ece7 ("ACPI: bus: Set CPPC _OSC bits for all and
when CPPC_LIB is supported") added support for claiming to
support CPPC in _OSC on non-Intel platforms.

This unfortunately caused a regression on a vartiety of AMD
platforms in the field because a number of AMD platforms don't set
the `_OSC` bit 5 or 6 to indicate CPPC or CPPC v2 support.

As these AMD platforms already claim CPPC support via a dedicated
MSR from `X86_FEATURE_CPPC`, use this enable this feature rather
than requiring the `_OSC` on platforms with a dedicated MSR.

If there is additional breakage on the shared memory designs also
missing this _OSC, additional follow up changes may be needed.

Fixes: 72f2ecb7ece7 ("Set CPPC _OSC bits for all and when CPPC_LIB is supported")
Reported-by: Perry Yuan <perry.yuan@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 arch/x86/kernel/acpi/cppc.c | 10 ++++++++++
 drivers/acpi/cppc_acpi.c    | 16 +++++++++++++++-
 include/acpi/cppc_acpi.h    |  1 +
 3 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c
index 8b8cbf22461a4..734b96454896b 100644
--- a/arch/x86/kernel/acpi/cppc.c
+++ b/arch/x86/kernel/acpi/cppc.c
@@ -11,6 +11,16 @@
 
 /* Refer to drivers/acpi/cppc_acpi.c for the description of functions */
 
+bool cpc_supported_by_cpu(void)
+{
+	switch (boot_cpu_data.x86_vendor) {
+	case X86_VENDOR_AMD:
+	case X86_VENDOR_HYGON:
+		return boot_cpu_has(X86_FEATURE_CPPC);
+	}
+	return false;
+}
+
 bool cpc_ffh_supported(void)
 {
 	return true;
diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index d64facbda0fb7..6ff1901d7d436 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -577,6 +577,19 @@ bool __weak cpc_ffh_supported(void)
 	return false;
 }
 
+/**
+ * cpc_supported_by_cpu() - check if CPPC is supported by CPU
+ *
+ * Check if the architectural support for CPPC is present even
+ * if the _OSC hasn't prescribed it
+ *
+ * Return: true for supported, false for not supported
+ */
+bool __weak cpc_supported_by_cpu(void)
+{
+	return false;
+}
+
 /**
  * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
  *
@@ -686,7 +699,8 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 
 	if (!osc_sb_cppc2_support_acked) {
 		pr_debug("CPPC v2 _OSC not acked\n");
-		return -ENODEV;
+		if (!cpc_supported_by_cpu())
+			return -ENODEV;
 	}
 
 	/* Parse the ACPI _CPC table for this CPU. */
diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h
index c6108581d97dc..d389bab54241d 100644
--- a/include/acpi/cppc_acpi.h
+++ b/include/acpi/cppc_acpi.h
@@ -145,6 +145,7 @@ extern bool cppc_allow_fast_switch(void);
 extern int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data);
 extern unsigned int cppc_get_transition_latency(int cpu);
 extern bool cpc_ffh_supported(void);
+extern bool cpc_supported_by_cpu(void);
 extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val);
 extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val);
 #else /* !CONFIG_ACPI_CPPC_LIB */
-- 
GitLab


From e36bea6e78ab2b6c9c7396972fee231eae551cfc Mon Sep 17 00:00:00 2001
From: Vasyl Vavrychuk <vasyl.vavrychuk@opensynergy.com>
Date: Tue, 5 Jul 2022 15:59:31 +0300
Subject: [PATCH 1598/1731] Bluetooth: core: Fix deadlock on hci_power_on_sync.

`cancel_work_sync(&hdev->power_on)` was moved to hci_dev_close_sync in
commit [1] to ensure that power_on work is canceled after HCI interface
down.

But, in certain cases power_on work function may call hci_dev_close_sync
itself: hci_power_on -> hci_dev_do_close -> hci_dev_close_sync ->
cancel_work_sync(&hdev->power_on), causing deadlock. In particular, this
happens when device is rfkilled on boot. To avoid deadlock, move
power_on work canceling out of hci_dev_do_close/hci_dev_close_sync.

Deadlock introduced by commit [1] was reported in [2,3] as broken
suspend. Suspend did not work because `hdev->req_lock` held as result of
`power_on` work deadlock. In fact, other BT features were not working.
It was not observed when testing [1] since it was verified without
rfkill in place.

NOTE: It is not needed to cancel power_on work from other places where
hci_dev_do_close/hci_dev_close_sync is called in case:
* Requests were serialized due to `hdev->req_workqueue`. The power_on
work is first in that workqueue.
* hci_rfkill_set_block which won't close device anyway until HCI_SETUP
is on.
* hci_sock_release which runs after hci_sock_bind which ensures
HCI_SETUP was cleared.

As result, behaviour is the same as in pre-dd06ed7 commit, except
power_on work cancel added to hci_dev_close.

[1]: commit ff7f2926114d ("Bluetooth: core: Fix missing power_on work cancel on HCI close")
[2]: https://lore.kernel.org/lkml/20220614181706.26513-1-max.oss.09@gmail.com/
[2]: https://lore.kernel.org/lkml/1236061d-95dd-c3ad-a38f-2dae7aae51ef@o2.pl/

Fixes: ff7f2926114d ("Bluetooth: core: Fix missing power_on work cancel on HCI close")
Signed-off-by: Vasyl Vavrychuk <vasyl.vavrychuk@opensynergy.com>
Reported-by: Max Krummenacher <max.krummenacher@toradex.com>
Reported-by: Mateusz Jonczyk <mat.jonczyk@o2.pl>
Tested-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
---
 net/bluetooth/hci_core.c | 3 +++
 net/bluetooth/hci_sync.c | 1 -
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c
index 59a5c1341c26a..a0f99baafd357 100644
--- a/net/bluetooth/hci_core.c
+++ b/net/bluetooth/hci_core.c
@@ -571,6 +571,7 @@ int hci_dev_close(__u16 dev)
 		goto done;
 	}
 
+	cancel_work_sync(&hdev->power_on);
 	if (hci_dev_test_and_clear_flag(hdev, HCI_AUTO_OFF))
 		cancel_delayed_work(&hdev->power_off);
 
@@ -2675,6 +2676,8 @@ void hci_unregister_dev(struct hci_dev *hdev)
 	list_del(&hdev->list);
 	write_unlock(&hci_dev_list_lock);
 
+	cancel_work_sync(&hdev->power_on);
+
 	hci_cmd_sync_clear(hdev);
 
 	if (!test_bit(HCI_QUIRK_NO_SUSPEND_NOTIFIER, &hdev->quirks))
diff --git a/net/bluetooth/hci_sync.c b/net/bluetooth/hci_sync.c
index 286d6767f0177..1739e8cb3291e 100644
--- a/net/bluetooth/hci_sync.c
+++ b/net/bluetooth/hci_sync.c
@@ -4088,7 +4088,6 @@ int hci_dev_close_sync(struct hci_dev *hdev)
 
 	bt_dev_dbg(hdev, "");
 
-	cancel_work_sync(&hdev->power_on);
 	cancel_delayed_work(&hdev->power_off);
 	cancel_delayed_work(&hdev->ncmd_timer);
 
-- 
GitLab


From e6fa930f73a15238f3cb0c204e2f786c919b815c Mon Sep 17 00:00:00 2001
From: Michael Walle <michael@walle.cc>
Date: Mon, 4 Jul 2022 17:36:54 +0200
Subject: [PATCH 1599/1731] net: lan966x: hardcode the number of external ports

Instead of counting the child nodes in the device tree, hardcode the
number of ports in the driver itself.  The counting won't work at all
if an ethernet port is marked as disabled, e.g. because it is not
connected on the board at all.

It turns out that the LAN9662 and LAN9668 use the same switching IP
with the same synthesis parameters. The only difference is that the
output ports are not connected. Thus, we can just hardcode the
number of physical ports to 8.

Fixes: db8bcaad5393 ("net: lan966x: add the basic lan966x driver")
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Link: https://lore.kernel.org/r/20220704153654.1167886-1-michael@walle.cc
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/ethernet/microchip/lan966x/lan966x_main.c | 8 ++------
 drivers/net/ethernet/microchip/lan966x/lan966x_main.h | 1 +
 2 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c
index 5784c4161e5e6..1d6e3b641b2e6 100644
--- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c
+++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c
@@ -994,7 +994,7 @@ static int lan966x_probe(struct platform_device *pdev)
 	struct fwnode_handle *ports, *portnp;
 	struct lan966x *lan966x;
 	u8 mac_addr[ETH_ALEN];
-	int err, i;
+	int err;
 
 	lan966x = devm_kzalloc(&pdev->dev, sizeof(*lan966x), GFP_KERNEL);
 	if (!lan966x)
@@ -1025,11 +1025,7 @@ static int lan966x_probe(struct platform_device *pdev)
 	if (err)
 		return dev_err_probe(&pdev->dev, err, "Reset failed");
 
-	i = 0;
-	fwnode_for_each_available_child_node(ports, portnp)
-		++i;
-
-	lan966x->num_phys_ports = i;
+	lan966x->num_phys_ports = NUM_PHYS_PORTS;
 	lan966x->ports = devm_kcalloc(&pdev->dev, lan966x->num_phys_ports,
 				      sizeof(struct lan966x_port *),
 				      GFP_KERNEL);
diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h b/drivers/net/ethernet/microchip/lan966x/lan966x_main.h
index 3b86ddddc7560..2787055c18475 100644
--- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h
+++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.h
@@ -34,6 +34,7 @@
 /* Reserved amount for (SRC, PRIO) at index 8*SRC + PRIO */
 #define QSYS_Q_RSRV			95
 
+#define NUM_PHYS_PORTS			8
 #define CPU_PORT			8
 
 /* Reserved PGIDs */
-- 
GitLab


From b64b3b2f1d81f83519582e1feee87d77f51f5f17 Mon Sep 17 00:00:00 2001
From: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Date: Fri, 20 May 2022 21:14:32 +0300
Subject: [PATCH 1600/1731] dmaengine: pl330: Fix lockdep warning about
 non-static key

The DEFINE_SPINLOCK() macro shouldn't be used for dynamically allocated
spinlocks. The lockdep warns about this and disables locking validator.
Fix the warning by making lock static.

 INFO: trying to register non-static key.
 The code is fine but needs lockdep annotation, or maybe
 you didn't initialize this object before use?
 turning off the locking correctness validator.
 Hardware name: Radxa ROCK Pi 4C (DT)
 Call trace:
  dump_backtrace.part.0+0xcc/0xe0
  show_stack+0x18/0x6c
  dump_stack_lvl+0x8c/0xb8
  dump_stack+0x18/0x34
  register_lock_class+0x4a8/0x4cc
  __lock_acquire+0x78/0x20cc
  lock_acquire.part.0+0xe0/0x230
  lock_acquire+0x68/0x84
  _raw_spin_lock_irqsave+0x84/0xc4
  add_desc+0x44/0xc0
  pl330_get_desc+0x15c/0x1d0
  pl330_prep_dma_cyclic+0x100/0x270
  snd_dmaengine_pcm_trigger+0xec/0x1c0
  dmaengine_pcm_trigger+0x18/0x24
  ...

Fixes: e588710311ee ("dmaengine: pl330: fix descriptor allocation fail")
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Link: https://lore.kernel.org/r/20220520181432.149904-1-dmitry.osipenko@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/dma/pl330.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 858400e42ec05..09915a5cba3ea 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -2589,7 +2589,7 @@ static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
 
 	/* If the DMAC pool is empty, alloc new */
 	if (!desc) {
-		DEFINE_SPINLOCK(lock);
+		static DEFINE_SPINLOCK(lock);
 		LIST_HEAD(pool);
 
 		if (!add_desc(&pool, &lock, GFP_ATOMIC, 1))
-- 
GitLab


From 1dbe67b9faea0bc340cce894018076679c16cb71 Mon Sep 17 00:00:00 2001
From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Date: Sun, 22 May 2022 19:41:05 +0200
Subject: [PATCH 1601/1731] dmaengine: lgm: Fix an error handling path in
 intel_ldma_probe()

ldma_clk_disable() calls both:
	clk_disable_unprepare(d->core_clk);
	reset_control_assert(d->rst);

So, should devm_reset_control_get_optional() fail, core_clk should not
be prepare_enable'd before it, otherwise it will never be
disable_unprepare'd.

Reorder the code to handle the error handling path as expected.

Fixes: 32d31c79a1a4 ("dmaengine: Add Intel LGM SoC DMA support.")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/18504549bc4d2b62a72a02cb22a2e4d8e6a58720.1653241224.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/dma/lgm/lgm-dma.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/lgm/lgm-dma.c b/drivers/dma/lgm/lgm-dma.c
index efe8bd3a0e2aa..9b9184f964be3 100644
--- a/drivers/dma/lgm/lgm-dma.c
+++ b/drivers/dma/lgm/lgm-dma.c
@@ -1593,11 +1593,12 @@ static int intel_ldma_probe(struct platform_device *pdev)
 	d->core_clk = devm_clk_get_optional(dev, NULL);
 	if (IS_ERR(d->core_clk))
 		return PTR_ERR(d->core_clk);
-	clk_prepare_enable(d->core_clk);
 
 	d->rst = devm_reset_control_get_optional(dev, NULL);
 	if (IS_ERR(d->rst))
 		return PTR_ERR(d->rst);
+
+	clk_prepare_enable(d->core_clk);
 	reset_control_deassert(d->rst);
 
 	ret = devm_add_action_or_reset(dev, ldma_clk_disable, d);
-- 
GitLab


From b57feed2cc2622ae14b2fa62f19e973e5e0a60cf Mon Sep 17 00:00:00 2001
From: Michael Roth <michael.roth@amd.com>
Date: Tue, 5 Jul 2022 21:53:15 -0500
Subject: [PATCH 1602/1731] x86/compressed/64: Add identity mappings for
 setup_data entries

The decompressed kernel initially relies on the identity map set up by
the boot/compressed kernel for accessing things like boot_params. With
the recent introduction of SEV-SNP support, the decompressed kernel
also needs to access the setup_data entries pointed to by
boot_params->hdr.setup_data.

This can lead to a crash in the kexec kernel during early boot due to
these entries not currently being included in the initial identity map,
see thread at Link below.

Include mappings for the setup_data entries in the initial identity map.

  [ bp: Massage commit message and use a helper var for better readability. ]

Fixes: b190a043c49a ("x86/sev: Add SEV-SNP feature detection/setup")
Reported-by: Jun'ichi Nomura <junichi.nomura@nec.com>
Signed-off-by: Michael Roth <michael.roth@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/TYCPR01MB694815CD815E98945F63C99183B49@TYCPR01MB6948.jpnprd01.prod.outlook.com
---
 arch/x86/boot/compressed/ident_map_64.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/x86/boot/compressed/ident_map_64.c b/arch/x86/boot/compressed/ident_map_64.c
index 44c350d627c79..d4a314cc50d6e 100644
--- a/arch/x86/boot/compressed/ident_map_64.c
+++ b/arch/x86/boot/compressed/ident_map_64.c
@@ -110,6 +110,7 @@ void kernel_add_identity_map(unsigned long start, unsigned long end)
 void initialize_identity_maps(void *rmode)
 {
 	unsigned long cmdline;
+	struct setup_data *sd;
 
 	/* Exclude the encryption mask from __PHYSICAL_MASK */
 	physical_mask &= ~sme_me_mask;
@@ -163,6 +164,18 @@ void initialize_identity_maps(void *rmode)
 	cmdline = get_cmd_line_ptr();
 	kernel_add_identity_map(cmdline, cmdline + COMMAND_LINE_SIZE);
 
+	/*
+	 * Also map the setup_data entries passed via boot_params in case they
+	 * need to be accessed by uncompressed kernel via the identity mapping.
+	 */
+	sd = (struct setup_data *)boot_params->hdr.setup_data;
+	while (sd) {
+		unsigned long sd_addr = (unsigned long)sd;
+
+		kernel_add_identity_map(sd_addr, sd_addr + sizeof(*sd) + sd->len);
+		sd = (struct setup_data *)sd->next;
+	}
+
 	sev_prep_identity_maps(top_level_pgt);
 
 	/* Load the new page-table. */
-- 
GitLab


From 316f92a705a4c2bf4712135180d56f3cca09243a Mon Sep 17 00:00:00 2001
From: Yian Chen <yian.chen@intel.com>
Date: Fri, 20 May 2022 17:21:15 -0700
Subject: [PATCH 1603/1731] iommu/vt-d: Fix PCI bus rescan device hot add

Notifier calling chain uses priority to determine the execution
order of the notifiers or listeners registered to the chain.
PCI bus device hot add utilizes the notification mechanism.

The current code sets low priority (INT_MIN) to Intel
dmar_pci_bus_notifier and postpones DMAR decoding after adding
new device into IOMMU. The result is that struct device pointer
cannot be found in DRHD search for the new device's DMAR/IOMMU.
Subsequently, the device is put under the "catch-all" IOMMU
instead of the correct one. This could cause system hang when
device TLB invalidation is sent to the wrong IOMMU. Invalidation
timeout error and hard lockup have been observed and data
inconsistency/crush may occur as well.

This patch fixes the issue by setting a positive priority(1) for
dmar_pci_bus_notifier while the priority of IOMMU bus notifier
uses the default value(0), therefore DMAR decoding will be in
advance of DRHD search for a new device to find the correct IOMMU.

Following is a 2-step example that triggers the bug by simulating
PCI device hot add behavior in Intel Sapphire Rapids server.

echo 1 > /sys/bus/pci/devices/0000:6a:01.0/remove
echo 1 > /sys/bus/pci/rescan

Fixes: 59ce0515cdaf ("iommu/vt-d: Update DRHD/RMRR/ATSR device scope")
Cc: stable@vger.kernel.org # v3.15+
Reported-by: Zhang, Bernice <bernice.zhang@intel.com>
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Yian Chen <yian.chen@intel.com>
Link: https://lore.kernel.org/r/20220521002115.1624069-1-yian.chen@intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
---
 drivers/iommu/intel/dmar.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
index 592c1e1a5d4b9..9699ca101c624 100644
--- a/drivers/iommu/intel/dmar.c
+++ b/drivers/iommu/intel/dmar.c
@@ -382,7 +382,7 @@ static int dmar_pci_bus_notifier(struct notifier_block *nb,
 
 static struct notifier_block dmar_pci_bus_nb = {
 	.notifier_call = dmar_pci_bus_notifier,
-	.priority = INT_MIN,
+	.priority = 1,
 };
 
 static struct dmar_drhd_unit *
-- 
GitLab


From 4140d77a022101376bbfa3ec3e3da5063455c60e Mon Sep 17 00:00:00 2001
From: Lu Baolu <baolu.lu@linux.intel.com>
Date: Sat, 25 Jun 2022 21:34:30 +0800
Subject: [PATCH 1604/1731] iommu/vt-d: Fix RID2PASID setup/teardown failure

The IOMMU driver shares the pasid table for PCI alias devices. When the
RID2PASID entry of the shared pasid table has been filled by the first
device, the subsequent device will encounter the "DMAR: Setup RID2PASID
failed" failure as the pasid entry has already been marked as present.
As the result, the IOMMU probing process will be aborted.

On the contrary, when any alias device is hot-removed from the system,
for example, by writing to /sys/bus/pci/devices/.../remove, the shared
RID2PASID will be cleared without any notifications to other devices.
As the result, any DMAs from those rest devices are blocked.

Sharing pasid table among PCI alias devices could save two memory pages
for devices underneath the PCIe-to-PCI bridges. Anyway, considering that
those devices are rare on modern platforms that support VT-d in scalable
mode and the saved memory is negligible, it's reasonable to remove this
part of immature code to make the driver feasible and stable.

Fixes: ef848b7e5a6a0 ("iommu/vt-d: Setup pasid entry for RID2PASID support")
Reported-by: Chenyi Qiang <chenyi.qiang@intel.com>
Reported-by: Ethan Zhao <haifeng.zhao@linux.intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Reviewed-by: Ethan Zhao <haifeng.zhao@linux.intel.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20220623065720.727849-1-baolu.lu@linux.intel.com
Link: https://lore.kernel.org/r/20220625133430.2200315-2-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
---
 drivers/iommu/intel/iommu.c | 24 -------------
 drivers/iommu/intel/pasid.c | 69 ++-----------------------------------
 drivers/iommu/intel/pasid.h |  1 -
 include/linux/intel-iommu.h |  3 --
 4 files changed, 3 insertions(+), 94 deletions(-)

diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 44016594831de..5c0dce78586aa 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -320,30 +320,6 @@ EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
 DEFINE_SPINLOCK(device_domain_lock);
 static LIST_HEAD(device_domain_list);
 
-/*
- * Iterate over elements in device_domain_list and call the specified
- * callback @fn against each element.
- */
-int for_each_device_domain(int (*fn)(struct device_domain_info *info,
-				     void *data), void *data)
-{
-	int ret = 0;
-	unsigned long flags;
-	struct device_domain_info *info;
-
-	spin_lock_irqsave(&device_domain_lock, flags);
-	list_for_each_entry(info, &device_domain_list, global) {
-		ret = fn(info, data);
-		if (ret) {
-			spin_unlock_irqrestore(&device_domain_lock, flags);
-			return ret;
-		}
-	}
-	spin_unlock_irqrestore(&device_domain_lock, flags);
-
-	return 0;
-}
-
 const struct iommu_ops intel_iommu_ops;
 
 static bool translation_pre_enabled(struct intel_iommu *iommu)
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index cb4c1d0cf25c0..17cad7c1f62d6 100644
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@ -86,54 +86,6 @@ void vcmd_free_pasid(struct intel_iommu *iommu, u32 pasid)
 /*
  * Per device pasid table management:
  */
-static inline void
-device_attach_pasid_table(struct device_domain_info *info,
-			  struct pasid_table *pasid_table)
-{
-	info->pasid_table = pasid_table;
-	list_add(&info->table, &pasid_table->dev);
-}
-
-static inline void
-device_detach_pasid_table(struct device_domain_info *info,
-			  struct pasid_table *pasid_table)
-{
-	info->pasid_table = NULL;
-	list_del(&info->table);
-}
-
-struct pasid_table_opaque {
-	struct pasid_table	**pasid_table;
-	int			segment;
-	int			bus;
-	int			devfn;
-};
-
-static int search_pasid_table(struct device_domain_info *info, void *opaque)
-{
-	struct pasid_table_opaque *data = opaque;
-
-	if (info->iommu->segment == data->segment &&
-	    info->bus == data->bus &&
-	    info->devfn == data->devfn &&
-	    info->pasid_table) {
-		*data->pasid_table = info->pasid_table;
-		return 1;
-	}
-
-	return 0;
-}
-
-static int get_alias_pasid_table(struct pci_dev *pdev, u16 alias, void *opaque)
-{
-	struct pasid_table_opaque *data = opaque;
-
-	data->segment = pci_domain_nr(pdev->bus);
-	data->bus = PCI_BUS_NUM(alias);
-	data->devfn = alias & 0xff;
-
-	return for_each_device_domain(&search_pasid_table, data);
-}
 
 /*
  * Allocate a pasid table for @dev. It should be called in a
@@ -143,28 +95,18 @@ int intel_pasid_alloc_table(struct device *dev)
 {
 	struct device_domain_info *info;
 	struct pasid_table *pasid_table;
-	struct pasid_table_opaque data;
 	struct page *pages;
 	u32 max_pasid = 0;
-	int ret, order;
-	int size;
+	int order, size;
 
 	might_sleep();
 	info = dev_iommu_priv_get(dev);
 	if (WARN_ON(!info || !dev_is_pci(dev) || info->pasid_table))
 		return -EINVAL;
 
-	/* DMA alias device already has a pasid table, use it: */
-	data.pasid_table = &pasid_table;
-	ret = pci_for_each_dma_alias(to_pci_dev(dev),
-				     &get_alias_pasid_table, &data);
-	if (ret)
-		goto attach_out;
-
 	pasid_table = kzalloc(sizeof(*pasid_table), GFP_KERNEL);
 	if (!pasid_table)
 		return -ENOMEM;
-	INIT_LIST_HEAD(&pasid_table->dev);
 
 	if (info->pasid_supported)
 		max_pasid = min_t(u32, pci_max_pasids(to_pci_dev(dev)),
@@ -182,9 +124,7 @@ int intel_pasid_alloc_table(struct device *dev)
 	pasid_table->table = page_address(pages);
 	pasid_table->order = order;
 	pasid_table->max_pasid = 1 << (order + PAGE_SHIFT + 3);
-
-attach_out:
-	device_attach_pasid_table(info, pasid_table);
+	info->pasid_table = pasid_table;
 
 	return 0;
 }
@@ -202,10 +142,7 @@ void intel_pasid_free_table(struct device *dev)
 		return;
 
 	pasid_table = info->pasid_table;
-	device_detach_pasid_table(info, pasid_table);
-
-	if (!list_empty(&pasid_table->dev))
-		return;
+	info->pasid_table = NULL;
 
 	/* Free scalable mode PASID directory tables: */
 	dir = pasid_table->table;
diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h
index 583ea67fc7836..bf5b937848b41 100644
--- a/drivers/iommu/intel/pasid.h
+++ b/drivers/iommu/intel/pasid.h
@@ -74,7 +74,6 @@ struct pasid_table {
 	void			*table;		/* pasid table pointer */
 	int			order;		/* page order of pasid table */
 	u32			max_pasid;	/* max pasid */
-	struct list_head	dev;		/* device list */
 };
 
 /* Get PRESENT bit of a PASID directory entry. */
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index 4f29139bbfc39..5fcf89faa31ab 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -612,7 +612,6 @@ struct intel_iommu {
 struct device_domain_info {
 	struct list_head link;	/* link to domain siblings */
 	struct list_head global; /* link to global list */
-	struct list_head table;	/* link to pasid table */
 	u32 segment;		/* PCI segment number */
 	u8 bus;			/* PCI bus number */
 	u8 devfn;		/* PCI devfn number */
@@ -729,8 +728,6 @@ extern int dmar_ir_support(void);
 void *alloc_pgtable_page(int node);
 void free_pgtable_page(void *vaddr);
 struct intel_iommu *domain_get_iommu(struct dmar_domain *domain);
-int for_each_device_domain(int (*fn)(struct device_domain_info *info,
-				     void *data), void *data);
 void iommu_flush_write_buffer(struct intel_iommu *iommu);
 int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct device *dev);
 struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn);
-- 
GitLab


From 052f744f44462cc49b88a125b0f7b93a9e47a9dd Mon Sep 17 00:00:00 2001
From: Vlad Buslov <vladbu@nvidia.com>
Date: Mon, 4 Jul 2022 22:44:04 +0200
Subject: [PATCH 1605/1731] net/sched: act_police: allow 'continue' action
 offload

Offloading police with action TC_ACT_UNSPEC was erroneously disabled even
though it was supported by mlx5 matchall offload implementation, which
didn't verify the action type but instead assumed that any single police
action attached to matchall classifier is a 'continue' action. Lack of
action type check made it non-obvious what mlx5 matchall implementation
actually supports and caused implementers and reviewers of referenced
commits to disallow it as a part of improved validation code.

Fixes: b8cd5831c61c ("net: flow_offload: add tc police action parameters")
Fixes: b50e462bc22d ("net/sched: act_police: Add extack messages for offload failure")
Signed-off-by: Vlad Buslov <vladbu@nvidia.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Tested-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 include/net/flow_offload.h | 1 +
 net/sched/act_police.c     | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/net/flow_offload.h b/include/net/flow_offload.h
index 6484095a8c011..7ac313858037a 100644
--- a/include/net/flow_offload.h
+++ b/include/net/flow_offload.h
@@ -152,6 +152,7 @@ enum flow_action_id {
 	FLOW_ACTION_PIPE,
 	FLOW_ACTION_VLAN_PUSH_ETH,
 	FLOW_ACTION_VLAN_POP_ETH,
+	FLOW_ACTION_CONTINUE,
 	NUM_FLOW_ACTIONS,
 };
 
diff --git a/net/sched/act_police.c b/net/sched/act_police.c
index 79c8901f66ab1..b759628a47c20 100644
--- a/net/sched/act_police.c
+++ b/net/sched/act_police.c
@@ -442,7 +442,7 @@ static int tcf_police_act_to_flow_act(int tc_act, u32 *extval,
 		act_id = FLOW_ACTION_JUMP;
 		*extval = tc_act & TC_ACT_EXT_VAL_MASK;
 	} else if (tc_act == TC_ACT_UNSPEC) {
-		NL_SET_ERR_MSG_MOD(extack, "Offload not supported when conform/exceed action is \"continue\"");
+		act_id = FLOW_ACTION_CONTINUE;
 	} else {
 		NL_SET_ERR_MSG_MOD(extack, "Unsupported conform/exceed action offload");
 	}
-- 
GitLab


From 4d1e07d83ccc87f210e5b852b0a5ea812a2f191c Mon Sep 17 00:00:00 2001
From: Vlad Buslov <vladbu@nvidia.com>
Date: Mon, 4 Jul 2022 22:44:05 +0200
Subject: [PATCH 1606/1731] net/mlx5e: Fix matchall police parameters
 validation

Referenced commit prepared the code for upcoming extension that allows mlx5
to offload police action attached to flower classifier. However, with
regard to existing matchall classifier offload validation should be
reversed as FLOW_ACTION_CONTINUE is the only supported notexceed police
action type. Fix the problem by allowing FLOW_ACTION_CONTINUE for police
action and extend scan_tc_matchall_fdb_actions() to only allow such actions
with matchall classifier.

Fixes: d97b4b105ce7 ("flow_offload: reject offload for all drivers with invalid police parameters")
Signed-off-by: Vlad Buslov <vladbu@nvidia.com>
Acked-by: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
index 34bf11cdf90fc..3a39a50146ddf 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
@@ -4529,13 +4529,6 @@ static int mlx5e_policer_validate(const struct flow_action *action,
 		return -EOPNOTSUPP;
 	}
 
-	if (act->police.notexceed.act_id != FLOW_ACTION_PIPE &&
-	    act->police.notexceed.act_id != FLOW_ACTION_ACCEPT) {
-		NL_SET_ERR_MSG_MOD(extack,
-				   "Offload not supported when conform action is not pipe or ok");
-		return -EOPNOTSUPP;
-	}
-
 	if (act->police.notexceed.act_id == FLOW_ACTION_ACCEPT &&
 	    !flow_action_is_last_entry(action, act)) {
 		NL_SET_ERR_MSG_MOD(extack,
@@ -4586,6 +4579,12 @@ static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
 	flow_action_for_each(i, act, flow_action) {
 		switch (act->id) {
 		case FLOW_ACTION_POLICE:
+			if (act->police.notexceed.act_id != FLOW_ACTION_CONTINUE) {
+				NL_SET_ERR_MSG_MOD(extack,
+						   "Offload not supported when conform action is not continue");
+				return -EOPNOTSUPP;
+			}
+
 			err = mlx5e_policer_validate(flow_action, act, extack);
 			if (err)
 				return err;
-- 
GitLab


From 5ccecaec5c1e85cabfda848c6f146da0d8d55bd6 Mon Sep 17 00:00:00 2001
From: Paolo Abeni <pabeni@redhat.com>
Date: Tue, 5 Jul 2022 14:32:11 -0700
Subject: [PATCH 1607/1731] mptcp: fix locking in mptcp_nl_cmd_sf_destroy()

The user-space PM subflow removal path uses a couple of helpers
that must be called under the msk socket lock and the current
code lacks such requirement.

Change the existing lock scope so that the relevant code is under
its protection.

Fixes: 702c2f646d42 ("mptcp: netlink: allow userspace-driven subflow establishment")
Closes: https://github.com/multipath-tcp/mptcp_net-next/issues/287
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/mptcp/pm_userspace.c | 19 ++++++-------------
 1 file changed, 6 insertions(+), 13 deletions(-)

diff --git a/net/mptcp/pm_userspace.c b/net/mptcp/pm_userspace.c
index f56378e4f5977..26212bebc5ed2 100644
--- a/net/mptcp/pm_userspace.c
+++ b/net/mptcp/pm_userspace.c
@@ -306,15 +306,11 @@ static struct sock *mptcp_nl_find_ssk(struct mptcp_sock *msk,
 				      const struct mptcp_addr_info *local,
 				      const struct mptcp_addr_info *remote)
 {
-	struct sock *sk = &msk->sk.icsk_inet.sk;
 	struct mptcp_subflow_context *subflow;
-	struct sock *found = NULL;
 
 	if (local->family != remote->family)
 		return NULL;
 
-	lock_sock(sk);
-
 	mptcp_for_each_subflow(msk, subflow) {
 		const struct inet_sock *issk;
 		struct sock *ssk;
@@ -347,16 +343,11 @@ static struct sock *mptcp_nl_find_ssk(struct mptcp_sock *msk,
 		}
 
 		if (issk->inet_sport == local->port &&
-		    issk->inet_dport == remote->port) {
-			found = ssk;
-			goto found;
-		}
+		    issk->inet_dport == remote->port)
+			return ssk;
 	}
 
-found:
-	release_sock(sk);
-
-	return found;
+	return NULL;
 }
 
 int mptcp_nl_cmd_sf_destroy(struct sk_buff *skb, struct genl_info *info)
@@ -412,6 +403,7 @@ int mptcp_nl_cmd_sf_destroy(struct sk_buff *skb, struct genl_info *info)
 	}
 
 	sk = &msk->sk.icsk_inet.sk;
+	lock_sock(sk);
 	ssk = mptcp_nl_find_ssk(msk, &addr_l, &addr_r);
 	if (ssk) {
 		struct mptcp_subflow_context *subflow = mptcp_subflow_ctx(ssk);
@@ -422,8 +414,9 @@ int mptcp_nl_cmd_sf_destroy(struct sk_buff *skb, struct genl_info *info)
 	} else {
 		err = -ESRCH;
 	}
+	release_sock(sk);
 
- destroy_err:
+destroy_err:
 	sock_put((struct sock *)msk);
 	return err;
 }
-- 
GitLab


From c21b50d5912b68c4414c60ef5b30416c103f9fd8 Mon Sep 17 00:00:00 2001
From: Mat Martineau <mathew.j.martineau@linux.intel.com>
Date: Tue, 5 Jul 2022 14:32:12 -0700
Subject: [PATCH 1608/1731] mptcp: Avoid acquiring PM lock for subflow priority
 changes

The in-kernel path manager code for changing subflow flags acquired both
the msk socket lock and the PM lock when possibly changing the "backup"
and "fullmesh" flags. mptcp_pm_nl_mp_prio_send_ack() does not access
anything protected by the PM lock, and it must release and reacquire
the PM lock.

By pushing the PM lock to where it is needed in mptcp_pm_nl_fullmesh(),
the lock is only acquired when the fullmesh flag is changed and the
backup flag code no longer has to release and reacquire the PM lock. The
change in locking context requires the MIB update to be modified - move
that to a better location instead.

This change also makes it possible to call
mptcp_pm_nl_mp_prio_send_ack() for the userspace PM commands without
manipulating the in-kernel PM lock.

Fixes: 0f9f696a502e ("mptcp: add set_flags command in PM netlink")
Acked-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/mptcp/options.c    | 3 +++
 net/mptcp/pm_netlink.c | 8 ++------
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/net/mptcp/options.c b/net/mptcp/options.c
index aead331866a0c..bd8f0f425be4c 100644
--- a/net/mptcp/options.c
+++ b/net/mptcp/options.c
@@ -1584,6 +1584,9 @@ mp_rst:
 		*ptr++ = mptcp_option(MPTCPOPT_MP_PRIO,
 				      TCPOLEN_MPTCP_PRIO,
 				      opts->backup, TCPOPT_NOP);
+
+		MPTCP_INC_STATS(sock_net((const struct sock *)tp),
+				MPTCP_MIB_MPPRIOTX);
 	}
 
 mp_capable_done:
diff --git a/net/mptcp/pm_netlink.c b/net/mptcp/pm_netlink.c
index e099f2a12504a..5ff93b73f33d0 100644
--- a/net/mptcp/pm_netlink.c
+++ b/net/mptcp/pm_netlink.c
@@ -727,7 +727,6 @@ static int mptcp_pm_nl_mp_prio_send_ack(struct mptcp_sock *msk,
 
 	mptcp_for_each_subflow(msk, subflow) {
 		struct sock *ssk = mptcp_subflow_tcp_sock(subflow);
-		struct sock *sk = (struct sock *)msk;
 		struct mptcp_addr_info local;
 
 		local_address((struct sock_common *)ssk, &local);
@@ -739,12 +738,9 @@ static int mptcp_pm_nl_mp_prio_send_ack(struct mptcp_sock *msk,
 		subflow->backup = bkup;
 		subflow->send_mp_prio = 1;
 		subflow->request_bkup = bkup;
-		__MPTCP_INC_STATS(sock_net(sk), MPTCP_MIB_MPPRIOTX);
 
-		spin_unlock_bh(&msk->pm.lock);
 		pr_debug("send ack for mp_prio");
 		mptcp_subflow_send_ack(ssk);
-		spin_lock_bh(&msk->pm.lock);
 
 		return 0;
 	}
@@ -1816,8 +1812,10 @@ static void mptcp_pm_nl_fullmesh(struct mptcp_sock *msk,
 
 	list.ids[list.nr++] = addr->id;
 
+	spin_lock_bh(&msk->pm.lock);
 	mptcp_pm_nl_rm_subflow_received(msk, &list);
 	mptcp_pm_create_subflow_or_signal_addr(msk);
+	spin_unlock_bh(&msk->pm.lock);
 }
 
 static int mptcp_nl_set_flags(struct net *net,
@@ -1835,12 +1833,10 @@ static int mptcp_nl_set_flags(struct net *net,
 			goto next;
 
 		lock_sock(sk);
-		spin_lock_bh(&msk->pm.lock);
 		if (changed & MPTCP_PM_ADDR_FLAG_BACKUP)
 			ret = mptcp_pm_nl_mp_prio_send_ack(msk, addr, bkup);
 		if (changed & MPTCP_PM_ADDR_FLAG_FULLMESH)
 			mptcp_pm_nl_fullmesh(msk, addr);
-		spin_unlock_bh(&msk->pm.lock);
 		release_sock(sk);
 
 next:
-- 
GitLab


From a657430260e5437df16004c8c317821d946b5ead Mon Sep 17 00:00:00 2001
From: Mat Martineau <mathew.j.martineau@linux.intel.com>
Date: Tue, 5 Jul 2022 14:32:13 -0700
Subject: [PATCH 1609/1731] mptcp: Acquire the subflow socket lock before
 modifying MP_PRIO flags

When setting up a subflow's flags for sending MP_PRIO MPTCP options, the
subflow socket lock was not held while reading and modifying several
struct members that are also read and modified in mptcp_write_options().

Acquire the subflow socket lock earlier and send the MP_PRIO ACK with
that lock already acquired. Add a new variant of the
mptcp_subflow_send_ack() helper to use with the subflow lock held.

Fixes: 067065422fcd ("mptcp: add the outgoing MP_PRIO support")
Acked-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/mptcp/pm_netlink.c | 5 ++++-
 net/mptcp/protocol.c   | 9 +++++++--
 net/mptcp/protocol.h   | 1 +
 3 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/net/mptcp/pm_netlink.c b/net/mptcp/pm_netlink.c
index 5ff93b73f33d0..ca86c88f89e03 100644
--- a/net/mptcp/pm_netlink.c
+++ b/net/mptcp/pm_netlink.c
@@ -728,11 +728,13 @@ static int mptcp_pm_nl_mp_prio_send_ack(struct mptcp_sock *msk,
 	mptcp_for_each_subflow(msk, subflow) {
 		struct sock *ssk = mptcp_subflow_tcp_sock(subflow);
 		struct mptcp_addr_info local;
+		bool slow;
 
 		local_address((struct sock_common *)ssk, &local);
 		if (!mptcp_addresses_equal(&local, addr, addr->port))
 			continue;
 
+		slow = lock_sock_fast(ssk);
 		if (subflow->backup != bkup)
 			msk->last_snd = NULL;
 		subflow->backup = bkup;
@@ -740,7 +742,8 @@ static int mptcp_pm_nl_mp_prio_send_ack(struct mptcp_sock *msk,
 		subflow->request_bkup = bkup;
 
 		pr_debug("send ack for mp_prio");
-		mptcp_subflow_send_ack(ssk);
+		__mptcp_subflow_send_ack(ssk);
+		unlock_sock_fast(ssk, slow);
 
 		return 0;
 	}
diff --git a/net/mptcp/protocol.c b/net/mptcp/protocol.c
index e475212f2618b..cc21fafd97265 100644
--- a/net/mptcp/protocol.c
+++ b/net/mptcp/protocol.c
@@ -506,13 +506,18 @@ static inline bool tcp_can_send_ack(const struct sock *ssk)
 	       (TCPF_SYN_SENT | TCPF_SYN_RECV | TCPF_TIME_WAIT | TCPF_CLOSE | TCPF_LISTEN));
 }
 
+void __mptcp_subflow_send_ack(struct sock *ssk)
+{
+	if (tcp_can_send_ack(ssk))
+		tcp_send_ack(ssk);
+}
+
 void mptcp_subflow_send_ack(struct sock *ssk)
 {
 	bool slow;
 
 	slow = lock_sock_fast(ssk);
-	if (tcp_can_send_ack(ssk))
-		tcp_send_ack(ssk);
+	__mptcp_subflow_send_ack(ssk);
 	unlock_sock_fast(ssk, slow);
 }
 
diff --git a/net/mptcp/protocol.h b/net/mptcp/protocol.h
index c14d70c036d0e..033c995772dc6 100644
--- a/net/mptcp/protocol.h
+++ b/net/mptcp/protocol.h
@@ -607,6 +607,7 @@ void __init mptcp_subflow_init(void);
 void mptcp_subflow_shutdown(struct sock *sk, struct sock *ssk, int how);
 void mptcp_close_ssk(struct sock *sk, struct sock *ssk,
 		     struct mptcp_subflow_context *subflow);
+void __mptcp_subflow_send_ack(struct sock *ssk);
 void mptcp_subflow_send_ack(struct sock *ssk);
 void mptcp_subflow_reset(struct sock *ssk);
 void mptcp_subflow_queue_clean(struct sock *ssk);
-- 
GitLab


From 892f396c8e68faab7f76ff49cf39e9fbbeea4097 Mon Sep 17 00:00:00 2001
From: Kishen Maloor <kishen.maloor@intel.com>
Date: Tue, 5 Jul 2022 14:32:14 -0700
Subject: [PATCH 1610/1731] mptcp: netlink: issue MP_PRIO signals from
 userspace PMs

This change updates MPTCP_PM_CMD_SET_FLAGS to allow userspace PMs
to issue MP_PRIO signals over a specific subflow selected by
the connection token, local and remote address+port.

Closes: https://github.com/multipath-tcp/mptcp_net-next/issues/286
Fixes: 702c2f646d42 ("mptcp: netlink: allow userspace-driven subflow establishment")
Acked-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Kishen Maloor <kishen.maloor@intel.com>
Signed-off-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/mptcp/pm_netlink.c   | 30 +++++++++++++++++++++++++-----
 net/mptcp/pm_userspace.c | 30 ++++++++++++++++++++++++++++++
 net/mptcp/protocol.h     |  8 +++++++-
 3 files changed, 62 insertions(+), 6 deletions(-)

diff --git a/net/mptcp/pm_netlink.c b/net/mptcp/pm_netlink.c
index ca86c88f89e03..2da251dd7c00b 100644
--- a/net/mptcp/pm_netlink.c
+++ b/net/mptcp/pm_netlink.c
@@ -717,9 +717,10 @@ void mptcp_pm_nl_addr_send_ack(struct mptcp_sock *msk)
 	}
 }
 
-static int mptcp_pm_nl_mp_prio_send_ack(struct mptcp_sock *msk,
-					struct mptcp_addr_info *addr,
-					u8 bkup)
+int mptcp_pm_nl_mp_prio_send_ack(struct mptcp_sock *msk,
+				 struct mptcp_addr_info *addr,
+				 struct mptcp_addr_info *rem,
+				 u8 bkup)
 {
 	struct mptcp_subflow_context *subflow;
 
@@ -727,13 +728,19 @@ static int mptcp_pm_nl_mp_prio_send_ack(struct mptcp_sock *msk,
 
 	mptcp_for_each_subflow(msk, subflow) {
 		struct sock *ssk = mptcp_subflow_tcp_sock(subflow);
-		struct mptcp_addr_info local;
+		struct mptcp_addr_info local, remote;
 		bool slow;
 
 		local_address((struct sock_common *)ssk, &local);
 		if (!mptcp_addresses_equal(&local, addr, addr->port))
 			continue;
 
+		if (rem && rem->family != AF_UNSPEC) {
+			remote_address((struct sock_common *)ssk, &remote);
+			if (!mptcp_addresses_equal(&remote, rem, rem->port))
+				continue;
+		}
+
 		slow = lock_sock_fast(ssk);
 		if (subflow->backup != bkup)
 			msk->last_snd = NULL;
@@ -1837,7 +1844,7 @@ static int mptcp_nl_set_flags(struct net *net,
 
 		lock_sock(sk);
 		if (changed & MPTCP_PM_ADDR_FLAG_BACKUP)
-			ret = mptcp_pm_nl_mp_prio_send_ack(msk, addr, bkup);
+			ret = mptcp_pm_nl_mp_prio_send_ack(msk, addr, NULL, bkup);
 		if (changed & MPTCP_PM_ADDR_FLAG_FULLMESH)
 			mptcp_pm_nl_fullmesh(msk, addr);
 		release_sock(sk);
@@ -1853,6 +1860,9 @@ next:
 static int mptcp_nl_cmd_set_flags(struct sk_buff *skb, struct genl_info *info)
 {
 	struct mptcp_pm_addr_entry addr = { .addr = { .family = AF_UNSPEC }, }, *entry;
+	struct mptcp_pm_addr_entry remote = { .addr = { .family = AF_UNSPEC }, };
+	struct nlattr *attr_rem = info->attrs[MPTCP_PM_ATTR_ADDR_REMOTE];
+	struct nlattr *token = info->attrs[MPTCP_PM_ATTR_TOKEN];
 	struct nlattr *attr = info->attrs[MPTCP_PM_ATTR_ADDR];
 	struct pm_nl_pernet *pernet = genl_info_pm_nl(info);
 	u8 changed, mask = MPTCP_PM_ADDR_FLAG_BACKUP |
@@ -1865,6 +1875,12 @@ static int mptcp_nl_cmd_set_flags(struct sk_buff *skb, struct genl_info *info)
 	if (ret < 0)
 		return ret;
 
+	if (attr_rem) {
+		ret = mptcp_pm_parse_entry(attr_rem, info, false, &remote);
+		if (ret < 0)
+			return ret;
+	}
+
 	if (addr.flags & MPTCP_PM_ADDR_FLAG_BACKUP)
 		bkup = 1;
 	if (addr.addr.family == AF_UNSPEC) {
@@ -1873,6 +1889,10 @@ static int mptcp_nl_cmd_set_flags(struct sk_buff *skb, struct genl_info *info)
 			return -EOPNOTSUPP;
 	}
 
+	if (token)
+		return mptcp_userspace_pm_set_flags(sock_net(skb->sk),
+						    token, &addr, &remote, bkup);
+
 	spin_lock_bh(&pernet->lock);
 	entry = __lookup_addr(pernet, &addr.addr, lookup_by_id);
 	if (!entry) {
diff --git a/net/mptcp/pm_userspace.c b/net/mptcp/pm_userspace.c
index 26212bebc5ed2..51e2f066d54f0 100644
--- a/net/mptcp/pm_userspace.c
+++ b/net/mptcp/pm_userspace.c
@@ -420,3 +420,33 @@ destroy_err:
 	sock_put((struct sock *)msk);
 	return err;
 }
+
+int mptcp_userspace_pm_set_flags(struct net *net, struct nlattr *token,
+				 struct mptcp_pm_addr_entry *loc,
+				 struct mptcp_pm_addr_entry *rem, u8 bkup)
+{
+	struct mptcp_sock *msk;
+	int ret = -EINVAL;
+	u32 token_val;
+
+	token_val = nla_get_u32(token);
+
+	msk = mptcp_token_get_sock(net, token_val);
+	if (!msk)
+		return ret;
+
+	if (!mptcp_pm_is_userspace(msk))
+		goto set_flags_err;
+
+	if (loc->addr.family == AF_UNSPEC ||
+	    rem->addr.family == AF_UNSPEC)
+		goto set_flags_err;
+
+	lock_sock((struct sock *)msk);
+	ret = mptcp_pm_nl_mp_prio_send_ack(msk, &loc->addr, &rem->addr, bkup);
+	release_sock((struct sock *)msk);
+
+set_flags_err:
+	sock_put((struct sock *)msk);
+	return ret;
+}
diff --git a/net/mptcp/protocol.h b/net/mptcp/protocol.h
index 033c995772dc6..480c5320b86e5 100644
--- a/net/mptcp/protocol.h
+++ b/net/mptcp/protocol.h
@@ -772,6 +772,10 @@ void mptcp_pm_rm_addr_received(struct mptcp_sock *msk,
 			       const struct mptcp_rm_list *rm_list);
 void mptcp_pm_mp_prio_received(struct sock *sk, u8 bkup);
 void mptcp_pm_mp_fail_received(struct sock *sk, u64 fail_seq);
+int mptcp_pm_nl_mp_prio_send_ack(struct mptcp_sock *msk,
+				 struct mptcp_addr_info *addr,
+				 struct mptcp_addr_info *rem,
+				 u8 bkup);
 bool mptcp_pm_alloc_anno_list(struct mptcp_sock *msk,
 			      const struct mptcp_pm_addr_entry *entry);
 void mptcp_pm_free_anno_list(struct mptcp_sock *msk);
@@ -788,7 +792,9 @@ int mptcp_pm_get_flags_and_ifindex_by_id(struct mptcp_sock *msk,
 int mptcp_userspace_pm_get_flags_and_ifindex_by_id(struct mptcp_sock *msk,
 						   unsigned int id,
 						   u8 *flags, int *ifindex);
-
+int mptcp_userspace_pm_set_flags(struct net *net, struct nlattr *token,
+				 struct mptcp_pm_addr_entry *loc,
+				 struct mptcp_pm_addr_entry *rem, u8 bkup);
 int mptcp_pm_announce_addr(struct mptcp_sock *msk,
 			   const struct mptcp_addr_info *addr,
 			   bool echo);
-- 
GitLab


From ca188a25d43f85f9c6f1e0a303edad47c9d24989 Mon Sep 17 00:00:00 2001
From: Kishen Maloor <kishen.maloor@intel.com>
Date: Tue, 5 Jul 2022 14:32:15 -0700
Subject: [PATCH 1611/1731] selftests: mptcp: userspace PM support for MP_PRIO
 signals

This change updates the testing sample (pm_nl_ctl) to exercise
the updated MPTCP_PM_CMD_SET_FLAGS command for userspace PMs to
issue MP_PRIO signals over the selected subflow.

E.g. ./pm_nl_ctl set 10.0.1.2 port 47234 flags backup token 823274047 rip 10.0.1.1 rport 50003

userspace_pm.sh has a new selftest that invokes this command.

Fixes: 259a834fadda ("selftests: mptcp: functional tests for the userspace PM type")
Acked-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Kishen Maloor <kishen.maloor@intel.com>
Signed-off-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 tools/testing/selftests/net/mptcp/pm_nl_ctl.c | 73 ++++++++++++++++++-
 .../selftests/net/mptcp/userspace_pm.sh       | 32 ++++++++
 2 files changed, 103 insertions(+), 2 deletions(-)

diff --git a/tools/testing/selftests/net/mptcp/pm_nl_ctl.c b/tools/testing/selftests/net/mptcp/pm_nl_ctl.c
index 6a2f4b981e1d9..cb79f0719e3b5 100644
--- a/tools/testing/selftests/net/mptcp/pm_nl_ctl.c
+++ b/tools/testing/selftests/net/mptcp/pm_nl_ctl.c
@@ -39,7 +39,7 @@ static void syntax(char *argv[])
 	fprintf(stderr, "\tdsf lip <local-ip> lport <local-port> rip <remote-ip> rport <remote-port> token <token>\n");
 	fprintf(stderr, "\tdel <id> [<ip>]\n");
 	fprintf(stderr, "\tget <id>\n");
-	fprintf(stderr, "\tset [<ip>] [id <nr>] flags [no]backup|[no]fullmesh [port <nr>]\n");
+	fprintf(stderr, "\tset [<ip>] [id <nr>] flags [no]backup|[no]fullmesh [port <nr>] [token <token>] [rip <ip>] [rport <port>]\n");
 	fprintf(stderr, "\tflush\n");
 	fprintf(stderr, "\tdump\n");
 	fprintf(stderr, "\tlimits [<rcv addr max> <subflow max>]\n");
@@ -1279,7 +1279,10 @@ int set_flags(int fd, int pm_family, int argc, char *argv[])
 	struct rtattr *rta, *nest;
 	struct nlmsghdr *nh;
 	u_int32_t flags = 0;
+	u_int32_t token = 0;
+	u_int16_t rport = 0;
 	u_int16_t family;
+	void *rip = NULL;
 	int nest_start;
 	int use_id = 0;
 	u_int8_t id;
@@ -1339,7 +1342,13 @@ int set_flags(int fd, int pm_family, int argc, char *argv[])
 		error(1, 0, " missing flags keyword");
 
 	for (; arg < argc; arg++) {
-		if (!strcmp(argv[arg], "flags")) {
+		if (!strcmp(argv[arg], "token")) {
+			if (++arg >= argc)
+				error(1, 0, " missing token value");
+
+			/* token */
+			token = atoi(argv[arg]);
+		} else if (!strcmp(argv[arg], "flags")) {
 			char *tok, *str;
 
 			/* flags */
@@ -1378,12 +1387,72 @@ int set_flags(int fd, int pm_family, int argc, char *argv[])
 			rta->rta_len = RTA_LENGTH(2);
 			memcpy(RTA_DATA(rta), &port, 2);
 			off += NLMSG_ALIGN(rta->rta_len);
+		} else if (!strcmp(argv[arg], "rport")) {
+			if (++arg >= argc)
+				error(1, 0, " missing remote port");
+
+			rport = atoi(argv[arg]);
+		} else if (!strcmp(argv[arg], "rip")) {
+			if (++arg >= argc)
+				error(1, 0, " missing remote ip");
+
+			rip = argv[arg];
 		} else {
 			error(1, 0, "unknown keyword %s", argv[arg]);
 		}
 	}
 	nest->rta_len = off - nest_start;
 
+	/* token */
+	if (token) {
+		rta = (void *)(data + off);
+		rta->rta_type = MPTCP_PM_ATTR_TOKEN;
+		rta->rta_len = RTA_LENGTH(4);
+		memcpy(RTA_DATA(rta), &token, 4);
+		off += NLMSG_ALIGN(rta->rta_len);
+	}
+
+	/* remote addr/port */
+	if (rip) {
+		nest_start = off;
+		nest = (void *)(data + off);
+		nest->rta_type = NLA_F_NESTED | MPTCP_PM_ATTR_ADDR_REMOTE;
+		nest->rta_len = RTA_LENGTH(0);
+		off += NLMSG_ALIGN(nest->rta_len);
+
+		/* addr data */
+		rta = (void *)(data + off);
+		if (inet_pton(AF_INET, rip, RTA_DATA(rta))) {
+			family = AF_INET;
+			rta->rta_type = MPTCP_PM_ADDR_ATTR_ADDR4;
+			rta->rta_len = RTA_LENGTH(4);
+		} else if (inet_pton(AF_INET6, rip, RTA_DATA(rta))) {
+			family = AF_INET6;
+			rta->rta_type = MPTCP_PM_ADDR_ATTR_ADDR6;
+			rta->rta_len = RTA_LENGTH(16);
+		} else {
+			error(1, errno, "can't parse ip %s", (char *)rip);
+		}
+		off += NLMSG_ALIGN(rta->rta_len);
+
+		/* family */
+		rta = (void *)(data + off);
+		rta->rta_type = MPTCP_PM_ADDR_ATTR_FAMILY;
+		rta->rta_len = RTA_LENGTH(2);
+		memcpy(RTA_DATA(rta), &family, 2);
+		off += NLMSG_ALIGN(rta->rta_len);
+
+		if (rport) {
+			rta = (void *)(data + off);
+			rta->rta_type = MPTCP_PM_ADDR_ATTR_PORT;
+			rta->rta_len = RTA_LENGTH(2);
+			memcpy(RTA_DATA(rta), &rport, 2);
+			off += NLMSG_ALIGN(rta->rta_len);
+		}
+
+		nest->rta_len = off - nest_start;
+	}
+
 	do_nl_req(fd, nh, off, 0);
 	return 0;
 }
diff --git a/tools/testing/selftests/net/mptcp/userspace_pm.sh b/tools/testing/selftests/net/mptcp/userspace_pm.sh
index 78d0bb640b117..abe3d4ebe5549 100755
--- a/tools/testing/selftests/net/mptcp/userspace_pm.sh
+++ b/tools/testing/selftests/net/mptcp/userspace_pm.sh
@@ -770,10 +770,42 @@ test_subflows()
 	rm -f "$evts"
 }
 
+test_prio()
+{
+	local count
+
+	# Send MP_PRIO signal from client to server machine
+	ip netns exec "$ns2" ./pm_nl_ctl set 10.0.1.2 port "$client4_port" flags backup token "$client4_token" rip 10.0.1.1 rport "$server4_port"
+	sleep 0.5
+
+	# Check TX
+	stdbuf -o0 -e0 printf "MP_PRIO TX                                                 \t"
+	count=$(ip netns exec "$ns2" nstat -as | grep MPTcpExtMPPrioTx | awk '{print $2}')
+	[ -z "$count" ] && count=0
+	if [ $count != 1 ]; then
+		stdbuf -o0 -e0 printf "[FAIL]\n"
+		exit 1
+	else
+		stdbuf -o0 -e0 printf "[OK]\n"
+	fi
+
+	# Check RX
+	stdbuf -o0 -e0 printf "MP_PRIO RX                                                 \t"
+	count=$(ip netns exec "$ns1" nstat -as | grep MPTcpExtMPPrioRx | awk '{print $2}')
+	[ -z "$count" ] && count=0
+	if [ $count != 1 ]; then
+		stdbuf -o0 -e0 printf "[FAIL]\n"
+		exit 1
+	else
+		stdbuf -o0 -e0 printf "[OK]\n"
+	fi
+}
+
 make_connection
 make_connection "v6"
 test_announce
 test_remove
 test_subflows
+test_prio
 
 exit 0
-- 
GitLab


From 843b5e75efff04db34fcf9856de53c9e415530a2 Mon Sep 17 00:00:00 2001
From: Paolo Abeni <pabeni@redhat.com>
Date: Tue, 5 Jul 2022 14:32:16 -0700
Subject: [PATCH 1612/1731] mptcp: fix local endpoint accounting

In mptcp_pm_nl_rm_addr_or_subflow() we always mark as available
the id corresponding to the just removed address.

The used bitmap actually tracks only the local IDs: we must
restrict the operation when a (local) subflow is removed.

Fixes: a88c9e496937 ("mptcp: do not block subflows creation on errors")
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/mptcp/pm_netlink.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/net/mptcp/pm_netlink.c b/net/mptcp/pm_netlink.c
index 2da251dd7c00b..7c7395b589449 100644
--- a/net/mptcp/pm_netlink.c
+++ b/net/mptcp/pm_netlink.c
@@ -807,7 +807,8 @@ static void mptcp_pm_nl_rm_addr_or_subflow(struct mptcp_sock *msk,
 			removed = true;
 			__MPTCP_INC_STATS(sock_net(sk), rm_type);
 		}
-		__set_bit(rm_list->ids[i], msk->pm.id_avail_bitmap);
+		if (rm_type == MPTCP_MIB_RMSUBFLOW)
+			__set_bit(rm_list->ids[i], msk->pm.id_avail_bitmap);
 		if (!removed)
 			continue;
 
-- 
GitLab


From d2d21f175f1f9580eb5681f5b476c8d7a0a3c895 Mon Sep 17 00:00:00 2001
From: Geliang Tang <geliang.tang@suse.com>
Date: Tue, 5 Jul 2022 14:32:17 -0700
Subject: [PATCH 1613/1731] mptcp: update MIB_RMSUBFLOW in cmd_sf_destroy

This patch increases MPTCP_MIB_RMSUBFLOW mib counter in userspace pm
destroy subflow function mptcp_nl_cmd_sf_destroy() when removing subflow.

Fixes: 702c2f646d42 ("mptcp: netlink: allow userspace-driven subflow establishment")
Signed-off-by: Geliang Tang <geliang.tang@suse.com>
Signed-off-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/mptcp/pm_userspace.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/net/mptcp/pm_userspace.c b/net/mptcp/pm_userspace.c
index 51e2f066d54f0..9e82250cbb703 100644
--- a/net/mptcp/pm_userspace.c
+++ b/net/mptcp/pm_userspace.c
@@ -5,6 +5,7 @@
  */
 
 #include "protocol.h"
+#include "mib.h"
 
 void mptcp_free_local_addr_list(struct mptcp_sock *msk)
 {
@@ -410,6 +411,7 @@ int mptcp_nl_cmd_sf_destroy(struct sk_buff *skb, struct genl_info *info)
 
 		mptcp_subflow_shutdown(sk, ssk, RCV_SHUTDOWN | SEND_SHUTDOWN);
 		mptcp_close_ssk(sk, ssk, subflow);
+		MPTCP_INC_STATS(sock_net(sk), MPTCP_MIB_RMSUBFLOW);
 		err = 0;
 	} else {
 		err = -ESRCH;
-- 
GitLab


From a069a90554168ac4cc81af65f000557d2a8a0745 Mon Sep 17 00:00:00 2001
From: Gal Pressman <gal@nvidia.com>
Date: Tue, 5 Jul 2022 14:08:37 +0300
Subject: [PATCH 1614/1731] Revert "tls: rx: move counting TlsDecryptErrors for
 sync"

This reverts commit 284b4d93daee56dff3e10029ddf2e03227f50dbf.
When using TLS device offload and coming from tls_device_reencrypt()
flow, -EBADMSG error in tls_do_decryption() should not be counted
towards the TLSTlsDecryptError counter.

Move the counter increase back to the decrypt_internal() call site in
decrypt_skb_update().
This also fixes an issue where:
	if (n_sgin < 1)
		return -EBADMSG;

Errors in decrypt_internal() were not counted after the cited patch.

Fixes: 284b4d93daee ("tls: rx: move counting TlsDecryptErrors for sync")
Cc: Jakub Kicinski <kuba@kernel.org>
Reviewed-by: Maxim Mikityanskiy <maximmi@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Signed-off-by: Gal Pressman <gal@nvidia.com>
Reviewed-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/tls/tls_sw.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/net/tls/tls_sw.c b/net/tls/tls_sw.c
index 0513f82b8537e..e30649f6dde5e 100644
--- a/net/tls/tls_sw.c
+++ b/net/tls/tls_sw.c
@@ -267,9 +267,6 @@ static int tls_do_decryption(struct sock *sk,
 	}
 	darg->async = false;
 
-	if (ret == -EBADMSG)
-		TLS_INC_STATS(sock_net(sk), LINUX_MIB_TLSDECRYPTERROR);
-
 	return ret;
 }
 
@@ -1579,8 +1576,11 @@ static int decrypt_skb_update(struct sock *sk, struct sk_buff *skb,
 	}
 
 	err = decrypt_internal(sk, skb, dest, NULL, darg);
-	if (err < 0)
+	if (err < 0) {
+		if (err == -EBADMSG)
+			TLS_INC_STATS(sock_net(sk), LINUX_MIB_TLSDECRYPTERROR);
 		return err;
+	}
 	if (darg->async)
 		goto decrypt_next;
 
-- 
GitLab


From b992131aac655ac451d4078d83c5a3b4a28ea802 Mon Sep 17 00:00:00 2001
From: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Date: Tue, 5 Jul 2022 18:25:26 +0800
Subject: [PATCH 1615/1731] drm/mediatek: dpi: Add YUV422 output support

Dp_intf supports YUV422 as output format. In MT8195 Chrome project,
YUV422 output format is used for 4K resolution.

To support this, it is also needed to support color format transfer.
Color format transfer is a new feature for both dpi and dpintf of MT8195.

The input format could be RGB888 and output format for dp_intf should be
YUV422. Therefore, we add a mtk_dpi_matrix_sel() helper to update the
DPI_MATRIX_SET register depending on the color format.

Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220705102530.1344-2-rex-bc.chen@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c      | 31 +++++++++++++++++++------
 drivers/gpu/drm/mediatek/mtk_dpi_regs.h |  6 +++++
 2 files changed, 30 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index ea8d866e67bc5..5ee74209a279c 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -54,7 +54,8 @@ enum mtk_dpi_out_channel_swap {
 };
 
 enum mtk_dpi_out_color_format {
-	MTK_DPI_COLOR_FORMAT_RGB
+	MTK_DPI_COLOR_FORMAT_RGB,
+	MTK_DPI_COLOR_FORMAT_YCBCR_422
 };
 
 struct mtk_dpi {
@@ -409,12 +410,25 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
 					enum mtk_dpi_out_color_format format)
 {
-	/* only support RGB888 */
-	mtk_dpi_config_yuv422_enable(dpi, false);
-	mtk_dpi_config_csc_enable(dpi, false);
-	if (dpi->conf->swap_input_support)
-		mtk_dpi_config_swap_input(dpi, false);
 	mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB);
+
+	if (format == MTK_DPI_COLOR_FORMAT_YCBCR_422) {
+		mtk_dpi_config_yuv422_enable(dpi, true);
+		mtk_dpi_config_csc_enable(dpi, true);
+
+		/*
+		 * If height is smaller than 720, we need to use RGB_TO_BT601
+		 * to transfer to yuv422. Otherwise, we use RGB_TO_JPEG.
+		 */
+		mtk_dpi_mask(dpi, DPI_MATRIX_SET, dpi->mode.hdisplay <= 720 ?
+			     MATRIX_SEL_RGB_TO_BT601 : MATRIX_SEL_RGB_TO_JPEG,
+			     INT_MATRIX_SEL_MASK);
+	} else {
+		mtk_dpi_config_yuv422_enable(dpi, false);
+		mtk_dpi_config_csc_enable(dpi, false);
+		if (dpi->conf->swap_input_support)
+			mtk_dpi_config_swap_input(dpi, false);
+	}
 }
 
 static void mtk_dpi_dual_edge(struct mtk_dpi *dpi)
@@ -648,7 +662,10 @@ static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge,
 	dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS;
 	dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB;
 	dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB;
-	dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;
+	if (out_bus_format == MEDIA_BUS_FMT_YUYV8_1X16)
+		dpi->color_format = MTK_DPI_COLOR_FORMAT_YCBCR_422;
+	else
+		dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
index 3a02fabe16627..9ce300313f3ed 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
@@ -217,4 +217,10 @@
 
 #define EDGE_SEL_EN			BIT(5)
 #define H_FRE_2N			BIT(25)
+
+#define DPI_MATRIX_SET		0xB4
+#define INT_MATRIX_SEL_MASK		GENMASK(4, 0)
+#define MATRIX_SEL_RGB_TO_JPEG		0
+#define MATRIX_SEL_RGB_TO_BT601		2
+
 #endif /* __MTK_DPI_REGS_H */
-- 
GitLab


From c83da6233d05715a1e5841aa0b874faaa8150074 Mon Sep 17 00:00:00 2001
From: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Date: Tue, 5 Jul 2022 18:25:27 +0800
Subject: [PATCH 1616/1731] drm/mediatek: dpi: Add config to support direct
 connection to dpi panels

MediaTek dpi supports direct connection to dpi panels while dp_intf does
not support. Therefore, add a config "support_direct_pin" to control this.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220705102530.1344-3-rex-bc.chen@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 5ee74209a279c..fcdd050fca996 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -123,6 +123,7 @@ struct mtk_dpi_yc_limit {
  * @num_output_fmts: Quantity of supported output formats.
  * @is_ck_de_pol: Support CK/DE polarity.
  * @swap_input_support: Support input swap function.
+ * @support_direct_pin: IP supports direct connection to dpi panels.
  * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH
  *		    (no shift).
  * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift).
@@ -139,6 +140,7 @@ struct mtk_dpi_conf {
 	u32 num_output_fmts;
 	bool is_ck_de_pol;
 	bool swap_input_support;
+	bool support_direct_pin;
 	u32 dimension_mask;
 	u32 hvsize_mask;
 	u32 channel_swap_shift;
@@ -579,11 +581,13 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	mtk_dpi_config_channel_limit(dpi);
 	mtk_dpi_config_bit_num(dpi, dpi->bit_num);
 	mtk_dpi_config_channel_swap(dpi, dpi->channel_swap);
-	mtk_dpi_config_yc_map(dpi, dpi->yc_map);
 	mtk_dpi_config_color_format(dpi, dpi->color_format);
-	mtk_dpi_config_2n_h_fre(dpi);
-	mtk_dpi_dual_edge(dpi);
-	mtk_dpi_config_disable_edge(dpi);
+	if (dpi->conf->support_direct_pin) {
+		mtk_dpi_config_yc_map(dpi, dpi->yc_map);
+		mtk_dpi_config_2n_h_fre(dpi);
+		mtk_dpi_dual_edge(dpi);
+		mtk_dpi_config_disable_edge(dpi);
+	}
 	mtk_dpi_sw_reset(dpi, false);
 
 	return 0;
@@ -842,6 +846,7 @@ static const struct mtk_dpi_conf mt8173_conf = {
 	.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
 	.is_ck_de_pol = true,
 	.swap_input_support = true,
+	.support_direct_pin = true,
 	.dimension_mask = HPW_MASK,
 	.hvsize_mask = HSIZE_MASK,
 	.channel_swap_shift = CH_SWAP,
@@ -858,6 +863,7 @@ static const struct mtk_dpi_conf mt2701_conf = {
 	.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
 	.is_ck_de_pol = true,
 	.swap_input_support = true,
+	.support_direct_pin = true,
 	.dimension_mask = HPW_MASK,
 	.hvsize_mask = HSIZE_MASK,
 	.channel_swap_shift = CH_SWAP,
@@ -873,6 +879,7 @@ static const struct mtk_dpi_conf mt8183_conf = {
 	.num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
 	.is_ck_de_pol = true,
 	.swap_input_support = true,
+	.support_direct_pin = true,
 	.dimension_mask = HPW_MASK,
 	.hvsize_mask = HSIZE_MASK,
 	.channel_swap_shift = CH_SWAP,
@@ -888,6 +895,7 @@ static const struct mtk_dpi_conf mt8192_conf = {
 	.num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
 	.is_ck_de_pol = true,
 	.swap_input_support = true,
+	.support_direct_pin = true,
 	.dimension_mask = HPW_MASK,
 	.hvsize_mask = HSIZE_MASK,
 	.channel_swap_shift = CH_SWAP,
-- 
GitLab


From 2587d8951b2f0e20a5e4a1f79b33f0b0932fb917 Mon Sep 17 00:00:00 2001
From: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Date: Tue, 5 Jul 2022 18:25:28 +0800
Subject: [PATCH 1617/1731] drm/mediatek: dpi: Add input_2pixel config support

The input pixel per iteration could be different, so we add a new config
"input_2pixel" to control this.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220705102530.1344-4-rex-bc.chen@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c      | 7 +++++++
 drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index fcdd050fca996..5722fce06e39e 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -124,6 +124,8 @@ struct mtk_dpi_yc_limit {
  * @is_ck_de_pol: Support CK/DE polarity.
  * @swap_input_support: Support input swap function.
  * @support_direct_pin: IP supports direct connection to dpi panels.
+ * @input_2pixel: Input pixel of dp_intf is 2 pixel per round, so enable this
+ *		  config to enable this feature.
  * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH
  *		    (no shift).
  * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift).
@@ -141,6 +143,7 @@ struct mtk_dpi_conf {
 	bool is_ck_de_pol;
 	bool swap_input_support;
 	bool support_direct_pin;
+	bool input_2pixel;
 	u32 dimension_mask;
 	u32 hvsize_mask;
 	u32 channel_swap_shift;
@@ -588,6 +591,10 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 		mtk_dpi_dual_edge(dpi);
 		mtk_dpi_config_disable_edge(dpi);
 	}
+	if (dpi->conf->input_2pixel) {
+		mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN,
+			     DPINTF_INPUT_2P_EN);
+	}
 	mtk_dpi_sw_reset(dpi, false);
 
 	return 0;
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
index 9ce300313f3ed..305066577d417 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
@@ -40,6 +40,7 @@
 #define FAKE_DE_LEVEN			BIT(21)
 #define FAKE_DE_RODD			BIT(22)
 #define FAKE_DE_REVEN			BIT(23)
+#define DPINTF_INPUT_2P_EN		BIT(29)
 
 #define DPI_OUTPUT_SETTING	0x14
 #define CH_SWAP				0
-- 
GitLab


From 49ecbb78dda86f5551fb176bba9a31ec419c6365 Mon Sep 17 00:00:00 2001
From: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Date: Tue, 5 Jul 2022 18:25:29 +0800
Subject: [PATCH 1618/1731] drm/mediatek: dpi: Add pixels_per_iter config
 support

The quantity of output for one iteration could be different for dpi and
dp_intf. For dp_intf, it's 4 pixels for one iteration it's 1 pixel for one
iteration for dpi. Therefore, we add a new config "pixels_per_iter" to
control quantity of transferred pixels per iteration.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220705102530.1344-5-rex-bc.chen@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 26 +++++++++++++++++++++++---
 1 file changed, 23 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 5722fce06e39e..54c8839c5f232 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -132,6 +132,7 @@ struct mtk_dpi_yc_limit {
  * @channel_swap_shift: Shift value of channel swap.
  * @yuv422_en_bit: Enable bit of yuv422.
  * @csc_enable_bit: Enable bit of CSC.
+ * @pixels_per_iter: Quantity of transferred pixels per iteration.
  */
 struct mtk_dpi_conf {
 	unsigned int (*cal_factor)(int clock);
@@ -149,6 +150,7 @@ struct mtk_dpi_conf {
 	u32 channel_swap_shift;
 	u32 yuv422_en_bit;
 	u32 csc_enable_bit;
+	u32 pixels_per_iter;
 };
 
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -521,7 +523,14 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	clk_set_rate(dpi->tvd_clk, pll_rate);
 	pll_rate = clk_get_rate(dpi->tvd_clk);
 
+	/*
+	 * Depending on the IP version, we may output a different amount of
+	 * pixels for each iteration: divide the clock by this number and
+	 * adjust the display porches accordingly.
+	 */
 	vm.pixelclock = pll_rate / factor;
+	vm.pixelclock /= dpi->conf->pixels_per_iter;
+
 	if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
 	    (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE))
 		clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2);
@@ -540,9 +549,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 			    MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
 	dpi_pol.vsync_pol = vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ?
 			    MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
-	hsync.sync_width = vm.hsync_len;
-	hsync.back_porch = vm.hback_porch;
-	hsync.front_porch = vm.hfront_porch;
+
+	/*
+	 * Depending on the IP version, we may output a different amount of
+	 * pixels for each iteration: divide the clock by this number and
+	 * adjust the display porches accordingly.
+	 */
+	hsync.sync_width = vm.hsync_len / dpi->conf->pixels_per_iter;
+	hsync.back_porch = vm.hback_porch / dpi->conf->pixels_per_iter;
+	hsync.front_porch = vm.hfront_porch / dpi->conf->pixels_per_iter;
+
 	hsync.shift_half_line = false;
 	vsync_lodd.sync_width = vm.vsync_len;
 	vsync_lodd.back_porch = vm.vback_porch;
@@ -851,6 +867,7 @@ static const struct mtk_dpi_conf mt8173_conf = {
 	.max_clock_khz = 300000,
 	.output_fmts = mt8173_output_fmts,
 	.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
+	.pixels_per_iter = 1,
 	.is_ck_de_pol = true,
 	.swap_input_support = true,
 	.support_direct_pin = true,
@@ -868,6 +885,7 @@ static const struct mtk_dpi_conf mt2701_conf = {
 	.max_clock_khz = 150000,
 	.output_fmts = mt8173_output_fmts,
 	.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
+	.pixels_per_iter = 1,
 	.is_ck_de_pol = true,
 	.swap_input_support = true,
 	.support_direct_pin = true,
@@ -884,6 +902,7 @@ static const struct mtk_dpi_conf mt8183_conf = {
 	.max_clock_khz = 100000,
 	.output_fmts = mt8183_output_fmts,
 	.num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
+	.pixels_per_iter = 1,
 	.is_ck_de_pol = true,
 	.swap_input_support = true,
 	.support_direct_pin = true,
@@ -900,6 +919,7 @@ static const struct mtk_dpi_conf mt8192_conf = {
 	.max_clock_khz = 150000,
 	.output_fmts = mt8183_output_fmts,
 	.num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
+	.pixels_per_iter = 1,
 	.is_ck_de_pol = true,
 	.swap_input_support = true,
 	.support_direct_pin = true,
-- 
GitLab


From d86c1568910e7079e6ceb875d653e44293409194 Mon Sep 17 00:00:00 2001
From: Guillaume Ranquet <granquet@baylibre.com>
Date: Tue, 5 Jul 2022 18:25:30 +0800
Subject: [PATCH 1619/1731] drm/mediatek: dpi: Add dp_intf support

Dpintf is the displayport interface hardware unit. This unit is similar
to dpi and can reuse most of the code.

This patch adds support for mt8195-dpintf to this dpi driver. Main
differences are:
 - 4 pixels for one iteration for dp_intf while dpi is 1 pixel for one
   iteration.
 - Input of dp_intf is two pixels per iteration.
 - Some register contents differ slightly between the two components.

Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220705102530.1344-6-rex-bc.chen@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c          | 32 +++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_dpi_regs.h     | 11 +++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  4 +++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      |  3 ++
 5 files changed, 51 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 54c8839c5f232..fb0b797046369 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -852,6 +852,16 @@ static unsigned int mt8183_calculate_factor(int clock)
 		return 2;
 }
 
+static unsigned int mt8195_dpintf_calculate_factor(int clock)
+{
+	if (clock < 70000)
+		return 4;
+	else if (clock < 200000)
+		return 2;
+	else
+		return 1;
+}
+
 static const u32 mt8173_output_fmts[] = {
 	MEDIA_BUS_FMT_RGB888_1X24,
 };
@@ -861,6 +871,11 @@ static const u32 mt8183_output_fmts[] = {
 	MEDIA_BUS_FMT_RGB888_2X12_BE,
 };
 
+static const u32 mt8195_output_fmts[] = {
+	MEDIA_BUS_FMT_RGB888_1X24,
+	MEDIA_BUS_FMT_YUYV8_1X16,
+};
+
 static const struct mtk_dpi_conf mt8173_conf = {
 	.cal_factor = mt8173_calculate_factor,
 	.reg_h_fre_con = 0xe0,
@@ -930,6 +945,20 @@ static const struct mtk_dpi_conf mt8192_conf = {
 	.csc_enable_bit = CSC_ENABLE,
 };
 
+static const struct mtk_dpi_conf mt8195_dpintf_conf = {
+	.cal_factor = mt8195_dpintf_calculate_factor,
+	.max_clock_khz = 600000,
+	.output_fmts = mt8195_output_fmts,
+	.num_output_fmts = ARRAY_SIZE(mt8195_output_fmts),
+	.pixels_per_iter = 4,
+	.input_2pixel = true,
+	.dimension_mask = DPINTF_HPW_MASK,
+	.hvsize_mask = DPINTF_HSIZE_MASK,
+	.channel_swap_shift = DPINTF_CH_SWAP,
+	.yuv422_en_bit = DPINTF_YUV422_EN,
+	.csc_enable_bit = DPINTF_CSC_ENABLE,
+};
+
 static int mtk_dpi_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -1052,6 +1081,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
 	{ .compatible = "mediatek,mt8192-dpi",
 	  .data = &mt8192_conf,
 	},
+	{ .compatible = "mediatek,mt8195-dp-intf",
+	  .data = &mt8195_dpintf_conf,
+	},
 	{ },
 };
 MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
index 305066577d417..62bd4931b344e 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
@@ -40,10 +40,13 @@
 #define FAKE_DE_LEVEN			BIT(21)
 #define FAKE_DE_RODD			BIT(22)
 #define FAKE_DE_REVEN			BIT(23)
+#define DPINTF_YUV422_EN		BIT(24)
+#define DPINTF_CSC_ENABLE		BIT(26)
 #define DPINTF_INPUT_2P_EN		BIT(29)
 
 #define DPI_OUTPUT_SETTING	0x14
 #define CH_SWAP				0
+#define DPINTF_CH_SWAP			1
 #define CH_SWAP_MASK			(0x7 << 0)
 #define SWAP_RGB			0x00
 #define SWAP_GBR			0x01
@@ -81,8 +84,10 @@
 #define DPI_SIZE		0x18
 #define HSIZE				0
 #define HSIZE_MASK			(0x1FFF << 0)
+#define DPINTF_HSIZE_MASK		(0xFFFF << 0)
 #define VSIZE				16
 #define VSIZE_MASK			(0x1FFF << 16)
+#define DPINTF_VSIZE_MASK		(0xFFFF << 16)
 
 #define DPI_DDR_SETTING		0x1C
 #define DDR_EN				BIT(0)
@@ -94,24 +99,30 @@
 #define DPI_TGEN_HWIDTH		0x20
 #define HPW				0
 #define HPW_MASK			(0xFFF << 0)
+#define DPINTF_HPW_MASK			(0xFFFF << 0)
 
 #define DPI_TGEN_HPORCH		0x24
 #define HBP				0
 #define HBP_MASK			(0xFFF << 0)
+#define DPINTF_HBP_MASK			(0xFFFF << 0)
 #define HFP				16
 #define HFP_MASK			(0xFFF << 16)
+#define DPINTF_HFP_MASK			(0xFFFF << 16)
 
 #define DPI_TGEN_VWIDTH		0x28
 #define DPI_TGEN_VPORCH		0x2C
 
 #define VSYNC_WIDTH_SHIFT		0
 #define VSYNC_WIDTH_MASK		(0xFFF << 0)
+#define DPINTF_VSYNC_WIDTH_MASK		(0xFFFF << 0)
 #define VSYNC_HALF_LINE_SHIFT		16
 #define VSYNC_HALF_LINE_MASK		BIT(16)
 #define VSYNC_BACK_PORCH_SHIFT		0
 #define VSYNC_BACK_PORCH_MASK		(0xFFF << 0)
+#define DPINTF_VSYNC_BACK_PORCH_MASK	(0xFFFF << 0)
 #define VSYNC_FRONT_PORCH_SHIFT		16
 #define VSYNC_FRONT_PORCH_MASK		(0xFFF << 16)
+#define DPINTF_VSYNC_FRONT_PORCH_MASK	(0xFFFF << 16)
 
 #define DPI_BG_HCNTL		0x30
 #define BG_RIGHT			(0x1FFF << 0)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index a848ca7e167ae..2d72cc5ddaba4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -407,6 +407,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_RDMA] = "rdma",
 	[MTK_DISP_UFOE] = "ufoe",
 	[MTK_DISP_WDMA] = "wdma",
+	[MTK_DP_INTF] = "dp-intf",
 	[MTK_DPI] = "dpi",
 	[MTK_DSI] = "dsi",
 };
@@ -425,6 +426,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_COLOR0]		= { MTK_DISP_COLOR,	0, &ddp_color },
 	[DDP_COMPONENT_COLOR1]		= { MTK_DISP_COLOR,	1, &ddp_color },
 	[DDP_COMPONENT_DITHER0]		= { MTK_DISP_DITHER,	0, &ddp_dither },
+	[DDP_COMPONENT_DP_INTF0]	= { MTK_DP_INTF,	0, &ddp_dpi },
+	[DDP_COMPONENT_DP_INTF1]	= { MTK_DP_INTF,	1, &ddp_dpi },
 	[DDP_COMPONENT_DPI0]		= { MTK_DPI,		0, &ddp_dpi },
 	[DDP_COMPONENT_DPI1]		= { MTK_DPI,		1, &ddp_dpi },
 	[DDP_COMPONENT_DSC0]		= { MTK_DISP_DSC,	0, &ddp_dsc },
@@ -548,6 +551,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
 	    type == MTK_DISP_PWM ||
 	    type == MTK_DISP_RDMA ||
 	    type == MTK_DPI ||
+	    type == MTK_DP_INTF ||
 	    type == MTK_DSI)
 		return 0;
 
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index a43d82c12a9a7..2d0052c23dcbc 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_UFOE,
 	MTK_DISP_WDMA,
 	MTK_DPI,
+	MTK_DP_INTF,
 	MTK_DSI,
 	MTK_DDP_COMP_TYPE_MAX,
 };
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index e659dc84d7e51..0e4c77724b055 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -633,6 +633,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DPI },
 	{ .compatible = "mediatek,mt8192-dpi",
 	  .data = (void *)MTK_DPI },
+	{ .compatible = "mediatek,mt8195-dp-intf",
+	  .data = (void *)MTK_DP_INTF },
 	{ .compatible = "mediatek,mt2701-dsi",
 	  .data = (void *)MTK_DSI },
 	{ .compatible = "mediatek,mt8173-dsi",
@@ -772,6 +774,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		    comp_type == MTK_DISP_OVL ||
 		    comp_type == MTK_DISP_OVL_2L ||
 		    comp_type == MTK_DISP_RDMA ||
+		    comp_type == MTK_DP_INTF ||
 		    comp_type == MTK_DPI ||
 		    comp_type == MTK_DSI) {
 			dev_info(dev, "Adding component match for %pOF\n",
-- 
GitLab


From 955f04766d4e6eb94bf3baa539e096808c74ebfb Mon Sep 17 00:00:00 2001
From: Guiling Deng <greens9@163.com>
Date: Tue, 28 Jun 2022 09:36:41 -0700
Subject: [PATCH 1620/1731] fbdev: fbmem: Fix logo center image dx issue

Image.dx gets wrong value because of missing '()'.

If xres == logo->width and n == 1, image.dx = -16.

Signed-off-by: Guiling Deng <greens9@163.com>
Fixes: 3d8b1933eb1c ("fbdev: fbmem: add config option to center the bootup logo")
Cc: stable@vger.kernel.org # v5.0+
Signed-off-by: Helge Deller <deller@gmx.de>
---
 drivers/video/fbdev/core/fbmem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/fbdev/core/fbmem.c b/drivers/video/fbdev/core/fbmem.c
index 8afc4538558cd..ee63b5b47290c 100644
--- a/drivers/video/fbdev/core/fbmem.c
+++ b/drivers/video/fbdev/core/fbmem.c
@@ -511,7 +511,7 @@ static int fb_show_logo_line(struct fb_info *info, int rotate,
 
 		while (n && (n * (logo->width + 8) - 8 > xres))
 			--n;
-		image.dx = (xres - n * (logo->width + 8) - 8) / 2;
+		image.dx = (xres - (n * (logo->width + 8) - 8)) / 2;
 		image.dy = y ?: (yres - logo->height) / 2;
 	} else {
 		image.dx = 0;
-- 
GitLab


From 3663a2fb325b8782524f3edb0ae32d6faa615109 Mon Sep 17 00:00:00 2001
From: Hsin-Yi Wang <hsinyi@chromium.org>
Date: Fri, 1 Jul 2022 01:33:29 +0800
Subject: [PATCH 1621/1731] video: of_display_timing.h: include errno.h

If CONFIG_OF is not enabled, default of_get_display_timing() returns an
errno, so include the header.

Fixes: 422b67e0b31a ("videomode: provide dummy inline functions for !CONFIG_OF")
Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Helge Deller <deller@gmx.de>
---
 include/video/of_display_timing.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/video/of_display_timing.h b/include/video/of_display_timing.h
index e1126a74882a5..eff166fdd81b9 100644
--- a/include/video/of_display_timing.h
+++ b/include/video/of_display_timing.h
@@ -8,6 +8,8 @@
 #ifndef __LINUX_OF_DISPLAY_TIMING_H
 #define __LINUX_OF_DISPLAY_TIMING_H
 
+#include <linux/errno.h>
+
 struct device_node;
 struct display_timing;
 struct display_timings;
-- 
GitLab


From 6694482a70e9536efbf2ac233cbf0c302d6e2dae Mon Sep 17 00:00:00 2001
From: Douglas Anderson <dianders@chromium.org>
Date: Fri, 10 Jun 2022 12:47:31 -0700
Subject: [PATCH 1622/1731] drm/msm: Avoid unclocked GMU register access in 6xx
 gpu_busy

From testing on sc7180-trogdor devices, reading the GMU registers
needs the GMU clocks to be enabled. Those clocks get turned on in
a6xx_gmu_resume(). Confusingly enough, that function is called as a
result of the runtime_pm of the GPU "struct device", not the GMU
"struct device". Unfortunately the current a6xx_gpu_busy() grabs a
reference to the GMU's "struct device".

The fact that we were grabbing the wrong reference was easily seen to
cause crashes that happen if we change the GPU's pm_runtime usage to
not use autosuspend. It's also believed to cause some long tail GPU
crashes even with autosuspend.

We could look at changing it so that we do pm_runtime_get_if_in_use()
on the GPU's "struct device", but then we run into a different
problem. pm_runtime_get_if_in_use() will return 0 for the GPU's
"struct device" the whole time when we're in the "autosuspend
delay". That is, when we drop the last reference to the GPU but we're
waiting a period before actually suspending then we'll think the GPU
is off. One reason that's bad is that if the GPU didn't actually turn
off then the cycle counter doesn't lose state and that throws off all
of our calculations.

Let's change the code to keep track of the suspend state of
devfreq. msm_devfreq_suspend() is always called before we actually
suspend the GPU and msm_devfreq_resume() after we resume it. This
means we can use the suspended state to know if we're powered or not.

NOTE: one might wonder when exactly our status function is called when
devfreq is supposed to be disabled. The stack crawl I captured was:
  msm_devfreq_get_dev_status
  devfreq_simple_ondemand_func
  devfreq_update_target
  qos_notifier_call
  qos_max_notifier_call
  blocking_notifier_call_chain
  pm_qos_update_target
  freq_qos_apply
  apply_constraint
  __dev_pm_qos_update_request
  dev_pm_qos_update_request
  msm_devfreq_idle_work

Fixes: eadf79286a4b ("drm/msm: Check for powered down HW in the devfreq callbacks")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/489124/
Link: https://lore.kernel.org/r/20220610124639.v4.1.Ie846c5352bc307ee4248d7cab998ab3016b85d06@changeid
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c |  8 ------
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 13 ++++-----
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++------
 drivers/gpu/drm/msm/adreno/a6xx_gpu.h |  3 ++-
 drivers/gpu/drm/msm/msm_gpu.h         | 11 +++++++-
 drivers/gpu/drm/msm/msm_gpu_devfreq.c | 39 +++++++++++++++++++++------
 6 files changed, 53 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index c424e9a376696..3dcec7acb3840 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -1666,18 +1666,10 @@ static u64 a5xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate)
 {
 	u64 busy_cycles;
 
-	/* Only read the gpu busy if the hardware is already active */
-	if (pm_runtime_get_if_in_use(&gpu->pdev->dev) == 0) {
-		*out_sample_rate = 1;
-		return 0;
-	}
-
 	busy_cycles = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_0_LO,
 			REG_A5XX_RBBM_PERFCTR_RBBM_0_HI);
 	*out_sample_rate = clk_get_rate(gpu->core_clk);
 
-	pm_runtime_put(&gpu->pdev->dev);
-
 	return busy_cycles;
 }
 
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 9f76f5b157598..dc715d88ff214 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -102,7 +102,8 @@ bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
 		A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
 }
 
-void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp)
+void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp,
+		       bool suspended)
 {
 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 	struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
@@ -127,15 +128,16 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp)
 
 	/*
 	 * This can get called from devfreq while the hardware is idle. Don't
-	 * bring up the power if it isn't already active
+	 * bring up the power if it isn't already active. All we're doing here
+	 * is updating the frequency so that when we come back online we're at
+	 * the right rate.
 	 */
-	if (pm_runtime_get_if_in_use(gmu->dev) == 0)
+	if (suspended)
 		return;
 
 	if (!gmu->legacy) {
 		a6xx_hfi_set_freq(gmu, perf_index);
 		dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
-		pm_runtime_put(gmu->dev);
 		return;
 	}
 
@@ -159,7 +161,6 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp)
 		dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
 
 	dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
-	pm_runtime_put(gmu->dev);
 }
 
 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu)
@@ -895,7 +896,7 @@ static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
 		return;
 
 	gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */
-	a6xx_gmu_set_freq(gpu, gpu_opp);
+	a6xx_gmu_set_freq(gpu, gpu_opp, false);
 	dev_pm_opp_put(gpu_opp);
 }
 
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 42ed9a3c49055..8c02a67f29f25 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1658,27 +1658,21 @@ static u64 a6xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate)
 	/* 19.2MHz */
 	*out_sample_rate = 19200000;
 
-	/* Only read the gpu busy if the hardware is already active */
-	if (pm_runtime_get_if_in_use(a6xx_gpu->gmu.dev) == 0)
-		return 0;
-
 	busy_cycles = gmu_read64(&a6xx_gpu->gmu,
 			REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L,
 			REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H);
 
-
-	pm_runtime_put(a6xx_gpu->gmu.dev);
-
 	return busy_cycles;
 }
 
-static void a6xx_gpu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp)
+static void a6xx_gpu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp,
+			      bool suspended)
 {
 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 	struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
 
 	mutex_lock(&a6xx_gpu->gmu.lock);
-	a6xx_gmu_set_freq(gpu, opp);
+	a6xx_gmu_set_freq(gpu, opp, suspended);
 	mutex_unlock(&a6xx_gpu->gmu.lock);
 }
 
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index 86e0a7c3fe6df..ab853f61db632 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -77,7 +77,8 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node);
 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu);
 
-void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp);
+void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp,
+		       bool suspended);
 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu);
 
 void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 4911943ba53b2..fefcf2c8fe659 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -64,11 +64,14 @@ struct msm_gpu_funcs {
 	/* for generation specific debugfs: */
 	void (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
 #endif
+	/* note: gpu_busy() can assume that we have been pm_resumed */
 	u64 (*gpu_busy)(struct msm_gpu *gpu, unsigned long *out_sample_rate);
 	struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
 	int (*gpu_state_put)(struct msm_gpu_state *state);
 	unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
-	void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp);
+	/* note: gpu_set_freq() can assume that we have been pm_resumed */
+	void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp,
+			     bool suspended);
 	struct msm_gem_address_space *(*create_address_space)
 		(struct msm_gpu *gpu, struct platform_device *pdev);
 	struct msm_gem_address_space *(*create_private_address_space)
@@ -92,6 +95,9 @@ struct msm_gpu_devfreq {
 	/** devfreq: devfreq instance */
 	struct devfreq *devfreq;
 
+	/** lock: lock for "suspended", "busy_cycles", and "time" */
+	struct mutex lock;
+
 	/**
 	 * idle_constraint:
 	 *
@@ -135,6 +141,9 @@ struct msm_gpu_devfreq {
 	 * elapsed
 	 */
 	struct msm_hrtimer_work boost_work;
+
+	/** suspended: tracks if we're suspended */
+	bool suspended;
 };
 
 struct msm_gpu {
diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c
index c2ea978c89218..d1f70426f554e 100644
--- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c
+++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c
@@ -20,6 +20,7 @@ static int msm_devfreq_target(struct device *dev, unsigned long *freq,
 		u32 flags)
 {
 	struct msm_gpu *gpu = dev_to_gpu(dev);
+	struct msm_gpu_devfreq *df = &gpu->devfreq;
 	struct dev_pm_opp *opp;
 
 	/*
@@ -32,10 +33,13 @@ static int msm_devfreq_target(struct device *dev, unsigned long *freq,
 
 	trace_msm_gpu_freq_change(dev_pm_opp_get_freq(opp));
 
-	if (gpu->funcs->gpu_set_freq)
-		gpu->funcs->gpu_set_freq(gpu, opp);
-	else
+	if (gpu->funcs->gpu_set_freq) {
+		mutex_lock(&df->lock);
+		gpu->funcs->gpu_set_freq(gpu, opp, df->suspended);
+		mutex_unlock(&df->lock);
+	} else {
 		clk_set_rate(gpu->core_clk, *freq);
+	}
 
 	dev_pm_opp_put(opp);
 
@@ -58,15 +62,24 @@ static void get_raw_dev_status(struct msm_gpu *gpu,
 	unsigned long sample_rate;
 	ktime_t time;
 
+	mutex_lock(&df->lock);
+
 	status->current_frequency = get_freq(gpu);
-	busy_cycles = gpu->funcs->gpu_busy(gpu, &sample_rate);
 	time = ktime_get();
-
-	busy_time = busy_cycles - df->busy_cycles;
 	status->total_time = ktime_us_delta(time, df->time);
+	df->time = time;
 
+	if (df->suspended) {
+		mutex_unlock(&df->lock);
+		status->busy_time = 0;
+		return;
+	}
+
+	busy_cycles = gpu->funcs->gpu_busy(gpu, &sample_rate);
+	busy_time = busy_cycles - df->busy_cycles;
 	df->busy_cycles = busy_cycles;
-	df->time = time;
+
+	mutex_unlock(&df->lock);
 
 	busy_time *= USEC_PER_SEC;
 	busy_time = div64_ul(busy_time, sample_rate);
@@ -175,6 +188,8 @@ void msm_devfreq_init(struct msm_gpu *gpu)
 	if (!gpu->funcs->gpu_busy)
 		return;
 
+	mutex_init(&df->lock);
+
 	dev_pm_qos_add_request(&gpu->pdev->dev, &df->idle_freq,
 			       DEV_PM_QOS_MAX_FREQUENCY,
 			       PM_QOS_MAX_FREQUENCY_DEFAULT_VALUE);
@@ -244,12 +259,16 @@ void msm_devfreq_cleanup(struct msm_gpu *gpu)
 void msm_devfreq_resume(struct msm_gpu *gpu)
 {
 	struct msm_gpu_devfreq *df = &gpu->devfreq;
+	unsigned long sample_rate;
 
 	if (!has_devfreq(gpu))
 		return;
 
-	df->busy_cycles = 0;
+	mutex_lock(&df->lock);
+	df->busy_cycles = gpu->funcs->gpu_busy(gpu, &sample_rate);
 	df->time = ktime_get();
+	df->suspended = false;
+	mutex_unlock(&df->lock);
 
 	devfreq_resume_device(df->devfreq);
 }
@@ -261,6 +280,10 @@ void msm_devfreq_suspend(struct msm_gpu *gpu)
 	if (!has_devfreq(gpu))
 		return;
 
+	mutex_lock(&df->lock);
+	df->suspended = true;
+	mutex_unlock(&df->lock);
+
 	devfreq_suspend_device(df->devfreq);
 
 	cancel_idle_work(df);
-- 
GitLab


From 0165e9c119c92fae4366c92ea459edde0224bfa7 Mon Sep 17 00:00:00 2001
From: Konrad Dybcio <konrad.dybcio@somainline.org>
Date: Sat, 28 May 2022 18:03:48 +0200
Subject: [PATCH 1623/1731] drm/msm/adreno: Remove dead code

This BUG_ON will never be reached, and there is a comment 20 above
explaining why.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/487586/
Link: https://lore.kernel.org/r/20220528160353.157870-1-konrad.dybcio@somainline.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index dc715d88ff214..7ccf9916bf193 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -1549,8 +1549,6 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
 		if (ret)
 			goto err_memory;
 	} else {
-		BUG_ON(adreno_is_a660_family(adreno_gpu));
-
 		/* HFI v1, has sptprac */
 		gmu->legacy = true;
 
-- 
GitLab


From b7616b5c69e62e76cf5364915321377344ce1f8e Mon Sep 17 00:00:00 2001
From: Konrad Dybcio <konrad.dybcio@somainline.org>
Date: Sat, 28 May 2022 18:03:49 +0200
Subject: [PATCH 1624/1731] drm/msm/adreno: Add A619 support

Add support for the Adreno 619 GPU, as found in Snapdragon 690 (SM6350),
480 (SM4350) and 750G (SM7225).

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/487588/
Link: https://lore.kernel.org/r/20220528160353.157870-2-konrad.dybcio@somainline.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c      | 13 +++-
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c      | 70 +++++++++++++++++++++-
 drivers/gpu/drm/msm/adreno/a6xx_hfi.c      | 65 +++++++++++++++++++-
 drivers/gpu/drm/msm/adreno/adreno_device.c | 14 +++++
 drivers/gpu/drm/msm/adreno/adreno_gpu.h    | 13 +++-
 5 files changed, 169 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 7ccf9916bf193..c6660307e437b 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -528,6 +528,8 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
 		pdc_in_aop = true;
 	else if (adreno_is_a618(adreno_gpu) || adreno_is_a640_family(adreno_gpu))
 		pdc_address_offset = 0x30090;
+	else if (adreno_is_a619(adreno_gpu))
+		pdc_address_offset = 0x300a0;
 	else
 		pdc_address_offset = 0x30080;
 
@@ -602,7 +604,8 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
 
 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
-	if (adreno_is_a618(adreno_gpu) || adreno_is_a650_family(adreno_gpu))
+	if (adreno_is_a618(adreno_gpu) || adreno_is_a619(adreno_gpu) ||
+			adreno_is_a650_family(adreno_gpu))
 		pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
 	else
 		pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
@@ -1538,6 +1541,12 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
 			SZ_16M - SZ_16K, 0x04000, "icache");
 		if (ret)
 			goto err_memory;
+	/*
+	 * NOTE: when porting legacy ("pre-650-family") GPUs you may be tempted to add a condition
+	 * to allocate icache/dcache here, as per downstream code flow, but it may not actually be
+	 * necessary. If you omit this step and you don't get random pagefaults, you are likely
+	 * good to go without this!
+	 */
 	} else if (adreno_is_a640_family(adreno_gpu)) {
 		ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
 			SZ_256K - SZ_16K, 0x04000, "icache");
@@ -1548,7 +1557,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
 			SZ_256K - SZ_16K, 0x44000, "dcache");
 		if (ret)
 			goto err_memory;
-	} else {
+	} else if (adreno_is_a630(adreno_gpu) || adreno_is_a615_family(adreno_gpu)) {
 		/* HFI v1, has sptprac */
 		gmu->legacy = true;
 
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 8c02a67f29f25..d5045c99eef91 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -252,6 +252,74 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
 	a6xx_flush(gpu, ring);
 }
 
+/* For a615 family (a615, a616, a618 and a619) */
+const struct adreno_reglist a615_hwcg[] = {
+	{REG_A6XX_RBBM_CLOCK_CNTL_SP0,  0x02222222},
+	{REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
+	{REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
+	{REG_A6XX_RBBM_CLOCK_HYST_SP0,  0x0000F3CF},
+	{REG_A6XX_RBBM_CLOCK_CNTL_TP0,  0x02222222},
+	{REG_A6XX_RBBM_CLOCK_CNTL_TP1,  0x02222222},
+	{REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+	{REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
+	{REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+	{REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
+	{REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+	{REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
+	{REG_A6XX_RBBM_CLOCK_HYST_TP0,  0x77777777},
+	{REG_A6XX_RBBM_CLOCK_HYST_TP1,  0x77777777},
+	{REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+	{REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
+	{REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
+	{REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
+	{REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+	{REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
+	{REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+	{REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
+	{REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+	{REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
+	{REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+	{REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
+	{REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+	{REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
+	{REG_A6XX_RBBM_CLOCK_CNTL_UCHE,  0x22222222},
+	{REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
+	{REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
+	{REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
+	{REG_A6XX_RBBM_CLOCK_HYST_UCHE,  0x00000004},
+	{REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+	{REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+	{REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
+	{REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002020},
+	{REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
+	{REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
+	{REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
+	{REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
+	{REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00},
+	{REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00},
+	{REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00},
+	{REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
+	{REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+	{REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+	{REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+	{REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+	{REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
+	{REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+	{REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+	{REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+	{REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+	{REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+	{REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+	{REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+	{REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+	{REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+	{REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+	{REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+	{REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+	{REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
+	{},
+};
+
 const struct adreno_reglist a630_hwcg[] = {
 	{REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
 	{REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
@@ -555,7 +623,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
 	gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);
 }
 
-/* For a615, a616, a618, A619, a630, a640 and a680 */
+/* For a615, a616, a618, a619, a630, a640 and a680 */
 static const u32 a6xx_protect[] = {
 	A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
 	A6XX_PROTECT_RDONLY(0x00501, 0x0005),
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
index d73fce5fdf1f1..2cc83e0496133 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
@@ -205,8 +205,8 @@ static int a6xx_hfi_get_fw_version(struct a6xx_gmu *gmu, u32 *version)
 {
 	struct a6xx_hfi_msg_fw_version msg = { 0 };
 
-	/* Currently supporting version 1.1 */
-	msg.supported_version = (1 << 28) | (1 << 16);
+	/* Currently supporting version 1.10 */
+	msg.supported_version = (1 << 28) | (1 << 19) | (1 << 17);
 
 	return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_FW_VERSION, &msg, sizeof(msg),
 		version, sizeof(*version));
@@ -285,6 +285,65 @@ static void a618_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
 	msg->cnoc_cmds_data[1][0] =  0x60000001;
 }
 
+static void a619_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
+{
+	msg->bw_level_num = 13;
+
+	msg->ddr_cmds_num = 3;
+	msg->ddr_wait_bitmask = 0x0;
+
+	msg->ddr_cmds_addrs[0] = 0x50000;
+	msg->ddr_cmds_addrs[1] = 0x50004;
+	msg->ddr_cmds_addrs[2] = 0x50080;
+
+	msg->ddr_cmds_data[0][0]  = 0x40000000;
+	msg->ddr_cmds_data[0][1]  = 0x40000000;
+	msg->ddr_cmds_data[0][2]  = 0x40000000;
+	msg->ddr_cmds_data[1][0]  = 0x6000030c;
+	msg->ddr_cmds_data[1][1]  = 0x600000db;
+	msg->ddr_cmds_data[1][2]  = 0x60000008;
+	msg->ddr_cmds_data[2][0]  = 0x60000618;
+	msg->ddr_cmds_data[2][1]  = 0x600001b6;
+	msg->ddr_cmds_data[2][2]  = 0x60000008;
+	msg->ddr_cmds_data[3][0]  = 0x60000925;
+	msg->ddr_cmds_data[3][1]  = 0x60000291;
+	msg->ddr_cmds_data[3][2]  = 0x60000008;
+	msg->ddr_cmds_data[4][0]  = 0x60000dc1;
+	msg->ddr_cmds_data[4][1]  = 0x600003dc;
+	msg->ddr_cmds_data[4][2]  = 0x60000008;
+	msg->ddr_cmds_data[5][0]  = 0x600010ad;
+	msg->ddr_cmds_data[5][1]  = 0x600004ae;
+	msg->ddr_cmds_data[5][2]  = 0x60000008;
+	msg->ddr_cmds_data[6][0]  = 0x600014c3;
+	msg->ddr_cmds_data[6][1]  = 0x600005d4;
+	msg->ddr_cmds_data[6][2]  = 0x60000008;
+	msg->ddr_cmds_data[7][0]  = 0x6000176a;
+	msg->ddr_cmds_data[7][1]  = 0x60000693;
+	msg->ddr_cmds_data[7][2]  = 0x60000008;
+	msg->ddr_cmds_data[8][0]  = 0x60001f01;
+	msg->ddr_cmds_data[8][1]  = 0x600008b5;
+	msg->ddr_cmds_data[8][2]  = 0x60000008;
+	msg->ddr_cmds_data[9][0]  = 0x60002940;
+	msg->ddr_cmds_data[9][1]  = 0x60000b95;
+	msg->ddr_cmds_data[9][2]  = 0x60000008;
+	msg->ddr_cmds_data[10][0] = 0x60002f68;
+	msg->ddr_cmds_data[10][1] = 0x60000d50;
+	msg->ddr_cmds_data[10][2] = 0x60000008;
+	msg->ddr_cmds_data[11][0] = 0x60003700;
+	msg->ddr_cmds_data[11][1] = 0x60000f71;
+	msg->ddr_cmds_data[11][2] = 0x60000008;
+	msg->ddr_cmds_data[12][0] = 0x60003fce;
+	msg->ddr_cmds_data[12][1] = 0x600011ea;
+	msg->ddr_cmds_data[12][2] = 0x60000008;
+
+	msg->cnoc_cmds_num = 1;
+	msg->cnoc_wait_bitmask = 0x0;
+
+	msg->cnoc_cmds_addrs[0] = 0x50054;
+
+	msg->cnoc_cmds_data[0][0] = 0x40000000;
+}
+
 static void a640_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
 {
 	/*
@@ -462,6 +521,8 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
 
 	if (adreno_is_a618(adreno_gpu))
 		a618_build_bw_table(&msg);
+	else if (adreno_is_a619(adreno_gpu))
+		a619_build_bw_table(&msg);
 	else if (adreno_is_a640_family(adreno_gpu))
 		a640_build_bw_table(&msg);
 	else if (adreno_is_a650(adreno_gpu))
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 8706bcdd1472e..87be25aec5408 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -264,6 +264,19 @@ static const struct adreno_info gpulist[] = {
 		.gmem = SZ_512K,
 		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
 		.init = a6xx_gpu_init,
+	}, {
+		.rev = ADRENO_REV(6, 1, 9, ANY_ID),
+		.revn = 619,
+		.name = "A619",
+		.fw = {
+			[ADRENO_FW_SQE] = "a630_sqe.fw",
+			[ADRENO_FW_GMU] = "a619_gmu.bin",
+		},
+		.gmem = SZ_512K,
+		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
+		.init = a6xx_gpu_init,
+		.zapfw = "a615_zap.mdt",
+		.hwcg = a615_hwcg,
 	}, {
 		.rev = ADRENO_REV(6, 3, 0, ANY_ID),
 		.revn = 630,
@@ -355,6 +368,7 @@ MODULE_FIRMWARE("qcom/a530_zap.mdt");
 MODULE_FIRMWARE("qcom/a530_zap.b00");
 MODULE_FIRMWARE("qcom/a530_zap.b01");
 MODULE_FIRMWARE("qcom/a530_zap.b02");
+MODULE_FIRMWARE("qcom/a619_gmu.bin");
 MODULE_FIRMWARE("qcom/a630_sqe.fw");
 MODULE_FIRMWARE("qcom/a630_gmu.bin");
 MODULE_FIRMWARE("qcom/a630_zap.mbn");
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index ab3b5ef80332d..c4dd388d26669 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -57,7 +57,7 @@ struct adreno_reglist {
 	u32 value;
 };
 
-extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];
+extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];
 
 struct adreno_info {
 	struct adreno_rev rev;
@@ -242,6 +242,11 @@ static inline int adreno_is_a618(struct adreno_gpu *gpu)
        return gpu->revn == 618;
 }
 
+static inline int adreno_is_a619(struct adreno_gpu *gpu)
+{
+	return gpu->revn == 619;
+}
+
 static inline int adreno_is_a630(struct adreno_gpu *gpu)
 {
        return gpu->revn == 630;
@@ -268,6 +273,12 @@ static inline int adreno_is_a660(struct adreno_gpu *gpu)
        return gpu->revn == 660;
 }
 
+/* check for a615, a616, a618, a619 or any derivatives */
+static inline int adreno_is_a615_family(struct adreno_gpu *gpu)
+{
+	return gpu->revn == 615 || gpu->revn == 616 || gpu->revn == 618 || gpu->revn == 619;
+}
+
 static inline int adreno_is_a660_family(struct adreno_gpu *gpu)
 {
        return adreno_is_a660(gpu) || adreno_is_7c3(gpu);
-- 
GitLab


From fba6767c2dabcfaed0a8abf77fde0a8cb1b9fe10 Mon Sep 17 00:00:00 2001
From: Konrad Dybcio <konrad.dybcio@somainline.org>
Date: Sat, 28 May 2022 18:03:50 +0200
Subject: [PATCH 1625/1731] drm/msm/a6xx: Add speedbin support for A619 GPU

There are various SKUs of A619, ranging from 565 MHz to 850 MHz, depending
on the bin. Add support for distinguishing them, so that proper frequency
ranges can be applied, depending on the HW.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/487590/
Link: https://lore.kernel.org/r/20220528160353.157870-3-konrad.dybcio@somainline.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index d5045c99eef91..2db5dbacb160d 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1825,6 +1825,22 @@ static u32 a618_get_speed_bin(u32 fuse)
 	return UINT_MAX;
 }
 
+static u32 a619_get_speed_bin(u32 fuse)
+{
+	if (fuse == 0)
+		return 0;
+	else if (fuse == 120)
+		return 4;
+	else if (fuse == 138)
+		return 3;
+	else if (fuse == 169)
+		return 2;
+	else if (fuse == 180)
+		return 1;
+
+	return UINT_MAX;
+}
+
 static u32 adreno_7c3_get_speed_bin(u32 fuse)
 {
 	if (fuse == 0)
@@ -1844,6 +1860,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
 	if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev))
 		val = a618_get_speed_bin(fuse);
 
+	if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev))
+		val = a619_get_speed_bin(fuse);
+
 	if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev))
 		val = adreno_7c3_get_speed_bin(fuse);
 
-- 
GitLab


From 9bec4399af223edba58ccb66c406b10878ef45b3 Mon Sep 17 00:00:00 2001
From: Konrad Dybcio <konrad.dybcio@somainline.org>
Date: Sat, 28 May 2022 18:03:51 +0200
Subject: [PATCH 1626/1731] drm/msm/adreno: Fix up formatting

Leading spaces are not something checkpatch likes, and it says so when
they are present. Use tabs consistently to indent function body and
unwrap a 83-char-long line, as 100 is cool nowadays.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/487592/
Link: https://lore.kernel.org/r/20220528160353.157870-4-konrad.dybcio@somainline.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.h | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index c4dd388d26669..5486c52a04346 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -199,7 +199,7 @@ static inline int adreno_is_a420(struct adreno_gpu *gpu)
 
 static inline int adreno_is_a430(struct adreno_gpu *gpu)
 {
-       return gpu->revn == 430;
+	return gpu->revn == 430;
 }
 
 static inline int adreno_is_a506(struct adreno_gpu *gpu)
@@ -239,7 +239,7 @@ static inline int adreno_is_a540(struct adreno_gpu *gpu)
 
 static inline int adreno_is_a618(struct adreno_gpu *gpu)
 {
-       return gpu->revn == 618;
+	return gpu->revn == 618;
 }
 
 static inline int adreno_is_a619(struct adreno_gpu *gpu)
@@ -249,7 +249,7 @@ static inline int adreno_is_a619(struct adreno_gpu *gpu)
 
 static inline int adreno_is_a630(struct adreno_gpu *gpu)
 {
-       return gpu->revn == 630;
+	return gpu->revn == 630;
 }
 
 static inline int adreno_is_a640_family(struct adreno_gpu *gpu)
@@ -259,18 +259,18 @@ static inline int adreno_is_a640_family(struct adreno_gpu *gpu)
 
 static inline int adreno_is_a650(struct adreno_gpu *gpu)
 {
-       return gpu->revn == 650;
+	return gpu->revn == 650;
 }
 
 static inline int adreno_is_7c3(struct adreno_gpu *gpu)
 {
 	/* The order of args is important here to handle ANY_ID correctly */
-       return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
+	return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
 }
 
 static inline int adreno_is_a660(struct adreno_gpu *gpu)
 {
-       return gpu->revn == 660;
+	return gpu->revn == 660;
 }
 
 /* check for a615, a616, a618, a619 or any derivatives */
@@ -281,14 +281,13 @@ static inline int adreno_is_a615_family(struct adreno_gpu *gpu)
 
 static inline int adreno_is_a660_family(struct adreno_gpu *gpu)
 {
-       return adreno_is_a660(gpu) || adreno_is_7c3(gpu);
+	return adreno_is_a660(gpu) || adreno_is_7c3(gpu);
 }
 
 /* check for a650, a660, or any derivatives */
 static inline int adreno_is_a650_family(struct adreno_gpu *gpu)
 {
-       return gpu->revn == 650 || gpu->revn == 620 ||
-	       adreno_is_a660_family(gpu);
+	return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu);
 }
 
 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
-- 
GitLab


From 36bbfdb8bcb62752966211de1c0b9ee5fd972305 Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Sun, 29 May 2022 11:04:23 -0700
Subject: [PATCH 1627/1731] drm/msm/adreno: Allow larger address space size

The restriction to 4G was strictly to work around 64b math bug in some
versions of SQE firmware.  This appears to be fixed in a650+ SQE fw, so
allow a larger address space size on these devices.

Also, add a modparam override for debugging and igt.

v2: Send the right version of the patch (ie. the one that actually
    compiles)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/487601/
Link: https://lore.kernel.org/r/20220529180428.2577832-1-robdclark@gmail.com
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c      |  3 ++-
 drivers/gpu/drm/msm/adreno/adreno_device.c |  3 +++
 drivers/gpu/drm/msm/adreno/adreno_gpu.c    | 17 +++++++++++++++++
 drivers/gpu/drm/msm/adreno/adreno_gpu.h    |  2 ++
 4 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 2db5dbacb160d..0a3a176649da5 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1799,7 +1799,8 @@ a6xx_create_private_address_space(struct msm_gpu *gpu)
 		return ERR_CAST(mmu);
 
 	return msm_gem_address_space_create(mmu,
-		"gpu", 0x100000000ULL, SZ_4G);
+		"gpu", 0x100000000ULL,
+		adreno_private_address_space_size(gpu));
 }
 
 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 87be25aec5408..0e45b442d85fc 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -316,6 +316,7 @@ static const struct adreno_info gpulist[] = {
 		.init = a6xx_gpu_init,
 		.zapfw = "a650_zap.mdt",
 		.hwcg = a650_hwcg,
+		.address_space_size = SZ_16G,
 	}, {
 		.rev = ADRENO_REV(6, 6, 0, ANY_ID),
 		.revn = 660,
@@ -329,6 +330,7 @@ static const struct adreno_info gpulist[] = {
 		.init = a6xx_gpu_init,
 		.zapfw = "a660_zap.mdt",
 		.hwcg = a660_hwcg,
+		.address_space_size = SZ_16G,
 	}, {
 		.rev = ADRENO_REV(6, 3, 5, ANY_ID),
 		.fw = {
@@ -339,6 +341,7 @@ static const struct adreno_info gpulist[] = {
 		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
 		.init = a6xx_gpu_init,
 		.hwcg = a660_hwcg,
+		.address_space_size = SZ_16G,
 	}, {
 		.rev = ADRENO_REV(6, 8, 0, ANY_ID),
 		.revn = 680,
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index efe9840e28fad..73c0d01ee31d5 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -21,6 +21,10 @@
 #include "msm_gem.h"
 #include "msm_mmu.h"
 
+static u64 address_space_size = 0;
+MODULE_PARM_DESC(address_space_size, "Override for size of processes private GPU address space");
+module_param(address_space_size, ullong, 0600);
+
 static bool zap_available = true;
 
 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname,
@@ -228,6 +232,19 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu,
 	return aspace;
 }
 
+u64 adreno_private_address_space_size(struct msm_gpu *gpu)
+{
+	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+
+	if (address_space_size)
+		return address_space_size;
+
+	if (adreno_gpu->info->address_space_size)
+		return adreno_gpu->info->address_space_size;
+
+	return SZ_4G;
+}
+
 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
 		     uint32_t param, uint64_t *value, uint32_t *len)
 {
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 5486c52a04346..e7adc5c632d07 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -70,6 +70,7 @@ struct adreno_info {
 	const char *zapfw;
 	u32 inactive_period;
 	const struct adreno_reglist *hwcg;
+	u64 address_space_size;
 };
 
 const struct adreno_info *adreno_info(struct adreno_rev rev);
@@ -290,6 +291,7 @@ static inline int adreno_is_a650_family(struct adreno_gpu *gpu)
 	return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu);
 }
 
+u64 adreno_private_address_space_size(struct msm_gpu *gpu);
 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
 		     uint32_t param, uint64_t *value, uint32_t *len);
 int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
-- 
GitLab


From d352d6d5241be2d9bf86da4ba71b6e58d34235a4 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Wed, 1 Jun 2022 19:13:46 +0300
Subject: [PATCH 1628/1731] drm/msm/dpu: drop xin_id from struct
 dpu_hw_blk_reg_map

Drop the unused field xin_id.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/488011/
Link: https://lore.kernel.org/r/20220601161349.1517667-2-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index ca74474d546b8..377a1eef4016b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -26,13 +26,11 @@
  * @base_off:     mdp register mapped offset
  * @blk_off:      pipe offset relative to mdss offset
  * @length        length of register block offset
- * @xin_id        xin id
  */
 struct dpu_hw_blk_reg_map {
 	void __iomem *base_off;
 	u32 blk_off;
 	u32 length;
-	u32 xin_id;
 	u32 log_mask;
 };
 
-- 
GitLab


From 1e5df24b996c1c46b60e396302120927b42c7f14 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Wed, 1 Jun 2022 19:13:47 +0300
Subject: [PATCH 1629/1731] drm/msm/dpu: drop length from struct
 dpu_hw_blk_reg_map

We (nearly) do not use the length field from struct dpu_hw_blk_reg_map,
so we can drop it safely.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/488013/
Link: https://lore.kernel.org/r/20220601161349.1517667-3-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c      | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c      | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c     | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c     | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c       | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c  | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c     | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c      | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h     | 2 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c     | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c       | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c         | 2 +-
 13 files changed, 1 insertion(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 7d416bf4ae916..1120ff408daec 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -60,7 +60,6 @@ static const struct dpu_ctl_cfg *_ctl_offset(enum dpu_ctl ctl,
 		if (ctl == m->ctl[i].id) {
 			b->base_off = addr;
 			b->blk_off = m->ctl[i].base;
-			b->length = m->ctl[i].len;
 			b->log_mask = DPU_DBG_MASK_CTL;
 			return &m->ctl[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
index 184a1b27b13d5..dfe6e4c119172 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
@@ -168,7 +168,6 @@ static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc,
 		if (dsc == m->dsc[i].id) {
 			b->base_off = addr;
 			b->blk_off = m->dsc[i].base;
-			b->length = m->dsc[i].len;
 			b->log_mask = DPU_DBG_MASK_DSC;
 			return &m->dsc[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
index 3e63bf4fa64e5..8196ae47dea8f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
@@ -82,7 +82,6 @@ static const struct dpu_dspp_cfg *_dspp_offset(enum dpu_dspp dspp,
 		if (dspp == m->dspp[i].id) {
 			b->base_off = addr;
 			b->blk_off = m->dspp[i].base;
-			b->length = m->dspp[i].len;
 			b->log_mask = DPU_DBG_MASK_DSPP;
 			return &m->dspp[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 90613f797ff58..3ae2a2c1cd9d6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -84,7 +84,6 @@ static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf,
 		(m->intf[i].type != INTF_NONE)) {
 			b->base_off = addr;
 			b->blk_off = m->intf[i].base;
-			b->length = m->intf[i].len;
 			b->log_mask = DPU_DBG_MASK_INTF;
 			return &m->intf[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index f1d237057ed91..9a1e91962ae73 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -41,7 +41,6 @@ static const struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer,
 		if (mixer == m->mixer[i].id) {
 			b->base_off = addr;
 			b->blk_off = m->mixer[i].base;
-			b->length = m->mixer[i].len;
 			b->log_mask = DPU_DBG_MASK_LM;
 			return &m->mixer[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
index b053d68d38da2..538691f7bf660 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
@@ -25,7 +25,6 @@ static const struct dpu_merge_3d_cfg *_merge_3d_offset(enum dpu_merge_3d idx,
 		if (idx == m->merge_3d[i].id) {
 			b->base_off = addr;
 			b->blk_off = m->merge_3d[i].base;
-			b->length = m->merge_3d[i].len;
 			b->log_mask = DPU_DBG_MASK_PINGPONG;
 			return &m->merge_3d[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
index 6538e195cfe94..0aa63636bc9a8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
@@ -53,7 +53,6 @@ static const struct dpu_pingpong_cfg *_pingpong_offset(enum dpu_pingpong pp,
 		if (pp == m->pingpong[i].id) {
 			b->base_off = addr;
 			b->blk_off = m->pingpong[i].base;
-			b->length = m->pingpong[i].len;
 			b->log_mask = DPU_DBG_MASK_PINGPONG;
 			return &m->pingpong[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index da4c7e4f304b4..876ae8faa8e5f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -771,7 +771,6 @@ static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp,
 			if (sspp == catalog->sspp[i].id) {
 				b->base_off = addr;
 				b->blk_off = catalog->sspp[i].base;
-				b->length = catalog->sspp[i].len;
 				b->log_mask = DPU_DBG_MASK_SSPP;
 				return &catalog->sspp[i];
 			}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
index 12d3b00672754..843cb607d411f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
@@ -287,7 +287,6 @@ static const struct dpu_mdp_cfg *_top_offset(enum dpu_mdp mdp,
 		if (mdp == m->mdp[i].id) {
 			b->base_off = addr;
 			b->blk_off = m->mdp[i].base;
-			b->length = m->mdp[i].len;
 			b->log_mask = DPU_DBG_MASK_TOP;
 			return &m->mdp[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index 377a1eef4016b..28200d31bc5b3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -25,12 +25,10 @@
  * absoulute IO address
  * @base_off:     mdp register mapped offset
  * @blk_off:      pipe offset relative to mdss offset
- * @length        length of register block offset
  */
 struct dpu_hw_blk_reg_map {
 	void __iomem *base_off;
 	u32 blk_off;
-	u32 length;
 	u32 log_mask;
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
index 789ecc531b43a..41ca4b179f1a7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
@@ -222,7 +222,6 @@ static const struct dpu_vbif_cfg *_top_offset(enum dpu_vbif vbif,
 		if (vbif == m->vbif[i].id) {
 			b->base_off = addr;
 			b->blk_off = m->vbif[i].base;
-			b->length = m->vbif[i].len;
 			b->log_mask = DPU_DBG_MASK_VBIF;
 			return &m->vbif[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
index 084439fdd3a0d..12f32cd3075ee 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
@@ -62,7 +62,6 @@ static const struct dpu_wb_cfg *_wb_offset(enum dpu_wb wb,
 		if (wb == m->wb[i].id) {
 			b->base_off = addr;
 			b->blk_off = m->wb[i].base;
-			b->length = m->wb[i].len;
 			return &m->wb[i];
 		}
 	}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index a2d71f0c96af2..457f9c911e92f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -945,7 +945,7 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k
 		msm_disp_snapshot_add_block(disp_state, cat->wb[i].len,
 				dpu_kms->mmio + cat->wb[i].base, "wb_%d", i);
 
-	msm_disp_snapshot_add_block(disp_state, top->hw.length,
+	msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len,
 			dpu_kms->mmio + top->hw.blk_off, "top");
 
 	pm_runtime_put_sync(&dpu_kms->pdev->dev);
-- 
GitLab


From 9403f9a42c881d59396a454347540108d787685f Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Wed, 1 Jun 2022 19:13:48 +0300
Subject: [PATCH 1630/1731] drm/msm/dpu: merge base_off with blk_off in struct
 dpu_hw_blk_reg_map

There is little point in keeping a separate MDP address and block offset
in this struct. Merge them to form a new blk_addr field used for all
register access.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/488017/
Link: https://lore.kernel.org/r/20220601161349.1517667-4-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c        | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c        | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c       | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c       | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c         | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c    | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c   | 5 ++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c       | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c        | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c       | 6 +++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h       | 7 +++----
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c       | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c         | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c           | 2 +-
 15 files changed, 20 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 1120ff408daec..e12b7fa48a7b3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -58,8 +58,7 @@ static const struct dpu_ctl_cfg *_ctl_offset(enum dpu_ctl ctl,
 
 	for (i = 0; i < m->ctl_count; i++) {
 		if (ctl == m->ctl[i].id) {
-			b->base_off = addr;
-			b->blk_off = m->ctl[i].base;
+			b->blk_addr = addr + m->ctl[i].base;
 			b->log_mask = DPU_DBG_MASK_CTL;
 			return &m->ctl[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
index dfe6e4c119172..411689ae63825 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
@@ -166,8 +166,7 @@ static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc,
 
 	for (i = 0; i < m->dsc_count; i++) {
 		if (dsc == m->dsc[i].id) {
-			b->base_off = addr;
-			b->blk_off = m->dsc[i].base;
+			b->blk_addr = addr + m->dsc[i].base;
 			b->log_mask = DPU_DBG_MASK_DSC;
 			return &m->dsc[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
index 8196ae47dea8f..8ab5ace34a2d5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
@@ -80,8 +80,7 @@ static const struct dpu_dspp_cfg *_dspp_offset(enum dpu_dspp dspp,
 
 	for (i = 0; i < m->dspp_count; i++) {
 		if (dspp == m->dspp[i].id) {
-			b->base_off = addr;
-			b->blk_off = m->dspp[i].base;
+			b->blk_addr = addr + m->dspp[i].base;
 			b->log_mask = DPU_DBG_MASK_DSPP;
 			return &m->dspp[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index d83503ea2419a..cf1b6d84c18a3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -401,8 +401,7 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
 static void __intr_offset(const struct dpu_mdss_cfg *m,
 		void __iomem *addr, struct dpu_hw_blk_reg_map *hw)
 {
-	hw->base_off = addr;
-	hw->blk_off = m->mdp[0].base;
+	hw->blk_addr = addr + m->mdp[0].base;
 }
 
 struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 3ae2a2c1cd9d6..7ce66bf3f4c8d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -82,8 +82,7 @@ static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf,
 	for (i = 0; i < m->intf_count; i++) {
 		if ((intf == m->intf[i].id) &&
 		(m->intf[i].type != INTF_NONE)) {
-			b->base_off = addr;
-			b->blk_off = m->intf[i].base;
+			b->blk_addr = addr + m->intf[i].base;
 			b->log_mask = DPU_DBG_MASK_INTF;
 			return &m->intf[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index 9a1e91962ae73..f5120ea91edee 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -39,8 +39,7 @@ static const struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer,
 
 	for (i = 0; i < m->mixer_count; i++) {
 		if (mixer == m->mixer[i].id) {
-			b->base_off = addr;
-			b->blk_off = m->mixer[i].base;
+			b->blk_addr = addr + m->mixer[i].base;
 			b->log_mask = DPU_DBG_MASK_LM;
 			return &m->mixer[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
index 538691f7bf660..def0a87fdba56 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
@@ -23,8 +23,7 @@ static const struct dpu_merge_3d_cfg *_merge_3d_offset(enum dpu_merge_3d idx,
 
 	for (i = 0; i < m->merge_3d_count; i++) {
 		if (idx == m->merge_3d[i].id) {
-			b->base_off = addr;
-			b->blk_off = m->merge_3d[i].base;
+			b->blk_addr = addr + m->merge_3d[i].base;
 			b->log_mask = DPU_DBG_MASK_PINGPONG;
 			return &m->merge_3d[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
index 0aa63636bc9a8..0fcad9760b6fc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
@@ -51,8 +51,7 @@ static const struct dpu_pingpong_cfg *_pingpong_offset(enum dpu_pingpong pp,
 
 	for (i = 0; i < m->pingpong_count; i++) {
 		if (pp == m->pingpong[i].id) {
-			b->base_off = addr;
-			b->blk_off = m->pingpong[i].base;
+			b->blk_addr = addr + m->pingpong[i].base;
 			b->log_mask = DPU_DBG_MASK_PINGPONG;
 			return &m->pingpong[i];
 		}
@@ -156,7 +155,7 @@ static int dpu_hw_pp_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp,
 		return -EINVAL;
 
 	c = &pp->hw;
-	rc = readl_poll_timeout(c->base_off + c->blk_off + PP_LINE_COUNT,
+	rc = readl_poll_timeout(c->blk_addr + PP_LINE_COUNT,
 			val, (val & 0xffff) >= 1, 10, timeout_us);
 
 	return rc;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 876ae8faa8e5f..102c21bb41921 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -769,8 +769,7 @@ static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp,
 	if ((sspp < SSPP_MAX) && catalog && addr && b) {
 		for (i = 0; i < catalog->sspp_count; i++) {
 			if (sspp == catalog->sspp[i].id) {
-				b->base_off = addr;
-				b->blk_off = catalog->sspp[i].base;
+				b->blk_addr = addr + catalog->sspp[i].base;
 				b->log_mask = DPU_DBG_MASK_SSPP;
 				return &catalog->sspp[i];
 			}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
index 843cb607d411f..c3110a25a30d0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
@@ -285,8 +285,7 @@ static const struct dpu_mdp_cfg *_top_offset(enum dpu_mdp mdp,
 
 	for (i = 0; i < m->mdp_count; i++) {
 		if (mdp == m->mdp[i].id) {
-			b->base_off = addr;
-			b->blk_off = m->mdp[i].base;
+			b->blk_addr = addr + m->mdp[i].base;
 			b->log_mask = DPU_DBG_MASK_TOP;
 			return &m->mdp[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
index a679757159e92..8062228eada68 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
@@ -82,13 +82,13 @@ void dpu_reg_write(struct dpu_hw_blk_reg_map *c,
 	/* don't need to mutex protect this */
 	if (c->log_mask & dpu_hw_util_log_mask)
 		DPU_DEBUG_DRIVER("[%s:0x%X] <= 0x%X\n",
-				name, c->blk_off + reg_off, val);
-	writel_relaxed(val, c->base_off + c->blk_off + reg_off);
+				name, reg_off, val);
+	writel_relaxed(val, c->blk_addr + reg_off);
 }
 
 int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off)
 {
-	return readl_relaxed(c->base_off + c->blk_off + reg_off);
+	return readl_relaxed(c->blk_addr + reg_off);
 }
 
 u32 *dpu_hw_util_get_log_mask_ptr(void)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index 28200d31bc5b3..b392e5c4f8958 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -23,12 +23,11 @@
  * This is the common struct maintained by each sub block
  * for mapping the register offsets in this block to the
  * absoulute IO address
- * @base_off:     mdp register mapped offset
- * @blk_off:      pipe offset relative to mdss offset
+ * @blk_addr:     hw block register mapped address
+ * @log_mask:     log mask for this block
  */
 struct dpu_hw_blk_reg_map {
-	void __iomem *base_off;
-	u32 blk_off;
+	void __iomem *blk_addr;
 	u32 log_mask;
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
index 41ca4b179f1a7..16c56e2407064 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
@@ -220,8 +220,7 @@ static const struct dpu_vbif_cfg *_top_offset(enum dpu_vbif vbif,
 
 	for (i = 0; i < m->vbif_count; i++) {
 		if (vbif == m->vbif[i].id) {
-			b->base_off = addr;
-			b->blk_off = m->vbif[i].base;
+			b->blk_addr = addr + m->vbif[i].base;
 			b->log_mask = DPU_DBG_MASK_VBIF;
 			return &m->vbif[i];
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
index 12f32cd3075ee..2d28afdf860ef 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
@@ -60,8 +60,7 @@ static const struct dpu_wb_cfg *_wb_offset(enum dpu_wb wb,
 
 	for (i = 0; i < m->wb_count; i++) {
 		if (wb == m->wb[i].id) {
-			b->base_off = addr;
-			b->blk_off = m->wb[i].base;
+			b->blk_addr = addr + m->wb[i].base;
 			return &m->wb[i];
 		}
 	}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 457f9c911e92f..26d32cd772c18 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -946,7 +946,7 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k
 				dpu_kms->mmio + cat->wb[i].base, "wb_%d", i);
 
 	msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len,
-			dpu_kms->mmio + top->hw.blk_off, "top");
+			dpu_kms->mmio + cat->mdp[0].base, "top");
 
 	pm_runtime_put_sync(&dpu_kms->pdev->dev);
 }
-- 
GitLab


From 4a42c5b5dd938f9775ab7897105ea6089a92c894 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Wed, 1 Jun 2022 19:13:49 +0300
Subject: [PATCH 1631/1731] drm/msm/dpu: move struct dpu_hw_blk definition to
 dpu_hw_utils.h

There is little point in having a separate header just for a single
opaque struct definition. Drop it now and move the struct to the
dpu_hw_util.h header.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/488016/
Link: https://lore.kernel.org/r/20220601161349.1517667-5-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h      |  1 -
 .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c   |  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h    | 25 -------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h    |  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h   |  2 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h   |  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h     |  1 -
 .../gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h    |  1 -
 .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h   |  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h   |  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h    |  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h   |  7 ++++++
 12 files changed, 7 insertions(+), 36 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index af03277a3e5aa..9b67645c25741 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -13,7 +13,6 @@
 #include <drm/drm_crtc.h>
 #include "dpu_kms.h"
 #include "dpu_core_perf.h"
-#include "dpu_hw_blk.h"
 
 #define DPU_CRTC_NAME_SIZE	12
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index d301070cd4a1e..a3480c3f6d335 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -12,7 +12,6 @@
 #include "dpu_hw_top.h"
 #include "dpu_hw_wb.h"
 #include "dpu_hw_lm.h"
-#include "dpu_hw_blk.h"
 #include "dpu_hw_merge3d.h"
 #include "dpu_hw_interrupts.h"
 #include "dpu_core_irq.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h
deleted file mode 100644
index 52e92f37eda41..0000000000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DPU_HW_BLK_H
-#define _DPU_HW_BLK_H
-
-#include <linux/types.h>
-#include <linux/list.h>
-
-struct dpu_hw_blk;
-
-
-/**
- * struct dpu_hw_blk - definition of hardware block object
- * @list: list of hardware blocks
- * @type: hardware block type
- * @id: instance id
- * @refcount: reference/usage count
- */
-struct dpu_hw_blk {
-	/* opaque */
-};
-
-#endif /*_DPU_HW_BLK_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
index 5755307089b52..7d9ad6a3f9f6a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
@@ -10,7 +10,6 @@
 #include "dpu_hw_util.h"
 #include "dpu_hw_catalog.h"
 #include "dpu_hw_sspp.h"
-#include "dpu_hw_blk.h"
 
 /**
  * dpu_ctl_mode_sel: Interface mode selection
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h
index 7fa189cfcb065..05ecfdfac93b7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h
@@ -5,8 +5,6 @@
 #ifndef _DPU_HW_DSPP_H
 #define _DPU_HW_DSPP_H
 
-#include "dpu_hw_blk.h"
-
 struct dpu_hw_dspp;
 
 /**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index 8d0e7b5092602..643dd10bc0306 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -10,7 +10,6 @@
 #include "dpu_hw_catalog.h"
 #include "dpu_hw_mdss.h"
 #include "dpu_hw_util.h"
-#include "dpu_hw_blk.h"
 
 struct dpu_hw_intf;
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
index d8052fb2d5da6..652ddfdedec37 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
@@ -8,7 +8,6 @@
 
 #include "dpu_hw_mdss.h"
 #include "dpu_hw_util.h"
-#include "dpu_hw_blk.h"
 
 struct dpu_hw_mixer;
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h
index 870bdb14613e4..81fd1d5f718e7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h
@@ -8,7 +8,6 @@
 #include "dpu_hw_catalog.h"
 #include "dpu_hw_mdss.h"
 #include "dpu_hw_util.h"
-#include "dpu_hw_blk.h"
 
 struct dpu_hw_merge_3d;
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
index 12758468d9ca1..c00223441d990 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
@@ -8,7 +8,6 @@
 #include "dpu_hw_catalog.h"
 #include "dpu_hw_mdss.h"
 #include "dpu_hw_util.h"
-#include "dpu_hw_blk.h"
 
 #define DITHER_MATRIX_SZ 16
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index 7f7338fcddeb6..78b1bc9e004fd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -8,7 +8,6 @@
 #include "dpu_hw_catalog.h"
 #include "dpu_hw_mdss.h"
 #include "dpu_hw_util.h"
-#include "dpu_hw_blk.h"
 #include "dpu_formats.h"
 
 struct dpu_hw_pipe;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
index 3aa10c89ca1b5..a1a9e44bed36b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
@@ -8,7 +8,6 @@
 #include "dpu_hw_catalog.h"
 #include "dpu_hw_mdss.h"
 #include "dpu_hw_util.h"
-#include "dpu_hw_blk.h"
 
 struct dpu_hw_mdp;
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index b392e5c4f8958..27f4c39e35ab3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -31,6 +31,13 @@ struct dpu_hw_blk_reg_map {
 	u32 log_mask;
 };
 
+/**
+ * struct dpu_hw_blk - opaque hardware block object
+ */
+struct dpu_hw_blk {
+	/* opaque */
+};
+
 /**
  * struct dpu_hw_scaler3_de_cfg : QSEEDv3 detail enhancer configuration
  * @enable:         detail enhancer enable/disable
-- 
GitLab


From ba0386a9c4827725e0fa677112941268f7b45e23 Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Wed, 15 Jun 2022 09:35:28 -0700
Subject: [PATCH 1632/1731] drm/msm: Fix %d vs %u

In debugging fence rollover, I noticed that GPU state capture and
devcore dumps were showing me negative fence numbers.  Let's fix that
and some related signed vs unsigned confusion.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/489621/
Link: https://lore.kernel.org/r/20220615163532.3013035-1-robdclark@gmail.com
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 73c0d01ee31d5..8d03e30f14c00 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -807,11 +807,11 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
 	for (i = 0; i < gpu->nr_rings; i++) {
 		drm_printf(p, "  - id: %d\n", i);
 		drm_printf(p, "    iova: 0x%016llx\n", state->ring[i].iova);
-		drm_printf(p, "    last-fence: %d\n", state->ring[i].seqno);
-		drm_printf(p, "    retired-fence: %d\n", state->ring[i].fence);
-		drm_printf(p, "    rptr: %d\n", state->ring[i].rptr);
-		drm_printf(p, "    wptr: %d\n", state->ring[i].wptr);
-		drm_printf(p, "    size: %d\n", MSM_GPU_RINGBUFFER_SZ);
+		drm_printf(p, "    last-fence: %u\n", state->ring[i].seqno);
+		drm_printf(p, "    retired-fence: %u\n", state->ring[i].fence);
+		drm_printf(p, "    rptr: %u\n", state->ring[i].rptr);
+		drm_printf(p, "    wptr: %u\n", state->ring[i].wptr);
+		drm_printf(p, "    size: %u\n", MSM_GPU_RINGBUFFER_SZ);
 
 		adreno_show_object(p, &state->ring[i].data,
 			state->ring[i].data_size, &state->ring[i].encoded);
-- 
GitLab


From a07ea70a57e258289acc1bc41360c384cc53ec22 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 16 Jun 2022 11:11:02 +0300
Subject: [PATCH 1633/1731] drm/msm/dpu: check both DPU and MDSS devices for
 the IOMMU

Follow the lead of MDP5 driver and check both DPU and MDSS devices for
the IOMMU specifiers.

Historically DPU devices had IOMMU specified in the MDSS device tree
node, but as some of MDP5 devices are being converted to the supported
by the DPU driver, the driver should adapt and check both devices.

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/489696/
Link: https://lore.kernel.org/r/20220616081106.350262-2-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 26d32cd772c18..6401bead29c2e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -997,14 +997,22 @@ static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms)
 	struct msm_mmu *mmu;
 	struct device *dpu_dev = dpu_kms->dev->dev;
 	struct device *mdss_dev = dpu_dev->parent;
+	struct device *iommu_dev;
 
 	domain = iommu_domain_alloc(&platform_bus_type);
 	if (!domain)
 		return 0;
 
-	/* IOMMUs are a part of MDSS device tree binding, not the
-	 * MDP/DPU device. */
-	mmu = msm_iommu_new(mdss_dev, domain);
+	/*
+	 * IOMMUs can be a part of MDSS device tree binding, or the
+	 * MDP/DPU device.
+	 */
+	if (dev_iommu_fwspec_get(dpu_dev))
+		iommu_dev = dpu_dev;
+	else
+		iommu_dev = mdss_dev;
+
+	mmu = msm_iommu_new(iommu_dev, domain);
 	if (IS_ERR(mmu)) {
 		iommu_domain_free(domain);
 		return PTR_ERR(mmu);
-- 
GitLab


From 8010b14e6219c0060716c885a89658060a388544 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 16 Jun 2022 11:11:03 +0300
Subject: [PATCH 1634/1731] drm/msm/mdp5: move iommu_domain_alloc() call close
 to its usage

Move iommu_domain_alloc() in front of adress space/IOMMU initialization.
This allows us to drop final bits of struct mdp5_cfg_platform which
remained from the pre-DT days.

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/489695/
Link: https://lore.kernel.org/r/20220616081106.350262-3-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 16 ----------------
 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h |  6 ------
 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c |  6 ++++--
 3 files changed, 4 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
index b17f868ffca83..1f1555aa02d23 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
@@ -1253,8 +1253,6 @@ static const struct mdp5_cfg_handler cfg_handlers_v3[] = {
 	{ .revision = 3, .config = { .hw = &sdm630_config } },
 };
 
-static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev);
-
 const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_handler)
 {
 	return cfg_handler->config.hw;
@@ -1279,10 +1277,8 @@ struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
 		uint32_t major, uint32_t minor)
 {
 	struct drm_device *dev = mdp5_kms->dev;
-	struct platform_device *pdev = to_platform_device(dev->dev);
 	struct mdp5_cfg_handler *cfg_handler;
 	const struct mdp5_cfg_handler *cfg_handlers;
-	struct mdp5_cfg_platform *pconfig;
 	int i, ret = 0, num_handlers;
 
 	cfg_handler = kzalloc(sizeof(*cfg_handler), GFP_KERNEL);
@@ -1325,9 +1321,6 @@ struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
 	cfg_handler->revision = minor;
 	cfg_handler->config.hw = mdp5_cfg;
 
-	pconfig = mdp5_get_config(pdev);
-	memcpy(&cfg_handler->config.platform, pconfig, sizeof(*pconfig));
-
 	DBG("MDP5: %s hw config selected", mdp5_cfg->name);
 
 	return cfg_handler;
@@ -1338,12 +1331,3 @@ fail:
 
 	return ERR_PTR(ret);
 }
-
-static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev)
-{
-	static struct mdp5_cfg_platform config = {};
-
-	config.iommu = iommu_domain_alloc(&platform_bus_type);
-
-	return &config;
-}
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h
index 6b03d7899309a..c2502cc338646 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h
@@ -104,14 +104,8 @@ struct mdp5_cfg_hw {
 	uint32_t max_clk;
 };
 
-/* platform config data (ie. from DT, or pdata) */
-struct mdp5_cfg_platform {
-	struct iommu_domain *iommu;
-};
-
 struct mdp5_cfg {
 	const struct mdp5_cfg_hw *hw;
-	struct mdp5_cfg_platform platform;
 };
 
 struct mdp5_kms;
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
index 3d5621a68f858..a69e23f10d918 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
@@ -558,6 +558,7 @@ static int mdp5_kms_init(struct drm_device *dev)
 	struct msm_gem_address_space *aspace;
 	int irq, i, ret;
 	struct device *iommu_dev;
+	struct iommu_domain *iommu;
 
 	ret = mdp5_init(to_platform_device(dev->dev), dev);
 
@@ -601,14 +602,15 @@ static int mdp5_kms_init(struct drm_device *dev)
 	}
 	mdelay(16);
 
-	if (config->platform.iommu) {
+	iommu = iommu_domain_alloc(&platform_bus_type);
+	if (iommu) {
 		struct msm_mmu *mmu;
 
 		iommu_dev = &pdev->dev;
 		if (!dev_iommu_fwspec_get(iommu_dev))
 			iommu_dev = iommu_dev->parent;
 
-		mmu = msm_iommu_new(iommu_dev, config->platform.iommu);
+		mmu = msm_iommu_new(iommu_dev, iommu);
 
 		aspace = msm_gem_address_space_create(mmu, "mdp5",
 			0x1000, 0x100000000 - 0x1000);
-- 
GitLab


From 73029c9b23cf1213e5f54c2b59efce08665199e7 Mon Sep 17 00:00:00 2001
From: Keith Busch <kbusch@kernel.org>
Date: Tue, 5 Jul 2022 10:21:02 -0700
Subject: [PATCH 1635/1731] nvme-pci: phison e16 has bogus namespace ids

Add the quirk.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=216049
Reported-by: Chris Egolf <cegolf@ugholf.net>
Signed-off-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Chaitanya Kulkarni <kch@nvidia.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/host/pci.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index e7af2234e53b9..193b447556628 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -3465,7 +3465,8 @@ static const struct pci_device_id nvme_id_table[] = {
 	{ PCI_DEVICE(0x1987, 0x5012),	/* Phison E12 */
 		.driver_data = NVME_QUIRK_BOGUS_NID, },
 	{ PCI_DEVICE(0x1987, 0x5016),	/* Phison E16 */
-		.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
+		.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
+				NVME_QUIRK_BOGUS_NID, },
 	{ PCI_DEVICE(0x1b4b, 0x1092),	/* Lexar 256 GB SSD */
 		.driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
 				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
-- 
GitLab


From 607a48c78e6b427b0b684d24e61c19e846ad65d6 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Fri, 1 Jul 2022 22:19:02 -0500
Subject: [PATCH 1636/1731] dt-bindings: dma: allwinner,sun50i-a64-dma: Fix
 min/max typo

The conditional block for variants with a second clock should have set
minItems, not maxItems, which was already 2. Since clock-names requires
two items, this typo should not have caused any problems.

Fixes: edd14218bd66 ("dt-bindings: dmaengine: Convert Allwinner A31 and A64 DMA to a schema")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220702031903.21703-1-samuel@sholland.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 .../devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml       | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml
index ff0a5c58d78cc..e712444abff17 100644
--- a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml
+++ b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml
@@ -67,7 +67,7 @@ if:
 then:
   properties:
     clocks:
-      maxItems: 2
+      minItems: 2
 
   required:
     - clock-names
-- 
GitLab


From 5c629dc9609dc43492a7bc8060cc6120875bf096 Mon Sep 17 00:00:00 2001
From: Keith Busch <kbusch@kernel.org>
Date: Wed, 6 Jul 2022 10:05:05 -0700
Subject: [PATCH 1637/1731] nvme: use struct group for generic command dwords

This will allow the trace event to know the full size of the data
intended to be copied and silence read overflow checks.

Reported-by: John Garry <john.garry@huawei.com>
Suggested-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/host/trace.h | 2 +-
 include/linux/nvme.h      | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/nvme/host/trace.h b/drivers/nvme/host/trace.h
index b5f85259461a6..37c7f4c89f92e 100644
--- a/drivers/nvme/host/trace.h
+++ b/drivers/nvme/host/trace.h
@@ -69,7 +69,7 @@ TRACE_EVENT(nvme_setup_cmd,
 		__entry->metadata = !!blk_integrity_rq(req);
 		__entry->fctype = cmd->fabrics.fctype;
 		__assign_disk_name(__entry->disk, req->q->disk);
-		memcpy(__entry->cdw10, &cmd->common.cdw10,
+		memcpy(__entry->cdw10, &cmd->common.cdws,
 			sizeof(__entry->cdw10));
 	    ),
 	    TP_printk("nvme%d: %sqid=%d, cmdid=%u, nsid=%u, flags=0x%x, meta=0x%x, cmd=(%s %s)",
diff --git a/include/linux/nvme.h b/include/linux/nvme.h
index e3934003f2397..07cfc922f8e48 100644
--- a/include/linux/nvme.h
+++ b/include/linux/nvme.h
@@ -906,12 +906,14 @@ struct nvme_common_command {
 	__le32			cdw2[2];
 	__le64			metadata;
 	union nvme_data_ptr	dptr;
+	struct_group(cdws,
 	__le32			cdw10;
 	__le32			cdw11;
 	__le32			cdw12;
 	__le32			cdw13;
 	__le32			cdw14;
 	__le32			cdw15;
+	);
 };
 
 struct nvme_rw_command {
-- 
GitLab


From ca1dc50fd5cfd7420faa46183f84bc203fae156a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Thu, 30 Jun 2022 18:05:58 +0300
Subject: [PATCH 1638/1731] drm/i915: Use short PCH names consistently
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The comments regarding PCH compatibility use long vs.
short names inconsistently. Just use short names always.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220630150600.24611-2-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_pch.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index e2b2bbdc07148..94446cac66052 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -25,7 +25,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 		drm_dbg_kms(&dev_priv->drm, "Found PantherPoint PCH\n");
 		drm_WARN_ON(&dev_priv->drm,
 			    GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv));
-		/* PantherPoint is CPT compatible */
+		/* PPT is CPT compatible */
 		return PCH_CPT;
 	case INTEL_PCH_LPT_DEVICE_ID_TYPE:
 		drm_dbg_kms(&dev_priv->drm, "Found LynxPoint PCH\n");
@@ -47,7 +47,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 			    !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 		drm_WARN_ON(&dev_priv->drm,
 			    IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
-		/* WildcatPoint is LPT compatible */
+		/* WPT is LPT compatible */
 		return PCH_LPT;
 	case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
 		drm_dbg_kms(&dev_priv->drm, "Found WildcatPoint LP PCH\n");
@@ -55,7 +55,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 			    !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 		drm_WARN_ON(&dev_priv->drm,
 			    !IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
-		/* WildcatPoint is LPT compatible */
+		/* WPT is LPT compatible */
 		return PCH_LPT;
 	case INTEL_PCH_SPT_DEVICE_ID_TYPE:
 		drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint PCH\n");
@@ -99,14 +99,14 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 			    !IS_COFFEELAKE(dev_priv) &&
 			    !IS_COMETLAKE(dev_priv) &&
 			    !IS_ROCKETLAKE(dev_priv));
-		/* CometPoint is CNP Compatible */
+		/* CMP is CNP compatible */
 		return PCH_CNP;
 	case INTEL_PCH_CMP_V_DEVICE_ID_TYPE:
 		drm_dbg_kms(&dev_priv->drm, "Found Comet Lake V PCH (CMP-V)\n");
 		drm_WARN_ON(&dev_priv->drm,
 			    !IS_COFFEELAKE(dev_priv) &&
 			    !IS_COMETLAKE(dev_priv));
-		/* Comet Lake V PCH is based on KBP, which is SPT compatible */
+		/* CMP-V is based on KBP, which is SPT compatible */
 		return PCH_SPT;
 	case INTEL_PCH_ICP_DEVICE_ID_TYPE:
 	case INTEL_PCH_ICP2_DEVICE_ID_TYPE:
-- 
GitLab


From f24d1d45084155c59a135506a37bc4db10703fe6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Thu, 30 Jun 2022 18:05:59 +0300
Subject: [PATCH 1639/1731] drm/i915: Nuke PCH_MCC
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

MCC is derived from TGP, and we have no real need to
differentiate between the two. Thus remove PCH_MCC and
just declare it to be PCH_TGP compatible.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220630150600.24611-3-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c  | 2 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
 drivers/gpu/drm/i915/intel_pch.c          | 3 ++-
 drivers/gpu/drm/i915/intel_pch.h          | 4 +---
 4 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 5d448e0563be4..f76eb6e345ec9 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4179,7 +4179,7 @@ static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv,
 	if (port == PORT_D)
 		return HPD_PORT_A;
 
-	if (HAS_PCH_MCC(dev_priv))
+	if (HAS_PCH_TGP(dev_priv))
 		return icl_hpd_pin(dev_priv, port);
 
 	return HPD_PORT_A + port - PORT_A;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index a4a6f8bd2841e..cb6898cbe1c8f 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2851,7 +2851,7 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
 		ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
 	else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
 		ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
-	else if (HAS_PCH_MCC(dev_priv))
+	else if (IS_JSL_EHL(dev_priv) && HAS_PCH_TGP(dev_priv))
 		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index 94446cac66052..b45c504c6f033 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -116,7 +116,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 	case INTEL_PCH_MCC_DEVICE_ID_TYPE:
 		drm_dbg_kms(&dev_priv->drm, "Found Mule Creek Canyon PCH\n");
 		drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
-		return PCH_MCC;
+		/* MCC is TGP compatible */
+		return PCH_TGP;
 	case INTEL_PCH_TGP_DEVICE_ID_TYPE:
 	case INTEL_PCH_TGP2_DEVICE_ID_TYPE:
 		drm_dbg_kms(&dev_priv->drm, "Found Tiger Lake LP PCH\n");
diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
index b7a8cf409d483..07f6f5517968d 100644
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@ -24,8 +24,7 @@ enum intel_pch {
 	PCH_CNP,        /* Cannon/Comet Lake PCH */
 	PCH_ICP,	/* Ice Lake PCH */
 	PCH_JSP,	/* Jasper Lake PCH */
-	PCH_MCC,        /* Mule Creek Canyon PCH */
-	PCH_TGP,	/* Tiger Lake PCH */
+	PCH_TGP,	/* Tiger Lake/Mule Creek Canyon PCH */
 	PCH_ADP,	/* Alder Lake PCH */
 
 	/* Fake PCHs, functionality handled on the same PCI dev */
@@ -69,7 +68,6 @@ enum intel_pch {
 #define HAS_PCH_ADP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
 #define HAS_PCH_DG1(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
 #define HAS_PCH_JSP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
-#define HAS_PCH_MCC(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
 #define HAS_PCH_TGP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
 #define HAS_PCH_ICP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
 #define HAS_PCH_CNP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
-- 
GitLab


From 3d9c653cf635849d0c24a1ab17c2752a19f4ded8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Thu, 30 Jun 2022 18:06:00 +0300
Subject: [PATCH 1640/1731] drm/i915: Nuke PCH_JSP
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

JSP is based on ICP and we don't really need to differentiate
between the two. So let's just delcare JSP to be ICP.

The only slight change here is for Wa_14011294188 which we
used to apply for JSP but now we'll only apply to MCC. This
should be fine since the issue being dealt with was introduced
in TGP and inherited into MCC. JSP being derived from ICP
should not need this workaround.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220630150600.24611-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
 drivers/gpu/drm/i915/intel_pch.c                   | 3 ++-
 drivers/gpu/drm/i915/intel_pch.h                   | 4 +---
 3 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index a9cb27f1c964a..589af257edebc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1608,7 +1608,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
 	/* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
 	    INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
 		intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
 			     PCH_DPMGUNIT_CLOCK_GATE_DISABLE);
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index b45c504c6f033..0fec25be146a2 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -128,7 +128,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 	case INTEL_PCH_JSP_DEVICE_ID_TYPE:
 		drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
 		drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
-		return PCH_JSP;
+		/* JSP is ICP compatible */
+		return PCH_ICP;
 	case INTEL_PCH_ADP_DEVICE_ID_TYPE:
 	case INTEL_PCH_ADP2_DEVICE_ID_TYPE:
 	case INTEL_PCH_ADP3_DEVICE_ID_TYPE:
diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
index 07f6f5517968d..7c8ce9781d1a2 100644
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@ -22,8 +22,7 @@ enum intel_pch {
 	PCH_LPT,	/* Lynxpoint/Wildcatpoint PCH */
 	PCH_SPT,        /* Sunrisepoint/Kaby Lake PCH */
 	PCH_CNP,        /* Cannon/Comet Lake PCH */
-	PCH_ICP,	/* Ice Lake PCH */
-	PCH_JSP,	/* Jasper Lake PCH */
+	PCH_ICP,	/* Ice Lake/Jasper Lake PCH */
 	PCH_TGP,	/* Tiger Lake/Mule Creek Canyon PCH */
 	PCH_ADP,	/* Alder Lake PCH */
 
@@ -67,7 +66,6 @@ enum intel_pch {
 #define HAS_PCH_DG2(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
 #define HAS_PCH_ADP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
 #define HAS_PCH_DG1(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
-#define HAS_PCH_JSP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
 #define HAS_PCH_TGP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
 #define HAS_PCH_ICP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
 #define HAS_PCH_CNP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
-- 
GitLab


From 8cb72adb1c6618c77fdf3e7c8acd8876d6d1b0b7 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 16 Jun 2022 11:11:04 +0300
Subject: [PATCH 1641/1731] drm/msm: Stop using iommu_present()

Even if some IOMMU has registered itself on the platform "bus", that
doesn't necessarily mean it provides translation for the device we
care about. Replace iommu_present() with a more appropriate check.

On Qualcomm platforms the IOMMU can be specified either for the MDP/DPU
device or for its parent MDSS device depending on the actual platform.
Check both of them, since that is how both DPU and MDP5 drivers work.

Co-developed-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/489699/
Link: https://lore.kernel.org/r/20220616081106.350262-4-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/msm_drv.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 57a66093e6711..df0df55d26f92 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -271,8 +271,14 @@ bool msm_use_mmu(struct drm_device *dev)
 {
 	struct msm_drm_private *priv = dev->dev_private;
 
-	/* a2xx comes with its own MMU */
-	return priv->is_a2xx || iommu_present(&platform_bus_type);
+	/*
+	 * a2xx comes with its own MMU
+	 * On other platforms IOMMU can be declared specified either for the
+	 * MDP/DPU device or for its parent, MDSS device.
+	 */
+	return priv->is_a2xx ||
+		device_iommu_mapped(dev->dev) ||
+		device_iommu_mapped(dev->dev->parent);
 }
 
 static int msm_init_vram(struct drm_device *dev)
-- 
GitLab


From 40ae54ed734a112c09fb80e2ee16a6bbb733aed4 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 16 Jun 2022 11:11:05 +0300
Subject: [PATCH 1642/1731] drm/msm: move KMS aspace init to the separate
 helper

MDP5 and DPU drivers have the same piece of code now to initialize
IOMMU and GEM address space. Move it to the msm_drv.c

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/489701/
Link: https://lore.kernel.org/r/20220616081106.350262-5-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c  | 32 ++-----------------
 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 33 ++++----------------
 drivers/gpu/drm/msm/msm_drv.c            | 39 ++++++++++++++++++++++++
 drivers/gpu/drm/msm/msm_drv.h            |  1 +
 4 files changed, 49 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 6401bead29c2e..c92f804679558 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -992,40 +992,14 @@ static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms)
 
 static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms)
 {
-	struct iommu_domain *domain;
 	struct msm_gem_address_space *aspace;
-	struct msm_mmu *mmu;
-	struct device *dpu_dev = dpu_kms->dev->dev;
-	struct device *mdss_dev = dpu_dev->parent;
-	struct device *iommu_dev;
-
-	domain = iommu_domain_alloc(&platform_bus_type);
-	if (!domain)
-		return 0;
-
-	/*
-	 * IOMMUs can be a part of MDSS device tree binding, or the
-	 * MDP/DPU device.
-	 */
-	if (dev_iommu_fwspec_get(dpu_dev))
-		iommu_dev = dpu_dev;
-	else
-		iommu_dev = mdss_dev;
-
-	mmu = msm_iommu_new(iommu_dev, domain);
-	if (IS_ERR(mmu)) {
-		iommu_domain_free(domain);
-		return PTR_ERR(mmu);
-	}
-	aspace = msm_gem_address_space_create(mmu, "dpu1",
-		0x1000, 0x100000000 - 0x1000);
 
-	if (IS_ERR(aspace)) {
-		mmu->funcs->destroy(mmu);
+	aspace = msm_kms_init_aspace(dpu_kms->dev);
+	if (IS_ERR(aspace))
 		return PTR_ERR(aspace);
-	}
 
 	dpu_kms->base.aspace = aspace;
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
index a69e23f10d918..d2a48caf9d27e 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
@@ -557,8 +557,6 @@ static int mdp5_kms_init(struct drm_device *dev)
 	struct msm_kms *kms;
 	struct msm_gem_address_space *aspace;
 	int irq, i, ret;
-	struct device *iommu_dev;
-	struct iommu_domain *iommu;
 
 	ret = mdp5_init(to_platform_device(dev->dev), dev);
 
@@ -602,33 +600,14 @@ static int mdp5_kms_init(struct drm_device *dev)
 	}
 	mdelay(16);
 
-	iommu = iommu_domain_alloc(&platform_bus_type);
-	if (iommu) {
-		struct msm_mmu *mmu;
-
-		iommu_dev = &pdev->dev;
-		if (!dev_iommu_fwspec_get(iommu_dev))
-			iommu_dev = iommu_dev->parent;
-
-		mmu = msm_iommu_new(iommu_dev, iommu);
-
-		aspace = msm_gem_address_space_create(mmu, "mdp5",
-			0x1000, 0x100000000 - 0x1000);
-
-		if (IS_ERR(aspace)) {
-			if (!IS_ERR(mmu))
-				mmu->funcs->destroy(mmu);
-			ret = PTR_ERR(aspace);
-			goto fail;
-		}
-
-		kms->aspace = aspace;
-	} else {
-		DRM_DEV_INFO(&pdev->dev,
-			 "no iommu, fallback to phys contig buffers for scanout\n");
-		aspace = NULL;
+	aspace = msm_kms_init_aspace(mdp5_kms->dev);
+	if (IS_ERR(aspace)) {
+		ret = PTR_ERR(aspace);
+		goto fail;
 	}
 
+	kms->aspace = aspace;
+
 	pm_runtime_put_sync(&pdev->dev);
 
 	ret = modeset_init(mdp5_kms);
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index df0df55d26f92..1182c9f81bfdb 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -26,6 +26,7 @@
 #include "msm_gem.h"
 #include "msm_gpu.h"
 #include "msm_kms.h"
+#include "msm_mmu.h"
 #include "adreno/adreno_gpu.h"
 
 /*
@@ -267,6 +268,44 @@ static int msm_drm_uninit(struct device *dev)
 
 #include <linux/of_address.h>
 
+struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev)
+{
+	struct iommu_domain *domain;
+	struct msm_gem_address_space *aspace;
+	struct msm_mmu *mmu;
+	struct device *mdp_dev = dev->dev;
+	struct device *mdss_dev = mdp_dev->parent;
+	struct device *iommu_dev;
+
+	domain = iommu_domain_alloc(&platform_bus_type);
+	if (!domain) {
+		drm_info(dev, "no IOMMU, fallback to phys contig buffers for scanout\n");
+		return NULL;
+	}
+
+	/*
+	 * IOMMUs can be a part of MDSS device tree binding, or the
+	 * MDP/DPU device.
+	 */
+	if (dev_iommu_fwspec_get(mdp_dev))
+		iommu_dev = mdp_dev;
+	else
+		iommu_dev = mdss_dev;
+
+	mmu = msm_iommu_new(iommu_dev, domain);
+	if (IS_ERR(mmu)) {
+		iommu_domain_free(domain);
+		return ERR_CAST(mmu);
+	}
+
+	aspace = msm_gem_address_space_create(mmu, "mdp_kms",
+		0x1000, 0x100000000 - 0x1000);
+	if (IS_ERR(aspace))
+		mmu->funcs->destroy(mmu);
+
+	return aspace;
+}
+
 bool msm_use_mmu(struct drm_device *dev)
 {
 	struct msm_drm_private *priv = dev->dev_private;
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index ae49e56ac0268..b3689a2d27d72 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -224,6 +224,7 @@ void msm_crtc_disable_vblank(struct drm_crtc *crtc);
 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
 
+struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev);
 bool msm_use_mmu(struct drm_device *dev);
 
 int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
-- 
GitLab


From b571cb5273ad2feacc75ab2d951d950534aa589d Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 16 Jun 2022 11:11:06 +0300
Subject: [PATCH 1643/1731] drm/msm: switch msm_kms_init_aspace() to use
 device_iommu_mapped()

Change msm_kms_init_aspace() to use generic function
device_iommu_mapped() instead of the fwnode-specific interface
dev_iommu_fwspec_get(). While we are at it, stop referencing
platform_bus_type directly and use the bus of the IOMMU device.

Suggested-by: Robin Murphy <robin.murphy@arm.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/489703/
Link: https://lore.kernel.org/r/20220616081106.350262-6-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/msm_drv.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 1182c9f81bfdb..984b937735543 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -277,21 +277,21 @@ struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev)
 	struct device *mdss_dev = mdp_dev->parent;
 	struct device *iommu_dev;
 
-	domain = iommu_domain_alloc(&platform_bus_type);
-	if (!domain) {
-		drm_info(dev, "no IOMMU, fallback to phys contig buffers for scanout\n");
-		return NULL;
-	}
-
 	/*
 	 * IOMMUs can be a part of MDSS device tree binding, or the
 	 * MDP/DPU device.
 	 */
-	if (dev_iommu_fwspec_get(mdp_dev))
+	if (device_iommu_mapped(mdp_dev))
 		iommu_dev = mdp_dev;
 	else
 		iommu_dev = mdss_dev;
 
+	domain = iommu_domain_alloc(iommu_dev->bus);
+	if (!domain) {
+		drm_info(dev, "no IOMMU, fallback to phys contig buffers for scanout\n");
+		return NULL;
+	}
+
 	mmu = msm_iommu_new(iommu_dev, domain);
 	if (IS_ERR(mmu)) {
 		iommu_domain_free(domain);
-- 
GitLab


From cc66a42c94b11b4a92068a730773283a28937571 Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Wed, 29 Jun 2022 14:19:15 -0700
Subject: [PATCH 1644/1731] drm/msm/gpu: Capture all BO addr+size in devcore

It is useful to know what buffers userspace thinks are associated with
the submit, even if we don't care to capture their content.  This brings
things more inline with $debugfs/rd cmdstream dumping.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/491908/
Link: https://lore.kernel.org/r/20220629211919.563585-2-robdclark@gmail.com
---
 drivers/gpu/drm/msm/msm_gpu.c | 36 ++++++++---------------------------
 1 file changed, 8 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 484346daa05f3..3314a137be3b9 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -221,7 +221,7 @@ static void msm_gpu_devcoredump_free(void *data)
 }
 
 static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state,
-		struct msm_gem_object *obj, u64 iova, u32 flags)
+		struct msm_gem_object *obj, u64 iova, bool full)
 {
 	struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos];
 
@@ -229,8 +229,7 @@ static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state,
 	state_bo->size = obj->base.size;
 	state_bo->iova = iova;
 
-	/* Only store data for non imported buffer objects marked for read */
-	if ((flags & MSM_SUBMIT_BO_READ) && !obj->base.import_attach) {
+	if (full) {
 		void *ptr;
 
 		state_bo->data = kvmalloc(obj->base.size, GFP_KERNEL);
@@ -276,34 +275,15 @@ static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
 	state->fault_info = gpu->fault_info;
 
 	if (submit) {
-		int i, nr = 0;
-
-		/* count # of buffers to dump: */
-		for (i = 0; i < submit->nr_bos; i++)
-			if (should_dump(submit, i))
-				nr++;
-		/* always dump cmd bo's, but don't double count them: */
-		for (i = 0; i < submit->nr_cmds; i++)
-			if (!should_dump(submit, submit->cmd[i].idx))
-				nr++;
-
-		state->bos = kcalloc(nr,
+		int i;
+
+		state->bos = kcalloc(submit->nr_bos,
 			sizeof(struct msm_gpu_state_bo), GFP_KERNEL);
 
 		for (i = 0; state->bos && i < submit->nr_bos; i++) {
-			if (should_dump(submit, i)) {
-				msm_gpu_crashstate_get_bo(state, submit->bos[i].obj,
-					submit->bos[i].iova, submit->bos[i].flags);
-			}
-		}
-
-		for (i = 0; state->bos && i < submit->nr_cmds; i++) {
-			int idx = submit->cmd[i].idx;
-
-			if (!should_dump(submit, submit->cmd[i].idx)) {
-				msm_gpu_crashstate_get_bo(state, submit->bos[idx].obj,
-					submit->bos[idx].iova, submit->bos[idx].flags);
-			}
+			msm_gpu_crashstate_get_bo(state, submit->bos[i].obj,
+						  submit->bos[i].iova,
+						  should_dump(submit, i));
 		}
 	}
 
-- 
GitLab


From 18514c3848cf86f3e2843c9cfc218c8471a1984e Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Wed, 29 Jun 2022 14:19:16 -0700
Subject: [PATCH 1645/1731] drm/msm/gpu: Add GEM debug label to devcore

When trying to understand an iova fault devcore, once you figure out
which buffer we accessed beyond the end of, it is useful to see the
buffer's debug label.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/491910/
Link: https://lore.kernel.org/r/20220629211919.563585-3-robdclark@gmail.com
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 +
 drivers/gpu/drm/msm/msm_gpu.c           | 4 ++++
 drivers/gpu/drm/msm/msm_gpu.h           | 1 +
 3 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 8d03e30f14c00..a049d5de338ad 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -824,6 +824,7 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
 			drm_printf(p, "  - iova: 0x%016llx\n",
 				state->bos[i].iova);
 			drm_printf(p, "    size: %zd\n", state->bos[i].size);
+			drm_printf(p, "    name: %-32s\n", state->bos[i].name);
 
 			adreno_show_object(p, &state->bos[i].data,
 				state->bos[i].size, &state->bos[i].encoded);
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 3314a137be3b9..e1ee85025b67a 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -229,6 +229,10 @@ static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state,
 	state_bo->size = obj->base.size;
 	state_bo->iova = iova;
 
+	BUILD_BUG_ON(sizeof(state_bo->name) != sizeof(obj->name));
+
+	memcpy(state_bo->name, obj->name, sizeof(state_bo->name));
+
 	if (full) {
 		void *ptr;
 
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index fefcf2c8fe659..4d935fedd2acc 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -489,6 +489,7 @@ struct msm_gpu_state_bo {
 	size_t size;
 	void *data;
 	bool encoded;
+	char name[32];
 };
 
 struct msm_gpu_state {
-- 
GitLab


From d7499634db4f43d3347ae58c5931ad1c795d4cbf Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert@linux-m68k.org>
Date: Wed, 6 Jul 2022 15:18:48 +0200
Subject: [PATCH 1646/1731] drm/msm/adreno: Do not propagate void return values

With sparse ("make C=2"), lots of

  error: return expression in void function

messages are seen.

Fix this by removing the return statements to propagate void return
values.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Patchwork: https://patchwork.freedesktop.org/patch/492529/
Link: https://lore.kernel.org/r/0083bc7e23753c19902580b902582ae499b44dbf.1657113388.git.geert@linux-m68k.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
 drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 4 ++--
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index c6660307e437b..310a317885a12 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -505,7 +505,7 @@ static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
 
 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)
 {
-	return msm_writel(value, ptr + (offset << 2));
+	msm_writel(value, ptr + (offset << 2));
 }
 
 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
index 84bd516f01e89..e034935b3986f 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
@@ -98,7 +98,7 @@ static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
 
 static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
 {
-	return msm_writel(value, gmu->mmio + (offset << 2));
+	msm_writel(value, gmu->mmio + (offset << 2));
 }
 
 static inline void
@@ -138,7 +138,7 @@ static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)
 
 static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value)
 {
-	return msm_writel(value, gmu->rscc + (offset << 2));
+	msm_writel(value, gmu->rscc + (offset << 2));
 }
 
 #define gmu_poll_timeout_rscc(gmu, addr, val, cond, interval, timeout) \
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 0a3a176649da5..4d501100b9e45 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1514,7 +1514,7 @@ static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)
 
 static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
 {
-	return msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));
+	msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));
 }
 
 static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu)
-- 
GitLab


From bce1e40568cbe7bee1c1425f2269673fd1f3c28b Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Sat, 18 Jun 2022 02:24:32 +0300
Subject: [PATCH 1647/1731] drm/msm/dp: remove unused stubs

Refactoring DP code transformed several functions into empty stubs.
Remove them.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/490100/
Link: https://lore.kernel.org/r/20220617232434.1139950-1-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/dp/dp_display.c | 35 -----------------------------
 1 file changed, 35 deletions(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index b36f8b69a2445..2dccc23487bcd 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -867,11 +867,6 @@ static int dp_display_set_mode(struct msm_dp *dp_display,
 	return 0;
 }
 
-static int dp_display_prepare(struct msm_dp *dp_display)
-{
-	return 0;
-}
-
 static int dp_display_enable(struct dp_display_private *dp, u32 data)
 {
 	int rc = 0;
@@ -948,11 +943,6 @@ static int dp_display_disable(struct dp_display_private *dp, u32 data)
 	return 0;
 }
 
-static int dp_display_unprepare(struct msm_dp *dp_display)
-{
-	return 0;
-}
-
 int dp_display_set_plugged_cb(struct msm_dp *dp_display,
 		hdmi_codec_plugged_cb fn, struct device *codec_dev)
 {
@@ -1468,21 +1458,9 @@ static int dp_pm_suspend(struct device *dev)
 	return 0;
 }
 
-static int dp_pm_prepare(struct device *dev)
-{
-	return 0;
-}
-
-static void dp_pm_complete(struct device *dev)
-{
-
-}
-
 static const struct dev_pm_ops dp_pm_ops = {
 	.suspend = dp_pm_suspend,
 	.resume =  dp_pm_resume,
-	.prepare = dp_pm_prepare,
-	.complete = dp_pm_complete,
 };
 
 static struct platform_driver dp_display_driver = {
@@ -1694,13 +1672,6 @@ void dp_bridge_enable(struct drm_bridge *drm_bridge)
 		return;
 	}
 
-	rc = dp_display_prepare(dp);
-	if (rc) {
-		DRM_ERROR("DP display prepare failed, rc=%d\n", rc);
-		mutex_unlock(&dp_display->event_mutex);
-		return;
-	}
-
 	state =  dp_display->hpd_state;
 
 	if (state == ST_DISPLAY_OFF) {
@@ -1714,7 +1685,6 @@ void dp_bridge_enable(struct drm_bridge *drm_bridge)
 	if (rc) {
 		DRM_ERROR("DP display post enable failed, rc=%d\n", rc);
 		dp_display_disable(dp_display, 0);
-		dp_display_unprepare(dp);
 	}
 
 	/* completed connection */
@@ -1739,7 +1709,6 @@ void dp_bridge_post_disable(struct drm_bridge *drm_bridge)
 {
 	struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge);
 	struct msm_dp *dp = dp_bridge->dp_display;
-	int rc = 0;
 	u32 state;
 	struct dp_display_private *dp_display;
 
@@ -1758,10 +1727,6 @@ void dp_bridge_post_disable(struct drm_bridge *drm_bridge)
 
 	dp_display_disable(dp_display, 0);
 
-	rc = dp_display_unprepare(dp);
-	if (rc)
-		DRM_ERROR("DP display unprepare failed, rc=%d\n", rc);
-
 	state =  dp_display->hpd_state;
 	if (state == ST_DISCONNECT_PENDING) {
 		/* completed disconnection */
-- 
GitLab


From 786a4f668550f8576c28d167fd50f4ef84af8ba4 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Sat, 18 Jun 2022 02:24:33 +0300
Subject: [PATCH 1648/1731] drm/msm/dp: rename second dp_display_enable()'s
 argument

To follow up recent changes, rename (and change type of) second
dp_display_enable()'s argument from generic u32 data to bool
force_link_train, which is later passed to dp_ctrl_on_stream().

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/490102/
Link: https://lore.kernel.org/r/20220617232434.1139950-2-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/dp/dp_display.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index 2dccc23487bcd..903f884797238 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -618,7 +618,7 @@ static int dp_hpd_plug_handle(struct dp_display_private *dp, u32 data)
 	return 0;
 };
 
-static int dp_display_enable(struct dp_display_private *dp, u32 data);
+static int dp_display_enable(struct dp_display_private *dp, bool force_link_train);
 static int dp_display_disable(struct dp_display_private *dp, u32 data);
 
 static void dp_display_handle_plugged_change(struct msm_dp *dp_display,
@@ -867,7 +867,7 @@ static int dp_display_set_mode(struct msm_dp *dp_display,
 	return 0;
 }
 
-static int dp_display_enable(struct dp_display_private *dp, u32 data)
+static int dp_display_enable(struct dp_display_private *dp, bool force_link_train)
 {
 	int rc = 0;
 	struct msm_dp *dp_display = &dp->dp_display;
@@ -878,7 +878,7 @@ static int dp_display_enable(struct dp_display_private *dp, u32 data)
 		return 0;
 	}
 
-	rc = dp_ctrl_on_stream(dp->ctrl, data);
+	rc = dp_ctrl_on_stream(dp->ctrl, force_link_train);
 	if (!rc)
 		dp_display->power_on = true;
 
-- 
GitLab


From ff46c2c481f2a379c457f2a815afdd6819521cc0 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Sat, 18 Jun 2022 02:24:34 +0300
Subject: [PATCH 1649/1731] drm/msm/dp: remove dp_display_en/disable prototypes
 and data argument

Remove unused dp_display_en/disable prototypes. While we are at it,
remove extra 'data' argument that is unused.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/490104/
Link: https://lore.kernel.org/r/20220617232434.1139950-3-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/dp/dp_display.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index 903f884797238..bfd0aeff3f0d0 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -618,9 +618,6 @@ static int dp_hpd_plug_handle(struct dp_display_private *dp, u32 data)
 	return 0;
 };
 
-static int dp_display_enable(struct dp_display_private *dp, bool force_link_train);
-static int dp_display_disable(struct dp_display_private *dp, u32 data);
-
 static void dp_display_handle_plugged_change(struct msm_dp *dp_display,
 		bool plugged)
 {
@@ -904,7 +901,7 @@ static int dp_display_post_enable(struct msm_dp *dp_display)
 	return 0;
 }
 
-static int dp_display_disable(struct dp_display_private *dp, u32 data)
+static int dp_display_disable(struct dp_display_private *dp)
 {
 	struct msm_dp *dp_display = &dp->dp_display;
 
@@ -1684,7 +1681,7 @@ void dp_bridge_enable(struct drm_bridge *drm_bridge)
 	rc = dp_display_post_enable(dp);
 	if (rc) {
 		DRM_ERROR("DP display post enable failed, rc=%d\n", rc);
-		dp_display_disable(dp_display, 0);
+		dp_display_disable(dp_display);
 	}
 
 	/* completed connection */
@@ -1725,7 +1722,7 @@ void dp_bridge_post_disable(struct drm_bridge *drm_bridge)
 		return;
 	}
 
-	dp_display_disable(dp_display, 0);
+	dp_display_disable(dp_display);
 
 	state =  dp_display->hpd_state;
 	if (state == ST_DISCONNECT_PENDING) {
-- 
GitLab


From a414fe3a2129b490e1e9b8ad66f0364f4f961887 Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Mon, 13 Jun 2022 13:50:32 -0700
Subject: [PATCH 1650/1731] drm/msm/gem: Drop obj lock in msm_gem_free_object()

The only reason we grabbed the lock was to satisfy a bunch of places
that WARN_ON() if called without the lock held.  But this angers lockdep
which doesn't realize no one else can be holding the lock by the time we
end up destroying the object (and sees what would otherwise be a locking
inversion between reservation_ww_class_mutex and fs_reclaim).

Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/14
Signed-off-by: Rob Clark <robdclark@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/489364/
Link: https://lore.kernel.org/r/20220613205032.2652374-1-robdclark@gmail.com
---
 drivers/gpu/drm/msm/msm_gem.c |  8 --------
 drivers/gpu/drm/msm/msm_gem.h | 14 +++++++++++++-
 2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 5514aca98dd02..520e4b7b812e5 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -1020,8 +1020,6 @@ static void msm_gem_free_object(struct drm_gem_object *obj)
 	list_del(&msm_obj->mm_list);
 	mutex_unlock(&priv->mm_lock);
 
-	msm_gem_lock(obj);
-
 	/* object should not be on active list: */
 	GEM_WARN_ON(is_active(msm_obj));
 
@@ -1037,17 +1035,11 @@ static void msm_gem_free_object(struct drm_gem_object *obj)
 
 		put_iova_vmas(obj);
 
-		/* dma_buf_detach() grabs resv lock, so we need to unlock
-		 * prior to drm_prime_gem_destroy
-		 */
-		msm_gem_unlock(obj);
-
 		drm_prime_gem_destroy(obj, msm_obj->sgt);
 	} else {
 		msm_gem_vunmap(obj);
 		put_pages(obj);
 		put_iova_vmas(obj);
-		msm_gem_unlock(obj);
 	}
 
 	drm_gem_object_release(obj);
diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h
index d608339c1643a..432032ad4aeda 100644
--- a/drivers/gpu/drm/msm/msm_gem.h
+++ b/drivers/gpu/drm/msm/msm_gem.h
@@ -229,7 +229,19 @@ msm_gem_unlock(struct drm_gem_object *obj)
 static inline bool
 msm_gem_is_locked(struct drm_gem_object *obj)
 {
-	return dma_resv_is_locked(obj->resv);
+	/*
+	 * Destroying the object is a special case.. msm_gem_free_object()
+	 * calls many things that WARN_ON if the obj lock is not held.  But
+	 * acquiring the obj lock in msm_gem_free_object() can cause a
+	 * locking order inversion between reservation_ww_class_mutex and
+	 * fs_reclaim.
+	 *
+	 * This deadlock is not actually possible, because no one should
+	 * be already holding the lock when msm_gem_free_object() is called.
+	 * Unfortunately lockdep is not aware of this detail.  So when the
+	 * refcount drops to zero, we pretend it is already locked.
+	 */
+	return dma_resv_is_locked(obj->resv) || (kref_read(&obj->refcount) == 0);
 }
 
 static inline bool is_active(struct msm_gem_object *msm_obj)
-- 
GitLab


From 4b18299b33655fa9672b774b6df774dc03d6aee8 Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Mon, 13 Jun 2022 11:20:30 -0700
Subject: [PATCH 1651/1731] drm/msm/adreno: Defer enabling runpm until
 hw_init()

To avoid preventing the display from coming up before the rootfs is
mounted, without resorting to packing fw in the initrd, the GPU has
this limbo state where the device is probed, but we aren't ready to
start sending commands to it.  This is particularly problematic for
a6xx, since the GMU (which requires fw to be loaded) is the one that
is controlling the power/clk/icc votes.

So defer enabling runpm until we are ready to call gpu->hw_init(),
as that is a point where we know we have all the needed fw and are
ready to start sending commands to the coproc's.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/489337/
Link: https://lore.kernel.org/r/20220613182036.2567963-1-robdclark@gmail.com
---
 drivers/gpu/drm/msm/adreno/adreno_device.c | 6 ++++++
 drivers/gpu/drm/msm/adreno/adreno_gpu.c    | 1 -
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 0e45b442d85fc..24b489b6129a0 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -432,6 +432,12 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
 	if (ret)
 		return NULL;
 
+	/*
+	 * Now that we have firmware loaded, and are ready to begin
+	 * booting the gpu, go ahead and enable runpm:
+	 */
+	pm_runtime_enable(&pdev->dev);
+
 	/* Make sure pm runtime is active and reset any previous errors */
 	pm_runtime_set_active(&pdev->dev);
 
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index a049d5de338ad..382fb7f9e4976 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -1065,7 +1065,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 	pm_runtime_set_autosuspend_delay(dev,
 		adreno_gpu->info->inactive_period);
 	pm_runtime_use_autosuspend(dev);
-	pm_runtime_enable(dev);
 
 	return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
 			gpu_name, &adreno_gpu_config);
-- 
GitLab


From 8b5de73595899858b377b41805f1d00ecbe18fcd Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Mon, 13 Jun 2022 12:46:23 -0700
Subject: [PATCH 1652/1731] drm/msm: Deprecate MSM_BO_UNCACHED harder

Handle the demotion to MSM_BO_WC at the userspace ABI level, and fix
the remaining internal MSM_BO_UNCACHED user.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/489339/
Link: https://lore.kernel.org/r/20220613194623.2588353-1-robdclark@gmail.com
---
 drivers/gpu/drm/msm/msm_drv.c | 13 +++++++++++++
 drivers/gpu/drm/msm/msm_gem.c |  7 +++----
 drivers/gpu/drm/msm/msm_gpu.c |  2 +-
 3 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 984b937735543..1ed4cd09dbf8b 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -678,12 +678,25 @@ static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
 		struct drm_file *file)
 {
 	struct drm_msm_gem_new *args = data;
+	uint32_t flags = args->flags;
 
 	if (args->flags & ~MSM_BO_FLAGS) {
 		DRM_ERROR("invalid flags: %08x\n", args->flags);
 		return -EINVAL;
 	}
 
+	/*
+	 * Uncached CPU mappings are deprecated, as of:
+	 *
+	 * 9ef364432db4 ("drm/msm: deprecate MSM_BO_UNCACHED (map as writecombine instead)")
+	 *
+	 * So promote them to WC.
+	 */
+	if (flags & MSM_BO_UNCACHED) {
+		flags &= ~MSM_BO_CACHED;
+		flags |= MSM_BO_WC;
+	}
+
 	return msm_gem_new_handle(dev, file, args->size,
 			args->flags, &args->handle, NULL);
 }
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 520e4b7b812e5..ad7da2ca35abb 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -129,7 +129,7 @@ static struct page **get_pages(struct drm_gem_object *obj)
 		/* For non-cached buffers, ensure the new pages are clean
 		 * because display controller, GPU, etc. are not coherent:
 		 */
-		if (msm_obj->flags & (MSM_BO_WC|MSM_BO_UNCACHED))
+		if (msm_obj->flags & MSM_BO_WC)
 			sync_for_device(msm_obj);
 
 		update_inactive(msm_obj);
@@ -160,7 +160,7 @@ static void put_pages(struct drm_gem_object *obj)
 			 * pages are clean because display controller,
 			 * GPU, etc. are not coherent:
 			 */
-			if (msm_obj->flags & (MSM_BO_WC|MSM_BO_UNCACHED))
+			if (msm_obj->flags & MSM_BO_WC)
 				sync_for_cpu(msm_obj);
 
 			sg_free_table(msm_obj->sgt);
@@ -213,7 +213,7 @@ void msm_gem_put_pages(struct drm_gem_object *obj)
 
 static pgprot_t msm_gem_pgprot(struct msm_gem_object *msm_obj, pgprot_t prot)
 {
-	if (msm_obj->flags & (MSM_BO_WC|MSM_BO_UNCACHED))
+	if (msm_obj->flags & MSM_BO_WC)
 		return pgprot_writecombine(prot);
 	return prot;
 }
@@ -1106,7 +1106,6 @@ static int msm_gem_new_impl(struct drm_device *dev,
 	struct msm_gem_object *msm_obj;
 
 	switch (flags & MSM_BO_CACHE_MASK) {
-	case MSM_BO_UNCACHED:
 	case MSM_BO_CACHED:
 	case MSM_BO_WC:
 		break;
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index e1ee85025b67a..c2bfcf3f1f403 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -918,7 +918,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 
 	memptrs = msm_gem_kernel_new(drm,
 		sizeof(struct msm_rbmemptrs) * nr_rings,
-		check_apriv(gpu, MSM_BO_UNCACHED), gpu->aspace, &gpu->memptrs_bo,
+		check_apriv(gpu, MSM_BO_WC), gpu->aspace, &gpu->memptrs_bo,
 		&memptrs_iova);
 
 	if (IS_ERR(memptrs)) {
-- 
GitLab


From 8246913a2e30e7028bff23b35f16657441d10855 Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Sat, 25 Jun 2022 15:54:36 -0700
Subject: [PATCH 1653/1731] drm/msm: Switch to pfn mappings

I'm not entirely sure why we were using VM_MIXEDMAP.  These are never
CoW mappings.  Let's switch to be more consistent with what other
drivers and the GEM shmem helpers do.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/491218/
Link: https://lore.kernel.org/r/20220625225454.81039-2-robdclark@gmail.com
---
 drivers/gpu/drm/msm/msm_gem.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index ad7da2ca35abb..8ddbd2e001d46 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -259,7 +259,8 @@ static vm_fault_t msm_gem_fault(struct vm_fault *vmf)
 	VERB("Inserting %p pfn %lx, pa %lx", (void *)vmf->address,
 			pfn, pfn << PAGE_SHIFT);
 
-	ret = vmf_insert_mixed(vma, vmf->address, __pfn_to_pfn_t(pfn, PFN_DEV));
+	ret = vmf_insert_pfn(vma, vmf->address, pfn);
+
 out_unlock:
 	msm_gem_unlock(obj);
 out:
@@ -1051,7 +1052,7 @@ static int msm_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct
 {
 	struct msm_gem_object *msm_obj = to_msm_bo(obj);
 
-	vma->vm_flags |= VM_IO | VM_MIXEDMAP | VM_DONTEXPAND | VM_DONTDUMP;
+	vma->vm_flags |= VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP;
 	vma->vm_page_prot = msm_gem_pgprot(msm_obj, vm_get_page_prot(vma->vm_flags));
 
 	return 0;
-- 
GitLab


From b55a21b764c1e182014630fa5486d717484ac58f Mon Sep 17 00:00:00 2001
From: Oliver Neukum <oneukum@suse.com>
Date: Tue, 5 Jul 2022 14:53:51 +0200
Subject: [PATCH 1654/1731] usbnet: fix memory leak in error case

usbnet_write_cmd_async() mixed up which buffers
need to be freed in which error case.

v2: add Fixes tag
v3: fix uninitialized buf pointer

Fixes: 877bd862f32b8 ("usbnet: introduce usbnet 3 command helpers")
Signed-off-by: Oliver Neukum <oneukum@suse.com>
Link: https://lore.kernel.org/r/20220705125351.17309-1-oneukum@suse.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/usb/usbnet.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/net/usb/usbnet.c b/drivers/net/usb/usbnet.c
index e2135ab87a6ed..78a92751ce4c2 100644
--- a/drivers/net/usb/usbnet.c
+++ b/drivers/net/usb/usbnet.c
@@ -2137,7 +2137,7 @@ static void usbnet_async_cmd_cb(struct urb *urb)
 int usbnet_write_cmd_async(struct usbnet *dev, u8 cmd, u8 reqtype,
 			   u16 value, u16 index, const void *data, u16 size)
 {
-	struct usb_ctrlrequest *req = NULL;
+	struct usb_ctrlrequest *req;
 	struct urb *urb;
 	int err = -ENOMEM;
 	void *buf = NULL;
@@ -2155,7 +2155,7 @@ int usbnet_write_cmd_async(struct usbnet *dev, u8 cmd, u8 reqtype,
 		if (!buf) {
 			netdev_err(dev->net, "Error allocating buffer"
 				   " in %s!\n", __func__);
-			goto fail_free;
+			goto fail_free_urb;
 		}
 	}
 
@@ -2179,14 +2179,21 @@ int usbnet_write_cmd_async(struct usbnet *dev, u8 cmd, u8 reqtype,
 	if (err < 0) {
 		netdev_err(dev->net, "Error submitting the control"
 			   " message: status=%d\n", err);
-		goto fail_free;
+		goto fail_free_all;
 	}
 	return 0;
 
+fail_free_all:
+	kfree(req);
 fail_free_buf:
 	kfree(buf);
-fail_free:
-	kfree(req);
+	/*
+	 * avoid a double free
+	 * needed because the flag can be set only
+	 * after filling the URB
+	 */
+	urb->transfer_flags = 0;
+fail_free_urb:
 	usb_free_urb(urb);
 fail:
 	return err;
-- 
GitLab


From 148ca04518070910739dfc4eeda765057856403d Mon Sep 17 00:00:00 2001
From: Duoming Zhou <duoming@zju.edu.cn>
Date: Tue, 5 Jul 2022 20:56:10 +0800
Subject: [PATCH 1655/1731] net: rose: fix UAF bug caused by
 rose_t0timer_expiry

There are UAF bugs caused by rose_t0timer_expiry(). The
root cause is that del_timer() could not stop the timer
handler that is running and there is no synchronization.
One of the race conditions is shown below:

    (thread 1)             |        (thread 2)
                           | rose_device_event
                           |   rose_rt_device_down
                           |     rose_remove_neigh
rose_t0timer_expiry        |       rose_stop_t0timer(rose_neigh)
  ...                      |         del_timer(&neigh->t0timer)
                           |         kfree(rose_neigh) //[1]FREE
  neigh->dce_mode //[2]USE |

The rose_neigh is deallocated in position [1] and use in
position [2].

The crash trace triggered by POC is like below:

BUG: KASAN: use-after-free in expire_timers+0x144/0x320
Write of size 8 at addr ffff888009b19658 by task swapper/0/0
...
Call Trace:
 <IRQ>
 dump_stack_lvl+0xbf/0xee
 print_address_description+0x7b/0x440
 print_report+0x101/0x230
 ? expire_timers+0x144/0x320
 kasan_report+0xed/0x120
 ? expire_timers+0x144/0x320
 expire_timers+0x144/0x320
 __run_timers+0x3ff/0x4d0
 run_timer_softirq+0x41/0x80
 __do_softirq+0x233/0x544
 ...

This patch changes rose_stop_ftimer() and rose_stop_t0timer()
in rose_remove_neigh() to del_timer_sync() in order that the
timer handler could be finished before the resources such as
rose_neigh and so on are deallocated. As a result, the UAF
bugs could be mitigated.

Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Signed-off-by: Duoming Zhou <duoming@zju.edu.cn>
Link: https://lore.kernel.org/r/20220705125610.77971-1-duoming@zju.edu.cn
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/rose/rose_route.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/net/rose/rose_route.c b/net/rose/rose_route.c
index fee6409c2bb38..eb0b8197ac825 100644
--- a/net/rose/rose_route.c
+++ b/net/rose/rose_route.c
@@ -227,8 +227,8 @@ static void rose_remove_neigh(struct rose_neigh *rose_neigh)
 {
 	struct rose_neigh *s;
 
-	rose_stop_ftimer(rose_neigh);
-	rose_stop_t0timer(rose_neigh);
+	del_timer_sync(&rose_neigh->ftimer);
+	del_timer_sync(&rose_neigh->t0timer);
 
 	skb_queue_purge(&rose_neigh->queue);
 
-- 
GitLab


From faa4e04e5e140a6d02260289a8fba8fd8d7a3003 Mon Sep 17 00:00:00 2001
From: Heiner Kallweit <hkallweit1@gmail.com>
Date: Tue, 5 Jul 2022 21:15:22 +0200
Subject: [PATCH 1656/1731] r8169: fix accessing unset transport header

66e4c8d95008 ("net: warn if transport header was not set") added
a check that triggers a warning in r8169, see [0].

The commit referenced in the Fixes tag refers to the change from
which the patch applies cleanly, there's nothing wrong with this
commit. It seems the actual issue (not bug, because the warning
is harmless here) was introduced with bdfa4ed68187
("r8169: use Giant Send").

[0] https://bugzilla.kernel.org/show_bug.cgi?id=216157

Fixes: 8d520b4de3ed ("r8169: work around RTL8125 UDP hw bug")
Reported-by: Erhard F. <erhard_f@mailbox.org>
Tested-by: Erhard F. <erhard_f@mailbox.org>
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Link: https://lore.kernel.org/r/1b2c2b29-3dc0-f7b6-5694-97ec526d51a0@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/ethernet/realtek/r8169_main.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c
index 3098d66721924..1b7fdb4f056bd 100644
--- a/drivers/net/ethernet/realtek/r8169_main.c
+++ b/drivers/net/ethernet/realtek/r8169_main.c
@@ -4190,7 +4190,6 @@ static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
 				struct sk_buff *skb, u32 *opts)
 {
-	u32 transport_offset = (u32)skb_transport_offset(skb);
 	struct skb_shared_info *shinfo = skb_shinfo(skb);
 	u32 mss = shinfo->gso_size;
 
@@ -4207,7 +4206,7 @@ static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
 			WARN_ON_ONCE(1);
 		}
 
-		opts[0] |= transport_offset << GTTCPHO_SHIFT;
+		opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT;
 		opts[1] |= mss << TD1_MSS_SHIFT;
 	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 		u8 ip_protocol;
@@ -4235,7 +4234,7 @@ static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
 		else
 			WARN_ON_ONCE(1);
 
-		opts[1] |= transport_offset << TCPHO_SHIFT;
+		opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT;
 	} else {
 		unsigned int padto = rtl_quirk_packet_padto(tp, skb);
 
@@ -4402,14 +4401,13 @@ static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
 						struct net_device *dev,
 						netdev_features_t features)
 {
-	int transport_offset = skb_transport_offset(skb);
 	struct rtl8169_private *tp = netdev_priv(dev);
 
 	if (skb_is_gso(skb)) {
 		if (tp->mac_version == RTL_GIGA_MAC_VER_34)
 			features = rtl8168evl_fix_tso(skb, features);
 
-		if (transport_offset > GTTCPHO_MAX &&
+		if (skb_transport_offset(skb) > GTTCPHO_MAX &&
 		    rtl_chip_supports_csum_v2(tp))
 			features &= ~NETIF_F_ALL_TSO;
 	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
@@ -4420,7 +4418,7 @@ static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
 		if (rtl_quirk_packet_padto(tp, skb))
 			features &= ~NETIF_F_CSUM_MASK;
 
-		if (transport_offset > TCPHO_MAX &&
+		if (skb_transport_offset(skb) > TCPHO_MAX &&
 		    rtl_chip_supports_csum_v2(tp))
 			features &= ~NETIF_F_CSUM_MASK;
 	}
-- 
GitLab


From 829be057dbc1e71383b8d7de8edb31dcf07b4aa0 Mon Sep 17 00:00:00 2001
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
Date: Thu, 7 Jul 2022 02:31:52 +0200
Subject: [PATCH 1657/1731] wireguard: selftests: set fake real time in init

Not all platforms have an RTC, and rather than trying to force one into
each, it's much easier to just set a fixed time. This is necessary
because WireGuard's latest handshakes parameter is returned in wallclock
time, and if the system time isn't set, and the system is really fast,
then this returns 0, which trips the test.

Turning this on requires setting CONFIG_COMPAT_32BIT_TIME=y, as musl
doesn't support settimeofday without it.

Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 .../testing/selftests/wireguard/qemu/arch/arm.config  |  1 +
 .../selftests/wireguard/qemu/arch/armeb.config        |  1 +
 .../testing/selftests/wireguard/qemu/arch/i686.config |  1 +
 .../testing/selftests/wireguard/qemu/arch/m68k.config |  1 +
 .../testing/selftests/wireguard/qemu/arch/mips.config |  1 +
 .../selftests/wireguard/qemu/arch/mipsel.config       |  1 +
 .../selftests/wireguard/qemu/arch/powerpc.config      |  1 +
 tools/testing/selftests/wireguard/qemu/init.c         | 11 +++++++++++
 8 files changed, 18 insertions(+)

diff --git a/tools/testing/selftests/wireguard/qemu/arch/arm.config b/tools/testing/selftests/wireguard/qemu/arch/arm.config
index fc7959bef9c25..0579c66be83ee 100644
--- a/tools/testing/selftests/wireguard/qemu/arch/arm.config
+++ b/tools/testing/selftests/wireguard/qemu/arch/arm.config
@@ -7,6 +7,7 @@ CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_VIRTIO_MENU=y
 CONFIG_VIRTIO_MMIO=y
 CONFIG_VIRTIO_CONSOLE=y
+CONFIG_COMPAT_32BIT_TIME=y
 CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyAMA0 wg.success=vport0p1 panic_on_warn=1"
 CONFIG_FRAME_WARN=1024
diff --git a/tools/testing/selftests/wireguard/qemu/arch/armeb.config b/tools/testing/selftests/wireguard/qemu/arch/armeb.config
index f3066be81c199..2a3307bbe534f 100644
--- a/tools/testing/selftests/wireguard/qemu/arch/armeb.config
+++ b/tools/testing/selftests/wireguard/qemu/arch/armeb.config
@@ -7,6 +7,7 @@ CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_VIRTIO_MENU=y
 CONFIG_VIRTIO_MMIO=y
 CONFIG_VIRTIO_CONSOLE=y
+CONFIG_COMPAT_32BIT_TIME=y
 CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyAMA0 wg.success=vport0p1 panic_on_warn=1"
 CONFIG_CPU_BIG_ENDIAN=y
diff --git a/tools/testing/selftests/wireguard/qemu/arch/i686.config b/tools/testing/selftests/wireguard/qemu/arch/i686.config
index 6d90892a85a24..cd864b9be6fb5 100644
--- a/tools/testing/selftests/wireguard/qemu/arch/i686.config
+++ b/tools/testing/selftests/wireguard/qemu/arch/i686.config
@@ -1,6 +1,7 @@
 CONFIG_ACPI=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_COMPAT_32BIT_TIME=y
 CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyS0 wg.success=ttyS1 panic_on_warn=1"
 CONFIG_FRAME_WARN=1024
diff --git a/tools/testing/selftests/wireguard/qemu/arch/m68k.config b/tools/testing/selftests/wireguard/qemu/arch/m68k.config
index 82c925e49beb7..9639bfe060744 100644
--- a/tools/testing/selftests/wireguard/qemu/arch/m68k.config
+++ b/tools/testing/selftests/wireguard/qemu/arch/m68k.config
@@ -5,5 +5,6 @@ CONFIG_MAC=y
 CONFIG_SERIAL_PMACZILOG=y
 CONFIG_SERIAL_PMACZILOG_TTYS=y
 CONFIG_SERIAL_PMACZILOG_CONSOLE=y
+CONFIG_COMPAT_32BIT_TIME=y
 CONFIG_CMDLINE="console=ttyS0 wg.success=ttyS1 panic_on_warn=1"
 CONFIG_FRAME_WARN=1024
diff --git a/tools/testing/selftests/wireguard/qemu/arch/mips.config b/tools/testing/selftests/wireguard/qemu/arch/mips.config
index d7ec63c17b30e..2a84402353ab8 100644
--- a/tools/testing/selftests/wireguard/qemu/arch/mips.config
+++ b/tools/testing/selftests/wireguard/qemu/arch/mips.config
@@ -6,6 +6,7 @@ CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_SYSCON=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_COMPAT_32BIT_TIME=y
 CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyS0 wg.success=ttyS1 panic_on_warn=1"
 CONFIG_FRAME_WARN=1024
diff --git a/tools/testing/selftests/wireguard/qemu/arch/mipsel.config b/tools/testing/selftests/wireguard/qemu/arch/mipsel.config
index 18a4982937376..56146a101e7e4 100644
--- a/tools/testing/selftests/wireguard/qemu/arch/mipsel.config
+++ b/tools/testing/selftests/wireguard/qemu/arch/mipsel.config
@@ -7,6 +7,7 @@ CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_SYSCON=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_COMPAT_32BIT_TIME=y
 CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyS0 wg.success=ttyS1 panic_on_warn=1"
 CONFIG_FRAME_WARN=1024
diff --git a/tools/testing/selftests/wireguard/qemu/arch/powerpc.config b/tools/testing/selftests/wireguard/qemu/arch/powerpc.config
index 5e04882e8e35b..174a9ffe2a362 100644
--- a/tools/testing/selftests/wireguard/qemu/arch/powerpc.config
+++ b/tools/testing/selftests/wireguard/qemu/arch/powerpc.config
@@ -4,6 +4,7 @@ CONFIG_PPC_85xx=y
 CONFIG_PHYS_64BIT=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_COMPAT_32BIT_TIME=y
 CONFIG_MATH_EMULATION=y
 CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyS0 wg.success=ttyS1 panic_on_warn=1"
diff --git a/tools/testing/selftests/wireguard/qemu/init.c b/tools/testing/selftests/wireguard/qemu/init.c
index c9e128436546f..3e49924dd77e8 100644
--- a/tools/testing/selftests/wireguard/qemu/init.c
+++ b/tools/testing/selftests/wireguard/qemu/init.c
@@ -11,6 +11,7 @@
 #include <stdlib.h>
 #include <stdbool.h>
 #include <fcntl.h>
+#include <time.h>
 #include <sys/wait.h>
 #include <sys/mount.h>
 #include <sys/stat.h>
@@ -70,6 +71,15 @@ static void seed_rng(void)
 	close(fd);
 }
 
+static void set_time(void)
+{
+	if (time(NULL))
+		return;
+	pretty_message("[+] Setting fake time...");
+	if (stime(&(time_t){1433512680}) < 0)
+		panic("settimeofday()");
+}
+
 static void mount_filesystems(void)
 {
 	pretty_message("[+] Mounting filesystems...");
@@ -259,6 +269,7 @@ int main(int argc, char *argv[])
 	print_banner();
 	mount_filesystems();
 	seed_rng();
+	set_time();
 	kmod_selftests();
 	enable_logging();
 	clear_leaks();
-- 
GitLab


From 1f2f341a62639c7066ee4c76b7d9ebe867e0a1d5 Mon Sep 17 00:00:00 2001
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
Date: Thu, 7 Jul 2022 02:31:53 +0200
Subject: [PATCH 1658/1731] wireguard: selftests: use virt machine on m68k

This should be a bit more stable hopefully.

Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 tools/testing/selftests/wireguard/qemu/Makefile         | 5 +++--
 tools/testing/selftests/wireguard/qemu/arch/m68k.config | 9 +++------
 2 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/tools/testing/selftests/wireguard/qemu/Makefile b/tools/testing/selftests/wireguard/qemu/Makefile
index 7d1b80988d8af..ed07fdc4589ce 100644
--- a/tools/testing/selftests/wireguard/qemu/Makefile
+++ b/tools/testing/selftests/wireguard/qemu/Makefile
@@ -208,10 +208,11 @@ QEMU_ARCH := m68k
 KERNEL_ARCH := m68k
 KERNEL_BZIMAGE := $(KERNEL_BUILD_PATH)/vmlinux
 KERNEL_CMDLINE := $(shell sed -n 's/CONFIG_CMDLINE=\(.*\)/\1/p' arch/m68k.config)
+QEMU_VPORT_RESULT := virtio-serial-device
 ifeq ($(HOST_ARCH),$(ARCH))
-QEMU_MACHINE := -cpu host,accel=kvm -machine q800 -append $(KERNEL_CMDLINE)
+QEMU_MACHINE := -cpu host,accel=kvm -machine virt -append $(KERNEL_CMDLINE)
 else
-QEMU_MACHINE := -machine q800 -smp 1 -append $(KERNEL_CMDLINE)
+QEMU_MACHINE := -machine virt -smp 1 -append $(KERNEL_CMDLINE)
 endif
 else ifeq ($(ARCH),riscv64)
 CHOST := riscv64-linux-musl
diff --git a/tools/testing/selftests/wireguard/qemu/arch/m68k.config b/tools/testing/selftests/wireguard/qemu/arch/m68k.config
index 9639bfe060744..39c48cba56b70 100644
--- a/tools/testing/selftests/wireguard/qemu/arch/m68k.config
+++ b/tools/testing/selftests/wireguard/qemu/arch/m68k.config
@@ -1,10 +1,7 @@
 CONFIG_MMU=y
+CONFIG_VIRT=y
 CONFIG_M68KCLASSIC=y
-CONFIG_M68040=y
-CONFIG_MAC=y
-CONFIG_SERIAL_PMACZILOG=y
-CONFIG_SERIAL_PMACZILOG_TTYS=y
-CONFIG_SERIAL_PMACZILOG_CONSOLE=y
+CONFIG_VIRTIO_CONSOLE=y
 CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CMDLINE="console=ttyS0 wg.success=ttyS1 panic_on_warn=1"
+CONFIG_CMDLINE="console=ttyGF0 wg.success=vport0p1 panic_on_warn=1"
 CONFIG_FRAME_WARN=1024
-- 
GitLab


From 1a087eec257154e26a81a7a0a15380d7a2431765 Mon Sep 17 00:00:00 2001
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
Date: Thu, 7 Jul 2022 02:31:54 +0200
Subject: [PATCH 1659/1731] wireguard: selftests: always call kernel makefile

These selftests are used for much more extensive changes than just the
wireguard source files. So always call the kernel's build file, which
will do something or nothing after checking the whole tree, per usual.

Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 tools/testing/selftests/wireguard/qemu/Makefile | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/tools/testing/selftests/wireguard/qemu/Makefile b/tools/testing/selftests/wireguard/qemu/Makefile
index ed07fdc4589ce..ce6176928a7d0 100644
--- a/tools/testing/selftests/wireguard/qemu/Makefile
+++ b/tools/testing/selftests/wireguard/qemu/Makefile
@@ -19,8 +19,6 @@ endif
 MIRROR := https://download.wireguard.com/qemu-test/distfiles/
 
 KERNEL_BUILD_PATH := $(BUILD_PATH)/kernel$(if $(findstring yes,$(DEBUG_KERNEL)),-debug)
-rwildcard=$(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2) $(filter $(subst *,%,$2),$d))
-WIREGUARD_SOURCES := $(call rwildcard,$(KERNEL_PATH)/drivers/net/wireguard/,*)
 
 default: qemu
 
@@ -323,8 +321,9 @@ $(KERNEL_BUILD_PATH)/.config: $(TOOLCHAIN_PATH)/.installed kernel.config arch/$(
 	cd $(KERNEL_BUILD_PATH) && ARCH=$(KERNEL_ARCH) $(KERNEL_PATH)/scripts/kconfig/merge_config.sh -n $(KERNEL_BUILD_PATH)/.config $(KERNEL_BUILD_PATH)/minimal.config
 	$(if $(findstring yes,$(DEBUG_KERNEL)),cp debug.config $(KERNEL_BUILD_PATH) && cd $(KERNEL_BUILD_PATH) && ARCH=$(KERNEL_ARCH) $(KERNEL_PATH)/scripts/kconfig/merge_config.sh -n $(KERNEL_BUILD_PATH)/.config debug.config,)
 
-$(KERNEL_BZIMAGE): $(TOOLCHAIN_PATH)/.installed $(KERNEL_BUILD_PATH)/.config $(BUILD_PATH)/init-cpio-spec.txt $(IPERF_PATH)/src/iperf3 $(IPUTILS_PATH)/ping $(BASH_PATH)/bash $(IPROUTE2_PATH)/misc/ss $(IPROUTE2_PATH)/ip/ip $(IPTABLES_PATH)/iptables/xtables-legacy-multi $(NMAP_PATH)/ncat/ncat $(WIREGUARD_TOOLS_PATH)/src/wg $(BUILD_PATH)/init ../netns.sh $(WIREGUARD_SOURCES)
+$(KERNEL_BZIMAGE): $(TOOLCHAIN_PATH)/.installed $(KERNEL_BUILD_PATH)/.config $(BUILD_PATH)/init-cpio-spec.txt $(IPERF_PATH)/src/iperf3 $(IPUTILS_PATH)/ping $(BASH_PATH)/bash $(IPROUTE2_PATH)/misc/ss $(IPROUTE2_PATH)/ip/ip $(IPTABLES_PATH)/iptables/xtables-legacy-multi $(NMAP_PATH)/ncat/ncat $(WIREGUARD_TOOLS_PATH)/src/wg $(BUILD_PATH)/init
 	$(MAKE) -C $(KERNEL_PATH) O=$(KERNEL_BUILD_PATH) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(CROSS_COMPILE)
+.PHONY: $(KERNEL_BZIMAGE)
 
 $(TOOLCHAIN_PATH)/$(CHOST)/include/linux/.installed: | $(KERNEL_BUILD_PATH)/.config $(TOOLCHAIN_PATH)/.installed
 	rm -rf $(TOOLCHAIN_PATH)/$(CHOST)/include/linux
-- 
GitLab


From b83fdcd9fb8ad7e59f4188ba9ec221917f463a17 Mon Sep 17 00:00:00 2001
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
Date: Thu, 7 Jul 2022 02:31:55 +0200
Subject: [PATCH 1660/1731] wireguard: selftests: use microvm on x86

This makes for faster tests, faster compile time, and allows us to ditch
ACPI finally.

Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 tools/testing/selftests/wireguard/qemu/Makefile        | 10 ++++++----
 .../testing/selftests/wireguard/qemu/arch/i686.config  |  7 +++++--
 .../selftests/wireguard/qemu/arch/x86_64.config        |  7 +++++--
 3 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/tools/testing/selftests/wireguard/qemu/Makefile b/tools/testing/selftests/wireguard/qemu/Makefile
index ce6176928a7d0..9700358e43374 100644
--- a/tools/testing/selftests/wireguard/qemu/Makefile
+++ b/tools/testing/selftests/wireguard/qemu/Makefile
@@ -107,20 +107,22 @@ CHOST := x86_64-linux-musl
 QEMU_ARCH := x86_64
 KERNEL_ARCH := x86_64
 KERNEL_BZIMAGE := $(KERNEL_BUILD_PATH)/arch/x86/boot/bzImage
+QEMU_VPORT_RESULT := virtio-serial-device
 ifeq ($(HOST_ARCH),$(ARCH))
-QEMU_MACHINE := -cpu host -machine q35,accel=kvm
+QEMU_MACHINE := -cpu host -machine microvm,accel=kvm,pit=off,pic=off,rtc=off -no-acpi
 else
-QEMU_MACHINE := -cpu max -machine q35
+QEMU_MACHINE := -cpu max -machine microvm -no-acpi
 endif
 else ifeq ($(ARCH),i686)
 CHOST := i686-linux-musl
 QEMU_ARCH := i386
 KERNEL_ARCH := x86
 KERNEL_BZIMAGE := $(KERNEL_BUILD_PATH)/arch/x86/boot/bzImage
+QEMU_VPORT_RESULT := virtio-serial-device
 ifeq ($(subst x86_64,i686,$(HOST_ARCH)),$(ARCH))
-QEMU_MACHINE := -cpu host -machine q35,accel=kvm
+QEMU_MACHINE := -cpu host -machine microvm,accel=kvm,pit=off,pic=off,rtc=off -no-acpi
 else
-QEMU_MACHINE := -cpu max -machine q35
+QEMU_MACHINE := -cpu coreduo -machine microvm -no-acpi
 endif
 else ifeq ($(ARCH),mips64)
 CHOST := mips64-linux-musl
diff --git a/tools/testing/selftests/wireguard/qemu/arch/i686.config b/tools/testing/selftests/wireguard/qemu/arch/i686.config
index cd864b9be6fb5..35b06502606f2 100644
--- a/tools/testing/selftests/wireguard/qemu/arch/i686.config
+++ b/tools/testing/selftests/wireguard/qemu/arch/i686.config
@@ -1,7 +1,10 @@
-CONFIG_ACPI=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_VIRTIO_MENU=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
 CONFIG_COMPAT_32BIT_TIME=y
 CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="console=ttyS0 wg.success=ttyS1 panic_on_warn=1"
+CONFIG_CMDLINE="console=ttyS0 wg.success=vport0p1 panic_on_warn=1 reboot=t"
 CONFIG_FRAME_WARN=1024
diff --git a/tools/testing/selftests/wireguard/qemu/arch/x86_64.config b/tools/testing/selftests/wireguard/qemu/arch/x86_64.config
index efa00693e08bf..cf2d1376d1219 100644
--- a/tools/testing/selftests/wireguard/qemu/arch/x86_64.config
+++ b/tools/testing/selftests/wireguard/qemu/arch/x86_64.config
@@ -1,6 +1,9 @@
-CONFIG_ACPI=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_VIRTIO_MENU=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
 CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="console=ttyS0 wg.success=ttyS1 panic_on_warn=1"
+CONFIG_CMDLINE="console=ttyS0 wg.success=vport0p1 panic_on_warn=1 reboot=t"
 CONFIG_FRAME_WARN=1280
-- 
GitLab


From b7133757da4c4c17d625970f6da3d76af12a8867 Mon Sep 17 00:00:00 2001
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
Date: Thu, 7 Jul 2022 02:31:56 +0200
Subject: [PATCH 1661/1731] crypto: s390 - do not depend on CRYPTO_HW for SIMD
 implementations

Various accelerated software implementation Kconfig values for S390 were
mistakenly placed into drivers/crypto/Kconfig, even though they're
mainly just SIMD code and live in arch/s390/crypto/ like usual. This
gives them the very unusual dependency on CRYPTO_HW, which leads to
problems elsewhere.

This patch fixes the issue by moving the Kconfig values for non-hardware
drivers into the usual place in crypto/Kconfig.

Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 crypto/Kconfig         | 114 ++++++++++++++++++++++++++++++++++++++++
 drivers/crypto/Kconfig | 115 -----------------------------------------
 2 files changed, 114 insertions(+), 115 deletions(-)

diff --git a/crypto/Kconfig b/crypto/Kconfig
index 1d44893a997ba..7b81685b56550 100644
--- a/crypto/Kconfig
+++ b/crypto/Kconfig
@@ -666,6 +666,18 @@ config CRYPTO_CRC32_MIPS
 	  CRC32c and CRC32 CRC algorithms implemented using mips crypto
 	  instructions, when available.
 
+config CRYPTO_CRC32_S390
+	tristate "CRC-32 algorithms"
+	depends on S390
+	select CRYPTO_HASH
+	select CRC32
+	help
+	  Select this option if you want to use hardware accelerated
+	  implementations of CRC algorithms.  With this option, you
+	  can optimize the computation of CRC-32 (IEEE 802.3 Ethernet)
+	  and CRC-32C (Castagnoli).
+
+	  It is available with IBM z13 or later.
 
 config CRYPTO_XXHASH
 	tristate "xxHash hash algorithm"
@@ -898,6 +910,16 @@ config CRYPTO_SHA512_SSSE3
 	  Extensions version 1 (AVX1), or Advanced Vector Extensions
 	  version 2 (AVX2) instructions, when available.
 
+config CRYPTO_SHA512_S390
+	tristate "SHA384 and SHA512 digest algorithm"
+	depends on S390
+	select CRYPTO_HASH
+	help
+	  This is the s390 hardware accelerated implementation of the
+	  SHA512 secure hash standard.
+
+	  It is available as of z10.
+
 config CRYPTO_SHA1_OCTEON
 	tristate "SHA1 digest algorithm (OCTEON)"
 	depends on CPU_CAVIUM_OCTEON
@@ -930,6 +952,16 @@ config CRYPTO_SHA1_PPC_SPE
 	  SHA-1 secure hash standard (DFIPS 180-4) implemented
 	  using powerpc SPE SIMD instruction set.
 
+config CRYPTO_SHA1_S390
+	tristate "SHA1 digest algorithm"
+	depends on S390
+	select CRYPTO_HASH
+	help
+	  This is the s390 hardware accelerated implementation of the
+	  SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2).
+
+	  It is available as of z990.
+
 config CRYPTO_SHA256
 	tristate "SHA224 and SHA256 digest algorithm"
 	select CRYPTO_HASH
@@ -970,6 +1002,16 @@ config CRYPTO_SHA256_SPARC64
 	  SHA-256 secure hash standard (DFIPS 180-2) implemented
 	  using sparc64 crypto instructions, when available.
 
+config CRYPTO_SHA256_S390
+	tristate "SHA256 digest algorithm"
+	depends on S390
+	select CRYPTO_HASH
+	help
+	  This is the s390 hardware accelerated implementation of the
+	  SHA256 secure hash standard (DFIPS 180-2).
+
+	  It is available as of z9.
+
 config CRYPTO_SHA512
 	tristate "SHA384 and SHA512 digest algorithms"
 	select CRYPTO_HASH
@@ -1010,6 +1052,26 @@ config CRYPTO_SHA3
 	  References:
 	  http://keccak.noekeon.org/
 
+config CRYPTO_SHA3_256_S390
+	tristate "SHA3_224 and SHA3_256 digest algorithm"
+	depends on S390
+	select CRYPTO_HASH
+	help
+	  This is the s390 hardware accelerated implementation of the
+	  SHA3_256 secure hash standard.
+
+	  It is available as of z14.
+
+config CRYPTO_SHA3_512_S390
+	tristate "SHA3_384 and SHA3_512 digest algorithm"
+	depends on S390
+	select CRYPTO_HASH
+	help
+	  This is the s390 hardware accelerated implementation of the
+	  SHA3_512 secure hash standard.
+
+	  It is available as of z14.
+
 config CRYPTO_SM3
 	tristate
 
@@ -1070,6 +1132,16 @@ config CRYPTO_GHASH_CLMUL_NI_INTEL
 	  This is the x86_64 CLMUL-NI accelerated implementation of
 	  GHASH, the hash function used in GCM (Galois/Counter mode).
 
+config CRYPTO_GHASH_S390
+	tristate "GHASH hash function"
+	depends on S390
+	select CRYPTO_HASH
+	help
+	  This is the s390 hardware accelerated implementation of GHASH,
+	  the hash function used in GCM (Galois/Counter mode).
+
+	  It is available as of z196.
+
 comment "Ciphers"
 
 config CRYPTO_AES
@@ -1185,6 +1257,23 @@ config CRYPTO_AES_PPC_SPE
 	  architecture specific assembler implementations that work on 1KB
 	  tables or 256 bytes S-boxes.
 
+config CRYPTO_AES_S390
+	tristate "AES cipher algorithms"
+	depends on S390
+	select CRYPTO_ALGAPI
+	select CRYPTO_SKCIPHER
+	help
+	  This is the s390 hardware accelerated implementation of the
+	  AES cipher algorithms (FIPS-197).
+
+	  As of z9 the ECB and CBC modes are hardware accelerated
+	  for 128 bit keys.
+	  As of z10 the ECB and CBC modes are hardware accelerated
+	  for all AES key sizes.
+	  As of z196 the CTR mode is hardware accelerated for all AES
+	  key sizes and XTS mode is hardware accelerated for 256 and
+	  512 bit keys.
+
 config CRYPTO_ANUBIS
 	tristate "Anubis cipher algorithm"
 	depends on CRYPTO_USER_API_ENABLE_OBSOLETE
@@ -1415,6 +1504,19 @@ config CRYPTO_DES3_EDE_X86_64
 	  algorithm are provided; regular processing one input block and
 	  one that processes three blocks parallel.
 
+config CRYPTO_DES_S390
+	tristate "DES and Triple DES cipher algorithms"
+	depends on S390
+	select CRYPTO_ALGAPI
+	select CRYPTO_SKCIPHER
+	select CRYPTO_LIB_DES
+	help
+	  This is the s390 hardware accelerated implementation of the
+	  DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3).
+
+	  As of z990 the ECB and CBC mode are hardware accelerated.
+	  As of z196 the CTR mode is hardware accelerated.
+
 config CRYPTO_FCRYPT
 	tristate "FCrypt cipher algorithm"
 	select CRYPTO_ALGAPI
@@ -1474,6 +1576,18 @@ config CRYPTO_CHACHA_MIPS
 	select CRYPTO_SKCIPHER
 	select CRYPTO_ARCH_HAVE_LIB_CHACHA
 
+config CRYPTO_CHACHA_S390
+	tristate "ChaCha20 stream cipher"
+	depends on S390
+	select CRYPTO_SKCIPHER
+	select CRYPTO_LIB_CHACHA_GENERIC
+	select CRYPTO_ARCH_HAVE_LIB_CHACHA
+	help
+	  This is the s390 SIMD implementation of the ChaCha20 stream
+	  cipher (RFC 7539).
+
+	  It is available as of z13.
+
 config CRYPTO_SEED
 	tristate "SEED cipher algorithm"
 	depends on CRYPTO_USER_API_ENABLE_OBSOLETE
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index ee99c02c84e81..3e6aa319920b7 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -133,98 +133,6 @@ config CRYPTO_PAES_S390
 	  Select this option if you want to use the paes cipher
 	  for example to use protected key encrypted devices.
 
-config CRYPTO_SHA1_S390
-	tristate "SHA1 digest algorithm"
-	depends on S390
-	select CRYPTO_HASH
-	help
-	  This is the s390 hardware accelerated implementation of the
-	  SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2).
-
-	  It is available as of z990.
-
-config CRYPTO_SHA256_S390
-	tristate "SHA256 digest algorithm"
-	depends on S390
-	select CRYPTO_HASH
-	help
-	  This is the s390 hardware accelerated implementation of the
-	  SHA256 secure hash standard (DFIPS 180-2).
-
-	  It is available as of z9.
-
-config CRYPTO_SHA512_S390
-	tristate "SHA384 and SHA512 digest algorithm"
-	depends on S390
-	select CRYPTO_HASH
-	help
-	  This is the s390 hardware accelerated implementation of the
-	  SHA512 secure hash standard.
-
-	  It is available as of z10.
-
-config CRYPTO_SHA3_256_S390
-	tristate "SHA3_224 and SHA3_256 digest algorithm"
-	depends on S390
-	select CRYPTO_HASH
-	help
-	  This is the s390 hardware accelerated implementation of the
-	  SHA3_256 secure hash standard.
-
-	  It is available as of z14.
-
-config CRYPTO_SHA3_512_S390
-	tristate "SHA3_384 and SHA3_512 digest algorithm"
-	depends on S390
-	select CRYPTO_HASH
-	help
-	  This is the s390 hardware accelerated implementation of the
-	  SHA3_512 secure hash standard.
-
-	  It is available as of z14.
-
-config CRYPTO_DES_S390
-	tristate "DES and Triple DES cipher algorithms"
-	depends on S390
-	select CRYPTO_ALGAPI
-	select CRYPTO_SKCIPHER
-	select CRYPTO_LIB_DES
-	help
-	  This is the s390 hardware accelerated implementation of the
-	  DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3).
-
-	  As of z990 the ECB and CBC mode are hardware accelerated.
-	  As of z196 the CTR mode is hardware accelerated.
-
-config CRYPTO_AES_S390
-	tristate "AES cipher algorithms"
-	depends on S390
-	select CRYPTO_ALGAPI
-	select CRYPTO_SKCIPHER
-	help
-	  This is the s390 hardware accelerated implementation of the
-	  AES cipher algorithms (FIPS-197).
-
-	  As of z9 the ECB and CBC modes are hardware accelerated
-	  for 128 bit keys.
-	  As of z10 the ECB and CBC modes are hardware accelerated
-	  for all AES key sizes.
-	  As of z196 the CTR mode is hardware accelerated for all AES
-	  key sizes and XTS mode is hardware accelerated for 256 and
-	  512 bit keys.
-
-config CRYPTO_CHACHA_S390
-	tristate "ChaCha20 stream cipher"
-	depends on S390
-	select CRYPTO_SKCIPHER
-	select CRYPTO_LIB_CHACHA_GENERIC
-	select CRYPTO_ARCH_HAVE_LIB_CHACHA
-	help
-	  This is the s390 SIMD implementation of the ChaCha20 stream
-	  cipher (RFC 7539).
-
-	  It is available as of z13.
-
 config S390_PRNG
 	tristate "Pseudo random number generator device driver"
 	depends on S390
@@ -238,29 +146,6 @@ config S390_PRNG
 
 	  It is available as of z9.
 
-config CRYPTO_GHASH_S390
-	tristate "GHASH hash function"
-	depends on S390
-	select CRYPTO_HASH
-	help
-	  This is the s390 hardware accelerated implementation of GHASH,
-	  the hash function used in GCM (Galois/Counter mode).
-
-	  It is available as of z196.
-
-config CRYPTO_CRC32_S390
-	tristate "CRC-32 algorithms"
-	depends on S390
-	select CRYPTO_HASH
-	select CRC32
-	help
-	  Select this option if you want to use hardware accelerated
-	  implementations of CRC algorithms.  With this option, you
-	  can optimize the computation of CRC-32 (IEEE 802.3 Ethernet)
-	  and CRC-32C (Castagnoli).
-
-	  It is available with IBM z13 or later.
-
 config CRYPTO_DEV_NIAGARA2
 	tristate "Niagara2 Stream Processing Unit driver"
 	select CRYPTO_LIB_DES
-- 
GitLab


From 0d1f700807d846b00e33cc87d90f404bbc904a97 Mon Sep 17 00:00:00 2001
From: Vladis Dronov <vdronov@redhat.com>
Date: Thu, 7 Jul 2022 02:31:57 +0200
Subject: [PATCH 1662/1731] wireguard: Kconfig: select CRYPTO_CHACHA_S390

Select the new implementation of CHACHA20 for S390 when available.
It is faster than the generic software implementation, but also prevents
some linker errors in certain situations.

Reported-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/linux-kernel/202207030630.6SZVkrWf-lkp@intel.com/
Signed-off-by: Vladis Dronov <vdronov@redhat.com>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index b2a4f998c180e..8c1eeb5a8db83 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -94,6 +94,7 @@ config WIREGUARD
 	select CRYPTO_CURVE25519_NEON if ARM && KERNEL_MODE_NEON
 	select CRYPTO_CHACHA_MIPS if CPU_MIPS32_R2
 	select CRYPTO_POLY1305_MIPS if MIPS
+	select CRYPTO_CHACHA_S390 if S390
 	help
 	  WireGuard is a secure, fast, and easy to use replacement for IPSec
 	  that uses modern cryptography and clever networking tricks. It's
-- 
GitLab


From 65a01e601dbba8b7a51a2677811f70f783766682 Mon Sep 17 00:00:00 2001
From: Helge Deller <deller@gmx.de>
Date: Sat, 25 Jun 2022 12:56:49 +0200
Subject: [PATCH 1663/1731] fbcon: Disallow setting font bigger than screen
 size

Prevent that users set a font size which is bigger than the physical screen.
It's unlikely this may happen (because screens are usually much larger than the
fonts and each font char is limited to 32x32 pixels), but it may happen on
smaller screens/LCD displays.

Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: stable@vger.kernel.org # v4.14+
---
 drivers/video/fbdev/core/fbcon.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/video/fbdev/core/fbcon.c b/drivers/video/fbdev/core/fbcon.c
index c4e91715ef006..a335325643935 100644
--- a/drivers/video/fbdev/core/fbcon.c
+++ b/drivers/video/fbdev/core/fbcon.c
@@ -2469,6 +2469,11 @@ static int fbcon_set_font(struct vc_data *vc, struct console_font *font,
 	if (charcount != 256 && charcount != 512)
 		return -EINVAL;
 
+	/* font bigger than screen resolution ? */
+	if (w > FBCON_SWAP(info->var.rotate, info->var.xres, info->var.yres) ||
+	    h > FBCON_SWAP(info->var.rotate, info->var.yres, info->var.xres))
+		return -EINVAL;
+
 	/* Make sure drawing engine can handle the font */
 	if (!(info->pixmap.blit_x & (1 << (font->width - 1))) ||
 	    !(info->pixmap.blit_y & (1 << (font->height - 1))))
-- 
GitLab


From e64242caef18b4a5840b0e7a9bff37abd4f4f933 Mon Sep 17 00:00:00 2001
From: Helge Deller <deller@gmx.de>
Date: Sat, 25 Jun 2022 13:00:34 +0200
Subject: [PATCH 1664/1731] fbcon: Prevent that screen size is smaller than
 font size

We need to prevent that users configure a screen size which is smaller than the
currently selected font size. Otherwise rendering chars on the screen will
access memory outside the graphics memory region.

This patch adds a new function fbcon_modechange_possible() which
implements this check and which later may be extended with other checks
if necessary.  The new function is called from the FBIOPUT_VSCREENINFO
ioctl handler in fbmem.c, which will return -EINVAL if userspace asked
for a too small screen size.

Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: stable@vger.kernel.org # v5.4+
---
 drivers/video/fbdev/core/fbcon.c | 28 ++++++++++++++++++++++++++++
 drivers/video/fbdev/core/fbmem.c |  4 +++-
 include/linux/fbcon.h            |  4 ++++
 3 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/video/fbdev/core/fbcon.c b/drivers/video/fbdev/core/fbcon.c
index a335325643935..5632870a9aebf 100644
--- a/drivers/video/fbdev/core/fbcon.c
+++ b/drivers/video/fbdev/core/fbcon.c
@@ -2736,6 +2736,34 @@ void fbcon_update_vcs(struct fb_info *info, bool all)
 }
 EXPORT_SYMBOL(fbcon_update_vcs);
 
+/* let fbcon check if it supports a new screen resolution */
+int fbcon_modechange_possible(struct fb_info *info, struct fb_var_screeninfo *var)
+{
+	struct fbcon_ops *ops = info->fbcon_par;
+	struct vc_data *vc;
+	unsigned int i;
+
+	WARN_CONSOLE_UNLOCKED();
+
+	if (!ops)
+		return 0;
+
+	/* prevent setting a screen size which is smaller than font size */
+	for (i = first_fb_vc; i <= last_fb_vc; i++) {
+		vc = vc_cons[i].d;
+		if (!vc || vc->vc_mode != KD_TEXT ||
+			   registered_fb[con2fb_map[i]] != info)
+			continue;
+
+		if (vc->vc_font.width  > FBCON_SWAP(var->rotate, var->xres, var->yres) ||
+		    vc->vc_font.height > FBCON_SWAP(var->rotate, var->yres, var->xres))
+			return -EINVAL;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(fbcon_modechange_possible);
+
 int fbcon_mode_deleted(struct fb_info *info,
 		       struct fb_videomode *mode)
 {
diff --git a/drivers/video/fbdev/core/fbmem.c b/drivers/video/fbdev/core/fbmem.c
index ee63b5b47290c..7dc6848a96bb9 100644
--- a/drivers/video/fbdev/core/fbmem.c
+++ b/drivers/video/fbdev/core/fbmem.c
@@ -1107,7 +1107,9 @@ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd,
 			return -EFAULT;
 		console_lock();
 		lock_fb_info(info);
-		ret = fb_set_var(info, &var);
+		ret = fbcon_modechange_possible(info, &var);
+		if (!ret)
+			ret = fb_set_var(info, &var);
 		if (!ret)
 			fbcon_update_vcs(info, var.activate & FB_ACTIVATE_ALL);
 		unlock_fb_info(info);
diff --git a/include/linux/fbcon.h b/include/linux/fbcon.h
index ff5596dd30f85..2382dec6d6ab8 100644
--- a/include/linux/fbcon.h
+++ b/include/linux/fbcon.h
@@ -15,6 +15,8 @@ void fbcon_new_modelist(struct fb_info *info);
 void fbcon_get_requirement(struct fb_info *info,
 			   struct fb_blit_caps *caps);
 void fbcon_fb_blanked(struct fb_info *info, int blank);
+int  fbcon_modechange_possible(struct fb_info *info,
+			       struct fb_var_screeninfo *var);
 void fbcon_update_vcs(struct fb_info *info, bool all);
 void fbcon_remap_all(struct fb_info *info);
 int fbcon_set_con2fb_map_ioctl(void __user *argp);
@@ -33,6 +35,8 @@ static inline void fbcon_new_modelist(struct fb_info *info) {}
 static inline void fbcon_get_requirement(struct fb_info *info,
 					 struct fb_blit_caps *caps) {}
 static inline void fbcon_fb_blanked(struct fb_info *info, int blank) {}
+static inline int  fbcon_modechange_possible(struct fb_info *info,
+				struct fb_var_screeninfo *var) { return 0; }
 static inline void fbcon_update_vcs(struct fb_info *info, bool all) {}
 static inline void fbcon_remap_all(struct fb_info *info) {}
 static inline int fbcon_set_con2fb_map_ioctl(void __user *argp) { return 0; }
-- 
GitLab


From 6c11df58fd1ac0aefcb3b227f72769272b939e56 Mon Sep 17 00:00:00 2001
From: Helge Deller <deller@gmx.de>
Date: Wed, 29 Jun 2022 15:53:55 +0200
Subject: [PATCH 1665/1731] fbmem: Check virtual screen sizes in fb_set_var()

Verify that the fbdev or drm driver correctly adjusted the virtual
screen sizes. On failure report the failing driver and reject the screen
size change.

Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: stable@vger.kernel.org # v5.4+
---
 drivers/video/fbdev/core/fbmem.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/video/fbdev/core/fbmem.c b/drivers/video/fbdev/core/fbmem.c
index 7dc6848a96bb9..7ee6eb2fa7151 100644
--- a/drivers/video/fbdev/core/fbmem.c
+++ b/drivers/video/fbdev/core/fbmem.c
@@ -1017,6 +1017,16 @@ fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var)
 	if (ret)
 		return ret;
 
+	/* verify that virtual resolution >= physical resolution */
+	if (var->xres_virtual < var->xres ||
+	    var->yres_virtual < var->yres) {
+		pr_warn("WARNING: fbcon: Driver '%s' missed to adjust virtual screen size (%ux%u vs. %ux%u)\n",
+			info->fix.id,
+			var->xres_virtual, var->yres_virtual,
+			var->xres, var->yres);
+		return -EINVAL;
+	}
+
 	if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_NOW)
 		return 0;
 
-- 
GitLab


From 53a6e66b1b4fea4b52f8bc62e5f9530af9061027 Mon Sep 17 00:00:00 2001
From: Helge Deller <deller@gmx.de>
Date: Sat, 25 Jun 2022 13:00:34 +0200
Subject: [PATCH 1666/1731] fbcon: Use fbcon_info_from_console() in
 fbcon_modechange_possible()

Use the fbcon_info_from_console() wrapper which was added to kernel
v5.19 with commit 409d6c95f9c6 ("fbcon: Introduce wrapper for console->fb_info lookup").

Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
---
 drivers/video/fbdev/core/fbcon.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/fbdev/core/fbcon.c b/drivers/video/fbdev/core/fbcon.c
index 5632870a9aebf..1a9aa12cf8860 100644
--- a/drivers/video/fbdev/core/fbcon.c
+++ b/drivers/video/fbdev/core/fbcon.c
@@ -2752,7 +2752,7 @@ int fbcon_modechange_possible(struct fb_info *info, struct fb_var_screeninfo *va
 	for (i = first_fb_vc; i <= last_fb_vc; i++) {
 		vc = vc_cons[i].d;
 		if (!vc || vc->vc_mode != KD_TEXT ||
-			   registered_fb[con2fb_map[i]] != info)
+			   fbcon_info_from_console(i) != info)
 			continue;
 
 		if (vc->vc_font.width  > FBCON_SWAP(var->rotate, var->xres, var->yres) ||
-- 
GitLab


From 7fd6ef61a5d610b4f74c0ac59450237b40130319 Mon Sep 17 00:00:00 2001
From: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Date: Tue, 5 Jul 2022 09:34:05 +0200
Subject: [PATCH 1667/1731] LoongArch: Drop these obsolete selects in Kconfig

Commit fa96b57c1490 ("LoongArch: Add build infrastructure") adds the new
file arch/loongarch/Kconfig.

As the work on LoongArch was probably quite some time under development,
various config symbols have changed and disappeared from the time of
initial writing of the Kconfig file and its inclusion in the repository.

The following four commits:

  commit c126a53c2760 ("arch: remove GENERIC_FIND_FIRST_BIT entirely")
  commit 140c8180eb7c ("arch: remove HAVE_COPY_THREAD_TLS")
  commit aca52c398389 ("mm: remove CONFIG_HAVE_MEMBLOCK")
  commit 3f08a302f533 ("mm: remove CONFIG_HAVE_MEMBLOCK_NODE_MAP option")

remove the mentioned config symbol, and enable the intended setup by
default without configuration.

Drop these obsolete selects in loongarch's Kconfig.

Reviewed-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 arch/loongarch/Kconfig | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig
index 1920d52653b41..53a912befb626 100644
--- a/arch/loongarch/Kconfig
+++ b/arch/loongarch/Kconfig
@@ -54,7 +54,6 @@ config LOONGARCH
 	select GENERIC_CMOS_UPDATE
 	select GENERIC_CPU_AUTOPROBE
 	select GENERIC_ENTRY
-	select GENERIC_FIND_FIRST_BIT
 	select GENERIC_GETTIMEOFDAY
 	select GENERIC_IRQ_MULTI_HANDLER
 	select GENERIC_IRQ_PROBE
@@ -77,7 +76,6 @@ config LOONGARCH
 	select HAVE_ARCH_TRANSPARENT_HUGEPAGE
 	select HAVE_ASM_MODVERSIONS
 	select HAVE_CONTEXT_TRACKING
-	select HAVE_COPY_THREAD_TLS
 	select HAVE_DEBUG_STACKOVERFLOW
 	select HAVE_DMA_CONTIGUOUS
 	select HAVE_EXIT_THREAD
@@ -86,8 +84,6 @@ config LOONGARCH
 	select HAVE_IOREMAP_PROT
 	select HAVE_IRQ_EXIT_ON_IRQ_STACK
 	select HAVE_IRQ_TIME_ACCOUNTING
-	select HAVE_MEMBLOCK
-	select HAVE_MEMBLOCK_NODE_MAP
 	select HAVE_MOD_ARCH_SPECIFIC
 	select HAVE_NMI
 	select HAVE_PERF_EVENTS
-- 
GitLab


From 112380996ac22e428264cd7186722e784db887e4 Mon Sep 17 00:00:00 2001
From: Qi Hu <huqi@loongson.cn>
Date: Wed, 6 Jul 2022 19:29:37 +0800
Subject: [PATCH 1668/1731] LoongArch: Remove obsolete mentions of vcsr

The `vcsr` only exists in the old hardware design, it isn't used in any
shipped hardware from Loongson-3A5000 on. Both scalar FP and LSX/LASX
instructions use the `fcsr` as their control and status registers now.
For example, the RM control bit in fcsr0 is shared by FP, LSX and LASX
instructions.

Particularly, fcsr16 to fcsr31 are reserved for LSX/LASX now, access to
these registers has no visible effect if LSX/LASX is enabled, and will
cause SXD/ASXD exceptions if LSX/LASX is not enabled.

So, mentions of vcsr are obsolete in the first place (it was just used
for debugging), let's remove them.

Reviewed-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Qi Hu <huqi@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 arch/loongarch/include/asm/fpregdef.h  |  1 -
 arch/loongarch/include/asm/processor.h |  2 --
 arch/loongarch/kernel/asm-offsets.c    |  1 -
 arch/loongarch/kernel/fpu.S            | 10 ----------
 4 files changed, 14 deletions(-)

diff --git a/arch/loongarch/include/asm/fpregdef.h b/arch/loongarch/include/asm/fpregdef.h
index adb16e4b43b01..b6be527831dd9 100644
--- a/arch/loongarch/include/asm/fpregdef.h
+++ b/arch/loongarch/include/asm/fpregdef.h
@@ -48,6 +48,5 @@
 #define fcsr1	$r1
 #define fcsr2	$r2
 #define fcsr3	$r3
-#define vcsr16	$r16
 
 #endif /* _ASM_FPREGDEF_H */
diff --git a/arch/loongarch/include/asm/processor.h b/arch/loongarch/include/asm/processor.h
index 1d63c934b289c..57ec45aa078ec 100644
--- a/arch/loongarch/include/asm/processor.h
+++ b/arch/loongarch/include/asm/processor.h
@@ -80,7 +80,6 @@ BUILD_FPR_ACCESS(64)
 
 struct loongarch_fpu {
 	unsigned int	fcsr;
-	unsigned int	vcsr;
 	uint64_t	fcc;	/* 8x8 */
 	union fpureg	fpr[NUM_FPU_REGS];
 };
@@ -161,7 +160,6 @@ struct thread_struct {
 	 */							\
 	.fpu			= {				\
 		.fcsr		= 0,				\
-		.vcsr		= 0,				\
 		.fcc		= 0,				\
 		.fpr		= {{{0,},},},			\
 	},							\
diff --git a/arch/loongarch/kernel/asm-offsets.c b/arch/loongarch/kernel/asm-offsets.c
index bfb65eb2844f5..20cd9e16a95ab 100644
--- a/arch/loongarch/kernel/asm-offsets.c
+++ b/arch/loongarch/kernel/asm-offsets.c
@@ -166,7 +166,6 @@ void output_thread_fpu_defines(void)
 
 	OFFSET(THREAD_FCSR, loongarch_fpu, fcsr);
 	OFFSET(THREAD_FCC,  loongarch_fpu, fcc);
-	OFFSET(THREAD_VCSR, loongarch_fpu, vcsr);
 	BLANK();
 }
 
diff --git a/arch/loongarch/kernel/fpu.S b/arch/loongarch/kernel/fpu.S
index 75c6ce0682a24..a631a7137667b 100644
--- a/arch/loongarch/kernel/fpu.S
+++ b/arch/loongarch/kernel/fpu.S
@@ -146,16 +146,6 @@
 	movgr2fcsr	fcsr0, \tmp0
 	.endm
 
-	.macro sc_save_vcsr base, tmp0
-	movfcsr2gr	\tmp0, vcsr16
-	EX	st.w \tmp0, \base, 0
-	.endm
-
-	.macro sc_restore_vcsr base, tmp0
-	EX	ld.w \tmp0, \base, 0
-	movgr2fcsr	vcsr16, \tmp0
-	.endm
-
 /*
  * Save a thread's fp context.
  */
-- 
GitLab


From e6ee90233eb155991e469d2047855fc466b831b6 Mon Sep 17 00:00:00 2001
From: Huacai Chen <chenhuacai@loongson.cn>
Date: Wed, 6 Jul 2022 11:03:09 +0800
Subject: [PATCH 1669/1731] LoongArch: Fix build errors for tinyconfig

Building loongarch:tinyconfig fails with the following error.

./arch/loongarch/include/asm/page.h: In function 'pfn_valid':
./arch/loongarch/include/asm/page.h:42:32: error: 'PHYS_OFFSET' undeclared

Add the missing include file and fix succeeding vdso errors.

Fixes: 09cfefb7fa70 ("LoongArch: Add memory management")
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 arch/loongarch/include/asm/page.h | 1 +
 arch/loongarch/vdso/Makefile      | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/loongarch/include/asm/page.h b/arch/loongarch/include/asm/page.h
index 3dba4986f6c92..dc47fc724fa17 100644
--- a/arch/loongarch/include/asm/page.h
+++ b/arch/loongarch/include/asm/page.h
@@ -6,6 +6,7 @@
 #define _ASM_PAGE_H
 
 #include <linux/const.h>
+#include <asm/addrspace.h>
 
 /*
  * PAGE_SHIFT determines the page size
diff --git a/arch/loongarch/vdso/Makefile b/arch/loongarch/vdso/Makefile
index 6b6e16732c603..92e4040322578 100644
--- a/arch/loongarch/vdso/Makefile
+++ b/arch/loongarch/vdso/Makefile
@@ -21,6 +21,7 @@ ccflags-vdso += $(filter --target=%,$(KBUILD_CFLAGS))
 endif
 
 cflags-vdso := $(ccflags-vdso) \
+	-isystem $(shell $(CC) -print-file-name=include) \
 	$(filter -W%,$(filter-out -Wa$(comma)%,$(KBUILD_CFLAGS))) \
 	-O2 -g -fno-strict-aliasing -fno-common -fno-builtin -G0 \
 	-fno-stack-protector -fno-jump-tables -DDISABLE_BRANCH_PROFILING \
-- 
GitLab


From f0fbe652e8529a180630617a17cd5922298c4f13 Mon Sep 17 00:00:00 2001
From: Tiezhu Yang <yangtiezhu@loongson.cn>
Date: Mon, 27 Jun 2022 14:57:35 +0800
Subject: [PATCH 1670/1731] LoongArch: Fix section mismatch warning

init_numa_memory() is annotated __init and not used by any module,
thus don't export it.

Remove not needed EXPORT_SYMBOL for init_numa_memory() to fix the
following section mismatch warning:

  MODPOST vmlinux.symvers
WARNING: modpost: vmlinux.o(___ksymtab+init_numa_memory+0x0): Section mismatch in reference
from the variable __ksymtab_init_numa_memory to the function .init.text:init_numa_memory()
The symbol init_numa_memory is exported and annotated __init
Fix this by removing the __init annotation of init_numa_memory or drop the export.

This is build on Linux 5.19-rc4.

Fixes: d4b6f1562a3c ("LoongArch: Add Non-Uniform Memory Access (NUMA) support")
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 arch/loongarch/kernel/numa.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/loongarch/kernel/numa.c b/arch/loongarch/kernel/numa.c
index a76f547a5aa3a..a13f92593cfda 100644
--- a/arch/loongarch/kernel/numa.c
+++ b/arch/loongarch/kernel/numa.c
@@ -429,7 +429,6 @@ int __init init_numa_memory(void)
 	return 0;
 }
 
-EXPORT_SYMBOL(init_numa_memory);
 #endif
 
 void __init paging_init(void)
-- 
GitLab


From c8e27a4a5136e7230f9e4ffcf132705bf56864cc Mon Sep 17 00:00:00 2001
From: Kent Gibson <warthog618@gmail.com>
Date: Wed, 6 Jul 2022 16:45:07 +0800
Subject: [PATCH 1671/1731] gpiolib: cdev: fix null pointer dereference in
 linereq_free()

Fix a kernel NULL pointer dereference reported by gpio kselftests.

linereq_free() can be called as part of the cleanup of a failed request,
at which time the desc for a line may not have been determined, so it
is unsafe to dereference without a check.

Add a check prior to dereferencing the line desc.

Fixes: 2068339a6c35 ("gpiolib: cdev: Add hardware timestamp clock type")
Signed-off-by: Kent Gibson <warthog618@gmail.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
---
 drivers/gpio/gpiolib-cdev.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpio/gpiolib-cdev.c b/drivers/gpio/gpiolib-cdev.c
index f5aa5f93342a4..0c9a63becfef5 100644
--- a/drivers/gpio/gpiolib-cdev.c
+++ b/drivers/gpio/gpiolib-cdev.c
@@ -1460,11 +1460,12 @@ static ssize_t linereq_read(struct file *file,
 static void linereq_free(struct linereq *lr)
 {
 	unsigned int i;
-	bool hte;
+	bool hte = false;
 
 	for (i = 0; i < lr->num_lines; i++) {
-		hte = !!test_bit(FLAG_EVENT_CLOCK_HTE,
-				 &lr->lines[i].desc->flags);
+		if (lr->lines[i].desc)
+			hte = !!test_bit(FLAG_EVENT_CLOCK_HTE,
+					 &lr->lines[i].desc->flags);
 		edge_detector_stop(&lr->lines[i], hte);
 		if (lr->lines[i].desc)
 			gpiod_free(lr->lines[i].desc);
-- 
GitLab


From 38e0e4d04d4187c63d6b511396faae7db6a3cd9e Mon Sep 17 00:00:00 2001
From: Peter Zijlstra <peterz@infradead.org>
Date: Tue, 28 Jun 2022 12:57:42 +0200
Subject: [PATCH 1672/1731] x86/ibt, objtool: Don't discard text references
 from tracepoint section

On Tue, Jun 28, 2022 at 04:28:58PM +0800, Pengfei Xu wrote:

> # ./ftracetest
> === Ftrace unit tests ===
> [1] Basic trace file check      [PASS]
> [2] Basic test for tracers      [PASS]
> [3] Basic trace clock test      [PASS]
> [4] Basic event tracing check   [PASS]
> [5] Change the ringbuffer size  [PASS]
> [6] Snapshot and tracing setting        [PASS]
> [7] trace_pipe and trace_marker [PASS]
> [8] Test ftrace direct functions against tracers        [UNRESOLVED]
> [9] Test ftrace direct functions against kprobes        [UNRESOLVED]
> [10] Generic dynamic event - add/remove eprobe events   [FAIL]
> [11] Generic dynamic event - add/remove kprobe events
>
> It 100% reproduced in step 11 and then missing ENDBR BUG generated:
> "
> [ 9332.752836] mmiotrace: enabled CPU7.
> [ 9332.788612] mmiotrace: disabled.
> [ 9337.103426] traps: Missing ENDBR: syscall_regfunc+0x0/0xb0

It turns out that while syscall_regfunc() does have an ENDBR when
generated, it gets sealed by objtool's .ibt_endbr_seal list.

Since the only text references to this function:

  $ git grep syscall_regfunc
  include/linux/tracepoint.h:extern int syscall_regfunc(void);
  include/trace/events/syscalls.h:        syscall_regfunc, syscall_unregfunc
  include/trace/events/syscalls.h:        syscall_regfunc, syscall_unregfunc
  kernel/tracepoint.c:int syscall_regfunc(void)

appear in the __tracepoint section which is excluded by objtool.

Fixes: 3c6f9f77e618 ("objtool: Rework ibt and extricate from stack validation")
Reported-by: Pengfei Xu <pengfei.xu@intel.com
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/Yrrepdaow4F5kqG0@hirez.programming.kicks-ass.net
---
 tools/objtool/check.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/tools/objtool/check.c b/tools/objtool/check.c
index 864bb9dd35845..57153e00349c0 100644
--- a/tools/objtool/check.c
+++ b/tools/objtool/check.c
@@ -3826,8 +3826,7 @@ static int validate_ibt(struct objtool_file *file)
 		    !strcmp(sec->name, "__bug_table")			||
 		    !strcmp(sec->name, "__ex_table")			||
 		    !strcmp(sec->name, "__jump_table")			||
-		    !strcmp(sec->name, "__mcount_loc")			||
-		    !strcmp(sec->name, "__tracepoints"))
+		    !strcmp(sec->name, "__mcount_loc"))
 			continue;
 
 		list_for_each_entry(reloc, &sec->reloc->reloc_list, list)
-- 
GitLab


From f392d6f64d179913fc716996cd35dd9dc1adc0f1 Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Sat, 25 Jun 2022 15:54:37 -0700
Subject: [PATCH 1673/1731] drm/msm: Make enable_eviction flag static

No need for it to be visible outside of this one src file.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/491219/
Link: https://lore.kernel.org/r/20220625225454.81039-3-robdclark@gmail.com
---
 drivers/gpu/drm/msm/msm_gem_shrinker.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/msm_gem_shrinker.c b/drivers/gpu/drm/msm/msm_gem_shrinker.c
index 086dacf2f26a7..6e39d959b9f0f 100644
--- a/drivers/gpu/drm/msm/msm_gem_shrinker.c
+++ b/drivers/gpu/drm/msm/msm_gem_shrinker.c
@@ -15,7 +15,7 @@
 /* Default disabled for now until it has some more testing on the different
  * iommu combinations that can be paired with the driver:
  */
-bool enable_eviction = false;
+static bool enable_eviction = false;
 MODULE_PARM_DESC(enable_eviction, "Enable swappable GEM buffers");
 module_param(enable_eviction, bool, 0600);
 
-- 
GitLab


From fe8b45aa61153f44a2e4851b021fda0b8bc94fb9 Mon Sep 17 00:00:00 2001
From: Thierry Reding <treding@nvidia.com>
Date: Mon, 25 May 2020 17:32:08 +0200
Subject: [PATCH 1674/1731] dt-bindings: display: tegra: Convert to json-schema

Convert the Tegra host1x controller bindings from the free-form text
format to json-schema.

This also adds the missing display-hub DT bindings that were not
previously documented.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../display/tegra/nvidia,tegra114-mipi.txt    |  41 --
 .../display/tegra/nvidia,tegra114-mipi.yaml   |  74 ++
 .../display/tegra/nvidia,tegra124-dpaux.yaml  | 152 ++++
 .../display/tegra/nvidia,tegra124-sor.yaml    | 197 +++++
 .../display/tegra/nvidia,tegra124-vic.yaml    |  71 ++
 .../display/tegra/nvidia,tegra186-dc.yaml     |  85 +++
 .../tegra/nvidia,tegra186-display.yaml        | 310 ++++++++
 .../tegra/nvidia,tegra186-dsi-padctl.yaml     |  45 ++
 .../display/tegra/nvidia,tegra20-dc.yaml      | 183 +++++
 .../display/tegra/nvidia,tegra20-dsi.yaml     | 159 +++++
 .../display/tegra/nvidia,tegra20-epp.yaml     |  70 ++
 .../display/tegra/nvidia,tegra20-gr2d.yaml    |  74 ++
 .../display/tegra/nvidia,tegra20-gr3d.yaml    | 215 ++++++
 .../display/tegra/nvidia,tegra20-hdmi.yaml    | 126 ++++
 .../display/tegra/nvidia,tegra20-host1x.txt   | 675 ------------------
 .../display/tegra/nvidia,tegra20-host1x.yaml  | 348 +++++++++
 .../display/tegra/nvidia,tegra20-isp.yaml     |  67 ++
 .../display/tegra/nvidia,tegra20-mpe.yaml     |  73 ++
 .../display/tegra/nvidia,tegra20-tvo.yaml     |  58 ++
 .../display/tegra/nvidia,tegra20-vi.yaml      | 163 +++++
 .../display/tegra/nvidia,tegra210-csi.yaml    |  52 ++
 .../pinctrl/nvidia,tegra124-dpaux-padctl.txt  |  59 --
 22 files changed, 2522 insertions(+), 775 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.txt
 create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml
 create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-dpaux.yaml
 create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml
 create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml
 create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml
 create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml
 create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml
 create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml
 create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml
 create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
 create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
 create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
 create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml
 delete mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
 create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
 create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
 create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
 create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml
 create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
 create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt

diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.txt
deleted file mode 100644
index e4a25cedc5cf4..0000000000000
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-NVIDIA Tegra MIPI pad calibration controller
-
-Required properties:
-- compatible: "nvidia,tegra<chip>-mipi"
-- reg: Physical base address and length of the controller's registers.
-- clocks: Must contain an entry for each entry in clock-names.
-  See ../clocks/clock-bindings.txt for details.
-- clock-names: Must include the following entries:
-  - mipi-cal
-- #nvidia,mipi-calibrate-cells: Should be 1. The cell is a bitmask of the pads
-  that need to be calibrated for a given device.
-
-User nodes need to contain an nvidia,mipi-calibrate property that has a
-phandle to refer to the calibration controller node and a bitmask of the pads
-that need to be calibrated.
-
-Example:
-
-	mipi: mipi@700e3000 {
-		compatible = "nvidia,tegra114-mipi";
-		reg = <0x700e3000 0x100>;
-		clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
-		clock-names = "mipi-cal";
-		#nvidia,mipi-calibrate-cells = <1>;
-	};
-
-	...
-
-	host1x@50000000 {
-		...
-
-		dsi@54300000 {
-			...
-
-			nvidia,mipi-calibrate = <&mipi 0x060>;
-
-			...
-		};
-
-		...
-	};
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml
new file mode 100644
index 0000000000000..d5ca8cf86e8e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-mipi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra MIPI pad calibration controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^mipi@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - nvidia,tegra114-mipi
+      - nvidia,tegra210-mipi
+      - nvidia,tegra186-mipi
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: module clock
+
+  clock-names:
+    items:
+      - const: mipi-cal
+
+  power-domains:
+    maxItems: 1
+
+  "#nvidia,mipi-calibrate-cells":
+    description: The number of cells in a MIPI calibration specifier.
+      Should be 1. The single cell specifies a bitmask of the pads that
+      need to be calibrated for a given device.
+    $ref: "/schemas/types.yaml#/definitions/uint32"
+    const: 1
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - "#nvidia,mipi-calibrate-cells"
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra114-car.h>
+
+    mipi@700e3000 {
+        compatible = "nvidia,tegra114-mipi";
+        reg = <0x700e3000 0x100>;
+        clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
+        clock-names = "mipi-cal";
+        #nvidia,mipi-calibrate-cells = <1>;
+    };
+
+    dsia: dsi@54300000 {
+        compatible = "nvidia,tegra114-dsi";
+        reg = <0x54300000 0x00040000>;
+        clocks = <&tegra_car TEGRA114_CLK_DSIA>,
+                 <&tegra_car TEGRA114_CLK_DSIALP>,
+                 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
+        clock-names = "dsi", "lp", "parent";
+        resets = <&tegra_car 48>;
+        reset-names = "dsi";
+        nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-dpaux.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-dpaux.yaml
new file mode 100644
index 0000000000000..9ab123cd23251
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-dpaux.yaml
@@ -0,0 +1,152 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-dpaux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra DisplayPort AUX Interface
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+description: |
+  The Tegra Display Port Auxiliary (DPAUX) pad controller manages two
+  pins which can be assigned to either the DPAUX channel or to an I2C
+  controller.
+
+  When configured for DisplayPort AUX operation, the DPAUX controller
+  can also be used to communicate with a DisplayPort device using the
+  AUX channel.
+
+properties:
+  $nodename:
+    pattern: "^dpaux@[0-9a-f]+$"
+
+  compatible:
+    oneOf:
+      - enum:
+          - nvidia,tegra124-dpaux
+          - nvidia,tegra210-dpaux
+          - nvidia,tegra186-dpaux
+          - nvidia,tegra194-dpaux
+
+      - items:
+          - const: nvidia,tegra132-dpaux
+          - const: nvidia,tegra124-dpaux
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: clock input for the DPAUX hardware
+      - description: reference clock
+
+  clock-names:
+    items:
+      - const: dpaux
+      - const: parent
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: dpaux
+
+  power-domains:
+    maxItems: 1
+
+  i2c-bus:
+    description: Subnode where I2C slave devices are listed. This
+      subnode must be always present. If there are no I2C slave
+      devices, an empty node should be added. See ../../i2c/i2c.yaml
+      for more information.
+    type: object
+
+  aux-bus:
+    $ref: /schemas/display/dp-aux-bus.yaml#
+
+  vdd-supply:
+    description: phandle of a supply that powers the DisplayPort
+      link
+
+patternProperties:
+  "^pinmux-[a-z0-9]+$":
+    description:
+      Since only three configurations are possible, only three child
+      nodes are needed to describe the pin mux'ing options for the
+      DPAUX pads. Furthermore, given that the pad functions are only
+      applicable to a single set of pads, the child nodes only need
+      to describe the pad group the functions are being applied to
+      rather than the individual pads.
+    type: object
+    properties:
+      groups:
+        const: dpaux-io
+
+      function:
+        enum:
+          - aux
+          - i2c
+          - off
+
+    additionalProperties: false
+
+    required:
+      - groups
+      - function
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra210-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    dpaux: dpaux@545c0000 {
+        compatible = "nvidia,tegra210-dpaux";
+        reg = <0x545c0000 0x00040000>;
+        interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
+                 <&tegra_car TEGRA210_CLK_PLL_DP>;
+        clock-names = "dpaux", "parent";
+        resets = <&tegra_car 181>;
+        reset-names = "dpaux";
+        power-domains = <&pd_sor>;
+        status = "disabled";
+
+        state_dpaux_aux: pinmux-aux {
+            groups = "dpaux-io";
+            function = "aux";
+        };
+
+        state_dpaux_i2c: pinmux-i2c {
+            groups = "dpaux-io";
+            function = "i2c";
+        };
+
+        state_dpaux_off: pinmux-off {
+            groups = "dpaux-io";
+            function = "off";
+        };
+
+        i2c-bus {
+            #address-cells = <1>;
+            #size-cells = <0>;
+        };
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml
new file mode 100644
index 0000000000000..907fb0baccaea
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml
@@ -0,0 +1,197 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra SOR Output Encoder
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+description: |
+  The Serial Output Resource (SOR) can be used to drive HDMI, LVDS, eDP
+  and DP outputs.
+
+properties:
+  $nodename:
+    pattern: "^sor@[0-9a-f]+$"
+
+  compatible:
+    oneOf:
+      - enum:
+          - nvidia,tegra124-sor
+          - nvidia,tegra210-sor
+          - nvidia,tegra210-sor1
+          - nvidia,tegra186-sor
+          - nvidia,tegra186-sor1
+          - nvidia,tegra194-sor
+
+      - items:
+          - const: nvidia,tegra132-sor
+          - const: nvidia,tegra124-sor
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 5
+    maxItems: 6
+
+  clock-names:
+    minItems: 5
+    maxItems: 6
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: sor
+
+  power-domains:
+    maxItems: 1
+
+  avdd-io-hdmi-dp-supply:
+    description: I/O supply for HDMI/DP
+
+  vdd-hdmi-dp-pll-supply:
+    description: PLL supply for HDMI/DP
+
+  hdmi-supply:
+    description: +5.0V HDMI connector supply, required for HDMI
+
+  # Tegra186 and later
+  nvidia,interface:
+    description: index of the SOR interface
+    $ref: "/schemas/types.yaml#/definitions/uint32"
+
+  nvidia,ddc-i2c-bus:
+    description: phandle of an I2C controller used for DDC EDID
+      probing
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  nvidia,hpd-gpio:
+    description: specifies a GPIO used for hotplug detection
+    maxItems: 1
+
+  nvidia,edid:
+    description: supplies a binary EDID blob
+    $ref: "/schemas/types.yaml#/definitions/uint8-array"
+
+  nvidia,panel:
+    description: phandle of a display panel, required for eDP
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  nvidia,xbar-cfg:
+    description: 5 cells containing the crossbar configuration.
+      Each lane of the SOR, identified by the cell's index, is
+      mapped via the crossbar to the pad specified by the cell's
+      value.
+    $ref: "/schemas/types.yaml#/definitions/uint32-array"
+
+  # optional when driving an eDP output
+  nvidia,dpaux:
+    description: phandle to a DispayPort AUX interface
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra186-sor
+              - nvidia,tegra194-sor
+    then:
+      properties:
+        clocks:
+          items:
+            - description: clock input for the SOR hardware
+            - description: SOR output clock
+            - description: input for the pixel clock
+            - description: reference clock for the SOR clock
+            - description: safe reference clock for the SOR clock
+                during power up
+            - description: SOR pad output clock
+
+        clock-names:
+          items:
+            - const: sor
+            - enum:
+                - source # deprecated
+                - out
+            - const: parent
+            - const: dp
+            - const: safe
+            - const: pad
+    else:
+      properties:
+        clocks:
+          items:
+            - description: clock input for the SOR hardware
+            - description: SOR output clock
+            - description: input for the pixel clock
+            - description: reference clock for the SOR clock
+            - description: safe reference clock for the SOR clock
+                during power up
+
+        clock-names:
+          items:
+            - const: sor
+            - enum:
+                - source # deprecated
+                - out
+            - const: parent
+            - const: dp
+            - const: safe
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - avdd-io-hdmi-dp-supply
+  - vdd-hdmi-dp-pll-supply
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra210-car.h>
+    #include <dt-bindings/gpio/tegra-gpio.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    sor0: sor@54540000 {
+        compatible = "nvidia,tegra210-sor";
+        reg = <0x54540000 0x00040000>;
+        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&tegra_car TEGRA210_CLK_SOR0>,
+                 <&tegra_car TEGRA210_CLK_SOR0_OUT>,
+                 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
+                 <&tegra_car TEGRA210_CLK_PLL_DP>,
+                 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
+        clock-names = "sor", "out", "parent", "dp", "safe";
+        resets = <&tegra_car 182>;
+        reset-names = "sor";
+        pinctrl-0 = <&state_dpaux_aux>;
+        pinctrl-1 = <&state_dpaux_i2c>;
+        pinctrl-2 = <&state_dpaux_off>;
+        pinctrl-names = "aux", "i2c", "off";
+        power-domains = <&pd_sor>;
+
+        avdd-io-hdmi-dp-supply = <&avdd_1v05>;
+        vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
+        hdmi-supply = <&vdd_hdmi>;
+
+        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) GPIO_ACTIVE_LOW>;
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml
new file mode 100644
index 0000000000000..37bb5ddc1963e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-vic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Video Image Composer
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^vic@[0-9a-f]+$"
+
+  compatible:
+    oneOf:
+      - enum:
+          - nvidia,tegra124-vic
+          - nvidia,tegra210-vic
+          - nvidia,tegra186-vic
+          - nvidia,tegra194-vic
+
+      - items:
+          - const: nvidia,tegra132-vic
+          - const: nvidia,tegra124-vic
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: clock input for the VIC hardware
+
+  clock-names:
+    items:
+      - const: vic
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: vic
+
+  power-domains:
+    maxItems: 1
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    description: Description of the interconnect paths for the VIC;
+      see ../interconnect/interconnect.txt for details.
+    items:
+      - description: memory read client for VIC
+      - description: memory write client for VIC
+
+  interconnect-names:
+    items:
+      - const: dma-mem # read
+      - const: write
+
+  dma-coherent: true
+
+additionalProperties: false
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml
new file mode 100644
index 0000000000000..265a60d79d89c
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra186 (and later) Display Controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^display@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - nvidia,tegra186-dc
+      - nvidia,tegra194-dc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: display controller pixel clock
+
+  clock-names:
+    items:
+      - const: dc
+
+  resets:
+    items:
+      - description: display controller reset
+
+  reset-names:
+    items:
+      - const: dc
+
+  power-domains:
+    maxItems: 1
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    description: Description of the interconnect paths for the
+      display controller; see ../interconnect/interconnect.txt
+      for details.
+
+  interconnect-names:
+    items:
+      - const: dma-mem # read-0
+      - const: read-1
+
+  nvidia,outputs:
+    description: A list of phandles of outputs that this display
+      controller can drive.
+    $ref: "/schemas/types.yaml#/definitions/phandle-array"
+
+  nvidia,head:
+    description: The number of the display controller head. This
+      is used to setup the various types of output to receive
+      video data from the given head.
+    $ref: "/schemas/types.yaml#/definitions/uint32"
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - power-domains
+  - nvidia,outputs
+  - nvidia,head
+
+# see nvidia,tegra186-display.yaml for examples
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml
new file mode 100644
index 0000000000000..8c02313455299
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml
@@ -0,0 +1,310 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra186 (and later) Display Hub
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^display-hub@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - nvidia,tegra186-display
+      - nvidia,tegra194-display
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 2
+    maxItems: 3
+
+  clock-names:
+    minItems: 2
+    maxItems: 3
+
+  resets:
+    items:
+      - description: display hub reset
+      - description: window group 0 reset
+      - description: window group 1 reset
+      - description: window group 2 reset
+      - description: window group 3 reset
+      - description: window group 4 reset
+      - description: window group 5 reset
+
+  reset-names:
+    items:
+      - const: misc
+      - const: wgrp0
+      - const: wgrp1
+      - const: wgrp2
+      - const: wgrp3
+      - const: wgrp4
+      - const: wgrp5
+
+  power-domains:
+    maxItems: 1
+
+  ranges:
+    maxItems: 1
+
+patternProperties:
+  "^display@[0-9a-f]+$":
+    type: object
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra186-display
+    then:
+      properties:
+        clocks:
+          items:
+            - description: display core clock
+            - description: display stream compression clock
+            - description: display hub clock
+
+        clock-names:
+          items:
+            - const: disp
+            - const: dsc
+            - const: hub
+    else:
+      properties:
+        clocks:
+          items:
+            - description: display core clock
+            - description: display hub clock
+
+        clock-names:
+          items:
+            - const: disp
+            - const: hub
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - power-domains
+  - "#address-cells"
+  - "#size-cells"
+  - ranges
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra186-clock.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/memory/tegra186-mc.h>
+    #include <dt-bindings/power/tegra186-powergate.h>
+    #include <dt-bindings/reset/tegra186-reset.h>
+
+    display-hub@15200000 {
+        compatible = "nvidia,tegra186-display";
+        reg = <0x15200000 0x00040000>;
+        resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
+                 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
+                 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
+                 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
+                 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
+                 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
+                 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
+        reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
+                      "wgrp3", "wgrp4", "wgrp5";
+        clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
+                 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
+                 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
+        clock-names = "disp", "dsc", "hub";
+        status = "disabled";
+
+        power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
+
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        ranges = <0x15200000 0x15200000 0x40000>;
+
+        display@15200000 {
+            compatible = "nvidia,tegra186-dc";
+            reg = <0x15200000 0x10000>;
+            interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
+            clock-names = "dc";
+            resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
+            reset-names = "dc";
+
+            power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
+            interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
+                            <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+            interconnect-names = "dma-mem", "read-1";
+            iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
+
+            nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
+            nvidia,head = <0>;
+        };
+
+        display@15210000 {
+            compatible = "nvidia,tegra186-dc";
+            reg = <0x15210000 0x10000>;
+            interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
+            clock-names = "dc";
+            resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
+            reset-names = "dc";
+
+            power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
+            interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
+                            <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+            interconnect-names = "dma-mem", "read-1";
+            iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
+
+            nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
+            nvidia,head = <1>;
+        };
+
+        display@15220000 {
+            compatible = "nvidia,tegra186-dc";
+            reg = <0x15220000 0x10000>;
+            interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
+            clock-names = "dc";
+            resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
+            reset-names = "dc";
+
+            power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
+            interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
+                            <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+            interconnect-names = "dma-mem", "read-1";
+            iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
+
+            nvidia,outputs = <&sor0 &sor1>;
+            nvidia,head = <2>;
+        };
+    };
+
+  - |
+    #include <dt-bindings/clock/tegra194-clock.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/memory/tegra194-mc.h>
+    #include <dt-bindings/power/tegra194-powergate.h>
+    #include <dt-bindings/reset/tegra194-reset.h>
+
+    display-hub@15200000 {
+        compatible = "nvidia,tegra194-display";
+        reg = <0x15200000 0x00040000>;
+        resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
+                 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
+                 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
+                 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
+                 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
+                 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
+                 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
+        reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
+                      "wgrp3", "wgrp4", "wgrp5";
+        clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
+                 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
+        clock-names = "disp", "hub";
+        status = "disabled";
+
+        power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        ranges = <0x15200000 0x15200000 0x40000>;
+
+        display@15200000 {
+            compatible = "nvidia,tegra194-dc";
+            reg = <0x15200000 0x10000>;
+            interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
+            clock-names = "dc";
+            resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
+            reset-names = "dc";
+
+            power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+            interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
+                            <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+            interconnect-names = "dma-mem", "read-1";
+
+            nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
+            nvidia,head = <0>;
+        };
+
+        display@15210000 {
+            compatible = "nvidia,tegra194-dc";
+            reg = <0x15210000 0x10000>;
+            interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
+            clock-names = "dc";
+            resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
+            reset-names = "dc";
+
+            power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
+            interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
+                            <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+            interconnect-names = "dma-mem", "read-1";
+
+            nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
+            nvidia,head = <1>;
+        };
+
+        display@15220000 {
+            compatible = "nvidia,tegra194-dc";
+            reg = <0x15220000 0x10000>;
+            interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
+            clock-names = "dc";
+            resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
+            reset-names = "dc";
+
+            power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
+            interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
+                            <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+            interconnect-names = "dma-mem", "read-1";
+
+            nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
+            nvidia,head = <2>;
+        };
+
+        display@15230000 {
+            compatible = "nvidia,tegra194-dc";
+            reg = <0x15230000 0x10000>;
+            interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
+            clock-names = "dc";
+            resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
+            reset-names = "dc";
+
+            power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
+            interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
+                            <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+            interconnect-names = "dma-mem", "read-1";
+
+            nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
+            nvidia,head = <3>;
+        };
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml
new file mode 100644
index 0000000000000..e5a6145c8c532
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dsi-padctl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra MIPI DSI pad controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^padctl@[0-9a-f]+$"
+
+  compatible:
+    const: nvidia,tegra186-dsi-padctl
+
+  reg:
+    maxItems: 1
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: dsi
+
+allOf:
+  - $ref: "/schemas/reset/reset.yaml"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/reset/tegra186-reset.h>
+
+    padctl@15880000 {
+        compatible = "nvidia,tegra186-dsi-padctl";
+        reg = <0x15880000 0x10000>;
+        resets = <&bpmp TEGRA186_RESET_DSI>;
+        reset-names = "dsi";
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml
new file mode 100644
index 0000000000000..6eedee503aa0f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml
@@ -0,0 +1,183 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Display Controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^dc@[0-9a-f]+$"
+
+  compatible:
+    oneOf:
+      - enum:
+          - nvidia,tegra20-dc
+          - nvidia,tegra30-dc
+          - nvidia,tegra114-dc
+          - nvidia,tegra124-dc
+          - nvidia,tegra210-dc
+
+      - items:
+          - const: nvidia,tegra124-dc
+          - const: nvidia,tegra132-dc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    items:
+      - description: display controller pixel clock
+      - description: parent clock # optional
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: dc
+      - const: parent # optional
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: dc
+
+  interconnect-names: true
+  interconnects: true
+
+  iommus:
+    maxItems: 1
+
+  operating-points-v2:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  power-domains:
+    items:
+      - description: phandle to the core power domain
+
+  memory-region: true
+
+  nvidia,head:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: The number of the display controller head. This is used to setup the various
+      types of output to receive video data from the given head.
+
+  nvidia,outputs:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description: A list of phandles of outputs that this display controller can drive.
+
+  rgb:
+    type: object
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra20-dc
+              - nvidia,tegra30-dc
+              - nvidia,tegra114-dc
+    then:
+      properties:
+        interconnects:
+          items:
+            - description: window A memory client
+            - description: window B memory client
+            - description: window B memory client (vertical filter)
+            - description: window C memory client
+            - description: cursor memory client
+
+        interconnect-names:
+          items:
+            - const: wina
+            - const: winb
+            - const: winb-vfilter
+            - const: winc
+            - const: cursor
+
+        rgb:
+          description: Each display controller node has a child node, named "rgb", that represents
+            the RGB output associated with the controller.
+          type: object
+          properties:
+            nvidia,ddc-i2c-bus:
+              $ref: /schemas/types.yaml#/definitions/phandle
+              description: phandle of an I2C controller used for DDC EDID probing
+
+            nvidia,hpd-gpio:
+              description: specifies a GPIO used for hotplug detection
+              maxItems: 1
+
+            nvidia,edid:
+              $ref: /schemas/types.yaml#/definitions/uint8-array
+              description: supplies a binary EDID blob
+
+            nvidia,panel:
+              $ref: /schemas/types.yaml#/definitions/phandle
+              description: phandle of a display panel
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra124-dc
+    then:
+      properties:
+        interconnects:
+          minItems: 4
+          items:
+            - description: window A memory client
+            - description: window B memory client
+            - description: window C memory client
+            - description: cursor memory client
+            - description: window D memory client
+            - description: window T memory client
+
+        interconnect-names:
+          minItems: 4
+          items:
+            - const: wina
+            - const: winb
+            - const: winc
+            - const: cursor
+            - const: wind
+            - const: wint
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra20-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    dc@54200000 {
+        compatible = "nvidia,tegra20-dc";
+        reg = <0x54200000 0x00040000>;
+        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&tegra_car TEGRA20_CLK_DISP1>;
+        clock-names = "dc";
+        resets = <&tegra_car 27>;
+        reset-names = "dc";
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml
new file mode 100644
index 0000000000000..75546f250ad7d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml
@@ -0,0 +1,159 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Display Serial Interface
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - nvidia,tegra20-dsi
+          - nvidia,tegra30-dsi
+          - nvidia,tegra114-dsi
+          - nvidia,tegra124-dsi
+          - nvidia,tegra210-dsi
+          - nvidia,tegra186-dsi
+
+      - items:
+          - const: nvidia,tegra132-dsi
+          - const: nvidia,tegra124-dsi
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 2
+    maxItems: 3
+
+  clock-names:
+    minItems: 2
+    maxItems: 3
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: dsi
+
+  operating-points-v2:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  power-domains:
+    maxItems: 1
+
+  avdd-dsi-csi-supply:
+    description: phandle of a supply that powers the DSI controller
+
+  nvidia,mipi-calibrate:
+    description: Should contain a phandle and a specifier specifying
+      which pads are used by this DSI output and need to be
+      calibrated. See nvidia,tegra114-mipi.yaml for details.
+    $ref: "/schemas/types.yaml#/definitions/phandle-array"
+
+  nvidia,ddc-i2c-bus:
+    description: phandle of an I2C controller used for DDC EDID
+      probing
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  nvidia,hpd-gpio:
+    description: specifies a GPIO used for hotplug detection
+    maxItems: 1
+
+  nvidia,edid:
+    description: supplies a binary EDID blob
+    $ref: "/schemas/types.yaml#/definitions/uint8-array"
+
+  nvidia,panel:
+    description: phandle of a display panel
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  nvidia,ganged-mode:
+    description: contains a phandle to a second DSI controller to
+      gang up with in order to support up to 8 data lanes
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+allOf:
+  - $ref: "../dsi-controller.yaml#"
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra20-dsi
+              - nvidia,tegra30-dsi
+    then:
+      properties:
+        clocks:
+          items:
+            - description: DSI module clock
+            - description: input for the pixel clock
+
+        clock-names:
+          items:
+            - const: dsi
+            - const: parent
+    else:
+      properties:
+        clocks:
+          items:
+            - description: DSI module clock
+            - description: low-power module clock
+            - description: input for the pixel clock
+
+        clock-names:
+          items:
+            - const: dsi
+            - const: lp
+            - const: parent
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra186-dsi
+    then:
+      required:
+        - interrupts
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra186-clock.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/tegra186-powergate.h>
+    #include <dt-bindings/reset/tegra186-reset.h>
+
+    dsi@15300000 {
+        compatible = "nvidia,tegra186-dsi";
+        reg = <0x15300000 0x10000>;
+        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&bpmp TEGRA186_CLK_DSI>,
+                 <&bpmp TEGRA186_CLK_DSIA_LP>,
+                 <&bpmp TEGRA186_CLK_PLLD>;
+        clock-names = "dsi", "lp", "parent";
+        resets = <&bpmp TEGRA186_RESET_DSI>;
+        reset-names = "dsi";
+
+        power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
new file mode 100644
index 0000000000000..0d55e6206b5e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-epp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Encoder Pre-Processor
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^epp@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - nvidia,tegra20-epp
+      - nvidia,tegra30-epp
+      - nvidia,tegra114-epp
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: epp
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    maxItems: 4
+
+  interconnect-names:
+    maxItems: 4
+
+  operating-points-v2:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  power-domains:
+    items:
+      - description: phandle to the core power domain
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra20-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    epp@540c0000 {
+        compatible = "nvidia,tegra20-epp";
+        reg = <0x540c0000 0x00040000>;
+        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&tegra_car TEGRA20_CLK_EPP>;
+        resets = <&tegra_car 19>;
+        reset-names = "epp";
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
new file mode 100644
index 0000000000000..bf38accd98eb5
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr2d.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA 2D graphics engine
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^gr2d@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - nvidia,tegra20-gr2d
+      - nvidia,tegra30-gr2d
+      - nvidia,tegra114-gr2d
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: module clock
+
+  resets:
+    items:
+      - description: module reset
+      - description: memory client hotflush reset
+
+  reset-names:
+    items:
+      - const: 2d
+      - const: mc
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    maxItems: 4
+
+  interconnect-names:
+    maxItems: 4
+
+  operating-points-v2:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  power-domains:
+    items:
+      - description: phandle to the HEG or core power domain
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra20-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/memory/tegra20-mc.h>
+
+    gr2d@54140000 {
+        compatible = "nvidia,tegra20-gr2d";
+        reg = <0x54140000 0x00040000>;
+        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&tegra_car TEGRA20_CLK_GR2D>;
+        resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
+        reset-names = "2d", "mc";
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
new file mode 100644
index 0000000000000..dbdf0229d9f65
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
@@ -0,0 +1,215 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr3d.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA 3D graphics engine
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^gr3d@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - nvidia,tegra20-gr3d
+      - nvidia,tegra30-gr3d
+      - nvidia,tegra114-gr3d
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+  clock-names:
+    minItems: 1
+    maxItems: 2
+
+  resets:
+    minItems: 2
+    maxItems: 4
+
+  reset-names:
+    minItems: 2
+    maxItems: 4
+
+  iommus:
+    minItems: 1
+    maxItems: 2
+
+  interconnects:
+    minItems: 4
+    maxItems: 10
+
+  interconnect-names:
+    minItems: 4
+    maxItems: 10
+
+  operating-points-v2:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  power-domains:
+    minItems: 1
+    maxItems: 2
+
+  power-domain-names:
+    minItems: 2
+    maxItems: 2
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra20-gr2d
+    then:
+      properties:
+        clocks:
+          items:
+            - description: module clock
+
+        clock-names:
+          items:
+            - const: 3d
+
+        resets:
+          items:
+            - description: module reset
+            - description: memory client hotflush reset
+
+        reset-names:
+          items:
+            - const: 3d
+            - const: mc
+
+        iommus:
+          maxItems: 1
+
+        interconnects:
+          minItems: 4
+          maxItems: 4
+
+        interconnect-names:
+          minItems: 4
+          maxItems: 4
+
+        power-domains:
+          items:
+            - description: phandle to the TD power domain
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra30-gr3d
+    then:
+      properties:
+        clocks:
+          items:
+            - description: primary module clock
+            - description: secondary module clock
+
+        clock-names:
+          items:
+            - const: 3d
+            - const: 3d2
+
+        resets:
+          items:
+            - description: primary module reset
+            - description: secondary module reset
+            - description: primary memory client hotflush reset
+            - description: secondary memory client hotflush reset
+
+        reset-names:
+          items:
+            - const: 3d
+            - const: 3d2
+            - const: mc
+            - const: mc2
+
+        iommus:
+          minItems: 2
+          maxItems: 2
+
+        interconnects:
+          minItems: 8
+          maxItems: 8
+
+        interconnect-names:
+          minItems: 8
+          maxItems: 8
+
+        power-domains:
+          items:
+            - description: phandle to the TD power domain
+            - description: phandle to the TD2 power domain
+
+        power-domain-names:
+          items:
+            - const: 3d0
+            - const: 3d1
+
+      dependencies:
+        power-domains: [ power-domain-names ]
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra114-gr2d
+    then:
+      properties:
+        clocks:
+          items:
+            - description: module clock
+
+        clock-names:
+          items:
+            - const: 3d
+
+        resets:
+          items:
+            - description: module reset
+            - description: memory client hotflush reset
+
+        reset-names:
+          items:
+            - const: 3d
+            - const: mc
+
+        iommus:
+          maxItems: 1
+
+        interconnects:
+          minItems: 10
+          maxItems: 10
+
+        interconnect-names:
+          minItems: 10
+          maxItems: 10
+
+        power-domains:
+          items:
+            - description: phandle to the TD power domain
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra20-car.h>
+    #include <dt-bindings/memory/tegra20-mc.h>
+
+    gr3d@54180000 {
+        compatible = "nvidia,tegra20-gr3d";
+        reg = <0x54180000 0x00040000>;
+        clocks = <&tegra_car TEGRA20_CLK_GR3D>;
+        resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
+        reset-names = "3d", "mc";
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml
new file mode 100644
index 0000000000000..035b9f1f2eb52
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra HDMI Output Encoder
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^hdmi@[0-9a-f]+$"
+
+  compatible:
+    oneOf:
+      - enum:
+          - nvidia,tegra20-hdmi
+          - nvidia,tegra30-hdmi
+          - nvidia,tegra114-hdmi
+          - nvidia,tegra124-hdmi
+
+      - items:
+          - const: nvidia,tegra132-hdmi
+          - const: nvidia,tegra124-hdmi
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: module clock
+      - description: parent clock
+
+  clock-names:
+    items:
+      - const: hdmi
+      - const: parent
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: hdmi
+
+  operating-points-v2:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  power-domains:
+    items:
+      - description: phandle to the core power domain
+
+  hdmi-supply:
+    description: supply for the +5V HDMI connector pin
+
+  vdd-supply:
+    description: regulator for supply voltage
+
+  pll-supply:
+    description: regulator for PLL
+
+  nvidia,ddc-i2c-bus:
+    description: phandle of an I2C controller used for DDC EDID
+      probing
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  nvidia,hpd-gpio:
+    description: specifies a GPIO used for hotplug detection
+    maxItems: 1
+
+  nvidia,edid:
+    description: supplies a binary EDID blob
+    $ref: "/schemas/types.yaml#/definitions/uint8-array"
+
+  nvidia,panel:
+    description: phandle of a display panel
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  "#sound-dai-cells":
+    const: 0
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - pll-supply
+  - vdd-supply
+  - nvidia,ddc-i2c-bus
+  - nvidia,hpd-gpio
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra124-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/gpio/tegra-gpio.h>
+
+    hdmi@54280000 {
+        compatible = "nvidia,tegra124-hdmi";
+        reg = <0x54280000 0x00040000>;
+        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&tegra_car TEGRA124_CLK_HDMI>,
+                 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
+        clock-names = "hdmi", "parent";
+        resets = <&tegra_car 51>;
+        reset-names = "hdmi";
+
+        hdmi-supply = <&vdd_5v0_hdmi>;
+        pll-supply = <&vdd_hdmi_pll>;
+        vdd-supply = <&vdd_3v3_hdmi>;
+
+        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
deleted file mode 100644
index e61999ce54e96..0000000000000
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
+++ /dev/null
@@ -1,675 +0,0 @@
-NVIDIA Tegra host1x
-
-Required properties:
-- compatible: "nvidia,tegra<chip>-host1x"
-- reg: Physical base address and length of the controller's registers.
-  For pre-Tegra186, one entry describing the whole register area.
-  For Tegra186, one entry for each entry in reg-names:
-    "vm" - VM region assigned to Linux
-    "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
-- interrupts: The interrupt outputs from the controller.
-- #address-cells: The number of cells used to represent physical base addresses
-  in the host1x address space. Should be 1.
-- #size-cells: The number of cells used to represent the size of an address
-  range in the host1x address space. Should be 1.
-- ranges: The mapping of the host1x address space to the CPU address space.
-- clocks: Must contain one entry, for the module clock.
-  See ../clocks/clock-bindings.txt for details.
-- resets: Must contain an entry for each entry in reset-names.
-  See ../reset/reset.txt for details.
-- reset-names: Must include the following entries:
-  - host1x
-  - mc
-
-Optional properties:
-- operating-points-v2: See ../bindings/opp/opp.txt for details.
-  - power-domains: Phandle to HEG or core power domain.
-
-For each opp entry in 'operating-points-v2' table of host1x and its modules:
-- opp-supported-hw: One bitfield indicating:
-	On Tegra20: SoC process ID mask
-	On Tegra30+: SoC speedo ID mask
-
-	A bitwise AND is performed against the value and if any bit
-	matches, the OPP gets enabled.
-
-Each host1x client module having to perform DMA through the Memory Controller
-should have the interconnect endpoints set to the Memory Client and External
-Memory respectively.
-
-The host1x top-level node defines a number of children, each representing one
-of the following host1x client modules:
-
-- mpe: video encoder
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-mpe"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-  - clocks: Must contain one entry, for the module clock.
-    See ../clocks/clock-bindings.txt for details.
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - mpe
-
-  Optional properties:
-  - interconnects: Must contain entry for the MPE memory clients.
-  - interconnect-names: Must include name of the interconnect path for each
-    interconnect entry. Consult TRM documentation for information about
-    available memory clients, see MEMORY CONTROLLER section.
-  - operating-points-v2: See ../bindings/opp/opp.txt for details.
-  - power-domains: Phandle to MPE power domain.
-
-- vi: video input
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-vi"
-  - reg: Physical base address and length of the controller registers.
-  - interrupts: The interrupt outputs from the controller.
-  - clocks: clocks: Must contain one entry, for the module clock.
-    See ../clocks/clock-bindings.txt for details.
-  - Tegra20/Tegra30/Tegra114/Tegra124:
-    - resets: Must contain an entry for each entry in reset-names.
-      See ../reset/reset.txt for details.
-    - reset-names: Must include the following entries:
-      - vi
-  - Tegra210:
-    - power-domains: Must include venc powergate node as vi is in VE partition.
-
-  ports (optional node)
-  vi can have optional ports node and max 6 ports are supported. Each port
-  should have single 'endpoint' child node. All port nodes are grouped under
-  ports node. Please refer to the bindings defined in
-  Documentation/devicetree/bindings/media/video-interfaces.txt
-
-  csi (required node)
-  Tegra210 has CSI part of VI sharing same host interface and register space.
-  So, VI device node should have CSI child node.
-
-    - csi: mipi csi interface to vi
-
-      Required properties:
-      - compatible: "nvidia,tegra210-csi"
-      - reg: Physical base address offset to parent and length of the controller
-        registers.
-      - clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks.
-        See ../clocks/clock-bindings.txt for details.
-      - power-domains: Must include sor powergate node as csicil is in
-        SOR partition.
-
-      channel (optional nodes)
-      Maximum 6 channels are supported with each csi brick as either x4 or x2
-      based on hw connectivity to sensor.
-
-      Required properties:
-      - reg: csi port number. Valid port numbers are 0 through 5.
-      - nvidia,mipi-calibrate: Should contain a phandle and a specifier
-        specifying which pads are used by this CSI port and need to be
-	calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt.
-
-      Each channel node must contain 2 port nodes which can be grouped
-      under 'ports' node and each port should have a single child 'endpoint'
-      node.
-
-        ports node
-        Please refer to the bindings defined in
-        Documentation/devicetree/bindings/media/video-interfaces.txt
-
-        ports node must contain below 2 port nodes.
-        port@0 with single child 'endpoint' node always a sink.
-        port@1 with single child 'endpoint' node always a source.
-
-        port@0 (required node)
-        Required properties:
-        - reg: 0
-
-	  endpoint (required node)
-	  Required properties:
-	  - data-lanes: an array of data lane from 1 to 8. Valid array
-	    lengths are 1/2/4/8.
-	  - remote-endpoint: phandle to sensor 'endpoint' node.
-
-        port@1 (required node)
-        Required properties:
-        - reg: 1
-
-	  endpoint (required node)
-	  Required properties:
-	  - remote-endpoint: phandle to vi port 'endpoint' node.
-
-  Optional properties:
-  - interconnects: Must contain entry for the VI memory clients.
-  - interconnect-names: Must include name of the interconnect path for each
-    interconnect entry. Consult TRM documentation for information about
-    available memory clients, see MEMORY CONTROLLER section.
-  - operating-points-v2: See ../bindings/opp/opp.txt for details.
-  - power-domains: Phandle to VENC power domain.
-
-- epp: encoder pre-processor
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-epp"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-  - clocks: Must contain one entry, for the module clock.
-    See ../clocks/clock-bindings.txt for details.
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - epp
-
-  Optional properties:
-  - interconnects: Must contain entry for the EPP memory clients.
-  - interconnect-names: Must include name of the interconnect path for each
-    interconnect entry. Consult TRM documentation for information about
-    available memory clients, see MEMORY CONTROLLER section.
-  - operating-points-v2: See ../bindings/opp/opp.txt for details.
-  - power-domains: Phandle to HEG or core power domain.
-
-- isp: image signal processor
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-isp"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-  - clocks: Must contain one entry, for the module clock.
-    See ../clocks/clock-bindings.txt for details.
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - isp
-
-  Optional properties:
-  - interconnects: Must contain entry for the ISP memory clients.
-  - interconnect-names: Must include name of the interconnect path for each
-    interconnect entry. Consult TRM documentation for information about
-    available memory clients, see MEMORY CONTROLLER section.
-  - power-domains: Phandle to VENC or core power domain.
-
-- gr2d: 2D graphics engine
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-gr2d"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-  - clocks: Must contain one entry, for the module clock.
-    See ../clocks/clock-bindings.txt for details.
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - 2d
-    - mc
-
-  Optional properties:
-  - interconnects: Must contain entry for the GR2D memory clients.
-  - interconnect-names: Must include name of the interconnect path for each
-    interconnect entry. Consult TRM documentation for information about
-    available memory clients, see MEMORY CONTROLLER section.
-  - operating-points-v2: See ../bindings/opp/opp.txt for details.
-  - power-domains: Phandle to HEG or core power domain.
-
-- gr3d: 3D graphics engine
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-gr3d"
-  - reg: Physical base address and length of the controller's registers.
-  - clocks: Must contain an entry for each entry in clock-names.
-    See ../clocks/clock-bindings.txt for details.
-  - clock-names: Must include the following entries:
-    (This property may be omitted if the only clock in the list is "3d")
-    - 3d
-      This MUST be the first entry.
-    - 3d2 (Only required on SoCs with two 3D clocks)
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - 3d
-    - 3d2 (Only required on SoCs with two 3D clocks)
-    - mc
-    - mc2 (Only required on SoCs with two 3D clocks)
-
-  Optional properties:
-  - interconnects: Must contain entry for the GR3D memory clients.
-  - interconnect-names: Must include name of the interconnect path for each
-    interconnect entry. Consult TRM documentation for information about
-    available memory clients, see MEMORY CONTROLLER section.
-  - operating-points-v2: See ../bindings/opp/opp.txt for details.
-  - power-domains: Phandles to 3D or core power domain.
-
-- dc: display controller
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-dc"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-  - clocks: Must contain an entry for each entry in clock-names.
-    See ../clocks/clock-bindings.txt for details.
-  - clock-names: Must include the following entries:
-    - dc
-      This MUST be the first entry.
-    - parent
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - dc
-  - nvidia,head: The number of the display controller head. This is used to
-    setup the various types of output to receive video data from the given
-    head.
-
-  Each display controller node has a child node, named "rgb", that represents
-  the RGB output associated with the controller. It can take the following
-  optional properties:
-  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
-  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
-  - nvidia,edid: supplies a binary EDID blob
-  - nvidia,panel: phandle of a display panel
-  - interconnects: Must contain entry for the DC memory clients.
-  - interconnect-names: Must include name of the interconnect path for each
-    interconnect entry. Consult TRM documentation for information about
-    available memory clients, see MEMORY CONTROLLER section.
-  - operating-points-v2: See ../bindings/opp/opp.txt for details.
-  - power-domains: Phandle to core power domain.
-
-- hdmi: High Definition Multimedia Interface
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-hdmi"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-  - hdmi-supply: supply for the +5V HDMI connector pin
-  - vdd-supply: regulator for supply voltage
-  - pll-supply: regulator for PLL
-  - clocks: Must contain an entry for each entry in clock-names.
-    See ../clocks/clock-bindings.txt for details.
-  - clock-names: Must include the following entries:
-    - hdmi
-      This MUST be the first entry.
-    - parent
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - hdmi
-
-  Optional properties:
-  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
-  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
-  - nvidia,edid: supplies a binary EDID blob
-  - nvidia,panel: phandle of a display panel
-  - operating-points-v2: See ../bindings/opp/opp.txt for details.
-
-- tvo: TV encoder output
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-tvo"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-  - clocks: Must contain one entry, for the module clock.
-    See ../clocks/clock-bindings.txt for details.
-
-  Optional properties:
-  - operating-points-v2: See ../bindings/opp/opp.txt for details.
-  - power-domains: Phandle to core power domain.
-
-- dsi: display serial interface
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-dsi"
-  - reg: Physical base address and length of the controller's registers.
-  - clocks: Must contain an entry for each entry in clock-names.
-    See ../clocks/clock-bindings.txt for details.
-  - clock-names: Must include the following entries:
-    - dsi
-      This MUST be the first entry.
-    - lp
-    - parent
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - dsi
-  - avdd-dsi-supply: phandle of a supply that powers the DSI controller
-  - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
-    which pads are used by this DSI output and need to be calibrated. See also
-    ../display/tegra/nvidia,tegra114-mipi.txt.
-
-  Optional properties:
-  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
-  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
-  - nvidia,edid: supplies a binary EDID blob
-  - nvidia,panel: phandle of a display panel
-  - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
-    up with in order to support up to 8 data lanes
-  - operating-points-v2: See ../bindings/opp/opp.txt for details.
-
-- sor: serial output resource
-
-  Required properties:
-  - compatible: Should be:
-    - "nvidia,tegra124-sor": for Tegra124 and Tegra132
-    - "nvidia,tegra132-sor": for Tegra132
-    - "nvidia,tegra210-sor": for Tegra210
-    - "nvidia,tegra210-sor1": for Tegra210
-    - "nvidia,tegra186-sor": for Tegra186
-    - "nvidia,tegra186-sor1": for Tegra186
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-  - clocks: Must contain an entry for each entry in clock-names.
-    See ../clocks/clock-bindings.txt for details.
-  - clock-names: Must include the following entries:
-    - sor: clock input for the SOR hardware
-    - out: SOR output clock
-    - parent: input for the pixel clock
-    - dp: reference clock for the SOR clock
-    - safe: safe reference for the SOR clock during power up
-
-    For Tegra186 and later:
-    - pad: SOR pad output clock (on Tegra186 and later)
-
-    Obsolete:
-    - source: source clock for the SOR clock (obsolete, use "out" instead)
-
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - sor
-
-  Required properties on Tegra186 and later:
-  - nvidia,interface: index of the SOR interface
-
-  Optional properties:
-  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
-  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
-  - nvidia,edid: supplies a binary EDID blob
-  - nvidia,panel: phandle of a display panel
-  - nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane
-    of the SOR, identified by the cell's index, is mapped via the crossbar to
-    the pad specified by the cell's value.
-
-  Optional properties when driving an eDP output:
-  - nvidia,dpaux: phandle to a DispayPort AUX interface
-
-- dpaux: DisplayPort AUX interface
-  - compatible : Should contain one of the following:
-    - "nvidia,tegra124-dpaux": for Tegra124 and Tegra132
-    - "nvidia,tegra210-dpaux": for Tegra210
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-  - clocks: Must contain an entry for each entry in clock-names.
-    See ../clocks/clock-bindings.txt for details.
-  - clock-names: Must include the following entries:
-    - dpaux: clock input for the DPAUX hardware
-    - parent: reference clock
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - dpaux
-  - vdd-supply: phandle of a supply that powers the DisplayPort link
-  - i2c-bus: Subnode where I2C slave devices are listed. This subnode
-    must be always present. If there are no I2C slave devices, an empty
-    node should be added. See ../../i2c/i2c.txt for more information.
-
-  See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information
-  regarding the DPAUX pad controller bindings.
-
-- vic: Video Image Compositor
-  - compatible : "nvidia,tegra<chip>-vic"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-  - clocks: Must contain an entry for each entry in clock-names.
-    See ../clocks/clock-bindings.txt for details.
-  - clock-names: Must include the following entries:
-    - vic: clock input for the VIC hardware
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - vic
-
-  Optional properties:
-  - interconnects: Must contain entry for the VIC memory clients.
-  - interconnect-names: Must include name of the interconnect path for each
-    interconnect entry. Consult TRM documentation for information about
-    available memory clients, see MEMORY CONTROLLER section.
-
-Example:
-
-/ {
-	...
-
-	host1x {
-		compatible = "nvidia,tegra20-host1x", "simple-bus";
-		reg = <0x50000000 0x00024000>;
-		interrupts = <0 65 0x04   /* mpcore syncpt */
-			      0 67 0x04>; /* mpcore general */
-		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
-		resets = <&tegra_car 28>;
-		reset-names = "host1x";
-		operating-points-v2 = <&dvfs_opp_table>;
-		power-domains = <&domain>;
-
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		ranges = <0x54000000 0x54000000 0x04000000>;
-
-		mpe {
-			compatible = "nvidia,tegra20-mpe";
-			reg = <0x54040000 0x00040000>;
-			interrupts = <0 68 0x04>;
-			clocks = <&tegra_car TEGRA20_CLK_MPE>;
-			resets = <&tegra_car 60>;
-			reset-names = "mpe";
-			operating-points-v2 = <&dvfs_opp_table>;
-			power-domains = <&domain>;
-		};
-
-		vi@54080000 {
-			compatible = "nvidia,tegra210-vi";
-			reg = <0x0 0x54080000 0x0 0x700>;
-			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-			assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
-			assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
-			operating-points-v2 = <&dvfs_opp_table>;
-
-			clocks = <&tegra_car TEGRA210_CLK_VI>;
-			power-domains = <&pd_venc>;
-
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			ranges = <0x0 0x0 0x54080000 0x2000>;
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@0 {
-					reg = <0>;
-					imx219_vi_in0: endpoint {
-						remote-endpoint = <&imx219_csi_out0>;
-					};
-				};
-			};
-
-			csi@838 {
-				compatible = "nvidia,tegra210-csi";
-				reg = <0x838 0x1300>;
-				assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
-						  <&tegra_car TEGRA210_CLK_CILCD>,
-						  <&tegra_car TEGRA210_CLK_CILE>,
-						  <&tegra_car TEGRA210_CLK_CSI_TPG>;
-				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
-							 <&tegra_car TEGRA210_CLK_PLL_P>,
-							 <&tegra_car TEGRA210_CLK_PLL_P>;
-				assigned-clock-rates = <102000000>,
-						       <102000000>,
-						       <102000000>,
-						       <972000000>;
-
-				clocks = <&tegra_car TEGRA210_CLK_CSI>,
-					 <&tegra_car TEGRA210_CLK_CILAB>,
-					 <&tegra_car TEGRA210_CLK_CILCD>,
-					 <&tegra_car TEGRA210_CLK_CILE>,
-					 <&tegra_car TEGRA210_CLK_CSI_TPG>;
-				clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
-				power-domains = <&pd_sor>;
-
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				channel@0 {
-					reg = <0>;
-					nvidia,mipi-calibrate = <&mipi 0x001>;
-
-					ports {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						port@0 {
-							reg = <0>;
-							imx219_csi_in0: endpoint {
-								data-lanes = <1 2>;
-								remote-endpoint = <&imx219_out0>;
-							};
-						};
-
-						port@1 {
-							reg = <1>;
-							imx219_csi_out0: endpoint {
-								remote-endpoint = <&imx219_vi_in0>;
-							};
-						};
-					};
-				};
-			};
-		};
-
-		epp {
-			compatible = "nvidia,tegra20-epp";
-			reg = <0x540c0000 0x00040000>;
-			interrupts = <0 70 0x04>;
-			clocks = <&tegra_car TEGRA20_CLK_EPP>;
-			resets = <&tegra_car 19>;
-			reset-names = "epp";
-			operating-points-v2 = <&dvfs_opp_table>;
-			power-domains = <&domain>;
-		};
-
-		isp {
-			compatible = "nvidia,tegra20-isp";
-			reg = <0x54100000 0x00040000>;
-			interrupts = <0 71 0x04>;
-			clocks = <&tegra_car TEGRA20_CLK_ISP>;
-			resets = <&tegra_car 23>;
-			reset-names = "isp";
-		};
-
-		gr2d {
-			compatible = "nvidia,tegra20-gr2d";
-			reg = <0x54140000 0x00040000>;
-			interrupts = <0 72 0x04>;
-			clocks = <&tegra_car TEGRA20_CLK_GR2D>;
-			resets = <&tegra_car 21>;
-			reset-names = "2d";
-			operating-points-v2 = <&dvfs_opp_table>;
-			power-domains = <&domain>;
-		};
-
-		gr3d {
-			compatible = "nvidia,tegra20-gr3d";
-			reg = <0x54180000 0x00040000>;
-			clocks = <&tegra_car TEGRA20_CLK_GR3D>;
-			resets = <&tegra_car 24>;
-			reset-names = "3d";
-			operating-points-v2 = <&dvfs_opp_table>;
-			power-domains = <&domain>;
-		};
-
-		dc@54200000 {
-			compatible = "nvidia,tegra20-dc";
-			reg = <0x54200000 0x00040000>;
-			interrupts = <0 73 0x04>;
-			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
-				 <&tegra_car TEGRA20_CLK_PLL_P>;
-			clock-names = "dc", "parent";
-			resets = <&tegra_car 27>;
-			reset-names = "dc";
-			operating-points-v2 = <&dvfs_opp_table>;
-			power-domains = <&domain>;
-
-			interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>,
-					<&mc TEGRA20_MC_DISPLAY0B &emc>,
-					<&mc TEGRA20_MC_DISPLAY0C &emc>,
-					<&mc TEGRA20_MC_DISPLAYHC &emc>;
-			interconnect-names = "wina",
-					     "winb",
-					     "winc",
-					     "cursor";
-
-			rgb {
-				status = "disabled";
-			};
-		};
-
-		dc@54240000 {
-			compatible = "nvidia,tegra20-dc";
-			reg = <0x54240000 0x00040000>;
-			interrupts = <0 74 0x04>;
-			clocks = <&tegra_car TEGRA20_CLK_DISP2>,
-				 <&tegra_car TEGRA20_CLK_PLL_P>;
-			clock-names = "dc", "parent";
-			resets = <&tegra_car 26>;
-			reset-names = "dc";
-			operating-points-v2 = <&dvfs_opp_table>;
-			power-domains = <&domain>;
-
-			interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>,
-					<&mc TEGRA20_MC_DISPLAY0BB &emc>,
-					<&mc TEGRA20_MC_DISPLAY0CB &emc>,
-					<&mc TEGRA20_MC_DISPLAYHCB &emc>;
-			interconnect-names = "wina",
-					     "winb",
-					     "winc",
-					     "cursor";
-
-			rgb {
-				status = "disabled";
-			};
-		};
-
-		hdmi {
-			compatible = "nvidia,tegra20-hdmi";
-			reg = <0x54280000 0x00040000>;
-			interrupts = <0 75 0x04>;
-			clocks = <&tegra_car TEGRA20_CLK_HDMI>,
-				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
-			clock-names = "hdmi", "parent";
-			resets = <&tegra_car 51>;
-			reset-names = "hdmi";
-			status = "disabled";
-			operating-points-v2 = <&dvfs_opp_table>;
-		};
-
-		tvo {
-			compatible = "nvidia,tegra20-tvo";
-			reg = <0x542c0000 0x00040000>;
-			interrupts = <0 76 0x04>;
-			clocks = <&tegra_car TEGRA20_CLK_TVO>;
-			status = "disabled";
-			operating-points-v2 = <&dvfs_opp_table>;
-		};
-
-		dsi {
-			compatible = "nvidia,tegra20-dsi";
-			reg = <0x54300000 0x00040000>;
-			clocks = <&tegra_car TEGRA20_CLK_DSI>,
-				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
-			clock-names = "dsi", "parent";
-			resets = <&tegra_car 48>;
-			reset-names = "dsi";
-			status = "disabled";
-			operating-points-v2 = <&dvfs_opp_table>;
-		};
-	};
-
-	...
-};
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
new file mode 100644
index 0000000000000..5b3df384f1a07
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
@@ -0,0 +1,348 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra host1x controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+description: The host1x top-level node defines a number of children, each
+  representing one of the host1x client modules defined in this binding.
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - nvidia,tegra20-host1x
+          - nvidia,tegra30-host1x
+          - nvidia,tegra114-host1x
+          - nvidia,tegra124-host1x
+          - nvidia,tegra210-host1x
+          - nvidia,tegra186-host1x
+          - nvidia,tegra194-host1x
+
+      - items:
+          - const: nvidia,tegra132-host1x
+          - const: nvidia,tegra124-host1x
+
+  reg:
+    minItems: 1
+    maxItems: 2
+
+  reg-names:
+    minItems: 1
+    maxItems: 2
+
+  interrupts:
+    items:
+      - description: host1x syncpoint interrupt
+      - description: host1x general interrupt
+    minItems: 1
+
+  interrupt-names:
+    items:
+      - const: syncpt
+      - const: host1x
+    minItems: 1
+
+  '#address-cells':
+    description: The number of cells used to represent physical base addresses
+      in the host1x address space.
+    enum: [1, 2]
+
+  '#size-cells':
+    description: The number of cells used to represent the size of an address
+      range in the host1x address space.
+    enum: [1, 2]
+
+  ranges:
+    maxItems: 1
+
+  clocks:
+    description: Must contain one entry, for the module clock. See
+      ../clocks/clock-bindings.txt for details.
+
+  clock-names:
+    items:
+      - const: host1x
+
+  resets:
+    minItems: 1 # MC reset is optional on Tegra186 and later
+    items:
+      - description: module reset
+      - description: memory client hotflush reset
+
+  reset-names:
+    minItems: 1 # MC reset is optional on Tegra186 and later
+    items:
+      - const: host1x
+      - const: mc
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    items:
+      - description: memory read client for host1x
+
+  interconnect-names:
+    items:
+      - const: dma-mem # read
+
+  operating-points-v2:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  power-domains:
+    items:
+      - description: phandle to the HEG or core power domain
+
+required:
+  - compatible
+  - interrupts
+  - interrupt-names
+  - '#address-cells'
+  - '#size-cells'
+  - ranges
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+
+unevaluatedProperties:
+  type: object
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra186-host1x
+              - nvidia,tegra194-host1x
+    then:
+      properties:
+        reg-names:
+          items:
+            - const: hypervisor
+            - const: vm
+
+        reg:
+          items:
+            - description: physical base address and length of the register
+                region assigned to the VM
+            - description: physical base address and length of the register
+                region used by the hypervisor
+
+        resets:
+          maxItems: 1
+
+        reset-names:
+          maxItems: 1
+
+      required:
+        - reg-names
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra20-car.h>
+    #include <dt-bindings/gpio/tegra-gpio.h>
+    #include <dt-bindings/memory/tegra20-mc.h>
+
+    host1x@50000000 {
+        compatible = "nvidia,tegra20-host1x";
+        reg = <0x50000000 0x00024000>;
+        interrupts = <0 65 0x04   /* mpcore syncpt */
+                      0 67 0x04>; /* mpcore general */
+        interrupt-names = "syncpt", "host1x";
+        clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
+        clock-names = "host1x";
+        resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>;
+        reset-names = "host1x", "mc";
+
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        ranges = <0x54000000 0x54000000 0x04000000>;
+
+        mpe@54040000 {
+            compatible = "nvidia,tegra20-mpe";
+            reg = <0x54040000 0x00040000>;
+            interrupts = <0 68 0x04>;
+            clocks = <&tegra_car TEGRA20_CLK_MPE>;
+            resets = <&tegra_car 60>;
+            reset-names = "mpe";
+        };
+
+        vi@54080000 {
+            compatible = "nvidia,tegra20-vi";
+            reg = <0x54080000 0x00040000>;
+            interrupts = <0 69 0x04>;
+            clocks = <&tegra_car TEGRA20_CLK_VI>;
+            resets = <&tegra_car 100>;
+            reset-names = "vi";
+        };
+
+        epp@540c0000 {
+            compatible = "nvidia,tegra20-epp";
+            reg = <0x540c0000 0x00040000>;
+            interrupts = <0 70 0x04>;
+            clocks = <&tegra_car TEGRA20_CLK_EPP>;
+            resets = <&tegra_car 19>;
+            reset-names = "epp";
+        };
+
+        isp@54100000 {
+            compatible = "nvidia,tegra20-isp";
+            reg = <0x54100000 0x00040000>;
+            interrupts = <0 71 0x04>;
+            clocks = <&tegra_car TEGRA20_CLK_ISP>;
+            resets = <&tegra_car 23>;
+            reset-names = "isp";
+        };
+
+        gr2d@54140000 {
+            compatible = "nvidia,tegra20-gr2d";
+            reg = <0x54140000 0x00040000>;
+            interrupts = <0 72 0x04>;
+            clocks = <&tegra_car TEGRA20_CLK_GR2D>;
+            resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
+            reset-names = "2d", "mc";
+        };
+
+        gr3d@54180000 {
+            compatible = "nvidia,tegra20-gr3d";
+            reg = <0x54180000 0x00040000>;
+            clocks = <&tegra_car TEGRA20_CLK_GR3D>;
+            resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
+            reset-names = "3d", "mc";
+        };
+
+        dc@54200000 {
+            compatible = "nvidia,tegra20-dc";
+            reg = <0x54200000 0x00040000>;
+            interrupts = <0 73 0x04>;
+            clocks = <&tegra_car TEGRA20_CLK_DISP1>;
+            clock-names = "dc";
+            resets = <&tegra_car 27>;
+            reset-names = "dc";
+
+            rgb {
+            };
+        };
+
+        dc@54240000 {
+            compatible = "nvidia,tegra20-dc";
+            reg = <0x54240000 0x00040000>;
+            interrupts = <0 74 0x04>;
+            clocks = <&tegra_car TEGRA20_CLK_DISP2>;
+            clock-names = "dc";
+            resets = <&tegra_car 26>;
+            reset-names = "dc";
+
+            rgb {
+            };
+        };
+
+        hdmi@54280000 {
+            compatible = "nvidia,tegra20-hdmi";
+            reg = <0x54280000 0x00040000>;
+            interrupts = <0 75 0x04>;
+            clocks = <&tegra_car TEGRA20_CLK_HDMI>,
+                     <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
+            clock-names = "hdmi", "parent";
+            resets = <&tegra_car 51>;
+            reset-names = "hdmi";
+
+            hdmi-supply = <&vdd_5v0_hdmi>;
+            pll-supply = <&vdd_hdmi_pll>;
+            vdd-supply = <&vdd_3v3_hdmi>;
+
+            nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+            nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+        };
+
+        tvo@542c0000 {
+            compatible = "nvidia,tegra20-tvo";
+            reg = <0x542c0000 0x00040000>;
+            interrupts = <0 76 0x04>;
+            clocks = <&tegra_car TEGRA20_CLK_TVO>;
+        };
+
+        dsi@54300000 {
+            compatible = "nvidia,tegra20-dsi";
+            reg = <0x54300000 0x00040000>;
+            clocks = <&tegra_car TEGRA20_CLK_DSI>,
+                     <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
+            clock-names = "dsi", "parent";
+            resets = <&tegra_car 48>;
+            reset-names = "dsi";
+        };
+    };
+
+  - |
+    #include <dt-bindings/clock/tegra210-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/memory/tegra210-mc.h>
+
+    host1x@50000000 {
+        compatible = "nvidia,tegra210-host1x";
+        reg = <0x50000000 0x00024000>;
+        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* mpcore syncpt */
+                     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* mpcore general */
+        interrupt-names = "syncpt", "host1x";
+        clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
+        clock-names = "host1x";
+        resets = <&tegra_car 28>;
+        reset-names = "host1x";
+
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        ranges = <0x54000000 0x54000000 0x01000000>;
+        iommus = <&mc TEGRA_SWGROUP_HC>;
+
+        vi@54080000 {
+            compatible = "nvidia,tegra210-vi";
+            reg = <0x54080000 0x00000700>;
+            interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+            assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
+            assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
+
+            clocks = <&tegra_car TEGRA210_CLK_VI>;
+            power-domains = <&pd_venc>;
+
+            #address-cells = <1>;
+            #size-cells = <1>;
+
+            ranges = <0x0 0x54080000 0x2000>;
+
+            csi@838 {
+                compatible = "nvidia,tegra210-csi";
+                reg = <0x838 0x1300>;
+                assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
+                                  <&tegra_car TEGRA210_CLK_CILCD>,
+                                  <&tegra_car TEGRA210_CLK_CILE>,
+                                  <&tegra_car TEGRA210_CLK_CSI_TPG>;
+                assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
+                                         <&tegra_car TEGRA210_CLK_PLL_P>,
+                                         <&tegra_car TEGRA210_CLK_PLL_P>;
+                assigned-clock-rates = <102000000>,
+                                       <102000000>,
+                                       <102000000>,
+                                       <972000000>;
+
+                clocks = <&tegra_car TEGRA210_CLK_CSI>,
+                         <&tegra_car TEGRA210_CLK_CILAB>,
+                         <&tegra_car TEGRA210_CLK_CILCD>,
+                         <&tegra_car TEGRA210_CLK_CILE>,
+                         <&tegra_car TEGRA210_CLK_CSI_TPG>;
+                clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
+                power-domains = <&pd_sor>;
+            };
+        };
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
new file mode 100644
index 0000000000000..3bc3b22e98e1d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra ISP processor
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  compatible:
+    enum:
+      - nvidia,tegra20-isp
+      - nvidia,tegra30-isp
+      - nvidia,tegra210-isp
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: module clock
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: isp
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    items:
+      - description: memory write client
+
+  interconnect-names:
+    items:
+      - const: dma-mem # write
+
+  power-domains:
+    items:
+      - description: phandle to the VENC or core power domain
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra20-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    isp@54100000 {
+        compatible = "nvidia,tegra20-isp";
+        reg = <0x54100000 0x00040000>;
+        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&tegra_car TEGRA20_CLK_ISP>;
+        resets = <&tegra_car 23>;
+        reset-names = "isp";
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
new file mode 100644
index 0000000000000..4154ae01ad133
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-mpe.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Video Encoder
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^mpe@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - nvidia,tegra20-mpe
+      - nvidia,tegra30-mpe
+      - nvidia,tegra114-mpe
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: module clock
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: mpe
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    minItems: 6
+    maxItems: 6
+
+  interconnect-names:
+    minItems: 6
+    maxItems: 6
+
+  operating-points-v2:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  power-domains:
+    items:
+      - description: phandle to the MPE power domain
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra20-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    mpe@54040000 {
+        compatible = "nvidia,tegra20-mpe";
+        reg = <0x54040000 0x00040000>;
+        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&tegra_car TEGRA20_CLK_MPE>;
+        resets = <&tegra_car 60>;
+        reset-names = "mpe";
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml
new file mode 100644
index 0000000000000..467b015e57007
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-tvo.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra TV Encoder Output
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^tvo@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - nvidia,tegra20-tvo
+      - nvidia,tegra30-tvo
+      - nvidia,tegra114-tvo
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: module clock
+
+  operating-points-v2:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  power-domains:
+    items:
+      - description: phandle to the core power domain
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra20-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    tvo@542c0000 {
+        compatible = "nvidia,tegra20-tvo";
+        reg = <0x542c0000 0x00040000>;
+        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&tegra_car TEGRA20_CLK_TVO>;
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
new file mode 100644
index 0000000000000..782a4b10150a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
@@ -0,0 +1,163 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Video Input controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^vi@[0-9a-f]+$"
+
+  compatible:
+    oneOf:
+      - const: nvidia,tegra20-vi
+      - const: nvidia,tegra30-vi
+      - const: nvidia,tegra114-vi
+      - const: nvidia,tegra124-vi
+      - items:
+          - const: nvidia,tegra132-vi
+          - const: nvidia,tegra124-vi
+      - const: nvidia,tegra210-vi
+      - const: nvidia,tegra186-vi
+      - const: nvidia,tegra194-vi
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: vi
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    minItems: 4
+    maxItems: 5
+
+  interconnect-names:
+    minItems: 4
+    maxItems: 5
+
+  operating-points-v2:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  power-domains:
+    items:
+      - description: phandle to the VENC power domain
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+  ranges:
+    maxItems: 1
+
+  avdd-dsi-csi-supply:
+    description: DSI/CSI power supply. Must supply 1.2 V.
+
+patternProperties:
+  "^csi@[0-9a-f]+$":
+    type: object
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra20-vi
+              - nvidia,tegra30-vi
+              - nvidia,tegra114-vi
+              - nvidia,tegra124-vi
+    then:
+      required:
+        - resets
+        - reset-names
+    else:
+      required:
+        - power-domains
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra20-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    vi@54080000 {
+        compatible = "nvidia,tegra20-vi";
+        reg = <0x54080000 0x00040000>;
+        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&tegra_car TEGRA20_CLK_VI>;
+        resets = <&tegra_car 100>;
+        reset-names = "vi";
+    };
+
+  - |
+    #include <dt-bindings/clock/tegra210-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    vi@54080000 {
+        compatible = "nvidia,tegra210-vi";
+        reg = <0x54080000 0x00000700>;
+        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+        assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
+        assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
+
+        clocks = <&tegra_car TEGRA210_CLK_VI>;
+        power-domains = <&pd_venc>;
+
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        ranges = <0x0 0x54080000 0x2000>;
+
+        csi@838 {
+            compatible = "nvidia,tegra210-csi";
+            reg = <0x838 0x1300>;
+            assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
+                              <&tegra_car TEGRA210_CLK_CILCD>,
+                              <&tegra_car TEGRA210_CLK_CILE>,
+                              <&tegra_car TEGRA210_CLK_CSI_TPG>;
+            assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
+                                     <&tegra_car TEGRA210_CLK_PLL_P>,
+                                     <&tegra_car TEGRA210_CLK_PLL_P>;
+            assigned-clock-rates = <102000000>,
+                                   <102000000>,
+                                   <102000000>,
+                                   <972000000>;
+
+            clocks = <&tegra_car TEGRA210_CLK_CSI>,
+                     <&tegra_car TEGRA210_CLK_CILAB>,
+                     <&tegra_car TEGRA210_CLK_CILCD>,
+                     <&tegra_car TEGRA210_CLK_CILE>,
+                     <&tegra_car TEGRA210_CLK_CSI_TPG>;
+            clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
+            power-domains = <&pd_sor>;
+        };
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml
new file mode 100644
index 0000000000000..fa07a40d10040
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra210-csi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra CSI controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^csi@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - nvidia,tegra210-csi
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: module clock
+      - description: A/B lanes clock
+      - description: C/D lanes clock
+      - description: E lane clock
+      - description: test pattern generator clock
+
+  clock-names:
+    items:
+      - const: csi
+      - const: cilab
+      - const: cilcd
+      - const: cile
+      - const: csi_tpg
+
+  power-domains:
+    maxItems: 1
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - power-domains
+
+# see nvidia,tegra20-vi.yaml for an example
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
deleted file mode 100644
index e0e886b735278..0000000000000
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
+++ /dev/null
@@ -1,59 +0,0 @@
-Device tree binding for NVIDIA Tegra DPAUX pad controller
-========================================================
-
-The Tegra Display Port Auxiliary (DPAUX) pad controller manages two pins
-which can be assigned to either the DPAUX channel or to an I2C
-controller.
-
-This document defines the device-specific binding for the DPAUX pad
-controller. Refer to pinctrl-bindings.txt in this directory for generic
-information about pin controller device tree bindings. Please refer to
-the binding document ../display/tegra/nvidia,tegra20-host1x.txt for more
-details on the DPAUX binding.
-
-Pin muxing:
------------
-
-Child nodes contain the pinmux configurations following the conventions
-from the pinctrl-bindings.txt document.
-
-Since only three configurations are possible, only three child nodes are
-needed to describe the pin mux'ing options for the DPAUX pads.
-Furthermore, given that the pad functions are only applicable to a
-single set of pads, the child nodes only need to describe the pad group
-the functions are being applied to rather than the individual pads.
-
-Required properties:
-- groups: Must be "dpaux-io"
-- function: Must be either "aux", "i2c" or "off".
-
-Example:
---------
-
-	dpaux@545c0000 {
-		...
-
-		state_dpaux_aux: pinmux-aux {
-			groups = "dpaux-io";
-			function = "aux";
-		};
-
-		state_dpaux_i2c: pinmux-i2c {
-			groups = "dpaux-io";
-			function = "i2c";
-		};
-
-		state_dpaux_off: pinmux-off {
-			groups = "dpaux-io";
-			function = "off";
-		};
-	};
-
-	...
-
-	i2c@7000d100 {
-		...
-		pinctrl-0 = <&state_dpaux_i2c>;
-		pinctrl-1 = <&state_dpaux_off>;
-		pinctrl-names = "default", "idle";
-	};
-- 
GitLab


From 7b86d50e74b9688aef6e75440ad59800ba770595 Mon Sep 17 00:00:00 2001
From: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Date: Thu, 23 Jun 2022 11:54:52 +0200
Subject: [PATCH 1675/1731] MAINTAINERS: Rectify entry for NVIDIA TEGRA DRM and
 VIDEO DRIVER

Commit fd27de58b0ad ("dt-bindings: display: tegra: Convert to json-schema")
converts nvidia,tegra20-host1x.txt to yaml, but missed to adjust its
references in MAINTAINERS.

Hence, ./scripts/get_maintainer.pl --self-test=patterns complains about a
broken reference.

Repair these file references in NVIDIA TEGRA DRM and VIDEO DRIVER.

Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 MAINTAINERS | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index a6d3bd9d2a8d0..203ec9a8cf9f6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6707,7 +6707,7 @@ L:	dri-devel@lists.freedesktop.org
 L:	linux-tegra@vger.kernel.org
 S:	Supported
 T:	git git://anongit.freedesktop.org/tegra/linux.git
-F:	Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
+F:	Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
 F:	Documentation/devicetree/bindings/gpu/host1x/
 F:	drivers/gpu/drm/tegra/
 F:	drivers/gpu/host1x/
@@ -19630,7 +19630,7 @@ M:	Sowjanya Komatineni <skomatineni@nvidia.com>
 L:	linux-media@vger.kernel.org
 L:	linux-tegra@vger.kernel.org
 S:	Maintained
-F:	Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
+F:	Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
 F:	drivers/staging/media/tegra-video/
 
 TEGRA XUSB PADCTL DRIVER
-- 
GitLab


From a382f8fee42ca10c9bfce0d2352d4153f931f5dc Mon Sep 17 00:00:00 2001
From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Wed, 6 Jul 2022 12:20:59 -0700
Subject: [PATCH 1676/1731] signal handling: don't use BUG_ON() for debugging

These are indeed "should not happen" situations, but it turns out recent
changes made the 'task_is_stopped_or_trace()' case trigger (fix for that
exists, is pending more testing), and the BUG_ON() makes it
unnecessarily hard to actually debug for no good reason.

It's been that way for a long time, but let's make it clear: BUG_ON() is
not good for debugging, and should never be used in situations where you
could just say "this shouldn't happen, but we can continue".

Use WARN_ON_ONCE() instead to make sure it gets logged, and then just
continue running.  Instead of making the system basically unusuable
because you crashed the machine while potentially holding some very core
locks (eg this function is commonly called while holding 'tasklist_lock'
for writing).

Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
---
 kernel/signal.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/kernel/signal.c b/kernel/signal.c
index edb1dc9b00dc8..6f86fda5e432a 100644
--- a/kernel/signal.c
+++ b/kernel/signal.c
@@ -2029,12 +2029,12 @@ bool do_notify_parent(struct task_struct *tsk, int sig)
 	bool autoreap = false;
 	u64 utime, stime;
 
-	BUG_ON(sig == -1);
+	WARN_ON_ONCE(sig == -1);
 
- 	/* do_notify_parent_cldstop should have been called instead.  */
- 	BUG_ON(task_is_stopped_or_traced(tsk));
+	/* do_notify_parent_cldstop should have been called instead.  */
+	WARN_ON_ONCE(task_is_stopped_or_traced(tsk));
 
-	BUG_ON(!tsk->ptrace &&
+	WARN_ON_ONCE(!tsk->ptrace &&
 	       (tsk->group_leader != tsk || !thread_group_empty(tsk)));
 
 	/* Wake up all pidfd waiters */
-- 
GitLab


From 92ef86ab513593c6329d04146e61f9a670e72fc5 Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Thu, 7 Jul 2022 09:20:37 -0700
Subject: [PATCH 1677/1731] drm/msm/mdp5: Fix global state lock backoff

We need to grab the lock after the early return for !hwpipe case.
Otherwise, we could have hit contention yet still returned 0.

Fixes an issue that the new CONFIG_DRM_DEBUG_MODESET_LOCK stuff flagged
in CI:

   WARNING: CPU: 0 PID: 282 at drivers/gpu/drm/drm_modeset_lock.c:296 drm_modeset_lock+0xf8/0x154
   Modules linked in:
   CPU: 0 PID: 282 Comm: kms_cursor_lega Tainted: G        W         5.19.0-rc2-15930-g875cc8bc536a #1
   Hardware name: Qualcomm Technologies, Inc. DB820c (DT)
   pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
   pc : drm_modeset_lock+0xf8/0x154
   lr : drm_atomic_get_private_obj_state+0x84/0x170
   sp : ffff80000cfab6a0
   x29: ffff80000cfab6a0 x28: 0000000000000000 x27: ffff000083bc4d00
   x26: 0000000000000038 x25: 0000000000000000 x24: ffff80000957ca58
   x23: 0000000000000000 x22: ffff000081ace080 x21: 0000000000000001
   x20: ffff000081acec18 x19: ffff80000cfabb80 x18: 0000000000000038
   x17: 0000000000000000 x16: 0000000000000000 x15: fffffffffffea0d0
   x14: 0000000000000000 x13: 284e4f5f4e524157 x12: 5f534b434f4c5f47
   x11: ffff80000a386aa8 x10: 0000000000000029 x9 : ffff80000cfab610
   x8 : 0000000000000029 x7 : 0000000000000014 x6 : 0000000000000000
   x5 : 0000000000000001 x4 : ffff8000081ad904 x3 : 0000000000000029
   x2 : ffff0000801db4c0 x1 : ffff80000cfabb80 x0 : ffff000081aceb58
   Call trace:
    drm_modeset_lock+0xf8/0x154
    drm_atomic_get_private_obj_state+0x84/0x170
    mdp5_get_global_state+0x54/0x6c
    mdp5_pipe_release+0x2c/0xd4
    mdp5_plane_atomic_check+0x2ec/0x414
    drm_atomic_helper_check_planes+0xd8/0x210
    drm_atomic_helper_check+0x54/0xb0
    ...
   ---[ end trace 0000000000000000 ]---
   drm_modeset_lock attempting to lock a contended lock without backoff:
      drm_modeset_lock+0x148/0x154
      mdp5_get_global_state+0x30/0x6c
      mdp5_pipe_release+0x2c/0xd4
      mdp5_plane_atomic_check+0x290/0x414
      drm_atomic_helper_check_planes+0xd8/0x210
      drm_atomic_helper_check+0x54/0xb0
      drm_atomic_check_only+0x4b0/0x8f4
      drm_atomic_commit+0x68/0xe0

Fixes: d59be579fa93 ("drm/msm/mdp5: Return error code in mdp5_pipe_release when deadlock is detected")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/492701/
Link: https://lore.kernel.org/r/20220707162040.1594855-1-robdclark@gmail.com
---
 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c
index a4f5cb90f3e80..e4b8a789835a4 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c
@@ -123,12 +123,13 @@ int mdp5_pipe_release(struct drm_atomic_state *s, struct mdp5_hw_pipe *hwpipe)
 {
 	struct msm_drm_private *priv = s->dev->dev_private;
 	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
-	struct mdp5_global_state *state = mdp5_get_global_state(s);
+	struct mdp5_global_state *state;
 	struct mdp5_hw_pipe_state *new_state;
 
 	if (!hwpipe)
 		return 0;
 
+	state = mdp5_get_global_state(s);
 	if (IS_ERR(state))
 		return PTR_ERR(state);
 
-- 
GitLab


From c8934e4e348915caac54085c01fd9d04fa16134a Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Fri, 1 Jul 2022 15:31:26 +0200
Subject: [PATCH 1678/1731] PM / devfreq: exynos-bus: Fix NULL pointer
 dereference

Fix exynos-bus NULL pointer dereference by correctly using the local
generated freq_table to output the debug values instead of using the
profile freq_table that is not used in the driver.

Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Fixes: b5d281f6c16d ("PM / devfreq: Rework freq_table to be local to devfreq struct")
Cc: stable@vger.kernel.org
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 drivers/devfreq/exynos-bus.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/devfreq/exynos-bus.c b/drivers/devfreq/exynos-bus.c
index e689101abc930..f7dcc44f9414c 100644
--- a/drivers/devfreq/exynos-bus.c
+++ b/drivers/devfreq/exynos-bus.c
@@ -447,9 +447,9 @@ static int exynos_bus_probe(struct platform_device *pdev)
 		}
 	}
 
-	max_state = bus->devfreq->profile->max_state;
-	min_freq = (bus->devfreq->profile->freq_table[0] / 1000);
-	max_freq = (bus->devfreq->profile->freq_table[max_state - 1] / 1000);
+	max_state = bus->devfreq->max_state;
+	min_freq = (bus->devfreq->freq_table[0] / 1000);
+	max_freq = (bus->devfreq->freq_table[max_state - 1] / 1000);
 	pr_info("exynos-bus: new bus device registered: %s (%6ld KHz ~ %6ld KHz)\n",
 			dev_name(dev), min_freq, max_freq);
 
-- 
GitLab


From 3501f0c663063513ad604fb1b3f06af637d3396d Mon Sep 17 00:00:00 2001
From: Satish Nagireddy <satish.nagireddy@getcruise.com>
Date: Tue, 28 Jun 2022 12:12:16 -0700
Subject: [PATCH 1679/1731] i2c: cadence: Unregister the clk notifier in error
 path

This patch ensures that the clock notifier is unregistered
when driver probe is returning error.

Fixes: df8eb5691c48 ("i2c: Add driver for Cadence I2C controller")
Signed-off-by: Satish Nagireddy <satish.nagireddy@getcruise.com>
Tested-by: Lars-Peter Clausen <lars@metafoo.de>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
---
 drivers/i2c/busses/i2c-cadence.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cadence.c
index b4c1ad19cdaec..3d6f8ee355bfc 100644
--- a/drivers/i2c/busses/i2c-cadence.c
+++ b/drivers/i2c/busses/i2c-cadence.c
@@ -1338,6 +1338,7 @@ static int cdns_i2c_probe(struct platform_device *pdev)
 	return 0;
 
 err_clk_dis:
+	clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
 	clk_disable_unprepare(id->clk);
 	pm_runtime_disable(&pdev->dev);
 	pm_runtime_set_suspended(&pdev->dev);
-- 
GitLab


From bdb2c48e4b38e6dbe82533b437468999ba3ae498 Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Thu, 7 Jul 2022 15:00:38 +0100
Subject: [PATCH 1680/1731] io_uring: explicit sqe padding for ioctl commands

32 bit sqe->cmd_op is an union with 64 bit values. It's always a good
idea to do padding explicitly. Also zero check it in prep, so it can be
used in the future if needed without compatibility concerns.

Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
Link: https://lore.kernel.org/r/e6b95a05e970af79000435166185e85b196b2ba2.1657202417.git.asml.silence@gmail.com
[axboe: turn bitwise OR into logical variant]
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c                 | 2 +-
 include/uapi/linux/io_uring.h | 5 ++++-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index 0d491ad15b66a..cddc0e8490af8 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -5066,7 +5066,7 @@ static int io_uring_cmd_prep(struct io_kiocb *req,
 {
 	struct io_uring_cmd *ioucmd = &req->uring_cmd;
 
-	if (sqe->rw_flags)
+	if (sqe->rw_flags || sqe->__pad1)
 		return -EINVAL;
 	ioucmd->cmd = sqe->cmd;
 	ioucmd->cmd_op = READ_ONCE(sqe->cmd_op);
diff --git a/include/uapi/linux/io_uring.h b/include/uapi/linux/io_uring.h
index f10b59d6693e3..0ad3da28d2fce 100644
--- a/include/uapi/linux/io_uring.h
+++ b/include/uapi/linux/io_uring.h
@@ -22,7 +22,10 @@ struct io_uring_sqe {
 	union {
 		__u64	off;	/* offset into file */
 		__u64	addr2;
-		__u32	cmd_op;
+		struct {
+			__u32	cmd_op;
+			__u32	__pad1;
+		};
 	};
 	union {
 		__u64	addr;	/* pointer to buffer or iovecs */
-- 
GitLab


From c51b8f85c4157eb91c2f4ab34b0c52fea642e77c Mon Sep 17 00:00:00 2001
From: Joerg Roedel <jroedel@suse.de>
Date: Wed, 6 Jul 2022 12:33:31 +0200
Subject: [PATCH 1681/1731] MAINTAINERS: Remove
 iommu@lists.linux-foundation.org

The IOMMU mailing list has moved to iommu@lists.linux.dev
and the old list should bounce by now. Remove it from the
MAINTAINERS file.

Cc: stable@vger.kernel.org
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Link: https://lore.kernel.org/r/20220706103331.10215-1-joro@8bytes.org
---
 MAINTAINERS | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 66bffb24a348a..ead381fdfc5a4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -426,7 +426,6 @@ F:	drivers/acpi/*thermal*
 ACPI VIOT DRIVER
 M:	Jean-Philippe Brucker <jean-philippe@linaro.org>
 L:	linux-acpi@vger.kernel.org
-L:	iommu@lists.linux-foundation.org
 L:	iommu@lists.linux.dev
 S:	Maintained
 F:	drivers/acpi/viot.c
@@ -960,7 +959,6 @@ F:	drivers/video/fbdev/geode/
 AMD IOMMU (AMD-VI)
 M:	Joerg Roedel <joro@8bytes.org>
 R:	Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
-L:	iommu@lists.linux-foundation.org
 L:	iommu@lists.linux.dev
 S:	Maintained
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
@@ -5979,7 +5977,6 @@ DMA MAPPING HELPERS
 M:	Christoph Hellwig <hch@lst.de>
 M:	Marek Szyprowski <m.szyprowski@samsung.com>
 R:	Robin Murphy <robin.murphy@arm.com>
-L:	iommu@lists.linux-foundation.org
 L:	iommu@lists.linux.dev
 S:	Supported
 W:	http://git.infradead.org/users/hch/dma-mapping.git
@@ -5992,7 +5989,6 @@ F:	kernel/dma/
 
 DMA MAPPING BENCHMARK
 M:	Xiang Chen <chenxiang66@hisilicon.com>
-L:	iommu@lists.linux-foundation.org
 L:	iommu@lists.linux.dev
 F:	kernel/dma/map_benchmark.c
 F:	tools/testing/selftests/dma/
@@ -7577,7 +7573,6 @@ F:	drivers/gpu/drm/exynos/exynos_dp*
 
 EXYNOS SYSMMU (IOMMU) driver
 M:	Marek Szyprowski <m.szyprowski@samsung.com>
-L:	iommu@lists.linux-foundation.org
 L:	iommu@lists.linux.dev
 S:	Maintained
 F:	drivers/iommu/exynos-iommu.c
@@ -9999,7 +9994,6 @@ F:	drivers/hid/intel-ish-hid/
 INTEL IOMMU (VT-d)
 M:	David Woodhouse <dwmw2@infradead.org>
 M:	Lu Baolu <baolu.lu@linux.intel.com>
-L:	iommu@lists.linux-foundation.org
 L:	iommu@lists.linux.dev
 S:	Supported
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
@@ -10379,7 +10373,6 @@ F:	include/linux/iomap.h
 IOMMU DRIVERS
 M:	Joerg Roedel <joro@8bytes.org>
 M:	Will Deacon <will@kernel.org>
-L:	iommu@lists.linux-foundation.org
 L:	iommu@lists.linux.dev
 S:	Maintained
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
@@ -12539,7 +12532,6 @@ F:	drivers/i2c/busses/i2c-mt65xx.c
 
 MEDIATEK IOMMU DRIVER
 M:	Yong Wu <yong.wu@mediatek.com>
-L:	iommu@lists.linux-foundation.org
 L:	iommu@lists.linux.dev
 L:	linux-mediatek@lists.infradead.org (moderated for non-subscribers)
 S:	Supported
@@ -16591,7 +16583,6 @@ F:	drivers/i2c/busses/i2c-qcom-cci.c
 
 QUALCOMM IOMMU
 M:	Rob Clark <robdclark@gmail.com>
-L:	iommu@lists.linux-foundation.org
 L:	iommu@lists.linux.dev
 L:	linux-arm-msm@vger.kernel.org
 S:	Maintained
@@ -19217,7 +19208,6 @@ F:	arch/x86/boot/video*
 
 SWIOTLB SUBSYSTEM
 M:	Christoph Hellwig <hch@infradead.org>
-L:	iommu@lists.linux-foundation.org
 L:	iommu@lists.linux.dev
 S:	Supported
 W:	http://git.infradead.org/users/hch/dma-mapping.git
@@ -21893,7 +21883,6 @@ XEN SWIOTLB SUBSYSTEM
 M:	Juergen Gross <jgross@suse.com>
 M:	Stefano Stabellini <sstabellini@kernel.org>
 L:	xen-devel@lists.xenproject.org (moderated for non-subscribers)
-L:	iommu@lists.linux-foundation.org
 L:	iommu@lists.linux.dev
 S:	Supported
 F:	arch/x86/xen/*swiotlb*
-- 
GitLab


From ea1a6270ff4fa4460914cf788b0560271a577615 Mon Sep 17 00:00:00 2001
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: Mon, 27 Jun 2022 17:19:47 +0300
Subject: [PATCH 1682/1731] dt-bindings: host1x: Add iommu-map property

Add schema information for specifying context stream IDs. This uses
the standard iommu-map property.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../bindings/display/tegra/nvidia,tegra20-host1x.yaml        | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
index 5b3df384f1a07..fcfda5d7b00f1 100644
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
@@ -144,6 +144,11 @@ allOf:
         reset-names:
           maxItems: 1
 
+        iommu-map:
+          description: Specification of stream IDs available for memory context device
+            use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
+            usable stream IDs.
+
       required:
         - reg-names
 
-- 
GitLab


From 5c5a6ff72e193302b21fd4c2afc6bd8cc26f68e2 Mon Sep 17 00:00:00 2001
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: Mon, 27 Jun 2022 17:19:55 +0300
Subject: [PATCH 1683/1731] dt-bindings: Add bindings for Tegra234 Host1x and
 VIC

Update VIC and Host1x bindings for changes in Tegra234.

Namely,
- New compatible strings
- Sharded syncpoint interrupts
- Optional reset.

Also, fix the order of descriptions for VM/hypervisor
register apertures -- while the reg-names specification
was correct, the descriptions for these were switched.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../display/tegra/nvidia,tegra124-vic.yaml    |   1 +
 .../display/tegra/nvidia,tegra20-host1x.yaml  | 106 +++++++++++++++---
 2 files changed, 93 insertions(+), 14 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml
index 37bb5ddc1963e..7200095ef19e3 100644
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml
@@ -21,6 +21,7 @@ properties:
           - nvidia,tegra210-vic
           - nvidia,tegra186-vic
           - nvidia,tegra194-vic
+          - nvidia,tegra234-vic
 
       - items:
           - const: nvidia,tegra132-vic
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
index fcfda5d7b00f1..2a6e54f74127e 100644
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
@@ -24,6 +24,7 @@ properties:
           - nvidia,tegra210-host1x
           - nvidia,tegra186-host1x
           - nvidia,tegra194-host1x
+          - nvidia,tegra234-host1x
 
       - items:
           - const: nvidia,tegra132-host1x
@@ -31,23 +32,19 @@ properties:
 
   reg:
     minItems: 1
-    maxItems: 2
+    maxItems: 3
 
   reg-names:
     minItems: 1
-    maxItems: 2
+    maxItems: 3
 
   interrupts:
-    items:
-      - description: host1x syncpoint interrupt
-      - description: host1x general interrupt
     minItems: 1
+    maxItems: 9
 
   interrupt-names:
-    items:
-      - const: syncpt
-      - const: host1x
     minItems: 1
+    maxItems: 9
 
   '#address-cells':
     description: The number of cells used to represent physical base addresses
@@ -110,13 +107,35 @@ required:
   - reg
   - clocks
   - clock-names
-  - resets
-  - reset-names
 
 unevaluatedProperties:
   type: object
 
 allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra20-host1x
+              - nvidia,tegra30-host1x
+              - nvidia,tegra114-host1x
+              - nvidia,tegra124-host1x
+              - nvidia,tegra210-host1x
+    then:
+      properties:
+        interrupts:
+          items:
+            - description: host1x syncpoint interrupt
+            - description: host1x general interrupt
+
+        interrupt-names:
+          items:
+            - const: syncpt
+            - const: host1x
+      required:
+        - resets
+        - reset-names
   - if:
       properties:
         compatible:
@@ -133,10 +152,8 @@ allOf:
 
         reg:
           items:
-            - description: physical base address and length of the register
-                region assigned to the VM
-            - description: physical base address and length of the register
-                region used by the hypervisor
+            - description: region used by the hypervisor
+            - description: region assigned to the virtual machine
 
         resets:
           maxItems: 1
@@ -144,6 +161,67 @@ allOf:
         reset-names:
           maxItems: 1
 
+        interrupts:
+          items:
+            - description: host1x syncpoint interrupt
+            - description: host1x general interrupt
+
+        interrupt-names:
+          items:
+            - const: syncpt
+            - const: host1x
+
+        iommu-map:
+          description: Specification of stream IDs available for memory context device
+            use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
+            usable stream IDs.
+
+      required:
+        - reg-names
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra234-host1x
+    then:
+      properties:
+        reg-names:
+          items:
+            - const: common
+            - const: hypervisor
+            - const: vm
+
+        reg:
+          items:
+            - description: region used by host1x server
+            - description: region used by the hypervisor
+            - description: region assigned to the virtual machine
+
+        interrupts:
+          items:
+            - description: host1x syncpoint interrupt 0
+            - description: host1x syncpoint interrupt 1
+            - description: host1x syncpoint interrupt 2
+            - description: host1x syncpoint interrupt 3
+            - description: host1x syncpoint interrupt 4
+            - description: host1x syncpoint interrupt 5
+            - description: host1x syncpoint interrupt 6
+            - description: host1x syncpoint interrupt 7
+            - description: host1x general interrupt
+
+        interrupt-names:
+          items:
+            - const: syncpt0
+            - const: syncpt1
+            - const: syncpt2
+            - const: syncpt3
+            - const: syncpt4
+            - const: syncpt5
+            - const: syncpt6
+            - const: syncpt7
+            - const: host1x
+
         iommu-map:
           description: Specification of stream IDs available for memory context device
             use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
-- 
GitLab


From a72d4b182f4e092573035fe6fa9402a14111fd64 Mon Sep 17 00:00:00 2001
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: Mon, 27 Jun 2022 17:19:56 +0300
Subject: [PATCH 1684/1731] dt-bindings: host1x: Fix bracketing in example

The bracketing for the interrupts property in the device tree
example is incorrect. Fix it.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../bindings/display/tegra/nvidia,tegra20-host1x.yaml         | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
index 2a6e54f74127e..913ca104c871d 100644
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
@@ -239,8 +239,8 @@ examples:
     host1x@50000000 {
         compatible = "nvidia,tegra20-host1x";
         reg = <0x50000000 0x00024000>;
-        interrupts = <0 65 0x04   /* mpcore syncpt */
-                      0 67 0x04>; /* mpcore general */
+        interrupts = <0 65 0x04>, /* mpcore syncpt */
+                     <0 67 0x04>; /* mpcore general */
         interrupt-names = "syncpt", "host1x";
         clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
         clock-names = "host1x";
-- 
GitLab


From 8aa5bcb61612060429223d1fbb7a1c30a579fc1f Mon Sep 17 00:00:00 2001
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: Mon, 27 Jun 2022 17:19:48 +0300
Subject: [PATCH 1685/1731] gpu: host1x: Add context device management code

Add code to register context devices from device tree, allocate them
out and manage their refcounts.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/host1x/Makefile  |   3 +
 drivers/gpu/host1x/context.c | 160 +++++++++++++++++++++++++++++++++++
 drivers/gpu/host1x/context.h |  38 +++++++++
 drivers/gpu/host1x/dev.c     |  12 ++-
 drivers/gpu/host1x/dev.h     |   2 +
 include/linux/host1x.h       |  34 ++++++++
 6 files changed, 248 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/host1x/context.c
 create mode 100644 drivers/gpu/host1x/context.h

diff --git a/drivers/gpu/host1x/Makefile b/drivers/gpu/host1x/Makefile
index c891a3e338441..28f7aaedce0ff 100644
--- a/drivers/gpu/host1x/Makefile
+++ b/drivers/gpu/host1x/Makefile
@@ -17,5 +17,8 @@ host1x-y = \
 	hw/host1x06.o \
 	hw/host1x07.o
 
+host1x-$(CONFIG_IOMMU_API) += \
+	context.o
+
 obj-$(CONFIG_TEGRA_HOST1X) += host1x.o
 obj-$(CONFIG_TEGRA_HOST1X_CONTEXT_BUS) += context_bus.o
diff --git a/drivers/gpu/host1x/context.c b/drivers/gpu/host1x/context.c
new file mode 100644
index 0000000000000..b08cf11f9a661
--- /dev/null
+++ b/drivers/gpu/host1x/context.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, NVIDIA Corporation.
+ */
+
+#include <linux/device.h>
+#include <linux/kref.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pid.h>
+#include <linux/slab.h>
+
+#include "context.h"
+#include "dev.h"
+
+int host1x_memory_context_list_init(struct host1x *host1x)
+{
+	struct host1x_memory_context_list *cdl = &host1x->context_list;
+	struct device_node *node = host1x->dev->of_node;
+	struct host1x_memory_context *ctx;
+	unsigned int i;
+	int err;
+
+	cdl->devs = NULL;
+	cdl->len = 0;
+	mutex_init(&cdl->lock);
+
+	err = of_property_count_u32_elems(node, "iommu-map");
+	if (err < 0)
+		return 0;
+
+	cdl->devs = kcalloc(err, sizeof(*cdl->devs), GFP_KERNEL);
+	if (!cdl->devs)
+		return -ENOMEM;
+	cdl->len = err / 4;
+
+	for (i = 0; i < cdl->len; i++) {
+		struct iommu_fwspec *fwspec;
+
+		ctx = &cdl->devs[i];
+
+		ctx->host = host1x;
+
+		device_initialize(&ctx->dev);
+
+		/*
+		 * Due to an issue with T194 NVENC, only 38 bits can be used.
+		 * Anyway, 256GiB of IOVA ought to be enough for anyone.
+		 */
+		ctx->dma_mask = DMA_BIT_MASK(38);
+		ctx->dev.dma_mask = &ctx->dma_mask;
+		ctx->dev.coherent_dma_mask = ctx->dma_mask;
+		dev_set_name(&ctx->dev, "host1x-ctx.%d", i);
+		ctx->dev.bus = &host1x_context_device_bus_type;
+		ctx->dev.parent = host1x->dev;
+
+		dma_set_max_seg_size(&ctx->dev, UINT_MAX);
+
+		err = device_add(&ctx->dev);
+		if (err) {
+			dev_err(host1x->dev, "could not add context device %d: %d\n", i, err);
+			goto del_devices;
+		}
+
+		err = of_dma_configure_id(&ctx->dev, node, true, &i);
+		if (err) {
+			dev_err(host1x->dev, "IOMMU configuration failed for context device %d: %d\n",
+				i, err);
+			device_del(&ctx->dev);
+			goto del_devices;
+		}
+
+		fwspec = dev_iommu_fwspec_get(&ctx->dev);
+		if (!fwspec || !device_iommu_mapped(&ctx->dev)) {
+			dev_err(host1x->dev, "Context device %d has no IOMMU!\n", i);
+			device_del(&ctx->dev);
+			goto del_devices;
+		}
+
+		ctx->stream_id = fwspec->ids[0] & 0xffff;
+	}
+
+	return 0;
+
+del_devices:
+	while (i--)
+		device_del(&cdl->devs[i].dev);
+
+	kfree(cdl->devs);
+	cdl->len = 0;
+
+	return err;
+}
+
+void host1x_memory_context_list_free(struct host1x_memory_context_list *cdl)
+{
+	unsigned int i;
+
+	for (i = 0; i < cdl->len; i++)
+		device_del(&cdl->devs[i].dev);
+
+	kfree(cdl->devs);
+	cdl->len = 0;
+}
+
+struct host1x_memory_context *host1x_memory_context_alloc(struct host1x *host1x,
+							  struct pid *pid)
+{
+	struct host1x_memory_context_list *cdl = &host1x->context_list;
+	struct host1x_memory_context *free = NULL;
+	int i;
+
+	if (!cdl->len)
+		return ERR_PTR(-EOPNOTSUPP);
+
+	mutex_lock(&cdl->lock);
+
+	for (i = 0; i < cdl->len; i++) {
+		struct host1x_memory_context *cd = &cdl->devs[i];
+
+		if (cd->owner == pid) {
+			refcount_inc(&cd->ref);
+			mutex_unlock(&cdl->lock);
+			return cd;
+		} else if (!cd->owner && !free) {
+			free = cd;
+		}
+	}
+
+	if (!free) {
+		mutex_unlock(&cdl->lock);
+		return ERR_PTR(-EBUSY);
+	}
+
+	refcount_set(&free->ref, 1);
+	free->owner = get_pid(pid);
+
+	mutex_unlock(&cdl->lock);
+
+	return free;
+}
+EXPORT_SYMBOL_GPL(host1x_memory_context_alloc);
+
+void host1x_memory_context_get(struct host1x_memory_context *cd)
+{
+	refcount_inc(&cd->ref);
+}
+EXPORT_SYMBOL_GPL(host1x_memory_context_get);
+
+void host1x_memory_context_put(struct host1x_memory_context *cd)
+{
+	struct host1x_memory_context_list *cdl = &cd->host->context_list;
+
+	if (refcount_dec_and_mutex_lock(&cd->ref, &cdl->lock)) {
+		put_pid(cd->owner);
+		cd->owner = NULL;
+		mutex_unlock(&cdl->lock);
+	}
+}
+EXPORT_SYMBOL_GPL(host1x_memory_context_put);
diff --git a/drivers/gpu/host1x/context.h b/drivers/gpu/host1x/context.h
new file mode 100644
index 0000000000000..3e03bc1d3bac3
--- /dev/null
+++ b/drivers/gpu/host1x/context.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Host1x context devices
+ *
+ * Copyright (c) 2020, NVIDIA Corporation.
+ */
+
+#ifndef __HOST1X_CONTEXT_H
+#define __HOST1X_CONTEXT_H
+
+#include <linux/mutex.h>
+#include <linux/refcount.h>
+
+struct host1x;
+
+extern struct bus_type host1x_context_device_bus_type;
+
+struct host1x_memory_context_list {
+	struct mutex lock;
+	struct host1x_memory_context *devs;
+	unsigned int len;
+};
+
+#ifdef CONFIG_IOMMU_API
+int host1x_memory_context_list_init(struct host1x *host1x);
+void host1x_memory_context_list_free(struct host1x_memory_context_list *cdl);
+#else
+static inline int host1x_memory_context_list_init(struct host1x *host1x)
+{
+	return 0;
+}
+
+static inline void host1x_memory_context_list_free(struct host1x_memory_context_list *cdl)
+{
+}
+#endif
+
+#endif
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 80c685ab3e30d..89cc79a48eab8 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -28,6 +28,7 @@
 
 #include "bus.h"
 #include "channel.h"
+#include "context.h"
 #include "debug.h"
 #include "dev.h"
 #include "intr.h"
@@ -503,10 +504,16 @@ static int host1x_probe(struct platform_device *pdev)
 		goto iommu_exit;
 	}
 
+	err = host1x_memory_context_list_init(host);
+	if (err) {
+		dev_err(&pdev->dev, "failed to initialize context list\n");
+		goto free_channels;
+	}
+
 	err = host1x_syncpt_init(host);
 	if (err) {
 		dev_err(&pdev->dev, "failed to initialize syncpts\n");
-		goto free_channels;
+		goto free_contexts;
 	}
 
 	err = host1x_intr_init(host, syncpt_irq);
@@ -550,6 +557,8 @@ pm_disable:
 	host1x_intr_deinit(host);
 deinit_syncpt:
 	host1x_syncpt_deinit(host);
+free_contexts:
+	host1x_memory_context_list_free(&host->context_list);
 free_channels:
 	host1x_channel_list_free(&host->channel_list);
 iommu_exit:
@@ -571,6 +580,7 @@ static int host1x_remove(struct platform_device *pdev)
 
 	host1x_intr_deinit(host);
 	host1x_syncpt_deinit(host);
+	host1x_memory_context_list_free(&host->context_list);
 	host1x_channel_list_free(&host->channel_list);
 	host1x_iommu_exit(host);
 	host1x_bo_cache_destroy(&host->cache);
diff --git a/drivers/gpu/host1x/dev.h b/drivers/gpu/host1x/dev.h
index ca4b082f0cd49..7552a45545347 100644
--- a/drivers/gpu/host1x/dev.h
+++ b/drivers/gpu/host1x/dev.h
@@ -14,6 +14,7 @@
 
 #include "cdma.h"
 #include "channel.h"
+#include "context.h"
 #include "intr.h"
 #include "job.h"
 #include "syncpt.h"
@@ -141,6 +142,7 @@ struct host1x {
 	struct mutex syncpt_mutex;
 
 	struct host1x_channel_list channel_list;
+	struct host1x_memory_context_list context_list;
 
 	struct dentry *debugfs;
 
diff --git a/include/linux/host1x.h b/include/linux/host1x.h
index c0bf4e581fe9d..32a82da13fedc 100644
--- a/include/linux/host1x.h
+++ b/include/linux/host1x.h
@@ -446,4 +446,38 @@ int tegra_mipi_disable(struct tegra_mipi_device *device);
 int tegra_mipi_start_calibration(struct tegra_mipi_device *device);
 int tegra_mipi_finish_calibration(struct tegra_mipi_device *device);
 
+/* host1x memory contexts */
+
+struct host1x_memory_context {
+	struct host1x *host;
+
+	refcount_t ref;
+	struct pid *owner;
+
+	struct device dev;
+	u64 dma_mask;
+	u32 stream_id;
+};
+
+#ifdef CONFIG_IOMMU_API
+struct host1x_memory_context *host1x_memory_context_alloc(struct host1x *host1x,
+							  struct pid *pid);
+void host1x_memory_context_get(struct host1x_memory_context *cd);
+void host1x_memory_context_put(struct host1x_memory_context *cd);
+#else
+static inline struct host1x_memory_context *host1x_memory_context_alloc(struct host1x *host1x,
+									struct pid *pid)
+{
+	return NULL;
+}
+
+static inline void host1x_memory_context_get(struct host1x_memory_context *cd)
+{
+}
+
+static inline void host1x_memory_context_put(struct host1x_memory_context *cd)
+{
+}
+#endif
+
 #endif
-- 
GitLab


From 2486254781eab6f6119fabea78f11386c54460d2 Mon Sep 17 00:00:00 2001
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: Mon, 27 Jun 2022 17:19:49 +0300
Subject: [PATCH 1686/1731] gpu: host1x: Program context stream ID on
 submission

Add code to do stream ID switching at the beginning of a job. The
stream ID is switched to the stream ID specified by the context
passed in the job structure.

Before switching the stream ID, an OP_DONE wait is done on the
channel's engine to ensure that there is no residual ongoing
work that might do DMA using the new stream ID.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/host1x/hw/channel_hw.c        | 52 +++++++++++++++++++++--
 drivers/gpu/host1x/hw/host1x06_hardware.h | 10 +++++
 drivers/gpu/host1x/hw/host1x07_hardware.h | 10 +++++
 include/linux/host1x.h                    |  8 ++++
 4 files changed, 76 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw/channel_hw.c
index 6b40e9af1e886..f84caf06621ab 100644
--- a/drivers/gpu/host1x/hw/channel_hw.c
+++ b/drivers/gpu/host1x/hw/channel_hw.c
@@ -180,6 +180,45 @@ static void host1x_enable_gather_filter(struct host1x_channel *ch)
 #endif
 }
 
+static void host1x_channel_program_engine_streamid(struct host1x_job *job)
+{
+#if HOST1X_HW >= 6
+	u32 fence;
+
+	if (!job->memory_context)
+		return;
+
+	fence = host1x_syncpt_incr_max(job->syncpt, 1);
+
+	/* First, increment a syncpoint on OP_DONE condition.. */
+
+	host1x_cdma_push(&job->channel->cdma,
+		host1x_opcode_nonincr(HOST1X_UCLASS_INCR_SYNCPT, 1),
+		HOST1X_UCLASS_INCR_SYNCPT_INDX_F(job->syncpt->id) |
+			HOST1X_UCLASS_INCR_SYNCPT_COND_F(1));
+
+	/* Wait for syncpoint to increment */
+
+	host1x_cdma_push(&job->channel->cdma,
+		host1x_opcode_setclass(HOST1X_CLASS_HOST1X,
+			host1x_uclass_wait_syncpt_r(), 1),
+		host1x_class_host_wait_syncpt(job->syncpt->id, fence));
+
+	/*
+	 * Now that we know the engine is idle, return to class and
+	 * change stream ID.
+	 */
+
+	host1x_cdma_push(&job->channel->cdma,
+		host1x_opcode_setclass(job->class, 0, 0),
+		HOST1X_OPCODE_NOP);
+
+	host1x_cdma_push(&job->channel->cdma,
+		host1x_opcode_setpayload(job->memory_context->stream_id),
+		host1x_opcode_setstreamid(job->engine_streamid_offset / 4));
+#endif
+}
+
 static int channel_submit(struct host1x_job *job)
 {
 	struct host1x_channel *ch = job->channel;
@@ -236,18 +275,23 @@ static int channel_submit(struct host1x_job *job)
 	if (sp->base)
 		synchronize_syncpt_base(job);
 
-	syncval = host1x_syncpt_incr_max(sp, user_syncpt_incrs);
-
 	host1x_hw_syncpt_assign_to_channel(host, sp, ch);
 
-	job->syncpt_end = syncval;
-
 	/* add a setclass for modules that require it */
 	if (job->class)
 		host1x_cdma_push(&ch->cdma,
 				 host1x_opcode_setclass(job->class, 0, 0),
 				 HOST1X_OPCODE_NOP);
 
+	/*
+	 * Ensure engine DMA is idle and set new stream ID. May increment
+	 * syncpt max.
+	 */
+	host1x_channel_program_engine_streamid(job);
+
+	syncval = host1x_syncpt_incr_max(sp, user_syncpt_incrs);
+	job->syncpt_end = syncval;
+
 	submit_gathers(job, syncval - user_syncpt_incrs);
 
 	/* end CDMA submit & stash pinned hMems into sync queue */
diff --git a/drivers/gpu/host1x/hw/host1x06_hardware.h b/drivers/gpu/host1x/hw/host1x06_hardware.h
index 01a142a09800c..5d515745eee7e 100644
--- a/drivers/gpu/host1x/hw/host1x06_hardware.h
+++ b/drivers/gpu/host1x/hw/host1x06_hardware.h
@@ -127,6 +127,16 @@ static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
 	return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
 }
 
+static inline u32 host1x_opcode_setstreamid(unsigned streamid)
+{
+	return (7 << 28) | streamid;
+}
+
+static inline u32 host1x_opcode_setpayload(unsigned payload)
+{
+	return (9 << 28) | payload;
+}
+
 static inline u32 host1x_opcode_gather_wide(unsigned count)
 {
 	return (12 << 28) | count;
diff --git a/drivers/gpu/host1x/hw/host1x07_hardware.h b/drivers/gpu/host1x/hw/host1x07_hardware.h
index e6582172ebfdb..82c0cc9bb0b5f 100644
--- a/drivers/gpu/host1x/hw/host1x07_hardware.h
+++ b/drivers/gpu/host1x/hw/host1x07_hardware.h
@@ -127,6 +127,16 @@ static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
 	return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
 }
 
+static inline u32 host1x_opcode_setstreamid(unsigned streamid)
+{
+	return (7 << 28) | streamid;
+}
+
+static inline u32 host1x_opcode_setpayload(unsigned payload)
+{
+	return (9 << 28) | payload;
+}
+
 static inline u32 host1x_opcode_gather_wide(unsigned count)
 {
 	return (12 << 28) | count;
diff --git a/include/linux/host1x.h b/include/linux/host1x.h
index 32a82da13fedc..cb2100d9b0ffe 100644
--- a/include/linux/host1x.h
+++ b/include/linux/host1x.h
@@ -327,6 +327,14 @@ struct host1x_job {
 
 	/* Whether host1x-side firewall should be ran for this job or not */
 	bool enable_firewall;
+
+	/* Options for configuring engine data stream ID */
+	/* Context device to use for job */
+	struct host1x_memory_context *memory_context;
+	/* Stream ID to use if context isolation is disabled (!memory_context) */
+	u32 engine_fallback_streamid;
+	/* Engine offset to program stream ID to */
+	u32 engine_streamid_offset;
 };
 
 struct host1x_job *host1x_job_alloc(struct host1x_channel *ch,
-- 
GitLab


From e078d8d6c3849019b927edb5beeca38dea00050c Mon Sep 17 00:00:00 2001
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: Mon, 27 Jun 2022 17:19:51 +0300
Subject: [PATCH 1687/1731] drm/tegra: falcon: Set DMACTX field on DMA
 transactions

The DMACTX field determines which context, as specified in the
TRANSCFG register, is used. While during boot it doesn't matter
which is used, later on it matters and this value is reused by
the firmware.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/drm/tegra/falcon.c | 8 ++++++++
 drivers/gpu/drm/tegra/falcon.h | 1 +
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/tegra/falcon.c b/drivers/gpu/drm/tegra/falcon.c
index 3762d87759d98..c0d85463eb1ac 100644
--- a/drivers/gpu/drm/tegra/falcon.c
+++ b/drivers/gpu/drm/tegra/falcon.c
@@ -48,6 +48,14 @@ static int falcon_copy_chunk(struct falcon *falcon,
 	if (target == FALCON_MEMORY_IMEM)
 		cmd |= FALCON_DMATRFCMD_IMEM;
 
+	/*
+	 * Use second DMA context (i.e. the one for firmware). Strictly
+	 * speaking, at this point both DMA contexts point to the firmware
+	 * stream ID, but this register's value will be reused by the firmware
+	 * for later DMA transactions, so we need to use the correct value.
+	 */
+	cmd |= FALCON_DMATRFCMD_DMACTX(1);
+
 	falcon_writel(falcon, offset, FALCON_DMATRFMOFFS);
 	falcon_writel(falcon, base, FALCON_DMATRFFBOFFS);
 	falcon_writel(falcon, cmd, FALCON_DMATRFCMD);
diff --git a/drivers/gpu/drm/tegra/falcon.h b/drivers/gpu/drm/tegra/falcon.h
index c56ee32d92eec..1955cf11a8a65 100644
--- a/drivers/gpu/drm/tegra/falcon.h
+++ b/drivers/gpu/drm/tegra/falcon.h
@@ -50,6 +50,7 @@
 #define FALCON_DMATRFCMD_IDLE			(1 << 1)
 #define FALCON_DMATRFCMD_IMEM			(1 << 4)
 #define FALCON_DMATRFCMD_SIZE_256B		(6 << 8)
+#define FALCON_DMATRFCMD_DMACTX(v)		(((v) & 0x7) << 12)
 
 #define FALCON_DMATRFFBOFFS			0x0000111c
 
-- 
GitLab


From 88c0292f023da4e4753a271430a36a66e6fb974f Mon Sep 17 00:00:00 2001
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: Mon, 27 Jun 2022 17:19:52 +0300
Subject: [PATCH 1688/1731] drm/tegra: nvdec: Fix TRANSCFG register offset

NVDEC's TRANSCFG register is at a different offset than VIC.
This becomes a problem now when context isolation is enabled and
the reset value of the register is no longer sufficient.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/drm/tegra/nvdec.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/tegra/nvdec.c b/drivers/gpu/drm/tegra/nvdec.c
index 79e1e88203cf4..386f9b2e78c41 100644
--- a/drivers/gpu/drm/tegra/nvdec.c
+++ b/drivers/gpu/drm/tegra/nvdec.c
@@ -21,6 +21,8 @@
 #include "falcon.h"
 #include "vic.h"
 
+#define NVDEC_TFBIF_TRANSCFG			0x2c44
+
 struct nvdec_config {
 	const char *firmware;
 	unsigned int version;
@@ -63,7 +65,7 @@ static int nvdec_boot(struct nvdec *nvdec)
 		u32 value;
 
 		value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) | TRANSCFG_ATT(0, TRANSCFG_SID_HW);
-		nvdec_writel(nvdec, value, VIC_TFBIF_TRANSCFG);
+		nvdec_writel(nvdec, value, NVDEC_TFBIF_TRANSCFG);
 
 		if (spec->num_ids > 0) {
 			value = spec->ids[0] & 0xffff;
-- 
GitLab


From e09db97889ec647ad373f7a7422c83099c6120c5 Mon Sep 17 00:00:00 2001
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: Mon, 27 Jun 2022 17:19:53 +0300
Subject: [PATCH 1689/1731] drm/tegra: Support context isolation

For engines that support context isolation, allocate a context when
opening a channel, and set up stream ID offset and context fields
when submitting a job.

As of this commit, the stream ID offset and fallback stream ID
are not used when context isolation is disabled. However, with
upcoming patches that enable a full featured job opcode sequence,
these will be necessary.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/drm/tegra/drm.h    |  3 +++
 drivers/gpu/drm/tegra/submit.c | 48 +++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/tegra/uapi.c   | 43 ++++++++++++++++++++++++++++--
 3 files changed, 91 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h
index fc0a19554eac7..2acc8f2948ade 100644
--- a/drivers/gpu/drm/tegra/drm.h
+++ b/drivers/gpu/drm/tegra/drm.h
@@ -80,6 +80,7 @@ struct tegra_drm_context {
 
 	/* Only used by new UAPI. */
 	struct xarray mappings;
+	struct host1x_memory_context *memory_context;
 };
 
 struct tegra_drm_client_ops {
@@ -91,6 +92,8 @@ struct tegra_drm_client_ops {
 	int (*submit)(struct tegra_drm_context *context,
 		      struct drm_tegra_submit *args, struct drm_device *drm,
 		      struct drm_file *file);
+	int (*get_streamid_offset)(struct tegra_drm_client *client, u32 *offset);
+	int (*can_use_memory_ctx)(struct tegra_drm_client *client, bool *supported);
 };
 
 int tegra_drm_submit(struct tegra_drm_context *context,
diff --git a/drivers/gpu/drm/tegra/submit.c b/drivers/gpu/drm/tegra/submit.c
index 6d6dd8c354757..b24738bdf3df8 100644
--- a/drivers/gpu/drm/tegra/submit.c
+++ b/drivers/gpu/drm/tegra/submit.c
@@ -498,6 +498,9 @@ static void release_job(struct host1x_job *job)
 	struct tegra_drm_submit_data *job_data = job->user_data;
 	u32 i;
 
+	if (job->memory_context)
+		host1x_memory_context_put(job->memory_context);
+
 	for (i = 0; i < job_data->num_used_mappings; i++)
 		tegra_drm_mapping_put(job_data->used_mappings[i].mapping);
 
@@ -588,11 +591,51 @@ int tegra_drm_ioctl_channel_submit(struct drm_device *drm, void *data,
 		goto put_job;
 	}
 
+	if (context->client->ops->get_streamid_offset) {
+		err = context->client->ops->get_streamid_offset(
+			context->client, &job->engine_streamid_offset);
+		if (err) {
+			SUBMIT_ERR(context, "failed to get streamid offset: %d", err);
+			goto unpin_job;
+		}
+	}
+
+	if (context->memory_context && context->client->ops->can_use_memory_ctx) {
+		bool supported;
+
+		err = context->client->ops->can_use_memory_ctx(context->client, &supported);
+		if (err) {
+			SUBMIT_ERR(context, "failed to detect if engine can use memory context: %d", err);
+			goto unpin_job;
+		}
+
+		if (supported) {
+			job->memory_context = context->memory_context;
+			host1x_memory_context_get(job->memory_context);
+		}
+	} else if (context->client->ops->get_streamid_offset) {
+#ifdef CONFIG_IOMMU_API
+		struct iommu_fwspec *spec;
+
+		/*
+		 * Job submission will need to temporarily change stream ID,
+		 * so need to tell it what to change it back to.
+		 */
+		spec = dev_iommu_fwspec_get(context->client->base.dev);
+		if (spec && spec->num_ids > 0)
+			job->engine_fallback_streamid = spec->ids[0] & 0xffff;
+		else
+			job->engine_fallback_streamid = 0x7f;
+#else
+		job->engine_fallback_streamid = 0x7f;
+#endif
+	}
+
 	/* Boot engine. */
 	err = pm_runtime_resume_and_get(context->client->base.dev);
 	if (err < 0) {
 		SUBMIT_ERR(context, "could not power up engine: %d", err);
-		goto unpin_job;
+		goto put_memory_context;
 	}
 
 	job->user_data = job_data;
@@ -627,6 +670,9 @@ int tegra_drm_ioctl_channel_submit(struct drm_device *drm, void *data,
 
 	goto put_job;
 
+put_memory_context:
+	if (job->memory_context)
+		host1x_memory_context_put(job->memory_context);
 unpin_job:
 	host1x_job_unpin(job);
 put_job:
diff --git a/drivers/gpu/drm/tegra/uapi.c b/drivers/gpu/drm/tegra/uapi.c
index 9ab9179d20262..a98239cb0e29a 100644
--- a/drivers/gpu/drm/tegra/uapi.c
+++ b/drivers/gpu/drm/tegra/uapi.c
@@ -33,6 +33,9 @@ static void tegra_drm_channel_context_close(struct tegra_drm_context *context)
 	struct tegra_drm_mapping *mapping;
 	unsigned long id;
 
+	if (context->memory_context)
+		host1x_memory_context_put(context->memory_context);
+
 	xa_for_each(&context->mappings, id, mapping)
 		tegra_drm_mapping_put(mapping);
 
@@ -72,6 +75,7 @@ static struct tegra_drm_client *tegra_drm_find_client(struct tegra_drm *tegra, u
 
 int tegra_drm_ioctl_channel_open(struct drm_device *drm, void *data, struct drm_file *file)
 {
+	struct host1x *host = tegra_drm_to_host1x(drm->dev_private);
 	struct tegra_drm_file *fpriv = file->driver_priv;
 	struct tegra_drm *tegra = drm->dev_private;
 	struct drm_tegra_channel_open *args = data;
@@ -102,10 +106,36 @@ int tegra_drm_ioctl_channel_open(struct drm_device *drm, void *data, struct drm_
 		}
 	}
 
+	/* Only allocate context if the engine supports context isolation. */
+	if (device_iommu_mapped(client->base.dev) && client->ops->can_use_memory_ctx) {
+		bool supported;
+
+		err = client->ops->can_use_memory_ctx(client, &supported);
+		if (err)
+			goto put_channel;
+
+		if (supported)
+			context->memory_context = host1x_memory_context_alloc(
+				host, get_task_pid(current, PIDTYPE_TGID));
+
+		if (IS_ERR(context->memory_context)) {
+			if (PTR_ERR(context->memory_context) != -EOPNOTSUPP) {
+				err = PTR_ERR(context->memory_context);
+				goto put_channel;
+			} else {
+				/*
+				 * OK, HW does not support contexts or contexts
+				 * are disabled.
+				 */
+				context->memory_context = NULL;
+			}
+		}
+	}
+
 	err = xa_alloc(&fpriv->contexts, &args->context, context, XA_LIMIT(1, U32_MAX),
 		       GFP_KERNEL);
 	if (err < 0)
-		goto put_channel;
+		goto put_memctx;
 
 	context->client = client;
 	xa_init_flags(&context->mappings, XA_FLAGS_ALLOC1);
@@ -118,6 +148,9 @@ int tegra_drm_ioctl_channel_open(struct drm_device *drm, void *data, struct drm_
 
 	return 0;
 
+put_memctx:
+	if (context->memory_context)
+		host1x_memory_context_put(context->memory_context);
 put_channel:
 	host1x_channel_put(context->channel);
 free:
@@ -156,6 +189,7 @@ int tegra_drm_ioctl_channel_map(struct drm_device *drm, void *data, struct drm_f
 	struct tegra_drm_mapping *mapping;
 	struct tegra_drm_context *context;
 	enum dma_data_direction direction;
+	struct device *mapping_dev;
 	int err = 0;
 
 	if (args->flags & ~DRM_TEGRA_CHANNEL_MAP_READ_WRITE)
@@ -177,6 +211,11 @@ int tegra_drm_ioctl_channel_map(struct drm_device *drm, void *data, struct drm_f
 
 	kref_init(&mapping->ref);
 
+	if (context->memory_context)
+		mapping_dev = &context->memory_context->dev;
+	else
+		mapping_dev = context->client->base.dev;
+
 	mapping->bo = tegra_gem_lookup(file, args->handle);
 	if (!mapping->bo) {
 		err = -EINVAL;
@@ -201,7 +240,7 @@ int tegra_drm_ioctl_channel_map(struct drm_device *drm, void *data, struct drm_f
 		goto put_gem;
 	}
 
-	mapping->map = host1x_bo_pin(context->client->base.dev, mapping->bo, direction, NULL);
+	mapping->map = host1x_bo_pin(mapping_dev, mapping->bo, direction, NULL);
 	if (IS_ERR(mapping->map)) {
 		err = PTR_ERR(mapping->map);
 		goto put_gem;
-- 
GitLab


From bf0297ac77f3c3187a79a612082ce7ddb64c1e4b Mon Sep 17 00:00:00 2001
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: Mon, 27 Jun 2022 17:19:54 +0300
Subject: [PATCH 1690/1731] drm/tegra: Implement stream ID related callbacks on
 engines

Implement the get_streamid_offset and can_use_memory_ctx callbacks
required for supporting context isolation. Since old firmware on VIC
cannot support context isolation without hacks that we don't want to
implement, check the firmware binary to see if context isolation
should be enabled.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/drm/tegra/drm.h   |  8 +++++
 drivers/gpu/drm/tegra/nvdec.c |  9 +++++
 drivers/gpu/drm/tegra/vic.c   | 67 ++++++++++++++++++++++++++++++-----
 3 files changed, 76 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h
index 2acc8f2948ade..845e60f144c71 100644
--- a/drivers/gpu/drm/tegra/drm.h
+++ b/drivers/gpu/drm/tegra/drm.h
@@ -100,6 +100,14 @@ int tegra_drm_submit(struct tegra_drm_context *context,
 		     struct drm_tegra_submit *args, struct drm_device *drm,
 		     struct drm_file *file);
 
+static inline int
+tegra_drm_get_streamid_offset_thi(struct tegra_drm_client *client, u32 *offset)
+{
+	*offset = 0x30;
+
+	return 0;
+}
+
 struct tegra_drm_client {
 	struct host1x_client base;
 	struct list_head list;
diff --git a/drivers/gpu/drm/tegra/nvdec.c b/drivers/gpu/drm/tegra/nvdec.c
index 386f9b2e78c41..a84f617096792 100644
--- a/drivers/gpu/drm/tegra/nvdec.c
+++ b/drivers/gpu/drm/tegra/nvdec.c
@@ -306,10 +306,19 @@ static void nvdec_close_channel(struct tegra_drm_context *context)
 	host1x_channel_put(context->channel);
 }
 
+static int nvdec_can_use_memory_ctx(struct tegra_drm_client *client, bool *supported)
+{
+	*supported = true;
+
+	return 0;
+}
+
 static const struct tegra_drm_client_ops nvdec_ops = {
 	.open_channel = nvdec_open_channel,
 	.close_channel = nvdec_close_channel,
 	.submit = tegra_drm_submit,
+	.get_streamid_offset = tegra_drm_get_streamid_offset_thi,
+	.can_use_memory_ctx = nvdec_can_use_memory_ctx,
 };
 
 #define NVIDIA_TEGRA_210_NVDEC_FIRMWARE "nvidia/tegra210/nvdec.bin"
diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c
index f56f5921a8c25..c5526bda88d66 100644
--- a/drivers/gpu/drm/tegra/vic.c
+++ b/drivers/gpu/drm/tegra/vic.c
@@ -38,6 +38,8 @@ struct vic {
 	struct clk *clk;
 	struct reset_control *rst;
 
+	bool can_use_context;
+
 	/* Platform configuration */
 	const struct vic_config *config;
 };
@@ -229,28 +231,38 @@ static int vic_load_firmware(struct vic *vic)
 {
 	struct host1x_client *client = &vic->client.base;
 	struct tegra_drm *tegra = vic->client.drm;
+	static DEFINE_MUTEX(lock);
+	u32 fce_bin_data_offset;
 	dma_addr_t iova;
 	size_t size;
 	void *virt;
 	int err;
 
-	if (vic->falcon.firmware.virt)
-		return 0;
+	mutex_lock(&lock);
+
+	if (vic->falcon.firmware.virt) {
+		err = 0;
+		goto unlock;
+	}
 
 	err = falcon_read_firmware(&vic->falcon, vic->config->firmware);
 	if (err < 0)
-		return err;
+		goto unlock;
 
 	size = vic->falcon.firmware.size;
 
 	if (!client->group) {
 		virt = dma_alloc_coherent(vic->dev, size, &iova, GFP_KERNEL);
-		if (!virt)
-			return -ENOMEM;
+		if (!virt) {
+			err = -ENOMEM;
+			goto unlock;
+		}
 	} else {
 		virt = tegra_drm_alloc(tegra, size, &iova);
-		if (IS_ERR(virt))
-			return PTR_ERR(virt);
+		if (IS_ERR(virt)) {
+			err = PTR_ERR(virt);
+			goto unlock;
+		}
 	}
 
 	vic->falcon.firmware.virt = virt;
@@ -277,7 +289,28 @@ static int vic_load_firmware(struct vic *vic)
 		vic->falcon.firmware.phys = phys;
 	}
 
-	return 0;
+	/*
+	 * Check if firmware is new enough to not require mapping firmware
+	 * to data buffer domains.
+	 */
+	fce_bin_data_offset = *(u32 *)(virt + VIC_UCODE_FCE_DATA_OFFSET);
+
+	if (!vic->config->supports_sid) {
+		vic->can_use_context = false;
+	} else if (fce_bin_data_offset != 0x0 && fce_bin_data_offset != 0xa5a5a5a5) {
+		/*
+		 * Firmware will access FCE through STREAMID0, so context
+		 * isolation cannot be used.
+		 */
+		vic->can_use_context = false;
+		dev_warn_once(vic->dev, "context isolation disabled due to old firmware\n");
+	} else {
+		vic->can_use_context = true;
+	}
+
+unlock:
+	mutex_unlock(&lock);
+	return err;
 
 cleanup:
 	if (!client->group)
@@ -285,6 +318,7 @@ cleanup:
 	else
 		tegra_drm_free(tegra, size, virt, iova);
 
+	mutex_unlock(&lock);
 	return err;
 }
 
@@ -358,10 +392,27 @@ static void vic_close_channel(struct tegra_drm_context *context)
 	host1x_channel_put(context->channel);
 }
 
+static int vic_can_use_memory_ctx(struct tegra_drm_client *client, bool *supported)
+{
+	struct vic *vic = to_vic(client);
+	int err;
+
+	/* This doesn't access HW so it's safe to call without powering up. */
+	err = vic_load_firmware(vic);
+	if (err < 0)
+		return err;
+
+	*supported = vic->can_use_context;
+
+	return 0;
+}
+
 static const struct tegra_drm_client_ops vic_ops = {
 	.open_channel = vic_open_channel,
 	.close_channel = vic_close_channel,
 	.submit = tegra_drm_submit,
+	.get_streamid_offset = tegra_drm_get_streamid_offset_thi,
+	.can_use_memory_ctx = vic_can_use_memory_ctx,
 };
 
 #define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin"
-- 
GitLab


From 3000c4ac02584e877926f598aff501c36202750c Mon Sep 17 00:00:00 2001
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: Mon, 27 Jun 2022 17:19:59 +0300
Subject: [PATCH 1691/1731] gpu: host1x: Deduplicate hardware headers

Host1x class information and opcodes are unchanged or backwards
compatible across SoCs so let's not duplicate them for each one
but have them in a shared header file.

At the same time, add opcode functions for acquire/release_mlock.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/host1x/hw/host1x01_hardware.h | 114 +---------------
 drivers/gpu/host1x/hw/host1x02_hardware.h | 113 +---------------
 drivers/gpu/host1x/hw/host1x04_hardware.h | 113 +---------------
 drivers/gpu/host1x/hw/host1x05_hardware.h | 113 +---------------
 drivers/gpu/host1x/hw/host1x06_hardware.h | 128 +-----------------
 drivers/gpu/host1x/hw/host1x07_hardware.h | 128 +-----------------
 drivers/gpu/host1x/hw/opcodes.h           | 150 ++++++++++++++++++++++
 7 files changed, 156 insertions(+), 703 deletions(-)
 create mode 100644 drivers/gpu/host1x/hw/opcodes.h

diff --git a/drivers/gpu/host1x/hw/host1x01_hardware.h b/drivers/gpu/host1x/hw/host1x01_hardware.h
index fe59df1d3dc37..cb93d7c1808c9 100644
--- a/drivers/gpu/host1x/hw/host1x01_hardware.h
+++ b/drivers/gpu/host1x/hw/host1x01_hardware.h
@@ -15,118 +15,6 @@
 #include "hw_host1x01_sync.h"
 #include "hw_host1x01_uclass.h"
 
-static inline u32 host1x_class_host_wait_syncpt(
-	unsigned indx, unsigned threshold)
-{
-	return host1x_uclass_wait_syncpt_indx_f(indx)
-		| host1x_uclass_wait_syncpt_thresh_f(threshold);
-}
-
-static inline u32 host1x_class_host_load_syncpt_base(
-	unsigned indx, unsigned threshold)
-{
-	return host1x_uclass_load_syncpt_base_base_indx_f(indx)
-		| host1x_uclass_load_syncpt_base_value_f(threshold);
-}
-
-static inline u32 host1x_class_host_wait_syncpt_base(
-	unsigned indx, unsigned base_indx, unsigned offset)
-{
-	return host1x_uclass_wait_syncpt_base_indx_f(indx)
-		| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
-		| host1x_uclass_wait_syncpt_base_offset_f(offset);
-}
-
-static inline u32 host1x_class_host_incr_syncpt_base(
-	unsigned base_indx, unsigned offset)
-{
-	return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
-		| host1x_uclass_incr_syncpt_base_offset_f(offset);
-}
-
-static inline u32 host1x_class_host_incr_syncpt(
-	unsigned cond, unsigned indx)
-{
-	return host1x_uclass_incr_syncpt_cond_f(cond)
-		| host1x_uclass_incr_syncpt_indx_f(indx);
-}
-
-static inline u32 host1x_class_host_indoff_reg_write(
-	unsigned mod_id, unsigned offset, bool auto_inc)
-{
-	u32 v = host1x_uclass_indoff_indbe_f(0xf)
-		| host1x_uclass_indoff_indmodid_f(mod_id)
-		| host1x_uclass_indoff_indroffset_f(offset);
-	if (auto_inc)
-		v |= host1x_uclass_indoff_autoinc_f(1);
-	return v;
-}
-
-static inline u32 host1x_class_host_indoff_reg_read(
-	unsigned mod_id, unsigned offset, bool auto_inc)
-{
-	u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
-		| host1x_uclass_indoff_indroffset_f(offset)
-		| host1x_uclass_indoff_rwn_read_v();
-	if (auto_inc)
-		v |= host1x_uclass_indoff_autoinc_f(1);
-	return v;
-}
-
-
-/* cdma opcodes */
-static inline u32 host1x_opcode_setclass(
-	unsigned class_id, unsigned offset, unsigned mask)
-{
-	return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
-}
-
-static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
-{
-	return (1 << 28) | (offset << 16) | count;
-}
-
-static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
-{
-	return (2 << 28) | (offset << 16) | count;
-}
-
-static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
-{
-	return (3 << 28) | (offset << 16) | mask;
-}
-
-static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
-{
-	return (4 << 28) | (offset << 16) | value;
-}
-
-static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
-{
-	return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
-		host1x_class_host_incr_syncpt(cond, indx));
-}
-
-static inline u32 host1x_opcode_restart(unsigned address)
-{
-	return (5 << 28) | (address >> 4);
-}
-
-static inline u32 host1x_opcode_gather(unsigned count)
-{
-	return (6 << 28) | count;
-}
-
-static inline u32 host1x_opcode_gather_nonincr(unsigned offset,	unsigned count)
-{
-	return (6 << 28) | (offset << 16) | BIT(15) | count;
-}
-
-static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
-{
-	return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
-}
-
-#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
+#include "opcodes.h"
 
 #endif
diff --git a/drivers/gpu/host1x/hw/host1x02_hardware.h b/drivers/gpu/host1x/hw/host1x02_hardware.h
index af60d7fb016d9..2d1282b9bc331 100644
--- a/drivers/gpu/host1x/hw/host1x02_hardware.h
+++ b/drivers/gpu/host1x/hw/host1x02_hardware.h
@@ -15,117 +15,6 @@
 #include "hw_host1x02_sync.h"
 #include "hw_host1x02_uclass.h"
 
-static inline u32 host1x_class_host_wait_syncpt(
-	unsigned indx, unsigned threshold)
-{
-	return host1x_uclass_wait_syncpt_indx_f(indx)
-		| host1x_uclass_wait_syncpt_thresh_f(threshold);
-}
-
-static inline u32 host1x_class_host_load_syncpt_base(
-	unsigned indx, unsigned threshold)
-{
-	return host1x_uclass_load_syncpt_base_base_indx_f(indx)
-		| host1x_uclass_load_syncpt_base_value_f(threshold);
-}
-
-static inline u32 host1x_class_host_wait_syncpt_base(
-	unsigned indx, unsigned base_indx, unsigned offset)
-{
-	return host1x_uclass_wait_syncpt_base_indx_f(indx)
-		| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
-		| host1x_uclass_wait_syncpt_base_offset_f(offset);
-}
-
-static inline u32 host1x_class_host_incr_syncpt_base(
-	unsigned base_indx, unsigned offset)
-{
-	return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
-		| host1x_uclass_incr_syncpt_base_offset_f(offset);
-}
-
-static inline u32 host1x_class_host_incr_syncpt(
-	unsigned cond, unsigned indx)
-{
-	return host1x_uclass_incr_syncpt_cond_f(cond)
-		| host1x_uclass_incr_syncpt_indx_f(indx);
-}
-
-static inline u32 host1x_class_host_indoff_reg_write(
-	unsigned mod_id, unsigned offset, bool auto_inc)
-{
-	u32 v = host1x_uclass_indoff_indbe_f(0xf)
-		| host1x_uclass_indoff_indmodid_f(mod_id)
-		| host1x_uclass_indoff_indroffset_f(offset);
-	if (auto_inc)
-		v |= host1x_uclass_indoff_autoinc_f(1);
-	return v;
-}
-
-static inline u32 host1x_class_host_indoff_reg_read(
-	unsigned mod_id, unsigned offset, bool auto_inc)
-{
-	u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
-		| host1x_uclass_indoff_indroffset_f(offset)
-		| host1x_uclass_indoff_rwn_read_v();
-	if (auto_inc)
-		v |= host1x_uclass_indoff_autoinc_f(1);
-	return v;
-}
-
-/* cdma opcodes */
-static inline u32 host1x_opcode_setclass(
-	unsigned class_id, unsigned offset, unsigned mask)
-{
-	return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
-}
-
-static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
-{
-	return (1 << 28) | (offset << 16) | count;
-}
-
-static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
-{
-	return (2 << 28) | (offset << 16) | count;
-}
-
-static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
-{
-	return (3 << 28) | (offset << 16) | mask;
-}
-
-static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
-{
-	return (4 << 28) | (offset << 16) | value;
-}
-
-static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
-{
-	return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
-		host1x_class_host_incr_syncpt(cond, indx));
-}
-
-static inline u32 host1x_opcode_restart(unsigned address)
-{
-	return (5 << 28) | (address >> 4);
-}
-
-static inline u32 host1x_opcode_gather(unsigned count)
-{
-	return (6 << 28) | count;
-}
-
-static inline u32 host1x_opcode_gather_nonincr(unsigned offset,	unsigned count)
-{
-	return (6 << 28) | (offset << 16) | BIT(15) | count;
-}
-
-static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
-{
-	return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
-}
-
-#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
+#include "opcodes.h"
 
 #endif
diff --git a/drivers/gpu/host1x/hw/host1x04_hardware.h b/drivers/gpu/host1x/hw/host1x04_hardware.h
index 4f9bcddf27e32..84d244e8af302 100644
--- a/drivers/gpu/host1x/hw/host1x04_hardware.h
+++ b/drivers/gpu/host1x/hw/host1x04_hardware.h
@@ -15,117 +15,6 @@
 #include "hw_host1x04_sync.h"
 #include "hw_host1x04_uclass.h"
 
-static inline u32 host1x_class_host_wait_syncpt(
-	unsigned indx, unsigned threshold)
-{
-	return host1x_uclass_wait_syncpt_indx_f(indx)
-		| host1x_uclass_wait_syncpt_thresh_f(threshold);
-}
-
-static inline u32 host1x_class_host_load_syncpt_base(
-	unsigned indx, unsigned threshold)
-{
-	return host1x_uclass_load_syncpt_base_base_indx_f(indx)
-		| host1x_uclass_load_syncpt_base_value_f(threshold);
-}
-
-static inline u32 host1x_class_host_wait_syncpt_base(
-	unsigned indx, unsigned base_indx, unsigned offset)
-{
-	return host1x_uclass_wait_syncpt_base_indx_f(indx)
-		| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
-		| host1x_uclass_wait_syncpt_base_offset_f(offset);
-}
-
-static inline u32 host1x_class_host_incr_syncpt_base(
-	unsigned base_indx, unsigned offset)
-{
-	return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
-		| host1x_uclass_incr_syncpt_base_offset_f(offset);
-}
-
-static inline u32 host1x_class_host_incr_syncpt(
-	unsigned cond, unsigned indx)
-{
-	return host1x_uclass_incr_syncpt_cond_f(cond)
-		| host1x_uclass_incr_syncpt_indx_f(indx);
-}
-
-static inline u32 host1x_class_host_indoff_reg_write(
-	unsigned mod_id, unsigned offset, bool auto_inc)
-{
-	u32 v = host1x_uclass_indoff_indbe_f(0xf)
-		| host1x_uclass_indoff_indmodid_f(mod_id)
-		| host1x_uclass_indoff_indroffset_f(offset);
-	if (auto_inc)
-		v |= host1x_uclass_indoff_autoinc_f(1);
-	return v;
-}
-
-static inline u32 host1x_class_host_indoff_reg_read(
-	unsigned mod_id, unsigned offset, bool auto_inc)
-{
-	u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
-		| host1x_uclass_indoff_indroffset_f(offset)
-		| host1x_uclass_indoff_rwn_read_v();
-	if (auto_inc)
-		v |= host1x_uclass_indoff_autoinc_f(1);
-	return v;
-}
-
-/* cdma opcodes */
-static inline u32 host1x_opcode_setclass(
-	unsigned class_id, unsigned offset, unsigned mask)
-{
-	return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
-}
-
-static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
-{
-	return (1 << 28) | (offset << 16) | count;
-}
-
-static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
-{
-	return (2 << 28) | (offset << 16) | count;
-}
-
-static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
-{
-	return (3 << 28) | (offset << 16) | mask;
-}
-
-static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
-{
-	return (4 << 28) | (offset << 16) | value;
-}
-
-static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
-{
-	return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
-		host1x_class_host_incr_syncpt(cond, indx));
-}
-
-static inline u32 host1x_opcode_restart(unsigned address)
-{
-	return (5 << 28) | (address >> 4);
-}
-
-static inline u32 host1x_opcode_gather(unsigned count)
-{
-	return (6 << 28) | count;
-}
-
-static inline u32 host1x_opcode_gather_nonincr(unsigned offset,	unsigned count)
-{
-	return (6 << 28) | (offset << 16) | BIT(15) | count;
-}
-
-static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
-{
-	return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
-}
-
-#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
+#include "opcodes.h"
 
 #endif
diff --git a/drivers/gpu/host1x/hw/host1x05_hardware.h b/drivers/gpu/host1x/hw/host1x05_hardware.h
index af3ab4b7f0106..1dcde6ec79095 100644
--- a/drivers/gpu/host1x/hw/host1x05_hardware.h
+++ b/drivers/gpu/host1x/hw/host1x05_hardware.h
@@ -15,117 +15,6 @@
 #include "hw_host1x05_sync.h"
 #include "hw_host1x05_uclass.h"
 
-static inline u32 host1x_class_host_wait_syncpt(
-	unsigned indx, unsigned threshold)
-{
-	return host1x_uclass_wait_syncpt_indx_f(indx)
-		| host1x_uclass_wait_syncpt_thresh_f(threshold);
-}
-
-static inline u32 host1x_class_host_load_syncpt_base(
-	unsigned indx, unsigned threshold)
-{
-	return host1x_uclass_load_syncpt_base_base_indx_f(indx)
-		| host1x_uclass_load_syncpt_base_value_f(threshold);
-}
-
-static inline u32 host1x_class_host_wait_syncpt_base(
-	unsigned indx, unsigned base_indx, unsigned offset)
-{
-	return host1x_uclass_wait_syncpt_base_indx_f(indx)
-		| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
-		| host1x_uclass_wait_syncpt_base_offset_f(offset);
-}
-
-static inline u32 host1x_class_host_incr_syncpt_base(
-	unsigned base_indx, unsigned offset)
-{
-	return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
-		| host1x_uclass_incr_syncpt_base_offset_f(offset);
-}
-
-static inline u32 host1x_class_host_incr_syncpt(
-	unsigned cond, unsigned indx)
-{
-	return host1x_uclass_incr_syncpt_cond_f(cond)
-		| host1x_uclass_incr_syncpt_indx_f(indx);
-}
-
-static inline u32 host1x_class_host_indoff_reg_write(
-	unsigned mod_id, unsigned offset, bool auto_inc)
-{
-	u32 v = host1x_uclass_indoff_indbe_f(0xf)
-		| host1x_uclass_indoff_indmodid_f(mod_id)
-		| host1x_uclass_indoff_indroffset_f(offset);
-	if (auto_inc)
-		v |= host1x_uclass_indoff_autoinc_f(1);
-	return v;
-}
-
-static inline u32 host1x_class_host_indoff_reg_read(
-	unsigned mod_id, unsigned offset, bool auto_inc)
-{
-	u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
-		| host1x_uclass_indoff_indroffset_f(offset)
-		| host1x_uclass_indoff_rwn_read_v();
-	if (auto_inc)
-		v |= host1x_uclass_indoff_autoinc_f(1);
-	return v;
-}
-
-/* cdma opcodes */
-static inline u32 host1x_opcode_setclass(
-	unsigned class_id, unsigned offset, unsigned mask)
-{
-	return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
-}
-
-static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
-{
-	return (1 << 28) | (offset << 16) | count;
-}
-
-static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
-{
-	return (2 << 28) | (offset << 16) | count;
-}
-
-static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
-{
-	return (3 << 28) | (offset << 16) | mask;
-}
-
-static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
-{
-	return (4 << 28) | (offset << 16) | value;
-}
-
-static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
-{
-	return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
-		host1x_class_host_incr_syncpt(cond, indx));
-}
-
-static inline u32 host1x_opcode_restart(unsigned address)
-{
-	return (5 << 28) | (address >> 4);
-}
-
-static inline u32 host1x_opcode_gather(unsigned count)
-{
-	return (6 << 28) | count;
-}
-
-static inline u32 host1x_opcode_gather_nonincr(unsigned offset,	unsigned count)
-{
-	return (6 << 28) | (offset << 16) | BIT(15) | count;
-}
-
-static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
-{
-	return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
-}
-
-#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
+#include "opcodes.h"
 
 #endif
diff --git a/drivers/gpu/host1x/hw/host1x06_hardware.h b/drivers/gpu/host1x/hw/host1x06_hardware.h
index 5d515745eee7e..c05cfa7e3090b 100644
--- a/drivers/gpu/host1x/hw/host1x06_hardware.h
+++ b/drivers/gpu/host1x/hw/host1x06_hardware.h
@@ -16,132 +16,6 @@
 #include "hw_host1x06_vm.h"
 #include "hw_host1x06_hypervisor.h"
 
-static inline u32 host1x_class_host_wait_syncpt(
-	unsigned indx, unsigned threshold)
-{
-	return host1x_uclass_wait_syncpt_indx_f(indx)
-		| host1x_uclass_wait_syncpt_thresh_f(threshold);
-}
-
-static inline u32 host1x_class_host_load_syncpt_base(
-	unsigned indx, unsigned threshold)
-{
-	return host1x_uclass_load_syncpt_base_base_indx_f(indx)
-		| host1x_uclass_load_syncpt_base_value_f(threshold);
-}
-
-static inline u32 host1x_class_host_wait_syncpt_base(
-	unsigned indx, unsigned base_indx, unsigned offset)
-{
-	return host1x_uclass_wait_syncpt_base_indx_f(indx)
-		| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
-		| host1x_uclass_wait_syncpt_base_offset_f(offset);
-}
-
-static inline u32 host1x_class_host_incr_syncpt_base(
-	unsigned base_indx, unsigned offset)
-{
-	return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
-		| host1x_uclass_incr_syncpt_base_offset_f(offset);
-}
-
-static inline u32 host1x_class_host_incr_syncpt(
-	unsigned cond, unsigned indx)
-{
-	return host1x_uclass_incr_syncpt_cond_f(cond)
-		| host1x_uclass_incr_syncpt_indx_f(indx);
-}
-
-static inline u32 host1x_class_host_indoff_reg_write(
-	unsigned mod_id, unsigned offset, bool auto_inc)
-{
-	u32 v = host1x_uclass_indoff_indbe_f(0xf)
-		| host1x_uclass_indoff_indmodid_f(mod_id)
-		| host1x_uclass_indoff_indroffset_f(offset);
-	if (auto_inc)
-		v |= host1x_uclass_indoff_autoinc_f(1);
-	return v;
-}
-
-static inline u32 host1x_class_host_indoff_reg_read(
-	unsigned mod_id, unsigned offset, bool auto_inc)
-{
-	u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
-		| host1x_uclass_indoff_indroffset_f(offset)
-		| host1x_uclass_indoff_rwn_read_v();
-	if (auto_inc)
-		v |= host1x_uclass_indoff_autoinc_f(1);
-	return v;
-}
-
-/* cdma opcodes */
-static inline u32 host1x_opcode_setclass(
-	unsigned class_id, unsigned offset, unsigned mask)
-{
-	return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
-}
-
-static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
-{
-	return (1 << 28) | (offset << 16) | count;
-}
-
-static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
-{
-	return (2 << 28) | (offset << 16) | count;
-}
-
-static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
-{
-	return (3 << 28) | (offset << 16) | mask;
-}
-
-static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
-{
-	return (4 << 28) | (offset << 16) | value;
-}
-
-static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
-{
-	return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
-		host1x_class_host_incr_syncpt(cond, indx));
-}
-
-static inline u32 host1x_opcode_restart(unsigned address)
-{
-	return (5 << 28) | (address >> 4);
-}
-
-static inline u32 host1x_opcode_gather(unsigned count)
-{
-	return (6 << 28) | count;
-}
-
-static inline u32 host1x_opcode_gather_nonincr(unsigned offset,	unsigned count)
-{
-	return (6 << 28) | (offset << 16) | BIT(15) | count;
-}
-
-static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
-{
-	return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
-}
-
-static inline u32 host1x_opcode_setstreamid(unsigned streamid)
-{
-	return (7 << 28) | streamid;
-}
-
-static inline u32 host1x_opcode_setpayload(unsigned payload)
-{
-	return (9 << 28) | payload;
-}
-
-static inline u32 host1x_opcode_gather_wide(unsigned count)
-{
-	return (12 << 28) | count;
-}
-
-#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
+#include "opcodes.h"
 
 #endif
diff --git a/drivers/gpu/host1x/hw/host1x07_hardware.h b/drivers/gpu/host1x/hw/host1x07_hardware.h
index 82c0cc9bb0b5f..d67364e03956f 100644
--- a/drivers/gpu/host1x/hw/host1x07_hardware.h
+++ b/drivers/gpu/host1x/hw/host1x07_hardware.h
@@ -16,132 +16,6 @@
 #include "hw_host1x07_vm.h"
 #include "hw_host1x07_hypervisor.h"
 
-static inline u32 host1x_class_host_wait_syncpt(
-	unsigned indx, unsigned threshold)
-{
-	return host1x_uclass_wait_syncpt_indx_f(indx)
-		| host1x_uclass_wait_syncpt_thresh_f(threshold);
-}
-
-static inline u32 host1x_class_host_load_syncpt_base(
-	unsigned indx, unsigned threshold)
-{
-	return host1x_uclass_load_syncpt_base_base_indx_f(indx)
-		| host1x_uclass_load_syncpt_base_value_f(threshold);
-}
-
-static inline u32 host1x_class_host_wait_syncpt_base(
-	unsigned indx, unsigned base_indx, unsigned offset)
-{
-	return host1x_uclass_wait_syncpt_base_indx_f(indx)
-		| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
-		| host1x_uclass_wait_syncpt_base_offset_f(offset);
-}
-
-static inline u32 host1x_class_host_incr_syncpt_base(
-	unsigned base_indx, unsigned offset)
-{
-	return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
-		| host1x_uclass_incr_syncpt_base_offset_f(offset);
-}
-
-static inline u32 host1x_class_host_incr_syncpt(
-	unsigned cond, unsigned indx)
-{
-	return host1x_uclass_incr_syncpt_cond_f(cond)
-		| host1x_uclass_incr_syncpt_indx_f(indx);
-}
-
-static inline u32 host1x_class_host_indoff_reg_write(
-	unsigned mod_id, unsigned offset, bool auto_inc)
-{
-	u32 v = host1x_uclass_indoff_indbe_f(0xf)
-		| host1x_uclass_indoff_indmodid_f(mod_id)
-		| host1x_uclass_indoff_indroffset_f(offset);
-	if (auto_inc)
-		v |= host1x_uclass_indoff_autoinc_f(1);
-	return v;
-}
-
-static inline u32 host1x_class_host_indoff_reg_read(
-	unsigned mod_id, unsigned offset, bool auto_inc)
-{
-	u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
-		| host1x_uclass_indoff_indroffset_f(offset)
-		| host1x_uclass_indoff_rwn_read_v();
-	if (auto_inc)
-		v |= host1x_uclass_indoff_autoinc_f(1);
-	return v;
-}
-
-/* cdma opcodes */
-static inline u32 host1x_opcode_setclass(
-	unsigned class_id, unsigned offset, unsigned mask)
-{
-	return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
-}
-
-static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
-{
-	return (1 << 28) | (offset << 16) | count;
-}
-
-static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
-{
-	return (2 << 28) | (offset << 16) | count;
-}
-
-static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
-{
-	return (3 << 28) | (offset << 16) | mask;
-}
-
-static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
-{
-	return (4 << 28) | (offset << 16) | value;
-}
-
-static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
-{
-	return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
-		host1x_class_host_incr_syncpt(cond, indx));
-}
-
-static inline u32 host1x_opcode_restart(unsigned address)
-{
-	return (5 << 28) | (address >> 4);
-}
-
-static inline u32 host1x_opcode_gather(unsigned count)
-{
-	return (6 << 28) | count;
-}
-
-static inline u32 host1x_opcode_gather_nonincr(unsigned offset,	unsigned count)
-{
-	return (6 << 28) | (offset << 16) | BIT(15) | count;
-}
-
-static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
-{
-	return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
-}
-
-static inline u32 host1x_opcode_setstreamid(unsigned streamid)
-{
-	return (7 << 28) | streamid;
-}
-
-static inline u32 host1x_opcode_setpayload(unsigned payload)
-{
-	return (9 << 28) | payload;
-}
-
-static inline u32 host1x_opcode_gather_wide(unsigned count)
-{
-	return (12 << 28) | count;
-}
-
-#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
+#include "opcodes.h"
 
 #endif
diff --git a/drivers/gpu/host1x/hw/opcodes.h b/drivers/gpu/host1x/hw/opcodes.h
new file mode 100644
index 0000000000000..649614499b04f
--- /dev/null
+++ b/drivers/gpu/host1x/hw/opcodes.h
@@ -0,0 +1,150 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Tegra host1x opcodes
+ *
+ * Copyright (c) 2022 NVIDIA Corporation.
+ */
+
+#ifndef __HOST1X_OPCODES_H
+#define __HOST1X_OPCODES_H
+
+#include <linux/types.h>
+
+static inline u32 host1x_class_host_wait_syncpt(
+	unsigned indx, unsigned threshold)
+{
+	return host1x_uclass_wait_syncpt_indx_f(indx)
+		| host1x_uclass_wait_syncpt_thresh_f(threshold);
+}
+
+static inline u32 host1x_class_host_load_syncpt_base(
+	unsigned indx, unsigned threshold)
+{
+	return host1x_uclass_load_syncpt_base_base_indx_f(indx)
+		| host1x_uclass_load_syncpt_base_value_f(threshold);
+}
+
+static inline u32 host1x_class_host_wait_syncpt_base(
+	unsigned indx, unsigned base_indx, unsigned offset)
+{
+	return host1x_uclass_wait_syncpt_base_indx_f(indx)
+		| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
+		| host1x_uclass_wait_syncpt_base_offset_f(offset);
+}
+
+static inline u32 host1x_class_host_incr_syncpt_base(
+	unsigned base_indx, unsigned offset)
+{
+	return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
+		| host1x_uclass_incr_syncpt_base_offset_f(offset);
+}
+
+static inline u32 host1x_class_host_incr_syncpt(
+	unsigned cond, unsigned indx)
+{
+	return host1x_uclass_incr_syncpt_cond_f(cond)
+		| host1x_uclass_incr_syncpt_indx_f(indx);
+}
+
+static inline u32 host1x_class_host_indoff_reg_write(
+	unsigned mod_id, unsigned offset, bool auto_inc)
+{
+	u32 v = host1x_uclass_indoff_indbe_f(0xf)
+		| host1x_uclass_indoff_indmodid_f(mod_id)
+		| host1x_uclass_indoff_indroffset_f(offset);
+	if (auto_inc)
+		v |= host1x_uclass_indoff_autoinc_f(1);
+	return v;
+}
+
+static inline u32 host1x_class_host_indoff_reg_read(
+	unsigned mod_id, unsigned offset, bool auto_inc)
+{
+	u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
+		| host1x_uclass_indoff_indroffset_f(offset)
+		| host1x_uclass_indoff_rwn_read_v();
+	if (auto_inc)
+		v |= host1x_uclass_indoff_autoinc_f(1);
+	return v;
+}
+
+static inline u32 host1x_opcode_setclass(
+	unsigned class_id, unsigned offset, unsigned mask)
+{
+	return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
+}
+
+static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
+{
+	return (1 << 28) | (offset << 16) | count;
+}
+
+static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
+{
+	return (2 << 28) | (offset << 16) | count;
+}
+
+static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
+{
+	return (3 << 28) | (offset << 16) | mask;
+}
+
+static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
+{
+	return (4 << 28) | (offset << 16) | value;
+}
+
+static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
+{
+	return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
+		host1x_class_host_incr_syncpt(cond, indx));
+}
+
+static inline u32 host1x_opcode_restart(unsigned address)
+{
+	return (5 << 28) | (address >> 4);
+}
+
+static inline u32 host1x_opcode_gather(unsigned count)
+{
+	return (6 << 28) | count;
+}
+
+static inline u32 host1x_opcode_gather_nonincr(unsigned offset,	unsigned count)
+{
+	return (6 << 28) | (offset << 16) | BIT(15) | count;
+}
+
+static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
+{
+	return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
+}
+
+static inline u32 host1x_opcode_setstreamid(unsigned streamid)
+{
+	return (7 << 28) | streamid;
+}
+
+static inline u32 host1x_opcode_setpayload(unsigned payload)
+{
+	return (9 << 28) | payload;
+}
+
+static inline u32 host1x_opcode_gather_wide(unsigned count)
+{
+	return (12 << 28) | count;
+}
+
+static inline u32 host1x_opcode_acquire_mlock(unsigned mlock)
+{
+	return (14 << 28) | (0 << 24) | mlock;
+}
+
+static inline u32 host1x_opcode_release_mlock(unsigned mlock)
+{
+	return (14 << 28) | (1 << 24) | mlock;
+}
+
+#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
+
+#endif
-- 
GitLab


From 97dea367d8dab90b520cda589f83c60514013110 Mon Sep 17 00:00:00 2001
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: Mon, 27 Jun 2022 17:20:00 +0300
Subject: [PATCH 1692/1731] gpu: host1x: Simplify register mapping and add
 common aperture

Refactor 'regs' property loading using devm_platform_ioremap_*
and add loading of the 'common' region found on Tegra234.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/host1x/dev.c | 46 +++++++++++++++++-----------------------
 drivers/gpu/host1x/dev.h |  3 +++
 2 files changed, 22 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 89cc79a48eab8..8c6ce8014c09d 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -40,6 +40,11 @@
 #include "hw/host1x06.h"
 #include "hw/host1x07.h"
 
+void host1x_common_writel(struct host1x *host1x, u32 v, u32 r)
+{
+	writel(v, host1x->common_regs + r);
+}
+
 void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)
 {
 	writel(v, host1x->hv_regs + r);
@@ -412,7 +417,6 @@ static int host1x_get_resets(struct host1x *host)
 static int host1x_probe(struct platform_device *pdev)
 {
 	struct host1x *host;
-	struct resource *regs, *hv_regs = NULL;
 	int syncpt_irq;
 	int err;
 
@@ -423,25 +427,23 @@ static int host1x_probe(struct platform_device *pdev)
 	host->info = of_device_get_match_data(&pdev->dev);
 
 	if (host->info->has_hypervisor) {
-		regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vm");
-		if (!regs) {
-			dev_err(&pdev->dev, "failed to get vm registers\n");
-			return -ENXIO;
-		}
+		host->regs = devm_platform_ioremap_resource_byname(pdev, "vm");
+		if (IS_ERR(host->regs))
+			return PTR_ERR(host->regs);
+
+		host->hv_regs = devm_platform_ioremap_resource_byname(pdev, "hypervisor");
+		if (IS_ERR(host->hv_regs))
+			return PTR_ERR(host->hv_regs);
 
-		hv_regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-						       "hypervisor");
-		if (!hv_regs) {
-			dev_err(&pdev->dev,
-				"failed to get hypervisor registers\n");
-			return -ENXIO;
+		if (host->info->has_common) {
+			host->common_regs = devm_platform_ioremap_resource_byname(pdev, "common");
+			if (IS_ERR(host->common_regs))
+				return PTR_ERR(host->common_regs);
 		}
 	} else {
-		regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-		if (!regs) {
-			dev_err(&pdev->dev, "failed to get registers\n");
-			return -ENXIO;
-		}
+		host->regs = devm_platform_ioremap_resource(pdev, 0);
+		if (IS_ERR(host->regs))
+			return PTR_ERR(host->regs);
 	}
 
 	syncpt_irq = platform_get_irq(pdev, 0);
@@ -456,16 +458,6 @@ static int host1x_probe(struct platform_device *pdev)
 	/* set common host1x device data */
 	platform_set_drvdata(pdev, host);
 
-	host->regs = devm_ioremap_resource(&pdev->dev, regs);
-	if (IS_ERR(host->regs))
-		return PTR_ERR(host->regs);
-
-	if (host->info->has_hypervisor) {
-		host->hv_regs = devm_ioremap_resource(&pdev->dev, hv_regs);
-		if (IS_ERR(host->hv_regs))
-			return PTR_ERR(host->hv_regs);
-	}
-
 	host->dev->dma_parms = &host->dma_parms;
 	dma_set_max_seg_size(host->dev, UINT_MAX);
 
diff --git a/drivers/gpu/host1x/dev.h b/drivers/gpu/host1x/dev.h
index 7552a45545347..85edcc6e0fc7a 100644
--- a/drivers/gpu/host1x/dev.h
+++ b/drivers/gpu/host1x/dev.h
@@ -100,6 +100,7 @@ struct host1x_info {
 	u64 dma_mask; /* mask of addressable memory */
 	bool has_wide_gather; /* supports GATHER_W opcode */
 	bool has_hypervisor; /* has hypervisor registers */
+	bool has_common; /* has common registers separate from hypervisor */
 	unsigned int num_sid_entries;
 	const struct host1x_sid_entry *sid_table;
 	/*
@@ -115,6 +116,7 @@ struct host1x {
 
 	void __iomem *regs;
 	void __iomem *hv_regs; /* hypervisor region */
+	void __iomem *common_regs;
 	struct host1x_syncpt *syncpt;
 	struct host1x_syncpt_base *bases;
 	struct device *dev;
@@ -156,6 +158,7 @@ struct host1x {
 	struct host1x_bo_cache cache;
 };
 
+void host1x_common_writel(struct host1x *host1x, u32 v, u32 r);
 void host1x_hypervisor_writel(struct host1x *host1x, u32 r, u32 v);
 u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r);
 void host1x_sync_writel(struct host1x *host1x, u32 r, u32 v);
-- 
GitLab


From 939179fab8ff42165c1e9a487495a3f2f3319e18 Mon Sep 17 00:00:00 2001
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: Mon, 27 Jun 2022 17:20:01 +0300
Subject: [PATCH 1693/1731] gpu: host1x: Program virtualization tables

Program virtualization tables specifying which VMs have access to which
Host1x hardware resources. Programming these has become mandatory in
Tegra234.

For now, since the driver does not operate as a Host1x hypervisor, we
basically allow access to everything to everyone.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/host1x/dev.c | 21 ++++++++++++++++++---
 drivers/gpu/host1x/dev.h |  8 ++++++++
 2 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 8c6ce8014c09d..5a57165ab0f6a 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -217,7 +217,7 @@ static const struct of_device_id host1x_of_match[] = {
 };
 MODULE_DEVICE_TABLE(of, host1x_of_match);
 
-static void host1x_setup_sid_table(struct host1x *host)
+static void host1x_setup_virtualization_tables(struct host1x *host)
 {
 	const struct host1x_info *info = host->info;
 	unsigned int i;
@@ -231,6 +231,21 @@ static void host1x_setup_sid_table(struct host1x *host)
 		host1x_hypervisor_writel(host, entry->offset, entry->base);
 		host1x_hypervisor_writel(host, entry->limit, entry->base + 4);
 	}
+
+	for (i = 0; i < info->streamid_vm_table.count; i++) {
+		/* Allow access to all stream IDs to all VMs. */
+		host1x_hypervisor_writel(host, 0xff, info->streamid_vm_table.base + 4 * i);
+	}
+
+	for (i = 0; i < info->classid_vm_table.count; i++) {
+		/* Allow access to all classes to all VMs. */
+		host1x_hypervisor_writel(host, 0xff, info->classid_vm_table.base + 4 * i);
+	}
+
+	for (i = 0; i < info->mmio_vm_table.count; i++) {
+		/* Use VM1 (that's us) as originator VMID for engine MMIO accesses. */
+		host1x_hypervisor_writel(host, 0x1, info->mmio_vm_table.base + 4 * i);
+	}
 }
 
 static bool host1x_wants_iommu(struct host1x *host1x)
@@ -602,7 +617,7 @@ static int __maybe_unused host1x_runtime_suspend(struct device *dev)
 	return 0;
 
 resume_host1x:
-	host1x_setup_sid_table(host);
+	host1x_setup_virtualization_tables(host);
 	host1x_syncpt_restore(host);
 	host1x_intr_start(host);
 
@@ -632,7 +647,7 @@ static int __maybe_unused host1x_runtime_resume(struct device *dev)
 		goto disable_clk;
 	}
 
-	host1x_setup_sid_table(host);
+	host1x_setup_virtualization_tables(host);
 	host1x_syncpt_restore(host);
 	host1x_intr_start(host);
 
diff --git a/drivers/gpu/host1x/dev.h b/drivers/gpu/host1x/dev.h
index 85edcc6e0fc7a..920e5548cfbca 100644
--- a/drivers/gpu/host1x/dev.h
+++ b/drivers/gpu/host1x/dev.h
@@ -90,6 +90,11 @@ struct host1x_sid_entry {
 	unsigned int limit;
 };
 
+struct host1x_table_desc {
+	unsigned int base;
+	unsigned int count;
+};
+
 struct host1x_info {
 	unsigned int nb_channels; /* host1x: number of channels supported */
 	unsigned int nb_pts; /* host1x: number of syncpoints supported */
@@ -103,6 +108,9 @@ struct host1x_info {
 	bool has_common; /* has common registers separate from hypervisor */
 	unsigned int num_sid_entries;
 	const struct host1x_sid_entry *sid_table;
+	struct host1x_table_desc streamid_vm_table;
+	struct host1x_table_desc classid_vm_table;
+	struct host1x_table_desc mmio_vm_table;
 	/*
 	 * On T20-T148, the boot chain may setup DC to increment syncpoints
 	 * 26/27 on VBLANK. As such we cannot use these syncpoints until
-- 
GitLab


From ee8f894f3fb326ac17b243441b8cbbb6fb0d0932 Mon Sep 17 00:00:00 2001
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: Mon, 27 Jun 2022 17:20:02 +0300
Subject: [PATCH 1694/1731] gpu: host1x: Allow reset to be missing

Host1x on Tegra234 does not have a software-controllable reset line.
As such, don't bail out if we don't find one in the device tree.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/host1x/dev.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 5a57165ab0f6a..c28939850bf69 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -423,9 +423,6 @@ static int host1x_get_resets(struct host1x *host)
 		return err;
 	}
 
-	if (WARN_ON(!host->resets[1].rstc))
-		return -ENOENT;
-
 	return 0;
 }
 
-- 
GitLab


From 7afd1194a3cdb7ba5aa8d658b2d0655f61457c86 Mon Sep 17 00:00:00 2001
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: Mon, 27 Jun 2022 17:20:03 +0300
Subject: [PATCH 1695/1731] gpu: host1x: Program interrupt destinations on
 Tegra234

On Tegra234, each Host1x VM has 8 interrupt lines. Each syncpoint
can be configured with which interrupt line should be used for
threshold interrupt, allowing for load balancing.

For now, to keep backwards compatibility, just set all syncpoints
to the first interrupt.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/host1x/hw/intr_hw.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/host1x/hw/intr_hw.c b/drivers/gpu/host1x/hw/intr_hw.c
index f56375ee6e718..9acccdb139e6e 100644
--- a/drivers/gpu/host1x/hw/intr_hw.c
+++ b/drivers/gpu/host1x/hw/intr_hw.c
@@ -76,6 +76,17 @@ static void intr_hw_init(struct host1x *host, u32 cpm)
 	/* update host clocks per usec */
 	host1x_sync_writel(host, cpm, HOST1X_SYNC_USEC_CLK);
 #endif
+#if HOST1X_HW >= 8
+	u32 id;
+
+	/*
+	 * Program threshold interrupt destination among 8 lines per VM,
+	 * per syncpoint. For now, just direct all to the first interrupt
+	 * line.
+	 */
+	for (id = 0; id < host->info->nb_pts; id++)
+		host1x_sync_writel(host, 0, HOST1X_SYNC_SYNCPT_INTR_DEST(id));
+#endif
 }
 
 static int
-- 
GitLab


From 9abdd497cd0ac08ed55aea30de1e46d73eef9fc5 Mon Sep 17 00:00:00 2001
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: Mon, 27 Jun 2022 17:20:04 +0300
Subject: [PATCH 1696/1731] gpu: host1x: Tegra234 device data and headers

Add device data and chip headers for Tegra234.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/host1x/Makefile                   |   3 +-
 drivers/gpu/host1x/dev.c                      |  42 ++++
 drivers/gpu/host1x/hw/host1x08.c              |  33 ++++
 drivers/gpu/host1x/hw/host1x08.h              |  15 ++
 drivers/gpu/host1x/hw/host1x08_hardware.h     |  21 ++
 drivers/gpu/host1x/hw/hw_host1x08_channel.h   |  11 ++
 drivers/gpu/host1x/hw/hw_host1x08_common.h    |   4 +
 .../gpu/host1x/hw/hw_host1x08_hypervisor.h    |   9 +
 drivers/gpu/host1x/hw/hw_host1x08_uclass.h    | 181 ++++++++++++++++++
 drivers/gpu/host1x/hw/hw_host1x08_vm.h        |  36 ++++
 10 files changed, 354 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/host1x/hw/host1x08.c
 create mode 100644 drivers/gpu/host1x/hw/host1x08.h
 create mode 100644 drivers/gpu/host1x/hw/host1x08_hardware.h
 create mode 100644 drivers/gpu/host1x/hw/hw_host1x08_channel.h
 create mode 100644 drivers/gpu/host1x/hw/hw_host1x08_common.h
 create mode 100644 drivers/gpu/host1x/hw/hw_host1x08_hypervisor.h
 create mode 100644 drivers/gpu/host1x/hw/hw_host1x08_uclass.h
 create mode 100644 drivers/gpu/host1x/hw/hw_host1x08_vm.h

diff --git a/drivers/gpu/host1x/Makefile b/drivers/gpu/host1x/Makefile
index 28f7aaedce0ff..ee5286ffe08d5 100644
--- a/drivers/gpu/host1x/Makefile
+++ b/drivers/gpu/host1x/Makefile
@@ -15,7 +15,8 @@ host1x-y = \
 	hw/host1x04.o \
 	hw/host1x05.o \
 	hw/host1x06.o \
-	hw/host1x07.o
+	hw/host1x07.o \
+	hw/host1x08.o
 
 host1x-$(CONFIG_IOMMU_API) += \
 	context.o
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index c28939850bf69..0cd3f97e7e49f 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -39,6 +39,7 @@
 #include "hw/host1x05.h"
 #include "hw/host1x06.h"
 #include "hw/host1x07.h"
+#include "hw/host1x08.h"
 
 void host1x_common_writel(struct host1x *host1x, u32 v, u32 r)
 {
@@ -205,7 +206,48 @@ static const struct host1x_info host1x07_info = {
 	.reserve_vblank_syncpts = false,
 };
 
+/*
+ * Tegra234 has two stream ID protection tables, one for setting stream IDs
+ * through the channel path via SETSTREAMID, and one for setting them via
+ * MMIO. We program each engine's data stream ID in the channel path table
+ * and firmware stream ID in the MMIO path table.
+ */
+static const struct host1x_sid_entry tegra234_sid_table[] = {
+	{
+		/* VIC channel */
+		.base = 0x17b8,
+		.offset = 0x30,
+		.limit = 0x30
+	},
+	{
+		/* VIC MMIO */
+		.base = 0x1688,
+		.offset = 0x34,
+		.limit = 0x34
+	},
+};
+
+static const struct host1x_info host1x08_info = {
+	.nb_channels = 63,
+	.nb_pts = 1024,
+	.nb_mlocks = 24,
+	.nb_bases = 0,
+	.init = host1x08_init,
+	.sync_offset = 0x0,
+	.dma_mask = DMA_BIT_MASK(40),
+	.has_wide_gather = true,
+	.has_hypervisor = true,
+	.has_common = true,
+	.num_sid_entries = ARRAY_SIZE(tegra234_sid_table),
+	.sid_table = tegra234_sid_table,
+	.streamid_vm_table = { 0x1004, 128 },
+	.classid_vm_table = { 0x1404, 25 },
+	.mmio_vm_table = { 0x1504, 25 },
+	.reserve_vblank_syncpts = false,
+};
+
 static const struct of_device_id host1x_of_match[] = {
+	{ .compatible = "nvidia,tegra234-host1x", .data = &host1x08_info, },
 	{ .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, },
 	{ .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },
 	{ .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
diff --git a/drivers/gpu/host1x/hw/host1x08.c b/drivers/gpu/host1x/hw/host1x08.c
new file mode 100644
index 0000000000000..754890c34c740
--- /dev/null
+++ b/drivers/gpu/host1x/hw/host1x08.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Host1x init for Tegra234 SoCs
+ *
+ * Copyright (c) 2022 NVIDIA Corporation.
+ */
+
+/* include hw specification */
+#include "host1x08.h"
+#include "host1x08_hardware.h"
+
+/* include code */
+#define HOST1X_HW 8
+
+#include "cdma_hw.c"
+#include "channel_hw.c"
+#include "debug_hw.c"
+#include "intr_hw.c"
+#include "syncpt_hw.c"
+
+#include "../dev.h"
+
+int host1x08_init(struct host1x *host)
+{
+	host->channel_op = &host1x_channel_ops;
+	host->cdma_op = &host1x_cdma_ops;
+	host->cdma_pb_op = &host1x_pushbuffer_ops;
+	host->syncpt_op = &host1x_syncpt_ops;
+	host->intr_op = &host1x_intr_ops;
+	host->debug_op = &host1x_debug_ops;
+
+	return 0;
+}
diff --git a/drivers/gpu/host1x/hw/host1x08.h b/drivers/gpu/host1x/hw/host1x08.h
new file mode 100644
index 0000000000000..a6bad56e44cfb
--- /dev/null
+++ b/drivers/gpu/host1x/hw/host1x08.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Host1x init for Tegra234 SoCs
+ *
+ * Copyright (c) 2018 NVIDIA Corporation.
+ */
+
+#ifndef HOST1X_HOST1X08_H
+#define HOST1X_HOST1X08_H
+
+struct host1x;
+
+int host1x08_init(struct host1x *host);
+
+#endif
diff --git a/drivers/gpu/host1x/hw/host1x08_hardware.h b/drivers/gpu/host1x/hw/host1x08_hardware.h
new file mode 100644
index 0000000000000..936243060bff6
--- /dev/null
+++ b/drivers/gpu/host1x/hw/host1x08_hardware.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Tegra host1x Register Offsets for Tegra234
+ *
+ * Copyright (c) 2022 NVIDIA Corporation.
+ */
+
+#ifndef __HOST1X_HOST1X08_HARDWARE_H
+#define __HOST1X_HOST1X08_HARDWARE_H
+
+#include <linux/types.h>
+#include <linux/bitops.h>
+
+#include "hw_host1x08_uclass.h"
+#include "hw_host1x08_vm.h"
+#include "hw_host1x08_hypervisor.h"
+#include "hw_host1x08_common.h"
+
+#include "opcodes.h"
+
+#endif
diff --git a/drivers/gpu/host1x/hw/hw_host1x08_channel.h b/drivers/gpu/host1x/hw/hw_host1x08_channel.h
new file mode 100644
index 0000000000000..c9272d2ab14af
--- /dev/null
+++ b/drivers/gpu/host1x/hw/hw_host1x08_channel.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 NVIDIA Corporation.
+ */
+
+#ifndef HOST1X_HW_HOST1X08_CHANNEL_H
+#define HOST1X_HW_HOST1X08_CHANNEL_H
+
+#define HOST1X_CHANNEL_SMMU_STREAMID 0x084
+
+#endif
diff --git a/drivers/gpu/host1x/hw/hw_host1x08_common.h b/drivers/gpu/host1x/hw/hw_host1x08_common.h
new file mode 100644
index 0000000000000..4df28440b86b7
--- /dev/null
+++ b/drivers/gpu/host1x/hw/hw_host1x08_common.h
@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 NVIDIA Corporation.
+ */
diff --git a/drivers/gpu/host1x/hw/hw_host1x08_hypervisor.h b/drivers/gpu/host1x/hw/hw_host1x08_hypervisor.h
new file mode 100644
index 0000000000000..22964324c914b
--- /dev/null
+++ b/drivers/gpu/host1x/hw/hw_host1x08_hypervisor.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 NVIDIA Corporation.
+ */
+
+#define HOST1X_HV_SYNCPT_PROT_EN			0x1724
+#define HOST1X_HV_SYNCPT_PROT_EN_CH_EN			BIT(1)
+#define HOST1X_HV_CH_MLOCK_EN(x)			(0x1700 + (x * 4))
+#define HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(x)		(0x1710 + (x * 4))
diff --git a/drivers/gpu/host1x/hw/hw_host1x08_uclass.h b/drivers/gpu/host1x/hw/hw_host1x08_uclass.h
new file mode 100644
index 0000000000000..724cccd71aa1a
--- /dev/null
+++ b/drivers/gpu/host1x/hw/hw_host1x08_uclass.h
@@ -0,0 +1,181 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2018 NVIDIA Corporation.
+ */
+
+ /*
+  * Function naming determines intended use:
+  *
+  *     <x>_r(void) : Returns the offset for register <x>.
+  *
+  *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+  *
+  *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+  *
+  *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+  *         and masked to place it at field <y> of register <x>.  This value
+  *         can be |'d with others to produce a full register value for
+  *         register <x>.
+  *
+  *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+  *         value can be ~'d and then &'d to clear the value of field <y> for
+  *         register <x>.
+  *
+  *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+  *         to place it at field <y> of register <x>.  This value can be |'d
+  *         with others to produce a full register value for <x>.
+  *
+  *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+  *         <x> value 'r' after being shifted to place its LSB at bit 0.
+  *         This value is suitable for direct comparison with other unshifted
+  *         values appropriate for use in field <y> of register <x>.
+  *
+  *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+  *         field <y> of register <x>.  This value is suitable for direct
+  *         comparison with unshifted values appropriate for use in field <y>
+  *         of register <x>.
+  */
+
+#ifndef HOST1X_HW_HOST1X08_UCLASS_H
+#define HOST1X_HW_HOST1X08_UCLASS_H
+
+static inline u32 host1x_uclass_incr_syncpt_r(void)
+{
+	return 0x0;
+}
+#define HOST1X_UCLASS_INCR_SYNCPT \
+	host1x_uclass_incr_syncpt_r()
+static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
+{
+	return (v & 0xff) << 10;
+}
+#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
+	host1x_uclass_incr_syncpt_cond_f(v)
+static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+#define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
+	host1x_uclass_incr_syncpt_indx_f(v)
+static inline u32 host1x_uclass_wait_syncpt_r(void)
+{
+	return 0x8;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT \
+	host1x_uclass_wait_syncpt_r()
+static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
+{
+	return (v & 0xff) << 24;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
+	host1x_uclass_wait_syncpt_indx_f(v)
+static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
+{
+	return (v & 0xffffff) << 0;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
+	host1x_uclass_wait_syncpt_thresh_f(v)
+static inline u32 host1x_uclass_wait_syncpt_base_r(void)
+{
+	return 0x9;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_BASE \
+	host1x_uclass_wait_syncpt_base_r()
+static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
+{
+	return (v & 0xff) << 24;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
+	host1x_uclass_wait_syncpt_base_indx_f(v)
+static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
+{
+	return (v & 0xff) << 16;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
+	host1x_uclass_wait_syncpt_base_base_indx_f(v)
+static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
+{
+	return (v & 0xffff) << 0;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
+	host1x_uclass_wait_syncpt_base_offset_f(v)
+static inline u32 host1x_uclass_load_syncpt_base_r(void)
+{
+	return 0xb;
+}
+#define HOST1X_UCLASS_LOAD_SYNCPT_BASE \
+	host1x_uclass_load_syncpt_base_r()
+static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
+{
+	return (v & 0xff) << 24;
+}
+#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
+	host1x_uclass_load_syncpt_base_base_indx_f(v)
+static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
+{
+	return (v & 0xffffff) << 0;
+}
+#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
+	host1x_uclass_load_syncpt_base_value_f(v)
+static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
+{
+	return (v & 0xff) << 24;
+}
+#define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
+	host1x_uclass_incr_syncpt_base_base_indx_f(v)
+static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
+{
+	return (v & 0xffffff) << 0;
+}
+#define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
+	host1x_uclass_incr_syncpt_base_offset_f(v)
+static inline u32 host1x_uclass_indoff_r(void)
+{
+	return 0x2d;
+}
+#define HOST1X_UCLASS_INDOFF \
+	host1x_uclass_indoff_r()
+static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
+{
+	return (v & 0xf) << 28;
+}
+#define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
+	host1x_uclass_indoff_indbe_f(v)
+static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
+{
+	return (v & 0x1) << 27;
+}
+#define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
+	host1x_uclass_indoff_autoinc_f(v)
+static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
+{
+	return (v & 0xff) << 18;
+}
+#define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
+	host1x_uclass_indoff_indmodid_f(v)
+static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
+{
+	return (v & 0xffff) << 2;
+}
+#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
+	host1x_uclass_indoff_indroffset_f(v)
+static inline u32 host1x_uclass_indoff_rwn_read_v(void)
+{
+	return 1;
+}
+#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
+	host1x_uclass_indoff_indroffset_f(v)
+static inline u32 host1x_uclass_load_syncpt_payload_32_r(void)
+{
+	return 0x4e;
+}
+#define HOST1X_UCLASS_LOAD_SYNCPT_PAYLOAD_32 \
+	host1x_uclass_load_syncpt_payload_32_r()
+static inline u32 host1x_uclass_wait_syncpt_32_r(void)
+{
+	return 0x50;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_32 \
+	host1x_uclass_wait_syncpt_32_r()
+
+#endif
diff --git a/drivers/gpu/host1x/hw/hw_host1x08_vm.h b/drivers/gpu/host1x/hw/hw_host1x08_vm.h
new file mode 100644
index 0000000000000..1455a4670bf85
--- /dev/null
+++ b/drivers/gpu/host1x/hw/hw_host1x08_vm.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 NVIDIA Corporation.
+ */
+
+#define HOST1X_CHANNEL_DMASTART				0x0000
+#define HOST1X_CHANNEL_DMASTART_HI			0x0004
+#define HOST1X_CHANNEL_DMAPUT				0x0008
+#define HOST1X_CHANNEL_DMAPUT_HI			0x000c
+#define HOST1X_CHANNEL_DMAGET				0x0010
+#define HOST1X_CHANNEL_DMAGET_HI			0x0014
+#define HOST1X_CHANNEL_DMAEND				0x0018
+#define HOST1X_CHANNEL_DMAEND_HI			0x001c
+#define HOST1X_CHANNEL_DMACTRL				0x0020
+#define HOST1X_CHANNEL_DMACTRL_DMASTOP			BIT(0)
+#define HOST1X_CHANNEL_DMACTRL_DMAGETRST		BIT(1)
+#define HOST1X_CHANNEL_DMACTRL_DMAINITGET		BIT(2)
+#define HOST1X_CHANNEL_CMDFIFO_STAT			0x0024
+#define HOST1X_CHANNEL_CMDFIFO_STAT_EMPTY		BIT(13)
+#define HOST1X_CHANNEL_CMDFIFO_RDATA			0x0028
+#define HOST1X_CHANNEL_CMDP_OFFSET			0x0030
+#define HOST1X_CHANNEL_CMDP_CLASS			0x0034
+#define HOST1X_CHANNEL_CHANNELSTAT			0x0038
+#define HOST1X_CHANNEL_CMDPROC_STOP			0x0048
+#define HOST1X_CHANNEL_TEARDOWN				0x004c
+#define HOST1X_CHANNEL_SMMU_STREAMID			0x0084
+
+#define HOST1X_SYNC_SYNCPT_CPU_INCR(x)			(0x6400 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(x)	(0x6600 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_INTR_DEST(x)			(0x6684 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(x)	(0x770c + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(x)	(0x7790 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT(x)				(0x8080 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_INT_THRESH(x)		(0xa088 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_CH_APP(x)			(0xb090 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_CH_APP_CH(v)			(((v) & 0x3f) << 8)
-- 
GitLab


From 1411796f200de86d037578752450a9853359670c Mon Sep 17 00:00:00 2001
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: Mon, 27 Jun 2022 17:20:05 +0300
Subject: [PATCH 1697/1731] gpu: host1x: Rewrite job opcode sequence

For new (Tegra186+) SoCs, use a new ('full-featured') job opcode
sequence that is compatible with virtualization. In particular,
the Host1x hardware in Tegra234 is more strict regarding the sequence,
requiring ACQUIRE_MLOCK-SETCLASS-SETSTREAMID opcodes to occur in
that sequence without gaps (except for SETPAYLOAD), so let's do it
properly in one go now.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/host1x/hw/channel_hw.c | 144 +++++++++++++++++------------
 1 file changed, 85 insertions(+), 59 deletions(-)

diff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw/channel_hw.c
index f84caf06621ab..4eb7fb2e4f0a2 100644
--- a/drivers/gpu/host1x/hw/channel_hw.c
+++ b/drivers/gpu/host1x/hw/channel_hw.c
@@ -47,10 +47,41 @@ static void trace_write_gather(struct host1x_cdma *cdma, struct host1x_bo *bo,
 	}
 }
 
-static void submit_wait(struct host1x_cdma *cdma, u32 id, u32 threshold,
+static void submit_wait(struct host1x_job *job, u32 id, u32 threshold,
 			u32 next_class)
 {
-#if HOST1X_HW >= 2
+	struct host1x_cdma *cdma = &job->channel->cdma;
+
+#if HOST1X_HW >= 6
+	u32 stream_id;
+
+	/*
+	 * If a memory context has been set, use it. Otherwise
+	 * (if context isolation is disabled) use the engine's
+	 * firmware stream ID.
+	 */
+	if (job->memory_context)
+		stream_id = job->memory_context->stream_id;
+	else
+		stream_id = job->engine_fallback_streamid;
+
+	host1x_cdma_push_wide(cdma,
+		host1x_opcode_setclass(
+			HOST1X_CLASS_HOST1X,
+			HOST1X_UCLASS_LOAD_SYNCPT_PAYLOAD_32,
+			/* WAIT_SYNCPT_32 is at SYNCPT_PAYLOAD_32+2 */
+			BIT(0) | BIT(2)
+		),
+		threshold,
+		id,
+		HOST1X_OPCODE_NOP
+	);
+	host1x_cdma_push_wide(&job->channel->cdma,
+		host1x_opcode_setclass(job->class, 0, 0),
+		host1x_opcode_setpayload(stream_id),
+		host1x_opcode_setstreamid(job->engine_streamid_offset / 4),
+		HOST1X_OPCODE_NOP);
+#elif HOST1X_HW >= 2
 	host1x_cdma_push_wide(cdma,
 		host1x_opcode_setclass(
 			HOST1X_CLASS_HOST1X,
@@ -97,7 +128,7 @@ static void submit_gathers(struct host1x_job *job, u32 job_syncpt_base)
 			else
 				threshold = cmd->wait.threshold;
 
-			submit_wait(cdma, cmd->wait.id, threshold, cmd->wait.next_class);
+			submit_wait(job, cmd->wait.id, threshold, cmd->wait.next_class);
 		} else {
 			struct host1x_job_gather *g = &cmd->gather;
 
@@ -180,42 +211,70 @@ static void host1x_enable_gather_filter(struct host1x_channel *ch)
 #endif
 }
 
-static void host1x_channel_program_engine_streamid(struct host1x_job *job)
+static void channel_program_cdma(struct host1x_job *job)
 {
+	struct host1x_cdma *cdma = &job->channel->cdma;
+	struct host1x_syncpt *sp = job->syncpt;
+
 #if HOST1X_HW >= 6
 	u32 fence;
 
-	if (!job->memory_context)
-		return;
+	/* Enter engine class with invalid stream ID. */
+	host1x_cdma_push_wide(cdma,
+		host1x_opcode_acquire_mlock(job->class),
+		host1x_opcode_setclass(job->class, 0, 0),
+		host1x_opcode_setpayload(0),
+		host1x_opcode_setstreamid(job->engine_streamid_offset / 4));
 
-	fence = host1x_syncpt_incr_max(job->syncpt, 1);
+	/* Before switching stream ID to real stream ID, ensure engine is idle. */
+	fence = host1x_syncpt_incr_max(sp, 1);
+	host1x_cdma_push(&job->channel->cdma,
+		host1x_opcode_nonincr(HOST1X_UCLASS_INCR_SYNCPT, 1),
+		HOST1X_UCLASS_INCR_SYNCPT_INDX_F(job->syncpt->id) |
+			HOST1X_UCLASS_INCR_SYNCPT_COND_F(4));
+	submit_wait(job, job->syncpt->id, fence, job->class);
 
-	/* First, increment a syncpoint on OP_DONE condition.. */
+	/* Submit work. */
+	job->syncpt_end = host1x_syncpt_incr_max(sp, job->syncpt_incrs);
+	submit_gathers(job, job->syncpt_end - job->syncpt_incrs);
 
+	/* Before releasing MLOCK, ensure engine is idle again. */
+	fence = host1x_syncpt_incr_max(sp, 1);
 	host1x_cdma_push(&job->channel->cdma,
 		host1x_opcode_nonincr(HOST1X_UCLASS_INCR_SYNCPT, 1),
 		HOST1X_UCLASS_INCR_SYNCPT_INDX_F(job->syncpt->id) |
-			HOST1X_UCLASS_INCR_SYNCPT_COND_F(1));
+			HOST1X_UCLASS_INCR_SYNCPT_COND_F(4));
+	submit_wait(job, job->syncpt->id, fence, job->class);
 
-	/* Wait for syncpoint to increment */
+	/* Release MLOCK. */
+	host1x_cdma_push(cdma,
+		HOST1X_OPCODE_NOP, host1x_opcode_release_mlock(job->class));
+#else
+	if (job->serialize) {
+		/*
+		 * Force serialization by inserting a host wait for the
+		 * previous job to finish before this one can commence.
+		 */
+		host1x_cdma_push(cdma,
+				 host1x_opcode_setclass(HOST1X_CLASS_HOST1X,
+					host1x_uclass_wait_syncpt_r(), 1),
+				 host1x_class_host_wait_syncpt(job->syncpt->id,
+					host1x_syncpt_read_max(sp)));
+	}
 
-	host1x_cdma_push(&job->channel->cdma,
-		host1x_opcode_setclass(HOST1X_CLASS_HOST1X,
-			host1x_uclass_wait_syncpt_r(), 1),
-		host1x_class_host_wait_syncpt(job->syncpt->id, fence));
+	/* Synchronize base register to allow using it for relative waiting */
+	if (sp->base)
+		synchronize_syncpt_base(job);
 
-	/*
-	 * Now that we know the engine is idle, return to class and
-	 * change stream ID.
-	 */
+	/* add a setclass for modules that require it */
+	if (job->class)
+		host1x_cdma_push(cdma,
+				 host1x_opcode_setclass(job->class, 0, 0),
+				 HOST1X_OPCODE_NOP);
 
-	host1x_cdma_push(&job->channel->cdma,
-		host1x_opcode_setclass(job->class, 0, 0),
-		HOST1X_OPCODE_NOP);
+	job->syncpt_end = host1x_syncpt_incr_max(sp, job->syncpt_incrs);
 
-	host1x_cdma_push(&job->channel->cdma,
-		host1x_opcode_setpayload(job->memory_context->stream_id),
-		host1x_opcode_setstreamid(job->engine_streamid_offset / 4));
+	submit_gathers(job, job->syncpt_end - job->syncpt_incrs);
 #endif
 }
 
@@ -223,7 +282,6 @@ static int channel_submit(struct host1x_job *job)
 {
 	struct host1x_channel *ch = job->channel;
 	struct host1x_syncpt *sp = job->syncpt;
-	u32 user_syncpt_incrs = job->syncpt_incrs;
 	u32 prev_max = 0;
 	u32 syncval;
 	int err;
@@ -251,6 +309,7 @@ static int channel_submit(struct host1x_job *job)
 
 	host1x_channel_set_streamid(ch);
 	host1x_enable_gather_filter(ch);
+	host1x_hw_syncpt_assign_to_channel(host, sp, ch);
 
 	/* begin a CDMA submit */
 	err = host1x_cdma_begin(&ch->cdma, job);
@@ -259,40 +318,7 @@ static int channel_submit(struct host1x_job *job)
 		goto error;
 	}
 
-	if (job->serialize) {
-		/*
-		 * Force serialization by inserting a host wait for the
-		 * previous job to finish before this one can commence.
-		 */
-		host1x_cdma_push(&ch->cdma,
-				 host1x_opcode_setclass(HOST1X_CLASS_HOST1X,
-					host1x_uclass_wait_syncpt_r(), 1),
-				 host1x_class_host_wait_syncpt(job->syncpt->id,
-					host1x_syncpt_read_max(sp)));
-	}
-
-	/* Synchronize base register to allow using it for relative waiting */
-	if (sp->base)
-		synchronize_syncpt_base(job);
-
-	host1x_hw_syncpt_assign_to_channel(host, sp, ch);
-
-	/* add a setclass for modules that require it */
-	if (job->class)
-		host1x_cdma_push(&ch->cdma,
-				 host1x_opcode_setclass(job->class, 0, 0),
-				 HOST1X_OPCODE_NOP);
-
-	/*
-	 * Ensure engine DMA is idle and set new stream ID. May increment
-	 * syncpt max.
-	 */
-	host1x_channel_program_engine_streamid(job);
-
-	syncval = host1x_syncpt_incr_max(sp, user_syncpt_incrs);
-	job->syncpt_end = syncval;
-
-	submit_gathers(job, syncval - user_syncpt_incrs);
+	channel_program_cdma(job);
 
 	/* end CDMA submit & stash pinned hMems into sync queue */
 	host1x_cdma_end(&ch->cdma, job);
-- 
GitLab


From a94b8a77bc914db6556e8019cf23d9dda9ab907e Mon Sep 17 00:00:00 2001
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: Mon, 27 Jun 2022 17:20:06 +0300
Subject: [PATCH 1698/1731] gpu: host1x: Add MLOCK release code on Tegra234

With the full-featured opcode sequence using MLOCKs, we need to also
unlock those MLOCKs in the event of a timeout. However, it turns out
that on Tegra186/Tegra194, by default, we don't need to do this;
furthermore, on Tegra234 it is much simpler to do; so only implement
this on Tegra234 for the time being.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/host1x/hw/cdma_hw.c            | 34 ++++++++++++++++++++++
 drivers/gpu/host1x/hw/hw_host1x08_common.h |  7 +++++
 2 files changed, 41 insertions(+)

diff --git a/drivers/gpu/host1x/hw/cdma_hw.c b/drivers/gpu/host1x/hw/cdma_hw.c
index e49cd5b8f7354..1b65a10b9dfcf 100644
--- a/drivers/gpu/host1x/hw/cdma_hw.c
+++ b/drivers/gpu/host1x/hw/cdma_hw.c
@@ -238,6 +238,37 @@ static void cdma_resume(struct host1x_cdma *cdma, u32 getptr)
 	cdma_timeout_restart(cdma, getptr);
 }
 
+static void timeout_release_mlock(struct host1x_cdma *cdma)
+{
+#if HOST1X_HW >= 8
+	/* Tegra186 and Tegra194 require a more complicated MLOCK release
+	 * sequence. Furthermore, those chips by default don't enforce MLOCKs,
+	 * so it turns out that if we don't /actually/ need MLOCKs, we can just
+	 * ignore them.
+	 *
+	 * As such, for now just implement this on Tegra234 where things are
+	 * stricter but also easy to implement.
+	 */
+	struct host1x_channel *ch = cdma_to_channel(cdma);
+	struct host1x *host1x = cdma_to_host1x(cdma);
+	u32 offset;
+
+	switch (ch->client->class) {
+	case HOST1X_CLASS_VIC:
+		offset = HOST1X_COMMON_VIC_MLOCK;
+		break;
+	case HOST1X_CLASS_NVDEC:
+		offset = HOST1X_COMMON_NVDEC_MLOCK;
+		break;
+	default:
+		WARN(1, "%s was not updated for class %u", __func__, ch->client->class);
+		return;
+	}
+
+	host1x_common_writel(host1x, 0x0, offset);
+#endif
+}
+
 /*
  * If this timeout fires, it indicates the current sync_queue entry has
  * exceeded its TTL and the userctx should be timed out and remaining
@@ -288,6 +319,9 @@ static void cdma_timeout_handler(struct work_struct *work)
 	/* stop HW, resetting channel/module */
 	host1x_hw_cdma_freeze(host1x, cdma);
 
+	/* release any held MLOCK */
+	timeout_release_mlock(cdma);
+
 	host1x_cdma_update_sync_queue(cdma, ch->dev);
 	mutex_unlock(&cdma->lock);
 }
diff --git a/drivers/gpu/host1x/hw/hw_host1x08_common.h b/drivers/gpu/host1x/hw/hw_host1x08_common.h
index 4df28440b86b7..8e0c99150ec2c 100644
--- a/drivers/gpu/host1x/hw/hw_host1x08_common.h
+++ b/drivers/gpu/host1x/hw/hw_host1x08_common.h
@@ -2,3 +2,10 @@
 /*
  * Copyright (c) 2022 NVIDIA Corporation.
  */
+
+#define HOST1X_COMMON_OFA_MLOCK			0x4050
+#define HOST1X_COMMON_NVJPG1_MLOCK		0x4070
+#define HOST1X_COMMON_VIC_MLOCK			0x4078
+#define HOST1X_COMMON_NVENC_MLOCK		0x407c
+#define HOST1X_COMMON_NVDEC_MLOCK		0x4080
+#define HOST1X_COMMON_NVJPG_MLOCK		0x4084
-- 
GitLab


From 0ae4ae9158f32fd77e8736da0585d8aff5a3b9d9 Mon Sep 17 00:00:00 2001
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: Mon, 27 Jun 2022 17:20:07 +0300
Subject: [PATCH 1699/1731] gpu: host1x: Use RESTART_W to skip timed out jobs
 on Tegra186+

When MLOCK enforcement is enabled, the 0-word write currently done
is rejected by the hardware outside of an MLOCK region. As such,
on these chips, which also have the newer, more convenient RESTART_W
opcode, use that instead to skip over the timed out job.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/host1x/cdma.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/host1x/cdma.c b/drivers/gpu/host1x/cdma.c
index 765e5aa64eb68..bb1f3c746be47 100644
--- a/drivers/gpu/host1x/cdma.c
+++ b/drivers/gpu/host1x/cdma.c
@@ -457,9 +457,24 @@ syncpt_incr:
 				 * to offset 0xbad. This does nothing but
 				 * has a easily detected signature in debug
 				 * traces.
+				 *
+				 * On systems with MLOCK enforcement enabled,
+				 * the above 0 word writes would fall foul of
+				 * the enforcement. As such, in the first slot
+				 * put a RESTART_W opcode to the beginning
+				 * of the next job. We don't use this for older
+				 * chips since those only support the RESTART
+				 * opcode with inconvenient alignment requirements.
 				 */
-				mapped[2*slot+0] = 0x1bad0000;
-				mapped[2*slot+1] = 0x1bad0000;
+				if (i == 0 && host1x->info->has_wide_gather) {
+					unsigned int next_job = (job->first_get/8 + job->num_slots)
+						% HOST1X_PUSHBUFFER_SLOTS;
+					mapped[2*slot+0] = (0xd << 28) | (next_job * 2);
+					mapped[2*slot+1] = 0x0;
+				} else {
+					mapped[2*slot+0] = 0x1bad0000;
+					mapped[2*slot+1] = 0x1bad0000;
+				}
 			}
 
 			job->cancelled = true;
-- 
GitLab


From 9550669c197510b9f994102280da7fc0ab468d05 Mon Sep 17 00:00:00 2001
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: Mon, 27 Jun 2022 17:20:08 +0300
Subject: [PATCH 1700/1731] drm/tegra: vic: Add Tegra234 support

Add Tegra234 support for VIC. It is backwards compatible with
Tegra194.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/drm/tegra/drm.c |  1 +
 drivers/gpu/drm/tegra/vic.c | 12 ++++++++++++
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 9464f522e2575..426ffeb51f722 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -1380,6 +1380,7 @@ static const struct of_device_id host1x_drm_subdevs[] = {
 	{ .compatible = "nvidia,tegra194-sor", },
 	{ .compatible = "nvidia,tegra194-vic", },
 	{ .compatible = "nvidia,tegra194-nvdec", },
+	{ .compatible = "nvidia,tegra234-vic", },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c
index c5526bda88d66..c1734f823d043 100644
--- a/drivers/gpu/drm/tegra/vic.c
+++ b/drivers/gpu/drm/tegra/vic.c
@@ -447,11 +447,20 @@ static const struct vic_config vic_t194_config = {
 	.supports_sid = true,
 };
 
+#define NVIDIA_TEGRA_234_VIC_FIRMWARE "nvidia/tegra234/vic.bin"
+
+static const struct vic_config vic_t234_config = {
+	.firmware = NVIDIA_TEGRA_234_VIC_FIRMWARE,
+	.version = 0x23,
+	.supports_sid = true,
+};
+
 static const struct of_device_id tegra_vic_of_match[] = {
 	{ .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config },
 	{ .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config },
 	{ .compatible = "nvidia,tegra186-vic", .data = &vic_t186_config },
 	{ .compatible = "nvidia,tegra194-vic", .data = &vic_t194_config },
+	{ .compatible = "nvidia,tegra234-vic", .data = &vic_t234_config },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, tegra_vic_of_match);
@@ -590,3 +599,6 @@ MODULE_FIRMWARE(NVIDIA_TEGRA_186_VIC_FIRMWARE);
 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
 MODULE_FIRMWARE(NVIDIA_TEGRA_194_VIC_FIRMWARE);
 #endif
+#if IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)
+MODULE_FIRMWARE(NVIDIA_TEGRA_234_VIC_FIRMWARE);
+#endif
-- 
GitLab


From f99e689181ea8ede795f2fcd8d658207920469dd Mon Sep 17 00:00:00 2001
From: Robin Murphy <robin.murphy@arm.com>
Date: Thu, 7 Jul 2022 18:30:44 +0100
Subject: [PATCH 1701/1731] gpu: host1x: Register context bus unconditionally

Conditional registration is a problem for other subsystems which may
unwittingly try to interact with host1x_context_device_bus_type in an
uninitialised state on non-Tegra platforms. A look under /sys/bus on a
typical system already reveals plenty of entries from enabled but
otherwise irrelevant configs, so lets keep things simple and register
our context bus unconditionally too.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/host1x/context_bus.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/host1x/context_bus.c b/drivers/gpu/host1x/context_bus.c
index b0d35b2bbe895..d9421179d7b43 100644
--- a/drivers/gpu/host1x/context_bus.c
+++ b/drivers/gpu/host1x/context_bus.c
@@ -15,11 +15,6 @@ static int __init host1x_context_device_bus_init(void)
 {
 	int err;
 
-	if (!of_machine_is_compatible("nvidia,tegra186") &&
-	    !of_machine_is_compatible("nvidia,tegra194") &&
-	    !of_machine_is_compatible("nvidia,tegra234"))
-		return 0;
-
 	err = bus_register(&host1x_context_device_bus_type);
 	if (err < 0) {
 		pr_err("bus type registration failed: %d\n", err);
-- 
GitLab


From b5d5288a46876f6767950449aea310f71ac86277 Mon Sep 17 00:00:00 2001
From: YueHaibing <yuehaibing@huawei.com>
Date: Sat, 5 Mar 2022 20:32:00 +0800
Subject: [PATCH 1702/1731] drm/tegra: vic: Fix build warning when CONFIG_PM=n
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

drivers/gpu/drm/tegra/vic.c:326:12: error: ‘vic_runtime_suspend’ defined but not used [-Werror=unused-function]
 static int vic_runtime_suspend(struct device *dev)
            ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/tegra/vic.c:292:12: error: ‘vic_runtime_resume’ defined but not used [-Werror=unused-function]
 static int vic_runtime_resume(struct device *dev)
            ^~~~~~~~~~~~~~~~~~

Mark it as __maybe_unused.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/drm/tegra/vic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c
index c1734f823d043..b14b84494be0a 100644
--- a/drivers/gpu/drm/tegra/vic.c
+++ b/drivers/gpu/drm/tegra/vic.c
@@ -323,7 +323,7 @@ cleanup:
 }
 
 
-static int vic_runtime_resume(struct device *dev)
+static int __maybe_unused vic_runtime_resume(struct device *dev)
 {
 	struct vic *vic = dev_get_drvdata(dev);
 	int err;
@@ -357,7 +357,7 @@ disable:
 	return err;
 }
 
-static int vic_runtime_suspend(struct device *dev)
+static int __maybe_unused vic_runtime_suspend(struct device *dev)
 {
 	struct vic *vic = dev_get_drvdata(dev);
 	int err;
-- 
GitLab


From c7860cbee9989882d2908682526a5ef617523cfe Mon Sep 17 00:00:00 2001
From: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Date: Wed, 29 Jun 2022 01:42:39 +0300
Subject: [PATCH 1703/1731] drm/tegra: Fix vmapping of prime buffers

The code assumes that Tegra GEM is permanently vmapped, which is not
true for the scattered buffers. After converting Tegra video decoder
driver to V4L API, we're now getting a BUG_ON from dma-buf core on playing
video using libvdpau-tegra on T30+ because tegra_gem_prime_vmap() sets
vaddr to NULL. Older pre-V4L video decoder driver wasn't vmapping dma-bufs.
Fix it by actually vmapping the exported GEMs.

Cc: stable@vger.kernel.org
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/drm/tegra/gem.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/tegra/gem.c b/drivers/gpu/drm/tegra/gem.c
index 7c7dd84e6db84..81991090adcc9 100644
--- a/drivers/gpu/drm/tegra/gem.c
+++ b/drivers/gpu/drm/tegra/gem.c
@@ -704,14 +704,23 @@ static int tegra_gem_prime_vmap(struct dma_buf *buf, struct iosys_map *map)
 {
 	struct drm_gem_object *gem = buf->priv;
 	struct tegra_bo *bo = to_tegra_bo(gem);
+	void *vaddr;
 
-	iosys_map_set_vaddr(map, bo->vaddr);
+	vaddr = tegra_bo_mmap(&bo->base);
+	if (IS_ERR(vaddr))
+		return PTR_ERR(vaddr);
+
+	iosys_map_set_vaddr(map, vaddr);
 
 	return 0;
 }
 
 static void tegra_gem_prime_vunmap(struct dma_buf *buf, struct iosys_map *map)
 {
+	struct drm_gem_object *gem = buf->priv;
+	struct tegra_bo *bo = to_tegra_bo(gem);
+
+	tegra_bo_munmap(&bo->base, map->vaddr);
 }
 
 static const struct dma_buf_ops tegra_gem_prime_dmabuf_ops = {
-- 
GitLab


From 7ac1a36a9823a573ad23ece58007a74b8089fe16 Mon Sep 17 00:00:00 2001
From: Robin Murphy <robin.murphy@arm.com>
Date: Mon, 11 Apr 2022 20:49:10 +0100
Subject: [PATCH 1704/1731] drm/tegra: Include DMA API header where used

Even though the IOVA API never actually needed it, iova.h is still
carrying an include of dma-mapping.h, now solely for the sake of not
breaking tegra-drm. Fix that properly.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/drm/tegra/dc.c    | 1 +
 drivers/gpu/drm/tegra/hub.c   | 1 +
 drivers/gpu/drm/tegra/nvdec.c | 1 +
 drivers/gpu/drm/tegra/plane.c | 1 +
 4 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index c6951cf5d2ca7..bfc79c61bca6a 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -7,6 +7,7 @@
 #include <linux/clk.h>
 #include <linux/debugfs.h>
 #include <linux/delay.h>
+#include <linux/dma-mapping.h>
 #include <linux/iommu.h>
 #include <linux/interconnect.h>
 #include <linux/module.h>
diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c
index b8d3174c04c91..5f9b85959fae8 100644
--- a/drivers/gpu/drm/tegra/hub.c
+++ b/drivers/gpu/drm/tegra/hub.c
@@ -5,6 +5,7 @@
 
 #include <linux/clk.h>
 #include <linux/delay.h>
+#include <linux/dma-mapping.h>
 #include <linux/host1x.h>
 #include <linux/module.h>
 #include <linux/of.h>
diff --git a/drivers/gpu/drm/tegra/nvdec.c b/drivers/gpu/drm/tegra/nvdec.c
index a84f617096792..276fe04727302 100644
--- a/drivers/gpu/drm/tegra/nvdec.c
+++ b/drivers/gpu/drm/tegra/nvdec.c
@@ -5,6 +5,7 @@
 
 #include <linux/clk.h>
 #include <linux/delay.h>
+#include <linux/dma-mapping.h>
 #include <linux/host1x.h>
 #include <linux/iommu.h>
 #include <linux/module.h>
diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers/gpu/drm/tegra/plane.c
index e0e6938c62003..e46adb107f777 100644
--- a/drivers/gpu/drm/tegra/plane.c
+++ b/drivers/gpu/drm/tegra/plane.c
@@ -3,6 +3,7 @@
  * Copyright (C) 2017 NVIDIA CORPORATION.  All rights reserved.
  */
 
+#include <linux/dma-mapping.h>
 #include <linux/iommu.h>
 #include <linux/interconnect.h>
 
-- 
GitLab


From cb77085b1f0a86ef9dfba86b5f3ed6c3340c2ea3 Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Thu, 7 Jul 2022 14:20:00 -0700
Subject: [PATCH 1705/1731] drm/msm/dpu: Fix for non-visible planes

Fixes `kms_cursor_crc --run-subtest cursor-offscreen`.. when the cursor
moves offscreen the plane becomes non-visible, so we need to skip over
it in crtc atomic test and mixer setup.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/492819/
Link: https://lore.kernel.org/r/20220707212003.1710163-1-robdclark@gmail.com
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 4dd0ce09ca743..4ba000951a908 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -422,6 +422,9 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
 		if (!state)
 			continue;
 
+		if (!state->visible)
+			continue;
+
 		pstate = to_dpu_plane_state(state);
 		fb = state->fb;
 
@@ -1195,6 +1198,9 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 		if (cnt >= DPU_STAGE_MAX * 4)
 			continue;
 
+		if (!pstate->visible)
+			continue;
+
 		pstates[cnt].dpu_pstate = dpu_pstate;
 		pstates[cnt].drm_pstate = pstate;
 		pstates[cnt].stage = pstate->normalized_zpos;
-- 
GitLab


From 5b7239c17ce29b4ffea90a5731d56bd8a3893960 Mon Sep 17 00:00:00 2001
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: Fri, 8 Jul 2022 18:18:01 +0300
Subject: [PATCH 1706/1731] gpu: host1x: Initialize syncval in channel_submit()

During the refactoring of channel_submit(), assignment of syncval was
moved but it is also used in channel_submit(). Add this assignment back
to channel_submit() as well.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/host1x/hw/channel_hw.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw/channel_hw.c
index 4eb7fb2e4f0a2..732abe0750ff9 100644
--- a/drivers/gpu/host1x/hw/channel_hw.c
+++ b/drivers/gpu/host1x/hw/channel_hw.c
@@ -319,6 +319,7 @@ static int channel_submit(struct host1x_job *job)
 	}
 
 	channel_program_cdma(job);
+	syncval = host1x_syncpt_read_max(sp);
 
 	/* end CDMA submit & stash pinned hMems into sync queue */
 	host1x_cdma_end(&ch->cdma, job);
-- 
GitLab


From 8c92243d9e68a93dd282fa2151b67b5c0e31e957 Mon Sep 17 00:00:00 2001
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: Fri, 8 Jul 2022 18:18:02 +0300
Subject: [PATCH 1707/1731] gpu: host1x: Generalize host1x_cdma_push_wide()

host1x_cdma_push_wide() had the assumptions that the last parameter word
was a NOP opcode, and that NOP opcodes could be used in all situations.

Neither are true with the new job opcode sequence, so adjust the
function to not have these assumptions, and instead place an early
RESTART opcode when necessary to jump back to the beginning of the
pushbuffer.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/host1x/cdma.c | 24 +++++++++---------------
 1 file changed, 9 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/host1x/cdma.c b/drivers/gpu/host1x/cdma.c
index bb1f3c746be47..103fda055394a 100644
--- a/drivers/gpu/host1x/cdma.c
+++ b/drivers/gpu/host1x/cdma.c
@@ -615,8 +615,8 @@ void host1x_cdma_push_wide(struct host1x_cdma *cdma, u32 op1, u32 op2,
 	struct host1x_channel *channel = cdma_to_channel(cdma);
 	struct host1x *host1x = cdma_to_host1x(cdma);
 	struct push_buffer *pb = &cdma->push_buffer;
-	unsigned int needed = 2, extra = 0, i;
 	unsigned int space = cdma->slots_free;
+	unsigned int needed = 2, extra = 0;
 
 	if (host1x_debug_trace_cmdbuf)
 		trace_host1x_cdma_push_wide(dev_name(channel->dev), op1, op2,
@@ -634,20 +634,14 @@ void host1x_cdma_push_wide(struct host1x_cdma *cdma, u32 op1, u32 op2,
 	cdma->slots_free = space - needed;
 	cdma->slots_used += needed;
 
-	/*
-	 * Note that we rely on the fact that this is only used to submit wide
-	 * gather opcodes, which consist of 3 words, and they are padded with
-	 * a NOP to avoid having to deal with fractional slots (a slot always
-	 * represents 2 words). The fourth opcode passed to this function will
-	 * therefore always be a NOP.
-	 *
-	 * This works around a slight ambiguity when it comes to opcodes. For
-	 * all current host1x incarnations the NOP opcode uses the exact same
-	 * encoding (0x20000000), so we could hard-code the value here, but a
-	 * new incarnation may change it and break that assumption.
-	 */
-	for (i = 0; i < extra; i++)
-		host1x_pushbuffer_push(pb, op4, op4);
+	if (extra > 0) {
+		/*
+		 * If there isn't enough space at the tail of the pushbuffer,
+		 * insert a RESTART(0) here to go back to the beginning.
+		 * The code above adjusted the indexes appropriately.
+		 */
+		host1x_pushbuffer_push(pb, (0x5 << 28), 0xdead0000);
+	}
 
 	host1x_pushbuffer_push(pb, op1, op2);
 	host1x_pushbuffer_push(pb, op3, op4);
-- 
GitLab


From 2e1bfb314c99de2f7b9c8280408316ad2f316de9 Mon Sep 17 00:00:00 2001
From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Date: Mon, 4 Jul 2022 22:31:51 +0200
Subject: [PATCH 1708/1731] gpu: host1x: Use the bitmap API to allocate bitmaps

Use bitmap_zalloc()/bitmap_free() instead of hand-writing them.

It is less verbose and it improves the semantic.

While at it, remove a useless bitmap_zero() call. The bitmap is already
zero'ed when allocated.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/host1x/channel.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/host1x/channel.c b/drivers/gpu/host1x/channel.c
index 2a9a3a8d5931a..2d0051d6314c2 100644
--- a/drivers/gpu/host1x/channel.c
+++ b/drivers/gpu/host1x/channel.c
@@ -21,22 +21,18 @@ int host1x_channel_list_init(struct host1x_channel_list *chlist,
 	if (!chlist->channels)
 		return -ENOMEM;
 
-	chlist->allocated_channels =
-		kcalloc(BITS_TO_LONGS(num_channels), sizeof(unsigned long),
-			GFP_KERNEL);
+	chlist->allocated_channels = bitmap_zalloc(num_channels, GFP_KERNEL);
 	if (!chlist->allocated_channels) {
 		kfree(chlist->channels);
 		return -ENOMEM;
 	}
 
-	bitmap_zero(chlist->allocated_channels, num_channels);
-
 	return 0;
 }
 
 void host1x_channel_list_free(struct host1x_channel_list *chlist)
 {
-	kfree(chlist->allocated_channels);
+	bitmap_free(chlist->allocated_channels);
 	kfree(chlist->channels);
 }
 
-- 
GitLab


From 135f4c551d51065ee2d0677bf5344a89767e9d9b Mon Sep 17 00:00:00 2001
From: Lv Ruyi <lv.ruyi@zte.com.cn>
Date: Thu, 21 Apr 2022 08:45:42 +0000
Subject: [PATCH 1709/1731] drm/tegra: vic: Use
 devm_platform_ioremap_resource()

Use the devm_platform_ioremap_resource() helper instead of calling
platform_get_resource() and devm_ioremap_resource() separately. Make the
code simpler without functional changes.

Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: Lv Ruyi <lv.ruyi@zte.com.cn>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/drm/tegra/vic.c | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c
index b14b84494be0a..7382ee132eb77 100644
--- a/drivers/gpu/drm/tegra/vic.c
+++ b/drivers/gpu/drm/tegra/vic.c
@@ -469,7 +469,6 @@ static int vic_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct host1x_syncpt **syncpts;
-	struct resource *regs;
 	struct vic *vic;
 	int err;
 
@@ -490,13 +489,7 @@ static int vic_probe(struct platform_device *pdev)
 	if (!syncpts)
 		return -ENOMEM;
 
-	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!regs) {
-		dev_err(&pdev->dev, "failed to get registers\n");
-		return -ENXIO;
-	}
-
-	vic->regs = devm_ioremap_resource(dev, regs);
+	vic->regs = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(vic->regs))
 		return PTR_ERR(vic->regs);
 
-- 
GitLab


From d785a773bed966a75ca1f11d108ae1897189975b Mon Sep 17 00:00:00 2001
From: Jens Axboe <axboe@kernel.dk>
Date: Sat, 9 Jul 2022 07:02:10 -0600
Subject: [PATCH 1710/1731] io_uring: check that we have a file table when
 allocating update slots

If IORING_FILE_INDEX_ALLOC is set asking for an allocated slot, the
helper doesn't check if we actually have a file table or not. The non
alloc path does do that correctly, and returns -ENXIO if we haven't set
one up.

Do the same for the allocated path, avoiding a NULL pointer dereference
when trying to find a free bit.

Fixes: a7c41b4687f5 ("io_uring: let IORING_OP_FILES_UPDATE support choosing fixed file slots")
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 fs/io_uring.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/fs/io_uring.c b/fs/io_uring.c
index cddc0e8490af8..a01ea49f30173 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -7973,6 +7973,9 @@ static int io_files_update_with_index_alloc(struct io_kiocb *req,
 	struct file *file;
 	int ret, fd;
 
+	if (!req->ctx->file_data)
+		return -ENXIO;
+
 	for (done = 0; done < req->rsrc_update.nr_args; done++) {
 		if (copy_from_user(&fd, &fds[done], sizeof(fd))) {
 			ret = -EFAULT;
-- 
GitLab


From de2a34771f5123270bc3842535ac91673116dd03 Mon Sep 17 00:00:00 2001
From: Sven Schnelle <svens@linux.ibm.com>
Date: Wed, 6 Jul 2022 12:16:25 +0200
Subject: [PATCH 1711/1731] ptrace: fix clearing of JOBCTL_TRACED in
 ptrace_unfreeze_traced()

CI reported the following splat while running the strace testsuite:

  WARNING: CPU: 1 PID: 3570031 at kernel/ptrace.c:272 ptrace_check_attach+0x12e/0x178
  CPU: 1 PID: 3570031 Comm: strace Tainted: G           OE     5.19.0-20220624.rc3.git0.ee819a77d4e7.300.fc36.s390x #1
  Hardware name: IBM 3906 M04 704 (z/VM 7.1.0)
  Call Trace:
   [<00000000ab4b645a>] ptrace_check_attach+0x132/0x178
  ([<00000000ab4b6450>] ptrace_check_attach+0x128/0x178)
   [<00000000ab4b6cde>] __s390x_sys_ptrace+0x86/0x160
   [<00000000ac03fcec>] __do_syscall+0x1d4/0x200
   [<00000000ac04e312>] system_call+0x82/0xb0
  Last Breaking-Event-Address:
   [<00000000ab4ea3c8>] wait_task_inactive+0x98/0x190

This is because JOBCTL_TRACED is set, but the task is not in TASK_TRACED
state. Caused by ptrace_unfreeze_traced() which does:

	task->jobctl &= ~TASK_TRACED

but it should be:

	task->jobctl &= ~JOBCTL_TRACED

Fixes: 31cae1eaae4f ("sched,signal,ptrace: Rework TASK_TRACED, TASK_STOPPED state")
Signed-off-by: Sven Schnelle <svens@linux.ibm.com>
Tested-by: Alexander Gordeev <agordeev@linux.ibm.com>
Acked-by: Oleg Nesterov <oleg@redhat.com>
Acked-by: Peter Zijlstra <peterz@infradead.org>
Cc: Eric Biederman <ebiederm@xmission.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Kees Cook <keescook@chromium.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
---
 kernel/ptrace.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/ptrace.c b/kernel/ptrace.c
index 156a99283b11d..1893d909e45ca 100644
--- a/kernel/ptrace.c
+++ b/kernel/ptrace.c
@@ -222,7 +222,7 @@ static void ptrace_unfreeze_traced(struct task_struct *task)
 	if (lock_task_sighand(task, &flags)) {
 		task->jobctl &= ~JOBCTL_PTRACE_FROZEN;
 		if (__fatal_signal_pending(task)) {
-			task->jobctl &= ~TASK_TRACED;
+			task->jobctl &= ~JOBCTL_TRACED;
 			wake_up_state(task, __TASK_TRACED);
 		}
 		unlock_task_sighand(task, &flags);
-- 
GitLab


From 84499c5d220a4f8fb0a35fa4673148525c81ea83 Mon Sep 17 00:00:00 2001
From: Thomas Zimmermann <tzimmermann@suse.de>
Date: Fri, 17 Jun 2022 14:10:27 +0200
Subject: [PATCH 1712/1731] drm/aperture: Run fbdev removal before internal
 helpers

Always run fbdev removal first to remove simpledrm via sysfb_disable().
This clears the internal state.

The later call to drm_aperture_detach_drivers() then does nothing.
Otherwise, with drm_aperture_detach_drivers() running first, the call to
sysfb_disable() uses inconsistent state.

Example backtrace show below:

  BUG: KASAN: use-after-free in device_del+0x79/0x5f0
  Read of size 8 at addr ffff888108185050 by task systemd-udevd/311
  CPU: 0 PID: 311 Comm: systemd-udevd Tainted: G            E     5.19.0-rc2-1-default+ #1689
  Hardware name: HP ProLiant DL120 G7, BIOS J01 04/21/2011
  Call Trace:
    device_del+0x79/0x5f0
    platform_device_del.part.0+0x19/0xe0
    platform_device_unregister+0x1c/0x30
    sysfb_disable+0x2d/0x70
    remove_conflicting_framebuffers+0x1c/0xf0
    remove_conflicting_pci_framebuffers+0x130/0x1a0
    drm_aperture_remove_conflicting_pci_framebuffers+0x86/0xb0
    mgag200_pci_probe+0x2d/0x140 [mgag200]

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Fixes: 873eb3b11860 ("fbdev: Disable sysfb device registration when removing conflicting FBs")
Cc: Javier Martinez Canillas <javierm@redhat.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Helge Deller <deller@gmx.de>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Zhen Lei <thunder.leizhen@huawei.com>
Cc: Changcheng Deng <deng.changcheng@zte.com.cn>
Reviewed-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
---
 drivers/gpu/drm/drm_aperture.c | 26 +++++++++++++++-----------
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/drm_aperture.c b/drivers/gpu/drm/drm_aperture.c
index 74bd4a76b253c..059fd71424f6b 100644
--- a/drivers/gpu/drm/drm_aperture.c
+++ b/drivers/gpu/drm/drm_aperture.c
@@ -329,7 +329,20 @@ int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev,
 						     const struct drm_driver *req_driver)
 {
 	resource_size_t base, size;
-	int bar, ret = 0;
+	int bar, ret;
+
+	/*
+	 * WARNING: Apparently we must kick fbdev drivers before vgacon,
+	 * otherwise the vga fbdev driver falls over.
+	 */
+#if IS_REACHABLE(CONFIG_FB)
+	ret = remove_conflicting_pci_framebuffers(pdev, req_driver->name);
+	if (ret)
+		return ret;
+#endif
+	ret = vga_remove_vgacon(pdev);
+	if (ret)
+		return ret;
 
 	for (bar = 0; bar < PCI_STD_NUM_BARS; ++bar) {
 		if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM))
@@ -339,15 +352,6 @@ int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev,
 		drm_aperture_detach_drivers(base, size);
 	}
 
-	/*
-	 * WARNING: Apparently we must kick fbdev drivers before vgacon,
-	 * otherwise the vga fbdev driver falls over.
-	 */
-#if IS_REACHABLE(CONFIG_FB)
-	ret = remove_conflicting_pci_framebuffers(pdev, req_driver->name);
-#endif
-	if (ret == 0)
-		ret = vga_remove_vgacon(pdev);
-	return ret;
+	return 0;
 }
 EXPORT_SYMBOL(drm_aperture_remove_conflicting_pci_framebuffers);
-- 
GitLab


From cb8a4beac39b90cd60abbf9fd639a3357274e469 Mon Sep 17 00:00:00 2001
From: Borislav Petkov <bp@suse.de>
Date: Sun, 10 Jul 2022 11:15:47 +0200
Subject: [PATCH 1713/1731] x86/boot: Fix the setup data types max limit

Commit in Fixes forgot to change the SETUP_TYPE_MAX definition which
contains the highest valid setup data type.

Correct that.

Fixes: 5ea98e01ab52 ("x86/boot: Add Confidential Computing type to setup_data")
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/ddba81dd-cc92-699c-5274-785396a17fb5@zytor.com
---
 arch/x86/include/uapi/asm/bootparam.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/include/uapi/asm/bootparam.h b/arch/x86/include/uapi/asm/bootparam.h
index bea5cdcdf5325..e02a8a8ef23ce 100644
--- a/arch/x86/include/uapi/asm/bootparam.h
+++ b/arch/x86/include/uapi/asm/bootparam.h
@@ -15,7 +15,7 @@
 #define SETUP_INDIRECT			(1<<31)
 
 /* SETUP_INDIRECT | max(SETUP_*) */
-#define SETUP_TYPE_MAX			(SETUP_INDIRECT | SETUP_JAILHOUSE)
+#define SETUP_TYPE_MAX			(SETUP_INDIRECT | SETUP_CC_BLOB)
 
 /* ram_size flags */
 #define RAMDISK_IMAGE_START_MASK	0x07FF
-- 
GitLab


From f5a4618587fb5c5eb5fec3dcce165ca8fd7d7f91 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <masahiroy@kernel.org>
Date: Thu, 30 Jun 2022 17:09:35 +0900
Subject: [PATCH 1714/1731] kbuild: remove unused cmd_none in
 scripts/Makefile.modinst

Commit 65ce9c38326e ("kbuild: move module strip/compression code into
scripts/Makefile.modinst") added this unused code.

Perhaps, I thought cmd_none was useful for CONFIG_MODULE_COMPRESS_NONE,
but I did not use it after all.

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
---
 scripts/Makefile.modinst | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/scripts/Makefile.modinst b/scripts/Makefile.modinst
index c2c43a0ecfe02..16a02e9237d36 100644
--- a/scripts/Makefile.modinst
+++ b/scripts/Makefile.modinst
@@ -28,9 +28,6 @@ modules := $(patsubst $(extmod_prefix)%, $(dst)/%$(suffix-y), $(modules))
 __modinst: $(modules)
 	@:
 
-quiet_cmd_none =
-      cmd_none = :
-
 #
 # Installation
 #
-- 
GitLab


From fc82bbf4dede758007763867d0282353c06d1121 Mon Sep 17 00:00:00 2001
From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sun, 10 Jul 2022 13:55:49 -0700
Subject: [PATCH 1715/1731] ida: don't use BUG_ON() for debugging

This is another old BUG_ON() that just shouldn't exist (see also commit
a382f8fee42c: "signal handling: don't use BUG_ON() for debugging").

In fact, as Matthew Wilcox points out, this condition shouldn't really
even result in a warning, since a negative id allocation result is just
a normal allocation failure:

  "I wonder if we should even warn here -- sure, the caller is trying to
   free something that wasn't allocated, but we don't warn for
   kfree(NULL)"

and goes on to point out how that current error check is only causing
people to unnecessarily do their own index range checking before freeing
it.

This was noted by Itay Iellin, because the bluetooth HCI socket cookie
code does *not* do that range checking, and ends up just freeing the
error case too, triggering the BUG_ON().

The HCI code requires CAP_NET_RAW, and seems to just result in an ugly
splat, but there really is no reason to BUG_ON() here, and we have
generally striven for allocation models where it's always ok to just do

    free(alloc());

even if the allocation were to fail for some random reason (usually
obviously that "random" reason being some resource limit).

Fixes: 88eca0207cf1 ("ida: simplified functions for id allocation")
Reported-by: Itay Iellin <ieitayie@gmail.com>
Suggested-by: Matthew Wilcox <willy@infradead.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
---
 lib/idr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/lib/idr.c b/lib/idr.c
index f4ab4f4aa3c7f..7ecdfdb5309e7 100644
--- a/lib/idr.c
+++ b/lib/idr.c
@@ -491,7 +491,8 @@ void ida_free(struct ida *ida, unsigned int id)
 	struct ida_bitmap *bitmap;
 	unsigned long flags;
 
-	BUG_ON((int)id < 0);
+	if ((int)id < 0)
+		return;
 
 	xas_lock_irqsave(&xas, flags);
 	bitmap = xas_load(&xas);
-- 
GitLab


From 32346491ddf24599decca06190ebca03ff9de7f8 Mon Sep 17 00:00:00 2001
From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sun, 10 Jul 2022 14:40:51 -0700
Subject: [PATCH 1716/1731] Linux 5.19-rc6

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 990d2ee79186c..faa4880f25f7e 100644
--- a/Makefile
+++ b/Makefile
@@ -2,7 +2,7 @@
 VERSION = 5
 PATCHLEVEL = 19
 SUBLEVEL = 0
-EXTRAVERSION = -rc5
+EXTRAVERSION = -rc6
 NAME = Superb Owl
 
 # *DOCUMENTATION*
-- 
GitLab


From 0cd8a73122b273672cec7efdfb617ddca3423a2e Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Thu, 30 Jun 2022 13:12:17 +0900
Subject: [PATCH 1717/1731] drm/exynos: MAINTAINERS: move Joonyoung Shim to
 credits

Emails to Joonyoung Shim bounce ("550 5.1.1 Recipient address rejected:
User unknown"), so move him to credits file.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
---
 CREDITS     | 4 ++++
 MAINTAINERS | 1 -
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/CREDITS b/CREDITS
index 7e85a53b6a880..91a564c17012d 100644
--- a/CREDITS
+++ b/CREDITS
@@ -3491,6 +3491,10 @@ D: wd33c93 SCSI driver (linux-m68k)
 S: San Jose, California
 S: USA
 
+N: Joonyoung Shim
+E: y0922.shim@samsung.com
+D: Samsung Exynos DRM drivers
+
 N: Robert Siemer
 E: Robert.Siemer@gmx.de
 P: 2048/C99A4289 2F DC 17 2E 56 62 01 C8  3D F2 AC 09 F2 E5 DD EE
diff --git a/MAINTAINERS b/MAINTAINERS
index 6a66d91e02a26..b6cb25173008b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6656,7 +6656,6 @@ F:	drivers/gpu/drm/bridge/
 
 DRM DRIVERS FOR EXYNOS
 M:	Inki Dae <inki.dae@samsung.com>
-M:	Joonyoung Shim <jy0922.shim@samsung.com>
 M:	Seung-Woo Kim <sw0312.kim@samsung.com>
 M:	Kyungmin Park <kyungmin.park@samsung.com>
 L:	dri-devel@lists.freedesktop.org
-- 
GitLab


From f4284724c2163efc941604990f4e2326f5c1093d Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Fri, 1 Jul 2022 09:31:23 +0900
Subject: [PATCH 1718/1731] dt-bindings: remove Joonyoung Shim from maintainers

Emails to Joonyoung Shim bounce ("550 5.1.1 Recipient address rejected:
User unknown"), so remove him from maintainers of DT bindings (display,
phy).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
---
 .../bindings/display/samsung/samsung,exynos-hdmi-ddc.yaml        | 1 -
 .../devicetree/bindings/display/samsung/samsung,exynos-hdmi.yaml | 1 -
 .../bindings/display/samsung/samsung,exynos-mixer.yaml           | 1 -
 .../bindings/display/samsung/samsung,exynos5433-decon.yaml       | 1 -
 .../bindings/display/samsung/samsung,exynos5433-mic.yaml         | 1 -
 .../bindings/display/samsung/samsung,exynos7-decon.yaml          | 1 -
 .../devicetree/bindings/display/samsung/samsung,fimd.yaml        | 1 -
 .../devicetree/bindings/phy/samsung,exynos-hdmi-phy.yaml         | 1 -
 8 files changed, 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/samsung/samsung,exynos-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/samsung/samsung,exynos-hdmi-ddc.yaml
index 919734c05c0b1..458d399cb025b 100644
--- a/Documentation/devicetree/bindings/display/samsung/samsung,exynos-hdmi-ddc.yaml
+++ b/Documentation/devicetree/bindings/display/samsung/samsung,exynos-hdmi-ddc.yaml
@@ -8,7 +8,6 @@ title: Samsung Exynos SoC HDMI DDC
 
 maintainers:
   - Inki Dae <inki.dae@samsung.com>
-  - Joonyoung Shim <jy0922.shim@samsung.com>
   - Seung-Woo Kim <sw0312.kim@samsung.com>
   - Kyungmin Park <kyungmin.park@samsung.com>
   - Krzysztof Kozlowski <krzk@kernel.org>
diff --git a/Documentation/devicetree/bindings/display/samsung/samsung,exynos-hdmi.yaml b/Documentation/devicetree/bindings/display/samsung/samsung,exynos-hdmi.yaml
index 63379fae36366..e4a68c5a1a095 100644
--- a/Documentation/devicetree/bindings/display/samsung/samsung,exynos-hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/samsung/samsung,exynos-hdmi.yaml
@@ -8,7 +8,6 @@ title: Samsung Exynos SoC HDMI
 
 maintainers:
   - Inki Dae <inki.dae@samsung.com>
-  - Joonyoung Shim <jy0922.shim@samsung.com>
   - Seung-Woo Kim <sw0312.kim@samsung.com>
   - Kyungmin Park <kyungmin.park@samsung.com>
   - Krzysztof Kozlowski <krzk@kernel.org>
diff --git a/Documentation/devicetree/bindings/display/samsung/samsung,exynos-mixer.yaml b/Documentation/devicetree/bindings/display/samsung/samsung,exynos-mixer.yaml
index 00e325a19cb1d..25d53fde92e11 100644
--- a/Documentation/devicetree/bindings/display/samsung/samsung,exynos-mixer.yaml
+++ b/Documentation/devicetree/bindings/display/samsung/samsung,exynos-mixer.yaml
@@ -8,7 +8,6 @@ title: Samsung Exynos SoC Mixer
 
 maintainers:
   - Inki Dae <inki.dae@samsung.com>
-  - Joonyoung Shim <jy0922.shim@samsung.com>
   - Seung-Woo Kim <sw0312.kim@samsung.com>
   - Kyungmin Park <kyungmin.park@samsung.com>
   - Krzysztof Kozlowski <krzk@kernel.org>
diff --git a/Documentation/devicetree/bindings/display/samsung/samsung,exynos5433-decon.yaml b/Documentation/devicetree/bindings/display/samsung/samsung,exynos5433-decon.yaml
index 7c37470bd3297..921bfe925cd64 100644
--- a/Documentation/devicetree/bindings/display/samsung/samsung,exynos5433-decon.yaml
+++ b/Documentation/devicetree/bindings/display/samsung/samsung,exynos5433-decon.yaml
@@ -8,7 +8,6 @@ title: Samsung Exynos5433 SoC Display and Enhancement Controller (DECON)
 
 maintainers:
   - Inki Dae <inki.dae@samsung.com>
-  - Joonyoung Shim <jy0922.shim@samsung.com>
   - Seung-Woo Kim <sw0312.kim@samsung.com>
   - Kyungmin Park <kyungmin.park@samsung.com>
   - Krzysztof Kozlowski <krzk@kernel.org>
diff --git a/Documentation/devicetree/bindings/display/samsung/samsung,exynos5433-mic.yaml b/Documentation/devicetree/bindings/display/samsung/samsung,exynos5433-mic.yaml
index c5c6239c28d07..7d405f2febcd2 100644
--- a/Documentation/devicetree/bindings/display/samsung/samsung,exynos5433-mic.yaml
+++ b/Documentation/devicetree/bindings/display/samsung/samsung,exynos5433-mic.yaml
@@ -8,7 +8,6 @@ title: Samsung Exynos5433 SoC Mobile Image Compressor (MIC)
 
 maintainers:
   - Inki Dae <inki.dae@samsung.com>
-  - Joonyoung Shim <jy0922.shim@samsung.com>
   - Seung-Woo Kim <sw0312.kim@samsung.com>
   - Kyungmin Park <kyungmin.park@samsung.com>
   - Krzysztof Kozlowski <krzk@kernel.org>
diff --git a/Documentation/devicetree/bindings/display/samsung/samsung,exynos7-decon.yaml b/Documentation/devicetree/bindings/display/samsung/samsung,exynos7-decon.yaml
index 320eedc61a5b5..969bd8c563a50 100644
--- a/Documentation/devicetree/bindings/display/samsung/samsung,exynos7-decon.yaml
+++ b/Documentation/devicetree/bindings/display/samsung/samsung,exynos7-decon.yaml
@@ -8,7 +8,6 @@ title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON)
 
 maintainers:
   - Inki Dae <inki.dae@samsung.com>
-  - Joonyoung Shim <jy0922.shim@samsung.com>
   - Seung-Woo Kim <sw0312.kim@samsung.com>
   - Kyungmin Park <kyungmin.park@samsung.com>
   - Krzysztof Kozlowski <krzk@kernel.org>
diff --git a/Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml b/Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml
index c62ea9d228432..5d5cc220f78a9 100644
--- a/Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml
+++ b/Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml
@@ -8,7 +8,6 @@ title: Samsung S3C/S5P/Exynos SoC Fully Interactive Mobile Display (FIMD)
 
 maintainers:
   - Inki Dae <inki.dae@samsung.com>
-  - Joonyoung Shim <jy0922.shim@samsung.com>
   - Seung-Woo Kim <sw0312.kim@samsung.com>
   - Kyungmin Park <kyungmin.park@samsung.com>
   - Krzysztof Kozlowski <krzk@kernel.org>
diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos-hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,exynos-hdmi-phy.yaml
index 3e5f035de2e9c..efc679c385ab5 100644
--- a/Documentation/devicetree/bindings/phy/samsung,exynos-hdmi-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/samsung,exynos-hdmi-phy.yaml
@@ -8,7 +8,6 @@ title: Samsung Exynos SoC HDMI PHY
 
 maintainers:
   - Inki Dae <inki.dae@samsung.com>
-  - Joonyoung Shim <jy0922.shim@samsung.com>
   - Seung-Woo Kim <sw0312.kim@samsung.com>
   - Kyungmin Park <kyungmin.park@samsung.com>
   - Krzysztof Kozlowski <krzk@kernel.org>
-- 
GitLab


From 48b927770f8ad3f8cf4a024a552abf272af9f592 Mon Sep 17 00:00:00 2001
From: Jian Zhang <zhangjian210@huawei.com>
Date: Tue, 12 Jul 2022 13:56:11 +0900
Subject: [PATCH 1719/1731] drm/exynos/exynos7_drm_decon: free resources when
 clk_set_parent() failed.

In exynos7_decon_resume, When it fails, we must use clk_disable_unprepare()
to free resource that have been used.

Fixes: 6f83d20838c09 ("drm/exynos: use DRM_DEV_ERROR to print out error
message")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Jian Zhang <zhangjian210@huawei.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
---
 drivers/gpu/drm/exynos/exynos7_drm_decon.c | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
index 3047edf355b54..7080cf7952ecb 100644
--- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
@@ -801,31 +801,40 @@ static int exynos7_decon_resume(struct device *dev)
 	if (ret < 0) {
 		DRM_DEV_ERROR(dev, "Failed to prepare_enable the pclk [%d]\n",
 			      ret);
-		return ret;
+		goto err_pclk_enable;
 	}
 
 	ret = clk_prepare_enable(ctx->aclk);
 	if (ret < 0) {
 		DRM_DEV_ERROR(dev, "Failed to prepare_enable the aclk [%d]\n",
 			      ret);
-		return ret;
+		goto err_aclk_enable;
 	}
 
 	ret = clk_prepare_enable(ctx->eclk);
 	if  (ret < 0) {
 		DRM_DEV_ERROR(dev, "Failed to prepare_enable the eclk [%d]\n",
 			      ret);
-		return ret;
+		goto err_eclk_enable;
 	}
 
 	ret = clk_prepare_enable(ctx->vclk);
 	if  (ret < 0) {
 		DRM_DEV_ERROR(dev, "Failed to prepare_enable the vclk [%d]\n",
 			      ret);
-		return ret;
+		goto err_vclk_enable;
 	}
 
 	return 0;
+
+err_vclk_enable:
+	clk_disable_unprepare(ctx->eclk);
+err_eclk_enable:
+	clk_disable_unprepare(ctx->aclk);
+err_aclk_enable:
+	clk_disable_unprepare(ctx->pclk);
+err_pclk_enable:
+	return ret;
 }
 #endif
 
-- 
GitLab


From 911dd554a129081f056417a30054f24ef6818e3d Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 1 Jun 2022 20:46:00 +1000
Subject: [PATCH 1720/1731] drm/nouveau/nvif: add wrapper for open-coded
 nvif_object_constructed()

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/nouveau/include/nvif/object.h | 6 ++++++
 drivers/gpu/drm/nouveau/nvif/object.c         | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/nouveau/include/nvif/object.h b/drivers/gpu/drm/nouveau/include/nvif/object.h
index 1e4c158d20fab..f52399caee820 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/object.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/object.h
@@ -22,6 +22,12 @@ struct nvif_object {
 	} map;
 };
 
+static inline bool
+nvif_object_constructed(struct nvif_object *object)
+{
+	return object->client != NULL;
+}
+
 int  nvif_object_ctor(struct nvif_object *, const char *name, u32 handle,
 		      s32 oclass, void *, u32, struct nvif_object *);
 void nvif_object_dtor(struct nvif_object *);
diff --git a/drivers/gpu/drm/nouveau/nvif/object.c b/drivers/gpu/drm/nouveau/nvif/object.c
index dce1ecee2af5a..4d1aaee8fe15f 100644
--- a/drivers/gpu/drm/nouveau/nvif/object.c
+++ b/drivers/gpu/drm/nouveau/nvif/object.c
@@ -250,7 +250,7 @@ nvif_object_dtor(struct nvif_object *object)
 		.ioctl.type = NVIF_IOCTL_V0_DEL,
 	};
 
-	if (!object->client)
+	if (!nvif_object_constructed(object))
 		return;
 
 	nvif_object_unmap(object);
-- 
GitLab


From c4feba47aad55aca90d9a2b104c0345ca6f93712 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 1 Jun 2022 20:46:01 +1000
Subject: [PATCH 1721/1731] drm/nouveau/nvkm: rip out event uapi

Userspace never ended up using this to be clever about dealing with
channel death, and it won't be, not like this anyway.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/nouveau/nouveau_drv.h  |   1 -
 drivers/gpu/drm/nouveau/nouveau_nvif.c |  31 +---
 drivers/gpu/drm/nouveau/nouveau_usif.c | 231 +------------------------
 3 files changed, 2 insertions(+), 261 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index b2a970aa9bf4b..84df5ddae4d06 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -102,7 +102,6 @@ struct nouveau_cli {
 	struct list_head head;
 	void *abi16;
 	struct list_head objects;
-	struct list_head notifys;
 	char name[32];
 
 	struct work_struct work;
diff --git a/drivers/gpu/drm/nouveau/nouveau_nvif.c b/drivers/gpu/drm/nouveau/nouveau_nvif.c
index 52f5793b7274f..df0fe58ca3ab2 100644
--- a/drivers/gpu/drm/nouveau/nouveau_nvif.c
+++ b/drivers/gpu/drm/nouveau/nouveau_nvif.c
@@ -71,40 +71,11 @@ nvkm_client_suspend(void *priv)
 	return nvkm_object_fini(&client->object, true);
 }
 
-static int
-nvkm_client_ntfy(const void *header, u32 length, const void *data, u32 size)
-{
-	const union {
-		struct nvif_notify_req_v0 v0;
-	} *args = header;
-	u8 route;
-
-	if (length == sizeof(args->v0) && args->v0.version == 0) {
-		route = args->v0.route;
-	} else {
-		WARN_ON(1);
-		return NVKM_NOTIFY_DROP;
-	}
-
-	switch (route) {
-	case NVDRM_NOTIFY_NVIF:
-		return nvif_notify(header, length, data, size);
-	case NVDRM_NOTIFY_USIF:
-		return usif_notify(header, length, data, size);
-	default:
-		WARN_ON(1);
-		break;
-	}
-
-	return NVKM_NOTIFY_DROP;
-}
-
 static int
 nvkm_client_driver_init(const char *name, u64 device, const char *cfg,
 			const char *dbg, void **ppriv)
 {
-	return nvkm_client_new(name, device, cfg, dbg, nvkm_client_ntfy,
-			       (struct nvkm_client **)ppriv);
+	return nvkm_client_new(name, device, cfg, dbg, nvif_notify, (struct nvkm_client **)ppriv);
 }
 
 const struct nvif_driver
diff --git a/drivers/gpu/drm/nouveau/nouveau_usif.c b/drivers/gpu/drm/nouveau/nouveau_usif.c
index 5da1f4d223d76..36df6840c0994 100644
--- a/drivers/gpu/drm/nouveau/nouveau_usif.c
+++ b/drivers/gpu/drm/nouveau/nouveau_usif.c
@@ -26,232 +26,15 @@
 #include "nouveau_usif.h"
 #include "nouveau_abi16.h"
 
-#include <nvif/notify.h>
 #include <nvif/unpack.h>
 #include <nvif/client.h>
-#include <nvif/event.h>
 #include <nvif/ioctl.h>
 
 #include <nvif/class.h>
 #include <nvif/cl0080.h>
 
-struct usif_notify_p {
-	struct drm_pending_event base;
-	struct {
-		struct drm_event base;
-		u8 data[];
-	} e;
-};
-
-struct usif_notify {
-	struct list_head head;
-	atomic_t enabled;
-	u32 handle;
-	u16 reply;
-	u8  route;
-	u64 token;
-	struct usif_notify_p *p;
-};
-
-static inline struct usif_notify *
-usif_notify_find(struct drm_file *filp, u32 handle)
-{
-	struct nouveau_cli *cli = nouveau_cli(filp);
-	struct usif_notify *ntfy;
-	list_for_each_entry(ntfy, &cli->notifys, head) {
-		if (ntfy->handle == handle)
-			return ntfy;
-	}
-	return NULL;
-}
-
-static inline void
-usif_notify_dtor(struct usif_notify *ntfy)
-{
-	list_del(&ntfy->head);
-	kfree(ntfy);
-}
-
-int
-usif_notify(const void *header, u32 length, const void *data, u32 size)
-{
-	struct usif_notify *ntfy = NULL;
-	const union {
-		struct nvif_notify_rep_v0 v0;
-	} *rep = header;
-	struct drm_device *dev;
-	struct drm_file *filp;
-	unsigned long flags;
-
-	if (length == sizeof(rep->v0) && rep->v0.version == 0) {
-		if (WARN_ON(!(ntfy = (void *)(unsigned long)rep->v0.token)))
-			return NVIF_NOTIFY_DROP;
-		BUG_ON(rep->v0.route != NVDRM_NOTIFY_USIF);
-	} else
-	if (WARN_ON(1))
-		return NVIF_NOTIFY_DROP;
-
-	if (WARN_ON(!ntfy->p || ntfy->reply != (length + size)))
-		return NVIF_NOTIFY_DROP;
-	filp = ntfy->p->base.file_priv;
-	dev = filp->minor->dev;
-
-	memcpy(&ntfy->p->e.data[0], header, length);
-	memcpy(&ntfy->p->e.data[length], data, size);
-	switch (rep->v0.version) {
-	case 0: {
-		struct nvif_notify_rep_v0 *rep = (void *)ntfy->p->e.data;
-		rep->route = ntfy->route;
-		rep->token = ntfy->token;
-	}
-		break;
-	default:
-		BUG();
-		break;
-	}
-
-	spin_lock_irqsave(&dev->event_lock, flags);
-	if (!WARN_ON(filp->event_space < ntfy->p->e.base.length)) {
-		list_add_tail(&ntfy->p->base.link, &filp->event_list);
-		filp->event_space -= ntfy->p->e.base.length;
-	}
-	wake_up_interruptible(&filp->event_wait);
-	spin_unlock_irqrestore(&dev->event_lock, flags);
-	atomic_set(&ntfy->enabled, 0);
-	return NVIF_NOTIFY_DROP;
-}
-
-static int
-usif_notify_new(struct drm_file *f, void *data, u32 size, void *argv, u32 argc)
-{
-	struct nouveau_cli *cli = nouveau_cli(f);
-	struct nvif_client *client = &cli->base;
-	union {
-		struct nvif_ioctl_ntfy_new_v0 v0;
-	} *args = data;
-	union {
-		struct nvif_notify_req_v0 v0;
-	} *req;
-	struct usif_notify *ntfy;
-	int ret = -ENOSYS;
-
-	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
-		if (usif_notify_find(f, args->v0.index))
-			return -EEXIST;
-	} else
-		return ret;
-	req = data;
-	ret = -ENOSYS;
-
-	if (!(ntfy = kmalloc(sizeof(*ntfy), GFP_KERNEL)))
-		return -ENOMEM;
-	atomic_set(&ntfy->enabled, 0);
-
-	if (!(ret = nvif_unpack(ret, &data, &size, req->v0, 0, 0, true))) {
-		ntfy->reply = sizeof(struct nvif_notify_rep_v0) + req->v0.reply;
-		ntfy->route = req->v0.route;
-		ntfy->token = req->v0.token;
-		req->v0.route = NVDRM_NOTIFY_USIF;
-		req->v0.token = (unsigned long)(void *)ntfy;
-		ret = nvif_client_ioctl(client, argv, argc);
-		req->v0.token = ntfy->token;
-		req->v0.route = ntfy->route;
-		ntfy->handle = args->v0.index;
-	}
-
-	if (ret == 0)
-		list_add(&ntfy->head, &cli->notifys);
-	if (ret)
-		kfree(ntfy);
-	return ret;
-}
-
-static int
-usif_notify_del(struct drm_file *f, void *data, u32 size, void *argv, u32 argc)
-{
-	struct nouveau_cli *cli = nouveau_cli(f);
-	struct nvif_client *client = &cli->base;
-	union {
-		struct nvif_ioctl_ntfy_del_v0 v0;
-	} *args = data;
-	struct usif_notify *ntfy;
-	int ret = -ENOSYS;
-
-	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
-		if (!(ntfy = usif_notify_find(f, args->v0.index)))
-			return -ENOENT;
-	} else
-		return ret;
-
-	ret = nvif_client_ioctl(client, argv, argc);
-	if (ret == 0)
-		usif_notify_dtor(ntfy);
-	return ret;
-}
-
-static int
-usif_notify_get(struct drm_file *f, void *data, u32 size, void *argv, u32 argc)
-{
-	struct nouveau_cli *cli = nouveau_cli(f);
-	struct nvif_client *client = &cli->base;
-	union {
-		struct nvif_ioctl_ntfy_del_v0 v0;
-	} *args = data;
-	struct usif_notify *ntfy;
-	int ret = -ENOSYS;
-
-	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
-		if (!(ntfy = usif_notify_find(f, args->v0.index)))
-			return -ENOENT;
-	} else
-		return ret;
-
-	if (atomic_xchg(&ntfy->enabled, 1))
-		return 0;
-
-	ntfy->p = kmalloc(sizeof(*ntfy->p) + ntfy->reply, GFP_KERNEL);
-	if (ret = -ENOMEM, !ntfy->p)
-		goto done;
-	ntfy->p->base.event = &ntfy->p->e.base;
-	ntfy->p->base.file_priv = f;
-	ntfy->p->e.base.type = DRM_NOUVEAU_EVENT_NVIF;
-	ntfy->p->e.base.length = sizeof(ntfy->p->e.base) + ntfy->reply;
-
-	ret = nvif_client_ioctl(client, argv, argc);
-done:
-	if (ret) {
-		atomic_set(&ntfy->enabled, 0);
-		kfree(ntfy->p);
-	}
-	return ret;
-}
-
-static int
-usif_notify_put(struct drm_file *f, void *data, u32 size, void *argv, u32 argc)
-{
-	struct nouveau_cli *cli = nouveau_cli(f);
-	struct nvif_client *client = &cli->base;
-	union {
-		struct nvif_ioctl_ntfy_put_v0 v0;
-	} *args = data;
-	struct usif_notify *ntfy;
-	int ret = -ENOSYS;
-
-	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
-		if (!(ntfy = usif_notify_find(f, args->v0.index)))
-			return -ENOENT;
-	} else
-		return ret;
-
-	ret = nvif_client_ioctl(client, argv, argc);
-	if (ret == 0 && atomic_xchg(&ntfy->enabled, 0))
-		kfree(ntfy->p);
-	return ret;
-}
-
 struct usif_object {
 	struct list_head head;
-	struct list_head ntfy;
 	u8  route;
 	u64 token;
 };
@@ -369,16 +152,10 @@ usif_ioctl(struct drm_file *filp, void __user *user, u32 argc)
 		ret = usif_object_new(filp, data, size, argv, argc, abi16);
 		break;
 	case NVIF_IOCTL_V0_NTFY_NEW:
-		ret = usif_notify_new(filp, data, size, argv, argc);
-		break;
 	case NVIF_IOCTL_V0_NTFY_DEL:
-		ret = usif_notify_del(filp, data, size, argv, argc);
-		break;
 	case NVIF_IOCTL_V0_NTFY_GET:
-		ret = usif_notify_get(filp, data, size, argv, argc);
-		break;
 	case NVIF_IOCTL_V0_NTFY_PUT:
-		ret = usif_notify_put(filp, data, size, argv, argc);
+		ret = -ENOSYS;
 		break;
 	default:
 		ret = nvif_client_ioctl(client, argv, argc);
@@ -410,11 +187,6 @@ void
 usif_client_fini(struct nouveau_cli *cli)
 {
 	struct usif_object *object, *otemp;
-	struct usif_notify *notify, *ntemp;
-
-	list_for_each_entry_safe(notify, ntemp, &cli->notifys, head) {
-		usif_notify_dtor(notify);
-	}
 
 	list_for_each_entry_safe(object, otemp, &cli->objects, head) {
 		usif_object_dtor(object);
@@ -425,5 +197,4 @@ void
 usif_client_init(struct nouveau_cli *cli)
 {
 	INIT_LIST_HEAD(&cli->objects);
-	INIT_LIST_HEAD(&cli->notifys);
 }
-- 
GitLab


From 61c1f340bc809a1ca1e3c8794207a91cde1a7c78 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 1 Jun 2022 20:46:02 +1000
Subject: [PATCH 1722/1731] drm/nouveau/nvkm: use list_add_tail() when building
 object tree

Fixes resume from hibernate failing on (at least) TU102, where cursor
channel init failed due to being performed before the core channel.

Not solid idea why suspend-to-ram worked, but, presumably HW being in
an entirely clean state has something to do with it.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c
index 735cb6816f108..06b2f675f5da3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c
@@ -128,7 +128,7 @@ nvkm_ioctl_new(struct nvkm_client *client,
 	if (ret == 0) {
 		ret = nvkm_object_init(object);
 		if (ret == 0) {
-			list_add(&object->head, &parent->tree);
+			list_add_tail(&object->head, &parent->tree);
 			if (nvkm_object_insert(object)) {
 				client->data = object;
 				return 0;
-- 
GitLab


From 4ddf8d7dedb881c6638850f1b74ff1f9967c89b7 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 1 Jun 2022 20:46:02 +1000
Subject: [PATCH 1723/1731] drm/nouveau/nvkm: zero out engine pointer for
 subdev-provided classes

Doesn't fix any known issue, but noticed fifo being initialised in
logs in response to mmu allocation.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
index 113ddc103ac26..45f509c11c361 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
@@ -346,6 +346,7 @@ nvkm_udevice_child_get(struct nvkm_object *object, int index,
 			return -EINVAL;
 
 		oclass->base = sclass->base;
+		oclass->engine = NULL;
 	}
 
 	oclass->ctor = nvkm_udevice_child_new;
-- 
GitLab


From 6d7291843ec5008a9ff1c011d342679fa9bfe4b9 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 1 Jun 2022 20:46:02 +1000
Subject: [PATCH 1724/1731] drm/nouveau/nvkm: remove unused header

Left-over from secboot->acr transition.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 .../drm/nouveau/include/nvkm/subdev/secboot.h | 66 -------------------
 .../gpu/drm/nouveau/nvkm/engine/gr/gm200.c    |  1 -
 2 files changed, 67 deletions(-)
 delete mode 100644 drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h

diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h
deleted file mode 100644
index b57fe4ae93bab..0000000000000
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef __NVKM_SECURE_BOOT_H__
-#define __NVKM_SECURE_BOOT_H__
-
-#include <core/subdev.h>
-
-enum nvkm_secboot_falcon {
-	NVKM_SECBOOT_FALCON_PMU = 0,
-	NVKM_SECBOOT_FALCON_RESERVED = 1,
-	NVKM_SECBOOT_FALCON_FECS = 2,
-	NVKM_SECBOOT_FALCON_GPCCS = 3,
-	NVKM_SECBOOT_FALCON_SEC2 = 7,
-	NVKM_SECBOOT_FALCON_END = 8,
-	NVKM_SECBOOT_FALCON_INVALID = 0xffffffff,
-};
-
-extern const char *nvkm_secboot_falcon_name[];
-
-/**
- * @wpr_set: whether the WPR region is currently set
-*/
-struct nvkm_secboot {
-	const struct nvkm_secboot_func *func;
-	struct nvkm_acr *acr;
-	struct nvkm_subdev subdev;
-	struct nvkm_falcon *boot_falcon;
-	struct nvkm_falcon *halt_falcon;
-
-	u64 wpr_addr;
-	u32 wpr_size;
-
-	bool wpr_set;
-};
-#define nvkm_secboot(p) container_of((p), struct nvkm_secboot, subdev)
-
-bool nvkm_secboot_is_managed(struct nvkm_secboot *, enum nvkm_secboot_falcon);
-int nvkm_secboot_reset(struct nvkm_secboot *, unsigned long);
-
-int gm200_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **);
-int gm20b_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **);
-int gp102_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **);
-int gp108_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **);
-int gp10b_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
index 5c38ff0fe7f9d..385cfd91b2669 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
@@ -26,7 +26,6 @@
 
 #include <core/firmware.h>
 #include <subdev/acr.h>
-#include <subdev/secboot.h>
 
 #include <nvfw/flcn.h>
 
-- 
GitLab


From 0196cc65f91710e30d45cea78d75fd616d705002 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 1 Jun 2022 20:46:03 +1000
Subject: [PATCH 1725/1731] drm/nouveau/device: remove pwrsrc notify in favour
 of a direct call to clk

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 .../drm/nouveau/include/nvkm/core/device.h    |  3 ---
 .../gpu/drm/nouveau/include/nvkm/subdev/clk.h |  3 +--
 .../drm/nouveau/include/nvkm/subdev/fault.h   |  1 +
 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c     |  1 +
 .../gpu/drm/nouveau/nvkm/engine/device/acpi.c |  6 ++---
 .../gpu/drm/nouveau/nvkm/engine/device/base.c | 25 -------------------
 .../gpu/drm/nouveau/nvkm/subdev/clk/base.c    | 20 ++++-----------
 7 files changed, 11 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index a18b6cfda07e4..efede1f11e1d9 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -2,7 +2,6 @@
 #ifndef __NVKM_DEVICE_H__
 #define __NVKM_DEVICE_H__
 #include <core/oclass.h>
-#include <core/event.h>
 enum nvkm_subdev_type;
 
 enum nvkm_device_type {
@@ -28,8 +27,6 @@ struct nvkm_device {
 
 	void __iomem *pri;
 
-	struct nvkm_event event;
-
 	u32 debug;
 
 	const struct nvkm_device_chip *chip;
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
index 05b99c9e9a26a..d5d8877064a71 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
@@ -2,7 +2,6 @@
 #ifndef __NVKM_CLK_H__
 #define __NVKM_CLK_H__
 #include <core/subdev.h>
-#include <core/notify.h>
 #include <subdev/pci.h>
 struct nvbios_pll;
 struct nvkm_pll_vals;
@@ -94,7 +93,6 @@ struct nvkm_clk {
 	wait_queue_head_t wait;
 	atomic_t waiting;
 
-	struct nvkm_notify pwrsrc_ntfy;
 	int pwrsrc;
 	int pstate; /* current */
 	int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */
@@ -124,6 +122,7 @@ int nvkm_clk_ustate(struct nvkm_clk *, int req, int pwr);
 int nvkm_clk_astate(struct nvkm_clk *, int req, int rel, bool wait);
 int nvkm_clk_dstate(struct nvkm_clk *, int req, int rel);
 int nvkm_clk_tstate(struct nvkm_clk *, u8 temperature);
+int nvkm_clk_pwrsrc(struct nvkm_device *);
 
 int nv04_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
 int nv40_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h
index 581458ad38e06..9c78f072d62b4 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h
@@ -1,6 +1,7 @@
 #ifndef __NVKM_FAULT_H__
 #define __NVKM_FAULT_H__
 #include <core/subdev.h>
+#include <core/event.h>
 #include <core/notify.h>
 
 struct nvkm_fault {
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c
index 06b2f675f5da3..45f920da89af5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c
@@ -24,6 +24,7 @@
 #include <core/ioctl.h>
 #include <core/client.h>
 #include <core/engine.h>
+#include <core/event.h>
 
 #include <nvif/unpack.h>
 #include <nvif/ioctl.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c
index fdca90bc8f0e5..c948a0dc9e62a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c
@@ -24,17 +24,17 @@
 #include "acpi.h"
 
 #include <core/device.h>
+#include <subdev/clk.h>
 
 #ifdef CONFIG_ACPI
 static int
 nvkm_acpi_ntfy(struct notifier_block *nb, unsigned long val, void *data)
 {
-	struct nvkm_device *device =
-		container_of(nb, typeof(*device), acpi.nb);
+	struct nvkm_device *device = container_of(nb, typeof(*device), acpi.nb);
 	struct acpi_bus_event *info = data;
 
 	if (!strcmp(info->device_class, "ac_adapter"))
-		nvkm_event_send(&device->event, 1, 0, NULL, 0);
+		nvkm_clk_pwrsrc(device);
 
 	return NOTIFY_DONE;
 }
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index 62efbd0f38466..568182e68dd73 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -24,7 +24,6 @@
 #include "priv.h"
 #include "acpi.h"
 
-#include <core/notify.h>
 #include <core/option.h>
 
 #include <subdev/bios.h>
@@ -2668,24 +2667,6 @@ nv177_chipset = {
 	.fifo     = { 0x00000001, ga102_fifo_new },
 };
 
-static int
-nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size,
-		       struct nvkm_notify *notify)
-{
-	if (!WARN_ON(size != 0)) {
-		notify->size  = 0;
-		notify->types = 1;
-		notify->index = 0;
-		return 0;
-	}
-	return -EINVAL;
-}
-
-static const struct nvkm_event_func
-nvkm_device_event_func = {
-	.ctor = nvkm_device_event_ctor,
-};
-
 struct nvkm_subdev *
 nvkm_device_subdev(struct nvkm_device *device, int type, int inst)
 {
@@ -2838,8 +2819,6 @@ nvkm_device_del(struct nvkm_device **pdevice)
 		list_for_each_entry_safe_reverse(subdev, subtmp, &device->subdev, head)
 			nvkm_subdev_del(&subdev);
 
-		nvkm_event_fini(&device->event);
-
 		if (device->pri)
 			iounmap(device->pri);
 		list_del(&device->head);
@@ -2914,10 +2893,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
 	device->debug = nvkm_dbgopt(device->dbgopt, "device");
 	INIT_LIST_HEAD(&device->subdev);
 
-	ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event);
-	if (ret)
-		goto done;
-
 	mmio_base = device->func->resource_addr(device, 0);
 	mmio_size = device->func->resource_size(device, 0);
 
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
index c2b5cc5f97eda..da07a2fbef062 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
@@ -330,7 +330,6 @@ nvkm_pstate_work(struct work_struct *work)
 	}
 
 	wake_up_all(&clk->wait);
-	nvkm_notify_get(&clk->pwrsrc_ntfy);
 }
 
 static int
@@ -559,13 +558,12 @@ nvkm_clk_dstate(struct nvkm_clk *clk, int req, int rel)
 	return nvkm_pstate_calc(clk, true);
 }
 
-static int
-nvkm_clk_pwrsrc(struct nvkm_notify *notify)
+int
+nvkm_clk_pwrsrc(struct nvkm_device *device)
 {
-	struct nvkm_clk *clk =
-		container_of(notify, typeof(*clk), pwrsrc_ntfy);
-	nvkm_pstate_calc(clk, false);
-	return NVKM_NOTIFY_DROP;
+	if (device->clk)
+		return nvkm_pstate_calc(device->clk, false);
+	return 0;
 }
 
 /******************************************************************************
@@ -582,7 +580,6 @@ static int
 nvkm_clk_fini(struct nvkm_subdev *subdev, bool suspend)
 {
 	struct nvkm_clk *clk = nvkm_clk(subdev);
-	nvkm_notify_put(&clk->pwrsrc_ntfy);
 	flush_work(&clk->work);
 	if (clk->func->fini)
 		clk->func->fini(clk);
@@ -629,8 +626,6 @@ nvkm_clk_dtor(struct nvkm_subdev *subdev)
 	struct nvkm_clk *clk = nvkm_clk(subdev);
 	struct nvkm_pstate *pstate, *temp;
 
-	nvkm_notify_fini(&clk->pwrsrc_ntfy);
-
 	/* Early return if the pstates have been provided statically */
 	if (clk->func->pstates)
 		return clk;
@@ -692,11 +687,6 @@ nvkm_clk_ctor(const struct nvkm_clk_func *func, struct nvkm_device *device,
 		clk->state_nr = func->nr_pstates;
 	}
 
-	ret = nvkm_notify_init(NULL, &device->event, nvkm_clk_pwrsrc, true,
-			       NULL, 0, 0, &clk->pwrsrc_ntfy);
-	if (ret)
-		return ret;
-
 	mode = nvkm_stropt(device->cfgopt, "NvClkMode", &arglen);
 	if (mode) {
 		clk->ustate_ac = nvkm_clk_nstate(clk, mode, arglen);
-- 
GitLab


From 66ff4e4ed471fdfa9ae4c49a0abcf5d5043ca65e Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 1 Jun 2022 20:46:03 +1000
Subject: [PATCH 1726/1731] drm/nouveau/fifo: rip out cevent, never used

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 .../drm/nouveau/include/nvkm/engine/fifo.h    |  1 -
 .../gpu/drm/nouveau/nvkm/engine/fifo/base.c   | 29 -------------------
 .../gpu/drm/nouveau/nvkm/engine/fifo/chan.c   |  2 --
 .../gpu/drm/nouveau/nvkm/engine/fifo/priv.h   |  1 -
 4 files changed, 33 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
index 64ee82c7c1be5..4d1a3bd558fd9 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
@@ -44,7 +44,6 @@ struct nvkm_fifo {
 	struct mutex mutex;
 
 	struct nvkm_event uevent; /* async user trigger */
-	struct nvkm_event cevent; /* channel creation event */
 	struct nvkm_event kevent; /* channel killed */
 };
 
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
index 2ed4ff05d2075..58b8df75fc402 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
@@ -144,30 +144,6 @@ nvkm_fifo_kevent_func = {
 	.ctor = nvkm_fifo_kevent_ctor,
 };
 
-static int
-nvkm_fifo_cevent_ctor(struct nvkm_object *object, void *data, u32 size,
-		      struct nvkm_notify *notify)
-{
-	if (size == 0) {
-		notify->size  = 0;
-		notify->types = 1;
-		notify->index = 0;
-		return 0;
-	}
-	return -ENOSYS;
-}
-
-static const struct nvkm_event_func
-nvkm_fifo_cevent_func = {
-	.ctor = nvkm_fifo_cevent_ctor,
-};
-
-void
-nvkm_fifo_cevent(struct nvkm_fifo *fifo)
-{
-	nvkm_event_send(&fifo->cevent, 1, 0, NULL, 0);
-}
-
 static void
 nvkm_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
 {
@@ -332,7 +308,6 @@ nvkm_fifo_dtor(struct nvkm_engine *engine)
 	if (fifo->func->dtor)
 		data = fifo->func->dtor(fifo);
 	nvkm_event_fini(&fifo->kevent);
-	nvkm_event_fini(&fifo->cevent);
 	nvkm_event_fini(&fifo->uevent);
 	mutex_destroy(&fifo->mutex);
 	return data;
@@ -378,9 +353,5 @@ nvkm_fifo_ctor(const struct nvkm_fifo_func *func, struct nvkm_device *device,
 			return ret;
 	}
 
-	ret = nvkm_event_init(&nvkm_fifo_cevent_func, 1, 1, &fifo->cevent);
-	if (ret)
-		return ret;
-
 	return nvkm_event_init(&nvkm_fifo_kevent_func, 1, nr, &fifo->kevent);
 }
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
index 8d957643940ae..4ddaa91ad409b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
@@ -424,7 +424,5 @@ nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *func,
 	chan->addr = device->func->resource_addr(device, bar) +
 		     base + user * chan->chid;
 	chan->size = user;
-
-	nvkm_fifo_cevent(fifo);
 	return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h
index 899272801a8bf..79cec57647f02 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h
@@ -7,7 +7,6 @@
 int nvkm_fifo_ctor(const struct nvkm_fifo_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
 		   int nr, struct nvkm_fifo *);
 void nvkm_fifo_uevent(struct nvkm_fifo *);
-void nvkm_fifo_cevent(struct nvkm_fifo *);
 void nvkm_fifo_kevent(struct nvkm_fifo *, int chid);
 void nvkm_fifo_recover_chan(struct nvkm_fifo *, int chid);
 
-- 
GitLab


From 097d56cdcd77639bce7e205adaa22b6f5e7d93a6 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 1 Jun 2022 20:46:04 +1000
Subject: [PATCH 1727/1731] drm/nouveau/fifo: remove rd32/wr32 accessors from
 channels

No need for these, we always map USERD to the client.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 .../drm/nouveau/include/nvkm/engine/fifo.h    |  1 -
 drivers/gpu/drm/nouveau/nouveau_chan.c        |  4 ++-
 .../gpu/drm/nouveau/nvkm/engine/fifo/chan.c   | 35 -------------------
 3 files changed, 3 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
index 4d1a3bd558fd9..15099913504d5 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
@@ -26,7 +26,6 @@ struct nvkm_fifo_chan {
 	struct nvkm_gpuobj *inst;
 	struct nvkm_gpuobj *push;
 	struct nvkm_vmm *vmm;
-	void __iomem *user;
 	u64 addr;
 	u32 size;
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c
index ea7769135b0dc..48dea5d0c580f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_chan.c
+++ b/drivers/gpu/drm/nouveau/nouveau_chan.c
@@ -385,7 +385,9 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
 	struct nv_dma_v0 args = {};
 	int ret, i;
 
-	nvif_object_map(&chan->user, NULL, 0);
+	ret = nvif_object_map(&chan->user, NULL, 0);
+	if (ret)
+		return ret;
 
 	if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO &&
 	    chan->user.oclass < AMPERE_CHANNEL_GPFIFO_B) {
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
index 4ddaa91ad409b..2e7f32cebf2a1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
@@ -271,36 +271,6 @@ nvkm_fifo_chan_map(struct nvkm_object *object, void *argv, u32 argc,
 	return 0;
 }
 
-static int
-nvkm_fifo_chan_rd32(struct nvkm_object *object, u64 addr, u32 *data)
-{
-	struct nvkm_fifo_chan *chan = nvkm_fifo_chan(object);
-	if (unlikely(!chan->user)) {
-		chan->user = ioremap(chan->addr, chan->size);
-		if (!chan->user)
-			return -ENOMEM;
-	}
-	if (unlikely(addr + 4 > chan->size))
-		return -EINVAL;
-	*data = ioread32_native(chan->user + addr);
-	return 0;
-}
-
-static int
-nvkm_fifo_chan_wr32(struct nvkm_object *object, u64 addr, u32 data)
-{
-	struct nvkm_fifo_chan *chan = nvkm_fifo_chan(object);
-	if (unlikely(!chan->user)) {
-		chan->user = ioremap(chan->addr, chan->size);
-		if (!chan->user)
-			return -ENOMEM;
-	}
-	if (unlikely(addr + 4 > chan->size))
-		return -EINVAL;
-	iowrite32_native(data, chan->user + addr);
-	return 0;
-}
-
 static int
 nvkm_fifo_chan_fini(struct nvkm_object *object, bool suspend)
 {
@@ -332,9 +302,6 @@ nvkm_fifo_chan_dtor(struct nvkm_object *object)
 	}
 	spin_unlock_irqrestore(&fifo->lock, flags);
 
-	if (chan->user)
-		iounmap(chan->user);
-
 	if (chan->vmm) {
 		nvkm_vmm_part(chan->vmm, chan->inst->memory);
 		nvkm_vmm_unref(&chan->vmm);
@@ -352,8 +319,6 @@ nvkm_fifo_chan_func = {
 	.fini = nvkm_fifo_chan_fini,
 	.ntfy = nvkm_fifo_chan_ntfy,
 	.map = nvkm_fifo_chan_map,
-	.rd32 = nvkm_fifo_chan_rd32,
-	.wr32 = nvkm_fifo_chan_wr32,
 	.sclass = nvkm_fifo_chan_child_get,
 };
 
-- 
GitLab


From 40184ece92ebc5adfdba84554bffb60ef0e37029 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 1 Jun 2022 20:46:04 +1000
Subject: [PATCH 1728/1731] drm/nouveau/ce/gv100-: move method buffer to ce ctx

Didn't really know what this buffer was when initially implemented,
but these days we do, so move it somewhere more appropriate.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/nouveau/nouveau_abi16.c       | 26 ++++++++++
 drivers/gpu/drm/nouveau/nouveau_abi16.h       |  1 +
 .../gpu/drm/nouveau/nvkm/engine/ce/gv100.c    | 24 ++++++++++
 drivers/gpu/drm/nouveau/nvkm/engine/ce/priv.h |  2 +
 .../gpu/drm/nouveau/nvkm/engine/ce/tu102.c    |  1 +
 .../drm/nouveau/nvkm/engine/fifo/changk104.h  |  2 -
 .../nouveau/nvkm/engine/fifo/gpfifogk104.c    | 11 +++--
 .../nouveau/nvkm/engine/fifo/gpfifogv100.c    | 47 +++++++++----------
 8 files changed, 85 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c
index 4107b70065398..2278b9243efe7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_abi16.c
+++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c
@@ -147,6 +147,7 @@ nouveau_abi16_chan_fini(struct nouveau_abi16 *abi16,
 
 	/* destroy channel object, all children will be killed too */
 	if (chan->chan) {
+		nvif_object_dtor(&chan->ce);
 		nouveau_channel_idle(chan->chan);
 		nouveau_channel_del(&chan->chan);
 	}
@@ -325,6 +326,31 @@ nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS)
 		init->nr_subchan = 2;
 	}
 
+	/* Workaround "nvc0" gallium driver using classes it doesn't allocate on
+	 * Kepler and above.  NVKM no longer always sets CE_CTX_VALID as part of
+	 * channel init, now we know what that stuff actually is.
+	 *
+	 * Doesn't matter for Kepler/Pascal, CE context stored in NV_RAMIN.
+	 *
+	 * Userspace was fixed prior to adding Ampere support.
+	 */
+	switch (device->info.family) {
+	case NV_DEVICE_INFO_V0_VOLTA:
+		ret = nvif_object_ctor(&chan->chan->user, "abi16CeWar", 0, VOLTA_DMA_COPY_A,
+				       NULL, 0, &chan->ce);
+		if (ret)
+			goto done;
+		break;
+	case NV_DEVICE_INFO_V0_TURING:
+		ret = nvif_object_ctor(&chan->chan->user, "abi16CeWar", 0, TURING_DMA_COPY_A,
+				       NULL, 0, &chan->ce);
+		if (ret)
+			goto done;
+		break;
+	default:
+		break;
+	}
+
 	/* Named memory object area */
 	ret = nouveau_gem_new(cli, PAGE_SIZE, 0, NOUVEAU_GEM_DOMAIN_GART,
 			      0, 0, &chan->ntfy);
diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.h b/drivers/gpu/drm/nouveau/nouveau_abi16.h
index 70f6aa5c9dd16..27eae85f33e61 100644
--- a/drivers/gpu/drm/nouveau/nouveau_abi16.h
+++ b/drivers/gpu/drm/nouveau/nouveau_abi16.h
@@ -21,6 +21,7 @@ struct nouveau_abi16_ntfy {
 struct nouveau_abi16_chan {
 	struct list_head head;
 	struct nouveau_channel *chan;
+	struct nvif_object ce;
 	struct list_head notifiers;
 	struct nouveau_bo *ntfy;
 	struct nouveau_vma *ntfy_vma;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.c
index cd5e9cdca1cf9..44021d1395d39 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.c
@@ -21,11 +21,35 @@
  */
 #include "priv.h"
 
+#include <core/gpuobj.h>
+#include <core/object.h>
+
 #include <nvif/class.h>
 
+static int
+gv100_ce_cclass_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, int align,
+		     struct nvkm_gpuobj **pgpuobj)
+{
+	struct nvkm_device *device = object->engine->subdev.device;
+	u32 size;
+
+	/* Allocate fault method buffer (magics come from nvgpu). */
+	size = nvkm_rd32(device, 0x104028); /* NV_PCE_PCE_MAP */
+	size = 27 * 5 * (((9 + 1 + 3) * hweight32(size)) + 2);
+	size = roundup(size, PAGE_SIZE);
+
+	return nvkm_gpuobj_new(device, size, align, true, parent, pgpuobj);
+}
+
+const struct nvkm_object_func
+gv100_ce_cclass = {
+	.bind = gv100_ce_cclass_bind,
+};
+
 static const struct nvkm_engine_func
 gv100_ce = {
 	.intr = gp100_ce_intr,
+	.cclass = &gv100_ce_cclass,
 	.sclass = {
 		{ -1, -1, VOLTA_DMA_COPY_A },
 		{}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/ce/priv.h
index b0c8342db15fd..cd53b93664d64 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/priv.h
@@ -6,4 +6,6 @@
 void gt215_ce_intr(struct nvkm_falcon *, struct nvkm_fifo_chan *);
 void gk104_ce_intr(struct nvkm_engine *);
 void gp100_ce_intr(struct nvkm_engine *);
+
+extern const struct nvkm_object_func gv100_ce_cclass;
 #endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.c
index e5ff92d9364cb..9563c0175142f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.c
@@ -26,6 +26,7 @@
 static const struct nvkm_engine_func
 tu102_ce = {
 	.intr = gp100_ce_intr,
+	.cclass = &gv100_ce_cclass,
 	.sclass = {
 		{ -1, -1, TURING_DMA_COPY_A },
 		{}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h
index cfbe096e604f5..9713daee6c766 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h
@@ -14,8 +14,6 @@ struct gk104_fifo_chan {
 	struct list_head head;
 	bool killed;
 
-	struct nvkm_memory *mthd;
-
 #define GK104_FIFO_ENGN_SW 15
 	struct gk104_fifo_engn {
 		struct nvkm_gpuobj *inst;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
index ae6c4d846eb59..80456ec70e8a0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
@@ -175,13 +175,19 @@ gk104_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base,
 	struct gk104_fifo_engn *engn = gk104_fifo_gpfifo_engine(chan, engine);
 	int ret;
 
-	if (!gk104_fifo_gpfifo_engine_addr(engine))
-		return 0;
+	if (!gk104_fifo_gpfifo_engine_addr(engine)) {
+		if (engine->subdev.type != NVKM_ENGINE_CE ||
+		    engine->subdev.device->card_type < GV100)
+			return 0;
+	}
 
 	ret = nvkm_object_bind(object, NULL, 0, &engn->inst);
 	if (ret)
 		return ret;
 
+	if (!gk104_fifo_gpfifo_engine_addr(engine))
+		return 0;
+
 	ret = nvkm_vmm_get(chan->base.vmm, 12, engn->inst->size, &engn->vma);
 	if (ret)
 		return ret;
@@ -231,7 +237,6 @@ void *
 gk104_fifo_gpfifo_dtor(struct nvkm_fifo_chan *base)
 {
 	struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
-	nvkm_memory_unref(&chan->mthd);
 	kfree(chan->cgrp);
 	return chan;
 }
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c
index 743791c514fef..428f9b41165c9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c
@@ -70,8 +70,17 @@ gv100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base,
 	struct nvkm_gpuobj *inst = chan->base.inst;
 	int ret;
 
-	if (engine->subdev.type == NVKM_ENGINE_CE)
-		return gk104_fifo_gpfifo_kick(chan);
+	if (engine->subdev.type == NVKM_ENGINE_CE) {
+		ret = gv100_fifo_gpfifo_engine_valid(chan, true, false);
+		if (ret && suspend)
+			return ret;
+
+		nvkm_kmap(inst);
+		nvkm_wo32(chan->base.inst, 0x220, 0x00000000);
+		nvkm_wo32(chan->base.inst, 0x224, 0x00000000);
+		nvkm_done(inst);
+		return ret;
+	}
 
 	ret = gv100_fifo_gpfifo_engine_valid(chan, false, false);
 	if (ret && suspend)
@@ -92,8 +101,16 @@ gv100_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base,
 	struct gk104_fifo_engn *engn = gk104_fifo_gpfifo_engine(chan, engine);
 	struct nvkm_gpuobj *inst = chan->base.inst;
 
-	if (engine->subdev.type == NVKM_ENGINE_CE)
-		return 0;
+	if (engine->subdev.type == NVKM_ENGINE_CE) {
+		const u64 bar2 = nvkm_memory_bar2(engn->inst->memory);
+
+		nvkm_kmap(inst);
+		nvkm_wo32(chan->base.inst, 0x220, lower_32_bits(bar2));
+		nvkm_wo32(chan->base.inst, 0x224, upper_32_bits(bar2));
+		nvkm_done(inst);
+
+		return gv100_fifo_gpfifo_engine_valid(chan, true, true);
+	}
 
 	nvkm_kmap(inst);
 	nvkm_wo32(inst, 0x210, lower_32_bits(engn->vma->addr) | 0x00000004);
@@ -123,11 +140,9 @@ gv100_fifo_gpfifo_new_(const struct nvkm_fifo_chan_func *func,
 		       u32 *token, const struct nvkm_oclass *oclass,
 		       struct nvkm_object **pobject)
 {
-	struct nvkm_device *device = fifo->base.engine.subdev.device;
 	struct gk104_fifo_chan *chan;
 	int runlist = ffs(*runlists) -1, ret, i;
-	u64 usermem, mthd;
-	u32 size;
+	u64 usermem;
 
 	if (!vmm || runlist < 0 || runlist >= fifo->runlist_nr)
 		return -EINVAL;
@@ -173,20 +188,6 @@ gv100_fifo_gpfifo_new_(const struct nvkm_fifo_chan_func *func,
 	nvkm_done(fifo->user.mem);
 	usermem = nvkm_memory_addr(fifo->user.mem) + usermem;
 
-	/* Allocate fault method buffer (magics come from nvgpu). */
-	size = nvkm_rd32(device, 0x104028); /* NV_PCE_PCE_MAP */
-	size = 27 * 5 * (((9 + 1 + 3) * hweight32(size)) + 2);
-	size = roundup(size, PAGE_SIZE);
-
-	ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, size, 0x1000, true,
-			      &chan->mthd);
-	if (ret)
-		return ret;
-
-	mthd = nvkm_memory_bar2(chan->mthd);
-	if (mthd == ~0ULL)
-		return -EFAULT;
-
 	/* RAMFC */
 	nvkm_kmap(chan->base.inst);
 	nvkm_wo32(chan->base.inst, 0x008, lower_32_bits(usermem));
@@ -203,10 +204,8 @@ gv100_fifo_gpfifo_new_(const struct nvkm_fifo_chan_func *func,
 	nvkm_wo32(chan->base.inst, 0x0f4, 0x00001000);
 	nvkm_wo32(chan->base.inst, 0x0f8, 0x10003080);
 	nvkm_mo32(chan->base.inst, 0x218, 0x00000000, 0x00000000);
-	nvkm_wo32(chan->base.inst, 0x220, lower_32_bits(mthd));
-	nvkm_wo32(chan->base.inst, 0x224, upper_32_bits(mthd));
 	nvkm_done(chan->base.inst);
-	return gv100_fifo_gpfifo_engine_valid(chan, true, true);
+	return 0;
 }
 
 int
-- 
GitLab


From 7ba01b504c16ae64a8faa5f5ee9a809d424cdf0e Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 1 Jun 2022 20:46:05 +1000
Subject: [PATCH 1729/1731] drm/nouveau: remove double WFI when destroying
 channels

This is particularly irritating when the channel has hung.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/nouveau/nouveau_abi16.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c
index 2278b9243efe7..5bee655e7e63e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_abi16.c
+++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c
@@ -126,9 +126,8 @@ nouveau_abi16_chan_fini(struct nouveau_abi16 *abi16,
 {
 	struct nouveau_abi16_ntfy *ntfy, *temp;
 
-	/* wait for all activity to stop before releasing notify object, which
-	 * may be still in use */
-	if (chan->chan && chan->ntfy)
+	/* wait for all activity to stop before cleaning up */
+	if (chan->chan)
 		nouveau_channel_idle(chan->chan);
 
 	/* cleanup notifier state */
@@ -148,7 +147,6 @@ nouveau_abi16_chan_fini(struct nouveau_abi16 *abi16,
 	/* destroy channel object, all children will be killed too */
 	if (chan->chan) {
 		nvif_object_dtor(&chan->ce);
-		nouveau_channel_idle(chan->chan);
 		nouveau_channel_del(&chan->chan);
 	}
 
-- 
GitLab


From ea0b20d3bd96f9ce2a1e9d886175411c05dcb179 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 1 Jun 2022 20:46:05 +1000
Subject: [PATCH 1730/1731] drm/nouveau/flcn: remove unused functions

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 .../drm/nouveau/include/nvkm/engine/falcon.h  | 10 --------
 drivers/gpu/drm/nouveau/nvkm/falcon/base.c    | 10 --------
 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c      | 25 -------------------
 3 files changed, 45 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
index 306125d17eced..b593407b9e36f 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
@@ -4,7 +4,6 @@
 #define nvkm_falcon(p) container_of((p), struct nvkm_falcon, engine)
 #include <core/engine.h>
 struct nvkm_fifo_chan;
-struct nvkm_gpuobj;
 
 enum nvkm_falcon_dmaidx {
 	FALCON_DMAIDX_UCODE		= 0,
@@ -51,15 +50,6 @@ struct nvkm_falcon {
 	struct nvkm_engine engine;
 };
 
-/* This constructor must be called from the owner's oneinit() hook and
- * *not* its constructor.  This is to ensure that DEVINIT has been
- * completed, and that the device is correctly enabled before we touch
- * falcon registers.
- */
-int nvkm_falcon_v1_new(struct nvkm_subdev *owner, const char *name, u32 addr,
-		       struct nvkm_falcon **);
-
-void nvkm_falcon_del(struct nvkm_falcon **);
 int nvkm_falcon_get(struct nvkm_falcon *, const struct nvkm_subdev *);
 void nvkm_falcon_put(struct nvkm_falcon *, const struct nvkm_subdev *);
 
diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/base.c b/drivers/gpu/drm/nouveau/nvkm/falcon/base.c
index c91130a6be2a1..f3f90c1063dd0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/falcon/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/falcon/base.c
@@ -221,13 +221,3 @@ nvkm_falcon_ctor(const struct nvkm_falcon_func *func,
 	mutex_init(&falcon->dmem_mutex);
 	return 0;
 }
-
-void
-nvkm_falcon_del(struct nvkm_falcon **pfalcon)
-{
-	if (*pfalcon) {
-		nvkm_falcon_dtor(*pfalcon);
-		kfree(*pfalcon);
-		*pfalcon = NULL;
-	}
-}
diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/v1.c b/drivers/gpu/drm/nouveau/nvkm/falcon/v1.c
index 1ff9b9c2e651f..b0ee4c31414c8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/falcon/v1.c
+++ b/drivers/gpu/drm/nouveau/nvkm/falcon/v1.c
@@ -309,28 +309,3 @@ nvkm_falcon_v1_disable(struct nvkm_falcon *falcon)
 	nvkm_falcon_wr32(falcon, 0x014, 0xff);
 	falcon_v1_wait_idle(falcon);
 }
-
-static const struct nvkm_falcon_func
-nvkm_falcon_v1 = {
-	.load_imem = nvkm_falcon_v1_load_imem,
-	.load_dmem = nvkm_falcon_v1_load_dmem,
-	.read_dmem = nvkm_falcon_v1_read_dmem,
-	.bind_context = nvkm_falcon_v1_bind_context,
-	.start = nvkm_falcon_v1_start,
-	.wait_for_halt = nvkm_falcon_v1_wait_for_halt,
-	.clear_interrupt = nvkm_falcon_v1_clear_interrupt,
-	.enable = nvkm_falcon_v1_enable,
-	.disable = nvkm_falcon_v1_disable,
-	.set_start_addr = nvkm_falcon_v1_set_start_addr,
-};
-
-int
-nvkm_falcon_v1_new(struct nvkm_subdev *owner, const char *name, u32 addr,
-		   struct nvkm_falcon **pfalcon)
-{
-	struct nvkm_falcon *falcon;
-	if (!(falcon = *pfalcon = kzalloc(sizeof(*falcon), GFP_KERNEL)))
-		return -ENOMEM;
-	nvkm_falcon_ctor(&nvkm_falcon_v1, owner, name, addr, falcon);
-	return 0;
-}
-- 
GitLab


From 89ed996b888faaf11c69bb4cbc19f21475c9050e Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 1 Jun 2022 20:46:06 +1000
Subject: [PATCH 1731/1731] drm/nouveau/kms/nv50-: remove unused functions

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/nouveau/dispnv50/disp.c | 16 ----------------
 drivers/gpu/drm/nouveau/dispnv50/wndw.c | 12 ------------
 drivers/gpu/drm/nouveau/dispnv50/wndw.h |  2 --
 3 files changed, 30 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index 4347f0b61797a..ade2988e85f36 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -2623,14 +2623,6 @@ nv50_display_fini(struct drm_device *dev, bool runtime, bool suspend)
 {
 	struct nouveau_drm *drm = nouveau_drm(dev);
 	struct drm_encoder *encoder;
-	struct drm_plane *plane;
-
-	drm_for_each_plane(plane, dev) {
-		struct nv50_wndw *wndw = nv50_wndw(plane);
-		if (plane->funcs != &nv50_wndw)
-			continue;
-		nv50_wndw_fini(wndw);
-	}
 
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 		if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
@@ -2646,7 +2638,6 @@ nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
 {
 	struct nv50_core *core = nv50_disp(dev)->core;
 	struct drm_encoder *encoder;
-	struct drm_plane *plane;
 
 	if (resume || runtime)
 		core->func->init(core);
@@ -2659,13 +2650,6 @@ nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
 		}
 	}
 
-	drm_for_each_plane(plane, dev) {
-		struct nv50_wndw *wndw = nv50_wndw(plane);
-		if (plane->funcs != &nv50_wndw)
-			continue;
-		nv50_wndw_init(wndw);
-	}
-
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c
index ef21cfa2b28e7..b21f49f0eae5d 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c
@@ -694,18 +694,6 @@ nv50_wndw_notify(struct nvif_notify *notify)
 	return NVIF_NOTIFY_KEEP;
 }
 
-void
-nv50_wndw_fini(struct nv50_wndw *wndw)
-{
-	nvif_notify_put(&wndw->notify);
-}
-
-void
-nv50_wndw_init(struct nv50_wndw *wndw)
-{
-	nvif_notify_get(&wndw->notify);
-}
-
 static const u64 nv50_cursor_format_modifiers[] = {
 	DRM_FORMAT_MOD_LINEAR,
 	DRM_FORMAT_MOD_INVALID,
diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h
index 9c9f2c2a71a50..96542ce666fce 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h
+++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h
@@ -40,8 +40,6 @@ int nv50_wndw_new_(const struct nv50_wndw_func *, struct drm_device *,
 		   enum drm_plane_type, const char *name, int index,
 		   const u32 *format, enum nv50_disp_interlock_type,
 		   u32 interlock_data, u32 heads, struct nv50_wndw **);
-void nv50_wndw_init(struct nv50_wndw *);
-void nv50_wndw_fini(struct nv50_wndw *);
 void nv50_wndw_flush_set(struct nv50_wndw *, u32 *interlock,
 			 struct nv50_wndw_atom *);
 void nv50_wndw_flush_clr(struct nv50_wndw *, u32 *interlock, bool flush,
-- 
GitLab